From 4c2983fdf23522ace0044770db41093d9cc5904b Mon Sep 17 00:00:00 2001 From: Vladimir Umek Date: Thu, 7 Mar 2024 14:43:54 +0100 Subject: [PATCH] Update FreeRTOS-Kernel to v11.0.1 (#87) --- ARM.CMSIS-FreeRTOS.pdsc | 10 +- Source/CMakeLists.txt | 69 +- Source/History.txt | 98 +- Source/MISRA.md | 118 + Source/README.md | 104 +- Source/croutine.c | 33 +- Source/cspell.config.yaml | 31 + Source/event_groups.c | 141 +- Source/examples/cmake_example/CMakeLists.txt | 73 + Source/examples/cmake_example/main.c | 92 + Source/examples/coverity/CMakeLists.txt | 39 + Source/examples/coverity/FreeRTOSConfig.h | 135 + Source/examples/coverity/README.md | 58 + .../examples/coverity/coverity_misra.config | 97 + .../template_configuration/FreeRTOSConfig.h | 568 + .../examples/template_configuration/readme.md | 7 + Source/include/FreeRTOS.h | 2135 ++- Source/include/StackMacros.h | 2 +- Source/include/atomic.h | 2 +- Source/include/croutine.h | 6 +- Source/include/deprecated_definitions.h | 2 +- Source/include/event_groups.h | 30 +- Source/include/list.h | 4 +- Source/include/message_buffer.h | 2 +- Source/include/mpu_prototypes.h | 31 +- Source/include/mpu_syscall_numbers.h | 117 +- Source/include/mpu_wrappers.h | 17 +- Source/include/newlib-freertos.h | 2 +- Source/include/picolibc-freertos.h | 23 +- Source/include/portable.h | 4 +- Source/include/projdefs.h | 13 +- Source/include/queue.h | 136 +- Source/include/semphr.h | 5 +- Source/include/stack_macros.h | 62 +- Source/include/stdint.readme | 2 +- Source/include/stream_buffer.h | 19 +- Source/include/task.h | 644 +- Source/include/timers.h | 66 +- Source/list.c | 41 +- Source/manifest.yml | 2 +- Source/portable/ARMv8M/ReadMe.txt | 2 +- Source/portable/ARMv8M/copy_files.py | 2 +- Source/portable/ARMv8M/non_secure/port.c | 335 +- .../GCC/ARM_CM23/mpu_wrappers_v2_asm.c | 67 +- .../portable/GCC/ARM_CM23/portasm.c | 12 +- .../portable/GCC/ARM_CM23/portmacro.h | 8 +- .../GCC/ARM_CM23_NTZ/mpu_wrappers_v2_asm.c | 67 +- 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Source/portable/GCC/Arm_AARCH64_SRE/README.md | 23 + .../port.c | 269 +- .../portASM.S | 2 +- .../portable/GCC/Arm_AARCH64_SRE/portmacro.h | 200 + Source/portable/GCC/CORTUS_APS3/port.c | 16 +- Source/portable/GCC/CORTUS_APS3/portmacro.h | 128 +- Source/portable/GCC/ColdFire_V2/port.c | 32 +- Source/portable/GCC/ColdFire_V2/portasm.S | 2 +- Source/portable/GCC/ColdFire_V2/portmacro.h | 72 +- Source/portable/GCC/H8S2329/port.c | 95 +- Source/portable/GCC/H8S2329/portmacro.h | 115 +- Source/portable/GCC/HCS12/port.c | 84 +- Source/portable/GCC/HCS12/portmacro.h | 171 +- Source/portable/GCC/IA32_flat/ISR_Support.h | 147 +- Source/portable/GCC/IA32_flat/port.c | 245 +- Source/portable/GCC/IA32_flat/portASM.S | 2 +- Source/portable/GCC/IA32_flat/portmacro.h | 263 +- Source/portable/GCC/MSP430F449/port.c | 209 +- Source/portable/GCC/MSP430F449/portmacro.h | 108 +- Source/portable/GCC/MicroBlaze/port.c | 174 +- Source/portable/GCC/MicroBlaze/portasm.s | 2 +- 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.../IAR/ARM_CM23_NTZ/non_secure/portasm.s | 22 +- .../IAR/ARM_CM23_NTZ/non_secure/portmacro.h | 8 +- .../ARM_CM23_NTZ/non_secure/portmacrocommon.h | 205 +- Source/portable/IAR/ARM_CM3/port.c | 95 +- Source/portable/IAR/ARM_CM3/portasm.s | 2 +- Source/portable/IAR/ARM_CM3/portmacro.h | 186 +- .../ARM_CM33/non_secure/mpu_wrappers_v2_asm.S | 46 +- .../portable/IAR/ARM_CM33/non_secure/port.c | 335 +- .../IAR/ARM_CM33/non_secure/portasm.h | 2 +- .../IAR/ARM_CM33/non_secure/portasm.s | 2 +- .../IAR/ARM_CM33/non_secure/portmacro.h | 14 +- .../IAR/ARM_CM33/non_secure/portmacrocommon.h | 205 +- .../IAR/ARM_CM33/secure/secure_context.c | 87 +- .../IAR/ARM_CM33/secure/secure_context.h | 15 +- .../ARM_CM33/secure/secure_context_port_asm.s | 2 +- .../IAR/ARM_CM33/secure/secure_heap.c | 98 +- .../IAR/ARM_CM33/secure/secure_heap.h | 2 +- .../IAR/ARM_CM33/secure/secure_init.c | 4 +- .../IAR/ARM_CM33/secure/secure_init.h | 2 +- .../IAR/ARM_CM33/secure/secure_port_macros.h | 2 +- .../non_secure/mpu_wrappers_v2_asm.S | 46 +- .../IAR/ARM_CM33_NTZ/non_secure/port.c | 335 +- .../IAR/ARM_CM33_NTZ/non_secure/portasm.h | 2 +- .../IAR/ARM_CM33_NTZ/non_secure/portasm.s | 2 +- .../IAR/ARM_CM33_NTZ/non_secure/portmacro.h | 14 +- .../ARM_CM33_NTZ/non_secure/portmacrocommon.h | 205 +- .../non_secure/mpu_wrappers_v2_asm.S | 46 +- .../portable/IAR/ARM_CM35P/non_secure/port.c | 335 +- .../IAR/ARM_CM35P/non_secure/portasm.h | 2 +- .../IAR/ARM_CM35P/non_secure/portasm.s | 2 +- .../IAR/ARM_CM35P/non_secure/portmacro.h | 14 +- .../ARM_CM35P/non_secure/portmacrocommon.h | 205 +- .../IAR/ARM_CM35P/secure/secure_context.c | 87 +- .../IAR/ARM_CM35P/secure/secure_context.h | 15 +- .../secure/secure_context_port_asm.s | 2 +- .../IAR/ARM_CM35P/secure/secure_heap.c | 98 +- .../IAR/ARM_CM35P/secure/secure_heap.h | 2 +- .../IAR/ARM_CM35P/secure/secure_init.c | 4 +- .../IAR/ARM_CM35P/secure/secure_init.h | 2 +- .../IAR/ARM_CM35P/secure/secure_port_macros.h | 2 +- .../non_secure/mpu_wrappers_v2_asm.S | 46 +- .../IAR/ARM_CM35P_NTZ/non_secure/port.c | 335 +- .../IAR/ARM_CM35P_NTZ/non_secure/portasm.h | 2 +- .../IAR/ARM_CM35P_NTZ/non_secure/portasm.s | 2 +- .../IAR/ARM_CM35P_NTZ/non_secure/portmacro.h | 14 +- .../non_secure/portmacrocommon.h | 205 +- Source/portable/IAR/ARM_CM4F/port.c | 95 +- Source/portable/IAR/ARM_CM4F/portasm.s | 2 +- Source/portable/IAR/ARM_CM4F/portmacro.h | 186 +- .../IAR/ARM_CM4F_MPU/mpu_wrappers_v2_asm.S | 46 +- Source/portable/IAR/ARM_CM4F_MPU/port.c | 157 +- Source/portable/IAR/ARM_CM4F_MPU/portasm.s | 24 +- Source/portable/IAR/ARM_CM4F_MPU/portmacro.h | 94 +- .../ARM_CM55/non_secure/mpu_wrappers_v2_asm.S | 46 +- .../portable/IAR/ARM_CM55/non_secure/port.c | 335 +- .../IAR/ARM_CM55/non_secure/portasm.h | 2 +- .../IAR/ARM_CM55/non_secure/portasm.s | 2 +- .../IAR/ARM_CM55/non_secure/portmacro.h | 14 +- .../IAR/ARM_CM55/non_secure/portmacrocommon.h | 205 +- .../IAR/ARM_CM55/secure/secure_context.c | 87 +- .../IAR/ARM_CM55/secure/secure_context.h | 15 +- .../ARM_CM55/secure/secure_context_port_asm.s | 2 +- .../IAR/ARM_CM55/secure/secure_heap.c | 98 +- .../IAR/ARM_CM55/secure/secure_heap.h | 2 +- .../IAR/ARM_CM55/secure/secure_init.c | 4 +- .../IAR/ARM_CM55/secure/secure_init.h | 2 +- .../IAR/ARM_CM55/secure/secure_port_macros.h | 2 +- .../non_secure/mpu_wrappers_v2_asm.S | 46 +- .../IAR/ARM_CM55_NTZ/non_secure/port.c | 335 +- .../IAR/ARM_CM55_NTZ/non_secure/portasm.h | 2 +- .../IAR/ARM_CM55_NTZ/non_secure/portasm.s | 2 +- .../IAR/ARM_CM55_NTZ/non_secure/portmacro.h | 14 +- .../ARM_CM55_NTZ/non_secure/portmacrocommon.h | 205 +- Source/portable/IAR/ARM_CM7/r0p1/port.c | 95 +- Source/portable/IAR/ARM_CM7/r0p1/portasm.s | 2 +- Source/portable/IAR/ARM_CM7/r0p1/portmacro.h | 186 +- .../ARM_CM85/non_secure/mpu_wrappers_v2_asm.S | 46 +- .../portable/IAR/ARM_CM85/non_secure/port.c | 335 +- .../IAR/ARM_CM85/non_secure/portasm.h | 2 +- .../IAR/ARM_CM85/non_secure/portasm.s | 2 +- .../IAR/ARM_CM85/non_secure/portmacro.h | 14 +- .../IAR/ARM_CM85/non_secure/portmacrocommon.h | 205 +- .../IAR/ARM_CM85/secure/secure_context.c | 87 +- .../IAR/ARM_CM85/secure/secure_context.h | 15 +- .../ARM_CM85/secure/secure_context_port_asm.s | 2 +- .../IAR/ARM_CM85/secure/secure_heap.c | 98 +- .../IAR/ARM_CM85/secure/secure_heap.h | 2 +- .../IAR/ARM_CM85/secure/secure_init.c | 4 +- .../IAR/ARM_CM85/secure/secure_init.h | 2 +- .../IAR/ARM_CM85/secure/secure_port_macros.h | 2 +- .../non_secure/mpu_wrappers_v2_asm.S | 46 +- .../IAR/ARM_CM85_NTZ/non_secure/port.c | 335 +- .../IAR/ARM_CM85_NTZ/non_secure/portasm.h | 2 +- .../IAR/ARM_CM85_NTZ/non_secure/portasm.s | 2 +- .../IAR/ARM_CM85_NTZ/non_secure/portmacro.h | 14 +- .../ARM_CM85_NTZ/non_secure/portmacrocommon.h | 205 +- Source/portable/IAR/ARM_CRx_No_GIC/port.c | 156 +- Source/portable/IAR/ARM_CRx_No_GIC/portASM.s | 2 +- .../portable/IAR/ARM_CRx_No_GIC/portmacro.h | 127 +- Source/portable/IAR/ATMega323/port.c | 170 +- Source/portable/IAR/ATMega323/portmacro.h | 72 +- Source/portable/IAR/ATMega323/portmacro.s90 | 2 +- Source/portable/IAR/AVR32_UC3/exception.s82 | 2 +- Source/portable/IAR/AVR32_UC3/port.c | 261 +- Source/portable/IAR/AVR32_UC3/portmacro.h | 900 +- Source/portable/IAR/AVR32_UC3/read.c | 78 +- Source/portable/IAR/AVR32_UC3/write.c | 81 +- Source/portable/IAR/AVR_AVRDx/port.c | 2 +- Source/portable/IAR/AVR_AVRDx/porthardware.h | 2 +- Source/portable/IAR/AVR_AVRDx/portmacro.h | 6 +- Source/portable/IAR/AVR_AVRDx/portmacro.s90 | 2 +- Source/portable/IAR/AVR_Mega0/port.c | 2 +- Source/portable/IAR/AVR_Mega0/porthardware.h | 2 +- Source/portable/IAR/AVR_Mega0/portmacro.h | 6 +- Source/portable/IAR/AVR_Mega0/portmacro.s90 | 2 +- .../portable/IAR/AtmelSAM7S64/AT91SAM7S64.h | 3742 +++--- .../IAR/AtmelSAM7S64/AT91SAM7S64_inc.h | 3564 ++--- .../portable/IAR/AtmelSAM7S64/AT91SAM7X128.h | 5450 ++++---- .../IAR/AtmelSAM7S64/AT91SAM7X128_inc.h | 4820 +++---- .../portable/IAR/AtmelSAM7S64/AT91SAM7X256.h | 5450 ++++---- .../IAR/AtmelSAM7S64/AT91SAM7X256_inc.h | 4820 +++---- .../portable/IAR/AtmelSAM7S64/ISR_Support.h | 222 +- .../IAR/AtmelSAM7S64/lib_AT91SAM7S64.h | 4446 +++---- .../IAR/AtmelSAM7S64/lib_AT91SAM7X128.h | 2783 ++-- .../IAR/AtmelSAM7S64/lib_AT91SAM7X256.h | 2783 ++-- Source/portable/IAR/AtmelSAM7S64/port.c | 120 +- Source/portable/IAR/AtmelSAM7S64/portasm.s79 | 2 +- Source/portable/IAR/AtmelSAM7S64/portmacro.h | 69 +- Source/portable/IAR/AtmelSAM9XE/ISR_Support.h | 220 +- Source/portable/IAR/AtmelSAM9XE/port.c | 96 +- Source/portable/IAR/AtmelSAM9XE/portasm.s79 | 2 +- Source/portable/IAR/AtmelSAM9XE/portmacro.h | 75 +- Source/portable/IAR/LPC2000/ISR_Support.h | 222 +- Source/portable/IAR/LPC2000/port.c | 152 +- Source/portable/IAR/LPC2000/portasm.s79 | 2 +- Source/portable/IAR/LPC2000/portmacro.h | 75 +- Source/portable/IAR/MSP430/port.c | 67 +- Source/portable/IAR/MSP430/portasm.h | 88 +- Source/portable/IAR/MSP430/portext.s43 | 2 +- Source/portable/IAR/MSP430/portmacro.h | 118 +- Source/portable/IAR/MSP430X/data_model.h | 38 +- Source/portable/IAR/MSP430X/port.c | 73 +- Source/portable/IAR/MSP430X/portext.s43 | 2 +- Source/portable/IAR/MSP430X/portmacro.h | 118 +- .../portable/IAR/RISC-V/chip_extensions.cmake | 16 + ...freertos_risc_v_chip_specific_extensions.h | 14 +- Source/portable/IAR/RISC-V/port.c | 16 +- Source/portable/IAR/RISC-V/portASM.s | 2 +- Source/portable/IAR/RISC-V/portContext.h | 206 +- Source/portable/IAR/RISC-V/portmacro.h | 154 +- Source/portable/IAR/RL78/port.c | 79 +- Source/portable/IAR/RL78/portasm.s | 2 +- Source/portable/IAR/RL78/portmacro.h | 298 +- Source/portable/IAR/RX100/port.c | 185 +- Source/portable/IAR/RX100/port_asm.s | 2 +- Source/portable/IAR/RX100/portmacro.h | 100 +- Source/portable/IAR/RX600/port.c | 34 +- Source/portable/IAR/RX600/port_asm.s | 2 +- Source/portable/IAR/RX600/portmacro.h | 116 +- Source/portable/IAR/RX700v3_DPFPU/port.c | 403 +- Source/portable/IAR/RX700v3_DPFPU/portmacro.h | 151 +- Source/portable/IAR/RXv2/port.c | 34 +- Source/portable/IAR/RXv2/port_asm.s | 2 +- Source/portable/IAR/RXv2/portmacro.h | 120 +- Source/portable/IAR/STR71x/ISR_Support.h | 222 +- Source/portable/IAR/STR71x/port.c | 96 +- Source/portable/IAR/STR71x/portasm.s79 | 2 +- Source/portable/IAR/STR71x/portmacro.h | 81 +- Source/portable/IAR/STR75x/ISR_Support.h | 222 +- Source/portable/IAR/STR75x/port.c | 94 +- Source/portable/IAR/STR75x/portasm.s79 | 2 +- Source/portable/IAR/STR75x/portmacro.h | 75 +- Source/portable/IAR/STR91x/ISR_Support.h | 166 +- Source/portable/IAR/STR91x/port.c | 208 +- Source/portable/IAR/STR91x/portasm.s79 | 2 +- Source/portable/IAR/STR91x/portmacro.h | 75 +- Source/portable/IAR/V850ES/ISR_Support.h | 243 +- Source/portable/IAR/V850ES/port.c | 112 +- Source/portable/IAR/V850ES/portasm.s85 | 2 +- Source/portable/IAR/V850ES/portasm_Fx3.s85 | 2 +- Source/portable/IAR/V850ES/portasm_Hx2.s85 | 2 +- Source/portable/IAR/V850ES/portmacro.h | 102 +- Source/portable/MPLAB/PIC18F/port.c | 4 +- Source/portable/MPLAB/PIC18F/portmacro.h | 4 +- Source/portable/MPLAB/PIC24_dsPIC/port.c | 2 +- .../MPLAB/PIC24_dsPIC/portasm_PIC24.S | 2 +- .../MPLAB/PIC24_dsPIC/portasm_dsPIC.S | 2 +- Source/portable/MPLAB/PIC24_dsPIC/portmacro.h | 4 +- .../portable/MPLAB/PIC32MEC14xx/ISR_Support.h | 2 +- Source/portable/MPLAB/PIC32MEC14xx/port.c | 2 +- Source/portable/MPLAB/PIC32MEC14xx/port_asm.S | 2 +- .../portable/MPLAB/PIC32MEC14xx/portmacro.h | 16 +- Source/portable/MPLAB/PIC32MX/ISR_Support.h | 2 +- Source/portable/MPLAB/PIC32MX/port.c | 4 +- Source/portable/MPLAB/PIC32MX/port_asm.S | 2 +- Source/portable/MPLAB/PIC32MX/portmacro.h | 16 +- Source/portable/MPLAB/PIC32MZ/ISR_Support.h | 2 +- Source/portable/MPLAB/PIC32MZ/port.c | 4 +- Source/portable/MPLAB/PIC32MZ/port_asm.S | 2 +- Source/portable/MPLAB/PIC32MZ/portmacro.h | 16 +- Source/portable/MSVC-MingW/port.c | 452 +- Source/portable/MSVC-MingW/portmacro.h | 146 +- Source/portable/MemMang/heap_1.c | 2 +- Source/portable/MemMang/heap_2.c | 72 +- Source/portable/MemMang/heap_3.c | 2 +- Source/portable/MemMang/heap_4.c | 189 +- Source/portable/MemMang/heap_5.c | 227 +- Source/portable/MikroC/ARM_CM4F/port.c | 9 +- Source/portable/MikroC/ARM_CM4F/portmacro.h | 22 +- .../Paradigm/Tern_EE/large_untested/port.c | 2 +- .../Paradigm/Tern_EE/large_untested/portasm.h | 2 +- .../Tern_EE/large_untested/portmacro.h | 2 +- Source/portable/Paradigm/Tern_EE/small/port.c | 2 +- .../portable/Paradigm/Tern_EE/small/portasm.h | 2 +- .../Paradigm/Tern_EE/small/portmacro.h | 2 +- Source/portable/RVDS/ARM7_LPC21xx/port.c | 154 +- Source/portable/RVDS/ARM7_LPC21xx/portASM.s | 2 +- Source/portable/RVDS/ARM7_LPC21xx/portmacro.h | 96 +- .../portable/RVDS/ARM7_LPC21xx/portmacro.inc | 2 +- Source/portable/RVDS/ARM_CA9/port.c | 311 +- Source/portable/RVDS/ARM_CA9/portASM.s | 2 +- Source/portable/RVDS/ARM_CA9/portmacro.h | 124 +- Source/portable/RVDS/ARM_CA9/portmacro.inc | 2 +- Source/portable/RVDS/ARM_CM0/port.c | 8 +- Source/portable/RVDS/ARM_CM0/portmacro.h | 18 +- Source/portable/RVDS/ARM_CM3/port.c | 41 +- Source/portable/RVDS/ARM_CM3/portmacro.h | 244 +- Source/portable/RVDS/ARM_CM4F/port.c | 41 +- Source/portable/RVDS/ARM_CM4F/portmacro.h | 244 +- .../RVDS/ARM_CM4_MPU/mpu_wrappers_v2_asm.c | 41 +- Source/portable/RVDS/ARM_CM4_MPU/port.c | 204 +- Source/portable/RVDS/ARM_CM4_MPU/portmacro.h | 63 +- Source/portable/RVDS/ARM_CM7/r0p1/port.c | 41 +- Source/portable/RVDS/ARM_CM7/r0p1/portmacro.h | 244 +- Source/portable/Renesas/RX100/port.c | 2 +- Source/portable/Renesas/RX100/port_asm.src | 2 +- Source/portable/Renesas/RX100/portmacro.h | 9 +- Source/portable/Renesas/RX200/port.c | 2 +- Source/portable/Renesas/RX200/port_asm.src | 2 +- Source/portable/Renesas/RX200/portmacro.h | 8 +- Source/portable/Renesas/RX600/port.c | 2 +- Source/portable/Renesas/RX600/port_asm.src | 2 +- Source/portable/Renesas/RX600/portmacro.h | 9 +- Source/portable/Renesas/RX600v2/port.c | 2 +- Source/portable/Renesas/RX600v2/port_asm.src | 2 +- Source/portable/Renesas/RX600v2/portmacro.h | 9 +- Source/portable/Renesas/RX700v3_DPFPU/port.c | 2 +- .../Renesas/RX700v3_DPFPU/port_asm.src | 2 +- .../Renesas/RX700v3_DPFPU/portmacro.h | 9 +- .../portable/Renesas/SH2A_FPU/ISR_Support.inc | 2 +- Source/portable/Renesas/SH2A_FPU/port.c | 72 +- Source/portable/Renesas/SH2A_FPU/portasm.src | 2 +- Source/portable/Renesas/SH2A_FPU/portmacro.h | 78 +- Source/portable/Rowley/MSP430F449/port.c | 2 +- Source/portable/Rowley/MSP430F449/portasm.h | 2 +- Source/portable/Rowley/MSP430F449/portext.asm | 2 +- Source/portable/Rowley/MSP430F449/portmacro.h | 2 +- Source/portable/SDCC/Cygnal/port.c | 2 +- Source/portable/SDCC/Cygnal/portmacro.h | 2 +- .../portable/Softune/MB91460/__STD_LIB_sbrk.c | 4 +- Source/portable/Softune/MB91460/port.c | 2 +- Source/portable/Softune/MB91460/portmacro.h | 2 +- .../portable/Softune/MB96340/__STD_LIB_sbrk.c | 4 +- Source/portable/Softune/MB96340/port.c | 16 +- Source/portable/Softune/MB96340/portmacro.h | 2 +- Source/portable/Tasking/ARM_CM4F/port.c | 8 +- Source/portable/Tasking/ARM_CM4F/port_asm.asm | 2 +- Source/portable/Tasking/ARM_CM4F/portmacro.h | 28 +- .../ThirdParty/CDK/T-HEAD_CK802/port.c | 113 +- .../ThirdParty/CDK/T-HEAD_CK802/portmacro.h | 126 +- .../CCS/C2000_C28x/README.md | 3 - .../CCS/C2000_C28x/port.c | 6 +- .../CCS/C2000_C28x/portasm.asm | 69 + .../GCC/TriCore_38xa/portmacro.h | 8 +- .../Community-Supported-Ports/README.md | 9 +- .../Z88DK/Z180/port.c | 72 +- .../Z88DK/Z180/portmacro.h | 243 +- .../Z88DK/Z180/readme.md | 8 +- .../GCC/ARC_EM_HS/arc_freertos_exceptions.c | 2 +- .../GCC/ARC_EM_HS/arc_freertos_exceptions.h | 2 +- .../ThirdParty/GCC/ARC_EM_HS/arc_support.s | 2 +- .../ThirdParty/GCC/ARC_EM_HS/freertos_tls.c | 2 +- .../portable/ThirdParty/GCC/ARC_EM_HS/port.c | 2 +- .../ThirdParty/GCC/ARC_EM_HS/portmacro.h | 16 +- .../GCC/ARC_v1/arc_freertos_exceptions.c | 2 +- .../GCC/ARC_v1/arc_freertos_exceptions.h | 2 +- .../ThirdParty/GCC/ARC_v1/arc_support.s | 2 +- Source/portable/ThirdParty/GCC/ARC_v1/port.c | 16 +- .../ThirdParty/GCC/ARC_v1/portmacro.h | 138 +- .../portable/ThirdParty/GCC/ARM_TFM/README.md | 2 +- .../GCC/ARM_TFM/os_wrapper_freertos.c | 44 +- Source/portable/ThirdParty/GCC/ATmega/port.c | 1003 +- .../ThirdParty/GCC/ATmega/portmacro.h | 104 +- Source/portable/ThirdParty/GCC/Posix/port.c | 41 +- .../portable/ThirdParty/GCC/Posix/portmacro.h | 98 +- .../GCC/Posix/utils/wait_for_event.c | 6 +- .../GCC/Posix/utils/wait_for_event.h | 8 +- .../portable/ThirdParty/GCC/RP2040/README.md | 23 +- .../GCC/RP2040/idle_task_static_memory.c | 18 +- .../GCC/RP2040/include/freertos_sdk_config.h | 42 +- .../ThirdParty/GCC/RP2040/include/portmacro.h | 272 +- .../GCC/RP2040/include/rp2040_config.h | 32 +- .../ThirdParty/GCC/RP2040/library.cmake | 7 +- Source/portable/ThirdParty/GCC/RP2040/port.c | 776 +- .../include/FreeRTOSConfig_arch.h | 89 +- .../GCC/Xtensa_ESP32/include/port_systick.h | 2 +- .../GCC/Xtensa_ESP32/include/portbenchmark.h | 1 + .../GCC/Xtensa_ESP32/include/portmacro.h | 153 +- .../GCC/Xtensa_ESP32/include/xt_asm_utils.h | 12 +- .../GCC/Xtensa_ESP32/include/xtensa_api.h | 1 + .../GCC/Xtensa_ESP32/include/xtensa_config.h | 53 +- .../GCC/Xtensa_ESP32/include/xtensa_context.h | 1 + .../GCC/Xtensa_ESP32/include/xtensa_rtos.h | 6 +- .../GCC/Xtensa_ESP32/include/xtensa_timer.h | 1 + .../ThirdParty/GCC/Xtensa_ESP32/port.c | 164 +- .../ThirdParty/GCC/Xtensa_ESP32/port_common.c | 182 +- .../GCC/Xtensa_ESP32/port_systick.c | 215 +- .../GCC/Xtensa_ESP32/portmux_impl.h | 6 +- .../GCC/Xtensa_ESP32/portmux_impl.inc.h | 20 +- .../ThirdParty/GCC/Xtensa_ESP32/xtensa_init.c | 39 +- .../GCC/Xtensa_ESP32/xtensa_overlay_os_hook.c | 1 + .../GCC/AVR_AVRDx/porthardware.h | 18 +- .../GCC/AVR_Mega0/porthardware.h | 2 +- .../Partner-Supported-Ports/README.md | 12 +- .../TI/CORTEX_A53_64-BIT_TI_AM64_SMP/port.c | 418 + .../CORTEX_A53_64-BIT_TI_AM64_SMP/portASM.S | 602 + .../CORTEX_A53_64-BIT_TI_AM64_SMP/portmacro.h | 294 + Source/portable/ThirdParty/XCC/Xtensa/port.c | 71 +- .../portable/ThirdParty/XCC/Xtensa/portasm.S | 2 +- .../ThirdParty/XCC/Xtensa/portbenchmark.h | 4 +- .../portable/ThirdParty/XCC/Xtensa/portclib.c | 396 +- .../ThirdParty/XCC/Xtensa/portmacro.h | 256 +- .../ThirdParty/XCC/Xtensa/porttrace.h | 8 +- .../ThirdParty/XCC/Xtensa/xtensa_api.h | 123 +- .../ThirdParty/XCC/Xtensa/xtensa_config.h | 210 +- .../ThirdParty/XCC/Xtensa/xtensa_context.S | 2 +- .../ThirdParty/XCC/Xtensa/xtensa_context.h | 480 +- .../ThirdParty/XCC/Xtensa/xtensa_init.c | 44 +- .../ThirdParty/XCC/Xtensa/xtensa_intr.c | 155 +- .../ThirdParty/XCC/Xtensa/xtensa_intr_asm.S | 2 +- .../XCC/Xtensa/xtensa_overlay_os_hook.c | 38 +- .../ThirdParty/XCC/Xtensa/xtensa_rtos.h | 234 +- .../ThirdParty/XCC/Xtensa/xtensa_timer.h | 162 +- .../ThirdParty/XCC/Xtensa/xtensa_vectors.S | 2 +- .../portable/ThirdParty/xClang/XCOREAI/port.c | 262 + .../ThirdParty/xClang/XCOREAI/port.xc | 26 + .../ThirdParty/xClang/XCOREAI/portasm.S | 189 + .../ThirdParty/xClang/XCOREAI/portmacro.h | 214 + .../xClang/XCOREAI/rtos_support_rtos_config.h | 95 + .../portable/WizC/PIC18/Drivers/Tick/Tick.c | 2 +- .../WizC/PIC18/Drivers/Tick/isrTick.c | 2 +- Source/portable/WizC/PIC18/addFreeRTOS.h | 2 +- Source/portable/WizC/PIC18/port.c | 4 +- Source/portable/WizC/PIC18/portmacro.h | 8 +- .../portable/oWatcom/16BitDOS/Flsh186/port.c | 2 +- .../oWatcom/16BitDOS/Flsh186/portmacro.h | 2 +- Source/portable/oWatcom/16BitDOS/PC/port.c | 2 +- .../portable/oWatcom/16BitDOS/PC/portmacro.h | 2 +- .../oWatcom/16BitDOS/common/portasm.h | 2 +- .../oWatcom/16BitDOS/common/portcomn.c | 2 +- Source/portable/template/port.c | 78 + Source/portable/template/portmacro.h | 142 + Source/queue.c | 376 +- Source/sbom.spdx | 1541 +-- Source/stream_buffer.c | 232 +- Source/tasks.c | 5017 +++++-- Source/timers.c | 344 +- 737 files changed, 70979 insertions(+), 54177 deletions(-) create mode 100644 Source/MISRA.md create mode 100644 Source/cspell.config.yaml create mode 100644 Source/examples/cmake_example/CMakeLists.txt create mode 100644 Source/examples/cmake_example/main.c create mode 100644 Source/examples/coverity/CMakeLists.txt create mode 100644 Source/examples/coverity/FreeRTOSConfig.h create mode 100644 Source/examples/coverity/README.md create mode 100644 Source/examples/coverity/coverity_misra.config create mode 100644 Source/examples/template_configuration/FreeRTOSConfig.h create mode 100644 Source/examples/template_configuration/readme.md create mode 100644 Source/portable/GCC/ARM_CA53_64_BIT/README.md delete mode 100644 Source/portable/GCC/ARM_CA53_64_BIT/portmacro.h create mode 100644 Source/portable/GCC/ARM_CA53_64_BIT_SRE/README.md delete mode 100644 Source/portable/GCC/ARM_CA53_64_BIT_SRE/portmacro.h create mode 100644 Source/portable/GCC/Arm_AARCH64/README.md rename Source/portable/GCC/{ARM_CA53_64_BIT => Arm_AARCH64}/port.c (54%) rename Source/portable/GCC/{ARM_CA53_64_BIT => Arm_AARCH64}/portASM.S (99%) create mode 100644 Source/portable/GCC/Arm_AARCH64/portmacro.h create mode 100644 Source/portable/GCC/Arm_AARCH64_SRE/README.md rename Source/portable/GCC/{ARM_CA53_64_BIT_SRE => Arm_AARCH64_SRE}/port.c (55%) rename Source/portable/GCC/{ARM_CA53_64_BIT_SRE => Arm_AARCH64_SRE}/portASM.S (99%) create mode 100644 Source/portable/GCC/Arm_AARCH64_SRE/portmacro.h create mode 100644 Source/portable/GCC/RISC-V/chip_extensions.cmake create mode 100644 Source/portable/IAR/RISC-V/chip_extensions.cmake create mode 100644 Source/portable/ThirdParty/Partner-Supported-Ports/TI/CORTEX_A53_64-BIT_TI_AM64_SMP/port.c create mode 100644 Source/portable/ThirdParty/Partner-Supported-Ports/TI/CORTEX_A53_64-BIT_TI_AM64_SMP/portASM.S create mode 100644 Source/portable/ThirdParty/Partner-Supported-Ports/TI/CORTEX_A53_64-BIT_TI_AM64_SMP/portmacro.h create mode 100644 Source/portable/ThirdParty/xClang/XCOREAI/port.c create mode 100644 Source/portable/ThirdParty/xClang/XCOREAI/port.xc create mode 100644 Source/portable/ThirdParty/xClang/XCOREAI/portasm.S create mode 100644 Source/portable/ThirdParty/xClang/XCOREAI/portmacro.h create mode 100644 Source/portable/ThirdParty/xClang/XCOREAI/rtos_support_rtos_config.h create mode 100644 Source/portable/template/port.c create mode 100644 Source/portable/template/portmacro.h diff --git a/ARM.CMSIS-FreeRTOS.pdsc b/ARM.CMSIS-FreeRTOS.pdsc index c5c477318..5d15957ff 100644 --- a/ARM.CMSIS-FreeRTOS.pdsc +++ b/ARM.CMSIS-FreeRTOS.pdsc @@ -929,7 +929,7 @@ - + CMSIS-RTOS implementation for Cortex-M based on FreeRTOS #define RTE_CMSIS_RTOS /* CMSIS-RTOS */ @@ -942,7 +942,7 @@ - + CMSIS-RTOS2 implementation for Cortex-M based on FreeRTOS #define RTE_CMSIS_RTOS2 /* CMSIS-RTOS2 */ @@ -959,7 +959,7 @@ - + CMSIS-RTOS2 implementation for Cortex-A based on FreeRTOS #define RTE_CMSIS_RTOS2 /* CMSIS-RTOS2 */ @@ -976,9 +976,9 @@ - + FreeRTOS Real Time Kernel - https://www.freertos.org/Documentation/FreeRTOS_Reference_Manual_V10.0.0.pdf + https://www.freertos.org/RTOS.html Core API (Kernel, Tasks, Semaphores, Mutexes, Queues) for Cortex-M diff --git a/Source/CMakeLists.txt b/Source/CMakeLists.txt index a68b652ca..5323ec19b 100644 --- a/Source/CMakeLists.txt +++ b/Source/CMakeLists.txt @@ -4,14 +4,16 @@ cmake_minimum_required(VERSION 3.15) # FREERTOS_PORT, if not specified and native port detected, uses the native compile. # # User is responsible for one library target: -# freertos_config ,typcially an INTERFACE library +# freertos_config ,typically an INTERFACE library # # DEPRECATED: FREERTOS_CONFIG_FILE_DIRECTORY - but still supported if no freertos_config defined for now. # May be removed at some point in the future. +# # User can choose which heap implementation to use (either the implementations -# included with FreeRTOS [1..5] or a custom implementation ) by providing the -# option FREERTOS_HEAP. If the option is not set, the cmake will default to -# using heap_4.c. +# included with FreeRTOS [1..5] or a custom implementation) by providing the +# option FREERTOS_HEAP. When dynamic allocation is used, the user must specify a +# heap implementation. If the option is not set, the cmake will use no heap +# implementation (e.g. when only static allocation is used). # `freertos_config` target defines the path to FreeRTOSConfig.h and optionally other freertos based config files if(NOT TARGET freertos_config ) @@ -37,9 +39,6 @@ if(NOT TARGET freertos_config ) endif() endif() -# Heap number or absolute path to custom heap implementation provided by user -set(FREERTOS_HEAP "4" CACHE STRING "FreeRTOS heap model number. 1 .. 5. Or absolute path to custom heap source file") - # FreeRTOS port option if(NOT FREERTOS_PORT) message(WARNING " FREERTOS_PORT is not set. Please specify it from top-level CMake file (example):\n" @@ -59,8 +58,8 @@ if(NOT FREERTOS_PORT) " CODEWARRIOR_COLDFIRE_V2 - Compiler: CoreWarrior Target: ColdFire V2\n" " CODEWARRIOR_HCS12 - Compiler: CoreWarrior Target: HCS12\n" " GCC_ARM_CA9 - Compiler: GCC Target: ARM Cortex-A9\n" - " GCC_ARM_CA53_64_BIT - Compiler: GCC Target: ARM Cortex-A53 64 bit\n" - " GCC_ARM_CA53_64_BIT_SRE - Compiler: GCC Target: ARM Cortex-A53 64 bit SRE\n" + " GCC_ARM_AARCH64 - Compiler: GCC Target: ARM v8-A\n" + " GCC_ARM_AARCH64_SRE - Compiler: GCC Target: ARM v8-A SRE\n" " GCC_ARM_CM0 - Compiler: GCC Target: ARM Cortex-M0\n" " GCC_ARM_CM3 - Compiler: GCC Target: ARM Cortex-M3\n" " GCC_ARM_CM3_MPU - Compiler: GCC Target: ARM Cortex-M3 with MPU\n" @@ -107,6 +106,7 @@ if(NOT FREERTOS_PORT) " GCC_PPC440_XILINX - Compiler: GCC Target: Xilinx PPC440\n" " GCC_RISC_V - Compiler: GCC Target: RISC-V\n" " GCC_RISC_V_PULPINO_VEGA_RV32M1RM - Compiler: GCC Target: RISC-V Pulpino Vega RV32M1RM\n" + " GCC_RISC_V_GENERIC - Compiler: GCC Target: RISC-V with FREERTOS_RISCV_EXTENSION\n" " GCC_RL78 - Compiler: GCC Target: Renesas RL78\n" " GCC_RX100 - Compiler: GCC Target: Renesas RX100\n" " GCC_RX200 - Compiler: GCC Target: Renesas RX200\n" @@ -157,6 +157,7 @@ if(NOT FREERTOS_PORT) " IAR_MSP430 - Compiler: IAR Target: MSP430\n" " IAR_MSP430X - Compiler: IAR Target: MSP430X\n" " IAR_RISC_V - Compiler: IAR Target: RISC-V\n" + " IAR_RISC_V_GENERIC - Compiler: IAR Target: RISC-V with FREERTOS_RISCV_EXTENSION\n" " IAR_RL78 - Compiler: IAR Target: Renesas RL78\n" " IAR_RX100 - Compiler: IAR Target: Renesas RX100\n" " IAR_RX600 - Compiler: IAR Target: Renesas RX600\n" @@ -196,6 +197,7 @@ if(NOT FREERTOS_PORT) " SOFTUNE_MB91460 - Compiler: Softune Target: MB91460\n" " SOFTUNE_MB96340 - Compiler: Softune Target: MB96340\n" " TASKING_ARM_CM4F - Compiler: Tasking Target: ARM Cortex-M4 with FPU\n" + " TEMPLATE - Compiler: HOST Target: None\n" " CDK_THEAD_CK802 - Compiler: CDK Target: T-head CK802\n" " XCC_XTENSA - Compiler: XCC Target: Xtensa\n" " WIZC_PIC18 - Compiler: WizC Target: PIC18") @@ -228,46 +230,13 @@ elseif((FREERTOS_PORT STREQUAL "A_CUSTOM_PORT") AND (NOT TARGET freertos_kernel_ " freertos_kernel_include)") endif() -######################################################################## -# Overall Compile Options -# Note the compile option strategy is to error on everything and then -# Per library opt-out of things that are warnings/errors. -# This ensures that no matter what strategy for compilation you take, the -# builds will still occur. -# -# Only tested with GNU and Clang. -# Other options are https://cmake.org/cmake/help/latest/variable/CMAKE_LANG_COMPILER_ID.html#variable:CMAKE_%3CLANG%3E_COMPILER_ID -# Naming of compilers translation map: -# -# FreeRTOS | CMake -# ------------------- -# CCS | ?TBD? -# GCC | GNU, Clang, *Clang Others? -# IAR | IAR -# Keil | ARMCC -# MSVC | MSVC # Note only for MinGW? -# Renesas | ?TBD? - -add_compile_options( - ### Gnu/Clang C Options - $<$:-fdiagnostics-color=always> - $<$:-fcolor-diagnostics> - - $<$:-Wall> - $<$:-Wextra> - $<$:-Wpedantic> - $<$:-Werror> - $<$:-Weverything> - - # TODO: Add in other Compilers here. -) - +add_library(freertos_kernel STATIC) ######################################################################## add_subdirectory(include) add_subdirectory(portable) -add_library(freertos_kernel STATIC +target_sources(freertos_kernel PRIVATE croutine.c event_groups.c list.c @@ -275,11 +244,17 @@ add_library(freertos_kernel STATIC stream_buffer.c tasks.c timers.c - - # If FREERTOS_HEAP is digit between 1 .. 5 - it is heap number, otherwise - it is path to custom heap source file - $>,${FREERTOS_HEAP},portable/MemMang/heap_${FREERTOS_HEAP}.c> ) +if (DEFINED FREERTOS_HEAP ) + # User specified a heap implementation add heap implementation to freertos_kernel. + target_sources(freertos_kernel PRIVATE + # If FREERTOS_HEAP is digit between 1 .. 5 - it is heap number, otherwise - it is path to custom heap source file + $>,${FREERTOS_HEAP},portable/MemMang/heap_${FREERTOS_HEAP}.c> + ) +endif() + + target_link_libraries(freertos_kernel PUBLIC freertos_kernel_port diff --git a/Source/History.txt b/Source/History.txt index 87e795277..a8e5ac7ba 100644 --- a/Source/History.txt +++ b/Source/History.txt @@ -1,5 +1,97 @@ Documentation and download available at https://www.FreeRTOS.org/ +Changes between FreeRTOS V11.0.0 and FreeRTOS V11.0.1 released December 21, 2023 + + + Updated the SBOM file. + +Changes between FreeRTOS V10.6.2 and FreeRTOS V11.0.0 released December 18, 2023 + + + SMP merged into the mainline: While FreeRTOS introduced Asymmetric + Multiprocessing (AMP) support in 2017, FreeRTOS Version 11.0.0 is the + first to merge Symmetric Multiprocessing (SMP) support into the mainline + release. SMP enables one instance of the FreeRTOS Kernel to schedule tasks + across multiple identical processor cores. We thank Mike Bruno and Jerry + McCarthy of XMOS and, Darian Liang, Sudeep Mohanty and Zim Kalinowski of + Espressif Systems for their contributions. + + Switch MISRA compliance checking from PC Lint to Coverity, and update from + MISRA C:2004 to MISRA C:2012. + + Add a template FreeRTOSConfig.h, inclusive of an abbreviated explanation of + each configuration item. Application writers can use this template as a + starting point to create the FreeRTOSConfig.h file for their application. + + Add a template FreeRTOS port which can be used as a starting point for + developing a new FreeRTOS port. + + Add bounds checking and obfuscation to internal heap block pointers in + heap_4.c and heap_5.c to help catch pointer corruptions. The application can + enable these checks by setting configENABLE_HEAP_PROTECTOR to 1 in their + FreeRTOSConfig.h. We thank @oliverlavery for their contribution. + + Update vTaskList and vTaskGetRunTimeStats APIs to replace the use of sprintf + with snprintf. + + Add trace macros to ports that enable tracing the interaction of ISRs with + scheduler events. We thank @conara for their contribution. + + Add trace macros that enable tracing of entering and exiting all APIs. We + thank @Techcore123 for their contribution. + + Add uxTaskBasePriorityGet and uxTaskBasePriorityGetFromISR APIs to get the + base priority of a task. The base priority of a task is the priority that + was last assigned to the task - which due to priority inheritance, may not + be the current priority of the task. + + Add pdTICKS_TO_MS macro to convert time in FreeRTOS ticks to time in + milliseconds. We thank @Dazza0 for their contribution. + + Add default implementations of vApplicationGetIdleTaskMemory and + vApplicationGetTimerTaskMemory. The application can enable these default + implementations by setting configKERNEL_PROVIDED_STATIC_MEMORY to 1 in their + FreeRTOSConfig.h. We thank @mdnr-g for their contribution. + + Update vTaskGetInfo to include start and end of the stack whenever both + values are available. We thank @vinceburns for their contribution. + + Prevent tasks waiting for a notification from being resumed by calls to + vTaskResume or vTaskResumeFromISR. We thank @Moral-Hao for their + contribution. + + Add asserts to validate that the application has correctly installed + FreeRTOS handlers for PendSV and SVCall interrupts on Cortex-M devices. + We thank @jefftenney for their contribution. + + Rename ARM_CA53_64_BIT and ARM_CA53_64_BIT_SRE ports to Arm_AARCH64 and + Arm_AARCH64_SRE respectively as these ports are applicable to all AArch64 + architecture. We thank @urutva for their contribution. + + Add CMake support to allow the application writer to select the RISC-V + chip extension. We thank @JoeBenczarski for their contribution. + + Add CMake support to allow the application writer to build an application + with static allocation only. We thank @conara for their contribution. + + Make taskYIELD available to unprivileged tasks for ARMv8-M ports. + + Update Cortex-M23 ports to not use PSPLIM_NS. We thank @urutva for their + contribution. + + Update the SysTick setup code for ARMv8-M ports to first configure the clock + source and then enable SysTick. This is needed to address a bug in QEMU + versions older than 7.0.0, which causes an emulation error if SysTick is + enabled without first selecting a valid clock source. We thank @jefftenney + for their contribution. + + Add the port-optimized task selection algorithm optionally available for + ARMv7-M ports to the ARMv8-M ports. We thank @jefftenney for their + contribution. + + Improve the speed of pvPortMalloc in heap_4.c and heap_5.c by removing + unnecessary steps while splitting a large memory block into two. We thank + @Moral-Hao for their contribution. + + Shorten the critical section in pvPortMalloc in heap_2.c, heap_4.c and + heap_5.c by moving the size calculation out of the critical section. We thank + @Moral-Hao for their contribution. + + Update xTaskNotifyWait and ulTaskNotifyTake to remove the non-deterministic + operation of traversing a linked link from a critical section. We thank + @karver8 for their contribution. + + Fix stack end and stack size computation in POSIX port to meet the stack + alignment requirements on MacOS. We thank @tegimeki for their contribution. + + Update the vTaskPrioritySet implementation to use the new priority when the + task has inherited priority from a mutex it is holding, and the new priority + is bigger than the inherited priority. We thank @Moral-Hao for their + contribution. + + Add stack alignment adjustment if stack grows upwards. We thank @ivq for + their contribution. + + Fix pxTopOfStack calculation in configINIT_TLS_BLOCK when picolib C is + selected as the C library implementation to ensure that + pxPortInitialiseStack does not overwrite the data in the TLS block portion + of the stack. We thank @bebebib-rs for their contribution. + + Fix vPortEndScheduler() for the MSVC port so that the function + prvProcessSimulatedInterrupts is not stuck in an infinite loop when the + scheduler is stopped. We thank @Ju1He1 for their contribution. + + Add the Pull Request (PR) Process explaining the stages a PR goes through. + Changes between FreeRTOS V10.6.1 and FreeRTOS V10.6.2 released November 29, 2023 + Add the following improvements to the new MPU wrapper (mpu_wrappers_v2.c) @@ -26,7 +118,7 @@ Changes between FreeRTOS V10.6.0 and FreeRTOS V10.6.1 released August 17, 2023 - Xinhui Shao, Yumeng Wei, Huaiyu Yan, Zhen Ling of School of Computer Science and Engineering, Southeast University, China. -Changes between FreeRTOS V10.5.1 and FreeRTOS V10.6.0 released July 13, 2023 +Changes between FreeRTOS V10.5.1 and FreeRTOS 10.6.0 released July 13, 2023 + Add a new MPU wrapper that places additional restrictions on unprivileged tasks. The following is the list of changes introduced with the new MPU @@ -87,8 +179,8 @@ Changes between FreeRTOS V10.5.1 and FreeRTOS V10.6.0 released July 13, 2023 China. - Xinwen Fu of Department of Computer Science, University of Massachusetts Lowell, USA. - - Yuequi Chen, Zicheng Wang, Minghao Lin of University of Colorado - Boulder, USA. + - Yueqi Chen, Zicheng Wang, Minghao Lin, Jiahe Wang of University of + Colorado Boulder, USA. + Add Cortex-M35P port. Contributed by @urutva. + Add embedded extension (RV32E) support to the IAR RISC-V port. + Add ulTaskGetRunTimeCounter and ulTaskGetRunTimePercent APIs. Contributed by diff --git a/Source/MISRA.md b/Source/MISRA.md new file mode 100644 index 000000000..8d501e0bd --- /dev/null +++ b/Source/MISRA.md @@ -0,0 +1,118 @@ +# MISRA Compliance + +FreeRTOS-Kernel conforms to [MISRA C:2012](https://www.misra.org.uk/misra-c) +guidelines, with the deviations listed below. Compliance is checked with +Coverity static analysis. Since the FreeRTOS kernel is designed for +small-embedded devices, it needs to have a very small memory footprint and +has to be efficient. To achieve that and to increase the performance, it +deviates from some MISRA rules. The specific deviations, suppressed inline, +are listed below. + +Additionally, [MISRA configuration file](examples/coverity/coverity_misra.config) +contains project wide deviations. + +### Suppressed with Coverity Comments +To find the violation references in the source files run grep on the source code +with ( Assuming rule 8.4 violation; with justification in point 1 ): +``` +grep 'MISRA Ref 8.4.1' . -rI +``` + +#### Rule 8.4 + +MISRA C:2012 Rule 8.4: A compatible declaration shall be visible when an +object or function with external linkage is defined. + +_Ref 8.4.1_ + - pxCurrentTCB(s) is defined with external linkage but it is only referenced + from the assembly code in the port files. Therefore, adding a declaration in + header file is not useful as the assembly code will still need to declare it + separately. + +_Ref 8.4.2_ + - xQueueRegistry is defined with external linkage because it is accessed by the + kernel unit tests. It is not meant to be directly accessed by the application + and therefore, not declared in a header file. + +#### Rule 8.6 + +MISRA C:2012 Rule 8.6: An identifier with external linkage shall have exactly +one external definition. + +_Ref 8.6.1_ + - This rule prohibits an identifier with external linkage to have multiple + definitions or no definition. FreeRTOS hook functions are implemented in + the application and therefore, have no definition in the Kernel code. + +#### Rule 11.1 +MISRA C:2012 Rule 11.1: Conversions shall not be performed between a pointer to +function and any other type. + +_Ref 11.1.1_ + - The pointer to function is casted into void to avoid unused parameter + compiler warning when Stream Buffer's Tx and Rx Completed callback feature is + not used. + +#### Rule 11.3 + +MISRA C:2012 Rule 11.3: A cast shall not be performed between a pointer to +object type and a pointer to a different object type. + +_Ref 11.3.1_ + - This rule prohibits casting a pointer to object into a pointer to a + different object because it may result in an incorrectly aligned pointer, + leading to undefined behavior. Even if the casting produces a correctly + aligned pointer, the behavior may be still undefined if the pointer is + used to access an object. FreeRTOS deliberately creates external aliases + for all the kernel object types (StaticEventGroup_t, StaticQueue_t, + StaticStreamBuffer_t, StaticTimer_t and StaticTask_t) for data hiding + purposes. The internal object types and the corresponding external + aliases are guaranteed to have the same size and alignment which is + checked using configASSERT. + + +#### Rule 11.5 + +MISRA C:2012 Rule 11.5: A conversion should not be performed from pointer to +void into pointer to object. +This rule prohibits conversion of a pointer to void into a pointer to +object because it may result in an incorrectly aligned pointer leading +to undefined behavior. + +_Ref 11.5.1_ + - The memory blocks returned by pvPortMalloc() are guaranteed to meet the + architecture alignment requirements specified by portBYTE_ALIGNMENT. + The casting of the pointer to void returned by pvPortMalloc() is, + therefore, safe because it is guaranteed to be aligned. + +_Ref 11.5.2_ + - The conversion from a pointer to void into a pointer to EventGroup_t is + safe because it is a pointer to EventGroup_t, which is returned to the + application at the time of event group creation for data hiding + purposes. + +_Ref 11.5.3_ + - The conversion from a pointer to void in list macros for list item owner + is safe because the type of the pointer stored and retrieved is the + same. + +_Ref 11.5.4_ + - The conversion from a pointer to void into a pointer to EventGroup_t is + safe because it is a pointer to EventGroup_t, which is passed as a + parameter to the xTimerPendFunctionCallFromISR API when the callback is + pended. + +_Ref 11.5.5_ + - The conversion from a pointer to void into a pointer to uint8_t is safe + because data storage buffers are implemented as uint8_t arrays for the + ease of sizing, alignment and access. + +#### Rule 21.6 + +MISRA C-2012 Rule 21.6: The Standard Library input/output functions shall not +be used. + +_Ref 21.6.1_ + - The Standard Library function snprintf is used in vTaskListTasks and + vTaskGetRunTimeStatistics APIs, both of which are utility functions only and + are not considered part of core kernel implementation. diff --git a/Source/README.md b/Source/README.md index dd79eee6c..7a60f3594 100644 --- a/Source/README.md +++ b/Source/README.md @@ -1,18 +1,39 @@ [![CMock Unit Tests](https://github.com/FreeRTOS/FreeRTOS-Kernel/actions/workflows/unit-tests.yml/badge.svg?branch=main&event=push)](https://github.com/FreeRTOS/FreeRTOS-Kernel/actions/workflows/unit-tests.yml?query=branch%3Amain+event%3Apush+workflow%3A%22CMock+Unit+Tests%22++) [![codecov](https://codecov.io/gh/FreeRTOS/FreeRTOS-Kernel/badge.svg?branch=main)](https://codecov.io/gh/FreeRTOS/FreeRTOS-Kernel) + ## Getting started -This repository contains FreeRTOS kernel source/header files and kernel ports only. This repository is referenced as a submodule in [FreeRTOS/FreeRTOS](https://github.com/FreeRTOS/FreeRTOS) repository, which contains pre-configured demo application projects under ```FreeRTOS/Demo``` directory. -The easiest way to use FreeRTOS is to start with one of the pre-configured demo application projects. That way you will have the correct FreeRTOS source files included, and the correct include paths configured. Once a demo application is building and executing you can remove the demo application files, and start to add in your own application source files. See the [FreeRTOS Kernel Quick Start Guide](https://www.FreeRTOS.org/FreeRTOS-quick-start-guide.html) for detailed instructions and other useful links. +This repository contains FreeRTOS kernel source/header files and kernel +ports only. This repository is referenced as a submodule in +[FreeRTOS/FreeRTOS](https://github.com/FreeRTOS/FreeRTOS) +repository, which contains pre-configured demo application projects under +```FreeRTOS/Demo``` directory. + +The easiest way to use FreeRTOS is to start with one of the pre-configured demo +application projects. That way you will have the correct FreeRTOS source files +included, and the correct include paths configured. Once a demo application is +building and executing you can remove the demo application files, and start to +add in your own application source files. See the +[FreeRTOS Kernel Quick Start Guide](https://www.FreeRTOS.org/FreeRTOS-quick-start-guide.html) +for detailed instructions and other useful links. -Additionally, for FreeRTOS kernel feature information refer to the [Developer Documentation](https://www.FreeRTOS.org/features.html), and [API Reference](https://www.FreeRTOS.org/a00106.html). +Additionally, for FreeRTOS kernel feature information refer to the +[Developer Documentation](https://www.FreeRTOS.org/features.html), +and [API Reference](https://www.FreeRTOS.org/a00106.html). + +Also for contributing and creating a Pull Request please refer to +[the instructions here](.github/CONTRIBUTING.md#contributing-via-pull-request). ### Getting help -If you have any questions or need assistance troubleshooting your FreeRTOS project, we have an active community that can help on the [FreeRTOS Community Support Forum](https://forums.freertos.org). + +If you have any questions or need assistance troubleshooting your FreeRTOS project, +we have an active community that can help on the +[FreeRTOS Community Support Forum](https://forums.freertos.org). ## To consume FreeRTOS-Kernel ### Consume with CMake + If using CMake, it is recommended to use this repository using FetchContent. Add the following into your project's main or a subdirectory's `CMakeLists.txt`: @@ -25,8 +46,16 @@ FetchContent_Declare( freertos_kernel ) ``` +In case you prefer to add it as a git submodule, do: + +```bash +git submodule add https://github.com/FreeRTOS/FreeRTOS-Kernel.git +git submodule update --init +``` + - Add a freertos_config library (typically an INTERFACE library) The following assumes the directory structure: - `include/FreeRTOSConfig.h` + ```cmake add_library(freertos_config INTERFACE) @@ -41,6 +70,12 @@ target_compile_definitions(freertos_config ) ``` +In case you installed FreeRTOS-Kernel as a submodule, you will have to add it as a subdirectory: + +```cmake +add_subdirectory(${FREERTOS_PATH}) +``` + - Configure the FreeRTOS-Kernel and make it available - this particular example supports a native and cross-compiled build option. @@ -56,18 +91,29 @@ endif() FetchContent_MakeAvailable(freertos_kernel) ``` +- In case of cross compilation, you should also add the following to `freertos_config`: + +```cmake +target_compile_definitions(freertos_config INTERFACE ${definitions}) +target_compile_options(freertos_config INTERFACE ${options}) +``` + ### Consuming stand-alone - Cloning this repository To clone using HTTPS: + ``` git clone https://github.com/FreeRTOS/FreeRTOS-Kernel.git ``` + Using SSH: + ``` git clone git@github.com:FreeRTOS/FreeRTOS-Kernel.git ``` ## Repository structure + - The root of this repository contains the three files that are common to every port - list.c, queue.c and tasks.c. The kernel is contained within these three files. croutine.c implements the optional co-routine functionality - which @@ -78,23 +124,59 @@ See the readme file in the ```./portable``` directory for more information. - The ```./include``` directory contains the real time kernel header files. +- The ```./template_configuration``` directory contains a sample `FreeRTOSConfig.h` to help jumpstart a new project. +See the [FreeRTOSConfig.h](examples/template_configuration/FreeRTOSConfig.h) file for instructions. + ### Code Formatting -FreeRTOS files are formatted using the "uncrustify" tool. The configuration file used by uncrustify can be found in the [.github/uncrustify.cfg](.github/uncrustify.cfg) file. + +FreeRTOS files are formatted using the +"[uncrustify](https://github.com/uncrustify/uncrustify)" tool. +The configuration file used by uncrustify can be found in the +[FreeRTOS/CI-CD-GitHub-Actions's](https://github.com/FreeRTOS/CI-CD-Github-Actions) +[uncrustify.cfg](https://github.com/FreeRTOS/CI-CD-Github-Actions/tree/main/formatting) +file. ### Line Endings -File checked into the FreeRTOS-Kernel repository use unix-style LF line endings for the best compatbility with git. -For optmial compatibility with Microsoft Windows tools, it is best to enable the git autocrlf feature. You can eanble this setting for the current repository using the following command: +File checked into the FreeRTOS-Kernel repository use unix-style LF line endings +for the best compatibility with git. + +For optimal compatibility with Microsoft Windows tools, it is best to enable +the git autocrlf feature. You can enable this setting for the current +repository using the following command: + ``` git config core.autocrlf true ``` ### Git History Optimizations -Some commits in this repository perform large refactors which touch many lines and lead to unwanted behavior when using the `git blame` command. You can configure git to ignore the list of large refactor commits in this repository with the followig command: + +Some commits in this repository perform large refactors which touch many lines +and lead to unwanted behavior when using the `git blame` command. You can +configure git to ignore the list of large refactor commits in this repository +with the following command: + ``` git config blame.ignoreRevsFile .git-blame-ignore-revs ``` -### Spelling -*lexicon.txt* contains words that are not traditionally found in an English dictionary. It is used by the spellchecker to verify the various jargon, variable names, and other odd words used in the FreeRTOS code base. If your pull request fails to pass the spelling and you believe this is a mistake, then add the word to *lexicon.txt*. -Note that only the FreeRTOS Kernel source files are checked for proper spelling, the portable section is ignored. +### Spelling and Formatting + +We recommend using [Visual Studio Code](https://code.visualstudio.com), +commonly referred to as VSCode, when working on the FreeRTOS-Kernel. +The FreeRTOS-Kernel also uses [cSpell](https://cspell.org/) as part of its +spelling check. The config file for which can be found at [cspell.config.yaml](cspell.config.yaml) +There is additionally a +[cSpell plugin for VSCode](https://marketplace.visualstudio.com/items?itemName=streetsidesoftware.code-spell-checker) +that can be used as well. +*[.cSpellWords.txt](.github/.cSpellWords.txt)* contains words that are not +traditionally found in an English dictionary. It is used by the spellchecker +to verify the various jargon, variable names, and other odd words used in the +FreeRTOS code base are correct. If your pull request fails to pass the spelling +and you believe this is a mistake, then add the word to +*[.cSpellWords.txt](.github/.cSpellWords.txt)*. When adding a word please +then sort the list, which can be done by running the bash command: +`sort -u .cSpellWords.txt -o .cSpellWords.txt` +Note that only the FreeRTOS-Kernel Source Files, [include](include), +[portable/MemMang](portable/MemMang), and [portable/Common](portable/Common) +files are checked for proper spelling, and formatting at this time. diff --git a/Source/croutine.c b/Source/croutine.c index 559276c52..1cf617dee 100644 --- a/Source/croutine.c +++ b/Source/croutine.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -43,12 +43,12 @@ /* Lists for ready and blocked co-routines. --------------------*/ - static List_t pxReadyCoRoutineLists[ configMAX_CO_ROUTINE_PRIORITIES ]; /*< Prioritised ready co-routines. */ - static List_t xDelayedCoRoutineList1; /*< Delayed co-routines. */ - static List_t xDelayedCoRoutineList2; /*< Delayed co-routines (two lists are used - one for delays that have overflowed the current tick count. */ - static List_t * pxDelayedCoRoutineList = NULL; /*< Points to the delayed co-routine list currently being used. */ - static List_t * pxOverflowDelayedCoRoutineList = NULL; /*< Points to the delayed co-routine list currently being used to hold co-routines that have overflowed the current tick count. */ - static List_t xPendingReadyCoRoutineList; /*< Holds co-routines that have been readied by an external event. They cannot be added directly to the ready lists as the ready lists cannot be accessed by interrupts. */ + static List_t pxReadyCoRoutineLists[ configMAX_CO_ROUTINE_PRIORITIES ]; /**< Prioritised ready co-routines. */ + static List_t xDelayedCoRoutineList1; /**< Delayed co-routines. */ + static List_t xDelayedCoRoutineList2; /**< Delayed co-routines (two lists are used - one for delays that have overflowed the current tick count. */ + static List_t * pxDelayedCoRoutineList = NULL; /**< Points to the delayed co-routine list currently being used. */ + static List_t * pxOverflowDelayedCoRoutineList = NULL; /**< Points to the delayed co-routine list currently being used to hold co-routines that have overflowed the current tick count. */ + static List_t xPendingReadyCoRoutineList; /**< Holds co-routines that have been readied by an external event. They cannot be added directly to the ready lists as the ready lists cannot be accessed by interrupts. */ /* Other file private variables. --------------------------------*/ CRCB_t * pxCurrentCoRoutine = NULL; @@ -107,7 +107,12 @@ BaseType_t xReturn; CRCB_t * pxCoRoutine; + traceENTER_xCoRoutineCreate( pxCoRoutineCode, uxPriority, uxIndex ); + /* Allocate the memory that will store the co-routine control block. */ + /* MISRA Ref 11.5.1 [Malloc memory assignment] */ + /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-115 */ + /* coverity[misra_c_2012_rule_11_5_violation] */ pxCoRoutine = ( CRCB_t * ) pvPortMalloc( sizeof( CRCB_t ) ); if( pxCoRoutine ) @@ -156,6 +161,8 @@ xReturn = errCOULD_NOT_ALLOCATE_REQUIRED_MEMORY; } + traceRETURN_xCoRoutineCreate( xReturn ); + return xReturn; } /*-----------------------------------------------------------*/ @@ -165,6 +172,8 @@ { TickType_t xTimeToWake; + traceENTER_vCoRoutineAddToDelayedList( xTicksToDelay, pxEventList ); + /* Calculate the time to wake - this may overflow but this is * not a problem. */ xTimeToWake = xCoRoutineTickCount + xTicksToDelay; @@ -196,6 +205,8 @@ * function must be called with interrupts disabled. */ vListInsert( pxEventList, &( pxCurrentCoRoutine->xEventListItem ) ); } + + traceRETURN_vCoRoutineAddToDelayedList(); } /*-----------------------------------------------------------*/ @@ -283,6 +294,8 @@ void vCoRoutineSchedule( void ) { + traceENTER_vCoRoutineSchedule(); + /* Only run a co-routine after prvInitialiseCoRoutineLists() has been * called. prvInitialiseCoRoutineLists() is called automatically when a * co-routine is created. */ @@ -313,6 +326,8 @@ /* Call the co-routine. */ ( pxCurrentCoRoutine->pxCoRoutineFunction )( pxCurrentCoRoutine, pxCurrentCoRoutine->uxIndex ); } + + traceRETURN_vCoRoutineSchedule(); } /*-----------------------------------------------------------*/ @@ -341,6 +356,8 @@ CRCB_t * pxUnblockedCRCB; BaseType_t xReturn; + traceENTER_xCoRoutineRemoveFromEventList( pxEventList ); + /* This function is called from within an interrupt. It can only access * event lists and the pending ready list. This function assumes that a * check has already been made to ensure pxEventList is not empty. */ @@ -357,6 +374,8 @@ xReturn = pdFALSE; } + traceRETURN_xCoRoutineRemoveFromEventList( xReturn ); + return xReturn; } diff --git a/Source/cspell.config.yaml b/Source/cspell.config.yaml new file mode 100644 index 000000000..911ce1d8f --- /dev/null +++ b/Source/cspell.config.yaml @@ -0,0 +1,31 @@ +--- +$schema: https://raw.githubusercontent.com/streetsidesoftware/cspell/main/cspell.schema.json +version: '0.2' +# Allows things like stringLength +allowCompoundWords: true + +# Read files not to spell check from the git ignore +useGitignore: true + +# Language settings for C +languageSettings: + - caseSensitive: false + enabled: true + languageId: c + locale: "*" + +# Add a dictionary, and the path to the word list +dictionaryDefinitions: + - name: freertos-words + path: '.github/.cSpellWords.txt' + addWords: true + +dictionaries: + - freertos-words + +# Paths and files to ignore +ignorePaths: + - 'dependency' + - 'docs' + - 'ThirdParty' + - 'History.txt' diff --git a/Source/event_groups.c b/Source/event_groups.c index e337f13bd..9f98536e5 100644 --- a/Source/event_groups.c +++ b/Source/event_groups.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -40,11 +40,10 @@ #include "timers.h" #include "event_groups.h" -/* Lint e961, e750 and e9021 are suppressed as a MISRA exception justified - * because the MPU ports require MPU_WRAPPERS_INCLUDED_FROM_API_FILE to be defined +/* The MPU ports require MPU_WRAPPERS_INCLUDED_FROM_API_FILE to be defined * for the header files above, but not in this file, in order to generate the * correct privileged Vs unprivileged linkage and placement. */ -#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE /*lint !e961 !e750 !e9021 See comment above. */ +#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE typedef struct EventGroupDef_t { @@ -82,6 +81,8 @@ static BaseType_t prvTestWaitCondition( const EventBits_t uxCurrentEventBits, { EventGroup_t * pxEventBits; + traceENTER_xEventGroupCreateStatic( pxEventGroupBuffer ); + /* A StaticEventGroup_t object must be provided. */ configASSERT( pxEventGroupBuffer ); @@ -92,11 +93,14 @@ static BaseType_t prvTestWaitCondition( const EventBits_t uxCurrentEventBits, * event group structure. */ volatile size_t xSize = sizeof( StaticEventGroup_t ); configASSERT( xSize == sizeof( EventGroup_t ) ); - } /*lint !e529 xSize is referenced if configASSERT() is defined. */ + } #endif /* configASSERT_DEFINED */ /* The user has provided a statically allocated event group - use it. */ - pxEventBits = ( EventGroup_t * ) pxEventGroupBuffer; /*lint !e740 !e9087 EventGroup_t and StaticEventGroup_t are deliberately aliased for data hiding purposes and guaranteed to have the same size and alignment requirement - checked by configASSERT(). */ + /* MISRA Ref 11.3.1 [Misaligned access] */ + /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-113 */ + /* coverity[misra_c_2012_rule_11_3_violation] */ + pxEventBits = ( EventGroup_t * ) pxEventGroupBuffer; if( pxEventBits != NULL ) { @@ -122,6 +126,8 @@ static BaseType_t prvTestWaitCondition( const EventBits_t uxCurrentEventBits, traceEVENT_GROUP_CREATE_FAILED(); } + traceRETURN_xEventGroupCreateStatic( pxEventBits ); + return pxEventBits; } @@ -134,20 +140,12 @@ static BaseType_t prvTestWaitCondition( const EventBits_t uxCurrentEventBits, { EventGroup_t * pxEventBits; - /* Allocate the event group. Justification for MISRA deviation as - * follows: pvPortMalloc() always ensures returned memory blocks are - * aligned per the requirements of the MCU stack. In this case - * pvPortMalloc() must return a pointer that is guaranteed to meet the - * alignment requirements of the EventGroup_t structure - which (if you - * follow it through) is the alignment requirements of the TickType_t type - * (EventBits_t being of TickType_t itself). Therefore, whenever the - * stack alignment requirements are greater than or equal to the - * TickType_t alignment requirements the cast is safe. In other cases, - * where the natural word size of the architecture is less than - * sizeof( TickType_t ), the TickType_t variables will be accessed in two - * or more reads operations, and the alignment requirements is only that - * of each individual read. */ - pxEventBits = ( EventGroup_t * ) pvPortMalloc( sizeof( EventGroup_t ) ); /*lint !e9087 !e9079 see comment above. */ + traceENTER_xEventGroupCreate(); + + /* MISRA Ref 11.5.1 [Malloc memory assignment] */ + /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-115 */ + /* coverity[misra_c_2012_rule_11_5_violation] */ + pxEventBits = ( EventGroup_t * ) pvPortMalloc( sizeof( EventGroup_t ) ); if( pxEventBits != NULL ) { @@ -167,9 +165,11 @@ static BaseType_t prvTestWaitCondition( const EventBits_t uxCurrentEventBits, } else { - traceEVENT_GROUP_CREATE_FAILED(); /*lint !e9063 Else branch only exists to allow tracing and does not generate code if trace macros are not defined. */ + traceEVENT_GROUP_CREATE_FAILED(); } + traceRETURN_xEventGroupCreate( pxEventBits ); + return pxEventBits; } @@ -186,6 +186,8 @@ EventBits_t xEventGroupSync( EventGroupHandle_t xEventGroup, BaseType_t xAlreadyYielded; BaseType_t xTimeoutOccurred = pdFALSE; + traceENTER_xEventGroupSync( xEventGroup, uxBitsToSet, uxBitsToWaitFor, xTicksToWait ); + configASSERT( ( uxBitsToWaitFor & eventEVENT_BITS_CONTROL_BYTES ) == 0 ); configASSERT( uxBitsToWaitFor != 0 ); #if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) ) @@ -243,7 +245,7 @@ EventBits_t xEventGroupSync( EventGroupHandle_t xEventGroup, { if( xAlreadyYielded == pdFALSE ) { - portYIELD_WITHIN_API(); + taskYIELD_WITHIN_API(); } else { @@ -295,6 +297,8 @@ EventBits_t xEventGroupSync( EventGroupHandle_t xEventGroup, /* Prevent compiler warnings when trace macros are not used. */ ( void ) xTimeoutOccurred; + traceRETURN_xEventGroupSync( uxReturn ); + return uxReturn; } /*-----------------------------------------------------------*/ @@ -310,6 +314,8 @@ EventBits_t xEventGroupWaitBits( EventGroupHandle_t xEventGroup, BaseType_t xWaitConditionMet, xAlreadyYielded; BaseType_t xTimeoutOccurred = pdFALSE; + traceENTER_xEventGroupWaitBits( xEventGroup, uxBitsToWaitFor, xClearOnExit, xWaitForAllBits, xTicksToWait ); + /* Check the user is not attempting to wait on the bits used by the kernel * itself, and that at least one bit is being requested. */ configASSERT( xEventGroup ); @@ -395,7 +401,7 @@ EventBits_t xEventGroupWaitBits( EventGroupHandle_t xEventGroup, { if( xAlreadyYielded == pdFALSE ) { - portYIELD_WITHIN_API(); + taskYIELD_WITHIN_API(); } else { @@ -451,6 +457,8 @@ EventBits_t xEventGroupWaitBits( EventGroupHandle_t xEventGroup, /* Prevent compiler warnings when trace macros are not used. */ ( void ) xTimeoutOccurred; + traceRETURN_xEventGroupWaitBits( uxReturn ); + return uxReturn; } /*-----------------------------------------------------------*/ @@ -461,6 +469,8 @@ EventBits_t xEventGroupClearBits( EventGroupHandle_t xEventGroup, EventGroup_t * pxEventBits = xEventGroup; EventBits_t uxReturn; + traceENTER_xEventGroupClearBits( xEventGroup, uxBitsToClear ); + /* Check the user is not attempting to clear the bits used by the kernel * itself. */ configASSERT( xEventGroup ); @@ -479,6 +489,8 @@ EventBits_t xEventGroupClearBits( EventGroupHandle_t xEventGroup, } taskEXIT_CRITICAL(); + traceRETURN_xEventGroupClearBits( uxReturn ); + return uxReturn; } /*-----------------------------------------------------------*/ @@ -490,8 +502,12 @@ EventBits_t xEventGroupClearBits( EventGroupHandle_t xEventGroup, { BaseType_t xReturn; + traceENTER_xEventGroupClearBitsFromISR( xEventGroup, uxBitsToClear ); + traceEVENT_GROUP_CLEAR_BITS_FROM_ISR( xEventGroup, uxBitsToClear ); - xReturn = xTimerPendFunctionCallFromISR( vEventGroupClearBitsCallback, ( void * ) xEventGroup, ( uint32_t ) uxBitsToClear, NULL ); /*lint !e9087 Can't avoid cast to void* as a generic callback function not specific to this use case. Callback casts back to original type so safe. */ + xReturn = xTimerPendFunctionCallFromISR( vEventGroupClearBitsCallback, ( void * ) xEventGroup, ( uint32_t ) uxBitsToClear, NULL ); + + traceRETURN_xEventGroupClearBitsFromISR( xReturn ); return xReturn; } @@ -505,14 +521,18 @@ EventBits_t xEventGroupGetBitsFromISR( EventGroupHandle_t xEventGroup ) EventGroup_t const * const pxEventBits = xEventGroup; EventBits_t uxReturn; - uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR(); + traceENTER_xEventGroupGetBitsFromISR( xEventGroup ); + + uxSavedInterruptStatus = taskENTER_CRITICAL_FROM_ISR(); { uxReturn = pxEventBits->uxEventBits; } - portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus ); + taskEXIT_CRITICAL_FROM_ISR( uxSavedInterruptStatus ); + + traceRETURN_xEventGroupGetBitsFromISR( uxReturn ); return uxReturn; -} /*lint !e818 EventGroupHandle_t is a typedef used in other functions to so can't be pointer to const. */ +} /*-----------------------------------------------------------*/ EventBits_t xEventGroupSetBits( EventGroupHandle_t xEventGroup, @@ -526,13 +546,15 @@ EventBits_t xEventGroupSetBits( EventGroupHandle_t xEventGroup, EventGroup_t * pxEventBits = xEventGroup; BaseType_t xMatchFound = pdFALSE; + traceENTER_xEventGroupSetBits( xEventGroup, uxBitsToSet ); + /* Check the user is not attempting to set the bits used by the kernel * itself. */ configASSERT( xEventGroup ); configASSERT( ( uxBitsToSet & eventEVENT_BITS_CONTROL_BYTES ) == 0 ); pxList = &( pxEventBits->xTasksWaitingForBits ); - pxListEnd = listGET_END_MARKER( pxList ); /*lint !e826 !e740 !e9087 The mini list structure is used as the list end to save RAM. This is checked and valid. */ + pxListEnd = listGET_END_MARKER( pxList ); vTaskSuspendAll(); { traceEVENT_GROUP_SET_BITS( xEventGroup, uxBitsToSet ); @@ -607,6 +629,8 @@ EventBits_t xEventGroupSetBits( EventGroupHandle_t xEventGroup, } ( void ) xTaskResumeAll(); + traceRETURN_xEventGroupSetBits( pxEventBits->uxEventBits ); + return pxEventBits->uxEventBits; } /*-----------------------------------------------------------*/ @@ -616,6 +640,8 @@ void vEventGroupDelete( EventGroupHandle_t xEventGroup ) EventGroup_t * pxEventBits = xEventGroup; const List_t * pxTasksWaitingForBits; + traceENTER_vEventGroupDelete( xEventGroup ); + configASSERT( pxEventBits ); pxTasksWaitingForBits = &( pxEventBits->xTasksWaitingForBits ); @@ -654,6 +680,8 @@ void vEventGroupDelete( EventGroupHandle_t xEventGroup ) } } #endif /* configSUPPORT_DYNAMIC_ALLOCATION */ + + traceRETURN_vEventGroupDelete(); } /*-----------------------------------------------------------*/ @@ -664,6 +692,8 @@ void vEventGroupDelete( EventGroupHandle_t xEventGroup ) BaseType_t xReturn; EventGroup_t * pxEventBits = xEventGroup; + traceENTER_xEventGroupGetStaticBuffer( xEventGroup, ppxEventGroupBuffer ); + configASSERT( pxEventBits ); configASSERT( ppxEventGroupBuffer ); @@ -672,6 +702,9 @@ void vEventGroupDelete( EventGroupHandle_t xEventGroup ) /* Check if the event group was statically allocated. */ if( pxEventBits->ucStaticallyAllocated == ( uint8_t ) pdTRUE ) { + /* MISRA Ref 11.3.1 [Misaligned access] */ + /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-113 */ + /* coverity[misra_c_2012_rule_11_3_violation] */ *ppxEventGroupBuffer = ( StaticEventGroup_t * ) pxEventBits; xReturn = pdTRUE; } @@ -683,11 +716,16 @@ void vEventGroupDelete( EventGroupHandle_t xEventGroup ) #else /* configSUPPORT_DYNAMIC_ALLOCATION */ { /* Event group must have been statically allocated. */ + /* MISRA Ref 11.3.1 [Misaligned access] */ + /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-113 */ + /* coverity[misra_c_2012_rule_11_3_violation] */ *ppxEventGroupBuffer = ( StaticEventGroup_t * ) pxEventBits; xReturn = pdTRUE; } #endif /* configSUPPORT_DYNAMIC_ALLOCATION */ + traceRETURN_xEventGroupGetStaticBuffer( xReturn ); + return xReturn; } #endif /* configSUPPORT_STATIC_ALLOCATION */ @@ -696,18 +734,32 @@ void vEventGroupDelete( EventGroupHandle_t xEventGroup ) /* For internal use only - execute a 'set bits' command that was pended from * an interrupt. */ void vEventGroupSetBitsCallback( void * pvEventGroup, - const uint32_t ulBitsToSet ) + uint32_t ulBitsToSet ) { - ( void ) xEventGroupSetBits( pvEventGroup, ( EventBits_t ) ulBitsToSet ); /*lint !e9079 Can't avoid cast to void* as a generic timer callback prototype. Callback casts back to original type so safe. */ + traceENTER_vEventGroupSetBitsCallback( pvEventGroup, ulBitsToSet ); + + /* MISRA Ref 11.5.4 [Callback function parameter] */ + /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-115 */ + /* coverity[misra_c_2012_rule_11_5_violation] */ + ( void ) xEventGroupSetBits( pvEventGroup, ( EventBits_t ) ulBitsToSet ); + + traceRETURN_vEventGroupSetBitsCallback(); } /*-----------------------------------------------------------*/ /* For internal use only - execute a 'clear bits' command that was pended from * an interrupt. */ void vEventGroupClearBitsCallback( void * pvEventGroup, - const uint32_t ulBitsToClear ) + uint32_t ulBitsToClear ) { - ( void ) xEventGroupClearBits( pvEventGroup, ( EventBits_t ) ulBitsToClear ); /*lint !e9079 Can't avoid cast to void* as a generic timer callback prototype. Callback casts back to original type so safe. */ + traceENTER_vEventGroupClearBitsCallback( pvEventGroup, ulBitsToClear ); + + /* MISRA Ref 11.5.4 [Callback function parameter] */ + /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-115 */ + /* coverity[misra_c_2012_rule_11_5_violation] */ + ( void ) xEventGroupClearBits( pvEventGroup, ( EventBits_t ) ulBitsToClear ); + + traceRETURN_vEventGroupClearBitsCallback(); } /*-----------------------------------------------------------*/ @@ -756,8 +808,12 @@ static BaseType_t prvTestWaitCondition( const EventBits_t uxCurrentEventBits, { BaseType_t xReturn; + traceENTER_xEventGroupSetBitsFromISR( xEventGroup, uxBitsToSet, pxHigherPriorityTaskWoken ); + traceEVENT_GROUP_SET_BITS_FROM_ISR( xEventGroup, uxBitsToSet ); - xReturn = xTimerPendFunctionCallFromISR( vEventGroupSetBitsCallback, ( void * ) xEventGroup, ( uint32_t ) uxBitsToSet, pxHigherPriorityTaskWoken ); /*lint !e9087 Can't avoid cast to void* as a generic callback function not specific to this use case. Callback casts back to original type so safe. */ + xReturn = xTimerPendFunctionCallFromISR( vEventGroupSetBitsCallback, ( void * ) xEventGroup, ( uint32_t ) uxBitsToSet, pxHigherPriorityTaskWoken ); + + traceRETURN_xEventGroupSetBitsFromISR( xReturn ); return xReturn; } @@ -770,7 +826,13 @@ static BaseType_t prvTestWaitCondition( const EventBits_t uxCurrentEventBits, UBaseType_t uxEventGroupGetNumber( void * xEventGroup ) { UBaseType_t xReturn; - EventGroup_t const * pxEventBits = ( EventGroup_t * ) xEventGroup; /*lint !e9087 !e9079 EventGroupHandle_t is a pointer to an EventGroup_t, but EventGroupHandle_t is kept opaque outside of this file for data hiding purposes. */ + + /* MISRA Ref 11.5.2 [Opaque pointer] */ + /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-115 */ + /* coverity[misra_c_2012_rule_11_5_violation] */ + EventGroup_t const * pxEventBits = ( EventGroup_t * ) xEventGroup; + + traceENTER_uxEventGroupGetNumber( xEventGroup ); if( xEventGroup == NULL ) { @@ -781,6 +843,8 @@ static BaseType_t prvTestWaitCondition( const EventBits_t uxCurrentEventBits, xReturn = pxEventBits->uxEventGroupNumber; } + traceRETURN_uxEventGroupGetNumber( xReturn ); + return xReturn; } @@ -792,7 +856,14 @@ static BaseType_t prvTestWaitCondition( const EventBits_t uxCurrentEventBits, void vEventGroupSetNumber( void * xEventGroup, UBaseType_t uxEventGroupNumber ) { - ( ( EventGroup_t * ) xEventGroup )->uxEventGroupNumber = uxEventGroupNumber; /*lint !e9087 !e9079 EventGroupHandle_t is a pointer to an EventGroup_t, but EventGroupHandle_t is kept opaque outside of this file for data hiding purposes. */ + traceENTER_vEventGroupSetNumber( xEventGroup, uxEventGroupNumber ); + + /* MISRA Ref 11.5.2 [Opaque pointer] */ + /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-115 */ + /* coverity[misra_c_2012_rule_11_5_violation] */ + ( ( EventGroup_t * ) xEventGroup )->uxEventGroupNumber = uxEventGroupNumber; + + traceRETURN_vEventGroupSetNumber(); } #endif /* configUSE_TRACE_FACILITY */ diff --git a/Source/examples/cmake_example/CMakeLists.txt b/Source/examples/cmake_example/CMakeLists.txt new file mode 100644 index 000000000..bff9317de --- /dev/null +++ b/Source/examples/cmake_example/CMakeLists.txt @@ -0,0 +1,73 @@ +cmake_minimum_required(VERSION 3.15) + +project(example) + +set(FREERTOS_KERNEL_PATH "../../") + +# Add the freertos_config for FreeRTOS-Kernel +add_library(freertos_config INTERFACE) + +target_include_directories(freertos_config + INTERFACE + "../template_configuration" +) + +if (DEFINED FREERTOS_SMP_EXAMPLE AND FREERTOS_SMP_EXAMPLE STREQUAL "1") + message(STATUS "Build FreeRTOS SMP example") + # Adding the following configurations to build SMP template port + add_compile_options( -DconfigNUMBER_OF_CORES=2 -DconfigUSE_PASSIVE_IDLE_HOOK=0 ) +endif() + +# Select the heap port. values between 1-4 will pick a heap. +set(FREERTOS_HEAP "4" CACHE STRING "" FORCE) + +# Select the native compile PORT +set(FREERTOS_PORT "TEMPLATE" CACHE STRING "" FORCE) + +# Adding the FreeRTOS-Kernel subdirectory +add_subdirectory(${FREERTOS_KERNEL_PATH} FreeRTOS-Kernel) + +######################################################################## +# Overall Compile Options +# Note the compile option strategy is to error on everything and then +# Per library opt-out of things that are warnings/errors. +# This ensures that no matter what strategy for compilation you take, the +# builds will still occur. +# +# Only tested with GNU and Clang. +# Other options are https://cmake.org/cmake/help/latest/variable/CMAKE_LANG_COMPILER_ID.html#variable:CMAKE_%3CLANG%3E_COMPILER_ID +# Naming of compilers translation map: +# +# FreeRTOS | CMake +# ------------------- +# CCS | ?TBD? +# GCC | GNU, Clang, *Clang Others? +# IAR | IAR +# Keil | ARMCC +# MSVC | MSVC # Note only for MinGW? +# Renesas | ?TBD? + +target_compile_options(freertos_kernel PRIVATE + ### Gnu/Clang C Options + $<$:-fdiagnostics-color=always> + $<$:-fcolor-diagnostics> + + $<$:-Wall> + $<$:-Wextra> + $<$:-Wpedantic> + $<$:-Werror> + $<$:-Wconversion> + $<$:-Weverything> + + # Suppressions required to build clean with clang. + $<$:-Wno-unused-macros> + $<$:-Wno-padded> + $<$:-Wno-missing-variable-declarations> + $<$:-Wno-covered-switch-default> + $<$:-Wno-cast-align> ) + +add_executable(${PROJECT_NAME} + main.c +) + +target_link_libraries(${PROJECT_NAME} freertos_kernel freertos_config) diff --git a/Source/examples/cmake_example/main.c b/Source/examples/cmake_example/main.c new file mode 100644 index 000000000..f7985489e --- /dev/null +++ b/Source/examples/cmake_example/main.c @@ -0,0 +1,92 @@ +/* + * FreeRTOS Kernel V11.0.1 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* + * This is a simple main that will start the FreeRTOS-Kernel and run a periodic task + * that only delays if compiled with the template port, this project will do nothing. + * For more information on getting started please look here: + * https://freertos.org/FreeRTOS-quick-start-guide.html + */ + +/* FreeRTOS includes. */ +#include +#include +#include +#include +#include + +/* Standard includes. */ +#include + +void exampleTask( void * parameters ) +{ + /* Unused parameters. */ + ( void ) parameters; + + for( ; ; ) + { + /* Example Task Code */ + vTaskDelay( 100 ); /* delay 100 ticks */ + } +} +/*-----------------------------------------------------------*/ + +void main( void ) +{ + static StaticTask_t exampleTaskTCB; + static StackType_t exampleTaskStack[ configMINIMAL_STACK_SIZE ]; + + printf( "Example FreeRTOS Project\n" ); + + xTaskCreateStatic( exampleTask, + "example", + configMINIMAL_STACK_SIZE, + NULL, + configMAX_PRIORITIES - 1, + &( exampleTaskStack[ 0 ] ), + &( exampleTaskTCB ) ); + + /* Start the scheduler. */ + vTaskStartScheduler(); + + for( ; ; ) + { + /* Should not reach here. */ + } +} +/*-----------------------------------------------------------*/ + +void vApplicationStackOverflowHook( TaskHandle_t xTask, + char * pcTaskName ) +{ + /* Check pcTaskName for the name of the offending task, + * or pxCurrentTCB if pcTaskName has itself been corrupted. */ + ( void ) xTask; + ( void ) pcTaskName; +} +/*-----------------------------------------------------------*/ diff --git a/Source/examples/coverity/CMakeLists.txt b/Source/examples/coverity/CMakeLists.txt new file mode 100644 index 000000000..b4538655e --- /dev/null +++ b/Source/examples/coverity/CMakeLists.txt @@ -0,0 +1,39 @@ +cmake_minimum_required(VERSION 3.15) + +project(coverity) + +set(FREERTOS_KERNEL_PATH "../../") +FILE(GLOB FREERTOS_KERNEL_SOURCE ${FREERTOS_KERNEL_PATH}*.c) + +# Coverity incorrectly infers the type of pdTRUE and pdFALSE as boolean because +# of their names. This generates multiple false positive warnings about type +# mismatch. Replace pdTRUE with pdPASS and pdFALSE with pdFAIL to avoid these +# false positive warnings. This workaround will not be needed after Coverity +# fixes the issue of incorrectly inferring the type of pdTRUE and pdFALSE as +# boolean. +add_custom_target(fix_source ALL + COMMAND sed -i -b -e 's/pdFALSE/pdFAIL/g' -e 's/pdTRUE/pdPASS/g' ${FREERTOS_KERNEL_SOURCE} + DEPENDS ${FREERTOS_KERNEL_SOURCE}) + +# Add the freertos_config for FreeRTOS-Kernel. +add_library(freertos_config INTERFACE) + +target_include_directories(freertos_config + INTERFACE + ./) + +# Select the heap. Values between 1-5 will pick a heap. +set(FREERTOS_HEAP "3" CACHE STRING "" FORCE) + +# Select the FreeRTOS port. +set(FREERTOS_PORT "TEMPLATE" CACHE STRING "" FORCE) + +# Add the FreeRTOS-Kernel subdirectory. +add_subdirectory(${FREERTOS_KERNEL_PATH} FreeRTOS-Kernel) + +add_executable(${PROJECT_NAME} + ../cmake_example/main.c) + +add_dependencies(${PROJECT_NAME} fix_source) + +target_link_libraries(${PROJECT_NAME} freertos_kernel freertos_config) diff --git a/Source/examples/coverity/FreeRTOSConfig.h b/Source/examples/coverity/FreeRTOSConfig.h new file mode 100644 index 000000000..a445dc943 --- /dev/null +++ b/Source/examples/coverity/FreeRTOSConfig.h @@ -0,0 +1,135 @@ +/* + * FreeRTOS Kernel V11.0.1 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef FREERTOS_CONFIG_H +#define FREERTOS_CONFIG_H + +/******************************************************************************/ +/* Hardware description related definitions. **********************************/ +/******************************************************************************/ + +#define configCPU_CLOCK_HZ ( ( unsigned long ) 20000000 ) + +/******************************************************************************/ +/* Scheduling behaviour related definitions. **********************************/ +/******************************************************************************/ + +#define configTICK_RATE_HZ ( 100U ) +#define configUSE_PREEMPTION 1 +#define configUSE_TIME_SLICING 1 +#define configUSE_PORT_OPTIMISED_TASK_SELECTION 0 +#define configUSE_TICKLESS_IDLE 1 +#define configMAX_PRIORITIES 5U +#define configMINIMAL_STACK_SIZE 128U +#define configMAX_TASK_NAME_LEN 4U +#define configTICK_TYPE_WIDTH_IN_BITS TICK_TYPE_WIDTH_64_BITS +#define configIDLE_SHOULD_YIELD 1 +#define configTASK_NOTIFICATION_ARRAY_ENTRIES 1U +#define configQUEUE_REGISTRY_SIZE 0U +#define configENABLE_BACKWARD_COMPATIBILITY 1 +#define configNUM_THREAD_LOCAL_STORAGE_POINTERS 0 +#define configSTACK_DEPTH_TYPE size_t +#define configMESSAGE_BUFFER_LENGTH_TYPE size_t +#define configUSE_NEWLIB_REENTRANT 0 + +/******************************************************************************/ +/* Software timer related definitions. ****************************************/ +/******************************************************************************/ + +#define configUSE_TIMERS 1 +#define configTIMER_TASK_PRIORITY ( configMAX_PRIORITIES - 1U ) +#define configTIMER_TASK_STACK_DEPTH configMINIMAL_STACK_SIZE +#define configTIMER_QUEUE_LENGTH 10U + +/******************************************************************************/ +/* Memory allocation related definitions. *************************************/ +/******************************************************************************/ + +#define configSUPPORT_STATIC_ALLOCATION 1 +#define configSUPPORT_DYNAMIC_ALLOCATION 1 +#define configTOTAL_HEAP_SIZE 4096U +#define configAPPLICATION_ALLOCATED_HEAP 1 +#define configSTACK_ALLOCATION_FROM_SEPARATE_HEAP 0 +#define configUSE_MINI_LIST_ITEM 0 + +/******************************************************************************/ +/* Interrupt nesting behaviour configuration. *********************************/ +/******************************************************************************/ + +#define configKERNEL_INTERRUPT_PRIORITY 0U +#define configMAX_SYSCALL_INTERRUPT_PRIORITY 0U +#define configMAX_API_CALL_INTERRUPT_PRIORITY 0U + +/******************************************************************************/ +/* Hook and callback function related definitions. ****************************/ +/******************************************************************************/ + +#define configUSE_IDLE_HOOK 0 +#define configUSE_TICK_HOOK 0 +#define configUSE_MALLOC_FAILED_HOOK 0 +#define configUSE_DAEMON_TASK_STARTUP_HOOK 0 +#define configCHECK_FOR_STACK_OVERFLOW 0 + +/******************************************************************************/ +/* Run time and task stats gathering related definitions. *********************/ +/******************************************************************************/ + +#define configGENERATE_RUN_TIME_STATS 0 +#define configUSE_TRACE_FACILITY 0 +#define configUSE_STATS_FORMATTING_FUNCTIONS 0 +#define configKERNEL_PROVIDED_STATIC_MEMORY 1 + +/******************************************************************************/ +/* Definitions that include or exclude functionality. *************************/ +/******************************************************************************/ + +#define configUSE_TASK_NOTIFICATIONS 1 +#define configUSE_MUTEXES 1 +#define configUSE_RECURSIVE_MUTEXES 1 +#define configUSE_COUNTING_SEMAPHORES 1 +#define configUSE_QUEUE_SETS 1 +#define configUSE_APPLICATION_TASK_TAG 1 +#define INCLUDE_vTaskPrioritySet 1 +#define INCLUDE_uxTaskPriorityGet 1 +#define INCLUDE_vTaskDelete 1 +#define INCLUDE_vTaskSuspend 1 +#define INCLUDE_xResumeFromISR 1 +#define INCLUDE_vTaskDelayUntil 1 +#define INCLUDE_vTaskDelay 1 +#define INCLUDE_xTaskGetSchedulerState 1 +#define INCLUDE_xTaskGetCurrentTaskHandle 1 +#define INCLUDE_uxTaskGetStackHighWaterMark 1 +#define INCLUDE_xTaskGetIdleTaskHandle 1 +#define INCLUDE_eTaskGetState 1 +#define INCLUDE_xEventGroupSetBitFromISR 1 +#define INCLUDE_xTimerPendFunctionCall 1 +#define INCLUDE_xTaskAbortDelay 1 +#define INCLUDE_xTaskGetHandle 1 +#define INCLUDE_xTaskResumeFromISR 1 + +#endif /* FREERTOS_CONFIG_H */ diff --git a/Source/examples/coverity/README.md b/Source/examples/coverity/README.md new file mode 100644 index 000000000..0daed7b22 --- /dev/null +++ b/Source/examples/coverity/README.md @@ -0,0 +1,58 @@ +# MISRA Compliance for FreeRTOS-Kernel +FreeRTOS-Kernel is MISRA C:2012 compliant. This directory contains a project to +run [Synopsys Coverity](https://www.synopsys.com/software-integrity/security-testing/static-analysis-sast.html) +for checking MISRA compliance. + +> **Note** +Coverity version 2022.6.1 incorrectly infers the type of `pdTRUE` and `pdFALSE` +as boolean because of their names, resulting in multiple false positive warnings +about type mismatch. We replace `pdTRUE` with `pdPASS` and `pdFALSE` with +`pdFAIL` to avoid these false positive warnings. This workaround will not be +needed after Coverity fixes the issue of incorrectly inferring the type of +`pdTRUE` and `pdFALSE` as boolean. + +Deviations from the MISRA C:2012 guidelines are documented in +[MISRA.md](../../MISRA.md) and [coverity_misra.config](coverity_misra.config) +files. + +## Getting Started +### Prerequisites +Coverity can be run on any platform mentioned [here](https://sig-docs.synopsys.com/polaris/topics/c_coverity-compatible-platforms.html). +The following are the prerequisites to generate coverity report: + +1. CMake version > 3.13.0 (You can check whether you have this by typing `cmake --version`). +2. GCC compiler. + - See download and installation instructions [here](https://gcc.gnu.org/install/). +3. Clone the repo using the following command: + - `git clone https://github.com/FreeRTOS/FreeRTOS-Kernel.git ./FreeRTOS-Kernel` + +### Generating Report +Go to the root directory of the FreeRTOS-Kernel repo and run the following +commands in a terminal: +1. Update the compiler configuration in Coverity: + ~~~ + cov-configure --force --compiler cc --comptype gcc + ~~~ +2. Create the build files using CMake in a `build` directory: + ~~~ + cmake -B build -S examples/coverity + ~~~ +3. Build the (pseudo) application: + ~~~ + cd build/ + cov-build --emit-complementary-info --dir cov-out make + ~~~ +4. Go to the Coverity output directory (`cov-out`) and begin Coverity static + analysis: + ~~~ + cd cov-out/ + cov-analyze --dir ./cov-out \ + --coding-standard-config ../examples/coverity/coverity_misra.config \ + --tu-pattern "file('.*/FreeRTOS/Source/[A-Za-z_]*\.c') + ~~~ +5. Generate the HTML report: + ~~~ + cov-format-errors --dir ./cov-out --html-output html-output + ~~~ + +HTML report should now be generated in a directory named `html-output`. diff --git a/Source/examples/coverity/coverity_misra.config b/Source/examples/coverity/coverity_misra.config new file mode 100644 index 000000000..101b20031 --- /dev/null +++ b/Source/examples/coverity/coverity_misra.config @@ -0,0 +1,97 @@ +// MISRA C-2012 Rules + +{ + version : "2.0", + standard : "c2012", + title: "Coverity MISRA Configuration", + deviations : [ + // Disable the following rules. + { + deviation: "Rule 3.1", + reason: "We post HTTP links in code comments which contain // inside comments blocks." + }, + { + deviation: "Rule 14.4", + reason: "do while( 0 ) pattern is used in macros to prevent extra semi-colon." + }, + + // Disable the following advisory rules and directives. + { + deviation: "Directive 4.4", + reason: "Code snippet is used in comment to help explanation." + }, + { + deviation: "Directive 4.5", + reason: "Allow names that MISRA considers ambiguous." + }, + { + deviation: "Directive 4.6", + reason: "Allow port to use primitive type with typedefs." + }, + { + deviation: "Directive 4.8", + reason: "HeapRegion_t and HeapStats_t are used only in heap files but declared in portable.h which is included in multiple source files. As a result, these definitions appear in multiple source files where they are not used." + }, + { + deviation: "Directive 4.9", + reason: "FreeRTOS-Kernel is optimised to work on small micro-controllers. To achieve that, function-like macros are used." + }, + { + deviation: "Rule 2.3", + reason: "FreeRTOS defines types which is used in application." + }, + { + deviation: "Rule 2.4", + reason: "Allow to define unused tag." + }, + { + deviation: "Rule 2.5", + reason: "Allow to define unused macro." + }, + { + deviation: "Rule 5.9", + reason: "Allow to define identifier with the same name in structure and global variable." + }, + { + deviation: "Rule 8.7", + reason: "API functions are not used by the library outside of the files they are defined; however, they must be externally visible in order to be used by an application." + }, + { + deviation: "Rule 8.9", + reason: "Allow to object to be defined in wider scope for debug purpose." + }, + { + deviation: "Rule 8.13", + reason: "Allow to not to use const-qualified type for callback function." + }, + { + deviation: "Rule 11.4", + reason: "Allow to convert between a pointer to object and an interger type for stack alignment." + }, + { + deviation: "Rule 15.4", + reason: "Allow to use multiple break statements in a loop." + }, + { + deviation: "Rule 15.5", + reason: "Allow to use multiple points of exit." + }, + { + deviation: "Rule 17.8", + reason: "Allow to update the parameters of a function." + }, + { + deviation: "Rule 18.4", + reason: "Allow to use pointer arithmetic." + }, + { + deviation: "Rule 19.2", + reason: "Allow to use union." + }, + { + deviation: "Rule 20.5", + reason: "Allow to use #undef for MPU wrappers." + } + ] +} + diff --git a/Source/examples/template_configuration/FreeRTOSConfig.h b/Source/examples/template_configuration/FreeRTOSConfig.h new file mode 100644 index 000000000..f763c1c99 --- /dev/null +++ b/Source/examples/template_configuration/FreeRTOSConfig.h @@ -0,0 +1,568 @@ +/* + * FreeRTOS Kernel V11.0.1 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/******************************************************************************* + * This file provides an example FreeRTOSConfig.h header file, inclusive of an + * abbreviated explanation of each configuration item. Online and reference + * documentation provides more information. + * https://www.freertos.org/a00110.html + * + * Constant values enclosed in square brackets ('[' and ']') must be completed + * before this file will build. + * + * Use the FreeRTOSConfig.h supplied with the RTOS port in use rather than this + * generic file, if one is available. + ******************************************************************************/ + +#ifndef FREERTOS_CONFIG_H +#define FREERTOS_CONFIG_H + +/******************************************************************************/ +/* Hardware description related definitions. **********************************/ +/******************************************************************************/ + +/* In most cases, configCPU_CLOCK_HZ must be set to the frequency of the clock + * that drives the peripheral used to generate the kernels periodic tick interrupt. + * The default value is set to 20MHz and matches the QEMU demo settings. Your + * application will certainly need a different value so set this correctly. + * This is very often, but not always, equal to the main system clock frequency. */ +#define configCPU_CLOCK_HZ ( ( unsigned long ) 20000000 ) + +/* configSYSTICK_CLOCK_HZ is an optional parameter for ARM Cortex-M ports only. + * + * By default ARM Cortex-M ports generate the RTOS tick interrupt from the + * Cortex-M SysTick timer. Most Cortex-M MCUs run the SysTick timer at the same + * frequency as the MCU itself - when that is the case configSYSTICK_CLOCK_HZ is + * not needed and should be left undefined. If the SysTick timer is clocked at a + * different frequency to the MCU core then set configCPU_CLOCK_HZ to the MCU clock + * frequency, as normal, and configSYSTICK_CLOCK_HZ to the SysTick clock + * frequency. Not used if left undefined. + * The default value is undefined (commented out). If you need this value bring it + * back and set it to a suitable value. */ + +/* + #define configSYSTICK_CLOCK_HZ [Platform specific] + */ + +/******************************************************************************/ +/* Scheduling behaviour related definitions. **********************************/ +/******************************************************************************/ + +/* configTICK_RATE_HZ sets frequency of the tick interrupt in Hz, normally + * calculated from the configCPU_CLOCK_HZ value. */ +#define configTICK_RATE_HZ 100 + +/* Set configUSE_PREEMPTION to 1 to use pre-emptive scheduling. Set + * configUSE_PREEMPTION to 0 to use co-operative scheduling. + * See https://www.freertos.org/single-core-amp-smp-rtos-scheduling.html. */ +#define configUSE_PREEMPTION 1 + +/* Set configUSE_TIME_SLICING to 1 to have the scheduler switch between Ready + * state tasks of equal priority on every tick interrupt. Set + * configUSE_TIME_SLICING to 0 to prevent the scheduler switching between Ready + * state tasks just because there was a tick interrupt. See + * https://freertos.org/single-core-amp-smp-rtos-scheduling.html. */ +#define configUSE_TIME_SLICING 0 + +/* Set configUSE_PORT_OPTIMISED_TASK_SELECTION to 1 to select the next task to + * run using an algorithm optimised to the instruction set of the target hardware - + * normally using a count leading zeros assembly instruction. Set to 0 to select + * the next task to run using a generic C algorithm that works for all FreeRTOS + * ports. Not all FreeRTOS ports have this option. Defaults to 0 if left + * undefined. */ +#define configUSE_PORT_OPTIMISED_TASK_SELECTION 0 + +/* Set configUSE_TICKLESS_IDLE to 1 to use the low power tickless mode. Set to + * 0 to keep the tick interrupt running at all times. Not all FreeRTOS ports + * support tickless mode. See https://www.freertos.org/low-power-tickless-rtos.html + * Defaults to 0 if left undefined. */ +#define configUSE_TICKLESS_IDLE 0 + +/* configMAX_PRIORITIES Sets the number of available task priorities. Tasks can + * be assigned priorities of 0 to (configMAX_PRIORITIES - 1). Zero is the lowest + * priority. */ +#define configMAX_PRIORITIES 5 + +/* configMINIMAL_STACK_SIZE defines the size of the stack used by the Idle task + * (in words, not in bytes!). The kernel does not use this constant for any other + * purpose. Demo applications use the constant to make the demos somewhat portable + * across hardware architectures. */ +#define configMINIMAL_STACK_SIZE 128 + +/* configMAX_TASK_NAME_LEN sets the maximum length (in characters) of a task's + * human readable name. Includes the NULL terminator. */ +#define configMAX_TASK_NAME_LEN 16 + +/* Time is measured in 'ticks' - which is the number of times the tick interrupt + * has executed since the RTOS kernel was started. + * The tick count is held in a variable of type TickType_t. + * + * configTICK_TYPE_WIDTH_IN_BITS controls the type (and therefore bit-width) of TickType_t: + * + * Defining configTICK_TYPE_WIDTH_IN_BITS as TICK_TYPE_WIDTH_16_BITS causes + * TickType_t to be defined (typedef'ed) as an unsigned 16-bit type. + * + * Defining configTICK_TYPE_WIDTH_IN_BITS as TICK_TYPE_WIDTH_32_BITS causes + * TickType_t to be defined (typedef'ed) as an unsigned 32-bit type. + * + * Defining configTICK_TYPE_WIDTH_IN_BITS as TICK_TYPE_WIDTH_64_BITS causes + * TickType_t to be defined (typedef'ed) as an unsigned 64-bit type. */ +#define configTICK_TYPE_WIDTH_IN_BITS TICK_TYPE_WIDTH_64_BITS + +/* Set configIDLE_SHOULD_YIELD to 1 to have the Idle task yield to an + * application task if there is an Idle priority (priority 0) application task that + * can run. Set to 0 to have the Idle task use all of its timeslice. Default to 1 + * if left undefined. */ +#define configIDLE_SHOULD_YIELD 1 + +/* Each task has an array of task notifications. + * configTASK_NOTIFICATION_ARRAY_ENTRIES sets the number of indexes in the array. + * See https://www.freertos.org/RTOS-task-notifications.html Defaults to 1 if + * left undefined. */ +#define configTASK_NOTIFICATION_ARRAY_ENTRIES 1 + +/* configQUEUE_REGISTRY_SIZE sets the maximum number of queues and semaphores + * that can be referenced from the queue registry. Only required when using a + * kernel aware debugger. Defaults to 0 if left undefined. */ +#define configQUEUE_REGISTRY_SIZE 0 + +/* Set configENABLE_BACKWARD_COMPATIBILITY to 1 to map function names and + * datatypes from old version of FreeRTOS to their latest equivalent. Defaults to + * 1 if left undefined. */ +#define configENABLE_BACKWARD_COMPATIBILITY 0 + +/* Each task has its own array of pointers that can be used as thread local + * storage. configNUM_THREAD_LOCAL_STORAGE_POINTERS set the number of indexes in + * the array. See https://www.freertos.org/thread-local-storage-pointers.html + * Defaults to 0 if left undefined. */ +#define configNUM_THREAD_LOCAL_STORAGE_POINTERS 0 + +/* When configUSE_MINI_LIST_ITEM is set to 0, MiniListItem_t and ListItem_t are + * both the same. When configUSE_MINI_LIST_ITEM is set to 1, MiniListItem_t contains + * 3 fewer fields than ListItem_t which saves some RAM at the cost of violating + * strict aliasing rules which some compilers depend on for optimization. Defaults + * to 1 if left undefined. */ +#define configUSE_MINI_LIST_ITEM 1 + +/* Sets the type used by the parameter to xTaskCreate() that specifies the stack + * size of the task being created. The same type is used to return information + * about stack usage in various other API calls. Defaults to size_t if left + * undefined. */ +#define configSTACK_DEPTH_TYPE size_t + +/* configMESSAGE_BUFFER_LENGTH_TYPE sets the type used to store the length of + * each message written to a FreeRTOS message buffer (the length is also written to + * the message buffer. Defaults to size_t if left undefined - but that may waste + * space if messages never go above a length that could be held in a uint8_t. */ +#define configMESSAGE_BUFFER_LENGTH_TYPE size_t + +/* If configHEAP_CLEAR_MEMORY_ON_FREE is set to 1, then blocks of memory allocated + * using pvPortMalloc() will be cleared (i.e. set to zero) when freed using + * vPortFree(). Defaults to 0 if left undefined. */ +#define configHEAP_CLEAR_MEMORY_ON_FREE 1 + +/* vTaskList and vTaskGetRunTimeStats APIs take a buffer as a parameter and assume + * that the length of the buffer is configSTATS_BUFFER_MAX_LENGTH. Defaults to + * 0xFFFF if left undefined. + * New applications are recommended to use vTaskListTasks and + * vTaskGetRunTimeStatistics APIs instead and supply the length of the buffer + * explicitly to avoid memory corruption. */ +#define configSTATS_BUFFER_MAX_LENGTH 0xFFFF + +/* Set configUSE_NEWLIB_REENTRANT to 1 to have a newlib reent structure + * allocated for each task. Set to 0 to not support newlib reent structures. + * Default to 0 if left undefined. + * + * Note Newlib support has been included by popular demand, but is not used or + * tested by the FreeRTOS maintainers themselves. FreeRTOS is not responsible for + * resulting newlib operation. User must be familiar with newlib and must provide + * system-wide implementations of the necessary stubs. Note that (at the time of + * writing) the current newlib design implements a system-wide malloc() that must + * be provided with locks. */ +#define configUSE_NEWLIB_REENTRANT 0 + +/******************************************************************************/ +/* Software timer related definitions. ****************************************/ +/******************************************************************************/ + +/* Set configUSE_TIMERS to 1 to include software timer functionality in the + * build. Set to 0 to exclude software timer functionality from the build. The + * FreeRTOS/source/timers.c source file must be included in the build if + * configUSE_TIMERS is set to 1. Default to 0 if left undefined. See + * https://www.freertos.org/RTOS-software-timer.html. */ +#define configUSE_TIMERS 1 + +/* configTIMER_TASK_PRIORITY sets the priority used by the timer task. Only + * used if configUSE_TIMERS is set to 1. The timer task is a standard FreeRTOS + * task, so its priority is set like any other task. See + * https://www.freertos.org/RTOS-software-timer-service-daemon-task.html Only used + * if configUSE_TIMERS is set to 1. */ +#define configTIMER_TASK_PRIORITY ( configMAX_PRIORITIES - 1 ) + +/* configTIMER_TASK_STACK_DEPTH sets the size of the stack allocated to the + * timer task (in words, not in bytes!). The timer task is a standard FreeRTOS + * task. See https://www.freertos.org/RTOS-software-timer-service-daemon-task.html + * Only used if configUSE_TIMERS is set to 1. */ +#define configTIMER_TASK_STACK_DEPTH configMINIMAL_STACK_SIZE + +/* configTIMER_QUEUE_LENGTH sets the length of the queue (the number of discrete + * items the queue can hold) used to send commands to the timer task. See + * https://www.freertos.org/RTOS-software-timer-service-daemon-task.html Only used + * if configUSE_TIMERS is set to 1. */ +#define configTIMER_QUEUE_LENGTH 10 + +/******************************************************************************/ +/* Memory allocation related definitions. *************************************/ +/******************************************************************************/ + +/* Set configSUPPORT_STATIC_ALLOCATION to 1 to include FreeRTOS API functions + * that create FreeRTOS objects (tasks, queues, etc.) using statically allocated + * memory in the build. Set to 0 to exclude the ability to create statically + * allocated objects from the build. Defaults to 0 if left undefined. See + * https://www.freertos.org/Static_Vs_Dynamic_Memory_Allocation.html. */ +#define configSUPPORT_STATIC_ALLOCATION 1 + +/* Set configSUPPORT_DYNAMIC_ALLOCATION to 1 to include FreeRTOS API functions + * that create FreeRTOS objects (tasks, queues, etc.) using dynamically allocated + * memory in the build. Set to 0 to exclude the ability to create dynamically + * allocated objects from the build. Defaults to 1 if left undefined. See + * https://www.freertos.org/Static_Vs_Dynamic_Memory_Allocation.html. */ +#define configSUPPORT_DYNAMIC_ALLOCATION 1 + +/* Sets the total size of the FreeRTOS heap, in bytes, when heap_1.c, heap_2.c + * or heap_4.c are included in the build. This value is defaulted to 4096 bytes but + * it must be tailored to each application. Note the heap will appear in the .bss + * section. See https://www.freertos.org/a00111.html. */ +#define configTOTAL_HEAP_SIZE 4096 + +/* Set configAPPLICATION_ALLOCATED_HEAP to 1 to have the application allocate + * the array used as the FreeRTOS heap. Set to 0 to have the linker allocate the + * array used as the FreeRTOS heap. Defaults to 0 if left undefined. */ +#define configAPPLICATION_ALLOCATED_HEAP 0 + +/* Set configSTACK_ALLOCATION_FROM_SEPARATE_HEAP to 1 to have task stacks + * allocated from somewhere other than the FreeRTOS heap. This is useful if you + * want to ensure stacks are held in fast memory. Set to 0 to have task stacks + * come from the standard FreeRTOS heap. The application writer must provide + * implementations for pvPortMallocStack() and vPortFreeStack() if set to 1. + * Defaults to 0 if left undefined. */ +#define configSTACK_ALLOCATION_FROM_SEPARATE_HEAP 0 + +/* Set configENABLE_HEAP_PROTECTOR to 1 to enable bounds checking and obfuscation + * to internal heap block pointers in heap_4.c and heap_5.c to help catch pointer + * corruptions. Defaults to 0 if left undefined. */ +#define configENABLE_HEAP_PROTECTOR 0 + +/******************************************************************************/ +/* Interrupt nesting behaviour configuration. *********************************/ +/******************************************************************************/ + +/* configKERNEL_INTERRUPT_PRIORITY sets the priority of the tick and context + * switch performing interrupts. The default value is set to the highest interrupt + * priority (0). Not supported by all FreeRTOS ports. See + * https://www.freertos.org/RTOS-Cortex-M3-M4.html for information specific to ARM + * Cortex-M devices. */ +#define configKERNEL_INTERRUPT_PRIORITY 0 + +/* configMAX_SYSCALL_INTERRUPT_PRIORITY sets the interrupt priority above which + * FreeRTOS API calls must not be made. Interrupts above this priority are never + * disabled, so never delayed by RTOS activity. The default value is set to the + * highest interrupt priority (0). Not supported by all FreeRTOS ports. + * See https://www.freertos.org/RTOS-Cortex-M3-M4.html for information specific to + * ARM Cortex-M devices. */ +#define configMAX_SYSCALL_INTERRUPT_PRIORITY 0 + +/* Another name for configMAX_SYSCALL_INTERRUPT_PRIORITY - the name used depends + * on the FreeRTOS port. */ +#define configMAX_API_CALL_INTERRUPT_PRIORITY 0 + +/******************************************************************************/ +/* Hook and callback function related definitions. ****************************/ +/******************************************************************************/ + +/* Set the following configUSE_* constants to 1 to include the named hook + * functionality in the build. Set to 0 to exclude the hook functionality from the + * build. The application writer is responsible for providing the hook function + * for any set to 1. See https://www.freertos.org/a00016.html. */ +#define configUSE_IDLE_HOOK 0 +#define configUSE_TICK_HOOK 0 +#define configUSE_MALLOC_FAILED_HOOK 0 +#define configUSE_DAEMON_TASK_STARTUP_HOOK 0 + +/* Set configUSE_SB_COMPLETED_CALLBACK to 1 to have send and receive completed + * callbacks for each instance of a stream buffer or message buffer. When the + * option is set to 1, APIs xStreamBufferCreateWithCallback() and + * xStreamBufferCreateStaticWithCallback() (and likewise APIs for message + * buffer) can be used to create a stream buffer or message buffer instance + * with application provided callbacks. Defaults to 0 if left undefined. */ +#define configUSE_SB_COMPLETED_CALLBACK 0 + +/* Set configCHECK_FOR_STACK_OVERFLOW to 1 or 2 for FreeRTOS to check for a + * stack overflow at the time of a context switch. Set to 0 to not look for a + * stack overflow. If configCHECK_FOR_STACK_OVERFLOW is 1 then the check only + * looks for the stack pointer being out of bounds when a task's context is saved + * to its stack - this is fast but somewhat ineffective. If + * configCHECK_FOR_STACK_OVERFLOW is 2 then the check looks for a pattern written + * to the end of a task's stack having been overwritten. This is slower, but will + * catch most (but not all) stack overflows. The application writer must provide + * the stack overflow callback when configCHECK_FOR_STACK_OVERFLOW is set to 1. + * See https://www.freertos.org/Stacks-and-stack-overflow-checking.html Defaults + * to 0 if left undefined. */ +#define configCHECK_FOR_STACK_OVERFLOW 2 + +/******************************************************************************/ +/* Run time and task stats gathering related definitions. *********************/ +/******************************************************************************/ + +/* Set configGENERATE_RUN_TIME_STATS to 1 to have FreeRTOS collect data on the + * processing time used by each task. Set to 0 to not collect the data. The + * application writer needs to provide a clock source if set to 1. Defaults to 0 + * if left undefined. See https://www.freertos.org/rtos-run-time-stats.html. */ +#define configGENERATE_RUN_TIME_STATS 0 + +/* Set configUSE_TRACE_FACILITY to include additional task structure members + * are used by trace and visualisation functions and tools. Set to 0 to exclude + * the additional information from the structures. Defaults to 0 if left + * undefined. */ +#define configUSE_TRACE_FACILITY 0 + +/* Set to 1 to include the vTaskList() and vTaskGetRunTimeStats() functions in + * the build. Set to 0 to exclude these functions from the build. These two + * functions introduce a dependency on string formatting functions that would + * otherwise not exist - hence they are kept separate. Defaults to 0 if left + * undefined. */ +#define configUSE_STATS_FORMATTING_FUNCTIONS 0 + +/******************************************************************************/ +/* Co-routine related definitions. ********************************************/ +/******************************************************************************/ + +/* Set configUSE_CO_ROUTINES to 1 to include co-routine functionality in the + * build, or 0 to omit co-routine functionality from the build. To include + * co-routines, croutine.c must be included in the project. Defaults to 0 if left + * undefined. */ +#define configUSE_CO_ROUTINES 0 + +/* configMAX_CO_ROUTINE_PRIORITIES defines the number of priorities available + * to the application co-routines. Any number of co-routines can share the same + * priority. Defaults to 0 if left undefined. */ +#define configMAX_CO_ROUTINE_PRIORITIES 1 + +/******************************************************************************/ +/* Debugging assistance. ******************************************************/ +/******************************************************************************/ + +/* configASSERT() has the same semantics as the standard C assert(). It can + * either be defined to take an action when the assertion fails, or not defined + * at all (i.e. comment out or delete the definitions) to completely remove + * assertions. configASSERT() can be defined to anything you want, for example + * you can call a function if an assert fails that passes the filename and line + * number of the failing assert (for example, "vAssertCalled( __FILE__, __LINE__ )" + * or it can simple disable interrupts and sit in a loop to halt all execution + * on the failing line for viewing in a debugger. */ +#define configASSERT( x ) \ + if( ( x ) == 0 ) \ + { \ + taskDISABLE_INTERRUPTS(); \ + for( ; ; ) \ + ; \ + } + +/******************************************************************************/ +/* FreeRTOS MPU specific definitions. *****************************************/ +/******************************************************************************/ + +/* If configINCLUDE_APPLICATION_DEFINED_PRIVILEGED_FUNCTIONS is set to 1 then + * the application writer can provide functions that execute in privileged mode. + * See: https://www.freertos.org/a00110.html#configINCLUDE_APPLICATION_DEFINED_PRIVILEGED_FUNCTIONS + * Defaults to 0 if left undefined. Only used by the FreeRTOS Cortex-M MPU ports, + * not the standard ARMv7-M Cortex-M port. */ +#define configINCLUDE_APPLICATION_DEFINED_PRIVILEGED_FUNCTIONS 0 + +/* Set configTOTAL_MPU_REGIONS to the number of MPU regions implemented on your + * target hardware. Normally 8 or 16. Only used by the FreeRTOS Cortex-M MPU + * ports, not the standard ARMv7-M Cortex-M port. Defaults to 8 if left + * undefined. */ +#define configTOTAL_MPU_REGIONS 8 + +/* configTEX_S_C_B_FLASH allows application writers to override the default + * values for the for TEX, Shareable (S), Cacheable (C) and Bufferable (B) bits for + * the MPU region covering Flash. Defaults to 0x07UL (which means TEX=000, S=1, + * C=1, B=1) if left undefined. Only used by the FreeRTOS Cortex-M MPU ports, not + * the standard ARMv7-M Cortex-M port. */ +#define configTEX_S_C_B_FLASH 0x07UL + +/* configTEX_S_C_B_SRAM allows application writers to override the default + * values for the for TEX, Shareable (S), Cacheable (C) and Bufferable (B) bits for + * the MPU region covering RAM. Defaults to 0x07UL (which means TEX=000, S=1, C=1, + * B=1) if left undefined. Only used by the FreeRTOS Cortex-M MPU ports, not + * the standard ARMv7-M Cortex-M port. */ +#define configTEX_S_C_B_SRAM 0x07UL + +/* Set configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY to 0 to prevent any privilege + * escalations originating from outside of the kernel code itself. Set to 1 to + * allow application tasks to raise privilege. Defaults to 1 if left undefined. + * Only used by the FreeRTOS Cortex-M MPU ports, not the standard ARMv7-M Cortex-M + * port. */ +#define configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY 1 + +/* Set configALLOW_UNPRIVILEGED_CRITICAL_SECTIONS to 1 to allow unprivileged + * tasks enter critical sections (effectively mask interrupts). Set to 0 to + * prevent unprivileged tasks entering critical sections. Defaults to 1 if left + * undefined. Only used by the FreeRTOS Cortex-M MPU ports, not the standard + * ARMv7-M Cortex-M port. */ +#define configALLOW_UNPRIVILEGED_CRITICAL_SECTIONS 0 + +/* FreeRTOS Kernel version 10.6.0 introduced a new v2 MPU wrapper, namely + * mpu_wrappers_v2.c. Set configUSE_MPU_WRAPPERS_V1 to 0 to use the new v2 MPU + * wrapper. Set configUSE_MPU_WRAPPERS_V1 to 1 to use the old v1 MPU wrapper + * (mpu_wrappers.c). Defaults to 0 if left undefined. */ +#define configUSE_MPU_WRAPPERS_V1 0 + +/* When using the v2 MPU wrapper, set configPROTECTED_KERNEL_OBJECT_POOL_SIZE to + * the total number of kernel objects, which includes tasks, queues, semaphores, + * mutexes, event groups, timers, stream buffers and message buffers, in your + * application. The application will not be able to have more than + * configPROTECTED_KERNEL_OBJECT_POOL_SIZE kernel objects at any point of + * time. */ +#define configPROTECTED_KERNEL_OBJECT_POOL_SIZE 10 + +/* When using the v2 MPU wrapper, set configSYSTEM_CALL_STACK_SIZE to the size + * of the system call stack in words. Each task has a statically allocated + * memory buffer of this size which is used as the stack to execute system + * calls. For example, if configSYSTEM_CALL_STACK_SIZE is defined as 128 and + * there are 10 tasks in the application, the total amount of memory used for + * system call stacks is 128 * 10 = 1280 words. */ +#define configSYSTEM_CALL_STACK_SIZE 128 + +/* When using the v2 MPU wrapper, set configENABLE_ACCESS_CONTROL_LIST to 1 to + * enable Access Control List (ACL) feature. When ACL is enabled, an + * unprivileged task by default does not have access to any kernel object other + * than itself. The application writer needs to explicitly grant the + * unprivileged task access to the kernel objects it needs using the APIs + * provided for the same. Defaults to 0 if left undefined. */ +#define configENABLE_ACCESS_CONTROL_LIST 1 + +/******************************************************************************/ +/* SMP( Symmetric MultiProcessing ) Specific Configuration definitions. *******/ +/******************************************************************************/ + +/* Set configNUMBER_OF_CORES to the number of available processor cores. Defaults + * to 1 if left undefined. */ + +/* + #define configNUMBER_OF_CORES [Num of available cores] + */ + +/* When using SMP (i.e. configNUMBER_OF_CORES is greater than one), set + * configRUN_MULTIPLE_PRIORITIES to 0 to allow multiple tasks to run + * simultaneously only if they do not have equal priority, thereby maintaining + * the paradigm of a lower priority task never running if a higher priority task + * is able to run. If configRUN_MULTIPLE_PRIORITIES is set to 1, multiple tasks + * with different priorities may run simultaneously - so a higher and lower + * priority task may run on different cores at the same time. */ +#define configRUN_MULTIPLE_PRIORITIES 0 + +/* When using SMP (i.e. configNUMBER_OF_CORES is greater than one), set + * configUSE_CORE_AFFINITY to 1 to enable core affinity feature. When core + * affinity feature is enabled, the vTaskCoreAffinitySet and vTaskCoreAffinityGet + * APIs can be used to set and retrieve which cores a task can run on. If + * configUSE_CORE_AFFINITY is set to 0 then the FreeRTOS scheduler is free to + * run any task on any available core. */ +#define configUSE_CORE_AFFINITY 0 + +/* When using SMP (i.e. configNUMBER_OF_CORES is greater than one), if + * configUSE_TASK_PREEMPTION_DISABLE is set to 1, individual tasks can be set to + * either pre-emptive or co-operative mode using the vTaskPreemptionDisable and + * vTaskPreemptionEnable APIs. */ +#define configUSE_TASK_PREEMPTION_DISABLE 0 + +/* When using SMP (i.e. configNUMBER_OF_CORES is greater than one), set + * configUSE_PASSIVE_IDLE_HOOK to 1 to allow the application writer to use + * the passive idle task hook to add background functionality without the overhead + * of a separate task. Defaults to 0 if left undefined. */ +#define configUSE_PASSIVE_IDLE_HOOK 0 + +/* When using SMP (i.e. configNUMBER_OF_CORES is greater than one), + * configTIMER_SERVICE_TASK_CORE_AFFINITY allows the application writer to set + * the core affinity of the RTOS Daemon/Timer Service task. Defaults to + * tskNO_AFFINITY if left undefined. */ +#define configTIMER_SERVICE_TASK_CORE_AFFINITY tskNO_AFFINITY + + +/******************************************************************************/ +/* ARMv8-M secure side port related definitions. ******************************/ +/******************************************************************************/ + +/* secureconfigMAX_SECURE_CONTEXTS define the maximum number of tasks that can + * call into the secure side of an ARMv8-M chip. Not used by any other ports. */ +#define secureconfigMAX_SECURE_CONTEXTS 5 + +/* Defines the kernel provided implementation of + * vApplicationGetIdleTaskMemory() and vApplicationGetTimerTaskMemory() + * to provide the memory that is used by the Idle task and Timer task respectively. + * The application can provide it's own implementation of + * vApplicationGetIdleTaskMemory() and vApplicationGetTimerTaskMemory() by + * setting configKERNEL_PROVIDED_STATIC_MEMORY to 0 or leaving it undefined. */ +#define configKERNEL_PROVIDED_STATIC_MEMORY 1 + +/******************************************************************************/ +/* Definitions that include or exclude functionality. *************************/ +/******************************************************************************/ + +/* Set the following configUSE_* constants to 1 to include the named feature in + * the build, or 0 to exclude the named feature from the build. */ +#define configUSE_TASK_NOTIFICATIONS 1 +#define configUSE_MUTEXES 1 +#define configUSE_RECURSIVE_MUTEXES 1 +#define configUSE_COUNTING_SEMAPHORES 1 +#define configUSE_QUEUE_SETS 0 +#define configUSE_APPLICATION_TASK_TAG 0 + +/* Set the following INCLUDE_* constants to 1 to incldue the named API function, + * or 0 to exclude the named API function. Most linkers will remove unused + * functions even when the constant is 1. */ +#define INCLUDE_vTaskPrioritySet 1 +#define INCLUDE_uxTaskPriorityGet 1 +#define INCLUDE_vTaskDelete 1 +#define INCLUDE_vTaskSuspend 1 +#define INCLUDE_xResumeFromISR 1 +#define INCLUDE_vTaskDelayUntil 1 +#define INCLUDE_vTaskDelay 1 +#define INCLUDE_xTaskGetSchedulerState 1 +#define INCLUDE_xTaskGetCurrentTaskHandle 1 +#define INCLUDE_uxTaskGetStackHighWaterMark 0 +#define INCLUDE_xTaskGetIdleTaskHandle 0 +#define INCLUDE_eTaskGetState 0 +#define INCLUDE_xEventGroupSetBitFromISR 1 +#define INCLUDE_xTimerPendFunctionCall 0 +#define INCLUDE_xTaskAbortDelay 0 +#define INCLUDE_xTaskGetHandle 0 +#define INCLUDE_xTaskResumeFromISR 1 + +#endif /* FREERTOS_CONFIG_H */ diff --git a/Source/examples/template_configuration/readme.md b/Source/examples/template_configuration/readme.md new file mode 100644 index 000000000..61c81f975 --- /dev/null +++ b/Source/examples/template_configuration/readme.md @@ -0,0 +1,7 @@ +# Configuration support for FreeRTOS + +## Overview + +Every FreeRTOS project requires FreeRTOSConfig.h located in their include path. In this folder you will find a sample FreeRTOSConfig.h that will assist you in preparing the configuration for your application. + +The FreeRTOSConfig.h in this folder is used in the minimal_freertos_example project provided and it not guaranteed to have the same configuration between updates. \ No newline at end of file diff --git a/Source/include/FreeRTOS.h b/Source/include/FreeRTOS.h index 4a19f932c..3400bca23 100644 --- a/Source/include/FreeRTOS.h +++ b/Source/include/FreeRTOS.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -91,6 +91,11 @@ #define configENABLE_ACCESS_CONTROL_LIST 0 #endif +/* Set default value of configNUMBER_OF_CORES to 1 to use single core FreeRTOS. */ +#ifndef configNUMBER_OF_CORES + #define configNUMBER_OF_CORES 1 +#endif + /* Basic FreeRTOS definitions. */ #include "projdefs.h" @@ -169,6 +174,12 @@ #error Missing definition: configUSE_IDLE_HOOK must be defined in FreeRTOSConfig.h as either 1 or 0. See the Configuration section of the FreeRTOS API documentation for details. #endif +#if ( configNUMBER_OF_CORES > 1 ) + #ifndef configUSE_PASSIVE_IDLE_HOOK + #error Missing definition: configUSE_PASSIVE_IDLE_HOOK must be defined in FreeRTOSConfig.h as either 1 or 0. See the Configuration section of the FreeRTOS API documentation for details. + #endif +#endif + #ifndef configUSE_TICK_HOOK #error Missing definition: configUSE_TICK_HOOK must be defined in FreeRTOSConfig.h as either 1 or 0. See the Configuration section of the FreeRTOS API documentation for details. #endif @@ -311,6 +322,10 @@ #define configUSE_COUNTING_SEMAPHORES 0 #endif +#ifndef configUSE_TASK_PREEMPTION_DISABLE + #define configUSE_TASK_PREEMPTION_DISABLE 0 +#endif + #ifndef configUSE_ALTERNATIVE_API #define configUSE_ALTERNATIVE_API 0 #endif @@ -350,6 +365,17 @@ #define configPRECONDITION_DEFINED 1 #endif +#ifndef configCHECK_HANDLER_INSTALLATION + #define configCHECK_HANDLER_INSTALLATION 1 +#else + +/* The application has explicitly defined configCHECK_HANDLER_INSTALLATION + * to 1. The checks requires configASSERT() to be defined. */ + #if ( ( configCHECK_HANDLER_INSTALLATION == 1 ) && ( configASSERT_DEFINED == 0 ) ) + #error You must define configASSERT() when configCHECK_HANDLER_INSTALLATION is 1. + #endif +#endif + #ifndef portMEMORY_BARRIER #define portMEMORY_BARRIER() #endif @@ -358,6 +384,110 @@ #define portSOFTWARE_BARRIER() #endif +#ifndef configRUN_MULTIPLE_PRIORITIES + #define configRUN_MULTIPLE_PRIORITIES 0 +#endif + +#ifndef portGET_CORE_ID + + #if ( configNUMBER_OF_CORES == 1 ) + #define portGET_CORE_ID() 0 + #else + #error configNUMBER_OF_CORES is set to more than 1 then portGET_CORE_ID must also be defined. + #endif /* configNUMBER_OF_CORES */ + +#endif /* portGET_CORE_ID */ + +#ifndef portYIELD_CORE + + #if ( configNUMBER_OF_CORES == 1 ) + #define portYIELD_CORE( x ) portYIELD() + #else + #error configNUMBER_OF_CORES is set to more than 1 then portYIELD_CORE must also be defined. + #endif /* configNUMBER_OF_CORES */ + +#endif /* portYIELD_CORE */ + +#ifndef portSET_INTERRUPT_MASK + + #if ( configNUMBER_OF_CORES > 1 ) + #error portSET_INTERRUPT_MASK is required in SMP + #endif + +#endif /* portSET_INTERRUPT_MASK */ + +#ifndef portCLEAR_INTERRUPT_MASK + + #if ( configNUMBER_OF_CORES > 1 ) + #error portCLEAR_INTERRUPT_MASK is required in SMP + #endif + +#endif /* portCLEAR_INTERRUPT_MASK */ + +#ifndef portRELEASE_TASK_LOCK + + #if ( configNUMBER_OF_CORES == 1 ) + #define portRELEASE_TASK_LOCK() + #else + #error portRELEASE_TASK_LOCK is required in SMP + #endif + +#endif /* portRELEASE_TASK_LOCK */ + +#ifndef portGET_TASK_LOCK + + #if ( configNUMBER_OF_CORES == 1 ) + #define portGET_TASK_LOCK() + #else + #error portGET_TASK_LOCK is required in SMP + #endif + +#endif /* portGET_TASK_LOCK */ + +#ifndef portRELEASE_ISR_LOCK + + #if ( configNUMBER_OF_CORES == 1 ) + #define portRELEASE_ISR_LOCK() + #else + #error portRELEASE_ISR_LOCK is required in SMP + #endif + +#endif /* portRELEASE_ISR_LOCK */ + +#ifndef portGET_ISR_LOCK + + #if ( configNUMBER_OF_CORES == 1 ) + #define portGET_ISR_LOCK() + #else + #error portGET_ISR_LOCK is required in SMP + #endif + +#endif /* portGET_ISR_LOCK */ + +#ifndef portENTER_CRITICAL_FROM_ISR + + #if ( configNUMBER_OF_CORES > 1 ) + #error portENTER_CRITICAL_FROM_ISR is required in SMP + #endif + +#endif + +#ifndef portEXIT_CRITICAL_FROM_ISR + + #if ( configNUMBER_OF_CORES > 1 ) + #error portEXIT_CRITICAL_FROM_ISR is required in SMP + #endif + +#endif + +#ifndef configUSE_CORE_AFFINITY + #define configUSE_CORE_AFFINITY 0 +#endif /* configUSE_CORE_AFFINITY */ + +#ifndef configUSE_PASSIVE_IDLE_HOOK + #define configUSE_PASSIVE_IDLE_HOOK 0 +#endif /* configUSE_PASSIVE_IDLE_HOOK */ + /* The timers module relies on xTaskGetSchedulerState(). */ #if configUSE_TIMERS == 1 @@ -373,6 +503,10 @@ #error If configUSE_TIMERS is set to 1 then configTIMER_TASK_STACK_DEPTH must also be defined. #endif /* configTIMER_TASK_STACK_DEPTH */ + #ifndef portTIMER_CALLBACK_ATTRIBUTE + #define portTIMER_CALLBACK_ATTRIBUTE + #endif /* portTIMER_CALLBACK_ATTRIBUTE */ + #endif /* configUSE_TIMERS */ #ifndef portSET_INTERRUPT_MASK_FROM_ISR @@ -395,6 +529,10 @@ #define portSETUP_TCB( pxTCB ) ( void ) ( pxTCB ) #endif +#ifndef portTASK_SWITCH_HOOK + #define portTASK_SWITCH_HOOK( pxTCB ) ( void ) ( pxTCB ) +#endif + #ifndef configQUEUE_REGISTRY_SIZE #define configQUEUE_REGISTRY_SIZE 0U #endif @@ -527,6 +665,14 @@ #define tracePOST_MOVED_TASK_TO_READY_STATE( pxTCB ) #endif +#ifndef traceMOVED_TASK_TO_DELAYED_LIST + #define traceMOVED_TASK_TO_DELAYED_LIST() +#endif + +#ifndef traceMOVED_TASK_TO_OVERFLOW_DELAYED_LIST + #define traceMOVED_TASK_TO_OVERFLOW_DELAYED_LIST() +#endif + #ifndef traceQUEUE_CREATE #define traceQUEUE_CREATE( pxNewQueue ) #endif @@ -775,6 +921,18 @@ #define traceTASK_NOTIFY_GIVE_FROM_ISR( uxIndexToNotify ) #endif +#ifndef traceISR_EXIT_TO_SCHEDULER + #define traceISR_EXIT_TO_SCHEDULER() +#endif + +#ifndef traceISR_EXIT + #define traceISR_EXIT() +#endif + +#ifndef traceISR_ENTER + #define traceISR_ENTER() +#endif + #ifndef traceSTREAM_BUFFER_CREATE_FAILED #define traceSTREAM_BUFFER_CREATE_FAILED( xIsMessageBuffer ) #endif @@ -827,279 +985,1907 @@ #define traceSTREAM_BUFFER_RECEIVE_FROM_ISR( xStreamBuffer, xReceivedLength ) #endif -#ifndef configGENERATE_RUN_TIME_STATS - #define configGENERATE_RUN_TIME_STATS 0 +#ifndef traceENTER_xEventGroupCreateStatic + #define traceENTER_xEventGroupCreateStatic( pxEventGroupBuffer ) #endif -#if ( configGENERATE_RUN_TIME_STATS == 1 ) +#ifndef traceRETURN_xEventGroupCreateStatic + #define traceRETURN_xEventGroupCreateStatic( pxEventBits ) +#endif - #ifndef portCONFIGURE_TIMER_FOR_RUN_TIME_STATS - #error If configGENERATE_RUN_TIME_STATS is defined then portCONFIGURE_TIMER_FOR_RUN_TIME_STATS must also be defined. portCONFIGURE_TIMER_FOR_RUN_TIME_STATS should call a port layer function to setup a peripheral timer/counter that can then be used as the run time counter time base. - #endif /* portCONFIGURE_TIMER_FOR_RUN_TIME_STATS */ +#ifndef traceENTER_xEventGroupCreate + #define traceENTER_xEventGroupCreate() +#endif - #ifndef portGET_RUN_TIME_COUNTER_VALUE - #ifndef portALT_GET_RUN_TIME_COUNTER_VALUE - #error If configGENERATE_RUN_TIME_STATS is defined then either portGET_RUN_TIME_COUNTER_VALUE or portALT_GET_RUN_TIME_COUNTER_VALUE must also be defined. See the examples provided and the FreeRTOS web site for more information. - #endif /* portALT_GET_RUN_TIME_COUNTER_VALUE */ - #endif /* portGET_RUN_TIME_COUNTER_VALUE */ +#ifndef traceRETURN_xEventGroupCreate + #define traceRETURN_xEventGroupCreate( pxEventBits ) +#endif -#endif /* configGENERATE_RUN_TIME_STATS */ +#ifndef traceENTER_xEventGroupSync + #define traceENTER_xEventGroupSync( xEventGroup, uxBitsToSet, uxBitsToWaitFor, xTicksToWait ) +#endif -#ifndef portCONFIGURE_TIMER_FOR_RUN_TIME_STATS - #define portCONFIGURE_TIMER_FOR_RUN_TIME_STATS() +#ifndef traceRETURN_xEventGroupSync + #define traceRETURN_xEventGroupSync( uxReturn ) #endif -#ifndef configUSE_MALLOC_FAILED_HOOK - #define configUSE_MALLOC_FAILED_HOOK 0 +#ifndef traceENTER_xEventGroupWaitBits + #define traceENTER_xEventGroupWaitBits( xEventGroup, uxBitsToWaitFor, xClearOnExit, xWaitForAllBits, xTicksToWait ) #endif -#ifndef portPRIVILEGE_BIT - #define portPRIVILEGE_BIT ( ( UBaseType_t ) 0x00 ) +#ifndef traceRETURN_xEventGroupWaitBits + #define traceRETURN_xEventGroupWaitBits( uxReturn ) #endif -#ifndef portYIELD_WITHIN_API - #define portYIELD_WITHIN_API portYIELD +#ifndef traceENTER_xEventGroupClearBits + #define traceENTER_xEventGroupClearBits( xEventGroup, uxBitsToClear ) #endif -#ifndef portSUPPRESS_TICKS_AND_SLEEP - #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime ) +#ifndef traceRETURN_xEventGroupClearBits + #define traceRETURN_xEventGroupClearBits( uxReturn ) #endif -#ifndef configEXPECTED_IDLE_TIME_BEFORE_SLEEP - #define configEXPECTED_IDLE_TIME_BEFORE_SLEEP 2 +#ifndef traceENTER_xEventGroupClearBitsFromISR + #define traceENTER_xEventGroupClearBitsFromISR( xEventGroup, uxBitsToClear ) #endif -#if configEXPECTED_IDLE_TIME_BEFORE_SLEEP < 2 - #error configEXPECTED_IDLE_TIME_BEFORE_SLEEP must not be less than 2 +#ifndef traceRETURN_xEventGroupClearBitsFromISR + #define traceRETURN_xEventGroupClearBitsFromISR( xReturn ) #endif -#ifndef configUSE_TICKLESS_IDLE - #define configUSE_TICKLESS_IDLE 0 +#ifndef traceENTER_xEventGroupGetBitsFromISR + #define traceENTER_xEventGroupGetBitsFromISR( xEventGroup ) #endif -#ifndef configPRE_SUPPRESS_TICKS_AND_SLEEP_PROCESSING - #define configPRE_SUPPRESS_TICKS_AND_SLEEP_PROCESSING( x ) +#ifndef traceRETURN_xEventGroupGetBitsFromISR + #define traceRETURN_xEventGroupGetBitsFromISR( uxReturn ) #endif -#ifndef configPRE_SLEEP_PROCESSING - #define configPRE_SLEEP_PROCESSING( x ) +#ifndef traceENTER_xEventGroupSetBits + #define traceENTER_xEventGroupSetBits( xEventGroup, uxBitsToSet ) #endif -#ifndef configPOST_SLEEP_PROCESSING - #define configPOST_SLEEP_PROCESSING( x ) +#ifndef traceRETURN_xEventGroupSetBits + #define traceRETURN_xEventGroupSetBits( uxEventBits ) #endif -#ifndef configUSE_QUEUE_SETS - #define configUSE_QUEUE_SETS 0 +#ifndef traceENTER_vEventGroupDelete + #define traceENTER_vEventGroupDelete( xEventGroup ) #endif -#ifndef portTASK_USES_FLOATING_POINT - #define portTASK_USES_FLOATING_POINT() +#ifndef traceRETURN_vEventGroupDelete + #define traceRETURN_vEventGroupDelete() #endif -#ifndef portALLOCATE_SECURE_CONTEXT - #define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize ) +#ifndef traceENTER_xEventGroupGetStaticBuffer + #define traceENTER_xEventGroupGetStaticBuffer( xEventGroup, ppxEventGroupBuffer ) #endif -#ifndef portDONT_DISCARD - #define portDONT_DISCARD +#ifndef traceRETURN_xEventGroupGetStaticBuffer + #define traceRETURN_xEventGroupGetStaticBuffer( xReturn ) #endif -#ifndef configUSE_TIME_SLICING - #define configUSE_TIME_SLICING 1 +#ifndef traceENTER_vEventGroupSetBitsCallback + #define traceENTER_vEventGroupSetBitsCallback( pvEventGroup, ulBitsToSet ) #endif -#ifndef configINCLUDE_APPLICATION_DEFINED_PRIVILEGED_FUNCTIONS - #define configINCLUDE_APPLICATION_DEFINED_PRIVILEGED_FUNCTIONS 0 +#ifndef traceRETURN_vEventGroupSetBitsCallback + #define traceRETURN_vEventGroupSetBitsCallback() #endif -#ifndef configUSE_STATS_FORMATTING_FUNCTIONS - #define configUSE_STATS_FORMATTING_FUNCTIONS 0 +#ifndef traceENTER_vEventGroupClearBitsCallback + #define traceENTER_vEventGroupClearBitsCallback( pvEventGroup, ulBitsToClear ) #endif -#ifndef portASSERT_IF_INTERRUPT_PRIORITY_INVALID - #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() +#ifndef traceRETURN_vEventGroupClearBitsCallback + #define traceRETURN_vEventGroupClearBitsCallback() #endif -#ifndef configUSE_TRACE_FACILITY - #define configUSE_TRACE_FACILITY 0 +#ifndef traceENTER_xEventGroupSetBitsFromISR + #define traceENTER_xEventGroupSetBitsFromISR( xEventGroup, uxBitsToSet, pxHigherPriorityTaskWoken ) #endif -#ifndef mtCOVERAGE_TEST_MARKER - #define mtCOVERAGE_TEST_MARKER() +#ifndef traceRETURN_xEventGroupSetBitsFromISR + #define traceRETURN_xEventGroupSetBitsFromISR( xReturn ) #endif -#ifndef mtCOVERAGE_TEST_DELAY - #define mtCOVERAGE_TEST_DELAY() +#ifndef traceENTER_uxEventGroupGetNumber + #define traceENTER_uxEventGroupGetNumber( xEventGroup ) #endif -#ifndef portASSERT_IF_IN_ISR - #define portASSERT_IF_IN_ISR() +#ifndef traceRETURN_uxEventGroupGetNumber + #define traceRETURN_uxEventGroupGetNumber( xReturn ) #endif -#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION - #define configUSE_PORT_OPTIMISED_TASK_SELECTION 0 +#ifndef traceENTER_vEventGroupSetNumber + #define traceENTER_vEventGroupSetNumber( xEventGroup, uxEventGroupNumber ) #endif -#ifndef configAPPLICATION_ALLOCATED_HEAP - #define configAPPLICATION_ALLOCATED_HEAP 0 +#ifndef traceRETURN_vEventGroupSetNumber + #define traceRETURN_vEventGroupSetNumber() #endif -#ifndef configUSE_TASK_NOTIFICATIONS - #define configUSE_TASK_NOTIFICATIONS 1 +#ifndef traceENTER_xQueueGenericReset + #define traceENTER_xQueueGenericReset( xQueue, xNewQueue ) #endif -#ifndef configTASK_NOTIFICATION_ARRAY_ENTRIES - #define configTASK_NOTIFICATION_ARRAY_ENTRIES 1 +#ifndef traceRETURN_xQueueGenericReset + #define traceRETURN_xQueueGenericReset( xReturn ) #endif -#if configTASK_NOTIFICATION_ARRAY_ENTRIES < 1 - #error configTASK_NOTIFICATION_ARRAY_ENTRIES must be at least 1 +#ifndef traceENTER_xQueueGenericCreateStatic + #define traceENTER_xQueueGenericCreateStatic( uxQueueLength, uxItemSize, pucQueueStorage, pxStaticQueue, ucQueueType ) #endif -#ifndef configUSE_POSIX_ERRNO - #define configUSE_POSIX_ERRNO 0 +#ifndef traceRETURN_xQueueGenericCreateStatic + #define traceRETURN_xQueueGenericCreateStatic( pxNewQueue ) #endif -#ifndef configUSE_SB_COMPLETED_CALLBACK +#ifndef traceENTER_xQueueGenericGetStaticBuffers + #define traceENTER_xQueueGenericGetStaticBuffers( xQueue, ppucQueueStorage, ppxStaticQueue ) +#endif -/* By default per-instance callbacks are not enabled for stream buffer or message buffer. */ - #define configUSE_SB_COMPLETED_CALLBACK 0 +#ifndef traceRETURN_xQueueGenericGetStaticBuffers + #define traceRETURN_xQueueGenericGetStaticBuffers( xReturn ) #endif -#ifndef portTICK_TYPE_IS_ATOMIC - #define portTICK_TYPE_IS_ATOMIC 0 +#ifndef traceENTER_xQueueGenericCreate + #define traceENTER_xQueueGenericCreate( uxQueueLength, uxItemSize, ucQueueType ) #endif -#ifndef configSUPPORT_STATIC_ALLOCATION - /* Defaults to 0 for backward compatibility. */ - #define configSUPPORT_STATIC_ALLOCATION 0 +#ifndef traceRETURN_xQueueGenericCreate + #define traceRETURN_xQueueGenericCreate( pxNewQueue ) #endif -#ifndef configSUPPORT_DYNAMIC_ALLOCATION - /* Defaults to 1 for backward compatibility. */ - #define configSUPPORT_DYNAMIC_ALLOCATION 1 +#ifndef traceENTER_xQueueCreateMutex + #define traceENTER_xQueueCreateMutex( ucQueueType ) #endif -#if ( ( configUSE_STATS_FORMATTING_FUNCTIONS > 0 ) && ( configSUPPORT_DYNAMIC_ALLOCATION != 1 ) ) - #error configUSE_STATS_FORMATTING_FUNCTIONS cannot be used without dynamic allocation, but configSUPPORT_DYNAMIC_ALLOCATION is not set to 1. +#ifndef traceRETURN_xQueueCreateMutex + #define traceRETURN_xQueueCreateMutex( xNewQueue ) #endif -#if ( configUSE_STATS_FORMATTING_FUNCTIONS > 0 ) - #if ( ( configUSE_TRACE_FACILITY != 1 ) && ( configGENERATE_RUN_TIME_STATS != 1 ) ) - #error configUSE_STATS_FORMATTING_FUNCTIONS is 1 but the functions it enables are not used because neither configUSE_TRACE_FACILITY or configGENERATE_RUN_TIME_STATS are 1. Set configUSE_STATS_FORMATTING_FUNCTIONS to 0 in FreeRTOSConfig.h. - #endif +#ifndef traceENTER_xQueueCreateMutexStatic + #define traceENTER_xQueueCreateMutexStatic( ucQueueType, pxStaticQueue ) #endif -#ifndef configSTACK_DEPTH_TYPE +#ifndef traceRETURN_xQueueCreateMutexStatic + #define traceRETURN_xQueueCreateMutexStatic( xNewQueue ) +#endif -/* Defaults to uint16_t for backward compatibility, but can be overridden - * in FreeRTOSConfig.h if uint16_t is too restrictive. */ - #define configSTACK_DEPTH_TYPE uint16_t +#ifndef traceENTER_xQueueGetMutexHolder + #define traceENTER_xQueueGetMutexHolder( xSemaphore ) #endif -#ifndef configRUN_TIME_COUNTER_TYPE +#ifndef traceRETURN_xQueueGetMutexHolder + #define traceRETURN_xQueueGetMutexHolder( pxReturn ) +#endif -/* Defaults to uint32_t for backward compatibility, but can be overridden in - * FreeRTOSConfig.h if uint32_t is too restrictive. */ +#ifndef traceENTER_xQueueGetMutexHolderFromISR + #define traceENTER_xQueueGetMutexHolderFromISR( xSemaphore ) +#endif - #define configRUN_TIME_COUNTER_TYPE uint32_t +#ifndef traceRETURN_xQueueGetMutexHolderFromISR + #define traceRETURN_xQueueGetMutexHolderFromISR( pxReturn ) #endif -#ifndef configMESSAGE_BUFFER_LENGTH_TYPE +#ifndef traceENTER_xQueueGiveMutexRecursive + #define traceENTER_xQueueGiveMutexRecursive( xMutex ) +#endif -/* Defaults to size_t for backward compatibility, but can be overridden - * in FreeRTOSConfig.h if lengths will always be less than the number of bytes - * in a size_t. */ - #define configMESSAGE_BUFFER_LENGTH_TYPE size_t +#ifndef traceRETURN_xQueueGiveMutexRecursive + #define traceRETURN_xQueueGiveMutexRecursive( xReturn ) #endif -/* Sanity check the configuration. */ -#if ( ( configSUPPORT_STATIC_ALLOCATION == 0 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 0 ) ) - #error configSUPPORT_STATIC_ALLOCATION and configSUPPORT_DYNAMIC_ALLOCATION cannot both be 0, but can both be 1. +#ifndef traceENTER_xQueueTakeMutexRecursive + #define traceENTER_xQueueTakeMutexRecursive( xMutex, xTicksToWait ) #endif -#if ( ( configUSE_RECURSIVE_MUTEXES == 1 ) && ( configUSE_MUTEXES != 1 ) ) - #error configUSE_MUTEXES must be set to 1 to use recursive mutexes +#ifndef traceRETURN_xQueueTakeMutexRecursive + #define traceRETURN_xQueueTakeMutexRecursive( xReturn ) #endif -#ifndef configINITIAL_TICK_COUNT - #define configINITIAL_TICK_COUNT 0 +#ifndef traceENTER_xQueueCreateCountingSemaphoreStatic + #define traceENTER_xQueueCreateCountingSemaphoreStatic( uxMaxCount, uxInitialCount, pxStaticQueue ) #endif -#if ( portTICK_TYPE_IS_ATOMIC == 0 ) +#ifndef traceRETURN_xQueueCreateCountingSemaphoreStatic + #define traceRETURN_xQueueCreateCountingSemaphoreStatic( xHandle ) +#endif -/* Either variables of tick type cannot be read atomically, or - * portTICK_TYPE_IS_ATOMIC was not set - map the critical sections used when - * the tick count is returned to the standard critical section macros. */ - #define portTICK_TYPE_ENTER_CRITICAL() portENTER_CRITICAL() - #define portTICK_TYPE_EXIT_CRITICAL() portEXIT_CRITICAL() - #define portTICK_TYPE_SET_INTERRUPT_MASK_FROM_ISR() portSET_INTERRUPT_MASK_FROM_ISR() - #define portTICK_TYPE_CLEAR_INTERRUPT_MASK_FROM_ISR( x ) portCLEAR_INTERRUPT_MASK_FROM_ISR( ( x ) ) -#else +#ifndef traceENTER_xQueueCreateCountingSemaphore + #define traceENTER_xQueueCreateCountingSemaphore( uxMaxCount, uxInitialCount ) +#endif -/* The tick type can be read atomically, so critical sections used when the - * tick count is returned can be defined away. */ - #define portTICK_TYPE_ENTER_CRITICAL() - #define portTICK_TYPE_EXIT_CRITICAL() - #define portTICK_TYPE_SET_INTERRUPT_MASK_FROM_ISR() 0 - #define portTICK_TYPE_CLEAR_INTERRUPT_MASK_FROM_ISR( x ) ( void ) ( x ) -#endif /* if ( portTICK_TYPE_IS_ATOMIC == 0 ) */ +#ifndef traceRETURN_xQueueCreateCountingSemaphore + #define traceRETURN_xQueueCreateCountingSemaphore( xHandle ) +#endif -/* Definitions to allow backward compatibility with FreeRTOS versions prior to - * V8 if desired. */ -#ifndef configENABLE_BACKWARD_COMPATIBILITY - #define configENABLE_BACKWARD_COMPATIBILITY 1 +#ifndef traceENTER_xQueueGenericSend + #define traceENTER_xQueueGenericSend( xQueue, pvItemToQueue, xTicksToWait, xCopyPosition ) #endif -#ifndef configPRINTF +#ifndef traceRETURN_xQueueGenericSend + #define traceRETURN_xQueueGenericSend( xReturn ) +#endif -/* configPRINTF() was not defined, so define it away to nothing. To use - * configPRINTF() then define it as follows (where MyPrintFunction() is - * provided by the application writer): - * - * void MyPrintFunction(const char *pcFormat, ... ); - #define configPRINTF( X ) MyPrintFunction X - * - * Then call like a standard printf() function, but placing brackets around - * all parameters so they are passed as a single parameter. For example: - * configPRINTF( ("Value = %d", MyVariable) ); */ - #define configPRINTF( X ) +#ifndef traceENTER_xQueueGenericSendFromISR + #define traceENTER_xQueueGenericSendFromISR( xQueue, pvItemToQueue, pxHigherPriorityTaskWoken, xCopyPosition ) #endif -#ifndef configMAX +#ifndef traceRETURN_xQueueGenericSendFromISR + #define traceRETURN_xQueueGenericSendFromISR( xReturn ) +#endif -/* The application writer has not provided their own MAX macro, so define - * the following generic implementation. */ - #define configMAX( a, b ) ( ( ( a ) > ( b ) ) ? ( a ) : ( b ) ) +#ifndef traceENTER_xQueueGiveFromISR + #define traceENTER_xQueueGiveFromISR( xQueue, pxHigherPriorityTaskWoken ) #endif -#ifndef configMIN +#ifndef traceRETURN_xQueueGiveFromISR + #define traceRETURN_xQueueGiveFromISR( xReturn ) +#endif -/* The application writer has not provided their own MIN macro, so define - * the following generic implementation. */ - #define configMIN( a, b ) ( ( ( a ) < ( b ) ) ? ( a ) : ( b ) ) +#ifndef traceENTER_xQueueReceive + #define traceENTER_xQueueReceive( xQueue, pvBuffer, xTicksToWait ) #endif -#if configENABLE_BACKWARD_COMPATIBILITY == 1 - #define eTaskStateGet eTaskGetState - #define portTickType TickType_t - #define xTaskHandle TaskHandle_t - #define xQueueHandle QueueHandle_t - #define xSemaphoreHandle SemaphoreHandle_t - #define xQueueSetHandle QueueSetHandle_t - #define xQueueSetMemberHandle QueueSetMemberHandle_t - #define xTimeOutType TimeOut_t - #define xMemoryRegion MemoryRegion_t - #define xTaskParameters TaskParameters_t - #define xTaskStatusType TaskStatus_t - #define xTimerHandle TimerHandle_t - #define xCoRoutineHandle CoRoutineHandle_t - #define pdTASK_HOOK_CODE TaskHookFunction_t - #define portTICK_RATE_MS portTICK_PERIOD_MS - #define pcTaskGetTaskName pcTaskGetName - #define pcTimerGetTimerName pcTimerGetName - #define pcQueueGetQueueName pcQueueGetName +#ifndef traceRETURN_xQueueReceive + #define traceRETURN_xQueueReceive( xReturn ) +#endif + +#ifndef traceENTER_xQueueSemaphoreTake + #define traceENTER_xQueueSemaphoreTake( xQueue, xTicksToWait ) +#endif + +#ifndef traceRETURN_xQueueSemaphoreTake + #define traceRETURN_xQueueSemaphoreTake( xReturn ) +#endif + +#ifndef traceENTER_xQueuePeek + #define traceENTER_xQueuePeek( xQueue, pvBuffer, xTicksToWait ) +#endif + +#ifndef traceRETURN_xQueuePeek + #define traceRETURN_xQueuePeek( xReturn ) +#endif + +#ifndef traceENTER_xQueueReceiveFromISR + #define traceENTER_xQueueReceiveFromISR( xQueue, pvBuffer, pxHigherPriorityTaskWoken ) +#endif + +#ifndef traceRETURN_xQueueReceiveFromISR + #define traceRETURN_xQueueReceiveFromISR( xReturn ) +#endif + +#ifndef traceENTER_xQueuePeekFromISR + #define traceENTER_xQueuePeekFromISR( xQueue, pvBuffer ) +#endif + +#ifndef traceRETURN_xQueuePeekFromISR + #define traceRETURN_xQueuePeekFromISR( xReturn ) +#endif + +#ifndef traceENTER_uxQueueMessagesWaiting + #define traceENTER_uxQueueMessagesWaiting( xQueue ) +#endif + +#ifndef traceRETURN_uxQueueMessagesWaiting + #define traceRETURN_uxQueueMessagesWaiting( uxReturn ) +#endif + +#ifndef traceENTER_uxQueueSpacesAvailable + #define traceENTER_uxQueueSpacesAvailable( xQueue ) +#endif + +#ifndef traceRETURN_uxQueueSpacesAvailable + #define traceRETURN_uxQueueSpacesAvailable( uxReturn ) +#endif + +#ifndef traceENTER_uxQueueMessagesWaitingFromISR + #define traceENTER_uxQueueMessagesWaitingFromISR( xQueue ) +#endif + +#ifndef traceRETURN_uxQueueMessagesWaitingFromISR + #define traceRETURN_uxQueueMessagesWaitingFromISR( uxReturn ) +#endif + +#ifndef traceENTER_vQueueDelete + #define traceENTER_vQueueDelete( xQueue ) +#endif + +#ifndef traceRETURN_vQueueDelete + #define traceRETURN_vQueueDelete() +#endif + +#ifndef traceENTER_uxQueueGetQueueNumber + #define traceENTER_uxQueueGetQueueNumber( xQueue ) +#endif + +#ifndef traceRETURN_uxQueueGetQueueNumber + #define traceRETURN_uxQueueGetQueueNumber( uxQueueNumber ) +#endif + +#ifndef traceENTER_vQueueSetQueueNumber + #define traceENTER_vQueueSetQueueNumber( xQueue, uxQueueNumber ) +#endif + +#ifndef traceRETURN_vQueueSetQueueNumber + #define traceRETURN_vQueueSetQueueNumber() +#endif + +#ifndef traceENTER_ucQueueGetQueueType + #define traceENTER_ucQueueGetQueueType( xQueue ) +#endif + +#ifndef traceRETURN_ucQueueGetQueueType + #define traceRETURN_ucQueueGetQueueType( ucQueueType ) +#endif + +#ifndef traceENTER_uxQueueGetQueueItemSize + #define traceENTER_uxQueueGetQueueItemSize( xQueue ) +#endif + +#ifndef traceRETURN_uxQueueGetQueueItemSize + #define traceRETURN_uxQueueGetQueueItemSize( uxItemSize ) +#endif + +#ifndef traceENTER_uxQueueGetQueueLength + #define traceENTER_uxQueueGetQueueLength( xQueue ) +#endif + +#ifndef traceRETURN_uxQueueGetQueueLength + #define traceRETURN_uxQueueGetQueueLength( uxLength ) +#endif + +#ifndef traceENTER_xQueueIsQueueEmptyFromISR + #define traceENTER_xQueueIsQueueEmptyFromISR( xQueue ) +#endif + +#ifndef traceRETURN_xQueueIsQueueEmptyFromISR + #define traceRETURN_xQueueIsQueueEmptyFromISR( xReturn ) +#endif + +#ifndef traceENTER_xQueueIsQueueFullFromISR + #define traceENTER_xQueueIsQueueFullFromISR( xQueue ) +#endif + +#ifndef traceRETURN_xQueueIsQueueFullFromISR + #define traceRETURN_xQueueIsQueueFullFromISR( xReturn ) +#endif + +#ifndef traceENTER_xQueueCRSend + #define traceENTER_xQueueCRSend( xQueue, pvItemToQueue, xTicksToWait ) +#endif + +#ifndef traceRETURN_xQueueCRSend + #define traceRETURN_xQueueCRSend( xReturn ) +#endif + +#ifndef traceENTER_xQueueCRReceive + #define traceENTER_xQueueCRReceive( xQueue, pvBuffer, xTicksToWait ) +#endif + +#ifndef traceRETURN_xQueueCRReceive + #define traceRETURN_xQueueCRReceive( xReturn ) +#endif + +#ifndef traceENTER_xQueueCRSendFromISR + #define traceENTER_xQueueCRSendFromISR( xQueue, pvItemToQueue, xCoRoutinePreviouslyWoken ) +#endif + +#ifndef traceRETURN_xQueueCRSendFromISR + #define traceRETURN_xQueueCRSendFromISR( xCoRoutinePreviouslyWoken ) +#endif + +#ifndef traceENTER_xQueueCRReceiveFromISR + #define traceENTER_xQueueCRReceiveFromISR( xQueue, pvBuffer, pxCoRoutineWoken ) +#endif + +#ifndef traceRETURN_xQueueCRReceiveFromISR + #define traceRETURN_xQueueCRReceiveFromISR( xReturn ) +#endif + +#ifndef traceENTER_vQueueAddToRegistry + #define traceENTER_vQueueAddToRegistry( xQueue, pcQueueName ) +#endif + +#ifndef traceRETURN_vQueueAddToRegistry + #define traceRETURN_vQueueAddToRegistry() +#endif + +#ifndef traceENTER_pcQueueGetName + #define traceENTER_pcQueueGetName( xQueue ) +#endif + +#ifndef traceRETURN_pcQueueGetName + #define traceRETURN_pcQueueGetName( pcReturn ) +#endif + +#ifndef traceENTER_vQueueUnregisterQueue + #define traceENTER_vQueueUnregisterQueue( xQueue ) +#endif + +#ifndef traceRETURN_vQueueUnregisterQueue + #define traceRETURN_vQueueUnregisterQueue() +#endif + +#ifndef traceENTER_vQueueWaitForMessageRestricted + #define traceENTER_vQueueWaitForMessageRestricted( xQueue, xTicksToWait, xWaitIndefinitely ) +#endif + +#ifndef traceRETURN_vQueueWaitForMessageRestricted + #define traceRETURN_vQueueWaitForMessageRestricted() +#endif + +#ifndef traceENTER_xQueueCreateSet + #define traceENTER_xQueueCreateSet( uxEventQueueLength ) +#endif + +#ifndef traceRETURN_xQueueCreateSet + #define traceRETURN_xQueueCreateSet( pxQueue ) +#endif + +#ifndef traceENTER_xQueueAddToSet + #define traceENTER_xQueueAddToSet( xQueueOrSemaphore, xQueueSet ) +#endif + +#ifndef traceRETURN_xQueueAddToSet + #define traceRETURN_xQueueAddToSet( xReturn ) +#endif + +#ifndef traceENTER_xQueueRemoveFromSet + #define traceENTER_xQueueRemoveFromSet( xQueueOrSemaphore, xQueueSet ) +#endif + +#ifndef traceRETURN_xQueueRemoveFromSet + #define traceRETURN_xQueueRemoveFromSet( xReturn ) +#endif + +#ifndef traceENTER_xQueueSelectFromSet + #define traceENTER_xQueueSelectFromSet( xQueueSet, xTicksToWait ) +#endif + +#ifndef traceRETURN_xQueueSelectFromSet + #define traceRETURN_xQueueSelectFromSet( xReturn ) +#endif + +#ifndef traceENTER_xQueueSelectFromSetFromISR + #define traceENTER_xQueueSelectFromSetFromISR( xQueueSet ) +#endif + +#ifndef traceRETURN_xQueueSelectFromSetFromISR + #define traceRETURN_xQueueSelectFromSetFromISR( xReturn ) +#endif + +#ifndef traceENTER_xTimerCreateTimerTask + #define traceENTER_xTimerCreateTimerTask() +#endif + +#ifndef traceRETURN_xTimerCreateTimerTask + #define traceRETURN_xTimerCreateTimerTask( xReturn ) +#endif + +#ifndef traceENTER_xTimerCreate + #define traceENTER_xTimerCreate( pcTimerName, xTimerPeriodInTicks, xAutoReload, pvTimerID, pxCallbackFunction ) +#endif + +#ifndef traceRETURN_xTimerCreate + #define traceRETURN_xTimerCreate( pxNewTimer ) +#endif + +#ifndef traceENTER_xTimerCreateStatic + #define traceENTER_xTimerCreateStatic( pcTimerName, xTimerPeriodInTicks, xAutoReload, pvTimerID, pxCallbackFunction, pxTimerBuffer ) +#endif + +#ifndef traceRETURN_xTimerCreateStatic + #define traceRETURN_xTimerCreateStatic( pxNewTimer ) +#endif + +#ifndef traceENTER_xTimerGenericCommandFromTask + #define traceENTER_xTimerGenericCommandFromTask( xTimer, xCommandID, xOptionalValue, pxHigherPriorityTaskWoken, xTicksToWait ) +#endif + +#ifndef traceRETURN_xTimerGenericCommandFromTask + #define traceRETURN_xTimerGenericCommandFromTask( xReturn ) +#endif + +#ifndef traceENTER_xTimerGenericCommandFromISR + #define traceENTER_xTimerGenericCommandFromISR( xTimer, xCommandID, xOptionalValue, pxHigherPriorityTaskWoken, xTicksToWait ) +#endif + +#ifndef traceRETURN_xTimerGenericCommandFromISR + #define traceRETURN_xTimerGenericCommandFromISR( xReturn ) +#endif + +#ifndef traceENTER_xTimerGetTimerDaemonTaskHandle + #define traceENTER_xTimerGetTimerDaemonTaskHandle() +#endif + +#ifndef traceRETURN_xTimerGetTimerDaemonTaskHandle + #define traceRETURN_xTimerGetTimerDaemonTaskHandle( xTimerTaskHandle ) +#endif + +#ifndef traceENTER_xTimerGetPeriod + #define traceENTER_xTimerGetPeriod( xTimer ) +#endif + +#ifndef traceRETURN_xTimerGetPeriod + #define traceRETURN_xTimerGetPeriod( xTimerPeriodInTicks ) +#endif + +#ifndef traceENTER_vTimerSetReloadMode + #define traceENTER_vTimerSetReloadMode( xTimer, xAutoReload ) +#endif + +#ifndef traceRETURN_vTimerSetReloadMode + #define traceRETURN_vTimerSetReloadMode() +#endif + +#ifndef traceENTER_xTimerGetReloadMode + #define traceENTER_xTimerGetReloadMode( xTimer ) +#endif + +#ifndef traceRETURN_xTimerGetReloadMode + #define traceRETURN_xTimerGetReloadMode( xReturn ) +#endif + +#ifndef traceENTER_uxTimerGetReloadMode + #define traceENTER_uxTimerGetReloadMode( xTimer ) +#endif + +#ifndef traceRETURN_uxTimerGetReloadMode + #define traceRETURN_uxTimerGetReloadMode( uxReturn ) +#endif + +#ifndef traceENTER_xTimerGetExpiryTime + #define traceENTER_xTimerGetExpiryTime( xTimer ) +#endif + +#ifndef traceRETURN_xTimerGetExpiryTime + #define traceRETURN_xTimerGetExpiryTime( xReturn ) +#endif + +#ifndef traceENTER_xTimerGetStaticBuffer + #define traceENTER_xTimerGetStaticBuffer( xTimer, ppxTimerBuffer ) +#endif + +#ifndef traceRETURN_xTimerGetStaticBuffer + #define traceRETURN_xTimerGetStaticBuffer( xReturn ) +#endif + +#ifndef traceENTER_pcTimerGetName + #define traceENTER_pcTimerGetName( xTimer ) +#endif + +#ifndef traceRETURN_pcTimerGetName + #define traceRETURN_pcTimerGetName( pcTimerName ) +#endif + +#ifndef traceENTER_xTimerIsTimerActive + #define traceENTER_xTimerIsTimerActive( xTimer ) +#endif + +#ifndef traceRETURN_xTimerIsTimerActive + #define traceRETURN_xTimerIsTimerActive( xReturn ) +#endif + +#ifndef traceENTER_pvTimerGetTimerID + #define traceENTER_pvTimerGetTimerID( xTimer ) +#endif + +#ifndef traceRETURN_pvTimerGetTimerID + #define traceRETURN_pvTimerGetTimerID( pvReturn ) +#endif + +#ifndef traceENTER_vTimerSetTimerID + #define traceENTER_vTimerSetTimerID( xTimer, pvNewID ) +#endif + +#ifndef traceRETURN_vTimerSetTimerID + #define traceRETURN_vTimerSetTimerID() +#endif + +#ifndef traceENTER_xTimerPendFunctionCallFromISR + #define traceENTER_xTimerPendFunctionCallFromISR( xFunctionToPend, pvParameter1, ulParameter2, pxHigherPriorityTaskWoken ) +#endif + +#ifndef traceRETURN_xTimerPendFunctionCallFromISR + #define traceRETURN_xTimerPendFunctionCallFromISR( xReturn ) +#endif + +#ifndef traceENTER_xTimerPendFunctionCall + #define traceENTER_xTimerPendFunctionCall( xFunctionToPend, pvParameter1, ulParameter2, xTicksToWait ) +#endif + +#ifndef traceRETURN_xTimerPendFunctionCall + #define traceRETURN_xTimerPendFunctionCall( xReturn ) +#endif + +#ifndef traceENTER_uxTimerGetTimerNumber + #define traceENTER_uxTimerGetTimerNumber( xTimer ) +#endif + +#ifndef traceRETURN_uxTimerGetTimerNumber + #define traceRETURN_uxTimerGetTimerNumber( uxTimerNumber ) +#endif + +#ifndef traceENTER_vTimerSetTimerNumber + #define traceENTER_vTimerSetTimerNumber( xTimer, uxTimerNumber ) +#endif + +#ifndef traceRETURN_vTimerSetTimerNumber + #define traceRETURN_vTimerSetTimerNumber() +#endif + +#ifndef traceENTER_xTaskCreateStatic + #define traceENTER_xTaskCreateStatic( pxTaskCode, pcName, ulStackDepth, pvParameters, uxPriority, puxStackBuffer, pxTaskBuffer ) +#endif + +#ifndef traceRETURN_xTaskCreateStatic + #define traceRETURN_xTaskCreateStatic( xReturn ) +#endif + +#ifndef traceENTER_xTaskCreateStaticAffinitySet + #define traceENTER_xTaskCreateStaticAffinitySet( pxTaskCode, pcName, ulStackDepth, pvParameters, uxPriority, puxStackBuffer, pxTaskBuffer, uxCoreAffinityMask ) +#endif + +#ifndef traceRETURN_xTaskCreateStaticAffinitySet + #define traceRETURN_xTaskCreateStaticAffinitySet( xReturn ) +#endif + +#ifndef traceENTER_xTaskCreateRestrictedStatic + #define traceENTER_xTaskCreateRestrictedStatic( pxTaskDefinition, pxCreatedTask ) +#endif + +#ifndef traceRETURN_xTaskCreateRestrictedStatic + #define traceRETURN_xTaskCreateRestrictedStatic( xReturn ) +#endif + +#ifndef traceENTER_xTaskCreateRestrictedStaticAffinitySet + #define traceENTER_xTaskCreateRestrictedStaticAffinitySet( pxTaskDefinition, uxCoreAffinityMask, pxCreatedTask ) +#endif + +#ifndef traceRETURN_xTaskCreateRestrictedStaticAffinitySet + #define traceRETURN_xTaskCreateRestrictedStaticAffinitySet( xReturn ) +#endif + +#ifndef traceENTER_xTaskCreateRestricted + #define traceENTER_xTaskCreateRestricted( pxTaskDefinition, pxCreatedTask ) +#endif + +#ifndef traceRETURN_xTaskCreateRestricted + #define traceRETURN_xTaskCreateRestricted( xReturn ) +#endif + +#ifndef traceENTER_xTaskCreateRestrictedAffinitySet + #define traceENTER_xTaskCreateRestrictedAffinitySet( pxTaskDefinition, uxCoreAffinityMask, pxCreatedTask ) +#endif + +#ifndef traceRETURN_xTaskCreateRestrictedAffinitySet + #define traceRETURN_xTaskCreateRestrictedAffinitySet( xReturn ) +#endif + +#ifndef traceENTER_xTaskCreate + #define traceENTER_xTaskCreate( pxTaskCode, pcName, usStackDepth, pvParameters, uxPriority, pxCreatedTask ) +#endif + +#ifndef traceRETURN_xTaskCreate + #define traceRETURN_xTaskCreate( xReturn ) +#endif + +#ifndef traceENTER_xTaskCreateAffinitySet + #define traceENTER_xTaskCreateAffinitySet( pxTaskCode, pcName, usStackDepth, pvParameters, uxPriority, uxCoreAffinityMask, pxCreatedTask ) +#endif + +#ifndef traceRETURN_xTaskCreateAffinitySet + #define traceRETURN_xTaskCreateAffinitySet( xReturn ) +#endif + +#ifndef traceENTER_vTaskDelete + #define traceENTER_vTaskDelete( xTaskToDelete ) +#endif + +#ifndef traceRETURN_vTaskDelete + #define traceRETURN_vTaskDelete() +#endif + +#ifndef traceENTER_xTaskDelayUntil + #define traceENTER_xTaskDelayUntil( pxPreviousWakeTime, xTimeIncrement ) +#endif + +#ifndef traceRETURN_xTaskDelayUntil + #define traceRETURN_xTaskDelayUntil( xShouldDelay ) +#endif + +#ifndef traceENTER_vTaskDelay + #define traceENTER_vTaskDelay( xTicksToDelay ) +#endif + +#ifndef traceRETURN_vTaskDelay + #define traceRETURN_vTaskDelay() +#endif + +#ifndef traceENTER_eTaskGetState + #define traceENTER_eTaskGetState( xTask ) +#endif + +#ifndef traceRETURN_eTaskGetState + #define traceRETURN_eTaskGetState( eReturn ) +#endif + +#ifndef traceENTER_uxTaskPriorityGet + #define traceENTER_uxTaskPriorityGet( xTask ) +#endif + +#ifndef traceRETURN_uxTaskPriorityGet + #define traceRETURN_uxTaskPriorityGet( uxReturn ) +#endif + +#ifndef traceENTER_uxTaskPriorityGetFromISR + #define traceENTER_uxTaskPriorityGetFromISR( xTask ) +#endif + +#ifndef traceRETURN_uxTaskPriorityGetFromISR + #define traceRETURN_uxTaskPriorityGetFromISR( uxReturn ) +#endif + +#ifndef traceENTER_uxTaskBasePriorityGet + #define traceENTER_uxTaskBasePriorityGet( xTask ) +#endif + +#ifndef traceRETURN_uxTaskBasePriorityGet + #define traceRETURN_uxTaskBasePriorityGet( uxReturn ) +#endif + +#ifndef traceENTER_uxTaskBasePriorityGetFromISR + #define traceENTER_uxTaskBasePriorityGetFromISR( xTask ) +#endif + +#ifndef traceRETURN_uxTaskBasePriorityGetFromISR + #define traceRETURN_uxTaskBasePriorityGetFromISR( uxReturn ) +#endif + +#ifndef traceENTER_vTaskPrioritySet + #define traceENTER_vTaskPrioritySet( xTask, uxNewPriority ) +#endif + +#ifndef traceRETURN_vTaskPrioritySet + #define traceRETURN_vTaskPrioritySet() +#endif + +#ifndef traceENTER_vTaskCoreAffinitySet + #define traceENTER_vTaskCoreAffinitySet( xTask, uxCoreAffinityMask ) +#endif + +#ifndef traceRETURN_vTaskCoreAffinitySet + #define traceRETURN_vTaskCoreAffinitySet() +#endif + +#ifndef traceENTER_vTaskCoreAffinityGet + #define traceENTER_vTaskCoreAffinityGet( xTask ) +#endif + +#ifndef traceRETURN_vTaskCoreAffinityGet + #define traceRETURN_vTaskCoreAffinityGet( uxCoreAffinityMask ) +#endif + +#ifndef traceENTER_vTaskPreemptionDisable + #define traceENTER_vTaskPreemptionDisable( xTask ) +#endif + +#ifndef traceRETURN_vTaskPreemptionDisable + #define traceRETURN_vTaskPreemptionDisable() +#endif + +#ifndef traceENTER_vTaskPreemptionEnable + #define traceENTER_vTaskPreemptionEnable( xTask ) +#endif + +#ifndef traceRETURN_vTaskPreemptionEnable + #define traceRETURN_vTaskPreemptionEnable() +#endif + +#ifndef traceENTER_vTaskSuspend + #define traceENTER_vTaskSuspend( xTaskToSuspend ) +#endif + +#ifndef traceRETURN_vTaskSuspend + #define traceRETURN_vTaskSuspend() +#endif + +#ifndef traceENTER_vTaskResume + #define traceENTER_vTaskResume( xTaskToResume ) +#endif + +#ifndef traceRETURN_vTaskResume + #define traceRETURN_vTaskResume() +#endif + +#ifndef traceENTER_xTaskResumeFromISR + #define traceENTER_xTaskResumeFromISR( xTaskToResume ) +#endif + +#ifndef traceRETURN_xTaskResumeFromISR + #define traceRETURN_xTaskResumeFromISR( xYieldRequired ) +#endif + +#ifndef traceENTER_vTaskStartScheduler + #define traceENTER_vTaskStartScheduler() +#endif + +#ifndef traceRETURN_vTaskStartScheduler + #define traceRETURN_vTaskStartScheduler() +#endif + +#ifndef traceENTER_vTaskEndScheduler + #define traceENTER_vTaskEndScheduler() +#endif + +#ifndef traceRETURN_vTaskEndScheduler + #define traceRETURN_vTaskEndScheduler() +#endif + +#ifndef traceENTER_vTaskSuspendAll + #define traceENTER_vTaskSuspendAll() +#endif + +#ifndef traceRETURN_vTaskSuspendAll + #define traceRETURN_vTaskSuspendAll() +#endif + +#ifndef traceENTER_xTaskResumeAll + #define traceENTER_xTaskResumeAll() +#endif + +#ifndef traceRETURN_xTaskResumeAll + #define traceRETURN_xTaskResumeAll( xAlreadyYielded ) +#endif + +#ifndef traceENTER_xTaskGetTickCount + #define traceENTER_xTaskGetTickCount() +#endif + +#ifndef traceRETURN_xTaskGetTickCount + #define traceRETURN_xTaskGetTickCount( xTicks ) +#endif + +#ifndef traceENTER_xTaskGetTickCountFromISR + #define traceENTER_xTaskGetTickCountFromISR() +#endif + +#ifndef traceRETURN_xTaskGetTickCountFromISR + #define traceRETURN_xTaskGetTickCountFromISR( xReturn ) +#endif + +#ifndef traceENTER_uxTaskGetNumberOfTasks + #define traceENTER_uxTaskGetNumberOfTasks() +#endif + +#ifndef traceRETURN_uxTaskGetNumberOfTasks + #define traceRETURN_uxTaskGetNumberOfTasks( uxCurrentNumberOfTasks ) +#endif + +#ifndef traceENTER_pcTaskGetName + #define traceENTER_pcTaskGetName( xTaskToQuery ) +#endif + +#ifndef traceRETURN_pcTaskGetName + #define traceRETURN_pcTaskGetName( pcTaskName ) +#endif + +#ifndef traceENTER_xTaskGetHandle + #define traceENTER_xTaskGetHandle( pcNameToQuery ) +#endif + +#ifndef traceRETURN_xTaskGetHandle + #define traceRETURN_xTaskGetHandle( pxTCB ) +#endif + +#ifndef traceENTER_xTaskGetStaticBuffers + #define traceENTER_xTaskGetStaticBuffers( xTask, ppuxStackBuffer, ppxTaskBuffer ) +#endif + +#ifndef traceRETURN_xTaskGetStaticBuffers + #define traceRETURN_xTaskGetStaticBuffers( xReturn ) +#endif + +#ifndef traceENTER_uxTaskGetSystemState + #define traceENTER_uxTaskGetSystemState( pxTaskStatusArray, uxArraySize, pulTotalRunTime ) +#endif + +#ifndef traceRETURN_uxTaskGetSystemState + #define traceRETURN_uxTaskGetSystemState( uxTask ) +#endif + +#if ( configNUMBER_OF_CORES == 1 ) + #ifndef traceENTER_xTaskGetIdleTaskHandle + #define traceENTER_xTaskGetIdleTaskHandle() + #endif +#endif + +#if ( configNUMBER_OF_CORES == 1 ) + #ifndef traceRETURN_xTaskGetIdleTaskHandle + #define traceRETURN_xTaskGetIdleTaskHandle( xIdleTaskHandle ) + #endif +#endif + +#ifndef traceENTER_xTaskGetIdleTaskHandleForCore + #define traceENTER_xTaskGetIdleTaskHandleForCore( xCoreID ) +#endif + +#ifndef traceRETURN_xTaskGetIdleTaskHandleForCore + #define traceRETURN_xTaskGetIdleTaskHandleForCore( xIdleTaskHandle ) +#endif + +#ifndef traceENTER_vTaskStepTick + #define traceENTER_vTaskStepTick( xTicksToJump ) +#endif + +#ifndef traceRETURN_vTaskStepTick + #define traceRETURN_vTaskStepTick() +#endif + +#ifndef traceENTER_xTaskCatchUpTicks + #define traceENTER_xTaskCatchUpTicks( xTicksToCatchUp ) +#endif + +#ifndef traceRETURN_xTaskCatchUpTicks + #define traceRETURN_xTaskCatchUpTicks( xYieldOccurred ) +#endif + +#ifndef traceENTER_xTaskAbortDelay + #define traceENTER_xTaskAbortDelay( xTask ) +#endif + +#ifndef traceRETURN_xTaskAbortDelay + #define traceRETURN_xTaskAbortDelay( xReturn ) +#endif + +#ifndef traceENTER_xTaskIncrementTick + #define traceENTER_xTaskIncrementTick() +#endif + +#ifndef traceRETURN_xTaskIncrementTick + #define traceRETURN_xTaskIncrementTick( xSwitchRequired ) +#endif + +#ifndef traceENTER_vTaskSetApplicationTaskTag + #define traceENTER_vTaskSetApplicationTaskTag( xTask, pxHookFunction ) +#endif + +#ifndef traceRETURN_vTaskSetApplicationTaskTag + #define traceRETURN_vTaskSetApplicationTaskTag() +#endif + +#ifndef traceENTER_xTaskGetApplicationTaskTag + #define traceENTER_xTaskGetApplicationTaskTag( xTask ) +#endif + +#ifndef traceRETURN_xTaskGetApplicationTaskTag + #define traceRETURN_xTaskGetApplicationTaskTag( xReturn ) +#endif + +#ifndef traceENTER_xTaskGetApplicationTaskTagFromISR + #define traceENTER_xTaskGetApplicationTaskTagFromISR( xTask ) +#endif + +#ifndef traceRETURN_xTaskGetApplicationTaskTagFromISR + #define traceRETURN_xTaskGetApplicationTaskTagFromISR( xReturn ) +#endif + +#ifndef traceENTER_xTaskCallApplicationTaskHook + #define traceENTER_xTaskCallApplicationTaskHook( xTask, pvParameter ) +#endif + +#ifndef traceRETURN_xTaskCallApplicationTaskHook + #define traceRETURN_xTaskCallApplicationTaskHook( xReturn ) +#endif + +#ifndef traceENTER_vTaskSwitchContext + #define traceENTER_vTaskSwitchContext() +#endif + +#ifndef traceRETURN_vTaskSwitchContext + #define traceRETURN_vTaskSwitchContext() +#endif + +#ifndef traceENTER_vTaskPlaceOnEventList + #define traceENTER_vTaskPlaceOnEventList( pxEventList, xTicksToWait ) +#endif + +#ifndef traceRETURN_vTaskPlaceOnEventList + #define traceRETURN_vTaskPlaceOnEventList() +#endif + +#ifndef traceENTER_vTaskPlaceOnUnorderedEventList + #define traceENTER_vTaskPlaceOnUnorderedEventList( pxEventList, xItemValue, xTicksToWait ) +#endif + +#ifndef traceRETURN_vTaskPlaceOnUnorderedEventList + #define traceRETURN_vTaskPlaceOnUnorderedEventList() +#endif + +#ifndef traceENTER_vTaskPlaceOnEventListRestricted + #define traceENTER_vTaskPlaceOnEventListRestricted( pxEventList, xTicksToWait, xWaitIndefinitely ) +#endif + +#ifndef traceRETURN_vTaskPlaceOnEventListRestricted + #define traceRETURN_vTaskPlaceOnEventListRestricted() +#endif + +#ifndef traceENTER_xTaskRemoveFromEventList + #define traceENTER_xTaskRemoveFromEventList( pxEventList ) +#endif + +#ifndef traceRETURN_xTaskRemoveFromEventList + #define traceRETURN_xTaskRemoveFromEventList( xReturn ) +#endif + +#ifndef traceENTER_vTaskRemoveFromUnorderedEventList + #define traceENTER_vTaskRemoveFromUnorderedEventList( pxEventListItem, xItemValue ) +#endif + +#ifndef traceRETURN_vTaskRemoveFromUnorderedEventList + #define traceRETURN_vTaskRemoveFromUnorderedEventList() +#endif + +#ifndef traceENTER_vTaskSetTimeOutState + #define traceENTER_vTaskSetTimeOutState( pxTimeOut ) +#endif + +#ifndef traceRETURN_vTaskSetTimeOutState + #define traceRETURN_vTaskSetTimeOutState() +#endif + +#ifndef traceENTER_vTaskInternalSetTimeOutState + #define traceENTER_vTaskInternalSetTimeOutState( pxTimeOut ) +#endif + +#ifndef traceRETURN_vTaskInternalSetTimeOutState + #define traceRETURN_vTaskInternalSetTimeOutState() +#endif + +#ifndef traceENTER_xTaskCheckForTimeOut + #define traceENTER_xTaskCheckForTimeOut( pxTimeOut, pxTicksToWait ) +#endif + +#ifndef traceRETURN_xTaskCheckForTimeOut + #define traceRETURN_xTaskCheckForTimeOut( xReturn ) +#endif + +#ifndef traceENTER_vTaskMissedYield + #define traceENTER_vTaskMissedYield() +#endif + +#ifndef traceRETURN_vTaskMissedYield + #define traceRETURN_vTaskMissedYield() +#endif + +#ifndef traceENTER_uxTaskGetTaskNumber + #define traceENTER_uxTaskGetTaskNumber( xTask ) +#endif + +#ifndef traceRETURN_uxTaskGetTaskNumber + #define traceRETURN_uxTaskGetTaskNumber( uxReturn ) +#endif + +#ifndef traceENTER_vTaskSetTaskNumber + #define traceENTER_vTaskSetTaskNumber( xTask, uxHandle ) +#endif + +#ifndef traceRETURN_vTaskSetTaskNumber + #define traceRETURN_vTaskSetTaskNumber() +#endif + +#ifndef traceENTER_eTaskConfirmSleepModeStatus + #define traceENTER_eTaskConfirmSleepModeStatus() +#endif + +#ifndef traceRETURN_eTaskConfirmSleepModeStatus + #define traceRETURN_eTaskConfirmSleepModeStatus( eReturn ) +#endif + +#ifndef traceENTER_vTaskSetThreadLocalStoragePointer + #define traceENTER_vTaskSetThreadLocalStoragePointer( xTaskToSet, xIndex, pvValue ) +#endif + +#ifndef traceRETURN_vTaskSetThreadLocalStoragePointer + #define traceRETURN_vTaskSetThreadLocalStoragePointer() +#endif + +#ifndef traceENTER_pvTaskGetThreadLocalStoragePointer + #define traceENTER_pvTaskGetThreadLocalStoragePointer( xTaskToQuery, xIndex ) +#endif + +#ifndef traceRETURN_pvTaskGetThreadLocalStoragePointer + #define traceRETURN_pvTaskGetThreadLocalStoragePointer( pvReturn ) +#endif + +#ifndef traceENTER_vTaskAllocateMPURegions + #define traceENTER_vTaskAllocateMPURegions( xTaskToModify, pxRegions ) +#endif + +#ifndef traceRETURN_vTaskAllocateMPURegions + #define traceRETURN_vTaskAllocateMPURegions() +#endif + +#ifndef traceENTER_vTaskGetInfo + #define traceENTER_vTaskGetInfo( xTask, pxTaskStatus, xGetFreeStackSpace, eState ) +#endif + +#ifndef traceRETURN_vTaskGetInfo + #define traceRETURN_vTaskGetInfo() +#endif + +#ifndef traceENTER_uxTaskGetStackHighWaterMark2 + #define traceENTER_uxTaskGetStackHighWaterMark2( xTask ) +#endif + +#ifndef traceRETURN_uxTaskGetStackHighWaterMark2 + #define traceRETURN_uxTaskGetStackHighWaterMark2( uxReturn ) +#endif + +#ifndef traceENTER_uxTaskGetStackHighWaterMark + #define traceENTER_uxTaskGetStackHighWaterMark( xTask ) +#endif + +#ifndef traceRETURN_uxTaskGetStackHighWaterMark + #define traceRETURN_uxTaskGetStackHighWaterMark( uxReturn ) +#endif + +#ifndef traceENTER_xTaskGetCurrentTaskHandle + #define traceENTER_xTaskGetCurrentTaskHandle() +#endif + +#ifndef traceRETURN_xTaskGetCurrentTaskHandle + #define traceRETURN_xTaskGetCurrentTaskHandle( xReturn ) +#endif + +#ifndef traceENTER_xTaskGetCurrentTaskHandleForCore + #define traceENTER_xTaskGetCurrentTaskHandleForCore( xCoreID ) +#endif + +#ifndef traceRETURN_xTaskGetCurrentTaskHandleForCore + #define traceRETURN_xTaskGetCurrentTaskHandleForCore( xReturn ) +#endif + +#ifndef traceENTER_xTaskGetSchedulerState + #define traceENTER_xTaskGetSchedulerState() +#endif + +#ifndef traceRETURN_xTaskGetSchedulerState + #define traceRETURN_xTaskGetSchedulerState( xReturn ) +#endif + +#ifndef traceENTER_xTaskPriorityInherit + #define traceENTER_xTaskPriorityInherit( pxMutexHolder ) +#endif + +#ifndef traceRETURN_xTaskPriorityInherit + #define traceRETURN_xTaskPriorityInherit( xReturn ) +#endif + +#ifndef traceENTER_xTaskPriorityDisinherit + #define traceENTER_xTaskPriorityDisinherit( pxMutexHolder ) +#endif + +#ifndef traceRETURN_xTaskPriorityDisinherit + #define traceRETURN_xTaskPriorityDisinherit( xReturn ) +#endif + +#ifndef traceENTER_vTaskPriorityDisinheritAfterTimeout + #define traceENTER_vTaskPriorityDisinheritAfterTimeout( pxMutexHolder, uxHighestPriorityWaitingTask ) +#endif + +#ifndef traceRETURN_vTaskPriorityDisinheritAfterTimeout + #define traceRETURN_vTaskPriorityDisinheritAfterTimeout() +#endif + +#ifndef traceENTER_vTaskYieldWithinAPI + #define traceENTER_vTaskYieldWithinAPI() +#endif + +#ifndef traceRETURN_vTaskYieldWithinAPI + #define traceRETURN_vTaskYieldWithinAPI() +#endif + +#ifndef traceENTER_vTaskEnterCritical + #define traceENTER_vTaskEnterCritical() +#endif + +#ifndef traceRETURN_vTaskEnterCritical + #define traceRETURN_vTaskEnterCritical() +#endif + +#ifndef traceENTER_vTaskEnterCriticalFromISR + #define traceENTER_vTaskEnterCriticalFromISR() +#endif + +#ifndef traceRETURN_vTaskEnterCriticalFromISR + #define traceRETURN_vTaskEnterCriticalFromISR( uxSavedInterruptStatus ) +#endif + +#ifndef traceENTER_vTaskExitCritical + #define traceENTER_vTaskExitCritical() +#endif + +#ifndef traceRETURN_vTaskExitCritical + #define traceRETURN_vTaskExitCritical() +#endif + +#ifndef traceENTER_vTaskExitCriticalFromISR + #define traceENTER_vTaskExitCriticalFromISR( uxSavedInterruptStatus ) +#endif + +#ifndef traceRETURN_vTaskExitCriticalFromISR + #define traceRETURN_vTaskExitCriticalFromISR() +#endif + +#ifndef traceENTER_vTaskListTasks + #define traceENTER_vTaskListTasks( pcWriteBuffer, uxBufferLength ) +#endif + +#ifndef traceRETURN_vTaskListTasks + #define traceRETURN_vTaskListTasks() +#endif + +#ifndef traceENTER_vTaskGetRunTimeStatistics + #define traceENTER_vTaskGetRunTimeStatistics( pcWriteBuffer, uxBufferLength ) +#endif + +#ifndef traceRETURN_vTaskGetRunTimeStatistics + #define traceRETURN_vTaskGetRunTimeStatistics() +#endif + +#ifndef traceENTER_uxTaskResetEventItemValue + #define traceENTER_uxTaskResetEventItemValue() +#endif + +#ifndef traceRETURN_uxTaskResetEventItemValue + #define traceRETURN_uxTaskResetEventItemValue( uxReturn ) +#endif + +#ifndef traceENTER_pvTaskIncrementMutexHeldCount + #define traceENTER_pvTaskIncrementMutexHeldCount() +#endif + +#ifndef traceRETURN_pvTaskIncrementMutexHeldCount + #define traceRETURN_pvTaskIncrementMutexHeldCount( pxTCB ) +#endif + +#ifndef traceENTER_ulTaskGenericNotifyTake + #define traceENTER_ulTaskGenericNotifyTake( uxIndexToWaitOn, xClearCountOnExit, xTicksToWait ) +#endif + +#ifndef traceRETURN_ulTaskGenericNotifyTake + #define traceRETURN_ulTaskGenericNotifyTake( ulReturn ) +#endif + +#ifndef traceENTER_xTaskGenericNotifyWait + #define traceENTER_xTaskGenericNotifyWait( uxIndexToWaitOn, ulBitsToClearOnEntry, ulBitsToClearOnExit, pulNotificationValue, xTicksToWait ) +#endif + +#ifndef traceRETURN_xTaskGenericNotifyWait + #define traceRETURN_xTaskGenericNotifyWait( xReturn ) +#endif + +#ifndef traceENTER_xTaskGenericNotify + #define traceENTER_xTaskGenericNotify( xTaskToNotify, uxIndexToNotify, ulValue, eAction, pulPreviousNotificationValue ) +#endif + +#ifndef traceRETURN_xTaskGenericNotify + #define traceRETURN_xTaskGenericNotify( xReturn ) +#endif + +#ifndef traceENTER_xTaskGenericNotifyFromISR + #define traceENTER_xTaskGenericNotifyFromISR( xTaskToNotify, uxIndexToNotify, ulValue, eAction, pulPreviousNotificationValue, pxHigherPriorityTaskWoken ) +#endif + +#ifndef traceRETURN_xTaskGenericNotifyFromISR + #define traceRETURN_xTaskGenericNotifyFromISR( xReturn ) +#endif + +#ifndef traceENTER_vTaskGenericNotifyGiveFromISR + #define traceENTER_vTaskGenericNotifyGiveFromISR( xTaskToNotify, uxIndexToNotify, pxHigherPriorityTaskWoken ) +#endif + +#ifndef traceRETURN_vTaskGenericNotifyGiveFromISR + #define traceRETURN_vTaskGenericNotifyGiveFromISR() +#endif + +#ifndef traceENTER_xTaskGenericNotifyStateClear + #define traceENTER_xTaskGenericNotifyStateClear( xTask, uxIndexToClear ) +#endif + +#ifndef traceRETURN_xTaskGenericNotifyStateClear + #define traceRETURN_xTaskGenericNotifyStateClear( xReturn ) +#endif + +#ifndef traceENTER_ulTaskGenericNotifyValueClear + #define traceENTER_ulTaskGenericNotifyValueClear( xTask, uxIndexToClear, ulBitsToClear ) +#endif + +#ifndef traceRETURN_ulTaskGenericNotifyValueClear + #define traceRETURN_ulTaskGenericNotifyValueClear( ulReturn ) +#endif + +#ifndef traceENTER_ulTaskGetRunTimeCounter + #define traceENTER_ulTaskGetRunTimeCounter( xTask ) +#endif + +#ifndef traceRETURN_ulTaskGetRunTimeCounter + #define traceRETURN_ulTaskGetRunTimeCounter( ulRunTimeCounter ) +#endif + +#ifndef traceENTER_ulTaskGetRunTimePercent + #define traceENTER_ulTaskGetRunTimePercent( xTask ) +#endif + +#ifndef traceRETURN_ulTaskGetRunTimePercent + #define traceRETURN_ulTaskGetRunTimePercent( ulReturn ) +#endif + +#ifndef traceENTER_ulTaskGetIdleRunTimeCounter + #define traceENTER_ulTaskGetIdleRunTimeCounter() +#endif + +#ifndef traceRETURN_ulTaskGetIdleRunTimeCounter + #define traceRETURN_ulTaskGetIdleRunTimeCounter( ulReturn ) +#endif + +#ifndef traceENTER_ulTaskGetIdleRunTimePercent + #define traceENTER_ulTaskGetIdleRunTimePercent() +#endif + +#ifndef traceRETURN_ulTaskGetIdleRunTimePercent + #define traceRETURN_ulTaskGetIdleRunTimePercent( ulReturn ) +#endif + +#ifndef traceENTER_xTaskGetMPUSettings + #define traceENTER_xTaskGetMPUSettings( xTask ) +#endif + +#ifndef traceRETURN_xTaskGetMPUSettings + #define traceRETURN_xTaskGetMPUSettings( xMPUSettings ) +#endif + +#ifndef traceENTER_xStreamBufferGenericCreate + #define traceENTER_xStreamBufferGenericCreate( xBufferSizeBytes, xTriggerLevelBytes, xIsMessageBuffer, pxSendCompletedCallback, pxReceiveCompletedCallback ) +#endif + +#ifndef traceRETURN_xStreamBufferGenericCreate + #define traceRETURN_xStreamBufferGenericCreate( pvAllocatedMemory ) +#endif + +#ifndef traceENTER_xStreamBufferGenericCreateStatic + #define traceENTER_xStreamBufferGenericCreateStatic( xBufferSizeBytes, xTriggerLevelBytes, xIsMessageBuffer, pucStreamBufferStorageArea, pxStaticStreamBuffer, pxSendCompletedCallback, pxReceiveCompletedCallback ) +#endif + +#ifndef traceRETURN_xStreamBufferGenericCreateStatic + #define traceRETURN_xStreamBufferGenericCreateStatic( xReturn ) +#endif + +#ifndef traceENTER_xStreamBufferGetStaticBuffers + #define traceENTER_xStreamBufferGetStaticBuffers( xStreamBuffer, ppucStreamBufferStorageArea, ppxStaticStreamBuffer ) +#endif + +#ifndef traceRETURN_xStreamBufferGetStaticBuffers + #define traceRETURN_xStreamBufferGetStaticBuffers( xReturn ) +#endif + +#ifndef traceENTER_vStreamBufferDelete + #define traceENTER_vStreamBufferDelete( xStreamBuffer ) +#endif + +#ifndef traceRETURN_vStreamBufferDelete + #define traceRETURN_vStreamBufferDelete() +#endif + +#ifndef traceENTER_xStreamBufferReset + #define traceENTER_xStreamBufferReset( xStreamBuffer ) +#endif + +#ifndef traceRETURN_xStreamBufferReset + #define traceRETURN_xStreamBufferReset( xReturn ) +#endif + +#ifndef traceENTER_xStreamBufferSetTriggerLevel + #define traceENTER_xStreamBufferSetTriggerLevel( xStreamBuffer, xTriggerLevel ) +#endif + +#ifndef traceRETURN_xStreamBufferSetTriggerLevel + #define traceRETURN_xStreamBufferSetTriggerLevel( xReturn ) +#endif + +#ifndef traceENTER_xStreamBufferSpacesAvailable + #define traceENTER_xStreamBufferSpacesAvailable( xStreamBuffer ) +#endif + +#ifndef traceRETURN_xStreamBufferSpacesAvailable + #define traceRETURN_xStreamBufferSpacesAvailable( xSpace ) +#endif + +#ifndef traceENTER_xStreamBufferBytesAvailable + #define traceENTER_xStreamBufferBytesAvailable( xStreamBuffer ) +#endif + +#ifndef traceRETURN_xStreamBufferBytesAvailable + #define traceRETURN_xStreamBufferBytesAvailable( xReturn ) +#endif + +#ifndef traceENTER_xStreamBufferSend + #define traceENTER_xStreamBufferSend( xStreamBuffer, pvTxData, xDataLengthBytes, xTicksToWait ) +#endif + +#ifndef traceRETURN_xStreamBufferSend + #define traceRETURN_xStreamBufferSend( xReturn ) +#endif + +#ifndef traceENTER_xStreamBufferSendFromISR + #define traceENTER_xStreamBufferSendFromISR( xStreamBuffer, pvTxData, xDataLengthBytes, pxHigherPriorityTaskWoken ) +#endif + +#ifndef traceRETURN_xStreamBufferSendFromISR + #define traceRETURN_xStreamBufferSendFromISR( xReturn ) +#endif + +#ifndef traceENTER_xStreamBufferReceive + #define traceENTER_xStreamBufferReceive( xStreamBuffer, pvRxData, xBufferLengthBytes, xTicksToWait ) +#endif + +#ifndef traceRETURN_xStreamBufferReceive + #define traceRETURN_xStreamBufferReceive( xReceivedLength ) +#endif + +#ifndef traceENTER_xStreamBufferNextMessageLengthBytes + #define traceENTER_xStreamBufferNextMessageLengthBytes( xStreamBuffer ) +#endif + +#ifndef traceRETURN_xStreamBufferNextMessageLengthBytes + #define traceRETURN_xStreamBufferNextMessageLengthBytes( xReturn ) +#endif + +#ifndef traceENTER_xStreamBufferReceiveFromISR + #define traceENTER_xStreamBufferReceiveFromISR( xStreamBuffer, pvRxData, xBufferLengthBytes, pxHigherPriorityTaskWoken ) +#endif + +#ifndef traceRETURN_xStreamBufferReceiveFromISR + #define traceRETURN_xStreamBufferReceiveFromISR( xReceivedLength ) +#endif + +#ifndef traceENTER_xStreamBufferIsEmpty + #define traceENTER_xStreamBufferIsEmpty( xStreamBuffer ) +#endif + +#ifndef traceRETURN_xStreamBufferIsEmpty + #define traceRETURN_xStreamBufferIsEmpty( xReturn ) +#endif + +#ifndef traceENTER_xStreamBufferIsFull + #define traceENTER_xStreamBufferIsFull( xStreamBuffer ) +#endif + +#ifndef traceRETURN_xStreamBufferIsFull + #define traceRETURN_xStreamBufferIsFull( xReturn ) +#endif + +#ifndef traceENTER_xStreamBufferSendCompletedFromISR + #define traceENTER_xStreamBufferSendCompletedFromISR( xStreamBuffer, pxHigherPriorityTaskWoken ) +#endif + +#ifndef traceRETURN_xStreamBufferSendCompletedFromISR + #define traceRETURN_xStreamBufferSendCompletedFromISR( xReturn ) +#endif + +#ifndef traceENTER_xStreamBufferReceiveCompletedFromISR + #define traceENTER_xStreamBufferReceiveCompletedFromISR( xStreamBuffer, pxHigherPriorityTaskWoken ) +#endif + +#ifndef traceRETURN_xStreamBufferReceiveCompletedFromISR + #define traceRETURN_xStreamBufferReceiveCompletedFromISR( xReturn ) +#endif + +#ifndef traceENTER_uxStreamBufferGetStreamBufferNumber + #define traceENTER_uxStreamBufferGetStreamBufferNumber( xStreamBuffer ) +#endif + +#ifndef traceRETURN_uxStreamBufferGetStreamBufferNumber + #define traceRETURN_uxStreamBufferGetStreamBufferNumber( uxStreamBufferNumber ) +#endif + +#ifndef traceENTER_vStreamBufferSetStreamBufferNumber + #define traceENTER_vStreamBufferSetStreamBufferNumber( xStreamBuffer, uxStreamBufferNumber ) +#endif + +#ifndef traceRETURN_vStreamBufferSetStreamBufferNumber + #define traceRETURN_vStreamBufferSetStreamBufferNumber() +#endif + +#ifndef traceENTER_ucStreamBufferGetStreamBufferType + #define traceENTER_ucStreamBufferGetStreamBufferType( xStreamBuffer ) +#endif + +#ifndef traceRETURN_ucStreamBufferGetStreamBufferType + #define traceRETURN_ucStreamBufferGetStreamBufferType( ucStreamBufferType ) +#endif + +#ifndef traceENTER_vListInitialise + #define traceENTER_vListInitialise( pxList ) +#endif + +#ifndef traceRETURN_vListInitialise + #define traceRETURN_vListInitialise() +#endif + +#ifndef traceENTER_vListInitialiseItem + #define traceENTER_vListInitialiseItem( pxItem ) +#endif + +#ifndef traceRETURN_vListInitialiseItem + #define traceRETURN_vListInitialiseItem() +#endif + +#ifndef traceENTER_vListInsertEnd + #define traceENTER_vListInsertEnd( pxList, pxNewListItem ) +#endif + +#ifndef traceRETURN_vListInsertEnd + #define traceRETURN_vListInsertEnd() +#endif + +#ifndef traceENTER_vListInsert + #define traceENTER_vListInsert( pxList, pxNewListItem ) +#endif + +#ifndef traceRETURN_vListInsert + #define traceRETURN_vListInsert() +#endif + +#ifndef traceENTER_uxListRemove + #define traceENTER_uxListRemove( pxItemToRemove ) +#endif + +#ifndef traceRETURN_uxListRemove + #define traceRETURN_uxListRemove( uxNumberOfItems ) +#endif + +#ifndef traceENTER_xCoRoutineCreate + #define traceENTER_xCoRoutineCreate( pxCoRoutineCode, uxPriority, uxIndex ) +#endif + +#ifndef traceRETURN_xCoRoutineCreate + #define traceRETURN_xCoRoutineCreate( xReturn ) +#endif + +#ifndef traceENTER_vCoRoutineAddToDelayedList + #define traceENTER_vCoRoutineAddToDelayedList( xTicksToDelay, pxEventList ) +#endif + +#ifndef traceRETURN_vCoRoutineAddToDelayedList + #define traceRETURN_vCoRoutineAddToDelayedList() +#endif + +#ifndef traceENTER_vCoRoutineSchedule + #define traceENTER_vCoRoutineSchedule() +#endif + +#ifndef traceRETURN_vCoRoutineSchedule + #define traceRETURN_vCoRoutineSchedule() +#endif + +#ifndef traceENTER_xCoRoutineRemoveFromEventList + #define traceENTER_xCoRoutineRemoveFromEventList( pxEventList ) +#endif + +#ifndef traceRETURN_xCoRoutineRemoveFromEventList + #define traceRETURN_xCoRoutineRemoveFromEventList( xReturn ) +#endif + +#ifndef configGENERATE_RUN_TIME_STATS + #define configGENERATE_RUN_TIME_STATS 0 +#endif + +#if ( configGENERATE_RUN_TIME_STATS == 1 ) + + #ifndef portCONFIGURE_TIMER_FOR_RUN_TIME_STATS + #error If configGENERATE_RUN_TIME_STATS is defined then portCONFIGURE_TIMER_FOR_RUN_TIME_STATS must also be defined. portCONFIGURE_TIMER_FOR_RUN_TIME_STATS should call a port layer function to setup a peripheral timer/counter that can then be used as the run time counter time base. + #endif /* portCONFIGURE_TIMER_FOR_RUN_TIME_STATS */ + + #ifndef portGET_RUN_TIME_COUNTER_VALUE + #ifndef portALT_GET_RUN_TIME_COUNTER_VALUE + #error If configGENERATE_RUN_TIME_STATS is defined then either portGET_RUN_TIME_COUNTER_VALUE or portALT_GET_RUN_TIME_COUNTER_VALUE must also be defined. See the examples provided and the FreeRTOS web site for more information. + #endif /* portALT_GET_RUN_TIME_COUNTER_VALUE */ + #endif /* portGET_RUN_TIME_COUNTER_VALUE */ + +#endif /* configGENERATE_RUN_TIME_STATS */ + +#ifndef portCONFIGURE_TIMER_FOR_RUN_TIME_STATS + #define portCONFIGURE_TIMER_FOR_RUN_TIME_STATS() +#endif + +#ifndef configUSE_MALLOC_FAILED_HOOK + #define configUSE_MALLOC_FAILED_HOOK 0 +#endif + +#ifndef portPRIVILEGE_BIT + #define portPRIVILEGE_BIT ( ( UBaseType_t ) 0x00 ) +#endif + +#ifndef portYIELD_WITHIN_API + #define portYIELD_WITHIN_API portYIELD +#endif + +#ifndef portSUPPRESS_TICKS_AND_SLEEP + #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime ) +#endif + +#ifndef configEXPECTED_IDLE_TIME_BEFORE_SLEEP + #define configEXPECTED_IDLE_TIME_BEFORE_SLEEP 2 +#endif + +#if configEXPECTED_IDLE_TIME_BEFORE_SLEEP < 2 + #error configEXPECTED_IDLE_TIME_BEFORE_SLEEP must not be less than 2 +#endif + +#ifndef configUSE_TICKLESS_IDLE + #define configUSE_TICKLESS_IDLE 0 +#endif + +#ifndef configPRE_SUPPRESS_TICKS_AND_SLEEP_PROCESSING + #define configPRE_SUPPRESS_TICKS_AND_SLEEP_PROCESSING( x ) +#endif + +#ifndef configPRE_SLEEP_PROCESSING + #define configPRE_SLEEP_PROCESSING( x ) +#endif + +#ifndef configPOST_SLEEP_PROCESSING + #define configPOST_SLEEP_PROCESSING( x ) +#endif + +#ifndef configUSE_QUEUE_SETS + #define configUSE_QUEUE_SETS 0 +#endif + +#ifndef portTASK_USES_FLOATING_POINT + #define portTASK_USES_FLOATING_POINT() +#endif + +#ifndef portALLOCATE_SECURE_CONTEXT + #define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize ) +#endif + +#ifndef portDONT_DISCARD + #define portDONT_DISCARD +#endif + +#ifndef configUSE_TIME_SLICING + #define configUSE_TIME_SLICING 1 +#endif + +#ifndef configINCLUDE_APPLICATION_DEFINED_PRIVILEGED_FUNCTIONS + #define configINCLUDE_APPLICATION_DEFINED_PRIVILEGED_FUNCTIONS 0 +#endif + +#ifndef configUSE_STATS_FORMATTING_FUNCTIONS + #define configUSE_STATS_FORMATTING_FUNCTIONS 0 +#endif + +#ifndef portASSERT_IF_INTERRUPT_PRIORITY_INVALID + #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() +#endif + +#ifndef configUSE_TRACE_FACILITY + #define configUSE_TRACE_FACILITY 0 +#endif + +#ifndef mtCOVERAGE_TEST_MARKER + #define mtCOVERAGE_TEST_MARKER() +#endif + +#ifndef mtCOVERAGE_TEST_DELAY + #define mtCOVERAGE_TEST_DELAY() +#endif + +#ifndef portASSERT_IF_IN_ISR + #define portASSERT_IF_IN_ISR() +#endif + +#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION + #define configUSE_PORT_OPTIMISED_TASK_SELECTION 0 +#endif + +#ifndef configAPPLICATION_ALLOCATED_HEAP + #define configAPPLICATION_ALLOCATED_HEAP 0 +#endif + +#ifndef configENABLE_HEAP_PROTECTOR + #define configENABLE_HEAP_PROTECTOR 0 +#endif + +#ifndef configUSE_TASK_NOTIFICATIONS + #define configUSE_TASK_NOTIFICATIONS 1 +#endif + +#ifndef configTASK_NOTIFICATION_ARRAY_ENTRIES + #define configTASK_NOTIFICATION_ARRAY_ENTRIES 1 +#endif + +#if configTASK_NOTIFICATION_ARRAY_ENTRIES < 1 + #error configTASK_NOTIFICATION_ARRAY_ENTRIES must be at least 1 +#endif + +#ifndef configUSE_POSIX_ERRNO + #define configUSE_POSIX_ERRNO 0 +#endif + +#ifndef configUSE_SB_COMPLETED_CALLBACK + +/* By default per-instance callbacks are not enabled for stream buffer or message buffer. */ + #define configUSE_SB_COMPLETED_CALLBACK 0 +#endif + +#ifndef portTICK_TYPE_IS_ATOMIC + #define portTICK_TYPE_IS_ATOMIC 0 +#endif + +#ifndef configSUPPORT_STATIC_ALLOCATION + /* Defaults to 0 for backward compatibility. */ + #define configSUPPORT_STATIC_ALLOCATION 0 +#endif + +#ifndef configKERNEL_PROVIDED_STATIC_MEMORY + #define configKERNEL_PROVIDED_STATIC_MEMORY 0 +#endif + +#ifndef configSUPPORT_DYNAMIC_ALLOCATION + /* Defaults to 1 for backward compatibility. */ + #define configSUPPORT_DYNAMIC_ALLOCATION 1 +#endif + +#if ( ( configUSE_STATS_FORMATTING_FUNCTIONS > 0 ) && ( configSUPPORT_DYNAMIC_ALLOCATION != 1 ) ) + #error configUSE_STATS_FORMATTING_FUNCTIONS cannot be used without dynamic allocation, but configSUPPORT_DYNAMIC_ALLOCATION is not set to 1. +#endif + +#if ( configUSE_STATS_FORMATTING_FUNCTIONS > 0 ) + #if ( ( configUSE_TRACE_FACILITY != 1 ) && ( configGENERATE_RUN_TIME_STATS != 1 ) ) + #error configUSE_STATS_FORMATTING_FUNCTIONS is 1 but the functions it enables are not used because neither configUSE_TRACE_FACILITY or configGENERATE_RUN_TIME_STATS are 1. Set configUSE_STATS_FORMATTING_FUNCTIONS to 0 in FreeRTOSConfig.h. + #endif +#endif + +#ifndef configSTATS_BUFFER_MAX_LENGTH + #define configSTATS_BUFFER_MAX_LENGTH 0xFFFF +#endif + +#ifndef configSTACK_DEPTH_TYPE + +/* Defaults to uint16_t for backward compatibility, but can be overridden + * in FreeRTOSConfig.h if uint16_t is too restrictive. */ + #define configSTACK_DEPTH_TYPE uint16_t +#endif + +#ifndef configRUN_TIME_COUNTER_TYPE + +/* Defaults to uint32_t for backward compatibility, but can be overridden in + * FreeRTOSConfig.h if uint32_t is too restrictive. */ + + #define configRUN_TIME_COUNTER_TYPE uint32_t +#endif + +#ifndef configMESSAGE_BUFFER_LENGTH_TYPE + +/* Defaults to size_t for backward compatibility, but can be overridden + * in FreeRTOSConfig.h if lengths will always be less than the number of bytes + * in a size_t. */ + #define configMESSAGE_BUFFER_LENGTH_TYPE size_t +#endif + +/* Sanity check the configuration. */ +#if ( ( configSUPPORT_STATIC_ALLOCATION == 0 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 0 ) ) + #error configSUPPORT_STATIC_ALLOCATION and configSUPPORT_DYNAMIC_ALLOCATION cannot both be 0, but can both be 1. +#endif + +#if ( ( configUSE_RECURSIVE_MUTEXES == 1 ) && ( configUSE_MUTEXES != 1 ) ) + #error configUSE_MUTEXES must be set to 1 to use recursive mutexes +#endif + +#if ( ( configRUN_MULTIPLE_PRIORITIES == 0 ) && ( configUSE_TASK_PREEMPTION_DISABLE != 0 ) ) + #error configRUN_MULTIPLE_PRIORITIES must be set to 1 to use task preemption disable +#endif + +#if ( ( configUSE_PREEMPTION == 0 ) && ( configUSE_TASK_PREEMPTION_DISABLE != 0 ) ) + #error configUSE_PREEMPTION must be set to 1 to use task preemption disable +#endif + +#if ( ( configNUMBER_OF_CORES == 1 ) && ( configUSE_TASK_PREEMPTION_DISABLE != 0 ) ) + #error configUSE_TASK_PREEMPTION_DISABLE is not supported in single core FreeRTOS +#endif + +#if ( ( configNUMBER_OF_CORES == 1 ) && ( configUSE_CORE_AFFINITY != 0 ) ) + #error configUSE_CORE_AFFINITY is not supported in single core FreeRTOS +#endif + +#if ( ( configNUMBER_OF_CORES > 1 ) && ( configUSE_PORT_OPTIMISED_TASK_SELECTION != 0 ) ) + #error configUSE_PORT_OPTIMISED_TASK_SELECTION is not supported in SMP FreeRTOS +#endif + +#ifndef configINITIAL_TICK_COUNT + #define configINITIAL_TICK_COUNT 0 +#endif + +#if ( portTICK_TYPE_IS_ATOMIC == 0 ) + +/* Either variables of tick type cannot be read atomically, or + * portTICK_TYPE_IS_ATOMIC was not set - map the critical sections used when + * the tick count is returned to the standard critical section macros. */ + #define portTICK_TYPE_ENTER_CRITICAL() portENTER_CRITICAL() + #define portTICK_TYPE_EXIT_CRITICAL() portEXIT_CRITICAL() + #define portTICK_TYPE_SET_INTERRUPT_MASK_FROM_ISR() portSET_INTERRUPT_MASK_FROM_ISR() + #define portTICK_TYPE_CLEAR_INTERRUPT_MASK_FROM_ISR( x ) portCLEAR_INTERRUPT_MASK_FROM_ISR( ( x ) ) +#else + +/* The tick type can be read atomically, so critical sections used when the + * tick count is returned can be defined away. */ + #define portTICK_TYPE_ENTER_CRITICAL() + #define portTICK_TYPE_EXIT_CRITICAL() + #define portTICK_TYPE_SET_INTERRUPT_MASK_FROM_ISR() 0 + #define portTICK_TYPE_CLEAR_INTERRUPT_MASK_FROM_ISR( x ) ( void ) ( x ) +#endif /* if ( portTICK_TYPE_IS_ATOMIC == 0 ) */ + +/* Definitions to allow backward compatibility with FreeRTOS versions prior to + * V8 if desired. */ +#ifndef configENABLE_BACKWARD_COMPATIBILITY + #define configENABLE_BACKWARD_COMPATIBILITY 1 +#endif + +#ifndef configPRINTF + +/* configPRINTF() was not defined, so define it away to nothing. To use + * configPRINTF() then define it as follows (where MyPrintFunction() is + * provided by the application writer): + * + * void MyPrintFunction(const char *pcFormat, ... ); + #define configPRINTF( X ) MyPrintFunction X + * + * Then call like a standard printf() function, but placing brackets around + * all parameters so they are passed as a single parameter. For example: + * configPRINTF( ("Value = %d", MyVariable) ); */ + #define configPRINTF( X ) +#endif + +#ifndef configMAX + +/* The application writer has not provided their own MAX macro, so define + * the following generic implementation. */ + #define configMAX( a, b ) ( ( ( a ) > ( b ) ) ? ( a ) : ( b ) ) +#endif + +#ifndef configMIN + +/* The application writer has not provided their own MIN macro, so define + * the following generic implementation. */ + #define configMIN( a, b ) ( ( ( a ) < ( b ) ) ? ( a ) : ( b ) ) +#endif + +#if configENABLE_BACKWARD_COMPATIBILITY == 1 + #define eTaskStateGet eTaskGetState + #define portTickType TickType_t + #define xTaskHandle TaskHandle_t + #define xQueueHandle QueueHandle_t + #define xSemaphoreHandle SemaphoreHandle_t + #define xQueueSetHandle QueueSetHandle_t + #define xQueueSetMemberHandle QueueSetMemberHandle_t + #define xTimeOutType TimeOut_t + #define xMemoryRegion MemoryRegion_t + #define xTaskParameters TaskParameters_t + #define xTaskStatusType TaskStatus_t + #define xTimerHandle TimerHandle_t + #define xCoRoutineHandle CoRoutineHandle_t + #define pdTASK_HOOK_CODE TaskHookFunction_t + #define portTICK_RATE_MS portTICK_PERIOD_MS + #define pcTaskGetTaskName pcTaskGetName + #define pcTimerGetTimerName pcTimerGetName + #define pcQueueGetQueueName pcQueueGetName #define vTaskGetTaskInfo vTaskGetInfo #define xTaskGetIdleRunTimeCounter ulTaskGetIdleRunTimeCounter @@ -1161,6 +2947,11 @@ #define configRUN_ADDITIONAL_TESTS 0 #endif +/* The following config allows infinite loop control. For example, control the + * infinite loop in idle task function when performing unit tests. */ +#ifndef configCONTROL_INFINITE_LOOP + #define configCONTROL_INFINITE_LOOP() +#endif /* Sometimes the FreeRTOSConfig.h settings only allow a task to be created using * dynamically allocated RAM, in which case when any task is deleted it is known @@ -1279,10 +3070,20 @@ typedef struct xSTATIC_TCB #if ( portUSING_MPU_WRAPPERS == 1 ) xMPU_SETTINGS xDummy2; #endif + #if ( configUSE_CORE_AFFINITY == 1 ) && ( configNUMBER_OF_CORES > 1 ) + UBaseType_t uxDummy26; + #endif StaticListItem_t xDummy3[ 2 ]; UBaseType_t uxDummy5; void * pxDummy6; + #if ( configNUMBER_OF_CORES > 1 ) + BaseType_t xDummy23; + UBaseType_t uxDummy24; + #endif uint8_t ucDummy7[ configMAX_TASK_NAME_LEN ]; + #if ( configUSE_TASK_PREEMPTION_DISABLE == 1 ) + BaseType_t xDummy25; + #endif #if ( ( portSTACK_GROWTH > 0 ) || ( configRECORD_STACK_HIGH_ADDRESS == 1 ) ) void * pxDummy8; #endif diff --git a/Source/include/StackMacros.h b/Source/include/StackMacros.h index 006068c7e..6559952dd 100644 --- a/Source/include/StackMacros.h +++ b/Source/include/StackMacros.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/Source/include/atomic.h b/Source/include/atomic.h index 033edce3a..65e6ea0bf 100644 --- a/Source/include/atomic.h +++ b/Source/include/atomic.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/Source/include/croutine.h b/Source/include/croutine.h index df50f870e..3437e1b0c 100644 --- a/Source/include/croutine.h +++ b/Source/include/croutine.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -47,8 +47,8 @@ typedef void * CoRoutineHandle_t; /* Defines the prototype to which co-routine functions must conform. */ -typedef void (* crCOROUTINE_CODE)( CoRoutineHandle_t, - UBaseType_t ); +typedef void (* crCOROUTINE_CODE)( CoRoutineHandle_t xHandle, + UBaseType_t uxIndex ); typedef struct corCoRoutineControlBlock { diff --git a/Source/include/deprecated_definitions.h b/Source/include/deprecated_definitions.h index 6a25d063b..39a422a03 100644 --- a/Source/include/deprecated_definitions.h +++ b/Source/include/deprecated_definitions.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/Source/include/event_groups.h b/Source/include/event_groups.h index a5c723d40..6a4ae0152 100644 --- a/Source/include/event_groups.h +++ b/Source/include/event_groups.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -40,20 +40,20 @@ * item value. It is important they don't clash with the * taskEVENT_LIST_ITEM_VALUE_IN_USE definition. */ #if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS ) - #define eventCLEAR_EVENTS_ON_EXIT_BIT 0x0100U - #define eventUNBLOCKED_DUE_TO_BIT_SET 0x0200U - #define eventWAIT_FOR_ALL_BITS 0x0400U - #define eventEVENT_BITS_CONTROL_BYTES 0xff00U + #define eventCLEAR_EVENTS_ON_EXIT_BIT ( ( uint16_t ) 0x0100U ) + #define eventUNBLOCKED_DUE_TO_BIT_SET ( ( uint16_t ) 0x0200U ) + #define eventWAIT_FOR_ALL_BITS ( ( uint16_t ) 0x0400U ) + #define eventEVENT_BITS_CONTROL_BYTES ( ( uint16_t ) 0xff00U ) #elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS ) - #define eventCLEAR_EVENTS_ON_EXIT_BIT 0x01000000UL - #define eventUNBLOCKED_DUE_TO_BIT_SET 0x02000000UL - #define eventWAIT_FOR_ALL_BITS 0x04000000UL - #define eventEVENT_BITS_CONTROL_BYTES 0xff000000UL + #define eventCLEAR_EVENTS_ON_EXIT_BIT ( ( uint32_t ) 0x01000000UL ) + #define eventUNBLOCKED_DUE_TO_BIT_SET ( ( uint32_t ) 0x02000000UL ) + #define eventWAIT_FOR_ALL_BITS ( ( uint32_t ) 0x04000000UL ) + #define eventEVENT_BITS_CONTROL_BYTES ( ( uint32_t ) 0xff000000UL ) #elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_64_BITS ) - #define eventCLEAR_EVENTS_ON_EXIT_BIT 0x0100000000000000ULL - #define eventUNBLOCKED_DUE_TO_BIT_SET 0x0200000000000000ULL - #define eventWAIT_FOR_ALL_BITS 0x0400000000000000ULL - #define eventEVENT_BITS_CONTROL_BYTES 0xff00000000000000ULL + #define eventCLEAR_EVENTS_ON_EXIT_BIT ( ( uint64_t ) 0x0100000000000000ULL ) + #define eventUNBLOCKED_DUE_TO_BIT_SET ( ( uint64_t ) 0x0200000000000000ULL ) + #define eventWAIT_FOR_ALL_BITS ( ( uint64_t ) 0x0400000000000000ULL ) + #define eventEVENT_BITS_CONTROL_BYTES ( ( uint64_t ) 0xff00000000000000ULL ) #endif /* if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS ) */ /* *INDENT-OFF* */ @@ -807,9 +807,9 @@ void vEventGroupDelete( EventGroupHandle_t xEventGroup ) PRIVILEGED_FUNCTION; /* For internal use only. */ void vEventGroupSetBitsCallback( void * pvEventGroup, - const uint32_t ulBitsToSet ) PRIVILEGED_FUNCTION; + uint32_t ulBitsToSet ) PRIVILEGED_FUNCTION; void vEventGroupClearBitsCallback( void * pvEventGroup, - const uint32_t ulBitsToClear ) PRIVILEGED_FUNCTION; + uint32_t ulBitsToClear ) PRIVILEGED_FUNCTION; #if ( configUSE_TRACE_FACILITY == 1 ) diff --git a/Source/include/list.h b/Source/include/list.h index 62c6238f6..a2e882736 100644 --- a/Source/include/list.h +++ b/Source/include/list.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -151,7 +151,7 @@ struct xLIST_ITEM struct xLIST * configLIST_VOLATILE pxContainer; /**< Pointer to the list in which this list item is placed (if any). */ listSECOND_LIST_ITEM_INTEGRITY_CHECK_VALUE /**< Set to a known value if configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES is set to 1. */ }; -typedef struct xLIST_ITEM ListItem_t; /* For some reason lint wants this as two separate definitions. */ +typedef struct xLIST_ITEM ListItem_t; #if ( configUSE_MINI_LIST_ITEM == 1 ) struct xMINI_LIST_ITEM diff --git a/Source/include/message_buffer.h b/Source/include/message_buffer.h index 136445d00..bc99870cf 100644 --- a/Source/include/message_buffer.h +++ b/Source/include/message_buffer.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/Source/include/mpu_prototypes.h b/Source/include/mpu_prototypes.h index 354b94e41..c3c6c7637 100644 --- a/Source/include/mpu_prototypes.h +++ b/Source/include/mpu_prototypes.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -56,14 +56,14 @@ typedef struct xTaskGenericNotifyWaitParams TickType_t xTicksToWait; } xTaskGenericNotifyWaitParams_t; -typedef struct xTimerGenericCommandParams +typedef struct xTimerGenericCommandFromTaskParams { TimerHandle_t xTimer; BaseType_t xCommandID; TickType_t xOptionalValue; BaseType_t * pxHigherPriorityTaskWoken; TickType_t xTicksToWait; -} xTimerGenericCommandParams_t; +} xTimerGenericCommandFromTaskParams_t; typedef struct xEventGroupWaitBitsParams { @@ -89,7 +89,6 @@ void MPU_vTaskSuspend( TaskHandle_t xTaskToSuspend ) FREERTOS_SYSTEM_CALL; void MPU_vTaskResume( TaskHandle_t xTaskToResume ) FREERTOS_SYSTEM_CALL; TickType_t MPU_xTaskGetTickCount( void ) FREERTOS_SYSTEM_CALL; UBaseType_t MPU_uxTaskGetNumberOfTasks( void ) FREERTOS_SYSTEM_CALL; -char * MPU_pcTaskGetName( TaskHandle_t xTaskToQuery ) FREERTOS_SYSTEM_CALL; UBaseType_t MPU_uxTaskGetStackHighWaterMark( TaskHandle_t xTask ) FREERTOS_SYSTEM_CALL; configSTACK_DEPTH_TYPE MPU_uxTaskGetStackHighWaterMark2( TaskHandle_t xTask ) FREERTOS_SYSTEM_CALL; void MPU_vTaskSetApplicationTaskTag( TaskHandle_t xTask, @@ -156,16 +155,19 @@ void MPU_vTaskPrioritySet( TaskHandle_t xTask, TaskHandle_t MPU_xTaskGetHandle( const char * pcNameToQuery ) PRIVILEGED_FUNCTION; BaseType_t MPU_xTaskCallApplicationTaskHook( TaskHandle_t xTask, void * pvParameter ) PRIVILEGED_FUNCTION; +char * MPU_pcTaskGetName( TaskHandle_t xTaskToQuery ) PRIVILEGED_FUNCTION; BaseType_t MPU_xTaskCreateRestricted( const TaskParameters_t * const pxTaskDefinition, TaskHandle_t * pxCreatedTask ) PRIVILEGED_FUNCTION; BaseType_t MPU_xTaskCreateRestrictedStatic( const TaskParameters_t * const pxTaskDefinition, TaskHandle_t * pxCreatedTask ) PRIVILEGED_FUNCTION; -void vTaskAllocateMPURegions( TaskHandle_t xTaskToModify, - const MemoryRegion_t * const xRegions ) PRIVILEGED_FUNCTION; +void MPU_vTaskAllocateMPURegions( TaskHandle_t xTaskToModify, + const MemoryRegion_t * const xRegions ) PRIVILEGED_FUNCTION; BaseType_t MPU_xTaskGetStaticBuffers( TaskHandle_t xTask, StackType_t ** ppuxStackBuffer, StaticTask_t ** ppxTaskBuffer ) PRIVILEGED_FUNCTION; UBaseType_t MPU_uxTaskPriorityGetFromISR( const TaskHandle_t xTask ) PRIVILEGED_FUNCTION; +UBaseType_t MPU_uxTaskBasePriorityGet( const TaskHandle_t xTask ) PRIVILEGED_FUNCTION; +UBaseType_t MPU_uxTaskBasePriorityGetFromISR( const TaskHandle_t xTask ) PRIVILEGED_FUNCTION; BaseType_t MPU_xTaskResumeFromISR( TaskHandle_t xTaskToResume ) PRIVILEGED_FUNCTION; TaskHookFunction_t MPU_xTaskGetApplicationTaskTagFromISR( TaskHandle_t xTask ) PRIVILEGED_FUNCTION; BaseType_t MPU_xTaskGenericNotifyFromISR( TaskHandle_t xTaskToNotify, @@ -261,12 +263,12 @@ void MPU_vTimerSetTimerID( TimerHandle_t xTimer, void * pvNewID ) FREERTOS_SYSTEM_CALL; BaseType_t MPU_xTimerIsTimerActive( TimerHandle_t xTimer ) FREERTOS_SYSTEM_CALL; TaskHandle_t MPU_xTimerGetTimerDaemonTaskHandle( void ) FREERTOS_SYSTEM_CALL; -BaseType_t MPU_xTimerGenericCommand( TimerHandle_t xTimer, - const BaseType_t xCommandID, - const TickType_t xOptionalValue, - BaseType_t * const pxHigherPriorityTaskWoken, - const TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL; -BaseType_t MPU_xTimerGenericCommandEntry( const xTimerGenericCommandParams_t * pxParams ) FREERTOS_SYSTEM_CALL; +BaseType_t MPU_xTimerGenericCommandFromTask( TimerHandle_t xTimer, + const BaseType_t xCommandID, + const TickType_t xOptionalValue, + BaseType_t * const pxHigherPriorityTaskWoken, + const TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL; +BaseType_t MPU_xTimerGenericCommandFromTaskEntry( const xTimerGenericCommandFromTaskParams_t * pxParams ) FREERTOS_SYSTEM_CALL; const char * MPU_pcTimerGetName( TimerHandle_t xTimer ) FREERTOS_SYSTEM_CALL; void MPU_vTimerSetReloadMode( TimerHandle_t xTimer, const BaseType_t uxAutoReload ) FREERTOS_SYSTEM_CALL; @@ -291,6 +293,11 @@ TimerHandle_t MPU_xTimerCreateStatic( const char * const pcTimerName, StaticTimer_t * pxTimerBuffer ) PRIVILEGED_FUNCTION; BaseType_t MPU_xTimerGetStaticBuffer( TimerHandle_t xTimer, StaticTimer_t ** ppxTimerBuffer ) PRIVILEGED_FUNCTION; +BaseType_t MPU_xTimerGenericCommandFromISR( TimerHandle_t xTimer, + const BaseType_t xCommandID, + const TickType_t xOptionalValue, + BaseType_t * const pxHigherPriorityTaskWoken, + const TickType_t xTicksToWait ) PRIVILEGED_FUNCTION; /* MPU versions of event_group.h API functions. */ EventBits_t MPU_xEventGroupWaitBits( EventGroupHandle_t xEventGroup, diff --git a/Source/include/mpu_syscall_numbers.h b/Source/include/mpu_syscall_numbers.h index 03c3ebd45..2cf6e2422 100644 --- a/Source/include/mpu_syscall_numbers.h +++ b/Source/include/mpu_syscall_numbers.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -32,7 +32,7 @@ /* Numbers assigned to various system calls. */ #define SYSTEM_CALL_xTaskGenericNotify 0 #define SYSTEM_CALL_xTaskGenericNotifyWait 1 -#define SYSTEM_CALL_xTimerGenericCommand 2 +#define SYSTEM_CALL_xTimerGenericCommandFromTask 2 #define SYSTEM_CALL_xEventGroupWaitBits 3 #define SYSTEM_CALL_xTaskDelayUntil 4 #define SYSTEM_CALL_xTaskAbortDelay 5 @@ -45,62 +45,61 @@ #define SYSTEM_CALL_vTaskResume 12 #define SYSTEM_CALL_xTaskGetTickCount 13 #define SYSTEM_CALL_uxTaskGetNumberOfTasks 14 -#define SYSTEM_CALL_pcTaskGetName 15 -#define SYSTEM_CALL_ulTaskGetRunTimeCounter 16 -#define SYSTEM_CALL_ulTaskGetRunTimePercent 17 -#define SYSTEM_CALL_ulTaskGetIdleRunTimePercent 18 -#define SYSTEM_CALL_ulTaskGetIdleRunTimeCounter 19 -#define SYSTEM_CALL_vTaskSetApplicationTaskTag 20 -#define SYSTEM_CALL_xTaskGetApplicationTaskTag 21 -#define SYSTEM_CALL_vTaskSetThreadLocalStoragePointer 22 -#define SYSTEM_CALL_pvTaskGetThreadLocalStoragePointer 23 -#define SYSTEM_CALL_uxTaskGetSystemState 24 -#define SYSTEM_CALL_uxTaskGetStackHighWaterMark 25 -#define SYSTEM_CALL_uxTaskGetStackHighWaterMark2 26 -#define SYSTEM_CALL_xTaskGetCurrentTaskHandle 27 -#define SYSTEM_CALL_xTaskGetSchedulerState 28 -#define SYSTEM_CALL_vTaskSetTimeOutState 29 -#define SYSTEM_CALL_xTaskCheckForTimeOut 30 -#define SYSTEM_CALL_ulTaskGenericNotifyTake 31 -#define SYSTEM_CALL_xTaskGenericNotifyStateClear 32 -#define SYSTEM_CALL_ulTaskGenericNotifyValueClear 33 -#define SYSTEM_CALL_xQueueGenericSend 34 -#define SYSTEM_CALL_uxQueueMessagesWaiting 35 -#define SYSTEM_CALL_uxQueueSpacesAvailable 36 -#define SYSTEM_CALL_xQueueReceive 37 -#define SYSTEM_CALL_xQueuePeek 38 -#define SYSTEM_CALL_xQueueSemaphoreTake 39 -#define SYSTEM_CALL_xQueueGetMutexHolder 40 -#define SYSTEM_CALL_xQueueTakeMutexRecursive 41 -#define SYSTEM_CALL_xQueueGiveMutexRecursive 42 -#define SYSTEM_CALL_xQueueSelectFromSet 43 -#define SYSTEM_CALL_xQueueAddToSet 44 -#define SYSTEM_CALL_vQueueAddToRegistry 45 -#define SYSTEM_CALL_vQueueUnregisterQueue 46 -#define SYSTEM_CALL_pcQueueGetName 47 -#define SYSTEM_CALL_pvTimerGetTimerID 48 -#define SYSTEM_CALL_vTimerSetTimerID 49 -#define SYSTEM_CALL_xTimerIsTimerActive 50 -#define SYSTEM_CALL_xTimerGetTimerDaemonTaskHandle 51 -#define SYSTEM_CALL_pcTimerGetName 52 -#define SYSTEM_CALL_vTimerSetReloadMode 53 -#define SYSTEM_CALL_xTimerGetReloadMode 54 -#define SYSTEM_CALL_uxTimerGetReloadMode 55 -#define SYSTEM_CALL_xTimerGetPeriod 56 -#define SYSTEM_CALL_xTimerGetExpiryTime 57 -#define SYSTEM_CALL_xEventGroupClearBits 58 -#define SYSTEM_CALL_xEventGroupSetBits 59 -#define SYSTEM_CALL_xEventGroupSync 60 -#define SYSTEM_CALL_uxEventGroupGetNumber 61 -#define SYSTEM_CALL_vEventGroupSetNumber 62 -#define SYSTEM_CALL_xStreamBufferSend 63 -#define SYSTEM_CALL_xStreamBufferReceive 64 -#define SYSTEM_CALL_xStreamBufferIsFull 65 -#define SYSTEM_CALL_xStreamBufferIsEmpty 66 -#define SYSTEM_CALL_xStreamBufferSpacesAvailable 67 -#define SYSTEM_CALL_xStreamBufferBytesAvailable 68 -#define SYSTEM_CALL_xStreamBufferSetTriggerLevel 69 -#define SYSTEM_CALL_xStreamBufferNextMessageLengthBytes 70 -#define NUM_SYSTEM_CALLS 71 /* Total number of system calls. */ +#define SYSTEM_CALL_ulTaskGetRunTimeCounter 15 +#define SYSTEM_CALL_ulTaskGetRunTimePercent 16 +#define SYSTEM_CALL_ulTaskGetIdleRunTimePercent 17 +#define SYSTEM_CALL_ulTaskGetIdleRunTimeCounter 18 +#define SYSTEM_CALL_vTaskSetApplicationTaskTag 19 +#define SYSTEM_CALL_xTaskGetApplicationTaskTag 20 +#define SYSTEM_CALL_vTaskSetThreadLocalStoragePointer 21 +#define SYSTEM_CALL_pvTaskGetThreadLocalStoragePointer 22 +#define SYSTEM_CALL_uxTaskGetSystemState 23 +#define SYSTEM_CALL_uxTaskGetStackHighWaterMark 24 +#define SYSTEM_CALL_uxTaskGetStackHighWaterMark2 25 +#define SYSTEM_CALL_xTaskGetCurrentTaskHandle 26 +#define SYSTEM_CALL_xTaskGetSchedulerState 27 +#define SYSTEM_CALL_vTaskSetTimeOutState 28 +#define SYSTEM_CALL_xTaskCheckForTimeOut 29 +#define SYSTEM_CALL_ulTaskGenericNotifyTake 30 +#define SYSTEM_CALL_xTaskGenericNotifyStateClear 31 +#define SYSTEM_CALL_ulTaskGenericNotifyValueClear 32 +#define SYSTEM_CALL_xQueueGenericSend 33 +#define SYSTEM_CALL_uxQueueMessagesWaiting 34 +#define SYSTEM_CALL_uxQueueSpacesAvailable 35 +#define SYSTEM_CALL_xQueueReceive 36 +#define SYSTEM_CALL_xQueuePeek 37 +#define SYSTEM_CALL_xQueueSemaphoreTake 38 +#define SYSTEM_CALL_xQueueGetMutexHolder 39 +#define SYSTEM_CALL_xQueueTakeMutexRecursive 40 +#define SYSTEM_CALL_xQueueGiveMutexRecursive 41 +#define SYSTEM_CALL_xQueueSelectFromSet 42 +#define SYSTEM_CALL_xQueueAddToSet 43 +#define SYSTEM_CALL_vQueueAddToRegistry 44 +#define SYSTEM_CALL_vQueueUnregisterQueue 45 +#define SYSTEM_CALL_pcQueueGetName 46 +#define SYSTEM_CALL_pvTimerGetTimerID 47 +#define SYSTEM_CALL_vTimerSetTimerID 48 +#define SYSTEM_CALL_xTimerIsTimerActive 49 +#define SYSTEM_CALL_xTimerGetTimerDaemonTaskHandle 50 +#define SYSTEM_CALL_pcTimerGetName 51 +#define SYSTEM_CALL_vTimerSetReloadMode 52 +#define SYSTEM_CALL_xTimerGetReloadMode 53 +#define SYSTEM_CALL_uxTimerGetReloadMode 54 +#define SYSTEM_CALL_xTimerGetPeriod 55 +#define SYSTEM_CALL_xTimerGetExpiryTime 56 +#define SYSTEM_CALL_xEventGroupClearBits 57 +#define SYSTEM_CALL_xEventGroupSetBits 58 +#define SYSTEM_CALL_xEventGroupSync 59 +#define SYSTEM_CALL_uxEventGroupGetNumber 60 +#define SYSTEM_CALL_vEventGroupSetNumber 61 +#define SYSTEM_CALL_xStreamBufferSend 62 +#define SYSTEM_CALL_xStreamBufferReceive 63 +#define SYSTEM_CALL_xStreamBufferIsFull 64 +#define SYSTEM_CALL_xStreamBufferIsEmpty 65 +#define SYSTEM_CALL_xStreamBufferSpacesAvailable 66 +#define SYSTEM_CALL_xStreamBufferBytesAvailable 67 +#define SYSTEM_CALL_xStreamBufferSetTriggerLevel 68 +#define SYSTEM_CALL_xStreamBufferNextMessageLengthBytes 69 +#define NUM_SYSTEM_CALLS 70 /* Total number of system calls. */ #endif /* MPU_SYSCALL_NUMBERS_H */ diff --git a/Source/include/mpu_wrappers.h b/Source/include/mpu_wrappers.h index bc19e0db5..cb08a0351 100644 --- a/Source/include/mpu_wrappers.h +++ b/Source/include/mpu_wrappers.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -57,7 +57,6 @@ #define vTaskResume MPU_vTaskResume #define xTaskGetTickCount MPU_xTaskGetTickCount #define uxTaskGetNumberOfTasks MPU_uxTaskGetNumberOfTasks - #define pcTaskGetName MPU_pcTaskGetName #define uxTaskGetStackHighWaterMark MPU_uxTaskGetStackHighWaterMark #define uxTaskGetStackHighWaterMark2 MPU_uxTaskGetStackHighWaterMark2 #define vTaskSetApplicationTaskTag MPU_vTaskSetApplicationTaskTag @@ -94,11 +93,14 @@ #define xTaskCallApplicationTaskHook MPU_xTaskCallApplicationTaskHook #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) + #define pcTaskGetName MPU_pcTaskGetName #define xTaskCreateRestricted MPU_xTaskCreateRestricted #define xTaskCreateRestrictedStatic MPU_xTaskCreateRestrictedStatic #define vTaskAllocateMPURegions MPU_vTaskAllocateMPURegions #define xTaskGetStaticBuffers MPU_xTaskGetStaticBuffers #define uxTaskPriorityGetFromISR MPU_uxTaskPriorityGetFromISR + #define uxTaskBasePriorityGet MPU_uxTaskBasePriorityGet + #define uxTaskBasePriorityGetFromISR MPU_uxTaskBasePriorityGetFromISR #define xTaskResumeFromISR MPU_xTaskResumeFromISR #define xTaskGetApplicationTaskTagFromISR MPU_xTaskGetApplicationTaskTagFromISR #define xTaskGenericNotifyFromISR MPU_xTaskGenericNotifyFromISR @@ -156,7 +158,7 @@ #define vTimerSetTimerID MPU_vTimerSetTimerID #define xTimerIsTimerActive MPU_xTimerIsTimerActive #define xTimerGetTimerDaemonTaskHandle MPU_xTimerGetTimerDaemonTaskHandle - #define xTimerGenericCommand MPU_xTimerGenericCommand + #define xTimerGenericCommandFromTask MPU_xTimerGenericCommandFromTask #define pcTimerGetName MPU_pcTimerGetName #define vTimerSetReloadMode MPU_vTimerSetReloadMode #define uxTimerGetReloadMode MPU_uxTimerGetReloadMode @@ -167,10 +169,11 @@ * the application can use opaque handles maintained in mpu_wrappers.c * with all the APIs. */ #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) - #define xTimerGetReloadMode MPU_xTimerGetReloadMode - #define xTimerCreate MPU_xTimerCreate - #define xTimerCreateStatic MPU_xTimerCreateStatic - #define xTimerGetStaticBuffer MPU_xTimerGetStaticBuffer + #define xTimerGetReloadMode MPU_xTimerGetReloadMode + #define xTimerCreate MPU_xTimerCreate + #define xTimerCreateStatic MPU_xTimerCreateStatic + #define xTimerGetStaticBuffer MPU_xTimerGetStaticBuffer + #define xTimerGenericCommandFromISR MPU_xTimerGenericCommandFromISR #endif /* #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ /* Map standard event_group.h API functions to the MPU equivalents. */ diff --git a/Source/include/newlib-freertos.h b/Source/include/newlib-freertos.h index b6911c9bf..6a74eee44 100644 --- a/Source/include/newlib-freertos.h +++ b/Source/include/newlib-freertos.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/Source/include/picolibc-freertos.h b/Source/include/picolibc-freertos.h index 63f692726..7699788c5 100644 --- a/Source/include/picolibc-freertos.h +++ b/Source/include/picolibc-freertos.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -58,18 +58,19 @@ #endif /* Allocate thread local storage block off the end of the -* stack. The _tls_size() function returns the size (in -* bytes) of the total TLS area used by the application */ + * stack. The picolibcTLS_SIZE macro returns the size (in + * bytes) of the total TLS area used by the application. + * Calculate the top of stack address. */ #if ( portSTACK_GROWTH < 0 ) - #define configINIT_TLS_BLOCK( xTLSBlock, pxTopOfStack ) \ - do { \ - pxTopOfStack = ( StackType_t * ) ( ( ( ( portPOINTER_SIZE_TYPE ) pxTopOfStack ) \ - - picolibcTLS_SIZE ) & ~ \ - configMAX( picolibcSTACK_ALIGNMENT_MASK, \ - picolibcTLS_ALIGNMENT_MASK ) ); \ - xTLSBlock = pxTopOfStack; \ - _init_tls( xTLSBlock ); \ + #define configINIT_TLS_BLOCK( xTLSBlock, pxTopOfStack ) \ + do { \ + xTLSBlock = ( void * ) ( ( ( ( portPOINTER_SIZE_TYPE ) pxTopOfStack ) - \ + picolibcTLS_SIZE ) & \ + ~picolibcTLS_ALIGNMENT_MASK ); \ + pxTopOfStack = ( StackType_t * ) ( ( ( ( portPOINTER_SIZE_TYPE ) xTLSBlock ) - 1 ) & \ + ~picolibcSTACK_ALIGNMENT_MASK ); \ + _init_tls( xTLSBlock ); \ } while( 0 ) #else /* portSTACK_GROWTH */ #define configINIT_TLS_BLOCK( xTLSBlock, pxTopOfStack ) \ diff --git a/Source/include/portable.h b/Source/include/portable.h index ec11f0f4d..70ed49644 100644 --- a/Source/include/portable.h +++ b/Source/include/portable.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -200,7 +200,7 @@ size_t xPortGetMinimumEverFreeHeapSize( void ) PRIVILEGED_FUNCTION; * * This hook function is called when allocation failed. */ - void vApplicationMallocFailedHook( void ); /*lint !e526 Symbol not defined as it is an application callback. */ + void vApplicationMallocFailedHook( void ); #endif /* diff --git a/Source/include/projdefs.h b/Source/include/projdefs.h index 4c4633395..e05db5349 100644 --- a/Source/include/projdefs.h +++ b/Source/include/projdefs.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -33,13 +33,20 @@ * Defines the prototype to which task functions must conform. Defined in this * file to ensure the type is known before portable.h is included. */ -typedef void (* TaskFunction_t)( void * ); +typedef void (* TaskFunction_t)( void * arg ); /* Converts a time in milliseconds to a time in ticks. This macro can be * overridden by a macro of the same name defined in FreeRTOSConfig.h in case the * definition here is not suitable for your application. */ #ifndef pdMS_TO_TICKS - #define pdMS_TO_TICKS( xTimeInMs ) ( ( TickType_t ) ( ( ( TickType_t ) ( xTimeInMs ) * ( TickType_t ) configTICK_RATE_HZ ) / ( TickType_t ) 1000U ) ) + #define pdMS_TO_TICKS( xTimeInMs ) ( ( TickType_t ) ( ( ( uint64_t ) ( xTimeInMs ) * ( uint64_t ) configTICK_RATE_HZ ) / ( uint64_t ) 1000U ) ) +#endif + +/* Converts a time in ticks to a time in milliseconds. This macro can be + * overridden by a macro of the same name defined in FreeRTOSConfig.h in case the + * definition here is not suitable for your application. */ +#ifndef pdTICKS_TO_MS + #define pdTICKS_TO_MS( xTimeInTicks ) ( ( TickType_t ) ( ( ( uint64_t ) ( xTimeInTicks ) * ( uint64_t ) 1000U ) / ( uint64_t ) configTICK_RATE_HZ ) ) #endif #define pdFALSE ( ( BaseType_t ) 0 ) diff --git a/Source/include/queue.h b/Source/include/queue.h index 836adf58d..e0a766d4f 100644 --- a/Source/include/queue.h +++ b/Source/include/queue.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -267,7 +267,7 @@ typedef struct QueueDefinition * QueueSetMemberHandle_t; /** * queue. h * @code{c} - * BaseType_t xQueueSendToToFront( + * BaseType_t xQueueSendToFront( * QueueHandle_t xQueue, * const void *pvItemToQueue, * TickType_t xTicksToWait @@ -995,7 +995,7 @@ void vQueueDelete( QueueHandle_t xQueue ) PRIVILEGED_FUNCTION; * @param pxHigherPriorityTaskWoken xQueueSendToFrontFromISR() will set * *pxHigherPriorityTaskWoken to pdTRUE if sending to the queue caused a task * to unblock, and the unblocked task has a priority higher than the currently - * running task. If xQueueSendToFromFromISR() sets this value to pdTRUE then + * running task. If xQueueSendToFrontFromISR() sets this value to pdTRUE then * a context switch should be requested before the interrupt is exited. * * @return pdTRUE if the data was successfully sent to the queue, otherwise @@ -1185,9 +1185,12 @@ void vQueueDelete( QueueHandle_t xQueue ) PRIVILEGED_FUNCTION; * { * // Writing to the queue caused a task to unblock and the unblocked task * // has a priority higher than or equal to the priority of the currently - * // executing task (the task this interrupt interrupted). Perform a context + * // executing task (the task this interrupt interrupted). Perform a context * // switch so this interrupt returns directly to the unblocked task. - * portYIELD_FROM_ISR(); // or portEND_SWITCHING_ISR() depending on the port. + * // The macro used is port specific and will be either + * // portYIELD_FROM_ISR() or portEND_SWITCHING_ISR() - refer to the documentation + * // page for the port being used. + * portYIELD_FROM_ISR( xHigherPriorityTaskWoken ); * } * } * @endcode @@ -1260,8 +1263,11 @@ void vQueueDelete( QueueHandle_t xQueue ) PRIVILEGED_FUNCTION; * // Now the buffer is empty we can switch context if necessary. * if( xHigherPriorityTaskWoken ) * { - * // Actual macro used here is port specific. - * portYIELD_FROM_ISR (); + * // As xHigherPriorityTaskWoken is now set to pdTRUE then a context + * // switch should be requested. The macro used is port specific and + * // will be either portYIELD_FROM_ISR() or portEND_SWITCHING_ISR() - + * // refer to the documentation page for the port being used. + * portYIELD_FROM_ISR( xHigherPriorityTaskWoken ); * } * } * @endcode @@ -1337,11 +1343,14 @@ void vQueueDelete( QueueHandle_t xQueue ) PRIVILEGED_FUNCTION; * * } while( portINPUT_BYTE( BUFFER_COUNT ) ); * - * // Now the buffer is empty we can switch context if necessary. Note that the - * // name of the yield function required is port specific. + * // Now the buffer is empty we can switch context if necessary. * if( xHigherPriorityTaskWokenByPost ) * { - * portYIELD_FROM_ISR(); + * // As xHigherPriorityTaskWokenByPost is now set to pdTRUE then a context + * // switch should be requested. The macro used is port specific and + * // will be either portYIELD_FROM_ISR() or portEND_SWITCHING_ISR() - + * // refer to the documentation page for the port being used. + * portYIELD_FROM_ISR( xHigherPriorityTaskWokenByPost ); * } * } * @endcode @@ -1455,6 +1464,8 @@ BaseType_t xQueueIsQueueEmptyFromISR( const QueueHandle_t xQueue ) PRIVILEGED_FU BaseType_t xQueueIsQueueFullFromISR( const QueueHandle_t xQueue ) PRIVILEGED_FUNCTION; UBaseType_t uxQueueMessagesWaitingFromISR( const QueueHandle_t xQueue ) PRIVILEGED_FUNCTION; +#if ( configUSE_CO_ROUTINES == 1 ) + /* * The functions defined above are for passing data to and from tasks. The * functions below are the equivalents for passing data to and from @@ -1464,18 +1475,20 @@ UBaseType_t uxQueueMessagesWaitingFromISR( const QueueHandle_t xQueue ) PRIVILEG * should not be called directly from application code. Instead use the macro * wrappers defined within croutine.h. */ -BaseType_t xQueueCRSendFromISR( QueueHandle_t xQueue, - const void * pvItemToQueue, - BaseType_t xCoRoutinePreviouslyWoken ); -BaseType_t xQueueCRReceiveFromISR( QueueHandle_t xQueue, - void * pvBuffer, - BaseType_t * pxTaskWoken ); -BaseType_t xQueueCRSend( QueueHandle_t xQueue, - const void * pvItemToQueue, - TickType_t xTicksToWait ); -BaseType_t xQueueCRReceive( QueueHandle_t xQueue, - void * pvBuffer, - TickType_t xTicksToWait ); + BaseType_t xQueueCRSendFromISR( QueueHandle_t xQueue, + const void * pvItemToQueue, + BaseType_t xCoRoutinePreviouslyWoken ); + BaseType_t xQueueCRReceiveFromISR( QueueHandle_t xQueue, + void * pvBuffer, + BaseType_t * pxTaskWoken ); + BaseType_t xQueueCRSend( QueueHandle_t xQueue, + const void * pvItemToQueue, + TickType_t xTicksToWait ); + BaseType_t xQueueCRReceive( QueueHandle_t xQueue, + void * pvBuffer, + TickType_t xTicksToWait ); + +#endif /* if ( configUSE_CO_ROUTINES == 1 ) */ /* * For internal use only. Use xSemaphoreCreateMutex(), @@ -1483,17 +1496,30 @@ BaseType_t xQueueCRReceive( QueueHandle_t xQueue, * these functions directly. */ QueueHandle_t xQueueCreateMutex( const uint8_t ucQueueType ) PRIVILEGED_FUNCTION; -QueueHandle_t xQueueCreateMutexStatic( const uint8_t ucQueueType, - StaticQueue_t * pxStaticQueue ) PRIVILEGED_FUNCTION; -QueueHandle_t xQueueCreateCountingSemaphore( const UBaseType_t uxMaxCount, - const UBaseType_t uxInitialCount ) PRIVILEGED_FUNCTION; -QueueHandle_t xQueueCreateCountingSemaphoreStatic( const UBaseType_t uxMaxCount, - const UBaseType_t uxInitialCount, - StaticQueue_t * pxStaticQueue ) PRIVILEGED_FUNCTION; + +#if ( configSUPPORT_STATIC_ALLOCATION == 1 ) + QueueHandle_t xQueueCreateMutexStatic( const uint8_t ucQueueType, + StaticQueue_t * pxStaticQueue ) PRIVILEGED_FUNCTION; +#endif + +#if ( configUSE_COUNTING_SEMAPHORES == 1 ) + QueueHandle_t xQueueCreateCountingSemaphore( const UBaseType_t uxMaxCount, + const UBaseType_t uxInitialCount ) PRIVILEGED_FUNCTION; +#endif + +#if ( ( configUSE_COUNTING_SEMAPHORES == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) ) + QueueHandle_t xQueueCreateCountingSemaphoreStatic( const UBaseType_t uxMaxCount, + const UBaseType_t uxInitialCount, + StaticQueue_t * pxStaticQueue ) PRIVILEGED_FUNCTION; +#endif + BaseType_t xQueueSemaphoreTake( QueueHandle_t xQueue, TickType_t xTicksToWait ) PRIVILEGED_FUNCTION; -TaskHandle_t xQueueGetMutexHolder( QueueHandle_t xSemaphore ) PRIVILEGED_FUNCTION; -TaskHandle_t xQueueGetMutexHolderFromISR( QueueHandle_t xSemaphore ) PRIVILEGED_FUNCTION; + +#if ( ( configUSE_MUTEXES == 1 ) && ( INCLUDE_xSemaphoreGetMutexHolder == 1 ) ) + TaskHandle_t xQueueGetMutexHolder( QueueHandle_t xSemaphore ) PRIVILEGED_FUNCTION; + TaskHandle_t xQueueGetMutexHolderFromISR( QueueHandle_t xSemaphore ) PRIVILEGED_FUNCTION; +#endif /* * For internal use only. Use xSemaphoreTakeMutexRecursive() or @@ -1537,7 +1563,7 @@ BaseType_t xQueueGiveMutexRecursive( QueueHandle_t xMutex ) PRIVILEGED_FUNCTION; */ #if ( configQUEUE_REGISTRY_SIZE > 0 ) void vQueueAddToRegistry( QueueHandle_t xQueue, - const char * pcQueueName ) PRIVILEGED_FUNCTION; /*lint !e971 Unqualified char types are allowed for strings and single characters only. */ + const char * pcQueueName ) PRIVILEGED_FUNCTION; #endif /* @@ -1566,7 +1592,7 @@ BaseType_t xQueueGiveMutexRecursive( QueueHandle_t xMutex ) PRIVILEGED_FUNCTION; * returned. */ #if ( configQUEUE_REGISTRY_SIZE > 0 ) - const char * pcQueueGetName( QueueHandle_t xQueue ) PRIVILEGED_FUNCTION; /*lint !e971 Unqualified char types are allowed for strings and single characters only. */ + const char * pcQueueGetName( QueueHandle_t xQueue ) PRIVILEGED_FUNCTION; #endif /* @@ -1653,7 +1679,9 @@ BaseType_t xQueueGiveMutexRecursive( QueueHandle_t xMutex ) PRIVILEGED_FUNCTION; * @return If the queue set is created successfully then a handle to the created * queue set is returned. Otherwise NULL is returned. */ -QueueSetHandle_t xQueueCreateSet( const UBaseType_t uxEventQueueLength ) PRIVILEGED_FUNCTION; +#if ( ( configUSE_QUEUE_SETS == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) ) + QueueSetHandle_t xQueueCreateSet( const UBaseType_t uxEventQueueLength ) PRIVILEGED_FUNCTION; +#endif /* * Adds a queue or semaphore to a queue set that was previously created by a @@ -1677,8 +1705,10 @@ QueueSetHandle_t xQueueCreateSet( const UBaseType_t uxEventQueueLength ) PRIVILE * queue set because it is already a member of a different queue set then pdFAIL * is returned. */ -BaseType_t xQueueAddToSet( QueueSetMemberHandle_t xQueueOrSemaphore, - QueueSetHandle_t xQueueSet ) PRIVILEGED_FUNCTION; +#if ( configUSE_QUEUE_SETS == 1 ) + BaseType_t xQueueAddToSet( QueueSetMemberHandle_t xQueueOrSemaphore, + QueueSetHandle_t xQueueSet ) PRIVILEGED_FUNCTION; +#endif /* * Removes a queue or semaphore from a queue set. A queue or semaphore can only @@ -1697,8 +1727,10 @@ BaseType_t xQueueAddToSet( QueueSetMemberHandle_t xQueueOrSemaphore, * then pdPASS is returned. If the queue was not in the queue set, or the * queue (or semaphore) was not empty, then pdFAIL is returned. */ -BaseType_t xQueueRemoveFromSet( QueueSetMemberHandle_t xQueueOrSemaphore, - QueueSetHandle_t xQueueSet ) PRIVILEGED_FUNCTION; +#if ( configUSE_QUEUE_SETS == 1 ) + BaseType_t xQueueRemoveFromSet( QueueSetMemberHandle_t xQueueOrSemaphore, + QueueSetHandle_t xQueueSet ) PRIVILEGED_FUNCTION; +#endif /* * xQueueSelectFromSet() selects from the members of a queue set a queue or @@ -1734,13 +1766,17 @@ BaseType_t xQueueRemoveFromSet( QueueSetMemberHandle_t xQueueOrSemaphore, * in the queue set that is available, or NULL if no such queue or semaphore * exists before before the specified block time expires. */ -QueueSetMemberHandle_t xQueueSelectFromSet( QueueSetHandle_t xQueueSet, - const TickType_t xTicksToWait ) PRIVILEGED_FUNCTION; +#if ( configUSE_QUEUE_SETS == 1 ) + QueueSetMemberHandle_t xQueueSelectFromSet( QueueSetHandle_t xQueueSet, + const TickType_t xTicksToWait ) PRIVILEGED_FUNCTION; +#endif /* * A version of xQueueSelectFromSet() that can be used from an ISR. */ -QueueSetMemberHandle_t xQueueSelectFromSetFromISR( QueueSetHandle_t xQueueSet ) PRIVILEGED_FUNCTION; +#if ( configUSE_QUEUE_SETS == 1 ) + QueueSetMemberHandle_t xQueueSelectFromSetFromISR( QueueSetHandle_t xQueueSet ) PRIVILEGED_FUNCTION; +#endif /* Not public API functions. */ void vQueueWaitForMessageRestricted( QueueHandle_t xQueue, @@ -1748,10 +1784,20 @@ void vQueueWaitForMessageRestricted( QueueHandle_t xQueue, const BaseType_t xWaitIndefinitely ) PRIVILEGED_FUNCTION; BaseType_t xQueueGenericReset( QueueHandle_t xQueue, BaseType_t xNewQueue ) PRIVILEGED_FUNCTION; -void vQueueSetQueueNumber( QueueHandle_t xQueue, - UBaseType_t uxQueueNumber ) PRIVILEGED_FUNCTION; -UBaseType_t uxQueueGetQueueNumber( QueueHandle_t xQueue ) PRIVILEGED_FUNCTION; -uint8_t ucQueueGetQueueType( QueueHandle_t xQueue ) PRIVILEGED_FUNCTION; + +#if ( configUSE_TRACE_FACILITY == 1 ) + void vQueueSetQueueNumber( QueueHandle_t xQueue, + UBaseType_t uxQueueNumber ) PRIVILEGED_FUNCTION; +#endif + +#if ( configUSE_TRACE_FACILITY == 1 ) + UBaseType_t uxQueueGetQueueNumber( QueueHandle_t xQueue ) PRIVILEGED_FUNCTION; +#endif + +#if ( configUSE_TRACE_FACILITY == 1 ) + uint8_t ucQueueGetQueueType( QueueHandle_t xQueue ) PRIVILEGED_FUNCTION; +#endif + UBaseType_t uxQueueGetQueueItemSize( QueueHandle_t xQueue ) PRIVILEGED_FUNCTION; UBaseType_t uxQueueGetQueueLength( QueueHandle_t xQueue ) PRIVILEGED_FUNCTION; diff --git a/Source/include/semphr.h b/Source/include/semphr.h index 46ac85a9d..9bcf80c88 100644 --- a/Source/include/semphr.h +++ b/Source/include/semphr.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -1193,7 +1193,8 @@ typedef QueueHandle_t SemaphoreHandle_t; /** * semphr.h * @code{c} - * BaseType_t xSemaphoreGetStaticBuffer( SemaphoreHandle_t xSemaphore ); + * BaseType_t xSemaphoreGetStaticBuffer( SemaphoreHandle_t xSemaphore, + * StaticSemaphore_t ** ppxSemaphoreBuffer ); * @endcode * * Retrieve pointer to a statically created binary semaphore, counting semaphore, diff --git a/Source/include/stack_macros.h b/Source/include/stack_macros.h index 354400d45..060edc609 100644 --- a/Source/include/stack_macros.h +++ b/Source/include/stack_macros.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -56,13 +56,14 @@ #if ( ( configCHECK_FOR_STACK_OVERFLOW == 1 ) && ( portSTACK_GROWTH < 0 ) ) /* Only the current stack state is to be checked. */ - #define taskCHECK_FOR_STACK_OVERFLOW() \ - do { \ - /* Is the currently saved stack pointer within the stack limit? */ \ - if( pxCurrentTCB->pxTopOfStack <= pxCurrentTCB->pxStack + portSTACK_LIMIT_PADDING ) \ - { \ - vApplicationStackOverflowHook( ( TaskHandle_t ) pxCurrentTCB, pxCurrentTCB->pcTaskName ); \ - } \ + #define taskCHECK_FOR_STACK_OVERFLOW() \ + do { \ + /* Is the currently saved stack pointer within the stack limit? */ \ + if( pxCurrentTCB->pxTopOfStack <= pxCurrentTCB->pxStack + portSTACK_LIMIT_PADDING ) \ + { \ + char * pcOverflowTaskName = pxCurrentTCB->pcTaskName; \ + vApplicationStackOverflowHook( ( TaskHandle_t ) pxCurrentTCB, pcOverflowTaskName ); \ + } \ } while( 0 ) #endif /* configCHECK_FOR_STACK_OVERFLOW == 1 */ @@ -71,14 +72,15 @@ #if ( ( configCHECK_FOR_STACK_OVERFLOW == 1 ) && ( portSTACK_GROWTH > 0 ) ) /* Only the current stack state is to be checked. */ - #define taskCHECK_FOR_STACK_OVERFLOW() \ - do { \ - \ - /* Is the currently saved stack pointer within the stack limit? */ \ - if( pxCurrentTCB->pxTopOfStack >= pxCurrentTCB->pxEndOfStack - portSTACK_LIMIT_PADDING ) \ - { \ - vApplicationStackOverflowHook( ( TaskHandle_t ) pxCurrentTCB, pxCurrentTCB->pcTaskName ); \ - } \ + #define taskCHECK_FOR_STACK_OVERFLOW() \ + do { \ + \ + /* Is the currently saved stack pointer within the stack limit? */ \ + if( pxCurrentTCB->pxTopOfStack >= pxCurrentTCB->pxEndOfStack - portSTACK_LIMIT_PADDING ) \ + { \ + char * pcOverflowTaskName = pxCurrentTCB->pcTaskName; \ + vApplicationStackOverflowHook( ( TaskHandle_t ) pxCurrentTCB, pcOverflowTaskName ); \ + } \ } while( 0 ) #endif /* configCHECK_FOR_STACK_OVERFLOW == 1 */ @@ -86,18 +88,19 @@ #if ( ( configCHECK_FOR_STACK_OVERFLOW > 1 ) && ( portSTACK_GROWTH < 0 ) ) - #define taskCHECK_FOR_STACK_OVERFLOW() \ - do { \ - const uint32_t * const pulStack = ( uint32_t * ) pxCurrentTCB->pxStack; \ - const uint32_t ulCheckValue = ( uint32_t ) 0xa5a5a5a5; \ - \ - if( ( pulStack[ 0 ] != ulCheckValue ) || \ - ( pulStack[ 1 ] != ulCheckValue ) || \ - ( pulStack[ 2 ] != ulCheckValue ) || \ - ( pulStack[ 3 ] != ulCheckValue ) ) \ - { \ - vApplicationStackOverflowHook( ( TaskHandle_t ) pxCurrentTCB, pxCurrentTCB->pcTaskName ); \ - } \ + #define taskCHECK_FOR_STACK_OVERFLOW() \ + do { \ + const uint32_t * const pulStack = ( uint32_t * ) pxCurrentTCB->pxStack; \ + const uint32_t ulCheckValue = ( uint32_t ) 0xa5a5a5a5U; \ + \ + if( ( pulStack[ 0 ] != ulCheckValue ) || \ + ( pulStack[ 1 ] != ulCheckValue ) || \ + ( pulStack[ 2 ] != ulCheckValue ) || \ + ( pulStack[ 3 ] != ulCheckValue ) ) \ + { \ + char * pcOverflowTaskName = pxCurrentTCB->pcTaskName; \ + vApplicationStackOverflowHook( ( TaskHandle_t ) pxCurrentTCB, pcOverflowTaskName ); \ + } \ } while( 0 ) #endif /* #if( configCHECK_FOR_STACK_OVERFLOW > 1 ) */ @@ -120,7 +123,8 @@ /* Has the extremity of the task stack ever been written over? */ \ if( memcmp( ( void * ) pcEndOfStack, ( void * ) ucExpectedStackBytes, sizeof( ucExpectedStackBytes ) ) != 0 ) \ { \ - vApplicationStackOverflowHook( ( TaskHandle_t ) pxCurrentTCB, pxCurrentTCB->pcTaskName ); \ + char * pcOverflowTaskName = pxCurrentTCB->pcTaskName; \ + vApplicationStackOverflowHook( ( TaskHandle_t ) pxCurrentTCB, pcOverflowTaskName ); \ } \ } while( 0 ) diff --git a/Source/include/stdint.readme b/Source/include/stdint.readme index 11664f308..9c1ebf9bf 100644 --- a/Source/include/stdint.readme +++ b/Source/include/stdint.readme @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/Source/include/stream_buffer.h b/Source/include/stream_buffer.h index 48ca266d6..d5eed1d29 100644 --- a/Source/include/stream_buffer.h +++ b/Source/include/stream_buffer.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -918,14 +918,15 @@ StreamBufferHandle_t xStreamBufferGenericCreate( size_t xBufferSizeBytes, StreamBufferCallbackFunction_t pxSendCompletedCallback, StreamBufferCallbackFunction_t pxReceiveCompletedCallback ) PRIVILEGED_FUNCTION; - -StreamBufferHandle_t xStreamBufferGenericCreateStatic( size_t xBufferSizeBytes, - size_t xTriggerLevelBytes, - BaseType_t xIsMessageBuffer, - uint8_t * const pucStreamBufferStorageArea, - StaticStreamBuffer_t * const pxStaticStreamBuffer, - StreamBufferCallbackFunction_t pxSendCompletedCallback, - StreamBufferCallbackFunction_t pxReceiveCompletedCallback ) PRIVILEGED_FUNCTION; +#if ( configSUPPORT_STATIC_ALLOCATION == 1 ) + StreamBufferHandle_t xStreamBufferGenericCreateStatic( size_t xBufferSizeBytes, + size_t xTriggerLevelBytes, + BaseType_t xIsMessageBuffer, + uint8_t * const pucStreamBufferStorageArea, + StaticStreamBuffer_t * const pxStaticStreamBuffer, + StreamBufferCallbackFunction_t pxSendCompletedCallback, + StreamBufferCallbackFunction_t pxReceiveCompletedCallback ) PRIVILEGED_FUNCTION; +#endif size_t xStreamBufferNextMessageLengthBytes( StreamBufferHandle_t xStreamBuffer ) PRIVILEGED_FUNCTION; diff --git a/Source/include/task.h b/Source/include/task.h index 1207e18c8..7ee076963 100644 --- a/Source/include/task.h +++ b/Source/include/task.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -53,10 +53,10 @@ * The tskKERNEL_VERSION_MAJOR, tskKERNEL_VERSION_MINOR, tskKERNEL_VERSION_BUILD * values will reflect the last released version number. */ -#define tskKERNEL_VERSION_NUMBER "V10.6.2" -#define tskKERNEL_VERSION_MAJOR 10 -#define tskKERNEL_VERSION_MINOR 6 -#define tskKERNEL_VERSION_BUILD 2 +#define tskKERNEL_VERSION_NUMBER "V11.0.1" +#define tskKERNEL_VERSION_MAJOR 11 +#define tskKERNEL_VERSION_MINOR 0 +#define tskKERNEL_VERSION_BUILD 1 /* MPU region parameters passed in ulParameters * of MemoryRegion_t struct. */ @@ -89,13 +89,14 @@ * \ingroup Tasks */ struct tskTaskControlBlock; /* The old naming convention is used to prevent breaking kernel aware debuggers. */ -typedef struct tskTaskControlBlock * TaskHandle_t; +typedef struct tskTaskControlBlock * TaskHandle_t; +typedef const struct tskTaskControlBlock * ConstTaskHandle_t; /* * Defines the prototype to which the application task hook function must * conform. */ -typedef BaseType_t (* TaskHookFunction_t)( void * ); +typedef BaseType_t (* TaskHookFunction_t)( void * arg ); /* Task states returned by eTaskGetState. */ typedef enum @@ -143,7 +144,7 @@ typedef struct xMEMORY_REGION typedef struct xTASK_PARAMETERS { TaskFunction_t pvTaskCode; - const char * pcName; /*lint !e971 Unqualified char types are allowed for strings and single characters only. */ + const char * pcName; configSTACK_DEPTH_TYPE usStackDepth; void * pvParameters; UBaseType_t uxPriority; @@ -159,18 +160,21 @@ typedef struct xTASK_PARAMETERS typedef struct xTASK_STATUS { TaskHandle_t xHandle; /* The handle of the task to which the rest of the information in the structure relates. */ - const char * pcTaskName; /* A pointer to the task's name. This value will be invalid if the task was deleted since the structure was populated! */ /*lint !e971 Unqualified char types are allowed for strings and single characters only. */ + const char * pcTaskName; /* A pointer to the task's name. This value will be invalid if the task was deleted since the structure was populated! */ UBaseType_t xTaskNumber; /* A number unique to the task. */ eTaskState eCurrentState; /* The state in which the task existed when the structure was populated. */ UBaseType_t uxCurrentPriority; /* The priority at which the task was running (may be inherited) when the structure was populated. */ UBaseType_t uxBasePriority; /* The priority to which the task will return if the task's current priority has been inherited to avoid unbounded priority inversion when obtaining a mutex. Only valid if configUSE_MUTEXES is defined as 1 in FreeRTOSConfig.h. */ configRUN_TIME_COUNTER_TYPE ulRunTimeCounter; /* The total run time allocated to the task so far, as defined by the run time stats clock. See https://www.FreeRTOS.org/rtos-run-time-stats.html. Only valid when configGENERATE_RUN_TIME_STATS is defined as 1 in FreeRTOSConfig.h. */ StackType_t * pxStackBase; /* Points to the lowest address of the task's stack area. */ - #if ( ( portSTACK_GROWTH > 0 ) && ( configRECORD_STACK_HIGH_ADDRESS == 1 ) ) + #if ( ( portSTACK_GROWTH > 0 ) || ( configRECORD_STACK_HIGH_ADDRESS == 1 ) ) StackType_t * pxTopOfStack; /* Points to the top address of the task's stack area. */ StackType_t * pxEndOfStack; /* Points to the end address of the task's stack area. */ #endif configSTACK_DEPTH_TYPE usStackHighWaterMark; /* The minimum amount of stack space that has remained for the task since the task was created. The closer this value is to zero the closer the task has come to overflowing its stack. */ + #if ( ( configUSE_CORE_AFFINITY == 1 ) && ( configNUMBER_OF_CORES > 1 ) ) + UBaseType_t uxCoreAffinityMask; /* The core affinity mask for the task */ + #endif } TaskStatus_t; /* Possible return values for eTaskConfirmSleepModeStatus(). */ @@ -190,6 +194,13 @@ typedef enum */ #define tskIDLE_PRIORITY ( ( UBaseType_t ) 0U ) +/** + * Defines affinity to all available cores. + * + * \ingroup TaskUtils + */ +#define tskNO_AFFINITY ( ( UBaseType_t ) -1 ) + /** * task. h * @@ -198,7 +209,7 @@ typedef enum * \defgroup taskYIELD taskYIELD * \ingroup SchedulerControl */ -#define taskYIELD() portYIELD() +#define taskYIELD() portYIELD() /** * task. h @@ -212,8 +223,12 @@ typedef enum * \defgroup taskENTER_CRITICAL taskENTER_CRITICAL * \ingroup SchedulerControl */ -#define taskENTER_CRITICAL() portENTER_CRITICAL() -#define taskENTER_CRITICAL_FROM_ISR() portSET_INTERRUPT_MASK_FROM_ISR() +#define taskENTER_CRITICAL() portENTER_CRITICAL() +#if ( configNUMBER_OF_CORES == 1 ) + #define taskENTER_CRITICAL_FROM_ISR() portSET_INTERRUPT_MASK_FROM_ISR() +#else + #define taskENTER_CRITICAL_FROM_ISR() portENTER_CRITICAL_FROM_ISR() +#endif /** * task. h @@ -227,8 +242,12 @@ typedef enum * \defgroup taskEXIT_CRITICAL taskEXIT_CRITICAL * \ingroup SchedulerControl */ -#define taskEXIT_CRITICAL() portEXIT_CRITICAL() -#define taskEXIT_CRITICAL_FROM_ISR( x ) portCLEAR_INTERRUPT_MASK_FROM_ISR( x ) +#define taskEXIT_CRITICAL() portEXIT_CRITICAL() +#if ( configNUMBER_OF_CORES == 1 ) + #define taskEXIT_CRITICAL_FROM_ISR( x ) portCLEAR_INTERRUPT_MASK_FROM_ISR( x ) +#else + #define taskEXIT_CRITICAL_FROM_ISR( x ) portEXIT_CRITICAL_FROM_ISR( x ) +#endif /** * task. h @@ -238,7 +257,7 @@ typedef enum * \defgroup taskDISABLE_INTERRUPTS taskDISABLE_INTERRUPTS * \ingroup SchedulerControl */ -#define taskDISABLE_INTERRUPTS() portDISABLE_INTERRUPTS() +#define taskDISABLE_INTERRUPTS() portDISABLE_INTERRUPTS() /** * task. h @@ -248,7 +267,7 @@ typedef enum * \defgroup taskENABLE_INTERRUPTS taskENABLE_INTERRUPTS * \ingroup SchedulerControl */ -#define taskENABLE_INTERRUPTS() portENABLE_INTERRUPTS() +#define taskENABLE_INTERRUPTS() portENABLE_INTERRUPTS() /* Definitions returned by xTaskGetSchedulerState(). taskSCHEDULER_SUSPENDED is * 0 to generate more optimal code when configASSERT() is defined as the constant @@ -257,6 +276,8 @@ typedef enum #define taskSCHEDULER_NOT_STARTED ( ( BaseType_t ) 1 ) #define taskSCHEDULER_RUNNING ( ( BaseType_t ) 2 ) +/* Checks if core ID is valid. */ +#define taskVALID_CORE_ID( xCoreID ) ( ( ( ( ( BaseType_t ) 0 <= ( xCoreID ) ) && ( ( xCoreID ) < ( BaseType_t ) configNUMBER_OF_CORES ) ) ) ? ( pdTRUE ) : ( pdFALSE ) ) /*----------------------------------------------------------- * TASK CREATION API @@ -358,13 +379,23 @@ typedef enum */ #if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) BaseType_t xTaskCreate( TaskFunction_t pxTaskCode, - const char * const pcName, /*lint !e971 Unqualified char types are allowed for strings and single characters only. */ + const char * const pcName, const configSTACK_DEPTH_TYPE usStackDepth, void * const pvParameters, UBaseType_t uxPriority, TaskHandle_t * const pxCreatedTask ) PRIVILEGED_FUNCTION; #endif +#if ( ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) && ( configNUMBER_OF_CORES > 1 ) && ( configUSE_CORE_AFFINITY == 1 ) ) + BaseType_t xTaskCreateAffinitySet( TaskFunction_t pxTaskCode, + const char * const pcName, + const configSTACK_DEPTH_TYPE usStackDepth, + void * const pvParameters, + UBaseType_t uxPriority, + UBaseType_t uxCoreAffinityMask, + TaskHandle_t * const pxCreatedTask ) PRIVILEGED_FUNCTION; +#endif + /** * task. h * @code{c} @@ -475,7 +506,7 @@ typedef enum */ #if ( configSUPPORT_STATIC_ALLOCATION == 1 ) TaskHandle_t xTaskCreateStatic( TaskFunction_t pxTaskCode, - const char * const pcName, /*lint !e971 Unqualified char types are allowed for strings and single characters only. */ + const char * const pcName, const uint32_t ulStackDepth, void * const pvParameters, UBaseType_t uxPriority, @@ -483,6 +514,17 @@ typedef enum StaticTask_t * const pxTaskBuffer ) PRIVILEGED_FUNCTION; #endif /* configSUPPORT_STATIC_ALLOCATION */ +#if ( ( configSUPPORT_STATIC_ALLOCATION == 1 ) && ( configNUMBER_OF_CORES > 1 ) && ( configUSE_CORE_AFFINITY == 1 ) ) + TaskHandle_t xTaskCreateStaticAffinitySet( TaskFunction_t pxTaskCode, + const char * const pcName, + const uint32_t ulStackDepth, + void * const pvParameters, + UBaseType_t uxPriority, + StackType_t * const puxStackBuffer, + StaticTask_t * const pxTaskBuffer, + UBaseType_t uxCoreAffinityMask ) PRIVILEGED_FUNCTION; +#endif + /** * task. h * @code{c} @@ -561,6 +603,12 @@ typedef enum TaskHandle_t * pxCreatedTask ) PRIVILEGED_FUNCTION; #endif +#if ( ( portUSING_MPU_WRAPPERS == 1 ) && ( configNUMBER_OF_CORES > 1 ) && ( configUSE_CORE_AFFINITY == 1 ) ) + BaseType_t xTaskCreateRestrictedAffinitySet( const TaskParameters_t * const pxTaskDefinition, + UBaseType_t uxCoreAffinityMask, + TaskHandle_t * pxCreatedTask ) PRIVILEGED_FUNCTION; +#endif + /** * task. h * @code{c} @@ -651,6 +699,12 @@ typedef enum TaskHandle_t * pxCreatedTask ) PRIVILEGED_FUNCTION; #endif +#if ( ( portUSING_MPU_WRAPPERS == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) && ( configNUMBER_OF_CORES > 1 ) && ( configUSE_CORE_AFFINITY == 1 ) ) + BaseType_t xTaskCreateRestrictedStaticAffinitySet( const TaskParameters_t * const pxTaskDefinition, + UBaseType_t uxCoreAffinityMask, + TaskHandle_t * pxCreatedTask ) PRIVILEGED_FUNCTION; +#endif + /** * task. h * @code{c} @@ -661,7 +715,7 @@ typedef enum * a call to xTaskCreateRestricted(). These regions can be redefined using * vTaskAllocateMPURegions(). * - * @param xTask The handle of the task being updated. + * @param xTaskToModify The handle of the task being updated. * * @param[in] pxRegions A pointer to a MemoryRegion_t structure that contains the * new memory region definitions. @@ -698,8 +752,10 @@ typedef enum * \defgroup vTaskAllocateMPURegions vTaskAllocateMPURegions * \ingroup Tasks */ -void vTaskAllocateMPURegions( TaskHandle_t xTask, - const MemoryRegion_t * const pxRegions ) PRIVILEGED_FUNCTION; +#if ( portUSING_MPU_WRAPPERS == 1 ) + void vTaskAllocateMPURegions( TaskHandle_t xTaskToModify, + const MemoryRegion_t * const pxRegions ) PRIVILEGED_FUNCTION; +#endif /** * task. h @@ -906,7 +962,9 @@ BaseType_t xTaskDelayUntil( TickType_t * const pxPreviousWakeTime, * \defgroup xTaskAbortDelay xTaskAbortDelay * \ingroup TaskCtrl */ -BaseType_t xTaskAbortDelay( TaskHandle_t xTask ) PRIVILEGED_FUNCTION; +#if ( INCLUDE_xTaskAbortDelay == 1 ) + BaseType_t xTaskAbortDelay( TaskHandle_t xTask ) PRIVILEGED_FUNCTION; +#endif /** * task. h @@ -967,6 +1025,37 @@ UBaseType_t uxTaskPriorityGet( const TaskHandle_t xTask ) PRIVILEGED_FUNCTION; */ UBaseType_t uxTaskPriorityGetFromISR( const TaskHandle_t xTask ) PRIVILEGED_FUNCTION; +/** + * task. h + * @code{c} + * UBaseType_t uxTaskBasePriorityGet( const TaskHandle_t xTask ); + * @endcode + * + * INCLUDE_uxTaskPriorityGet and configUSE_MUTEXES must be defined as 1 for this + * function to be available. See the configuration section for more information. + * + * Obtain the base priority of any task. + * + * @param xTask Handle of the task to be queried. Passing a NULL + * handle results in the base priority of the calling task being returned. + * + * @return The base priority of xTask. + * + * \defgroup uxTaskPriorityGet uxTaskBasePriorityGet + * \ingroup TaskCtrl + */ +UBaseType_t uxTaskBasePriorityGet( const TaskHandle_t xTask ) PRIVILEGED_FUNCTION; + +/** + * task. h + * @code{c} + * UBaseType_t uxTaskBasePriorityGetFromISR( const TaskHandle_t xTask ); + * @endcode + * + * A version of uxTaskBasePriorityGet() that can be used from an ISR. + */ +UBaseType_t uxTaskBasePriorityGetFromISR( const TaskHandle_t xTask ) PRIVILEGED_FUNCTION; + /** * task. h * @code{c} @@ -985,7 +1074,9 @@ UBaseType_t uxTaskPriorityGetFromISR( const TaskHandle_t xTask ) PRIVILEGED_FUNC * state of the task might change between the function being called, and the * functions return value being tested by the calling task. */ -eTaskState eTaskGetState( TaskHandle_t xTask ) PRIVILEGED_FUNCTION; +#if ( ( INCLUDE_eTaskGetState == 1 ) || ( configUSE_TRACE_FACILITY == 1 ) || ( INCLUDE_xTaskAbortDelay == 1 ) ) + eTaskState eTaskGetState( TaskHandle_t xTask ) PRIVILEGED_FUNCTION; +#endif /** * task. h @@ -1043,10 +1134,12 @@ eTaskState eTaskGetState( TaskHandle_t xTask ) PRIVILEGED_FUNCTION; * \defgroup vTaskGetInfo vTaskGetInfo * \ingroup TaskCtrl */ -void vTaskGetInfo( TaskHandle_t xTask, - TaskStatus_t * pxTaskStatus, - BaseType_t xGetFreeStackSpace, - eTaskState eState ) PRIVILEGED_FUNCTION; +#if ( configUSE_TRACE_FACILITY == 1 ) + void vTaskGetInfo( TaskHandle_t xTask, + TaskStatus_t * pxTaskStatus, + BaseType_t xGetFreeStackSpace, + eTaskState eState ) PRIVILEGED_FUNCTION; +#endif /** * task. h @@ -1228,6 +1321,164 @@ void vTaskResume( TaskHandle_t xTaskToResume ) PRIVILEGED_FUNCTION; */ BaseType_t xTaskResumeFromISR( TaskHandle_t xTaskToResume ) PRIVILEGED_FUNCTION; +#if ( configUSE_CORE_AFFINITY == 1 ) + +/** + * @brief Sets the core affinity mask for a task. + * + * It sets the cores on which a task can run. configUSE_CORE_AFFINITY must + * be defined as 1 for this function to be available. + * + * @param xTask The handle of the task to set the core affinity mask for. + * Passing NULL will set the core affinity mask for the calling task. + * + * @param uxCoreAffinityMask A bitwise value that indicates the cores on + * which the task can run. Cores are numbered from 0 to configNUMBER_OF_CORES - 1. + * For example, to ensure that a task can run on core 0 and core 1, set + * uxCoreAffinityMask to 0x03. + * + * Example usage: + * + * // The function that creates task. + * void vAFunction( void ) + * { + * TaskHandle_t xHandle; + * UBaseType_t uxCoreAffinityMask; + * + * // Create a task, storing the handle. + * xTaskCreate( vTaskCode, "NAME", STACK_SIZE, NULL, tskIDLE_PRIORITY, &( xHandle ) ); + * + * // Define the core affinity mask such that this task can only run + * // on core 0 and core 2. + * uxCoreAffinityMask = ( ( 1 << 0 ) | ( 1 << 2 ) ); + * + * //Set the core affinity mask for the task. + * vTaskCoreAffinitySet( xHandle, uxCoreAffinityMask ); + * } + */ + void vTaskCoreAffinitySet( const TaskHandle_t xTask, + UBaseType_t uxCoreAffinityMask ); +#endif + +#if ( ( configNUMBER_OF_CORES > 1 ) && ( configUSE_CORE_AFFINITY == 1 ) ) + +/** + * @brief Gets the core affinity mask for a task. + * + * configUSE_CORE_AFFINITY must be defined as 1 for this function to be + * available. + * + * @param xTask The handle of the task to get the core affinity mask for. + * Passing NULL will get the core affinity mask for the calling task. + * + * @return The core affinity mask which is a bitwise value that indicates + * the cores on which a task can run. Cores are numbered from 0 to + * configNUMBER_OF_CORES - 1. For example, if a task can run on core 0 and core 1, + * the core affinity mask is 0x03. + * + * Example usage: + * + * // Task handle of the networking task - it is populated elsewhere. + * TaskHandle_t xNetworkingTaskHandle; + * + * void vAFunction( void ) + * { + * TaskHandle_t xHandle; + * UBaseType_t uxNetworkingCoreAffinityMask; + * + * // Create a task, storing the handle. + * xTaskCreate( vTaskCode, "NAME", STACK_SIZE, NULL, tskIDLE_PRIORITY, &( xHandle ) ); + * + * //Get the core affinity mask for the networking task. + * uxNetworkingCoreAffinityMask = vTaskCoreAffinityGet( xNetworkingTaskHandle ); + * + * // Here is a hypothetical scenario, just for the example. Assume that we + * // have 2 cores - Core 0 and core 1. We want to pin the application task to + * // the core different than the networking task to ensure that the + * // application task does not interfere with networking. + * if( ( uxNetworkingCoreAffinityMask & ( 1 << 0 ) ) != 0 ) + * { + * // The networking task can run on core 0, pin our task to core 1. + * vTaskCoreAffinitySet( xHandle, ( 1 << 1 ) ); + * } + * else + * { + * // Otherwise, pin our task to core 0. + * vTaskCoreAffinitySet( xHandle, ( 1 << 0 ) ); + * } + * } + */ + UBaseType_t vTaskCoreAffinityGet( ConstTaskHandle_t xTask ); +#endif + +#if ( configUSE_TASK_PREEMPTION_DISABLE == 1 ) + +/** + * @brief Disables preemption for a task. + * + * @param xTask The handle of the task to disable preemption. Passing NULL + * disables preemption for the calling task. + * + * Example usage: + * + * void vTaskCode( void *pvParameters ) + * { + * // Silence warnings about unused parameters. + * ( void ) pvParameters; + * + * for( ;; ) + * { + * // ... Perform some function here. + * + * // Disable preemption for this task. + * vTaskPreemptionDisable( NULL ); + * + * // The task will not be preempted when it is executing in this portion ... + * + * // ... until the preemption is enabled again. + * vTaskPreemptionEnable( NULL ); + * + * // The task can be preempted when it is executing in this portion. + * } + * } + */ + void vTaskPreemptionDisable( const TaskHandle_t xTask ); +#endif + +#if ( configUSE_TASK_PREEMPTION_DISABLE == 1 ) + +/** + * @brief Enables preemption for a task. + * + * @param xTask The handle of the task to enable preemption. Passing NULL + * enables preemption for the calling task. + * + * Example usage: + * + * void vTaskCode( void *pvParameters ) + * { + * // Silence warnings about unused parameters. + * ( void ) pvParameters; + * + * for( ;; ) + * { + * // ... Perform some function here. + * + * // Disable preemption for this task. + * vTaskPreemptionDisable( NULL ); + * + * // The task will not be preempted when it is executing in this portion ... + * + * // ... until the preemption is enabled again. + * vTaskPreemptionEnable( NULL ); + * + * // The task can be preempted when it is executing in this portion. + * } + * } + */ + void vTaskPreemptionEnable( const TaskHandle_t xTask ); +#endif + /*----------------------------------------------------------- * SCHEDULER CONTROL *----------------------------------------------------------*/ @@ -1494,7 +1745,7 @@ UBaseType_t uxTaskGetNumberOfTasks( void ) PRIVILEGED_FUNCTION; * \defgroup pcTaskGetName pcTaskGetName * \ingroup TaskUtils */ -char * pcTaskGetName( TaskHandle_t xTaskToQuery ) PRIVILEGED_FUNCTION; /*lint !e971 Unqualified char types are allowed for strings and single characters only. */ +char * pcTaskGetName( TaskHandle_t xTaskToQuery ) PRIVILEGED_FUNCTION; /** * task. h @@ -1512,7 +1763,9 @@ char * pcTaskGetName( TaskHandle_t xTaskToQuery ) PRIVILEGED_FUNCTION; /*lint !e * \defgroup pcTaskGetHandle pcTaskGetHandle * \ingroup TaskUtils */ -TaskHandle_t xTaskGetHandle( const char * pcNameToQuery ) PRIVILEGED_FUNCTION; /*lint !e971 Unqualified char types are allowed for strings and single characters only. */ +#if ( INCLUDE_xTaskGetHandle == 1 ) + TaskHandle_t xTaskGetHandle( const char * pcNameToQuery ) PRIVILEGED_FUNCTION; +#endif /** * task. h @@ -1571,7 +1824,9 @@ TaskHandle_t xTaskGetHandle( const char * pcNameToQuery ) PRIVILEGED_FUNCTION; / * actual spaces on the stack rather than bytes) since the task referenced by * xTask was created. */ -UBaseType_t uxTaskGetStackHighWaterMark( TaskHandle_t xTask ) PRIVILEGED_FUNCTION; +#if ( INCLUDE_uxTaskGetStackHighWaterMark == 1 ) + UBaseType_t uxTaskGetStackHighWaterMark( TaskHandle_t xTask ) PRIVILEGED_FUNCTION; +#endif /** * task.h @@ -1600,7 +1855,9 @@ UBaseType_t uxTaskGetStackHighWaterMark( TaskHandle_t xTask ) PRIVILEGED_FUNCTIO * actual spaces on the stack rather than bytes) since the task referenced by * xTask was created. */ -configSTACK_DEPTH_TYPE uxTaskGetStackHighWaterMark2( TaskHandle_t xTask ) PRIVILEGED_FUNCTION; +#if ( INCLUDE_uxTaskGetStackHighWaterMark2 == 1 ) + configSTACK_DEPTH_TYPE uxTaskGetStackHighWaterMark2( TaskHandle_t xTask ) PRIVILEGED_FUNCTION; +#endif /* When using trace macros it is sometimes necessary to include task.h before * FreeRTOS.h. When this is done TaskHookFunction_t will not yet have been defined, @@ -1679,6 +1936,9 @@ configSTACK_DEPTH_TYPE uxTaskGetStackHighWaterMark2( TaskHandle_t xTask ) PRIVIL * @param xTask the task that just exceeded its stack boundaries. * @param pcTaskName A character string containing the name of the offending task. */ + /* MISRA Ref 8.6.1 [External linkage] */ + /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-86 */ + /* coverity[misra_c_2012_rule_8_6_violation] */ void vApplicationStackOverflowHook( TaskHandle_t xTask, char * pcTaskName ); @@ -1697,6 +1957,9 @@ configSTACK_DEPTH_TYPE uxTaskGetStackHighWaterMark2( TaskHandle_t xTask ) PRIVIL * the overhead of a separate task. * NOTE: vApplicationIdleHook() MUST NOT, UNDER ANY CIRCUMSTANCES, CALL A FUNCTION THAT MIGHT BLOCK. */ + /* MISRA Ref 8.6.1 [External linkage] */ + /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-86 */ + /* coverity[misra_c_2012_rule_8_6_violation] */ void vApplicationIdleHook( void ); #endif @@ -1712,7 +1975,10 @@ configSTACK_DEPTH_TYPE uxTaskGetStackHighWaterMark2( TaskHandle_t xTask ) PRIVIL * * This hook function is called in the system tick handler after any OS work is completed. */ - void vApplicationTickHook( void ); /*lint !e526 Symbol not defined as it is an application callback. */ + /* MISRA Ref 8.6.1 [External linkage] */ + /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-86 */ + /* coverity[misra_c_2012_rule_8_6_violation] */ + void vApplicationTickHook( void ); #endif @@ -1733,8 +1999,39 @@ configSTACK_DEPTH_TYPE uxTaskGetStackHighWaterMark2( TaskHandle_t xTask ) PRIVIL */ void vApplicationGetIdleTaskMemory( StaticTask_t ** ppxIdleTaskTCBBuffer, StackType_t ** ppxIdleTaskStackBuffer, - uint32_t * pulIdleTaskStackSize ); /*lint !e526 Symbol not defined as it is an application callback. */ -#endif + uint32_t * pulIdleTaskStackSize ); + +/** + * task.h + * @code{c} + * void vApplicationGetPassiveIdleTaskMemory( StaticTask_t ** ppxIdleTaskTCBBuffer, StackType_t ** ppxIdleTaskStackBuffer, uint32_t *pulIdleTaskStackSize, BaseType_t xCoreID ) + * @endcode + * + * This function is used to provide a statically allocated block of memory to FreeRTOS to hold the Idle Tasks TCB. This function is required when + * configSUPPORT_STATIC_ALLOCATION is set. For more information see this URI: https://www.FreeRTOS.org/a00110.html#configSUPPORT_STATIC_ALLOCATION + * + * In the FreeRTOS SMP, there are a total of configNUMBER_OF_CORES idle tasks: + * 1. 1 Active idle task which does all the housekeeping. + * 2. ( configNUMBER_OF_CORES - 1 ) Passive idle tasks which do nothing. + * These idle tasks are created to ensure that each core has an idle task to run when + * no other task is available to run. + * + * The function vApplicationGetPassiveIdleTaskMemory is called with passive idle + * task index 0, 1 ... ( configNUMBER_OF_CORES - 2 ) to get memory for passive idle + * tasks. + * + * @param ppxIdleTaskTCBBuffer A handle to a statically allocated TCB buffer + * @param ppxIdleTaskStackBuffer A handle to a statically allocated Stack buffer for the idle task + * @param pulIdleTaskStackSize A pointer to the number of elements that will fit in the allocated stack buffer + * @param xPassiveIdleTaskIndex The passive idle task index of the idle task buffer + */ + #if ( configNUMBER_OF_CORES > 1 ) + void vApplicationGetPassiveIdleTaskMemory( StaticTask_t ** ppxIdleTaskTCBBuffer, + StackType_t ** ppxIdleTaskStackBuffer, + uint32_t * pulIdleTaskStackSize, + BaseType_t xPassiveIdleTaskIndex ); + #endif /* #if ( configNUMBER_OF_CORES > 1 ) */ +#endif /* if ( configSUPPORT_STATIC_ALLOCATION == 1 ) */ /** * task.h @@ -1749,17 +2046,35 @@ configSTACK_DEPTH_TYPE uxTaskGetStackHighWaterMark2( TaskHandle_t xTask ) PRIVIL * wants. The return value is the value returned by the task hook function * registered by the user. */ -BaseType_t xTaskCallApplicationTaskHook( TaskHandle_t xTask, - void * pvParameter ) PRIVILEGED_FUNCTION; +#if ( configUSE_APPLICATION_TASK_TAG == 1 ) + BaseType_t xTaskCallApplicationTaskHook( TaskHandle_t xTask, + void * pvParameter ) PRIVILEGED_FUNCTION; +#endif /** * xTaskGetIdleTaskHandle() is only available if * INCLUDE_xTaskGetIdleTaskHandle is set to 1 in FreeRTOSConfig.h. * - * Simply returns the handle of the idle task. It is not valid to call - * xTaskGetIdleTaskHandle() before the scheduler has been started. + * In single-core FreeRTOS, this function simply returns the handle of the idle + * task. It is not valid to call xTaskGetIdleTaskHandle() before the scheduler + * has been started. + * + * In the FreeRTOS SMP, there are a total of configNUMBER_OF_CORES idle tasks: + * 1. 1 Active idle task which does all the housekeeping. + * 2. ( configNUMBER_OF_CORES - 1 ) Passive idle tasks which do nothing. + * These idle tasks are created to ensure that each core has an idle task to run when + * no other task is available to run. Call xTaskGetIdleTaskHandle() or + * xTaskGetIdleTaskHandleForCore() with xCoreID set to 0 to get the Active + * idle task handle. Call xTaskGetIdleTaskHandleForCore() with xCoreID set to + * 1,2 ... ( configNUMBER_OF_CORES - 1 ) to get the Passive idle task handles. */ -TaskHandle_t xTaskGetIdleTaskHandle( void ) PRIVILEGED_FUNCTION; +#if ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) + #if ( configNUMBER_OF_CORES == 1 ) + TaskHandle_t xTaskGetIdleTaskHandle( void ) PRIVILEGED_FUNCTION; + #endif /* #if ( configNUMBER_OF_CORES == 1 ) */ + + TaskHandle_t xTaskGetIdleTaskHandleForCore( BaseType_t xCoreID ) PRIVILEGED_FUNCTION; +#endif /* #if ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) */ /** * configUSE_TRACE_FACILITY must be defined as 1 in FreeRTOSConfig.h for @@ -1858,9 +2173,67 @@ TaskHandle_t xTaskGetIdleTaskHandle( void ) PRIVILEGED_FUNCTION; * } * @endcode */ -UBaseType_t uxTaskGetSystemState( TaskStatus_t * const pxTaskStatusArray, - const UBaseType_t uxArraySize, - configRUN_TIME_COUNTER_TYPE * const pulTotalRunTime ) PRIVILEGED_FUNCTION; +#if ( configUSE_TRACE_FACILITY == 1 ) + UBaseType_t uxTaskGetSystemState( TaskStatus_t * const pxTaskStatusArray, + const UBaseType_t uxArraySize, + configRUN_TIME_COUNTER_TYPE * const pulTotalRunTime ) PRIVILEGED_FUNCTION; +#endif + +/** + * task. h + * @code{c} + * void vTaskListTasks( char *pcWriteBuffer, size_t uxBufferLength ); + * @endcode + * + * configUSE_TRACE_FACILITY and configUSE_STATS_FORMATTING_FUNCTIONS must + * both be defined as 1 for this function to be available. See the + * configuration section of the FreeRTOS.org website for more information. + * + * NOTE 1: This function will disable interrupts for its duration. It is + * not intended for normal application runtime use but as a debug aid. + * + * Lists all the current tasks, along with their current state and stack + * usage high water mark. + * + * Tasks are reported as blocked ('B'), ready ('R'), deleted ('D') or + * suspended ('S'). + * + * PLEASE NOTE: + * + * This function is provided for convenience only, and is used by many of the + * demo applications. Do not consider it to be part of the scheduler. + * + * vTaskListTasks() calls uxTaskGetSystemState(), then formats part of the + * uxTaskGetSystemState() output into a human readable table that displays task: + * names, states, priority, stack usage and task number. + * Stack usage specified as the number of unused StackType_t words stack can hold + * on top of stack - not the number of bytes. + * + * vTaskListTasks() has a dependency on the snprintf() C library function that might + * bloat the code size, use a lot of stack, and provide different results on + * different platforms. An alternative, tiny, third party, and limited + * functionality implementation of snprintf() is provided in many of the + * FreeRTOS/Demo sub-directories in a file called printf-stdarg.c (note + * printf-stdarg.c does not provide a full snprintf() implementation!). + * + * It is recommended that production systems call uxTaskGetSystemState() + * directly to get access to raw stats data, rather than indirectly through a + * call to vTaskListTasks(). + * + * @param pcWriteBuffer A buffer into which the above mentioned details + * will be written, in ASCII form. This buffer is assumed to be large + * enough to contain the generated report. Approximately 40 bytes per + * task should be sufficient. + * + * @param uxBufferLength Length of the pcWriteBuffer. + * + * \defgroup vTaskListTasks vTaskListTasks + * \ingroup TaskUtils + */ +#if ( ( configUSE_TRACE_FACILITY == 1 ) && ( configUSE_STATS_FORMATTING_FUNCTIONS > 0 ) ) + void vTaskListTasks( char * pcWriteBuffer, + size_t uxBufferLength ) PRIVILEGED_FUNCTION; +#endif /** * task. h @@ -1872,6 +2245,11 @@ UBaseType_t uxTaskGetSystemState( TaskStatus_t * const pxTaskStatusArray, * both be defined as 1 for this function to be available. See the * configuration section of the FreeRTOS.org website for more information. * + * WARN: This function assumes that the pcWriteBuffer is of length + * configSTATS_BUFFER_MAX_LENGTH. This function is there only for + * backward compatibility. New applications are recommended to + * use vTaskListTasks and supply the length of the pcWriteBuffer explicitly. + * * NOTE 1: This function will disable interrupts for its duration. It is * not intended for normal application runtime use but as a debug aid. * @@ -1892,10 +2270,10 @@ UBaseType_t uxTaskGetSystemState( TaskStatus_t * const pxTaskStatusArray, * Stack usage specified as the number of unused StackType_t words stack can hold * on top of stack - not the number of bytes. * - * vTaskList() has a dependency on the sprintf() C library function that might + * vTaskList() has a dependency on the snprintf() C library function that might * bloat the code size, use a lot of stack, and provide different results on * different platforms. An alternative, tiny, third party, and limited - * functionality implementation of sprintf() is provided in many of the + * functionality implementation of snprintf() is provided in many of the * FreeRTOS/Demo sub-directories in a file called printf-stdarg.c (note * printf-stdarg.c does not provide a full snprintf() implementation!). * @@ -1911,7 +2289,68 @@ UBaseType_t uxTaskGetSystemState( TaskStatus_t * const pxTaskStatusArray, * \defgroup vTaskList vTaskList * \ingroup TaskUtils */ -void vTaskList( char * pcWriteBuffer ) PRIVILEGED_FUNCTION; /*lint !e971 Unqualified char types are allowed for strings and single characters only. */ +#define vTaskList( pcWriteBuffer ) vTaskListTasks( pcWriteBuffer, configSTATS_BUFFER_MAX_LENGTH ) + +/** + * task. h + * @code{c} + * void vTaskGetRunTimeStatistics( char *pcWriteBuffer, size_t uxBufferLength ); + * @endcode + * + * configGENERATE_RUN_TIME_STATS and configUSE_STATS_FORMATTING_FUNCTIONS + * must both be defined as 1 for this function to be available. The application + * must also then provide definitions for + * portCONFIGURE_TIMER_FOR_RUN_TIME_STATS() and portGET_RUN_TIME_COUNTER_VALUE() + * to configure a peripheral timer/counter and return the timers current count + * value respectively. The counter should be at least 10 times the frequency of + * the tick count. + * + * NOTE 1: This function will disable interrupts for its duration. It is + * not intended for normal application runtime use but as a debug aid. + * + * Setting configGENERATE_RUN_TIME_STATS to 1 will result in a total + * accumulated execution time being stored for each task. The resolution + * of the accumulated time value depends on the frequency of the timer + * configured by the portCONFIGURE_TIMER_FOR_RUN_TIME_STATS() macro. + * Calling vTaskGetRunTimeStatistics() writes the total execution time of each + * task into a buffer, both as an absolute count value and as a percentage + * of the total system execution time. + * + * NOTE 2: + * + * This function is provided for convenience only, and is used by many of the + * demo applications. Do not consider it to be part of the scheduler. + * + * vTaskGetRunTimeStatistics() calls uxTaskGetSystemState(), then formats part of + * the uxTaskGetSystemState() output into a human readable table that displays the + * amount of time each task has spent in the Running state in both absolute and + * percentage terms. + * + * vTaskGetRunTimeStatistics() has a dependency on the snprintf() C library function + * that might bloat the code size, use a lot of stack, and provide different + * results on different platforms. An alternative, tiny, third party, and + * limited functionality implementation of snprintf() is provided in many of the + * FreeRTOS/Demo sub-directories in a file called printf-stdarg.c (note + * printf-stdarg.c does not provide a full snprintf() implementation!). + * + * It is recommended that production systems call uxTaskGetSystemState() directly + * to get access to raw stats data, rather than indirectly through a call to + * vTaskGetRunTimeStatistics(). + * + * @param pcWriteBuffer A buffer into which the execution times will be + * written, in ASCII form. This buffer is assumed to be large enough to + * contain the generated report. Approximately 40 bytes per task should + * be sufficient. + * + * @param uxBufferLength Length of the pcWriteBuffer. + * + * \defgroup vTaskGetRunTimeStatistics vTaskGetRunTimeStatistics + * \ingroup TaskUtils + */ +#if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( configUSE_STATS_FORMATTING_FUNCTIONS > 0 ) && ( configUSE_TRACE_FACILITY == 1 ) ) + void vTaskGetRunTimeStatistics( char * pcWriteBuffer, + size_t uxBufferLength ) PRIVILEGED_FUNCTION; +#endif /** * task. h @@ -1927,6 +2366,12 @@ void vTaskList( char * pcWriteBuffer ) PRIVILEGED_FUNCTION; /*lint !e971 Unquali * value respectively. The counter should be at least 10 times the frequency of * the tick count. * + * WARN: This function assumes that the pcWriteBuffer is of length + * configSTATS_BUFFER_MAX_LENGTH. This function is there only for + * backward compatiblity. New applications are recommended to use + * vTaskGetRunTimeStatistics and supply the length of the pcWriteBuffer + * explicitly. + * * NOTE 1: This function will disable interrupts for its duration. It is * not intended for normal application runtime use but as a debug aid. * @@ -1948,10 +2393,10 @@ void vTaskList( char * pcWriteBuffer ) PRIVILEGED_FUNCTION; /*lint !e971 Unquali * amount of time each task has spent in the Running state in both absolute and * percentage terms. * - * vTaskGetRunTimeStats() has a dependency on the sprintf() C library function + * vTaskGetRunTimeStats() has a dependency on the snprintf() C library function * that might bloat the code size, use a lot of stack, and provide different * results on different platforms. An alternative, tiny, third party, and - * limited functionality implementation of sprintf() is provided in many of the + * limited functionality implementation of snprintf() is provided in many of the * FreeRTOS/Demo sub-directories in a file called printf-stdarg.c (note * printf-stdarg.c does not provide a full snprintf() implementation!). * @@ -1967,7 +2412,7 @@ void vTaskList( char * pcWriteBuffer ) PRIVILEGED_FUNCTION; /*lint !e971 Unquali * \defgroup vTaskGetRunTimeStats vTaskGetRunTimeStats * \ingroup TaskUtils */ -void vTaskGetRunTimeStats( char * pcWriteBuffer ) PRIVILEGED_FUNCTION; /*lint !e971 Unqualified char types are allowed for strings and single characters only. */ +#define vTaskGetRunTimeStats( pcWriteBuffer ) vTaskGetRunTimeStatistics( pcWriteBuffer, configSTATS_BUFFER_MAX_LENGTH ) /** * task. h @@ -2002,8 +2447,10 @@ void vTaskGetRunTimeStats( char * pcWriteBuffer ) PRIVILEGED_FUNCTION; /*lint !e * \defgroup ulTaskGetRunTimeCounter ulTaskGetRunTimeCounter * \ingroup TaskUtils */ -configRUN_TIME_COUNTER_TYPE ulTaskGetRunTimeCounter( const TaskHandle_t xTask ) PRIVILEGED_FUNCTION; -configRUN_TIME_COUNTER_TYPE ulTaskGetRunTimePercent( const TaskHandle_t xTask ) PRIVILEGED_FUNCTION; +#if ( configGENERATE_RUN_TIME_STATS == 1 ) + configRUN_TIME_COUNTER_TYPE ulTaskGetRunTimeCounter( const TaskHandle_t xTask ) PRIVILEGED_FUNCTION; + configRUN_TIME_COUNTER_TYPE ulTaskGetRunTimePercent( const TaskHandle_t xTask ) PRIVILEGED_FUNCTION; +#endif /** * task. h @@ -2042,8 +2489,10 @@ configRUN_TIME_COUNTER_TYPE ulTaskGetRunTimePercent( const TaskHandle_t xTask ) * \defgroup ulTaskGetIdleRunTimeCounter ulTaskGetIdleRunTimeCounter * \ingroup TaskUtils */ -configRUN_TIME_COUNTER_TYPE ulTaskGetIdleRunTimeCounter( void ) PRIVILEGED_FUNCTION; -configRUN_TIME_COUNTER_TYPE ulTaskGetIdleRunTimePercent( void ) PRIVILEGED_FUNCTION; +#if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) ) + configRUN_TIME_COUNTER_TYPE ulTaskGetIdleRunTimeCounter( void ) PRIVILEGED_FUNCTION; + configRUN_TIME_COUNTER_TYPE ulTaskGetIdleRunTimePercent( void ) PRIVILEGED_FUNCTION; +#endif /** * task. h @@ -2994,6 +3443,12 @@ BaseType_t xTaskCatchUpTicks( TickType_t xTicksToCatchUp ) PRIVILEGED_FUNCTION; * SCHEDULER INTERNALS AVAILABLE FOR PORTING PURPOSES *----------------------------------------------------------*/ +#if ( configNUMBER_OF_CORES == 1 ) + #define taskYIELD_WITHIN_API() portYIELD_WITHIN_API() +#else /* #if ( configNUMBER_OF_CORES == 1 ) */ + #define taskYIELD_WITHIN_API() vTaskYieldWithinAPI() +#endif /* #if ( configNUMBER_OF_CORES == 1 ) */ + /* * THIS FUNCTION MUST NOT BE USED FROM APPLICATION CODE. IT IS ONLY * INTENDED FOR USE WHEN IMPLEMENTING A PORT OF THE SCHEDULER AND IS @@ -3099,7 +3554,11 @@ void vTaskRemoveFromUnorderedEventList( ListItem_t * pxEventListItem, * Sets the pointer to the current TCB to the TCB of the highest priority task * that is ready to run. */ -portDONT_DISCARD void vTaskSwitchContext( void ) PRIVILEGED_FUNCTION; +#if ( configNUMBER_OF_CORES == 1 ) + portDONT_DISCARD void vTaskSwitchContext( void ) PRIVILEGED_FUNCTION; +#else + portDONT_DISCARD void vTaskSwitchContext( BaseType_t xCoreID ) PRIVILEGED_FUNCTION; +#endif /* * THESE FUNCTIONS MUST NOT BE USED FROM APPLICATION CODE. THEY ARE USED BY @@ -3112,6 +3571,13 @@ TickType_t uxTaskResetEventItemValue( void ) PRIVILEGED_FUNCTION; */ TaskHandle_t xTaskGetCurrentTaskHandle( void ) PRIVILEGED_FUNCTION; +/* + * Return the handle of the task running on specified core. + */ +#if ( configNUMBER_OF_CORES > 1 ) + TaskHandle_t xTaskGetCurrentTaskHandleForCore( BaseType_t xCoreID ) PRIVILEGED_FUNCTION; +#endif + /* * Shortcut used by the queue implementation to prevent unnecessary call to * taskYIELD(); @@ -3150,14 +3616,18 @@ void vTaskPriorityDisinheritAfterTimeout( TaskHandle_t const pxMutexHolder, /* * Get the uxTaskNumber assigned to the task referenced by the xTask parameter. */ -UBaseType_t uxTaskGetTaskNumber( TaskHandle_t xTask ) PRIVILEGED_FUNCTION; +#if ( configUSE_TRACE_FACILITY == 1 ) + UBaseType_t uxTaskGetTaskNumber( TaskHandle_t xTask ) PRIVILEGED_FUNCTION; +#endif /* * Set the uxTaskNumber of the task referenced by the xTask parameter to * uxHandle. */ -void vTaskSetTaskNumber( TaskHandle_t xTask, - const UBaseType_t uxHandle ) PRIVILEGED_FUNCTION; +#if ( configUSE_TRACE_FACILITY == 1 ) + void vTaskSetTaskNumber( TaskHandle_t xTask, + const UBaseType_t uxHandle ) PRIVILEGED_FUNCTION; +#endif /* * Only available when configUSE_TICKLESS_IDLE is set to 1. @@ -3167,7 +3637,9 @@ void vTaskSetTaskNumber( TaskHandle_t xTask, * to date with the actual execution time by being skipped forward by a time * equal to the idle period. */ -void vTaskStepTick( TickType_t xTicksToJump ) PRIVILEGED_FUNCTION; +#if ( configUSE_TICKLESS_IDLE != 0 ) + void vTaskStepTick( TickType_t xTicksToJump ) PRIVILEGED_FUNCTION; +#endif /* * Only available when configUSE_TICKLESS_IDLE is set to 1. @@ -3183,7 +3655,9 @@ void vTaskStepTick( TickType_t xTicksToJump ) PRIVILEGED_FUNCTION; * critical section between the timer being stopped and the sleep mode being * entered to ensure it is ok to proceed into the sleep mode. */ -eSleepModeStatus eTaskConfirmSleepModeStatus( void ) PRIVILEGED_FUNCTION; +#if ( configUSE_TICKLESS_IDLE != 0 ) + eSleepModeStatus eTaskConfirmSleepModeStatus( void ) PRIVILEGED_FUNCTION; +#endif /* * For internal use only. Increment the mutex held count when a mutex is @@ -3197,6 +3671,58 @@ TaskHandle_t pvTaskIncrementMutexHeldCount( void ) PRIVILEGED_FUNCTION; */ void vTaskInternalSetTimeOutState( TimeOut_t * const pxTimeOut ) PRIVILEGED_FUNCTION; +/* + * For internal use only. Same as portYIELD_WITHIN_API() in single core FreeRTOS. + * For SMP this is not defined by the port. + */ +#if ( configNUMBER_OF_CORES > 1 ) + void vTaskYieldWithinAPI( void ); +#endif + +/* + * This function is only intended for use when implementing a port of the scheduler + * and is only available when portCRITICAL_NESTING_IN_TCB is set to 1 or configNUMBER_OF_CORES + * is greater than 1. This function can be used in the implementation of portENTER_CRITICAL + * if port wants to maintain critical nesting count in TCB in single core FreeRTOS. + * It should be used in the implementation of portENTER_CRITICAL if port is running a + * multiple core FreeRTOS. + */ +#if ( ( portCRITICAL_NESTING_IN_TCB == 1 ) || ( configNUMBER_OF_CORES > 1 ) ) + void vTaskEnterCritical( void ); +#endif + +/* + * This function is only intended for use when implementing a port of the scheduler + * and is only available when portCRITICAL_NESTING_IN_TCB is set to 1 or configNUMBER_OF_CORES + * is greater than 1. This function can be used in the implementation of portEXIT_CRITICAL + * if port wants to maintain critical nesting count in TCB in single core FreeRTOS. + * It should be used in the implementation of portEXIT_CRITICAL if port is running a + * multiple core FreeRTOS. + */ +#if ( ( portCRITICAL_NESTING_IN_TCB == 1 ) || ( configNUMBER_OF_CORES > 1 ) ) + void vTaskExitCritical( void ); +#endif + +/* + * This function is only intended for use when implementing a port of the scheduler + * and is only available when configNUMBER_OF_CORES is greater than 1. This function + * should be used in the implementation of portENTER_CRITICAL_FROM_ISR if port is + * running a multiple core FreeRTOS. + */ +#if ( configNUMBER_OF_CORES > 1 ) + UBaseType_t vTaskEnterCriticalFromISR( void ); +#endif + +/* + * This function is only intended for use when implementing a port of the scheduler + * and is only available when configNUMBER_OF_CORES is greater than 1. This function + * should be used in the implementation of portEXIT_CRITICAL_FROM_ISR if port is + * running a multiple core FreeRTOS. + */ +#if ( configNUMBER_OF_CORES > 1 ) + void vTaskExitCriticalFromISR( UBaseType_t uxSavedInterruptStatus ); +#endif + #if ( portUSING_MPU_WRAPPERS == 1 ) /* diff --git a/Source/include/timers.h b/Source/include/timers.h index 0900edb2a..5a23ea196 100644 --- a/Source/include/timers.h +++ b/Source/include/timers.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -34,10 +34,8 @@ #error "include FreeRTOS.h must appear in source files before include timers.h" #endif -/*lint -save -e537 This headers are only multiply included if the application code - * happens to also be including task.h. */ #include "task.h" -/*lint -restore */ + /* *INDENT-OFF* */ #ifdef __cplusplus @@ -88,8 +86,8 @@ typedef void (* TimerCallbackFunction_t)( TimerHandle_t xTimer ); * Defines the prototype to which functions used with the * xTimerPendFunctionCallFromISR() function must conform. */ -typedef void (* PendedFunction_t)( void *, - uint32_t ); +typedef void (* PendedFunction_t)( void * arg1, + uint32_t arg2 ); /** * TimerHandle_t xTimerCreate( const char * const pcTimerName, @@ -229,7 +227,7 @@ typedef void (* PendedFunction_t)( void *, * @endverbatim */ #if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) - TimerHandle_t xTimerCreate( const char * const pcTimerName, /*lint !e971 Unqualified char types are allowed for strings and single characters only. */ + TimerHandle_t xTimerCreate( const char * const pcTimerName, const TickType_t xTimerPeriodInTicks, const BaseType_t xAutoReload, void * const pvTimerID, @@ -359,7 +357,7 @@ typedef void (* PendedFunction_t)( void *, * @endverbatim */ #if ( configSUPPORT_STATIC_ALLOCATION == 1 ) - TimerHandle_t xTimerCreateStatic( const char * const pcTimerName, /*lint !e971 Unqualified char types are allowed for strings and single characters only. */ + TimerHandle_t xTimerCreateStatic( const char * const pcTimerName, const TickType_t xTimerPeriodInTicks, const BaseType_t xAutoReload, void * const pvTimerID, @@ -1198,10 +1196,12 @@ TaskHandle_t xTimerGetTimerDaemonTaskHandle( void ) PRIVILEGED_FUNCTION; * } * @endverbatim */ -BaseType_t xTimerPendFunctionCallFromISR( PendedFunction_t xFunctionToPend, - void * pvParameter1, - uint32_t ulParameter2, - BaseType_t * pxHigherPriorityTaskWoken ) PRIVILEGED_FUNCTION; +#if ( INCLUDE_xTimerPendFunctionCall == 1 ) + BaseType_t xTimerPendFunctionCallFromISR( PendedFunction_t xFunctionToPend, + void * pvParameter1, + uint32_t ulParameter2, + BaseType_t * pxHigherPriorityTaskWoken ) PRIVILEGED_FUNCTION; +#endif /** * BaseType_t xTimerPendFunctionCall( PendedFunction_t xFunctionToPend, @@ -1235,10 +1235,12 @@ BaseType_t xTimerPendFunctionCallFromISR( PendedFunction_t xFunctionToPend, * timer daemon task, otherwise pdFALSE is returned. * */ -BaseType_t xTimerPendFunctionCall( PendedFunction_t xFunctionToPend, - void * pvParameter1, - uint32_t ulParameter2, - TickType_t xTicksToWait ) PRIVILEGED_FUNCTION; +#if ( INCLUDE_xTimerPendFunctionCall == 1 ) + BaseType_t xTimerPendFunctionCall( PendedFunction_t xFunctionToPend, + void * pvParameter1, + uint32_t ulParameter2, + TickType_t xTicksToWait ) PRIVILEGED_FUNCTION; +#endif /** * const char * const pcTimerGetName( TimerHandle_t xTimer ); @@ -1249,7 +1251,7 @@ BaseType_t xTimerPendFunctionCall( PendedFunction_t xFunctionToPend, * * @return The name assigned to the timer specified by the xTimer parameter. */ -const char * pcTimerGetName( TimerHandle_t xTimer ) PRIVILEGED_FUNCTION; /*lint !e971 Unqualified char types are allowed for strings and single characters only. */ +const char * pcTimerGetName( TimerHandle_t xTimer ) PRIVILEGED_FUNCTION; /** * void vTimerSetReloadMode( TimerHandle_t xTimer, const BaseType_t xAutoReload ); @@ -1348,12 +1350,29 @@ TickType_t xTimerGetExpiryTime( TimerHandle_t xTimer ) PRIVILEGED_FUNCTION; * for use by the kernel only. */ BaseType_t xTimerCreateTimerTask( void ) PRIVILEGED_FUNCTION; -BaseType_t xTimerGenericCommand( TimerHandle_t xTimer, - const BaseType_t xCommandID, - const TickType_t xOptionalValue, - BaseType_t * const pxHigherPriorityTaskWoken, - const TickType_t xTicksToWait ) PRIVILEGED_FUNCTION; +/* + * Splitting the xTimerGenericCommand into two sub functions and making it a macro + * removes a recursion path when called from ISRs. This is primarily for the XCore + * XCC port which detects the recursion path and throws an error during compilation + * when this is not split. + */ +BaseType_t xTimerGenericCommandFromTask( TimerHandle_t xTimer, + const BaseType_t xCommandID, + const TickType_t xOptionalValue, + BaseType_t * const pxHigherPriorityTaskWoken, + const TickType_t xTicksToWait ) PRIVILEGED_FUNCTION; + +BaseType_t xTimerGenericCommandFromISR( TimerHandle_t xTimer, + const BaseType_t xCommandID, + const TickType_t xOptionalValue, + BaseType_t * const pxHigherPriorityTaskWoken, + const TickType_t xTicksToWait ) PRIVILEGED_FUNCTION; + +#define xTimerGenericCommand( xTimer, xCommandID, xOptionalValue, pxHigherPriorityTaskWoken, xTicksToWait ) \ + ( ( xCommandID ) < tmrFIRST_FROM_ISR_COMMAND ? \ + xTimerGenericCommandFromTask( xTimer, xCommandID, xOptionalValue, pxHigherPriorityTaskWoken, xTicksToWait ) : \ + xTimerGenericCommandFromISR( xTimer, xCommandID, xOptionalValue, pxHigherPriorityTaskWoken, xTicksToWait ) ) #if ( configUSE_TRACE_FACILITY == 1 ) void vTimerSetTimerNumber( TimerHandle_t xTimer, UBaseType_t uxTimerNumber ) PRIVILEGED_FUNCTION; @@ -1391,6 +1410,9 @@ BaseType_t xTimerGenericCommand( TimerHandle_t xTimer, * * This hook function is called form the timer task once when the task starts running. */ + /* MISRA Ref 8.6.1 [External linkage] */ + /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-86 */ + /* coverity[misra_c_2012_rule_8_6_violation] */ void vApplicationDaemonTaskStartupHook( void ); #endif diff --git a/Source/list.c b/Source/list.c index 6129affbe..d500aad0c 100644 --- a/Source/list.c +++ b/Source/list.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -37,11 +37,10 @@ #include "FreeRTOS.h" #include "list.h" -/* Lint e9021, e961 and e750 are suppressed as a MISRA exception justified - * because the MPU ports require MPU_WRAPPERS_INCLUDED_FROM_API_FILE to be +/* The MPU ports require MPU_WRAPPERS_INCLUDED_FROM_API_FILE to be * defined for the header files above, but not in this file, in order to * generate the correct privileged Vs unprivileged linkage and placement. */ -#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE /*lint !e961 !e750 !e9021. */ +#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE /*----------------------------------------------------------- * PUBLIC LIST API documented in list.h @@ -49,10 +48,12 @@ void vListInitialise( List_t * const pxList ) { + traceENTER_vListInitialise( pxList ); + /* The list structure contains a list item which is used to mark the * end of the list. To initialise the list the list end is inserted * as the only list entry. */ - pxList->pxIndex = ( ListItem_t * ) &( pxList->xListEnd ); /*lint !e826 !e740 !e9087 The mini list structure is used as the list end to save RAM. This is checked and valid. */ + pxList->pxIndex = ( ListItem_t * ) &( pxList->xListEnd ); listSET_FIRST_LIST_ITEM_INTEGRITY_CHECK_VALUE( &( pxList->xListEnd ) ); @@ -62,8 +63,8 @@ void vListInitialise( List_t * const pxList ) /* The list end next and previous pointers point to itself so we know * when the list is empty. */ - pxList->xListEnd.pxNext = ( ListItem_t * ) &( pxList->xListEnd ); /*lint !e826 !e740 !e9087 The mini list structure is used as the list end to save RAM. This is checked and valid. */ - pxList->xListEnd.pxPrevious = ( ListItem_t * ) &( pxList->xListEnd ); /*lint !e826 !e740 !e9087 The mini list structure is used as the list end to save RAM. This is checked and valid. */ + pxList->xListEnd.pxNext = ( ListItem_t * ) &( pxList->xListEnd ); + pxList->xListEnd.pxPrevious = ( ListItem_t * ) &( pxList->xListEnd ); /* Initialize the remaining fields of xListEnd when it is a proper ListItem_t */ #if ( configUSE_MINI_LIST_ITEM == 0 ) @@ -80,11 +81,15 @@ void vListInitialise( List_t * const pxList ) * configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES is set to 1. */ listSET_LIST_INTEGRITY_CHECK_1_VALUE( pxList ); listSET_LIST_INTEGRITY_CHECK_2_VALUE( pxList ); + + traceRETURN_vListInitialise(); } /*-----------------------------------------------------------*/ void vListInitialiseItem( ListItem_t * const pxItem ) { + traceENTER_vListInitialiseItem( pxItem ); + /* Make sure the list item is not recorded as being on a list. */ pxItem->pxContainer = NULL; @@ -92,6 +97,8 @@ void vListInitialiseItem( ListItem_t * const pxItem ) * configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES is set to 1. */ listSET_FIRST_LIST_ITEM_INTEGRITY_CHECK_VALUE( pxItem ); listSET_SECOND_LIST_ITEM_INTEGRITY_CHECK_VALUE( pxItem ); + + traceRETURN_vListInitialiseItem(); } /*-----------------------------------------------------------*/ @@ -100,6 +107,8 @@ void vListInsertEnd( List_t * const pxList, { ListItem_t * const pxIndex = pxList->pxIndex; + traceENTER_vListInsertEnd( pxList, pxNewListItem ); + /* Only effective when configASSERT() is also defined, these tests may catch * the list data structures being overwritten in memory. They will not catch * data errors caused by incorrect configuration or use of FreeRTOS. */ @@ -122,6 +131,8 @@ void vListInsertEnd( List_t * const pxList, pxNewListItem->pxContainer = pxList; ( pxList->uxNumberOfItems )++; + + traceRETURN_vListInsertEnd(); } /*-----------------------------------------------------------*/ @@ -131,6 +142,8 @@ void vListInsert( List_t * const pxList, ListItem_t * pxIterator; const TickType_t xValueOfInsertion = pxNewListItem->xItemValue; + traceENTER_vListInsert( pxList, pxNewListItem ); + /* Only effective when configASSERT() is also defined, these tests may catch * the list data structures being overwritten in memory. They will not catch * data errors caused by incorrect configuration or use of FreeRTOS. */ @@ -176,7 +189,7 @@ void vListInsert( List_t * const pxList, * configMAX_SYSCALL_INTERRUPT_PRIORITY. **********************************************************************/ - for( pxIterator = ( ListItem_t * ) &( pxList->xListEnd ); pxIterator->pxNext->xItemValue <= xValueOfInsertion; pxIterator = pxIterator->pxNext ) /*lint !e826 !e740 !e9087 The mini list structure is used as the list end to save RAM. This is checked and valid. *//*lint !e440 The iterator moves to a different value, not xValueOfInsertion. */ + for( pxIterator = ( ListItem_t * ) &( pxList->xListEnd ); pxIterator->pxNext->xItemValue <= xValueOfInsertion; pxIterator = pxIterator->pxNext ) { /* There is nothing to do here, just iterating to the wanted * insertion position. */ @@ -193,15 +206,21 @@ void vListInsert( List_t * const pxList, pxNewListItem->pxContainer = pxList; ( pxList->uxNumberOfItems )++; + + traceRETURN_vListInsert(); } /*-----------------------------------------------------------*/ UBaseType_t uxListRemove( ListItem_t * const pxItemToRemove ) { -/* The list item knows which list it is in. Obtain the list from the list - * item. */ + /* The list item knows which list it is in. Obtain the list from the list + * item. */ List_t * const pxList = pxItemToRemove->pxContainer; + traceENTER_uxListRemove( pxItemToRemove ); + + + pxItemToRemove->pxNext->pxPrevious = pxItemToRemove->pxPrevious; pxItemToRemove->pxPrevious->pxNext = pxItemToRemove->pxNext; @@ -221,6 +240,8 @@ UBaseType_t uxListRemove( ListItem_t * const pxItemToRemove ) pxItemToRemove->pxContainer = NULL; ( pxList->uxNumberOfItems )--; + traceRETURN_uxListRemove( pxList->uxNumberOfItems ); + return pxList->uxNumberOfItems; } /*-----------------------------------------------------------*/ diff --git a/Source/manifest.yml b/Source/manifest.yml index 437a9be16..5e022748b 100644 --- a/Source/manifest.yml +++ b/Source/manifest.yml @@ -1,4 +1,4 @@ name : "FreeRTOS-Kernel" -version: "v10.6.2" +version: "v11.0.1" description: "FreeRTOS Kernel." license: "MIT" diff --git a/Source/portable/ARMv8M/ReadMe.txt b/Source/portable/ARMv8M/ReadMe.txt index 3f864bb03..c6dbe7709 100644 --- a/Source/portable/ARMv8M/ReadMe.txt +++ b/Source/portable/ARMv8M/ReadMe.txt @@ -1,4 +1,4 @@ -This directory tree contains the master copy of the FreeeRTOS Armv8-M and +This directory tree contains the master copy of the FreeRTOS Armv8-M and Armv8.1-M ports. Do not use the files located here! These file are copied into separate FreeRTOS/Source/portable/[compiler]/ARM_CM[23|33|55|85]_NNN directories prior to each diff --git a/Source/portable/ARMv8M/copy_files.py b/Source/portable/ARMv8M/copy_files.py index c48a0c692..6e679206b 100644 --- a/Source/portable/ARMv8M/copy_files.py +++ b/Source/portable/ARMv8M/copy_files.py @@ -1,5 +1,5 @@ #/* -# * FreeRTOS Kernel V10.6.2 +# * FreeRTOS Kernel V11.0.1 # * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. # * # * SPDX-License-Identifier: MIT diff --git a/Source/portable/ARMv8M/non_secure/port.c b/Source/portable/ARMv8M/non_secure/port.c index 9712ac353..230fe5fc2 100644 --- a/Source/portable/ARMv8M/non_secure/port.c +++ b/Source/portable/ARMv8M/non_secure/port.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -68,6 +68,22 @@ #if ( ( configRUN_FREERTOS_SECURE_ONLY == 1 ) && ( configENABLE_TRUSTZONE == 1 ) ) #error TrustZone needs to be disabled in order to run FreeRTOS on the Secure Side. #endif + +/** + * Cortex-M23 does not have non-secure PSPLIM. We should use PSPLIM on Cortex-M23 + * only when FreeRTOS runs on secure side. + */ +#if ( ( portHAS_ARMV8M_MAIN_EXTENSION == 0 ) && ( configRUN_FREERTOS_SECURE_ONLY == 0 ) ) + #define portUSE_PSPLIM_REGISTER 0 +#else + #define portUSE_PSPLIM_REGISTER 1 +#endif +/*-----------------------------------------------------------*/ + +/** + * @brief Prototype of all Interrupt Service Routines (ISRs). + */ +typedef void ( * portISR_t )( void ); /*-----------------------------------------------------------*/ /** @@ -91,10 +107,18 @@ /** * @brief Constants required to manipulate the SCB. */ -#define portSCB_SYS_HANDLER_CTRL_STATE_REG ( *( volatile uint32_t * ) 0xe000ed24 ) +#define portSCB_VTOR_REG ( *( ( portISR_t ** ) 0xe000ed08 ) ) +#define portSCB_SYS_HANDLER_CTRL_STATE_REG ( *( ( volatile uint32_t * ) 0xe000ed24 ) ) #define portSCB_MEM_FAULT_ENABLE_BIT ( 1UL << 16UL ) /*-----------------------------------------------------------*/ +/** + * @brief Constants used to check the installation of the FreeRTOS interrupt handlers. + */ +#define portVECTOR_INDEX_SVC ( 11 ) +#define portVECTOR_INDEX_PENDSV ( 14 ) +/*-----------------------------------------------------------*/ + /** * @brief Constants required to check the validity of an interrupt priority. */ @@ -111,8 +135,8 @@ /** * @brief Constants used during system call enter and exit. */ -#define portPSR_STACK_PADDING_MASK ( 1UL << 9UL ) -#define portEXC_RETURN_STACK_FRAME_TYPE_MASK ( 1UL << 4UL ) +#define portPSR_STACK_PADDING_MASK ( 1UL << 9UL ) +#define portEXC_RETURN_STACK_FRAME_TYPE_MASK ( 1UL << 4UL ) /*-----------------------------------------------------------*/ /** @@ -134,81 +158,81 @@ /** * @brief Offsets in the stack to the parameters when inside the SVC handler. */ -#define portOFFSET_TO_LR ( 5 ) -#define portOFFSET_TO_PC ( 6 ) -#define portOFFSET_TO_PSR ( 7 ) +#define portOFFSET_TO_LR ( 5 ) +#define portOFFSET_TO_PC ( 6 ) +#define portOFFSET_TO_PSR ( 7 ) /*-----------------------------------------------------------*/ /** * @brief Constants required to manipulate the MPU. */ -#define portMPU_TYPE_REG ( *( ( volatile uint32_t * ) 0xe000ed90 ) ) -#define portMPU_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed94 ) ) -#define portMPU_RNR_REG ( *( ( volatile uint32_t * ) 0xe000ed98 ) ) +#define portMPU_TYPE_REG ( *( ( volatile uint32_t * ) 0xe000ed90 ) ) +#define portMPU_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed94 ) ) +#define portMPU_RNR_REG ( *( ( volatile uint32_t * ) 0xe000ed98 ) ) -#define portMPU_RBAR_REG ( *( ( volatile uint32_t * ) 0xe000ed9c ) ) -#define portMPU_RLAR_REG ( *( ( volatile uint32_t * ) 0xe000eda0 ) ) +#define portMPU_RBAR_REG ( *( ( volatile uint32_t * ) 0xe000ed9c ) ) +#define portMPU_RLAR_REG ( *( ( volatile uint32_t * ) 0xe000eda0 ) ) -#define portMPU_RBAR_A1_REG ( *( ( volatile uint32_t * ) 0xe000eda4 ) ) -#define portMPU_RLAR_A1_REG ( *( ( volatile uint32_t * ) 0xe000eda8 ) ) +#define portMPU_RBAR_A1_REG ( *( ( volatile uint32_t * ) 0xe000eda4 ) ) +#define portMPU_RLAR_A1_REG ( *( ( volatile uint32_t * ) 0xe000eda8 ) ) -#define portMPU_RBAR_A2_REG ( *( ( volatile uint32_t * ) 0xe000edac ) ) -#define portMPU_RLAR_A2_REG ( *( ( volatile uint32_t * ) 0xe000edb0 ) ) +#define portMPU_RBAR_A2_REG ( *( ( volatile uint32_t * ) 0xe000edac ) ) +#define portMPU_RLAR_A2_REG ( *( ( volatile uint32_t * ) 0xe000edb0 ) ) -#define portMPU_RBAR_A3_REG ( *( ( volatile uint32_t * ) 0xe000edb4 ) ) -#define portMPU_RLAR_A3_REG ( *( ( volatile uint32_t * ) 0xe000edb8 ) ) +#define portMPU_RBAR_A3_REG ( *( ( volatile uint32_t * ) 0xe000edb4 ) ) +#define portMPU_RLAR_A3_REG ( *( ( volatile uint32_t * ) 0xe000edb8 ) ) -#define portMPU_MAIR0_REG ( *( ( volatile uint32_t * ) 0xe000edc0 ) ) -#define portMPU_MAIR1_REG ( *( ( volatile uint32_t * ) 0xe000edc4 ) ) +#define portMPU_MAIR0_REG ( *( ( volatile uint32_t * ) 0xe000edc0 ) ) +#define portMPU_MAIR1_REG ( *( ( volatile uint32_t * ) 0xe000edc4 ) ) -#define portMPU_RBAR_ADDRESS_MASK ( 0xffffffe0 ) /* Must be 32-byte aligned. */ -#define portMPU_RLAR_ADDRESS_MASK ( 0xffffffe0 ) /* Must be 32-byte aligned. */ +#define portMPU_RBAR_ADDRESS_MASK ( 0xffffffe0 ) /* Must be 32-byte aligned. */ +#define portMPU_RLAR_ADDRESS_MASK ( 0xffffffe0 ) /* Must be 32-byte aligned. */ -#define portMPU_RBAR_ACCESS_PERMISSIONS_MASK ( 3UL << 1UL ) +#define portMPU_RBAR_ACCESS_PERMISSIONS_MASK ( 3UL << 1UL ) -#define portMPU_MAIR_ATTR0_POS ( 0UL ) -#define portMPU_MAIR_ATTR0_MASK ( 0x000000ff ) +#define portMPU_MAIR_ATTR0_POS ( 0UL ) +#define portMPU_MAIR_ATTR0_MASK ( 0x000000ff ) -#define portMPU_MAIR_ATTR1_POS ( 8UL ) -#define portMPU_MAIR_ATTR1_MASK ( 0x0000ff00 ) +#define portMPU_MAIR_ATTR1_POS ( 8UL ) +#define portMPU_MAIR_ATTR1_MASK ( 0x0000ff00 ) -#define portMPU_MAIR_ATTR2_POS ( 16UL ) -#define portMPU_MAIR_ATTR2_MASK ( 0x00ff0000 ) +#define portMPU_MAIR_ATTR2_POS ( 16UL ) +#define portMPU_MAIR_ATTR2_MASK ( 0x00ff0000 ) -#define portMPU_MAIR_ATTR3_POS ( 24UL ) -#define portMPU_MAIR_ATTR3_MASK ( 0xff000000 ) +#define portMPU_MAIR_ATTR3_POS ( 24UL ) +#define portMPU_MAIR_ATTR3_MASK ( 0xff000000 ) -#define portMPU_MAIR_ATTR4_POS ( 0UL ) -#define portMPU_MAIR_ATTR4_MASK ( 0x000000ff ) +#define portMPU_MAIR_ATTR4_POS ( 0UL ) +#define portMPU_MAIR_ATTR4_MASK ( 0x000000ff ) -#define portMPU_MAIR_ATTR5_POS ( 8UL ) -#define portMPU_MAIR_ATTR5_MASK ( 0x0000ff00 ) +#define portMPU_MAIR_ATTR5_POS ( 8UL ) +#define portMPU_MAIR_ATTR5_MASK ( 0x0000ff00 ) -#define portMPU_MAIR_ATTR6_POS ( 16UL ) -#define portMPU_MAIR_ATTR6_MASK ( 0x00ff0000 ) +#define portMPU_MAIR_ATTR6_POS ( 16UL ) +#define portMPU_MAIR_ATTR6_MASK ( 0x00ff0000 ) -#define portMPU_MAIR_ATTR7_POS ( 24UL ) -#define portMPU_MAIR_ATTR7_MASK ( 0xff000000 ) +#define portMPU_MAIR_ATTR7_POS ( 24UL ) +#define portMPU_MAIR_ATTR7_MASK ( 0xff000000 ) -#define portMPU_RLAR_ATTR_INDEX0 ( 0UL << 1UL ) -#define portMPU_RLAR_ATTR_INDEX1 ( 1UL << 1UL ) -#define portMPU_RLAR_ATTR_INDEX2 ( 2UL << 1UL ) -#define portMPU_RLAR_ATTR_INDEX3 ( 3UL << 1UL ) -#define portMPU_RLAR_ATTR_INDEX4 ( 4UL << 1UL ) -#define portMPU_RLAR_ATTR_INDEX5 ( 5UL << 1UL ) -#define portMPU_RLAR_ATTR_INDEX6 ( 6UL << 1UL ) -#define portMPU_RLAR_ATTR_INDEX7 ( 7UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX0 ( 0UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX1 ( 1UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX2 ( 2UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX3 ( 3UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX4 ( 4UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX5 ( 5UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX6 ( 6UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX7 ( 7UL << 1UL ) -#define portMPU_RLAR_REGION_ENABLE ( 1UL ) +#define portMPU_RLAR_REGION_ENABLE ( 1UL ) /* Enable privileged access to unmapped region. */ -#define portMPU_PRIV_BACKGROUND_ENABLE_BIT ( 1UL << 2UL ) +#define portMPU_PRIV_BACKGROUND_ENABLE_BIT ( 1UL << 2UL ) /* Enable MPU. */ -#define portMPU_ENABLE_BIT ( 1UL << 0UL ) +#define portMPU_ENABLE_BIT ( 1UL << 0UL ) /* Expected value of the portMPU_TYPE register. */ -#define portEXPECTED_MPU_TYPE_VALUE ( configTOTAL_MPU_REGIONS << 8UL ) +#define portEXPECTED_MPU_TYPE_VALUE ( configTOTAL_MPU_REGIONS << 8UL ) /* Extract first address of the MPU region as encoded in the * RBAR (Region Base Address Register) value. */ @@ -448,13 +472,13 @@ portDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIV #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) - /** - * @brief Sets up the task stack so that upon returning from - * SVC, the task stack is used again. - * - * @param pulSystemCallStack The current SP when the SVC was raised. - * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler. - */ +/** + * @brief Sets up the task stack so that upon returning from + * SVC, the task stack is used again. + * + * @param pulSystemCallStack The current SP when the SVC was raised. + * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler. + */ void vSystemCallExit( uint32_t * pulSystemCallStack, uint32_t ulLR ) PRIVILEGED_FUNCTION; @@ -462,11 +486,11 @@ portDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIV #if ( configENABLE_MPU == 1 ) - /** - * @brief Checks whether or not the calling task is privileged. - * - * @return pdTRUE if the calling task is privileged, pdFALSE otherwise. - */ +/** + * @brief Checks whether or not the calling task is privileged. + * + * @return pdTRUE if the calling task is privileged, pdFALSE otherwise. + */ BaseType_t xPortIsTaskPrivileged( void ) PRIVILEGED_FUNCTION; #endif /* configENABLE_MPU == 1 */ @@ -501,13 +525,13 @@ PRIVILEGED_DATA static volatile uint32_t ulCriticalNesting = 0xaaaaaaaaUL; * FreeRTOS API functions are not called from interrupts that have been assigned * a priority above configMAX_SYSCALL_INTERRUPT_PRIORITY. */ -#if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) ) +#if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) static uint8_t ucMaxSysCallPriority = 0; static uint32_t ulMaxPRIGROUPValue = 0; static const volatile uint8_t * const pcInterruptPriorityRegisters = ( const volatile uint8_t * ) portNVIC_IP_REGISTERS_OFFSET_16; -#endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) ) */ +#endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */ #if ( configUSE_TICKLESS_IDLE == 1 ) @@ -760,8 +784,15 @@ __attribute__( ( weak ) ) void vPortSetupTimerInterrupt( void ) /* PRIVILEGED_FU } #endif /* configUSE_TICKLESS_IDLE */ - /* Stop and reset the SysTick. */ - portNVIC_SYSTICK_CTRL_REG = 0UL; + /* Stop and reset SysTick. + * + * QEMU versions older than 7.0.0 contain a bug which causes an error if we + * enable SysTick without first selecting a valid clock source. We trigger + * the bug if we change clock sources from a clock with a zero clock period + * to one with a nonzero clock period and enable Systick at the same time. + * So we configure the CLKSOURCE bit here, prior to setting the ENABLE bit. + * This workaround avoids the bug in QEMU versions older than 7.0.0. */ + portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT_CONFIG; portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL; /* Configure SysTick to interrupt at the requested rate. */ @@ -819,6 +850,7 @@ static void prvTaskExitError( void ) static void prvSetupMPU( void ) /* PRIVILEGED_FUNCTION */ { #if defined( __ARMCC_VERSION ) + /* Declaration when these variable are defined in code instead of being * exported from linker scripts. */ extern uint32_t * __privileged_functions_start__; @@ -972,13 +1004,19 @@ void SysTick_Handler( void ) /* PRIVILEGED_FUNCTION */ uint32_t ulPreviousMask; ulPreviousMask = portSET_INTERRUPT_MASK_FROM_ISR(); + traceISR_ENTER(); { /* Increment the RTOS tick. */ if( xTaskIncrementTick() != pdFALSE ) { + traceISR_EXIT_TO_SCHEDULER(); /* Pend a context switch. */ portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; } + else + { + traceISR_EXIT(); + } } portCLEAR_INTERRUPT_MASK_FROM_ISR( ulPreviousMask ); } @@ -988,6 +1026,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO { #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) ) #if defined( __ARMCC_VERSION ) + /* Declaration when these variable are defined in code instead of being * exported from linker scripts. */ extern uint32_t * __syscalls_flash_start__; @@ -1083,18 +1122,24 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO vRestoreContextOfFirstTask(); break; - #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) ) - case portSVC_RAISE_PRIVILEGE: + #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) ) + case portSVC_RAISE_PRIVILEGE: - /* Only raise the privilege, if the svc was raised from any of - * the system calls. */ - if( ( ulPC >= ( uint32_t ) __syscalls_flash_start__ ) && - ( ulPC <= ( uint32_t ) __syscalls_flash_end__ ) ) - { - vRaisePrivilege(); - } - break; - #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) */ + /* Only raise the privilege, if the svc was raised from any of + * the system calls. */ + if( ( ulPC >= ( uint32_t ) __syscalls_flash_start__ ) && + ( ulPC <= ( uint32_t ) __syscalls_flash_end__ ) ) + { + vRaisePrivilege(); + } + break; + #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) */ + + #if ( configENABLE_MPU == 1 ) + case portSVC_YIELD: + vPortYield(); + break; + #endif /* configENABLE_MPU == 1 */ default: /* Incorrect SVC call. */ @@ -1154,12 +1199,11 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO { /* Extended frame i.e. FPU in use. */ ulStackFrameSize = 26; - __asm volatile - ( + __asm volatile ( " vpush {s0} \n" /* Trigger lazy stacking. */ " vpop {s0} \n" /* Nullify the affect of the above instruction. */ ::: "memory" - ); + ); } else { @@ -1171,7 +1215,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO { ulStackFrameSize = 8; } - #endif /* if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */ + #endif /* configENABLE_FPU || configENABLE_MVE */ /* Make space on the system call stack for the stack frame. */ pulSystemCallStack = pulSystemCallStack - ulStackFrameSize; @@ -1187,18 +1231,24 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO * point (i.e. the caller of the MPU_). We need to restore it * when we exit from the system call. */ pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry = pulTaskStack[ portOFFSET_TO_LR ]; - /* Store the value of the PSPLIM register before the SVC was raised. * We need to restore it when we exit from the system call. */ - __asm volatile ( "mrs %0, psplim" : "=r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) ); + #if ( portUSE_PSPLIM_REGISTER == 1 ) + { + __asm volatile ( "mrs %0, psplim" : "=r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) ); + } + #endif /* Use the pulSystemCallStack in thread mode. */ __asm volatile ( "msr psp, %0" : : "r" ( pulSystemCallStack ) ); - __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) ); + #if ( portUSE_PSPLIM_REGISTER == 1 ) + { + __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) ); + } + #endif /* Start executing the system call upon returning from this handler. */ pulSystemCallStack[ portOFFSET_TO_PC ] = uxSystemCallImplementations[ ucSystemCallNumber ]; - /* Raise a request to exit from the system call upon finishing the * system call. */ pulSystemCallStack[ portOFFSET_TO_LR ] = ( uint32_t ) vRequestSystemCallExit; @@ -1224,14 +1274,13 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO pulSystemCallStack[ portOFFSET_TO_PSR ] &= ( ~portPSR_STACK_PADDING_MASK ); /* Raise the privilege for the duration of the system call. */ - __asm volatile - ( + __asm volatile ( " mrs r0, control \n" /* Obtain current control value. */ " movs r1, #1 \n" /* r1 = 1. */ " bics r0, r1 \n" /* Clear nPRIV bit. */ " msr control, r0 \n" /* Write back new control value. */ ::: "r0", "r1", "memory" - ); + ); } } @@ -1293,12 +1342,11 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO { /* Extended frame i.e. FPU in use. */ ulStackFrameSize = 26; - __asm volatile - ( + __asm volatile ( " vpush {s0} \n" /* Trigger lazy stacking. */ " vpop {s0} \n" /* Nullify the affect of the above instruction. */ ::: "memory" - ); + ); } else { @@ -1310,7 +1358,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO { ulStackFrameSize = 8; } - #endif /* if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */ + #endif /* configENABLE_FPU || configENABLE_MVE */ /* Make space on the task stack for the stack frame. */ pulTaskStack = pulTaskStack - ulStackFrameSize; @@ -1332,7 +1380,11 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO /* Restore the PSPLIM register to what it was at the time of * system call entry. */ - __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) ); + #if ( portUSE_PSPLIM_REGISTER == 1 ) + { + __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) ); + } + #endif /* If the hardware used padding to force the stack pointer * to be double word aligned, set the stacked xPSR bit[9], @@ -1350,14 +1402,13 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO pxMpuSettings->xSystemCallStackInfo.pulTaskStack = NULL; /* Drop the privilege before returning to the thread mode. */ - __asm volatile - ( + __asm volatile ( " mrs r0, control \n" /* Obtain current control value. */ " movs r1, #1 \n" /* r1 = 1. */ " orrs r0, r1 \n" /* Set nPRIV bit. */ " msr control, r0 \n" /* Write back new control value. */ ::: "r0", "r1", "memory" - ); + ); } } @@ -1410,21 +1461,21 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO xMPUSettings->ulContext[ ulIndex ] = 0x11111111; /* r11. */ ulIndex++; - xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pvParameters; /* r0. */ + xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pvParameters; /* r0. */ ulIndex++; - xMPUSettings->ulContext[ ulIndex ] = 0x01010101; /* r1. */ + xMPUSettings->ulContext[ ulIndex ] = 0x01010101; /* r1. */ ulIndex++; - xMPUSettings->ulContext[ ulIndex ] = 0x02020202; /* r2. */ + xMPUSettings->ulContext[ ulIndex ] = 0x02020202; /* r2. */ ulIndex++; - xMPUSettings->ulContext[ ulIndex ] = 0x03030303; /* r3. */ + xMPUSettings->ulContext[ ulIndex ] = 0x03030303; /* r3. */ ulIndex++; - xMPUSettings->ulContext[ ulIndex ] = 0x12121212; /* r12. */ + xMPUSettings->ulContext[ ulIndex ] = 0x12121212; /* r12. */ ulIndex++; xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portTASK_RETURN_ADDRESS; /* LR. */ ulIndex++; - xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxCode; /* PC. */ + xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxCode; /* PC. */ ulIndex++; - xMPUSettings->ulContext[ ulIndex ] = portINITIAL_XPSR; /* xPSR. */ + xMPUSettings->ulContext[ ulIndex ] = portINITIAL_XPSR; /* xPSR. */ ulIndex++; #if ( configENABLE_TRUSTZONE == 1 ) @@ -1435,8 +1486,9 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO #endif /* configENABLE_TRUSTZONE */ xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) ( pxTopOfStack - 8 ); /* PSP with the hardware saved stack. */ ulIndex++; - xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxEndOfStack; /* PSPLIM. */ + xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxEndOfStack; /* PSPLIM. */ ulIndex++; + if( xRunPrivileged == pdTRUE ) { xMPUSettings->ulTaskFlags |= portTASK_IS_PRIVILEGED_FLAG; @@ -1449,6 +1501,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portINITIAL_CONTROL_UNPRIVILEGED; /* CONTROL. */ ulIndex++; } + xMPUSettings->ulContext[ ulIndex ] = portINITIAL_EXC_RETURN; /* LR (EXC_RETURN). */ ulIndex++; @@ -1483,7 +1536,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO * interrupt. */ #if ( portPRELOAD_REGISTERS == 0 ) { - pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */ + pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */ *pxTopOfStack = portINITIAL_XPSR; /* xPSR. */ pxTopOfStack--; *pxTopOfStack = ( StackType_t ) pxCode; /* PC. */ @@ -1505,7 +1558,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO } #else /* portPRELOAD_REGISTERS */ { - pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */ + pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */ *pxTopOfStack = portINITIAL_XPSR; /* xPSR. */ pxTopOfStack--; *pxTopOfStack = ( StackType_t ) pxCode; /* PC. */ @@ -1540,7 +1593,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO pxTopOfStack--; *pxTopOfStack = portINITIAL_EXC_RETURN; /* EXC_RETURN. */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */ + *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */ #if ( configENABLE_TRUSTZONE == 1 ) { @@ -1559,22 +1612,52 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */ { - #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) ) + /* An application can install FreeRTOS interrupt handlers in one of the + * folllowing ways: + * 1. Direct Routing - Install the functions SVC_Handler and PendSV_Handler + * for SVCall and PendSV interrupts respectively. + * 2. Indirect Routing - Install separate handlers for SVCall and PendSV + * interrupts and route program control from those handlers to + * SVC_Handler and PendSV_Handler functions. + * + * Applications that use Indirect Routing must set + * configCHECK_HANDLER_INSTALLATION to 0 in their FreeRTOSConfig.h. Direct + * routing, which is validated here when configCHECK_HANDLER_INSTALLATION + * is 1, should be preferred when possible. */ + #if ( configCHECK_HANDLER_INSTALLATION == 1 ) + { + const portISR_t * const pxVectorTable = portSCB_VTOR_REG; + + /* Validate that the application has correctly installed the FreeRTOS + * handlers for SVCall and PendSV interrupts. We do not check the + * installation of the SysTick handler because the application may + * choose to drive the RTOS tick using a timer other than the SysTick + * timer by overriding the weak function vPortSetupTimerInterrupt(). + * + * Assertion failures here indicate incorrect installation of the + * FreeRTOS handlers. For help installing the FreeRTOS handlers, see + * https://www.FreeRTOS.org/FAQHelp.html. + * + * Systems with a configurable address for the interrupt vector table + * can also encounter assertion failures or even system faults here if + * VTOR is not set correctly to point to the application's vector table. */ + configASSERT( pxVectorTable[ portVECTOR_INDEX_SVC ] == SVC_Handler ); + configASSERT( pxVectorTable[ portVECTOR_INDEX_PENDSV ] == PendSV_Handler ); + } + #endif /* configCHECK_HANDLER_INSTALLATION */ + + #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) { - volatile uint32_t ulOriginalPriority; volatile uint32_t ulImplementedPrioBits = 0; volatile uint8_t ucMaxPriorityValue; /* Determine the maximum priority from which ISR safe FreeRTOS API - * functions can be called. ISR safe functions are those that end in - * "FromISR". FreeRTOS maintains separate thread and ISR API functions to + * functions can be called. ISR safe functions are those that end in + * "FromISR". FreeRTOS maintains separate thread and ISR API functions to * ensure interrupt entry is as fast and simple as possible. * - * Save the interrupt priority value that is about to be clobbered. */ - ulOriginalPriority = portNVIC_SHPR2_REG; - - /* Determine the number of priority bits available. First write to all - * possible bits. */ + * First, determine the number of priority bits available. Write to all + * possible bits in the priority setting for SVCall. */ portNVIC_SHPR2_REG = 0xFF000000; /* Read the value back to see how many bits stuck. */ @@ -1593,11 +1676,10 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */ /* Check that the bits not implemented in hardware are zero in * configMAX_SYSCALL_INTERRUPT_PRIORITY. */ - configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( ~ucMaxPriorityValue ) ) == 0U ); + configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( uint8_t ) ( ~( uint32_t ) ucMaxPriorityValue ) ) == 0U ); /* Calculate the maximum acceptable priority group value for the number * of bits read back. */ - while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE ) { ulImplementedPrioBits++; @@ -1635,16 +1717,14 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */ * register. */ ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT; ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK; - - /* Restore the clobbered interrupt priority register to its original - * value. */ - portNVIC_SHPR2_REG = ulOriginalPriority; } - #endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) ) */ + #endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */ - /* Make PendSV, CallSV and SysTick the same priority as the kernel. */ + /* Make PendSV and SysTick the lowest priority interrupts, and make SVCall + * the highest priority. */ portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI; portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI; + portNVIC_SHPR2_REG = 0; #if ( configENABLE_MPU == 1 ) { @@ -1701,6 +1781,7 @@ void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */ int32_t lIndex = 0; #if defined( __ARMCC_VERSION ) + /* Declaration when these variable are defined in code instead of being * exported from linker scripts. */ extern uint32_t * __privileged_sram_start__; @@ -1886,7 +1967,7 @@ BaseType_t xPortIsInsideInterrupt( void ) } /*-----------------------------------------------------------*/ -#if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) ) +#if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) void vPortValidateInterruptPriority( void ) { @@ -1944,7 +2025,7 @@ BaseType_t xPortIsInsideInterrupt( void ) configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue ); } -#endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) ) */ +#endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */ /*-----------------------------------------------------------*/ #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) diff --git a/Source/portable/ARMv8M/non_secure/portable/GCC/ARM_CM23/mpu_wrappers_v2_asm.c b/Source/portable/ARMv8M/non_secure/portable/GCC/ARM_CM23/mpu_wrappers_v2_asm.c index b8164a001..451244845 100644 --- a/Source/portable/ARMv8M/non_secure/portable/GCC/ARM_CM23/mpu_wrappers_v2_asm.c +++ b/Source/portable/ARMv8M/non_secure/portable/GCC/ARM_CM23/mpu_wrappers_v2_asm.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -376,32 +376,6 @@ } /*-----------------------------------------------------------*/ - char * MPU_pcTaskGetName( TaskHandle_t xTaskToQuery ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; - - char * MPU_pcTaskGetName( TaskHandle_t xTaskToQuery ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ - { - __asm volatile - ( - " .syntax unified \n" - " .extern MPU_pcTaskGetNameImpl \n" - " \n" - " push {r0, r1} \n" - " mrs r0, control \n" - " movs r1, #1 \n" - " tst r0, r1 \n" - " bne MPU_pcTaskGetName_Unpriv \n" - " MPU_pcTaskGetName_Priv: \n" - " pop {r0, r1} \n" - " b MPU_pcTaskGetNameImpl \n" - " MPU_pcTaskGetName_Unpriv: \n" - " pop {r0, r1} \n" - " svc %0 \n" - " \n" - : : "i" ( SYSTEM_CALL_pcTaskGetName ) : "memory" - ); - } -/*-----------------------------------------------------------*/ - #if ( configGENERATE_RUN_TIME_STATS == 1 ) configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetRunTimeCounter( const TaskHandle_t xTask ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; @@ -1562,31 +1536,28 @@ #if ( configUSE_TIMERS == 1 ) - BaseType_t MPU_xTimerGenericCommandEntry( const xTimerGenericCommandParams_t * pxParams ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + BaseType_t MPU_xTimerGenericCommandFromTaskEntry( const xTimerGenericCommandFromTaskParams_t * pxParams ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; - BaseType_t MPU_xTimerGenericCommandEntry( const xTimerGenericCommandParams_t * pxParams ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + BaseType_t MPU_xTimerGenericCommandFromTaskEntry( const xTimerGenericCommandFromTaskParams_t * pxParams ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ { __asm volatile ( - " .syntax unified \n" - " .extern MPU_xTimerGenericCommandPrivImpl \n" - " \n" - " push {r0, r1} \n" - " mrs r0, ipsr \n" - " cmp r0, #0 \n" - " bne MPU_xTimerGenericCommand_Priv \n" - " mrs r0, control \n" - " movs r1, #1 \n" - " tst r0, r1 \n" - " beq MPU_xTimerGenericCommand_Priv \n" - " MPU_xTimerGenericCommand_Unpriv: \n" - " pop {r0, r1} \n" - " svc %0 \n" - " MPU_xTimerGenericCommand_Priv: \n" - " pop {r0, r1} \n" - " b MPU_xTimerGenericCommandPrivImpl \n" - " \n" - : : "i" ( SYSTEM_CALL_xTimerGenericCommand ) : "memory" + " .syntax unified \n" + " .extern MPU_xTimerGenericCommandFromTaskImpl \n" + " \n" + " push {r0, r1} \n" + " mrs r0, control \n" + " movs r1, #1 \n" + " tst r0, r1 \n" + " bne MPU_xTimerGenericCommandFromTask_Unpriv \n" + " MPU_xTimerGenericCommandFromTask_Priv: \n" + " pop {r0, r1} \n" + " b MPU_xTimerGenericCommandFromTaskImpl \n" + " MPU_xTimerGenericCommandFromTask_Unpriv: \n" + " pop {r0, r1} \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xTimerGenericCommandFromTask ) : "memory" ); } diff --git a/Source/portable/ARMv8M/non_secure/portable/GCC/ARM_CM23/portasm.c b/Source/portable/ARMv8M/non_secure/portable/GCC/ARM_CM23/portasm.c index b23defe79..8b62c201c 100644 --- a/Source/portable/ARMv8M/non_secure/portable/GCC/ARM_CM23/portasm.c +++ b/Source/portable/ARMv8M/non_secure/portable/GCC/ARM_CM23/portasm.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -112,7 +112,6 @@ " ldmia r2!, {r0, r3-r6} \n" /* r0 = xSecureContext, r3 = original PSP, r4 = PSPLIM, r5 = CONTROL, r6 = LR. */ " subs r2, #20 \n" " msr psp, r3 \n" - " msr psplim, r4 \n" " msr control, r5 \n" " mov lr, r6 \n" " ldr r4, xSecureContextConst2 \n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */ @@ -163,7 +162,6 @@ " ldm r0!, {r1-r3} \n" /* Read from stack - r1 = xSecureContext, r2 = PSPLIM and r3 = EXC_RETURN. */ " ldr r4, xSecureContextConst2 \n" " str r1, [r4] \n" /* Set xSecureContext to this task's value for the same. */ - " msr psplim, r2 \n" /* Set this task's PSPLIM value. */ " movs r1, #2 \n" /* r1 = 2. */ " msr CONTROL, r1 \n" /* Switch to use PSP in the thread mode. */ " adds r0, #32 \n" /* Discard everything up to r0. */ @@ -327,7 +325,7 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att " \n" " save_special_regs: \n" " mrs r3, psp \n" /* r3 = PSP. */ - " mrs r4, psplim \n" /* r4 = PSPLIM. */ + " movs r4, #0 \n" /* r4 = 0. 0 is stored in the PSPLIM slot. */ " mrs r5, control \n" /* r5 = CONTROL. */ " mov r6, lr \n" /* r6 = LR. */ " stmia r2!, {r0, r3-r6} \n" /* Store xSecureContext, original PSP (after hardware has saved context), PSPLIM, CONTROL and LR. */ @@ -395,7 +393,6 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att " ldmia r2!, {r0, r3-r6} \n" /* r0 = xSecureContext, r3 = original PSP, r4 = PSPLIM, r5 = CONTROL, r6 = LR. */ " subs r2, #20 \n" " msr psp, r3 \n" - " msr psplim, r4 \n" " msr control, r5 \n" " mov lr, r6 \n" " ldr r4, xSecureContextConst \n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */ @@ -470,7 +467,7 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att " ldr r1, [r3] \n" /* Read pxCurrentTCB. */ " subs r2, r2, #12 \n" /* Make space for xSecureContext, PSPLIM and LR on the stack. */ " str r2, [r1] \n" /* Save the new top of stack in TCB. */ - " mrs r1, psplim \n" /* r1 = PSPLIM. */ + " movs r1, #0 \n" /* r1 = 0. 0 is stored in the PSPLIM slot. */ " mov r3, lr \n" /* r3 = LR/EXC_RETURN. */ " stmia r2!, {r0, r1, r3} \n" /* Store xSecureContext, PSPLIM and LR on the stack. */ " b select_next_task \n" @@ -480,7 +477,7 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att " ldr r1, [r3] \n" /* Read pxCurrentTCB. */ " subs r2, r2, #44 \n" /* Make space for xSecureContext, PSPLIM, LR and the remaining registers on the stack. */ " str r2, [r1] \n" /* Save the new top of stack in TCB. */ - " mrs r1, psplim \n" /* r1 = PSPLIM. */ + " movs r1, #0 \n" /* r1 = 0. 0 is stored in the PSPLIM slot. */ " mov r3, lr \n" /* r3 = LR/EXC_RETURN. */ " stmia r2!, {r0, r1, r3-r7} \n" /* Store xSecureContext, PSPLIM, LR and the low registers that are not saved automatically. */ " mov r4, r8 \n" /* r4 = r8. */ @@ -499,7 +496,6 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att " ldr r2, [r1] \n" /* The first item in pxCurrentTCB is the task top of stack. r2 now points to the top of stack. */ " \n" " ldmia r2!, {r0, r1, r4} \n" /* Read from stack - r0 = xSecureContext, r1 = PSPLIM and r4 = LR. */ - " msr psplim, r1 \n" /* Restore the PSPLIM register value for the task. */ " mov lr, r4 \n" /* LR = r4. */ " ldr r3, xSecureContextConst \n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */ " str r0, [r3] \n" /* Restore the task's xSecureContext. */ diff --git a/Source/portable/ARMv8M/non_secure/portable/GCC/ARM_CM23/portmacro.h b/Source/portable/ARMv8M/non_secure/portable/GCC/ARM_CM23/portmacro.h index d8dab9285..8034aa3a7 100644 --- a/Source/portable/ARMv8M/non_secure/portable/GCC/ARM_CM23/portmacro.h +++ b/Source/portable/ARMv8M/non_secure/portable/GCC/ARM_CM23/portmacro.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -48,9 +48,9 @@ /** * Architecture specifics. */ -#define portARCH_NAME "Cortex-M23" -#define portHAS_BASEPRI 0 -#define portDONT_DISCARD __attribute__( ( used ) ) +#define portARCH_NAME "Cortex-M23" +#define portHAS_ARMV8M_MAIN_EXTENSION 0 +#define portDONT_DISCARD __attribute__( ( used ) ) /*-----------------------------------------------------------*/ /* ARMv8-M common port configurations. */ diff --git a/Source/portable/ARMv8M/non_secure/portable/GCC/ARM_CM23_NTZ/mpu_wrappers_v2_asm.c b/Source/portable/ARMv8M/non_secure/portable/GCC/ARM_CM23_NTZ/mpu_wrappers_v2_asm.c index b8164a001..451244845 100644 --- a/Source/portable/ARMv8M/non_secure/portable/GCC/ARM_CM23_NTZ/mpu_wrappers_v2_asm.c +++ b/Source/portable/ARMv8M/non_secure/portable/GCC/ARM_CM23_NTZ/mpu_wrappers_v2_asm.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -376,32 +376,6 @@ } /*-----------------------------------------------------------*/ - char * MPU_pcTaskGetName( TaskHandle_t xTaskToQuery ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; - - char * MPU_pcTaskGetName( TaskHandle_t xTaskToQuery ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ - { - __asm volatile - ( - " .syntax unified \n" - " .extern MPU_pcTaskGetNameImpl \n" - " \n" - " push {r0, r1} \n" - " mrs r0, control \n" - " movs r1, #1 \n" - " tst r0, r1 \n" - " bne MPU_pcTaskGetName_Unpriv \n" - " MPU_pcTaskGetName_Priv: \n" - " pop {r0, r1} \n" - " b MPU_pcTaskGetNameImpl \n" - " MPU_pcTaskGetName_Unpriv: \n" - " pop {r0, r1} \n" - " svc %0 \n" - " \n" - : : "i" ( SYSTEM_CALL_pcTaskGetName ) : "memory" - ); - } -/*-----------------------------------------------------------*/ - #if ( configGENERATE_RUN_TIME_STATS == 1 ) configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetRunTimeCounter( const TaskHandle_t xTask ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; @@ -1562,31 +1536,28 @@ #if ( configUSE_TIMERS == 1 ) - BaseType_t MPU_xTimerGenericCommandEntry( const xTimerGenericCommandParams_t * pxParams ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + BaseType_t MPU_xTimerGenericCommandFromTaskEntry( const xTimerGenericCommandFromTaskParams_t * pxParams ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; - BaseType_t MPU_xTimerGenericCommandEntry( const xTimerGenericCommandParams_t * pxParams ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + BaseType_t MPU_xTimerGenericCommandFromTaskEntry( const xTimerGenericCommandFromTaskParams_t * pxParams ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ { __asm volatile ( - " .syntax unified \n" - " .extern MPU_xTimerGenericCommandPrivImpl \n" - " \n" - " push {r0, r1} \n" - " mrs r0, ipsr \n" - " cmp r0, #0 \n" - " bne MPU_xTimerGenericCommand_Priv \n" - " mrs r0, control \n" - " movs r1, #1 \n" - " tst r0, r1 \n" - " beq MPU_xTimerGenericCommand_Priv \n" - " MPU_xTimerGenericCommand_Unpriv: \n" - " pop {r0, r1} \n" - " svc %0 \n" - " MPU_xTimerGenericCommand_Priv: \n" - " pop {r0, r1} \n" - " b MPU_xTimerGenericCommandPrivImpl \n" - " \n" - : : "i" ( SYSTEM_CALL_xTimerGenericCommand ) : "memory" + " .syntax unified \n" + " .extern MPU_xTimerGenericCommandFromTaskImpl \n" + " \n" + " push {r0, r1} \n" + " mrs r0, control \n" + " movs r1, #1 \n" + " tst r0, r1 \n" + " bne MPU_xTimerGenericCommandFromTask_Unpriv \n" + " MPU_xTimerGenericCommandFromTask_Priv: \n" + " pop {r0, r1} \n" + " b MPU_xTimerGenericCommandFromTaskImpl \n" + " MPU_xTimerGenericCommandFromTask_Unpriv: \n" + " pop {r0, r1} \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xTimerGenericCommandFromTask ) : "memory" ); } diff --git a/Source/portable/ARMv8M/non_secure/portable/GCC/ARM_CM23_NTZ/portasm.c b/Source/portable/ARMv8M/non_secure/portable/GCC/ARM_CM23_NTZ/portasm.c index b90da71f3..6c5a74b5c 100644 --- a/Source/portable/ARMv8M/non_secure/portable/GCC/ARM_CM23_NTZ/portasm.c +++ b/Source/portable/ARMv8M/non_secure/portable/GCC/ARM_CM23_NTZ/portasm.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -112,7 +112,9 @@ " ldmia r1!, {r2-r5} \n" /* r2 = original PSP, r3 = PSPLIM, r4 = CONTROL, r5 = LR. */ " subs r1, #16 \n" " msr psp, r2 \n" - " msr psplim, r3 \n" + #if ( configRUN_FREERTOS_SECURE_ONLY == 1 ) + " msr psplim, r3 \n" + #endif " msr control, r4 \n" " mov lr, r5 \n" " \n" @@ -158,7 +160,9 @@ " ldr r0, [r1] \n" /* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */ " \n" " ldm r0!, {r1-r2} \n" /* Read from stack - r1 = PSPLIM and r2 = EXC_RETURN. */ - " msr psplim, r1 \n" /* Set this task's PSPLIM value. */ + #if ( configRUN_FREERTOS_SECURE_ONLY == 1 ) + " msr psplim, r1 \n" /* Set this task's PSPLIM value. */ + #endif " movs r1, #2 \n" /* r1 = 2. */ " msr CONTROL, r1 \n" /* Switch to use PSP in the thread mode. */ " adds r0, #32 \n" /* Discard everything up to r0. */ @@ -305,7 +309,11 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att " \n" " save_special_regs: \n" " mrs r2, psp \n" /* r2 = PSP. */ - " mrs r3, psplim \n" /* r3 = PSPLIM. */ + #if ( configRUN_FREERTOS_SECURE_ONLY == 1 ) + " mrs r3, psplim \n" /* r3 = PSPLIM. */ + #else + " movs r3, #0 \n" /* r3 = 0. 0 is stored in the PSPLIM slot. */ + #endif " mrs r4, control \n" /* r4 = CONTROL. */ " mov r5, lr \n" /* r5 = LR. */ " stmia r1!, {r2-r5} \n" /* Store original PSP (after hardware has saved context), PSPLIM, CONTROL and LR. */ @@ -373,7 +381,9 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att " ldmia r1!, {r2-r5} \n" /* r2 = original PSP, r3 = PSPLIM, r4 = CONTROL, r5 = LR. */ " subs r1, #16 \n" " msr psp, r2 \n" - " msr psplim, r3 \n" + #if ( configRUN_FREERTOS_SECURE_ONLY == 1 ) + " msr psplim, r3 \n" + #endif " msr control, r4 \n" " mov lr, r5 \n" " \n" @@ -419,7 +429,11 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att " ldr r1, [r2] \n" /* Read pxCurrentTCB. */ " subs r0, r0, #40 \n" /* Make space for PSPLIM, LR and the remaining registers on the stack. */ " str r0, [r1] \n" /* Save the new top of stack in TCB. */ - " mrs r2, psplim \n" /* r2 = PSPLIM. */ + #if ( configRUN_FREERTOS_SECURE_ONLY == 1 ) + " mrs r2, psplim \n" /* r2 = PSPLIM. */ + #else + " movs r2, #0 \n" /* r2 = 0. 0 is stored in the PSPLIM slot. */ + #endif " mov r3, lr \n" /* r3 = LR/EXC_RETURN. */ " stmia r0!, {r2-r7} \n" /* Store on the stack - PSPLIM, LR and low registers that are not automatically saved. */ " mov r4, r8 \n" /* r4 = r8. */ @@ -445,7 +459,9 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att " msr psp, r0 \n" /* Remember the new top of stack for the task. */ " subs r0, r0, #40 \n" /* Move to the starting of the saved context. */ " ldmia r0!, {r2-r7} \n" /* Read from stack - r2 = PSPLIM, r3 = LR and r4-r7 restored. */ - " msr psplim, r2 \n" /* Restore the PSPLIM register value for the task. */ + #if ( configRUN_FREERTOS_SECURE_ONLY == 1 ) + " msr psplim, r2 \n" /* Restore the PSPLIM register value for the task. */ + #endif " bx r3 \n" " \n" " .align 4 \n" diff --git a/Source/portable/ARMv8M/non_secure/portable/GCC/ARM_CM23_NTZ/portmacro.h b/Source/portable/ARMv8M/non_secure/portable/GCC/ARM_CM23_NTZ/portmacro.h index d8dab9285..8034aa3a7 100644 --- a/Source/portable/ARMv8M/non_secure/portable/GCC/ARM_CM23_NTZ/portmacro.h +++ b/Source/portable/ARMv8M/non_secure/portable/GCC/ARM_CM23_NTZ/portmacro.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -48,9 +48,9 @@ /** * Architecture specifics. */ -#define portARCH_NAME "Cortex-M23" -#define portHAS_BASEPRI 0 -#define portDONT_DISCARD __attribute__( ( used ) ) +#define portARCH_NAME "Cortex-M23" +#define portHAS_ARMV8M_MAIN_EXTENSION 0 +#define portDONT_DISCARD __attribute__( ( used ) ) /*-----------------------------------------------------------*/ /* ARMv8-M common port configurations. */ diff --git a/Source/portable/ARMv8M/non_secure/portable/GCC/ARM_CM33/mpu_wrappers_v2_asm.c b/Source/portable/ARMv8M/non_secure/portable/GCC/ARM_CM33/mpu_wrappers_v2_asm.c index d247c92e0..052f97850 100644 --- a/Source/portable/ARMv8M/non_secure/portable/GCC/ARM_CM33/mpu_wrappers_v2_asm.c +++ b/Source/portable/ARMv8M/non_secure/portable/GCC/ARM_CM33/mpu_wrappers_v2_asm.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -365,31 +365,6 @@ } /*-----------------------------------------------------------*/ - char * MPU_pcTaskGetName( TaskHandle_t xTaskToQuery ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; - - char * MPU_pcTaskGetName( TaskHandle_t xTaskToQuery ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ - { - __asm volatile - ( - " .syntax unified \n" - " .extern MPU_pcTaskGetNameImpl \n" - " \n" - " push {r0} \n" - " mrs r0, control \n" - " tst r0, #1 \n" - " bne MPU_pcTaskGetName_Unpriv \n" - " MPU_pcTaskGetName_Priv: \n" - " pop {r0} \n" - " b MPU_pcTaskGetNameImpl \n" - " MPU_pcTaskGetName_Unpriv: \n" - " pop {r0} \n" - " svc %0 \n" - " \n" - : : "i" ( SYSTEM_CALL_pcTaskGetName ) : "memory" - ); - } -/*-----------------------------------------------------------*/ - #if ( configGENERATE_RUN_TIME_STATS == 1 ) configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetRunTimeCounter( const TaskHandle_t xTask ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; @@ -1512,31 +1487,27 @@ #if ( configUSE_TIMERS == 1 ) - BaseType_t MPU_xTimerGenericCommandEntry( const xTimerGenericCommandParams_t * pxParams ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + BaseType_t MPU_xTimerGenericCommandFromTaskEntry( const xTimerGenericCommandFromTaskParams_t * pxParams ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; - BaseType_t MPU_xTimerGenericCommandEntry( const xTimerGenericCommandParams_t * pxParams ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + BaseType_t MPU_xTimerGenericCommandFromTaskEntry( const xTimerGenericCommandFromTaskParams_t * pxParams ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ { __asm volatile ( - " .syntax unified \n" - " .extern MPU_xTimerGenericCommandPrivImpl \n" - " \n" - " push {r0} \n" - " mrs r0, ipsr \n" - " cmp r0, #0 \n" - " bne MPU_xTimerGenericCommand_Priv \n" - " mrs r0, control \n" - " tst r0, #1 \n" - " beq MPU_xTimerGenericCommand_Priv \n" - " MPU_xTimerGenericCommand_Unpriv: \n" - " pop {r0} \n" - " svc %0 \n" - " MPU_xTimerGenericCommand_Priv: \n" - " pop {r0} \n" - " b MPU_xTimerGenericCommandPrivImpl \n" - " \n" - " \n" - : : "i" ( SYSTEM_CALL_xTimerGenericCommand ) : "memory" + " .syntax unified \n" + " .extern MPU_xTimerGenericCommandFromTaskImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " bne MPU_xTimerGenericCommandFromTask_Unpriv \n" + " MPU_xTimerGenericCommandFromTask_Priv: \n" + " pop {r0} \n" + " b MPU_xTimerGenericCommandFromTaskImpl \n" + " MPU_xTimerGenericCommandFromTask_Unpriv: \n" + " pop {r0} \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xTimerGenericCommandFromTask ) : "memory" ); } diff --git a/Source/portable/ARMv8M/non_secure/portable/GCC/ARM_CM33/portasm.c b/Source/portable/ARMv8M/non_secure/portable/GCC/ARM_CM33/portasm.c index 7431c98f1..451e0abb7 100644 --- a/Source/portable/ARMv8M/non_secure/portable/GCC/ARM_CM33/portasm.c +++ b/Source/portable/ARMv8M/non_secure/portable/GCC/ARM_CM33/portasm.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -75,16 +75,16 @@ " ldmia r0!, {r4-r11} \n" /* Read 4 set of RBAR/RLAR registers from TCB. */ " stmia r2, {r4-r11} \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */ " \n" - #if ( configTOTAL_MPU_REGIONS == 16 ) - " movs r3, #8 \n" /* r3 = 8. */ - " str r3, [r1] \n" /* Program RNR = 8. */ - " ldmia r0!, {r4-r11} \n" /* Read 4 set of RBAR/RLAR registers from TCB. */ - " stmia r2, {r4-r11} \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */ - " movs r3, #12 \n" /* r3 = 12. */ - " str r3, [r1] \n" /* Program RNR = 12. */ - " ldmia r0!, {r4-r11} \n" /* Read 4 set of RBAR/RLAR registers from TCB. */ - " stmia r2, {r4-r11} \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */ - #endif /* configTOTAL_MPU_REGIONS == 16 */ + #if ( configTOTAL_MPU_REGIONS == 16 ) + " movs r3, #8 \n" /* r3 = 8. */ + " str r3, [r1] \n" /* Program RNR = 8. */ + " ldmia r0!, {r4-r11} \n" /* Read 4 set of RBAR/RLAR registers from TCB. */ + " stmia r2, {r4-r11} \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */ + " movs r3, #12 \n" /* r3 = 12. */ + " str r3, [r1] \n" /* Program RNR = 12. */ + " ldmia r0!, {r4-r11} \n" /* Read 4 set of RBAR/RLAR registers from TCB. */ + " stmia r2, {r4-r11} \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */ + #endif /* configTOTAL_MPU_REGIONS == 16 */ " \n" " ldr r1, xMPUCTRLConst2 \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */ " ldr r2, [r1] \n" /* Read the value of MPU_CTRL. */ @@ -294,15 +294,15 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att " save_general_regs: \n" " mrs r3, psp \n" " \n" - #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) - " add r3, r3, #0x20 \n" /* Move r3 to location where s0 is saved. */ - " tst lr, #0x10 \n" - " ittt eq \n" - " vstmiaeq r2!, {s16-s31} \n" /* Store s16-s31. */ - " vldmiaeq r3, {s0-s16} \n" /* Copy hardware saved FP context into s0-s16. */ - " vstmiaeq r2!, {s0-s16} \n" /* Store hardware saved FP context. */ - " sub r3, r3, #0x20 \n" /* Set r3 back to the location of hardware saved context. */ - #endif /* configENABLE_FPU || configENABLE_MVE */ + #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) + " add r3, r3, #0x20 \n" /* Move r3 to location where s0 is saved. */ + " tst lr, #0x10 \n" + " ittt eq \n" + " vstmiaeq r2!, {s16-s31} \n" /* Store s16-s31. */ + " vldmiaeq r3, {s0-s16} \n" /* Copy hardware saved FP context into s0-s16. */ + " vstmiaeq r2!, {s0-s16} \n" /* Store hardware saved FP context. */ + " sub r3, r3, #0x20 \n" /* Set r3 back to the location of hardware saved context. */ + #endif /* configENABLE_FPU || configENABLE_MVE */ " \n" " stmia r2!, {r4-r11} \n" /* Store r4-r11. */ " ldmia r3, {r4-r11} \n" /* Copy the hardware saved context into r4-r11. */ @@ -348,16 +348,16 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att " ldmia r0!, {r4-r11} \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */ " stmia r2, {r4-r11} \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */ " \n" - #if ( configTOTAL_MPU_REGIONS == 16 ) - " movs r3, #8 \n" /* r3 = 8. */ - " str r3, [r1] \n" /* Program RNR = 8. */ - " ldmia r0!, {r4-r11} \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */ - " stmia r2, {r4-r11} \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */ - " movs r3, #12 \n" /* r3 = 12. */ - " str r3, [r1] \n" /* Program RNR = 12. */ - " ldmia r0!, {r4-r11} \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */ - " stmia r2, {r4-r11} \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */ - #endif /* configTOTAL_MPU_REGIONS == 16 */ + #if ( configTOTAL_MPU_REGIONS == 16 ) + " movs r3, #8 \n" /* r3 = 8. */ + " str r3, [r1] \n" /* Program RNR = 8. */ + " ldmia r0!, {r4-r11} \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */ + " stmia r2, {r4-r11} \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */ + " movs r3, #12 \n" /* r3 = 12. */ + " str r3, [r1] \n" /* Program RNR = 12. */ + " ldmia r0!, {r4-r11} \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */ + " stmia r2, {r4-r11} \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */ + #endif /* configTOTAL_MPU_REGIONS == 16 */ " \n" " ldr r1, xMPUCTRLConst \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */ " ldr r2, [r1] \n" /* Read the value of MPU_CTRL. */ @@ -393,13 +393,13 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att " ldmdb r2!, {r4-r11} \n" /* r4-r11 contain hardware saved context. */ " stmia r3!, {r4-r11} \n" /* Copy the hardware saved context on the task stack. */ " ldmdb r2!, {r4-r11} \n" /* r4-r11 restored. */ - #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) - " tst lr, #0x10 \n" - " ittt eq \n" - " vldmdbeq r2!, {s0-s16} \n" /* s0-s16 contain hardware saved FP context. */ - " vstmiaeq r3!, {s0-s16} \n" /* Copy hardware saved FP context on the task stack. */ - " vldmdbeq r2!, {s16-s31} \n" /* Restore s16-s31. */ - #endif /* configENABLE_FPU || configENABLE_MVE */ + #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) + " tst lr, #0x10 \n" + " ittt eq \n" + " vldmdbeq r2!, {s0-s16} \n" /* s0-s16 contain hardware saved FP context. */ + " vstmiaeq r3!, {s0-s16} \n" /* Copy hardware saved FP context on the task stack. */ + " vldmdbeq r2!, {s16-s31} \n" /* Restore s16-s31. */ + #endif /* configENABLE_FPU || configENABLE_MVE */ " \n" " restore_context_done: \n" " str r2, [r1] \n" /* Save the location where the context should be saved next as the first member of TCB. */ @@ -452,11 +452,11 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att " save_ns_context: \n" " ldr r3, pxCurrentTCBConst \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ " ldr r1, [r3] \n" /* Read pxCurrentTCB. */ - #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) - " tst lr, #0x10 \n" /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */ - " it eq \n" - " vstmdbeq r2!, {s16-s31} \n" /* Store the additional FP context registers which are not saved automatically. */ - #endif /* configENABLE_FPU || configENABLE_MVE */ + #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) + " tst lr, #0x10 \n" /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */ + " it eq \n" + " vstmdbeq r2!, {s16-s31} \n" /* Store the additional FP context registers which are not saved automatically. */ + #endif /* configENABLE_FPU || configENABLE_MVE */ " subs r2, r2, #44 \n" /* Make space for xSecureContext, PSPLIM, LR and the remaining registers on the stack. */ " str r2, [r1] \n" /* Save the new top of stack in TCB. */ " adds r2, r2, #12 \n" /* r2 = r2 + 12. */ @@ -498,11 +498,11 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att " \n" " restore_ns_context: \n" " ldmia r2!, {r4-r11} \n" /* Restore the registers that are not automatically restored. */ - #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) - " tst lr, #0x10 \n" /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */ - " it eq \n" - " vldmiaeq r2!, {s16-s31} \n" /* Restore the additional FP context registers which are not restored automatically. */ - #endif /* configENABLE_FPU || configENABLE_MVE */ + #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) + " tst lr, #0x10 \n" /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */ + " it eq \n" + " vldmiaeq r2!, {s16-s31} \n" /* Restore the additional FP context registers which are not restored automatically. */ + #endif /* configENABLE_FPU || configENABLE_MVE */ " msr psp, r2 \n" /* Remember the new top of stack for the task. */ " bx lr \n" " \n" diff --git a/Source/portable/ARMv8M/non_secure/portable/GCC/ARM_CM33/portmacro.h b/Source/portable/ARMv8M/non_secure/portable/GCC/ARM_CM33/portmacro.h index cc798707e..a5416a66a 100644 --- a/Source/portable/ARMv8M/non_secure/portable/GCC/ARM_CM33/portmacro.h +++ b/Source/portable/ARMv8M/non_secure/portable/GCC/ARM_CM33/portmacro.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -48,9 +48,9 @@ /** * Architecture specifics. */ -#define portARCH_NAME "Cortex-M33" -#define portHAS_BASEPRI 1 -#define portDONT_DISCARD __attribute__( ( used ) ) +#define portARCH_NAME "Cortex-M33" +#define portHAS_ARMV8M_MAIN_EXTENSION 1 +#define portDONT_DISCARD __attribute__( ( used ) ) /*-----------------------------------------------------------*/ /* ARMv8-M common port configurations. */ @@ -60,8 +60,8 @@ /** * @brief Critical section management. */ -#define portDISABLE_INTERRUPTS() ulSetInterruptMask() -#define portENABLE_INTERRUPTS() vClearInterruptMask( 0 ) +#define portDISABLE_INTERRUPTS() ulSetInterruptMask() +#define portENABLE_INTERRUPTS() vClearInterruptMask( 0 ) /*-----------------------------------------------------------*/ /* *INDENT-OFF* */ diff --git a/Source/portable/ARMv8M/non_secure/portable/GCC/ARM_CM33_NTZ/mpu_wrappers_v2_asm.c b/Source/portable/ARMv8M/non_secure/portable/GCC/ARM_CM33_NTZ/mpu_wrappers_v2_asm.c index d247c92e0..052f97850 100644 --- a/Source/portable/ARMv8M/non_secure/portable/GCC/ARM_CM33_NTZ/mpu_wrappers_v2_asm.c +++ b/Source/portable/ARMv8M/non_secure/portable/GCC/ARM_CM33_NTZ/mpu_wrappers_v2_asm.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -365,31 +365,6 @@ } /*-----------------------------------------------------------*/ - char * MPU_pcTaskGetName( TaskHandle_t xTaskToQuery ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; - - char * MPU_pcTaskGetName( TaskHandle_t xTaskToQuery ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ - { - __asm volatile - ( - " .syntax unified \n" - " .extern MPU_pcTaskGetNameImpl \n" - " \n" - " push {r0} \n" - " mrs r0, control \n" - " tst r0, #1 \n" - " bne MPU_pcTaskGetName_Unpriv \n" - " MPU_pcTaskGetName_Priv: \n" - " pop {r0} \n" - " b MPU_pcTaskGetNameImpl \n" - " MPU_pcTaskGetName_Unpriv: \n" - " pop {r0} \n" - " svc %0 \n" - " \n" - : : "i" ( SYSTEM_CALL_pcTaskGetName ) : "memory" - ); - } -/*-----------------------------------------------------------*/ - #if ( configGENERATE_RUN_TIME_STATS == 1 ) configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetRunTimeCounter( const TaskHandle_t xTask ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; @@ -1512,31 +1487,27 @@ #if ( configUSE_TIMERS == 1 ) - BaseType_t MPU_xTimerGenericCommandEntry( const xTimerGenericCommandParams_t * pxParams ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + BaseType_t MPU_xTimerGenericCommandFromTaskEntry( const xTimerGenericCommandFromTaskParams_t * pxParams ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; - BaseType_t MPU_xTimerGenericCommandEntry( const xTimerGenericCommandParams_t * pxParams ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + BaseType_t MPU_xTimerGenericCommandFromTaskEntry( const xTimerGenericCommandFromTaskParams_t * pxParams ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ { __asm volatile ( - " .syntax unified \n" - " .extern MPU_xTimerGenericCommandPrivImpl \n" - " \n" - " push {r0} \n" - " mrs r0, ipsr \n" - " cmp r0, #0 \n" - " bne MPU_xTimerGenericCommand_Priv \n" - " mrs r0, control \n" - " tst r0, #1 \n" - " beq MPU_xTimerGenericCommand_Priv \n" - " MPU_xTimerGenericCommand_Unpriv: \n" - " pop {r0} \n" - " svc %0 \n" - " MPU_xTimerGenericCommand_Priv: \n" - " pop {r0} \n" - " b MPU_xTimerGenericCommandPrivImpl \n" - " \n" - " \n" - : : "i" ( SYSTEM_CALL_xTimerGenericCommand ) : "memory" + " .syntax unified \n" + " .extern MPU_xTimerGenericCommandFromTaskImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " bne MPU_xTimerGenericCommandFromTask_Unpriv \n" + " MPU_xTimerGenericCommandFromTask_Priv: \n" + " pop {r0} \n" + " b MPU_xTimerGenericCommandFromTaskImpl \n" + " MPU_xTimerGenericCommandFromTask_Unpriv: \n" + " pop {r0} \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xTimerGenericCommandFromTask ) : "memory" ); } diff --git a/Source/portable/ARMv8M/non_secure/portable/GCC/ARM_CM33_NTZ/portasm.c b/Source/portable/ARMv8M/non_secure/portable/GCC/ARM_CM33_NTZ/portasm.c index b3f6a0aac..6169b9358 100644 --- a/Source/portable/ARMv8M/non_secure/portable/GCC/ARM_CM33_NTZ/portasm.c +++ b/Source/portable/ARMv8M/non_secure/portable/GCC/ARM_CM33_NTZ/portasm.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -75,16 +75,16 @@ " ldmia r0!, {r4-r11} \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */ " stmia r2, {r4-r11} \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */ " \n" - #if ( configTOTAL_MPU_REGIONS == 16 ) - " movs r3, #8 \n" /* r3 = 8. */ - " str r3, [r1] \n" /* Program RNR = 8. */ - " ldmia r0!, {r4-r11} \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */ - " stmia r2, {r4-r11} \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */ - " movs r3, #12 \n" /* r3 = 12. */ - " str r3, [r1] \n" /* Program RNR = 12. */ - " ldmia r0!, {r4-r11} \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */ - " stmia r2, {r4-r11} \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */ - #endif /* configTOTAL_MPU_REGIONS == 16 */ + #if ( configTOTAL_MPU_REGIONS == 16 ) + " movs r3, #8 \n" /* r3 = 8. */ + " str r3, [r1] \n" /* Program RNR = 8. */ + " ldmia r0!, {r4-r11} \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */ + " stmia r2, {r4-r11} \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */ + " movs r3, #12 \n" /* r3 = 12. */ + " str r3, [r1] \n" /* Program RNR = 12. */ + " ldmia r0!, {r4-r11} \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */ + " stmia r2, {r4-r11} \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */ + #endif /* configTOTAL_MPU_REGIONS == 16 */ " \n" " ldr r1, xMPUCTRLConst2 \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */ " ldr r2, [r1] \n" /* Read the value of MPU_CTRL. */ @@ -273,15 +273,15 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att " mrs r2, psp \n" /* r2 = PSP. */ " \n" " save_general_regs: \n" - #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) - " add r2, r2, #0x20 \n" /* Move r2 to location where s0 is saved. */ - " tst lr, #0x10 \n" - " ittt eq \n" - " vstmiaeq r1!, {s16-s31} \n" /* Store s16-s31. */ - " vldmiaeq r2, {s0-s16} \n" /* Copy hardware saved FP context into s0-s16. */ - " vstmiaeq r1!, {s0-s16} \n" /* Store hardware saved FP context. */ - " sub r2, r2, #0x20 \n" /* Set r2 back to the location of hardware saved context. */ - #endif /* configENABLE_FPU || configENABLE_MVE */ + #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) + " add r2, r2, #0x20 \n" /* Move r2 to location where s0 is saved. */ + " tst lr, #0x10 \n" + " ittt eq \n" + " vstmiaeq r1!, {s16-s31} \n" /* Store s16-s31. */ + " vldmiaeq r2, {s0-s16} \n" /* Copy hardware saved FP context into s0-s16. */ + " vstmiaeq r1!, {s0-s16} \n" /* Store hardware saved FP context. */ + " sub r2, r2, #0x20 \n" /* Set r2 back to the location of hardware saved context. */ + #endif /* configENABLE_FPU || configENABLE_MVE */ " \n" " stmia r1!, {r4-r11} \n" /* Store r4-r11. */ " ldmia r2, {r4-r11} \n" /* Copy the hardware saved context into r4-r11. */ @@ -326,16 +326,16 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att " ldmia r0!, {r4-r11} \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */ " stmia r2, {r4-r11} \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */ " \n" - #if ( configTOTAL_MPU_REGIONS == 16 ) - " movs r3, #8 \n" /* r3 = 8. */ - " str r3, [r1] \n" /* Program RNR = 8. */ - " ldmia r0!, {r4-r11} \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */ - " stmia r2, {r4-r11} \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */ - " movs r3, #12 \n" /* r3 = 12. */ - " str r3, [r1] \n" /* Program RNR = 12. */ - " ldmia r0!, {r4-r11} \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */ - " stmia r2, {r4-r11} \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */ - #endif /* configTOTAL_MPU_REGIONS == 16 */ + #if ( configTOTAL_MPU_REGIONS == 16 ) + " movs r3, #8 \n" /* r3 = 8. */ + " str r3, [r1] \n" /* Program RNR = 8. */ + " ldmia r0!, {r4-r11} \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */ + " stmia r2, {r4-r11} \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */ + " movs r3, #12 \n" /* r3 = 12. */ + " str r3, [r1] \n" /* Program RNR = 12. */ + " ldmia r0!, {r4-r11} \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */ + " stmia r2, {r4-r11} \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */ + #endif /* configTOTAL_MPU_REGIONS == 16 */ " \n" " ldr r1, xMPUCTRLConst \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */ " ldr r2, [r1] \n" /* Read the value of MPU_CTRL. */ @@ -358,13 +358,13 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att " ldmdb r1!, {r4-r11} \n" /* r4-r11 contain hardware saved context. */ " stmia r2!, {r4-r11} \n" /* Copy the hardware saved context on the task stack. */ " ldmdb r1!, {r4-r11} \n" /* r4-r11 restored. */ - #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) - " tst lr, #0x10 \n" - " ittt eq \n" - " vldmdbeq r1!, {s0-s16} \n" /* s0-s16 contain hardware saved FP context. */ - " vstmiaeq r2!, {s0-s16} \n" /* Copy hardware saved FP context on the task stack. */ - " vldmdbeq r1!, {s16-s31} \n" /* Restore s16-s31. */ - #endif /* configENABLE_FPU || configENABLE_MVE */ + #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) + " tst lr, #0x10 \n" + " ittt eq \n" + " vldmdbeq r1!, {s0-s16} \n" /* s0-s16 contain hardware saved FP context. */ + " vstmiaeq r2!, {s0-s16} \n" /* Copy hardware saved FP context on the task stack. */ + " vldmdbeq r1!, {s16-s31} \n" /* Restore s16-s31. */ + #endif /* configENABLE_FPU || configENABLE_MVE */ " \n" " restore_context_done: \n" " str r1, [r0] \n" /* Save the location where the context should be saved next as the first member of TCB. */ @@ -390,11 +390,11 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att " \n" " mrs r0, psp \n" /* Read PSP in r0. */ " \n" - #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) - " tst lr, #0x10 \n" /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */ - " it eq \n" - " vstmdbeq r0!, {s16-s31} \n" /* Store the additional FP context registers which are not saved automatically. */ - #endif /* configENABLE_FPU || configENABLE_MVE */ + #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) + " tst lr, #0x10 \n" /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */ + " it eq \n" + " vstmdbeq r0!, {s16-s31} \n" /* Store the additional FP context registers which are not saved automatically. */ + #endif /* configENABLE_FPU || configENABLE_MVE */ " \n" " mrs r2, psplim \n" /* r2 = PSPLIM. */ " mov r3, lr \n" /* r3 = LR/EXC_RETURN. */ @@ -418,11 +418,11 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att " \n" " ldmia r0!, {r2-r11} \n" /* Read from stack - r2 = PSPLIM, r3 = LR and r4-r11 restored. */ " \n" - #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) - " tst r3, #0x10 \n" /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */ - " it eq \n" - " vldmiaeq r0!, {s16-s31} \n" /* Restore the additional FP context registers which are not restored automatically. */ - #endif /* configENABLE_FPU || configENABLE_MVE */ + #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) + " tst r3, #0x10 \n" /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */ + " it eq \n" + " vldmiaeq r0!, {s16-s31} \n" /* Restore the additional FP context registers which are not restored automatically. */ + #endif /* configENABLE_FPU || configENABLE_MVE */ " \n" " msr psplim, r2 \n" /* Restore the PSPLIM register value for the task. */ " msr psp, r0 \n" /* Remember the new top of stack for the task. */ diff --git a/Source/portable/ARMv8M/non_secure/portable/GCC/ARM_CM33_NTZ/portmacro.h b/Source/portable/ARMv8M/non_secure/portable/GCC/ARM_CM33_NTZ/portmacro.h index cc798707e..a5416a66a 100644 --- a/Source/portable/ARMv8M/non_secure/portable/GCC/ARM_CM33_NTZ/portmacro.h +++ b/Source/portable/ARMv8M/non_secure/portable/GCC/ARM_CM33_NTZ/portmacro.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -48,9 +48,9 @@ /** * Architecture specifics. */ -#define portARCH_NAME "Cortex-M33" -#define portHAS_BASEPRI 1 -#define portDONT_DISCARD __attribute__( ( used ) ) +#define portARCH_NAME "Cortex-M33" +#define portHAS_ARMV8M_MAIN_EXTENSION 1 +#define portDONT_DISCARD __attribute__( ( used ) ) /*-----------------------------------------------------------*/ /* ARMv8-M common port configurations. */ @@ -60,8 +60,8 @@ /** * @brief Critical section management. */ -#define portDISABLE_INTERRUPTS() ulSetInterruptMask() -#define portENABLE_INTERRUPTS() vClearInterruptMask( 0 ) +#define portDISABLE_INTERRUPTS() ulSetInterruptMask() +#define portENABLE_INTERRUPTS() vClearInterruptMask( 0 ) /*-----------------------------------------------------------*/ /* *INDENT-OFF* */ diff --git a/Source/portable/ARMv8M/non_secure/portable/GCC/ARM_CM35P/portmacro.h b/Source/portable/ARMv8M/non_secure/portable/GCC/ARM_CM35P/portmacro.h index 557b542eb..ea29ac207 100644 --- a/Source/portable/ARMv8M/non_secure/portable/GCC/ARM_CM35P/portmacro.h +++ b/Source/portable/ARMv8M/non_secure/portable/GCC/ARM_CM35P/portmacro.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -48,9 +48,9 @@ /** * Architecture specifics. */ -#define portARCH_NAME "Cortex-M35P" -#define portHAS_BASEPRI 1 -#define portDONT_DISCARD __attribute__( ( used ) ) +#define portARCH_NAME "Cortex-M35P" +#define portHAS_ARMV8M_MAIN_EXTENSION 1 +#define portDONT_DISCARD __attribute__( ( used ) ) /*-----------------------------------------------------------*/ /* ARMv8-M common port configurations. */ @@ -60,8 +60,8 @@ /** * @brief Critical section management. */ -#define portDISABLE_INTERRUPTS() ulSetInterruptMask() -#define portENABLE_INTERRUPTS() vClearInterruptMask( 0 ) +#define portDISABLE_INTERRUPTS() ulSetInterruptMask() +#define portENABLE_INTERRUPTS() vClearInterruptMask( 0 ) /*-----------------------------------------------------------*/ /* *INDENT-OFF* */ diff --git a/Source/portable/ARMv8M/non_secure/portable/GCC/ARM_CM55/portmacro.h b/Source/portable/ARMv8M/non_secure/portable/GCC/ARM_CM55/portmacro.h index 880205cb1..9f2bdb433 100644 --- a/Source/portable/ARMv8M/non_secure/portable/GCC/ARM_CM55/portmacro.h +++ b/Source/portable/ARMv8M/non_secure/portable/GCC/ARM_CM55/portmacro.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -53,9 +53,9 @@ /** * Architecture specifics. */ -#define portARCH_NAME "Cortex-M55" -#define portHAS_BASEPRI 1 -#define portDONT_DISCARD __attribute__( ( used ) ) +#define portARCH_NAME "Cortex-M55" +#define portHAS_ARMV8M_MAIN_EXTENSION 1 +#define portDONT_DISCARD __attribute__( ( used ) ) /*-----------------------------------------------------------*/ /* ARMv8-M common port configurations. */ @@ -65,8 +65,8 @@ /** * @brief Critical section management. */ -#define portDISABLE_INTERRUPTS() ulSetInterruptMask() -#define portENABLE_INTERRUPTS() vClearInterruptMask( 0 ) +#define portDISABLE_INTERRUPTS() ulSetInterruptMask() +#define portENABLE_INTERRUPTS() vClearInterruptMask( 0 ) /*-----------------------------------------------------------*/ /* *INDENT-OFF* */ diff --git a/Source/portable/ARMv8M/non_secure/portable/GCC/ARM_CM85/portmacro.h b/Source/portable/ARMv8M/non_secure/portable/GCC/ARM_CM85/portmacro.h index f606f817d..bd605f630 100644 --- a/Source/portable/ARMv8M/non_secure/portable/GCC/ARM_CM85/portmacro.h +++ b/Source/portable/ARMv8M/non_secure/portable/GCC/ARM_CM85/portmacro.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -53,9 +53,9 @@ /** * Architecture specifics. */ -#define portARCH_NAME "Cortex-M85" -#define portHAS_BASEPRI 1 -#define portDONT_DISCARD __attribute__( ( used ) ) +#define portARCH_NAME "Cortex-M85" +#define portHAS_ARMV8M_MAIN_EXTENSION 1 +#define portDONT_DISCARD __attribute__( ( used ) ) /*-----------------------------------------------------------*/ /* ARMv8-M common port configurations. */ @@ -65,8 +65,8 @@ /** * @brief Critical section management. */ -#define portDISABLE_INTERRUPTS() ulSetInterruptMask() -#define portENABLE_INTERRUPTS() vClearInterruptMask( 0 ) +#define portDISABLE_INTERRUPTS() ulSetInterruptMask() +#define portENABLE_INTERRUPTS() vClearInterruptMask( 0 ) /*-----------------------------------------------------------*/ /* *INDENT-OFF* */ diff --git a/Source/portable/ARMv8M/non_secure/portable/IAR/ARM_CM23/mpu_wrappers_v2_asm.S b/Source/portable/ARMv8M/non_secure/portable/IAR/ARM_CM23/mpu_wrappers_v2_asm.S index 4d805f3e2..0b7d942e4 100644 --- a/Source/portable/ARMv8M/non_secure/portable/IAR/ARM_CM23/mpu_wrappers_v2_asm.S +++ b/Source/portable/ARMv8M/non_secure/portable/IAR/ARM_CM23/mpu_wrappers_v2_asm.S @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -207,21 +207,6 @@ MPU_uxTaskGetNumberOfTasks: svc #SYSTEM_CALL_uxTaskGetNumberOfTasks /*-----------------------------------------------------------*/ - PUBLIC MPU_pcTaskGetName -MPU_pcTaskGetName: - push {r0, r1} - mrs r0, control - movs r1, #1 - tst r0, r1 - bne MPU_pcTaskGetName_Unpriv - MPU_pcTaskGetName_Priv: - pop {r0, r1} - b MPU_pcTaskGetNameImpl - MPU_pcTaskGetName_Unpriv: - pop {r0, r1} - svc #SYSTEM_CALL_pcTaskGetName -/*-----------------------------------------------------------*/ - PUBLIC MPU_ulTaskGetRunTimeCounter MPU_ulTaskGetRunTimeCounter: push {r0, r1} @@ -792,25 +777,19 @@ MPU_xTimerGetTimerDaemonTaskHandle: svc #SYSTEM_CALL_xTimerGetTimerDaemonTaskHandle /*-----------------------------------------------------------*/ - PUBLIC MPU_xTimerGenericCommandEntry -MPU_xTimerGenericCommandEntry: + PUBLIC MPU_xTimerGenericCommandFromTaskEntry +MPU_xTimerGenericCommandFromTaskEntry: push {r0, r1} - /* This function can be called from ISR also and therefore, we need a check - * to take privileged path, if called from ISR. */ - mrs r0, ipsr - cmp r0, #0 - bne MPU_xTimerGenericCommand_Priv mrs r0, control movs r1, #1 tst r0, r1 - beq MPU_xTimerGenericCommand_Priv - MPU_xTimerGenericCommand_Unpriv: + bne MPU_xTimerGenericCommandFromTask_Unpriv + MPU_xTimerGenericCommandFromTask_Priv: pop {r0, r1} - svc #SYSTEM_CALL_xTimerGenericCommand - MPU_xTimerGenericCommand_Priv: + b MPU_xTimerGenericCommandFromTaskImpl + MPU_xTimerGenericCommandFromTask_Unpriv: pop {r0, r1} - b MPU_xTimerGenericCommandPrivImpl - + svc #SYSTEM_CALL_xTimerGenericCommandFromTask /*-----------------------------------------------------------*/ PUBLIC MPU_pcTimerGetName @@ -1160,10 +1139,6 @@ MPU_xTaskGetTickCountImpl: MPU_uxTaskGetNumberOfTasksImpl: b MPU_uxTaskGetNumberOfTasksImpl - PUBWEAK MPU_pcTaskGetNameImpl -MPU_pcTaskGetNameImpl: - b MPU_pcTaskGetNameImpl - PUBWEAK MPU_ulTaskGetRunTimeCounterImpl MPU_ulTaskGetRunTimeCounterImpl: b MPU_ulTaskGetRunTimeCounterImpl @@ -1316,9 +1291,9 @@ MPU_xTimerIsTimerActiveImpl: MPU_xTimerGetTimerDaemonTaskHandleImpl: b MPU_xTimerGetTimerDaemonTaskHandleImpl - PUBWEAK MPU_xTimerGenericCommandPrivImpl -MPU_xTimerGenericCommandPrivImpl: - b MPU_xTimerGenericCommandPrivImpl + PUBWEAK MPU_xTimerGenericCommandFromTaskImpl +MPU_xTimerGenericCommandFromTaskImpl: + b MPU_xTimerGenericCommandFromTaskImpl PUBWEAK MPU_pcTimerGetNameImpl MPU_pcTimerGetNameImpl: diff --git a/Source/portable/ARMv8M/non_secure/portable/IAR/ARM_CM23/portasm.s b/Source/portable/ARMv8M/non_secure/portable/IAR/ARM_CM23/portasm.s index 3c1788998..276fb3969 100644 --- a/Source/portable/ARMv8M/non_secure/portable/IAR/ARM_CM23/portasm.s +++ b/Source/portable/ARMv8M/non_secure/portable/IAR/ARM_CM23/portasm.s @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -40,6 +40,7 @@ files (__ICCARM__ is defined by the IAR C compiler but not by the IAR assembler. #define configUSE_MPU_WRAPPERS_V1 0 #endif + EXTERN pxCurrentTCB EXTERN xSecureContext EXTERN vTaskSwitchContext @@ -169,7 +170,6 @@ vRestoreContextOfFirstTask: ldmia r2!, {r0, r3-r6} /* r0 = xSecureContext, r3 = original PSP, r4 = PSPLIM, r5 = CONTROL, r6 = LR. */ subs r2, #20 msr psp, r3 - msr psplim, r4 msr control, r5 mov lr, r6 ldr r4, =xSecureContext /* Read the location of xSecureContext i.e. &( xSecureContext ). */ @@ -205,7 +205,6 @@ vRestoreContextOfFirstTask: ldm r0!, {r1-r3} /* Read from stack - r1 = xSecureContext, r2 = PSPLIM and r3 = EXC_RETURN. */ ldr r4, =xSecureContext str r1, [r4] /* Set xSecureContext to this task's value for the same. */ - msr psplim, r2 /* Set this task's PSPLIM value. */ movs r1, #2 /* r1 = 2. */ msr CONTROL, r1 /* Switch to use PSP in the thread mode. */ adds r0, #32 /* Discard everything up to r0. */ @@ -281,7 +280,7 @@ PendSV_Handler: save_special_regs: mrs r3, psp /* r3 = PSP. */ - mrs r4, psplim /* r4 = PSPLIM. */ + movs r4, #0 /* r4 = 0. 0 is stored in the PSPLIM slot. */ mrs r5, control /* r5 = CONTROL. */ mov r6, lr /* r6 = LR. */ stmia r2!, {r0, r3-r6} /* Store xSecureContext, original PSP (after hardware has saved context), PSPLIM, CONTROL and LR. */ @@ -349,7 +348,6 @@ PendSV_Handler: ldmia r2!, {r0, r3-r6} /* r0 = xSecureContext, r3 = original PSP, r4 = PSPLIM, r5 = CONTROL, r6 = LR. */ subs r2, #20 msr psp, r3 - msr psplim, r4 msr control, r5 mov lr, r6 ldr r4, =xSecureContext /* Read the location of xSecureContext i.e. &( xSecureContext ). */ @@ -408,7 +406,7 @@ PendSV_Handler: subs r2, r2, #12 /* Make space for xSecureContext, PSPLIM and LR on the stack. */ str r2, [r1] /* Save the new top of stack in TCB. */ - mrs r1, psplim /* r1 = PSPLIM. */ + movs r1, #0 /* r1 = 0. 0 is stored in the PSPLIM slot. */ mov r3, lr /* r3 = LR/EXC_RETURN. */ stmia r2!, {r0, r1, r3} /* Store xSecureContext, PSPLIM and LR on the stack. */ @@ -419,7 +417,7 @@ PendSV_Handler: ldr r1, [r3] /* Read pxCurrentTCB. */ subs r2, r2, #44 /* Make space for xSecureContext, PSPLIM, LR and the remaining registers on the stack. */ str r2, [r1] /* Save the new top of stack in TCB. */ - mrs r1, psplim /* r1 = PSPLIM. */ + movs r1, #0 /* r1 = 0. 0 is stored in the PSPLIM slot. */ mov r3, lr /* r3 = LR/EXC_RETURN. */ stmia r2!, {r0, r1, r3-r7} /* Store xSecureContext, PSPLIM, LR and the low registers that are not saved automatically. */ mov r4, r8 /* r4 = r8. */ @@ -438,7 +436,6 @@ PendSV_Handler: ldr r2, [r1] /* The first item in pxCurrentTCB is the task top of stack. r2 now points to the top of stack. */ ldmia r2!, {r0, r1, r4} /* Read from stack - r0 = xSecureContext, r1 = PSPLIM and r4 = LR. */ - msr psplim, r1 /* Restore the PSPLIM register value for the task. */ mov lr, r4 /* LR = r4. */ ldr r3, =xSecureContext /* Read the location of xSecureContext i.e. &( xSecureContext ). */ str r0, [r3] /* Restore the task's xSecureContext. */ diff --git a/Source/portable/ARMv8M/non_secure/portable/IAR/ARM_CM23/portmacro.h b/Source/portable/ARMv8M/non_secure/portable/IAR/ARM_CM23/portmacro.h index 19d7556fb..52ab2a3ac 100644 --- a/Source/portable/ARMv8M/non_secure/portable/IAR/ARM_CM23/portmacro.h +++ b/Source/portable/ARMv8M/non_secure/portable/IAR/ARM_CM23/portmacro.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -48,9 +48,9 @@ /** * Architecture specifics. */ -#define portARCH_NAME "Cortex-M23" -#define portHAS_BASEPRI 0 -#define portDONT_DISCARD __root +#define portARCH_NAME "Cortex-M23" +#define portHAS_ARMV8M_MAIN_EXTENSION 0 +#define portDONT_DISCARD __root /*-----------------------------------------------------------*/ /* ARMv8-M common port configurations. */ diff --git a/Source/portable/ARMv8M/non_secure/portable/IAR/ARM_CM23_NTZ/mpu_wrappers_v2_asm.S b/Source/portable/ARMv8M/non_secure/portable/IAR/ARM_CM23_NTZ/mpu_wrappers_v2_asm.S index 4d805f3e2..0b7d942e4 100644 --- a/Source/portable/ARMv8M/non_secure/portable/IAR/ARM_CM23_NTZ/mpu_wrappers_v2_asm.S +++ b/Source/portable/ARMv8M/non_secure/portable/IAR/ARM_CM23_NTZ/mpu_wrappers_v2_asm.S @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -207,21 +207,6 @@ MPU_uxTaskGetNumberOfTasks: svc #SYSTEM_CALL_uxTaskGetNumberOfTasks /*-----------------------------------------------------------*/ - PUBLIC MPU_pcTaskGetName -MPU_pcTaskGetName: - push {r0, r1} - mrs r0, control - movs r1, #1 - tst r0, r1 - bne MPU_pcTaskGetName_Unpriv - MPU_pcTaskGetName_Priv: - pop {r0, r1} - b MPU_pcTaskGetNameImpl - MPU_pcTaskGetName_Unpriv: - pop {r0, r1} - svc #SYSTEM_CALL_pcTaskGetName -/*-----------------------------------------------------------*/ - PUBLIC MPU_ulTaskGetRunTimeCounter MPU_ulTaskGetRunTimeCounter: push {r0, r1} @@ -792,25 +777,19 @@ MPU_xTimerGetTimerDaemonTaskHandle: svc #SYSTEM_CALL_xTimerGetTimerDaemonTaskHandle /*-----------------------------------------------------------*/ - PUBLIC MPU_xTimerGenericCommandEntry -MPU_xTimerGenericCommandEntry: + PUBLIC MPU_xTimerGenericCommandFromTaskEntry +MPU_xTimerGenericCommandFromTaskEntry: push {r0, r1} - /* This function can be called from ISR also and therefore, we need a check - * to take privileged path, if called from ISR. */ - mrs r0, ipsr - cmp r0, #0 - bne MPU_xTimerGenericCommand_Priv mrs r0, control movs r1, #1 tst r0, r1 - beq MPU_xTimerGenericCommand_Priv - MPU_xTimerGenericCommand_Unpriv: + bne MPU_xTimerGenericCommandFromTask_Unpriv + MPU_xTimerGenericCommandFromTask_Priv: pop {r0, r1} - svc #SYSTEM_CALL_xTimerGenericCommand - MPU_xTimerGenericCommand_Priv: + b MPU_xTimerGenericCommandFromTaskImpl + MPU_xTimerGenericCommandFromTask_Unpriv: pop {r0, r1} - b MPU_xTimerGenericCommandPrivImpl - + svc #SYSTEM_CALL_xTimerGenericCommandFromTask /*-----------------------------------------------------------*/ PUBLIC MPU_pcTimerGetName @@ -1160,10 +1139,6 @@ MPU_xTaskGetTickCountImpl: MPU_uxTaskGetNumberOfTasksImpl: b MPU_uxTaskGetNumberOfTasksImpl - PUBWEAK MPU_pcTaskGetNameImpl -MPU_pcTaskGetNameImpl: - b MPU_pcTaskGetNameImpl - PUBWEAK MPU_ulTaskGetRunTimeCounterImpl MPU_ulTaskGetRunTimeCounterImpl: b MPU_ulTaskGetRunTimeCounterImpl @@ -1316,9 +1291,9 @@ MPU_xTimerIsTimerActiveImpl: MPU_xTimerGetTimerDaemonTaskHandleImpl: b MPU_xTimerGetTimerDaemonTaskHandleImpl - PUBWEAK MPU_xTimerGenericCommandPrivImpl -MPU_xTimerGenericCommandPrivImpl: - b MPU_xTimerGenericCommandPrivImpl + PUBWEAK MPU_xTimerGenericCommandFromTaskImpl +MPU_xTimerGenericCommandFromTaskImpl: + b MPU_xTimerGenericCommandFromTaskImpl PUBWEAK MPU_pcTimerGetNameImpl MPU_pcTimerGetNameImpl: diff --git a/Source/portable/ARMv8M/non_secure/portable/IAR/ARM_CM23_NTZ/portasm.s b/Source/portable/ARMv8M/non_secure/portable/IAR/ARM_CM23_NTZ/portasm.s index cef6b8a66..78a97a558 100644 --- a/Source/portable/ARMv8M/non_secure/portable/IAR/ARM_CM23_NTZ/portasm.s +++ b/Source/portable/ARMv8M/non_secure/portable/IAR/ARM_CM23_NTZ/portasm.s @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -39,6 +39,10 @@ files (__ICCARM__ is defined by the IAR C compiler but not by the IAR assembler. #define configUSE_MPU_WRAPPERS_V1 0 #endif +#ifndef configRUN_FREERTOS_SECURE_ONLY + #define configRUN_FREERTOS_SECURE_ONLY 0 +#endif + EXTERN pxCurrentTCB EXTERN vTaskSwitchContext EXTERN vPortSVCHandler_C @@ -159,7 +163,9 @@ vRestoreContextOfFirstTask: ldmia r1!, {r2-r5} /* r2 = original PSP, r3 = PSPLIM, r4 = CONTROL, r5 = LR. */ subs r1, #16 msr psp, r2 + #if ( configRUN_FREERTOS_SECURE_ONLY == 1 ) msr psplim, r3 + #endif msr control, r4 mov lr, r5 @@ -191,7 +197,9 @@ vRestoreContextOfFirstTask: ldr r0, [r1] /* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */ ldm r0!, {r1-r2} /* Read from stack - r1 = PSPLIM and r2 = EXC_RETURN. */ +#if ( configRUN_FREERTOS_SECURE_ONLY == 1 ) msr psplim, r1 /* Set this task's PSPLIM value. */ +#endif movs r1, #2 /* r1 = 2. */ msr CONTROL, r1 /* Switch to use PSP in the thread mode. */ adds r0, #32 /* Discard everything up to r0. */ @@ -255,7 +263,11 @@ PendSV_Handler: save_special_regs: mrs r2, psp /* r2 = PSP. */ + #if ( configRUN_FREERTOS_SECURE_ONLY == 1 ) mrs r3, psplim /* r3 = PSPLIM. */ + #else + movs r3, #0 /* r3 = 0. 0 is stored in the PSPLIM slot. */ + #endif mrs r4, control /* r4 = CONTROL. */ mov r5, lr /* r5 = LR. */ stmia r1!, {r2-r5} /* Store original PSP (after hardware has saved context), PSPLIM, CONTROL and LR. */ @@ -323,7 +335,9 @@ PendSV_Handler: ldmia r1!, {r2-r5} /* r2 = original PSP, r3 = PSPLIM, r4 = CONTROL, r5 = LR. */ subs r1, #16 msr psp, r2 + #if ( configRUN_FREERTOS_SECURE_ONLY == 1 ) msr psplim, r3 + #endif msr control, r4 mov lr, r5 @@ -356,7 +370,11 @@ PendSV_Handler: subs r0, r0, #40 /* Make space for PSPLIM, LR and the remaining registers on the stack. */ str r0, [r1] /* Save the new top of stack in TCB. */ +#if ( configRUN_FREERTOS_SECURE_ONLY == 1 ) mrs r2, psplim /* r2 = PSPLIM. */ +#else + movs r2, #0 /* r0 = 0. 0 is stored in the PSPLIM slot. */ +#endif mov r3, lr /* r3 = LR/EXC_RETURN. */ stmia r0!, {r2-r7} /* Store on the stack - PSPLIM, LR and low registers that are not automatically saved. */ mov r4, r8 /* r4 = r8. */ @@ -382,7 +400,9 @@ PendSV_Handler: msr psp, r0 /* Remember the new top of stack for the task. */ subs r0, r0, #40 /* Move to the starting of the saved context. */ ldmia r0!, {r2-r7} /* Read from stack - r2 = PSPLIM, r3 = LR and r4-r7 restored. */ +#if ( configRUN_FREERTOS_SECURE_ONLY == 1 ) msr psplim, r2 /* Restore the PSPLIM register value for the task. */ +#endif bx r3 #endif /* configENABLE_MPU */ diff --git a/Source/portable/ARMv8M/non_secure/portable/IAR/ARM_CM23_NTZ/portmacro.h b/Source/portable/ARMv8M/non_secure/portable/IAR/ARM_CM23_NTZ/portmacro.h index 19d7556fb..52ab2a3ac 100644 --- a/Source/portable/ARMv8M/non_secure/portable/IAR/ARM_CM23_NTZ/portmacro.h +++ b/Source/portable/ARMv8M/non_secure/portable/IAR/ARM_CM23_NTZ/portmacro.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -48,9 +48,9 @@ /** * Architecture specifics. */ -#define portARCH_NAME "Cortex-M23" -#define portHAS_BASEPRI 0 -#define portDONT_DISCARD __root +#define portARCH_NAME "Cortex-M23" +#define portHAS_ARMV8M_MAIN_EXTENSION 0 +#define portDONT_DISCARD __root /*-----------------------------------------------------------*/ /* ARMv8-M common port configurations. */ diff --git a/Source/portable/ARMv8M/non_secure/portable/IAR/ARM_CM33/mpu_wrappers_v2_asm.S b/Source/portable/ARMv8M/non_secure/portable/IAR/ARM_CM33/mpu_wrappers_v2_asm.S index ef180bd91..b4f1fbc3b 100644 --- a/Source/portable/ARMv8M/non_secure/portable/IAR/ARM_CM33/mpu_wrappers_v2_asm.S +++ b/Source/portable/ARMv8M/non_secure/portable/IAR/ARM_CM33/mpu_wrappers_v2_asm.S @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -196,20 +196,6 @@ MPU_uxTaskGetNumberOfTasks: svc #SYSTEM_CALL_uxTaskGetNumberOfTasks /*-----------------------------------------------------------*/ - PUBLIC MPU_pcTaskGetName -MPU_pcTaskGetName: - push {r0} - mrs r0, control - tst r0, #1 - bne MPU_pcTaskGetName_Unpriv - MPU_pcTaskGetName_Priv: - pop {r0} - b MPU_pcTaskGetNameImpl - MPU_pcTaskGetName_Unpriv: - pop {r0} - svc #SYSTEM_CALL_pcTaskGetName -/*-----------------------------------------------------------*/ - PUBLIC MPU_ulTaskGetRunTimeCounter MPU_ulTaskGetRunTimeCounter: push {r0} @@ -742,24 +728,18 @@ MPU_xTimerGetTimerDaemonTaskHandle: svc #SYSTEM_CALL_xTimerGetTimerDaemonTaskHandle /*-----------------------------------------------------------*/ - PUBLIC MPU_xTimerGenericCommandEntry -MPU_xTimerGenericCommandEntry: + PUBLIC MPU_xTimerGenericCommandFromTaskEntry +MPU_xTimerGenericCommandFromTaskEntry: push {r0} - /* This function can be called from ISR also and therefore, we need a check - * to take privileged path, if called from ISR. */ - mrs r0, ipsr - cmp r0, #0 - bne MPU_xTimerGenericCommand_Priv mrs r0, control tst r0, #1 - beq MPU_xTimerGenericCommand_Priv - MPU_xTimerGenericCommand_Unpriv: + bne MPU_xTimerGenericCommandFromTask_Unpriv + MPU_xTimerGenericCommandFromTask_Priv: pop {r0} - svc #SYSTEM_CALL_xTimerGenericCommand - MPU_xTimerGenericCommand_Priv: + b MPU_xTimerGenericCommandFromTaskImpl + MPU_xTimerGenericCommandFromTask_Unpriv: pop {r0} - b MPU_xTimerGenericCommandPrivImpl - + svc #SYSTEM_CALL_xTimerGenericCommandFromTask /*-----------------------------------------------------------*/ PUBLIC MPU_pcTimerGetName @@ -1089,10 +1069,6 @@ MPU_xTaskGetTickCountImpl: MPU_uxTaskGetNumberOfTasksImpl: b MPU_uxTaskGetNumberOfTasksImpl - PUBWEAK MPU_pcTaskGetNameImpl -MPU_pcTaskGetNameImpl: - b MPU_pcTaskGetNameImpl - PUBWEAK MPU_ulTaskGetRunTimeCounterImpl MPU_ulTaskGetRunTimeCounterImpl: b MPU_ulTaskGetRunTimeCounterImpl @@ -1245,9 +1221,9 @@ MPU_xTimerIsTimerActiveImpl: MPU_xTimerGetTimerDaemonTaskHandleImpl: b MPU_xTimerGetTimerDaemonTaskHandleImpl - PUBWEAK MPU_xTimerGenericCommandPrivImpl -MPU_xTimerGenericCommandPrivImpl: - b MPU_xTimerGenericCommandPrivImpl + PUBWEAK MPU_xTimerGenericCommandFromTaskImpl +MPU_xTimerGenericCommandFromTaskImpl: + b MPU_xTimerGenericCommandFromTaskImpl PUBWEAK MPU_pcTimerGetNameImpl MPU_pcTimerGetNameImpl: diff --git a/Source/portable/ARMv8M/non_secure/portable/IAR/ARM_CM33/portasm.s b/Source/portable/ARMv8M/non_secure/portable/IAR/ARM_CM33/portasm.s index 530910341..6a6b677bf 100644 --- a/Source/portable/ARMv8M/non_secure/portable/IAR/ARM_CM33/portasm.s +++ b/Source/portable/ARMv8M/non_secure/portable/IAR/ARM_CM33/portasm.s @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/Source/portable/ARMv8M/non_secure/portable/IAR/ARM_CM33/portmacro.h b/Source/portable/ARMv8M/non_secure/portable/IAR/ARM_CM33/portmacro.h index 5afc234c1..ece523f2b 100644 --- a/Source/portable/ARMv8M/non_secure/portable/IAR/ARM_CM33/portmacro.h +++ b/Source/portable/ARMv8M/non_secure/portable/IAR/ARM_CM33/portmacro.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -48,12 +48,12 @@ /** * Architecture specifics. */ -#define portARCH_NAME "Cortex-M33" -#define portHAS_BASEPRI 1 -#define portDONT_DISCARD __root +#define portARCH_NAME "Cortex-M33" +#define portHAS_ARMV8M_MAIN_EXTENSION 1 +#define portDONT_DISCARD __root /*-----------------------------------------------------------*/ -#if( configTOTAL_MPU_REGIONS == 16 ) +#if ( configTOTAL_MPU_REGIONS == 16 ) #error 16 MPU regions are not yet supported for this port. #endif /*-----------------------------------------------------------*/ @@ -65,8 +65,8 @@ /** * @brief Critical section management. */ -#define portDISABLE_INTERRUPTS() ulSetInterruptMask() -#define portENABLE_INTERRUPTS() vClearInterruptMask( 0 ) +#define portDISABLE_INTERRUPTS() ulSetInterruptMask() +#define portENABLE_INTERRUPTS() vClearInterruptMask( 0 ) /*-----------------------------------------------------------*/ /* Suppress warnings that are generated by the IAR tools, but cannot be fixed in diff --git a/Source/portable/ARMv8M/non_secure/portable/IAR/ARM_CM33_NTZ/mpu_wrappers_v2_asm.S b/Source/portable/ARMv8M/non_secure/portable/IAR/ARM_CM33_NTZ/mpu_wrappers_v2_asm.S index ef180bd91..b4f1fbc3b 100644 --- a/Source/portable/ARMv8M/non_secure/portable/IAR/ARM_CM33_NTZ/mpu_wrappers_v2_asm.S +++ b/Source/portable/ARMv8M/non_secure/portable/IAR/ARM_CM33_NTZ/mpu_wrappers_v2_asm.S @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -196,20 +196,6 @@ MPU_uxTaskGetNumberOfTasks: svc #SYSTEM_CALL_uxTaskGetNumberOfTasks /*-----------------------------------------------------------*/ - PUBLIC MPU_pcTaskGetName -MPU_pcTaskGetName: - push {r0} - mrs r0, control - tst r0, #1 - bne MPU_pcTaskGetName_Unpriv - MPU_pcTaskGetName_Priv: - pop {r0} - b MPU_pcTaskGetNameImpl - MPU_pcTaskGetName_Unpriv: - pop {r0} - svc #SYSTEM_CALL_pcTaskGetName -/*-----------------------------------------------------------*/ - PUBLIC MPU_ulTaskGetRunTimeCounter MPU_ulTaskGetRunTimeCounter: push {r0} @@ -742,24 +728,18 @@ MPU_xTimerGetTimerDaemonTaskHandle: svc #SYSTEM_CALL_xTimerGetTimerDaemonTaskHandle /*-----------------------------------------------------------*/ - PUBLIC MPU_xTimerGenericCommandEntry -MPU_xTimerGenericCommandEntry: + PUBLIC MPU_xTimerGenericCommandFromTaskEntry +MPU_xTimerGenericCommandFromTaskEntry: push {r0} - /* This function can be called from ISR also and therefore, we need a check - * to take privileged path, if called from ISR. */ - mrs r0, ipsr - cmp r0, #0 - bne MPU_xTimerGenericCommand_Priv mrs r0, control tst r0, #1 - beq MPU_xTimerGenericCommand_Priv - MPU_xTimerGenericCommand_Unpriv: + bne MPU_xTimerGenericCommandFromTask_Unpriv + MPU_xTimerGenericCommandFromTask_Priv: pop {r0} - svc #SYSTEM_CALL_xTimerGenericCommand - MPU_xTimerGenericCommand_Priv: + b MPU_xTimerGenericCommandFromTaskImpl + MPU_xTimerGenericCommandFromTask_Unpriv: pop {r0} - b MPU_xTimerGenericCommandPrivImpl - + svc #SYSTEM_CALL_xTimerGenericCommandFromTask /*-----------------------------------------------------------*/ PUBLIC MPU_pcTimerGetName @@ -1089,10 +1069,6 @@ MPU_xTaskGetTickCountImpl: MPU_uxTaskGetNumberOfTasksImpl: b MPU_uxTaskGetNumberOfTasksImpl - PUBWEAK MPU_pcTaskGetNameImpl -MPU_pcTaskGetNameImpl: - b MPU_pcTaskGetNameImpl - PUBWEAK MPU_ulTaskGetRunTimeCounterImpl MPU_ulTaskGetRunTimeCounterImpl: b MPU_ulTaskGetRunTimeCounterImpl @@ -1245,9 +1221,9 @@ MPU_xTimerIsTimerActiveImpl: MPU_xTimerGetTimerDaemonTaskHandleImpl: b MPU_xTimerGetTimerDaemonTaskHandleImpl - PUBWEAK MPU_xTimerGenericCommandPrivImpl -MPU_xTimerGenericCommandPrivImpl: - b MPU_xTimerGenericCommandPrivImpl + PUBWEAK MPU_xTimerGenericCommandFromTaskImpl +MPU_xTimerGenericCommandFromTaskImpl: + b MPU_xTimerGenericCommandFromTaskImpl PUBWEAK MPU_pcTimerGetNameImpl MPU_pcTimerGetNameImpl: diff --git a/Source/portable/ARMv8M/non_secure/portable/IAR/ARM_CM33_NTZ/portasm.s b/Source/portable/ARMv8M/non_secure/portable/IAR/ARM_CM33_NTZ/portasm.s index 00ee5a5cb..cb3ad91f9 100644 --- a/Source/portable/ARMv8M/non_secure/portable/IAR/ARM_CM33_NTZ/portasm.s +++ b/Source/portable/ARMv8M/non_secure/portable/IAR/ARM_CM33_NTZ/portasm.s @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/Source/portable/ARMv8M/non_secure/portable/IAR/ARM_CM33_NTZ/portmacro.h b/Source/portable/ARMv8M/non_secure/portable/IAR/ARM_CM33_NTZ/portmacro.h index 84e86d9f9..5f81b5fe8 100644 --- a/Source/portable/ARMv8M/non_secure/portable/IAR/ARM_CM33_NTZ/portmacro.h +++ b/Source/portable/ARMv8M/non_secure/portable/IAR/ARM_CM33_NTZ/portmacro.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -48,16 +48,16 @@ /** * Architecture specifics. */ -#define portARCH_NAME "Cortex-M33" -#define portHAS_BASEPRI 1 -#define portDONT_DISCARD __root +#define portARCH_NAME "Cortex-M33" +#define portHAS_ARMV8M_MAIN_EXTENSION 1 +#define portDONT_DISCARD __root /*-----------------------------------------------------------*/ /* ARMv8-M common port configurations. */ #include "portmacrocommon.h" /*-----------------------------------------------------------*/ -#if( configTOTAL_MPU_REGIONS == 16 ) +#if ( configTOTAL_MPU_REGIONS == 16 ) #error 16 MPU regions are not yet supported for this port. #endif /*-----------------------------------------------------------*/ @@ -65,8 +65,8 @@ /** * @brief Critical section management. */ -#define portDISABLE_INTERRUPTS() ulSetInterruptMask() -#define portENABLE_INTERRUPTS() vClearInterruptMask( 0 ) +#define portDISABLE_INTERRUPTS() ulSetInterruptMask() +#define portENABLE_INTERRUPTS() vClearInterruptMask( 0 ) /*-----------------------------------------------------------*/ /* Suppress warnings that are generated by the IAR tools, but cannot be fixed in diff --git a/Source/portable/ARMv8M/non_secure/portable/IAR/ARM_CM35P/portmacro.h b/Source/portable/ARMv8M/non_secure/portable/IAR/ARM_CM35P/portmacro.h index 247468478..e24fabc75 100644 --- a/Source/portable/ARMv8M/non_secure/portable/IAR/ARM_CM35P/portmacro.h +++ b/Source/portable/ARMv8M/non_secure/portable/IAR/ARM_CM35P/portmacro.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -48,16 +48,16 @@ /** * Architecture specifics. */ -#define portARCH_NAME "Cortex-M35P" -#define portHAS_BASEPRI 1 -#define portDONT_DISCARD __root +#define portARCH_NAME "Cortex-M35P" +#define portHAS_ARMV8M_MAIN_EXTENSION 1 +#define portDONT_DISCARD __root /*-----------------------------------------------------------*/ /* ARMv8-M common port configurations. */ #include "portmacrocommon.h" /*-----------------------------------------------------------*/ -#if( configTOTAL_MPU_REGIONS == 16 ) +#if ( configTOTAL_MPU_REGIONS == 16 ) #error 16 MPU regions are not yet supported for this port. #endif /*-----------------------------------------------------------*/ @@ -65,8 +65,8 @@ /** * @brief Critical section management. */ -#define portDISABLE_INTERRUPTS() ulSetInterruptMask() -#define portENABLE_INTERRUPTS() vClearInterruptMask( 0 ) +#define portDISABLE_INTERRUPTS() ulSetInterruptMask() +#define portENABLE_INTERRUPTS() vClearInterruptMask( 0 ) /*-----------------------------------------------------------*/ /* Suppress warnings that are generated by the IAR tools, but cannot be fixed in diff --git a/Source/portable/ARMv8M/non_secure/portable/IAR/ARM_CM55/portmacro.h b/Source/portable/ARMv8M/non_secure/portable/IAR/ARM_CM55/portmacro.h index d8d08f155..771a1bb3d 100644 --- a/Source/portable/ARMv8M/non_secure/portable/IAR/ARM_CM55/portmacro.h +++ b/Source/portable/ARMv8M/non_secure/portable/IAR/ARM_CM55/portmacro.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -53,16 +53,16 @@ /** * Architecture specifics. */ -#define portARCH_NAME "Cortex-M55" -#define portHAS_BASEPRI 1 -#define portDONT_DISCARD __root +#define portARCH_NAME "Cortex-M55" +#define portHAS_ARMV8M_MAIN_EXTENSION 1 +#define portDONT_DISCARD __root /*-----------------------------------------------------------*/ /* ARMv8-M common port configurations. */ #include "portmacrocommon.h" /*-----------------------------------------------------------*/ -#if( configTOTAL_MPU_REGIONS == 16 ) +#if ( configTOTAL_MPU_REGIONS == 16 ) #error 16 MPU regions are not yet supported for this port. #endif /*-----------------------------------------------------------*/ @@ -70,8 +70,8 @@ /** * @brief Critical section management. */ -#define portDISABLE_INTERRUPTS() ulSetInterruptMask() -#define portENABLE_INTERRUPTS() vClearInterruptMask( 0 ) +#define portDISABLE_INTERRUPTS() ulSetInterruptMask() +#define portENABLE_INTERRUPTS() vClearInterruptMask( 0 ) /*-----------------------------------------------------------*/ /* Suppress warnings that are generated by the IAR tools, but cannot be fixed in diff --git a/Source/portable/ARMv8M/non_secure/portable/IAR/ARM_CM85/portmacro.h b/Source/portable/ARMv8M/non_secure/portable/IAR/ARM_CM85/portmacro.h index 4f7cf2bc0..024ce2b15 100644 --- a/Source/portable/ARMv8M/non_secure/portable/IAR/ARM_CM85/portmacro.h +++ b/Source/portable/ARMv8M/non_secure/portable/IAR/ARM_CM85/portmacro.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -53,16 +53,16 @@ /** * Architecture specifics. */ -#define portARCH_NAME "Cortex-M85" -#define portHAS_BASEPRI 1 -#define portDONT_DISCARD __root +#define portARCH_NAME "Cortex-M85" +#define portHAS_ARMV8M_MAIN_EXTENSION 1 +#define portDONT_DISCARD __root /*-----------------------------------------------------------*/ /* ARMv8-M common port configurations. */ #include "portmacrocommon.h" /*-----------------------------------------------------------*/ -#if( configTOTAL_MPU_REGIONS == 16 ) +#if ( configTOTAL_MPU_REGIONS == 16 ) #error 16 MPU regions are not yet supported for this port. #endif /*-----------------------------------------------------------*/ @@ -70,8 +70,8 @@ /** * @brief Critical section management. */ -#define portDISABLE_INTERRUPTS() ulSetInterruptMask() -#define portENABLE_INTERRUPTS() vClearInterruptMask( 0 ) +#define portDISABLE_INTERRUPTS() ulSetInterruptMask() +#define portENABLE_INTERRUPTS() vClearInterruptMask( 0 ) /*-----------------------------------------------------------*/ /* Suppress warnings that are generated by the IAR tools, but cannot be fixed in diff --git a/Source/portable/ARMv8M/non_secure/portasm.h b/Source/portable/ARMv8M/non_secure/portasm.h index f64ceb525..c6d2ebd58 100644 --- a/Source/portable/ARMv8M/non_secure/portasm.h +++ b/Source/portable/ARMv8M/non_secure/portasm.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/Source/portable/ARMv8M/non_secure/portmacrocommon.h b/Source/portable/ARMv8M/non_secure/portmacrocommon.h index 6f666da22..33f21d85b 100644 --- a/Source/portable/ARMv8M/non_secure/portmacrocommon.h +++ b/Source/portable/ARMv8M/non_secure/portmacrocommon.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -117,7 +117,7 @@ extern uint32_t ulSetInterruptMask( void ) /* __attribute__(( naked )) PRIVILEGE extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */; #if ( configENABLE_TRUSTZONE == 1 ) - extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize ); /* __attribute__ (( naked )) */ + extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize ); /* __attribute__ (( naked )) */ extern void vPortFreeSecureContext( uint32_t * pulTCB ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */; #endif /* configENABLE_TRUSTZONE */ @@ -188,13 +188,13 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P #if ( configENABLE_MPU == 1 ) - /** - * @brief Settings to define an MPU region. - */ +/** + * @brief Settings to define an MPU region. + */ typedef struct MPURegionSettings { - uint32_t ulRBAR; /**< RBAR for the region. */ - uint32_t ulRLAR; /**< RLAR for the region. */ + uint32_t ulRBAR; /**< RBAR for the region. */ + uint32_t ulRLAR; /**< RLAR for the region. */ } MPURegionSettings_t; #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) @@ -203,9 +203,9 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P #error configSYSTEM_CALL_STACK_SIZE must be defined to the desired size of the system call stack in words for using MPU wrappers v2. #endif - /** - * @brief System call stack. - */ +/** + * @brief System call stack. + */ typedef struct SYSTEM_CALL_STACK_INFO { uint32_t ulSystemCallStackBuffer[ configSYSTEM_CALL_STACK_SIZE ]; @@ -218,74 +218,74 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P #endif /* configUSE_MPU_WRAPPERS_V1 == 0 */ - /** - * @brief MPU settings as stored in the TCB. - */ +/** + * @brief MPU settings as stored in the TCB. + */ #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) - #if( configENABLE_TRUSTZONE == 1 ) + #if ( configENABLE_TRUSTZONE == 1 ) - /* - * +-----------+---------------+----------+-----------------+------------------------------+-----+ - * | s16-s31 | s0-s15, FPSCR | r4-r11 | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, | | - * | | | | PC, xPSR | CONTROL, EXC_RETURN | | - * +-----------+---------------+----------+-----------------+------------------------------+-----+ - * - * <-----------><--------------><---------><----------------><-----------------------------><----> - * 16 16 8 8 5 1 - */ - #define MAX_CONTEXT_SIZE 54 +/* + * +-----------+---------------+----------+-----------------+------------------------------+-----+ + * | s16-s31 | s0-s15, FPSCR | r4-r11 | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, | | + * | | | | PC, xPSR | CONTROL, EXC_RETURN | | + * +-----------+---------------+----------+-----------------+------------------------------+-----+ + * + * <-----------><--------------><---------><----------------><-----------------------------><----> + * 16 16 8 8 5 1 + */ + #define MAX_CONTEXT_SIZE 54 #else /* #if( configENABLE_TRUSTZONE == 1 ) */ - /* - * +-----------+---------------+----------+-----------------+----------------------+-----+ - * | s16-s31 | s0-s15, FPSCR | r4-r11 | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL | | - * | | | | PC, xPSR | EXC_RETURN | | - * +-----------+---------------+----------+-----------------+----------------------+-----+ - * - * <-----------><--------------><---------><----------------><---------------------><----> - * 16 16 8 8 4 1 - */ - #define MAX_CONTEXT_SIZE 53 +/* + * +-----------+---------------+----------+-----------------+----------------------+-----+ + * | s16-s31 | s0-s15, FPSCR | r4-r11 | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL | | + * | | | | PC, xPSR | EXC_RETURN | | + * +-----------+---------------+----------+-----------------+----------------------+-----+ + * + * <-----------><--------------><---------><----------------><---------------------><----> + * 16 16 8 8 4 1 + */ + #define MAX_CONTEXT_SIZE 53 #endif /* #if( configENABLE_TRUSTZONE == 1 ) */ #else /* #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */ - #if( configENABLE_TRUSTZONE == 1 ) + #if ( configENABLE_TRUSTZONE == 1 ) - /* - * +----------+-----------------+------------------------------+-----+ - * | r4-r11 | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, | | - * | | PC, xPSR | CONTROL, EXC_RETURN | | - * +----------+-----------------+------------------------------+-----+ - * - * <---------><----------------><------------------------------><----> - * 8 8 5 1 - */ - #define MAX_CONTEXT_SIZE 22 +/* + * +----------+-----------------+------------------------------+-----+ + * | r4-r11 | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, | | + * | | PC, xPSR | CONTROL, EXC_RETURN | | + * +----------+-----------------+------------------------------+-----+ + * + * <---------><----------------><------------------------------><----> + * 8 8 5 1 + */ + #define MAX_CONTEXT_SIZE 22 #else /* #if( configENABLE_TRUSTZONE == 1 ) */ - /* - * +----------+-----------------+----------------------+-----+ - * | r4-r11 | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL | | - * | | PC, xPSR | EXC_RETURN | | - * +----------+-----------------+----------------------+-----+ - * - * <---------><----------------><----------------------><----> - * 8 8 4 1 - */ - #define MAX_CONTEXT_SIZE 21 +/* + * +----------+-----------------+----------------------+-----+ + * | r4-r11 | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL | | + * | | PC, xPSR | EXC_RETURN | | + * +----------+-----------------+----------------------+-----+ + * + * <---------><----------------><----------------------><----> + * 8 8 4 1 + */ + #define MAX_CONTEXT_SIZE 21 #endif /* #if( configENABLE_TRUSTZONE == 1 ) */ #endif /* #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */ - /* Flags used for xMPU_SETTINGS.ulTaskFlags member. */ - #define portSTACK_FRAME_HAS_PADDING_FLAG ( 1UL << 0UL ) - #define portTASK_IS_PRIVILEGED_FLAG ( 1UL << 1UL ) +/* Flags used for xMPU_SETTINGS.ulTaskFlags member. */ + #define portSTACK_FRAME_HAS_PADDING_FLAG ( 1UL << 0UL ) + #define portTASK_IS_PRIVILEGED_FLAG ( 1UL << 1UL ) /* Size of an Access Control List (ACL) entry in bits. */ #define portACL_ENTRY_SIZE_BITS ( 32U ) @@ -313,7 +313,7 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P * system calls. */ #ifdef configASSERT - #if ( portHAS_BASEPRI == 1 ) + #if ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) void vPortValidateInterruptPriority( void ); #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() vPortValidateInterruptPriority() #endif @@ -333,12 +333,29 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P /** * @brief Scheduler utilities. */ -#define portYIELD() vPortYield() +#if ( configENABLE_MPU == 1 ) + #define portYIELD() __asm volatile ( "svc %0" ::"i" ( portSVC_YIELD ) : "memory" ) + #define portYIELD_WITHIN_API() vPortYield() +#else + #define portYIELD() vPortYield() + #define portYIELD_WITHIN_API() vPortYield() +#endif + #define portNVIC_INT_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed04 ) ) #define portNVIC_PENDSVSET_BIT ( 1UL << 28UL ) -#define portEND_SWITCHING_ISR( xSwitchRequired ) \ - do { if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; } \ - while( 0 ) +#define portEND_SWITCHING_ISR( xSwitchRequired ) \ + do \ + { \ + if( xSwitchRequired ) \ + { \ + traceISR_EXIT_TO_SCHEDULER(); \ + portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; \ + } \ + else \ + { \ + traceISR_EXIT(); \ + } \ + } while( 0 ) #define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x ) /*-----------------------------------------------------------*/ @@ -424,12 +441,12 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P extern BaseType_t xPortIsTaskPrivileged( void ); - /** - * @brief Checks whether or not the calling task is privileged. - * - * @return pdTRUE if the calling task is privileged, pdFALSE otherwise. - */ - #define portIS_TASK_PRIVILEGED() xPortIsTaskPrivileged() +/** + * @brief Checks whether or not the calling task is privileged. + * + * @return pdTRUE if the calling task is privileged, pdFALSE otherwise. + */ + #define portIS_TASK_PRIVILEGED() xPortIsTaskPrivileged() #endif /* configENABLE_MPU == 1 */ /*-----------------------------------------------------------*/ @@ -440,6 +457,56 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P #define portMEMORY_BARRIER() __asm volatile ( "" ::: "memory" ) /*-----------------------------------------------------------*/ +/* Select correct value of configUSE_PORT_OPTIMISED_TASK_SELECTION + * based on whether or not Mainline extension is implemented. */ +#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION + #if ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) + #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1 + #else + #define configUSE_PORT_OPTIMISED_TASK_SELECTION 0 + #endif +#endif /* #ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION */ + +/** + * @brief Port-optimised task selection. + */ +#if ( configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 ) + +/** + * @brief Count the number of leading zeros in a 32-bit value. + */ + static portFORCE_INLINE uint32_t ulPortCountLeadingZeros( uint32_t ulBitmap ) + { + uint32_t ulReturn; + + __asm volatile ( "clz %0, %1" : "=r" ( ulReturn ) : "r" ( ulBitmap ) : "memory" ); + + return ulReturn; + } + +/* Check the configuration. */ + #if ( configMAX_PRIORITIES > 32 ) + #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 different priorities as tasks that share a priority will time slice. + #endif + + #if ( portHAS_ARMV8M_MAIN_EXTENSION == 0 ) + #error ARMv8-M baseline implementations (such as Cortex-M23) do not support port-optimised task selection. Please set configUSE_PORT_OPTIMISED_TASK_SELECTION to 0 or leave it undefined. + #endif + +/** + * @brief Store/clear the ready priorities in a bit map. + */ + #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) ) + #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) ) + +/** + * @brief Get the priority of the highest-priority task that is ready to execute. + */ + #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - ulPortCountLeadingZeros( ( uxReadyPriorities ) ) ) + +#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */ +/*-----------------------------------------------------------*/ + /* *INDENT-OFF* */ #ifdef __cplusplus } diff --git a/Source/portable/ARMv8M/secure/context/portable/GCC/ARM_CM23/secure_context_port.c b/Source/portable/ARMv8M/secure/context/portable/GCC/ARM_CM23/secure_context_port.c index ce3534010..dbedd29eb 100644 --- a/Source/portable/ARMv8M/secure/context/portable/GCC/ARM_CM23/secure_context_port.c +++ b/Source/portable/ARMv8M/secure/context/portable/GCC/ARM_CM23/secure_context_port.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/Source/portable/ARMv8M/secure/context/portable/GCC/ARM_CM33/secure_context_port.c b/Source/portable/ARMv8M/secure/context/portable/GCC/ARM_CM33/secure_context_port.c index d70822c06..31c1f7331 100644 --- a/Source/portable/ARMv8M/secure/context/portable/GCC/ARM_CM33/secure_context_port.c +++ b/Source/portable/ARMv8M/secure/context/portable/GCC/ARM_CM33/secure_context_port.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/Source/portable/ARMv8M/secure/context/portable/IAR/ARM_CM23/secure_context_port_asm.s b/Source/portable/ARMv8M/secure/context/portable/IAR/ARM_CM23/secure_context_port_asm.s index 1e4b3a57a..de0b495ae 100644 --- a/Source/portable/ARMv8M/secure/context/portable/IAR/ARM_CM23/secure_context_port_asm.s +++ b/Source/portable/ARMv8M/secure/context/portable/IAR/ARM_CM23/secure_context_port_asm.s @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/Source/portable/ARMv8M/secure/context/portable/IAR/ARM_CM33/secure_context_port_asm.s b/Source/portable/ARMv8M/secure/context/portable/IAR/ARM_CM33/secure_context_port_asm.s index 0da3e0f12..5124d9246 100644 --- a/Source/portable/ARMv8M/secure/context/portable/IAR/ARM_CM33/secure_context_port_asm.s +++ b/Source/portable/ARMv8M/secure/context/portable/IAR/ARM_CM33/secure_context_port_asm.s @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/Source/portable/ARMv8M/secure/context/secure_context.c b/Source/portable/ARMv8M/secure/context/secure_context.c index e37dd9672..83b3dbce1 100644 --- a/Source/portable/ARMv8M/secure/context/secure_context.c +++ b/Source/portable/ARMv8M/secure/context/secure_context.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -65,7 +65,7 @@ * @brief Maximum number of secure contexts. */ #ifndef secureconfigMAX_SECURE_CONTEXTS - #define secureconfigMAX_SECURE_CONTEXTS 8UL + #define secureconfigMAX_SECURE_CONTEXTS 8UL #endif /*-----------------------------------------------------------*/ @@ -164,15 +164,15 @@ secureportNON_SECURE_CALLABLE void SecureContext_Init( void ) } #if ( configENABLE_MPU == 1 ) - { - /* Configure thread mode to use PSP and to be unprivileged. */ - secureportSET_CONTROL( securecontextCONTROL_VALUE_UNPRIVILEGED ); - } + { + /* Configure thread mode to use PSP and to be unprivileged. */ + secureportSET_CONTROL( securecontextCONTROL_VALUE_UNPRIVILEGED ); + } #else /* configENABLE_MPU */ - { - /* Configure thread mode to use PSP and to be privileged. */ - secureportSET_CONTROL( securecontextCONTROL_VALUE_PRIVILEGED ); - } + { + /* Configure thread mode to use PSP and to be privileged. */ + secureportSET_CONTROL( securecontextCONTROL_VALUE_PRIVILEGED ); + } #endif /* configENABLE_MPU */ } } @@ -219,16 +219,16 @@ secureportNON_SECURE_CALLABLE void SecureContext_Init( void ) if( pucStackMemory != NULL ) { /* Since stack grows down, the starting point will be the last - * location. Note that this location is next to the last - * allocated byte for stack (excluding the space for seal values) - * because the hardware decrements the stack pointer before - * writing i.e. if stack pointer is 0x2, a push operation will - * decrement the stack pointer to 0x1 and then write at 0x1. */ + * location. Note that this location is next to the last + * allocated byte for stack (excluding the space for seal values) + * because the hardware decrements the stack pointer before + * writing i.e. if stack pointer is 0x2, a push operation will + * decrement the stack pointer to 0x1 and then write at 0x1. */ xSecureContexts[ ulSecureContextIndex ].pucStackStart = pucStackMemory + ulSecureStackSize; /* Seal the created secure process stack. */ - *( uint32_t * )( pucStackMemory + ulSecureStackSize ) = securecontextSTACK_SEAL_VALUE; - *( uint32_t * )( pucStackMemory + ulSecureStackSize + 4 ) = securecontextSTACK_SEAL_VALUE; + *( uint32_t * ) ( pucStackMemory + ulSecureStackSize ) = securecontextSTACK_SEAL_VALUE; + *( uint32_t * ) ( pucStackMemory + ulSecureStackSize + 4 ) = securecontextSTACK_SEAL_VALUE; /* The stack cannot go beyond this location. This value is * programmed in the PSPLIM register on context switch.*/ @@ -237,32 +237,32 @@ secureportNON_SECURE_CALLABLE void SecureContext_Init( void ) xSecureContexts[ ulSecureContextIndex ].pvTaskHandle = pvTaskHandle; #if ( configENABLE_MPU == 1 ) + { + /* Store the correct CONTROL value for the task on the stack. + * This value is programmed in the CONTROL register on + * context switch. */ + pulCurrentStackPointer = ( uint32_t * ) xSecureContexts[ ulSecureContextIndex ].pucStackStart; + pulCurrentStackPointer--; + + if( ulIsTaskPrivileged ) { - /* Store the correct CONTROL value for the task on the stack. - * This value is programmed in the CONTROL register on - * context switch. */ - pulCurrentStackPointer = ( uint32_t * ) xSecureContexts[ ulSecureContextIndex ].pucStackStart; - pulCurrentStackPointer--; - - if( ulIsTaskPrivileged ) - { - *( pulCurrentStackPointer ) = securecontextCONTROL_VALUE_PRIVILEGED; - } - else - { - *( pulCurrentStackPointer ) = securecontextCONTROL_VALUE_UNPRIVILEGED; - } - - /* Store the current stack pointer. This value is programmed in - * the PSP register on context switch. */ - xSecureContexts[ ulSecureContextIndex ].pucCurrentStackPointer = ( uint8_t * ) pulCurrentStackPointer; + *( pulCurrentStackPointer ) = securecontextCONTROL_VALUE_PRIVILEGED; } - #else /* configENABLE_MPU */ + else { - /* Current SP is set to the starting of the stack. This - * value programmed in the PSP register on context switch. */ - xSecureContexts[ ulSecureContextIndex ].pucCurrentStackPointer = xSecureContexts[ ulSecureContextIndex ].pucStackStart; + *( pulCurrentStackPointer ) = securecontextCONTROL_VALUE_UNPRIVILEGED; } + + /* Store the current stack pointer. This value is programmed in + * the PSP register on context switch. */ + xSecureContexts[ ulSecureContextIndex ].pucCurrentStackPointer = ( uint8_t * ) pulCurrentStackPointer; + } + #else /* configENABLE_MPU */ + { + /* Current SP is set to the starting of the stack. This + * value programmed in the PSP register on context switch. */ + xSecureContexts[ ulSecureContextIndex ].pucCurrentStackPointer = xSecureContexts[ ulSecureContextIndex ].pucStackStart; + } #endif /* configENABLE_MPU */ /* Ensure to never return 0 as a valid context handle. */ @@ -275,7 +275,8 @@ secureportNON_SECURE_CALLABLE void SecureContext_Init( void ) } /*-----------------------------------------------------------*/ -secureportNON_SECURE_CALLABLE void SecureContext_FreeContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle ) +secureportNON_SECURE_CALLABLE void SecureContext_FreeContext( SecureContextHandle_t xSecureContextHandle, + void * pvTaskHandle ) { uint32_t ulIPSR, ulSecureContextIndex; @@ -306,7 +307,8 @@ secureportNON_SECURE_CALLABLE void SecureContext_FreeContext( SecureContextHandl } /*-----------------------------------------------------------*/ -secureportNON_SECURE_CALLABLE void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle ) +secureportNON_SECURE_CALLABLE void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle, + void * pvTaskHandle ) { uint8_t * pucStackLimit; uint32_t ulSecureContextIndex; @@ -328,7 +330,8 @@ secureportNON_SECURE_CALLABLE void SecureContext_LoadContext( SecureContextHandl } /*-----------------------------------------------------------*/ -secureportNON_SECURE_CALLABLE void SecureContext_SaveContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle ) +secureportNON_SECURE_CALLABLE void SecureContext_SaveContext( SecureContextHandle_t xSecureContextHandle, + void * pvTaskHandle ) { uint8_t * pucStackLimit; uint32_t ulSecureContextIndex; diff --git a/Source/portable/ARMv8M/secure/context/secure_context.h b/Source/portable/ARMv8M/secure/context/secure_context.h index 2220ea646..40fdc276d 100644 --- a/Source/portable/ARMv8M/secure/context/secure_context.h +++ b/Source/portable/ARMv8M/secure/context/secure_context.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -38,12 +38,12 @@ /** * @brief PSP value when no secure context is loaded. */ -#define securecontextNO_STACK 0x0 +#define securecontextNO_STACK 0x0 /** * @brief Invalid context ID. */ -#define securecontextINVALID_CONTEXT_ID 0UL +#define securecontextINVALID_CONTEXT_ID 0UL /*-----------------------------------------------------------*/ /** @@ -108,7 +108,8 @@ void SecureContext_Init( void ); * @param[in] xSecureContextHandle Context handle corresponding to the * context to be freed. */ -void SecureContext_FreeContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle ); +void SecureContext_FreeContext( SecureContextHandle_t xSecureContextHandle, + void * pvTaskHandle ); /** * @brief Loads the given context. @@ -119,7 +120,8 @@ void SecureContext_FreeContext( SecureContextHandle_t xSecureContextHandle, void * @param[in] xSecureContextHandle Context handle corresponding to the context * to be loaded. */ -void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle ); +void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle, + void * pvTaskHandle ); /** * @brief Saves the given context. @@ -130,6 +132,7 @@ void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle, void * @param[in] xSecureContextHandle Context handle corresponding to the context * to be saved. */ -void SecureContext_SaveContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle ); +void SecureContext_SaveContext( SecureContextHandle_t xSecureContextHandle, + void * pvTaskHandle ); #endif /* __SECURE_CONTEXT_H__ */ diff --git a/Source/portable/ARMv8M/secure/heap/secure_heap.c b/Source/portable/ARMv8M/secure/heap/secure_heap.c index 19f7c2354..d9789404b 100644 --- a/Source/portable/ARMv8M/secure/heap/secure_heap.c +++ b/Source/portable/ARMv8M/secure/heap/secure_heap.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -62,6 +62,22 @@ /* Assumes 8bit bytes! */ #define secureheapBITS_PER_BYTE ( ( size_t ) 8 ) + +/* Max value that fits in a size_t type. */ +#define secureheapSIZE_MAX ( ~( ( size_t ) 0 ) ) + +/* Check if adding a and b will result in overflow. */ +#define secureheapADD_WILL_OVERFLOW( a, b ) ( ( a ) > ( secureheapSIZE_MAX - ( b ) ) ) + +/* MSB of the xBlockSize member of an BlockLink_t structure is used to track + * the allocation status of a block. When MSB of the xBlockSize member of + * an BlockLink_t structure is set then the block belongs to the application. + * When the bit is free the block is still part of the free heap space. */ +#define secureheapBLOCK_ALLOCATED_BITMASK ( ( ( size_t ) 1 ) << ( ( sizeof( size_t ) * secureheapBITS_PER_BYTE ) - 1 ) ) +#define secureheapBLOCK_SIZE_IS_VALID( xBlockSize ) ( ( ( xBlockSize ) & secureheapBLOCK_ALLOCATED_BITMASK ) == 0 ) +#define secureheapBLOCK_IS_ALLOCATED( pxBlock ) ( ( ( pxBlock->xBlockSize ) & secureheapBLOCK_ALLOCATED_BITMASK ) != 0 ) +#define secureheapALLOCATE_BLOCK( pxBlock ) ( ( pxBlock->xBlockSize ) |= secureheapBLOCK_ALLOCATED_BITMASK ) +#define secureheapFREE_BLOCK( pxBlock ) ( ( pxBlock->xBlockSize ) &= ~secureheapBLOCK_ALLOCATED_BITMASK ) /*-----------------------------------------------------------*/ /* Allocate the memory for the heap. */ @@ -123,14 +139,6 @@ static BlockLink_t * pxEnd = NULL; static size_t xFreeBytesRemaining = 0U; static size_t xMinimumEverFreeBytesRemaining = 0U; -/** - * @brief Gets set to the top bit of an size_t type. - * - * When this bit in the xBlockSize member of an BlockLink_t structure is set - * then the block belongs to the application. When the bit is free the block is - * still part of the free heap space. - */ -static size_t xBlockAllocatedBit = 0; /*-----------------------------------------------------------*/ static void prvHeapInit( void ) @@ -175,9 +183,6 @@ static void prvHeapInit( void ) /* Only one block exists - and it covers the entire usable heap space. */ xMinimumEverFreeBytesRemaining = pxFirstFreeBlock->xBlockSize; xFreeBytesRemaining = pxFirstFreeBlock->xBlockSize; - - /* Work out the position of the top bit in a size_t variable. */ - xBlockAllocatedBit = ( ( size_t ) 1 ) << ( ( sizeof( size_t ) * secureheapBITS_PER_BYTE ) - 1 ); } /*-----------------------------------------------------------*/ @@ -250,6 +255,7 @@ void * pvPortMalloc( size_t xWantedSize ) BlockLink_t * pxPreviousBlock; BlockLink_t * pxNewBlockLink; void * pvReturn = NULL; + size_t xAdditionalRequiredSize; /* If this is the first call to malloc then the heap will require * initialisation to setup the list of free blocks. */ @@ -262,25 +268,29 @@ void * pvPortMalloc( size_t xWantedSize ) mtCOVERAGE_TEST_MARKER(); } - /* Check the requested block size is not so large that the top bit is set. - * The top bit of the block size member of the BlockLink_t structure is used - * to determine who owns the block - the application or the kernel, so it - * must be free. */ - if( ( xWantedSize & xBlockAllocatedBit ) == 0 ) + if( xWantedSize > 0 ) { - /* The wanted size is increased so it can contain a BlockLink_t + /* The wanted size must be increased so it can contain a BlockLink_t * structure in addition to the requested amount of bytes. */ - if( xWantedSize > 0 ) + if( secureheapADD_WILL_OVERFLOW( xWantedSize, xHeapStructSize ) == 0 ) { xWantedSize += xHeapStructSize; - /* Ensure that blocks are always aligned to the required number of - * bytes. */ + /* Ensure that blocks are always aligned to the required number + * of bytes. */ if( ( xWantedSize & secureportBYTE_ALIGNMENT_MASK ) != 0x00 ) { /* Byte alignment required. */ - xWantedSize += ( secureportBYTE_ALIGNMENT - ( xWantedSize & secureportBYTE_ALIGNMENT_MASK ) ); - secureportASSERT( ( xWantedSize & secureportBYTE_ALIGNMENT_MASK ) == 0 ); + xAdditionalRequiredSize = secureportBYTE_ALIGNMENT - ( xWantedSize & secureportBYTE_ALIGNMENT_MASK ); + + if( secureheapADD_WILL_OVERFLOW( xWantedSize, xAdditionalRequiredSize ) == 0 ) + { + xWantedSize += xAdditionalRequiredSize; + } + else + { + xWantedSize = 0; + } } else { @@ -289,9 +299,20 @@ void * pvPortMalloc( size_t xWantedSize ) } else { - mtCOVERAGE_TEST_MARKER(); + xWantedSize = 0; } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + /* Check the requested block size is not so large that the top bit is set. + * The top bit of the block size member of the BlockLink_t structure is used + * to determine who owns the block - the application or the kernel, so it + * must be free. */ + if( secureheapBLOCK_SIZE_IS_VALID( xWantedSize ) != 0 ) + { if( ( xWantedSize > 0 ) && ( xWantedSize <= xFreeBytesRemaining ) ) { /* Traverse the list from the start (lowest address) block until @@ -334,7 +355,8 @@ void * pvPortMalloc( size_t xWantedSize ) pxBlock->xBlockSize = xWantedSize; /* Insert the new block into the list of free blocks. */ - prvInsertBlockIntoFreeList( pxNewBlockLink ); + pxNewBlockLink->pxNextFreeBlock = pxPreviousBlock->pxNextFreeBlock; + pxPreviousBlock->pxNextFreeBlock = pxNewBlockLink; } else { @@ -354,7 +376,7 @@ void * pvPortMalloc( size_t xWantedSize ) /* The block is being returned - it is allocated and owned by * the application and has no "next" block. */ - pxBlock->xBlockSize |= xBlockAllocatedBit; + secureheapALLOCATE_BLOCK( pxBlock ); pxBlock->pxNextFreeBlock = NULL; } else @@ -375,17 +397,17 @@ void * pvPortMalloc( size_t xWantedSize ) traceMALLOC( pvReturn, xWantedSize ); #if ( secureconfigUSE_MALLOC_FAILED_HOOK == 1 ) + { + if( pvReturn == NULL ) { - if( pvReturn == NULL ) - { - extern void vApplicationMallocFailedHook( void ); - vApplicationMallocFailedHook(); - } - else - { - mtCOVERAGE_TEST_MARKER(); - } + extern void vApplicationMallocFailedHook( void ); + vApplicationMallocFailedHook(); } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } #endif /* if ( secureconfigUSE_MALLOC_FAILED_HOOK == 1 ) */ secureportASSERT( ( ( ( size_t ) pvReturn ) & ( size_t ) secureportBYTE_ALIGNMENT_MASK ) == 0 ); @@ -408,16 +430,16 @@ void vPortFree( void * pv ) pxLink = ( void * ) puc; /* Check the block is actually allocated. */ - secureportASSERT( ( pxLink->xBlockSize & xBlockAllocatedBit ) != 0 ); + secureportASSERT( secureheapBLOCK_IS_ALLOCATED( pxLink ) != 0 ); secureportASSERT( pxLink->pxNextFreeBlock == NULL ); - if( ( pxLink->xBlockSize & xBlockAllocatedBit ) != 0 ) + if( secureheapBLOCK_IS_ALLOCATED( pxLink ) != 0 ) { if( pxLink->pxNextFreeBlock == NULL ) { /* The block is being returned to the heap - it is no longer * allocated. */ - pxLink->xBlockSize &= ~xBlockAllocatedBit; + secureheapFREE_BLOCK( pxLink ); secureportDISABLE_NON_SECURE_INTERRUPTS(); { diff --git a/Source/portable/ARMv8M/secure/heap/secure_heap.h b/Source/portable/ARMv8M/secure/heap/secure_heap.h index 75c9cb00b..cf5551046 100644 --- a/Source/portable/ARMv8M/secure/heap/secure_heap.h +++ b/Source/portable/ARMv8M/secure/heap/secure_heap.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/Source/portable/ARMv8M/secure/init/secure_init.c b/Source/portable/ARMv8M/secure/init/secure_init.c index f93bfce95..66d35eccc 100644 --- a/Source/portable/ARMv8M/secure/init/secure_init.c +++ b/Source/portable/ARMv8M/secure/init/secure_init.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -93,7 +93,7 @@ secureportNON_SECURE_CALLABLE void SecureInit_EnableNSFPUAccess( void ) * permitted. CP11 should be programmed to the same value as CP10. */ *( secureinitNSACR ) |= ( secureinitNSACR_CP10_MASK | secureinitNSACR_CP11_MASK ); - /* LSPENS = 0 ==> LSPEN is writable fron non-secure state. This ensures + /* LSPENS = 0 ==> LSPEN is writable from non-secure state. This ensures * that we can enable/disable lazy stacking in port.c file. */ *( secureinitFPCCR ) &= ~( secureinitFPCCR_LSPENS_MASK ); diff --git a/Source/portable/ARMv8M/secure/init/secure_init.h b/Source/portable/ARMv8M/secure/init/secure_init.h index e6c9da0b4..6404c5cc4 100644 --- a/Source/portable/ARMv8M/secure/init/secure_init.h +++ b/Source/portable/ARMv8M/secure/init/secure_init.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/Source/portable/ARMv8M/secure/macros/secure_port_macros.h b/Source/portable/ARMv8M/secure/macros/secure_port_macros.h index d7ac5833c..085108cc1 100644 --- a/Source/portable/ARMv8M/secure/macros/secure_port_macros.h +++ b/Source/portable/ARMv8M/secure/macros/secure_port_macros.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/Source/portable/BCC/16BitDOS/Flsh186/port.c b/Source/portable/BCC/16BitDOS/Flsh186/port.c index 827f458cc..faab8c18d 100644 --- a/Source/portable/BCC/16BitDOS/Flsh186/port.c +++ b/Source/portable/BCC/16BitDOS/Flsh186/port.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/Source/portable/BCC/16BitDOS/Flsh186/prtmacro.h b/Source/portable/BCC/16BitDOS/Flsh186/prtmacro.h index 3ae68e6db..306c5c601 100644 --- a/Source/portable/BCC/16BitDOS/Flsh186/prtmacro.h +++ b/Source/portable/BCC/16BitDOS/Flsh186/prtmacro.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/Source/portable/BCC/16BitDOS/PC/port.c b/Source/portable/BCC/16BitDOS/PC/port.c index ec5845e8d..2f5d5434b 100644 --- a/Source/portable/BCC/16BitDOS/PC/port.c +++ b/Source/portable/BCC/16BitDOS/PC/port.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/Source/portable/BCC/16BitDOS/PC/prtmacro.h b/Source/portable/BCC/16BitDOS/PC/prtmacro.h index 03118cefd..d4295897b 100644 --- a/Source/portable/BCC/16BitDOS/PC/prtmacro.h +++ b/Source/portable/BCC/16BitDOS/PC/prtmacro.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/Source/portable/BCC/16BitDOS/common/portasm.h b/Source/portable/BCC/16BitDOS/common/portasm.h index bc2941a40..34a79088c 100644 --- a/Source/portable/BCC/16BitDOS/common/portasm.h +++ b/Source/portable/BCC/16BitDOS/common/portasm.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/Source/portable/BCC/16BitDOS/common/portcomn.c b/Source/portable/BCC/16BitDOS/common/portcomn.c index ff3049645..3e9b2b131 100644 --- a/Source/portable/BCC/16BitDOS/common/portcomn.c +++ b/Source/portable/BCC/16BitDOS/common/portcomn.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/Source/portable/CCS/ARM_CM3/port.c b/Source/portable/CCS/ARM_CM3/port.c index 3ba7d68ca..b77031755 100644 --- a/Source/portable/CCS/ARM_CM3/port.c +++ b/Source/portable/CCS/ARM_CM3/port.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -363,14 +363,21 @@ void xPortSysTickHandler( void ) * save and then restore the interrupt mask value as its value is already * known. */ ( void ) portSET_INTERRUPT_MASK_FROM_ISR(); + traceISR_ENTER(); { /* Increment the RTOS tick. */ if( xTaskIncrementTick() != pdFALSE ) { + traceISR_EXIT_TO_SCHEDULER(); + /* A context switch is required. Context switching is performed in * the PendSV interrupt. Pend the PendSV interrupt. */ portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; } + else + { + traceISR_EXIT(); + } } portCLEAR_INTERRUPT_MASK_FROM_ISR( 0 ); } diff --git a/Source/portable/CCS/ARM_CM3/portasm.asm b/Source/portable/CCS/ARM_CM3/portasm.asm index 59b495fb2..7304b5626 100644 --- a/Source/portable/CCS/ARM_CM3/portasm.asm +++ b/Source/portable/CCS/ARM_CM3/portasm.asm @@ -1,5 +1,5 @@ ;/* -; * FreeRTOS Kernel V10.6.2 +; * FreeRTOS Kernel V11.0.1 ; * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. ; * ; * SPDX-License-Identifier: MIT diff --git a/Source/portable/CCS/ARM_CM3/portmacro.h b/Source/portable/CCS/ARM_CM3/portmacro.h index f4cc7d267..f7e2de0e4 100644 --- a/Source/portable/CCS/ARM_CM3/portmacro.h +++ b/Source/portable/CCS/ARM_CM3/portmacro.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -95,10 +95,22 @@ __asm( " isb"); \ } - #define portNVIC_INT_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed04 ) ) - #define portNVIC_PENDSVSET_BIT ( 1UL << 28UL ) - #define portEND_SWITCHING_ISR( xSwitchRequired ) do { if( xSwitchRequired != pdFALSE ) portYIELD(); } while( 0 ) - #define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x ) +#define portNVIC_INT_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed04 ) ) +#define portNVIC_PENDSVSET_BIT ( 1UL << 28UL ) +#define portEND_SWITCHING_ISR( xSwitchRequired ) \ + do \ + { \ + if( xSwitchRequired != pdFALSE ) \ + { \ + traceISR_EXIT_TO_SCHEDULER(); \ + portYIELD(); \ + } \ + else \ + { \ + traceISR_EXIT(); \ + } \ + } while( 0 ) +#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x ) /*-----------------------------------------------------------*/ @@ -132,8 +144,8 @@ #define portDISABLE_INTERRUPTS() \ { \ _set_interrupt_priority( configMAX_SYSCALL_INTERRUPT_PRIORITY ); \ - __asm( " dsb"); \ - __asm( " isb"); \ + __asm( " dsb"); \ + __asm( " isb"); \ } #define portENABLE_INTERRUPTS() _set_interrupt_priority( 0 ) diff --git a/Source/portable/CCS/ARM_CM4F/port.c b/Source/portable/CCS/ARM_CM4F/port.c index bb245ec04..04251a9f1 100644 --- a/Source/portable/CCS/ARM_CM4F/port.c +++ b/Source/portable/CCS/ARM_CM4F/port.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -388,14 +388,21 @@ void xPortSysTickHandler( void ) * save and then restore the interrupt mask value as its value is already * known. */ ( void ) portSET_INTERRUPT_MASK_FROM_ISR(); + traceISR_ENTER(); { /* Increment the RTOS tick. */ if( xTaskIncrementTick() != pdFALSE ) { + traceISR_EXIT_TO_SCHEDULER(); + /* A context switch is required. Context switching is performed in * the PendSV interrupt. Pend the PendSV interrupt. */ portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; } + else + { + traceISR_EXIT(); + } } portCLEAR_INTERRUPT_MASK_FROM_ISR( 0 ); } diff --git a/Source/portable/CCS/ARM_CM4F/portasm.asm b/Source/portable/CCS/ARM_CM4F/portasm.asm index 9f604bd22..6ee6cb123 100644 --- a/Source/portable/CCS/ARM_CM4F/portasm.asm +++ b/Source/portable/CCS/ARM_CM4F/portasm.asm @@ -1,5 +1,5 @@ ;/* -; * FreeRTOS Kernel V10.6.2 +; * FreeRTOS Kernel V11.0.1 ; * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. ; * ; * SPDX-License-Identifier: MIT diff --git a/Source/portable/CCS/ARM_CM4F/portmacro.h b/Source/portable/CCS/ARM_CM4F/portmacro.h index a72893fef..c19d24893 100644 --- a/Source/portable/CCS/ARM_CM4F/portmacro.h +++ b/Source/portable/CCS/ARM_CM4F/portmacro.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -89,10 +89,22 @@ __asm( " isb"); \ } - #define portNVIC_INT_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed04 ) ) - #define portNVIC_PENDSVSET_BIT ( 1UL << 28UL ) - #define portEND_SWITCHING_ISR( xSwitchRequired ) do { if( xSwitchRequired != pdFALSE ) portYIELD(); } while( 0 ) - #define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x ) +#define portNVIC_INT_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed04 ) ) +#define portNVIC_PENDSVSET_BIT ( 1UL << 28UL ) +#define portEND_SWITCHING_ISR( xSwitchRequired ) \ + do \ + { \ + if( xSwitchRequired != pdFALSE ) \ + { \ + traceISR_EXIT_TO_SCHEDULER(); \ + portYIELD(); \ + } \ + else \ + { \ + traceISR_EXIT(); \ + } \ + } while( 0 ) +#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x ) /*-----------------------------------------------------------*/ diff --git a/Source/portable/CCS/ARM_Cortex-R4/port.c b/Source/portable/CCS/ARM_Cortex-R4/port.c index 535c96ae5..3354d7b24 100644 --- a/Source/portable/CCS/ARM_Cortex-R4/port.c +++ b/Source/portable/CCS/ARM_Cortex-R4/port.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/Source/portable/CCS/ARM_Cortex-R4/portASM.asm b/Source/portable/CCS/ARM_Cortex-R4/portASM.asm index c837408db..073643ed7 100644 --- a/Source/portable/CCS/ARM_Cortex-R4/portASM.asm +++ b/Source/portable/CCS/ARM_Cortex-R4/portASM.asm @@ -1,5 +1,5 @@ ;/* -; * FreeRTOS Kernel V10.6.2 +; * FreeRTOS Kernel V11.0.1 ; * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. ; * ; * SPDX-License-Identifier: MIT diff --git a/Source/portable/CCS/ARM_Cortex-R4/portmacro.h b/Source/portable/CCS/ARM_Cortex-R4/portmacro.h index 33e3b8852..2f0634fd9 100644 --- a/Source/portable/CCS/ARM_Cortex-R4/portmacro.h +++ b/Source/portable/CCS/ARM_Cortex-R4/portmacro.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/Source/portable/CCS/MSP430X/data_model.h b/Source/portable/CCS/MSP430X/data_model.h index 0c341d3fd..7916396d0 100644 --- a/Source/portable/CCS/MSP430X/data_model.h +++ b/Source/portable/CCS/MSP430X/data_model.h @@ -1,5 +1,5 @@ ;/* -; * FreeRTOS Kernel V10.6.2 +; * FreeRTOS Kernel V11.0.1 ; * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. ; * ; * SPDX-License-Identifier: MIT diff --git a/Source/portable/CCS/MSP430X/port.c b/Source/portable/CCS/MSP430X/port.c index 16c5a635c..fbfb6a86e 100644 --- a/Source/portable/CCS/MSP430X/port.c +++ b/Source/portable/CCS/MSP430X/port.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/Source/portable/CCS/MSP430X/portext.asm b/Source/portable/CCS/MSP430X/portext.asm index 76dc984b7..14d86a3eb 100644 --- a/Source/portable/CCS/MSP430X/portext.asm +++ b/Source/portable/CCS/MSP430X/portext.asm @@ -1,5 +1,5 @@ ;/* -; * FreeRTOS Kernel V10.6.2 +; * FreeRTOS Kernel V11.0.1 ; * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. ; * ; * SPDX-License-Identifier: MIT diff --git a/Source/portable/CCS/MSP430X/portmacro.h b/Source/portable/CCS/MSP430X/portmacro.h index f9df74561..f318139a5 100644 --- a/Source/portable/CCS/MSP430X/portmacro.h +++ b/Source/portable/CCS/MSP430X/portmacro.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/Source/portable/CMakeLists.txt b/Source/portable/CMakeLists.txt index 988be1524..b84b3018b 100644 --- a/Source/portable/CMakeLists.txt +++ b/Source/portable/CMakeLists.txt @@ -1,3 +1,11 @@ +if( FREERTOS_PORT STREQUAL "GCC_RISC_V_GENERIC" ) + include( GCC/RISC-V/chip_extensions.cmake ) +endif() + +if( FREERTOS_PORT STREQUAL "IAR_RISC_V_GENERIC" ) + include( IAR/RISC-V/chip_extensions.cmake ) +endif() + # FreeRTOS internal cmake file. Do not use it in user top-level project if (FREERTOS_PORT STREQUAL "A_CUSTOM_PORT") @@ -8,7 +16,11 @@ endif() # FreeRTOS internal cmake file. Do not use it in user top-level project add_library(freertos_kernel_port STATIC - # 16-Bit DOS ports for BCC + # TEMPLATE Port + $<$: + template/port.c> + + # 16-Bit DOS ports for BCC $<$: BCC/16BitDOS/common/portcomn.c BCC/16BitDOS/Flsh186/port.c> @@ -55,13 +67,13 @@ add_library(freertos_kernel_port STATIC GCC/ARM_CA9/portASM.S> # ARMv8-A ports for GCC - $<$: - GCC/ARM_CA53_64_BIT/port.c - GCC/ARM_CA53_64_BIT/portASM.S> + $<$: + GCC/Arm_AARCH64/port.c + GCC/Arm_AARCH64/portASM.S> - $<$: - GCC/ARM_CA53_64_BIT_SRE/port.c - GCC/ARM_CA53_64_BIT_SRE/portASM.S> + $<$: + GCC/Arm_AARCH64_SRE/port.c + GCC/Arm_AARCH64_SRE/portASM.S> # ARMv6-M port for GCC $<$: @@ -288,6 +300,10 @@ add_library(freertos_kernel_port STATIC GCC/RISC-V/port.c GCC/RISC-V/portASM.S> + $<$: + GCC/RISC-V/port.c + GCC/RISC-V/portASM.S> + # Renesas RL78 port for GCC $<$: GCC/RL78/port.c @@ -493,6 +509,10 @@ add_library(freertos_kernel_port STATIC IAR/RISC-V/port.c IAR/RISC-V/portASM.s> + $<$: + IAR/RISC-V/port.c + IAR/RISC-V/portASM.s> + # Renesas RL78 port for IAR EWRL78 $<$: IAR/RL78/port.c @@ -708,7 +728,10 @@ if( FREERTOS_PORT MATCHES "GCC_ARM_CM(3|4)_MPU" OR endif() target_include_directories(freertos_kernel_port PUBLIC - # 16-Bit DOS ports for BCC + # TEMPLATE Port + $<$:${CMAKE_CURRENT_LIST_DIR}/template> + + # 16-Bit DOS ports for BCC $<$: ${CMAKE_CURRENT_LIST_DIR}/BCC/16BitDOS/common ${CMAKE_CURRENT_LIST_DIR}/BCC/16BitDOS/Flsh186> @@ -738,8 +761,8 @@ target_include_directories(freertos_kernel_port PUBLIC $<$:${CMAKE_CURRENT_LIST_DIR}/GCC/ARM_CA9> # ARMv8-A ports for GCC - $<$:${CMAKE_CURRENT_LIST_DIR}/GCC/ARM_CA53_64_BIT> - $<$:${CMAKE_CURRENT_LIST_DIR}/GCC/ARM_CA53_64_BIT_SRE> + $<$:${CMAKE_CURRENT_LIST_DIR}/GCC/Arm_AARCH64> + $<$:${CMAKE_CURRENT_LIST_DIR}/GCC/Arm_AARCH64_SRE> # ARMv6-M port for GCC $<$:${CMAKE_CURRENT_LIST_DIR}/GCC/ARM_CM0> @@ -774,7 +797,7 @@ target_include_directories(freertos_kernel_port PUBLIC $<$:${CMAKE_CURRENT_LIST_DIR}/GCC/ARM_CM55/non_secure> $<$:${CMAKE_CURRENT_LIST_DIR}/GCC/ARM_CM55/secure> $<$:${CMAKE_CURRENT_LIST_DIR}/GCC/ARM_CM55_NTZ/non_secure> - $<$:${CMAKE_CURRENT_LIST_DIR}/GCC/ARM_CM85_NTZ/non_secure> + $<$:${CMAKE_CURRENT_LIST_DIR}/GCC/ARM_CM55_NTZ/non_secure> $<$:${CMAKE_CURRENT_LIST_DIR}/GCC/ARM_CM85/non_secure> $<$:${CMAKE_CURRENT_LIST_DIR}/GCC/ARM_CM85/secure> @@ -838,6 +861,10 @@ target_include_directories(freertos_kernel_port PUBLIC ${CMAKE_CURRENT_LIST_DIR}/GCC/RISC-V ${CMAKE_CURRENT_LIST_DIR}/GCC/RISC-V/chip_specific_extensions/Pulpino_Vega_RV32M1RM> + $<$: + ${CMAKE_CURRENT_LIST_DIR}/GCC/RISC-V + ${CMAKE_CURRENT_LIST_DIR}/GCC/RISC-V/chip_specific_extensions/${FREERTOS_RISCV_EXTENSION}> + # Renesas RL78 port for GCC $<$:${CMAKE_CURRENT_LIST_DIR}/GCC/RL78> @@ -935,6 +962,10 @@ target_include_directories(freertos_kernel_port PUBLIC ${CMAKE_CURRENT_LIST_DIR}/IAR/RISC-V ${CMAKE_CURRENT_LIST_DIR}/IAR/RISC-V/chip_specific_extensions/RV32I_CLINT_no_extensions> + $<$: + ${CMAKE_CURRENT_LIST_DIR}/IAR/RISC-V + ${CMAKE_CURRENT_LIST_DIR}/IAR/RISC-V/chip_specific_extensions/${FREERTOS_RISCV_EXTENSION}> + # Renesas RL78 port for IAR EWRL78 $<$:${CMAKE_CURRENT_LIST_DIR}/IAR/RL78> diff --git a/Source/portable/CodeWarrior/ColdFire_V1/port.c b/Source/portable/CodeWarrior/ColdFire_V1/port.c index 00c5e5dbf..a9454efdb 100644 --- a/Source/portable/CodeWarrior/ColdFire_V1/port.c +++ b/Source/portable/CodeWarrior/ColdFire_V1/port.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -75,7 +75,7 @@ uint32_t ulOriginalA5; /* Parameter in A0. */ *( pxTopOfStack + 8 ) = ( StackType_t ) pvParameters; - /* A5 must be maintained as it is resurved by the compiler. */ + /* A5 must be maintained as it is reserved by the compiler. */ *( pxTopOfStack + 13 ) = ulOriginalA5; return pxTopOfStack; diff --git a/Source/portable/CodeWarrior/ColdFire_V1/portasm.S b/Source/portable/CodeWarrior/ColdFire_V1/portasm.S index 06ac417aa..f55e3d590 100644 --- a/Source/portable/CodeWarrior/ColdFire_V1/portasm.S +++ b/Source/portable/CodeWarrior/ColdFire_V1/portasm.S @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/Source/portable/CodeWarrior/ColdFire_V1/portmacro.h b/Source/portable/CodeWarrior/ColdFire_V1/portmacro.h index ebaa9b916..42dfe7c7d 100644 --- a/Source/portable/CodeWarrior/ColdFire_V1/portmacro.h +++ b/Source/portable/CodeWarrior/ColdFire_V1/portmacro.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -106,8 +106,20 @@ extern void vPortClearInterruptMaskFromISR( UBaseType_t ); #define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters ) /*-----------------------------------------------------------*/ -#define portEND_SWITCHING_ISR( xSwitchRequired ) do { if( xSwitchRequired != pdFALSE ) { portYIELD(); } } while( 0 ) +#define portEND_SWITCHING_ISR( xSwitchRequired ) \ + do \ + { \ + if( xSwitchRequired != pdFALSE ) \ + { \ + traceISR_EXIT_TO_SCHEDULER(); \ + portYIELD(); \ + } \ + else \ + { \ + traceISR_EXIT(); \ + } \ + } while( 0 ) /* *INDENT-OFF* */ #ifdef __cplusplus diff --git a/Source/portable/CodeWarrior/ColdFire_V2/port.c b/Source/portable/CodeWarrior/ColdFire_V2/port.c index 4e65f9a6d..6b603b3c7 100644 --- a/Source/portable/CodeWarrior/ColdFire_V2/port.c +++ b/Source/portable/CodeWarrior/ColdFire_V2/port.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/Source/portable/CodeWarrior/ColdFire_V2/portasm.S b/Source/portable/CodeWarrior/ColdFire_V2/portasm.S index b9e9e9e6a..7a910508e 100644 --- a/Source/portable/CodeWarrior/ColdFire_V2/portasm.S +++ b/Source/portable/CodeWarrior/ColdFire_V2/portasm.S @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/Source/portable/CodeWarrior/ColdFire_V2/portmacro.h b/Source/portable/CodeWarrior/ColdFire_V2/portmacro.h index 26806616a..c6088fbdf 100644 --- a/Source/portable/CodeWarrior/ColdFire_V2/portmacro.h +++ b/Source/portable/CodeWarrior/ColdFire_V2/portmacro.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -105,8 +105,19 @@ extern void vPortClearInterruptMaskFromISR( UBaseType_t ); #define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters ) /*-----------------------------------------------------------*/ -#define portEND_SWITCHING_ISR( xSwitchRequired ) do { if( xSwitchRequired != pdFALSE ) { portYIELD(); } } while( 0 ) - +#define portEND_SWITCHING_ISR( xSwitchRequired ) \ + do \ + { \ + if( xSwitchRequired != pdFALSE ) \ + { \ + traceISR_EXIT_TO_SCHEDULER(); \ + portYIELD(); \ + } \ + else \ + { \ + traceISR_EXIT(); \ + } \ + } while( 0 ) /* *INDENT-OFF* */ #ifdef __cplusplus diff --git a/Source/portable/CodeWarrior/HCS12/port.c b/Source/portable/CodeWarrior/HCS12/port.c index bab292f9a..e73a183bc 100644 --- a/Source/portable/CodeWarrior/HCS12/port.c +++ b/Source/portable/CodeWarrior/HCS12/port.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/Source/portable/CodeWarrior/HCS12/portmacro.h b/Source/portable/CodeWarrior/HCS12/portmacro.h index 76ac8ed73..5c5cd0002 100644 --- a/Source/portable/CodeWarrior/HCS12/portmacro.h +++ b/Source/portable/CodeWarrior/HCS12/portmacro.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/Source/portable/Common/mpu_wrappers.c b/Source/portable/Common/mpu_wrappers.c index 17efcdbce..397d2478d 100644 --- a/Source/portable/Common/mpu_wrappers.c +++ b/Source/portable/Common/mpu_wrappers.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -481,30 +481,6 @@ } /*-----------------------------------------------------------*/ - char * MPU_pcTaskGetName( TaskHandle_t xTaskToQuery ) /* FREERTOS_SYSTEM_CALL */ - { - char * pcReturn; - - if( portIS_PRIVILEGED() == pdFALSE ) - { - portRAISE_PRIVILEGE(); - portMEMORY_BARRIER(); - - pcReturn = pcTaskGetName( xTaskToQuery ); - portMEMORY_BARRIER(); - - portRESET_PRIVILEGE(); - portMEMORY_BARRIER(); - } - else - { - pcReturn = pcTaskGetName( xTaskToQuery ); - } - - return pcReturn; - } -/*-----------------------------------------------------------*/ - #if ( INCLUDE_xTaskGetHandle == 1 ) TaskHandle_t MPU_xTaskGetHandle( const char * pcNameToQuery ) /* FREERTOS_SYSTEM_CALL */ { @@ -1947,11 +1923,11 @@ /*-----------------------------------------------------------*/ #if ( configUSE_TIMERS == 1 ) - BaseType_t MPU_xTimerGenericCommand( TimerHandle_t xTimer, - const BaseType_t xCommandID, - const TickType_t xOptionalValue, - BaseType_t * const pxHigherPriorityTaskWoken, - const TickType_t xTicksToWait ) /* FREERTOS_SYSTEM_CALL */ + BaseType_t MPU_xTimerGenericCommandFromTask( TimerHandle_t xTimer, + const BaseType_t xCommandID, + const TickType_t xOptionalValue, + BaseType_t * const pxHigherPriorityTaskWoken, + const TickType_t xTicksToWait ) /* FREERTOS_SYSTEM_CALL */ { BaseType_t xReturn; @@ -1960,7 +1936,7 @@ portRAISE_PRIVILEGE(); portMEMORY_BARRIER(); - xReturn = xTimerGenericCommand( xTimer, xCommandID, xOptionalValue, pxHigherPriorityTaskWoken, xTicksToWait ); + xReturn = xTimerGenericCommandFromTask( xTimer, xCommandID, xOptionalValue, pxHigherPriorityTaskWoken, xTicksToWait ); portMEMORY_BARRIER(); portRESET_PRIVILEGE(); @@ -1968,7 +1944,7 @@ } else { - xReturn = xTimerGenericCommand( xTimer, xCommandID, xOptionalValue, pxHigherPriorityTaskWoken, xTicksToWait ); + xReturn = xTimerGenericCommandFromTask( xTimer, xCommandID, xOptionalValue, pxHigherPriorityTaskWoken, xTicksToWait ); } return xReturn; diff --git a/Source/portable/Common/mpu_wrappers_v2.c b/Source/portable/Common/mpu_wrappers_v2.c index f82762dc6..d40141e16 100644 --- a/Source/portable/Common/mpu_wrappers_v2.c +++ b/Source/portable/Common/mpu_wrappers_v2.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -763,37 +763,6 @@ } /*-----------------------------------------------------------*/ - char * MPU_pcTaskGetNameImpl( TaskHandle_t xTaskToQuery ) PRIVILEGED_FUNCTION; - - char * MPU_pcTaskGetNameImpl( TaskHandle_t xTaskToQuery ) /* PRIVILEGED_FUNCTION */ - { - char * pcReturn = NULL; - int32_t lIndex; - TaskHandle_t xInternalTaskHandle = NULL; - - if( xTaskToQuery == NULL ) - { - pcReturn = pcTaskGetName( xTaskToQuery ); - } - else - { - lIndex = ( int32_t ) xTaskToQuery; - - if( IS_EXTERNAL_INDEX_VALID( lIndex ) != pdFALSE ) - { - xInternalTaskHandle = MPU_GetTaskHandleAtIndex( CONVERT_TO_INTERNAL_INDEX( lIndex ) ); - - if( xInternalTaskHandle != NULL ) - { - pcReturn = pcTaskGetName( xInternalTaskHandle ); - } - } - } - - return pcReturn; - } -/*-----------------------------------------------------------*/ - #if ( configGENERATE_RUN_TIME_STATS == 1 ) configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetRunTimeCounterImpl( const TaskHandle_t xTask ) PRIVILEGED_FUNCTION; @@ -1672,12 +1641,12 @@ xInternalTaskHandle = xTaskGetCurrentTaskHandle(); lIndex = MPU_GetIndexForTaskHandle( xInternalTaskHandle ); - vTaskDelete( xInternalTaskHandle ); - if( lIndex != -1 ) { MPU_SetIndexFreeInKernelObjectPool( lIndex ); } + + vTaskDelete( xInternalTaskHandle ); } else { @@ -1689,8 +1658,8 @@ if( xInternalTaskHandle != NULL ) { - vTaskDelete( xInternalTaskHandle ); MPU_SetIndexFreeInKernelObjectPool( CONVERT_TO_INTERNAL_INDEX( lIndex ) ); + vTaskDelete( xInternalTaskHandle ); } } } @@ -1947,6 +1916,35 @@ #endif /* if ( configSUPPORT_STATIC_ALLOCATION == 1 ) */ /*-----------------------------------------------------------*/ + char * MPU_pcTaskGetName( TaskHandle_t xTaskToQuery ) /* PRIVILEGED_FUNCTION */ + { + char * pcReturn = NULL; + int32_t lIndex; + TaskHandle_t xInternalTaskHandle = NULL; + + if( xTaskToQuery == NULL ) + { + pcReturn = pcTaskGetName( xTaskToQuery ); + } + else + { + lIndex = ( int32_t ) xTaskToQuery; + + if( IS_EXTERNAL_INDEX_VALID( lIndex ) != pdFALSE ) + { + xInternalTaskHandle = MPU_GetTaskHandleAtIndex( CONVERT_TO_INTERNAL_INDEX( lIndex ) ); + + if( xInternalTaskHandle != NULL ) + { + pcReturn = pcTaskGetName( xInternalTaskHandle ); + } + } + } + + return pcReturn; + } +/*-----------------------------------------------------------*/ + #if ( INCLUDE_uxTaskPriorityGet == 1 ) UBaseType_t MPU_uxTaskPriorityGetFromISR( const TaskHandle_t xTask ) /* PRIVILEGED_FUNCTION */ @@ -1980,6 +1978,72 @@ #endif /* #if ( INCLUDE_uxTaskPriorityGet == 1 ) */ /*-----------------------------------------------------------*/ + #if ( ( INCLUDE_uxTaskPriorityGet == 1 ) && ( configUSE_MUTEXES == 1 ) ) + + UBaseType_t MPU_uxTaskBasePriorityGet( const TaskHandle_t xTask ) /* PRIVILEGED_FUNCTION */ + { + UBaseType_t uxReturn = configMAX_PRIORITIES; + int32_t lIndex; + TaskHandle_t xInternalTaskHandle = NULL; + + if( xTask == NULL ) + { + uxReturn = uxTaskBasePriorityGet( xTask ); + } + else + { + lIndex = ( int32_t ) xTask; + + if( IS_EXTERNAL_INDEX_VALID( lIndex ) != pdFALSE ) + { + xInternalTaskHandle = MPU_GetTaskHandleAtIndex( CONVERT_TO_INTERNAL_INDEX( lIndex ) ); + + if( xInternalTaskHandle != NULL ) + { + uxReturn = uxTaskBasePriorityGet( xInternalTaskHandle ); + } + } + } + + return uxReturn; + } + + #endif /* #if ( ( INCLUDE_uxTaskPriorityGet == 1 ) && ( configUSE_MUTEXES == 1 ) ) */ +/*-----------------------------------------------------------*/ + + #if ( ( INCLUDE_uxTaskPriorityGet == 1 ) && ( configUSE_MUTEXES == 1 ) ) + + UBaseType_t MPU_uxTaskBasePriorityGetFromISR( const TaskHandle_t xTask ) /* PRIVILEGED_FUNCTION */ + { + UBaseType_t uxReturn = configMAX_PRIORITIES; + int32_t lIndex; + TaskHandle_t xInternalTaskHandle = NULL; + + if( xTask == NULL ) + { + uxReturn = uxTaskBasePriorityGetFromISR( xTask ); + } + else + { + lIndex = ( int32_t ) xTask; + + if( IS_EXTERNAL_INDEX_VALID( lIndex ) != pdFALSE ) + { + xInternalTaskHandle = MPU_GetTaskHandleAtIndex( CONVERT_TO_INTERNAL_INDEX( lIndex ) ); + + if( xInternalTaskHandle != NULL ) + { + uxReturn = uxTaskBasePriorityGetFromISR( xInternalTaskHandle ); + } + } + } + + return uxReturn; + } + + #endif /* #if ( ( INCLUDE_uxTaskPriorityGet == 1 ) && ( configUSE_MUTEXES == 1 ) ) */ +/*-----------------------------------------------------------*/ + #if ( ( INCLUDE_xTaskResumeFromISR == 1 ) && ( INCLUDE_vTaskSuspend == 1 ) ) BaseType_t MPU_xTaskResumeFromISR( TaskHandle_t xTaskToResume ) /* PRIVILEGED_FUNCTION */ @@ -2140,7 +2204,7 @@ if( pvItemToQueue != NULL ) { xIsItemToQueueReadable = xPortIsAuthorizedToAccessBuffer( pvItemToQueue, - uxQueueGetQueueItemSize( xInternalQueueHandle ), + uxQueueItemSize, tskMPU_READ_PERMISSION ); } @@ -2253,7 +2317,7 @@ ) { xIsReceiveBufferWritable = xPortIsAuthorizedToAccessBuffer( pvBuffer, - uxQueueGetQueueItemSize( xInternalQueueHandle ), + uxQueueItemSize, tskMPU_WRITE_PERMISSION ); if( xIsReceiveBufferWritable == pdTRUE ) @@ -2305,7 +2369,7 @@ ) { xIsReceiveBufferWritable = xPortIsAuthorizedToAccessBuffer( pvBuffer, - uxQueueGetQueueItemSize( xInternalQueueHandle ), + uxQueueItemSize, tskMPU_WRITE_PERMISSION ); if( xIsReceiveBufferWritable == pdTRUE ) @@ -3370,14 +3434,14 @@ #if ( configUSE_TIMERS == 1 ) - BaseType_t MPU_xTimerGenericCommand( TimerHandle_t xTimer, - const BaseType_t xCommandID, - const TickType_t xOptionalValue, - BaseType_t * const pxHigherPriorityTaskWoken, - const TickType_t xTicksToWait ) /* FREERTOS_SYSTEM_CALL */ + BaseType_t MPU_xTimerGenericCommandFromTask( TimerHandle_t xTimer, + const BaseType_t xCommandID, + const TickType_t xOptionalValue, + BaseType_t * const pxHigherPriorityTaskWoken, + const TickType_t xTicksToWait ) /* FREERTOS_SYSTEM_CALL */ { BaseType_t xReturn = pdFALSE; - xTimerGenericCommandParams_t xParams; + xTimerGenericCommandFromTaskParams_t xParams; xParams.xTimer = xTimer; xParams.xCommandID = xCommandID; @@ -3385,14 +3449,14 @@ xParams.pxHigherPriorityTaskWoken = pxHigherPriorityTaskWoken; xParams.xTicksToWait = xTicksToWait; - xReturn = MPU_xTimerGenericCommandEntry( &( xParams ) ); + xReturn = MPU_xTimerGenericCommandFromTaskEntry( &( xParams ) ); return xReturn; } - BaseType_t MPU_xTimerGenericCommandImpl( const xTimerGenericCommandParams_t * pxParams ) PRIVILEGED_FUNCTION; + BaseType_t MPU_xTimerGenericCommandFromTaskImpl( const xTimerGenericCommandFromTaskParams_t * pxParams ) PRIVILEGED_FUNCTION; - BaseType_t MPU_xTimerGenericCommandImpl( const xTimerGenericCommandParams_t * pxParams ) /* PRIVILEGED_FUNCTION */ + BaseType_t MPU_xTimerGenericCommandFromTaskImpl( const xTimerGenericCommandFromTaskParams_t * pxParams ) /* PRIVILEGED_FUNCTION */ { BaseType_t xReturn = pdFALSE; TimerHandle_t xInternalTimerHandle = NULL; @@ -3404,39 +3468,42 @@ if( pxParams != NULL ) { xAreParamsReadable = xPortIsAuthorizedToAccessBuffer( pxParams, - sizeof( xTimerGenericCommandParams_t ), + sizeof( xTimerGenericCommandFromTaskParams_t ), tskMPU_READ_PERMISSION ); } if( xAreParamsReadable == pdTRUE ) { - if( pxParams->pxHigherPriorityTaskWoken != NULL ) - { - xIsHigherPriorityTaskWokenWriteable = xPortIsAuthorizedToAccessBuffer( pxParams->pxHigherPriorityTaskWoken, - sizeof( BaseType_t ), - tskMPU_WRITE_PERMISSION ); - } - - if( ( pxParams->pxHigherPriorityTaskWoken == NULL ) || - ( xIsHigherPriorityTaskWokenWriteable == pdTRUE ) ) + if( pxParams->xCommandID < tmrFIRST_FROM_ISR_COMMAND ) { - lIndex = ( int32_t ) ( pxParams->xTimer ); + if( pxParams->pxHigherPriorityTaskWoken != NULL ) + { + xIsHigherPriorityTaskWokenWriteable = xPortIsAuthorizedToAccessBuffer( pxParams->pxHigherPriorityTaskWoken, + sizeof( BaseType_t ), + tskMPU_WRITE_PERMISSION ); + } - if( IS_EXTERNAL_INDEX_VALID( lIndex ) != pdFALSE ) + if( ( pxParams->pxHigherPriorityTaskWoken == NULL ) || + ( xIsHigherPriorityTaskWokenWriteable == pdTRUE ) ) { - xCallingTaskIsAuthorizedToAccessTimer = xPortIsAuthorizedToAccessKernelObject( CONVERT_TO_INTERNAL_INDEX( lIndex ) ); + lIndex = ( int32_t ) ( pxParams->xTimer ); - if( xCallingTaskIsAuthorizedToAccessTimer == pdTRUE ) + if( IS_EXTERNAL_INDEX_VALID( lIndex ) != pdFALSE ) { - xInternalTimerHandle = MPU_GetTimerHandleAtIndex( CONVERT_TO_INTERNAL_INDEX( lIndex ) ); + xCallingTaskIsAuthorizedToAccessTimer = xPortIsAuthorizedToAccessKernelObject( CONVERT_TO_INTERNAL_INDEX( lIndex ) ); - if( xInternalTimerHandle != NULL ) + if( xCallingTaskIsAuthorizedToAccessTimer == pdTRUE ) { - xReturn = xTimerGenericCommand( xInternalTimerHandle, - pxParams->xCommandID, - pxParams->xOptionalValue, - pxParams->pxHigherPriorityTaskWoken, - pxParams->xTicksToWait ); + xInternalTimerHandle = MPU_GetTimerHandleAtIndex( CONVERT_TO_INTERNAL_INDEX( lIndex ) ); + + if( xInternalTimerHandle != NULL ) + { + xReturn = xTimerGenericCommandFromTask( xInternalTimerHandle, + pxParams->xCommandID, + pxParams->xOptionalValue, + pxParams->pxHigherPriorityTaskWoken, + pxParams->xTicksToWait ); + } } } } @@ -3446,36 +3513,6 @@ return xReturn; } - BaseType_t MPU_xTimerGenericCommandPrivImpl( const xTimerGenericCommandParams_t * pxParams ) PRIVILEGED_FUNCTION; - - BaseType_t MPU_xTimerGenericCommandPrivImpl( const xTimerGenericCommandParams_t * pxParams ) /* PRIVILEGED_FUNCTION */ - { - BaseType_t xReturn = pdFALSE; - TimerHandle_t xInternalTimerHandle = NULL; - int32_t lIndex; - - if( pxParams != NULL ) - { - lIndex = ( int32_t ) ( pxParams->xTimer ); - - if( IS_EXTERNAL_INDEX_VALID( lIndex ) != pdFALSE ) - { - xInternalTimerHandle = MPU_GetTimerHandleAtIndex( CONVERT_TO_INTERNAL_INDEX( lIndex ) ); - - if( xInternalTimerHandle != NULL ) - { - xReturn = xTimerGenericCommand( xInternalTimerHandle, - pxParams->xCommandID, - pxParams->xOptionalValue, - pxParams->pxHigherPriorityTaskWoken, - pxParams->xTicksToWait ); - } - } - } - - return xReturn; - } - #endif /* if ( configUSE_TIMERS == 1 ) */ /*-----------------------------------------------------------*/ @@ -3785,6 +3822,47 @@ #endif /* if ( configSUPPORT_STATIC_ALLOCATION == 1 ) && ( configUSE_TIMERS == 1 ) */ /*-----------------------------------------------------------*/ + #if ( configUSE_TIMERS == 1 ) + + BaseType_t MPU_xTimerGenericCommandFromISR( TimerHandle_t xTimer, + const BaseType_t xCommandID, + const TickType_t xOptionalValue, + BaseType_t * const pxHigherPriorityTaskWoken, + const TickType_t xTicksToWait ) /* PRIVILEGED_FUNCTION */ + { + BaseType_t xReturn = pdFALSE; + TimerHandle_t xInternalTimerHandle = NULL; + int32_t lIndex; + BaseType_t xIsHigherPriorityTaskWokenWriteable = pdFALSE; + + if( pxHigherPriorityTaskWoken != NULL ) + { + xIsHigherPriorityTaskWokenWriteable = xPortIsAuthorizedToAccessBuffer( pxHigherPriorityTaskWoken, + sizeof( BaseType_t ), + tskMPU_WRITE_PERMISSION ); + } + + if( ( pxHigherPriorityTaskWoken == NULL ) || ( xIsHigherPriorityTaskWokenWriteable == pdTRUE ) ) + { + lIndex = ( int32_t ) xTimer; + + if( IS_EXTERNAL_INDEX_VALID( lIndex ) != pdFALSE ) + { + xInternalTimerHandle = MPU_GetTimerHandleAtIndex( CONVERT_TO_INTERNAL_INDEX( lIndex ) ); + + if( xInternalTimerHandle != NULL ) + { + xReturn = xTimerGenericCommandFromISR( xInternalTimerHandle, xCommandID, xOptionalValue, pxHigherPriorityTaskWoken, xTicksToWait ); + } + } + } + + return xReturn; + } + + #endif /* if ( configUSE_TIMERS == 1 ) */ +/*-----------------------------------------------------------*/ + /*-----------------------------------------------------------*/ /* MPU wrappers for event group APIs. */ /*-----------------------------------------------------------*/ @@ -4818,235 +4896,234 @@ PRIVILEGED_DATA UBaseType_t uxSystemCallImplementations[ NUM_SYSTEM_CALLS ] = { #if ( configUSE_TASK_NOTIFICATIONS == 1 ) - ( UBaseType_t ) MPU_xTaskGenericNotifyImpl, /* SYSTEM_CALL_xTaskGenericNotify. */ - ( UBaseType_t ) MPU_xTaskGenericNotifyWaitImpl, /* SYSTEM_CALL_xTaskGenericNotifyWait. */ + ( UBaseType_t ) MPU_xTaskGenericNotifyImpl, /* SYSTEM_CALL_xTaskGenericNotify. */ + ( UBaseType_t ) MPU_xTaskGenericNotifyWaitImpl, /* SYSTEM_CALL_xTaskGenericNotifyWait. */ #else - ( UBaseType_t ) 0, /* SYSTEM_CALL_xTaskGenericNotify. */ - ( UBaseType_t ) 0, /* SYSTEM_CALL_xTaskGenericNotifyWait. */ + ( UBaseType_t ) 0, /* SYSTEM_CALL_xTaskGenericNotify. */ + ( UBaseType_t ) 0, /* SYSTEM_CALL_xTaskGenericNotifyWait. */ #endif #if ( configUSE_TIMERS == 1 ) - ( UBaseType_t ) MPU_xTimerGenericCommandImpl, /* SYSTEM_CALL_xTimerGenericCommand. */ + ( UBaseType_t ) MPU_xTimerGenericCommandFromTaskImpl, /* SYSTEM_CALL_xTimerGenericCommandFromTask. */ #else - ( UBaseType_t ) 0, /* SYSTEM_CALL_xTimerGenericCommand. */ + ( UBaseType_t ) 0, /* SYSTEM_CALL_xTimerGenericCommandFromTask. */ #endif - ( UBaseType_t ) MPU_xEventGroupWaitBitsImpl, /* SYSTEM_CALL_xEventGroupWaitBits. */ + ( UBaseType_t ) MPU_xEventGroupWaitBitsImpl, /* SYSTEM_CALL_xEventGroupWaitBits. */ /* The system calls above this line take 5 parameters. */ #if ( INCLUDE_xTaskDelayUntil == 1 ) - ( UBaseType_t ) MPU_xTaskDelayUntilImpl, /* SYSTEM_CALL_xTaskDelayUntil. */ + ( UBaseType_t ) MPU_xTaskDelayUntilImpl, /* SYSTEM_CALL_xTaskDelayUntil. */ #else - ( UBaseType_t ) 0, /* SYSTEM_CALL_xTaskDelayUntil. */ + ( UBaseType_t ) 0, /* SYSTEM_CALL_xTaskDelayUntil. */ #endif #if ( INCLUDE_xTaskAbortDelay == 1 ) - ( UBaseType_t ) MPU_xTaskAbortDelayImpl, /* SYSTEM_CALL_xTaskAbortDelay. */ + ( UBaseType_t ) MPU_xTaskAbortDelayImpl, /* SYSTEM_CALL_xTaskAbortDelay. */ #else - ( UBaseType_t ) 0, /* SYSTEM_CALL_xTaskAbortDelay. */ + ( UBaseType_t ) 0, /* SYSTEM_CALL_xTaskAbortDelay. */ #endif #if ( INCLUDE_vTaskDelay == 1 ) - ( UBaseType_t ) MPU_vTaskDelayImpl, /* SYSTEM_CALL_vTaskDelay. */ + ( UBaseType_t ) MPU_vTaskDelayImpl, /* SYSTEM_CALL_vTaskDelay. */ #else - ( UBaseType_t ) 0, /* SYSTEM_CALL_vTaskDelay. */ + ( UBaseType_t ) 0, /* SYSTEM_CALL_vTaskDelay. */ #endif #if ( INCLUDE_uxTaskPriorityGet == 1 ) - ( UBaseType_t ) MPU_uxTaskPriorityGetImpl, /* SYSTEM_CALL_uxTaskPriorityGet. */ + ( UBaseType_t ) MPU_uxTaskPriorityGetImpl, /* SYSTEM_CALL_uxTaskPriorityGet. */ #else - ( UBaseType_t ) 0, /* SYSTEM_CALL_uxTaskPriorityGet. */ + ( UBaseType_t ) 0, /* SYSTEM_CALL_uxTaskPriorityGet. */ #endif #if ( INCLUDE_eTaskGetState == 1 ) - ( UBaseType_t ) MPU_eTaskGetStateImpl, /* SYSTEM_CALL_eTaskGetState. */ + ( UBaseType_t ) MPU_eTaskGetStateImpl, /* SYSTEM_CALL_eTaskGetState. */ #else - ( UBaseType_t ) 0, /* SYSTEM_CALL_eTaskGetState. */ + ( UBaseType_t ) 0, /* SYSTEM_CALL_eTaskGetState. */ #endif #if ( configUSE_TRACE_FACILITY == 1 ) - ( UBaseType_t ) MPU_vTaskGetInfoImpl, /* SYSTEM_CALL_vTaskGetInfo. */ + ( UBaseType_t ) MPU_vTaskGetInfoImpl, /* SYSTEM_CALL_vTaskGetInfo. */ #else - ( UBaseType_t ) 0, /* SYSTEM_CALL_vTaskGetInfo. */ + ( UBaseType_t ) 0, /* SYSTEM_CALL_vTaskGetInfo. */ #endif #if ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) - ( UBaseType_t ) MPU_xTaskGetIdleTaskHandleImpl, /* SYSTEM_CALL_xTaskGetIdleTaskHandle. */ + ( UBaseType_t ) MPU_xTaskGetIdleTaskHandleImpl, /* SYSTEM_CALL_xTaskGetIdleTaskHandle. */ #else - ( UBaseType_t ) 0, /* SYSTEM_CALL_xTaskGetIdleTaskHandle. */ + ( UBaseType_t ) 0, /* SYSTEM_CALL_xTaskGetIdleTaskHandle. */ #endif #if ( INCLUDE_vTaskSuspend == 1 ) - ( UBaseType_t ) MPU_vTaskSuspendImpl, /* SYSTEM_CALL_vTaskSuspend. */ - ( UBaseType_t ) MPU_vTaskResumeImpl, /* SYSTEM_CALL_vTaskResume. */ + ( UBaseType_t ) MPU_vTaskSuspendImpl, /* SYSTEM_CALL_vTaskSuspend. */ + ( UBaseType_t ) MPU_vTaskResumeImpl, /* SYSTEM_CALL_vTaskResume. */ #else - ( UBaseType_t ) 0, /* SYSTEM_CALL_vTaskSuspend. */ - ( UBaseType_t ) 0, /* SYSTEM_CALL_vTaskResume. */ + ( UBaseType_t ) 0, /* SYSTEM_CALL_vTaskSuspend. */ + ( UBaseType_t ) 0, /* SYSTEM_CALL_vTaskResume. */ #endif - ( UBaseType_t ) MPU_xTaskGetTickCountImpl, /* SYSTEM_CALL_xTaskGetTickCount. */ - ( UBaseType_t ) MPU_uxTaskGetNumberOfTasksImpl, /* SYSTEM_CALL_uxTaskGetNumberOfTasks. */ - ( UBaseType_t ) MPU_pcTaskGetNameImpl, /* SYSTEM_CALL_pcTaskGetName. */ + ( UBaseType_t ) MPU_xTaskGetTickCountImpl, /* SYSTEM_CALL_xTaskGetTickCount. */ + ( UBaseType_t ) MPU_uxTaskGetNumberOfTasksImpl, /* SYSTEM_CALL_uxTaskGetNumberOfTasks. */ #if ( configGENERATE_RUN_TIME_STATS == 1 ) - ( UBaseType_t ) MPU_ulTaskGetRunTimeCounterImpl, /* SYSTEM_CALL_ulTaskGetRunTimeCounter. */ - ( UBaseType_t ) MPU_ulTaskGetRunTimePercentImpl, /* SYSTEM_CALL_ulTaskGetRunTimePercent. */ + ( UBaseType_t ) MPU_ulTaskGetRunTimeCounterImpl, /* SYSTEM_CALL_ulTaskGetRunTimeCounter. */ + ( UBaseType_t ) MPU_ulTaskGetRunTimePercentImpl, /* SYSTEM_CALL_ulTaskGetRunTimePercent. */ #else - ( UBaseType_t ) 0, /* SYSTEM_CALL_ulTaskGetRunTimeCounter. */ - ( UBaseType_t ) 0, /* SYSTEM_CALL_ulTaskGetRunTimePercent. */ + ( UBaseType_t ) 0, /* SYSTEM_CALL_ulTaskGetRunTimeCounter. */ + ( UBaseType_t ) 0, /* SYSTEM_CALL_ulTaskGetRunTimePercent. */ #endif #if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) ) - ( UBaseType_t ) MPU_ulTaskGetIdleRunTimePercentImpl, /* SYSTEM_CALL_ulTaskGetIdleRunTimePercent. */ - ( UBaseType_t ) MPU_ulTaskGetIdleRunTimeCounterImpl, /* SYSTEM_CALL_ulTaskGetIdleRunTimeCounter. */ + ( UBaseType_t ) MPU_ulTaskGetIdleRunTimePercentImpl, /* SYSTEM_CALL_ulTaskGetIdleRunTimePercent. */ + ( UBaseType_t ) MPU_ulTaskGetIdleRunTimeCounterImpl, /* SYSTEM_CALL_ulTaskGetIdleRunTimeCounter. */ #else - ( UBaseType_t ) 0, /* SYSTEM_CALL_ulTaskGetIdleRunTimePercent. */ - ( UBaseType_t ) 0, /* SYSTEM_CALL_ulTaskGetIdleRunTimeCounter. */ + ( UBaseType_t ) 0, /* SYSTEM_CALL_ulTaskGetIdleRunTimePercent. */ + ( UBaseType_t ) 0, /* SYSTEM_CALL_ulTaskGetIdleRunTimeCounter. */ #endif #if ( configUSE_APPLICATION_TASK_TAG == 1 ) - ( UBaseType_t ) MPU_vTaskSetApplicationTaskTagImpl, /* SYSTEM_CALL_vTaskSetApplicationTaskTag. */ - ( UBaseType_t ) MPU_xTaskGetApplicationTaskTagImpl, /* SYSTEM_CALL_xTaskGetApplicationTaskTag. */ + ( UBaseType_t ) MPU_vTaskSetApplicationTaskTagImpl, /* SYSTEM_CALL_vTaskSetApplicationTaskTag. */ + ( UBaseType_t ) MPU_xTaskGetApplicationTaskTagImpl, /* SYSTEM_CALL_xTaskGetApplicationTaskTag. */ #else - ( UBaseType_t ) 0, /* SYSTEM_CALL_vTaskSetApplicationTaskTag. */ - ( UBaseType_t ) 0, /* SYSTEM_CALL_xTaskGetApplicationTaskTag. */ + ( UBaseType_t ) 0, /* SYSTEM_CALL_vTaskSetApplicationTaskTag. */ + ( UBaseType_t ) 0, /* SYSTEM_CALL_xTaskGetApplicationTaskTag. */ #endif #if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 ) - ( UBaseType_t ) MPU_vTaskSetThreadLocalStoragePointerImpl, /* SYSTEM_CALL_vTaskSetThreadLocalStoragePointer. */ - ( UBaseType_t ) MPU_pvTaskGetThreadLocalStoragePointerImpl, /* SYSTEM_CALL_pvTaskGetThreadLocalStoragePointer. */ + ( UBaseType_t ) MPU_vTaskSetThreadLocalStoragePointerImpl, /* SYSTEM_CALL_vTaskSetThreadLocalStoragePointer. */ + ( UBaseType_t ) MPU_pvTaskGetThreadLocalStoragePointerImpl, /* SYSTEM_CALL_pvTaskGetThreadLocalStoragePointer. */ #else - ( UBaseType_t ) 0, /* SYSTEM_CALL_vTaskSetThreadLocalStoragePointer. */ - ( UBaseType_t ) 0, /* SYSTEM_CALL_pvTaskGetThreadLocalStoragePointer. */ + ( UBaseType_t ) 0, /* SYSTEM_CALL_vTaskSetThreadLocalStoragePointer. */ + ( UBaseType_t ) 0, /* SYSTEM_CALL_pvTaskGetThreadLocalStoragePointer. */ #endif #if ( configUSE_TRACE_FACILITY == 1 ) - ( UBaseType_t ) MPU_uxTaskGetSystemStateImpl, /* SYSTEM_CALL_uxTaskGetSystemState. */ + ( UBaseType_t ) MPU_uxTaskGetSystemStateImpl, /* SYSTEM_CALL_uxTaskGetSystemState. */ #else - ( UBaseType_t ) 0, /* SYSTEM_CALL_uxTaskGetSystemState. */ + ( UBaseType_t ) 0, /* SYSTEM_CALL_uxTaskGetSystemState. */ #endif #if ( INCLUDE_uxTaskGetStackHighWaterMark == 1 ) - ( UBaseType_t ) MPU_uxTaskGetStackHighWaterMarkImpl, /* SYSTEM_CALL_uxTaskGetStackHighWaterMark. */ + ( UBaseType_t ) MPU_uxTaskGetStackHighWaterMarkImpl, /* SYSTEM_CALL_uxTaskGetStackHighWaterMark. */ #else - ( UBaseType_t ) 0, /* SYSTEM_CALL_uxTaskGetStackHighWaterMark. */ + ( UBaseType_t ) 0, /* SYSTEM_CALL_uxTaskGetStackHighWaterMark. */ #endif #if ( INCLUDE_uxTaskGetStackHighWaterMark2 == 1 ) - ( UBaseType_t ) MPU_uxTaskGetStackHighWaterMark2Impl, /* SYSTEM_CALL_uxTaskGetStackHighWaterMark2. */ + ( UBaseType_t ) MPU_uxTaskGetStackHighWaterMark2Impl, /* SYSTEM_CALL_uxTaskGetStackHighWaterMark2. */ #else - ( UBaseType_t ) 0, /* SYSTEM_CALL_uxTaskGetStackHighWaterMark2. */ + ( UBaseType_t ) 0, /* SYSTEM_CALL_uxTaskGetStackHighWaterMark2. */ #endif #if ( ( INCLUDE_xTaskGetCurrentTaskHandle == 1 ) || ( configUSE_MUTEXES == 1 ) ) - ( UBaseType_t ) MPU_xTaskGetCurrentTaskHandleImpl, /* SYSTEM_CALL_xTaskGetCurrentTaskHandle. */ + ( UBaseType_t ) MPU_xTaskGetCurrentTaskHandleImpl, /* SYSTEM_CALL_xTaskGetCurrentTaskHandle. */ #else - ( UBaseType_t ) 0, /* SYSTEM_CALL_xTaskGetCurrentTaskHandle. */ + ( UBaseType_t ) 0, /* SYSTEM_CALL_xTaskGetCurrentTaskHandle. */ #endif #if ( INCLUDE_xTaskGetSchedulerState == 1 ) - ( UBaseType_t ) MPU_xTaskGetSchedulerStateImpl, /* SYSTEM_CALL_xTaskGetSchedulerState. */ + ( UBaseType_t ) MPU_xTaskGetSchedulerStateImpl, /* SYSTEM_CALL_xTaskGetSchedulerState. */ #else - ( UBaseType_t ) 0, /* SYSTEM_CALL_xTaskGetSchedulerState. */ + ( UBaseType_t ) 0, /* SYSTEM_CALL_xTaskGetSchedulerState. */ #endif - ( UBaseType_t ) MPU_vTaskSetTimeOutStateImpl, /* SYSTEM_CALL_vTaskSetTimeOutState. */ - ( UBaseType_t ) MPU_xTaskCheckForTimeOutImpl, /* SYSTEM_CALL_xTaskCheckForTimeOut. */ + ( UBaseType_t ) MPU_vTaskSetTimeOutStateImpl, /* SYSTEM_CALL_vTaskSetTimeOutState. */ + ( UBaseType_t ) MPU_xTaskCheckForTimeOutImpl, /* SYSTEM_CALL_xTaskCheckForTimeOut. */ #if ( configUSE_TASK_NOTIFICATIONS == 1 ) - ( UBaseType_t ) MPU_ulTaskGenericNotifyTakeImpl, /* SYSTEM_CALL_ulTaskGenericNotifyTake. */ - ( UBaseType_t ) MPU_xTaskGenericNotifyStateClearImpl, /* SYSTEM_CALL_xTaskGenericNotifyStateClear. */ - ( UBaseType_t ) MPU_ulTaskGenericNotifyValueClearImpl, /* SYSTEM_CALL_ulTaskGenericNotifyValueClear. */ + ( UBaseType_t ) MPU_ulTaskGenericNotifyTakeImpl, /* SYSTEM_CALL_ulTaskGenericNotifyTake. */ + ( UBaseType_t ) MPU_xTaskGenericNotifyStateClearImpl, /* SYSTEM_CALL_xTaskGenericNotifyStateClear. */ + ( UBaseType_t ) MPU_ulTaskGenericNotifyValueClearImpl, /* SYSTEM_CALL_ulTaskGenericNotifyValueClear. */ #else - ( UBaseType_t ) 0, /* SYSTEM_CALL_ulTaskGenericNotifyTake. */ - ( UBaseType_t ) 0, /* SYSTEM_CALL_xTaskGenericNotifyStateClear. */ - ( UBaseType_t ) 0, /* SYSTEM_CALL_ulTaskGenericNotifyValueClear. */ + ( UBaseType_t ) 0, /* SYSTEM_CALL_ulTaskGenericNotifyTake. */ + ( UBaseType_t ) 0, /* SYSTEM_CALL_xTaskGenericNotifyStateClear. */ + ( UBaseType_t ) 0, /* SYSTEM_CALL_ulTaskGenericNotifyValueClear. */ #endif - ( UBaseType_t ) MPU_xQueueGenericSendImpl, /* SYSTEM_CALL_xQueueGenericSend. */ - ( UBaseType_t ) MPU_uxQueueMessagesWaitingImpl, /* SYSTEM_CALL_uxQueueMessagesWaiting. */ - ( UBaseType_t ) MPU_uxQueueSpacesAvailableImpl, /* SYSTEM_CALL_uxQueueSpacesAvailable. */ - ( UBaseType_t ) MPU_xQueueReceiveImpl, /* SYSTEM_CALL_xQueueReceive. */ - ( UBaseType_t ) MPU_xQueuePeekImpl, /* SYSTEM_CALL_xQueuePeek. */ - ( UBaseType_t ) MPU_xQueueSemaphoreTakeImpl, /* SYSTEM_CALL_xQueueSemaphoreTake. */ + ( UBaseType_t ) MPU_xQueueGenericSendImpl, /* SYSTEM_CALL_xQueueGenericSend. */ + ( UBaseType_t ) MPU_uxQueueMessagesWaitingImpl, /* SYSTEM_CALL_uxQueueMessagesWaiting. */ + ( UBaseType_t ) MPU_uxQueueSpacesAvailableImpl, /* SYSTEM_CALL_uxQueueSpacesAvailable. */ + ( UBaseType_t ) MPU_xQueueReceiveImpl, /* SYSTEM_CALL_xQueueReceive. */ + ( UBaseType_t ) MPU_xQueuePeekImpl, /* SYSTEM_CALL_xQueuePeek. */ + ( UBaseType_t ) MPU_xQueueSemaphoreTakeImpl, /* SYSTEM_CALL_xQueueSemaphoreTake. */ #if ( ( configUSE_MUTEXES == 1 ) && ( INCLUDE_xSemaphoreGetMutexHolder == 1 ) ) - ( UBaseType_t ) MPU_xQueueGetMutexHolderImpl, /* SYSTEM_CALL_xQueueGetMutexHolder. */ + ( UBaseType_t ) MPU_xQueueGetMutexHolderImpl, /* SYSTEM_CALL_xQueueGetMutexHolder. */ #else - ( UBaseType_t ) 0, /* SYSTEM_CALL_xQueueGetMutexHolder. */ + ( UBaseType_t ) 0, /* SYSTEM_CALL_xQueueGetMutexHolder. */ #endif #if ( configUSE_RECURSIVE_MUTEXES == 1 ) - ( UBaseType_t ) MPU_xQueueTakeMutexRecursiveImpl, /* SYSTEM_CALL_xQueueTakeMutexRecursive. */ - ( UBaseType_t ) MPU_xQueueGiveMutexRecursiveImpl, /* SYSTEM_CALL_xQueueGiveMutexRecursive. */ + ( UBaseType_t ) MPU_xQueueTakeMutexRecursiveImpl, /* SYSTEM_CALL_xQueueTakeMutexRecursive. */ + ( UBaseType_t ) MPU_xQueueGiveMutexRecursiveImpl, /* SYSTEM_CALL_xQueueGiveMutexRecursive. */ #else - ( UBaseType_t ) 0, /* SYSTEM_CALL_xQueueTakeMutexRecursive. */ - ( UBaseType_t ) 0, /* SYSTEM_CALL_xQueueGiveMutexRecursive. */ + ( UBaseType_t ) 0, /* SYSTEM_CALL_xQueueTakeMutexRecursive. */ + ( UBaseType_t ) 0, /* SYSTEM_CALL_xQueueGiveMutexRecursive. */ #endif #if ( configUSE_QUEUE_SETS == 1 ) - ( UBaseType_t ) MPU_xQueueSelectFromSetImpl, /* SYSTEM_CALL_xQueueSelectFromSet. */ - ( UBaseType_t ) MPU_xQueueAddToSetImpl, /* SYSTEM_CALL_xQueueAddToSet. */ + ( UBaseType_t ) MPU_xQueueSelectFromSetImpl, /* SYSTEM_CALL_xQueueSelectFromSet. */ + ( UBaseType_t ) MPU_xQueueAddToSetImpl, /* SYSTEM_CALL_xQueueAddToSet. */ #else - ( UBaseType_t ) 0, /* SYSTEM_CALL_xQueueSelectFromSet. */ - ( UBaseType_t ) 0, /* SYSTEM_CALL_xQueueAddToSet. */ + ( UBaseType_t ) 0, /* SYSTEM_CALL_xQueueSelectFromSet. */ + ( UBaseType_t ) 0, /* SYSTEM_CALL_xQueueAddToSet. */ #endif #if configQUEUE_REGISTRY_SIZE > 0 - ( UBaseType_t ) MPU_vQueueAddToRegistryImpl, /* SYSTEM_CALL_vQueueAddToRegistry. */ - ( UBaseType_t ) MPU_vQueueUnregisterQueueImpl, /* SYSTEM_CALL_vQueueUnregisterQueue. */ - ( UBaseType_t ) MPU_pcQueueGetNameImpl, /* SYSTEM_CALL_pcQueueGetName. */ + ( UBaseType_t ) MPU_vQueueAddToRegistryImpl, /* SYSTEM_CALL_vQueueAddToRegistry. */ + ( UBaseType_t ) MPU_vQueueUnregisterQueueImpl, /* SYSTEM_CALL_vQueueUnregisterQueue. */ + ( UBaseType_t ) MPU_pcQueueGetNameImpl, /* SYSTEM_CALL_pcQueueGetName. */ #else - ( UBaseType_t ) 0, /* SYSTEM_CALL_vQueueAddToRegistry. */ - ( UBaseType_t ) 0, /* SYSTEM_CALL_vQueueUnregisterQueue. */ - ( UBaseType_t ) 0, /* SYSTEM_CALL_pcQueueGetName. */ + ( UBaseType_t ) 0, /* SYSTEM_CALL_vQueueAddToRegistry. */ + ( UBaseType_t ) 0, /* SYSTEM_CALL_vQueueUnregisterQueue. */ + ( UBaseType_t ) 0, /* SYSTEM_CALL_pcQueueGetName. */ #endif #if ( configUSE_TIMERS == 1 ) - ( UBaseType_t ) MPU_pvTimerGetTimerIDImpl, /* SYSTEM_CALL_pvTimerGetTimerID. */ - ( UBaseType_t ) MPU_vTimerSetTimerIDImpl, /* SYSTEM_CALL_vTimerSetTimerID. */ - ( UBaseType_t ) MPU_xTimerIsTimerActiveImpl, /* SYSTEM_CALL_xTimerIsTimerActive. */ - ( UBaseType_t ) MPU_xTimerGetTimerDaemonTaskHandleImpl, /* SYSTEM_CALL_xTimerGetTimerDaemonTaskHandle. */ - ( UBaseType_t ) MPU_pcTimerGetNameImpl, /* SYSTEM_CALL_pcTimerGetName. */ - ( UBaseType_t ) MPU_vTimerSetReloadModeImpl, /* SYSTEM_CALL_vTimerSetReloadMode. */ - ( UBaseType_t ) MPU_xTimerGetReloadModeImpl, /* SYSTEM_CALL_xTimerGetReloadMode. */ - ( UBaseType_t ) MPU_uxTimerGetReloadModeImpl, /* SYSTEM_CALL_uxTimerGetReloadMode. */ - ( UBaseType_t ) MPU_xTimerGetPeriodImpl, /* SYSTEM_CALL_xTimerGetPeriod. */ - ( UBaseType_t ) MPU_xTimerGetExpiryTimeImpl, /* SYSTEM_CALL_xTimerGetExpiryTime. */ - #else /* if ( configUSE_TIMERS == 1 ) */ - ( UBaseType_t ) 0, /* SYSTEM_CALL_pvTimerGetTimerID. */ - ( UBaseType_t ) 0, /* SYSTEM_CALL_vTimerSetTimerID. */ - ( UBaseType_t ) 0, /* SYSTEM_CALL_xTimerIsTimerActive. */ - ( UBaseType_t ) 0, /* SYSTEM_CALL_xTimerGetTimerDaemonTaskHandle. */ - ( UBaseType_t ) 0, /* SYSTEM_CALL_pcTimerGetName. */ - ( UBaseType_t ) 0, /* SYSTEM_CALL_vTimerSetReloadMode. */ - ( UBaseType_t ) 0, /* SYSTEM_CALL_xTimerGetReloadMode. */ - ( UBaseType_t ) 0, /* SYSTEM_CALL_uxTimerGetReloadMode. */ - ( UBaseType_t ) 0, /* SYSTEM_CALL_xTimerGetPeriod. */ - ( UBaseType_t ) 0, /* SYSTEM_CALL_xTimerGetExpiryTime. */ - #endif /* if ( configUSE_TIMERS == 1 ) */ - - ( UBaseType_t ) MPU_xEventGroupClearBitsImpl, /* SYSTEM_CALL_xEventGroupClearBits. */ - ( UBaseType_t ) MPU_xEventGroupSetBitsImpl, /* SYSTEM_CALL_xEventGroupSetBits. */ - ( UBaseType_t ) MPU_xEventGroupSyncImpl, /* SYSTEM_CALL_xEventGroupSync. */ + ( UBaseType_t ) MPU_pvTimerGetTimerIDImpl, /* SYSTEM_CALL_pvTimerGetTimerID. */ + ( UBaseType_t ) MPU_vTimerSetTimerIDImpl, /* SYSTEM_CALL_vTimerSetTimerID. */ + ( UBaseType_t ) MPU_xTimerIsTimerActiveImpl, /* SYSTEM_CALL_xTimerIsTimerActive. */ + ( UBaseType_t ) MPU_xTimerGetTimerDaemonTaskHandleImpl, /* SYSTEM_CALL_xTimerGetTimerDaemonTaskHandle. */ + ( UBaseType_t ) MPU_pcTimerGetNameImpl, /* SYSTEM_CALL_pcTimerGetName. */ + ( UBaseType_t ) MPU_vTimerSetReloadModeImpl, /* SYSTEM_CALL_vTimerSetReloadMode. */ + ( UBaseType_t ) MPU_xTimerGetReloadModeImpl, /* SYSTEM_CALL_xTimerGetReloadMode. */ + ( UBaseType_t ) MPU_uxTimerGetReloadModeImpl, /* SYSTEM_CALL_uxTimerGetReloadMode. */ + ( UBaseType_t ) MPU_xTimerGetPeriodImpl, /* SYSTEM_CALL_xTimerGetPeriod. */ + ( UBaseType_t ) MPU_xTimerGetExpiryTimeImpl, /* SYSTEM_CALL_xTimerGetExpiryTime. */ + #else + ( UBaseType_t ) 0, /* SYSTEM_CALL_pvTimerGetTimerID. */ + ( UBaseType_t ) 0, /* SYSTEM_CALL_vTimerSetTimerID. */ + ( UBaseType_t ) 0, /* SYSTEM_CALL_xTimerIsTimerActive. */ + ( UBaseType_t ) 0, /* SYSTEM_CALL_xTimerGetTimerDaemonTaskHandle. */ + ( UBaseType_t ) 0, /* SYSTEM_CALL_pcTimerGetName. */ + ( UBaseType_t ) 0, /* SYSTEM_CALL_vTimerSetReloadMode. */ + ( UBaseType_t ) 0, /* SYSTEM_CALL_xTimerGetReloadMode. */ + ( UBaseType_t ) 0, /* SYSTEM_CALL_uxTimerGetReloadMode. */ + ( UBaseType_t ) 0, /* SYSTEM_CALL_xTimerGetPeriod. */ + ( UBaseType_t ) 0, /* SYSTEM_CALL_xTimerGetExpiryTime. */ + #endif + + ( UBaseType_t ) MPU_xEventGroupClearBitsImpl, /* SYSTEM_CALL_xEventGroupClearBits. */ + ( UBaseType_t ) MPU_xEventGroupSetBitsImpl, /* SYSTEM_CALL_xEventGroupSetBits. */ + ( UBaseType_t ) MPU_xEventGroupSyncImpl, /* SYSTEM_CALL_xEventGroupSync. */ #if ( configUSE_TRACE_FACILITY == 1 ) - ( UBaseType_t ) MPU_uxEventGroupGetNumberImpl, /* SYSTEM_CALL_uxEventGroupGetNumber. */ - ( UBaseType_t ) MPU_vEventGroupSetNumberImpl, /* SYSTEM_CALL_vEventGroupSetNumber. */ + ( UBaseType_t ) MPU_uxEventGroupGetNumberImpl, /* SYSTEM_CALL_uxEventGroupGetNumber. */ + ( UBaseType_t ) MPU_vEventGroupSetNumberImpl, /* SYSTEM_CALL_vEventGroupSetNumber. */ #else - ( UBaseType_t ) 0, /* SYSTEM_CALL_uxEventGroupGetNumber. */ - ( UBaseType_t ) 0, /* SYSTEM_CALL_vEventGroupSetNumber. */ + ( UBaseType_t ) 0, /* SYSTEM_CALL_uxEventGroupGetNumber. */ + ( UBaseType_t ) 0, /* SYSTEM_CALL_vEventGroupSetNumber. */ #endif - ( UBaseType_t ) MPU_xStreamBufferSendImpl, /* SYSTEM_CALL_xStreamBufferSend. */ - ( UBaseType_t ) MPU_xStreamBufferReceiveImpl, /* SYSTEM_CALL_xStreamBufferReceive. */ - ( UBaseType_t ) MPU_xStreamBufferIsFullImpl, /* SYSTEM_CALL_xStreamBufferIsFull. */ - ( UBaseType_t ) MPU_xStreamBufferIsEmptyImpl, /* SYSTEM_CALL_xStreamBufferIsEmpty. */ - ( UBaseType_t ) MPU_xStreamBufferSpacesAvailableImpl, /* SYSTEM_CALL_xStreamBufferSpacesAvailable. */ - ( UBaseType_t ) MPU_xStreamBufferBytesAvailableImpl, /* SYSTEM_CALL_xStreamBufferBytesAvailable. */ - ( UBaseType_t ) MPU_xStreamBufferSetTriggerLevelImpl, /* SYSTEM_CALL_xStreamBufferSetTriggerLevel. */ - ( UBaseType_t ) MPU_xStreamBufferNextMessageLengthBytesImpl /* SYSTEM_CALL_xStreamBufferNextMessageLengthBytes. */ + ( UBaseType_t ) MPU_xStreamBufferSendImpl, /* SYSTEM_CALL_xStreamBufferSend. */ + ( UBaseType_t ) MPU_xStreamBufferReceiveImpl, /* SYSTEM_CALL_xStreamBufferReceive. */ + ( UBaseType_t ) MPU_xStreamBufferIsFullImpl, /* SYSTEM_CALL_xStreamBufferIsFull. */ + ( UBaseType_t ) MPU_xStreamBufferIsEmptyImpl, /* SYSTEM_CALL_xStreamBufferIsEmpty. */ + ( UBaseType_t ) MPU_xStreamBufferSpacesAvailableImpl, /* SYSTEM_CALL_xStreamBufferSpacesAvailable. */ + ( UBaseType_t ) MPU_xStreamBufferBytesAvailableImpl, /* SYSTEM_CALL_xStreamBufferBytesAvailable. */ + ( UBaseType_t ) MPU_xStreamBufferSetTriggerLevelImpl, /* SYSTEM_CALL_xStreamBufferSetTriggerLevel. */ + ( UBaseType_t ) MPU_xStreamBufferNextMessageLengthBytesImpl /* SYSTEM_CALL_xStreamBufferNextMessageLengthBytes. */ }; /*-----------------------------------------------------------*/ diff --git a/Source/portable/GCC/ARM7_AT91FR40008/port.c b/Source/portable/GCC/ARM7_AT91FR40008/port.c index 19463b0cd..f36c2ab92 100644 --- a/Source/portable/GCC/ARM7_AT91FR40008/port.c +++ b/Source/portable/GCC/ARM7_AT91FR40008/port.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -28,13 +28,13 @@ /*----------------------------------------------------------- - * Implementation of functions defined in portable.h for the Atmel AT91R40008 - * port. - * - * Components that can be compiled to either ARM or THUMB mode are - * contained in this file. The ISR routines, which can only be compiled - * to ARM mode are contained in portISR.c. - *----------------------------------------------------------*/ +* Implementation of functions defined in portable.h for the Atmel AT91R40008 +* port. +* +* Components that can be compiled to either ARM or THUMB mode are +* contained in this file. The ISR routines, which can only be compiled +* to ARM mode are contained in portISR.c. +*----------------------------------------------------------*/ /* Standard includes. */ #include @@ -50,11 +50,11 @@ #include "tc.h" /* Constants required to setup the task context. */ -#define portINITIAL_SPSR ( ( StackType_t ) 0x1f ) /* System mode, ARM mode, interrupts enabled. */ -#define portTHUMB_MODE_BIT ( ( StackType_t ) 0x20 ) -#define portINSTRUCTION_SIZE ( ( StackType_t ) 4 ) -#define portNO_CRITICAL_SECTION_NESTING ( ( StackType_t ) 0 ) -#define portTICK_PRIORITY_6 ( 6 ) +#define portINITIAL_SPSR ( ( StackType_t ) 0x1f ) /* System mode, ARM mode, interrupts enabled. */ +#define portTHUMB_MODE_BIT ( ( StackType_t ) 0x20 ) +#define portINSTRUCTION_SIZE ( ( StackType_t ) 4 ) +#define portNO_CRITICAL_SECTION_NESTING ( ( StackType_t ) 0 ) +#define portTICK_PRIORITY_6 ( 6 ) /*-----------------------------------------------------------*/ /* Setup the timer to generate the tick interrupts. */ @@ -74,61 +74,63 @@ extern void vPortISRStartFirstTask( void ); * * See header file for description. */ -StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters ) +StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, + TaskFunction_t pxCode, + void * pvParameters ) { -StackType_t *pxOriginalTOS; + StackType_t * pxOriginalTOS; pxOriginalTOS = pxTopOfStack; /* To ensure asserts in tasks.c don't fail, although in this case the assert - is not really required. */ + * is not really required. */ pxTopOfStack--; /* Setup the initial stack of the task. The stack is set exactly as - expected by the portRESTORE_CONTEXT() macro. */ + * expected by the portRESTORE_CONTEXT() macro. */ /* First on the stack is the return address - which in this case is the - start of the task. The offset is added to make the return address appear - as it would within an IRQ ISR. */ + * start of the task. The offset is added to make the return address appear + * as it would within an IRQ ISR. */ *pxTopOfStack = ( StackType_t ) pxCode + portINSTRUCTION_SIZE; pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0xaaaaaaaa; /* R14 */ + *pxTopOfStack = ( StackType_t ) 0xaaaaaaaa; /* R14 */ pxTopOfStack--; *pxTopOfStack = ( StackType_t ) pxOriginalTOS; /* Stack used when task starts goes in R13. */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x12121212; /* R12 */ + *pxTopOfStack = ( StackType_t ) 0x12121212; /* R12 */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x11111111; /* R11 */ + *pxTopOfStack = ( StackType_t ) 0x11111111; /* R11 */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x10101010; /* R10 */ + *pxTopOfStack = ( StackType_t ) 0x10101010; /* R10 */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x09090909; /* R9 */ + *pxTopOfStack = ( StackType_t ) 0x09090909; /* R9 */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x08080808; /* R8 */ + *pxTopOfStack = ( StackType_t ) 0x08080808; /* R8 */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x07070707; /* R7 */ + *pxTopOfStack = ( StackType_t ) 0x07070707; /* R7 */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x06060606; /* R6 */ + *pxTopOfStack = ( StackType_t ) 0x06060606; /* R6 */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x05050505; /* R5 */ + *pxTopOfStack = ( StackType_t ) 0x05050505; /* R5 */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x04040404; /* R4 */ + *pxTopOfStack = ( StackType_t ) 0x04040404; /* R4 */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x03030303; /* R3 */ + *pxTopOfStack = ( StackType_t ) 0x03030303; /* R3 */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x02020202; /* R2 */ + *pxTopOfStack = ( StackType_t ) 0x02020202; /* R2 */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x01010101; /* R1 */ + *pxTopOfStack = ( StackType_t ) 0x01010101; /* R1 */ pxTopOfStack--; /* When the task starts is will expect to find the function parameter in - R0. */ + * R0. */ *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */ pxTopOfStack--; /* The last thing onto the stack is the status register, which is set for - system mode, with interrupts enabled. */ + * system mode, with interrupts enabled. */ *pxTopOfStack = ( StackType_t ) portINITIAL_SPSR; #ifdef THUMB_INTERWORK @@ -141,9 +143,9 @@ StackType_t *pxOriginalTOS; pxTopOfStack--; /* Some optimisation levels use the stack differently to others. This - means the interrupt flags cannot always be stored on the stack and will - instead be stored in a variable, which is then saved as part of the - tasks context. */ + * means the interrupt flags cannot always be stored on the stack and will + * instead be stored in a variable, which is then saved as part of the + * tasks context. */ *pxTopOfStack = portNO_CRITICAL_SECTION_NESTING; return pxTopOfStack; @@ -153,7 +155,7 @@ StackType_t *pxOriginalTOS; BaseType_t xPortStartScheduler( void ) { /* Start the timer that generates the tick ISR. Interrupts are disabled - here already. */ + * here already. */ prvSetupTimerInterrupt(); /* Start the first task. */ @@ -167,7 +169,7 @@ BaseType_t xPortStartScheduler( void ) void vPortEndScheduler( void ) { /* It is unlikely that the ARM port will require this function as there - is nothing to return to. */ + * is nothing to return to. */ } /*-----------------------------------------------------------*/ @@ -176,7 +178,7 @@ void vPortEndScheduler( void ) */ static void prvSetupTimerInterrupt( void ) { -volatile uint32_t ulDummy; + volatile uint32_t ulDummy; /* Enable clock to the tick timer... */ AT91C_BASE_PS->PS_PCER = portTIMER_CLK_ENABLE_BIT; @@ -191,17 +193,17 @@ volatile uint32_t ulDummy; ulDummy = portTIMER_REG_BASE_PTR->TC_SR; /* Store interrupt handler function address in tick timer vector register... - The ISR installed depends on whether the preemptive or cooperative - scheduler is being used. */ + * The ISR installed depends on whether the preemptive or cooperative + * scheduler is being used. */ #if configUSE_PREEMPTION == 1 { - extern void ( vPreemptiveTick )( void ); - AT91C_BASE_AIC->AIC_SVR[portTIMER_AIC_CHANNEL] = ( uint32_t ) vPreemptiveTick; + extern void( vPreemptiveTick )( void ); + AT91C_BASE_AIC->AIC_SVR[ portTIMER_AIC_CHANNEL ] = ( uint32_t ) vPreemptiveTick; } - #else // else use cooperative scheduler + #else // else use cooperative scheduler { - extern void ( vNonPreemptiveTick )( void ); - AT91C_BASE_AIC->AIC_SVR[portTIMER_AIC_CHANNEL] = ( uint32_t ) vNonPreemptiveTick; + extern void( vNonPreemptiveTick )( void ); + AT91C_BASE_AIC->AIC_SVR[ portTIMER_AIC_CHANNEL ] = ( uint32_t ) vNonPreemptiveTick; } #endif @@ -209,27 +211,27 @@ volatile uint32_t ulDummy; AT91C_BASE_AIC->AIC_SMR[ portTIMER_AIC_CHANNEL ] = AIC_SRCTYPE_INT_LEVEL_SENSITIVE | portTICK_PRIORITY_6; /* Enable the tick timer interrupt... - - First at timer level */ + * + * First at timer level */ portTIMER_REG_BASE_PTR->TC_IER = TC_CPCS; /* Then at the AIC level. */ - AT91C_BASE_AIC->AIC_IECR = (1 << portTIMER_AIC_CHANNEL); + AT91C_BASE_AIC->AIC_IECR = ( 1 << portTIMER_AIC_CHANNEL ); /* Calculate timer compare value to achieve the desired tick rate... */ - if( (configCPU_CLOCK_HZ / (configTICK_RATE_HZ * 2) ) <= 0xFFFF ) + if( ( configCPU_CLOCK_HZ / ( configTICK_RATE_HZ * 2 ) ) <= 0xFFFF ) { /* The tick rate is fast enough for us to use the faster timer input - clock (main clock / 2). */ + * clock (main clock / 2). */ portTIMER_REG_BASE_PTR->TC_CMR = TC_WAVE | TC_CLKS_MCK2 | TC_BURST_NONE | TC_CPCTRG; - portTIMER_REG_BASE_PTR->TC_RC = configCPU_CLOCK_HZ / (configTICK_RATE_HZ * 2); + portTIMER_REG_BASE_PTR->TC_RC = configCPU_CLOCK_HZ / ( configTICK_RATE_HZ * 2 ); } else { /* We must use a slower timer input clock (main clock / 8) because the - tick rate is too slow for the faster input clock. */ + * tick rate is too slow for the faster input clock. */ portTIMER_REG_BASE_PTR->TC_CMR = TC_WAVE | TC_CLKS_MCK8 | TC_BURST_NONE | TC_CPCTRG; - portTIMER_REG_BASE_PTR->TC_RC = configCPU_CLOCK_HZ / (configTICK_RATE_HZ * 8); + portTIMER_REG_BASE_PTR->TC_RC = configCPU_CLOCK_HZ / ( configTICK_RATE_HZ * 8 ); } /* Start tick timer... */ diff --git a/Source/portable/GCC/ARM7_AT91FR40008/portISR.c b/Source/portable/GCC/ARM7_AT91FR40008/portISR.c index 923186a82..c5b711596 100644 --- a/Source/portable/GCC/ARM7_AT91FR40008/portISR.c +++ b/Source/portable/GCC/ARM7_AT91FR40008/portISR.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -28,17 +28,17 @@ /*----------------------------------------------------------- - * Components that can be compiled to either ARM or THUMB mode are - * contained in port.c The ISR routines, which can only be compiled - * to ARM mode, are contained in this file. - *----------------------------------------------------------*/ +* Components that can be compiled to either ARM or THUMB mode are +* contained in port.c The ISR routines, which can only be compiled +* to ARM mode, are contained in this file. +*----------------------------------------------------------*/ /* - Changes from V3.2.4 - - + The assembler statements are now included in a single asm block rather - than each line having its own asm block. -*/ + * Changes from V3.2.4 + * + + The assembler statements are now included in a single asm block rather + + than each line having its own asm block. + */ /* Scheduler includes. */ @@ -46,16 +46,16 @@ #include "task.h" /* Constants required to handle interrupts. */ -#define portCLEAR_AIC_INTERRUPT ( ( uint32_t ) 0 ) +#define portCLEAR_AIC_INTERRUPT ( ( uint32_t ) 0 ) /* Constants required to handle critical sections. */ -#define portNO_CRITICAL_NESTING ( ( uint32_t ) 0 ) +#define portNO_CRITICAL_NESTING ( ( uint32_t ) 0 ) volatile uint32_t ulCriticalNesting = 9999UL; /*-----------------------------------------------------------*/ /* ISR to handle manual context switches (from a call to taskYIELD()). */ -void vPortYieldProcessor( void ) __attribute__((interrupt("SWI"), naked)); +void vPortYieldProcessor( void ) __attribute__( ( interrupt( "SWI" ), naked ) ); /* * The scheduler can only be started from ARM mode, hence the inclusion of this @@ -67,7 +67,7 @@ void vPortISRStartFirstTask( void ); void vPortISRStartFirstTask( void ) { /* Simply start the scheduler. This is included here as it can only be - called from ARM mode. */ + * called from ARM mode. */ portRESTORE_CONTEXT(); } /*-----------------------------------------------------------*/ @@ -83,8 +83,8 @@ void vPortISRStartFirstTask( void ) void vPortYieldProcessor( void ) { /* Within an IRQ ISR the link register has an offset from the true return - address, but an SWI ISR does not. Add the offset manually so the same - ISR return code can be used in both cases. */ + * address, but an SWI ISR does not. Add the offset manually so the same + * ISR return code can be used in both cases. */ asm volatile ( "ADD LR, LR, #4" ); /* Perform the context switch. First save the context of the current task. */ @@ -105,12 +105,12 @@ void vPortYieldProcessor( void ) #if configUSE_PREEMPTION == 0 - /* The cooperative scheduler requires a normal IRQ service routine to - simply increment the system tick. */ - void vNonPreemptiveTick( void ) __attribute__ ((interrupt ("IRQ"))); +/* The cooperative scheduler requires a normal IRQ service routine to + * simply increment the system tick. */ + void vNonPreemptiveTick( void ) __attribute__( ( interrupt( "IRQ" ) ) ); void vNonPreemptiveTick( void ) { - static volatile uint32_t ulDummy; + static volatile uint32_t ulDummy; /* Clear tick timer interrupt indication. */ ulDummy = portTIMER_REG_BASE_PTR->TC_SR; @@ -121,25 +121,25 @@ void vPortYieldProcessor( void ) AT91C_BASE_AIC->AIC_EOICR = portCLEAR_AIC_INTERRUPT; } -#else /* else preemption is turned on */ +#else /* else preemption is turned on */ - /* The preemptive scheduler is defined as "naked" as the full context is - saved on entry as part of the context switch. */ - void vPreemptiveTick( void ) __attribute__((naked)); +/* The preemptive scheduler is defined as "naked" as the full context is + * saved on entry as part of the context switch. */ + void vPreemptiveTick( void ) __attribute__( ( naked ) ); void vPreemptiveTick( void ) { /* Save the context of the interrupted task. */ portSAVE_CONTEXT(); /* WARNING - Do not use local (stack) variables here. Use globals - if you must! */ + * if you must! */ static volatile uint32_t ulDummy; /* Clear tick timer interrupt indication. */ ulDummy = portTIMER_REG_BASE_PTR->TC_SR; /* Increment the RTOS tick count, then look for the highest priority - task that is ready to run. */ + * task that is ready to run. */ if( xTaskIncrementTick() != pdFALSE ) { vTaskSwitchContext(); @@ -152,7 +152,7 @@ void vPortYieldProcessor( void ) portRESTORE_CONTEXT(); } -#endif +#endif /* if configUSE_PREEMPTION == 0 */ /*-----------------------------------------------------------*/ /* @@ -163,50 +163,50 @@ void vPortYieldProcessor( void ) */ #ifdef THUMB_INTERWORK - void vPortDisableInterruptsFromThumb( void ) __attribute__ ((naked)); - void vPortEnableInterruptsFromThumb( void ) __attribute__ ((naked)); + void vPortDisableInterruptsFromThumb( void ) __attribute__( ( naked ) ); + void vPortEnableInterruptsFromThumb( void ) __attribute__( ( naked ) ); void vPortDisableInterruptsFromThumb( void ) { asm volatile ( - "STMDB SP!, {R0} \n\t" /* Push R0. */ - "MRS R0, CPSR \n\t" /* Get CPSR. */ - "ORR R0, R0, #0xC0 \n\t" /* Disable IRQ, FIQ. */ - "MSR CPSR, R0 \n\t" /* Write back modified value. */ - "LDMIA SP!, {R0} \n\t" /* Pop R0. */ - "BX R14" ); /* Return back to thumb. */ + "STMDB SP!, {R0} \n\t" /* Push R0. */ + "MRS R0, CPSR \n\t" /* Get CPSR. */ + "ORR R0, R0, #0xC0 \n\t" /* Disable IRQ, FIQ. */ + "MSR CPSR, R0 \n\t" /* Write back modified value. */ + "LDMIA SP!, {R0} \n\t" /* Pop R0. */ + "BX R14" ); /* Return back to thumb. */ } void vPortEnableInterruptsFromThumb( void ) { asm volatile ( - "STMDB SP!, {R0} \n\t" /* Push R0. */ - "MRS R0, CPSR \n\t" /* Get CPSR. */ - "BIC R0, R0, #0xC0 \n\t" /* Enable IRQ, FIQ. */ - "MSR CPSR, R0 \n\t" /* Write back modified value. */ - "LDMIA SP!, {R0} \n\t" /* Pop R0. */ - "BX R14" ); /* Return back to thumb. */ + "STMDB SP!, {R0} \n\t" /* Push R0. */ + "MRS R0, CPSR \n\t" /* Get CPSR. */ + "BIC R0, R0, #0xC0 \n\t" /* Enable IRQ, FIQ. */ + "MSR CPSR, R0 \n\t" /* Write back modified value. */ + "LDMIA SP!, {R0} \n\t" /* Pop R0. */ + "BX R14" ); /* Return back to thumb. */ } #endif /* THUMB_INTERWORK */ /* The code generated by the GCC compiler uses the stack in different ways at -different optimisation levels. The interrupt flags can therefore not always -be saved to the stack. Instead the critical section nesting level is stored -in a variable, which is then saved as part of the stack context. */ + * different optimisation levels. The interrupt flags can therefore not always + * be saved to the stack. Instead the critical section nesting level is stored + * in a variable, which is then saved as part of the stack context. */ void vPortEnterCritical( void ) { /* Disable interrupts as per portDISABLE_INTERRUPTS(); */ asm volatile ( - "STMDB SP!, {R0} \n\t" /* Push R0. */ - "MRS R0, CPSR \n\t" /* Get CPSR. */ - "ORR R0, R0, #0xC0 \n\t" /* Disable IRQ, FIQ. */ - "MSR CPSR, R0 \n\t" /* Write back modified value. */ - "LDMIA SP!, {R0}" ); /* Pop R0. */ - - /* Now interrupts are disabled ulCriticalNesting can be accessed - directly. Increment ulCriticalNesting to keep a count of how many times - portENTER_CRITICAL() has been called. */ + "STMDB SP!, {R0} \n\t" /* Push R0. */ + "MRS R0, CPSR \n\t" /* Get CPSR. */ + "ORR R0, R0, #0xC0 \n\t" /* Disable IRQ, FIQ. */ + "MSR CPSR, R0 \n\t" /* Write back modified value. */ + "LDMIA SP!, {R0}" ); /* Pop R0. */ + + /* Now that interrupts are disabled, ulCriticalNesting can be accessed + * directly. Increment ulCriticalNesting to keep a count of how many times + * portENTER_CRITICAL() has been called. */ ulCriticalNesting++; } @@ -218,16 +218,16 @@ void vPortExitCritical( void ) ulCriticalNesting--; /* If the nesting level has reached zero then interrupts should be - re-enabled. */ + * re-enabled. */ if( ulCriticalNesting == portNO_CRITICAL_NESTING ) { /* Enable interrupts as per portEXIT_CRITICAL(). */ asm volatile ( - "STMDB SP!, {R0} \n\t" /* Push R0. */ - "MRS R0, CPSR \n\t" /* Get CPSR. */ - "BIC R0, R0, #0xC0 \n\t" /* Enable IRQ, FIQ. */ - "MSR CPSR, R0 \n\t" /* Write back modified value. */ - "LDMIA SP!, {R0}" ); /* Pop R0. */ + "STMDB SP!, {R0} \n\t" /* Push R0. */ + "MRS R0, CPSR \n\t" /* Get CPSR. */ + "BIC R0, R0, #0xC0 \n\t" /* Enable IRQ, FIQ. */ + "MSR CPSR, R0 \n\t" /* Write back modified value. */ + "LDMIA SP!, {R0}" ); /* Pop R0. */ } } } diff --git a/Source/portable/GCC/ARM7_AT91FR40008/portmacro.h b/Source/portable/GCC/ARM7_AT91FR40008/portmacro.h index 3a45ac93b..de761fe3d 100644 --- a/Source/portable/GCC/ARM7_AT91FR40008/portmacro.h +++ b/Source/portable/GCC/ARM7_AT91FR40008/portmacro.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -27,27 +27,27 @@ */ /* - Changes from V3.2.3 - - + Modified portENTER_SWITCHING_ISR() to allow use with GCC V4.0.1. - - Changes from V3.2.4 - - + Removed the use of the %0 parameter within the assembler macros and - replaced them with hard coded registers. This will ensure the - assembler does not select the link register as the temp register as - was occasionally happening previously. - - + The assembler statements are now included in a single asm block rather - than each line having its own asm block. - - Changes from V4.5.0 - - + Removed the portENTER_SWITCHING_ISR() and portEXIT_SWITCHING_ISR() macros - and replaced them with portYIELD_FROM_ISR() macro. Application code - should now make use of the portSAVE_CONTEXT() and portRESTORE_CONTEXT() - macros as per the V4.5.1 demo code. -*/ + * Changes from V3.2.3 + * + + Modified portENTER_SWITCHING_ISR() to allow use with GCC V4.0.1. + + + + Changes from V3.2.4 + + + + Removed the use of the %0 parameter within the assembler macros and + + replaced them with hard coded registers. This will ensure the + + assembler does not select the link register as the temp register as + + was occasionally happening previously. + + + + The assembler statements are now included in a single asm block rather + + than each line having its own asm block. + + + + Changes from V4.5.0 + + + + Removed the portENTER_SWITCHING_ISR() and portEXIT_SWITCHING_ISR() macros + + and replaced them with portYIELD_FROM_ISR() macro. Application code + + should now make use of the portSAVE_CONTEXT() and portRESTORE_CONTEXT() + + macros as per the V4.5.1 demo code. + */ #ifndef PORTMACRO_H #define PORTMACRO_H @@ -69,35 +69,35 @@ */ /* Type definitions. */ -#define portCHAR char -#define portFLOAT float -#define portDOUBLE double -#define portLONG long -#define portSHORT short -#define portSTACK_TYPE uint32_t -#define portBASE_TYPE long - -typedef portSTACK_TYPE StackType_t; -typedef long BaseType_t; -typedef unsigned long UBaseType_t; - -#if( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS ) - typedef uint16_t TickType_t; - #define portMAX_DELAY ( TickType_t ) 0xffff +#define portCHAR char +#define portFLOAT float +#define portDOUBLE double +#define portLONG long +#define portSHORT short +#define portSTACK_TYPE uint32_t +#define portBASE_TYPE long + +typedef portSTACK_TYPE StackType_t; +typedef long BaseType_t; +typedef unsigned long UBaseType_t; + +#if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS ) + typedef uint16_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffff #elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS ) - typedef uint32_t TickType_t; - #define portMAX_DELAY ( TickType_t ) ( 0xFFFFFFFFUL ) + typedef uint32_t TickType_t; + #define portMAX_DELAY ( TickType_t ) ( 0xFFFFFFFFUL ) #else #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width. #endif /*-----------------------------------------------------------*/ /* Hardware specifics. */ -#define portSTACK_GROWTH ( -1 ) -#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) -#define portBYTE_ALIGNMENT 8 -#define portYIELD() asm volatile ( "SWI 0" ) -#define portNOP() asm volatile ( "NOP" ) +#define portSTACK_GROWTH ( -1 ) +#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) +#define portBYTE_ALIGNMENT 8 +#define portYIELD() asm volatile ( "SWI 0" ) +#define portNOP() asm volatile ( "NOP" ) /* * These define the timer to use for generating the tick interrupt. @@ -118,90 +118,90 @@ typedef unsigned long UBaseType_t; * THUMB mode code will result in a compile time error. */ -#define portRESTORE_CONTEXT() \ -{ \ -extern volatile void * volatile pxCurrentTCB; \ -extern volatile uint32_t ulCriticalNesting; \ - \ - /* Set the LR to the task stack. */ \ - asm volatile ( \ - "LDR R0, =pxCurrentTCB \n\t" \ - "LDR R0, [R0] \n\t" \ - "LDR LR, [R0] \n\t" \ - \ - /* The critical nesting depth is the first item on the stack. */ \ - /* Load it into the ulCriticalNesting variable. */ \ - "LDR R0, =ulCriticalNesting \n\t" \ - "LDMFD LR!, {R1} \n\t" \ - "STR R1, [R0] \n\t" \ - \ - /* Get the SPSR from the stack. */ \ - "LDMFD LR!, {R0} \n\t" \ - "MSR SPSR, R0 \n\t" \ - \ - /* Restore all system mode registers for the task. */ \ - "LDMFD LR, {R0-R14}^ \n\t" \ - "NOP \n\t" \ - \ - /* Restore the return address. */ \ - "LDR LR, [LR, #+60] \n\t" \ - \ - /* And return - correcting the offset in the LR to obtain the */ \ - /* correct address. */ \ - "SUBS PC, LR, #4 \n\t" \ - ); \ - ( void ) ulCriticalNesting; \ - ( void ) pxCurrentTCB; \ -} +#define portRESTORE_CONTEXT() \ + { \ + extern volatile void * volatile pxCurrentTCB; \ + extern volatile uint32_t ulCriticalNesting; \ + \ + /* Set the LR to the task stack. */ \ + asm volatile ( \ + "LDR R0, =pxCurrentTCB \n\t" \ + "LDR R0, [R0] \n\t" \ + "LDR LR, [R0] \n\t" \ + \ + /* The critical nesting depth is the first item on the stack. */ \ + /* Load it into the ulCriticalNesting variable. */ \ + "LDR R0, =ulCriticalNesting \n\t" \ + "LDMFD LR!, {R1} \n\t" \ + "STR R1, [R0] \n\t" \ + \ + /* Get the SPSR from the stack. */ \ + "LDMFD LR!, {R0} \n\t" \ + "MSR SPSR, R0 \n\t" \ + \ + /* Restore all system mode registers for the task. */ \ + "LDMFD LR, {R0-R14}^ \n\t" \ + "NOP \n\t" \ + \ + /* Restore the return address. */ \ + "LDR LR, [LR, #+60] \n\t" \ + \ + /* And return - correcting the offset in the LR to obtain the */ \ + /* correct address. */ \ + "SUBS PC, LR, #4 \n\t" \ + ); \ + ( void ) ulCriticalNesting; \ + ( void ) pxCurrentTCB; \ + } /*-----------------------------------------------------------*/ -#define portSAVE_CONTEXT() \ -{ \ -extern volatile void * volatile pxCurrentTCB; \ -extern volatile uint32_t ulCriticalNesting; \ - \ - /* Push R0 as we are going to use the register. */ \ - asm volatile ( \ - "STMDB SP!, {R0} \n\t" \ - \ - /* Set R0 to point to the task stack pointer. */ \ - "STMDB SP,{SP}^ \n\t" \ - "NOP \n\t" \ - "SUB SP, SP, #4 \n\t" \ - "LDMIA SP!,{R0} \n\t" \ - \ - /* Push the return address onto the stack. */ \ - "STMDB R0!, {LR} \n\t" \ - \ - /* Now we have saved LR we can use it instead of R0. */ \ - "MOV LR, R0 \n\t" \ - \ - /* Pop R0 so we can save it onto the system mode stack. */ \ - "LDMIA SP!, {R0} \n\t" \ - \ - /* Push all the system mode registers onto the task stack. */ \ - "STMDB LR,{R0-LR}^ \n\t" \ - "NOP \n\t" \ - "SUB LR, LR, #60 \n\t" \ - \ - /* Push the SPSR onto the task stack. */ \ - "MRS R0, SPSR \n\t" \ - "STMDB LR!, {R0} \n\t" \ - \ - "LDR R0, =ulCriticalNesting \n\t" \ - "LDR R0, [R0] \n\t" \ - "STMDB LR!, {R0} \n\t" \ - \ - /* Store the new top of stack for the task. */ \ - "LDR R0, =pxCurrentTCB \n\t" \ - "LDR R0, [R0] \n\t" \ - "STR LR, [R0] \n\t" \ - ); \ - ( void ) ulCriticalNesting; \ - ( void ) pxCurrentTCB; \ -} +#define portSAVE_CONTEXT() \ + { \ + extern volatile void * volatile pxCurrentTCB; \ + extern volatile uint32_t ulCriticalNesting; \ + \ + /* Push R0 as we are going to use the register. */ \ + asm volatile ( \ + "STMDB SP!, {R0} \n\t" \ + \ + /* Set R0 to point to the task stack pointer. */ \ + "STMDB SP,{SP}^ \n\t" \ + "NOP \n\t" \ + "SUB SP, SP, #4 \n\t" \ + "LDMIA SP!,{R0} \n\t" \ + \ + /* Push the return address onto the stack. */ \ + "STMDB R0!, {LR} \n\t" \ + \ + /* Now we have saved LR we can use it instead of R0. */ \ + "MOV LR, R0 \n\t" \ + \ + /* Pop R0 so we can save it onto the system mode stack. */ \ + "LDMIA SP!, {R0} \n\t" \ + \ + /* Push all the system mode registers onto the task stack. */ \ + "STMDB LR,{R0-LR}^ \n\t" \ + "NOP \n\t" \ + "SUB LR, LR, #60 \n\t" \ + \ + /* Push the SPSR onto the task stack. */ \ + "MRS R0, SPSR \n\t" \ + "STMDB LR!, {R0} \n\t" \ + \ + "LDR R0, =ulCriticalNesting \n\t" \ + "LDR R0, [R0] \n\t" \ + "STMDB LR!, {R0} \n\t" \ + \ + /* Store the new top of stack for the task. */ \ + "LDR R0, =pxCurrentTCB \n\t" \ + "LDR R0, [R0] \n\t" \ + "STR LR, [R0] \n\t" \ + ); \ + ( void ) ulCriticalNesting; \ + ( void ) pxCurrentTCB; \ + } -#define portYIELD_FROM_ISR() vTaskSwitchContext() +#define portYIELD_FROM_ISR() vTaskSwitchContext() /* Critical section handling. */ @@ -214,43 +214,43 @@ extern volatile uint32_t ulCriticalNesting; \ #ifdef THUMB_INTERWORK - extern void vPortDisableInterruptsFromThumb( void ) __attribute__ ((naked)); - extern void vPortEnableInterruptsFromThumb( void ) __attribute__ ((naked)); + extern void vPortDisableInterruptsFromThumb( void ) __attribute__( ( naked ) ); + extern void vPortEnableInterruptsFromThumb( void ) __attribute__( ( naked ) ); #define portDISABLE_INTERRUPTS() vPortDisableInterruptsFromThumb() #define portENABLE_INTERRUPTS() vPortEnableInterruptsFromThumb() #else - #define portDISABLE_INTERRUPTS() \ - asm volatile ( \ - "STMDB SP!, {R0} \n\t" /* Push R0. */ \ - "MRS R0, CPSR \n\t" /* Get CPSR. */ \ - "ORR R0, R0, #0xC0 \n\t" /* Disable IRQ, FIQ. */ \ - "MSR CPSR, R0 \n\t" /* Write back modified value. */ \ - "LDMIA SP!, {R0} " ) /* Pop R0. */ - - #define portENABLE_INTERRUPTS() \ - asm volatile ( \ - "STMDB SP!, {R0} \n\t" /* Push R0. */ \ - "MRS R0, CPSR \n\t" /* Get CPSR. */ \ - "BIC R0, R0, #0xC0 \n\t" /* Enable IRQ, FIQ. */ \ - "MSR CPSR, R0 \n\t" /* Write back modified value. */ \ - "LDMIA SP!, {R0} " ) /* Pop R0. */ + #define portDISABLE_INTERRUPTS() \ + asm volatile ( \ + "STMDB SP!, {R0} \n\t" /* Push R0. */ \ + "MRS R0, CPSR \n\t" /* Get CPSR. */ \ + "ORR R0, R0, #0xC0 \n\t" /* Disable IRQ, FIQ. */ \ + "MSR CPSR, R0 \n\t" /* Write back modified value. */ \ + "LDMIA SP!, {R0} " ) /* Pop R0. */ + + #define portENABLE_INTERRUPTS() \ + asm volatile ( \ + "STMDB SP!, {R0} \n\t" /* Push R0. */ \ + "MRS R0, CPSR \n\t" /* Get CPSR. */ \ + "BIC R0, R0, #0xC0 \n\t" /* Enable IRQ, FIQ. */ \ + "MSR CPSR, R0 \n\t" /* Write back modified value. */ \ + "LDMIA SP!, {R0} " ) /* Pop R0. */ #endif /* THUMB_INTERWORK */ extern void vPortEnterCritical( void ); extern void vPortExitCritical( void ); -#define portENTER_CRITICAL() vPortEnterCritical(); -#define portEXIT_CRITICAL() vPortExitCritical(); +#define portENTER_CRITICAL() vPortEnterCritical(); +#define portEXIT_CRITICAL() vPortExitCritical(); /*-----------------------------------------------------------*/ /* Task function macros as described on the FreeRTOS.org WEB site. */ -#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters ) -#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters ) +#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters ) +#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters ) /* *INDENT-OFF* */ #ifdef __cplusplus diff --git a/Source/portable/GCC/ARM7_AT91SAM7S/AT91SAM7X256.h b/Source/portable/GCC/ARM7_AT91SAM7S/AT91SAM7X256.h index d44cb286e..a335e4ad2 100644 --- a/Source/portable/GCC/ARM7_AT91SAM7S/AT91SAM7X256.h +++ b/Source/portable/GCC/ARM7_AT91SAM7S/AT91SAM7X256.h @@ -1,2731 +1,2759 @@ -// ---------------------------------------------------------------------------- -// ATMEL Microcontroller Software Support - ROUSSET - -// ---------------------------------------------------------------------------- -// DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR -// IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF -// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE -// DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, -// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, -// OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF -// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING -// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, -// EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// ---------------------------------------------------------------------------- -// File Name : AT91SAM7X256.h -// Object : AT91SAM7X256 definitions -// Generated : AT91 SW Application Group 05/20/2005 (16:22:29) -// -// CVS Reference : /AT91SAM7X256.pl/1.11/Tue May 10 12:15:32 2005// -// CVS Reference : /SYS_SAM7X.pl/1.3/Tue Feb 1 17:01:43 2005// -// CVS Reference : /MC_SAM7X.pl/1.2/Fri May 20 14:13:04 2005// -// CVS Reference : /PMC_SAM7X.pl/1.4/Tue Feb 8 13:58:10 2005// -// CVS Reference : /RSTC_SAM7X.pl/1.1/Tue Feb 1 16:16:26 2005// -// CVS Reference : /UDP_SAM7X.pl/1.1/Tue May 10 11:35:35 2005// -// CVS Reference : /PWM_SAM7X.pl/1.1/Tue May 10 11:53:07 2005// -// CVS Reference : /AIC_6075B.pl/1.3/Fri May 20 14:01:30 2005// -// CVS Reference : /PIO_6057A.pl/1.2/Thu Feb 3 10:18:28 2005// -// CVS Reference : /RTTC_6081A.pl/1.2/Tue Nov 9 14:43:58 2004// -// CVS Reference : /PITC_6079A.pl/1.2/Tue Nov 9 14:43:56 2004// -// CVS Reference : /WDTC_6080A.pl/1.3/Tue Nov 9 14:44:00 2004// -// CVS Reference : /VREG_6085B.pl/1.1/Tue Feb 1 16:05:48 2005// -// CVS Reference : /PDC_6074C.pl/1.2/Thu Feb 3 08:48:54 2005// -// CVS Reference : /DBGU_6059D.pl/1.1/Mon Jan 31 13:15:32 2005// -// CVS Reference : /SPI_6088D.pl/1.3/Fri May 20 14:08:59 2005// -// CVS Reference : /US_6089C.pl/1.1/Mon Jul 12 18:23:26 2004// -// CVS Reference : /SSC_6078A.pl/1.1/Tue Jul 13 07:45:40 2004// -// CVS Reference : /TWI_6061A.pl/1.1/Tue Jul 13 07:38:06 2004// -// CVS Reference : /TC_6082A.pl/1.7/Fri Mar 11 12:52:17 2005// -// CVS Reference : /CAN_6019B.pl/1.1/Tue Mar 8 12:42:22 2005// -// CVS Reference : /EMACB_6119A.pl/1.5/Thu Feb 3 15:52:04 2005// -// CVS Reference : /ADC_6051C.pl/1.1/Fri Oct 17 09:12:38 2003// -// CVS Reference : /AES_6149A.pl/1.10/Mon Feb 7 09:44:25 2005// -// CVS Reference : /DES3_6150A.pl/1.1/Mon Jan 17 08:34:31 2005// -// ---------------------------------------------------------------------------- +/* ---------------------------------------------------------------------------- */ +/* ATMEL Microcontroller Software Support - ROUSSET - */ +/* ---------------------------------------------------------------------------- */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ +/* File Name : AT91SAM7X256.h */ +/* Object : AT91SAM7X256 definitions */ +/* Generated : AT91 SW Application Group 05/20/2005 (16:22:29) */ +/* */ +/* CVS Reference : /AT91SAM7X256.pl/1.11/Tue May 10 12:15:32 2005// */ +/* CVS Reference : /SYS_SAM7X.pl/1.3/Tue Feb 1 17:01:43 2005// */ +/* CVS Reference : /MC_SAM7X.pl/1.2/Fri May 20 14:13:04 2005// */ +/* CVS Reference : /PMC_SAM7X.pl/1.4/Tue Feb 8 13:58:10 2005// */ +/* CVS Reference : /RSTC_SAM7X.pl/1.1/Tue Feb 1 16:16:26 2005// */ +/* CVS Reference : /UDP_SAM7X.pl/1.1/Tue May 10 11:35:35 2005// */ +/* CVS Reference : /PWM_SAM7X.pl/1.1/Tue May 10 11:53:07 2005// */ +/* CVS Reference : /AIC_6075B.pl/1.3/Fri May 20 14:01:30 2005// */ +/* CVS Reference : /PIO_6057A.pl/1.2/Thu Feb 3 10:18:28 2005// */ +/* CVS Reference : /RTTC_6081A.pl/1.2/Tue Nov 9 14:43:58 2004// */ +/* CVS Reference : /PITC_6079A.pl/1.2/Tue Nov 9 14:43:56 2004// */ +/* CVS Reference : /WDTC_6080A.pl/1.3/Tue Nov 9 14:44:00 2004// */ +/* CVS Reference : /VREG_6085B.pl/1.1/Tue Feb 1 16:05:48 2005// */ +/* CVS Reference : /PDC_6074C.pl/1.2/Thu Feb 3 08:48:54 2005// */ +/* CVS Reference : /DBGU_6059D.pl/1.1/Mon Jan 31 13:15:32 2005// */ +/* CVS Reference : /SPI_6088D.pl/1.3/Fri May 20 14:08:59 2005// */ +/* CVS Reference : /US_6089C.pl/1.1/Mon Jul 12 18:23:26 2004// */ +/* CVS Reference : /SSC_6078A.pl/1.1/Tue Jul 13 07:45:40 2004// */ +/* CVS Reference : /TWI_6061A.pl/1.1/Tue Jul 13 07:38:06 2004// */ +/* CVS Reference : /TC_6082A.pl/1.7/Fri Mar 11 12:52:17 2005// */ +/* CVS Reference : /CAN_6019B.pl/1.1/Tue Mar 8 12:42:22 2005// */ +/* CVS Reference : /EMACB_6119A.pl/1.5/Thu Feb 3 15:52:04 2005// */ +/* CVS Reference : /ADC_6051C.pl/1.1/Fri Oct 17 09:12:38 2003// */ +/* CVS Reference : /AES_6149A.pl/1.10/Mon Feb 7 09:44:25 2005// */ +/* CVS Reference : /DES3_6150A.pl/1.1/Mon Jan 17 08:34:31 2005// */ +/* ---------------------------------------------------------------------------- */ #ifndef AT91SAM7X256_H #define AT91SAM7X256_H -typedef volatile unsigned int AT91_REG;// Hardware register definition - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR System Peripherals -// ***************************************************************************** -typedef struct _AT91S_SYS { - AT91_REG AIC_SMR[32]; // Source Mode Register - AT91_REG AIC_SVR[32]; // Source Vector Register - AT91_REG AIC_IVR; // IRQ Vector Register - AT91_REG AIC_FVR; // FIQ Vector Register - AT91_REG AIC_ISR; // Interrupt Status Register - AT91_REG AIC_IPR; // Interrupt Pending Register - AT91_REG AIC_IMR; // Interrupt Mask Register - AT91_REG AIC_CISR; // Core Interrupt Status Register - AT91_REG Reserved0[2]; // - AT91_REG AIC_IECR; // Interrupt Enable Command Register - AT91_REG AIC_IDCR; // Interrupt Disable Command Register - AT91_REG AIC_ICCR; // Interrupt Clear Command Register - AT91_REG AIC_ISCR; // Interrupt Set Command Register - AT91_REG AIC_EOICR; // End of Interrupt Command Register - AT91_REG AIC_SPU; // Spurious Vector Register - AT91_REG AIC_DCR; // Debug Control Register (Protect) - AT91_REG Reserved1[1]; // - AT91_REG AIC_FFER; // Fast Forcing Enable Register - AT91_REG AIC_FFDR; // Fast Forcing Disable Register - AT91_REG AIC_FFSR; // Fast Forcing Status Register - AT91_REG Reserved2[45]; // - AT91_REG DBGU_CR; // Control Register - AT91_REG DBGU_MR; // Mode Register - AT91_REG DBGU_IER; // Interrupt Enable Register - AT91_REG DBGU_IDR; // Interrupt Disable Register - AT91_REG DBGU_IMR; // Interrupt Mask Register - AT91_REG DBGU_CSR; // Channel Status Register - AT91_REG DBGU_RHR; // Receiver Holding Register - AT91_REG DBGU_THR; // Transmitter Holding Register - AT91_REG DBGU_BRGR; // Baud Rate Generator Register - AT91_REG Reserved3[7]; // - AT91_REG DBGU_CIDR; // Chip ID Register - AT91_REG DBGU_EXID; // Chip ID Extension Register - AT91_REG DBGU_FNTR; // Force NTRST Register - AT91_REG Reserved4[45]; // - AT91_REG DBGU_RPR; // Receive Pointer Register - AT91_REG DBGU_RCR; // Receive Counter Register - AT91_REG DBGU_TPR; // Transmit Pointer Register - AT91_REG DBGU_TCR; // Transmit Counter Register - AT91_REG DBGU_RNPR; // Receive Next Pointer Register - AT91_REG DBGU_RNCR; // Receive Next Counter Register - AT91_REG DBGU_TNPR; // Transmit Next Pointer Register - AT91_REG DBGU_TNCR; // Transmit Next Counter Register - AT91_REG DBGU_PTCR; // PDC Transfer Control Register - AT91_REG DBGU_PTSR; // PDC Transfer Status Register - AT91_REG Reserved5[54]; // - AT91_REG PIOA_PER; // PIO Enable Register - AT91_REG PIOA_PDR; // PIO Disable Register - AT91_REG PIOA_PSR; // PIO Status Register - AT91_REG Reserved6[1]; // - AT91_REG PIOA_OER; // Output Enable Register - AT91_REG PIOA_ODR; // Output Disable Registerr - AT91_REG PIOA_OSR; // Output Status Register - AT91_REG Reserved7[1]; // - AT91_REG PIOA_IFER; // Input Filter Enable Register - AT91_REG PIOA_IFDR; // Input Filter Disable Register - AT91_REG PIOA_IFSR; // Input Filter Status Register - AT91_REG Reserved8[1]; // - AT91_REG PIOA_SODR; // Set Output Data Register - AT91_REG PIOA_CODR; // Clear Output Data Register - AT91_REG PIOA_ODSR; // Output Data Status Register - AT91_REG PIOA_PDSR; // Pin Data Status Register - AT91_REG PIOA_IER; // Interrupt Enable Register - AT91_REG PIOA_IDR; // Interrupt Disable Register - AT91_REG PIOA_IMR; // Interrupt Mask Register - AT91_REG PIOA_ISR; // Interrupt Status Register - AT91_REG PIOA_MDER; // Multi-driver Enable Register - AT91_REG PIOA_MDDR; // Multi-driver Disable Register - AT91_REG PIOA_MDSR; // Multi-driver Status Register - AT91_REG Reserved9[1]; // - AT91_REG PIOA_PPUDR; // Pull-up Disable Register - AT91_REG PIOA_PPUER; // Pull-up Enable Register - AT91_REG PIOA_PPUSR; // Pull-up Status Register - AT91_REG Reserved10[1]; // - AT91_REG PIOA_ASR; // Select A Register - AT91_REG PIOA_BSR; // Select B Register - AT91_REG PIOA_ABSR; // AB Select Status Register - AT91_REG Reserved11[9]; // - AT91_REG PIOA_OWER; // Output Write Enable Register - AT91_REG PIOA_OWDR; // Output Write Disable Register - AT91_REG PIOA_OWSR; // Output Write Status Register - AT91_REG Reserved12[85]; // - AT91_REG PIOB_PER; // PIO Enable Register - AT91_REG PIOB_PDR; // PIO Disable Register - AT91_REG PIOB_PSR; // PIO Status Register - AT91_REG Reserved13[1]; // - AT91_REG PIOB_OER; // Output Enable Register - AT91_REG PIOB_ODR; // Output Disable Registerr - AT91_REG PIOB_OSR; // Output Status Register - AT91_REG Reserved14[1]; // - AT91_REG PIOB_IFER; // Input Filter Enable Register - AT91_REG PIOB_IFDR; // Input Filter Disable Register - AT91_REG PIOB_IFSR; // Input Filter Status Register - AT91_REG Reserved15[1]; // - AT91_REG PIOB_SODR; // Set Output Data Register - AT91_REG PIOB_CODR; // Clear Output Data Register - AT91_REG PIOB_ODSR; // Output Data Status Register - AT91_REG PIOB_PDSR; // Pin Data Status Register - AT91_REG PIOB_IER; // Interrupt Enable Register - AT91_REG PIOB_IDR; // Interrupt Disable Register - AT91_REG PIOB_IMR; // Interrupt Mask Register - AT91_REG PIOB_ISR; // Interrupt Status Register - AT91_REG PIOB_MDER; // Multi-driver Enable Register - AT91_REG PIOB_MDDR; // Multi-driver Disable Register - AT91_REG PIOB_MDSR; // Multi-driver Status Register - AT91_REG Reserved16[1]; // - AT91_REG PIOB_PPUDR; // Pull-up Disable Register - AT91_REG PIOB_PPUER; // Pull-up Enable Register - AT91_REG PIOB_PPUSR; // Pull-up Status Register - AT91_REG Reserved17[1]; // - AT91_REG PIOB_ASR; // Select A Register - AT91_REG PIOB_BSR; // Select B Register - AT91_REG PIOB_ABSR; // AB Select Status Register - AT91_REG Reserved18[9]; // - AT91_REG PIOB_OWER; // Output Write Enable Register - AT91_REG PIOB_OWDR; // Output Write Disable Register - AT91_REG PIOB_OWSR; // Output Write Status Register - AT91_REG Reserved19[341]; // - AT91_REG PMC_SCER; // System Clock Enable Register - AT91_REG PMC_SCDR; // System Clock Disable Register - AT91_REG PMC_SCSR; // System Clock Status Register - AT91_REG Reserved20[1]; // - AT91_REG PMC_PCER; // Peripheral Clock Enable Register - AT91_REG PMC_PCDR; // Peripheral Clock Disable Register - AT91_REG PMC_PCSR; // Peripheral Clock Status Register - AT91_REG Reserved21[1]; // - AT91_REG PMC_MOR; // Main Oscillator Register - AT91_REG PMC_MCFR; // Main Clock Frequency Register - AT91_REG Reserved22[1]; // - AT91_REG PMC_PLLR; // PLL Register - AT91_REG PMC_MCKR; // Master Clock Register - AT91_REG Reserved23[3]; // - AT91_REG PMC_PCKR[4]; // Programmable Clock Register - AT91_REG Reserved24[4]; // - AT91_REG PMC_IER; // Interrupt Enable Register - AT91_REG PMC_IDR; // Interrupt Disable Register - AT91_REG PMC_SR; // Status Register - AT91_REG PMC_IMR; // Interrupt Mask Register - AT91_REG Reserved25[36]; // - AT91_REG RSTC_RCR; // Reset Control Register - AT91_REG RSTC_RSR; // Reset Status Register - AT91_REG RSTC_RMR; // Reset Mode Register - AT91_REG Reserved26[5]; // - AT91_REG RTTC_RTMR; // Real-time Mode Register - AT91_REG RTTC_RTAR; // Real-time Alarm Register - AT91_REG RTTC_RTVR; // Real-time Value Register - AT91_REG RTTC_RTSR; // Real-time Status Register - AT91_REG PITC_PIMR; // Period Interval Mode Register - AT91_REG PITC_PISR; // Period Interval Status Register - AT91_REG PITC_PIVR; // Period Interval Value Register - AT91_REG PITC_PIIR; // Period Interval Image Register - AT91_REG WDTC_WDCR; // Watchdog Control Register - AT91_REG WDTC_WDMR; // Watchdog Mode Register - AT91_REG WDTC_WDSR; // Watchdog Status Register - AT91_REG Reserved27[5]; // - AT91_REG VREG_MR; // Voltage Regulator Mode Register -} AT91S_SYS, *AT91PS_SYS; - - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Advanced Interrupt Controller -// ***************************************************************************** -typedef struct _AT91S_AIC { - AT91_REG AIC_SMR[32]; // Source Mode Register - AT91_REG AIC_SVR[32]; // Source Vector Register - AT91_REG AIC_IVR; // IRQ Vector Register - AT91_REG AIC_FVR; // FIQ Vector Register - AT91_REG AIC_ISR; // Interrupt Status Register - AT91_REG AIC_IPR; // Interrupt Pending Register - AT91_REG AIC_IMR; // Interrupt Mask Register - AT91_REG AIC_CISR; // Core Interrupt Status Register - AT91_REG Reserved0[2]; // - AT91_REG AIC_IECR; // Interrupt Enable Command Register - AT91_REG AIC_IDCR; // Interrupt Disable Command Register - AT91_REG AIC_ICCR; // Interrupt Clear Command Register - AT91_REG AIC_ISCR; // Interrupt Set Command Register - AT91_REG AIC_EOICR; // End of Interrupt Command Register - AT91_REG AIC_SPU; // Spurious Vector Register - AT91_REG AIC_DCR; // Debug Control Register (Protect) - AT91_REG Reserved1[1]; // - AT91_REG AIC_FFER; // Fast Forcing Enable Register - AT91_REG AIC_FFDR; // Fast Forcing Disable Register - AT91_REG AIC_FFSR; // Fast Forcing Status Register -} AT91S_AIC, *AT91PS_AIC; - -// -------- AIC_SMR : (AIC Offset: 0x0) Control Register -------- -#define AT91C_AIC_PRIOR ((unsigned int) 0x7 << 0) // (AIC) Priority Level -#define AT91C_AIC_PRIOR_LOWEST ((unsigned int) 0x0) // (AIC) Lowest priority level -#define AT91C_AIC_PRIOR_HIGHEST ((unsigned int) 0x7) // (AIC) Highest priority level -#define AT91C_AIC_SRCTYPE ((unsigned int) 0x3 << 5) // (AIC) Interrupt Source Type -#define AT91C_AIC_SRCTYPE_INT_HIGH_LEVEL ((unsigned int) 0x0 << 5) // (AIC) Internal Sources Code Label High-level Sensitive -#define AT91C_AIC_SRCTYPE_EXT_LOW_LEVEL ((unsigned int) 0x0 << 5) // (AIC) External Sources Code Label Low-level Sensitive -#define AT91C_AIC_SRCTYPE_INT_POSITIVE_EDGE ((unsigned int) 0x1 << 5) // (AIC) Internal Sources Code Label Positive Edge triggered -#define AT91C_AIC_SRCTYPE_EXT_NEGATIVE_EDGE ((unsigned int) 0x1 << 5) // (AIC) External Sources Code Label Negative Edge triggered -#define AT91C_AIC_SRCTYPE_HIGH_LEVEL ((unsigned int) 0x2 << 5) // (AIC) Internal Or External Sources Code Label High-level Sensitive -#define AT91C_AIC_SRCTYPE_POSITIVE_EDGE ((unsigned int) 0x3 << 5) // (AIC) Internal Or External Sources Code Label Positive Edge triggered -// -------- AIC_CISR : (AIC Offset: 0x114) AIC Core Interrupt Status Register -------- -#define AT91C_AIC_NFIQ ((unsigned int) 0x1 << 0) // (AIC) NFIQ Status -#define AT91C_AIC_NIRQ ((unsigned int) 0x1 << 1) // (AIC) NIRQ Status -// -------- AIC_DCR : (AIC Offset: 0x138) AIC Debug Control Register (Protect) -------- -#define AT91C_AIC_DCR_PROT ((unsigned int) 0x1 << 0) // (AIC) Protection Mode -#define AT91C_AIC_DCR_GMSK ((unsigned int) 0x1 << 1) // (AIC) General Mask - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Peripheral DMA Controller -// ***************************************************************************** -typedef struct _AT91S_PDC { - AT91_REG PDC_RPR; // Receive Pointer Register - AT91_REG PDC_RCR; // Receive Counter Register - AT91_REG PDC_TPR; // Transmit Pointer Register - AT91_REG PDC_TCR; // Transmit Counter Register - AT91_REG PDC_RNPR; // Receive Next Pointer Register - AT91_REG PDC_RNCR; // Receive Next Counter Register - AT91_REG PDC_TNPR; // Transmit Next Pointer Register - AT91_REG PDC_TNCR; // Transmit Next Counter Register - AT91_REG PDC_PTCR; // PDC Transfer Control Register - AT91_REG PDC_PTSR; // PDC Transfer Status Register -} AT91S_PDC, *AT91PS_PDC; - -// -------- PDC_PTCR : (PDC Offset: 0x20) PDC Transfer Control Register -------- -#define AT91C_PDC_RXTEN ((unsigned int) 0x1 << 0) // (PDC) Receiver Transfer Enable -#define AT91C_PDC_RXTDIS ((unsigned int) 0x1 << 1) // (PDC) Receiver Transfer Disable -#define AT91C_PDC_TXTEN ((unsigned int) 0x1 << 8) // (PDC) Transmitter Transfer Enable -#define AT91C_PDC_TXTDIS ((unsigned int) 0x1 << 9) // (PDC) Transmitter Transfer Disable -// -------- PDC_PTSR : (PDC Offset: 0x24) PDC Transfer Status Register -------- - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Debug Unit -// ***************************************************************************** -typedef struct _AT91S_DBGU { - AT91_REG DBGU_CR; // Control Register - AT91_REG DBGU_MR; // Mode Register - AT91_REG DBGU_IER; // Interrupt Enable Register - AT91_REG DBGU_IDR; // Interrupt Disable Register - AT91_REG DBGU_IMR; // Interrupt Mask Register - AT91_REG DBGU_CSR; // Channel Status Register - AT91_REG DBGU_RHR; // Receiver Holding Register - AT91_REG DBGU_THR; // Transmitter Holding Register - AT91_REG DBGU_BRGR; // Baud Rate Generator Register - AT91_REG Reserved0[7]; // - AT91_REG DBGU_CIDR; // Chip ID Register - AT91_REG DBGU_EXID; // Chip ID Extension Register - AT91_REG DBGU_FNTR; // Force NTRST Register - AT91_REG Reserved1[45]; // - AT91_REG DBGU_RPR; // Receive Pointer Register - AT91_REG DBGU_RCR; // Receive Counter Register - AT91_REG DBGU_TPR; // Transmit Pointer Register - AT91_REG DBGU_TCR; // Transmit Counter Register - AT91_REG DBGU_RNPR; // Receive Next Pointer Register - AT91_REG DBGU_RNCR; // Receive Next Counter Register - AT91_REG DBGU_TNPR; // Transmit Next Pointer Register - AT91_REG DBGU_TNCR; // Transmit Next Counter Register - AT91_REG DBGU_PTCR; // PDC Transfer Control Register - AT91_REG DBGU_PTSR; // PDC Transfer Status Register -} AT91S_DBGU, *AT91PS_DBGU; - -// -------- DBGU_CR : (DBGU Offset: 0x0) Debug Unit Control Register -------- -#define AT91C_US_RSTRX ((unsigned int) 0x1 << 2) // (DBGU) Reset Receiver -#define AT91C_US_RSTTX ((unsigned int) 0x1 << 3) // (DBGU) Reset Transmitter -#define AT91C_US_RXEN ((unsigned int) 0x1 << 4) // (DBGU) Receiver Enable -#define AT91C_US_RXDIS ((unsigned int) 0x1 << 5) // (DBGU) Receiver Disable -#define AT91C_US_TXEN ((unsigned int) 0x1 << 6) // (DBGU) Transmitter Enable -#define AT91C_US_TXDIS ((unsigned int) 0x1 << 7) // (DBGU) Transmitter Disable -#define AT91C_US_RSTSTA ((unsigned int) 0x1 << 8) // (DBGU) Reset Status Bits -// -------- DBGU_MR : (DBGU Offset: 0x4) Debug Unit Mode Register -------- -#define AT91C_US_PAR ((unsigned int) 0x7 << 9) // (DBGU) Parity type -#define AT91C_US_PAR_EVEN ((unsigned int) 0x0 << 9) // (DBGU) Even Parity -#define AT91C_US_PAR_ODD ((unsigned int) 0x1 << 9) // (DBGU) Odd Parity -#define AT91C_US_PAR_SPACE ((unsigned int) 0x2 << 9) // (DBGU) Parity forced to 0 (Space) -#define AT91C_US_PAR_MARK ((unsigned int) 0x3 << 9) // (DBGU) Parity forced to 1 (Mark) -#define AT91C_US_PAR_NONE ((unsigned int) 0x4 << 9) // (DBGU) No Parity -#define AT91C_US_PAR_MULTI_DROP ((unsigned int) 0x6 << 9) // (DBGU) Multi-drop mode -#define AT91C_US_CHMODE ((unsigned int) 0x3 << 14) // (DBGU) Channel Mode -#define AT91C_US_CHMODE_NORMAL ((unsigned int) 0x0 << 14) // (DBGU) Normal Mode: The USART channel operates as an RX/TX USART. -#define AT91C_US_CHMODE_AUTO ((unsigned int) 0x1 << 14) // (DBGU) Automatic Echo: Receiver Data Input is connected to the TXD pin. -#define AT91C_US_CHMODE_LOCAL ((unsigned int) 0x2 << 14) // (DBGU) Local Loopback: Transmitter Output Signal is connected to Receiver Input Signal. -#define AT91C_US_CHMODE_REMOTE ((unsigned int) 0x3 << 14) // (DBGU) Remote Loopback: RXD pin is internally connected to TXD pin. -// -------- DBGU_IER : (DBGU Offset: 0x8) Debug Unit Interrupt Enable Register -------- -#define AT91C_US_RXRDY ((unsigned int) 0x1 << 0) // (DBGU) RXRDY Interrupt -#define AT91C_US_TXRDY ((unsigned int) 0x1 << 1) // (DBGU) TXRDY Interrupt -#define AT91C_US_ENDRX ((unsigned int) 0x1 << 3) // (DBGU) End of Receive Transfer Interrupt -#define AT91C_US_ENDTX ((unsigned int) 0x1 << 4) // (DBGU) End of Transmit Interrupt -#define AT91C_US_OVRE ((unsigned int) 0x1 << 5) // (DBGU) Overrun Interrupt -#define AT91C_US_FRAME ((unsigned int) 0x1 << 6) // (DBGU) Framing Error Interrupt -#define AT91C_US_PARE ((unsigned int) 0x1 << 7) // (DBGU) Parity Error Interrupt -#define AT91C_US_TXEMPTY ((unsigned int) 0x1 << 9) // (DBGU) TXEMPTY Interrupt -#define AT91C_US_TXBUFE ((unsigned int) 0x1 << 11) // (DBGU) TXBUFE Interrupt -#define AT91C_US_RXBUFF ((unsigned int) 0x1 << 12) // (DBGU) RXBUFF Interrupt -#define AT91C_US_COMM_TX ((unsigned int) 0x1 << 30) // (DBGU) COMM_TX Interrupt -#define AT91C_US_COMM_RX ((unsigned int) 0x1 << 31) // (DBGU) COMM_RX Interrupt -// -------- DBGU_IDR : (DBGU Offset: 0xc) Debug Unit Interrupt Disable Register -------- -// -------- DBGU_IMR : (DBGU Offset: 0x10) Debug Unit Interrupt Mask Register -------- -// -------- DBGU_CSR : (DBGU Offset: 0x14) Debug Unit Channel Status Register -------- -// -------- DBGU_FNTR : (DBGU Offset: 0x48) Debug Unit FORCE_NTRST Register -------- -#define AT91C_US_FORCE_NTRST ((unsigned int) 0x1 << 0) // (DBGU) Force NTRST in JTAG - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Parallel Input Output Controler -// ***************************************************************************** -typedef struct _AT91S_PIO { - AT91_REG PIO_PER; // PIO Enable Register - AT91_REG PIO_PDR; // PIO Disable Register - AT91_REG PIO_PSR; // PIO Status Register - AT91_REG Reserved0[1]; // - AT91_REG PIO_OER; // Output Enable Register - AT91_REG PIO_ODR; // Output Disable Registerr - AT91_REG PIO_OSR; // Output Status Register - AT91_REG Reserved1[1]; // - AT91_REG PIO_IFER; // Input Filter Enable Register - AT91_REG PIO_IFDR; // Input Filter Disable Register - AT91_REG PIO_IFSR; // Input Filter Status Register - AT91_REG Reserved2[1]; // - AT91_REG PIO_SODR; // Set Output Data Register - AT91_REG PIO_CODR; // Clear Output Data Register - AT91_REG PIO_ODSR; // Output Data Status Register - AT91_REG PIO_PDSR; // Pin Data Status Register - AT91_REG PIO_IER; // Interrupt Enable Register - AT91_REG PIO_IDR; // Interrupt Disable Register - AT91_REG PIO_IMR; // Interrupt Mask Register - AT91_REG PIO_ISR; // Interrupt Status Register - AT91_REG PIO_MDER; // Multi-driver Enable Register - AT91_REG PIO_MDDR; // Multi-driver Disable Register - AT91_REG PIO_MDSR; // Multi-driver Status Register - AT91_REG Reserved3[1]; // - AT91_REG PIO_PPUDR; // Pull-up Disable Register - AT91_REG PIO_PPUER; // Pull-up Enable Register - AT91_REG PIO_PPUSR; // Pull-up Status Register - AT91_REG Reserved4[1]; // - AT91_REG PIO_ASR; // Select A Register - AT91_REG PIO_BSR; // Select B Register - AT91_REG PIO_ABSR; // AB Select Status Register - AT91_REG Reserved5[9]; // - AT91_REG PIO_OWER; // Output Write Enable Register - AT91_REG PIO_OWDR; // Output Write Disable Register - AT91_REG PIO_OWSR; // Output Write Status Register -} AT91S_PIO, *AT91PS_PIO; - - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Clock Generator Controler -// ***************************************************************************** -typedef struct _AT91S_CKGR { - AT91_REG CKGR_MOR; // Main Oscillator Register - AT91_REG CKGR_MCFR; // Main Clock Frequency Register - AT91_REG Reserved0[1]; // - AT91_REG CKGR_PLLR; // PLL Register -} AT91S_CKGR, *AT91PS_CKGR; - -// -------- CKGR_MOR : (CKGR Offset: 0x0) Main Oscillator Register -------- -#define AT91C_CKGR_MOSCEN ((unsigned int) 0x1 << 0) // (CKGR) Main Oscillator Enable -#define AT91C_CKGR_OSCBYPASS ((unsigned int) 0x1 << 1) // (CKGR) Main Oscillator Bypass -#define AT91C_CKGR_OSCOUNT ((unsigned int) 0xFF << 8) // (CKGR) Main Oscillator Start-up Time -// -------- CKGR_MCFR : (CKGR Offset: 0x4) Main Clock Frequency Register -------- -#define AT91C_CKGR_MAINF ((unsigned int) 0xFFFF << 0) // (CKGR) Main Clock Frequency -#define AT91C_CKGR_MAINRDY ((unsigned int) 0x1 << 16) // (CKGR) Main Clock Ready -// -------- CKGR_PLLR : (CKGR Offset: 0xc) PLL B Register -------- -#define AT91C_CKGR_DIV ((unsigned int) 0xFF << 0) // (CKGR) Divider Selected -#define AT91C_CKGR_DIV_0 ((unsigned int) 0x0) // (CKGR) Divider output is 0 -#define AT91C_CKGR_DIV_BYPASS ((unsigned int) 0x1) // (CKGR) Divider is bypassed -#define AT91C_CKGR_PLLCOUNT ((unsigned int) 0x3F << 8) // (CKGR) PLL Counter -#define AT91C_CKGR_OUT ((unsigned int) 0x3 << 14) // (CKGR) PLL Output Frequency Range -#define AT91C_CKGR_OUT_0 ((unsigned int) 0x0 << 14) // (CKGR) Please refer to the PLL datasheet -#define AT91C_CKGR_OUT_1 ((unsigned int) 0x1 << 14) // (CKGR) Please refer to the PLL datasheet -#define AT91C_CKGR_OUT_2 ((unsigned int) 0x2 << 14) // (CKGR) Please refer to the PLL datasheet -#define AT91C_CKGR_OUT_3 ((unsigned int) 0x3 << 14) // (CKGR) Please refer to the PLL datasheet -#define AT91C_CKGR_MUL ((unsigned int) 0x7FF << 16) // (CKGR) PLL Multiplier -#define AT91C_CKGR_USBDIV ((unsigned int) 0x3 << 28) // (CKGR) Divider for USB Clocks -#define AT91C_CKGR_USBDIV_0 ((unsigned int) 0x0 << 28) // (CKGR) Divider output is PLL clock output -#define AT91C_CKGR_USBDIV_1 ((unsigned int) 0x1 << 28) // (CKGR) Divider output is PLL clock output divided by 2 -#define AT91C_CKGR_USBDIV_2 ((unsigned int) 0x2 << 28) // (CKGR) Divider output is PLL clock output divided by 4 - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Power Management Controler -// ***************************************************************************** -typedef struct _AT91S_PMC { - AT91_REG PMC_SCER; // System Clock Enable Register - AT91_REG PMC_SCDR; // System Clock Disable Register - AT91_REG PMC_SCSR; // System Clock Status Register - AT91_REG Reserved0[1]; // - AT91_REG PMC_PCER; // Peripheral Clock Enable Register - AT91_REG PMC_PCDR; // Peripheral Clock Disable Register - AT91_REG PMC_PCSR; // Peripheral Clock Status Register - AT91_REG Reserved1[1]; // - AT91_REG PMC_MOR; // Main Oscillator Register - AT91_REG PMC_MCFR; // Main Clock Frequency Register - AT91_REG Reserved2[1]; // - AT91_REG PMC_PLLR; // PLL Register - AT91_REG PMC_MCKR; // Master Clock Register - AT91_REG Reserved3[3]; // - AT91_REG PMC_PCKR[4]; // Programmable Clock Register - AT91_REG Reserved4[4]; // - AT91_REG PMC_IER; // Interrupt Enable Register - AT91_REG PMC_IDR; // Interrupt Disable Register - AT91_REG PMC_SR; // Status Register - AT91_REG PMC_IMR; // Interrupt Mask Register -} AT91S_PMC, *AT91PS_PMC; - -// -------- PMC_SCER : (PMC Offset: 0x0) System Clock Enable Register -------- -#define AT91C_PMC_PCK ((unsigned int) 0x1 << 0) // (PMC) Processor Clock -#define AT91C_PMC_UDP ((unsigned int) 0x1 << 7) // (PMC) USB Device Port Clock -#define AT91C_PMC_PCK0 ((unsigned int) 0x1 << 8) // (PMC) Programmable Clock Output -#define AT91C_PMC_PCK1 ((unsigned int) 0x1 << 9) // (PMC) Programmable Clock Output -#define AT91C_PMC_PCK2 ((unsigned int) 0x1 << 10) // (PMC) Programmable Clock Output -#define AT91C_PMC_PCK3 ((unsigned int) 0x1 << 11) // (PMC) Programmable Clock Output -// -------- PMC_SCDR : (PMC Offset: 0x4) System Clock Disable Register -------- -// -------- PMC_SCSR : (PMC Offset: 0x8) System Clock Status Register -------- -// -------- CKGR_MOR : (PMC Offset: 0x20) Main Oscillator Register -------- -// -------- CKGR_MCFR : (PMC Offset: 0x24) Main Clock Frequency Register -------- -// -------- CKGR_PLLR : (PMC Offset: 0x2c) PLL B Register -------- -// -------- PMC_MCKR : (PMC Offset: 0x30) Master Clock Register -------- -#define AT91C_PMC_CSS ((unsigned int) 0x3 << 0) // (PMC) Programmable Clock Selection -#define AT91C_PMC_CSS_SLOW_CLK ((unsigned int) 0x0) // (PMC) Slow Clock is selected -#define AT91C_PMC_CSS_MAIN_CLK ((unsigned int) 0x1) // (PMC) Main Clock is selected -#define AT91C_PMC_CSS_PLL_CLK ((unsigned int) 0x3) // (PMC) Clock from PLL is selected -#define AT91C_PMC_PRES ((unsigned int) 0x7 << 2) // (PMC) Programmable Clock Prescaler -#define AT91C_PMC_PRES_CLK ((unsigned int) 0x0 << 2) // (PMC) Selected clock -#define AT91C_PMC_PRES_CLK_2 ((unsigned int) 0x1 << 2) // (PMC) Selected clock divided by 2 -#define AT91C_PMC_PRES_CLK_4 ((unsigned int) 0x2 << 2) // (PMC) Selected clock divided by 4 -#define AT91C_PMC_PRES_CLK_8 ((unsigned int) 0x3 << 2) // (PMC) Selected clock divided by 8 -#define AT91C_PMC_PRES_CLK_16 ((unsigned int) 0x4 << 2) // (PMC) Selected clock divided by 16 -#define AT91C_PMC_PRES_CLK_32 ((unsigned int) 0x5 << 2) // (PMC) Selected clock divided by 32 -#define AT91C_PMC_PRES_CLK_64 ((unsigned int) 0x6 << 2) // (PMC) Selected clock divided by 64 -// -------- PMC_PCKR : (PMC Offset: 0x40) Programmable Clock Register -------- -// -------- PMC_IER : (PMC Offset: 0x60) PMC Interrupt Enable Register -------- -#define AT91C_PMC_MOSCS ((unsigned int) 0x1 << 0) // (PMC) MOSC Status/Enable/Disable/Mask -#define AT91C_PMC_LOCK ((unsigned int) 0x1 << 2) // (PMC) PLL Status/Enable/Disable/Mask -#define AT91C_PMC_MCKRDY ((unsigned int) 0x1 << 3) // (PMC) MCK_RDY Status/Enable/Disable/Mask -#define AT91C_PMC_PCK0RDY ((unsigned int) 0x1 << 8) // (PMC) PCK0_RDY Status/Enable/Disable/Mask -#define AT91C_PMC_PCK1RDY ((unsigned int) 0x1 << 9) // (PMC) PCK1_RDY Status/Enable/Disable/Mask -#define AT91C_PMC_PCK2RDY ((unsigned int) 0x1 << 10) // (PMC) PCK2_RDY Status/Enable/Disable/Mask -#define AT91C_PMC_PCK3RDY ((unsigned int) 0x1 << 11) // (PMC) PCK3_RDY Status/Enable/Disable/Mask -// -------- PMC_IDR : (PMC Offset: 0x64) PMC Interrupt Disable Register -------- -// -------- PMC_SR : (PMC Offset: 0x68) PMC Status Register -------- -// -------- PMC_IMR : (PMC Offset: 0x6c) PMC Interrupt Mask Register -------- - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Reset Controller Interface -// ***************************************************************************** -typedef struct _AT91S_RSTC { - AT91_REG RSTC_RCR; // Reset Control Register - AT91_REG RSTC_RSR; // Reset Status Register - AT91_REG RSTC_RMR; // Reset Mode Register -} AT91S_RSTC, *AT91PS_RSTC; - -// -------- RSTC_RCR : (RSTC Offset: 0x0) Reset Control Register -------- -#define AT91C_RSTC_PROCRST ((unsigned int) 0x1 << 0) // (RSTC) Processor Reset -#define AT91C_RSTC_PERRST ((unsigned int) 0x1 << 2) // (RSTC) Peripheral Reset -#define AT91C_RSTC_EXTRST ((unsigned int) 0x1 << 3) // (RSTC) External Reset -#define AT91C_RSTC_KEY ((unsigned int) 0xFF << 24) // (RSTC) Password -// -------- RSTC_RSR : (RSTC Offset: 0x4) Reset Status Register -------- -#define AT91C_RSTC_URSTS ((unsigned int) 0x1 << 0) // (RSTC) User Reset Status -#define AT91C_RSTC_BODSTS ((unsigned int) 0x1 << 1) // (RSTC) Brownout Detection Status -#define AT91C_RSTC_RSTTYP ((unsigned int) 0x7 << 8) // (RSTC) Reset Type -#define AT91C_RSTC_RSTTYP_POWERUP ((unsigned int) 0x0 << 8) // (RSTC) Power-up Reset. VDDCORE rising. -#define AT91C_RSTC_RSTTYP_WAKEUP ((unsigned int) 0x1 << 8) // (RSTC) WakeUp Reset. VDDCORE rising. -#define AT91C_RSTC_RSTTYP_WATCHDOG ((unsigned int) 0x2 << 8) // (RSTC) Watchdog Reset. Watchdog overflow occured. -#define AT91C_RSTC_RSTTYP_SOFTWARE ((unsigned int) 0x3 << 8) // (RSTC) Software Reset. Processor reset required by the software. -#define AT91C_RSTC_RSTTYP_USER ((unsigned int) 0x4 << 8) // (RSTC) User Reset. NRST pin detected low. -#define AT91C_RSTC_RSTTYP_BROWNOUT ((unsigned int) 0x5 << 8) // (RSTC) Brownout Reset occured. -#define AT91C_RSTC_NRSTL ((unsigned int) 0x1 << 16) // (RSTC) NRST pin level -#define AT91C_RSTC_SRCMP ((unsigned int) 0x1 << 17) // (RSTC) Software Reset Command in Progress. -// -------- RSTC_RMR : (RSTC Offset: 0x8) Reset Mode Register -------- -#define AT91C_RSTC_URSTEN ((unsigned int) 0x1 << 0) // (RSTC) User Reset Enable -#define AT91C_RSTC_URSTIEN ((unsigned int) 0x1 << 4) // (RSTC) User Reset Interrupt Enable -#define AT91C_RSTC_ERSTL ((unsigned int) 0xF << 8) // (RSTC) User Reset Enable -#define AT91C_RSTC_BODIEN ((unsigned int) 0x1 << 16) // (RSTC) Brownout Detection Interrupt Enable - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Real Time Timer Controller Interface -// ***************************************************************************** -typedef struct _AT91S_RTTC { - AT91_REG RTTC_RTMR; // Real-time Mode Register - AT91_REG RTTC_RTAR; // Real-time Alarm Register - AT91_REG RTTC_RTVR; // Real-time Value Register - AT91_REG RTTC_RTSR; // Real-time Status Register -} AT91S_RTTC, *AT91PS_RTTC; - -// -------- RTTC_RTMR : (RTTC Offset: 0x0) Real-time Mode Register -------- -#define AT91C_RTTC_RTPRES ((unsigned int) 0xFFFF << 0) // (RTTC) Real-time Timer Prescaler Value -#define AT91C_RTTC_ALMIEN ((unsigned int) 0x1 << 16) // (RTTC) Alarm Interrupt Enable -#define AT91C_RTTC_RTTINCIEN ((unsigned int) 0x1 << 17) // (RTTC) Real Time Timer Increment Interrupt Enable -#define AT91C_RTTC_RTTRST ((unsigned int) 0x1 << 18) // (RTTC) Real Time Timer Restart -// -------- RTTC_RTAR : (RTTC Offset: 0x4) Real-time Alarm Register -------- -#define AT91C_RTTC_ALMV ((unsigned int) 0x0 << 0) // (RTTC) Alarm Value -// -------- RTTC_RTVR : (RTTC Offset: 0x8) Current Real-time Value Register -------- -#define AT91C_RTTC_CRTV ((unsigned int) 0x0 << 0) // (RTTC) Current Real-time Value -// -------- RTTC_RTSR : (RTTC Offset: 0xc) Real-time Status Register -------- -#define AT91C_RTTC_ALMS ((unsigned int) 0x1 << 0) // (RTTC) Real-time Alarm Status -#define AT91C_RTTC_RTTINC ((unsigned int) 0x1 << 1) // (RTTC) Real-time Timer Increment - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Periodic Interval Timer Controller Interface -// ***************************************************************************** -typedef struct _AT91S_PITC { - AT91_REG PITC_PIMR; // Period Interval Mode Register - AT91_REG PITC_PISR; // Period Interval Status Register - AT91_REG PITC_PIVR; // Period Interval Value Register - AT91_REG PITC_PIIR; // Period Interval Image Register -} AT91S_PITC, *AT91PS_PITC; - -// -------- PITC_PIMR : (PITC Offset: 0x0) Periodic Interval Mode Register -------- -#define AT91C_PITC_PIV ((unsigned int) 0xFFFFF << 0) // (PITC) Periodic Interval Value -#define AT91C_PITC_PITEN ((unsigned int) 0x1 << 24) // (PITC) Periodic Interval Timer Enabled -#define AT91C_PITC_PITIEN ((unsigned int) 0x1 << 25) // (PITC) Periodic Interval Timer Interrupt Enable -// -------- PITC_PISR : (PITC Offset: 0x4) Periodic Interval Status Register -------- -#define AT91C_PITC_PITS ((unsigned int) 0x1 << 0) // (PITC) Periodic Interval Timer Status -// -------- PITC_PIVR : (PITC Offset: 0x8) Periodic Interval Value Register -------- -#define AT91C_PITC_CPIV ((unsigned int) 0xFFFFF << 0) // (PITC) Current Periodic Interval Value -#define AT91C_PITC_PICNT ((unsigned int) 0xFFF << 20) // (PITC) Periodic Interval Counter -// -------- PITC_PIIR : (PITC Offset: 0xc) Periodic Interval Image Register -------- - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Watchdog Timer Controller Interface -// ***************************************************************************** -typedef struct _AT91S_WDTC { - AT91_REG WDTC_WDCR; // Watchdog Control Register - AT91_REG WDTC_WDMR; // Watchdog Mode Register - AT91_REG WDTC_WDSR; // Watchdog Status Register -} AT91S_WDTC, *AT91PS_WDTC; - -// -------- WDTC_WDCR : (WDTC Offset: 0x0) Periodic Interval Image Register -------- -#define AT91C_WDTC_WDRSTT ((unsigned int) 0x1 << 0) // (WDTC) Watchdog Restart -#define AT91C_WDTC_KEY ((unsigned int) 0xFF << 24) // (WDTC) Watchdog KEY Password -// -------- WDTC_WDMR : (WDTC Offset: 0x4) Watchdog Mode Register -------- -#define AT91C_WDTC_WDV ((unsigned int) 0xFFF << 0) // (WDTC) Watchdog Timer Restart -#define AT91C_WDTC_WDFIEN ((unsigned int) 0x1 << 12) // (WDTC) Watchdog Fault Interrupt Enable -#define AT91C_WDTC_WDRSTEN ((unsigned int) 0x1 << 13) // (WDTC) Watchdog Reset Enable -#define AT91C_WDTC_WDRPROC ((unsigned int) 0x1 << 14) // (WDTC) Watchdog Timer Restart -#define AT91C_WDTC_WDDIS ((unsigned int) 0x1 << 15) // (WDTC) Watchdog Disable -#define AT91C_WDTC_WDD ((unsigned int) 0xFFF << 16) // (WDTC) Watchdog Delta Value -#define AT91C_WDTC_WDDBGHLT ((unsigned int) 0x1 << 28) // (WDTC) Watchdog Debug Halt -#define AT91C_WDTC_WDIDLEHLT ((unsigned int) 0x1 << 29) // (WDTC) Watchdog Idle Halt -// -------- WDTC_WDSR : (WDTC Offset: 0x8) Watchdog Status Register -------- -#define AT91C_WDTC_WDUNF ((unsigned int) 0x1 << 0) // (WDTC) Watchdog Underflow -#define AT91C_WDTC_WDERR ((unsigned int) 0x1 << 1) // (WDTC) Watchdog Error - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Voltage Regulator Mode Controller Interface -// ***************************************************************************** -typedef struct _AT91S_VREG { - AT91_REG VREG_MR; // Voltage Regulator Mode Register -} AT91S_VREG, *AT91PS_VREG; - -// -------- VREG_MR : (VREG Offset: 0x0) Voltage Regulator Mode Register -------- -#define AT91C_VREG_PSTDBY ((unsigned int) 0x1 << 0) // (VREG) Voltage Regulator Power Standby Mode - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Memory Controller Interface -// ***************************************************************************** -typedef struct _AT91S_MC { - AT91_REG MC_RCR; // MC Remap Control Register - AT91_REG MC_ASR; // MC Abort Status Register - AT91_REG MC_AASR; // MC Abort Address Status Register - AT91_REG Reserved0[21]; // - AT91_REG MC_FMR; // MC Flash Mode Register - AT91_REG MC_FCR; // MC Flash Command Register - AT91_REG MC_FSR; // MC Flash Status Register -} AT91S_MC, *AT91PS_MC; - -// -------- MC_RCR : (MC Offset: 0x0) MC Remap Control Register -------- -#define AT91C_MC_RCB ((unsigned int) 0x1 << 0) // (MC) Remap Command Bit -// -------- MC_ASR : (MC Offset: 0x4) MC Abort Status Register -------- -#define AT91C_MC_UNDADD ((unsigned int) 0x1 << 0) // (MC) Undefined Addess Abort Status -#define AT91C_MC_MISADD ((unsigned int) 0x1 << 1) // (MC) Misaligned Addess Abort Status -#define AT91C_MC_ABTSZ ((unsigned int) 0x3 << 8) // (MC) Abort Size Status -#define AT91C_MC_ABTSZ_BYTE ((unsigned int) 0x0 << 8) // (MC) Byte -#define AT91C_MC_ABTSZ_HWORD ((unsigned int) 0x1 << 8) // (MC) Half-word -#define AT91C_MC_ABTSZ_WORD ((unsigned int) 0x2 << 8) // (MC) Word -#define AT91C_MC_ABTTYP ((unsigned int) 0x3 << 10) // (MC) Abort Type Status -#define AT91C_MC_ABTTYP_DATAR ((unsigned int) 0x0 << 10) // (MC) Data Read -#define AT91C_MC_ABTTYP_DATAW ((unsigned int) 0x1 << 10) // (MC) Data Write -#define AT91C_MC_ABTTYP_FETCH ((unsigned int) 0x2 << 10) // (MC) Code Fetch -#define AT91C_MC_MST0 ((unsigned int) 0x1 << 16) // (MC) Master 0 Abort Source -#define AT91C_MC_MST1 ((unsigned int) 0x1 << 17) // (MC) Master 1 Abort Source -#define AT91C_MC_SVMST0 ((unsigned int) 0x1 << 24) // (MC) Saved Master 0 Abort Source -#define AT91C_MC_SVMST1 ((unsigned int) 0x1 << 25) // (MC) Saved Master 1 Abort Source -// -------- MC_FMR : (MC Offset: 0x60) MC Flash Mode Register -------- -#define AT91C_MC_FRDY ((unsigned int) 0x1 << 0) // (MC) Flash Ready -#define AT91C_MC_LOCKE ((unsigned int) 0x1 << 2) // (MC) Lock Error -#define AT91C_MC_PROGE ((unsigned int) 0x1 << 3) // (MC) Programming Error -#define AT91C_MC_NEBP ((unsigned int) 0x1 << 7) // (MC) No Erase Before Programming -#define AT91C_MC_FWS ((unsigned int) 0x3 << 8) // (MC) Flash Wait State -#define AT91C_MC_FWS_0FWS ((unsigned int) 0x0 << 8) // (MC) 1 cycle for Read, 2 for Write operations -#define AT91C_MC_FWS_1FWS ((unsigned int) 0x1 << 8) // (MC) 2 cycles for Read, 3 for Write operations -#define AT91C_MC_FWS_2FWS ((unsigned int) 0x2 << 8) // (MC) 3 cycles for Read, 4 for Write operations -#define AT91C_MC_FWS_3FWS ((unsigned int) 0x3 << 8) // (MC) 4 cycles for Read, 4 for Write operations -#define AT91C_MC_FMCN ((unsigned int) 0xFF << 16) // (MC) Flash Microsecond Cycle Number -// -------- MC_FCR : (MC Offset: 0x64) MC Flash Command Register -------- -#define AT91C_MC_FCMD ((unsigned int) 0xF << 0) // (MC) Flash Command -#define AT91C_MC_FCMD_START_PROG ((unsigned int) 0x1) // (MC) Starts the programming of th epage specified by PAGEN. -#define AT91C_MC_FCMD_LOCK ((unsigned int) 0x2) // (MC) Starts a lock sequence of the sector defined by the bits 4 to 7 of the field PAGEN. -#define AT91C_MC_FCMD_PROG_AND_LOCK ((unsigned int) 0x3) // (MC) The lock sequence automatically happens after the programming sequence is completed. -#define AT91C_MC_FCMD_UNLOCK ((unsigned int) 0x4) // (MC) Starts an unlock sequence of the sector defined by the bits 4 to 7 of the field PAGEN. -#define AT91C_MC_FCMD_ERASE_ALL ((unsigned int) 0x8) // (MC) Starts the erase of the entire flash.If at least a page is locked, the command is cancelled. -#define AT91C_MC_FCMD_SET_GP_NVM ((unsigned int) 0xB) // (MC) Set General Purpose NVM bits. -#define AT91C_MC_FCMD_CLR_GP_NVM ((unsigned int) 0xD) // (MC) Clear General Purpose NVM bits. -#define AT91C_MC_FCMD_SET_SECURITY ((unsigned int) 0xF) // (MC) Set Security Bit. -#define AT91C_MC_PAGEN ((unsigned int) 0x3FF << 8) // (MC) Page Number -#define AT91C_MC_KEY ((unsigned int) 0xFF << 24) // (MC) Writing Protect Key -// -------- MC_FSR : (MC Offset: 0x68) MC Flash Command Register -------- -#define AT91C_MC_SECURITY ((unsigned int) 0x1 << 4) // (MC) Security Bit Status -#define AT91C_MC_GPNVM0 ((unsigned int) 0x1 << 8) // (MC) Sector 0 Lock Status -#define AT91C_MC_GPNVM1 ((unsigned int) 0x1 << 9) // (MC) Sector 1 Lock Status -#define AT91C_MC_GPNVM2 ((unsigned int) 0x1 << 10) // (MC) Sector 2 Lock Status -#define AT91C_MC_GPNVM3 ((unsigned int) 0x1 << 11) // (MC) Sector 3 Lock Status -#define AT91C_MC_GPNVM4 ((unsigned int) 0x1 << 12) // (MC) Sector 4 Lock Status -#define AT91C_MC_GPNVM5 ((unsigned int) 0x1 << 13) // (MC) Sector 5 Lock Status -#define AT91C_MC_GPNVM6 ((unsigned int) 0x1 << 14) // (MC) Sector 6 Lock Status -#define AT91C_MC_GPNVM7 ((unsigned int) 0x1 << 15) // (MC) Sector 7 Lock Status -#define AT91C_MC_LOCKS0 ((unsigned int) 0x1 << 16) // (MC) Sector 0 Lock Status -#define AT91C_MC_LOCKS1 ((unsigned int) 0x1 << 17) // (MC) Sector 1 Lock Status -#define AT91C_MC_LOCKS2 ((unsigned int) 0x1 << 18) // (MC) Sector 2 Lock Status -#define AT91C_MC_LOCKS3 ((unsigned int) 0x1 << 19) // (MC) Sector 3 Lock Status -#define AT91C_MC_LOCKS4 ((unsigned int) 0x1 << 20) // (MC) Sector 4 Lock Status -#define AT91C_MC_LOCKS5 ((unsigned int) 0x1 << 21) // (MC) Sector 5 Lock Status -#define AT91C_MC_LOCKS6 ((unsigned int) 0x1 << 22) // (MC) Sector 6 Lock Status -#define AT91C_MC_LOCKS7 ((unsigned int) 0x1 << 23) // (MC) Sector 7 Lock Status -#define AT91C_MC_LOCKS8 ((unsigned int) 0x1 << 24) // (MC) Sector 8 Lock Status -#define AT91C_MC_LOCKS9 ((unsigned int) 0x1 << 25) // (MC) Sector 9 Lock Status -#define AT91C_MC_LOCKS10 ((unsigned int) 0x1 << 26) // (MC) Sector 10 Lock Status -#define AT91C_MC_LOCKS11 ((unsigned int) 0x1 << 27) // (MC) Sector 11 Lock Status -#define AT91C_MC_LOCKS12 ((unsigned int) 0x1 << 28) // (MC) Sector 12 Lock Status -#define AT91C_MC_LOCKS13 ((unsigned int) 0x1 << 29) // (MC) Sector 13 Lock Status -#define AT91C_MC_LOCKS14 ((unsigned int) 0x1 << 30) // (MC) Sector 14 Lock Status -#define AT91C_MC_LOCKS15 ((unsigned int) 0x1 << 31) // (MC) Sector 15 Lock Status - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Serial Parallel Interface -// ***************************************************************************** -typedef struct _AT91S_SPI { - AT91_REG SPI_CR; // Control Register - AT91_REG SPI_MR; // Mode Register - AT91_REG SPI_RDR; // Receive Data Register - AT91_REG SPI_TDR; // Transmit Data Register - AT91_REG SPI_SR; // Status Register - AT91_REG SPI_IER; // Interrupt Enable Register - AT91_REG SPI_IDR; // Interrupt Disable Register - AT91_REG SPI_IMR; // Interrupt Mask Register - AT91_REG Reserved0[4]; // - AT91_REG SPI_CSR[4]; // Chip Select Register - AT91_REG Reserved1[48]; // - AT91_REG SPI_RPR; // Receive Pointer Register - AT91_REG SPI_RCR; // Receive Counter Register - AT91_REG SPI_TPR; // Transmit Pointer Register - AT91_REG SPI_TCR; // Transmit Counter Register - AT91_REG SPI_RNPR; // Receive Next Pointer Register - AT91_REG SPI_RNCR; // Receive Next Counter Register - AT91_REG SPI_TNPR; // Transmit Next Pointer Register - AT91_REG SPI_TNCR; // Transmit Next Counter Register - AT91_REG SPI_PTCR; // PDC Transfer Control Register - AT91_REG SPI_PTSR; // PDC Transfer Status Register -} AT91S_SPI, *AT91PS_SPI; - -// -------- SPI_CR : (SPI Offset: 0x0) SPI Control Register -------- -#define AT91C_SPI_SPIEN ((unsigned int) 0x1 << 0) // (SPI) SPI Enable -#define AT91C_SPI_SPIDIS ((unsigned int) 0x1 << 1) // (SPI) SPI Disable -#define AT91C_SPI_SWRST ((unsigned int) 0x1 << 7) // (SPI) SPI Software reset -#define AT91C_SPI_LASTXFER ((unsigned int) 0x1 << 24) // (SPI) SPI Last Transfer -// -------- SPI_MR : (SPI Offset: 0x4) SPI Mode Register -------- -#define AT91C_SPI_MSTR ((unsigned int) 0x1 << 0) // (SPI) Master/Slave Mode -#define AT91C_SPI_PS ((unsigned int) 0x1 << 1) // (SPI) Peripheral Select -#define AT91C_SPI_PS_FIXED ((unsigned int) 0x0 << 1) // (SPI) Fixed Peripheral Select -#define AT91C_SPI_PS_VARIABLE ((unsigned int) 0x1 << 1) // (SPI) Variable Peripheral Select -#define AT91C_SPI_PCSDEC ((unsigned int) 0x1 << 2) // (SPI) Chip Select Decode -#define AT91C_SPI_FDIV ((unsigned int) 0x1 << 3) // (SPI) Clock Selection -#define AT91C_SPI_MODFDIS ((unsigned int) 0x1 << 4) // (SPI) Mode Fault Detection -#define AT91C_SPI_LLB ((unsigned int) 0x1 << 7) // (SPI) Clock Selection -#define AT91C_SPI_PCS ((unsigned int) 0xF << 16) // (SPI) Peripheral Chip Select -#define AT91C_SPI_DLYBCS ((unsigned int) 0xFF << 24) // (SPI) Delay Between Chip Selects -// -------- SPI_RDR : (SPI Offset: 0x8) Receive Data Register -------- -#define AT91C_SPI_RD ((unsigned int) 0xFFFF << 0) // (SPI) Receive Data -#define AT91C_SPI_RPCS ((unsigned int) 0xF << 16) // (SPI) Peripheral Chip Select Status -// -------- SPI_TDR : (SPI Offset: 0xc) Transmit Data Register -------- -#define AT91C_SPI_TD ((unsigned int) 0xFFFF << 0) // (SPI) Transmit Data -#define AT91C_SPI_TPCS ((unsigned int) 0xF << 16) // (SPI) Peripheral Chip Select Status -// -------- SPI_SR : (SPI Offset: 0x10) Status Register -------- -#define AT91C_SPI_RDRF ((unsigned int) 0x1 << 0) // (SPI) Receive Data Register Full -#define AT91C_SPI_TDRE ((unsigned int) 0x1 << 1) // (SPI) Transmit Data Register Empty -#define AT91C_SPI_MODF ((unsigned int) 0x1 << 2) // (SPI) Mode Fault Error -#define AT91C_SPI_OVRES ((unsigned int) 0x1 << 3) // (SPI) Overrun Error Status -#define AT91C_SPI_ENDRX ((unsigned int) 0x1 << 4) // (SPI) End of Receiver Transfer -#define AT91C_SPI_ENDTX ((unsigned int) 0x1 << 5) // (SPI) End of Receiver Transfer -#define AT91C_SPI_RXBUFF ((unsigned int) 0x1 << 6) // (SPI) RXBUFF Interrupt -#define AT91C_SPI_TXBUFE ((unsigned int) 0x1 << 7) // (SPI) TXBUFE Interrupt -#define AT91C_SPI_NSSR ((unsigned int) 0x1 << 8) // (SPI) NSSR Interrupt -#define AT91C_SPI_TXEMPTY ((unsigned int) 0x1 << 9) // (SPI) TXEMPTY Interrupt -#define AT91C_SPI_SPIENS ((unsigned int) 0x1 << 16) // (SPI) Enable Status -// -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register -------- -// -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register -------- -// -------- SPI_IMR : (SPI Offset: 0x1c) Interrupt Mask Register -------- -// -------- SPI_CSR : (SPI Offset: 0x30) Chip Select Register -------- -#define AT91C_SPI_CPOL ((unsigned int) 0x1 << 0) // (SPI) Clock Polarity -#define AT91C_SPI_NCPHA ((unsigned int) 0x1 << 1) // (SPI) Clock Phase -#define AT91C_SPI_CSAAT ((unsigned int) 0x1 << 3) // (SPI) Chip Select Active After Transfer -#define AT91C_SPI_BITS ((unsigned int) 0xF << 4) // (SPI) Bits Per Transfer -#define AT91C_SPI_BITS_8 ((unsigned int) 0x0 << 4) // (SPI) 8 Bits Per transfer -#define AT91C_SPI_BITS_9 ((unsigned int) 0x1 << 4) // (SPI) 9 Bits Per transfer -#define AT91C_SPI_BITS_10 ((unsigned int) 0x2 << 4) // (SPI) 10 Bits Per transfer -#define AT91C_SPI_BITS_11 ((unsigned int) 0x3 << 4) // (SPI) 11 Bits Per transfer -#define AT91C_SPI_BITS_12 ((unsigned int) 0x4 << 4) // (SPI) 12 Bits Per transfer -#define AT91C_SPI_BITS_13 ((unsigned int) 0x5 << 4) // (SPI) 13 Bits Per transfer -#define AT91C_SPI_BITS_14 ((unsigned int) 0x6 << 4) // (SPI) 14 Bits Per transfer -#define AT91C_SPI_BITS_15 ((unsigned int) 0x7 << 4) // (SPI) 15 Bits Per transfer -#define AT91C_SPI_BITS_16 ((unsigned int) 0x8 << 4) // (SPI) 16 Bits Per transfer -#define AT91C_SPI_SCBR ((unsigned int) 0xFF << 8) // (SPI) Serial Clock Baud Rate -#define AT91C_SPI_DLYBS ((unsigned int) 0xFF << 16) // (SPI) Delay Before SPCK -#define AT91C_SPI_DLYBCT ((unsigned int) 0xFF << 24) // (SPI) Delay Between Consecutive Transfers - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Usart -// ***************************************************************************** -typedef struct _AT91S_USART { - AT91_REG US_CR; // Control Register - AT91_REG US_MR; // Mode Register - AT91_REG US_IER; // Interrupt Enable Register - AT91_REG US_IDR; // Interrupt Disable Register - AT91_REG US_IMR; // Interrupt Mask Register - AT91_REG US_CSR; // Channel Status Register - AT91_REG US_RHR; // Receiver Holding Register - AT91_REG US_THR; // Transmitter Holding Register - AT91_REG US_BRGR; // Baud Rate Generator Register - AT91_REG US_RTOR; // Receiver Time-out Register - AT91_REG US_TTGR; // Transmitter Time-guard Register - AT91_REG Reserved0[5]; // - AT91_REG US_FIDI; // FI_DI_Ratio Register - AT91_REG US_NER; // Nb Errors Register - AT91_REG Reserved1[1]; // - AT91_REG US_IF; // IRDA_FILTER Register - AT91_REG Reserved2[44]; // - AT91_REG US_RPR; // Receive Pointer Register - AT91_REG US_RCR; // Receive Counter Register - AT91_REG US_TPR; // Transmit Pointer Register - AT91_REG US_TCR; // Transmit Counter Register - AT91_REG US_RNPR; // Receive Next Pointer Register - AT91_REG US_RNCR; // Receive Next Counter Register - AT91_REG US_TNPR; // Transmit Next Pointer Register - AT91_REG US_TNCR; // Transmit Next Counter Register - AT91_REG US_PTCR; // PDC Transfer Control Register - AT91_REG US_PTSR; // PDC Transfer Status Register -} AT91S_USART, *AT91PS_USART; - -// -------- US_CR : (USART Offset: 0x0) Debug Unit Control Register -------- -#define AT91C_US_STTBRK ((unsigned int) 0x1 << 9) // (USART) Start Break -#define AT91C_US_STPBRK ((unsigned int) 0x1 << 10) // (USART) Stop Break -#define AT91C_US_STTTO ((unsigned int) 0x1 << 11) // (USART) Start Time-out -#define AT91C_US_SENDA ((unsigned int) 0x1 << 12) // (USART) Send Address -#define AT91C_US_RSTIT ((unsigned int) 0x1 << 13) // (USART) Reset Iterations -#define AT91C_US_RSTNACK ((unsigned int) 0x1 << 14) // (USART) Reset Non Acknowledge -#define AT91C_US_RETTO ((unsigned int) 0x1 << 15) // (USART) Rearm Time-out -#define AT91C_US_DTREN ((unsigned int) 0x1 << 16) // (USART) Data Terminal ready Enable -#define AT91C_US_DTRDIS ((unsigned int) 0x1 << 17) // (USART) Data Terminal ready Disable -#define AT91C_US_RTSEN ((unsigned int) 0x1 << 18) // (USART) Request to Send enable -#define AT91C_US_RTSDIS ((unsigned int) 0x1 << 19) // (USART) Request to Send Disable -// -------- US_MR : (USART Offset: 0x4) Debug Unit Mode Register -------- -#define AT91C_US_USMODE ((unsigned int) 0xF << 0) // (USART) Usart mode -#define AT91C_US_USMODE_NORMAL ((unsigned int) 0x0) // (USART) Normal -#define AT91C_US_USMODE_RS485 ((unsigned int) 0x1) // (USART) RS485 -#define AT91C_US_USMODE_HWHSH ((unsigned int) 0x2) // (USART) Hardware Handshaking -#define AT91C_US_USMODE_MODEM ((unsigned int) 0x3) // (USART) Modem -#define AT91C_US_USMODE_ISO7816_0 ((unsigned int) 0x4) // (USART) ISO7816 protocol: T = 0 -#define AT91C_US_USMODE_ISO7816_1 ((unsigned int) 0x6) // (USART) ISO7816 protocol: T = 1 -#define AT91C_US_USMODE_IRDA ((unsigned int) 0x8) // (USART) IrDA -#define AT91C_US_USMODE_SWHSH ((unsigned int) 0xC) // (USART) Software Handshaking -#define AT91C_US_CLKS ((unsigned int) 0x3 << 4) // (USART) Clock Selection (Baud Rate generator Input Clock -#define AT91C_US_CLKS_CLOCK ((unsigned int) 0x0 << 4) // (USART) Clock -#define AT91C_US_CLKS_FDIV1 ((unsigned int) 0x1 << 4) // (USART) fdiv1 -#define AT91C_US_CLKS_SLOW ((unsigned int) 0x2 << 4) // (USART) slow_clock (ARM) -#define AT91C_US_CLKS_EXT ((unsigned int) 0x3 << 4) // (USART) External (SCK) -#define AT91C_US_CHRL ((unsigned int) 0x3 << 6) // (USART) Clock Selection (Baud Rate generator Input Clock -#define AT91C_US_CHRL_5_BITS ((unsigned int) 0x0 << 6) // (USART) Character Length: 5 bits -#define AT91C_US_CHRL_6_BITS ((unsigned int) 0x1 << 6) // (USART) Character Length: 6 bits -#define AT91C_US_CHRL_7_BITS ((unsigned int) 0x2 << 6) // (USART) Character Length: 7 bits -#define AT91C_US_CHRL_8_BITS ((unsigned int) 0x3 << 6) // (USART) Character Length: 8 bits -#define AT91C_US_SYNC ((unsigned int) 0x1 << 8) // (USART) Synchronous Mode Select -#define AT91C_US_NBSTOP ((unsigned int) 0x3 << 12) // (USART) Number of Stop bits -#define AT91C_US_NBSTOP_1_BIT ((unsigned int) 0x0 << 12) // (USART) 1 stop bit -#define AT91C_US_NBSTOP_15_BIT ((unsigned int) 0x1 << 12) // (USART) Asynchronous (SYNC=0) 2 stop bits Synchronous (SYNC=1) 2 stop bits -#define AT91C_US_NBSTOP_2_BIT ((unsigned int) 0x2 << 12) // (USART) 2 stop bits -#define AT91C_US_MSBF ((unsigned int) 0x1 << 16) // (USART) Bit Order -#define AT91C_US_MODE9 ((unsigned int) 0x1 << 17) // (USART) 9-bit Character length -#define AT91C_US_CKLO ((unsigned int) 0x1 << 18) // (USART) Clock Output Select -#define AT91C_US_OVER ((unsigned int) 0x1 << 19) // (USART) Over Sampling Mode -#define AT91C_US_INACK ((unsigned int) 0x1 << 20) // (USART) Inhibit Non Acknowledge -#define AT91C_US_DSNACK ((unsigned int) 0x1 << 21) // (USART) Disable Successive NACK -#define AT91C_US_MAX_ITER ((unsigned int) 0x1 << 24) // (USART) Number of Repetitions -#define AT91C_US_FILTER ((unsigned int) 0x1 << 28) // (USART) Receive Line Filter -// -------- US_IER : (USART Offset: 0x8) Debug Unit Interrupt Enable Register -------- -#define AT91C_US_RXBRK ((unsigned int) 0x1 << 2) // (USART) Break Received/End of Break -#define AT91C_US_TIMEOUT ((unsigned int) 0x1 << 8) // (USART) Receiver Time-out -#define AT91C_US_ITERATION ((unsigned int) 0x1 << 10) // (USART) Max number of Repetitions Reached -#define AT91C_US_NACK ((unsigned int) 0x1 << 13) // (USART) Non Acknowledge -#define AT91C_US_RIIC ((unsigned int) 0x1 << 16) // (USART) Ring INdicator Input Change Flag -#define AT91C_US_DSRIC ((unsigned int) 0x1 << 17) // (USART) Data Set Ready Input Change Flag -#define AT91C_US_DCDIC ((unsigned int) 0x1 << 18) // (USART) Data Carrier Flag -#define AT91C_US_CTSIC ((unsigned int) 0x1 << 19) // (USART) Clear To Send Input Change Flag -// -------- US_IDR : (USART Offset: 0xc) Debug Unit Interrupt Disable Register -------- -// -------- US_IMR : (USART Offset: 0x10) Debug Unit Interrupt Mask Register -------- -// -------- US_CSR : (USART Offset: 0x14) Debug Unit Channel Status Register -------- -#define AT91C_US_RI ((unsigned int) 0x1 << 20) // (USART) Image of RI Input -#define AT91C_US_DSR ((unsigned int) 0x1 << 21) // (USART) Image of DSR Input -#define AT91C_US_DCD ((unsigned int) 0x1 << 22) // (USART) Image of DCD Input -#define AT91C_US_CTS ((unsigned int) 0x1 << 23) // (USART) Image of CTS Input - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Synchronous Serial Controller Interface -// ***************************************************************************** -typedef struct _AT91S_SSC { - AT91_REG SSC_CR; // Control Register - AT91_REG SSC_CMR; // Clock Mode Register - AT91_REG Reserved0[2]; // - AT91_REG SSC_RCMR; // Receive Clock ModeRegister - AT91_REG SSC_RFMR; // Receive Frame Mode Register - AT91_REG SSC_TCMR; // Transmit Clock Mode Register - AT91_REG SSC_TFMR; // Transmit Frame Mode Register - AT91_REG SSC_RHR; // Receive Holding Register - AT91_REG SSC_THR; // Transmit Holding Register - AT91_REG Reserved1[2]; // - AT91_REG SSC_RSHR; // Receive Sync Holding Register - AT91_REG SSC_TSHR; // Transmit Sync Holding Register - AT91_REG Reserved2[2]; // - AT91_REG SSC_SR; // Status Register - AT91_REG SSC_IER; // Interrupt Enable Register - AT91_REG SSC_IDR; // Interrupt Disable Register - AT91_REG SSC_IMR; // Interrupt Mask Register - AT91_REG Reserved3[44]; // - AT91_REG SSC_RPR; // Receive Pointer Register - AT91_REG SSC_RCR; // Receive Counter Register - AT91_REG SSC_TPR; // Transmit Pointer Register - AT91_REG SSC_TCR; // Transmit Counter Register - AT91_REG SSC_RNPR; // Receive Next Pointer Register - AT91_REG SSC_RNCR; // Receive Next Counter Register - AT91_REG SSC_TNPR; // Transmit Next Pointer Register - AT91_REG SSC_TNCR; // Transmit Next Counter Register - AT91_REG SSC_PTCR; // PDC Transfer Control Register - AT91_REG SSC_PTSR; // PDC Transfer Status Register -} AT91S_SSC, *AT91PS_SSC; - -// -------- SSC_CR : (SSC Offset: 0x0) SSC Control Register -------- -#define AT91C_SSC_RXEN ((unsigned int) 0x1 << 0) // (SSC) Receive Enable -#define AT91C_SSC_RXDIS ((unsigned int) 0x1 << 1) // (SSC) Receive Disable -#define AT91C_SSC_TXEN ((unsigned int) 0x1 << 8) // (SSC) Transmit Enable -#define AT91C_SSC_TXDIS ((unsigned int) 0x1 << 9) // (SSC) Transmit Disable -#define AT91C_SSC_SWRST ((unsigned int) 0x1 << 15) // (SSC) Software Reset -// -------- SSC_RCMR : (SSC Offset: 0x10) SSC Receive Clock Mode Register -------- -#define AT91C_SSC_CKS ((unsigned int) 0x3 << 0) // (SSC) Receive/Transmit Clock Selection -#define AT91C_SSC_CKS_DIV ((unsigned int) 0x0) // (SSC) Divided Clock -#define AT91C_SSC_CKS_TK ((unsigned int) 0x1) // (SSC) TK Clock signal -#define AT91C_SSC_CKS_RK ((unsigned int) 0x2) // (SSC) RK pin -#define AT91C_SSC_CKO ((unsigned int) 0x7 << 2) // (SSC) Receive/Transmit Clock Output Mode Selection -#define AT91C_SSC_CKO_NONE ((unsigned int) 0x0 << 2) // (SSC) Receive/Transmit Clock Output Mode: None RK pin: Input-only -#define AT91C_SSC_CKO_CONTINOUS ((unsigned int) 0x1 << 2) // (SSC) Continuous Receive/Transmit Clock RK pin: Output -#define AT91C_SSC_CKO_DATA_TX ((unsigned int) 0x2 << 2) // (SSC) Receive/Transmit Clock only during data transfers RK pin: Output -#define AT91C_SSC_CKI ((unsigned int) 0x1 << 5) // (SSC) Receive/Transmit Clock Inversion -#define AT91C_SSC_START ((unsigned int) 0xF << 8) // (SSC) Receive/Transmit Start Selection -#define AT91C_SSC_START_CONTINOUS ((unsigned int) 0x0 << 8) // (SSC) Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data. -#define AT91C_SSC_START_TX ((unsigned int) 0x1 << 8) // (SSC) Transmit/Receive start -#define AT91C_SSC_START_LOW_RF ((unsigned int) 0x2 << 8) // (SSC) Detection of a low level on RF input -#define AT91C_SSC_START_HIGH_RF ((unsigned int) 0x3 << 8) // (SSC) Detection of a high level on RF input -#define AT91C_SSC_START_FALL_RF ((unsigned int) 0x4 << 8) // (SSC) Detection of a falling edge on RF input -#define AT91C_SSC_START_RISE_RF ((unsigned int) 0x5 << 8) // (SSC) Detection of a rising edge on RF input -#define AT91C_SSC_START_LEVEL_RF ((unsigned int) 0x6 << 8) // (SSC) Detection of any level change on RF input -#define AT91C_SSC_START_EDGE_RF ((unsigned int) 0x7 << 8) // (SSC) Detection of any edge on RF input -#define AT91C_SSC_START_0 ((unsigned int) 0x8 << 8) // (SSC) Compare 0 -#define AT91C_SSC_STTDLY ((unsigned int) 0xFF << 16) // (SSC) Receive/Transmit Start Delay -#define AT91C_SSC_PERIOD ((unsigned int) 0xFF << 24) // (SSC) Receive/Transmit Period Divider Selection -// -------- SSC_RFMR : (SSC Offset: 0x14) SSC Receive Frame Mode Register -------- -#define AT91C_SSC_DATLEN ((unsigned int) 0x1F << 0) // (SSC) Data Length -#define AT91C_SSC_LOOP ((unsigned int) 0x1 << 5) // (SSC) Loop Mode -#define AT91C_SSC_MSBF ((unsigned int) 0x1 << 7) // (SSC) Most Significant Bit First -#define AT91C_SSC_DATNB ((unsigned int) 0xF << 8) // (SSC) Data Number per Frame -#define AT91C_SSC_FSLEN ((unsigned int) 0xF << 16) // (SSC) Receive/Transmit Frame Sync length -#define AT91C_SSC_FSOS ((unsigned int) 0x7 << 20) // (SSC) Receive/Transmit Frame Sync Output Selection -#define AT91C_SSC_FSOS_NONE ((unsigned int) 0x0 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: None RK pin Input-only -#define AT91C_SSC_FSOS_NEGATIVE ((unsigned int) 0x1 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Negative Pulse -#define AT91C_SSC_FSOS_POSITIVE ((unsigned int) 0x2 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Positive Pulse -#define AT91C_SSC_FSOS_LOW ((unsigned int) 0x3 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver Low during data transfer -#define AT91C_SSC_FSOS_HIGH ((unsigned int) 0x4 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver High during data transfer -#define AT91C_SSC_FSOS_TOGGLE ((unsigned int) 0x5 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Toggling at each start of data transfer -#define AT91C_SSC_FSEDGE ((unsigned int) 0x1 << 24) // (SSC) Frame Sync Edge Detection -// -------- SSC_TCMR : (SSC Offset: 0x18) SSC Transmit Clock Mode Register -------- -// -------- SSC_TFMR : (SSC Offset: 0x1c) SSC Transmit Frame Mode Register -------- -#define AT91C_SSC_DATDEF ((unsigned int) 0x1 << 5) // (SSC) Data Default Value -#define AT91C_SSC_FSDEN ((unsigned int) 0x1 << 23) // (SSC) Frame Sync Data Enable -// -------- SSC_SR : (SSC Offset: 0x40) SSC Status Register -------- -#define AT91C_SSC_TXRDY ((unsigned int) 0x1 << 0) // (SSC) Transmit Ready -#define AT91C_SSC_TXEMPTY ((unsigned int) 0x1 << 1) // (SSC) Transmit Empty -#define AT91C_SSC_ENDTX ((unsigned int) 0x1 << 2) // (SSC) End Of Transmission -#define AT91C_SSC_TXBUFE ((unsigned int) 0x1 << 3) // (SSC) Transmit Buffer Empty -#define AT91C_SSC_RXRDY ((unsigned int) 0x1 << 4) // (SSC) Receive Ready -#define AT91C_SSC_OVRUN ((unsigned int) 0x1 << 5) // (SSC) Receive Overrun -#define AT91C_SSC_ENDRX ((unsigned int) 0x1 << 6) // (SSC) End of Reception -#define AT91C_SSC_RXBUFF ((unsigned int) 0x1 << 7) // (SSC) Receive Buffer Full -#define AT91C_SSC_TXSYN ((unsigned int) 0x1 << 10) // (SSC) Transmit Sync -#define AT91C_SSC_RXSYN ((unsigned int) 0x1 << 11) // (SSC) Receive Sync -#define AT91C_SSC_TXENA ((unsigned int) 0x1 << 16) // (SSC) Transmit Enable -#define AT91C_SSC_RXENA ((unsigned int) 0x1 << 17) // (SSC) Receive Enable -// -------- SSC_IER : (SSC Offset: 0x44) SSC Interrupt Enable Register -------- -// -------- SSC_IDR : (SSC Offset: 0x48) SSC Interrupt Disable Register -------- -// -------- SSC_IMR : (SSC Offset: 0x4c) SSC Interrupt Mask Register -------- - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Two-wire Interface -// ***************************************************************************** -typedef struct _AT91S_TWI { - AT91_REG TWI_CR; // Control Register - AT91_REG TWI_MMR; // Master Mode Register - AT91_REG Reserved0[1]; // - AT91_REG TWI_IADR; // Internal Address Register - AT91_REG TWI_CWGR; // Clock Waveform Generator Register - AT91_REG Reserved1[3]; // - AT91_REG TWI_SR; // Status Register - AT91_REG TWI_IER; // Interrupt Enable Register - AT91_REG TWI_IDR; // Interrupt Disable Register - AT91_REG TWI_IMR; // Interrupt Mask Register - AT91_REG TWI_RHR; // Receive Holding Register - AT91_REG TWI_THR; // Transmit Holding Register -} AT91S_TWI, *AT91PS_TWI; - -// -------- TWI_CR : (TWI Offset: 0x0) TWI Control Register -------- -#define AT91C_TWI_START ((unsigned int) 0x1 << 0) // (TWI) Send a START Condition -#define AT91C_TWI_STOP ((unsigned int) 0x1 << 1) // (TWI) Send a STOP Condition -#define AT91C_TWI_MSEN ((unsigned int) 0x1 << 2) // (TWI) TWI Master Transfer Enabled -#define AT91C_TWI_MSDIS ((unsigned int) 0x1 << 3) // (TWI) TWI Master Transfer Disabled -#define AT91C_TWI_SWRST ((unsigned int) 0x1 << 7) // (TWI) Software Reset -// -------- TWI_MMR : (TWI Offset: 0x4) TWI Master Mode Register -------- -#define AT91C_TWI_IADRSZ ((unsigned int) 0x3 << 8) // (TWI) Internal Device Address Size -#define AT91C_TWI_IADRSZ_NO ((unsigned int) 0x0 << 8) // (TWI) No internal device address -#define AT91C_TWI_IADRSZ_1_BYTE ((unsigned int) 0x1 << 8) // (TWI) One-byte internal device address -#define AT91C_TWI_IADRSZ_2_BYTE ((unsigned int) 0x2 << 8) // (TWI) Two-byte internal device address -#define AT91C_TWI_IADRSZ_3_BYTE ((unsigned int) 0x3 << 8) // (TWI) Three-byte internal device address -#define AT91C_TWI_MREAD ((unsigned int) 0x1 << 12) // (TWI) Master Read Direction -#define AT91C_TWI_DADR ((unsigned int) 0x7F << 16) // (TWI) Device Address -// -------- TWI_CWGR : (TWI Offset: 0x10) TWI Clock Waveform Generator Register -------- -#define AT91C_TWI_CLDIV ((unsigned int) 0xFF << 0) // (TWI) Clock Low Divider -#define AT91C_TWI_CHDIV ((unsigned int) 0xFF << 8) // (TWI) Clock High Divider -#define AT91C_TWI_CKDIV ((unsigned int) 0x7 << 16) // (TWI) Clock Divider -// -------- TWI_SR : (TWI Offset: 0x20) TWI Status Register -------- -#define AT91C_TWI_TXCOMP ((unsigned int) 0x1 << 0) // (TWI) Transmission Completed -#define AT91C_TWI_RXRDY ((unsigned int) 0x1 << 1) // (TWI) Receive holding register ReaDY -#define AT91C_TWI_TXRDY ((unsigned int) 0x1 << 2) // (TWI) Transmit holding register ReaDY -#define AT91C_TWI_OVRE ((unsigned int) 0x1 << 6) // (TWI) Overrun Error -#define AT91C_TWI_UNRE ((unsigned int) 0x1 << 7) // (TWI) Underrun Error -#define AT91C_TWI_NACK ((unsigned int) 0x1 << 8) // (TWI) Not Acknowledged -// -------- TWI_IER : (TWI Offset: 0x24) TWI Interrupt Enable Register -------- -// -------- TWI_IDR : (TWI Offset: 0x28) TWI Interrupt Disable Register -------- -// -------- TWI_IMR : (TWI Offset: 0x2c) TWI Interrupt Mask Register -------- - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR PWMC Channel Interface -// ***************************************************************************** -typedef struct _AT91S_PWMC_CH { - AT91_REG PWMC_CMR; // Channel Mode Register - AT91_REG PWMC_CDTYR; // Channel Duty Cycle Register - AT91_REG PWMC_CPRDR; // Channel Period Register - AT91_REG PWMC_CCNTR; // Channel Counter Register - AT91_REG PWMC_CUPDR; // Channel Update Register - AT91_REG PWMC_Reserved[3]; // Reserved -} AT91S_PWMC_CH, *AT91PS_PWMC_CH; - -// -------- PWMC_CMR : (PWMC_CH Offset: 0x0) PWMC Channel Mode Register -------- -#define AT91C_PWMC_CPRE ((unsigned int) 0xF << 0) // (PWMC_CH) Channel Pre-scaler : PWMC_CLKx -#define AT91C_PWMC_CPRE_MCK ((unsigned int) 0x0) // (PWMC_CH) -#define AT91C_PWMC_CPRE_MCKA ((unsigned int) 0xB) // (PWMC_CH) -#define AT91C_PWMC_CPRE_MCKB ((unsigned int) 0xC) // (PWMC_CH) -#define AT91C_PWMC_CALG ((unsigned int) 0x1 << 8) // (PWMC_CH) Channel Alignment -#define AT91C_PWMC_CPOL ((unsigned int) 0x1 << 9) // (PWMC_CH) Channel Polarity -#define AT91C_PWMC_CPD ((unsigned int) 0x1 << 10) // (PWMC_CH) Channel Update Period -// -------- PWMC_CDTYR : (PWMC_CH Offset: 0x4) PWMC Channel Duty Cycle Register -------- -#define AT91C_PWMC_CDTY ((unsigned int) 0x0 << 0) // (PWMC_CH) Channel Duty Cycle -// -------- PWMC_CPRDR : (PWMC_CH Offset: 0x8) PWMC Channel Period Register -------- -#define AT91C_PWMC_CPRD ((unsigned int) 0x0 << 0) // (PWMC_CH) Channel Period -// -------- PWMC_CCNTR : (PWMC_CH Offset: 0xc) PWMC Channel Counter Register -------- -#define AT91C_PWMC_CCNT ((unsigned int) 0x0 << 0) // (PWMC_CH) Channel Counter -// -------- PWMC_CUPDR : (PWMC_CH Offset: 0x10) PWMC Channel Update Register -------- -#define AT91C_PWMC_CUPD ((unsigned int) 0x0 << 0) // (PWMC_CH) Channel Update - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Pulse Width Modulation Controller Interface -// ***************************************************************************** -typedef struct _AT91S_PWMC { - AT91_REG PWMC_MR; // PWMC Mode Register - AT91_REG PWMC_ENA; // PWMC Enable Register - AT91_REG PWMC_DIS; // PWMC Disable Register - AT91_REG PWMC_SR; // PWMC Status Register - AT91_REG PWMC_IER; // PWMC Interrupt Enable Register - AT91_REG PWMC_IDR; // PWMC Interrupt Disable Register - AT91_REG PWMC_IMR; // PWMC Interrupt Mask Register - AT91_REG PWMC_ISR; // PWMC Interrupt Status Register - AT91_REG Reserved0[55]; // - AT91_REG PWMC_VR; // PWMC Version Register - AT91_REG Reserved1[64]; // - AT91S_PWMC_CH PWMC_CH[4]; // PWMC Channel -} AT91S_PWMC, *AT91PS_PWMC; - -// -------- PWMC_MR : (PWMC Offset: 0x0) PWMC Mode Register -------- -#define AT91C_PWMC_DIVA ((unsigned int) 0xFF << 0) // (PWMC) CLKA divide factor. -#define AT91C_PWMC_PREA ((unsigned int) 0xF << 8) // (PWMC) Divider Input Clock Prescaler A -#define AT91C_PWMC_PREA_MCK ((unsigned int) 0x0 << 8) // (PWMC) -#define AT91C_PWMC_DIVB ((unsigned int) 0xFF << 16) // (PWMC) CLKB divide factor. -#define AT91C_PWMC_PREB ((unsigned int) 0xF << 24) // (PWMC) Divider Input Clock Prescaler B -#define AT91C_PWMC_PREB_MCK ((unsigned int) 0x0 << 24) // (PWMC) -// -------- PWMC_ENA : (PWMC Offset: 0x4) PWMC Enable Register -------- -#define AT91C_PWMC_CHID0 ((unsigned int) 0x1 << 0) // (PWMC) Channel ID 0 -#define AT91C_PWMC_CHID1 ((unsigned int) 0x1 << 1) // (PWMC) Channel ID 1 -#define AT91C_PWMC_CHID2 ((unsigned int) 0x1 << 2) // (PWMC) Channel ID 2 -#define AT91C_PWMC_CHID3 ((unsigned int) 0x1 << 3) // (PWMC) Channel ID 3 -// -------- PWMC_DIS : (PWMC Offset: 0x8) PWMC Disable Register -------- -// -------- PWMC_SR : (PWMC Offset: 0xc) PWMC Status Register -------- -// -------- PWMC_IER : (PWMC Offset: 0x10) PWMC Interrupt Enable Register -------- -// -------- PWMC_IDR : (PWMC Offset: 0x14) PWMC Interrupt Disable Register -------- -// -------- PWMC_IMR : (PWMC Offset: 0x18) PWMC Interrupt Mask Register -------- -// -------- PWMC_ISR : (PWMC Offset: 0x1c) PWMC Interrupt Status Register -------- - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR USB Device Interface -// ***************************************************************************** -typedef struct _AT91S_UDP { - AT91_REG UDP_NUM; // Frame Number Register - AT91_REG UDP_GLBSTATE; // Global State Register - AT91_REG UDP_FADDR; // Function Address Register - AT91_REG Reserved0[1]; // - AT91_REG UDP_IER; // Interrupt Enable Register - AT91_REG UDP_IDR; // Interrupt Disable Register - AT91_REG UDP_IMR; // Interrupt Mask Register - AT91_REG UDP_ISR; // Interrupt Status Register - AT91_REG UDP_ICR; // Interrupt Clear Register - AT91_REG Reserved1[1]; // - AT91_REG UDP_RSTEP; // Reset Endpoint Register - AT91_REG Reserved2[1]; // - AT91_REG UDP_CSR[6]; // Endpoint Control and Status Register - AT91_REG Reserved3[2]; // - AT91_REG UDP_FDR[6]; // Endpoint FIFO Data Register - AT91_REG Reserved4[3]; // - AT91_REG UDP_TXVC; // Transceiver Control Register -} AT91S_UDP, *AT91PS_UDP; - -// -------- UDP_FRM_NUM : (UDP Offset: 0x0) USB Frame Number Register -------- -#define AT91C_UDP_FRM_NUM ((unsigned int) 0x7FF << 0) // (UDP) Frame Number as Defined in the Packet Field Formats -#define AT91C_UDP_FRM_ERR ((unsigned int) 0x1 << 16) // (UDP) Frame Error -#define AT91C_UDP_FRM_OK ((unsigned int) 0x1 << 17) // (UDP) Frame OK -// -------- UDP_GLB_STATE : (UDP Offset: 0x4) USB Global State Register -------- -#define AT91C_UDP_FADDEN ((unsigned int) 0x1 << 0) // (UDP) Function Address Enable -#define AT91C_UDP_CONFG ((unsigned int) 0x1 << 1) // (UDP) Configured -#define AT91C_UDP_ESR ((unsigned int) 0x1 << 2) // (UDP) Enable Send Resume -#define AT91C_UDP_RSMINPR ((unsigned int) 0x1 << 3) // (UDP) A Resume Has Been Sent to the Host -#define AT91C_UDP_RMWUPE ((unsigned int) 0x1 << 4) // (UDP) Remote Wake Up Enable -// -------- UDP_FADDR : (UDP Offset: 0x8) USB Function Address Register -------- -#define AT91C_UDP_FADD ((unsigned int) 0xFF << 0) // (UDP) Function Address Value -#define AT91C_UDP_FEN ((unsigned int) 0x1 << 8) // (UDP) Function Enable -// -------- UDP_IER : (UDP Offset: 0x10) USB Interrupt Enable Register -------- -#define AT91C_UDP_EPINT0 ((unsigned int) 0x1 << 0) // (UDP) Endpoint 0 Interrupt -#define AT91C_UDP_EPINT1 ((unsigned int) 0x1 << 1) // (UDP) Endpoint 0 Interrupt -#define AT91C_UDP_EPINT2 ((unsigned int) 0x1 << 2) // (UDP) Endpoint 2 Interrupt -#define AT91C_UDP_EPINT3 ((unsigned int) 0x1 << 3) // (UDP) Endpoint 3 Interrupt -#define AT91C_UDP_EPINT4 ((unsigned int) 0x1 << 4) // (UDP) Endpoint 4 Interrupt -#define AT91C_UDP_EPINT5 ((unsigned int) 0x1 << 5) // (UDP) Endpoint 5 Interrupt -#define AT91C_UDP_RXSUSP ((unsigned int) 0x1 << 8) // (UDP) USB Suspend Interrupt -#define AT91C_UDP_RXRSM ((unsigned int) 0x1 << 9) // (UDP) USB Resume Interrupt -#define AT91C_UDP_EXTRSM ((unsigned int) 0x1 << 10) // (UDP) USB External Resume Interrupt -#define AT91C_UDP_SOFINT ((unsigned int) 0x1 << 11) // (UDP) USB Start Of frame Interrupt -#define AT91C_UDP_WAKEUP ((unsigned int) 0x1 << 13) // (UDP) USB Resume Interrupt -// -------- UDP_IDR : (UDP Offset: 0x14) USB Interrupt Disable Register -------- -// -------- UDP_IMR : (UDP Offset: 0x18) USB Interrupt Mask Register -------- -// -------- UDP_ISR : (UDP Offset: 0x1c) USB Interrupt Status Register -------- -#define AT91C_UDP_ENDBUSRES ((unsigned int) 0x1 << 12) // (UDP) USB End Of Bus Reset Interrupt -// -------- UDP_ICR : (UDP Offset: 0x20) USB Interrupt Clear Register -------- -// -------- UDP_RST_EP : (UDP Offset: 0x28) USB Reset Endpoint Register -------- -#define AT91C_UDP_EP0 ((unsigned int) 0x1 << 0) // (UDP) Reset Endpoint 0 -#define AT91C_UDP_EP1 ((unsigned int) 0x1 << 1) // (UDP) Reset Endpoint 1 -#define AT91C_UDP_EP2 ((unsigned int) 0x1 << 2) // (UDP) Reset Endpoint 2 -#define AT91C_UDP_EP3 ((unsigned int) 0x1 << 3) // (UDP) Reset Endpoint 3 -#define AT91C_UDP_EP4 ((unsigned int) 0x1 << 4) // (UDP) Reset Endpoint 4 -#define AT91C_UDP_EP5 ((unsigned int) 0x1 << 5) // (UDP) Reset Endpoint 5 -// -------- UDP_CSR : (UDP Offset: 0x30) USB Endpoint Control and Status Register -------- -#define AT91C_UDP_TXCOMP ((unsigned int) 0x1 << 0) // (UDP) Generates an IN packet with data previously written in the DPR -#define AT91C_UDP_RX_DATA_BK0 ((unsigned int) 0x1 << 1) // (UDP) Receive Data Bank 0 -#define AT91C_UDP_RXSETUP ((unsigned int) 0x1 << 2) // (UDP) Sends STALL to the Host (Control endpoints) -#define AT91C_UDP_ISOERROR ((unsigned int) 0x1 << 3) // (UDP) Isochronous error (Isochronous endpoints) -#define AT91C_UDP_TXPKTRDY ((unsigned int) 0x1 << 4) // (UDP) Transmit Packet Ready -#define AT91C_UDP_FORCESTALL ((unsigned int) 0x1 << 5) // (UDP) Force Stall (used by Control, Bulk and Isochronous endpoints). -#define AT91C_UDP_RX_DATA_BK1 ((unsigned int) 0x1 << 6) // (UDP) Receive Data Bank 1 (only used by endpoints with ping-pong attributes). -#define AT91C_UDP_DIR ((unsigned int) 0x1 << 7) // (UDP) Transfer Direction -#define AT91C_UDP_EPTYPE ((unsigned int) 0x7 << 8) // (UDP) Endpoint type -#define AT91C_UDP_EPTYPE_CTRL ((unsigned int) 0x0 << 8) // (UDP) Control -#define AT91C_UDP_EPTYPE_ISO_OUT ((unsigned int) 0x1 << 8) // (UDP) Isochronous OUT -#define AT91C_UDP_EPTYPE_BULK_OUT ((unsigned int) 0x2 << 8) // (UDP) Bulk OUT -#define AT91C_UDP_EPTYPE_INT_OUT ((unsigned int) 0x3 << 8) // (UDP) Interrupt OUT -#define AT91C_UDP_EPTYPE_ISO_IN ((unsigned int) 0x5 << 8) // (UDP) Isochronous IN -#define AT91C_UDP_EPTYPE_BULK_IN ((unsigned int) 0x6 << 8) // (UDP) Bulk IN -#define AT91C_UDP_EPTYPE_INT_IN ((unsigned int) 0x7 << 8) // (UDP) Interrupt IN -#define AT91C_UDP_DTGLE ((unsigned int) 0x1 << 11) // (UDP) Data Toggle -#define AT91C_UDP_EPEDS ((unsigned int) 0x1 << 15) // (UDP) Endpoint Enable Disable -#define AT91C_UDP_RXBYTECNT ((unsigned int) 0x7FF << 16) // (UDP) Number Of Bytes Available in the FIFO -// -------- UDP_TXVC : (UDP Offset: 0x74) Transceiver Control Register -------- -#define AT91C_UDP_TXVDIS ((unsigned int) 0x1 << 8) // (UDP) -#define AT91C_UDP_PUON ((unsigned int) 0x1 << 9) // (UDP) Pull-up ON - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Timer Counter Channel Interface -// ***************************************************************************** -typedef struct _AT91S_TC { - AT91_REG TC_CCR; // Channel Control Register - AT91_REG TC_CMR; // Channel Mode Register (Capture Mode / Waveform Mode) - AT91_REG Reserved0[2]; // - AT91_REG TC_CV; // Counter Value - AT91_REG TC_RA; // Register A - AT91_REG TC_RB; // Register B - AT91_REG TC_RC; // Register C - AT91_REG TC_SR; // Status Register - AT91_REG TC_IER; // Interrupt Enable Register - AT91_REG TC_IDR; // Interrupt Disable Register - AT91_REG TC_IMR; // Interrupt Mask Register -} AT91S_TC, *AT91PS_TC; - -// -------- TC_CCR : (TC Offset: 0x0) TC Channel Control Register -------- -#define AT91C_TC_CLKEN ((unsigned int) 0x1 << 0) // (TC) Counter Clock Enable Command -#define AT91C_TC_CLKDIS ((unsigned int) 0x1 << 1) // (TC) Counter Clock Disable Command -#define AT91C_TC_SWTRG ((unsigned int) 0x1 << 2) // (TC) Software Trigger Command -// -------- TC_CMR : (TC Offset: 0x4) TC Channel Mode Register: Capture Mode / Waveform Mode -------- -#define AT91C_TC_CLKS ((unsigned int) 0x7 << 0) // (TC) Clock Selection -#define AT91C_TC_CLKS_TIMER_DIV1_CLOCK ((unsigned int) 0x0) // (TC) Clock selected: TIMER_DIV1_CLOCK -#define AT91C_TC_CLKS_TIMER_DIV2_CLOCK ((unsigned int) 0x1) // (TC) Clock selected: TIMER_DIV2_CLOCK -#define AT91C_TC_CLKS_TIMER_DIV3_CLOCK ((unsigned int) 0x2) // (TC) Clock selected: TIMER_DIV3_CLOCK -#define AT91C_TC_CLKS_TIMER_DIV4_CLOCK ((unsigned int) 0x3) // (TC) Clock selected: TIMER_DIV4_CLOCK -#define AT91C_TC_CLKS_TIMER_DIV5_CLOCK ((unsigned int) 0x4) // (TC) Clock selected: TIMER_DIV5_CLOCK -#define AT91C_TC_CLKS_XC0 ((unsigned int) 0x5) // (TC) Clock selected: XC0 -#define AT91C_TC_CLKS_XC1 ((unsigned int) 0x6) // (TC) Clock selected: XC1 -#define AT91C_TC_CLKS_XC2 ((unsigned int) 0x7) // (TC) Clock selected: XC2 -#define AT91C_TC_CLKI ((unsigned int) 0x1 << 3) // (TC) Clock Invert -#define AT91C_TC_BURST ((unsigned int) 0x3 << 4) // (TC) Burst Signal Selection -#define AT91C_TC_BURST_NONE ((unsigned int) 0x0 << 4) // (TC) The clock is not gated by an external signal -#define AT91C_TC_BURST_XC0 ((unsigned int) 0x1 << 4) // (TC) XC0 is ANDed with the selected clock -#define AT91C_TC_BURST_XC1 ((unsigned int) 0x2 << 4) // (TC) XC1 is ANDed with the selected clock -#define AT91C_TC_BURST_XC2 ((unsigned int) 0x3 << 4) // (TC) XC2 is ANDed with the selected clock -#define AT91C_TC_CPCSTOP ((unsigned int) 0x1 << 6) // (TC) Counter Clock Stopped with RC Compare -#define AT91C_TC_LDBSTOP ((unsigned int) 0x1 << 6) // (TC) Counter Clock Stopped with RB Loading -#define AT91C_TC_CPCDIS ((unsigned int) 0x1 << 7) // (TC) Counter Clock Disable with RC Compare -#define AT91C_TC_LDBDIS ((unsigned int) 0x1 << 7) // (TC) Counter Clock Disabled with RB Loading -#define AT91C_TC_ETRGEDG ((unsigned int) 0x3 << 8) // (TC) External Trigger Edge Selection -#define AT91C_TC_ETRGEDG_NONE ((unsigned int) 0x0 << 8) // (TC) Edge: None -#define AT91C_TC_ETRGEDG_RISING ((unsigned int) 0x1 << 8) // (TC) Edge: rising edge -#define AT91C_TC_ETRGEDG_FALLING ((unsigned int) 0x2 << 8) // (TC) Edge: falling edge -#define AT91C_TC_ETRGEDG_BOTH ((unsigned int) 0x3 << 8) // (TC) Edge: each edge -#define AT91C_TC_EEVTEDG ((unsigned int) 0x3 << 8) // (TC) External Event Edge Selection -#define AT91C_TC_EEVTEDG_NONE ((unsigned int) 0x0 << 8) // (TC) Edge: None -#define AT91C_TC_EEVTEDG_RISING ((unsigned int) 0x1 << 8) // (TC) Edge: rising edge -#define AT91C_TC_EEVTEDG_FALLING ((unsigned int) 0x2 << 8) // (TC) Edge: falling edge -#define AT91C_TC_EEVTEDG_BOTH ((unsigned int) 0x3 << 8) // (TC) Edge: each edge -#define AT91C_TC_EEVT ((unsigned int) 0x3 << 10) // (TC) External Event Selection -#define AT91C_TC_EEVT_TIOB ((unsigned int) 0x0 << 10) // (TC) Signal selected as external event: TIOB TIOB direction: input -#define AT91C_TC_EEVT_XC0 ((unsigned int) 0x1 << 10) // (TC) Signal selected as external event: XC0 TIOB direction: output -#define AT91C_TC_EEVT_XC1 ((unsigned int) 0x2 << 10) // (TC) Signal selected as external event: XC1 TIOB direction: output -#define AT91C_TC_EEVT_XC2 ((unsigned int) 0x3 << 10) // (TC) Signal selected as external event: XC2 TIOB direction: output -#define AT91C_TC_ABETRG ((unsigned int) 0x1 << 10) // (TC) TIOA or TIOB External Trigger Selection -#define AT91C_TC_ENETRG ((unsigned int) 0x1 << 12) // (TC) External Event Trigger enable -#define AT91C_TC_WAVESEL ((unsigned int) 0x3 << 13) // (TC) Waveform Selection -#define AT91C_TC_WAVESEL_UP ((unsigned int) 0x0 << 13) // (TC) UP mode without atomatic trigger on RC Compare -#define AT91C_TC_WAVESEL_UPDOWN ((unsigned int) 0x1 << 13) // (TC) UPDOWN mode without automatic trigger on RC Compare -#define AT91C_TC_WAVESEL_UP_AUTO ((unsigned int) 0x2 << 13) // (TC) UP mode with automatic trigger on RC Compare -#define AT91C_TC_WAVESEL_UPDOWN_AUTO ((unsigned int) 0x3 << 13) // (TC) UPDOWN mode with automatic trigger on RC Compare -#define AT91C_TC_CPCTRG ((unsigned int) 0x1 << 14) // (TC) RC Compare Trigger Enable -#define AT91C_TC_WAVE ((unsigned int) 0x1 << 15) // (TC) -#define AT91C_TC_ACPA ((unsigned int) 0x3 << 16) // (TC) RA Compare Effect on TIOA -#define AT91C_TC_ACPA_NONE ((unsigned int) 0x0 << 16) // (TC) Effect: none -#define AT91C_TC_ACPA_SET ((unsigned int) 0x1 << 16) // (TC) Effect: set -#define AT91C_TC_ACPA_CLEAR ((unsigned int) 0x2 << 16) // (TC) Effect: clear -#define AT91C_TC_ACPA_TOGGLE ((unsigned int) 0x3 << 16) // (TC) Effect: toggle -#define AT91C_TC_LDRA ((unsigned int) 0x3 << 16) // (TC) RA Loading Selection -#define AT91C_TC_LDRA_NONE ((unsigned int) 0x0 << 16) // (TC) Edge: None -#define AT91C_TC_LDRA_RISING ((unsigned int) 0x1 << 16) // (TC) Edge: rising edge of TIOA -#define AT91C_TC_LDRA_FALLING ((unsigned int) 0x2 << 16) // (TC) Edge: falling edge of TIOA -#define AT91C_TC_LDRA_BOTH ((unsigned int) 0x3 << 16) // (TC) Edge: each edge of TIOA -#define AT91C_TC_ACPC ((unsigned int) 0x3 << 18) // (TC) RC Compare Effect on TIOA -#define AT91C_TC_ACPC_NONE ((unsigned int) 0x0 << 18) // (TC) Effect: none -#define AT91C_TC_ACPC_SET ((unsigned int) 0x1 << 18) // (TC) Effect: set -#define AT91C_TC_ACPC_CLEAR ((unsigned int) 0x2 << 18) // (TC) Effect: clear -#define AT91C_TC_ACPC_TOGGLE ((unsigned int) 0x3 << 18) // (TC) Effect: toggle -#define AT91C_TC_LDRB ((unsigned int) 0x3 << 18) // (TC) RB Loading Selection -#define AT91C_TC_LDRB_NONE ((unsigned int) 0x0 << 18) // (TC) Edge: None -#define AT91C_TC_LDRB_RISING ((unsigned int) 0x1 << 18) // (TC) Edge: rising edge of TIOA -#define AT91C_TC_LDRB_FALLING ((unsigned int) 0x2 << 18) // (TC) Edge: falling edge of TIOA -#define AT91C_TC_LDRB_BOTH ((unsigned int) 0x3 << 18) // (TC) Edge: each edge of TIOA -#define AT91C_TC_AEEVT ((unsigned int) 0x3 << 20) // (TC) External Event Effect on TIOA -#define AT91C_TC_AEEVT_NONE ((unsigned int) 0x0 << 20) // (TC) Effect: none -#define AT91C_TC_AEEVT_SET ((unsigned int) 0x1 << 20) // (TC) Effect: set -#define AT91C_TC_AEEVT_CLEAR ((unsigned int) 0x2 << 20) // (TC) Effect: clear -#define AT91C_TC_AEEVT_TOGGLE ((unsigned int) 0x3 << 20) // (TC) Effect: toggle -#define AT91C_TC_ASWTRG ((unsigned int) 0x3 << 22) // (TC) Software Trigger Effect on TIOA -#define AT91C_TC_ASWTRG_NONE ((unsigned int) 0x0 << 22) // (TC) Effect: none -#define AT91C_TC_ASWTRG_SET ((unsigned int) 0x1 << 22) // (TC) Effect: set -#define AT91C_TC_ASWTRG_CLEAR ((unsigned int) 0x2 << 22) // (TC) Effect: clear -#define AT91C_TC_ASWTRG_TOGGLE ((unsigned int) 0x3 << 22) // (TC) Effect: toggle -#define AT91C_TC_BCPB ((unsigned int) 0x3 << 24) // (TC) RB Compare Effect on TIOB -#define AT91C_TC_BCPB_NONE ((unsigned int) 0x0 << 24) // (TC) Effect: none -#define AT91C_TC_BCPB_SET ((unsigned int) 0x1 << 24) // (TC) Effect: set -#define AT91C_TC_BCPB_CLEAR ((unsigned int) 0x2 << 24) // (TC) Effect: clear -#define AT91C_TC_BCPB_TOGGLE ((unsigned int) 0x3 << 24) // (TC) Effect: toggle -#define AT91C_TC_BCPC ((unsigned int) 0x3 << 26) // (TC) RC Compare Effect on TIOB -#define AT91C_TC_BCPC_NONE ((unsigned int) 0x0 << 26) // (TC) Effect: none -#define AT91C_TC_BCPC_SET ((unsigned int) 0x1 << 26) // (TC) Effect: set -#define AT91C_TC_BCPC_CLEAR ((unsigned int) 0x2 << 26) // (TC) Effect: clear -#define AT91C_TC_BCPC_TOGGLE ((unsigned int) 0x3 << 26) // (TC) Effect: toggle -#define AT91C_TC_BEEVT ((unsigned int) 0x3 << 28) // (TC) External Event Effect on TIOB -#define AT91C_TC_BEEVT_NONE ((unsigned int) 0x0 << 28) // (TC) Effect: none -#define AT91C_TC_BEEVT_SET ((unsigned int) 0x1 << 28) // (TC) Effect: set -#define AT91C_TC_BEEVT_CLEAR ((unsigned int) 0x2 << 28) // (TC) Effect: clear -#define AT91C_TC_BEEVT_TOGGLE ((unsigned int) 0x3 << 28) // (TC) Effect: toggle -#define AT91C_TC_BSWTRG ((unsigned int) 0x3 << 30) // (TC) Software Trigger Effect on TIOB -#define AT91C_TC_BSWTRG_NONE ((unsigned int) 0x0 << 30) // (TC) Effect: none -#define AT91C_TC_BSWTRG_SET ((unsigned int) 0x1 << 30) // (TC) Effect: set -#define AT91C_TC_BSWTRG_CLEAR ((unsigned int) 0x2 << 30) // (TC) Effect: clear -#define AT91C_TC_BSWTRG_TOGGLE ((unsigned int) 0x3 << 30) // (TC) Effect: toggle -// -------- TC_SR : (TC Offset: 0x20) TC Channel Status Register -------- -#define AT91C_TC_COVFS ((unsigned int) 0x1 << 0) // (TC) Counter Overflow -#define AT91C_TC_LOVRS ((unsigned int) 0x1 << 1) // (TC) Load Overrun -#define AT91C_TC_CPAS ((unsigned int) 0x1 << 2) // (TC) RA Compare -#define AT91C_TC_CPBS ((unsigned int) 0x1 << 3) // (TC) RB Compare -#define AT91C_TC_CPCS ((unsigned int) 0x1 << 4) // (TC) RC Compare -#define AT91C_TC_LDRAS ((unsigned int) 0x1 << 5) // (TC) RA Loading -#define AT91C_TC_LDRBS ((unsigned int) 0x1 << 6) // (TC) RB Loading -#define AT91C_TC_ETRGS ((unsigned int) 0x1 << 7) // (TC) External Trigger -#define AT91C_TC_CLKSTA ((unsigned int) 0x1 << 16) // (TC) Clock Enabling -#define AT91C_TC_MTIOA ((unsigned int) 0x1 << 17) // (TC) TIOA Mirror -#define AT91C_TC_MTIOB ((unsigned int) 0x1 << 18) // (TC) TIOA Mirror -// -------- TC_IER : (TC Offset: 0x24) TC Channel Interrupt Enable Register -------- -// -------- TC_IDR : (TC Offset: 0x28) TC Channel Interrupt Disable Register -------- -// -------- TC_IMR : (TC Offset: 0x2c) TC Channel Interrupt Mask Register -------- - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Timer Counter Interface -// ***************************************************************************** -typedef struct _AT91S_TCB { - AT91S_TC TCB_TC0; // TC Channel 0 - AT91_REG Reserved0[4]; // - AT91S_TC TCB_TC1; // TC Channel 1 - AT91_REG Reserved1[4]; // - AT91S_TC TCB_TC2; // TC Channel 2 - AT91_REG Reserved2[4]; // - AT91_REG TCB_BCR; // TC Block Control Register - AT91_REG TCB_BMR; // TC Block Mode Register -} AT91S_TCB, *AT91PS_TCB; - -// -------- TCB_BCR : (TCB Offset: 0xc0) TC Block Control Register -------- -#define AT91C_TCB_SYNC ((unsigned int) 0x1 << 0) // (TCB) Synchro Command -// -------- TCB_BMR : (TCB Offset: 0xc4) TC Block Mode Register -------- -#define AT91C_TCB_TC0XC0S ((unsigned int) 0x3 << 0) // (TCB) External Clock Signal 0 Selection -#define AT91C_TCB_TC0XC0S_TCLK0 ((unsigned int) 0x0) // (TCB) TCLK0 connected to XC0 -#define AT91C_TCB_TC0XC0S_NONE ((unsigned int) 0x1) // (TCB) None signal connected to XC0 -#define AT91C_TCB_TC0XC0S_TIOA1 ((unsigned int) 0x2) // (TCB) TIOA1 connected to XC0 -#define AT91C_TCB_TC0XC0S_TIOA2 ((unsigned int) 0x3) // (TCB) TIOA2 connected to XC0 -#define AT91C_TCB_TC1XC1S ((unsigned int) 0x3 << 2) // (TCB) External Clock Signal 1 Selection -#define AT91C_TCB_TC1XC1S_TCLK1 ((unsigned int) 0x0 << 2) // (TCB) TCLK1 connected to XC1 -#define AT91C_TCB_TC1XC1S_NONE ((unsigned int) 0x1 << 2) // (TCB) None signal connected to XC1 -#define AT91C_TCB_TC1XC1S_TIOA0 ((unsigned int) 0x2 << 2) // (TCB) TIOA0 connected to XC1 -#define AT91C_TCB_TC1XC1S_TIOA2 ((unsigned int) 0x3 << 2) // (TCB) TIOA2 connected to XC1 -#define AT91C_TCB_TC2XC2S ((unsigned int) 0x3 << 4) // (TCB) External Clock Signal 2 Selection -#define AT91C_TCB_TC2XC2S_TCLK2 ((unsigned int) 0x0 << 4) // (TCB) TCLK2 connected to XC2 -#define AT91C_TCB_TC2XC2S_NONE ((unsigned int) 0x1 << 4) // (TCB) None signal connected to XC2 -#define AT91C_TCB_TC2XC2S_TIOA0 ((unsigned int) 0x2 << 4) // (TCB) TIOA0 connected to XC2 -#define AT91C_TCB_TC2XC2S_TIOA1 ((unsigned int) 0x3 << 4) // (TCB) TIOA2 connected to XC2 - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Control Area Network MailBox Interface -// ***************************************************************************** -typedef struct _AT91S_CAN_MB { - AT91_REG CAN_MB_MMR; // MailBox Mode Register - AT91_REG CAN_MB_MAM; // MailBox Acceptance Mask Register - AT91_REG CAN_MB_MID; // MailBox ID Register - AT91_REG CAN_MB_MFID; // MailBox Family ID Register - AT91_REG CAN_MB_MSR; // MailBox Status Register - AT91_REG CAN_MB_MDL; // MailBox Data Low Register - AT91_REG CAN_MB_MDH; // MailBox Data High Register - AT91_REG CAN_MB_MCR; // MailBox Control Register -} AT91S_CAN_MB, *AT91PS_CAN_MB; - -// -------- CAN_MMR : (CAN_MB Offset: 0x0) CAN Message Mode Register -------- -#define AT91C_CAN_MTIMEMARK ((unsigned int) 0xFFFF << 0) // (CAN_MB) Mailbox Timemark -#define AT91C_CAN_PRIOR ((unsigned int) 0xF << 16) // (CAN_MB) Mailbox Priority -#define AT91C_CAN_MOT ((unsigned int) 0x7 << 24) // (CAN_MB) Mailbox Object Type -#define AT91C_CAN_MOT_DIS ((unsigned int) 0x0 << 24) // (CAN_MB) -#define AT91C_CAN_MOT_RX ((unsigned int) 0x1 << 24) // (CAN_MB) -#define AT91C_CAN_MOT_RXOVERWRITE ((unsigned int) 0x2 << 24) // (CAN_MB) -#define AT91C_CAN_MOT_TX ((unsigned int) 0x3 << 24) // (CAN_MB) -#define AT91C_CAN_MOT_CONSUMER ((unsigned int) 0x4 << 24) // (CAN_MB) -#define AT91C_CAN_MOT_PRODUCER ((unsigned int) 0x5 << 24) // (CAN_MB) -// -------- CAN_MAM : (CAN_MB Offset: 0x4) CAN Message Acceptance Mask Register -------- -#define AT91C_CAN_MIDvB ((unsigned int) 0x3FFFF << 0) // (CAN_MB) Complementary bits for identifier in extended mode -#define AT91C_CAN_MIDvA ((unsigned int) 0x7FF << 18) // (CAN_MB) Identifier for standard frame mode -#define AT91C_CAN_MIDE ((unsigned int) 0x1 << 29) // (CAN_MB) Identifier Version -// -------- CAN_MID : (CAN_MB Offset: 0x8) CAN Message ID Register -------- -// -------- CAN_MFID : (CAN_MB Offset: 0xc) CAN Message Family ID Register -------- -// -------- CAN_MSR : (CAN_MB Offset: 0x10) CAN Message Status Register -------- -#define AT91C_CAN_MTIMESTAMP ((unsigned int) 0xFFFF << 0) // (CAN_MB) Timer Value -#define AT91C_CAN_MDLC ((unsigned int) 0xF << 16) // (CAN_MB) Mailbox Data Length Code -#define AT91C_CAN_MRTR ((unsigned int) 0x1 << 20) // (CAN_MB) Mailbox Remote Transmission Request -#define AT91C_CAN_MABT ((unsigned int) 0x1 << 22) // (CAN_MB) Mailbox Message Abort -#define AT91C_CAN_MRDY ((unsigned int) 0x1 << 23) // (CAN_MB) Mailbox Ready -#define AT91C_CAN_MMI ((unsigned int) 0x1 << 24) // (CAN_MB) Mailbox Message Ignored -// -------- CAN_MDL : (CAN_MB Offset: 0x14) CAN Message Data Low Register -------- -// -------- CAN_MDH : (CAN_MB Offset: 0x18) CAN Message Data High Register -------- -// -------- CAN_MCR : (CAN_MB Offset: 0x1c) CAN Message Control Register -------- -#define AT91C_CAN_MACR ((unsigned int) 0x1 << 22) // (CAN_MB) Abort Request for Mailbox -#define AT91C_CAN_MTCR ((unsigned int) 0x1 << 23) // (CAN_MB) Mailbox Transfer Command - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Control Area Network Interface -// ***************************************************************************** -typedef struct _AT91S_CAN { - AT91_REG CAN_MR; // Mode Register - AT91_REG CAN_IER; // Interrupt Enable Register - AT91_REG CAN_IDR; // Interrupt Disable Register - AT91_REG CAN_IMR; // Interrupt Mask Register - AT91_REG CAN_SR; // Status Register - AT91_REG CAN_BR; // Baudrate Register - AT91_REG CAN_TIM; // Timer Register - AT91_REG CAN_TIMESTP; // Time Stamp Register - AT91_REG CAN_ECR; // Error Counter Register - AT91_REG CAN_TCR; // Transfer Command Register - AT91_REG CAN_ACR; // Abort Command Register - AT91_REG Reserved0[52]; // - AT91_REG CAN_VR; // Version Register - AT91_REG Reserved1[64]; // - AT91S_CAN_MB CAN_MB0; // CAN Mailbox 0 - AT91S_CAN_MB CAN_MB1; // CAN Mailbox 1 - AT91S_CAN_MB CAN_MB2; // CAN Mailbox 2 - AT91S_CAN_MB CAN_MB3; // CAN Mailbox 3 - AT91S_CAN_MB CAN_MB4; // CAN Mailbox 4 - AT91S_CAN_MB CAN_MB5; // CAN Mailbox 5 - AT91S_CAN_MB CAN_MB6; // CAN Mailbox 6 - AT91S_CAN_MB CAN_MB7; // CAN Mailbox 7 - AT91S_CAN_MB CAN_MB8; // CAN Mailbox 8 - AT91S_CAN_MB CAN_MB9; // CAN Mailbox 9 - AT91S_CAN_MB CAN_MB10; // CAN Mailbox 10 - AT91S_CAN_MB CAN_MB11; // CAN Mailbox 11 - AT91S_CAN_MB CAN_MB12; // CAN Mailbox 12 - AT91S_CAN_MB CAN_MB13; // CAN Mailbox 13 - AT91S_CAN_MB CAN_MB14; // CAN Mailbox 14 - AT91S_CAN_MB CAN_MB15; // CAN Mailbox 15 -} AT91S_CAN, *AT91PS_CAN; - -// -------- CAN_MR : (CAN Offset: 0x0) CAN Mode Register -------- -#define AT91C_CAN_CANEN ((unsigned int) 0x1 << 0) // (CAN) CAN Controller Enable -#define AT91C_CAN_LPM ((unsigned int) 0x1 << 1) // (CAN) Disable/Enable Low Power Mode -#define AT91C_CAN_ABM ((unsigned int) 0x1 << 2) // (CAN) Disable/Enable Autobaud/Listen Mode -#define AT91C_CAN_OVL ((unsigned int) 0x1 << 3) // (CAN) Disable/Enable Overload Frame -#define AT91C_CAN_TEOF ((unsigned int) 0x1 << 4) // (CAN) Time Stamp messages at each end of Frame -#define AT91C_CAN_TTM ((unsigned int) 0x1 << 5) // (CAN) Disable/Enable Time Trigger Mode -#define AT91C_CAN_TIMFRZ ((unsigned int) 0x1 << 6) // (CAN) Enable Timer Freeze -#define AT91C_CAN_DRPT ((unsigned int) 0x1 << 7) // (CAN) Disable Repeat -// -------- CAN_IER : (CAN Offset: 0x4) CAN Interrupt Enable Register -------- -#define AT91C_CAN_MB0 ((unsigned int) 0x1 << 0) // (CAN) Mailbox 0 Flag -#define AT91C_CAN_MB1 ((unsigned int) 0x1 << 1) // (CAN) Mailbox 1 Flag -#define AT91C_CAN_MB2 ((unsigned int) 0x1 << 2) // (CAN) Mailbox 2 Flag -#define AT91C_CAN_MB3 ((unsigned int) 0x1 << 3) // (CAN) Mailbox 3 Flag -#define AT91C_CAN_MB4 ((unsigned int) 0x1 << 4) // (CAN) Mailbox 4 Flag -#define AT91C_CAN_MB5 ((unsigned int) 0x1 << 5) // (CAN) Mailbox 5 Flag -#define AT91C_CAN_MB6 ((unsigned int) 0x1 << 6) // (CAN) Mailbox 6 Flag -#define AT91C_CAN_MB7 ((unsigned int) 0x1 << 7) // (CAN) Mailbox 7 Flag -#define AT91C_CAN_MB8 ((unsigned int) 0x1 << 8) // (CAN) Mailbox 8 Flag -#define AT91C_CAN_MB9 ((unsigned int) 0x1 << 9) // (CAN) Mailbox 9 Flag -#define AT91C_CAN_MB10 ((unsigned int) 0x1 << 10) // (CAN) Mailbox 10 Flag -#define AT91C_CAN_MB11 ((unsigned int) 0x1 << 11) // (CAN) Mailbox 11 Flag -#define AT91C_CAN_MB12 ((unsigned int) 0x1 << 12) // (CAN) Mailbox 12 Flag -#define AT91C_CAN_MB13 ((unsigned int) 0x1 << 13) // (CAN) Mailbox 13 Flag -#define AT91C_CAN_MB14 ((unsigned int) 0x1 << 14) // (CAN) Mailbox 14 Flag -#define AT91C_CAN_MB15 ((unsigned int) 0x1 << 15) // (CAN) Mailbox 15 Flag -#define AT91C_CAN_ERRA ((unsigned int) 0x1 << 16) // (CAN) Error Active Mode Flag -#define AT91C_CAN_WARN ((unsigned int) 0x1 << 17) // (CAN) Warning Limit Flag -#define AT91C_CAN_ERRP ((unsigned int) 0x1 << 18) // (CAN) Error Passive Mode Flag -#define AT91C_CAN_BOFF ((unsigned int) 0x1 << 19) // (CAN) Bus Off Mode Flag -#define AT91C_CAN_SLEEP ((unsigned int) 0x1 << 20) // (CAN) Sleep Flag -#define AT91C_CAN_WAKEUP ((unsigned int) 0x1 << 21) // (CAN) Wakeup Flag -#define AT91C_CAN_TOVF ((unsigned int) 0x1 << 22) // (CAN) Timer Overflow Flag -#define AT91C_CAN_TSTP ((unsigned int) 0x1 << 23) // (CAN) Timestamp Flag -#define AT91C_CAN_CERR ((unsigned int) 0x1 << 24) // (CAN) CRC Error -#define AT91C_CAN_SERR ((unsigned int) 0x1 << 25) // (CAN) Stuffing Error -#define AT91C_CAN_AERR ((unsigned int) 0x1 << 26) // (CAN) Acknowledgment Error -#define AT91C_CAN_FERR ((unsigned int) 0x1 << 27) // (CAN) Form Error -#define AT91C_CAN_BERR ((unsigned int) 0x1 << 28) // (CAN) Bit Error -// -------- CAN_IDR : (CAN Offset: 0x8) CAN Interrupt Disable Register -------- -// -------- CAN_IMR : (CAN Offset: 0xc) CAN Interrupt Mask Register -------- -// -------- CAN_SR : (CAN Offset: 0x10) CAN Status Register -------- -#define AT91C_CAN_RBSY ((unsigned int) 0x1 << 29) // (CAN) Receiver Busy -#define AT91C_CAN_TBSY ((unsigned int) 0x1 << 30) // (CAN) Transmitter Busy -#define AT91C_CAN_OVLY ((unsigned int) 0x1 << 31) // (CAN) Overload Busy -// -------- CAN_BR : (CAN Offset: 0x14) CAN Baudrate Register -------- -#define AT91C_CAN_PHASE2 ((unsigned int) 0x7 << 0) // (CAN) Phase 2 segment -#define AT91C_CAN_PHASE1 ((unsigned int) 0x7 << 4) // (CAN) Phase 1 segment -#define AT91C_CAN_PROPAG ((unsigned int) 0x7 << 8) // (CAN) Programmation time segment -#define AT91C_CAN_SYNC ((unsigned int) 0x3 << 12) // (CAN) Re-synchronization jump width segment -#define AT91C_CAN_BRP ((unsigned int) 0x7F << 16) // (CAN) Baudrate Prescaler -#define AT91C_CAN_SMP ((unsigned int) 0x1 << 24) // (CAN) Sampling mode -// -------- CAN_TIM : (CAN Offset: 0x18) CAN Timer Register -------- -#define AT91C_CAN_TIMER ((unsigned int) 0xFFFF << 0) // (CAN) Timer field -// -------- CAN_TIMESTP : (CAN Offset: 0x1c) CAN Timestamp Register -------- -// -------- CAN_ECR : (CAN Offset: 0x20) CAN Error Counter Register -------- -#define AT91C_CAN_REC ((unsigned int) 0xFF << 0) // (CAN) Receive Error Counter -#define AT91C_CAN_TEC ((unsigned int) 0xFF << 16) // (CAN) Transmit Error Counter -// -------- CAN_TCR : (CAN Offset: 0x24) CAN Transfer Command Register -------- -#define AT91C_CAN_TIMRST ((unsigned int) 0x1 << 31) // (CAN) Timer Reset Field -// -------- CAN_ACR : (CAN Offset: 0x28) CAN Abort Command Register -------- - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Ethernet MAC 10/100 -// ***************************************************************************** -typedef struct _AT91S_EMAC { - AT91_REG EMAC_NCR; // Network Control Register - AT91_REG EMAC_NCFGR; // Network Configuration Register - AT91_REG EMAC_NSR; // Network Status Register - AT91_REG Reserved0[2]; // - AT91_REG EMAC_TSR; // Transmit Status Register - AT91_REG EMAC_RBQP; // Receive Buffer Queue Pointer - AT91_REG EMAC_TBQP; // Transmit Buffer Queue Pointer - AT91_REG EMAC_RSR; // Receive Status Register - AT91_REG EMAC_ISR; // Interrupt Status Register - AT91_REG EMAC_IER; // Interrupt Enable Register - AT91_REG EMAC_IDR; // Interrupt Disable Register - AT91_REG EMAC_IMR; // Interrupt Mask Register - AT91_REG EMAC_MAN; // PHY Maintenance Register - AT91_REG EMAC_PTR; // Pause Time Register - AT91_REG EMAC_PFR; // Pause Frames received Register - AT91_REG EMAC_FTO; // Frames Transmitted OK Register - AT91_REG EMAC_SCF; // Single Collision Frame Register - AT91_REG EMAC_MCF; // Multiple Collision Frame Register - AT91_REG EMAC_FRO; // Frames Received OK Register - AT91_REG EMAC_FCSE; // Frame Check Sequence Error Register - AT91_REG EMAC_ALE; // Alignment Error Register - AT91_REG EMAC_DTF; // Deferred Transmission Frame Register - AT91_REG EMAC_LCOL; // Late Collision Register - AT91_REG EMAC_ECOL; // Excessive Collision Register - AT91_REG EMAC_TUND; // Transmit Underrun Error Register - AT91_REG EMAC_CSE; // Carrier Sense Error Register - AT91_REG EMAC_RRE; // Receive Ressource Error Register - AT91_REG EMAC_ROV; // Receive Overrun Errors Register - AT91_REG EMAC_RSE; // Receive Symbol Errors Register - AT91_REG EMAC_ELE; // Excessive Length Errors Register - AT91_REG EMAC_RJA; // Receive Jabbers Register - AT91_REG EMAC_USF; // Undersize Frames Register - AT91_REG EMAC_STE; // SQE Test Error Register - AT91_REG EMAC_RLE; // Receive Length Field Mismatch Register - AT91_REG EMAC_TPF; // Transmitted Pause Frames Register - AT91_REG EMAC_HRB; // Hash Address Bottom[31:0] - AT91_REG EMAC_HRT; // Hash Address Top[63:32] - AT91_REG EMAC_SA1L; // Specific Address 1 Bottom, First 4 bytes - AT91_REG EMAC_SA1H; // Specific Address 1 Top, Last 2 bytes - AT91_REG EMAC_SA2L; // Specific Address 2 Bottom, First 4 bytes - AT91_REG EMAC_SA2H; // Specific Address 2 Top, Last 2 bytes - AT91_REG EMAC_SA3L; // Specific Address 3 Bottom, First 4 bytes - AT91_REG EMAC_SA3H; // Specific Address 3 Top, Last 2 bytes - AT91_REG EMAC_SA4L; // Specific Address 4 Bottom, First 4 bytes - AT91_REG EMAC_SA4H; // Specific Address 4 Top, Last 2 bytes - AT91_REG EMAC_TID; // Type ID Checking Register - AT91_REG EMAC_TPQ; // Transmit Pause Quantum Register - AT91_REG EMAC_USRIO; // USER Input/Output Register - AT91_REG EMAC_WOL; // Wake On LAN Register - AT91_REG Reserved1[13]; // - AT91_REG EMAC_REV; // Revision Register -} AT91S_EMAC, *AT91PS_EMAC; - -// -------- EMAC_NCR : (EMAC Offset: 0x0) -------- -#define AT91C_EMAC_LB ((unsigned int) 0x1 << 0) // (EMAC) Loopback. Optional. When set, loopback signal is at high level. -#define AT91C_EMAC_LLB ((unsigned int) 0x1 << 1) // (EMAC) Loopback local. -#define AT91C_EMAC_RE ((unsigned int) 0x1 << 2) // (EMAC) Receive enable. -#define AT91C_EMAC_TE ((unsigned int) 0x1 << 3) // (EMAC) Transmit enable. -#define AT91C_EMAC_MPE ((unsigned int) 0x1 << 4) // (EMAC) Management port enable. -#define AT91C_EMAC_CLRSTAT ((unsigned int) 0x1 << 5) // (EMAC) Clear statistics registers. -#define AT91C_EMAC_INCSTAT ((unsigned int) 0x1 << 6) // (EMAC) Increment statistics registers. -#define AT91C_EMAC_WESTAT ((unsigned int) 0x1 << 7) // (EMAC) Write enable for statistics registers. -#define AT91C_EMAC_BP ((unsigned int) 0x1 << 8) // (EMAC) Back pressure. -#define AT91C_EMAC_TSTART ((unsigned int) 0x1 << 9) // (EMAC) Start Transmission. -#define AT91C_EMAC_THALT ((unsigned int) 0x1 << 10) // (EMAC) Transmission Halt. -#define AT91C_EMAC_TPFR ((unsigned int) 0x1 << 11) // (EMAC) Transmit pause frame -#define AT91C_EMAC_TZQ ((unsigned int) 0x1 << 12) // (EMAC) Transmit zero quantum pause frame -// -------- EMAC_NCFGR : (EMAC Offset: 0x4) Network Configuration Register -------- -#define AT91C_EMAC_SPD ((unsigned int) 0x1 << 0) // (EMAC) Speed. -#define AT91C_EMAC_FD ((unsigned int) 0x1 << 1) // (EMAC) Full duplex. -#define AT91C_EMAC_JFRAME ((unsigned int) 0x1 << 3) // (EMAC) Jumbo Frames. -#define AT91C_EMAC_CAF ((unsigned int) 0x1 << 4) // (EMAC) Copy all frames. -#define AT91C_EMAC_NBC ((unsigned int) 0x1 << 5) // (EMAC) No broadcast. -#define AT91C_EMAC_MTI ((unsigned int) 0x1 << 6) // (EMAC) Multicast hash event enable -#define AT91C_EMAC_UNI ((unsigned int) 0x1 << 7) // (EMAC) Unicast hash enable. -#define AT91C_EMAC_BIG ((unsigned int) 0x1 << 8) // (EMAC) Receive 1522 bytes. -#define AT91C_EMAC_EAE ((unsigned int) 0x1 << 9) // (EMAC) External address match enable. -#define AT91C_EMAC_CLK ((unsigned int) 0x3 << 10) // (EMAC) -#define AT91C_EMAC_CLK_HCLK_8 ((unsigned int) 0x0 << 10) // (EMAC) HCLK divided by 8 -#define AT91C_EMAC_CLK_HCLK_16 ((unsigned int) 0x1 << 10) // (EMAC) HCLK divided by 16 -#define AT91C_EMAC_CLK_HCLK_32 ((unsigned int) 0x2 << 10) // (EMAC) HCLK divided by 32 -#define AT91C_EMAC_CLK_HCLK_64 ((unsigned int) 0x3 << 10) // (EMAC) HCLK divided by 64 -#define AT91C_EMAC_RTY ((unsigned int) 0x1 << 12) // (EMAC) -#define AT91C_EMAC_PAE ((unsigned int) 0x1 << 13) // (EMAC) -#define AT91C_EMAC_RBOF ((unsigned int) 0x3 << 14) // (EMAC) -#define AT91C_EMAC_RBOF_OFFSET_0 ((unsigned int) 0x0 << 14) // (EMAC) no offset from start of receive buffer -#define AT91C_EMAC_RBOF_OFFSET_1 ((unsigned int) 0x1 << 14) // (EMAC) one byte offset from start of receive buffer -#define AT91C_EMAC_RBOF_OFFSET_2 ((unsigned int) 0x2 << 14) // (EMAC) two bytes offset from start of receive buffer -#define AT91C_EMAC_RBOF_OFFSET_3 ((unsigned int) 0x3 << 14) // (EMAC) three bytes offset from start of receive buffer -#define AT91C_EMAC_RLCE ((unsigned int) 0x1 << 16) // (EMAC) Receive Length field Checking Enable -#define AT91C_EMAC_DRFCS ((unsigned int) 0x1 << 17) // (EMAC) Discard Receive FCS -#define AT91C_EMAC_EFRHD ((unsigned int) 0x1 << 18) // (EMAC) -#define AT91C_EMAC_IRXFCS ((unsigned int) 0x1 << 19) // (EMAC) Ignore RX FCS -// -------- EMAC_NSR : (EMAC Offset: 0x8) Network Status Register -------- -#define AT91C_EMAC_LINKR ((unsigned int) 0x1 << 0) // (EMAC) -#define AT91C_EMAC_MDIO ((unsigned int) 0x1 << 1) // (EMAC) -#define AT91C_EMAC_IDLE ((unsigned int) 0x1 << 2) // (EMAC) -// -------- EMAC_TSR : (EMAC Offset: 0x14) Transmit Status Register -------- -#define AT91C_EMAC_UBR ((unsigned int) 0x1 << 0) // (EMAC) -#define AT91C_EMAC_COL ((unsigned int) 0x1 << 1) // (EMAC) -#define AT91C_EMAC_RLES ((unsigned int) 0x1 << 2) // (EMAC) -#define AT91C_EMAC_TGO ((unsigned int) 0x1 << 3) // (EMAC) Transmit Go -#define AT91C_EMAC_BEX ((unsigned int) 0x1 << 4) // (EMAC) Buffers exhausted mid frame -#define AT91C_EMAC_COMP ((unsigned int) 0x1 << 5) // (EMAC) -#define AT91C_EMAC_UND ((unsigned int) 0x1 << 6) // (EMAC) -// -------- EMAC_RSR : (EMAC Offset: 0x20) Receive Status Register -------- -#define AT91C_EMAC_BNA ((unsigned int) 0x1 << 0) // (EMAC) -#define AT91C_EMAC_REC ((unsigned int) 0x1 << 1) // (EMAC) -#define AT91C_EMAC_OVR ((unsigned int) 0x1 << 2) // (EMAC) -// -------- EMAC_ISR : (EMAC Offset: 0x24) Interrupt Status Register -------- -#define AT91C_EMAC_MFD ((unsigned int) 0x1 << 0) // (EMAC) -#define AT91C_EMAC_RCOMP ((unsigned int) 0x1 << 1) // (EMAC) -#define AT91C_EMAC_RXUBR ((unsigned int) 0x1 << 2) // (EMAC) -#define AT91C_EMAC_TXUBR ((unsigned int) 0x1 << 3) // (EMAC) -#define AT91C_EMAC_TUNDR ((unsigned int) 0x1 << 4) // (EMAC) -#define AT91C_EMAC_RLEX ((unsigned int) 0x1 << 5) // (EMAC) -#define AT91C_EMAC_TXERR ((unsigned int) 0x1 << 6) // (EMAC) -#define AT91C_EMAC_TCOMP ((unsigned int) 0x1 << 7) // (EMAC) -#define AT91C_EMAC_LINK ((unsigned int) 0x1 << 9) // (EMAC) -#define AT91C_EMAC_ROVR ((unsigned int) 0x1 << 10) // (EMAC) -#define AT91C_EMAC_HRESP ((unsigned int) 0x1 << 11) // (EMAC) -#define AT91C_EMAC_PFRE ((unsigned int) 0x1 << 12) // (EMAC) -#define AT91C_EMAC_PTZ ((unsigned int) 0x1 << 13) // (EMAC) -// -------- EMAC_IER : (EMAC Offset: 0x28) Interrupt Enable Register -------- -// -------- EMAC_IDR : (EMAC Offset: 0x2c) Interrupt Disable Register -------- -// -------- EMAC_IMR : (EMAC Offset: 0x30) Interrupt Mask Register -------- -// -------- EMAC_MAN : (EMAC Offset: 0x34) PHY Maintenance Register -------- -#define AT91C_EMAC_DATA ((unsigned int) 0xFFFF << 0) // (EMAC) -#define AT91C_EMAC_CODE ((unsigned int) 0x3 << 16) // (EMAC) -#define AT91C_EMAC_REGA ((unsigned int) 0x1F << 18) // (EMAC) -#define AT91C_EMAC_PHYA ((unsigned int) 0x1F << 23) // (EMAC) -#define AT91C_EMAC_RW ((unsigned int) 0x3 << 28) // (EMAC) -#define AT91C_EMAC_SOF ((unsigned int) 0x3 << 30) // (EMAC) -// -------- EMAC_USRIO : (EMAC Offset: 0xc0) USER Input Output Register -------- -#define AT91C_EMAC_RMII ((unsigned int) 0x1 << 0) // (EMAC) Reduce MII -// -------- EMAC_WOL : (EMAC Offset: 0xc4) Wake On LAN Register -------- -#define AT91C_EMAC_IP ((unsigned int) 0xFFFF << 0) // (EMAC) ARP request IP address -#define AT91C_EMAC_MAG ((unsigned int) 0x1 << 16) // (EMAC) Magic packet event enable -#define AT91C_EMAC_ARP ((unsigned int) 0x1 << 17) // (EMAC) ARP request event enable -#define AT91C_EMAC_SA1 ((unsigned int) 0x1 << 18) // (EMAC) Specific address register 1 event enable -// -------- EMAC_REV : (EMAC Offset: 0xfc) Revision Register -------- -#define AT91C_EMAC_REVREF ((unsigned int) 0xFFFF << 0) // (EMAC) -#define AT91C_EMAC_PARTREF ((unsigned int) 0xFFFF << 16) // (EMAC) - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Analog to Digital Convertor -// ***************************************************************************** -typedef struct _AT91S_ADC { - AT91_REG ADC_CR; // ADC Control Register - AT91_REG ADC_MR; // ADC Mode Register - AT91_REG Reserved0[2]; // - AT91_REG ADC_CHER; // ADC Channel Enable Register - AT91_REG ADC_CHDR; // ADC Channel Disable Register - AT91_REG ADC_CHSR; // ADC Channel Status Register - AT91_REG ADC_SR; // ADC Status Register - AT91_REG ADC_LCDR; // ADC Last Converted Data Register - AT91_REG ADC_IER; // ADC Interrupt Enable Register - AT91_REG ADC_IDR; // ADC Interrupt Disable Register - AT91_REG ADC_IMR; // ADC Interrupt Mask Register - AT91_REG ADC_CDR0; // ADC Channel Data Register 0 - AT91_REG ADC_CDR1; // ADC Channel Data Register 1 - AT91_REG ADC_CDR2; // ADC Channel Data Register 2 - AT91_REG ADC_CDR3; // ADC Channel Data Register 3 - AT91_REG ADC_CDR4; // ADC Channel Data Register 4 - AT91_REG ADC_CDR5; // ADC Channel Data Register 5 - AT91_REG ADC_CDR6; // ADC Channel Data Register 6 - AT91_REG ADC_CDR7; // ADC Channel Data Register 7 - AT91_REG Reserved1[44]; // - AT91_REG ADC_RPR; // Receive Pointer Register - AT91_REG ADC_RCR; // Receive Counter Register - AT91_REG ADC_TPR; // Transmit Pointer Register - AT91_REG ADC_TCR; // Transmit Counter Register - AT91_REG ADC_RNPR; // Receive Next Pointer Register - AT91_REG ADC_RNCR; // Receive Next Counter Register - AT91_REG ADC_TNPR; // Transmit Next Pointer Register - AT91_REG ADC_TNCR; // Transmit Next Counter Register - AT91_REG ADC_PTCR; // PDC Transfer Control Register - AT91_REG ADC_PTSR; // PDC Transfer Status Register -} AT91S_ADC, *AT91PS_ADC; - -// -------- ADC_CR : (ADC Offset: 0x0) ADC Control Register -------- -#define AT91C_ADC_SWRST ((unsigned int) 0x1 << 0) // (ADC) Software Reset -#define AT91C_ADC_START ((unsigned int) 0x1 << 1) // (ADC) Start Conversion -// -------- ADC_MR : (ADC Offset: 0x4) ADC Mode Register -------- -#define AT91C_ADC_TRGEN ((unsigned int) 0x1 << 0) // (ADC) Trigger Enable -#define AT91C_ADC_TRGEN_DIS ((unsigned int) 0x0) // (ADC) Hradware triggers are disabled. Starting a conversion is only possible by software -#define AT91C_ADC_TRGEN_EN ((unsigned int) 0x1) // (ADC) Hardware trigger selected by TRGSEL field is enabled. -#define AT91C_ADC_TRGSEL ((unsigned int) 0x7 << 1) // (ADC) Trigger Selection -#define AT91C_ADC_TRGSEL_TIOA0 ((unsigned int) 0x0 << 1) // (ADC) Selected TRGSEL = TIAO0 -#define AT91C_ADC_TRGSEL_TIOA1 ((unsigned int) 0x1 << 1) // (ADC) Selected TRGSEL = TIAO1 -#define AT91C_ADC_TRGSEL_TIOA2 ((unsigned int) 0x2 << 1) // (ADC) Selected TRGSEL = TIAO2 -#define AT91C_ADC_TRGSEL_TIOA3 ((unsigned int) 0x3 << 1) // (ADC) Selected TRGSEL = TIAO3 -#define AT91C_ADC_TRGSEL_TIOA4 ((unsigned int) 0x4 << 1) // (ADC) Selected TRGSEL = TIAO4 -#define AT91C_ADC_TRGSEL_TIOA5 ((unsigned int) 0x5 << 1) // (ADC) Selected TRGSEL = TIAO5 -#define AT91C_ADC_TRGSEL_EXT ((unsigned int) 0x6 << 1) // (ADC) Selected TRGSEL = External Trigger -#define AT91C_ADC_LOWRES ((unsigned int) 0x1 << 4) // (ADC) Resolution. -#define AT91C_ADC_LOWRES_10_BIT ((unsigned int) 0x0 << 4) // (ADC) 10-bit resolution -#define AT91C_ADC_LOWRES_8_BIT ((unsigned int) 0x1 << 4) // (ADC) 8-bit resolution -#define AT91C_ADC_SLEEP ((unsigned int) 0x1 << 5) // (ADC) Sleep Mode -#define AT91C_ADC_SLEEP_NORMAL_MODE ((unsigned int) 0x0 << 5) // (ADC) Normal Mode -#define AT91C_ADC_SLEEP_MODE ((unsigned int) 0x1 << 5) // (ADC) Sleep Mode -#define AT91C_ADC_PRESCAL ((unsigned int) 0x3F << 8) // (ADC) Prescaler rate selection -#define AT91C_ADC_STARTUP ((unsigned int) 0x1F << 16) // (ADC) Startup Time -#define AT91C_ADC_SHTIM ((unsigned int) 0xF << 24) // (ADC) Sample & Hold Time -// -------- ADC_CHER : (ADC Offset: 0x10) ADC Channel Enable Register -------- -#define AT91C_ADC_CH0 ((unsigned int) 0x1 << 0) // (ADC) Channel 0 -#define AT91C_ADC_CH1 ((unsigned int) 0x1 << 1) // (ADC) Channel 1 -#define AT91C_ADC_CH2 ((unsigned int) 0x1 << 2) // (ADC) Channel 2 -#define AT91C_ADC_CH3 ((unsigned int) 0x1 << 3) // (ADC) Channel 3 -#define AT91C_ADC_CH4 ((unsigned int) 0x1 << 4) // (ADC) Channel 4 -#define AT91C_ADC_CH5 ((unsigned int) 0x1 << 5) // (ADC) Channel 5 -#define AT91C_ADC_CH6 ((unsigned int) 0x1 << 6) // (ADC) Channel 6 -#define AT91C_ADC_CH7 ((unsigned int) 0x1 << 7) // (ADC) Channel 7 -// -------- ADC_CHDR : (ADC Offset: 0x14) ADC Channel Disable Register -------- -// -------- ADC_CHSR : (ADC Offset: 0x18) ADC Channel Status Register -------- -// -------- ADC_SR : (ADC Offset: 0x1c) ADC Status Register -------- -#define AT91C_ADC_EOC0 ((unsigned int) 0x1 << 0) // (ADC) End of Conversion -#define AT91C_ADC_EOC1 ((unsigned int) 0x1 << 1) // (ADC) End of Conversion -#define AT91C_ADC_EOC2 ((unsigned int) 0x1 << 2) // (ADC) End of Conversion -#define AT91C_ADC_EOC3 ((unsigned int) 0x1 << 3) // (ADC) End of Conversion -#define AT91C_ADC_EOC4 ((unsigned int) 0x1 << 4) // (ADC) End of Conversion -#define AT91C_ADC_EOC5 ((unsigned int) 0x1 << 5) // (ADC) End of Conversion -#define AT91C_ADC_EOC6 ((unsigned int) 0x1 << 6) // (ADC) End of Conversion -#define AT91C_ADC_EOC7 ((unsigned int) 0x1 << 7) // (ADC) End of Conversion -#define AT91C_ADC_OVRE0 ((unsigned int) 0x1 << 8) // (ADC) Overrun Error -#define AT91C_ADC_OVRE1 ((unsigned int) 0x1 << 9) // (ADC) Overrun Error -#define AT91C_ADC_OVRE2 ((unsigned int) 0x1 << 10) // (ADC) Overrun Error -#define AT91C_ADC_OVRE3 ((unsigned int) 0x1 << 11) // (ADC) Overrun Error -#define AT91C_ADC_OVRE4 ((unsigned int) 0x1 << 12) // (ADC) Overrun Error -#define AT91C_ADC_OVRE5 ((unsigned int) 0x1 << 13) // (ADC) Overrun Error -#define AT91C_ADC_OVRE6 ((unsigned int) 0x1 << 14) // (ADC) Overrun Error -#define AT91C_ADC_OVRE7 ((unsigned int) 0x1 << 15) // (ADC) Overrun Error -#define AT91C_ADC_DRDY ((unsigned int) 0x1 << 16) // (ADC) Data Ready -#define AT91C_ADC_GOVRE ((unsigned int) 0x1 << 17) // (ADC) General Overrun -#define AT91C_ADC_ENDRX ((unsigned int) 0x1 << 18) // (ADC) End of Receiver Transfer -#define AT91C_ADC_RXBUFF ((unsigned int) 0x1 << 19) // (ADC) RXBUFF Interrupt -// -------- ADC_LCDR : (ADC Offset: 0x20) ADC Last Converted Data Register -------- -#define AT91C_ADC_LDATA ((unsigned int) 0x3FF << 0) // (ADC) Last Data Converted -// -------- ADC_IER : (ADC Offset: 0x24) ADC Interrupt Enable Register -------- -// -------- ADC_IDR : (ADC Offset: 0x28) ADC Interrupt Disable Register -------- -// -------- ADC_IMR : (ADC Offset: 0x2c) ADC Interrupt Mask Register -------- -// -------- ADC_CDR0 : (ADC Offset: 0x30) ADC Channel Data Register 0 -------- -#define AT91C_ADC_DATA ((unsigned int) 0x3FF << 0) // (ADC) Converted Data -// -------- ADC_CDR1 : (ADC Offset: 0x34) ADC Channel Data Register 1 -------- -// -------- ADC_CDR2 : (ADC Offset: 0x38) ADC Channel Data Register 2 -------- -// -------- ADC_CDR3 : (ADC Offset: 0x3c) ADC Channel Data Register 3 -------- -// -------- ADC_CDR4 : (ADC Offset: 0x40) ADC Channel Data Register 4 -------- -// -------- ADC_CDR5 : (ADC Offset: 0x44) ADC Channel Data Register 5 -------- -// -------- ADC_CDR6 : (ADC Offset: 0x48) ADC Channel Data Register 6 -------- -// -------- ADC_CDR7 : (ADC Offset: 0x4c) ADC Channel Data Register 7 -------- - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Advanced Encryption Standard -// ***************************************************************************** -typedef struct _AT91S_AES { - AT91_REG AES_CR; // Control Register - AT91_REG AES_MR; // Mode Register - AT91_REG Reserved0[2]; // - AT91_REG AES_IER; // Interrupt Enable Register - AT91_REG AES_IDR; // Interrupt Disable Register - AT91_REG AES_IMR; // Interrupt Mask Register - AT91_REG AES_ISR; // Interrupt Status Register - AT91_REG AES_KEYWxR[4]; // Key Word x Register - AT91_REG Reserved1[4]; // - AT91_REG AES_IDATAxR[4]; // Input Data x Register - AT91_REG AES_ODATAxR[4]; // Output Data x Register - AT91_REG AES_IVxR[4]; // Initialization Vector x Register - AT91_REG Reserved2[35]; // - AT91_REG AES_VR; // AES Version Register - AT91_REG AES_RPR; // Receive Pointer Register - AT91_REG AES_RCR; // Receive Counter Register - AT91_REG AES_TPR; // Transmit Pointer Register - AT91_REG AES_TCR; // Transmit Counter Register - AT91_REG AES_RNPR; // Receive Next Pointer Register - AT91_REG AES_RNCR; // Receive Next Counter Register - AT91_REG AES_TNPR; // Transmit Next Pointer Register - AT91_REG AES_TNCR; // Transmit Next Counter Register - AT91_REG AES_PTCR; // PDC Transfer Control Register - AT91_REG AES_PTSR; // PDC Transfer Status Register -} AT91S_AES, *AT91PS_AES; - -// -------- AES_CR : (AES Offset: 0x0) Control Register -------- -#define AT91C_AES_START ((unsigned int) 0x1 << 0) // (AES) Starts Processing -#define AT91C_AES_SWRST ((unsigned int) 0x1 << 8) // (AES) Software Reset -#define AT91C_AES_LOADSEED ((unsigned int) 0x1 << 16) // (AES) Random Number Generator Seed Loading -// -------- AES_MR : (AES Offset: 0x4) Mode Register -------- -#define AT91C_AES_CIPHER ((unsigned int) 0x1 << 0) // (AES) Processing Mode -#define AT91C_AES_PROCDLY ((unsigned int) 0xF << 4) // (AES) Processing Delay -#define AT91C_AES_SMOD ((unsigned int) 0x3 << 8) // (AES) Start Mode -#define AT91C_AES_SMOD_MANUAL ((unsigned int) 0x0 << 8) // (AES) Manual Mode: The START bit in register AES_CR must be set to begin encryption or decryption. -#define AT91C_AES_SMOD_AUTO ((unsigned int) 0x1 << 8) // (AES) Auto Mode: no action in AES_CR is necessary (cf datasheet). -#define AT91C_AES_SMOD_PDC ((unsigned int) 0x2 << 8) // (AES) PDC Mode (cf datasheet). -#define AT91C_AES_OPMOD ((unsigned int) 0x7 << 12) // (AES) Operation Mode -#define AT91C_AES_OPMOD_ECB ((unsigned int) 0x0 << 12) // (AES) ECB Electronic CodeBook mode. -#define AT91C_AES_OPMOD_CBC ((unsigned int) 0x1 << 12) // (AES) CBC Cipher Block Chaining mode. -#define AT91C_AES_OPMOD_OFB ((unsigned int) 0x2 << 12) // (AES) OFB Output Feedback mode. -#define AT91C_AES_OPMOD_CFB ((unsigned int) 0x3 << 12) // (AES) CFB Cipher Feedback mode. -#define AT91C_AES_OPMOD_CTR ((unsigned int) 0x4 << 12) // (AES) CTR Counter mode. -#define AT91C_AES_LOD ((unsigned int) 0x1 << 15) // (AES) Last Output Data Mode -#define AT91C_AES_CFBS ((unsigned int) 0x7 << 16) // (AES) Cipher Feedback Data Size -#define AT91C_AES_CFBS_128_BIT ((unsigned int) 0x0 << 16) // (AES) 128-bit. -#define AT91C_AES_CFBS_64_BIT ((unsigned int) 0x1 << 16) // (AES) 64-bit. -#define AT91C_AES_CFBS_32_BIT ((unsigned int) 0x2 << 16) // (AES) 32-bit. -#define AT91C_AES_CFBS_16_BIT ((unsigned int) 0x3 << 16) // (AES) 16-bit. -#define AT91C_AES_CFBS_8_BIT ((unsigned int) 0x4 << 16) // (AES) 8-bit. -#define AT91C_AES_CKEY ((unsigned int) 0xF << 20) // (AES) Countermeasure Key -#define AT91C_AES_CTYPE ((unsigned int) 0x1F << 24) // (AES) Countermeasure Type -#define AT91C_AES_CTYPE_TYPE1_EN ((unsigned int) 0x1 << 24) // (AES) Countermeasure type 1 is enabled. -#define AT91C_AES_CTYPE_TYPE2_EN ((unsigned int) 0x2 << 24) // (AES) Countermeasure type 2 is enabled. -#define AT91C_AES_CTYPE_TYPE3_EN ((unsigned int) 0x4 << 24) // (AES) Countermeasure type 3 is enabled. -#define AT91C_AES_CTYPE_TYPE4_EN ((unsigned int) 0x8 << 24) // (AES) Countermeasure type 4 is enabled. -#define AT91C_AES_CTYPE_TYPE5_EN ((unsigned int) 0x10 << 24) // (AES) Countermeasure type 5 is enabled. -// -------- AES_IER : (AES Offset: 0x10) Interrupt Enable Register -------- -#define AT91C_AES_DATRDY ((unsigned int) 0x1 << 0) // (AES) DATRDY -#define AT91C_AES_ENDRX ((unsigned int) 0x1 << 1) // (AES) PDC Read Buffer End -#define AT91C_AES_ENDTX ((unsigned int) 0x1 << 2) // (AES) PDC Write Buffer End -#define AT91C_AES_RXBUFF ((unsigned int) 0x1 << 3) // (AES) PDC Read Buffer Full -#define AT91C_AES_TXBUFE ((unsigned int) 0x1 << 4) // (AES) PDC Write Buffer Empty -#define AT91C_AES_URAD ((unsigned int) 0x1 << 8) // (AES) Unspecified Register Access Detection -// -------- AES_IDR : (AES Offset: 0x14) Interrupt Disable Register -------- -// -------- AES_IMR : (AES Offset: 0x18) Interrupt Mask Register -------- -// -------- AES_ISR : (AES Offset: 0x1c) Interrupt Status Register -------- -#define AT91C_AES_URAT ((unsigned int) 0x7 << 12) // (AES) Unspecified Register Access Type Status -#define AT91C_AES_URAT_IN_DAT_WRITE_DATPROC ((unsigned int) 0x0 << 12) // (AES) Input data register written during the data processing in PDC mode. -#define AT91C_AES_URAT_OUT_DAT_READ_DATPROC ((unsigned int) 0x1 << 12) // (AES) Output data register read during the data processing. -#define AT91C_AES_URAT_MODEREG_WRITE_DATPROC ((unsigned int) 0x2 << 12) // (AES) Mode register written during the data processing. -#define AT91C_AES_URAT_OUT_DAT_READ_SUBKEY ((unsigned int) 0x3 << 12) // (AES) Output data register read during the sub-keys generation. -#define AT91C_AES_URAT_MODEREG_WRITE_SUBKEY ((unsigned int) 0x4 << 12) // (AES) Mode register written during the sub-keys generation. -#define AT91C_AES_URAT_WO_REG_READ ((unsigned int) 0x5 << 12) // (AES) Write-only register read access. - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Triple Data Encryption Standard -// ***************************************************************************** -typedef struct _AT91S_TDES { - AT91_REG TDES_CR; // Control Register - AT91_REG TDES_MR; // Mode Register - AT91_REG Reserved0[2]; // - AT91_REG TDES_IER; // Interrupt Enable Register - AT91_REG TDES_IDR; // Interrupt Disable Register - AT91_REG TDES_IMR; // Interrupt Mask Register - AT91_REG TDES_ISR; // Interrupt Status Register - AT91_REG TDES_KEY1WxR[2]; // Key 1 Word x Register - AT91_REG TDES_KEY2WxR[2]; // Key 2 Word x Register - AT91_REG TDES_KEY3WxR[2]; // Key 3 Word x Register - AT91_REG Reserved1[2]; // - AT91_REG TDES_IDATAxR[2]; // Input Data x Register - AT91_REG Reserved2[2]; // - AT91_REG TDES_ODATAxR[2]; // Output Data x Register - AT91_REG Reserved3[2]; // - AT91_REG TDES_IVxR[2]; // Initialization Vector x Register - AT91_REG Reserved4[37]; // - AT91_REG TDES_VR; // TDES Version Register - AT91_REG TDES_RPR; // Receive Pointer Register - AT91_REG TDES_RCR; // Receive Counter Register - AT91_REG TDES_TPR; // Transmit Pointer Register - AT91_REG TDES_TCR; // Transmit Counter Register - AT91_REG TDES_RNPR; // Receive Next Pointer Register - AT91_REG TDES_RNCR; // Receive Next Counter Register - AT91_REG TDES_TNPR; // Transmit Next Pointer Register - AT91_REG TDES_TNCR; // Transmit Next Counter Register - AT91_REG TDES_PTCR; // PDC Transfer Control Register - AT91_REG TDES_PTSR; // PDC Transfer Status Register -} AT91S_TDES, *AT91PS_TDES; - -// -------- TDES_CR : (TDES Offset: 0x0) Control Register -------- -#define AT91C_TDES_START ((unsigned int) 0x1 << 0) // (TDES) Starts Processing -#define AT91C_TDES_SWRST ((unsigned int) 0x1 << 8) // (TDES) Software Reset -// -------- TDES_MR : (TDES Offset: 0x4) Mode Register -------- -#define AT91C_TDES_CIPHER ((unsigned int) 0x1 << 0) // (TDES) Processing Mode -#define AT91C_TDES_TDESMOD ((unsigned int) 0x1 << 1) // (TDES) Single or Triple DES Mode -#define AT91C_TDES_KEYMOD ((unsigned int) 0x1 << 4) // (TDES) Key Mode -#define AT91C_TDES_SMOD ((unsigned int) 0x3 << 8) // (TDES) Start Mode -#define AT91C_TDES_SMOD_MANUAL ((unsigned int) 0x0 << 8) // (TDES) Manual Mode: The START bit in register TDES_CR must be set to begin encryption or decryption. -#define AT91C_TDES_SMOD_AUTO ((unsigned int) 0x1 << 8) // (TDES) Auto Mode: no action in TDES_CR is necessary (cf datasheet). -#define AT91C_TDES_SMOD_PDC ((unsigned int) 0x2 << 8) // (TDES) PDC Mode (cf datasheet). -#define AT91C_TDES_OPMOD ((unsigned int) 0x3 << 12) // (TDES) Operation Mode -#define AT91C_TDES_OPMOD_ECB ((unsigned int) 0x0 << 12) // (TDES) ECB Electronic CodeBook mode. -#define AT91C_TDES_OPMOD_CBC ((unsigned int) 0x1 << 12) // (TDES) CBC Cipher Block Chaining mode. -#define AT91C_TDES_OPMOD_OFB ((unsigned int) 0x2 << 12) // (TDES) OFB Output Feedback mode. -#define AT91C_TDES_OPMOD_CFB ((unsigned int) 0x3 << 12) // (TDES) CFB Cipher Feedback mode. -#define AT91C_TDES_LOD ((unsigned int) 0x1 << 15) // (TDES) Last Output Data Mode -#define AT91C_TDES_CFBS ((unsigned int) 0x3 << 16) // (TDES) Cipher Feedback Data Size -#define AT91C_TDES_CFBS_64_BIT ((unsigned int) 0x0 << 16) // (TDES) 64-bit. -#define AT91C_TDES_CFBS_32_BIT ((unsigned int) 0x1 << 16) // (TDES) 32-bit. -#define AT91C_TDES_CFBS_16_BIT ((unsigned int) 0x2 << 16) // (TDES) 16-bit. -#define AT91C_TDES_CFBS_8_BIT ((unsigned int) 0x3 << 16) // (TDES) 8-bit. -// -------- TDES_IER : (TDES Offset: 0x10) Interrupt Enable Register -------- -#define AT91C_TDES_DATRDY ((unsigned int) 0x1 << 0) // (TDES) DATRDY -#define AT91C_TDES_ENDRX ((unsigned int) 0x1 << 1) // (TDES) PDC Read Buffer End -#define AT91C_TDES_ENDTX ((unsigned int) 0x1 << 2) // (TDES) PDC Write Buffer End -#define AT91C_TDES_RXBUFF ((unsigned int) 0x1 << 3) // (TDES) PDC Read Buffer Full -#define AT91C_TDES_TXBUFE ((unsigned int) 0x1 << 4) // (TDES) PDC Write Buffer Empty -#define AT91C_TDES_URAD ((unsigned int) 0x1 << 8) // (TDES) Unspecified Register Access Detection -// -------- TDES_IDR : (TDES Offset: 0x14) Interrupt Disable Register -------- -// -------- TDES_IMR : (TDES Offset: 0x18) Interrupt Mask Register -------- -// -------- TDES_ISR : (TDES Offset: 0x1c) Interrupt Status Register -------- -#define AT91C_TDES_URAT ((unsigned int) 0x3 << 12) // (TDES) Unspecified Register Access Type Status -#define AT91C_TDES_URAT_IN_DAT_WRITE_DATPROC ((unsigned int) 0x0 << 12) // (TDES) Input data register written during the data processing in PDC mode. -#define AT91C_TDES_URAT_OUT_DAT_READ_DATPROC ((unsigned int) 0x1 << 12) // (TDES) Output data register read during the data processing. -#define AT91C_TDES_URAT_MODEREG_WRITE_DATPROC ((unsigned int) 0x2 << 12) // (TDES) Mode register written during the data processing. -#define AT91C_TDES_URAT_WO_REG_READ ((unsigned int) 0x3 << 12) // (TDES) Write-only register read access. - -// ***************************************************************************** -// REGISTER ADDRESS DEFINITION FOR AT91SAM7X256 -// ***************************************************************************** -// ========== Register definition for SYS peripheral ========== -// ========== Register definition for AIC peripheral ========== -#define AT91C_AIC_IVR ((AT91_REG *) 0xFFFFF100) // (AIC) IRQ Vector Register -#define AT91C_AIC_SMR ((AT91_REG *) 0xFFFFF000) // (AIC) Source Mode Register -#define AT91C_AIC_FVR ((AT91_REG *) 0xFFFFF104) // (AIC) FIQ Vector Register -#define AT91C_AIC_DCR ((AT91_REG *) 0xFFFFF138) // (AIC) Debug Control Register (Protect) -#define AT91C_AIC_EOICR ((AT91_REG *) 0xFFFFF130) // (AIC) End of Interrupt Command Register -#define AT91C_AIC_SVR ((AT91_REG *) 0xFFFFF080) // (AIC) Source Vector Register -#define AT91C_AIC_FFSR ((AT91_REG *) 0xFFFFF148) // (AIC) Fast Forcing Status Register -#define AT91C_AIC_ICCR ((AT91_REG *) 0xFFFFF128) // (AIC) Interrupt Clear Command Register -#define AT91C_AIC_ISR ((AT91_REG *) 0xFFFFF108) // (AIC) Interrupt Status Register -#define AT91C_AIC_IMR ((AT91_REG *) 0xFFFFF110) // (AIC) Interrupt Mask Register -#define AT91C_AIC_IPR ((AT91_REG *) 0xFFFFF10C) // (AIC) Interrupt Pending Register -#define AT91C_AIC_FFER ((AT91_REG *) 0xFFFFF140) // (AIC) Fast Forcing Enable Register -#define AT91C_AIC_IECR ((AT91_REG *) 0xFFFFF120) // (AIC) Interrupt Enable Command Register -#define AT91C_AIC_ISCR ((AT91_REG *) 0xFFFFF12C) // (AIC) Interrupt Set Command Register -#define AT91C_AIC_FFDR ((AT91_REG *) 0xFFFFF144) // (AIC) Fast Forcing Disable Register -#define AT91C_AIC_CISR ((AT91_REG *) 0xFFFFF114) // (AIC) Core Interrupt Status Register -#define AT91C_AIC_IDCR ((AT91_REG *) 0xFFFFF124) // (AIC) Interrupt Disable Command Register -#define AT91C_AIC_SPU ((AT91_REG *) 0xFFFFF134) // (AIC) Spurious Vector Register -// ========== Register definition for PDC_DBGU peripheral ========== -#define AT91C_DBGU_TCR ((AT91_REG *) 0xFFFFF30C) // (PDC_DBGU) Transmit Counter Register -#define AT91C_DBGU_RNPR ((AT91_REG *) 0xFFFFF310) // (PDC_DBGU) Receive Next Pointer Register -#define AT91C_DBGU_TNPR ((AT91_REG *) 0xFFFFF318) // (PDC_DBGU) Transmit Next Pointer Register -#define AT91C_DBGU_TPR ((AT91_REG *) 0xFFFFF308) // (PDC_DBGU) Transmit Pointer Register -#define AT91C_DBGU_RPR ((AT91_REG *) 0xFFFFF300) // (PDC_DBGU) Receive Pointer Register -#define AT91C_DBGU_RCR ((AT91_REG *) 0xFFFFF304) // (PDC_DBGU) Receive Counter Register -#define AT91C_DBGU_RNCR ((AT91_REG *) 0xFFFFF314) // (PDC_DBGU) Receive Next Counter Register -#define AT91C_DBGU_PTCR ((AT91_REG *) 0xFFFFF320) // (PDC_DBGU) PDC Transfer Control Register -#define AT91C_DBGU_PTSR ((AT91_REG *) 0xFFFFF324) // (PDC_DBGU) PDC Transfer Status Register -#define AT91C_DBGU_TNCR ((AT91_REG *) 0xFFFFF31C) // (PDC_DBGU) Transmit Next Counter Register -// ========== Register definition for DBGU peripheral ========== -#define AT91C_DBGU_EXID ((AT91_REG *) 0xFFFFF244) // (DBGU) Chip ID Extension Register -#define AT91C_DBGU_BRGR ((AT91_REG *) 0xFFFFF220) // (DBGU) Baud Rate Generator Register -#define AT91C_DBGU_IDR ((AT91_REG *) 0xFFFFF20C) // (DBGU) Interrupt Disable Register -#define AT91C_DBGU_CSR ((AT91_REG *) 0xFFFFF214) // (DBGU) Channel Status Register -#define AT91C_DBGU_CIDR ((AT91_REG *) 0xFFFFF240) // (DBGU) Chip ID Register -#define AT91C_DBGU_MR ((AT91_REG *) 0xFFFFF204) // (DBGU) Mode Register -#define AT91C_DBGU_IMR ((AT91_REG *) 0xFFFFF210) // (DBGU) Interrupt Mask Register -#define AT91C_DBGU_CR ((AT91_REG *) 0xFFFFF200) // (DBGU) Control Register -#define AT91C_DBGU_FNTR ((AT91_REG *) 0xFFFFF248) // (DBGU) Force NTRST Register -#define AT91C_DBGU_THR ((AT91_REG *) 0xFFFFF21C) // (DBGU) Transmitter Holding Register -#define AT91C_DBGU_RHR ((AT91_REG *) 0xFFFFF218) // (DBGU) Receiver Holding Register -#define AT91C_DBGU_IER ((AT91_REG *) 0xFFFFF208) // (DBGU) Interrupt Enable Register -// ========== Register definition for PIOA peripheral ========== -#define AT91C_PIOA_ODR ((AT91_REG *) 0xFFFFF414) // (PIOA) Output Disable Registerr -#define AT91C_PIOA_SODR ((AT91_REG *) 0xFFFFF430) // (PIOA) Set Output Data Register -#define AT91C_PIOA_ISR ((AT91_REG *) 0xFFFFF44C) // (PIOA) Interrupt Status Register -#define AT91C_PIOA_ABSR ((AT91_REG *) 0xFFFFF478) // (PIOA) AB Select Status Register -#define AT91C_PIOA_IER ((AT91_REG *) 0xFFFFF440) // (PIOA) Interrupt Enable Register -#define AT91C_PIOA_PPUDR ((AT91_REG *) 0xFFFFF460) // (PIOA) Pull-up Disable Register -#define AT91C_PIOA_IMR ((AT91_REG *) 0xFFFFF448) // (PIOA) Interrupt Mask Register -#define AT91C_PIOA_PER ((AT91_REG *) 0xFFFFF400) // (PIOA) PIO Enable Register -#define AT91C_PIOA_IFDR ((AT91_REG *) 0xFFFFF424) // (PIOA) Input Filter Disable Register -#define AT91C_PIOA_OWDR ((AT91_REG *) 0xFFFFF4A4) // (PIOA) Output Write Disable Register -#define AT91C_PIOA_MDSR ((AT91_REG *) 0xFFFFF458) // (PIOA) Multi-driver Status Register -#define AT91C_PIOA_IDR ((AT91_REG *) 0xFFFFF444) // (PIOA) Interrupt Disable Register -#define AT91C_PIOA_ODSR ((AT91_REG *) 0xFFFFF438) // (PIOA) Output Data Status Register -#define AT91C_PIOA_PPUSR ((AT91_REG *) 0xFFFFF468) // (PIOA) Pull-up Status Register -#define AT91C_PIOA_OWSR ((AT91_REG *) 0xFFFFF4A8) // (PIOA) Output Write Status Register -#define AT91C_PIOA_BSR ((AT91_REG *) 0xFFFFF474) // (PIOA) Select B Register -#define AT91C_PIOA_OWER ((AT91_REG *) 0xFFFFF4A0) // (PIOA) Output Write Enable Register -#define AT91C_PIOA_IFER ((AT91_REG *) 0xFFFFF420) // (PIOA) Input Filter Enable Register -#define AT91C_PIOA_PDSR ((AT91_REG *) 0xFFFFF43C) // (PIOA) Pin Data Status Register -#define AT91C_PIOA_PPUER ((AT91_REG *) 0xFFFFF464) // (PIOA) Pull-up Enable Register -#define AT91C_PIOA_OSR ((AT91_REG *) 0xFFFFF418) // (PIOA) Output Status Register -#define AT91C_PIOA_ASR ((AT91_REG *) 0xFFFFF470) // (PIOA) Select A Register -#define AT91C_PIOA_MDDR ((AT91_REG *) 0xFFFFF454) // (PIOA) Multi-driver Disable Register -#define AT91C_PIOA_CODR ((AT91_REG *) 0xFFFFF434) // (PIOA) Clear Output Data Register -#define AT91C_PIOA_MDER ((AT91_REG *) 0xFFFFF450) // (PIOA) Multi-driver Enable Register -#define AT91C_PIOA_PDR ((AT91_REG *) 0xFFFFF404) // (PIOA) PIO Disable Register -#define AT91C_PIOA_IFSR ((AT91_REG *) 0xFFFFF428) // (PIOA) Input Filter Status Register -#define AT91C_PIOA_OER ((AT91_REG *) 0xFFFFF410) // (PIOA) Output Enable Register -#define AT91C_PIOA_PSR ((AT91_REG *) 0xFFFFF408) // (PIOA) PIO Status Register -// ========== Register definition for PIOB peripheral ========== -#define AT91C_PIOB_OWDR ((AT91_REG *) 0xFFFFF6A4) // (PIOB) Output Write Disable Register -#define AT91C_PIOB_MDER ((AT91_REG *) 0xFFFFF650) // (PIOB) Multi-driver Enable Register -#define AT91C_PIOB_PPUSR ((AT91_REG *) 0xFFFFF668) // (PIOB) Pull-up Status Register -#define AT91C_PIOB_IMR ((AT91_REG *) 0xFFFFF648) // (PIOB) Interrupt Mask Register -#define AT91C_PIOB_ASR ((AT91_REG *) 0xFFFFF670) // (PIOB) Select A Register -#define AT91C_PIOB_PPUDR ((AT91_REG *) 0xFFFFF660) // (PIOB) Pull-up Disable Register -#define AT91C_PIOB_PSR ((AT91_REG *) 0xFFFFF608) // (PIOB) PIO Status Register -#define AT91C_PIOB_IER ((AT91_REG *) 0xFFFFF640) // (PIOB) Interrupt Enable Register -#define AT91C_PIOB_CODR ((AT91_REG *) 0xFFFFF634) // (PIOB) Clear Output Data Register -#define AT91C_PIOB_OWER ((AT91_REG *) 0xFFFFF6A0) // (PIOB) Output Write Enable Register -#define AT91C_PIOB_ABSR ((AT91_REG *) 0xFFFFF678) // (PIOB) AB Select Status Register -#define AT91C_PIOB_IFDR ((AT91_REG *) 0xFFFFF624) // (PIOB) Input Filter Disable Register -#define AT91C_PIOB_PDSR ((AT91_REG *) 0xFFFFF63C) // (PIOB) Pin Data Status Register -#define AT91C_PIOB_IDR ((AT91_REG *) 0xFFFFF644) // (PIOB) Interrupt Disable Register -#define AT91C_PIOB_OWSR ((AT91_REG *) 0xFFFFF6A8) // (PIOB) Output Write Status Register -#define AT91C_PIOB_PDR ((AT91_REG *) 0xFFFFF604) // (PIOB) PIO Disable Register -#define AT91C_PIOB_ODR ((AT91_REG *) 0xFFFFF614) // (PIOB) Output Disable Registerr -#define AT91C_PIOB_IFSR ((AT91_REG *) 0xFFFFF628) // (PIOB) Input Filter Status Register -#define AT91C_PIOB_PPUER ((AT91_REG *) 0xFFFFF664) // (PIOB) Pull-up Enable Register -#define AT91C_PIOB_SODR ((AT91_REG *) 0xFFFFF630) // (PIOB) Set Output Data Register -#define AT91C_PIOB_ISR ((AT91_REG *) 0xFFFFF64C) // (PIOB) Interrupt Status Register -#define AT91C_PIOB_ODSR ((AT91_REG *) 0xFFFFF638) // (PIOB) Output Data Status Register -#define AT91C_PIOB_OSR ((AT91_REG *) 0xFFFFF618) // (PIOB) Output Status Register -#define AT91C_PIOB_MDSR ((AT91_REG *) 0xFFFFF658) // (PIOB) Multi-driver Status Register -#define AT91C_PIOB_IFER ((AT91_REG *) 0xFFFFF620) // (PIOB) Input Filter Enable Register -#define AT91C_PIOB_BSR ((AT91_REG *) 0xFFFFF674) // (PIOB) Select B Register -#define AT91C_PIOB_MDDR ((AT91_REG *) 0xFFFFF654) // (PIOB) Multi-driver Disable Register -#define AT91C_PIOB_OER ((AT91_REG *) 0xFFFFF610) // (PIOB) Output Enable Register -#define AT91C_PIOB_PER ((AT91_REG *) 0xFFFFF600) // (PIOB) PIO Enable Register -// ========== Register definition for CKGR peripheral ========== -#define AT91C_CKGR_MOR ((AT91_REG *) 0xFFFFFC20) // (CKGR) Main Oscillator Register -#define AT91C_CKGR_PLLR ((AT91_REG *) 0xFFFFFC2C) // (CKGR) PLL Register -#define AT91C_CKGR_MCFR ((AT91_REG *) 0xFFFFFC24) // (CKGR) Main Clock Frequency Register -// ========== Register definition for PMC peripheral ========== -#define AT91C_PMC_IDR ((AT91_REG *) 0xFFFFFC64) // (PMC) Interrupt Disable Register -#define AT91C_PMC_MOR ((AT91_REG *) 0xFFFFFC20) // (PMC) Main Oscillator Register -#define AT91C_PMC_PLLR ((AT91_REG *) 0xFFFFFC2C) // (PMC) PLL Register -#define AT91C_PMC_PCER ((AT91_REG *) 0xFFFFFC10) // (PMC) Peripheral Clock Enable Register -#define AT91C_PMC_PCKR ((AT91_REG *) 0xFFFFFC40) // (PMC) Programmable Clock Register -#define AT91C_PMC_MCKR ((AT91_REG *) 0xFFFFFC30) // (PMC) Master Clock Register -#define AT91C_PMC_SCDR ((AT91_REG *) 0xFFFFFC04) // (PMC) System Clock Disable Register -#define AT91C_PMC_PCDR ((AT91_REG *) 0xFFFFFC14) // (PMC) Peripheral Clock Disable Register -#define AT91C_PMC_SCSR ((AT91_REG *) 0xFFFFFC08) // (PMC) System Clock Status Register -#define AT91C_PMC_PCSR ((AT91_REG *) 0xFFFFFC18) // (PMC) Peripheral Clock Status Register -#define AT91C_PMC_MCFR ((AT91_REG *) 0xFFFFFC24) // (PMC) Main Clock Frequency Register -#define AT91C_PMC_SCER ((AT91_REG *) 0xFFFFFC00) // (PMC) System Clock Enable Register -#define AT91C_PMC_IMR ((AT91_REG *) 0xFFFFFC6C) // (PMC) Interrupt Mask Register -#define AT91C_PMC_IER ((AT91_REG *) 0xFFFFFC60) // (PMC) Interrupt Enable Register -#define AT91C_PMC_SR ((AT91_REG *) 0xFFFFFC68) // (PMC) Status Register -// ========== Register definition for RSTC peripheral ========== -#define AT91C_RSTC_RCR ((AT91_REG *) 0xFFFFFD00) // (RSTC) Reset Control Register -#define AT91C_RSTC_RMR ((AT91_REG *) 0xFFFFFD08) // (RSTC) Reset Mode Register -#define AT91C_RSTC_RSR ((AT91_REG *) 0xFFFFFD04) // (RSTC) Reset Status Register -// ========== Register definition for RTTC peripheral ========== -#define AT91C_RTTC_RTSR ((AT91_REG *) 0xFFFFFD2C) // (RTTC) Real-time Status Register -#define AT91C_RTTC_RTMR ((AT91_REG *) 0xFFFFFD20) // (RTTC) Real-time Mode Register -#define AT91C_RTTC_RTVR ((AT91_REG *) 0xFFFFFD28) // (RTTC) Real-time Value Register -#define AT91C_RTTC_RTAR ((AT91_REG *) 0xFFFFFD24) // (RTTC) Real-time Alarm Register -// ========== Register definition for PITC peripheral ========== -#define AT91C_PITC_PIVR ((AT91_REG *) 0xFFFFFD38) // (PITC) Period Interval Value Register -#define AT91C_PITC_PISR ((AT91_REG *) 0xFFFFFD34) // (PITC) Period Interval Status Register -#define AT91C_PITC_PIIR ((AT91_REG *) 0xFFFFFD3C) // (PITC) Period Interval Image Register -#define AT91C_PITC_PIMR ((AT91_REG *) 0xFFFFFD30) // (PITC) Period Interval Mode Register -// ========== Register definition for WDTC peripheral ========== -#define AT91C_WDTC_WDCR ((AT91_REG *) 0xFFFFFD40) // (WDTC) Watchdog Control Register -#define AT91C_WDTC_WDSR ((AT91_REG *) 0xFFFFFD48) // (WDTC) Watchdog Status Register -#define AT91C_WDTC_WDMR ((AT91_REG *) 0xFFFFFD44) // (WDTC) Watchdog Mode Register -// ========== Register definition for VREG peripheral ========== -#define AT91C_VREG_MR ((AT91_REG *) 0xFFFFFD60) // (VREG) Voltage Regulator Mode Register -// ========== Register definition for MC peripheral ========== -#define AT91C_MC_ASR ((AT91_REG *) 0xFFFFFF04) // (MC) MC Abort Status Register -#define AT91C_MC_RCR ((AT91_REG *) 0xFFFFFF00) // (MC) MC Remap Control Register -#define AT91C_MC_FCR ((AT91_REG *) 0xFFFFFF64) // (MC) MC Flash Command Register -#define AT91C_MC_AASR ((AT91_REG *) 0xFFFFFF08) // (MC) MC Abort Address Status Register -#define AT91C_MC_FSR ((AT91_REG *) 0xFFFFFF68) // (MC) MC Flash Status Register -#define AT91C_MC_FMR ((AT91_REG *) 0xFFFFFF60) // (MC) MC Flash Mode Register -// ========== Register definition for PDC_SPI1 peripheral ========== -#define AT91C_SPI1_PTCR ((AT91_REG *) 0xFFFE4120) // (PDC_SPI1) PDC Transfer Control Register -#define AT91C_SPI1_RPR ((AT91_REG *) 0xFFFE4100) // (PDC_SPI1) Receive Pointer Register -#define AT91C_SPI1_TNCR ((AT91_REG *) 0xFFFE411C) // (PDC_SPI1) Transmit Next Counter Register -#define AT91C_SPI1_TPR ((AT91_REG *) 0xFFFE4108) // (PDC_SPI1) Transmit Pointer Register -#define AT91C_SPI1_TNPR ((AT91_REG *) 0xFFFE4118) // (PDC_SPI1) Transmit Next Pointer Register -#define AT91C_SPI1_TCR ((AT91_REG *) 0xFFFE410C) // (PDC_SPI1) Transmit Counter Register -#define AT91C_SPI1_RCR ((AT91_REG *) 0xFFFE4104) // (PDC_SPI1) Receive Counter Register -#define AT91C_SPI1_RNPR ((AT91_REG *) 0xFFFE4110) // (PDC_SPI1) Receive Next Pointer Register -#define AT91C_SPI1_RNCR ((AT91_REG *) 0xFFFE4114) // (PDC_SPI1) Receive Next Counter Register -#define AT91C_SPI1_PTSR ((AT91_REG *) 0xFFFE4124) // (PDC_SPI1) PDC Transfer Status Register -// ========== Register definition for SPI1 peripheral ========== -#define AT91C_SPI1_IMR ((AT91_REG *) 0xFFFE401C) // (SPI1) Interrupt Mask Register -#define AT91C_SPI1_IER ((AT91_REG *) 0xFFFE4014) // (SPI1) Interrupt Enable Register -#define AT91C_SPI1_MR ((AT91_REG *) 0xFFFE4004) // (SPI1) Mode Register -#define AT91C_SPI1_RDR ((AT91_REG *) 0xFFFE4008) // (SPI1) Receive Data Register -#define AT91C_SPI1_IDR ((AT91_REG *) 0xFFFE4018) // (SPI1) Interrupt Disable Register -#define AT91C_SPI1_SR ((AT91_REG *) 0xFFFE4010) // (SPI1) Status Register -#define AT91C_SPI1_TDR ((AT91_REG *) 0xFFFE400C) // (SPI1) Transmit Data Register -#define AT91C_SPI1_CR ((AT91_REG *) 0xFFFE4000) // (SPI1) Control Register -#define AT91C_SPI1_CSR ((AT91_REG *) 0xFFFE4030) // (SPI1) Chip Select Register -// ========== Register definition for PDC_SPI0 peripheral ========== -#define AT91C_SPI0_PTCR ((AT91_REG *) 0xFFFE0120) // (PDC_SPI0) PDC Transfer Control Register -#define AT91C_SPI0_TPR ((AT91_REG *) 0xFFFE0108) // (PDC_SPI0) Transmit Pointer Register -#define AT91C_SPI0_TCR ((AT91_REG *) 0xFFFE010C) // (PDC_SPI0) Transmit Counter Register -#define AT91C_SPI0_RCR ((AT91_REG *) 0xFFFE0104) // (PDC_SPI0) Receive Counter Register -#define AT91C_SPI0_PTSR ((AT91_REG *) 0xFFFE0124) // (PDC_SPI0) PDC Transfer Status Register -#define AT91C_SPI0_RNPR ((AT91_REG *) 0xFFFE0110) // (PDC_SPI0) Receive Next Pointer Register -#define AT91C_SPI0_RPR ((AT91_REG *) 0xFFFE0100) // (PDC_SPI0) Receive Pointer Register -#define AT91C_SPI0_TNCR ((AT91_REG *) 0xFFFE011C) // (PDC_SPI0) Transmit Next Counter Register -#define AT91C_SPI0_RNCR ((AT91_REG *) 0xFFFE0114) // (PDC_SPI0) Receive Next Counter Register -#define AT91C_SPI0_TNPR ((AT91_REG *) 0xFFFE0118) // (PDC_SPI0) Transmit Next Pointer Register -// ========== Register definition for SPI0 peripheral ========== -#define AT91C_SPI0_IER ((AT91_REG *) 0xFFFE0014) // (SPI0) Interrupt Enable Register -#define AT91C_SPI0_SR ((AT91_REG *) 0xFFFE0010) // (SPI0) Status Register -#define AT91C_SPI0_IDR ((AT91_REG *) 0xFFFE0018) // (SPI0) Interrupt Disable Register -#define AT91C_SPI0_CR ((AT91_REG *) 0xFFFE0000) // (SPI0) Control Register -#define AT91C_SPI0_MR ((AT91_REG *) 0xFFFE0004) // (SPI0) Mode Register -#define AT91C_SPI0_IMR ((AT91_REG *) 0xFFFE001C) // (SPI0) Interrupt Mask Register -#define AT91C_SPI0_TDR ((AT91_REG *) 0xFFFE000C) // (SPI0) Transmit Data Register -#define AT91C_SPI0_RDR ((AT91_REG *) 0xFFFE0008) // (SPI0) Receive Data Register -#define AT91C_SPI0_CSR ((AT91_REG *) 0xFFFE0030) // (SPI0) Chip Select Register -// ========== Register definition for PDC_US1 peripheral ========== -#define AT91C_US1_RNCR ((AT91_REG *) 0xFFFC4114) // (PDC_US1) Receive Next Counter Register -#define AT91C_US1_PTCR ((AT91_REG *) 0xFFFC4120) // (PDC_US1) PDC Transfer Control Register -#define AT91C_US1_TCR ((AT91_REG *) 0xFFFC410C) // (PDC_US1) Transmit Counter Register -#define AT91C_US1_PTSR ((AT91_REG *) 0xFFFC4124) // (PDC_US1) PDC Transfer Status Register -#define AT91C_US1_TNPR ((AT91_REG *) 0xFFFC4118) // (PDC_US1) Transmit Next Pointer Register -#define AT91C_US1_RCR ((AT91_REG *) 0xFFFC4104) // (PDC_US1) Receive Counter Register -#define AT91C_US1_RNPR ((AT91_REG *) 0xFFFC4110) // (PDC_US1) Receive Next Pointer Register -#define AT91C_US1_RPR ((AT91_REG *) 0xFFFC4100) // (PDC_US1) Receive Pointer Register -#define AT91C_US1_TNCR ((AT91_REG *) 0xFFFC411C) // (PDC_US1) Transmit Next Counter Register -#define AT91C_US1_TPR ((AT91_REG *) 0xFFFC4108) // (PDC_US1) Transmit Pointer Register -// ========== Register definition for US1 peripheral ========== -#define AT91C_US1_IF ((AT91_REG *) 0xFFFC404C) // (US1) IRDA_FILTER Register -#define AT91C_US1_NER ((AT91_REG *) 0xFFFC4044) // (US1) Nb Errors Register -#define AT91C_US1_RTOR ((AT91_REG *) 0xFFFC4024) // (US1) Receiver Time-out Register -#define AT91C_US1_CSR ((AT91_REG *) 0xFFFC4014) // (US1) Channel Status Register -#define AT91C_US1_IDR ((AT91_REG *) 0xFFFC400C) // (US1) Interrupt Disable Register -#define AT91C_US1_IER ((AT91_REG *) 0xFFFC4008) // (US1) Interrupt Enable Register -#define AT91C_US1_THR ((AT91_REG *) 0xFFFC401C) // (US1) Transmitter Holding Register -#define AT91C_US1_TTGR ((AT91_REG *) 0xFFFC4028) // (US1) Transmitter Time-guard Register -#define AT91C_US1_RHR ((AT91_REG *) 0xFFFC4018) // (US1) Receiver Holding Register -#define AT91C_US1_BRGR ((AT91_REG *) 0xFFFC4020) // (US1) Baud Rate Generator Register -#define AT91C_US1_IMR ((AT91_REG *) 0xFFFC4010) // (US1) Interrupt Mask Register -#define AT91C_US1_FIDI ((AT91_REG *) 0xFFFC4040) // (US1) FI_DI_Ratio Register -#define AT91C_US1_CR ((AT91_REG *) 0xFFFC4000) // (US1) Control Register -#define AT91C_US1_MR ((AT91_REG *) 0xFFFC4004) // (US1) Mode Register -// ========== Register definition for PDC_US0 peripheral ========== -#define AT91C_US0_TNPR ((AT91_REG *) 0xFFFC0118) // (PDC_US0) Transmit Next Pointer Register -#define AT91C_US0_RNPR ((AT91_REG *) 0xFFFC0110) // (PDC_US0) Receive Next Pointer Register -#define AT91C_US0_TCR ((AT91_REG *) 0xFFFC010C) // (PDC_US0) Transmit Counter Register -#define AT91C_US0_PTCR ((AT91_REG *) 0xFFFC0120) // (PDC_US0) PDC Transfer Control Register -#define AT91C_US0_PTSR ((AT91_REG *) 0xFFFC0124) // (PDC_US0) PDC Transfer Status Register -#define AT91C_US0_TNCR ((AT91_REG *) 0xFFFC011C) // (PDC_US0) Transmit Next Counter Register -#define AT91C_US0_TPR ((AT91_REG *) 0xFFFC0108) // (PDC_US0) Transmit Pointer Register -#define AT91C_US0_RCR ((AT91_REG *) 0xFFFC0104) // (PDC_US0) Receive Counter Register -#define AT91C_US0_RPR ((AT91_REG *) 0xFFFC0100) // (PDC_US0) Receive Pointer Register -#define AT91C_US0_RNCR ((AT91_REG *) 0xFFFC0114) // (PDC_US0) Receive Next Counter Register -// ========== Register definition for US0 peripheral ========== -#define AT91C_US0_BRGR ((AT91_REG *) 0xFFFC0020) // (US0) Baud Rate Generator Register -#define AT91C_US0_NER ((AT91_REG *) 0xFFFC0044) // (US0) Nb Errors Register -#define AT91C_US0_CR ((AT91_REG *) 0xFFFC0000) // (US0) Control Register -#define AT91C_US0_IMR ((AT91_REG *) 0xFFFC0010) // (US0) Interrupt Mask Register -#define AT91C_US0_FIDI ((AT91_REG *) 0xFFFC0040) // (US0) FI_DI_Ratio Register -#define AT91C_US0_TTGR ((AT91_REG *) 0xFFFC0028) // (US0) Transmitter Time-guard Register -#define AT91C_US0_MR ((AT91_REG *) 0xFFFC0004) // (US0) Mode Register -#define AT91C_US0_RTOR ((AT91_REG *) 0xFFFC0024) // (US0) Receiver Time-out Register -#define AT91C_US0_CSR ((AT91_REG *) 0xFFFC0014) // (US0) Channel Status Register -#define AT91C_US0_RHR ((AT91_REG *) 0xFFFC0018) // (US0) Receiver Holding Register -#define AT91C_US0_IDR ((AT91_REG *) 0xFFFC000C) // (US0) Interrupt Disable Register -#define AT91C_US0_THR ((AT91_REG *) 0xFFFC001C) // (US0) Transmitter Holding Register -#define AT91C_US0_IF ((AT91_REG *) 0xFFFC004C) // (US0) IRDA_FILTER Register -#define AT91C_US0_IER ((AT91_REG *) 0xFFFC0008) // (US0) Interrupt Enable Register -// ========== Register definition for PDC_SSC peripheral ========== -#define AT91C_SSC_TNCR ((AT91_REG *) 0xFFFD411C) // (PDC_SSC) Transmit Next Counter Register -#define AT91C_SSC_RPR ((AT91_REG *) 0xFFFD4100) // (PDC_SSC) Receive Pointer Register -#define AT91C_SSC_RNCR ((AT91_REG *) 0xFFFD4114) // (PDC_SSC) Receive Next Counter Register -#define AT91C_SSC_TPR ((AT91_REG *) 0xFFFD4108) // (PDC_SSC) Transmit Pointer Register -#define AT91C_SSC_PTCR ((AT91_REG *) 0xFFFD4120) // (PDC_SSC) PDC Transfer Control Register -#define AT91C_SSC_TCR ((AT91_REG *) 0xFFFD410C) // (PDC_SSC) Transmit Counter Register -#define AT91C_SSC_RCR ((AT91_REG *) 0xFFFD4104) // (PDC_SSC) Receive Counter Register -#define AT91C_SSC_RNPR ((AT91_REG *) 0xFFFD4110) // (PDC_SSC) Receive Next Pointer Register -#define AT91C_SSC_TNPR ((AT91_REG *) 0xFFFD4118) // (PDC_SSC) Transmit Next Pointer Register -#define AT91C_SSC_PTSR ((AT91_REG *) 0xFFFD4124) // (PDC_SSC) PDC Transfer Status Register -// ========== Register definition for SSC peripheral ========== -#define AT91C_SSC_RHR ((AT91_REG *) 0xFFFD4020) // (SSC) Receive Holding Register -#define AT91C_SSC_RSHR ((AT91_REG *) 0xFFFD4030) // (SSC) Receive Sync Holding Register -#define AT91C_SSC_TFMR ((AT91_REG *) 0xFFFD401C) // (SSC) Transmit Frame Mode Register -#define AT91C_SSC_IDR ((AT91_REG *) 0xFFFD4048) // (SSC) Interrupt Disable Register -#define AT91C_SSC_THR ((AT91_REG *) 0xFFFD4024) // (SSC) Transmit Holding Register -#define AT91C_SSC_RCMR ((AT91_REG *) 0xFFFD4010) // (SSC) Receive Clock ModeRegister -#define AT91C_SSC_IER ((AT91_REG *) 0xFFFD4044) // (SSC) Interrupt Enable Register -#define AT91C_SSC_TSHR ((AT91_REG *) 0xFFFD4034) // (SSC) Transmit Sync Holding Register -#define AT91C_SSC_SR ((AT91_REG *) 0xFFFD4040) // (SSC) Status Register -#define AT91C_SSC_CMR ((AT91_REG *) 0xFFFD4004) // (SSC) Clock Mode Register -#define AT91C_SSC_TCMR ((AT91_REG *) 0xFFFD4018) // (SSC) Transmit Clock Mode Register -#define AT91C_SSC_CR ((AT91_REG *) 0xFFFD4000) // (SSC) Control Register -#define AT91C_SSC_IMR ((AT91_REG *) 0xFFFD404C) // (SSC) Interrupt Mask Register -#define AT91C_SSC_RFMR ((AT91_REG *) 0xFFFD4014) // (SSC) Receive Frame Mode Register -// ========== Register definition for TWI peripheral ========== -#define AT91C_TWI_IER ((AT91_REG *) 0xFFFB8024) // (TWI) Interrupt Enable Register -#define AT91C_TWI_CR ((AT91_REG *) 0xFFFB8000) // (TWI) Control Register -#define AT91C_TWI_SR ((AT91_REG *) 0xFFFB8020) // (TWI) Status Register -#define AT91C_TWI_IMR ((AT91_REG *) 0xFFFB802C) // (TWI) Interrupt Mask Register -#define AT91C_TWI_THR ((AT91_REG *) 0xFFFB8034) // (TWI) Transmit Holding Register -#define AT91C_TWI_IDR ((AT91_REG *) 0xFFFB8028) // (TWI) Interrupt Disable Register -#define AT91C_TWI_IADR ((AT91_REG *) 0xFFFB800C) // (TWI) Internal Address Register -#define AT91C_TWI_MMR ((AT91_REG *) 0xFFFB8004) // (TWI) Master Mode Register -#define AT91C_TWI_CWGR ((AT91_REG *) 0xFFFB8010) // (TWI) Clock Waveform Generator Register -#define AT91C_TWI_RHR ((AT91_REG *) 0xFFFB8030) // (TWI) Receive Holding Register -// ========== Register definition for PWMC_CH3 peripheral ========== -#define AT91C_PWMC_CH3_CUPDR ((AT91_REG *) 0xFFFCC270) // (PWMC_CH3) Channel Update Register -#define AT91C_PWMC_CH3_Reserved ((AT91_REG *) 0xFFFCC274) // (PWMC_CH3) Reserved -#define AT91C_PWMC_CH3_CPRDR ((AT91_REG *) 0xFFFCC268) // (PWMC_CH3) Channel Period Register -#define AT91C_PWMC_CH3_CDTYR ((AT91_REG *) 0xFFFCC264) // (PWMC_CH3) Channel Duty Cycle Register -#define AT91C_PWMC_CH3_CCNTR ((AT91_REG *) 0xFFFCC26C) // (PWMC_CH3) Channel Counter Register -#define AT91C_PWMC_CH3_CMR ((AT91_REG *) 0xFFFCC260) // (PWMC_CH3) Channel Mode Register -// ========== Register definition for PWMC_CH2 peripheral ========== -#define AT91C_PWMC_CH2_Reserved ((AT91_REG *) 0xFFFCC254) // (PWMC_CH2) Reserved -#define AT91C_PWMC_CH2_CMR ((AT91_REG *) 0xFFFCC240) // (PWMC_CH2) Channel Mode Register -#define AT91C_PWMC_CH2_CCNTR ((AT91_REG *) 0xFFFCC24C) // (PWMC_CH2) Channel Counter Register -#define AT91C_PWMC_CH2_CPRDR ((AT91_REG *) 0xFFFCC248) // (PWMC_CH2) Channel Period Register -#define AT91C_PWMC_CH2_CUPDR ((AT91_REG *) 0xFFFCC250) // (PWMC_CH2) Channel Update Register -#define AT91C_PWMC_CH2_CDTYR ((AT91_REG *) 0xFFFCC244) // (PWMC_CH2) Channel Duty Cycle Register -// ========== Register definition for PWMC_CH1 peripheral ========== -#define AT91C_PWMC_CH1_Reserved ((AT91_REG *) 0xFFFCC234) // (PWMC_CH1) Reserved -#define AT91C_PWMC_CH1_CUPDR ((AT91_REG *) 0xFFFCC230) // (PWMC_CH1) Channel Update Register -#define AT91C_PWMC_CH1_CPRDR ((AT91_REG *) 0xFFFCC228) // (PWMC_CH1) Channel Period Register -#define AT91C_PWMC_CH1_CCNTR ((AT91_REG *) 0xFFFCC22C) // (PWMC_CH1) Channel Counter Register -#define AT91C_PWMC_CH1_CDTYR ((AT91_REG *) 0xFFFCC224) // (PWMC_CH1) Channel Duty Cycle Register -#define AT91C_PWMC_CH1_CMR ((AT91_REG *) 0xFFFCC220) // (PWMC_CH1) Channel Mode Register -// ========== Register definition for PWMC_CH0 peripheral ========== -#define AT91C_PWMC_CH0_Reserved ((AT91_REG *) 0xFFFCC214) // (PWMC_CH0) Reserved -#define AT91C_PWMC_CH0_CPRDR ((AT91_REG *) 0xFFFCC208) // (PWMC_CH0) Channel Period Register -#define AT91C_PWMC_CH0_CDTYR ((AT91_REG *) 0xFFFCC204) // (PWMC_CH0) Channel Duty Cycle Register -#define AT91C_PWMC_CH0_CMR ((AT91_REG *) 0xFFFCC200) // (PWMC_CH0) Channel Mode Register -#define AT91C_PWMC_CH0_CUPDR ((AT91_REG *) 0xFFFCC210) // (PWMC_CH0) Channel Update Register -#define AT91C_PWMC_CH0_CCNTR ((AT91_REG *) 0xFFFCC20C) // (PWMC_CH0) Channel Counter Register -// ========== Register definition for PWMC peripheral ========== -#define AT91C_PWMC_IDR ((AT91_REG *) 0xFFFCC014) // (PWMC) PWMC Interrupt Disable Register -#define AT91C_PWMC_DIS ((AT91_REG *) 0xFFFCC008) // (PWMC) PWMC Disable Register -#define AT91C_PWMC_IER ((AT91_REG *) 0xFFFCC010) // (PWMC) PWMC Interrupt Enable Register -#define AT91C_PWMC_VR ((AT91_REG *) 0xFFFCC0FC) // (PWMC) PWMC Version Register -#define AT91C_PWMC_ISR ((AT91_REG *) 0xFFFCC01C) // (PWMC) PWMC Interrupt Status Register -#define AT91C_PWMC_SR ((AT91_REG *) 0xFFFCC00C) // (PWMC) PWMC Status Register -#define AT91C_PWMC_IMR ((AT91_REG *) 0xFFFCC018) // (PWMC) PWMC Interrupt Mask Register -#define AT91C_PWMC_MR ((AT91_REG *) 0xFFFCC000) // (PWMC) PWMC Mode Register -#define AT91C_PWMC_ENA ((AT91_REG *) 0xFFFCC004) // (PWMC) PWMC Enable Register -// ========== Register definition for UDP peripheral ========== -#define AT91C_UDP_IMR ((AT91_REG *) 0xFFFB0018) // (UDP) Interrupt Mask Register -#define AT91C_UDP_FADDR ((AT91_REG *) 0xFFFB0008) // (UDP) Function Address Register -#define AT91C_UDP_NUM ((AT91_REG *) 0xFFFB0000) // (UDP) Frame Number Register -#define AT91C_UDP_FDR ((AT91_REG *) 0xFFFB0050) // (UDP) Endpoint FIFO Data Register -#define AT91C_UDP_ISR ((AT91_REG *) 0xFFFB001C) // (UDP) Interrupt Status Register -#define AT91C_UDP_CSR ((AT91_REG *) 0xFFFB0030) // (UDP) Endpoint Control and Status Register -#define AT91C_UDP_IDR ((AT91_REG *) 0xFFFB0014) // (UDP) Interrupt Disable Register -#define AT91C_UDP_ICR ((AT91_REG *) 0xFFFB0020) // (UDP) Interrupt Clear Register -#define AT91C_UDP_RSTEP ((AT91_REG *) 0xFFFB0028) // (UDP) Reset Endpoint Register -#define AT91C_UDP_TXVC ((AT91_REG *) 0xFFFB0074) // (UDP) Transceiver Control Register -#define AT91C_UDP_GLBSTATE ((AT91_REG *) 0xFFFB0004) // (UDP) Global State Register -#define AT91C_UDP_IER ((AT91_REG *) 0xFFFB0010) // (UDP) Interrupt Enable Register -// ========== Register definition for TC0 peripheral ========== -#define AT91C_TC0_SR ((AT91_REG *) 0xFFFA0020) // (TC0) Status Register -#define AT91C_TC0_RC ((AT91_REG *) 0xFFFA001C) // (TC0) Register C -#define AT91C_TC0_RB ((AT91_REG *) 0xFFFA0018) // (TC0) Register B -#define AT91C_TC0_CCR ((AT91_REG *) 0xFFFA0000) // (TC0) Channel Control Register -#define AT91C_TC0_CMR ((AT91_REG *) 0xFFFA0004) // (TC0) Channel Mode Register (Capture Mode / Waveform Mode) -#define AT91C_TC0_IER ((AT91_REG *) 0xFFFA0024) // (TC0) Interrupt Enable Register -#define AT91C_TC0_RA ((AT91_REG *) 0xFFFA0014) // (TC0) Register A -#define AT91C_TC0_IDR ((AT91_REG *) 0xFFFA0028) // (TC0) Interrupt Disable Register -#define AT91C_TC0_CV ((AT91_REG *) 0xFFFA0010) // (TC0) Counter Value -#define AT91C_TC0_IMR ((AT91_REG *) 0xFFFA002C) // (TC0) Interrupt Mask Register -// ========== Register definition for TC1 peripheral ========== -#define AT91C_TC1_RB ((AT91_REG *) 0xFFFA0058) // (TC1) Register B -#define AT91C_TC1_CCR ((AT91_REG *) 0xFFFA0040) // (TC1) Channel Control Register -#define AT91C_TC1_IER ((AT91_REG *) 0xFFFA0064) // (TC1) Interrupt Enable Register -#define AT91C_TC1_IDR ((AT91_REG *) 0xFFFA0068) // (TC1) Interrupt Disable Register -#define AT91C_TC1_SR ((AT91_REG *) 0xFFFA0060) // (TC1) Status Register -#define AT91C_TC1_CMR ((AT91_REG *) 0xFFFA0044) // (TC1) Channel Mode Register (Capture Mode / Waveform Mode) -#define AT91C_TC1_RA ((AT91_REG *) 0xFFFA0054) // (TC1) Register A -#define AT91C_TC1_RC ((AT91_REG *) 0xFFFA005C) // (TC1) Register C -#define AT91C_TC1_IMR ((AT91_REG *) 0xFFFA006C) // (TC1) Interrupt Mask Register -#define AT91C_TC1_CV ((AT91_REG *) 0xFFFA0050) // (TC1) Counter Value -// ========== Register definition for TC2 peripheral ========== -#define AT91C_TC2_CMR ((AT91_REG *) 0xFFFA0084) // (TC2) Channel Mode Register (Capture Mode / Waveform Mode) -#define AT91C_TC2_CCR ((AT91_REG *) 0xFFFA0080) // (TC2) Channel Control Register -#define AT91C_TC2_CV ((AT91_REG *) 0xFFFA0090) // (TC2) Counter Value -#define AT91C_TC2_RA ((AT91_REG *) 0xFFFA0094) // (TC2) Register A -#define AT91C_TC2_RB ((AT91_REG *) 0xFFFA0098) // (TC2) Register B -#define AT91C_TC2_IDR ((AT91_REG *) 0xFFFA00A8) // (TC2) Interrupt Disable Register -#define AT91C_TC2_IMR ((AT91_REG *) 0xFFFA00AC) // (TC2) Interrupt Mask Register -#define AT91C_TC2_RC ((AT91_REG *) 0xFFFA009C) // (TC2) Register C -#define AT91C_TC2_IER ((AT91_REG *) 0xFFFA00A4) // (TC2) Interrupt Enable Register -#define AT91C_TC2_SR ((AT91_REG *) 0xFFFA00A0) // (TC2) Status Register -// ========== Register definition for TCB peripheral ========== -#define AT91C_TCB_BMR ((AT91_REG *) 0xFFFA00C4) // (TCB) TC Block Mode Register -#define AT91C_TCB_BCR ((AT91_REG *) 0xFFFA00C0) // (TCB) TC Block Control Register -// ========== Register definition for CAN_MB0 peripheral ========== -#define AT91C_CAN_MB0_MDL ((AT91_REG *) 0xFFFD0214) // (CAN_MB0) MailBox Data Low Register -#define AT91C_CAN_MB0_MAM ((AT91_REG *) 0xFFFD0204) // (CAN_MB0) MailBox Acceptance Mask Register -#define AT91C_CAN_MB0_MCR ((AT91_REG *) 0xFFFD021C) // (CAN_MB0) MailBox Control Register -#define AT91C_CAN_MB0_MID ((AT91_REG *) 0xFFFD0208) // (CAN_MB0) MailBox ID Register -#define AT91C_CAN_MB0_MSR ((AT91_REG *) 0xFFFD0210) // (CAN_MB0) MailBox Status Register -#define AT91C_CAN_MB0_MFID ((AT91_REG *) 0xFFFD020C) // (CAN_MB0) MailBox Family ID Register -#define AT91C_CAN_MB0_MDH ((AT91_REG *) 0xFFFD0218) // (CAN_MB0) MailBox Data High Register -#define AT91C_CAN_MB0_MMR ((AT91_REG *) 0xFFFD0200) // (CAN_MB0) MailBox Mode Register -// ========== Register definition for CAN_MB1 peripheral ========== -#define AT91C_CAN_MB1_MDL ((AT91_REG *) 0xFFFD0234) // (CAN_MB1) MailBox Data Low Register -#define AT91C_CAN_MB1_MID ((AT91_REG *) 0xFFFD0228) // (CAN_MB1) MailBox ID Register -#define AT91C_CAN_MB1_MMR ((AT91_REG *) 0xFFFD0220) // (CAN_MB1) MailBox Mode Register -#define AT91C_CAN_MB1_MSR ((AT91_REG *) 0xFFFD0230) // (CAN_MB1) MailBox Status Register -#define AT91C_CAN_MB1_MAM ((AT91_REG *) 0xFFFD0224) // (CAN_MB1) MailBox Acceptance Mask Register -#define AT91C_CAN_MB1_MDH ((AT91_REG *) 0xFFFD0238) // (CAN_MB1) MailBox Data High Register -#define AT91C_CAN_MB1_MCR ((AT91_REG *) 0xFFFD023C) // (CAN_MB1) MailBox Control Register -#define AT91C_CAN_MB1_MFID ((AT91_REG *) 0xFFFD022C) // (CAN_MB1) MailBox Family ID Register -// ========== Register definition for CAN_MB2 peripheral ========== -#define AT91C_CAN_MB2_MCR ((AT91_REG *) 0xFFFD025C) // (CAN_MB2) MailBox Control Register -#define AT91C_CAN_MB2_MDH ((AT91_REG *) 0xFFFD0258) // (CAN_MB2) MailBox Data High Register -#define AT91C_CAN_MB2_MID ((AT91_REG *) 0xFFFD0248) // (CAN_MB2) MailBox ID Register -#define AT91C_CAN_MB2_MDL ((AT91_REG *) 0xFFFD0254) // (CAN_MB2) MailBox Data Low Register -#define AT91C_CAN_MB2_MMR ((AT91_REG *) 0xFFFD0240) // (CAN_MB2) MailBox Mode Register -#define AT91C_CAN_MB2_MAM ((AT91_REG *) 0xFFFD0244) // (CAN_MB2) MailBox Acceptance Mask Register -#define AT91C_CAN_MB2_MFID ((AT91_REG *) 0xFFFD024C) // (CAN_MB2) MailBox Family ID Register -#define AT91C_CAN_MB2_MSR ((AT91_REG *) 0xFFFD0250) // (CAN_MB2) MailBox Status Register -// ========== Register definition for CAN_MB3 peripheral ========== -#define AT91C_CAN_MB3_MFID ((AT91_REG *) 0xFFFD026C) // (CAN_MB3) MailBox Family ID Register -#define AT91C_CAN_MB3_MAM ((AT91_REG *) 0xFFFD0264) // (CAN_MB3) MailBox Acceptance Mask Register -#define AT91C_CAN_MB3_MID ((AT91_REG *) 0xFFFD0268) // (CAN_MB3) MailBox ID Register -#define AT91C_CAN_MB3_MCR ((AT91_REG *) 0xFFFD027C) // (CAN_MB3) MailBox Control Register -#define AT91C_CAN_MB3_MMR ((AT91_REG *) 0xFFFD0260) // (CAN_MB3) MailBox Mode Register -#define AT91C_CAN_MB3_MSR ((AT91_REG *) 0xFFFD0270) // (CAN_MB3) MailBox Status Register -#define AT91C_CAN_MB3_MDL ((AT91_REG *) 0xFFFD0274) // (CAN_MB3) MailBox Data Low Register -#define AT91C_CAN_MB3_MDH ((AT91_REG *) 0xFFFD0278) // (CAN_MB3) MailBox Data High Register -// ========== Register definition for CAN_MB4 peripheral ========== -#define AT91C_CAN_MB4_MID ((AT91_REG *) 0xFFFD0288) // (CAN_MB4) MailBox ID Register -#define AT91C_CAN_MB4_MMR ((AT91_REG *) 0xFFFD0280) // (CAN_MB4) MailBox Mode Register -#define AT91C_CAN_MB4_MDH ((AT91_REG *) 0xFFFD0298) // (CAN_MB4) MailBox Data High Register -#define AT91C_CAN_MB4_MFID ((AT91_REG *) 0xFFFD028C) // (CAN_MB4) MailBox Family ID Register -#define AT91C_CAN_MB4_MSR ((AT91_REG *) 0xFFFD0290) // (CAN_MB4) MailBox Status Register -#define AT91C_CAN_MB4_MCR ((AT91_REG *) 0xFFFD029C) // (CAN_MB4) MailBox Control Register -#define AT91C_CAN_MB4_MDL ((AT91_REG *) 0xFFFD0294) // (CAN_MB4) MailBox Data Low Register -#define AT91C_CAN_MB4_MAM ((AT91_REG *) 0xFFFD0284) // (CAN_MB4) MailBox Acceptance Mask Register -// ========== Register definition for CAN_MB5 peripheral ========== -#define AT91C_CAN_MB5_MSR ((AT91_REG *) 0xFFFD02B0) // (CAN_MB5) MailBox Status Register -#define AT91C_CAN_MB5_MCR ((AT91_REG *) 0xFFFD02BC) // (CAN_MB5) MailBox Control Register -#define AT91C_CAN_MB5_MFID ((AT91_REG *) 0xFFFD02AC) // (CAN_MB5) MailBox Family ID Register -#define AT91C_CAN_MB5_MDH ((AT91_REG *) 0xFFFD02B8) // (CAN_MB5) MailBox Data High Register -#define AT91C_CAN_MB5_MID ((AT91_REG *) 0xFFFD02A8) // (CAN_MB5) MailBox ID Register -#define AT91C_CAN_MB5_MMR ((AT91_REG *) 0xFFFD02A0) // (CAN_MB5) MailBox Mode Register -#define AT91C_CAN_MB5_MDL ((AT91_REG *) 0xFFFD02B4) // (CAN_MB5) MailBox Data Low Register -#define AT91C_CAN_MB5_MAM ((AT91_REG *) 0xFFFD02A4) // (CAN_MB5) MailBox Acceptance Mask Register -// ========== Register definition for CAN_MB6 peripheral ========== -#define AT91C_CAN_MB6_MFID ((AT91_REG *) 0xFFFD02CC) // (CAN_MB6) MailBox Family ID Register -#define AT91C_CAN_MB6_MID ((AT91_REG *) 0xFFFD02C8) // (CAN_MB6) MailBox ID Register -#define AT91C_CAN_MB6_MAM ((AT91_REG *) 0xFFFD02C4) // (CAN_MB6) MailBox Acceptance Mask Register -#define AT91C_CAN_MB6_MSR ((AT91_REG *) 0xFFFD02D0) // (CAN_MB6) MailBox Status Register -#define AT91C_CAN_MB6_MDL ((AT91_REG *) 0xFFFD02D4) // (CAN_MB6) MailBox Data Low Register -#define AT91C_CAN_MB6_MCR ((AT91_REG *) 0xFFFD02DC) // (CAN_MB6) MailBox Control Register -#define AT91C_CAN_MB6_MDH ((AT91_REG *) 0xFFFD02D8) // (CAN_MB6) MailBox Data High Register -#define AT91C_CAN_MB6_MMR ((AT91_REG *) 0xFFFD02C0) // (CAN_MB6) MailBox Mode Register -// ========== Register definition for CAN_MB7 peripheral ========== -#define AT91C_CAN_MB7_MCR ((AT91_REG *) 0xFFFD02FC) // (CAN_MB7) MailBox Control Register -#define AT91C_CAN_MB7_MDH ((AT91_REG *) 0xFFFD02F8) // (CAN_MB7) MailBox Data High Register -#define AT91C_CAN_MB7_MFID ((AT91_REG *) 0xFFFD02EC) // (CAN_MB7) MailBox Family ID Register -#define AT91C_CAN_MB7_MDL ((AT91_REG *) 0xFFFD02F4) // (CAN_MB7) MailBox Data Low Register -#define AT91C_CAN_MB7_MID ((AT91_REG *) 0xFFFD02E8) // (CAN_MB7) MailBox ID Register -#define AT91C_CAN_MB7_MMR ((AT91_REG *) 0xFFFD02E0) // (CAN_MB7) MailBox Mode Register -#define AT91C_CAN_MB7_MAM ((AT91_REG *) 0xFFFD02E4) // (CAN_MB7) MailBox Acceptance Mask Register -#define AT91C_CAN_MB7_MSR ((AT91_REG *) 0xFFFD02F0) // (CAN_MB7) MailBox Status Register -// ========== Register definition for CAN peripheral ========== -#define AT91C_CAN_TCR ((AT91_REG *) 0xFFFD0024) // (CAN) Transfer Command Register -#define AT91C_CAN_IMR ((AT91_REG *) 0xFFFD000C) // (CAN) Interrupt Mask Register -#define AT91C_CAN_IER ((AT91_REG *) 0xFFFD0004) // (CAN) Interrupt Enable Register -#define AT91C_CAN_ECR ((AT91_REG *) 0xFFFD0020) // (CAN) Error Counter Register -#define AT91C_CAN_TIMESTP ((AT91_REG *) 0xFFFD001C) // (CAN) Time Stamp Register -#define AT91C_CAN_MR ((AT91_REG *) 0xFFFD0000) // (CAN) Mode Register -#define AT91C_CAN_IDR ((AT91_REG *) 0xFFFD0008) // (CAN) Interrupt Disable Register -#define AT91C_CAN_ACR ((AT91_REG *) 0xFFFD0028) // (CAN) Abort Command Register -#define AT91C_CAN_TIM ((AT91_REG *) 0xFFFD0018) // (CAN) Timer Register -#define AT91C_CAN_SR ((AT91_REG *) 0xFFFD0010) // (CAN) Status Register -#define AT91C_CAN_BR ((AT91_REG *) 0xFFFD0014) // (CAN) Baudrate Register -#define AT91C_CAN_VR ((AT91_REG *) 0xFFFD00FC) // (CAN) Version Register -// ========== Register definition for EMAC peripheral ========== -#define AT91C_EMAC_ISR ((AT91_REG *) 0xFFFDC024) // (EMAC) Interrupt Status Register -#define AT91C_EMAC_SA4H ((AT91_REG *) 0xFFFDC0B4) // (EMAC) Specific Address 4 Top, Last 2 bytes -#define AT91C_EMAC_SA1L ((AT91_REG *) 0xFFFDC098) // (EMAC) Specific Address 1 Bottom, First 4 bytes -#define AT91C_EMAC_ELE ((AT91_REG *) 0xFFFDC078) // (EMAC) Excessive Length Errors Register -#define AT91C_EMAC_LCOL ((AT91_REG *) 0xFFFDC05C) // (EMAC) Late Collision Register -#define AT91C_EMAC_RLE ((AT91_REG *) 0xFFFDC088) // (EMAC) Receive Length Field Mismatch Register -#define AT91C_EMAC_WOL ((AT91_REG *) 0xFFFDC0C4) // (EMAC) Wake On LAN Register -#define AT91C_EMAC_DTF ((AT91_REG *) 0xFFFDC058) // (EMAC) Deferred Transmission Frame Register -#define AT91C_EMAC_TUND ((AT91_REG *) 0xFFFDC064) // (EMAC) Transmit Underrun Error Register -#define AT91C_EMAC_NCR ((AT91_REG *) 0xFFFDC000) // (EMAC) Network Control Register -#define AT91C_EMAC_SA4L ((AT91_REG *) 0xFFFDC0B0) // (EMAC) Specific Address 4 Bottom, First 4 bytes -#define AT91C_EMAC_RSR ((AT91_REG *) 0xFFFDC020) // (EMAC) Receive Status Register -#define AT91C_EMAC_SA3L ((AT91_REG *) 0xFFFDC0A8) // (EMAC) Specific Address 3 Bottom, First 4 bytes -#define AT91C_EMAC_TSR ((AT91_REG *) 0xFFFDC014) // (EMAC) Transmit Status Register -#define AT91C_EMAC_IDR ((AT91_REG *) 0xFFFDC02C) // (EMAC) Interrupt Disable Register -#define AT91C_EMAC_RSE ((AT91_REG *) 0xFFFDC074) // (EMAC) Receive Symbol Errors Register -#define AT91C_EMAC_ECOL ((AT91_REG *) 0xFFFDC060) // (EMAC) Excessive Collision Register -#define AT91C_EMAC_TID ((AT91_REG *) 0xFFFDC0B8) // (EMAC) Type ID Checking Register -#define AT91C_EMAC_HRB ((AT91_REG *) 0xFFFDC090) // (EMAC) Hash Address Bottom[31:0] -#define AT91C_EMAC_TBQP ((AT91_REG *) 0xFFFDC01C) // (EMAC) Transmit Buffer Queue Pointer -#define AT91C_EMAC_USRIO ((AT91_REG *) 0xFFFDC0C0) // (EMAC) USER Input/Output Register -#define AT91C_EMAC_PTR ((AT91_REG *) 0xFFFDC038) // (EMAC) Pause Time Register -#define AT91C_EMAC_SA2H ((AT91_REG *) 0xFFFDC0A4) // (EMAC) Specific Address 2 Top, Last 2 bytes -#define AT91C_EMAC_ROV ((AT91_REG *) 0xFFFDC070) // (EMAC) Receive Overrun Errors Register -#define AT91C_EMAC_ALE ((AT91_REG *) 0xFFFDC054) // (EMAC) Alignment Error Register -#define AT91C_EMAC_RJA ((AT91_REG *) 0xFFFDC07C) // (EMAC) Receive Jabbers Register -#define AT91C_EMAC_RBQP ((AT91_REG *) 0xFFFDC018) // (EMAC) Receive Buffer Queue Pointer -#define AT91C_EMAC_TPF ((AT91_REG *) 0xFFFDC08C) // (EMAC) Transmitted Pause Frames Register -#define AT91C_EMAC_NCFGR ((AT91_REG *) 0xFFFDC004) // (EMAC) Network Configuration Register -#define AT91C_EMAC_HRT ((AT91_REG *) 0xFFFDC094) // (EMAC) Hash Address Top[63:32] -#define AT91C_EMAC_USF ((AT91_REG *) 0xFFFDC080) // (EMAC) Undersize Frames Register -#define AT91C_EMAC_FCSE ((AT91_REG *) 0xFFFDC050) // (EMAC) Frame Check Sequence Error Register -#define AT91C_EMAC_TPQ ((AT91_REG *) 0xFFFDC0BC) // (EMAC) Transmit Pause Quantum Register -#define AT91C_EMAC_MAN ((AT91_REG *) 0xFFFDC034) // (EMAC) PHY Maintenance Register -#define AT91C_EMAC_FTO ((AT91_REG *) 0xFFFDC040) // (EMAC) Frames Transmitted OK Register -#define AT91C_EMAC_REV ((AT91_REG *) 0xFFFDC0FC) // (EMAC) Revision Register -#define AT91C_EMAC_IMR ((AT91_REG *) 0xFFFDC030) // (EMAC) Interrupt Mask Register -#define AT91C_EMAC_SCF ((AT91_REG *) 0xFFFDC044) // (EMAC) Single Collision Frame Register -#define AT91C_EMAC_PFR ((AT91_REG *) 0xFFFDC03C) // (EMAC) Pause Frames received Register -#define AT91C_EMAC_MCF ((AT91_REG *) 0xFFFDC048) // (EMAC) Multiple Collision Frame Register -#define AT91C_EMAC_NSR ((AT91_REG *) 0xFFFDC008) // (EMAC) Network Status Register -#define AT91C_EMAC_SA2L ((AT91_REG *) 0xFFFDC0A0) // (EMAC) Specific Address 2 Bottom, First 4 bytes -#define AT91C_EMAC_FRO ((AT91_REG *) 0xFFFDC04C) // (EMAC) Frames Received OK Register -#define AT91C_EMAC_IER ((AT91_REG *) 0xFFFDC028) // (EMAC) Interrupt Enable Register -#define AT91C_EMAC_SA1H ((AT91_REG *) 0xFFFDC09C) // (EMAC) Specific Address 1 Top, Last 2 bytes -#define AT91C_EMAC_CSE ((AT91_REG *) 0xFFFDC068) // (EMAC) Carrier Sense Error Register -#define AT91C_EMAC_SA3H ((AT91_REG *) 0xFFFDC0AC) // (EMAC) Specific Address 3 Top, Last 2 bytes -#define AT91C_EMAC_RRE ((AT91_REG *) 0xFFFDC06C) // (EMAC) Receive Ressource Error Register -#define AT91C_EMAC_STE ((AT91_REG *) 0xFFFDC084) // (EMAC) SQE Test Error Register -// ========== Register definition for PDC_ADC peripheral ========== -#define AT91C_ADC_PTSR ((AT91_REG *) 0xFFFD8124) // (PDC_ADC) PDC Transfer Status Register -#define AT91C_ADC_PTCR ((AT91_REG *) 0xFFFD8120) // (PDC_ADC) PDC Transfer Control Register -#define AT91C_ADC_TNPR ((AT91_REG *) 0xFFFD8118) // (PDC_ADC) Transmit Next Pointer Register -#define AT91C_ADC_TNCR ((AT91_REG *) 0xFFFD811C) // (PDC_ADC) Transmit Next Counter Register -#define AT91C_ADC_RNPR ((AT91_REG *) 0xFFFD8110) // (PDC_ADC) Receive Next Pointer Register -#define AT91C_ADC_RNCR ((AT91_REG *) 0xFFFD8114) // (PDC_ADC) Receive Next Counter Register -#define AT91C_ADC_RPR ((AT91_REG *) 0xFFFD8100) // (PDC_ADC) Receive Pointer Register -#define AT91C_ADC_TCR ((AT91_REG *) 0xFFFD810C) // (PDC_ADC) Transmit Counter Register -#define AT91C_ADC_TPR ((AT91_REG *) 0xFFFD8108) // (PDC_ADC) Transmit Pointer Register -#define AT91C_ADC_RCR ((AT91_REG *) 0xFFFD8104) // (PDC_ADC) Receive Counter Register -// ========== Register definition for ADC peripheral ========== -#define AT91C_ADC_CDR2 ((AT91_REG *) 0xFFFD8038) // (ADC) ADC Channel Data Register 2 -#define AT91C_ADC_CDR3 ((AT91_REG *) 0xFFFD803C) // (ADC) ADC Channel Data Register 3 -#define AT91C_ADC_CDR0 ((AT91_REG *) 0xFFFD8030) // (ADC) ADC Channel Data Register 0 -#define AT91C_ADC_CDR5 ((AT91_REG *) 0xFFFD8044) // (ADC) ADC Channel Data Register 5 -#define AT91C_ADC_CHDR ((AT91_REG *) 0xFFFD8014) // (ADC) ADC Channel Disable Register -#define AT91C_ADC_SR ((AT91_REG *) 0xFFFD801C) // (ADC) ADC Status Register -#define AT91C_ADC_CDR4 ((AT91_REG *) 0xFFFD8040) // (ADC) ADC Channel Data Register 4 -#define AT91C_ADC_CDR1 ((AT91_REG *) 0xFFFD8034) // (ADC) ADC Channel Data Register 1 -#define AT91C_ADC_LCDR ((AT91_REG *) 0xFFFD8020) // (ADC) ADC Last Converted Data Register -#define AT91C_ADC_IDR ((AT91_REG *) 0xFFFD8028) // (ADC) ADC Interrupt Disable Register -#define AT91C_ADC_CR ((AT91_REG *) 0xFFFD8000) // (ADC) ADC Control Register -#define AT91C_ADC_CDR7 ((AT91_REG *) 0xFFFD804C) // (ADC) ADC Channel Data Register 7 -#define AT91C_ADC_CDR6 ((AT91_REG *) 0xFFFD8048) // (ADC) ADC Channel Data Register 6 -#define AT91C_ADC_IER ((AT91_REG *) 0xFFFD8024) // (ADC) ADC Interrupt Enable Register -#define AT91C_ADC_CHER ((AT91_REG *) 0xFFFD8010) // (ADC) ADC Channel Enable Register -#define AT91C_ADC_CHSR ((AT91_REG *) 0xFFFD8018) // (ADC) ADC Channel Status Register -#define AT91C_ADC_MR ((AT91_REG *) 0xFFFD8004) // (ADC) ADC Mode Register -#define AT91C_ADC_IMR ((AT91_REG *) 0xFFFD802C) // (ADC) ADC Interrupt Mask Register -// ========== Register definition for PDC_AES peripheral ========== -#define AT91C_AES_TPR ((AT91_REG *) 0xFFFA4108) // (PDC_AES) Transmit Pointer Register -#define AT91C_AES_PTCR ((AT91_REG *) 0xFFFA4120) // (PDC_AES) PDC Transfer Control Register -#define AT91C_AES_RNPR ((AT91_REG *) 0xFFFA4110) // (PDC_AES) Receive Next Pointer Register -#define AT91C_AES_TNCR ((AT91_REG *) 0xFFFA411C) // (PDC_AES) Transmit Next Counter Register -#define AT91C_AES_TCR ((AT91_REG *) 0xFFFA410C) // (PDC_AES) Transmit Counter Register -#define AT91C_AES_RCR ((AT91_REG *) 0xFFFA4104) // (PDC_AES) Receive Counter Register -#define AT91C_AES_RNCR ((AT91_REG *) 0xFFFA4114) // (PDC_AES) Receive Next Counter Register -#define AT91C_AES_TNPR ((AT91_REG *) 0xFFFA4118) // (PDC_AES) Transmit Next Pointer Register -#define AT91C_AES_RPR ((AT91_REG *) 0xFFFA4100) // (PDC_AES) Receive Pointer Register -#define AT91C_AES_PTSR ((AT91_REG *) 0xFFFA4124) // (PDC_AES) PDC Transfer Status Register -// ========== Register definition for AES peripheral ========== -#define AT91C_AES_IVxR ((AT91_REG *) 0xFFFA4060) // (AES) Initialization Vector x Register -#define AT91C_AES_MR ((AT91_REG *) 0xFFFA4004) // (AES) Mode Register -#define AT91C_AES_VR ((AT91_REG *) 0xFFFA40FC) // (AES) AES Version Register -#define AT91C_AES_ODATAxR ((AT91_REG *) 0xFFFA4050) // (AES) Output Data x Register -#define AT91C_AES_IDATAxR ((AT91_REG *) 0xFFFA4040) // (AES) Input Data x Register -#define AT91C_AES_CR ((AT91_REG *) 0xFFFA4000) // (AES) Control Register -#define AT91C_AES_IDR ((AT91_REG *) 0xFFFA4014) // (AES) Interrupt Disable Register -#define AT91C_AES_IMR ((AT91_REG *) 0xFFFA4018) // (AES) Interrupt Mask Register -#define AT91C_AES_IER ((AT91_REG *) 0xFFFA4010) // (AES) Interrupt Enable Register -#define AT91C_AES_KEYWxR ((AT91_REG *) 0xFFFA4020) // (AES) Key Word x Register -#define AT91C_AES_ISR ((AT91_REG *) 0xFFFA401C) // (AES) Interrupt Status Register -// ========== Register definition for PDC_TDES peripheral ========== -#define AT91C_TDES_RNCR ((AT91_REG *) 0xFFFA8114) // (PDC_TDES) Receive Next Counter Register -#define AT91C_TDES_TCR ((AT91_REG *) 0xFFFA810C) // (PDC_TDES) Transmit Counter Register -#define AT91C_TDES_RCR ((AT91_REG *) 0xFFFA8104) // (PDC_TDES) Receive Counter Register -#define AT91C_TDES_TNPR ((AT91_REG *) 0xFFFA8118) // (PDC_TDES) Transmit Next Pointer Register -#define AT91C_TDES_RNPR ((AT91_REG *) 0xFFFA8110) // (PDC_TDES) Receive Next Pointer Register -#define AT91C_TDES_RPR ((AT91_REG *) 0xFFFA8100) // (PDC_TDES) Receive Pointer Register -#define AT91C_TDES_TNCR ((AT91_REG *) 0xFFFA811C) // (PDC_TDES) Transmit Next Counter Register -#define AT91C_TDES_TPR ((AT91_REG *) 0xFFFA8108) // (PDC_TDES) Transmit Pointer Register -#define AT91C_TDES_PTSR ((AT91_REG *) 0xFFFA8124) // (PDC_TDES) PDC Transfer Status Register -#define AT91C_TDES_PTCR ((AT91_REG *) 0xFFFA8120) // (PDC_TDES) PDC Transfer Control Register -// ========== Register definition for TDES peripheral ========== -#define AT91C_TDES_KEY2WxR ((AT91_REG *) 0xFFFA8028) // (TDES) Key 2 Word x Register -#define AT91C_TDES_KEY3WxR ((AT91_REG *) 0xFFFA8030) // (TDES) Key 3 Word x Register -#define AT91C_TDES_IDR ((AT91_REG *) 0xFFFA8014) // (TDES) Interrupt Disable Register -#define AT91C_TDES_VR ((AT91_REG *) 0xFFFA80FC) // (TDES) TDES Version Register -#define AT91C_TDES_IVxR ((AT91_REG *) 0xFFFA8060) // (TDES) Initialization Vector x Register -#define AT91C_TDES_ODATAxR ((AT91_REG *) 0xFFFA8050) // (TDES) Output Data x Register -#define AT91C_TDES_IMR ((AT91_REG *) 0xFFFA8018) // (TDES) Interrupt Mask Register -#define AT91C_TDES_MR ((AT91_REG *) 0xFFFA8004) // (TDES) Mode Register -#define AT91C_TDES_CR ((AT91_REG *) 0xFFFA8000) // (TDES) Control Register -#define AT91C_TDES_IER ((AT91_REG *) 0xFFFA8010) // (TDES) Interrupt Enable Register -#define AT91C_TDES_ISR ((AT91_REG *) 0xFFFA801C) // (TDES) Interrupt Status Register -#define AT91C_TDES_IDATAxR ((AT91_REG *) 0xFFFA8040) // (TDES) Input Data x Register -#define AT91C_TDES_KEY1WxR ((AT91_REG *) 0xFFFA8020) // (TDES) Key 1 Word x Register - -// ***************************************************************************** -// PIO DEFINITIONS FOR AT91SAM7X256 -// ***************************************************************************** -#define AT91C_PIO_PA0 ((unsigned int) 1 << 0) // Pin Controlled by PA0 -#define AT91C_PA0_RXD0 ((unsigned int) AT91C_PIO_PA0) // USART 0 Receive Data -#define AT91C_PIO_PA1 ((unsigned int) 1 << 1) // Pin Controlled by PA1 -#define AT91C_PA1_TXD0 ((unsigned int) AT91C_PIO_PA1) // USART 0 Transmit Data -#define AT91C_PIO_PA10 ((unsigned int) 1 << 10) // Pin Controlled by PA10 -#define AT91C_PA10_TWD ((unsigned int) AT91C_PIO_PA10) // TWI Two-wire Serial Data -#define AT91C_PIO_PA11 ((unsigned int) 1 << 11) // Pin Controlled by PA11 -#define AT91C_PA11_TWCK ((unsigned int) AT91C_PIO_PA11) // TWI Two-wire Serial Clock -#define AT91C_PIO_PA12 ((unsigned int) 1 << 12) // Pin Controlled by PA12 -#define AT91C_PA12_NPCS00 ((unsigned int) AT91C_PIO_PA12) // SPI 0 Peripheral Chip Select 0 -#define AT91C_PIO_PA13 ((unsigned int) 1 << 13) // Pin Controlled by PA13 -#define AT91C_PA13_NPCS01 ((unsigned int) AT91C_PIO_PA13) // SPI 0 Peripheral Chip Select 1 -#define AT91C_PA13_PCK1 ((unsigned int) AT91C_PIO_PA13) // PMC Programmable Clock Output 1 -#define AT91C_PIO_PA14 ((unsigned int) 1 << 14) // Pin Controlled by PA14 -#define AT91C_PA14_NPCS02 ((unsigned int) AT91C_PIO_PA14) // SPI 0 Peripheral Chip Select 2 -#define AT91C_PA14_IRQ1 ((unsigned int) AT91C_PIO_PA14) // External Interrupt 1 -#define AT91C_PIO_PA15 ((unsigned int) 1 << 15) // Pin Controlled by PA15 -#define AT91C_PA15_NPCS03 ((unsigned int) AT91C_PIO_PA15) // SPI 0 Peripheral Chip Select 3 -#define AT91C_PA15_TCLK2 ((unsigned int) AT91C_PIO_PA15) // Timer Counter 2 external clock input -#define AT91C_PIO_PA16 ((unsigned int) 1 << 16) // Pin Controlled by PA16 -#define AT91C_PA16_MISO0 ((unsigned int) AT91C_PIO_PA16) // SPI 0 Master In Slave -#define AT91C_PIO_PA17 ((unsigned int) 1 << 17) // Pin Controlled by PA17 -#define AT91C_PA17_MOSI0 ((unsigned int) AT91C_PIO_PA17) // SPI 0 Master Out Slave -#define AT91C_PIO_PA18 ((unsigned int) 1 << 18) // Pin Controlled by PA18 -#define AT91C_PA18_SPCK0 ((unsigned int) AT91C_PIO_PA18) // SPI 0 Serial Clock -#define AT91C_PIO_PA19 ((unsigned int) 1 << 19) // Pin Controlled by PA19 -#define AT91C_PA19_CANRX ((unsigned int) AT91C_PIO_PA19) // CAN Receive -#define AT91C_PIO_PA2 ((unsigned int) 1 << 2) // Pin Controlled by PA2 -#define AT91C_PA2_SCK0 ((unsigned int) AT91C_PIO_PA2) // USART 0 Serial Clock -#define AT91C_PA2_NPCS11 ((unsigned int) AT91C_PIO_PA2) // SPI 1 Peripheral Chip Select 1 -#define AT91C_PIO_PA20 ((unsigned int) 1 << 20) // Pin Controlled by PA20 -#define AT91C_PA20_CANTX ((unsigned int) AT91C_PIO_PA20) // CAN Transmit -#define AT91C_PIO_PA21 ((unsigned int) 1 << 21) // Pin Controlled by PA21 -#define AT91C_PA21_TF ((unsigned int) AT91C_PIO_PA21) // SSC Transmit Frame Sync -#define AT91C_PA21_NPCS10 ((unsigned int) AT91C_PIO_PA21) // SPI 1 Peripheral Chip Select 0 -#define AT91C_PIO_PA22 ((unsigned int) 1 << 22) // Pin Controlled by PA22 -#define AT91C_PA22_TK ((unsigned int) AT91C_PIO_PA22) // SSC Transmit Clock -#define AT91C_PA22_SPCK1 ((unsigned int) AT91C_PIO_PA22) // SPI 1 Serial Clock -#define AT91C_PIO_PA23 ((unsigned int) 1 << 23) // Pin Controlled by PA23 -#define AT91C_PA23_TD ((unsigned int) AT91C_PIO_PA23) // SSC Transmit data -#define AT91C_PA23_MOSI1 ((unsigned int) AT91C_PIO_PA23) // SPI 1 Master Out Slave -#define AT91C_PIO_PA24 ((unsigned int) 1 << 24) // Pin Controlled by PA24 -#define AT91C_PA24_RD ((unsigned int) AT91C_PIO_PA24) // SSC Receive Data -#define AT91C_PA24_MISO1 ((unsigned int) AT91C_PIO_PA24) // SPI 1 Master In Slave -#define AT91C_PIO_PA25 ((unsigned int) 1 << 25) // Pin Controlled by PA25 -#define AT91C_PA25_RK ((unsigned int) AT91C_PIO_PA25) // SSC Receive Clock -#define AT91C_PA25_NPCS11 ((unsigned int) AT91C_PIO_PA25) // SPI 1 Peripheral Chip Select 1 -#define AT91C_PIO_PA26 ((unsigned int) 1 << 26) // Pin Controlled by PA26 -#define AT91C_PA26_RF ((unsigned int) AT91C_PIO_PA26) // SSC Receive Frame Sync -#define AT91C_PA26_NPCS12 ((unsigned int) AT91C_PIO_PA26) // SPI 1 Peripheral Chip Select 2 -#define AT91C_PIO_PA27 ((unsigned int) 1 << 27) // Pin Controlled by PA27 -#define AT91C_PA27_DRXD ((unsigned int) AT91C_PIO_PA27) // DBGU Debug Receive Data -#define AT91C_PA27_PCK3 ((unsigned int) AT91C_PIO_PA27) // PMC Programmable Clock Output 3 -#define AT91C_PIO_PA28 ((unsigned int) 1 << 28) // Pin Controlled by PA28 -#define AT91C_PA28_DTXD ((unsigned int) AT91C_PIO_PA28) // DBGU Debug Transmit Data -#define AT91C_PIO_PA29 ((unsigned int) 1 << 29) // Pin Controlled by PA29 -#define AT91C_PA29_FIQ ((unsigned int) AT91C_PIO_PA29) // AIC Fast Interrupt Input -#define AT91C_PA29_NPCS13 ((unsigned int) AT91C_PIO_PA29) // SPI 1 Peripheral Chip Select 3 -#define AT91C_PIO_PA3 ((unsigned int) 1 << 3) // Pin Controlled by PA3 -#define AT91C_PA3_RTS0 ((unsigned int) AT91C_PIO_PA3) // USART 0 Ready To Send -#define AT91C_PA3_NPCS12 ((unsigned int) AT91C_PIO_PA3) // SPI 1 Peripheral Chip Select 2 -#define AT91C_PIO_PA30 ((unsigned int) 1 << 30) // Pin Controlled by PA30 -#define AT91C_PA30_IRQ0 ((unsigned int) AT91C_PIO_PA30) // External Interrupt 0 -#define AT91C_PA30_PCK2 ((unsigned int) AT91C_PIO_PA30) // PMC Programmable Clock Output 2 -#define AT91C_PIO_PA4 ((unsigned int) 1 << 4) // Pin Controlled by PA4 -#define AT91C_PA4_CTS0 ((unsigned int) AT91C_PIO_PA4) // USART 0 Clear To Send -#define AT91C_PA4_NPCS13 ((unsigned int) AT91C_PIO_PA4) // SPI 1 Peripheral Chip Select 3 -#define AT91C_PIO_PA5 ((unsigned int) 1 << 5) // Pin Controlled by PA5 -#define AT91C_PA5_RXD1 ((unsigned int) AT91C_PIO_PA5) // USART 1 Receive Data -#define AT91C_PIO_PA6 ((unsigned int) 1 << 6) // Pin Controlled by PA6 -#define AT91C_PA6_TXD1 ((unsigned int) AT91C_PIO_PA6) // USART 1 Transmit Data -#define AT91C_PIO_PA7 ((unsigned int) 1 << 7) // Pin Controlled by PA7 -#define AT91C_PA7_SCK1 ((unsigned int) AT91C_PIO_PA7) // USART 1 Serial Clock -#define AT91C_PA7_NPCS01 ((unsigned int) AT91C_PIO_PA7) // SPI 0 Peripheral Chip Select 1 -#define AT91C_PIO_PA8 ((unsigned int) 1 << 8) // Pin Controlled by PA8 -#define AT91C_PA8_RTS1 ((unsigned int) AT91C_PIO_PA8) // USART 1 Ready To Send -#define AT91C_PA8_NPCS02 ((unsigned int) AT91C_PIO_PA8) // SPI 0 Peripheral Chip Select 2 -#define AT91C_PIO_PA9 ((unsigned int) 1 << 9) // Pin Controlled by PA9 -#define AT91C_PA9_CTS1 ((unsigned int) AT91C_PIO_PA9) // USART 1 Clear To Send -#define AT91C_PA9_NPCS03 ((unsigned int) AT91C_PIO_PA9) // SPI 0 Peripheral Chip Select 3 -#define AT91C_PIO_PB0 ((unsigned int) 1 << 0) // Pin Controlled by PB0 -#define AT91C_PB0_ETXCK_EREFCK ((unsigned int) AT91C_PIO_PB0) // Ethernet MAC Transmit Clock/Reference Clock -#define AT91C_PB0_PCK0 ((unsigned int) AT91C_PIO_PB0) // PMC Programmable Clock Output 0 -#define AT91C_PIO_PB1 ((unsigned int) 1 << 1) // Pin Controlled by PB1 -#define AT91C_PB1_ETXEN ((unsigned int) AT91C_PIO_PB1) // Ethernet MAC Transmit Enable -#define AT91C_PIO_PB10 ((unsigned int) 1 << 10) // Pin Controlled by PB10 -#define AT91C_PB10_ETX2 ((unsigned int) AT91C_PIO_PB10) // Ethernet MAC Transmit Data 2 -#define AT91C_PB10_NPCS11 ((unsigned int) AT91C_PIO_PB10) // SPI 1 Peripheral Chip Select 1 -#define AT91C_PIO_PB11 ((unsigned int) 1 << 11) // Pin Controlled by PB11 -#define AT91C_PB11_ETX3 ((unsigned int) AT91C_PIO_PB11) // Ethernet MAC Transmit Data 3 -#define AT91C_PB11_NPCS12 ((unsigned int) AT91C_PIO_PB11) // SPI 1 Peripheral Chip Select 2 -#define AT91C_PIO_PB12 ((unsigned int) 1 << 12) // Pin Controlled by PB12 -#define AT91C_PB12_ETXER ((unsigned int) AT91C_PIO_PB12) // Ethernet MAC Transmikt Coding Error -#define AT91C_PB12_TCLK0 ((unsigned int) AT91C_PIO_PB12) // Timer Counter 0 external clock input -#define AT91C_PIO_PB13 ((unsigned int) 1 << 13) // Pin Controlled by PB13 -#define AT91C_PB13_ERX2 ((unsigned int) AT91C_PIO_PB13) // Ethernet MAC Receive Data 2 -#define AT91C_PB13_NPCS01 ((unsigned int) AT91C_PIO_PB13) // SPI 0 Peripheral Chip Select 1 -#define AT91C_PIO_PB14 ((unsigned int) 1 << 14) // Pin Controlled by PB14 -#define AT91C_PB14_ERX3 ((unsigned int) AT91C_PIO_PB14) // Ethernet MAC Receive Data 3 -#define AT91C_PB14_NPCS02 ((unsigned int) AT91C_PIO_PB14) // SPI 0 Peripheral Chip Select 2 -#define AT91C_PIO_PB15 ((unsigned int) 1 << 15) // Pin Controlled by PB15 -#define AT91C_PB15_ERXDV ((unsigned int) AT91C_PIO_PB15) // Ethernet MAC Receive Data Valid -#define AT91C_PIO_PB16 ((unsigned int) 1 << 16) // Pin Controlled by PB16 -#define AT91C_PB16_ECOL ((unsigned int) AT91C_PIO_PB16) // Ethernet MAC Collision Detected -#define AT91C_PB16_NPCS13 ((unsigned int) AT91C_PIO_PB16) // SPI 1 Peripheral Chip Select 3 -#define AT91C_PIO_PB17 ((unsigned int) 1 << 17) // Pin Controlled by PB17 -#define AT91C_PB17_ERXCK ((unsigned int) AT91C_PIO_PB17) // Ethernet MAC Receive Clock -#define AT91C_PB17_NPCS03 ((unsigned int) AT91C_PIO_PB17) // SPI 0 Peripheral Chip Select 3 -#define AT91C_PIO_PB18 ((unsigned int) 1 << 18) // Pin Controlled by PB18 -#define AT91C_PB18_EF100 ((unsigned int) AT91C_PIO_PB18) // Ethernet MAC Force 100 Mbits/sec -#define AT91C_PB18_ADTRG ((unsigned int) AT91C_PIO_PB18) // ADC External Trigger -#define AT91C_PIO_PB19 ((unsigned int) 1 << 19) // Pin Controlled by PB19 -#define AT91C_PB19_PWM0 ((unsigned int) AT91C_PIO_PB19) // PWM Channel 0 -#define AT91C_PB19_TCLK1 ((unsigned int) AT91C_PIO_PB19) // Timer Counter 1 external clock input -#define AT91C_PIO_PB2 ((unsigned int) 1 << 2) // Pin Controlled by PB2 -#define AT91C_PB2_ETX0 ((unsigned int) AT91C_PIO_PB2) // Ethernet MAC Transmit Data 0 -#define AT91C_PIO_PB20 ((unsigned int) 1 << 20) // Pin Controlled by PB20 -#define AT91C_PB20_PWM1 ((unsigned int) AT91C_PIO_PB20) // PWM Channel 1 -#define AT91C_PB20_PCK0 ((unsigned int) AT91C_PIO_PB20) // PMC Programmable Clock Output 0 -#define AT91C_PIO_PB21 ((unsigned int) 1 << 21) // Pin Controlled by PB21 -#define AT91C_PB21_PWM2 ((unsigned int) AT91C_PIO_PB21) // PWM Channel 2 -#define AT91C_PB21_PCK1 ((unsigned int) AT91C_PIO_PB21) // PMC Programmable Clock Output 1 -#define AT91C_PIO_PB22 ((unsigned int) 1 << 22) // Pin Controlled by PB22 -#define AT91C_PB22_PWM3 ((unsigned int) AT91C_PIO_PB22) // PWM Channel 3 -#define AT91C_PB22_PCK2 ((unsigned int) AT91C_PIO_PB22) // PMC Programmable Clock Output 2 -#define AT91C_PIO_PB23 ((unsigned int) 1 << 23) // Pin Controlled by PB23 -#define AT91C_PB23_TIOA0 ((unsigned int) AT91C_PIO_PB23) // Timer Counter 0 Multipurpose Timer I/O Pin A -#define AT91C_PB23_DCD1 ((unsigned int) AT91C_PIO_PB23) // USART 1 Data Carrier Detect -#define AT91C_PIO_PB24 ((unsigned int) 1 << 24) // Pin Controlled by PB24 -#define AT91C_PB24_TIOB0 ((unsigned int) AT91C_PIO_PB24) // Timer Counter 0 Multipurpose Timer I/O Pin B -#define AT91C_PB24_DSR1 ((unsigned int) AT91C_PIO_PB24) // USART 1 Data Set ready -#define AT91C_PIO_PB25 ((unsigned int) 1 << 25) // Pin Controlled by PB25 -#define AT91C_PB25_TIOA1 ((unsigned int) AT91C_PIO_PB25) // Timer Counter 1 Multipurpose Timer I/O Pin A -#define AT91C_PB25_DTR1 ((unsigned int) AT91C_PIO_PB25) // USART 1 Data Terminal ready -#define AT91C_PIO_PB26 ((unsigned int) 1 << 26) // Pin Controlled by PB26 -#define AT91C_PB26_TIOB1 ((unsigned int) AT91C_PIO_PB26) // Timer Counter 1 Multipurpose Timer I/O Pin B -#define AT91C_PB26_RI1 ((unsigned int) AT91C_PIO_PB26) // USART 1 Ring Indicator -#define AT91C_PIO_PB27 ((unsigned int) 1 << 27) // Pin Controlled by PB27 -#define AT91C_PB27_TIOA2 ((unsigned int) AT91C_PIO_PB27) // Timer Counter 2 Multipurpose Timer I/O Pin A -#define AT91C_PB27_PWM0 ((unsigned int) AT91C_PIO_PB27) // PWM Channel 0 -#define AT91C_PIO_PB28 ((unsigned int) 1 << 28) // Pin Controlled by PB28 -#define AT91C_PB28_TIOB2 ((unsigned int) AT91C_PIO_PB28) // Timer Counter 2 Multipurpose Timer I/O Pin B -#define AT91C_PB28_PWM1 ((unsigned int) AT91C_PIO_PB28) // PWM Channel 1 -#define AT91C_PIO_PB29 ((unsigned int) 1 << 29) // Pin Controlled by PB29 -#define AT91C_PB29_PCK1 ((unsigned int) AT91C_PIO_PB29) // PMC Programmable Clock Output 1 -#define AT91C_PB29_PWM2 ((unsigned int) AT91C_PIO_PB29) // PWM Channel 2 -#define AT91C_PIO_PB3 ((unsigned int) 1 << 3) // Pin Controlled by PB3 -#define AT91C_PB3_ETX1 ((unsigned int) AT91C_PIO_PB3) // Ethernet MAC Transmit Data 1 -#define AT91C_PIO_PB30 ((unsigned int) 1 << 30) // Pin Controlled by PB30 -#define AT91C_PB30_PCK2 ((unsigned int) AT91C_PIO_PB30) // PMC Programmable Clock Output 2 -#define AT91C_PB30_PWM3 ((unsigned int) AT91C_PIO_PB30) // PWM Channel 3 -#define AT91C_PIO_PB4 ((unsigned int) 1 << 4) // Pin Controlled by PB4 -#define AT91C_PB4_ECRS_ECRSDV ((unsigned int) AT91C_PIO_PB4) // Ethernet MAC Carrier Sense/Carrier Sense and Data Valid -#define AT91C_PIO_PB5 ((unsigned int) 1 << 5) // Pin Controlled by PB5 -#define AT91C_PB5_ERX0 ((unsigned int) AT91C_PIO_PB5) // Ethernet MAC Receive Data 0 -#define AT91C_PIO_PB6 ((unsigned int) 1 << 6) // Pin Controlled by PB6 -#define AT91C_PB6_ERX1 ((unsigned int) AT91C_PIO_PB6) // Ethernet MAC Receive Data 1 -#define AT91C_PIO_PB7 ((unsigned int) 1 << 7) // Pin Controlled by PB7 -#define AT91C_PB7_ERXER ((unsigned int) AT91C_PIO_PB7) // Ethernet MAC Receive Error -#define AT91C_PIO_PB8 ((unsigned int) 1 << 8) // Pin Controlled by PB8 -#define AT91C_PB8_EMDC ((unsigned int) AT91C_PIO_PB8) // Ethernet MAC Management Data Clock -#define AT91C_PIO_PB9 ((unsigned int) 1 << 9) // Pin Controlled by PB9 -#define AT91C_PB9_EMDIO ((unsigned int) AT91C_PIO_PB9) // Ethernet MAC Management Data Input/Output - -// ***************************************************************************** -// PERIPHERAL ID DEFINITIONS FOR AT91SAM7X256 -// ***************************************************************************** -#define AT91C_ID_FIQ ((unsigned int) 0) // Advanced Interrupt Controller (FIQ) -#define AT91C_ID_SYS ((unsigned int) 1) // System Peripheral -#define AT91C_ID_PIOA ((unsigned int) 2) // Parallel IO Controller A -#define AT91C_ID_PIOB ((unsigned int) 3) // Parallel IO Controller B -#define AT91C_ID_SPI0 ((unsigned int) 4) // Serial Peripheral Interface 0 -#define AT91C_ID_SPI1 ((unsigned int) 5) // Serial Peripheral Interface 1 -#define AT91C_ID_US0 ((unsigned int) 6) // USART 0 -#define AT91C_ID_US1 ((unsigned int) 7) // USART 1 -#define AT91C_ID_SSC ((unsigned int) 8) // Serial Synchronous Controller -#define AT91C_ID_TWI ((unsigned int) 9) // Two-Wire Interface -#define AT91C_ID_PWMC ((unsigned int) 10) // PWM Controller -#define AT91C_ID_UDP ((unsigned int) 11) // USB Device Port -#define AT91C_ID_TC0 ((unsigned int) 12) // Timer Counter 0 -#define AT91C_ID_TC1 ((unsigned int) 13) // Timer Counter 1 -#define AT91C_ID_TC2 ((unsigned int) 14) // Timer Counter 2 -#define AT91C_ID_CAN ((unsigned int) 15) // Control Area Network Controller -#define AT91C_ID_EMAC ((unsigned int) 16) // Ethernet MAC -#define AT91C_ID_ADC ((unsigned int) 17) // Analog-to-Digital Converter -#define AT91C_ID_AES ((unsigned int) 18) // Advanced Encryption Standard 128-bit -#define AT91C_ID_TDES ((unsigned int) 19) // Triple Data Encryption Standard -#define AT91C_ID_20_Reserved ((unsigned int) 20) // Reserved -#define AT91C_ID_21_Reserved ((unsigned int) 21) // Reserved -#define AT91C_ID_22_Reserved ((unsigned int) 22) // Reserved -#define AT91C_ID_23_Reserved ((unsigned int) 23) // Reserved -#define AT91C_ID_24_Reserved ((unsigned int) 24) // Reserved -#define AT91C_ID_25_Reserved ((unsigned int) 25) // Reserved -#define AT91C_ID_26_Reserved ((unsigned int) 26) // Reserved -#define AT91C_ID_27_Reserved ((unsigned int) 27) // Reserved -#define AT91C_ID_28_Reserved ((unsigned int) 28) // Reserved -#define AT91C_ID_29_Reserved ((unsigned int) 29) // Reserved -#define AT91C_ID_IRQ0 ((unsigned int) 30) // Advanced Interrupt Controller (IRQ0) -#define AT91C_ID_IRQ1 ((unsigned int) 31) // Advanced Interrupt Controller (IRQ1) - -// ***************************************************************************** -// BASE ADDRESS DEFINITIONS FOR AT91SAM7X256 -// ***************************************************************************** -#define AT91C_BASE_SYS ((AT91PS_SYS) 0xFFFFF000) // (SYS) Base Address -#define AT91C_BASE_AIC ((AT91PS_AIC) 0xFFFFF000) // (AIC) Base Address -#define AT91C_BASE_PDC_DBGU ((AT91PS_PDC) 0xFFFFF300) // (PDC_DBGU) Base Address -#define AT91C_BASE_DBGU ((AT91PS_DBGU) 0xFFFFF200) // (DBGU) Base Address -#define AT91C_BASE_PIOA ((AT91PS_PIO) 0xFFFFF400) // (PIOA) Base Address -#define AT91C_BASE_PIOB ((AT91PS_PIO) 0xFFFFF600) // (PIOB) Base Address -#define AT91C_BASE_CKGR ((AT91PS_CKGR) 0xFFFFFC20) // (CKGR) Base Address -#define AT91C_BASE_PMC ((AT91PS_PMC) 0xFFFFFC00) // (PMC) Base Address -#define AT91C_BASE_RSTC ((AT91PS_RSTC) 0xFFFFFD00) // (RSTC) Base Address -#define AT91C_BASE_RTTC ((AT91PS_RTTC) 0xFFFFFD20) // (RTTC) Base Address -#define AT91C_BASE_PITC ((AT91PS_PITC) 0xFFFFFD30) // (PITC) Base Address -#define AT91C_BASE_WDTC ((AT91PS_WDTC) 0xFFFFFD40) // (WDTC) Base Address -#define AT91C_BASE_VREG ((AT91PS_VREG) 0xFFFFFD60) // (VREG) Base Address -#define AT91C_BASE_MC ((AT91PS_MC) 0xFFFFFF00) // (MC) Base Address -#define AT91C_BASE_PDC_SPI1 ((AT91PS_PDC) 0xFFFE4100) // (PDC_SPI1) Base Address -#define AT91C_BASE_SPI1 ((AT91PS_SPI) 0xFFFE4000) // (SPI1) Base Address -#define AT91C_BASE_PDC_SPI0 ((AT91PS_PDC) 0xFFFE0100) // (PDC_SPI0) Base Address -#define AT91C_BASE_SPI0 ((AT91PS_SPI) 0xFFFE0000) // (SPI0) Base Address -#define AT91C_BASE_PDC_US1 ((AT91PS_PDC) 0xFFFC4100) // (PDC_US1) Base Address -#define AT91C_BASE_US1 ((AT91PS_USART) 0xFFFC4000) // (US1) Base Address -#define AT91C_BASE_PDC_US0 ((AT91PS_PDC) 0xFFFC0100) // (PDC_US0) Base Address -#define AT91C_BASE_US0 ((AT91PS_USART) 0xFFFC0000) // (US0) Base Address -#define AT91C_BASE_PDC_SSC ((AT91PS_PDC) 0xFFFD4100) // (PDC_SSC) Base Address -#define AT91C_BASE_SSC ((AT91PS_SSC) 0xFFFD4000) // (SSC) Base Address -#define AT91C_BASE_TWI ((AT91PS_TWI) 0xFFFB8000) // (TWI) Base Address -#define AT91C_BASE_PWMC_CH3 ((AT91PS_PWMC_CH) 0xFFFCC260) // (PWMC_CH3) Base Address -#define AT91C_BASE_PWMC_CH2 ((AT91PS_PWMC_CH) 0xFFFCC240) // (PWMC_CH2) Base Address -#define AT91C_BASE_PWMC_CH1 ((AT91PS_PWMC_CH) 0xFFFCC220) // (PWMC_CH1) Base Address -#define AT91C_BASE_PWMC_CH0 ((AT91PS_PWMC_CH) 0xFFFCC200) // (PWMC_CH0) Base Address -#define AT91C_BASE_PWMC ((AT91PS_PWMC) 0xFFFCC000) // (PWMC) Base Address -#define AT91C_BASE_UDP ((AT91PS_UDP) 0xFFFB0000) // (UDP) Base Address -#define AT91C_BASE_TC0 ((AT91PS_TC) 0xFFFA0000) // (TC0) Base Address -#define AT91C_BASE_TC1 ((AT91PS_TC) 0xFFFA0040) // (TC1) Base Address -#define AT91C_BASE_TC2 ((AT91PS_TC) 0xFFFA0080) // (TC2) Base Address -#define AT91C_BASE_TCB ((AT91PS_TCB) 0xFFFA0000) // (TCB) Base Address -#define AT91C_BASE_CAN_MB0 ((AT91PS_CAN_MB) 0xFFFD0200) // (CAN_MB0) Base Address -#define AT91C_BASE_CAN_MB1 ((AT91PS_CAN_MB) 0xFFFD0220) // (CAN_MB1) Base Address -#define AT91C_BASE_CAN_MB2 ((AT91PS_CAN_MB) 0xFFFD0240) // (CAN_MB2) Base Address -#define AT91C_BASE_CAN_MB3 ((AT91PS_CAN_MB) 0xFFFD0260) // (CAN_MB3) Base Address -#define AT91C_BASE_CAN_MB4 ((AT91PS_CAN_MB) 0xFFFD0280) // (CAN_MB4) Base Address -#define AT91C_BASE_CAN_MB5 ((AT91PS_CAN_MB) 0xFFFD02A0) // (CAN_MB5) Base Address -#define AT91C_BASE_CAN_MB6 ((AT91PS_CAN_MB) 0xFFFD02C0) // (CAN_MB6) Base Address -#define AT91C_BASE_CAN_MB7 ((AT91PS_CAN_MB) 0xFFFD02E0) // (CAN_MB7) Base Address -#define AT91C_BASE_CAN ((AT91PS_CAN) 0xFFFD0000) // (CAN) Base Address -#define AT91C_BASE_EMAC ((AT91PS_EMAC) 0xFFFDC000) // (EMAC) Base Address -#define AT91C_BASE_PDC_ADC ((AT91PS_PDC) 0xFFFD8100) // (PDC_ADC) Base Address -#define AT91C_BASE_ADC ((AT91PS_ADC) 0xFFFD8000) // (ADC) Base Address -#define AT91C_BASE_PDC_AES ((AT91PS_PDC) 0xFFFA4100) // (PDC_AES) Base Address -#define AT91C_BASE_AES ((AT91PS_AES) 0xFFFA4000) // (AES) Base Address -#define AT91C_BASE_PDC_TDES ((AT91PS_PDC) 0xFFFA8100) // (PDC_TDES) Base Address -#define AT91C_BASE_TDES ((AT91PS_TDES) 0xFFFA8000) // (TDES) Base Address - -// ***************************************************************************** -// MEMORY MAPPING DEFINITIONS FOR AT91SAM7X256 -// ***************************************************************************** -#define AT91C_ISRAM ((char *) 0x00200000) // Internal SRAM base address -#define AT91C_ISRAM_SIZE ((unsigned int) 0x00010000) // Internal SRAM size in byte (64 Kbyte) -#define AT91C_IFLASH ((char *) 0x00100000) // Internal ROM base address -#define AT91C_IFLASH_SIZE ((unsigned int) 0x00040000) // Internal ROM size in byte (256 Kbyte) - -#define AT91F_AIC_ConfigureIt( irq_id, priority, src_type, newHandler ) \ -{ \ - unsigned int mask ; \ - \ - mask = 0x1 << irq_id; \ - /* Disable the interrupt on the interrupt controller */ \ - AT91C_BASE_AIC->AIC_IDCR = mask ; \ - /* Save the interrupt handler routine pointer and the interrupt priority */ \ - AT91C_BASE_AIC->AIC_SVR[irq_id] = (unsigned int) newHandler ; \ - /* Store the Source Mode Register */ \ - AT91C_BASE_AIC->AIC_SMR[irq_id] = src_type | priority ; \ - /* Clear the interrupt on the interrupt controller */ \ - AT91C_BASE_AIC->AIC_ICCR = mask ; \ -} - - -#endif +typedef volatile unsigned int AT91_REG; /* Hardware register definition */ + +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR System Peripherals */ +/* ***************************************************************************** */ +typedef struct _AT91S_SYS +{ + AT91_REG AIC_SMR[ 32 ]; /* Source Mode Register */ + AT91_REG AIC_SVR[ 32 ]; /* Source Vector Register */ + AT91_REG AIC_IVR; /* IRQ Vector Register */ + AT91_REG AIC_FVR; /* FIQ Vector Register */ + AT91_REG AIC_ISR; /* Interrupt Status Register */ + AT91_REG AIC_IPR; /* Interrupt Pending Register */ + AT91_REG AIC_IMR; /* Interrupt Mask Register */ + AT91_REG AIC_CISR; /* Core Interrupt Status Register */ + AT91_REG Reserved0[ 2 ]; /* */ + AT91_REG AIC_IECR; /* Interrupt Enable Command Register */ + AT91_REG AIC_IDCR; /* Interrupt Disable Command Register */ + AT91_REG AIC_ICCR; /* Interrupt Clear Command Register */ + AT91_REG AIC_ISCR; /* Interrupt Set Command Register */ + AT91_REG AIC_EOICR; /* End of Interrupt Command Register */ + AT91_REG AIC_SPU; /* Spurious Vector Register */ + AT91_REG AIC_DCR; /* Debug Control Register (Protect) */ + AT91_REG Reserved1[ 1 ]; /* */ + AT91_REG AIC_FFER; /* Fast Forcing Enable Register */ + AT91_REG AIC_FFDR; /* Fast Forcing Disable Register */ + AT91_REG AIC_FFSR; /* Fast Forcing Status Register */ + AT91_REG Reserved2[ 45 ]; /* */ + AT91_REG DBGU_CR; /* Control Register */ + AT91_REG DBGU_MR; /* Mode Register */ + AT91_REG DBGU_IER; /* Interrupt Enable Register */ + AT91_REG DBGU_IDR; /* Interrupt Disable Register */ + AT91_REG DBGU_IMR; /* Interrupt Mask Register */ + AT91_REG DBGU_CSR; /* Channel Status Register */ + AT91_REG DBGU_RHR; /* Receiver Holding Register */ + AT91_REG DBGU_THR; /* Transmitter Holding Register */ + AT91_REG DBGU_BRGR; /* Baud Rate Generator Register */ + AT91_REG Reserved3[ 7 ]; /* */ + AT91_REG DBGU_CIDR; /* Chip ID Register */ + AT91_REG DBGU_EXID; /* Chip ID Extension Register */ + AT91_REG DBGU_FNTR; /* Force NTRST Register */ + AT91_REG Reserved4[ 45 ]; /* */ + AT91_REG DBGU_RPR; /* Receive Pointer Register */ + AT91_REG DBGU_RCR; /* Receive Counter Register */ + AT91_REG DBGU_TPR; /* Transmit Pointer Register */ + AT91_REG DBGU_TCR; /* Transmit Counter Register */ + AT91_REG DBGU_RNPR; /* Receive Next Pointer Register */ + AT91_REG DBGU_RNCR; /* Receive Next Counter Register */ + AT91_REG DBGU_TNPR; /* Transmit Next Pointer Register */ + AT91_REG DBGU_TNCR; /* Transmit Next Counter Register */ + AT91_REG DBGU_PTCR; /* PDC Transfer Control Register */ + AT91_REG DBGU_PTSR; /* PDC Transfer Status Register */ + AT91_REG Reserved5[ 54 ]; /* */ + AT91_REG PIOA_PER; /* PIO Enable Register */ + AT91_REG PIOA_PDR; /* PIO Disable Register */ + AT91_REG PIOA_PSR; /* PIO Status Register */ + AT91_REG Reserved6[ 1 ]; /* */ + AT91_REG PIOA_OER; /* Output Enable Register */ + AT91_REG PIOA_ODR; /* Output Disable Registerr */ + AT91_REG PIOA_OSR; /* Output Status Register */ + AT91_REG Reserved7[ 1 ]; /* */ + AT91_REG PIOA_IFER; /* Input Filter Enable Register */ + AT91_REG PIOA_IFDR; /* Input Filter Disable Register */ + AT91_REG PIOA_IFSR; /* Input Filter Status Register */ + AT91_REG Reserved8[ 1 ]; /* */ + AT91_REG PIOA_SODR; /* Set Output Data Register */ + AT91_REG PIOA_CODR; /* Clear Output Data Register */ + AT91_REG PIOA_ODSR; /* Output Data Status Register */ + AT91_REG PIOA_PDSR; /* Pin Data Status Register */ + AT91_REG PIOA_IER; /* Interrupt Enable Register */ + AT91_REG PIOA_IDR; /* Interrupt Disable Register */ + AT91_REG PIOA_IMR; /* Interrupt Mask Register */ + AT91_REG PIOA_ISR; /* Interrupt Status Register */ + AT91_REG PIOA_MDER; /* Multi-driver Enable Register */ + AT91_REG PIOA_MDDR; /* Multi-driver Disable Register */ + AT91_REG PIOA_MDSR; /* Multi-driver Status Register */ + AT91_REG Reserved9[ 1 ]; /* */ + AT91_REG PIOA_PPUDR; /* Pull-up Disable Register */ + AT91_REG PIOA_PPUER; /* Pull-up Enable Register */ + AT91_REG PIOA_PPUSR; /* Pull-up Status Register */ + AT91_REG Reserved10[ 1 ]; /* */ + AT91_REG PIOA_ASR; /* Select A Register */ + AT91_REG PIOA_BSR; /* Select B Register */ + AT91_REG PIOA_ABSR; /* AB Select Status Register */ + AT91_REG Reserved11[ 9 ]; /* */ + AT91_REG PIOA_OWER; /* Output Write Enable Register */ + AT91_REG PIOA_OWDR; /* Output Write Disable Register */ + AT91_REG PIOA_OWSR; /* Output Write Status Register */ + AT91_REG Reserved12[ 85 ]; /* */ + AT91_REG PIOB_PER; /* PIO Enable Register */ + AT91_REG PIOB_PDR; /* PIO Disable Register */ + AT91_REG PIOB_PSR; /* PIO Status Register */ + AT91_REG Reserved13[ 1 ]; /* */ + AT91_REG PIOB_OER; /* Output Enable Register */ + AT91_REG PIOB_ODR; /* Output Disable Registerr */ + AT91_REG PIOB_OSR; /* Output Status Register */ + AT91_REG Reserved14[ 1 ]; /* */ + AT91_REG PIOB_IFER; /* Input Filter Enable Register */ + AT91_REG PIOB_IFDR; /* Input Filter Disable Register */ + AT91_REG PIOB_IFSR; /* Input Filter Status Register */ + AT91_REG Reserved15[ 1 ]; /* */ + AT91_REG PIOB_SODR; /* Set Output Data Register */ + AT91_REG PIOB_CODR; /* Clear Output Data Register */ + AT91_REG PIOB_ODSR; /* Output Data Status Register */ + AT91_REG PIOB_PDSR; /* Pin Data Status Register */ + AT91_REG PIOB_IER; /* Interrupt Enable Register */ + AT91_REG PIOB_IDR; /* Interrupt Disable Register */ + AT91_REG PIOB_IMR; /* Interrupt Mask Register */ + AT91_REG PIOB_ISR; /* Interrupt Status Register */ + AT91_REG PIOB_MDER; /* Multi-driver Enable Register */ + AT91_REG PIOB_MDDR; /* Multi-driver Disable Register */ + AT91_REG PIOB_MDSR; /* Multi-driver Status Register */ + AT91_REG Reserved16[ 1 ]; /* */ + AT91_REG PIOB_PPUDR; /* Pull-up Disable Register */ + AT91_REG PIOB_PPUER; /* Pull-up Enable Register */ + AT91_REG PIOB_PPUSR; /* Pull-up Status Register */ + AT91_REG Reserved17[ 1 ]; /* */ + AT91_REG PIOB_ASR; /* Select A Register */ + AT91_REG PIOB_BSR; /* Select B Register */ + AT91_REG PIOB_ABSR; /* AB Select Status Register */ + AT91_REG Reserved18[ 9 ]; /* */ + AT91_REG PIOB_OWER; /* Output Write Enable Register */ + AT91_REG PIOB_OWDR; /* Output Write Disable Register */ + AT91_REG PIOB_OWSR; /* Output Write Status Register */ + AT91_REG Reserved19[ 341 ]; /* */ + AT91_REG PMC_SCER; /* System Clock Enable Register */ + AT91_REG PMC_SCDR; /* System Clock Disable Register */ + AT91_REG PMC_SCSR; /* System Clock Status Register */ + AT91_REG Reserved20[ 1 ]; /* */ + AT91_REG PMC_PCER; /* Peripheral Clock Enable Register */ + AT91_REG PMC_PCDR; /* Peripheral Clock Disable Register */ + AT91_REG PMC_PCSR; /* Peripheral Clock Status Register */ + AT91_REG Reserved21[ 1 ]; /* */ + AT91_REG PMC_MOR; /* Main Oscillator Register */ + AT91_REG PMC_MCFR; /* Main Clock Frequency Register */ + AT91_REG Reserved22[ 1 ]; /* */ + AT91_REG PMC_PLLR; /* PLL Register */ + AT91_REG PMC_MCKR; /* Master Clock Register */ + AT91_REG Reserved23[ 3 ]; /* */ + AT91_REG PMC_PCKR[ 4 ]; /* Programmable Clock Register */ + AT91_REG Reserved24[ 4 ]; /* */ + AT91_REG PMC_IER; /* Interrupt Enable Register */ + AT91_REG PMC_IDR; /* Interrupt Disable Register */ + AT91_REG PMC_SR; /* Status Register */ + AT91_REG PMC_IMR; /* Interrupt Mask Register */ + AT91_REG Reserved25[ 36 ]; /* */ + AT91_REG RSTC_RCR; /* Reset Control Register */ + AT91_REG RSTC_RSR; /* Reset Status Register */ + AT91_REG RSTC_RMR; /* Reset Mode Register */ + AT91_REG Reserved26[ 5 ]; /* */ + AT91_REG RTTC_RTMR; /* Real-time Mode Register */ + AT91_REG RTTC_RTAR; /* Real-time Alarm Register */ + AT91_REG RTTC_RTVR; /* Real-time Value Register */ + AT91_REG RTTC_RTSR; /* Real-time Status Register */ + AT91_REG PITC_PIMR; /* Period Interval Mode Register */ + AT91_REG PITC_PISR; /* Period Interval Status Register */ + AT91_REG PITC_PIVR; /* Period Interval Value Register */ + AT91_REG PITC_PIIR; /* Period Interval Image Register */ + AT91_REG WDTC_WDCR; /* Watchdog Control Register */ + AT91_REG WDTC_WDMR; /* Watchdog Mode Register */ + AT91_REG WDTC_WDSR; /* Watchdog Status Register */ + AT91_REG Reserved27[ 5 ]; /* */ + AT91_REG VREG_MR; /* Voltage Regulator Mode Register */ +} AT91S_SYS, * AT91PS_SYS; + + +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR Advanced Interrupt Controller */ +/* ***************************************************************************** */ +typedef struct _AT91S_AIC +{ + AT91_REG AIC_SMR[ 32 ]; /* Source Mode Register */ + AT91_REG AIC_SVR[ 32 ]; /* Source Vector Register */ + AT91_REG AIC_IVR; /* IRQ Vector Register */ + AT91_REG AIC_FVR; /* FIQ Vector Register */ + AT91_REG AIC_ISR; /* Interrupt Status Register */ + AT91_REG AIC_IPR; /* Interrupt Pending Register */ + AT91_REG AIC_IMR; /* Interrupt Mask Register */ + AT91_REG AIC_CISR; /* Core Interrupt Status Register */ + AT91_REG Reserved0[ 2 ]; /* */ + AT91_REG AIC_IECR; /* Interrupt Enable Command Register */ + AT91_REG AIC_IDCR; /* Interrupt Disable Command Register */ + AT91_REG AIC_ICCR; /* Interrupt Clear Command Register */ + AT91_REG AIC_ISCR; /* Interrupt Set Command Register */ + AT91_REG AIC_EOICR; /* End of Interrupt Command Register */ + AT91_REG AIC_SPU; /* Spurious Vector Register */ + AT91_REG AIC_DCR; /* Debug Control Register (Protect) */ + AT91_REG Reserved1[ 1 ]; /* */ + AT91_REG AIC_FFER; /* Fast Forcing Enable Register */ + AT91_REG AIC_FFDR; /* Fast Forcing Disable Register */ + AT91_REG AIC_FFSR; /* Fast Forcing Status Register */ +} AT91S_AIC, * AT91PS_AIC; + +/* -------- AIC_SMR : (AIC Offset: 0x0) Control Register -------- */ +#define AT91C_AIC_PRIOR ( ( unsigned int ) 0x7 << 0 ) /* (AIC) Priority Level */ +#define AT91C_AIC_PRIOR_LOWEST ( ( unsigned int ) 0x0 ) /* (AIC) Lowest priority level */ +#define AT91C_AIC_PRIOR_HIGHEST ( ( unsigned int ) 0x7 ) /* (AIC) Highest priority level */ +#define AT91C_AIC_SRCTYPE ( ( unsigned int ) 0x3 << 5 ) /* (AIC) Interrupt Source Type */ +#define AT91C_AIC_SRCTYPE_INT_HIGH_LEVEL ( ( unsigned int ) 0x0 << 5 ) /* (AIC) Internal Sources Code Label High-level Sensitive */ +#define AT91C_AIC_SRCTYPE_EXT_LOW_LEVEL ( ( unsigned int ) 0x0 << 5 ) /* (AIC) External Sources Code Label Low-level Sensitive */ +#define AT91C_AIC_SRCTYPE_INT_POSITIVE_EDGE ( ( unsigned int ) 0x1 << 5 ) /* (AIC) Internal Sources Code Label Positive Edge triggered */ +#define AT91C_AIC_SRCTYPE_EXT_NEGATIVE_EDGE ( ( unsigned int ) 0x1 << 5 ) /* (AIC) External Sources Code Label Negative Edge triggered */ +#define AT91C_AIC_SRCTYPE_HIGH_LEVEL ( ( unsigned int ) 0x2 << 5 ) /* (AIC) Internal Or External Sources Code Label High-level Sensitive */ +#define AT91C_AIC_SRCTYPE_POSITIVE_EDGE ( ( unsigned int ) 0x3 << 5 ) /* (AIC) Internal Or External Sources Code Label Positive Edge triggered */ +/* -------- AIC_CISR : (AIC Offset: 0x114) AIC Core Interrupt Status Register -------- */ +#define AT91C_AIC_NFIQ ( ( unsigned int ) 0x1 << 0 ) /* (AIC) NFIQ Status */ +#define AT91C_AIC_NIRQ ( ( unsigned int ) 0x1 << 1 ) /* (AIC) NIRQ Status */ +/* -------- AIC_DCR : (AIC Offset: 0x138) AIC Debug Control Register (Protect) -------- */ +#define AT91C_AIC_DCR_PROT ( ( unsigned int ) 0x1 << 0 ) /* (AIC) Protection Mode */ +#define AT91C_AIC_DCR_GMSK ( ( unsigned int ) 0x1 << 1 ) /* (AIC) General Mask */ + +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR Peripheral DMA Controller */ +/* ***************************************************************************** */ +typedef struct _AT91S_PDC +{ + AT91_REG PDC_RPR; /* Receive Pointer Register */ + AT91_REG PDC_RCR; /* Receive Counter Register */ + AT91_REG PDC_TPR; /* Transmit Pointer Register */ + AT91_REG PDC_TCR; /* Transmit Counter Register */ + AT91_REG PDC_RNPR; /* Receive Next Pointer Register */ + AT91_REG PDC_RNCR; /* Receive Next Counter Register */ + AT91_REG PDC_TNPR; /* Transmit Next Pointer Register */ + AT91_REG PDC_TNCR; /* Transmit Next Counter Register */ + AT91_REG PDC_PTCR; /* PDC Transfer Control Register */ + AT91_REG PDC_PTSR; /* PDC Transfer Status Register */ +} AT91S_PDC, * AT91PS_PDC; + +/* -------- PDC_PTCR : (PDC Offset: 0x20) PDC Transfer Control Register -------- */ +#define AT91C_PDC_RXTEN ( ( unsigned int ) 0x1 << 0 ) /* (PDC) Receiver Transfer Enable */ +#define AT91C_PDC_RXTDIS ( ( unsigned int ) 0x1 << 1 ) /* (PDC) Receiver Transfer Disable */ +#define AT91C_PDC_TXTEN ( ( unsigned int ) 0x1 << 8 ) /* (PDC) Transmitter Transfer Enable */ +#define AT91C_PDC_TXTDIS ( ( unsigned int ) 0x1 << 9 ) /* (PDC) Transmitter Transfer Disable */ +/* -------- PDC_PTSR : (PDC Offset: 0x24) PDC Transfer Status Register -------- */ + +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR Debug Unit */ +/* ***************************************************************************** */ +typedef struct _AT91S_DBGU +{ + AT91_REG DBGU_CR; /* Control Register */ + AT91_REG DBGU_MR; /* Mode Register */ + AT91_REG DBGU_IER; /* Interrupt Enable Register */ + AT91_REG DBGU_IDR; /* Interrupt Disable Register */ + AT91_REG DBGU_IMR; /* Interrupt Mask Register */ + AT91_REG DBGU_CSR; /* Channel Status Register */ + AT91_REG DBGU_RHR; /* Receiver Holding Register */ + AT91_REG DBGU_THR; /* Transmitter Holding Register */ + AT91_REG DBGU_BRGR; /* Baud Rate Generator Register */ + AT91_REG Reserved0[ 7 ]; /* */ + AT91_REG DBGU_CIDR; /* Chip ID Register */ + AT91_REG DBGU_EXID; /* Chip ID Extension Register */ + AT91_REG DBGU_FNTR; /* Force NTRST Register */ + AT91_REG Reserved1[ 45 ]; /* */ + AT91_REG DBGU_RPR; /* Receive Pointer Register */ + AT91_REG DBGU_RCR; /* Receive Counter Register */ + AT91_REG DBGU_TPR; /* Transmit Pointer Register */ + AT91_REG DBGU_TCR; /* Transmit Counter Register */ + AT91_REG DBGU_RNPR; /* Receive Next Pointer Register */ + AT91_REG DBGU_RNCR; /* Receive Next Counter Register */ + AT91_REG DBGU_TNPR; /* Transmit Next Pointer Register */ + AT91_REG DBGU_TNCR; /* Transmit Next Counter Register */ + AT91_REG DBGU_PTCR; /* PDC Transfer Control Register */ + AT91_REG DBGU_PTSR; /* PDC Transfer Status Register */ +} AT91S_DBGU, * AT91PS_DBGU; + +/* -------- DBGU_CR : (DBGU Offset: 0x0) Debug Unit Control Register -------- */ +#define AT91C_US_RSTRX ( ( unsigned int ) 0x1 << 2 ) /* (DBGU) Reset Receiver */ +#define AT91C_US_RSTTX ( ( unsigned int ) 0x1 << 3 ) /* (DBGU) Reset Transmitter */ +#define AT91C_US_RXEN ( ( unsigned int ) 0x1 << 4 ) /* (DBGU) Receiver Enable */ +#define AT91C_US_RXDIS ( ( unsigned int ) 0x1 << 5 ) /* (DBGU) Receiver Disable */ +#define AT91C_US_TXEN ( ( unsigned int ) 0x1 << 6 ) /* (DBGU) Transmitter Enable */ +#define AT91C_US_TXDIS ( ( unsigned int ) 0x1 << 7 ) /* (DBGU) Transmitter Disable */ +#define AT91C_US_RSTSTA ( ( unsigned int ) 0x1 << 8 ) /* (DBGU) Reset Status Bits */ +/* -------- DBGU_MR : (DBGU Offset: 0x4) Debug Unit Mode Register -------- */ +#define AT91C_US_PAR ( ( unsigned int ) 0x7 << 9 ) /* (DBGU) Parity type */ +#define AT91C_US_PAR_EVEN ( ( unsigned int ) 0x0 << 9 ) /* (DBGU) Even Parity */ +#define AT91C_US_PAR_ODD ( ( unsigned int ) 0x1 << 9 ) /* (DBGU) Odd Parity */ +#define AT91C_US_PAR_SPACE ( ( unsigned int ) 0x2 << 9 ) /* (DBGU) Parity forced to 0 (Space) */ +#define AT91C_US_PAR_MARK ( ( unsigned int ) 0x3 << 9 ) /* (DBGU) Parity forced to 1 (Mark) */ +#define AT91C_US_PAR_NONE ( ( unsigned int ) 0x4 << 9 ) /* (DBGU) No Parity */ +#define AT91C_US_PAR_MULTI_DROP ( ( unsigned int ) 0x6 << 9 ) /* (DBGU) Multi-drop mode */ +#define AT91C_US_CHMODE ( ( unsigned int ) 0x3 << 14 ) /* (DBGU) Channel Mode */ +#define AT91C_US_CHMODE_NORMAL ( ( unsigned int ) 0x0 << 14 ) /* (DBGU) Normal Mode: The USART channel operates as an RX/TX USART. */ +#define AT91C_US_CHMODE_AUTO ( ( unsigned int ) 0x1 << 14 ) /* (DBGU) Automatic Echo: Receiver Data Input is connected to the TXD pin. */ +#define AT91C_US_CHMODE_LOCAL ( ( unsigned int ) 0x2 << 14 ) /* (DBGU) Local Loopback: Transmitter Output Signal is connected to Receiver Input Signal. */ +#define AT91C_US_CHMODE_REMOTE ( ( unsigned int ) 0x3 << 14 ) /* (DBGU) Remote Loopback: RXD pin is internally connected to TXD pin. */ +/* -------- DBGU_IER : (DBGU Offset: 0x8) Debug Unit Interrupt Enable Register -------- */ +#define AT91C_US_RXRDY ( ( unsigned int ) 0x1 << 0 ) /* (DBGU) RXRDY Interrupt */ +#define AT91C_US_TXRDY ( ( unsigned int ) 0x1 << 1 ) /* (DBGU) TXRDY Interrupt */ +#define AT91C_US_ENDRX ( ( unsigned int ) 0x1 << 3 ) /* (DBGU) End of Receive Transfer Interrupt */ +#define AT91C_US_ENDTX ( ( unsigned int ) 0x1 << 4 ) /* (DBGU) End of Transmit Interrupt */ +#define AT91C_US_OVRE ( ( unsigned int ) 0x1 << 5 ) /* (DBGU) Overrun Interrupt */ +#define AT91C_US_FRAME ( ( unsigned int ) 0x1 << 6 ) /* (DBGU) Framing Error Interrupt */ +#define AT91C_US_PARE ( ( unsigned int ) 0x1 << 7 ) /* (DBGU) Parity Error Interrupt */ +#define AT91C_US_TXEMPTY ( ( unsigned int ) 0x1 << 9 ) /* (DBGU) TXEMPTY Interrupt */ +#define AT91C_US_TXBUFE ( ( unsigned int ) 0x1 << 11 ) /* (DBGU) TXBUFE Interrupt */ +#define AT91C_US_RXBUFF ( ( unsigned int ) 0x1 << 12 ) /* (DBGU) RXBUFF Interrupt */ +#define AT91C_US_COMM_TX ( ( unsigned int ) 0x1 << 30 ) /* (DBGU) COMM_TX Interrupt */ +#define AT91C_US_COMM_RX ( ( unsigned int ) 0x1 << 31 ) /* (DBGU) COMM_RX Interrupt */ +/* -------- DBGU_IDR : (DBGU Offset: 0xc) Debug Unit Interrupt Disable Register -------- */ +/* -------- DBGU_IMR : (DBGU Offset: 0x10) Debug Unit Interrupt Mask Register -------- */ +/* -------- DBGU_CSR : (DBGU Offset: 0x14) Debug Unit Channel Status Register -------- */ +/* -------- DBGU_FNTR : (DBGU Offset: 0x48) Debug Unit FORCE_NTRST Register -------- */ +#define AT91C_US_FORCE_NTRST ( ( unsigned int ) 0x1 << 0 ) /* (DBGU) Force NTRST in JTAG */ + +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR Parallel Input Output Controller */ +/* ***************************************************************************** */ +typedef struct _AT91S_PIO +{ + AT91_REG PIO_PER; /* PIO Enable Register */ + AT91_REG PIO_PDR; /* PIO Disable Register */ + AT91_REG PIO_PSR; /* PIO Status Register */ + AT91_REG Reserved0[ 1 ]; /* */ + AT91_REG PIO_OER; /* Output Enable Register */ + AT91_REG PIO_ODR; /* Output Disable Registerr */ + AT91_REG PIO_OSR; /* Output Status Register */ + AT91_REG Reserved1[ 1 ]; /* */ + AT91_REG PIO_IFER; /* Input Filter Enable Register */ + AT91_REG PIO_IFDR; /* Input Filter Disable Register */ + AT91_REG PIO_IFSR; /* Input Filter Status Register */ + AT91_REG Reserved2[ 1 ]; /* */ + AT91_REG PIO_SODR; /* Set Output Data Register */ + AT91_REG PIO_CODR; /* Clear Output Data Register */ + AT91_REG PIO_ODSR; /* Output Data Status Register */ + AT91_REG PIO_PDSR; /* Pin Data Status Register */ + AT91_REG PIO_IER; /* Interrupt Enable Register */ + AT91_REG PIO_IDR; /* Interrupt Disable Register */ + AT91_REG PIO_IMR; /* Interrupt Mask Register */ + AT91_REG PIO_ISR; /* Interrupt Status Register */ + AT91_REG PIO_MDER; /* Multi-driver Enable Register */ + AT91_REG PIO_MDDR; /* Multi-driver Disable Register */ + AT91_REG PIO_MDSR; /* Multi-driver Status Register */ + AT91_REG Reserved3[ 1 ]; /* */ + AT91_REG PIO_PPUDR; /* Pull-up Disable Register */ + AT91_REG PIO_PPUER; /* Pull-up Enable Register */ + AT91_REG PIO_PPUSR; /* Pull-up Status Register */ + AT91_REG Reserved4[ 1 ]; /* */ + AT91_REG PIO_ASR; /* Select A Register */ + AT91_REG PIO_BSR; /* Select B Register */ + AT91_REG PIO_ABSR; /* AB Select Status Register */ + AT91_REG Reserved5[ 9 ]; /* */ + AT91_REG PIO_OWER; /* Output Write Enable Register */ + AT91_REG PIO_OWDR; /* Output Write Disable Register */ + AT91_REG PIO_OWSR; /* Output Write Status Register */ +} AT91S_PIO, * AT91PS_PIO; + + +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR Clock Generator Controller */ +/* ***************************************************************************** */ +typedef struct _AT91S_CKGR +{ + AT91_REG CKGR_MOR; /* Main Oscillator Register */ + AT91_REG CKGR_MCFR; /* Main Clock Frequency Register */ + AT91_REG Reserved0[ 1 ]; /* */ + AT91_REG CKGR_PLLR; /* PLL Register */ +} AT91S_CKGR, * AT91PS_CKGR; + +/* -------- CKGR_MOR : (CKGR Offset: 0x0) Main Oscillator Register -------- */ +#define AT91C_CKGR_MOSCEN ( ( unsigned int ) 0x1 << 0 ) /* (CKGR) Main Oscillator Enable */ +#define AT91C_CKGR_OSCBYPASS ( ( unsigned int ) 0x1 << 1 ) /* (CKGR) Main Oscillator Bypass */ +#define AT91C_CKGR_OSCOUNT ( ( unsigned int ) 0xFF << 8 ) /* (CKGR) Main Oscillator Start-up Time */ +/* -------- CKGR_MCFR : (CKGR Offset: 0x4) Main Clock Frequency Register -------- */ +#define AT91C_CKGR_MAINF ( ( unsigned int ) 0xFFFF << 0 ) /* (CKGR) Main Clock Frequency */ +#define AT91C_CKGR_MAINRDY ( ( unsigned int ) 0x1 << 16 ) /* (CKGR) Main Clock Ready */ +/* -------- CKGR_PLLR : (CKGR Offset: 0xc) PLL B Register -------- */ +#define AT91C_CKGR_DIV ( ( unsigned int ) 0xFF << 0 ) /* (CKGR) Divider Selected */ +#define AT91C_CKGR_DIV_0 ( ( unsigned int ) 0x0 ) /* (CKGR) Divider output is 0 */ +#define AT91C_CKGR_DIV_BYPASS ( ( unsigned int ) 0x1 ) /* (CKGR) Divider is bypassed */ +#define AT91C_CKGR_PLLCOUNT ( ( unsigned int ) 0x3F << 8 ) /* (CKGR) PLL Counter */ +#define AT91C_CKGR_OUT ( ( unsigned int ) 0x3 << 14 ) /* (CKGR) PLL Output Frequency Range */ +#define AT91C_CKGR_OUT_0 ( ( unsigned int ) 0x0 << 14 ) /* (CKGR) Please refer to the PLL datasheet */ +#define AT91C_CKGR_OUT_1 ( ( unsigned int ) 0x1 << 14 ) /* (CKGR) Please refer to the PLL datasheet */ +#define AT91C_CKGR_OUT_2 ( ( unsigned int ) 0x2 << 14 ) /* (CKGR) Please refer to the PLL datasheet */ +#define AT91C_CKGR_OUT_3 ( ( unsigned int ) 0x3 << 14 ) /* (CKGR) Please refer to the PLL datasheet */ +#define AT91C_CKGR_MUL ( ( unsigned int ) 0x7FF << 16 ) /* (CKGR) PLL Multiplier */ +#define AT91C_CKGR_USBDIV ( ( unsigned int ) 0x3 << 28 ) /* (CKGR) Divider for USB Clocks */ +#define AT91C_CKGR_USBDIV_0 ( ( unsigned int ) 0x0 << 28 ) /* (CKGR) Divider output is PLL clock output */ +#define AT91C_CKGR_USBDIV_1 ( ( unsigned int ) 0x1 << 28 ) /* (CKGR) Divider output is PLL clock output divided by 2 */ +#define AT91C_CKGR_USBDIV_2 ( ( unsigned int ) 0x2 << 28 ) /* (CKGR) Divider output is PLL clock output divided by 4 */ + +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR Power Management Controller */ +/* ***************************************************************************** */ +typedef struct _AT91S_PMC +{ + AT91_REG PMC_SCER; /* System Clock Enable Register */ + AT91_REG PMC_SCDR; /* System Clock Disable Register */ + AT91_REG PMC_SCSR; /* System Clock Status Register */ + AT91_REG Reserved0[ 1 ]; /* */ + AT91_REG PMC_PCER; /* Peripheral Clock Enable Register */ + AT91_REG PMC_PCDR; /* Peripheral Clock Disable Register */ + AT91_REG PMC_PCSR; /* Peripheral Clock Status Register */ + AT91_REG Reserved1[ 1 ]; /* */ + AT91_REG PMC_MOR; /* Main Oscillator Register */ + AT91_REG PMC_MCFR; /* Main Clock Frequency Register */ + AT91_REG Reserved2[ 1 ]; /* */ + AT91_REG PMC_PLLR; /* PLL Register */ + AT91_REG PMC_MCKR; /* Master Clock Register */ + AT91_REG Reserved3[ 3 ]; /* */ + AT91_REG PMC_PCKR[ 4 ]; /* Programmable Clock Register */ + AT91_REG Reserved4[ 4 ]; /* */ + AT91_REG PMC_IER; /* Interrupt Enable Register */ + AT91_REG PMC_IDR; /* Interrupt Disable Register */ + AT91_REG PMC_SR; /* Status Register */ + AT91_REG PMC_IMR; /* Interrupt Mask Register */ +} AT91S_PMC, * AT91PS_PMC; + +/* -------- PMC_SCER : (PMC Offset: 0x0) System Clock Enable Register -------- */ +#define AT91C_PMC_PCK ( ( unsigned int ) 0x1 << 0 ) /* (PMC) Processor Clock */ +#define AT91C_PMC_UDP ( ( unsigned int ) 0x1 << 7 ) /* (PMC) USB Device Port Clock */ +#define AT91C_PMC_PCK0 ( ( unsigned int ) 0x1 << 8 ) /* (PMC) Programmable Clock Output */ +#define AT91C_PMC_PCK1 ( ( unsigned int ) 0x1 << 9 ) /* (PMC) Programmable Clock Output */ +#define AT91C_PMC_PCK2 ( ( unsigned int ) 0x1 << 10 ) /* (PMC) Programmable Clock Output */ +#define AT91C_PMC_PCK3 ( ( unsigned int ) 0x1 << 11 ) /* (PMC) Programmable Clock Output */ +/* -------- PMC_SCDR : (PMC Offset: 0x4) System Clock Disable Register -------- */ +/* -------- PMC_SCSR : (PMC Offset: 0x8) System Clock Status Register -------- */ +/* -------- CKGR_MOR : (PMC Offset: 0x20) Main Oscillator Register -------- */ +/* -------- CKGR_MCFR : (PMC Offset: 0x24) Main Clock Frequency Register -------- */ +/* -------- CKGR_PLLR : (PMC Offset: 0x2c) PLL B Register -------- */ +/* -------- PMC_MCKR : (PMC Offset: 0x30) Master Clock Register -------- */ +#define AT91C_PMC_CSS ( ( unsigned int ) 0x3 << 0 ) /* (PMC) Programmable Clock Selection */ +#define AT91C_PMC_CSS_SLOW_CLK ( ( unsigned int ) 0x0 ) /* (PMC) Slow Clock is selected */ +#define AT91C_PMC_CSS_MAIN_CLK ( ( unsigned int ) 0x1 ) /* (PMC) Main Clock is selected */ +#define AT91C_PMC_CSS_PLL_CLK ( ( unsigned int ) 0x3 ) /* (PMC) Clock from PLL is selected */ +#define AT91C_PMC_PRES ( ( unsigned int ) 0x7 << 2 ) /* (PMC) Programmable Clock Prescaler */ +#define AT91C_PMC_PRES_CLK ( ( unsigned int ) 0x0 << 2 ) /* (PMC) Selected clock */ +#define AT91C_PMC_PRES_CLK_2 ( ( unsigned int ) 0x1 << 2 ) /* (PMC) Selected clock divided by 2 */ +#define AT91C_PMC_PRES_CLK_4 ( ( unsigned int ) 0x2 << 2 ) /* (PMC) Selected clock divided by 4 */ +#define AT91C_PMC_PRES_CLK_8 ( ( unsigned int ) 0x3 << 2 ) /* (PMC) Selected clock divided by 8 */ +#define AT91C_PMC_PRES_CLK_16 ( ( unsigned int ) 0x4 << 2 ) /* (PMC) Selected clock divided by 16 */ +#define AT91C_PMC_PRES_CLK_32 ( ( unsigned int ) 0x5 << 2 ) /* (PMC) Selected clock divided by 32 */ +#define AT91C_PMC_PRES_CLK_64 ( ( unsigned int ) 0x6 << 2 ) /* (PMC) Selected clock divided by 64 */ +/* -------- PMC_PCKR : (PMC Offset: 0x40) Programmable Clock Register -------- */ +/* -------- PMC_IER : (PMC Offset: 0x60) PMC Interrupt Enable Register -------- */ +#define AT91C_PMC_MOSCS ( ( unsigned int ) 0x1 << 0 ) /* (PMC) MOSC Status/Enable/Disable/Mask */ +#define AT91C_PMC_LOCK ( ( unsigned int ) 0x1 << 2 ) /* (PMC) PLL Status/Enable/Disable/Mask */ +#define AT91C_PMC_MCKRDY ( ( unsigned int ) 0x1 << 3 ) /* (PMC) MCK_RDY Status/Enable/Disable/Mask */ +#define AT91C_PMC_PCK0RDY ( ( unsigned int ) 0x1 << 8 ) /* (PMC) PCK0_RDY Status/Enable/Disable/Mask */ +#define AT91C_PMC_PCK1RDY ( ( unsigned int ) 0x1 << 9 ) /* (PMC) PCK1_RDY Status/Enable/Disable/Mask */ +#define AT91C_PMC_PCK2RDY ( ( unsigned int ) 0x1 << 10 ) /* (PMC) PCK2_RDY Status/Enable/Disable/Mask */ +#define AT91C_PMC_PCK3RDY ( ( unsigned int ) 0x1 << 11 ) /* (PMC) PCK3_RDY Status/Enable/Disable/Mask */ +/* -------- PMC_IDR : (PMC Offset: 0x64) PMC Interrupt Disable Register -------- */ +/* -------- PMC_SR : (PMC Offset: 0x68) PMC Status Register -------- */ +/* -------- PMC_IMR : (PMC Offset: 0x6c) PMC Interrupt Mask Register -------- */ + +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR Reset Controller Interface */ +/* ***************************************************************************** */ +typedef struct _AT91S_RSTC +{ + AT91_REG RSTC_RCR; /* Reset Control Register */ + AT91_REG RSTC_RSR; /* Reset Status Register */ + AT91_REG RSTC_RMR; /* Reset Mode Register */ +} AT91S_RSTC, * AT91PS_RSTC; + +/* -------- RSTC_RCR : (RSTC Offset: 0x0) Reset Control Register -------- */ +#define AT91C_RSTC_PROCRST ( ( unsigned int ) 0x1 << 0 ) /* (RSTC) Processor Reset */ +#define AT91C_RSTC_PERRST ( ( unsigned int ) 0x1 << 2 ) /* (RSTC) Peripheral Reset */ +#define AT91C_RSTC_EXTRST ( ( unsigned int ) 0x1 << 3 ) /* (RSTC) External Reset */ +#define AT91C_RSTC_KEY ( ( unsigned int ) 0xFF << 24 ) /* (RSTC) Password */ +/* -------- RSTC_RSR : (RSTC Offset: 0x4) Reset Status Register -------- */ +#define AT91C_RSTC_URSTS ( ( unsigned int ) 0x1 << 0 ) /* (RSTC) User Reset Status */ +#define AT91C_RSTC_BODSTS ( ( unsigned int ) 0x1 << 1 ) /* (RSTC) Brownout Detection Status */ +#define AT91C_RSTC_RSTTYP ( ( unsigned int ) 0x7 << 8 ) /* (RSTC) Reset Type */ +#define AT91C_RSTC_RSTTYP_POWERUP ( ( unsigned int ) 0x0 << 8 ) /* (RSTC) Power-up Reset. VDDCORE rising. */ +#define AT91C_RSTC_RSTTYP_WAKEUP ( ( unsigned int ) 0x1 << 8 ) /* (RSTC) WakeUp Reset. VDDCORE rising. */ +#define AT91C_RSTC_RSTTYP_WATCHDOG ( ( unsigned int ) 0x2 << 8 ) /* (RSTC) Watchdog Reset. Watchdog overflow occurred. */ +#define AT91C_RSTC_RSTTYP_SOFTWARE ( ( unsigned int ) 0x3 << 8 ) /* (RSTC) Software Reset. Processor reset required by the software. */ +#define AT91C_RSTC_RSTTYP_USER ( ( unsigned int ) 0x4 << 8 ) /* (RSTC) User Reset. NRST pin detected low. */ +#define AT91C_RSTC_RSTTYP_BROWNOUT ( ( unsigned int ) 0x5 << 8 ) /* (RSTC) Brownout Reset occurred. */ +#define AT91C_RSTC_NRSTL ( ( unsigned int ) 0x1 << 16 ) /* (RSTC) NRST pin level */ +#define AT91C_RSTC_SRCMP ( ( unsigned int ) 0x1 << 17 ) /* (RSTC) Software Reset Command in Progress. */ +/* -------- RSTC_RMR : (RSTC Offset: 0x8) Reset Mode Register -------- */ +#define AT91C_RSTC_URSTEN ( ( unsigned int ) 0x1 << 0 ) /* (RSTC) User Reset Enable */ +#define AT91C_RSTC_URSTIEN ( ( unsigned int ) 0x1 << 4 ) /* (RSTC) User Reset Interrupt Enable */ +#define AT91C_RSTC_ERSTL ( ( unsigned int ) 0xF << 8 ) /* (RSTC) User Reset Enable */ +#define AT91C_RSTC_BODIEN ( ( unsigned int ) 0x1 << 16 ) /* (RSTC) Brownout Detection Interrupt Enable */ + +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR Real Time Timer Controller Interface */ +/* ***************************************************************************** */ +typedef struct _AT91S_RTTC +{ + AT91_REG RTTC_RTMR; /* Real-time Mode Register */ + AT91_REG RTTC_RTAR; /* Real-time Alarm Register */ + AT91_REG RTTC_RTVR; /* Real-time Value Register */ + AT91_REG RTTC_RTSR; /* Real-time Status Register */ +} AT91S_RTTC, * AT91PS_RTTC; + +/* -------- RTTC_RTMR : (RTTC Offset: 0x0) Real-time Mode Register -------- */ +#define AT91C_RTTC_RTPRES ( ( unsigned int ) 0xFFFF << 0 ) /* (RTTC) Real-time Timer Prescaler Value */ +#define AT91C_RTTC_ALMIEN ( ( unsigned int ) 0x1 << 16 ) /* (RTTC) Alarm Interrupt Enable */ +#define AT91C_RTTC_RTTINCIEN ( ( unsigned int ) 0x1 << 17 ) /* (RTTC) Real Time Timer Increment Interrupt Enable */ +#define AT91C_RTTC_RTTRST ( ( unsigned int ) 0x1 << 18 ) /* (RTTC) Real Time Timer Restart */ +/* -------- RTTC_RTAR : (RTTC Offset: 0x4) Real-time Alarm Register -------- */ +#define AT91C_RTTC_ALMV ( ( unsigned int ) 0x0 << 0 ) /* (RTTC) Alarm Value */ +/* -------- RTTC_RTVR : (RTTC Offset: 0x8) Current Real-time Value Register -------- */ +#define AT91C_RTTC_CRTV ( ( unsigned int ) 0x0 << 0 ) /* (RTTC) Current Real-time Value */ +/* -------- RTTC_RTSR : (RTTC Offset: 0xc) Real-time Status Register -------- */ +#define AT91C_RTTC_ALMS ( ( unsigned int ) 0x1 << 0 ) /* (RTTC) Real-time Alarm Status */ +#define AT91C_RTTC_RTTINC ( ( unsigned int ) 0x1 << 1 ) /* (RTTC) Real-time Timer Increment */ + +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR Periodic Interval Timer Controller Interface */ +/* ***************************************************************************** */ +typedef struct _AT91S_PITC +{ + AT91_REG PITC_PIMR; /* Period Interval Mode Register */ + AT91_REG PITC_PISR; /* Period Interval Status Register */ + AT91_REG PITC_PIVR; /* Period Interval Value Register */ + AT91_REG PITC_PIIR; /* Period Interval Image Register */ +} AT91S_PITC, * AT91PS_PITC; + +/* -------- PITC_PIMR : (PITC Offset: 0x0) Periodic Interval Mode Register -------- */ +#define AT91C_PITC_PIV ( ( unsigned int ) 0xFFFFF << 0 ) /* (PITC) Periodic Interval Value */ +#define AT91C_PITC_PITEN ( ( unsigned int ) 0x1 << 24 ) /* (PITC) Periodic Interval Timer Enabled */ +#define AT91C_PITC_PITIEN ( ( unsigned int ) 0x1 << 25 ) /* (PITC) Periodic Interval Timer Interrupt Enable */ +/* -------- PITC_PISR : (PITC Offset: 0x4) Periodic Interval Status Register -------- */ +#define AT91C_PITC_PITS ( ( unsigned int ) 0x1 << 0 ) /* (PITC) Periodic Interval Timer Status */ +/* -------- PITC_PIVR : (PITC Offset: 0x8) Periodic Interval Value Register -------- */ +#define AT91C_PITC_CPIV ( ( unsigned int ) 0xFFFFF << 0 ) /* (PITC) Current Periodic Interval Value */ +#define AT91C_PITC_PICNT ( ( unsigned int ) 0xFFF << 20 ) /* (PITC) Periodic Interval Counter */ +/* -------- PITC_PIIR : (PITC Offset: 0xc) Periodic Interval Image Register -------- */ + +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR Watchdog Timer Controller Interface */ +/* ***************************************************************************** */ +typedef struct _AT91S_WDTC +{ + AT91_REG WDTC_WDCR; /* Watchdog Control Register */ + AT91_REG WDTC_WDMR; /* Watchdog Mode Register */ + AT91_REG WDTC_WDSR; /* Watchdog Status Register */ +} AT91S_WDTC, * AT91PS_WDTC; + +/* -------- WDTC_WDCR : (WDTC Offset: 0x0) Periodic Interval Image Register -------- */ +#define AT91C_WDTC_WDRSTT ( ( unsigned int ) 0x1 << 0 ) /* (WDTC) Watchdog Restart */ +#define AT91C_WDTC_KEY ( ( unsigned int ) 0xFF << 24 ) /* (WDTC) Watchdog KEY Password */ +/* -------- WDTC_WDMR : (WDTC Offset: 0x4) Watchdog Mode Register -------- */ +#define AT91C_WDTC_WDV ( ( unsigned int ) 0xFFF << 0 ) /* (WDTC) Watchdog Timer Restart */ +#define AT91C_WDTC_WDFIEN ( ( unsigned int ) 0x1 << 12 ) /* (WDTC) Watchdog Fault Interrupt Enable */ +#define AT91C_WDTC_WDRSTEN ( ( unsigned int ) 0x1 << 13 ) /* (WDTC) Watchdog Reset Enable */ +#define AT91C_WDTC_WDRPROC ( ( unsigned int ) 0x1 << 14 ) /* (WDTC) Watchdog Timer Restart */ +#define AT91C_WDTC_WDDIS ( ( unsigned int ) 0x1 << 15 ) /* (WDTC) Watchdog Disable */ +#define AT91C_WDTC_WDD ( ( unsigned int ) 0xFFF << 16 ) /* (WDTC) Watchdog Delta Value */ +#define AT91C_WDTC_WDDBGHLT ( ( unsigned int ) 0x1 << 28 ) /* (WDTC) Watchdog Debug Halt */ +#define AT91C_WDTC_WDIDLEHLT ( ( unsigned int ) 0x1 << 29 ) /* (WDTC) Watchdog Idle Halt */ +/* -------- WDTC_WDSR : (WDTC Offset: 0x8) Watchdog Status Register -------- */ +#define AT91C_WDTC_WDUNF ( ( unsigned int ) 0x1 << 0 ) /* (WDTC) Watchdog Underflow */ +#define AT91C_WDTC_WDERR ( ( unsigned int ) 0x1 << 1 ) /* (WDTC) Watchdog Error */ + +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR Voltage Regulator Mode Controller Interface */ +/* ***************************************************************************** */ +typedef struct _AT91S_VREG +{ + AT91_REG VREG_MR; /* Voltage Regulator Mode Register */ +} AT91S_VREG, * AT91PS_VREG; + +/* -------- VREG_MR : (VREG Offset: 0x0) Voltage Regulator Mode Register -------- */ +#define AT91C_VREG_PSTDBY ( ( unsigned int ) 0x1 << 0 ) /* (VREG) Voltage Regulator Power Standby Mode */ + +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR Memory Controller Interface */ +/* ***************************************************************************** */ +typedef struct _AT91S_MC +{ + AT91_REG MC_RCR; /* MC Remap Control Register */ + AT91_REG MC_ASR; /* MC Abort Status Register */ + AT91_REG MC_AASR; /* MC Abort Address Status Register */ + AT91_REG Reserved0[ 21 ]; /* */ + AT91_REG MC_FMR; /* MC Flash Mode Register */ + AT91_REG MC_FCR; /* MC Flash Command Register */ + AT91_REG MC_FSR; /* MC Flash Status Register */ +} AT91S_MC, * AT91PS_MC; + +/* -------- MC_RCR : (MC Offset: 0x0) MC Remap Control Register -------- */ +#define AT91C_MC_RCB ( ( unsigned int ) 0x1 << 0 ) /* (MC) Remap Command Bit */ +/* -------- MC_ASR : (MC Offset: 0x4) MC Abort Status Register -------- */ +#define AT91C_MC_UNDADD ( ( unsigned int ) 0x1 << 0 ) /* (MC) Undefined Addess Abort Status */ +#define AT91C_MC_MISADD ( ( unsigned int ) 0x1 << 1 ) /* (MC) Misaligned Addess Abort Status */ +#define AT91C_MC_ABTSZ ( ( unsigned int ) 0x3 << 8 ) /* (MC) Abort Size Status */ +#define AT91C_MC_ABTSZ_BYTE ( ( unsigned int ) 0x0 << 8 ) /* (MC) Byte */ +#define AT91C_MC_ABTSZ_HWORD ( ( unsigned int ) 0x1 << 8 ) /* (MC) Half-word */ +#define AT91C_MC_ABTSZ_WORD ( ( unsigned int ) 0x2 << 8 ) /* (MC) Word */ +#define AT91C_MC_ABTTYP ( ( unsigned int ) 0x3 << 10 ) /* (MC) Abort Type Status */ +#define AT91C_MC_ABTTYP_DATAR ( ( unsigned int ) 0x0 << 10 ) /* (MC) Data Read */ +#define AT91C_MC_ABTTYP_DATAW ( ( unsigned int ) 0x1 << 10 ) /* (MC) Data Write */ +#define AT91C_MC_ABTTYP_FETCH ( ( unsigned int ) 0x2 << 10 ) /* (MC) Code Fetch */ +#define AT91C_MC_MST0 ( ( unsigned int ) 0x1 << 16 ) /* (MC) Master 0 Abort Source */ +#define AT91C_MC_MST1 ( ( unsigned int ) 0x1 << 17 ) /* (MC) Master 1 Abort Source */ +#define AT91C_MC_SVMST0 ( ( unsigned int ) 0x1 << 24 ) /* (MC) Saved Master 0 Abort Source */ +#define AT91C_MC_SVMST1 ( ( unsigned int ) 0x1 << 25 ) /* (MC) Saved Master 1 Abort Source */ +/* -------- MC_FMR : (MC Offset: 0x60) MC Flash Mode Register -------- */ +#define AT91C_MC_FRDY ( ( unsigned int ) 0x1 << 0 ) /* (MC) Flash Ready */ +#define AT91C_MC_LOCKE ( ( unsigned int ) 0x1 << 2 ) /* (MC) Lock Error */ +#define AT91C_MC_PROGE ( ( unsigned int ) 0x1 << 3 ) /* (MC) Programming Error */ +#define AT91C_MC_NEBP ( ( unsigned int ) 0x1 << 7 ) /* (MC) No Erase Before Programming */ +#define AT91C_MC_FWS ( ( unsigned int ) 0x3 << 8 ) /* (MC) Flash Wait State */ +#define AT91C_MC_FWS_0FWS ( ( unsigned int ) 0x0 << 8 ) /* (MC) 1 cycle for Read, 2 for Write operations */ +#define AT91C_MC_FWS_1FWS ( ( unsigned int ) 0x1 << 8 ) /* (MC) 2 cycles for Read, 3 for Write operations */ +#define AT91C_MC_FWS_2FWS ( ( unsigned int ) 0x2 << 8 ) /* (MC) 3 cycles for Read, 4 for Write operations */ +#define AT91C_MC_FWS_3FWS ( ( unsigned int ) 0x3 << 8 ) /* (MC) 4 cycles for Read, 4 for Write operations */ +#define AT91C_MC_FMCN ( ( unsigned int ) 0xFF << 16 ) /* (MC) Flash Microsecond Cycle Number */ +/* -------- MC_FCR : (MC Offset: 0x64) MC Flash Command Register -------- */ +#define AT91C_MC_FCMD ( ( unsigned int ) 0xF << 0 ) /* (MC) Flash Command */ +#define AT91C_MC_FCMD_START_PROG ( ( unsigned int ) 0x1 ) /* (MC) Starts the programming of th epage specified by PAGEN. */ +#define AT91C_MC_FCMD_LOCK ( ( unsigned int ) 0x2 ) /* (MC) Starts a lock sequence of the sector defined by the bits 4 to 7 of the field PAGEN. */ +#define AT91C_MC_FCMD_PROG_AND_LOCK ( ( unsigned int ) 0x3 ) /* (MC) The lock sequence automatically happens after the programming sequence is completed. */ +#define AT91C_MC_FCMD_UNLOCK ( ( unsigned int ) 0x4 ) /* (MC) Starts an unlock sequence of the sector defined by the bits 4 to 7 of the field PAGEN. */ +#define AT91C_MC_FCMD_ERASE_ALL ( ( unsigned int ) 0x8 ) /* (MC) Starts the erase of the entire flash.If at least a page is locked, the command is cancelled. */ +#define AT91C_MC_FCMD_SET_GP_NVM ( ( unsigned int ) 0xB ) /* (MC) Set General Purpose NVM bits. */ +#define AT91C_MC_FCMD_CLR_GP_NVM ( ( unsigned int ) 0xD ) /* (MC) Clear General Purpose NVM bits. */ +#define AT91C_MC_FCMD_SET_SECURITY ( ( unsigned int ) 0xF ) /* (MC) Set Security Bit. */ +#define AT91C_MC_PAGEN ( ( unsigned int ) 0x3FF << 8 ) /* (MC) Page Number */ +#define AT91C_MC_KEY ( ( unsigned int ) 0xFF << 24 ) /* (MC) Writing Protect Key */ +/* -------- MC_FSR : (MC Offset: 0x68) MC Flash Command Register -------- */ +#define AT91C_MC_SECURITY ( ( unsigned int ) 0x1 << 4 ) /* (MC) Security Bit Status */ +#define AT91C_MC_GPNVM0 ( ( unsigned int ) 0x1 << 8 ) /* (MC) Sector 0 Lock Status */ +#define AT91C_MC_GPNVM1 ( ( unsigned int ) 0x1 << 9 ) /* (MC) Sector 1 Lock Status */ +#define AT91C_MC_GPNVM2 ( ( unsigned int ) 0x1 << 10 ) /* (MC) Sector 2 Lock Status */ +#define AT91C_MC_GPNVM3 ( ( unsigned int ) 0x1 << 11 ) /* (MC) Sector 3 Lock Status */ +#define AT91C_MC_GPNVM4 ( ( unsigned int ) 0x1 << 12 ) /* (MC) Sector 4 Lock Status */ +#define AT91C_MC_GPNVM5 ( ( unsigned int ) 0x1 << 13 ) /* (MC) Sector 5 Lock Status */ +#define AT91C_MC_GPNVM6 ( ( unsigned int ) 0x1 << 14 ) /* (MC) Sector 6 Lock Status */ +#define AT91C_MC_GPNVM7 ( ( unsigned int ) 0x1 << 15 ) /* (MC) Sector 7 Lock Status */ +#define AT91C_MC_LOCKS0 ( ( unsigned int ) 0x1 << 16 ) /* (MC) Sector 0 Lock Status */ +#define AT91C_MC_LOCKS1 ( ( unsigned int ) 0x1 << 17 ) /* (MC) Sector 1 Lock Status */ +#define AT91C_MC_LOCKS2 ( ( unsigned int ) 0x1 << 18 ) /* (MC) Sector 2 Lock Status */ +#define AT91C_MC_LOCKS3 ( ( unsigned int ) 0x1 << 19 ) /* (MC) Sector 3 Lock Status */ +#define AT91C_MC_LOCKS4 ( ( unsigned int ) 0x1 << 20 ) /* (MC) Sector 4 Lock Status */ +#define AT91C_MC_LOCKS5 ( ( unsigned int ) 0x1 << 21 ) /* (MC) Sector 5 Lock Status */ +#define AT91C_MC_LOCKS6 ( ( unsigned int ) 0x1 << 22 ) /* (MC) Sector 6 Lock Status */ +#define AT91C_MC_LOCKS7 ( ( unsigned int ) 0x1 << 23 ) /* (MC) Sector 7 Lock Status */ +#define AT91C_MC_LOCKS8 ( ( unsigned int ) 0x1 << 24 ) /* (MC) Sector 8 Lock Status */ +#define AT91C_MC_LOCKS9 ( ( unsigned int ) 0x1 << 25 ) /* (MC) Sector 9 Lock Status */ +#define AT91C_MC_LOCKS10 ( ( unsigned int ) 0x1 << 26 ) /* (MC) Sector 10 Lock Status */ +#define AT91C_MC_LOCKS11 ( ( unsigned int ) 0x1 << 27 ) /* (MC) Sector 11 Lock Status */ +#define AT91C_MC_LOCKS12 ( ( unsigned int ) 0x1 << 28 ) /* (MC) Sector 12 Lock Status */ +#define AT91C_MC_LOCKS13 ( ( unsigned int ) 0x1 << 29 ) /* (MC) Sector 13 Lock Status */ +#define AT91C_MC_LOCKS14 ( ( unsigned int ) 0x1 << 30 ) /* (MC) Sector 14 Lock Status */ +#define AT91C_MC_LOCKS15 ( ( unsigned int ) 0x1 << 31 ) /* (MC) Sector 15 Lock Status */ + +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR Serial Parallel Interface */ +/* ***************************************************************************** */ +typedef struct _AT91S_SPI +{ + AT91_REG SPI_CR; /* Control Register */ + AT91_REG SPI_MR; /* Mode Register */ + AT91_REG SPI_RDR; /* Receive Data Register */ + AT91_REG SPI_TDR; /* Transmit Data Register */ + AT91_REG SPI_SR; /* Status Register */ + AT91_REG SPI_IER; /* Interrupt Enable Register */ + AT91_REG SPI_IDR; /* Interrupt Disable Register */ + AT91_REG SPI_IMR; /* Interrupt Mask Register */ + AT91_REG Reserved0[ 4 ]; /* */ + AT91_REG SPI_CSR[ 4 ]; /* Chip Select Register */ + AT91_REG Reserved1[ 48 ]; /* */ + AT91_REG SPI_RPR; /* Receive Pointer Register */ + AT91_REG SPI_RCR; /* Receive Counter Register */ + AT91_REG SPI_TPR; /* Transmit Pointer Register */ + AT91_REG SPI_TCR; /* Transmit Counter Register */ + AT91_REG SPI_RNPR; /* Receive Next Pointer Register */ + AT91_REG SPI_RNCR; /* Receive Next Counter Register */ + AT91_REG SPI_TNPR; /* Transmit Next Pointer Register */ + AT91_REG SPI_TNCR; /* Transmit Next Counter Register */ + AT91_REG SPI_PTCR; /* PDC Transfer Control Register */ + AT91_REG SPI_PTSR; /* PDC Transfer Status Register */ +} AT91S_SPI, * AT91PS_SPI; + +/* -------- SPI_CR : (SPI Offset: 0x0) SPI Control Register -------- */ +#define AT91C_SPI_SPIEN ( ( unsigned int ) 0x1 << 0 ) /* (SPI) SPI Enable */ +#define AT91C_SPI_SPIDIS ( ( unsigned int ) 0x1 << 1 ) /* (SPI) SPI Disable */ +#define AT91C_SPI_SWRST ( ( unsigned int ) 0x1 << 7 ) /* (SPI) SPI Software reset */ +#define AT91C_SPI_LASTXFER ( ( unsigned int ) 0x1 << 24 ) /* (SPI) SPI Last Transfer */ +/* -------- SPI_MR : (SPI Offset: 0x4) SPI Mode Register -------- */ +#define AT91C_SPI_MSTR ( ( unsigned int ) 0x1 << 0 ) /* (SPI) Master/Slave Mode */ +#define AT91C_SPI_PS ( ( unsigned int ) 0x1 << 1 ) /* (SPI) Peripheral Select */ +#define AT91C_SPI_PS_FIXED ( ( unsigned int ) 0x0 << 1 ) /* (SPI) Fixed Peripheral Select */ +#define AT91C_SPI_PS_VARIABLE ( ( unsigned int ) 0x1 << 1 ) /* (SPI) Variable Peripheral Select */ +#define AT91C_SPI_PCSDEC ( ( unsigned int ) 0x1 << 2 ) /* (SPI) Chip Select Decode */ +#define AT91C_SPI_FDIV ( ( unsigned int ) 0x1 << 3 ) /* (SPI) Clock Selection */ +#define AT91C_SPI_MODFDIS ( ( unsigned int ) 0x1 << 4 ) /* (SPI) Mode Fault Detection */ +#define AT91C_SPI_LLB ( ( unsigned int ) 0x1 << 7 ) /* (SPI) Clock Selection */ +#define AT91C_SPI_PCS ( ( unsigned int ) 0xF << 16 ) /* (SPI) Peripheral Chip Select */ +#define AT91C_SPI_DLYBCS ( ( unsigned int ) 0xFF << 24 ) /* (SPI) Delay Between Chip Selects */ +/* -------- SPI_RDR : (SPI Offset: 0x8) Receive Data Register -------- */ +#define AT91C_SPI_RD ( ( unsigned int ) 0xFFFF << 0 ) /* (SPI) Receive Data */ +#define AT91C_SPI_RPCS ( ( unsigned int ) 0xF << 16 ) /* (SPI) Peripheral Chip Select Status */ +/* -------- SPI_TDR : (SPI Offset: 0xc) Transmit Data Register -------- */ +#define AT91C_SPI_TD ( ( unsigned int ) 0xFFFF << 0 ) /* (SPI) Transmit Data */ +#define AT91C_SPI_TPCS ( ( unsigned int ) 0xF << 16 ) /* (SPI) Peripheral Chip Select Status */ +/* -------- SPI_SR : (SPI Offset: 0x10) Status Register -------- */ +#define AT91C_SPI_RDRF ( ( unsigned int ) 0x1 << 0 ) /* (SPI) Receive Data Register Full */ +#define AT91C_SPI_TDRE ( ( unsigned int ) 0x1 << 1 ) /* (SPI) Transmit Data Register Empty */ +#define AT91C_SPI_MODF ( ( unsigned int ) 0x1 << 2 ) /* (SPI) Mode Fault Error */ +#define AT91C_SPI_OVRES ( ( unsigned int ) 0x1 << 3 ) /* (SPI) Overrun Error Status */ +#define AT91C_SPI_ENDRX ( ( unsigned int ) 0x1 << 4 ) /* (SPI) End of Receiver Transfer */ +#define AT91C_SPI_ENDTX ( ( unsigned int ) 0x1 << 5 ) /* (SPI) End of Receiver Transfer */ +#define AT91C_SPI_RXBUFF ( ( unsigned int ) 0x1 << 6 ) /* (SPI) RXBUFF Interrupt */ +#define AT91C_SPI_TXBUFE ( ( unsigned int ) 0x1 << 7 ) /* (SPI) TXBUFE Interrupt */ +#define AT91C_SPI_NSSR ( ( unsigned int ) 0x1 << 8 ) /* (SPI) NSSR Interrupt */ +#define AT91C_SPI_TXEMPTY ( ( unsigned int ) 0x1 << 9 ) /* (SPI) TXEMPTY Interrupt */ +#define AT91C_SPI_SPIENS ( ( unsigned int ) 0x1 << 16 ) /* (SPI) Enable Status */ +/* -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register -------- */ +/* -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register -------- */ +/* -------- SPI_IMR : (SPI Offset: 0x1c) Interrupt Mask Register -------- */ +/* -------- SPI_CSR : (SPI Offset: 0x30) Chip Select Register -------- */ +#define AT91C_SPI_CPOL ( ( unsigned int ) 0x1 << 0 ) /* (SPI) Clock Polarity */ +#define AT91C_SPI_NCPHA ( ( unsigned int ) 0x1 << 1 ) /* (SPI) Clock Phase */ +#define AT91C_SPI_CSAAT ( ( unsigned int ) 0x1 << 3 ) /* (SPI) Chip Select Active After Transfer */ +#define AT91C_SPI_BITS ( ( unsigned int ) 0xF << 4 ) /* (SPI) Bits Per Transfer */ +#define AT91C_SPI_BITS_8 ( ( unsigned int ) 0x0 << 4 ) /* (SPI) 8 Bits Per transfer */ +#define AT91C_SPI_BITS_9 ( ( unsigned int ) 0x1 << 4 ) /* (SPI) 9 Bits Per transfer */ +#define AT91C_SPI_BITS_10 ( ( unsigned int ) 0x2 << 4 ) /* (SPI) 10 Bits Per transfer */ +#define AT91C_SPI_BITS_11 ( ( unsigned int ) 0x3 << 4 ) /* (SPI) 11 Bits Per transfer */ +#define AT91C_SPI_BITS_12 ( ( unsigned int ) 0x4 << 4 ) /* (SPI) 12 Bits Per transfer */ +#define AT91C_SPI_BITS_13 ( ( unsigned int ) 0x5 << 4 ) /* (SPI) 13 Bits Per transfer */ +#define AT91C_SPI_BITS_14 ( ( unsigned int ) 0x6 << 4 ) /* (SPI) 14 Bits Per transfer */ +#define AT91C_SPI_BITS_15 ( ( unsigned int ) 0x7 << 4 ) /* (SPI) 15 Bits Per transfer */ +#define AT91C_SPI_BITS_16 ( ( unsigned int ) 0x8 << 4 ) /* (SPI) 16 Bits Per transfer */ +#define AT91C_SPI_SCBR ( ( unsigned int ) 0xFF << 8 ) /* (SPI) Serial Clock Baud Rate */ +#define AT91C_SPI_DLYBS ( ( unsigned int ) 0xFF << 16 ) /* (SPI) Delay Before SPCK */ +#define AT91C_SPI_DLYBCT ( ( unsigned int ) 0xFF << 24 ) /* (SPI) Delay Between Consecutive Transfers */ + +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR Usart */ +/* ***************************************************************************** */ +typedef struct _AT91S_USART +{ + AT91_REG US_CR; /* Control Register */ + AT91_REG US_MR; /* Mode Register */ + AT91_REG US_IER; /* Interrupt Enable Register */ + AT91_REG US_IDR; /* Interrupt Disable Register */ + AT91_REG US_IMR; /* Interrupt Mask Register */ + AT91_REG US_CSR; /* Channel Status Register */ + AT91_REG US_RHR; /* Receiver Holding Register */ + AT91_REG US_THR; /* Transmitter Holding Register */ + AT91_REG US_BRGR; /* Baud Rate Generator Register */ + AT91_REG US_RTOR; /* Receiver Time-out Register */ + AT91_REG US_TTGR; /* Transmitter Time-guard Register */ + AT91_REG Reserved0[ 5 ]; /* */ + AT91_REG US_FIDI; /* FI_DI_Ratio Register */ + AT91_REG US_NER; /* Nb Errors Register */ + AT91_REG Reserved1[ 1 ]; /* */ + AT91_REG US_IF; /* IRDA_FILTER Register */ + AT91_REG Reserved2[ 44 ]; /* */ + AT91_REG US_RPR; /* Receive Pointer Register */ + AT91_REG US_RCR; /* Receive Counter Register */ + AT91_REG US_TPR; /* Transmit Pointer Register */ + AT91_REG US_TCR; /* Transmit Counter Register */ + AT91_REG US_RNPR; /* Receive Next Pointer Register */ + AT91_REG US_RNCR; /* Receive Next Counter Register */ + AT91_REG US_TNPR; /* Transmit Next Pointer Register */ + AT91_REG US_TNCR; /* Transmit Next Counter Register */ + AT91_REG US_PTCR; /* PDC Transfer Control Register */ + AT91_REG US_PTSR; /* PDC Transfer Status Register */ +} AT91S_USART, * AT91PS_USART; + +/* -------- US_CR : (USART Offset: 0x0) Debug Unit Control Register -------- */ +#define AT91C_US_STTBRK ( ( unsigned int ) 0x1 << 9 ) /* (USART) Start Break */ +#define AT91C_US_STPBRK ( ( unsigned int ) 0x1 << 10 ) /* (USART) Stop Break */ +#define AT91C_US_STTTO ( ( unsigned int ) 0x1 << 11 ) /* (USART) Start Time-out */ +#define AT91C_US_SENDA ( ( unsigned int ) 0x1 << 12 ) /* (USART) Send Address */ +#define AT91C_US_RSTIT ( ( unsigned int ) 0x1 << 13 ) /* (USART) Reset Iterations */ +#define AT91C_US_RSTNACK ( ( unsigned int ) 0x1 << 14 ) /* (USART) Reset Non Acknowledge */ +#define AT91C_US_RETTO ( ( unsigned int ) 0x1 << 15 ) /* (USART) Rearm Time-out */ +#define AT91C_US_DTREN ( ( unsigned int ) 0x1 << 16 ) /* (USART) Data Terminal ready Enable */ +#define AT91C_US_DTRDIS ( ( unsigned int ) 0x1 << 17 ) /* (USART) Data Terminal ready Disable */ +#define AT91C_US_RTSEN ( ( unsigned int ) 0x1 << 18 ) /* (USART) Request to Send enable */ +#define AT91C_US_RTSDIS ( ( unsigned int ) 0x1 << 19 ) /* (USART) Request to Send Disable */ +/* -------- US_MR : (USART Offset: 0x4) Debug Unit Mode Register -------- */ +#define AT91C_US_USMODE ( ( unsigned int ) 0xF << 0 ) /* (USART) Usart mode */ +#define AT91C_US_USMODE_NORMAL ( ( unsigned int ) 0x0 ) /* (USART) Normal */ +#define AT91C_US_USMODE_RS485 ( ( unsigned int ) 0x1 ) /* (USART) RS485 */ +#define AT91C_US_USMODE_HWHSH ( ( unsigned int ) 0x2 ) /* (USART) Hardware Handshaking */ +#define AT91C_US_USMODE_MODEM ( ( unsigned int ) 0x3 ) /* (USART) Modem */ +#define AT91C_US_USMODE_ISO7816_0 ( ( unsigned int ) 0x4 ) /* (USART) ISO7816 protocol: T = 0 */ +#define AT91C_US_USMODE_ISO7816_1 ( ( unsigned int ) 0x6 ) /* (USART) ISO7816 protocol: T = 1 */ +#define AT91C_US_USMODE_IRDA ( ( unsigned int ) 0x8 ) /* (USART) IrDA */ +#define AT91C_US_USMODE_SWHSH ( ( unsigned int ) 0xC ) /* (USART) Software Handshaking */ +#define AT91C_US_CLKS ( ( unsigned int ) 0x3 << 4 ) /* (USART) Clock Selection (Baud Rate generator Input Clock */ +#define AT91C_US_CLKS_CLOCK ( ( unsigned int ) 0x0 << 4 ) /* (USART) Clock */ +#define AT91C_US_CLKS_FDIV1 ( ( unsigned int ) 0x1 << 4 ) /* (USART) fdiv1 */ +#define AT91C_US_CLKS_SLOW ( ( unsigned int ) 0x2 << 4 ) /* (USART) slow_clock (ARM) */ +#define AT91C_US_CLKS_EXT ( ( unsigned int ) 0x3 << 4 ) /* (USART) External (SCK) */ +#define AT91C_US_CHRL ( ( unsigned int ) 0x3 << 6 ) /* (USART) Clock Selection (Baud Rate generator Input Clock */ +#define AT91C_US_CHRL_5_BITS ( ( unsigned int ) 0x0 << 6 ) /* (USART) Character Length: 5 bits */ +#define AT91C_US_CHRL_6_BITS ( ( unsigned int ) 0x1 << 6 ) /* (USART) Character Length: 6 bits */ +#define AT91C_US_CHRL_7_BITS ( ( unsigned int ) 0x2 << 6 ) /* (USART) Character Length: 7 bits */ +#define AT91C_US_CHRL_8_BITS ( ( unsigned int ) 0x3 << 6 ) /* (USART) Character Length: 8 bits */ +#define AT91C_US_SYNC ( ( unsigned int ) 0x1 << 8 ) /* (USART) Synchronous Mode Select */ +#define AT91C_US_NBSTOP ( ( unsigned int ) 0x3 << 12 ) /* (USART) Number of Stop bits */ +#define AT91C_US_NBSTOP_1_BIT ( ( unsigned int ) 0x0 << 12 ) /* (USART) 1 stop bit */ +#define AT91C_US_NBSTOP_15_BIT ( ( unsigned int ) 0x1 << 12 ) /* (USART) Asynchronous (SYNC=0) 2 stop bits Synchronous (SYNC=1) 2 stop bits */ +#define AT91C_US_NBSTOP_2_BIT ( ( unsigned int ) 0x2 << 12 ) /* (USART) 2 stop bits */ +#define AT91C_US_MSBF ( ( unsigned int ) 0x1 << 16 ) /* (USART) Bit Order */ +#define AT91C_US_MODE9 ( ( unsigned int ) 0x1 << 17 ) /* (USART) 9-bit Character length */ +#define AT91C_US_CKLO ( ( unsigned int ) 0x1 << 18 ) /* (USART) Clock Output Select */ +#define AT91C_US_OVER ( ( unsigned int ) 0x1 << 19 ) /* (USART) Over Sampling Mode */ +#define AT91C_US_INACK ( ( unsigned int ) 0x1 << 20 ) /* (USART) Inhibit Non Acknowledge */ +#define AT91C_US_DSNACK ( ( unsigned int ) 0x1 << 21 ) /* (USART) Disable Successive NACK */ +#define AT91C_US_MAX_ITER ( ( unsigned int ) 0x1 << 24 ) /* (USART) Number of Repetitions */ +#define AT91C_US_FILTER ( ( unsigned int ) 0x1 << 28 ) /* (USART) Receive Line Filter */ +/* -------- US_IER : (USART Offset: 0x8) Debug Unit Interrupt Enable Register -------- */ +#define AT91C_US_RXBRK ( ( unsigned int ) 0x1 << 2 ) /* (USART) Break Received/End of Break */ +#define AT91C_US_TIMEOUT ( ( unsigned int ) 0x1 << 8 ) /* (USART) Receiver Time-out */ +#define AT91C_US_ITERATION ( ( unsigned int ) 0x1 << 10 ) /* (USART) Max number of Repetitions Reached */ +#define AT91C_US_NACK ( ( unsigned int ) 0x1 << 13 ) /* (USART) Non Acknowledge */ +#define AT91C_US_RIIC ( ( unsigned int ) 0x1 << 16 ) /* (USART) Ring INdicator Input Change Flag */ +#define AT91C_US_DSRIC ( ( unsigned int ) 0x1 << 17 ) /* (USART) Data Set Ready Input Change Flag */ +#define AT91C_US_DCDIC ( ( unsigned int ) 0x1 << 18 ) /* (USART) Data Carrier Flag */ +#define AT91C_US_CTSIC ( ( unsigned int ) 0x1 << 19 ) /* (USART) Clear To Send Input Change Flag */ +/* -------- US_IDR : (USART Offset: 0xc) Debug Unit Interrupt Disable Register -------- */ +/* -------- US_IMR : (USART Offset: 0x10) Debug Unit Interrupt Mask Register -------- */ +/* -------- US_CSR : (USART Offset: 0x14) Debug Unit Channel Status Register -------- */ +#define AT91C_US_RI ( ( unsigned int ) 0x1 << 20 ) /* (USART) Image of RI Input */ +#define AT91C_US_DSR ( ( unsigned int ) 0x1 << 21 ) /* (USART) Image of DSR Input */ +#define AT91C_US_DCD ( ( unsigned int ) 0x1 << 22 ) /* (USART) Image of DCD Input */ +#define AT91C_US_CTS ( ( unsigned int ) 0x1 << 23 ) /* (USART) Image of CTS Input */ + +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR Synchronous Serial Controller Interface */ +/* ***************************************************************************** */ +typedef struct _AT91S_SSC +{ + AT91_REG SSC_CR; /* Control Register */ + AT91_REG SSC_CMR; /* Clock Mode Register */ + AT91_REG Reserved0[ 2 ]; /* */ + AT91_REG SSC_RCMR; /* Receive Clock ModeRegister */ + AT91_REG SSC_RFMR; /* Receive Frame Mode Register */ + AT91_REG SSC_TCMR; /* Transmit Clock Mode Register */ + AT91_REG SSC_TFMR; /* Transmit Frame Mode Register */ + AT91_REG SSC_RHR; /* Receive Holding Register */ + AT91_REG SSC_THR; /* Transmit Holding Register */ + AT91_REG Reserved1[ 2 ]; /* */ + AT91_REG SSC_RSHR; /* Receive Sync Holding Register */ + AT91_REG SSC_TSHR; /* Transmit Sync Holding Register */ + AT91_REG Reserved2[ 2 ]; /* */ + AT91_REG SSC_SR; /* Status Register */ + AT91_REG SSC_IER; /* Interrupt Enable Register */ + AT91_REG SSC_IDR; /* Interrupt Disable Register */ + AT91_REG SSC_IMR; /* Interrupt Mask Register */ + AT91_REG Reserved3[ 44 ]; /* */ + AT91_REG SSC_RPR; /* Receive Pointer Register */ + AT91_REG SSC_RCR; /* Receive Counter Register */ + AT91_REG SSC_TPR; /* Transmit Pointer Register */ + AT91_REG SSC_TCR; /* Transmit Counter Register */ + AT91_REG SSC_RNPR; /* Receive Next Pointer Register */ + AT91_REG SSC_RNCR; /* Receive Next Counter Register */ + AT91_REG SSC_TNPR; /* Transmit Next Pointer Register */ + AT91_REG SSC_TNCR; /* Transmit Next Counter Register */ + AT91_REG SSC_PTCR; /* PDC Transfer Control Register */ + AT91_REG SSC_PTSR; /* PDC Transfer Status Register */ +} AT91S_SSC, * AT91PS_SSC; + +/* -------- SSC_CR : (SSC Offset: 0x0) SSC Control Register -------- */ +#define AT91C_SSC_RXEN ( ( unsigned int ) 0x1 << 0 ) /* (SSC) Receive Enable */ +#define AT91C_SSC_RXDIS ( ( unsigned int ) 0x1 << 1 ) /* (SSC) Receive Disable */ +#define AT91C_SSC_TXEN ( ( unsigned int ) 0x1 << 8 ) /* (SSC) Transmit Enable */ +#define AT91C_SSC_TXDIS ( ( unsigned int ) 0x1 << 9 ) /* (SSC) Transmit Disable */ +#define AT91C_SSC_SWRST ( ( unsigned int ) 0x1 << 15 ) /* (SSC) Software Reset */ +/* -------- SSC_RCMR : (SSC Offset: 0x10) SSC Receive Clock Mode Register -------- */ +#define AT91C_SSC_CKS ( ( unsigned int ) 0x3 << 0 ) /* (SSC) Receive/Transmit Clock Selection */ +#define AT91C_SSC_CKS_DIV ( ( unsigned int ) 0x0 ) /* (SSC) Divided Clock */ +#define AT91C_SSC_CKS_TK ( ( unsigned int ) 0x1 ) /* (SSC) TK Clock signal */ +#define AT91C_SSC_CKS_RK ( ( unsigned int ) 0x2 ) /* (SSC) RK pin */ +#define AT91C_SSC_CKO ( ( unsigned int ) 0x7 << 2 ) /* (SSC) Receive/Transmit Clock Output Mode Selection */ +#define AT91C_SSC_CKO_NONE ( ( unsigned int ) 0x0 << 2 ) /* (SSC) Receive/Transmit Clock Output Mode: None RK pin: Input-only */ +#define AT91C_SSC_CKO_CONTINUOUS ( ( unsigned int ) 0x1 << 2 ) /* (SSC) Continuous Receive/Transmit Clock RK pin: Output */ +#define AT91C_SSC_CKO_DATA_TX ( ( unsigned int ) 0x2 << 2 ) /* (SSC) Receive/Transmit Clock only during data transfers RK pin: Output */ +#define AT91C_SSC_CKI ( ( unsigned int ) 0x1 << 5 ) /* (SSC) Receive/Transmit Clock Inversion */ +#define AT91C_SSC_START ( ( unsigned int ) 0xF << 8 ) /* (SSC) Receive/Transmit Start Selection */ +#define AT91C_SSC_START_CONTINUOUS ( ( unsigned int ) 0x0 << 8 ) /* (SSC) Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data. */ +#define AT91C_SSC_START_TX ( ( unsigned int ) 0x1 << 8 ) /* (SSC) Transmit/Receive start */ +#define AT91C_SSC_START_LOW_RF ( ( unsigned int ) 0x2 << 8 ) /* (SSC) Detection of a low level on RF input */ +#define AT91C_SSC_START_HIGH_RF ( ( unsigned int ) 0x3 << 8 ) /* (SSC) Detection of a high level on RF input */ +#define AT91C_SSC_START_FALL_RF ( ( unsigned int ) 0x4 << 8 ) /* (SSC) Detection of a falling edge on RF input */ +#define AT91C_SSC_START_RISE_RF ( ( unsigned int ) 0x5 << 8 ) /* (SSC) Detection of a rising edge on RF input */ +#define AT91C_SSC_START_LEVEL_RF ( ( unsigned int ) 0x6 << 8 ) /* (SSC) Detection of any level change on RF input */ +#define AT91C_SSC_START_EDGE_RF ( ( unsigned int ) 0x7 << 8 ) /* (SSC) Detection of any edge on RF input */ +#define AT91C_SSC_START_0 ( ( unsigned int ) 0x8 << 8 ) /* (SSC) Compare 0 */ +#define AT91C_SSC_STTDLY ( ( unsigned int ) 0xFF << 16 ) /* (SSC) Receive/Transmit Start Delay */ +#define AT91C_SSC_PERIOD ( ( unsigned int ) 0xFF << 24 ) /* (SSC) Receive/Transmit Period Divider Selection */ +/* -------- SSC_RFMR : (SSC Offset: 0x14) SSC Receive Frame Mode Register -------- */ +#define AT91C_SSC_DATLEN ( ( unsigned int ) 0x1F << 0 ) /* (SSC) Data Length */ +#define AT91C_SSC_LOOP ( ( unsigned int ) 0x1 << 5 ) /* (SSC) Loop Mode */ +#define AT91C_SSC_MSBF ( ( unsigned int ) 0x1 << 7 ) /* (SSC) Most Significant Bit First */ +#define AT91C_SSC_DATNB ( ( unsigned int ) 0xF << 8 ) /* (SSC) Data Number per Frame */ +#define AT91C_SSC_FSLEN ( ( unsigned int ) 0xF << 16 ) /* (SSC) Receive/Transmit Frame Sync length */ +#define AT91C_SSC_FSOS ( ( unsigned int ) 0x7 << 20 ) /* (SSC) Receive/Transmit Frame Sync Output Selection */ +#define AT91C_SSC_FSOS_NONE ( ( unsigned int ) 0x0 << 20 ) /* (SSC) Selected Receive/Transmit Frame Sync Signal: None RK pin Input-only */ +#define AT91C_SSC_FSOS_NEGATIVE ( ( unsigned int ) 0x1 << 20 ) /* (SSC) Selected Receive/Transmit Frame Sync Signal: Negative Pulse */ +#define AT91C_SSC_FSOS_POSITIVE ( ( unsigned int ) 0x2 << 20 ) /* (SSC) Selected Receive/Transmit Frame Sync Signal: Positive Pulse */ +#define AT91C_SSC_FSOS_LOW ( ( unsigned int ) 0x3 << 20 ) /* (SSC) Selected Receive/Transmit Frame Sync Signal: Driver Low during data transfer */ +#define AT91C_SSC_FSOS_HIGH ( ( unsigned int ) 0x4 << 20 ) /* (SSC) Selected Receive/Transmit Frame Sync Signal: Driver High during data transfer */ +#define AT91C_SSC_FSOS_TOGGLE ( ( unsigned int ) 0x5 << 20 ) /* (SSC) Selected Receive/Transmit Frame Sync Signal: Toggling at each start of data transfer */ +#define AT91C_SSC_FSEDGE ( ( unsigned int ) 0x1 << 24 ) /* (SSC) Frame Sync Edge Detection */ +/* -------- SSC_TCMR : (SSC Offset: 0x18) SSC Transmit Clock Mode Register -------- */ +/* -------- SSC_TFMR : (SSC Offset: 0x1c) SSC Transmit Frame Mode Register -------- */ +#define AT91C_SSC_DATDEF ( ( unsigned int ) 0x1 << 5 ) /* (SSC) Data Default Value */ +#define AT91C_SSC_FSDEN ( ( unsigned int ) 0x1 << 23 ) /* (SSC) Frame Sync Data Enable */ +/* -------- SSC_SR : (SSC Offset: 0x40) SSC Status Register -------- */ +#define AT91C_SSC_TXRDY ( ( unsigned int ) 0x1 << 0 ) /* (SSC) Transmit Ready */ +#define AT91C_SSC_TXEMPTY ( ( unsigned int ) 0x1 << 1 ) /* (SSC) Transmit Empty */ +#define AT91C_SSC_ENDTX ( ( unsigned int ) 0x1 << 2 ) /* (SSC) End Of Transmission */ +#define AT91C_SSC_TXBUFE ( ( unsigned int ) 0x1 << 3 ) /* (SSC) Transmit Buffer Empty */ +#define AT91C_SSC_RXRDY ( ( unsigned int ) 0x1 << 4 ) /* (SSC) Receive Ready */ +#define AT91C_SSC_OVRUN ( ( unsigned int ) 0x1 << 5 ) /* (SSC) Receive Overrun */ +#define AT91C_SSC_ENDRX ( ( unsigned int ) 0x1 << 6 ) /* (SSC) End of Reception */ +#define AT91C_SSC_RXBUFF ( ( unsigned int ) 0x1 << 7 ) /* (SSC) Receive Buffer Full */ +#define AT91C_SSC_TXSYN ( ( unsigned int ) 0x1 << 10 ) /* (SSC) Transmit Sync */ +#define AT91C_SSC_RXSYN ( ( unsigned int ) 0x1 << 11 ) /* (SSC) Receive Sync */ +#define AT91C_SSC_TXENA ( ( unsigned int ) 0x1 << 16 ) /* (SSC) Transmit Enable */ +#define AT91C_SSC_RXENA ( ( unsigned int ) 0x1 << 17 ) /* (SSC) Receive Enable */ +/* -------- SSC_IER : (SSC Offset: 0x44) SSC Interrupt Enable Register -------- */ +/* -------- SSC_IDR : (SSC Offset: 0x48) SSC Interrupt Disable Register -------- */ +/* -------- SSC_IMR : (SSC Offset: 0x4c) SSC Interrupt Mask Register -------- */ + +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR Two-wire Interface */ +/* ***************************************************************************** */ +typedef struct _AT91S_TWI +{ + AT91_REG TWI_CR; /* Control Register */ + AT91_REG TWI_MMR; /* Master Mode Register */ + AT91_REG Reserved0[ 1 ]; /* */ + AT91_REG TWI_IADR; /* Internal Address Register */ + AT91_REG TWI_CWGR; /* Clock Waveform Generator Register */ + AT91_REG Reserved1[ 3 ]; /* */ + AT91_REG TWI_SR; /* Status Register */ + AT91_REG TWI_IER; /* Interrupt Enable Register */ + AT91_REG TWI_IDR; /* Interrupt Disable Register */ + AT91_REG TWI_IMR; /* Interrupt Mask Register */ + AT91_REG TWI_RHR; /* Receive Holding Register */ + AT91_REG TWI_THR; /* Transmit Holding Register */ +} AT91S_TWI, * AT91PS_TWI; + +/* -------- TWI_CR : (TWI Offset: 0x0) TWI Control Register -------- */ +#define AT91C_TWI_START ( ( unsigned int ) 0x1 << 0 ) /* (TWI) Send a START Condition */ +#define AT91C_TWI_STOP ( ( unsigned int ) 0x1 << 1 ) /* (TWI) Send a STOP Condition */ +#define AT91C_TWI_MSEN ( ( unsigned int ) 0x1 << 2 ) /* (TWI) TWI Master Transfer Enabled */ +#define AT91C_TWI_MSDIS ( ( unsigned int ) 0x1 << 3 ) /* (TWI) TWI Master Transfer Disabled */ +#define AT91C_TWI_SWRST ( ( unsigned int ) 0x1 << 7 ) /* (TWI) Software Reset */ +/* -------- TWI_MMR : (TWI Offset: 0x4) TWI Master Mode Register -------- */ +#define AT91C_TWI_IADRSZ ( ( unsigned int ) 0x3 << 8 ) /* (TWI) Internal Device Address Size */ +#define AT91C_TWI_IADRSZ_NO ( ( unsigned int ) 0x0 << 8 ) /* (TWI) No internal device address */ +#define AT91C_TWI_IADRSZ_1_BYTE ( ( unsigned int ) 0x1 << 8 ) /* (TWI) One-byte internal device address */ +#define AT91C_TWI_IADRSZ_2_BYTE ( ( unsigned int ) 0x2 << 8 ) /* (TWI) Two-byte internal device address */ +#define AT91C_TWI_IADRSZ_3_BYTE ( ( unsigned int ) 0x3 << 8 ) /* (TWI) Three-byte internal device address */ +#define AT91C_TWI_MREAD ( ( unsigned int ) 0x1 << 12 ) /* (TWI) Master Read Direction */ +#define AT91C_TWI_DADR ( ( unsigned int ) 0x7F << 16 ) /* (TWI) Device Address */ +/* -------- TWI_CWGR : (TWI Offset: 0x10) TWI Clock Waveform Generator Register -------- */ +#define AT91C_TWI_CLDIV ( ( unsigned int ) 0xFF << 0 ) /* (TWI) Clock Low Divider */ +#define AT91C_TWI_CHDIV ( ( unsigned int ) 0xFF << 8 ) /* (TWI) Clock High Divider */ +#define AT91C_TWI_CKDIV ( ( unsigned int ) 0x7 << 16 ) /* (TWI) Clock Divider */ +/* -------- TWI_SR : (TWI Offset: 0x20) TWI Status Register -------- */ +#define AT91C_TWI_TXCOMP ( ( unsigned int ) 0x1 << 0 ) /* (TWI) Transmission Completed */ +#define AT91C_TWI_RXRDY ( ( unsigned int ) 0x1 << 1 ) /* (TWI) Receive holding register ReaDY */ +#define AT91C_TWI_TXRDY ( ( unsigned int ) 0x1 << 2 ) /* (TWI) Transmit holding register ReaDY */ +#define AT91C_TWI_OVRE ( ( unsigned int ) 0x1 << 6 ) /* (TWI) Overrun Error */ +#define AT91C_TWI_UNRE ( ( unsigned int ) 0x1 << 7 ) /* (TWI) Underrun Error */ +#define AT91C_TWI_NACK ( ( unsigned int ) 0x1 << 8 ) /* (TWI) Not Acknowledged */ +/* -------- TWI_IER : (TWI Offset: 0x24) TWI Interrupt Enable Register -------- */ +/* -------- TWI_IDR : (TWI Offset: 0x28) TWI Interrupt Disable Register -------- */ +/* -------- TWI_IMR : (TWI Offset: 0x2c) TWI Interrupt Mask Register -------- */ + +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR PWMC Channel Interface */ +/* ***************************************************************************** */ +typedef struct _AT91S_PWMC_CH +{ + AT91_REG PWMC_CMR; /* Channel Mode Register */ + AT91_REG PWMC_CDTYR; /* Channel Duty Cycle Register */ + AT91_REG PWMC_CPRDR; /* Channel Period Register */ + AT91_REG PWMC_CCNTR; /* Channel Counter Register */ + AT91_REG PWMC_CUPDR; /* Channel Update Register */ + AT91_REG PWMC_Reserved[ 3 ]; /* Reserved */ +} AT91S_PWMC_CH, * AT91PS_PWMC_CH; + +/* -------- PWMC_CMR : (PWMC_CH Offset: 0x0) PWMC Channel Mode Register -------- */ +#define AT91C_PWMC_CPRE ( ( unsigned int ) 0xF << 0 ) /* (PWMC_CH) Channel Pre-scaler : PWMC_CLKx */ +#define AT91C_PWMC_CPRE_MCK ( ( unsigned int ) 0x0 ) /* (PWMC_CH) */ +#define AT91C_PWMC_CPRE_MCKA ( ( unsigned int ) 0xB ) /* (PWMC_CH) */ +#define AT91C_PWMC_CPRE_MCKB ( ( unsigned int ) 0xC ) /* (PWMC_CH) */ +#define AT91C_PWMC_CALG ( ( unsigned int ) 0x1 << 8 ) /* (PWMC_CH) Channel Alignment */ +#define AT91C_PWMC_CPOL ( ( unsigned int ) 0x1 << 9 ) /* (PWMC_CH) Channel Polarity */ +#define AT91C_PWMC_CPD ( ( unsigned int ) 0x1 << 10 ) /* (PWMC_CH) Channel Update Period */ +/* -------- PWMC_CDTYR : (PWMC_CH Offset: 0x4) PWMC Channel Duty Cycle Register -------- */ +#define AT91C_PWMC_CDTY ( ( unsigned int ) 0x0 << 0 ) /* (PWMC_CH) Channel Duty Cycle */ +/* -------- PWMC_CPRDR : (PWMC_CH Offset: 0x8) PWMC Channel Period Register -------- */ +#define AT91C_PWMC_CPRD ( ( unsigned int ) 0x0 << 0 ) /* (PWMC_CH) Channel Period */ +/* -------- PWMC_CCNTR : (PWMC_CH Offset: 0xc) PWMC Channel Counter Register -------- */ +#define AT91C_PWMC_CCNT ( ( unsigned int ) 0x0 << 0 ) /* (PWMC_CH) Channel Counter */ +/* -------- PWMC_CUPDR : (PWMC_CH Offset: 0x10) PWMC Channel Update Register -------- */ +#define AT91C_PWMC_CUPD ( ( unsigned int ) 0x0 << 0 ) /* (PWMC_CH) Channel Update */ + +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR Pulse Width Modulation Controller Interface */ +/* ***************************************************************************** */ +typedef struct _AT91S_PWMC +{ + AT91_REG PWMC_MR; /* PWMC Mode Register */ + AT91_REG PWMC_ENA; /* PWMC Enable Register */ + AT91_REG PWMC_DIS; /* PWMC Disable Register */ + AT91_REG PWMC_SR; /* PWMC Status Register */ + AT91_REG PWMC_IER; /* PWMC Interrupt Enable Register */ + AT91_REG PWMC_IDR; /* PWMC Interrupt Disable Register */ + AT91_REG PWMC_IMR; /* PWMC Interrupt Mask Register */ + AT91_REG PWMC_ISR; /* PWMC Interrupt Status Register */ + AT91_REG Reserved0[ 55 ]; /* */ + AT91_REG PWMC_VR; /* PWMC Version Register */ + AT91_REG Reserved1[ 64 ]; /* */ + AT91S_PWMC_CH PWMC_CH[ 4 ]; /* PWMC Channel */ +} AT91S_PWMC, * AT91PS_PWMC; + +/* -------- PWMC_MR : (PWMC Offset: 0x0) PWMC Mode Register -------- */ +#define AT91C_PWMC_DIVA ( ( unsigned int ) 0xFF << 0 ) /* (PWMC) CLKA divide factor. */ +#define AT91C_PWMC_PREA ( ( unsigned int ) 0xF << 8 ) /* (PWMC) Divider Input Clock Prescaler A */ +#define AT91C_PWMC_PREA_MCK ( ( unsigned int ) 0x0 << 8 ) /* (PWMC) */ +#define AT91C_PWMC_DIVB ( ( unsigned int ) 0xFF << 16 ) /* (PWMC) CLKB divide factor. */ +#define AT91C_PWMC_PREB ( ( unsigned int ) 0xF << 24 ) /* (PWMC) Divider Input Clock Prescaler B */ +#define AT91C_PWMC_PREB_MCK ( ( unsigned int ) 0x0 << 24 ) /* (PWMC) */ +/* -------- PWMC_ENA : (PWMC Offset: 0x4) PWMC Enable Register -------- */ +#define AT91C_PWMC_CHID0 ( ( unsigned int ) 0x1 << 0 ) /* (PWMC) Channel ID 0 */ +#define AT91C_PWMC_CHID1 ( ( unsigned int ) 0x1 << 1 ) /* (PWMC) Channel ID 1 */ +#define AT91C_PWMC_CHID2 ( ( unsigned int ) 0x1 << 2 ) /* (PWMC) Channel ID 2 */ +#define AT91C_PWMC_CHID3 ( ( unsigned int ) 0x1 << 3 ) /* (PWMC) Channel ID 3 */ +/* -------- PWMC_DIS : (PWMC Offset: 0x8) PWMC Disable Register -------- */ +/* -------- PWMC_SR : (PWMC Offset: 0xc) PWMC Status Register -------- */ +/* -------- PWMC_IER : (PWMC Offset: 0x10) PWMC Interrupt Enable Register -------- */ +/* -------- PWMC_IDR : (PWMC Offset: 0x14) PWMC Interrupt Disable Register -------- */ +/* -------- PWMC_IMR : (PWMC Offset: 0x18) PWMC Interrupt Mask Register -------- */ +/* -------- PWMC_ISR : (PWMC Offset: 0x1c) PWMC Interrupt Status Register -------- */ + +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR USB Device Interface */ +/* ***************************************************************************** */ +typedef struct _AT91S_UDP +{ + AT91_REG UDP_NUM; /* Frame Number Register */ + AT91_REG UDP_GLBSTATE; /* Global State Register */ + AT91_REG UDP_FADDR; /* Function Address Register */ + AT91_REG Reserved0[ 1 ]; /* */ + AT91_REG UDP_IER; /* Interrupt Enable Register */ + AT91_REG UDP_IDR; /* Interrupt Disable Register */ + AT91_REG UDP_IMR; /* Interrupt Mask Register */ + AT91_REG UDP_ISR; /* Interrupt Status Register */ + AT91_REG UDP_ICR; /* Interrupt Clear Register */ + AT91_REG Reserved1[ 1 ]; /* */ + AT91_REG UDP_RSTEP; /* Reset Endpoint Register */ + AT91_REG Reserved2[ 1 ]; /* */ + AT91_REG UDP_CSR[ 6 ]; /* Endpoint Control and Status Register */ + AT91_REG Reserved3[ 2 ]; /* */ + AT91_REG UDP_FDR[ 6 ]; /* Endpoint FIFO Data Register */ + AT91_REG Reserved4[ 3 ]; /* */ + AT91_REG UDP_TXVC; /* Transceiver Control Register */ +} AT91S_UDP, * AT91PS_UDP; + +/* -------- UDP_FRM_NUM : (UDP Offset: 0x0) USB Frame Number Register -------- */ +#define AT91C_UDP_FRM_NUM ( ( unsigned int ) 0x7FF << 0 ) /* (UDP) Frame Number as Defined in the Packet Field Formats */ +#define AT91C_UDP_FRM_ERR ( ( unsigned int ) 0x1 << 16 ) /* (UDP) Frame Error */ +#define AT91C_UDP_FRM_OK ( ( unsigned int ) 0x1 << 17 ) /* (UDP) Frame OK */ +/* -------- UDP_GLB_STATE : (UDP Offset: 0x4) USB Global State Register -------- */ +#define AT91C_UDP_FADDEN ( ( unsigned int ) 0x1 << 0 ) /* (UDP) Function Address Enable */ +#define AT91C_UDP_CONFG ( ( unsigned int ) 0x1 << 1 ) /* (UDP) Configured */ +#define AT91C_UDP_ESR ( ( unsigned int ) 0x1 << 2 ) /* (UDP) Enable Send Resume */ +#define AT91C_UDP_RSMINPR ( ( unsigned int ) 0x1 << 3 ) /* (UDP) A Resume Has Been Sent to the Host */ +#define AT91C_UDP_RMWUPE ( ( unsigned int ) 0x1 << 4 ) /* (UDP) Remote Wake Up Enable */ +/* -------- UDP_FADDR : (UDP Offset: 0x8) USB Function Address Register -------- */ +#define AT91C_UDP_FADD ( ( unsigned int ) 0xFF << 0 ) /* (UDP) Function Address Value */ +#define AT91C_UDP_FEN ( ( unsigned int ) 0x1 << 8 ) /* (UDP) Function Enable */ +/* -------- UDP_IER : (UDP Offset: 0x10) USB Interrupt Enable Register -------- */ +#define AT91C_UDP_EPINT0 ( ( unsigned int ) 0x1 << 0 ) /* (UDP) Endpoint 0 Interrupt */ +#define AT91C_UDP_EPINT1 ( ( unsigned int ) 0x1 << 1 ) /* (UDP) Endpoint 0 Interrupt */ +#define AT91C_UDP_EPINT2 ( ( unsigned int ) 0x1 << 2 ) /* (UDP) Endpoint 2 Interrupt */ +#define AT91C_UDP_EPINT3 ( ( unsigned int ) 0x1 << 3 ) /* (UDP) Endpoint 3 Interrupt */ +#define AT91C_UDP_EPINT4 ( ( unsigned int ) 0x1 << 4 ) /* (UDP) Endpoint 4 Interrupt */ +#define AT91C_UDP_EPINT5 ( ( unsigned int ) 0x1 << 5 ) /* (UDP) Endpoint 5 Interrupt */ +#define AT91C_UDP_RXSUSP ( ( unsigned int ) 0x1 << 8 ) /* (UDP) USB Suspend Interrupt */ +#define AT91C_UDP_RXRSM ( ( unsigned int ) 0x1 << 9 ) /* (UDP) USB Resume Interrupt */ +#define AT91C_UDP_EXTRSM ( ( unsigned int ) 0x1 << 10 ) /* (UDP) USB External Resume Interrupt */ +#define AT91C_UDP_SOFINT ( ( unsigned int ) 0x1 << 11 ) /* (UDP) USB Start Of frame Interrupt */ +#define AT91C_UDP_WAKEUP ( ( unsigned int ) 0x1 << 13 ) /* (UDP) USB Resume Interrupt */ +/* -------- UDP_IDR : (UDP Offset: 0x14) USB Interrupt Disable Register -------- */ +/* -------- UDP_IMR : (UDP Offset: 0x18) USB Interrupt Mask Register -------- */ +/* -------- UDP_ISR : (UDP Offset: 0x1c) USB Interrupt Status Register -------- */ +#define AT91C_UDP_ENDBUSRES ( ( unsigned int ) 0x1 << 12 ) /* (UDP) USB End Of Bus Reset Interrupt */ +/* -------- UDP_ICR : (UDP Offset: 0x20) USB Interrupt Clear Register -------- */ +/* -------- UDP_RST_EP : (UDP Offset: 0x28) USB Reset Endpoint Register -------- */ +#define AT91C_UDP_EP0 ( ( unsigned int ) 0x1 << 0 ) /* (UDP) Reset Endpoint 0 */ +#define AT91C_UDP_EP1 ( ( unsigned int ) 0x1 << 1 ) /* (UDP) Reset Endpoint 1 */ +#define AT91C_UDP_EP2 ( ( unsigned int ) 0x1 << 2 ) /* (UDP) Reset Endpoint 2 */ +#define AT91C_UDP_EP3 ( ( unsigned int ) 0x1 << 3 ) /* (UDP) Reset Endpoint 3 */ +#define AT91C_UDP_EP4 ( ( unsigned int ) 0x1 << 4 ) /* (UDP) Reset Endpoint 4 */ +#define AT91C_UDP_EP5 ( ( unsigned int ) 0x1 << 5 ) /* (UDP) Reset Endpoint 5 */ +/* -------- UDP_CSR : (UDP Offset: 0x30) USB Endpoint Control and Status Register -------- */ +#define AT91C_UDP_TXCOMP ( ( unsigned int ) 0x1 << 0 ) /* (UDP) Generates an IN packet with data previously written in the DPR */ +#define AT91C_UDP_RX_DATA_BK0 ( ( unsigned int ) 0x1 << 1 ) /* (UDP) Receive Data Bank 0 */ +#define AT91C_UDP_RXSETUP ( ( unsigned int ) 0x1 << 2 ) /* (UDP) Sends STALL to the Host (Control endpoints) */ +#define AT91C_UDP_ISOERROR ( ( unsigned int ) 0x1 << 3 ) /* (UDP) Isochronous error (Isochronous endpoints) */ +#define AT91C_UDP_TXPKTRDY ( ( unsigned int ) 0x1 << 4 ) /* (UDP) Transmit Packet Ready */ +#define AT91C_UDP_FORCESTALL ( ( unsigned int ) 0x1 << 5 ) /* (UDP) Force Stall (used by Control, Bulk and Isochronous endpoints). */ +#define AT91C_UDP_RX_DATA_BK1 ( ( unsigned int ) 0x1 << 6 ) /* (UDP) Receive Data Bank 1 (only used by endpoints with ping-pong attributes). */ +#define AT91C_UDP_DIR ( ( unsigned int ) 0x1 << 7 ) /* (UDP) Transfer Direction */ +#define AT91C_UDP_EPTYPE ( ( unsigned int ) 0x7 << 8 ) /* (UDP) Endpoint type */ +#define AT91C_UDP_EPTYPE_CTRL ( ( unsigned int ) 0x0 << 8 ) /* (UDP) Control */ +#define AT91C_UDP_EPTYPE_ISO_OUT ( ( unsigned int ) 0x1 << 8 ) /* (UDP) Isochronous OUT */ +#define AT91C_UDP_EPTYPE_BULK_OUT ( ( unsigned int ) 0x2 << 8 ) /* (UDP) Bulk OUT */ +#define AT91C_UDP_EPTYPE_INT_OUT ( ( unsigned int ) 0x3 << 8 ) /* (UDP) Interrupt OUT */ +#define AT91C_UDP_EPTYPE_ISO_IN ( ( unsigned int ) 0x5 << 8 ) /* (UDP) Isochronous IN */ +#define AT91C_UDP_EPTYPE_BULK_IN ( ( unsigned int ) 0x6 << 8 ) /* (UDP) Bulk IN */ +#define AT91C_UDP_EPTYPE_INT_IN ( ( unsigned int ) 0x7 << 8 ) /* (UDP) Interrupt IN */ +#define AT91C_UDP_DTGLE ( ( unsigned int ) 0x1 << 11 ) /* (UDP) Data Toggle */ +#define AT91C_UDP_EPEDS ( ( unsigned int ) 0x1 << 15 ) /* (UDP) Endpoint Enable Disable */ +#define AT91C_UDP_RXBYTECNT ( ( unsigned int ) 0x7FF << 16 ) /* (UDP) Number Of Bytes Available in the FIFO */ +/* -------- UDP_TXVC : (UDP Offset: 0x74) Transceiver Control Register -------- */ +#define AT91C_UDP_TXVDIS ( ( unsigned int ) 0x1 << 8 ) /* (UDP) */ +#define AT91C_UDP_PUON ( ( unsigned int ) 0x1 << 9 ) /* (UDP) Pull-up ON */ + +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR Timer Counter Channel Interface */ +/* ***************************************************************************** */ +typedef struct _AT91S_TC +{ + AT91_REG TC_CCR; /* Channel Control Register */ + AT91_REG TC_CMR; /* Channel Mode Register (Capture Mode / Waveform Mode) */ + AT91_REG Reserved0[ 2 ]; /* */ + AT91_REG TC_CV; /* Counter Value */ + AT91_REG TC_RA; /* Register A */ + AT91_REG TC_RB; /* Register B */ + AT91_REG TC_RC; /* Register C */ + AT91_REG TC_SR; /* Status Register */ + AT91_REG TC_IER; /* Interrupt Enable Register */ + AT91_REG TC_IDR; /* Interrupt Disable Register */ + AT91_REG TC_IMR; /* Interrupt Mask Register */ +} AT91S_TC, * AT91PS_TC; + +/* -------- TC_CCR : (TC Offset: 0x0) TC Channel Control Register -------- */ +#define AT91C_TC_CLKEN ( ( unsigned int ) 0x1 << 0 ) /* (TC) Counter Clock Enable Command */ +#define AT91C_TC_CLKDIS ( ( unsigned int ) 0x1 << 1 ) /* (TC) Counter Clock Disable Command */ +#define AT91C_TC_SWTRG ( ( unsigned int ) 0x1 << 2 ) /* (TC) Software Trigger Command */ +/* -------- TC_CMR : (TC Offset: 0x4) TC Channel Mode Register: Capture Mode / Waveform Mode -------- */ +#define AT91C_TC_CLKS ( ( unsigned int ) 0x7 << 0 ) /* (TC) Clock Selection */ +#define AT91C_TC_CLKS_TIMER_DIV1_CLOCK ( ( unsigned int ) 0x0 ) /* (TC) Clock selected: TIMER_DIV1_CLOCK */ +#define AT91C_TC_CLKS_TIMER_DIV2_CLOCK ( ( unsigned int ) 0x1 ) /* (TC) Clock selected: TIMER_DIV2_CLOCK */ +#define AT91C_TC_CLKS_TIMER_DIV3_CLOCK ( ( unsigned int ) 0x2 ) /* (TC) Clock selected: TIMER_DIV3_CLOCK */ +#define AT91C_TC_CLKS_TIMER_DIV4_CLOCK ( ( unsigned int ) 0x3 ) /* (TC) Clock selected: TIMER_DIV4_CLOCK */ +#define AT91C_TC_CLKS_TIMER_DIV5_CLOCK ( ( unsigned int ) 0x4 ) /* (TC) Clock selected: TIMER_DIV5_CLOCK */ +#define AT91C_TC_CLKS_XC0 ( ( unsigned int ) 0x5 ) /* (TC) Clock selected: XC0 */ +#define AT91C_TC_CLKS_XC1 ( ( unsigned int ) 0x6 ) /* (TC) Clock selected: XC1 */ +#define AT91C_TC_CLKS_XC2 ( ( unsigned int ) 0x7 ) /* (TC) Clock selected: XC2 */ +#define AT91C_TC_CLKI ( ( unsigned int ) 0x1 << 3 ) /* (TC) Clock Invert */ +#define AT91C_TC_BURST ( ( unsigned int ) 0x3 << 4 ) /* (TC) Burst Signal Selection */ +#define AT91C_TC_BURST_NONE ( ( unsigned int ) 0x0 << 4 ) /* (TC) The clock is not gated by an external signal */ +#define AT91C_TC_BURST_XC0 ( ( unsigned int ) 0x1 << 4 ) /* (TC) XC0 is ANDed with the selected clock */ +#define AT91C_TC_BURST_XC1 ( ( unsigned int ) 0x2 << 4 ) /* (TC) XC1 is ANDed with the selected clock */ +#define AT91C_TC_BURST_XC2 ( ( unsigned int ) 0x3 << 4 ) /* (TC) XC2 is ANDed with the selected clock */ +#define AT91C_TC_CPCSTOP ( ( unsigned int ) 0x1 << 6 ) /* (TC) Counter Clock Stopped with RC Compare */ +#define AT91C_TC_LDBSTOP ( ( unsigned int ) 0x1 << 6 ) /* (TC) Counter Clock Stopped with RB Loading */ +#define AT91C_TC_CPCDIS ( ( unsigned int ) 0x1 << 7 ) /* (TC) Counter Clock Disable with RC Compare */ +#define AT91C_TC_LDBDIS ( ( unsigned int ) 0x1 << 7 ) /* (TC) Counter Clock Disabled with RB Loading */ +#define AT91C_TC_ETRGEDG ( ( unsigned int ) 0x3 << 8 ) /* (TC) External Trigger Edge Selection */ +#define AT91C_TC_ETRGEDG_NONE ( ( unsigned int ) 0x0 << 8 ) /* (TC) Edge: None */ +#define AT91C_TC_ETRGEDG_RISING ( ( unsigned int ) 0x1 << 8 ) /* (TC) Edge: rising edge */ +#define AT91C_TC_ETRGEDG_FALLING ( ( unsigned int ) 0x2 << 8 ) /* (TC) Edge: falling edge */ +#define AT91C_TC_ETRGEDG_BOTH ( ( unsigned int ) 0x3 << 8 ) /* (TC) Edge: each edge */ +#define AT91C_TC_EEVTEDG ( ( unsigned int ) 0x3 << 8 ) /* (TC) External Event Edge Selection */ +#define AT91C_TC_EEVTEDG_NONE ( ( unsigned int ) 0x0 << 8 ) /* (TC) Edge: None */ +#define AT91C_TC_EEVTEDG_RISING ( ( unsigned int ) 0x1 << 8 ) /* (TC) Edge: rising edge */ +#define AT91C_TC_EEVTEDG_FALLING ( ( unsigned int ) 0x2 << 8 ) /* (TC) Edge: falling edge */ +#define AT91C_TC_EEVTEDG_BOTH ( ( unsigned int ) 0x3 << 8 ) /* (TC) Edge: each edge */ +#define AT91C_TC_EEVT ( ( unsigned int ) 0x3 << 10 ) /* (TC) External Event Selection */ +#define AT91C_TC_EEVT_TIOB ( ( unsigned int ) 0x0 << 10 ) /* (TC) Signal selected as external event: TIOB TIOB direction: input */ +#define AT91C_TC_EEVT_XC0 ( ( unsigned int ) 0x1 << 10 ) /* (TC) Signal selected as external event: XC0 TIOB direction: output */ +#define AT91C_TC_EEVT_XC1 ( ( unsigned int ) 0x2 << 10 ) /* (TC) Signal selected as external event: XC1 TIOB direction: output */ +#define AT91C_TC_EEVT_XC2 ( ( unsigned int ) 0x3 << 10 ) /* (TC) Signal selected as external event: XC2 TIOB direction: output */ +#define AT91C_TC_ABETRG ( ( unsigned int ) 0x1 << 10 ) /* (TC) TIOA or TIOB External Trigger Selection */ +#define AT91C_TC_ENETRG ( ( unsigned int ) 0x1 << 12 ) /* (TC) External Event Trigger enable */ +#define AT91C_TC_WAVESEL ( ( unsigned int ) 0x3 << 13 ) /* (TC) Waveform Selection */ +#define AT91C_TC_WAVESEL_UP ( ( unsigned int ) 0x0 << 13 ) /* (TC) UP mode without atomatic trigger on RC Compare */ +#define AT91C_TC_WAVESEL_UPDOWN ( ( unsigned int ) 0x1 << 13 ) /* (TC) UPDOWN mode without automatic trigger on RC Compare */ +#define AT91C_TC_WAVESEL_UP_AUTO ( ( unsigned int ) 0x2 << 13 ) /* (TC) UP mode with automatic trigger on RC Compare */ +#define AT91C_TC_WAVESEL_UPDOWN_AUTO ( ( unsigned int ) 0x3 << 13 ) /* (TC) UPDOWN mode with automatic trigger on RC Compare */ +#define AT91C_TC_CPCTRG ( ( unsigned int ) 0x1 << 14 ) /* (TC) RC Compare Trigger Enable */ +#define AT91C_TC_WAVE ( ( unsigned int ) 0x1 << 15 ) /* (TC) */ +#define AT91C_TC_ACPA ( ( unsigned int ) 0x3 << 16 ) /* (TC) RA Compare Effect on TIOA */ +#define AT91C_TC_ACPA_NONE ( ( unsigned int ) 0x0 << 16 ) /* (TC) Effect: none */ +#define AT91C_TC_ACPA_SET ( ( unsigned int ) 0x1 << 16 ) /* (TC) Effect: set */ +#define AT91C_TC_ACPA_CLEAR ( ( unsigned int ) 0x2 << 16 ) /* (TC) Effect: clear */ +#define AT91C_TC_ACPA_TOGGLE ( ( unsigned int ) 0x3 << 16 ) /* (TC) Effect: toggle */ +#define AT91C_TC_LDRA ( ( unsigned int ) 0x3 << 16 ) /* (TC) RA Loading Selection */ +#define AT91C_TC_LDRA_NONE ( ( unsigned int ) 0x0 << 16 ) /* (TC) Edge: None */ +#define AT91C_TC_LDRA_RISING ( ( unsigned int ) 0x1 << 16 ) /* (TC) Edge: rising edge of TIOA */ +#define AT91C_TC_LDRA_FALLING ( ( unsigned int ) 0x2 << 16 ) /* (TC) Edge: falling edge of TIOA */ +#define AT91C_TC_LDRA_BOTH ( ( unsigned int ) 0x3 << 16 ) /* (TC) Edge: each edge of TIOA */ +#define AT91C_TC_ACPC ( ( unsigned int ) 0x3 << 18 ) /* (TC) RC Compare Effect on TIOA */ +#define AT91C_TC_ACPC_NONE ( ( unsigned int ) 0x0 << 18 ) /* (TC) Effect: none */ +#define AT91C_TC_ACPC_SET ( ( unsigned int ) 0x1 << 18 ) /* (TC) Effect: set */ +#define AT91C_TC_ACPC_CLEAR ( ( unsigned int ) 0x2 << 18 ) /* (TC) Effect: clear */ +#define AT91C_TC_ACPC_TOGGLE ( ( unsigned int ) 0x3 << 18 ) /* (TC) Effect: toggle */ +#define AT91C_TC_LDRB ( ( unsigned int ) 0x3 << 18 ) /* (TC) RB Loading Selection */ +#define AT91C_TC_LDRB_NONE ( ( unsigned int ) 0x0 << 18 ) /* (TC) Edge: None */ +#define AT91C_TC_LDRB_RISING ( ( unsigned int ) 0x1 << 18 ) /* (TC) Edge: rising edge of TIOA */ +#define AT91C_TC_LDRB_FALLING ( ( unsigned int ) 0x2 << 18 ) /* (TC) Edge: falling edge of TIOA */ +#define AT91C_TC_LDRB_BOTH ( ( unsigned int ) 0x3 << 18 ) /* (TC) Edge: each edge of TIOA */ +#define AT91C_TC_AEEVT ( ( unsigned int ) 0x3 << 20 ) /* (TC) External Event Effect on TIOA */ +#define AT91C_TC_AEEVT_NONE ( ( unsigned int ) 0x0 << 20 ) /* (TC) Effect: none */ +#define AT91C_TC_AEEVT_SET ( ( unsigned int ) 0x1 << 20 ) /* (TC) Effect: set */ +#define AT91C_TC_AEEVT_CLEAR ( ( unsigned int ) 0x2 << 20 ) /* (TC) Effect: clear */ +#define AT91C_TC_AEEVT_TOGGLE ( ( unsigned int ) 0x3 << 20 ) /* (TC) Effect: toggle */ +#define AT91C_TC_ASWTRG ( ( unsigned int ) 0x3 << 22 ) /* (TC) Software Trigger Effect on TIOA */ +#define AT91C_TC_ASWTRG_NONE ( ( unsigned int ) 0x0 << 22 ) /* (TC) Effect: none */ +#define AT91C_TC_ASWTRG_SET ( ( unsigned int ) 0x1 << 22 ) /* (TC) Effect: set */ +#define AT91C_TC_ASWTRG_CLEAR ( ( unsigned int ) 0x2 << 22 ) /* (TC) Effect: clear */ +#define AT91C_TC_ASWTRG_TOGGLE ( ( unsigned int ) 0x3 << 22 ) /* (TC) Effect: toggle */ +#define AT91C_TC_BCPB ( ( unsigned int ) 0x3 << 24 ) /* (TC) RB Compare Effect on TIOB */ +#define AT91C_TC_BCPB_NONE ( ( unsigned int ) 0x0 << 24 ) /* (TC) Effect: none */ +#define AT91C_TC_BCPB_SET ( ( unsigned int ) 0x1 << 24 ) /* (TC) Effect: set */ +#define AT91C_TC_BCPB_CLEAR ( ( unsigned int ) 0x2 << 24 ) /* (TC) Effect: clear */ +#define AT91C_TC_BCPB_TOGGLE ( ( unsigned int ) 0x3 << 24 ) /* (TC) Effect: toggle */ +#define AT91C_TC_BCPC ( ( unsigned int ) 0x3 << 26 ) /* (TC) RC Compare Effect on TIOB */ +#define AT91C_TC_BCPC_NONE ( ( unsigned int ) 0x0 << 26 ) /* (TC) Effect: none */ +#define AT91C_TC_BCPC_SET ( ( unsigned int ) 0x1 << 26 ) /* (TC) Effect: set */ +#define AT91C_TC_BCPC_CLEAR ( ( unsigned int ) 0x2 << 26 ) /* (TC) Effect: clear */ +#define AT91C_TC_BCPC_TOGGLE ( ( unsigned int ) 0x3 << 26 ) /* (TC) Effect: toggle */ +#define AT91C_TC_BEEVT ( ( unsigned int ) 0x3 << 28 ) /* (TC) External Event Effect on TIOB */ +#define AT91C_TC_BEEVT_NONE ( ( unsigned int ) 0x0 << 28 ) /* (TC) Effect: none */ +#define AT91C_TC_BEEVT_SET ( ( unsigned int ) 0x1 << 28 ) /* (TC) Effect: set */ +#define AT91C_TC_BEEVT_CLEAR ( ( unsigned int ) 0x2 << 28 ) /* (TC) Effect: clear */ +#define AT91C_TC_BEEVT_TOGGLE ( ( unsigned int ) 0x3 << 28 ) /* (TC) Effect: toggle */ +#define AT91C_TC_BSWTRG ( ( unsigned int ) 0x3 << 30 ) /* (TC) Software Trigger Effect on TIOB */ +#define AT91C_TC_BSWTRG_NONE ( ( unsigned int ) 0x0 << 30 ) /* (TC) Effect: none */ +#define AT91C_TC_BSWTRG_SET ( ( unsigned int ) 0x1 << 30 ) /* (TC) Effect: set */ +#define AT91C_TC_BSWTRG_CLEAR ( ( unsigned int ) 0x2 << 30 ) /* (TC) Effect: clear */ +#define AT91C_TC_BSWTRG_TOGGLE ( ( unsigned int ) 0x3 << 30 ) /* (TC) Effect: toggle */ +/* -------- TC_SR : (TC Offset: 0x20) TC Channel Status Register -------- */ +#define AT91C_TC_COVFS ( ( unsigned int ) 0x1 << 0 ) /* (TC) Counter Overflow */ +#define AT91C_TC_LOVRS ( ( unsigned int ) 0x1 << 1 ) /* (TC) Load Overrun */ +#define AT91C_TC_CPAS ( ( unsigned int ) 0x1 << 2 ) /* (TC) RA Compare */ +#define AT91C_TC_CPBS ( ( unsigned int ) 0x1 << 3 ) /* (TC) RB Compare */ +#define AT91C_TC_CPCS ( ( unsigned int ) 0x1 << 4 ) /* (TC) RC Compare */ +#define AT91C_TC_LDRAS ( ( unsigned int ) 0x1 << 5 ) /* (TC) RA Loading */ +#define AT91C_TC_LDRBS ( ( unsigned int ) 0x1 << 6 ) /* (TC) RB Loading */ +#define AT91C_TC_ETRGS ( ( unsigned int ) 0x1 << 7 ) /* (TC) External Trigger */ +#define AT91C_TC_CLKSTA ( ( unsigned int ) 0x1 << 16 ) /* (TC) Clock Enabling */ +#define AT91C_TC_MTIOA ( ( unsigned int ) 0x1 << 17 ) /* (TC) TIOA Mirror */ +#define AT91C_TC_MTIOB ( ( unsigned int ) 0x1 << 18 ) /* (TC) TIOA Mirror */ +/* -------- TC_IER : (TC Offset: 0x24) TC Channel Interrupt Enable Register -------- */ +/* -------- TC_IDR : (TC Offset: 0x28) TC Channel Interrupt Disable Register -------- */ +/* -------- TC_IMR : (TC Offset: 0x2c) TC Channel Interrupt Mask Register -------- */ + +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR Timer Counter Interface */ +/* ***************************************************************************** */ +typedef struct _AT91S_TCB +{ + AT91S_TC TCB_TC0; /* TC Channel 0 */ + AT91_REG Reserved0[ 4 ]; /* */ + AT91S_TC TCB_TC1; /* TC Channel 1 */ + AT91_REG Reserved1[ 4 ]; /* */ + AT91S_TC TCB_TC2; /* TC Channel 2 */ + AT91_REG Reserved2[ 4 ]; /* */ + AT91_REG TCB_BCR; /* TC Block Control Register */ + AT91_REG TCB_BMR; /* TC Block Mode Register */ +} AT91S_TCB, * AT91PS_TCB; + +/* -------- TCB_BCR : (TCB Offset: 0xc0) TC Block Control Register -------- */ +#define AT91C_TCB_SYNC ( ( unsigned int ) 0x1 << 0 ) /* (TCB) Synchro Command */ +/* -------- TCB_BMR : (TCB Offset: 0xc4) TC Block Mode Register -------- */ +#define AT91C_TCB_TC0XC0S ( ( unsigned int ) 0x3 << 0 ) /* (TCB) External Clock Signal 0 Selection */ +#define AT91C_TCB_TC0XC0S_TCLK0 ( ( unsigned int ) 0x0 ) /* (TCB) TCLK0 connected to XC0 */ +#define AT91C_TCB_TC0XC0S_NONE ( ( unsigned int ) 0x1 ) /* (TCB) None signal connected to XC0 */ +#define AT91C_TCB_TC0XC0S_TIOA1 ( ( unsigned int ) 0x2 ) /* (TCB) TIOA1 connected to XC0 */ +#define AT91C_TCB_TC0XC0S_TIOA2 ( ( unsigned int ) 0x3 ) /* (TCB) TIOA2 connected to XC0 */ +#define AT91C_TCB_TC1XC1S ( ( unsigned int ) 0x3 << 2 ) /* (TCB) External Clock Signal 1 Selection */ +#define AT91C_TCB_TC1XC1S_TCLK1 ( ( unsigned int ) 0x0 << 2 ) /* (TCB) TCLK1 connected to XC1 */ +#define AT91C_TCB_TC1XC1S_NONE ( ( unsigned int ) 0x1 << 2 ) /* (TCB) None signal connected to XC1 */ +#define AT91C_TCB_TC1XC1S_TIOA0 ( ( unsigned int ) 0x2 << 2 ) /* (TCB) TIOA0 connected to XC1 */ +#define AT91C_TCB_TC1XC1S_TIOA2 ( ( unsigned int ) 0x3 << 2 ) /* (TCB) TIOA2 connected to XC1 */ +#define AT91C_TCB_TC2XC2S ( ( unsigned int ) 0x3 << 4 ) /* (TCB) External Clock Signal 2 Selection */ +#define AT91C_TCB_TC2XC2S_TCLK2 ( ( unsigned int ) 0x0 << 4 ) /* (TCB) TCLK2 connected to XC2 */ +#define AT91C_TCB_TC2XC2S_NONE ( ( unsigned int ) 0x1 << 4 ) /* (TCB) None signal connected to XC2 */ +#define AT91C_TCB_TC2XC2S_TIOA0 ( ( unsigned int ) 0x2 << 4 ) /* (TCB) TIOA0 connected to XC2 */ +#define AT91C_TCB_TC2XC2S_TIOA1 ( ( unsigned int ) 0x3 << 4 ) /* (TCB) TIOA2 connected to XC2 */ + +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR Control Area Network MailBox Interface */ +/* ***************************************************************************** */ +typedef struct _AT91S_CAN_MB +{ + AT91_REG CAN_MB_MMR; /* MailBox Mode Register */ + AT91_REG CAN_MB_MAM; /* MailBox Acceptance Mask Register */ + AT91_REG CAN_MB_MID; /* MailBox ID Register */ + AT91_REG CAN_MB_MFID; /* MailBox Family ID Register */ + AT91_REG CAN_MB_MSR; /* MailBox Status Register */ + AT91_REG CAN_MB_MDL; /* MailBox Data Low Register */ + AT91_REG CAN_MB_MDH; /* MailBox Data High Register */ + AT91_REG CAN_MB_MCR; /* MailBox Control Register */ +} AT91S_CAN_MB, * AT91PS_CAN_MB; + +/* -------- CAN_MMR : (CAN_MB Offset: 0x0) CAN Message Mode Register -------- */ +#define AT91C_CAN_MTIMEMARK ( ( unsigned int ) 0xFFFF << 0 ) /* (CAN_MB) Mailbox Timemark */ +#define AT91C_CAN_PRIOR ( ( unsigned int ) 0xF << 16 ) /* (CAN_MB) Mailbox Priority */ +#define AT91C_CAN_MOT ( ( unsigned int ) 0x7 << 24 ) /* (CAN_MB) Mailbox Object Type */ +#define AT91C_CAN_MOT_DIS ( ( unsigned int ) 0x0 << 24 ) /* (CAN_MB) */ +#define AT91C_CAN_MOT_RX ( ( unsigned int ) 0x1 << 24 ) /* (CAN_MB) */ +#define AT91C_CAN_MOT_RXOVERWRITE ( ( unsigned int ) 0x2 << 24 ) /* (CAN_MB) */ +#define AT91C_CAN_MOT_TX ( ( unsigned int ) 0x3 << 24 ) /* (CAN_MB) */ +#define AT91C_CAN_MOT_CONSUMER ( ( unsigned int ) 0x4 << 24 ) /* (CAN_MB) */ +#define AT91C_CAN_MOT_PRODUCER ( ( unsigned int ) 0x5 << 24 ) /* (CAN_MB) */ +/* -------- CAN_MAM : (CAN_MB Offset: 0x4) CAN Message Acceptance Mask Register -------- */ +#define AT91C_CAN_MIDvB ( ( unsigned int ) 0x3FFFF << 0 ) /* (CAN_MB) Complementary bits for identifier in extended mode */ +#define AT91C_CAN_MIDvA ( ( unsigned int ) 0x7FF << 18 ) /* (CAN_MB) Identifier for standard frame mode */ +#define AT91C_CAN_MIDE ( ( unsigned int ) 0x1 << 29 ) /* (CAN_MB) Identifier Version */ +/* -------- CAN_MID : (CAN_MB Offset: 0x8) CAN Message ID Register -------- */ +/* -------- CAN_MFID : (CAN_MB Offset: 0xc) CAN Message Family ID Register -------- */ +/* -------- CAN_MSR : (CAN_MB Offset: 0x10) CAN Message Status Register -------- */ +#define AT91C_CAN_MTIMESTAMP ( ( unsigned int ) 0xFFFF << 0 ) /* (CAN_MB) Timer Value */ +#define AT91C_CAN_MDLC ( ( unsigned int ) 0xF << 16 ) /* (CAN_MB) Mailbox Data Length Code */ +#define AT91C_CAN_MRTR ( ( unsigned int ) 0x1 << 20 ) /* (CAN_MB) Mailbox Remote Transmission Request */ +#define AT91C_CAN_MABT ( ( unsigned int ) 0x1 << 22 ) /* (CAN_MB) Mailbox Message Abort */ +#define AT91C_CAN_MRDY ( ( unsigned int ) 0x1 << 23 ) /* (CAN_MB) Mailbox Ready */ +#define AT91C_CAN_MMI ( ( unsigned int ) 0x1 << 24 ) /* (CAN_MB) Mailbox Message Ignored */ +/* -------- CAN_MDL : (CAN_MB Offset: 0x14) CAN Message Data Low Register -------- */ +/* -------- CAN_MDH : (CAN_MB Offset: 0x18) CAN Message Data High Register -------- */ +/* -------- CAN_MCR : (CAN_MB Offset: 0x1c) CAN Message Control Register -------- */ +#define AT91C_CAN_MACR ( ( unsigned int ) 0x1 << 22 ) /* (CAN_MB) Abort Request for Mailbox */ +#define AT91C_CAN_MTCR ( ( unsigned int ) 0x1 << 23 ) /* (CAN_MB) Mailbox Transfer Command */ + +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR Control Area Network Interface */ +/* ***************************************************************************** */ +typedef struct _AT91S_CAN +{ + AT91_REG CAN_MR; /* Mode Register */ + AT91_REG CAN_IER; /* Interrupt Enable Register */ + AT91_REG CAN_IDR; /* Interrupt Disable Register */ + AT91_REG CAN_IMR; /* Interrupt Mask Register */ + AT91_REG CAN_SR; /* Status Register */ + AT91_REG CAN_BR; /* Baudrate Register */ + AT91_REG CAN_TIM; /* Timer Register */ + AT91_REG CAN_TIMESTP; /* Time Stamp Register */ + AT91_REG CAN_ECR; /* Error Counter Register */ + AT91_REG CAN_TCR; /* Transfer Command Register */ + AT91_REG CAN_ACR; /* Abort Command Register */ + AT91_REG Reserved0[ 52 ]; /* */ + AT91_REG CAN_VR; /* Version Register */ + AT91_REG Reserved1[ 64 ]; /* */ + AT91S_CAN_MB CAN_MB0; /* CAN Mailbox 0 */ + AT91S_CAN_MB CAN_MB1; /* CAN Mailbox 1 */ + AT91S_CAN_MB CAN_MB2; /* CAN Mailbox 2 */ + AT91S_CAN_MB CAN_MB3; /* CAN Mailbox 3 */ + AT91S_CAN_MB CAN_MB4; /* CAN Mailbox 4 */ + AT91S_CAN_MB CAN_MB5; /* CAN Mailbox 5 */ + AT91S_CAN_MB CAN_MB6; /* CAN Mailbox 6 */ + AT91S_CAN_MB CAN_MB7; /* CAN Mailbox 7 */ + AT91S_CAN_MB CAN_MB8; /* CAN Mailbox 8 */ + AT91S_CAN_MB CAN_MB9; /* CAN Mailbox 9 */ + AT91S_CAN_MB CAN_MB10; /* CAN Mailbox 10 */ + AT91S_CAN_MB CAN_MB11; /* CAN Mailbox 11 */ + AT91S_CAN_MB CAN_MB12; /* CAN Mailbox 12 */ + AT91S_CAN_MB CAN_MB13; /* CAN Mailbox 13 */ + AT91S_CAN_MB CAN_MB14; /* CAN Mailbox 14 */ + AT91S_CAN_MB CAN_MB15; /* CAN Mailbox 15 */ +} AT91S_CAN, * AT91PS_CAN; + +/* -------- CAN_MR : (CAN Offset: 0x0) CAN Mode Register -------- */ +#define AT91C_CAN_CANEN ( ( unsigned int ) 0x1 << 0 ) /* (CAN) CAN Controller Enable */ +#define AT91C_CAN_LPM ( ( unsigned int ) 0x1 << 1 ) /* (CAN) Disable/Enable Low Power Mode */ +#define AT91C_CAN_ABM ( ( unsigned int ) 0x1 << 2 ) /* (CAN) Disable/Enable Autobaud/Listen Mode */ +#define AT91C_CAN_OVL ( ( unsigned int ) 0x1 << 3 ) /* (CAN) Disable/Enable Overload Frame */ +#define AT91C_CAN_TEOF ( ( unsigned int ) 0x1 << 4 ) /* (CAN) Time Stamp messages at each end of Frame */ +#define AT91C_CAN_TTM ( ( unsigned int ) 0x1 << 5 ) /* (CAN) Disable/Enable Time Trigger Mode */ +#define AT91C_CAN_TIMFRZ ( ( unsigned int ) 0x1 << 6 ) /* (CAN) Enable Timer Freeze */ +#define AT91C_CAN_DRPT ( ( unsigned int ) 0x1 << 7 ) /* (CAN) Disable Repeat */ +/* -------- CAN_IER : (CAN Offset: 0x4) CAN Interrupt Enable Register -------- */ +#define AT91C_CAN_MB0 ( ( unsigned int ) 0x1 << 0 ) /* (CAN) Mailbox 0 Flag */ +#define AT91C_CAN_MB1 ( ( unsigned int ) 0x1 << 1 ) /* (CAN) Mailbox 1 Flag */ +#define AT91C_CAN_MB2 ( ( unsigned int ) 0x1 << 2 ) /* (CAN) Mailbox 2 Flag */ +#define AT91C_CAN_MB3 ( ( unsigned int ) 0x1 << 3 ) /* (CAN) Mailbox 3 Flag */ +#define AT91C_CAN_MB4 ( ( unsigned int ) 0x1 << 4 ) /* (CAN) Mailbox 4 Flag */ +#define AT91C_CAN_MB5 ( ( unsigned int ) 0x1 << 5 ) /* (CAN) Mailbox 5 Flag */ +#define AT91C_CAN_MB6 ( ( unsigned int ) 0x1 << 6 ) /* (CAN) Mailbox 6 Flag */ +#define AT91C_CAN_MB7 ( ( unsigned int ) 0x1 << 7 ) /* (CAN) Mailbox 7 Flag */ +#define AT91C_CAN_MB8 ( ( unsigned int ) 0x1 << 8 ) /* (CAN) Mailbox 8 Flag */ +#define AT91C_CAN_MB9 ( ( unsigned int ) 0x1 << 9 ) /* (CAN) Mailbox 9 Flag */ +#define AT91C_CAN_MB10 ( ( unsigned int ) 0x1 << 10 ) /* (CAN) Mailbox 10 Flag */ +#define AT91C_CAN_MB11 ( ( unsigned int ) 0x1 << 11 ) /* (CAN) Mailbox 11 Flag */ +#define AT91C_CAN_MB12 ( ( unsigned int ) 0x1 << 12 ) /* (CAN) Mailbox 12 Flag */ +#define AT91C_CAN_MB13 ( ( unsigned int ) 0x1 << 13 ) /* (CAN) Mailbox 13 Flag */ +#define AT91C_CAN_MB14 ( ( unsigned int ) 0x1 << 14 ) /* (CAN) Mailbox 14 Flag */ +#define AT91C_CAN_MB15 ( ( unsigned int ) 0x1 << 15 ) /* (CAN) Mailbox 15 Flag */ +#define AT91C_CAN_ERRA ( ( unsigned int ) 0x1 << 16 ) /* (CAN) Error Active Mode Flag */ +#define AT91C_CAN_WARN ( ( unsigned int ) 0x1 << 17 ) /* (CAN) Warning Limit Flag */ +#define AT91C_CAN_ERRP ( ( unsigned int ) 0x1 << 18 ) /* (CAN) Error Passive Mode Flag */ +#define AT91C_CAN_BOFF ( ( unsigned int ) 0x1 << 19 ) /* (CAN) Bus Off Mode Flag */ +#define AT91C_CAN_SLEEP ( ( unsigned int ) 0x1 << 20 ) /* (CAN) Sleep Flag */ +#define AT91C_CAN_WAKEUP ( ( unsigned int ) 0x1 << 21 ) /* (CAN) Wakeup Flag */ +#define AT91C_CAN_TOVF ( ( unsigned int ) 0x1 << 22 ) /* (CAN) Timer Overflow Flag */ +#define AT91C_CAN_TSTP ( ( unsigned int ) 0x1 << 23 ) /* (CAN) Timestamp Flag */ +#define AT91C_CAN_CERR ( ( unsigned int ) 0x1 << 24 ) /* (CAN) CRC Error */ +#define AT91C_CAN_SERR ( ( unsigned int ) 0x1 << 25 ) /* (CAN) Stuffing Error */ +#define AT91C_CAN_AERR ( ( unsigned int ) 0x1 << 26 ) /* (CAN) Acknowledgment Error */ +#define AT91C_CAN_FERR ( ( unsigned int ) 0x1 << 27 ) /* (CAN) Form Error */ +#define AT91C_CAN_BERR ( ( unsigned int ) 0x1 << 28 ) /* (CAN) Bit Error */ +/* -------- CAN_IDR : (CAN Offset: 0x8) CAN Interrupt Disable Register -------- */ +/* -------- CAN_IMR : (CAN Offset: 0xc) CAN Interrupt Mask Register -------- */ +/* -------- CAN_SR : (CAN Offset: 0x10) CAN Status Register -------- */ +#define AT91C_CAN_RBSY ( ( unsigned int ) 0x1 << 29 ) /* (CAN) Receiver Busy */ +#define AT91C_CAN_TBSY ( ( unsigned int ) 0x1 << 30 ) /* (CAN) Transmitter Busy */ +#define AT91C_CAN_OVLY ( ( unsigned int ) 0x1 << 31 ) /* (CAN) Overload Busy */ +/* -------- CAN_BR : (CAN Offset: 0x14) CAN Baudrate Register -------- */ +#define AT91C_CAN_PHASE2 ( ( unsigned int ) 0x7 << 0 ) /* (CAN) Phase 2 segment */ +#define AT91C_CAN_PHASE1 ( ( unsigned int ) 0x7 << 4 ) /* (CAN) Phase 1 segment */ +#define AT91C_CAN_PROPAG ( ( unsigned int ) 0x7 << 8 ) /* (CAN) Programmation time segment */ +#define AT91C_CAN_SYNC ( ( unsigned int ) 0x3 << 12 ) /* (CAN) Re-synchronization jump width segment */ +#define AT91C_CAN_BRP ( ( unsigned int ) 0x7F << 16 ) /* (CAN) Baudrate Prescaler */ +#define AT91C_CAN_SMP ( ( unsigned int ) 0x1 << 24 ) /* (CAN) Sampling mode */ +/* -------- CAN_TIM : (CAN Offset: 0x18) CAN Timer Register -------- */ +#define AT91C_CAN_TIMER ( ( unsigned int ) 0xFFFF << 0 ) /* (CAN) Timer field */ +/* -------- CAN_TIMESTP : (CAN Offset: 0x1c) CAN Timestamp Register -------- */ +/* -------- CAN_ECR : (CAN Offset: 0x20) CAN Error Counter Register -------- */ +#define AT91C_CAN_REC ( ( unsigned int ) 0xFF << 0 ) /* (CAN) Receive Error Counter */ +#define AT91C_CAN_TEC ( ( unsigned int ) 0xFF << 16 ) /* (CAN) Transmit Error Counter */ +/* -------- CAN_TCR : (CAN Offset: 0x24) CAN Transfer Command Register -------- */ +#define AT91C_CAN_TIMRST ( ( unsigned int ) 0x1 << 31 ) /* (CAN) Timer Reset Field */ +/* -------- CAN_ACR : (CAN Offset: 0x28) CAN Abort Command Register -------- */ + +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR Ethernet MAC 10/100 */ +/* ***************************************************************************** */ +typedef struct _AT91S_EMAC +{ + AT91_REG EMAC_NCR; /* Network Control Register */ + AT91_REG EMAC_NCFGR; /* Network Configuration Register */ + AT91_REG EMAC_NSR; /* Network Status Register */ + AT91_REG Reserved0[ 2 ]; /* */ + AT91_REG EMAC_TSR; /* Transmit Status Register */ + AT91_REG EMAC_RBQP; /* Receive Buffer Queue Pointer */ + AT91_REG EMAC_TBQP; /* Transmit Buffer Queue Pointer */ + AT91_REG EMAC_RSR; /* Receive Status Register */ + AT91_REG EMAC_ISR; /* Interrupt Status Register */ + AT91_REG EMAC_IER; /* Interrupt Enable Register */ + AT91_REG EMAC_IDR; /* Interrupt Disable Register */ + AT91_REG EMAC_IMR; /* Interrupt Mask Register */ + AT91_REG EMAC_MAN; /* PHY Maintenance Register */ + AT91_REG EMAC_PTR; /* Pause Time Register */ + AT91_REG EMAC_PFR; /* Pause Frames received Register */ + AT91_REG EMAC_FTO; /* Frames Transmitted OK Register */ + AT91_REG EMAC_SCF; /* Single Collision Frame Register */ + AT91_REG EMAC_MCF; /* Multiple Collision Frame Register */ + AT91_REG EMAC_FRO; /* Frames Received OK Register */ + AT91_REG EMAC_FCSE; /* Frame Check Sequence Error Register */ + AT91_REG EMAC_ALE; /* Alignment Error Register */ + AT91_REG EMAC_DTF; /* Deferred Transmission Frame Register */ + AT91_REG EMAC_LCOL; /* Late Collision Register */ + AT91_REG EMAC_ECOL; /* Excessive Collision Register */ + AT91_REG EMAC_TUND; /* Transmit Underrun Error Register */ + AT91_REG EMAC_CSE; /* Carrier Sense Error Register */ + AT91_REG EMAC_RRE; /* Receive Ressource Error Register */ + AT91_REG EMAC_ROV; /* Receive Overrun Errors Register */ + AT91_REG EMAC_RSE; /* Receive Symbol Errors Register */ + AT91_REG EMAC_ELE; /* Excessive Length Errors Register */ + AT91_REG EMAC_RJA; /* Receive Jabbers Register */ + AT91_REG EMAC_USF; /* Undersize Frames Register */ + AT91_REG EMAC_STE; /* SQE Test Error Register */ + AT91_REG EMAC_RLE; /* Receive Length Field Mismatch Register */ + AT91_REG EMAC_TPF; /* Transmitted Pause Frames Register */ + AT91_REG EMAC_HRB; /* Hash Address Bottom[31:0] */ + AT91_REG EMAC_HRT; /* Hash Address Top[63:32] */ + AT91_REG EMAC_SA1L; /* Specific Address 1 Bottom, First 4 bytes */ + AT91_REG EMAC_SA1H; /* Specific Address 1 Top, Last 2 bytes */ + AT91_REG EMAC_SA2L; /* Specific Address 2 Bottom, First 4 bytes */ + AT91_REG EMAC_SA2H; /* Specific Address 2 Top, Last 2 bytes */ + AT91_REG EMAC_SA3L; /* Specific Address 3 Bottom, First 4 bytes */ + AT91_REG EMAC_SA3H; /* Specific Address 3 Top, Last 2 bytes */ + AT91_REG EMAC_SA4L; /* Specific Address 4 Bottom, First 4 bytes */ + AT91_REG EMAC_SA4H; /* Specific Address 4 Top, Last 2 bytes */ + AT91_REG EMAC_TID; /* Type ID Checking Register */ + AT91_REG EMAC_TPQ; /* Transmit Pause Quantum Register */ + AT91_REG EMAC_USRIO; /* USER Input/Output Register */ + AT91_REG EMAC_WOL; /* Wake On LAN Register */ + AT91_REG Reserved1[ 13 ]; /* */ + AT91_REG EMAC_REV; /* Revision Register */ +} AT91S_EMAC, * AT91PS_EMAC; + +/* -------- EMAC_NCR : (EMAC Offset: 0x0) -------- */ +#define AT91C_EMAC_LB ( ( unsigned int ) 0x1 << 0 ) /* (EMAC) Loopback. Optional. When set, loopback signal is at high level. */ +#define AT91C_EMAC_LLB ( ( unsigned int ) 0x1 << 1 ) /* (EMAC) Loopback local. */ +#define AT91C_EMAC_RE ( ( unsigned int ) 0x1 << 2 ) /* (EMAC) Receive enable. */ +#define AT91C_EMAC_TE ( ( unsigned int ) 0x1 << 3 ) /* (EMAC) Transmit enable. */ +#define AT91C_EMAC_MPE ( ( unsigned int ) 0x1 << 4 ) /* (EMAC) Management port enable. */ +#define AT91C_EMAC_CLRSTAT ( ( unsigned int ) 0x1 << 5 ) /* (EMAC) Clear statistics registers. */ +#define AT91C_EMAC_INCSTAT ( ( unsigned int ) 0x1 << 6 ) /* (EMAC) Increment statistics registers. */ +#define AT91C_EMAC_WESTAT ( ( unsigned int ) 0x1 << 7 ) /* (EMAC) Write enable for statistics registers. */ +#define AT91C_EMAC_BP ( ( unsigned int ) 0x1 << 8 ) /* (EMAC) Back pressure. */ +#define AT91C_EMAC_TSTART ( ( unsigned int ) 0x1 << 9 ) /* (EMAC) Start Transmission. */ +#define AT91C_EMAC_THALT ( ( unsigned int ) 0x1 << 10 ) /* (EMAC) Transmission Halt. */ +#define AT91C_EMAC_TPFR ( ( unsigned int ) 0x1 << 11 ) /* (EMAC) Transmit pause frame */ +#define AT91C_EMAC_TZQ ( ( unsigned int ) 0x1 << 12 ) /* (EMAC) Transmit zero quantum pause frame */ +/* -------- EMAC_NCFGR : (EMAC Offset: 0x4) Network Configuration Register -------- */ +#define AT91C_EMAC_SPD ( ( unsigned int ) 0x1 << 0 ) /* (EMAC) Speed. */ +#define AT91C_EMAC_FD ( ( unsigned int ) 0x1 << 1 ) /* (EMAC) Full duplex. */ +#define AT91C_EMAC_JFRAME ( ( unsigned int ) 0x1 << 3 ) /* (EMAC) Jumbo Frames. */ +#define AT91C_EMAC_CAF ( ( unsigned int ) 0x1 << 4 ) /* (EMAC) Copy all frames. */ +#define AT91C_EMAC_NBC ( ( unsigned int ) 0x1 << 5 ) /* (EMAC) No broadcast. */ +#define AT91C_EMAC_MTI ( ( unsigned int ) 0x1 << 6 ) /* (EMAC) Multicast hash event enable */ +#define AT91C_EMAC_UNI ( ( unsigned int ) 0x1 << 7 ) /* (EMAC) Unicast hash enable. */ +#define AT91C_EMAC_BIG ( ( unsigned int ) 0x1 << 8 ) /* (EMAC) Receive 1522 bytes. */ +#define AT91C_EMAC_EAE ( ( unsigned int ) 0x1 << 9 ) /* (EMAC) External address match enable. */ +#define AT91C_EMAC_CLK ( ( unsigned int ) 0x3 << 10 ) /* (EMAC) */ +#define AT91C_EMAC_CLK_HCLK_8 ( ( unsigned int ) 0x0 << 10 ) /* (EMAC) HCLK divided by 8 */ +#define AT91C_EMAC_CLK_HCLK_16 ( ( unsigned int ) 0x1 << 10 ) /* (EMAC) HCLK divided by 16 */ +#define AT91C_EMAC_CLK_HCLK_32 ( ( unsigned int ) 0x2 << 10 ) /* (EMAC) HCLK divided by 32 */ +#define AT91C_EMAC_CLK_HCLK_64 ( ( unsigned int ) 0x3 << 10 ) /* (EMAC) HCLK divided by 64 */ +#define AT91C_EMAC_RTY ( ( unsigned int ) 0x1 << 12 ) /* (EMAC) */ +#define AT91C_EMAC_PAE ( ( unsigned int ) 0x1 << 13 ) /* (EMAC) */ +#define AT91C_EMAC_RBOF ( ( unsigned int ) 0x3 << 14 ) /* (EMAC) */ +#define AT91C_EMAC_RBOF_OFFSET_0 ( ( unsigned int ) 0x0 << 14 ) /* (EMAC) no offset from start of receive buffer */ +#define AT91C_EMAC_RBOF_OFFSET_1 ( ( unsigned int ) 0x1 << 14 ) /* (EMAC) one byte offset from start of receive buffer */ +#define AT91C_EMAC_RBOF_OFFSET_2 ( ( unsigned int ) 0x2 << 14 ) /* (EMAC) two bytes offset from start of receive buffer */ +#define AT91C_EMAC_RBOF_OFFSET_3 ( ( unsigned int ) 0x3 << 14 ) /* (EMAC) three bytes offset from start of receive buffer */ +#define AT91C_EMAC_RLCE ( ( unsigned int ) 0x1 << 16 ) /* (EMAC) Receive Length field Checking Enable */ +#define AT91C_EMAC_DRFCS ( ( unsigned int ) 0x1 << 17 ) /* (EMAC) Discard Receive FCS */ +#define AT91C_EMAC_EFRHD ( ( unsigned int ) 0x1 << 18 ) /* (EMAC) */ +#define AT91C_EMAC_IRXFCS ( ( unsigned int ) 0x1 << 19 ) /* (EMAC) Ignore RX FCS */ +/* -------- EMAC_NSR : (EMAC Offset: 0x8) Network Status Register -------- */ +#define AT91C_EMAC_LINKR ( ( unsigned int ) 0x1 << 0 ) /* (EMAC) */ +#define AT91C_EMAC_MDIO ( ( unsigned int ) 0x1 << 1 ) /* (EMAC) */ +#define AT91C_EMAC_IDLE ( ( unsigned int ) 0x1 << 2 ) /* (EMAC) */ +/* -------- EMAC_TSR : (EMAC Offset: 0x14) Transmit Status Register -------- */ +#define AT91C_EMAC_UBR ( ( unsigned int ) 0x1 << 0 ) /* (EMAC) */ +#define AT91C_EMAC_COL ( ( unsigned int ) 0x1 << 1 ) /* (EMAC) */ +#define AT91C_EMAC_RLES ( ( unsigned int ) 0x1 << 2 ) /* (EMAC) */ +#define AT91C_EMAC_TGO ( ( unsigned int ) 0x1 << 3 ) /* (EMAC) Transmit Go */ +#define AT91C_EMAC_BEX ( ( unsigned int ) 0x1 << 4 ) /* (EMAC) Buffers exhausted mid frame */ +#define AT91C_EMAC_COMP ( ( unsigned int ) 0x1 << 5 ) /* (EMAC) */ +#define AT91C_EMAC_UND ( ( unsigned int ) 0x1 << 6 ) /* (EMAC) */ +/* -------- EMAC_RSR : (EMAC Offset: 0x20) Receive Status Register -------- */ +#define AT91C_EMAC_BNA ( ( unsigned int ) 0x1 << 0 ) /* (EMAC) */ +#define AT91C_EMAC_REC ( ( unsigned int ) 0x1 << 1 ) /* (EMAC) */ +#define AT91C_EMAC_OVR ( ( unsigned int ) 0x1 << 2 ) /* (EMAC) */ +/* -------- EMAC_ISR : (EMAC Offset: 0x24) Interrupt Status Register -------- */ +#define AT91C_EMAC_MFD ( ( unsigned int ) 0x1 << 0 ) /* (EMAC) */ +#define AT91C_EMAC_RCOMP ( ( unsigned int ) 0x1 << 1 ) /* (EMAC) */ +#define AT91C_EMAC_RXUBR ( ( unsigned int ) 0x1 << 2 ) /* (EMAC) */ +#define AT91C_EMAC_TXUBR ( ( unsigned int ) 0x1 << 3 ) /* (EMAC) */ +#define AT91C_EMAC_TUNDR ( ( unsigned int ) 0x1 << 4 ) /* (EMAC) */ +#define AT91C_EMAC_RLEX ( ( unsigned int ) 0x1 << 5 ) /* (EMAC) */ +#define AT91C_EMAC_TXERR ( ( unsigned int ) 0x1 << 6 ) /* (EMAC) */ +#define AT91C_EMAC_TCOMP ( ( unsigned int ) 0x1 << 7 ) /* (EMAC) */ +#define AT91C_EMAC_LINK ( ( unsigned int ) 0x1 << 9 ) /* (EMAC) */ +#define AT91C_EMAC_ROVR ( ( unsigned int ) 0x1 << 10 ) /* (EMAC) */ +#define AT91C_EMAC_HRESP ( ( unsigned int ) 0x1 << 11 ) /* (EMAC) */ +#define AT91C_EMAC_PFRE ( ( unsigned int ) 0x1 << 12 ) /* (EMAC) */ +#define AT91C_EMAC_PTZ ( ( unsigned int ) 0x1 << 13 ) /* (EMAC) */ +/* -------- EMAC_IER : (EMAC Offset: 0x28) Interrupt Enable Register -------- */ +/* -------- EMAC_IDR : (EMAC Offset: 0x2c) Interrupt Disable Register -------- */ +/* -------- EMAC_IMR : (EMAC Offset: 0x30) Interrupt Mask Register -------- */ +/* -------- EMAC_MAN : (EMAC Offset: 0x34) PHY Maintenance Register -------- */ +#define AT91C_EMAC_DATA ( ( unsigned int ) 0xFFFF << 0 ) /* (EMAC) */ +#define AT91C_EMAC_CODE ( ( unsigned int ) 0x3 << 16 ) /* (EMAC) */ +#define AT91C_EMAC_REGA ( ( unsigned int ) 0x1F << 18 ) /* (EMAC) */ +#define AT91C_EMAC_PHYA ( ( unsigned int ) 0x1F << 23 ) /* (EMAC) */ +#define AT91C_EMAC_RW ( ( unsigned int ) 0x3 << 28 ) /* (EMAC) */ +#define AT91C_EMAC_SOF ( ( unsigned int ) 0x3 << 30 ) /* (EMAC) */ +/* -------- EMAC_USRIO : (EMAC Offset: 0xc0) USER Input Output Register -------- */ +#define AT91C_EMAC_RMII ( ( unsigned int ) 0x1 << 0 ) /* (EMAC) Reduce MII */ +/* -------- EMAC_WOL : (EMAC Offset: 0xc4) Wake On LAN Register -------- */ +#define AT91C_EMAC_IP ( ( unsigned int ) 0xFFFF << 0 ) /* (EMAC) ARP request IP address */ +#define AT91C_EMAC_MAG ( ( unsigned int ) 0x1 << 16 ) /* (EMAC) Magic packet event enable */ +#define AT91C_EMAC_ARP ( ( unsigned int ) 0x1 << 17 ) /* (EMAC) ARP request event enable */ +#define AT91C_EMAC_SA1 ( ( unsigned int ) 0x1 << 18 ) /* (EMAC) Specific address register 1 event enable */ +/* -------- EMAC_REV : (EMAC Offset: 0xfc) Revision Register -------- */ +#define AT91C_EMAC_REVREF ( ( unsigned int ) 0xFFFF << 0 ) /* (EMAC) */ +#define AT91C_EMAC_PARTREF ( ( unsigned int ) 0xFFFF << 16 ) /* (EMAC) */ + +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR Analog to Digital Convertor */ +/* ***************************************************************************** */ +typedef struct _AT91S_ADC +{ + AT91_REG ADC_CR; /* ADC Control Register */ + AT91_REG ADC_MR; /* ADC Mode Register */ + AT91_REG Reserved0[ 2 ]; /* */ + AT91_REG ADC_CHER; /* ADC Channel Enable Register */ + AT91_REG ADC_CHDR; /* ADC Channel Disable Register */ + AT91_REG ADC_CHSR; /* ADC Channel Status Register */ + AT91_REG ADC_SR; /* ADC Status Register */ + AT91_REG ADC_LCDR; /* ADC Last Converted Data Register */ + AT91_REG ADC_IER; /* ADC Interrupt Enable Register */ + AT91_REG ADC_IDR; /* ADC Interrupt Disable Register */ + AT91_REG ADC_IMR; /* ADC Interrupt Mask Register */ + AT91_REG ADC_CDR0; /* ADC Channel Data Register 0 */ + AT91_REG ADC_CDR1; /* ADC Channel Data Register 1 */ + AT91_REG ADC_CDR2; /* ADC Channel Data Register 2 */ + AT91_REG ADC_CDR3; /* ADC Channel Data Register 3 */ + AT91_REG ADC_CDR4; /* ADC Channel Data Register 4 */ + AT91_REG ADC_CDR5; /* ADC Channel Data Register 5 */ + AT91_REG ADC_CDR6; /* ADC Channel Data Register 6 */ + AT91_REG ADC_CDR7; /* ADC Channel Data Register 7 */ + AT91_REG Reserved1[ 44 ]; /* */ + AT91_REG ADC_RPR; /* Receive Pointer Register */ + AT91_REG ADC_RCR; /* Receive Counter Register */ + AT91_REG ADC_TPR; /* Transmit Pointer Register */ + AT91_REG ADC_TCR; /* Transmit Counter Register */ + AT91_REG ADC_RNPR; /* Receive Next Pointer Register */ + AT91_REG ADC_RNCR; /* Receive Next Counter Register */ + AT91_REG ADC_TNPR; /* Transmit Next Pointer Register */ + AT91_REG ADC_TNCR; /* Transmit Next Counter Register */ + AT91_REG ADC_PTCR; /* PDC Transfer Control Register */ + AT91_REG ADC_PTSR; /* PDC Transfer Status Register */ +} AT91S_ADC, * AT91PS_ADC; + +/* -------- ADC_CR : (ADC Offset: 0x0) ADC Control Register -------- */ +#define AT91C_ADC_SWRST ( ( unsigned int ) 0x1 << 0 ) /* (ADC) Software Reset */ +#define AT91C_ADC_START ( ( unsigned int ) 0x1 << 1 ) /* (ADC) Start Conversion */ +/* -------- ADC_MR : (ADC Offset: 0x4) ADC Mode Register -------- */ +#define AT91C_ADC_TRGEN ( ( unsigned int ) 0x1 << 0 ) /* (ADC) Trigger Enable */ +#define AT91C_ADC_TRGEN_DIS ( ( unsigned int ) 0x0 ) /* (ADC) Hardware triggers are disabled. Starting a conversion is only possible by software */ +#define AT91C_ADC_TRGEN_EN ( ( unsigned int ) 0x1 ) /* (ADC) Hardware trigger selected by TRGSEL field is enabled. */ +#define AT91C_ADC_TRGSEL ( ( unsigned int ) 0x7 << 1 ) /* (ADC) Trigger Selection */ +#define AT91C_ADC_TRGSEL_TIOA0 ( ( unsigned int ) 0x0 << 1 ) /* (ADC) Selected TRGSEL = TIAO0 */ +#define AT91C_ADC_TRGSEL_TIOA1 ( ( unsigned int ) 0x1 << 1 ) /* (ADC) Selected TRGSEL = TIAO1 */ +#define AT91C_ADC_TRGSEL_TIOA2 ( ( unsigned int ) 0x2 << 1 ) /* (ADC) Selected TRGSEL = TIAO2 */ +#define AT91C_ADC_TRGSEL_TIOA3 ( ( unsigned int ) 0x3 << 1 ) /* (ADC) Selected TRGSEL = TIAO3 */ +#define AT91C_ADC_TRGSEL_TIOA4 ( ( unsigned int ) 0x4 << 1 ) /* (ADC) Selected TRGSEL = TIAO4 */ +#define AT91C_ADC_TRGSEL_TIOA5 ( ( unsigned int ) 0x5 << 1 ) /* (ADC) Selected TRGSEL = TIAO5 */ +#define AT91C_ADC_TRGSEL_EXT ( ( unsigned int ) 0x6 << 1 ) /* (ADC) Selected TRGSEL = External Trigger */ +#define AT91C_ADC_LOWRES ( ( unsigned int ) 0x1 << 4 ) /* (ADC) Resolution. */ +#define AT91C_ADC_LOWRES_10_BIT ( ( unsigned int ) 0x0 << 4 ) /* (ADC) 10-bit resolution */ +#define AT91C_ADC_LOWRES_8_BIT ( ( unsigned int ) 0x1 << 4 ) /* (ADC) 8-bit resolution */ +#define AT91C_ADC_SLEEP ( ( unsigned int ) 0x1 << 5 ) /* (ADC) Sleep Mode */ +#define AT91C_ADC_SLEEP_NORMAL_MODE ( ( unsigned int ) 0x0 << 5 ) /* (ADC) Normal Mode */ +#define AT91C_ADC_SLEEP_MODE ( ( unsigned int ) 0x1 << 5 ) /* (ADC) Sleep Mode */ +#define AT91C_ADC_PRESCAL ( ( unsigned int ) 0x3F << 8 ) /* (ADC) Prescaler rate selection */ +#define AT91C_ADC_STARTUP ( ( unsigned int ) 0x1F << 16 ) /* (ADC) Startup Time */ +#define AT91C_ADC_SHTIM ( ( unsigned int ) 0xF << 24 ) /* (ADC) Sample & Hold Time */ +/* -------- ADC_CHER : (ADC Offset: 0x10) ADC Channel Enable Register -------- */ +#define AT91C_ADC_CH0 ( ( unsigned int ) 0x1 << 0 ) /* (ADC) Channel 0 */ +#define AT91C_ADC_CH1 ( ( unsigned int ) 0x1 << 1 ) /* (ADC) Channel 1 */ +#define AT91C_ADC_CH2 ( ( unsigned int ) 0x1 << 2 ) /* (ADC) Channel 2 */ +#define AT91C_ADC_CH3 ( ( unsigned int ) 0x1 << 3 ) /* (ADC) Channel 3 */ +#define AT91C_ADC_CH4 ( ( unsigned int ) 0x1 << 4 ) /* (ADC) Channel 4 */ +#define AT91C_ADC_CH5 ( ( unsigned int ) 0x1 << 5 ) /* (ADC) Channel 5 */ +#define AT91C_ADC_CH6 ( ( unsigned int ) 0x1 << 6 ) /* (ADC) Channel 6 */ +#define AT91C_ADC_CH7 ( ( unsigned int ) 0x1 << 7 ) /* (ADC) Channel 7 */ +/* -------- ADC_CHDR : (ADC Offset: 0x14) ADC Channel Disable Register -------- */ +/* -------- ADC_CHSR : (ADC Offset: 0x18) ADC Channel Status Register -------- */ +/* -------- ADC_SR : (ADC Offset: 0x1c) ADC Status Register -------- */ +#define AT91C_ADC_EOC0 ( ( unsigned int ) 0x1 << 0 ) /* (ADC) End of Conversion */ +#define AT91C_ADC_EOC1 ( ( unsigned int ) 0x1 << 1 ) /* (ADC) End of Conversion */ +#define AT91C_ADC_EOC2 ( ( unsigned int ) 0x1 << 2 ) /* (ADC) End of Conversion */ +#define AT91C_ADC_EOC3 ( ( unsigned int ) 0x1 << 3 ) /* (ADC) End of Conversion */ +#define AT91C_ADC_EOC4 ( ( unsigned int ) 0x1 << 4 ) /* (ADC) End of Conversion */ +#define AT91C_ADC_EOC5 ( ( unsigned int ) 0x1 << 5 ) /* (ADC) End of Conversion */ +#define AT91C_ADC_EOC6 ( ( unsigned int ) 0x1 << 6 ) /* (ADC) End of Conversion */ +#define AT91C_ADC_EOC7 ( ( unsigned int ) 0x1 << 7 ) /* (ADC) End of Conversion */ +#define AT91C_ADC_OVRE0 ( ( unsigned int ) 0x1 << 8 ) /* (ADC) Overrun Error */ +#define AT91C_ADC_OVRE1 ( ( unsigned int ) 0x1 << 9 ) /* (ADC) Overrun Error */ +#define AT91C_ADC_OVRE2 ( ( unsigned int ) 0x1 << 10 ) /* (ADC) Overrun Error */ +#define AT91C_ADC_OVRE3 ( ( unsigned int ) 0x1 << 11 ) /* (ADC) Overrun Error */ +#define AT91C_ADC_OVRE4 ( ( unsigned int ) 0x1 << 12 ) /* (ADC) Overrun Error */ +#define AT91C_ADC_OVRE5 ( ( unsigned int ) 0x1 << 13 ) /* (ADC) Overrun Error */ +#define AT91C_ADC_OVRE6 ( ( unsigned int ) 0x1 << 14 ) /* (ADC) Overrun Error */ +#define AT91C_ADC_OVRE7 ( ( unsigned int ) 0x1 << 15 ) /* (ADC) Overrun Error */ +#define AT91C_ADC_DRDY ( ( unsigned int ) 0x1 << 16 ) /* (ADC) Data Ready */ +#define AT91C_ADC_GOVRE ( ( unsigned int ) 0x1 << 17 ) /* (ADC) General Overrun */ +#define AT91C_ADC_ENDRX ( ( unsigned int ) 0x1 << 18 ) /* (ADC) End of Receiver Transfer */ +#define AT91C_ADC_RXBUFF ( ( unsigned int ) 0x1 << 19 ) /* (ADC) RXBUFF Interrupt */ +/* -------- ADC_LCDR : (ADC Offset: 0x20) ADC Last Converted Data Register -------- */ +#define AT91C_ADC_LDATA ( ( unsigned int ) 0x3FF << 0 ) /* (ADC) Last Data Converted */ +/* -------- ADC_IER : (ADC Offset: 0x24) ADC Interrupt Enable Register -------- */ +/* -------- ADC_IDR : (ADC Offset: 0x28) ADC Interrupt Disable Register -------- */ +/* -------- ADC_IMR : (ADC Offset: 0x2c) ADC Interrupt Mask Register -------- */ +/* -------- ADC_CDR0 : (ADC Offset: 0x30) ADC Channel Data Register 0 -------- */ +#define AT91C_ADC_DATA ( ( unsigned int ) 0x3FF << 0 ) /* (ADC) Converted Data */ +/* -------- ADC_CDR1 : (ADC Offset: 0x34) ADC Channel Data Register 1 -------- */ +/* -------- ADC_CDR2 : (ADC Offset: 0x38) ADC Channel Data Register 2 -------- */ +/* -------- ADC_CDR3 : (ADC Offset: 0x3c) ADC Channel Data Register 3 -------- */ +/* -------- ADC_CDR4 : (ADC Offset: 0x40) ADC Channel Data Register 4 -------- */ +/* -------- ADC_CDR5 : (ADC Offset: 0x44) ADC Channel Data Register 5 -------- */ +/* -------- ADC_CDR6 : (ADC Offset: 0x48) ADC Channel Data Register 6 -------- */ +/* -------- ADC_CDR7 : (ADC Offset: 0x4c) ADC Channel Data Register 7 -------- */ + +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR Advanced Encryption Standard */ +/* ***************************************************************************** */ +typedef struct _AT91S_AES +{ + AT91_REG AES_CR; /* Control Register */ + AT91_REG AES_MR; /* Mode Register */ + AT91_REG Reserved0[ 2 ]; /* */ + AT91_REG AES_IER; /* Interrupt Enable Register */ + AT91_REG AES_IDR; /* Interrupt Disable Register */ + AT91_REG AES_IMR; /* Interrupt Mask Register */ + AT91_REG AES_ISR; /* Interrupt Status Register */ + AT91_REG AES_KEYWxR[ 4 ]; /* Key Word x Register */ + AT91_REG Reserved1[ 4 ]; /* */ + AT91_REG AES_IDATAxR[ 4 ]; /* Input Data x Register */ + AT91_REG AES_ODATAxR[ 4 ]; /* Output Data x Register */ + AT91_REG AES_IVxR[ 4 ]; /* Initialization Vector x Register */ + AT91_REG Reserved2[ 35 ]; /* */ + AT91_REG AES_VR; /* AES Version Register */ + AT91_REG AES_RPR; /* Receive Pointer Register */ + AT91_REG AES_RCR; /* Receive Counter Register */ + AT91_REG AES_TPR; /* Transmit Pointer Register */ + AT91_REG AES_TCR; /* Transmit Counter Register */ + AT91_REG AES_RNPR; /* Receive Next Pointer Register */ + AT91_REG AES_RNCR; /* Receive Next Counter Register */ + AT91_REG AES_TNPR; /* Transmit Next Pointer Register */ + AT91_REG AES_TNCR; /* Transmit Next Counter Register */ + AT91_REG AES_PTCR; /* PDC Transfer Control Register */ + AT91_REG AES_PTSR; /* PDC Transfer Status Register */ +} AT91S_AES, * AT91PS_AES; + +/* -------- AES_CR : (AES Offset: 0x0) Control Register -------- */ +#define AT91C_AES_START ( ( unsigned int ) 0x1 << 0 ) /* (AES) Starts Processing */ +#define AT91C_AES_SWRST ( ( unsigned int ) 0x1 << 8 ) /* (AES) Software Reset */ +#define AT91C_AES_LOADSEED ( ( unsigned int ) 0x1 << 16 ) /* (AES) Random Number Generator Seed Loading */ +/* -------- AES_MR : (AES Offset: 0x4) Mode Register -------- */ +#define AT91C_AES_CIPHER ( ( unsigned int ) 0x1 << 0 ) /* (AES) Processing Mode */ +#define AT91C_AES_PROCDLY ( ( unsigned int ) 0xF << 4 ) /* (AES) Processing Delay */ +#define AT91C_AES_SMOD ( ( unsigned int ) 0x3 << 8 ) /* (AES) Start Mode */ +#define AT91C_AES_SMOD_MANUAL ( ( unsigned int ) 0x0 << 8 ) /* (AES) Manual Mode: The START bit in register AES_CR must be set to begin encryption or decryption. */ +#define AT91C_AES_SMOD_AUTO ( ( unsigned int ) 0x1 << 8 ) /* (AES) Auto Mode: no action in AES_CR is necessary (cf datasheet). */ +#define AT91C_AES_SMOD_PDC ( ( unsigned int ) 0x2 << 8 ) /* (AES) PDC Mode (cf datasheet). */ +#define AT91C_AES_OPMOD ( ( unsigned int ) 0x7 << 12 ) /* (AES) Operation Mode */ +#define AT91C_AES_OPMOD_ECB ( ( unsigned int ) 0x0 << 12 ) /* (AES) ECB Electronic CodeBook mode. */ +#define AT91C_AES_OPMOD_CBC ( ( unsigned int ) 0x1 << 12 ) /* (AES) CBC Cipher Block Chaining mode. */ +#define AT91C_AES_OPMOD_OFB ( ( unsigned int ) 0x2 << 12 ) /* (AES) OFB Output Feedback mode. */ +#define AT91C_AES_OPMOD_CFB ( ( unsigned int ) 0x3 << 12 ) /* (AES) CFB Cipher Feedback mode. */ +#define AT91C_AES_OPMOD_CTR ( ( unsigned int ) 0x4 << 12 ) /* (AES) CTR Counter mode. */ +#define AT91C_AES_LOD ( ( unsigned int ) 0x1 << 15 ) /* (AES) Last Output Data Mode */ +#define AT91C_AES_CFBS ( ( unsigned int ) 0x7 << 16 ) /* (AES) Cipher Feedback Data Size */ +#define AT91C_AES_CFBS_128_BIT ( ( unsigned int ) 0x0 << 16 ) /* (AES) 128-bit. */ +#define AT91C_AES_CFBS_64_BIT ( ( unsigned int ) 0x1 << 16 ) /* (AES) 64-bit. */ +#define AT91C_AES_CFBS_32_BIT ( ( unsigned int ) 0x2 << 16 ) /* (AES) 32-bit. */ +#define AT91C_AES_CFBS_16_BIT ( ( unsigned int ) 0x3 << 16 ) /* (AES) 16-bit. */ +#define AT91C_AES_CFBS_8_BIT ( ( unsigned int ) 0x4 << 16 ) /* (AES) 8-bit. */ +#define AT91C_AES_CKEY ( ( unsigned int ) 0xF << 20 ) /* (AES) Countermeasure Key */ +#define AT91C_AES_CTYPE ( ( unsigned int ) 0x1F << 24 ) /* (AES) Countermeasure Type */ +#define AT91C_AES_CTYPE_TYPE1_EN ( ( unsigned int ) 0x1 << 24 ) /* (AES) Countermeasure type 1 is enabled. */ +#define AT91C_AES_CTYPE_TYPE2_EN ( ( unsigned int ) 0x2 << 24 ) /* (AES) Countermeasure type 2 is enabled. */ +#define AT91C_AES_CTYPE_TYPE3_EN ( ( unsigned int ) 0x4 << 24 ) /* (AES) Countermeasure type 3 is enabled. */ +#define AT91C_AES_CTYPE_TYPE4_EN ( ( unsigned int ) 0x8 << 24 ) /* (AES) Countermeasure type 4 is enabled. */ +#define AT91C_AES_CTYPE_TYPE5_EN ( ( unsigned int ) 0x10 << 24 ) /* (AES) Countermeasure type 5 is enabled. */ +/* -------- AES_IER : (AES Offset: 0x10) Interrupt Enable Register -------- */ +#define AT91C_AES_DATRDY ( ( unsigned int ) 0x1 << 0 ) /* (AES) DATRDY */ +#define AT91C_AES_ENDRX ( ( unsigned int ) 0x1 << 1 ) /* (AES) PDC Read Buffer End */ +#define AT91C_AES_ENDTX ( ( unsigned int ) 0x1 << 2 ) /* (AES) PDC Write Buffer End */ +#define AT91C_AES_RXBUFF ( ( unsigned int ) 0x1 << 3 ) /* (AES) PDC Read Buffer Full */ +#define AT91C_AES_TXBUFE ( ( unsigned int ) 0x1 << 4 ) /* (AES) PDC Write Buffer Empty */ +#define AT91C_AES_URAD ( ( unsigned int ) 0x1 << 8 ) /* (AES) Unspecified Register Access Detection */ +/* -------- AES_IDR : (AES Offset: 0x14) Interrupt Disable Register -------- */ +/* -------- AES_IMR : (AES Offset: 0x18) Interrupt Mask Register -------- */ +/* -------- AES_ISR : (AES Offset: 0x1c) Interrupt Status Register -------- */ +#define AT91C_AES_URAT ( ( unsigned int ) 0x7 << 12 ) /* (AES) Unspecified Register Access Type Status */ +#define AT91C_AES_URAT_IN_DAT_WRITE_DATPROC ( ( unsigned int ) 0x0 << 12 ) /* (AES) Input data register written during the data processing in PDC mode. */ +#define AT91C_AES_URAT_OUT_DAT_READ_DATPROC ( ( unsigned int ) 0x1 << 12 ) /* (AES) Output data register read during the data processing. */ +#define AT91C_AES_URAT_MODEREG_WRITE_DATPROC ( ( unsigned int ) 0x2 << 12 ) /* (AES) Mode register written during the data processing. */ +#define AT91C_AES_URAT_OUT_DAT_READ_SUBKEY ( ( unsigned int ) 0x3 << 12 ) /* (AES) Output data register read during the sub-keys generation. */ +#define AT91C_AES_URAT_MODEREG_WRITE_SUBKEY ( ( unsigned int ) 0x4 << 12 ) /* (AES) Mode register written during the sub-keys generation. */ +#define AT91C_AES_URAT_WO_REG_READ ( ( unsigned int ) 0x5 << 12 ) /* (AES) Write-only register read access. */ + +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR Triple Data Encryption Standard */ +/* ***************************************************************************** */ +typedef struct _AT91S_TDES +{ + AT91_REG TDES_CR; /* Control Register */ + AT91_REG TDES_MR; /* Mode Register */ + AT91_REG Reserved0[ 2 ]; /* */ + AT91_REG TDES_IER; /* Interrupt Enable Register */ + AT91_REG TDES_IDR; /* Interrupt Disable Register */ + AT91_REG TDES_IMR; /* Interrupt Mask Register */ + AT91_REG TDES_ISR; /* Interrupt Status Register */ + AT91_REG TDES_KEY1WxR[ 2 ]; /* Key 1 Word x Register */ + AT91_REG TDES_KEY2WxR[ 2 ]; /* Key 2 Word x Register */ + AT91_REG TDES_KEY3WxR[ 2 ]; /* Key 3 Word x Register */ + AT91_REG Reserved1[ 2 ]; /* */ + AT91_REG TDES_IDATAxR[ 2 ]; /* Input Data x Register */ + AT91_REG Reserved2[ 2 ]; /* */ + AT91_REG TDES_ODATAxR[ 2 ]; /* Output Data x Register */ + AT91_REG Reserved3[ 2 ]; /* */ + AT91_REG TDES_IVxR[ 2 ]; /* Initialization Vector x Register */ + AT91_REG Reserved4[ 37 ]; /* */ + AT91_REG TDES_VR; /* TDES Version Register */ + AT91_REG TDES_RPR; /* Receive Pointer Register */ + AT91_REG TDES_RCR; /* Receive Counter Register */ + AT91_REG TDES_TPR; /* Transmit Pointer Register */ + AT91_REG TDES_TCR; /* Transmit Counter Register */ + AT91_REG TDES_RNPR; /* Receive Next Pointer Register */ + AT91_REG TDES_RNCR; /* Receive Next Counter Register */ + AT91_REG TDES_TNPR; /* Transmit Next Pointer Register */ + AT91_REG TDES_TNCR; /* Transmit Next Counter Register */ + AT91_REG TDES_PTCR; /* PDC Transfer Control Register */ + AT91_REG TDES_PTSR; /* PDC Transfer Status Register */ +} AT91S_TDES, * AT91PS_TDES; + +/* -------- TDES_CR : (TDES Offset: 0x0) Control Register -------- */ +#define AT91C_TDES_START ( ( unsigned int ) 0x1 << 0 ) /* (TDES) Starts Processing */ +#define AT91C_TDES_SWRST ( ( unsigned int ) 0x1 << 8 ) /* (TDES) Software Reset */ +/* -------- TDES_MR : (TDES Offset: 0x4) Mode Register -------- */ +#define AT91C_TDES_CIPHER ( ( unsigned int ) 0x1 << 0 ) /* (TDES) Processing Mode */ +#define AT91C_TDES_TDESMOD ( ( unsigned int ) 0x1 << 1 ) /* (TDES) Single or Triple DES Mode */ +#define AT91C_TDES_KEYMOD ( ( unsigned int ) 0x1 << 4 ) /* (TDES) Key Mode */ +#define AT91C_TDES_SMOD ( ( unsigned int ) 0x3 << 8 ) /* (TDES) Start Mode */ +#define AT91C_TDES_SMOD_MANUAL ( ( unsigned int ) 0x0 << 8 ) /* (TDES) Manual Mode: The START bit in register TDES_CR must be set to begin encryption or decryption. */ +#define AT91C_TDES_SMOD_AUTO ( ( unsigned int ) 0x1 << 8 ) /* (TDES) Auto Mode: no action in TDES_CR is necessary (cf datasheet). */ +#define AT91C_TDES_SMOD_PDC ( ( unsigned int ) 0x2 << 8 ) /* (TDES) PDC Mode (cf datasheet). */ +#define AT91C_TDES_OPMOD ( ( unsigned int ) 0x3 << 12 ) /* (TDES) Operation Mode */ +#define AT91C_TDES_OPMOD_ECB ( ( unsigned int ) 0x0 << 12 ) /* (TDES) ECB Electronic CodeBook mode. */ +#define AT91C_TDES_OPMOD_CBC ( ( unsigned int ) 0x1 << 12 ) /* (TDES) CBC Cipher Block Chaining mode. */ +#define AT91C_TDES_OPMOD_OFB ( ( unsigned int ) 0x2 << 12 ) /* (TDES) OFB Output Feedback mode. */ +#define AT91C_TDES_OPMOD_CFB ( ( unsigned int ) 0x3 << 12 ) /* (TDES) CFB Cipher Feedback mode. */ +#define AT91C_TDES_LOD ( ( unsigned int ) 0x1 << 15 ) /* (TDES) Last Output Data Mode */ +#define AT91C_TDES_CFBS ( ( unsigned int ) 0x3 << 16 ) /* (TDES) Cipher Feedback Data Size */ +#define AT91C_TDES_CFBS_64_BIT ( ( unsigned int ) 0x0 << 16 ) /* (TDES) 64-bit. */ +#define AT91C_TDES_CFBS_32_BIT ( ( unsigned int ) 0x1 << 16 ) /* (TDES) 32-bit. */ +#define AT91C_TDES_CFBS_16_BIT ( ( unsigned int ) 0x2 << 16 ) /* (TDES) 16-bit. */ +#define AT91C_TDES_CFBS_8_BIT ( ( unsigned int ) 0x3 << 16 ) /* (TDES) 8-bit. */ +/* -------- TDES_IER : (TDES Offset: 0x10) Interrupt Enable Register -------- */ +#define AT91C_TDES_DATRDY ( ( unsigned int ) 0x1 << 0 ) /* (TDES) DATRDY */ +#define AT91C_TDES_ENDRX ( ( unsigned int ) 0x1 << 1 ) /* (TDES) PDC Read Buffer End */ +#define AT91C_TDES_ENDTX ( ( unsigned int ) 0x1 << 2 ) /* (TDES) PDC Write Buffer End */ +#define AT91C_TDES_RXBUFF ( ( unsigned int ) 0x1 << 3 ) /* (TDES) PDC Read Buffer Full */ +#define AT91C_TDES_TXBUFE ( ( unsigned int ) 0x1 << 4 ) /* (TDES) PDC Write Buffer Empty */ +#define AT91C_TDES_URAD ( ( unsigned int ) 0x1 << 8 ) /* (TDES) Unspecified Register Access Detection */ +/* -------- TDES_IDR : (TDES Offset: 0x14) Interrupt Disable Register -------- */ +/* -------- TDES_IMR : (TDES Offset: 0x18) Interrupt Mask Register -------- */ +/* -------- TDES_ISR : (TDES Offset: 0x1c) Interrupt Status Register -------- */ +#define AT91C_TDES_URAT ( ( unsigned int ) 0x3 << 12 ) /* (TDES) Unspecified Register Access Type Status */ +#define AT91C_TDES_URAT_IN_DAT_WRITE_DATPROC ( ( unsigned int ) 0x0 << 12 ) /* (TDES) Input data register written during the data processing in PDC mode. */ +#define AT91C_TDES_URAT_OUT_DAT_READ_DATPROC ( ( unsigned int ) 0x1 << 12 ) /* (TDES) Output data register read during the data processing. */ +#define AT91C_TDES_URAT_MODEREG_WRITE_DATPROC ( ( unsigned int ) 0x2 << 12 ) /* (TDES) Mode register written during the data processing. */ +#define AT91C_TDES_URAT_WO_REG_READ ( ( unsigned int ) 0x3 << 12 ) /* (TDES) Write-only register read access. */ + +/* ***************************************************************************** */ +/* REGISTER ADDRESS DEFINITION FOR AT91SAM7X256 */ +/* ***************************************************************************** */ +/* ========== Register definition for SYS peripheral ========== */ +/* ========== Register definition for AIC peripheral ========== */ +#define AT91C_AIC_IVR ( ( AT91_REG * ) 0xFFFFF100 ) /* (AIC) IRQ Vector Register */ +#define AT91C_AIC_SMR ( ( AT91_REG * ) 0xFFFFF000 ) /* (AIC) Source Mode Register */ +#define AT91C_AIC_FVR ( ( AT91_REG * ) 0xFFFFF104 ) /* (AIC) FIQ Vector Register */ +#define AT91C_AIC_DCR ( ( AT91_REG * ) 0xFFFFF138 ) /* (AIC) Debug Control Register (Protect) */ +#define AT91C_AIC_EOICR ( ( AT91_REG * ) 0xFFFFF130 ) /* (AIC) End of Interrupt Command Register */ +#define AT91C_AIC_SVR ( ( AT91_REG * ) 0xFFFFF080 ) /* (AIC) Source Vector Register */ +#define AT91C_AIC_FFSR ( ( AT91_REG * ) 0xFFFFF148 ) /* (AIC) Fast Forcing Status Register */ +#define AT91C_AIC_ICCR ( ( AT91_REG * ) 0xFFFFF128 ) /* (AIC) Interrupt Clear Command Register */ +#define AT91C_AIC_ISR ( ( AT91_REG * ) 0xFFFFF108 ) /* (AIC) Interrupt Status Register */ +#define AT91C_AIC_IMR ( ( AT91_REG * ) 0xFFFFF110 ) /* (AIC) Interrupt Mask Register */ +#define AT91C_AIC_IPR ( ( AT91_REG * ) 0xFFFFF10C ) /* (AIC) Interrupt Pending Register */ +#define AT91C_AIC_FFER ( ( AT91_REG * ) 0xFFFFF140 ) /* (AIC) Fast Forcing Enable Register */ +#define AT91C_AIC_IECR ( ( AT91_REG * ) 0xFFFFF120 ) /* (AIC) Interrupt Enable Command Register */ +#define AT91C_AIC_ISCR ( ( AT91_REG * ) 0xFFFFF12C ) /* (AIC) Interrupt Set Command Register */ +#define AT91C_AIC_FFDR ( ( AT91_REG * ) 0xFFFFF144 ) /* (AIC) Fast Forcing Disable Register */ +#define AT91C_AIC_CISR ( ( AT91_REG * ) 0xFFFFF114 ) /* (AIC) Core Interrupt Status Register */ +#define AT91C_AIC_IDCR ( ( AT91_REG * ) 0xFFFFF124 ) /* (AIC) Interrupt Disable Command Register */ +#define AT91C_AIC_SPU ( ( AT91_REG * ) 0xFFFFF134 ) /* (AIC) Spurious Vector Register */ +/* ========== Register definition for PDC_DBGU peripheral ========== */ +#define AT91C_DBGU_TCR ( ( AT91_REG * ) 0xFFFFF30C ) /* (PDC_DBGU) Transmit Counter Register */ +#define AT91C_DBGU_RNPR ( ( AT91_REG * ) 0xFFFFF310 ) /* (PDC_DBGU) Receive Next Pointer Register */ +#define AT91C_DBGU_TNPR ( ( AT91_REG * ) 0xFFFFF318 ) /* (PDC_DBGU) Transmit Next Pointer Register */ +#define AT91C_DBGU_TPR ( ( AT91_REG * ) 0xFFFFF308 ) /* (PDC_DBGU) Transmit Pointer Register */ +#define AT91C_DBGU_RPR ( ( AT91_REG * ) 0xFFFFF300 ) /* (PDC_DBGU) Receive Pointer Register */ +#define AT91C_DBGU_RCR ( ( AT91_REG * ) 0xFFFFF304 ) /* (PDC_DBGU) Receive Counter Register */ +#define AT91C_DBGU_RNCR ( ( AT91_REG * ) 0xFFFFF314 ) /* (PDC_DBGU) Receive Next Counter Register */ +#define AT91C_DBGU_PTCR ( ( AT91_REG * ) 0xFFFFF320 ) /* (PDC_DBGU) PDC Transfer Control Register */ +#define AT91C_DBGU_PTSR ( ( AT91_REG * ) 0xFFFFF324 ) /* (PDC_DBGU) PDC Transfer Status Register */ +#define AT91C_DBGU_TNCR ( ( AT91_REG * ) 0xFFFFF31C ) /* (PDC_DBGU) Transmit Next Counter Register */ +/* ========== Register definition for DBGU peripheral ========== */ +#define AT91C_DBGU_EXID ( ( AT91_REG * ) 0xFFFFF244 ) /* (DBGU) Chip ID Extension Register */ +#define AT91C_DBGU_BRGR ( ( AT91_REG * ) 0xFFFFF220 ) /* (DBGU) Baud Rate Generator Register */ +#define AT91C_DBGU_IDR ( ( AT91_REG * ) 0xFFFFF20C ) /* (DBGU) Interrupt Disable Register */ +#define AT91C_DBGU_CSR ( ( AT91_REG * ) 0xFFFFF214 ) /* (DBGU) Channel Status Register */ +#define AT91C_DBGU_CIDR ( ( AT91_REG * ) 0xFFFFF240 ) /* (DBGU) Chip ID Register */ +#define AT91C_DBGU_MR ( ( AT91_REG * ) 0xFFFFF204 ) /* (DBGU) Mode Register */ +#define AT91C_DBGU_IMR ( ( AT91_REG * ) 0xFFFFF210 ) /* (DBGU) Interrupt Mask Register */ +#define AT91C_DBGU_CR ( ( AT91_REG * ) 0xFFFFF200 ) /* (DBGU) Control Register */ +#define AT91C_DBGU_FNTR ( ( AT91_REG * ) 0xFFFFF248 ) /* (DBGU) Force NTRST Register */ +#define AT91C_DBGU_THR ( ( AT91_REG * ) 0xFFFFF21C ) /* (DBGU) Transmitter Holding Register */ +#define AT91C_DBGU_RHR ( ( AT91_REG * ) 0xFFFFF218 ) /* (DBGU) Receiver Holding Register */ +#define AT91C_DBGU_IER ( ( AT91_REG * ) 0xFFFFF208 ) /* (DBGU) Interrupt Enable Register */ +/* ========== Register definition for PIOA peripheral ========== */ +#define AT91C_PIOA_ODR ( ( AT91_REG * ) 0xFFFFF414 ) /* (PIOA) Output Disable Registerr */ +#define AT91C_PIOA_SODR ( ( AT91_REG * ) 0xFFFFF430 ) /* (PIOA) Set Output Data Register */ +#define AT91C_PIOA_ISR ( ( AT91_REG * ) 0xFFFFF44C ) /* (PIOA) Interrupt Status Register */ +#define AT91C_PIOA_ABSR ( ( AT91_REG * ) 0xFFFFF478 ) /* (PIOA) AB Select Status Register */ +#define AT91C_PIOA_IER ( ( AT91_REG * ) 0xFFFFF440 ) /* (PIOA) Interrupt Enable Register */ +#define AT91C_PIOA_PPUDR ( ( AT91_REG * ) 0xFFFFF460 ) /* (PIOA) Pull-up Disable Register */ +#define AT91C_PIOA_IMR ( ( AT91_REG * ) 0xFFFFF448 ) /* (PIOA) Interrupt Mask Register */ +#define AT91C_PIOA_PER ( ( AT91_REG * ) 0xFFFFF400 ) /* (PIOA) PIO Enable Register */ +#define AT91C_PIOA_IFDR ( ( AT91_REG * ) 0xFFFFF424 ) /* (PIOA) Input Filter Disable Register */ +#define AT91C_PIOA_OWDR ( ( AT91_REG * ) 0xFFFFF4A4 ) /* (PIOA) Output Write Disable Register */ +#define AT91C_PIOA_MDSR ( ( AT91_REG * ) 0xFFFFF458 ) /* (PIOA) Multi-driver Status Register */ +#define AT91C_PIOA_IDR ( ( AT91_REG * ) 0xFFFFF444 ) /* (PIOA) Interrupt Disable Register */ +#define AT91C_PIOA_ODSR ( ( AT91_REG * ) 0xFFFFF438 ) /* (PIOA) Output Data Status Register */ +#define AT91C_PIOA_PPUSR ( ( AT91_REG * ) 0xFFFFF468 ) /* (PIOA) Pull-up Status Register */ +#define AT91C_PIOA_OWSR ( ( AT91_REG * ) 0xFFFFF4A8 ) /* (PIOA) Output Write Status Register */ +#define AT91C_PIOA_BSR ( ( AT91_REG * ) 0xFFFFF474 ) /* (PIOA) Select B Register */ +#define AT91C_PIOA_OWER ( ( AT91_REG * ) 0xFFFFF4A0 ) /* (PIOA) Output Write Enable Register */ +#define AT91C_PIOA_IFER ( ( AT91_REG * ) 0xFFFFF420 ) /* (PIOA) Input Filter Enable Register */ +#define AT91C_PIOA_PDSR ( ( AT91_REG * ) 0xFFFFF43C ) /* (PIOA) Pin Data Status Register */ +#define AT91C_PIOA_PPUER ( ( AT91_REG * ) 0xFFFFF464 ) /* (PIOA) Pull-up Enable Register */ +#define AT91C_PIOA_OSR ( ( AT91_REG * ) 0xFFFFF418 ) /* (PIOA) Output Status Register */ +#define AT91C_PIOA_ASR ( ( AT91_REG * ) 0xFFFFF470 ) /* (PIOA) Select A Register */ +#define AT91C_PIOA_MDDR ( ( AT91_REG * ) 0xFFFFF454 ) /* (PIOA) Multi-driver Disable Register */ +#define AT91C_PIOA_CODR ( ( AT91_REG * ) 0xFFFFF434 ) /* (PIOA) Clear Output Data Register */ +#define AT91C_PIOA_MDER ( ( AT91_REG * ) 0xFFFFF450 ) /* (PIOA) Multi-driver Enable Register */ +#define AT91C_PIOA_PDR ( ( AT91_REG * ) 0xFFFFF404 ) /* (PIOA) PIO Disable Register */ +#define AT91C_PIOA_IFSR ( ( AT91_REG * ) 0xFFFFF428 ) /* (PIOA) Input Filter Status Register */ +#define AT91C_PIOA_OER ( ( AT91_REG * ) 0xFFFFF410 ) /* (PIOA) Output Enable Register */ +#define AT91C_PIOA_PSR ( ( AT91_REG * ) 0xFFFFF408 ) /* (PIOA) PIO Status Register */ +/* ========== Register definition for PIOB peripheral ========== */ +#define AT91C_PIOB_OWDR ( ( AT91_REG * ) 0xFFFFF6A4 ) /* (PIOB) Output Write Disable Register */ +#define AT91C_PIOB_MDER ( ( AT91_REG * ) 0xFFFFF650 ) /* (PIOB) Multi-driver Enable Register */ +#define AT91C_PIOB_PPUSR ( ( AT91_REG * ) 0xFFFFF668 ) /* (PIOB) Pull-up Status Register */ +#define AT91C_PIOB_IMR ( ( AT91_REG * ) 0xFFFFF648 ) /* (PIOB) Interrupt Mask Register */ +#define AT91C_PIOB_ASR ( ( AT91_REG * ) 0xFFFFF670 ) /* (PIOB) Select A Register */ +#define AT91C_PIOB_PPUDR ( ( AT91_REG * ) 0xFFFFF660 ) /* (PIOB) Pull-up Disable Register */ +#define AT91C_PIOB_PSR ( ( AT91_REG * ) 0xFFFFF608 ) /* (PIOB) PIO Status Register */ +#define AT91C_PIOB_IER ( ( AT91_REG * ) 0xFFFFF640 ) /* (PIOB) Interrupt Enable Register */ +#define AT91C_PIOB_CODR ( ( AT91_REG * ) 0xFFFFF634 ) /* (PIOB) Clear Output Data Register */ +#define AT91C_PIOB_OWER ( ( AT91_REG * ) 0xFFFFF6A0 ) /* (PIOB) Output Write Enable Register */ +#define AT91C_PIOB_ABSR ( ( AT91_REG * ) 0xFFFFF678 ) /* (PIOB) AB Select Status Register */ +#define AT91C_PIOB_IFDR ( ( AT91_REG * ) 0xFFFFF624 ) /* (PIOB) Input Filter Disable Register */ +#define AT91C_PIOB_PDSR ( ( AT91_REG * ) 0xFFFFF63C ) /* (PIOB) Pin Data Status Register */ +#define AT91C_PIOB_IDR ( ( AT91_REG * ) 0xFFFFF644 ) /* (PIOB) Interrupt Disable Register */ +#define AT91C_PIOB_OWSR ( ( AT91_REG * ) 0xFFFFF6A8 ) /* (PIOB) Output Write Status Register */ +#define AT91C_PIOB_PDR ( ( AT91_REG * ) 0xFFFFF604 ) /* (PIOB) PIO Disable Register */ +#define AT91C_PIOB_ODR ( ( AT91_REG * ) 0xFFFFF614 ) /* (PIOB) Output Disable Registerr */ +#define AT91C_PIOB_IFSR ( ( AT91_REG * ) 0xFFFFF628 ) /* (PIOB) Input Filter Status Register */ +#define AT91C_PIOB_PPUER ( ( AT91_REG * ) 0xFFFFF664 ) /* (PIOB) Pull-up Enable Register */ +#define AT91C_PIOB_SODR ( ( AT91_REG * ) 0xFFFFF630 ) /* (PIOB) Set Output Data Register */ +#define AT91C_PIOB_ISR ( ( AT91_REG * ) 0xFFFFF64C ) /* (PIOB) Interrupt Status Register */ +#define AT91C_PIOB_ODSR ( ( AT91_REG * ) 0xFFFFF638 ) /* (PIOB) Output Data Status Register */ +#define AT91C_PIOB_OSR ( ( AT91_REG * ) 0xFFFFF618 ) /* (PIOB) Output Status Register */ +#define AT91C_PIOB_MDSR ( ( AT91_REG * ) 0xFFFFF658 ) /* (PIOB) Multi-driver Status Register */ +#define AT91C_PIOB_IFER ( ( AT91_REG * ) 0xFFFFF620 ) /* (PIOB) Input Filter Enable Register */ +#define AT91C_PIOB_BSR ( ( AT91_REG * ) 0xFFFFF674 ) /* (PIOB) Select B Register */ +#define AT91C_PIOB_MDDR ( ( AT91_REG * ) 0xFFFFF654 ) /* (PIOB) Multi-driver Disable Register */ +#define AT91C_PIOB_OER ( ( AT91_REG * ) 0xFFFFF610 ) /* (PIOB) Output Enable Register */ +#define AT91C_PIOB_PER ( ( AT91_REG * ) 0xFFFFF600 ) /* (PIOB) PIO Enable Register */ +/* ========== Register definition for CKGR peripheral ========== */ +#define AT91C_CKGR_MOR ( ( AT91_REG * ) 0xFFFFFC20 ) /* (CKGR) Main Oscillator Register */ +#define AT91C_CKGR_PLLR ( ( AT91_REG * ) 0xFFFFFC2C ) /* (CKGR) PLL Register */ +#define AT91C_CKGR_MCFR ( ( AT91_REG * ) 0xFFFFFC24 ) /* (CKGR) Main Clock Frequency Register */ +/* ========== Register definition for PMC peripheral ========== */ +#define AT91C_PMC_IDR ( ( AT91_REG * ) 0xFFFFFC64 ) /* (PMC) Interrupt Disable Register */ +#define AT91C_PMC_MOR ( ( AT91_REG * ) 0xFFFFFC20 ) /* (PMC) Main Oscillator Register */ +#define AT91C_PMC_PLLR ( ( AT91_REG * ) 0xFFFFFC2C ) /* (PMC) PLL Register */ +#define AT91C_PMC_PCER ( ( AT91_REG * ) 0xFFFFFC10 ) /* (PMC) Peripheral Clock Enable Register */ +#define AT91C_PMC_PCKR ( ( AT91_REG * ) 0xFFFFFC40 ) /* (PMC) Programmable Clock Register */ +#define AT91C_PMC_MCKR ( ( AT91_REG * ) 0xFFFFFC30 ) /* (PMC) Master Clock Register */ +#define AT91C_PMC_SCDR ( ( AT91_REG * ) 0xFFFFFC04 ) /* (PMC) System Clock Disable Register */ +#define AT91C_PMC_PCDR ( ( AT91_REG * ) 0xFFFFFC14 ) /* (PMC) Peripheral Clock Disable Register */ +#define AT91C_PMC_SCSR ( ( AT91_REG * ) 0xFFFFFC08 ) /* (PMC) System Clock Status Register */ +#define AT91C_PMC_PCSR ( ( AT91_REG * ) 0xFFFFFC18 ) /* (PMC) Peripheral Clock Status Register */ +#define AT91C_PMC_MCFR ( ( AT91_REG * ) 0xFFFFFC24 ) /* (PMC) Main Clock Frequency Register */ +#define AT91C_PMC_SCER ( ( AT91_REG * ) 0xFFFFFC00 ) /* (PMC) System Clock Enable Register */ +#define AT91C_PMC_IMR ( ( AT91_REG * ) 0xFFFFFC6C ) /* (PMC) Interrupt Mask Register */ +#define AT91C_PMC_IER ( ( AT91_REG * ) 0xFFFFFC60 ) /* (PMC) Interrupt Enable Register */ +#define AT91C_PMC_SR ( ( AT91_REG * ) 0xFFFFFC68 ) /* (PMC) Status Register */ +/* ========== Register definition for RSTC peripheral ========== */ +#define AT91C_RSTC_RCR ( ( AT91_REG * ) 0xFFFFFD00 ) /* (RSTC) Reset Control Register */ +#define AT91C_RSTC_RMR ( ( AT91_REG * ) 0xFFFFFD08 ) /* (RSTC) Reset Mode Register */ +#define AT91C_RSTC_RSR ( ( AT91_REG * ) 0xFFFFFD04 ) /* (RSTC) Reset Status Register */ +/* ========== Register definition for RTTC peripheral ========== */ +#define AT91C_RTTC_RTSR ( ( AT91_REG * ) 0xFFFFFD2C ) /* (RTTC) Real-time Status Register */ +#define AT91C_RTTC_RTMR ( ( AT91_REG * ) 0xFFFFFD20 ) /* (RTTC) Real-time Mode Register */ +#define AT91C_RTTC_RTVR ( ( AT91_REG * ) 0xFFFFFD28 ) /* (RTTC) Real-time Value Register */ +#define AT91C_RTTC_RTAR ( ( AT91_REG * ) 0xFFFFFD24 ) /* (RTTC) Real-time Alarm Register */ +/* ========== Register definition for PITC peripheral ========== */ +#define AT91C_PITC_PIVR ( ( AT91_REG * ) 0xFFFFFD38 ) /* (PITC) Period Interval Value Register */ +#define AT91C_PITC_PISR ( ( AT91_REG * ) 0xFFFFFD34 ) /* (PITC) Period Interval Status Register */ +#define AT91C_PITC_PIIR ( ( AT91_REG * ) 0xFFFFFD3C ) /* (PITC) Period Interval Image Register */ +#define AT91C_PITC_PIMR ( ( AT91_REG * ) 0xFFFFFD30 ) /* (PITC) Period Interval Mode Register */ +/* ========== Register definition for WDTC peripheral ========== */ +#define AT91C_WDTC_WDCR ( ( AT91_REG * ) 0xFFFFFD40 ) /* (WDTC) Watchdog Control Register */ +#define AT91C_WDTC_WDSR ( ( AT91_REG * ) 0xFFFFFD48 ) /* (WDTC) Watchdog Status Register */ +#define AT91C_WDTC_WDMR ( ( AT91_REG * ) 0xFFFFFD44 ) /* (WDTC) Watchdog Mode Register */ +/* ========== Register definition for VREG peripheral ========== */ +#define AT91C_VREG_MR ( ( AT91_REG * ) 0xFFFFFD60 ) /* (VREG) Voltage Regulator Mode Register */ +/* ========== Register definition for MC peripheral ========== */ +#define AT91C_MC_ASR ( ( AT91_REG * ) 0xFFFFFF04 ) /* (MC) MC Abort Status Register */ +#define AT91C_MC_RCR ( ( AT91_REG * ) 0xFFFFFF00 ) /* (MC) MC Remap Control Register */ +#define AT91C_MC_FCR ( ( AT91_REG * ) 0xFFFFFF64 ) /* (MC) MC Flash Command Register */ +#define AT91C_MC_AASR ( ( AT91_REG * ) 0xFFFFFF08 ) /* (MC) MC Abort Address Status Register */ +#define AT91C_MC_FSR ( ( AT91_REG * ) 0xFFFFFF68 ) /* (MC) MC Flash Status Register */ +#define AT91C_MC_FMR ( ( AT91_REG * ) 0xFFFFFF60 ) /* (MC) MC Flash Mode Register */ +/* ========== Register definition for PDC_SPI1 peripheral ========== */ +#define AT91C_SPI1_PTCR ( ( AT91_REG * ) 0xFFFE4120 ) /* (PDC_SPI1) PDC Transfer Control Register */ +#define AT91C_SPI1_RPR ( ( AT91_REG * ) 0xFFFE4100 ) /* (PDC_SPI1) Receive Pointer Register */ +#define AT91C_SPI1_TNCR ( ( AT91_REG * ) 0xFFFE411C ) /* (PDC_SPI1) Transmit Next Counter Register */ +#define AT91C_SPI1_TPR ( ( AT91_REG * ) 0xFFFE4108 ) /* (PDC_SPI1) Transmit Pointer Register */ +#define AT91C_SPI1_TNPR ( ( AT91_REG * ) 0xFFFE4118 ) /* (PDC_SPI1) Transmit Next Pointer Register */ +#define AT91C_SPI1_TCR ( ( AT91_REG * ) 0xFFFE410C ) /* (PDC_SPI1) Transmit Counter Register */ +#define AT91C_SPI1_RCR ( ( AT91_REG * ) 0xFFFE4104 ) /* (PDC_SPI1) Receive Counter Register */ +#define AT91C_SPI1_RNPR ( ( AT91_REG * ) 0xFFFE4110 ) /* (PDC_SPI1) Receive Next Pointer Register */ +#define AT91C_SPI1_RNCR ( ( AT91_REG * ) 0xFFFE4114 ) /* (PDC_SPI1) Receive Next Counter Register */ +#define AT91C_SPI1_PTSR ( ( AT91_REG * ) 0xFFFE4124 ) /* (PDC_SPI1) PDC Transfer Status Register */ +/* ========== Register definition for SPI1 peripheral ========== */ +#define AT91C_SPI1_IMR ( ( AT91_REG * ) 0xFFFE401C ) /* (SPI1) Interrupt Mask Register */ +#define AT91C_SPI1_IER ( ( AT91_REG * ) 0xFFFE4014 ) /* (SPI1) Interrupt Enable Register */ +#define AT91C_SPI1_MR ( ( AT91_REG * ) 0xFFFE4004 ) /* (SPI1) Mode Register */ +#define AT91C_SPI1_RDR ( ( AT91_REG * ) 0xFFFE4008 ) /* (SPI1) Receive Data Register */ +#define AT91C_SPI1_IDR ( ( AT91_REG * ) 0xFFFE4018 ) /* (SPI1) Interrupt Disable Register */ +#define AT91C_SPI1_SR ( ( AT91_REG * ) 0xFFFE4010 ) /* (SPI1) Status Register */ +#define AT91C_SPI1_TDR ( ( AT91_REG * ) 0xFFFE400C ) /* (SPI1) Transmit Data Register */ +#define AT91C_SPI1_CR ( ( AT91_REG * ) 0xFFFE4000 ) /* (SPI1) Control Register */ +#define AT91C_SPI1_CSR ( ( AT91_REG * ) 0xFFFE4030 ) /* (SPI1) Chip Select Register */ +/* ========== Register definition for PDC_SPI0 peripheral ========== */ +#define AT91C_SPI0_PTCR ( ( AT91_REG * ) 0xFFFE0120 ) /* (PDC_SPI0) PDC Transfer Control Register */ +#define AT91C_SPI0_TPR ( ( AT91_REG * ) 0xFFFE0108 ) /* (PDC_SPI0) Transmit Pointer Register */ +#define AT91C_SPI0_TCR ( ( AT91_REG * ) 0xFFFE010C ) /* (PDC_SPI0) Transmit Counter Register */ +#define AT91C_SPI0_RCR ( ( AT91_REG * ) 0xFFFE0104 ) /* (PDC_SPI0) Receive Counter Register */ +#define AT91C_SPI0_PTSR ( ( AT91_REG * ) 0xFFFE0124 ) /* (PDC_SPI0) PDC Transfer Status Register */ +#define AT91C_SPI0_RNPR ( ( AT91_REG * ) 0xFFFE0110 ) /* (PDC_SPI0) Receive Next Pointer Register */ +#define AT91C_SPI0_RPR ( ( AT91_REG * ) 0xFFFE0100 ) /* (PDC_SPI0) Receive Pointer Register */ +#define AT91C_SPI0_TNCR ( ( AT91_REG * ) 0xFFFE011C ) /* (PDC_SPI0) Transmit Next Counter Register */ +#define AT91C_SPI0_RNCR ( ( AT91_REG * ) 0xFFFE0114 ) /* (PDC_SPI0) Receive Next Counter Register */ +#define AT91C_SPI0_TNPR ( ( AT91_REG * ) 0xFFFE0118 ) /* (PDC_SPI0) Transmit Next Pointer Register */ +/* ========== Register definition for SPI0 peripheral ========== */ +#define AT91C_SPI0_IER ( ( AT91_REG * ) 0xFFFE0014 ) /* (SPI0) Interrupt Enable Register */ +#define AT91C_SPI0_SR ( ( AT91_REG * ) 0xFFFE0010 ) /* (SPI0) Status Register */ +#define AT91C_SPI0_IDR ( ( AT91_REG * ) 0xFFFE0018 ) /* (SPI0) Interrupt Disable Register */ +#define AT91C_SPI0_CR ( ( AT91_REG * ) 0xFFFE0000 ) /* (SPI0) Control Register */ +#define AT91C_SPI0_MR ( ( AT91_REG * ) 0xFFFE0004 ) /* (SPI0) Mode Register */ +#define AT91C_SPI0_IMR ( ( AT91_REG * ) 0xFFFE001C ) /* (SPI0) Interrupt Mask Register */ +#define AT91C_SPI0_TDR ( ( AT91_REG * ) 0xFFFE000C ) /* (SPI0) Transmit Data Register */ +#define AT91C_SPI0_RDR ( ( AT91_REG * ) 0xFFFE0008 ) /* (SPI0) Receive Data Register */ +#define AT91C_SPI0_CSR ( ( AT91_REG * ) 0xFFFE0030 ) /* (SPI0) Chip Select Register */ +/* ========== Register definition for PDC_US1 peripheral ========== */ +#define AT91C_US1_RNCR ( ( AT91_REG * ) 0xFFFC4114 ) /* (PDC_US1) Receive Next Counter Register */ +#define AT91C_US1_PTCR ( ( AT91_REG * ) 0xFFFC4120 ) /* (PDC_US1) PDC Transfer Control Register */ +#define AT91C_US1_TCR ( ( AT91_REG * ) 0xFFFC410C ) /* (PDC_US1) Transmit Counter Register */ +#define AT91C_US1_PTSR ( ( AT91_REG * ) 0xFFFC4124 ) /* (PDC_US1) PDC Transfer Status Register */ +#define AT91C_US1_TNPR ( ( AT91_REG * ) 0xFFFC4118 ) /* (PDC_US1) Transmit Next Pointer Register */ +#define AT91C_US1_RCR ( ( AT91_REG * ) 0xFFFC4104 ) /* (PDC_US1) Receive Counter Register */ +#define AT91C_US1_RNPR ( ( AT91_REG * ) 0xFFFC4110 ) /* (PDC_US1) Receive Next Pointer Register */ +#define AT91C_US1_RPR ( ( AT91_REG * ) 0xFFFC4100 ) /* (PDC_US1) Receive Pointer Register */ +#define AT91C_US1_TNCR ( ( AT91_REG * ) 0xFFFC411C ) /* (PDC_US1) Transmit Next Counter Register */ +#define AT91C_US1_TPR ( ( AT91_REG * ) 0xFFFC4108 ) /* (PDC_US1) Transmit Pointer Register */ +/* ========== Register definition for US1 peripheral ========== */ +#define AT91C_US1_IF ( ( AT91_REG * ) 0xFFFC404C ) /* (US1) IRDA_FILTER Register */ +#define AT91C_US1_NER ( ( AT91_REG * ) 0xFFFC4044 ) /* (US1) Nb Errors Register */ +#define AT91C_US1_RTOR ( ( AT91_REG * ) 0xFFFC4024 ) /* (US1) Receiver Time-out Register */ +#define AT91C_US1_CSR ( ( AT91_REG * ) 0xFFFC4014 ) /* (US1) Channel Status Register */ +#define AT91C_US1_IDR ( ( AT91_REG * ) 0xFFFC400C ) /* (US1) Interrupt Disable Register */ +#define AT91C_US1_IER ( ( AT91_REG * ) 0xFFFC4008 ) /* (US1) Interrupt Enable Register */ +#define AT91C_US1_THR ( ( AT91_REG * ) 0xFFFC401C ) /* (US1) Transmitter Holding Register */ +#define AT91C_US1_TTGR ( ( AT91_REG * ) 0xFFFC4028 ) /* (US1) Transmitter Time-guard Register */ +#define AT91C_US1_RHR ( ( AT91_REG * ) 0xFFFC4018 ) /* (US1) Receiver Holding Register */ +#define AT91C_US1_BRGR ( ( AT91_REG * ) 0xFFFC4020 ) /* (US1) Baud Rate Generator Register */ +#define AT91C_US1_IMR ( ( AT91_REG * ) 0xFFFC4010 ) /* (US1) Interrupt Mask Register */ +#define AT91C_US1_FIDI ( ( AT91_REG * ) 0xFFFC4040 ) /* (US1) FI_DI_Ratio Register */ +#define AT91C_US1_CR ( ( AT91_REG * ) 0xFFFC4000 ) /* (US1) Control Register */ +#define AT91C_US1_MR ( ( AT91_REG * ) 0xFFFC4004 ) /* (US1) Mode Register */ +/* ========== Register definition for PDC_US0 peripheral ========== */ +#define AT91C_US0_TNPR ( ( AT91_REG * ) 0xFFFC0118 ) /* (PDC_US0) Transmit Next Pointer Register */ +#define AT91C_US0_RNPR ( ( AT91_REG * ) 0xFFFC0110 ) /* (PDC_US0) Receive Next Pointer Register */ +#define AT91C_US0_TCR ( ( AT91_REG * ) 0xFFFC010C ) /* (PDC_US0) Transmit Counter Register */ +#define AT91C_US0_PTCR ( ( AT91_REG * ) 0xFFFC0120 ) /* (PDC_US0) PDC Transfer Control Register */ +#define AT91C_US0_PTSR ( ( AT91_REG * ) 0xFFFC0124 ) /* (PDC_US0) PDC Transfer Status Register */ +#define AT91C_US0_TNCR ( ( AT91_REG * ) 0xFFFC011C ) /* (PDC_US0) Transmit Next Counter Register */ +#define AT91C_US0_TPR ( ( AT91_REG * ) 0xFFFC0108 ) /* (PDC_US0) Transmit Pointer Register */ +#define AT91C_US0_RCR ( ( AT91_REG * ) 0xFFFC0104 ) /* (PDC_US0) Receive Counter Register */ +#define AT91C_US0_RPR ( ( AT91_REG * ) 0xFFFC0100 ) /* (PDC_US0) Receive Pointer Register */ +#define AT91C_US0_RNCR ( ( AT91_REG * ) 0xFFFC0114 ) /* (PDC_US0) Receive Next Counter Register */ +/* ========== Register definition for US0 peripheral ========== */ +#define AT91C_US0_BRGR ( ( AT91_REG * ) 0xFFFC0020 ) /* (US0) Baud Rate Generator Register */ +#define AT91C_US0_NER ( ( AT91_REG * ) 0xFFFC0044 ) /* (US0) Nb Errors Register */ +#define AT91C_US0_CR ( ( AT91_REG * ) 0xFFFC0000 ) /* (US0) Control Register */ +#define AT91C_US0_IMR ( ( AT91_REG * ) 0xFFFC0010 ) /* (US0) Interrupt Mask Register */ +#define AT91C_US0_FIDI ( ( AT91_REG * ) 0xFFFC0040 ) /* (US0) FI_DI_Ratio Register */ +#define AT91C_US0_TTGR ( ( AT91_REG * ) 0xFFFC0028 ) /* (US0) Transmitter Time-guard Register */ +#define AT91C_US0_MR ( ( AT91_REG * ) 0xFFFC0004 ) /* (US0) Mode Register */ +#define AT91C_US0_RTOR ( ( AT91_REG * ) 0xFFFC0024 ) /* (US0) Receiver Time-out Register */ +#define AT91C_US0_CSR ( ( AT91_REG * ) 0xFFFC0014 ) /* (US0) Channel Status Register */ +#define AT91C_US0_RHR ( ( AT91_REG * ) 0xFFFC0018 ) /* (US0) Receiver Holding Register */ +#define AT91C_US0_IDR ( ( AT91_REG * ) 0xFFFC000C ) /* (US0) Interrupt Disable Register */ +#define AT91C_US0_THR ( ( AT91_REG * ) 0xFFFC001C ) /* (US0) Transmitter Holding Register */ +#define AT91C_US0_IF ( ( AT91_REG * ) 0xFFFC004C ) /* (US0) IRDA_FILTER Register */ +#define AT91C_US0_IER ( ( AT91_REG * ) 0xFFFC0008 ) /* (US0) Interrupt Enable Register */ +/* ========== Register definition for PDC_SSC peripheral ========== */ +#define AT91C_SSC_TNCR ( ( AT91_REG * ) 0xFFFD411C ) /* (PDC_SSC) Transmit Next Counter Register */ +#define AT91C_SSC_RPR ( ( AT91_REG * ) 0xFFFD4100 ) /* (PDC_SSC) Receive Pointer Register */ +#define AT91C_SSC_RNCR ( ( AT91_REG * ) 0xFFFD4114 ) /* (PDC_SSC) Receive Next Counter Register */ +#define AT91C_SSC_TPR ( ( AT91_REG * ) 0xFFFD4108 ) /* (PDC_SSC) Transmit Pointer Register */ +#define AT91C_SSC_PTCR ( ( AT91_REG * ) 0xFFFD4120 ) /* (PDC_SSC) PDC Transfer Control Register */ +#define AT91C_SSC_TCR ( ( AT91_REG * ) 0xFFFD410C ) /* (PDC_SSC) Transmit Counter Register */ +#define AT91C_SSC_RCR ( ( AT91_REG * ) 0xFFFD4104 ) /* (PDC_SSC) Receive Counter Register */ +#define AT91C_SSC_RNPR ( ( AT91_REG * ) 0xFFFD4110 ) /* (PDC_SSC) Receive Next Pointer Register */ +#define AT91C_SSC_TNPR ( ( AT91_REG * ) 0xFFFD4118 ) /* (PDC_SSC) Transmit Next Pointer Register */ +#define AT91C_SSC_PTSR ( ( AT91_REG * ) 0xFFFD4124 ) /* (PDC_SSC) PDC Transfer Status Register */ +/* ========== Register definition for SSC peripheral ========== */ +#define AT91C_SSC_RHR ( ( AT91_REG * ) 0xFFFD4020 ) /* (SSC) Receive Holding Register */ +#define AT91C_SSC_RSHR ( ( AT91_REG * ) 0xFFFD4030 ) /* (SSC) Receive Sync Holding Register */ +#define AT91C_SSC_TFMR ( ( AT91_REG * ) 0xFFFD401C ) /* (SSC) Transmit Frame Mode Register */ +#define AT91C_SSC_IDR ( ( AT91_REG * ) 0xFFFD4048 ) /* (SSC) Interrupt Disable Register */ +#define AT91C_SSC_THR ( ( AT91_REG * ) 0xFFFD4024 ) /* (SSC) Transmit Holding Register */ +#define AT91C_SSC_RCMR ( ( AT91_REG * ) 0xFFFD4010 ) /* (SSC) Receive Clock ModeRegister */ +#define AT91C_SSC_IER ( ( AT91_REG * ) 0xFFFD4044 ) /* (SSC) Interrupt Enable Register */ +#define AT91C_SSC_TSHR ( ( AT91_REG * ) 0xFFFD4034 ) /* (SSC) Transmit Sync Holding Register */ +#define AT91C_SSC_SR ( ( AT91_REG * ) 0xFFFD4040 ) /* (SSC) Status Register */ +#define AT91C_SSC_CMR ( ( AT91_REG * ) 0xFFFD4004 ) /* (SSC) Clock Mode Register */ +#define AT91C_SSC_TCMR ( ( AT91_REG * ) 0xFFFD4018 ) /* (SSC) Transmit Clock Mode Register */ +#define AT91C_SSC_CR ( ( AT91_REG * ) 0xFFFD4000 ) /* (SSC) Control Register */ +#define AT91C_SSC_IMR ( ( AT91_REG * ) 0xFFFD404C ) /* (SSC) Interrupt Mask Register */ +#define AT91C_SSC_RFMR ( ( AT91_REG * ) 0xFFFD4014 ) /* (SSC) Receive Frame Mode Register */ +/* ========== Register definition for TWI peripheral ========== */ +#define AT91C_TWI_IER ( ( AT91_REG * ) 0xFFFB8024 ) /* (TWI) Interrupt Enable Register */ +#define AT91C_TWI_CR ( ( AT91_REG * ) 0xFFFB8000 ) /* (TWI) Control Register */ +#define AT91C_TWI_SR ( ( AT91_REG * ) 0xFFFB8020 ) /* (TWI) Status Register */ +#define AT91C_TWI_IMR ( ( AT91_REG * ) 0xFFFB802C ) /* (TWI) Interrupt Mask Register */ +#define AT91C_TWI_THR ( ( AT91_REG * ) 0xFFFB8034 ) /* (TWI) Transmit Holding Register */ +#define AT91C_TWI_IDR ( ( AT91_REG * ) 0xFFFB8028 ) /* (TWI) Interrupt Disable Register */ +#define AT91C_TWI_IADR ( ( AT91_REG * ) 0xFFFB800C ) /* (TWI) Internal Address Register */ +#define AT91C_TWI_MMR ( ( AT91_REG * ) 0xFFFB8004 ) /* (TWI) Master Mode Register */ +#define AT91C_TWI_CWGR ( ( AT91_REG * ) 0xFFFB8010 ) /* (TWI) Clock Waveform Generator Register */ +#define AT91C_TWI_RHR ( ( AT91_REG * ) 0xFFFB8030 ) /* (TWI) Receive Holding Register */ +/* ========== Register definition for PWMC_CH3 peripheral ========== */ +#define AT91C_PWMC_CH3_CUPDR ( ( AT91_REG * ) 0xFFFCC270 ) /* (PWMC_CH3) Channel Update Register */ +#define AT91C_PWMC_CH3_Reserved ( ( AT91_REG * ) 0xFFFCC274 ) /* (PWMC_CH3) Reserved */ +#define AT91C_PWMC_CH3_CPRDR ( ( AT91_REG * ) 0xFFFCC268 ) /* (PWMC_CH3) Channel Period Register */ +#define AT91C_PWMC_CH3_CDTYR ( ( AT91_REG * ) 0xFFFCC264 ) /* (PWMC_CH3) Channel Duty Cycle Register */ +#define AT91C_PWMC_CH3_CCNTR ( ( AT91_REG * ) 0xFFFCC26C ) /* (PWMC_CH3) Channel Counter Register */ +#define AT91C_PWMC_CH3_CMR ( ( AT91_REG * ) 0xFFFCC260 ) /* (PWMC_CH3) Channel Mode Register */ +/* ========== Register definition for PWMC_CH2 peripheral ========== */ +#define AT91C_PWMC_CH2_Reserved ( ( AT91_REG * ) 0xFFFCC254 ) /* (PWMC_CH2) Reserved */ +#define AT91C_PWMC_CH2_CMR ( ( AT91_REG * ) 0xFFFCC240 ) /* (PWMC_CH2) Channel Mode Register */ +#define AT91C_PWMC_CH2_CCNTR ( ( AT91_REG * ) 0xFFFCC24C ) /* (PWMC_CH2) Channel Counter Register */ +#define AT91C_PWMC_CH2_CPRDR ( ( AT91_REG * ) 0xFFFCC248 ) /* (PWMC_CH2) Channel Period Register */ +#define AT91C_PWMC_CH2_CUPDR ( ( AT91_REG * ) 0xFFFCC250 ) /* (PWMC_CH2) Channel Update Register */ +#define AT91C_PWMC_CH2_CDTYR ( ( AT91_REG * ) 0xFFFCC244 ) /* (PWMC_CH2) Channel Duty Cycle Register */ +/* ========== Register definition for PWMC_CH1 peripheral ========== */ +#define AT91C_PWMC_CH1_Reserved ( ( AT91_REG * ) 0xFFFCC234 ) /* (PWMC_CH1) Reserved */ +#define AT91C_PWMC_CH1_CUPDR ( ( AT91_REG * ) 0xFFFCC230 ) /* (PWMC_CH1) Channel Update Register */ +#define AT91C_PWMC_CH1_CPRDR ( ( AT91_REG * ) 0xFFFCC228 ) /* (PWMC_CH1) Channel Period Register */ +#define AT91C_PWMC_CH1_CCNTR ( ( AT91_REG * ) 0xFFFCC22C ) /* (PWMC_CH1) Channel Counter Register */ +#define AT91C_PWMC_CH1_CDTYR ( ( AT91_REG * ) 0xFFFCC224 ) /* (PWMC_CH1) Channel Duty Cycle Register */ +#define AT91C_PWMC_CH1_CMR ( ( AT91_REG * ) 0xFFFCC220 ) /* (PWMC_CH1) Channel Mode Register */ +/* ========== Register definition for PWMC_CH0 peripheral ========== */ +#define AT91C_PWMC_CH0_Reserved ( ( AT91_REG * ) 0xFFFCC214 ) /* (PWMC_CH0) Reserved */ +#define AT91C_PWMC_CH0_CPRDR ( ( AT91_REG * ) 0xFFFCC208 ) /* (PWMC_CH0) Channel Period Register */ +#define AT91C_PWMC_CH0_CDTYR ( ( AT91_REG * ) 0xFFFCC204 ) /* (PWMC_CH0) Channel Duty Cycle Register */ +#define AT91C_PWMC_CH0_CMR ( ( AT91_REG * ) 0xFFFCC200 ) /* (PWMC_CH0) Channel Mode Register */ +#define AT91C_PWMC_CH0_CUPDR ( ( AT91_REG * ) 0xFFFCC210 ) /* (PWMC_CH0) Channel Update Register */ +#define AT91C_PWMC_CH0_CCNTR ( ( AT91_REG * ) 0xFFFCC20C ) /* (PWMC_CH0) Channel Counter Register */ +/* ========== Register definition for PWMC peripheral ========== */ +#define AT91C_PWMC_IDR ( ( AT91_REG * ) 0xFFFCC014 ) /* (PWMC) PWMC Interrupt Disable Register */ +#define AT91C_PWMC_DIS ( ( AT91_REG * ) 0xFFFCC008 ) /* (PWMC) PWMC Disable Register */ +#define AT91C_PWMC_IER ( ( AT91_REG * ) 0xFFFCC010 ) /* (PWMC) PWMC Interrupt Enable Register */ +#define AT91C_PWMC_VR ( ( AT91_REG * ) 0xFFFCC0FC ) /* (PWMC) PWMC Version Register */ +#define AT91C_PWMC_ISR ( ( AT91_REG * ) 0xFFFCC01C ) /* (PWMC) PWMC Interrupt Status Register */ +#define AT91C_PWMC_SR ( ( AT91_REG * ) 0xFFFCC00C ) /* (PWMC) PWMC Status Register */ +#define AT91C_PWMC_IMR ( ( AT91_REG * ) 0xFFFCC018 ) /* (PWMC) PWMC Interrupt Mask Register */ +#define AT91C_PWMC_MR ( ( AT91_REG * ) 0xFFFCC000 ) /* (PWMC) PWMC Mode Register */ +#define AT91C_PWMC_ENA ( ( AT91_REG * ) 0xFFFCC004 ) /* (PWMC) PWMC Enable Register */ +/* ========== Register definition for UDP peripheral ========== */ +#define AT91C_UDP_IMR ( ( AT91_REG * ) 0xFFFB0018 ) /* (UDP) Interrupt Mask Register */ +#define AT91C_UDP_FADDR ( ( AT91_REG * ) 0xFFFB0008 ) /* (UDP) Function Address Register */ +#define AT91C_UDP_NUM ( ( AT91_REG * ) 0xFFFB0000 ) /* (UDP) Frame Number Register */ +#define AT91C_UDP_FDR ( ( AT91_REG * ) 0xFFFB0050 ) /* (UDP) Endpoint FIFO Data Register */ +#define AT91C_UDP_ISR ( ( AT91_REG * ) 0xFFFB001C ) /* (UDP) Interrupt Status Register */ +#define AT91C_UDP_CSR ( ( AT91_REG * ) 0xFFFB0030 ) /* (UDP) Endpoint Control and Status Register */ +#define AT91C_UDP_IDR ( ( AT91_REG * ) 0xFFFB0014 ) /* (UDP) Interrupt Disable Register */ +#define AT91C_UDP_ICR ( ( AT91_REG * ) 0xFFFB0020 ) /* (UDP) Interrupt Clear Register */ +#define AT91C_UDP_RSTEP ( ( AT91_REG * ) 0xFFFB0028 ) /* (UDP) Reset Endpoint Register */ +#define AT91C_UDP_TXVC ( ( AT91_REG * ) 0xFFFB0074 ) /* (UDP) Transceiver Control Register */ +#define AT91C_UDP_GLBSTATE ( ( AT91_REG * ) 0xFFFB0004 ) /* (UDP) Global State Register */ +#define AT91C_UDP_IER ( ( AT91_REG * ) 0xFFFB0010 ) /* (UDP) Interrupt Enable Register */ +/* ========== Register definition for TC0 peripheral ========== */ +#define AT91C_TC0_SR ( ( AT91_REG * ) 0xFFFA0020 ) /* (TC0) Status Register */ +#define AT91C_TC0_RC ( ( AT91_REG * ) 0xFFFA001C ) /* (TC0) Register C */ +#define AT91C_TC0_RB ( ( AT91_REG * ) 0xFFFA0018 ) /* (TC0) Register B */ +#define AT91C_TC0_CCR ( ( AT91_REG * ) 0xFFFA0000 ) /* (TC0) Channel Control Register */ +#define AT91C_TC0_CMR ( ( AT91_REG * ) 0xFFFA0004 ) /* (TC0) Channel Mode Register (Capture Mode / Waveform Mode) */ +#define AT91C_TC0_IER ( ( AT91_REG * ) 0xFFFA0024 ) /* (TC0) Interrupt Enable Register */ +#define AT91C_TC0_RA ( ( AT91_REG * ) 0xFFFA0014 ) /* (TC0) Register A */ +#define AT91C_TC0_IDR ( ( AT91_REG * ) 0xFFFA0028 ) /* (TC0) Interrupt Disable Register */ +#define AT91C_TC0_CV ( ( AT91_REG * ) 0xFFFA0010 ) /* (TC0) Counter Value */ +#define AT91C_TC0_IMR ( ( AT91_REG * ) 0xFFFA002C ) /* (TC0) Interrupt Mask Register */ +/* ========== Register definition for TC1 peripheral ========== */ +#define AT91C_TC1_RB ( ( AT91_REG * ) 0xFFFA0058 ) /* (TC1) Register B */ +#define AT91C_TC1_CCR ( ( AT91_REG * ) 0xFFFA0040 ) /* (TC1) Channel Control Register */ +#define AT91C_TC1_IER ( ( AT91_REG * ) 0xFFFA0064 ) /* (TC1) Interrupt Enable Register */ +#define AT91C_TC1_IDR ( ( AT91_REG * ) 0xFFFA0068 ) /* (TC1) Interrupt Disable Register */ +#define AT91C_TC1_SR ( ( AT91_REG * ) 0xFFFA0060 ) /* (TC1) Status Register */ +#define AT91C_TC1_CMR ( ( AT91_REG * ) 0xFFFA0044 ) /* (TC1) Channel Mode Register (Capture Mode / Waveform Mode) */ +#define AT91C_TC1_RA ( ( AT91_REG * ) 0xFFFA0054 ) /* (TC1) Register A */ +#define AT91C_TC1_RC ( ( AT91_REG * ) 0xFFFA005C ) /* (TC1) Register C */ +#define AT91C_TC1_IMR ( ( AT91_REG * ) 0xFFFA006C ) /* (TC1) Interrupt Mask Register */ +#define AT91C_TC1_CV ( ( AT91_REG * ) 0xFFFA0050 ) /* (TC1) Counter Value */ +/* ========== Register definition for TC2 peripheral ========== */ +#define AT91C_TC2_CMR ( ( AT91_REG * ) 0xFFFA0084 ) /* (TC2) Channel Mode Register (Capture Mode / Waveform Mode) */ +#define AT91C_TC2_CCR ( ( AT91_REG * ) 0xFFFA0080 ) /* (TC2) Channel Control Register */ +#define AT91C_TC2_CV ( ( AT91_REG * ) 0xFFFA0090 ) /* (TC2) Counter Value */ +#define AT91C_TC2_RA ( ( AT91_REG * ) 0xFFFA0094 ) /* (TC2) Register A */ +#define AT91C_TC2_RB ( ( AT91_REG * ) 0xFFFA0098 ) /* (TC2) Register B */ +#define AT91C_TC2_IDR ( ( AT91_REG * ) 0xFFFA00A8 ) /* (TC2) Interrupt Disable Register */ +#define AT91C_TC2_IMR ( ( AT91_REG * ) 0xFFFA00AC ) /* (TC2) Interrupt Mask Register */ +#define AT91C_TC2_RC ( ( AT91_REG * ) 0xFFFA009C ) /* (TC2) Register C */ +#define AT91C_TC2_IER ( ( AT91_REG * ) 0xFFFA00A4 ) /* (TC2) Interrupt Enable Register */ +#define AT91C_TC2_SR ( ( AT91_REG * ) 0xFFFA00A0 ) /* (TC2) Status Register */ +/* ========== Register definition for TCB peripheral ========== */ +#define AT91C_TCB_BMR ( ( AT91_REG * ) 0xFFFA00C4 ) /* (TCB) TC Block Mode Register */ +#define AT91C_TCB_BCR ( ( AT91_REG * ) 0xFFFA00C0 ) /* (TCB) TC Block Control Register */ +/* ========== Register definition for CAN_MB0 peripheral ========== */ +#define AT91C_CAN_MB0_MDL ( ( AT91_REG * ) 0xFFFD0214 ) /* (CAN_MB0) MailBox Data Low Register */ +#define AT91C_CAN_MB0_MAM ( ( AT91_REG * ) 0xFFFD0204 ) /* (CAN_MB0) MailBox Acceptance Mask Register */ +#define AT91C_CAN_MB0_MCR ( ( AT91_REG * ) 0xFFFD021C ) /* (CAN_MB0) MailBox Control Register */ +#define AT91C_CAN_MB0_MID ( ( AT91_REG * ) 0xFFFD0208 ) /* (CAN_MB0) MailBox ID Register */ +#define AT91C_CAN_MB0_MSR ( ( AT91_REG * ) 0xFFFD0210 ) /* (CAN_MB0) MailBox Status Register */ +#define AT91C_CAN_MB0_MFID ( ( AT91_REG * ) 0xFFFD020C ) /* (CAN_MB0) MailBox Family ID Register */ +#define AT91C_CAN_MB0_MDH ( ( AT91_REG * ) 0xFFFD0218 ) /* (CAN_MB0) MailBox Data High Register */ +#define AT91C_CAN_MB0_MMR ( ( AT91_REG * ) 0xFFFD0200 ) /* (CAN_MB0) MailBox Mode Register */ +/* ========== Register definition for CAN_MB1 peripheral ========== */ +#define AT91C_CAN_MB1_MDL ( ( AT91_REG * ) 0xFFFD0234 ) /* (CAN_MB1) MailBox Data Low Register */ +#define AT91C_CAN_MB1_MID ( ( AT91_REG * ) 0xFFFD0228 ) /* (CAN_MB1) MailBox ID Register */ +#define AT91C_CAN_MB1_MMR ( ( AT91_REG * ) 0xFFFD0220 ) /* (CAN_MB1) MailBox Mode Register */ +#define AT91C_CAN_MB1_MSR ( ( AT91_REG * ) 0xFFFD0230 ) /* (CAN_MB1) MailBox Status Register */ +#define AT91C_CAN_MB1_MAM ( ( AT91_REG * ) 0xFFFD0224 ) /* (CAN_MB1) MailBox Acceptance Mask Register */ +#define AT91C_CAN_MB1_MDH ( ( AT91_REG * ) 0xFFFD0238 ) /* (CAN_MB1) MailBox Data High Register */ +#define AT91C_CAN_MB1_MCR ( ( AT91_REG * ) 0xFFFD023C ) /* (CAN_MB1) MailBox Control Register */ +#define AT91C_CAN_MB1_MFID ( ( AT91_REG * ) 0xFFFD022C ) /* (CAN_MB1) MailBox Family ID Register */ +/* ========== Register definition for CAN_MB2 peripheral ========== */ +#define AT91C_CAN_MB2_MCR ( ( AT91_REG * ) 0xFFFD025C ) /* (CAN_MB2) MailBox Control Register */ +#define AT91C_CAN_MB2_MDH ( ( AT91_REG * ) 0xFFFD0258 ) /* (CAN_MB2) MailBox Data High Register */ +#define AT91C_CAN_MB2_MID ( ( AT91_REG * ) 0xFFFD0248 ) /* (CAN_MB2) MailBox ID Register */ +#define AT91C_CAN_MB2_MDL ( ( AT91_REG * ) 0xFFFD0254 ) /* (CAN_MB2) MailBox Data Low Register */ +#define AT91C_CAN_MB2_MMR ( ( AT91_REG * ) 0xFFFD0240 ) /* (CAN_MB2) MailBox Mode Register */ +#define AT91C_CAN_MB2_MAM ( ( AT91_REG * ) 0xFFFD0244 ) /* (CAN_MB2) MailBox Acceptance Mask Register */ +#define AT91C_CAN_MB2_MFID ( ( AT91_REG * ) 0xFFFD024C ) /* (CAN_MB2) MailBox Family ID Register */ +#define AT91C_CAN_MB2_MSR ( ( AT91_REG * ) 0xFFFD0250 ) /* (CAN_MB2) MailBox Status Register */ +/* ========== Register definition for CAN_MB3 peripheral ========== */ +#define AT91C_CAN_MB3_MFID ( ( AT91_REG * ) 0xFFFD026C ) /* (CAN_MB3) MailBox Family ID Register */ +#define AT91C_CAN_MB3_MAM ( ( AT91_REG * ) 0xFFFD0264 ) /* (CAN_MB3) MailBox Acceptance Mask Register */ +#define AT91C_CAN_MB3_MID ( ( AT91_REG * ) 0xFFFD0268 ) /* (CAN_MB3) MailBox ID Register */ +#define AT91C_CAN_MB3_MCR ( ( AT91_REG * ) 0xFFFD027C ) /* (CAN_MB3) MailBox Control Register */ +#define AT91C_CAN_MB3_MMR ( ( AT91_REG * ) 0xFFFD0260 ) /* (CAN_MB3) MailBox Mode Register */ +#define AT91C_CAN_MB3_MSR ( ( AT91_REG * ) 0xFFFD0270 ) /* (CAN_MB3) MailBox Status Register */ +#define AT91C_CAN_MB3_MDL ( ( AT91_REG * ) 0xFFFD0274 ) /* (CAN_MB3) MailBox Data Low Register */ +#define AT91C_CAN_MB3_MDH ( ( AT91_REG * ) 0xFFFD0278 ) /* (CAN_MB3) MailBox Data High Register */ +/* ========== Register definition for CAN_MB4 peripheral ========== */ +#define AT91C_CAN_MB4_MID ( ( AT91_REG * ) 0xFFFD0288 ) /* (CAN_MB4) MailBox ID Register */ +#define AT91C_CAN_MB4_MMR ( ( AT91_REG * ) 0xFFFD0280 ) /* (CAN_MB4) MailBox Mode Register */ +#define AT91C_CAN_MB4_MDH ( ( AT91_REG * ) 0xFFFD0298 ) /* (CAN_MB4) MailBox Data High Register */ +#define AT91C_CAN_MB4_MFID ( ( AT91_REG * ) 0xFFFD028C ) /* (CAN_MB4) MailBox Family ID Register */ +#define AT91C_CAN_MB4_MSR ( ( AT91_REG * ) 0xFFFD0290 ) /* (CAN_MB4) MailBox Status Register */ +#define AT91C_CAN_MB4_MCR ( ( AT91_REG * ) 0xFFFD029C ) /* (CAN_MB4) MailBox Control Register */ +#define AT91C_CAN_MB4_MDL ( ( AT91_REG * ) 0xFFFD0294 ) /* (CAN_MB4) MailBox Data Low Register */ +#define AT91C_CAN_MB4_MAM ( ( AT91_REG * ) 0xFFFD0284 ) /* (CAN_MB4) MailBox Acceptance Mask Register */ +/* ========== Register definition for CAN_MB5 peripheral ========== */ +#define AT91C_CAN_MB5_MSR ( ( AT91_REG * ) 0xFFFD02B0 ) /* (CAN_MB5) MailBox Status Register */ +#define AT91C_CAN_MB5_MCR ( ( AT91_REG * ) 0xFFFD02BC ) /* (CAN_MB5) MailBox Control Register */ +#define AT91C_CAN_MB5_MFID ( ( AT91_REG * ) 0xFFFD02AC ) /* (CAN_MB5) MailBox Family ID Register */ +#define AT91C_CAN_MB5_MDH ( ( AT91_REG * ) 0xFFFD02B8 ) /* (CAN_MB5) MailBox Data High Register */ +#define AT91C_CAN_MB5_MID ( ( AT91_REG * ) 0xFFFD02A8 ) /* (CAN_MB5) MailBox ID Register */ +#define AT91C_CAN_MB5_MMR ( ( AT91_REG * ) 0xFFFD02A0 ) /* (CAN_MB5) MailBox Mode Register */ +#define AT91C_CAN_MB5_MDL ( ( AT91_REG * ) 0xFFFD02B4 ) /* (CAN_MB5) MailBox Data Low Register */ +#define AT91C_CAN_MB5_MAM ( ( AT91_REG * ) 0xFFFD02A4 ) /* (CAN_MB5) MailBox Acceptance Mask Register */ +/* ========== Register definition for CAN_MB6 peripheral ========== */ +#define AT91C_CAN_MB6_MFID ( ( AT91_REG * ) 0xFFFD02CC ) /* (CAN_MB6) MailBox Family ID Register */ +#define AT91C_CAN_MB6_MID ( ( AT91_REG * ) 0xFFFD02C8 ) /* (CAN_MB6) MailBox ID Register */ +#define AT91C_CAN_MB6_MAM ( ( AT91_REG * ) 0xFFFD02C4 ) /* (CAN_MB6) MailBox Acceptance Mask Register */ +#define AT91C_CAN_MB6_MSR ( ( AT91_REG * ) 0xFFFD02D0 ) /* (CAN_MB6) MailBox Status Register */ +#define AT91C_CAN_MB6_MDL ( ( AT91_REG * ) 0xFFFD02D4 ) /* (CAN_MB6) MailBox Data Low Register */ +#define AT91C_CAN_MB6_MCR ( ( AT91_REG * ) 0xFFFD02DC ) /* (CAN_MB6) MailBox Control Register */ +#define AT91C_CAN_MB6_MDH ( ( AT91_REG * ) 0xFFFD02D8 ) /* (CAN_MB6) MailBox Data High Register */ +#define AT91C_CAN_MB6_MMR ( ( AT91_REG * ) 0xFFFD02C0 ) /* (CAN_MB6) MailBox Mode Register */ +/* ========== Register definition for CAN_MB7 peripheral ========== */ +#define AT91C_CAN_MB7_MCR ( ( AT91_REG * ) 0xFFFD02FC ) /* (CAN_MB7) MailBox Control Register */ +#define AT91C_CAN_MB7_MDH ( ( AT91_REG * ) 0xFFFD02F8 ) /* (CAN_MB7) MailBox Data High Register */ +#define AT91C_CAN_MB7_MFID ( ( AT91_REG * ) 0xFFFD02EC ) /* (CAN_MB7) MailBox Family ID Register */ +#define AT91C_CAN_MB7_MDL ( ( AT91_REG * ) 0xFFFD02F4 ) /* (CAN_MB7) MailBox Data Low Register */ +#define AT91C_CAN_MB7_MID ( ( AT91_REG * ) 0xFFFD02E8 ) /* (CAN_MB7) MailBox ID Register */ +#define AT91C_CAN_MB7_MMR ( ( AT91_REG * ) 0xFFFD02E0 ) /* (CAN_MB7) MailBox Mode Register */ +#define AT91C_CAN_MB7_MAM ( ( AT91_REG * ) 0xFFFD02E4 ) /* (CAN_MB7) MailBox Acceptance Mask Register */ +#define AT91C_CAN_MB7_MSR ( ( AT91_REG * ) 0xFFFD02F0 ) /* (CAN_MB7) MailBox Status Register */ +/* ========== Register definition for CAN peripheral ========== */ +#define AT91C_CAN_TCR ( ( AT91_REG * ) 0xFFFD0024 ) /* (CAN) Transfer Command Register */ +#define AT91C_CAN_IMR ( ( AT91_REG * ) 0xFFFD000C ) /* (CAN) Interrupt Mask Register */ +#define AT91C_CAN_IER ( ( AT91_REG * ) 0xFFFD0004 ) /* (CAN) Interrupt Enable Register */ +#define AT91C_CAN_ECR ( ( AT91_REG * ) 0xFFFD0020 ) /* (CAN) Error Counter Register */ +#define AT91C_CAN_TIMESTP ( ( AT91_REG * ) 0xFFFD001C ) /* (CAN) Time Stamp Register */ +#define AT91C_CAN_MR ( ( AT91_REG * ) 0xFFFD0000 ) /* (CAN) Mode Register */ +#define AT91C_CAN_IDR ( ( AT91_REG * ) 0xFFFD0008 ) /* (CAN) Interrupt Disable Register */ +#define AT91C_CAN_ACR ( ( AT91_REG * ) 0xFFFD0028 ) /* (CAN) Abort Command Register */ +#define AT91C_CAN_TIM ( ( AT91_REG * ) 0xFFFD0018 ) /* (CAN) Timer Register */ +#define AT91C_CAN_SR ( ( AT91_REG * ) 0xFFFD0010 ) /* (CAN) Status Register */ +#define AT91C_CAN_BR ( ( AT91_REG * ) 0xFFFD0014 ) /* (CAN) Baudrate Register */ +#define AT91C_CAN_VR ( ( AT91_REG * ) 0xFFFD00FC ) /* (CAN) Version Register */ +/* ========== Register definition for EMAC peripheral ========== */ +#define AT91C_EMAC_ISR ( ( AT91_REG * ) 0xFFFDC024 ) /* (EMAC) Interrupt Status Register */ +#define AT91C_EMAC_SA4H ( ( AT91_REG * ) 0xFFFDC0B4 ) /* (EMAC) Specific Address 4 Top, Last 2 bytes */ +#define AT91C_EMAC_SA1L ( ( AT91_REG * ) 0xFFFDC098 ) /* (EMAC) Specific Address 1 Bottom, First 4 bytes */ +#define AT91C_EMAC_ELE ( ( AT91_REG * ) 0xFFFDC078 ) /* (EMAC) Excessive Length Errors Register */ +#define AT91C_EMAC_LCOL ( ( AT91_REG * ) 0xFFFDC05C ) /* (EMAC) Late Collision Register */ +#define AT91C_EMAC_RLE ( ( AT91_REG * ) 0xFFFDC088 ) /* (EMAC) Receive Length Field Mismatch Register */ +#define AT91C_EMAC_WOL ( ( AT91_REG * ) 0xFFFDC0C4 ) /* (EMAC) Wake On LAN Register */ +#define AT91C_EMAC_DTF ( ( AT91_REG * ) 0xFFFDC058 ) /* (EMAC) Deferred Transmission Frame Register */ +#define AT91C_EMAC_TUND ( ( AT91_REG * ) 0xFFFDC064 ) /* (EMAC) Transmit Underrun Error Register */ +#define AT91C_EMAC_NCR ( ( AT91_REG * ) 0xFFFDC000 ) /* (EMAC) Network Control Register */ +#define AT91C_EMAC_SA4L ( ( AT91_REG * ) 0xFFFDC0B0 ) /* (EMAC) Specific Address 4 Bottom, First 4 bytes */ +#define AT91C_EMAC_RSR ( ( AT91_REG * ) 0xFFFDC020 ) /* (EMAC) Receive Status Register */ +#define AT91C_EMAC_SA3L ( ( AT91_REG * ) 0xFFFDC0A8 ) /* (EMAC) Specific Address 3 Bottom, First 4 bytes */ +#define AT91C_EMAC_TSR ( ( AT91_REG * ) 0xFFFDC014 ) /* (EMAC) Transmit Status Register */ +#define AT91C_EMAC_IDR ( ( AT91_REG * ) 0xFFFDC02C ) /* (EMAC) Interrupt Disable Register */ +#define AT91C_EMAC_RSE ( ( AT91_REG * ) 0xFFFDC074 ) /* (EMAC) Receive Symbol Errors Register */ +#define AT91C_EMAC_ECOL ( ( AT91_REG * ) 0xFFFDC060 ) /* (EMAC) Excessive Collision Register */ +#define AT91C_EMAC_TID ( ( AT91_REG * ) 0xFFFDC0B8 ) /* (EMAC) Type ID Checking Register */ +#define AT91C_EMAC_HRB ( ( AT91_REG * ) 0xFFFDC090 ) /* (EMAC) Hash Address Bottom[31:0] */ +#define AT91C_EMAC_TBQP ( ( AT91_REG * ) 0xFFFDC01C ) /* (EMAC) Transmit Buffer Queue Pointer */ +#define AT91C_EMAC_USRIO ( ( AT91_REG * ) 0xFFFDC0C0 ) /* (EMAC) USER Input/Output Register */ +#define AT91C_EMAC_PTR ( ( AT91_REG * ) 0xFFFDC038 ) /* (EMAC) Pause Time Register */ +#define AT91C_EMAC_SA2H ( ( AT91_REG * ) 0xFFFDC0A4 ) /* (EMAC) Specific Address 2 Top, Last 2 bytes */ +#define AT91C_EMAC_ROV ( ( AT91_REG * ) 0xFFFDC070 ) /* (EMAC) Receive Overrun Errors Register */ +#define AT91C_EMAC_ALE ( ( AT91_REG * ) 0xFFFDC054 ) /* (EMAC) Alignment Error Register */ +#define AT91C_EMAC_RJA ( ( AT91_REG * ) 0xFFFDC07C ) /* (EMAC) Receive Jabbers Register */ +#define AT91C_EMAC_RBQP ( ( AT91_REG * ) 0xFFFDC018 ) /* (EMAC) Receive Buffer Queue Pointer */ +#define AT91C_EMAC_TPF ( ( AT91_REG * ) 0xFFFDC08C ) /* (EMAC) Transmitted Pause Frames Register */ +#define AT91C_EMAC_NCFGR ( ( AT91_REG * ) 0xFFFDC004 ) /* (EMAC) Network Configuration Register */ +#define AT91C_EMAC_HRT ( ( AT91_REG * ) 0xFFFDC094 ) /* (EMAC) Hash Address Top[63:32] */ +#define AT91C_EMAC_USF ( ( AT91_REG * ) 0xFFFDC080 ) /* (EMAC) Undersize Frames Register */ +#define AT91C_EMAC_FCSE ( ( AT91_REG * ) 0xFFFDC050 ) /* (EMAC) Frame Check Sequence Error Register */ +#define AT91C_EMAC_TPQ ( ( AT91_REG * ) 0xFFFDC0BC ) /* (EMAC) Transmit Pause Quantum Register */ +#define AT91C_EMAC_MAN ( ( AT91_REG * ) 0xFFFDC034 ) /* (EMAC) PHY Maintenance Register */ +#define AT91C_EMAC_FTO ( ( AT91_REG * ) 0xFFFDC040 ) /* (EMAC) Frames Transmitted OK Register */ +#define AT91C_EMAC_REV ( ( AT91_REG * ) 0xFFFDC0FC ) /* (EMAC) Revision Register */ +#define AT91C_EMAC_IMR ( ( AT91_REG * ) 0xFFFDC030 ) /* (EMAC) Interrupt Mask Register */ +#define AT91C_EMAC_SCF ( ( AT91_REG * ) 0xFFFDC044 ) /* (EMAC) Single Collision Frame Register */ +#define AT91C_EMAC_PFR ( ( AT91_REG * ) 0xFFFDC03C ) /* (EMAC) Pause Frames received Register */ +#define AT91C_EMAC_MCF ( ( AT91_REG * ) 0xFFFDC048 ) /* (EMAC) Multiple Collision Frame Register */ +#define AT91C_EMAC_NSR ( ( AT91_REG * ) 0xFFFDC008 ) /* (EMAC) Network Status Register */ +#define AT91C_EMAC_SA2L ( ( AT91_REG * ) 0xFFFDC0A0 ) /* (EMAC) Specific Address 2 Bottom, First 4 bytes */ +#define AT91C_EMAC_FRO ( ( AT91_REG * ) 0xFFFDC04C ) /* (EMAC) Frames Received OK Register */ +#define AT91C_EMAC_IER ( ( AT91_REG * ) 0xFFFDC028 ) /* (EMAC) Interrupt Enable Register */ +#define AT91C_EMAC_SA1H ( ( AT91_REG * ) 0xFFFDC09C ) /* (EMAC) Specific Address 1 Top, Last 2 bytes */ +#define AT91C_EMAC_CSE ( ( AT91_REG * ) 0xFFFDC068 ) /* (EMAC) Carrier Sense Error Register */ +#define AT91C_EMAC_SA3H ( ( AT91_REG * ) 0xFFFDC0AC ) /* (EMAC) Specific Address 3 Top, Last 2 bytes */ +#define AT91C_EMAC_RRE ( ( AT91_REG * ) 0xFFFDC06C ) /* (EMAC) Receive Ressource Error Register */ +#define AT91C_EMAC_STE ( ( AT91_REG * ) 0xFFFDC084 ) /* (EMAC) SQE Test Error Register */ +/* ========== Register definition for PDC_ADC peripheral ========== */ +#define AT91C_ADC_PTSR ( ( AT91_REG * ) 0xFFFD8124 ) /* (PDC_ADC) PDC Transfer Status Register */ +#define AT91C_ADC_PTCR ( ( AT91_REG * ) 0xFFFD8120 ) /* (PDC_ADC) PDC Transfer Control Register */ +#define AT91C_ADC_TNPR ( ( AT91_REG * ) 0xFFFD8118 ) /* (PDC_ADC) Transmit Next Pointer Register */ +#define AT91C_ADC_TNCR ( ( AT91_REG * ) 0xFFFD811C ) /* (PDC_ADC) Transmit Next Counter Register */ +#define AT91C_ADC_RNPR ( ( AT91_REG * ) 0xFFFD8110 ) /* (PDC_ADC) Receive Next Pointer Register */ +#define AT91C_ADC_RNCR ( ( AT91_REG * ) 0xFFFD8114 ) /* (PDC_ADC) Receive Next Counter Register */ +#define AT91C_ADC_RPR ( ( AT91_REG * ) 0xFFFD8100 ) /* (PDC_ADC) Receive Pointer Register */ +#define AT91C_ADC_TCR ( ( AT91_REG * ) 0xFFFD810C ) /* (PDC_ADC) Transmit Counter Register */ +#define AT91C_ADC_TPR ( ( AT91_REG * ) 0xFFFD8108 ) /* (PDC_ADC) Transmit Pointer Register */ +#define AT91C_ADC_RCR ( ( AT91_REG * ) 0xFFFD8104 ) /* (PDC_ADC) Receive Counter Register */ +/* ========== Register definition for ADC peripheral ========== */ +#define AT91C_ADC_CDR2 ( ( AT91_REG * ) 0xFFFD8038 ) /* (ADC) ADC Channel Data Register 2 */ +#define AT91C_ADC_CDR3 ( ( AT91_REG * ) 0xFFFD803C ) /* (ADC) ADC Channel Data Register 3 */ +#define AT91C_ADC_CDR0 ( ( AT91_REG * ) 0xFFFD8030 ) /* (ADC) ADC Channel Data Register 0 */ +#define AT91C_ADC_CDR5 ( ( AT91_REG * ) 0xFFFD8044 ) /* (ADC) ADC Channel Data Register 5 */ +#define AT91C_ADC_CHDR ( ( AT91_REG * ) 0xFFFD8014 ) /* (ADC) ADC Channel Disable Register */ +#define AT91C_ADC_SR ( ( AT91_REG * ) 0xFFFD801C ) /* (ADC) ADC Status Register */ +#define AT91C_ADC_CDR4 ( ( AT91_REG * ) 0xFFFD8040 ) /* (ADC) ADC Channel Data Register 4 */ +#define AT91C_ADC_CDR1 ( ( AT91_REG * ) 0xFFFD8034 ) /* (ADC) ADC Channel Data Register 1 */ +#define AT91C_ADC_LCDR ( ( AT91_REG * ) 0xFFFD8020 ) /* (ADC) ADC Last Converted Data Register */ +#define AT91C_ADC_IDR ( ( AT91_REG * ) 0xFFFD8028 ) /* (ADC) ADC Interrupt Disable Register */ +#define AT91C_ADC_CR ( ( AT91_REG * ) 0xFFFD8000 ) /* (ADC) ADC Control Register */ +#define AT91C_ADC_CDR7 ( ( AT91_REG * ) 0xFFFD804C ) /* (ADC) ADC Channel Data Register 7 */ +#define AT91C_ADC_CDR6 ( ( AT91_REG * ) 0xFFFD8048 ) /* (ADC) ADC Channel Data Register 6 */ +#define AT91C_ADC_IER ( ( AT91_REG * ) 0xFFFD8024 ) /* (ADC) ADC Interrupt Enable Register */ +#define AT91C_ADC_CHER ( ( AT91_REG * ) 0xFFFD8010 ) /* (ADC) ADC Channel Enable Register */ +#define AT91C_ADC_CHSR ( ( AT91_REG * ) 0xFFFD8018 ) /* (ADC) ADC Channel Status Register */ +#define AT91C_ADC_MR ( ( AT91_REG * ) 0xFFFD8004 ) /* (ADC) ADC Mode Register */ +#define AT91C_ADC_IMR ( ( AT91_REG * ) 0xFFFD802C ) /* (ADC) ADC Interrupt Mask Register */ +/* ========== Register definition for PDC_AES peripheral ========== */ +#define AT91C_AES_TPR ( ( AT91_REG * ) 0xFFFA4108 ) /* (PDC_AES) Transmit Pointer Register */ +#define AT91C_AES_PTCR ( ( AT91_REG * ) 0xFFFA4120 ) /* (PDC_AES) PDC Transfer Control Register */ +#define AT91C_AES_RNPR ( ( AT91_REG * ) 0xFFFA4110 ) /* (PDC_AES) Receive Next Pointer Register */ +#define AT91C_AES_TNCR ( ( AT91_REG * ) 0xFFFA411C ) /* (PDC_AES) Transmit Next Counter Register */ +#define AT91C_AES_TCR ( ( AT91_REG * ) 0xFFFA410C ) /* (PDC_AES) Transmit Counter Register */ +#define AT91C_AES_RCR ( ( AT91_REG * ) 0xFFFA4104 ) /* (PDC_AES) Receive Counter Register */ +#define AT91C_AES_RNCR ( ( AT91_REG * ) 0xFFFA4114 ) /* (PDC_AES) Receive Next Counter Register */ +#define AT91C_AES_TNPR ( ( AT91_REG * ) 0xFFFA4118 ) /* (PDC_AES) Transmit Next Pointer Register */ +#define AT91C_AES_RPR ( ( AT91_REG * ) 0xFFFA4100 ) /* (PDC_AES) Receive Pointer Register */ +#define AT91C_AES_PTSR ( ( AT91_REG * ) 0xFFFA4124 ) /* (PDC_AES) PDC Transfer Status Register */ +/* ========== Register definition for AES peripheral ========== */ +#define AT91C_AES_IVxR ( ( AT91_REG * ) 0xFFFA4060 ) /* (AES) Initialization Vector x Register */ +#define AT91C_AES_MR ( ( AT91_REG * ) 0xFFFA4004 ) /* (AES) Mode Register */ +#define AT91C_AES_VR ( ( AT91_REG * ) 0xFFFA40FC ) /* (AES) AES Version Register */ +#define AT91C_AES_ODATAxR ( ( AT91_REG * ) 0xFFFA4050 ) /* (AES) Output Data x Register */ +#define AT91C_AES_IDATAxR ( ( AT91_REG * ) 0xFFFA4040 ) /* (AES) Input Data x Register */ +#define AT91C_AES_CR ( ( AT91_REG * ) 0xFFFA4000 ) /* (AES) Control Register */ +#define AT91C_AES_IDR ( ( AT91_REG * ) 0xFFFA4014 ) /* (AES) Interrupt Disable Register */ +#define AT91C_AES_IMR ( ( AT91_REG * ) 0xFFFA4018 ) /* (AES) Interrupt Mask Register */ +#define AT91C_AES_IER ( ( AT91_REG * ) 0xFFFA4010 ) /* (AES) Interrupt Enable Register */ +#define AT91C_AES_KEYWxR ( ( AT91_REG * ) 0xFFFA4020 ) /* (AES) Key Word x Register */ +#define AT91C_AES_ISR ( ( AT91_REG * ) 0xFFFA401C ) /* (AES) Interrupt Status Register */ +/* ========== Register definition for PDC_TDES peripheral ========== */ +#define AT91C_TDES_RNCR ( ( AT91_REG * ) 0xFFFA8114 ) /* (PDC_TDES) Receive Next Counter Register */ +#define AT91C_TDES_TCR ( ( AT91_REG * ) 0xFFFA810C ) /* (PDC_TDES) Transmit Counter Register */ +#define AT91C_TDES_RCR ( ( AT91_REG * ) 0xFFFA8104 ) /* (PDC_TDES) Receive Counter Register */ +#define AT91C_TDES_TNPR ( ( AT91_REG * ) 0xFFFA8118 ) /* (PDC_TDES) Transmit Next Pointer Register */ +#define AT91C_TDES_RNPR ( ( AT91_REG * ) 0xFFFA8110 ) /* (PDC_TDES) Receive Next Pointer Register */ +#define AT91C_TDES_RPR ( ( AT91_REG * ) 0xFFFA8100 ) /* (PDC_TDES) Receive Pointer Register */ +#define AT91C_TDES_TNCR ( ( AT91_REG * ) 0xFFFA811C ) /* (PDC_TDES) Transmit Next Counter Register */ +#define AT91C_TDES_TPR ( ( AT91_REG * ) 0xFFFA8108 ) /* (PDC_TDES) Transmit Pointer Register */ +#define AT91C_TDES_PTSR ( ( AT91_REG * ) 0xFFFA8124 ) /* (PDC_TDES) PDC Transfer Status Register */ +#define AT91C_TDES_PTCR ( ( AT91_REG * ) 0xFFFA8120 ) /* (PDC_TDES) PDC Transfer Control Register */ +/* ========== Register definition for TDES peripheral ========== */ +#define AT91C_TDES_KEY2WxR ( ( AT91_REG * ) 0xFFFA8028 ) /* (TDES) Key 2 Word x Register */ +#define AT91C_TDES_KEY3WxR ( ( AT91_REG * ) 0xFFFA8030 ) /* (TDES) Key 3 Word x Register */ +#define AT91C_TDES_IDR ( ( AT91_REG * ) 0xFFFA8014 ) /* (TDES) Interrupt Disable Register */ +#define AT91C_TDES_VR ( ( AT91_REG * ) 0xFFFA80FC ) /* (TDES) TDES Version Register */ +#define AT91C_TDES_IVxR ( ( AT91_REG * ) 0xFFFA8060 ) /* (TDES) Initialization Vector x Register */ +#define AT91C_TDES_ODATAxR ( ( AT91_REG * ) 0xFFFA8050 ) /* (TDES) Output Data x Register */ +#define AT91C_TDES_IMR ( ( AT91_REG * ) 0xFFFA8018 ) /* (TDES) Interrupt Mask Register */ +#define AT91C_TDES_MR ( ( AT91_REG * ) 0xFFFA8004 ) /* (TDES) Mode Register */ +#define AT91C_TDES_CR ( ( AT91_REG * ) 0xFFFA8000 ) /* (TDES) Control Register */ +#define AT91C_TDES_IER ( ( AT91_REG * ) 0xFFFA8010 ) /* (TDES) Interrupt Enable Register */ +#define AT91C_TDES_ISR ( ( AT91_REG * ) 0xFFFA801C ) /* (TDES) Interrupt Status Register */ +#define AT91C_TDES_IDATAxR ( ( AT91_REG * ) 0xFFFA8040 ) /* (TDES) Input Data x Register */ +#define AT91C_TDES_KEY1WxR ( ( AT91_REG * ) 0xFFFA8020 ) /* (TDES) Key 1 Word x Register */ + +/* ***************************************************************************** */ +/* PIO DEFINITIONS FOR AT91SAM7X256 */ +/* ***************************************************************************** */ +#define AT91C_PIO_PA0 ( ( unsigned int ) 1 << 0 ) /* Pin Controlled by PA0 */ +#define AT91C_PA0_RXD0 ( ( unsigned int ) AT91C_PIO_PA0 ) /* USART 0 Receive Data */ +#define AT91C_PIO_PA1 ( ( unsigned int ) 1 << 1 ) /* Pin Controlled by PA1 */ +#define AT91C_PA1_TXD0 ( ( unsigned int ) AT91C_PIO_PA1 ) /* USART 0 Transmit Data */ +#define AT91C_PIO_PA10 ( ( unsigned int ) 1 << 10 ) /* Pin Controlled by PA10 */ +#define AT91C_PA10_TWD ( ( unsigned int ) AT91C_PIO_PA10 ) /* TWI Two-wire Serial Data */ +#define AT91C_PIO_PA11 ( ( unsigned int ) 1 << 11 ) /* Pin Controlled by PA11 */ +#define AT91C_PA11_TWCK ( ( unsigned int ) AT91C_PIO_PA11 ) /* TWI Two-wire Serial Clock */ +#define AT91C_PIO_PA12 ( ( unsigned int ) 1 << 12 ) /* Pin Controlled by PA12 */ +#define AT91C_PA12_NPCS00 ( ( unsigned int ) AT91C_PIO_PA12 ) /* SPI 0 Peripheral Chip Select 0 */ +#define AT91C_PIO_PA13 ( ( unsigned int ) 1 << 13 ) /* Pin Controlled by PA13 */ +#define AT91C_PA13_NPCS01 ( ( unsigned int ) AT91C_PIO_PA13 ) /* SPI 0 Peripheral Chip Select 1 */ +#define AT91C_PA13_PCK1 ( ( unsigned int ) AT91C_PIO_PA13 ) /* PMC Programmable Clock Output 1 */ +#define AT91C_PIO_PA14 ( ( unsigned int ) 1 << 14 ) /* Pin Controlled by PA14 */ +#define AT91C_PA14_NPCS02 ( ( unsigned int ) AT91C_PIO_PA14 ) /* SPI 0 Peripheral Chip Select 2 */ +#define AT91C_PA14_IRQ1 ( ( unsigned int ) AT91C_PIO_PA14 ) /* External Interrupt 1 */ +#define AT91C_PIO_PA15 ( ( unsigned int ) 1 << 15 ) /* Pin Controlled by PA15 */ +#define AT91C_PA15_NPCS03 ( ( unsigned int ) AT91C_PIO_PA15 ) /* SPI 0 Peripheral Chip Select 3 */ +#define AT91C_PA15_TCLK2 ( ( unsigned int ) AT91C_PIO_PA15 ) /* Timer Counter 2 external clock input */ +#define AT91C_PIO_PA16 ( ( unsigned int ) 1 << 16 ) /* Pin Controlled by PA16 */ +#define AT91C_PA16_MISO0 ( ( unsigned int ) AT91C_PIO_PA16 ) /* SPI 0 Master In Slave */ +#define AT91C_PIO_PA17 ( ( unsigned int ) 1 << 17 ) /* Pin Controlled by PA17 */ +#define AT91C_PA17_MOSI0 ( ( unsigned int ) AT91C_PIO_PA17 ) /* SPI 0 Master Out Slave */ +#define AT91C_PIO_PA18 ( ( unsigned int ) 1 << 18 ) /* Pin Controlled by PA18 */ +#define AT91C_PA18_SPCK0 ( ( unsigned int ) AT91C_PIO_PA18 ) /* SPI 0 Serial Clock */ +#define AT91C_PIO_PA19 ( ( unsigned int ) 1 << 19 ) /* Pin Controlled by PA19 */ +#define AT91C_PA19_CANRX ( ( unsigned int ) AT91C_PIO_PA19 ) /* CAN Receive */ +#define AT91C_PIO_PA2 ( ( unsigned int ) 1 << 2 ) /* Pin Controlled by PA2 */ +#define AT91C_PA2_SCK0 ( ( unsigned int ) AT91C_PIO_PA2 ) /* USART 0 Serial Clock */ +#define AT91C_PA2_NPCS11 ( ( unsigned int ) AT91C_PIO_PA2 ) /* SPI 1 Peripheral Chip Select 1 */ +#define AT91C_PIO_PA20 ( ( unsigned int ) 1 << 20 ) /* Pin Controlled by PA20 */ +#define AT91C_PA20_CANTX ( ( unsigned int ) AT91C_PIO_PA20 ) /* CAN Transmit */ +#define AT91C_PIO_PA21 ( ( unsigned int ) 1 << 21 ) /* Pin Controlled by PA21 */ +#define AT91C_PA21_TF ( ( unsigned int ) AT91C_PIO_PA21 ) /* SSC Transmit Frame Sync */ +#define AT91C_PA21_NPCS10 ( ( unsigned int ) AT91C_PIO_PA21 ) /* SPI 1 Peripheral Chip Select 0 */ +#define AT91C_PIO_PA22 ( ( unsigned int ) 1 << 22 ) /* Pin Controlled by PA22 */ +#define AT91C_PA22_TK ( ( unsigned int ) AT91C_PIO_PA22 ) /* SSC Transmit Clock */ +#define AT91C_PA22_SPCK1 ( ( unsigned int ) AT91C_PIO_PA22 ) /* SPI 1 Serial Clock */ +#define AT91C_PIO_PA23 ( ( unsigned int ) 1 << 23 ) /* Pin Controlled by PA23 */ +#define AT91C_PA23_TD ( ( unsigned int ) AT91C_PIO_PA23 ) /* SSC Transmit data */ +#define AT91C_PA23_MOSI1 ( ( unsigned int ) AT91C_PIO_PA23 ) /* SPI 1 Master Out Slave */ +#define AT91C_PIO_PA24 ( ( unsigned int ) 1 << 24 ) /* Pin Controlled by PA24 */ +#define AT91C_PA24_RD ( ( unsigned int ) AT91C_PIO_PA24 ) /* SSC Receive Data */ +#define AT91C_PA24_MISO1 ( ( unsigned int ) AT91C_PIO_PA24 ) /* SPI 1 Master In Slave */ +#define AT91C_PIO_PA25 ( ( unsigned int ) 1 << 25 ) /* Pin Controlled by PA25 */ +#define AT91C_PA25_RK ( ( unsigned int ) AT91C_PIO_PA25 ) /* SSC Receive Clock */ +#define AT91C_PA25_NPCS11 ( ( unsigned int ) AT91C_PIO_PA25 ) /* SPI 1 Peripheral Chip Select 1 */ +#define AT91C_PIO_PA26 ( ( unsigned int ) 1 << 26 ) /* Pin Controlled by PA26 */ +#define AT91C_PA26_RF ( ( unsigned int ) AT91C_PIO_PA26 ) /* SSC Receive Frame Sync */ +#define AT91C_PA26_NPCS12 ( ( unsigned int ) AT91C_PIO_PA26 ) /* SPI 1 Peripheral Chip Select 2 */ +#define AT91C_PIO_PA27 ( ( unsigned int ) 1 << 27 ) /* Pin Controlled by PA27 */ +#define AT91C_PA27_DRXD ( ( unsigned int ) AT91C_PIO_PA27 ) /* DBGU Debug Receive Data */ +#define AT91C_PA27_PCK3 ( ( unsigned int ) AT91C_PIO_PA27 ) /* PMC Programmable Clock Output 3 */ +#define AT91C_PIO_PA28 ( ( unsigned int ) 1 << 28 ) /* Pin Controlled by PA28 */ +#define AT91C_PA28_DTXD ( ( unsigned int ) AT91C_PIO_PA28 ) /* DBGU Debug Transmit Data */ +#define AT91C_PIO_PA29 ( ( unsigned int ) 1 << 29 ) /* Pin Controlled by PA29 */ +#define AT91C_PA29_FIQ ( ( unsigned int ) AT91C_PIO_PA29 ) /* AIC Fast Interrupt Input */ +#define AT91C_PA29_NPCS13 ( ( unsigned int ) AT91C_PIO_PA29 ) /* SPI 1 Peripheral Chip Select 3 */ +#define AT91C_PIO_PA3 ( ( unsigned int ) 1 << 3 ) /* Pin Controlled by PA3 */ +#define AT91C_PA3_RTS0 ( ( unsigned int ) AT91C_PIO_PA3 ) /* USART 0 Ready To Send */ +#define AT91C_PA3_NPCS12 ( ( unsigned int ) AT91C_PIO_PA3 ) /* SPI 1 Peripheral Chip Select 2 */ +#define AT91C_PIO_PA30 ( ( unsigned int ) 1 << 30 ) /* Pin Controlled by PA30 */ +#define AT91C_PA30_IRQ0 ( ( unsigned int ) AT91C_PIO_PA30 ) /* External Interrupt 0 */ +#define AT91C_PA30_PCK2 ( ( unsigned int ) AT91C_PIO_PA30 ) /* PMC Programmable Clock Output 2 */ +#define AT91C_PIO_PA4 ( ( unsigned int ) 1 << 4 ) /* Pin Controlled by PA4 */ +#define AT91C_PA4_CTS0 ( ( unsigned int ) AT91C_PIO_PA4 ) /* USART 0 Clear To Send */ +#define AT91C_PA4_NPCS13 ( ( unsigned int ) AT91C_PIO_PA4 ) /* SPI 1 Peripheral Chip Select 3 */ +#define AT91C_PIO_PA5 ( ( unsigned int ) 1 << 5 ) /* Pin Controlled by PA5 */ +#define AT91C_PA5_RXD1 ( ( unsigned int ) AT91C_PIO_PA5 ) /* USART 1 Receive Data */ +#define AT91C_PIO_PA6 ( ( unsigned int ) 1 << 6 ) /* Pin Controlled by PA6 */ +#define AT91C_PA6_TXD1 ( ( unsigned int ) AT91C_PIO_PA6 ) /* USART 1 Transmit Data */ +#define AT91C_PIO_PA7 ( ( unsigned int ) 1 << 7 ) /* Pin Controlled by PA7 */ +#define AT91C_PA7_SCK1 ( ( unsigned int ) AT91C_PIO_PA7 ) /* USART 1 Serial Clock */ +#define AT91C_PA7_NPCS01 ( ( unsigned int ) AT91C_PIO_PA7 ) /* SPI 0 Peripheral Chip Select 1 */ +#define AT91C_PIO_PA8 ( ( unsigned int ) 1 << 8 ) /* Pin Controlled by PA8 */ +#define AT91C_PA8_RTS1 ( ( unsigned int ) AT91C_PIO_PA8 ) /* USART 1 Ready To Send */ +#define AT91C_PA8_NPCS02 ( ( unsigned int ) AT91C_PIO_PA8 ) /* SPI 0 Peripheral Chip Select 2 */ +#define AT91C_PIO_PA9 ( ( unsigned int ) 1 << 9 ) /* Pin Controlled by PA9 */ +#define AT91C_PA9_CTS1 ( ( unsigned int ) AT91C_PIO_PA9 ) /* USART 1 Clear To Send */ +#define AT91C_PA9_NPCS03 ( ( unsigned int ) AT91C_PIO_PA9 ) /* SPI 0 Peripheral Chip Select 3 */ +#define AT91C_PIO_PB0 ( ( unsigned int ) 1 << 0 ) /* Pin Controlled by PB0 */ +#define AT91C_PB0_ETXCK_EREFCK ( ( unsigned int ) AT91C_PIO_PB0 ) /* Ethernet MAC Transmit Clock/Reference Clock */ +#define AT91C_PB0_PCK0 ( ( unsigned int ) AT91C_PIO_PB0 ) /* PMC Programmable Clock Output 0 */ +#define AT91C_PIO_PB1 ( ( unsigned int ) 1 << 1 ) /* Pin Controlled by PB1 */ +#define AT91C_PB1_ETXEN ( ( unsigned int ) AT91C_PIO_PB1 ) /* Ethernet MAC Transmit Enable */ +#define AT91C_PIO_PB10 ( ( unsigned int ) 1 << 10 ) /* Pin Controlled by PB10 */ +#define AT91C_PB10_ETX2 ( ( unsigned int ) AT91C_PIO_PB10 ) /* Ethernet MAC Transmit Data 2 */ +#define AT91C_PB10_NPCS11 ( ( unsigned int ) AT91C_PIO_PB10 ) /* SPI 1 Peripheral Chip Select 1 */ +#define AT91C_PIO_PB11 ( ( unsigned int ) 1 << 11 ) /* Pin Controlled by PB11 */ +#define AT91C_PB11_ETX3 ( ( unsigned int ) AT91C_PIO_PB11 ) /* Ethernet MAC Transmit Data 3 */ +#define AT91C_PB11_NPCS12 ( ( unsigned int ) AT91C_PIO_PB11 ) /* SPI 1 Peripheral Chip Select 2 */ +#define AT91C_PIO_PB12 ( ( unsigned int ) 1 << 12 ) /* Pin Controlled by PB12 */ +#define AT91C_PB12_ETXER ( ( unsigned int ) AT91C_PIO_PB12 ) /* Ethernet MAC Transmit Coding Error */ +#define AT91C_PB12_TCLK0 ( ( unsigned int ) AT91C_PIO_PB12 ) /* Timer Counter 0 external clock input */ +#define AT91C_PIO_PB13 ( ( unsigned int ) 1 << 13 ) /* Pin Controlled by PB13 */ +#define AT91C_PB13_ERX2 ( ( unsigned int ) AT91C_PIO_PB13 ) /* Ethernet MAC Receive Data 2 */ +#define AT91C_PB13_NPCS01 ( ( unsigned int ) AT91C_PIO_PB13 ) /* SPI 0 Peripheral Chip Select 1 */ +#define AT91C_PIO_PB14 ( ( unsigned int ) 1 << 14 ) /* Pin Controlled by PB14 */ +#define AT91C_PB14_ERX3 ( ( unsigned int ) AT91C_PIO_PB14 ) /* Ethernet MAC Receive Data 3 */ +#define AT91C_PB14_NPCS02 ( ( unsigned int ) AT91C_PIO_PB14 ) /* SPI 0 Peripheral Chip Select 2 */ +#define AT91C_PIO_PB15 ( ( unsigned int ) 1 << 15 ) /* Pin Controlled by PB15 */ +#define AT91C_PB15_ERXDV ( ( unsigned int ) AT91C_PIO_PB15 ) /* Ethernet MAC Receive Data Valid */ +#define AT91C_PIO_PB16 ( ( unsigned int ) 1 << 16 ) /* Pin Controlled by PB16 */ +#define AT91C_PB16_ECOL ( ( unsigned int ) AT91C_PIO_PB16 ) /* Ethernet MAC Collision Detected */ +#define AT91C_PB16_NPCS13 ( ( unsigned int ) AT91C_PIO_PB16 ) /* SPI 1 Peripheral Chip Select 3 */ +#define AT91C_PIO_PB17 ( ( unsigned int ) 1 << 17 ) /* Pin Controlled by PB17 */ +#define AT91C_PB17_ERXCK ( ( unsigned int ) AT91C_PIO_PB17 ) /* Ethernet MAC Receive Clock */ +#define AT91C_PB17_NPCS03 ( ( unsigned int ) AT91C_PIO_PB17 ) /* SPI 0 Peripheral Chip Select 3 */ +#define AT91C_PIO_PB18 ( ( unsigned int ) 1 << 18 ) /* Pin Controlled by PB18 */ +#define AT91C_PB18_EF100 ( ( unsigned int ) AT91C_PIO_PB18 ) /* Ethernet MAC Force 100 Mbits/sec */ +#define AT91C_PB18_ADTRG ( ( unsigned int ) AT91C_PIO_PB18 ) /* ADC External Trigger */ +#define AT91C_PIO_PB19 ( ( unsigned int ) 1 << 19 ) /* Pin Controlled by PB19 */ +#define AT91C_PB19_PWM0 ( ( unsigned int ) AT91C_PIO_PB19 ) /* PWM Channel 0 */ +#define AT91C_PB19_TCLK1 ( ( unsigned int ) AT91C_PIO_PB19 ) /* Timer Counter 1 external clock input */ +#define AT91C_PIO_PB2 ( ( unsigned int ) 1 << 2 ) /* Pin Controlled by PB2 */ +#define AT91C_PB2_ETX0 ( ( unsigned int ) AT91C_PIO_PB2 ) /* Ethernet MAC Transmit Data 0 */ +#define AT91C_PIO_PB20 ( ( unsigned int ) 1 << 20 ) /* Pin Controlled by PB20 */ +#define AT91C_PB20_PWM1 ( ( unsigned int ) AT91C_PIO_PB20 ) /* PWM Channel 1 */ +#define AT91C_PB20_PCK0 ( ( unsigned int ) AT91C_PIO_PB20 ) /* PMC Programmable Clock Output 0 */ +#define AT91C_PIO_PB21 ( ( unsigned int ) 1 << 21 ) /* Pin Controlled by PB21 */ +#define AT91C_PB21_PWM2 ( ( unsigned int ) AT91C_PIO_PB21 ) /* PWM Channel 2 */ +#define AT91C_PB21_PCK1 ( ( unsigned int ) AT91C_PIO_PB21 ) /* PMC Programmable Clock Output 1 */ +#define AT91C_PIO_PB22 ( ( unsigned int ) 1 << 22 ) /* Pin Controlled by PB22 */ +#define AT91C_PB22_PWM3 ( ( unsigned int ) AT91C_PIO_PB22 ) /* PWM Channel 3 */ +#define AT91C_PB22_PCK2 ( ( unsigned int ) AT91C_PIO_PB22 ) /* PMC Programmable Clock Output 2 */ +#define AT91C_PIO_PB23 ( ( unsigned int ) 1 << 23 ) /* Pin Controlled by PB23 */ +#define AT91C_PB23_TIOA0 ( ( unsigned int ) AT91C_PIO_PB23 ) /* Timer Counter 0 Multipurpose Timer I/O Pin A */ +#define AT91C_PB23_DCD1 ( ( unsigned int ) AT91C_PIO_PB23 ) /* USART 1 Data Carrier Detect */ +#define AT91C_PIO_PB24 ( ( unsigned int ) 1 << 24 ) /* Pin Controlled by PB24 */ +#define AT91C_PB24_TIOB0 ( ( unsigned int ) AT91C_PIO_PB24 ) /* Timer Counter 0 Multipurpose Timer I/O Pin B */ +#define AT91C_PB24_DSR1 ( ( unsigned int ) AT91C_PIO_PB24 ) /* USART 1 Data Set ready */ +#define AT91C_PIO_PB25 ( ( unsigned int ) 1 << 25 ) /* Pin Controlled by PB25 */ +#define AT91C_PB25_TIOA1 ( ( unsigned int ) AT91C_PIO_PB25 ) /* Timer Counter 1 Multipurpose Timer I/O Pin A */ +#define AT91C_PB25_DTR1 ( ( unsigned int ) AT91C_PIO_PB25 ) /* USART 1 Data Terminal ready */ +#define AT91C_PIO_PB26 ( ( unsigned int ) 1 << 26 ) /* Pin Controlled by PB26 */ +#define AT91C_PB26_TIOB1 ( ( unsigned int ) AT91C_PIO_PB26 ) /* Timer Counter 1 Multipurpose Timer I/O Pin B */ +#define AT91C_PB26_RI1 ( ( unsigned int ) AT91C_PIO_PB26 ) /* USART 1 Ring Indicator */ +#define AT91C_PIO_PB27 ( ( unsigned int ) 1 << 27 ) /* Pin Controlled by PB27 */ +#define AT91C_PB27_TIOA2 ( ( unsigned int ) AT91C_PIO_PB27 ) /* Timer Counter 2 Multipurpose Timer I/O Pin A */ +#define AT91C_PB27_PWM0 ( ( unsigned int ) AT91C_PIO_PB27 ) /* PWM Channel 0 */ +#define AT91C_PIO_PB28 ( ( unsigned int ) 1 << 28 ) /* Pin Controlled by PB28 */ +#define AT91C_PB28_TIOB2 ( ( unsigned int ) AT91C_PIO_PB28 ) /* Timer Counter 2 Multipurpose Timer I/O Pin B */ +#define AT91C_PB28_PWM1 ( ( unsigned int ) AT91C_PIO_PB28 ) /* PWM Channel 1 */ +#define AT91C_PIO_PB29 ( ( unsigned int ) 1 << 29 ) /* Pin Controlled by PB29 */ +#define AT91C_PB29_PCK1 ( ( unsigned int ) AT91C_PIO_PB29 ) /* PMC Programmable Clock Output 1 */ +#define AT91C_PB29_PWM2 ( ( unsigned int ) AT91C_PIO_PB29 ) /* PWM Channel 2 */ +#define AT91C_PIO_PB3 ( ( unsigned int ) 1 << 3 ) /* Pin Controlled by PB3 */ +#define AT91C_PB3_ETX1 ( ( unsigned int ) AT91C_PIO_PB3 ) /* Ethernet MAC Transmit Data 1 */ +#define AT91C_PIO_PB30 ( ( unsigned int ) 1 << 30 ) /* Pin Controlled by PB30 */ +#define AT91C_PB30_PCK2 ( ( unsigned int ) AT91C_PIO_PB30 ) /* PMC Programmable Clock Output 2 */ +#define AT91C_PB30_PWM3 ( ( unsigned int ) AT91C_PIO_PB30 ) /* PWM Channel 3 */ +#define AT91C_PIO_PB4 ( ( unsigned int ) 1 << 4 ) /* Pin Controlled by PB4 */ +#define AT91C_PB4_ECRS_ECRSDV ( ( unsigned int ) AT91C_PIO_PB4 ) /* Ethernet MAC Carrier Sense/Carrier Sense and Data Valid */ +#define AT91C_PIO_PB5 ( ( unsigned int ) 1 << 5 ) /* Pin Controlled by PB5 */ +#define AT91C_PB5_ERX0 ( ( unsigned int ) AT91C_PIO_PB5 ) /* Ethernet MAC Receive Data 0 */ +#define AT91C_PIO_PB6 ( ( unsigned int ) 1 << 6 ) /* Pin Controlled by PB6 */ +#define AT91C_PB6_ERX1 ( ( unsigned int ) AT91C_PIO_PB6 ) /* Ethernet MAC Receive Data 1 */ +#define AT91C_PIO_PB7 ( ( unsigned int ) 1 << 7 ) /* Pin Controlled by PB7 */ +#define AT91C_PB7_ERXER ( ( unsigned int ) AT91C_PIO_PB7 ) /* Ethernet MAC Receive Error */ +#define AT91C_PIO_PB8 ( ( unsigned int ) 1 << 8 ) /* Pin Controlled by PB8 */ +#define AT91C_PB8_EMDC ( ( unsigned int ) AT91C_PIO_PB8 ) /* Ethernet MAC Management Data Clock */ +#define AT91C_PIO_PB9 ( ( unsigned int ) 1 << 9 ) /* Pin Controlled by PB9 */ +#define AT91C_PB9_EMDIO ( ( unsigned int ) AT91C_PIO_PB9 ) /* Ethernet MAC Management Data Input/Output */ + +/* ***************************************************************************** */ +/* PERIPHERAL ID DEFINITIONS FOR AT91SAM7X256 */ +/* ***************************************************************************** */ +#define AT91C_ID_FIQ ( ( unsigned int ) 0 ) /* Advanced Interrupt Controller (FIQ) */ +#define AT91C_ID_SYS ( ( unsigned int ) 1 ) /* System Peripheral */ +#define AT91C_ID_PIOA ( ( unsigned int ) 2 ) /* Parallel IO Controller A */ +#define AT91C_ID_PIOB ( ( unsigned int ) 3 ) /* Parallel IO Controller B */ +#define AT91C_ID_SPI0 ( ( unsigned int ) 4 ) /* Serial Peripheral Interface 0 */ +#define AT91C_ID_SPI1 ( ( unsigned int ) 5 ) /* Serial Peripheral Interface 1 */ +#define AT91C_ID_US0 ( ( unsigned int ) 6 ) /* USART 0 */ +#define AT91C_ID_US1 ( ( unsigned int ) 7 ) /* USART 1 */ +#define AT91C_ID_SSC ( ( unsigned int ) 8 ) /* Serial Synchronous Controller */ +#define AT91C_ID_TWI ( ( unsigned int ) 9 ) /* Two-Wire Interface */ +#define AT91C_ID_PWMC ( ( unsigned int ) 10 ) /* PWM Controller */ +#define AT91C_ID_UDP ( ( unsigned int ) 11 ) /* USB Device Port */ +#define AT91C_ID_TC0 ( ( unsigned int ) 12 ) /* Timer Counter 0 */ +#define AT91C_ID_TC1 ( ( unsigned int ) 13 ) /* Timer Counter 1 */ +#define AT91C_ID_TC2 ( ( unsigned int ) 14 ) /* Timer Counter 2 */ +#define AT91C_ID_CAN ( ( unsigned int ) 15 ) /* Control Area Network Controller */ +#define AT91C_ID_EMAC ( ( unsigned int ) 16 ) /* Ethernet MAC */ +#define AT91C_ID_ADC ( ( unsigned int ) 17 ) /* Analog-to-Digital Converter */ +#define AT91C_ID_AES ( ( unsigned int ) 18 ) /* Advanced Encryption Standard 128-bit */ +#define AT91C_ID_TDES ( ( unsigned int ) 19 ) /* Triple Data Encryption Standard */ +#define AT91C_ID_20_Reserved ( ( unsigned int ) 20 ) /* Reserved */ +#define AT91C_ID_21_Reserved ( ( unsigned int ) 21 ) /* Reserved */ +#define AT91C_ID_22_Reserved ( ( unsigned int ) 22 ) /* Reserved */ +#define AT91C_ID_23_Reserved ( ( unsigned int ) 23 ) /* Reserved */ +#define AT91C_ID_24_Reserved ( ( unsigned int ) 24 ) /* Reserved */ +#define AT91C_ID_25_Reserved ( ( unsigned int ) 25 ) /* Reserved */ +#define AT91C_ID_26_Reserved ( ( unsigned int ) 26 ) /* Reserved */ +#define AT91C_ID_27_Reserved ( ( unsigned int ) 27 ) /* Reserved */ +#define AT91C_ID_28_Reserved ( ( unsigned int ) 28 ) /* Reserved */ +#define AT91C_ID_29_Reserved ( ( unsigned int ) 29 ) /* Reserved */ +#define AT91C_ID_IRQ0 ( ( unsigned int ) 30 ) /* Advanced Interrupt Controller (IRQ0) */ +#define AT91C_ID_IRQ1 ( ( unsigned int ) 31 ) /* Advanced Interrupt Controller (IRQ1) */ + +/* ***************************************************************************** */ +/* BASE ADDRESS DEFINITIONS FOR AT91SAM7X256 */ +/* ***************************************************************************** */ +#define AT91C_BASE_SYS ( ( AT91PS_SYS ) 0xFFFFF000 ) /* (SYS) Base Address */ +#define AT91C_BASE_AIC ( ( AT91PS_AIC ) 0xFFFFF000 ) /* (AIC) Base Address */ +#define AT91C_BASE_PDC_DBGU ( ( AT91PS_PDC ) 0xFFFFF300 ) /* (PDC_DBGU) Base Address */ +#define AT91C_BASE_DBGU ( ( AT91PS_DBGU ) 0xFFFFF200 ) /* (DBGU) Base Address */ +#define AT91C_BASE_PIOA ( ( AT91PS_PIO ) 0xFFFFF400 ) /* (PIOA) Base Address */ +#define AT91C_BASE_PIOB ( ( AT91PS_PIO ) 0xFFFFF600 ) /* (PIOB) Base Address */ +#define AT91C_BASE_CKGR ( ( AT91PS_CKGR ) 0xFFFFFC20 ) /* (CKGR) Base Address */ +#define AT91C_BASE_PMC ( ( AT91PS_PMC ) 0xFFFFFC00 ) /* (PMC) Base Address */ +#define AT91C_BASE_RSTC ( ( AT91PS_RSTC ) 0xFFFFFD00 ) /* (RSTC) Base Address */ +#define AT91C_BASE_RTTC ( ( AT91PS_RTTC ) 0xFFFFFD20 ) /* (RTTC) Base Address */ +#define AT91C_BASE_PITC ( ( AT91PS_PITC ) 0xFFFFFD30 ) /* (PITC) Base Address */ +#define AT91C_BASE_WDTC ( ( AT91PS_WDTC ) 0xFFFFFD40 ) /* (WDTC) Base Address */ +#define AT91C_BASE_VREG ( ( AT91PS_VREG ) 0xFFFFFD60 ) /* (VREG) Base Address */ +#define AT91C_BASE_MC ( ( AT91PS_MC ) 0xFFFFFF00 ) /* (MC) Base Address */ +#define AT91C_BASE_PDC_SPI1 ( ( AT91PS_PDC ) 0xFFFE4100 ) /* (PDC_SPI1) Base Address */ +#define AT91C_BASE_SPI1 ( ( AT91PS_SPI ) 0xFFFE4000 ) /* (SPI1) Base Address */ +#define AT91C_BASE_PDC_SPI0 ( ( AT91PS_PDC ) 0xFFFE0100 ) /* (PDC_SPI0) Base Address */ +#define AT91C_BASE_SPI0 ( ( AT91PS_SPI ) 0xFFFE0000 ) /* (SPI0) Base Address */ +#define AT91C_BASE_PDC_US1 ( ( AT91PS_PDC ) 0xFFFC4100 ) /* (PDC_US1) Base Address */ +#define AT91C_BASE_US1 ( ( AT91PS_USART ) 0xFFFC4000 ) /* (US1) Base Address */ +#define AT91C_BASE_PDC_US0 ( ( AT91PS_PDC ) 0xFFFC0100 ) /* (PDC_US0) Base Address */ +#define AT91C_BASE_US0 ( ( AT91PS_USART ) 0xFFFC0000 ) /* (US0) Base Address */ +#define AT91C_BASE_PDC_SSC ( ( AT91PS_PDC ) 0xFFFD4100 ) /* (PDC_SSC) Base Address */ +#define AT91C_BASE_SSC ( ( AT91PS_SSC ) 0xFFFD4000 ) /* (SSC) Base Address */ +#define AT91C_BASE_TWI ( ( AT91PS_TWI ) 0xFFFB8000 ) /* (TWI) Base Address */ +#define AT91C_BASE_PWMC_CH3 ( ( AT91PS_PWMC_CH ) 0xFFFCC260 ) /* (PWMC_CH3) Base Address */ +#define AT91C_BASE_PWMC_CH2 ( ( AT91PS_PWMC_CH ) 0xFFFCC240 ) /* (PWMC_CH2) Base Address */ +#define AT91C_BASE_PWMC_CH1 ( ( AT91PS_PWMC_CH ) 0xFFFCC220 ) /* (PWMC_CH1) Base Address */ +#define AT91C_BASE_PWMC_CH0 ( ( AT91PS_PWMC_CH ) 0xFFFCC200 ) /* (PWMC_CH0) Base Address */ +#define AT91C_BASE_PWMC ( ( AT91PS_PWMC ) 0xFFFCC000 ) /* (PWMC) Base Address */ +#define AT91C_BASE_UDP ( ( AT91PS_UDP ) 0xFFFB0000 ) /* (UDP) Base Address */ +#define AT91C_BASE_TC0 ( ( AT91PS_TC ) 0xFFFA0000 ) /* (TC0) Base Address */ +#define AT91C_BASE_TC1 ( ( AT91PS_TC ) 0xFFFA0040 ) /* (TC1) Base Address */ +#define AT91C_BASE_TC2 ( ( AT91PS_TC ) 0xFFFA0080 ) /* (TC2) Base Address */ +#define AT91C_BASE_TCB ( ( AT91PS_TCB ) 0xFFFA0000 ) /* (TCB) Base Address */ +#define AT91C_BASE_CAN_MB0 ( ( AT91PS_CAN_MB ) 0xFFFD0200 ) /* (CAN_MB0) Base Address */ +#define AT91C_BASE_CAN_MB1 ( ( AT91PS_CAN_MB ) 0xFFFD0220 ) /* (CAN_MB1) Base Address */ +#define AT91C_BASE_CAN_MB2 ( ( AT91PS_CAN_MB ) 0xFFFD0240 ) /* (CAN_MB2) Base Address */ +#define AT91C_BASE_CAN_MB3 ( ( AT91PS_CAN_MB ) 0xFFFD0260 ) /* (CAN_MB3) Base Address */ +#define AT91C_BASE_CAN_MB4 ( ( AT91PS_CAN_MB ) 0xFFFD0280 ) /* (CAN_MB4) Base Address */ +#define AT91C_BASE_CAN_MB5 ( ( AT91PS_CAN_MB ) 0xFFFD02A0 ) /* (CAN_MB5) Base Address */ +#define AT91C_BASE_CAN_MB6 ( ( AT91PS_CAN_MB ) 0xFFFD02C0 ) /* (CAN_MB6) Base Address */ +#define AT91C_BASE_CAN_MB7 ( ( AT91PS_CAN_MB ) 0xFFFD02E0 ) /* (CAN_MB7) Base Address */ +#define AT91C_BASE_CAN ( ( AT91PS_CAN ) 0xFFFD0000 ) /* (CAN) Base Address */ +#define AT91C_BASE_EMAC ( ( AT91PS_EMAC ) 0xFFFDC000 ) /* (EMAC) Base Address */ +#define AT91C_BASE_PDC_ADC ( ( AT91PS_PDC ) 0xFFFD8100 ) /* (PDC_ADC) Base Address */ +#define AT91C_BASE_ADC ( ( AT91PS_ADC ) 0xFFFD8000 ) /* (ADC) Base Address */ +#define AT91C_BASE_PDC_AES ( ( AT91PS_PDC ) 0xFFFA4100 ) /* (PDC_AES) Base Address */ +#define AT91C_BASE_AES ( ( AT91PS_AES ) 0xFFFA4000 ) /* (AES) Base Address */ +#define AT91C_BASE_PDC_TDES ( ( AT91PS_PDC ) 0xFFFA8100 ) /* (PDC_TDES) Base Address */ +#define AT91C_BASE_TDES ( ( AT91PS_TDES ) 0xFFFA8000 ) /* (TDES) Base Address */ + +/* ***************************************************************************** */ +/* MEMORY MAPPING DEFINITIONS FOR AT91SAM7X256 */ +/* ***************************************************************************** */ +#define AT91C_ISRAM ( ( char * ) 0x00200000 ) /* Internal SRAM base address */ +#define AT91C_ISRAM_SIZE ( ( unsigned int ) 0x00010000 ) /* Internal SRAM size in byte (64 Kbyte) */ +#define AT91C_IFLASH ( ( char * ) 0x00100000 ) /* Internal ROM base address */ +#define AT91C_IFLASH_SIZE ( ( unsigned int ) 0x00040000 ) /* Internal ROM size in byte (256 Kbyte) */ + +#define AT91F_AIC_ConfigureIt( irq_id, priority, src_type, newHandler ) \ + { \ + unsigned int mask; \ + \ + mask = 0x1 << irq_id; \ + /* Disable the interrupt on the interrupt controller */ \ + AT91C_BASE_AIC->AIC_IDCR = mask; \ + /* Save the interrupt handler routine pointer and the interrupt priority */ \ + AT91C_BASE_AIC->AIC_SVR[ irq_id ] = ( unsigned int ) newHandler; \ + /* Store the Source Mode Register */ \ + AT91C_BASE_AIC->AIC_SMR[ irq_id ] = src_type | priority; \ + /* Clear the interrupt on the interrupt controller */ \ + AT91C_BASE_AIC->AIC_ICCR = mask; \ + } + + +#endif /* ifndef AT91SAM7X256_H */ diff --git a/Source/portable/GCC/ARM7_AT91SAM7S/ioat91sam7x256.h b/Source/portable/GCC/ARM7_AT91SAM7S/ioat91sam7x256.h index d4c43e8f3..a680c4861 100644 --- a/Source/portable/GCC/ARM7_AT91SAM7S/ioat91sam7x256.h +++ b/Source/portable/GCC/ARM7_AT91SAM7S/ioat91sam7x256.h @@ -1,4697 +1,6372 @@ -// - ---------------------------------------------------------------------------- -// - ATMEL Microcontroller Software Support - ROUSSET - -// - ---------------------------------------------------------------------------- -// - DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR -// - IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF -// - MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE -// - DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, -// - INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// - LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, -// - OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF -// - LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING -// - NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, -// - EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// - ---------------------------------------------------------------------------- -// - File Name : AT91SAM7X256.h -// - Object : AT91SAM7X256 definitions -// - Generated : AT91 SW Application Group 05/20/2005 (16:22:29) -// - -// - CVS Reference : /AT91SAM7X256.pl/1.11/Tue May 10 12:15:32 2005// -// - CVS Reference : /SYS_SAM7X.pl/1.3/Tue Feb 1 17:01:43 2005// -// - CVS Reference : /MC_SAM7X.pl/1.2/Fri May 20 14:13:04 2005// -// - CVS Reference : /PMC_SAM7X.pl/1.4/Tue Feb 8 13:58:10 2005// -// - CVS Reference : /RSTC_SAM7X.pl/1.1/Tue Feb 1 16:16:26 2005// -// - CVS Reference : /UDP_SAM7X.pl/1.1/Tue May 10 11:35:35 2005// -// - CVS Reference : /PWM_SAM7X.pl/1.1/Tue May 10 11:53:07 2005// -// - CVS Reference : /AIC_6075B.pl/1.3/Fri May 20 14:01:30 2005// -// - CVS Reference : /PIO_6057A.pl/1.2/Thu Feb 3 10:18:28 2005// -// - CVS Reference : /RTTC_6081A.pl/1.2/Tue Nov 9 14:43:58 2004// -// - CVS Reference : /PITC_6079A.pl/1.2/Tue Nov 9 14:43:56 2004// -// - CVS Reference : /WDTC_6080A.pl/1.3/Tue Nov 9 14:44:00 2004// -// - CVS Reference : /VREG_6085B.pl/1.1/Tue Feb 1 16:05:48 2005// -// - CVS Reference : /PDC_6074C.pl/1.2/Thu Feb 3 08:48:54 2005// -// - CVS Reference : /DBGU_6059D.pl/1.1/Mon Jan 31 13:15:32 2005// -// - CVS Reference : /SPI_6088D.pl/1.3/Fri May 20 14:08:59 2005// -// - CVS Reference : /US_6089C.pl/1.1/Mon Jul 12 18:23:26 2004// -// - CVS Reference : /SSC_6078A.pl/1.1/Tue Jul 13 07:45:40 2004// -// - CVS Reference : /TWI_6061A.pl/1.1/Tue Jul 13 07:38:06 2004// -// - CVS Reference : /TC_6082A.pl/1.7/Fri Mar 11 12:52:17 2005// -// - CVS Reference : /CAN_6019B.pl/1.1/Tue Mar 8 12:42:22 2005// -// - CVS Reference : /EMACB_6119A.pl/1.5/Thu Feb 3 15:52:04 2005// -// - CVS Reference : /ADC_6051C.pl/1.1/Fri Oct 17 09:12:38 2003// -// - CVS Reference : /AES_6149A.pl/1.10/Mon Feb 7 09:44:25 2005// -// - CVS Reference : /DES3_6150A.pl/1.1/Mon Jan 17 08:34:31 2005// -// - ---------------------------------------------------------------------------- +/* - ---------------------------------------------------------------------------- */ +/* - ATMEL Microcontroller Software Support - ROUSSET - */ +/* - ---------------------------------------------------------------------------- */ +/* - DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* - IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* - MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* - DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* - INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* - LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* - OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* - LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* - NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* - EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* - ---------------------------------------------------------------------------- */ +/* - File Name : AT91SAM7X256.h */ +/* - Object : AT91SAM7X256 definitions */ +/* - Generated : AT91 SW Application Group 05/20/2005 (16:22:29) */ +/* - */ +/* - CVS Reference : /AT91SAM7X256.pl/1.11/Tue May 10 12:15:32 2005// */ +/* - CVS Reference : /SYS_SAM7X.pl/1.3/Tue Feb 1 17:01:43 2005// */ +/* - CVS Reference : /MC_SAM7X.pl/1.2/Fri May 20 14:13:04 2005// */ +/* - CVS Reference : /PMC_SAM7X.pl/1.4/Tue Feb 8 13:58:10 2005// */ +/* - CVS Reference : /RSTC_SAM7X.pl/1.1/Tue Feb 1 16:16:26 2005// */ +/* - CVS Reference : /UDP_SAM7X.pl/1.1/Tue May 10 11:35:35 2005// */ +/* - CVS Reference : /PWM_SAM7X.pl/1.1/Tue May 10 11:53:07 2005// */ +/* - CVS Reference : /AIC_6075B.pl/1.3/Fri May 20 14:01:30 2005// */ +/* - CVS Reference : /PIO_6057A.pl/1.2/Thu Feb 3 10:18:28 2005// */ +/* - CVS Reference : /RTTC_6081A.pl/1.2/Tue Nov 9 14:43:58 2004// */ +/* - CVS Reference : /PITC_6079A.pl/1.2/Tue Nov 9 14:43:56 2004// */ +/* - CVS Reference : /WDTC_6080A.pl/1.3/Tue Nov 9 14:44:00 2004// */ +/* - CVS Reference : /VREG_6085B.pl/1.1/Tue Feb 1 16:05:48 2005// */ +/* - CVS Reference : /PDC_6074C.pl/1.2/Thu Feb 3 08:48:54 2005// */ +/* - CVS Reference : /DBGU_6059D.pl/1.1/Mon Jan 31 13:15:32 2005// */ +/* - CVS Reference : /SPI_6088D.pl/1.3/Fri May 20 14:08:59 2005// */ +/* - CVS Reference : /US_6089C.pl/1.1/Mon Jul 12 18:23:26 2004// */ +/* - CVS Reference : /SSC_6078A.pl/1.1/Tue Jul 13 07:45:40 2004// */ +/* - CVS Reference : /TWI_6061A.pl/1.1/Tue Jul 13 07:38:06 2004// */ +/* - CVS Reference : /TC_6082A.pl/1.7/Fri Mar 11 12:52:17 2005// */ +/* - CVS Reference : /CAN_6019B.pl/1.1/Tue Mar 8 12:42:22 2005// */ +/* - CVS Reference : /EMACB_6119A.pl/1.5/Thu Feb 3 15:52:04 2005// */ +/* - CVS Reference : /ADC_6051C.pl/1.1/Fri Oct 17 09:12:38 2003// */ +/* - CVS Reference : /AES_6149A.pl/1.10/Mon Feb 7 09:44:25 2005// */ +/* - CVS Reference : /DES3_6150A.pl/1.1/Mon Jan 17 08:34:31 2005// */ +/* - ---------------------------------------------------------------------------- */ #ifndef AT91SAM7X256_H #define AT91SAM7X256_H -typedef volatile unsigned int AT91_REG;// Hardware register definition +typedef volatile unsigned int AT91_REG; /* Hardware register definition */ -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR System Peripherals -// ***************************************************************************** -typedef struct _AT91S_SYS { - AT91_REG AIC_SMR[32]; // Source Mode Register - AT91_REG AIC_SVR[32]; // Source Vector Register - AT91_REG AIC_IVR; // IRQ Vector Register - AT91_REG AIC_FVR; // FIQ Vector Register - AT91_REG AIC_ISR; // Interrupt Status Register - AT91_REG AIC_IPR; // Interrupt Pending Register - AT91_REG AIC_IMR; // Interrupt Mask Register - AT91_REG AIC_CISR; // Core Interrupt Status Register - AT91_REG Reserved0[2]; // - AT91_REG AIC_IECR; // Interrupt Enable Command Register - AT91_REG AIC_IDCR; // Interrupt Disable Command Register - AT91_REG AIC_ICCR; // Interrupt Clear Command Register - AT91_REG AIC_ISCR; // Interrupt Set Command Register - AT91_REG AIC_EOICR; // End of Interrupt Command Register - AT91_REG AIC_SPU; // Spurious Vector Register - AT91_REG AIC_DCR; // Debug Control Register (Protect) - AT91_REG Reserved1[1]; // - AT91_REG AIC_FFER; // Fast Forcing Enable Register - AT91_REG AIC_FFDR; // Fast Forcing Disable Register - AT91_REG AIC_FFSR; // Fast Forcing Status Register - AT91_REG Reserved2[45]; // - AT91_REG DBGU_CR; // Control Register - AT91_REG DBGU_MR; // Mode Register - AT91_REG DBGU_IER; // Interrupt Enable Register - AT91_REG DBGU_IDR; // Interrupt Disable Register - AT91_REG DBGU_IMR; // Interrupt Mask Register - AT91_REG DBGU_CSR; // Channel Status Register - AT91_REG DBGU_RHR; // Receiver Holding Register - AT91_REG DBGU_THR; // Transmitter Holding Register - AT91_REG DBGU_BRGR; // Baud Rate Generator Register - AT91_REG Reserved3[7]; // - AT91_REG DBGU_CIDR; // Chip ID Register - AT91_REG DBGU_EXID; // Chip ID Extension Register - AT91_REG DBGU_FNTR; // Force NTRST Register - AT91_REG Reserved4[45]; // - AT91_REG DBGU_RPR; // Receive Pointer Register - AT91_REG DBGU_RCR; // Receive Counter Register - AT91_REG DBGU_TPR; // Transmit Pointer Register - AT91_REG DBGU_TCR; // Transmit Counter Register - AT91_REG DBGU_RNPR; // Receive Next Pointer Register - AT91_REG DBGU_RNCR; // Receive Next Counter Register - AT91_REG DBGU_TNPR; // Transmit Next Pointer Register - AT91_REG DBGU_TNCR; // Transmit Next Counter Register - AT91_REG DBGU_PTCR; // PDC Transfer Control Register - AT91_REG DBGU_PTSR; // PDC Transfer Status Register - AT91_REG Reserved5[54]; // - AT91_REG PIOA_PER; // PIO Enable Register - AT91_REG PIOA_PDR; // PIO Disable Register - AT91_REG PIOA_PSR; // PIO Status Register - AT91_REG Reserved6[1]; // - AT91_REG PIOA_OER; // Output Enable Register - AT91_REG PIOA_ODR; // Output Disable Registerr - AT91_REG PIOA_OSR; // Output Status Register - AT91_REG Reserved7[1]; // - AT91_REG PIOA_IFER; // Input Filter Enable Register - AT91_REG PIOA_IFDR; // Input Filter Disable Register - AT91_REG PIOA_IFSR; // Input Filter Status Register - AT91_REG Reserved8[1]; // - AT91_REG PIOA_SODR; // Set Output Data Register - AT91_REG PIOA_CODR; // Clear Output Data Register - AT91_REG PIOA_ODSR; // Output Data Status Register - AT91_REG PIOA_PDSR; // Pin Data Status Register - AT91_REG PIOA_IER; // Interrupt Enable Register - AT91_REG PIOA_IDR; // Interrupt Disable Register - AT91_REG PIOA_IMR; // Interrupt Mask Register - AT91_REG PIOA_ISR; // Interrupt Status Register - AT91_REG PIOA_MDER; // Multi-driver Enable Register - AT91_REG PIOA_MDDR; // Multi-driver Disable Register - AT91_REG PIOA_MDSR; // Multi-driver Status Register - AT91_REG Reserved9[1]; // - AT91_REG PIOA_PPUDR; // Pull-up Disable Register - AT91_REG PIOA_PPUER; // Pull-up Enable Register - AT91_REG PIOA_PPUSR; // Pull-up Status Register - AT91_REG Reserved10[1]; // - AT91_REG PIOA_ASR; // Select A Register - AT91_REG PIOA_BSR; // Select B Register - AT91_REG PIOA_ABSR; // AB Select Status Register - AT91_REG Reserved11[9]; // - AT91_REG PIOA_OWER; // Output Write Enable Register - AT91_REG PIOA_OWDR; // Output Write Disable Register - AT91_REG PIOA_OWSR; // Output Write Status Register - AT91_REG Reserved12[85]; // - AT91_REG PIOB_PER; // PIO Enable Register - AT91_REG PIOB_PDR; // PIO Disable Register - AT91_REG PIOB_PSR; // PIO Status Register - AT91_REG Reserved13[1]; // - AT91_REG PIOB_OER; // Output Enable Register - AT91_REG PIOB_ODR; // Output Disable Registerr - AT91_REG PIOB_OSR; // Output Status Register - AT91_REG Reserved14[1]; // - AT91_REG PIOB_IFER; // Input Filter Enable Register - AT91_REG PIOB_IFDR; // Input Filter Disable Register - AT91_REG PIOB_IFSR; // Input Filter Status Register - AT91_REG Reserved15[1]; // - AT91_REG PIOB_SODR; // Set Output Data Register - AT91_REG PIOB_CODR; // Clear Output Data Register - AT91_REG PIOB_ODSR; // Output Data Status Register - AT91_REG PIOB_PDSR; // Pin Data Status Register - AT91_REG PIOB_IER; // Interrupt Enable Register - AT91_REG PIOB_IDR; // Interrupt Disable Register - AT91_REG PIOB_IMR; // Interrupt Mask Register - AT91_REG PIOB_ISR; // Interrupt Status Register - AT91_REG PIOB_MDER; // Multi-driver Enable Register - AT91_REG PIOB_MDDR; // Multi-driver Disable Register - AT91_REG PIOB_MDSR; // Multi-driver Status Register - AT91_REG Reserved16[1]; // - AT91_REG PIOB_PPUDR; // Pull-up Disable Register - AT91_REG PIOB_PPUER; // Pull-up Enable Register - AT91_REG PIOB_PPUSR; // Pull-up Status Register - AT91_REG Reserved17[1]; // - AT91_REG PIOB_ASR; // Select A Register - AT91_REG PIOB_BSR; // Select B Register - AT91_REG PIOB_ABSR; // AB Select Status Register - AT91_REG Reserved18[9]; // - AT91_REG PIOB_OWER; // Output Write Enable Register - AT91_REG PIOB_OWDR; // Output Write Disable Register - AT91_REG PIOB_OWSR; // Output Write Status Register - AT91_REG Reserved19[341]; // - AT91_REG PMC_SCER; // System Clock Enable Register - AT91_REG PMC_SCDR; // System Clock Disable Register - AT91_REG PMC_SCSR; // System Clock Status Register - AT91_REG Reserved20[1]; // - AT91_REG PMC_PCER; // Peripheral Clock Enable Register - AT91_REG PMC_PCDR; // Peripheral Clock Disable Register - AT91_REG PMC_PCSR; // Peripheral Clock Status Register - AT91_REG Reserved21[1]; // - AT91_REG PMC_MOR; // Main Oscillator Register - AT91_REG PMC_MCFR; // Main Clock Frequency Register - AT91_REG Reserved22[1]; // - AT91_REG PMC_PLLR; // PLL Register - AT91_REG PMC_MCKR; // Master Clock Register - AT91_REG Reserved23[3]; // - AT91_REG PMC_PCKR[4]; // Programmable Clock Register - AT91_REG Reserved24[4]; // - AT91_REG PMC_IER; // Interrupt Enable Register - AT91_REG PMC_IDR; // Interrupt Disable Register - AT91_REG PMC_SR; // Status Register - AT91_REG PMC_IMR; // Interrupt Mask Register - AT91_REG Reserved25[36]; // - AT91_REG RSTC_RCR; // Reset Control Register - AT91_REG RSTC_RSR; // Reset Status Register - AT91_REG RSTC_RMR; // Reset Mode Register - AT91_REG Reserved26[5]; // - AT91_REG RTTC_RTMR; // Real-time Mode Register - AT91_REG RTTC_RTAR; // Real-time Alarm Register - AT91_REG RTTC_RTVR; // Real-time Value Register - AT91_REG RTTC_RTSR; // Real-time Status Register - AT91_REG PITC_PIMR; // Period Interval Mode Register - AT91_REG PITC_PISR; // Period Interval Status Register - AT91_REG PITC_PIVR; // Period Interval Value Register - AT91_REG PITC_PIIR; // Period Interval Image Register - AT91_REG WDTC_WDCR; // Watchdog Control Register - AT91_REG WDTC_WDMR; // Watchdog Mode Register - AT91_REG WDTC_WDSR; // Watchdog Status Register - AT91_REG Reserved27[5]; // - AT91_REG VREG_MR; // Voltage Regulator Mode Register -} AT91S_SYS, *AT91PS_SYS; +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR System Peripherals */ +/* ***************************************************************************** */ +typedef struct _AT91S_SYS +{ + AT91_REG AIC_SMR[ 32 ]; /* Source Mode Register */ + AT91_REG AIC_SVR[ 32 ]; /* Source Vector Register */ + AT91_REG AIC_IVR; /* IRQ Vector Register */ + AT91_REG AIC_FVR; /* FIQ Vector Register */ + AT91_REG AIC_ISR; /* Interrupt Status Register */ + AT91_REG AIC_IPR; /* Interrupt Pending Register */ + AT91_REG AIC_IMR; /* Interrupt Mask Register */ + AT91_REG AIC_CISR; /* Core Interrupt Status Register */ + AT91_REG Reserved0[ 2 ]; /* */ + AT91_REG AIC_IECR; /* Interrupt Enable Command Register */ + AT91_REG AIC_IDCR; /* Interrupt Disable Command Register */ + AT91_REG AIC_ICCR; /* Interrupt Clear Command Register */ + AT91_REG AIC_ISCR; /* Interrupt Set Command Register */ + AT91_REG AIC_EOICR; /* End of Interrupt Command Register */ + AT91_REG AIC_SPU; /* Spurious Vector Register */ + AT91_REG AIC_DCR; /* Debug Control Register (Protect) */ + AT91_REG Reserved1[ 1 ]; /* */ + AT91_REG AIC_FFER; /* Fast Forcing Enable Register */ + AT91_REG AIC_FFDR; /* Fast Forcing Disable Register */ + AT91_REG AIC_FFSR; /* Fast Forcing Status Register */ + AT91_REG Reserved2[ 45 ]; /* */ + AT91_REG DBGU_CR; /* Control Register */ + AT91_REG DBGU_MR; /* Mode Register */ + AT91_REG DBGU_IER; /* Interrupt Enable Register */ + AT91_REG DBGU_IDR; /* Interrupt Disable Register */ + AT91_REG DBGU_IMR; /* Interrupt Mask Register */ + AT91_REG DBGU_CSR; /* Channel Status Register */ + AT91_REG DBGU_RHR; /* Receiver Holding Register */ + AT91_REG DBGU_THR; /* Transmitter Holding Register */ + AT91_REG DBGU_BRGR; /* Baud Rate Generator Register */ + AT91_REG Reserved3[ 7 ]; /* */ + AT91_REG DBGU_CIDR; /* Chip ID Register */ + AT91_REG DBGU_EXID; /* Chip ID Extension Register */ + AT91_REG DBGU_FNTR; /* Force NTRST Register */ + AT91_REG Reserved4[ 45 ]; /* */ + AT91_REG DBGU_RPR; /* Receive Pointer Register */ + AT91_REG DBGU_RCR; /* Receive Counter Register */ + AT91_REG DBGU_TPR; /* Transmit Pointer Register */ + AT91_REG DBGU_TCR; /* Transmit Counter Register */ + AT91_REG DBGU_RNPR; /* Receive Next Pointer Register */ + AT91_REG DBGU_RNCR; /* Receive Next Counter Register */ + AT91_REG DBGU_TNPR; /* Transmit Next Pointer Register */ + AT91_REG DBGU_TNCR; /* Transmit Next Counter Register */ + AT91_REG DBGU_PTCR; /* PDC Transfer Control Register */ + AT91_REG DBGU_PTSR; /* PDC Transfer Status Register */ + AT91_REG Reserved5[ 54 ]; /* */ + AT91_REG PIOA_PER; /* PIO Enable Register */ + AT91_REG PIOA_PDR; /* PIO Disable Register */ + AT91_REG PIOA_PSR; /* PIO Status Register */ + AT91_REG Reserved6[ 1 ]; /* */ + AT91_REG PIOA_OER; /* Output Enable Register */ + AT91_REG PIOA_ODR; /* Output Disable Registerr */ + AT91_REG PIOA_OSR; /* Output Status Register */ + AT91_REG Reserved7[ 1 ]; /* */ + AT91_REG PIOA_IFER; /* Input Filter Enable Register */ + AT91_REG PIOA_IFDR; /* Input Filter Disable Register */ + AT91_REG PIOA_IFSR; /* Input Filter Status Register */ + AT91_REG Reserved8[ 1 ]; /* */ + AT91_REG PIOA_SODR; /* Set Output Data Register */ + AT91_REG PIOA_CODR; /* Clear Output Data Register */ + AT91_REG PIOA_ODSR; /* Output Data Status Register */ + AT91_REG PIOA_PDSR; /* Pin Data Status Register */ + AT91_REG PIOA_IER; /* Interrupt Enable Register */ + AT91_REG PIOA_IDR; /* Interrupt Disable Register */ + AT91_REG PIOA_IMR; /* Interrupt Mask Register */ + AT91_REG PIOA_ISR; /* Interrupt Status Register */ + AT91_REG PIOA_MDER; /* Multi-driver Enable Register */ + AT91_REG PIOA_MDDR; /* Multi-driver Disable Register */ + AT91_REG PIOA_MDSR; /* Multi-driver Status Register */ + AT91_REG Reserved9[ 1 ]; /* */ + AT91_REG PIOA_PPUDR; /* Pull-up Disable Register */ + AT91_REG PIOA_PPUER; /* Pull-up Enable Register */ + AT91_REG PIOA_PPUSR; /* Pull-up Status Register */ + AT91_REG Reserved10[ 1 ]; /* */ + AT91_REG PIOA_ASR; /* Select A Register */ + AT91_REG PIOA_BSR; /* Select B Register */ + AT91_REG PIOA_ABSR; /* AB Select Status Register */ + AT91_REG Reserved11[ 9 ]; /* */ + AT91_REG PIOA_OWER; /* Output Write Enable Register */ + AT91_REG PIOA_OWDR; /* Output Write Disable Register */ + AT91_REG PIOA_OWSR; /* Output Write Status Register */ + AT91_REG Reserved12[ 85 ]; /* */ + AT91_REG PIOB_PER; /* PIO Enable Register */ + AT91_REG PIOB_PDR; /* PIO Disable Register */ + AT91_REG PIOB_PSR; /* PIO Status Register */ + AT91_REG Reserved13[ 1 ]; /* */ + AT91_REG PIOB_OER; /* Output Enable Register */ + AT91_REG PIOB_ODR; /* Output Disable Registerr */ + AT91_REG PIOB_OSR; /* Output Status Register */ + AT91_REG Reserved14[ 1 ]; /* */ + AT91_REG PIOB_IFER; /* Input Filter Enable Register */ + AT91_REG PIOB_IFDR; /* Input Filter Disable Register */ + AT91_REG PIOB_IFSR; /* Input Filter Status Register */ + AT91_REG Reserved15[ 1 ]; /* */ + AT91_REG PIOB_SODR; /* Set Output Data Register */ + AT91_REG PIOB_CODR; /* Clear Output Data Register */ + AT91_REG PIOB_ODSR; /* Output Data Status Register */ + AT91_REG PIOB_PDSR; /* Pin Data Status Register */ + AT91_REG PIOB_IER; /* Interrupt Enable Register */ + AT91_REG PIOB_IDR; /* Interrupt Disable Register */ + AT91_REG PIOB_IMR; /* Interrupt Mask Register */ + AT91_REG PIOB_ISR; /* Interrupt Status Register */ + AT91_REG PIOB_MDER; /* Multi-driver Enable Register */ + AT91_REG PIOB_MDDR; /* Multi-driver Disable Register */ + AT91_REG PIOB_MDSR; /* Multi-driver Status Register */ + AT91_REG Reserved16[ 1 ]; /* */ + AT91_REG PIOB_PPUDR; /* Pull-up Disable Register */ + AT91_REG PIOB_PPUER; /* Pull-up Enable Register */ + AT91_REG PIOB_PPUSR; /* Pull-up Status Register */ + AT91_REG Reserved17[ 1 ]; /* */ + AT91_REG PIOB_ASR; /* Select A Register */ + AT91_REG PIOB_BSR; /* Select B Register */ + AT91_REG PIOB_ABSR; /* AB Select Status Register */ + AT91_REG Reserved18[ 9 ]; /* */ + AT91_REG PIOB_OWER; /* Output Write Enable Register */ + AT91_REG PIOB_OWDR; /* Output Write Disable Register */ + AT91_REG PIOB_OWSR; /* Output Write Status Register */ + AT91_REG Reserved19[ 341 ]; /* */ + AT91_REG PMC_SCER; /* System Clock Enable Register */ + AT91_REG PMC_SCDR; /* System Clock Disable Register */ + AT91_REG PMC_SCSR; /* System Clock Status Register */ + AT91_REG Reserved20[ 1 ]; /* */ + AT91_REG PMC_PCER; /* Peripheral Clock Enable Register */ + AT91_REG PMC_PCDR; /* Peripheral Clock Disable Register */ + AT91_REG PMC_PCSR; /* Peripheral Clock Status Register */ + AT91_REG Reserved21[ 1 ]; /* */ + AT91_REG PMC_MOR; /* Main Oscillator Register */ + AT91_REG PMC_MCFR; /* Main Clock Frequency Register */ + AT91_REG Reserved22[ 1 ]; /* */ + AT91_REG PMC_PLLR; /* PLL Register */ + AT91_REG PMC_MCKR; /* Master Clock Register */ + AT91_REG Reserved23[ 3 ]; /* */ + AT91_REG PMC_PCKR[ 4 ]; /* Programmable Clock Register */ + AT91_REG Reserved24[ 4 ]; /* */ + AT91_REG PMC_IER; /* Interrupt Enable Register */ + AT91_REG PMC_IDR; /* Interrupt Disable Register */ + AT91_REG PMC_SR; /* Status Register */ + AT91_REG PMC_IMR; /* Interrupt Mask Register */ + AT91_REG Reserved25[ 36 ]; /* */ + AT91_REG RSTC_RCR; /* Reset Control Register */ + AT91_REG RSTC_RSR; /* Reset Status Register */ + AT91_REG RSTC_RMR; /* Reset Mode Register */ + AT91_REG Reserved26[ 5 ]; /* */ + AT91_REG RTTC_RTMR; /* Real-time Mode Register */ + AT91_REG RTTC_RTAR; /* Real-time Alarm Register */ + AT91_REG RTTC_RTVR; /* Real-time Value Register */ + AT91_REG RTTC_RTSR; /* Real-time Status Register */ + AT91_REG PITC_PIMR; /* Period Interval Mode Register */ + AT91_REG PITC_PISR; /* Period Interval Status Register */ + AT91_REG PITC_PIVR; /* Period Interval Value Register */ + AT91_REG PITC_PIIR; /* Period Interval Image Register */ + AT91_REG WDTC_WDCR; /* Watchdog Control Register */ + AT91_REG WDTC_WDMR; /* Watchdog Mode Register */ + AT91_REG WDTC_WDSR; /* Watchdog Status Register */ + AT91_REG Reserved27[ 5 ]; /* */ + AT91_REG VREG_MR; /* Voltage Regulator Mode Register */ +} AT91S_SYS, * AT91PS_SYS; -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Advanced Interrupt Controller -// ***************************************************************************** -typedef struct _AT91S_AIC { - AT91_REG AIC_SMR[32]; // Source Mode Register - AT91_REG AIC_SVR[32]; // Source Vector Register - AT91_REG AIC_IVR; // IRQ Vector Register - AT91_REG AIC_FVR; // FIQ Vector Register - AT91_REG AIC_ISR; // Interrupt Status Register - AT91_REG AIC_IPR; // Interrupt Pending Register - AT91_REG AIC_IMR; // Interrupt Mask Register - AT91_REG AIC_CISR; // Core Interrupt Status Register - AT91_REG Reserved0[2]; // - AT91_REG AIC_IECR; // Interrupt Enable Command Register - AT91_REG AIC_IDCR; // Interrupt Disable Command Register - AT91_REG AIC_ICCR; // Interrupt Clear Command Register - AT91_REG AIC_ISCR; // Interrupt Set Command Register - AT91_REG AIC_EOICR; // End of Interrupt Command Register - AT91_REG AIC_SPU; // Spurious Vector Register - AT91_REG AIC_DCR; // Debug Control Register (Protect) - AT91_REG Reserved1[1]; // - AT91_REG AIC_FFER; // Fast Forcing Enable Register - AT91_REG AIC_FFDR; // Fast Forcing Disable Register - AT91_REG AIC_FFSR; // Fast Forcing Status Register -} AT91S_AIC, *AT91PS_AIC; +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR Advanced Interrupt Controller */ +/* ***************************************************************************** */ +typedef struct _AT91S_AIC +{ + AT91_REG AIC_SMR[ 32 ]; /* Source Mode Register */ + AT91_REG AIC_SVR[ 32 ]; /* Source Vector Register */ + AT91_REG AIC_IVR; /* IRQ Vector Register */ + AT91_REG AIC_FVR; /* FIQ Vector Register */ + AT91_REG AIC_ISR; /* Interrupt Status Register */ + AT91_REG AIC_IPR; /* Interrupt Pending Register */ + AT91_REG AIC_IMR; /* Interrupt Mask Register */ + AT91_REG AIC_CISR; /* Core Interrupt Status Register */ + AT91_REG Reserved0[ 2 ]; /* */ + AT91_REG AIC_IECR; /* Interrupt Enable Command Register */ + AT91_REG AIC_IDCR; /* Interrupt Disable Command Register */ + AT91_REG AIC_ICCR; /* Interrupt Clear Command Register */ + AT91_REG AIC_ISCR; /* Interrupt Set Command Register */ + AT91_REG AIC_EOICR; /* End of Interrupt Command Register */ + AT91_REG AIC_SPU; /* Spurious Vector Register */ + AT91_REG AIC_DCR; /* Debug Control Register (Protect) */ + AT91_REG Reserved1[ 1 ]; /* */ + AT91_REG AIC_FFER; /* Fast Forcing Enable Register */ + AT91_REG AIC_FFDR; /* Fast Forcing Disable Register */ + AT91_REG AIC_FFSR; /* Fast Forcing Status Register */ +} AT91S_AIC, * AT91PS_AIC; -// -------- AIC_SMR : (AIC Offset: 0x0) Control Register -------- -#define AT91C_AIC_PRIOR ((unsigned int) 0x7 << 0) // (AIC) Priority Level -#define AT91C_AIC_PRIOR_LOWEST ((unsigned int) 0x0) // (AIC) Lowest priority level -#define AT91C_AIC_PRIOR_HIGHEST ((unsigned int) 0x7) // (AIC) Highest priority level -#define AT91C_AIC_SRCTYPE ((unsigned int) 0x3 << 5) // (AIC) Interrupt Source Type -#define AT91C_AIC_SRCTYPE_INT_HIGH_LEVEL ((unsigned int) 0x0 << 5) // (AIC) Internal Sources Code Label High-level Sensitive -#define AT91C_AIC_SRCTYPE_EXT_LOW_LEVEL ((unsigned int) 0x0 << 5) // (AIC) External Sources Code Label Low-level Sensitive -#define AT91C_AIC_SRCTYPE_INT_POSITIVE_EDGE ((unsigned int) 0x1 << 5) // (AIC) Internal Sources Code Label Positive Edge triggered -#define AT91C_AIC_SRCTYPE_EXT_NEGATIVE_EDGE ((unsigned int) 0x1 << 5) // (AIC) External Sources Code Label Negative Edge triggered -#define AT91C_AIC_SRCTYPE_HIGH_LEVEL ((unsigned int) 0x2 << 5) // (AIC) Internal Or External Sources Code Label High-level Sensitive -#define AT91C_AIC_SRCTYPE_POSITIVE_EDGE ((unsigned int) 0x3 << 5) // (AIC) Internal Or External Sources Code Label Positive Edge triggered -// -------- AIC_CISR : (AIC Offset: 0x114) AIC Core Interrupt Status Register -------- -#define AT91C_AIC_NFIQ ((unsigned int) 0x1 << 0) // (AIC) NFIQ Status -#define AT91C_AIC_NIRQ ((unsigned int) 0x1 << 1) // (AIC) NIRQ Status -// -------- AIC_DCR : (AIC Offset: 0x138) AIC Debug Control Register (Protect) -------- -#define AT91C_AIC_DCR_PROT ((unsigned int) 0x1 << 0) // (AIC) Protection Mode -#define AT91C_AIC_DCR_GMSK ((unsigned int) 0x1 << 1) // (AIC) General Mask +/* -------- AIC_SMR : (AIC Offset: 0x0) Control Register -------- */ +#define AT91C_AIC_PRIOR ( ( unsigned int ) 0x7 << 0 ) /* (AIC) Priority Level */ +#define AT91C_AIC_PRIOR_LOWEST ( ( unsigned int ) 0x0 ) /* (AIC) Lowest priority level */ +#define AT91C_AIC_PRIOR_HIGHEST ( ( unsigned int ) 0x7 ) /* (AIC) Highest priority level */ +#define AT91C_AIC_SRCTYPE ( ( unsigned int ) 0x3 << 5 ) /* (AIC) Interrupt Source Type */ +#define AT91C_AIC_SRCTYPE_INT_HIGH_LEVEL ( ( unsigned int ) 0x0 << 5 ) /* (AIC) Internal Sources Code Label High-level Sensitive */ +#define AT91C_AIC_SRCTYPE_EXT_LOW_LEVEL ( ( unsigned int ) 0x0 << 5 ) /* (AIC) External Sources Code Label Low-level Sensitive */ +#define AT91C_AIC_SRCTYPE_INT_POSITIVE_EDGE ( ( unsigned int ) 0x1 << 5 ) /* (AIC) Internal Sources Code Label Positive Edge triggered */ +#define AT91C_AIC_SRCTYPE_EXT_NEGATIVE_EDGE ( ( unsigned int ) 0x1 << 5 ) /* (AIC) External Sources Code Label Negative Edge triggered */ +#define AT91C_AIC_SRCTYPE_HIGH_LEVEL ( ( unsigned int ) 0x2 << 5 ) /* (AIC) Internal Or External Sources Code Label High-level Sensitive */ +#define AT91C_AIC_SRCTYPE_POSITIVE_EDGE ( ( unsigned int ) 0x3 << 5 ) /* (AIC) Internal Or External Sources Code Label Positive Edge triggered */ +/* -------- AIC_CISR : (AIC Offset: 0x114) AIC Core Interrupt Status Register -------- */ +#define AT91C_AIC_NFIQ ( ( unsigned int ) 0x1 << 0 ) /* (AIC) NFIQ Status */ +#define AT91C_AIC_NIRQ ( ( unsigned int ) 0x1 << 1 ) /* (AIC) NIRQ Status */ +/* -------- AIC_DCR : (AIC Offset: 0x138) AIC Debug Control Register (Protect) -------- */ +#define AT91C_AIC_DCR_PROT ( ( unsigned int ) 0x1 << 0 ) /* (AIC) Protection Mode */ +#define AT91C_AIC_DCR_GMSK ( ( unsigned int ) 0x1 << 1 ) /* (AIC) General Mask */ -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Peripheral DMA Controller -// ***************************************************************************** -typedef struct _AT91S_PDC { - AT91_REG PDC_RPR; // Receive Pointer Register - AT91_REG PDC_RCR; // Receive Counter Register - AT91_REG PDC_TPR; // Transmit Pointer Register - AT91_REG PDC_TCR; // Transmit Counter Register - AT91_REG PDC_RNPR; // Receive Next Pointer Register - AT91_REG PDC_RNCR; // Receive Next Counter Register - AT91_REG PDC_TNPR; // Transmit Next Pointer Register - AT91_REG PDC_TNCR; // Transmit Next Counter Register - AT91_REG PDC_PTCR; // PDC Transfer Control Register - AT91_REG PDC_PTSR; // PDC Transfer Status Register -} AT91S_PDC, *AT91PS_PDC; +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR Peripheral DMA Controller */ +/* ***************************************************************************** */ +typedef struct _AT91S_PDC +{ + AT91_REG PDC_RPR; /* Receive Pointer Register */ + AT91_REG PDC_RCR; /* Receive Counter Register */ + AT91_REG PDC_TPR; /* Transmit Pointer Register */ + AT91_REG PDC_TCR; /* Transmit Counter Register */ + AT91_REG PDC_RNPR; /* Receive Next Pointer Register */ + AT91_REG PDC_RNCR; /* Receive Next Counter Register */ + AT91_REG PDC_TNPR; /* Transmit Next Pointer Register */ + AT91_REG PDC_TNCR; /* Transmit Next Counter Register */ + AT91_REG PDC_PTCR; /* PDC Transfer Control Register */ + AT91_REG PDC_PTSR; /* PDC Transfer Status Register */ +} AT91S_PDC, * AT91PS_PDC; -// -------- PDC_PTCR : (PDC Offset: 0x20) PDC Transfer Control Register -------- -#define AT91C_PDC_RXTEN ((unsigned int) 0x1 << 0) // (PDC) Receiver Transfer Enable -#define AT91C_PDC_RXTDIS ((unsigned int) 0x1 << 1) // (PDC) Receiver Transfer Disable -#define AT91C_PDC_TXTEN ((unsigned int) 0x1 << 8) // (PDC) Transmitter Transfer Enable -#define AT91C_PDC_TXTDIS ((unsigned int) 0x1 << 9) // (PDC) Transmitter Transfer Disable -// -------- PDC_PTSR : (PDC Offset: 0x24) PDC Transfer Status Register -------- +/* -------- PDC_PTCR : (PDC Offset: 0x20) PDC Transfer Control Register -------- */ +#define AT91C_PDC_RXTEN ( ( unsigned int ) 0x1 << 0 ) /* (PDC) Receiver Transfer Enable */ +#define AT91C_PDC_RXTDIS ( ( unsigned int ) 0x1 << 1 ) /* (PDC) Receiver Transfer Disable */ +#define AT91C_PDC_TXTEN ( ( unsigned int ) 0x1 << 8 ) /* (PDC) Transmitter Transfer Enable */ +#define AT91C_PDC_TXTDIS ( ( unsigned int ) 0x1 << 9 ) /* (PDC) Transmitter Transfer Disable */ +/* -------- PDC_PTSR : (PDC Offset: 0x24) PDC Transfer Status Register -------- */ -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Debug Unit -// ***************************************************************************** -typedef struct _AT91S_DBGU { - AT91_REG DBGU_CR; // Control Register - AT91_REG DBGU_MR; // Mode Register - AT91_REG DBGU_IER; // Interrupt Enable Register - AT91_REG DBGU_IDR; // Interrupt Disable Register - AT91_REG DBGU_IMR; // Interrupt Mask Register - AT91_REG DBGU_CSR; // Channel Status Register - AT91_REG DBGU_RHR; // Receiver Holding Register - AT91_REG DBGU_THR; // Transmitter Holding Register - AT91_REG DBGU_BRGR; // Baud Rate Generator Register - AT91_REG Reserved0[7]; // - AT91_REG DBGU_CIDR; // Chip ID Register - AT91_REG DBGU_EXID; // Chip ID Extension Register - AT91_REG DBGU_FNTR; // Force NTRST Register - AT91_REG Reserved1[45]; // - AT91_REG DBGU_RPR; // Receive Pointer Register - AT91_REG DBGU_RCR; // Receive Counter Register - AT91_REG DBGU_TPR; // Transmit Pointer Register - AT91_REG DBGU_TCR; // Transmit Counter Register - AT91_REG DBGU_RNPR; // Receive Next Pointer Register - AT91_REG DBGU_RNCR; // Receive Next Counter Register - AT91_REG DBGU_TNPR; // Transmit Next Pointer Register - AT91_REG DBGU_TNCR; // Transmit Next Counter Register - AT91_REG DBGU_PTCR; // PDC Transfer Control Register - AT91_REG DBGU_PTSR; // PDC Transfer Status Register -} AT91S_DBGU, *AT91PS_DBGU; +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR Debug Unit */ +/* ***************************************************************************** */ +typedef struct _AT91S_DBGU +{ + AT91_REG DBGU_CR; /* Control Register */ + AT91_REG DBGU_MR; /* Mode Register */ + AT91_REG DBGU_IER; /* Interrupt Enable Register */ + AT91_REG DBGU_IDR; /* Interrupt Disable Register */ + AT91_REG DBGU_IMR; /* Interrupt Mask Register */ + AT91_REG DBGU_CSR; /* Channel Status Register */ + AT91_REG DBGU_RHR; /* Receiver Holding Register */ + AT91_REG DBGU_THR; /* Transmitter Holding Register */ + AT91_REG DBGU_BRGR; /* Baud Rate Generator Register */ + AT91_REG Reserved0[ 7 ]; /* */ + AT91_REG DBGU_CIDR; /* Chip ID Register */ + AT91_REG DBGU_EXID; /* Chip ID Extension Register */ + AT91_REG DBGU_FNTR; /* Force NTRST Register */ + AT91_REG Reserved1[ 45 ]; /* */ + AT91_REG DBGU_RPR; /* Receive Pointer Register */ + AT91_REG DBGU_RCR; /* Receive Counter Register */ + AT91_REG DBGU_TPR; /* Transmit Pointer Register */ + AT91_REG DBGU_TCR; /* Transmit Counter Register */ + AT91_REG DBGU_RNPR; /* Receive Next Pointer Register */ + AT91_REG DBGU_RNCR; /* Receive Next Counter Register */ + AT91_REG DBGU_TNPR; /* Transmit Next Pointer Register */ + AT91_REG DBGU_TNCR; /* Transmit Next Counter Register */ + AT91_REG DBGU_PTCR; /* PDC Transfer Control Register */ + AT91_REG DBGU_PTSR; /* PDC Transfer Status Register */ +} AT91S_DBGU, * AT91PS_DBGU; -// -------- DBGU_CR : (DBGU Offset: 0x0) Debug Unit Control Register -------- -#define AT91C_US_RSTRX ((unsigned int) 0x1 << 2) // (DBGU) Reset Receiver -#define AT91C_US_RSTTX ((unsigned int) 0x1 << 3) // (DBGU) Reset Transmitter -#define AT91C_US_RXEN ((unsigned int) 0x1 << 4) // (DBGU) Receiver Enable -#define AT91C_US_RXDIS ((unsigned int) 0x1 << 5) // (DBGU) Receiver Disable -#define AT91C_US_TXEN ((unsigned int) 0x1 << 6) // (DBGU) Transmitter Enable -#define AT91C_US_TXDIS ((unsigned int) 0x1 << 7) // (DBGU) Transmitter Disable -#define AT91C_US_RSTSTA ((unsigned int) 0x1 << 8) // (DBGU) Reset Status Bits -// -------- DBGU_MR : (DBGU Offset: 0x4) Debug Unit Mode Register -------- -#define AT91C_US_PAR ((unsigned int) 0x7 << 9) // (DBGU) Parity type -#define AT91C_US_PAR_EVEN ((unsigned int) 0x0 << 9) // (DBGU) Even Parity -#define AT91C_US_PAR_ODD ((unsigned int) 0x1 << 9) // (DBGU) Odd Parity -#define AT91C_US_PAR_SPACE ((unsigned int) 0x2 << 9) // (DBGU) Parity forced to 0 (Space) -#define AT91C_US_PAR_MARK ((unsigned int) 0x3 << 9) // (DBGU) Parity forced to 1 (Mark) -#define AT91C_US_PAR_NONE ((unsigned int) 0x4 << 9) // (DBGU) No Parity -#define AT91C_US_PAR_MULTI_DROP ((unsigned int) 0x6 << 9) // (DBGU) Multi-drop mode -#define AT91C_US_CHMODE ((unsigned int) 0x3 << 14) // (DBGU) Channel Mode -#define AT91C_US_CHMODE_NORMAL ((unsigned int) 0x0 << 14) // (DBGU) Normal Mode: The USART channel operates as an RX/TX USART. -#define AT91C_US_CHMODE_AUTO ((unsigned int) 0x1 << 14) // (DBGU) Automatic Echo: Receiver Data Input is connected to the TXD pin. -#define AT91C_US_CHMODE_LOCAL ((unsigned int) 0x2 << 14) // (DBGU) Local Loopback: Transmitter Output Signal is connected to Receiver Input Signal. -#define AT91C_US_CHMODE_REMOTE ((unsigned int) 0x3 << 14) // (DBGU) Remote Loopback: RXD pin is internally connected to TXD pin. -// -------- DBGU_IER : (DBGU Offset: 0x8) Debug Unit Interrupt Enable Register -------- -#define AT91C_US_RXRDY ((unsigned int) 0x1 << 0) // (DBGU) RXRDY Interrupt -#define AT91C_US_TXRDY ((unsigned int) 0x1 << 1) // (DBGU) TXRDY Interrupt -#define AT91C_US_ENDRX ((unsigned int) 0x1 << 3) // (DBGU) End of Receive Transfer Interrupt -#define AT91C_US_ENDTX ((unsigned int) 0x1 << 4) // (DBGU) End of Transmit Interrupt -#define AT91C_US_OVRE ((unsigned int) 0x1 << 5) // (DBGU) Overrun Interrupt -#define AT91C_US_FRAME ((unsigned int) 0x1 << 6) // (DBGU) Framing Error Interrupt -#define AT91C_US_PARE ((unsigned int) 0x1 << 7) // (DBGU) Parity Error Interrupt -#define AT91C_US_TXEMPTY ((unsigned int) 0x1 << 9) // (DBGU) TXEMPTY Interrupt -#define AT91C_US_TXBUFE ((unsigned int) 0x1 << 11) // (DBGU) TXBUFE Interrupt -#define AT91C_US_RXBUFF ((unsigned int) 0x1 << 12) // (DBGU) RXBUFF Interrupt -#define AT91C_US_COMM_TX ((unsigned int) 0x1 << 30) // (DBGU) COMM_TX Interrupt -#define AT91C_US_COMM_RX ((unsigned int) 0x1 << 31) // (DBGU) COMM_RX Interrupt -// -------- DBGU_IDR : (DBGU Offset: 0xc) Debug Unit Interrupt Disable Register -------- -// -------- DBGU_IMR : (DBGU Offset: 0x10) Debug Unit Interrupt Mask Register -------- -// -------- DBGU_CSR : (DBGU Offset: 0x14) Debug Unit Channel Status Register -------- -// -------- DBGU_FNTR : (DBGU Offset: 0x48) Debug Unit FORCE_NTRST Register -------- -#define AT91C_US_FORCE_NTRST ((unsigned int) 0x1 << 0) // (DBGU) Force NTRST in JTAG +/* -------- DBGU_CR : (DBGU Offset: 0x0) Debug Unit Control Register -------- */ +#define AT91C_US_RSTRX ( ( unsigned int ) 0x1 << 2 ) /* (DBGU) Reset Receiver */ +#define AT91C_US_RSTTX ( ( unsigned int ) 0x1 << 3 ) /* (DBGU) Reset Transmitter */ +#define AT91C_US_RXEN ( ( unsigned int ) 0x1 << 4 ) /* (DBGU) Receiver Enable */ +#define AT91C_US_RXDIS ( ( unsigned int ) 0x1 << 5 ) /* (DBGU) Receiver Disable */ +#define AT91C_US_TXEN ( ( unsigned int ) 0x1 << 6 ) /* (DBGU) Transmitter Enable */ +#define AT91C_US_TXDIS ( ( unsigned int ) 0x1 << 7 ) /* (DBGU) Transmitter Disable */ +#define AT91C_US_RSTSTA ( ( unsigned int ) 0x1 << 8 ) /* (DBGU) Reset Status Bits */ +/* -------- DBGU_MR : (DBGU Offset: 0x4) Debug Unit Mode Register -------- */ +#define AT91C_US_PAR ( ( unsigned int ) 0x7 << 9 ) /* (DBGU) Parity type */ +#define AT91C_US_PAR_EVEN ( ( unsigned int ) 0x0 << 9 ) /* (DBGU) Even Parity */ +#define AT91C_US_PAR_ODD ( ( unsigned int ) 0x1 << 9 ) /* (DBGU) Odd Parity */ +#define AT91C_US_PAR_SPACE ( ( unsigned int ) 0x2 << 9 ) /* (DBGU) Parity forced to 0 (Space) */ +#define AT91C_US_PAR_MARK ( ( unsigned int ) 0x3 << 9 ) /* (DBGU) Parity forced to 1 (Mark) */ +#define AT91C_US_PAR_NONE ( ( unsigned int ) 0x4 << 9 ) /* (DBGU) No Parity */ +#define AT91C_US_PAR_MULTI_DROP ( ( unsigned int ) 0x6 << 9 ) /* (DBGU) Multi-drop mode */ +#define AT91C_US_CHMODE ( ( unsigned int ) 0x3 << 14 ) /* (DBGU) Channel Mode */ +#define AT91C_US_CHMODE_NORMAL ( ( unsigned int ) 0x0 << 14 ) /* (DBGU) Normal Mode: The USART channel operates as an RX/TX USART. */ +#define AT91C_US_CHMODE_AUTO ( ( unsigned int ) 0x1 << 14 ) /* (DBGU) Automatic Echo: Receiver Data Input is connected to the TXD pin. */ +#define AT91C_US_CHMODE_LOCAL ( ( unsigned int ) 0x2 << 14 ) /* (DBGU) Local Loopback: Transmitter Output Signal is connected to Receiver Input Signal. */ +#define AT91C_US_CHMODE_REMOTE ( ( unsigned int ) 0x3 << 14 ) /* (DBGU) Remote Loopback: RXD pin is internally connected to TXD pin. */ +/* -------- DBGU_IER : (DBGU Offset: 0x8) Debug Unit Interrupt Enable Register -------- */ +#define AT91C_US_RXRDY ( ( unsigned int ) 0x1 << 0 ) /* (DBGU) RXRDY Interrupt */ +#define AT91C_US_TXRDY ( ( unsigned int ) 0x1 << 1 ) /* (DBGU) TXRDY Interrupt */ +#define AT91C_US_ENDRX ( ( unsigned int ) 0x1 << 3 ) /* (DBGU) End of Receive Transfer Interrupt */ +#define AT91C_US_ENDTX ( ( unsigned int ) 0x1 << 4 ) /* (DBGU) End of Transmit Interrupt */ +#define AT91C_US_OVRE ( ( unsigned int ) 0x1 << 5 ) /* (DBGU) Overrun Interrupt */ +#define AT91C_US_FRAME ( ( unsigned int ) 0x1 << 6 ) /* (DBGU) Framing Error Interrupt */ +#define AT91C_US_PARE ( ( unsigned int ) 0x1 << 7 ) /* (DBGU) Parity Error Interrupt */ +#define AT91C_US_TXEMPTY ( ( unsigned int ) 0x1 << 9 ) /* (DBGU) TXEMPTY Interrupt */ +#define AT91C_US_TXBUFE ( ( unsigned int ) 0x1 << 11 ) /* (DBGU) TXBUFE Interrupt */ +#define AT91C_US_RXBUFF ( ( unsigned int ) 0x1 << 12 ) /* (DBGU) RXBUFF Interrupt */ +#define AT91C_US_COMM_TX ( ( unsigned int ) 0x1 << 30 ) /* (DBGU) COMM_TX Interrupt */ +#define AT91C_US_COMM_RX ( ( unsigned int ) 0x1 << 31 ) /* (DBGU) COMM_RX Interrupt */ +/* -------- DBGU_IDR : (DBGU Offset: 0xc) Debug Unit Interrupt Disable Register -------- */ +/* -------- DBGU_IMR : (DBGU Offset: 0x10) Debug Unit Interrupt Mask Register -------- */ +/* -------- DBGU_CSR : (DBGU Offset: 0x14) Debug Unit Channel Status Register -------- */ +/* -------- DBGU_FNTR : (DBGU Offset: 0x48) Debug Unit FORCE_NTRST Register -------- */ +#define AT91C_US_FORCE_NTRST ( ( unsigned int ) 0x1 << 0 ) /* (DBGU) Force NTRST in JTAG */ -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Parallel Input Output Controler -// ***************************************************************************** -typedef struct _AT91S_PIO { - AT91_REG PIO_PER; // PIO Enable Register - AT91_REG PIO_PDR; // PIO Disable Register - AT91_REG PIO_PSR; // PIO Status Register - AT91_REG Reserved0[1]; // - AT91_REG PIO_OER; // Output Enable Register - AT91_REG PIO_ODR; // Output Disable Registerr - AT91_REG PIO_OSR; // Output Status Register - AT91_REG Reserved1[1]; // - AT91_REG PIO_IFER; // Input Filter Enable Register - AT91_REG PIO_IFDR; // Input Filter Disable Register - AT91_REG PIO_IFSR; // Input Filter Status Register - AT91_REG Reserved2[1]; // - AT91_REG PIO_SODR; // Set Output Data Register - AT91_REG PIO_CODR; // Clear Output Data Register - AT91_REG PIO_ODSR; // Output Data Status Register - AT91_REG PIO_PDSR; // Pin Data Status Register - AT91_REG PIO_IER; // Interrupt Enable Register - AT91_REG PIO_IDR; // Interrupt Disable Register - AT91_REG PIO_IMR; // Interrupt Mask Register - AT91_REG PIO_ISR; // Interrupt Status Register - AT91_REG PIO_MDER; // Multi-driver Enable Register - AT91_REG PIO_MDDR; // Multi-driver Disable Register - AT91_REG PIO_MDSR; // Multi-driver Status Register - AT91_REG Reserved3[1]; // - AT91_REG PIO_PPUDR; // Pull-up Disable Register - AT91_REG PIO_PPUER; // Pull-up Enable Register - AT91_REG PIO_PPUSR; // Pull-up Status Register - AT91_REG Reserved4[1]; // - AT91_REG PIO_ASR; // Select A Register - AT91_REG PIO_BSR; // Select B Register - AT91_REG PIO_ABSR; // AB Select Status Register - AT91_REG Reserved5[9]; // - AT91_REG PIO_OWER; // Output Write Enable Register - AT91_REG PIO_OWDR; // Output Write Disable Register - AT91_REG PIO_OWSR; // Output Write Status Register -} AT91S_PIO, *AT91PS_PIO; +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR Parallel Input Output Controller */ +/* ***************************************************************************** */ +typedef struct _AT91S_PIO +{ + AT91_REG PIO_PER; /* PIO Enable Register */ + AT91_REG PIO_PDR; /* PIO Disable Register */ + AT91_REG PIO_PSR; /* PIO Status Register */ + AT91_REG Reserved0[ 1 ]; /* */ + AT91_REG PIO_OER; /* Output Enable Register */ + AT91_REG PIO_ODR; /* Output Disable Registerr */ + AT91_REG PIO_OSR; /* Output Status Register */ + AT91_REG Reserved1[ 1 ]; /* */ + AT91_REG PIO_IFER; /* Input Filter Enable Register */ + AT91_REG PIO_IFDR; /* Input Filter Disable Register */ + AT91_REG PIO_IFSR; /* Input Filter Status Register */ + AT91_REG Reserved2[ 1 ]; /* */ + AT91_REG PIO_SODR; /* Set Output Data Register */ + AT91_REG PIO_CODR; /* Clear Output Data Register */ + AT91_REG PIO_ODSR; /* Output Data Status Register */ + AT91_REG PIO_PDSR; /* Pin Data Status Register */ + AT91_REG PIO_IER; /* Interrupt Enable Register */ + AT91_REG PIO_IDR; /* Interrupt Disable Register */ + AT91_REG PIO_IMR; /* Interrupt Mask Register */ + AT91_REG PIO_ISR; /* Interrupt Status Register */ + AT91_REG PIO_MDER; /* Multi-driver Enable Register */ + AT91_REG PIO_MDDR; /* Multi-driver Disable Register */ + AT91_REG PIO_MDSR; /* Multi-driver Status Register */ + AT91_REG Reserved3[ 1 ]; /* */ + AT91_REG PIO_PPUDR; /* Pull-up Disable Register */ + AT91_REG PIO_PPUER; /* Pull-up Enable Register */ + AT91_REG PIO_PPUSR; /* Pull-up Status Register */ + AT91_REG Reserved4[ 1 ]; /* */ + AT91_REG PIO_ASR; /* Select A Register */ + AT91_REG PIO_BSR; /* Select B Register */ + AT91_REG PIO_ABSR; /* AB Select Status Register */ + AT91_REG Reserved5[ 9 ]; /* */ + AT91_REG PIO_OWER; /* Output Write Enable Register */ + AT91_REG PIO_OWDR; /* Output Write Disable Register */ + AT91_REG PIO_OWSR; /* Output Write Status Register */ +} AT91S_PIO, * AT91PS_PIO; -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Clock Generator Controler -// ***************************************************************************** -typedef struct _AT91S_CKGR { - AT91_REG CKGR_MOR; // Main Oscillator Register - AT91_REG CKGR_MCFR; // Main Clock Frequency Register - AT91_REG Reserved0[1]; // - AT91_REG CKGR_PLLR; // PLL Register -} AT91S_CKGR, *AT91PS_CKGR; +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR Clock Generator Controller */ +/* ***************************************************************************** */ +typedef struct _AT91S_CKGR +{ + AT91_REG CKGR_MOR; /* Main Oscillator Register */ + AT91_REG CKGR_MCFR; /* Main Clock Frequency Register */ + AT91_REG Reserved0[ 1 ]; /* */ + AT91_REG CKGR_PLLR; /* PLL Register */ +} AT91S_CKGR, * AT91PS_CKGR; -// -------- CKGR_MOR : (CKGR Offset: 0x0) Main Oscillator Register -------- -#define AT91C_CKGR_MOSCEN ((unsigned int) 0x1 << 0) // (CKGR) Main Oscillator Enable -#define AT91C_CKGR_OSCBYPASS ((unsigned int) 0x1 << 1) // (CKGR) Main Oscillator Bypass -#define AT91C_CKGR_OSCOUNT ((unsigned int) 0xFF << 8) // (CKGR) Main Oscillator Start-up Time -// -------- CKGR_MCFR : (CKGR Offset: 0x4) Main Clock Frequency Register -------- -#define AT91C_CKGR_MAINF ((unsigned int) 0xFFFF << 0) // (CKGR) Main Clock Frequency -#define AT91C_CKGR_MAINRDY ((unsigned int) 0x1 << 16) // (CKGR) Main Clock Ready -// -------- CKGR_PLLR : (CKGR Offset: 0xc) PLL B Register -------- -#define AT91C_CKGR_DIV ((unsigned int) 0xFF << 0) // (CKGR) Divider Selected -#define AT91C_CKGR_DIV_0 ((unsigned int) 0x0) // (CKGR) Divider output is 0 -#define AT91C_CKGR_DIV_BYPASS ((unsigned int) 0x1) // (CKGR) Divider is bypassed -#define AT91C_CKGR_PLLCOUNT ((unsigned int) 0x3F << 8) // (CKGR) PLL Counter -#define AT91C_CKGR_OUT ((unsigned int) 0x3 << 14) // (CKGR) PLL Output Frequency Range -#define AT91C_CKGR_OUT_0 ((unsigned int) 0x0 << 14) // (CKGR) Please refer to the PLL datasheet -#define AT91C_CKGR_OUT_1 ((unsigned int) 0x1 << 14) // (CKGR) Please refer to the PLL datasheet -#define AT91C_CKGR_OUT_2 ((unsigned int) 0x2 << 14) // (CKGR) Please refer to the PLL datasheet -#define AT91C_CKGR_OUT_3 ((unsigned int) 0x3 << 14) // (CKGR) Please refer to the PLL datasheet -#define AT91C_CKGR_MUL ((unsigned int) 0x7FF << 16) // (CKGR) PLL Multiplier -#define AT91C_CKGR_USBDIV ((unsigned int) 0x3 << 28) // (CKGR) Divider for USB Clocks -#define AT91C_CKGR_USBDIV_0 ((unsigned int) 0x0 << 28) // (CKGR) Divider output is PLL clock output -#define AT91C_CKGR_USBDIV_1 ((unsigned int) 0x1 << 28) // (CKGR) Divider output is PLL clock output divided by 2 -#define AT91C_CKGR_USBDIV_2 ((unsigned int) 0x2 << 28) // (CKGR) Divider output is PLL clock output divided by 4 +/* -------- CKGR_MOR : (CKGR Offset: 0x0) Main Oscillator Register -------- */ +#define AT91C_CKGR_MOSCEN ( ( unsigned int ) 0x1 << 0 ) /* (CKGR) Main Oscillator Enable */ +#define AT91C_CKGR_OSCBYPASS ( ( unsigned int ) 0x1 << 1 ) /* (CKGR) Main Oscillator Bypass */ +#define AT91C_CKGR_OSCOUNT ( ( unsigned int ) 0xFF << 8 ) /* (CKGR) Main Oscillator Start-up Time */ +/* -------- CKGR_MCFR : (CKGR Offset: 0x4) Main Clock Frequency Register -------- */ +#define AT91C_CKGR_MAINF ( ( unsigned int ) 0xFFFF << 0 ) /* (CKGR) Main Clock Frequency */ +#define AT91C_CKGR_MAINRDY ( ( unsigned int ) 0x1 << 16 ) /* (CKGR) Main Clock Ready */ +/* -------- CKGR_PLLR : (CKGR Offset: 0xc) PLL B Register -------- */ +#define AT91C_CKGR_DIV ( ( unsigned int ) 0xFF << 0 ) /* (CKGR) Divider Selected */ +#define AT91C_CKGR_DIV_0 ( ( unsigned int ) 0x0 ) /* (CKGR) Divider output is 0 */ +#define AT91C_CKGR_DIV_BYPASS ( ( unsigned int ) 0x1 ) /* (CKGR) Divider is bypassed */ +#define AT91C_CKGR_PLLCOUNT ( ( unsigned int ) 0x3F << 8 ) /* (CKGR) PLL Counter */ +#define AT91C_CKGR_OUT ( ( unsigned int ) 0x3 << 14 ) /* (CKGR) PLL Output Frequency Range */ +#define AT91C_CKGR_OUT_0 ( ( unsigned int ) 0x0 << 14 ) /* (CKGR) Please refer to the PLL datasheet */ +#define AT91C_CKGR_OUT_1 ( ( unsigned int ) 0x1 << 14 ) /* (CKGR) Please refer to the PLL datasheet */ +#define AT91C_CKGR_OUT_2 ( ( unsigned int ) 0x2 << 14 ) /* (CKGR) Please refer to the PLL datasheet */ +#define AT91C_CKGR_OUT_3 ( ( unsigned int ) 0x3 << 14 ) /* (CKGR) Please refer to the PLL datasheet */ +#define AT91C_CKGR_MUL ( ( unsigned int ) 0x7FF << 16 ) /* (CKGR) PLL Multiplier */ +#define AT91C_CKGR_USBDIV ( ( unsigned int ) 0x3 << 28 ) /* (CKGR) Divider for USB Clocks */ +#define AT91C_CKGR_USBDIV_0 ( ( unsigned int ) 0x0 << 28 ) /* (CKGR) Divider output is PLL clock output */ +#define AT91C_CKGR_USBDIV_1 ( ( unsigned int ) 0x1 << 28 ) /* (CKGR) Divider output is PLL clock output divided by 2 */ +#define AT91C_CKGR_USBDIV_2 ( ( unsigned int ) 0x2 << 28 ) /* (CKGR) Divider output is PLL clock output divided by 4 */ -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Power Management Controler -// ***************************************************************************** -typedef struct _AT91S_PMC { - AT91_REG PMC_SCER; // System Clock Enable Register - AT91_REG PMC_SCDR; // System Clock Disable Register - AT91_REG PMC_SCSR; // System Clock Status Register - AT91_REG Reserved0[1]; // - AT91_REG PMC_PCER; // Peripheral Clock Enable Register - AT91_REG PMC_PCDR; // Peripheral Clock Disable Register - AT91_REG PMC_PCSR; // Peripheral Clock Status Register - AT91_REG Reserved1[1]; // - AT91_REG PMC_MOR; // Main Oscillator Register - AT91_REG PMC_MCFR; // Main Clock Frequency Register - AT91_REG Reserved2[1]; // - AT91_REG PMC_PLLR; // PLL Register - AT91_REG PMC_MCKR; // Master Clock Register - AT91_REG Reserved3[3]; // - AT91_REG PMC_PCKR[4]; // Programmable Clock Register - AT91_REG Reserved4[4]; // - AT91_REG PMC_IER; // Interrupt Enable Register - AT91_REG PMC_IDR; // Interrupt Disable Register - AT91_REG PMC_SR; // Status Register - AT91_REG PMC_IMR; // Interrupt Mask Register -} AT91S_PMC, *AT91PS_PMC; +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR Power Management Controller */ +/* ***************************************************************************** */ +typedef struct _AT91S_PMC +{ + AT91_REG PMC_SCER; /* System Clock Enable Register */ + AT91_REG PMC_SCDR; /* System Clock Disable Register */ + AT91_REG PMC_SCSR; /* System Clock Status Register */ + AT91_REG Reserved0[ 1 ]; /* */ + AT91_REG PMC_PCER; /* Peripheral Clock Enable Register */ + AT91_REG PMC_PCDR; /* Peripheral Clock Disable Register */ + AT91_REG PMC_PCSR; /* Peripheral Clock Status Register */ + AT91_REG Reserved1[ 1 ]; /* */ + AT91_REG PMC_MOR; /* Main Oscillator Register */ + AT91_REG PMC_MCFR; /* Main Clock Frequency Register */ + AT91_REG Reserved2[ 1 ]; /* */ + AT91_REG PMC_PLLR; /* PLL Register */ + AT91_REG PMC_MCKR; /* Master Clock Register */ + AT91_REG Reserved3[ 3 ]; /* */ + AT91_REG PMC_PCKR[ 4 ]; /* Programmable Clock Register */ + AT91_REG Reserved4[ 4 ]; /* */ + AT91_REG PMC_IER; /* Interrupt Enable Register */ + AT91_REG PMC_IDR; /* Interrupt Disable Register */ + AT91_REG PMC_SR; /* Status Register */ + AT91_REG PMC_IMR; /* Interrupt Mask Register */ +} AT91S_PMC, * AT91PS_PMC; -// -------- PMC_SCER : (PMC Offset: 0x0) System Clock Enable Register -------- -#define AT91C_PMC_PCK ((unsigned int) 0x1 << 0) // (PMC) Processor Clock -#define AT91C_PMC_UDP ((unsigned int) 0x1 << 7) // (PMC) USB Device Port Clock -#define AT91C_PMC_PCK0 ((unsigned int) 0x1 << 8) // (PMC) Programmable Clock Output -#define AT91C_PMC_PCK1 ((unsigned int) 0x1 << 9) // (PMC) Programmable Clock Output -#define AT91C_PMC_PCK2 ((unsigned int) 0x1 << 10) // (PMC) Programmable Clock Output -#define AT91C_PMC_PCK3 ((unsigned int) 0x1 << 11) // (PMC) Programmable Clock Output -// -------- PMC_SCDR : (PMC Offset: 0x4) System Clock Disable Register -------- -// -------- PMC_SCSR : (PMC Offset: 0x8) System Clock Status Register -------- -// -------- CKGR_MOR : (PMC Offset: 0x20) Main Oscillator Register -------- -// -------- CKGR_MCFR : (PMC Offset: 0x24) Main Clock Frequency Register -------- -// -------- CKGR_PLLR : (PMC Offset: 0x2c) PLL B Register -------- -// -------- PMC_MCKR : (PMC Offset: 0x30) Master Clock Register -------- -#define AT91C_PMC_CSS ((unsigned int) 0x3 << 0) // (PMC) Programmable Clock Selection -#define AT91C_PMC_CSS_SLOW_CLK ((unsigned int) 0x0) // (PMC) Slow Clock is selected -#define AT91C_PMC_CSS_MAIN_CLK ((unsigned int) 0x1) // (PMC) Main Clock is selected -#define AT91C_PMC_CSS_PLL_CLK ((unsigned int) 0x3) // (PMC) Clock from PLL is selected -#define AT91C_PMC_PRES ((unsigned int) 0x7 << 2) // (PMC) Programmable Clock Prescaler -#define AT91C_PMC_PRES_CLK ((unsigned int) 0x0 << 2) // (PMC) Selected clock -#define AT91C_PMC_PRES_CLK_2 ((unsigned int) 0x1 << 2) // (PMC) Selected clock divided by 2 -#define AT91C_PMC_PRES_CLK_4 ((unsigned int) 0x2 << 2) // (PMC) Selected clock divided by 4 -#define AT91C_PMC_PRES_CLK_8 ((unsigned int) 0x3 << 2) // (PMC) Selected clock divided by 8 -#define AT91C_PMC_PRES_CLK_16 ((unsigned int) 0x4 << 2) // (PMC) Selected clock divided by 16 -#define AT91C_PMC_PRES_CLK_32 ((unsigned int) 0x5 << 2) // (PMC) Selected clock divided by 32 -#define AT91C_PMC_PRES_CLK_64 ((unsigned int) 0x6 << 2) // (PMC) Selected clock divided by 64 -// -------- PMC_PCKR : (PMC Offset: 0x40) Programmable Clock Register -------- -// -------- PMC_IER : (PMC Offset: 0x60) PMC Interrupt Enable Register -------- -#define AT91C_PMC_MOSCS ((unsigned int) 0x1 << 0) // (PMC) MOSC Status/Enable/Disable/Mask -#define AT91C_PMC_LOCK ((unsigned int) 0x1 << 2) // (PMC) PLL Status/Enable/Disable/Mask -#define AT91C_PMC_MCKRDY ((unsigned int) 0x1 << 3) // (PMC) MCK_RDY Status/Enable/Disable/Mask -#define AT91C_PMC_PCK0RDY ((unsigned int) 0x1 << 8) // (PMC) PCK0_RDY Status/Enable/Disable/Mask -#define AT91C_PMC_PCK1RDY ((unsigned int) 0x1 << 9) // (PMC) PCK1_RDY Status/Enable/Disable/Mask -#define AT91C_PMC_PCK2RDY ((unsigned int) 0x1 << 10) // (PMC) PCK2_RDY Status/Enable/Disable/Mask -#define AT91C_PMC_PCK3RDY ((unsigned int) 0x1 << 11) // (PMC) PCK3_RDY Status/Enable/Disable/Mask -// -------- PMC_IDR : (PMC Offset: 0x64) PMC Interrupt Disable Register -------- -// -------- PMC_SR : (PMC Offset: 0x68) PMC Status Register -------- -// -------- PMC_IMR : (PMC Offset: 0x6c) PMC Interrupt Mask Register -------- +/* -------- PMC_SCER : (PMC Offset: 0x0) System Clock Enable Register -------- */ +#define AT91C_PMC_PCK ( ( unsigned int ) 0x1 << 0 ) /* (PMC) Processor Clock */ +#define AT91C_PMC_UDP ( ( unsigned int ) 0x1 << 7 ) /* (PMC) USB Device Port Clock */ +#define AT91C_PMC_PCK0 ( ( unsigned int ) 0x1 << 8 ) /* (PMC) Programmable Clock Output */ +#define AT91C_PMC_PCK1 ( ( unsigned int ) 0x1 << 9 ) /* (PMC) Programmable Clock Output */ +#define AT91C_PMC_PCK2 ( ( unsigned int ) 0x1 << 10 ) /* (PMC) Programmable Clock Output */ +#define AT91C_PMC_PCK3 ( ( unsigned int ) 0x1 << 11 ) /* (PMC) Programmable Clock Output */ +/* -------- PMC_SCDR : (PMC Offset: 0x4) System Clock Disable Register -------- */ +/* -------- PMC_SCSR : (PMC Offset: 0x8) System Clock Status Register -------- */ +/* -------- CKGR_MOR : (PMC Offset: 0x20) Main Oscillator Register -------- */ +/* -------- CKGR_MCFR : (PMC Offset: 0x24) Main Clock Frequency Register -------- */ +/* -------- CKGR_PLLR : (PMC Offset: 0x2c) PLL B Register -------- */ +/* -------- PMC_MCKR : (PMC Offset: 0x30) Master Clock Register -------- */ +#define AT91C_PMC_CSS ( ( unsigned int ) 0x3 << 0 ) /* (PMC) Programmable Clock Selection */ +#define AT91C_PMC_CSS_SLOW_CLK ( ( unsigned int ) 0x0 ) /* (PMC) Slow Clock is selected */ +#define AT91C_PMC_CSS_MAIN_CLK ( ( unsigned int ) 0x1 ) /* (PMC) Main Clock is selected */ +#define AT91C_PMC_CSS_PLL_CLK ( ( unsigned int ) 0x3 ) /* (PMC) Clock from PLL is selected */ +#define AT91C_PMC_PRES ( ( unsigned int ) 0x7 << 2 ) /* (PMC) Programmable Clock Prescaler */ +#define AT91C_PMC_PRES_CLK ( ( unsigned int ) 0x0 << 2 ) /* (PMC) Selected clock */ +#define AT91C_PMC_PRES_CLK_2 ( ( unsigned int ) 0x1 << 2 ) /* (PMC) Selected clock divided by 2 */ +#define AT91C_PMC_PRES_CLK_4 ( ( unsigned int ) 0x2 << 2 ) /* (PMC) Selected clock divided by 4 */ +#define AT91C_PMC_PRES_CLK_8 ( ( unsigned int ) 0x3 << 2 ) /* (PMC) Selected clock divided by 8 */ +#define AT91C_PMC_PRES_CLK_16 ( ( unsigned int ) 0x4 << 2 ) /* (PMC) Selected clock divided by 16 */ +#define AT91C_PMC_PRES_CLK_32 ( ( unsigned int ) 0x5 << 2 ) /* (PMC) Selected clock divided by 32 */ +#define AT91C_PMC_PRES_CLK_64 ( ( unsigned int ) 0x6 << 2 ) /* (PMC) Selected clock divided by 64 */ +/* -------- PMC_PCKR : (PMC Offset: 0x40) Programmable Clock Register -------- */ +/* -------- PMC_IER : (PMC Offset: 0x60) PMC Interrupt Enable Register -------- */ +#define AT91C_PMC_MOSCS ( ( unsigned int ) 0x1 << 0 ) /* (PMC) MOSC Status/Enable/Disable/Mask */ +#define AT91C_PMC_LOCK ( ( unsigned int ) 0x1 << 2 ) /* (PMC) PLL Status/Enable/Disable/Mask */ +#define AT91C_PMC_MCKRDY ( ( unsigned int ) 0x1 << 3 ) /* (PMC) MCK_RDY Status/Enable/Disable/Mask */ +#define AT91C_PMC_PCK0RDY ( ( unsigned int ) 0x1 << 8 ) /* (PMC) PCK0_RDY Status/Enable/Disable/Mask */ +#define AT91C_PMC_PCK1RDY ( ( unsigned int ) 0x1 << 9 ) /* (PMC) PCK1_RDY Status/Enable/Disable/Mask */ +#define AT91C_PMC_PCK2RDY ( ( unsigned int ) 0x1 << 10 ) /* (PMC) PCK2_RDY Status/Enable/Disable/Mask */ +#define AT91C_PMC_PCK3RDY ( ( unsigned int ) 0x1 << 11 ) /* (PMC) PCK3_RDY Status/Enable/Disable/Mask */ +/* -------- PMC_IDR : (PMC Offset: 0x64) PMC Interrupt Disable Register -------- */ +/* -------- PMC_SR : (PMC Offset: 0x68) PMC Status Register -------- */ +/* -------- PMC_IMR : (PMC Offset: 0x6c) PMC Interrupt Mask Register -------- */ -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Reset Controller Interface -// ***************************************************************************** -typedef struct _AT91S_RSTC { - AT91_REG RSTC_RCR; // Reset Control Register - AT91_REG RSTC_RSR; // Reset Status Register - AT91_REG RSTC_RMR; // Reset Mode Register -} AT91S_RSTC, *AT91PS_RSTC; +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR Reset Controller Interface */ +/* ***************************************************************************** */ +typedef struct _AT91S_RSTC +{ + AT91_REG RSTC_RCR; /* Reset Control Register */ + AT91_REG RSTC_RSR; /* Reset Status Register */ + AT91_REG RSTC_RMR; /* Reset Mode Register */ +} AT91S_RSTC, * AT91PS_RSTC; -// -------- RSTC_RCR : (RSTC Offset: 0x0) Reset Control Register -------- -#define AT91C_RSTC_PROCRST ((unsigned int) 0x1 << 0) // (RSTC) Processor Reset -#define AT91C_RSTC_PERRST ((unsigned int) 0x1 << 2) // (RSTC) Peripheral Reset -#define AT91C_RSTC_EXTRST ((unsigned int) 0x1 << 3) // (RSTC) External Reset -#define AT91C_RSTC_KEY ((unsigned int) 0xFF << 24) // (RSTC) Password -// -------- RSTC_RSR : (RSTC Offset: 0x4) Reset Status Register -------- -#define AT91C_RSTC_URSTS ((unsigned int) 0x1 << 0) // (RSTC) User Reset Status -#define AT91C_RSTC_BODSTS ((unsigned int) 0x1 << 1) // (RSTC) Brownout Detection Status -#define AT91C_RSTC_RSTTYP ((unsigned int) 0x7 << 8) // (RSTC) Reset Type -#define AT91C_RSTC_RSTTYP_POWERUP ((unsigned int) 0x0 << 8) // (RSTC) Power-up Reset. VDDCORE rising. -#define AT91C_RSTC_RSTTYP_WAKEUP ((unsigned int) 0x1 << 8) // (RSTC) WakeUp Reset. VDDCORE rising. -#define AT91C_RSTC_RSTTYP_WATCHDOG ((unsigned int) 0x2 << 8) // (RSTC) Watchdog Reset. Watchdog overflow occured. -#define AT91C_RSTC_RSTTYP_SOFTWARE ((unsigned int) 0x3 << 8) // (RSTC) Software Reset. Processor reset required by the software. -#define AT91C_RSTC_RSTTYP_USER ((unsigned int) 0x4 << 8) // (RSTC) User Reset. NRST pin detected low. -#define AT91C_RSTC_RSTTYP_BROWNOUT ((unsigned int) 0x5 << 8) // (RSTC) Brownout Reset occured. -#define AT91C_RSTC_NRSTL ((unsigned int) 0x1 << 16) // (RSTC) NRST pin level -#define AT91C_RSTC_SRCMP ((unsigned int) 0x1 << 17) // (RSTC) Software Reset Command in Progress. -// -------- RSTC_RMR : (RSTC Offset: 0x8) Reset Mode Register -------- -#define AT91C_RSTC_URSTEN ((unsigned int) 0x1 << 0) // (RSTC) User Reset Enable -#define AT91C_RSTC_URSTIEN ((unsigned int) 0x1 << 4) // (RSTC) User Reset Interrupt Enable -#define AT91C_RSTC_ERSTL ((unsigned int) 0xF << 8) // (RSTC) User Reset Enable -#define AT91C_RSTC_BODIEN ((unsigned int) 0x1 << 16) // (RSTC) Brownout Detection Interrupt Enable +/* -------- RSTC_RCR : (RSTC Offset: 0x0) Reset Control Register -------- */ +#define AT91C_RSTC_PROCRST ( ( unsigned int ) 0x1 << 0 ) /* (RSTC) Processor Reset */ +#define AT91C_RSTC_PERRST ( ( unsigned int ) 0x1 << 2 ) /* (RSTC) Peripheral Reset */ +#define AT91C_RSTC_EXTRST ( ( unsigned int ) 0x1 << 3 ) /* (RSTC) External Reset */ +#define AT91C_RSTC_KEY ( ( unsigned int ) 0xFF << 24 ) /* (RSTC) Password */ +/* -------- RSTC_RSR : (RSTC Offset: 0x4) Reset Status Register -------- */ +#define AT91C_RSTC_URSTS ( ( unsigned int ) 0x1 << 0 ) /* (RSTC) User Reset Status */ +#define AT91C_RSTC_BODSTS ( ( unsigned int ) 0x1 << 1 ) /* (RSTC) Brownout Detection Status */ +#define AT91C_RSTC_RSTTYP ( ( unsigned int ) 0x7 << 8 ) /* (RSTC) Reset Type */ +#define AT91C_RSTC_RSTTYP_POWERUP ( ( unsigned int ) 0x0 << 8 ) /* (RSTC) Power-up Reset. VDDCORE rising. */ +#define AT91C_RSTC_RSTTYP_WAKEUP ( ( unsigned int ) 0x1 << 8 ) /* (RSTC) WakeUp Reset. VDDCORE rising. */ +#define AT91C_RSTC_RSTTYP_WATCHDOG ( ( unsigned int ) 0x2 << 8 ) /* (RSTC) Watchdog Reset. Watchdog overflow occurred. */ +#define AT91C_RSTC_RSTTYP_SOFTWARE ( ( unsigned int ) 0x3 << 8 ) /* (RSTC) Software Reset. Processor reset required by the software. */ +#define AT91C_RSTC_RSTTYP_USER ( ( unsigned int ) 0x4 << 8 ) /* (RSTC) User Reset. NRST pin detected low. */ +#define AT91C_RSTC_RSTTYP_BROWNOUT ( ( unsigned int ) 0x5 << 8 ) /* (RSTC) Brownout Reset occurred. */ +#define AT91C_RSTC_NRSTL ( ( unsigned int ) 0x1 << 16 ) /* (RSTC) NRST pin level */ +#define AT91C_RSTC_SRCMP ( ( unsigned int ) 0x1 << 17 ) /* (RSTC) Software Reset Command in Progress. */ +/* -------- RSTC_RMR : (RSTC Offset: 0x8) Reset Mode Register -------- */ +#define AT91C_RSTC_URSTEN ( ( unsigned int ) 0x1 << 0 ) /* (RSTC) User Reset Enable */ +#define AT91C_RSTC_URSTIEN ( ( unsigned int ) 0x1 << 4 ) /* (RSTC) User Reset Interrupt Enable */ +#define AT91C_RSTC_ERSTL ( ( unsigned int ) 0xF << 8 ) /* (RSTC) User Reset Enable */ +#define AT91C_RSTC_BODIEN ( ( unsigned int ) 0x1 << 16 ) /* (RSTC) Brownout Detection Interrupt Enable */ -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Real Time Timer Controller Interface -// ***************************************************************************** -typedef struct _AT91S_RTTC { - AT91_REG RTTC_RTMR; // Real-time Mode Register - AT91_REG RTTC_RTAR; // Real-time Alarm Register - AT91_REG RTTC_RTVR; // Real-time Value Register - AT91_REG RTTC_RTSR; // Real-time Status Register -} AT91S_RTTC, *AT91PS_RTTC; +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR Real Time Timer Controller Interface */ +/* ***************************************************************************** */ +typedef struct _AT91S_RTTC +{ + AT91_REG RTTC_RTMR; /* Real-time Mode Register */ + AT91_REG RTTC_RTAR; /* Real-time Alarm Register */ + AT91_REG RTTC_RTVR; /* Real-time Value Register */ + AT91_REG RTTC_RTSR; /* Real-time Status Register */ +} AT91S_RTTC, * AT91PS_RTTC; -// -------- RTTC_RTMR : (RTTC Offset: 0x0) Real-time Mode Register -------- -#define AT91C_RTTC_RTPRES ((unsigned int) 0xFFFF << 0) // (RTTC) Real-time Timer Prescaler Value -#define AT91C_RTTC_ALMIEN ((unsigned int) 0x1 << 16) // (RTTC) Alarm Interrupt Enable -#define AT91C_RTTC_RTTINCIEN ((unsigned int) 0x1 << 17) // (RTTC) Real Time Timer Increment Interrupt Enable -#define AT91C_RTTC_RTTRST ((unsigned int) 0x1 << 18) // (RTTC) Real Time Timer Restart -// -------- RTTC_RTAR : (RTTC Offset: 0x4) Real-time Alarm Register -------- -#define AT91C_RTTC_ALMV ((unsigned int) 0x0 << 0) // (RTTC) Alarm Value -// -------- RTTC_RTVR : (RTTC Offset: 0x8) Current Real-time Value Register -------- -#define AT91C_RTTC_CRTV ((unsigned int) 0x0 << 0) // (RTTC) Current Real-time Value -// -------- RTTC_RTSR : (RTTC Offset: 0xc) Real-time Status Register -------- -#define AT91C_RTTC_ALMS ((unsigned int) 0x1 << 0) // (RTTC) Real-time Alarm Status -#define AT91C_RTTC_RTTINC ((unsigned int) 0x1 << 1) // (RTTC) Real-time Timer Increment +/* -------- RTTC_RTMR : (RTTC Offset: 0x0) Real-time Mode Register -------- */ +#define AT91C_RTTC_RTPRES ( ( unsigned int ) 0xFFFF << 0 ) /* (RTTC) Real-time Timer Prescaler Value */ +#define AT91C_RTTC_ALMIEN ( ( unsigned int ) 0x1 << 16 ) /* (RTTC) Alarm Interrupt Enable */ +#define AT91C_RTTC_RTTINCIEN ( ( unsigned int ) 0x1 << 17 ) /* (RTTC) Real Time Timer Increment Interrupt Enable */ +#define AT91C_RTTC_RTTRST ( ( unsigned int ) 0x1 << 18 ) /* (RTTC) Real Time Timer Restart */ +/* -------- RTTC_RTAR : (RTTC Offset: 0x4) Real-time Alarm Register -------- */ +#define AT91C_RTTC_ALMV ( ( unsigned int ) 0x0 << 0 ) /* (RTTC) Alarm Value */ +/* -------- RTTC_RTVR : (RTTC Offset: 0x8) Current Real-time Value Register -------- */ +#define AT91C_RTTC_CRTV ( ( unsigned int ) 0x0 << 0 ) /* (RTTC) Current Real-time Value */ +/* -------- RTTC_RTSR : (RTTC Offset: 0xc) Real-time Status Register -------- */ +#define AT91C_RTTC_ALMS ( ( unsigned int ) 0x1 << 0 ) /* (RTTC) Real-time Alarm Status */ +#define AT91C_RTTC_RTTINC ( ( unsigned int ) 0x1 << 1 ) /* (RTTC) Real-time Timer Increment */ -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Periodic Interval Timer Controller Interface -// ***************************************************************************** -typedef struct _AT91S_PITC { - AT91_REG PITC_PIMR; // Period Interval Mode Register - AT91_REG PITC_PISR; // Period Interval Status Register - AT91_REG PITC_PIVR; // Period Interval Value Register - AT91_REG PITC_PIIR; // Period Interval Image Register -} AT91S_PITC, *AT91PS_PITC; +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR Periodic Interval Timer Controller Interface */ +/* ***************************************************************************** */ +typedef struct _AT91S_PITC +{ + AT91_REG PITC_PIMR; /* Period Interval Mode Register */ + AT91_REG PITC_PISR; /* Period Interval Status Register */ + AT91_REG PITC_PIVR; /* Period Interval Value Register */ + AT91_REG PITC_PIIR; /* Period Interval Image Register */ +} AT91S_PITC, * AT91PS_PITC; -// -------- PITC_PIMR : (PITC Offset: 0x0) Periodic Interval Mode Register -------- -#define AT91C_PITC_PIV ((unsigned int) 0xFFFFF << 0) // (PITC) Periodic Interval Value -#define AT91C_PITC_PITEN ((unsigned int) 0x1 << 24) // (PITC) Periodic Interval Timer Enabled -#define AT91C_PITC_PITIEN ((unsigned int) 0x1 << 25) // (PITC) Periodic Interval Timer Interrupt Enable -// -------- PITC_PISR : (PITC Offset: 0x4) Periodic Interval Status Register -------- -#define AT91C_PITC_PITS ((unsigned int) 0x1 << 0) // (PITC) Periodic Interval Timer Status -// -------- PITC_PIVR : (PITC Offset: 0x8) Periodic Interval Value Register -------- -#define AT91C_PITC_CPIV ((unsigned int) 0xFFFFF << 0) // (PITC) Current Periodic Interval Value -#define AT91C_PITC_PICNT ((unsigned int) 0xFFF << 20) // (PITC) Periodic Interval Counter -// -------- PITC_PIIR : (PITC Offset: 0xc) Periodic Interval Image Register -------- +/* -------- PITC_PIMR : (PITC Offset: 0x0) Periodic Interval Mode Register -------- */ +#define AT91C_PITC_PIV ( ( unsigned int ) 0xFFFFF << 0 ) /* (PITC) Periodic Interval Value */ +#define AT91C_PITC_PITEN ( ( unsigned int ) 0x1 << 24 ) /* (PITC) Periodic Interval Timer Enabled */ +#define AT91C_PITC_PITIEN ( ( unsigned int ) 0x1 << 25 ) /* (PITC) Periodic Interval Timer Interrupt Enable */ +/* -------- PITC_PISR : (PITC Offset: 0x4) Periodic Interval Status Register -------- */ +#define AT91C_PITC_PITS ( ( unsigned int ) 0x1 << 0 ) /* (PITC) Periodic Interval Timer Status */ +/* -------- PITC_PIVR : (PITC Offset: 0x8) Periodic Interval Value Register -------- */ +#define AT91C_PITC_CPIV ( ( unsigned int ) 0xFFFFF << 0 ) /* (PITC) Current Periodic Interval Value */ +#define AT91C_PITC_PICNT ( ( unsigned int ) 0xFFF << 20 ) /* (PITC) Periodic Interval Counter */ +/* -------- PITC_PIIR : (PITC Offset: 0xc) Periodic Interval Image Register -------- */ -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Watchdog Timer Controller Interface -// ***************************************************************************** -typedef struct _AT91S_WDTC { - AT91_REG WDTC_WDCR; // Watchdog Control Register - AT91_REG WDTC_WDMR; // Watchdog Mode Register - AT91_REG WDTC_WDSR; // Watchdog Status Register -} AT91S_WDTC, *AT91PS_WDTC; +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR Watchdog Timer Controller Interface */ +/* ***************************************************************************** */ +typedef struct _AT91S_WDTC +{ + AT91_REG WDTC_WDCR; /* Watchdog Control Register */ + AT91_REG WDTC_WDMR; /* Watchdog Mode Register */ + AT91_REG WDTC_WDSR; /* Watchdog Status Register */ +} AT91S_WDTC, * AT91PS_WDTC; -// -------- WDTC_WDCR : (WDTC Offset: 0x0) Periodic Interval Image Register -------- -#define AT91C_WDTC_WDRSTT ((unsigned int) 0x1 << 0) // (WDTC) Watchdog Restart -#define AT91C_WDTC_KEY ((unsigned int) 0xFF << 24) // (WDTC) Watchdog KEY Password -// -------- WDTC_WDMR : (WDTC Offset: 0x4) Watchdog Mode Register -------- -#define AT91C_WDTC_WDV ((unsigned int) 0xFFF << 0) // (WDTC) Watchdog Timer Restart -#define AT91C_WDTC_WDFIEN ((unsigned int) 0x1 << 12) // (WDTC) Watchdog Fault Interrupt Enable -#define AT91C_WDTC_WDRSTEN ((unsigned int) 0x1 << 13) // (WDTC) Watchdog Reset Enable -#define AT91C_WDTC_WDRPROC ((unsigned int) 0x1 << 14) // (WDTC) Watchdog Timer Restart -#define AT91C_WDTC_WDDIS ((unsigned int) 0x1 << 15) // (WDTC) Watchdog Disable -#define AT91C_WDTC_WDD ((unsigned int) 0xFFF << 16) // (WDTC) Watchdog Delta Value -#define AT91C_WDTC_WDDBGHLT ((unsigned int) 0x1 << 28) // (WDTC) Watchdog Debug Halt -#define AT91C_WDTC_WDIDLEHLT ((unsigned int) 0x1 << 29) // (WDTC) Watchdog Idle Halt -// -------- WDTC_WDSR : (WDTC Offset: 0x8) Watchdog Status Register -------- -#define AT91C_WDTC_WDUNF ((unsigned int) 0x1 << 0) // (WDTC) Watchdog Underflow -#define AT91C_WDTC_WDERR ((unsigned int) 0x1 << 1) // (WDTC) Watchdog Error +/* -------- WDTC_WDCR : (WDTC Offset: 0x0) Periodic Interval Image Register -------- */ +#define AT91C_WDTC_WDRSTT ( ( unsigned int ) 0x1 << 0 ) /* (WDTC) Watchdog Restart */ +#define AT91C_WDTC_KEY ( ( unsigned int ) 0xFF << 24 ) /* (WDTC) Watchdog KEY Password */ +/* -------- WDTC_WDMR : (WDTC Offset: 0x4) Watchdog Mode Register -------- */ +#define AT91C_WDTC_WDV ( ( unsigned int ) 0xFFF << 0 ) /* (WDTC) Watchdog Timer Restart */ +#define AT91C_WDTC_WDFIEN ( ( unsigned int ) 0x1 << 12 ) /* (WDTC) Watchdog Fault Interrupt Enable */ +#define AT91C_WDTC_WDRSTEN ( ( unsigned int ) 0x1 << 13 ) /* (WDTC) Watchdog Reset Enable */ +#define AT91C_WDTC_WDRPROC ( ( unsigned int ) 0x1 << 14 ) /* (WDTC) Watchdog Timer Restart */ +#define AT91C_WDTC_WDDIS ( ( unsigned int ) 0x1 << 15 ) /* (WDTC) Watchdog Disable */ +#define AT91C_WDTC_WDD ( ( unsigned int ) 0xFFF << 16 ) /* (WDTC) Watchdog Delta Value */ +#define AT91C_WDTC_WDDBGHLT ( ( unsigned int ) 0x1 << 28 ) /* (WDTC) Watchdog Debug Halt */ +#define AT91C_WDTC_WDIDLEHLT ( ( unsigned int ) 0x1 << 29 ) /* (WDTC) Watchdog Idle Halt */ +/* -------- WDTC_WDSR : (WDTC Offset: 0x8) Watchdog Status Register -------- */ +#define AT91C_WDTC_WDUNF ( ( unsigned int ) 0x1 << 0 ) /* (WDTC) Watchdog Underflow */ +#define AT91C_WDTC_WDERR ( ( unsigned int ) 0x1 << 1 ) /* (WDTC) Watchdog Error */ -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Voltage Regulator Mode Controller Interface -// ***************************************************************************** -typedef struct _AT91S_VREG { - AT91_REG VREG_MR; // Voltage Regulator Mode Register -} AT91S_VREG, *AT91PS_VREG; +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR Voltage Regulator Mode Controller Interface */ +/* ***************************************************************************** */ +typedef struct _AT91S_VREG +{ + AT91_REG VREG_MR; /* Voltage Regulator Mode Register */ +} AT91S_VREG, * AT91PS_VREG; -// -------- VREG_MR : (VREG Offset: 0x0) Voltage Regulator Mode Register -------- -#define AT91C_VREG_PSTDBY ((unsigned int) 0x1 << 0) // (VREG) Voltage Regulator Power Standby Mode +/* -------- VREG_MR : (VREG Offset: 0x0) Voltage Regulator Mode Register -------- */ +#define AT91C_VREG_PSTDBY ( ( unsigned int ) 0x1 << 0 ) /* (VREG) Voltage Regulator Power Standby Mode */ -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Memory Controller Interface -// ***************************************************************************** -typedef struct _AT91S_MC { - AT91_REG MC_RCR; // MC Remap Control Register - AT91_REG MC_ASR; // MC Abort Status Register - AT91_REG MC_AASR; // MC Abort Address Status Register - AT91_REG Reserved0[21]; // - AT91_REG MC_FMR; // MC Flash Mode Register - AT91_REG MC_FCR; // MC Flash Command Register - AT91_REG MC_FSR; // MC Flash Status Register -} AT91S_MC, *AT91PS_MC; +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR Memory Controller Interface */ +/* ***************************************************************************** */ +typedef struct _AT91S_MC +{ + AT91_REG MC_RCR; /* MC Remap Control Register */ + AT91_REG MC_ASR; /* MC Abort Status Register */ + AT91_REG MC_AASR; /* MC Abort Address Status Register */ + AT91_REG Reserved0[ 21 ]; /* */ + AT91_REG MC_FMR; /* MC Flash Mode Register */ + AT91_REG MC_FCR; /* MC Flash Command Register */ + AT91_REG MC_FSR; /* MC Flash Status Register */ +} AT91S_MC, * AT91PS_MC; -// -------- MC_RCR : (MC Offset: 0x0) MC Remap Control Register -------- -#define AT91C_MC_RCB ((unsigned int) 0x1 << 0) // (MC) Remap Command Bit -// -------- MC_ASR : (MC Offset: 0x4) MC Abort Status Register -------- -#define AT91C_MC_UNDADD ((unsigned int) 0x1 << 0) // (MC) Undefined Addess Abort Status -#define AT91C_MC_MISADD ((unsigned int) 0x1 << 1) // (MC) Misaligned Addess Abort Status -#define AT91C_MC_ABTSZ ((unsigned int) 0x3 << 8) // (MC) Abort Size Status -#define AT91C_MC_ABTSZ_BYTE ((unsigned int) 0x0 << 8) // (MC) Byte -#define AT91C_MC_ABTSZ_HWORD ((unsigned int) 0x1 << 8) // (MC) Half-word -#define AT91C_MC_ABTSZ_WORD ((unsigned int) 0x2 << 8) // (MC) Word -#define AT91C_MC_ABTTYP ((unsigned int) 0x3 << 10) // (MC) Abort Type Status -#define AT91C_MC_ABTTYP_DATAR ((unsigned int) 0x0 << 10) // (MC) Data Read -#define AT91C_MC_ABTTYP_DATAW ((unsigned int) 0x1 << 10) // (MC) Data Write -#define AT91C_MC_ABTTYP_FETCH ((unsigned int) 0x2 << 10) // (MC) Code Fetch -#define AT91C_MC_MST0 ((unsigned int) 0x1 << 16) // (MC) Master 0 Abort Source -#define AT91C_MC_MST1 ((unsigned int) 0x1 << 17) // (MC) Master 1 Abort Source -#define AT91C_MC_SVMST0 ((unsigned int) 0x1 << 24) // (MC) Saved Master 0 Abort Source -#define AT91C_MC_SVMST1 ((unsigned int) 0x1 << 25) // (MC) Saved Master 1 Abort Source -// -------- MC_FMR : (MC Offset: 0x60) MC Flash Mode Register -------- -#define AT91C_MC_FRDY ((unsigned int) 0x1 << 0) // (MC) Flash Ready -#define AT91C_MC_LOCKE ((unsigned int) 0x1 << 2) // (MC) Lock Error -#define AT91C_MC_PROGE ((unsigned int) 0x1 << 3) // (MC) Programming Error -#define AT91C_MC_NEBP ((unsigned int) 0x1 << 7) // (MC) No Erase Before Programming -#define AT91C_MC_FWS ((unsigned int) 0x3 << 8) // (MC) Flash Wait State -#define AT91C_MC_FWS_0FWS ((unsigned int) 0x0 << 8) // (MC) 1 cycle for Read, 2 for Write operations -#define AT91C_MC_FWS_1FWS ((unsigned int) 0x1 << 8) // (MC) 2 cycles for Read, 3 for Write operations -#define AT91C_MC_FWS_2FWS ((unsigned int) 0x2 << 8) // (MC) 3 cycles for Read, 4 for Write operations -#define AT91C_MC_FWS_3FWS ((unsigned int) 0x3 << 8) // (MC) 4 cycles for Read, 4 for Write operations -#define AT91C_MC_FMCN ((unsigned int) 0xFF << 16) // (MC) Flash Microsecond Cycle Number -// -------- MC_FCR : (MC Offset: 0x64) MC Flash Command Register -------- -#define AT91C_MC_FCMD ((unsigned int) 0xF << 0) // (MC) Flash Command -#define AT91C_MC_FCMD_START_PROG ((unsigned int) 0x1) // (MC) Starts the programming of th epage specified by PAGEN. -#define AT91C_MC_FCMD_LOCK ((unsigned int) 0x2) // (MC) Starts a lock sequence of the sector defined by the bits 4 to 7 of the field PAGEN. -#define AT91C_MC_FCMD_PROG_AND_LOCK ((unsigned int) 0x3) // (MC) The lock sequence automatically happens after the programming sequence is completed. -#define AT91C_MC_FCMD_UNLOCK ((unsigned int) 0x4) // (MC) Starts an unlock sequence of the sector defined by the bits 4 to 7 of the field PAGEN. -#define AT91C_MC_FCMD_ERASE_ALL ((unsigned int) 0x8) // (MC) Starts the erase of the entire flash.If at least a page is locked, the command is cancelled. -#define AT91C_MC_FCMD_SET_GP_NVM ((unsigned int) 0xB) // (MC) Set General Purpose NVM bits. -#define AT91C_MC_FCMD_CLR_GP_NVM ((unsigned int) 0xD) // (MC) Clear General Purpose NVM bits. -#define AT91C_MC_FCMD_SET_SECURITY ((unsigned int) 0xF) // (MC) Set Security Bit. -#define AT91C_MC_PAGEN ((unsigned int) 0x3FF << 8) // (MC) Page Number -#define AT91C_MC_KEY ((unsigned int) 0xFF << 24) // (MC) Writing Protect Key -// -------- MC_FSR : (MC Offset: 0x68) MC Flash Command Register -------- -#define AT91C_MC_SECURITY ((unsigned int) 0x1 << 4) // (MC) Security Bit Status -#define AT91C_MC_GPNVM0 ((unsigned int) 0x1 << 8) // (MC) Sector 0 Lock Status -#define AT91C_MC_GPNVM1 ((unsigned int) 0x1 << 9) // (MC) Sector 1 Lock Status -#define AT91C_MC_GPNVM2 ((unsigned int) 0x1 << 10) // (MC) Sector 2 Lock Status -#define AT91C_MC_GPNVM3 ((unsigned int) 0x1 << 11) // (MC) Sector 3 Lock Status -#define AT91C_MC_GPNVM4 ((unsigned int) 0x1 << 12) // (MC) Sector 4 Lock Status -#define AT91C_MC_GPNVM5 ((unsigned int) 0x1 << 13) // (MC) Sector 5 Lock Status -#define AT91C_MC_GPNVM6 ((unsigned int) 0x1 << 14) // (MC) Sector 6 Lock Status -#define AT91C_MC_GPNVM7 ((unsigned int) 0x1 << 15) // (MC) Sector 7 Lock Status -#define AT91C_MC_LOCKS0 ((unsigned int) 0x1 << 16) // (MC) Sector 0 Lock Status -#define AT91C_MC_LOCKS1 ((unsigned int) 0x1 << 17) // (MC) Sector 1 Lock Status -#define AT91C_MC_LOCKS2 ((unsigned int) 0x1 << 18) // (MC) Sector 2 Lock Status -#define AT91C_MC_LOCKS3 ((unsigned int) 0x1 << 19) // (MC) Sector 3 Lock Status -#define AT91C_MC_LOCKS4 ((unsigned int) 0x1 << 20) // (MC) Sector 4 Lock Status -#define AT91C_MC_LOCKS5 ((unsigned int) 0x1 << 21) // (MC) Sector 5 Lock Status -#define AT91C_MC_LOCKS6 ((unsigned int) 0x1 << 22) // (MC) Sector 6 Lock Status -#define AT91C_MC_LOCKS7 ((unsigned int) 0x1 << 23) // (MC) Sector 7 Lock Status -#define AT91C_MC_LOCKS8 ((unsigned int) 0x1 << 24) // (MC) Sector 8 Lock Status -#define AT91C_MC_LOCKS9 ((unsigned int) 0x1 << 25) // (MC) Sector 9 Lock Status -#define AT91C_MC_LOCKS10 ((unsigned int) 0x1 << 26) // (MC) Sector 10 Lock Status -#define AT91C_MC_LOCKS11 ((unsigned int) 0x1 << 27) // (MC) Sector 11 Lock Status -#define AT91C_MC_LOCKS12 ((unsigned int) 0x1 << 28) // (MC) Sector 12 Lock Status -#define AT91C_MC_LOCKS13 ((unsigned int) 0x1 << 29) // (MC) Sector 13 Lock Status -#define AT91C_MC_LOCKS14 ((unsigned int) 0x1 << 30) // (MC) Sector 14 Lock Status -#define AT91C_MC_LOCKS15 ((unsigned int) 0x1 << 31) // (MC) Sector 15 Lock Status +/* -------- MC_RCR : (MC Offset: 0x0) MC Remap Control Register -------- */ +#define AT91C_MC_RCB ( ( unsigned int ) 0x1 << 0 ) /* (MC) Remap Command Bit */ +/* -------- MC_ASR : (MC Offset: 0x4) MC Abort Status Register -------- */ +#define AT91C_MC_UNDADD ( ( unsigned int ) 0x1 << 0 ) /* (MC) Undefined Addess Abort Status */ +#define AT91C_MC_MISADD ( ( unsigned int ) 0x1 << 1 ) /* (MC) Misaligned Addess Abort Status */ +#define AT91C_MC_ABTSZ ( ( unsigned int ) 0x3 << 8 ) /* (MC) Abort Size Status */ +#define AT91C_MC_ABTSZ_BYTE ( ( unsigned int ) 0x0 << 8 ) /* (MC) Byte */ +#define AT91C_MC_ABTSZ_HWORD ( ( unsigned int ) 0x1 << 8 ) /* (MC) Half-word */ +#define AT91C_MC_ABTSZ_WORD ( ( unsigned int ) 0x2 << 8 ) /* (MC) Word */ +#define AT91C_MC_ABTTYP ( ( unsigned int ) 0x3 << 10 ) /* (MC) Abort Type Status */ +#define AT91C_MC_ABTTYP_DATAR ( ( unsigned int ) 0x0 << 10 ) /* (MC) Data Read */ +#define AT91C_MC_ABTTYP_DATAW ( ( unsigned int ) 0x1 << 10 ) /* (MC) Data Write */ +#define AT91C_MC_ABTTYP_FETCH ( ( unsigned int ) 0x2 << 10 ) /* (MC) Code Fetch */ +#define AT91C_MC_MST0 ( ( unsigned int ) 0x1 << 16 ) /* (MC) Master 0 Abort Source */ +#define AT91C_MC_MST1 ( ( unsigned int ) 0x1 << 17 ) /* (MC) Master 1 Abort Source */ +#define AT91C_MC_SVMST0 ( ( unsigned int ) 0x1 << 24 ) /* (MC) Saved Master 0 Abort Source */ +#define AT91C_MC_SVMST1 ( ( unsigned int ) 0x1 << 25 ) /* (MC) Saved Master 1 Abort Source */ +/* -------- MC_FMR : (MC Offset: 0x60) MC Flash Mode Register -------- */ +#define AT91C_MC_FRDY ( ( unsigned int ) 0x1 << 0 ) /* (MC) Flash Ready */ +#define AT91C_MC_LOCKE ( ( unsigned int ) 0x1 << 2 ) /* (MC) Lock Error */ +#define AT91C_MC_PROGE ( ( unsigned int ) 0x1 << 3 ) /* (MC) Programming Error */ +#define AT91C_MC_NEBP ( ( unsigned int ) 0x1 << 7 ) /* (MC) No Erase Before Programming */ +#define AT91C_MC_FWS ( ( unsigned int ) 0x3 << 8 ) /* (MC) Flash Wait State */ +#define AT91C_MC_FWS_0FWS ( ( unsigned int ) 0x0 << 8 ) /* (MC) 1 cycle for Read, 2 for Write operations */ +#define AT91C_MC_FWS_1FWS ( ( unsigned int ) 0x1 << 8 ) /* (MC) 2 cycles for Read, 3 for Write operations */ +#define AT91C_MC_FWS_2FWS ( ( unsigned int ) 0x2 << 8 ) /* (MC) 3 cycles for Read, 4 for Write operations */ +#define AT91C_MC_FWS_3FWS ( ( unsigned int ) 0x3 << 8 ) /* (MC) 4 cycles for Read, 4 for Write operations */ +#define AT91C_MC_FMCN ( ( unsigned int ) 0xFF << 16 ) /* (MC) Flash Microsecond Cycle Number */ +/* -------- MC_FCR : (MC Offset: 0x64) MC Flash Command Register -------- */ +#define AT91C_MC_FCMD ( ( unsigned int ) 0xF << 0 ) /* (MC) Flash Command */ +#define AT91C_MC_FCMD_START_PROG ( ( unsigned int ) 0x1 ) /* (MC) Starts the programming of th epage specified by PAGEN. */ +#define AT91C_MC_FCMD_LOCK ( ( unsigned int ) 0x2 ) /* (MC) Starts a lock sequence of the sector defined by the bits 4 to 7 of the field PAGEN. */ +#define AT91C_MC_FCMD_PROG_AND_LOCK ( ( unsigned int ) 0x3 ) /* (MC) The lock sequence automatically happens after the programming sequence is completed. */ +#define AT91C_MC_FCMD_UNLOCK ( ( unsigned int ) 0x4 ) /* (MC) Starts an unlock sequence of the sector defined by the bits 4 to 7 of the field PAGEN. */ +#define AT91C_MC_FCMD_ERASE_ALL ( ( unsigned int ) 0x8 ) /* (MC) Starts the erase of the entire flash.If at least a page is locked, the command is cancelled. */ +#define AT91C_MC_FCMD_SET_GP_NVM ( ( unsigned int ) 0xB ) /* (MC) Set General Purpose NVM bits. */ +#define AT91C_MC_FCMD_CLR_GP_NVM ( ( unsigned int ) 0xD ) /* (MC) Clear General Purpose NVM bits. */ +#define AT91C_MC_FCMD_SET_SECURITY ( ( unsigned int ) 0xF ) /* (MC) Set Security Bit. */ +#define AT91C_MC_PAGEN ( ( unsigned int ) 0x3FF << 8 ) /* (MC) Page Number */ +#define AT91C_MC_KEY ( ( unsigned int ) 0xFF << 24 ) /* (MC) Writing Protect Key */ +/* -------- MC_FSR : (MC Offset: 0x68) MC Flash Command Register -------- */ +#define AT91C_MC_SECURITY ( ( unsigned int ) 0x1 << 4 ) /* (MC) Security Bit Status */ +#define AT91C_MC_GPNVM0 ( ( unsigned int ) 0x1 << 8 ) /* (MC) Sector 0 Lock Status */ +#define AT91C_MC_GPNVM1 ( ( unsigned int ) 0x1 << 9 ) /* (MC) Sector 1 Lock Status */ +#define AT91C_MC_GPNVM2 ( ( unsigned int ) 0x1 << 10 ) /* (MC) Sector 2 Lock Status */ +#define AT91C_MC_GPNVM3 ( ( unsigned int ) 0x1 << 11 ) /* (MC) Sector 3 Lock Status */ +#define AT91C_MC_GPNVM4 ( ( unsigned int ) 0x1 << 12 ) /* (MC) Sector 4 Lock Status */ +#define AT91C_MC_GPNVM5 ( ( unsigned int ) 0x1 << 13 ) /* (MC) Sector 5 Lock Status */ +#define AT91C_MC_GPNVM6 ( ( unsigned int ) 0x1 << 14 ) /* (MC) Sector 6 Lock Status */ +#define AT91C_MC_GPNVM7 ( ( unsigned int ) 0x1 << 15 ) /* (MC) Sector 7 Lock Status */ +#define AT91C_MC_LOCKS0 ( ( unsigned int ) 0x1 << 16 ) /* (MC) Sector 0 Lock Status */ +#define AT91C_MC_LOCKS1 ( ( unsigned int ) 0x1 << 17 ) /* (MC) Sector 1 Lock Status */ +#define AT91C_MC_LOCKS2 ( ( unsigned int ) 0x1 << 18 ) /* (MC) Sector 2 Lock Status */ +#define AT91C_MC_LOCKS3 ( ( unsigned int ) 0x1 << 19 ) /* (MC) Sector 3 Lock Status */ +#define AT91C_MC_LOCKS4 ( ( unsigned int ) 0x1 << 20 ) /* (MC) Sector 4 Lock Status */ +#define AT91C_MC_LOCKS5 ( ( unsigned int ) 0x1 << 21 ) /* (MC) Sector 5 Lock Status */ +#define AT91C_MC_LOCKS6 ( ( unsigned int ) 0x1 << 22 ) /* (MC) Sector 6 Lock Status */ +#define AT91C_MC_LOCKS7 ( ( unsigned int ) 0x1 << 23 ) /* (MC) Sector 7 Lock Status */ +#define AT91C_MC_LOCKS8 ( ( unsigned int ) 0x1 << 24 ) /* (MC) Sector 8 Lock Status */ +#define AT91C_MC_LOCKS9 ( ( unsigned int ) 0x1 << 25 ) /* (MC) Sector 9 Lock Status */ +#define AT91C_MC_LOCKS10 ( ( unsigned int ) 0x1 << 26 ) /* (MC) Sector 10 Lock Status */ +#define AT91C_MC_LOCKS11 ( ( unsigned int ) 0x1 << 27 ) /* (MC) Sector 11 Lock Status */ +#define AT91C_MC_LOCKS12 ( ( unsigned int ) 0x1 << 28 ) /* (MC) Sector 12 Lock Status */ +#define AT91C_MC_LOCKS13 ( ( unsigned int ) 0x1 << 29 ) /* (MC) Sector 13 Lock Status */ +#define AT91C_MC_LOCKS14 ( ( unsigned int ) 0x1 << 30 ) /* (MC) Sector 14 Lock Status */ +#define AT91C_MC_LOCKS15 ( ( unsigned int ) 0x1 << 31 ) /* (MC) Sector 15 Lock Status */ -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Serial Parallel Interface -// ***************************************************************************** -typedef struct _AT91S_SPI { - AT91_REG SPI_CR; // Control Register - AT91_REG SPI_MR; // Mode Register - AT91_REG SPI_RDR; // Receive Data Register - AT91_REG SPI_TDR; // Transmit Data Register - AT91_REG SPI_SR; // Status Register - AT91_REG SPI_IER; // Interrupt Enable Register - AT91_REG SPI_IDR; // Interrupt Disable Register - AT91_REG SPI_IMR; // Interrupt Mask Register - AT91_REG Reserved0[4]; // - AT91_REG SPI_CSR[4]; // Chip Select Register - AT91_REG Reserved1[48]; // - AT91_REG SPI_RPR; // Receive Pointer Register - AT91_REG SPI_RCR; // Receive Counter Register - AT91_REG SPI_TPR; // Transmit Pointer Register - AT91_REG SPI_TCR; // Transmit Counter Register - AT91_REG SPI_RNPR; // Receive Next Pointer Register - AT91_REG SPI_RNCR; // Receive Next Counter Register - AT91_REG SPI_TNPR; // Transmit Next Pointer Register - AT91_REG SPI_TNCR; // Transmit Next Counter Register - AT91_REG SPI_PTCR; // PDC Transfer Control Register - AT91_REG SPI_PTSR; // PDC Transfer Status Register -} AT91S_SPI, *AT91PS_SPI; +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR Serial Parallel Interface */ +/* ***************************************************************************** */ +typedef struct _AT91S_SPI +{ + AT91_REG SPI_CR; /* Control Register */ + AT91_REG SPI_MR; /* Mode Register */ + AT91_REG SPI_RDR; /* Receive Data Register */ + AT91_REG SPI_TDR; /* Transmit Data Register */ + AT91_REG SPI_SR; /* Status Register */ + AT91_REG SPI_IER; /* Interrupt Enable Register */ + AT91_REG SPI_IDR; /* Interrupt Disable Register */ + AT91_REG SPI_IMR; /* Interrupt Mask Register */ + AT91_REG Reserved0[ 4 ]; /* */ + AT91_REG SPI_CSR[ 4 ]; /* Chip Select Register */ + AT91_REG Reserved1[ 48 ]; /* */ + AT91_REG SPI_RPR; /* Receive Pointer Register */ + AT91_REG SPI_RCR; /* Receive Counter Register */ + AT91_REG SPI_TPR; /* Transmit Pointer Register */ + AT91_REG SPI_TCR; /* Transmit Counter Register */ + AT91_REG SPI_RNPR; /* Receive Next Pointer Register */ + AT91_REG SPI_RNCR; /* Receive Next Counter Register */ + AT91_REG SPI_TNPR; /* Transmit Next Pointer Register */ + AT91_REG SPI_TNCR; /* Transmit Next Counter Register */ + AT91_REG SPI_PTCR; /* PDC Transfer Control Register */ + AT91_REG SPI_PTSR; /* PDC Transfer Status Register */ +} AT91S_SPI, * AT91PS_SPI; -// -------- SPI_CR : (SPI Offset: 0x0) SPI Control Register -------- -#define AT91C_SPI_SPIEN ((unsigned int) 0x1 << 0) // (SPI) SPI Enable -#define AT91C_SPI_SPIDIS ((unsigned int) 0x1 << 1) // (SPI) SPI Disable -#define AT91C_SPI_SWRST ((unsigned int) 0x1 << 7) // (SPI) SPI Software reset -#define AT91C_SPI_LASTXFER ((unsigned int) 0x1 << 24) // (SPI) SPI Last Transfer -// -------- SPI_MR : (SPI Offset: 0x4) SPI Mode Register -------- -#define AT91C_SPI_MSTR ((unsigned int) 0x1 << 0) // (SPI) Master/Slave Mode -#define AT91C_SPI_PS ((unsigned int) 0x1 << 1) // (SPI) Peripheral Select -#define AT91C_SPI_PS_FIXED ((unsigned int) 0x0 << 1) // (SPI) Fixed Peripheral Select -#define AT91C_SPI_PS_VARIABLE ((unsigned int) 0x1 << 1) // (SPI) Variable Peripheral Select -#define AT91C_SPI_PCSDEC ((unsigned int) 0x1 << 2) // (SPI) Chip Select Decode -#define AT91C_SPI_FDIV ((unsigned int) 0x1 << 3) // (SPI) Clock Selection -#define AT91C_SPI_MODFDIS ((unsigned int) 0x1 << 4) // (SPI) Mode Fault Detection -#define AT91C_SPI_LLB ((unsigned int) 0x1 << 7) // (SPI) Clock Selection -#define AT91C_SPI_PCS ((unsigned int) 0xF << 16) // (SPI) Peripheral Chip Select -#define AT91C_SPI_DLYBCS ((unsigned int) 0xFF << 24) // (SPI) Delay Between Chip Selects -// -------- SPI_RDR : (SPI Offset: 0x8) Receive Data Register -------- -#define AT91C_SPI_RD ((unsigned int) 0xFFFF << 0) // (SPI) Receive Data -#define AT91C_SPI_RPCS ((unsigned int) 0xF << 16) // (SPI) Peripheral Chip Select Status -// -------- SPI_TDR : (SPI Offset: 0xc) Transmit Data Register -------- -#define AT91C_SPI_TD ((unsigned int) 0xFFFF << 0) // (SPI) Transmit Data -#define AT91C_SPI_TPCS ((unsigned int) 0xF << 16) // (SPI) Peripheral Chip Select Status -// -------- SPI_SR : (SPI Offset: 0x10) Status Register -------- -#define AT91C_SPI_RDRF ((unsigned int) 0x1 << 0) // (SPI) Receive Data Register Full -#define AT91C_SPI_TDRE ((unsigned int) 0x1 << 1) // (SPI) Transmit Data Register Empty -#define AT91C_SPI_MODF ((unsigned int) 0x1 << 2) // (SPI) Mode Fault Error -#define AT91C_SPI_OVRES ((unsigned int) 0x1 << 3) // (SPI) Overrun Error Status -#define AT91C_SPI_ENDRX ((unsigned int) 0x1 << 4) // (SPI) End of Receiver Transfer -#define AT91C_SPI_ENDTX ((unsigned int) 0x1 << 5) // (SPI) End of Receiver Transfer -#define AT91C_SPI_RXBUFF ((unsigned int) 0x1 << 6) // (SPI) RXBUFF Interrupt -#define AT91C_SPI_TXBUFE ((unsigned int) 0x1 << 7) // (SPI) TXBUFE Interrupt -#define AT91C_SPI_NSSR ((unsigned int) 0x1 << 8) // (SPI) NSSR Interrupt -#define AT91C_SPI_TXEMPTY ((unsigned int) 0x1 << 9) // (SPI) TXEMPTY Interrupt -#define AT91C_SPI_SPIENS ((unsigned int) 0x1 << 16) // (SPI) Enable Status -// -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register -------- -// -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register -------- -// -------- SPI_IMR : (SPI Offset: 0x1c) Interrupt Mask Register -------- -// -------- SPI_CSR : (SPI Offset: 0x30) Chip Select Register -------- -#define AT91C_SPI_CPOL ((unsigned int) 0x1 << 0) // (SPI) Clock Polarity -#define AT91C_SPI_NCPHA ((unsigned int) 0x1 << 1) // (SPI) Clock Phase -#define AT91C_SPI_CSAAT ((unsigned int) 0x1 << 3) // (SPI) Chip Select Active After Transfer -#define AT91C_SPI_BITS ((unsigned int) 0xF << 4) // (SPI) Bits Per Transfer -#define AT91C_SPI_BITS_8 ((unsigned int) 0x0 << 4) // (SPI) 8 Bits Per transfer -#define AT91C_SPI_BITS_9 ((unsigned int) 0x1 << 4) // (SPI) 9 Bits Per transfer -#define AT91C_SPI_BITS_10 ((unsigned int) 0x2 << 4) // (SPI) 10 Bits Per transfer -#define AT91C_SPI_BITS_11 ((unsigned int) 0x3 << 4) // (SPI) 11 Bits Per transfer -#define AT91C_SPI_BITS_12 ((unsigned int) 0x4 << 4) // (SPI) 12 Bits Per transfer -#define AT91C_SPI_BITS_13 ((unsigned int) 0x5 << 4) // (SPI) 13 Bits Per transfer -#define AT91C_SPI_BITS_14 ((unsigned int) 0x6 << 4) // (SPI) 14 Bits Per transfer -#define AT91C_SPI_BITS_15 ((unsigned int) 0x7 << 4) // (SPI) 15 Bits Per transfer -#define AT91C_SPI_BITS_16 ((unsigned int) 0x8 << 4) // (SPI) 16 Bits Per transfer -#define AT91C_SPI_SCBR ((unsigned int) 0xFF << 8) // (SPI) Serial Clock Baud Rate -#define AT91C_SPI_DLYBS ((unsigned int) 0xFF << 16) // (SPI) Delay Before SPCK -#define AT91C_SPI_DLYBCT ((unsigned int) 0xFF << 24) // (SPI) Delay Between Consecutive Transfers +/* -------- SPI_CR : (SPI Offset: 0x0) SPI Control Register -------- */ +#define AT91C_SPI_SPIEN ( ( unsigned int ) 0x1 << 0 ) /* (SPI) SPI Enable */ +#define AT91C_SPI_SPIDIS ( ( unsigned int ) 0x1 << 1 ) /* (SPI) SPI Disable */ +#define AT91C_SPI_SWRST ( ( unsigned int ) 0x1 << 7 ) /* (SPI) SPI Software reset */ +#define AT91C_SPI_LASTXFER ( ( unsigned int ) 0x1 << 24 ) /* (SPI) SPI Last Transfer */ +/* -------- SPI_MR : (SPI Offset: 0x4) SPI Mode Register -------- */ +#define AT91C_SPI_MSTR ( ( unsigned int ) 0x1 << 0 ) /* (SPI) Master/Slave Mode */ +#define AT91C_SPI_PS ( ( unsigned int ) 0x1 << 1 ) /* (SPI) Peripheral Select */ +#define AT91C_SPI_PS_FIXED ( ( unsigned int ) 0x0 << 1 ) /* (SPI) Fixed Peripheral Select */ +#define AT91C_SPI_PS_VARIABLE ( ( unsigned int ) 0x1 << 1 ) /* (SPI) Variable Peripheral Select */ +#define AT91C_SPI_PCSDEC ( ( unsigned int ) 0x1 << 2 ) /* (SPI) Chip Select Decode */ +#define AT91C_SPI_FDIV ( ( unsigned int ) 0x1 << 3 ) /* (SPI) Clock Selection */ +#define AT91C_SPI_MODFDIS ( ( unsigned int ) 0x1 << 4 ) /* (SPI) Mode Fault Detection */ +#define AT91C_SPI_LLB ( ( unsigned int ) 0x1 << 7 ) /* (SPI) Clock Selection */ +#define AT91C_SPI_PCS ( ( unsigned int ) 0xF << 16 ) /* (SPI) Peripheral Chip Select */ +#define AT91C_SPI_DLYBCS ( ( unsigned int ) 0xFF << 24 ) /* (SPI) Delay Between Chip Selects */ +/* -------- SPI_RDR : (SPI Offset: 0x8) Receive Data Register -------- */ +#define AT91C_SPI_RD ( ( unsigned int ) 0xFFFF << 0 ) /* (SPI) Receive Data */ +#define AT91C_SPI_RPCS ( ( unsigned int ) 0xF << 16 ) /* (SPI) Peripheral Chip Select Status */ +/* -------- SPI_TDR : (SPI Offset: 0xc) Transmit Data Register -------- */ +#define AT91C_SPI_TD ( ( unsigned int ) 0xFFFF << 0 ) /* (SPI) Transmit Data */ +#define AT91C_SPI_TPCS ( ( unsigned int ) 0xF << 16 ) /* (SPI) Peripheral Chip Select Status */ +/* -------- SPI_SR : (SPI Offset: 0x10) Status Register -------- */ +#define AT91C_SPI_RDRF ( ( unsigned int ) 0x1 << 0 ) /* (SPI) Receive Data Register Full */ +#define AT91C_SPI_TDRE ( ( unsigned int ) 0x1 << 1 ) /* (SPI) Transmit Data Register Empty */ +#define AT91C_SPI_MODF ( ( unsigned int ) 0x1 << 2 ) /* (SPI) Mode Fault Error */ +#define AT91C_SPI_OVRES ( ( unsigned int ) 0x1 << 3 ) /* (SPI) Overrun Error Status */ +#define AT91C_SPI_ENDRX ( ( unsigned int ) 0x1 << 4 ) /* (SPI) End of Receiver Transfer */ +#define AT91C_SPI_ENDTX ( ( unsigned int ) 0x1 << 5 ) /* (SPI) End of Receiver Transfer */ +#define AT91C_SPI_RXBUFF ( ( unsigned int ) 0x1 << 6 ) /* (SPI) RXBUFF Interrupt */ +#define AT91C_SPI_TXBUFE ( ( unsigned int ) 0x1 << 7 ) /* (SPI) TXBUFE Interrupt */ +#define AT91C_SPI_NSSR ( ( unsigned int ) 0x1 << 8 ) /* (SPI) NSSR Interrupt */ +#define AT91C_SPI_TXEMPTY ( ( unsigned int ) 0x1 << 9 ) /* (SPI) TXEMPTY Interrupt */ +#define AT91C_SPI_SPIENS ( ( unsigned int ) 0x1 << 16 ) /* (SPI) Enable Status */ +/* -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register -------- */ +/* -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register -------- */ +/* -------- SPI_IMR : (SPI Offset: 0x1c) Interrupt Mask Register -------- */ +/* -------- SPI_CSR : (SPI Offset: 0x30) Chip Select Register -------- */ +#define AT91C_SPI_CPOL ( ( unsigned int ) 0x1 << 0 ) /* (SPI) Clock Polarity */ +#define AT91C_SPI_NCPHA ( ( unsigned int ) 0x1 << 1 ) /* (SPI) Clock Phase */ +#define AT91C_SPI_CSAAT ( ( unsigned int ) 0x1 << 3 ) /* (SPI) Chip Select Active After Transfer */ +#define AT91C_SPI_BITS ( ( unsigned int ) 0xF << 4 ) /* (SPI) Bits Per Transfer */ +#define AT91C_SPI_BITS_8 ( ( unsigned int ) 0x0 << 4 ) /* (SPI) 8 Bits Per transfer */ +#define AT91C_SPI_BITS_9 ( ( unsigned int ) 0x1 << 4 ) /* (SPI) 9 Bits Per transfer */ +#define AT91C_SPI_BITS_10 ( ( unsigned int ) 0x2 << 4 ) /* (SPI) 10 Bits Per transfer */ +#define AT91C_SPI_BITS_11 ( ( unsigned int ) 0x3 << 4 ) /* (SPI) 11 Bits Per transfer */ +#define AT91C_SPI_BITS_12 ( ( unsigned int ) 0x4 << 4 ) /* (SPI) 12 Bits Per transfer */ +#define AT91C_SPI_BITS_13 ( ( unsigned int ) 0x5 << 4 ) /* (SPI) 13 Bits Per transfer */ +#define AT91C_SPI_BITS_14 ( ( unsigned int ) 0x6 << 4 ) /* (SPI) 14 Bits Per transfer */ +#define AT91C_SPI_BITS_15 ( ( unsigned int ) 0x7 << 4 ) /* (SPI) 15 Bits Per transfer */ +#define AT91C_SPI_BITS_16 ( ( unsigned int ) 0x8 << 4 ) /* (SPI) 16 Bits Per transfer */ +#define AT91C_SPI_SCBR ( ( unsigned int ) 0xFF << 8 ) /* (SPI) Serial Clock Baud Rate */ +#define AT91C_SPI_DLYBS ( ( unsigned int ) 0xFF << 16 ) /* (SPI) Delay Before SPCK */ +#define AT91C_SPI_DLYBCT ( ( unsigned int ) 0xFF << 24 ) /* (SPI) Delay Between Consecutive Transfers */ -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Usart -// ***************************************************************************** -typedef struct _AT91S_USART { - AT91_REG US_CR; // Control Register - AT91_REG US_MR; // Mode Register - AT91_REG US_IER; // Interrupt Enable Register - AT91_REG US_IDR; // Interrupt Disable Register - AT91_REG US_IMR; // Interrupt Mask Register - AT91_REG US_CSR; // Channel Status Register - AT91_REG US_RHR; // Receiver Holding Register - AT91_REG US_THR; // Transmitter Holding Register - AT91_REG US_BRGR; // Baud Rate Generator Register - AT91_REG US_RTOR; // Receiver Time-out Register - AT91_REG US_TTGR; // Transmitter Time-guard Register - AT91_REG Reserved0[5]; // - AT91_REG US_FIDI; // FI_DI_Ratio Register - AT91_REG US_NER; // Nb Errors Register - AT91_REG Reserved1[1]; // - AT91_REG US_IF; // IRDA_FILTER Register - AT91_REG Reserved2[44]; // - AT91_REG US_RPR; // Receive Pointer Register - AT91_REG US_RCR; // Receive Counter Register - AT91_REG US_TPR; // Transmit Pointer Register - AT91_REG US_TCR; // Transmit Counter Register - AT91_REG US_RNPR; // Receive Next Pointer Register - AT91_REG US_RNCR; // Receive Next Counter Register - AT91_REG US_TNPR; // Transmit Next Pointer Register - AT91_REG US_TNCR; // Transmit Next Counter Register - AT91_REG US_PTCR; // PDC Transfer Control Register - AT91_REG US_PTSR; // PDC Transfer Status Register -} AT91S_USART, *AT91PS_USART; +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR Usart */ +/* ***************************************************************************** */ +typedef struct _AT91S_USART +{ + AT91_REG US_CR; /* Control Register */ + AT91_REG US_MR; /* Mode Register */ + AT91_REG US_IER; /* Interrupt Enable Register */ + AT91_REG US_IDR; /* Interrupt Disable Register */ + AT91_REG US_IMR; /* Interrupt Mask Register */ + AT91_REG US_CSR; /* Channel Status Register */ + AT91_REG US_RHR; /* Receiver Holding Register */ + AT91_REG US_THR; /* Transmitter Holding Register */ + AT91_REG US_BRGR; /* Baud Rate Generator Register */ + AT91_REG US_RTOR; /* Receiver Time-out Register */ + AT91_REG US_TTGR; /* Transmitter Time-guard Register */ + AT91_REG Reserved0[ 5 ]; /* */ + AT91_REG US_FIDI; /* FI_DI_Ratio Register */ + AT91_REG US_NER; /* Nb Errors Register */ + AT91_REG Reserved1[ 1 ]; /* */ + AT91_REG US_IF; /* IRDA_FILTER Register */ + AT91_REG Reserved2[ 44 ]; /* */ + AT91_REG US_RPR; /* Receive Pointer Register */ + AT91_REG US_RCR; /* Receive Counter Register */ + AT91_REG US_TPR; /* Transmit Pointer Register */ + AT91_REG US_TCR; /* Transmit Counter Register */ + AT91_REG US_RNPR; /* Receive Next Pointer Register */ + AT91_REG US_RNCR; /* Receive Next Counter Register */ + AT91_REG US_TNPR; /* Transmit Next Pointer Register */ + AT91_REG US_TNCR; /* Transmit Next Counter Register */ + AT91_REG US_PTCR; /* PDC Transfer Control Register */ + AT91_REG US_PTSR; /* PDC Transfer Status Register */ +} AT91S_USART, * AT91PS_USART; -// -------- US_CR : (USART Offset: 0x0) Debug Unit Control Register -------- -#define AT91C_US_STTBRK ((unsigned int) 0x1 << 9) // (USART) Start Break -#define AT91C_US_STPBRK ((unsigned int) 0x1 << 10) // (USART) Stop Break -#define AT91C_US_STTTO ((unsigned int) 0x1 << 11) // (USART) Start Time-out -#define AT91C_US_SENDA ((unsigned int) 0x1 << 12) // (USART) Send Address -#define AT91C_US_RSTIT ((unsigned int) 0x1 << 13) // (USART) Reset Iterations -#define AT91C_US_RSTNACK ((unsigned int) 0x1 << 14) // (USART) Reset Non Acknowledge -#define AT91C_US_RETTO ((unsigned int) 0x1 << 15) // (USART) Rearm Time-out -#define AT91C_US_DTREN ((unsigned int) 0x1 << 16) // (USART) Data Terminal ready Enable -#define AT91C_US_DTRDIS ((unsigned int) 0x1 << 17) // (USART) Data Terminal ready Disable -#define AT91C_US_RTSEN ((unsigned int) 0x1 << 18) // (USART) Request to Send enable -#define AT91C_US_RTSDIS ((unsigned int) 0x1 << 19) // (USART) Request to Send Disable -// -------- US_MR : (USART Offset: 0x4) Debug Unit Mode Register -------- -#define AT91C_US_USMODE ((unsigned int) 0xF << 0) // (USART) Usart mode -#define AT91C_US_USMODE_NORMAL ((unsigned int) 0x0) // (USART) Normal -#define AT91C_US_USMODE_RS485 ((unsigned int) 0x1) // (USART) RS485 -#define AT91C_US_USMODE_HWHSH ((unsigned int) 0x2) // (USART) Hardware Handshaking -#define AT91C_US_USMODE_MODEM ((unsigned int) 0x3) // (USART) Modem -#define AT91C_US_USMODE_ISO7816_0 ((unsigned int) 0x4) // (USART) ISO7816 protocol: T = 0 -#define AT91C_US_USMODE_ISO7816_1 ((unsigned int) 0x6) // (USART) ISO7816 protocol: T = 1 -#define AT91C_US_USMODE_IRDA ((unsigned int) 0x8) // (USART) IrDA -#define AT91C_US_USMODE_SWHSH ((unsigned int) 0xC) // (USART) Software Handshaking -#define AT91C_US_CLKS ((unsigned int) 0x3 << 4) // (USART) Clock Selection (Baud Rate generator Input Clock -#define AT91C_US_CLKS_CLOCK ((unsigned int) 0x0 << 4) // (USART) Clock -#define AT91C_US_CLKS_FDIV1 ((unsigned int) 0x1 << 4) // (USART) fdiv1 -#define AT91C_US_CLKS_SLOW ((unsigned int) 0x2 << 4) // (USART) slow_clock (ARM) -#define AT91C_US_CLKS_EXT ((unsigned int) 0x3 << 4) // (USART) External (SCK) -#define AT91C_US_CHRL ((unsigned int) 0x3 << 6) // (USART) Clock Selection (Baud Rate generator Input Clock -#define AT91C_US_CHRL_5_BITS ((unsigned int) 0x0 << 6) // (USART) Character Length: 5 bits -#define AT91C_US_CHRL_6_BITS ((unsigned int) 0x1 << 6) // (USART) Character Length: 6 bits -#define AT91C_US_CHRL_7_BITS ((unsigned int) 0x2 << 6) // (USART) Character Length: 7 bits -#define AT91C_US_CHRL_8_BITS ((unsigned int) 0x3 << 6) // (USART) Character Length: 8 bits -#define AT91C_US_SYNC ((unsigned int) 0x1 << 8) // (USART) Synchronous Mode Select -#define AT91C_US_NBSTOP ((unsigned int) 0x3 << 12) // (USART) Number of Stop bits -#define AT91C_US_NBSTOP_1_BIT ((unsigned int) 0x0 << 12) // (USART) 1 stop bit -#define AT91C_US_NBSTOP_15_BIT ((unsigned int) 0x1 << 12) // (USART) Asynchronous (SYNC=0) 2 stop bits Synchronous (SYNC=1) 2 stop bits -#define AT91C_US_NBSTOP_2_BIT ((unsigned int) 0x2 << 12) // (USART) 2 stop bits -#define AT91C_US_MSBF ((unsigned int) 0x1 << 16) // (USART) Bit Order -#define AT91C_US_MODE9 ((unsigned int) 0x1 << 17) // (USART) 9-bit Character length -#define AT91C_US_CKLO ((unsigned int) 0x1 << 18) // (USART) Clock Output Select -#define AT91C_US_OVER ((unsigned int) 0x1 << 19) // (USART) Over Sampling Mode -#define AT91C_US_INACK ((unsigned int) 0x1 << 20) // (USART) Inhibit Non Acknowledge -#define AT91C_US_DSNACK ((unsigned int) 0x1 << 21) // (USART) Disable Successive NACK -#define AT91C_US_MAX_ITER ((unsigned int) 0x1 << 24) // (USART) Number of Repetitions -#define AT91C_US_FILTER ((unsigned int) 0x1 << 28) // (USART) Receive Line Filter -// -------- US_IER : (USART Offset: 0x8) Debug Unit Interrupt Enable Register -------- -#define AT91C_US_RXBRK ((unsigned int) 0x1 << 2) // (USART) Break Received/End of Break -#define AT91C_US_TIMEOUT ((unsigned int) 0x1 << 8) // (USART) Receiver Time-out -#define AT91C_US_ITERATION ((unsigned int) 0x1 << 10) // (USART) Max number of Repetitions Reached -#define AT91C_US_NACK ((unsigned int) 0x1 << 13) // (USART) Non Acknowledge -#define AT91C_US_RIIC ((unsigned int) 0x1 << 16) // (USART) Ring INdicator Input Change Flag -#define AT91C_US_DSRIC ((unsigned int) 0x1 << 17) // (USART) Data Set Ready Input Change Flag -#define AT91C_US_DCDIC ((unsigned int) 0x1 << 18) // (USART) Data Carrier Flag -#define AT91C_US_CTSIC ((unsigned int) 0x1 << 19) // (USART) Clear To Send Input Change Flag -// -------- US_IDR : (USART Offset: 0xc) Debug Unit Interrupt Disable Register -------- -// -------- US_IMR : (USART Offset: 0x10) Debug Unit Interrupt Mask Register -------- -// -------- US_CSR : (USART Offset: 0x14) Debug Unit Channel Status Register -------- -#define AT91C_US_RI ((unsigned int) 0x1 << 20) // (USART) Image of RI Input -#define AT91C_US_DSR ((unsigned int) 0x1 << 21) // (USART) Image of DSR Input -#define AT91C_US_DCD ((unsigned int) 0x1 << 22) // (USART) Image of DCD Input -#define AT91C_US_CTS ((unsigned int) 0x1 << 23) // (USART) Image of CTS Input +/* -------- US_CR : (USART Offset: 0x0) Debug Unit Control Register -------- */ +#define AT91C_US_STTBRK ( ( unsigned int ) 0x1 << 9 ) /* (USART) Start Break */ +#define AT91C_US_STPBRK ( ( unsigned int ) 0x1 << 10 ) /* (USART) Stop Break */ +#define AT91C_US_STTTO ( ( unsigned int ) 0x1 << 11 ) /* (USART) Start Time-out */ +#define AT91C_US_SENDA ( ( unsigned int ) 0x1 << 12 ) /* (USART) Send Address */ +#define AT91C_US_RSTIT ( ( unsigned int ) 0x1 << 13 ) /* (USART) Reset Iterations */ +#define AT91C_US_RSTNACK ( ( unsigned int ) 0x1 << 14 ) /* (USART) Reset Non Acknowledge */ +#define AT91C_US_RETTO ( ( unsigned int ) 0x1 << 15 ) /* (USART) Rearm Time-out */ +#define AT91C_US_DTREN ( ( unsigned int ) 0x1 << 16 ) /* (USART) Data Terminal ready Enable */ +#define AT91C_US_DTRDIS ( ( unsigned int ) 0x1 << 17 ) /* (USART) Data Terminal ready Disable */ +#define AT91C_US_RTSEN ( ( unsigned int ) 0x1 << 18 ) /* (USART) Request to Send enable */ +#define AT91C_US_RTSDIS ( ( unsigned int ) 0x1 << 19 ) /* (USART) Request to Send Disable */ +/* -------- US_MR : (USART Offset: 0x4) Debug Unit Mode Register -------- */ +#define AT91C_US_USMODE ( ( unsigned int ) 0xF << 0 ) /* (USART) Usart mode */ +#define AT91C_US_USMODE_NORMAL ( ( unsigned int ) 0x0 ) /* (USART) Normal */ +#define AT91C_US_USMODE_RS485 ( ( unsigned int ) 0x1 ) /* (USART) RS485 */ +#define AT91C_US_USMODE_HWHSH ( ( unsigned int ) 0x2 ) /* (USART) Hardware Handshaking */ +#define AT91C_US_USMODE_MODEM ( ( unsigned int ) 0x3 ) /* (USART) Modem */ +#define AT91C_US_USMODE_ISO7816_0 ( ( unsigned int ) 0x4 ) /* (USART) ISO7816 protocol: T = 0 */ +#define AT91C_US_USMODE_ISO7816_1 ( ( unsigned int ) 0x6 ) /* (USART) ISO7816 protocol: T = 1 */ +#define AT91C_US_USMODE_IRDA ( ( unsigned int ) 0x8 ) /* (USART) IrDA */ +#define AT91C_US_USMODE_SWHSH ( ( unsigned int ) 0xC ) /* (USART) Software Handshaking */ +#define AT91C_US_CLKS ( ( unsigned int ) 0x3 << 4 ) /* (USART) Clock Selection (Baud Rate generator Input Clock */ +#define AT91C_US_CLKS_CLOCK ( ( unsigned int ) 0x0 << 4 ) /* (USART) Clock */ +#define AT91C_US_CLKS_FDIV1 ( ( unsigned int ) 0x1 << 4 ) /* (USART) fdiv1 */ +#define AT91C_US_CLKS_SLOW ( ( unsigned int ) 0x2 << 4 ) /* (USART) slow_clock (ARM) */ +#define AT91C_US_CLKS_EXT ( ( unsigned int ) 0x3 << 4 ) /* (USART) External (SCK) */ +#define AT91C_US_CHRL ( ( unsigned int ) 0x3 << 6 ) /* (USART) Clock Selection (Baud Rate generator Input Clock */ +#define AT91C_US_CHRL_5_BITS ( ( unsigned int ) 0x0 << 6 ) /* (USART) Character Length: 5 bits */ +#define AT91C_US_CHRL_6_BITS ( ( unsigned int ) 0x1 << 6 ) /* (USART) Character Length: 6 bits */ +#define AT91C_US_CHRL_7_BITS ( ( unsigned int ) 0x2 << 6 ) /* (USART) Character Length: 7 bits */ +#define AT91C_US_CHRL_8_BITS ( ( unsigned int ) 0x3 << 6 ) /* (USART) Character Length: 8 bits */ +#define AT91C_US_SYNC ( ( unsigned int ) 0x1 << 8 ) /* (USART) Synchronous Mode Select */ +#define AT91C_US_NBSTOP ( ( unsigned int ) 0x3 << 12 ) /* (USART) Number of Stop bits */ +#define AT91C_US_NBSTOP_1_BIT ( ( unsigned int ) 0x0 << 12 ) /* (USART) 1 stop bit */ +#define AT91C_US_NBSTOP_15_BIT ( ( unsigned int ) 0x1 << 12 ) /* (USART) Asynchronous (SYNC=0) 2 stop bits Synchronous (SYNC=1) 2 stop bits */ +#define AT91C_US_NBSTOP_2_BIT ( ( unsigned int ) 0x2 << 12 ) /* (USART) 2 stop bits */ +#define AT91C_US_MSBF ( ( unsigned int ) 0x1 << 16 ) /* (USART) Bit Order */ +#define AT91C_US_MODE9 ( ( unsigned int ) 0x1 << 17 ) /* (USART) 9-bit Character length */ +#define AT91C_US_CKLO ( ( unsigned int ) 0x1 << 18 ) /* (USART) Clock Output Select */ +#define AT91C_US_OVER ( ( unsigned int ) 0x1 << 19 ) /* (USART) Over Sampling Mode */ +#define AT91C_US_INACK ( ( unsigned int ) 0x1 << 20 ) /* (USART) Inhibit Non Acknowledge */ +#define AT91C_US_DSNACK ( ( unsigned int ) 0x1 << 21 ) /* (USART) Disable Successive NACK */ +#define AT91C_US_MAX_ITER ( ( unsigned int ) 0x1 << 24 ) /* (USART) Number of Repetitions */ +#define AT91C_US_FILTER ( ( unsigned int ) 0x1 << 28 ) /* (USART) Receive Line Filter */ +/* -------- US_IER : (USART Offset: 0x8) Debug Unit Interrupt Enable Register -------- */ +#define AT91C_US_RXBRK ( ( unsigned int ) 0x1 << 2 ) /* (USART) Break Received/End of Break */ +#define AT91C_US_TIMEOUT ( ( unsigned int ) 0x1 << 8 ) /* (USART) Receiver Time-out */ +#define AT91C_US_ITERATION ( ( unsigned int ) 0x1 << 10 ) /* (USART) Max number of Repetitions Reached */ +#define AT91C_US_NACK ( ( unsigned int ) 0x1 << 13 ) /* (USART) Non Acknowledge */ +#define AT91C_US_RIIC ( ( unsigned int ) 0x1 << 16 ) /* (USART) Ring INdicator Input Change Flag */ +#define AT91C_US_DSRIC ( ( unsigned int ) 0x1 << 17 ) /* (USART) Data Set Ready Input Change Flag */ +#define AT91C_US_DCDIC ( ( unsigned int ) 0x1 << 18 ) /* (USART) Data Carrier Flag */ +#define AT91C_US_CTSIC ( ( unsigned int ) 0x1 << 19 ) /* (USART) Clear To Send Input Change Flag */ +/* -------- US_IDR : (USART Offset: 0xc) Debug Unit Interrupt Disable Register -------- */ +/* -------- US_IMR : (USART Offset: 0x10) Debug Unit Interrupt Mask Register -------- */ +/* -------- US_CSR : (USART Offset: 0x14) Debug Unit Channel Status Register -------- */ +#define AT91C_US_RI ( ( unsigned int ) 0x1 << 20 ) /* (USART) Image of RI Input */ +#define AT91C_US_DSR ( ( unsigned int ) 0x1 << 21 ) /* (USART) Image of DSR Input */ +#define AT91C_US_DCD ( ( unsigned int ) 0x1 << 22 ) /* (USART) Image of DCD Input */ +#define AT91C_US_CTS ( ( unsigned int ) 0x1 << 23 ) /* (USART) Image of CTS Input */ -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Synchronous Serial Controller Interface -// ***************************************************************************** -typedef struct _AT91S_SSC { - AT91_REG SSC_CR; // Control Register - AT91_REG SSC_CMR; // Clock Mode Register - AT91_REG Reserved0[2]; // - AT91_REG SSC_RCMR; // Receive Clock ModeRegister - AT91_REG SSC_RFMR; // Receive Frame Mode Register - AT91_REG SSC_TCMR; // Transmit Clock Mode Register - AT91_REG SSC_TFMR; // Transmit Frame Mode Register - AT91_REG SSC_RHR; // Receive Holding Register - AT91_REG SSC_THR; // Transmit Holding Register - AT91_REG Reserved1[2]; // - AT91_REG SSC_RSHR; // Receive Sync Holding Register - AT91_REG SSC_TSHR; // Transmit Sync Holding Register - AT91_REG Reserved2[2]; // - AT91_REG SSC_SR; // Status Register - AT91_REG SSC_IER; // Interrupt Enable Register - AT91_REG SSC_IDR; // Interrupt Disable Register - AT91_REG SSC_IMR; // Interrupt Mask Register - AT91_REG Reserved3[44]; // - AT91_REG SSC_RPR; // Receive Pointer Register - AT91_REG SSC_RCR; // Receive Counter Register - AT91_REG SSC_TPR; // Transmit Pointer Register - AT91_REG SSC_TCR; // Transmit Counter Register - AT91_REG SSC_RNPR; // Receive Next Pointer Register - AT91_REG SSC_RNCR; // Receive Next Counter Register - AT91_REG SSC_TNPR; // Transmit Next Pointer Register - AT91_REG SSC_TNCR; // Transmit Next Counter Register - AT91_REG SSC_PTCR; // PDC Transfer Control Register - AT91_REG SSC_PTSR; // PDC Transfer Status Register -} AT91S_SSC, *AT91PS_SSC; +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR Synchronous Serial Controller Interface */ +/* ***************************************************************************** */ +typedef struct _AT91S_SSC +{ + AT91_REG SSC_CR; /* Control Register */ + AT91_REG SSC_CMR; /* Clock Mode Register */ + AT91_REG Reserved0[ 2 ]; /* */ + AT91_REG SSC_RCMR; /* Receive Clock ModeRegister */ + AT91_REG SSC_RFMR; /* Receive Frame Mode Register */ + AT91_REG SSC_TCMR; /* Transmit Clock Mode Register */ + AT91_REG SSC_TFMR; /* Transmit Frame Mode Register */ + AT91_REG SSC_RHR; /* Receive Holding Register */ + AT91_REG SSC_THR; /* Transmit Holding Register */ + AT91_REG Reserved1[ 2 ]; /* */ + AT91_REG SSC_RSHR; /* Receive Sync Holding Register */ + AT91_REG SSC_TSHR; /* Transmit Sync Holding Register */ + AT91_REG Reserved2[ 2 ]; /* */ + AT91_REG SSC_SR; /* Status Register */ + AT91_REG SSC_IER; /* Interrupt Enable Register */ + AT91_REG SSC_IDR; /* Interrupt Disable Register */ + AT91_REG SSC_IMR; /* Interrupt Mask Register */ + AT91_REG Reserved3[ 44 ]; /* */ + AT91_REG SSC_RPR; /* Receive Pointer Register */ + AT91_REG SSC_RCR; /* Receive Counter Register */ + AT91_REG SSC_TPR; /* Transmit Pointer Register */ + AT91_REG SSC_TCR; /* Transmit Counter Register */ + AT91_REG SSC_RNPR; /* Receive Next Pointer Register */ + AT91_REG SSC_RNCR; /* Receive Next Counter Register */ + AT91_REG SSC_TNPR; /* Transmit Next Pointer Register */ + AT91_REG SSC_TNCR; /* Transmit Next Counter Register */ + AT91_REG SSC_PTCR; /* PDC Transfer Control Register */ + AT91_REG SSC_PTSR; /* PDC Transfer Status Register */ +} AT91S_SSC, * AT91PS_SSC; -// -------- SSC_CR : (SSC Offset: 0x0) SSC Control Register -------- -#define AT91C_SSC_RXEN ((unsigned int) 0x1 << 0) // (SSC) Receive Enable -#define AT91C_SSC_RXDIS ((unsigned int) 0x1 << 1) // (SSC) Receive Disable -#define AT91C_SSC_TXEN ((unsigned int) 0x1 << 8) // (SSC) Transmit Enable -#define AT91C_SSC_TXDIS ((unsigned int) 0x1 << 9) // (SSC) Transmit Disable -#define AT91C_SSC_SWRST ((unsigned int) 0x1 << 15) // (SSC) Software Reset -// -------- SSC_RCMR : (SSC Offset: 0x10) SSC Receive Clock Mode Register -------- -#define AT91C_SSC_CKS ((unsigned int) 0x3 << 0) // (SSC) Receive/Transmit Clock Selection -#define AT91C_SSC_CKS_DIV ((unsigned int) 0x0) // (SSC) Divided Clock -#define AT91C_SSC_CKS_TK ((unsigned int) 0x1) // (SSC) TK Clock signal -#define AT91C_SSC_CKS_RK ((unsigned int) 0x2) // (SSC) RK pin -#define AT91C_SSC_CKO ((unsigned int) 0x7 << 2) // (SSC) Receive/Transmit Clock Output Mode Selection -#define AT91C_SSC_CKO_NONE ((unsigned int) 0x0 << 2) // (SSC) Receive/Transmit Clock Output Mode: None RK pin: Input-only -#define AT91C_SSC_CKO_CONTINOUS ((unsigned int) 0x1 << 2) // (SSC) Continuous Receive/Transmit Clock RK pin: Output -#define AT91C_SSC_CKO_DATA_TX ((unsigned int) 0x2 << 2) // (SSC) Receive/Transmit Clock only during data transfers RK pin: Output -#define AT91C_SSC_CKI ((unsigned int) 0x1 << 5) // (SSC) Receive/Transmit Clock Inversion -#define AT91C_SSC_START ((unsigned int) 0xF << 8) // (SSC) Receive/Transmit Start Selection -#define AT91C_SSC_START_CONTINOUS ((unsigned int) 0x0 << 8) // (SSC) Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data. -#define AT91C_SSC_START_TX ((unsigned int) 0x1 << 8) // (SSC) Transmit/Receive start -#define AT91C_SSC_START_LOW_RF ((unsigned int) 0x2 << 8) // (SSC) Detection of a low level on RF input -#define AT91C_SSC_START_HIGH_RF ((unsigned int) 0x3 << 8) // (SSC) Detection of a high level on RF input -#define AT91C_SSC_START_FALL_RF ((unsigned int) 0x4 << 8) // (SSC) Detection of a falling edge on RF input -#define AT91C_SSC_START_RISE_RF ((unsigned int) 0x5 << 8) // (SSC) Detection of a rising edge on RF input -#define AT91C_SSC_START_LEVEL_RF ((unsigned int) 0x6 << 8) // (SSC) Detection of any level change on RF input -#define AT91C_SSC_START_EDGE_RF ((unsigned int) 0x7 << 8) // (SSC) Detection of any edge on RF input -#define AT91C_SSC_START_0 ((unsigned int) 0x8 << 8) // (SSC) Compare 0 -#define AT91C_SSC_STTDLY ((unsigned int) 0xFF << 16) // (SSC) Receive/Transmit Start Delay -#define AT91C_SSC_PERIOD ((unsigned int) 0xFF << 24) // (SSC) Receive/Transmit Period Divider Selection -// -------- SSC_RFMR : (SSC Offset: 0x14) SSC Receive Frame Mode Register -------- -#define AT91C_SSC_DATLEN ((unsigned int) 0x1F << 0) // (SSC) Data Length -#define AT91C_SSC_LOOP ((unsigned int) 0x1 << 5) // (SSC) Loop Mode -#define AT91C_SSC_MSBF ((unsigned int) 0x1 << 7) // (SSC) Most Significant Bit First -#define AT91C_SSC_DATNB ((unsigned int) 0xF << 8) // (SSC) Data Number per Frame -#define AT91C_SSC_FSLEN ((unsigned int) 0xF << 16) // (SSC) Receive/Transmit Frame Sync length -#define AT91C_SSC_FSOS ((unsigned int) 0x7 << 20) // (SSC) Receive/Transmit Frame Sync Output Selection -#define AT91C_SSC_FSOS_NONE ((unsigned int) 0x0 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: None RK pin Input-only -#define AT91C_SSC_FSOS_NEGATIVE ((unsigned int) 0x1 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Negative Pulse -#define AT91C_SSC_FSOS_POSITIVE ((unsigned int) 0x2 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Positive Pulse -#define AT91C_SSC_FSOS_LOW ((unsigned int) 0x3 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver Low during data transfer -#define AT91C_SSC_FSOS_HIGH ((unsigned int) 0x4 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver High during data transfer -#define AT91C_SSC_FSOS_TOGGLE ((unsigned int) 0x5 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Toggling at each start of data transfer -#define AT91C_SSC_FSEDGE ((unsigned int) 0x1 << 24) // (SSC) Frame Sync Edge Detection -// -------- SSC_TCMR : (SSC Offset: 0x18) SSC Transmit Clock Mode Register -------- -// -------- SSC_TFMR : (SSC Offset: 0x1c) SSC Transmit Frame Mode Register -------- -#define AT91C_SSC_DATDEF ((unsigned int) 0x1 << 5) // (SSC) Data Default Value -#define AT91C_SSC_FSDEN ((unsigned int) 0x1 << 23) // (SSC) Frame Sync Data Enable -// -------- SSC_SR : (SSC Offset: 0x40) SSC Status Register -------- -#define AT91C_SSC_TXRDY ((unsigned int) 0x1 << 0) // (SSC) Transmit Ready -#define AT91C_SSC_TXEMPTY ((unsigned int) 0x1 << 1) // (SSC) Transmit Empty -#define AT91C_SSC_ENDTX ((unsigned int) 0x1 << 2) // (SSC) End Of Transmission -#define AT91C_SSC_TXBUFE ((unsigned int) 0x1 << 3) // (SSC) Transmit Buffer Empty -#define AT91C_SSC_RXRDY ((unsigned int) 0x1 << 4) // (SSC) Receive Ready -#define AT91C_SSC_OVRUN ((unsigned int) 0x1 << 5) // (SSC) Receive Overrun -#define AT91C_SSC_ENDRX ((unsigned int) 0x1 << 6) // (SSC) End of Reception -#define AT91C_SSC_RXBUFF ((unsigned int) 0x1 << 7) // (SSC) Receive Buffer Full -#define AT91C_SSC_TXSYN ((unsigned int) 0x1 << 10) // (SSC) Transmit Sync -#define AT91C_SSC_RXSYN ((unsigned int) 0x1 << 11) // (SSC) Receive Sync -#define AT91C_SSC_TXENA ((unsigned int) 0x1 << 16) // (SSC) Transmit Enable -#define AT91C_SSC_RXENA ((unsigned int) 0x1 << 17) // (SSC) Receive Enable -// -------- SSC_IER : (SSC Offset: 0x44) SSC Interrupt Enable Register -------- -// -------- SSC_IDR : (SSC Offset: 0x48) SSC Interrupt Disable Register -------- -// -------- SSC_IMR : (SSC Offset: 0x4c) SSC Interrupt Mask Register -------- +/* -------- SSC_CR : (SSC Offset: 0x0) SSC Control Register -------- */ +#define AT91C_SSC_RXEN ( ( unsigned int ) 0x1 << 0 ) /* (SSC) Receive Enable */ +#define AT91C_SSC_RXDIS ( ( unsigned int ) 0x1 << 1 ) /* (SSC) Receive Disable */ +#define AT91C_SSC_TXEN ( ( unsigned int ) 0x1 << 8 ) /* (SSC) Transmit Enable */ +#define AT91C_SSC_TXDIS ( ( unsigned int ) 0x1 << 9 ) /* (SSC) Transmit Disable */ +#define AT91C_SSC_SWRST ( ( unsigned int ) 0x1 << 15 ) /* (SSC) Software Reset */ +/* -------- SSC_RCMR : (SSC Offset: 0x10) SSC Receive Clock Mode Register -------- */ +#define AT91C_SSC_CKS ( ( unsigned int ) 0x3 << 0 ) /* (SSC) Receive/Transmit Clock Selection */ +#define AT91C_SSC_CKS_DIV ( ( unsigned int ) 0x0 ) /* (SSC) Divided Clock */ +#define AT91C_SSC_CKS_TK ( ( unsigned int ) 0x1 ) /* (SSC) TK Clock signal */ +#define AT91C_SSC_CKS_RK ( ( unsigned int ) 0x2 ) /* (SSC) RK pin */ +#define AT91C_SSC_CKO ( ( unsigned int ) 0x7 << 2 ) /* (SSC) Receive/Transmit Clock Output Mode Selection */ +#define AT91C_SSC_CKO_NONE ( ( unsigned int ) 0x0 << 2 ) /* (SSC) Receive/Transmit Clock Output Mode: None RK pin: Input-only */ +#define AT91C_SSC_CKO_CONTINUOUS ( ( unsigned int ) 0x1 << 2 ) /* (SSC) Continuous Receive/Transmit Clock RK pin: Output */ +#define AT91C_SSC_CKO_DATA_TX ( ( unsigned int ) 0x2 << 2 ) /* (SSC) Receive/Transmit Clock only during data transfers RK pin: Output */ +#define AT91C_SSC_CKI ( ( unsigned int ) 0x1 << 5 ) /* (SSC) Receive/Transmit Clock Inversion */ +#define AT91C_SSC_START ( ( unsigned int ) 0xF << 8 ) /* (SSC) Receive/Transmit Start Selection */ +#define AT91C_SSC_START_CONTINUOUS ( ( unsigned int ) 0x0 << 8 ) /* (SSC) Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data. */ +#define AT91C_SSC_START_TX ( ( unsigned int ) 0x1 << 8 ) /* (SSC) Transmit/Receive start */ +#define AT91C_SSC_START_LOW_RF ( ( unsigned int ) 0x2 << 8 ) /* (SSC) Detection of a low level on RF input */ +#define AT91C_SSC_START_HIGH_RF ( ( unsigned int ) 0x3 << 8 ) /* (SSC) Detection of a high level on RF input */ +#define AT91C_SSC_START_FALL_RF ( ( unsigned int ) 0x4 << 8 ) /* (SSC) Detection of a falling edge on RF input */ +#define AT91C_SSC_START_RISE_RF ( ( unsigned int ) 0x5 << 8 ) /* (SSC) Detection of a rising edge on RF input */ +#define AT91C_SSC_START_LEVEL_RF ( ( unsigned int ) 0x6 << 8 ) /* (SSC) Detection of any level change on RF input */ +#define AT91C_SSC_START_EDGE_RF ( ( unsigned int ) 0x7 << 8 ) /* (SSC) Detection of any edge on RF input */ +#define AT91C_SSC_START_0 ( ( unsigned int ) 0x8 << 8 ) /* (SSC) Compare 0 */ +#define AT91C_SSC_STTDLY ( ( unsigned int ) 0xFF << 16 ) /* (SSC) Receive/Transmit Start Delay */ +#define AT91C_SSC_PERIOD ( ( unsigned int ) 0xFF << 24 ) /* (SSC) Receive/Transmit Period Divider Selection */ +/* -------- SSC_RFMR : (SSC Offset: 0x14) SSC Receive Frame Mode Register -------- */ +#define AT91C_SSC_DATLEN ( ( unsigned int ) 0x1F << 0 ) /* (SSC) Data Length */ +#define AT91C_SSC_LOOP ( ( unsigned int ) 0x1 << 5 ) /* (SSC) Loop Mode */ +#define AT91C_SSC_MSBF ( ( unsigned int ) 0x1 << 7 ) /* (SSC) Most Significant Bit First */ +#define AT91C_SSC_DATNB ( ( unsigned int ) 0xF << 8 ) /* (SSC) Data Number per Frame */ +#define AT91C_SSC_FSLEN ( ( unsigned int ) 0xF << 16 ) /* (SSC) Receive/Transmit Frame Sync length */ +#define AT91C_SSC_FSOS ( ( unsigned int ) 0x7 << 20 ) /* (SSC) Receive/Transmit Frame Sync Output Selection */ +#define AT91C_SSC_FSOS_NONE ( ( unsigned int ) 0x0 << 20 ) /* (SSC) Selected Receive/Transmit Frame Sync Signal: None RK pin Input-only */ +#define AT91C_SSC_FSOS_NEGATIVE ( ( unsigned int ) 0x1 << 20 ) /* (SSC) Selected Receive/Transmit Frame Sync Signal: Negative Pulse */ +#define AT91C_SSC_FSOS_POSITIVE ( ( unsigned int ) 0x2 << 20 ) /* (SSC) Selected Receive/Transmit Frame Sync Signal: Positive Pulse */ +#define AT91C_SSC_FSOS_LOW ( ( unsigned int ) 0x3 << 20 ) /* (SSC) Selected Receive/Transmit Frame Sync Signal: Driver Low during data transfer */ +#define AT91C_SSC_FSOS_HIGH ( ( unsigned int ) 0x4 << 20 ) /* (SSC) Selected Receive/Transmit Frame Sync Signal: Driver High during data transfer */ +#define AT91C_SSC_FSOS_TOGGLE ( ( unsigned int ) 0x5 << 20 ) /* (SSC) Selected Receive/Transmit Frame Sync Signal: Toggling at each start of data transfer */ +#define AT91C_SSC_FSEDGE ( ( unsigned int ) 0x1 << 24 ) /* (SSC) Frame Sync Edge Detection */ +/* -------- SSC_TCMR : (SSC Offset: 0x18) SSC Transmit Clock Mode Register -------- */ +/* -------- SSC_TFMR : (SSC Offset: 0x1c) SSC Transmit Frame Mode Register -------- */ +#define AT91C_SSC_DATDEF ( ( unsigned int ) 0x1 << 5 ) /* (SSC) Data Default Value */ +#define AT91C_SSC_FSDEN ( ( unsigned int ) 0x1 << 23 ) /* (SSC) Frame Sync Data Enable */ +/* -------- SSC_SR : (SSC Offset: 0x40) SSC Status Register -------- */ +#define AT91C_SSC_TXRDY ( ( unsigned int ) 0x1 << 0 ) /* (SSC) Transmit Ready */ +#define AT91C_SSC_TXEMPTY ( ( unsigned int ) 0x1 << 1 ) /* (SSC) Transmit Empty */ +#define AT91C_SSC_ENDTX ( ( unsigned int ) 0x1 << 2 ) /* (SSC) End Of Transmission */ +#define AT91C_SSC_TXBUFE ( ( unsigned int ) 0x1 << 3 ) /* (SSC) Transmit Buffer Empty */ +#define AT91C_SSC_RXRDY ( ( unsigned int ) 0x1 << 4 ) /* (SSC) Receive Ready */ +#define AT91C_SSC_OVRUN ( ( unsigned int ) 0x1 << 5 ) /* (SSC) Receive Overrun */ +#define AT91C_SSC_ENDRX ( ( unsigned int ) 0x1 << 6 ) /* (SSC) End of Reception */ +#define AT91C_SSC_RXBUFF ( ( unsigned int ) 0x1 << 7 ) /* (SSC) Receive Buffer Full */ +#define AT91C_SSC_TXSYN ( ( unsigned int ) 0x1 << 10 ) /* (SSC) Transmit Sync */ +#define AT91C_SSC_RXSYN ( ( unsigned int ) 0x1 << 11 ) /* (SSC) Receive Sync */ +#define AT91C_SSC_TXENA ( ( unsigned int ) 0x1 << 16 ) /* (SSC) Transmit Enable */ +#define AT91C_SSC_RXENA ( ( unsigned int ) 0x1 << 17 ) /* (SSC) Receive Enable */ +/* -------- SSC_IER : (SSC Offset: 0x44) SSC Interrupt Enable Register -------- */ +/* -------- SSC_IDR : (SSC Offset: 0x48) SSC Interrupt Disable Register -------- */ +/* -------- SSC_IMR : (SSC Offset: 0x4c) SSC Interrupt Mask Register -------- */ -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Two-wire Interface -// ***************************************************************************** -typedef struct _AT91S_TWI { - AT91_REG TWI_CR; // Control Register - AT91_REG TWI_MMR; // Master Mode Register - AT91_REG Reserved0[1]; // - AT91_REG TWI_IADR; // Internal Address Register - AT91_REG TWI_CWGR; // Clock Waveform Generator Register - AT91_REG Reserved1[3]; // - AT91_REG TWI_SR; // Status Register - AT91_REG TWI_IER; // Interrupt Enable Register - AT91_REG TWI_IDR; // Interrupt Disable Register - AT91_REG TWI_IMR; // Interrupt Mask Register - AT91_REG TWI_RHR; // Receive Holding Register - AT91_REG TWI_THR; // Transmit Holding Register -} AT91S_TWI, *AT91PS_TWI; +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR Two-wire Interface */ +/* ***************************************************************************** */ +typedef struct _AT91S_TWI +{ + AT91_REG TWI_CR; /* Control Register */ + AT91_REG TWI_MMR; /* Master Mode Register */ + AT91_REG Reserved0[ 1 ]; /* */ + AT91_REG TWI_IADR; /* Internal Address Register */ + AT91_REG TWI_CWGR; /* Clock Waveform Generator Register */ + AT91_REG Reserved1[ 3 ]; /* */ + AT91_REG TWI_SR; /* Status Register */ + AT91_REG TWI_IER; /* Interrupt Enable Register */ + AT91_REG TWI_IDR; /* Interrupt Disable Register */ + AT91_REG TWI_IMR; /* Interrupt Mask Register */ + AT91_REG TWI_RHR; /* Receive Holding Register */ + AT91_REG TWI_THR; /* Transmit Holding Register */ +} AT91S_TWI, * AT91PS_TWI; -// -------- TWI_CR : (TWI Offset: 0x0) TWI Control Register -------- -#define AT91C_TWI_START ((unsigned int) 0x1 << 0) // (TWI) Send a START Condition -#define AT91C_TWI_STOP ((unsigned int) 0x1 << 1) // (TWI) Send a STOP Condition -#define AT91C_TWI_MSEN ((unsigned int) 0x1 << 2) // (TWI) TWI Master Transfer Enabled -#define AT91C_TWI_MSDIS ((unsigned int) 0x1 << 3) // (TWI) TWI Master Transfer Disabled -#define AT91C_TWI_SWRST ((unsigned int) 0x1 << 7) // (TWI) Software Reset -// -------- TWI_MMR : (TWI Offset: 0x4) TWI Master Mode Register -------- -#define AT91C_TWI_IADRSZ ((unsigned int) 0x3 << 8) // (TWI) Internal Device Address Size -#define AT91C_TWI_IADRSZ_NO ((unsigned int) 0x0 << 8) // (TWI) No internal device address -#define AT91C_TWI_IADRSZ_1_BYTE ((unsigned int) 0x1 << 8) // (TWI) One-byte internal device address -#define AT91C_TWI_IADRSZ_2_BYTE ((unsigned int) 0x2 << 8) // (TWI) Two-byte internal device address -#define AT91C_TWI_IADRSZ_3_BYTE ((unsigned int) 0x3 << 8) // (TWI) Three-byte internal device address -#define AT91C_TWI_MREAD ((unsigned int) 0x1 << 12) // (TWI) Master Read Direction -#define AT91C_TWI_DADR ((unsigned int) 0x7F << 16) // (TWI) Device Address -// -------- TWI_CWGR : (TWI Offset: 0x10) TWI Clock Waveform Generator Register -------- -#define AT91C_TWI_CLDIV ((unsigned int) 0xFF << 0) // (TWI) Clock Low Divider -#define AT91C_TWI_CHDIV ((unsigned int) 0xFF << 8) // (TWI) Clock High Divider -#define AT91C_TWI_CKDIV ((unsigned int) 0x7 << 16) // (TWI) Clock Divider -// -------- TWI_SR : (TWI Offset: 0x20) TWI Status Register -------- -#define AT91C_TWI_TXCOMP ((unsigned int) 0x1 << 0) // (TWI) Transmission Completed -#define AT91C_TWI_RXRDY ((unsigned int) 0x1 << 1) // (TWI) Receive holding register ReaDY -#define AT91C_TWI_TXRDY ((unsigned int) 0x1 << 2) // (TWI) Transmit holding register ReaDY -#define AT91C_TWI_OVRE ((unsigned int) 0x1 << 6) // (TWI) Overrun Error -#define AT91C_TWI_UNRE ((unsigned int) 0x1 << 7) // (TWI) Underrun Error -#define AT91C_TWI_NACK ((unsigned int) 0x1 << 8) // (TWI) Not Acknowledged -// -------- TWI_IER : (TWI Offset: 0x24) TWI Interrupt Enable Register -------- -// -------- TWI_IDR : (TWI Offset: 0x28) TWI Interrupt Disable Register -------- -// -------- TWI_IMR : (TWI Offset: 0x2c) TWI Interrupt Mask Register -------- +/* -------- TWI_CR : (TWI Offset: 0x0) TWI Control Register -------- */ +#define AT91C_TWI_START ( ( unsigned int ) 0x1 << 0 ) /* (TWI) Send a START Condition */ +#define AT91C_TWI_STOP ( ( unsigned int ) 0x1 << 1 ) /* (TWI) Send a STOP Condition */ +#define AT91C_TWI_MSEN ( ( unsigned int ) 0x1 << 2 ) /* (TWI) TWI Master Transfer Enabled */ +#define AT91C_TWI_MSDIS ( ( unsigned int ) 0x1 << 3 ) /* (TWI) TWI Master Transfer Disabled */ +#define AT91C_TWI_SWRST ( ( unsigned int ) 0x1 << 7 ) /* (TWI) Software Reset */ +/* -------- TWI_MMR : (TWI Offset: 0x4) TWI Master Mode Register -------- */ +#define AT91C_TWI_IADRSZ ( ( unsigned int ) 0x3 << 8 ) /* (TWI) Internal Device Address Size */ +#define AT91C_TWI_IADRSZ_NO ( ( unsigned int ) 0x0 << 8 ) /* (TWI) No internal device address */ +#define AT91C_TWI_IADRSZ_1_BYTE ( ( unsigned int ) 0x1 << 8 ) /* (TWI) One-byte internal device address */ +#define AT91C_TWI_IADRSZ_2_BYTE ( ( unsigned int ) 0x2 << 8 ) /* (TWI) Two-byte internal device address */ +#define AT91C_TWI_IADRSZ_3_BYTE ( ( unsigned int ) 0x3 << 8 ) /* (TWI) Three-byte internal device address */ +#define AT91C_TWI_MREAD ( ( unsigned int ) 0x1 << 12 ) /* (TWI) Master Read Direction */ +#define AT91C_TWI_DADR ( ( unsigned int ) 0x7F << 16 ) /* (TWI) Device Address */ +/* -------- TWI_CWGR : (TWI Offset: 0x10) TWI Clock Waveform Generator Register -------- */ +#define AT91C_TWI_CLDIV ( ( unsigned int ) 0xFF << 0 ) /* (TWI) Clock Low Divider */ +#define AT91C_TWI_CHDIV ( ( unsigned int ) 0xFF << 8 ) /* (TWI) Clock High Divider */ +#define AT91C_TWI_CKDIV ( ( unsigned int ) 0x7 << 16 ) /* (TWI) Clock Divider */ +/* -------- TWI_SR : (TWI Offset: 0x20) TWI Status Register -------- */ +#define AT91C_TWI_TXCOMP ( ( unsigned int ) 0x1 << 0 ) /* (TWI) Transmission Completed */ +#define AT91C_TWI_RXRDY ( ( unsigned int ) 0x1 << 1 ) /* (TWI) Receive holding register ReaDY */ +#define AT91C_TWI_TXRDY ( ( unsigned int ) 0x1 << 2 ) /* (TWI) Transmit holding register ReaDY */ +#define AT91C_TWI_OVRE ( ( unsigned int ) 0x1 << 6 ) /* (TWI) Overrun Error */ +#define AT91C_TWI_UNRE ( ( unsigned int ) 0x1 << 7 ) /* (TWI) Underrun Error */ +#define AT91C_TWI_NACK ( ( unsigned int ) 0x1 << 8 ) /* (TWI) Not Acknowledged */ +/* -------- TWI_IER : (TWI Offset: 0x24) TWI Interrupt Enable Register -------- */ +/* -------- TWI_IDR : (TWI Offset: 0x28) TWI Interrupt Disable Register -------- */ +/* -------- TWI_IMR : (TWI Offset: 0x2c) TWI Interrupt Mask Register -------- */ -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR PWMC Channel Interface -// ***************************************************************************** -typedef struct _AT91S_PWMC_CH { - AT91_REG PWMC_CMR; // Channel Mode Register - AT91_REG PWMC_CDTYR; // Channel Duty Cycle Register - AT91_REG PWMC_CPRDR; // Channel Period Register - AT91_REG PWMC_CCNTR; // Channel Counter Register - AT91_REG PWMC_CUPDR; // Channel Update Register - AT91_REG PWMC_Reserved[3]; // Reserved -} AT91S_PWMC_CH, *AT91PS_PWMC_CH; +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR PWMC Channel Interface */ +/* ***************************************************************************** */ +typedef struct _AT91S_PWMC_CH +{ + AT91_REG PWMC_CMR; /* Channel Mode Register */ + AT91_REG PWMC_CDTYR; /* Channel Duty Cycle Register */ + AT91_REG PWMC_CPRDR; /* Channel Period Register */ + AT91_REG PWMC_CCNTR; /* Channel Counter Register */ + AT91_REG PWMC_CUPDR; /* Channel Update Register */ + AT91_REG PWMC_Reserved[ 3 ]; /* Reserved */ +} AT91S_PWMC_CH, * AT91PS_PWMC_CH; -// -------- PWMC_CMR : (PWMC_CH Offset: 0x0) PWMC Channel Mode Register -------- -#define AT91C_PWMC_CPRE ((unsigned int) 0xF << 0) // (PWMC_CH) Channel Pre-scaler : PWMC_CLKx -#define AT91C_PWMC_CPRE_MCK ((unsigned int) 0x0) // (PWMC_CH) -#define AT91C_PWMC_CPRE_MCKA ((unsigned int) 0xB) // (PWMC_CH) -#define AT91C_PWMC_CPRE_MCKB ((unsigned int) 0xC) // (PWMC_CH) -#define AT91C_PWMC_CALG ((unsigned int) 0x1 << 8) // (PWMC_CH) Channel Alignment -#define AT91C_PWMC_CPOL ((unsigned int) 0x1 << 9) // (PWMC_CH) Channel Polarity -#define AT91C_PWMC_CPD ((unsigned int) 0x1 << 10) // (PWMC_CH) Channel Update Period -// -------- PWMC_CDTYR : (PWMC_CH Offset: 0x4) PWMC Channel Duty Cycle Register -------- -#define AT91C_PWMC_CDTY ((unsigned int) 0x0 << 0) // (PWMC_CH) Channel Duty Cycle -// -------- PWMC_CPRDR : (PWMC_CH Offset: 0x8) PWMC Channel Period Register -------- -#define AT91C_PWMC_CPRD ((unsigned int) 0x0 << 0) // (PWMC_CH) Channel Period -// -------- PWMC_CCNTR : (PWMC_CH Offset: 0xc) PWMC Channel Counter Register -------- -#define AT91C_PWMC_CCNT ((unsigned int) 0x0 << 0) // (PWMC_CH) Channel Counter -// -------- PWMC_CUPDR : (PWMC_CH Offset: 0x10) PWMC Channel Update Register -------- -#define AT91C_PWMC_CUPD ((unsigned int) 0x0 << 0) // (PWMC_CH) Channel Update +/* -------- PWMC_CMR : (PWMC_CH Offset: 0x0) PWMC Channel Mode Register -------- */ +#define AT91C_PWMC_CPRE ( ( unsigned int ) 0xF << 0 ) /* (PWMC_CH) Channel Pre-scaler : PWMC_CLKx */ +#define AT91C_PWMC_CPRE_MCK ( ( unsigned int ) 0x0 ) /* (PWMC_CH) */ +#define AT91C_PWMC_CPRE_MCKA ( ( unsigned int ) 0xB ) /* (PWMC_CH) */ +#define AT91C_PWMC_CPRE_MCKB ( ( unsigned int ) 0xC ) /* (PWMC_CH) */ +#define AT91C_PWMC_CALG ( ( unsigned int ) 0x1 << 8 ) /* (PWMC_CH) Channel Alignment */ +#define AT91C_PWMC_CPOL ( ( unsigned int ) 0x1 << 9 ) /* (PWMC_CH) Channel Polarity */ +#define AT91C_PWMC_CPD ( ( unsigned int ) 0x1 << 10 ) /* (PWMC_CH) Channel Update Period */ +/* -------- PWMC_CDTYR : (PWMC_CH Offset: 0x4) PWMC Channel Duty Cycle Register -------- */ +#define AT91C_PWMC_CDTY ( ( unsigned int ) 0x0 << 0 ) /* (PWMC_CH) Channel Duty Cycle */ +/* -------- PWMC_CPRDR : (PWMC_CH Offset: 0x8) PWMC Channel Period Register -------- */ +#define AT91C_PWMC_CPRD ( ( unsigned int ) 0x0 << 0 ) /* (PWMC_CH) Channel Period */ +/* -------- PWMC_CCNTR : (PWMC_CH Offset: 0xc) PWMC Channel Counter Register -------- */ +#define AT91C_PWMC_CCNT ( ( unsigned int ) 0x0 << 0 ) /* (PWMC_CH) Channel Counter */ +/* -------- PWMC_CUPDR : (PWMC_CH Offset: 0x10) PWMC Channel Update Register -------- */ +#define AT91C_PWMC_CUPD ( ( unsigned int ) 0x0 << 0 ) /* (PWMC_CH) Channel Update */ -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Pulse Width Modulation Controller Interface -// ***************************************************************************** -typedef struct _AT91S_PWMC { - AT91_REG PWMC_MR; // PWMC Mode Register - AT91_REG PWMC_ENA; // PWMC Enable Register - AT91_REG PWMC_DIS; // PWMC Disable Register - AT91_REG PWMC_SR; // PWMC Status Register - AT91_REG PWMC_IER; // PWMC Interrupt Enable Register - AT91_REG PWMC_IDR; // PWMC Interrupt Disable Register - AT91_REG PWMC_IMR; // PWMC Interrupt Mask Register - AT91_REG PWMC_ISR; // PWMC Interrupt Status Register - AT91_REG Reserved0[55]; // - AT91_REG PWMC_VR; // PWMC Version Register - AT91_REG Reserved1[64]; // - AT91S_PWMC_CH PWMC_CH[4]; // PWMC Channel -} AT91S_PWMC, *AT91PS_PWMC; +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR Pulse Width Modulation Controller Interface */ +/* ***************************************************************************** */ +typedef struct _AT91S_PWMC +{ + AT91_REG PWMC_MR; /* PWMC Mode Register */ + AT91_REG PWMC_ENA; /* PWMC Enable Register */ + AT91_REG PWMC_DIS; /* PWMC Disable Register */ + AT91_REG PWMC_SR; /* PWMC Status Register */ + AT91_REG PWMC_IER; /* PWMC Interrupt Enable Register */ + AT91_REG PWMC_IDR; /* PWMC Interrupt Disable Register */ + AT91_REG PWMC_IMR; /* PWMC Interrupt Mask Register */ + AT91_REG PWMC_ISR; /* PWMC Interrupt Status Register */ + AT91_REG Reserved0[ 55 ]; /* */ + AT91_REG PWMC_VR; /* PWMC Version Register */ + AT91_REG Reserved1[ 64 ]; /* */ + AT91S_PWMC_CH PWMC_CH[ 4 ]; /* PWMC Channel */ +} AT91S_PWMC, * AT91PS_PWMC; -// -------- PWMC_MR : (PWMC Offset: 0x0) PWMC Mode Register -------- -#define AT91C_PWMC_DIVA ((unsigned int) 0xFF << 0) // (PWMC) CLKA divide factor. -#define AT91C_PWMC_PREA ((unsigned int) 0xF << 8) // (PWMC) Divider Input Clock Prescaler A -#define AT91C_PWMC_PREA_MCK ((unsigned int) 0x0 << 8) // (PWMC) -#define AT91C_PWMC_DIVB ((unsigned int) 0xFF << 16) // (PWMC) CLKB divide factor. -#define AT91C_PWMC_PREB ((unsigned int) 0xF << 24) // (PWMC) Divider Input Clock Prescaler B -#define AT91C_PWMC_PREB_MCK ((unsigned int) 0x0 << 24) // (PWMC) -// -------- PWMC_ENA : (PWMC Offset: 0x4) PWMC Enable Register -------- -#define AT91C_PWMC_CHID0 ((unsigned int) 0x1 << 0) // (PWMC) Channel ID 0 -#define AT91C_PWMC_CHID1 ((unsigned int) 0x1 << 1) // (PWMC) Channel ID 1 -#define AT91C_PWMC_CHID2 ((unsigned int) 0x1 << 2) // (PWMC) Channel ID 2 -#define AT91C_PWMC_CHID3 ((unsigned int) 0x1 << 3) // (PWMC) Channel ID 3 -// -------- PWMC_DIS : (PWMC Offset: 0x8) PWMC Disable Register -------- -// -------- PWMC_SR : (PWMC Offset: 0xc) PWMC Status Register -------- -// -------- PWMC_IER : (PWMC Offset: 0x10) PWMC Interrupt Enable Register -------- -// -------- PWMC_IDR : (PWMC Offset: 0x14) PWMC Interrupt Disable Register -------- -// -------- PWMC_IMR : (PWMC Offset: 0x18) PWMC Interrupt Mask Register -------- -// -------- PWMC_ISR : (PWMC Offset: 0x1c) PWMC Interrupt Status Register -------- +/* -------- PWMC_MR : (PWMC Offset: 0x0) PWMC Mode Register -------- */ +#define AT91C_PWMC_DIVA ( ( unsigned int ) 0xFF << 0 ) /* (PWMC) CLKA divide factor. */ +#define AT91C_PWMC_PREA ( ( unsigned int ) 0xF << 8 ) /* (PWMC) Divider Input Clock Prescaler A */ +#define AT91C_PWMC_PREA_MCK ( ( unsigned int ) 0x0 << 8 ) /* (PWMC) */ +#define AT91C_PWMC_DIVB ( ( unsigned int ) 0xFF << 16 ) /* (PWMC) CLKB divide factor. */ +#define AT91C_PWMC_PREB ( ( unsigned int ) 0xF << 24 ) /* (PWMC) Divider Input Clock Prescaler B */ +#define AT91C_PWMC_PREB_MCK ( ( unsigned int ) 0x0 << 24 ) /* (PWMC) */ +/* -------- PWMC_ENA : (PWMC Offset: 0x4) PWMC Enable Register -------- */ +#define AT91C_PWMC_CHID0 ( ( unsigned int ) 0x1 << 0 ) /* (PWMC) Channel ID 0 */ +#define AT91C_PWMC_CHID1 ( ( unsigned int ) 0x1 << 1 ) /* (PWMC) Channel ID 1 */ +#define AT91C_PWMC_CHID2 ( ( unsigned int ) 0x1 << 2 ) /* (PWMC) Channel ID 2 */ +#define AT91C_PWMC_CHID3 ( ( unsigned int ) 0x1 << 3 ) /* (PWMC) Channel ID 3 */ +/* -------- PWMC_DIS : (PWMC Offset: 0x8) PWMC Disable Register -------- */ +/* -------- PWMC_SR : (PWMC Offset: 0xc) PWMC Status Register -------- */ +/* -------- PWMC_IER : (PWMC Offset: 0x10) PWMC Interrupt Enable Register -------- */ +/* -------- PWMC_IDR : (PWMC Offset: 0x14) PWMC Interrupt Disable Register -------- */ +/* -------- PWMC_IMR : (PWMC Offset: 0x18) PWMC Interrupt Mask Register -------- */ +/* -------- PWMC_ISR : (PWMC Offset: 0x1c) PWMC Interrupt Status Register -------- */ -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR USB Device Interface -// ***************************************************************************** -typedef struct _AT91S_UDP { - AT91_REG UDP_NUM; // Frame Number Register - AT91_REG UDP_GLBSTATE; // Global State Register - AT91_REG UDP_FADDR; // Function Address Register - AT91_REG Reserved0[1]; // - AT91_REG UDP_IER; // Interrupt Enable Register - AT91_REG UDP_IDR; // Interrupt Disable Register - AT91_REG UDP_IMR; // Interrupt Mask Register - AT91_REG UDP_ISR; // Interrupt Status Register - AT91_REG UDP_ICR; // Interrupt Clear Register - AT91_REG Reserved1[1]; // - AT91_REG UDP_RSTEP; // Reset Endpoint Register - AT91_REG Reserved2[1]; // - AT91_REG UDP_CSR[6]; // Endpoint Control and Status Register - AT91_REG Reserved3[2]; // - AT91_REG UDP_FDR[6]; // Endpoint FIFO Data Register - AT91_REG Reserved4[3]; // - AT91_REG UDP_TXVC; // Transceiver Control Register -} AT91S_UDP, *AT91PS_UDP; +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR USB Device Interface */ +/* ***************************************************************************** */ +typedef struct _AT91S_UDP +{ + AT91_REG UDP_NUM; /* Frame Number Register */ + AT91_REG UDP_GLBSTATE; /* Global State Register */ + AT91_REG UDP_FADDR; /* Function Address Register */ + AT91_REG Reserved0[ 1 ]; /* */ + AT91_REG UDP_IER; /* Interrupt Enable Register */ + AT91_REG UDP_IDR; /* Interrupt Disable Register */ + AT91_REG UDP_IMR; /* Interrupt Mask Register */ + AT91_REG UDP_ISR; /* Interrupt Status Register */ + AT91_REG UDP_ICR; /* Interrupt Clear Register */ + AT91_REG Reserved1[ 1 ]; /* */ + AT91_REG UDP_RSTEP; /* Reset Endpoint Register */ + AT91_REG Reserved2[ 1 ]; /* */ + AT91_REG UDP_CSR[ 6 ]; /* Endpoint Control and Status Register */ + AT91_REG Reserved3[ 2 ]; /* */ + AT91_REG UDP_FDR[ 6 ]; /* Endpoint FIFO Data Register */ + AT91_REG Reserved4[ 3 ]; /* */ + AT91_REG UDP_TXVC; /* Transceiver Control Register */ +} AT91S_UDP, * AT91PS_UDP; -// -------- UDP_FRM_NUM : (UDP Offset: 0x0) USB Frame Number Register -------- -#define AT91C_UDP_FRM_NUM ((unsigned int) 0x7FF << 0) // (UDP) Frame Number as Defined in the Packet Field Formats -#define AT91C_UDP_FRM_ERR ((unsigned int) 0x1 << 16) // (UDP) Frame Error -#define AT91C_UDP_FRM_OK ((unsigned int) 0x1 << 17) // (UDP) Frame OK -// -------- UDP_GLB_STATE : (UDP Offset: 0x4) USB Global State Register -------- -#define AT91C_UDP_FADDEN ((unsigned int) 0x1 << 0) // (UDP) Function Address Enable -#define AT91C_UDP_CONFG ((unsigned int) 0x1 << 1) // (UDP) Configured -#define AT91C_UDP_ESR ((unsigned int) 0x1 << 2) // (UDP) Enable Send Resume -#define AT91C_UDP_RSMINPR ((unsigned int) 0x1 << 3) // (UDP) A Resume Has Been Sent to the Host -#define AT91C_UDP_RMWUPE ((unsigned int) 0x1 << 4) // (UDP) Remote Wake Up Enable -// -------- UDP_FADDR : (UDP Offset: 0x8) USB Function Address Register -------- -#define AT91C_UDP_FADD ((unsigned int) 0xFF << 0) // (UDP) Function Address Value -#define AT91C_UDP_FEN ((unsigned int) 0x1 << 8) // (UDP) Function Enable -// -------- UDP_IER : (UDP Offset: 0x10) USB Interrupt Enable Register -------- -#define AT91C_UDP_EPINT0 ((unsigned int) 0x1 << 0) // (UDP) Endpoint 0 Interrupt -#define AT91C_UDP_EPINT1 ((unsigned int) 0x1 << 1) // (UDP) Endpoint 0 Interrupt -#define AT91C_UDP_EPINT2 ((unsigned int) 0x1 << 2) // (UDP) Endpoint 2 Interrupt -#define AT91C_UDP_EPINT3 ((unsigned int) 0x1 << 3) // (UDP) Endpoint 3 Interrupt -#define AT91C_UDP_EPINT4 ((unsigned int) 0x1 << 4) // (UDP) Endpoint 4 Interrupt -#define AT91C_UDP_EPINT5 ((unsigned int) 0x1 << 5) // (UDP) Endpoint 5 Interrupt -#define AT91C_UDP_RXSUSP ((unsigned int) 0x1 << 8) // (UDP) USB Suspend Interrupt -#define AT91C_UDP_RXRSM ((unsigned int) 0x1 << 9) // (UDP) USB Resume Interrupt -#define AT91C_UDP_EXTRSM ((unsigned int) 0x1 << 10) // (UDP) USB External Resume Interrupt -#define AT91C_UDP_SOFINT ((unsigned int) 0x1 << 11) // (UDP) USB Start Of frame Interrupt -#define AT91C_UDP_WAKEUP ((unsigned int) 0x1 << 13) // (UDP) USB Resume Interrupt -// -------- UDP_IDR : (UDP Offset: 0x14) USB Interrupt Disable Register -------- -// -------- UDP_IMR : (UDP Offset: 0x18) USB Interrupt Mask Register -------- -// -------- UDP_ISR : (UDP Offset: 0x1c) USB Interrupt Status Register -------- -#define AT91C_UDP_ENDBUSRES ((unsigned int) 0x1 << 12) // (UDP) USB End Of Bus Reset Interrupt -// -------- UDP_ICR : (UDP Offset: 0x20) USB Interrupt Clear Register -------- -// -------- UDP_RST_EP : (UDP Offset: 0x28) USB Reset Endpoint Register -------- -#define AT91C_UDP_EP0 ((unsigned int) 0x1 << 0) // (UDP) Reset Endpoint 0 -#define AT91C_UDP_EP1 ((unsigned int) 0x1 << 1) // (UDP) Reset Endpoint 1 -#define AT91C_UDP_EP2 ((unsigned int) 0x1 << 2) // (UDP) Reset Endpoint 2 -#define AT91C_UDP_EP3 ((unsigned int) 0x1 << 3) // (UDP) Reset Endpoint 3 -#define AT91C_UDP_EP4 ((unsigned int) 0x1 << 4) // (UDP) Reset Endpoint 4 -#define AT91C_UDP_EP5 ((unsigned int) 0x1 << 5) // (UDP) Reset Endpoint 5 -// -------- UDP_CSR : (UDP Offset: 0x30) USB Endpoint Control and Status Register -------- -#define AT91C_UDP_TXCOMP ((unsigned int) 0x1 << 0) // (UDP) Generates an IN packet with data previously written in the DPR -#define AT91C_UDP_RX_DATA_BK0 ((unsigned int) 0x1 << 1) // (UDP) Receive Data Bank 0 -#define AT91C_UDP_RXSETUP ((unsigned int) 0x1 << 2) // (UDP) Sends STALL to the Host (Control endpoints) -#define AT91C_UDP_ISOERROR ((unsigned int) 0x1 << 3) // (UDP) Isochronous error (Isochronous endpoints) -#define AT91C_UDP_TXPKTRDY ((unsigned int) 0x1 << 4) // (UDP) Transmit Packet Ready -#define AT91C_UDP_FORCESTALL ((unsigned int) 0x1 << 5) // (UDP) Force Stall (used by Control, Bulk and Isochronous endpoints). -#define AT91C_UDP_RX_DATA_BK1 ((unsigned int) 0x1 << 6) // (UDP) Receive Data Bank 1 (only used by endpoints with ping-pong attributes). -#define AT91C_UDP_DIR ((unsigned int) 0x1 << 7) // (UDP) Transfer Direction -#define AT91C_UDP_EPTYPE ((unsigned int) 0x7 << 8) // (UDP) Endpoint type -#define AT91C_UDP_EPTYPE_CTRL ((unsigned int) 0x0 << 8) // (UDP) Control -#define AT91C_UDP_EPTYPE_ISO_OUT ((unsigned int) 0x1 << 8) // (UDP) Isochronous OUT -#define AT91C_UDP_EPTYPE_BULK_OUT ((unsigned int) 0x2 << 8) // (UDP) Bulk OUT -#define AT91C_UDP_EPTYPE_INT_OUT ((unsigned int) 0x3 << 8) // (UDP) Interrupt OUT -#define AT91C_UDP_EPTYPE_ISO_IN ((unsigned int) 0x5 << 8) // (UDP) Isochronous IN -#define AT91C_UDP_EPTYPE_BULK_IN ((unsigned int) 0x6 << 8) // (UDP) Bulk IN -#define AT91C_UDP_EPTYPE_INT_IN ((unsigned int) 0x7 << 8) // (UDP) Interrupt IN -#define AT91C_UDP_DTGLE ((unsigned int) 0x1 << 11) // (UDP) Data Toggle -#define AT91C_UDP_EPEDS ((unsigned int) 0x1 << 15) // (UDP) Endpoint Enable Disable -#define AT91C_UDP_RXBYTECNT ((unsigned int) 0x7FF << 16) // (UDP) Number Of Bytes Available in the FIFO -// -------- UDP_TXVC : (UDP Offset: 0x74) Transceiver Control Register -------- -#define AT91C_UDP_TXVDIS ((unsigned int) 0x1 << 8) // (UDP) -#define AT91C_UDP_PUON ((unsigned int) 0x1 << 9) // (UDP) Pull-up ON +/* -------- UDP_FRM_NUM : (UDP Offset: 0x0) USB Frame Number Register -------- */ +#define AT91C_UDP_FRM_NUM ( ( unsigned int ) 0x7FF << 0 ) /* (UDP) Frame Number as Defined in the Packet Field Formats */ +#define AT91C_UDP_FRM_ERR ( ( unsigned int ) 0x1 << 16 ) /* (UDP) Frame Error */ +#define AT91C_UDP_FRM_OK ( ( unsigned int ) 0x1 << 17 ) /* (UDP) Frame OK */ +/* -------- UDP_GLB_STATE : (UDP Offset: 0x4) USB Global State Register -------- */ +#define AT91C_UDP_FADDEN ( ( unsigned int ) 0x1 << 0 ) /* (UDP) Function Address Enable */ +#define AT91C_UDP_CONFG ( ( unsigned int ) 0x1 << 1 ) /* (UDP) Configured */ +#define AT91C_UDP_ESR ( ( unsigned int ) 0x1 << 2 ) /* (UDP) Enable Send Resume */ +#define AT91C_UDP_RSMINPR ( ( unsigned int ) 0x1 << 3 ) /* (UDP) A Resume Has Been Sent to the Host */ +#define AT91C_UDP_RMWUPE ( ( unsigned int ) 0x1 << 4 ) /* (UDP) Remote Wake Up Enable */ +/* -------- UDP_FADDR : (UDP Offset: 0x8) USB Function Address Register -------- */ +#define AT91C_UDP_FADD ( ( unsigned int ) 0xFF << 0 ) /* (UDP) Function Address Value */ +#define AT91C_UDP_FEN ( ( unsigned int ) 0x1 << 8 ) /* (UDP) Function Enable */ +/* -------- UDP_IER : (UDP Offset: 0x10) USB Interrupt Enable Register -------- */ +#define AT91C_UDP_EPINT0 ( ( unsigned int ) 0x1 << 0 ) /* (UDP) Endpoint 0 Interrupt */ +#define AT91C_UDP_EPINT1 ( ( unsigned int ) 0x1 << 1 ) /* (UDP) Endpoint 0 Interrupt */ +#define AT91C_UDP_EPINT2 ( ( unsigned int ) 0x1 << 2 ) /* (UDP) Endpoint 2 Interrupt */ +#define AT91C_UDP_EPINT3 ( ( unsigned int ) 0x1 << 3 ) /* (UDP) Endpoint 3 Interrupt */ +#define AT91C_UDP_EPINT4 ( ( unsigned int ) 0x1 << 4 ) /* (UDP) Endpoint 4 Interrupt */ +#define AT91C_UDP_EPINT5 ( ( unsigned int ) 0x1 << 5 ) /* (UDP) Endpoint 5 Interrupt */ +#define AT91C_UDP_RXSUSP ( ( unsigned int ) 0x1 << 8 ) /* (UDP) USB Suspend Interrupt */ +#define AT91C_UDP_RXRSM ( ( unsigned int ) 0x1 << 9 ) /* (UDP) USB Resume Interrupt */ +#define AT91C_UDP_EXTRSM ( ( unsigned int ) 0x1 << 10 ) /* (UDP) USB External Resume Interrupt */ +#define AT91C_UDP_SOFINT ( ( unsigned int ) 0x1 << 11 ) /* (UDP) USB Start Of frame Interrupt */ +#define AT91C_UDP_WAKEUP ( ( unsigned int ) 0x1 << 13 ) /* (UDP) USB Resume Interrupt */ +/* -------- UDP_IDR : (UDP Offset: 0x14) USB Interrupt Disable Register -------- */ +/* -------- UDP_IMR : (UDP Offset: 0x18) USB Interrupt Mask Register -------- */ +/* -------- UDP_ISR : (UDP Offset: 0x1c) USB Interrupt Status Register -------- */ +#define AT91C_UDP_ENDBUSRES ( ( unsigned int ) 0x1 << 12 ) /* (UDP) USB End Of Bus Reset Interrupt */ +/* -------- UDP_ICR : (UDP Offset: 0x20) USB Interrupt Clear Register -------- */ +/* -------- UDP_RST_EP : (UDP Offset: 0x28) USB Reset Endpoint Register -------- */ +#define AT91C_UDP_EP0 ( ( unsigned int ) 0x1 << 0 ) /* (UDP) Reset Endpoint 0 */ +#define AT91C_UDP_EP1 ( ( unsigned int ) 0x1 << 1 ) /* (UDP) Reset Endpoint 1 */ +#define AT91C_UDP_EP2 ( ( unsigned int ) 0x1 << 2 ) /* (UDP) Reset Endpoint 2 */ +#define AT91C_UDP_EP3 ( ( unsigned int ) 0x1 << 3 ) /* (UDP) Reset Endpoint 3 */ +#define AT91C_UDP_EP4 ( ( unsigned int ) 0x1 << 4 ) /* (UDP) Reset Endpoint 4 */ +#define AT91C_UDP_EP5 ( ( unsigned int ) 0x1 << 5 ) /* (UDP) Reset Endpoint 5 */ +/* -------- UDP_CSR : (UDP Offset: 0x30) USB Endpoint Control and Status Register -------- */ +#define AT91C_UDP_TXCOMP ( ( unsigned int ) 0x1 << 0 ) /* (UDP) Generates an IN packet with data previously written in the DPR */ +#define AT91C_UDP_RX_DATA_BK0 ( ( unsigned int ) 0x1 << 1 ) /* (UDP) Receive Data Bank 0 */ +#define AT91C_UDP_RXSETUP ( ( unsigned int ) 0x1 << 2 ) /* (UDP) Sends STALL to the Host (Control endpoints) */ +#define AT91C_UDP_ISOERROR ( ( unsigned int ) 0x1 << 3 ) /* (UDP) Isochronous error (Isochronous endpoints) */ +#define AT91C_UDP_TXPKTRDY ( ( unsigned int ) 0x1 << 4 ) /* (UDP) Transmit Packet Ready */ +#define AT91C_UDP_FORCESTALL ( ( unsigned int ) 0x1 << 5 ) /* (UDP) Force Stall (used by Control, Bulk and Isochronous endpoints). */ +#define AT91C_UDP_RX_DATA_BK1 ( ( unsigned int ) 0x1 << 6 ) /* (UDP) Receive Data Bank 1 (only used by endpoints with ping-pong attributes). */ +#define AT91C_UDP_DIR ( ( unsigned int ) 0x1 << 7 ) /* (UDP) Transfer Direction */ +#define AT91C_UDP_EPTYPE ( ( unsigned int ) 0x7 << 8 ) /* (UDP) Endpoint type */ +#define AT91C_UDP_EPTYPE_CTRL ( ( unsigned int ) 0x0 << 8 ) /* (UDP) Control */ +#define AT91C_UDP_EPTYPE_ISO_OUT ( ( unsigned int ) 0x1 << 8 ) /* (UDP) Isochronous OUT */ +#define AT91C_UDP_EPTYPE_BULK_OUT ( ( unsigned int ) 0x2 << 8 ) /* (UDP) Bulk OUT */ +#define AT91C_UDP_EPTYPE_INT_OUT ( ( unsigned int ) 0x3 << 8 ) /* (UDP) Interrupt OUT */ +#define AT91C_UDP_EPTYPE_ISO_IN ( ( unsigned int ) 0x5 << 8 ) /* (UDP) Isochronous IN */ +#define AT91C_UDP_EPTYPE_BULK_IN ( ( unsigned int ) 0x6 << 8 ) /* (UDP) Bulk IN */ +#define AT91C_UDP_EPTYPE_INT_IN ( ( unsigned int ) 0x7 << 8 ) /* (UDP) Interrupt IN */ +#define AT91C_UDP_DTGLE ( ( unsigned int ) 0x1 << 11 ) /* (UDP) Data Toggle */ +#define AT91C_UDP_EPEDS ( ( unsigned int ) 0x1 << 15 ) /* (UDP) Endpoint Enable Disable */ +#define AT91C_UDP_RXBYTECNT ( ( unsigned int ) 0x7FF << 16 ) /* (UDP) Number Of Bytes Available in the FIFO */ +/* -------- UDP_TXVC : (UDP Offset: 0x74) Transceiver Control Register -------- */ +#define AT91C_UDP_TXVDIS ( ( unsigned int ) 0x1 << 8 ) /* (UDP) */ +#define AT91C_UDP_PUON ( ( unsigned int ) 0x1 << 9 ) /* (UDP) Pull-up ON */ -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Timer Counter Channel Interface -// ***************************************************************************** -typedef struct _AT91S_TC { - AT91_REG TC_CCR; // Channel Control Register - AT91_REG TC_CMR; // Channel Mode Register (Capture Mode / Waveform Mode) - AT91_REG Reserved0[2]; // - AT91_REG TC_CV; // Counter Value - AT91_REG TC_RA; // Register A - AT91_REG TC_RB; // Register B - AT91_REG TC_RC; // Register C - AT91_REG TC_SR; // Status Register - AT91_REG TC_IER; // Interrupt Enable Register - AT91_REG TC_IDR; // Interrupt Disable Register - AT91_REG TC_IMR; // Interrupt Mask Register -} AT91S_TC, *AT91PS_TC; +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR Timer Counter Channel Interface */ +/* ***************************************************************************** */ +typedef struct _AT91S_TC +{ + AT91_REG TC_CCR; /* Channel Control Register */ + AT91_REG TC_CMR; /* Channel Mode Register (Capture Mode / Waveform Mode) */ + AT91_REG Reserved0[ 2 ]; /* */ + AT91_REG TC_CV; /* Counter Value */ + AT91_REG TC_RA; /* Register A */ + AT91_REG TC_RB; /* Register B */ + AT91_REG TC_RC; /* Register C */ + AT91_REG TC_SR; /* Status Register */ + AT91_REG TC_IER; /* Interrupt Enable Register */ + AT91_REG TC_IDR; /* Interrupt Disable Register */ + AT91_REG TC_IMR; /* Interrupt Mask Register */ +} AT91S_TC, * AT91PS_TC; -// -------- TC_CCR : (TC Offset: 0x0) TC Channel Control Register -------- -#define AT91C_TC_CLKEN ((unsigned int) 0x1 << 0) // (TC) Counter Clock Enable Command -#define AT91C_TC_CLKDIS ((unsigned int) 0x1 << 1) // (TC) Counter Clock Disable Command -#define AT91C_TC_SWTRG ((unsigned int) 0x1 << 2) // (TC) Software Trigger Command -// -------- TC_CMR : (TC Offset: 0x4) TC Channel Mode Register: Capture Mode / Waveform Mode -------- -#define AT91C_TC_CLKS ((unsigned int) 0x7 << 0) // (TC) Clock Selection -#define AT91C_TC_CLKS_TIMER_DIV1_CLOCK ((unsigned int) 0x0) // (TC) Clock selected: TIMER_DIV1_CLOCK -#define AT91C_TC_CLKS_TIMER_DIV2_CLOCK ((unsigned int) 0x1) // (TC) Clock selected: TIMER_DIV2_CLOCK -#define AT91C_TC_CLKS_TIMER_DIV3_CLOCK ((unsigned int) 0x2) // (TC) Clock selected: TIMER_DIV3_CLOCK -#define AT91C_TC_CLKS_TIMER_DIV4_CLOCK ((unsigned int) 0x3) // (TC) Clock selected: TIMER_DIV4_CLOCK -#define AT91C_TC_CLKS_TIMER_DIV5_CLOCK ((unsigned int) 0x4) // (TC) Clock selected: TIMER_DIV5_CLOCK -#define AT91C_TC_CLKS_XC0 ((unsigned int) 0x5) // (TC) Clock selected: XC0 -#define AT91C_TC_CLKS_XC1 ((unsigned int) 0x6) // (TC) Clock selected: XC1 -#define AT91C_TC_CLKS_XC2 ((unsigned int) 0x7) // (TC) Clock selected: XC2 -#define AT91C_TC_CLKI ((unsigned int) 0x1 << 3) // (TC) Clock Invert -#define AT91C_TC_BURST ((unsigned int) 0x3 << 4) // (TC) Burst Signal Selection -#define AT91C_TC_BURST_NONE ((unsigned int) 0x0 << 4) // (TC) The clock is not gated by an external signal -#define AT91C_TC_BURST_XC0 ((unsigned int) 0x1 << 4) // (TC) XC0 is ANDed with the selected clock -#define AT91C_TC_BURST_XC1 ((unsigned int) 0x2 << 4) // (TC) XC1 is ANDed with the selected clock -#define AT91C_TC_BURST_XC2 ((unsigned int) 0x3 << 4) // (TC) XC2 is ANDed with the selected clock -#define AT91C_TC_CPCSTOP ((unsigned int) 0x1 << 6) // (TC) Counter Clock Stopped with RC Compare -#define AT91C_TC_LDBSTOP ((unsigned int) 0x1 << 6) // (TC) Counter Clock Stopped with RB Loading -#define AT91C_TC_CPCDIS ((unsigned int) 0x1 << 7) // (TC) Counter Clock Disable with RC Compare -#define AT91C_TC_LDBDIS ((unsigned int) 0x1 << 7) // (TC) Counter Clock Disabled with RB Loading -#define AT91C_TC_ETRGEDG ((unsigned int) 0x3 << 8) // (TC) External Trigger Edge Selection -#define AT91C_TC_ETRGEDG_NONE ((unsigned int) 0x0 << 8) // (TC) Edge: None -#define AT91C_TC_ETRGEDG_RISING ((unsigned int) 0x1 << 8) // (TC) Edge: rising edge -#define AT91C_TC_ETRGEDG_FALLING ((unsigned int) 0x2 << 8) // (TC) Edge: falling edge -#define AT91C_TC_ETRGEDG_BOTH ((unsigned int) 0x3 << 8) // (TC) Edge: each edge -#define AT91C_TC_EEVTEDG ((unsigned int) 0x3 << 8) // (TC) External Event Edge Selection -#define AT91C_TC_EEVTEDG_NONE ((unsigned int) 0x0 << 8) // (TC) Edge: None -#define AT91C_TC_EEVTEDG_RISING ((unsigned int) 0x1 << 8) // (TC) Edge: rising edge -#define AT91C_TC_EEVTEDG_FALLING ((unsigned int) 0x2 << 8) // (TC) Edge: falling edge -#define AT91C_TC_EEVTEDG_BOTH ((unsigned int) 0x3 << 8) // (TC) Edge: each edge -#define AT91C_TC_EEVT ((unsigned int) 0x3 << 10) // (TC) External Event Selection -#define AT91C_TC_EEVT_TIOB ((unsigned int) 0x0 << 10) // (TC) Signal selected as external event: TIOB TIOB direction: input -#define AT91C_TC_EEVT_XC0 ((unsigned int) 0x1 << 10) // (TC) Signal selected as external event: XC0 TIOB direction: output -#define AT91C_TC_EEVT_XC1 ((unsigned int) 0x2 << 10) // (TC) Signal selected as external event: XC1 TIOB direction: output -#define AT91C_TC_EEVT_XC2 ((unsigned int) 0x3 << 10) // (TC) Signal selected as external event: XC2 TIOB direction: output -#define AT91C_TC_ABETRG ((unsigned int) 0x1 << 10) // (TC) TIOA or TIOB External Trigger Selection -#define AT91C_TC_ENETRG ((unsigned int) 0x1 << 12) // (TC) External Event Trigger enable -#define AT91C_TC_WAVESEL ((unsigned int) 0x3 << 13) // (TC) Waveform Selection -#define AT91C_TC_WAVESEL_UP ((unsigned int) 0x0 << 13) // (TC) UP mode without atomatic trigger on RC Compare -#define AT91C_TC_WAVESEL_UPDOWN ((unsigned int) 0x1 << 13) // (TC) UPDOWN mode without automatic trigger on RC Compare -#define AT91C_TC_WAVESEL_UP_AUTO ((unsigned int) 0x2 << 13) // (TC) UP mode with automatic trigger on RC Compare -#define AT91C_TC_WAVESEL_UPDOWN_AUTO ((unsigned int) 0x3 << 13) // (TC) UPDOWN mode with automatic trigger on RC Compare -#define AT91C_TC_CPCTRG ((unsigned int) 0x1 << 14) // (TC) RC Compare Trigger Enable -#define AT91C_TC_WAVE ((unsigned int) 0x1 << 15) // (TC) -#define AT91C_TC_ACPA ((unsigned int) 0x3 << 16) // (TC) RA Compare Effect on TIOA -#define AT91C_TC_ACPA_NONE ((unsigned int) 0x0 << 16) // (TC) Effect: none -#define AT91C_TC_ACPA_SET ((unsigned int) 0x1 << 16) // (TC) Effect: set -#define AT91C_TC_ACPA_CLEAR ((unsigned int) 0x2 << 16) // (TC) Effect: clear -#define AT91C_TC_ACPA_TOGGLE ((unsigned int) 0x3 << 16) // (TC) Effect: toggle -#define AT91C_TC_LDRA ((unsigned int) 0x3 << 16) // (TC) RA Loading Selection -#define AT91C_TC_LDRA_NONE ((unsigned int) 0x0 << 16) // (TC) Edge: None -#define AT91C_TC_LDRA_RISING ((unsigned int) 0x1 << 16) // (TC) Edge: rising edge of TIOA -#define AT91C_TC_LDRA_FALLING ((unsigned int) 0x2 << 16) // (TC) Edge: falling edge of TIOA -#define AT91C_TC_LDRA_BOTH ((unsigned int) 0x3 << 16) // (TC) Edge: each edge of TIOA -#define AT91C_TC_ACPC ((unsigned int) 0x3 << 18) // (TC) RC Compare Effect on TIOA -#define AT91C_TC_ACPC_NONE ((unsigned int) 0x0 << 18) // (TC) Effect: none -#define AT91C_TC_ACPC_SET ((unsigned int) 0x1 << 18) // (TC) Effect: set -#define AT91C_TC_ACPC_CLEAR ((unsigned int) 0x2 << 18) // (TC) Effect: clear -#define AT91C_TC_ACPC_TOGGLE ((unsigned int) 0x3 << 18) // (TC) Effect: toggle -#define AT91C_TC_LDRB ((unsigned int) 0x3 << 18) // (TC) RB Loading Selection -#define AT91C_TC_LDRB_NONE ((unsigned int) 0x0 << 18) // (TC) Edge: None -#define AT91C_TC_LDRB_RISING ((unsigned int) 0x1 << 18) // (TC) Edge: rising edge of TIOA -#define AT91C_TC_LDRB_FALLING ((unsigned int) 0x2 << 18) // (TC) Edge: falling edge of TIOA -#define AT91C_TC_LDRB_BOTH ((unsigned int) 0x3 << 18) // (TC) Edge: each edge of TIOA -#define AT91C_TC_AEEVT ((unsigned int) 0x3 << 20) // (TC) External Event Effect on TIOA -#define AT91C_TC_AEEVT_NONE ((unsigned int) 0x0 << 20) // (TC) Effect: none -#define AT91C_TC_AEEVT_SET ((unsigned int) 0x1 << 20) // (TC) Effect: set -#define AT91C_TC_AEEVT_CLEAR ((unsigned int) 0x2 << 20) // (TC) Effect: clear -#define AT91C_TC_AEEVT_TOGGLE ((unsigned int) 0x3 << 20) // (TC) Effect: toggle -#define AT91C_TC_ASWTRG ((unsigned int) 0x3 << 22) // (TC) Software Trigger Effect on TIOA -#define AT91C_TC_ASWTRG_NONE ((unsigned int) 0x0 << 22) // (TC) Effect: none -#define AT91C_TC_ASWTRG_SET ((unsigned int) 0x1 << 22) // (TC) Effect: set -#define AT91C_TC_ASWTRG_CLEAR ((unsigned int) 0x2 << 22) // (TC) Effect: clear -#define AT91C_TC_ASWTRG_TOGGLE ((unsigned int) 0x3 << 22) // (TC) Effect: toggle -#define AT91C_TC_BCPB ((unsigned int) 0x3 << 24) // (TC) RB Compare Effect on TIOB -#define AT91C_TC_BCPB_NONE ((unsigned int) 0x0 << 24) // (TC) Effect: none -#define AT91C_TC_BCPB_SET ((unsigned int) 0x1 << 24) // (TC) Effect: set -#define AT91C_TC_BCPB_CLEAR ((unsigned int) 0x2 << 24) // (TC) Effect: clear -#define AT91C_TC_BCPB_TOGGLE ((unsigned int) 0x3 << 24) // (TC) Effect: toggle -#define AT91C_TC_BCPC ((unsigned int) 0x3 << 26) // (TC) RC Compare Effect on TIOB -#define AT91C_TC_BCPC_NONE ((unsigned int) 0x0 << 26) // (TC) Effect: none -#define AT91C_TC_BCPC_SET ((unsigned int) 0x1 << 26) // (TC) Effect: set -#define AT91C_TC_BCPC_CLEAR ((unsigned int) 0x2 << 26) // (TC) Effect: clear -#define AT91C_TC_BCPC_TOGGLE ((unsigned int) 0x3 << 26) // (TC) Effect: toggle -#define AT91C_TC_BEEVT ((unsigned int) 0x3 << 28) // (TC) External Event Effect on TIOB -#define AT91C_TC_BEEVT_NONE ((unsigned int) 0x0 << 28) // (TC) Effect: none -#define AT91C_TC_BEEVT_SET ((unsigned int) 0x1 << 28) // (TC) Effect: set -#define AT91C_TC_BEEVT_CLEAR ((unsigned int) 0x2 << 28) // (TC) Effect: clear -#define AT91C_TC_BEEVT_TOGGLE ((unsigned int) 0x3 << 28) // (TC) Effect: toggle -#define AT91C_TC_BSWTRG ((unsigned int) 0x3 << 30) // (TC) Software Trigger Effect on TIOB -#define AT91C_TC_BSWTRG_NONE ((unsigned int) 0x0 << 30) // (TC) Effect: none -#define AT91C_TC_BSWTRG_SET ((unsigned int) 0x1 << 30) // (TC) Effect: set -#define AT91C_TC_BSWTRG_CLEAR ((unsigned int) 0x2 << 30) // (TC) Effect: clear -#define AT91C_TC_BSWTRG_TOGGLE ((unsigned int) 0x3 << 30) // (TC) Effect: toggle -// -------- TC_SR : (TC Offset: 0x20) TC Channel Status Register -------- -#define AT91C_TC_COVFS ((unsigned int) 0x1 << 0) // (TC) Counter Overflow -#define AT91C_TC_LOVRS ((unsigned int) 0x1 << 1) // (TC) Load Overrun -#define AT91C_TC_CPAS ((unsigned int) 0x1 << 2) // (TC) RA Compare -#define AT91C_TC_CPBS ((unsigned int) 0x1 << 3) // (TC) RB Compare -#define AT91C_TC_CPCS ((unsigned int) 0x1 << 4) // (TC) RC Compare -#define AT91C_TC_LDRAS ((unsigned int) 0x1 << 5) // (TC) RA Loading -#define AT91C_TC_LDRBS ((unsigned int) 0x1 << 6) // (TC) RB Loading -#define AT91C_TC_ETRGS ((unsigned int) 0x1 << 7) // (TC) External Trigger -#define AT91C_TC_CLKSTA ((unsigned int) 0x1 << 16) // (TC) Clock Enabling -#define AT91C_TC_MTIOA ((unsigned int) 0x1 << 17) // (TC) TIOA Mirror -#define AT91C_TC_MTIOB ((unsigned int) 0x1 << 18) // (TC) TIOA Mirror -// -------- TC_IER : (TC Offset: 0x24) TC Channel Interrupt Enable Register -------- -// -------- TC_IDR : (TC Offset: 0x28) TC Channel Interrupt Disable Register -------- -// -------- TC_IMR : (TC Offset: 0x2c) TC Channel Interrupt Mask Register -------- +/* -------- TC_CCR : (TC Offset: 0x0) TC Channel Control Register -------- */ +#define AT91C_TC_CLKEN ( ( unsigned int ) 0x1 << 0 ) /* (TC) Counter Clock Enable Command */ +#define AT91C_TC_CLKDIS ( ( unsigned int ) 0x1 << 1 ) /* (TC) Counter Clock Disable Command */ +#define AT91C_TC_SWTRG ( ( unsigned int ) 0x1 << 2 ) /* (TC) Software Trigger Command */ +/* -------- TC_CMR : (TC Offset: 0x4) TC Channel Mode Register: Capture Mode / Waveform Mode -------- */ +#define AT91C_TC_CLKS ( ( unsigned int ) 0x7 << 0 ) /* (TC) Clock Selection */ +#define AT91C_TC_CLKS_TIMER_DIV1_CLOCK ( ( unsigned int ) 0x0 ) /* (TC) Clock selected: TIMER_DIV1_CLOCK */ +#define AT91C_TC_CLKS_TIMER_DIV2_CLOCK ( ( unsigned int ) 0x1 ) /* (TC) Clock selected: TIMER_DIV2_CLOCK */ +#define AT91C_TC_CLKS_TIMER_DIV3_CLOCK ( ( unsigned int ) 0x2 ) /* (TC) Clock selected: TIMER_DIV3_CLOCK */ +#define AT91C_TC_CLKS_TIMER_DIV4_CLOCK ( ( unsigned int ) 0x3 ) /* (TC) Clock selected: TIMER_DIV4_CLOCK */ +#define AT91C_TC_CLKS_TIMER_DIV5_CLOCK ( ( unsigned int ) 0x4 ) /* (TC) Clock selected: TIMER_DIV5_CLOCK */ +#define AT91C_TC_CLKS_XC0 ( ( unsigned int ) 0x5 ) /* (TC) Clock selected: XC0 */ +#define AT91C_TC_CLKS_XC1 ( ( unsigned int ) 0x6 ) /* (TC) Clock selected: XC1 */ +#define AT91C_TC_CLKS_XC2 ( ( unsigned int ) 0x7 ) /* (TC) Clock selected: XC2 */ +#define AT91C_TC_CLKI ( ( unsigned int ) 0x1 << 3 ) /* (TC) Clock Invert */ +#define AT91C_TC_BURST ( ( unsigned int ) 0x3 << 4 ) /* (TC) Burst Signal Selection */ +#define AT91C_TC_BURST_NONE ( ( unsigned int ) 0x0 << 4 ) /* (TC) The clock is not gated by an external signal */ +#define AT91C_TC_BURST_XC0 ( ( unsigned int ) 0x1 << 4 ) /* (TC) XC0 is ANDed with the selected clock */ +#define AT91C_TC_BURST_XC1 ( ( unsigned int ) 0x2 << 4 ) /* (TC) XC1 is ANDed with the selected clock */ +#define AT91C_TC_BURST_XC2 ( ( unsigned int ) 0x3 << 4 ) /* (TC) XC2 is ANDed with the selected clock */ +#define AT91C_TC_CPCSTOP ( ( unsigned int ) 0x1 << 6 ) /* (TC) Counter Clock Stopped with RC Compare */ +#define AT91C_TC_LDBSTOP ( ( unsigned int ) 0x1 << 6 ) /* (TC) Counter Clock Stopped with RB Loading */ +#define AT91C_TC_CPCDIS ( ( unsigned int ) 0x1 << 7 ) /* (TC) Counter Clock Disable with RC Compare */ +#define AT91C_TC_LDBDIS ( ( unsigned int ) 0x1 << 7 ) /* (TC) Counter Clock Disabled with RB Loading */ +#define AT91C_TC_ETRGEDG ( ( unsigned int ) 0x3 << 8 ) /* (TC) External Trigger Edge Selection */ +#define AT91C_TC_ETRGEDG_NONE ( ( unsigned int ) 0x0 << 8 ) /* (TC) Edge: None */ +#define AT91C_TC_ETRGEDG_RISING ( ( unsigned int ) 0x1 << 8 ) /* (TC) Edge: rising edge */ +#define AT91C_TC_ETRGEDG_FALLING ( ( unsigned int ) 0x2 << 8 ) /* (TC) Edge: falling edge */ +#define AT91C_TC_ETRGEDG_BOTH ( ( unsigned int ) 0x3 << 8 ) /* (TC) Edge: each edge */ +#define AT91C_TC_EEVTEDG ( ( unsigned int ) 0x3 << 8 ) /* (TC) External Event Edge Selection */ +#define AT91C_TC_EEVTEDG_NONE ( ( unsigned int ) 0x0 << 8 ) /* (TC) Edge: None */ +#define AT91C_TC_EEVTEDG_RISING ( ( unsigned int ) 0x1 << 8 ) /* (TC) Edge: rising edge */ +#define AT91C_TC_EEVTEDG_FALLING ( ( unsigned int ) 0x2 << 8 ) /* (TC) Edge: falling edge */ +#define AT91C_TC_EEVTEDG_BOTH ( ( unsigned int ) 0x3 << 8 ) /* (TC) Edge: each edge */ +#define AT91C_TC_EEVT ( ( unsigned int ) 0x3 << 10 ) /* (TC) External Event Selection */ +#define AT91C_TC_EEVT_TIOB ( ( unsigned int ) 0x0 << 10 ) /* (TC) Signal selected as external event: TIOB TIOB direction: input */ +#define AT91C_TC_EEVT_XC0 ( ( unsigned int ) 0x1 << 10 ) /* (TC) Signal selected as external event: XC0 TIOB direction: output */ +#define AT91C_TC_EEVT_XC1 ( ( unsigned int ) 0x2 << 10 ) /* (TC) Signal selected as external event: XC1 TIOB direction: output */ +#define AT91C_TC_EEVT_XC2 ( ( unsigned int ) 0x3 << 10 ) /* (TC) Signal selected as external event: XC2 TIOB direction: output */ +#define AT91C_TC_ABETRG ( ( unsigned int ) 0x1 << 10 ) /* (TC) TIOA or TIOB External Trigger Selection */ +#define AT91C_TC_ENETRG ( ( unsigned int ) 0x1 << 12 ) /* (TC) External Event Trigger enable */ +#define AT91C_TC_WAVESEL ( ( unsigned int ) 0x3 << 13 ) /* (TC) Waveform Selection */ +#define AT91C_TC_WAVESEL_UP ( ( unsigned int ) 0x0 << 13 ) /* (TC) UP mode without atomatic trigger on RC Compare */ +#define AT91C_TC_WAVESEL_UPDOWN ( ( unsigned int ) 0x1 << 13 ) /* (TC) UPDOWN mode without automatic trigger on RC Compare */ +#define AT91C_TC_WAVESEL_UP_AUTO ( ( unsigned int ) 0x2 << 13 ) /* (TC) UP mode with automatic trigger on RC Compare */ +#define AT91C_TC_WAVESEL_UPDOWN_AUTO ( ( unsigned int ) 0x3 << 13 ) /* (TC) UPDOWN mode with automatic trigger on RC Compare */ +#define AT91C_TC_CPCTRG ( ( unsigned int ) 0x1 << 14 ) /* (TC) RC Compare Trigger Enable */ +#define AT91C_TC_WAVE ( ( unsigned int ) 0x1 << 15 ) /* (TC) */ +#define AT91C_TC_ACPA ( ( unsigned int ) 0x3 << 16 ) /* (TC) RA Compare Effect on TIOA */ +#define AT91C_TC_ACPA_NONE ( ( unsigned int ) 0x0 << 16 ) /* (TC) Effect: none */ +#define AT91C_TC_ACPA_SET ( ( unsigned int ) 0x1 << 16 ) /* (TC) Effect: set */ +#define AT91C_TC_ACPA_CLEAR ( ( unsigned int ) 0x2 << 16 ) /* (TC) Effect: clear */ +#define AT91C_TC_ACPA_TOGGLE ( ( unsigned int ) 0x3 << 16 ) /* (TC) Effect: toggle */ +#define AT91C_TC_LDRA ( ( unsigned int ) 0x3 << 16 ) /* (TC) RA Loading Selection */ +#define AT91C_TC_LDRA_NONE ( ( unsigned int ) 0x0 << 16 ) /* (TC) Edge: None */ +#define AT91C_TC_LDRA_RISING ( ( unsigned int ) 0x1 << 16 ) /* (TC) Edge: rising edge of TIOA */ +#define AT91C_TC_LDRA_FALLING ( ( unsigned int ) 0x2 << 16 ) /* (TC) Edge: falling edge of TIOA */ +#define AT91C_TC_LDRA_BOTH ( ( unsigned int ) 0x3 << 16 ) /* (TC) Edge: each edge of TIOA */ +#define AT91C_TC_ACPC ( ( unsigned int ) 0x3 << 18 ) /* (TC) RC Compare Effect on TIOA */ +#define AT91C_TC_ACPC_NONE ( ( unsigned int ) 0x0 << 18 ) /* (TC) Effect: none */ +#define AT91C_TC_ACPC_SET ( ( unsigned int ) 0x1 << 18 ) /* (TC) Effect: set */ +#define AT91C_TC_ACPC_CLEAR ( ( unsigned int ) 0x2 << 18 ) /* (TC) Effect: clear */ +#define AT91C_TC_ACPC_TOGGLE ( ( unsigned int ) 0x3 << 18 ) /* (TC) Effect: toggle */ +#define AT91C_TC_LDRB ( ( unsigned int ) 0x3 << 18 ) /* (TC) RB Loading Selection */ +#define AT91C_TC_LDRB_NONE ( ( unsigned int ) 0x0 << 18 ) /* (TC) Edge: None */ +#define AT91C_TC_LDRB_RISING ( ( unsigned int ) 0x1 << 18 ) /* (TC) Edge: rising edge of TIOA */ +#define AT91C_TC_LDRB_FALLING ( ( unsigned int ) 0x2 << 18 ) /* (TC) Edge: falling edge of TIOA */ +#define AT91C_TC_LDRB_BOTH ( ( unsigned int ) 0x3 << 18 ) /* (TC) Edge: each edge of TIOA */ +#define AT91C_TC_AEEVT ( ( unsigned int ) 0x3 << 20 ) /* (TC) External Event Effect on TIOA */ +#define AT91C_TC_AEEVT_NONE ( ( unsigned int ) 0x0 << 20 ) /* (TC) Effect: none */ +#define AT91C_TC_AEEVT_SET ( ( unsigned int ) 0x1 << 20 ) /* (TC) Effect: set */ +#define AT91C_TC_AEEVT_CLEAR ( ( unsigned int ) 0x2 << 20 ) /* (TC) Effect: clear */ +#define AT91C_TC_AEEVT_TOGGLE ( ( unsigned int ) 0x3 << 20 ) /* (TC) Effect: toggle */ +#define AT91C_TC_ASWTRG ( ( unsigned int ) 0x3 << 22 ) /* (TC) Software Trigger Effect on TIOA */ +#define AT91C_TC_ASWTRG_NONE ( ( unsigned int ) 0x0 << 22 ) /* (TC) Effect: none */ +#define AT91C_TC_ASWTRG_SET ( ( unsigned int ) 0x1 << 22 ) /* (TC) Effect: set */ +#define AT91C_TC_ASWTRG_CLEAR ( ( unsigned int ) 0x2 << 22 ) /* (TC) Effect: clear */ +#define AT91C_TC_ASWTRG_TOGGLE ( ( unsigned int ) 0x3 << 22 ) /* (TC) Effect: toggle */ +#define AT91C_TC_BCPB ( ( unsigned int ) 0x3 << 24 ) /* (TC) RB Compare Effect on TIOB */ +#define AT91C_TC_BCPB_NONE ( ( unsigned int ) 0x0 << 24 ) /* (TC) Effect: none */ +#define AT91C_TC_BCPB_SET ( ( unsigned int ) 0x1 << 24 ) /* (TC) Effect: set */ +#define AT91C_TC_BCPB_CLEAR ( ( unsigned int ) 0x2 << 24 ) /* (TC) Effect: clear */ +#define AT91C_TC_BCPB_TOGGLE ( ( unsigned int ) 0x3 << 24 ) /* (TC) Effect: toggle */ +#define AT91C_TC_BCPC ( ( unsigned int ) 0x3 << 26 ) /* (TC) RC Compare Effect on TIOB */ +#define AT91C_TC_BCPC_NONE ( ( unsigned int ) 0x0 << 26 ) /* (TC) Effect: none */ +#define AT91C_TC_BCPC_SET ( ( unsigned int ) 0x1 << 26 ) /* (TC) Effect: set */ +#define AT91C_TC_BCPC_CLEAR ( ( unsigned int ) 0x2 << 26 ) /* (TC) Effect: clear */ +#define AT91C_TC_BCPC_TOGGLE ( ( unsigned int ) 0x3 << 26 ) /* (TC) Effect: toggle */ +#define AT91C_TC_BEEVT ( ( unsigned int ) 0x3 << 28 ) /* (TC) External Event Effect on TIOB */ +#define AT91C_TC_BEEVT_NONE ( ( unsigned int ) 0x0 << 28 ) /* (TC) Effect: none */ +#define AT91C_TC_BEEVT_SET ( ( unsigned int ) 0x1 << 28 ) /* (TC) Effect: set */ +#define AT91C_TC_BEEVT_CLEAR ( ( unsigned int ) 0x2 << 28 ) /* (TC) Effect: clear */ +#define AT91C_TC_BEEVT_TOGGLE ( ( unsigned int ) 0x3 << 28 ) /* (TC) Effect: toggle */ +#define AT91C_TC_BSWTRG ( ( unsigned int ) 0x3 << 30 ) /* (TC) Software Trigger Effect on TIOB */ +#define AT91C_TC_BSWTRG_NONE ( ( unsigned int ) 0x0 << 30 ) /* (TC) Effect: none */ +#define AT91C_TC_BSWTRG_SET ( ( unsigned int ) 0x1 << 30 ) /* (TC) Effect: set */ +#define AT91C_TC_BSWTRG_CLEAR ( ( unsigned int ) 0x2 << 30 ) /* (TC) Effect: clear */ +#define AT91C_TC_BSWTRG_TOGGLE ( ( unsigned int ) 0x3 << 30 ) /* (TC) Effect: toggle */ +/* -------- TC_SR : (TC Offset: 0x20) TC Channel Status Register -------- */ +#define AT91C_TC_COVFS ( ( unsigned int ) 0x1 << 0 ) /* (TC) Counter Overflow */ +#define AT91C_TC_LOVRS ( ( unsigned int ) 0x1 << 1 ) /* (TC) Load Overrun */ +#define AT91C_TC_CPAS ( ( unsigned int ) 0x1 << 2 ) /* (TC) RA Compare */ +#define AT91C_TC_CPBS ( ( unsigned int ) 0x1 << 3 ) /* (TC) RB Compare */ +#define AT91C_TC_CPCS ( ( unsigned int ) 0x1 << 4 ) /* (TC) RC Compare */ +#define AT91C_TC_LDRAS ( ( unsigned int ) 0x1 << 5 ) /* (TC) RA Loading */ +#define AT91C_TC_LDRBS ( ( unsigned int ) 0x1 << 6 ) /* (TC) RB Loading */ +#define AT91C_TC_ETRGS ( ( unsigned int ) 0x1 << 7 ) /* (TC) External Trigger */ +#define AT91C_TC_CLKSTA ( ( unsigned int ) 0x1 << 16 ) /* (TC) Clock Enabling */ +#define AT91C_TC_MTIOA ( ( unsigned int ) 0x1 << 17 ) /* (TC) TIOA Mirror */ +#define AT91C_TC_MTIOB ( ( unsigned int ) 0x1 << 18 ) /* (TC) TIOA Mirror */ +/* -------- TC_IER : (TC Offset: 0x24) TC Channel Interrupt Enable Register -------- */ +/* -------- TC_IDR : (TC Offset: 0x28) TC Channel Interrupt Disable Register -------- */ +/* -------- TC_IMR : (TC Offset: 0x2c) TC Channel Interrupt Mask Register -------- */ -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Timer Counter Interface -// ***************************************************************************** -typedef struct _AT91S_TCB { - AT91S_TC TCB_TC0; // TC Channel 0 - AT91_REG Reserved0[4]; // - AT91S_TC TCB_TC1; // TC Channel 1 - AT91_REG Reserved1[4]; // - AT91S_TC TCB_TC2; // TC Channel 2 - AT91_REG Reserved2[4]; // - AT91_REG TCB_BCR; // TC Block Control Register - AT91_REG TCB_BMR; // TC Block Mode Register -} AT91S_TCB, *AT91PS_TCB; +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR Timer Counter Interface */ +/* ***************************************************************************** */ +typedef struct _AT91S_TCB +{ + AT91S_TC TCB_TC0; /* TC Channel 0 */ + AT91_REG Reserved0[ 4 ]; /* */ + AT91S_TC TCB_TC1; /* TC Channel 1 */ + AT91_REG Reserved1[ 4 ]; /* */ + AT91S_TC TCB_TC2; /* TC Channel 2 */ + AT91_REG Reserved2[ 4 ]; /* */ + AT91_REG TCB_BCR; /* TC Block Control Register */ + AT91_REG TCB_BMR; /* TC Block Mode Register */ +} AT91S_TCB, * AT91PS_TCB; -// -------- TCB_BCR : (TCB Offset: 0xc0) TC Block Control Register -------- -#define AT91C_TCB_SYNC ((unsigned int) 0x1 << 0) // (TCB) Synchro Command -// -------- TCB_BMR : (TCB Offset: 0xc4) TC Block Mode Register -------- -#define AT91C_TCB_TC0XC0S ((unsigned int) 0x3 << 0) // (TCB) External Clock Signal 0 Selection -#define AT91C_TCB_TC0XC0S_TCLK0 ((unsigned int) 0x0) // (TCB) TCLK0 connected to XC0 -#define AT91C_TCB_TC0XC0S_NONE ((unsigned int) 0x1) // (TCB) None signal connected to XC0 -#define AT91C_TCB_TC0XC0S_TIOA1 ((unsigned int) 0x2) // (TCB) TIOA1 connected to XC0 -#define AT91C_TCB_TC0XC0S_TIOA2 ((unsigned int) 0x3) // (TCB) TIOA2 connected to XC0 -#define AT91C_TCB_TC1XC1S ((unsigned int) 0x3 << 2) // (TCB) External Clock Signal 1 Selection -#define AT91C_TCB_TC1XC1S_TCLK1 ((unsigned int) 0x0 << 2) // (TCB) TCLK1 connected to XC1 -#define AT91C_TCB_TC1XC1S_NONE ((unsigned int) 0x1 << 2) // (TCB) None signal connected to XC1 -#define AT91C_TCB_TC1XC1S_TIOA0 ((unsigned int) 0x2 << 2) // (TCB) TIOA0 connected to XC1 -#define AT91C_TCB_TC1XC1S_TIOA2 ((unsigned int) 0x3 << 2) // (TCB) TIOA2 connected to XC1 -#define AT91C_TCB_TC2XC2S ((unsigned int) 0x3 << 4) // (TCB) External Clock Signal 2 Selection -#define AT91C_TCB_TC2XC2S_TCLK2 ((unsigned int) 0x0 << 4) // (TCB) TCLK2 connected to XC2 -#define AT91C_TCB_TC2XC2S_NONE ((unsigned int) 0x1 << 4) // (TCB) None signal connected to XC2 -#define AT91C_TCB_TC2XC2S_TIOA0 ((unsigned int) 0x2 << 4) // (TCB) TIOA0 connected to XC2 -#define AT91C_TCB_TC2XC2S_TIOA1 ((unsigned int) 0x3 << 4) // (TCB) TIOA2 connected to XC2 +/* -------- TCB_BCR : (TCB Offset: 0xc0) TC Block Control Register -------- */ +#define AT91C_TCB_SYNC ( ( unsigned int ) 0x1 << 0 ) /* (TCB) Synchro Command */ +/* -------- TCB_BMR : (TCB Offset: 0xc4) TC Block Mode Register -------- */ +#define AT91C_TCB_TC0XC0S ( ( unsigned int ) 0x3 << 0 ) /* (TCB) External Clock Signal 0 Selection */ +#define AT91C_TCB_TC0XC0S_TCLK0 ( ( unsigned int ) 0x0 ) /* (TCB) TCLK0 connected to XC0 */ +#define AT91C_TCB_TC0XC0S_NONE ( ( unsigned int ) 0x1 ) /* (TCB) None signal connected to XC0 */ +#define AT91C_TCB_TC0XC0S_TIOA1 ( ( unsigned int ) 0x2 ) /* (TCB) TIOA1 connected to XC0 */ +#define AT91C_TCB_TC0XC0S_TIOA2 ( ( unsigned int ) 0x3 ) /* (TCB) TIOA2 connected to XC0 */ +#define AT91C_TCB_TC1XC1S ( ( unsigned int ) 0x3 << 2 ) /* (TCB) External Clock Signal 1 Selection */ +#define AT91C_TCB_TC1XC1S_TCLK1 ( ( unsigned int ) 0x0 << 2 ) /* (TCB) TCLK1 connected to XC1 */ +#define AT91C_TCB_TC1XC1S_NONE ( ( unsigned int ) 0x1 << 2 ) /* (TCB) None signal connected to XC1 */ +#define AT91C_TCB_TC1XC1S_TIOA0 ( ( unsigned int ) 0x2 << 2 ) /* (TCB) TIOA0 connected to XC1 */ +#define AT91C_TCB_TC1XC1S_TIOA2 ( ( unsigned int ) 0x3 << 2 ) /* (TCB) TIOA2 connected to XC1 */ +#define AT91C_TCB_TC2XC2S ( ( unsigned int ) 0x3 << 4 ) /* (TCB) External Clock Signal 2 Selection */ +#define AT91C_TCB_TC2XC2S_TCLK2 ( ( unsigned int ) 0x0 << 4 ) /* (TCB) TCLK2 connected to XC2 */ +#define AT91C_TCB_TC2XC2S_NONE ( ( unsigned int ) 0x1 << 4 ) /* (TCB) None signal connected to XC2 */ +#define AT91C_TCB_TC2XC2S_TIOA0 ( ( unsigned int ) 0x2 << 4 ) /* (TCB) TIOA0 connected to XC2 */ +#define AT91C_TCB_TC2XC2S_TIOA1 ( ( unsigned int ) 0x3 << 4 ) /* (TCB) TIOA2 connected to XC2 */ -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Control Area Network MailBox Interface -// ***************************************************************************** -typedef struct _AT91S_CAN_MB { - AT91_REG CAN_MB_MMR; // MailBox Mode Register - AT91_REG CAN_MB_MAM; // MailBox Acceptance Mask Register - AT91_REG CAN_MB_MID; // MailBox ID Register - AT91_REG CAN_MB_MFID; // MailBox Family ID Register - AT91_REG CAN_MB_MSR; // MailBox Status Register - AT91_REG CAN_MB_MDL; // MailBox Data Low Register - AT91_REG CAN_MB_MDH; // MailBox Data High Register - AT91_REG CAN_MB_MCR; // MailBox Control Register -} AT91S_CAN_MB, *AT91PS_CAN_MB; +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR Control Area Network MailBox Interface */ +/* ***************************************************************************** */ +typedef struct _AT91S_CAN_MB +{ + AT91_REG CAN_MB_MMR; /* MailBox Mode Register */ + AT91_REG CAN_MB_MAM; /* MailBox Acceptance Mask Register */ + AT91_REG CAN_MB_MID; /* MailBox ID Register */ + AT91_REG CAN_MB_MFID; /* MailBox Family ID Register */ + AT91_REG CAN_MB_MSR; /* MailBox Status Register */ + AT91_REG CAN_MB_MDL; /* MailBox Data Low Register */ + AT91_REG CAN_MB_MDH; /* MailBox Data High Register */ + AT91_REG CAN_MB_MCR; /* MailBox Control Register */ +} AT91S_CAN_MB, * AT91PS_CAN_MB; -// -------- CAN_MMR : (CAN_MB Offset: 0x0) CAN Message Mode Register -------- -#define AT91C_CAN_MTIMEMARK ((unsigned int) 0xFFFF << 0) // (CAN_MB) Mailbox Timemark -#define AT91C_CAN_PRIOR ((unsigned int) 0xF << 16) // (CAN_MB) Mailbox Priority -#define AT91C_CAN_MOT ((unsigned int) 0x7 << 24) // (CAN_MB) Mailbox Object Type -#define AT91C_CAN_MOT_DIS ((unsigned int) 0x0 << 24) // (CAN_MB) -#define AT91C_CAN_MOT_RX ((unsigned int) 0x1 << 24) // (CAN_MB) -#define AT91C_CAN_MOT_RXOVERWRITE ((unsigned int) 0x2 << 24) // (CAN_MB) -#define AT91C_CAN_MOT_TX ((unsigned int) 0x3 << 24) // (CAN_MB) -#define AT91C_CAN_MOT_CONSUMER ((unsigned int) 0x4 << 24) // (CAN_MB) -#define AT91C_CAN_MOT_PRODUCER ((unsigned int) 0x5 << 24) // (CAN_MB) -// -------- CAN_MAM : (CAN_MB Offset: 0x4) CAN Message Acceptance Mask Register -------- -#define AT91C_CAN_MIDvB ((unsigned int) 0x3FFFF << 0) // (CAN_MB) Complementary bits for identifier in extended mode -#define AT91C_CAN_MIDvA ((unsigned int) 0x7FF << 18) // (CAN_MB) Identifier for standard frame mode -#define AT91C_CAN_MIDE ((unsigned int) 0x1 << 29) // (CAN_MB) Identifier Version -// -------- CAN_MID : (CAN_MB Offset: 0x8) CAN Message ID Register -------- -// -------- CAN_MFID : (CAN_MB Offset: 0xc) CAN Message Family ID Register -------- -// -------- CAN_MSR : (CAN_MB Offset: 0x10) CAN Message Status Register -------- -#define AT91C_CAN_MTIMESTAMP ((unsigned int) 0xFFFF << 0) // (CAN_MB) Timer Value -#define AT91C_CAN_MDLC ((unsigned int) 0xF << 16) // (CAN_MB) Mailbox Data Length Code -#define AT91C_CAN_MRTR ((unsigned int) 0x1 << 20) // (CAN_MB) Mailbox Remote Transmission Request -#define AT91C_CAN_MABT ((unsigned int) 0x1 << 22) // (CAN_MB) Mailbox Message Abort -#define AT91C_CAN_MRDY ((unsigned int) 0x1 << 23) // (CAN_MB) Mailbox Ready -#define AT91C_CAN_MMI ((unsigned int) 0x1 << 24) // (CAN_MB) Mailbox Message Ignored -// -------- CAN_MDL : (CAN_MB Offset: 0x14) CAN Message Data Low Register -------- -// -------- CAN_MDH : (CAN_MB Offset: 0x18) CAN Message Data High Register -------- -// -------- CAN_MCR : (CAN_MB Offset: 0x1c) CAN Message Control Register -------- -#define AT91C_CAN_MACR ((unsigned int) 0x1 << 22) // (CAN_MB) Abort Request for Mailbox -#define AT91C_CAN_MTCR ((unsigned int) 0x1 << 23) // (CAN_MB) Mailbox Transfer Command +/* -------- CAN_MMR : (CAN_MB Offset: 0x0) CAN Message Mode Register -------- */ +#define AT91C_CAN_MTIMEMARK ( ( unsigned int ) 0xFFFF << 0 ) /* (CAN_MB) Mailbox Timemark */ +#define AT91C_CAN_PRIOR ( ( unsigned int ) 0xF << 16 ) /* (CAN_MB) Mailbox Priority */ +#define AT91C_CAN_MOT ( ( unsigned int ) 0x7 << 24 ) /* (CAN_MB) Mailbox Object Type */ +#define AT91C_CAN_MOT_DIS ( ( unsigned int ) 0x0 << 24 ) /* (CAN_MB) */ +#define AT91C_CAN_MOT_RX ( ( unsigned int ) 0x1 << 24 ) /* (CAN_MB) */ +#define AT91C_CAN_MOT_RXOVERWRITE ( ( unsigned int ) 0x2 << 24 ) /* (CAN_MB) */ +#define AT91C_CAN_MOT_TX ( ( unsigned int ) 0x3 << 24 ) /* (CAN_MB) */ +#define AT91C_CAN_MOT_CONSUMER ( ( unsigned int ) 0x4 << 24 ) /* (CAN_MB) */ +#define AT91C_CAN_MOT_PRODUCER ( ( unsigned int ) 0x5 << 24 ) /* (CAN_MB) */ +/* -------- CAN_MAM : (CAN_MB Offset: 0x4) CAN Message Acceptance Mask Register -------- */ +#define AT91C_CAN_MIDvB ( ( unsigned int ) 0x3FFFF << 0 ) /* (CAN_MB) Complementary bits for identifier in extended mode */ +#define AT91C_CAN_MIDvA ( ( unsigned int ) 0x7FF << 18 ) /* (CAN_MB) Identifier for standard frame mode */ +#define AT91C_CAN_MIDE ( ( unsigned int ) 0x1 << 29 ) /* (CAN_MB) Identifier Version */ +/* -------- CAN_MID : (CAN_MB Offset: 0x8) CAN Message ID Register -------- */ +/* -------- CAN_MFID : (CAN_MB Offset: 0xc) CAN Message Family ID Register -------- */ +/* -------- CAN_MSR : (CAN_MB Offset: 0x10) CAN Message Status Register -------- */ +#define AT91C_CAN_MTIMESTAMP ( ( unsigned int ) 0xFFFF << 0 ) /* (CAN_MB) Timer Value */ +#define AT91C_CAN_MDLC ( ( unsigned int ) 0xF << 16 ) /* (CAN_MB) Mailbox Data Length Code */ +#define AT91C_CAN_MRTR ( ( unsigned int ) 0x1 << 20 ) /* (CAN_MB) Mailbox Remote Transmission Request */ +#define AT91C_CAN_MABT ( ( unsigned int ) 0x1 << 22 ) /* (CAN_MB) Mailbox Message Abort */ +#define AT91C_CAN_MRDY ( ( unsigned int ) 0x1 << 23 ) /* (CAN_MB) Mailbox Ready */ +#define AT91C_CAN_MMI ( ( unsigned int ) 0x1 << 24 ) /* (CAN_MB) Mailbox Message Ignored */ +/* -------- CAN_MDL : (CAN_MB Offset: 0x14) CAN Message Data Low Register -------- */ +/* -------- CAN_MDH : (CAN_MB Offset: 0x18) CAN Message Data High Register -------- */ +/* -------- CAN_MCR : (CAN_MB Offset: 0x1c) CAN Message Control Register -------- */ +#define AT91C_CAN_MACR ( ( unsigned int ) 0x1 << 22 ) /* (CAN_MB) Abort Request for Mailbox */ +#define AT91C_CAN_MTCR ( ( unsigned int ) 0x1 << 23 ) /* (CAN_MB) Mailbox Transfer Command */ -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Control Area Network Interface -// ***************************************************************************** -typedef struct _AT91S_CAN { - AT91_REG CAN_MR; // Mode Register - AT91_REG CAN_IER; // Interrupt Enable Register - AT91_REG CAN_IDR; // Interrupt Disable Register - AT91_REG CAN_IMR; // Interrupt Mask Register - AT91_REG CAN_SR; // Status Register - AT91_REG CAN_BR; // Baudrate Register - AT91_REG CAN_TIM; // Timer Register - AT91_REG CAN_TIMESTP; // Time Stamp Register - AT91_REG CAN_ECR; // Error Counter Register - AT91_REG CAN_TCR; // Transfer Command Register - AT91_REG CAN_ACR; // Abort Command Register - AT91_REG Reserved0[52]; // - AT91_REG CAN_VR; // Version Register - AT91_REG Reserved1[64]; // - AT91S_CAN_MB CAN_MB0; // CAN Mailbox 0 - AT91S_CAN_MB CAN_MB1; // CAN Mailbox 1 - AT91S_CAN_MB CAN_MB2; // CAN Mailbox 2 - AT91S_CAN_MB CAN_MB3; // CAN Mailbox 3 - AT91S_CAN_MB CAN_MB4; // CAN Mailbox 4 - AT91S_CAN_MB CAN_MB5; // CAN Mailbox 5 - AT91S_CAN_MB CAN_MB6; // CAN Mailbox 6 - AT91S_CAN_MB CAN_MB7; // CAN Mailbox 7 - AT91S_CAN_MB CAN_MB8; // CAN Mailbox 8 - AT91S_CAN_MB CAN_MB9; // CAN Mailbox 9 - AT91S_CAN_MB CAN_MB10; // CAN Mailbox 10 - AT91S_CAN_MB CAN_MB11; // CAN Mailbox 11 - AT91S_CAN_MB CAN_MB12; // CAN Mailbox 12 - AT91S_CAN_MB CAN_MB13; // CAN Mailbox 13 - AT91S_CAN_MB CAN_MB14; // CAN Mailbox 14 - AT91S_CAN_MB CAN_MB15; // CAN Mailbox 15 -} AT91S_CAN, *AT91PS_CAN; +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR Control Area Network Interface */ +/* ***************************************************************************** */ +typedef struct _AT91S_CAN +{ + AT91_REG CAN_MR; /* Mode Register */ + AT91_REG CAN_IER; /* Interrupt Enable Register */ + AT91_REG CAN_IDR; /* Interrupt Disable Register */ + AT91_REG CAN_IMR; /* Interrupt Mask Register */ + AT91_REG CAN_SR; /* Status Register */ + AT91_REG CAN_BR; /* Baudrate Register */ + AT91_REG CAN_TIM; /* Timer Register */ + AT91_REG CAN_TIMESTP; /* Time Stamp Register */ + AT91_REG CAN_ECR; /* Error Counter Register */ + AT91_REG CAN_TCR; /* Transfer Command Register */ + AT91_REG CAN_ACR; /* Abort Command Register */ + AT91_REG Reserved0[ 52 ]; /* */ + AT91_REG CAN_VR; /* Version Register */ + AT91_REG Reserved1[ 64 ]; /* */ + AT91S_CAN_MB CAN_MB0; /* CAN Mailbox 0 */ + AT91S_CAN_MB CAN_MB1; /* CAN Mailbox 1 */ + AT91S_CAN_MB CAN_MB2; /* CAN Mailbox 2 */ + AT91S_CAN_MB CAN_MB3; /* CAN Mailbox 3 */ + AT91S_CAN_MB CAN_MB4; /* CAN Mailbox 4 */ + AT91S_CAN_MB CAN_MB5; /* CAN Mailbox 5 */ + AT91S_CAN_MB CAN_MB6; /* CAN Mailbox 6 */ + AT91S_CAN_MB CAN_MB7; /* CAN Mailbox 7 */ + AT91S_CAN_MB CAN_MB8; /* CAN Mailbox 8 */ + AT91S_CAN_MB CAN_MB9; /* CAN Mailbox 9 */ + AT91S_CAN_MB CAN_MB10; /* CAN Mailbox 10 */ + AT91S_CAN_MB CAN_MB11; /* CAN Mailbox 11 */ + AT91S_CAN_MB CAN_MB12; /* CAN Mailbox 12 */ + AT91S_CAN_MB CAN_MB13; /* CAN Mailbox 13 */ + AT91S_CAN_MB CAN_MB14; /* CAN Mailbox 14 */ + AT91S_CAN_MB CAN_MB15; /* CAN Mailbox 15 */ +} AT91S_CAN, * AT91PS_CAN; -// -------- CAN_MR : (CAN Offset: 0x0) CAN Mode Register -------- -#define AT91C_CAN_CANEN ((unsigned int) 0x1 << 0) // (CAN) CAN Controller Enable -#define AT91C_CAN_LPM ((unsigned int) 0x1 << 1) // (CAN) Disable/Enable Low Power Mode -#define AT91C_CAN_ABM ((unsigned int) 0x1 << 2) // (CAN) Disable/Enable Autobaud/Listen Mode -#define AT91C_CAN_OVL ((unsigned int) 0x1 << 3) // (CAN) Disable/Enable Overload Frame -#define AT91C_CAN_TEOF ((unsigned int) 0x1 << 4) // (CAN) Time Stamp messages at each end of Frame -#define AT91C_CAN_TTM ((unsigned int) 0x1 << 5) // (CAN) Disable/Enable Time Trigger Mode -#define AT91C_CAN_TIMFRZ ((unsigned int) 0x1 << 6) // (CAN) Enable Timer Freeze -#define AT91C_CAN_DRPT ((unsigned int) 0x1 << 7) // (CAN) Disable Repeat -// -------- CAN_IER : (CAN Offset: 0x4) CAN Interrupt Enable Register -------- -#define AT91C_CAN_MB0 ((unsigned int) 0x1 << 0) // (CAN) Mailbox 0 Flag -#define AT91C_CAN_MB1 ((unsigned int) 0x1 << 1) // (CAN) Mailbox 1 Flag -#define AT91C_CAN_MB2 ((unsigned int) 0x1 << 2) // (CAN) Mailbox 2 Flag -#define AT91C_CAN_MB3 ((unsigned int) 0x1 << 3) // (CAN) Mailbox 3 Flag -#define AT91C_CAN_MB4 ((unsigned int) 0x1 << 4) // (CAN) Mailbox 4 Flag -#define AT91C_CAN_MB5 ((unsigned int) 0x1 << 5) // (CAN) Mailbox 5 Flag -#define AT91C_CAN_MB6 ((unsigned int) 0x1 << 6) // (CAN) Mailbox 6 Flag -#define AT91C_CAN_MB7 ((unsigned int) 0x1 << 7) // (CAN) Mailbox 7 Flag -#define AT91C_CAN_MB8 ((unsigned int) 0x1 << 8) // (CAN) Mailbox 8 Flag -#define AT91C_CAN_MB9 ((unsigned int) 0x1 << 9) // (CAN) Mailbox 9 Flag -#define AT91C_CAN_MB10 ((unsigned int) 0x1 << 10) // (CAN) Mailbox 10 Flag -#define AT91C_CAN_MB11 ((unsigned int) 0x1 << 11) // (CAN) Mailbox 11 Flag -#define AT91C_CAN_MB12 ((unsigned int) 0x1 << 12) // (CAN) Mailbox 12 Flag -#define AT91C_CAN_MB13 ((unsigned int) 0x1 << 13) // (CAN) Mailbox 13 Flag -#define AT91C_CAN_MB14 ((unsigned int) 0x1 << 14) // (CAN) Mailbox 14 Flag -#define AT91C_CAN_MB15 ((unsigned int) 0x1 << 15) // (CAN) Mailbox 15 Flag -#define AT91C_CAN_ERRA ((unsigned int) 0x1 << 16) // (CAN) Error Active Mode Flag -#define AT91C_CAN_WARN ((unsigned int) 0x1 << 17) // (CAN) Warning Limit Flag -#define AT91C_CAN_ERRP ((unsigned int) 0x1 << 18) // (CAN) Error Passive Mode Flag -#define AT91C_CAN_BOFF ((unsigned int) 0x1 << 19) // (CAN) Bus Off Mode Flag -#define AT91C_CAN_SLEEP ((unsigned int) 0x1 << 20) // (CAN) Sleep Flag -#define AT91C_CAN_WAKEUP ((unsigned int) 0x1 << 21) // (CAN) Wakeup Flag -#define AT91C_CAN_TOVF ((unsigned int) 0x1 << 22) // (CAN) Timer Overflow Flag -#define AT91C_CAN_TSTP ((unsigned int) 0x1 << 23) // (CAN) Timestamp Flag -#define AT91C_CAN_CERR ((unsigned int) 0x1 << 24) // (CAN) CRC Error -#define AT91C_CAN_SERR ((unsigned int) 0x1 << 25) // (CAN) Stuffing Error -#define AT91C_CAN_AERR ((unsigned int) 0x1 << 26) // (CAN) Acknowledgment Error -#define AT91C_CAN_FERR ((unsigned int) 0x1 << 27) // (CAN) Form Error -#define AT91C_CAN_BERR ((unsigned int) 0x1 << 28) // (CAN) Bit Error -// -------- CAN_IDR : (CAN Offset: 0x8) CAN Interrupt Disable Register -------- -// -------- CAN_IMR : (CAN Offset: 0xc) CAN Interrupt Mask Register -------- -// -------- CAN_SR : (CAN Offset: 0x10) CAN Status Register -------- -#define AT91C_CAN_RBSY ((unsigned int) 0x1 << 29) // (CAN) Receiver Busy -#define AT91C_CAN_TBSY ((unsigned int) 0x1 << 30) // (CAN) Transmitter Busy -#define AT91C_CAN_OVLY ((unsigned int) 0x1 << 31) // (CAN) Overload Busy -// -------- CAN_BR : (CAN Offset: 0x14) CAN Baudrate Register -------- -#define AT91C_CAN_PHASE2 ((unsigned int) 0x7 << 0) // (CAN) Phase 2 segment -#define AT91C_CAN_PHASE1 ((unsigned int) 0x7 << 4) // (CAN) Phase 1 segment -#define AT91C_CAN_PROPAG ((unsigned int) 0x7 << 8) // (CAN) Programmation time segment -#define AT91C_CAN_SYNC ((unsigned int) 0x3 << 12) // (CAN) Re-synchronization jump width segment -#define AT91C_CAN_BRP ((unsigned int) 0x7F << 16) // (CAN) Baudrate Prescaler -#define AT91C_CAN_SMP ((unsigned int) 0x1 << 24) // (CAN) Sampling mode -// -------- CAN_TIM : (CAN Offset: 0x18) CAN Timer Register -------- -#define AT91C_CAN_TIMER ((unsigned int) 0xFFFF << 0) // (CAN) Timer field -// -------- CAN_TIMESTP : (CAN Offset: 0x1c) CAN Timestamp Register -------- -// -------- CAN_ECR : (CAN Offset: 0x20) CAN Error Counter Register -------- -#define AT91C_CAN_REC ((unsigned int) 0xFF << 0) // (CAN) Receive Error Counter -#define AT91C_CAN_TEC ((unsigned int) 0xFF << 16) // (CAN) Transmit Error Counter -// -------- CAN_TCR : (CAN Offset: 0x24) CAN Transfer Command Register -------- -#define AT91C_CAN_TIMRST ((unsigned int) 0x1 << 31) // (CAN) Timer Reset Field -// -------- CAN_ACR : (CAN Offset: 0x28) CAN Abort Command Register -------- +/* -------- CAN_MR : (CAN Offset: 0x0) CAN Mode Register -------- */ +#define AT91C_CAN_CANEN ( ( unsigned int ) 0x1 << 0 ) /* (CAN) CAN Controller Enable */ +#define AT91C_CAN_LPM ( ( unsigned int ) 0x1 << 1 ) /* (CAN) Disable/Enable Low Power Mode */ +#define AT91C_CAN_ABM ( ( unsigned int ) 0x1 << 2 ) /* (CAN) Disable/Enable Autobaud/Listen Mode */ +#define AT91C_CAN_OVL ( ( unsigned int ) 0x1 << 3 ) /* (CAN) Disable/Enable Overload Frame */ +#define AT91C_CAN_TEOF ( ( unsigned int ) 0x1 << 4 ) /* (CAN) Time Stamp messages at each end of Frame */ +#define AT91C_CAN_TTM ( ( unsigned int ) 0x1 << 5 ) /* (CAN) Disable/Enable Time Trigger Mode */ +#define AT91C_CAN_TIMFRZ ( ( unsigned int ) 0x1 << 6 ) /* (CAN) Enable Timer Freeze */ +#define AT91C_CAN_DRPT ( ( unsigned int ) 0x1 << 7 ) /* (CAN) Disable Repeat */ +/* -------- CAN_IER : (CAN Offset: 0x4) CAN Interrupt Enable Register -------- */ +#define AT91C_CAN_MB0 ( ( unsigned int ) 0x1 << 0 ) /* (CAN) Mailbox 0 Flag */ +#define AT91C_CAN_MB1 ( ( unsigned int ) 0x1 << 1 ) /* (CAN) Mailbox 1 Flag */ +#define AT91C_CAN_MB2 ( ( unsigned int ) 0x1 << 2 ) /* (CAN) Mailbox 2 Flag */ +#define AT91C_CAN_MB3 ( ( unsigned int ) 0x1 << 3 ) /* (CAN) Mailbox 3 Flag */ +#define AT91C_CAN_MB4 ( ( unsigned int ) 0x1 << 4 ) /* (CAN) Mailbox 4 Flag */ +#define AT91C_CAN_MB5 ( ( unsigned int ) 0x1 << 5 ) /* (CAN) Mailbox 5 Flag */ +#define AT91C_CAN_MB6 ( ( unsigned int ) 0x1 << 6 ) /* (CAN) Mailbox 6 Flag */ +#define AT91C_CAN_MB7 ( ( unsigned int ) 0x1 << 7 ) /* (CAN) Mailbox 7 Flag */ +#define AT91C_CAN_MB8 ( ( unsigned int ) 0x1 << 8 ) /* (CAN) Mailbox 8 Flag */ +#define AT91C_CAN_MB9 ( ( unsigned int ) 0x1 << 9 ) /* (CAN) Mailbox 9 Flag */ +#define AT91C_CAN_MB10 ( ( unsigned int ) 0x1 << 10 ) /* (CAN) Mailbox 10 Flag */ +#define AT91C_CAN_MB11 ( ( unsigned int ) 0x1 << 11 ) /* (CAN) Mailbox 11 Flag */ +#define AT91C_CAN_MB12 ( ( unsigned int ) 0x1 << 12 ) /* (CAN) Mailbox 12 Flag */ +#define AT91C_CAN_MB13 ( ( unsigned int ) 0x1 << 13 ) /* (CAN) Mailbox 13 Flag */ +#define AT91C_CAN_MB14 ( ( unsigned int ) 0x1 << 14 ) /* (CAN) Mailbox 14 Flag */ +#define AT91C_CAN_MB15 ( ( unsigned int ) 0x1 << 15 ) /* (CAN) Mailbox 15 Flag */ +#define AT91C_CAN_ERRA ( ( unsigned int ) 0x1 << 16 ) /* (CAN) Error Active Mode Flag */ +#define AT91C_CAN_WARN ( ( unsigned int ) 0x1 << 17 ) /* (CAN) Warning Limit Flag */ +#define AT91C_CAN_ERRP ( ( unsigned int ) 0x1 << 18 ) /* (CAN) Error Passive Mode Flag */ +#define AT91C_CAN_BOFF ( ( unsigned int ) 0x1 << 19 ) /* (CAN) Bus Off Mode Flag */ +#define AT91C_CAN_SLEEP ( ( unsigned int ) 0x1 << 20 ) /* (CAN) Sleep Flag */ +#define AT91C_CAN_WAKEUP ( ( unsigned int ) 0x1 << 21 ) /* (CAN) Wakeup Flag */ +#define AT91C_CAN_TOVF ( ( unsigned int ) 0x1 << 22 ) /* (CAN) Timer Overflow Flag */ +#define AT91C_CAN_TSTP ( ( unsigned int ) 0x1 << 23 ) /* (CAN) Timestamp Flag */ +#define AT91C_CAN_CERR ( ( unsigned int ) 0x1 << 24 ) /* (CAN) CRC Error */ +#define AT91C_CAN_SERR ( ( unsigned int ) 0x1 << 25 ) /* (CAN) Stuffing Error */ +#define AT91C_CAN_AERR ( ( unsigned int ) 0x1 << 26 ) /* (CAN) Acknowledgment Error */ +#define AT91C_CAN_FERR ( ( unsigned int ) 0x1 << 27 ) /* (CAN) Form Error */ +#define AT91C_CAN_BERR ( ( unsigned int ) 0x1 << 28 ) /* (CAN) Bit Error */ +/* -------- CAN_IDR : (CAN Offset: 0x8) CAN Interrupt Disable Register -------- */ +/* -------- CAN_IMR : (CAN Offset: 0xc) CAN Interrupt Mask Register -------- */ +/* -------- CAN_SR : (CAN Offset: 0x10) CAN Status Register -------- */ +#define AT91C_CAN_RBSY ( ( unsigned int ) 0x1 << 29 ) /* (CAN) Receiver Busy */ +#define AT91C_CAN_TBSY ( ( unsigned int ) 0x1 << 30 ) /* (CAN) Transmitter Busy */ +#define AT91C_CAN_OVLY ( ( unsigned int ) 0x1 << 31 ) /* (CAN) Overload Busy */ +/* -------- CAN_BR : (CAN Offset: 0x14) CAN Baudrate Register -------- */ +#define AT91C_CAN_PHASE2 ( ( unsigned int ) 0x7 << 0 ) /* (CAN) Phase 2 segment */ +#define AT91C_CAN_PHASE1 ( ( unsigned int ) 0x7 << 4 ) /* (CAN) Phase 1 segment */ +#define AT91C_CAN_PROPAG ( ( unsigned int ) 0x7 << 8 ) /* (CAN) Programmation time segment */ +#define AT91C_CAN_SYNC ( ( unsigned int ) 0x3 << 12 ) /* (CAN) Re-synchronization jump width segment */ +#define AT91C_CAN_BRP ( ( unsigned int ) 0x7F << 16 ) /* (CAN) Baudrate Prescaler */ +#define AT91C_CAN_SMP ( ( unsigned int ) 0x1 << 24 ) /* (CAN) Sampling mode */ +/* -------- CAN_TIM : (CAN Offset: 0x18) CAN Timer Register -------- */ +#define AT91C_CAN_TIMER ( ( unsigned int ) 0xFFFF << 0 ) /* (CAN) Timer field */ +/* -------- CAN_TIMESTP : (CAN Offset: 0x1c) CAN Timestamp Register -------- */ +/* -------- CAN_ECR : (CAN Offset: 0x20) CAN Error Counter Register -------- */ +#define AT91C_CAN_REC ( ( unsigned int ) 0xFF << 0 ) /* (CAN) Receive Error Counter */ +#define AT91C_CAN_TEC ( ( unsigned int ) 0xFF << 16 ) /* (CAN) Transmit Error Counter */ +/* -------- CAN_TCR : (CAN Offset: 0x24) CAN Transfer Command Register -------- */ +#define AT91C_CAN_TIMRST ( ( unsigned int ) 0x1 << 31 ) /* (CAN) Timer Reset Field */ +/* -------- CAN_ACR : (CAN Offset: 0x28) CAN Abort Command Register -------- */ -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Ethernet MAC 10/100 -// ***************************************************************************** -typedef struct _AT91S_EMAC { - AT91_REG EMAC_NCR; // Network Control Register - AT91_REG EMAC_NCFGR; // Network Configuration Register - AT91_REG EMAC_NSR; // Network Status Register - AT91_REG Reserved0[2]; // - AT91_REG EMAC_TSR; // Transmit Status Register - AT91_REG EMAC_RBQP; // Receive Buffer Queue Pointer - AT91_REG EMAC_TBQP; // Transmit Buffer Queue Pointer - AT91_REG EMAC_RSR; // Receive Status Register - AT91_REG EMAC_ISR; // Interrupt Status Register - AT91_REG EMAC_IER; // Interrupt Enable Register - AT91_REG EMAC_IDR; // Interrupt Disable Register - AT91_REG EMAC_IMR; // Interrupt Mask Register - AT91_REG EMAC_MAN; // PHY Maintenance Register - AT91_REG EMAC_PTR; // Pause Time Register - AT91_REG EMAC_PFR; // Pause Frames received Register - AT91_REG EMAC_FTO; // Frames Transmitted OK Register - AT91_REG EMAC_SCF; // Single Collision Frame Register - AT91_REG EMAC_MCF; // Multiple Collision Frame Register - AT91_REG EMAC_FRO; // Frames Received OK Register - AT91_REG EMAC_FCSE; // Frame Check Sequence Error Register - AT91_REG EMAC_ALE; // Alignment Error Register - AT91_REG EMAC_DTF; // Deferred Transmission Frame Register - AT91_REG EMAC_LCOL; // Late Collision Register - AT91_REG EMAC_ECOL; // Excessive Collision Register - AT91_REG EMAC_TUND; // Transmit Underrun Error Register - AT91_REG EMAC_CSE; // Carrier Sense Error Register - AT91_REG EMAC_RRE; // Receive Ressource Error Register - AT91_REG EMAC_ROV; // Receive Overrun Errors Register - AT91_REG EMAC_RSE; // Receive Symbol Errors Register - AT91_REG EMAC_ELE; // Excessive Length Errors Register - AT91_REG EMAC_RJA; // Receive Jabbers Register - AT91_REG EMAC_USF; // Undersize Frames Register - AT91_REG EMAC_STE; // SQE Test Error Register - AT91_REG EMAC_RLE; // Receive Length Field Mismatch Register - AT91_REG EMAC_TPF; // Transmitted Pause Frames Register - AT91_REG EMAC_HRB; // Hash Address Bottom[31:0] - AT91_REG EMAC_HRT; // Hash Address Top[63:32] - AT91_REG EMAC_SA1L; // Specific Address 1 Bottom, First 4 bytes - AT91_REG EMAC_SA1H; // Specific Address 1 Top, Last 2 bytes - AT91_REG EMAC_SA2L; // Specific Address 2 Bottom, First 4 bytes - AT91_REG EMAC_SA2H; // Specific Address 2 Top, Last 2 bytes - AT91_REG EMAC_SA3L; // Specific Address 3 Bottom, First 4 bytes - AT91_REG EMAC_SA3H; // Specific Address 3 Top, Last 2 bytes - AT91_REG EMAC_SA4L; // Specific Address 4 Bottom, First 4 bytes - AT91_REG EMAC_SA4H; // Specific Address 4 Top, Last 2 bytes - AT91_REG EMAC_TID; // Type ID Checking Register - AT91_REG EMAC_TPQ; // Transmit Pause Quantum Register - AT91_REG EMAC_USRIO; // USER Input/Output Register - AT91_REG EMAC_WOL; // Wake On LAN Register - AT91_REG Reserved1[13]; // - AT91_REG EMAC_REV; // Revision Register -} AT91S_EMAC, *AT91PS_EMAC; +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR Ethernet MAC 10/100 */ +/* ***************************************************************************** */ +typedef struct _AT91S_EMAC +{ + AT91_REG EMAC_NCR; /* Network Control Register */ + AT91_REG EMAC_NCFGR; /* Network Configuration Register */ + AT91_REG EMAC_NSR; /* Network Status Register */ + AT91_REG Reserved0[ 2 ]; /* */ + AT91_REG EMAC_TSR; /* Transmit Status Register */ + AT91_REG EMAC_RBQP; /* Receive Buffer Queue Pointer */ + AT91_REG EMAC_TBQP; /* Transmit Buffer Queue Pointer */ + AT91_REG EMAC_RSR; /* Receive Status Register */ + AT91_REG EMAC_ISR; /* Interrupt Status Register */ + AT91_REG EMAC_IER; /* Interrupt Enable Register */ + AT91_REG EMAC_IDR; /* Interrupt Disable Register */ + AT91_REG EMAC_IMR; /* Interrupt Mask Register */ + AT91_REG EMAC_MAN; /* PHY Maintenance Register */ + AT91_REG EMAC_PTR; /* Pause Time Register */ + AT91_REG EMAC_PFR; /* Pause Frames received Register */ + AT91_REG EMAC_FTO; /* Frames Transmitted OK Register */ + AT91_REG EMAC_SCF; /* Single Collision Frame Register */ + AT91_REG EMAC_MCF; /* Multiple Collision Frame Register */ + AT91_REG EMAC_FRO; /* Frames Received OK Register */ + AT91_REG EMAC_FCSE; /* Frame Check Sequence Error Register */ + AT91_REG EMAC_ALE; /* Alignment Error Register */ + AT91_REG EMAC_DTF; /* Deferred Transmission Frame Register */ + AT91_REG EMAC_LCOL; /* Late Collision Register */ + AT91_REG EMAC_ECOL; /* Excessive Collision Register */ + AT91_REG EMAC_TUND; /* Transmit Underrun Error Register */ + AT91_REG EMAC_CSE; /* Carrier Sense Error Register */ + AT91_REG EMAC_RRE; /* Receive Ressource Error Register */ + AT91_REG EMAC_ROV; /* Receive Overrun Errors Register */ + AT91_REG EMAC_RSE; /* Receive Symbol Errors Register */ + AT91_REG EMAC_ELE; /* Excessive Length Errors Register */ + AT91_REG EMAC_RJA; /* Receive Jabbers Register */ + AT91_REG EMAC_USF; /* Undersize Frames Register */ + AT91_REG EMAC_STE; /* SQE Test Error Register */ + AT91_REG EMAC_RLE; /* Receive Length Field Mismatch Register */ + AT91_REG EMAC_TPF; /* Transmitted Pause Frames Register */ + AT91_REG EMAC_HRB; /* Hash Address Bottom[31:0] */ + AT91_REG EMAC_HRT; /* Hash Address Top[63:32] */ + AT91_REG EMAC_SA1L; /* Specific Address 1 Bottom, First 4 bytes */ + AT91_REG EMAC_SA1H; /* Specific Address 1 Top, Last 2 bytes */ + AT91_REG EMAC_SA2L; /* Specific Address 2 Bottom, First 4 bytes */ + AT91_REG EMAC_SA2H; /* Specific Address 2 Top, Last 2 bytes */ + AT91_REG EMAC_SA3L; /* Specific Address 3 Bottom, First 4 bytes */ + AT91_REG EMAC_SA3H; /* Specific Address 3 Top, Last 2 bytes */ + AT91_REG EMAC_SA4L; /* Specific Address 4 Bottom, First 4 bytes */ + AT91_REG EMAC_SA4H; /* Specific Address 4 Top, Last 2 bytes */ + AT91_REG EMAC_TID; /* Type ID Checking Register */ + AT91_REG EMAC_TPQ; /* Transmit Pause Quantum Register */ + AT91_REG EMAC_USRIO; /* USER Input/Output Register */ + AT91_REG EMAC_WOL; /* Wake On LAN Register */ + AT91_REG Reserved1[ 13 ]; /* */ + AT91_REG EMAC_REV; /* Revision Register */ +} AT91S_EMAC, * AT91PS_EMAC; -// -------- EMAC_NCR : (EMAC Offset: 0x0) -------- -#define AT91C_EMAC_LB ((unsigned int) 0x1 << 0) // (EMAC) Loopback. Optional. When set, loopback signal is at high level. -#define AT91C_EMAC_LLB ((unsigned int) 0x1 << 1) // (EMAC) Loopback local. -#define AT91C_EMAC_RE ((unsigned int) 0x1 << 2) // (EMAC) Receive enable. -#define AT91C_EMAC_TE ((unsigned int) 0x1 << 3) // (EMAC) Transmit enable. -#define AT91C_EMAC_MPE ((unsigned int) 0x1 << 4) // (EMAC) Management port enable. -#define AT91C_EMAC_CLRSTAT ((unsigned int) 0x1 << 5) // (EMAC) Clear statistics registers. -#define AT91C_EMAC_INCSTAT ((unsigned int) 0x1 << 6) // (EMAC) Increment statistics registers. -#define AT91C_EMAC_WESTAT ((unsigned int) 0x1 << 7) // (EMAC) Write enable for statistics registers. -#define AT91C_EMAC_BP ((unsigned int) 0x1 << 8) // (EMAC) Back pressure. -#define AT91C_EMAC_TSTART ((unsigned int) 0x1 << 9) // (EMAC) Start Transmission. -#define AT91C_EMAC_THALT ((unsigned int) 0x1 << 10) // (EMAC) Transmission Halt. -#define AT91C_EMAC_TPFR ((unsigned int) 0x1 << 11) // (EMAC) Transmit pause frame -#define AT91C_EMAC_TZQ ((unsigned int) 0x1 << 12) // (EMAC) Transmit zero quantum pause frame -// -------- EMAC_NCFGR : (EMAC Offset: 0x4) Network Configuration Register -------- -#define AT91C_EMAC_SPD ((unsigned int) 0x1 << 0) // (EMAC) Speed. -#define AT91C_EMAC_FD ((unsigned int) 0x1 << 1) // (EMAC) Full duplex. -#define AT91C_EMAC_JFRAME ((unsigned int) 0x1 << 3) // (EMAC) Jumbo Frames. -#define AT91C_EMAC_CAF ((unsigned int) 0x1 << 4) // (EMAC) Copy all frames. -#define AT91C_EMAC_NBC ((unsigned int) 0x1 << 5) // (EMAC) No broadcast. -#define AT91C_EMAC_MTI ((unsigned int) 0x1 << 6) // (EMAC) Multicast hash event enable -#define AT91C_EMAC_UNI ((unsigned int) 0x1 << 7) // (EMAC) Unicast hash enable. -#define AT91C_EMAC_BIG ((unsigned int) 0x1 << 8) // (EMAC) Receive 1522 bytes. -#define AT91C_EMAC_EAE ((unsigned int) 0x1 << 9) // (EMAC) External address match enable. -#define AT91C_EMAC_CLK ((unsigned int) 0x3 << 10) // (EMAC) -#define AT91C_EMAC_CLK_HCLK_8 ((unsigned int) 0x0 << 10) // (EMAC) HCLK divided by 8 -#define AT91C_EMAC_CLK_HCLK_16 ((unsigned int) 0x1 << 10) // (EMAC) HCLK divided by 16 -#define AT91C_EMAC_CLK_HCLK_32 ((unsigned int) 0x2 << 10) // (EMAC) HCLK divided by 32 -#define AT91C_EMAC_CLK_HCLK_64 ((unsigned int) 0x3 << 10) // (EMAC) HCLK divided by 64 -#define AT91C_EMAC_RTY ((unsigned int) 0x1 << 12) // (EMAC) -#define AT91C_EMAC_PAE ((unsigned int) 0x1 << 13) // (EMAC) -#define AT91C_EMAC_RBOF ((unsigned int) 0x3 << 14) // (EMAC) -#define AT91C_EMAC_RBOF_OFFSET_0 ((unsigned int) 0x0 << 14) // (EMAC) no offset from start of receive buffer -#define AT91C_EMAC_RBOF_OFFSET_1 ((unsigned int) 0x1 << 14) // (EMAC) one byte offset from start of receive buffer -#define AT91C_EMAC_RBOF_OFFSET_2 ((unsigned int) 0x2 << 14) // (EMAC) two bytes offset from start of receive buffer -#define AT91C_EMAC_RBOF_OFFSET_3 ((unsigned int) 0x3 << 14) // (EMAC) three bytes offset from start of receive buffer -#define AT91C_EMAC_RLCE ((unsigned int) 0x1 << 16) // (EMAC) Receive Length field Checking Enable -#define AT91C_EMAC_DRFCS ((unsigned int) 0x1 << 17) // (EMAC) Discard Receive FCS -#define AT91C_EMAC_EFRHD ((unsigned int) 0x1 << 18) // (EMAC) -#define AT91C_EMAC_IRXFCS ((unsigned int) 0x1 << 19) // (EMAC) Ignore RX FCS -// -------- EMAC_NSR : (EMAC Offset: 0x8) Network Status Register -------- -#define AT91C_EMAC_LINKR ((unsigned int) 0x1 << 0) // (EMAC) -#define AT91C_EMAC_MDIO ((unsigned int) 0x1 << 1) // (EMAC) -#define AT91C_EMAC_IDLE ((unsigned int) 0x1 << 2) // (EMAC) -// -------- EMAC_TSR : (EMAC Offset: 0x14) Transmit Status Register -------- -#define AT91C_EMAC_UBR ((unsigned int) 0x1 << 0) // (EMAC) -#define AT91C_EMAC_COL ((unsigned int) 0x1 << 1) // (EMAC) -#define AT91C_EMAC_RLES ((unsigned int) 0x1 << 2) // (EMAC) -#define AT91C_EMAC_TGO ((unsigned int) 0x1 << 3) // (EMAC) Transmit Go -#define AT91C_EMAC_BEX ((unsigned int) 0x1 << 4) // (EMAC) Buffers exhausted mid frame -#define AT91C_EMAC_COMP ((unsigned int) 0x1 << 5) // (EMAC) -#define AT91C_EMAC_UND ((unsigned int) 0x1 << 6) // (EMAC) -// -------- EMAC_RSR : (EMAC Offset: 0x20) Receive Status Register -------- -#define AT91C_EMAC_BNA ((unsigned int) 0x1 << 0) // (EMAC) -#define AT91C_EMAC_REC ((unsigned int) 0x1 << 1) // (EMAC) -#define AT91C_EMAC_OVR ((unsigned int) 0x1 << 2) // (EMAC) -// -------- EMAC_ISR : (EMAC Offset: 0x24) Interrupt Status Register -------- -#define AT91C_EMAC_MFD ((unsigned int) 0x1 << 0) // (EMAC) -#define AT91C_EMAC_RCOMP ((unsigned int) 0x1 << 1) // (EMAC) -#define AT91C_EMAC_RXUBR ((unsigned int) 0x1 << 2) // (EMAC) -#define AT91C_EMAC_TXUBR ((unsigned int) 0x1 << 3) // (EMAC) -#define AT91C_EMAC_TUNDR ((unsigned int) 0x1 << 4) // (EMAC) -#define AT91C_EMAC_RLEX ((unsigned int) 0x1 << 5) // (EMAC) -#define AT91C_EMAC_TXERR ((unsigned int) 0x1 << 6) // (EMAC) -#define AT91C_EMAC_TCOMP ((unsigned int) 0x1 << 7) // (EMAC) -#define AT91C_EMAC_LINK ((unsigned int) 0x1 << 9) // (EMAC) -#define AT91C_EMAC_ROVR ((unsigned int) 0x1 << 10) // (EMAC) -#define AT91C_EMAC_HRESP ((unsigned int) 0x1 << 11) // (EMAC) -#define AT91C_EMAC_PFRE ((unsigned int) 0x1 << 12) // (EMAC) -#define AT91C_EMAC_PTZ ((unsigned int) 0x1 << 13) // (EMAC) -// -------- EMAC_IER : (EMAC Offset: 0x28) Interrupt Enable Register -------- -// -------- EMAC_IDR : (EMAC Offset: 0x2c) Interrupt Disable Register -------- -// -------- EMAC_IMR : (EMAC Offset: 0x30) Interrupt Mask Register -------- -// -------- EMAC_MAN : (EMAC Offset: 0x34) PHY Maintenance Register -------- -#define AT91C_EMAC_DATA ((unsigned int) 0xFFFF << 0) // (EMAC) -#define AT91C_EMAC_CODE ((unsigned int) 0x3 << 16) // (EMAC) -#define AT91C_EMAC_REGA ((unsigned int) 0x1F << 18) // (EMAC) -#define AT91C_EMAC_PHYA ((unsigned int) 0x1F << 23) // (EMAC) -#define AT91C_EMAC_RW ((unsigned int) 0x3 << 28) // (EMAC) -#define AT91C_EMAC_SOF ((unsigned int) 0x3 << 30) // (EMAC) -// -------- EMAC_USRIO : (EMAC Offset: 0xc0) USER Input Output Register -------- -#define AT91C_EMAC_RMII ((unsigned int) 0x1 << 0) // (EMAC) Reduce MII -// -------- EMAC_WOL : (EMAC Offset: 0xc4) Wake On LAN Register -------- -#define AT91C_EMAC_IP ((unsigned int) 0xFFFF << 0) // (EMAC) ARP request IP address -#define AT91C_EMAC_MAG ((unsigned int) 0x1 << 16) // (EMAC) Magic packet event enable -#define AT91C_EMAC_ARP ((unsigned int) 0x1 << 17) // (EMAC) ARP request event enable -#define AT91C_EMAC_SA1 ((unsigned int) 0x1 << 18) // (EMAC) Specific address register 1 event enable -// -------- EMAC_REV : (EMAC Offset: 0xfc) Revision Register -------- -#define AT91C_EMAC_REVREF ((unsigned int) 0xFFFF << 0) // (EMAC) -#define AT91C_EMAC_PARTREF ((unsigned int) 0xFFFF << 16) // (EMAC) +/* -------- EMAC_NCR : (EMAC Offset: 0x0) -------- */ +#define AT91C_EMAC_LB ( ( unsigned int ) 0x1 << 0 ) /* (EMAC) Loopback. Optional. When set, loopback signal is at high level. */ +#define AT91C_EMAC_LLB ( ( unsigned int ) 0x1 << 1 ) /* (EMAC) Loopback local. */ +#define AT91C_EMAC_RE ( ( unsigned int ) 0x1 << 2 ) /* (EMAC) Receive enable. */ +#define AT91C_EMAC_TE ( ( unsigned int ) 0x1 << 3 ) /* (EMAC) Transmit enable. */ +#define AT91C_EMAC_MPE ( ( unsigned int ) 0x1 << 4 ) /* (EMAC) Management port enable. */ +#define AT91C_EMAC_CLRSTAT ( ( unsigned int ) 0x1 << 5 ) /* (EMAC) Clear statistics registers. */ +#define AT91C_EMAC_INCSTAT ( ( unsigned int ) 0x1 << 6 ) /* (EMAC) Increment statistics registers. */ +#define AT91C_EMAC_WESTAT ( ( unsigned int ) 0x1 << 7 ) /* (EMAC) Write enable for statistics registers. */ +#define AT91C_EMAC_BP ( ( unsigned int ) 0x1 << 8 ) /* (EMAC) Back pressure. */ +#define AT91C_EMAC_TSTART ( ( unsigned int ) 0x1 << 9 ) /* (EMAC) Start Transmission. */ +#define AT91C_EMAC_THALT ( ( unsigned int ) 0x1 << 10 ) /* (EMAC) Transmission Halt. */ +#define AT91C_EMAC_TPFR ( ( unsigned int ) 0x1 << 11 ) /* (EMAC) Transmit pause frame */ +#define AT91C_EMAC_TZQ ( ( unsigned int ) 0x1 << 12 ) /* (EMAC) Transmit zero quantum pause frame */ +/* -------- EMAC_NCFGR : (EMAC Offset: 0x4) Network Configuration Register -------- */ +#define AT91C_EMAC_SPD ( ( unsigned int ) 0x1 << 0 ) /* (EMAC) Speed. */ +#define AT91C_EMAC_FD ( ( unsigned int ) 0x1 << 1 ) /* (EMAC) Full duplex. */ +#define AT91C_EMAC_JFRAME ( ( unsigned int ) 0x1 << 3 ) /* (EMAC) Jumbo Frames. */ +#define AT91C_EMAC_CAF ( ( unsigned int ) 0x1 << 4 ) /* (EMAC) Copy all frames. */ +#define AT91C_EMAC_NBC ( ( unsigned int ) 0x1 << 5 ) /* (EMAC) No broadcast. */ +#define AT91C_EMAC_MTI ( ( unsigned int ) 0x1 << 6 ) /* (EMAC) Multicast hash event enable */ +#define AT91C_EMAC_UNI ( ( unsigned int ) 0x1 << 7 ) /* (EMAC) Unicast hash enable. */ +#define AT91C_EMAC_BIG ( ( unsigned int ) 0x1 << 8 ) /* (EMAC) Receive 1522 bytes. */ +#define AT91C_EMAC_EAE ( ( unsigned int ) 0x1 << 9 ) /* (EMAC) External address match enable. */ +#define AT91C_EMAC_CLK ( ( unsigned int ) 0x3 << 10 ) /* (EMAC) */ +#define AT91C_EMAC_CLK_HCLK_8 ( ( unsigned int ) 0x0 << 10 ) /* (EMAC) HCLK divided by 8 */ +#define AT91C_EMAC_CLK_HCLK_16 ( ( unsigned int ) 0x1 << 10 ) /* (EMAC) HCLK divided by 16 */ +#define AT91C_EMAC_CLK_HCLK_32 ( ( unsigned int ) 0x2 << 10 ) /* (EMAC) HCLK divided by 32 */ +#define AT91C_EMAC_CLK_HCLK_64 ( ( unsigned int ) 0x3 << 10 ) /* (EMAC) HCLK divided by 64 */ +#define AT91C_EMAC_RTY ( ( unsigned int ) 0x1 << 12 ) /* (EMAC) */ +#define AT91C_EMAC_PAE ( ( unsigned int ) 0x1 << 13 ) /* (EMAC) */ +#define AT91C_EMAC_RBOF ( ( unsigned int ) 0x3 << 14 ) /* (EMAC) */ +#define AT91C_EMAC_RBOF_OFFSET_0 ( ( unsigned int ) 0x0 << 14 ) /* (EMAC) no offset from start of receive buffer */ +#define AT91C_EMAC_RBOF_OFFSET_1 ( ( unsigned int ) 0x1 << 14 ) /* (EMAC) one byte offset from start of receive buffer */ +#define AT91C_EMAC_RBOF_OFFSET_2 ( ( unsigned int ) 0x2 << 14 ) /* (EMAC) two bytes offset from start of receive buffer */ +#define AT91C_EMAC_RBOF_OFFSET_3 ( ( unsigned int ) 0x3 << 14 ) /* (EMAC) three bytes offset from start of receive buffer */ +#define AT91C_EMAC_RLCE ( ( unsigned int ) 0x1 << 16 ) /* (EMAC) Receive Length field Checking Enable */ +#define AT91C_EMAC_DRFCS ( ( unsigned int ) 0x1 << 17 ) /* (EMAC) Discard Receive FCS */ +#define AT91C_EMAC_EFRHD ( ( unsigned int ) 0x1 << 18 ) /* (EMAC) */ +#define AT91C_EMAC_IRXFCS ( ( unsigned int ) 0x1 << 19 ) /* (EMAC) Ignore RX FCS */ +/* -------- EMAC_NSR : (EMAC Offset: 0x8) Network Status Register -------- */ +#define AT91C_EMAC_LINKR ( ( unsigned int ) 0x1 << 0 ) /* (EMAC) */ +#define AT91C_EMAC_MDIO ( ( unsigned int ) 0x1 << 1 ) /* (EMAC) */ +#define AT91C_EMAC_IDLE ( ( unsigned int ) 0x1 << 2 ) /* (EMAC) */ +/* -------- EMAC_TSR : (EMAC Offset: 0x14) Transmit Status Register -------- */ +#define AT91C_EMAC_UBR ( ( unsigned int ) 0x1 << 0 ) /* (EMAC) */ +#define AT91C_EMAC_COL ( ( unsigned int ) 0x1 << 1 ) /* (EMAC) */ +#define AT91C_EMAC_RLES ( ( unsigned int ) 0x1 << 2 ) /* (EMAC) */ +#define AT91C_EMAC_TGO ( ( unsigned int ) 0x1 << 3 ) /* (EMAC) Transmit Go */ +#define AT91C_EMAC_BEX ( ( unsigned int ) 0x1 << 4 ) /* (EMAC) Buffers exhausted mid frame */ +#define AT91C_EMAC_COMP ( ( unsigned int ) 0x1 << 5 ) /* (EMAC) */ +#define AT91C_EMAC_UND ( ( unsigned int ) 0x1 << 6 ) /* (EMAC) */ +/* -------- EMAC_RSR : (EMAC Offset: 0x20) Receive Status Register -------- */ +#define AT91C_EMAC_BNA ( ( unsigned int ) 0x1 << 0 ) /* (EMAC) */ +#define AT91C_EMAC_REC ( ( unsigned int ) 0x1 << 1 ) /* (EMAC) */ +#define AT91C_EMAC_OVR ( ( unsigned int ) 0x1 << 2 ) /* (EMAC) */ +/* -------- EMAC_ISR : (EMAC Offset: 0x24) Interrupt Status Register -------- */ +#define AT91C_EMAC_MFD ( ( unsigned int ) 0x1 << 0 ) /* (EMAC) */ +#define AT91C_EMAC_RCOMP ( ( unsigned int ) 0x1 << 1 ) /* (EMAC) */ +#define AT91C_EMAC_RXUBR ( ( unsigned int ) 0x1 << 2 ) /* (EMAC) */ +#define AT91C_EMAC_TXUBR ( ( unsigned int ) 0x1 << 3 ) /* (EMAC) */ +#define AT91C_EMAC_TUNDR ( ( unsigned int ) 0x1 << 4 ) /* (EMAC) */ +#define AT91C_EMAC_RLEX ( ( unsigned int ) 0x1 << 5 ) /* (EMAC) */ +#define AT91C_EMAC_TXERR ( ( unsigned int ) 0x1 << 6 ) /* (EMAC) */ +#define AT91C_EMAC_TCOMP ( ( unsigned int ) 0x1 << 7 ) /* (EMAC) */ +#define AT91C_EMAC_LINK ( ( unsigned int ) 0x1 << 9 ) /* (EMAC) */ +#define AT91C_EMAC_ROVR ( ( unsigned int ) 0x1 << 10 ) /* (EMAC) */ +#define AT91C_EMAC_HRESP ( ( unsigned int ) 0x1 << 11 ) /* (EMAC) */ +#define AT91C_EMAC_PFRE ( ( unsigned int ) 0x1 << 12 ) /* (EMAC) */ +#define AT91C_EMAC_PTZ ( ( unsigned int ) 0x1 << 13 ) /* (EMAC) */ +/* -------- EMAC_IER : (EMAC Offset: 0x28) Interrupt Enable Register -------- */ +/* -------- EMAC_IDR : (EMAC Offset: 0x2c) Interrupt Disable Register -------- */ +/* -------- EMAC_IMR : (EMAC Offset: 0x30) Interrupt Mask Register -------- */ +/* -------- EMAC_MAN : (EMAC Offset: 0x34) PHY Maintenance Register -------- */ +#define AT91C_EMAC_DATA ( ( unsigned int ) 0xFFFF << 0 ) /* (EMAC) */ +#define AT91C_EMAC_CODE ( ( unsigned int ) 0x3 << 16 ) /* (EMAC) */ +#define AT91C_EMAC_REGA ( ( unsigned int ) 0x1F << 18 ) /* (EMAC) */ +#define AT91C_EMAC_PHYA ( ( unsigned int ) 0x1F << 23 ) /* (EMAC) */ +#define AT91C_EMAC_RW ( ( unsigned int ) 0x3 << 28 ) /* (EMAC) */ +#define AT91C_EMAC_SOF ( ( unsigned int ) 0x3 << 30 ) /* (EMAC) */ +/* -------- EMAC_USRIO : (EMAC Offset: 0xc0) USER Input Output Register -------- */ +#define AT91C_EMAC_RMII ( ( unsigned int ) 0x1 << 0 ) /* (EMAC) Reduce MII */ +/* -------- EMAC_WOL : (EMAC Offset: 0xc4) Wake On LAN Register -------- */ +#define AT91C_EMAC_IP ( ( unsigned int ) 0xFFFF << 0 ) /* (EMAC) ARP request IP address */ +#define AT91C_EMAC_MAG ( ( unsigned int ) 0x1 << 16 ) /* (EMAC) Magic packet event enable */ +#define AT91C_EMAC_ARP ( ( unsigned int ) 0x1 << 17 ) /* (EMAC) ARP request event enable */ +#define AT91C_EMAC_SA1 ( ( unsigned int ) 0x1 << 18 ) /* (EMAC) Specific address register 1 event enable */ +/* -------- EMAC_REV : (EMAC Offset: 0xfc) Revision Register -------- */ +#define AT91C_EMAC_REVREF ( ( unsigned int ) 0xFFFF << 0 ) /* (EMAC) */ +#define AT91C_EMAC_PARTREF ( ( unsigned int ) 0xFFFF << 16 ) /* (EMAC) */ -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Analog to Digital Convertor -// ***************************************************************************** -typedef struct _AT91S_ADC { - AT91_REG ADC_CR; // ADC Control Register - AT91_REG ADC_MR; // ADC Mode Register - AT91_REG Reserved0[2]; // - AT91_REG ADC_CHER; // ADC Channel Enable Register - AT91_REG ADC_CHDR; // ADC Channel Disable Register - AT91_REG ADC_CHSR; // ADC Channel Status Register - AT91_REG ADC_SR; // ADC Status Register - AT91_REG ADC_LCDR; // ADC Last Converted Data Register - AT91_REG ADC_IER; // ADC Interrupt Enable Register - AT91_REG ADC_IDR; // ADC Interrupt Disable Register - AT91_REG ADC_IMR; // ADC Interrupt Mask Register - AT91_REG ADC_CDR0; // ADC Channel Data Register 0 - AT91_REG ADC_CDR1; // ADC Channel Data Register 1 - AT91_REG ADC_CDR2; // ADC Channel Data Register 2 - AT91_REG ADC_CDR3; // ADC Channel Data Register 3 - AT91_REG ADC_CDR4; // ADC Channel Data Register 4 - AT91_REG ADC_CDR5; // ADC Channel Data Register 5 - AT91_REG ADC_CDR6; // ADC Channel Data Register 6 - AT91_REG ADC_CDR7; // ADC Channel Data Register 7 - AT91_REG Reserved1[44]; // - AT91_REG ADC_RPR; // Receive Pointer Register - AT91_REG ADC_RCR; // Receive Counter Register - AT91_REG ADC_TPR; // Transmit Pointer Register - AT91_REG ADC_TCR; // Transmit Counter Register - AT91_REG ADC_RNPR; // Receive Next Pointer Register - AT91_REG ADC_RNCR; // Receive Next Counter Register - AT91_REG ADC_TNPR; // Transmit Next Pointer Register - AT91_REG ADC_TNCR; // Transmit Next Counter Register - AT91_REG ADC_PTCR; // PDC Transfer Control Register - AT91_REG ADC_PTSR; // PDC Transfer Status Register -} AT91S_ADC, *AT91PS_ADC; +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR Analog to Digital Convertor */ +/* ***************************************************************************** */ +typedef struct _AT91S_ADC +{ + AT91_REG ADC_CR; /* ADC Control Register */ + AT91_REG ADC_MR; /* ADC Mode Register */ + AT91_REG Reserved0[ 2 ]; /* */ + AT91_REG ADC_CHER; /* ADC Channel Enable Register */ + AT91_REG ADC_CHDR; /* ADC Channel Disable Register */ + AT91_REG ADC_CHSR; /* ADC Channel Status Register */ + AT91_REG ADC_SR; /* ADC Status Register */ + AT91_REG ADC_LCDR; /* ADC Last Converted Data Register */ + AT91_REG ADC_IER; /* ADC Interrupt Enable Register */ + AT91_REG ADC_IDR; /* ADC Interrupt Disable Register */ + AT91_REG ADC_IMR; /* ADC Interrupt Mask Register */ + AT91_REG ADC_CDR0; /* ADC Channel Data Register 0 */ + AT91_REG ADC_CDR1; /* ADC Channel Data Register 1 */ + AT91_REG ADC_CDR2; /* ADC Channel Data Register 2 */ + AT91_REG ADC_CDR3; /* ADC Channel Data Register 3 */ + AT91_REG ADC_CDR4; /* ADC Channel Data Register 4 */ + AT91_REG ADC_CDR5; /* ADC Channel Data Register 5 */ + AT91_REG ADC_CDR6; /* ADC Channel Data Register 6 */ + AT91_REG ADC_CDR7; /* ADC Channel Data Register 7 */ + AT91_REG Reserved1[ 44 ]; /* */ + AT91_REG ADC_RPR; /* Receive Pointer Register */ + AT91_REG ADC_RCR; /* Receive Counter Register */ + AT91_REG ADC_TPR; /* Transmit Pointer Register */ + AT91_REG ADC_TCR; /* Transmit Counter Register */ + AT91_REG ADC_RNPR; /* Receive Next Pointer Register */ + AT91_REG ADC_RNCR; /* Receive Next Counter Register */ + AT91_REG ADC_TNPR; /* Transmit Next Pointer Register */ + AT91_REG ADC_TNCR; /* Transmit Next Counter Register */ + AT91_REG ADC_PTCR; /* PDC Transfer Control Register */ + AT91_REG ADC_PTSR; /* PDC Transfer Status Register */ +} AT91S_ADC, * AT91PS_ADC; -// -------- ADC_CR : (ADC Offset: 0x0) ADC Control Register -------- -#define AT91C_ADC_SWRST ((unsigned int) 0x1 << 0) // (ADC) Software Reset -#define AT91C_ADC_START ((unsigned int) 0x1 << 1) // (ADC) Start Conversion -// -------- ADC_MR : (ADC Offset: 0x4) ADC Mode Register -------- -#define AT91C_ADC_TRGEN ((unsigned int) 0x1 << 0) // (ADC) Trigger Enable -#define AT91C_ADC_TRGEN_DIS ((unsigned int) 0x0) // (ADC) Hradware triggers are disabled. Starting a conversion is only possible by software -#define AT91C_ADC_TRGEN_EN ((unsigned int) 0x1) // (ADC) Hardware trigger selected by TRGSEL field is enabled. -#define AT91C_ADC_TRGSEL ((unsigned int) 0x7 << 1) // (ADC) Trigger Selection -#define AT91C_ADC_TRGSEL_TIOA0 ((unsigned int) 0x0 << 1) // (ADC) Selected TRGSEL = TIAO0 -#define AT91C_ADC_TRGSEL_TIOA1 ((unsigned int) 0x1 << 1) // (ADC) Selected TRGSEL = TIAO1 -#define AT91C_ADC_TRGSEL_TIOA2 ((unsigned int) 0x2 << 1) // (ADC) Selected TRGSEL = TIAO2 -#define AT91C_ADC_TRGSEL_TIOA3 ((unsigned int) 0x3 << 1) // (ADC) Selected TRGSEL = TIAO3 -#define AT91C_ADC_TRGSEL_TIOA4 ((unsigned int) 0x4 << 1) // (ADC) Selected TRGSEL = TIAO4 -#define AT91C_ADC_TRGSEL_TIOA5 ((unsigned int) 0x5 << 1) // (ADC) Selected TRGSEL = TIAO5 -#define AT91C_ADC_TRGSEL_EXT ((unsigned int) 0x6 << 1) // (ADC) Selected TRGSEL = External Trigger -#define AT91C_ADC_LOWRES ((unsigned int) 0x1 << 4) // (ADC) Resolution. -#define AT91C_ADC_LOWRES_10_BIT ((unsigned int) 0x0 << 4) // (ADC) 10-bit resolution -#define AT91C_ADC_LOWRES_8_BIT ((unsigned int) 0x1 << 4) // (ADC) 8-bit resolution -#define AT91C_ADC_SLEEP ((unsigned int) 0x1 << 5) // (ADC) Sleep Mode -#define AT91C_ADC_SLEEP_NORMAL_MODE ((unsigned int) 0x0 << 5) // (ADC) Normal Mode -#define AT91C_ADC_SLEEP_MODE ((unsigned int) 0x1 << 5) // (ADC) Sleep Mode -#define AT91C_ADC_PRESCAL ((unsigned int) 0x3F << 8) // (ADC) Prescaler rate selection -#define AT91C_ADC_STARTUP ((unsigned int) 0x1F << 16) // (ADC) Startup Time -#define AT91C_ADC_SHTIM ((unsigned int) 0xF << 24) // (ADC) Sample & Hold Time -// -------- ADC_CHER : (ADC Offset: 0x10) ADC Channel Enable Register -------- -#define AT91C_ADC_CH0 ((unsigned int) 0x1 << 0) // (ADC) Channel 0 -#define AT91C_ADC_CH1 ((unsigned int) 0x1 << 1) // (ADC) Channel 1 -#define AT91C_ADC_CH2 ((unsigned int) 0x1 << 2) // (ADC) Channel 2 -#define AT91C_ADC_CH3 ((unsigned int) 0x1 << 3) // (ADC) Channel 3 -#define AT91C_ADC_CH4 ((unsigned int) 0x1 << 4) // (ADC) Channel 4 -#define AT91C_ADC_CH5 ((unsigned int) 0x1 << 5) // (ADC) Channel 5 -#define AT91C_ADC_CH6 ((unsigned int) 0x1 << 6) // (ADC) Channel 6 -#define AT91C_ADC_CH7 ((unsigned int) 0x1 << 7) // (ADC) Channel 7 -// -------- ADC_CHDR : (ADC Offset: 0x14) ADC Channel Disable Register -------- -// -------- ADC_CHSR : (ADC Offset: 0x18) ADC Channel Status Register -------- -// -------- ADC_SR : (ADC Offset: 0x1c) ADC Status Register -------- -#define AT91C_ADC_EOC0 ((unsigned int) 0x1 << 0) // (ADC) End of Conversion -#define AT91C_ADC_EOC1 ((unsigned int) 0x1 << 1) // (ADC) End of Conversion -#define AT91C_ADC_EOC2 ((unsigned int) 0x1 << 2) // (ADC) End of Conversion -#define AT91C_ADC_EOC3 ((unsigned int) 0x1 << 3) // (ADC) End of Conversion -#define AT91C_ADC_EOC4 ((unsigned int) 0x1 << 4) // (ADC) End of Conversion -#define AT91C_ADC_EOC5 ((unsigned int) 0x1 << 5) // (ADC) End of Conversion -#define AT91C_ADC_EOC6 ((unsigned int) 0x1 << 6) // (ADC) End of Conversion -#define AT91C_ADC_EOC7 ((unsigned int) 0x1 << 7) // (ADC) End of Conversion -#define AT91C_ADC_OVRE0 ((unsigned int) 0x1 << 8) // (ADC) Overrun Error -#define AT91C_ADC_OVRE1 ((unsigned int) 0x1 << 9) // (ADC) Overrun Error -#define AT91C_ADC_OVRE2 ((unsigned int) 0x1 << 10) // (ADC) Overrun Error -#define AT91C_ADC_OVRE3 ((unsigned int) 0x1 << 11) // (ADC) Overrun Error -#define AT91C_ADC_OVRE4 ((unsigned int) 0x1 << 12) // (ADC) Overrun Error -#define AT91C_ADC_OVRE5 ((unsigned int) 0x1 << 13) // (ADC) Overrun Error -#define AT91C_ADC_OVRE6 ((unsigned int) 0x1 << 14) // (ADC) Overrun Error -#define AT91C_ADC_OVRE7 ((unsigned int) 0x1 << 15) // (ADC) Overrun Error -#define AT91C_ADC_DRDY ((unsigned int) 0x1 << 16) // (ADC) Data Ready -#define AT91C_ADC_GOVRE ((unsigned int) 0x1 << 17) // (ADC) General Overrun -#define AT91C_ADC_ENDRX ((unsigned int) 0x1 << 18) // (ADC) End of Receiver Transfer -#define AT91C_ADC_RXBUFF ((unsigned int) 0x1 << 19) // (ADC) RXBUFF Interrupt -// -------- ADC_LCDR : (ADC Offset: 0x20) ADC Last Converted Data Register -------- -#define AT91C_ADC_LDATA ((unsigned int) 0x3FF << 0) // (ADC) Last Data Converted -// -------- ADC_IER : (ADC Offset: 0x24) ADC Interrupt Enable Register -------- -// -------- ADC_IDR : (ADC Offset: 0x28) ADC Interrupt Disable Register -------- -// -------- ADC_IMR : (ADC Offset: 0x2c) ADC Interrupt Mask Register -------- -// -------- ADC_CDR0 : (ADC Offset: 0x30) ADC Channel Data Register 0 -------- -#define AT91C_ADC_DATA ((unsigned int) 0x3FF << 0) // (ADC) Converted Data -// -------- ADC_CDR1 : (ADC Offset: 0x34) ADC Channel Data Register 1 -------- -// -------- ADC_CDR2 : (ADC Offset: 0x38) ADC Channel Data Register 2 -------- -// -------- ADC_CDR3 : (ADC Offset: 0x3c) ADC Channel Data Register 3 -------- -// -------- ADC_CDR4 : (ADC Offset: 0x40) ADC Channel Data Register 4 -------- -// -------- ADC_CDR5 : (ADC Offset: 0x44) ADC Channel Data Register 5 -------- -// -------- ADC_CDR6 : (ADC Offset: 0x48) ADC Channel Data Register 6 -------- -// -------- ADC_CDR7 : (ADC Offset: 0x4c) ADC Channel Data Register 7 -------- +/* -------- ADC_CR : (ADC Offset: 0x0) ADC Control Register -------- */ +#define AT91C_ADC_SWRST ( ( unsigned int ) 0x1 << 0 ) /* (ADC) Software Reset */ +#define AT91C_ADC_START ( ( unsigned int ) 0x1 << 1 ) /* (ADC) Start Conversion */ +/* -------- ADC_MR : (ADC Offset: 0x4) ADC Mode Register -------- */ +#define AT91C_ADC_TRGEN ( ( unsigned int ) 0x1 << 0 ) /* (ADC) Trigger Enable */ +#define AT91C_ADC_TRGEN_DIS ( ( unsigned int ) 0x0 ) /* (ADC) Hardware triggers are disabled. Starting a conversion is only possible by software */ +#define AT91C_ADC_TRGEN_EN ( ( unsigned int ) 0x1 ) /* (ADC) Hardware trigger selected by TRGSEL field is enabled. */ +#define AT91C_ADC_TRGSEL ( ( unsigned int ) 0x7 << 1 ) /* (ADC) Trigger Selection */ +#define AT91C_ADC_TRGSEL_TIOA0 ( ( unsigned int ) 0x0 << 1 ) /* (ADC) Selected TRGSEL = TIAO0 */ +#define AT91C_ADC_TRGSEL_TIOA1 ( ( unsigned int ) 0x1 << 1 ) /* (ADC) Selected TRGSEL = TIAO1 */ +#define AT91C_ADC_TRGSEL_TIOA2 ( ( unsigned int ) 0x2 << 1 ) /* (ADC) Selected TRGSEL = TIAO2 */ +#define AT91C_ADC_TRGSEL_TIOA3 ( ( unsigned int ) 0x3 << 1 ) /* (ADC) Selected TRGSEL = TIAO3 */ +#define AT91C_ADC_TRGSEL_TIOA4 ( ( unsigned int ) 0x4 << 1 ) /* (ADC) Selected TRGSEL = TIAO4 */ +#define AT91C_ADC_TRGSEL_TIOA5 ( ( unsigned int ) 0x5 << 1 ) /* (ADC) Selected TRGSEL = TIAO5 */ +#define AT91C_ADC_TRGSEL_EXT ( ( unsigned int ) 0x6 << 1 ) /* (ADC) Selected TRGSEL = External Trigger */ +#define AT91C_ADC_LOWRES ( ( unsigned int ) 0x1 << 4 ) /* (ADC) Resolution. */ +#define AT91C_ADC_LOWRES_10_BIT ( ( unsigned int ) 0x0 << 4 ) /* (ADC) 10-bit resolution */ +#define AT91C_ADC_LOWRES_8_BIT ( ( unsigned int ) 0x1 << 4 ) /* (ADC) 8-bit resolution */ +#define AT91C_ADC_SLEEP ( ( unsigned int ) 0x1 << 5 ) /* (ADC) Sleep Mode */ +#define AT91C_ADC_SLEEP_NORMAL_MODE ( ( unsigned int ) 0x0 << 5 ) /* (ADC) Normal Mode */ +#define AT91C_ADC_SLEEP_MODE ( ( unsigned int ) 0x1 << 5 ) /* (ADC) Sleep Mode */ +#define AT91C_ADC_PRESCAL ( ( unsigned int ) 0x3F << 8 ) /* (ADC) Prescaler rate selection */ +#define AT91C_ADC_STARTUP ( ( unsigned int ) 0x1F << 16 ) /* (ADC) Startup Time */ +#define AT91C_ADC_SHTIM ( ( unsigned int ) 0xF << 24 ) /* (ADC) Sample & Hold Time */ +/* -------- ADC_CHER : (ADC Offset: 0x10) ADC Channel Enable Register -------- */ +#define AT91C_ADC_CH0 ( ( unsigned int ) 0x1 << 0 ) /* (ADC) Channel 0 */ +#define AT91C_ADC_CH1 ( ( unsigned int ) 0x1 << 1 ) /* (ADC) Channel 1 */ +#define AT91C_ADC_CH2 ( ( unsigned int ) 0x1 << 2 ) /* (ADC) Channel 2 */ +#define AT91C_ADC_CH3 ( ( unsigned int ) 0x1 << 3 ) /* (ADC) Channel 3 */ +#define AT91C_ADC_CH4 ( ( unsigned int ) 0x1 << 4 ) /* (ADC) Channel 4 */ +#define AT91C_ADC_CH5 ( ( unsigned int ) 0x1 << 5 ) /* (ADC) Channel 5 */ +#define AT91C_ADC_CH6 ( ( unsigned int ) 0x1 << 6 ) /* (ADC) Channel 6 */ +#define AT91C_ADC_CH7 ( ( unsigned int ) 0x1 << 7 ) /* (ADC) Channel 7 */ +/* -------- ADC_CHDR : (ADC Offset: 0x14) ADC Channel Disable Register -------- */ +/* -------- ADC_CHSR : (ADC Offset: 0x18) ADC Channel Status Register -------- */ +/* -------- ADC_SR : (ADC Offset: 0x1c) ADC Status Register -------- */ +#define AT91C_ADC_EOC0 ( ( unsigned int ) 0x1 << 0 ) /* (ADC) End of Conversion */ +#define AT91C_ADC_EOC1 ( ( unsigned int ) 0x1 << 1 ) /* (ADC) End of Conversion */ +#define AT91C_ADC_EOC2 ( ( unsigned int ) 0x1 << 2 ) /* (ADC) End of Conversion */ +#define AT91C_ADC_EOC3 ( ( unsigned int ) 0x1 << 3 ) /* (ADC) End of Conversion */ +#define AT91C_ADC_EOC4 ( ( unsigned int ) 0x1 << 4 ) /* (ADC) End of Conversion */ +#define AT91C_ADC_EOC5 ( ( unsigned int ) 0x1 << 5 ) /* (ADC) End of Conversion */ +#define AT91C_ADC_EOC6 ( ( unsigned int ) 0x1 << 6 ) /* (ADC) End of Conversion */ +#define AT91C_ADC_EOC7 ( ( unsigned int ) 0x1 << 7 ) /* (ADC) End of Conversion */ +#define AT91C_ADC_OVRE0 ( ( unsigned int ) 0x1 << 8 ) /* (ADC) Overrun Error */ +#define AT91C_ADC_OVRE1 ( ( unsigned int ) 0x1 << 9 ) /* (ADC) Overrun Error */ +#define AT91C_ADC_OVRE2 ( ( unsigned int ) 0x1 << 10 ) /* (ADC) Overrun Error */ +#define AT91C_ADC_OVRE3 ( ( unsigned int ) 0x1 << 11 ) /* (ADC) Overrun Error */ +#define AT91C_ADC_OVRE4 ( ( unsigned int ) 0x1 << 12 ) /* (ADC) Overrun Error */ +#define AT91C_ADC_OVRE5 ( ( unsigned int ) 0x1 << 13 ) /* (ADC) Overrun Error */ +#define AT91C_ADC_OVRE6 ( ( unsigned int ) 0x1 << 14 ) /* (ADC) Overrun Error */ +#define AT91C_ADC_OVRE7 ( ( unsigned int ) 0x1 << 15 ) /* (ADC) Overrun Error */ +#define AT91C_ADC_DRDY ( ( unsigned int ) 0x1 << 16 ) /* (ADC) Data Ready */ +#define AT91C_ADC_GOVRE ( ( unsigned int ) 0x1 << 17 ) /* (ADC) General Overrun */ +#define AT91C_ADC_ENDRX ( ( unsigned int ) 0x1 << 18 ) /* (ADC) End of Receiver Transfer */ +#define AT91C_ADC_RXBUFF ( ( unsigned int ) 0x1 << 19 ) /* (ADC) RXBUFF Interrupt */ +/* -------- ADC_LCDR : (ADC Offset: 0x20) ADC Last Converted Data Register -------- */ +#define AT91C_ADC_LDATA ( ( unsigned int ) 0x3FF << 0 ) /* (ADC) Last Data Converted */ +/* -------- ADC_IER : (ADC Offset: 0x24) ADC Interrupt Enable Register -------- */ +/* -------- ADC_IDR : (ADC Offset: 0x28) ADC Interrupt Disable Register -------- */ +/* -------- ADC_IMR : (ADC Offset: 0x2c) ADC Interrupt Mask Register -------- */ +/* -------- ADC_CDR0 : (ADC Offset: 0x30) ADC Channel Data Register 0 -------- */ +#define AT91C_ADC_DATA ( ( unsigned int ) 0x3FF << 0 ) /* (ADC) Converted Data */ +/* -------- ADC_CDR1 : (ADC Offset: 0x34) ADC Channel Data Register 1 -------- */ +/* -------- ADC_CDR2 : (ADC Offset: 0x38) ADC Channel Data Register 2 -------- */ +/* -------- ADC_CDR3 : (ADC Offset: 0x3c) ADC Channel Data Register 3 -------- */ +/* -------- ADC_CDR4 : (ADC Offset: 0x40) ADC Channel Data Register 4 -------- */ +/* -------- ADC_CDR5 : (ADC Offset: 0x44) ADC Channel Data Register 5 -------- */ +/* -------- ADC_CDR6 : (ADC Offset: 0x48) ADC Channel Data Register 6 -------- */ +/* -------- ADC_CDR7 : (ADC Offset: 0x4c) ADC Channel Data Register 7 -------- */ -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Advanced Encryption Standard -// ***************************************************************************** -typedef struct _AT91S_AES { - AT91_REG AES_CR; // Control Register - AT91_REG AES_MR; // Mode Register - AT91_REG Reserved0[2]; // - AT91_REG AES_IER; // Interrupt Enable Register - AT91_REG AES_IDR; // Interrupt Disable Register - AT91_REG AES_IMR; // Interrupt Mask Register - AT91_REG AES_ISR; // Interrupt Status Register - AT91_REG AES_KEYWxR[4]; // Key Word x Register - AT91_REG Reserved1[4]; // - AT91_REG AES_IDATAxR[4]; // Input Data x Register - AT91_REG AES_ODATAxR[4]; // Output Data x Register - AT91_REG AES_IVxR[4]; // Initialization Vector x Register - AT91_REG Reserved2[35]; // - AT91_REG AES_VR; // AES Version Register - AT91_REG AES_RPR; // Receive Pointer Register - AT91_REG AES_RCR; // Receive Counter Register - AT91_REG AES_TPR; // Transmit Pointer Register - AT91_REG AES_TCR; // Transmit Counter Register - AT91_REG AES_RNPR; // Receive Next Pointer Register - AT91_REG AES_RNCR; // Receive Next Counter Register - AT91_REG AES_TNPR; // Transmit Next Pointer Register - AT91_REG AES_TNCR; // Transmit Next Counter Register - AT91_REG AES_PTCR; // PDC Transfer Control Register - AT91_REG AES_PTSR; // PDC Transfer Status Register -} AT91S_AES, *AT91PS_AES; +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR Advanced Encryption Standard */ +/* ***************************************************************************** */ +typedef struct _AT91S_AES +{ + AT91_REG AES_CR; /* Control Register */ + AT91_REG AES_MR; /* Mode Register */ + AT91_REG Reserved0[ 2 ]; /* */ + AT91_REG AES_IER; /* Interrupt Enable Register */ + AT91_REG AES_IDR; /* Interrupt Disable Register */ + AT91_REG AES_IMR; /* Interrupt Mask Register */ + AT91_REG AES_ISR; /* Interrupt Status Register */ + AT91_REG AES_KEYWxR[ 4 ]; /* Key Word x Register */ + AT91_REG Reserved1[ 4 ]; /* */ + AT91_REG AES_IDATAxR[ 4 ]; /* Input Data x Register */ + AT91_REG AES_ODATAxR[ 4 ]; /* Output Data x Register */ + AT91_REG AES_IVxR[ 4 ]; /* Initialization Vector x Register */ + AT91_REG Reserved2[ 35 ]; /* */ + AT91_REG AES_VR; /* AES Version Register */ + AT91_REG AES_RPR; /* Receive Pointer Register */ + AT91_REG AES_RCR; /* Receive Counter Register */ + AT91_REG AES_TPR; /* Transmit Pointer Register */ + AT91_REG AES_TCR; /* Transmit Counter Register */ + AT91_REG AES_RNPR; /* Receive Next Pointer Register */ + AT91_REG AES_RNCR; /* Receive Next Counter Register */ + AT91_REG AES_TNPR; /* Transmit Next Pointer Register */ + AT91_REG AES_TNCR; /* Transmit Next Counter Register */ + AT91_REG AES_PTCR; /* PDC Transfer Control Register */ + AT91_REG AES_PTSR; /* PDC Transfer Status Register */ +} AT91S_AES, * AT91PS_AES; -// -------- AES_CR : (AES Offset: 0x0) Control Register -------- -#define AT91C_AES_START ((unsigned int) 0x1 << 0) // (AES) Starts Processing -#define AT91C_AES_SWRST ((unsigned int) 0x1 << 8) // (AES) Software Reset -#define AT91C_AES_LOADSEED ((unsigned int) 0x1 << 16) // (AES) Random Number Generator Seed Loading -// -------- AES_MR : (AES Offset: 0x4) Mode Register -------- -#define AT91C_AES_CIPHER ((unsigned int) 0x1 << 0) // (AES) Processing Mode -#define AT91C_AES_PROCDLY ((unsigned int) 0xF << 4) // (AES) Processing Delay -#define AT91C_AES_SMOD ((unsigned int) 0x3 << 8) // (AES) Start Mode -#define AT91C_AES_SMOD_MANUAL ((unsigned int) 0x0 << 8) // (AES) Manual Mode: The START bit in register AES_CR must be set to begin encryption or decryption. -#define AT91C_AES_SMOD_AUTO ((unsigned int) 0x1 << 8) // (AES) Auto Mode: no action in AES_CR is necessary (cf datasheet). -#define AT91C_AES_SMOD_PDC ((unsigned int) 0x2 << 8) // (AES) PDC Mode (cf datasheet). -#define AT91C_AES_OPMOD ((unsigned int) 0x7 << 12) // (AES) Operation Mode -#define AT91C_AES_OPMOD_ECB ((unsigned int) 0x0 << 12) // (AES) ECB Electronic CodeBook mode. -#define AT91C_AES_OPMOD_CBC ((unsigned int) 0x1 << 12) // (AES) CBC Cipher Block Chaining mode. -#define AT91C_AES_OPMOD_OFB ((unsigned int) 0x2 << 12) // (AES) OFB Output Feedback mode. -#define AT91C_AES_OPMOD_CFB ((unsigned int) 0x3 << 12) // (AES) CFB Cipher Feedback mode. -#define AT91C_AES_OPMOD_CTR ((unsigned int) 0x4 << 12) // (AES) CTR Counter mode. -#define AT91C_AES_LOD ((unsigned int) 0x1 << 15) // (AES) Last Output Data Mode -#define AT91C_AES_CFBS ((unsigned int) 0x7 << 16) // (AES) Cipher Feedback Data Size -#define AT91C_AES_CFBS_128_BIT ((unsigned int) 0x0 << 16) // (AES) 128-bit. -#define AT91C_AES_CFBS_64_BIT ((unsigned int) 0x1 << 16) // (AES) 64-bit. -#define AT91C_AES_CFBS_32_BIT ((unsigned int) 0x2 << 16) // (AES) 32-bit. -#define AT91C_AES_CFBS_16_BIT ((unsigned int) 0x3 << 16) // (AES) 16-bit. -#define AT91C_AES_CFBS_8_BIT ((unsigned int) 0x4 << 16) // (AES) 8-bit. -#define AT91C_AES_CKEY ((unsigned int) 0xF << 20) // (AES) Countermeasure Key -#define AT91C_AES_CTYPE ((unsigned int) 0x1F << 24) // (AES) Countermeasure Type -#define AT91C_AES_CTYPE_TYPE1_EN ((unsigned int) 0x1 << 24) // (AES) Countermeasure type 1 is enabled. -#define AT91C_AES_CTYPE_TYPE2_EN ((unsigned int) 0x2 << 24) // (AES) Countermeasure type 2 is enabled. -#define AT91C_AES_CTYPE_TYPE3_EN ((unsigned int) 0x4 << 24) // (AES) Countermeasure type 3 is enabled. -#define AT91C_AES_CTYPE_TYPE4_EN ((unsigned int) 0x8 << 24) // (AES) Countermeasure type 4 is enabled. -#define AT91C_AES_CTYPE_TYPE5_EN ((unsigned int) 0x10 << 24) // (AES) Countermeasure type 5 is enabled. -// -------- AES_IER : (AES Offset: 0x10) Interrupt Enable Register -------- -#define AT91C_AES_DATRDY ((unsigned int) 0x1 << 0) // (AES) DATRDY -#define AT91C_AES_ENDRX ((unsigned int) 0x1 << 1) // (AES) PDC Read Buffer End -#define AT91C_AES_ENDTX ((unsigned int) 0x1 << 2) // (AES) PDC Write Buffer End -#define AT91C_AES_RXBUFF ((unsigned int) 0x1 << 3) // (AES) PDC Read Buffer Full -#define AT91C_AES_TXBUFE ((unsigned int) 0x1 << 4) // (AES) PDC Write Buffer Empty -#define AT91C_AES_URAD ((unsigned int) 0x1 << 8) // (AES) Unspecified Register Access Detection -// -------- AES_IDR : (AES Offset: 0x14) Interrupt Disable Register -------- -// -------- AES_IMR : (AES Offset: 0x18) Interrupt Mask Register -------- -// -------- AES_ISR : (AES Offset: 0x1c) Interrupt Status Register -------- -#define AT91C_AES_URAT ((unsigned int) 0x7 << 12) // (AES) Unspecified Register Access Type Status -#define AT91C_AES_URAT_IN_DAT_WRITE_DATPROC ((unsigned int) 0x0 << 12) // (AES) Input data register written during the data processing in PDC mode. -#define AT91C_AES_URAT_OUT_DAT_READ_DATPROC ((unsigned int) 0x1 << 12) // (AES) Output data register read during the data processing. -#define AT91C_AES_URAT_MODEREG_WRITE_DATPROC ((unsigned int) 0x2 << 12) // (AES) Mode register written during the data processing. -#define AT91C_AES_URAT_OUT_DAT_READ_SUBKEY ((unsigned int) 0x3 << 12) // (AES) Output data register read during the sub-keys generation. -#define AT91C_AES_URAT_MODEREG_WRITE_SUBKEY ((unsigned int) 0x4 << 12) // (AES) Mode register written during the sub-keys generation. -#define AT91C_AES_URAT_WO_REG_READ ((unsigned int) 0x5 << 12) // (AES) Write-only register read access. +/* -------- AES_CR : (AES Offset: 0x0) Control Register -------- */ +#define AT91C_AES_START ( ( unsigned int ) 0x1 << 0 ) /* (AES) Starts Processing */ +#define AT91C_AES_SWRST ( ( unsigned int ) 0x1 << 8 ) /* (AES) Software Reset */ +#define AT91C_AES_LOADSEED ( ( unsigned int ) 0x1 << 16 ) /* (AES) Random Number Generator Seed Loading */ +/* -------- AES_MR : (AES Offset: 0x4) Mode Register -------- */ +#define AT91C_AES_CIPHER ( ( unsigned int ) 0x1 << 0 ) /* (AES) Processing Mode */ +#define AT91C_AES_PROCDLY ( ( unsigned int ) 0xF << 4 ) /* (AES) Processing Delay */ +#define AT91C_AES_SMOD ( ( unsigned int ) 0x3 << 8 ) /* (AES) Start Mode */ +#define AT91C_AES_SMOD_MANUAL ( ( unsigned int ) 0x0 << 8 ) /* (AES) Manual Mode: The START bit in register AES_CR must be set to begin encryption or decryption. */ +#define AT91C_AES_SMOD_AUTO ( ( unsigned int ) 0x1 << 8 ) /* (AES) Auto Mode: no action in AES_CR is necessary (cf datasheet). */ +#define AT91C_AES_SMOD_PDC ( ( unsigned int ) 0x2 << 8 ) /* (AES) PDC Mode (cf datasheet). */ +#define AT91C_AES_OPMOD ( ( unsigned int ) 0x7 << 12 ) /* (AES) Operation Mode */ +#define AT91C_AES_OPMOD_ECB ( ( unsigned int ) 0x0 << 12 ) /* (AES) ECB Electronic CodeBook mode. */ +#define AT91C_AES_OPMOD_CBC ( ( unsigned int ) 0x1 << 12 ) /* (AES) CBC Cipher Block Chaining mode. */ +#define AT91C_AES_OPMOD_OFB ( ( unsigned int ) 0x2 << 12 ) /* (AES) OFB Output Feedback mode. */ +#define AT91C_AES_OPMOD_CFB ( ( unsigned int ) 0x3 << 12 ) /* (AES) CFB Cipher Feedback mode. */ +#define AT91C_AES_OPMOD_CTR ( ( unsigned int ) 0x4 << 12 ) /* (AES) CTR Counter mode. */ +#define AT91C_AES_LOD ( ( unsigned int ) 0x1 << 15 ) /* (AES) Last Output Data Mode */ +#define AT91C_AES_CFBS ( ( unsigned int ) 0x7 << 16 ) /* (AES) Cipher Feedback Data Size */ +#define AT91C_AES_CFBS_128_BIT ( ( unsigned int ) 0x0 << 16 ) /* (AES) 128-bit. */ +#define AT91C_AES_CFBS_64_BIT ( ( unsigned int ) 0x1 << 16 ) /* (AES) 64-bit. */ +#define AT91C_AES_CFBS_32_BIT ( ( unsigned int ) 0x2 << 16 ) /* (AES) 32-bit. */ +#define AT91C_AES_CFBS_16_BIT ( ( unsigned int ) 0x3 << 16 ) /* (AES) 16-bit. */ +#define AT91C_AES_CFBS_8_BIT ( ( unsigned int ) 0x4 << 16 ) /* (AES) 8-bit. */ +#define AT91C_AES_CKEY ( ( unsigned int ) 0xF << 20 ) /* (AES) Countermeasure Key */ +#define AT91C_AES_CTYPE ( ( unsigned int ) 0x1F << 24 ) /* (AES) Countermeasure Type */ +#define AT91C_AES_CTYPE_TYPE1_EN ( ( unsigned int ) 0x1 << 24 ) /* (AES) Countermeasure type 1 is enabled. */ +#define AT91C_AES_CTYPE_TYPE2_EN ( ( unsigned int ) 0x2 << 24 ) /* (AES) Countermeasure type 2 is enabled. */ +#define AT91C_AES_CTYPE_TYPE3_EN ( ( unsigned int ) 0x4 << 24 ) /* (AES) Countermeasure type 3 is enabled. */ +#define AT91C_AES_CTYPE_TYPE4_EN ( ( unsigned int ) 0x8 << 24 ) /* (AES) Countermeasure type 4 is enabled. */ +#define AT91C_AES_CTYPE_TYPE5_EN ( ( unsigned int ) 0x10 << 24 ) /* (AES) Countermeasure type 5 is enabled. */ +/* -------- AES_IER : (AES Offset: 0x10) Interrupt Enable Register -------- */ +#define AT91C_AES_DATRDY ( ( unsigned int ) 0x1 << 0 ) /* (AES) DATRDY */ +#define AT91C_AES_ENDRX ( ( unsigned int ) 0x1 << 1 ) /* (AES) PDC Read Buffer End */ +#define AT91C_AES_ENDTX ( ( unsigned int ) 0x1 << 2 ) /* (AES) PDC Write Buffer End */ +#define AT91C_AES_RXBUFF ( ( unsigned int ) 0x1 << 3 ) /* (AES) PDC Read Buffer Full */ +#define AT91C_AES_TXBUFE ( ( unsigned int ) 0x1 << 4 ) /* (AES) PDC Write Buffer Empty */ +#define AT91C_AES_URAD ( ( unsigned int ) 0x1 << 8 ) /* (AES) Unspecified Register Access Detection */ +/* -------- AES_IDR : (AES Offset: 0x14) Interrupt Disable Register -------- */ +/* -------- AES_IMR : (AES Offset: 0x18) Interrupt Mask Register -------- */ +/* -------- AES_ISR : (AES Offset: 0x1c) Interrupt Status Register -------- */ +#define AT91C_AES_URAT ( ( unsigned int ) 0x7 << 12 ) /* (AES) Unspecified Register Access Type Status */ +#define AT91C_AES_URAT_IN_DAT_WRITE_DATPROC ( ( unsigned int ) 0x0 << 12 ) /* (AES) Input data register written during the data processing in PDC mode. */ +#define AT91C_AES_URAT_OUT_DAT_READ_DATPROC ( ( unsigned int ) 0x1 << 12 ) /* (AES) Output data register read during the data processing. */ +#define AT91C_AES_URAT_MODEREG_WRITE_DATPROC ( ( unsigned int ) 0x2 << 12 ) /* (AES) Mode register written during the data processing. */ +#define AT91C_AES_URAT_OUT_DAT_READ_SUBKEY ( ( unsigned int ) 0x3 << 12 ) /* (AES) Output data register read during the sub-keys generation. */ +#define AT91C_AES_URAT_MODEREG_WRITE_SUBKEY ( ( unsigned int ) 0x4 << 12 ) /* (AES) Mode register written during the sub-keys generation. */ +#define AT91C_AES_URAT_WO_REG_READ ( ( unsigned int ) 0x5 << 12 ) /* (AES) Write-only register read access. */ -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Triple Data Encryption Standard -// ***************************************************************************** -typedef struct _AT91S_TDES { - AT91_REG TDES_CR; // Control Register - AT91_REG TDES_MR; // Mode Register - AT91_REG Reserved0[2]; // - AT91_REG TDES_IER; // Interrupt Enable Register - AT91_REG TDES_IDR; // Interrupt Disable Register - AT91_REG TDES_IMR; // Interrupt Mask Register - AT91_REG TDES_ISR; // Interrupt Status Register - AT91_REG TDES_KEY1WxR[2]; // Key 1 Word x Register - AT91_REG TDES_KEY2WxR[2]; // Key 2 Word x Register - AT91_REG TDES_KEY3WxR[2]; // Key 3 Word x Register - AT91_REG Reserved1[2]; // - AT91_REG TDES_IDATAxR[2]; // Input Data x Register - AT91_REG Reserved2[2]; // - AT91_REG TDES_ODATAxR[2]; // Output Data x Register - AT91_REG Reserved3[2]; // - AT91_REG TDES_IVxR[2]; // Initialization Vector x Register - AT91_REG Reserved4[37]; // - AT91_REG TDES_VR; // TDES Version Register - AT91_REG TDES_RPR; // Receive Pointer Register - AT91_REG TDES_RCR; // Receive Counter Register - AT91_REG TDES_TPR; // Transmit Pointer Register - AT91_REG TDES_TCR; // Transmit Counter Register - AT91_REG TDES_RNPR; // Receive Next Pointer Register - AT91_REG TDES_RNCR; // Receive Next Counter Register - AT91_REG TDES_TNPR; // Transmit Next Pointer Register - AT91_REG TDES_TNCR; // Transmit Next Counter Register - AT91_REG TDES_PTCR; // PDC Transfer Control Register - AT91_REG TDES_PTSR; // PDC Transfer Status Register -} AT91S_TDES, *AT91PS_TDES; +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR Triple Data Encryption Standard */ +/* ***************************************************************************** */ +typedef struct _AT91S_TDES +{ + AT91_REG TDES_CR; /* Control Register */ + AT91_REG TDES_MR; /* Mode Register */ + AT91_REG Reserved0[ 2 ]; /* */ + AT91_REG TDES_IER; /* Interrupt Enable Register */ + AT91_REG TDES_IDR; /* Interrupt Disable Register */ + AT91_REG TDES_IMR; /* Interrupt Mask Register */ + AT91_REG TDES_ISR; /* Interrupt Status Register */ + AT91_REG TDES_KEY1WxR[ 2 ]; /* Key 1 Word x Register */ + AT91_REG TDES_KEY2WxR[ 2 ]; /* Key 2 Word x Register */ + AT91_REG TDES_KEY3WxR[ 2 ]; /* Key 3 Word x Register */ + AT91_REG Reserved1[ 2 ]; /* */ + AT91_REG TDES_IDATAxR[ 2 ]; /* Input Data x Register */ + AT91_REG Reserved2[ 2 ]; /* */ + AT91_REG TDES_ODATAxR[ 2 ]; /* Output Data x Register */ + AT91_REG Reserved3[ 2 ]; /* */ + AT91_REG TDES_IVxR[ 2 ]; /* Initialization Vector x Register */ + AT91_REG Reserved4[ 37 ]; /* */ + AT91_REG TDES_VR; /* TDES Version Register */ + AT91_REG TDES_RPR; /* Receive Pointer Register */ + AT91_REG TDES_RCR; /* Receive Counter Register */ + AT91_REG TDES_TPR; /* Transmit Pointer Register */ + AT91_REG TDES_TCR; /* Transmit Counter Register */ + AT91_REG TDES_RNPR; /* Receive Next Pointer Register */ + AT91_REG TDES_RNCR; /* Receive Next Counter Register */ + AT91_REG TDES_TNPR; /* Transmit Next Pointer Register */ + AT91_REG TDES_TNCR; /* Transmit Next Counter Register */ + AT91_REG TDES_PTCR; /* PDC Transfer Control Register */ + AT91_REG TDES_PTSR; /* PDC Transfer Status Register */ +} AT91S_TDES, * AT91PS_TDES; -// -------- TDES_CR : (TDES Offset: 0x0) Control Register -------- -#define AT91C_TDES_START ((unsigned int) 0x1 << 0) // (TDES) Starts Processing -#define AT91C_TDES_SWRST ((unsigned int) 0x1 << 8) // (TDES) Software Reset -// -------- TDES_MR : (TDES Offset: 0x4) Mode Register -------- -#define AT91C_TDES_CIPHER ((unsigned int) 0x1 << 0) // (TDES) Processing Mode -#define AT91C_TDES_TDESMOD ((unsigned int) 0x1 << 1) // (TDES) Single or Triple DES Mode -#define AT91C_TDES_KEYMOD ((unsigned int) 0x1 << 4) // (TDES) Key Mode -#define AT91C_TDES_SMOD ((unsigned int) 0x3 << 8) // (TDES) Start Mode -#define AT91C_TDES_SMOD_MANUAL ((unsigned int) 0x0 << 8) // (TDES) Manual Mode: The START bit in register TDES_CR must be set to begin encryption or decryption. -#define AT91C_TDES_SMOD_AUTO ((unsigned int) 0x1 << 8) // (TDES) Auto Mode: no action in TDES_CR is necessary (cf datasheet). -#define AT91C_TDES_SMOD_PDC ((unsigned int) 0x2 << 8) // (TDES) PDC Mode (cf datasheet). -#define AT91C_TDES_OPMOD ((unsigned int) 0x3 << 12) // (TDES) Operation Mode -#define AT91C_TDES_OPMOD_ECB ((unsigned int) 0x0 << 12) // (TDES) ECB Electronic CodeBook mode. -#define AT91C_TDES_OPMOD_CBC ((unsigned int) 0x1 << 12) // (TDES) CBC Cipher Block Chaining mode. -#define AT91C_TDES_OPMOD_OFB ((unsigned int) 0x2 << 12) // (TDES) OFB Output Feedback mode. -#define AT91C_TDES_OPMOD_CFB ((unsigned int) 0x3 << 12) // (TDES) CFB Cipher Feedback mode. -#define AT91C_TDES_LOD ((unsigned int) 0x1 << 15) // (TDES) Last Output Data Mode -#define AT91C_TDES_CFBS ((unsigned int) 0x3 << 16) // (TDES) Cipher Feedback Data Size -#define AT91C_TDES_CFBS_64_BIT ((unsigned int) 0x0 << 16) // (TDES) 64-bit. -#define AT91C_TDES_CFBS_32_BIT ((unsigned int) 0x1 << 16) // (TDES) 32-bit. -#define AT91C_TDES_CFBS_16_BIT ((unsigned int) 0x2 << 16) // (TDES) 16-bit. -#define AT91C_TDES_CFBS_8_BIT ((unsigned int) 0x3 << 16) // (TDES) 8-bit. -// -------- TDES_IER : (TDES Offset: 0x10) Interrupt Enable Register -------- -#define AT91C_TDES_DATRDY ((unsigned int) 0x1 << 0) // (TDES) DATRDY -#define AT91C_TDES_ENDRX ((unsigned int) 0x1 << 1) // (TDES) PDC Read Buffer End -#define AT91C_TDES_ENDTX ((unsigned int) 0x1 << 2) // (TDES) PDC Write Buffer End -#define AT91C_TDES_RXBUFF ((unsigned int) 0x1 << 3) // (TDES) PDC Read Buffer Full -#define AT91C_TDES_TXBUFE ((unsigned int) 0x1 << 4) // (TDES) PDC Write Buffer Empty -#define AT91C_TDES_URAD ((unsigned int) 0x1 << 8) // (TDES) Unspecified Register Access Detection -// -------- TDES_IDR : (TDES Offset: 0x14) Interrupt Disable Register -------- -// -------- TDES_IMR : (TDES Offset: 0x18) Interrupt Mask Register -------- -// -------- TDES_ISR : (TDES Offset: 0x1c) Interrupt Status Register -------- -#define AT91C_TDES_URAT ((unsigned int) 0x3 << 12) // (TDES) Unspecified Register Access Type Status -#define AT91C_TDES_URAT_IN_DAT_WRITE_DATPROC ((unsigned int) 0x0 << 12) // (TDES) Input data register written during the data processing in PDC mode. -#define AT91C_TDES_URAT_OUT_DAT_READ_DATPROC ((unsigned int) 0x1 << 12) // (TDES) Output data register read during the data processing. -#define AT91C_TDES_URAT_MODEREG_WRITE_DATPROC ((unsigned int) 0x2 << 12) // (TDES) Mode register written during the data processing. -#define AT91C_TDES_URAT_WO_REG_READ ((unsigned int) 0x3 << 12) // (TDES) Write-only register read access. +/* -------- TDES_CR : (TDES Offset: 0x0) Control Register -------- */ +#define AT91C_TDES_START ( ( unsigned int ) 0x1 << 0 ) /* (TDES) Starts Processing */ +#define AT91C_TDES_SWRST ( ( unsigned int ) 0x1 << 8 ) /* (TDES) Software Reset */ +/* -------- TDES_MR : (TDES Offset: 0x4) Mode Register -------- */ +#define AT91C_TDES_CIPHER ( ( unsigned int ) 0x1 << 0 ) /* (TDES) Processing Mode */ +#define AT91C_TDES_TDESMOD ( ( unsigned int ) 0x1 << 1 ) /* (TDES) Single or Triple DES Mode */ +#define AT91C_TDES_KEYMOD ( ( unsigned int ) 0x1 << 4 ) /* (TDES) Key Mode */ +#define AT91C_TDES_SMOD ( ( unsigned int ) 0x3 << 8 ) /* (TDES) Start Mode */ +#define AT91C_TDES_SMOD_MANUAL ( ( unsigned int ) 0x0 << 8 ) /* (TDES) Manual Mode: The START bit in register TDES_CR must be set to begin encryption or decryption. */ +#define AT91C_TDES_SMOD_AUTO ( ( unsigned int ) 0x1 << 8 ) /* (TDES) Auto Mode: no action in TDES_CR is necessary (cf datasheet). */ +#define AT91C_TDES_SMOD_PDC ( ( unsigned int ) 0x2 << 8 ) /* (TDES) PDC Mode (cf datasheet). */ +#define AT91C_TDES_OPMOD ( ( unsigned int ) 0x3 << 12 ) /* (TDES) Operation Mode */ +#define AT91C_TDES_OPMOD_ECB ( ( unsigned int ) 0x0 << 12 ) /* (TDES) ECB Electronic CodeBook mode. */ +#define AT91C_TDES_OPMOD_CBC ( ( unsigned int ) 0x1 << 12 ) /* (TDES) CBC Cipher Block Chaining mode. */ +#define AT91C_TDES_OPMOD_OFB ( ( unsigned int ) 0x2 << 12 ) /* (TDES) OFB Output Feedback mode. */ +#define AT91C_TDES_OPMOD_CFB ( ( unsigned int ) 0x3 << 12 ) /* (TDES) CFB Cipher Feedback mode. */ +#define AT91C_TDES_LOD ( ( unsigned int ) 0x1 << 15 ) /* (TDES) Last Output Data Mode */ +#define AT91C_TDES_CFBS ( ( unsigned int ) 0x3 << 16 ) /* (TDES) Cipher Feedback Data Size */ +#define AT91C_TDES_CFBS_64_BIT ( ( unsigned int ) 0x0 << 16 ) /* (TDES) 64-bit. */ +#define AT91C_TDES_CFBS_32_BIT ( ( unsigned int ) 0x1 << 16 ) /* (TDES) 32-bit. */ +#define AT91C_TDES_CFBS_16_BIT ( ( unsigned int ) 0x2 << 16 ) /* (TDES) 16-bit. */ +#define AT91C_TDES_CFBS_8_BIT ( ( unsigned int ) 0x3 << 16 ) /* (TDES) 8-bit. */ +/* -------- TDES_IER : (TDES Offset: 0x10) Interrupt Enable Register -------- */ +#define AT91C_TDES_DATRDY ( ( unsigned int ) 0x1 << 0 ) /* (TDES) DATRDY */ +#define AT91C_TDES_ENDRX ( ( unsigned int ) 0x1 << 1 ) /* (TDES) PDC Read Buffer End */ +#define AT91C_TDES_ENDTX ( ( unsigned int ) 0x1 << 2 ) /* (TDES) PDC Write Buffer End */ +#define AT91C_TDES_RXBUFF ( ( unsigned int ) 0x1 << 3 ) /* (TDES) PDC Read Buffer Full */ +#define AT91C_TDES_TXBUFE ( ( unsigned int ) 0x1 << 4 ) /* (TDES) PDC Write Buffer Empty */ +#define AT91C_TDES_URAD ( ( unsigned int ) 0x1 << 8 ) /* (TDES) Unspecified Register Access Detection */ +/* -------- TDES_IDR : (TDES Offset: 0x14) Interrupt Disable Register -------- */ +/* -------- TDES_IMR : (TDES Offset: 0x18) Interrupt Mask Register -------- */ +/* -------- TDES_ISR : (TDES Offset: 0x1c) Interrupt Status Register -------- */ +#define AT91C_TDES_URAT ( ( unsigned int ) 0x3 << 12 ) /* (TDES) Unspecified Register Access Type Status */ +#define AT91C_TDES_URAT_IN_DAT_WRITE_DATPROC ( ( unsigned int ) 0x0 << 12 ) /* (TDES) Input data register written during the data processing in PDC mode. */ +#define AT91C_TDES_URAT_OUT_DAT_READ_DATPROC ( ( unsigned int ) 0x1 << 12 ) /* (TDES) Output data register read during the data processing. */ +#define AT91C_TDES_URAT_MODEREG_WRITE_DATPROC ( ( unsigned int ) 0x2 << 12 ) /* (TDES) Mode register written during the data processing. */ +#define AT91C_TDES_URAT_WO_REG_READ ( ( unsigned int ) 0x3 << 12 ) /* (TDES) Write-only register read access. */ -// ***************************************************************************** -// REGISTER ADDRESS DEFINITION FOR AT91SAM7X256 -// ***************************************************************************** -// ========== Register definition for SYS peripheral ========== -// ========== Register definition for AIC peripheral ========== -#define AT91C_AIC_IVR ((AT91_REG *) 0xFFFFF100) // (AIC) IRQ Vector Register -#define AT91C_AIC_SMR ((AT91_REG *) 0xFFFFF000) // (AIC) Source Mode Register -#define AT91C_AIC_FVR ((AT91_REG *) 0xFFFFF104) // (AIC) FIQ Vector Register -#define AT91C_AIC_DCR ((AT91_REG *) 0xFFFFF138) // (AIC) Debug Control Register (Protect) -#define AT91C_AIC_EOICR ((AT91_REG *) 0xFFFFF130) // (AIC) End of Interrupt Command Register -#define AT91C_AIC_SVR ((AT91_REG *) 0xFFFFF080) // (AIC) Source Vector Register -#define AT91C_AIC_FFSR ((AT91_REG *) 0xFFFFF148) // (AIC) Fast Forcing Status Register -#define AT91C_AIC_ICCR ((AT91_REG *) 0xFFFFF128) // (AIC) Interrupt Clear Command Register -#define AT91C_AIC_ISR ((AT91_REG *) 0xFFFFF108) // (AIC) Interrupt Status Register -#define AT91C_AIC_IMR ((AT91_REG *) 0xFFFFF110) // (AIC) Interrupt Mask Register -#define AT91C_AIC_IPR ((AT91_REG *) 0xFFFFF10C) // (AIC) Interrupt Pending Register -#define AT91C_AIC_FFER ((AT91_REG *) 0xFFFFF140) // (AIC) Fast Forcing Enable Register -#define AT91C_AIC_IECR ((AT91_REG *) 0xFFFFF120) // (AIC) Interrupt Enable Command Register -#define AT91C_AIC_ISCR ((AT91_REG *) 0xFFFFF12C) // (AIC) Interrupt Set Command Register -#define AT91C_AIC_FFDR ((AT91_REG *) 0xFFFFF144) // (AIC) Fast Forcing Disable Register -#define AT91C_AIC_CISR ((AT91_REG *) 0xFFFFF114) // (AIC) Core Interrupt Status Register -#define AT91C_AIC_IDCR ((AT91_REG *) 0xFFFFF124) // (AIC) Interrupt Disable Command Register -#define AT91C_AIC_SPU ((AT91_REG *) 0xFFFFF134) // (AIC) Spurious Vector Register -// ========== Register definition for PDC_DBGU peripheral ========== -#define AT91C_DBGU_TCR ((AT91_REG *) 0xFFFFF30C) // (PDC_DBGU) Transmit Counter Register -#define AT91C_DBGU_RNPR ((AT91_REG *) 0xFFFFF310) // (PDC_DBGU) Receive Next Pointer Register -#define AT91C_DBGU_TNPR ((AT91_REG *) 0xFFFFF318) // (PDC_DBGU) Transmit Next Pointer Register -#define AT91C_DBGU_TPR ((AT91_REG *) 0xFFFFF308) // (PDC_DBGU) Transmit Pointer Register -#define AT91C_DBGU_RPR ((AT91_REG *) 0xFFFFF300) // (PDC_DBGU) Receive Pointer Register -#define AT91C_DBGU_RCR ((AT91_REG *) 0xFFFFF304) // (PDC_DBGU) Receive Counter Register -#define AT91C_DBGU_RNCR ((AT91_REG *) 0xFFFFF314) // (PDC_DBGU) Receive Next Counter Register -#define AT91C_DBGU_PTCR ((AT91_REG *) 0xFFFFF320) // (PDC_DBGU) PDC Transfer Control Register -#define AT91C_DBGU_PTSR ((AT91_REG *) 0xFFFFF324) // (PDC_DBGU) PDC Transfer Status Register -#define AT91C_DBGU_TNCR ((AT91_REG *) 0xFFFFF31C) // (PDC_DBGU) Transmit Next Counter Register -// ========== Register definition for DBGU peripheral ========== -#define AT91C_DBGU_EXID ((AT91_REG *) 0xFFFFF244) // (DBGU) Chip ID Extension Register -#define AT91C_DBGU_BRGR ((AT91_REG *) 0xFFFFF220) // (DBGU) Baud Rate Generator Register -#define AT91C_DBGU_IDR ((AT91_REG *) 0xFFFFF20C) // (DBGU) Interrupt Disable Register -#define AT91C_DBGU_CSR ((AT91_REG *) 0xFFFFF214) // (DBGU) Channel Status Register -#define AT91C_DBGU_CIDR ((AT91_REG *) 0xFFFFF240) // (DBGU) Chip ID Register -#define AT91C_DBGU_MR ((AT91_REG *) 0xFFFFF204) // (DBGU) Mode Register -#define AT91C_DBGU_IMR ((AT91_REG *) 0xFFFFF210) // (DBGU) Interrupt Mask Register -#define AT91C_DBGU_CR ((AT91_REG *) 0xFFFFF200) // (DBGU) Control Register -#define AT91C_DBGU_FNTR ((AT91_REG *) 0xFFFFF248) // (DBGU) Force NTRST Register -#define AT91C_DBGU_THR ((AT91_REG *) 0xFFFFF21C) // (DBGU) Transmitter Holding Register -#define AT91C_DBGU_RHR ((AT91_REG *) 0xFFFFF218) // (DBGU) Receiver Holding Register -#define AT91C_DBGU_IER ((AT91_REG *) 0xFFFFF208) // (DBGU) Interrupt Enable Register -// ========== Register definition for PIOA peripheral ========== -#define AT91C_PIOA_ODR ((AT91_REG *) 0xFFFFF414) // (PIOA) Output Disable Registerr -#define AT91C_PIOA_SODR ((AT91_REG *) 0xFFFFF430) // (PIOA) Set Output Data Register -#define AT91C_PIOA_ISR ((AT91_REG *) 0xFFFFF44C) // (PIOA) Interrupt Status Register -#define AT91C_PIOA_ABSR ((AT91_REG *) 0xFFFFF478) // (PIOA) AB Select Status Register -#define AT91C_PIOA_IER ((AT91_REG *) 0xFFFFF440) // (PIOA) Interrupt Enable Register -#define AT91C_PIOA_PPUDR ((AT91_REG *) 0xFFFFF460) // (PIOA) Pull-up Disable Register -#define AT91C_PIOA_IMR ((AT91_REG *) 0xFFFFF448) // (PIOA) Interrupt Mask Register -#define AT91C_PIOA_PER ((AT91_REG *) 0xFFFFF400) // (PIOA) PIO Enable Register -#define AT91C_PIOA_IFDR ((AT91_REG *) 0xFFFFF424) // (PIOA) Input Filter Disable Register -#define AT91C_PIOA_OWDR ((AT91_REG *) 0xFFFFF4A4) // (PIOA) Output Write Disable Register -#define AT91C_PIOA_MDSR ((AT91_REG *) 0xFFFFF458) // (PIOA) Multi-driver Status Register -#define AT91C_PIOA_IDR ((AT91_REG *) 0xFFFFF444) // (PIOA) Interrupt Disable Register -#define AT91C_PIOA_ODSR ((AT91_REG *) 0xFFFFF438) // (PIOA) Output Data Status Register -#define AT91C_PIOA_PPUSR ((AT91_REG *) 0xFFFFF468) // (PIOA) Pull-up Status Register -#define AT91C_PIOA_OWSR ((AT91_REG *) 0xFFFFF4A8) // (PIOA) Output Write Status Register -#define AT91C_PIOA_BSR ((AT91_REG *) 0xFFFFF474) // (PIOA) Select B Register -#define AT91C_PIOA_OWER ((AT91_REG *) 0xFFFFF4A0) // (PIOA) Output Write Enable Register -#define AT91C_PIOA_IFER ((AT91_REG *) 0xFFFFF420) // (PIOA) Input Filter Enable Register -#define AT91C_PIOA_PDSR ((AT91_REG *) 0xFFFFF43C) // (PIOA) Pin Data Status Register -#define AT91C_PIOA_PPUER ((AT91_REG *) 0xFFFFF464) // (PIOA) Pull-up Enable Register -#define AT91C_PIOA_OSR ((AT91_REG *) 0xFFFFF418) // (PIOA) Output Status Register -#define AT91C_PIOA_ASR ((AT91_REG *) 0xFFFFF470) // (PIOA) Select A Register -#define AT91C_PIOA_MDDR ((AT91_REG *) 0xFFFFF454) // (PIOA) Multi-driver Disable Register -#define AT91C_PIOA_CODR ((AT91_REG *) 0xFFFFF434) // (PIOA) Clear Output Data Register -#define AT91C_PIOA_MDER ((AT91_REG *) 0xFFFFF450) // (PIOA) Multi-driver Enable Register -#define AT91C_PIOA_PDR ((AT91_REG *) 0xFFFFF404) // (PIOA) PIO Disable Register -#define AT91C_PIOA_IFSR ((AT91_REG *) 0xFFFFF428) // (PIOA) Input Filter Status Register -#define AT91C_PIOA_OER ((AT91_REG *) 0xFFFFF410) // (PIOA) Output Enable Register -#define AT91C_PIOA_PSR ((AT91_REG *) 0xFFFFF408) // (PIOA) PIO Status Register -// ========== Register definition for PIOB peripheral ========== -#define AT91C_PIOB_OWDR ((AT91_REG *) 0xFFFFF6A4) // (PIOB) Output Write Disable Register -#define AT91C_PIOB_MDER ((AT91_REG *) 0xFFFFF650) // (PIOB) Multi-driver Enable Register -#define AT91C_PIOB_PPUSR ((AT91_REG *) 0xFFFFF668) // (PIOB) Pull-up Status Register -#define AT91C_PIOB_IMR ((AT91_REG *) 0xFFFFF648) // (PIOB) Interrupt Mask Register -#define AT91C_PIOB_ASR ((AT91_REG *) 0xFFFFF670) // (PIOB) Select A Register -#define AT91C_PIOB_PPUDR ((AT91_REG *) 0xFFFFF660) // (PIOB) Pull-up Disable Register -#define AT91C_PIOB_PSR ((AT91_REG *) 0xFFFFF608) // (PIOB) PIO Status Register -#define AT91C_PIOB_IER ((AT91_REG *) 0xFFFFF640) // (PIOB) Interrupt Enable Register -#define AT91C_PIOB_CODR ((AT91_REG *) 0xFFFFF634) // (PIOB) Clear Output Data Register -#define AT91C_PIOB_OWER ((AT91_REG *) 0xFFFFF6A0) // (PIOB) Output Write Enable Register -#define AT91C_PIOB_ABSR ((AT91_REG *) 0xFFFFF678) // (PIOB) AB Select Status Register -#define AT91C_PIOB_IFDR ((AT91_REG *) 0xFFFFF624) // (PIOB) Input Filter Disable Register -#define AT91C_PIOB_PDSR ((AT91_REG *) 0xFFFFF63C) // (PIOB) Pin Data Status Register -#define AT91C_PIOB_IDR ((AT91_REG *) 0xFFFFF644) // (PIOB) Interrupt Disable Register -#define AT91C_PIOB_OWSR ((AT91_REG *) 0xFFFFF6A8) // (PIOB) Output Write Status Register -#define AT91C_PIOB_PDR ((AT91_REG *) 0xFFFFF604) // (PIOB) PIO Disable Register -#define AT91C_PIOB_ODR ((AT91_REG *) 0xFFFFF614) // (PIOB) Output Disable Registerr -#define AT91C_PIOB_IFSR ((AT91_REG *) 0xFFFFF628) // (PIOB) Input Filter Status Register -#define AT91C_PIOB_PPUER ((AT91_REG *) 0xFFFFF664) // (PIOB) Pull-up Enable Register -#define AT91C_PIOB_SODR ((AT91_REG *) 0xFFFFF630) // (PIOB) Set Output Data Register -#define AT91C_PIOB_ISR ((AT91_REG *) 0xFFFFF64C) // (PIOB) Interrupt Status Register -#define AT91C_PIOB_ODSR ((AT91_REG *) 0xFFFFF638) // (PIOB) Output Data Status Register -#define AT91C_PIOB_OSR ((AT91_REG *) 0xFFFFF618) // (PIOB) Output Status Register -#define AT91C_PIOB_MDSR ((AT91_REG *) 0xFFFFF658) // (PIOB) Multi-driver Status Register -#define AT91C_PIOB_IFER ((AT91_REG *) 0xFFFFF620) // (PIOB) Input Filter Enable Register -#define AT91C_PIOB_BSR ((AT91_REG *) 0xFFFFF674) // (PIOB) Select B Register -#define AT91C_PIOB_MDDR ((AT91_REG *) 0xFFFFF654) // (PIOB) Multi-driver Disable Register -#define AT91C_PIOB_OER ((AT91_REG *) 0xFFFFF610) // (PIOB) Output Enable Register -#define AT91C_PIOB_PER ((AT91_REG *) 0xFFFFF600) // (PIOB) PIO Enable Register -// ========== Register definition for CKGR peripheral ========== -#define AT91C_CKGR_MOR ((AT91_REG *) 0xFFFFFC20) // (CKGR) Main Oscillator Register -#define AT91C_CKGR_PLLR ((AT91_REG *) 0xFFFFFC2C) // (CKGR) PLL Register -#define AT91C_CKGR_MCFR ((AT91_REG *) 0xFFFFFC24) // (CKGR) Main Clock Frequency Register -// ========== Register definition for PMC peripheral ========== -#define AT91C_PMC_IDR ((AT91_REG *) 0xFFFFFC64) // (PMC) Interrupt Disable Register -#define AT91C_PMC_MOR ((AT91_REG *) 0xFFFFFC20) // (PMC) Main Oscillator Register -#define AT91C_PMC_PLLR ((AT91_REG *) 0xFFFFFC2C) // (PMC) PLL Register -#define AT91C_PMC_PCER ((AT91_REG *) 0xFFFFFC10) // (PMC) Peripheral Clock Enable Register -#define AT91C_PMC_PCKR ((AT91_REG *) 0xFFFFFC40) // (PMC) Programmable Clock Register -#define AT91C_PMC_MCKR ((AT91_REG *) 0xFFFFFC30) // (PMC) Master Clock Register -#define AT91C_PMC_SCDR ((AT91_REG *) 0xFFFFFC04) // (PMC) System Clock Disable Register -#define AT91C_PMC_PCDR ((AT91_REG *) 0xFFFFFC14) // (PMC) Peripheral Clock Disable Register -#define AT91C_PMC_SCSR ((AT91_REG *) 0xFFFFFC08) // (PMC) System Clock Status Register -#define AT91C_PMC_PCSR ((AT91_REG *) 0xFFFFFC18) // (PMC) Peripheral Clock Status Register -#define AT91C_PMC_MCFR ((AT91_REG *) 0xFFFFFC24) // (PMC) Main Clock Frequency Register -#define AT91C_PMC_SCER ((AT91_REG *) 0xFFFFFC00) // (PMC) System Clock Enable Register -#define AT91C_PMC_IMR ((AT91_REG *) 0xFFFFFC6C) // (PMC) Interrupt Mask Register -#define AT91C_PMC_IER ((AT91_REG *) 0xFFFFFC60) // (PMC) Interrupt Enable Register -#define AT91C_PMC_SR ((AT91_REG *) 0xFFFFFC68) // (PMC) Status Register -// ========== Register definition for RSTC peripheral ========== -#define AT91C_RSTC_RCR ((AT91_REG *) 0xFFFFFD00) // (RSTC) Reset Control Register -#define AT91C_RSTC_RMR ((AT91_REG *) 0xFFFFFD08) // (RSTC) Reset Mode Register -#define AT91C_RSTC_RSR ((AT91_REG *) 0xFFFFFD04) // (RSTC) Reset Status Register -// ========== Register definition for RTTC peripheral ========== -#define AT91C_RTTC_RTSR ((AT91_REG *) 0xFFFFFD2C) // (RTTC) Real-time Status Register -#define AT91C_RTTC_RTMR ((AT91_REG *) 0xFFFFFD20) // (RTTC) Real-time Mode Register -#define AT91C_RTTC_RTVR ((AT91_REG *) 0xFFFFFD28) // (RTTC) Real-time Value Register -#define AT91C_RTTC_RTAR ((AT91_REG *) 0xFFFFFD24) // (RTTC) Real-time Alarm Register -// ========== Register definition for PITC peripheral ========== -#define AT91C_PITC_PIVR ((AT91_REG *) 0xFFFFFD38) // (PITC) Period Interval Value Register -#define AT91C_PITC_PISR ((AT91_REG *) 0xFFFFFD34) // (PITC) Period Interval Status Register -#define AT91C_PITC_PIIR ((AT91_REG *) 0xFFFFFD3C) // (PITC) Period Interval Image Register -#define AT91C_PITC_PIMR ((AT91_REG *) 0xFFFFFD30) // (PITC) Period Interval Mode Register -// ========== Register definition for WDTC peripheral ========== -#define AT91C_WDTC_WDCR ((AT91_REG *) 0xFFFFFD40) // (WDTC) Watchdog Control Register -#define AT91C_WDTC_WDSR ((AT91_REG *) 0xFFFFFD48) // (WDTC) Watchdog Status Register -#define AT91C_WDTC_WDMR ((AT91_REG *) 0xFFFFFD44) // (WDTC) Watchdog Mode Register -// ========== Register definition for VREG peripheral ========== -#define AT91C_VREG_MR ((AT91_REG *) 0xFFFFFD60) // (VREG) Voltage Regulator Mode Register -// ========== Register definition for MC peripheral ========== -#define AT91C_MC_ASR ((AT91_REG *) 0xFFFFFF04) // (MC) MC Abort Status Register -#define AT91C_MC_RCR ((AT91_REG *) 0xFFFFFF00) // (MC) MC Remap Control Register -#define AT91C_MC_FCR ((AT91_REG *) 0xFFFFFF64) // (MC) MC Flash Command Register -#define AT91C_MC_AASR ((AT91_REG *) 0xFFFFFF08) // (MC) MC Abort Address Status Register -#define AT91C_MC_FSR ((AT91_REG *) 0xFFFFFF68) // (MC) MC Flash Status Register -#define AT91C_MC_FMR ((AT91_REG *) 0xFFFFFF60) // (MC) MC Flash Mode Register -// ========== Register definition for PDC_SPI1 peripheral ========== -#define AT91C_SPI1_PTCR ((AT91_REG *) 0xFFFE4120) // (PDC_SPI1) PDC Transfer Control Register -#define AT91C_SPI1_RPR ((AT91_REG *) 0xFFFE4100) // (PDC_SPI1) Receive Pointer Register -#define AT91C_SPI1_TNCR ((AT91_REG *) 0xFFFE411C) // (PDC_SPI1) Transmit Next Counter Register -#define AT91C_SPI1_TPR ((AT91_REG *) 0xFFFE4108) // (PDC_SPI1) Transmit Pointer Register -#define AT91C_SPI1_TNPR ((AT91_REG *) 0xFFFE4118) // (PDC_SPI1) Transmit Next Pointer Register -#define AT91C_SPI1_TCR ((AT91_REG *) 0xFFFE410C) // (PDC_SPI1) Transmit Counter Register -#define AT91C_SPI1_RCR ((AT91_REG *) 0xFFFE4104) // (PDC_SPI1) Receive Counter Register -#define AT91C_SPI1_RNPR ((AT91_REG *) 0xFFFE4110) // (PDC_SPI1) Receive Next Pointer Register -#define AT91C_SPI1_RNCR ((AT91_REG *) 0xFFFE4114) // (PDC_SPI1) Receive Next Counter Register -#define AT91C_SPI1_PTSR ((AT91_REG *) 0xFFFE4124) // (PDC_SPI1) PDC Transfer Status Register -// ========== Register definition for SPI1 peripheral ========== -#define AT91C_SPI1_IMR ((AT91_REG *) 0xFFFE401C) // (SPI1) Interrupt Mask Register -#define AT91C_SPI1_IER ((AT91_REG *) 0xFFFE4014) // (SPI1) Interrupt Enable Register -#define AT91C_SPI1_MR ((AT91_REG *) 0xFFFE4004) // (SPI1) Mode Register -#define AT91C_SPI1_RDR ((AT91_REG *) 0xFFFE4008) // (SPI1) Receive Data Register -#define AT91C_SPI1_IDR ((AT91_REG *) 0xFFFE4018) // (SPI1) Interrupt Disable Register -#define AT91C_SPI1_SR ((AT91_REG *) 0xFFFE4010) // (SPI1) Status Register -#define AT91C_SPI1_TDR ((AT91_REG *) 0xFFFE400C) // (SPI1) Transmit Data Register -#define AT91C_SPI1_CR ((AT91_REG *) 0xFFFE4000) // (SPI1) Control Register -#define AT91C_SPI1_CSR ((AT91_REG *) 0xFFFE4030) // (SPI1) Chip Select Register -// ========== Register definition for PDC_SPI0 peripheral ========== -#define AT91C_SPI0_PTCR ((AT91_REG *) 0xFFFE0120) // (PDC_SPI0) PDC Transfer Control Register -#define AT91C_SPI0_TPR ((AT91_REG *) 0xFFFE0108) // (PDC_SPI0) Transmit Pointer Register -#define AT91C_SPI0_TCR ((AT91_REG *) 0xFFFE010C) // (PDC_SPI0) Transmit Counter Register -#define AT91C_SPI0_RCR ((AT91_REG *) 0xFFFE0104) // (PDC_SPI0) Receive Counter Register -#define AT91C_SPI0_PTSR ((AT91_REG *) 0xFFFE0124) // (PDC_SPI0) PDC Transfer Status Register -#define AT91C_SPI0_RNPR ((AT91_REG *) 0xFFFE0110) // (PDC_SPI0) Receive Next Pointer Register -#define AT91C_SPI0_RPR ((AT91_REG *) 0xFFFE0100) // (PDC_SPI0) Receive Pointer Register -#define AT91C_SPI0_TNCR ((AT91_REG *) 0xFFFE011C) // (PDC_SPI0) Transmit Next Counter Register -#define AT91C_SPI0_RNCR ((AT91_REG *) 0xFFFE0114) // (PDC_SPI0) Receive Next Counter Register -#define AT91C_SPI0_TNPR ((AT91_REG *) 0xFFFE0118) // (PDC_SPI0) Transmit Next Pointer Register -// ========== Register definition for SPI0 peripheral ========== -#define AT91C_SPI0_IER ((AT91_REG *) 0xFFFE0014) // (SPI0) Interrupt Enable Register -#define AT91C_SPI0_SR ((AT91_REG *) 0xFFFE0010) // (SPI0) Status Register -#define AT91C_SPI0_IDR ((AT91_REG *) 0xFFFE0018) // (SPI0) Interrupt Disable Register -#define AT91C_SPI0_CR ((AT91_REG *) 0xFFFE0000) // (SPI0) Control Register -#define AT91C_SPI0_MR ((AT91_REG *) 0xFFFE0004) // (SPI0) Mode Register -#define AT91C_SPI0_IMR ((AT91_REG *) 0xFFFE001C) // (SPI0) Interrupt Mask Register -#define AT91C_SPI0_TDR ((AT91_REG *) 0xFFFE000C) // (SPI0) Transmit Data Register -#define AT91C_SPI0_RDR ((AT91_REG *) 0xFFFE0008) // (SPI0) Receive Data Register -#define AT91C_SPI0_CSR ((AT91_REG *) 0xFFFE0030) // (SPI0) Chip Select Register -// ========== Register definition for PDC_US1 peripheral ========== -#define AT91C_US1_RNCR ((AT91_REG *) 0xFFFC4114) // (PDC_US1) Receive Next Counter Register -#define AT91C_US1_PTCR ((AT91_REG *) 0xFFFC4120) // (PDC_US1) PDC Transfer Control Register -#define AT91C_US1_TCR ((AT91_REG *) 0xFFFC410C) // (PDC_US1) Transmit Counter Register -#define AT91C_US1_PTSR ((AT91_REG *) 0xFFFC4124) // (PDC_US1) PDC Transfer Status Register -#define AT91C_US1_TNPR ((AT91_REG *) 0xFFFC4118) // (PDC_US1) Transmit Next Pointer Register -#define AT91C_US1_RCR ((AT91_REG *) 0xFFFC4104) // (PDC_US1) Receive Counter Register -#define AT91C_US1_RNPR ((AT91_REG *) 0xFFFC4110) // (PDC_US1) Receive Next Pointer Register -#define AT91C_US1_RPR ((AT91_REG *) 0xFFFC4100) // (PDC_US1) Receive Pointer Register -#define AT91C_US1_TNCR ((AT91_REG *) 0xFFFC411C) // (PDC_US1) Transmit Next Counter Register -#define AT91C_US1_TPR ((AT91_REG *) 0xFFFC4108) // (PDC_US1) Transmit Pointer Register -// ========== Register definition for US1 peripheral ========== -#define AT91C_US1_IF ((AT91_REG *) 0xFFFC404C) // (US1) IRDA_FILTER Register -#define AT91C_US1_NER ((AT91_REG *) 0xFFFC4044) // (US1) Nb Errors Register -#define AT91C_US1_RTOR ((AT91_REG *) 0xFFFC4024) // (US1) Receiver Time-out Register -#define AT91C_US1_CSR ((AT91_REG *) 0xFFFC4014) // (US1) Channel Status Register -#define AT91C_US1_IDR ((AT91_REG *) 0xFFFC400C) // (US1) Interrupt Disable Register -#define AT91C_US1_IER ((AT91_REG *) 0xFFFC4008) // (US1) Interrupt Enable Register -#define AT91C_US1_THR ((AT91_REG *) 0xFFFC401C) // (US1) Transmitter Holding Register -#define AT91C_US1_TTGR ((AT91_REG *) 0xFFFC4028) // (US1) Transmitter Time-guard Register -#define AT91C_US1_RHR ((AT91_REG *) 0xFFFC4018) // (US1) Receiver Holding Register -#define AT91C_US1_BRGR ((AT91_REG *) 0xFFFC4020) // (US1) Baud Rate Generator Register -#define AT91C_US1_IMR ((AT91_REG *) 0xFFFC4010) // (US1) Interrupt Mask Register -#define AT91C_US1_FIDI ((AT91_REG *) 0xFFFC4040) // (US1) FI_DI_Ratio Register -#define AT91C_US1_CR ((AT91_REG *) 0xFFFC4000) // (US1) Control Register -#define AT91C_US1_MR ((AT91_REG *) 0xFFFC4004) // (US1) Mode Register -// ========== Register definition for PDC_US0 peripheral ========== -#define AT91C_US0_TNPR ((AT91_REG *) 0xFFFC0118) // (PDC_US0) Transmit Next Pointer Register -#define AT91C_US0_RNPR ((AT91_REG *) 0xFFFC0110) // (PDC_US0) Receive Next Pointer Register -#define AT91C_US0_TCR ((AT91_REG *) 0xFFFC010C) // (PDC_US0) Transmit Counter Register -#define AT91C_US0_PTCR ((AT91_REG *) 0xFFFC0120) // (PDC_US0) PDC Transfer Control Register -#define AT91C_US0_PTSR ((AT91_REG *) 0xFFFC0124) // (PDC_US0) PDC Transfer Status Register -#define AT91C_US0_TNCR ((AT91_REG *) 0xFFFC011C) // (PDC_US0) Transmit Next Counter Register -#define AT91C_US0_TPR ((AT91_REG *) 0xFFFC0108) // (PDC_US0) Transmit Pointer Register -#define AT91C_US0_RCR ((AT91_REG *) 0xFFFC0104) // (PDC_US0) Receive Counter Register -#define AT91C_US0_RPR ((AT91_REG *) 0xFFFC0100) // (PDC_US0) Receive Pointer Register -#define AT91C_US0_RNCR ((AT91_REG *) 0xFFFC0114) // (PDC_US0) Receive Next Counter Register -// ========== Register definition for US0 peripheral ========== -#define AT91C_US0_BRGR ((AT91_REG *) 0xFFFC0020) // (US0) Baud Rate Generator Register -#define AT91C_US0_NER ((AT91_REG *) 0xFFFC0044) // (US0) Nb Errors Register -#define AT91C_US0_CR ((AT91_REG *) 0xFFFC0000) // (US0) Control Register -#define AT91C_US0_IMR ((AT91_REG *) 0xFFFC0010) // (US0) Interrupt Mask Register -#define AT91C_US0_FIDI ((AT91_REG *) 0xFFFC0040) // (US0) FI_DI_Ratio Register -#define AT91C_US0_TTGR ((AT91_REG *) 0xFFFC0028) // (US0) Transmitter Time-guard Register -#define AT91C_US0_MR ((AT91_REG *) 0xFFFC0004) // (US0) Mode Register -#define AT91C_US0_RTOR ((AT91_REG *) 0xFFFC0024) // (US0) Receiver Time-out Register -#define AT91C_US0_CSR ((AT91_REG *) 0xFFFC0014) // (US0) Channel Status Register -#define AT91C_US0_RHR ((AT91_REG *) 0xFFFC0018) // (US0) Receiver Holding Register -#define AT91C_US0_IDR ((AT91_REG *) 0xFFFC000C) // (US0) Interrupt Disable Register -#define AT91C_US0_THR ((AT91_REG *) 0xFFFC001C) // (US0) Transmitter Holding Register -#define AT91C_US0_IF ((AT91_REG *) 0xFFFC004C) // (US0) IRDA_FILTER Register -#define AT91C_US0_IER ((AT91_REG *) 0xFFFC0008) // (US0) Interrupt Enable Register -// ========== Register definition for PDC_SSC peripheral ========== -#define AT91C_SSC_TNCR ((AT91_REG *) 0xFFFD411C) // (PDC_SSC) Transmit Next Counter Register -#define AT91C_SSC_RPR ((AT91_REG *) 0xFFFD4100) // (PDC_SSC) Receive Pointer Register -#define AT91C_SSC_RNCR ((AT91_REG *) 0xFFFD4114) // (PDC_SSC) Receive Next Counter Register -#define AT91C_SSC_TPR ((AT91_REG *) 0xFFFD4108) // (PDC_SSC) Transmit Pointer Register -#define AT91C_SSC_PTCR ((AT91_REG *) 0xFFFD4120) // (PDC_SSC) PDC Transfer Control Register -#define AT91C_SSC_TCR ((AT91_REG *) 0xFFFD410C) // (PDC_SSC) Transmit Counter Register -#define AT91C_SSC_RCR ((AT91_REG *) 0xFFFD4104) // (PDC_SSC) Receive Counter Register -#define AT91C_SSC_RNPR ((AT91_REG *) 0xFFFD4110) // (PDC_SSC) Receive Next Pointer Register -#define AT91C_SSC_TNPR ((AT91_REG *) 0xFFFD4118) // (PDC_SSC) Transmit Next Pointer Register -#define AT91C_SSC_PTSR ((AT91_REG *) 0xFFFD4124) // (PDC_SSC) PDC Transfer Status Register -// ========== Register definition for SSC peripheral ========== -#define AT91C_SSC_RHR ((AT91_REG *) 0xFFFD4020) // (SSC) Receive Holding Register -#define AT91C_SSC_RSHR ((AT91_REG *) 0xFFFD4030) // (SSC) Receive Sync Holding Register -#define AT91C_SSC_TFMR ((AT91_REG *) 0xFFFD401C) // (SSC) Transmit Frame Mode Register -#define AT91C_SSC_IDR ((AT91_REG *) 0xFFFD4048) // (SSC) Interrupt Disable Register -#define AT91C_SSC_THR ((AT91_REG *) 0xFFFD4024) // (SSC) Transmit Holding Register -#define AT91C_SSC_RCMR ((AT91_REG *) 0xFFFD4010) // (SSC) Receive Clock ModeRegister -#define AT91C_SSC_IER ((AT91_REG *) 0xFFFD4044) // (SSC) Interrupt Enable Register -#define AT91C_SSC_TSHR ((AT91_REG *) 0xFFFD4034) // (SSC) Transmit Sync Holding Register -#define AT91C_SSC_SR ((AT91_REG *) 0xFFFD4040) // (SSC) Status Register -#define AT91C_SSC_CMR ((AT91_REG *) 0xFFFD4004) // (SSC) Clock Mode Register -#define AT91C_SSC_TCMR ((AT91_REG *) 0xFFFD4018) // (SSC) Transmit Clock Mode Register -#define AT91C_SSC_CR ((AT91_REG *) 0xFFFD4000) // (SSC) Control Register -#define AT91C_SSC_IMR ((AT91_REG *) 0xFFFD404C) // (SSC) Interrupt Mask Register -#define AT91C_SSC_RFMR ((AT91_REG *) 0xFFFD4014) // (SSC) Receive Frame Mode Register -// ========== Register definition for TWI peripheral ========== -#define AT91C_TWI_IER ((AT91_REG *) 0xFFFB8024) // (TWI) Interrupt Enable Register -#define AT91C_TWI_CR ((AT91_REG *) 0xFFFB8000) // (TWI) Control Register -#define AT91C_TWI_SR ((AT91_REG *) 0xFFFB8020) // (TWI) Status Register -#define AT91C_TWI_IMR ((AT91_REG *) 0xFFFB802C) // (TWI) Interrupt Mask Register -#define AT91C_TWI_THR ((AT91_REG *) 0xFFFB8034) // (TWI) Transmit Holding Register -#define AT91C_TWI_IDR ((AT91_REG *) 0xFFFB8028) // (TWI) Interrupt Disable Register -#define AT91C_TWI_IADR ((AT91_REG *) 0xFFFB800C) // (TWI) Internal Address Register -#define AT91C_TWI_MMR ((AT91_REG *) 0xFFFB8004) // (TWI) Master Mode Register -#define AT91C_TWI_CWGR ((AT91_REG *) 0xFFFB8010) // (TWI) Clock Waveform Generator Register -#define AT91C_TWI_RHR ((AT91_REG *) 0xFFFB8030) // (TWI) Receive Holding Register -// ========== Register definition for PWMC_CH3 peripheral ========== -#define AT91C_PWMC_CH3_CUPDR ((AT91_REG *) 0xFFFCC270) // (PWMC_CH3) Channel Update Register -#define AT91C_PWMC_CH3_Reserved ((AT91_REG *) 0xFFFCC274) // (PWMC_CH3) Reserved -#define AT91C_PWMC_CH3_CPRDR ((AT91_REG *) 0xFFFCC268) // (PWMC_CH3) Channel Period Register -#define AT91C_PWMC_CH3_CDTYR ((AT91_REG *) 0xFFFCC264) // (PWMC_CH3) Channel Duty Cycle Register -#define AT91C_PWMC_CH3_CCNTR ((AT91_REG *) 0xFFFCC26C) // (PWMC_CH3) Channel Counter Register -#define AT91C_PWMC_CH3_CMR ((AT91_REG *) 0xFFFCC260) // (PWMC_CH3) Channel Mode Register -// ========== Register definition for PWMC_CH2 peripheral ========== -#define AT91C_PWMC_CH2_Reserved ((AT91_REG *) 0xFFFCC254) // (PWMC_CH2) Reserved -#define AT91C_PWMC_CH2_CMR ((AT91_REG *) 0xFFFCC240) // (PWMC_CH2) Channel Mode Register -#define AT91C_PWMC_CH2_CCNTR ((AT91_REG *) 0xFFFCC24C) // (PWMC_CH2) Channel Counter Register -#define AT91C_PWMC_CH2_CPRDR ((AT91_REG *) 0xFFFCC248) // (PWMC_CH2) Channel Period Register -#define AT91C_PWMC_CH2_CUPDR ((AT91_REG *) 0xFFFCC250) // (PWMC_CH2) Channel Update Register -#define AT91C_PWMC_CH2_CDTYR ((AT91_REG *) 0xFFFCC244) // (PWMC_CH2) Channel Duty Cycle Register -// ========== Register definition for PWMC_CH1 peripheral ========== -#define AT91C_PWMC_CH1_Reserved ((AT91_REG *) 0xFFFCC234) // (PWMC_CH1) Reserved -#define AT91C_PWMC_CH1_CUPDR ((AT91_REG *) 0xFFFCC230) // (PWMC_CH1) Channel Update Register -#define AT91C_PWMC_CH1_CPRDR ((AT91_REG *) 0xFFFCC228) // (PWMC_CH1) Channel Period Register -#define AT91C_PWMC_CH1_CCNTR ((AT91_REG *) 0xFFFCC22C) // (PWMC_CH1) Channel Counter Register -#define AT91C_PWMC_CH1_CDTYR ((AT91_REG *) 0xFFFCC224) // (PWMC_CH1) Channel Duty Cycle Register -#define AT91C_PWMC_CH1_CMR ((AT91_REG *) 0xFFFCC220) // (PWMC_CH1) Channel Mode Register -// ========== Register definition for PWMC_CH0 peripheral ========== -#define AT91C_PWMC_CH0_Reserved ((AT91_REG *) 0xFFFCC214) // (PWMC_CH0) Reserved -#define AT91C_PWMC_CH0_CPRDR ((AT91_REG *) 0xFFFCC208) // (PWMC_CH0) Channel Period Register -#define AT91C_PWMC_CH0_CDTYR ((AT91_REG *) 0xFFFCC204) // (PWMC_CH0) Channel Duty Cycle Register -#define AT91C_PWMC_CH0_CMR ((AT91_REG *) 0xFFFCC200) // (PWMC_CH0) Channel Mode Register -#define AT91C_PWMC_CH0_CUPDR ((AT91_REG *) 0xFFFCC210) // (PWMC_CH0) Channel Update Register -#define AT91C_PWMC_CH0_CCNTR ((AT91_REG *) 0xFFFCC20C) // (PWMC_CH0) Channel Counter Register -// ========== Register definition for PWMC peripheral ========== -#define AT91C_PWMC_IDR ((AT91_REG *) 0xFFFCC014) // (PWMC) PWMC Interrupt Disable Register -#define AT91C_PWMC_DIS ((AT91_REG *) 0xFFFCC008) // (PWMC) PWMC Disable Register -#define AT91C_PWMC_IER ((AT91_REG *) 0xFFFCC010) // (PWMC) PWMC Interrupt Enable Register -#define AT91C_PWMC_VR ((AT91_REG *) 0xFFFCC0FC) // (PWMC) PWMC Version Register -#define AT91C_PWMC_ISR ((AT91_REG *) 0xFFFCC01C) // (PWMC) PWMC Interrupt Status Register -#define AT91C_PWMC_SR ((AT91_REG *) 0xFFFCC00C) // (PWMC) PWMC Status Register -#define AT91C_PWMC_IMR ((AT91_REG *) 0xFFFCC018) // (PWMC) PWMC Interrupt Mask Register -#define AT91C_PWMC_MR ((AT91_REG *) 0xFFFCC000) // (PWMC) PWMC Mode Register -#define AT91C_PWMC_ENA ((AT91_REG *) 0xFFFCC004) // (PWMC) PWMC Enable Register -// ========== Register definition for UDP peripheral ========== -#define AT91C_UDP_IMR ((AT91_REG *) 0xFFFB0018) // (UDP) Interrupt Mask Register -#define AT91C_UDP_FADDR ((AT91_REG *) 0xFFFB0008) // (UDP) Function Address Register -#define AT91C_UDP_NUM ((AT91_REG *) 0xFFFB0000) // (UDP) Frame Number Register -#define AT91C_UDP_FDR ((AT91_REG *) 0xFFFB0050) // (UDP) Endpoint FIFO Data Register -#define AT91C_UDP_ISR ((AT91_REG *) 0xFFFB001C) // (UDP) Interrupt Status Register -#define AT91C_UDP_CSR ((AT91_REG *) 0xFFFB0030) // (UDP) Endpoint Control and Status Register -#define AT91C_UDP_IDR ((AT91_REG *) 0xFFFB0014) // (UDP) Interrupt Disable Register -#define AT91C_UDP_ICR ((AT91_REG *) 0xFFFB0020) // (UDP) Interrupt Clear Register -#define AT91C_UDP_RSTEP ((AT91_REG *) 0xFFFB0028) // (UDP) Reset Endpoint Register -#define AT91C_UDP_TXVC ((AT91_REG *) 0xFFFB0074) // (UDP) Transceiver Control Register -#define AT91C_UDP_GLBSTATE ((AT91_REG *) 0xFFFB0004) // (UDP) Global State Register -#define AT91C_UDP_IER ((AT91_REG *) 0xFFFB0010) // (UDP) Interrupt Enable Register -// ========== Register definition for TC0 peripheral ========== -#define AT91C_TC0_SR ((AT91_REG *) 0xFFFA0020) // (TC0) Status Register -#define AT91C_TC0_RC ((AT91_REG *) 0xFFFA001C) // (TC0) Register C -#define AT91C_TC0_RB ((AT91_REG *) 0xFFFA0018) // (TC0) Register B -#define AT91C_TC0_CCR ((AT91_REG *) 0xFFFA0000) // (TC0) Channel Control Register -#define AT91C_TC0_CMR ((AT91_REG *) 0xFFFA0004) // (TC0) Channel Mode Register (Capture Mode / Waveform Mode) -#define AT91C_TC0_IER ((AT91_REG *) 0xFFFA0024) // (TC0) Interrupt Enable Register -#define AT91C_TC0_RA ((AT91_REG *) 0xFFFA0014) // (TC0) Register A -#define AT91C_TC0_IDR ((AT91_REG *) 0xFFFA0028) // (TC0) Interrupt Disable Register -#define AT91C_TC0_CV ((AT91_REG *) 0xFFFA0010) // (TC0) Counter Value -#define AT91C_TC0_IMR ((AT91_REG *) 0xFFFA002C) // (TC0) Interrupt Mask Register -// ========== Register definition for TC1 peripheral ========== -#define AT91C_TC1_RB ((AT91_REG *) 0xFFFA0058) // (TC1) Register B -#define AT91C_TC1_CCR ((AT91_REG *) 0xFFFA0040) // (TC1) Channel Control Register -#define AT91C_TC1_IER ((AT91_REG *) 0xFFFA0064) // (TC1) Interrupt Enable Register -#define AT91C_TC1_IDR ((AT91_REG *) 0xFFFA0068) // (TC1) Interrupt Disable Register -#define AT91C_TC1_SR ((AT91_REG *) 0xFFFA0060) // (TC1) Status Register -#define AT91C_TC1_CMR ((AT91_REG *) 0xFFFA0044) // (TC1) Channel Mode Register (Capture Mode / Waveform Mode) -#define AT91C_TC1_RA ((AT91_REG *) 0xFFFA0054) // (TC1) Register A -#define AT91C_TC1_RC ((AT91_REG *) 0xFFFA005C) // (TC1) Register C -#define AT91C_TC1_IMR ((AT91_REG *) 0xFFFA006C) // (TC1) Interrupt Mask Register -#define AT91C_TC1_CV ((AT91_REG *) 0xFFFA0050) // (TC1) Counter Value -// ========== Register definition for TC2 peripheral ========== -#define AT91C_TC2_CMR ((AT91_REG *) 0xFFFA0084) // (TC2) Channel Mode Register (Capture Mode / Waveform Mode) -#define AT91C_TC2_CCR ((AT91_REG *) 0xFFFA0080) // (TC2) Channel Control Register -#define AT91C_TC2_CV ((AT91_REG *) 0xFFFA0090) // (TC2) Counter Value -#define AT91C_TC2_RA ((AT91_REG *) 0xFFFA0094) // (TC2) Register A -#define AT91C_TC2_RB ((AT91_REG *) 0xFFFA0098) // (TC2) Register B -#define AT91C_TC2_IDR ((AT91_REG *) 0xFFFA00A8) // (TC2) Interrupt Disable Register -#define AT91C_TC2_IMR ((AT91_REG *) 0xFFFA00AC) // (TC2) Interrupt Mask Register -#define AT91C_TC2_RC ((AT91_REG *) 0xFFFA009C) // (TC2) Register C -#define AT91C_TC2_IER ((AT91_REG *) 0xFFFA00A4) // (TC2) Interrupt Enable Register -#define AT91C_TC2_SR ((AT91_REG *) 0xFFFA00A0) // (TC2) Status Register -// ========== Register definition for TCB peripheral ========== -#define AT91C_TCB_BMR ((AT91_REG *) 0xFFFA00C4) // (TCB) TC Block Mode Register -#define AT91C_TCB_BCR ((AT91_REG *) 0xFFFA00C0) // (TCB) TC Block Control Register -// ========== Register definition for CAN_MB0 peripheral ========== -#define AT91C_CAN_MB0_MDL ((AT91_REG *) 0xFFFD0214) // (CAN_MB0) MailBox Data Low Register -#define AT91C_CAN_MB0_MAM ((AT91_REG *) 0xFFFD0204) // (CAN_MB0) MailBox Acceptance Mask Register -#define AT91C_CAN_MB0_MCR ((AT91_REG *) 0xFFFD021C) // (CAN_MB0) MailBox Control Register -#define AT91C_CAN_MB0_MID ((AT91_REG *) 0xFFFD0208) // (CAN_MB0) MailBox ID Register -#define AT91C_CAN_MB0_MSR ((AT91_REG *) 0xFFFD0210) // (CAN_MB0) MailBox Status Register -#define AT91C_CAN_MB0_MFID ((AT91_REG *) 0xFFFD020C) // (CAN_MB0) MailBox Family ID Register -#define AT91C_CAN_MB0_MDH ((AT91_REG *) 0xFFFD0218) // (CAN_MB0) MailBox Data High Register -#define AT91C_CAN_MB0_MMR ((AT91_REG *) 0xFFFD0200) // (CAN_MB0) MailBox Mode Register -// ========== Register definition for CAN_MB1 peripheral ========== -#define AT91C_CAN_MB1_MDL ((AT91_REG *) 0xFFFD0234) // (CAN_MB1) MailBox Data Low Register -#define AT91C_CAN_MB1_MID ((AT91_REG *) 0xFFFD0228) // (CAN_MB1) MailBox ID Register -#define AT91C_CAN_MB1_MMR ((AT91_REG *) 0xFFFD0220) // (CAN_MB1) MailBox Mode Register -#define AT91C_CAN_MB1_MSR ((AT91_REG *) 0xFFFD0230) // (CAN_MB1) MailBox Status Register -#define AT91C_CAN_MB1_MAM ((AT91_REG *) 0xFFFD0224) // (CAN_MB1) MailBox Acceptance Mask Register -#define AT91C_CAN_MB1_MDH ((AT91_REG *) 0xFFFD0238) // (CAN_MB1) MailBox Data High Register -#define AT91C_CAN_MB1_MCR ((AT91_REG *) 0xFFFD023C) // (CAN_MB1) MailBox Control Register -#define AT91C_CAN_MB1_MFID ((AT91_REG *) 0xFFFD022C) // (CAN_MB1) MailBox Family ID Register -// ========== Register definition for CAN_MB2 peripheral ========== -#define AT91C_CAN_MB2_MCR ((AT91_REG *) 0xFFFD025C) // (CAN_MB2) MailBox Control Register -#define AT91C_CAN_MB2_MDH ((AT91_REG *) 0xFFFD0258) // (CAN_MB2) MailBox Data High Register -#define AT91C_CAN_MB2_MID ((AT91_REG *) 0xFFFD0248) // (CAN_MB2) MailBox ID Register -#define AT91C_CAN_MB2_MDL ((AT91_REG *) 0xFFFD0254) // (CAN_MB2) MailBox Data Low Register -#define AT91C_CAN_MB2_MMR ((AT91_REG *) 0xFFFD0240) // (CAN_MB2) MailBox Mode Register -#define AT91C_CAN_MB2_MAM ((AT91_REG *) 0xFFFD0244) // (CAN_MB2) MailBox Acceptance Mask Register -#define AT91C_CAN_MB2_MFID ((AT91_REG *) 0xFFFD024C) // (CAN_MB2) MailBox Family ID Register -#define AT91C_CAN_MB2_MSR ((AT91_REG *) 0xFFFD0250) // (CAN_MB2) MailBox Status Register -// ========== Register definition for CAN_MB3 peripheral ========== -#define AT91C_CAN_MB3_MFID ((AT91_REG *) 0xFFFD026C) // (CAN_MB3) MailBox Family ID Register -#define AT91C_CAN_MB3_MAM ((AT91_REG *) 0xFFFD0264) // (CAN_MB3) MailBox Acceptance Mask Register -#define AT91C_CAN_MB3_MID ((AT91_REG *) 0xFFFD0268) // (CAN_MB3) MailBox ID Register -#define AT91C_CAN_MB3_MCR ((AT91_REG *) 0xFFFD027C) // (CAN_MB3) MailBox Control Register -#define AT91C_CAN_MB3_MMR ((AT91_REG *) 0xFFFD0260) // (CAN_MB3) MailBox Mode Register -#define AT91C_CAN_MB3_MSR ((AT91_REG *) 0xFFFD0270) // (CAN_MB3) MailBox Status Register -#define AT91C_CAN_MB3_MDL ((AT91_REG *) 0xFFFD0274) // (CAN_MB3) MailBox Data Low Register -#define AT91C_CAN_MB3_MDH ((AT91_REG *) 0xFFFD0278) // (CAN_MB3) MailBox Data High Register -// ========== Register definition for CAN_MB4 peripheral ========== -#define AT91C_CAN_MB4_MID ((AT91_REG *) 0xFFFD0288) // (CAN_MB4) MailBox ID Register -#define AT91C_CAN_MB4_MMR ((AT91_REG *) 0xFFFD0280) // (CAN_MB4) MailBox Mode Register -#define AT91C_CAN_MB4_MDH ((AT91_REG *) 0xFFFD0298) // (CAN_MB4) MailBox Data High Register -#define AT91C_CAN_MB4_MFID ((AT91_REG *) 0xFFFD028C) // (CAN_MB4) MailBox Family ID Register -#define AT91C_CAN_MB4_MSR ((AT91_REG *) 0xFFFD0290) // (CAN_MB4) MailBox Status Register -#define AT91C_CAN_MB4_MCR ((AT91_REG *) 0xFFFD029C) // (CAN_MB4) MailBox Control Register -#define AT91C_CAN_MB4_MDL ((AT91_REG *) 0xFFFD0294) // (CAN_MB4) MailBox Data Low Register -#define AT91C_CAN_MB4_MAM ((AT91_REG *) 0xFFFD0284) // (CAN_MB4) MailBox Acceptance Mask Register -// ========== Register definition for CAN_MB5 peripheral ========== -#define AT91C_CAN_MB5_MSR ((AT91_REG *) 0xFFFD02B0) // (CAN_MB5) MailBox Status Register -#define AT91C_CAN_MB5_MCR ((AT91_REG *) 0xFFFD02BC) // (CAN_MB5) MailBox Control Register -#define AT91C_CAN_MB5_MFID ((AT91_REG *) 0xFFFD02AC) // (CAN_MB5) MailBox Family ID Register -#define AT91C_CAN_MB5_MDH ((AT91_REG *) 0xFFFD02B8) // (CAN_MB5) MailBox Data High Register -#define AT91C_CAN_MB5_MID ((AT91_REG *) 0xFFFD02A8) // (CAN_MB5) MailBox ID Register -#define AT91C_CAN_MB5_MMR ((AT91_REG *) 0xFFFD02A0) // (CAN_MB5) MailBox Mode Register -#define AT91C_CAN_MB5_MDL ((AT91_REG *) 0xFFFD02B4) // (CAN_MB5) MailBox Data Low Register -#define AT91C_CAN_MB5_MAM ((AT91_REG *) 0xFFFD02A4) // (CAN_MB5) MailBox Acceptance Mask Register -// ========== Register definition for CAN_MB6 peripheral ========== -#define AT91C_CAN_MB6_MFID ((AT91_REG *) 0xFFFD02CC) // (CAN_MB6) MailBox Family ID Register -#define AT91C_CAN_MB6_MID ((AT91_REG *) 0xFFFD02C8) // (CAN_MB6) MailBox ID Register -#define AT91C_CAN_MB6_MAM ((AT91_REG *) 0xFFFD02C4) // (CAN_MB6) MailBox Acceptance Mask Register -#define AT91C_CAN_MB6_MSR ((AT91_REG *) 0xFFFD02D0) // (CAN_MB6) MailBox Status Register -#define AT91C_CAN_MB6_MDL ((AT91_REG *) 0xFFFD02D4) // (CAN_MB6) MailBox Data Low Register -#define AT91C_CAN_MB6_MCR ((AT91_REG *) 0xFFFD02DC) // (CAN_MB6) MailBox Control Register -#define AT91C_CAN_MB6_MDH ((AT91_REG *) 0xFFFD02D8) // (CAN_MB6) MailBox Data High Register -#define AT91C_CAN_MB6_MMR ((AT91_REG *) 0xFFFD02C0) // (CAN_MB6) MailBox Mode Register -// ========== Register definition for CAN_MB7 peripheral ========== -#define AT91C_CAN_MB7_MCR ((AT91_REG *) 0xFFFD02FC) // (CAN_MB7) MailBox Control Register -#define AT91C_CAN_MB7_MDH ((AT91_REG *) 0xFFFD02F8) // (CAN_MB7) MailBox Data High Register -#define AT91C_CAN_MB7_MFID ((AT91_REG *) 0xFFFD02EC) // (CAN_MB7) MailBox Family ID Register -#define AT91C_CAN_MB7_MDL ((AT91_REG *) 0xFFFD02F4) // (CAN_MB7) MailBox Data Low Register -#define AT91C_CAN_MB7_MID ((AT91_REG *) 0xFFFD02E8) // (CAN_MB7) MailBox ID Register -#define AT91C_CAN_MB7_MMR ((AT91_REG *) 0xFFFD02E0) // (CAN_MB7) MailBox Mode Register -#define AT91C_CAN_MB7_MAM ((AT91_REG *) 0xFFFD02E4) // (CAN_MB7) MailBox Acceptance Mask Register -#define AT91C_CAN_MB7_MSR ((AT91_REG *) 0xFFFD02F0) // (CAN_MB7) MailBox Status Register -// ========== Register definition for CAN peripheral ========== -#define AT91C_CAN_TCR ((AT91_REG *) 0xFFFD0024) // (CAN) Transfer Command Register -#define AT91C_CAN_IMR ((AT91_REG *) 0xFFFD000C) // (CAN) Interrupt Mask Register -#define AT91C_CAN_IER ((AT91_REG *) 0xFFFD0004) // (CAN) Interrupt Enable Register -#define AT91C_CAN_ECR ((AT91_REG *) 0xFFFD0020) // (CAN) Error Counter Register -#define AT91C_CAN_TIMESTP ((AT91_REG *) 0xFFFD001C) // (CAN) Time Stamp Register -#define AT91C_CAN_MR ((AT91_REG *) 0xFFFD0000) // (CAN) Mode Register -#define AT91C_CAN_IDR ((AT91_REG *) 0xFFFD0008) // (CAN) Interrupt Disable Register -#define AT91C_CAN_ACR ((AT91_REG *) 0xFFFD0028) // (CAN) Abort Command Register -#define AT91C_CAN_TIM ((AT91_REG *) 0xFFFD0018) // (CAN) Timer Register -#define AT91C_CAN_SR ((AT91_REG *) 0xFFFD0010) // (CAN) Status Register -#define AT91C_CAN_BR ((AT91_REG *) 0xFFFD0014) // (CAN) Baudrate Register -#define AT91C_CAN_VR ((AT91_REG *) 0xFFFD00FC) // (CAN) Version Register -// ========== Register definition for EMAC peripheral ========== -#define AT91C_EMAC_ISR ((AT91_REG *) 0xFFFDC024) // (EMAC) Interrupt Status Register -#define AT91C_EMAC_SA4H ((AT91_REG *) 0xFFFDC0B4) // (EMAC) Specific Address 4 Top, Last 2 bytes -#define AT91C_EMAC_SA1L ((AT91_REG *) 0xFFFDC098) // (EMAC) Specific Address 1 Bottom, First 4 bytes -#define AT91C_EMAC_ELE ((AT91_REG *) 0xFFFDC078) // (EMAC) Excessive Length Errors Register -#define AT91C_EMAC_LCOL ((AT91_REG *) 0xFFFDC05C) // (EMAC) Late Collision Register -#define AT91C_EMAC_RLE ((AT91_REG *) 0xFFFDC088) // (EMAC) Receive Length Field Mismatch Register -#define AT91C_EMAC_WOL ((AT91_REG *) 0xFFFDC0C4) // (EMAC) Wake On LAN Register -#define AT91C_EMAC_DTF ((AT91_REG *) 0xFFFDC058) // (EMAC) Deferred Transmission Frame Register -#define AT91C_EMAC_TUND ((AT91_REG *) 0xFFFDC064) // (EMAC) Transmit Underrun Error Register -#define AT91C_EMAC_NCR ((AT91_REG *) 0xFFFDC000) // (EMAC) Network Control Register -#define AT91C_EMAC_SA4L ((AT91_REG *) 0xFFFDC0B0) // (EMAC) Specific Address 4 Bottom, First 4 bytes -#define AT91C_EMAC_RSR ((AT91_REG *) 0xFFFDC020) // (EMAC) Receive Status Register -#define AT91C_EMAC_SA3L ((AT91_REG *) 0xFFFDC0A8) // (EMAC) Specific Address 3 Bottom, First 4 bytes -#define AT91C_EMAC_TSR ((AT91_REG *) 0xFFFDC014) // (EMAC) Transmit Status Register -#define AT91C_EMAC_IDR ((AT91_REG *) 0xFFFDC02C) // (EMAC) Interrupt Disable Register -#define AT91C_EMAC_RSE ((AT91_REG *) 0xFFFDC074) // (EMAC) Receive Symbol Errors Register -#define AT91C_EMAC_ECOL ((AT91_REG *) 0xFFFDC060) // (EMAC) Excessive Collision Register -#define AT91C_EMAC_TID ((AT91_REG *) 0xFFFDC0B8) // (EMAC) Type ID Checking Register -#define AT91C_EMAC_HRB ((AT91_REG *) 0xFFFDC090) // (EMAC) Hash Address Bottom[31:0] -#define AT91C_EMAC_TBQP ((AT91_REG *) 0xFFFDC01C) // (EMAC) Transmit Buffer Queue Pointer -#define AT91C_EMAC_USRIO ((AT91_REG *) 0xFFFDC0C0) // (EMAC) USER Input/Output Register -#define AT91C_EMAC_PTR ((AT91_REG *) 0xFFFDC038) // (EMAC) Pause Time Register -#define AT91C_EMAC_SA2H ((AT91_REG *) 0xFFFDC0A4) // (EMAC) Specific Address 2 Top, Last 2 bytes -#define AT91C_EMAC_ROV ((AT91_REG *) 0xFFFDC070) // (EMAC) Receive Overrun Errors Register -#define AT91C_EMAC_ALE ((AT91_REG *) 0xFFFDC054) // (EMAC) Alignment Error Register -#define AT91C_EMAC_RJA ((AT91_REG *) 0xFFFDC07C) // (EMAC) Receive Jabbers Register -#define AT91C_EMAC_RBQP ((AT91_REG *) 0xFFFDC018) // (EMAC) Receive Buffer Queue Pointer -#define AT91C_EMAC_TPF ((AT91_REG *) 0xFFFDC08C) // (EMAC) Transmitted Pause Frames Register -#define AT91C_EMAC_NCFGR ((AT91_REG *) 0xFFFDC004) // (EMAC) Network Configuration Register -#define AT91C_EMAC_HRT ((AT91_REG *) 0xFFFDC094) // (EMAC) Hash Address Top[63:32] -#define AT91C_EMAC_USF ((AT91_REG *) 0xFFFDC080) // (EMAC) Undersize Frames Register -#define AT91C_EMAC_FCSE ((AT91_REG *) 0xFFFDC050) // (EMAC) Frame Check Sequence Error Register -#define AT91C_EMAC_TPQ ((AT91_REG *) 0xFFFDC0BC) // (EMAC) Transmit Pause Quantum Register -#define AT91C_EMAC_MAN ((AT91_REG *) 0xFFFDC034) // (EMAC) PHY Maintenance Register -#define AT91C_EMAC_FTO ((AT91_REG *) 0xFFFDC040) // (EMAC) Frames Transmitted OK Register -#define AT91C_EMAC_REV ((AT91_REG *) 0xFFFDC0FC) // (EMAC) Revision Register -#define AT91C_EMAC_IMR ((AT91_REG *) 0xFFFDC030) // (EMAC) Interrupt Mask Register -#define AT91C_EMAC_SCF ((AT91_REG *) 0xFFFDC044) // (EMAC) Single Collision Frame Register -#define AT91C_EMAC_PFR ((AT91_REG *) 0xFFFDC03C) // (EMAC) Pause Frames received Register -#define AT91C_EMAC_MCF ((AT91_REG *) 0xFFFDC048) // (EMAC) Multiple Collision Frame Register -#define AT91C_EMAC_NSR ((AT91_REG *) 0xFFFDC008) // (EMAC) Network Status Register -#define AT91C_EMAC_SA2L ((AT91_REG *) 0xFFFDC0A0) // (EMAC) Specific Address 2 Bottom, First 4 bytes -#define AT91C_EMAC_FRO ((AT91_REG *) 0xFFFDC04C) // (EMAC) Frames Received OK Register -#define AT91C_EMAC_IER ((AT91_REG *) 0xFFFDC028) // (EMAC) Interrupt Enable Register -#define AT91C_EMAC_SA1H ((AT91_REG *) 0xFFFDC09C) // (EMAC) Specific Address 1 Top, Last 2 bytes -#define AT91C_EMAC_CSE ((AT91_REG *) 0xFFFDC068) // (EMAC) Carrier Sense Error Register -#define AT91C_EMAC_SA3H ((AT91_REG *) 0xFFFDC0AC) // (EMAC) Specific Address 3 Top, Last 2 bytes -#define AT91C_EMAC_RRE ((AT91_REG *) 0xFFFDC06C) // (EMAC) Receive Ressource Error Register -#define AT91C_EMAC_STE ((AT91_REG *) 0xFFFDC084) // (EMAC) SQE Test Error Register -// ========== Register definition for PDC_ADC peripheral ========== -#define AT91C_ADC_PTSR ((AT91_REG *) 0xFFFD8124) // (PDC_ADC) PDC Transfer Status Register -#define AT91C_ADC_PTCR ((AT91_REG *) 0xFFFD8120) // (PDC_ADC) PDC Transfer Control Register -#define AT91C_ADC_TNPR ((AT91_REG *) 0xFFFD8118) // (PDC_ADC) Transmit Next Pointer Register -#define AT91C_ADC_TNCR ((AT91_REG *) 0xFFFD811C) // (PDC_ADC) Transmit Next Counter Register -#define AT91C_ADC_RNPR ((AT91_REG *) 0xFFFD8110) // (PDC_ADC) Receive Next Pointer Register -#define AT91C_ADC_RNCR ((AT91_REG *) 0xFFFD8114) // (PDC_ADC) Receive Next Counter Register -#define AT91C_ADC_RPR ((AT91_REG *) 0xFFFD8100) // (PDC_ADC) Receive Pointer Register -#define AT91C_ADC_TCR ((AT91_REG *) 0xFFFD810C) // (PDC_ADC) Transmit Counter Register -#define AT91C_ADC_TPR ((AT91_REG *) 0xFFFD8108) // (PDC_ADC) Transmit Pointer Register -#define AT91C_ADC_RCR ((AT91_REG *) 0xFFFD8104) // (PDC_ADC) Receive Counter Register -// ========== Register definition for ADC peripheral ========== -#define AT91C_ADC_CDR2 ((AT91_REG *) 0xFFFD8038) // (ADC) ADC Channel Data Register 2 -#define AT91C_ADC_CDR3 ((AT91_REG *) 0xFFFD803C) // (ADC) ADC Channel Data Register 3 -#define AT91C_ADC_CDR0 ((AT91_REG *) 0xFFFD8030) // (ADC) ADC Channel Data Register 0 -#define AT91C_ADC_CDR5 ((AT91_REG *) 0xFFFD8044) // (ADC) ADC Channel Data Register 5 -#define AT91C_ADC_CHDR ((AT91_REG *) 0xFFFD8014) // (ADC) ADC Channel Disable Register -#define AT91C_ADC_SR ((AT91_REG *) 0xFFFD801C) // (ADC) ADC Status Register -#define AT91C_ADC_CDR4 ((AT91_REG *) 0xFFFD8040) // (ADC) ADC Channel Data Register 4 -#define AT91C_ADC_CDR1 ((AT91_REG *) 0xFFFD8034) // (ADC) ADC Channel Data Register 1 -#define AT91C_ADC_LCDR ((AT91_REG *) 0xFFFD8020) // (ADC) ADC Last Converted Data Register -#define AT91C_ADC_IDR ((AT91_REG *) 0xFFFD8028) // (ADC) ADC Interrupt Disable Register -#define AT91C_ADC_CR ((AT91_REG *) 0xFFFD8000) // (ADC) ADC Control Register -#define AT91C_ADC_CDR7 ((AT91_REG *) 0xFFFD804C) // (ADC) ADC Channel Data Register 7 -#define AT91C_ADC_CDR6 ((AT91_REG *) 0xFFFD8048) // (ADC) ADC Channel Data Register 6 -#define AT91C_ADC_IER ((AT91_REG *) 0xFFFD8024) // (ADC) ADC Interrupt Enable Register -#define AT91C_ADC_CHER ((AT91_REG *) 0xFFFD8010) // (ADC) ADC Channel Enable Register -#define AT91C_ADC_CHSR ((AT91_REG *) 0xFFFD8018) // (ADC) ADC Channel Status Register -#define AT91C_ADC_MR ((AT91_REG *) 0xFFFD8004) // (ADC) ADC Mode Register -#define AT91C_ADC_IMR ((AT91_REG *) 0xFFFD802C) // (ADC) ADC Interrupt Mask Register -// ========== Register definition for PDC_AES peripheral ========== -#define AT91C_AES_TPR ((AT91_REG *) 0xFFFA4108) // (PDC_AES) Transmit Pointer Register -#define AT91C_AES_PTCR ((AT91_REG *) 0xFFFA4120) // (PDC_AES) PDC Transfer Control Register -#define AT91C_AES_RNPR ((AT91_REG *) 0xFFFA4110) // (PDC_AES) Receive Next Pointer Register -#define AT91C_AES_TNCR ((AT91_REG *) 0xFFFA411C) // (PDC_AES) Transmit Next Counter Register -#define AT91C_AES_TCR ((AT91_REG *) 0xFFFA410C) // (PDC_AES) Transmit Counter Register -#define AT91C_AES_RCR ((AT91_REG *) 0xFFFA4104) // (PDC_AES) Receive Counter Register -#define AT91C_AES_RNCR ((AT91_REG *) 0xFFFA4114) // (PDC_AES) Receive Next Counter Register -#define AT91C_AES_TNPR ((AT91_REG *) 0xFFFA4118) // (PDC_AES) Transmit Next Pointer Register -#define AT91C_AES_RPR ((AT91_REG *) 0xFFFA4100) // (PDC_AES) Receive Pointer Register -#define AT91C_AES_PTSR ((AT91_REG *) 0xFFFA4124) // (PDC_AES) PDC Transfer Status Register -// ========== Register definition for AES peripheral ========== -#define AT91C_AES_IVxR ((AT91_REG *) 0xFFFA4060) // (AES) Initialization Vector x Register -#define AT91C_AES_MR ((AT91_REG *) 0xFFFA4004) // (AES) Mode Register -#define AT91C_AES_VR ((AT91_REG *) 0xFFFA40FC) // (AES) AES Version Register -#define AT91C_AES_ODATAxR ((AT91_REG *) 0xFFFA4050) // (AES) Output Data x Register -#define AT91C_AES_IDATAxR ((AT91_REG *) 0xFFFA4040) // (AES) Input Data x Register -#define AT91C_AES_CR ((AT91_REG *) 0xFFFA4000) // (AES) Control Register -#define AT91C_AES_IDR ((AT91_REG *) 0xFFFA4014) // (AES) Interrupt Disable Register -#define AT91C_AES_IMR ((AT91_REG *) 0xFFFA4018) // (AES) Interrupt Mask Register -#define AT91C_AES_IER ((AT91_REG *) 0xFFFA4010) // (AES) Interrupt Enable Register -#define AT91C_AES_KEYWxR ((AT91_REG *) 0xFFFA4020) // (AES) Key Word x Register -#define AT91C_AES_ISR ((AT91_REG *) 0xFFFA401C) // (AES) Interrupt Status Register -// ========== Register definition for PDC_TDES peripheral ========== -#define AT91C_TDES_RNCR ((AT91_REG *) 0xFFFA8114) // (PDC_TDES) Receive Next Counter Register -#define AT91C_TDES_TCR ((AT91_REG *) 0xFFFA810C) // (PDC_TDES) Transmit Counter Register -#define AT91C_TDES_RCR ((AT91_REG *) 0xFFFA8104) // (PDC_TDES) Receive Counter Register -#define AT91C_TDES_TNPR ((AT91_REG *) 0xFFFA8118) // (PDC_TDES) Transmit Next Pointer Register -#define AT91C_TDES_RNPR ((AT91_REG *) 0xFFFA8110) // (PDC_TDES) Receive Next Pointer Register -#define AT91C_TDES_RPR ((AT91_REG *) 0xFFFA8100) // (PDC_TDES) Receive Pointer Register -#define AT91C_TDES_TNCR ((AT91_REG *) 0xFFFA811C) // (PDC_TDES) Transmit Next Counter Register -#define AT91C_TDES_TPR ((AT91_REG *) 0xFFFA8108) // (PDC_TDES) Transmit Pointer Register -#define AT91C_TDES_PTSR ((AT91_REG *) 0xFFFA8124) // (PDC_TDES) PDC Transfer Status Register -#define AT91C_TDES_PTCR ((AT91_REG *) 0xFFFA8120) // (PDC_TDES) PDC Transfer Control Register -// ========== Register definition for TDES peripheral ========== -#define AT91C_TDES_KEY2WxR ((AT91_REG *) 0xFFFA8028) // (TDES) Key 2 Word x Register -#define AT91C_TDES_KEY3WxR ((AT91_REG *) 0xFFFA8030) // (TDES) Key 3 Word x Register -#define AT91C_TDES_IDR ((AT91_REG *) 0xFFFA8014) // (TDES) Interrupt Disable Register -#define AT91C_TDES_VR ((AT91_REG *) 0xFFFA80FC) // (TDES) TDES Version Register -#define AT91C_TDES_IVxR ((AT91_REG *) 0xFFFA8060) // (TDES) Initialization Vector x Register -#define AT91C_TDES_ODATAxR ((AT91_REG *) 0xFFFA8050) // (TDES) Output Data x Register -#define AT91C_TDES_IMR ((AT91_REG *) 0xFFFA8018) // (TDES) Interrupt Mask Register -#define AT91C_TDES_MR ((AT91_REG *) 0xFFFA8004) // (TDES) Mode Register -#define AT91C_TDES_CR ((AT91_REG *) 0xFFFA8000) // (TDES) Control Register -#define AT91C_TDES_IER ((AT91_REG *) 0xFFFA8010) // (TDES) Interrupt Enable Register -#define AT91C_TDES_ISR ((AT91_REG *) 0xFFFA801C) // (TDES) Interrupt Status Register -#define AT91C_TDES_IDATAxR ((AT91_REG *) 0xFFFA8040) // (TDES) Input Data x Register -#define AT91C_TDES_KEY1WxR ((AT91_REG *) 0xFFFA8020) // (TDES) Key 1 Word x Register +/* ***************************************************************************** */ +/* REGISTER ADDRESS DEFINITION FOR AT91SAM7X256 */ +/* ***************************************************************************** */ +/* ========== Register definition for SYS peripheral ========== */ +/* ========== Register definition for AIC peripheral ========== */ +#define AT91C_AIC_IVR ( ( AT91_REG * ) 0xFFFFF100 ) /* (AIC) IRQ Vector Register */ +#define AT91C_AIC_SMR ( ( AT91_REG * ) 0xFFFFF000 ) /* (AIC) Source Mode Register */ +#define AT91C_AIC_FVR ( ( AT91_REG * ) 0xFFFFF104 ) /* (AIC) FIQ Vector Register */ +#define AT91C_AIC_DCR ( ( AT91_REG * ) 0xFFFFF138 ) /* (AIC) Debug Control Register (Protect) */ +#define AT91C_AIC_EOICR ( ( AT91_REG * ) 0xFFFFF130 ) /* (AIC) End of Interrupt Command Register */ +#define AT91C_AIC_SVR ( ( AT91_REG * ) 0xFFFFF080 ) /* (AIC) Source Vector Register */ +#define AT91C_AIC_FFSR ( ( AT91_REG * ) 0xFFFFF148 ) /* (AIC) Fast Forcing Status Register */ +#define AT91C_AIC_ICCR ( ( AT91_REG * ) 0xFFFFF128 ) /* (AIC) Interrupt Clear Command Register */ +#define AT91C_AIC_ISR ( ( AT91_REG * ) 0xFFFFF108 ) /* (AIC) Interrupt Status Register */ +#define AT91C_AIC_IMR ( ( AT91_REG * ) 0xFFFFF110 ) /* (AIC) Interrupt Mask Register */ +#define AT91C_AIC_IPR ( ( AT91_REG * ) 0xFFFFF10C ) /* (AIC) Interrupt Pending Register */ +#define AT91C_AIC_FFER ( ( AT91_REG * ) 0xFFFFF140 ) /* (AIC) Fast Forcing Enable Register */ +#define AT91C_AIC_IECR ( ( AT91_REG * ) 0xFFFFF120 ) /* (AIC) Interrupt Enable Command Register */ +#define AT91C_AIC_ISCR ( ( AT91_REG * ) 0xFFFFF12C ) /* (AIC) Interrupt Set Command Register */ +#define AT91C_AIC_FFDR ( ( AT91_REG * ) 0xFFFFF144 ) /* (AIC) Fast Forcing Disable Register */ +#define AT91C_AIC_CISR ( ( AT91_REG * ) 0xFFFFF114 ) /* (AIC) Core Interrupt Status Register */ +#define AT91C_AIC_IDCR ( ( AT91_REG * ) 0xFFFFF124 ) /* (AIC) Interrupt Disable Command Register */ +#define AT91C_AIC_SPU ( ( AT91_REG * ) 0xFFFFF134 ) /* (AIC) Spurious Vector Register */ +/* ========== Register definition for PDC_DBGU peripheral ========== */ +#define AT91C_DBGU_TCR ( ( AT91_REG * ) 0xFFFFF30C ) /* (PDC_DBGU) Transmit Counter Register */ +#define AT91C_DBGU_RNPR ( ( AT91_REG * ) 0xFFFFF310 ) /* (PDC_DBGU) Receive Next Pointer Register */ +#define AT91C_DBGU_TNPR ( ( AT91_REG * ) 0xFFFFF318 ) /* (PDC_DBGU) Transmit Next Pointer Register */ +#define AT91C_DBGU_TPR ( ( AT91_REG * ) 0xFFFFF308 ) /* (PDC_DBGU) Transmit Pointer Register */ +#define AT91C_DBGU_RPR ( ( AT91_REG * ) 0xFFFFF300 ) /* (PDC_DBGU) Receive Pointer Register */ +#define AT91C_DBGU_RCR ( ( AT91_REG * ) 0xFFFFF304 ) /* (PDC_DBGU) Receive Counter Register */ +#define AT91C_DBGU_RNCR ( ( AT91_REG * ) 0xFFFFF314 ) /* (PDC_DBGU) Receive Next Counter Register */ +#define AT91C_DBGU_PTCR ( ( AT91_REG * ) 0xFFFFF320 ) /* (PDC_DBGU) PDC Transfer Control Register */ +#define AT91C_DBGU_PTSR ( ( AT91_REG * ) 0xFFFFF324 ) /* (PDC_DBGU) PDC Transfer Status Register */ +#define AT91C_DBGU_TNCR ( ( AT91_REG * ) 0xFFFFF31C ) /* (PDC_DBGU) Transmit Next Counter Register */ +/* ========== Register definition for DBGU peripheral ========== */ +#define AT91C_DBGU_EXID ( ( AT91_REG * ) 0xFFFFF244 ) /* (DBGU) Chip ID Extension Register */ +#define AT91C_DBGU_BRGR ( ( AT91_REG * ) 0xFFFFF220 ) /* (DBGU) Baud Rate Generator Register */ +#define AT91C_DBGU_IDR ( ( AT91_REG * ) 0xFFFFF20C ) /* (DBGU) Interrupt Disable Register */ +#define AT91C_DBGU_CSR ( ( AT91_REG * ) 0xFFFFF214 ) /* (DBGU) Channel Status Register */ +#define AT91C_DBGU_CIDR ( ( AT91_REG * ) 0xFFFFF240 ) /* (DBGU) Chip ID Register */ +#define AT91C_DBGU_MR ( ( AT91_REG * ) 0xFFFFF204 ) /* (DBGU) Mode Register */ +#define AT91C_DBGU_IMR ( ( AT91_REG * ) 0xFFFFF210 ) /* (DBGU) Interrupt Mask Register */ +#define AT91C_DBGU_CR ( ( AT91_REG * ) 0xFFFFF200 ) /* (DBGU) Control Register */ +#define AT91C_DBGU_FNTR ( ( AT91_REG * ) 0xFFFFF248 ) /* (DBGU) Force NTRST Register */ +#define AT91C_DBGU_THR ( ( AT91_REG * ) 0xFFFFF21C ) /* (DBGU) Transmitter Holding Register */ +#define AT91C_DBGU_RHR ( ( AT91_REG * ) 0xFFFFF218 ) /* (DBGU) Receiver Holding Register */ +#define AT91C_DBGU_IER ( ( AT91_REG * ) 0xFFFFF208 ) /* (DBGU) Interrupt Enable Register */ +/* ========== Register definition for PIOA peripheral ========== */ +#define AT91C_PIOA_ODR ( ( AT91_REG * ) 0xFFFFF414 ) /* (PIOA) Output Disable Registerr */ +#define AT91C_PIOA_SODR ( ( AT91_REG * ) 0xFFFFF430 ) /* (PIOA) Set Output Data Register */ +#define AT91C_PIOA_ISR ( ( AT91_REG * ) 0xFFFFF44C ) /* (PIOA) Interrupt Status Register */ +#define AT91C_PIOA_ABSR ( ( AT91_REG * ) 0xFFFFF478 ) /* (PIOA) AB Select Status Register */ +#define AT91C_PIOA_IER ( ( AT91_REG * ) 0xFFFFF440 ) /* (PIOA) Interrupt Enable Register */ +#define AT91C_PIOA_PPUDR ( ( AT91_REG * ) 0xFFFFF460 ) /* (PIOA) Pull-up Disable Register */ +#define AT91C_PIOA_IMR ( ( AT91_REG * ) 0xFFFFF448 ) /* (PIOA) Interrupt Mask Register */ +#define AT91C_PIOA_PER ( ( AT91_REG * ) 0xFFFFF400 ) /* (PIOA) PIO Enable Register */ +#define AT91C_PIOA_IFDR ( ( AT91_REG * ) 0xFFFFF424 ) /* (PIOA) Input Filter Disable Register */ +#define AT91C_PIOA_OWDR ( ( AT91_REG * ) 0xFFFFF4A4 ) /* (PIOA) Output Write Disable Register */ +#define AT91C_PIOA_MDSR ( ( AT91_REG * ) 0xFFFFF458 ) /* (PIOA) Multi-driver Status Register */ +#define AT91C_PIOA_IDR ( ( AT91_REG * ) 0xFFFFF444 ) /* (PIOA) Interrupt Disable Register */ +#define AT91C_PIOA_ODSR ( ( AT91_REG * ) 0xFFFFF438 ) /* (PIOA) Output Data Status Register */ +#define AT91C_PIOA_PPUSR ( ( AT91_REG * ) 0xFFFFF468 ) /* (PIOA) Pull-up Status Register */ +#define AT91C_PIOA_OWSR ( ( AT91_REG * ) 0xFFFFF4A8 ) /* (PIOA) Output Write Status Register */ +#define AT91C_PIOA_BSR ( ( AT91_REG * ) 0xFFFFF474 ) /* (PIOA) Select B Register */ +#define AT91C_PIOA_OWER ( ( AT91_REG * ) 0xFFFFF4A0 ) /* (PIOA) Output Write Enable Register */ +#define AT91C_PIOA_IFER ( ( AT91_REG * ) 0xFFFFF420 ) /* (PIOA) Input Filter Enable Register */ +#define AT91C_PIOA_PDSR ( ( AT91_REG * ) 0xFFFFF43C ) /* (PIOA) Pin Data Status Register */ +#define AT91C_PIOA_PPUER ( ( AT91_REG * ) 0xFFFFF464 ) /* (PIOA) Pull-up Enable Register */ +#define AT91C_PIOA_OSR ( ( AT91_REG * ) 0xFFFFF418 ) /* (PIOA) Output Status Register */ +#define AT91C_PIOA_ASR ( ( AT91_REG * ) 0xFFFFF470 ) /* (PIOA) Select A Register */ +#define AT91C_PIOA_MDDR ( ( AT91_REG * ) 0xFFFFF454 ) /* (PIOA) Multi-driver Disable Register */ +#define AT91C_PIOA_CODR ( ( AT91_REG * ) 0xFFFFF434 ) /* (PIOA) Clear Output Data Register */ +#define AT91C_PIOA_MDER ( ( AT91_REG * ) 0xFFFFF450 ) /* (PIOA) Multi-driver Enable Register */ +#define AT91C_PIOA_PDR ( ( AT91_REG * ) 0xFFFFF404 ) /* (PIOA) PIO Disable Register */ +#define AT91C_PIOA_IFSR ( ( AT91_REG * ) 0xFFFFF428 ) /* (PIOA) Input Filter Status Register */ +#define AT91C_PIOA_OER ( ( AT91_REG * ) 0xFFFFF410 ) /* (PIOA) Output Enable Register */ +#define AT91C_PIOA_PSR ( ( AT91_REG * ) 0xFFFFF408 ) /* (PIOA) PIO Status Register */ +/* ========== Register definition for PIOB peripheral ========== */ +#define AT91C_PIOB_OWDR ( ( AT91_REG * ) 0xFFFFF6A4 ) /* (PIOB) Output Write Disable Register */ +#define AT91C_PIOB_MDER ( ( AT91_REG * ) 0xFFFFF650 ) /* (PIOB) Multi-driver Enable Register */ +#define AT91C_PIOB_PPUSR ( ( AT91_REG * ) 0xFFFFF668 ) /* (PIOB) Pull-up Status Register */ +#define AT91C_PIOB_IMR ( ( AT91_REG * ) 0xFFFFF648 ) /* (PIOB) Interrupt Mask Register */ +#define AT91C_PIOB_ASR ( ( AT91_REG * ) 0xFFFFF670 ) /* (PIOB) Select A Register */ +#define AT91C_PIOB_PPUDR ( ( AT91_REG * ) 0xFFFFF660 ) /* (PIOB) Pull-up Disable Register */ +#define AT91C_PIOB_PSR ( ( AT91_REG * ) 0xFFFFF608 ) /* (PIOB) PIO Status Register */ +#define AT91C_PIOB_IER ( ( AT91_REG * ) 0xFFFFF640 ) /* (PIOB) Interrupt Enable Register */ +#define AT91C_PIOB_CODR ( ( AT91_REG * ) 0xFFFFF634 ) /* (PIOB) Clear Output Data Register */ +#define AT91C_PIOB_OWER ( ( AT91_REG * ) 0xFFFFF6A0 ) /* (PIOB) Output Write Enable Register */ +#define AT91C_PIOB_ABSR ( ( AT91_REG * ) 0xFFFFF678 ) /* (PIOB) AB Select Status Register */ +#define AT91C_PIOB_IFDR ( ( AT91_REG * ) 0xFFFFF624 ) /* (PIOB) Input Filter Disable Register */ +#define AT91C_PIOB_PDSR ( ( AT91_REG * ) 0xFFFFF63C ) /* (PIOB) Pin Data Status Register */ +#define AT91C_PIOB_IDR ( ( AT91_REG * ) 0xFFFFF644 ) /* (PIOB) Interrupt Disable Register */ +#define AT91C_PIOB_OWSR ( ( AT91_REG * ) 0xFFFFF6A8 ) /* (PIOB) Output Write Status Register */ +#define AT91C_PIOB_PDR ( ( AT91_REG * ) 0xFFFFF604 ) /* (PIOB) PIO Disable Register */ +#define AT91C_PIOB_ODR ( ( AT91_REG * ) 0xFFFFF614 ) /* (PIOB) Output Disable Registerr */ +#define AT91C_PIOB_IFSR ( ( AT91_REG * ) 0xFFFFF628 ) /* (PIOB) Input Filter Status Register */ +#define AT91C_PIOB_PPUER ( ( AT91_REG * ) 0xFFFFF664 ) /* (PIOB) Pull-up Enable Register */ +#define AT91C_PIOB_SODR ( ( AT91_REG * ) 0xFFFFF630 ) /* (PIOB) Set Output Data Register */ +#define AT91C_PIOB_ISR ( ( AT91_REG * ) 0xFFFFF64C ) /* (PIOB) Interrupt Status Register */ +#define AT91C_PIOB_ODSR ( ( AT91_REG * ) 0xFFFFF638 ) /* (PIOB) Output Data Status Register */ +#define AT91C_PIOB_OSR ( ( AT91_REG * ) 0xFFFFF618 ) /* (PIOB) Output Status Register */ +#define AT91C_PIOB_MDSR ( ( AT91_REG * ) 0xFFFFF658 ) /* (PIOB) Multi-driver Status Register */ +#define AT91C_PIOB_IFER ( ( AT91_REG * ) 0xFFFFF620 ) /* (PIOB) Input Filter Enable Register */ +#define AT91C_PIOB_BSR ( ( AT91_REG * ) 0xFFFFF674 ) /* (PIOB) Select B Register */ +#define AT91C_PIOB_MDDR ( ( AT91_REG * ) 0xFFFFF654 ) /* (PIOB) Multi-driver Disable Register */ +#define AT91C_PIOB_OER ( ( AT91_REG * ) 0xFFFFF610 ) /* (PIOB) Output Enable Register */ +#define AT91C_PIOB_PER ( ( AT91_REG * ) 0xFFFFF600 ) /* (PIOB) PIO Enable Register */ +/* ========== Register definition for CKGR peripheral ========== */ +#define AT91C_CKGR_MOR ( ( AT91_REG * ) 0xFFFFFC20 ) /* (CKGR) Main Oscillator Register */ +#define AT91C_CKGR_PLLR ( ( AT91_REG * ) 0xFFFFFC2C ) /* (CKGR) PLL Register */ +#define AT91C_CKGR_MCFR ( ( AT91_REG * ) 0xFFFFFC24 ) /* (CKGR) Main Clock Frequency Register */ +/* ========== Register definition for PMC peripheral ========== */ +#define AT91C_PMC_IDR ( ( AT91_REG * ) 0xFFFFFC64 ) /* (PMC) Interrupt Disable Register */ +#define AT91C_PMC_MOR ( ( AT91_REG * ) 0xFFFFFC20 ) /* (PMC) Main Oscillator Register */ +#define AT91C_PMC_PLLR ( ( AT91_REG * ) 0xFFFFFC2C ) /* (PMC) PLL Register */ +#define AT91C_PMC_PCER ( ( AT91_REG * ) 0xFFFFFC10 ) /* (PMC) Peripheral Clock Enable Register */ +#define AT91C_PMC_PCKR ( ( AT91_REG * ) 0xFFFFFC40 ) /* (PMC) Programmable Clock Register */ +#define AT91C_PMC_MCKR ( ( AT91_REG * ) 0xFFFFFC30 ) /* (PMC) Master Clock Register */ +#define AT91C_PMC_SCDR ( ( AT91_REG * ) 0xFFFFFC04 ) /* (PMC) System Clock Disable Register */ +#define AT91C_PMC_PCDR ( ( AT91_REG * ) 0xFFFFFC14 ) /* (PMC) Peripheral Clock Disable Register */ +#define AT91C_PMC_SCSR ( ( AT91_REG * ) 0xFFFFFC08 ) /* (PMC) System Clock Status Register */ +#define AT91C_PMC_PCSR ( ( AT91_REG * ) 0xFFFFFC18 ) /* (PMC) Peripheral Clock Status Register */ +#define AT91C_PMC_MCFR ( ( AT91_REG * ) 0xFFFFFC24 ) /* (PMC) Main Clock Frequency Register */ +#define AT91C_PMC_SCER ( ( AT91_REG * ) 0xFFFFFC00 ) /* (PMC) System Clock Enable Register */ +#define AT91C_PMC_IMR ( ( AT91_REG * ) 0xFFFFFC6C ) /* (PMC) Interrupt Mask Register */ +#define AT91C_PMC_IER ( ( AT91_REG * ) 0xFFFFFC60 ) /* (PMC) Interrupt Enable Register */ +#define AT91C_PMC_SR ( ( AT91_REG * ) 0xFFFFFC68 ) /* (PMC) Status Register */ +/* ========== Register definition for RSTC peripheral ========== */ +#define AT91C_RSTC_RCR ( ( AT91_REG * ) 0xFFFFFD00 ) /* (RSTC) Reset Control Register */ +#define AT91C_RSTC_RMR ( ( AT91_REG * ) 0xFFFFFD08 ) /* (RSTC) Reset Mode Register */ +#define AT91C_RSTC_RSR ( ( AT91_REG * ) 0xFFFFFD04 ) /* (RSTC) Reset Status Register */ +/* ========== Register definition for RTTC peripheral ========== */ +#define AT91C_RTTC_RTSR ( ( AT91_REG * ) 0xFFFFFD2C ) /* (RTTC) Real-time Status Register */ +#define AT91C_RTTC_RTMR ( ( AT91_REG * ) 0xFFFFFD20 ) /* (RTTC) Real-time Mode Register */ +#define AT91C_RTTC_RTVR ( ( AT91_REG * ) 0xFFFFFD28 ) /* (RTTC) Real-time Value Register */ +#define AT91C_RTTC_RTAR ( ( AT91_REG * ) 0xFFFFFD24 ) /* (RTTC) Real-time Alarm Register */ +/* ========== Register definition for PITC peripheral ========== */ +#define AT91C_PITC_PIVR ( ( AT91_REG * ) 0xFFFFFD38 ) /* (PITC) Period Interval Value Register */ +#define AT91C_PITC_PISR ( ( AT91_REG * ) 0xFFFFFD34 ) /* (PITC) Period Interval Status Register */ +#define AT91C_PITC_PIIR ( ( AT91_REG * ) 0xFFFFFD3C ) /* (PITC) Period Interval Image Register */ +#define AT91C_PITC_PIMR ( ( AT91_REG * ) 0xFFFFFD30 ) /* (PITC) Period Interval Mode Register */ +/* ========== Register definition for WDTC peripheral ========== */ +#define AT91C_WDTC_WDCR ( ( AT91_REG * ) 0xFFFFFD40 ) /* (WDTC) Watchdog Control Register */ +#define AT91C_WDTC_WDSR ( ( AT91_REG * ) 0xFFFFFD48 ) /* (WDTC) Watchdog Status Register */ +#define AT91C_WDTC_WDMR ( ( AT91_REG * ) 0xFFFFFD44 ) /* (WDTC) Watchdog Mode Register */ +/* ========== Register definition for VREG peripheral ========== */ +#define AT91C_VREG_MR ( ( AT91_REG * ) 0xFFFFFD60 ) /* (VREG) Voltage Regulator Mode Register */ +/* ========== Register definition for MC peripheral ========== */ +#define AT91C_MC_ASR ( ( AT91_REG * ) 0xFFFFFF04 ) /* (MC) MC Abort Status Register */ +#define AT91C_MC_RCR ( ( AT91_REG * ) 0xFFFFFF00 ) /* (MC) MC Remap Control Register */ +#define AT91C_MC_FCR ( ( AT91_REG * ) 0xFFFFFF64 ) /* (MC) MC Flash Command Register */ +#define AT91C_MC_AASR ( ( AT91_REG * ) 0xFFFFFF08 ) /* (MC) MC Abort Address Status Register */ +#define AT91C_MC_FSR ( ( AT91_REG * ) 0xFFFFFF68 ) /* (MC) MC Flash Status Register */ +#define AT91C_MC_FMR ( ( AT91_REG * ) 0xFFFFFF60 ) /* (MC) MC Flash Mode Register */ +/* ========== Register definition for PDC_SPI1 peripheral ========== */ +#define AT91C_SPI1_PTCR ( ( AT91_REG * ) 0xFFFE4120 ) /* (PDC_SPI1) PDC Transfer Control Register */ +#define AT91C_SPI1_RPR ( ( AT91_REG * ) 0xFFFE4100 ) /* (PDC_SPI1) Receive Pointer Register */ +#define AT91C_SPI1_TNCR ( ( AT91_REG * ) 0xFFFE411C ) /* (PDC_SPI1) Transmit Next Counter Register */ +#define AT91C_SPI1_TPR ( ( AT91_REG * ) 0xFFFE4108 ) /* (PDC_SPI1) Transmit Pointer Register */ +#define AT91C_SPI1_TNPR ( ( AT91_REG * ) 0xFFFE4118 ) /* (PDC_SPI1) Transmit Next Pointer Register */ +#define AT91C_SPI1_TCR ( ( AT91_REG * ) 0xFFFE410C ) /* (PDC_SPI1) Transmit Counter Register */ +#define AT91C_SPI1_RCR ( ( AT91_REG * ) 0xFFFE4104 ) /* (PDC_SPI1) Receive Counter Register */ +#define AT91C_SPI1_RNPR ( ( AT91_REG * ) 0xFFFE4110 ) /* (PDC_SPI1) Receive Next Pointer Register */ +#define AT91C_SPI1_RNCR ( ( AT91_REG * ) 0xFFFE4114 ) /* (PDC_SPI1) Receive Next Counter Register */ +#define AT91C_SPI1_PTSR ( ( AT91_REG * ) 0xFFFE4124 ) /* (PDC_SPI1) PDC Transfer Status Register */ +/* ========== Register definition for SPI1 peripheral ========== */ +#define AT91C_SPI1_IMR ( ( AT91_REG * ) 0xFFFE401C ) /* (SPI1) Interrupt Mask Register */ +#define AT91C_SPI1_IER ( ( AT91_REG * ) 0xFFFE4014 ) /* (SPI1) Interrupt Enable Register */ +#define AT91C_SPI1_MR ( ( AT91_REG * ) 0xFFFE4004 ) /* (SPI1) Mode Register */ +#define AT91C_SPI1_RDR ( ( AT91_REG * ) 0xFFFE4008 ) /* (SPI1) Receive Data Register */ +#define AT91C_SPI1_IDR ( ( AT91_REG * ) 0xFFFE4018 ) /* (SPI1) Interrupt Disable Register */ +#define AT91C_SPI1_SR ( ( AT91_REG * ) 0xFFFE4010 ) /* (SPI1) Status Register */ +#define AT91C_SPI1_TDR ( ( AT91_REG * ) 0xFFFE400C ) /* (SPI1) Transmit Data Register */ +#define AT91C_SPI1_CR ( ( AT91_REG * ) 0xFFFE4000 ) /* (SPI1) Control Register */ +#define AT91C_SPI1_CSR ( ( AT91_REG * ) 0xFFFE4030 ) /* (SPI1) Chip Select Register */ +/* ========== Register definition for PDC_SPI0 peripheral ========== */ +#define AT91C_SPI0_PTCR ( ( AT91_REG * ) 0xFFFE0120 ) /* (PDC_SPI0) PDC Transfer Control Register */ +#define AT91C_SPI0_TPR ( ( AT91_REG * ) 0xFFFE0108 ) /* (PDC_SPI0) Transmit Pointer Register */ +#define AT91C_SPI0_TCR ( ( AT91_REG * ) 0xFFFE010C ) /* (PDC_SPI0) Transmit Counter Register */ +#define AT91C_SPI0_RCR ( ( AT91_REG * ) 0xFFFE0104 ) /* (PDC_SPI0) Receive Counter Register */ +#define AT91C_SPI0_PTSR ( ( AT91_REG * ) 0xFFFE0124 ) /* (PDC_SPI0) PDC Transfer Status Register */ +#define AT91C_SPI0_RNPR ( ( AT91_REG * ) 0xFFFE0110 ) /* (PDC_SPI0) Receive Next Pointer Register */ +#define AT91C_SPI0_RPR ( ( AT91_REG * ) 0xFFFE0100 ) /* (PDC_SPI0) Receive Pointer Register */ +#define AT91C_SPI0_TNCR ( ( AT91_REG * ) 0xFFFE011C ) /* (PDC_SPI0) Transmit Next Counter Register */ +#define AT91C_SPI0_RNCR ( ( AT91_REG * ) 0xFFFE0114 ) /* (PDC_SPI0) Receive Next Counter Register */ +#define AT91C_SPI0_TNPR ( ( AT91_REG * ) 0xFFFE0118 ) /* (PDC_SPI0) Transmit Next Pointer Register */ +/* ========== Register definition for SPI0 peripheral ========== */ +#define AT91C_SPI0_IER ( ( AT91_REG * ) 0xFFFE0014 ) /* (SPI0) Interrupt Enable Register */ +#define AT91C_SPI0_SR ( ( AT91_REG * ) 0xFFFE0010 ) /* (SPI0) Status Register */ +#define AT91C_SPI0_IDR ( ( AT91_REG * ) 0xFFFE0018 ) /* (SPI0) Interrupt Disable Register */ +#define AT91C_SPI0_CR ( ( AT91_REG * ) 0xFFFE0000 ) /* (SPI0) Control Register */ +#define AT91C_SPI0_MR ( ( AT91_REG * ) 0xFFFE0004 ) /* (SPI0) Mode Register */ +#define AT91C_SPI0_IMR ( ( AT91_REG * ) 0xFFFE001C ) /* (SPI0) Interrupt Mask Register */ +#define AT91C_SPI0_TDR ( ( AT91_REG * ) 0xFFFE000C ) /* (SPI0) Transmit Data Register */ +#define AT91C_SPI0_RDR ( ( AT91_REG * ) 0xFFFE0008 ) /* (SPI0) Receive Data Register */ +#define AT91C_SPI0_CSR ( ( AT91_REG * ) 0xFFFE0030 ) /* (SPI0) Chip Select Register */ +/* ========== Register definition for PDC_US1 peripheral ========== */ +#define AT91C_US1_RNCR ( ( AT91_REG * ) 0xFFFC4114 ) /* (PDC_US1) Receive Next Counter Register */ +#define AT91C_US1_PTCR ( ( AT91_REG * ) 0xFFFC4120 ) /* (PDC_US1) PDC Transfer Control Register */ +#define AT91C_US1_TCR ( ( AT91_REG * ) 0xFFFC410C ) /* (PDC_US1) Transmit Counter Register */ +#define AT91C_US1_PTSR ( ( AT91_REG * ) 0xFFFC4124 ) /* (PDC_US1) PDC Transfer Status Register */ +#define AT91C_US1_TNPR ( ( AT91_REG * ) 0xFFFC4118 ) /* (PDC_US1) Transmit Next Pointer Register */ +#define AT91C_US1_RCR ( ( AT91_REG * ) 0xFFFC4104 ) /* (PDC_US1) Receive Counter Register */ +#define AT91C_US1_RNPR ( ( AT91_REG * ) 0xFFFC4110 ) /* (PDC_US1) Receive Next Pointer Register */ +#define AT91C_US1_RPR ( ( AT91_REG * ) 0xFFFC4100 ) /* (PDC_US1) Receive Pointer Register */ +#define AT91C_US1_TNCR ( ( AT91_REG * ) 0xFFFC411C ) /* (PDC_US1) Transmit Next Counter Register */ +#define AT91C_US1_TPR ( ( AT91_REG * ) 0xFFFC4108 ) /* (PDC_US1) Transmit Pointer Register */ +/* ========== Register definition for US1 peripheral ========== */ +#define AT91C_US1_IF ( ( AT91_REG * ) 0xFFFC404C ) /* (US1) IRDA_FILTER Register */ +#define AT91C_US1_NER ( ( AT91_REG * ) 0xFFFC4044 ) /* (US1) Nb Errors Register */ +#define AT91C_US1_RTOR ( ( AT91_REG * ) 0xFFFC4024 ) /* (US1) Receiver Time-out Register */ +#define AT91C_US1_CSR ( ( AT91_REG * ) 0xFFFC4014 ) /* (US1) Channel Status Register */ +#define AT91C_US1_IDR ( ( AT91_REG * ) 0xFFFC400C ) /* (US1) Interrupt Disable Register */ +#define AT91C_US1_IER ( ( AT91_REG * ) 0xFFFC4008 ) /* (US1) Interrupt Enable Register */ +#define AT91C_US1_THR ( ( AT91_REG * ) 0xFFFC401C ) /* (US1) Transmitter Holding Register */ +#define AT91C_US1_TTGR ( ( AT91_REG * ) 0xFFFC4028 ) /* (US1) Transmitter Time-guard Register */ +#define AT91C_US1_RHR ( ( AT91_REG * ) 0xFFFC4018 ) /* (US1) Receiver Holding Register */ +#define AT91C_US1_BRGR ( ( AT91_REG * ) 0xFFFC4020 ) /* (US1) Baud Rate Generator Register */ +#define AT91C_US1_IMR ( ( AT91_REG * ) 0xFFFC4010 ) /* (US1) Interrupt Mask Register */ +#define AT91C_US1_FIDI ( ( AT91_REG * ) 0xFFFC4040 ) /* (US1) FI_DI_Ratio Register */ +#define AT91C_US1_CR ( ( AT91_REG * ) 0xFFFC4000 ) /* (US1) Control Register */ +#define AT91C_US1_MR ( ( AT91_REG * ) 0xFFFC4004 ) /* (US1) Mode Register */ +/* ========== Register definition for PDC_US0 peripheral ========== */ +#define AT91C_US0_TNPR ( ( AT91_REG * ) 0xFFFC0118 ) /* (PDC_US0) Transmit Next Pointer Register */ +#define AT91C_US0_RNPR ( ( AT91_REG * ) 0xFFFC0110 ) /* (PDC_US0) Receive Next Pointer Register */ +#define AT91C_US0_TCR ( ( AT91_REG * ) 0xFFFC010C ) /* (PDC_US0) Transmit Counter Register */ +#define AT91C_US0_PTCR ( ( AT91_REG * ) 0xFFFC0120 ) /* (PDC_US0) PDC Transfer Control Register */ +#define AT91C_US0_PTSR ( ( AT91_REG * ) 0xFFFC0124 ) /* (PDC_US0) PDC Transfer Status Register */ +#define AT91C_US0_TNCR ( ( AT91_REG * ) 0xFFFC011C ) /* (PDC_US0) Transmit Next Counter Register */ +#define AT91C_US0_TPR ( ( AT91_REG * ) 0xFFFC0108 ) /* (PDC_US0) Transmit Pointer Register */ +#define AT91C_US0_RCR ( ( AT91_REG * ) 0xFFFC0104 ) /* (PDC_US0) Receive Counter Register */ +#define AT91C_US0_RPR ( ( AT91_REG * ) 0xFFFC0100 ) /* (PDC_US0) Receive Pointer Register */ +#define AT91C_US0_RNCR ( ( AT91_REG * ) 0xFFFC0114 ) /* (PDC_US0) Receive Next Counter Register */ +/* ========== Register definition for US0 peripheral ========== */ +#define AT91C_US0_BRGR ( ( AT91_REG * ) 0xFFFC0020 ) /* (US0) Baud Rate Generator Register */ +#define AT91C_US0_NER ( ( AT91_REG * ) 0xFFFC0044 ) /* (US0) Nb Errors Register */ +#define AT91C_US0_CR ( ( AT91_REG * ) 0xFFFC0000 ) /* (US0) Control Register */ +#define AT91C_US0_IMR ( ( AT91_REG * ) 0xFFFC0010 ) /* (US0) Interrupt Mask Register */ +#define AT91C_US0_FIDI ( ( AT91_REG * ) 0xFFFC0040 ) /* (US0) FI_DI_Ratio Register */ +#define AT91C_US0_TTGR ( ( AT91_REG * ) 0xFFFC0028 ) /* (US0) Transmitter Time-guard Register */ +#define AT91C_US0_MR ( ( AT91_REG * ) 0xFFFC0004 ) /* (US0) Mode Register */ +#define AT91C_US0_RTOR ( ( AT91_REG * ) 0xFFFC0024 ) /* (US0) Receiver Time-out Register */ +#define AT91C_US0_CSR ( ( AT91_REG * ) 0xFFFC0014 ) /* (US0) Channel Status Register */ +#define AT91C_US0_RHR ( ( AT91_REG * ) 0xFFFC0018 ) /* (US0) Receiver Holding Register */ +#define AT91C_US0_IDR ( ( AT91_REG * ) 0xFFFC000C ) /* (US0) Interrupt Disable Register */ +#define AT91C_US0_THR ( ( AT91_REG * ) 0xFFFC001C ) /* (US0) Transmitter Holding Register */ +#define AT91C_US0_IF ( ( AT91_REG * ) 0xFFFC004C ) /* (US0) IRDA_FILTER Register */ +#define AT91C_US0_IER ( ( AT91_REG * ) 0xFFFC0008 ) /* (US0) Interrupt Enable Register */ +/* ========== Register definition for PDC_SSC peripheral ========== */ +#define AT91C_SSC_TNCR ( ( AT91_REG * ) 0xFFFD411C ) /* (PDC_SSC) Transmit Next Counter Register */ +#define AT91C_SSC_RPR ( ( AT91_REG * ) 0xFFFD4100 ) /* (PDC_SSC) Receive Pointer Register */ +#define AT91C_SSC_RNCR ( ( AT91_REG * ) 0xFFFD4114 ) /* (PDC_SSC) Receive Next Counter Register */ +#define AT91C_SSC_TPR ( ( AT91_REG * ) 0xFFFD4108 ) /* (PDC_SSC) Transmit Pointer Register */ +#define AT91C_SSC_PTCR ( ( AT91_REG * ) 0xFFFD4120 ) /* (PDC_SSC) PDC Transfer Control Register */ +#define AT91C_SSC_TCR ( ( AT91_REG * ) 0xFFFD410C ) /* (PDC_SSC) Transmit Counter Register */ +#define AT91C_SSC_RCR ( ( AT91_REG * ) 0xFFFD4104 ) /* (PDC_SSC) Receive Counter Register */ +#define AT91C_SSC_RNPR ( ( AT91_REG * ) 0xFFFD4110 ) /* (PDC_SSC) Receive Next Pointer Register */ +#define AT91C_SSC_TNPR ( ( AT91_REG * ) 0xFFFD4118 ) /* (PDC_SSC) Transmit Next Pointer Register */ +#define AT91C_SSC_PTSR ( ( AT91_REG * ) 0xFFFD4124 ) /* (PDC_SSC) PDC Transfer Status Register */ +/* ========== Register definition for SSC peripheral ========== */ +#define AT91C_SSC_RHR ( ( AT91_REG * ) 0xFFFD4020 ) /* (SSC) Receive Holding Register */ +#define AT91C_SSC_RSHR ( ( AT91_REG * ) 0xFFFD4030 ) /* (SSC) Receive Sync Holding Register */ +#define AT91C_SSC_TFMR ( ( AT91_REG * ) 0xFFFD401C ) /* (SSC) Transmit Frame Mode Register */ +#define AT91C_SSC_IDR ( ( AT91_REG * ) 0xFFFD4048 ) /* (SSC) Interrupt Disable Register */ +#define AT91C_SSC_THR ( ( AT91_REG * ) 0xFFFD4024 ) /* (SSC) Transmit Holding Register */ +#define AT91C_SSC_RCMR ( ( AT91_REG * ) 0xFFFD4010 ) /* (SSC) Receive Clock ModeRegister */ +#define AT91C_SSC_IER ( ( AT91_REG * ) 0xFFFD4044 ) /* (SSC) Interrupt Enable Register */ +#define AT91C_SSC_TSHR ( ( AT91_REG * ) 0xFFFD4034 ) /* (SSC) Transmit Sync Holding Register */ +#define AT91C_SSC_SR ( ( AT91_REG * ) 0xFFFD4040 ) /* (SSC) Status Register */ +#define AT91C_SSC_CMR ( ( AT91_REG * ) 0xFFFD4004 ) /* (SSC) Clock Mode Register */ +#define AT91C_SSC_TCMR ( ( AT91_REG * ) 0xFFFD4018 ) /* (SSC) Transmit Clock Mode Register */ +#define AT91C_SSC_CR ( ( AT91_REG * ) 0xFFFD4000 ) /* (SSC) Control Register */ +#define AT91C_SSC_IMR ( ( AT91_REG * ) 0xFFFD404C ) /* (SSC) Interrupt Mask Register */ +#define AT91C_SSC_RFMR ( ( AT91_REG * ) 0xFFFD4014 ) /* (SSC) Receive Frame Mode Register */ +/* ========== Register definition for TWI peripheral ========== */ +#define AT91C_TWI_IER ( ( AT91_REG * ) 0xFFFB8024 ) /* (TWI) Interrupt Enable Register */ +#define AT91C_TWI_CR ( ( AT91_REG * ) 0xFFFB8000 ) /* (TWI) Control Register */ +#define AT91C_TWI_SR ( ( AT91_REG * ) 0xFFFB8020 ) /* (TWI) Status Register */ +#define AT91C_TWI_IMR ( ( AT91_REG * ) 0xFFFB802C ) /* (TWI) Interrupt Mask Register */ +#define AT91C_TWI_THR ( ( AT91_REG * ) 0xFFFB8034 ) /* (TWI) Transmit Holding Register */ +#define AT91C_TWI_IDR ( ( AT91_REG * ) 0xFFFB8028 ) /* (TWI) Interrupt Disable Register */ +#define AT91C_TWI_IADR ( ( AT91_REG * ) 0xFFFB800C ) /* (TWI) Internal Address Register */ +#define AT91C_TWI_MMR ( ( AT91_REG * ) 0xFFFB8004 ) /* (TWI) Master Mode Register */ +#define AT91C_TWI_CWGR ( ( AT91_REG * ) 0xFFFB8010 ) /* (TWI) Clock Waveform Generator Register */ +#define AT91C_TWI_RHR ( ( AT91_REG * ) 0xFFFB8030 ) /* (TWI) Receive Holding Register */ +/* ========== Register definition for PWMC_CH3 peripheral ========== */ +#define AT91C_PWMC_CH3_CUPDR ( ( AT91_REG * ) 0xFFFCC270 ) /* (PWMC_CH3) Channel Update Register */ +#define AT91C_PWMC_CH3_Reserved ( ( AT91_REG * ) 0xFFFCC274 ) /* (PWMC_CH3) Reserved */ +#define AT91C_PWMC_CH3_CPRDR ( ( AT91_REG * ) 0xFFFCC268 ) /* (PWMC_CH3) Channel Period Register */ +#define AT91C_PWMC_CH3_CDTYR ( ( AT91_REG * ) 0xFFFCC264 ) /* (PWMC_CH3) Channel Duty Cycle Register */ +#define AT91C_PWMC_CH3_CCNTR ( ( AT91_REG * ) 0xFFFCC26C ) /* (PWMC_CH3) Channel Counter Register */ +#define AT91C_PWMC_CH3_CMR ( ( AT91_REG * ) 0xFFFCC260 ) /* (PWMC_CH3) Channel Mode Register */ +/* ========== Register definition for PWMC_CH2 peripheral ========== */ +#define AT91C_PWMC_CH2_Reserved ( ( AT91_REG * ) 0xFFFCC254 ) /* (PWMC_CH2) Reserved */ +#define AT91C_PWMC_CH2_CMR ( ( AT91_REG * ) 0xFFFCC240 ) /* (PWMC_CH2) Channel Mode Register */ +#define AT91C_PWMC_CH2_CCNTR ( ( AT91_REG * ) 0xFFFCC24C ) /* (PWMC_CH2) Channel Counter Register */ +#define AT91C_PWMC_CH2_CPRDR ( ( AT91_REG * ) 0xFFFCC248 ) /* (PWMC_CH2) Channel Period Register */ +#define AT91C_PWMC_CH2_CUPDR ( ( AT91_REG * ) 0xFFFCC250 ) /* (PWMC_CH2) Channel Update Register */ +#define AT91C_PWMC_CH2_CDTYR ( ( AT91_REG * ) 0xFFFCC244 ) /* (PWMC_CH2) Channel Duty Cycle Register */ +/* ========== Register definition for PWMC_CH1 peripheral ========== */ +#define AT91C_PWMC_CH1_Reserved ( ( AT91_REG * ) 0xFFFCC234 ) /* (PWMC_CH1) Reserved */ +#define AT91C_PWMC_CH1_CUPDR ( ( AT91_REG * ) 0xFFFCC230 ) /* (PWMC_CH1) Channel Update Register */ +#define AT91C_PWMC_CH1_CPRDR ( ( AT91_REG * ) 0xFFFCC228 ) /* (PWMC_CH1) Channel Period Register */ +#define AT91C_PWMC_CH1_CCNTR ( ( AT91_REG * ) 0xFFFCC22C ) /* (PWMC_CH1) Channel Counter Register */ +#define AT91C_PWMC_CH1_CDTYR ( ( AT91_REG * ) 0xFFFCC224 ) /* (PWMC_CH1) Channel Duty Cycle Register */ +#define AT91C_PWMC_CH1_CMR ( ( AT91_REG * ) 0xFFFCC220 ) /* (PWMC_CH1) Channel Mode Register */ +/* ========== Register definition for PWMC_CH0 peripheral ========== */ +#define AT91C_PWMC_CH0_Reserved ( ( AT91_REG * ) 0xFFFCC214 ) /* (PWMC_CH0) Reserved */ +#define AT91C_PWMC_CH0_CPRDR ( ( AT91_REG * ) 0xFFFCC208 ) /* (PWMC_CH0) Channel Period Register */ +#define AT91C_PWMC_CH0_CDTYR ( ( AT91_REG * ) 0xFFFCC204 ) /* (PWMC_CH0) Channel Duty Cycle Register */ +#define AT91C_PWMC_CH0_CMR ( ( AT91_REG * ) 0xFFFCC200 ) /* (PWMC_CH0) Channel Mode Register */ +#define AT91C_PWMC_CH0_CUPDR ( ( AT91_REG * ) 0xFFFCC210 ) /* (PWMC_CH0) Channel Update Register */ +#define AT91C_PWMC_CH0_CCNTR ( ( AT91_REG * ) 0xFFFCC20C ) /* (PWMC_CH0) Channel Counter Register */ +/* ========== Register definition for PWMC peripheral ========== */ +#define AT91C_PWMC_IDR ( ( AT91_REG * ) 0xFFFCC014 ) /* (PWMC) PWMC Interrupt Disable Register */ +#define AT91C_PWMC_DIS ( ( AT91_REG * ) 0xFFFCC008 ) /* (PWMC) PWMC Disable Register */ +#define AT91C_PWMC_IER ( ( AT91_REG * ) 0xFFFCC010 ) /* (PWMC) PWMC Interrupt Enable Register */ +#define AT91C_PWMC_VR ( ( AT91_REG * ) 0xFFFCC0FC ) /* (PWMC) PWMC Version Register */ +#define AT91C_PWMC_ISR ( ( AT91_REG * ) 0xFFFCC01C ) /* (PWMC) PWMC Interrupt Status Register */ +#define AT91C_PWMC_SR ( ( AT91_REG * ) 0xFFFCC00C ) /* (PWMC) PWMC Status Register */ +#define AT91C_PWMC_IMR ( ( AT91_REG * ) 0xFFFCC018 ) /* (PWMC) PWMC Interrupt Mask Register */ +#define AT91C_PWMC_MR ( ( AT91_REG * ) 0xFFFCC000 ) /* (PWMC) PWMC Mode Register */ +#define AT91C_PWMC_ENA ( ( AT91_REG * ) 0xFFFCC004 ) /* (PWMC) PWMC Enable Register */ +/* ========== Register definition for UDP peripheral ========== */ +#define AT91C_UDP_IMR ( ( AT91_REG * ) 0xFFFB0018 ) /* (UDP) Interrupt Mask Register */ +#define AT91C_UDP_FADDR ( ( AT91_REG * ) 0xFFFB0008 ) /* (UDP) Function Address Register */ +#define AT91C_UDP_NUM ( ( AT91_REG * ) 0xFFFB0000 ) /* (UDP) Frame Number Register */ +#define AT91C_UDP_FDR ( ( AT91_REG * ) 0xFFFB0050 ) /* (UDP) Endpoint FIFO Data Register */ +#define AT91C_UDP_ISR ( ( AT91_REG * ) 0xFFFB001C ) /* (UDP) Interrupt Status Register */ +#define AT91C_UDP_CSR ( ( AT91_REG * ) 0xFFFB0030 ) /* (UDP) Endpoint Control and Status Register */ +#define AT91C_UDP_IDR ( ( AT91_REG * ) 0xFFFB0014 ) /* (UDP) Interrupt Disable Register */ +#define AT91C_UDP_ICR ( ( AT91_REG * ) 0xFFFB0020 ) /* (UDP) Interrupt Clear Register */ +#define AT91C_UDP_RSTEP ( ( AT91_REG * ) 0xFFFB0028 ) /* (UDP) Reset Endpoint Register */ +#define AT91C_UDP_TXVC ( ( AT91_REG * ) 0xFFFB0074 ) /* (UDP) Transceiver Control Register */ +#define AT91C_UDP_GLBSTATE ( ( AT91_REG * ) 0xFFFB0004 ) /* (UDP) Global State Register */ +#define AT91C_UDP_IER ( ( AT91_REG * ) 0xFFFB0010 ) /* (UDP) Interrupt Enable Register */ +/* ========== Register definition for TC0 peripheral ========== */ +#define AT91C_TC0_SR ( ( AT91_REG * ) 0xFFFA0020 ) /* (TC0) Status Register */ +#define AT91C_TC0_RC ( ( AT91_REG * ) 0xFFFA001C ) /* (TC0) Register C */ +#define AT91C_TC0_RB ( ( AT91_REG * ) 0xFFFA0018 ) /* (TC0) Register B */ +#define AT91C_TC0_CCR ( ( AT91_REG * ) 0xFFFA0000 ) /* (TC0) Channel Control Register */ +#define AT91C_TC0_CMR ( ( AT91_REG * ) 0xFFFA0004 ) /* (TC0) Channel Mode Register (Capture Mode / Waveform Mode) */ +#define AT91C_TC0_IER ( ( AT91_REG * ) 0xFFFA0024 ) /* (TC0) Interrupt Enable Register */ +#define AT91C_TC0_RA ( ( AT91_REG * ) 0xFFFA0014 ) /* (TC0) Register A */ +#define AT91C_TC0_IDR ( ( AT91_REG * ) 0xFFFA0028 ) /* (TC0) Interrupt Disable Register */ +#define AT91C_TC0_CV ( ( AT91_REG * ) 0xFFFA0010 ) /* (TC0) Counter Value */ +#define AT91C_TC0_IMR ( ( AT91_REG * ) 0xFFFA002C ) /* (TC0) Interrupt Mask Register */ +/* ========== Register definition for TC1 peripheral ========== */ +#define AT91C_TC1_RB ( ( AT91_REG * ) 0xFFFA0058 ) /* (TC1) Register B */ +#define AT91C_TC1_CCR ( ( AT91_REG * ) 0xFFFA0040 ) /* (TC1) Channel Control Register */ +#define AT91C_TC1_IER ( ( AT91_REG * ) 0xFFFA0064 ) /* (TC1) Interrupt Enable Register */ +#define AT91C_TC1_IDR ( ( AT91_REG * ) 0xFFFA0068 ) /* (TC1) Interrupt Disable Register */ +#define AT91C_TC1_SR ( ( AT91_REG * ) 0xFFFA0060 ) /* (TC1) Status Register */ +#define AT91C_TC1_CMR ( ( AT91_REG * ) 0xFFFA0044 ) /* (TC1) Channel Mode Register (Capture Mode / Waveform Mode) */ +#define AT91C_TC1_RA ( ( AT91_REG * ) 0xFFFA0054 ) /* (TC1) Register A */ +#define AT91C_TC1_RC ( ( AT91_REG * ) 0xFFFA005C ) /* (TC1) Register C */ +#define AT91C_TC1_IMR ( ( AT91_REG * ) 0xFFFA006C ) /* (TC1) Interrupt Mask Register */ +#define AT91C_TC1_CV ( ( AT91_REG * ) 0xFFFA0050 ) /* (TC1) Counter Value */ +/* ========== Register definition for TC2 peripheral ========== */ +#define AT91C_TC2_CMR ( ( AT91_REG * ) 0xFFFA0084 ) /* (TC2) Channel Mode Register (Capture Mode / Waveform Mode) */ +#define AT91C_TC2_CCR ( ( AT91_REG * ) 0xFFFA0080 ) /* (TC2) Channel Control Register */ +#define AT91C_TC2_CV ( ( AT91_REG * ) 0xFFFA0090 ) /* (TC2) Counter Value */ +#define AT91C_TC2_RA ( ( AT91_REG * ) 0xFFFA0094 ) /* (TC2) Register A */ +#define AT91C_TC2_RB ( ( AT91_REG * ) 0xFFFA0098 ) /* (TC2) Register B */ +#define AT91C_TC2_IDR ( ( AT91_REG * ) 0xFFFA00A8 ) /* (TC2) Interrupt Disable Register */ +#define AT91C_TC2_IMR ( ( AT91_REG * ) 0xFFFA00AC ) /* (TC2) Interrupt Mask Register */ +#define AT91C_TC2_RC ( ( AT91_REG * ) 0xFFFA009C ) /* (TC2) Register C */ +#define AT91C_TC2_IER ( ( AT91_REG * ) 0xFFFA00A4 ) /* (TC2) Interrupt Enable Register */ +#define AT91C_TC2_SR ( ( AT91_REG * ) 0xFFFA00A0 ) /* (TC2) Status Register */ +/* ========== Register definition for TCB peripheral ========== */ +#define AT91C_TCB_BMR ( ( AT91_REG * ) 0xFFFA00C4 ) /* (TCB) TC Block Mode Register */ +#define AT91C_TCB_BCR ( ( AT91_REG * ) 0xFFFA00C0 ) /* (TCB) TC Block Control Register */ +/* ========== Register definition for CAN_MB0 peripheral ========== */ +#define AT91C_CAN_MB0_MDL ( ( AT91_REG * ) 0xFFFD0214 ) /* (CAN_MB0) MailBox Data Low Register */ +#define AT91C_CAN_MB0_MAM ( ( AT91_REG * ) 0xFFFD0204 ) /* (CAN_MB0) MailBox Acceptance Mask Register */ +#define AT91C_CAN_MB0_MCR ( ( AT91_REG * ) 0xFFFD021C ) /* (CAN_MB0) MailBox Control Register */ +#define AT91C_CAN_MB0_MID ( ( AT91_REG * ) 0xFFFD0208 ) /* (CAN_MB0) MailBox ID Register */ +#define AT91C_CAN_MB0_MSR ( ( AT91_REG * ) 0xFFFD0210 ) /* (CAN_MB0) MailBox Status Register */ +#define AT91C_CAN_MB0_MFID ( ( AT91_REG * ) 0xFFFD020C ) /* (CAN_MB0) MailBox Family ID Register */ +#define AT91C_CAN_MB0_MDH ( ( AT91_REG * ) 0xFFFD0218 ) /* (CAN_MB0) MailBox Data High Register */ +#define AT91C_CAN_MB0_MMR ( ( AT91_REG * ) 0xFFFD0200 ) /* (CAN_MB0) MailBox Mode Register */ +/* ========== Register definition for CAN_MB1 peripheral ========== */ +#define AT91C_CAN_MB1_MDL ( ( AT91_REG * ) 0xFFFD0234 ) /* (CAN_MB1) MailBox Data Low Register */ +#define AT91C_CAN_MB1_MID ( ( AT91_REG * ) 0xFFFD0228 ) /* (CAN_MB1) MailBox ID Register */ +#define AT91C_CAN_MB1_MMR ( ( AT91_REG * ) 0xFFFD0220 ) /* (CAN_MB1) MailBox Mode Register */ +#define AT91C_CAN_MB1_MSR ( ( AT91_REG * ) 0xFFFD0230 ) /* (CAN_MB1) MailBox Status Register */ +#define AT91C_CAN_MB1_MAM ( ( AT91_REG * ) 0xFFFD0224 ) /* (CAN_MB1) MailBox Acceptance Mask Register */ +#define AT91C_CAN_MB1_MDH ( ( AT91_REG * ) 0xFFFD0238 ) /* (CAN_MB1) MailBox Data High Register */ +#define AT91C_CAN_MB1_MCR ( ( AT91_REG * ) 0xFFFD023C ) /* (CAN_MB1) MailBox Control Register */ +#define AT91C_CAN_MB1_MFID ( ( AT91_REG * ) 0xFFFD022C ) /* (CAN_MB1) MailBox Family ID Register */ +/* ========== Register definition for CAN_MB2 peripheral ========== */ +#define AT91C_CAN_MB2_MCR ( ( AT91_REG * ) 0xFFFD025C ) /* (CAN_MB2) MailBox Control Register */ +#define AT91C_CAN_MB2_MDH ( ( AT91_REG * ) 0xFFFD0258 ) /* (CAN_MB2) MailBox Data High Register */ +#define AT91C_CAN_MB2_MID ( ( AT91_REG * ) 0xFFFD0248 ) /* (CAN_MB2) MailBox ID Register */ +#define AT91C_CAN_MB2_MDL ( ( AT91_REG * ) 0xFFFD0254 ) /* (CAN_MB2) MailBox Data Low Register */ +#define AT91C_CAN_MB2_MMR ( ( AT91_REG * ) 0xFFFD0240 ) /* (CAN_MB2) MailBox Mode Register */ +#define AT91C_CAN_MB2_MAM ( ( AT91_REG * ) 0xFFFD0244 ) /* (CAN_MB2) MailBox Acceptance Mask Register */ +#define AT91C_CAN_MB2_MFID ( ( AT91_REG * ) 0xFFFD024C ) /* (CAN_MB2) MailBox Family ID Register */ +#define AT91C_CAN_MB2_MSR ( ( AT91_REG * ) 0xFFFD0250 ) /* (CAN_MB2) MailBox Status Register */ +/* ========== Register definition for CAN_MB3 peripheral ========== */ +#define AT91C_CAN_MB3_MFID ( ( AT91_REG * ) 0xFFFD026C ) /* (CAN_MB3) MailBox Family ID Register */ +#define AT91C_CAN_MB3_MAM ( ( AT91_REG * ) 0xFFFD0264 ) /* (CAN_MB3) MailBox Acceptance Mask Register */ +#define AT91C_CAN_MB3_MID ( ( AT91_REG * ) 0xFFFD0268 ) /* (CAN_MB3) MailBox ID Register */ +#define AT91C_CAN_MB3_MCR ( ( AT91_REG * ) 0xFFFD027C ) /* (CAN_MB3) MailBox Control Register */ +#define AT91C_CAN_MB3_MMR ( ( AT91_REG * ) 0xFFFD0260 ) /* (CAN_MB3) MailBox Mode Register */ +#define AT91C_CAN_MB3_MSR ( ( AT91_REG * ) 0xFFFD0270 ) /* (CAN_MB3) MailBox Status Register */ +#define AT91C_CAN_MB3_MDL ( ( AT91_REG * ) 0xFFFD0274 ) /* (CAN_MB3) MailBox Data Low Register */ +#define AT91C_CAN_MB3_MDH ( ( AT91_REG * ) 0xFFFD0278 ) /* (CAN_MB3) MailBox Data High Register */ +/* ========== Register definition for CAN_MB4 peripheral ========== */ +#define AT91C_CAN_MB4_MID ( ( AT91_REG * ) 0xFFFD0288 ) /* (CAN_MB4) MailBox ID Register */ +#define AT91C_CAN_MB4_MMR ( ( AT91_REG * ) 0xFFFD0280 ) /* (CAN_MB4) MailBox Mode Register */ +#define AT91C_CAN_MB4_MDH ( ( AT91_REG * ) 0xFFFD0298 ) /* (CAN_MB4) MailBox Data High Register */ +#define AT91C_CAN_MB4_MFID ( ( AT91_REG * ) 0xFFFD028C ) /* (CAN_MB4) MailBox Family ID Register */ +#define AT91C_CAN_MB4_MSR ( ( AT91_REG * ) 0xFFFD0290 ) /* (CAN_MB4) MailBox Status Register */ +#define AT91C_CAN_MB4_MCR ( ( AT91_REG * ) 0xFFFD029C ) /* (CAN_MB4) MailBox Control Register */ +#define AT91C_CAN_MB4_MDL ( ( AT91_REG * ) 0xFFFD0294 ) /* (CAN_MB4) MailBox Data Low Register */ +#define AT91C_CAN_MB4_MAM ( ( AT91_REG * ) 0xFFFD0284 ) /* (CAN_MB4) MailBox Acceptance Mask Register */ +/* ========== Register definition for CAN_MB5 peripheral ========== */ +#define AT91C_CAN_MB5_MSR ( ( AT91_REG * ) 0xFFFD02B0 ) /* (CAN_MB5) MailBox Status Register */ +#define AT91C_CAN_MB5_MCR ( ( AT91_REG * ) 0xFFFD02BC ) /* (CAN_MB5) MailBox Control Register */ +#define AT91C_CAN_MB5_MFID ( ( AT91_REG * ) 0xFFFD02AC ) /* (CAN_MB5) MailBox Family ID Register */ +#define AT91C_CAN_MB5_MDH ( ( AT91_REG * ) 0xFFFD02B8 ) /* (CAN_MB5) MailBox Data High Register */ +#define AT91C_CAN_MB5_MID ( ( AT91_REG * ) 0xFFFD02A8 ) /* (CAN_MB5) MailBox ID Register */ +#define AT91C_CAN_MB5_MMR ( ( AT91_REG * ) 0xFFFD02A0 ) /* (CAN_MB5) MailBox Mode Register */ +#define AT91C_CAN_MB5_MDL ( ( AT91_REG * ) 0xFFFD02B4 ) /* (CAN_MB5) MailBox Data Low Register */ +#define AT91C_CAN_MB5_MAM ( ( AT91_REG * ) 0xFFFD02A4 ) /* (CAN_MB5) MailBox Acceptance Mask Register */ +/* ========== Register definition for CAN_MB6 peripheral ========== */ +#define AT91C_CAN_MB6_MFID ( ( AT91_REG * ) 0xFFFD02CC ) /* (CAN_MB6) MailBox Family ID Register */ +#define AT91C_CAN_MB6_MID ( ( AT91_REG * ) 0xFFFD02C8 ) /* (CAN_MB6) MailBox ID Register */ +#define AT91C_CAN_MB6_MAM ( ( AT91_REG * ) 0xFFFD02C4 ) /* (CAN_MB6) MailBox Acceptance Mask Register */ +#define AT91C_CAN_MB6_MSR ( ( AT91_REG * ) 0xFFFD02D0 ) /* (CAN_MB6) MailBox Status Register */ +#define AT91C_CAN_MB6_MDL ( ( AT91_REG * ) 0xFFFD02D4 ) /* (CAN_MB6) MailBox Data Low Register */ +#define AT91C_CAN_MB6_MCR ( ( AT91_REG * ) 0xFFFD02DC ) /* (CAN_MB6) MailBox Control Register */ +#define AT91C_CAN_MB6_MDH ( ( AT91_REG * ) 0xFFFD02D8 ) /* (CAN_MB6) MailBox Data High Register */ +#define AT91C_CAN_MB6_MMR ( ( AT91_REG * ) 0xFFFD02C0 ) /* (CAN_MB6) MailBox Mode Register */ +/* ========== Register definition for CAN_MB7 peripheral ========== */ +#define AT91C_CAN_MB7_MCR ( ( AT91_REG * ) 0xFFFD02FC ) /* (CAN_MB7) MailBox Control Register */ +#define AT91C_CAN_MB7_MDH ( ( AT91_REG * ) 0xFFFD02F8 ) /* (CAN_MB7) MailBox Data High Register */ +#define AT91C_CAN_MB7_MFID ( ( AT91_REG * ) 0xFFFD02EC ) /* (CAN_MB7) MailBox Family ID Register */ +#define AT91C_CAN_MB7_MDL ( ( AT91_REG * ) 0xFFFD02F4 ) /* (CAN_MB7) MailBox Data Low Register */ +#define AT91C_CAN_MB7_MID ( ( AT91_REG * ) 0xFFFD02E8 ) /* (CAN_MB7) MailBox ID Register */ +#define AT91C_CAN_MB7_MMR ( ( AT91_REG * ) 0xFFFD02E0 ) /* (CAN_MB7) MailBox Mode Register */ +#define AT91C_CAN_MB7_MAM ( ( AT91_REG * ) 0xFFFD02E4 ) /* (CAN_MB7) MailBox Acceptance Mask Register */ +#define AT91C_CAN_MB7_MSR ( ( AT91_REG * ) 0xFFFD02F0 ) /* (CAN_MB7) MailBox Status Register */ +/* ========== Register definition for CAN peripheral ========== */ +#define AT91C_CAN_TCR ( ( AT91_REG * ) 0xFFFD0024 ) /* (CAN) Transfer Command Register */ +#define AT91C_CAN_IMR ( ( AT91_REG * ) 0xFFFD000C ) /* (CAN) Interrupt Mask Register */ +#define AT91C_CAN_IER ( ( AT91_REG * ) 0xFFFD0004 ) /* (CAN) Interrupt Enable Register */ +#define AT91C_CAN_ECR ( ( AT91_REG * ) 0xFFFD0020 ) /* (CAN) Error Counter Register */ +#define AT91C_CAN_TIMESTP ( ( AT91_REG * ) 0xFFFD001C ) /* (CAN) Time Stamp Register */ +#define AT91C_CAN_MR ( ( AT91_REG * ) 0xFFFD0000 ) /* (CAN) Mode Register */ +#define AT91C_CAN_IDR ( ( AT91_REG * ) 0xFFFD0008 ) /* (CAN) Interrupt Disable Register */ +#define AT91C_CAN_ACR ( ( AT91_REG * ) 0xFFFD0028 ) /* (CAN) Abort Command Register */ +#define AT91C_CAN_TIM ( ( AT91_REG * ) 0xFFFD0018 ) /* (CAN) Timer Register */ +#define AT91C_CAN_SR ( ( AT91_REG * ) 0xFFFD0010 ) /* (CAN) Status Register */ +#define AT91C_CAN_BR ( ( AT91_REG * ) 0xFFFD0014 ) /* (CAN) Baudrate Register */ +#define AT91C_CAN_VR ( ( AT91_REG * ) 0xFFFD00FC ) /* (CAN) Version Register */ +/* ========== Register definition for EMAC peripheral ========== */ +#define AT91C_EMAC_ISR ( ( AT91_REG * ) 0xFFFDC024 ) /* (EMAC) Interrupt Status Register */ +#define AT91C_EMAC_SA4H ( ( AT91_REG * ) 0xFFFDC0B4 ) /* (EMAC) Specific Address 4 Top, Last 2 bytes */ +#define AT91C_EMAC_SA1L ( ( AT91_REG * ) 0xFFFDC098 ) /* (EMAC) Specific Address 1 Bottom, First 4 bytes */ +#define AT91C_EMAC_ELE ( ( AT91_REG * ) 0xFFFDC078 ) /* (EMAC) Excessive Length Errors Register */ +#define AT91C_EMAC_LCOL ( ( AT91_REG * ) 0xFFFDC05C ) /* (EMAC) Late Collision Register */ +#define AT91C_EMAC_RLE ( ( AT91_REG * ) 0xFFFDC088 ) /* (EMAC) Receive Length Field Mismatch Register */ +#define AT91C_EMAC_WOL ( ( AT91_REG * ) 0xFFFDC0C4 ) /* (EMAC) Wake On LAN Register */ +#define AT91C_EMAC_DTF ( ( AT91_REG * ) 0xFFFDC058 ) /* (EMAC) Deferred Transmission Frame Register */ +#define AT91C_EMAC_TUND ( ( AT91_REG * ) 0xFFFDC064 ) /* (EMAC) Transmit Underrun Error Register */ +#define AT91C_EMAC_NCR ( ( AT91_REG * ) 0xFFFDC000 ) /* (EMAC) Network Control Register */ +#define AT91C_EMAC_SA4L ( ( AT91_REG * ) 0xFFFDC0B0 ) /* (EMAC) Specific Address 4 Bottom, First 4 bytes */ +#define AT91C_EMAC_RSR ( ( AT91_REG * ) 0xFFFDC020 ) /* (EMAC) Receive Status Register */ +#define AT91C_EMAC_SA3L ( ( AT91_REG * ) 0xFFFDC0A8 ) /* (EMAC) Specific Address 3 Bottom, First 4 bytes */ +#define AT91C_EMAC_TSR ( ( AT91_REG * ) 0xFFFDC014 ) /* (EMAC) Transmit Status Register */ +#define AT91C_EMAC_IDR ( ( AT91_REG * ) 0xFFFDC02C ) /* (EMAC) Interrupt Disable Register */ +#define AT91C_EMAC_RSE ( ( AT91_REG * ) 0xFFFDC074 ) /* (EMAC) Receive Symbol Errors Register */ +#define AT91C_EMAC_ECOL ( ( AT91_REG * ) 0xFFFDC060 ) /* (EMAC) Excessive Collision Register */ +#define AT91C_EMAC_TID ( ( AT91_REG * ) 0xFFFDC0B8 ) /* (EMAC) Type ID Checking Register */ +#define AT91C_EMAC_HRB ( ( AT91_REG * ) 0xFFFDC090 ) /* (EMAC) Hash Address Bottom[31:0] */ +#define AT91C_EMAC_TBQP ( ( AT91_REG * ) 0xFFFDC01C ) /* (EMAC) Transmit Buffer Queue Pointer */ +#define AT91C_EMAC_USRIO ( ( AT91_REG * ) 0xFFFDC0C0 ) /* (EMAC) USER Input/Output Register */ +#define AT91C_EMAC_PTR ( ( AT91_REG * ) 0xFFFDC038 ) /* (EMAC) Pause Time Register */ +#define AT91C_EMAC_SA2H ( ( AT91_REG * ) 0xFFFDC0A4 ) /* (EMAC) Specific Address 2 Top, Last 2 bytes */ +#define AT91C_EMAC_ROV ( ( AT91_REG * ) 0xFFFDC070 ) /* (EMAC) Receive Overrun Errors Register */ +#define AT91C_EMAC_ALE ( ( AT91_REG * ) 0xFFFDC054 ) /* (EMAC) Alignment Error Register */ +#define AT91C_EMAC_RJA ( ( AT91_REG * ) 0xFFFDC07C ) /* (EMAC) Receive Jabbers Register */ +#define AT91C_EMAC_RBQP ( ( AT91_REG * ) 0xFFFDC018 ) /* (EMAC) Receive Buffer Queue Pointer */ +#define AT91C_EMAC_TPF ( ( AT91_REG * ) 0xFFFDC08C ) /* (EMAC) Transmitted Pause Frames Register */ +#define AT91C_EMAC_NCFGR ( ( AT91_REG * ) 0xFFFDC004 ) /* (EMAC) Network Configuration Register */ +#define AT91C_EMAC_HRT ( ( AT91_REG * ) 0xFFFDC094 ) /* (EMAC) Hash Address Top[63:32] */ +#define AT91C_EMAC_USF ( ( AT91_REG * ) 0xFFFDC080 ) /* (EMAC) Undersize Frames Register */ +#define AT91C_EMAC_FCSE ( ( AT91_REG * ) 0xFFFDC050 ) /* (EMAC) Frame Check Sequence Error Register */ +#define AT91C_EMAC_TPQ ( ( AT91_REG * ) 0xFFFDC0BC ) /* (EMAC) Transmit Pause Quantum Register */ +#define AT91C_EMAC_MAN ( ( AT91_REG * ) 0xFFFDC034 ) /* (EMAC) PHY Maintenance Register */ +#define AT91C_EMAC_FTO ( ( AT91_REG * ) 0xFFFDC040 ) /* (EMAC) Frames Transmitted OK Register */ +#define AT91C_EMAC_REV ( ( AT91_REG * ) 0xFFFDC0FC ) /* (EMAC) Revision Register */ +#define AT91C_EMAC_IMR ( ( AT91_REG * ) 0xFFFDC030 ) /* (EMAC) Interrupt Mask Register */ +#define AT91C_EMAC_SCF ( ( AT91_REG * ) 0xFFFDC044 ) /* (EMAC) Single Collision Frame Register */ +#define AT91C_EMAC_PFR ( ( AT91_REG * ) 0xFFFDC03C ) /* (EMAC) Pause Frames received Register */ +#define AT91C_EMAC_MCF ( ( AT91_REG * ) 0xFFFDC048 ) /* (EMAC) Multiple Collision Frame Register */ +#define AT91C_EMAC_NSR ( ( AT91_REG * ) 0xFFFDC008 ) /* (EMAC) Network Status Register */ +#define AT91C_EMAC_SA2L ( ( AT91_REG * ) 0xFFFDC0A0 ) /* (EMAC) Specific Address 2 Bottom, First 4 bytes */ +#define AT91C_EMAC_FRO ( ( AT91_REG * ) 0xFFFDC04C ) /* (EMAC) Frames Received OK Register */ +#define AT91C_EMAC_IER ( ( AT91_REG * ) 0xFFFDC028 ) /* (EMAC) Interrupt Enable Register */ +#define AT91C_EMAC_SA1H ( ( AT91_REG * ) 0xFFFDC09C ) /* (EMAC) Specific Address 1 Top, Last 2 bytes */ +#define AT91C_EMAC_CSE ( ( AT91_REG * ) 0xFFFDC068 ) /* (EMAC) Carrier Sense Error Register */ +#define AT91C_EMAC_SA3H ( ( AT91_REG * ) 0xFFFDC0AC ) /* (EMAC) Specific Address 3 Top, Last 2 bytes */ +#define AT91C_EMAC_RRE ( ( AT91_REG * ) 0xFFFDC06C ) /* (EMAC) Receive Ressource Error Register */ +#define AT91C_EMAC_STE ( ( AT91_REG * ) 0xFFFDC084 ) /* (EMAC) SQE Test Error Register */ +/* ========== Register definition for PDC_ADC peripheral ========== */ +#define AT91C_ADC_PTSR ( ( AT91_REG * ) 0xFFFD8124 ) /* (PDC_ADC) PDC Transfer Status Register */ +#define AT91C_ADC_PTCR ( ( AT91_REG * ) 0xFFFD8120 ) /* (PDC_ADC) PDC Transfer Control Register */ +#define AT91C_ADC_TNPR ( ( AT91_REG * ) 0xFFFD8118 ) /* (PDC_ADC) Transmit Next Pointer Register */ +#define AT91C_ADC_TNCR ( ( AT91_REG * ) 0xFFFD811C ) /* (PDC_ADC) Transmit Next Counter Register */ +#define AT91C_ADC_RNPR ( ( AT91_REG * ) 0xFFFD8110 ) /* (PDC_ADC) Receive Next Pointer Register */ +#define AT91C_ADC_RNCR ( ( AT91_REG * ) 0xFFFD8114 ) /* (PDC_ADC) Receive Next Counter Register */ +#define AT91C_ADC_RPR ( ( AT91_REG * ) 0xFFFD8100 ) /* (PDC_ADC) Receive Pointer Register */ +#define AT91C_ADC_TCR ( ( AT91_REG * ) 0xFFFD810C ) /* (PDC_ADC) Transmit Counter Register */ +#define AT91C_ADC_TPR ( ( AT91_REG * ) 0xFFFD8108 ) /* (PDC_ADC) Transmit Pointer Register */ +#define AT91C_ADC_RCR ( ( AT91_REG * ) 0xFFFD8104 ) /* (PDC_ADC) Receive Counter Register */ +/* ========== Register definition for ADC peripheral ========== */ +#define AT91C_ADC_CDR2 ( ( AT91_REG * ) 0xFFFD8038 ) /* (ADC) ADC Channel Data Register 2 */ +#define AT91C_ADC_CDR3 ( ( AT91_REG * ) 0xFFFD803C ) /* (ADC) ADC Channel Data Register 3 */ +#define AT91C_ADC_CDR0 ( ( AT91_REG * ) 0xFFFD8030 ) /* (ADC) ADC Channel Data Register 0 */ +#define AT91C_ADC_CDR5 ( ( AT91_REG * ) 0xFFFD8044 ) /* (ADC) ADC Channel Data Register 5 */ +#define AT91C_ADC_CHDR ( ( AT91_REG * ) 0xFFFD8014 ) /* (ADC) ADC Channel Disable Register */ +#define AT91C_ADC_SR ( ( AT91_REG * ) 0xFFFD801C ) /* (ADC) ADC Status Register */ +#define AT91C_ADC_CDR4 ( ( AT91_REG * ) 0xFFFD8040 ) /* (ADC) ADC Channel Data Register 4 */ +#define AT91C_ADC_CDR1 ( ( AT91_REG * ) 0xFFFD8034 ) /* (ADC) ADC Channel Data Register 1 */ +#define AT91C_ADC_LCDR ( ( AT91_REG * ) 0xFFFD8020 ) /* (ADC) ADC Last Converted Data Register */ +#define AT91C_ADC_IDR ( ( AT91_REG * ) 0xFFFD8028 ) /* (ADC) ADC Interrupt Disable Register */ +#define AT91C_ADC_CR ( ( AT91_REG * ) 0xFFFD8000 ) /* (ADC) ADC Control Register */ +#define AT91C_ADC_CDR7 ( ( AT91_REG * ) 0xFFFD804C ) /* (ADC) ADC Channel Data Register 7 */ +#define AT91C_ADC_CDR6 ( ( AT91_REG * ) 0xFFFD8048 ) /* (ADC) ADC Channel Data Register 6 */ +#define AT91C_ADC_IER ( ( AT91_REG * ) 0xFFFD8024 ) /* (ADC) ADC Interrupt Enable Register */ +#define AT91C_ADC_CHER ( ( AT91_REG * ) 0xFFFD8010 ) /* (ADC) ADC Channel Enable Register */ +#define AT91C_ADC_CHSR ( ( AT91_REG * ) 0xFFFD8018 ) /* (ADC) ADC Channel Status Register */ +#define AT91C_ADC_MR ( ( AT91_REG * ) 0xFFFD8004 ) /* (ADC) ADC Mode Register */ +#define AT91C_ADC_IMR ( ( AT91_REG * ) 0xFFFD802C ) /* (ADC) ADC Interrupt Mask Register */ +/* ========== Register definition for PDC_AES peripheral ========== */ +#define AT91C_AES_TPR ( ( AT91_REG * ) 0xFFFA4108 ) /* (PDC_AES) Transmit Pointer Register */ +#define AT91C_AES_PTCR ( ( AT91_REG * ) 0xFFFA4120 ) /* (PDC_AES) PDC Transfer Control Register */ +#define AT91C_AES_RNPR ( ( AT91_REG * ) 0xFFFA4110 ) /* (PDC_AES) Receive Next Pointer Register */ +#define AT91C_AES_TNCR ( ( AT91_REG * ) 0xFFFA411C ) /* (PDC_AES) Transmit Next Counter Register */ +#define AT91C_AES_TCR ( ( AT91_REG * ) 0xFFFA410C ) /* (PDC_AES) Transmit Counter Register */ +#define AT91C_AES_RCR ( ( AT91_REG * ) 0xFFFA4104 ) /* (PDC_AES) Receive Counter Register */ +#define AT91C_AES_RNCR ( ( AT91_REG * ) 0xFFFA4114 ) /* (PDC_AES) Receive Next Counter Register */ +#define AT91C_AES_TNPR ( ( AT91_REG * ) 0xFFFA4118 ) /* (PDC_AES) Transmit Next Pointer Register */ +#define AT91C_AES_RPR ( ( AT91_REG * ) 0xFFFA4100 ) /* (PDC_AES) Receive Pointer Register */ +#define AT91C_AES_PTSR ( ( AT91_REG * ) 0xFFFA4124 ) /* (PDC_AES) PDC Transfer Status Register */ +/* ========== Register definition for AES peripheral ========== */ +#define AT91C_AES_IVxR ( ( AT91_REG * ) 0xFFFA4060 ) /* (AES) Initialization Vector x Register */ +#define AT91C_AES_MR ( ( AT91_REG * ) 0xFFFA4004 ) /* (AES) Mode Register */ +#define AT91C_AES_VR ( ( AT91_REG * ) 0xFFFA40FC ) /* (AES) AES Version Register */ +#define AT91C_AES_ODATAxR ( ( AT91_REG * ) 0xFFFA4050 ) /* (AES) Output Data x Register */ +#define AT91C_AES_IDATAxR ( ( AT91_REG * ) 0xFFFA4040 ) /* (AES) Input Data x Register */ +#define AT91C_AES_CR ( ( AT91_REG * ) 0xFFFA4000 ) /* (AES) Control Register */ +#define AT91C_AES_IDR ( ( AT91_REG * ) 0xFFFA4014 ) /* (AES) Interrupt Disable Register */ +#define AT91C_AES_IMR ( ( AT91_REG * ) 0xFFFA4018 ) /* (AES) Interrupt Mask Register */ +#define AT91C_AES_IER ( ( AT91_REG * ) 0xFFFA4010 ) /* (AES) Interrupt Enable Register */ +#define AT91C_AES_KEYWxR ( ( AT91_REG * ) 0xFFFA4020 ) /* (AES) Key Word x Register */ +#define AT91C_AES_ISR ( ( AT91_REG * ) 0xFFFA401C ) /* (AES) Interrupt Status Register */ +/* ========== Register definition for PDC_TDES peripheral ========== */ +#define AT91C_TDES_RNCR ( ( AT91_REG * ) 0xFFFA8114 ) /* (PDC_TDES) Receive Next Counter Register */ +#define AT91C_TDES_TCR ( ( AT91_REG * ) 0xFFFA810C ) /* (PDC_TDES) Transmit Counter Register */ +#define AT91C_TDES_RCR ( ( AT91_REG * ) 0xFFFA8104 ) /* (PDC_TDES) Receive Counter Register */ +#define AT91C_TDES_TNPR ( ( AT91_REG * ) 0xFFFA8118 ) /* (PDC_TDES) Transmit Next Pointer Register */ +#define AT91C_TDES_RNPR ( ( AT91_REG * ) 0xFFFA8110 ) /* (PDC_TDES) Receive Next Pointer Register */ +#define AT91C_TDES_RPR ( ( AT91_REG * ) 0xFFFA8100 ) /* (PDC_TDES) Receive Pointer Register */ +#define AT91C_TDES_TNCR ( ( AT91_REG * ) 0xFFFA811C ) /* (PDC_TDES) Transmit Next Counter Register */ +#define AT91C_TDES_TPR ( ( AT91_REG * ) 0xFFFA8108 ) /* (PDC_TDES) Transmit Pointer Register */ +#define AT91C_TDES_PTSR ( ( AT91_REG * ) 0xFFFA8124 ) /* (PDC_TDES) PDC Transfer Status Register */ +#define AT91C_TDES_PTCR ( ( AT91_REG * ) 0xFFFA8120 ) /* (PDC_TDES) PDC Transfer Control Register */ +/* ========== Register definition for TDES peripheral ========== */ +#define AT91C_TDES_KEY2WxR ( ( AT91_REG * ) 0xFFFA8028 ) /* (TDES) Key 2 Word x Register */ +#define AT91C_TDES_KEY3WxR ( ( AT91_REG * ) 0xFFFA8030 ) /* (TDES) Key 3 Word x Register */ +#define AT91C_TDES_IDR ( ( AT91_REG * ) 0xFFFA8014 ) /* (TDES) Interrupt Disable Register */ +#define AT91C_TDES_VR ( ( AT91_REG * ) 0xFFFA80FC ) /* (TDES) TDES Version Register */ +#define AT91C_TDES_IVxR ( ( AT91_REG * ) 0xFFFA8060 ) /* (TDES) Initialization Vector x Register */ +#define AT91C_TDES_ODATAxR ( ( AT91_REG * ) 0xFFFA8050 ) /* (TDES) Output Data x Register */ +#define AT91C_TDES_IMR ( ( AT91_REG * ) 0xFFFA8018 ) /* (TDES) Interrupt Mask Register */ +#define AT91C_TDES_MR ( ( AT91_REG * ) 0xFFFA8004 ) /* (TDES) Mode Register */ +#define AT91C_TDES_CR ( ( AT91_REG * ) 0xFFFA8000 ) /* (TDES) Control Register */ +#define AT91C_TDES_IER ( ( AT91_REG * ) 0xFFFA8010 ) /* (TDES) Interrupt Enable Register */ +#define AT91C_TDES_ISR ( ( AT91_REG * ) 0xFFFA801C ) /* (TDES) Interrupt Status Register */ +#define AT91C_TDES_IDATAxR ( ( AT91_REG * ) 0xFFFA8040 ) /* (TDES) Input Data x Register */ +#define AT91C_TDES_KEY1WxR ( ( AT91_REG * ) 0xFFFA8020 ) /* (TDES) Key 1 Word x Register */ -// ***************************************************************************** -// PIO DEFINITIONS FOR AT91SAM7X256 -// ***************************************************************************** -#define AT91C_PIO_PA0 ((unsigned int) 1 << 0) // Pin Controlled by PA0 -#define AT91C_PA0_RXD0 ((unsigned int) AT91C_PIO_PA0) // USART 0 Receive Data -#define AT91C_PIO_PA1 ((unsigned int) 1 << 1) // Pin Controlled by PA1 -#define AT91C_PA1_TXD0 ((unsigned int) AT91C_PIO_PA1) // USART 0 Transmit Data -#define AT91C_PIO_PA10 ((unsigned int) 1 << 10) // Pin Controlled by PA10 -#define AT91C_PA10_TWD ((unsigned int) AT91C_PIO_PA10) // TWI Two-wire Serial Data -#define AT91C_PIO_PA11 ((unsigned int) 1 << 11) // Pin Controlled by PA11 -#define AT91C_PA11_TWCK ((unsigned int) AT91C_PIO_PA11) // TWI Two-wire Serial Clock -#define AT91C_PIO_PA12 ((unsigned int) 1 << 12) // Pin Controlled by PA12 -#define AT91C_PA12_NPCS00 ((unsigned int) AT91C_PIO_PA12) // SPI 0 Peripheral Chip Select 0 -#define AT91C_PIO_PA13 ((unsigned int) 1 << 13) // Pin Controlled by PA13 -#define AT91C_PA13_NPCS01 ((unsigned int) AT91C_PIO_PA13) // SPI 0 Peripheral Chip Select 1 -#define AT91C_PA13_PCK1 ((unsigned int) AT91C_PIO_PA13) // PMC Programmable Clock Output 1 -#define AT91C_PIO_PA14 ((unsigned int) 1 << 14) // Pin Controlled by PA14 -#define AT91C_PA14_NPCS02 ((unsigned int) AT91C_PIO_PA14) // SPI 0 Peripheral Chip Select 2 -#define AT91C_PA14_IRQ1 ((unsigned int) AT91C_PIO_PA14) // External Interrupt 1 -#define AT91C_PIO_PA15 ((unsigned int) 1 << 15) // Pin Controlled by PA15 -#define AT91C_PA15_NPCS03 ((unsigned int) AT91C_PIO_PA15) // SPI 0 Peripheral Chip Select 3 -#define AT91C_PA15_TCLK2 ((unsigned int) AT91C_PIO_PA15) // Timer Counter 2 external clock input -#define AT91C_PIO_PA16 ((unsigned int) 1 << 16) // Pin Controlled by PA16 -#define AT91C_PA16_MISO0 ((unsigned int) AT91C_PIO_PA16) // SPI 0 Master In Slave -#define AT91C_PIO_PA17 ((unsigned int) 1 << 17) // Pin Controlled by PA17 -#define AT91C_PA17_MOSI0 ((unsigned int) AT91C_PIO_PA17) // SPI 0 Master Out Slave -#define AT91C_PIO_PA18 ((unsigned int) 1 << 18) // Pin Controlled by PA18 -#define AT91C_PA18_SPCK0 ((unsigned int) AT91C_PIO_PA18) // SPI 0 Serial Clock -#define AT91C_PIO_PA19 ((unsigned int) 1 << 19) // Pin Controlled by PA19 -#define AT91C_PA19_CANRX ((unsigned int) AT91C_PIO_PA19) // CAN Receive -#define AT91C_PIO_PA2 ((unsigned int) 1 << 2) // Pin Controlled by PA2 -#define AT91C_PA2_SCK0 ((unsigned int) AT91C_PIO_PA2) // USART 0 Serial Clock -#define AT91C_PA2_NPCS11 ((unsigned int) AT91C_PIO_PA2) // SPI 1 Peripheral Chip Select 1 -#define AT91C_PIO_PA20 ((unsigned int) 1 << 20) // Pin Controlled by PA20 -#define AT91C_PA20_CANTX ((unsigned int) AT91C_PIO_PA20) // CAN Transmit -#define AT91C_PIO_PA21 ((unsigned int) 1 << 21) // Pin Controlled by PA21 -#define AT91C_PA21_TF ((unsigned int) AT91C_PIO_PA21) // SSC Transmit Frame Sync -#define AT91C_PA21_NPCS10 ((unsigned int) AT91C_PIO_PA21) // SPI 1 Peripheral Chip Select 0 -#define AT91C_PIO_PA22 ((unsigned int) 1 << 22) // Pin Controlled by PA22 -#define AT91C_PA22_TK ((unsigned int) AT91C_PIO_PA22) // SSC Transmit Clock -#define AT91C_PA22_SPCK1 ((unsigned int) AT91C_PIO_PA22) // SPI 1 Serial Clock -#define AT91C_PIO_PA23 ((unsigned int) 1 << 23) // Pin Controlled by PA23 -#define AT91C_PA23_TD ((unsigned int) AT91C_PIO_PA23) // SSC Transmit data -#define AT91C_PA23_MOSI1 ((unsigned int) AT91C_PIO_PA23) // SPI 1 Master Out Slave -#define AT91C_PIO_PA24 ((unsigned int) 1 << 24) // Pin Controlled by PA24 -#define AT91C_PA24_RD ((unsigned int) AT91C_PIO_PA24) // SSC Receive Data -#define AT91C_PA24_MISO1 ((unsigned int) AT91C_PIO_PA24) // SPI 1 Master In Slave -#define AT91C_PIO_PA25 ((unsigned int) 1 << 25) // Pin Controlled by PA25 -#define AT91C_PA25_RK ((unsigned int) AT91C_PIO_PA25) // SSC Receive Clock -#define AT91C_PA25_NPCS11 ((unsigned int) AT91C_PIO_PA25) // SPI 1 Peripheral Chip Select 1 -#define AT91C_PIO_PA26 ((unsigned int) 1 << 26) // Pin Controlled by PA26 -#define AT91C_PA26_RF ((unsigned int) AT91C_PIO_PA26) // SSC Receive Frame Sync -#define AT91C_PA26_NPCS12 ((unsigned int) AT91C_PIO_PA26) // SPI 1 Peripheral Chip Select 2 -#define AT91C_PIO_PA27 ((unsigned int) 1 << 27) // Pin Controlled by PA27 -#define AT91C_PA27_DRXD ((unsigned int) AT91C_PIO_PA27) // DBGU Debug Receive Data -#define AT91C_PA27_PCK3 ((unsigned int) AT91C_PIO_PA27) // PMC Programmable Clock Output 3 -#define AT91C_PIO_PA28 ((unsigned int) 1 << 28) // Pin Controlled by PA28 -#define AT91C_PA28_DTXD ((unsigned int) AT91C_PIO_PA28) // DBGU Debug Transmit Data -#define AT91C_PIO_PA29 ((unsigned int) 1 << 29) // Pin Controlled by PA29 -#define AT91C_PA29_FIQ ((unsigned int) AT91C_PIO_PA29) // AIC Fast Interrupt Input -#define AT91C_PA29_NPCS13 ((unsigned int) AT91C_PIO_PA29) // SPI 1 Peripheral Chip Select 3 -#define AT91C_PIO_PA3 ((unsigned int) 1 << 3) // Pin Controlled by PA3 -#define AT91C_PA3_RTS0 ((unsigned int) AT91C_PIO_PA3) // USART 0 Ready To Send -#define AT91C_PA3_NPCS12 ((unsigned int) AT91C_PIO_PA3) // SPI 1 Peripheral Chip Select 2 -#define AT91C_PIO_PA30 ((unsigned int) 1 << 30) // Pin Controlled by PA30 -#define AT91C_PA30_IRQ0 ((unsigned int) AT91C_PIO_PA30) // External Interrupt 0 -#define AT91C_PA30_PCK2 ((unsigned int) AT91C_PIO_PA30) // PMC Programmable Clock Output 2 -#define AT91C_PIO_PA4 ((unsigned int) 1 << 4) // Pin Controlled by PA4 -#define AT91C_PA4_CTS0 ((unsigned int) AT91C_PIO_PA4) // USART 0 Clear To Send -#define AT91C_PA4_NPCS13 ((unsigned int) AT91C_PIO_PA4) // SPI 1 Peripheral Chip Select 3 -#define AT91C_PIO_PA5 ((unsigned int) 1 << 5) // Pin Controlled by PA5 -#define AT91C_PA5_RXD1 ((unsigned int) AT91C_PIO_PA5) // USART 1 Receive Data -#define AT91C_PIO_PA6 ((unsigned int) 1 << 6) // Pin Controlled by PA6 -#define AT91C_PA6_TXD1 ((unsigned int) AT91C_PIO_PA6) // USART 1 Transmit Data -#define AT91C_PIO_PA7 ((unsigned int) 1 << 7) // Pin Controlled by PA7 -#define AT91C_PA7_SCK1 ((unsigned int) AT91C_PIO_PA7) // USART 1 Serial Clock -#define AT91C_PA7_NPCS01 ((unsigned int) AT91C_PIO_PA7) // SPI 0 Peripheral Chip Select 1 -#define AT91C_PIO_PA8 ((unsigned int) 1 << 8) // Pin Controlled by PA8 -#define AT91C_PA8_RTS1 ((unsigned int) AT91C_PIO_PA8) // USART 1 Ready To Send -#define AT91C_PA8_NPCS02 ((unsigned int) AT91C_PIO_PA8) // SPI 0 Peripheral Chip Select 2 -#define AT91C_PIO_PA9 ((unsigned int) 1 << 9) // Pin Controlled by PA9 -#define AT91C_PA9_CTS1 ((unsigned int) AT91C_PIO_PA9) // USART 1 Clear To Send -#define AT91C_PA9_NPCS03 ((unsigned int) AT91C_PIO_PA9) // SPI 0 Peripheral Chip Select 3 -#define AT91C_PIO_PB0 ((unsigned int) 1 << 0) // Pin Controlled by PB0 -#define AT91C_PB0_ETXCK_EREFCK ((unsigned int) AT91C_PIO_PB0) // Ethernet MAC Transmit Clock/Reference Clock -#define AT91C_PB0_PCK0 ((unsigned int) AT91C_PIO_PB0) // PMC Programmable Clock Output 0 -#define AT91C_PIO_PB1 ((unsigned int) 1 << 1) // Pin Controlled by PB1 -#define AT91C_PB1_ETXEN ((unsigned int) AT91C_PIO_PB1) // Ethernet MAC Transmit Enable -#define AT91C_PIO_PB10 ((unsigned int) 1 << 10) // Pin Controlled by PB10 -#define AT91C_PB10_ETX2 ((unsigned int) AT91C_PIO_PB10) // Ethernet MAC Transmit Data 2 -#define AT91C_PB10_NPCS11 ((unsigned int) AT91C_PIO_PB10) // SPI 1 Peripheral Chip Select 1 -#define AT91C_PIO_PB11 ((unsigned int) 1 << 11) // Pin Controlled by PB11 -#define AT91C_PB11_ETX3 ((unsigned int) AT91C_PIO_PB11) // Ethernet MAC Transmit Data 3 -#define AT91C_PB11_NPCS12 ((unsigned int) AT91C_PIO_PB11) // SPI 1 Peripheral Chip Select 2 -#define AT91C_PIO_PB12 ((unsigned int) 1 << 12) // Pin Controlled by PB12 -#define AT91C_PB12_ETXER ((unsigned int) AT91C_PIO_PB12) // Ethernet MAC Transmikt Coding Error -#define AT91C_PB12_TCLK0 ((unsigned int) AT91C_PIO_PB12) // Timer Counter 0 external clock input -#define AT91C_PIO_PB13 ((unsigned int) 1 << 13) // Pin Controlled by PB13 -#define AT91C_PB13_ERX2 ((unsigned int) AT91C_PIO_PB13) // Ethernet MAC Receive Data 2 -#define AT91C_PB13_NPCS01 ((unsigned int) AT91C_PIO_PB13) // SPI 0 Peripheral Chip Select 1 -#define AT91C_PIO_PB14 ((unsigned int) 1 << 14) // Pin Controlled by PB14 -#define AT91C_PB14_ERX3 ((unsigned int) AT91C_PIO_PB14) // Ethernet MAC Receive Data 3 -#define AT91C_PB14_NPCS02 ((unsigned int) AT91C_PIO_PB14) // SPI 0 Peripheral Chip Select 2 -#define AT91C_PIO_PB15 ((unsigned int) 1 << 15) // Pin Controlled by PB15 -#define AT91C_PB15_ERXDV ((unsigned int) AT91C_PIO_PB15) // Ethernet MAC Receive Data Valid -#define AT91C_PIO_PB16 ((unsigned int) 1 << 16) // Pin Controlled by PB16 -#define AT91C_PB16_ECOL ((unsigned int) AT91C_PIO_PB16) // Ethernet MAC Collision Detected -#define AT91C_PB16_NPCS13 ((unsigned int) AT91C_PIO_PB16) // SPI 1 Peripheral Chip Select 3 -#define AT91C_PIO_PB17 ((unsigned int) 1 << 17) // Pin Controlled by PB17 -#define AT91C_PB17_ERXCK ((unsigned int) AT91C_PIO_PB17) // Ethernet MAC Receive Clock -#define AT91C_PB17_NPCS03 ((unsigned int) AT91C_PIO_PB17) // SPI 0 Peripheral Chip Select 3 -#define AT91C_PIO_PB18 ((unsigned int) 1 << 18) // Pin Controlled by PB18 -#define AT91C_PB18_EF100 ((unsigned int) AT91C_PIO_PB18) // Ethernet MAC Force 100 Mbits/sec -#define AT91C_PB18_ADTRG ((unsigned int) AT91C_PIO_PB18) // ADC External Trigger -#define AT91C_PIO_PB19 ((unsigned int) 1 << 19) // Pin Controlled by PB19 -#define AT91C_PB19_PWM0 ((unsigned int) AT91C_PIO_PB19) // PWM Channel 0 -#define AT91C_PB19_TCLK1 ((unsigned int) AT91C_PIO_PB19) // Timer Counter 1 external clock input -#define AT91C_PIO_PB2 ((unsigned int) 1 << 2) // Pin Controlled by PB2 -#define AT91C_PB2_ETX0 ((unsigned int) AT91C_PIO_PB2) // Ethernet MAC Transmit Data 0 -#define AT91C_PIO_PB20 ((unsigned int) 1 << 20) // Pin Controlled by PB20 -#define AT91C_PB20_PWM1 ((unsigned int) AT91C_PIO_PB20) // PWM Channel 1 -#define AT91C_PB20_PCK0 ((unsigned int) AT91C_PIO_PB20) // PMC Programmable Clock Output 0 -#define AT91C_PIO_PB21 ((unsigned int) 1 << 21) // Pin Controlled by PB21 -#define AT91C_PB21_PWM2 ((unsigned int) AT91C_PIO_PB21) // PWM Channel 2 -#define AT91C_PB21_PCK1 ((unsigned int) AT91C_PIO_PB21) // PMC Programmable Clock Output 1 -#define AT91C_PIO_PB22 ((unsigned int) 1 << 22) // Pin Controlled by PB22 -#define AT91C_PB22_PWM3 ((unsigned int) AT91C_PIO_PB22) // PWM Channel 3 -#define AT91C_PB22_PCK2 ((unsigned int) AT91C_PIO_PB22) // PMC Programmable Clock Output 2 -#define AT91C_PIO_PB23 ((unsigned int) 1 << 23) // Pin Controlled by PB23 -#define AT91C_PB23_TIOA0 ((unsigned int) AT91C_PIO_PB23) // Timer Counter 0 Multipurpose Timer I/O Pin A -#define AT91C_PB23_DCD1 ((unsigned int) AT91C_PIO_PB23) // USART 1 Data Carrier Detect -#define AT91C_PIO_PB24 ((unsigned int) 1 << 24) // Pin Controlled by PB24 -#define AT91C_PB24_TIOB0 ((unsigned int) AT91C_PIO_PB24) // Timer Counter 0 Multipurpose Timer I/O Pin B -#define AT91C_PB24_DSR1 ((unsigned int) AT91C_PIO_PB24) // USART 1 Data Set ready -#define AT91C_PIO_PB25 ((unsigned int) 1 << 25) // Pin Controlled by PB25 -#define AT91C_PB25_TIOA1 ((unsigned int) AT91C_PIO_PB25) // Timer Counter 1 Multipurpose Timer I/O Pin A -#define AT91C_PB25_DTR1 ((unsigned int) AT91C_PIO_PB25) // USART 1 Data Terminal ready -#define AT91C_PIO_PB26 ((unsigned int) 1 << 26) // Pin Controlled by PB26 -#define AT91C_PB26_TIOB1 ((unsigned int) AT91C_PIO_PB26) // Timer Counter 1 Multipurpose Timer I/O Pin B -#define AT91C_PB26_RI1 ((unsigned int) AT91C_PIO_PB26) // USART 1 Ring Indicator -#define AT91C_PIO_PB27 ((unsigned int) 1 << 27) // Pin Controlled by PB27 -#define AT91C_PB27_TIOA2 ((unsigned int) AT91C_PIO_PB27) // Timer Counter 2 Multipurpose Timer I/O Pin A -#define AT91C_PB27_PWM0 ((unsigned int) AT91C_PIO_PB27) // PWM Channel 0 -#define AT91C_PIO_PB28 ((unsigned int) 1 << 28) // Pin Controlled by PB28 -#define AT91C_PB28_TIOB2 ((unsigned int) AT91C_PIO_PB28) // Timer Counter 2 Multipurpose Timer I/O Pin B -#define AT91C_PB28_PWM1 ((unsigned int) AT91C_PIO_PB28) // PWM Channel 1 -#define AT91C_PIO_PB29 ((unsigned int) 1 << 29) // Pin Controlled by PB29 -#define AT91C_PB29_PCK1 ((unsigned int) AT91C_PIO_PB29) // PMC Programmable Clock Output 1 -#define AT91C_PB29_PWM2 ((unsigned int) AT91C_PIO_PB29) // PWM Channel 2 -#define AT91C_PIO_PB3 ((unsigned int) 1 << 3) // Pin Controlled by PB3 -#define AT91C_PB3_ETX1 ((unsigned int) AT91C_PIO_PB3) // Ethernet MAC Transmit Data 1 -#define AT91C_PIO_PB30 ((unsigned int) 1 << 30) // Pin Controlled by PB30 -#define AT91C_PB30_PCK2 ((unsigned int) AT91C_PIO_PB30) // PMC Programmable Clock Output 2 -#define AT91C_PB30_PWM3 ((unsigned int) AT91C_PIO_PB30) // PWM Channel 3 -#define AT91C_PIO_PB4 ((unsigned int) 1 << 4) // Pin Controlled by PB4 -#define AT91C_PB4_ECRS_ECRSDV ((unsigned int) AT91C_PIO_PB4) // Ethernet MAC Carrier Sense/Carrier Sense and Data Valid -#define AT91C_PIO_PB5 ((unsigned int) 1 << 5) // Pin Controlled by PB5 -#define AT91C_PB5_ERX0 ((unsigned int) AT91C_PIO_PB5) // Ethernet MAC Receive Data 0 -#define AT91C_PIO_PB6 ((unsigned int) 1 << 6) // Pin Controlled by PB6 -#define AT91C_PB6_ERX1 ((unsigned int) AT91C_PIO_PB6) // Ethernet MAC Receive Data 1 -#define AT91C_PIO_PB7 ((unsigned int) 1 << 7) // Pin Controlled by PB7 -#define AT91C_PB7_ERXER ((unsigned int) AT91C_PIO_PB7) // Ethernet MAC Receive Error -#define AT91C_PIO_PB8 ((unsigned int) 1 << 8) // Pin Controlled by PB8 -#define AT91C_PB8_EMDC ((unsigned int) AT91C_PIO_PB8) // Ethernet MAC Management Data Clock -#define AT91C_PIO_PB9 ((unsigned int) 1 << 9) // Pin Controlled by PB9 -#define AT91C_PB9_EMDIO ((unsigned int) AT91C_PIO_PB9) // Ethernet MAC Management Data Input/Output +/* ***************************************************************************** */ +/* PIO DEFINITIONS FOR AT91SAM7X256 */ +/* ***************************************************************************** */ +#define AT91C_PIO_PA0 ( ( unsigned int ) 1 << 0 ) /* Pin Controlled by PA0 */ +#define AT91C_PA0_RXD0 ( ( unsigned int ) AT91C_PIO_PA0 ) /* USART 0 Receive Data */ +#define AT91C_PIO_PA1 ( ( unsigned int ) 1 << 1 ) /* Pin Controlled by PA1 */ +#define AT91C_PA1_TXD0 ( ( unsigned int ) AT91C_PIO_PA1 ) /* USART 0 Transmit Data */ +#define AT91C_PIO_PA10 ( ( unsigned int ) 1 << 10 ) /* Pin Controlled by PA10 */ +#define AT91C_PA10_TWD ( ( unsigned int ) AT91C_PIO_PA10 ) /* TWI Two-wire Serial Data */ +#define AT91C_PIO_PA11 ( ( unsigned int ) 1 << 11 ) /* Pin Controlled by PA11 */ +#define AT91C_PA11_TWCK ( ( unsigned int ) AT91C_PIO_PA11 ) /* TWI Two-wire Serial Clock */ +#define AT91C_PIO_PA12 ( ( unsigned int ) 1 << 12 ) /* Pin Controlled by PA12 */ +#define AT91C_PA12_NPCS00 ( ( unsigned int ) AT91C_PIO_PA12 ) /* SPI 0 Peripheral Chip Select 0 */ +#define AT91C_PIO_PA13 ( ( unsigned int ) 1 << 13 ) /* Pin Controlled by PA13 */ +#define AT91C_PA13_NPCS01 ( ( unsigned int ) AT91C_PIO_PA13 ) /* SPI 0 Peripheral Chip Select 1 */ +#define AT91C_PA13_PCK1 ( ( unsigned int ) AT91C_PIO_PA13 ) /* PMC Programmable Clock Output 1 */ +#define AT91C_PIO_PA14 ( ( unsigned int ) 1 << 14 ) /* Pin Controlled by PA14 */ +#define AT91C_PA14_NPCS02 ( ( unsigned int ) AT91C_PIO_PA14 ) /* SPI 0 Peripheral Chip Select 2 */ +#define AT91C_PA14_IRQ1 ( ( unsigned int ) AT91C_PIO_PA14 ) /* External Interrupt 1 */ +#define AT91C_PIO_PA15 ( ( unsigned int ) 1 << 15 ) /* Pin Controlled by PA15 */ +#define AT91C_PA15_NPCS03 ( ( unsigned int ) AT91C_PIO_PA15 ) /* SPI 0 Peripheral Chip Select 3 */ +#define AT91C_PA15_TCLK2 ( ( unsigned int ) AT91C_PIO_PA15 ) /* Timer Counter 2 external clock input */ +#define AT91C_PIO_PA16 ( ( unsigned int ) 1 << 16 ) /* Pin Controlled by PA16 */ +#define AT91C_PA16_MISO0 ( ( unsigned int ) AT91C_PIO_PA16 ) /* SPI 0 Master In Slave */ +#define AT91C_PIO_PA17 ( ( unsigned int ) 1 << 17 ) /* Pin Controlled by PA17 */ +#define AT91C_PA17_MOSI0 ( ( unsigned int ) AT91C_PIO_PA17 ) /* SPI 0 Master Out Slave */ +#define AT91C_PIO_PA18 ( ( unsigned int ) 1 << 18 ) /* Pin Controlled by PA18 */ +#define AT91C_PA18_SPCK0 ( ( unsigned int ) AT91C_PIO_PA18 ) /* SPI 0 Serial Clock */ +#define AT91C_PIO_PA19 ( ( unsigned int ) 1 << 19 ) /* Pin Controlled by PA19 */ +#define AT91C_PA19_CANRX ( ( unsigned int ) AT91C_PIO_PA19 ) /* CAN Receive */ +#define AT91C_PIO_PA2 ( ( unsigned int ) 1 << 2 ) /* Pin Controlled by PA2 */ +#define AT91C_PA2_SCK0 ( ( unsigned int ) AT91C_PIO_PA2 ) /* USART 0 Serial Clock */ +#define AT91C_PA2_NPCS11 ( ( unsigned int ) AT91C_PIO_PA2 ) /* SPI 1 Peripheral Chip Select 1 */ +#define AT91C_PIO_PA20 ( ( unsigned int ) 1 << 20 ) /* Pin Controlled by PA20 */ +#define AT91C_PA20_CANTX ( ( unsigned int ) AT91C_PIO_PA20 ) /* CAN Transmit */ +#define AT91C_PIO_PA21 ( ( unsigned int ) 1 << 21 ) /* Pin Controlled by PA21 */ +#define AT91C_PA21_TF ( ( unsigned int ) AT91C_PIO_PA21 ) /* SSC Transmit Frame Sync */ +#define AT91C_PA21_NPCS10 ( ( unsigned int ) AT91C_PIO_PA21 ) /* SPI 1 Peripheral Chip Select 0 */ +#define AT91C_PIO_PA22 ( ( unsigned int ) 1 << 22 ) /* Pin Controlled by PA22 */ +#define AT91C_PA22_TK ( ( unsigned int ) AT91C_PIO_PA22 ) /* SSC Transmit Clock */ +#define AT91C_PA22_SPCK1 ( ( unsigned int ) AT91C_PIO_PA22 ) /* SPI 1 Serial Clock */ +#define AT91C_PIO_PA23 ( ( unsigned int ) 1 << 23 ) /* Pin Controlled by PA23 */ +#define AT91C_PA23_TD ( ( unsigned int ) AT91C_PIO_PA23 ) /* SSC Transmit data */ +#define AT91C_PA23_MOSI1 ( ( unsigned int ) AT91C_PIO_PA23 ) /* SPI 1 Master Out Slave */ +#define AT91C_PIO_PA24 ( ( unsigned int ) 1 << 24 ) /* Pin Controlled by PA24 */ +#define AT91C_PA24_RD ( ( unsigned int ) AT91C_PIO_PA24 ) /* SSC Receive Data */ +#define AT91C_PA24_MISO1 ( ( unsigned int ) AT91C_PIO_PA24 ) /* SPI 1 Master In Slave */ +#define AT91C_PIO_PA25 ( ( unsigned int ) 1 << 25 ) /* Pin Controlled by PA25 */ +#define AT91C_PA25_RK ( ( unsigned int ) AT91C_PIO_PA25 ) /* SSC Receive Clock */ +#define AT91C_PA25_NPCS11 ( ( unsigned int ) AT91C_PIO_PA25 ) /* SPI 1 Peripheral Chip Select 1 */ +#define AT91C_PIO_PA26 ( ( unsigned int ) 1 << 26 ) /* Pin Controlled by PA26 */ +#define AT91C_PA26_RF ( ( unsigned int ) AT91C_PIO_PA26 ) /* SSC Receive Frame Sync */ +#define AT91C_PA26_NPCS12 ( ( unsigned int ) AT91C_PIO_PA26 ) /* SPI 1 Peripheral Chip Select 2 */ +#define AT91C_PIO_PA27 ( ( unsigned int ) 1 << 27 ) /* Pin Controlled by PA27 */ +#define AT91C_PA27_DRXD ( ( unsigned int ) AT91C_PIO_PA27 ) /* DBGU Debug Receive Data */ +#define AT91C_PA27_PCK3 ( ( unsigned int ) AT91C_PIO_PA27 ) /* PMC Programmable Clock Output 3 */ +#define AT91C_PIO_PA28 ( ( unsigned int ) 1 << 28 ) /* Pin Controlled by PA28 */ +#define AT91C_PA28_DTXD ( ( unsigned int ) AT91C_PIO_PA28 ) /* DBGU Debug Transmit Data */ +#define AT91C_PIO_PA29 ( ( unsigned int ) 1 << 29 ) /* Pin Controlled by PA29 */ +#define AT91C_PA29_FIQ ( ( unsigned int ) AT91C_PIO_PA29 ) /* AIC Fast Interrupt Input */ +#define AT91C_PA29_NPCS13 ( ( unsigned int ) AT91C_PIO_PA29 ) /* SPI 1 Peripheral Chip Select 3 */ +#define AT91C_PIO_PA3 ( ( unsigned int ) 1 << 3 ) /* Pin Controlled by PA3 */ +#define AT91C_PA3_RTS0 ( ( unsigned int ) AT91C_PIO_PA3 ) /* USART 0 Ready To Send */ +#define AT91C_PA3_NPCS12 ( ( unsigned int ) AT91C_PIO_PA3 ) /* SPI 1 Peripheral Chip Select 2 */ +#define AT91C_PIO_PA30 ( ( unsigned int ) 1 << 30 ) /* Pin Controlled by PA30 */ +#define AT91C_PA30_IRQ0 ( ( unsigned int ) AT91C_PIO_PA30 ) /* External Interrupt 0 */ +#define AT91C_PA30_PCK2 ( ( unsigned int ) AT91C_PIO_PA30 ) /* PMC Programmable Clock Output 2 */ +#define AT91C_PIO_PA4 ( ( unsigned int ) 1 << 4 ) /* Pin Controlled by PA4 */ +#define AT91C_PA4_CTS0 ( ( unsigned int ) AT91C_PIO_PA4 ) /* USART 0 Clear To Send */ +#define AT91C_PA4_NPCS13 ( ( unsigned int ) AT91C_PIO_PA4 ) /* SPI 1 Peripheral Chip Select 3 */ +#define AT91C_PIO_PA5 ( ( unsigned int ) 1 << 5 ) /* Pin Controlled by PA5 */ +#define AT91C_PA5_RXD1 ( ( unsigned int ) AT91C_PIO_PA5 ) /* USART 1 Receive Data */ +#define AT91C_PIO_PA6 ( ( unsigned int ) 1 << 6 ) /* Pin Controlled by PA6 */ +#define AT91C_PA6_TXD1 ( ( unsigned int ) AT91C_PIO_PA6 ) /* USART 1 Transmit Data */ +#define AT91C_PIO_PA7 ( ( unsigned int ) 1 << 7 ) /* Pin Controlled by PA7 */ +#define AT91C_PA7_SCK1 ( ( unsigned int ) AT91C_PIO_PA7 ) /* USART 1 Serial Clock */ +#define AT91C_PA7_NPCS01 ( ( unsigned int ) AT91C_PIO_PA7 ) /* SPI 0 Peripheral Chip Select 1 */ +#define AT91C_PIO_PA8 ( ( unsigned int ) 1 << 8 ) /* Pin Controlled by PA8 */ +#define AT91C_PA8_RTS1 ( ( unsigned int ) AT91C_PIO_PA8 ) /* USART 1 Ready To Send */ +#define AT91C_PA8_NPCS02 ( ( unsigned int ) AT91C_PIO_PA8 ) /* SPI 0 Peripheral Chip Select 2 */ +#define AT91C_PIO_PA9 ( ( unsigned int ) 1 << 9 ) /* Pin Controlled by PA9 */ +#define AT91C_PA9_CTS1 ( ( unsigned int ) AT91C_PIO_PA9 ) /* USART 1 Clear To Send */ +#define AT91C_PA9_NPCS03 ( ( unsigned int ) AT91C_PIO_PA9 ) /* SPI 0 Peripheral Chip Select 3 */ +#define AT91C_PIO_PB0 ( ( unsigned int ) 1 << 0 ) /* Pin Controlled by PB0 */ +#define AT91C_PB0_ETXCK_EREFCK ( ( unsigned int ) AT91C_PIO_PB0 ) /* Ethernet MAC Transmit Clock/Reference Clock */ +#define AT91C_PB0_PCK0 ( ( unsigned int ) AT91C_PIO_PB0 ) /* PMC Programmable Clock Output 0 */ +#define AT91C_PIO_PB1 ( ( unsigned int ) 1 << 1 ) /* Pin Controlled by PB1 */ +#define AT91C_PB1_ETXEN ( ( unsigned int ) AT91C_PIO_PB1 ) /* Ethernet MAC Transmit Enable */ +#define AT91C_PIO_PB10 ( ( unsigned int ) 1 << 10 ) /* Pin Controlled by PB10 */ +#define AT91C_PB10_ETX2 ( ( unsigned int ) AT91C_PIO_PB10 ) /* Ethernet MAC Transmit Data 2 */ +#define AT91C_PB10_NPCS11 ( ( unsigned int ) AT91C_PIO_PB10 ) /* SPI 1 Peripheral Chip Select 1 */ +#define AT91C_PIO_PB11 ( ( unsigned int ) 1 << 11 ) /* Pin Controlled by PB11 */ +#define AT91C_PB11_ETX3 ( ( unsigned int ) AT91C_PIO_PB11 ) /* Ethernet MAC Transmit Data 3 */ +#define AT91C_PB11_NPCS12 ( ( unsigned int ) AT91C_PIO_PB11 ) /* SPI 1 Peripheral Chip Select 2 */ +#define AT91C_PIO_PB12 ( ( unsigned int ) 1 << 12 ) /* Pin Controlled by PB12 */ +#define AT91C_PB12_ETXER ( ( unsigned int ) AT91C_PIO_PB12 ) /* Ethernet MAC Transmit Coding Error */ +#define AT91C_PB12_TCLK0 ( ( unsigned int ) AT91C_PIO_PB12 ) /* Timer Counter 0 external clock input */ +#define AT91C_PIO_PB13 ( ( unsigned int ) 1 << 13 ) /* Pin Controlled by PB13 */ +#define AT91C_PB13_ERX2 ( ( unsigned int ) AT91C_PIO_PB13 ) /* Ethernet MAC Receive Data 2 */ +#define AT91C_PB13_NPCS01 ( ( unsigned int ) AT91C_PIO_PB13 ) /* SPI 0 Peripheral Chip Select 1 */ +#define AT91C_PIO_PB14 ( ( unsigned int ) 1 << 14 ) /* Pin Controlled by PB14 */ +#define AT91C_PB14_ERX3 ( ( unsigned int ) AT91C_PIO_PB14 ) /* Ethernet MAC Receive Data 3 */ +#define AT91C_PB14_NPCS02 ( ( unsigned int ) AT91C_PIO_PB14 ) /* SPI 0 Peripheral Chip Select 2 */ +#define AT91C_PIO_PB15 ( ( unsigned int ) 1 << 15 ) /* Pin Controlled by PB15 */ +#define AT91C_PB15_ERXDV ( ( unsigned int ) AT91C_PIO_PB15 ) /* Ethernet MAC Receive Data Valid */ +#define AT91C_PIO_PB16 ( ( unsigned int ) 1 << 16 ) /* Pin Controlled by PB16 */ +#define AT91C_PB16_ECOL ( ( unsigned int ) AT91C_PIO_PB16 ) /* Ethernet MAC Collision Detected */ +#define AT91C_PB16_NPCS13 ( ( unsigned int ) AT91C_PIO_PB16 ) /* SPI 1 Peripheral Chip Select 3 */ +#define AT91C_PIO_PB17 ( ( unsigned int ) 1 << 17 ) /* Pin Controlled by PB17 */ +#define AT91C_PB17_ERXCK ( ( unsigned int ) AT91C_PIO_PB17 ) /* Ethernet MAC Receive Clock */ +#define AT91C_PB17_NPCS03 ( ( unsigned int ) AT91C_PIO_PB17 ) /* SPI 0 Peripheral Chip Select 3 */ +#define AT91C_PIO_PB18 ( ( unsigned int ) 1 << 18 ) /* Pin Controlled by PB18 */ +#define AT91C_PB18_EF100 ( ( unsigned int ) AT91C_PIO_PB18 ) /* Ethernet MAC Force 100 Mbits/sec */ +#define AT91C_PB18_ADTRG ( ( unsigned int ) AT91C_PIO_PB18 ) /* ADC External Trigger */ +#define AT91C_PIO_PB19 ( ( unsigned int ) 1 << 19 ) /* Pin Controlled by PB19 */ +#define AT91C_PB19_PWM0 ( ( unsigned int ) AT91C_PIO_PB19 ) /* PWM Channel 0 */ +#define AT91C_PB19_TCLK1 ( ( unsigned int ) AT91C_PIO_PB19 ) /* Timer Counter 1 external clock input */ +#define AT91C_PIO_PB2 ( ( unsigned int ) 1 << 2 ) /* Pin Controlled by PB2 */ +#define AT91C_PB2_ETX0 ( ( unsigned int ) AT91C_PIO_PB2 ) /* Ethernet MAC Transmit Data 0 */ +#define AT91C_PIO_PB20 ( ( unsigned int ) 1 << 20 ) /* Pin Controlled by PB20 */ +#define AT91C_PB20_PWM1 ( ( unsigned int ) AT91C_PIO_PB20 ) /* PWM Channel 1 */ +#define AT91C_PB20_PCK0 ( ( unsigned int ) AT91C_PIO_PB20 ) /* PMC Programmable Clock Output 0 */ +#define AT91C_PIO_PB21 ( ( unsigned int ) 1 << 21 ) /* Pin Controlled by PB21 */ +#define AT91C_PB21_PWM2 ( ( unsigned int ) AT91C_PIO_PB21 ) /* PWM Channel 2 */ +#define AT91C_PB21_PCK1 ( ( unsigned int ) AT91C_PIO_PB21 ) /* PMC Programmable Clock Output 1 */ +#define AT91C_PIO_PB22 ( ( unsigned int ) 1 << 22 ) /* Pin Controlled by PB22 */ +#define AT91C_PB22_PWM3 ( ( unsigned int ) AT91C_PIO_PB22 ) /* PWM Channel 3 */ +#define AT91C_PB22_PCK2 ( ( unsigned int ) AT91C_PIO_PB22 ) /* PMC Programmable Clock Output 2 */ +#define AT91C_PIO_PB23 ( ( unsigned int ) 1 << 23 ) /* Pin Controlled by PB23 */ +#define AT91C_PB23_TIOA0 ( ( unsigned int ) AT91C_PIO_PB23 ) /* Timer Counter 0 Multipurpose Timer I/O Pin A */ +#define AT91C_PB23_DCD1 ( ( unsigned int ) AT91C_PIO_PB23 ) /* USART 1 Data Carrier Detect */ +#define AT91C_PIO_PB24 ( ( unsigned int ) 1 << 24 ) /* Pin Controlled by PB24 */ +#define AT91C_PB24_TIOB0 ( ( unsigned int ) AT91C_PIO_PB24 ) /* Timer Counter 0 Multipurpose Timer I/O Pin B */ +#define AT91C_PB24_DSR1 ( ( unsigned int ) AT91C_PIO_PB24 ) /* USART 1 Data Set ready */ +#define AT91C_PIO_PB25 ( ( unsigned int ) 1 << 25 ) /* Pin Controlled by PB25 */ +#define AT91C_PB25_TIOA1 ( ( unsigned int ) AT91C_PIO_PB25 ) /* Timer Counter 1 Multipurpose Timer I/O Pin A */ +#define AT91C_PB25_DTR1 ( ( unsigned int ) AT91C_PIO_PB25 ) /* USART 1 Data Terminal ready */ +#define AT91C_PIO_PB26 ( ( unsigned int ) 1 << 26 ) /* Pin Controlled by PB26 */ +#define AT91C_PB26_TIOB1 ( ( unsigned int ) AT91C_PIO_PB26 ) /* Timer Counter 1 Multipurpose Timer I/O Pin B */ +#define AT91C_PB26_RI1 ( ( unsigned int ) AT91C_PIO_PB26 ) /* USART 1 Ring Indicator */ +#define AT91C_PIO_PB27 ( ( unsigned int ) 1 << 27 ) /* Pin Controlled by PB27 */ +#define AT91C_PB27_TIOA2 ( ( unsigned int ) AT91C_PIO_PB27 ) /* Timer Counter 2 Multipurpose Timer I/O Pin A */ +#define AT91C_PB27_PWM0 ( ( unsigned int ) AT91C_PIO_PB27 ) /* PWM Channel 0 */ +#define AT91C_PIO_PB28 ( ( unsigned int ) 1 << 28 ) /* Pin Controlled by PB28 */ +#define AT91C_PB28_TIOB2 ( ( unsigned int ) AT91C_PIO_PB28 ) /* Timer Counter 2 Multipurpose Timer I/O Pin B */ +#define AT91C_PB28_PWM1 ( ( unsigned int ) AT91C_PIO_PB28 ) /* PWM Channel 1 */ +#define AT91C_PIO_PB29 ( ( unsigned int ) 1 << 29 ) /* Pin Controlled by PB29 */ +#define AT91C_PB29_PCK1 ( ( unsigned int ) AT91C_PIO_PB29 ) /* PMC Programmable Clock Output 1 */ +#define AT91C_PB29_PWM2 ( ( unsigned int ) AT91C_PIO_PB29 ) /* PWM Channel 2 */ +#define AT91C_PIO_PB3 ( ( unsigned int ) 1 << 3 ) /* Pin Controlled by PB3 */ +#define AT91C_PB3_ETX1 ( ( unsigned int ) AT91C_PIO_PB3 ) /* Ethernet MAC Transmit Data 1 */ +#define AT91C_PIO_PB30 ( ( unsigned int ) 1 << 30 ) /* Pin Controlled by PB30 */ +#define AT91C_PB30_PCK2 ( ( unsigned int ) AT91C_PIO_PB30 ) /* PMC Programmable Clock Output 2 */ +#define AT91C_PB30_PWM3 ( ( unsigned int ) AT91C_PIO_PB30 ) /* PWM Channel 3 */ +#define AT91C_PIO_PB4 ( ( unsigned int ) 1 << 4 ) /* Pin Controlled by PB4 */ +#define AT91C_PB4_ECRS_ECRSDV ( ( unsigned int ) AT91C_PIO_PB4 ) /* Ethernet MAC Carrier Sense/Carrier Sense and Data Valid */ +#define AT91C_PIO_PB5 ( ( unsigned int ) 1 << 5 ) /* Pin Controlled by PB5 */ +#define AT91C_PB5_ERX0 ( ( unsigned int ) AT91C_PIO_PB5 ) /* Ethernet MAC Receive Data 0 */ +#define AT91C_PIO_PB6 ( ( unsigned int ) 1 << 6 ) /* Pin Controlled by PB6 */ +#define AT91C_PB6_ERX1 ( ( unsigned int ) AT91C_PIO_PB6 ) /* Ethernet MAC Receive Data 1 */ +#define AT91C_PIO_PB7 ( ( unsigned int ) 1 << 7 ) /* Pin Controlled by PB7 */ +#define AT91C_PB7_ERXER ( ( unsigned int ) AT91C_PIO_PB7 ) /* Ethernet MAC Receive Error */ +#define AT91C_PIO_PB8 ( ( unsigned int ) 1 << 8 ) /* Pin Controlled by PB8 */ +#define AT91C_PB8_EMDC ( ( unsigned int ) AT91C_PIO_PB8 ) /* Ethernet MAC Management Data Clock */ +#define AT91C_PIO_PB9 ( ( unsigned int ) 1 << 9 ) /* Pin Controlled by PB9 */ +#define AT91C_PB9_EMDIO ( ( unsigned int ) AT91C_PIO_PB9 ) /* Ethernet MAC Management Data Input/Output */ -// ***************************************************************************** -// PERIPHERAL ID DEFINITIONS FOR AT91SAM7X256 -// ***************************************************************************** -#define AT91C_ID_FIQ ((unsigned int) 0) // Advanced Interrupt Controller (FIQ) -#define AT91C_ID_SYS ((unsigned int) 1) // System Peripheral -#define AT91C_ID_PIOA ((unsigned int) 2) // Parallel IO Controller A -#define AT91C_ID_PIOB ((unsigned int) 3) // Parallel IO Controller B -#define AT91C_ID_SPI0 ((unsigned int) 4) // Serial Peripheral Interface 0 -#define AT91C_ID_SPI1 ((unsigned int) 5) // Serial Peripheral Interface 1 -#define AT91C_ID_US0 ((unsigned int) 6) // USART 0 -#define AT91C_ID_US1 ((unsigned int) 7) // USART 1 -#define AT91C_ID_SSC ((unsigned int) 8) // Serial Synchronous Controller -#define AT91C_ID_TWI ((unsigned int) 9) // Two-Wire Interface -#define AT91C_ID_PWMC ((unsigned int) 10) // PWM Controller -#define AT91C_ID_UDP ((unsigned int) 11) // USB Device Port -#define AT91C_ID_TC0 ((unsigned int) 12) // Timer Counter 0 -#define AT91C_ID_TC1 ((unsigned int) 13) // Timer Counter 1 -#define AT91C_ID_TC2 ((unsigned int) 14) // Timer Counter 2 -#define AT91C_ID_CAN ((unsigned int) 15) // Control Area Network Controller -#define AT91C_ID_EMAC ((unsigned int) 16) // Ethernet MAC -#define AT91C_ID_ADC ((unsigned int) 17) // Analog-to-Digital Converter -#define AT91C_ID_AES ((unsigned int) 18) // Advanced Encryption Standard 128-bit -#define AT91C_ID_TDES ((unsigned int) 19) // Triple Data Encryption Standard -#define AT91C_ID_20_Reserved ((unsigned int) 20) // Reserved -#define AT91C_ID_21_Reserved ((unsigned int) 21) // Reserved -#define AT91C_ID_22_Reserved ((unsigned int) 22) // Reserved -#define AT91C_ID_23_Reserved ((unsigned int) 23) // Reserved -#define AT91C_ID_24_Reserved ((unsigned int) 24) // Reserved -#define AT91C_ID_25_Reserved ((unsigned int) 25) // Reserved -#define AT91C_ID_26_Reserved ((unsigned int) 26) // Reserved -#define AT91C_ID_27_Reserved ((unsigned int) 27) // Reserved -#define AT91C_ID_28_Reserved ((unsigned int) 28) // Reserved -#define AT91C_ID_29_Reserved ((unsigned int) 29) // Reserved -#define AT91C_ID_IRQ0 ((unsigned int) 30) // Advanced Interrupt Controller (IRQ0) -#define AT91C_ID_IRQ1 ((unsigned int) 31) // Advanced Interrupt Controller (IRQ1) +/* ***************************************************************************** */ +/* PERIPHERAL ID DEFINITIONS FOR AT91SAM7X256 */ +/* ***************************************************************************** */ +#define AT91C_ID_FIQ ( ( unsigned int ) 0 ) /* Advanced Interrupt Controller (FIQ) */ +#define AT91C_ID_SYS ( ( unsigned int ) 1 ) /* System Peripheral */ +#define AT91C_ID_PIOA ( ( unsigned int ) 2 ) /* Parallel IO Controller A */ +#define AT91C_ID_PIOB ( ( unsigned int ) 3 ) /* Parallel IO Controller B */ +#define AT91C_ID_SPI0 ( ( unsigned int ) 4 ) /* Serial Peripheral Interface 0 */ +#define AT91C_ID_SPI1 ( ( unsigned int ) 5 ) /* Serial Peripheral Interface 1 */ +#define AT91C_ID_US0 ( ( unsigned int ) 6 ) /* USART 0 */ +#define AT91C_ID_US1 ( ( unsigned int ) 7 ) /* USART 1 */ +#define AT91C_ID_SSC ( ( unsigned int ) 8 ) /* Serial Synchronous Controller */ +#define AT91C_ID_TWI ( ( unsigned int ) 9 ) /* Two-Wire Interface */ +#define AT91C_ID_PWMC ( ( unsigned int ) 10 ) /* PWM Controller */ +#define AT91C_ID_UDP ( ( unsigned int ) 11 ) /* USB Device Port */ +#define AT91C_ID_TC0 ( ( unsigned int ) 12 ) /* Timer Counter 0 */ +#define AT91C_ID_TC1 ( ( unsigned int ) 13 ) /* Timer Counter 1 */ +#define AT91C_ID_TC2 ( ( unsigned int ) 14 ) /* Timer Counter 2 */ +#define AT91C_ID_CAN ( ( unsigned int ) 15 ) /* Control Area Network Controller */ +#define AT91C_ID_EMAC ( ( unsigned int ) 16 ) /* Ethernet MAC */ +#define AT91C_ID_ADC ( ( unsigned int ) 17 ) /* Analog-to-Digital Converter */ +#define AT91C_ID_AES ( ( unsigned int ) 18 ) /* Advanced Encryption Standard 128-bit */ +#define AT91C_ID_TDES ( ( unsigned int ) 19 ) /* Triple Data Encryption Standard */ +#define AT91C_ID_20_Reserved ( ( unsigned int ) 20 ) /* Reserved */ +#define AT91C_ID_21_Reserved ( ( unsigned int ) 21 ) /* Reserved */ +#define AT91C_ID_22_Reserved ( ( unsigned int ) 22 ) /* Reserved */ +#define AT91C_ID_23_Reserved ( ( unsigned int ) 23 ) /* Reserved */ +#define AT91C_ID_24_Reserved ( ( unsigned int ) 24 ) /* Reserved */ +#define AT91C_ID_25_Reserved ( ( unsigned int ) 25 ) /* Reserved */ +#define AT91C_ID_26_Reserved ( ( unsigned int ) 26 ) /* Reserved */ +#define AT91C_ID_27_Reserved ( ( unsigned int ) 27 ) /* Reserved */ +#define AT91C_ID_28_Reserved ( ( unsigned int ) 28 ) /* Reserved */ +#define AT91C_ID_29_Reserved ( ( unsigned int ) 29 ) /* Reserved */ +#define AT91C_ID_IRQ0 ( ( unsigned int ) 30 ) /* Advanced Interrupt Controller (IRQ0) */ +#define AT91C_ID_IRQ1 ( ( unsigned int ) 31 ) /* Advanced Interrupt Controller (IRQ1) */ -// ***************************************************************************** -// BASE ADDRESS DEFINITIONS FOR AT91SAM7X256 -// ***************************************************************************** -#define AT91C_BASE_SYS ((AT91PS_SYS) 0xFFFFF000) // (SYS) Base Address -#define AT91C_BASE_AIC ((AT91PS_AIC) 0xFFFFF000) // (AIC) Base Address -#define AT91C_BASE_PDC_DBGU ((AT91PS_PDC) 0xFFFFF300) // (PDC_DBGU) Base Address -#define AT91C_BASE_DBGU ((AT91PS_DBGU) 0xFFFFF200) // (DBGU) Base Address -#define AT91C_BASE_PIOA ((AT91PS_PIO) 0xFFFFF400) // (PIOA) Base Address -#define AT91C_BASE_PIOB ((AT91PS_PIO) 0xFFFFF600) // (PIOB) Base Address -#define AT91C_BASE_CKGR ((AT91PS_CKGR) 0xFFFFFC20) // (CKGR) Base Address -#define AT91C_BASE_PMC ((AT91PS_PMC) 0xFFFFFC00) // (PMC) Base Address -#define AT91C_BASE_RSTC ((AT91PS_RSTC) 0xFFFFFD00) // (RSTC) Base Address -#define AT91C_BASE_RTTC ((AT91PS_RTTC) 0xFFFFFD20) // (RTTC) Base Address -#define AT91C_BASE_PITC ((AT91PS_PITC) 0xFFFFFD30) // (PITC) Base Address -#define AT91C_BASE_WDTC ((AT91PS_WDTC) 0xFFFFFD40) // (WDTC) Base Address -#define AT91C_BASE_VREG ((AT91PS_VREG) 0xFFFFFD60) // (VREG) Base Address -#define AT91C_BASE_MC ((AT91PS_MC) 0xFFFFFF00) // (MC) Base Address -#define AT91C_BASE_PDC_SPI1 ((AT91PS_PDC) 0xFFFE4100) // (PDC_SPI1) Base Address -#define AT91C_BASE_SPI1 ((AT91PS_SPI) 0xFFFE4000) // (SPI1) Base Address -#define AT91C_BASE_PDC_SPI0 ((AT91PS_PDC) 0xFFFE0100) // (PDC_SPI0) Base Address -#define AT91C_BASE_SPI0 ((AT91PS_SPI) 0xFFFE0000) // (SPI0) Base Address -#define AT91C_BASE_PDC_US1 ((AT91PS_PDC) 0xFFFC4100) // (PDC_US1) Base Address -#define AT91C_BASE_US1 ((AT91PS_USART) 0xFFFC4000) // (US1) Base Address -#define AT91C_BASE_PDC_US0 ((AT91PS_PDC) 0xFFFC0100) // (PDC_US0) Base Address -#define AT91C_BASE_US0 ((AT91PS_USART) 0xFFFC0000) // (US0) Base Address -#define AT91C_BASE_PDC_SSC ((AT91PS_PDC) 0xFFFD4100) // (PDC_SSC) Base Address -#define AT91C_BASE_SSC ((AT91PS_SSC) 0xFFFD4000) // (SSC) Base Address -#define AT91C_BASE_TWI ((AT91PS_TWI) 0xFFFB8000) // (TWI) Base Address -#define AT91C_BASE_PWMC_CH3 ((AT91PS_PWMC_CH) 0xFFFCC260) // (PWMC_CH3) Base Address -#define AT91C_BASE_PWMC_CH2 ((AT91PS_PWMC_CH) 0xFFFCC240) // (PWMC_CH2) Base Address -#define AT91C_BASE_PWMC_CH1 ((AT91PS_PWMC_CH) 0xFFFCC220) // (PWMC_CH1) Base Address -#define AT91C_BASE_PWMC_CH0 ((AT91PS_PWMC_CH) 0xFFFCC200) // (PWMC_CH0) Base Address -#define AT91C_BASE_PWMC ((AT91PS_PWMC) 0xFFFCC000) // (PWMC) Base Address -#define AT91C_BASE_UDP ((AT91PS_UDP) 0xFFFB0000) // (UDP) Base Address -#define AT91C_BASE_TC0 ((AT91PS_TC) 0xFFFA0000) // (TC0) Base Address -#define AT91C_BASE_TC1 ((AT91PS_TC) 0xFFFA0040) // (TC1) Base Address -#define AT91C_BASE_TC2 ((AT91PS_TC) 0xFFFA0080) // (TC2) Base Address -#define AT91C_BASE_TCB ((AT91PS_TCB) 0xFFFA0000) // (TCB) Base Address -#define AT91C_BASE_CAN_MB0 ((AT91PS_CAN_MB) 0xFFFD0200) // (CAN_MB0) Base Address -#define AT91C_BASE_CAN_MB1 ((AT91PS_CAN_MB) 0xFFFD0220) // (CAN_MB1) Base Address -#define AT91C_BASE_CAN_MB2 ((AT91PS_CAN_MB) 0xFFFD0240) // (CAN_MB2) Base Address -#define AT91C_BASE_CAN_MB3 ((AT91PS_CAN_MB) 0xFFFD0260) // (CAN_MB3) Base Address -#define AT91C_BASE_CAN_MB4 ((AT91PS_CAN_MB) 0xFFFD0280) // (CAN_MB4) Base Address -#define AT91C_BASE_CAN_MB5 ((AT91PS_CAN_MB) 0xFFFD02A0) // (CAN_MB5) Base Address -#define AT91C_BASE_CAN_MB6 ((AT91PS_CAN_MB) 0xFFFD02C0) // (CAN_MB6) Base Address -#define AT91C_BASE_CAN_MB7 ((AT91PS_CAN_MB) 0xFFFD02E0) // (CAN_MB7) Base Address -#define AT91C_BASE_CAN ((AT91PS_CAN) 0xFFFD0000) // (CAN) Base Address -#define AT91C_BASE_EMAC ((AT91PS_EMAC) 0xFFFDC000) // (EMAC) Base Address -#define AT91C_BASE_PDC_ADC ((AT91PS_PDC) 0xFFFD8100) // (PDC_ADC) Base Address -#define AT91C_BASE_ADC ((AT91PS_ADC) 0xFFFD8000) // (ADC) Base Address -#define AT91C_BASE_PDC_AES ((AT91PS_PDC) 0xFFFA4100) // (PDC_AES) Base Address -#define AT91C_BASE_AES ((AT91PS_AES) 0xFFFA4000) // (AES) Base Address -#define AT91C_BASE_PDC_TDES ((AT91PS_PDC) 0xFFFA8100) // (PDC_TDES) Base Address -#define AT91C_BASE_TDES ((AT91PS_TDES) 0xFFFA8000) // (TDES) Base Address +/* ***************************************************************************** */ +/* BASE ADDRESS DEFINITIONS FOR AT91SAM7X256 */ +/* ***************************************************************************** */ +#define AT91C_BASE_SYS ( ( AT91PS_SYS ) 0xFFFFF000 ) /* (SYS) Base Address */ +#define AT91C_BASE_AIC ( ( AT91PS_AIC ) 0xFFFFF000 ) /* (AIC) Base Address */ +#define AT91C_BASE_PDC_DBGU ( ( AT91PS_PDC ) 0xFFFFF300 ) /* (PDC_DBGU) Base Address */ +#define AT91C_BASE_DBGU ( ( AT91PS_DBGU ) 0xFFFFF200 ) /* (DBGU) Base Address */ +#define AT91C_BASE_PIOA ( ( AT91PS_PIO ) 0xFFFFF400 ) /* (PIOA) Base Address */ +#define AT91C_BASE_PIOB ( ( AT91PS_PIO ) 0xFFFFF600 ) /* (PIOB) Base Address */ +#define AT91C_BASE_CKGR ( ( AT91PS_CKGR ) 0xFFFFFC20 ) /* (CKGR) Base Address */ +#define AT91C_BASE_PMC ( ( AT91PS_PMC ) 0xFFFFFC00 ) /* (PMC) Base Address */ +#define AT91C_BASE_RSTC ( ( AT91PS_RSTC ) 0xFFFFFD00 ) /* (RSTC) Base Address */ +#define AT91C_BASE_RTTC ( ( AT91PS_RTTC ) 0xFFFFFD20 ) /* (RTTC) Base Address */ +#define AT91C_BASE_PITC ( ( AT91PS_PITC ) 0xFFFFFD30 ) /* (PITC) Base Address */ +#define AT91C_BASE_WDTC ( ( AT91PS_WDTC ) 0xFFFFFD40 ) /* (WDTC) Base Address */ +#define AT91C_BASE_VREG ( ( AT91PS_VREG ) 0xFFFFFD60 ) /* (VREG) Base Address */ +#define AT91C_BASE_MC ( ( AT91PS_MC ) 0xFFFFFF00 ) /* (MC) Base Address */ +#define AT91C_BASE_PDC_SPI1 ( ( AT91PS_PDC ) 0xFFFE4100 ) /* (PDC_SPI1) Base Address */ +#define AT91C_BASE_SPI1 ( ( AT91PS_SPI ) 0xFFFE4000 ) /* (SPI1) Base Address */ +#define AT91C_BASE_PDC_SPI0 ( ( AT91PS_PDC ) 0xFFFE0100 ) /* (PDC_SPI0) Base Address */ +#define AT91C_BASE_SPI0 ( ( AT91PS_SPI ) 0xFFFE0000 ) /* (SPI0) Base Address */ +#define AT91C_BASE_PDC_US1 ( ( AT91PS_PDC ) 0xFFFC4100 ) /* (PDC_US1) Base Address */ +#define AT91C_BASE_US1 ( ( AT91PS_USART ) 0xFFFC4000 ) /* (US1) Base Address */ +#define AT91C_BASE_PDC_US0 ( ( AT91PS_PDC ) 0xFFFC0100 ) /* (PDC_US0) Base Address */ +#define AT91C_BASE_US0 ( ( AT91PS_USART ) 0xFFFC0000 ) /* (US0) Base Address */ +#define AT91C_BASE_PDC_SSC ( ( AT91PS_PDC ) 0xFFFD4100 ) /* (PDC_SSC) Base Address */ +#define AT91C_BASE_SSC ( ( AT91PS_SSC ) 0xFFFD4000 ) /* (SSC) Base Address */ +#define AT91C_BASE_TWI ( ( AT91PS_TWI ) 0xFFFB8000 ) /* (TWI) Base Address */ +#define AT91C_BASE_PWMC_CH3 ( ( AT91PS_PWMC_CH ) 0xFFFCC260 ) /* (PWMC_CH3) Base Address */ +#define AT91C_BASE_PWMC_CH2 ( ( AT91PS_PWMC_CH ) 0xFFFCC240 ) /* (PWMC_CH2) Base Address */ +#define AT91C_BASE_PWMC_CH1 ( ( AT91PS_PWMC_CH ) 0xFFFCC220 ) /* (PWMC_CH1) Base Address */ +#define AT91C_BASE_PWMC_CH0 ( ( AT91PS_PWMC_CH ) 0xFFFCC200 ) /* (PWMC_CH0) Base Address */ +#define AT91C_BASE_PWMC ( ( AT91PS_PWMC ) 0xFFFCC000 ) /* (PWMC) Base Address */ +#define AT91C_BASE_UDP ( ( AT91PS_UDP ) 0xFFFB0000 ) /* (UDP) Base Address */ +#define AT91C_BASE_TC0 ( ( AT91PS_TC ) 0xFFFA0000 ) /* (TC0) Base Address */ +#define AT91C_BASE_TC1 ( ( AT91PS_TC ) 0xFFFA0040 ) /* (TC1) Base Address */ +#define AT91C_BASE_TC2 ( ( AT91PS_TC ) 0xFFFA0080 ) /* (TC2) Base Address */ +#define AT91C_BASE_TCB ( ( AT91PS_TCB ) 0xFFFA0000 ) /* (TCB) Base Address */ +#define AT91C_BASE_CAN_MB0 ( ( AT91PS_CAN_MB ) 0xFFFD0200 ) /* (CAN_MB0) Base Address */ +#define AT91C_BASE_CAN_MB1 ( ( AT91PS_CAN_MB ) 0xFFFD0220 ) /* (CAN_MB1) Base Address */ +#define AT91C_BASE_CAN_MB2 ( ( AT91PS_CAN_MB ) 0xFFFD0240 ) /* (CAN_MB2) Base Address */ +#define AT91C_BASE_CAN_MB3 ( ( AT91PS_CAN_MB ) 0xFFFD0260 ) /* (CAN_MB3) Base Address */ +#define AT91C_BASE_CAN_MB4 ( ( AT91PS_CAN_MB ) 0xFFFD0280 ) /* (CAN_MB4) Base Address */ +#define AT91C_BASE_CAN_MB5 ( ( AT91PS_CAN_MB ) 0xFFFD02A0 ) /* (CAN_MB5) Base Address */ +#define AT91C_BASE_CAN_MB6 ( ( AT91PS_CAN_MB ) 0xFFFD02C0 ) /* (CAN_MB6) Base Address */ +#define AT91C_BASE_CAN_MB7 ( ( AT91PS_CAN_MB ) 0xFFFD02E0 ) /* (CAN_MB7) Base Address */ +#define AT91C_BASE_CAN ( ( AT91PS_CAN ) 0xFFFD0000 ) /* (CAN) Base Address */ +#define AT91C_BASE_EMAC ( ( AT91PS_EMAC ) 0xFFFDC000 ) /* (EMAC) Base Address */ +#define AT91C_BASE_PDC_ADC ( ( AT91PS_PDC ) 0xFFFD8100 ) /* (PDC_ADC) Base Address */ +#define AT91C_BASE_ADC ( ( AT91PS_ADC ) 0xFFFD8000 ) /* (ADC) Base Address */ +#define AT91C_BASE_PDC_AES ( ( AT91PS_PDC ) 0xFFFA4100 ) /* (PDC_AES) Base Address */ +#define AT91C_BASE_AES ( ( AT91PS_AES ) 0xFFFA4000 ) /* (AES) Base Address */ +#define AT91C_BASE_PDC_TDES ( ( AT91PS_PDC ) 0xFFFA8100 ) /* (PDC_TDES) Base Address */ +#define AT91C_BASE_TDES ( ( AT91PS_TDES ) 0xFFFA8000 ) /* (TDES) Base Address */ -// ***************************************************************************** -// MEMORY MAPPING DEFINITIONS FOR AT91SAM7X256 -// ***************************************************************************** -#define AT91C_ISRAM ((char *) 0x00200000) // Internal SRAM base address -#define AT91C_ISRAM_SIZE ((unsigned int) 0x00010000) // Internal SRAM size in byte (64 Kbyte) -#define AT91C_IFLASH ((char *) 0x00100000) // Internal ROM base address -#define AT91C_IFLASH_SIZE ((unsigned int) 0x00040000) // Internal ROM size in byte (256 Kbyte) +/* ***************************************************************************** */ +/* MEMORY MAPPING DEFINITIONS FOR AT91SAM7X256 */ +/* ***************************************************************************** */ +#define AT91C_ISRAM ( ( char * ) 0x00200000 ) /* Internal SRAM base address */ +#define AT91C_ISRAM_SIZE ( ( unsigned int ) 0x00010000 ) /* Internal SRAM size in byte (64 Kbyte) */ +#define AT91C_IFLASH ( ( char * ) 0x00100000 ) /* Internal ROM base address */ +#define AT91C_IFLASH_SIZE ( ( unsigned int ) 0x00040000 ) /* Internal ROM size in byte (256 Kbyte) */ -// - Hardware register definition +/* - Hardware register definition */ -// - ***************************************************************************** -// - SOFTWARE API DEFINITION FOR System Peripherals -// - ***************************************************************************** +/* - ***************************************************************************** */ +/* - SOFTWARE API DEFINITION FOR System Peripherals */ +/* - ***************************************************************************** */ -// - ***************************************************************************** -// - SOFTWARE API DEFINITION FOR Advanced Interrupt Controller -// - ***************************************************************************** -// - -------- AIC_SMR : (AIC Offset: 0x0) Control Register -------- +/* - ***************************************************************************** */ +/* - SOFTWARE API DEFINITION FOR Advanced Interrupt Controller */ +/* - ***************************************************************************** */ +/* - -------- AIC_SMR : (AIC Offset: 0x0) Control Register -------- */ #if 0 /*_RB_*/ -AT91C_AIC_PRIOR EQU (0x7 << 0) ;- (AIC) Priority Level -AT91C_AIC_PRIOR_LOWEST EQU (0x0) ;- (AIC) Lowest priority level -AT91C_AIC_PRIOR_HIGHEST EQU (0x7) ;- (AIC) Highest priority level -AT91C_AIC_SRCTYPE EQU (0x3 << 5) ;- (AIC) Interrupt Source Type -AT91C_AIC_SRCTYPE_INT_HIGH_LEVEL EQU (0x0 << 5) ;- (AIC) Internal Sources Code Label High-level Sensitive -AT91C_AIC_SRCTYPE_EXT_LOW_LEVEL EQU (0x0 << 5) ;- (AIC) External Sources Code Label Low-level Sensitive -AT91C_AIC_SRCTYPE_INT_POSITIVE_EDGE EQU (0x1 << 5) ;- (AIC) Internal Sources Code Label Positive Edge triggered -AT91C_AIC_SRCTYPE_EXT_NEGATIVE_EDGE EQU (0x1 << 5) ;- (AIC) External Sources Code Label Negative Edge triggered -AT91C_AIC_SRCTYPE_HIGH_LEVEL EQU (0x2 << 5) ;- (AIC) Internal Or External Sources Code Label High-level Sensitive -AT91C_AIC_SRCTYPE_POSITIVE_EDGE EQU (0x3 << 5) ;- (AIC) Internal Or External Sources Code Label Positive Edge triggered -// - -------- AIC_CISR : (AIC Offset: 0x114) AIC Core Interrupt Status Register -------- -AT91C_AIC_NFIQ EQU (0x1 << 0) ;- (AIC) NFIQ Status -AT91C_AIC_NIRQ EQU (0x1 << 1) ;- (AIC) NIRQ Status -// - -------- AIC_DCR : (AIC Offset: 0x138) AIC Debug Control Register (Protect) -------- -AT91C_AIC_DCR_PROT EQU (0x1 << 0) ;- (AIC) Protection Mode -AT91C_AIC_DCR_GMSK EQU (0x1 << 1) ;- (AIC) General Mask -#endif -// - ***************************************************************************** -// - SOFTWARE API DEFINITION FOR Peripheral DMA Controller -// - ***************************************************************************** -// - -------- PDC_PTCR : (PDC Offset: 0x20) PDC Transfer Control Register -------- -AT91C_PDC_RXTEN EQU (0x1 << 0) ;- (PDC) Receiver Transfer Enable -AT91C_PDC_RXTDIS EQU (0x1 << 1) ;- (PDC) Receiver Transfer Disable -AT91C_PDC_TXTEN EQU (0x1 << 8) ;- (PDC) Transmitter Transfer Enable -AT91C_PDC_TXTDIS EQU (0x1 << 9) ;- (PDC) Transmitter Transfer Disable -// - -------- PDC_PTSR : (PDC Offset: 0x24) PDC Transfer Status Register -------- + AT91C_AIC_PRIOR EQU( 0x7 << 0 ); + -( AIC ) Priority Level + AT91C_AIC_PRIOR_LOWEST EQU( 0x0 ); + -( AIC ) Lowest priority level + AT91C_AIC_PRIOR_HIGHEST EQU( 0x7 ); + -( AIC ) Highest priority level + AT91C_AIC_SRCTYPE EQU( 0x3 << 5 ); + -( AIC ) Interrupt Source Type + AT91C_AIC_SRCTYPE_INT_HIGH_LEVEL EQU( 0x0 << 5 ); + -( AIC ) Internal Sources Code Label High - level Sensitive + AT91C_AIC_SRCTYPE_EXT_LOW_LEVEL EQU( 0x0 << 5 ); + -( AIC ) External Sources Code Label Low - level Sensitive + AT91C_AIC_SRCTYPE_INT_POSITIVE_EDGE EQU( 0x1 << 5 ); + -( AIC ) Internal Sources Code Label Positive Edge triggered + AT91C_AIC_SRCTYPE_EXT_NEGATIVE_EDGE EQU( 0x1 << 5 ); + -( AIC ) External Sources Code Label Negative Edge triggered + AT91C_AIC_SRCTYPE_HIGH_LEVEL EQU( 0x2 << 5 ); + -( AIC ) Internal Or External Sources Code Label High - level Sensitive + AT91C_AIC_SRCTYPE_POSITIVE_EDGE EQU( 0x3 << 5 ); + -( AIC ) Internal Or External Sources Code Label Positive Edge triggered +/* - -------- AIC_CISR : (AIC Offset: 0x114) AIC Core Interrupt Status Register -------- */ + AT91C_AIC_NFIQ EQU( 0x1 << 0 ); + -( AIC ) NFIQ Status + AT91C_AIC_NIRQ EQU( 0x1 << 1 ); + -( AIC ) NIRQ Status +/* - -------- AIC_DCR : (AIC Offset: 0x138) AIC Debug Control Register (Protect) -------- */ + AT91C_AIC_DCR_PROT EQU( 0x1 << 0 ); + -( AIC ) Protection Mode + AT91C_AIC_DCR_GMSK EQU( 0x1 << 1 ); + -( AIC ) General Mask +#endif /* if 0 */ +/* - ***************************************************************************** */ +/* - SOFTWARE API DEFINITION FOR Peripheral DMA Controller */ +/* - ***************************************************************************** */ +/* - -------- PDC_PTCR : (PDC Offset: 0x20) PDC Transfer Control Register -------- */ +AT91C_PDC_RXTEN EQU( 0x1 << 0 ); +-( PDC ) Receiver Transfer Enable +AT91C_PDC_RXTDIS EQU( 0x1 << 1 ); +-( PDC ) Receiver Transfer Disable +AT91C_PDC_TXTEN EQU( 0x1 << 8 ); +-( PDC ) Transmitter Transfer Enable +AT91C_PDC_TXTDIS EQU( 0x1 << 9 ); +-( PDC ) Transmitter Transfer Disable +/* - -------- PDC_PTSR : (PDC Offset: 0x24) PDC Transfer Status Register -------- */ -// - ***************************************************************************** -// - SOFTWARE API DEFINITION FOR Debug Unit -// - ***************************************************************************** -// - -------- DBGU_CR : (DBGU Offset: 0x0) Debug Unit Control Register -------- -AT91C_US_RSTRX EQU (0x1 << 2) ;- (DBGU) Reset Receiver -AT91C_US_RSTTX EQU (0x1 << 3) ;- (DBGU) Reset Transmitter -AT91C_US_RXEN EQU (0x1 << 4) ;- (DBGU) Receiver Enable -AT91C_US_RXDIS EQU (0x1 << 5) ;- (DBGU) Receiver Disable -AT91C_US_TXEN EQU (0x1 << 6) ;- (DBGU) Transmitter Enable -AT91C_US_TXDIS EQU (0x1 << 7) ;- (DBGU) Transmitter Disable -AT91C_US_RSTSTA EQU (0x1 << 8) ;- (DBGU) Reset Status Bits -// - -------- DBGU_MR : (DBGU Offset: 0x4) Debug Unit Mode Register -------- -AT91C_US_PAR EQU (0x7 << 9) ;- (DBGU) Parity type -AT91C_US_PAR_EVEN EQU (0x0 << 9) ;- (DBGU) Even Parity -AT91C_US_PAR_ODD EQU (0x1 << 9) ;- (DBGU) Odd Parity -AT91C_US_PAR_SPACE EQU (0x2 << 9) ;- (DBGU) Parity forced to 0 (Space) -AT91C_US_PAR_MARK EQU (0x3 << 9) ;- (DBGU) Parity forced to 1 (Mark) -AT91C_US_PAR_NONE EQU (0x4 << 9) ;- (DBGU) No Parity -AT91C_US_PAR_MULTI_DROP EQU (0x6 << 9) ;- (DBGU) Multi-drop mode -AT91C_US_CHMODE EQU (0x3 << 14) ;- (DBGU) Channel Mode -AT91C_US_CHMODE_NORMAL EQU (0x0 << 14) ;- (DBGU) Normal Mode: The USART channel operates as an RX/TX USART. -AT91C_US_CHMODE_AUTO EQU (0x1 << 14) ;- (DBGU) Automatic Echo: Receiver Data Input is connected to the TXD pin. -AT91C_US_CHMODE_LOCAL EQU (0x2 << 14) ;- (DBGU) Local Loopback: Transmitter Output Signal is connected to Receiver Input Signal. -AT91C_US_CHMODE_REMOTE EQU (0x3 << 14) ;- (DBGU) Remote Loopback: RXD pin is internally connected to TXD pin. -// - -------- DBGU_IER : (DBGU Offset: 0x8) Debug Unit Interrupt Enable Register -------- -AT91C_US_RXRDY EQU (0x1 << 0) ;- (DBGU) RXRDY Interrupt -AT91C_US_TXRDY EQU (0x1 << 1) ;- (DBGU) TXRDY Interrupt -AT91C_US_ENDRX EQU (0x1 << 3) ;- (DBGU) End of Receive Transfer Interrupt -AT91C_US_ENDTX EQU (0x1 << 4) ;- (DBGU) End of Transmit Interrupt -AT91C_US_OVRE EQU (0x1 << 5) ;- (DBGU) Overrun Interrupt -AT91C_US_FRAME EQU (0x1 << 6) ;- (DBGU) Framing Error Interrupt -AT91C_US_PARE EQU (0x1 << 7) ;- (DBGU) Parity Error Interrupt -AT91C_US_TXEMPTY EQU (0x1 << 9) ;- (DBGU) TXEMPTY Interrupt -AT91C_US_TXBUFE EQU (0x1 << 11) ;- (DBGU) TXBUFE Interrupt -AT91C_US_RXBUFF EQU (0x1 << 12) ;- (DBGU) RXBUFF Interrupt -AT91C_US_COMM_TX EQU (0x1 << 30) ;- (DBGU) COMM_TX Interrupt -AT91C_US_COMM_RX EQU (0x1 << 31) ;- (DBGU) COMM_RX Interrupt -// - -------- DBGU_IDR : (DBGU Offset: 0xc) Debug Unit Interrupt Disable Register -------- -// - -------- DBGU_IMR : (DBGU Offset: 0x10) Debug Unit Interrupt Mask Register -------- -// - -------- DBGU_CSR : (DBGU Offset: 0x14) Debug Unit Channel Status Register -------- -// - -------- DBGU_FNTR : (DBGU Offset: 0x48) Debug Unit FORCE_NTRST Register -------- -AT91C_US_FORCE_NTRST EQU (0x1 << 0) ;- (DBGU) Force NTRST in JTAG +/* - ***************************************************************************** */ +/* - SOFTWARE API DEFINITION FOR Debug Unit */ +/* - ***************************************************************************** */ +/* - -------- DBGU_CR : (DBGU Offset: 0x0) Debug Unit Control Register -------- */ +AT91C_US_RSTRX EQU( 0x1 << 2 ); +-( DBGU ) Reset Receiver +AT91C_US_RSTTX EQU( 0x1 << 3 ); +-( DBGU ) Reset Transmitter +AT91C_US_RXEN EQU( 0x1 << 4 ); +-( DBGU ) Receiver Enable +AT91C_US_RXDIS EQU( 0x1 << 5 ); +-( DBGU ) Receiver Disable +AT91C_US_TXEN EQU( 0x1 << 6 ); +-( DBGU ) Transmitter Enable +AT91C_US_TXDIS EQU( 0x1 << 7 ); +-( DBGU ) Transmitter Disable +AT91C_US_RSTSTA EQU( 0x1 << 8 ); +-( DBGU ) Reset Status Bits +/* - -------- DBGU_MR : (DBGU Offset: 0x4) Debug Unit Mode Register -------- */ +AT91C_US_PAR EQU( 0x7 << 9 ); +-( DBGU ) Parity type +AT91C_US_PAR_EVEN EQU( 0x0 << 9 ); +-( DBGU ) Even Parity +AT91C_US_PAR_ODD EQU( 0x1 << 9 ); +-( DBGU ) Odd Parity +AT91C_US_PAR_SPACE EQU( 0x2 << 9 ); +-( DBGU ) Parity forced to 0 ( Space ) +AT91C_US_PAR_MARK EQU( 0x3 << 9 ); +-( DBGU ) Parity forced to 1 ( Mark ) +AT91C_US_PAR_NONE EQU( 0x4 << 9 ); +-( DBGU ) No Parity +AT91C_US_PAR_MULTI_DROP EQU( 0x6 << 9 ); +-( DBGU ) Multi - drop mode +AT91C_US_CHMODE EQU( 0x3 << 14 ); +-( DBGU ) Channel Mode +AT91C_US_CHMODE_NORMAL EQU( 0x0 << 14 ); +-( DBGU ) Normal Mode: The USART channel operates as an RX / TX USART. + AT91C_US_CHMODE_AUTO EQU( 0x1 << 14 ); +-( DBGU ) Automatic Echo: Receiver Data Input is connected to the TXD pin. + AT91C_US_CHMODE_LOCAL EQU( 0x2 << 14 ); +-( DBGU ) Local Loopback: Transmitter Output Signal is connected to Receiver Input Signal. + AT91C_US_CHMODE_REMOTE EQU( 0x3 << 14 ); +-( DBGU ) Remote Loopback: RXD pin is internally connected to TXD pin. +/* - -------- DBGU_IER : (DBGU Offset: 0x8) Debug Unit Interrupt Enable Register -------- */ + AT91C_US_RXRDY EQU( 0x1 << 0 ); +-( DBGU ) RXRDY Interrupt +AT91C_US_TXRDY EQU( 0x1 << 1 ); +-( DBGU ) TXRDY Interrupt +AT91C_US_ENDRX EQU( 0x1 << 3 ); +-( DBGU ) End of Receive Transfer Interrupt +AT91C_US_ENDTX EQU( 0x1 << 4 ); +-( DBGU ) End of Transmit Interrupt +AT91C_US_OVRE EQU( 0x1 << 5 ); +-( DBGU ) Overrun Interrupt +AT91C_US_FRAME EQU( 0x1 << 6 ); +-( DBGU ) Framing Error Interrupt +AT91C_US_PARE EQU( 0x1 << 7 ); +-( DBGU ) Parity Error Interrupt +AT91C_US_TXEMPTY EQU( 0x1 << 9 ); +-( DBGU ) TXEMPTY Interrupt +AT91C_US_TXBUFE EQU( 0x1 << 11 ); +-( DBGU ) TXBUFE Interrupt +AT91C_US_RXBUFF EQU( 0x1 << 12 ); +-( DBGU ) RXBUFF Interrupt +AT91C_US_COMM_TX EQU( 0x1 << 30 ); +-( DBGU ) COMM_TX Interrupt +AT91C_US_COMM_RX EQU( 0x1 << 31 ); +-( DBGU ) COMM_RX Interrupt +/* - -------- DBGU_IDR : (DBGU Offset: 0xc) Debug Unit Interrupt Disable Register -------- */ +/* - -------- DBGU_IMR : (DBGU Offset: 0x10) Debug Unit Interrupt Mask Register -------- */ +/* - -------- DBGU_CSR : (DBGU Offset: 0x14) Debug Unit Channel Status Register -------- */ +/* - -------- DBGU_FNTR : (DBGU Offset: 0x48) Debug Unit FORCE_NTRST Register -------- */ +AT91C_US_FORCE_NTRST EQU( 0x1 << 0 ); +-( DBGU ) Force NTRST in JTAG -// - ***************************************************************************** -// - SOFTWARE API DEFINITION FOR Parallel Input Output Controler -// - ***************************************************************************** +/* - ***************************************************************************** */ +/* - SOFTWARE API DEFINITION FOR Parallel Input Output Controller */ +/* - ***************************************************************************** */ -// - ***************************************************************************** -// - SOFTWARE API DEFINITION FOR Clock Generator Controler -// - ***************************************************************************** -// - -------- CKGR_MOR : (CKGR Offset: 0x0) Main Oscillator Register -------- -AT91C_CKGR_MOSCEN EQU (0x1 << 0) ;- (CKGR) Main Oscillator Enable -AT91C_CKGR_OSCBYPASS EQU (0x1 << 1) ;- (CKGR) Main Oscillator Bypass -AT91C_CKGR_OSCOUNT EQU (0xFF << 8) ;- (CKGR) Main Oscillator Start-up Time -// - -------- CKGR_MCFR : (CKGR Offset: 0x4) Main Clock Frequency Register -------- -AT91C_CKGR_MAINF EQU (0xFFFF << 0) ;- (CKGR) Main Clock Frequency -AT91C_CKGR_MAINRDY EQU (0x1 << 16) ;- (CKGR) Main Clock Ready -// - -------- CKGR_PLLR : (CKGR Offset: 0xc) PLL B Register -------- -AT91C_CKGR_DIV EQU (0xFF << 0) ;- (CKGR) Divider Selected -AT91C_CKGR_DIV_0 EQU (0x0) ;- (CKGR) Divider output is 0 -AT91C_CKGR_DIV_BYPASS EQU (0x1) ;- (CKGR) Divider is bypassed -AT91C_CKGR_PLLCOUNT EQU (0x3F << 8) ;- (CKGR) PLL Counter -AT91C_CKGR_OUT EQU (0x3 << 14) ;- (CKGR) PLL Output Frequency Range -AT91C_CKGR_OUT_0 EQU (0x0 << 14) ;- (CKGR) Please refer to the PLL datasheet -AT91C_CKGR_OUT_1 EQU (0x1 << 14) ;- (CKGR) Please refer to the PLL datasheet -AT91C_CKGR_OUT_2 EQU (0x2 << 14) ;- (CKGR) Please refer to the PLL datasheet -AT91C_CKGR_OUT_3 EQU (0x3 << 14) ;- (CKGR) Please refer to the PLL datasheet -AT91C_CKGR_MUL EQU (0x7FF << 16) ;- (CKGR) PLL Multiplier -AT91C_CKGR_USBDIV EQU (0x3 << 28) ;- (CKGR) Divider for USB Clocks -AT91C_CKGR_USBDIV_0 EQU (0x0 << 28) ;- (CKGR) Divider output is PLL clock output -AT91C_CKGR_USBDIV_1 EQU (0x1 << 28) ;- (CKGR) Divider output is PLL clock output divided by 2 -AT91C_CKGR_USBDIV_2 EQU (0x2 << 28) ;- (CKGR) Divider output is PLL clock output divided by 4 +/* - ***************************************************************************** */ +/* - SOFTWARE API DEFINITION FOR Clock Generator Controller */ +/* - ***************************************************************************** */ +/* - -------- CKGR_MOR : (CKGR Offset: 0x0) Main Oscillator Register -------- */ +AT91C_CKGR_MOSCEN EQU( 0x1 << 0 ); +-( CKGR ) Main Oscillator Enable +AT91C_CKGR_OSCBYPASS EQU( 0x1 << 1 ); +-( CKGR ) Main Oscillator Bypass +AT91C_CKGR_OSCOUNT EQU( 0xFF << 8 ); +-( CKGR ) Main Oscillator Start - up Time +/* - -------- CKGR_MCFR : (CKGR Offset: 0x4) Main Clock Frequency Register -------- */ +AT91C_CKGR_MAINF EQU( 0xFFFF << 0 ); +-( CKGR ) Main Clock Frequency +AT91C_CKGR_MAINRDY EQU( 0x1 << 16 ); +-( CKGR ) Main Clock Ready +/* - -------- CKGR_PLLR : (CKGR Offset: 0xc) PLL B Register -------- */ +AT91C_CKGR_DIV EQU( 0xFF << 0 ); +-( CKGR ) Divider Selected +AT91C_CKGR_DIV_0 EQU( 0x0 ); +-( CKGR ) Divider output is 0 +AT91C_CKGR_DIV_BYPASS EQU( 0x1 ); +-( CKGR ) Divider is bypassed +AT91C_CKGR_PLLCOUNT EQU( 0x3F << 8 ); +-( CKGR ) PLL Counter +AT91C_CKGR_OUT EQU( 0x3 << 14 ); +-( CKGR ) PLL Output Frequency Range +AT91C_CKGR_OUT_0 EQU( 0x0 << 14 ); +-( CKGR ) Please refer to the PLL datasheet +AT91C_CKGR_OUT_1 EQU( 0x1 << 14 ); +-( CKGR ) Please refer to the PLL datasheet +AT91C_CKGR_OUT_2 EQU( 0x2 << 14 ); +-( CKGR ) Please refer to the PLL datasheet +AT91C_CKGR_OUT_3 EQU( 0x3 << 14 ); +-( CKGR ) Please refer to the PLL datasheet +AT91C_CKGR_MUL EQU( 0x7FF << 16 ); +-( CKGR ) PLL Multiplier +AT91C_CKGR_USBDIV EQU( 0x3 << 28 ); +-( CKGR ) Divider -// - ***************************************************************************** -// - SOFTWARE API DEFINITION FOR Power Management Controler -// - ***************************************************************************** -// - -------- PMC_SCER : (PMC Offset: 0x0) System Clock Enable Register -------- -AT91C_PMC_PCK EQU (0x1 << 0) ;- (PMC) Processor Clock -AT91C_PMC_UDP EQU (0x1 << 7) ;- (PMC) USB Device Port Clock -AT91C_PMC_PCK0 EQU (0x1 << 8) ;- (PMC) Programmable Clock Output -AT91C_PMC_PCK1 EQU (0x1 << 9) ;- (PMC) Programmable Clock Output -AT91C_PMC_PCK2 EQU (0x1 << 10) ;- (PMC) Programmable Clock Output -AT91C_PMC_PCK3 EQU (0x1 << 11) ;- (PMC) Programmable Clock Output -// - -------- PMC_SCDR : (PMC Offset: 0x4) System Clock Disable Register -------- -// - -------- PMC_SCSR : (PMC Offset: 0x8) System Clock Status Register -------- -// - -------- CKGR_MOR : (PMC Offset: 0x20) Main Oscillator Register -------- -// - -------- CKGR_MCFR : (PMC Offset: 0x24) Main Clock Frequency Register -------- -// - -------- CKGR_PLLR : (PMC Offset: 0x2c) PLL B Register -------- -// - -------- PMC_MCKR : (PMC Offset: 0x30) Master Clock Register -------- -AT91C_PMC_CSS EQU (0x3 << 0) ;- (PMC) Programmable Clock Selection -AT91C_PMC_CSS_SLOW_CLK EQU (0x0) ;- (PMC) Slow Clock is selected -AT91C_PMC_CSS_MAIN_CLK EQU (0x1) ;- (PMC) Main Clock is selected -AT91C_PMC_CSS_PLL_CLK EQU (0x3) ;- (PMC) Clock from PLL is selected -AT91C_PMC_PRES EQU (0x7 << 2) ;- (PMC) Programmable Clock Prescaler -AT91C_PMC_PRES_CLK EQU (0x0 << 2) ;- (PMC) Selected clock -AT91C_PMC_PRES_CLK_2 EQU (0x1 << 2) ;- (PMC) Selected clock divided by 2 -AT91C_PMC_PRES_CLK_4 EQU (0x2 << 2) ;- (PMC) Selected clock divided by 4 -AT91C_PMC_PRES_CLK_8 EQU (0x3 << 2) ;- (PMC) Selected clock divided by 8 -AT91C_PMC_PRES_CLK_16 EQU (0x4 << 2) ;- (PMC) Selected clock divided by 16 -AT91C_PMC_PRES_CLK_32 EQU (0x5 << 2) ;- (PMC) Selected clock divided by 32 -AT91C_PMC_PRES_CLK_64 EQU (0x6 << 2) ;- (PMC) Selected clock divided by 64 -// - -------- PMC_PCKR : (PMC Offset: 0x40) Programmable Clock Register -------- -// - -------- PMC_IER : (PMC Offset: 0x60) PMC Interrupt Enable Register -------- -AT91C_PMC_MOSCS EQU (0x1 << 0) ;- (PMC) MOSC Status/Enable/Disable/Mask -AT91C_PMC_LOCK EQU (0x1 << 2) ;- (PMC) PLL Status/Enable/Disable/Mask -AT91C_PMC_MCKRDY EQU (0x1 << 3) ;- (PMC) MCK_RDY Status/Enable/Disable/Mask -AT91C_PMC_PCK0RDY EQU (0x1 << 8) ;- (PMC) PCK0_RDY Status/Enable/Disable/Mask -AT91C_PMC_PCK1RDY EQU (0x1 << 9) ;- (PMC) PCK1_RDY Status/Enable/Disable/Mask -AT91C_PMC_PCK2RDY EQU (0x1 << 10) ;- (PMC) PCK2_RDY Status/Enable/Disable/Mask -AT91C_PMC_PCK3RDY EQU (0x1 << 11) ;- (PMC) PCK3_RDY Status/Enable/Disable/Mask -// - -------- PMC_IDR : (PMC Offset: 0x64) PMC Interrupt Disable Register -------- -// - -------- PMC_SR : (PMC Offset: 0x68) PMC Status Register -------- -// - -------- PMC_IMR : (PMC Offset: 0x6c) PMC Interrupt Mask Register -------- +for USB Clocks +AT91C_CKGR_USBDIV_0 EQU( 0x0 << 28 ); +-( CKGR ) Divider output is PLL clock output +AT91C_CKGR_USBDIV_1 EQU( 0x1 << 28 ); +-( CKGR ) Divider output is PLL clock output divided by 2 +AT91C_CKGR_USBDIV_2 EQU( 0x2 << 28 ); +-( CKGR ) Divider output is PLL clock output divided by 4 -// - ***************************************************************************** -// - SOFTWARE API DEFINITION FOR Reset Controller Interface -// - ***************************************************************************** -// - -------- RSTC_RCR : (RSTC Offset: 0x0) Reset Control Register -------- -AT91C_RSTC_PROCRST EQU (0x1 << 0) ;- (RSTC) Processor Reset -AT91C_RSTC_PERRST EQU (0x1 << 2) ;- (RSTC) Peripheral Reset -AT91C_RSTC_EXTRST EQU (0x1 << 3) ;- (RSTC) External Reset -AT91C_RSTC_KEY EQU (0xFF << 24) ;- (RSTC) Password -// - -------- RSTC_RSR : (RSTC Offset: 0x4) Reset Status Register -------- -AT91C_RSTC_URSTS EQU (0x1 << 0) ;- (RSTC) User Reset Status -AT91C_RSTC_BODSTS EQU (0x1 << 1) ;- (RSTC) Brownout Detection Status -AT91C_RSTC_RSTTYP EQU (0x7 << 8) ;- (RSTC) Reset Type -AT91C_RSTC_RSTTYP_POWERUP EQU (0x0 << 8) ;- (RSTC) Power-up Reset. VDDCORE rising. -AT91C_RSTC_RSTTYP_WAKEUP EQU (0x1 << 8) ;- (RSTC) WakeUp Reset. VDDCORE rising. -AT91C_RSTC_RSTTYP_WATCHDOG EQU (0x2 << 8) ;- (RSTC) Watchdog Reset. Watchdog overflow occured. -AT91C_RSTC_RSTTYP_SOFTWARE EQU (0x3 << 8) ;- (RSTC) Software Reset. Processor reset required by the software. -AT91C_RSTC_RSTTYP_USER EQU (0x4 << 8) ;- (RSTC) User Reset. NRST pin detected low. -AT91C_RSTC_RSTTYP_BROWNOUT EQU (0x5 << 8) ;- (RSTC) Brownout Reset occured. -AT91C_RSTC_NRSTL EQU (0x1 << 16) ;- (RSTC) NRST pin level -AT91C_RSTC_SRCMP EQU (0x1 << 17) ;- (RSTC) Software Reset Command in Progress. -// - -------- RSTC_RMR : (RSTC Offset: 0x8) Reset Mode Register -------- -AT91C_RSTC_URSTEN EQU (0x1 << 0) ;- (RSTC) User Reset Enable -AT91C_RSTC_URSTIEN EQU (0x1 << 4) ;- (RSTC) User Reset Interrupt Enable -AT91C_RSTC_ERSTL EQU (0xF << 8) ;- (RSTC) User Reset Enable -AT91C_RSTC_BODIEN EQU (0x1 << 16) ;- (RSTC) Brownout Detection Interrupt Enable +/* - ***************************************************************************** */ +/* - SOFTWARE API DEFINITION FOR Power Management Controller */ +/* - ***************************************************************************** */ +/* - -------- PMC_SCER : (PMC Offset: 0x0) System Clock Enable Register -------- */ +AT91C_PMC_PCK EQU( 0x1 << 0 ); +-( PMC ) Processor Clock +AT91C_PMC_UDP EQU( 0x1 << 7 ); +-( PMC ) USB Device Port Clock +AT91C_PMC_PCK0 EQU( 0x1 << 8 ); +-( PMC ) Programmable Clock Output +AT91C_PMC_PCK1 EQU( 0x1 << 9 ); +-( PMC ) Programmable Clock Output +AT91C_PMC_PCK2 EQU( 0x1 << 10 ); +-( PMC ) Programmable Clock Output +AT91C_PMC_PCK3 EQU( 0x1 << 11 ); +-( PMC ) Programmable Clock Output +/* - -------- PMC_SCDR : (PMC Offset: 0x4) System Clock Disable Register -------- */ +/* - -------- PMC_SCSR : (PMC Offset: 0x8) System Clock Status Register -------- */ +/* - -------- CKGR_MOR : (PMC Offset: 0x20) Main Oscillator Register -------- */ +/* - -------- CKGR_MCFR : (PMC Offset: 0x24) Main Clock Frequency Register -------- */ +/* - -------- CKGR_PLLR : (PMC Offset: 0x2c) PLL B Register -------- */ +/* - -------- PMC_MCKR : (PMC Offset: 0x30) Master Clock Register -------- */ +AT91C_PMC_CSS EQU( 0x3 << 0 ); +-( PMC ) Programmable Clock Selection +AT91C_PMC_CSS_SLOW_CLK EQU( 0x0 ); +-( PMC ) Slow Clock is selected +AT91C_PMC_CSS_MAIN_CLK EQU( 0x1 ); +-( PMC ) Main Clock is selected +AT91C_PMC_CSS_PLL_CLK EQU( 0x3 ); +-( PMC ) Clock from PLL is selected +AT91C_PMC_PRES EQU( 0x7 << 2 ); +-( PMC ) Programmable Clock Prescaler +AT91C_PMC_PRES_CLK EQU( 0x0 << 2 ); +-( PMC ) Selected clock +AT91C_PMC_PRES_CLK_2 EQU( 0x1 << 2 ); +-( PMC ) Selected clock divided by 2 +AT91C_PMC_PRES_CLK_4 EQU( 0x2 << 2 ); +-( PMC ) Selected clock divided by 4 +AT91C_PMC_PRES_CLK_8 EQU( 0x3 << 2 ); +-( PMC ) Selected clock divided by 8 +AT91C_PMC_PRES_CLK_16 EQU( 0x4 << 2 ); +-( PMC ) Selected clock divided by 16 +AT91C_PMC_PRES_CLK_32 EQU( 0x5 << 2 ); +-( PMC ) Selected clock divided by 32 +AT91C_PMC_PRES_CLK_64 EQU( 0x6 << 2 ); +-( PMC ) Selected clock divided by 64 +/* - -------- PMC_PCKR : (PMC Offset: 0x40) Programmable Clock Register -------- */ +/* - -------- PMC_IER : (PMC Offset: 0x60) PMC Interrupt Enable Register -------- */ +AT91C_PMC_MOSCS EQU( 0x1 << 0 ); +-( PMC ) MOSC Status / Enable / Disable / Mask +AT91C_PMC_LOCK EQU( 0x1 << 2 ); +-( PMC ) PLL Status / Enable / Disable / Mask +AT91C_PMC_MCKRDY EQU( 0x1 << 3 ); +-( PMC ) MCK_RDY Status / Enable / Disable / Mask +AT91C_PMC_PCK0RDY EQU( 0x1 << 8 ); +-( PMC ) PCK0_RDY Status / Enable / Disable / Mask +AT91C_PMC_PCK1RDY EQU( 0x1 << 9 ); +-( PMC ) PCK1_RDY Status / Enable / Disable / Mask +AT91C_PMC_PCK2RDY EQU( 0x1 << 10 ); +-( PMC ) PCK2_RDY Status / Enable / Disable / Mask +AT91C_PMC_PCK3RDY EQU( 0x1 << 11 ); +-( PMC ) PCK3_RDY Status / Enable / Disable / Mask +/* - -------- PMC_IDR : (PMC Offset: 0x64) PMC Interrupt Disable Register -------- */ +/* - -------- PMC_SR : (PMC Offset: 0x68) PMC Status Register -------- */ +/* - -------- PMC_IMR : (PMC Offset: 0x6c) PMC Interrupt Mask Register -------- */ -// - ***************************************************************************** -// - SOFTWARE API DEFINITION FOR Real Time Timer Controller Interface -// - ***************************************************************************** -// - -------- RTTC_RTMR : (RTTC Offset: 0x0) Real-time Mode Register -------- -AT91C_RTTC_RTPRES EQU (0xFFFF << 0) ;- (RTTC) Real-time Timer Prescaler Value -AT91C_RTTC_ALMIEN EQU (0x1 << 16) ;- (RTTC) Alarm Interrupt Enable -AT91C_RTTC_RTTINCIEN EQU (0x1 << 17) ;- (RTTC) Real Time Timer Increment Interrupt Enable -AT91C_RTTC_RTTRST EQU (0x1 << 18) ;- (RTTC) Real Time Timer Restart -// - -------- RTTC_RTAR : (RTTC Offset: 0x4) Real-time Alarm Register -------- -AT91C_RTTC_ALMV EQU (0x0 << 0) ;- (RTTC) Alarm Value -// - -------- RTTC_RTVR : (RTTC Offset: 0x8) Current Real-time Value Register -------- -AT91C_RTTC_CRTV EQU (0x0 << 0) ;- (RTTC) Current Real-time Value -// - -------- RTTC_RTSR : (RTTC Offset: 0xc) Real-time Status Register -------- -AT91C_RTTC_ALMS EQU (0x1 << 0) ;- (RTTC) Real-time Alarm Status -AT91C_RTTC_RTTINC EQU (0x1 << 1) ;- (RTTC) Real-time Timer Increment +/* - ***************************************************************************** */ +/* - SOFTWARE API DEFINITION FOR Reset Controller Interface */ +/* - ***************************************************************************** */ +/* - -------- RSTC_RCR : (RSTC Offset: 0x0) Reset Control Register -------- */ +AT91C_RSTC_PROCRST EQU( 0x1 << 0 ); +-( RSTC ) Processor Reset +AT91C_RSTC_PERRST EQU( 0x1 << 2 ); +-( RSTC ) Peripheral Reset +AT91C_RSTC_EXTRST EQU( 0x1 << 3 ); +-( RSTC ) External Reset +AT91C_RSTC_KEY EQU( 0xFF << 24 ); +-( RSTC ) Password +/* - -------- RSTC_RSR : (RSTC Offset: 0x4) Reset Status Register -------- */ +AT91C_RSTC_URSTS EQU( 0x1 << 0 ); +-( RSTC ) User Reset Status +AT91C_RSTC_BODSTS EQU( 0x1 << 1 ); +-( RSTC ) Brownout Detection Status +AT91C_RSTC_RSTTYP EQU( 0x7 << 8 ); +-( RSTC ) Reset Type +AT91C_RSTC_RSTTYP_POWERUP EQU( 0x0 << 8 ); +-( RSTC ) Power - up Reset.VDDCORE rising. + AT91C_RSTC_RSTTYP_WAKEUP EQU( 0x1 << 8 ); +-( RSTC ) WakeUp Reset.VDDCORE rising. + AT91C_RSTC_RSTTYP_WATCHDOG EQU( 0x2 << 8 ); +-( RSTC ) Watchdog Reset.Watchdog overflow occurred. + AT91C_RSTC_RSTTYP_SOFTWARE EQU( 0x3 << 8 ); +-( RSTC ) Software Reset.Processor reset required by the software. + AT91C_RSTC_RSTTYP_USER EQU( 0x4 << 8 ); +-( RSTC ) User Reset.NRST pin detected low. + AT91C_RSTC_RSTTYP_BROWNOUT EQU( 0x5 << 8 ); +-( RSTC ) Brownout Reset occurred. + AT91C_RSTC_NRSTL EQU( 0x1 << 16 ); +-( RSTC ) NRST pin level +AT91C_RSTC_SRCMP EQU( 0x1 << 17 ); +-( RSTC ) Software Reset Command in Progress. +/* - -------- RSTC_RMR : (RSTC Offset: 0x8) Reset Mode Register -------- */ + AT91C_RSTC_URSTEN EQU( 0x1 << 0 ); +-( RSTC ) User Reset Enable +AT91C_RSTC_URSTIEN EQU( 0x1 << 4 ); +-( RSTC ) User Reset Interrupt Enable +AT91C_RSTC_ERSTL EQU( 0xF << 8 ); +-( RSTC ) User Reset Enable +AT91C_RSTC_BODIEN EQU( 0x1 << 16 ); +-( RSTC ) Brownout Detection Interrupt Enable -// - ***************************************************************************** -// - SOFTWARE API DEFINITION FOR Periodic Interval Timer Controller Interface -// - ***************************************************************************** -// - -------- PITC_PIMR : (PITC Offset: 0x0) Periodic Interval Mode Register -------- -AT91C_PITC_PIV EQU (0xFFFFF << 0) ;- (PITC) Periodic Interval Value -AT91C_PITC_PITEN EQU (0x1 << 24) ;- (PITC) Periodic Interval Timer Enabled -AT91C_PITC_PITIEN EQU (0x1 << 25) ;- (PITC) Periodic Interval Timer Interrupt Enable -// - -------- PITC_PISR : (PITC Offset: 0x4) Periodic Interval Status Register -------- -AT91C_PITC_PITS EQU (0x1 << 0) ;- (PITC) Periodic Interval Timer Status -// - -------- PITC_PIVR : (PITC Offset: 0x8) Periodic Interval Value Register -------- -AT91C_PITC_CPIV EQU (0xFFFFF << 0) ;- (PITC) Current Periodic Interval Value -AT91C_PITC_PICNT EQU (0xFFF << 20) ;- (PITC) Periodic Interval Counter -// - -------- PITC_PIIR : (PITC Offset: 0xc) Periodic Interval Image Register -------- +/* - ***************************************************************************** */ +/* - SOFTWARE API DEFINITION FOR Real Time Timer Controller Interface */ +/* - ***************************************************************************** */ +/* - -------- RTTC_RTMR : (RTTC Offset: 0x0) Real-time Mode Register -------- */ +AT91C_RTTC_RTPRES EQU( 0xFFFF << 0 ); +-( RTTC ) Real - time Timer Prescaler Value +AT91C_RTTC_ALMIEN EQU( 0x1 << 16 ); +-( RTTC ) Alarm Interrupt Enable +AT91C_RTTC_RTTINCIEN EQU( 0x1 << 17 ); +-( RTTC ) Real Time Timer Increment Interrupt Enable +AT91C_RTTC_RTTRST EQU( 0x1 << 18 ); +-( RTTC ) Real Time Timer Restart +/* - -------- RTTC_RTAR : (RTTC Offset: 0x4) Real-time Alarm Register -------- */ +AT91C_RTTC_ALMV EQU( 0x0 << 0 ); +-( RTTC ) Alarm Value +/* - -------- RTTC_RTVR : (RTTC Offset: 0x8) Current Real-time Value Register -------- */ +AT91C_RTTC_CRTV EQU( 0x0 << 0 ); +-( RTTC ) Current Real - time Value +/* - -------- RTTC_RTSR : (RTTC Offset: 0xc) Real-time Status Register -------- */ +AT91C_RTTC_ALMS EQU( 0x1 << 0 ); +-( RTTC ) Real - time Alarm Status +AT91C_RTTC_RTTINC EQU( 0x1 << 1 ); +-( RTTC ) Real - time Timer Increment -// - ***************************************************************************** -// - SOFTWARE API DEFINITION FOR Watchdog Timer Controller Interface -// - ***************************************************************************** -// - -------- WDTC_WDCR : (WDTC Offset: 0x0) Periodic Interval Image Register -------- -AT91C_WDTC_WDRSTT EQU (0x1 << 0) ;- (WDTC) Watchdog Restart -AT91C_WDTC_KEY EQU (0xFF << 24) ;- (WDTC) Watchdog KEY Password -// - -------- WDTC_WDMR : (WDTC Offset: 0x4) Watchdog Mode Register -------- -AT91C_WDTC_WDV EQU (0xFFF << 0) ;- (WDTC) Watchdog Timer Restart -AT91C_WDTC_WDFIEN EQU (0x1 << 12) ;- (WDTC) Watchdog Fault Interrupt Enable -AT91C_WDTC_WDRSTEN EQU (0x1 << 13) ;- (WDTC) Watchdog Reset Enable -AT91C_WDTC_WDRPROC EQU (0x1 << 14) ;- (WDTC) Watchdog Timer Restart -AT91C_WDTC_WDDIS EQU (0x1 << 15) ;- (WDTC) Watchdog Disable -AT91C_WDTC_WDD EQU (0xFFF << 16) ;- (WDTC) Watchdog Delta Value -AT91C_WDTC_WDDBGHLT EQU (0x1 << 28) ;- (WDTC) Watchdog Debug Halt -AT91C_WDTC_WDIDLEHLT EQU (0x1 << 29) ;- (WDTC) Watchdog Idle Halt -// - -------- WDTC_WDSR : (WDTC Offset: 0x8) Watchdog Status Register -------- -AT91C_WDTC_WDUNF EQU (0x1 << 0) ;- (WDTC) Watchdog Underflow -AT91C_WDTC_WDERR EQU (0x1 << 1) ;- (WDTC) Watchdog Error +/* - ***************************************************************************** */ +/* - SOFTWARE API DEFINITION FOR Periodic Interval Timer Controller Interface */ +/* - ***************************************************************************** */ +/* - -------- PITC_PIMR : (PITC Offset: 0x0) Periodic Interval Mode Register -------- */ +AT91C_PITC_PIV EQU( 0xFFFFF << 0 ); +-( PITC ) Periodic Interval Value +AT91C_PITC_PITEN EQU( 0x1 << 24 ); +-( PITC ) Periodic Interval Timer Enabled +AT91C_PITC_PITIEN EQU( 0x1 << 25 ); +-( PITC ) Periodic Interval Timer Interrupt Enable +/* - -------- PITC_PISR : (PITC Offset: 0x4) Periodic Interval Status Register -------- */ +AT91C_PITC_PITS EQU( 0x1 << 0 ); +-( PITC ) Periodic Interval Timer Status +/* - -------- PITC_PIVR : (PITC Offset: 0x8) Periodic Interval Value Register -------- */ +AT91C_PITC_CPIV EQU( 0xFFFFF << 0 ); +-( PITC ) Current Periodic Interval Value +AT91C_PITC_PICNT EQU( 0xFFF << 20 ); +-( PITC ) Periodic Interval Counter +/* - -------- PITC_PIIR : (PITC Offset: 0xc) Periodic Interval Image Register -------- */ -// - ***************************************************************************** -// - SOFTWARE API DEFINITION FOR Voltage Regulator Mode Controller Interface -// - ***************************************************************************** -// - -------- VREG_MR : (VREG Offset: 0x0) Voltage Regulator Mode Register -------- -AT91C_VREG_PSTDBY EQU (0x1 << 0) ;- (VREG) Voltage Regulator Power Standby Mode +/* - ***************************************************************************** */ +/* - SOFTWARE API DEFINITION FOR Watchdog Timer Controller Interface */ +/* - ***************************************************************************** */ +/* - -------- WDTC_WDCR : (WDTC Offset: 0x0) Periodic Interval Image Register -------- */ +AT91C_WDTC_WDRSTT EQU( 0x1 << 0 ); +-( WDTC ) Watchdog Restart +AT91C_WDTC_KEY EQU( 0xFF << 24 ); +-( WDTC ) Watchdog KEY Password +/* - -------- WDTC_WDMR : (WDTC Offset: 0x4) Watchdog Mode Register -------- */ +AT91C_WDTC_WDV EQU( 0xFFF << 0 ); +-( WDTC ) Watchdog Timer Restart +AT91C_WDTC_WDFIEN EQU( 0x1 << 12 ); +-( WDTC ) Watchdog Fault Interrupt Enable +AT91C_WDTC_WDRSTEN EQU( 0x1 << 13 ); +-( WDTC ) Watchdog Reset Enable +AT91C_WDTC_WDRPROC EQU( 0x1 << 14 ); +-( WDTC ) Watchdog Timer Restart +AT91C_WDTC_WDDIS EQU( 0x1 << 15 ); +-( WDTC ) Watchdog Disable +AT91C_WDTC_WDD EQU( 0xFFF << 16 ); +-( WDTC ) Watchdog Delta Value +AT91C_WDTC_WDDBGHLT EQU( 0x1 << 28 ); +-( WDTC ) Watchdog Debug Halt +AT91C_WDTC_WDIDLEHLT EQU( 0x1 << 29 ); +-( WDTC ) Watchdog Idle Halt +/* - -------- WDTC_WDSR : (WDTC Offset: 0x8) Watchdog Status Register -------- */ +AT91C_WDTC_WDUNF EQU( 0x1 << 0 ); +-( WDTC ) Watchdog Underflow +AT91C_WDTC_WDERR EQU( 0x1 << 1 ); +-( WDTC ) Watchdog Error -// - ***************************************************************************** -// - SOFTWARE API DEFINITION FOR Memory Controller Interface -// - ***************************************************************************** -// - -------- MC_RCR : (MC Offset: 0x0) MC Remap Control Register -------- -AT91C_MC_RCB EQU (0x1 << 0) ;- (MC) Remap Command Bit -// - -------- MC_ASR : (MC Offset: 0x4) MC Abort Status Register -------- -AT91C_MC_UNDADD EQU (0x1 << 0) ;- (MC) Undefined Addess Abort Status -AT91C_MC_MISADD EQU (0x1 << 1) ;- (MC) Misaligned Addess Abort Status -AT91C_MC_ABTSZ EQU (0x3 << 8) ;- (MC) Abort Size Status -AT91C_MC_ABTSZ_BYTE EQU (0x0 << 8) ;- (MC) Byte -AT91C_MC_ABTSZ_HWORD EQU (0x1 << 8) ;- (MC) Half-word -AT91C_MC_ABTSZ_WORD EQU (0x2 << 8) ;- (MC) Word -AT91C_MC_ABTTYP EQU (0x3 << 10) ;- (MC) Abort Type Status -AT91C_MC_ABTTYP_DATAR EQU (0x0 << 10) ;- (MC) Data Read -AT91C_MC_ABTTYP_DATAW EQU (0x1 << 10) ;- (MC) Data Write -AT91C_MC_ABTTYP_FETCH EQU (0x2 << 10) ;- (MC) Code Fetch -AT91C_MC_MST0 EQU (0x1 << 16) ;- (MC) Master 0 Abort Source -AT91C_MC_MST1 EQU (0x1 << 17) ;- (MC) Master 1 Abort Source -AT91C_MC_SVMST0 EQU (0x1 << 24) ;- (MC) Saved Master 0 Abort Source -AT91C_MC_SVMST1 EQU (0x1 << 25) ;- (MC) Saved Master 1 Abort Source -// - -------- MC_FMR : (MC Offset: 0x60) MC Flash Mode Register -------- -AT91C_MC_FRDY EQU (0x1 << 0) ;- (MC) Flash Ready -AT91C_MC_LOCKE EQU (0x1 << 2) ;- (MC) Lock Error -AT91C_MC_PROGE EQU (0x1 << 3) ;- (MC) Programming Error -AT91C_MC_NEBP EQU (0x1 << 7) ;- (MC) No Erase Before Programming -AT91C_MC_FWS EQU (0x3 << 8) ;- (MC) Flash Wait State -AT91C_MC_FWS_0FWS EQU (0x0 << 8) ;- (MC) 1 cycle for Read, 2 for Write operations -AT91C_MC_FWS_1FWS EQU (0x1 << 8) ;- (MC) 2 cycles for Read, 3 for Write operations -AT91C_MC_FWS_2FWS EQU (0x2 << 8) ;- (MC) 3 cycles for Read, 4 for Write operations -AT91C_MC_FWS_3FWS EQU (0x3 << 8) ;- (MC) 4 cycles for Read, 4 for Write operations -AT91C_MC_FMCN EQU (0xFF << 16) ;- (MC) Flash Microsecond Cycle Number -// - -------- MC_FCR : (MC Offset: 0x64) MC Flash Command Register -------- -AT91C_MC_FCMD EQU (0xF << 0) ;- (MC) Flash Command -AT91C_MC_FCMD_START_PROG EQU (0x1) ;- (MC) Starts the programming of th epage specified by PAGEN. -AT91C_MC_FCMD_LOCK EQU (0x2) ;- (MC) Starts a lock sequence of the sector defined by the bits 4 to 7 of the field PAGEN. -AT91C_MC_FCMD_PROG_AND_LOCK EQU (0x3) ;- (MC) The lock sequence automatically happens after the programming sequence is completed. -AT91C_MC_FCMD_UNLOCK EQU (0x4) ;- (MC) Starts an unlock sequence of the sector defined by the bits 4 to 7 of the field PAGEN. -AT91C_MC_FCMD_ERASE_ALL EQU (0x8) ;- (MC) Starts the erase of the entire flash.If at least a page is locked, the command is cancelled. -AT91C_MC_FCMD_SET_GP_NVM EQU (0xB) ;- (MC) Set General Purpose NVM bits. -AT91C_MC_FCMD_CLR_GP_NVM EQU (0xD) ;- (MC) Clear General Purpose NVM bits. -AT91C_MC_FCMD_SET_SECURITY EQU (0xF) ;- (MC) Set Security Bit. -AT91C_MC_PAGEN EQU (0x3FF << 8) ;- (MC) Page Number -AT91C_MC_KEY EQU (0xFF << 24) ;- (MC) Writing Protect Key -// - -------- MC_FSR : (MC Offset: 0x68) MC Flash Command Register -------- -AT91C_MC_SECURITY EQU (0x1 << 4) ;- (MC) Security Bit Status -AT91C_MC_GPNVM0 EQU (0x1 << 8) ;- (MC) Sector 0 Lock Status -AT91C_MC_GPNVM1 EQU (0x1 << 9) ;- (MC) Sector 1 Lock Status -AT91C_MC_GPNVM2 EQU (0x1 << 10) ;- (MC) Sector 2 Lock Status -AT91C_MC_GPNVM3 EQU (0x1 << 11) ;- (MC) Sector 3 Lock Status -AT91C_MC_GPNVM4 EQU (0x1 << 12) ;- (MC) Sector 4 Lock Status -AT91C_MC_GPNVM5 EQU (0x1 << 13) ;- (MC) Sector 5 Lock Status -AT91C_MC_GPNVM6 EQU (0x1 << 14) ;- (MC) Sector 6 Lock Status -AT91C_MC_GPNVM7 EQU (0x1 << 15) ;- (MC) Sector 7 Lock Status -AT91C_MC_LOCKS0 EQU (0x1 << 16) ;- (MC) Sector 0 Lock Status -AT91C_MC_LOCKS1 EQU (0x1 << 17) ;- (MC) Sector 1 Lock Status -AT91C_MC_LOCKS2 EQU (0x1 << 18) ;- (MC) Sector 2 Lock Status -AT91C_MC_LOCKS3 EQU (0x1 << 19) ;- (MC) Sector 3 Lock Status -AT91C_MC_LOCKS4 EQU (0x1 << 20) ;- (MC) Sector 4 Lock Status -AT91C_MC_LOCKS5 EQU (0x1 << 21) ;- (MC) Sector 5 Lock Status -AT91C_MC_LOCKS6 EQU (0x1 << 22) ;- (MC) Sector 6 Lock Status -AT91C_MC_LOCKS7 EQU (0x1 << 23) ;- (MC) Sector 7 Lock Status -AT91C_MC_LOCKS8 EQU (0x1 << 24) ;- (MC) Sector 8 Lock Status -AT91C_MC_LOCKS9 EQU (0x1 << 25) ;- (MC) Sector 9 Lock Status -AT91C_MC_LOCKS10 EQU (0x1 << 26) ;- (MC) Sector 10 Lock Status -AT91C_MC_LOCKS11 EQU (0x1 << 27) ;- (MC) Sector 11 Lock Status -AT91C_MC_LOCKS12 EQU (0x1 << 28) ;- (MC) Sector 12 Lock Status -AT91C_MC_LOCKS13 EQU (0x1 << 29) ;- (MC) Sector 13 Lock Status -AT91C_MC_LOCKS14 EQU (0x1 << 30) ;- (MC) Sector 14 Lock Status -AT91C_MC_LOCKS15 EQU (0x1 << 31) ;- (MC) Sector 15 Lock Status +/* - ***************************************************************************** */ +/* - SOFTWARE API DEFINITION FOR Voltage Regulator Mode Controller Interface */ +/* - ***************************************************************************** */ +/* - -------- VREG_MR : (VREG Offset: 0x0) Voltage Regulator Mode Register -------- */ +AT91C_VREG_PSTDBY EQU( 0x1 << 0 ); +-( VREG ) Voltage Regulator Power Standby Mode -// - ***************************************************************************** -// - SOFTWARE API DEFINITION FOR Serial Parallel Interface -// - ***************************************************************************** -// - -------- SPI_CR : (SPI Offset: 0x0) SPI Control Register -------- -AT91C_SPI_SPIEN EQU (0x1 << 0) ;- (SPI) SPI Enable -AT91C_SPI_SPIDIS EQU (0x1 << 1) ;- (SPI) SPI Disable -AT91C_SPI_SWRST EQU (0x1 << 7) ;- (SPI) SPI Software reset -AT91C_SPI_LASTXFER EQU (0x1 << 24) ;- (SPI) SPI Last Transfer -// - -------- SPI_MR : (SPI Offset: 0x4) SPI Mode Register -------- -AT91C_SPI_MSTR EQU (0x1 << 0) ;- (SPI) Master/Slave Mode -AT91C_SPI_PS EQU (0x1 << 1) ;- (SPI) Peripheral Select -AT91C_SPI_PS_FIXED EQU (0x0 << 1) ;- (SPI) Fixed Peripheral Select -AT91C_SPI_PS_VARIABLE EQU (0x1 << 1) ;- (SPI) Variable Peripheral Select -AT91C_SPI_PCSDEC EQU (0x1 << 2) ;- (SPI) Chip Select Decode -AT91C_SPI_FDIV EQU (0x1 << 3) ;- (SPI) Clock Selection -AT91C_SPI_MODFDIS EQU (0x1 << 4) ;- (SPI) Mode Fault Detection -AT91C_SPI_LLB EQU (0x1 << 7) ;- (SPI) Clock Selection -AT91C_SPI_PCS EQU (0xF << 16) ;- (SPI) Peripheral Chip Select -AT91C_SPI_DLYBCS EQU (0xFF << 24) ;- (SPI) Delay Between Chip Selects -// - -------- SPI_RDR : (SPI Offset: 0x8) Receive Data Register -------- -AT91C_SPI_RD EQU (0xFFFF << 0) ;- (SPI) Receive Data -AT91C_SPI_RPCS EQU (0xF << 16) ;- (SPI) Peripheral Chip Select Status -// - -------- SPI_TDR : (SPI Offset: 0xc) Transmit Data Register -------- -AT91C_SPI_TD EQU (0xFFFF << 0) ;- (SPI) Transmit Data -AT91C_SPI_TPCS EQU (0xF << 16) ;- (SPI) Peripheral Chip Select Status -// - -------- SPI_SR : (SPI Offset: 0x10) Status Register -------- -AT91C_SPI_RDRF EQU (0x1 << 0) ;- (SPI) Receive Data Register Full -AT91C_SPI_TDRE EQU (0x1 << 1) ;- (SPI) Transmit Data Register Empty -AT91C_SPI_MODF EQU (0x1 << 2) ;- (SPI) Mode Fault Error -AT91C_SPI_OVRES EQU (0x1 << 3) ;- (SPI) Overrun Error Status -AT91C_SPI_ENDRX EQU (0x1 << 4) ;- (SPI) End of Receiver Transfer -AT91C_SPI_ENDTX EQU (0x1 << 5) ;- (SPI) End of Receiver Transfer -AT91C_SPI_RXBUFF EQU (0x1 << 6) ;- (SPI) RXBUFF Interrupt -AT91C_SPI_TXBUFE EQU (0x1 << 7) ;- (SPI) TXBUFE Interrupt -AT91C_SPI_NSSR EQU (0x1 << 8) ;- (SPI) NSSR Interrupt -AT91C_SPI_TXEMPTY EQU (0x1 << 9) ;- (SPI) TXEMPTY Interrupt -AT91C_SPI_SPIENS EQU (0x1 << 16) ;- (SPI) Enable Status -// - -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register -------- -// - -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register -------- -// - -------- SPI_IMR : (SPI Offset: 0x1c) Interrupt Mask Register -------- -// - -------- SPI_CSR : (SPI Offset: 0x30) Chip Select Register -------- -AT91C_SPI_CPOL EQU (0x1 << 0) ;- (SPI) Clock Polarity -AT91C_SPI_NCPHA EQU (0x1 << 1) ;- (SPI) Clock Phase -AT91C_SPI_CSAAT EQU (0x1 << 3) ;- (SPI) Chip Select Active After Transfer -AT91C_SPI_BITS EQU (0xF << 4) ;- (SPI) Bits Per Transfer -AT91C_SPI_BITS_8 EQU (0x0 << 4) ;- (SPI) 8 Bits Per transfer -AT91C_SPI_BITS_9 EQU (0x1 << 4) ;- (SPI) 9 Bits Per transfer -AT91C_SPI_BITS_10 EQU (0x2 << 4) ;- (SPI) 10 Bits Per transfer -AT91C_SPI_BITS_11 EQU (0x3 << 4) ;- (SPI) 11 Bits Per transfer -AT91C_SPI_BITS_12 EQU (0x4 << 4) ;- (SPI) 12 Bits Per transfer -AT91C_SPI_BITS_13 EQU (0x5 << 4) ;- (SPI) 13 Bits Per transfer -AT91C_SPI_BITS_14 EQU (0x6 << 4) ;- (SPI) 14 Bits Per transfer -AT91C_SPI_BITS_15 EQU (0x7 << 4) ;- (SPI) 15 Bits Per transfer -AT91C_SPI_BITS_16 EQU (0x8 << 4) ;- (SPI) 16 Bits Per transfer -AT91C_SPI_SCBR EQU (0xFF << 8) ;- (SPI) Serial Clock Baud Rate -AT91C_SPI_DLYBS EQU (0xFF << 16) ;- (SPI) Delay Before SPCK -AT91C_SPI_DLYBCT EQU (0xFF << 24) ;- (SPI) Delay Between Consecutive Transfers +/* - ***************************************************************************** */ +/* - SOFTWARE API DEFINITION FOR Memory Controller Interface */ +/* - ***************************************************************************** */ +/* - -------- MC_RCR : (MC Offset: 0x0) MC Remap Control Register -------- */ +AT91C_MC_RCB EQU( 0x1 << 0 ); +-( MC ) Remap Command Bit +/* - -------- MC_ASR : (MC Offset: 0x4) MC Abort Status Register -------- */ +AT91C_MC_UNDADD EQU( 0x1 << 0 ); +-( MC ) Undefined Addess Abort Status +AT91C_MC_MISADD EQU( 0x1 << 1 ); +-( MC ) Misaligned Addess Abort Status +AT91C_MC_ABTSZ EQU( 0x3 << 8 ); +-( MC ) Abort Size Status +AT91C_MC_ABTSZ_BYTE EQU( 0x0 << 8 ); +-( MC ) Byte +AT91C_MC_ABTSZ_HWORD EQU( 0x1 << 8 ); +-( MC ) Half - word +AT91C_MC_ABTSZ_WORD EQU( 0x2 << 8 ); +-( MC ) Word +AT91C_MC_ABTTYP EQU( 0x3 << 10 ); +-( MC ) Abort Type Status +AT91C_MC_ABTTYP_DATAR EQU( 0x0 << 10 ); +-( MC ) Data Read +AT91C_MC_ABTTYP_DATAW EQU( 0x1 << 10 ); +-( MC ) Data Write +AT91C_MC_ABTTYP_FETCH EQU( 0x2 << 10 ); +-( MC ) Code Fetch +AT91C_MC_MST0 EQU( 0x1 << 16 ); +-( MC ) Master 0 Abort Source +AT91C_MC_MST1 EQU( 0x1 << 17 ); +-( MC ) Master 1 Abort Source +AT91C_MC_SVMST0 EQU( 0x1 << 24 ); +-( MC ) Saved Master 0 Abort Source +AT91C_MC_SVMST1 EQU( 0x1 << 25 ); +-( MC ) Saved Master 1 Abort Source +/* - -------- MC_FMR : (MC Offset: 0x60) MC Flash Mode Register -------- */ +AT91C_MC_FRDY EQU( 0x1 << 0 ); +-( MC ) Flash Ready +AT91C_MC_LOCKE EQU( 0x1 << 2 ); +-( MC ) Lock Error +AT91C_MC_PROGE EQU( 0x1 << 3 ); +-( MC ) Programming Error +AT91C_MC_NEBP EQU( 0x1 << 7 ); +-( MC ) No Erase Before Programming +AT91C_MC_FWS EQU( 0x3 << 8 ); +-( MC ) Flash Wait State +AT91C_MC_FWS_0FWS EQU( 0x0 << 8 ); +-( MC ) 1 cycle -// - ***************************************************************************** -// - SOFTWARE API DEFINITION FOR Usart -// - ***************************************************************************** -// - -------- US_CR : (USART Offset: 0x0) Debug Unit Control Register -------- -AT91C_US_STTBRK EQU (0x1 << 9) ;- (USART) Start Break -AT91C_US_STPBRK EQU (0x1 << 10) ;- (USART) Stop Break -AT91C_US_STTTO EQU (0x1 << 11) ;- (USART) Start Time-out -AT91C_US_SENDA EQU (0x1 << 12) ;- (USART) Send Address -AT91C_US_RSTIT EQU (0x1 << 13) ;- (USART) Reset Iterations -AT91C_US_RSTNACK EQU (0x1 << 14) ;- (USART) Reset Non Acknowledge -AT91C_US_RETTO EQU (0x1 << 15) ;- (USART) Rearm Time-out -AT91C_US_DTREN EQU (0x1 << 16) ;- (USART) Data Terminal ready Enable -AT91C_US_DTRDIS EQU (0x1 << 17) ;- (USART) Data Terminal ready Disable -AT91C_US_RTSEN EQU (0x1 << 18) ;- (USART) Request to Send enable -AT91C_US_RTSDIS EQU (0x1 << 19) ;- (USART) Request to Send Disable -// - -------- US_MR : (USART Offset: 0x4) Debug Unit Mode Register -------- -AT91C_US_USMODE EQU (0xF << 0) ;- (USART) Usart mode -AT91C_US_USMODE_NORMAL EQU (0x0) ;- (USART) Normal -AT91C_US_USMODE_RS485 EQU (0x1) ;- (USART) RS485 -AT91C_US_USMODE_HWHSH EQU (0x2) ;- (USART) Hardware Handshaking -AT91C_US_USMODE_MODEM EQU (0x3) ;- (USART) Modem -AT91C_US_USMODE_ISO7816_0 EQU (0x4) ;- (USART) ISO7816 protocol: T = 0 -AT91C_US_USMODE_ISO7816_1 EQU (0x6) ;- (USART) ISO7816 protocol: T = 1 -AT91C_US_USMODE_IRDA EQU (0x8) ;- (USART) IrDA -AT91C_US_USMODE_SWHSH EQU (0xC) ;- (USART) Software Handshaking -AT91C_US_CLKS EQU (0x3 << 4) ;- (USART) Clock Selection (Baud Rate generator Input Clock -AT91C_US_CLKS_CLOCK EQU (0x0 << 4) ;- (USART) Clock -AT91C_US_CLKS_FDIV1 EQU (0x1 << 4) ;- (USART) fdiv1 -AT91C_US_CLKS_SLOW EQU (0x2 << 4) ;- (USART) slow_clock (ARM) -AT91C_US_CLKS_EXT EQU (0x3 << 4) ;- (USART) External (SCK) -AT91C_US_CHRL EQU (0x3 << 6) ;- (USART) Clock Selection (Baud Rate generator Input Clock -AT91C_US_CHRL_5_BITS EQU (0x0 << 6) ;- (USART) Character Length: 5 bits -AT91C_US_CHRL_6_BITS EQU (0x1 << 6) ;- (USART) Character Length: 6 bits -AT91C_US_CHRL_7_BITS EQU (0x2 << 6) ;- (USART) Character Length: 7 bits -AT91C_US_CHRL_8_BITS EQU (0x3 << 6) ;- (USART) Character Length: 8 bits -AT91C_US_SYNC EQU (0x1 << 8) ;- (USART) Synchronous Mode Select -AT91C_US_NBSTOP EQU (0x3 << 12) ;- (USART) Number of Stop bits -AT91C_US_NBSTOP_1_BIT EQU (0x0 << 12) ;- (USART) 1 stop bit -AT91C_US_NBSTOP_15_BIT EQU (0x1 << 12) ;- (USART) Asynchronous (SYNC=0) 2 stop bits Synchronous (SYNC=1) 2 stop bits -AT91C_US_NBSTOP_2_BIT EQU (0x2 << 12) ;- (USART) 2 stop bits -AT91C_US_MSBF EQU (0x1 << 16) ;- (USART) Bit Order -AT91C_US_MODE9 EQU (0x1 << 17) ;- (USART) 9-bit Character length -AT91C_US_CKLO EQU (0x1 << 18) ;- (USART) Clock Output Select -AT91C_US_OVER EQU (0x1 << 19) ;- (USART) Over Sampling Mode -AT91C_US_INACK EQU (0x1 << 20) ;- (USART) Inhibit Non Acknowledge -AT91C_US_DSNACK EQU (0x1 << 21) ;- (USART) Disable Successive NACK -AT91C_US_MAX_ITER EQU (0x1 << 24) ;- (USART) Number of Repetitions -AT91C_US_FILTER EQU (0x1 << 28) ;- (USART) Receive Line Filter -// - -------- US_IER : (USART Offset: 0x8) Debug Unit Interrupt Enable Register -------- -AT91C_US_RXBRK EQU (0x1 << 2) ;- (USART) Break Received/End of Break -AT91C_US_TIMEOUT EQU (0x1 << 8) ;- (USART) Receiver Time-out -AT91C_US_ITERATION EQU (0x1 << 10) ;- (USART) Max number of Repetitions Reached -AT91C_US_NACK EQU (0x1 << 13) ;- (USART) Non Acknowledge -AT91C_US_RIIC EQU (0x1 << 16) ;- (USART) Ring INdicator Input Change Flag -AT91C_US_DSRIC EQU (0x1 << 17) ;- (USART) Data Set Ready Input Change Flag -AT91C_US_DCDIC EQU (0x1 << 18) ;- (USART) Data Carrier Flag -AT91C_US_CTSIC EQU (0x1 << 19) ;- (USART) Clear To Send Input Change Flag -// - -------- US_IDR : (USART Offset: 0xc) Debug Unit Interrupt Disable Register -------- -// - -------- US_IMR : (USART Offset: 0x10) Debug Unit Interrupt Mask Register -------- -// - -------- US_CSR : (USART Offset: 0x14) Debug Unit Channel Status Register -------- -AT91C_US_RI EQU (0x1 << 20) ;- (USART) Image of RI Input -AT91C_US_DSR EQU (0x1 << 21) ;- (USART) Image of DSR Input -AT91C_US_DCD EQU (0x1 << 22) ;- (USART) Image of DCD Input -AT91C_US_CTS EQU (0x1 << 23) ;- (USART) Image of CTS Input +for Read, 2 -// - ***************************************************************************** -// - SOFTWARE API DEFINITION FOR Synchronous Serial Controller Interface -// - ***************************************************************************** -// - -------- SSC_CR : (SSC Offset: 0x0) SSC Control Register -------- -AT91C_SSC_RXEN EQU (0x1 << 0) ;- (SSC) Receive Enable -AT91C_SSC_RXDIS EQU (0x1 << 1) ;- (SSC) Receive Disable -AT91C_SSC_TXEN EQU (0x1 << 8) ;- (SSC) Transmit Enable -AT91C_SSC_TXDIS EQU (0x1 << 9) ;- (SSC) Transmit Disable -AT91C_SSC_SWRST EQU (0x1 << 15) ;- (SSC) Software Reset -// - -------- SSC_RCMR : (SSC Offset: 0x10) SSC Receive Clock Mode Register -------- -AT91C_SSC_CKS EQU (0x3 << 0) ;- (SSC) Receive/Transmit Clock Selection -AT91C_SSC_CKS_DIV EQU (0x0) ;- (SSC) Divided Clock -AT91C_SSC_CKS_TK EQU (0x1) ;- (SSC) TK Clock signal -AT91C_SSC_CKS_RK EQU (0x2) ;- (SSC) RK pin -AT91C_SSC_CKO EQU (0x7 << 2) ;- (SSC) Receive/Transmit Clock Output Mode Selection -AT91C_SSC_CKO_NONE EQU (0x0 << 2) ;- (SSC) Receive/Transmit Clock Output Mode: None RK pin: Input-only -AT91C_SSC_CKO_CONTINOUS EQU (0x1 << 2) ;- (SSC) Continuous Receive/Transmit Clock RK pin: Output -AT91C_SSC_CKO_DATA_TX EQU (0x2 << 2) ;- (SSC) Receive/Transmit Clock only during data transfers RK pin: Output -AT91C_SSC_CKI EQU (0x1 << 5) ;- (SSC) Receive/Transmit Clock Inversion -AT91C_SSC_START EQU (0xF << 8) ;- (SSC) Receive/Transmit Start Selection -AT91C_SSC_START_CONTINOUS EQU (0x0 << 8) ;- (SSC) Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data. -AT91C_SSC_START_TX EQU (0x1 << 8) ;- (SSC) Transmit/Receive start -AT91C_SSC_START_LOW_RF EQU (0x2 << 8) ;- (SSC) Detection of a low level on RF input -AT91C_SSC_START_HIGH_RF EQU (0x3 << 8) ;- (SSC) Detection of a high level on RF input -AT91C_SSC_START_FALL_RF EQU (0x4 << 8) ;- (SSC) Detection of a falling edge on RF input -AT91C_SSC_START_RISE_RF EQU (0x5 << 8) ;- (SSC) Detection of a rising edge on RF input -AT91C_SSC_START_LEVEL_RF EQU (0x6 << 8) ;- (SSC) Detection of any level change on RF input -AT91C_SSC_START_EDGE_RF EQU (0x7 << 8) ;- (SSC) Detection of any edge on RF input -AT91C_SSC_START_0 EQU (0x8 << 8) ;- (SSC) Compare 0 -AT91C_SSC_STTDLY EQU (0xFF << 16) ;- (SSC) Receive/Transmit Start Delay -AT91C_SSC_PERIOD EQU (0xFF << 24) ;- (SSC) Receive/Transmit Period Divider Selection -// - -------- SSC_RFMR : (SSC Offset: 0x14) SSC Receive Frame Mode Register -------- -AT91C_SSC_DATLEN EQU (0x1F << 0) ;- (SSC) Data Length -AT91C_SSC_LOOP EQU (0x1 << 5) ;- (SSC) Loop Mode -AT91C_SSC_MSBF EQU (0x1 << 7) ;- (SSC) Most Significant Bit First -AT91C_SSC_DATNB EQU (0xF << 8) ;- (SSC) Data Number per Frame -AT91C_SSC_FSLEN EQU (0xF << 16) ;- (SSC) Receive/Transmit Frame Sync length -AT91C_SSC_FSOS EQU (0x7 << 20) ;- (SSC) Receive/Transmit Frame Sync Output Selection -AT91C_SSC_FSOS_NONE EQU (0x0 << 20) ;- (SSC) Selected Receive/Transmit Frame Sync Signal: None RK pin Input-only -AT91C_SSC_FSOS_NEGATIVE EQU (0x1 << 20) ;- (SSC) Selected Receive/Transmit Frame Sync Signal: Negative Pulse -AT91C_SSC_FSOS_POSITIVE EQU (0x2 << 20) ;- (SSC) Selected Receive/Transmit Frame Sync Signal: Positive Pulse -AT91C_SSC_FSOS_LOW EQU (0x3 << 20) ;- (SSC) Selected Receive/Transmit Frame Sync Signal: Driver Low during data transfer -AT91C_SSC_FSOS_HIGH EQU (0x4 << 20) ;- (SSC) Selected Receive/Transmit Frame Sync Signal: Driver High during data transfer -AT91C_SSC_FSOS_TOGGLE EQU (0x5 << 20) ;- (SSC) Selected Receive/Transmit Frame Sync Signal: Toggling at each start of data transfer -AT91C_SSC_FSEDGE EQU (0x1 << 24) ;- (SSC) Frame Sync Edge Detection -// - -------- SSC_TCMR : (SSC Offset: 0x18) SSC Transmit Clock Mode Register -------- -// - -------- SSC_TFMR : (SSC Offset: 0x1c) SSC Transmit Frame Mode Register -------- -AT91C_SSC_DATDEF EQU (0x1 << 5) ;- (SSC) Data Default Value -AT91C_SSC_FSDEN EQU (0x1 << 23) ;- (SSC) Frame Sync Data Enable -// - -------- SSC_SR : (SSC Offset: 0x40) SSC Status Register -------- -AT91C_SSC_TXRDY EQU (0x1 << 0) ;- (SSC) Transmit Ready -AT91C_SSC_TXEMPTY EQU (0x1 << 1) ;- (SSC) Transmit Empty -AT91C_SSC_ENDTX EQU (0x1 << 2) ;- (SSC) End Of Transmission -AT91C_SSC_TXBUFE EQU (0x1 << 3) ;- (SSC) Transmit Buffer Empty -AT91C_SSC_RXRDY EQU (0x1 << 4) ;- (SSC) Receive Ready -AT91C_SSC_OVRUN EQU (0x1 << 5) ;- (SSC) Receive Overrun -AT91C_SSC_ENDRX EQU (0x1 << 6) ;- (SSC) End of Reception -AT91C_SSC_RXBUFF EQU (0x1 << 7) ;- (SSC) Receive Buffer Full -AT91C_SSC_TXSYN EQU (0x1 << 10) ;- (SSC) Transmit Sync -AT91C_SSC_RXSYN EQU (0x1 << 11) ;- (SSC) Receive Sync -AT91C_SSC_TXENA EQU (0x1 << 16) ;- (SSC) Transmit Enable -AT91C_SSC_RXENA EQU (0x1 << 17) ;- (SSC) Receive Enable -// - -------- SSC_IER : (SSC Offset: 0x44) SSC Interrupt Enable Register -------- -// - -------- SSC_IDR : (SSC Offset: 0x48) SSC Interrupt Disable Register -------- -// - -------- SSC_IMR : (SSC Offset: 0x4c) SSC Interrupt Mask Register -------- +for Write operations +AT91C_MC_FWS_1FWS EQU( 0x1 << 8 ); +-( MC ) 2 cycles -// - ***************************************************************************** -// - SOFTWARE API DEFINITION FOR Two-wire Interface -// - ***************************************************************************** -// - -------- TWI_CR : (TWI Offset: 0x0) TWI Control Register -------- -AT91C_TWI_START EQU (0x1 << 0) ;- (TWI) Send a START Condition -AT91C_TWI_STOP EQU (0x1 << 1) ;- (TWI) Send a STOP Condition -AT91C_TWI_MSEN EQU (0x1 << 2) ;- (TWI) TWI Master Transfer Enabled -AT91C_TWI_MSDIS EQU (0x1 << 3) ;- (TWI) TWI Master Transfer Disabled -AT91C_TWI_SWRST EQU (0x1 << 7) ;- (TWI) Software Reset -// - -------- TWI_MMR : (TWI Offset: 0x4) TWI Master Mode Register -------- -AT91C_TWI_IADRSZ EQU (0x3 << 8) ;- (TWI) Internal Device Address Size -AT91C_TWI_IADRSZ_NO EQU (0x0 << 8) ;- (TWI) No internal device address -AT91C_TWI_IADRSZ_1_BYTE EQU (0x1 << 8) ;- (TWI) One-byte internal device address -AT91C_TWI_IADRSZ_2_BYTE EQU (0x2 << 8) ;- (TWI) Two-byte internal device address -AT91C_TWI_IADRSZ_3_BYTE EQU (0x3 << 8) ;- (TWI) Three-byte internal device address -AT91C_TWI_MREAD EQU (0x1 << 12) ;- (TWI) Master Read Direction -AT91C_TWI_DADR EQU (0x7F << 16) ;- (TWI) Device Address -// - -------- TWI_CWGR : (TWI Offset: 0x10) TWI Clock Waveform Generator Register -------- -AT91C_TWI_CLDIV EQU (0xFF << 0) ;- (TWI) Clock Low Divider -AT91C_TWI_CHDIV EQU (0xFF << 8) ;- (TWI) Clock High Divider -AT91C_TWI_CKDIV EQU (0x7 << 16) ;- (TWI) Clock Divider -// - -------- TWI_SR : (TWI Offset: 0x20) TWI Status Register -------- -AT91C_TWI_TXCOMP EQU (0x1 << 0) ;- (TWI) Transmission Completed -AT91C_TWI_RXRDY EQU (0x1 << 1) ;- (TWI) Receive holding register ReaDY -AT91C_TWI_TXRDY EQU (0x1 << 2) ;- (TWI) Transmit holding register ReaDY -AT91C_TWI_OVRE EQU (0x1 << 6) ;- (TWI) Overrun Error -AT91C_TWI_UNRE EQU (0x1 << 7) ;- (TWI) Underrun Error -AT91C_TWI_NACK EQU (0x1 << 8) ;- (TWI) Not Acknowledged -// - -------- TWI_IER : (TWI Offset: 0x24) TWI Interrupt Enable Register -------- -// - -------- TWI_IDR : (TWI Offset: 0x28) TWI Interrupt Disable Register -------- -// - -------- TWI_IMR : (TWI Offset: 0x2c) TWI Interrupt Mask Register -------- +for Read, 3 -// - ***************************************************************************** -// - SOFTWARE API DEFINITION FOR PWMC Channel Interface -// - ***************************************************************************** -// - -------- PWMC_CMR : (PWMC_CH Offset: 0x0) PWMC Channel Mode Register -------- -AT91C_PWMC_CPRE EQU (0xF << 0) ;- (PWMC_CH) Channel Pre-scaler : PWMC_CLKx -AT91C_PWMC_CPRE_MCK EQU (0x0) ;- (PWMC_CH) -AT91C_PWMC_CPRE_MCKA EQU (0xB) ;- (PWMC_CH) -AT91C_PWMC_CPRE_MCKB EQU (0xC) ;- (PWMC_CH) -AT91C_PWMC_CALG EQU (0x1 << 8) ;- (PWMC_CH) Channel Alignment -AT91C_PWMC_CPOL EQU (0x1 << 9) ;- (PWMC_CH) Channel Polarity -AT91C_PWMC_CPD EQU (0x1 << 10) ;- (PWMC_CH) Channel Update Period -// - -------- PWMC_CDTYR : (PWMC_CH Offset: 0x4) PWMC Channel Duty Cycle Register -------- -AT91C_PWMC_CDTY EQU (0x0 << 0) ;- (PWMC_CH) Channel Duty Cycle -// - -------- PWMC_CPRDR : (PWMC_CH Offset: 0x8) PWMC Channel Period Register -------- -AT91C_PWMC_CPRD EQU (0x0 << 0) ;- (PWMC_CH) Channel Period -// - -------- PWMC_CCNTR : (PWMC_CH Offset: 0xc) PWMC Channel Counter Register -------- -AT91C_PWMC_CCNT EQU (0x0 << 0) ;- (PWMC_CH) Channel Counter -// - -------- PWMC_CUPDR : (PWMC_CH Offset: 0x10) PWMC Channel Update Register -------- -AT91C_PWMC_CUPD EQU (0x0 << 0) ;- (PWMC_CH) Channel Update +for Write operations +AT91C_MC_FWS_2FWS EQU( 0x2 << 8 ); +-( MC ) 3 cycles -// - ***************************************************************************** -// - SOFTWARE API DEFINITION FOR Pulse Width Modulation Controller Interface -// - ***************************************************************************** -// - -------- PWMC_MR : (PWMC Offset: 0x0) PWMC Mode Register -------- -AT91C_PWMC_DIVA EQU (0xFF << 0) ;- (PWMC) CLKA divide factor. -AT91C_PWMC_PREA EQU (0xF << 8) ;- (PWMC) Divider Input Clock Prescaler A -AT91C_PWMC_PREA_MCK EQU (0x0 << 8) ;- (PWMC) -AT91C_PWMC_DIVB EQU (0xFF << 16) ;- (PWMC) CLKB divide factor. -AT91C_PWMC_PREB EQU (0xF << 24) ;- (PWMC) Divider Input Clock Prescaler B -AT91C_PWMC_PREB_MCK EQU (0x0 << 24) ;- (PWMC) -// - -------- PWMC_ENA : (PWMC Offset: 0x4) PWMC Enable Register -------- -AT91C_PWMC_CHID0 EQU (0x1 << 0) ;- (PWMC) Channel ID 0 -AT91C_PWMC_CHID1 EQU (0x1 << 1) ;- (PWMC) Channel ID 1 -AT91C_PWMC_CHID2 EQU (0x1 << 2) ;- (PWMC) Channel ID 2 -AT91C_PWMC_CHID3 EQU (0x1 << 3) ;- (PWMC) Channel ID 3 -// - -------- PWMC_DIS : (PWMC Offset: 0x8) PWMC Disable Register -------- -// - -------- PWMC_SR : (PWMC Offset: 0xc) PWMC Status Register -------- -// - -------- PWMC_IER : (PWMC Offset: 0x10) PWMC Interrupt Enable Register -------- -// - -------- PWMC_IDR : (PWMC Offset: 0x14) PWMC Interrupt Disable Register -------- -// - -------- PWMC_IMR : (PWMC Offset: 0x18) PWMC Interrupt Mask Register -------- -// - -------- PWMC_ISR : (PWMC Offset: 0x1c) PWMC Interrupt Status Register -------- +for Read, 4 -// - ***************************************************************************** -// - SOFTWARE API DEFINITION FOR USB Device Interface -// - ***************************************************************************** -// - -------- UDP_FRM_NUM : (UDP Offset: 0x0) USB Frame Number Register -------- -AT91C_UDP_FRM_NUM EQU (0x7FF << 0) ;- (UDP) Frame Number as Defined in the Packet Field Formats -AT91C_UDP_FRM_ERR EQU (0x1 << 16) ;- (UDP) Frame Error -AT91C_UDP_FRM_OK EQU (0x1 << 17) ;- (UDP) Frame OK -// - -------- UDP_GLB_STATE : (UDP Offset: 0x4) USB Global State Register -------- -AT91C_UDP_FADDEN EQU (0x1 << 0) ;- (UDP) Function Address Enable -AT91C_UDP_CONFG EQU (0x1 << 1) ;- (UDP) Configured -AT91C_UDP_ESR EQU (0x1 << 2) ;- (UDP) Enable Send Resume -AT91C_UDP_RSMINPR EQU (0x1 << 3) ;- (UDP) A Resume Has Been Sent to the Host -AT91C_UDP_RMWUPE EQU (0x1 << 4) ;- (UDP) Remote Wake Up Enable -// - -------- UDP_FADDR : (UDP Offset: 0x8) USB Function Address Register -------- -AT91C_UDP_FADD EQU (0xFF << 0) ;- (UDP) Function Address Value -AT91C_UDP_FEN EQU (0x1 << 8) ;- (UDP) Function Enable -// - -------- UDP_IER : (UDP Offset: 0x10) USB Interrupt Enable Register -------- -AT91C_UDP_EPINT0 EQU (0x1 << 0) ;- (UDP) Endpoint 0 Interrupt -AT91C_UDP_EPINT1 EQU (0x1 << 1) ;- (UDP) Endpoint 0 Interrupt -AT91C_UDP_EPINT2 EQU (0x1 << 2) ;- (UDP) Endpoint 2 Interrupt -AT91C_UDP_EPINT3 EQU (0x1 << 3) ;- (UDP) Endpoint 3 Interrupt -AT91C_UDP_EPINT4 EQU (0x1 << 4) ;- (UDP) Endpoint 4 Interrupt -AT91C_UDP_EPINT5 EQU (0x1 << 5) ;- (UDP) Endpoint 5 Interrupt -AT91C_UDP_RXSUSP EQU (0x1 << 8) ;- (UDP) USB Suspend Interrupt -AT91C_UDP_RXRSM EQU (0x1 << 9) ;- (UDP) USB Resume Interrupt -AT91C_UDP_EXTRSM EQU (0x1 << 10) ;- (UDP) USB External Resume Interrupt -AT91C_UDP_SOFINT EQU (0x1 << 11) ;- (UDP) USB Start Of frame Interrupt -AT91C_UDP_WAKEUP EQU (0x1 << 13) ;- (UDP) USB Resume Interrupt -// - -------- UDP_IDR : (UDP Offset: 0x14) USB Interrupt Disable Register -------- -// - -------- UDP_IMR : (UDP Offset: 0x18) USB Interrupt Mask Register -------- -// - -------- UDP_ISR : (UDP Offset: 0x1c) USB Interrupt Status Register -------- -AT91C_UDP_ENDBUSRES EQU (0x1 << 12) ;- (UDP) USB End Of Bus Reset Interrupt -// - -------- UDP_ICR : (UDP Offset: 0x20) USB Interrupt Clear Register -------- -// - -------- UDP_RST_EP : (UDP Offset: 0x28) USB Reset Endpoint Register -------- -AT91C_UDP_EP0 EQU (0x1 << 0) ;- (UDP) Reset Endpoint 0 -AT91C_UDP_EP1 EQU (0x1 << 1) ;- (UDP) Reset Endpoint 1 -AT91C_UDP_EP2 EQU (0x1 << 2) ;- (UDP) Reset Endpoint 2 -AT91C_UDP_EP3 EQU (0x1 << 3) ;- (UDP) Reset Endpoint 3 -AT91C_UDP_EP4 EQU (0x1 << 4) ;- (UDP) Reset Endpoint 4 -AT91C_UDP_EP5 EQU (0x1 << 5) ;- (UDP) Reset Endpoint 5 -// - -------- UDP_CSR : (UDP Offset: 0x30) USB Endpoint Control and Status Register -------- -AT91C_UDP_TXCOMP EQU (0x1 << 0) ;- (UDP) Generates an IN packet with data previously written in the DPR -AT91C_UDP_RX_DATA_BK0 EQU (0x1 << 1) ;- (UDP) Receive Data Bank 0 -AT91C_UDP_RXSETUP EQU (0x1 << 2) ;- (UDP) Sends STALL to the Host (Control endpoints) -AT91C_UDP_ISOERROR EQU (0x1 << 3) ;- (UDP) Isochronous error (Isochronous endpoints) -AT91C_UDP_TXPKTRDY EQU (0x1 << 4) ;- (UDP) Transmit Packet Ready -AT91C_UDP_FORCESTALL EQU (0x1 << 5) ;- (UDP) Force Stall (used by Control, Bulk and Isochronous endpoints). -AT91C_UDP_RX_DATA_BK1 EQU (0x1 << 6) ;- (UDP) Receive Data Bank 1 (only used by endpoints with ping-pong attributes). -AT91C_UDP_DIR EQU (0x1 << 7) ;- (UDP) Transfer Direction -AT91C_UDP_EPTYPE EQU (0x7 << 8) ;- (UDP) Endpoint type -AT91C_UDP_EPTYPE_CTRL EQU (0x0 << 8) ;- (UDP) Control -AT91C_UDP_EPTYPE_ISO_OUT EQU (0x1 << 8) ;- (UDP) Isochronous OUT -AT91C_UDP_EPTYPE_BULK_OUT EQU (0x2 << 8) ;- (UDP) Bulk OUT -AT91C_UDP_EPTYPE_INT_OUT EQU (0x3 << 8) ;- (UDP) Interrupt OUT -AT91C_UDP_EPTYPE_ISO_IN EQU (0x5 << 8) ;- (UDP) Isochronous IN -AT91C_UDP_EPTYPE_BULK_IN EQU (0x6 << 8) ;- (UDP) Bulk IN -AT91C_UDP_EPTYPE_INT_IN EQU (0x7 << 8) ;- (UDP) Interrupt IN -AT91C_UDP_DTGLE EQU (0x1 << 11) ;- (UDP) Data Toggle -AT91C_UDP_EPEDS EQU (0x1 << 15) ;- (UDP) Endpoint Enable Disable -AT91C_UDP_RXBYTECNT EQU (0x7FF << 16) ;- (UDP) Number Of Bytes Available in the FIFO -// - -------- UDP_TXVC : (UDP Offset: 0x74) Transceiver Control Register -------- -AT91C_UDP_TXVDIS EQU (0x1 << 8) ;- (UDP) -AT91C_UDP_PUON EQU (0x1 << 9) ;- (UDP) Pull-up ON +for Write operations +AT91C_MC_FWS_3FWS EQU( 0x3 << 8 ); +-( MC ) 4 cycles -// - ***************************************************************************** -// - SOFTWARE API DEFINITION FOR Timer Counter Channel Interface -// - ***************************************************************************** -// - -------- TC_CCR : (TC Offset: 0x0) TC Channel Control Register -------- -AT91C_TC_CLKEN EQU (0x1 << 0) ;- (TC) Counter Clock Enable Command -AT91C_TC_CLKDIS EQU (0x1 << 1) ;- (TC) Counter Clock Disable Command -AT91C_TC_SWTRG EQU (0x1 << 2) ;- (TC) Software Trigger Command -// - -------- TC_CMR : (TC Offset: 0x4) TC Channel Mode Register: Capture Mode / Waveform Mode -------- -AT91C_TC_CLKS EQU (0x7 << 0) ;- (TC) Clock Selection -AT91C_TC_CLKS_TIMER_DIV1_CLOCK EQU (0x0) ;- (TC) Clock selected: TIMER_DIV1_CLOCK -AT91C_TC_CLKS_TIMER_DIV2_CLOCK EQU (0x1) ;- (TC) Clock selected: TIMER_DIV2_CLOCK -AT91C_TC_CLKS_TIMER_DIV3_CLOCK EQU (0x2) ;- (TC) Clock selected: TIMER_DIV3_CLOCK -AT91C_TC_CLKS_TIMER_DIV4_CLOCK EQU (0x3) ;- (TC) Clock selected: TIMER_DIV4_CLOCK -AT91C_TC_CLKS_TIMER_DIV5_CLOCK EQU (0x4) ;- (TC) Clock selected: TIMER_DIV5_CLOCK -AT91C_TC_CLKS_XC0 EQU (0x5) ;- (TC) Clock selected: XC0 -AT91C_TC_CLKS_XC1 EQU (0x6) ;- (TC) Clock selected: XC1 -AT91C_TC_CLKS_XC2 EQU (0x7) ;- (TC) Clock selected: XC2 -AT91C_TC_CLKI EQU (0x1 << 3) ;- (TC) Clock Invert -AT91C_TC_BURST EQU (0x3 << 4) ;- (TC) Burst Signal Selection -AT91C_TC_BURST_NONE EQU (0x0 << 4) ;- (TC) The clock is not gated by an external signal -AT91C_TC_BURST_XC0 EQU (0x1 << 4) ;- (TC) XC0 is ANDed with the selected clock -AT91C_TC_BURST_XC1 EQU (0x2 << 4) ;- (TC) XC1 is ANDed with the selected clock -AT91C_TC_BURST_XC2 EQU (0x3 << 4) ;- (TC) XC2 is ANDed with the selected clock -AT91C_TC_CPCSTOP EQU (0x1 << 6) ;- (TC) Counter Clock Stopped with RC Compare -AT91C_TC_LDBSTOP EQU (0x1 << 6) ;- (TC) Counter Clock Stopped with RB Loading -AT91C_TC_CPCDIS EQU (0x1 << 7) ;- (TC) Counter Clock Disable with RC Compare -AT91C_TC_LDBDIS EQU (0x1 << 7) ;- (TC) Counter Clock Disabled with RB Loading -AT91C_TC_ETRGEDG EQU (0x3 << 8) ;- (TC) External Trigger Edge Selection -AT91C_TC_ETRGEDG_NONE EQU (0x0 << 8) ;- (TC) Edge: None -AT91C_TC_ETRGEDG_RISING EQU (0x1 << 8) ;- (TC) Edge: rising edge -AT91C_TC_ETRGEDG_FALLING EQU (0x2 << 8) ;- (TC) Edge: falling edge -AT91C_TC_ETRGEDG_BOTH EQU (0x3 << 8) ;- (TC) Edge: each edge -AT91C_TC_EEVTEDG EQU (0x3 << 8) ;- (TC) External Event Edge Selection -AT91C_TC_EEVTEDG_NONE EQU (0x0 << 8) ;- (TC) Edge: None -AT91C_TC_EEVTEDG_RISING EQU (0x1 << 8) ;- (TC) Edge: rising edge -AT91C_TC_EEVTEDG_FALLING EQU (0x2 << 8) ;- (TC) Edge: falling edge -AT91C_TC_EEVTEDG_BOTH EQU (0x3 << 8) ;- (TC) Edge: each edge -AT91C_TC_EEVT EQU (0x3 << 10) ;- (TC) External Event Selection -AT91C_TC_EEVT_TIOB EQU (0x0 << 10) ;- (TC) Signal selected as external event: TIOB TIOB direction: input -AT91C_TC_EEVT_XC0 EQU (0x1 << 10) ;- (TC) Signal selected as external event: XC0 TIOB direction: output -AT91C_TC_EEVT_XC1 EQU (0x2 << 10) ;- (TC) Signal selected as external event: XC1 TIOB direction: output -AT91C_TC_EEVT_XC2 EQU (0x3 << 10) ;- (TC) Signal selected as external event: XC2 TIOB direction: output -AT91C_TC_ABETRG EQU (0x1 << 10) ;- (TC) TIOA or TIOB External Trigger Selection -AT91C_TC_ENETRG EQU (0x1 << 12) ;- (TC) External Event Trigger enable -AT91C_TC_WAVESEL EQU (0x3 << 13) ;- (TC) Waveform Selection -AT91C_TC_WAVESEL_UP EQU (0x0 << 13) ;- (TC) UP mode without atomatic trigger on RC Compare -AT91C_TC_WAVESEL_UPDOWN EQU (0x1 << 13) ;- (TC) UPDOWN mode without automatic trigger on RC Compare -AT91C_TC_WAVESEL_UP_AUTO EQU (0x2 << 13) ;- (TC) UP mode with automatic trigger on RC Compare -AT91C_TC_WAVESEL_UPDOWN_AUTO EQU (0x3 << 13) ;- (TC) UPDOWN mode with automatic trigger on RC Compare -AT91C_TC_CPCTRG EQU (0x1 << 14) ;- (TC) RC Compare Trigger Enable -AT91C_TC_WAVE EQU (0x1 << 15) ;- (TC) -AT91C_TC_ACPA EQU (0x3 << 16) ;- (TC) RA Compare Effect on TIOA -AT91C_TC_ACPA_NONE EQU (0x0 << 16) ;- (TC) Effect: none -AT91C_TC_ACPA_SET EQU (0x1 << 16) ;- (TC) Effect: set -AT91C_TC_ACPA_CLEAR EQU (0x2 << 16) ;- (TC) Effect: clear -AT91C_TC_ACPA_TOGGLE EQU (0x3 << 16) ;- (TC) Effect: toggle -AT91C_TC_LDRA EQU (0x3 << 16) ;- (TC) RA Loading Selection -AT91C_TC_LDRA_NONE EQU (0x0 << 16) ;- (TC) Edge: None -AT91C_TC_LDRA_RISING EQU (0x1 << 16) ;- (TC) Edge: rising edge of TIOA -AT91C_TC_LDRA_FALLING EQU (0x2 << 16) ;- (TC) Edge: falling edge of TIOA -AT91C_TC_LDRA_BOTH EQU (0x3 << 16) ;- (TC) Edge: each edge of TIOA -AT91C_TC_ACPC EQU (0x3 << 18) ;- (TC) RC Compare Effect on TIOA -AT91C_TC_ACPC_NONE EQU (0x0 << 18) ;- (TC) Effect: none -AT91C_TC_ACPC_SET EQU (0x1 << 18) ;- (TC) Effect: set -AT91C_TC_ACPC_CLEAR EQU (0x2 << 18) ;- (TC) Effect: clear -AT91C_TC_ACPC_TOGGLE EQU (0x3 << 18) ;- (TC) Effect: toggle -AT91C_TC_LDRB EQU (0x3 << 18) ;- (TC) RB Loading Selection -AT91C_TC_LDRB_NONE EQU (0x0 << 18) ;- (TC) Edge: None -AT91C_TC_LDRB_RISING EQU (0x1 << 18) ;- (TC) Edge: rising edge of TIOA -AT91C_TC_LDRB_FALLING EQU (0x2 << 18) ;- (TC) Edge: falling edge of TIOA -AT91C_TC_LDRB_BOTH EQU (0x3 << 18) ;- (TC) Edge: each edge of TIOA -AT91C_TC_AEEVT EQU (0x3 << 20) ;- (TC) External Event Effect on TIOA -AT91C_TC_AEEVT_NONE EQU (0x0 << 20) ;- (TC) Effect: none -AT91C_TC_AEEVT_SET EQU (0x1 << 20) ;- (TC) Effect: set -AT91C_TC_AEEVT_CLEAR EQU (0x2 << 20) ;- (TC) Effect: clear -AT91C_TC_AEEVT_TOGGLE EQU (0x3 << 20) ;- (TC) Effect: toggle -AT91C_TC_ASWTRG EQU (0x3 << 22) ;- (TC) Software Trigger Effect on TIOA -AT91C_TC_ASWTRG_NONE EQU (0x0 << 22) ;- (TC) Effect: none -AT91C_TC_ASWTRG_SET EQU (0x1 << 22) ;- (TC) Effect: set -AT91C_TC_ASWTRG_CLEAR EQU (0x2 << 22) ;- (TC) Effect: clear -AT91C_TC_ASWTRG_TOGGLE EQU (0x3 << 22) ;- (TC) Effect: toggle -AT91C_TC_BCPB EQU (0x3 << 24) ;- (TC) RB Compare Effect on TIOB -AT91C_TC_BCPB_NONE EQU (0x0 << 24) ;- (TC) Effect: none -AT91C_TC_BCPB_SET EQU (0x1 << 24) ;- (TC) Effect: set -AT91C_TC_BCPB_CLEAR EQU (0x2 << 24) ;- (TC) Effect: clear -AT91C_TC_BCPB_TOGGLE EQU (0x3 << 24) ;- (TC) Effect: toggle -AT91C_TC_BCPC EQU (0x3 << 26) ;- (TC) RC Compare Effect on TIOB -AT91C_TC_BCPC_NONE EQU (0x0 << 26) ;- (TC) Effect: none -AT91C_TC_BCPC_SET EQU (0x1 << 26) ;- (TC) Effect: set -AT91C_TC_BCPC_CLEAR EQU (0x2 << 26) ;- (TC) Effect: clear -AT91C_TC_BCPC_TOGGLE EQU (0x3 << 26) ;- (TC) Effect: toggle -AT91C_TC_BEEVT EQU (0x3 << 28) ;- (TC) External Event Effect on TIOB -AT91C_TC_BEEVT_NONE EQU (0x0 << 28) ;- (TC) Effect: none -AT91C_TC_BEEVT_SET EQU (0x1 << 28) ;- (TC) Effect: set -AT91C_TC_BEEVT_CLEAR EQU (0x2 << 28) ;- (TC) Effect: clear -AT91C_TC_BEEVT_TOGGLE EQU (0x3 << 28) ;- (TC) Effect: toggle -AT91C_TC_BSWTRG EQU (0x3 << 30) ;- (TC) Software Trigger Effect on TIOB -AT91C_TC_BSWTRG_NONE EQU (0x0 << 30) ;- (TC) Effect: none -AT91C_TC_BSWTRG_SET EQU (0x1 << 30) ;- (TC) Effect: set -AT91C_TC_BSWTRG_CLEAR EQU (0x2 << 30) ;- (TC) Effect: clear -AT91C_TC_BSWTRG_TOGGLE EQU (0x3 << 30) ;- (TC) Effect: toggle -// - -------- TC_SR : (TC Offset: 0x20) TC Channel Status Register -------- -AT91C_TC_COVFS EQU (0x1 << 0) ;- (TC) Counter Overflow -AT91C_TC_LOVRS EQU (0x1 << 1) ;- (TC) Load Overrun -AT91C_TC_CPAS EQU (0x1 << 2) ;- (TC) RA Compare -AT91C_TC_CPBS EQU (0x1 << 3) ;- (TC) RB Compare -AT91C_TC_CPCS EQU (0x1 << 4) ;- (TC) RC Compare -AT91C_TC_LDRAS EQU (0x1 << 5) ;- (TC) RA Loading -AT91C_TC_LDRBS EQU (0x1 << 6) ;- (TC) RB Loading -AT91C_TC_ETRGS EQU (0x1 << 7) ;- (TC) External Trigger -AT91C_TC_CLKSTA EQU (0x1 << 16) ;- (TC) Clock Enabling -AT91C_TC_MTIOA EQU (0x1 << 17) ;- (TC) TIOA Mirror -AT91C_TC_MTIOB EQU (0x1 << 18) ;- (TC) TIOA Mirror -// - -------- TC_IER : (TC Offset: 0x24) TC Channel Interrupt Enable Register -------- -// - -------- TC_IDR : (TC Offset: 0x28) TC Channel Interrupt Disable Register -------- -// - -------- TC_IMR : (TC Offset: 0x2c) TC Channel Interrupt Mask Register -------- +for Read, 4 -// - ***************************************************************************** -// - SOFTWARE API DEFINITION FOR Timer Counter Interface -// - ***************************************************************************** -// - -------- TCB_BCR : (TCB Offset: 0xc0) TC Block Control Register -------- -AT91C_TCB_SYNC EQU (0x1 << 0) ;- (TCB) Synchro Command -// - -------- TCB_BMR : (TCB Offset: 0xc4) TC Block Mode Register -------- -AT91C_TCB_TC0XC0S EQU (0x3 << 0) ;- (TCB) External Clock Signal 0 Selection -AT91C_TCB_TC0XC0S_TCLK0 EQU (0x0) ;- (TCB) TCLK0 connected to XC0 -AT91C_TCB_TC0XC0S_NONE EQU (0x1) ;- (TCB) None signal connected to XC0 -AT91C_TCB_TC0XC0S_TIOA1 EQU (0x2) ;- (TCB) TIOA1 connected to XC0 -AT91C_TCB_TC0XC0S_TIOA2 EQU (0x3) ;- (TCB) TIOA2 connected to XC0 -AT91C_TCB_TC1XC1S EQU (0x3 << 2) ;- (TCB) External Clock Signal 1 Selection -AT91C_TCB_TC1XC1S_TCLK1 EQU (0x0 << 2) ;- (TCB) TCLK1 connected to XC1 -AT91C_TCB_TC1XC1S_NONE EQU (0x1 << 2) ;- (TCB) None signal connected to XC1 -AT91C_TCB_TC1XC1S_TIOA0 EQU (0x2 << 2) ;- (TCB) TIOA0 connected to XC1 -AT91C_TCB_TC1XC1S_TIOA2 EQU (0x3 << 2) ;- (TCB) TIOA2 connected to XC1 -AT91C_TCB_TC2XC2S EQU (0x3 << 4) ;- (TCB) External Clock Signal 2 Selection -AT91C_TCB_TC2XC2S_TCLK2 EQU (0x0 << 4) ;- (TCB) TCLK2 connected to XC2 -AT91C_TCB_TC2XC2S_NONE EQU (0x1 << 4) ;- (TCB) None signal connected to XC2 -AT91C_TCB_TC2XC2S_TIOA0 EQU (0x2 << 4) ;- (TCB) TIOA0 connected to XC2 -AT91C_TCB_TC2XC2S_TIOA1 EQU (0x3 << 4) ;- (TCB) TIOA2 connected to XC2 +for Write operations +AT91C_MC_FMCN EQU( 0xFF << 16 ); +-( MC ) Flash Microsecond Cycle Number +/* - -------- MC_FCR : (MC Offset: 0x64) MC Flash Command Register -------- */ +AT91C_MC_FCMD EQU( 0xF << 0 ); +-( MC ) Flash Command +AT91C_MC_FCMD_START_PROG EQU( 0x1 ); +-( MC ) Starts the programming of th epage specified by PAGEN. + AT91C_MC_FCMD_LOCK EQU( 0x2 ); +-( MC ) Starts a lock sequence of the sector defined by the bits 4 to 7 of the field PAGEN. + AT91C_MC_FCMD_PROG_AND_LOCK EQU( 0x3 ); +-( MC ) The lock sequence automatically happens after the programming sequence is completed. + AT91C_MC_FCMD_UNLOCK EQU( 0x4 ); +-( MC ) Starts an unlock sequence of the sector defined by the bits 4 to 7 of the field PAGEN. + AT91C_MC_FCMD_ERASE_ALL EQU( 0x8 ); +-( MC ) Starts the erase of the entire flash.If at least a page is locked, the command is cancelled. + AT91C_MC_FCMD_SET_GP_NVM EQU( 0xB ); +-( MC ) Set General Purpose NVM bits. + AT91C_MC_FCMD_CLR_GP_NVM EQU( 0xD ); +-( MC ) Clear General Purpose NVM bits. + AT91C_MC_FCMD_SET_SECURITY EQU( 0xF ); +-( MC ) Set Security Bit. + AT91C_MC_PAGEN EQU( 0x3FF << 8 ); +-( MC ) Page Number +AT91C_MC_KEY EQU( 0xFF << 24 ); +-( MC ) Writing Protect Key +/* - -------- MC_FSR : (MC Offset: 0x68) MC Flash Command Register -------- */ +AT91C_MC_SECURITY EQU( 0x1 << 4 ); +-( MC ) Security Bit Status +AT91C_MC_GPNVM0 EQU( 0x1 << 8 ); +-( MC ) Sector 0 Lock Status +AT91C_MC_GPNVM1 EQU( 0x1 << 9 ); +-( MC ) Sector 1 Lock Status +AT91C_MC_GPNVM2 EQU( 0x1 << 10 ); +-( MC ) Sector 2 Lock Status +AT91C_MC_GPNVM3 EQU( 0x1 << 11 ); +-( MC ) Sector 3 Lock Status +AT91C_MC_GPNVM4 EQU( 0x1 << 12 ); +-( MC ) Sector 4 Lock Status +AT91C_MC_GPNVM5 EQU( 0x1 << 13 ); +-( MC ) Sector 5 Lock Status +AT91C_MC_GPNVM6 EQU( 0x1 << 14 ); +-( MC ) Sector 6 Lock Status +AT91C_MC_GPNVM7 EQU( 0x1 << 15 ); +-( MC ) Sector 7 Lock Status +AT91C_MC_LOCKS0 EQU( 0x1 << 16 ); +-( MC ) Sector 0 Lock Status +AT91C_MC_LOCKS1 EQU( 0x1 << 17 ); +-( MC ) Sector 1 Lock Status +AT91C_MC_LOCKS2 EQU( 0x1 << 18 ); +-( MC ) Sector 2 Lock Status +AT91C_MC_LOCKS3 EQU( 0x1 << 19 ); +-( MC ) Sector 3 Lock Status +AT91C_MC_LOCKS4 EQU( 0x1 << 20 ); +-( MC ) Sector 4 Lock Status +AT91C_MC_LOCKS5 EQU( 0x1 << 21 ); +-( MC ) Sector 5 Lock Status +AT91C_MC_LOCKS6 EQU( 0x1 << 22 ); +-( MC ) Sector 6 Lock Status +AT91C_MC_LOCKS7 EQU( 0x1 << 23 ); +-( MC ) Sector 7 Lock Status +AT91C_MC_LOCKS8 EQU( 0x1 << 24 ); +-( MC ) Sector 8 Lock Status +AT91C_MC_LOCKS9 EQU( 0x1 << 25 ); +-( MC ) Sector 9 Lock Status +AT91C_MC_LOCKS10 EQU( 0x1 << 26 ); +-( MC ) Sector 10 Lock Status +AT91C_MC_LOCKS11 EQU( 0x1 << 27 ); +-( MC ) Sector 11 Lock Status +AT91C_MC_LOCKS12 EQU( 0x1 << 28 ); +-( MC ) Sector 12 Lock Status +AT91C_MC_LOCKS13 EQU( 0x1 << 29 ); +-( MC ) Sector 13 Lock Status +AT91C_MC_LOCKS14 EQU( 0x1 << 30 ); +-( MC ) Sector 14 Lock Status +AT91C_MC_LOCKS15 EQU( 0x1 << 31 ); +-( MC ) Sector 15 Lock Status -// - ***************************************************************************** -// - SOFTWARE API DEFINITION FOR Control Area Network MailBox Interface -// - ***************************************************************************** -// - -------- CAN_MMR : (CAN_MB Offset: 0x0) CAN Message Mode Register -------- -AT91C_CAN_MTIMEMARK EQU (0xFFFF << 0) ;- (CAN_MB) Mailbox Timemark -AT91C_CAN_PRIOR EQU (0xF << 16) ;- (CAN_MB) Mailbox Priority -AT91C_CAN_MOT EQU (0x7 << 24) ;- (CAN_MB) Mailbox Object Type -AT91C_CAN_MOT_DIS EQU (0x0 << 24) ;- (CAN_MB) -AT91C_CAN_MOT_RX EQU (0x1 << 24) ;- (CAN_MB) -AT91C_CAN_MOT_RXOVERWRITE EQU (0x2 << 24) ;- (CAN_MB) -AT91C_CAN_MOT_TX EQU (0x3 << 24) ;- (CAN_MB) -AT91C_CAN_MOT_CONSUMER EQU (0x4 << 24) ;- (CAN_MB) -AT91C_CAN_MOT_PRODUCER EQU (0x5 << 24) ;- (CAN_MB) -// - -------- CAN_MAM : (CAN_MB Offset: 0x4) CAN Message Acceptance Mask Register -------- -AT91C_CAN_MIDvB EQU (0x3FFFF << 0) ;- (CAN_MB) Complementary bits for identifier in extended mode -AT91C_CAN_MIDvA EQU (0x7FF << 18) ;- (CAN_MB) Identifier for standard frame mode -AT91C_CAN_MIDE EQU (0x1 << 29) ;- (CAN_MB) Identifier Version -// - -------- CAN_MID : (CAN_MB Offset: 0x8) CAN Message ID Register -------- -// - -------- CAN_MFID : (CAN_MB Offset: 0xc) CAN Message Family ID Register -------- -// - -------- CAN_MSR : (CAN_MB Offset: 0x10) CAN Message Status Register -------- -AT91C_CAN_MTIMESTAMP EQU (0xFFFF << 0) ;- (CAN_MB) Timer Value -AT91C_CAN_MDLC EQU (0xF << 16) ;- (CAN_MB) Mailbox Data Length Code -AT91C_CAN_MRTR EQU (0x1 << 20) ;- (CAN_MB) Mailbox Remote Transmission Request -AT91C_CAN_MABT EQU (0x1 << 22) ;- (CAN_MB) Mailbox Message Abort -AT91C_CAN_MRDY EQU (0x1 << 23) ;- (CAN_MB) Mailbox Ready -AT91C_CAN_MMI EQU (0x1 << 24) ;- (CAN_MB) Mailbox Message Ignored -// - -------- CAN_MDL : (CAN_MB Offset: 0x14) CAN Message Data Low Register -------- -// - -------- CAN_MDH : (CAN_MB Offset: 0x18) CAN Message Data High Register -------- -// - -------- CAN_MCR : (CAN_MB Offset: 0x1c) CAN Message Control Register -------- -AT91C_CAN_MACR EQU (0x1 << 22) ;- (CAN_MB) Abort Request for Mailbox -AT91C_CAN_MTCR EQU (0x1 << 23) ;- (CAN_MB) Mailbox Transfer Command +/* - ***************************************************************************** */ +/* - SOFTWARE API DEFINITION FOR Serial Parallel Interface */ +/* - ***************************************************************************** */ +/* - -------- SPI_CR : (SPI Offset: 0x0) SPI Control Register -------- */ +AT91C_SPI_SPIEN EQU( 0x1 << 0 ); +-( SPI ) SPI Enable +AT91C_SPI_SPIDIS EQU( 0x1 << 1 ); +-( SPI ) SPI Disable +AT91C_SPI_SWRST EQU( 0x1 << 7 ); +-( SPI ) SPI Software reset +AT91C_SPI_LASTXFER EQU( 0x1 << 24 ); +-( SPI ) SPI Last Transfer +/* - -------- SPI_MR : (SPI Offset: 0x4) SPI Mode Register -------- */ +AT91C_SPI_MSTR EQU( 0x1 << 0 ); +-( SPI ) Master / Slave Mode +AT91C_SPI_PS EQU( 0x1 << 1 ); +-( SPI ) Peripheral Select +AT91C_SPI_PS_FIXED EQU( 0x0 << 1 ); +-( SPI ) Fixed Peripheral Select +AT91C_SPI_PS_VARIABLE EQU( 0x1 << 1 ); +-( SPI ) Variable Peripheral Select +AT91C_SPI_PCSDEC EQU( 0x1 << 2 ); +-( SPI ) Chip Select Decode +AT91C_SPI_FDIV EQU( 0x1 << 3 ); +-( SPI ) Clock Selection +AT91C_SPI_MODFDIS EQU( 0x1 << 4 ); +-( SPI ) Mode Fault Detection +AT91C_SPI_LLB EQU( 0x1 << 7 ); +-( SPI ) Clock Selection +AT91C_SPI_PCS EQU( 0xF << 16 ); +-( SPI ) Peripheral Chip Select +AT91C_SPI_DLYBCS EQU( 0xFF << 24 ); +-( SPI ) Delay Between Chip Selects +/* - -------- SPI_RDR : (SPI Offset: 0x8) Receive Data Register -------- */ +AT91C_SPI_RD EQU( 0xFFFF << 0 ); +-( SPI ) Receive Data +AT91C_SPI_RPCS EQU( 0xF << 16 ); +-( SPI ) Peripheral Chip Select Status +/* - -------- SPI_TDR : (SPI Offset: 0xc) Transmit Data Register -------- */ +AT91C_SPI_TD EQU( 0xFFFF << 0 ); +-( SPI ) Transmit Data +AT91C_SPI_TPCS EQU( 0xF << 16 ); +-( SPI ) Peripheral Chip Select Status +/* - -------- SPI_SR : (SPI Offset: 0x10) Status Register -------- */ +AT91C_SPI_RDRF EQU( 0x1 << 0 ); +-( SPI ) Receive Data Register Full +AT91C_SPI_TDRE EQU( 0x1 << 1 ); +-( SPI ) Transmit Data Register Empty +AT91C_SPI_MODF EQU( 0x1 << 2 ); +-( SPI ) Mode Fault Error +AT91C_SPI_OVRES EQU( 0x1 << 3 ); +-( SPI ) Overrun Error Status +AT91C_SPI_ENDRX EQU( 0x1 << 4 ); +-( SPI ) End of Receiver Transfer +AT91C_SPI_ENDTX EQU( 0x1 << 5 ); +-( SPI ) End of Receiver Transfer +AT91C_SPI_RXBUFF EQU( 0x1 << 6 ); +-( SPI ) RXBUFF Interrupt +AT91C_SPI_TXBUFE EQU( 0x1 << 7 ); +-( SPI ) TXBUFE Interrupt +AT91C_SPI_NSSR EQU( 0x1 << 8 ); +-( SPI ) NSSR Interrupt +AT91C_SPI_TXEMPTY EQU( 0x1 << 9 ); +-( SPI ) TXEMPTY Interrupt +AT91C_SPI_SPIENS EQU( 0x1 << 16 ); +-( SPI ) Enable Status +/* - -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register -------- */ +/* - -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register -------- */ +/* - -------- SPI_IMR : (SPI Offset: 0x1c) Interrupt Mask Register -------- */ +/* - -------- SPI_CSR : (SPI Offset: 0x30) Chip Select Register -------- */ +AT91C_SPI_CPOL EQU( 0x1 << 0 ); +-( SPI ) Clock Polarity +AT91C_SPI_NCPHA EQU( 0x1 << 1 ); +-( SPI ) Clock Phase +AT91C_SPI_CSAAT EQU( 0x1 << 3 ); +-( SPI ) Chip Select Active After Transfer +AT91C_SPI_BITS EQU( 0xF << 4 ); +-( SPI ) Bits Per Transfer +AT91C_SPI_BITS_8 EQU( 0x0 << 4 ); +-( SPI ) 8 Bits Per transfer +AT91C_SPI_BITS_9 EQU( 0x1 << 4 ); +-( SPI ) 9 Bits Per transfer +AT91C_SPI_BITS_10 EQU( 0x2 << 4 ); +-( SPI ) 10 Bits Per transfer +AT91C_SPI_BITS_11 EQU( 0x3 << 4 ); +-( SPI ) 11 Bits Per transfer +AT91C_SPI_BITS_12 EQU( 0x4 << 4 ); +-( SPI ) 12 Bits Per transfer +AT91C_SPI_BITS_13 EQU( 0x5 << 4 ); +-( SPI ) 13 Bits Per transfer +AT91C_SPI_BITS_14 EQU( 0x6 << 4 ); +-( SPI ) 14 Bits Per transfer +AT91C_SPI_BITS_15 EQU( 0x7 << 4 ); +-( SPI ) 15 Bits Per transfer +AT91C_SPI_BITS_16 EQU( 0x8 << 4 ); +-( SPI ) 16 Bits Per transfer +AT91C_SPI_SCBR EQU( 0xFF << 8 ); +-( SPI ) Serial Clock Baud Rate +AT91C_SPI_DLYBS EQU( 0xFF << 16 ); +-( SPI ) Delay Before SPCK +AT91C_SPI_DLYBCT EQU( 0xFF << 24 ); +-( SPI ) Delay Between Consecutive Transfers -// - ***************************************************************************** -// - SOFTWARE API DEFINITION FOR Control Area Network Interface -// - ***************************************************************************** -// - -------- CAN_MR : (CAN Offset: 0x0) CAN Mode Register -------- -AT91C_CAN_CANEN EQU (0x1 << 0) ;- (CAN) CAN Controller Enable -AT91C_CAN_LPM EQU (0x1 << 1) ;- (CAN) Disable/Enable Low Power Mode -AT91C_CAN_ABM EQU (0x1 << 2) ;- (CAN) Disable/Enable Autobaud/Listen Mode -AT91C_CAN_OVL EQU (0x1 << 3) ;- (CAN) Disable/Enable Overload Frame -AT91C_CAN_TEOF EQU (0x1 << 4) ;- (CAN) Time Stamp messages at each end of Frame -AT91C_CAN_TTM EQU (0x1 << 5) ;- (CAN) Disable/Enable Time Trigger Mode -AT91C_CAN_TIMFRZ EQU (0x1 << 6) ;- (CAN) Enable Timer Freeze -AT91C_CAN_DRPT EQU (0x1 << 7) ;- (CAN) Disable Repeat -// - -------- CAN_IER : (CAN Offset: 0x4) CAN Interrupt Enable Register -------- -AT91C_CAN_MB0 EQU (0x1 << 0) ;- (CAN) Mailbox 0 Flag -AT91C_CAN_MB1 EQU (0x1 << 1) ;- (CAN) Mailbox 1 Flag -AT91C_CAN_MB2 EQU (0x1 << 2) ;- (CAN) Mailbox 2 Flag -AT91C_CAN_MB3 EQU (0x1 << 3) ;- (CAN) Mailbox 3 Flag -AT91C_CAN_MB4 EQU (0x1 << 4) ;- (CAN) Mailbox 4 Flag -AT91C_CAN_MB5 EQU (0x1 << 5) ;- (CAN) Mailbox 5 Flag -AT91C_CAN_MB6 EQU (0x1 << 6) ;- (CAN) Mailbox 6 Flag -AT91C_CAN_MB7 EQU (0x1 << 7) ;- (CAN) Mailbox 7 Flag -AT91C_CAN_MB8 EQU (0x1 << 8) ;- (CAN) Mailbox 8 Flag -AT91C_CAN_MB9 EQU (0x1 << 9) ;- (CAN) Mailbox 9 Flag -AT91C_CAN_MB10 EQU (0x1 << 10) ;- (CAN) Mailbox 10 Flag -AT91C_CAN_MB11 EQU (0x1 << 11) ;- (CAN) Mailbox 11 Flag -AT91C_CAN_MB12 EQU (0x1 << 12) ;- (CAN) Mailbox 12 Flag -AT91C_CAN_MB13 EQU (0x1 << 13) ;- (CAN) Mailbox 13 Flag -AT91C_CAN_MB14 EQU (0x1 << 14) ;- (CAN) Mailbox 14 Flag -AT91C_CAN_MB15 EQU (0x1 << 15) ;- (CAN) Mailbox 15 Flag -AT91C_CAN_ERRA EQU (0x1 << 16) ;- (CAN) Error Active Mode Flag -AT91C_CAN_WARN EQU (0x1 << 17) ;- (CAN) Warning Limit Flag -AT91C_CAN_ERRP EQU (0x1 << 18) ;- (CAN) Error Passive Mode Flag -AT91C_CAN_BOFF EQU (0x1 << 19) ;- (CAN) Bus Off Mode Flag -AT91C_CAN_SLEEP EQU (0x1 << 20) ;- (CAN) Sleep Flag -AT91C_CAN_WAKEUP EQU (0x1 << 21) ;- (CAN) Wakeup Flag -AT91C_CAN_TOVF EQU (0x1 << 22) ;- (CAN) Timer Overflow Flag -AT91C_CAN_TSTP EQU (0x1 << 23) ;- (CAN) Timestamp Flag -AT91C_CAN_CERR EQU (0x1 << 24) ;- (CAN) CRC Error -AT91C_CAN_SERR EQU (0x1 << 25) ;- (CAN) Stuffing Error -AT91C_CAN_AERR EQU (0x1 << 26) ;- (CAN) Acknowledgment Error -AT91C_CAN_FERR EQU (0x1 << 27) ;- (CAN) Form Error -AT91C_CAN_BERR EQU (0x1 << 28) ;- (CAN) Bit Error -// - -------- CAN_IDR : (CAN Offset: 0x8) CAN Interrupt Disable Register -------- -// - -------- CAN_IMR : (CAN Offset: 0xc) CAN Interrupt Mask Register -------- -// - -------- CAN_SR : (CAN Offset: 0x10) CAN Status Register -------- -AT91C_CAN_RBSY EQU (0x1 << 29) ;- (CAN) Receiver Busy -AT91C_CAN_TBSY EQU (0x1 << 30) ;- (CAN) Transmitter Busy -AT91C_CAN_OVLY EQU (0x1 << 31) ;- (CAN) Overload Busy -// - -------- CAN_BR : (CAN Offset: 0x14) CAN Baudrate Register -------- -AT91C_CAN_PHASE2 EQU (0x7 << 0) ;- (CAN) Phase 2 segment -AT91C_CAN_PHASE1 EQU (0x7 << 4) ;- (CAN) Phase 1 segment -AT91C_CAN_PROPAG EQU (0x7 << 8) ;- (CAN) Programmation time segment -AT91C_CAN_SYNC EQU (0x3 << 12) ;- (CAN) Re-synchronization jump width segment -AT91C_CAN_BRP EQU (0x7F << 16) ;- (CAN) Baudrate Prescaler -AT91C_CAN_SMP EQU (0x1 << 24) ;- (CAN) Sampling mode -// - -------- CAN_TIM : (CAN Offset: 0x18) CAN Timer Register -------- -AT91C_CAN_TIMER EQU (0xFFFF << 0) ;- (CAN) Timer field -// - -------- CAN_TIMESTP : (CAN Offset: 0x1c) CAN Timestamp Register -------- -// - -------- CAN_ECR : (CAN Offset: 0x20) CAN Error Counter Register -------- -AT91C_CAN_REC EQU (0xFF << 0) ;- (CAN) Receive Error Counter -AT91C_CAN_TEC EQU (0xFF << 16) ;- (CAN) Transmit Error Counter -// - -------- CAN_TCR : (CAN Offset: 0x24) CAN Transfer Command Register -------- -AT91C_CAN_TIMRST EQU (0x1 << 31) ;- (CAN) Timer Reset Field -// - -------- CAN_ACR : (CAN Offset: 0x28) CAN Abort Command Register -------- +/* - ***************************************************************************** */ +/* - SOFTWARE API DEFINITION FOR Usart */ +/* - ***************************************************************************** */ +/* - -------- US_CR : (USART Offset: 0x0) Debug Unit Control Register -------- */ +AT91C_US_STTBRK EQU( 0x1 << 9 ); +-( USART ) Start Break +AT91C_US_STPBRK EQU( 0x1 << 10 ); +-( USART ) Stop Break +AT91C_US_STTTO EQU( 0x1 << 11 ); +-( USART ) Start Time - out +AT91C_US_SENDA EQU( 0x1 << 12 ); +-( USART ) Send Address +AT91C_US_RSTIT EQU( 0x1 << 13 ); +-( USART ) Reset Iterations +AT91C_US_RSTNACK EQU( 0x1 << 14 ); +-( USART ) Reset Non Acknowledge +AT91C_US_RETTO EQU( 0x1 << 15 ); +-( USART ) Rearm Time - out +AT91C_US_DTREN EQU( 0x1 << 16 ); +-( USART ) Data Terminal ready Enable +AT91C_US_DTRDIS EQU( 0x1 << 17 ); +-( USART ) Data Terminal ready Disable +AT91C_US_RTSEN EQU( 0x1 << 18 ); +-( USART ) Request to Send enable +AT91C_US_RTSDIS EQU( 0x1 << 19 ); +-( USART ) Request to Send Disable +/* - -------- US_MR : (USART Offset: 0x4) Debug Unit Mode Register -------- */ +AT91C_US_USMODE EQU( 0xF << 0 ); +-( USART ) Usart mode +AT91C_US_USMODE_NORMAL EQU( 0x0 ); +-( USART ) Normal +AT91C_US_USMODE_RS485 EQU( 0x1 ); +-( USART ) RS485 +AT91C_US_USMODE_HWHSH EQU( 0x2 ); +-( USART ) Hardware Handshaking +AT91C_US_USMODE_MODEM EQU( 0x3 ); +-( USART ) Modem +AT91C_US_USMODE_ISO7816_0 EQU( 0x4 ); +-( USART ) ISO7816 protocol: T = 0 + AT91C_US_USMODE_ISO7816_1 EQU( 0x6 ); +-( USART ) ISO7816 protocol: T = 1 + AT91C_US_USMODE_IRDA EQU( 0x8 ); +-( USART ) IrDA +AT91C_US_USMODE_SWHSH EQU( 0xC ); +-( USART ) Software Handshaking +AT91C_US_CLKS EQU( 0x3 << 4 ); +-( USART ) Clock Selection ( Baud Rate generator Input Clock + AT91C_US_CLKS_CLOCK EQU( 0x0 << 4 ); + -( USART ) Clock + AT91C_US_CLKS_FDIV1 EQU( 0x1 << 4 ); + -( USART ) fdiv1 + AT91C_US_CLKS_SLOW EQU( 0x2 << 4 ); + -( USART ) slow_clock( ARM ) + AT91C_US_CLKS_EXT EQU( 0x3 << 4 ); + -( USART ) External( SCK ) + AT91C_US_CHRL EQU( 0x3 << 6 ); + -( USART ) Clock Selection ( Baud Rate generator Input Clock + AT91C_US_CHRL_5_BITS EQU( 0x0 << 6 ); + -( USART ) Character Length : 5 bits + AT91C_US_CHRL_6_BITS EQU( 0x1 << 6 ); + -( USART ) Character Length : 6 bits + AT91C_US_CHRL_7_BITS EQU( 0x2 << 6 ); + -( USART ) Character Length : 7 bits + AT91C_US_CHRL_8_BITS EQU( 0x3 << 6 ); + -( USART ) Character Length : 8 bits + AT91C_US_SYNC EQU( 0x1 << 8 ); + -( USART ) Synchronous Mode Select + AT91C_US_NBSTOP EQU( 0x3 << 12 ); + -( USART ) Number of Stop bits + AT91C_US_NBSTOP_1_BIT EQU( 0x0 << 12 ); + -( USART ) 1 stop bit + AT91C_US_NBSTOP_15_BIT EQU( 0x1 << 12 ); + -( USART ) Asynchronous( SYNC = 0 ) 2 stop bits Synchronous( SYNC = 1 ) 2 stop bits + AT91C_US_NBSTOP_2_BIT EQU( 0x2 << 12 ); + -( USART ) 2 stop bits + AT91C_US_MSBF EQU( 0x1 << 16 ); + -( USART ) Bit Order + AT91C_US_MODE9 EQU( 0x1 << 17 ); + -( USART ) 9 - bit Character length + AT91C_US_CKLO EQU( 0x1 << 18 ); + -( USART ) Clock Output Select + AT91C_US_OVER EQU( 0x1 << 19 ); + -( USART ) Over Sampling Mode + AT91C_US_INACK EQU( 0x1 << 20 ); + -( USART ) Inhibit Non Acknowledge + AT91C_US_DSNACK EQU( 0x1 << 21 ); + -( USART ) Disable Successive NACK + AT91C_US_MAX_ITER EQU( 0x1 << 24 ); + -( USART ) Number of Repetitions + AT91C_US_FILTER EQU( 0x1 << 28 ); + -( USART ) Receive Line Filter +/* - -------- US_IER : (USART Offset: 0x8) Debug Unit Interrupt Enable Register -------- */ + AT91C_US_RXBRK EQU( 0x1 << 2 ); + -( USART ) Break Received / End of Break + AT91C_US_TIMEOUT EQU( 0x1 << 8 ); + -( USART ) Receiver Time - out + AT91C_US_ITERATION EQU( 0x1 << 10 ); + -( USART ) Max number of Repetitions Reached + AT91C_US_NACK EQU( 0x1 << 13 ); + -( USART ) Non Acknowledge + AT91C_US_RIIC EQU( 0x1 << 16 ); + -( USART ) Ring INdicator Input Change Flag + AT91C_US_DSRIC EQU( 0x1 << 17 ); + -( USART ) Data Set Ready Input Change Flag + AT91C_US_DCDIC EQU( 0x1 << 18 ); + -( USART ) Data Carrier Flag + AT91C_US_CTSIC EQU( 0x1 << 19 ); + -( USART ) Clear To Send Input Change Flag +/* - -------- US_IDR : (USART Offset: 0xc) Debug Unit Interrupt Disable Register -------- */ +/* - -------- US_IMR : (USART Offset: 0x10) Debug Unit Interrupt Mask Register -------- */ +/* - -------- US_CSR : (USART Offset: 0x14) Debug Unit Channel Status Register -------- */ + AT91C_US_RI EQU( 0x1 << 20 ); + -( USART ) Image of RI Input + AT91C_US_DSR EQU( 0x1 << 21 ); + -( USART ) Image of DSR Input + AT91C_US_DCD EQU( 0x1 << 22 ); + -( USART ) Image of DCD Input + AT91C_US_CTS EQU( 0x1 << 23 ); + -( USART ) Image of CTS Input -// - ***************************************************************************** -// - SOFTWARE API DEFINITION FOR Ethernet MAC 10/100 -// - ***************************************************************************** -// - -------- EMAC_NCR : (EMAC Offset: 0x0) -------- -AT91C_EMAC_LB EQU (0x1 << 0) ;- (EMAC) Loopback. Optional. When set, loopback signal is at high level. -AT91C_EMAC_LLB EQU (0x1 << 1) ;- (EMAC) Loopback local. -AT91C_EMAC_RE EQU (0x1 << 2) ;- (EMAC) Receive enable. -AT91C_EMAC_TE EQU (0x1 << 3) ;- (EMAC) Transmit enable. -AT91C_EMAC_MPE EQU (0x1 << 4) ;- (EMAC) Management port enable. -AT91C_EMAC_CLRSTAT EQU (0x1 << 5) ;- (EMAC) Clear statistics registers. -AT91C_EMAC_INCSTAT EQU (0x1 << 6) ;- (EMAC) Increment statistics registers. -AT91C_EMAC_WESTAT EQU (0x1 << 7) ;- (EMAC) Write enable for statistics registers. -AT91C_EMAC_BP EQU (0x1 << 8) ;- (EMAC) Back pressure. -AT91C_EMAC_TSTART EQU (0x1 << 9) ;- (EMAC) Start Transmission. -AT91C_EMAC_THALT EQU (0x1 << 10) ;- (EMAC) Transmission Halt. -AT91C_EMAC_TPFR EQU (0x1 << 11) ;- (EMAC) Transmit pause frame -AT91C_EMAC_TZQ EQU (0x1 << 12) ;- (EMAC) Transmit zero quantum pause frame -// - -------- EMAC_NCFGR : (EMAC Offset: 0x4) Network Configuration Register -------- -AT91C_EMAC_SPD EQU (0x1 << 0) ;- (EMAC) Speed. -AT91C_EMAC_FD EQU (0x1 << 1) ;- (EMAC) Full duplex. -AT91C_EMAC_JFRAME EQU (0x1 << 3) ;- (EMAC) Jumbo Frames. -AT91C_EMAC_CAF EQU (0x1 << 4) ;- (EMAC) Copy all frames. -AT91C_EMAC_NBC EQU (0x1 << 5) ;- (EMAC) No broadcast. -AT91C_EMAC_MTI EQU (0x1 << 6) ;- (EMAC) Multicast hash event enable -AT91C_EMAC_UNI EQU (0x1 << 7) ;- (EMAC) Unicast hash enable. -AT91C_EMAC_BIG EQU (0x1 << 8) ;- (EMAC) Receive 1522 bytes. -AT91C_EMAC_EAE EQU (0x1 << 9) ;- (EMAC) External address match enable. -AT91C_EMAC_CLK EQU (0x3 << 10) ;- (EMAC) -AT91C_EMAC_CLK_HCLK_8 EQU (0x0 << 10) ;- (EMAC) HCLK divided by 8 -AT91C_EMAC_CLK_HCLK_16 EQU (0x1 << 10) ;- (EMAC) HCLK divided by 16 -AT91C_EMAC_CLK_HCLK_32 EQU (0x2 << 10) ;- (EMAC) HCLK divided by 32 -AT91C_EMAC_CLK_HCLK_64 EQU (0x3 << 10) ;- (EMAC) HCLK divided by 64 -AT91C_EMAC_RTY EQU (0x1 << 12) ;- (EMAC) -AT91C_EMAC_PAE EQU (0x1 << 13) ;- (EMAC) -AT91C_EMAC_RBOF EQU (0x3 << 14) ;- (EMAC) -AT91C_EMAC_RBOF_OFFSET_0 EQU (0x0 << 14) ;- (EMAC) no offset from start of receive buffer -AT91C_EMAC_RBOF_OFFSET_1 EQU (0x1 << 14) ;- (EMAC) one byte offset from start of receive buffer -AT91C_EMAC_RBOF_OFFSET_2 EQU (0x2 << 14) ;- (EMAC) two bytes offset from start of receive buffer -AT91C_EMAC_RBOF_OFFSET_3 EQU (0x3 << 14) ;- (EMAC) three bytes offset from start of receive buffer -AT91C_EMAC_RLCE EQU (0x1 << 16) ;- (EMAC) Receive Length field Checking Enable -AT91C_EMAC_DRFCS EQU (0x1 << 17) ;- (EMAC) Discard Receive FCS -AT91C_EMAC_EFRHD EQU (0x1 << 18) ;- (EMAC) -AT91C_EMAC_IRXFCS EQU (0x1 << 19) ;- (EMAC) Ignore RX FCS -// - -------- EMAC_NSR : (EMAC Offset: 0x8) Network Status Register -------- -AT91C_EMAC_LINKR EQU (0x1 << 0) ;- (EMAC) -AT91C_EMAC_MDIO EQU (0x1 << 1) ;- (EMAC) -AT91C_EMAC_IDLE EQU (0x1 << 2) ;- (EMAC) -// - -------- EMAC_TSR : (EMAC Offset: 0x14) Transmit Status Register -------- -AT91C_EMAC_UBR EQU (0x1 << 0) ;- (EMAC) -AT91C_EMAC_COL EQU (0x1 << 1) ;- (EMAC) -AT91C_EMAC_RLES EQU (0x1 << 2) ;- (EMAC) -AT91C_EMAC_TGO EQU (0x1 << 3) ;- (EMAC) Transmit Go -AT91C_EMAC_BEX EQU (0x1 << 4) ;- (EMAC) Buffers exhausted mid frame -AT91C_EMAC_COMP EQU (0x1 << 5) ;- (EMAC) -AT91C_EMAC_UND EQU (0x1 << 6) ;- (EMAC) -// - -------- EMAC_RSR : (EMAC Offset: 0x20) Receive Status Register -------- -AT91C_EMAC_BNA EQU (0x1 << 0) ;- (EMAC) -AT91C_EMAC_REC EQU (0x1 << 1) ;- (EMAC) -AT91C_EMAC_OVR EQU (0x1 << 2) ;- (EMAC) -// - -------- EMAC_ISR : (EMAC Offset: 0x24) Interrupt Status Register -------- -AT91C_EMAC_MFD EQU (0x1 << 0) ;- (EMAC) -AT91C_EMAC_RCOMP EQU (0x1 << 1) ;- (EMAC) -AT91C_EMAC_RXUBR EQU (0x1 << 2) ;- (EMAC) -AT91C_EMAC_TXUBR EQU (0x1 << 3) ;- (EMAC) -AT91C_EMAC_TUNDR EQU (0x1 << 4) ;- (EMAC) -AT91C_EMAC_RLEX EQU (0x1 << 5) ;- (EMAC) -AT91C_EMAC_TXERR EQU (0x1 << 6) ;- (EMAC) -AT91C_EMAC_TCOMP EQU (0x1 << 7) ;- (EMAC) -AT91C_EMAC_LINK EQU (0x1 << 9) ;- (EMAC) -AT91C_EMAC_ROVR EQU (0x1 << 10) ;- (EMAC) -AT91C_EMAC_HRESP EQU (0x1 << 11) ;- (EMAC) -AT91C_EMAC_PFRE EQU (0x1 << 12) ;- (EMAC) -AT91C_EMAC_PTZ EQU (0x1 << 13) ;- (EMAC) -// - -------- EMAC_IER : (EMAC Offset: 0x28) Interrupt Enable Register -------- -// - -------- EMAC_IDR : (EMAC Offset: 0x2c) Interrupt Disable Register -------- -// - -------- EMAC_IMR : (EMAC Offset: 0x30) Interrupt Mask Register -------- -// - -------- EMAC_MAN : (EMAC Offset: 0x34) PHY Maintenance Register -------- -AT91C_EMAC_DATA EQU (0xFFFF << 0) ;- (EMAC) -AT91C_EMAC_CODE EQU (0x3 << 16) ;- (EMAC) -AT91C_EMAC_REGA EQU (0x1F << 18) ;- (EMAC) -AT91C_EMAC_PHYA EQU (0x1F << 23) ;- (EMAC) -AT91C_EMAC_RW EQU (0x3 << 28) ;- (EMAC) -AT91C_EMAC_SOF EQU (0x3 << 30) ;- (EMAC) -// - -------- EMAC_USRIO : (EMAC Offset: 0xc0) USER Input Output Register -------- -AT91C_EMAC_RMII EQU (0x1 << 0) ;- (EMAC) Reduce MII -// - -------- EMAC_WOL : (EMAC Offset: 0xc4) Wake On LAN Register -------- -AT91C_EMAC_IP EQU (0xFFFF << 0) ;- (EMAC) ARP request IP address -AT91C_EMAC_MAG EQU (0x1 << 16) ;- (EMAC) Magic packet event enable -AT91C_EMAC_ARP EQU (0x1 << 17) ;- (EMAC) ARP request event enable -AT91C_EMAC_SA1 EQU (0x1 << 18) ;- (EMAC) Specific address register 1 event enable -// - -------- EMAC_REV : (EMAC Offset: 0xfc) Revision Register -------- -AT91C_EMAC_REVREF EQU (0xFFFF << 0) ;- (EMAC) -AT91C_EMAC_PARTREF EQU (0xFFFF << 16) ;- (EMAC) +/* - ***************************************************************************** */ +/* - SOFTWARE API DEFINITION FOR Synchronous Serial Controller Interface */ +/* - ***************************************************************************** */ +/* - -------- SSC_CR : (SSC Offset: 0x0) SSC Control Register -------- */ + AT91C_SSC_RXEN EQU( 0x1 << 0 ); + -( SSC ) Receive Enable + AT91C_SSC_RXDIS EQU( 0x1 << 1 ); + -( SSC ) Receive Disable + AT91C_SSC_TXEN EQU( 0x1 << 8 ); + -( SSC ) Transmit Enable + AT91C_SSC_TXDIS EQU( 0x1 << 9 ); + -( SSC ) Transmit Disable + AT91C_SSC_SWRST EQU( 0x1 << 15 ); + -( SSC ) Software Reset +/* - -------- SSC_RCMR : (SSC Offset: 0x10) SSC Receive Clock Mode Register -------- */ + AT91C_SSC_CKS EQU( 0x3 << 0 ); + -( SSC ) Receive / Transmit Clock Selection + AT91C_SSC_CKS_DIV EQU( 0x0 ); + -( SSC ) Divided Clock + AT91C_SSC_CKS_TK EQU( 0x1 ); + -( SSC ) TK Clock signal + AT91C_SSC_CKS_RK EQU( 0x2 ); + -( SSC ) RK pin + AT91C_SSC_CKO EQU( 0x7 << 2 ); + -( SSC ) Receive / Transmit Clock Output Mode Selection + AT91C_SSC_CKO_NONE EQU( 0x0 << 2 ); + -( SSC ) Receive / Transmit Clock Output Mode:None RK pin: Input - only + AT91C_SSC_CKO_CONTINUOUS EQU( 0x1 << 2 ); + -( SSC ) Continuous Receive / Transmit Clock RK pin:Output + AT91C_SSC_CKO_DATA_TX EQU( 0x2 << 2 ); + -( SSC ) Receive / Transmit Clock only during data transfers RK pin:Output + AT91C_SSC_CKI EQU( 0x1 << 5 ); + -( SSC ) Receive / Transmit Clock Inversion + AT91C_SSC_START EQU( 0xF << 8 ); + -( SSC ) Receive / Transmit Start Selection + AT91C_SSC_START_CONTINUOUS EQU( 0x0 << 8 ); + -( SSC ) Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data. + AT91C_SSC_START_TX EQU( 0x1 << 8 ); + -( SSC ) Transmit / Receive start + AT91C_SSC_START_LOW_RF EQU( 0x2 << 8 ); + -( SSC ) Detection of a low level on RF input + AT91C_SSC_START_HIGH_RF EQU( 0x3 << 8 ); + -( SSC ) Detection of a high level on RF input + AT91C_SSC_START_FALL_RF EQU( 0x4 << 8 ); + -( SSC ) Detection of a falling edge on RF input + AT91C_SSC_START_RISE_RF EQU( 0x5 << 8 ); + -( SSC ) Detection of a rising edge on RF input + AT91C_SSC_START_LEVEL_RF EQU( 0x6 << 8 ); + -( SSC ) Detection of any level change on RF input + AT91C_SSC_START_EDGE_RF EQU( 0x7 << 8 ); + -( SSC ) Detection of any edge on RF input + AT91C_SSC_START_0 EQU( 0x8 << 8 ); + -( SSC ) Compare 0 + AT91C_SSC_STTDLY EQU( 0xFF << 16 ); + -( SSC ) Receive / Transmit Start Delay + AT91C_SSC_PERIOD EQU( 0xFF << 24 ); + -( SSC ) Receive / Transmit Period Divider Selection +/* - -------- SSC_RFMR : (SSC Offset: 0x14) SSC Receive Frame Mode Register -------- */ + AT91C_SSC_DATLEN EQU( 0x1F << 0 ); + -( SSC ) Data Length + AT91C_SSC_LOOP EQU( 0x1 << 5 ); + -( SSC ) Loop Mode + AT91C_SSC_MSBF EQU( 0x1 << 7 ); + -( SSC ) Most Significant Bit First + AT91C_SSC_DATNB EQU( 0xF << 8 ); + -( SSC ) Data Number per Frame + AT91C_SSC_FSLEN EQU( 0xF << 16 ); + -( SSC ) Receive / Transmit Frame Sync length + AT91C_SSC_FSOS EQU( 0x7 << 20 ); + -( SSC ) Receive / Transmit Frame Sync Output Selection + AT91C_SSC_FSOS_NONE EQU( 0x0 << 20 ); + -( SSC ) Selected Receive / Transmit Frame Sync Signal:None RK pin Input - only + AT91C_SSC_FSOS_NEGATIVE EQU( 0x1 << 20 ); + -( SSC ) Selected Receive / Transmit Frame Sync Signal:Negative Pulse + AT91C_SSC_FSOS_POSITIVE EQU( 0x2 << 20 ); + -( SSC ) Selected Receive / Transmit Frame Sync Signal:Positive Pulse + AT91C_SSC_FSOS_LOW EQU( 0x3 << 20 ); + -( SSC ) Selected Receive / Transmit Frame Sync Signal:Driver Low during data transfer + AT91C_SSC_FSOS_HIGH EQU( 0x4 << 20 ); + -( SSC ) Selected Receive / Transmit Frame Sync Signal:Driver High during data transfer + AT91C_SSC_FSOS_TOGGLE EQU( 0x5 << 20 ); + -( SSC ) Selected Receive / Transmit Frame Sync Signal:Toggling at each start of data transfer + AT91C_SSC_FSEDGE EQU( 0x1 << 24 ); + -( SSC ) Frame Sync Edge Detection +/* - -------- SSC_TCMR : (SSC Offset: 0x18) SSC Transmit Clock Mode Register -------- */ +/* - -------- SSC_TFMR : (SSC Offset: 0x1c) SSC Transmit Frame Mode Register -------- */ + AT91C_SSC_DATDEF EQU( 0x1 << 5 ); + -( SSC ) Data Default Value + AT91C_SSC_FSDEN EQU( 0x1 << 23 ); + -( SSC ) Frame Sync Data Enable +/* - -------- SSC_SR : (SSC Offset: 0x40) SSC Status Register -------- */ + AT91C_SSC_TXRDY EQU( 0x1 << 0 ); + -( SSC ) Transmit Ready + AT91C_SSC_TXEMPTY EQU( 0x1 << 1 ); + -( SSC ) Transmit Empty + AT91C_SSC_ENDTX EQU( 0x1 << 2 ); + -( SSC ) End Of Transmission + AT91C_SSC_TXBUFE EQU( 0x1 << 3 ); + -( SSC ) Transmit Buffer Empty + AT91C_SSC_RXRDY EQU( 0x1 << 4 ); + -( SSC ) Receive Ready + AT91C_SSC_OVRUN EQU( 0x1 << 5 ); + -( SSC ) Receive Overrun + AT91C_SSC_ENDRX EQU( 0x1 << 6 ); + -( SSC ) End of Reception + AT91C_SSC_RXBUFF EQU( 0x1 << 7 ); + -( SSC ) Receive Buffer Full + AT91C_SSC_TXSYN EQU( 0x1 << 10 ); + -( SSC ) Transmit Sync + AT91C_SSC_RXSYN EQU( 0x1 << 11 ); + -( SSC ) Receive Sync + AT91C_SSC_TXENA EQU( 0x1 << 16 ); + -( SSC ) Transmit Enable + AT91C_SSC_RXENA EQU( 0x1 << 17 ); + -( SSC ) Receive Enable +/* - -------- SSC_IER : (SSC Offset: 0x44) SSC Interrupt Enable Register -------- */ +/* - -------- SSC_IDR : (SSC Offset: 0x48) SSC Interrupt Disable Register -------- */ +/* - -------- SSC_IMR : (SSC Offset: 0x4c) SSC Interrupt Mask Register -------- */ -// - ***************************************************************************** -// - SOFTWARE API DEFINITION FOR Analog to Digital Convertor -// - ***************************************************************************** -// - -------- ADC_CR : (ADC Offset: 0x0) ADC Control Register -------- -AT91C_ADC_SWRST EQU (0x1 << 0) ;- (ADC) Software Reset -AT91C_ADC_START EQU (0x1 << 1) ;- (ADC) Start Conversion -// - -------- ADC_MR : (ADC Offset: 0x4) ADC Mode Register -------- -AT91C_ADC_TRGEN EQU (0x1 << 0) ;- (ADC) Trigger Enable -AT91C_ADC_TRGEN_DIS EQU (0x0) ;- (ADC) Hradware triggers are disabled. Starting a conversion is only possible by software -AT91C_ADC_TRGEN_EN EQU (0x1) ;- (ADC) Hardware trigger selected by TRGSEL field is enabled. -AT91C_ADC_TRGSEL EQU (0x7 << 1) ;- (ADC) Trigger Selection -AT91C_ADC_TRGSEL_TIOA0 EQU (0x0 << 1) ;- (ADC) Selected TRGSEL = TIAO0 -AT91C_ADC_TRGSEL_TIOA1 EQU (0x1 << 1) ;- (ADC) Selected TRGSEL = TIAO1 -AT91C_ADC_TRGSEL_TIOA2 EQU (0x2 << 1) ;- (ADC) Selected TRGSEL = TIAO2 -AT91C_ADC_TRGSEL_TIOA3 EQU (0x3 << 1) ;- (ADC) Selected TRGSEL = TIAO3 -AT91C_ADC_TRGSEL_TIOA4 EQU (0x4 << 1) ;- (ADC) Selected TRGSEL = TIAO4 -AT91C_ADC_TRGSEL_TIOA5 EQU (0x5 << 1) ;- (ADC) Selected TRGSEL = TIAO5 -AT91C_ADC_TRGSEL_EXT EQU (0x6 << 1) ;- (ADC) Selected TRGSEL = External Trigger -AT91C_ADC_LOWRES EQU (0x1 << 4) ;- (ADC) Resolution. -AT91C_ADC_LOWRES_10_BIT EQU (0x0 << 4) ;- (ADC) 10-bit resolution -AT91C_ADC_LOWRES_8_BIT EQU (0x1 << 4) ;- (ADC) 8-bit resolution -AT91C_ADC_SLEEP EQU (0x1 << 5) ;- (ADC) Sleep Mode -AT91C_ADC_SLEEP_NORMAL_MODE EQU (0x0 << 5) ;- (ADC) Normal Mode -AT91C_ADC_SLEEP_MODE EQU (0x1 << 5) ;- (ADC) Sleep Mode -AT91C_ADC_PRESCAL EQU (0x3F << 8) ;- (ADC) Prescaler rate selection -AT91C_ADC_STARTUP EQU (0x1F << 16) ;- (ADC) Startup Time -AT91C_ADC_SHTIM EQU (0xF << 24) ;- (ADC) Sample & Hold Time -// - -------- ADC_CHER : (ADC Offset: 0x10) ADC Channel Enable Register -------- -AT91C_ADC_CH0 EQU (0x1 << 0) ;- (ADC) Channel 0 -AT91C_ADC_CH1 EQU (0x1 << 1) ;- (ADC) Channel 1 -AT91C_ADC_CH2 EQU (0x1 << 2) ;- (ADC) Channel 2 -AT91C_ADC_CH3 EQU (0x1 << 3) ;- (ADC) Channel 3 -AT91C_ADC_CH4 EQU (0x1 << 4) ;- (ADC) Channel 4 -AT91C_ADC_CH5 EQU (0x1 << 5) ;- (ADC) Channel 5 -AT91C_ADC_CH6 EQU (0x1 << 6) ;- (ADC) Channel 6 -AT91C_ADC_CH7 EQU (0x1 << 7) ;- (ADC) Channel 7 -// - -------- ADC_CHDR : (ADC Offset: 0x14) ADC Channel Disable Register -------- -// - -------- ADC_CHSR : (ADC Offset: 0x18) ADC Channel Status Register -------- -// - -------- ADC_SR : (ADC Offset: 0x1c) ADC Status Register -------- -AT91C_ADC_EOC0 EQU (0x1 << 0) ;- (ADC) End of Conversion -AT91C_ADC_EOC1 EQU (0x1 << 1) ;- (ADC) End of Conversion -AT91C_ADC_EOC2 EQU (0x1 << 2) ;- (ADC) End of Conversion -AT91C_ADC_EOC3 EQU (0x1 << 3) ;- (ADC) End of Conversion -AT91C_ADC_EOC4 EQU (0x1 << 4) ;- (ADC) End of Conversion -AT91C_ADC_EOC5 EQU (0x1 << 5) ;- (ADC) End of Conversion -AT91C_ADC_EOC6 EQU (0x1 << 6) ;- (ADC) End of Conversion -AT91C_ADC_EOC7 EQU (0x1 << 7) ;- (ADC) End of Conversion -AT91C_ADC_OVRE0 EQU (0x1 << 8) ;- (ADC) Overrun Error -AT91C_ADC_OVRE1 EQU (0x1 << 9) ;- (ADC) Overrun Error -AT91C_ADC_OVRE2 EQU (0x1 << 10) ;- (ADC) Overrun Error -AT91C_ADC_OVRE3 EQU (0x1 << 11) ;- (ADC) Overrun Error -AT91C_ADC_OVRE4 EQU (0x1 << 12) ;- (ADC) Overrun Error -AT91C_ADC_OVRE5 EQU (0x1 << 13) ;- (ADC) Overrun Error -AT91C_ADC_OVRE6 EQU (0x1 << 14) ;- (ADC) Overrun Error -AT91C_ADC_OVRE7 EQU (0x1 << 15) ;- (ADC) Overrun Error -AT91C_ADC_DRDY EQU (0x1 << 16) ;- (ADC) Data Ready -AT91C_ADC_GOVRE EQU (0x1 << 17) ;- (ADC) General Overrun -AT91C_ADC_ENDRX EQU (0x1 << 18) ;- (ADC) End of Receiver Transfer -AT91C_ADC_RXBUFF EQU (0x1 << 19) ;- (ADC) RXBUFF Interrupt -// - -------- ADC_LCDR : (ADC Offset: 0x20) ADC Last Converted Data Register -------- -AT91C_ADC_LDATA EQU (0x3FF << 0) ;- (ADC) Last Data Converted -// - -------- ADC_IER : (ADC Offset: 0x24) ADC Interrupt Enable Register -------- -// - -------- ADC_IDR : (ADC Offset: 0x28) ADC Interrupt Disable Register -------- -// - -------- ADC_IMR : (ADC Offset: 0x2c) ADC Interrupt Mask Register -------- -// - -------- ADC_CDR0 : (ADC Offset: 0x30) ADC Channel Data Register 0 -------- -AT91C_ADC_DATA EQU (0x3FF << 0) ;- (ADC) Converted Data -// - -------- ADC_CDR1 : (ADC Offset: 0x34) ADC Channel Data Register 1 -------- -// - -------- ADC_CDR2 : (ADC Offset: 0x38) ADC Channel Data Register 2 -------- -// - -------- ADC_CDR3 : (ADC Offset: 0x3c) ADC Channel Data Register 3 -------- -// - -------- ADC_CDR4 : (ADC Offset: 0x40) ADC Channel Data Register 4 -------- -// - -------- ADC_CDR5 : (ADC Offset: 0x44) ADC Channel Data Register 5 -------- -// - -------- ADC_CDR6 : (ADC Offset: 0x48) ADC Channel Data Register 6 -------- -// - -------- ADC_CDR7 : (ADC Offset: 0x4c) ADC Channel Data Register 7 -------- +/* - ***************************************************************************** */ +/* - SOFTWARE API DEFINITION FOR Two-wire Interface */ +/* - ***************************************************************************** */ +/* - -------- TWI_CR : (TWI Offset: 0x0) TWI Control Register -------- */ + AT91C_TWI_START EQU( 0x1 << 0 ); + -( TWI ) Send a START Condition + AT91C_TWI_STOP EQU( 0x1 << 1 ); + -( TWI ) Send a STOP Condition + AT91C_TWI_MSEN EQU( 0x1 << 2 ); + -( TWI ) TWI Master Transfer Enabled + AT91C_TWI_MSDIS EQU( 0x1 << 3 ); + -( TWI ) TWI Master Transfer Disabled + AT91C_TWI_SWRST EQU( 0x1 << 7 ); + -( TWI ) Software Reset +/* - -------- TWI_MMR : (TWI Offset: 0x4) TWI Master Mode Register -------- */ + AT91C_TWI_IADRSZ EQU( 0x3 << 8 ); + -( TWI ) Internal Device Address Size + AT91C_TWI_IADRSZ_NO EQU( 0x0 << 8 ); + -( TWI ) No internal device address + AT91C_TWI_IADRSZ_1_BYTE EQU( 0x1 << 8 ); + -( TWI ) One - byte internal device address + AT91C_TWI_IADRSZ_2_BYTE EQU( 0x2 << 8 ); + -( TWI ) Two - byte internal device address + AT91C_TWI_IADRSZ_3_BYTE EQU( 0x3 << 8 ); + -( TWI ) Three - byte internal device address + AT91C_TWI_MREAD EQU( 0x1 << 12 ); + -( TWI ) Master Read Direction + AT91C_TWI_DADR EQU( 0x7F << 16 ); + -( TWI ) Device Address +/* - -------- TWI_CWGR : (TWI Offset: 0x10) TWI Clock Waveform Generator Register -------- */ + AT91C_TWI_CLDIV EQU( 0xFF << 0 ); + -( TWI ) Clock Low Divider + AT91C_TWI_CHDIV EQU( 0xFF << 8 ); + -( TWI ) Clock High Divider + AT91C_TWI_CKDIV EQU( 0x7 << 16 ); + -( TWI ) Clock Divider +/* - -------- TWI_SR : (TWI Offset: 0x20) TWI Status Register -------- */ + AT91C_TWI_TXCOMP EQU( 0x1 << 0 ); + -( TWI ) Transmission Completed + AT91C_TWI_RXRDY EQU( 0x1 << 1 ); + -( TWI ) Receive holding register ReaDY + AT91C_TWI_TXRDY EQU( 0x1 << 2 ); + -( TWI ) Transmit holding register ReaDY + AT91C_TWI_OVRE EQU( 0x1 << 6 ); + -( TWI ) Overrun Error + AT91C_TWI_UNRE EQU( 0x1 << 7 ); + -( TWI ) Underrun Error + AT91C_TWI_NACK EQU( 0x1 << 8 ); + -( TWI ) Not Acknowledged +/* - -------- TWI_IER : (TWI Offset: 0x24) TWI Interrupt Enable Register -------- */ +/* - -------- TWI_IDR : (TWI Offset: 0x28) TWI Interrupt Disable Register -------- */ +/* - -------- TWI_IMR : (TWI Offset: 0x2c) TWI Interrupt Mask Register -------- */ -// - ***************************************************************************** -// - SOFTWARE API DEFINITION FOR Advanced Encryption Standard -// - ***************************************************************************** -// - -------- AES_CR : (AES Offset: 0x0) Control Register -------- -AT91C_AES_START EQU (0x1 << 0) ;- (AES) Starts Processing -AT91C_AES_SWRST EQU (0x1 << 8) ;- (AES) Software Reset -AT91C_AES_LOADSEED EQU (0x1 << 16) ;- (AES) Random Number Generator Seed Loading -// - -------- AES_MR : (AES Offset: 0x4) Mode Register -------- -AT91C_AES_CIPHER EQU (0x1 << 0) ;- (AES) Processing Mode -AT91C_AES_PROCDLY EQU (0xF << 4) ;- (AES) Processing Delay -AT91C_AES_SMOD EQU (0x3 << 8) ;- (AES) Start Mode -AT91C_AES_SMOD_MANUAL EQU (0x0 << 8) ;- (AES) Manual Mode: The START bit in register AES_CR must be set to begin encryption or decryption. -AT91C_AES_SMOD_AUTO EQU (0x1 << 8) ;- (AES) Auto Mode: no action in AES_CR is necessary (cf datasheet). -AT91C_AES_SMOD_PDC EQU (0x2 << 8) ;- (AES) PDC Mode (cf datasheet). -AT91C_AES_OPMOD EQU (0x7 << 12) ;- (AES) Operation Mode -AT91C_AES_OPMOD_ECB EQU (0x0 << 12) ;- (AES) ECB Electronic CodeBook mode. -AT91C_AES_OPMOD_CBC EQU (0x1 << 12) ;- (AES) CBC Cipher Block Chaining mode. -AT91C_AES_OPMOD_OFB EQU (0x2 << 12) ;- (AES) OFB Output Feedback mode. -AT91C_AES_OPMOD_CFB EQU (0x3 << 12) ;- (AES) CFB Cipher Feedback mode. -AT91C_AES_OPMOD_CTR EQU (0x4 << 12) ;- (AES) CTR Counter mode. -AT91C_AES_LOD EQU (0x1 << 15) ;- (AES) Last Output Data Mode -AT91C_AES_CFBS EQU (0x7 << 16) ;- (AES) Cipher Feedback Data Size -AT91C_AES_CFBS_128_BIT EQU (0x0 << 16) ;- (AES) 128-bit. -AT91C_AES_CFBS_64_BIT EQU (0x1 << 16) ;- (AES) 64-bit. -AT91C_AES_CFBS_32_BIT EQU (0x2 << 16) ;- (AES) 32-bit. -AT91C_AES_CFBS_16_BIT EQU (0x3 << 16) ;- (AES) 16-bit. -AT91C_AES_CFBS_8_BIT EQU (0x4 << 16) ;- (AES) 8-bit. -AT91C_AES_CKEY EQU (0xF << 20) ;- (AES) Countermeasure Key -AT91C_AES_CTYPE EQU (0x1F << 24) ;- (AES) Countermeasure Type -AT91C_AES_CTYPE_TYPE1_EN EQU (0x1 << 24) ;- (AES) Countermeasure type 1 is enabled. -AT91C_AES_CTYPE_TYPE2_EN EQU (0x2 << 24) ;- (AES) Countermeasure type 2 is enabled. -AT91C_AES_CTYPE_TYPE3_EN EQU (0x4 << 24) ;- (AES) Countermeasure type 3 is enabled. -AT91C_AES_CTYPE_TYPE4_EN EQU (0x8 << 24) ;- (AES) Countermeasure type 4 is enabled. -AT91C_AES_CTYPE_TYPE5_EN EQU (0x10 << 24) ;- (AES) Countermeasure type 5 is enabled. -// - -------- AES_IER : (AES Offset: 0x10) Interrupt Enable Register -------- -AT91C_AES_DATRDY EQU (0x1 << 0) ;- (AES) DATRDY -AT91C_AES_ENDRX EQU (0x1 << 1) ;- (AES) PDC Read Buffer End -AT91C_AES_ENDTX EQU (0x1 << 2) ;- (AES) PDC Write Buffer End -AT91C_AES_RXBUFF EQU (0x1 << 3) ;- (AES) PDC Read Buffer Full -AT91C_AES_TXBUFE EQU (0x1 << 4) ;- (AES) PDC Write Buffer Empty -AT91C_AES_URAD EQU (0x1 << 8) ;- (AES) Unspecified Register Access Detection -// - -------- AES_IDR : (AES Offset: 0x14) Interrupt Disable Register -------- -// - -------- AES_IMR : (AES Offset: 0x18) Interrupt Mask Register -------- -// - -------- AES_ISR : (AES Offset: 0x1c) Interrupt Status Register -------- -AT91C_AES_URAT EQU (0x7 << 12) ;- (AES) Unspecified Register Access Type Status -AT91C_AES_URAT_IN_DAT_WRITE_DATPROC EQU (0x0 << 12) ;- (AES) Input data register written during the data processing in PDC mode. -AT91C_AES_URAT_OUT_DAT_READ_DATPROC EQU (0x1 << 12) ;- (AES) Output data register read during the data processing. -AT91C_AES_URAT_MODEREG_WRITE_DATPROC EQU (0x2 << 12) ;- (AES) Mode register written during the data processing. -AT91C_AES_URAT_OUT_DAT_READ_SUBKEY EQU (0x3 << 12) ;- (AES) Output data register read during the sub-keys generation. -AT91C_AES_URAT_MODEREG_WRITE_SUBKEY EQU (0x4 << 12) ;- (AES) Mode register written during the sub-keys generation. -AT91C_AES_URAT_WO_REG_READ EQU (0x5 << 12) ;- (AES) Write-only register read access. +/* - ***************************************************************************** */ +/* - SOFTWARE API DEFINITION FOR PWMC Channel Interface */ +/* - ***************************************************************************** */ +/* - -------- PWMC_CMR : (PWMC_CH Offset: 0x0) PWMC Channel Mode Register -------- */ + AT91C_PWMC_CPRE EQU( 0xF << 0 ); + -( PWMC_CH ) Channel Pre - scaler:PWMC_CLKx + AT91C_PWMC_CPRE_MCK EQU( 0x0 ); + -( PWMC_CH ) + AT91C_PWMC_CPRE_MCKA EQU( 0xB ); + -( PWMC_CH ) + AT91C_PWMC_CPRE_MCKB EQU( 0xC ); + -( PWMC_CH ) + AT91C_PWMC_CALG EQU( 0x1 << 8 ); + -( PWMC_CH ) Channel Alignment + AT91C_PWMC_CPOL EQU( 0x1 << 9 ); + -( PWMC_CH ) Channel Polarity + AT91C_PWMC_CPD EQU( 0x1 << 10 ); + -( PWMC_CH ) Channel Update Period +/* - -------- PWMC_CDTYR : (PWMC_CH Offset: 0x4) PWMC Channel Duty Cycle Register -------- */ + AT91C_PWMC_CDTY EQU( 0x0 << 0 ); + -( PWMC_CH ) Channel Duty Cycle +/* - -------- PWMC_CPRDR : (PWMC_CH Offset: 0x8) PWMC Channel Period Register -------- */ + AT91C_PWMC_CPRD EQU( 0x0 << 0 ); + -( PWMC_CH ) Channel Period +/* - -------- PWMC_CCNTR : (PWMC_CH Offset: 0xc) PWMC Channel Counter Register -------- */ + AT91C_PWMC_CCNT EQU( 0x0 << 0 ); + -( PWMC_CH ) Channel Counter +/* - -------- PWMC_CUPDR : (PWMC_CH Offset: 0x10) PWMC Channel Update Register -------- */ + AT91C_PWMC_CUPD EQU( 0x0 << 0 ); + -( PWMC_CH ) Channel Update -// - ***************************************************************************** -// - SOFTWARE API DEFINITION FOR Triple Data Encryption Standard -// - ***************************************************************************** -// - -------- TDES_CR : (TDES Offset: 0x0) Control Register -------- -AT91C_TDES_START EQU (0x1 << 0) ;- (TDES) Starts Processing -AT91C_TDES_SWRST EQU (0x1 << 8) ;- (TDES) Software Reset -// - -------- TDES_MR : (TDES Offset: 0x4) Mode Register -------- -AT91C_TDES_CIPHER EQU (0x1 << 0) ;- (TDES) Processing Mode -AT91C_TDES_TDESMOD EQU (0x1 << 1) ;- (TDES) Single or Triple DES Mode -AT91C_TDES_KEYMOD EQU (0x1 << 4) ;- (TDES) Key Mode -AT91C_TDES_SMOD EQU (0x3 << 8) ;- (TDES) Start Mode -AT91C_TDES_SMOD_MANUAL EQU (0x0 << 8) ;- (TDES) Manual Mode: The START bit in register TDES_CR must be set to begin encryption or decryption. -AT91C_TDES_SMOD_AUTO EQU (0x1 << 8) ;- (TDES) Auto Mode: no action in TDES_CR is necessary (cf datasheet). -AT91C_TDES_SMOD_PDC EQU (0x2 << 8) ;- (TDES) PDC Mode (cf datasheet). -AT91C_TDES_OPMOD EQU (0x3 << 12) ;- (TDES) Operation Mode -AT91C_TDES_OPMOD_ECB EQU (0x0 << 12) ;- (TDES) ECB Electronic CodeBook mode. -AT91C_TDES_OPMOD_CBC EQU (0x1 << 12) ;- (TDES) CBC Cipher Block Chaining mode. -AT91C_TDES_OPMOD_OFB EQU (0x2 << 12) ;- (TDES) OFB Output Feedback mode. -AT91C_TDES_OPMOD_CFB EQU (0x3 << 12) ;- (TDES) CFB Cipher Feedback mode. -AT91C_TDES_LOD EQU (0x1 << 15) ;- (TDES) Last Output Data Mode -AT91C_TDES_CFBS EQU (0x3 << 16) ;- (TDES) Cipher Feedback Data Size -AT91C_TDES_CFBS_64_BIT EQU (0x0 << 16) ;- (TDES) 64-bit. -AT91C_TDES_CFBS_32_BIT EQU (0x1 << 16) ;- (TDES) 32-bit. -AT91C_TDES_CFBS_16_BIT EQU (0x2 << 16) ;- (TDES) 16-bit. -AT91C_TDES_CFBS_8_BIT EQU (0x3 << 16) ;- (TDES) 8-bit. -// - -------- TDES_IER : (TDES Offset: 0x10) Interrupt Enable Register -------- -AT91C_TDES_DATRDY EQU (0x1 << 0) ;- (TDES) DATRDY -AT91C_TDES_ENDRX EQU (0x1 << 1) ;- (TDES) PDC Read Buffer End -AT91C_TDES_ENDTX EQU (0x1 << 2) ;- (TDES) PDC Write Buffer End -AT91C_TDES_RXBUFF EQU (0x1 << 3) ;- (TDES) PDC Read Buffer Full -AT91C_TDES_TXBUFE EQU (0x1 << 4) ;- (TDES) PDC Write Buffer Empty -AT91C_TDES_URAD EQU (0x1 << 8) ;- (TDES) Unspecified Register Access Detection -// - -------- TDES_IDR : (TDES Offset: 0x14) Interrupt Disable Register -------- -// - -------- TDES_IMR : (TDES Offset: 0x18) Interrupt Mask Register -------- -// - -------- TDES_ISR : (TDES Offset: 0x1c) Interrupt Status Register -------- -AT91C_TDES_URAT EQU (0x3 << 12) ;- (TDES) Unspecified Register Access Type Status -AT91C_TDES_URAT_IN_DAT_WRITE_DATPROC EQU (0x0 << 12) ;- (TDES) Input data register written during the data processing in PDC mode. -AT91C_TDES_URAT_OUT_DAT_READ_DATPROC EQU (0x1 << 12) ;- (TDES) Output data register read during the data processing. -AT91C_TDES_URAT_MODEREG_WRITE_DATPROC EQU (0x2 << 12) ;- (TDES) Mode register written during the data processing. -AT91C_TDES_URAT_WO_REG_READ EQU (0x3 << 12) ;- (TDES) Write-only register read access. +/* - ***************************************************************************** */ +/* - SOFTWARE API DEFINITION FOR Pulse Width Modulation Controller Interface */ +/* - ***************************************************************************** */ +/* - -------- PWMC_MR : (PWMC Offset: 0x0) PWMC Mode Register -------- */ + AT91C_PWMC_DIVA EQU( 0xFF << 0 ); + -( PWMC ) CLKA divide factor. + AT91C_PWMC_PREA EQU( 0xF << 8 ); + -( PWMC ) Divider Input Clock Prescaler A + AT91C_PWMC_PREA_MCK EQU( 0x0 << 8 ); + -( PWMC ) + AT91C_PWMC_DIVB EQU( 0xFF << 16 ); + -( PWMC ) CLKB divide factor. + AT91C_PWMC_PREB EQU( 0xF << 24 ); + -( PWMC ) Divider Input Clock Prescaler B + AT91C_PWMC_PREB_MCK EQU( 0x0 << 24 ); + -( PWMC ) +/* - -------- PWMC_ENA : (PWMC Offset: 0x4) PWMC Enable Register -------- */ + AT91C_PWMC_CHID0 EQU( 0x1 << 0 ); + -( PWMC ) Channel ID 0 + AT91C_PWMC_CHID1 EQU( 0x1 << 1 ); + -( PWMC ) Channel ID 1 + AT91C_PWMC_CHID2 EQU( 0x1 << 2 ); + -( PWMC ) Channel ID 2 + AT91C_PWMC_CHID3 EQU( 0x1 << 3 ); + -( PWMC ) Channel ID 3 +/* - -------- PWMC_DIS : (PWMC Offset: 0x8) PWMC Disable Register -------- */ +/* - -------- PWMC_SR : (PWMC Offset: 0xc) PWMC Status Register -------- */ +/* - -------- PWMC_IER : (PWMC Offset: 0x10) PWMC Interrupt Enable Register -------- */ +/* - -------- PWMC_IDR : (PWMC Offset: 0x14) PWMC Interrupt Disable Register -------- */ +/* - -------- PWMC_IMR : (PWMC Offset: 0x18) PWMC Interrupt Mask Register -------- */ +/* - -------- PWMC_ISR : (PWMC Offset: 0x1c) PWMC Interrupt Status Register -------- */ -// - ***************************************************************************** -// - REGISTER ADDRESS DEFINITION FOR AT91SAM7X256 -// - ***************************************************************************** -// - ========== Register definition for SYS peripheral ========== -// - ========== Register definition for AIC peripheral ========== -AT91C_AIC_IVR EQU (0xFFFFF100) ;- (AIC) IRQ Vector Register -AT91C_AIC_SMR EQU (0xFFFFF000) ;- (AIC) Source Mode Register -AT91C_AIC_FVR EQU (0xFFFFF104) ;- (AIC) FIQ Vector Register -AT91C_AIC_DCR EQU (0xFFFFF138) ;- (AIC) Debug Control Register (Protect) -AT91C_AIC_EOICR EQU (0xFFFFF130) ;- (AIC) End of Interrupt Command Register -AT91C_AIC_SVR EQU (0xFFFFF080) ;- (AIC) Source Vector Register -AT91C_AIC_FFSR EQU (0xFFFFF148) ;- (AIC) Fast Forcing Status Register -AT91C_AIC_ICCR EQU (0xFFFFF128) ;- (AIC) Interrupt Clear Command Register -AT91C_AIC_ISR EQU (0xFFFFF108) ;- (AIC) Interrupt Status Register -AT91C_AIC_IMR EQU (0xFFFFF110) ;- (AIC) Interrupt Mask Register -AT91C_AIC_IPR EQU (0xFFFFF10C) ;- (AIC) Interrupt Pending Register -AT91C_AIC_FFER EQU (0xFFFFF140) ;- (AIC) Fast Forcing Enable Register -AT91C_AIC_IECR EQU (0xFFFFF120) ;- (AIC) Interrupt Enable Command Register -AT91C_AIC_ISCR EQU (0xFFFFF12C) ;- (AIC) Interrupt Set Command Register -AT91C_AIC_FFDR EQU (0xFFFFF144) ;- (AIC) Fast Forcing Disable Register -AT91C_AIC_CISR EQU (0xFFFFF114) ;- (AIC) Core Interrupt Status Register -AT91C_AIC_IDCR EQU (0xFFFFF124) ;- (AIC) Interrupt Disable Command Register -AT91C_AIC_SPU EQU (0xFFFFF134) ;- (AIC) Spurious Vector Register -// - ========== Register definition for PDC_DBGU peripheral ========== -AT91C_DBGU_TCR EQU (0xFFFFF30C) ;- (PDC_DBGU) Transmit Counter Register -AT91C_DBGU_RNPR EQU (0xFFFFF310) ;- (PDC_DBGU) Receive Next Pointer Register -AT91C_DBGU_TNPR EQU (0xFFFFF318) ;- (PDC_DBGU) Transmit Next Pointer Register -AT91C_DBGU_TPR EQU (0xFFFFF308) ;- (PDC_DBGU) Transmit Pointer Register -AT91C_DBGU_RPR EQU (0xFFFFF300) ;- (PDC_DBGU) Receive Pointer Register -AT91C_DBGU_RCR EQU (0xFFFFF304) ;- (PDC_DBGU) Receive Counter Register -AT91C_DBGU_RNCR EQU (0xFFFFF314) ;- (PDC_DBGU) Receive Next Counter Register -AT91C_DBGU_PTCR EQU (0xFFFFF320) ;- (PDC_DBGU) PDC Transfer Control Register -AT91C_DBGU_PTSR EQU (0xFFFFF324) ;- (PDC_DBGU) PDC Transfer Status Register -AT91C_DBGU_TNCR EQU (0xFFFFF31C) ;- (PDC_DBGU) Transmit Next Counter Register -// - ========== Register definition for DBGU peripheral ========== -AT91C_DBGU_EXID EQU (0xFFFFF244) ;- (DBGU) Chip ID Extension Register -AT91C_DBGU_BRGR EQU (0xFFFFF220) ;- (DBGU) Baud Rate Generator Register -AT91C_DBGU_IDR EQU (0xFFFFF20C) ;- (DBGU) Interrupt Disable Register -AT91C_DBGU_CSR EQU (0xFFFFF214) ;- (DBGU) Channel Status Register -AT91C_DBGU_CIDR EQU (0xFFFFF240) ;- (DBGU) Chip ID Register -AT91C_DBGU_MR EQU (0xFFFFF204) ;- (DBGU) Mode Register -AT91C_DBGU_IMR EQU (0xFFFFF210) ;- (DBGU) Interrupt Mask Register -AT91C_DBGU_CR EQU (0xFFFFF200) ;- (DBGU) Control Register -AT91C_DBGU_FNTR EQU (0xFFFFF248) ;- (DBGU) Force NTRST Register -AT91C_DBGU_THR EQU (0xFFFFF21C) ;- (DBGU) Transmitter Holding Register -AT91C_DBGU_RHR EQU (0xFFFFF218) ;- (DBGU) Receiver Holding Register -AT91C_DBGU_IER EQU (0xFFFFF208) ;- (DBGU) Interrupt Enable Register -// - ========== Register definition for PIOA peripheral ========== -AT91C_PIOA_ODR EQU (0xFFFFF414) ;- (PIOA) Output Disable Registerr -AT91C_PIOA_SODR EQU (0xFFFFF430) ;- (PIOA) Set Output Data Register -AT91C_PIOA_ISR EQU (0xFFFFF44C) ;- (PIOA) Interrupt Status Register -AT91C_PIOA_ABSR EQU (0xFFFFF478) ;- (PIOA) AB Select Status Register -AT91C_PIOA_IER EQU (0xFFFFF440) ;- (PIOA) Interrupt Enable Register -AT91C_PIOA_PPUDR EQU (0xFFFFF460) ;- (PIOA) Pull-up Disable Register -AT91C_PIOA_IMR EQU (0xFFFFF448) ;- (PIOA) Interrupt Mask Register -AT91C_PIOA_PER EQU (0xFFFFF400) ;- (PIOA) PIO Enable Register -AT91C_PIOA_IFDR EQU (0xFFFFF424) ;- (PIOA) Input Filter Disable Register -AT91C_PIOA_OWDR EQU (0xFFFFF4A4) ;- (PIOA) Output Write Disable Register -AT91C_PIOA_MDSR EQU (0xFFFFF458) ;- (PIOA) Multi-driver Status Register -AT91C_PIOA_IDR EQU (0xFFFFF444) ;- (PIOA) Interrupt Disable Register -AT91C_PIOA_ODSR EQU (0xFFFFF438) ;- (PIOA) Output Data Status Register -AT91C_PIOA_PPUSR EQU (0xFFFFF468) ;- (PIOA) Pull-up Status Register -AT91C_PIOA_OWSR EQU (0xFFFFF4A8) ;- (PIOA) Output Write Status Register -AT91C_PIOA_BSR EQU (0xFFFFF474) ;- (PIOA) Select B Register -AT91C_PIOA_OWER EQU (0xFFFFF4A0) ;- (PIOA) Output Write Enable Register -AT91C_PIOA_IFER EQU (0xFFFFF420) ;- (PIOA) Input Filter Enable Register -AT91C_PIOA_PDSR EQU (0xFFFFF43C) ;- (PIOA) Pin Data Status Register -AT91C_PIOA_PPUER EQU (0xFFFFF464) ;- (PIOA) Pull-up Enable Register -AT91C_PIOA_OSR EQU (0xFFFFF418) ;- (PIOA) Output Status Register -AT91C_PIOA_ASR EQU (0xFFFFF470) ;- (PIOA) Select A Register -AT91C_PIOA_MDDR EQU (0xFFFFF454) ;- (PIOA) Multi-driver Disable Register -AT91C_PIOA_CODR EQU (0xFFFFF434) ;- (PIOA) Clear Output Data Register -AT91C_PIOA_MDER EQU (0xFFFFF450) ;- (PIOA) Multi-driver Enable Register -AT91C_PIOA_PDR EQU (0xFFFFF404) ;- (PIOA) PIO Disable Register -AT91C_PIOA_IFSR EQU (0xFFFFF428) ;- (PIOA) Input Filter Status Register -AT91C_PIOA_OER EQU (0xFFFFF410) ;- (PIOA) Output Enable Register -AT91C_PIOA_PSR EQU (0xFFFFF408) ;- (PIOA) PIO Status Register -// - ========== Register definition for PIOB peripheral ========== -AT91C_PIOB_OWDR EQU (0xFFFFF6A4) ;- (PIOB) Output Write Disable Register -AT91C_PIOB_MDER EQU (0xFFFFF650) ;- (PIOB) Multi-driver Enable Register -AT91C_PIOB_PPUSR EQU (0xFFFFF668) ;- (PIOB) Pull-up Status Register -AT91C_PIOB_IMR EQU (0xFFFFF648) ;- (PIOB) Interrupt Mask Register -AT91C_PIOB_ASR EQU (0xFFFFF670) ;- (PIOB) Select A Register -AT91C_PIOB_PPUDR EQU (0xFFFFF660) ;- (PIOB) Pull-up Disable Register -AT91C_PIOB_PSR EQU (0xFFFFF608) ;- (PIOB) PIO Status Register -AT91C_PIOB_IER EQU (0xFFFFF640) ;- (PIOB) Interrupt Enable Register -AT91C_PIOB_CODR EQU (0xFFFFF634) ;- (PIOB) Clear Output Data Register -AT91C_PIOB_OWER EQU (0xFFFFF6A0) ;- (PIOB) Output Write Enable Register -AT91C_PIOB_ABSR EQU (0xFFFFF678) ;- (PIOB) AB Select Status Register -AT91C_PIOB_IFDR EQU (0xFFFFF624) ;- (PIOB) Input Filter Disable Register -AT91C_PIOB_PDSR EQU (0xFFFFF63C) ;- (PIOB) Pin Data Status Register -AT91C_PIOB_IDR EQU (0xFFFFF644) ;- (PIOB) Interrupt Disable Register -AT91C_PIOB_OWSR EQU (0xFFFFF6A8) ;- (PIOB) Output Write Status Register -AT91C_PIOB_PDR EQU (0xFFFFF604) ;- (PIOB) PIO Disable Register -AT91C_PIOB_ODR EQU (0xFFFFF614) ;- (PIOB) Output Disable Registerr -AT91C_PIOB_IFSR EQU (0xFFFFF628) ;- (PIOB) Input Filter Status Register -AT91C_PIOB_PPUER EQU (0xFFFFF664) ;- (PIOB) Pull-up Enable Register -AT91C_PIOB_SODR EQU (0xFFFFF630) ;- (PIOB) Set Output Data Register -AT91C_PIOB_ISR EQU (0xFFFFF64C) ;- (PIOB) Interrupt Status Register -AT91C_PIOB_ODSR EQU (0xFFFFF638) ;- (PIOB) Output Data Status Register -AT91C_PIOB_OSR EQU (0xFFFFF618) ;- (PIOB) Output Status Register -AT91C_PIOB_MDSR EQU (0xFFFFF658) ;- (PIOB) Multi-driver Status Register -AT91C_PIOB_IFER EQU (0xFFFFF620) ;- (PIOB) Input Filter Enable Register -AT91C_PIOB_BSR EQU (0xFFFFF674) ;- (PIOB) Select B Register -AT91C_PIOB_MDDR EQU (0xFFFFF654) ;- (PIOB) Multi-driver Disable Register -AT91C_PIOB_OER EQU (0xFFFFF610) ;- (PIOB) Output Enable Register -AT91C_PIOB_PER EQU (0xFFFFF600) ;- (PIOB) PIO Enable Register -// - ========== Register definition for CKGR peripheral ========== -AT91C_CKGR_MOR EQU (0xFFFFFC20) ;- (CKGR) Main Oscillator Register -AT91C_CKGR_PLLR EQU (0xFFFFFC2C) ;- (CKGR) PLL Register -AT91C_CKGR_MCFR EQU (0xFFFFFC24) ;- (CKGR) Main Clock Frequency Register -// - ========== Register definition for PMC peripheral ========== -AT91C_PMC_IDR EQU (0xFFFFFC64) ;- (PMC) Interrupt Disable Register -AT91C_PMC_MOR EQU (0xFFFFFC20) ;- (PMC) Main Oscillator Register -AT91C_PMC_PLLR EQU (0xFFFFFC2C) ;- (PMC) PLL Register -AT91C_PMC_PCER EQU (0xFFFFFC10) ;- (PMC) Peripheral Clock Enable Register -AT91C_PMC_PCKR EQU (0xFFFFFC40) ;- (PMC) Programmable Clock Register -AT91C_PMC_MCKR EQU (0xFFFFFC30) ;- (PMC) Master Clock Register -AT91C_PMC_SCDR EQU (0xFFFFFC04) ;- (PMC) System Clock Disable Register -AT91C_PMC_PCDR EQU (0xFFFFFC14) ;- (PMC) Peripheral Clock Disable Register -AT91C_PMC_SCSR EQU (0xFFFFFC08) ;- (PMC) System Clock Status Register -AT91C_PMC_PCSR EQU (0xFFFFFC18) ;- (PMC) Peripheral Clock Status Register -AT91C_PMC_MCFR EQU (0xFFFFFC24) ;- (PMC) Main Clock Frequency Register -AT91C_PMC_SCER EQU (0xFFFFFC00) ;- (PMC) System Clock Enable Register -AT91C_PMC_IMR EQU (0xFFFFFC6C) ;- (PMC) Interrupt Mask Register -AT91C_PMC_IER EQU (0xFFFFFC60) ;- (PMC) Interrupt Enable Register -AT91C_PMC_SR EQU (0xFFFFFC68) ;- (PMC) Status Register -// - ========== Register definition for RSTC peripheral ========== -AT91C_RSTC_RCR EQU (0xFFFFFD00) ;- (RSTC) Reset Control Register -AT91C_RSTC_RMR EQU (0xFFFFFD08) ;- (RSTC) Reset Mode Register -AT91C_RSTC_RSR EQU (0xFFFFFD04) ;- (RSTC) Reset Status Register -// - ========== Register definition for RTTC peripheral ========== -AT91C_RTTC_RTSR EQU (0xFFFFFD2C) ;- (RTTC) Real-time Status Register -AT91C_RTTC_RTMR EQU (0xFFFFFD20) ;- (RTTC) Real-time Mode Register -AT91C_RTTC_RTVR EQU (0xFFFFFD28) ;- (RTTC) Real-time Value Register -AT91C_RTTC_RTAR EQU (0xFFFFFD24) ;- (RTTC) Real-time Alarm Register -// - ========== Register definition for PITC peripheral ========== -AT91C_PITC_PIVR EQU (0xFFFFFD38) ;- (PITC) Period Interval Value Register -AT91C_PITC_PISR EQU (0xFFFFFD34) ;- (PITC) Period Interval Status Register -AT91C_PITC_PIIR EQU (0xFFFFFD3C) ;- (PITC) Period Interval Image Register -AT91C_PITC_PIMR EQU (0xFFFFFD30) ;- (PITC) Period Interval Mode Register -// - ========== Register definition for WDTC peripheral ========== -AT91C_WDTC_WDCR EQU (0xFFFFFD40) ;- (WDTC) Watchdog Control Register -AT91C_WDTC_WDSR EQU (0xFFFFFD48) ;- (WDTC) Watchdog Status Register -AT91C_WDTC_WDMR EQU (0xFFFFFD44) ;- (WDTC) Watchdog Mode Register -// - ========== Register definition for VREG peripheral ========== -AT91C_VREG_MR EQU (0xFFFFFD60) ;- (VREG) Voltage Regulator Mode Register -// - ========== Register definition for MC peripheral ========== -AT91C_MC_ASR EQU (0xFFFFFF04) ;- (MC) MC Abort Status Register -AT91C_MC_RCR EQU (0xFFFFFF00) ;- (MC) MC Remap Control Register -AT91C_MC_FCR EQU (0xFFFFFF64) ;- (MC) MC Flash Command Register -AT91C_MC_AASR EQU (0xFFFFFF08) ;- (MC) MC Abort Address Status Register -AT91C_MC_FSR EQU (0xFFFFFF68) ;- (MC) MC Flash Status Register -AT91C_MC_FMR EQU (0xFFFFFF60) ;- (MC) MC Flash Mode Register -// - ========== Register definition for PDC_SPI1 peripheral ========== -AT91C_SPI1_PTCR EQU (0xFFFE4120) ;- (PDC_SPI1) PDC Transfer Control Register -AT91C_SPI1_RPR EQU (0xFFFE4100) ;- (PDC_SPI1) Receive Pointer Register -AT91C_SPI1_TNCR EQU (0xFFFE411C) ;- (PDC_SPI1) Transmit Next Counter Register -AT91C_SPI1_TPR EQU (0xFFFE4108) ;- (PDC_SPI1) Transmit Pointer Register -AT91C_SPI1_TNPR EQU (0xFFFE4118) ;- (PDC_SPI1) Transmit Next Pointer Register -AT91C_SPI1_TCR EQU (0xFFFE410C) ;- (PDC_SPI1) Transmit Counter Register -AT91C_SPI1_RCR EQU (0xFFFE4104) ;- (PDC_SPI1) Receive Counter Register -AT91C_SPI1_RNPR EQU (0xFFFE4110) ;- (PDC_SPI1) Receive Next Pointer Register -AT91C_SPI1_RNCR EQU (0xFFFE4114) ;- (PDC_SPI1) Receive Next Counter Register -AT91C_SPI1_PTSR EQU (0xFFFE4124) ;- (PDC_SPI1) PDC Transfer Status Register -// - ========== Register definition for SPI1 peripheral ========== -AT91C_SPI1_IMR EQU (0xFFFE401C) ;- (SPI1) Interrupt Mask Register -AT91C_SPI1_IER EQU (0xFFFE4014) ;- (SPI1) Interrupt Enable Register -AT91C_SPI1_MR EQU (0xFFFE4004) ;- (SPI1) Mode Register -AT91C_SPI1_RDR EQU (0xFFFE4008) ;- (SPI1) Receive Data Register -AT91C_SPI1_IDR EQU (0xFFFE4018) ;- (SPI1) Interrupt Disable Register -AT91C_SPI1_SR EQU (0xFFFE4010) ;- (SPI1) Status Register -AT91C_SPI1_TDR EQU (0xFFFE400C) ;- (SPI1) Transmit Data Register -AT91C_SPI1_CR EQU (0xFFFE4000) ;- (SPI1) Control Register -AT91C_SPI1_CSR EQU (0xFFFE4030) ;- (SPI1) Chip Select Register -// - ========== Register definition for PDC_SPI0 peripheral ========== -AT91C_SPI0_PTCR EQU (0xFFFE0120) ;- (PDC_SPI0) PDC Transfer Control Register -AT91C_SPI0_TPR EQU (0xFFFE0108) ;- (PDC_SPI0) Transmit Pointer Register -AT91C_SPI0_TCR EQU (0xFFFE010C) ;- (PDC_SPI0) Transmit Counter Register -AT91C_SPI0_RCR EQU (0xFFFE0104) ;- (PDC_SPI0) Receive Counter Register -AT91C_SPI0_PTSR EQU (0xFFFE0124) ;- (PDC_SPI0) PDC Transfer Status Register -AT91C_SPI0_RNPR EQU (0xFFFE0110) ;- (PDC_SPI0) Receive Next Pointer Register -AT91C_SPI0_RPR EQU (0xFFFE0100) ;- (PDC_SPI0) Receive Pointer Register -AT91C_SPI0_TNCR EQU (0xFFFE011C) ;- (PDC_SPI0) Transmit Next Counter Register -AT91C_SPI0_RNCR EQU (0xFFFE0114) ;- (PDC_SPI0) Receive Next Counter Register -AT91C_SPI0_TNPR EQU (0xFFFE0118) ;- (PDC_SPI0) Transmit Next Pointer Register -// - ========== Register definition for SPI0 peripheral ========== -AT91C_SPI0_IER EQU (0xFFFE0014) ;- (SPI0) Interrupt Enable Register -AT91C_SPI0_SR EQU (0xFFFE0010) ;- (SPI0) Status Register -AT91C_SPI0_IDR EQU (0xFFFE0018) ;- (SPI0) Interrupt Disable Register -AT91C_SPI0_CR EQU (0xFFFE0000) ;- (SPI0) Control Register -AT91C_SPI0_MR EQU (0xFFFE0004) ;- (SPI0) Mode Register -AT91C_SPI0_IMR EQU (0xFFFE001C) ;- (SPI0) Interrupt Mask Register -AT91C_SPI0_TDR EQU (0xFFFE000C) ;- (SPI0) Transmit Data Register -AT91C_SPI0_RDR EQU (0xFFFE0008) ;- (SPI0) Receive Data Register -AT91C_SPI0_CSR EQU (0xFFFE0030) ;- (SPI0) Chip Select Register -// - ========== Register definition for PDC_US1 peripheral ========== -AT91C_US1_RNCR EQU (0xFFFC4114) ;- (PDC_US1) Receive Next Counter Register -AT91C_US1_PTCR EQU (0xFFFC4120) ;- (PDC_US1) PDC Transfer Control Register -AT91C_US1_TCR EQU (0xFFFC410C) ;- (PDC_US1) Transmit Counter Register -AT91C_US1_PTSR EQU (0xFFFC4124) ;- (PDC_US1) PDC Transfer Status Register -AT91C_US1_TNPR EQU (0xFFFC4118) ;- (PDC_US1) Transmit Next Pointer Register -AT91C_US1_RCR EQU (0xFFFC4104) ;- (PDC_US1) Receive Counter Register -AT91C_US1_RNPR EQU (0xFFFC4110) ;- (PDC_US1) Receive Next Pointer Register -AT91C_US1_RPR EQU (0xFFFC4100) ;- (PDC_US1) Receive Pointer Register -AT91C_US1_TNCR EQU (0xFFFC411C) ;- (PDC_US1) Transmit Next Counter Register -AT91C_US1_TPR EQU (0xFFFC4108) ;- (PDC_US1) Transmit Pointer Register -// - ========== Register definition for US1 peripheral ========== -AT91C_US1_IF EQU (0xFFFC404C) ;- (US1) IRDA_FILTER Register -AT91C_US1_NER EQU (0xFFFC4044) ;- (US1) Nb Errors Register -AT91C_US1_RTOR EQU (0xFFFC4024) ;- (US1) Receiver Time-out Register -AT91C_US1_CSR EQU (0xFFFC4014) ;- (US1) Channel Status Register -AT91C_US1_IDR EQU (0xFFFC400C) ;- (US1) Interrupt Disable Register -AT91C_US1_IER EQU (0xFFFC4008) ;- (US1) Interrupt Enable Register -AT91C_US1_THR EQU (0xFFFC401C) ;- (US1) Transmitter Holding Register -AT91C_US1_TTGR EQU (0xFFFC4028) ;- (US1) Transmitter Time-guard Register -AT91C_US1_RHR EQU (0xFFFC4018) ;- (US1) Receiver Holding Register -AT91C_US1_BRGR EQU (0xFFFC4020) ;- (US1) Baud Rate Generator Register -AT91C_US1_IMR EQU (0xFFFC4010) ;- (US1) Interrupt Mask Register -AT91C_US1_FIDI EQU (0xFFFC4040) ;- (US1) FI_DI_Ratio Register -AT91C_US1_CR EQU (0xFFFC4000) ;- (US1) Control Register -AT91C_US1_MR EQU (0xFFFC4004) ;- (US1) Mode Register -// - ========== Register definition for PDC_US0 peripheral ========== -AT91C_US0_TNPR EQU (0xFFFC0118) ;- (PDC_US0) Transmit Next Pointer Register -AT91C_US0_RNPR EQU (0xFFFC0110) ;- (PDC_US0) Receive Next Pointer Register -AT91C_US0_TCR EQU (0xFFFC010C) ;- (PDC_US0) Transmit Counter Register -AT91C_US0_PTCR EQU (0xFFFC0120) ;- (PDC_US0) PDC Transfer Control Register -AT91C_US0_PTSR EQU (0xFFFC0124) ;- (PDC_US0) PDC Transfer Status Register -AT91C_US0_TNCR EQU (0xFFFC011C) ;- (PDC_US0) Transmit Next Counter Register -AT91C_US0_TPR EQU (0xFFFC0108) ;- (PDC_US0) Transmit Pointer Register -AT91C_US0_RCR EQU (0xFFFC0104) ;- (PDC_US0) Receive Counter Register -AT91C_US0_RPR EQU (0xFFFC0100) ;- (PDC_US0) Receive Pointer Register -AT91C_US0_RNCR EQU (0xFFFC0114) ;- (PDC_US0) Receive Next Counter Register -// - ========== Register definition for US0 peripheral ========== -AT91C_US0_BRGR EQU (0xFFFC0020) ;- (US0) Baud Rate Generator Register -AT91C_US0_NER EQU (0xFFFC0044) ;- (US0) Nb Errors Register -AT91C_US0_CR EQU (0xFFFC0000) ;- (US0) Control Register -AT91C_US0_IMR EQU (0xFFFC0010) ;- (US0) Interrupt Mask Register -AT91C_US0_FIDI EQU (0xFFFC0040) ;- (US0) FI_DI_Ratio Register -AT91C_US0_TTGR EQU (0xFFFC0028) ;- (US0) Transmitter Time-guard Register -AT91C_US0_MR EQU (0xFFFC0004) ;- (US0) Mode Register -AT91C_US0_RTOR EQU (0xFFFC0024) ;- (US0) Receiver Time-out Register -AT91C_US0_CSR EQU (0xFFFC0014) ;- (US0) Channel Status Register -AT91C_US0_RHR EQU (0xFFFC0018) ;- (US0) Receiver Holding Register -AT91C_US0_IDR EQU (0xFFFC000C) ;- (US0) Interrupt Disable Register -AT91C_US0_THR EQU (0xFFFC001C) ;- (US0) Transmitter Holding Register -AT91C_US0_IF EQU (0xFFFC004C) ;- (US0) IRDA_FILTER Register -AT91C_US0_IER EQU (0xFFFC0008) ;- (US0) Interrupt Enable Register -// - ========== Register definition for PDC_SSC peripheral ========== -AT91C_SSC_TNCR EQU (0xFFFD411C) ;- (PDC_SSC) Transmit Next Counter Register -AT91C_SSC_RPR EQU (0xFFFD4100) ;- (PDC_SSC) Receive Pointer Register -AT91C_SSC_RNCR EQU (0xFFFD4114) ;- (PDC_SSC) Receive Next Counter Register -AT91C_SSC_TPR EQU (0xFFFD4108) ;- (PDC_SSC) Transmit Pointer Register -AT91C_SSC_PTCR EQU (0xFFFD4120) ;- (PDC_SSC) PDC Transfer Control Register -AT91C_SSC_TCR EQU (0xFFFD410C) ;- (PDC_SSC) Transmit Counter Register -AT91C_SSC_RCR EQU (0xFFFD4104) ;- (PDC_SSC) Receive Counter Register -AT91C_SSC_RNPR EQU (0xFFFD4110) ;- (PDC_SSC) Receive Next Pointer Register -AT91C_SSC_TNPR EQU (0xFFFD4118) ;- (PDC_SSC) Transmit Next Pointer Register -AT91C_SSC_PTSR EQU (0xFFFD4124) ;- (PDC_SSC) PDC Transfer Status Register -// - ========== Register definition for SSC peripheral ========== -AT91C_SSC_RHR EQU (0xFFFD4020) ;- (SSC) Receive Holding Register -AT91C_SSC_RSHR EQU (0xFFFD4030) ;- (SSC) Receive Sync Holding Register -AT91C_SSC_TFMR EQU (0xFFFD401C) ;- (SSC) Transmit Frame Mode Register -AT91C_SSC_IDR EQU (0xFFFD4048) ;- (SSC) Interrupt Disable Register -AT91C_SSC_THR EQU (0xFFFD4024) ;- (SSC) Transmit Holding Register -AT91C_SSC_RCMR EQU (0xFFFD4010) ;- (SSC) Receive Clock ModeRegister -AT91C_SSC_IER EQU (0xFFFD4044) ;- (SSC) Interrupt Enable Register -AT91C_SSC_TSHR EQU (0xFFFD4034) ;- (SSC) Transmit Sync Holding Register -AT91C_SSC_SR EQU (0xFFFD4040) ;- (SSC) Status Register -AT91C_SSC_CMR EQU (0xFFFD4004) ;- (SSC) Clock Mode Register -AT91C_SSC_TCMR EQU (0xFFFD4018) ;- (SSC) Transmit Clock Mode Register -AT91C_SSC_CR EQU (0xFFFD4000) ;- (SSC) Control Register -AT91C_SSC_IMR EQU (0xFFFD404C) ;- (SSC) Interrupt Mask Register -AT91C_SSC_RFMR EQU (0xFFFD4014) ;- (SSC) Receive Frame Mode Register -// - ========== Register definition for TWI peripheral ========== -AT91C_TWI_IER EQU (0xFFFB8024) ;- (TWI) Interrupt Enable Register -AT91C_TWI_CR EQU (0xFFFB8000) ;- (TWI) Control Register -AT91C_TWI_SR EQU (0xFFFB8020) ;- (TWI) Status Register -AT91C_TWI_IMR EQU (0xFFFB802C) ;- (TWI) Interrupt Mask Register -AT91C_TWI_THR EQU (0xFFFB8034) ;- (TWI) Transmit Holding Register -AT91C_TWI_IDR EQU (0xFFFB8028) ;- (TWI) Interrupt Disable Register -AT91C_TWI_IADR EQU (0xFFFB800C) ;- (TWI) Internal Address Register -AT91C_TWI_MMR EQU (0xFFFB8004) ;- (TWI) Master Mode Register -AT91C_TWI_CWGR EQU (0xFFFB8010) ;- (TWI) Clock Waveform Generator Register -AT91C_TWI_RHR EQU (0xFFFB8030) ;- (TWI) Receive Holding Register -// - ========== Register definition for PWMC_CH3 peripheral ========== -AT91C_PWMC_CH3_CUPDR EQU (0xFFFCC270) ;- (PWMC_CH3) Channel Update Register -AT91C_PWMC_CH3_Reserved EQU (0xFFFCC274) ;- (PWMC_CH3) Reserved -AT91C_PWMC_CH3_CPRDR EQU (0xFFFCC268) ;- (PWMC_CH3) Channel Period Register -AT91C_PWMC_CH3_CDTYR EQU (0xFFFCC264) ;- (PWMC_CH3) Channel Duty Cycle Register -AT91C_PWMC_CH3_CCNTR EQU (0xFFFCC26C) ;- (PWMC_CH3) Channel Counter Register -AT91C_PWMC_CH3_CMR EQU (0xFFFCC260) ;- (PWMC_CH3) Channel Mode Register -// - ========== Register definition for PWMC_CH2 peripheral ========== -AT91C_PWMC_CH2_Reserved EQU (0xFFFCC254) ;- (PWMC_CH2) Reserved -AT91C_PWMC_CH2_CMR EQU (0xFFFCC240) ;- (PWMC_CH2) Channel Mode Register -AT91C_PWMC_CH2_CCNTR EQU (0xFFFCC24C) ;- (PWMC_CH2) Channel Counter Register -AT91C_PWMC_CH2_CPRDR EQU (0xFFFCC248) ;- (PWMC_CH2) Channel Period Register -AT91C_PWMC_CH2_CUPDR EQU (0xFFFCC250) ;- (PWMC_CH2) Channel Update Register -AT91C_PWMC_CH2_CDTYR EQU (0xFFFCC244) ;- (PWMC_CH2) Channel Duty Cycle Register -// - ========== Register definition for PWMC_CH1 peripheral ========== -AT91C_PWMC_CH1_Reserved EQU (0xFFFCC234) ;- (PWMC_CH1) Reserved -AT91C_PWMC_CH1_CUPDR EQU (0xFFFCC230) ;- (PWMC_CH1) Channel Update Register -AT91C_PWMC_CH1_CPRDR EQU (0xFFFCC228) ;- (PWMC_CH1) Channel Period Register -AT91C_PWMC_CH1_CCNTR EQU (0xFFFCC22C) ;- (PWMC_CH1) Channel Counter Register -AT91C_PWMC_CH1_CDTYR EQU (0xFFFCC224) ;- (PWMC_CH1) Channel Duty Cycle Register -AT91C_PWMC_CH1_CMR EQU (0xFFFCC220) ;- (PWMC_CH1) Channel Mode Register -// - ========== Register definition for PWMC_CH0 peripheral ========== -AT91C_PWMC_CH0_Reserved EQU (0xFFFCC214) ;- (PWMC_CH0) Reserved -AT91C_PWMC_CH0_CPRDR EQU (0xFFFCC208) ;- (PWMC_CH0) Channel Period Register -AT91C_PWMC_CH0_CDTYR EQU (0xFFFCC204) ;- (PWMC_CH0) Channel Duty Cycle Register -AT91C_PWMC_CH0_CMR EQU (0xFFFCC200) ;- (PWMC_CH0) Channel Mode Register -AT91C_PWMC_CH0_CUPDR EQU (0xFFFCC210) ;- (PWMC_CH0) Channel Update Register -AT91C_PWMC_CH0_CCNTR EQU (0xFFFCC20C) ;- (PWMC_CH0) Channel Counter Register -// - ========== Register definition for PWMC peripheral ========== -AT91C_PWMC_IDR EQU (0xFFFCC014) ;- (PWMC) PWMC Interrupt Disable Register -AT91C_PWMC_DIS EQU (0xFFFCC008) ;- (PWMC) PWMC Disable Register -AT91C_PWMC_IER EQU (0xFFFCC010) ;- (PWMC) PWMC Interrupt Enable Register -AT91C_PWMC_VR EQU (0xFFFCC0FC) ;- (PWMC) PWMC Version Register -AT91C_PWMC_ISR EQU (0xFFFCC01C) ;- (PWMC) PWMC Interrupt Status Register -AT91C_PWMC_SR EQU (0xFFFCC00C) ;- (PWMC) PWMC Status Register -AT91C_PWMC_IMR EQU (0xFFFCC018) ;- (PWMC) PWMC Interrupt Mask Register -AT91C_PWMC_MR EQU (0xFFFCC000) ;- (PWMC) PWMC Mode Register -AT91C_PWMC_ENA EQU (0xFFFCC004) ;- (PWMC) PWMC Enable Register -// - ========== Register definition for UDP peripheral ========== -AT91C_UDP_IMR EQU (0xFFFB0018) ;- (UDP) Interrupt Mask Register -AT91C_UDP_FADDR EQU (0xFFFB0008) ;- (UDP) Function Address Register -AT91C_UDP_NUM EQU (0xFFFB0000) ;- (UDP) Frame Number Register -AT91C_UDP_FDR EQU (0xFFFB0050) ;- (UDP) Endpoint FIFO Data Register -AT91C_UDP_ISR EQU (0xFFFB001C) ;- (UDP) Interrupt Status Register -AT91C_UDP_CSR EQU (0xFFFB0030) ;- (UDP) Endpoint Control and Status Register -AT91C_UDP_IDR EQU (0xFFFB0014) ;- (UDP) Interrupt Disable Register -AT91C_UDP_ICR EQU (0xFFFB0020) ;- (UDP) Interrupt Clear Register -AT91C_UDP_RSTEP EQU (0xFFFB0028) ;- (UDP) Reset Endpoint Register -AT91C_UDP_TXVC EQU (0xFFFB0074) ;- (UDP) Transceiver Control Register -AT91C_UDP_GLBSTATE EQU (0xFFFB0004) ;- (UDP) Global State Register -AT91C_UDP_IER EQU (0xFFFB0010) ;- (UDP) Interrupt Enable Register -// - ========== Register definition for TC0 peripheral ========== -AT91C_TC0_SR EQU (0xFFFA0020) ;- (TC0) Status Register -AT91C_TC0_RC EQU (0xFFFA001C) ;- (TC0) Register C -AT91C_TC0_RB EQU (0xFFFA0018) ;- (TC0) Register B -AT91C_TC0_CCR EQU (0xFFFA0000) ;- (TC0) Channel Control Register -AT91C_TC0_CMR EQU (0xFFFA0004) ;- (TC0) Channel Mode Register (Capture Mode / Waveform Mode) -AT91C_TC0_IER EQU (0xFFFA0024) ;- (TC0) Interrupt Enable Register -AT91C_TC0_RA EQU (0xFFFA0014) ;- (TC0) Register A -AT91C_TC0_IDR EQU (0xFFFA0028) ;- (TC0) Interrupt Disable Register -AT91C_TC0_CV EQU (0xFFFA0010) ;- (TC0) Counter Value -AT91C_TC0_IMR EQU (0xFFFA002C) ;- (TC0) Interrupt Mask Register -// - ========== Register definition for TC1 peripheral ========== -AT91C_TC1_RB EQU (0xFFFA0058) ;- (TC1) Register B -AT91C_TC1_CCR EQU (0xFFFA0040) ;- (TC1) Channel Control Register -AT91C_TC1_IER EQU (0xFFFA0064) ;- (TC1) Interrupt Enable Register -AT91C_TC1_IDR EQU (0xFFFA0068) ;- (TC1) Interrupt Disable Register -AT91C_TC1_SR EQU (0xFFFA0060) ;- (TC1) Status Register -AT91C_TC1_CMR EQU (0xFFFA0044) ;- (TC1) Channel Mode Register (Capture Mode / Waveform Mode) -AT91C_TC1_RA EQU (0xFFFA0054) ;- (TC1) Register A -AT91C_TC1_RC EQU (0xFFFA005C) ;- (TC1) Register C -AT91C_TC1_IMR EQU (0xFFFA006C) ;- (TC1) Interrupt Mask Register -AT91C_TC1_CV EQU (0xFFFA0050) ;- (TC1) Counter Value -// - ========== Register definition for TC2 peripheral ========== -AT91C_TC2_CMR EQU (0xFFFA0084) ;- (TC2) Channel Mode Register (Capture Mode / Waveform Mode) -AT91C_TC2_CCR EQU (0xFFFA0080) ;- (TC2) Channel Control Register -AT91C_TC2_CV EQU (0xFFFA0090) ;- (TC2) Counter Value -AT91C_TC2_RA EQU (0xFFFA0094) ;- (TC2) Register A -AT91C_TC2_RB EQU (0xFFFA0098) ;- (TC2) Register B -AT91C_TC2_IDR EQU (0xFFFA00A8) ;- (TC2) Interrupt Disable Register -AT91C_TC2_IMR EQU (0xFFFA00AC) ;- (TC2) Interrupt Mask Register -AT91C_TC2_RC EQU (0xFFFA009C) ;- (TC2) Register C -AT91C_TC2_IER EQU (0xFFFA00A4) ;- (TC2) Interrupt Enable Register -AT91C_TC2_SR EQU (0xFFFA00A0) ;- (TC2) Status Register -// - ========== Register definition for TCB peripheral ========== -AT91C_TCB_BMR EQU (0xFFFA00C4) ;- (TCB) TC Block Mode Register -AT91C_TCB_BCR EQU (0xFFFA00C0) ;- (TCB) TC Block Control Register -// - ========== Register definition for CAN_MB0 peripheral ========== -AT91C_CAN_MB0_MDL EQU (0xFFFD0214) ;- (CAN_MB0) MailBox Data Low Register -AT91C_CAN_MB0_MAM EQU (0xFFFD0204) ;- (CAN_MB0) MailBox Acceptance Mask Register -AT91C_CAN_MB0_MCR EQU (0xFFFD021C) ;- (CAN_MB0) MailBox Control Register -AT91C_CAN_MB0_MID EQU (0xFFFD0208) ;- (CAN_MB0) MailBox ID Register -AT91C_CAN_MB0_MSR EQU (0xFFFD0210) ;- (CAN_MB0) MailBox Status Register -AT91C_CAN_MB0_MFID EQU (0xFFFD020C) ;- (CAN_MB0) MailBox Family ID Register -AT91C_CAN_MB0_MDH EQU (0xFFFD0218) ;- (CAN_MB0) MailBox Data High Register -AT91C_CAN_MB0_MMR EQU (0xFFFD0200) ;- (CAN_MB0) MailBox Mode Register -// - ========== Register definition for CAN_MB1 peripheral ========== -AT91C_CAN_MB1_MDL EQU (0xFFFD0234) ;- (CAN_MB1) MailBox Data Low Register -AT91C_CAN_MB1_MID EQU (0xFFFD0228) ;- (CAN_MB1) MailBox ID Register -AT91C_CAN_MB1_MMR EQU (0xFFFD0220) ;- (CAN_MB1) MailBox Mode Register -AT91C_CAN_MB1_MSR EQU (0xFFFD0230) ;- (CAN_MB1) MailBox Status Register -AT91C_CAN_MB1_MAM EQU (0xFFFD0224) ;- (CAN_MB1) MailBox Acceptance Mask Register -AT91C_CAN_MB1_MDH EQU (0xFFFD0238) ;- (CAN_MB1) MailBox Data High Register -AT91C_CAN_MB1_MCR EQU (0xFFFD023C) ;- (CAN_MB1) MailBox Control Register -AT91C_CAN_MB1_MFID EQU (0xFFFD022C) ;- (CAN_MB1) MailBox Family ID Register -// - ========== Register definition for CAN_MB2 peripheral ========== -AT91C_CAN_MB2_MCR EQU (0xFFFD025C) ;- (CAN_MB2) MailBox Control Register -AT91C_CAN_MB2_MDH EQU (0xFFFD0258) ;- (CAN_MB2) MailBox Data High Register -AT91C_CAN_MB2_MID EQU (0xFFFD0248) ;- (CAN_MB2) MailBox ID Register -AT91C_CAN_MB2_MDL EQU (0xFFFD0254) ;- (CAN_MB2) MailBox Data Low Register -AT91C_CAN_MB2_MMR EQU (0xFFFD0240) ;- (CAN_MB2) MailBox Mode Register -AT91C_CAN_MB2_MAM EQU (0xFFFD0244) ;- (CAN_MB2) MailBox Acceptance Mask Register -AT91C_CAN_MB2_MFID EQU (0xFFFD024C) ;- (CAN_MB2) MailBox Family ID Register -AT91C_CAN_MB2_MSR EQU (0xFFFD0250) ;- (CAN_MB2) MailBox Status Register -// - ========== Register definition for CAN_MB3 peripheral ========== -AT91C_CAN_MB3_MFID EQU (0xFFFD026C) ;- (CAN_MB3) MailBox Family ID Register -AT91C_CAN_MB3_MAM EQU (0xFFFD0264) ;- (CAN_MB3) MailBox Acceptance Mask Register -AT91C_CAN_MB3_MID EQU (0xFFFD0268) ;- (CAN_MB3) MailBox ID Register -AT91C_CAN_MB3_MCR EQU (0xFFFD027C) ;- (CAN_MB3) MailBox Control Register -AT91C_CAN_MB3_MMR EQU (0xFFFD0260) ;- (CAN_MB3) MailBox Mode Register -AT91C_CAN_MB3_MSR EQU (0xFFFD0270) ;- (CAN_MB3) MailBox Status Register -AT91C_CAN_MB3_MDL EQU (0xFFFD0274) ;- (CAN_MB3) MailBox Data Low Register -AT91C_CAN_MB3_MDH EQU (0xFFFD0278) ;- (CAN_MB3) MailBox Data High Register -// - ========== Register definition for CAN_MB4 peripheral ========== -AT91C_CAN_MB4_MID EQU (0xFFFD0288) ;- (CAN_MB4) MailBox ID Register -AT91C_CAN_MB4_MMR EQU (0xFFFD0280) ;- (CAN_MB4) MailBox Mode Register -AT91C_CAN_MB4_MDH EQU (0xFFFD0298) ;- (CAN_MB4) MailBox Data High Register -AT91C_CAN_MB4_MFID EQU (0xFFFD028C) ;- (CAN_MB4) MailBox Family ID Register -AT91C_CAN_MB4_MSR EQU (0xFFFD0290) ;- (CAN_MB4) MailBox Status Register -AT91C_CAN_MB4_MCR EQU (0xFFFD029C) ;- (CAN_MB4) MailBox Control Register -AT91C_CAN_MB4_MDL EQU (0xFFFD0294) ;- (CAN_MB4) MailBox Data Low Register -AT91C_CAN_MB4_MAM EQU (0xFFFD0284) ;- (CAN_MB4) MailBox Acceptance Mask Register -// - ========== Register definition for CAN_MB5 peripheral ========== -AT91C_CAN_MB5_MSR EQU (0xFFFD02B0) ;- (CAN_MB5) MailBox Status Register -AT91C_CAN_MB5_MCR EQU (0xFFFD02BC) ;- (CAN_MB5) MailBox Control Register -AT91C_CAN_MB5_MFID EQU (0xFFFD02AC) ;- (CAN_MB5) MailBox Family ID Register -AT91C_CAN_MB5_MDH EQU (0xFFFD02B8) ;- (CAN_MB5) MailBox Data High Register -AT91C_CAN_MB5_MID EQU (0xFFFD02A8) ;- (CAN_MB5) MailBox ID Register -AT91C_CAN_MB5_MMR EQU (0xFFFD02A0) ;- (CAN_MB5) MailBox Mode Register -AT91C_CAN_MB5_MDL EQU (0xFFFD02B4) ;- (CAN_MB5) MailBox Data Low Register -AT91C_CAN_MB5_MAM EQU (0xFFFD02A4) ;- (CAN_MB5) MailBox Acceptance Mask Register -// - ========== Register definition for CAN_MB6 peripheral ========== -AT91C_CAN_MB6_MFID EQU (0xFFFD02CC) ;- (CAN_MB6) MailBox Family ID Register -AT91C_CAN_MB6_MID EQU (0xFFFD02C8) ;- (CAN_MB6) MailBox ID Register -AT91C_CAN_MB6_MAM EQU (0xFFFD02C4) ;- (CAN_MB6) MailBox Acceptance Mask Register -AT91C_CAN_MB6_MSR EQU (0xFFFD02D0) ;- (CAN_MB6) MailBox Status Register -AT91C_CAN_MB6_MDL EQU (0xFFFD02D4) ;- (CAN_MB6) MailBox Data Low Register -AT91C_CAN_MB6_MCR EQU (0xFFFD02DC) ;- (CAN_MB6) MailBox Control Register -AT91C_CAN_MB6_MDH EQU (0xFFFD02D8) ;- (CAN_MB6) MailBox Data High Register -AT91C_CAN_MB6_MMR EQU (0xFFFD02C0) ;- (CAN_MB6) MailBox Mode Register -// - ========== Register definition for CAN_MB7 peripheral ========== -AT91C_CAN_MB7_MCR EQU (0xFFFD02FC) ;- (CAN_MB7) MailBox Control Register -AT91C_CAN_MB7_MDH EQU (0xFFFD02F8) ;- (CAN_MB7) MailBox Data High Register -AT91C_CAN_MB7_MFID EQU (0xFFFD02EC) ;- (CAN_MB7) MailBox Family ID Register -AT91C_CAN_MB7_MDL EQU (0xFFFD02F4) ;- (CAN_MB7) MailBox Data Low Register -AT91C_CAN_MB7_MID EQU (0xFFFD02E8) ;- (CAN_MB7) MailBox ID Register -AT91C_CAN_MB7_MMR EQU (0xFFFD02E0) ;- (CAN_MB7) MailBox Mode Register -AT91C_CAN_MB7_MAM EQU (0xFFFD02E4) ;- (CAN_MB7) MailBox Acceptance Mask Register -AT91C_CAN_MB7_MSR EQU (0xFFFD02F0) ;- (CAN_MB7) MailBox Status Register -// - ========== Register definition for CAN peripheral ========== -AT91C_CAN_TCR EQU (0xFFFD0024) ;- (CAN) Transfer Command Register -AT91C_CAN_IMR EQU (0xFFFD000C) ;- (CAN) Interrupt Mask Register -AT91C_CAN_IER EQU (0xFFFD0004) ;- (CAN) Interrupt Enable Register -AT91C_CAN_ECR EQU (0xFFFD0020) ;- (CAN) Error Counter Register -AT91C_CAN_TIMESTP EQU (0xFFFD001C) ;- (CAN) Time Stamp Register -AT91C_CAN_MR EQU (0xFFFD0000) ;- (CAN) Mode Register -AT91C_CAN_IDR EQU (0xFFFD0008) ;- (CAN) Interrupt Disable Register -AT91C_CAN_ACR EQU (0xFFFD0028) ;- (CAN) Abort Command Register -AT91C_CAN_TIM EQU (0xFFFD0018) ;- (CAN) Timer Register -AT91C_CAN_SR EQU (0xFFFD0010) ;- (CAN) Status Register -AT91C_CAN_BR EQU (0xFFFD0014) ;- (CAN) Baudrate Register -AT91C_CAN_VR EQU (0xFFFD00FC) ;- (CAN) Version Register -// - ========== Register definition for EMAC peripheral ========== -AT91C_EMAC_ISR EQU (0xFFFDC024) ;- (EMAC) Interrupt Status Register -AT91C_EMAC_SA4H EQU (0xFFFDC0B4) ;- (EMAC) Specific Address 4 Top, Last 2 bytes -AT91C_EMAC_SA1L EQU (0xFFFDC098) ;- (EMAC) Specific Address 1 Bottom, First 4 bytes -AT91C_EMAC_ELE EQU (0xFFFDC078) ;- (EMAC) Excessive Length Errors Register -AT91C_EMAC_LCOL EQU (0xFFFDC05C) ;- (EMAC) Late Collision Register -AT91C_EMAC_RLE EQU (0xFFFDC088) ;- (EMAC) Receive Length Field Mismatch Register -AT91C_EMAC_WOL EQU (0xFFFDC0C4) ;- (EMAC) Wake On LAN Register -AT91C_EMAC_DTF EQU (0xFFFDC058) ;- (EMAC) Deferred Transmission Frame Register -AT91C_EMAC_TUND EQU (0xFFFDC064) ;- (EMAC) Transmit Underrun Error Register -AT91C_EMAC_NCR EQU (0xFFFDC000) ;- (EMAC) Network Control Register -AT91C_EMAC_SA4L EQU (0xFFFDC0B0) ;- (EMAC) Specific Address 4 Bottom, First 4 bytes -AT91C_EMAC_RSR EQU (0xFFFDC020) ;- (EMAC) Receive Status Register -AT91C_EMAC_SA3L EQU (0xFFFDC0A8) ;- (EMAC) Specific Address 3 Bottom, First 4 bytes -AT91C_EMAC_TSR EQU (0xFFFDC014) ;- (EMAC) Transmit Status Register -AT91C_EMAC_IDR EQU (0xFFFDC02C) ;- (EMAC) Interrupt Disable Register -AT91C_EMAC_RSE EQU (0xFFFDC074) ;- (EMAC) Receive Symbol Errors Register -AT91C_EMAC_ECOL EQU (0xFFFDC060) ;- (EMAC) Excessive Collision Register -AT91C_EMAC_TID EQU (0xFFFDC0B8) ;- (EMAC) Type ID Checking Register -AT91C_EMAC_HRB EQU (0xFFFDC090) ;- (EMAC) Hash Address Bottom[31:0] -AT91C_EMAC_TBQP EQU (0xFFFDC01C) ;- (EMAC) Transmit Buffer Queue Pointer -AT91C_EMAC_USRIO EQU (0xFFFDC0C0) ;- (EMAC) USER Input/Output Register -AT91C_EMAC_PTR EQU (0xFFFDC038) ;- (EMAC) Pause Time Register -AT91C_EMAC_SA2H EQU (0xFFFDC0A4) ;- (EMAC) Specific Address 2 Top, Last 2 bytes -AT91C_EMAC_ROV EQU (0xFFFDC070) ;- (EMAC) Receive Overrun Errors Register -AT91C_EMAC_ALE EQU (0xFFFDC054) ;- (EMAC) Alignment Error Register -AT91C_EMAC_RJA EQU (0xFFFDC07C) ;- (EMAC) Receive Jabbers Register -AT91C_EMAC_RBQP EQU (0xFFFDC018) ;- (EMAC) Receive Buffer Queue Pointer -AT91C_EMAC_TPF EQU (0xFFFDC08C) ;- (EMAC) Transmitted Pause Frames Register -AT91C_EMAC_NCFGR EQU (0xFFFDC004) ;- (EMAC) Network Configuration Register -AT91C_EMAC_HRT EQU (0xFFFDC094) ;- (EMAC) Hash Address Top[63:32] -AT91C_EMAC_USF EQU (0xFFFDC080) ;- (EMAC) Undersize Frames Register -AT91C_EMAC_FCSE EQU (0xFFFDC050) ;- (EMAC) Frame Check Sequence Error Register -AT91C_EMAC_TPQ EQU (0xFFFDC0BC) ;- (EMAC) Transmit Pause Quantum Register -AT91C_EMAC_MAN EQU (0xFFFDC034) ;- (EMAC) PHY Maintenance Register -AT91C_EMAC_FTO EQU (0xFFFDC040) ;- (EMAC) Frames Transmitted OK Register -AT91C_EMAC_REV EQU (0xFFFDC0FC) ;- (EMAC) Revision Register -AT91C_EMAC_IMR EQU (0xFFFDC030) ;- (EMAC) Interrupt Mask Register -AT91C_EMAC_SCF EQU (0xFFFDC044) ;- (EMAC) Single Collision Frame Register -AT91C_EMAC_PFR EQU (0xFFFDC03C) ;- (EMAC) Pause Frames received Register -AT91C_EMAC_MCF EQU (0xFFFDC048) ;- (EMAC) Multiple Collision Frame Register -AT91C_EMAC_NSR EQU (0xFFFDC008) ;- (EMAC) Network Status Register -AT91C_EMAC_SA2L EQU (0xFFFDC0A0) ;- (EMAC) Specific Address 2 Bottom, First 4 bytes -AT91C_EMAC_FRO EQU (0xFFFDC04C) ;- (EMAC) Frames Received OK Register -AT91C_EMAC_IER EQU (0xFFFDC028) ;- (EMAC) Interrupt Enable Register -AT91C_EMAC_SA1H EQU (0xFFFDC09C) ;- (EMAC) Specific Address 1 Top, Last 2 bytes -AT91C_EMAC_CSE EQU (0xFFFDC068) ;- (EMAC) Carrier Sense Error Register -AT91C_EMAC_SA3H EQU (0xFFFDC0AC) ;- (EMAC) Specific Address 3 Top, Last 2 bytes -AT91C_EMAC_RRE EQU (0xFFFDC06C) ;- (EMAC) Receive Ressource Error Register -AT91C_EMAC_STE EQU (0xFFFDC084) ;- (EMAC) SQE Test Error Register -// - ========== Register definition for PDC_ADC peripheral ========== -AT91C_ADC_PTSR EQU (0xFFFD8124) ;- (PDC_ADC) PDC Transfer Status Register -AT91C_ADC_PTCR EQU (0xFFFD8120) ;- (PDC_ADC) PDC Transfer Control Register -AT91C_ADC_TNPR EQU (0xFFFD8118) ;- (PDC_ADC) Transmit Next Pointer Register -AT91C_ADC_TNCR EQU (0xFFFD811C) ;- (PDC_ADC) Transmit Next Counter Register -AT91C_ADC_RNPR EQU (0xFFFD8110) ;- (PDC_ADC) Receive Next Pointer Register -AT91C_ADC_RNCR EQU (0xFFFD8114) ;- (PDC_ADC) Receive Next Counter Register -AT91C_ADC_RPR EQU (0xFFFD8100) ;- (PDC_ADC) Receive Pointer Register -AT91C_ADC_TCR EQU (0xFFFD810C) ;- (PDC_ADC) Transmit Counter Register -AT91C_ADC_TPR EQU (0xFFFD8108) ;- (PDC_ADC) Transmit Pointer Register -AT91C_ADC_RCR EQU (0xFFFD8104) ;- (PDC_ADC) Receive Counter Register -// - ========== Register definition for ADC peripheral ========== -AT91C_ADC_CDR2 EQU (0xFFFD8038) ;- (ADC) ADC Channel Data Register 2 -AT91C_ADC_CDR3 EQU (0xFFFD803C) ;- (ADC) ADC Channel Data Register 3 -AT91C_ADC_CDR0 EQU (0xFFFD8030) ;- (ADC) ADC Channel Data Register 0 -AT91C_ADC_CDR5 EQU (0xFFFD8044) ;- (ADC) ADC Channel Data Register 5 -AT91C_ADC_CHDR EQU (0xFFFD8014) ;- (ADC) ADC Channel Disable Register -AT91C_ADC_SR EQU (0xFFFD801C) ;- (ADC) ADC Status Register -AT91C_ADC_CDR4 EQU (0xFFFD8040) ;- (ADC) ADC Channel Data Register 4 -AT91C_ADC_CDR1 EQU (0xFFFD8034) ;- (ADC) ADC Channel Data Register 1 -AT91C_ADC_LCDR EQU (0xFFFD8020) ;- (ADC) ADC Last Converted Data Register -AT91C_ADC_IDR EQU (0xFFFD8028) ;- (ADC) ADC Interrupt Disable Register -AT91C_ADC_CR EQU (0xFFFD8000) ;- (ADC) ADC Control Register -AT91C_ADC_CDR7 EQU (0xFFFD804C) ;- (ADC) ADC Channel Data Register 7 -AT91C_ADC_CDR6 EQU (0xFFFD8048) ;- (ADC) ADC Channel Data Register 6 -AT91C_ADC_IER EQU (0xFFFD8024) ;- (ADC) ADC Interrupt Enable Register -AT91C_ADC_CHER EQU (0xFFFD8010) ;- (ADC) ADC Channel Enable Register -AT91C_ADC_CHSR EQU (0xFFFD8018) ;- (ADC) ADC Channel Status Register -AT91C_ADC_MR EQU (0xFFFD8004) ;- (ADC) ADC Mode Register -AT91C_ADC_IMR EQU (0xFFFD802C) ;- (ADC) ADC Interrupt Mask Register -// - ========== Register definition for PDC_AES peripheral ========== -AT91C_AES_TPR EQU (0xFFFA4108) ;- (PDC_AES) Transmit Pointer Register -AT91C_AES_PTCR EQU (0xFFFA4120) ;- (PDC_AES) PDC Transfer Control Register -AT91C_AES_RNPR EQU (0xFFFA4110) ;- (PDC_AES) Receive Next Pointer Register -AT91C_AES_TNCR EQU (0xFFFA411C) ;- (PDC_AES) Transmit Next Counter Register -AT91C_AES_TCR EQU (0xFFFA410C) ;- (PDC_AES) Transmit Counter Register -AT91C_AES_RCR EQU (0xFFFA4104) ;- (PDC_AES) Receive Counter Register -AT91C_AES_RNCR EQU (0xFFFA4114) ;- (PDC_AES) Receive Next Counter Register -AT91C_AES_TNPR EQU (0xFFFA4118) ;- (PDC_AES) Transmit Next Pointer Register -AT91C_AES_RPR EQU (0xFFFA4100) ;- (PDC_AES) Receive Pointer Register -AT91C_AES_PTSR EQU (0xFFFA4124) ;- (PDC_AES) PDC Transfer Status Register -// - ========== Register definition for AES peripheral ========== -AT91C_AES_IVxR EQU (0xFFFA4060) ;- (AES) Initialization Vector x Register -AT91C_AES_MR EQU (0xFFFA4004) ;- (AES) Mode Register -AT91C_AES_VR EQU (0xFFFA40FC) ;- (AES) AES Version Register -AT91C_AES_ODATAxR EQU (0xFFFA4050) ;- (AES) Output Data x Register -AT91C_AES_IDATAxR EQU (0xFFFA4040) ;- (AES) Input Data x Register -AT91C_AES_CR EQU (0xFFFA4000) ;- (AES) Control Register -AT91C_AES_IDR EQU (0xFFFA4014) ;- (AES) Interrupt Disable Register -AT91C_AES_IMR EQU (0xFFFA4018) ;- (AES) Interrupt Mask Register -AT91C_AES_IER EQU (0xFFFA4010) ;- (AES) Interrupt Enable Register -AT91C_AES_KEYWxR EQU (0xFFFA4020) ;- (AES) Key Word x Register -AT91C_AES_ISR EQU (0xFFFA401C) ;- (AES) Interrupt Status Register -// - ========== Register definition for PDC_TDES peripheral ========== -AT91C_TDES_RNCR EQU (0xFFFA8114) ;- (PDC_TDES) Receive Next Counter Register -AT91C_TDES_TCR EQU (0xFFFA810C) ;- (PDC_TDES) Transmit Counter Register -AT91C_TDES_RCR EQU (0xFFFA8104) ;- (PDC_TDES) Receive Counter Register -AT91C_TDES_TNPR EQU (0xFFFA8118) ;- (PDC_TDES) Transmit Next Pointer Register -AT91C_TDES_RNPR EQU (0xFFFA8110) ;- (PDC_TDES) Receive Next Pointer Register -AT91C_TDES_RPR EQU (0xFFFA8100) ;- (PDC_TDES) Receive Pointer Register -AT91C_TDES_TNCR EQU (0xFFFA811C) ;- (PDC_TDES) Transmit Next Counter Register -AT91C_TDES_TPR EQU (0xFFFA8108) ;- (PDC_TDES) Transmit Pointer Register -AT91C_TDES_PTSR EQU (0xFFFA8124) ;- (PDC_TDES) PDC Transfer Status Register -AT91C_TDES_PTCR EQU (0xFFFA8120) ;- (PDC_TDES) PDC Transfer Control Register -// - ========== Register definition for TDES peripheral ========== -AT91C_TDES_KEY2WxR EQU (0xFFFA8028) ;- (TDES) Key 2 Word x Register -AT91C_TDES_KEY3WxR EQU (0xFFFA8030) ;- (TDES) Key 3 Word x Register -AT91C_TDES_IDR EQU (0xFFFA8014) ;- (TDES) Interrupt Disable Register -AT91C_TDES_VR EQU (0xFFFA80FC) ;- (TDES) TDES Version Register -AT91C_TDES_IVxR EQU (0xFFFA8060) ;- (TDES) Initialization Vector x Register -AT91C_TDES_ODATAxR EQU (0xFFFA8050) ;- (TDES) Output Data x Register -AT91C_TDES_IMR EQU (0xFFFA8018) ;- (TDES) Interrupt Mask Register -AT91C_TDES_MR EQU (0xFFFA8004) ;- (TDES) Mode Register -AT91C_TDES_CR EQU (0xFFFA8000) ;- (TDES) Control Register -AT91C_TDES_IER EQU (0xFFFA8010) ;- (TDES) Interrupt Enable Register -AT91C_TDES_ISR EQU (0xFFFA801C) ;- (TDES) Interrupt Status Register -AT91C_TDES_IDATAxR EQU (0xFFFA8040) ;- (TDES) Input Data x Register -AT91C_TDES_KEY1WxR EQU (0xFFFA8020) ;- (TDES) Key 1 Word x Register +/* - ***************************************************************************** */ +/* - SOFTWARE API DEFINITION FOR USB Device Interface */ +/* - ***************************************************************************** */ +/* - -------- UDP_FRM_NUM : (UDP Offset: 0x0) USB Frame Number Register -------- */ + AT91C_UDP_FRM_NUM EQU( 0x7FF << 0 ); + -( UDP ) Frame Number as Defined in the Packet Field Formats + AT91C_UDP_FRM_ERR EQU( 0x1 << 16 ); + -( UDP ) Frame Error + AT91C_UDP_FRM_OK EQU( 0x1 << 17 ); + -( UDP ) Frame OK +/* - -------- UDP_GLB_STATE : (UDP Offset: 0x4) USB Global State Register -------- */ + AT91C_UDP_FADDEN EQU( 0x1 << 0 ); + -( UDP ) Function Address Enable + AT91C_UDP_CONFG EQU( 0x1 << 1 ); + -( UDP ) Configured + AT91C_UDP_ESR EQU( 0x1 << 2 ); + -( UDP ) Enable Send Resume + AT91C_UDP_RSMINPR EQU( 0x1 << 3 ); + -( UDP ) A Resume Has Been Sent to the Host + AT91C_UDP_RMWUPE EQU( 0x1 << 4 ); + -( UDP ) Remote Wake Up Enable +/* - -------- UDP_FADDR : (UDP Offset: 0x8) USB Function Address Register -------- */ + AT91C_UDP_FADD EQU( 0xFF << 0 ); + -( UDP ) Function Address Value + AT91C_UDP_FEN EQU( 0x1 << 8 ); + -( UDP ) Function Enable +/* - -------- UDP_IER : (UDP Offset: 0x10) USB Interrupt Enable Register -------- */ + AT91C_UDP_EPINT0 EQU( 0x1 << 0 ); + -( UDP ) Endpoint 0 Interrupt + AT91C_UDP_EPINT1 EQU( 0x1 << 1 ); + -( UDP ) Endpoint 0 Interrupt + AT91C_UDP_EPINT2 EQU( 0x1 << 2 ); + -( UDP ) Endpoint 2 Interrupt + AT91C_UDP_EPINT3 EQU( 0x1 << 3 ); + -( UDP ) Endpoint 3 Interrupt + AT91C_UDP_EPINT4 EQU( 0x1 << 4 ); + -( UDP ) Endpoint 4 Interrupt + AT91C_UDP_EPINT5 EQU( 0x1 << 5 ); + -( UDP ) Endpoint 5 Interrupt + AT91C_UDP_RXSUSP EQU( 0x1 << 8 ); + -( UDP ) USB Suspend Interrupt + AT91C_UDP_RXRSM EQU( 0x1 << 9 ); + -( UDP ) USB Resume Interrupt + AT91C_UDP_EXTRSM EQU( 0x1 << 10 ); + -( UDP ) USB External Resume Interrupt + AT91C_UDP_SOFINT EQU( 0x1 << 11 ); + -( UDP ) USB Start Of frame Interrupt + AT91C_UDP_WAKEUP EQU( 0x1 << 13 ); + -( UDP ) USB Resume Interrupt +/* - -------- UDP_IDR : (UDP Offset: 0x14) USB Interrupt Disable Register -------- */ +/* - -------- UDP_IMR : (UDP Offset: 0x18) USB Interrupt Mask Register -------- */ +/* - -------- UDP_ISR : (UDP Offset: 0x1c) USB Interrupt Status Register -------- */ + AT91C_UDP_ENDBUSRES EQU( 0x1 << 12 ); + -( UDP ) USB End Of Bus Reset Interrupt +/* - -------- UDP_ICR : (UDP Offset: 0x20) USB Interrupt Clear Register -------- */ +/* - -------- UDP_RST_EP : (UDP Offset: 0x28) USB Reset Endpoint Register -------- */ + AT91C_UDP_EP0 EQU( 0x1 << 0 ); + -( UDP ) Reset Endpoint 0 + AT91C_UDP_EP1 EQU( 0x1 << 1 ); + -( UDP ) Reset Endpoint 1 + AT91C_UDP_EP2 EQU( 0x1 << 2 ); + -( UDP ) Reset Endpoint 2 + AT91C_UDP_EP3 EQU( 0x1 << 3 ); + -( UDP ) Reset Endpoint 3 + AT91C_UDP_EP4 EQU( 0x1 << 4 ); + -( UDP ) Reset Endpoint 4 + AT91C_UDP_EP5 EQU( 0x1 << 5 ); + -( UDP ) Reset Endpoint 5 +/* - -------- UDP_CSR : (UDP Offset: 0x30) USB Endpoint Control and Status Register -------- */ + AT91C_UDP_TXCOMP EQU( 0x1 << 0 ); + -( UDP ) Generates an IN packet with data previously written in the DPR + AT91C_UDP_RX_DATA_BK0 EQU( 0x1 << 1 ); + -( UDP ) Receive Data Bank 0 + AT91C_UDP_RXSETUP EQU( 0x1 << 2 ); + -( UDP ) Sends STALL to the Host( Control endpoints ) + AT91C_UDP_ISOERROR EQU( 0x1 << 3 ); + -( UDP ) Isochronous error( Isochronous endpoints ) + AT91C_UDP_TXPKTRDY EQU( 0x1 << 4 ); + -( UDP ) Transmit Packet Ready + AT91C_UDP_FORCESTALL EQU( 0x1 << 5 ); + -( UDP ) Force Stall( used by Control, Bulk and Isochronous endpoints ). + AT91C_UDP_RX_DATA_BK1 EQU( 0x1 << 6 ); + -( UDP ) Receive Data Bank 1 ( only used by endpoints with ping - pong attributes ). + AT91C_UDP_DIR EQU( 0x1 << 7 ); + -( UDP ) Transfer Direction + AT91C_UDP_EPTYPE EQU( 0x7 << 8 ); + -( UDP ) Endpoint type + AT91C_UDP_EPTYPE_CTRL EQU( 0x0 << 8 ); + -( UDP ) Control + AT91C_UDP_EPTYPE_ISO_OUT EQU( 0x1 << 8 ); + -( UDP ) Isochronous OUT + AT91C_UDP_EPTYPE_BULK_OUT EQU( 0x2 << 8 ); + -( UDP ) Bulk OUT + AT91C_UDP_EPTYPE_INT_OUT EQU( 0x3 << 8 ); + -( UDP ) Interrupt OUT + AT91C_UDP_EPTYPE_ISO_IN EQU( 0x5 << 8 ); + -( UDP ) Isochronous IN + AT91C_UDP_EPTYPE_BULK_IN EQU( 0x6 << 8 ); + -( UDP ) Bulk IN + AT91C_UDP_EPTYPE_INT_IN EQU( 0x7 << 8 ); + -( UDP ) Interrupt IN + AT91C_UDP_DTGLE EQU( 0x1 << 11 ); + -( UDP ) Data Toggle + AT91C_UDP_EPEDS EQU( 0x1 << 15 ); + -( UDP ) Endpoint Enable Disable + AT91C_UDP_RXBYTECNT EQU( 0x7FF << 16 ); + -( UDP ) Number Of Bytes Available in the FIFO +/* - -------- UDP_TXVC : (UDP Offset: 0x74) Transceiver Control Register -------- */ + AT91C_UDP_TXVDIS EQU( 0x1 << 8 ); + -( UDP ) + AT91C_UDP_PUON EQU( 0x1 << 9 ); + -( UDP ) Pull - up ON -// - ***************************************************************************** -// - PIO DEFINITIONS FOR AT91SAM7X256 -// - ***************************************************************************** -AT91C_PIO_PA0 EQU (1 << 0) ;- Pin Controlled by PA0 -AT91C_PA0_RXD0 EQU (AT91C_PIO_PA0) ;- USART 0 Receive Data -AT91C_PIO_PA1 EQU (1 << 1) ;- Pin Controlled by PA1 -AT91C_PA1_TXD0 EQU (AT91C_PIO_PA1) ;- USART 0 Transmit Data -AT91C_PIO_PA10 EQU (1 << 10) ;- Pin Controlled by PA10 -AT91C_PA10_TWD EQU (AT91C_PIO_PA10) ;- TWI Two-wire Serial Data -AT91C_PIO_PA11 EQU (1 << 11) ;- Pin Controlled by PA11 -AT91C_PA11_TWCK EQU (AT91C_PIO_PA11) ;- TWI Two-wire Serial Clock -AT91C_PIO_PA12 EQU (1 << 12) ;- Pin Controlled by PA12 -AT91C_PA12_NPCS00 EQU (AT91C_PIO_PA12) ;- SPI 0 Peripheral Chip Select 0 -AT91C_PIO_PA13 EQU (1 << 13) ;- Pin Controlled by PA13 -AT91C_PA13_NPCS01 EQU (AT91C_PIO_PA13) ;- SPI 0 Peripheral Chip Select 1 -AT91C_PA13_PCK1 EQU (AT91C_PIO_PA13) ;- PMC Programmable Clock Output 1 -AT91C_PIO_PA14 EQU (1 << 14) ;- Pin Controlled by PA14 -AT91C_PA14_NPCS02 EQU (AT91C_PIO_PA14) ;- SPI 0 Peripheral Chip Select 2 -AT91C_PA14_IRQ1 EQU (AT91C_PIO_PA14) ;- External Interrupt 1 -AT91C_PIO_PA15 EQU (1 << 15) ;- Pin Controlled by PA15 -AT91C_PA15_NPCS03 EQU (AT91C_PIO_PA15) ;- SPI 0 Peripheral Chip Select 3 -AT91C_PA15_TCLK2 EQU (AT91C_PIO_PA15) ;- Timer Counter 2 external clock input -AT91C_PIO_PA16 EQU (1 << 16) ;- Pin Controlled by PA16 -AT91C_PA16_MISO0 EQU (AT91C_PIO_PA16) ;- SPI 0 Master In Slave -AT91C_PIO_PA17 EQU (1 << 17) ;- Pin Controlled by PA17 -AT91C_PA17_MOSI0 EQU (AT91C_PIO_PA17) ;- SPI 0 Master Out Slave -AT91C_PIO_PA18 EQU (1 << 18) ;- Pin Controlled by PA18 -AT91C_PA18_SPCK0 EQU (AT91C_PIO_PA18) ;- SPI 0 Serial Clock -AT91C_PIO_PA19 EQU (1 << 19) ;- Pin Controlled by PA19 -AT91C_PA19_CANRX EQU (AT91C_PIO_PA19) ;- CAN Receive -AT91C_PIO_PA2 EQU (1 << 2) ;- Pin Controlled by PA2 -AT91C_PA2_SCK0 EQU (AT91C_PIO_PA2) ;- USART 0 Serial Clock -AT91C_PA2_NPCS11 EQU (AT91C_PIO_PA2) ;- SPI 1 Peripheral Chip Select 1 -AT91C_PIO_PA20 EQU (1 << 20) ;- Pin Controlled by PA20 -AT91C_PA20_CANTX EQU (AT91C_PIO_PA20) ;- CAN Transmit -AT91C_PIO_PA21 EQU (1 << 21) ;- Pin Controlled by PA21 -AT91C_PA21_TF EQU (AT91C_PIO_PA21) ;- SSC Transmit Frame Sync -AT91C_PA21_NPCS10 EQU (AT91C_PIO_PA21) ;- SPI 1 Peripheral Chip Select 0 -AT91C_PIO_PA22 EQU (1 << 22) ;- Pin Controlled by PA22 -AT91C_PA22_TK EQU (AT91C_PIO_PA22) ;- SSC Transmit Clock -AT91C_PA22_SPCK1 EQU (AT91C_PIO_PA22) ;- SPI 1 Serial Clock -AT91C_PIO_PA23 EQU (1 << 23) ;- Pin Controlled by PA23 -AT91C_PA23_TD EQU (AT91C_PIO_PA23) ;- SSC Transmit data -AT91C_PA23_MOSI1 EQU (AT91C_PIO_PA23) ;- SPI 1 Master Out Slave -AT91C_PIO_PA24 EQU (1 << 24) ;- Pin Controlled by PA24 -AT91C_PA24_RD EQU (AT91C_PIO_PA24) ;- SSC Receive Data -AT91C_PA24_MISO1 EQU (AT91C_PIO_PA24) ;- SPI 1 Master In Slave -AT91C_PIO_PA25 EQU (1 << 25) ;- Pin Controlled by PA25 -AT91C_PA25_RK EQU (AT91C_PIO_PA25) ;- SSC Receive Clock -AT91C_PA25_NPCS11 EQU (AT91C_PIO_PA25) ;- SPI 1 Peripheral Chip Select 1 -AT91C_PIO_PA26 EQU (1 << 26) ;- Pin Controlled by PA26 -AT91C_PA26_RF EQU (AT91C_PIO_PA26) ;- SSC Receive Frame Sync -AT91C_PA26_NPCS12 EQU (AT91C_PIO_PA26) ;- SPI 1 Peripheral Chip Select 2 -AT91C_PIO_PA27 EQU (1 << 27) ;- Pin Controlled by PA27 -AT91C_PA27_DRXD EQU (AT91C_PIO_PA27) ;- DBGU Debug Receive Data -AT91C_PA27_PCK3 EQU (AT91C_PIO_PA27) ;- PMC Programmable Clock Output 3 -AT91C_PIO_PA28 EQU (1 << 28) ;- Pin Controlled by PA28 -AT91C_PA28_DTXD EQU (AT91C_PIO_PA28) ;- DBGU Debug Transmit Data -AT91C_PIO_PA29 EQU (1 << 29) ;- Pin Controlled by PA29 -AT91C_PA29_FIQ EQU (AT91C_PIO_PA29) ;- AIC Fast Interrupt Input -AT91C_PA29_NPCS13 EQU (AT91C_PIO_PA29) ;- SPI 1 Peripheral Chip Select 3 -AT91C_PIO_PA3 EQU (1 << 3) ;- Pin Controlled by PA3 -AT91C_PA3_RTS0 EQU (AT91C_PIO_PA3) ;- USART 0 Ready To Send -AT91C_PA3_NPCS12 EQU (AT91C_PIO_PA3) ;- SPI 1 Peripheral Chip Select 2 -AT91C_PIO_PA30 EQU (1 << 30) ;- Pin Controlled by PA30 -AT91C_PA30_IRQ0 EQU (AT91C_PIO_PA30) ;- External Interrupt 0 -AT91C_PA30_PCK2 EQU (AT91C_PIO_PA30) ;- PMC Programmable Clock Output 2 -AT91C_PIO_PA4 EQU (1 << 4) ;- Pin Controlled by PA4 -AT91C_PA4_CTS0 EQU (AT91C_PIO_PA4) ;- USART 0 Clear To Send -AT91C_PA4_NPCS13 EQU (AT91C_PIO_PA4) ;- SPI 1 Peripheral Chip Select 3 -AT91C_PIO_PA5 EQU (1 << 5) ;- Pin Controlled by PA5 -AT91C_PA5_RXD1 EQU (AT91C_PIO_PA5) ;- USART 1 Receive Data -AT91C_PIO_PA6 EQU (1 << 6) ;- Pin Controlled by PA6 -AT91C_PA6_TXD1 EQU (AT91C_PIO_PA6) ;- USART 1 Transmit Data -AT91C_PIO_PA7 EQU (1 << 7) ;- Pin Controlled by PA7 -AT91C_PA7_SCK1 EQU (AT91C_PIO_PA7) ;- USART 1 Serial Clock -AT91C_PA7_NPCS01 EQU (AT91C_PIO_PA7) ;- SPI 0 Peripheral Chip Select 1 -AT91C_PIO_PA8 EQU (1 << 8) ;- Pin Controlled by PA8 -AT91C_PA8_RTS1 EQU (AT91C_PIO_PA8) ;- USART 1 Ready To Send -AT91C_PA8_NPCS02 EQU (AT91C_PIO_PA8) ;- SPI 0 Peripheral Chip Select 2 -AT91C_PIO_PA9 EQU (1 << 9) ;- Pin Controlled by PA9 -AT91C_PA9_CTS1 EQU (AT91C_PIO_PA9) ;- USART 1 Clear To Send -AT91C_PA9_NPCS03 EQU (AT91C_PIO_PA9) ;- SPI 0 Peripheral Chip Select 3 -AT91C_PIO_PB0 EQU (1 << 0) ;- Pin Controlled by PB0 -AT91C_PB0_ETXCK_EREFCK EQU (AT91C_PIO_PB0) ;- Ethernet MAC Transmit Clock/Reference Clock -AT91C_PB0_PCK0 EQU (AT91C_PIO_PB0) ;- PMC Programmable Clock Output 0 -AT91C_PIO_PB1 EQU (1 << 1) ;- Pin Controlled by PB1 -AT91C_PB1_ETXEN EQU (AT91C_PIO_PB1) ;- Ethernet MAC Transmit Enable -AT91C_PIO_PB10 EQU (1 << 10) ;- Pin Controlled by PB10 -AT91C_PB10_ETX2 EQU (AT91C_PIO_PB10) ;- Ethernet MAC Transmit Data 2 -AT91C_PB10_NPCS11 EQU (AT91C_PIO_PB10) ;- SPI 1 Peripheral Chip Select 1 -AT91C_PIO_PB11 EQU (1 << 11) ;- Pin Controlled by PB11 -AT91C_PB11_ETX3 EQU (AT91C_PIO_PB11) ;- Ethernet MAC Transmit Data 3 -AT91C_PB11_NPCS12 EQU (AT91C_PIO_PB11) ;- SPI 1 Peripheral Chip Select 2 -AT91C_PIO_PB12 EQU (1 << 12) ;- Pin Controlled by PB12 -AT91C_PB12_ETXER EQU (AT91C_PIO_PB12) ;- Ethernet MAC Transmikt Coding Error -AT91C_PB12_TCLK0 EQU (AT91C_PIO_PB12) ;- Timer Counter 0 external clock input -AT91C_PIO_PB13 EQU (1 << 13) ;- Pin Controlled by PB13 -AT91C_PB13_ERX2 EQU (AT91C_PIO_PB13) ;- Ethernet MAC Receive Data 2 -AT91C_PB13_NPCS01 EQU (AT91C_PIO_PB13) ;- SPI 0 Peripheral Chip Select 1 -AT91C_PIO_PB14 EQU (1 << 14) ;- Pin Controlled by PB14 -AT91C_PB14_ERX3 EQU (AT91C_PIO_PB14) ;- Ethernet MAC Receive Data 3 -AT91C_PB14_NPCS02 EQU (AT91C_PIO_PB14) ;- SPI 0 Peripheral Chip Select 2 -AT91C_PIO_PB15 EQU (1 << 15) ;- Pin Controlled by PB15 -AT91C_PB15_ERXDV EQU (AT91C_PIO_PB15) ;- Ethernet MAC Receive Data Valid -AT91C_PIO_PB16 EQU (1 << 16) ;- Pin Controlled by PB16 -AT91C_PB16_ECOL EQU (AT91C_PIO_PB16) ;- Ethernet MAC Collision Detected -AT91C_PB16_NPCS13 EQU (AT91C_PIO_PB16) ;- SPI 1 Peripheral Chip Select 3 -AT91C_PIO_PB17 EQU (1 << 17) ;- Pin Controlled by PB17 -AT91C_PB17_ERXCK EQU (AT91C_PIO_PB17) ;- Ethernet MAC Receive Clock -AT91C_PB17_NPCS03 EQU (AT91C_PIO_PB17) ;- SPI 0 Peripheral Chip Select 3 -AT91C_PIO_PB18 EQU (1 << 18) ;- Pin Controlled by PB18 -AT91C_PB18_EF100 EQU (AT91C_PIO_PB18) ;- Ethernet MAC Force 100 Mbits/sec -AT91C_PB18_ADTRG EQU (AT91C_PIO_PB18) ;- ADC External Trigger -AT91C_PIO_PB19 EQU (1 << 19) ;- Pin Controlled by PB19 -AT91C_PB19_PWM0 EQU (AT91C_PIO_PB19) ;- PWM Channel 0 -AT91C_PB19_TCLK1 EQU (AT91C_PIO_PB19) ;- Timer Counter 1 external clock input -AT91C_PIO_PB2 EQU (1 << 2) ;- Pin Controlled by PB2 -AT91C_PB2_ETX0 EQU (AT91C_PIO_PB2) ;- Ethernet MAC Transmit Data 0 -AT91C_PIO_PB20 EQU (1 << 20) ;- Pin Controlled by PB20 -AT91C_PB20_PWM1 EQU (AT91C_PIO_PB20) ;- PWM Channel 1 -AT91C_PB20_PCK0 EQU (AT91C_PIO_PB20) ;- PMC Programmable Clock Output 0 -AT91C_PIO_PB21 EQU (1 << 21) ;- Pin Controlled by PB21 -AT91C_PB21_PWM2 EQU (AT91C_PIO_PB21) ;- PWM Channel 2 -AT91C_PB21_PCK1 EQU (AT91C_PIO_PB21) ;- PMC Programmable Clock Output 1 -AT91C_PIO_PB22 EQU (1 << 22) ;- Pin Controlled by PB22 -AT91C_PB22_PWM3 EQU (AT91C_PIO_PB22) ;- PWM Channel 3 -AT91C_PB22_PCK2 EQU (AT91C_PIO_PB22) ;- PMC Programmable Clock Output 2 -AT91C_PIO_PB23 EQU (1 << 23) ;- Pin Controlled by PB23 -AT91C_PB23_TIOA0 EQU (AT91C_PIO_PB23) ;- Timer Counter 0 Multipurpose Timer I/O Pin A -AT91C_PB23_DCD1 EQU (AT91C_PIO_PB23) ;- USART 1 Data Carrier Detect -AT91C_PIO_PB24 EQU (1 << 24) ;- Pin Controlled by PB24 -AT91C_PB24_TIOB0 EQU (AT91C_PIO_PB24) ;- Timer Counter 0 Multipurpose Timer I/O Pin B -AT91C_PB24_DSR1 EQU (AT91C_PIO_PB24) ;- USART 1 Data Set ready -AT91C_PIO_PB25 EQU (1 << 25) ;- Pin Controlled by PB25 -AT91C_PB25_TIOA1 EQU (AT91C_PIO_PB25) ;- Timer Counter 1 Multipurpose Timer I/O Pin A -AT91C_PB25_DTR1 EQU (AT91C_PIO_PB25) ;- USART 1 Data Terminal ready -AT91C_PIO_PB26 EQU (1 << 26) ;- Pin Controlled by PB26 -AT91C_PB26_TIOB1 EQU (AT91C_PIO_PB26) ;- Timer Counter 1 Multipurpose Timer I/O Pin B -AT91C_PB26_RI1 EQU (AT91C_PIO_PB26) ;- USART 1 Ring Indicator -AT91C_PIO_PB27 EQU (1 << 27) ;- Pin Controlled by PB27 -AT91C_PB27_TIOA2 EQU (AT91C_PIO_PB27) ;- Timer Counter 2 Multipurpose Timer I/O Pin A -AT91C_PB27_PWM0 EQU (AT91C_PIO_PB27) ;- PWM Channel 0 -AT91C_PIO_PB28 EQU (1 << 28) ;- Pin Controlled by PB28 -AT91C_PB28_TIOB2 EQU (AT91C_PIO_PB28) ;- Timer Counter 2 Multipurpose Timer I/O Pin B -AT91C_PB28_PWM1 EQU (AT91C_PIO_PB28) ;- PWM Channel 1 -AT91C_PIO_PB29 EQU (1 << 29) ;- Pin Controlled by PB29 -AT91C_PB29_PCK1 EQU (AT91C_PIO_PB29) ;- PMC Programmable Clock Output 1 -AT91C_PB29_PWM2 EQU (AT91C_PIO_PB29) ;- PWM Channel 2 -AT91C_PIO_PB3 EQU (1 << 3) ;- Pin Controlled by PB3 -AT91C_PB3_ETX1 EQU (AT91C_PIO_PB3) ;- Ethernet MAC Transmit Data 1 -AT91C_PIO_PB30 EQU (1 << 30) ;- Pin Controlled by PB30 -AT91C_PB30_PCK2 EQU (AT91C_PIO_PB30) ;- PMC Programmable Clock Output 2 -AT91C_PB30_PWM3 EQU (AT91C_PIO_PB30) ;- PWM Channel 3 -AT91C_PIO_PB4 EQU (1 << 4) ;- Pin Controlled by PB4 -AT91C_PB4_ECRS_ECRSDV EQU (AT91C_PIO_PB4) ;- Ethernet MAC Carrier Sense/Carrier Sense and Data Valid -AT91C_PIO_PB5 EQU (1 << 5) ;- Pin Controlled by PB5 -AT91C_PB5_ERX0 EQU (AT91C_PIO_PB5) ;- Ethernet MAC Receive Data 0 -AT91C_PIO_PB6 EQU (1 << 6) ;- Pin Controlled by PB6 -AT91C_PB6_ERX1 EQU (AT91C_PIO_PB6) ;- Ethernet MAC Receive Data 1 -AT91C_PIO_PB7 EQU (1 << 7) ;- Pin Controlled by PB7 -AT91C_PB7_ERXER EQU (AT91C_PIO_PB7) ;- Ethernet MAC Receive Error -AT91C_PIO_PB8 EQU (1 << 8) ;- Pin Controlled by PB8 -AT91C_PB8_EMDC EQU (AT91C_PIO_PB8) ;- Ethernet MAC Management Data Clock -AT91C_PIO_PB9 EQU (1 << 9) ;- Pin Controlled by PB9 -AT91C_PB9_EMDIO EQU (AT91C_PIO_PB9) ;- Ethernet MAC Management Data Input/Output +/* - ***************************************************************************** */ +/* - SOFTWARE API DEFINITION FOR Timer Counter Channel Interface */ +/* - ***************************************************************************** */ +/* - -------- TC_CCR : (TC Offset: 0x0) TC Channel Control Register -------- */ + AT91C_TC_CLKEN EQU( 0x1 << 0 ); + -( TC ) Counter Clock Enable Command + AT91C_TC_CLKDIS EQU( 0x1 << 1 ); + -( TC ) Counter Clock Disable Command + AT91C_TC_SWTRG EQU( 0x1 << 2 ); + -( TC ) Software Trigger Command +/* - -------- TC_CMR : (TC Offset: 0x4) TC Channel Mode Register: Capture Mode / Waveform Mode -------- */ + AT91C_TC_CLKS EQU( 0x7 << 0 ); + -( TC ) Clock Selection + AT91C_TC_CLKS_TIMER_DIV1_CLOCK EQU( 0x0 ); + -( TC ) Clock selected:TIMER_DIV1_CLOCK + AT91C_TC_CLKS_TIMER_DIV2_CLOCK EQU( 0x1 ); + -( TC ) Clock selected:TIMER_DIV2_CLOCK + AT91C_TC_CLKS_TIMER_DIV3_CLOCK EQU( 0x2 ); + -( TC ) Clock selected:TIMER_DIV3_CLOCK + AT91C_TC_CLKS_TIMER_DIV4_CLOCK EQU( 0x3 ); + -( TC ) Clock selected:TIMER_DIV4_CLOCK + AT91C_TC_CLKS_TIMER_DIV5_CLOCK EQU( 0x4 ); + -( TC ) Clock selected:TIMER_DIV5_CLOCK + AT91C_TC_CLKS_XC0 EQU( 0x5 ); + -( TC ) Clock selected:XC0 + AT91C_TC_CLKS_XC1 EQU( 0x6 ); + -( TC ) Clock selected:XC1 + AT91C_TC_CLKS_XC2 EQU( 0x7 ); + -( TC ) Clock selected:XC2 + AT91C_TC_CLKI EQU( 0x1 << 3 ); + -( TC ) Clock Invert + AT91C_TC_BURST EQU( 0x3 << 4 ); + -( TC ) Burst Signal Selection + AT91C_TC_BURST_NONE EQU( 0x0 << 4 ); + -( TC ) The clock is not gated by an external signal + AT91C_TC_BURST_XC0 EQU( 0x1 << 4 ); + -( TC ) XC0 is ANDed with the selected clock + AT91C_TC_BURST_XC1 EQU( 0x2 << 4 ); + -( TC ) XC1 is ANDed with the selected clock + AT91C_TC_BURST_XC2 EQU( 0x3 << 4 ); + -( TC ) XC2 is ANDed with the selected clock + AT91C_TC_CPCSTOP EQU( 0x1 << 6 ); + -( TC ) Counter Clock Stopped with RC Compare + AT91C_TC_LDBSTOP EQU( 0x1 << 6 ); + -( TC ) Counter Clock Stopped with RB Loading + AT91C_TC_CPCDIS EQU( 0x1 << 7 ); + -( TC ) Counter Clock Disable with RC Compare + AT91C_TC_LDBDIS EQU( 0x1 << 7 ); + -( TC ) Counter Clock Disabled with RB Loading + AT91C_TC_ETRGEDG EQU( 0x3 << 8 ); + -( TC ) External Trigger Edge Selection + AT91C_TC_ETRGEDG_NONE EQU( 0x0 << 8 ); + -( TC ) Edge:None + AT91C_TC_ETRGEDG_RISING EQU( 0x1 << 8 ); + -( TC ) Edge:rising edge + AT91C_TC_ETRGEDG_FALLING EQU( 0x2 << 8 ); + -( TC ) Edge:falling edge + AT91C_TC_ETRGEDG_BOTH EQU( 0x3 << 8 ); + -( TC ) Edge:each edge + AT91C_TC_EEVTEDG EQU( 0x3 << 8 ); + -( TC ) External Event Edge Selection + AT91C_TC_EEVTEDG_NONE EQU( 0x0 << 8 ); + -( TC ) Edge:None + AT91C_TC_EEVTEDG_RISING EQU( 0x1 << 8 ); + -( TC ) Edge:rising edge + AT91C_TC_EEVTEDG_FALLING EQU( 0x2 << 8 ); + -( TC ) Edge:falling edge + AT91C_TC_EEVTEDG_BOTH EQU( 0x3 << 8 ); + -( TC ) Edge:each edge + AT91C_TC_EEVT EQU( 0x3 << 10 ); + -( TC ) External Event Selection + AT91C_TC_EEVT_TIOB EQU( 0x0 << 10 ); + -( TC ) Signal selected as external event:TIOB TIOB direction: input + AT91C_TC_EEVT_XC0 EQU( 0x1 << 10 ); + -( TC ) Signal selected as external event:XC0 TIOB direction: output + AT91C_TC_EEVT_XC1 EQU( 0x2 << 10 ); + -( TC ) Signal selected as external event:XC1 TIOB direction: output + AT91C_TC_EEVT_XC2 EQU( 0x3 << 10 ); + -( TC ) Signal selected as external event:XC2 TIOB direction: output + AT91C_TC_ABETRG EQU( 0x1 << 10 ); + -( TC ) TIOA or TIOB External Trigger Selection + AT91C_TC_ENETRG EQU( 0x1 << 12 ); + -( TC ) External Event Trigger enable + AT91C_TC_WAVESEL EQU( 0x3 << 13 ); + -( TC ) Waveform Selection + AT91C_TC_WAVESEL_UP EQU( 0x0 << 13 ); + -( TC ) UP mode without atomatic trigger on RC Compare + AT91C_TC_WAVESEL_UPDOWN EQU( 0x1 << 13 ); + -( TC ) UPDOWN mode without automatic trigger on RC Compare + AT91C_TC_WAVESEL_UP_AUTO EQU( 0x2 << 13 ); + -( TC ) UP mode with automatic trigger on RC Compare + AT91C_TC_WAVESEL_UPDOWN_AUTO EQU( 0x3 << 13 ); + -( TC ) UPDOWN mode with automatic trigger on RC Compare + AT91C_TC_CPCTRG EQU( 0x1 << 14 ); + -( TC ) RC Compare Trigger Enable + AT91C_TC_WAVE EQU( 0x1 << 15 ); + -( TC ) + AT91C_TC_ACPA EQU( 0x3 << 16 ); + -( TC ) RA Compare Effect on TIOA + AT91C_TC_ACPA_NONE EQU( 0x0 << 16 ); + -( TC ) Effect:none + AT91C_TC_ACPA_SET EQU( 0x1 << 16 ); + -( TC ) Effect:set + AT91C_TC_ACPA_CLEAR EQU( 0x2 << 16 ); + -( TC ) Effect:clear + AT91C_TC_ACPA_TOGGLE EQU( 0x3 << 16 ); + -( TC ) Effect:toggle + AT91C_TC_LDRA EQU( 0x3 << 16 ); + -( TC ) RA Loading Selection + AT91C_TC_LDRA_NONE EQU( 0x0 << 16 ); + -( TC ) Edge:None + AT91C_TC_LDRA_RISING EQU( 0x1 << 16 ); + -( TC ) Edge:rising edge of TIOA + AT91C_TC_LDRA_FALLING EQU( 0x2 << 16 ); + -( TC ) Edge:falling edge of TIOA + AT91C_TC_LDRA_BOTH EQU( 0x3 << 16 ); + -( TC ) Edge:each edge of TIOA + AT91C_TC_ACPC EQU( 0x3 << 18 ); + -( TC ) RC Compare Effect on TIOA + AT91C_TC_ACPC_NONE EQU( 0x0 << 18 ); + -( TC ) Effect:none + AT91C_TC_ACPC_SET EQU( 0x1 << 18 ); + -( TC ) Effect:set + AT91C_TC_ACPC_CLEAR EQU( 0x2 << 18 ); + -( TC ) Effect:clear + AT91C_TC_ACPC_TOGGLE EQU( 0x3 << 18 ); + -( TC ) Effect:toggle + AT91C_TC_LDRB EQU( 0x3 << 18 ); + -( TC ) RB Loading Selection + AT91C_TC_LDRB_NONE EQU( 0x0 << 18 ); + -( TC ) Edge:None + AT91C_TC_LDRB_RISING EQU( 0x1 << 18 ); + -( TC ) Edge:rising edge of TIOA + AT91C_TC_LDRB_FALLING EQU( 0x2 << 18 ); + -( TC ) Edge:falling edge of TIOA + AT91C_TC_LDRB_BOTH EQU( 0x3 << 18 ); + -( TC ) Edge:each edge of TIOA + AT91C_TC_AEEVT EQU( 0x3 << 20 ); + -( TC ) External Event Effect on TIOA + AT91C_TC_AEEVT_NONE EQU( 0x0 << 20 ); + -( TC ) Effect:none + AT91C_TC_AEEVT_SET EQU( 0x1 << 20 ); + -( TC ) Effect:set + AT91C_TC_AEEVT_CLEAR EQU( 0x2 << 20 ); + -( TC ) Effect:clear + AT91C_TC_AEEVT_TOGGLE EQU( 0x3 << 20 ); + -( TC ) Effect:toggle + AT91C_TC_ASWTRG EQU( 0x3 << 22 ); + -( TC ) Software Trigger Effect on TIOA + AT91C_TC_ASWTRG_NONE EQU( 0x0 << 22 ); + -( TC ) Effect:none + AT91C_TC_ASWTRG_SET EQU( 0x1 << 22 ); + -( TC ) Effect:set + AT91C_TC_ASWTRG_CLEAR EQU( 0x2 << 22 ); + -( TC ) Effect:clear + AT91C_TC_ASWTRG_TOGGLE EQU( 0x3 << 22 ); + -( TC ) Effect:toggle + AT91C_TC_BCPB EQU( 0x3 << 24 ); + -( TC ) RB Compare Effect on TIOB + AT91C_TC_BCPB_NONE EQU( 0x0 << 24 ); + -( TC ) Effect:none + AT91C_TC_BCPB_SET EQU( 0x1 << 24 ); + -( TC ) Effect:set + AT91C_TC_BCPB_CLEAR EQU( 0x2 << 24 ); + -( TC ) Effect:clear + AT91C_TC_BCPB_TOGGLE EQU( 0x3 << 24 ); + -( TC ) Effect:toggle + AT91C_TC_BCPC EQU( 0x3 << 26 ); + -( TC ) RC Compare Effect on TIOB + AT91C_TC_BCPC_NONE EQU( 0x0 << 26 ); + -( TC ) Effect:none + AT91C_TC_BCPC_SET EQU( 0x1 << 26 ); + -( TC ) Effect:set + AT91C_TC_BCPC_CLEAR EQU( 0x2 << 26 ); + -( TC ) Effect:clear + AT91C_TC_BCPC_TOGGLE EQU( 0x3 << 26 ); + -( TC ) Effect:toggle + AT91C_TC_BEEVT EQU( 0x3 << 28 ); + -( TC ) External Event Effect on TIOB + AT91C_TC_BEEVT_NONE EQU( 0x0 << 28 ); + -( TC ) Effect:none + AT91C_TC_BEEVT_SET EQU( 0x1 << 28 ); + -( TC ) Effect:set + AT91C_TC_BEEVT_CLEAR EQU( 0x2 << 28 ); + -( TC ) Effect:clear + AT91C_TC_BEEVT_TOGGLE EQU( 0x3 << 28 ); + -( TC ) Effect:toggle + AT91C_TC_BSWTRG EQU( 0x3 << 30 ); + -( TC ) Software Trigger Effect on TIOB + AT91C_TC_BSWTRG_NONE EQU( 0x0 << 30 ); + -( TC ) Effect:none + AT91C_TC_BSWTRG_SET EQU( 0x1 << 30 ); + -( TC ) Effect:set + AT91C_TC_BSWTRG_CLEAR EQU( 0x2 << 30 ); + -( TC ) Effect:clear + AT91C_TC_BSWTRG_TOGGLE EQU( 0x3 << 30 ); + -( TC ) Effect:toggle +/* - -------- TC_SR : (TC Offset: 0x20) TC Channel Status Register -------- */ + AT91C_TC_COVFS EQU( 0x1 << 0 ); + -( TC ) Counter Overflow + AT91C_TC_LOVRS EQU( 0x1 << 1 ); + -( TC ) Load Overrun + AT91C_TC_CPAS EQU( 0x1 << 2 ); + -( TC ) RA Compare + AT91C_TC_CPBS EQU( 0x1 << 3 ); + -( TC ) RB Compare + AT91C_TC_CPCS EQU( 0x1 << 4 ); + -( TC ) RC Compare + AT91C_TC_LDRAS EQU( 0x1 << 5 ); + -( TC ) RA Loading + AT91C_TC_LDRBS EQU( 0x1 << 6 ); + -( TC ) RB Loading + AT91C_TC_ETRGS EQU( 0x1 << 7 ); + -( TC ) External Trigger + AT91C_TC_CLKSTA EQU( 0x1 << 16 ); + -( TC ) Clock Enabling + AT91C_TC_MTIOA EQU( 0x1 << 17 ); + -( TC ) TIOA Mirror + AT91C_TC_MTIOB EQU( 0x1 << 18 ); + -( TC ) TIOA Mirror +/* - -------- TC_IER : (TC Offset: 0x24) TC Channel Interrupt Enable Register -------- */ +/* - -------- TC_IDR : (TC Offset: 0x28) TC Channel Interrupt Disable Register -------- */ +/* - -------- TC_IMR : (TC Offset: 0x2c) TC Channel Interrupt Mask Register -------- */ -// - ***************************************************************************** -// - PERIPHERAL ID DEFINITIONS FOR AT91SAM7X256 -// - ***************************************************************************** -AT91C_ID_FIQ EQU ( 0) ;- Advanced Interrupt Controller (FIQ) -AT91C_ID_SYS EQU ( 1) ;- System Peripheral -AT91C_ID_PIOA EQU ( 2) ;- Parallel IO Controller A -AT91C_ID_PIOB EQU ( 3) ;- Parallel IO Controller B -AT91C_ID_SPI0 EQU ( 4) ;- Serial Peripheral Interface 0 -AT91C_ID_SPI1 EQU ( 5) ;- Serial Peripheral Interface 1 -AT91C_ID_US0 EQU ( 6) ;- USART 0 -AT91C_ID_US1 EQU ( 7) ;- USART 1 -AT91C_ID_SSC EQU ( 8) ;- Serial Synchronous Controller -AT91C_ID_TWI EQU ( 9) ;- Two-Wire Interface -AT91C_ID_PWMC EQU (10) ;- PWM Controller -AT91C_ID_UDP EQU (11) ;- USB Device Port -AT91C_ID_TC0 EQU (12) ;- Timer Counter 0 -AT91C_ID_TC1 EQU (13) ;- Timer Counter 1 -AT91C_ID_TC2 EQU (14) ;- Timer Counter 2 -AT91C_ID_CAN EQU (15) ;- Control Area Network Controller -AT91C_ID_EMAC EQU (16) ;- Ethernet MAC -AT91C_ID_ADC EQU (17) ;- Analog-to-Digital Converter -AT91C_ID_AES EQU (18) ;- Advanced Encryption Standard 128-bit -AT91C_ID_TDES EQU (19) ;- Triple Data Encryption Standard -AT91C_ID_20_Reserved EQU (20) ;- Reserved -AT91C_ID_21_Reserved EQU (21) ;- Reserved -AT91C_ID_22_Reserved EQU (22) ;- Reserved -AT91C_ID_23_Reserved EQU (23) ;- Reserved -AT91C_ID_24_Reserved EQU (24) ;- Reserved -AT91C_ID_25_Reserved EQU (25) ;- Reserved -AT91C_ID_26_Reserved EQU (26) ;- Reserved -AT91C_ID_27_Reserved EQU (27) ;- Reserved -AT91C_ID_28_Reserved EQU (28) ;- Reserved -AT91C_ID_29_Reserved EQU (29) ;- Reserved -AT91C_ID_IRQ0 EQU (30) ;- Advanced Interrupt Controller (IRQ0) -AT91C_ID_IRQ1 EQU (31) ;- Advanced Interrupt Controller (IRQ1) +/* - ***************************************************************************** */ +/* - SOFTWARE API DEFINITION FOR Timer Counter Interface */ +/* - ***************************************************************************** */ +/* - -------- TCB_BCR : (TCB Offset: 0xc0) TC Block Control Register -------- */ + AT91C_TCB_SYNC EQU( 0x1 << 0 ); + -( TCB ) Synchro Command +/* - -------- TCB_BMR : (TCB Offset: 0xc4) TC Block Mode Register -------- */ + AT91C_TCB_TC0XC0S EQU( 0x3 << 0 ); + -( TCB ) External Clock Signal 0 Selection + AT91C_TCB_TC0XC0S_TCLK0 EQU( 0x0 ); + -( TCB ) TCLK0 connected to XC0 + AT91C_TCB_TC0XC0S_NONE EQU( 0x1 ); + -( TCB ) None signal connected to XC0 + AT91C_TCB_TC0XC0S_TIOA1 EQU( 0x2 ); + -( TCB ) TIOA1 connected to XC0 + AT91C_TCB_TC0XC0S_TIOA2 EQU( 0x3 ); + -( TCB ) TIOA2 connected to XC0 + AT91C_TCB_TC1XC1S EQU( 0x3 << 2 ); + -( TCB ) External Clock Signal 1 Selection + AT91C_TCB_TC1XC1S_TCLK1 EQU( 0x0 << 2 ); + -( TCB ) TCLK1 connected to XC1 + AT91C_TCB_TC1XC1S_NONE EQU( 0x1 << 2 ); + -( TCB ) None signal connected to XC1 + AT91C_TCB_TC1XC1S_TIOA0 EQU( 0x2 << 2 ); + -( TCB ) TIOA0 connected to XC1 + AT91C_TCB_TC1XC1S_TIOA2 EQU( 0x3 << 2 ); + -( TCB ) TIOA2 connected to XC1 + AT91C_TCB_TC2XC2S EQU( 0x3 << 4 ); + -( TCB ) External Clock Signal 2 Selection + AT91C_TCB_TC2XC2S_TCLK2 EQU( 0x0 << 4 ); + -( TCB ) TCLK2 connected to XC2 + AT91C_TCB_TC2XC2S_NONE EQU( 0x1 << 4 ); + -( TCB ) None signal connected to XC2 + AT91C_TCB_TC2XC2S_TIOA0 EQU( 0x2 << 4 ); + -( TCB ) TIOA0 connected to XC2 + AT91C_TCB_TC2XC2S_TIOA1 EQU( 0x3 << 4 ); + -( TCB ) TIOA2 connected to XC2 -// - ***************************************************************************** -// - BASE ADDRESS DEFINITIONS FOR AT91SAM7X256 -// - ***************************************************************************** -AT91C_BASE_SYS EQU (0xFFFFF000) ;- (SYS) Base Address -AT91C_BASE_AIC EQU (0xFFFFF000) ;- (AIC) Base Address -AT91C_BASE_PDC_DBGU EQU (0xFFFFF300) ;- (PDC_DBGU) Base Address -AT91C_BASE_DBGU EQU (0xFFFFF200) ;- (DBGU) Base Address -AT91C_BASE_PIOA EQU (0xFFFFF400) ;- (PIOA) Base Address -AT91C_BASE_PIOB EQU (0xFFFFF600) ;- (PIOB) Base Address -AT91C_BASE_CKGR EQU (0xFFFFFC20) ;- (CKGR) Base Address -AT91C_BASE_PMC EQU (0xFFFFFC00) ;- (PMC) Base Address -AT91C_BASE_RSTC EQU (0xFFFFFD00) ;- (RSTC) Base Address -AT91C_BASE_RTTC EQU (0xFFFFFD20) ;- (RTTC) Base Address -AT91C_BASE_PITC EQU (0xFFFFFD30) ;- (PITC) Base Address -AT91C_BASE_WDTC EQU (0xFFFFFD40) ;- (WDTC) Base Address -AT91C_BASE_VREG EQU (0xFFFFFD60) ;- (VREG) Base Address -AT91C_BASE_MC EQU (0xFFFFFF00) ;- (MC) Base Address -AT91C_BASE_PDC_SPI1 EQU (0xFFFE4100) ;- (PDC_SPI1) Base Address -AT91C_BASE_SPI1 EQU (0xFFFE4000) ;- (SPI1) Base Address -AT91C_BASE_PDC_SPI0 EQU (0xFFFE0100) ;- (PDC_SPI0) Base Address -AT91C_BASE_SPI0 EQU (0xFFFE0000) ;- (SPI0) Base Address -AT91C_BASE_PDC_US1 EQU (0xFFFC4100) ;- (PDC_US1) Base Address -AT91C_BASE_US1 EQU (0xFFFC4000) ;- (US1) Base Address -AT91C_BASE_PDC_US0 EQU (0xFFFC0100) ;- (PDC_US0) Base Address -AT91C_BASE_US0 EQU (0xFFFC0000) ;- (US0) Base Address -AT91C_BASE_PDC_SSC EQU (0xFFFD4100) ;- (PDC_SSC) Base Address -AT91C_BASE_SSC EQU (0xFFFD4000) ;- (SSC) Base Address -AT91C_BASE_TWI EQU (0xFFFB8000) ;- (TWI) Base Address -AT91C_BASE_PWMC_CH3 EQU (0xFFFCC260) ;- (PWMC_CH3) Base Address -AT91C_BASE_PWMC_CH2 EQU (0xFFFCC240) ;- (PWMC_CH2) Base Address -AT91C_BASE_PWMC_CH1 EQU (0xFFFCC220) ;- (PWMC_CH1) Base Address -AT91C_BASE_PWMC_CH0 EQU (0xFFFCC200) ;- (PWMC_CH0) Base Address -AT91C_BASE_PWMC EQU (0xFFFCC000) ;- (PWMC) Base Address -AT91C_BASE_UDP EQU (0xFFFB0000) ;- (UDP) Base Address -AT91C_BASE_TC0 EQU (0xFFFA0000) ;- (TC0) Base Address -AT91C_BASE_TC1 EQU (0xFFFA0040) ;- (TC1) Base Address -AT91C_BASE_TC2 EQU (0xFFFA0080) ;- (TC2) Base Address -AT91C_BASE_TCB EQU (0xFFFA0000) ;- (TCB) Base Address -AT91C_BASE_CAN_MB0 EQU (0xFFFD0200) ;- (CAN_MB0) Base Address -AT91C_BASE_CAN_MB1 EQU (0xFFFD0220) ;- (CAN_MB1) Base Address -AT91C_BASE_CAN_MB2 EQU (0xFFFD0240) ;- (CAN_MB2) Base Address -AT91C_BASE_CAN_MB3 EQU (0xFFFD0260) ;- (CAN_MB3) Base Address -AT91C_BASE_CAN_MB4 EQU (0xFFFD0280) ;- (CAN_MB4) Base Address -AT91C_BASE_CAN_MB5 EQU (0xFFFD02A0) ;- (CAN_MB5) Base Address -AT91C_BASE_CAN_MB6 EQU (0xFFFD02C0) ;- (CAN_MB6) Base Address -AT91C_BASE_CAN_MB7 EQU (0xFFFD02E0) ;- (CAN_MB7) Base Address -AT91C_BASE_CAN EQU (0xFFFD0000) ;- (CAN) Base Address -AT91C_BASE_EMAC EQU (0xFFFDC000) ;- (EMAC) Base Address -AT91C_BASE_PDC_ADC EQU (0xFFFD8100) ;- (PDC_ADC) Base Address -AT91C_BASE_ADC EQU (0xFFFD8000) ;- (ADC) Base Address -AT91C_BASE_PDC_AES EQU (0xFFFA4100) ;- (PDC_AES) Base Address -AT91C_BASE_AES EQU (0xFFFA4000) ;- (AES) Base Address -AT91C_BASE_PDC_TDES EQU (0xFFFA8100) ;- (PDC_TDES) Base Address -AT91C_BASE_TDES EQU (0xFFFA8000) ;- (TDES) Base Address +/* - ***************************************************************************** */ +/* - SOFTWARE API DEFINITION FOR Control Area Network MailBox Interface */ +/* - ***************************************************************************** */ +/* - -------- CAN_MMR : (CAN_MB Offset: 0x0) CAN Message Mode Register -------- */ + AT91C_CAN_MTIMEMARK EQU( 0xFFFF << 0 ); + -( CAN_MB ) Mailbox Timemark + AT91C_CAN_PRIOR EQU( 0xF << 16 ); + -( CAN_MB ) Mailbox Priority + AT91C_CAN_MOT EQU( 0x7 << 24 ); + -( CAN_MB ) Mailbox Object Type + AT91C_CAN_MOT_DIS EQU( 0x0 << 24 ); + -( CAN_MB ) + AT91C_CAN_MOT_RX EQU( 0x1 << 24 ); + -( CAN_MB ) + AT91C_CAN_MOT_RXOVERWRITE EQU( 0x2 << 24 ); + -( CAN_MB ) + AT91C_CAN_MOT_TX EQU( 0x3 << 24 ); + -( CAN_MB ) + AT91C_CAN_MOT_CONSUMER EQU( 0x4 << 24 ); + -( CAN_MB ) + AT91C_CAN_MOT_PRODUCER EQU( 0x5 << 24 ); + -( CAN_MB ) +/* - -------- CAN_MAM : (CAN_MB Offset: 0x4) CAN Message Acceptance Mask Register -------- */ + AT91C_CAN_MIDvB EQU( 0x3FFFF << 0 ); + -( CAN_MB ) Complementary bits -// - ***************************************************************************** -// - MEMORY MAPPING DEFINITIONS FOR AT91SAM7X256 -// - ***************************************************************************** -AT91C_ISRAM EQU (0x00200000) ;- Internal SRAM base address -AT91C_ISRAM_SIZE EQU (0x00010000) ;- Internal SRAM size in byte (64 Kbyte) -AT91C_IFLASH EQU (0x00100000) ;- Internal ROM base address -AT91C_IFLASH_SIZE EQU (0x00040000) ;- Internal ROM size in byte (256 Kbyte) + for identifier in extended mode + AT91C_CAN_MIDvA EQU( 0x7FF << 18 ); + -( CAN_MB ) Identifier + + for standard frame mode + AT91C_CAN_MIDE EQU( 0x1 << 29 ); + -( CAN_MB ) Identifier Version +/* - -------- CAN_MID : (CAN_MB Offset: 0x8) CAN Message ID Register -------- */ +/* - -------- CAN_MFID : (CAN_MB Offset: 0xc) CAN Message Family ID Register -------- */ +/* - -------- CAN_MSR : (CAN_MB Offset: 0x10) CAN Message Status Register -------- */ + AT91C_CAN_MTIMESTAMP EQU( 0xFFFF << 0 ); + -( CAN_MB ) Timer Value + AT91C_CAN_MDLC EQU( 0xF << 16 ); + -( CAN_MB ) Mailbox Data Length Code + AT91C_CAN_MRTR EQU( 0x1 << 20 ); + -( CAN_MB ) Mailbox Remote Transmission Request + AT91C_CAN_MABT EQU( 0x1 << 22 ); + -( CAN_MB ) Mailbox Message Abort + AT91C_CAN_MRDY EQU( 0x1 << 23 ); + -( CAN_MB ) Mailbox Ready + AT91C_CAN_MMI EQU( 0x1 << 24 ); + -( CAN_MB ) Mailbox Message Ignored +/* - -------- CAN_MDL : (CAN_MB Offset: 0x14) CAN Message Data Low Register -------- */ +/* - -------- CAN_MDH : (CAN_MB Offset: 0x18) CAN Message Data High Register -------- */ +/* - -------- CAN_MCR : (CAN_MB Offset: 0x1c) CAN Message Control Register -------- */ + AT91C_CAN_MACR EQU( 0x1 << 22 ); + -( CAN_MB ) Abort Request + + for Mailbox + AT91C_CAN_MTCR EQU( 0x1 << 23 ); + -( CAN_MB ) Mailbox Transfer Command + +/* - ***************************************************************************** */ +/* - SOFTWARE API DEFINITION FOR Control Area Network Interface */ +/* - ***************************************************************************** */ +/* - -------- CAN_MR : (CAN Offset: 0x0) CAN Mode Register -------- */ + AT91C_CAN_CANEN EQU( 0x1 << 0 ); + -( CAN ) CAN Controller Enable + AT91C_CAN_LPM EQU( 0x1 << 1 ); + -( CAN ) Disable / Enable Low Power Mode + AT91C_CAN_ABM EQU( 0x1 << 2 ); + -( CAN ) Disable / Enable Autobaud / Listen Mode + AT91C_CAN_OVL EQU( 0x1 << 3 ); + -( CAN ) Disable / Enable Overload Frame + AT91C_CAN_TEOF EQU( 0x1 << 4 ); + -( CAN ) Time Stamp messages at each end of Frame + AT91C_CAN_TTM EQU( 0x1 << 5 ); + -( CAN ) Disable / Enable Time Trigger Mode + AT91C_CAN_TIMFRZ EQU( 0x1 << 6 ); + -( CAN ) Enable Timer Freeze + AT91C_CAN_DRPT EQU( 0x1 << 7 ); + -( CAN ) Disable Repeat +/* - -------- CAN_IER : (CAN Offset: 0x4) CAN Interrupt Enable Register -------- */ + AT91C_CAN_MB0 EQU( 0x1 << 0 ); + -( CAN ) Mailbox 0 Flag + AT91C_CAN_MB1 EQU( 0x1 << 1 ); + -( CAN ) Mailbox 1 Flag + AT91C_CAN_MB2 EQU( 0x1 << 2 ); + -( CAN ) Mailbox 2 Flag + AT91C_CAN_MB3 EQU( 0x1 << 3 ); + -( CAN ) Mailbox 3 Flag + AT91C_CAN_MB4 EQU( 0x1 << 4 ); + -( CAN ) Mailbox 4 Flag + AT91C_CAN_MB5 EQU( 0x1 << 5 ); + -( CAN ) Mailbox 5 Flag + AT91C_CAN_MB6 EQU( 0x1 << 6 ); + -( CAN ) Mailbox 6 Flag + AT91C_CAN_MB7 EQU( 0x1 << 7 ); + -( CAN ) Mailbox 7 Flag + AT91C_CAN_MB8 EQU( 0x1 << 8 ); + -( CAN ) Mailbox 8 Flag + AT91C_CAN_MB9 EQU( 0x1 << 9 ); + -( CAN ) Mailbox 9 Flag + AT91C_CAN_MB10 EQU( 0x1 << 10 ); + -( CAN ) Mailbox 10 Flag + AT91C_CAN_MB11 EQU( 0x1 << 11 ); + -( CAN ) Mailbox 11 Flag + AT91C_CAN_MB12 EQU( 0x1 << 12 ); + -( CAN ) Mailbox 12 Flag + AT91C_CAN_MB13 EQU( 0x1 << 13 ); + -( CAN ) Mailbox 13 Flag + AT91C_CAN_MB14 EQU( 0x1 << 14 ); + -( CAN ) Mailbox 14 Flag + AT91C_CAN_MB15 EQU( 0x1 << 15 ); + -( CAN ) Mailbox 15 Flag + AT91C_CAN_ERRA EQU( 0x1 << 16 ); + -( CAN ) Error Active Mode Flag + AT91C_CAN_WARN EQU( 0x1 << 17 ); + -( CAN ) Warning Limit Flag + AT91C_CAN_ERRP EQU( 0x1 << 18 ); + -( CAN ) Error Passive Mode Flag + AT91C_CAN_BOFF EQU( 0x1 << 19 ); + -( CAN ) Bus Off Mode Flag + AT91C_CAN_SLEEP EQU( 0x1 << 20 ); + -( CAN ) Sleep Flag + AT91C_CAN_WAKEUP EQU( 0x1 << 21 ); + -( CAN ) Wakeup Flag + AT91C_CAN_TOVF EQU( 0x1 << 22 ); + -( CAN ) Timer Overflow Flag + AT91C_CAN_TSTP EQU( 0x1 << 23 ); + -( CAN ) Timestamp Flag + AT91C_CAN_CERR EQU( 0x1 << 24 ); + -( CAN ) CRC Error + AT91C_CAN_SERR EQU( 0x1 << 25 ); + -( CAN ) Stuffing Error + AT91C_CAN_AERR EQU( 0x1 << 26 ); + -( CAN ) Acknowledgment Error + AT91C_CAN_FERR EQU( 0x1 << 27 ); + -( CAN ) Form Error + AT91C_CAN_BERR EQU( 0x1 << 28 ); + -( CAN ) Bit Error +/* - -------- CAN_IDR : (CAN Offset: 0x8) CAN Interrupt Disable Register -------- */ +/* - -------- CAN_IMR : (CAN Offset: 0xc) CAN Interrupt Mask Register -------- */ +/* - -------- CAN_SR : (CAN Offset: 0x10) CAN Status Register -------- */ + AT91C_CAN_RBSY EQU( 0x1 << 29 ); + -( CAN ) Receiver Busy + AT91C_CAN_TBSY EQU( 0x1 << 30 ); + -( CAN ) Transmitter Busy + AT91C_CAN_OVLY EQU( 0x1 << 31 ); + -( CAN ) Overload Busy +/* - -------- CAN_BR : (CAN Offset: 0x14) CAN Baudrate Register -------- */ + AT91C_CAN_PHASE2 EQU( 0x7 << 0 ); + -( CAN ) Phase 2 segment + AT91C_CAN_PHASE1 EQU( 0x7 << 4 ); + -( CAN ) Phase 1 segment + AT91C_CAN_PROPAG EQU( 0x7 << 8 ); + -( CAN ) Programmation time segment + AT91C_CAN_SYNC EQU( 0x3 << 12 ); + -( CAN ) Re - synchronization jump width segment + AT91C_CAN_BRP EQU( 0x7F << 16 ); + -( CAN ) Baudrate Prescaler + AT91C_CAN_SMP EQU( 0x1 << 24 ); + -( CAN ) Sampling mode +/* - -------- CAN_TIM : (CAN Offset: 0x18) CAN Timer Register -------- */ + AT91C_CAN_TIMER EQU( 0xFFFF << 0 ); + -( CAN ) Timer field +/* - -------- CAN_TIMESTP : (CAN Offset: 0x1c) CAN Timestamp Register -------- */ +/* - -------- CAN_ECR : (CAN Offset: 0x20) CAN Error Counter Register -------- */ + AT91C_CAN_REC EQU( 0xFF << 0 ); + -( CAN ) Receive Error Counter + AT91C_CAN_TEC EQU( 0xFF << 16 ); + -( CAN ) Transmit Error Counter +/* - -------- CAN_TCR : (CAN Offset: 0x24) CAN Transfer Command Register -------- */ + AT91C_CAN_TIMRST EQU( 0x1 << 31 ); + -( CAN ) Timer Reset Field +/* - -------- CAN_ACR : (CAN Offset: 0x28) CAN Abort Command Register -------- */ + +/* - ***************************************************************************** */ +/* - SOFTWARE API DEFINITION FOR Ethernet MAC 10/100 */ +/* - ***************************************************************************** */ +/* - -------- EMAC_NCR : (EMAC Offset: 0x0) -------- */ + AT91C_EMAC_LB EQU( 0x1 << 0 ); + -( EMAC ) Loopback.Optional.When set, loopback signal is at high level. + AT91C_EMAC_LLB EQU( 0x1 << 1 ); + -( EMAC ) Loopback local. + AT91C_EMAC_RE EQU( 0x1 << 2 ); + -( EMAC ) Receive enable. + AT91C_EMAC_TE EQU( 0x1 << 3 ); + -( EMAC ) Transmit enable. + AT91C_EMAC_MPE EQU( 0x1 << 4 ); + -( EMAC ) Management port enable. + AT91C_EMAC_CLRSTAT EQU( 0x1 << 5 ); + -( EMAC ) Clear statistics registers. + AT91C_EMAC_INCSTAT EQU( 0x1 << 6 ); + -( EMAC ) Increment statistics registers. + AT91C_EMAC_WESTAT EQU( 0x1 << 7 ); + -( EMAC ) Write enable + + for statistics registers. + AT91C_EMAC_BP EQU( 0x1 << 8 ); + -( EMAC ) Back pressure. + AT91C_EMAC_TSTART EQU( 0x1 << 9 ); + -( EMAC ) Start Transmission. + AT91C_EMAC_THALT EQU( 0x1 << 10 ); + -( EMAC ) Transmission Halt. + AT91C_EMAC_TPFR EQU( 0x1 << 11 ); + -( EMAC ) Transmit pause frame + AT91C_EMAC_TZQ EQU( 0x1 << 12 ); + -( EMAC ) Transmit zero quantum pause frame +/* - -------- EMAC_NCFGR : (EMAC Offset: 0x4) Network Configuration Register -------- */ + AT91C_EMAC_SPD EQU( 0x1 << 0 ); + -( EMAC ) Speed. + AT91C_EMAC_FD EQU( 0x1 << 1 ); + -( EMAC ) Full duplex. + AT91C_EMAC_JFRAME EQU( 0x1 << 3 ); + -( EMAC ) Jumbo Frames. + AT91C_EMAC_CAF EQU( 0x1 << 4 ); + -( EMAC ) Copy all frames. + AT91C_EMAC_NBC EQU( 0x1 << 5 ); + -( EMAC ) No broadcast. + AT91C_EMAC_MTI EQU( 0x1 << 6 ); + -( EMAC ) Multicast hash event enable + AT91C_EMAC_UNI EQU( 0x1 << 7 ); + -( EMAC ) Unicast hash enable. + AT91C_EMAC_BIG EQU( 0x1 << 8 ); + -( EMAC ) Receive 1522 bytes. + AT91C_EMAC_EAE EQU( 0x1 << 9 ); + -( EMAC ) External address match enable. + AT91C_EMAC_CLK EQU( 0x3 << 10 ); + -( EMAC ) + AT91C_EMAC_CLK_HCLK_8 EQU( 0x0 << 10 ); + -( EMAC ) HCLK divided by 8 + AT91C_EMAC_CLK_HCLK_16 EQU( 0x1 << 10 ); + -( EMAC ) HCLK divided by 16 + AT91C_EMAC_CLK_HCLK_32 EQU( 0x2 << 10 ); + -( EMAC ) HCLK divided by 32 + AT91C_EMAC_CLK_HCLK_64 EQU( 0x3 << 10 ); + -( EMAC ) HCLK divided by 64 + AT91C_EMAC_RTY EQU( 0x1 << 12 ); + -( EMAC ) + AT91C_EMAC_PAE EQU( 0x1 << 13 ); + -( EMAC ) + AT91C_EMAC_RBOF EQU( 0x3 << 14 ); + -( EMAC ) + AT91C_EMAC_RBOF_OFFSET_0 EQU( 0x0 << 14 ); + -( EMAC ) no offset from start of receive buffer + AT91C_EMAC_RBOF_OFFSET_1 EQU( 0x1 << 14 ); + -( EMAC ) one byte offset from start of receive buffer + AT91C_EMAC_RBOF_OFFSET_2 EQU( 0x2 << 14 ); + -( EMAC ) two bytes offset from start of receive buffer + AT91C_EMAC_RBOF_OFFSET_3 EQU( 0x3 << 14 ); + -( EMAC ) three bytes offset from start of receive buffer + AT91C_EMAC_RLCE EQU( 0x1 << 16 ); + -( EMAC ) Receive Length field Checking Enable + AT91C_EMAC_DRFCS EQU( 0x1 << 17 ); + -( EMAC ) Discard Receive FCS + AT91C_EMAC_EFRHD EQU( 0x1 << 18 ); + -( EMAC ) + AT91C_EMAC_IRXFCS EQU( 0x1 << 19 ); + -( EMAC ) Ignore RX FCS +/* - -------- EMAC_NSR : (EMAC Offset: 0x8) Network Status Register -------- */ + AT91C_EMAC_LINKR EQU( 0x1 << 0 ); + -( EMAC ) + AT91C_EMAC_MDIO EQU( 0x1 << 1 ); + -( EMAC ) + AT91C_EMAC_IDLE EQU( 0x1 << 2 ); + -( EMAC ) +/* - -------- EMAC_TSR : (EMAC Offset: 0x14) Transmit Status Register -------- */ + AT91C_EMAC_UBR EQU( 0x1 << 0 ); + -( EMAC ) + AT91C_EMAC_COL EQU( 0x1 << 1 ); + -( EMAC ) + AT91C_EMAC_RLES EQU( 0x1 << 2 ); + -( EMAC ) + AT91C_EMAC_TGO EQU( 0x1 << 3 ); + -( EMAC ) Transmit Go + AT91C_EMAC_BEX EQU( 0x1 << 4 ); + -( EMAC ) Buffers exhausted mid frame + AT91C_EMAC_COMP EQU( 0x1 << 5 ); + -( EMAC ) + AT91C_EMAC_UND EQU( 0x1 << 6 ); + -( EMAC ) +/* - -------- EMAC_RSR : (EMAC Offset: 0x20) Receive Status Register -------- */ + AT91C_EMAC_BNA EQU( 0x1 << 0 ); + -( EMAC ) + AT91C_EMAC_REC EQU( 0x1 << 1 ); + -( EMAC ) + AT91C_EMAC_OVR EQU( 0x1 << 2 ); + -( EMAC ) +/* - -------- EMAC_ISR : (EMAC Offset: 0x24) Interrupt Status Register -------- */ + AT91C_EMAC_MFD EQU( 0x1 << 0 ); + -( EMAC ) + AT91C_EMAC_RCOMP EQU( 0x1 << 1 ); + -( EMAC ) + AT91C_EMAC_RXUBR EQU( 0x1 << 2 ); + -( EMAC ) + AT91C_EMAC_TXUBR EQU( 0x1 << 3 ); + -( EMAC ) + AT91C_EMAC_TUNDR EQU( 0x1 << 4 ); + -( EMAC ) + AT91C_EMAC_RLEX EQU( 0x1 << 5 ); + -( EMAC ) + AT91C_EMAC_TXERR EQU( 0x1 << 6 ); + -( EMAC ) + AT91C_EMAC_TCOMP EQU( 0x1 << 7 ); + -( EMAC ) + AT91C_EMAC_LINK EQU( 0x1 << 9 ); + -( EMAC ) + AT91C_EMAC_ROVR EQU( 0x1 << 10 ); + -( EMAC ) + AT91C_EMAC_HRESP EQU( 0x1 << 11 ); + -( EMAC ) + AT91C_EMAC_PFRE EQU( 0x1 << 12 ); + -( EMAC ) + AT91C_EMAC_PTZ EQU( 0x1 << 13 ); + -( EMAC ) +/* - -------- EMAC_IER : (EMAC Offset: 0x28) Interrupt Enable Register -------- */ +/* - -------- EMAC_IDR : (EMAC Offset: 0x2c) Interrupt Disable Register -------- */ +/* - -------- EMAC_IMR : (EMAC Offset: 0x30) Interrupt Mask Register -------- */ +/* - -------- EMAC_MAN : (EMAC Offset: 0x34) PHY Maintenance Register -------- */ + AT91C_EMAC_DATA EQU( 0xFFFF << 0 ); + -( EMAC ) + AT91C_EMAC_CODE EQU( 0x3 << 16 ); + -( EMAC ) + AT91C_EMAC_REGA EQU( 0x1F << 18 ); + -( EMAC ) + AT91C_EMAC_PHYA EQU( 0x1F << 23 ); + -( EMAC ) + AT91C_EMAC_RW EQU( 0x3 << 28 ); + -( EMAC ) + AT91C_EMAC_SOF EQU( 0x3 << 30 ); + -( EMAC ) +/* - -------- EMAC_USRIO : (EMAC Offset: 0xc0) USER Input Output Register -------- */ + AT91C_EMAC_RMII EQU( 0x1 << 0 ); + -( EMAC ) Reduce MII +/* - -------- EMAC_WOL : (EMAC Offset: 0xc4) Wake On LAN Register -------- */ + AT91C_EMAC_IP EQU( 0xFFFF << 0 ); + -( EMAC ) ARP request IP address + AT91C_EMAC_MAG EQU( 0x1 << 16 ); + -( EMAC ) Magic packet event enable + AT91C_EMAC_ARP EQU( 0x1 << 17 ); + -( EMAC ) ARP request event enable + AT91C_EMAC_SA1 EQU( 0x1 << 18 ); + -( EMAC ) Specific address register 1 event enable +/* - -------- EMAC_REV : (EMAC Offset: 0xfc) Revision Register -------- */ + AT91C_EMAC_REVREF EQU( 0xFFFF << 0 ); + -( EMAC ) + AT91C_EMAC_PARTREF EQU( 0xFFFF << 16 ); + -( EMAC ) + +/* - ***************************************************************************** */ +/* - SOFTWARE API DEFINITION FOR Analog to Digital Convertor */ +/* - ***************************************************************************** */ +/* - -------- ADC_CR : (ADC Offset: 0x0) ADC Control Register -------- */ + AT91C_ADC_SWRST EQU( 0x1 << 0 ); + -( ADC ) Software Reset + AT91C_ADC_START EQU( 0x1 << 1 ); + -( ADC ) Start Conversion +/* - -------- ADC_MR : (ADC Offset: 0x4) ADC Mode Register -------- */ + AT91C_ADC_TRGEN EQU( 0x1 << 0 ); + -( ADC ) Trigger Enable + AT91C_ADC_TRGEN_DIS EQU( 0x0 ); + -( ADC ) Hardware triggers are disabled.Starting a conversion is only possible by software + AT91C_ADC_TRGEN_EN EQU( 0x1 ); + -( ADC ) Hardware trigger selected by TRGSEL field is enabled. + AT91C_ADC_TRGSEL EQU( 0x7 << 1 ); + -( ADC ) Trigger Selection + AT91C_ADC_TRGSEL_TIOA0 EQU( 0x0 << 1 ); + -( ADC ) Selected TRGSEL = TIAO0 + AT91C_ADC_TRGSEL_TIOA1 EQU( 0x1 << 1 ); + -( ADC ) Selected TRGSEL = TIAO1 + AT91C_ADC_TRGSEL_TIOA2 EQU( 0x2 << 1 ); + -( ADC ) Selected TRGSEL = TIAO2 + AT91C_ADC_TRGSEL_TIOA3 EQU( 0x3 << 1 ); + -( ADC ) Selected TRGSEL = TIAO3 + AT91C_ADC_TRGSEL_TIOA4 EQU( 0x4 << 1 ); + -( ADC ) Selected TRGSEL = TIAO4 + AT91C_ADC_TRGSEL_TIOA5 EQU( 0x5 << 1 ); + -( ADC ) Selected TRGSEL = TIAO5 + AT91C_ADC_TRGSEL_EXT EQU( 0x6 << 1 ); + -( ADC ) Selected TRGSEL = External Trigger + AT91C_ADC_LOWRES EQU( 0x1 << 4 ); + -( ADC ) Resolution. + AT91C_ADC_LOWRES_10_BIT EQU( 0x0 << 4 ); + -( ADC ) 10 - bit resolution + AT91C_ADC_LOWRES_8_BIT EQU( 0x1 << 4 ); + -( ADC ) 8 - bit resolution + AT91C_ADC_SLEEP EQU( 0x1 << 5 ); + -( ADC ) Sleep Mode + AT91C_ADC_SLEEP_NORMAL_MODE EQU( 0x0 << 5 ); + -( ADC ) Normal Mode + AT91C_ADC_SLEEP_MODE EQU( 0x1 << 5 ); + -( ADC ) Sleep Mode + AT91C_ADC_PRESCAL EQU( 0x3F << 8 ); + -( ADC ) Prescaler rate selection + AT91C_ADC_STARTUP EQU( 0x1F << 16 ); + -( ADC ) Startup Time + AT91C_ADC_SHTIM EQU( 0xF << 24 ); + -( ADC ) Sample & Hold Time +/* - -------- ADC_CHER : (ADC Offset: 0x10) ADC Channel Enable Register -------- */ + AT91C_ADC_CH0 EQU( 0x1 << 0 ); + -( ADC ) Channel 0 + AT91C_ADC_CH1 EQU( 0x1 << 1 ); + -( ADC ) Channel 1 + AT91C_ADC_CH2 EQU( 0x1 << 2 ); + -( ADC ) Channel 2 + AT91C_ADC_CH3 EQU( 0x1 << 3 ); + -( ADC ) Channel 3 + AT91C_ADC_CH4 EQU( 0x1 << 4 ); + -( ADC ) Channel 4 + AT91C_ADC_CH5 EQU( 0x1 << 5 ); + -( ADC ) Channel 5 + AT91C_ADC_CH6 EQU( 0x1 << 6 ); + -( ADC ) Channel 6 + AT91C_ADC_CH7 EQU( 0x1 << 7 ); + -( ADC ) Channel 7 +/* - -------- ADC_CHDR : (ADC Offset: 0x14) ADC Channel Disable Register -------- */ +/* - -------- ADC_CHSR : (ADC Offset: 0x18) ADC Channel Status Register -------- */ +/* - -------- ADC_SR : (ADC Offset: 0x1c) ADC Status Register -------- */ + AT91C_ADC_EOC0 EQU( 0x1 << 0 ); + -( ADC ) End of Conversion + AT91C_ADC_EOC1 EQU( 0x1 << 1 ); + -( ADC ) End of Conversion + AT91C_ADC_EOC2 EQU( 0x1 << 2 ); + -( ADC ) End of Conversion + AT91C_ADC_EOC3 EQU( 0x1 << 3 ); + -( ADC ) End of Conversion + AT91C_ADC_EOC4 EQU( 0x1 << 4 ); + -( ADC ) End of Conversion + AT91C_ADC_EOC5 EQU( 0x1 << 5 ); + -( ADC ) End of Conversion + AT91C_ADC_EOC6 EQU( 0x1 << 6 ); + -( ADC ) End of Conversion + AT91C_ADC_EOC7 EQU( 0x1 << 7 ); + -( ADC ) End of Conversion + AT91C_ADC_OVRE0 EQU( 0x1 << 8 ); + -( ADC ) Overrun Error + AT91C_ADC_OVRE1 EQU( 0x1 << 9 ); + -( ADC ) Overrun Error + AT91C_ADC_OVRE2 EQU( 0x1 << 10 ); + -( ADC ) Overrun Error + AT91C_ADC_OVRE3 EQU( 0x1 << 11 ); + -( ADC ) Overrun Error + AT91C_ADC_OVRE4 EQU( 0x1 << 12 ); + -( ADC ) Overrun Error + AT91C_ADC_OVRE5 EQU( 0x1 << 13 ); + -( ADC ) Overrun Error + AT91C_ADC_OVRE6 EQU( 0x1 << 14 ); + -( ADC ) Overrun Error + AT91C_ADC_OVRE7 EQU( 0x1 << 15 ); + -( ADC ) Overrun Error + AT91C_ADC_DRDY EQU( 0x1 << 16 ); + -( ADC ) Data Ready + AT91C_ADC_GOVRE EQU( 0x1 << 17 ); + -( ADC ) General Overrun + AT91C_ADC_ENDRX EQU( 0x1 << 18 ); + -( ADC ) End of Receiver Transfer + AT91C_ADC_RXBUFF EQU( 0x1 << 19 ); + -( ADC ) RXBUFF Interrupt +/* - -------- ADC_LCDR : (ADC Offset: 0x20) ADC Last Converted Data Register -------- */ + AT91C_ADC_LDATA EQU( 0x3FF << 0 ); + -( ADC ) Last Data Converted +/* - -------- ADC_IER : (ADC Offset: 0x24) ADC Interrupt Enable Register -------- */ +/* - -------- ADC_IDR : (ADC Offset: 0x28) ADC Interrupt Disable Register -------- */ +/* - -------- ADC_IMR : (ADC Offset: 0x2c) ADC Interrupt Mask Register -------- */ +/* - -------- ADC_CDR0 : (ADC Offset: 0x30) ADC Channel Data Register 0 -------- */ + AT91C_ADC_DATA EQU( 0x3FF << 0 ); + -( ADC ) Converted Data +/* - -------- ADC_CDR1 : (ADC Offset: 0x34) ADC Channel Data Register 1 -------- */ +/* - -------- ADC_CDR2 : (ADC Offset: 0x38) ADC Channel Data Register 2 -------- */ +/* - -------- ADC_CDR3 : (ADC Offset: 0x3c) ADC Channel Data Register 3 -------- */ +/* - -------- ADC_CDR4 : (ADC Offset: 0x40) ADC Channel Data Register 4 -------- */ +/* - -------- ADC_CDR5 : (ADC Offset: 0x44) ADC Channel Data Register 5 -------- */ +/* - -------- ADC_CDR6 : (ADC Offset: 0x48) ADC Channel Data Register 6 -------- */ +/* - -------- ADC_CDR7 : (ADC Offset: 0x4c) ADC Channel Data Register 7 -------- */ + +/* - ***************************************************************************** */ +/* - SOFTWARE API DEFINITION FOR Advanced Encryption Standard */ +/* - ***************************************************************************** */ +/* - -------- AES_CR : (AES Offset: 0x0) Control Register -------- */ + AT91C_AES_START EQU( 0x1 << 0 ); + -( AES ) Starts Processing + AT91C_AES_SWRST EQU( 0x1 << 8 ); + -( AES ) Software Reset + AT91C_AES_LOADSEED EQU( 0x1 << 16 ); + -( AES ) Random Number Generator Seed Loading +/* - -------- AES_MR : (AES Offset: 0x4) Mode Register -------- */ + AT91C_AES_CIPHER EQU( 0x1 << 0 ); + -( AES ) Processing Mode + AT91C_AES_PROCDLY EQU( 0xF << 4 ); + -( AES ) Processing Delay + AT91C_AES_SMOD EQU( 0x3 << 8 ); + -( AES ) Start Mode + AT91C_AES_SMOD_MANUAL EQU( 0x0 << 8 ); + -( AES ) Manual Mode:The START bit in register AES_CR must be set to begin encryption or decryption. + AT91C_AES_SMOD_AUTO EQU( 0x1 << 8 ); + -( AES ) Auto Mode:no action in AES_CR is necessary( cf datasheet ). + AT91C_AES_SMOD_PDC EQU( 0x2 << 8 ); + -( AES ) PDC Mode( cf datasheet ). + AT91C_AES_OPMOD EQU( 0x7 << 12 ); + -( AES ) Operation Mode + AT91C_AES_OPMOD_ECB EQU( 0x0 << 12 ); + -( AES ) ECB Electronic CodeBook mode. + AT91C_AES_OPMOD_CBC EQU( 0x1 << 12 ); + -( AES ) CBC Cipher Block Chaining mode. + AT91C_AES_OPMOD_OFB EQU( 0x2 << 12 ); + -( AES ) OFB Output Feedback mode. + AT91C_AES_OPMOD_CFB EQU( 0x3 << 12 ); + -( AES ) CFB Cipher Feedback mode. + AT91C_AES_OPMOD_CTR EQU( 0x4 << 12 ); + -( AES ) CTR Counter mode. + AT91C_AES_LOD EQU( 0x1 << 15 ); + -( AES ) Last Output Data Mode + AT91C_AES_CFBS EQU( 0x7 << 16 ); + -( AES ) Cipher Feedback Data Size + AT91C_AES_CFBS_128_BIT EQU( 0x0 << 16 ); + -( AES ) 128 - bit. + AT91C_AES_CFBS_64_BIT EQU( 0x1 << 16 ); + -( AES ) 64 - bit. + AT91C_AES_CFBS_32_BIT EQU( 0x2 << 16 ); + -( AES ) 32 - bit. + AT91C_AES_CFBS_16_BIT EQU( 0x3 << 16 ); + -( AES ) 16 - bit. + AT91C_AES_CFBS_8_BIT EQU( 0x4 << 16 ); + -( AES ) 8 - bit. + AT91C_AES_CKEY EQU( 0xF << 20 ); + -( AES ) Countermeasure Key + AT91C_AES_CTYPE EQU( 0x1F << 24 ); + -( AES ) Countermeasure Type + AT91C_AES_CTYPE_TYPE1_EN EQU( 0x1 << 24 ); + -( AES ) Countermeasure type 1 is enabled. + AT91C_AES_CTYPE_TYPE2_EN EQU( 0x2 << 24 ); + -( AES ) Countermeasure type 2 is enabled. + AT91C_AES_CTYPE_TYPE3_EN EQU( 0x4 << 24 ); + -( AES ) Countermeasure type 3 is enabled. + AT91C_AES_CTYPE_TYPE4_EN EQU( 0x8 << 24 ); + -( AES ) Countermeasure type 4 is enabled. + AT91C_AES_CTYPE_TYPE5_EN EQU( 0x10 << 24 ); + -( AES ) Countermeasure type 5 is enabled. +/* - -------- AES_IER : (AES Offset: 0x10) Interrupt Enable Register -------- */ + AT91C_AES_DATRDY EQU( 0x1 << 0 ); + -( AES ) DATRDY + AT91C_AES_ENDRX EQU( 0x1 << 1 ); + -( AES ) PDC Read Buffer End + AT91C_AES_ENDTX EQU( 0x1 << 2 ); + -( AES ) PDC Write Buffer End + AT91C_AES_RXBUFF EQU( 0x1 << 3 ); + -( AES ) PDC Read Buffer Full + AT91C_AES_TXBUFE EQU( 0x1 << 4 ); + -( AES ) PDC Write Buffer Empty + AT91C_AES_URAD EQU( 0x1 << 8 ); + -( AES ) Unspecified Register Access Detection +/* - -------- AES_IDR : (AES Offset: 0x14) Interrupt Disable Register -------- */ +/* - -------- AES_IMR : (AES Offset: 0x18) Interrupt Mask Register -------- */ +/* - -------- AES_ISR : (AES Offset: 0x1c) Interrupt Status Register -------- */ + AT91C_AES_URAT EQU( 0x7 << 12 ); + -( AES ) Unspecified Register Access Type Status + AT91C_AES_URAT_IN_DAT_WRITE_DATPROC EQU( 0x0 << 12 ); + -( AES ) Input data register written during the data processing in PDC mode. + AT91C_AES_URAT_OUT_DAT_READ_DATPROC EQU( 0x1 << 12 ); + -( AES ) Output data register read during the data processing. + AT91C_AES_URAT_MODEREG_WRITE_DATPROC EQU( 0x2 << 12 ); + -( AES ) Mode register written during the data processing. + AT91C_AES_URAT_OUT_DAT_READ_SUBKEY EQU( 0x3 << 12 ); + -( AES ) Output data register read during the sub - keys generation. + AT91C_AES_URAT_MODEREG_WRITE_SUBKEY EQU( 0x4 << 12 ); + -( AES ) Mode register written during the sub - keys generation. + AT91C_AES_URAT_WO_REG_READ EQU( 0x5 << 12 ); + -( AES ) Write - only register read access. + +/* - ***************************************************************************** */ +/* - SOFTWARE API DEFINITION FOR Triple Data Encryption Standard */ +/* - ***************************************************************************** */ +/* - -------- TDES_CR : (TDES Offset: 0x0) Control Register -------- */ + AT91C_TDES_START EQU( 0x1 << 0 ); + -( TDES ) Starts Processing + AT91C_TDES_SWRST EQU( 0x1 << 8 ); + -( TDES ) Software Reset +/* - -------- TDES_MR : (TDES Offset: 0x4) Mode Register -------- */ + AT91C_TDES_CIPHER EQU( 0x1 << 0 ); + -( TDES ) Processing Mode + AT91C_TDES_TDESMOD EQU( 0x1 << 1 ); + -( TDES ) Single or Triple DES Mode + AT91C_TDES_KEYMOD EQU( 0x1 << 4 ); + -( TDES ) Key Mode + AT91C_TDES_SMOD EQU( 0x3 << 8 ); + -( TDES ) Start Mode + AT91C_TDES_SMOD_MANUAL EQU( 0x0 << 8 ); + -( TDES ) Manual Mode:The START bit in register TDES_CR must be set to begin encryption or decryption. + AT91C_TDES_SMOD_AUTO EQU( 0x1 << 8 ); + -( TDES ) Auto Mode:no action in TDES_CR is necessary( cf datasheet ). + AT91C_TDES_SMOD_PDC EQU( 0x2 << 8 ); + -( TDES ) PDC Mode( cf datasheet ). + AT91C_TDES_OPMOD EQU( 0x3 << 12 ); + -( TDES ) Operation Mode + AT91C_TDES_OPMOD_ECB EQU( 0x0 << 12 ); + -( TDES ) ECB Electronic CodeBook mode. + AT91C_TDES_OPMOD_CBC EQU( 0x1 << 12 ); + -( TDES ) CBC Cipher Block Chaining mode. + AT91C_TDES_OPMOD_OFB EQU( 0x2 << 12 ); + -( TDES ) OFB Output Feedback mode. + AT91C_TDES_OPMOD_CFB EQU( 0x3 << 12 ); + -( TDES ) CFB Cipher Feedback mode. + AT91C_TDES_LOD EQU( 0x1 << 15 ); + -( TDES ) Last Output Data Mode + AT91C_TDES_CFBS EQU( 0x3 << 16 ); + -( TDES ) Cipher Feedback Data Size + AT91C_TDES_CFBS_64_BIT EQU( 0x0 << 16 ); + -( TDES ) 64 - bit. + AT91C_TDES_CFBS_32_BIT EQU( 0x1 << 16 ); + -( TDES ) 32 - bit. + AT91C_TDES_CFBS_16_BIT EQU( 0x2 << 16 ); + -( TDES ) 16 - bit. + AT91C_TDES_CFBS_8_BIT EQU( 0x3 << 16 ); + -( TDES ) 8 - bit. +/* - -------- TDES_IER : (TDES Offset: 0x10) Interrupt Enable Register -------- */ + AT91C_TDES_DATRDY EQU( 0x1 << 0 ); + -( TDES ) DATRDY + AT91C_TDES_ENDRX EQU( 0x1 << 1 ); + -( TDES ) PDC Read Buffer End + AT91C_TDES_ENDTX EQU( 0x1 << 2 ); + -( TDES ) PDC Write Buffer End + AT91C_TDES_RXBUFF EQU( 0x1 << 3 ); + -( TDES ) PDC Read Buffer Full + AT91C_TDES_TXBUFE EQU( 0x1 << 4 ); + -( TDES ) PDC Write Buffer Empty + AT91C_TDES_URAD EQU( 0x1 << 8 ); + -( TDES ) Unspecified Register Access Detection +/* - -------- TDES_IDR : (TDES Offset: 0x14) Interrupt Disable Register -------- */ +/* - -------- TDES_IMR : (TDES Offset: 0x18) Interrupt Mask Register -------- */ +/* - -------- TDES_ISR : (TDES Offset: 0x1c) Interrupt Status Register -------- */ + AT91C_TDES_URAT EQU( 0x3 << 12 ); + -( TDES ) Unspecified Register Access Type Status + AT91C_TDES_URAT_IN_DAT_WRITE_DATPROC EQU( 0x0 << 12 ); + -( TDES ) Input data register written during the data processing in PDC mode. + AT91C_TDES_URAT_OUT_DAT_READ_DATPROC EQU( 0x1 << 12 ); + -( TDES ) Output data register read during the data processing. + AT91C_TDES_URAT_MODEREG_WRITE_DATPROC EQU( 0x2 << 12 ); + -( TDES ) Mode register written during the data processing. + AT91C_TDES_URAT_WO_REG_READ EQU( 0x3 << 12 ); + -( TDES ) Write - only register read access. + +/* - ***************************************************************************** */ +/* - REGISTER ADDRESS DEFINITION FOR AT91SAM7X256 */ +/* - ***************************************************************************** */ +/* - ========== Register definition for SYS peripheral ========== */ +/* - ========== Register definition for AIC peripheral ========== */ + AT91C_AIC_IVR EQU( 0xFFFFF100 ); + -( AIC ) IRQ Vector Register + AT91C_AIC_SMR EQU( 0xFFFFF000 ); + -( AIC ) Source Mode Register + AT91C_AIC_FVR EQU( 0xFFFFF104 ); + -( AIC ) FIQ Vector Register + AT91C_AIC_DCR EQU( 0xFFFFF138 ); + -( AIC ) Debug Control Register( Protect ) + AT91C_AIC_EOICR EQU( 0xFFFFF130 ); + -( AIC ) End of Interrupt Command Register + AT91C_AIC_SVR EQU( 0xFFFFF080 ); + -( AIC ) Source Vector Register + AT91C_AIC_FFSR EQU( 0xFFFFF148 ); + -( AIC ) Fast Forcing Status Register + AT91C_AIC_ICCR EQU( 0xFFFFF128 ); + -( AIC ) Interrupt Clear Command Register + AT91C_AIC_ISR EQU( 0xFFFFF108 ); + -( AIC ) Interrupt Status Register + AT91C_AIC_IMR EQU( 0xFFFFF110 ); + -( AIC ) Interrupt Mask Register + AT91C_AIC_IPR EQU( 0xFFFFF10C ); + -( AIC ) Interrupt Pending Register + AT91C_AIC_FFER EQU( 0xFFFFF140 ); + -( AIC ) Fast Forcing Enable Register + AT91C_AIC_IECR EQU( 0xFFFFF120 ); + -( AIC ) Interrupt Enable Command Register + AT91C_AIC_ISCR EQU( 0xFFFFF12C ); + -( AIC ) Interrupt Set Command Register + AT91C_AIC_FFDR EQU( 0xFFFFF144 ); + -( AIC ) Fast Forcing Disable Register + AT91C_AIC_CISR EQU( 0xFFFFF114 ); + -( AIC ) Core Interrupt Status Register + AT91C_AIC_IDCR EQU( 0xFFFFF124 ); + -( AIC ) Interrupt Disable Command Register + AT91C_AIC_SPU EQU( 0xFFFFF134 ); + -( AIC ) Spurious Vector Register +/* - ========== Register definition for PDC_DBGU peripheral ========== */ + AT91C_DBGU_TCR EQU( 0xFFFFF30C ); + -( PDC_DBGU ) Transmit Counter Register + AT91C_DBGU_RNPR EQU( 0xFFFFF310 ); + -( PDC_DBGU ) Receive Next Pointer Register + AT91C_DBGU_TNPR EQU( 0xFFFFF318 ); + -( PDC_DBGU ) Transmit Next Pointer Register + AT91C_DBGU_TPR EQU( 0xFFFFF308 ); + -( PDC_DBGU ) Transmit Pointer Register + AT91C_DBGU_RPR EQU( 0xFFFFF300 ); + -( PDC_DBGU ) Receive Pointer Register + AT91C_DBGU_RCR EQU( 0xFFFFF304 ); + -( PDC_DBGU ) Receive Counter Register + AT91C_DBGU_RNCR EQU( 0xFFFFF314 ); + -( PDC_DBGU ) Receive Next Counter Register + AT91C_DBGU_PTCR EQU( 0xFFFFF320 ); + -( PDC_DBGU ) PDC Transfer Control Register + AT91C_DBGU_PTSR EQU( 0xFFFFF324 ); + -( PDC_DBGU ) PDC Transfer Status Register + AT91C_DBGU_TNCR EQU( 0xFFFFF31C ); + -( PDC_DBGU ) Transmit Next Counter Register +/* - ========== Register definition for DBGU peripheral ========== */ + AT91C_DBGU_EXID EQU( 0xFFFFF244 ); + -( DBGU ) Chip ID Extension Register + AT91C_DBGU_BRGR EQU( 0xFFFFF220 ); + -( DBGU ) Baud Rate Generator Register + AT91C_DBGU_IDR EQU( 0xFFFFF20C ); + -( DBGU ) Interrupt Disable Register + AT91C_DBGU_CSR EQU( 0xFFFFF214 ); + -( DBGU ) Channel Status Register + AT91C_DBGU_CIDR EQU( 0xFFFFF240 ); + -( DBGU ) Chip ID Register + AT91C_DBGU_MR EQU( 0xFFFFF204 ); + -( DBGU ) Mode Register + AT91C_DBGU_IMR EQU( 0xFFFFF210 ); + -( DBGU ) Interrupt Mask Register + AT91C_DBGU_CR EQU( 0xFFFFF200 ); + -( DBGU ) Control Register + AT91C_DBGU_FNTR EQU( 0xFFFFF248 ); + -( DBGU ) Force NTRST Register + AT91C_DBGU_THR EQU( 0xFFFFF21C ); + -( DBGU ) Transmitter Holding Register + AT91C_DBGU_RHR EQU( 0xFFFFF218 ); + -( DBGU ) Receiver Holding Register + AT91C_DBGU_IER EQU( 0xFFFFF208 ); + -( DBGU ) Interrupt Enable Register +/* - ========== Register definition for PIOA peripheral ========== */ + AT91C_PIOA_ODR EQU( 0xFFFFF414 ); + -( PIOA ) Output Disable Registerr + AT91C_PIOA_SODR EQU( 0xFFFFF430 ); + -( PIOA ) Set Output Data Register + AT91C_PIOA_ISR EQU( 0xFFFFF44C ); + -( PIOA ) Interrupt Status Register + AT91C_PIOA_ABSR EQU( 0xFFFFF478 ); + -( PIOA ) AB Select Status Register + AT91C_PIOA_IER EQU( 0xFFFFF440 ); + -( PIOA ) Interrupt Enable Register + AT91C_PIOA_PPUDR EQU( 0xFFFFF460 ); + -( PIOA ) Pull - up Disable Register + AT91C_PIOA_IMR EQU( 0xFFFFF448 ); + -( PIOA ) Interrupt Mask Register + AT91C_PIOA_PER EQU( 0xFFFFF400 ); + -( PIOA ) PIO Enable Register + AT91C_PIOA_IFDR EQU( 0xFFFFF424 ); + -( PIOA ) Input Filter Disable Register + AT91C_PIOA_OWDR EQU( 0xFFFFF4A4 ); + -( PIOA ) Output Write Disable Register + AT91C_PIOA_MDSR EQU( 0xFFFFF458 ); + -( PIOA ) Multi - driver Status Register + AT91C_PIOA_IDR EQU( 0xFFFFF444 ); + -( PIOA ) Interrupt Disable Register + AT91C_PIOA_ODSR EQU( 0xFFFFF438 ); + -( PIOA ) Output Data Status Register + AT91C_PIOA_PPUSR EQU( 0xFFFFF468 ); + -( PIOA ) Pull - up Status Register + AT91C_PIOA_OWSR EQU( 0xFFFFF4A8 ); + -( PIOA ) Output Write Status Register + AT91C_PIOA_BSR EQU( 0xFFFFF474 ); + -( PIOA ) Select B Register + AT91C_PIOA_OWER EQU( 0xFFFFF4A0 ); + -( PIOA ) Output Write Enable Register + AT91C_PIOA_IFER EQU( 0xFFFFF420 ); + -( PIOA ) Input Filter Enable Register + AT91C_PIOA_PDSR EQU( 0xFFFFF43C ); + -( PIOA ) Pin Data Status Register + AT91C_PIOA_PPUER EQU( 0xFFFFF464 ); + -( PIOA ) Pull - up Enable Register + AT91C_PIOA_OSR EQU( 0xFFFFF418 ); + -( PIOA ) Output Status Register + AT91C_PIOA_ASR EQU( 0xFFFFF470 ); + -( PIOA ) Select A Register + AT91C_PIOA_MDDR EQU( 0xFFFFF454 ); + -( PIOA ) Multi - driver Disable Register + AT91C_PIOA_CODR EQU( 0xFFFFF434 ); + -( PIOA ) Clear Output Data Register + AT91C_PIOA_MDER EQU( 0xFFFFF450 ); + -( PIOA ) Multi - driver Enable Register + AT91C_PIOA_PDR EQU( 0xFFFFF404 ); + -( PIOA ) PIO Disable Register + AT91C_PIOA_IFSR EQU( 0xFFFFF428 ); + -( PIOA ) Input Filter Status Register + AT91C_PIOA_OER EQU( 0xFFFFF410 ); + -( PIOA ) Output Enable Register + AT91C_PIOA_PSR EQU( 0xFFFFF408 ); + -( PIOA ) PIO Status Register +/* - ========== Register definition for PIOB peripheral ========== */ + AT91C_PIOB_OWDR EQU( 0xFFFFF6A4 ); + -( PIOB ) Output Write Disable Register + AT91C_PIOB_MDER EQU( 0xFFFFF650 ); + -( PIOB ) Multi - driver Enable Register + AT91C_PIOB_PPUSR EQU( 0xFFFFF668 ); + -( PIOB ) Pull - up Status Register + AT91C_PIOB_IMR EQU( 0xFFFFF648 ); + -( PIOB ) Interrupt Mask Register + AT91C_PIOB_ASR EQU( 0xFFFFF670 ); + -( PIOB ) Select A Register + AT91C_PIOB_PPUDR EQU( 0xFFFFF660 ); + -( PIOB ) Pull - up Disable Register + AT91C_PIOB_PSR EQU( 0xFFFFF608 ); + -( PIOB ) PIO Status Register + AT91C_PIOB_IER EQU( 0xFFFFF640 ); + -( PIOB ) Interrupt Enable Register + AT91C_PIOB_CODR EQU( 0xFFFFF634 ); + -( PIOB ) Clear Output Data Register + AT91C_PIOB_OWER EQU( 0xFFFFF6A0 ); + -( PIOB ) Output Write Enable Register + AT91C_PIOB_ABSR EQU( 0xFFFFF678 ); + -( PIOB ) AB Select Status Register + AT91C_PIOB_IFDR EQU( 0xFFFFF624 ); + -( PIOB ) Input Filter Disable Register + AT91C_PIOB_PDSR EQU( 0xFFFFF63C ); + -( PIOB ) Pin Data Status Register + AT91C_PIOB_IDR EQU( 0xFFFFF644 ); + -( PIOB ) Interrupt Disable Register + AT91C_PIOB_OWSR EQU( 0xFFFFF6A8 ); + -( PIOB ) Output Write Status Register + AT91C_PIOB_PDR EQU( 0xFFFFF604 ); + -( PIOB ) PIO Disable Register + AT91C_PIOB_ODR EQU( 0xFFFFF614 ); + -( PIOB ) Output Disable Registerr + AT91C_PIOB_IFSR EQU( 0xFFFFF628 ); + -( PIOB ) Input Filter Status Register + AT91C_PIOB_PPUER EQU( 0xFFFFF664 ); + -( PIOB ) Pull - up Enable Register + AT91C_PIOB_SODR EQU( 0xFFFFF630 ); + -( PIOB ) Set Output Data Register + AT91C_PIOB_ISR EQU( 0xFFFFF64C ); + -( PIOB ) Interrupt Status Register + AT91C_PIOB_ODSR EQU( 0xFFFFF638 ); + -( PIOB ) Output Data Status Register + AT91C_PIOB_OSR EQU( 0xFFFFF618 ); + -( PIOB ) Output Status Register + AT91C_PIOB_MDSR EQU( 0xFFFFF658 ); + -( PIOB ) Multi - driver Status Register + AT91C_PIOB_IFER EQU( 0xFFFFF620 ); + -( PIOB ) Input Filter Enable Register + AT91C_PIOB_BSR EQU( 0xFFFFF674 ); + -( PIOB ) Select B Register + AT91C_PIOB_MDDR EQU( 0xFFFFF654 ); + -( PIOB ) Multi - driver Disable Register + AT91C_PIOB_OER EQU( 0xFFFFF610 ); + -( PIOB ) Output Enable Register + AT91C_PIOB_PER EQU( 0xFFFFF600 ); + -( PIOB ) PIO Enable Register +/* - ========== Register definition for CKGR peripheral ========== */ + AT91C_CKGR_MOR EQU( 0xFFFFFC20 ); + -( CKGR ) Main Oscillator Register + AT91C_CKGR_PLLR EQU( 0xFFFFFC2C ); + -( CKGR ) PLL Register + AT91C_CKGR_MCFR EQU( 0xFFFFFC24 ); + -( CKGR ) Main Clock Frequency Register +/* - ========== Register definition for PMC peripheral ========== */ + AT91C_PMC_IDR EQU( 0xFFFFFC64 ); + -( PMC ) Interrupt Disable Register + AT91C_PMC_MOR EQU( 0xFFFFFC20 ); + -( PMC ) Main Oscillator Register + AT91C_PMC_PLLR EQU( 0xFFFFFC2C ); + -( PMC ) PLL Register + AT91C_PMC_PCER EQU( 0xFFFFFC10 ); + -( PMC ) Peripheral Clock Enable Register + AT91C_PMC_PCKR EQU( 0xFFFFFC40 ); + -( PMC ) Programmable Clock Register + AT91C_PMC_MCKR EQU( 0xFFFFFC30 ); + -( PMC ) Master Clock Register + AT91C_PMC_SCDR EQU( 0xFFFFFC04 ); + -( PMC ) System Clock Disable Register + AT91C_PMC_PCDR EQU( 0xFFFFFC14 ); + -( PMC ) Peripheral Clock Disable Register + AT91C_PMC_SCSR EQU( 0xFFFFFC08 ); + -( PMC ) System Clock Status Register + AT91C_PMC_PCSR EQU( 0xFFFFFC18 ); + -( PMC ) Peripheral Clock Status Register + AT91C_PMC_MCFR EQU( 0xFFFFFC24 ); + -( PMC ) Main Clock Frequency Register + AT91C_PMC_SCER EQU( 0xFFFFFC00 ); + -( PMC ) System Clock Enable Register + AT91C_PMC_IMR EQU( 0xFFFFFC6C ); + -( PMC ) Interrupt Mask Register + AT91C_PMC_IER EQU( 0xFFFFFC60 ); + -( PMC ) Interrupt Enable Register + AT91C_PMC_SR EQU( 0xFFFFFC68 ); + -( PMC ) Status Register +/* - ========== Register definition for RSTC peripheral ========== */ + AT91C_RSTC_RCR EQU( 0xFFFFFD00 ); + -( RSTC ) Reset Control Register + AT91C_RSTC_RMR EQU( 0xFFFFFD08 ); + -( RSTC ) Reset Mode Register + AT91C_RSTC_RSR EQU( 0xFFFFFD04 ); + -( RSTC ) Reset Status Register +/* - ========== Register definition for RTTC peripheral ========== */ + AT91C_RTTC_RTSR EQU( 0xFFFFFD2C ); + -( RTTC ) Real - time Status Register + AT91C_RTTC_RTMR EQU( 0xFFFFFD20 ); + -( RTTC ) Real - time Mode Register + AT91C_RTTC_RTVR EQU( 0xFFFFFD28 ); + -( RTTC ) Real - time Value Register + AT91C_RTTC_RTAR EQU( 0xFFFFFD24 ); + -( RTTC ) Real - time Alarm Register +/* - ========== Register definition for PITC peripheral ========== */ + AT91C_PITC_PIVR EQU( 0xFFFFFD38 ); + -( PITC ) Period Interval Value Register + AT91C_PITC_PISR EQU( 0xFFFFFD34 ); + -( PITC ) Period Interval Status Register + AT91C_PITC_PIIR EQU( 0xFFFFFD3C ); + -( PITC ) Period Interval Image Register + AT91C_PITC_PIMR EQU( 0xFFFFFD30 ); + -( PITC ) Period Interval Mode Register +/* - ========== Register definition for WDTC peripheral ========== */ + AT91C_WDTC_WDCR EQU( 0xFFFFFD40 ); + -( WDTC ) Watchdog Control Register + AT91C_WDTC_WDSR EQU( 0xFFFFFD48 ); + -( WDTC ) Watchdog Status Register + AT91C_WDTC_WDMR EQU( 0xFFFFFD44 ); + -( WDTC ) Watchdog Mode Register +/* - ========== Register definition for VREG peripheral ========== */ + AT91C_VREG_MR EQU( 0xFFFFFD60 ); + -( VREG ) Voltage Regulator Mode Register +/* - ========== Register definition for MC peripheral ========== */ + AT91C_MC_ASR EQU( 0xFFFFFF04 ); + -( MC ) MC Abort Status Register + AT91C_MC_RCR EQU( 0xFFFFFF00 ); + -( MC ) MC Remap Control Register + AT91C_MC_FCR EQU( 0xFFFFFF64 ); + -( MC ) MC Flash Command Register + AT91C_MC_AASR EQU( 0xFFFFFF08 ); + -( MC ) MC Abort Address Status Register + AT91C_MC_FSR EQU( 0xFFFFFF68 ); + -( MC ) MC Flash Status Register + AT91C_MC_FMR EQU( 0xFFFFFF60 ); + -( MC ) MC Flash Mode Register +/* - ========== Register definition for PDC_SPI1 peripheral ========== */ + AT91C_SPI1_PTCR EQU( 0xFFFE4120 ); + -( PDC_SPI1 ) PDC Transfer Control Register + AT91C_SPI1_RPR EQU( 0xFFFE4100 ); + -( PDC_SPI1 ) Receive Pointer Register + AT91C_SPI1_TNCR EQU( 0xFFFE411C ); + -( PDC_SPI1 ) Transmit Next Counter Register + AT91C_SPI1_TPR EQU( 0xFFFE4108 ); + -( PDC_SPI1 ) Transmit Pointer Register + AT91C_SPI1_TNPR EQU( 0xFFFE4118 ); + -( PDC_SPI1 ) Transmit Next Pointer Register + AT91C_SPI1_TCR EQU( 0xFFFE410C ); + -( PDC_SPI1 ) Transmit Counter Register + AT91C_SPI1_RCR EQU( 0xFFFE4104 ); + -( PDC_SPI1 ) Receive Counter Register + AT91C_SPI1_RNPR EQU( 0xFFFE4110 ); + -( PDC_SPI1 ) Receive Next Pointer Register + AT91C_SPI1_RNCR EQU( 0xFFFE4114 ); + -( PDC_SPI1 ) Receive Next Counter Register + AT91C_SPI1_PTSR EQU( 0xFFFE4124 ); + -( PDC_SPI1 ) PDC Transfer Status Register +/* - ========== Register definition for SPI1 peripheral ========== */ + AT91C_SPI1_IMR EQU( 0xFFFE401C ); + -( SPI1 ) Interrupt Mask Register + AT91C_SPI1_IER EQU( 0xFFFE4014 ); + -( SPI1 ) Interrupt Enable Register + AT91C_SPI1_MR EQU( 0xFFFE4004 ); + -( SPI1 ) Mode Register + AT91C_SPI1_RDR EQU( 0xFFFE4008 ); + -( SPI1 ) Receive Data Register + AT91C_SPI1_IDR EQU( 0xFFFE4018 ); + -( SPI1 ) Interrupt Disable Register + AT91C_SPI1_SR EQU( 0xFFFE4010 ); + -( SPI1 ) Status Register + AT91C_SPI1_TDR EQU( 0xFFFE400C ); + -( SPI1 ) Transmit Data Register + AT91C_SPI1_CR EQU( 0xFFFE4000 ); + -( SPI1 ) Control Register + AT91C_SPI1_CSR EQU( 0xFFFE4030 ); + -( SPI1 ) Chip Select Register +/* - ========== Register definition for PDC_SPI0 peripheral ========== */ + AT91C_SPI0_PTCR EQU( 0xFFFE0120 ); + -( PDC_SPI0 ) PDC Transfer Control Register + AT91C_SPI0_TPR EQU( 0xFFFE0108 ); + -( PDC_SPI0 ) Transmit Pointer Register + AT91C_SPI0_TCR EQU( 0xFFFE010C ); + -( PDC_SPI0 ) Transmit Counter Register + AT91C_SPI0_RCR EQU( 0xFFFE0104 ); + -( PDC_SPI0 ) Receive Counter Register + AT91C_SPI0_PTSR EQU( 0xFFFE0124 ); + -( PDC_SPI0 ) PDC Transfer Status Register + AT91C_SPI0_RNPR EQU( 0xFFFE0110 ); + -( PDC_SPI0 ) Receive Next Pointer Register + AT91C_SPI0_RPR EQU( 0xFFFE0100 ); + -( PDC_SPI0 ) Receive Pointer Register + AT91C_SPI0_TNCR EQU( 0xFFFE011C ); + -( PDC_SPI0 ) Transmit Next Counter Register + AT91C_SPI0_RNCR EQU( 0xFFFE0114 ); + -( PDC_SPI0 ) Receive Next Counter Register + AT91C_SPI0_TNPR EQU( 0xFFFE0118 ); + -( PDC_SPI0 ) Transmit Next Pointer Register +/* - ========== Register definition for SPI0 peripheral ========== */ + AT91C_SPI0_IER EQU( 0xFFFE0014 ); + -( SPI0 ) Interrupt Enable Register + AT91C_SPI0_SR EQU( 0xFFFE0010 ); + -( SPI0 ) Status Register + AT91C_SPI0_IDR EQU( 0xFFFE0018 ); + -( SPI0 ) Interrupt Disable Register + AT91C_SPI0_CR EQU( 0xFFFE0000 ); + -( SPI0 ) Control Register + AT91C_SPI0_MR EQU( 0xFFFE0004 ); + -( SPI0 ) Mode Register + AT91C_SPI0_IMR EQU( 0xFFFE001C ); + -( SPI0 ) Interrupt Mask Register + AT91C_SPI0_TDR EQU( 0xFFFE000C ); + -( SPI0 ) Transmit Data Register + AT91C_SPI0_RDR EQU( 0xFFFE0008 ); + -( SPI0 ) Receive Data Register + AT91C_SPI0_CSR EQU( 0xFFFE0030 ); + -( SPI0 ) Chip Select Register +/* - ========== Register definition for PDC_US1 peripheral ========== */ + AT91C_US1_RNCR EQU( 0xFFFC4114 ); + -( PDC_US1 ) Receive Next Counter Register + AT91C_US1_PTCR EQU( 0xFFFC4120 ); + -( PDC_US1 ) PDC Transfer Control Register + AT91C_US1_TCR EQU( 0xFFFC410C ); + -( PDC_US1 ) Transmit Counter Register + AT91C_US1_PTSR EQU( 0xFFFC4124 ); + -( PDC_US1 ) PDC Transfer Status Register + AT91C_US1_TNPR EQU( 0xFFFC4118 ); + -( PDC_US1 ) Transmit Next Pointer Register + AT91C_US1_RCR EQU( 0xFFFC4104 ); + -( PDC_US1 ) Receive Counter Register + AT91C_US1_RNPR EQU( 0xFFFC4110 ); + -( PDC_US1 ) Receive Next Pointer Register + AT91C_US1_RPR EQU( 0xFFFC4100 ); + -( PDC_US1 ) Receive Pointer Register + AT91C_US1_TNCR EQU( 0xFFFC411C ); + -( PDC_US1 ) Transmit Next Counter Register + AT91C_US1_TPR EQU( 0xFFFC4108 ); + -( PDC_US1 ) Transmit Pointer Register +/* - ========== Register definition for US1 peripheral ========== */ + AT91C_US1_IF EQU( 0xFFFC404C ); + -( US1 ) IRDA_FILTER Register + AT91C_US1_NER EQU( 0xFFFC4044 ); + -( US1 ) Nb Errors Register + AT91C_US1_RTOR EQU( 0xFFFC4024 ); + -( US1 ) Receiver Time - out Register + AT91C_US1_CSR EQU( 0xFFFC4014 ); + -( US1 ) Channel Status Register + AT91C_US1_IDR EQU( 0xFFFC400C ); + -( US1 ) Interrupt Disable Register + AT91C_US1_IER EQU( 0xFFFC4008 ); + -( US1 ) Interrupt Enable Register + AT91C_US1_THR EQU( 0xFFFC401C ); + -( US1 ) Transmitter Holding Register + AT91C_US1_TTGR EQU( 0xFFFC4028 ); + -( US1 ) Transmitter Time - guard Register + AT91C_US1_RHR EQU( 0xFFFC4018 ); + -( US1 ) Receiver Holding Register + AT91C_US1_BRGR EQU( 0xFFFC4020 ); + -( US1 ) Baud Rate Generator Register + AT91C_US1_IMR EQU( 0xFFFC4010 ); + -( US1 ) Interrupt Mask Register + AT91C_US1_FIDI EQU( 0xFFFC4040 ); + -( US1 ) FI_DI_Ratio Register + AT91C_US1_CR EQU( 0xFFFC4000 ); + -( US1 ) Control Register + AT91C_US1_MR EQU( 0xFFFC4004 ); + -( US1 ) Mode Register +/* - ========== Register definition for PDC_US0 peripheral ========== */ + AT91C_US0_TNPR EQU( 0xFFFC0118 ); + -( PDC_US0 ) Transmit Next Pointer Register + AT91C_US0_RNPR EQU( 0xFFFC0110 ); + -( PDC_US0 ) Receive Next Pointer Register + AT91C_US0_TCR EQU( 0xFFFC010C ); + -( PDC_US0 ) Transmit Counter Register + AT91C_US0_PTCR EQU( 0xFFFC0120 ); + -( PDC_US0 ) PDC Transfer Control Register + AT91C_US0_PTSR EQU( 0xFFFC0124 ); + -( PDC_US0 ) PDC Transfer Status Register + AT91C_US0_TNCR EQU( 0xFFFC011C ); + -( PDC_US0 ) Transmit Next Counter Register + AT91C_US0_TPR EQU( 0xFFFC0108 ); + -( PDC_US0 ) Transmit Pointer Register + AT91C_US0_RCR EQU( 0xFFFC0104 ); + -( PDC_US0 ) Receive Counter Register + AT91C_US0_RPR EQU( 0xFFFC0100 ); + -( PDC_US0 ) Receive Pointer Register + AT91C_US0_RNCR EQU( 0xFFFC0114 ); + -( PDC_US0 ) Receive Next Counter Register +/* - ========== Register definition for US0 peripheral ========== */ + AT91C_US0_BRGR EQU( 0xFFFC0020 ); + -( US0 ) Baud Rate Generator Register + AT91C_US0_NER EQU( 0xFFFC0044 ); + -( US0 ) Nb Errors Register + AT91C_US0_CR EQU( 0xFFFC0000 ); + -( US0 ) Control Register + AT91C_US0_IMR EQU( 0xFFFC0010 ); + -( US0 ) Interrupt Mask Register + AT91C_US0_FIDI EQU( 0xFFFC0040 ); + -( US0 ) FI_DI_Ratio Register + AT91C_US0_TTGR EQU( 0xFFFC0028 ); + -( US0 ) Transmitter Time - guard Register + AT91C_US0_MR EQU( 0xFFFC0004 ); + -( US0 ) Mode Register + AT91C_US0_RTOR EQU( 0xFFFC0024 ); + -( US0 ) Receiver Time - out Register + AT91C_US0_CSR EQU( 0xFFFC0014 ); + -( US0 ) Channel Status Register + AT91C_US0_RHR EQU( 0xFFFC0018 ); + -( US0 ) Receiver Holding Register + AT91C_US0_IDR EQU( 0xFFFC000C ); + -( US0 ) Interrupt Disable Register + AT91C_US0_THR EQU( 0xFFFC001C ); + -( US0 ) Transmitter Holding Register + AT91C_US0_IF EQU( 0xFFFC004C ); + -( US0 ) IRDA_FILTER Register + AT91C_US0_IER EQU( 0xFFFC0008 ); + -( US0 ) Interrupt Enable Register +/* - ========== Register definition for PDC_SSC peripheral ========== */ + AT91C_SSC_TNCR EQU( 0xFFFD411C ); + -( PDC_SSC ) Transmit Next Counter Register + AT91C_SSC_RPR EQU( 0xFFFD4100 ); + -( PDC_SSC ) Receive Pointer Register + AT91C_SSC_RNCR EQU( 0xFFFD4114 ); + -( PDC_SSC ) Receive Next Counter Register + AT91C_SSC_TPR EQU( 0xFFFD4108 ); + -( PDC_SSC ) Transmit Pointer Register + AT91C_SSC_PTCR EQU( 0xFFFD4120 ); + -( PDC_SSC ) PDC Transfer Control Register + AT91C_SSC_TCR EQU( 0xFFFD410C ); + -( PDC_SSC ) Transmit Counter Register + AT91C_SSC_RCR EQU( 0xFFFD4104 ); + -( PDC_SSC ) Receive Counter Register + AT91C_SSC_RNPR EQU( 0xFFFD4110 ); + -( PDC_SSC ) Receive Next Pointer Register + AT91C_SSC_TNPR EQU( 0xFFFD4118 ); + -( PDC_SSC ) Transmit Next Pointer Register + AT91C_SSC_PTSR EQU( 0xFFFD4124 ); + -( PDC_SSC ) PDC Transfer Status Register +/* - ========== Register definition for SSC peripheral ========== */ + AT91C_SSC_RHR EQU( 0xFFFD4020 ); + -( SSC ) Receive Holding Register + AT91C_SSC_RSHR EQU( 0xFFFD4030 ); + -( SSC ) Receive Sync Holding Register + AT91C_SSC_TFMR EQU( 0xFFFD401C ); + -( SSC ) Transmit Frame Mode Register + AT91C_SSC_IDR EQU( 0xFFFD4048 ); + -( SSC ) Interrupt Disable Register + AT91C_SSC_THR EQU( 0xFFFD4024 ); + -( SSC ) Transmit Holding Register + AT91C_SSC_RCMR EQU( 0xFFFD4010 ); + -( SSC ) Receive Clock ModeRegister + AT91C_SSC_IER EQU( 0xFFFD4044 ); + -( SSC ) Interrupt Enable Register + AT91C_SSC_TSHR EQU( 0xFFFD4034 ); + -( SSC ) Transmit Sync Holding Register + AT91C_SSC_SR EQU( 0xFFFD4040 ); + -( SSC ) Status Register + AT91C_SSC_CMR EQU( 0xFFFD4004 ); + -( SSC ) Clock Mode Register + AT91C_SSC_TCMR EQU( 0xFFFD4018 ); + -( SSC ) Transmit Clock Mode Register + AT91C_SSC_CR EQU( 0xFFFD4000 ); + -( SSC ) Control Register + AT91C_SSC_IMR EQU( 0xFFFD404C ); + -( SSC ) Interrupt Mask Register + AT91C_SSC_RFMR EQU( 0xFFFD4014 ); + -( SSC ) Receive Frame Mode Register +/* - ========== Register definition for TWI peripheral ========== */ + AT91C_TWI_IER EQU( 0xFFFB8024 ); + -( TWI ) Interrupt Enable Register + AT91C_TWI_CR EQU( 0xFFFB8000 ); + -( TWI ) Control Register + AT91C_TWI_SR EQU( 0xFFFB8020 ); + -( TWI ) Status Register + AT91C_TWI_IMR EQU( 0xFFFB802C ); + -( TWI ) Interrupt Mask Register + AT91C_TWI_THR EQU( 0xFFFB8034 ); + -( TWI ) Transmit Holding Register + AT91C_TWI_IDR EQU( 0xFFFB8028 ); + -( TWI ) Interrupt Disable Register + AT91C_TWI_IADR EQU( 0xFFFB800C ); + -( TWI ) Internal Address Register + AT91C_TWI_MMR EQU( 0xFFFB8004 ); + -( TWI ) Master Mode Register + AT91C_TWI_CWGR EQU( 0xFFFB8010 ); + -( TWI ) Clock Waveform Generator Register + AT91C_TWI_RHR EQU( 0xFFFB8030 ); + -( TWI ) Receive Holding Register +/* - ========== Register definition for PWMC_CH3 peripheral ========== */ + AT91C_PWMC_CH3_CUPDR EQU( 0xFFFCC270 ); + -( PWMC_CH3 ) Channel Update Register + AT91C_PWMC_CH3_Reserved EQU( 0xFFFCC274 ); + -( PWMC_CH3 ) Reserved + AT91C_PWMC_CH3_CPRDR EQU( 0xFFFCC268 ); + -( PWMC_CH3 ) Channel Period Register + AT91C_PWMC_CH3_CDTYR EQU( 0xFFFCC264 ); + -( PWMC_CH3 ) Channel Duty Cycle Register + AT91C_PWMC_CH3_CCNTR EQU( 0xFFFCC26C ); + -( PWMC_CH3 ) Channel Counter Register + AT91C_PWMC_CH3_CMR EQU( 0xFFFCC260 ); + -( PWMC_CH3 ) Channel Mode Register +/* - ========== Register definition for PWMC_CH2 peripheral ========== */ + AT91C_PWMC_CH2_Reserved EQU( 0xFFFCC254 ); + -( PWMC_CH2 ) Reserved + AT91C_PWMC_CH2_CMR EQU( 0xFFFCC240 ); + -( PWMC_CH2 ) Channel Mode Register + AT91C_PWMC_CH2_CCNTR EQU( 0xFFFCC24C ); + -( PWMC_CH2 ) Channel Counter Register + AT91C_PWMC_CH2_CPRDR EQU( 0xFFFCC248 ); + -( PWMC_CH2 ) Channel Period Register + AT91C_PWMC_CH2_CUPDR EQU( 0xFFFCC250 ); + -( PWMC_CH2 ) Channel Update Register + AT91C_PWMC_CH2_CDTYR EQU( 0xFFFCC244 ); + -( PWMC_CH2 ) Channel Duty Cycle Register +/* - ========== Register definition for PWMC_CH1 peripheral ========== */ + AT91C_PWMC_CH1_Reserved EQU( 0xFFFCC234 ); + -( PWMC_CH1 ) Reserved + AT91C_PWMC_CH1_CUPDR EQU( 0xFFFCC230 ); + -( PWMC_CH1 ) Channel Update Register + AT91C_PWMC_CH1_CPRDR EQU( 0xFFFCC228 ); + -( PWMC_CH1 ) Channel Period Register + AT91C_PWMC_CH1_CCNTR EQU( 0xFFFCC22C ); + -( PWMC_CH1 ) Channel Counter Register + AT91C_PWMC_CH1_CDTYR EQU( 0xFFFCC224 ); + -( PWMC_CH1 ) Channel Duty Cycle Register + AT91C_PWMC_CH1_CMR EQU( 0xFFFCC220 ); + -( PWMC_CH1 ) Channel Mode Register +/* - ========== Register definition for PWMC_CH0 peripheral ========== */ + AT91C_PWMC_CH0_Reserved EQU( 0xFFFCC214 ); + -( PWMC_CH0 ) Reserved + AT91C_PWMC_CH0_CPRDR EQU( 0xFFFCC208 ); + -( PWMC_CH0 ) Channel Period Register + AT91C_PWMC_CH0_CDTYR EQU( 0xFFFCC204 ); + -( PWMC_CH0 ) Channel Duty Cycle Register + AT91C_PWMC_CH0_CMR EQU( 0xFFFCC200 ); + -( PWMC_CH0 ) Channel Mode Register + AT91C_PWMC_CH0_CUPDR EQU( 0xFFFCC210 ); + -( PWMC_CH0 ) Channel Update Register + AT91C_PWMC_CH0_CCNTR EQU( 0xFFFCC20C ); + -( PWMC_CH0 ) Channel Counter Register +/* - ========== Register definition for PWMC peripheral ========== */ + AT91C_PWMC_IDR EQU( 0xFFFCC014 ); + -( PWMC ) PWMC Interrupt Disable Register + AT91C_PWMC_DIS EQU( 0xFFFCC008 ); + -( PWMC ) PWMC Disable Register + AT91C_PWMC_IER EQU( 0xFFFCC010 ); + -( PWMC ) PWMC Interrupt Enable Register + AT91C_PWMC_VR EQU( 0xFFFCC0FC ); + -( PWMC ) PWMC Version Register + AT91C_PWMC_ISR EQU( 0xFFFCC01C ); + -( PWMC ) PWMC Interrupt Status Register + AT91C_PWMC_SR EQU( 0xFFFCC00C ); + -( PWMC ) PWMC Status Register + AT91C_PWMC_IMR EQU( 0xFFFCC018 ); + -( PWMC ) PWMC Interrupt Mask Register + AT91C_PWMC_MR EQU( 0xFFFCC000 ); + -( PWMC ) PWMC Mode Register + AT91C_PWMC_ENA EQU( 0xFFFCC004 ); + -( PWMC ) PWMC Enable Register +/* - ========== Register definition for UDP peripheral ========== */ + AT91C_UDP_IMR EQU( 0xFFFB0018 ); + -( UDP ) Interrupt Mask Register + AT91C_UDP_FADDR EQU( 0xFFFB0008 ); + -( UDP ) Function Address Register + AT91C_UDP_NUM EQU( 0xFFFB0000 ); + -( UDP ) Frame Number Register + AT91C_UDP_FDR EQU( 0xFFFB0050 ); + -( UDP ) Endpoint FIFO Data Register + AT91C_UDP_ISR EQU( 0xFFFB001C ); + -( UDP ) Interrupt Status Register + AT91C_UDP_CSR EQU( 0xFFFB0030 ); + -( UDP ) Endpoint Control and Status Register + AT91C_UDP_IDR EQU( 0xFFFB0014 ); + -( UDP ) Interrupt Disable Register + AT91C_UDP_ICR EQU( 0xFFFB0020 ); + -( UDP ) Interrupt Clear Register + AT91C_UDP_RSTEP EQU( 0xFFFB0028 ); + -( UDP ) Reset Endpoint Register + AT91C_UDP_TXVC EQU( 0xFFFB0074 ); + -( UDP ) Transceiver Control Register + AT91C_UDP_GLBSTATE EQU( 0xFFFB0004 ); + -( UDP ) Global State Register + AT91C_UDP_IER EQU( 0xFFFB0010 ); + -( UDP ) Interrupt Enable Register +/* - ========== Register definition for TC0 peripheral ========== */ + AT91C_TC0_SR EQU( 0xFFFA0020 ); + -( TC0 ) Status Register + AT91C_TC0_RC EQU( 0xFFFA001C ); + -( TC0 ) Register C + AT91C_TC0_RB EQU( 0xFFFA0018 ); + -( TC0 ) Register B + AT91C_TC0_CCR EQU( 0xFFFA0000 ); + -( TC0 ) Channel Control Register + AT91C_TC0_CMR EQU( 0xFFFA0004 ); + -( TC0 ) Channel Mode Register( Capture Mode / Waveform Mode ) + AT91C_TC0_IER EQU( 0xFFFA0024 ); + -( TC0 ) Interrupt Enable Register + AT91C_TC0_RA EQU( 0xFFFA0014 ); + -( TC0 ) Register A + AT91C_TC0_IDR EQU( 0xFFFA0028 ); + -( TC0 ) Interrupt Disable Register + AT91C_TC0_CV EQU( 0xFFFA0010 ); + -( TC0 ) Counter Value + AT91C_TC0_IMR EQU( 0xFFFA002C ); + -( TC0 ) Interrupt Mask Register +/* - ========== Register definition for TC1 peripheral ========== */ + AT91C_TC1_RB EQU( 0xFFFA0058 ); + -( TC1 ) Register B + AT91C_TC1_CCR EQU( 0xFFFA0040 ); + -( TC1 ) Channel Control Register + AT91C_TC1_IER EQU( 0xFFFA0064 ); + -( TC1 ) Interrupt Enable Register + AT91C_TC1_IDR EQU( 0xFFFA0068 ); + -( TC1 ) Interrupt Disable Register + AT91C_TC1_SR EQU( 0xFFFA0060 ); + -( TC1 ) Status Register + AT91C_TC1_CMR EQU( 0xFFFA0044 ); + -( TC1 ) Channel Mode Register( Capture Mode / Waveform Mode ) + AT91C_TC1_RA EQU( 0xFFFA0054 ); + -( TC1 ) Register A + AT91C_TC1_RC EQU( 0xFFFA005C ); + -( TC1 ) Register C + AT91C_TC1_IMR EQU( 0xFFFA006C ); + -( TC1 ) Interrupt Mask Register + AT91C_TC1_CV EQU( 0xFFFA0050 ); + -( TC1 ) Counter Value +/* - ========== Register definition for TC2 peripheral ========== */ + AT91C_TC2_CMR EQU( 0xFFFA0084 ); + -( TC2 ) Channel Mode Register( Capture Mode / Waveform Mode ) + AT91C_TC2_CCR EQU( 0xFFFA0080 ); + -( TC2 ) Channel Control Register + AT91C_TC2_CV EQU( 0xFFFA0090 ); + -( TC2 ) Counter Value + AT91C_TC2_RA EQU( 0xFFFA0094 ); + -( TC2 ) Register A + AT91C_TC2_RB EQU( 0xFFFA0098 ); + -( TC2 ) Register B + AT91C_TC2_IDR EQU( 0xFFFA00A8 ); + -( TC2 ) Interrupt Disable Register + AT91C_TC2_IMR EQU( 0xFFFA00AC ); + -( TC2 ) Interrupt Mask Register + AT91C_TC2_RC EQU( 0xFFFA009C ); + -( TC2 ) Register C + AT91C_TC2_IER EQU( 0xFFFA00A4 ); + -( TC2 ) Interrupt Enable Register + AT91C_TC2_SR EQU( 0xFFFA00A0 ); + -( TC2 ) Status Register +/* - ========== Register definition for TCB peripheral ========== */ + AT91C_TCB_BMR EQU( 0xFFFA00C4 ); + -( TCB ) TC Block Mode Register + AT91C_TCB_BCR EQU( 0xFFFA00C0 ); + -( TCB ) TC Block Control Register +/* - ========== Register definition for CAN_MB0 peripheral ========== */ + AT91C_CAN_MB0_MDL EQU( 0xFFFD0214 ); + -( CAN_MB0 ) MailBox Data Low Register + AT91C_CAN_MB0_MAM EQU( 0xFFFD0204 ); + -( CAN_MB0 ) MailBox Acceptance Mask Register + AT91C_CAN_MB0_MCR EQU( 0xFFFD021C ); + -( CAN_MB0 ) MailBox Control Register + AT91C_CAN_MB0_MID EQU( 0xFFFD0208 ); + -( CAN_MB0 ) MailBox ID Register + AT91C_CAN_MB0_MSR EQU( 0xFFFD0210 ); + -( CAN_MB0 ) MailBox Status Register + AT91C_CAN_MB0_MFID EQU( 0xFFFD020C ); + -( CAN_MB0 ) MailBox Family ID Register + AT91C_CAN_MB0_MDH EQU( 0xFFFD0218 ); + -( CAN_MB0 ) MailBox Data High Register + AT91C_CAN_MB0_MMR EQU( 0xFFFD0200 ); + -( CAN_MB0 ) MailBox Mode Register +/* - ========== Register definition for CAN_MB1 peripheral ========== */ + AT91C_CAN_MB1_MDL EQU( 0xFFFD0234 ); + -( CAN_MB1 ) MailBox Data Low Register + AT91C_CAN_MB1_MID EQU( 0xFFFD0228 ); + -( CAN_MB1 ) MailBox ID Register + AT91C_CAN_MB1_MMR EQU( 0xFFFD0220 ); + -( CAN_MB1 ) MailBox Mode Register + AT91C_CAN_MB1_MSR EQU( 0xFFFD0230 ); + -( CAN_MB1 ) MailBox Status Register + AT91C_CAN_MB1_MAM EQU( 0xFFFD0224 ); + -( CAN_MB1 ) MailBox Acceptance Mask Register + AT91C_CAN_MB1_MDH EQU( 0xFFFD0238 ); + -( CAN_MB1 ) MailBox Data High Register + AT91C_CAN_MB1_MCR EQU( 0xFFFD023C ); + -( CAN_MB1 ) MailBox Control Register + AT91C_CAN_MB1_MFID EQU( 0xFFFD022C ); + -( CAN_MB1 ) MailBox Family ID Register +/* - ========== Register definition for CAN_MB2 peripheral ========== */ + AT91C_CAN_MB2_MCR EQU( 0xFFFD025C ); + -( CAN_MB2 ) MailBox Control Register + AT91C_CAN_MB2_MDH EQU( 0xFFFD0258 ); + -( CAN_MB2 ) MailBox Data High Register + AT91C_CAN_MB2_MID EQU( 0xFFFD0248 ); + -( CAN_MB2 ) MailBox ID Register + AT91C_CAN_MB2_MDL EQU( 0xFFFD0254 ); + -( CAN_MB2 ) MailBox Data Low Register + AT91C_CAN_MB2_MMR EQU( 0xFFFD0240 ); + -( CAN_MB2 ) MailBox Mode Register + AT91C_CAN_MB2_MAM EQU( 0xFFFD0244 ); + -( CAN_MB2 ) MailBox Acceptance Mask Register + AT91C_CAN_MB2_MFID EQU( 0xFFFD024C ); + -( CAN_MB2 ) MailBox Family ID Register + AT91C_CAN_MB2_MSR EQU( 0xFFFD0250 ); + -( CAN_MB2 ) MailBox Status Register +/* - ========== Register definition for CAN_MB3 peripheral ========== */ + AT91C_CAN_MB3_MFID EQU( 0xFFFD026C ); + -( CAN_MB3 ) MailBox Family ID Register + AT91C_CAN_MB3_MAM EQU( 0xFFFD0264 ); + -( CAN_MB3 ) MailBox Acceptance Mask Register + AT91C_CAN_MB3_MID EQU( 0xFFFD0268 ); + -( CAN_MB3 ) MailBox ID Register + AT91C_CAN_MB3_MCR EQU( 0xFFFD027C ); + -( CAN_MB3 ) MailBox Control Register + AT91C_CAN_MB3_MMR EQU( 0xFFFD0260 ); + -( CAN_MB3 ) MailBox Mode Register + AT91C_CAN_MB3_MSR EQU( 0xFFFD0270 ); + -( CAN_MB3 ) MailBox Status Register + AT91C_CAN_MB3_MDL EQU( 0xFFFD0274 ); + -( CAN_MB3 ) MailBox Data Low Register + AT91C_CAN_MB3_MDH EQU( 0xFFFD0278 ); + -( CAN_MB3 ) MailBox Data High Register +/* - ========== Register definition for CAN_MB4 peripheral ========== */ + AT91C_CAN_MB4_MID EQU( 0xFFFD0288 ); + -( CAN_MB4 ) MailBox ID Register + AT91C_CAN_MB4_MMR EQU( 0xFFFD0280 ); + -( CAN_MB4 ) MailBox Mode Register + AT91C_CAN_MB4_MDH EQU( 0xFFFD0298 ); + -( CAN_MB4 ) MailBox Data High Register + AT91C_CAN_MB4_MFID EQU( 0xFFFD028C ); + -( CAN_MB4 ) MailBox Family ID Register + AT91C_CAN_MB4_MSR EQU( 0xFFFD0290 ); + -( CAN_MB4 ) MailBox Status Register + AT91C_CAN_MB4_MCR EQU( 0xFFFD029C ); + -( CAN_MB4 ) MailBox Control Register + AT91C_CAN_MB4_MDL EQU( 0xFFFD0294 ); + -( CAN_MB4 ) MailBox Data Low Register + AT91C_CAN_MB4_MAM EQU( 0xFFFD0284 ); + -( CAN_MB4 ) MailBox Acceptance Mask Register +/* - ========== Register definition for CAN_MB5 peripheral ========== */ + AT91C_CAN_MB5_MSR EQU( 0xFFFD02B0 ); + -( CAN_MB5 ) MailBox Status Register + AT91C_CAN_MB5_MCR EQU( 0xFFFD02BC ); + -( CAN_MB5 ) MailBox Control Register + AT91C_CAN_MB5_MFID EQU( 0xFFFD02AC ); + -( CAN_MB5 ) MailBox Family ID Register + AT91C_CAN_MB5_MDH EQU( 0xFFFD02B8 ); + -( CAN_MB5 ) MailBox Data High Register + AT91C_CAN_MB5_MID EQU( 0xFFFD02A8 ); + -( CAN_MB5 ) MailBox ID Register + AT91C_CAN_MB5_MMR EQU( 0xFFFD02A0 ); + -( CAN_MB5 ) MailBox Mode Register + AT91C_CAN_MB5_MDL EQU( 0xFFFD02B4 ); + -( CAN_MB5 ) MailBox Data Low Register + AT91C_CAN_MB5_MAM EQU( 0xFFFD02A4 ); + -( CAN_MB5 ) MailBox Acceptance Mask Register +/* - ========== Register definition for CAN_MB6 peripheral ========== */ + AT91C_CAN_MB6_MFID EQU( 0xFFFD02CC ); + -( CAN_MB6 ) MailBox Family ID Register + AT91C_CAN_MB6_MID EQU( 0xFFFD02C8 ); + -( CAN_MB6 ) MailBox ID Register + AT91C_CAN_MB6_MAM EQU( 0xFFFD02C4 ); + -( CAN_MB6 ) MailBox Acceptance Mask Register + AT91C_CAN_MB6_MSR EQU( 0xFFFD02D0 ); + -( CAN_MB6 ) MailBox Status Register + AT91C_CAN_MB6_MDL EQU( 0xFFFD02D4 ); + -( CAN_MB6 ) MailBox Data Low Register + AT91C_CAN_MB6_MCR EQU( 0xFFFD02DC ); + -( CAN_MB6 ) MailBox Control Register + AT91C_CAN_MB6_MDH EQU( 0xFFFD02D8 ); + -( CAN_MB6 ) MailBox Data High Register + AT91C_CAN_MB6_MMR EQU( 0xFFFD02C0 ); + -( CAN_MB6 ) MailBox Mode Register +/* - ========== Register definition for CAN_MB7 peripheral ========== */ + AT91C_CAN_MB7_MCR EQU( 0xFFFD02FC ); + -( CAN_MB7 ) MailBox Control Register + AT91C_CAN_MB7_MDH EQU( 0xFFFD02F8 ); + -( CAN_MB7 ) MailBox Data High Register + AT91C_CAN_MB7_MFID EQU( 0xFFFD02EC ); + -( CAN_MB7 ) MailBox Family ID Register + AT91C_CAN_MB7_MDL EQU( 0xFFFD02F4 ); + -( CAN_MB7 ) MailBox Data Low Register + AT91C_CAN_MB7_MID EQU( 0xFFFD02E8 ); + -( CAN_MB7 ) MailBox ID Register + AT91C_CAN_MB7_MMR EQU( 0xFFFD02E0 ); + -( CAN_MB7 ) MailBox Mode Register + AT91C_CAN_MB7_MAM EQU( 0xFFFD02E4 ); + -( CAN_MB7 ) MailBox Acceptance Mask Register + AT91C_CAN_MB7_MSR EQU( 0xFFFD02F0 ); + -( CAN_MB7 ) MailBox Status Register +/* - ========== Register definition for CAN peripheral ========== */ + AT91C_CAN_TCR EQU( 0xFFFD0024 ); + -( CAN ) Transfer Command Register + AT91C_CAN_IMR EQU( 0xFFFD000C ); + -( CAN ) Interrupt Mask Register + AT91C_CAN_IER EQU( 0xFFFD0004 ); + -( CAN ) Interrupt Enable Register + AT91C_CAN_ECR EQU( 0xFFFD0020 ); + -( CAN ) Error Counter Register + AT91C_CAN_TIMESTP EQU( 0xFFFD001C ); + -( CAN ) Time Stamp Register + AT91C_CAN_MR EQU( 0xFFFD0000 ); + -( CAN ) Mode Register + AT91C_CAN_IDR EQU( 0xFFFD0008 ); + -( CAN ) Interrupt Disable Register + AT91C_CAN_ACR EQU( 0xFFFD0028 ); + -( CAN ) Abort Command Register + AT91C_CAN_TIM EQU( 0xFFFD0018 ); + -( CAN ) Timer Register + AT91C_CAN_SR EQU( 0xFFFD0010 ); + -( CAN ) Status Register + AT91C_CAN_BR EQU( 0xFFFD0014 ); + -( CAN ) Baudrate Register + AT91C_CAN_VR EQU( 0xFFFD00FC ); + -( CAN ) Version Register +/* - ========== Register definition for EMAC peripheral ========== */ + AT91C_EMAC_ISR EQU( 0xFFFDC024 ); + -( EMAC ) Interrupt Status Register + AT91C_EMAC_SA4H EQU( 0xFFFDC0B4 ); + -( EMAC ) Specific Address 4 Top, Last 2 bytes + AT91C_EMAC_SA1L EQU( 0xFFFDC098 ); + -( EMAC ) Specific Address 1 Bottom, First 4 bytes + AT91C_EMAC_ELE EQU( 0xFFFDC078 ); + -( EMAC ) Excessive Length Errors Register + AT91C_EMAC_LCOL EQU( 0xFFFDC05C ); + -( EMAC ) Late Collision Register + AT91C_EMAC_RLE EQU( 0xFFFDC088 ); + -( EMAC ) Receive Length Field Mismatch Register + AT91C_EMAC_WOL EQU( 0xFFFDC0C4 ); + -( EMAC ) Wake On LAN Register + AT91C_EMAC_DTF EQU( 0xFFFDC058 ); + -( EMAC ) Deferred Transmission Frame Register + AT91C_EMAC_TUND EQU( 0xFFFDC064 ); + -( EMAC ) Transmit Underrun Error Register + AT91C_EMAC_NCR EQU( 0xFFFDC000 ); + -( EMAC ) Network Control Register + AT91C_EMAC_SA4L EQU( 0xFFFDC0B0 ); + -( EMAC ) Specific Address 4 Bottom, First 4 bytes + AT91C_EMAC_RSR EQU( 0xFFFDC020 ); + -( EMAC ) Receive Status Register + AT91C_EMAC_SA3L EQU( 0xFFFDC0A8 ); + -( EMAC ) Specific Address 3 Bottom, First 4 bytes + AT91C_EMAC_TSR EQU( 0xFFFDC014 ); + -( EMAC ) Transmit Status Register + AT91C_EMAC_IDR EQU( 0xFFFDC02C ); + -( EMAC ) Interrupt Disable Register + AT91C_EMAC_RSE EQU( 0xFFFDC074 ); + -( EMAC ) Receive Symbol Errors Register + AT91C_EMAC_ECOL EQU( 0xFFFDC060 ); + -( EMAC ) Excessive Collision Register + AT91C_EMAC_TID EQU( 0xFFFDC0B8 ); + -( EMAC ) Type ID Checking Register + AT91C_EMAC_HRB EQU( 0xFFFDC090 ); + -( EMAC ) Hash Address Bottom[ 31 : 0 ] + AT91C_EMAC_TBQP EQU( 0xFFFDC01C ); + -( EMAC ) Transmit Buffer Queue Pointer + AT91C_EMAC_USRIO EQU( 0xFFFDC0C0 ); + -( EMAC ) USER Input / Output Register + AT91C_EMAC_PTR EQU( 0xFFFDC038 ); + -( EMAC ) Pause Time Register + AT91C_EMAC_SA2H EQU( 0xFFFDC0A4 ); + -( EMAC ) Specific Address 2 Top, Last 2 bytes + AT91C_EMAC_ROV EQU( 0xFFFDC070 ); + -( EMAC ) Receive Overrun Errors Register + AT91C_EMAC_ALE EQU( 0xFFFDC054 ); + -( EMAC ) Alignment Error Register + AT91C_EMAC_RJA EQU( 0xFFFDC07C ); + -( EMAC ) Receive Jabbers Register + AT91C_EMAC_RBQP EQU( 0xFFFDC018 ); + -( EMAC ) Receive Buffer Queue Pointer + AT91C_EMAC_TPF EQU( 0xFFFDC08C ); + -( EMAC ) Transmitted Pause Frames Register + AT91C_EMAC_NCFGR EQU( 0xFFFDC004 ); + -( EMAC ) Network Configuration Register + AT91C_EMAC_HRT EQU( 0xFFFDC094 ); + -( EMAC ) Hash Address Top[ 63 : 32 ] + AT91C_EMAC_USF EQU( 0xFFFDC080 ); + -( EMAC ) Undersize Frames Register + AT91C_EMAC_FCSE EQU( 0xFFFDC050 ); + -( EMAC ) Frame Check Sequence Error Register + AT91C_EMAC_TPQ EQU( 0xFFFDC0BC ); + -( EMAC ) Transmit Pause Quantum Register + AT91C_EMAC_MAN EQU( 0xFFFDC034 ); + -( EMAC ) PHY Maintenance Register + AT91C_EMAC_FTO EQU( 0xFFFDC040 ); + -( EMAC ) Frames Transmitted OK Register + AT91C_EMAC_REV EQU( 0xFFFDC0FC ); + -( EMAC ) Revision Register + AT91C_EMAC_IMR EQU( 0xFFFDC030 ); + -( EMAC ) Interrupt Mask Register + AT91C_EMAC_SCF EQU( 0xFFFDC044 ); + -( EMAC ) Single Collision Frame Register + AT91C_EMAC_PFR EQU( 0xFFFDC03C ); + -( EMAC ) Pause Frames received Register + AT91C_EMAC_MCF EQU( 0xFFFDC048 ); + -( EMAC ) Multiple Collision Frame Register + AT91C_EMAC_NSR EQU( 0xFFFDC008 ); + -( EMAC ) Network Status Register + AT91C_EMAC_SA2L EQU( 0xFFFDC0A0 ); + -( EMAC ) Specific Address 2 Bottom, First 4 bytes + AT91C_EMAC_FRO EQU( 0xFFFDC04C ); + -( EMAC ) Frames Received OK Register + AT91C_EMAC_IER EQU( 0xFFFDC028 ); + -( EMAC ) Interrupt Enable Register + AT91C_EMAC_SA1H EQU( 0xFFFDC09C ); + -( EMAC ) Specific Address 1 Top, Last 2 bytes + AT91C_EMAC_CSE EQU( 0xFFFDC068 ); + -( EMAC ) Carrier Sense Error Register + AT91C_EMAC_SA3H EQU( 0xFFFDC0AC ); + -( EMAC ) Specific Address 3 Top, Last 2 bytes + AT91C_EMAC_RRE EQU( 0xFFFDC06C ); + -( EMAC ) Receive Ressource Error Register + AT91C_EMAC_STE EQU( 0xFFFDC084 ); + -( EMAC ) SQE Test Error Register +/* - ========== Register definition for PDC_ADC peripheral ========== */ + AT91C_ADC_PTSR EQU( 0xFFFD8124 ); + -( PDC_ADC ) PDC Transfer Status Register + AT91C_ADC_PTCR EQU( 0xFFFD8120 ); + -( PDC_ADC ) PDC Transfer Control Register + AT91C_ADC_TNPR EQU( 0xFFFD8118 ); + -( PDC_ADC ) Transmit Next Pointer Register + AT91C_ADC_TNCR EQU( 0xFFFD811C ); + -( PDC_ADC ) Transmit Next Counter Register + AT91C_ADC_RNPR EQU( 0xFFFD8110 ); + -( PDC_ADC ) Receive Next Pointer Register + AT91C_ADC_RNCR EQU( 0xFFFD8114 ); + -( PDC_ADC ) Receive Next Counter Register + AT91C_ADC_RPR EQU( 0xFFFD8100 ); + -( PDC_ADC ) Receive Pointer Register + AT91C_ADC_TCR EQU( 0xFFFD810C ); + -( PDC_ADC ) Transmit Counter Register + AT91C_ADC_TPR EQU( 0xFFFD8108 ); + -( PDC_ADC ) Transmit Pointer Register + AT91C_ADC_RCR EQU( 0xFFFD8104 ); + -( PDC_ADC ) Receive Counter Register +/* - ========== Register definition for ADC peripheral ========== */ + AT91C_ADC_CDR2 EQU( 0xFFFD8038 ); + -( ADC ) ADC Channel Data Register 2 + AT91C_ADC_CDR3 EQU( 0xFFFD803C ); + -( ADC ) ADC Channel Data Register 3 + AT91C_ADC_CDR0 EQU( 0xFFFD8030 ); + -( ADC ) ADC Channel Data Register 0 + AT91C_ADC_CDR5 EQU( 0xFFFD8044 ); + -( ADC ) ADC Channel Data Register 5 + AT91C_ADC_CHDR EQU( 0xFFFD8014 ); + -( ADC ) ADC Channel Disable Register + AT91C_ADC_SR EQU( 0xFFFD801C ); + -( ADC ) ADC Status Register + AT91C_ADC_CDR4 EQU( 0xFFFD8040 ); + -( ADC ) ADC Channel Data Register 4 + AT91C_ADC_CDR1 EQU( 0xFFFD8034 ); + -( ADC ) ADC Channel Data Register 1 + AT91C_ADC_LCDR EQU( 0xFFFD8020 ); + -( ADC ) ADC Last Converted Data Register + AT91C_ADC_IDR EQU( 0xFFFD8028 ); + -( ADC ) ADC Interrupt Disable Register + AT91C_ADC_CR EQU( 0xFFFD8000 ); + -( ADC ) ADC Control Register + AT91C_ADC_CDR7 EQU( 0xFFFD804C ); + -( ADC ) ADC Channel Data Register 7 + AT91C_ADC_CDR6 EQU( 0xFFFD8048 ); + -( ADC ) ADC Channel Data Register 6 + AT91C_ADC_IER EQU( 0xFFFD8024 ); + -( ADC ) ADC Interrupt Enable Register + AT91C_ADC_CHER EQU( 0xFFFD8010 ); + -( ADC ) ADC Channel Enable Register + AT91C_ADC_CHSR EQU( 0xFFFD8018 ); + -( ADC ) ADC Channel Status Register + AT91C_ADC_MR EQU( 0xFFFD8004 ); + -( ADC ) ADC Mode Register + AT91C_ADC_IMR EQU( 0xFFFD802C ); + -( ADC ) ADC Interrupt Mask Register +/* - ========== Register definition for PDC_AES peripheral ========== */ + AT91C_AES_TPR EQU( 0xFFFA4108 ); + -( PDC_AES ) Transmit Pointer Register + AT91C_AES_PTCR EQU( 0xFFFA4120 ); + -( PDC_AES ) PDC Transfer Control Register + AT91C_AES_RNPR EQU( 0xFFFA4110 ); + -( PDC_AES ) Receive Next Pointer Register + AT91C_AES_TNCR EQU( 0xFFFA411C ); + -( PDC_AES ) Transmit Next Counter Register + AT91C_AES_TCR EQU( 0xFFFA410C ); + -( PDC_AES ) Transmit Counter Register + AT91C_AES_RCR EQU( 0xFFFA4104 ); + -( PDC_AES ) Receive Counter Register + AT91C_AES_RNCR EQU( 0xFFFA4114 ); + -( PDC_AES ) Receive Next Counter Register + AT91C_AES_TNPR EQU( 0xFFFA4118 ); + -( PDC_AES ) Transmit Next Pointer Register + AT91C_AES_RPR EQU( 0xFFFA4100 ); + -( PDC_AES ) Receive Pointer Register + AT91C_AES_PTSR EQU( 0xFFFA4124 ); + -( PDC_AES ) PDC Transfer Status Register +/* - ========== Register definition for AES peripheral ========== */ + AT91C_AES_IVxR EQU( 0xFFFA4060 ); + -( AES ) Initialization Vector x Register + AT91C_AES_MR EQU( 0xFFFA4004 ); + -( AES ) Mode Register + AT91C_AES_VR EQU( 0xFFFA40FC ); + -( AES ) AES Version Register + AT91C_AES_ODATAxR EQU( 0xFFFA4050 ); + -( AES ) Output Data x Register + AT91C_AES_IDATAxR EQU( 0xFFFA4040 ); + -( AES ) Input Data x Register + AT91C_AES_CR EQU( 0xFFFA4000 ); + -( AES ) Control Register + AT91C_AES_IDR EQU( 0xFFFA4014 ); + -( AES ) Interrupt Disable Register + AT91C_AES_IMR EQU( 0xFFFA4018 ); + -( AES ) Interrupt Mask Register + AT91C_AES_IER EQU( 0xFFFA4010 ); + -( AES ) Interrupt Enable Register + AT91C_AES_KEYWxR EQU( 0xFFFA4020 ); + -( AES ) Key Word x Register + AT91C_AES_ISR EQU( 0xFFFA401C ); + -( AES ) Interrupt Status Register +/* - ========== Register definition for PDC_TDES peripheral ========== */ + AT91C_TDES_RNCR EQU( 0xFFFA8114 ); + -( PDC_TDES ) Receive Next Counter Register + AT91C_TDES_TCR EQU( 0xFFFA810C ); + -( PDC_TDES ) Transmit Counter Register + AT91C_TDES_RCR EQU( 0xFFFA8104 ); + -( PDC_TDES ) Receive Counter Register + AT91C_TDES_TNPR EQU( 0xFFFA8118 ); + -( PDC_TDES ) Transmit Next Pointer Register + AT91C_TDES_RNPR EQU( 0xFFFA8110 ); + -( PDC_TDES ) Receive Next Pointer Register + AT91C_TDES_RPR EQU( 0xFFFA8100 ); + -( PDC_TDES ) Receive Pointer Register + AT91C_TDES_TNCR EQU( 0xFFFA811C ); + -( PDC_TDES ) Transmit Next Counter Register + AT91C_TDES_TPR EQU( 0xFFFA8108 ); + -( PDC_TDES ) Transmit Pointer Register + AT91C_TDES_PTSR EQU( 0xFFFA8124 ); + -( PDC_TDES ) PDC Transfer Status Register + AT91C_TDES_PTCR EQU( 0xFFFA8120 ); + -( PDC_TDES ) PDC Transfer Control Register +/* - ========== Register definition for TDES peripheral ========== */ + AT91C_TDES_KEY2WxR EQU( 0xFFFA8028 ); + -( TDES ) Key 2 Word x Register + AT91C_TDES_KEY3WxR EQU( 0xFFFA8030 ); + -( TDES ) Key 3 Word x Register + AT91C_TDES_IDR EQU( 0xFFFA8014 ); + -( TDES ) Interrupt Disable Register + AT91C_TDES_VR EQU( 0xFFFA80FC ); + -( TDES ) TDES Version Register + AT91C_TDES_IVxR EQU( 0xFFFA8060 ); + -( TDES ) Initialization Vector x Register + AT91C_TDES_ODATAxR EQU( 0xFFFA8050 ); + -( TDES ) Output Data x Register + AT91C_TDES_IMR EQU( 0xFFFA8018 ); + -( TDES ) Interrupt Mask Register + AT91C_TDES_MR EQU( 0xFFFA8004 ); + -( TDES ) Mode Register + AT91C_TDES_CR EQU( 0xFFFA8000 ); + -( TDES ) Control Register + AT91C_TDES_IER EQU( 0xFFFA8010 ); + -( TDES ) Interrupt Enable Register + AT91C_TDES_ISR EQU( 0xFFFA801C ); + -( TDES ) Interrupt Status Register + AT91C_TDES_IDATAxR EQU( 0xFFFA8040 ); + -( TDES ) Input Data x Register + AT91C_TDES_KEY1WxR EQU( 0xFFFA8020 ); + -( TDES ) Key 1 Word x Register + +/* - ***************************************************************************** */ +/* - PIO DEFINITIONS FOR AT91SAM7X256 */ +/* - ***************************************************************************** */ + AT91C_PIO_PA0 EQU( 1 << 0 ); + -Pin Controlled by PA0 + AT91C_PA0_RXD0 EQU( AT91C_PIO_PA0 ); + -USART 0 Receive Data + AT91C_PIO_PA1 EQU( 1 << 1 ); + -Pin Controlled by PA1 + AT91C_PA1_TXD0 EQU( AT91C_PIO_PA1 ); + -USART 0 Transmit Data + AT91C_PIO_PA10 EQU( 1 << 10 ); + -Pin Controlled by PA10 + AT91C_PA10_TWD EQU( AT91C_PIO_PA10 ); + -TWI Two - wire Serial Data + AT91C_PIO_PA11 EQU( 1 << 11 ); + -Pin Controlled by PA11 + AT91C_PA11_TWCK EQU( AT91C_PIO_PA11 ); + -TWI Two - wire Serial Clock + AT91C_PIO_PA12 EQU( 1 << 12 ); + -Pin Controlled by PA12 + AT91C_PA12_NPCS00 EQU( AT91C_PIO_PA12 ); + -SPI 0 Peripheral Chip Select 0 + AT91C_PIO_PA13 EQU( 1 << 13 ); + -Pin Controlled by PA13 + AT91C_PA13_NPCS01 EQU( AT91C_PIO_PA13 ); + -SPI 0 Peripheral Chip Select 1 + AT91C_PA13_PCK1 EQU( AT91C_PIO_PA13 ); + -PMC Programmable Clock Output 1 + AT91C_PIO_PA14 EQU( 1 << 14 ); + -Pin Controlled by PA14 + AT91C_PA14_NPCS02 EQU( AT91C_PIO_PA14 ); + -SPI 0 Peripheral Chip Select 2 + AT91C_PA14_IRQ1 EQU( AT91C_PIO_PA14 ); + -External Interrupt 1 + AT91C_PIO_PA15 EQU( 1 << 15 ); + -Pin Controlled by PA15 + AT91C_PA15_NPCS03 EQU( AT91C_PIO_PA15 ); + -SPI 0 Peripheral Chip Select 3 + AT91C_PA15_TCLK2 EQU( AT91C_PIO_PA15 ); + -Timer Counter 2 external clock input + AT91C_PIO_PA16 EQU( 1 << 16 ); + -Pin Controlled by PA16 + AT91C_PA16_MISO0 EQU( AT91C_PIO_PA16 ); + -SPI 0 Master In Slave + AT91C_PIO_PA17 EQU( 1 << 17 ); + -Pin Controlled by PA17 + AT91C_PA17_MOSI0 EQU( AT91C_PIO_PA17 ); + -SPI 0 Master Out Slave + AT91C_PIO_PA18 EQU( 1 << 18 ); + -Pin Controlled by PA18 + AT91C_PA18_SPCK0 EQU( AT91C_PIO_PA18 ); + -SPI 0 Serial Clock + AT91C_PIO_PA19 EQU( 1 << 19 ); + -Pin Controlled by PA19 + AT91C_PA19_CANRX EQU( AT91C_PIO_PA19 ); + -CAN Receive + AT91C_PIO_PA2 EQU( 1 << 2 ); + -Pin Controlled by PA2 + AT91C_PA2_SCK0 EQU( AT91C_PIO_PA2 ); + -USART 0 Serial Clock + AT91C_PA2_NPCS11 EQU( AT91C_PIO_PA2 ); + -SPI 1 Peripheral Chip Select 1 + AT91C_PIO_PA20 EQU( 1 << 20 ); + -Pin Controlled by PA20 + AT91C_PA20_CANTX EQU( AT91C_PIO_PA20 ); + -CAN Transmit + AT91C_PIO_PA21 EQU( 1 << 21 ); + -Pin Controlled by PA21 + AT91C_PA21_TF EQU( AT91C_PIO_PA21 ); + -SSC Transmit Frame Sync + AT91C_PA21_NPCS10 EQU( AT91C_PIO_PA21 ); + -SPI 1 Peripheral Chip Select 0 + AT91C_PIO_PA22 EQU( 1 << 22 ); + -Pin Controlled by PA22 + AT91C_PA22_TK EQU( AT91C_PIO_PA22 ); + -SSC Transmit Clock + AT91C_PA22_SPCK1 EQU( AT91C_PIO_PA22 ); + -SPI 1 Serial Clock + AT91C_PIO_PA23 EQU( 1 << 23 ); + -Pin Controlled by PA23 + AT91C_PA23_TD EQU( AT91C_PIO_PA23 ); + -SSC Transmit data + AT91C_PA23_MOSI1 EQU( AT91C_PIO_PA23 ); + -SPI 1 Master Out Slave + AT91C_PIO_PA24 EQU( 1 << 24 ); + -Pin Controlled by PA24 + AT91C_PA24_RD EQU( AT91C_PIO_PA24 ); + -SSC Receive Data + AT91C_PA24_MISO1 EQU( AT91C_PIO_PA24 ); + -SPI 1 Master In Slave + AT91C_PIO_PA25 EQU( 1 << 25 ); + -Pin Controlled by PA25 + AT91C_PA25_RK EQU( AT91C_PIO_PA25 ); + -SSC Receive Clock + AT91C_PA25_NPCS11 EQU( AT91C_PIO_PA25 ); + -SPI 1 Peripheral Chip Select 1 + AT91C_PIO_PA26 EQU( 1 << 26 ); + -Pin Controlled by PA26 + AT91C_PA26_RF EQU( AT91C_PIO_PA26 ); + -SSC Receive Frame Sync + AT91C_PA26_NPCS12 EQU( AT91C_PIO_PA26 ); + -SPI 1 Peripheral Chip Select 2 + AT91C_PIO_PA27 EQU( 1 << 27 ); + -Pin Controlled by PA27 + AT91C_PA27_DRXD EQU( AT91C_PIO_PA27 ); + -DBGU Debug Receive Data + AT91C_PA27_PCK3 EQU( AT91C_PIO_PA27 ); + -PMC Programmable Clock Output 3 + AT91C_PIO_PA28 EQU( 1 << 28 ); + -Pin Controlled by PA28 + AT91C_PA28_DTXD EQU( AT91C_PIO_PA28 ); + -DBGU Debug Transmit Data + AT91C_PIO_PA29 EQU( 1 << 29 ); + -Pin Controlled by PA29 + AT91C_PA29_FIQ EQU( AT91C_PIO_PA29 ); + -AIC Fast Interrupt Input + AT91C_PA29_NPCS13 EQU( AT91C_PIO_PA29 ); + -SPI 1 Peripheral Chip Select 3 + AT91C_PIO_PA3 EQU( 1 << 3 ); + -Pin Controlled by PA3 + AT91C_PA3_RTS0 EQU( AT91C_PIO_PA3 ); + -USART 0 Ready To Send + AT91C_PA3_NPCS12 EQU( AT91C_PIO_PA3 ); + -SPI 1 Peripheral Chip Select 2 + AT91C_PIO_PA30 EQU( 1 << 30 ); + -Pin Controlled by PA30 + AT91C_PA30_IRQ0 EQU( AT91C_PIO_PA30 ); + -External Interrupt 0 + AT91C_PA30_PCK2 EQU( AT91C_PIO_PA30 ); + -PMC Programmable Clock Output 2 + AT91C_PIO_PA4 EQU( 1 << 4 ); + -Pin Controlled by PA4 + AT91C_PA4_CTS0 EQU( AT91C_PIO_PA4 ); + -USART 0 Clear To Send + AT91C_PA4_NPCS13 EQU( AT91C_PIO_PA4 ); + -SPI 1 Peripheral Chip Select 3 + AT91C_PIO_PA5 EQU( 1 << 5 ); + -Pin Controlled by PA5 + AT91C_PA5_RXD1 EQU( AT91C_PIO_PA5 ); + -USART 1 Receive Data + AT91C_PIO_PA6 EQU( 1 << 6 ); + -Pin Controlled by PA6 + AT91C_PA6_TXD1 EQU( AT91C_PIO_PA6 ); + -USART 1 Transmit Data + AT91C_PIO_PA7 EQU( 1 << 7 ); + -Pin Controlled by PA7 + AT91C_PA7_SCK1 EQU( AT91C_PIO_PA7 ); + -USART 1 Serial Clock + AT91C_PA7_NPCS01 EQU( AT91C_PIO_PA7 ); + -SPI 0 Peripheral Chip Select 1 + AT91C_PIO_PA8 EQU( 1 << 8 ); + -Pin Controlled by PA8 + AT91C_PA8_RTS1 EQU( AT91C_PIO_PA8 ); + -USART 1 Ready To Send + AT91C_PA8_NPCS02 EQU( AT91C_PIO_PA8 ); + -SPI 0 Peripheral Chip Select 2 + AT91C_PIO_PA9 EQU( 1 << 9 ); + -Pin Controlled by PA9 + AT91C_PA9_CTS1 EQU( AT91C_PIO_PA9 ); + -USART 1 Clear To Send + AT91C_PA9_NPCS03 EQU( AT91C_PIO_PA9 ); + -SPI 0 Peripheral Chip Select 3 + AT91C_PIO_PB0 EQU( 1 << 0 ); + -Pin Controlled by PB0 + AT91C_PB0_ETXCK_EREFCK EQU( AT91C_PIO_PB0 ); + -Ethernet MAC Transmit Clock / Reference Clock + AT91C_PB0_PCK0 EQU( AT91C_PIO_PB0 ); + -PMC Programmable Clock Output 0 + AT91C_PIO_PB1 EQU( 1 << 1 ); + -Pin Controlled by PB1 + AT91C_PB1_ETXEN EQU( AT91C_PIO_PB1 ); + -Ethernet MAC Transmit Enable + AT91C_PIO_PB10 EQU( 1 << 10 ); + -Pin Controlled by PB10 + AT91C_PB10_ETX2 EQU( AT91C_PIO_PB10 ); + -Ethernet MAC Transmit Data 2 + AT91C_PB10_NPCS11 EQU( AT91C_PIO_PB10 ); + -SPI 1 Peripheral Chip Select 1 + AT91C_PIO_PB11 EQU( 1 << 11 ); + -Pin Controlled by PB11 + AT91C_PB11_ETX3 EQU( AT91C_PIO_PB11 ); + -Ethernet MAC Transmit Data 3 + AT91C_PB11_NPCS12 EQU( AT91C_PIO_PB11 ); + -SPI 1 Peripheral Chip Select 2 + AT91C_PIO_PB12 EQU( 1 << 12 ); + -Pin Controlled by PB12 + AT91C_PB12_ETXER EQU( AT91C_PIO_PB12 ); + -Ethernet MAC Transmit Coding Error + AT91C_PB12_TCLK0 EQU( AT91C_PIO_PB12 ); + -Timer Counter 0 external clock input + AT91C_PIO_PB13 EQU( 1 << 13 ); + -Pin Controlled by PB13 + AT91C_PB13_ERX2 EQU( AT91C_PIO_PB13 ); + -Ethernet MAC Receive Data 2 + AT91C_PB13_NPCS01 EQU( AT91C_PIO_PB13 ); + -SPI 0 Peripheral Chip Select 1 + AT91C_PIO_PB14 EQU( 1 << 14 ); + -Pin Controlled by PB14 + AT91C_PB14_ERX3 EQU( AT91C_PIO_PB14 ); + -Ethernet MAC Receive Data 3 + AT91C_PB14_NPCS02 EQU( AT91C_PIO_PB14 ); + -SPI 0 Peripheral Chip Select 2 + AT91C_PIO_PB15 EQU( 1 << 15 ); + -Pin Controlled by PB15 + AT91C_PB15_ERXDV EQU( AT91C_PIO_PB15 ); + -Ethernet MAC Receive Data Valid + AT91C_PIO_PB16 EQU( 1 << 16 ); + -Pin Controlled by PB16 + AT91C_PB16_ECOL EQU( AT91C_PIO_PB16 ); + -Ethernet MAC Collision Detected + AT91C_PB16_NPCS13 EQU( AT91C_PIO_PB16 ); + -SPI 1 Peripheral Chip Select 3 + AT91C_PIO_PB17 EQU( 1 << 17 ); + -Pin Controlled by PB17 + AT91C_PB17_ERXCK EQU( AT91C_PIO_PB17 ); + -Ethernet MAC Receive Clock + AT91C_PB17_NPCS03 EQU( AT91C_PIO_PB17 ); + -SPI 0 Peripheral Chip Select 3 + AT91C_PIO_PB18 EQU( 1 << 18 ); + -Pin Controlled by PB18 + AT91C_PB18_EF100 EQU( AT91C_PIO_PB18 ); + -Ethernet MAC Force 100 Mbits / sec + AT91C_PB18_ADTRG EQU( AT91C_PIO_PB18 ); + -ADC External Trigger + AT91C_PIO_PB19 EQU( 1 << 19 ); + -Pin Controlled by PB19 + AT91C_PB19_PWM0 EQU( AT91C_PIO_PB19 ); + -PWM Channel 0 + AT91C_PB19_TCLK1 EQU( AT91C_PIO_PB19 ); + -Timer Counter 1 external clock input + AT91C_PIO_PB2 EQU( 1 << 2 ); + -Pin Controlled by PB2 + AT91C_PB2_ETX0 EQU( AT91C_PIO_PB2 ); + -Ethernet MAC Transmit Data 0 + AT91C_PIO_PB20 EQU( 1 << 20 ); + -Pin Controlled by PB20 + AT91C_PB20_PWM1 EQU( AT91C_PIO_PB20 ); + -PWM Channel 1 + AT91C_PB20_PCK0 EQU( AT91C_PIO_PB20 ); + -PMC Programmable Clock Output 0 + AT91C_PIO_PB21 EQU( 1 << 21 ); + -Pin Controlled by PB21 + AT91C_PB21_PWM2 EQU( AT91C_PIO_PB21 ); + -PWM Channel 2 + AT91C_PB21_PCK1 EQU( AT91C_PIO_PB21 ); + -PMC Programmable Clock Output 1 + AT91C_PIO_PB22 EQU( 1 << 22 ); + -Pin Controlled by PB22 + AT91C_PB22_PWM3 EQU( AT91C_PIO_PB22 ); + -PWM Channel 3 + AT91C_PB22_PCK2 EQU( AT91C_PIO_PB22 ); + -PMC Programmable Clock Output 2 + AT91C_PIO_PB23 EQU( 1 << 23 ); + -Pin Controlled by PB23 + AT91C_PB23_TIOA0 EQU( AT91C_PIO_PB23 ); + -Timer Counter 0 Multipurpose Timer I / O Pin A + AT91C_PB23_DCD1 EQU( AT91C_PIO_PB23 ); + -USART 1 Data Carrier Detect + AT91C_PIO_PB24 EQU( 1 << 24 ); + -Pin Controlled by PB24 + AT91C_PB24_TIOB0 EQU( AT91C_PIO_PB24 ); + -Timer Counter 0 Multipurpose Timer I / O Pin B + AT91C_PB24_DSR1 EQU( AT91C_PIO_PB24 ); + -USART 1 Data Set ready + AT91C_PIO_PB25 EQU( 1 << 25 ); + -Pin Controlled by PB25 + AT91C_PB25_TIOA1 EQU( AT91C_PIO_PB25 ); + -Timer Counter 1 Multipurpose Timer I / O Pin A + AT91C_PB25_DTR1 EQU( AT91C_PIO_PB25 ); + -USART 1 Data Terminal ready + AT91C_PIO_PB26 EQU( 1 << 26 ); + -Pin Controlled by PB26 + AT91C_PB26_TIOB1 EQU( AT91C_PIO_PB26 ); + -Timer Counter 1 Multipurpose Timer I / O Pin B + AT91C_PB26_RI1 EQU( AT91C_PIO_PB26 ); + -USART 1 Ring Indicator + AT91C_PIO_PB27 EQU( 1 << 27 ); + -Pin Controlled by PB27 + AT91C_PB27_TIOA2 EQU( AT91C_PIO_PB27 ); + -Timer Counter 2 Multipurpose Timer I / O Pin A + AT91C_PB27_PWM0 EQU( AT91C_PIO_PB27 ); + -PWM Channel 0 + AT91C_PIO_PB28 EQU( 1 << 28 ); + -Pin Controlled by PB28 + AT91C_PB28_TIOB2 EQU( AT91C_PIO_PB28 ); + -Timer Counter 2 Multipurpose Timer I / O Pin B + AT91C_PB28_PWM1 EQU( AT91C_PIO_PB28 ); + -PWM Channel 1 + AT91C_PIO_PB29 EQU( 1 << 29 ); + -Pin Controlled by PB29 + AT91C_PB29_PCK1 EQU( AT91C_PIO_PB29 ); + -PMC Programmable Clock Output 1 + AT91C_PB29_PWM2 EQU( AT91C_PIO_PB29 ); + -PWM Channel 2 + AT91C_PIO_PB3 EQU( 1 << 3 ); + -Pin Controlled by PB3 + AT91C_PB3_ETX1 EQU( AT91C_PIO_PB3 ); + -Ethernet MAC Transmit Data 1 + AT91C_PIO_PB30 EQU( 1 << 30 ); + -Pin Controlled by PB30 + AT91C_PB30_PCK2 EQU( AT91C_PIO_PB30 ); + -PMC Programmable Clock Output 2 + AT91C_PB30_PWM3 EQU( AT91C_PIO_PB30 ); + -PWM Channel 3 + AT91C_PIO_PB4 EQU( 1 << 4 ); + -Pin Controlled by PB4 + AT91C_PB4_ECRS_ECRSDV EQU( AT91C_PIO_PB4 ); + -Ethernet MAC Carrier Sense / Carrier Sense and Data Valid + AT91C_PIO_PB5 EQU( 1 << 5 ); + -Pin Controlled by PB5 + AT91C_PB5_ERX0 EQU( AT91C_PIO_PB5 ); + -Ethernet MAC Receive Data 0 + AT91C_PIO_PB6 EQU( 1 << 6 ); + -Pin Controlled by PB6 + AT91C_PB6_ERX1 EQU( AT91C_PIO_PB6 ); + -Ethernet MAC Receive Data 1 + AT91C_PIO_PB7 EQU( 1 << 7 ); + -Pin Controlled by PB7 + AT91C_PB7_ERXER EQU( AT91C_PIO_PB7 ); + -Ethernet MAC Receive Error + AT91C_PIO_PB8 EQU( 1 << 8 ); + -Pin Controlled by PB8 + AT91C_PB8_EMDC EQU( AT91C_PIO_PB8 ); + -Ethernet MAC Management Data Clock + AT91C_PIO_PB9 EQU( 1 << 9 ); + -Pin Controlled by PB9 + AT91C_PB9_EMDIO EQU( AT91C_PIO_PB9 ); + -Ethernet MAC Management Data Input / Output + +/* - ***************************************************************************** */ +/* - PERIPHERAL ID DEFINITIONS FOR AT91SAM7X256 */ +/* - ***************************************************************************** */ + AT91C_ID_FIQ EQU( 0 ); + -Advanced Interrupt Controller( FIQ ) + AT91C_ID_SYS EQU( 1 ); + -System Peripheral + AT91C_ID_PIOA EQU( 2 ); + -Parallel IO Controller A + AT91C_ID_PIOB EQU( 3 ); + -Parallel IO Controller B + AT91C_ID_SPI0 EQU( 4 ); + -Serial Peripheral Interface 0 + AT91C_ID_SPI1 EQU( 5 ); + -Serial Peripheral Interface 1 + AT91C_ID_US0 EQU( 6 ); + -USART 0 + AT91C_ID_US1 EQU( 7 ); + -USART 1 + AT91C_ID_SSC EQU( 8 ); + -Serial Synchronous Controller + AT91C_ID_TWI EQU( 9 ); + -Two - Wire Interface + AT91C_ID_PWMC EQU( 10 ); + -PWM Controller + AT91C_ID_UDP EQU( 11 ); + -USB Device Port + AT91C_ID_TC0 EQU( 12 ); + -Timer Counter 0 + AT91C_ID_TC1 EQU( 13 ); + -Timer Counter 1 + AT91C_ID_TC2 EQU( 14 ); + -Timer Counter 2 + AT91C_ID_CAN EQU( 15 ); + -Control Area Network Controller + AT91C_ID_EMAC EQU( 16 ); + -Ethernet MAC + AT91C_ID_ADC EQU( 17 ); + -Analog - to - Digital Converter + AT91C_ID_AES EQU( 18 ); + -Advanced Encryption Standard 128 - bit + AT91C_ID_TDES EQU( 19 ); + -Triple Data Encryption Standard + AT91C_ID_20_Reserved EQU( 20 ); + -Reserved + AT91C_ID_21_Reserved EQU( 21 ); + -Reserved + AT91C_ID_22_Reserved EQU( 22 ); + -Reserved + AT91C_ID_23_Reserved EQU( 23 ); + -Reserved + AT91C_ID_24_Reserved EQU( 24 ); + -Reserved + AT91C_ID_25_Reserved EQU( 25 ); + -Reserved + AT91C_ID_26_Reserved EQU( 26 ); + -Reserved + AT91C_ID_27_Reserved EQU( 27 ); + -Reserved + AT91C_ID_28_Reserved EQU( 28 ); + -Reserved + AT91C_ID_29_Reserved EQU( 29 ); + -Reserved + AT91C_ID_IRQ0 EQU( 30 ); + -Advanced Interrupt Controller( IRQ0 ) + AT91C_ID_IRQ1 EQU( 31 ); + -Advanced Interrupt Controller( IRQ1 ) + +/* - ***************************************************************************** */ +/* - BASE ADDRESS DEFINITIONS FOR AT91SAM7X256 */ +/* - ***************************************************************************** */ + AT91C_BASE_SYS EQU( 0xFFFFF000 ); + -( SYS ) Base Address + AT91C_BASE_AIC EQU( 0xFFFFF000 ); + -( AIC ) Base Address + AT91C_BASE_PDC_DBGU EQU( 0xFFFFF300 ); + -( PDC_DBGU ) Base Address + AT91C_BASE_DBGU EQU( 0xFFFFF200 ); + -( DBGU ) Base Address + AT91C_BASE_PIOA EQU( 0xFFFFF400 ); + -( PIOA ) Base Address + AT91C_BASE_PIOB EQU( 0xFFFFF600 ); + -( PIOB ) Base Address + AT91C_BASE_CKGR EQU( 0xFFFFFC20 ); + -( CKGR ) Base Address + AT91C_BASE_PMC EQU( 0xFFFFFC00 ); + -( PMC ) Base Address + AT91C_BASE_RSTC EQU( 0xFFFFFD00 ); + -( RSTC ) Base Address + AT91C_BASE_RTTC EQU( 0xFFFFFD20 ); + -( RTTC ) Base Address + AT91C_BASE_PITC EQU( 0xFFFFFD30 ); + -( PITC ) Base Address + AT91C_BASE_WDTC EQU( 0xFFFFFD40 ); + -( WDTC ) Base Address + AT91C_BASE_VREG EQU( 0xFFFFFD60 ); + -( VREG ) Base Address + AT91C_BASE_MC EQU( 0xFFFFFF00 ); + -( MC ) Base Address + AT91C_BASE_PDC_SPI1 EQU( 0xFFFE4100 ); + -( PDC_SPI1 ) Base Address + AT91C_BASE_SPI1 EQU( 0xFFFE4000 ); + -( SPI1 ) Base Address + AT91C_BASE_PDC_SPI0 EQU( 0xFFFE0100 ); + -( PDC_SPI0 ) Base Address + AT91C_BASE_SPI0 EQU( 0xFFFE0000 ); + -( SPI0 ) Base Address + AT91C_BASE_PDC_US1 EQU( 0xFFFC4100 ); + -( PDC_US1 ) Base Address + AT91C_BASE_US1 EQU( 0xFFFC4000 ); + -( US1 ) Base Address + AT91C_BASE_PDC_US0 EQU( 0xFFFC0100 ); + -( PDC_US0 ) Base Address + AT91C_BASE_US0 EQU( 0xFFFC0000 ); + -( US0 ) Base Address + AT91C_BASE_PDC_SSC EQU( 0xFFFD4100 ); + -( PDC_SSC ) Base Address + AT91C_BASE_SSC EQU( 0xFFFD4000 ); + -( SSC ) Base Address + AT91C_BASE_TWI EQU( 0xFFFB8000 ); + -( TWI ) Base Address + AT91C_BASE_PWMC_CH3 EQU( 0xFFFCC260 ); + -( PWMC_CH3 ) Base Address + AT91C_BASE_PWMC_CH2 EQU( 0xFFFCC240 ); + -( PWMC_CH2 ) Base Address + AT91C_BASE_PWMC_CH1 EQU( 0xFFFCC220 ); + -( PWMC_CH1 ) Base Address + AT91C_BASE_PWMC_CH0 EQU( 0xFFFCC200 ); + -( PWMC_CH0 ) Base Address + AT91C_BASE_PWMC EQU( 0xFFFCC000 ); + -( PWMC ) Base Address + AT91C_BASE_UDP EQU( 0xFFFB0000 ); + -( UDP ) Base Address + AT91C_BASE_TC0 EQU( 0xFFFA0000 ); + -( TC0 ) Base Address + AT91C_BASE_TC1 EQU( 0xFFFA0040 ); + -( TC1 ) Base Address + AT91C_BASE_TC2 EQU( 0xFFFA0080 ); + -( TC2 ) Base Address + AT91C_BASE_TCB EQU( 0xFFFA0000 ); + -( TCB ) Base Address + AT91C_BASE_CAN_MB0 EQU( 0xFFFD0200 ); + -( CAN_MB0 ) Base Address + AT91C_BASE_CAN_MB1 EQU( 0xFFFD0220 ); + -( CAN_MB1 ) Base Address + AT91C_BASE_CAN_MB2 EQU( 0xFFFD0240 ); + -( CAN_MB2 ) Base Address + AT91C_BASE_CAN_MB3 EQU( 0xFFFD0260 ); + -( CAN_MB3 ) Base Address + AT91C_BASE_CAN_MB4 EQU( 0xFFFD0280 ); + -( CAN_MB4 ) Base Address + AT91C_BASE_CAN_MB5 EQU( 0xFFFD02A0 ); + -( CAN_MB5 ) Base Address + AT91C_BASE_CAN_MB6 EQU( 0xFFFD02C0 ); + -( CAN_MB6 ) Base Address + AT91C_BASE_CAN_MB7 EQU( 0xFFFD02E0 ); + -( CAN_MB7 ) Base Address + AT91C_BASE_CAN EQU( 0xFFFD0000 ); + -( CAN ) Base Address + AT91C_BASE_EMAC EQU( 0xFFFDC000 ); + -( EMAC ) Base Address + AT91C_BASE_PDC_ADC EQU( 0xFFFD8100 ); + -( PDC_ADC ) Base Address + AT91C_BASE_ADC EQU( 0xFFFD8000 ); + -( ADC ) Base Address + AT91C_BASE_PDC_AES EQU( 0xFFFA4100 ); + -( PDC_AES ) Base Address + AT91C_BASE_AES EQU( 0xFFFA4000 ); + -( AES ) Base Address + AT91C_BASE_PDC_TDES EQU( 0xFFFA8100 ); + -( PDC_TDES ) Base Address + AT91C_BASE_TDES EQU( 0xFFFA8000 ); + -( TDES ) Base Address + +/* - ***************************************************************************** */ +/* - MEMORY MAPPING DEFINITIONS FOR AT91SAM7X256 */ +/* - ***************************************************************************** */ + AT91C_ISRAM EQU( 0x00200000 ); + -Internal SRAM base address + AT91C_ISRAM_SIZE EQU( 0x00010000 ); + -Internal SRAM size in byte( 64 Kbyte ) + AT91C_IFLASH EQU( 0x00100000 ); + -Internal ROM base address + AT91C_IFLASH_SIZE EQU( 0x00040000 ); + -Internal ROM size in byte( 256 Kbyte ) diff --git a/Source/portable/GCC/ARM7_AT91SAM7S/lib_AT91SAM7X256.c b/Source/portable/GCC/ARM7_AT91SAM7S/lib_AT91SAM7X256.c index 240c7334b..269d390cc 100644 --- a/Source/portable/GCC/ARM7_AT91SAM7S/lib_AT91SAM7X256.c +++ b/Source/portable/GCC/ARM7_AT91SAM7S/lib_AT91SAM7X256.c @@ -1,50 +1,50 @@ -//* ---------------------------------------------------------------------------- -//* ATMEL Microcontroller Software Support - ROUSSET - -//* ---------------------------------------------------------------------------- -//* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR -//* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF -//* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE -//* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, -//* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -//* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, -//* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF -//* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING -//* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, -//* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -//* ---------------------------------------------------------------------------- -//* File Name : lib_AT91SAM7X256.h -//* Object : AT91SAM7X256 inlined functions -//* Generated : AT91 SW Application Group 05/20/2005 (16:22:29) -//* -//* CVS Reference : /lib_dbgu.h/1.1/Fri Jan 31 12:18:40 2003// -//* CVS Reference : /lib_pmc_SAM7X.h/1.1/Tue Feb 1 08:32:10 2005// -//* CVS Reference : /lib_VREG_6085B.h/1.1/Tue Feb 1 16:20:47 2005// -//* CVS Reference : /lib_rstc_6098A.h/1.1/Wed Oct 6 10:39:20 2004// -//* CVS Reference : /lib_ssc.h/1.4/Fri Jan 31 12:19:20 2003// -//* CVS Reference : /lib_wdtc_6080A.h/1.1/Wed Oct 6 10:38:30 2004// -//* CVS Reference : /lib_usart.h/1.5/Thu Nov 21 16:01:54 2002// -//* CVS Reference : /lib_spi2.h/1.1/Mon Aug 25 14:23:52 2003// -//* CVS Reference : /lib_pitc_6079A.h/1.2/Tue Nov 9 14:43:56 2004// -//* CVS Reference : /lib_aic_6075b.h/1.1/Fri May 20 14:01:19 2005// -//* CVS Reference : /lib_aes_6149a.h/1.1/Mon Jan 17 07:43:09 2005// -//* CVS Reference : /lib_twi.h/1.3/Mon Jul 19 14:27:58 2004// -//* CVS Reference : /lib_adc.h/1.6/Fri Oct 17 09:12:38 2003// -//* CVS Reference : /lib_rttc_6081A.h/1.1/Wed Oct 6 10:39:38 2004// -//* CVS Reference : /lib_udp.h/1.4/Wed Feb 16 08:39:34 2005// -//* CVS Reference : /lib_des3_6150a.h/1.1/Mon Jan 17 09:19:19 2005// -//* CVS Reference : /lib_tc_1753b.h/1.1/Fri Jan 31 12:20:02 2003// -//* CVS Reference : /lib_MC_SAM7X.h/1.1/Thu Mar 25 15:19:14 2004// -//* CVS Reference : /lib_pio.h/1.3/Fri Jan 31 12:18:56 2003// -//* CVS Reference : /lib_can_AT91.h/1.4/Fri Oct 17 09:12:50 2003// -//* CVS Reference : /lib_PWM_SAM.h/1.3/Thu Jan 22 10:10:50 2004// -//* CVS Reference : /lib_pdc.h/1.2/Tue Jul 2 13:29:40 2002// -//* ---------------------------------------------------------------------------- +/** ---------------------------------------------------------------------------- */ +/** ATMEL Microcontroller Software Support - ROUSSET - */ +/** ---------------------------------------------------------------------------- */ +/** DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/** IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/** MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/** DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/** INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/** LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/** OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/** LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/** NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/** EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/** ---------------------------------------------------------------------------- */ +/** File Name : lib_AT91SAM7X256.h */ +/** Object : AT91SAM7X256 inlined functions */ +/** Generated : AT91 SW Application Group 05/20/2005 (16:22:29) */ +/** */ +/** CVS Reference : /lib_dbgu.h/1.1/Fri Jan 31 12:18:40 2003// */ +/** CVS Reference : /lib_pmc_SAM7X.h/1.1/Tue Feb 1 08:32:10 2005// */ +/** CVS Reference : /lib_VREG_6085B.h/1.1/Tue Feb 1 16:20:47 2005// */ +/** CVS Reference : /lib_rstc_6098A.h/1.1/Wed Oct 6 10:39:20 2004// */ +/** CVS Reference : /lib_ssc.h/1.4/Fri Jan 31 12:19:20 2003// */ +/** CVS Reference : /lib_wdtc_6080A.h/1.1/Wed Oct 6 10:38:30 2004// */ +/** CVS Reference : /lib_usart.h/1.5/Thu Nov 21 16:01:54 2002// */ +/** CVS Reference : /lib_spi2.h/1.1/Mon Aug 25 14:23:52 2003// */ +/** CVS Reference : /lib_pitc_6079A.h/1.2/Tue Nov 9 14:43:56 2004// */ +/** CVS Reference : /lib_aic_6075b.h/1.1/Fri May 20 14:01:19 2005// */ +/** CVS Reference : /lib_aes_6149a.h/1.1/Mon Jan 17 07:43:09 2005// */ +/** CVS Reference : /lib_twi.h/1.3/Mon Jul 19 14:27:58 2004// */ +/** CVS Reference : /lib_adc.h/1.6/Fri Oct 17 09:12:38 2003// */ +/** CVS Reference : /lib_rttc_6081A.h/1.1/Wed Oct 6 10:39:38 2004// */ +/** CVS Reference : /lib_udp.h/1.4/Wed Feb 16 08:39:34 2005// */ +/** CVS Reference : /lib_des3_6150a.h/1.1/Mon Jan 17 09:19:19 2005// */ +/** CVS Reference : /lib_tc_1753b.h/1.1/Fri Jan 31 12:20:02 2003// */ +/** CVS Reference : /lib_MC_SAM7X.h/1.1/Thu Mar 25 15:19:14 2004// */ +/** CVS Reference : /lib_pio.h/1.3/Fri Jan 31 12:18:56 2003// */ +/** CVS Reference : /lib_can_AT91.h/1.4/Fri Oct 17 09:12:50 2003// */ +/** CVS Reference : /lib_PWM_SAM.h/1.3/Thu Jan 22 10:10:50 2004// */ +/** CVS Reference : /lib_pdc.h/1.2/Tue Jul 2 13:29:40 2002// */ +/** ---------------------------------------------------------------------------- */ #include "AT91SAM7X256.h" -//*---------------------------------------------------------------------------- -//* \fn AT91F_AIC_ConfigureIt -//* \brief Interrupt Handler Initialization -//*---------------------------------------------------------------------------- +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_AIC_ConfigureIt */ +/** \brief Interrupt Handler Initialization */ +/**---------------------------------------------------------------------------- */ diff --git a/Source/portable/GCC/ARM7_AT91SAM7S/lib_AT91SAM7X256.h b/Source/portable/GCC/ARM7_AT91SAM7S/lib_AT91SAM7X256.h index 556e0ca16..0d9a70884 100644 --- a/Source/portable/GCC/ARM7_AT91SAM7S/lib_AT91SAM7X256.h +++ b/Source/portable/GCC/ARM7_AT91SAM7S/lib_AT91SAM7X256.h @@ -1,1469 +1,1396 @@ -//* ---------------------------------------------------------------------------- -//* ATMEL Microcontroller Software Support - ROUSSET - -//* ---------------------------------------------------------------------------- -//* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR -//* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF -//* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE -//* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, -//* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -//* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, -//* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF -//* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING -//* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, -//* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -//* ---------------------------------------------------------------------------- -//* File Name : lib_AT91SAM7X256.h -//* Object : AT91SAM7X256 inlined functions -//* Generated : AT91 SW Application Group 05/20/2005 (16:22:29) -//* -//* CVS Reference : /lib_dbgu.h/1.1/Fri Jan 31 12:18:40 2003// -//* CVS Reference : /lib_pmc_SAM7X.h/1.1/Tue Feb 1 08:32:10 2005// -//* CVS Reference : /lib_VREG_6085B.h/1.1/Tue Feb 1 16:20:47 2005// -//* CVS Reference : /lib_rstc_6098A.h/1.1/Wed Oct 6 10:39:20 2004// -//* CVS Reference : /lib_ssc.h/1.4/Fri Jan 31 12:19:20 2003// -//* CVS Reference : /lib_wdtc_6080A.h/1.1/Wed Oct 6 10:38:30 2004// -//* CVS Reference : /lib_usart.h/1.5/Thu Nov 21 16:01:54 2002// -//* CVS Reference : /lib_spi2.h/1.1/Mon Aug 25 14:23:52 2003// -//* CVS Reference : /lib_pitc_6079A.h/1.2/Tue Nov 9 14:43:56 2004// -//* CVS Reference : /lib_aic_6075b.h/1.1/Fri May 20 14:01:19 2005// -//* CVS Reference : /lib_aes_6149a.h/1.1/Mon Jan 17 07:43:09 2005// -//* CVS Reference : /lib_twi.h/1.3/Mon Jul 19 14:27:58 2004// -//* CVS Reference : /lib_adc.h/1.6/Fri Oct 17 09:12:38 2003// -//* CVS Reference : /lib_rttc_6081A.h/1.1/Wed Oct 6 10:39:38 2004// -//* CVS Reference : /lib_udp.h/1.4/Wed Feb 16 08:39:34 2005// -//* CVS Reference : /lib_des3_6150a.h/1.1/Mon Jan 17 09:19:19 2005// -//* CVS Reference : /lib_tc_1753b.h/1.1/Fri Jan 31 12:20:02 2003// -//* CVS Reference : /lib_MC_SAM7X.h/1.1/Thu Mar 25 15:19:14 2004// -//* CVS Reference : /lib_pio.h/1.3/Fri Jan 31 12:18:56 2003// -//* CVS Reference : /lib_can_AT91.h/1.4/Fri Oct 17 09:12:50 2003// -//* CVS Reference : /lib_PWM_SAM.h/1.3/Thu Jan 22 10:10:50 2004// -//* CVS Reference : /lib_pdc.h/1.2/Tue Jul 2 13:29:40 2002// -//* ---------------------------------------------------------------------------- +/** ---------------------------------------------------------------------------- */ +/** ATMEL Microcontroller Software Support - ROUSSET - */ +/** ---------------------------------------------------------------------------- */ +/** DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/** IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/** MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/** DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/** INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/** LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/** OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/** LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/** NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/** EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/** ---------------------------------------------------------------------------- */ +/** File Name : lib_AT91SAM7X256.h */ +/** Object : AT91SAM7X256 inlined functions */ +/** Generated : AT91 SW Application Group 05/20/2005 (16:22:29) */ +/** */ +/** CVS Reference : /lib_dbgu.h/1.1/Fri Jan 31 12:18:40 2003// */ +/** CVS Reference : /lib_pmc_SAM7X.h/1.1/Tue Feb 1 08:32:10 2005// */ +/** CVS Reference : /lib_VREG_6085B.h/1.1/Tue Feb 1 16:20:47 2005// */ +/** CVS Reference : /lib_rstc_6098A.h/1.1/Wed Oct 6 10:39:20 2004// */ +/** CVS Reference : /lib_ssc.h/1.4/Fri Jan 31 12:19:20 2003// */ +/** CVS Reference : /lib_wdtc_6080A.h/1.1/Wed Oct 6 10:38:30 2004// */ +/** CVS Reference : /lib_usart.h/1.5/Thu Nov 21 16:01:54 2002// */ +/** CVS Reference : /lib_spi2.h/1.1/Mon Aug 25 14:23:52 2003// */ +/** CVS Reference : /lib_pitc_6079A.h/1.2/Tue Nov 9 14:43:56 2004// */ +/** CVS Reference : /lib_aic_6075b.h/1.1/Fri May 20 14:01:19 2005// */ +/** CVS Reference : /lib_aes_6149a.h/1.1/Mon Jan 17 07:43:09 2005// */ +/** CVS Reference : /lib_twi.h/1.3/Mon Jul 19 14:27:58 2004// */ +/** CVS Reference : /lib_adc.h/1.6/Fri Oct 17 09:12:38 2003// */ +/** CVS Reference : /lib_rttc_6081A.h/1.1/Wed Oct 6 10:39:38 2004// */ +/** CVS Reference : /lib_udp.h/1.4/Wed Feb 16 08:39:34 2005// */ +/** CVS Reference : /lib_des3_6150a.h/1.1/Mon Jan 17 09:19:19 2005// */ +/** CVS Reference : /lib_tc_1753b.h/1.1/Fri Jan 31 12:20:02 2003// */ +/** CVS Reference : /lib_MC_SAM7X.h/1.1/Thu Mar 25 15:19:14 2004// */ +/** CVS Reference : /lib_pio.h/1.3/Fri Jan 31 12:18:56 2003// */ +/** CVS Reference : /lib_can_AT91.h/1.4/Fri Oct 17 09:12:50 2003// */ +/** CVS Reference : /lib_PWM_SAM.h/1.3/Thu Jan 22 10:10:50 2004// */ +/** CVS Reference : /lib_pdc.h/1.2/Tue Jul 2 13:29:40 2002// */ +/** ---------------------------------------------------------------------------- */ #ifndef lib_AT91SAM7X256_H -#define lib_AT91SAM7X256_H + #define lib_AT91SAM7X256_H /* ***************************************************************************** - SOFTWARE API FOR AIC - ***************************************************************************** */ -#define AT91C_AIC_BRANCH_OPCODE ((void (*) ()) 0xE51FFF20) // ldr, pc, [pc, #-&F20] - -//*---------------------------------------------------------------------------- -//* \fn AT91F_AIC_ConfigureIt -//* \brief Interrupt Handler Initialization -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_AIC_ConfigureIt ( - AT91PS_AIC pAic, // \arg pointer to the AIC registers - unsigned int irq_id, // \arg interrupt number to initialize - unsigned int priority, // \arg priority to give to the interrupt - unsigned int src_type, // \arg activation and sense of activation - void (*newHandler) (void) ) // \arg address of the interrupt handler -{ - unsigned int oldHandler; - unsigned int mask ; - - oldHandler = pAic->AIC_SVR[irq_id]; - - mask = 0x1 << irq_id ; - //* Disable the interrupt on the interrupt controller - pAic->AIC_IDCR = mask ; - //* Save the interrupt handler routine pointer and the interrupt priority - pAic->AIC_SVR[irq_id] = (unsigned int) newHandler ; - //* Store the Source Mode Register - pAic->AIC_SMR[irq_id] = src_type | priority ; - //* Clear the interrupt on the interrupt controller - pAic->AIC_ICCR = mask ; - - return oldHandler; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_AIC_EnableIt -//* \brief Enable corresponding IT number -//*---------------------------------------------------------------------------- -__inline void AT91F_AIC_EnableIt ( - AT91PS_AIC pAic, // \arg pointer to the AIC registers - unsigned int irq_id ) // \arg interrupt number to initialize -{ - //* Enable the interrupt on the interrupt controller - pAic->AIC_IECR = 0x1 << irq_id ; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_AIC_DisableIt -//* \brief Disable corresponding IT number -//*---------------------------------------------------------------------------- -__inline void AT91F_AIC_DisableIt ( - AT91PS_AIC pAic, // \arg pointer to the AIC registers - unsigned int irq_id ) // \arg interrupt number to initialize -{ - unsigned int mask = 0x1 << irq_id; - //* Disable the interrupt on the interrupt controller - pAic->AIC_IDCR = mask ; - //* Clear the interrupt on the Interrupt Controller ( if one is pending ) - pAic->AIC_ICCR = mask ; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_AIC_ClearIt -//* \brief Clear corresponding IT number -//*---------------------------------------------------------------------------- -__inline void AT91F_AIC_ClearIt ( - AT91PS_AIC pAic, // \arg pointer to the AIC registers - unsigned int irq_id) // \arg interrupt number to initialize -{ - //* Clear the interrupt on the Interrupt Controller ( if one is pending ) - pAic->AIC_ICCR = (0x1 << irq_id); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_AIC_AcknowledgeIt -//* \brief Acknowledge corresponding IT number -//*---------------------------------------------------------------------------- -__inline void AT91F_AIC_AcknowledgeIt ( - AT91PS_AIC pAic) // \arg pointer to the AIC registers -{ - pAic->AIC_EOICR = pAic->AIC_EOICR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_AIC_SetExceptionVector -//* \brief Configure vector handler -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_AIC_SetExceptionVector ( - unsigned int *pVector, // \arg pointer to the AIC registers - void (*Handler) () ) // \arg Interrupt Handler -{ - unsigned int oldVector = *pVector; - - if ((unsigned int) Handler == (unsigned int) AT91C_AIC_BRANCH_OPCODE) - *pVector = (unsigned int) AT91C_AIC_BRANCH_OPCODE; - else - *pVector = (((((unsigned int) Handler) - ((unsigned int) pVector) - 0x8) >> 2) & 0x00FFFFFF) | 0xEA000000; - - return oldVector; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_AIC_Trig -//* \brief Trig an IT -//*---------------------------------------------------------------------------- -__inline void AT91F_AIC_Trig ( - AT91PS_AIC pAic, // \arg pointer to the AIC registers - unsigned int irq_id) // \arg interrupt number -{ - pAic->AIC_ISCR = (0x1 << irq_id) ; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_AIC_IsActive -//* \brief Test if an IT is active -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_AIC_IsActive ( - AT91PS_AIC pAic, // \arg pointer to the AIC registers - unsigned int irq_id) // \arg Interrupt Number -{ - return (pAic->AIC_ISR & (0x1 << irq_id)); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_AIC_IsPending -//* \brief Test if an IT is pending -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_AIC_IsPending ( - AT91PS_AIC pAic, // \arg pointer to the AIC registers - unsigned int irq_id) // \arg Interrupt Number -{ - return (pAic->AIC_IPR & (0x1 << irq_id)); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_AIC_Open -//* \brief Set exception vectors and AIC registers to default values -//*---------------------------------------------------------------------------- -__inline void AT91F_AIC_Open( - AT91PS_AIC pAic, // \arg pointer to the AIC registers - void (*IrqHandler) (), // \arg Default IRQ vector exception - void (*FiqHandler) (), // \arg Default FIQ vector exception - void (*DefaultHandler) (), // \arg Default Handler set in ISR - void (*SpuriousHandler) (), // \arg Default Spurious Handler - unsigned int protectMode) // \arg Debug Control Register -{ - int i; - - // Disable all interrupts and set IVR to the default handler - for (i = 0; i < 32; ++i) { - AT91F_AIC_DisableIt(pAic, i); - AT91F_AIC_ConfigureIt(pAic, i, AT91C_AIC_PRIOR_LOWEST, AT91C_AIC_SRCTYPE_HIGH_LEVEL, DefaultHandler); - } - - // Set the IRQ exception vector - AT91F_AIC_SetExceptionVector((unsigned int *) 0x18, IrqHandler); - // Set the Fast Interrupt exception vector - AT91F_AIC_SetExceptionVector((unsigned int *) 0x1C, FiqHandler); - - pAic->AIC_SPU = (unsigned int) SpuriousHandler; - pAic->AIC_DCR = protectMode; -} +* SOFTWARE API FOR AIC +***************************************************************************** */ + #define AT91C_AIC_BRANCH_OPCODE ( ( void ( * )() ) 0xE51FFF20 ) /* ldr, pc, [pc, #-&F20] */ + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_AIC_ConfigureIt */ +/** \brief Interrupt Handler Initialization */ +/**---------------------------------------------------------------------------- */ + __inline unsigned int AT91F_AIC_ConfigureIt( AT91PS_AIC pAic, /* \arg pointer to the AIC registers */ + unsigned int irq_id, /* \arg interrupt number to initialize */ + unsigned int priority, /* \arg priority to give to the interrupt */ + unsigned int src_type, /* \arg activation and sense of activation */ + void ( * newHandler )( void ) ) /* \arg address of the interrupt handler */ + { + unsigned int oldHandler; + unsigned int mask; + + oldHandler = pAic->AIC_SVR[ irq_id ]; + + mask = 0x1 << irq_id; + /** Disable the interrupt on the interrupt controller */ + pAic->AIC_IDCR = mask; + /** Save the interrupt handler routine pointer and the interrupt priority */ + pAic->AIC_SVR[ irq_id ] = ( unsigned int ) newHandler; + /** Store the Source Mode Register */ + pAic->AIC_SMR[ irq_id ] = src_type | priority; + /** Clear the interrupt on the interrupt controller */ + pAic->AIC_ICCR = mask; + + return oldHandler; + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_AIC_EnableIt */ +/** \brief Enable corresponding IT number */ +/**---------------------------------------------------------------------------- */ + __inline void AT91F_AIC_EnableIt( AT91PS_AIC pAic, /* \arg pointer to the AIC registers */ + unsigned int irq_id ) /* \arg interrupt number to initialize */ + { + /** Enable the interrupt on the interrupt controller */ + pAic->AIC_IECR = 0x1 << irq_id; + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_AIC_DisableIt */ +/** \brief Disable corresponding IT number */ +/**---------------------------------------------------------------------------- */ + __inline void AT91F_AIC_DisableIt( AT91PS_AIC pAic, /* \arg pointer to the AIC registers */ + unsigned int irq_id ) /* \arg interrupt number to initialize */ + { + unsigned int mask = 0x1 << irq_id; + + /** Disable the interrupt on the interrupt controller */ + pAic->AIC_IDCR = mask; + /** Clear the interrupt on the Interrupt Controller ( if one is pending ) */ + pAic->AIC_ICCR = mask; + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_AIC_ClearIt */ +/** \brief Clear corresponding IT number */ +/**---------------------------------------------------------------------------- */ + __inline void AT91F_AIC_ClearIt( AT91PS_AIC pAic, /* \arg pointer to the AIC registers */ + unsigned int irq_id ) /* \arg interrupt number to initialize */ + { + /** Clear the interrupt on the Interrupt Controller ( if one is pending ) */ + pAic->AIC_ICCR = ( 0x1 << irq_id ); + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_AIC_AcknowledgeIt */ +/** \brief Acknowledge corresponding IT number */ +/**---------------------------------------------------------------------------- */ + __inline void AT91F_AIC_AcknowledgeIt( AT91PS_AIC pAic ) /* \arg pointer to the AIC registers */ + { + pAic->AIC_EOICR = pAic->AIC_EOICR; + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_AIC_SetExceptionVector */ +/** \brief Configure vector handler */ +/**---------------------------------------------------------------------------- */ + __inline unsigned int AT91F_AIC_SetExceptionVector( unsigned int * pVector, /* \arg pointer to the AIC registers */ + void ( * Handler )() ) /* \arg Interrupt Handler */ + { + unsigned int oldVector = *pVector; + + if( ( unsigned int ) Handler == ( unsigned int ) AT91C_AIC_BRANCH_OPCODE ) + { + *pVector = ( unsigned int ) AT91C_AIC_BRANCH_OPCODE; + } + else + { + *pVector = ( ( ( ( ( unsigned int ) Handler ) - ( ( unsigned int ) pVector ) - 0x8 ) >> 2 ) & 0x00FFFFFF ) | 0xEA000000; + } + + return oldVector; + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_AIC_Trig */ +/** \brief Trig an IT */ +/**---------------------------------------------------------------------------- */ + __inline void AT91F_AIC_Trig( AT91PS_AIC pAic, /* \arg pointer to the AIC registers */ + unsigned int irq_id ) /* \arg interrupt number */ + { + pAic->AIC_ISCR = ( 0x1 << irq_id ); + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_AIC_IsActive */ +/** \brief Test if an IT is active */ +/**---------------------------------------------------------------------------- */ + __inline unsigned int AT91F_AIC_IsActive( AT91PS_AIC pAic, /* \arg pointer to the AIC registers */ + unsigned int irq_id ) /* \arg Interrupt Number */ + { + return( pAic->AIC_ISR & ( 0x1 << irq_id ) ); + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_AIC_IsPending */ +/** \brief Test if an IT is pending */ +/**---------------------------------------------------------------------------- */ + __inline unsigned int AT91F_AIC_IsPending( AT91PS_AIC pAic, /* \arg pointer to the AIC registers */ + unsigned int irq_id ) /* \arg Interrupt Number */ + { + return( pAic->AIC_IPR & ( 0x1 << irq_id ) ); + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_AIC_Open */ +/** \brief Set exception vectors and AIC registers to default values */ +/**---------------------------------------------------------------------------- */ + __inline void AT91F_AIC_Open( AT91PS_AIC pAic, /* \arg pointer to the AIC registers */ + void ( * IrqHandler )(), /* \arg Default IRQ vector exception */ + void ( * FiqHandler )(), /* \arg Default FIQ vector exception */ + void ( * DefaultHandler )(), /* \arg Default Handler set in ISR */ + void ( * SpuriousHandler )(), /* \arg Default Spurious Handler */ + unsigned int protectMode ) /* \arg Debug Control Register */ + { + int i; + + /* Disable all interrupts and set IVR to the default handler */ + for( i = 0; i < 32; ++i ) + { + AT91F_AIC_DisableIt( pAic, i ); + AT91F_AIC_ConfigureIt( pAic, i, AT91C_AIC_PRIOR_LOWEST, AT91C_AIC_SRCTYPE_HIGH_LEVEL, DefaultHandler ); + } + + /* Set the IRQ exception vector */ + AT91F_AIC_SetExceptionVector( ( unsigned int * ) 0x18, IrqHandler ); + /* Set the Fast Interrupt exception vector */ + AT91F_AIC_SetExceptionVector( ( unsigned int * ) 0x1C, FiqHandler ); + + pAic->AIC_SPU = ( unsigned int ) SpuriousHandler; + pAic->AIC_DCR = protectMode; + } + /* ***************************************************************************** - SOFTWARE API FOR PDC - ***************************************************************************** */ -//*---------------------------------------------------------------------------- -//* \fn AT91F_PDC_SetNextRx -//* \brief Set the next receive transfer descriptor -//*---------------------------------------------------------------------------- -__inline void AT91F_PDC_SetNextRx ( - AT91PS_PDC pPDC, // \arg pointer to a PDC controller - char *address, // \arg address to the next bloc to be received - unsigned int bytes) // \arg number of bytes to be received -{ - pPDC->PDC_RNPR = (unsigned int) address; - pPDC->PDC_RNCR = bytes; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PDC_SetNextTx -//* \brief Set the next transmit transfer descriptor -//*---------------------------------------------------------------------------- -__inline void AT91F_PDC_SetNextTx ( - AT91PS_PDC pPDC, // \arg pointer to a PDC controller - char *address, // \arg address to the next bloc to be transmitted - unsigned int bytes) // \arg number of bytes to be transmitted -{ - pPDC->PDC_TNPR = (unsigned int) address; - pPDC->PDC_TNCR = bytes; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PDC_SetRx -//* \brief Set the receive transfer descriptor -//*---------------------------------------------------------------------------- -__inline void AT91F_PDC_SetRx ( - AT91PS_PDC pPDC, // \arg pointer to a PDC controller - char *address, // \arg address to the next bloc to be received - unsigned int bytes) // \arg number of bytes to be received -{ - pPDC->PDC_RPR = (unsigned int) address; - pPDC->PDC_RCR = bytes; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PDC_SetTx -//* \brief Set the transmit transfer descriptor -//*---------------------------------------------------------------------------- -__inline void AT91F_PDC_SetTx ( - AT91PS_PDC pPDC, // \arg pointer to a PDC controller - char *address, // \arg address to the next bloc to be transmitted - unsigned int bytes) // \arg number of bytes to be transmitted -{ - pPDC->PDC_TPR = (unsigned int) address; - pPDC->PDC_TCR = bytes; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PDC_EnableTx -//* \brief Enable transmit -//*---------------------------------------------------------------------------- -__inline void AT91F_PDC_EnableTx ( - AT91PS_PDC pPDC ) // \arg pointer to a PDC controller -{ - pPDC->PDC_PTCR = AT91C_PDC_TXTEN; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PDC_EnableRx -//* \brief Enable receive -//*---------------------------------------------------------------------------- -__inline void AT91F_PDC_EnableRx ( - AT91PS_PDC pPDC ) // \arg pointer to a PDC controller -{ - pPDC->PDC_PTCR = AT91C_PDC_RXTEN; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PDC_DisableTx -//* \brief Disable transmit -//*---------------------------------------------------------------------------- -__inline void AT91F_PDC_DisableTx ( - AT91PS_PDC pPDC ) // \arg pointer to a PDC controller -{ - pPDC->PDC_PTCR = AT91C_PDC_TXTDIS; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PDC_DisableRx -//* \brief Disable receive -//*---------------------------------------------------------------------------- -__inline void AT91F_PDC_DisableRx ( - AT91PS_PDC pPDC ) // \arg pointer to a PDC controller -{ - pPDC->PDC_PTCR = AT91C_PDC_RXTDIS; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PDC_IsTxEmpty -//* \brief Test if the current transfer descriptor has been sent -//*---------------------------------------------------------------------------- -__inline int AT91F_PDC_IsTxEmpty ( // \return return 1 if transfer is complete - AT91PS_PDC pPDC ) // \arg pointer to a PDC controller -{ - return !(pPDC->PDC_TCR); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PDC_IsNextTxEmpty -//* \brief Test if the next transfer descriptor has been moved to the current td -//*---------------------------------------------------------------------------- -__inline int AT91F_PDC_IsNextTxEmpty ( // \return return 1 if transfer is complete - AT91PS_PDC pPDC ) // \arg pointer to a PDC controller -{ - return !(pPDC->PDC_TNCR); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PDC_IsRxEmpty -//* \brief Test if the current transfer descriptor has been filled -//*---------------------------------------------------------------------------- -__inline int AT91F_PDC_IsRxEmpty ( // \return return 1 if transfer is complete - AT91PS_PDC pPDC ) // \arg pointer to a PDC controller -{ - return !(pPDC->PDC_RCR); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PDC_IsNextRxEmpty -//* \brief Test if the next transfer descriptor has been moved to the current td -//*---------------------------------------------------------------------------- -__inline int AT91F_PDC_IsNextRxEmpty ( // \return return 1 if transfer is complete - AT91PS_PDC pPDC ) // \arg pointer to a PDC controller -{ - return !(pPDC->PDC_RNCR); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PDC_Open -//* \brief Open PDC: disable TX and RX reset transfer descriptors, re-enable RX and TX -//*---------------------------------------------------------------------------- -__inline void AT91F_PDC_Open ( - AT91PS_PDC pPDC) // \arg pointer to a PDC controller -{ - //* Disable the RX and TX PDC transfer requests - AT91F_PDC_DisableRx(pPDC); - AT91F_PDC_DisableTx(pPDC); - - //* Reset all Counter register Next buffer first - AT91F_PDC_SetNextTx(pPDC, (char *) 0, 0); - AT91F_PDC_SetNextRx(pPDC, (char *) 0, 0); - AT91F_PDC_SetTx(pPDC, (char *) 0, 0); - AT91F_PDC_SetRx(pPDC, (char *) 0, 0); - - //* Enable the RX and TX PDC transfer requests - AT91F_PDC_EnableRx(pPDC); - AT91F_PDC_EnableTx(pPDC); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PDC_Close -//* \brief Close PDC: disable TX and RX reset transfer descriptors -//*---------------------------------------------------------------------------- -__inline void AT91F_PDC_Close ( - AT91PS_PDC pPDC) // \arg pointer to a PDC controller -{ - //* Disable the RX and TX PDC transfer requests - AT91F_PDC_DisableRx(pPDC); - AT91F_PDC_DisableTx(pPDC); - - //* Reset all Counter register Next buffer first - AT91F_PDC_SetNextTx(pPDC, (char *) 0, 0); - AT91F_PDC_SetNextRx(pPDC, (char *) 0, 0); - AT91F_PDC_SetTx(pPDC, (char *) 0, 0); - AT91F_PDC_SetRx(pPDC, (char *) 0, 0); - -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PDC_SendFrame -//* \brief Close PDC: disable TX and RX reset transfer descriptors -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_PDC_SendFrame( - AT91PS_PDC pPDC, - char *pBuffer, - unsigned int szBuffer, - char *pNextBuffer, - unsigned int szNextBuffer ) -{ - if (AT91F_PDC_IsTxEmpty(pPDC)) { - //* Buffer and next buffer can be initialized - AT91F_PDC_SetTx(pPDC, pBuffer, szBuffer); - AT91F_PDC_SetNextTx(pPDC, pNextBuffer, szNextBuffer); - return 2; - } - else if (AT91F_PDC_IsNextTxEmpty(pPDC)) { - //* Only one buffer can be initialized - AT91F_PDC_SetNextTx(pPDC, pBuffer, szBuffer); - return 1; - } - else { - //* All buffer are in use... - return 0; +* SOFTWARE API FOR PDC +***************************************************************************** */ +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PDC_SetNextRx */ +/** \brief Set the next receive transfer descriptor */ +/**---------------------------------------------------------------------------- */ + __inline void AT91F_PDC_SetNextRx( AT91PS_PDC pPDC, /* \arg pointer to a PDC controller */ + char * address, /* \arg address to the next bloc to be received */ + unsigned int bytes ) /* \arg number of bytes to be received */ + { + pPDC->PDC_RNPR = ( unsigned int ) address; + pPDC->PDC_RNCR = bytes; } -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PDC_ReceiveFrame -//* \brief Close PDC: disable TX and RX reset transfer descriptors -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_PDC_ReceiveFrame ( - AT91PS_PDC pPDC, - char *pBuffer, - unsigned int szBuffer, - char *pNextBuffer, - unsigned int szNextBuffer ) -{ - if (AT91F_PDC_IsRxEmpty(pPDC)) { - //* Buffer and next buffer can be initialized - AT91F_PDC_SetRx(pPDC, pBuffer, szBuffer); - AT91F_PDC_SetNextRx(pPDC, pNextBuffer, szNextBuffer); - return 2; - } - else if (AT91F_PDC_IsNextRxEmpty(pPDC)) { - //* Only one buffer can be initialized - AT91F_PDC_SetNextRx(pPDC, pBuffer, szBuffer); - return 1; - } - else { - //* All buffer are in use... - return 0; + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PDC_SetNextTx */ +/** \brief Set the next transmit transfer descriptor */ +/**---------------------------------------------------------------------------- */ + __inline void AT91F_PDC_SetNextTx( AT91PS_PDC pPDC, /* \arg pointer to a PDC controller */ + char * address, /* \arg address to the next bloc to be transmitted */ + unsigned int bytes ) /* \arg number of bytes to be transmitted */ + { + pPDC->PDC_TNPR = ( unsigned int ) address; + pPDC->PDC_TNCR = bytes; + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PDC_SetRx */ +/** \brief Set the receive transfer descriptor */ +/**---------------------------------------------------------------------------- */ + __inline void AT91F_PDC_SetRx( AT91PS_PDC pPDC, /* \arg pointer to a PDC controller */ + char * address, /* \arg address to the next bloc to be received */ + unsigned int bytes ) /* \arg number of bytes to be received */ + { + pPDC->PDC_RPR = ( unsigned int ) address; + pPDC->PDC_RCR = bytes; + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PDC_SetTx */ +/** \brief Set the transmit transfer descriptor */ +/**---------------------------------------------------------------------------- */ + __inline void AT91F_PDC_SetTx( AT91PS_PDC pPDC, /* \arg pointer to a PDC controller */ + char * address, /* \arg address to the next bloc to be transmitted */ + unsigned int bytes ) /* \arg number of bytes to be transmitted */ + { + pPDC->PDC_TPR = ( unsigned int ) address; + pPDC->PDC_TCR = bytes; + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PDC_EnableTx */ +/** \brief Enable transmit */ +/**---------------------------------------------------------------------------- */ + __inline void AT91F_PDC_EnableTx( AT91PS_PDC pPDC ) /* \arg pointer to a PDC controller */ + { + pPDC->PDC_PTCR = AT91C_PDC_TXTEN; } -} + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PDC_EnableRx */ +/** \brief Enable receive */ +/**---------------------------------------------------------------------------- */ + __inline void AT91F_PDC_EnableRx( AT91PS_PDC pPDC ) /* \arg pointer to a PDC controller */ + { + pPDC->PDC_PTCR = AT91C_PDC_RXTEN; + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PDC_DisableTx */ +/** \brief Disable transmit */ +/**---------------------------------------------------------------------------- */ + __inline void AT91F_PDC_DisableTx( AT91PS_PDC pPDC ) /* \arg pointer to a PDC controller */ + { + pPDC->PDC_PTCR = AT91C_PDC_TXTDIS; + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PDC_DisableRx */ +/** \brief Disable receive */ +/**---------------------------------------------------------------------------- */ + __inline void AT91F_PDC_DisableRx( AT91PS_PDC pPDC ) /* \arg pointer to a PDC controller */ + { + pPDC->PDC_PTCR = AT91C_PDC_RXTDIS; + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PDC_IsTxEmpty */ +/** \brief Test if the current transfer descriptor has been sent */ +/**---------------------------------------------------------------------------- */ + __inline int AT91F_PDC_IsTxEmpty( /* \return return 1 if transfer is complete */ + AT91PS_PDC pPDC ) /* \arg pointer to a PDC controller */ + { + return !( pPDC->PDC_TCR ); + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PDC_IsNextTxEmpty */ +/** \brief Test if the next transfer descriptor has been moved to the current td */ +/**---------------------------------------------------------------------------- */ + __inline int AT91F_PDC_IsNextTxEmpty( /* \return return 1 if transfer is complete */ + AT91PS_PDC pPDC ) /* \arg pointer to a PDC controller */ + { + return !( pPDC->PDC_TNCR ); + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PDC_IsRxEmpty */ +/** \brief Test if the current transfer descriptor has been filled */ +/**---------------------------------------------------------------------------- */ + __inline int AT91F_PDC_IsRxEmpty( /* \return return 1 if transfer is complete */ + AT91PS_PDC pPDC ) /* \arg pointer to a PDC controller */ + { + return !( pPDC->PDC_RCR ); + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PDC_IsNextRxEmpty */ +/** \brief Test if the next transfer descriptor has been moved to the current td */ +/**---------------------------------------------------------------------------- */ + __inline int AT91F_PDC_IsNextRxEmpty( /* \return return 1 if transfer is complete */ + AT91PS_PDC pPDC ) /* \arg pointer to a PDC controller */ + { + return !( pPDC->PDC_RNCR ); + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PDC_Open */ +/** \brief Open PDC: disable TX and RX reset transfer descriptors, re-enable RX and TX */ +/**---------------------------------------------------------------------------- */ + __inline void AT91F_PDC_Open( AT91PS_PDC pPDC ) /* \arg pointer to a PDC controller */ + { + /** Disable the RX and TX PDC transfer requests */ + AT91F_PDC_DisableRx( pPDC ); + AT91F_PDC_DisableTx( pPDC ); + + /** Reset all Counter register Next buffer first */ + AT91F_PDC_SetNextTx( pPDC, ( char * ) 0, 0 ); + AT91F_PDC_SetNextRx( pPDC, ( char * ) 0, 0 ); + AT91F_PDC_SetTx( pPDC, ( char * ) 0, 0 ); + AT91F_PDC_SetRx( pPDC, ( char * ) 0, 0 ); + + /** Enable the RX and TX PDC transfer requests */ + AT91F_PDC_EnableRx( pPDC ); + AT91F_PDC_EnableTx( pPDC ); + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PDC_Close */ +/** \brief Close PDC: disable TX and RX reset transfer descriptors */ +/**---------------------------------------------------------------------------- */ + __inline void AT91F_PDC_Close( AT91PS_PDC pPDC ) /* \arg pointer to a PDC controller */ + { + /** Disable the RX and TX PDC transfer requests */ + AT91F_PDC_DisableRx( pPDC ); + AT91F_PDC_DisableTx( pPDC ); + + /** Reset all Counter register Next buffer first */ + AT91F_PDC_SetNextTx( pPDC, ( char * ) 0, 0 ); + AT91F_PDC_SetNextRx( pPDC, ( char * ) 0, 0 ); + AT91F_PDC_SetTx( pPDC, ( char * ) 0, 0 ); + AT91F_PDC_SetRx( pPDC, ( char * ) 0, 0 ); + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PDC_SendFrame */ +/** \brief Close PDC: disable TX and RX reset transfer descriptors */ +/**---------------------------------------------------------------------------- */ + __inline unsigned int AT91F_PDC_SendFrame( AT91PS_PDC pPDC, + char * pBuffer, + unsigned int szBuffer, + char * pNextBuffer, + unsigned int szNextBuffer ) + { + if( AT91F_PDC_IsTxEmpty( pPDC ) ) + { + /** Buffer and next buffer can be initialized */ + AT91F_PDC_SetTx( pPDC, pBuffer, szBuffer ); + AT91F_PDC_SetNextTx( pPDC, pNextBuffer, szNextBuffer ); + return 2; + } + else if( AT91F_PDC_IsNextTxEmpty( pPDC ) ) + { + /** Only one buffer can be initialized */ + AT91F_PDC_SetNextTx( pPDC, pBuffer, szBuffer ); + return 1; + } + else + { + /** All buffer are in use... */ + return 0; + } + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PDC_ReceiveFrame */ +/** \brief Close PDC: disable TX and RX reset transfer descriptors */ +/**---------------------------------------------------------------------------- */ + __inline unsigned int AT91F_PDC_ReceiveFrame( AT91PS_PDC pPDC, + char * pBuffer, + unsigned int szBuffer, + char * pNextBuffer, + unsigned int szNextBuffer ) + { + if( AT91F_PDC_IsRxEmpty( pPDC ) ) + { + /** Buffer and next buffer can be initialized */ + AT91F_PDC_SetRx( pPDC, pBuffer, szBuffer ); + AT91F_PDC_SetNextRx( pPDC, pNextBuffer, szNextBuffer ); + return 2; + } + else if( AT91F_PDC_IsNextRxEmpty( pPDC ) ) + { + /** Only one buffer can be initialized */ + AT91F_PDC_SetNextRx( pPDC, pBuffer, szBuffer ); + return 1; + } + else + { + /** All buffer are in use... */ + return 0; + } + } + /* ***************************************************************************** - SOFTWARE API FOR DBGU - ***************************************************************************** */ -//*---------------------------------------------------------------------------- -//* \fn AT91F_DBGU_InterruptEnable -//* \brief Enable DBGU Interrupt -//*---------------------------------------------------------------------------- -__inline void AT91F_DBGU_InterruptEnable( - AT91PS_DBGU pDbgu, // \arg pointer to a DBGU controller - unsigned int flag) // \arg dbgu interrupt to be enabled -{ +* SOFTWARE API FOR DBGU +***************************************************************************** */ +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_DBGU_InterruptEnable */ +/** \brief Enable DBGU Interrupt */ +/**---------------------------------------------------------------------------- */ + __inline void AT91F_DBGU_InterruptEnable( AT91PS_DBGU pDbgu, /* \arg pointer to a DBGU controller */ + unsigned int flag ) /* \arg dbgu interrupt to be enabled */ + { pDbgu->DBGU_IER = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_DBGU_InterruptDisable -//* \brief Disable DBGU Interrupt -//*---------------------------------------------------------------------------- -__inline void AT91F_DBGU_InterruptDisable( - AT91PS_DBGU pDbgu, // \arg pointer to a DBGU controller - unsigned int flag) // \arg dbgu interrupt to be disabled -{ + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_DBGU_InterruptDisable */ +/** \brief Disable DBGU Interrupt */ +/**---------------------------------------------------------------------------- */ + __inline void AT91F_DBGU_InterruptDisable( AT91PS_DBGU pDbgu, /* \arg pointer to a DBGU controller */ + unsigned int flag ) /* \arg dbgu interrupt to be disabled */ + { pDbgu->DBGU_IDR = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_DBGU_GetInterruptMaskStatus -//* \brief Return DBGU Interrupt Mask Status -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_DBGU_GetInterruptMaskStatus( // \return DBGU Interrupt Mask Status - AT91PS_DBGU pDbgu) // \arg pointer to a DBGU controller -{ + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_DBGU_GetInterruptMaskStatus */ +/** \brief Return DBGU Interrupt Mask Status */ +/**---------------------------------------------------------------------------- */ + __inline unsigned int AT91F_DBGU_GetInterruptMaskStatus( /* \return DBGU Interrupt Mask Status */ + AT91PS_DBGU pDbgu ) /* \arg pointer to a DBGU controller */ + { return pDbgu->DBGU_IMR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_DBGU_IsInterruptMasked -//* \brief Test if DBGU Interrupt is Masked -//*---------------------------------------------------------------------------- -__inline int AT91F_DBGU_IsInterruptMasked( - AT91PS_DBGU pDbgu, // \arg pointer to a DBGU controller - unsigned int flag) // \arg flag to be tested -{ - return (AT91F_DBGU_GetInterruptMaskStatus(pDbgu) & flag); -} + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_DBGU_IsInterruptMasked */ +/** \brief Test if DBGU Interrupt is Masked */ +/**---------------------------------------------------------------------------- */ + __inline int AT91F_DBGU_IsInterruptMasked( AT91PS_DBGU pDbgu, /* \arg pointer to a DBGU controller */ + unsigned int flag ) /* \arg flag to be tested */ + { + return( AT91F_DBGU_GetInterruptMaskStatus( pDbgu ) & flag ); + } /* ***************************************************************************** - SOFTWARE API FOR PIO - ***************************************************************************** */ -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_CfgPeriph -//* \brief Enable pins to be drived by peripheral -//*---------------------------------------------------------------------------- -__inline void AT91F_PIO_CfgPeriph( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int periphAEnable, // \arg PERIPH A to enable - unsigned int periphBEnable) // \arg PERIPH B to enable - -{ - pPio->PIO_ASR = periphAEnable; - pPio->PIO_BSR = periphBEnable; - pPio->PIO_PDR = (periphAEnable | periphBEnable); // Set in Periph mode -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_CfgOutput -//* \brief Enable PIO in output mode -//*---------------------------------------------------------------------------- -__inline void AT91F_PIO_CfgOutput( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int pioEnable) // \arg PIO to be enabled -{ - pPio->PIO_PER = pioEnable; // Set in PIO mode - pPio->PIO_OER = pioEnable; // Configure in Output -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_CfgInput -//* \brief Enable PIO in input mode -//*---------------------------------------------------------------------------- -__inline void AT91F_PIO_CfgInput( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int inputEnable) // \arg PIO to be enabled -{ - // Disable output - pPio->PIO_ODR = inputEnable; - pPio->PIO_PER = inputEnable; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_CfgOpendrain -//* \brief Configure PIO in open drain -//*---------------------------------------------------------------------------- -__inline void AT91F_PIO_CfgOpendrain( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int multiDrvEnable) // \arg pio to be configured in open drain -{ - // Configure the multi-drive option - pPio->PIO_MDDR = ~multiDrvEnable; - pPio->PIO_MDER = multiDrvEnable; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_CfgPullup -//* \brief Enable pullup on PIO -//*---------------------------------------------------------------------------- -__inline void AT91F_PIO_CfgPullup( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int pullupEnable) // \arg enable pullup on PIO -{ - // Connect or not Pullup - pPio->PIO_PPUDR = ~pullupEnable; - pPio->PIO_PPUER = pullupEnable; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_CfgDirectDrive -//* \brief Enable direct drive on PIO -//*---------------------------------------------------------------------------- -__inline void AT91F_PIO_CfgDirectDrive( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int directDrive) // \arg PIO to be configured with direct drive - -{ - // Configure the Direct Drive - pPio->PIO_OWDR = ~directDrive; - pPio->PIO_OWER = directDrive; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_CfgInputFilter -//* \brief Enable input filter on input PIO -//*---------------------------------------------------------------------------- -__inline void AT91F_PIO_CfgInputFilter( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int inputFilter) // \arg PIO to be configured with input filter - -{ - // Configure the Direct Drive - pPio->PIO_IFDR = ~inputFilter; - pPio->PIO_IFER = inputFilter; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_GetInput -//* \brief Return PIO input value -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_PIO_GetInput( // \return PIO input - AT91PS_PIO pPio) // \arg pointer to a PIO controller -{ - return pPio->PIO_PDSR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_IsInputSet -//* \brief Test if PIO is input flag is active -//*---------------------------------------------------------------------------- -__inline int AT91F_PIO_IsInputSet( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag) // \arg flag to be tested -{ - return (AT91F_PIO_GetInput(pPio) & flag); -} - - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_SetOutput -//* \brief Set to 1 output PIO -//*---------------------------------------------------------------------------- -__inline void AT91F_PIO_SetOutput( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag) // \arg output to be set -{ - pPio->PIO_SODR = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_ClearOutput -//* \brief Set to 0 output PIO -//*---------------------------------------------------------------------------- -__inline void AT91F_PIO_ClearOutput( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag) // \arg output to be cleared -{ - pPio->PIO_CODR = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_ForceOutput -//* \brief Force output when Direct drive option is enabled -//*---------------------------------------------------------------------------- -__inline void AT91F_PIO_ForceOutput( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag) // \arg output to be forced -{ - pPio->PIO_ODSR = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_Enable -//* \brief Enable PIO -//*---------------------------------------------------------------------------- -__inline void AT91F_PIO_Enable( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag) // \arg pio to be enabled -{ +* SOFTWARE API FOR PIO +***************************************************************************** */ +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PIO_CfgPeriph */ +/** \brief Enable pins to be derived by peripheral */ +/**---------------------------------------------------------------------------- */ + __inline void AT91F_PIO_CfgPeriph( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */ + unsigned int periphAEnable, /* \arg PERIPH A to enable */ + unsigned int periphBEnable ) /* \arg PERIPH B to enable */ + + { + pPio->PIO_ASR = periphAEnable; + pPio->PIO_BSR = periphBEnable; + pPio->PIO_PDR = ( periphAEnable | periphBEnable ); /* Set in Periph mode */ + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PIO_CfgOutput */ +/** \brief Enable PIO in output mode */ +/**---------------------------------------------------------------------------- */ + __inline void AT91F_PIO_CfgOutput( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */ + unsigned int pioEnable ) /* \arg PIO to be enabled */ + { + pPio->PIO_PER = pioEnable; /* Set in PIO mode */ + pPio->PIO_OER = pioEnable; /* Configure in Output */ + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PIO_CfgInput */ +/** \brief Enable PIO in input mode */ +/**---------------------------------------------------------------------------- */ + __inline void AT91F_PIO_CfgInput( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */ + unsigned int inputEnable ) /* \arg PIO to be enabled */ + { + /* Disable output */ + pPio->PIO_ODR = inputEnable; + pPio->PIO_PER = inputEnable; + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PIO_CfgOpendrain */ +/** \brief Configure PIO in open drain */ +/**---------------------------------------------------------------------------- */ + __inline void AT91F_PIO_CfgOpendrain( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */ + unsigned int multiDrvEnable ) /* \arg pio to be configured in open drain */ + { + /* Configure the multi-drive option */ + pPio->PIO_MDDR = ~multiDrvEnable; + pPio->PIO_MDER = multiDrvEnable; + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PIO_CfgPullup */ +/** \brief Enable pullup on PIO */ +/**---------------------------------------------------------------------------- */ + __inline void AT91F_PIO_CfgPullup( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */ + unsigned int pullupEnable ) /* \arg enable pullup on PIO */ + { + /* Connect or not Pullup */ + pPio->PIO_PPUDR = ~pullupEnable; + pPio->PIO_PPUER = pullupEnable; + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PIO_CfgDirectDrive */ +/** \brief Enable direct drive on PIO */ +/**---------------------------------------------------------------------------- */ + __inline void AT91F_PIO_CfgDirectDrive( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */ + unsigned int directDrive ) /* \arg PIO to be configured with direct drive */ + + { + /* Configure the Direct Drive */ + pPio->PIO_OWDR = ~directDrive; + pPio->PIO_OWER = directDrive; + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PIO_CfgInputFilter */ +/** \brief Enable input filter on input PIO */ +/**---------------------------------------------------------------------------- */ + __inline void AT91F_PIO_CfgInputFilter( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */ + unsigned int inputFilter ) /* \arg PIO to be configured with input filter */ + + { + /* Configure the Direct Drive */ + pPio->PIO_IFDR = ~inputFilter; + pPio->PIO_IFER = inputFilter; + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PIO_GetInput */ +/** \brief Return PIO input value */ +/**---------------------------------------------------------------------------- */ + __inline unsigned int AT91F_PIO_GetInput( /* \return PIO input */ + AT91PS_PIO pPio ) /* \arg pointer to a PIO controller */ + { + return pPio->PIO_PDSR; + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PIO_IsInputSet */ +/** \brief Test if PIO is input flag is active */ +/**---------------------------------------------------------------------------- */ + __inline int AT91F_PIO_IsInputSet( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */ + unsigned int flag ) /* \arg flag to be tested */ + { + return( AT91F_PIO_GetInput( pPio ) & flag ); + } + + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PIO_SetOutput */ +/** \brief Set to 1 output PIO */ +/**---------------------------------------------------------------------------- */ + __inline void AT91F_PIO_SetOutput( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */ + unsigned int flag ) /* \arg output to be set */ + { + pPio->PIO_SODR = flag; + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PIO_ClearOutput */ +/** \brief Set to 0 output PIO */ +/**---------------------------------------------------------------------------- */ + __inline void AT91F_PIO_ClearOutput( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */ + unsigned int flag ) /* \arg output to be cleared */ + { + pPio->PIO_CODR = flag; + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PIO_ForceOutput */ +/** \brief Force output when Direct drive option is enabled */ +/**---------------------------------------------------------------------------- */ + __inline void AT91F_PIO_ForceOutput( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */ + unsigned int flag ) /* \arg output to be forced */ + { + pPio->PIO_ODSR = flag; + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PIO_Enable */ +/** \brief Enable PIO */ +/**---------------------------------------------------------------------------- */ + __inline void AT91F_PIO_Enable( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */ + unsigned int flag ) /* \arg pio to be enabled */ + { pPio->PIO_PER = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_Disable -//* \brief Disable PIO -//*---------------------------------------------------------------------------- -__inline void AT91F_PIO_Disable( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag) // \arg pio to be disabled -{ + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PIO_Disable */ +/** \brief Disable PIO */ +/**---------------------------------------------------------------------------- */ + __inline void AT91F_PIO_Disable( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */ + unsigned int flag ) /* \arg pio to be disabled */ + { pPio->PIO_PDR = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_GetStatus -//* \brief Return PIO Status -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_PIO_GetStatus( // \return PIO Status - AT91PS_PIO pPio) // \arg pointer to a PIO controller -{ + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PIO_GetStatus */ +/** \brief Return PIO Status */ +/**---------------------------------------------------------------------------- */ + __inline unsigned int AT91F_PIO_GetStatus( /* \return PIO Status */ + AT91PS_PIO pPio ) /* \arg pointer to a PIO controller */ + { return pPio->PIO_PSR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_IsSet -//* \brief Test if PIO is Set -//*---------------------------------------------------------------------------- -__inline int AT91F_PIO_IsSet( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag) // \arg flag to be tested -{ - return (AT91F_PIO_GetStatus(pPio) & flag); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_OutputEnable -//* \brief Output Enable PIO -//*---------------------------------------------------------------------------- -__inline void AT91F_PIO_OutputEnable( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag) // \arg pio output to be enabled -{ + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PIO_IsSet */ +/** \brief Test if PIO is Set */ +/**---------------------------------------------------------------------------- */ + __inline int AT91F_PIO_IsSet( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */ + unsigned int flag ) /* \arg flag to be tested */ + { + return( AT91F_PIO_GetStatus( pPio ) & flag ); + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PIO_OutputEnable */ +/** \brief Output Enable PIO */ +/**---------------------------------------------------------------------------- */ + __inline void AT91F_PIO_OutputEnable( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */ + unsigned int flag ) /* \arg pio output to be enabled */ + { pPio->PIO_OER = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_OutputDisable -//* \brief Output Enable PIO -//*---------------------------------------------------------------------------- -__inline void AT91F_PIO_OutputDisable( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag) // \arg pio output to be disabled -{ + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PIO_OutputDisable */ +/** \brief Output Enable PIO */ +/**---------------------------------------------------------------------------- */ + __inline void AT91F_PIO_OutputDisable( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */ + unsigned int flag ) /* \arg pio output to be disabled */ + { pPio->PIO_ODR = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_GetOutputStatus -//* \brief Return PIO Output Status -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_PIO_GetOutputStatus( // \return PIO Output Status - AT91PS_PIO pPio) // \arg pointer to a PIO controller -{ + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PIO_GetOutputStatus */ +/** \brief Return PIO Output Status */ +/**---------------------------------------------------------------------------- */ + __inline unsigned int AT91F_PIO_GetOutputStatus( /* \return PIO Output Status */ + AT91PS_PIO pPio ) /* \arg pointer to a PIO controller */ + { return pPio->PIO_OSR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_IsOuputSet -//* \brief Test if PIO Output is Set -//*---------------------------------------------------------------------------- -__inline int AT91F_PIO_IsOutputSet( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag) // \arg flag to be tested -{ - return (AT91F_PIO_GetOutputStatus(pPio) & flag); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_InputFilterEnable -//* \brief Input Filter Enable PIO -//*---------------------------------------------------------------------------- -__inline void AT91F_PIO_InputFilterEnable( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag) // \arg pio input filter to be enabled -{ + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PIO_IsOuputSet */ +/** \brief Test if PIO Output is Set */ +/**---------------------------------------------------------------------------- */ + __inline int AT91F_PIO_IsOutputSet( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */ + unsigned int flag ) /* \arg flag to be tested */ + { + return( AT91F_PIO_GetOutputStatus( pPio ) & flag ); + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PIO_InputFilterEnable */ +/** \brief Input Filter Enable PIO */ +/**---------------------------------------------------------------------------- */ + __inline void AT91F_PIO_InputFilterEnable( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */ + unsigned int flag ) /* \arg pio input filter to be enabled */ + { pPio->PIO_IFER = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_InputFilterDisable -//* \brief Input Filter Disable PIO -//*---------------------------------------------------------------------------- -__inline void AT91F_PIO_InputFilterDisable( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag) // \arg pio input filter to be disabled -{ + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PIO_InputFilterDisable */ +/** \brief Input Filter Disable PIO */ +/**---------------------------------------------------------------------------- */ + __inline void AT91F_PIO_InputFilterDisable( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */ + unsigned int flag ) /* \arg pio input filter to be disabled */ + { pPio->PIO_IFDR = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_GetInputFilterStatus -//* \brief Return PIO Input Filter Status -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_PIO_GetInputFilterStatus( // \return PIO Input Filter Status - AT91PS_PIO pPio) // \arg pointer to a PIO controller -{ + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PIO_GetInputFilterStatus */ +/** \brief Return PIO Input Filter Status */ +/**---------------------------------------------------------------------------- */ + __inline unsigned int AT91F_PIO_GetInputFilterStatus( /* \return PIO Input Filter Status */ + AT91PS_PIO pPio ) /* \arg pointer to a PIO controller */ + { return pPio->PIO_IFSR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_IsInputFilterSet -//* \brief Test if PIO Input filter is Set -//*---------------------------------------------------------------------------- -__inline int AT91F_PIO_IsInputFilterSet( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag) // \arg flag to be tested -{ - return (AT91F_PIO_GetInputFilterStatus(pPio) & flag); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_GetOutputDataStatus -//* \brief Return PIO Output Data Status -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_PIO_GetOutputDataStatus( // \return PIO Output Data Status - AT91PS_PIO pPio) // \arg pointer to a PIO controller -{ + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PIO_IsInputFilterSet */ +/** \brief Test if PIO Input filter is Set */ +/**---------------------------------------------------------------------------- */ + __inline int AT91F_PIO_IsInputFilterSet( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */ + unsigned int flag ) /* \arg flag to be tested */ + { + return( AT91F_PIO_GetInputFilterStatus( pPio ) & flag ); + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PIO_GetOutputDataStatus */ +/** \brief Return PIO Output Data Status */ +/**---------------------------------------------------------------------------- */ + __inline unsigned int AT91F_PIO_GetOutputDataStatus( /* \return PIO Output Data Status */ + AT91PS_PIO pPio ) /* \arg pointer to a PIO controller */ + { return pPio->PIO_ODSR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_InterruptEnable -//* \brief Enable PIO Interrupt -//*---------------------------------------------------------------------------- -__inline void AT91F_PIO_InterruptEnable( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag) // \arg pio interrupt to be enabled -{ + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PIO_InterruptEnable */ +/** \brief Enable PIO Interrupt */ +/**---------------------------------------------------------------------------- */ + __inline void AT91F_PIO_InterruptEnable( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */ + unsigned int flag ) /* \arg pio interrupt to be enabled */ + { pPio->PIO_IER = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_InterruptDisable -//* \brief Disable PIO Interrupt -//*---------------------------------------------------------------------------- -__inline void AT91F_PIO_InterruptDisable( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag) // \arg pio interrupt to be disabled -{ + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PIO_InterruptDisable */ +/** \brief Disable PIO Interrupt */ +/**---------------------------------------------------------------------------- */ + __inline void AT91F_PIO_InterruptDisable( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */ + unsigned int flag ) /* \arg pio interrupt to be disabled */ + { pPio->PIO_IDR = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_GetInterruptMaskStatus -//* \brief Return PIO Interrupt Mask Status -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_PIO_GetInterruptMaskStatus( // \return PIO Interrupt Mask Status - AT91PS_PIO pPio) // \arg pointer to a PIO controller -{ + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PIO_GetInterruptMaskStatus */ +/** \brief Return PIO Interrupt Mask Status */ +/**---------------------------------------------------------------------------- */ + __inline unsigned int AT91F_PIO_GetInterruptMaskStatus( /* \return PIO Interrupt Mask Status */ + AT91PS_PIO pPio ) /* \arg pointer to a PIO controller */ + { return pPio->PIO_IMR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_GetInterruptStatus -//* \brief Return PIO Interrupt Status -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_PIO_GetInterruptStatus( // \return PIO Interrupt Status - AT91PS_PIO pPio) // \arg pointer to a PIO controller -{ + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PIO_GetInterruptStatus */ +/** \brief Return PIO Interrupt Status */ +/**---------------------------------------------------------------------------- */ + __inline unsigned int AT91F_PIO_GetInterruptStatus( /* \return PIO Interrupt Status */ + AT91PS_PIO pPio ) /* \arg pointer to a PIO controller */ + { return pPio->PIO_ISR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_IsInterruptMasked -//* \brief Test if PIO Interrupt is Masked -//*---------------------------------------------------------------------------- -__inline int AT91F_PIO_IsInterruptMasked( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag) // \arg flag to be tested -{ - return (AT91F_PIO_GetInterruptMaskStatus(pPio) & flag); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_IsInterruptSet -//* \brief Test if PIO Interrupt is Set -//*---------------------------------------------------------------------------- -__inline int AT91F_PIO_IsInterruptSet( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag) // \arg flag to be tested -{ - return (AT91F_PIO_GetInterruptStatus(pPio) & flag); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_MultiDriverEnable -//* \brief Multi Driver Enable PIO -//*---------------------------------------------------------------------------- -__inline void AT91F_PIO_MultiDriverEnable( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag) // \arg pio to be enabled -{ + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PIO_IsInterruptMasked */ +/** \brief Test if PIO Interrupt is Masked */ +/**---------------------------------------------------------------------------- */ + __inline int AT91F_PIO_IsInterruptMasked( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */ + unsigned int flag ) /* \arg flag to be tested */ + { + return( AT91F_PIO_GetInterruptMaskStatus( pPio ) & flag ); + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PIO_IsInterruptSet */ +/** \brief Test if PIO Interrupt is Set */ +/**---------------------------------------------------------------------------- */ + __inline int AT91F_PIO_IsInterruptSet( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */ + unsigned int flag ) /* \arg flag to be tested */ + { + return( AT91F_PIO_GetInterruptStatus( pPio ) & flag ); + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PIO_MultiDriverEnable */ +/** \brief Multi Driver Enable PIO */ +/**---------------------------------------------------------------------------- */ + __inline void AT91F_PIO_MultiDriverEnable( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */ + unsigned int flag ) /* \arg pio to be enabled */ + { pPio->PIO_MDER = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_MultiDriverDisable -//* \brief Multi Driver Disable PIO -//*---------------------------------------------------------------------------- -__inline void AT91F_PIO_MultiDriverDisable( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag) // \arg pio to be disabled -{ + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PIO_MultiDriverDisable */ +/** \brief Multi Driver Disable PIO */ +/**---------------------------------------------------------------------------- */ + __inline void AT91F_PIO_MultiDriverDisable( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */ + unsigned int flag ) /* \arg pio to be disabled */ + { pPio->PIO_MDDR = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_GetMultiDriverStatus -//* \brief Return PIO Multi Driver Status -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_PIO_GetMultiDriverStatus( // \return PIO Multi Driver Status - AT91PS_PIO pPio) // \arg pointer to a PIO controller -{ + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PIO_GetMultiDriverStatus */ +/** \brief Return PIO Multi Driver Status */ +/**---------------------------------------------------------------------------- */ + __inline unsigned int AT91F_PIO_GetMultiDriverStatus( /* \return PIO Multi Driver Status */ + AT91PS_PIO pPio ) /* \arg pointer to a PIO controller */ + { return pPio->PIO_MDSR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_IsMultiDriverSet -//* \brief Test if PIO MultiDriver is Set -//*---------------------------------------------------------------------------- -__inline int AT91F_PIO_IsMultiDriverSet( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag) // \arg flag to be tested -{ - return (AT91F_PIO_GetMultiDriverStatus(pPio) & flag); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_A_RegisterSelection -//* \brief PIO A Register Selection -//*---------------------------------------------------------------------------- -__inline void AT91F_PIO_A_RegisterSelection( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag) // \arg pio A register selection -{ + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PIO_IsMultiDriverSet */ +/** \brief Test if PIO MultiDriver is Set */ +/**---------------------------------------------------------------------------- */ + __inline int AT91F_PIO_IsMultiDriverSet( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */ + unsigned int flag ) /* \arg flag to be tested */ + { + return( AT91F_PIO_GetMultiDriverStatus( pPio ) & flag ); + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PIO_A_RegisterSelection */ +/** \brief PIO A Register Selection */ +/**---------------------------------------------------------------------------- */ + __inline void AT91F_PIO_A_RegisterSelection( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */ + unsigned int flag ) /* \arg pio A register selection */ + { pPio->PIO_ASR = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_B_RegisterSelection -//* \brief PIO B Register Selection -//*---------------------------------------------------------------------------- -__inline void AT91F_PIO_B_RegisterSelection( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag) // \arg pio B register selection -{ + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PIO_B_RegisterSelection */ +/** \brief PIO B Register Selection */ +/**---------------------------------------------------------------------------- */ + __inline void AT91F_PIO_B_RegisterSelection( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */ + unsigned int flag ) /* \arg pio B register selection */ + { pPio->PIO_BSR = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_Get_AB_RegisterStatus -//* \brief Return PIO Interrupt Status -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_PIO_Get_AB_RegisterStatus( // \return PIO AB Register Status - AT91PS_PIO pPio) // \arg pointer to a PIO controller -{ + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PIO_Get_AB_RegisterStatus */ +/** \brief Return PIO Interrupt Status */ +/**---------------------------------------------------------------------------- */ + __inline unsigned int AT91F_PIO_Get_AB_RegisterStatus( /* \return PIO AB Register Status */ + AT91PS_PIO pPio ) /* \arg pointer to a PIO controller */ + { return pPio->PIO_ABSR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_IsAB_RegisterSet -//* \brief Test if PIO AB Register is Set -//*---------------------------------------------------------------------------- -__inline int AT91F_PIO_IsAB_RegisterSet( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag) // \arg flag to be tested -{ - return (AT91F_PIO_Get_AB_RegisterStatus(pPio) & flag); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_OutputWriteEnable -//* \brief Output Write Enable PIO -//*---------------------------------------------------------------------------- -__inline void AT91F_PIO_OutputWriteEnable( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag) // \arg pio output write to be enabled -{ + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PIO_IsAB_RegisterSet */ +/** \brief Test if PIO AB Register is Set */ +/**---------------------------------------------------------------------------- */ + __inline int AT91F_PIO_IsAB_RegisterSet( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */ + unsigned int flag ) /* \arg flag to be tested */ + { + return( AT91F_PIO_Get_AB_RegisterStatus( pPio ) & flag ); + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PIO_OutputWriteEnable */ +/** \brief Output Write Enable PIO */ +/**---------------------------------------------------------------------------- */ + __inline void AT91F_PIO_OutputWriteEnable( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */ + unsigned int flag ) /* \arg pio output write to be enabled */ + { pPio->PIO_OWER = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_OutputWriteDisable -//* \brief Output Write Disable PIO -//*---------------------------------------------------------------------------- -__inline void AT91F_PIO_OutputWriteDisable( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag) // \arg pio output write to be disabled -{ + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PIO_OutputWriteDisable */ +/** \brief Output Write Disable PIO */ +/**---------------------------------------------------------------------------- */ + __inline void AT91F_PIO_OutputWriteDisable( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */ + unsigned int flag ) /* \arg pio output write to be disabled */ + { pPio->PIO_OWDR = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_GetOutputWriteStatus -//* \brief Return PIO Output Write Status -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_PIO_GetOutputWriteStatus( // \return PIO Output Write Status - AT91PS_PIO pPio) // \arg pointer to a PIO controller -{ + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PIO_GetOutputWriteStatus */ +/** \brief Return PIO Output Write Status */ +/**---------------------------------------------------------------------------- */ + __inline unsigned int AT91F_PIO_GetOutputWriteStatus( /* \return PIO Output Write Status */ + AT91PS_PIO pPio ) /* \arg pointer to a PIO controller */ + { return pPio->PIO_OWSR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_IsOutputWriteSet -//* \brief Test if PIO OutputWrite is Set -//*---------------------------------------------------------------------------- -__inline int AT91F_PIO_IsOutputWriteSet( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag) // \arg flag to be tested -{ - return (AT91F_PIO_GetOutputWriteStatus(pPio) & flag); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_GetCfgPullup -//* \brief Return PIO Configuration Pullup -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_PIO_GetCfgPullup( // \return PIO Configuration Pullup - AT91PS_PIO pPio) // \arg pointer to a PIO controller -{ + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PIO_IsOutputWriteSet */ +/** \brief Test if PIO OutputWrite is Set */ +/**---------------------------------------------------------------------------- */ + __inline int AT91F_PIO_IsOutputWriteSet( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */ + unsigned int flag ) /* \arg flag to be tested */ + { + return( AT91F_PIO_GetOutputWriteStatus( pPio ) & flag ); + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PIO_GetCfgPullup */ +/** \brief Return PIO Configuration Pullup */ +/**---------------------------------------------------------------------------- */ + __inline unsigned int AT91F_PIO_GetCfgPullup( /* \return PIO Configuration Pullup */ + AT91PS_PIO pPio ) /* \arg pointer to a PIO controller */ + { return pPio->PIO_PPUSR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_IsOutputDataStatusSet -//* \brief Test if PIO Output Data Status is Set -//*---------------------------------------------------------------------------- -__inline int AT91F_PIO_IsOutputDataStatusSet( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag) // \arg flag to be tested -{ - return (AT91F_PIO_GetOutputDataStatus(pPio) & flag); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_IsCfgPullupStatusSet -//* \brief Test if PIO Configuration Pullup Status is Set -//*---------------------------------------------------------------------------- -__inline int AT91F_PIO_IsCfgPullupStatusSet( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag) // \arg flag to be tested -{ - return (~AT91F_PIO_GetCfgPullup(pPio) & flag); -} + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PIO_IsOutputDataStatusSet */ +/** \brief Test if PIO Output Data Status is Set */ +/**---------------------------------------------------------------------------- */ + __inline int AT91F_PIO_IsOutputDataStatusSet( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */ + unsigned int flag ) /* \arg flag to be tested */ + { + return( AT91F_PIO_GetOutputDataStatus( pPio ) & flag ); + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PIO_IsCfgPullupStatusSet */ +/** \brief Test if PIO Configuration Pullup Status is Set */ +/**---------------------------------------------------------------------------- */ + __inline int AT91F_PIO_IsCfgPullupStatusSet( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */ + unsigned int flag ) /* \arg flag to be tested */ + { + return( ~AT91F_PIO_GetCfgPullup( pPio ) & flag ); + } /* ***************************************************************************** - SOFTWARE API FOR PMC - ***************************************************************************** */ -//*---------------------------------------------------------------------------- -//* \fn AT91F_PMC_CfgSysClkEnableReg -//* \brief Configure the System Clock Enable Register of the PMC controller -//*---------------------------------------------------------------------------- -__inline void AT91F_PMC_CfgSysClkEnableReg ( - AT91PS_PMC pPMC, // \arg pointer to PMC controller - unsigned int mode) -{ - //* Write to the SCER register - pPMC->PMC_SCER = mode; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PMC_CfgSysClkDisableReg -//* \brief Configure the System Clock Disable Register of the PMC controller -//*---------------------------------------------------------------------------- -__inline void AT91F_PMC_CfgSysClkDisableReg ( - AT91PS_PMC pPMC, // \arg pointer to PMC controller - unsigned int mode) -{ - //* Write to the SCDR register - pPMC->PMC_SCDR = mode; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PMC_GetSysClkStatusReg -//* \brief Return the System Clock Status Register of the PMC controller -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_PMC_GetSysClkStatusReg ( - AT91PS_PMC pPMC // pointer to a CAN controller - ) -{ - return pPMC->PMC_SCSR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PMC_EnablePeriphClock -//* \brief Enable peripheral clock -//*---------------------------------------------------------------------------- -__inline void AT91F_PMC_EnablePeriphClock ( - AT91PS_PMC pPMC, // \arg pointer to PMC controller - unsigned int periphIds) // \arg IDs of peripherals to enable -{ - pPMC->PMC_PCER = periphIds; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PMC_DisablePeriphClock -//* \brief Disable peripheral clock -//*---------------------------------------------------------------------------- -__inline void AT91F_PMC_DisablePeriphClock ( - AT91PS_PMC pPMC, // \arg pointer to PMC controller - unsigned int periphIds) // \arg IDs of peripherals to enable -{ - pPMC->PMC_PCDR = periphIds; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PMC_GetPeriphClock -//* \brief Get peripheral clock status -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_PMC_GetPeriphClock ( - AT91PS_PMC pPMC) // \arg pointer to PMC controller -{ - return pPMC->PMC_PCSR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_CKGR_CfgMainOscillatorReg -//* \brief Cfg the main oscillator -//*---------------------------------------------------------------------------- -__inline void AT91F_CKGR_CfgMainOscillatorReg ( - AT91PS_CKGR pCKGR, // \arg pointer to CKGR controller - unsigned int mode) -{ - pCKGR->CKGR_MOR = mode; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_CKGR_GetMainOscillatorReg -//* \brief Cfg the main oscillator -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_CKGR_GetMainOscillatorReg ( - AT91PS_CKGR pCKGR) // \arg pointer to CKGR controller -{ - return pCKGR->CKGR_MOR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_CKGR_EnableMainOscillator -//* \brief Enable the main oscillator -//*---------------------------------------------------------------------------- -__inline void AT91F_CKGR_EnableMainOscillator( - AT91PS_CKGR pCKGR) // \arg pointer to CKGR controller -{ - pCKGR->CKGR_MOR |= AT91C_CKGR_MOSCEN; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_CKGR_DisableMainOscillator -//* \brief Disable the main oscillator -//*---------------------------------------------------------------------------- -__inline void AT91F_CKGR_DisableMainOscillator ( - AT91PS_CKGR pCKGR) // \arg pointer to CKGR controller -{ - pCKGR->CKGR_MOR &= ~AT91C_CKGR_MOSCEN; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_CKGR_CfgMainOscStartUpTime -//* \brief Cfg MOR Register according to the main osc startup time -//*---------------------------------------------------------------------------- -__inline void AT91F_CKGR_CfgMainOscStartUpTime ( - AT91PS_CKGR pCKGR, // \arg pointer to CKGR controller - unsigned int startup_time, // \arg main osc startup time in microsecond (us) - unsigned int slowClock) // \arg slowClock in Hz -{ - pCKGR->CKGR_MOR &= ~AT91C_CKGR_OSCOUNT; - pCKGR->CKGR_MOR |= ((slowClock * startup_time)/(8*1000000)) << 8; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_CKGR_GetMainClockFreqReg -//* \brief Cfg the main oscillator -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_CKGR_GetMainClockFreqReg ( - AT91PS_CKGR pCKGR) // \arg pointer to CKGR controller -{ - return pCKGR->CKGR_MCFR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_CKGR_GetMainClock -//* \brief Return Main clock in Hz -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_CKGR_GetMainClock ( - AT91PS_CKGR pCKGR, // \arg pointer to CKGR controller - unsigned int slowClock) // \arg slowClock in Hz -{ - return ((pCKGR->CKGR_MCFR & AT91C_CKGR_MAINF) * slowClock) >> 4; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PMC_CfgMCKReg -//* \brief Cfg Master Clock Register -//*---------------------------------------------------------------------------- -__inline void AT91F_PMC_CfgMCKReg ( - AT91PS_PMC pPMC, // \arg pointer to PMC controller - unsigned int mode) -{ - pPMC->PMC_MCKR = mode; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PMC_GetMCKReg -//* \brief Return Master Clock Register -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_PMC_GetMCKReg( - AT91PS_PMC pPMC) // \arg pointer to PMC controller -{ - return pPMC->PMC_MCKR; -} - -//*------------------------------------------------------------------------------ -//* \fn AT91F_PMC_GetMasterClock -//* \brief Return master clock in Hz which correponds to processor clock for ARM7 -//*------------------------------------------------------------------------------ -__inline unsigned int AT91F_PMC_GetMasterClock ( - AT91PS_PMC pPMC, // \arg pointer to PMC controller - AT91PS_CKGR pCKGR, // \arg pointer to CKGR controller - unsigned int slowClock) // \arg slowClock in Hz -{ - unsigned int reg = pPMC->PMC_MCKR; - unsigned int prescaler = (1 << ((reg & AT91C_PMC_PRES) >> 2)); - unsigned int pllDivider, pllMultiplier; - - switch (reg & AT91C_PMC_CSS) { - case AT91C_PMC_CSS_SLOW_CLK: // Slow clock selected - return slowClock / prescaler; - case AT91C_PMC_CSS_MAIN_CLK: // Main clock is selected - return AT91F_CKGR_GetMainClock(pCKGR, slowClock) / prescaler; - case AT91C_PMC_CSS_PLL_CLK: // PLLB clock is selected - reg = pCKGR->CKGR_PLLR; - pllDivider = (reg & AT91C_CKGR_DIV); - pllMultiplier = ((reg & AT91C_CKGR_MUL) >> 16) + 1; - return AT91F_CKGR_GetMainClock(pCKGR, slowClock) / pllDivider * pllMultiplier / prescaler; - } - return 0; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PMC_EnablePCK -//* \brief Enable peripheral clock -//*---------------------------------------------------------------------------- -__inline void AT91F_PMC_EnablePCK ( - AT91PS_PMC pPMC, // \arg pointer to PMC controller - unsigned int pck, // \arg Peripheral clock identifier 0 .. 7 - unsigned int mode) -{ - pPMC->PMC_PCKR[pck] = mode; - pPMC->PMC_SCER = (1 << pck) << 8; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PMC_DisablePCK -//* \brief Enable peripheral clock -//*---------------------------------------------------------------------------- -__inline void AT91F_PMC_DisablePCK ( - AT91PS_PMC pPMC, // \arg pointer to PMC controller - unsigned int pck) // \arg Peripheral clock identifier 0 .. 7 -{ - pPMC->PMC_SCDR = (1 << pck) << 8; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PMC_EnableIt -//* \brief Enable PMC interrupt -//*---------------------------------------------------------------------------- -__inline void AT91F_PMC_EnableIt ( - AT91PS_PMC pPMC, // pointer to a PMC controller - unsigned int flag) // IT to be enabled -{ - //* Write to the IER register - pPMC->PMC_IER = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PMC_DisableIt -//* \brief Disable PMC interrupt -//*---------------------------------------------------------------------------- -__inline void AT91F_PMC_DisableIt ( - AT91PS_PMC pPMC, // pointer to a PMC controller - unsigned int flag) // IT to be disabled -{ - //* Write to the IDR register - pPMC->PMC_IDR = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PMC_GetStatus -//* \brief Return PMC Interrupt Status -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_PMC_GetStatus( // \return PMC Interrupt Status - AT91PS_PMC pPMC) // pointer to a PMC controller -{ - return pPMC->PMC_SR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PMC_GetInterruptMaskStatus -//* \brief Return PMC Interrupt Mask Status -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_PMC_GetInterruptMaskStatus( // \return PMC Interrupt Mask Status - AT91PS_PMC pPMC) // pointer to a PMC controller -{ - return pPMC->PMC_IMR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PMC_IsInterruptMasked -//* \brief Test if PMC Interrupt is Masked -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_PMC_IsInterruptMasked( - AT91PS_PMC pPMC, // \arg pointer to a PMC controller - unsigned int flag) // \arg flag to be tested -{ - return (AT91F_PMC_GetInterruptMaskStatus(pPMC) & flag); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PMC_IsStatusSet -//* \brief Test if PMC Status is Set -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_PMC_IsStatusSet( - AT91PS_PMC pPMC, // \arg pointer to a PMC controller - unsigned int flag) // \arg flag to be tested -{ - return (AT91F_PMC_GetStatus(pPMC) & flag); -}/* ***************************************************************************** - SOFTWARE API FOR RSTC - ***************************************************************************** */ -//*---------------------------------------------------------------------------- -//* \fn AT91F_RSTSoftReset -//* \brief Start Software Reset -//*---------------------------------------------------------------------------- -__inline void AT91F_RSTSoftReset( - AT91PS_RSTC pRSTC, - unsigned int reset) -{ - pRSTC->RSTC_RCR = (0xA5000000 | reset); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_RSTSetMode -//* \brief Set Reset Mode -//*---------------------------------------------------------------------------- -__inline void AT91F_RSTSetMode( - AT91PS_RSTC pRSTC, - unsigned int mode) -{ - pRSTC->RSTC_RMR = (0xA5000000 | mode); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_RSTGetMode -//* \brief Get Reset Mode -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_RSTGetMode( - AT91PS_RSTC pRSTC) -{ - return (pRSTC->RSTC_RMR); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_RSTGetStatus -//* \brief Get Reset Status -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_RSTGetStatus( - AT91PS_RSTC pRSTC) -{ - return (pRSTC->RSTC_RSR); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_RSTIsSoftRstActive -//* \brief Return !=0 if software reset is still not completed -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_RSTIsSoftRstActive( - AT91PS_RSTC pRSTC) -{ - return ((pRSTC->RSTC_RSR) & AT91C_RSTC_SRCMP); -} +* SOFTWARE API FOR PMC +***************************************************************************** */ +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PMC_CfgSysClkEnableReg */ +/** \brief Configure the System Clock Enable Register of the PMC controller */ +/**---------------------------------------------------------------------------- */ + __inline void AT91F_PMC_CfgSysClkEnableReg( AT91PS_PMC pPMC, /* \arg pointer to PMC controller */ + unsigned int mode ) + { + /** Write to the SCER register */ + pPMC->PMC_SCER = mode; + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PMC_CfgSysClkDisableReg */ +/** \brief Configure the System Clock Disable Register of the PMC controller */ +/**---------------------------------------------------------------------------- */ + __inline void AT91F_PMC_CfgSysClkDisableReg( AT91PS_PMC pPMC, /* \arg pointer to PMC controller */ + unsigned int mode ) + { + /** Write to the SCDR register */ + pPMC->PMC_SCDR = mode; + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PMC_GetSysClkStatusReg */ +/** \brief Return the System Clock Status Register of the PMC controller */ +/**---------------------------------------------------------------------------- */ + __inline unsigned int AT91F_PMC_GetSysClkStatusReg( AT91PS_PMC pPMC /* pointer to a CAN controller */ + ) + { + return pPMC->PMC_SCSR; + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PMC_EnablePeriphClock */ +/** \brief Enable peripheral clock */ +/**---------------------------------------------------------------------------- */ + __inline void AT91F_PMC_EnablePeriphClock( AT91PS_PMC pPMC, /* \arg pointer to PMC controller */ + unsigned int periphIds ) /* \arg IDs of peripherals to enable */ + { + pPMC->PMC_PCER = periphIds; + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PMC_DisablePeriphClock */ +/** \brief Disable peripheral clock */ +/**---------------------------------------------------------------------------- */ + __inline void AT91F_PMC_DisablePeriphClock( AT91PS_PMC pPMC, /* \arg pointer to PMC controller */ + unsigned int periphIds ) /* \arg IDs of peripherals to enable */ + { + pPMC->PMC_PCDR = periphIds; + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PMC_GetPeriphClock */ +/** \brief Get peripheral clock status */ +/**---------------------------------------------------------------------------- */ + __inline unsigned int AT91F_PMC_GetPeriphClock( AT91PS_PMC pPMC ) /* \arg pointer to PMC controller */ + { + return pPMC->PMC_PCSR; + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_CKGR_CfgMainOscillatorReg */ +/** \brief Cfg the main oscillator */ +/**---------------------------------------------------------------------------- */ + __inline void AT91F_CKGR_CfgMainOscillatorReg( AT91PS_CKGR pCKGR, /* \arg pointer to CKGR controller */ + unsigned int mode ) + { + pCKGR->CKGR_MOR = mode; + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_CKGR_GetMainOscillatorReg */ +/** \brief Cfg the main oscillator */ +/**---------------------------------------------------------------------------- */ + __inline unsigned int AT91F_CKGR_GetMainOscillatorReg( AT91PS_CKGR pCKGR ) /* \arg pointer to CKGR controller */ + { + return pCKGR->CKGR_MOR; + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_CKGR_EnableMainOscillator */ +/** \brief Enable the main oscillator */ +/**---------------------------------------------------------------------------- */ + __inline void AT91F_CKGR_EnableMainOscillator( AT91PS_CKGR pCKGR ) /* \arg pointer to CKGR controller */ + { + pCKGR->CKGR_MOR |= AT91C_CKGR_MOSCEN; + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_CKGR_DisableMainOscillator */ +/** \brief Disable the main oscillator */ +/**---------------------------------------------------------------------------- */ + __inline void AT91F_CKGR_DisableMainOscillator( AT91PS_CKGR pCKGR ) /* \arg pointer to CKGR controller */ + { + pCKGR->CKGR_MOR &= ~AT91C_CKGR_MOSCEN; + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_CKGR_CfgMainOscStartUpTime */ +/** \brief Cfg MOR Register according to the main osc startup time */ +/**---------------------------------------------------------------------------- */ + __inline void AT91F_CKGR_CfgMainOscStartUpTime( AT91PS_CKGR pCKGR, /* \arg pointer to CKGR controller */ + unsigned int startup_time, /* \arg main osc startup time in microsecond (us) */ + unsigned int slowClock ) /* \arg slowClock in Hz */ + { + pCKGR->CKGR_MOR &= ~AT91C_CKGR_OSCOUNT; + pCKGR->CKGR_MOR |= ( ( slowClock * startup_time ) / ( 8 * 1000000 ) ) << 8; + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_CKGR_GetMainClockFreqReg */ +/** \brief Cfg the main oscillator */ +/**---------------------------------------------------------------------------- */ + __inline unsigned int AT91F_CKGR_GetMainClockFreqReg( AT91PS_CKGR pCKGR ) /* \arg pointer to CKGR controller */ + { + return pCKGR->CKGR_MCFR; + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_CKGR_GetMainClock */ +/** \brief Return Main clock in Hz */ +/**---------------------------------------------------------------------------- */ + __inline unsigned int AT91F_CKGR_GetMainClock( AT91PS_CKGR pCKGR, /* \arg pointer to CKGR controller */ + unsigned int slowClock ) /* \arg slowClock in Hz */ + { + return ( ( pCKGR->CKGR_MCFR & AT91C_CKGR_MAINF ) * slowClock ) >> 4; + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PMC_CfgMCKReg */ +/** \brief Cfg Master Clock Register */ +/**---------------------------------------------------------------------------- */ + __inline void AT91F_PMC_CfgMCKReg( AT91PS_PMC pPMC, /* \arg pointer to PMC controller */ + unsigned int mode ) + { + pPMC->PMC_MCKR = mode; + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PMC_GetMCKReg */ +/** \brief Return Master Clock Register */ +/**---------------------------------------------------------------------------- */ + __inline unsigned int AT91F_PMC_GetMCKReg( AT91PS_PMC pPMC ) /* \arg pointer to PMC controller */ + { + return pPMC->PMC_MCKR; + } + +/**------------------------------------------------------------------------------ */ +/** \fn AT91F_PMC_GetMasterClock */ +/** \brief Return master clock in Hz which corresponds to processor clock for ARM7 */ +/**------------------------------------------------------------------------------ */ + __inline unsigned int AT91F_PMC_GetMasterClock( AT91PS_PMC pPMC, /* \arg pointer to PMC controller */ + AT91PS_CKGR pCKGR, /* \arg pointer to CKGR controller */ + unsigned int slowClock ) /* \arg slowClock in Hz */ + { + unsigned int reg = pPMC->PMC_MCKR; + unsigned int prescaler = ( 1 << ( ( reg & AT91C_PMC_PRES ) >> 2 ) ); + unsigned int pllDivider, pllMultiplier; + + switch( reg & AT91C_PMC_CSS ) + { + case AT91C_PMC_CSS_SLOW_CLK: /* Slow clock selected */ + return slowClock / prescaler; + + case AT91C_PMC_CSS_MAIN_CLK: /* Main clock is selected */ + return AT91F_CKGR_GetMainClock( pCKGR, slowClock ) / prescaler; + + case AT91C_PMC_CSS_PLL_CLK: /* PLLB clock is selected */ + reg = pCKGR->CKGR_PLLR; + pllDivider = ( reg & AT91C_CKGR_DIV ); + pllMultiplier = ( ( reg & AT91C_CKGR_MUL ) >> 16 ) + 1; + return AT91F_CKGR_GetMainClock( pCKGR, slowClock ) / pllDivider * pllMultiplier / prescaler; + } + + return 0; + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PMC_EnablePCK */ +/** \brief Enable peripheral clock */ +/**---------------------------------------------------------------------------- */ + __inline void AT91F_PMC_EnablePCK( AT91PS_PMC pPMC, /* \arg pointer to PMC controller */ + unsigned int pck, /* \arg Peripheral clock identifier 0 .. 7 */ + unsigned int mode ) + { + pPMC->PMC_PCKR[ pck ] = mode; + pPMC->PMC_SCER = ( 1 << pck ) << 8; + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PMC_DisablePCK */ +/** \brief Enable peripheral clock */ +/**---------------------------------------------------------------------------- */ + __inline void AT91F_PMC_DisablePCK( AT91PS_PMC pPMC, /* \arg pointer to PMC controller */ + unsigned int pck ) /* \arg Peripheral clock identifier 0 .. 7 */ + { + pPMC->PMC_SCDR = ( 1 << pck ) << 8; + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PMC_EnableIt */ +/** \brief Enable PMC interrupt */ +/**---------------------------------------------------------------------------- */ + __inline void AT91F_PMC_EnableIt( AT91PS_PMC pPMC, /* pointer to a PMC controller */ + unsigned int flag ) /* IT to be enabled */ + { + /** Write to the IER register */ + pPMC->PMC_IER = flag; + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PMC_DisableIt */ +/** \brief Disable PMC interrupt */ +/**---------------------------------------------------------------------------- */ + __inline void AT91F_PMC_DisableIt( AT91PS_PMC pPMC, /* pointer to a PMC controller */ + unsigned int flag ) /* IT to be disabled */ + { + /** Write to the IDR register */ + pPMC->PMC_IDR = flag; + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PMC_GetStatus */ +/** \brief Return PMC Interrupt Status */ +/**---------------------------------------------------------------------------- */ + __inline unsigned int AT91F_PMC_GetStatus( /* \return PMC Interrupt Status */ + AT91PS_PMC pPMC ) /* pointer to a PMC controller */ + { + return pPMC->PMC_SR; + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PMC_GetInterruptMaskStatus */ +/** \brief Return PMC Interrupt Mask Status */ +/**---------------------------------------------------------------------------- */ + __inline unsigned int AT91F_PMC_GetInterruptMaskStatus( /* \return PMC Interrupt Mask Status */ + AT91PS_PMC pPMC ) /* pointer to a PMC controller */ + { + return pPMC->PMC_IMR; + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PMC_IsInterruptMasked */ +/** \brief Test if PMC Interrupt is Masked */ +/**---------------------------------------------------------------------------- */ + __inline unsigned int AT91F_PMC_IsInterruptMasked( AT91PS_PMC pPMC, /* \arg pointer to a PMC controller */ + unsigned int flag ) /* \arg flag to be tested */ + { + return( AT91F_PMC_GetInterruptMaskStatus( pPMC ) & flag ); + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PMC_IsStatusSet */ +/** \brief Test if PMC Status is Set */ +/**---------------------------------------------------------------------------- */ + __inline unsigned int AT91F_PMC_IsStatusSet( AT91PS_PMC pPMC, /* \arg pointer to a PMC controller */ + unsigned int flag ) /* \arg flag to be tested */ + { + return( AT91F_PMC_GetStatus( pPMC ) & flag ); + } /* ***************************************************************************** + * SOFTWARE API FOR RSTC + ***************************************************************************** */ +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_RSTSoftReset */ +/** \brief Start Software Reset */ +/**---------------------------------------------------------------------------- */ + __inline void AT91F_RSTSoftReset( AT91PS_RSTC pRSTC, + unsigned int reset ) + { + pRSTC->RSTC_RCR = ( 0xA5000000 | reset ); + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_RSTSetMode */ +/** \brief Set Reset Mode */ +/**---------------------------------------------------------------------------- */ + __inline void AT91F_RSTSetMode( AT91PS_RSTC pRSTC, + unsigned int mode ) + { + pRSTC->RSTC_RMR = ( 0xA5000000 | mode ); + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_RSTGetMode */ +/** \brief Get Reset Mode */ +/**---------------------------------------------------------------------------- */ + __inline unsigned int AT91F_RSTGetMode( AT91PS_RSTC pRSTC ) + { + return( pRSTC->RSTC_RMR ); + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_RSTGetStatus */ +/** \brief Get Reset Status */ +/**---------------------------------------------------------------------------- */ + __inline unsigned int AT91F_RSTGetStatus( AT91PS_RSTC pRSTC ) + { + return( pRSTC->RSTC_RSR ); + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_RSTIsSoftRstActive */ +/** \brief Return !=0 if software reset is still not completed */ +/**---------------------------------------------------------------------------- */ + __inline unsigned int AT91F_RSTIsSoftRstActive( AT91PS_RSTC pRSTC ) + { + return( ( pRSTC->RSTC_RSR ) & AT91C_RSTC_SRCMP ); + } + /* ***************************************************************************** - SOFTWARE API FOR RTTC - ***************************************************************************** */ -//*-------------------------------------------------------------------------------------- -//* \fn AT91F_SetRTT_TimeBase() -//* \brief Set the RTT prescaler according to the TimeBase in ms -//*-------------------------------------------------------------------------------------- -__inline unsigned int AT91F_RTTSetTimeBase( - AT91PS_RTTC pRTTC, - unsigned int ms) -{ - if (ms > 2000) - return 1; // AT91C_TIME_OUT_OF_RANGE - pRTTC->RTTC_RTMR &= ~0xFFFF; - pRTTC->RTTC_RTMR |= (((ms << 15) /1000) & 0xFFFF); - return 0; -} - -//*-------------------------------------------------------------------------------------- -//* \fn AT91F_RTTSetPrescaler() -//* \brief Set the new prescaler value -//*-------------------------------------------------------------------------------------- -__inline unsigned int AT91F_RTTSetPrescaler( - AT91PS_RTTC pRTTC, - unsigned int rtpres) -{ - pRTTC->RTTC_RTMR &= ~0xFFFF; - pRTTC->RTTC_RTMR |= (rtpres & 0xFFFF); - return (pRTTC->RTTC_RTMR); -} - -//*-------------------------------------------------------------------------------------- -//* \fn AT91F_RTTRestart() -//* \brief Restart the RTT prescaler -//*-------------------------------------------------------------------------------------- -__inline void AT91F_RTTRestart( - AT91PS_RTTC pRTTC) -{ - pRTTC->RTTC_RTMR |= AT91C_RTTC_RTTRST; -} - - -//*-------------------------------------------------------------------------------------- -//* \fn AT91F_RTT_SetAlarmINT() -//* \brief Enable RTT Alarm Interrupt -//*-------------------------------------------------------------------------------------- -__inline void AT91F_RTTSetAlarmINT( - AT91PS_RTTC pRTTC) -{ - pRTTC->RTTC_RTMR |= AT91C_RTTC_ALMIEN; -} - -//*-------------------------------------------------------------------------------------- -//* \fn AT91F_RTT_ClearAlarmINT() -//* \brief Disable RTT Alarm Interrupt -//*-------------------------------------------------------------------------------------- -__inline void AT91F_RTTClearAlarmINT( - AT91PS_RTTC pRTTC) -{ - pRTTC->RTTC_RTMR &= ~AT91C_RTTC_ALMIEN; -} - -//*-------------------------------------------------------------------------------------- -//* \fn AT91F_RTT_SetRttIncINT() -//* \brief Enable RTT INC Interrupt -//*-------------------------------------------------------------------------------------- -__inline void AT91F_RTTSetRttIncINT( - AT91PS_RTTC pRTTC) -{ - pRTTC->RTTC_RTMR |= AT91C_RTTC_RTTINCIEN; -} - -//*-------------------------------------------------------------------------------------- -//* \fn AT91F_RTT_ClearRttIncINT() -//* \brief Disable RTT INC Interrupt -//*-------------------------------------------------------------------------------------- -__inline void AT91F_RTTClearRttIncINT( - AT91PS_RTTC pRTTC) -{ - pRTTC->RTTC_RTMR &= ~AT91C_RTTC_RTTINCIEN; -} - -//*-------------------------------------------------------------------------------------- -//* \fn AT91F_RTT_SetAlarmValue() -//* \brief Set RTT Alarm Value -//*-------------------------------------------------------------------------------------- -__inline void AT91F_RTTSetAlarmValue( - AT91PS_RTTC pRTTC, unsigned int alarm) -{ - pRTTC->RTTC_RTAR = alarm; -} - -//*-------------------------------------------------------------------------------------- -//* \fn AT91F_RTT_GetAlarmValue() -//* \brief Get RTT Alarm Value -//*-------------------------------------------------------------------------------------- -__inline unsigned int AT91F_RTTGetAlarmValue( - AT91PS_RTTC pRTTC) -{ - return(pRTTC->RTTC_RTAR); -} - -//*-------------------------------------------------------------------------------------- -//* \fn AT91F_RTTGetStatus() -//* \brief Read the RTT status -//*-------------------------------------------------------------------------------------- -__inline unsigned int AT91F_RTTGetStatus( - AT91PS_RTTC pRTTC) -{ - return(pRTTC->RTTC_RTSR); -} - -//*-------------------------------------------------------------------------------------- -//* \fn AT91F_RTT_ReadValue() -//* \brief Read the RTT value -//*-------------------------------------------------------------------------------------- -__inline unsigned int AT91F_RTTReadValue( - AT91PS_RTTC pRTTC) -{ - register volatile unsigned int val1,val2; - do - { - val1 = pRTTC->RTTC_RTVR; - val2 = pRTTC->RTTC_RTVR; - } - while(val1 != val2); - return(val1); -} +* SOFTWARE API FOR RTTC +***************************************************************************** */ +/**-------------------------------------------------------------------------------------- */ +/** \fn AT91F_SetRTT_TimeBase() */ +/** \brief Set the RTT prescaler according to the TimeBase in ms */ +/**-------------------------------------------------------------------------------------- */ + __inline unsigned int AT91F_RTTSetTimeBase( AT91PS_RTTC pRTTC, + unsigned int ms ) + { + if( ms > 2000 ) + { + return 1; /* AT91C_TIME_OUT_OF_RANGE */ + } + + pRTTC->RTTC_RTMR &= ~0xFFFF; + pRTTC->RTTC_RTMR |= ( ( ( ms << 15 ) / 1000 ) & 0xFFFF ); + return 0; + } + +/**-------------------------------------------------------------------------------------- */ +/** \fn AT91F_RTTSetPrescaler() */ +/** \brief Set the new prescaler value */ +/**-------------------------------------------------------------------------------------- */ + __inline unsigned int AT91F_RTTSetPrescaler( AT91PS_RTTC pRTTC, + unsigned int rtpres ) + { + pRTTC->RTTC_RTMR &= ~0xFFFF; + pRTTC->RTTC_RTMR |= ( rtpres & 0xFFFF ); + return( pRTTC->RTTC_RTMR ); + } + +/**-------------------------------------------------------------------------------------- */ +/** \fn AT91F_RTTRestart() */ +/** \brief Restart the RTT prescaler */ +/**-------------------------------------------------------------------------------------- */ + __inline void AT91F_RTTRestart( AT91PS_RTTC pRTTC ) + { + pRTTC->RTTC_RTMR |= AT91C_RTTC_RTTRST; + } + + +/**-------------------------------------------------------------------------------------- */ +/** \fn AT91F_RTT_SetAlarmINT() */ +/** \brief Enable RTT Alarm Interrupt */ +/**-------------------------------------------------------------------------------------- */ + __inline void AT91F_RTTSetAlarmINT( AT91PS_RTTC pRTTC ) + { + pRTTC->RTTC_RTMR |= AT91C_RTTC_ALMIEN; + } + +/**-------------------------------------------------------------------------------------- */ +/** \fn AT91F_RTT_ClearAlarmINT() */ +/** \brief Disable RTT Alarm Interrupt */ +/**-------------------------------------------------------------------------------------- */ + __inline void AT91F_RTTClearAlarmINT( AT91PS_RTTC pRTTC ) + { + pRTTC->RTTC_RTMR &= ~AT91C_RTTC_ALMIEN; + } + +/**-------------------------------------------------------------------------------------- */ +/** \fn AT91F_RTT_SetRttIncINT() */ +/** \brief Enable RTT INC Interrupt */ +/**-------------------------------------------------------------------------------------- */ + __inline void AT91F_RTTSetRttIncINT( AT91PS_RTTC pRTTC ) + { + pRTTC->RTTC_RTMR |= AT91C_RTTC_RTTINCIEN; + } + +/**-------------------------------------------------------------------------------------- */ +/** \fn AT91F_RTT_ClearRttIncINT() */ +/** \brief Disable RTT INC Interrupt */ +/**-------------------------------------------------------------------------------------- */ + __inline void AT91F_RTTClearRttIncINT( AT91PS_RTTC pRTTC ) + { + pRTTC->RTTC_RTMR &= ~AT91C_RTTC_RTTINCIEN; + } + +/**-------------------------------------------------------------------------------------- */ +/** \fn AT91F_RTT_SetAlarmValue() */ +/** \brief Set RTT Alarm Value */ +/**-------------------------------------------------------------------------------------- */ + __inline void AT91F_RTTSetAlarmValue( AT91PS_RTTC pRTTC, + unsigned int alarm ) + { + pRTTC->RTTC_RTAR = alarm; + } + +/**-------------------------------------------------------------------------------------- */ +/** \fn AT91F_RTT_GetAlarmValue() */ +/** \brief Get RTT Alarm Value */ +/**-------------------------------------------------------------------------------------- */ + __inline unsigned int AT91F_RTTGetAlarmValue( AT91PS_RTTC pRTTC ) + { + return( pRTTC->RTTC_RTAR ); + } + +/**-------------------------------------------------------------------------------------- */ +/** \fn AT91F_RTTGetStatus() */ +/** \brief Read the RTT status */ +/**-------------------------------------------------------------------------------------- */ + __inline unsigned int AT91F_RTTGetStatus( AT91PS_RTTC pRTTC ) + { + return( pRTTC->RTTC_RTSR ); + } + +/**-------------------------------------------------------------------------------------- */ +/** \fn AT91F_RTT_ReadValue() */ +/** \brief Read the RTT value */ +/**-------------------------------------------------------------------------------------- */ + __inline unsigned int AT91F_RTTReadValue( AT91PS_RTTC pRTTC ) + { + register volatile unsigned int val1, val2; + + do + { + val1 = pRTTC->RTTC_RTVR; + val2 = pRTTC->RTTC_RTVR; + } + while( val1 != val2 ); + + return( val1 ); + } + /* ***************************************************************************** - SOFTWARE API FOR PITC - ***************************************************************************** */ -//*---------------------------------------------------------------------------- -//* \fn AT91F_PITInit -//* \brief System timer init : period in \ No newline at end of file +* SOFTWARE API FOR PITC +***************************************************************************** */ +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PITInit */ +/** \brief System timer init : period in */ diff --git a/Source/portable/GCC/ARM7_AT91SAM7S/port.c b/Source/portable/GCC/ARM7_AT91SAM7S/port.c index 9a111a957..c8547669e 100644 --- a/Source/portable/GCC/ARM7_AT91SAM7S/port.c +++ b/Source/portable/GCC/ARM7_AT91SAM7S/port.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -28,12 +28,12 @@ /*----------------------------------------------------------- - * Implementation of functions defined in portable.h for the ARM7 port. - * - * Components that can be compiled to either ARM or THUMB mode are - * contained in this file. The ISR routines, which can only be compiled - * to ARM mode are contained in portISR.c. - *----------------------------------------------------------*/ +* Implementation of functions defined in portable.h for the ARM7 port. +* +* Components that can be compiled to either ARM or THUMB mode are +* contained in this file. The ISR routines, which can only be compiled +* to ARM mode are contained in portISR.c. +*----------------------------------------------------------*/ /* Standard includes. */ #include @@ -46,24 +46,24 @@ #include "AT91SAM7X256.h" /* Constants required to setup the task context. */ -#define portINITIAL_SPSR ( ( StackType_t ) 0x1f ) /* System mode, ARM mode, interrupts enabled. */ -#define portTHUMB_MODE_BIT ( ( StackType_t ) 0x20 ) -#define portINSTRUCTION_SIZE ( ( StackType_t ) 4 ) -#define portNO_CRITICAL_SECTION_NESTING ( ( StackType_t ) 0 ) +#define portINITIAL_SPSR ( ( StackType_t ) 0x1f ) /* System mode, ARM mode, interrupts enabled. */ +#define portTHUMB_MODE_BIT ( ( StackType_t ) 0x20 ) +#define portINSTRUCTION_SIZE ( ( StackType_t ) 4 ) +#define portNO_CRITICAL_SECTION_NESTING ( ( StackType_t ) 0 ) /* Constants required to setup the tick ISR. */ -#define portENABLE_TIMER ( ( uint8_t ) 0x01 ) -#define portPRESCALE_VALUE 0x00 -#define portINTERRUPT_ON_MATCH ( ( uint32_t ) 0x01 ) -#define portRESET_COUNT_ON_MATCH ( ( uint32_t ) 0x02 ) +#define portENABLE_TIMER ( ( uint8_t ) 0x01 ) +#define portPRESCALE_VALUE 0x00 +#define portINTERRUPT_ON_MATCH ( ( uint32_t ) 0x01 ) +#define portRESET_COUNT_ON_MATCH ( ( uint32_t ) 0x02 ) /* Constants required to setup the PIT. */ -#define portPIT_CLOCK_DIVISOR ( ( uint32_t ) 16 ) -#define portPIT_COUNTER_VALUE ( ( ( configCPU_CLOCK_HZ / portPIT_CLOCK_DIVISOR ) / 1000UL ) * portTICK_PERIOD_MS ) +#define portPIT_CLOCK_DIVISOR ( ( uint32_t ) 16 ) +#define portPIT_COUNTER_VALUE ( ( ( configCPU_CLOCK_HZ / portPIT_CLOCK_DIVISOR ) / 1000UL ) * portTICK_PERIOD_MS ) -#define portINT_LEVEL_SENSITIVE 0 -#define portPIT_ENABLE ( ( uint16_t ) 0x1 << 24 ) -#define portPIT_INT_ENABLE ( ( uint16_t ) 0x1 << 25 ) +#define portINT_LEVEL_SENSITIVE 0 +#define portPIT_ENABLE ( ( uint16_t ) 0x1 << 24 ) +#define portPIT_INT_ENABLE ( ( uint16_t ) 0x1 << 25 ) /*-----------------------------------------------------------*/ /* Setup the timer to generate the tick interrupts. */ @@ -83,61 +83,63 @@ extern void vPortISRStartFirstTask( void ); * * See header file for description. */ -StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters ) +StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, + TaskFunction_t pxCode, + void * pvParameters ) { -StackType_t *pxOriginalTOS; + StackType_t * pxOriginalTOS; pxOriginalTOS = pxTopOfStack; /* To ensure asserts in tasks.c don't fail, although in this case the assert - is not really required. */ + * is not really required. */ pxTopOfStack--; /* Setup the initial stack of the task. The stack is set exactly as - expected by the portRESTORE_CONTEXT() macro. */ + * expected by the portRESTORE_CONTEXT() macro. */ /* First on the stack is the return address - which in this case is the - start of the task. The offset is added to make the return address appear - as it would within an IRQ ISR. */ + * start of the task. The offset is added to make the return address appear + * as it would within an IRQ ISR. */ *pxTopOfStack = ( StackType_t ) pxCode + portINSTRUCTION_SIZE; pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x00000000; /* R14 */ + *pxTopOfStack = ( StackType_t ) 0x00000000; /* R14 */ pxTopOfStack--; *pxTopOfStack = ( StackType_t ) pxOriginalTOS; /* Stack used when task starts goes in R13. */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x12121212; /* R12 */ + *pxTopOfStack = ( StackType_t ) 0x12121212; /* R12 */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x11111111; /* R11 */ + *pxTopOfStack = ( StackType_t ) 0x11111111; /* R11 */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x10101010; /* R10 */ + *pxTopOfStack = ( StackType_t ) 0x10101010; /* R10 */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x09090909; /* R9 */ + *pxTopOfStack = ( StackType_t ) 0x09090909; /* R9 */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x08080808; /* R8 */ + *pxTopOfStack = ( StackType_t ) 0x08080808; /* R8 */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x07070707; /* R7 */ + *pxTopOfStack = ( StackType_t ) 0x07070707; /* R7 */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x06060606; /* R6 */ + *pxTopOfStack = ( StackType_t ) 0x06060606; /* R6 */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x05050505; /* R5 */ + *pxTopOfStack = ( StackType_t ) 0x05050505; /* R5 */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x04040404; /* R4 */ + *pxTopOfStack = ( StackType_t ) 0x04040404; /* R4 */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x03030303; /* R3 */ + *pxTopOfStack = ( StackType_t ) 0x03030303; /* R3 */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x02020202; /* R2 */ + *pxTopOfStack = ( StackType_t ) 0x02020202; /* R2 */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x01010101; /* R1 */ + *pxTopOfStack = ( StackType_t ) 0x01010101; /* R1 */ pxTopOfStack--; /* When the task starts is will expect to find the function parameter in - R0. */ + * R0. */ *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */ pxTopOfStack--; /* The last thing onto the stack is the status register, which is set for - system mode, with interrupts enabled. */ + * system mode, with interrupts enabled. */ *pxTopOfStack = ( StackType_t ) portINITIAL_SPSR; #ifdef THUMB_INTERWORK @@ -150,9 +152,9 @@ StackType_t *pxOriginalTOS; pxTopOfStack--; /* Some optimisation levels use the stack differently to others. This - means the interrupt flags cannot always be stored on the stack and will - instead be stored in a variable, which is then saved as part of the - tasks context. */ + * means the interrupt flags cannot always be stored on the stack and will + * instead be stored in a variable, which is then saved as part of the + * tasks context. */ *pxTopOfStack = portNO_CRITICAL_SECTION_NESTING; return pxTopOfStack; @@ -162,7 +164,7 @@ StackType_t *pxOriginalTOS; BaseType_t xPortStartScheduler( void ) { /* Start the timer that generates the tick ISR. Interrupts are disabled - here already. */ + * here already. */ prvSetupTimerInterrupt(); /* Start the first task. */ @@ -176,7 +178,7 @@ BaseType_t xPortStartScheduler( void ) void vPortEndScheduler( void ) { /* It is unlikely that the ARM port will require this function as there - is nothing to return to. */ + * is nothing to return to. */ } /*-----------------------------------------------------------*/ @@ -185,27 +187,23 @@ void vPortEndScheduler( void ) */ static void prvSetupTimerInterrupt( void ) { -AT91PS_PITC pxPIT = AT91C_BASE_PITC; + AT91PS_PITC pxPIT = AT91C_BASE_PITC; /* Setup the AIC for PIT interrupts. The interrupt routine chosen depends - on whether the preemptive or cooperative scheduler is being used. */ + * on whether the preemptive or cooperative scheduler is being used. */ #if configUSE_PREEMPTION == 0 - - extern void ( vNonPreemptiveTick ) ( void ); - AT91F_AIC_ConfigureIt( AT91C_ID_SYS, AT91C_AIC_PRIOR_HIGHEST, portINT_LEVEL_SENSITIVE, ( void (*)(void) ) vNonPreemptiveTick ); - + extern void( vNonPreemptiveTick ) ( void ); + AT91F_AIC_ConfigureIt( AT91C_ID_SYS, AT91C_AIC_PRIOR_HIGHEST, portINT_LEVEL_SENSITIVE, ( void ( * )( void ) )vNonPreemptiveTick ); #else - - extern void ( vPreemptiveTick )( void ); - AT91F_AIC_ConfigureIt( AT91C_ID_SYS, AT91C_AIC_PRIOR_HIGHEST, portINT_LEVEL_SENSITIVE, ( void (*)(void) ) vPreemptiveTick ); - + extern void( vPreemptiveTick )( void ); + AT91F_AIC_ConfigureIt( AT91C_ID_SYS, AT91C_AIC_PRIOR_HIGHEST, portINT_LEVEL_SENSITIVE, ( void ( * )( void ) )vPreemptiveTick ); #endif /* Configure the PIT period. */ pxPIT->PITC_PIMR = portPIT_ENABLE | portPIT_INT_ENABLE | portPIT_COUNTER_VALUE; /* Enable the interrupt. Global interrupts are disabled at this point so - this is safe. */ + * this is safe. */ AT91C_BASE_AIC->AIC_IECR = 0x1 << AT91C_ID_SYS; } /*-----------------------------------------------------------*/ diff --git a/Source/portable/GCC/ARM7_AT91SAM7S/portISR.c b/Source/portable/GCC/ARM7_AT91SAM7S/portISR.c index 5e7cc8e39..651c4d6c7 100644 --- a/Source/portable/GCC/ARM7_AT91SAM7S/portISR.c +++ b/Source/portable/GCC/ARM7_AT91SAM7S/portISR.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -28,17 +28,17 @@ /*----------------------------------------------------------- - * Components that can be compiled to either ARM or THUMB mode are - * contained in port.c The ISR routines, which can only be compiled - * to ARM mode, are contained in this file. - *----------------------------------------------------------*/ +* Components that can be compiled to either ARM or THUMB mode are +* contained in port.c The ISR routines, which can only be compiled +* to ARM mode, are contained in this file. +*----------------------------------------------------------*/ /* - Changes from V3.2.4 - - + The assembler statements are now included in a single asm block rather - than each line having its own asm block. -*/ + * Changes from V3.2.4 + * + + The assembler statements are now included in a single asm block rather + + than each line having its own asm block. + */ /* Scheduler includes. */ #include "FreeRTOS.h" @@ -47,17 +47,17 @@ #include "AT91SAM7X256.h" /* Constants required to handle interrupts. */ -#define portTIMER_MATCH_ISR_BIT ( ( uint8_t ) 0x01 ) -#define portCLEAR_VIC_INTERRUPT ( ( uint32_t ) 0 ) +#define portTIMER_MATCH_ISR_BIT ( ( uint8_t ) 0x01 ) +#define portCLEAR_VIC_INTERRUPT ( ( uint32_t ) 0 ) /* Constants required to handle critical sections. */ -#define portNO_CRITICAL_NESTING ( ( uint32_t ) 0 ) +#define portNO_CRITICAL_NESTING ( ( uint32_t ) 0 ) volatile uint32_t ulCriticalNesting = 9999UL; /*-----------------------------------------------------------*/ /* ISR to handle manual context switches (from a call to taskYIELD()). */ -void vPortYieldProcessor( void ) __attribute__((interrupt("SWI"), naked)); +void vPortYieldProcessor( void ) __attribute__( ( interrupt( "SWI" ), naked ) ); /* * The scheduler can only be started from ARM mode, hence the inclusion of this @@ -69,7 +69,7 @@ void vPortISRStartFirstTask( void ); void vPortISRStartFirstTask( void ) { /* Simply start the scheduler. This is included here as it can only be - called from ARM mode. */ + * called from ARM mode. */ portRESTORE_CONTEXT(); } /*-----------------------------------------------------------*/ @@ -85,8 +85,8 @@ void vPortISRStartFirstTask( void ) void vPortYieldProcessor( void ) { /* Within an IRQ ISR the link register has an offset from the true return - address, but an SWI ISR does not. Add the offset manually so the same - ISR return code can be used in both cases. */ + * address, but an SWI ISR does not. Add the offset manually so the same + * ISR return code can be used in both cases. */ __asm volatile ( "ADD LR, LR, #4" ); /* Perform the context switch. First save the context of the current task. */ @@ -107,16 +107,16 @@ void vPortYieldProcessor( void ) #if configUSE_PREEMPTION == 0 - /* The cooperative scheduler requires a normal IRQ service routine to - simply increment the system tick. */ - void vNonPreemptiveTick( void ) __attribute__ ((interrupt ("IRQ"))); +/* The cooperative scheduler requires a normal IRQ service routine to + * simply increment the system tick. */ + void vNonPreemptiveTick( void ) __attribute__( ( interrupt( "IRQ" ) ) ); void vNonPreemptiveTick( void ) { uint32_t ulDummy; /* Increment the tick count - which may wake some tasks but as the - preemptive scheduler is not being used any woken task is not given - processor time no matter what its priority. */ + * preemptive scheduler is not being used any woken task is not given + * processor time no matter what its priority. */ xTaskIncrementTick(); /* Clear the PIT interrupt. */ @@ -126,11 +126,11 @@ void vPortYieldProcessor( void ) AT91C_BASE_AIC->AIC_EOICR = ulDummy; } -#else +#else /* if configUSE_PREEMPTION == 0 */ - /* The preemptive scheduler is defined as "naked" as the full context is - saved on entry as part of the context switch. */ - void vPreemptiveTick( void ) __attribute__((naked)); +/* The preemptive scheduler is defined as "naked" as the full context is + * saved on entry as part of the context switch. */ + void vPreemptiveTick( void ) __attribute__( ( naked ) ); void vPreemptiveTick( void ) { /* Save the context of the current task. */ @@ -149,7 +149,7 @@ void vPortYieldProcessor( void ) portRESTORE_CONTEXT(); } -#endif +#endif /* if configUSE_PREEMPTION == 0 */ /*-----------------------------------------------------------*/ /* @@ -158,49 +158,49 @@ void vPortYieldProcessor( void ) * ensure a switch to ARM mode. When THUMB_INTERWORK is not defined then * the utilities are defined as macros in portmacro.h - as per other ports. */ -void vPortDisableInterruptsFromThumb( void ) __attribute__ ((naked)); -void vPortEnableInterruptsFromThumb( void ) __attribute__ ((naked)); +void vPortDisableInterruptsFromThumb( void ) __attribute__( ( naked ) ); +void vPortEnableInterruptsFromThumb( void ) __attribute__( ( naked ) ); void vPortDisableInterruptsFromThumb( void ) { __asm volatile ( - "STMDB SP!, {R0} \n\t" /* Push R0. */ - "MRS R0, CPSR \n\t" /* Get CPSR. */ - "ORR R0, R0, #0xC0 \n\t" /* Disable IRQ, FIQ. */ - "MSR CPSR, R0 \n\t" /* Write back modified value. */ - "LDMIA SP!, {R0} \n\t" /* Pop R0. */ - "BX R14" ); /* Return back to thumb. */ + "STMDB SP!, {R0} \n\t" /* Push R0. */ + "MRS R0, CPSR \n\t" /* Get CPSR. */ + "ORR R0, R0, #0xC0 \n\t" /* Disable IRQ, FIQ. */ + "MSR CPSR, R0 \n\t" /* Write back modified value. */ + "LDMIA SP!, {R0} \n\t" /* Pop R0. */ + "BX R14" ); /* Return back to thumb. */ } void vPortEnableInterruptsFromThumb( void ) { __asm volatile ( - "STMDB SP!, {R0} \n\t" /* Push R0. */ - "MRS R0, CPSR \n\t" /* Get CPSR. */ - "BIC R0, R0, #0xC0 \n\t" /* Enable IRQ, FIQ. */ - "MSR CPSR, R0 \n\t" /* Write back modified value. */ - "LDMIA SP!, {R0} \n\t" /* Pop R0. */ - "BX R14" ); /* Return back to thumb. */ + "STMDB SP!, {R0} \n\t" /* Push R0. */ + "MRS R0, CPSR \n\t" /* Get CPSR. */ + "BIC R0, R0, #0xC0 \n\t" /* Enable IRQ, FIQ. */ + "MSR CPSR, R0 \n\t" /* Write back modified value. */ + "LDMIA SP!, {R0} \n\t" /* Pop R0. */ + "BX R14" ); /* Return back to thumb. */ } /* The code generated by the GCC compiler uses the stack in different ways at -different optimisation levels. The interrupt flags can therefore not always -be saved to the stack. Instead the critical section nesting level is stored -in a variable, which is then saved as part of the stack context. */ + * different optimisation levels. The interrupt flags can therefore not always + * be saved to the stack. Instead the critical section nesting level is stored + * in a variable, which is then saved as part of the stack context. */ void vPortEnterCritical( void ) { /* Disable interrupts as per portDISABLE_INTERRUPTS(); */ __asm volatile ( - "STMDB SP!, {R0} \n\t" /* Push R0. */ - "MRS R0, CPSR \n\t" /* Get CPSR. */ - "ORR R0, R0, #0xC0 \n\t" /* Disable IRQ, FIQ. */ - "MSR CPSR, R0 \n\t" /* Write back modified value. */ - "LDMIA SP!, {R0}" ); /* Pop R0. */ - - /* Now interrupts are disabled ulCriticalNesting can be accessed - directly. Increment ulCriticalNesting to keep a count of how many times - portENTER_CRITICAL() has been called. */ + "STMDB SP!, {R0} \n\t" /* Push R0. */ + "MRS R0, CPSR \n\t" /* Get CPSR. */ + "ORR R0, R0, #0xC0 \n\t" /* Disable IRQ, FIQ. */ + "MSR CPSR, R0 \n\t" /* Write back modified value. */ + "LDMIA SP!, {R0}" ); /* Pop R0. */ + + /* Now that interrupts are disabled, ulCriticalNesting can be accessed + * directly. Increment ulCriticalNesting to keep a count of how many times + * portENTER_CRITICAL() has been called. */ ulCriticalNesting++; } @@ -212,16 +212,16 @@ void vPortExitCritical( void ) ulCriticalNesting--; /* If the nesting level has reached zero then interrupts should be - re-enabled. */ + * re-enabled. */ if( ulCriticalNesting == portNO_CRITICAL_NESTING ) { /* Enable interrupts as per portEXIT_CRITICAL(). */ __asm volatile ( - "STMDB SP!, {R0} \n\t" /* Push R0. */ - "MRS R0, CPSR \n\t" /* Get CPSR. */ - "BIC R0, R0, #0xC0 \n\t" /* Enable IRQ, FIQ. */ - "MSR CPSR, R0 \n\t" /* Write back modified value. */ - "LDMIA SP!, {R0}" ); /* Pop R0. */ + "STMDB SP!, {R0} \n\t" /* Push R0. */ + "MRS R0, CPSR \n\t" /* Get CPSR. */ + "BIC R0, R0, #0xC0 \n\t" /* Enable IRQ, FIQ. */ + "MSR CPSR, R0 \n\t" /* Write back modified value. */ + "LDMIA SP!, {R0}" ); /* Pop R0. */ } } } diff --git a/Source/portable/GCC/ARM7_AT91SAM7S/portmacro.h b/Source/portable/GCC/ARM7_AT91SAM7S/portmacro.h index fe17c6388..2c1f8ae73 100644 --- a/Source/portable/GCC/ARM7_AT91SAM7S/portmacro.h +++ b/Source/portable/GCC/ARM7_AT91SAM7S/portmacro.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -27,27 +27,27 @@ */ /* - Changes from V3.2.3 - - + Modified portENTER_SWITCHING_ISR() to allow use with GCC V4.0.1. - - Changes from V3.2.4 - - + Removed the use of the %0 parameter within the assembler macros and - replaced them with hard coded registers. This will ensure the - assembler does not select the link register as the temp register as - was occasionally happening previously. - - + The assembler statements are now included in a single asm block rather - than each line having its own asm block. - - Changes from V4.5.0 - - + Removed the portENTER_SWITCHING_ISR() and portEXIT_SWITCHING_ISR() macros - and replaced them with portYIELD_FROM_ISR() macro. Application code - should now make use of the portSAVE_CONTEXT() and portRESTORE_CONTEXT() - macros as per the V4.5.1 demo code. -*/ + * Changes from V3.2.3 + * + + Modified portENTER_SWITCHING_ISR() to allow use with GCC V4.0.1. + + + + Changes from V3.2.4 + + + + Removed the use of the %0 parameter within the assembler macros and + + replaced them with hard coded registers. This will ensure the + + assembler does not select the link register as the temp register as + + was occasionally happening previously. + + + + The assembler statements are now included in a single asm block rather + + than each line having its own asm block. + + + + Changes from V4.5.0 + + + + Removed the portENTER_SWITCHING_ISR() and portEXIT_SWITCHING_ISR() macros + + and replaced them with portYIELD_FROM_ISR() macro. Application code + + should now make use of the portSAVE_CONTEXT() and portRESTORE_CONTEXT() + + macros as per the V4.5.1 demo code. + */ #ifndef PORTMACRO_H #define PORTMACRO_H @@ -69,34 +69,34 @@ */ /* Type definitions. */ -#define portCHAR char -#define portFLOAT float -#define portDOUBLE double -#define portLONG long -#define portSHORT short -#define portSTACK_TYPE uint32_t -#define portBASE_TYPE portLONG - -typedef portSTACK_TYPE StackType_t; -typedef long BaseType_t; -typedef unsigned long UBaseType_t; - -#if( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS ) - typedef uint16_t TickType_t; - #define portMAX_DELAY ( TickType_t ) 0xffff +#define portCHAR char +#define portFLOAT float +#define portDOUBLE double +#define portLONG long +#define portSHORT short +#define portSTACK_TYPE uint32_t +#define portBASE_TYPE portLONG + +typedef portSTACK_TYPE StackType_t; +typedef long BaseType_t; +typedef unsigned long UBaseType_t; + +#if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS ) + typedef uint16_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffff #elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS ) - typedef uint32_t TickType_t; - #define portMAX_DELAY ( TickType_t ) ( 0xFFFFFFFFUL ) + typedef uint32_t TickType_t; + #define portMAX_DELAY ( TickType_t ) ( 0xFFFFFFFFUL ) #else #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width. #endif /*-----------------------------------------------------------*/ /* Architecture specifics. */ -#define portSTACK_GROWTH ( -1 ) -#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) -#define portBYTE_ALIGNMENT 8 -#define portNOP() __asm volatile ( "NOP" ); +#define portSTACK_GROWTH ( -1 ) +#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) +#define portBYTE_ALIGNMENT 8 +#define portNOP() __asm volatile ( "NOP" ); /*-----------------------------------------------------------*/ @@ -109,92 +109,92 @@ typedef unsigned long UBaseType_t; * THUMB mode code will result in a compile time error. */ -#define portRESTORE_CONTEXT() \ -{ \ -extern volatile void * volatile pxCurrentTCB; \ -extern volatile uint32_t ulCriticalNesting; \ - \ - /* Set the LR to the task stack. */ \ - __asm volatile ( \ - "LDR R0, =pxCurrentTCB \n\t" \ - "LDR R0, [R0] \n\t" \ - "LDR LR, [R0] \n\t" \ - \ - /* The critical nesting depth is the first item on the stack. */ \ - /* Load it into the ulCriticalNesting variable. */ \ - "LDR R0, =ulCriticalNesting \n\t" \ - "LDMFD LR!, {R1} \n\t" \ - "STR R1, [R0] \n\t" \ - \ - /* Get the SPSR from the stack. */ \ - "LDMFD LR!, {R0} \n\t" \ - "MSR SPSR, R0 \n\t" \ - \ - /* Restore all system mode registers for the task. */ \ - "LDMFD LR, {R0-R14}^ \n\t" \ - "NOP \n\t" \ - \ - /* Restore the return address. */ \ - "LDR LR, [LR, #+60] \n\t" \ - \ - /* And return - correcting the offset in the LR to obtain the */ \ - /* correct address. */ \ - "SUBS PC, LR, #4 \n\t" \ - ); \ - ( void ) ulCriticalNesting; \ - ( void ) pxCurrentTCB; \ -} +#define portRESTORE_CONTEXT() \ + { \ + extern volatile void * volatile pxCurrentTCB; \ + extern volatile uint32_t ulCriticalNesting; \ + \ + /* Set the LR to the task stack. */ \ + __asm volatile ( \ + "LDR R0, =pxCurrentTCB \n\t" \ + "LDR R0, [R0] \n\t" \ + "LDR LR, [R0] \n\t" \ + \ + /* The critical nesting depth is the first item on the stack. */ \ + /* Load it into the ulCriticalNesting variable. */ \ + "LDR R0, =ulCriticalNesting \n\t" \ + "LDMFD LR!, {R1} \n\t" \ + "STR R1, [R0] \n\t" \ + \ + /* Get the SPSR from the stack. */ \ + "LDMFD LR!, {R0} \n\t" \ + "MSR SPSR, R0 \n\t" \ + \ + /* Restore all system mode registers for the task. */ \ + "LDMFD LR, {R0-R14}^ \n\t" \ + "NOP \n\t" \ + \ + /* Restore the return address. */ \ + "LDR LR, [LR, #+60] \n\t" \ + \ + /* And return - correcting the offset in the LR to obtain the */ \ + /* correct address. */ \ + "SUBS PC, LR, #4 \n\t" \ + ); \ + ( void ) ulCriticalNesting; \ + ( void ) pxCurrentTCB; \ + } /*-----------------------------------------------------------*/ -#define portSAVE_CONTEXT() \ -{ \ -extern volatile void * volatile pxCurrentTCB; \ -extern volatile uint32_t ulCriticalNesting; \ - \ - /* Push R0 as we are going to use the register. */ \ - __asm volatile ( \ - "STMDB SP!, {R0} \n\t" \ - \ - /* Set R0 to point to the task stack pointer. */ \ - "STMDB SP,{SP}^ \n\t" \ - "NOP \n\t" \ - "SUB SP, SP, #4 \n\t" \ - "LDMIA SP!,{R0} \n\t" \ - \ - /* Push the return address onto the stack. */ \ - "STMDB R0!, {LR} \n\t" \ - \ - /* Now we have saved LR we can use it instead of R0. */ \ - "MOV LR, R0 \n\t" \ - \ - /* Pop R0 so we can save it onto the system mode stack. */ \ - "LDMIA SP!, {R0} \n\t" \ - \ - /* Push all the system mode registers onto the task stack. */ \ - "STMDB LR,{R0-LR}^ \n\t" \ - "NOP \n\t" \ - "SUB LR, LR, #60 \n\t" \ - \ - /* Push the SPSR onto the task stack. */ \ - "MRS R0, SPSR \n\t" \ - "STMDB LR!, {R0} \n\t" \ - \ - "LDR R0, =ulCriticalNesting \n\t" \ - "LDR R0, [R0] \n\t" \ - "STMDB LR!, {R0} \n\t" \ - \ - /* Store the new top of stack for the task. */ \ - "LDR R0, =pxCurrentTCB \n\t" \ - "LDR R0, [R0] \n\t" \ - "STR LR, [R0] \n\t" \ - ); \ - ( void ) ulCriticalNesting; \ - ( void ) pxCurrentTCB; \ -} - - -#define portYIELD_FROM_ISR() vTaskSwitchContext() -#define portYIELD() __asm volatile ( "SWI 0" ) +#define portSAVE_CONTEXT() \ + { \ + extern volatile void * volatile pxCurrentTCB; \ + extern volatile uint32_t ulCriticalNesting; \ + \ + /* Push R0 as we are going to use the register. */ \ + __asm volatile ( \ + "STMDB SP!, {R0} \n\t" \ + \ + /* Set R0 to point to the task stack pointer. */ \ + "STMDB SP,{SP}^ \n\t" \ + "NOP \n\t" \ + "SUB SP, SP, #4 \n\t" \ + "LDMIA SP!,{R0} \n\t" \ + \ + /* Push the return address onto the stack. */ \ + "STMDB R0!, {LR} \n\t" \ + \ + /* Now we have saved LR we can use it instead of R0. */ \ + "MOV LR, R0 \n\t" \ + \ + /* Pop R0 so we can save it onto the system mode stack. */ \ + "LDMIA SP!, {R0} \n\t" \ + \ + /* Push all the system mode registers onto the task stack. */ \ + "STMDB LR,{R0-LR}^ \n\t" \ + "NOP \n\t" \ + "SUB LR, LR, #60 \n\t" \ + \ + /* Push the SPSR onto the task stack. */ \ + "MRS R0, SPSR \n\t" \ + "STMDB LR!, {R0} \n\t" \ + \ + "LDR R0, =ulCriticalNesting \n\t" \ + "LDR R0, [R0] \n\t" \ + "STMDB LR!, {R0} \n\t" \ + \ + /* Store the new top of stack for the task. */ \ + "LDR R0, =pxCurrentTCB \n\t" \ + "LDR R0, [R0] \n\t" \ + "STR LR, [R0] \n\t" \ + ); \ + ( void ) ulCriticalNesting; \ + ( void ) pxCurrentTCB; \ + } + + +#define portYIELD_FROM_ISR() vTaskSwitchContext() +#define portYIELD() __asm volatile ( "SWI 0" ) /*-----------------------------------------------------------*/ @@ -209,42 +209,42 @@ extern volatile uint32_t ulCriticalNesting; \ #ifdef THUMB_INTERWORK - extern void vPortDisableInterruptsFromThumb( void ) __attribute__ ((naked)); - extern void vPortEnableInterruptsFromThumb( void ) __attribute__ ((naked)); + extern void vPortDisableInterruptsFromThumb( void ) __attribute__( ( naked ) ); + extern void vPortEnableInterruptsFromThumb( void ) __attribute__( ( naked ) ); #define portDISABLE_INTERRUPTS() vPortDisableInterruptsFromThumb() #define portENABLE_INTERRUPTS() vPortEnableInterruptsFromThumb() #else - #define portDISABLE_INTERRUPTS() \ - __asm volatile ( \ - "STMDB SP!, {R0} \n\t" /* Push R0. */ \ - "MRS R0, CPSR \n\t" /* Get CPSR. */ \ - "ORR R0, R0, #0xC0 \n\t" /* Disable IRQ, FIQ. */ \ - "MSR CPSR, R0 \n\t" /* Write back modified value. */ \ - "LDMIA SP!, {R0} " ) /* Pop R0. */ - - #define portENABLE_INTERRUPTS() \ - __asm volatile ( \ - "STMDB SP!, {R0} \n\t" /* Push R0. */ \ - "MRS R0, CPSR \n\t" /* Get CPSR. */ \ - "BIC R0, R0, #0xC0 \n\t" /* Enable IRQ, FIQ. */ \ - "MSR CPSR, R0 \n\t" /* Write back modified value. */ \ - "LDMIA SP!, {R0} " ) /* Pop R0. */ + #define portDISABLE_INTERRUPTS() \ + __asm volatile ( \ + "STMDB SP!, {R0} \n\t" /* Push R0. */ \ + "MRS R0, CPSR \n\t" /* Get CPSR. */ \ + "ORR R0, R0, #0xC0 \n\t" /* Disable IRQ, FIQ. */ \ + "MSR CPSR, R0 \n\t" /* Write back modified value. */ \ + "LDMIA SP!, {R0} " ) /* Pop R0. */ + + #define portENABLE_INTERRUPTS() \ + __asm volatile ( \ + "STMDB SP!, {R0} \n\t" /* Push R0. */ \ + "MRS R0, CPSR \n\t" /* Get CPSR. */ \ + "BIC R0, R0, #0xC0 \n\t" /* Enable IRQ, FIQ. */ \ + "MSR CPSR, R0 \n\t" /* Write back modified value. */ \ + "LDMIA SP!, {R0} " ) /* Pop R0. */ #endif /* THUMB_INTERWORK */ extern void vPortEnterCritical( void ); extern void vPortExitCritical( void ); -#define portENTER_CRITICAL() vPortEnterCritical(); -#define portEXIT_CRITICAL() vPortExitCritical(); +#define portENTER_CRITICAL() vPortEnterCritical(); +#define portEXIT_CRITICAL() vPortExitCritical(); /*-----------------------------------------------------------*/ /* Task function macros as described on the FreeRTOS.org WEB site. */ -#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters ) -#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters ) +#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters ) +#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters ) /* *INDENT-OFF* */ #ifdef __cplusplus diff --git a/Source/portable/GCC/ARM7_LPC2000/port.c b/Source/portable/GCC/ARM7_LPC2000/port.c index 37ad4c8f3..bcd3f6b8d 100644 --- a/Source/portable/GCC/ARM7_LPC2000/port.c +++ b/Source/portable/GCC/ARM7_LPC2000/port.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -28,12 +28,12 @@ /*----------------------------------------------------------- - * Implementation of functions defined in portable.h for the ARM7 port. - * - * Components that can be compiled to either ARM or THUMB mode are - * contained in this file. The ISR routines, which can only be compiled - * to ARM mode are contained in portISR.c. - *----------------------------------------------------------*/ +* Implementation of functions defined in portable.h for the ARM7 port. +* +* Components that can be compiled to either ARM or THUMB mode are +* contained in this file. The ISR routines, which can only be compiled +* to ARM mode are contained in portISR.c. +*----------------------------------------------------------*/ /* Standard includes. */ @@ -44,21 +44,21 @@ #include "task.h" /* Constants required to setup the task context. */ -#define portINITIAL_SPSR ( ( StackType_t ) 0x1f ) /* System mode, ARM mode, interrupts enabled. */ -#define portTHUMB_MODE_BIT ( ( StackType_t ) 0x20 ) -#define portINSTRUCTION_SIZE ( ( StackType_t ) 4 ) -#define portNO_CRITICAL_SECTION_NESTING ( ( StackType_t ) 0 ) +#define portINITIAL_SPSR ( ( StackType_t ) 0x1f ) /* System mode, ARM mode, interrupts enabled. */ +#define portTHUMB_MODE_BIT ( ( StackType_t ) 0x20 ) +#define portINSTRUCTION_SIZE ( ( StackType_t ) 4 ) +#define portNO_CRITICAL_SECTION_NESTING ( ( StackType_t ) 0 ) /* Constants required to setup the tick ISR. */ -#define portENABLE_TIMER ( ( uint8_t ) 0x01 ) -#define portPRESCALE_VALUE 0x00 -#define portINTERRUPT_ON_MATCH ( ( uint32_t ) 0x01 ) -#define portRESET_COUNT_ON_MATCH ( ( uint32_t ) 0x02 ) +#define portENABLE_TIMER ( ( uint8_t ) 0x01 ) +#define portPRESCALE_VALUE 0x00 +#define portINTERRUPT_ON_MATCH ( ( uint32_t ) 0x01 ) +#define portRESET_COUNT_ON_MATCH ( ( uint32_t ) 0x02 ) /* Constants required to setup the VIC for the tick ISR. */ -#define portTIMER_VIC_CHANNEL ( ( uint32_t ) 0x0004 ) -#define portTIMER_VIC_CHANNEL_BIT ( ( uint32_t ) 0x0010 ) -#define portTIMER_VIC_ENABLE ( ( uint32_t ) 0x0020 ) +#define portTIMER_VIC_CHANNEL ( ( uint32_t ) 0x0004 ) +#define portTIMER_VIC_CHANNEL_BIT ( ( uint32_t ) 0x0010 ) +#define portTIMER_VIC_ENABLE ( ( uint32_t ) 0x0020 ) /*-----------------------------------------------------------*/ @@ -79,61 +79,63 @@ extern void vPortISRStartFirstTask( void ); * * See header file for description. */ -StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters ) +StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, + TaskFunction_t pxCode, + void * pvParameters ) { -StackType_t *pxOriginalTOS; + StackType_t * pxOriginalTOS; pxOriginalTOS = pxTopOfStack; /* To ensure asserts in tasks.c don't fail, although in this case the assert - is not really required. */ + * is not really required. */ pxTopOfStack--; /* Setup the initial stack of the task. The stack is set exactly as - expected by the portRESTORE_CONTEXT() macro. */ + * expected by the portRESTORE_CONTEXT() macro. */ /* First on the stack is the return address - which in this case is the - start of the task. The offset is added to make the return address appear - as it would within an IRQ ISR. */ + * start of the task. The offset is added to make the return address appear + * as it would within an IRQ ISR. */ *pxTopOfStack = ( StackType_t ) pxCode + portINSTRUCTION_SIZE; pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0xaaaaaaaa; /* R14 */ + *pxTopOfStack = ( StackType_t ) 0xaaaaaaaa; /* R14 */ pxTopOfStack--; *pxTopOfStack = ( StackType_t ) pxOriginalTOS; /* Stack used when task starts goes in R13. */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x12121212; /* R12 */ + *pxTopOfStack = ( StackType_t ) 0x12121212; /* R12 */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x11111111; /* R11 */ + *pxTopOfStack = ( StackType_t ) 0x11111111; /* R11 */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x10101010; /* R10 */ + *pxTopOfStack = ( StackType_t ) 0x10101010; /* R10 */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x09090909; /* R9 */ + *pxTopOfStack = ( StackType_t ) 0x09090909; /* R9 */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x08080808; /* R8 */ + *pxTopOfStack = ( StackType_t ) 0x08080808; /* R8 */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x07070707; /* R7 */ + *pxTopOfStack = ( StackType_t ) 0x07070707; /* R7 */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x06060606; /* R6 */ + *pxTopOfStack = ( StackType_t ) 0x06060606; /* R6 */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x05050505; /* R5 */ + *pxTopOfStack = ( StackType_t ) 0x05050505; /* R5 */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x04040404; /* R4 */ + *pxTopOfStack = ( StackType_t ) 0x04040404; /* R4 */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x03030303; /* R3 */ + *pxTopOfStack = ( StackType_t ) 0x03030303; /* R3 */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x02020202; /* R2 */ + *pxTopOfStack = ( StackType_t ) 0x02020202; /* R2 */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x01010101; /* R1 */ + *pxTopOfStack = ( StackType_t ) 0x01010101; /* R1 */ pxTopOfStack--; /* When the task starts is will expect to find the function parameter in - R0. */ + * R0. */ *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */ pxTopOfStack--; /* The last thing onto the stack is the status register, which is set for - system mode, with interrupts enabled. */ + * system mode, with interrupts enabled. */ *pxTopOfStack = ( StackType_t ) portINITIAL_SPSR; if( ( ( uint32_t ) pxCode & 0x01UL ) != 0x00 ) @@ -145,9 +147,9 @@ StackType_t *pxOriginalTOS; pxTopOfStack--; /* Some optimisation levels use the stack differently to others. This - means the interrupt flags cannot always be stored on the stack and will - instead be stored in a variable, which is then saved as part of the - tasks context. */ + * means the interrupt flags cannot always be stored on the stack and will + * instead be stored in a variable, which is then saved as part of the + * tasks context. */ *pxTopOfStack = portNO_CRITICAL_SECTION_NESTING; return pxTopOfStack; @@ -157,7 +159,7 @@ StackType_t *pxOriginalTOS; BaseType_t xPortStartScheduler( void ) { /* Start the timer that generates the tick ISR. Interrupts are disabled - here already. */ + * here already. */ prvSetupTimerInterrupt(); /* Start the first task. */ @@ -171,7 +173,7 @@ BaseType_t xPortStartScheduler( void ) void vPortEndScheduler( void ) { /* It is unlikely that the ARM port will require this function as there - is nothing to return to. */ + * is nothing to return to. */ } /*-----------------------------------------------------------*/ @@ -180,18 +182,19 @@ void vPortEndScheduler( void ) */ static void prvSetupTimerInterrupt( void ) { -uint32_t ulCompareMatch; -extern void ( vTickISR )( void ); + uint32_t ulCompareMatch; + + extern void( vTickISR )( void ); /* A 1ms tick does not require the use of the timer prescale. This is - defaulted to zero but can be used if necessary. */ + * defaulted to zero but can be used if necessary. */ T0_PR = portPRESCALE_VALUE; /* Calculate the match value required for our wanted tick rate. */ ulCompareMatch = configCPU_CLOCK_HZ / configTICK_RATE_HZ; /* Protect against divide by zero. Using an if() statement still results - in a warning - hence the #if. */ + * in a warning - hence the #if. */ #if portPRESCALE_VALUE != 0 { ulCompareMatch /= ( portPRESCALE_VALUE + 1 ); @@ -207,13 +210,13 @@ extern void ( vTickISR )( void ); VICIntEnable |= portTIMER_VIC_CHANNEL_BIT; /* The ISR installed depends on whether the preemptive or cooperative - scheduler is being used. */ + * scheduler is being used. */ VICVectAddr0 = ( int32_t ) vTickISR; VICVectCntl0 = portTIMER_VIC_CHANNEL | portTIMER_VIC_ENABLE; /* Start the timer - interrupts are disabled when this function is called - so it is okay to do this here. */ + * so it is okay to do this here. */ T0_TCR = portENABLE_TIMER; } /*-----------------------------------------------------------*/ diff --git a/Source/portable/GCC/ARM7_LPC2000/portISR.c b/Source/portable/GCC/ARM7_LPC2000/portISR.c index 5510ab42d..c92c89415 100644 --- a/Source/portable/GCC/ARM7_LPC2000/portISR.c +++ b/Source/portable/GCC/ARM7_LPC2000/portISR.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -28,45 +28,45 @@ /*----------------------------------------------------------- - * Components that can be compiled to either ARM or THUMB mode are - * contained in port.c The ISR routines, which can only be compiled - * to ARM mode, are contained in this file. - *----------------------------------------------------------*/ +* Components that can be compiled to either ARM or THUMB mode are +* contained in port.c The ISR routines, which can only be compiled +* to ARM mode, are contained in this file. +*----------------------------------------------------------*/ /* - Changes from V2.5.2 - - + The critical section management functions have been changed. These no - longer modify the stack and are safe to use at all optimisation levels. - The functions are now also the same for both ARM and THUMB modes. - - Changes from V2.6.0 - - + Removed the 'static' from the definition of vNonPreemptiveTick() to - allow the demo to link when using the cooperative scheduler. - - Changes from V3.2.4 - - + The assembler statements are now included in a single asm block rather - than each line having its own asm block. -*/ + * Changes from V2.5.2 + * + + The critical section management functions have been changed. These no + + longer modify the stack and are safe to use at all optimisation levels. + + The functions are now also the same for both ARM and THUMB modes. + + + + Changes from V2.6.0 + + + + Removed the 'static' from the definition of vNonPreemptiveTick() to + + allow the demo to link when using the cooperative scheduler. + + + + Changes from V3.2.4 + + + + The assembler statements are now included in a single asm block rather + + than each line having its own asm block. + */ /* Scheduler includes. */ #include "FreeRTOS.h" /* Constants required to handle interrupts. */ -#define portTIMER_MATCH_ISR_BIT ( ( uint8_t ) 0x01 ) -#define portCLEAR_VIC_INTERRUPT ( ( uint32_t ) 0 ) +#define portTIMER_MATCH_ISR_BIT ( ( uint8_t ) 0x01 ) +#define portCLEAR_VIC_INTERRUPT ( ( uint32_t ) 0 ) /* Constants required to handle critical sections. */ -#define portNO_CRITICAL_NESTING ( ( uint32_t ) 0 ) +#define portNO_CRITICAL_NESTING ( ( uint32_t ) 0 ) volatile uint32_t ulCriticalNesting = 9999UL; /*-----------------------------------------------------------*/ /* ISR to handle manual context switches (from a call to taskYIELD()). */ -void vPortYieldProcessor( void ) __attribute__((interrupt("SWI"), naked)); +void vPortYieldProcessor( void ) __attribute__( ( interrupt( "SWI" ), naked ) ); /* * The scheduler can only be started from ARM mode, hence the inclusion of this @@ -78,7 +78,7 @@ void vPortISRStartFirstTask( void ); void vPortISRStartFirstTask( void ) { /* Simply start the scheduler. This is included here as it can only be - called from ARM mode. */ + * called from ARM mode. */ portRESTORE_CONTEXT(); } /*-----------------------------------------------------------*/ @@ -94,8 +94,8 @@ void vPortISRStartFirstTask( void ) void vPortYieldProcessor( void ) { /* Within an IRQ ISR the link register has an offset from the true return - address, but an SWI ISR does not. Add the offset manually so the same - ISR return code can be used in both cases. */ + * address, but an SWI ISR does not. Add the offset manually so the same + * ISR return code can be used in both cases. */ __asm volatile ( "ADD LR, LR, #4" ); /* Perform the context switch. First save the context of the current task. */ @@ -112,14 +112,14 @@ void vPortYieldProcessor( void ) /* * The ISR used for the scheduler tick. */ -void vTickISR( void ) __attribute__((naked)); +void vTickISR( void ) __attribute__( ( naked ) ); void vTickISR( void ) { /* Save the context of the interrupted task. */ portSAVE_CONTEXT(); /* Increment the RTOS tick count, then look for the highest priority - task that is ready to run. */ + * task that is ready to run. */ __asm volatile ( " bl xTaskIncrementTick \t\n" \ @@ -146,50 +146,50 @@ void vTickISR( void ) */ #ifdef THUMB_INTERWORK - void vPortDisableInterruptsFromThumb( void ) __attribute__ ((naked)); - void vPortEnableInterruptsFromThumb( void ) __attribute__ ((naked)); + void vPortDisableInterruptsFromThumb( void ) __attribute__( ( naked ) ); + void vPortEnableInterruptsFromThumb( void ) __attribute__( ( naked ) ); void vPortDisableInterruptsFromThumb( void ) { __asm volatile ( - "STMDB SP!, {R0} \n\t" /* Push R0. */ - "MRS R0, CPSR \n\t" /* Get CPSR. */ - "ORR R0, R0, #0xC0 \n\t" /* Disable IRQ, FIQ. */ - "MSR CPSR, R0 \n\t" /* Write back modified value. */ - "LDMIA SP!, {R0} \n\t" /* Pop R0. */ - "BX R14" ); /* Return back to thumb. */ + "STMDB SP!, {R0} \n\t" /* Push R0. */ + "MRS R0, CPSR \n\t" /* Get CPSR. */ + "ORR R0, R0, #0xC0 \n\t" /* Disable IRQ, FIQ. */ + "MSR CPSR, R0 \n\t" /* Write back modified value. */ + "LDMIA SP!, {R0} \n\t" /* Pop R0. */ + "BX R14" ); /* Return back to thumb. */ } void vPortEnableInterruptsFromThumb( void ) { __asm volatile ( - "STMDB SP!, {R0} \n\t" /* Push R0. */ - "MRS R0, CPSR \n\t" /* Get CPSR. */ - "BIC R0, R0, #0xC0 \n\t" /* Enable IRQ, FIQ. */ - "MSR CPSR, R0 \n\t" /* Write back modified value. */ - "LDMIA SP!, {R0} \n\t" /* Pop R0. */ - "BX R14" ); /* Return back to thumb. */ + "STMDB SP!, {R0} \n\t" /* Push R0. */ + "MRS R0, CPSR \n\t" /* Get CPSR. */ + "BIC R0, R0, #0xC0 \n\t" /* Enable IRQ, FIQ. */ + "MSR CPSR, R0 \n\t" /* Write back modified value. */ + "LDMIA SP!, {R0} \n\t" /* Pop R0. */ + "BX R14" ); /* Return back to thumb. */ } #endif /* THUMB_INTERWORK */ /* The code generated by the GCC compiler uses the stack in different ways at -different optimisation levels. The interrupt flags can therefore not always -be saved to the stack. Instead the critical section nesting level is stored -in a variable, which is then saved as part of the stack context. */ + * different optimisation levels. The interrupt flags can therefore not always + * be saved to the stack. Instead the critical section nesting level is stored + * in a variable, which is then saved as part of the stack context. */ void vPortEnterCritical( void ) { /* Disable interrupts as per portDISABLE_INTERRUPTS(); */ __asm volatile ( - "STMDB SP!, {R0} \n\t" /* Push R0. */ - "MRS R0, CPSR \n\t" /* Get CPSR. */ - "ORR R0, R0, #0xC0 \n\t" /* Disable IRQ, FIQ. */ - "MSR CPSR, R0 \n\t" /* Write back modified value. */ - "LDMIA SP!, {R0}" ); /* Pop R0. */ - - /* Now interrupts are disabled ulCriticalNesting can be accessed - directly. Increment ulCriticalNesting to keep a count of how many times - portENTER_CRITICAL() has been called. */ + "STMDB SP!, {R0} \n\t" /* Push R0. */ + "MRS R0, CPSR \n\t" /* Get CPSR. */ + "ORR R0, R0, #0xC0 \n\t" /* Disable IRQ, FIQ. */ + "MSR CPSR, R0 \n\t" /* Write back modified value. */ + "LDMIA SP!, {R0}" ); /* Pop R0. */ + + /* Now that interrupts are disabled, ulCriticalNesting can be accessed + * directly. Increment ulCriticalNesting to keep a count of how many times + * portENTER_CRITICAL() has been called. */ ulCriticalNesting++; } @@ -201,16 +201,16 @@ void vPortExitCritical( void ) ulCriticalNesting--; /* If the nesting level has reached zero then interrupts should be - re-enabled. */ + * re-enabled. */ if( ulCriticalNesting == portNO_CRITICAL_NESTING ) { /* Enable interrupts as per portEXIT_CRITICAL(). */ __asm volatile ( - "STMDB SP!, {R0} \n\t" /* Push R0. */ - "MRS R0, CPSR \n\t" /* Get CPSR. */ - "BIC R0, R0, #0xC0 \n\t" /* Enable IRQ, FIQ. */ - "MSR CPSR, R0 \n\t" /* Write back modified value. */ - "LDMIA SP!, {R0}" ); /* Pop R0. */ + "STMDB SP!, {R0} \n\t" /* Push R0. */ + "MRS R0, CPSR \n\t" /* Get CPSR. */ + "BIC R0, R0, #0xC0 \n\t" /* Enable IRQ, FIQ. */ + "MSR CPSR, R0 \n\t" /* Write back modified value. */ + "LDMIA SP!, {R0}" ); /* Pop R0. */ } } } diff --git a/Source/portable/GCC/ARM7_LPC2000/portmacro.h b/Source/portable/GCC/ARM7_LPC2000/portmacro.h index fb074355b..51ee1b195 100644 --- a/Source/portable/GCC/ARM7_LPC2000/portmacro.h +++ b/Source/portable/GCC/ARM7_LPC2000/portmacro.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -46,34 +46,34 @@ */ /* Type definitions. */ -#define portCHAR char -#define portFLOAT float -#define portDOUBLE double -#define portLONG long -#define portSHORT short -#define portSTACK_TYPE uint32_t -#define portBASE_TYPE portLONG - -typedef portSTACK_TYPE StackType_t; -typedef long BaseType_t; -typedef unsigned long UBaseType_t; - -#if( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS ) - typedef uint16_t TickType_t; - #define portMAX_DELAY ( TickType_t ) 0xffff +#define portCHAR char +#define portFLOAT float +#define portDOUBLE double +#define portLONG long +#define portSHORT short +#define portSTACK_TYPE uint32_t +#define portBASE_TYPE portLONG + +typedef portSTACK_TYPE StackType_t; +typedef long BaseType_t; +typedef unsigned long UBaseType_t; + +#if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS ) + typedef uint16_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffff #elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS ) - typedef uint32_t TickType_t; - #define portMAX_DELAY ( TickType_t ) ( 0xFFFFFFFFUL ) + typedef uint32_t TickType_t; + #define portMAX_DELAY ( TickType_t ) ( 0xFFFFFFFFUL ) #else #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width. #endif /*-----------------------------------------------------------*/ /* Architecture specifics. */ -#define portSTACK_GROWTH ( -1 ) -#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) -#define portBYTE_ALIGNMENT 8 -#define portNOP() __asm volatile ( "NOP" ); +#define portSTACK_GROWTH ( -1 ) +#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) +#define portBYTE_ALIGNMENT 8 +#define portNOP() __asm volatile ( "NOP" ); /*-----------------------------------------------------------*/ @@ -86,92 +86,92 @@ typedef unsigned long UBaseType_t; * THUMB mode code will result in a compile time error. */ -#define portRESTORE_CONTEXT() \ -{ \ -extern volatile void * volatile pxCurrentTCB; \ -extern volatile uint32_t ulCriticalNesting; \ - \ - /* Set the LR to the task stack. */ \ - __asm volatile ( \ - "LDR R0, =pxCurrentTCB \n\t" \ - "LDR R0, [R0] \n\t" \ - "LDR LR, [R0] \n\t" \ - \ - /* The critical nesting depth is the first item on the stack. */ \ - /* Load it into the ulCriticalNesting variable. */ \ - "LDR R0, =ulCriticalNesting \n\t" \ - "LDMFD LR!, {R1} \n\t" \ - "STR R1, [R0] \n\t" \ - \ - /* Get the SPSR from the stack. */ \ - "LDMFD LR!, {R0} \n\t" \ - "MSR SPSR, R0 \n\t" \ - \ - /* Restore all system mode registers for the task. */ \ - "LDMFD LR, {R0-R14}^ \n\t" \ - "NOP \n\t" \ - \ - /* Restore the return address. */ \ - "LDR LR, [LR, #+60] \n\t" \ - \ - /* And return - correcting the offset in the LR to obtain the */ \ - /* correct address. */ \ - "SUBS PC, LR, #4 \n\t" \ - ); \ - ( void ) ulCriticalNesting; \ - ( void ) pxCurrentTCB; \ -} +#define portRESTORE_CONTEXT() \ + { \ + extern volatile void * volatile pxCurrentTCB; \ + extern volatile uint32_t ulCriticalNesting; \ + \ + /* Set the LR to the task stack. */ \ + __asm volatile ( \ + "LDR R0, =pxCurrentTCB \n\t" \ + "LDR R0, [R0] \n\t" \ + "LDR LR, [R0] \n\t" \ + \ + /* The critical nesting depth is the first item on the stack. */ \ + /* Load it into the ulCriticalNesting variable. */ \ + "LDR R0, =ulCriticalNesting \n\t" \ + "LDMFD LR!, {R1} \n\t" \ + "STR R1, [R0] \n\t" \ + \ + /* Get the SPSR from the stack. */ \ + "LDMFD LR!, {R0} \n\t" \ + "MSR SPSR, R0 \n\t" \ + \ + /* Restore all system mode registers for the task. */ \ + "LDMFD LR, {R0-R14}^ \n\t" \ + "NOP \n\t" \ + \ + /* Restore the return address. */ \ + "LDR LR, [LR, #+60] \n\t" \ + \ + /* And return - correcting the offset in the LR to obtain the */ \ + /* correct address. */ \ + "SUBS PC, LR, #4 \n\t" \ + ); \ + ( void ) ulCriticalNesting; \ + ( void ) pxCurrentTCB; \ + } /*-----------------------------------------------------------*/ -#define portSAVE_CONTEXT() \ -{ \ -extern volatile void * volatile pxCurrentTCB; \ -extern volatile uint32_t ulCriticalNesting; \ - \ - /* Push R0 as we are going to use the register. */ \ - __asm volatile ( \ - "STMDB SP!, {R0} \n\t" \ - \ - /* Set R0 to point to the task stack pointer. */ \ - "STMDB SP,{SP}^ \n\t" \ - "NOP \n\t" \ - "SUB SP, SP, #4 \n\t" \ - "LDMIA SP!,{R0} \n\t" \ - \ - /* Push the return address onto the stack. */ \ - "STMDB R0!, {LR} \n\t" \ - \ - /* Now we have saved LR we can use it instead of R0. */ \ - "MOV LR, R0 \n\t" \ - \ - /* Pop R0 so we can save it onto the system mode stack. */ \ - "LDMIA SP!, {R0} \n\t" \ - \ - /* Push all the system mode registers onto the task stack. */ \ - "STMDB LR,{R0-LR}^ \n\t" \ - "NOP \n\t" \ - "SUB LR, LR, #60 \n\t" \ - \ - /* Push the SPSR onto the task stack. */ \ - "MRS R0, SPSR \n\t" \ - "STMDB LR!, {R0} \n\t" \ - \ - "LDR R0, =ulCriticalNesting \n\t" \ - "LDR R0, [R0] \n\t" \ - "STMDB LR!, {R0} \n\t" \ - \ - /* Store the new top of stack for the task. */ \ - "LDR R0, =pxCurrentTCB \n\t" \ - "LDR R0, [R0] \n\t" \ - "STR LR, [R0] \n\t" \ - ); \ - ( void ) ulCriticalNesting; \ - ( void ) pxCurrentTCB; \ -} +#define portSAVE_CONTEXT() \ + { \ + extern volatile void * volatile pxCurrentTCB; \ + extern volatile uint32_t ulCriticalNesting; \ + \ + /* Push R0 as we are going to use the register. */ \ + __asm volatile ( \ + "STMDB SP!, {R0} \n\t" \ + \ + /* Set R0 to point to the task stack pointer. */ \ + "STMDB SP,{SP}^ \n\t" \ + "NOP \n\t" \ + "SUB SP, SP, #4 \n\t" \ + "LDMIA SP!,{R0} \n\t" \ + \ + /* Push the return address onto the stack. */ \ + "STMDB R0!, {LR} \n\t" \ + \ + /* Now we have saved LR we can use it instead of R0. */ \ + "MOV LR, R0 \n\t" \ + \ + /* Pop R0 so we can save it onto the system mode stack. */ \ + "LDMIA SP!, {R0} \n\t" \ + \ + /* Push all the system mode registers onto the task stack. */ \ + "STMDB LR,{R0-LR}^ \n\t" \ + "NOP \n\t" \ + "SUB LR, LR, #60 \n\t" \ + \ + /* Push the SPSR onto the task stack. */ \ + "MRS R0, SPSR \n\t" \ + "STMDB LR!, {R0} \n\t" \ + \ + "LDR R0, =ulCriticalNesting \n\t" \ + "LDR R0, [R0] \n\t" \ + "STMDB LR!, {R0} \n\t" \ + \ + /* Store the new top of stack for the task. */ \ + "LDR R0, =pxCurrentTCB \n\t" \ + "LDR R0, [R0] \n\t" \ + "STR LR, [R0] \n\t" \ + ); \ + ( void ) ulCriticalNesting; \ + ( void ) pxCurrentTCB; \ + } extern void vTaskSwitchContext( void ); -#define portYIELD_FROM_ISR() vTaskSwitchContext() -#define portYIELD() __asm volatile ( "SWI 0" ) +#define portYIELD_FROM_ISR() vTaskSwitchContext() +#define portYIELD() __asm volatile ( "SWI 0" ) /*-----------------------------------------------------------*/ @@ -186,42 +186,42 @@ extern void vTaskSwitchContext( void ); #ifdef THUMB_INTERWORK - extern void vPortDisableInterruptsFromThumb( void ) __attribute__ ((naked)); - extern void vPortEnableInterruptsFromThumb( void ) __attribute__ ((naked)); + extern void vPortDisableInterruptsFromThumb( void ) __attribute__( ( naked ) ); + extern void vPortEnableInterruptsFromThumb( void ) __attribute__( ( naked ) ); #define portDISABLE_INTERRUPTS() vPortDisableInterruptsFromThumb() #define portENABLE_INTERRUPTS() vPortEnableInterruptsFromThumb() #else - #define portDISABLE_INTERRUPTS() \ - __asm volatile ( \ - "STMDB SP!, {R0} \n\t" /* Push R0. */ \ - "MRS R0, CPSR \n\t" /* Get CPSR. */ \ - "ORR R0, R0, #0xC0 \n\t" /* Disable IRQ, FIQ. */ \ - "MSR CPSR, R0 \n\t" /* Write back modified value. */ \ - "LDMIA SP!, {R0} " ) /* Pop R0. */ - - #define portENABLE_INTERRUPTS() \ - __asm volatile ( \ - "STMDB SP!, {R0} \n\t" /* Push R0. */ \ - "MRS R0, CPSR \n\t" /* Get CPSR. */ \ - "BIC R0, R0, #0xC0 \n\t" /* Enable IRQ, FIQ. */ \ - "MSR CPSR, R0 \n\t" /* Write back modified value. */ \ - "LDMIA SP!, {R0} " ) /* Pop R0. */ + #define portDISABLE_INTERRUPTS() \ + __asm volatile ( \ + "STMDB SP!, {R0} \n\t" /* Push R0. */ \ + "MRS R0, CPSR \n\t" /* Get CPSR. */ \ + "ORR R0, R0, #0xC0 \n\t" /* Disable IRQ, FIQ. */ \ + "MSR CPSR, R0 \n\t" /* Write back modified value. */ \ + "LDMIA SP!, {R0} " ) /* Pop R0. */ + + #define portENABLE_INTERRUPTS() \ + __asm volatile ( \ + "STMDB SP!, {R0} \n\t" /* Push R0. */ \ + "MRS R0, CPSR \n\t" /* Get CPSR. */ \ + "BIC R0, R0, #0xC0 \n\t" /* Enable IRQ, FIQ. */ \ + "MSR CPSR, R0 \n\t" /* Write back modified value. */ \ + "LDMIA SP!, {R0} " ) /* Pop R0. */ #endif /* THUMB_INTERWORK */ extern void vPortEnterCritical( void ); extern void vPortExitCritical( void ); -#define portENTER_CRITICAL() vPortEnterCritical(); -#define portEXIT_CRITICAL() vPortExitCritical(); +#define portENTER_CRITICAL() vPortEnterCritical(); +#define portEXIT_CRITICAL() vPortExitCritical(); /*-----------------------------------------------------------*/ /* Task function macros as described on the FreeRTOS.org WEB site. */ -#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters ) -#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters ) +#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters ) +#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters ) /* *INDENT-OFF* */ #ifdef __cplusplus diff --git a/Source/portable/GCC/ARM7_LPC23xx/port.c b/Source/portable/GCC/ARM7_LPC23xx/port.c index 2e293dcd3..36424aad4 100644 --- a/Source/portable/GCC/ARM7_LPC23xx/port.c +++ b/Source/portable/GCC/ARM7_LPC23xx/port.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -28,12 +28,12 @@ /*----------------------------------------------------------- - * Implementation of functions defined in portable.h for the ARM7 port. - * - * Components that can be compiled to either ARM or THUMB mode are - * contained in this file. The ISR routines, which can only be compiled - * to ARM mode are contained in portISR.c. - *----------------------------------------------------------*/ +* Implementation of functions defined in portable.h for the ARM7 port. +* +* Components that can be compiled to either ARM or THUMB mode are +* contained in this file. The ISR routines, which can only be compiled +* to ARM mode are contained in portISR.c. +*----------------------------------------------------------*/ /* Standard includes. */ @@ -44,21 +44,21 @@ #include "task.h" /* Constants required to setup the task context. */ -#define portINITIAL_SPSR ( ( StackType_t ) 0x1f ) /* System mode, ARM mode, interrupts enabled. */ -#define portTHUMB_MODE_BIT ( ( StackType_t ) 0x20 ) -#define portINSTRUCTION_SIZE ( ( StackType_t ) 4 ) -#define portNO_CRITICAL_SECTION_NESTING ( ( StackType_t ) 0 ) +#define portINITIAL_SPSR ( ( StackType_t ) 0x1f ) /* System mode, ARM mode, interrupts enabled. */ +#define portTHUMB_MODE_BIT ( ( StackType_t ) 0x20 ) +#define portINSTRUCTION_SIZE ( ( StackType_t ) 4 ) +#define portNO_CRITICAL_SECTION_NESTING ( ( StackType_t ) 0 ) /* Constants required to setup the tick ISR. */ -#define portENABLE_TIMER ( ( uint8_t ) 0x01 ) -#define portPRESCALE_VALUE 0x00 -#define portINTERRUPT_ON_MATCH ( ( uint32_t ) 0x01 ) -#define portRESET_COUNT_ON_MATCH ( ( uint32_t ) 0x02 ) +#define portENABLE_TIMER ( ( uint8_t ) 0x01 ) +#define portPRESCALE_VALUE 0x00 +#define portINTERRUPT_ON_MATCH ( ( uint32_t ) 0x01 ) +#define portRESET_COUNT_ON_MATCH ( ( uint32_t ) 0x02 ) /* Constants required to setup the VIC for the tick ISR. */ -#define portTIMER_VIC_CHANNEL ( ( uint32_t ) 0x0004 ) -#define portTIMER_VIC_CHANNEL_BIT ( ( uint32_t ) 0x0010 ) -#define portTIMER_VIC_ENABLE ( ( uint32_t ) 0x0020 ) +#define portTIMER_VIC_CHANNEL ( ( uint32_t ) 0x0004 ) +#define portTIMER_VIC_CHANNEL_BIT ( ( uint32_t ) 0x0010 ) +#define portTIMER_VIC_ENABLE ( ( uint32_t ) 0x0020 ) /*-----------------------------------------------------------*/ @@ -79,61 +79,63 @@ extern void vPortISRStartFirstTask( void ); * * See header file for description. */ -StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters ) +StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, + TaskFunction_t pxCode, + void * pvParameters ) { -StackType_t *pxOriginalTOS; + StackType_t * pxOriginalTOS; pxOriginalTOS = pxTopOfStack; /* To ensure asserts in tasks.c don't fail, although in this case the assert - is not really required. */ + * is not really required. */ pxTopOfStack--; /* Setup the initial stack of the task. The stack is set exactly as - expected by the portRESTORE_CONTEXT() macro. */ + * expected by the portRESTORE_CONTEXT() macro. */ /* First on the stack is the return address - which in this case is the - start of the task. The offset is added to make the return address appear - as it would within an IRQ ISR. */ + * start of the task. The offset is added to make the return address appear + * as it would within an IRQ ISR. */ *pxTopOfStack = ( StackType_t ) pxCode + portINSTRUCTION_SIZE; pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x00000000; /* R14 */ + *pxTopOfStack = ( StackType_t ) 0x00000000; /* R14 */ pxTopOfStack--; *pxTopOfStack = ( StackType_t ) pxOriginalTOS; /* Stack used when task starts goes in R13. */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x12121212; /* R12 */ + *pxTopOfStack = ( StackType_t ) 0x12121212; /* R12 */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x11111111; /* R11 */ + *pxTopOfStack = ( StackType_t ) 0x11111111; /* R11 */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x10101010; /* R10 */ + *pxTopOfStack = ( StackType_t ) 0x10101010; /* R10 */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x09090909; /* R9 */ + *pxTopOfStack = ( StackType_t ) 0x09090909; /* R9 */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x08080808; /* R8 */ + *pxTopOfStack = ( StackType_t ) 0x08080808; /* R8 */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x07070707; /* R7 */ + *pxTopOfStack = ( StackType_t ) 0x07070707; /* R7 */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x06060606; /* R6 */ + *pxTopOfStack = ( StackType_t ) 0x06060606; /* R6 */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x05050505; /* R5 */ + *pxTopOfStack = ( StackType_t ) 0x05050505; /* R5 */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x04040404; /* R4 */ + *pxTopOfStack = ( StackType_t ) 0x04040404; /* R4 */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x03030303; /* R3 */ + *pxTopOfStack = ( StackType_t ) 0x03030303; /* R3 */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x02020202; /* R2 */ + *pxTopOfStack = ( StackType_t ) 0x02020202; /* R2 */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x01010101; /* R1 */ + *pxTopOfStack = ( StackType_t ) 0x01010101; /* R1 */ pxTopOfStack--; /* When the task starts is will expect to find the function parameter in - R0. */ + * R0. */ *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */ pxTopOfStack--; /* The last thing onto the stack is the status register, which is set for - system mode, with interrupts enabled. */ + * system mode, with interrupts enabled. */ *pxTopOfStack = ( StackType_t ) portINITIAL_SPSR; if( ( ( uint32_t ) pxCode & 0x01UL ) != 0x00 ) @@ -145,9 +147,9 @@ StackType_t *pxOriginalTOS; pxTopOfStack--; /* Some optimisation levels use the stack differently to others. This - means the interrupt flags cannot always be stored on the stack and will - instead be stored in a variable, which is then saved as part of the - tasks context. */ + * means the interrupt flags cannot always be stored on the stack and will + * instead be stored in a variable, which is then saved as part of the + * tasks context. */ *pxTopOfStack = portNO_CRITICAL_SECTION_NESTING; return pxTopOfStack; @@ -157,7 +159,7 @@ StackType_t *pxOriginalTOS; BaseType_t xPortStartScheduler( void ) { /* Start the timer that generates the tick ISR. Interrupts are disabled - here already. */ + * here already. */ prvSetupTimerInterrupt(); /* Start the first task. */ @@ -171,7 +173,7 @@ BaseType_t xPortStartScheduler( void ) void vPortEndScheduler( void ) { /* It is unlikely that the ARM port will require this function as there - is nothing to return to. */ + * is nothing to return to. */ } /*-----------------------------------------------------------*/ @@ -180,21 +182,21 @@ void vPortEndScheduler( void ) */ static void prvSetupTimerInterrupt( void ) { -uint32_t ulCompareMatch; + uint32_t ulCompareMatch; - PCLKSEL0 = (PCLKSEL0 & (~(0x3<<2))) | (0x01 << 2); - T0TCR = 2; /* Stop and reset the timer */ - T0CTCR = 0; /* Timer mode */ + PCLKSEL0 = ( PCLKSEL0 & ( ~( 0x3 << 2 ) ) ) | ( 0x01 << 2 ); + T0TCR = 2; /* Stop and reset the timer */ + T0CTCR = 0; /* Timer mode */ /* A 1ms tick does not require the use of the timer prescale. This is - defaulted to zero but can be used if necessary. */ + * defaulted to zero but can be used if necessary. */ T0PR = portPRESCALE_VALUE; /* Calculate the match value required for our wanted tick rate. */ ulCompareMatch = configCPU_CLOCK_HZ / configTICK_RATE_HZ; /* Protect against divide by zero. Using an if() statement still results - in a warning - hence the #if. */ + * in a warning - hence the #if. */ #if portPRESCALE_VALUE != 0 { ulCompareMatch /= ( portPRESCALE_VALUE + 1 ); @@ -203,21 +205,21 @@ uint32_t ulCompareMatch; T0MR1 = ulCompareMatch; /* Generate tick with timer 0 compare match. */ - T0MCR = (3 << 3); /* Reset timer on match and generate interrupt */ + T0MCR = ( 3 << 3 ); /* Reset timer on match and generate interrupt */ /* Setup the VIC for the timer. */ VICIntEnable = 0x00000010; /* The ISR installed depends on whether the preemptive or cooperative - scheduler is being used. */ + * scheduler is being used. */ #if configUSE_PREEMPTION == 1 { - extern void ( vPreemptiveTick )( void ); + extern void( vPreemptiveTick )( void ); VICVectAddr4 = ( int32_t ) vPreemptiveTick; } #else { - extern void ( vNonPreemptiveTick )( void ); + extern void( vNonPreemptiveTick )( void ); VICVectAddr4 = ( int32_t ) vNonPreemptiveTick; } #endif @@ -225,7 +227,7 @@ uint32_t ulCompareMatch; VICVectCntl4 = 1; /* Start the timer - interrupts are disabled when this function is called - so it is okay to do this here. */ + * so it is okay to do this here. */ T0TCR = portENABLE_TIMER; } /*-----------------------------------------------------------*/ diff --git a/Source/portable/GCC/ARM7_LPC23xx/portISR.c b/Source/portable/GCC/ARM7_LPC23xx/portISR.c index 01084f7bf..e43cb410a 100644 --- a/Source/portable/GCC/ARM7_LPC23xx/portISR.c +++ b/Source/portable/GCC/ARM7_LPC23xx/portISR.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -28,27 +28,27 @@ /*----------------------------------------------------------- - * Components that can be compiled to either ARM or THUMB mode are - * contained in port.c The ISR routines, which can only be compiled - * to ARM mode, are contained in this file. - *----------------------------------------------------------*/ +* Components that can be compiled to either ARM or THUMB mode are +* contained in port.c The ISR routines, which can only be compiled +* to ARM mode, are contained in this file. +*----------------------------------------------------------*/ /* Scheduler includes. */ #include "FreeRTOS.h" #include "task.h" /* Constants required to handle interrupts. */ -#define portTIMER_MATCH_ISR_BIT ( ( uint8_t ) 0x01 ) -#define portCLEAR_VIC_INTERRUPT ( ( uint32_t ) 0 ) +#define portTIMER_MATCH_ISR_BIT ( ( uint8_t ) 0x01 ) +#define portCLEAR_VIC_INTERRUPT ( ( uint32_t ) 0 ) /* Constants required to handle critical sections. */ -#define portNO_CRITICAL_NESTING ( ( uint32_t ) 0 ) +#define portNO_CRITICAL_NESTING ( ( uint32_t ) 0 ) volatile uint32_t ulCriticalNesting = 9999UL; /*-----------------------------------------------------------*/ /* ISR to handle manual context switches (from a call to taskYIELD()). */ -void vPortYieldProcessor( void ) __attribute__((interrupt("SWI"), naked)); +void vPortYieldProcessor( void ) __attribute__( ( interrupt( "SWI" ), naked ) ); /* * The scheduler can only be started from ARM mode, hence the inclusion of this @@ -60,7 +60,7 @@ void vPortISRStartFirstTask( void ); void vPortISRStartFirstTask( void ) { /* Simply start the scheduler. This is included here as it can only be - called from ARM mode. */ + * called from ARM mode. */ portRESTORE_CONTEXT(); } /*-----------------------------------------------------------*/ @@ -76,15 +76,15 @@ void vPortISRStartFirstTask( void ) void vPortYieldProcessor( void ) { /* Within an IRQ ISR the link register has an offset from the true return - address, but an SWI ISR does not. Add the offset manually so the same - ISR return code can be used in both cases. */ + * address, but an SWI ISR does not. Add the offset manually so the same + * ISR return code can be used in both cases. */ __asm volatile ( "ADD LR, LR, #4" ); /* Perform the context switch. First save the context of the current task. */ portSAVE_CONTEXT(); /* Find the highest priority task that is ready to run. */ - __asm volatile( "bl vTaskSwitchContext" ); + __asm volatile ( "bl vTaskSwitchContext" ); /* Restore the context of the new task. */ portRESTORE_CONTEXT(); @@ -99,9 +99,9 @@ void vPortYieldProcessor( void ) #if configUSE_PREEMPTION == 0 - /* The cooperative scheduler requires a normal IRQ service routine to - simply increment the system tick. */ - void vNonPreemptiveTick( void ) __attribute__ ((interrupt ("IRQ"))); +/* The cooperative scheduler requires a normal IRQ service routine to + * simply increment the system tick. */ + void vNonPreemptiveTick( void ) __attribute__( ( interrupt( "IRQ" ) ) ); void vNonPreemptiveTick( void ) { xTaskIncrementTick(); @@ -109,18 +109,18 @@ void vPortYieldProcessor( void ) VICVectAddr = portCLEAR_VIC_INTERRUPT; } -#else +#else /* if configUSE_PREEMPTION == 0 */ - /* The preemptive scheduler is defined as "naked" as the full context is - saved on entry as part of the context switch. */ - void vPreemptiveTick( void ) __attribute__((naked)); +/* The preemptive scheduler is defined as "naked" as the full context is + * saved on entry as part of the context switch. */ + void vPreemptiveTick( void ) __attribute__( ( naked ) ); void vPreemptiveTick( void ) { /* Save the context of the interrupted task. */ portSAVE_CONTEXT(); /* Increment the RTOS tick count, then look for the highest priority - task that is ready to run. */ + * task that is ready to run. */ __asm volatile ( " bl xTaskIncrementTick \t\n" \ @@ -138,7 +138,7 @@ void vPortYieldProcessor( void ) portRESTORE_CONTEXT(); } -#endif +#endif /* if configUSE_PREEMPTION == 0 */ /*-----------------------------------------------------------*/ /* @@ -149,50 +149,50 @@ void vPortYieldProcessor( void ) */ #ifdef THUMB_INTERWORK - void vPortDisableInterruptsFromThumb( void ) __attribute__ ((naked)); - void vPortEnableInterruptsFromThumb( void ) __attribute__ ((naked)); + void vPortDisableInterruptsFromThumb( void ) __attribute__( ( naked ) ); + void vPortEnableInterruptsFromThumb( void ) __attribute__( ( naked ) ); void vPortDisableInterruptsFromThumb( void ) { __asm volatile ( - "STMDB SP!, {R0} \n\t" /* Push R0. */ - "MRS R0, CPSR \n\t" /* Get CPSR. */ - "ORR R0, R0, #0xC0 \n\t" /* Disable IRQ, FIQ. */ - "MSR CPSR, R0 \n\t" /* Write back modified value. */ - "LDMIA SP!, {R0} \n\t" /* Pop R0. */ - "BX R14" ); /* Return back to thumb. */ + "STMDB SP!, {R0} \n\t" /* Push R0. */ + "MRS R0, CPSR \n\t" /* Get CPSR. */ + "ORR R0, R0, #0xC0 \n\t" /* Disable IRQ, FIQ. */ + "MSR CPSR, R0 \n\t" /* Write back modified value. */ + "LDMIA SP!, {R0} \n\t" /* Pop R0. */ + "BX R14" ); /* Return back to thumb. */ } void vPortEnableInterruptsFromThumb( void ) { __asm volatile ( - "STMDB SP!, {R0} \n\t" /* Push R0. */ - "MRS R0, CPSR \n\t" /* Get CPSR. */ - "BIC R0, R0, #0xC0 \n\t" /* Enable IRQ, FIQ. */ - "MSR CPSR, R0 \n\t" /* Write back modified value. */ - "LDMIA SP!, {R0} \n\t" /* Pop R0. */ - "BX R14" ); /* Return back to thumb. */ + "STMDB SP!, {R0} \n\t" /* Push R0. */ + "MRS R0, CPSR \n\t" /* Get CPSR. */ + "BIC R0, R0, #0xC0 \n\t" /* Enable IRQ, FIQ. */ + "MSR CPSR, R0 \n\t" /* Write back modified value. */ + "LDMIA SP!, {R0} \n\t" /* Pop R0. */ + "BX R14" ); /* Return back to thumb. */ } #endif /* THUMB_INTERWORK */ /* The code generated by the GCC compiler uses the stack in different ways at -different optimisation levels. The interrupt flags can therefore not always -be saved to the stack. Instead the critical section nesting level is stored -in a variable, which is then saved as part of the stack context. */ + * different optimisation levels. The interrupt flags can therefore not always + * be saved to the stack. Instead the critical section nesting level is stored + * in a variable, which is then saved as part of the stack context. */ void vPortEnterCritical( void ) { /* Disable interrupts as per portDISABLE_INTERRUPTS(); */ __asm volatile ( - "STMDB SP!, {R0} \n\t" /* Push R0. */ - "MRS R0, CPSR \n\t" /* Get CPSR. */ - "ORR R0, R0, #0xC0 \n\t" /* Disable IRQ, FIQ. */ - "MSR CPSR, R0 \n\t" /* Write back modified value. */ - "LDMIA SP!, {R0}" ); /* Pop R0. */ - - /* Now interrupts are disabled ulCriticalNesting can be accessed - directly. Increment ulCriticalNesting to keep a count of how many times - portENTER_CRITICAL() has been called. */ + "STMDB SP!, {R0} \n\t" /* Push R0. */ + "MRS R0, CPSR \n\t" /* Get CPSR. */ + "ORR R0, R0, #0xC0 \n\t" /* Disable IRQ, FIQ. */ + "MSR CPSR, R0 \n\t" /* Write back modified value. */ + "LDMIA SP!, {R0}" ); /* Pop R0. */ + + /* Now that interrupts are disabled, ulCriticalNesting can be accessed + * directly. Increment ulCriticalNesting to keep a count of how many times + * portENTER_CRITICAL() has been called. */ ulCriticalNesting++; } @@ -204,16 +204,16 @@ void vPortExitCritical( void ) ulCriticalNesting--; /* If the nesting level has reached zero then interrupts should be - re-enabled. */ + * re-enabled. */ if( ulCriticalNesting == portNO_CRITICAL_NESTING ) { /* Enable interrupts as per portEXIT_CRITICAL(). */ __asm volatile ( - "STMDB SP!, {R0} \n\t" /* Push R0. */ - "MRS R0, CPSR \n\t" /* Get CPSR. */ - "BIC R0, R0, #0xC0 \n\t" /* Enable IRQ, FIQ. */ - "MSR CPSR, R0 \n\t" /* Write back modified value. */ - "LDMIA SP!, {R0}" ); /* Pop R0. */ + "STMDB SP!, {R0} \n\t" /* Push R0. */ + "MRS R0, CPSR \n\t" /* Get CPSR. */ + "BIC R0, R0, #0xC0 \n\t" /* Enable IRQ, FIQ. */ + "MSR CPSR, R0 \n\t" /* Write back modified value. */ + "LDMIA SP!, {R0}" ); /* Pop R0. */ } } } diff --git a/Source/portable/GCC/ARM7_LPC23xx/portmacro.h b/Source/portable/GCC/ARM7_LPC23xx/portmacro.h index 75bbe480c..2c1f8ae73 100644 --- a/Source/portable/GCC/ARM7_LPC23xx/portmacro.h +++ b/Source/portable/GCC/ARM7_LPC23xx/portmacro.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -27,27 +27,27 @@ */ /* - Changes from V3.2.3 - - + Modified portENTER_SWITCHING_ISR() to allow use with GCC V4.0.1. - - Changes from V3.2.4 - - + Removed the use of the %0 parameter within the assembler macros and - replaced them with hard coded registers. This will ensure the - assembler does not select the link register as the temp register as - was occasionally happening previously. - - + The assembler statements are now included in a single asm block rather - than each line having its own asm block. - - Changes from V4.5.0 - - + Removed the portENTER_SWITCHING_ISR() and portEXIT_SWITCHING_ISR() macros - and replaced them with portYIELD_FROM_ISR() macro. Application code - should now make use of the portSAVE_CONTEXT() and portRESTORE_CONTEXT() - macros as per the V4.5.1 demo code. -*/ + * Changes from V3.2.3 + * + + Modified portENTER_SWITCHING_ISR() to allow use with GCC V4.0.1. + + + + Changes from V3.2.4 + + + + Removed the use of the %0 parameter within the assembler macros and + + replaced them with hard coded registers. This will ensure the + + assembler does not select the link register as the temp register as + + was occasionally happening previously. + + + + The assembler statements are now included in a single asm block rather + + than each line having its own asm block. + + + + Changes from V4.5.0 + + + + Removed the portENTER_SWITCHING_ISR() and portEXIT_SWITCHING_ISR() macros + + and replaced them with portYIELD_FROM_ISR() macro. Application code + + should now make use of the portSAVE_CONTEXT() and portRESTORE_CONTEXT() + + macros as per the V4.5.1 demo code. + */ #ifndef PORTMACRO_H #define PORTMACRO_H @@ -69,34 +69,34 @@ */ /* Type definitions. */ -#define portCHAR char -#define portFLOAT float -#define portDOUBLE double -#define portLONG long -#define portSHORT short -#define portSTACK_TYPE uint32_t -#define portBASE_TYPE portLONG - -typedef portSTACK_TYPE StackType_t; -typedef long BaseType_t; -typedef unsigned long UBaseType_t; - -#if( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS ) - typedef uint16_t TickType_t; - #define portMAX_DELAY ( TickType_t ) 0xffff +#define portCHAR char +#define portFLOAT float +#define portDOUBLE double +#define portLONG long +#define portSHORT short +#define portSTACK_TYPE uint32_t +#define portBASE_TYPE portLONG + +typedef portSTACK_TYPE StackType_t; +typedef long BaseType_t; +typedef unsigned long UBaseType_t; + +#if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS ) + typedef uint16_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffff #elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS ) - typedef uint32_t TickType_t; - #define portMAX_DELAY ( TickType_t ) ( 0xFFFFFFFFUL ) + typedef uint32_t TickType_t; + #define portMAX_DELAY ( TickType_t ) ( 0xFFFFFFFFUL ) #else #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width. #endif /*-----------------------------------------------------------*/ /* Architecture specifics. */ -#define portSTACK_GROWTH ( -1 ) -#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) -#define portBYTE_ALIGNMENT 8 -#define portNOP() __asm volatile ( "NOP" ); +#define portSTACK_GROWTH ( -1 ) +#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) +#define portBYTE_ALIGNMENT 8 +#define portNOP() __asm volatile ( "NOP" ); /*-----------------------------------------------------------*/ @@ -109,92 +109,92 @@ typedef unsigned long UBaseType_t; * THUMB mode code will result in a compile time error. */ -#define portRESTORE_CONTEXT() \ -{ \ -extern volatile void * volatile pxCurrentTCB; \ -extern volatile uint32_t ulCriticalNesting; \ - \ - /* Set the LR to the task stack. */ \ - __asm volatile ( \ - "LDR R0, =pxCurrentTCB \n\t" \ - "LDR R0, [R0] \n\t" \ - "LDR LR, [R0] \n\t" \ - \ - /* The critical nesting depth is the first item on the stack. */ \ - /* Load it into the ulCriticalNesting variable. */ \ - "LDR R0, =ulCriticalNesting \n\t" \ - "LDMFD LR!, {R1} \n\t" \ - "STR R1, [R0] \n\t" \ - \ - /* Get the SPSR from the stack. */ \ - "LDMFD LR!, {R0} \n\t" \ - "MSR SPSR, R0 \n\t" \ - \ - /* Restore all system mode registers for the task. */ \ - "LDMFD LR, {R0-R14}^ \n\t" \ - "NOP \n\t" \ - \ - /* Restore the return address. */ \ - "LDR LR, [LR, #+60] \n\t" \ - \ - /* And return - correcting the offset in the LR to obtain the */ \ - /* correct address. */ \ - "SUBS PC, LR, #4 \n\t" \ - ); \ - ( void ) ulCriticalNesting; \ - ( void ) pxCurrentTCB; \ -} +#define portRESTORE_CONTEXT() \ + { \ + extern volatile void * volatile pxCurrentTCB; \ + extern volatile uint32_t ulCriticalNesting; \ + \ + /* Set the LR to the task stack. */ \ + __asm volatile ( \ + "LDR R0, =pxCurrentTCB \n\t" \ + "LDR R0, [R0] \n\t" \ + "LDR LR, [R0] \n\t" \ + \ + /* The critical nesting depth is the first item on the stack. */ \ + /* Load it into the ulCriticalNesting variable. */ \ + "LDR R0, =ulCriticalNesting \n\t" \ + "LDMFD LR!, {R1} \n\t" \ + "STR R1, [R0] \n\t" \ + \ + /* Get the SPSR from the stack. */ \ + "LDMFD LR!, {R0} \n\t" \ + "MSR SPSR, R0 \n\t" \ + \ + /* Restore all system mode registers for the task. */ \ + "LDMFD LR, {R0-R14}^ \n\t" \ + "NOP \n\t" \ + \ + /* Restore the return address. */ \ + "LDR LR, [LR, #+60] \n\t" \ + \ + /* And return - correcting the offset in the LR to obtain the */ \ + /* correct address. */ \ + "SUBS PC, LR, #4 \n\t" \ + ); \ + ( void ) ulCriticalNesting; \ + ( void ) pxCurrentTCB; \ + } /*-----------------------------------------------------------*/ -#define portSAVE_CONTEXT() \ -{ \ -extern volatile void * volatile pxCurrentTCB; \ -extern volatile uint32_t ulCriticalNesting; \ - \ - /* Push R0 as we are going to use the register. */ \ - __asm volatile ( \ - "STMDB SP!, {R0} \n\t" \ - \ - /* Set R0 to point to the task stack pointer. */ \ - "STMDB SP,{SP}^ \n\t" \ - "NOP \n\t" \ - "SUB SP, SP, #4 \n\t" \ - "LDMIA SP!,{R0} \n\t" \ - \ - /* Push the return address onto the stack. */ \ - "STMDB R0!, {LR} \n\t" \ - \ - /* Now we have saved LR we can use it instead of R0. */ \ - "MOV LR, R0 \n\t" \ - \ - /* Pop R0 so we can save it onto the system mode stack. */ \ - "LDMIA SP!, {R0} \n\t" \ - \ - /* Push all the system mode registers onto the task stack. */ \ - "STMDB LR,{R0-LR}^ \n\t" \ - "NOP \n\t" \ - "SUB LR, LR, #60 \n\t" \ - \ - /* Push the SPSR onto the task stack. */ \ - "MRS R0, SPSR \n\t" \ - "STMDB LR!, {R0} \n\t" \ - \ - "LDR R0, =ulCriticalNesting \n\t" \ - "LDR R0, [R0] \n\t" \ - "STMDB LR!, {R0} \n\t" \ - \ - /* Store the new top of stack for the task. */ \ - "LDR R0, =pxCurrentTCB \n\t" \ - "LDR R0, [R0] \n\t" \ - "STR LR, [R0] \n\t" \ - ); \ - ( void ) ulCriticalNesting; \ - ( void ) pxCurrentTCB; \ -} - - -#define portYIELD_FROM_ISR() vTaskSwitchContext() -#define portYIELD() __asm volatile ( "SWI 0" ) +#define portSAVE_CONTEXT() \ + { \ + extern volatile void * volatile pxCurrentTCB; \ + extern volatile uint32_t ulCriticalNesting; \ + \ + /* Push R0 as we are going to use the register. */ \ + __asm volatile ( \ + "STMDB SP!, {R0} \n\t" \ + \ + /* Set R0 to point to the task stack pointer. */ \ + "STMDB SP,{SP}^ \n\t" \ + "NOP \n\t" \ + "SUB SP, SP, #4 \n\t" \ + "LDMIA SP!,{R0} \n\t" \ + \ + /* Push the return address onto the stack. */ \ + "STMDB R0!, {LR} \n\t" \ + \ + /* Now we have saved LR we can use it instead of R0. */ \ + "MOV LR, R0 \n\t" \ + \ + /* Pop R0 so we can save it onto the system mode stack. */ \ + "LDMIA SP!, {R0} \n\t" \ + \ + /* Push all the system mode registers onto the task stack. */ \ + "STMDB LR,{R0-LR}^ \n\t" \ + "NOP \n\t" \ + "SUB LR, LR, #60 \n\t" \ + \ + /* Push the SPSR onto the task stack. */ \ + "MRS R0, SPSR \n\t" \ + "STMDB LR!, {R0} \n\t" \ + \ + "LDR R0, =ulCriticalNesting \n\t" \ + "LDR R0, [R0] \n\t" \ + "STMDB LR!, {R0} \n\t" \ + \ + /* Store the new top of stack for the task. */ \ + "LDR R0, =pxCurrentTCB \n\t" \ + "LDR R0, [R0] \n\t" \ + "STR LR, [R0] \n\t" \ + ); \ + ( void ) ulCriticalNesting; \ + ( void ) pxCurrentTCB; \ + } + + +#define portYIELD_FROM_ISR() vTaskSwitchContext() +#define portYIELD() __asm volatile ( "SWI 0" ) /*-----------------------------------------------------------*/ @@ -209,42 +209,42 @@ extern volatile uint32_t ulCriticalNesting; \ #ifdef THUMB_INTERWORK - extern void vPortDisableInterruptsFromThumb( void ) __attribute__ ((naked)); - extern void vPortEnableInterruptsFromThumb( void ) __attribute__ ((naked)); + extern void vPortDisableInterruptsFromThumb( void ) __attribute__( ( naked ) ); + extern void vPortEnableInterruptsFromThumb( void ) __attribute__( ( naked ) ); #define portDISABLE_INTERRUPTS() vPortDisableInterruptsFromThumb() #define portENABLE_INTERRUPTS() vPortEnableInterruptsFromThumb() #else - #define portDISABLE_INTERRUPTS() \ - __asm volatile ( \ - "STMDB SP!, {R0} \n\t" /* Push R0. */ \ - "MRS R0, CPSR \n\t" /* Get CPSR. */ \ - "ORR R0, R0, #0xC0 \n\t" /* Disable IRQ, FIQ. */ \ - "MSR CPSR, R0 \n\t" /* Write back modified value. */ \ - "LDMIA SP!, {R0} " ) /* Pop R0. */ - - #define portENABLE_INTERRUPTS() \ - __asm volatile ( \ - "STMDB SP!, {R0} \n\t" /* Push R0. */ \ - "MRS R0, CPSR \n\t" /* Get CPSR. */ \ - "BIC R0, R0, #0xC0 \n\t" /* Enable IRQ, FIQ. */ \ - "MSR CPSR, R0 \n\t" /* Write back modified value. */ \ - "LDMIA SP!, {R0} " ) /* Pop R0. */ + #define portDISABLE_INTERRUPTS() \ + __asm volatile ( \ + "STMDB SP!, {R0} \n\t" /* Push R0. */ \ + "MRS R0, CPSR \n\t" /* Get CPSR. */ \ + "ORR R0, R0, #0xC0 \n\t" /* Disable IRQ, FIQ. */ \ + "MSR CPSR, R0 \n\t" /* Write back modified value. */ \ + "LDMIA SP!, {R0} " ) /* Pop R0. */ + + #define portENABLE_INTERRUPTS() \ + __asm volatile ( \ + "STMDB SP!, {R0} \n\t" /* Push R0. */ \ + "MRS R0, CPSR \n\t" /* Get CPSR. */ \ + "BIC R0, R0, #0xC0 \n\t" /* Enable IRQ, FIQ. */ \ + "MSR CPSR, R0 \n\t" /* Write back modified value. */ \ + "LDMIA SP!, {R0} " ) /* Pop R0. */ #endif /* THUMB_INTERWORK */ extern void vPortEnterCritical( void ); extern void vPortExitCritical( void ); -#define portENTER_CRITICAL() vPortEnterCritical(); -#define portEXIT_CRITICAL() vPortExitCritical(); +#define portENTER_CRITICAL() vPortEnterCritical(); +#define portEXIT_CRITICAL() vPortExitCritical(); /*-----------------------------------------------------------*/ /* Task function macros as described on the FreeRTOS.org WEB site. */ -#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters ) -#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters ) +#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters ) +#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters ) /* *INDENT-OFF* */ #ifdef __cplusplus diff --git a/Source/portable/GCC/ARM_CA53_64_BIT/README.md b/Source/portable/GCC/ARM_CA53_64_BIT/README.md new file mode 100644 index 000000000..b3d56c040 --- /dev/null +++ b/Source/portable/GCC/ARM_CA53_64_BIT/README.md @@ -0,0 +1,16 @@ +# ARM_CA53_64_BIT port + +Initial port to support Armv8-A architecture in FreeRTOS kernel was written for +Arm Cortex-A53 processor. + +* ARM_CA53_64_BIT + * Memory mapped interace to access Arm GIC registers + +This port is generic and can be used as a starting point for other Armv8-A +application processors. Therefore, the port `ARM_CA53_64_BIT` is renamed as +`Arm_AARCH64`. The existing projects that use old port `ARM_CA53_64_BIT`, +should migrate to renamed port `Arm_AARCH64`. + +**NOTE** + +This port uses memory mapped interace to access Arm GIC registers. diff --git a/Source/portable/GCC/ARM_CA53_64_BIT/portmacro.h b/Source/portable/GCC/ARM_CA53_64_BIT/portmacro.h deleted file mode 100644 index fd6366065..000000000 --- a/Source/portable/GCC/ARM_CA53_64_BIT/portmacro.h +++ /dev/null @@ -1,214 +0,0 @@ -/* - * FreeRTOS Kernel V10.6.2 - * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - * - * SPDX-License-Identifier: MIT - * - * Permission is hereby granted, free of charge, to any person obtaining a copy of - * this software and associated documentation files (the "Software"), to deal in - * the Software without restriction, including without limitation the rights to - * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of - * the Software, and to permit persons to whom the Software is furnished to do so, - * subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in all - * copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS - * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR - * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER - * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN - * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - * - * https://www.FreeRTOS.org - * https://github.com/FreeRTOS - * - */ - -#ifndef PORTMACRO_H -#define PORTMACRO_H - -/* *INDENT-OFF* */ -#ifdef __cplusplus - extern "C" { -#endif -/* *INDENT-ON* */ - -/*----------------------------------------------------------- - * Port specific definitions. - * - * The settings in this file configure FreeRTOS correctly for the given hardware - * and compiler. - * - * These settings should not be altered. - *----------------------------------------------------------- - */ - -/* Type definitions. */ -#define portCHAR char -#define portFLOAT float -#define portDOUBLE double -#define portLONG long -#define portSHORT short -#define portSTACK_TYPE size_t -#define portBASE_TYPE long - -typedef portSTACK_TYPE StackType_t; -typedef portBASE_TYPE BaseType_t; -typedef uint64_t UBaseType_t; - -typedef uint64_t TickType_t; -#define portMAX_DELAY ( ( TickType_t ) 0xffffffffffffffff ) - -/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do -not need to be guarded with a critical section. */ -#define portTICK_TYPE_IS_ATOMIC 1 - -/*-----------------------------------------------------------*/ - -/* Hardware specifics. */ -#define portSTACK_GROWTH ( -1 ) -#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) -#define portBYTE_ALIGNMENT 16 -#define portPOINTER_SIZE_TYPE uint64_t - -/*-----------------------------------------------------------*/ - -/* Task utilities. */ - -/* Called at the end of an ISR that can cause a context switch. */ -#define portEND_SWITCHING_ISR( xSwitchRequired )\ -{ \ -extern uint64_t ullPortYieldRequired; \ - \ - if( xSwitchRequired != pdFALSE ) \ - { \ - ullPortYieldRequired = pdTRUE; \ - } \ -} - -#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x ) -#if defined( GUEST ) - #define portYIELD() __asm volatile ( "SVC 0" ::: "memory" ) -#else - #define portYIELD() __asm volatile ( "SMC 0" ::: "memory" ) -#endif -/*----------------------------------------------------------- - * Critical section control - *----------------------------------------------------------*/ - -extern void vPortEnterCritical( void ); -extern void vPortExitCritical( void ); -extern UBaseType_t uxPortSetInterruptMask( void ); -extern void vPortClearInterruptMask( UBaseType_t uxNewMaskValue ); -extern void vPortInstallFreeRTOSVectorTable( void ); - -#define portDISABLE_INTERRUPTS() \ - __asm volatile ( "MSR DAIFSET, #2" ::: "memory" ); \ - __asm volatile ( "DSB SY" ); \ - __asm volatile ( "ISB SY" ); - -#define portENABLE_INTERRUPTS() \ - __asm volatile ( "MSR DAIFCLR, #2" ::: "memory" ); \ - __asm volatile ( "DSB SY" ); \ - __asm volatile ( "ISB SY" ); - - -/* These macros do not globally disable/enable interrupts. They do mask off -interrupts that have a priority below configMAX_API_CALL_INTERRUPT_PRIORITY. */ -#define portENTER_CRITICAL() vPortEnterCritical(); -#define portEXIT_CRITICAL() vPortExitCritical(); -#define portSET_INTERRUPT_MASK_FROM_ISR() uxPortSetInterruptMask() -#define portCLEAR_INTERRUPT_MASK_FROM_ISR(x) vPortClearInterruptMask(x) - -/*-----------------------------------------------------------*/ - -/* Task function macros as described on the FreeRTOS.org WEB site. These are -not required for this port but included in case common demo code that uses these -macros is used. */ -#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters ) -#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters ) - -/* Prototype of the FreeRTOS tick handler. This must be installed as the -handler for whichever peripheral is used to generate the RTOS tick. */ -void FreeRTOS_Tick_Handler( void ); - -/* Any task that uses the floating point unit MUST call vPortTaskUsesFPU() -before any floating point instructions are executed. */ -void vPortTaskUsesFPU( void ); -#define portTASK_USES_FLOATING_POINT() vPortTaskUsesFPU() - -#define portLOWEST_INTERRUPT_PRIORITY ( ( ( uint32_t ) configUNIQUE_INTERRUPT_PRIORITIES ) - 1UL ) -#define portLOWEST_USABLE_INTERRUPT_PRIORITY ( portLOWEST_INTERRUPT_PRIORITY - 1UL ) - -/* Architecture specific optimisations. */ -#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION - #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1 -#endif - -#if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 - - /* Store/clear the ready priorities in a bit map. */ - #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) ) - #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) ) - - /*-----------------------------------------------------------*/ - - #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31 - __builtin_clz( uxReadyPriorities ) ) - -#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */ - -#ifdef configASSERT - void vPortValidateInterruptPriority( void ); - #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() vPortValidateInterruptPriority() -#endif /* configASSERT */ - -#define portNOP() __asm volatile( "NOP" ) -#define portINLINE __inline - -/* The number of bits to shift for an interrupt priority is dependent on the -number of bits implemented by the interrupt controller. */ -#if configUNIQUE_INTERRUPT_PRIORITIES == 16 - #define portPRIORITY_SHIFT 4 - #define portMAX_BINARY_POINT_VALUE 3 -#elif configUNIQUE_INTERRUPT_PRIORITIES == 32 - #define portPRIORITY_SHIFT 3 - #define portMAX_BINARY_POINT_VALUE 2 -#elif configUNIQUE_INTERRUPT_PRIORITIES == 64 - #define portPRIORITY_SHIFT 2 - #define portMAX_BINARY_POINT_VALUE 1 -#elif configUNIQUE_INTERRUPT_PRIORITIES == 128 - #define portPRIORITY_SHIFT 1 - #define portMAX_BINARY_POINT_VALUE 0 -#elif configUNIQUE_INTERRUPT_PRIORITIES == 256 - #define portPRIORITY_SHIFT 0 - #define portMAX_BINARY_POINT_VALUE 0 -#else - #error Invalid configUNIQUE_INTERRUPT_PRIORITIES setting. configUNIQUE_INTERRUPT_PRIORITIES must be set to the number of unique priorities implemented by the target hardware -#endif - -/* Interrupt controller access addresses. */ -#define portICCPMR_PRIORITY_MASK_OFFSET ( 0x04 ) -#define portICCIAR_INTERRUPT_ACKNOWLEDGE_OFFSET ( 0x0C ) -#define portICCEOIR_END_OF_INTERRUPT_OFFSET ( 0x10 ) -#define portICCBPR_BINARY_POINT_OFFSET ( 0x08 ) -#define portICCRPR_RUNNING_PRIORITY_OFFSET ( 0x14 ) - -#define portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS ( configINTERRUPT_CONTROLLER_BASE_ADDRESS + configINTERRUPT_CONTROLLER_CPU_INTERFACE_OFFSET ) -#define portICCPMR_PRIORITY_MASK_REGISTER ( *( ( volatile uint32_t * ) ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCPMR_PRIORITY_MASK_OFFSET ) ) ) -#define portICCIAR_INTERRUPT_ACKNOWLEDGE_REGISTER_ADDRESS ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCIAR_INTERRUPT_ACKNOWLEDGE_OFFSET ) -#define portICCEOIR_END_OF_INTERRUPT_REGISTER_ADDRESS ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCEOIR_END_OF_INTERRUPT_OFFSET ) -#define portICCPMR_PRIORITY_MASK_REGISTER_ADDRESS ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCPMR_PRIORITY_MASK_OFFSET ) -#define portICCBPR_BINARY_POINT_REGISTER ( *( ( const volatile uint32_t * ) ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCBPR_BINARY_POINT_OFFSET ) ) ) -#define portICCRPR_RUNNING_PRIORITY_REGISTER ( *( ( const volatile uint32_t * ) ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCRPR_RUNNING_PRIORITY_OFFSET ) ) ) - -#define portMEMORY_BARRIER() __asm volatile( "" ::: "memory" ) - -/* *INDENT-OFF* */ -#ifdef __cplusplus - } -#endif -/* *INDENT-ON* */ - -#endif /* PORTMACRO_H */ diff --git a/Source/portable/GCC/ARM_CA53_64_BIT_SRE/README.md b/Source/portable/GCC/ARM_CA53_64_BIT_SRE/README.md new file mode 100644 index 000000000..fb5d7936a --- /dev/null +++ b/Source/portable/GCC/ARM_CA53_64_BIT_SRE/README.md @@ -0,0 +1,16 @@ +# ARM_CA53_64_BIT_SRE port + +Initial port to support Armv8-A architecture in FreeRTOS kernel was written for +Arm Cortex-A53 processor. + +* ARM_CA53_64_BIT_SRE + * System Register interace to access Arm GIC registers + +This port is generic and can be used as a starting point for other Armv8-A +application processors. Therefore, the port `Arm_AARCH64_SRE` is renamed as +`Arm_AARCH64_SRE`. The existing projects that use old port `Arm_AARCH64_SRE`, +should migrate to renamed port `Arm_AARCH64_SRE`. + +**NOTE** + +This port uses System Register interace to access Arm GIC registers. diff --git a/Source/portable/GCC/ARM_CA53_64_BIT_SRE/portmacro.h b/Source/portable/GCC/ARM_CA53_64_BIT_SRE/portmacro.h deleted file mode 100644 index f401f7dfc..000000000 --- a/Source/portable/GCC/ARM_CA53_64_BIT_SRE/portmacro.h +++ /dev/null @@ -1,199 +0,0 @@ -/* - * FreeRTOS Kernel V10.6.2 - * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - * - * SPDX-License-Identifier: MIT - * - * Permission is hereby granted, free of charge, to any person obtaining a copy of - * this software and associated documentation files (the "Software"), to deal in - * the Software without restriction, including without limitation the rights to - * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of - * the Software, and to permit persons to whom the Software is furnished to do so, - * subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in all - * copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS - * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR - * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER - * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN - * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - * - * https://www.FreeRTOS.org - * https://github.com/FreeRTOS - * - */ - -#ifndef PORTMACRO_H -#define PORTMACRO_H - -/* *INDENT-OFF* */ -#ifdef __cplusplus - extern "C" { -#endif -/* *INDENT-ON* */ - -/*----------------------------------------------------------- - * Port specific definitions. - * - * The settings in this file configure FreeRTOS correctly for the given hardware - * and compiler. - * - * These settings should not be altered. - *----------------------------------------------------------- - */ - -/* Type definitions. */ -#define portCHAR char -#define portFLOAT float -#define portDOUBLE double -#define portLONG long -#define portSHORT short -#define portSTACK_TYPE size_t -#define portBASE_TYPE long - -typedef portSTACK_TYPE StackType_t; -typedef portBASE_TYPE BaseType_t; -typedef uint64_t UBaseType_t; - -typedef uint64_t TickType_t; -#define portMAX_DELAY ( ( TickType_t ) 0xffffffffffffffff ) - -/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do -not need to be guarded with a critical section. */ -#define portTICK_TYPE_IS_ATOMIC 1 - -/*-----------------------------------------------------------*/ - -/* Hardware specifics. */ -#define portSTACK_GROWTH ( -1 ) -#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) -#define portBYTE_ALIGNMENT 16 -#define portPOINTER_SIZE_TYPE uint64_t - -/*-----------------------------------------------------------*/ - -/* Task utilities. */ - -/* Called at the end of an ISR that can cause a context switch. */ -#define portEND_SWITCHING_ISR( xSwitchRequired )\ -{ \ -extern uint64_t ullPortYieldRequired; \ - \ - if( xSwitchRequired != pdFALSE ) \ - { \ - ullPortYieldRequired = pdTRUE; \ - } \ -} - -#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x ) -#if defined( GUEST ) - #define portYIELD() __asm volatile ( "SVC 0" ::: "memory" ) -#else - #define portYIELD() __asm volatile ( "SMC 0" ::: "memory" ) -#endif -/*----------------------------------------------------------- - * Critical section control - *----------------------------------------------------------*/ - -extern void vPortEnterCritical( void ); -extern void vPortExitCritical( void ); -extern UBaseType_t uxPortSetInterruptMask( void ); -extern void vPortClearInterruptMask( UBaseType_t uxNewMaskValue ); -extern void vPortInstallFreeRTOSVectorTable( void ); - -#define portDISABLE_INTERRUPTS() \ - __asm volatile ( "MSR DAIFSET, #2" ::: "memory" ); \ - __asm volatile ( "DSB SY" ); \ - __asm volatile ( "ISB SY" ); - -#define portENABLE_INTERRUPTS() \ - __asm volatile ( "MSR DAIFCLR, #2" ::: "memory" ); \ - __asm volatile ( "DSB SY" ); \ - __asm volatile ( "ISB SY" ); - - -/* These macros do not globally disable/enable interrupts. They do mask off -interrupts that have a priority below configMAX_API_CALL_INTERRUPT_PRIORITY. */ -#define portENTER_CRITICAL() vPortEnterCritical(); -#define portEXIT_CRITICAL() vPortExitCritical(); -#define portSET_INTERRUPT_MASK_FROM_ISR() uxPortSetInterruptMask() -#define portCLEAR_INTERRUPT_MASK_FROM_ISR(x) vPortClearInterruptMask(x) - -/*-----------------------------------------------------------*/ - -/* Task function macros as described on the FreeRTOS.org WEB site. These are -not required for this port but included in case common demo code that uses these -macros is used. */ -#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters ) -#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters ) - -/* Prototype of the FreeRTOS tick handler. This must be installed as the -handler for whichever peripheral is used to generate the RTOS tick. */ -void FreeRTOS_Tick_Handler( void ); - -/* Any task that uses the floating point unit MUST call vPortTaskUsesFPU() -before any floating point instructions are executed. */ -void vPortTaskUsesFPU( void ); -#define portTASK_USES_FLOATING_POINT() vPortTaskUsesFPU() - -#define portLOWEST_INTERRUPT_PRIORITY ( ( ( uint32_t ) configUNIQUE_INTERRUPT_PRIORITIES ) - 1UL ) -#define portLOWEST_USABLE_INTERRUPT_PRIORITY ( portLOWEST_INTERRUPT_PRIORITY - 1UL ) - -/* Architecture specific optimisations. */ -#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION - #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1 -#endif - -#if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 - - /* Store/clear the ready priorities in a bit map. */ - #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) ) - #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) ) - - /*-----------------------------------------------------------*/ - - #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31 - __builtin_clz( uxReadyPriorities ) ) - -#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */ - -#ifdef configASSERT - void vPortValidateInterruptPriority( void ); - #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() vPortValidateInterruptPriority() -#endif /* configASSERT */ - -#define portNOP() __asm volatile( "NOP" ) -#define portINLINE __inline - -/* The number of bits to shift for an interrupt priority is dependent on the -number of bits implemented by the interrupt controller. */ -#if configUNIQUE_INTERRUPT_PRIORITIES == 16 - #define portPRIORITY_SHIFT 4 - #define portMAX_BINARY_POINT_VALUE 3 -#elif configUNIQUE_INTERRUPT_PRIORITIES == 32 - #define portPRIORITY_SHIFT 3 - #define portMAX_BINARY_POINT_VALUE 2 -#elif configUNIQUE_INTERRUPT_PRIORITIES == 64 - #define portPRIORITY_SHIFT 2 - #define portMAX_BINARY_POINT_VALUE 1 -#elif configUNIQUE_INTERRUPT_PRIORITIES == 128 - #define portPRIORITY_SHIFT 1 - #define portMAX_BINARY_POINT_VALUE 0 -#elif configUNIQUE_INTERRUPT_PRIORITIES == 256 - #define portPRIORITY_SHIFT 0 - #define portMAX_BINARY_POINT_VALUE 0 -#else - #error Invalid configUNIQUE_INTERRUPT_PRIORITIES setting. configUNIQUE_INTERRUPT_PRIORITIES must be set to the number of unique priorities implemented by the target hardware -#endif - -#define portMEMORY_BARRIER() __asm volatile( "" ::: "memory" ) - -/* *INDENT-OFF* */ -#ifdef __cplusplus - } -#endif -/* *INDENT-ON* */ - -#endif /* PORTMACRO_H */ diff --git a/Source/portable/GCC/ARM_CA9/port.c b/Source/portable/GCC/ARM_CA9/port.c index 79fa32d10..bb3f1c002 100644 --- a/Source/portable/GCC/ARM_CA9/port.c +++ b/Source/portable/GCC/ARM_CA9/port.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -35,123 +35,123 @@ #include "task.h" #ifndef configINTERRUPT_CONTROLLER_BASE_ADDRESS - #error configINTERRUPT_CONTROLLER_BASE_ADDRESS must be defined. See https://www.FreeRTOS.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html + #error "configINTERRUPT_CONTROLLER_BASE_ADDRESS must be defined. See www.FreeRTOS.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html" #endif #ifndef configINTERRUPT_CONTROLLER_CPU_INTERFACE_OFFSET - #error configINTERRUPT_CONTROLLER_CPU_INTERFACE_OFFSET must be defined. See https://www.FreeRTOS.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html + #error "configINTERRUPT_CONTROLLER_CPU_INTERFACE_OFFSET must be defined. See www.FreeRTOS.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html" #endif #ifndef configUNIQUE_INTERRUPT_PRIORITIES - #error configUNIQUE_INTERRUPT_PRIORITIES must be defined. See https://www.FreeRTOS.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html + #error "configUNIQUE_INTERRUPT_PRIORITIES must be defined. See www.FreeRTOS.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html" #endif #ifndef configSETUP_TICK_INTERRUPT - #error configSETUP_TICK_INTERRUPT() must be defined. See https://www.FreeRTOS.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html + #error "configSETUP_TICK_INTERRUPT() must be defined. See www.FreeRTOS.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html" #endif /* configSETUP_TICK_INTERRUPT */ #ifndef configMAX_API_CALL_INTERRUPT_PRIORITY - #error configMAX_API_CALL_INTERRUPT_PRIORITY must be defined. See https://www.FreeRTOS.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html + #error "configMAX_API_CALL_INTERRUPT_PRIORITY must be defined. See www.FreeRTOS.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html" #endif #if configMAX_API_CALL_INTERRUPT_PRIORITY == 0 - #error configMAX_API_CALL_INTERRUPT_PRIORITY must not be set to 0 + #error "configMAX_API_CALL_INTERRUPT_PRIORITY must not be set to 0" #endif #if configMAX_API_CALL_INTERRUPT_PRIORITY > configUNIQUE_INTERRUPT_PRIORITIES - #error configMAX_API_CALL_INTERRUPT_PRIORITY must be less than or equal to configUNIQUE_INTERRUPT_PRIORITIES as the lower the numeric priority value the higher the logical interrupt priority + #error "configMAX_API_CALL_INTERRUPT_PRIORITY must be less than or equal to configUNIQUE_INTERRUPT_PRIORITIES as the lower the numeric priority value the higher the logical interrupt priority" #endif #if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 /* Check the configuration. */ - #if( configMAX_PRIORITIES > 32 ) - #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice. + #if ( configMAX_PRIORITIES > 32 ) + #error "configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice." #endif #endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */ /* In case security extensions are implemented. */ #if configMAX_API_CALL_INTERRUPT_PRIORITY <= ( configUNIQUE_INTERRUPT_PRIORITIES / 2 ) - #error configMAX_API_CALL_INTERRUPT_PRIORITY must be greater than ( configUNIQUE_INTERRUPT_PRIORITIES / 2 ) + #error "configMAX_API_CALL_INTERRUPT_PRIORITY must be greater than ( configUNIQUE_INTERRUPT_PRIORITIES / 2 )" #endif /* Some vendor specific files default configCLEAR_TICK_INTERRUPT() in -portmacro.h. */ + * portmacro.h. */ #ifndef configCLEAR_TICK_INTERRUPT #define configCLEAR_TICK_INTERRUPT() #endif /* A critical section is exited when the critical section nesting count reaches -this value. */ -#define portNO_CRITICAL_NESTING ( ( uint32_t ) 0 ) + * this value. */ +#define portNO_CRITICAL_NESTING ( ( uint32_t ) 0 ) /* In all GICs 255 can be written to the priority mask register to unmask all -(but the lowest) interrupt priority. */ -#define portUNMASK_VALUE ( 0xFFUL ) + * (but the lowest) interrupt priority. */ +#define portUNMASK_VALUE ( 0xFFUL ) /* Tasks are not created with a floating point context, but can be given a -floating point context after they have been created. A variable is stored as -part of the tasks context that holds portNO_FLOATING_POINT_CONTEXT if the task -does not have an FPU context, or any other value if the task does have an FPU -context. */ -#define portNO_FLOATING_POINT_CONTEXT ( ( StackType_t ) 0 ) + * floating point context after they have been created. A variable is stored as + * part of the tasks context that holds portNO_FLOATING_POINT_CONTEXT if the task + * does not have an FPU context, or any other value if the task does have an FPU + * context. */ +#define portNO_FLOATING_POINT_CONTEXT ( ( StackType_t ) 0 ) /* Constants required to setup the initial task context. */ -#define portINITIAL_SPSR ( ( StackType_t ) 0x1f ) /* System mode, ARM mode, IRQ enabled FIQ enabled. */ -#define portTHUMB_MODE_BIT ( ( StackType_t ) 0x20 ) -#define portINTERRUPT_ENABLE_BIT ( 0x80UL ) -#define portTHUMB_MODE_ADDRESS ( 0x01UL ) +#define portINITIAL_SPSR ( ( StackType_t ) 0x1f ) /* System mode, ARM mode, IRQ enabled FIQ enabled. */ +#define portTHUMB_MODE_BIT ( ( StackType_t ) 0x20 ) +#define portINTERRUPT_ENABLE_BIT ( 0x80UL ) +#define portTHUMB_MODE_ADDRESS ( 0x01UL ) /* Used by portASSERT_IF_INTERRUPT_PRIORITY_INVALID() when ensuring the binary -point is zero. */ -#define portBINARY_POINT_BITS ( ( uint8_t ) 0x03 ) + * point is zero. */ +#define portBINARY_POINT_BITS ( ( uint8_t ) 0x03 ) /* Masks all bits in the APSR other than the mode bits. */ -#define portAPSR_MODE_BITS_MASK ( 0x1F ) +#define portAPSR_MODE_BITS_MASK ( 0x1F ) /* The value of the mode bits in the APSR when the CPU is executing in user -mode. */ -#define portAPSR_USER_MODE ( 0x10 ) + * mode. */ +#define portAPSR_USER_MODE ( 0x10 ) /* The critical section macros only mask interrupts up to an application -determined priority level. Sometimes it is necessary to turn interrupt off in -the CPU itself before modifying certain hardware registers. */ -#define portCPU_IRQ_DISABLE() \ - __asm volatile ( "CPSID i" ::: "memory" ); \ - __asm volatile ( "DSB" ); \ + * determined priority level. Sometimes it is necessary to turn interrupt off in + * the CPU itself before modifying certain hardware registers. */ +#define portCPU_IRQ_DISABLE() \ + __asm volatile ( "CPSID i" ::: "memory" ); \ + __asm volatile ( "DSB" ); \ __asm volatile ( "ISB" ); -#define portCPU_IRQ_ENABLE() \ - __asm volatile ( "CPSIE i" ::: "memory" ); \ - __asm volatile ( "DSB" ); \ +#define portCPU_IRQ_ENABLE() \ + __asm volatile ( "CPSIE i" ::: "memory" ); \ + __asm volatile ( "DSB" ); \ __asm volatile ( "ISB" ); /* Macro to unmask all interrupt priorities. */ -#define portCLEAR_INTERRUPT_MASK() \ -{ \ - portCPU_IRQ_DISABLE(); \ - portICCPMR_PRIORITY_MASK_REGISTER = portUNMASK_VALUE; \ - __asm volatile ( "DSB \n" \ - "ISB \n" ); \ - portCPU_IRQ_ENABLE(); \ -} +#define portCLEAR_INTERRUPT_MASK() \ + { \ + portCPU_IRQ_DISABLE(); \ + portICCPMR_PRIORITY_MASK_REGISTER = portUNMASK_VALUE; \ + __asm volatile ( "DSB \n" \ + "ISB \n" ); \ + portCPU_IRQ_ENABLE(); \ + } -#define portINTERRUPT_PRIORITY_REGISTER_OFFSET 0x400UL -#define portMAX_8_BIT_VALUE ( ( uint8_t ) 0xff ) -#define portBIT_0_SET ( ( uint8_t ) 0x01 ) +#define portINTERRUPT_PRIORITY_REGISTER_OFFSET 0x400UL +#define portMAX_8_BIT_VALUE ( ( uint8_t ) 0xff ) +#define portBIT_0_SET ( ( uint8_t ) 0x01 ) /* Let the user override the pre-loading of the initial LR with the address of -prvTaskExitError() in case it messes up unwinding of the stack in the -debugger. */ + * prvTaskExitError() in case it messes up unwinding of the stack in the + * debugger. */ #ifdef configTASK_RETURN_ADDRESS - #define portTASK_RETURN_ADDRESS configTASK_RETURN_ADDRESS + #define portTASK_RETURN_ADDRESS configTASK_RETURN_ADDRESS #else - #define portTASK_RETURN_ADDRESS prvTaskExitError + #define portTASK_RETURN_ADDRESS prvTaskExitError #endif /* The space on the stack required to hold the FPU registers. This is 32 64-bit -registers, plus a 32-bit status register. */ -#define portFPU_REGISTER_WORDS ( ( 32 * 2 ) + 1 ) + * registers, plus a 32-bit status register. */ +#define portFPU_REGISTER_WORDS ( ( 32 * 2 ) + 1 ) /*-----------------------------------------------------------*/ @@ -185,47 +185,49 @@ static void prvTaskExitError( void ); * FPU registers to be saved on interrupt entry their IRQ handler must be * called vApplicationIRQHandler(). */ -void vApplicationFPUSafeIRQHandler( uint32_t ulICCIAR ) __attribute__((weak) ); +void vApplicationFPUSafeIRQHandler( uint32_t ulICCIAR ) __attribute__( ( weak ) ); /*-----------------------------------------------------------*/ /* A variable is used to keep track of the critical section nesting. This -variable has to be stored as part of the task context and must be initialised to -a non zero value to ensure interrupts don't inadvertently become unmasked before -the scheduler starts. As it is stored as part of the task context it will -automatically be set to 0 when the first task is started. */ + * variable has to be stored as part of the task context and must be initialised to + * a non zero value to ensure interrupts don't inadvertently become unmasked before + * the scheduler starts. As it is stored as part of the task context it will + * automatically be set to 0 when the first task is started. */ volatile uint32_t ulCriticalNesting = 9999UL; /* Saved as part of the task context. If ulPortTaskHasFPUContext is non-zero then -a floating point context must be saved and restored for the task. */ + * a floating point context must be saved and restored for the task. */ volatile uint32_t ulPortTaskHasFPUContext = pdFALSE; /* Set to 1 to pend a context switch from an ISR. */ volatile uint32_t ulPortYieldRequired = pdFALSE; /* Counts the interrupt nesting depth. A context switch is only performed if -if the nesting depth is 0. */ + * if the nesting depth is 0. */ volatile uint32_t ulPortInterruptNesting = 0UL; /* Used in the asm file. */ -__attribute__(( used )) const uint32_t ulICCIAR = portICCIAR_INTERRUPT_ACKNOWLEDGE_REGISTER_ADDRESS; -__attribute__(( used )) const uint32_t ulICCEOIR = portICCEOIR_END_OF_INTERRUPT_REGISTER_ADDRESS; -__attribute__(( used )) const uint32_t ulICCPMR = portICCPMR_PRIORITY_MASK_REGISTER_ADDRESS; -__attribute__(( used )) const uint32_t ulMaxAPIPriorityMask = ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT ); +__attribute__( ( used ) ) const uint32_t ulICCIAR = portICCIAR_INTERRUPT_ACKNOWLEDGE_REGISTER_ADDRESS; +__attribute__( ( used ) ) const uint32_t ulICCEOIR = portICCEOIR_END_OF_INTERRUPT_REGISTER_ADDRESS; +__attribute__( ( used ) ) const uint32_t ulICCPMR = portICCPMR_PRIORITY_MASK_REGISTER_ADDRESS; +__attribute__( ( used ) ) const uint32_t ulMaxAPIPriorityMask = ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT ); /*-----------------------------------------------------------*/ /* * See header file for description. */ -StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters ) +StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, + TaskFunction_t pxCode, + void * pvParameters ) { /* Setup the initial stack of the task. The stack is set exactly as - expected by the portRESTORE_CONTEXT() macro. - - The fist real value on the stack is the status register, which is set for - system mode, with interrupts enabled. A few NULLs are added first to ensure - GDB does not try decoding a non-existent return address. */ + * expected by the portRESTORE_CONTEXT() macro. + * + * The fist real value on the stack is the status register, which is set for + * system mode, with interrupts enabled. A few NULLs are added first to ensure + * GDB does not try decoding a non-existent return address. */ *pxTopOfStack = ( StackType_t ) NULL; pxTopOfStack--; *pxTopOfStack = ( StackType_t ) NULL; @@ -247,51 +249,51 @@ StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t px pxTopOfStack--; /* Next all the registers other than the stack pointer. */ - *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* R14 */ + *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* R14 */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x12121212; /* R12 */ + *pxTopOfStack = ( StackType_t ) 0x12121212; /* R12 */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x11111111; /* R11 */ + *pxTopOfStack = ( StackType_t ) 0x11111111; /* R11 */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x10101010; /* R10 */ + *pxTopOfStack = ( StackType_t ) 0x10101010; /* R10 */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x09090909; /* R9 */ + *pxTopOfStack = ( StackType_t ) 0x09090909; /* R9 */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x08080808; /* R8 */ + *pxTopOfStack = ( StackType_t ) 0x08080808; /* R8 */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x07070707; /* R7 */ + *pxTopOfStack = ( StackType_t ) 0x07070707; /* R7 */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x06060606; /* R6 */ + *pxTopOfStack = ( StackType_t ) 0x06060606; /* R6 */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x05050505; /* R5 */ + *pxTopOfStack = ( StackType_t ) 0x05050505; /* R5 */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x04040404; /* R4 */ + *pxTopOfStack = ( StackType_t ) 0x04040404; /* R4 */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x03030303; /* R3 */ + *pxTopOfStack = ( StackType_t ) 0x03030303; /* R3 */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x02020202; /* R2 */ + *pxTopOfStack = ( StackType_t ) 0x02020202; /* R2 */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x01010101; /* R1 */ + *pxTopOfStack = ( StackType_t ) 0x01010101; /* R1 */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */ + *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */ pxTopOfStack--; /* The task will start with a critical nesting count of 0 as interrupts are - enabled. */ + * enabled. */ *pxTopOfStack = portNO_CRITICAL_NESTING; - #if( configUSE_TASK_FPU_SUPPORT == 1 ) + #if ( configUSE_TASK_FPU_SUPPORT == 1 ) { /* The task will start without a floating point context. A task that - uses the floating point hardware must call vPortTaskUsesFPU() before - executing any floating point instructions. */ + * uses the floating point hardware must call vPortTaskUsesFPU() before + * executing any floating point instructions. */ pxTopOfStack--; *pxTopOfStack = portNO_FLOATING_POINT_CONTEXT; } - #elif( configUSE_TASK_FPU_SUPPORT == 2 ) + #elif ( configUSE_TASK_FPU_SUPPORT == 2 ) { /* The task will start with a floating point context. Leave enough - space for the registers - and ensure they are initialised to 0. */ + * space for the registers - and ensure they are initialised to 0. */ pxTopOfStack -= portFPU_REGISTER_WORDS; memset( pxTopOfStack, 0x00, portFPU_REGISTER_WORDS * sizeof( StackType_t ) ); @@ -299,11 +301,11 @@ StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t px *pxTopOfStack = pdTRUE; ulPortTaskHasFPUContext = pdTRUE; } - #else + #else /* if ( configUSE_TASK_FPU_SUPPORT == 1 ) */ { - #error Invalid configUSE_TASK_FPU_SUPPORT setting - configUSE_TASK_FPU_SUPPORT must be set to 1, 2, or left undefined. + #error "Invalid configUSE_TASK_FPU_SUPPORT setting - configUSE_TASK_FPU_SUPPORT must be set to 1, 2, or left undefined." } - #endif + #endif /* if ( configUSE_TASK_FPU_SUPPORT == 1 ) */ return pxTopOfStack; } @@ -312,34 +314,37 @@ StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t px static void prvTaskExitError( void ) { /* A function that implements a task must not exit or attempt to return to - its caller as there is nothing to return to. If a task wants to exit it - should instead call vTaskDelete( NULL ). - - Artificially force an assert() to be triggered if configASSERT() is - defined, then stop here so application writers can catch the error. */ + * its caller as there is nothing to return to. If a task wants to exit it + * should instead call vTaskDelete( NULL ). + * + * Artificially force an assert() to be triggered if configASSERT() is + * defined, then stop here so application writers can catch the error. */ configASSERT( ulPortInterruptNesting == ~0UL ); portDISABLE_INTERRUPTS(); - for( ;; ); + + for( ; ; ) + { + } } /*-----------------------------------------------------------*/ BaseType_t xPortStartScheduler( void ) { -uint32_t ulAPSR; + uint32_t ulAPSR; - #if( configASSERT_DEFINED == 1 ) + #if ( configASSERT_DEFINED == 1 ) { volatile uint8_t ucOriginalPriority; volatile uint8_t * const pucFirstUserPriorityRegister = ( volatile uint8_t * const ) ( configINTERRUPT_CONTROLLER_BASE_ADDRESS + portINTERRUPT_PRIORITY_REGISTER_OFFSET ); volatile uint8_t ucMaxPriorityValue; /* Determine how many priority bits are implemented in the GIC. - - Save the interrupt priority value that is about to be clobbered. */ + * + * Save the interrupt priority value that is about to be clobbered. */ ucOriginalPriority = *pucFirstUserPriorityRegister; /* Determine the number of priority bits available. First write to - all possible bits. */ + * all possible bits. */ *pucFirstUserPriorityRegister = portMAX_8_BIT_VALUE; /* Read the value back to see how many bits stuck. */ @@ -352,35 +357,35 @@ uint32_t ulAPSR; } /* Sanity check configUNIQUE_INTERRUPT_PRIORITIES matches the read - value. */ + * value. */ configASSERT( ucMaxPriorityValue == portLOWEST_INTERRUPT_PRIORITY ); /* Restore the clobbered interrupt priority register to its original - value. */ + * value. */ *pucFirstUserPriorityRegister = ucOriginalPriority; } #endif /* configASSERT_DEFINED */ /* Only continue if the CPU is not in User mode. The CPU must be in a - Privileged mode for the scheduler to start. */ - __asm volatile ( "MRS %0, APSR" : "=r" ( ulAPSR ) :: "memory" ); + * Privileged mode for the scheduler to start. */ + __asm volatile ( "MRS %0, APSR" : "=r" ( ulAPSR )::"memory" ); ulAPSR &= portAPSR_MODE_BITS_MASK; configASSERT( ulAPSR != portAPSR_USER_MODE ); if( ulAPSR != portAPSR_USER_MODE ) { /* Only continue if the binary point value is set to its lowest possible - setting. See the comments in vPortValidateInterruptPriority() below for - more information. */ + * setting. See the comments in vPortValidateInterruptPriority() below for + * more information. */ configASSERT( ( portICCBPR_BINARY_POINT_REGISTER & portBINARY_POINT_BITS ) <= portMAX_BINARY_POINT_VALUE ); if( ( portICCBPR_BINARY_POINT_REGISTER & portBINARY_POINT_BITS ) <= portMAX_BINARY_POINT_VALUE ) { /* Interrupts are turned off in the CPU itself to ensure tick does - not execute while the scheduler is being started. Interrupts are - automatically turned back on in the CPU when the first task starts - executing. */ + * not execute while the scheduler is being started. Interrupts are + * automatically turned back on in the CPU when the first task starts + * executing. */ portCPU_IRQ_DISABLE(); /* Start the timer that generates the tick ISR. */ @@ -392,10 +397,10 @@ uint32_t ulAPSR; } /* Will only get here if vTaskStartScheduler() was called with the CPU in - a non-privileged mode or the binary point register was not set to its lowest - possible value. prvTaskExitError() is referenced to prevent a compiler - warning about it being defined but not referenced in the case that the user - defines their own exit address. */ + * a non-privileged mode or the binary point register was not set to its lowest + * possible value. prvTaskExitError() is referenced to prevent a compiler + * warning about it being defined but not referenced in the case that the user + * defines their own exit address. */ ( void ) prvTaskExitError; return 0; } @@ -404,7 +409,7 @@ uint32_t ulAPSR; void vPortEndScheduler( void ) { /* Not implemented in ports where there is nothing to return to. - Artificially force an assert. */ + * Artificially force an assert. */ configASSERT( ulCriticalNesting == 1000UL ); } /*-----------------------------------------------------------*/ @@ -414,16 +419,16 @@ void vPortEnterCritical( void ) /* Mask interrupts up to the max syscall interrupt priority. */ ulPortSetInterruptMask(); - /* Now interrupts are disabled ulCriticalNesting can be accessed - directly. Increment ulCriticalNesting to keep a count of how many times - portENTER_CRITICAL() has been called. */ + /* Now that interrupts are disabled, ulCriticalNesting can be accessed + * directly. Increment ulCriticalNesting to keep a count of how many times + * portENTER_CRITICAL() has been called. */ ulCriticalNesting++; /* This is not the interrupt safe version of the enter critical function so - assert() if it is being called from an interrupt context. Only API - functions that end in "FromISR" can be used in an interrupt. Only assert if - the critical nesting count is 1 to protect against recursive calls if the - assert function also uses a critical section. */ + * assert() if it is being called from an interrupt context. Only API + * functions that end in "FromISR" can be used in an interrupt. Only assert if + * the critical nesting count is 1 to protect against recursive calls if the + * assert function also uses a critical section. */ if( ulCriticalNesting == 1 ) { configASSERT( ulPortInterruptNesting == 0 ); @@ -436,15 +441,15 @@ void vPortExitCritical( void ) if( ulCriticalNesting > portNO_CRITICAL_NESTING ) { /* Decrement the nesting count as the critical section is being - exited. */ + * exited. */ ulCriticalNesting--; /* If the nesting level has reached zero then all interrupt - priorities must be re-enabled. */ + * priorities must be re-enabled. */ if( ulCriticalNesting == portNO_CRITICAL_NESTING ) { /* Critical nesting has reached zero so all interrupt priorities - should be unmasked. */ + * should be unmasked. */ portCLEAR_INTERRUPT_MASK(); } } @@ -454,14 +459,14 @@ void vPortExitCritical( void ) void FreeRTOS_Tick_Handler( void ) { /* Set interrupt mask before altering scheduler structures. The tick - handler runs at the lowest priority, so interrupts cannot already be masked, - so there is no need to save and restore the current mask value. It is - necessary to turn off interrupts in the CPU itself while the ICCPMR is being - updated. */ + * handler runs at the lowest priority, so interrupts cannot already be masked, + * so there is no need to save and restore the current mask value. It is + * necessary to turn off interrupts in the CPU itself while the ICCPMR is being + * updated. */ portCPU_IRQ_DISABLE(); portICCPMR_PRIORITY_MASK_REGISTER = ( uint32_t ) ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT ); - __asm volatile ( "dsb \n" - "isb \n" ::: "memory" ); + __asm volatile ( "dsb \n" + "isb \n" ::: "memory" ); portCPU_IRQ_ENABLE(); /* Increment the RTOS tick. */ @@ -476,18 +481,18 @@ void FreeRTOS_Tick_Handler( void ) } /*-----------------------------------------------------------*/ -#if( configUSE_TASK_FPU_SUPPORT != 2 ) +#if ( configUSE_TASK_FPU_SUPPORT != 2 ) void vPortTaskUsesFPU( void ) { - uint32_t ulInitialFPSCR = 0; + uint32_t ulInitialFPSCR = 0; /* A task is registering the fact that it needs an FPU context. Set the - FPU flag (which is saved as part of the task context). */ + * FPU flag (which is saved as part of the task context). */ ulPortTaskHasFPUContext = pdTRUE; /* Initialise the floating point status register. */ - __asm volatile ( "FMXR FPSCR, %0" :: "r" (ulInitialFPSCR) : "memory" ); + __asm volatile ( "FMXR FPSCR, %0" ::"r" ( ulInitialFPSCR ) : "memory" ); } #endif /* configUSE_TASK_FPU_SUPPORT */ @@ -504,11 +509,12 @@ void vPortClearInterruptMask( uint32_t ulNewMaskValue ) uint32_t ulPortSetInterruptMask( void ) { -uint32_t ulReturn; + uint32_t ulReturn; /* Interrupt in the CPU must be turned off while the ICCPMR is being - updated. */ + * updated. */ portCPU_IRQ_DISABLE(); + if( portICCPMR_PRIORITY_MASK_REGISTER == ( uint32_t ) ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT ) ) { /* Interrupts were already masked. */ @@ -518,45 +524,46 @@ uint32_t ulReturn; { ulReturn = pdFALSE; portICCPMR_PRIORITY_MASK_REGISTER = ( uint32_t ) ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT ); - __asm volatile ( "dsb \n" - "isb \n" ::: "memory" ); + __asm volatile ( "dsb \n" + "isb \n" ::: "memory" ); } + portCPU_IRQ_ENABLE(); return ulReturn; } /*-----------------------------------------------------------*/ -#if( configASSERT_DEFINED == 1 ) +#if ( configASSERT_DEFINED == 1 ) void vPortValidateInterruptPriority( void ) { /* The following assertion will fail if a service routine (ISR) for - an interrupt that has been assigned a priority above - configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API - function. ISR safe FreeRTOS API functions must *only* be called - from interrupts that have been assigned a priority at or below - configMAX_SYSCALL_INTERRUPT_PRIORITY. - - Numerically low interrupt priority numbers represent logically high - interrupt priorities, therefore the priority of the interrupt must - be set to a value equal to or numerically *higher* than - configMAX_SYSCALL_INTERRUPT_PRIORITY. - - FreeRTOS maintains separate thread and ISR API functions to ensure - interrupt entry is as fast and simple as possible. */ + * an interrupt that has been assigned a priority above + * configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API + * function. ISR safe FreeRTOS API functions must *only* be called + * from interrupts that have been assigned a priority at or below + * configMAX_SYSCALL_INTERRUPT_PRIORITY. + * + * Numerically low interrupt priority numbers represent logically high + * interrupt priorities, therefore the priority of the interrupt must + * be set to a value equal to or numerically *higher* than + * configMAX_SYSCALL_INTERRUPT_PRIORITY. + * + * FreeRTOS maintains separate thread and ISR API functions to ensure + * interrupt entry is as fast and simple as possible. */ configASSERT( portICCRPR_RUNNING_PRIORITY_REGISTER >= ( uint32_t ) ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT ) ); /* Priority grouping: The interrupt controller (GIC) allows the bits - that define each interrupt's priority to be split between bits that - define the interrupt's pre-emption priority bits and bits that define - the interrupt's sub-priority. For simplicity all bits must be defined - to be pre-emption priority bits. The following assertion will fail if - this is not the case (if some bits represent a sub-priority). - - The priority grouping is configured by the GIC's binary point register - (ICCBPR). Writting 0 to ICCBPR will ensure it is set to its lowest - possible value (which may be above 0). */ + * that define each interrupt's priority to be split between bits that + * define the interrupt's pre-emption priority bits and bits that define + * the interrupt's sub-priority. For simplicity all bits must be defined + * to be pre-emption priority bits. The following assertion will fail if + * this is not the case (if some bits represent a sub-priority). + * + * The priority grouping is configured by the GIC's binary point register + * (ICCBPR). Writting 0 to ICCBPR will ensure it is set to its lowest + * possible value (which may be above 0). */ configASSERT( ( portICCBPR_BINARY_POINT_REGISTER & portBINARY_POINT_BITS ) <= portMAX_BINARY_POINT_VALUE ); } diff --git a/Source/portable/GCC/ARM_CA9/portASM.S b/Source/portable/GCC/ARM_CA9/portASM.S index c9eb16d77..bf187ebd6 100644 --- a/Source/portable/GCC/ARM_CA9/portASM.S +++ b/Source/portable/GCC/ARM_CA9/portASM.S @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -75,9 +75,9 @@ /* Save the floating point context, if any. */ FMRXNE R1, FPSCR + PUSHNE {R1} VPUSHNE {D0-D15} VPUSHNE {D16-D31} - PUSHNE {R1} /* Save ulPortTaskHasFPUContext itself. */ PUSH {R3} @@ -106,9 +106,9 @@ CMP R1, #0 /* Restore the floating point context, if any. */ - POPNE {R0} VPOPNE {D16-D31} VPOPNE {D0-D15} + POPNE {R0} VMSRNE FPSCR, R0 /* Restore the critical section nesting depth. */ @@ -145,8 +145,15 @@ FreeRTOS_SWI_Handler: /* Save the context of the current task and select a new task to run. */ portSAVE_CONTEXT + + /* Ensure bit 2 of the stack pointer is clear. */ + MOV r2, sp + AND r2, r2, #4 + SUB sp, sp, r2 + LDR R0, vTaskSwitchContextConst BLX R0 + portRESTORE_CONTEXT @@ -256,7 +263,13 @@ switch_before_exit: /* Call the function that selects the new task to execute. vTaskSwitchContext() if vTaskSwitchContext() uses LDRD or STRD instructions, or 8 byte aligned stack allocated data. LR does not need - saving as a new LR will be loaded by portRESTORE_CONTEXT anyway. */ + saving as a new LR will be loaded by portRESTORE_CONTEXT anyway. + Ensure bit 2 of the stack pointer is clear. r2 holds the bit 2 value for + future use. */ + MOV r2, sp + AND r2, r2, #4 + SUB sp, sp, r2 + LDR R0, vTaskSwitchContextConst BLX R0 diff --git a/Source/portable/GCC/ARM_CA9/portmacro.h b/Source/portable/GCC/ARM_CA9/portmacro.h index a88b3d8f2..f472a0ba7 100644 --- a/Source/portable/GCC/ARM_CA9/portmacro.h +++ b/Source/portable/GCC/ARM_CA9/portmacro.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -46,54 +46,54 @@ */ /* Type definitions. */ -#define portCHAR char -#define portFLOAT float -#define portDOUBLE double -#define portLONG long -#define portSHORT short -#define portSTACK_TYPE uint32_t -#define portBASE_TYPE long +#define portCHAR char +#define portFLOAT float +#define portDOUBLE double +#define portLONG long +#define portSHORT short +#define portSTACK_TYPE uint32_t +#define portBASE_TYPE long -typedef portSTACK_TYPE StackType_t; -typedef long BaseType_t; -typedef unsigned long UBaseType_t; +typedef portSTACK_TYPE StackType_t; +typedef long BaseType_t; +typedef unsigned long UBaseType_t; -typedef uint32_t TickType_t; -#define portMAX_DELAY ( TickType_t ) 0xffffffffUL +typedef uint32_t TickType_t; +#define portMAX_DELAY ( TickType_t ) 0xffffffffUL /* 32-bit tick type on a 32-bit architecture, so reads of the tick count do -not need to be guarded with a critical section. */ -#define portTICK_TYPE_IS_ATOMIC 1 + * not need to be guarded with a critical section. */ +#define portTICK_TYPE_IS_ATOMIC 1 /*-----------------------------------------------------------*/ /* Hardware specifics. */ -#define portSTACK_GROWTH ( -1 ) -#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) -#define portBYTE_ALIGNMENT 8 +#define portSTACK_GROWTH ( -1 ) +#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) +#define portBYTE_ALIGNMENT 8 /*-----------------------------------------------------------*/ /* Task utilities. */ /* Called at the end of an ISR that can cause a context switch. */ -#define portEND_SWITCHING_ISR( xSwitchRequired )\ -{ \ -extern uint32_t ulPortYieldRequired; \ - \ - if( xSwitchRequired != pdFALSE ) \ - { \ - ulPortYieldRequired = pdTRUE; \ - } \ -} +#define portEND_SWITCHING_ISR( xSwitchRequired ) \ + { \ + extern uint32_t ulPortYieldRequired; \ + \ + if( xSwitchRequired != pdFALSE ) \ + { \ + ulPortYieldRequired = pdTRUE; \ + } \ + } -#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x ) -#define portYIELD() __asm volatile ( "SWI 0" ::: "memory" ); +#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x ) +#define portYIELD() __asm volatile ( "SWI 0" ::: "memory" ); /*----------------------------------------------------------- - * Critical section control - *----------------------------------------------------------*/ +* Critical section control +*----------------------------------------------------------*/ extern void vPortEnterCritical( void ); extern void vPortExitCritical( void ); @@ -102,105 +102,106 @@ extern void vPortClearInterruptMask( uint32_t ulNewMaskValue ); extern void vPortInstallFreeRTOSVectorTable( void ); /* These macros do not globally disable/enable interrupts. They do mask off -interrupts that have a priority below configMAX_API_CALL_INTERRUPT_PRIORITY. */ -#define portENTER_CRITICAL() vPortEnterCritical(); -#define portEXIT_CRITICAL() vPortExitCritical(); -#define portDISABLE_INTERRUPTS() ulPortSetInterruptMask() -#define portENABLE_INTERRUPTS() vPortClearInterruptMask( 0 ) -#define portSET_INTERRUPT_MASK_FROM_ISR() ulPortSetInterruptMask() -#define portCLEAR_INTERRUPT_MASK_FROM_ISR(x) vPortClearInterruptMask(x) + * interrupts that have a priority below configMAX_API_CALL_INTERRUPT_PRIORITY. */ +#define portENTER_CRITICAL() vPortEnterCritical(); +#define portEXIT_CRITICAL() vPortExitCritical(); +#define portDISABLE_INTERRUPTS() ulPortSetInterruptMask() +#define portENABLE_INTERRUPTS() vPortClearInterruptMask( 0 ) +#define portSET_INTERRUPT_MASK_FROM_ISR() ulPortSetInterruptMask() +#define portCLEAR_INTERRUPT_MASK_FROM_ISR( x ) vPortClearInterruptMask( x ) /*-----------------------------------------------------------*/ /* Task function macros as described on the FreeRTOS.org WEB site. These are -not required for this port but included in case common demo code that uses these -macros is used. */ -#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters ) -#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters ) + * not required for this port but included in case common demo code that uses these + * macros is used. */ +#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters ) +#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters ) /* Prototype of the FreeRTOS tick handler. This must be installed as the -handler for whichever peripheral is used to generate the RTOS tick. */ + * handler for whichever peripheral is used to generate the RTOS tick. */ void FreeRTOS_Tick_Handler( void ); /* If configUSE_TASK_FPU_SUPPORT is set to 1 (or left undefined) then tasks are -created without an FPU context and must call vPortTaskUsesFPU() to give -themselves an FPU context before using any FPU instructions. If -configUSE_TASK_FPU_SUPPORT is set to 2 then all tasks will have an FPU context -by default. */ -#if( configUSE_TASK_FPU_SUPPORT != 2 ) + * created without an FPU context and must call vPortTaskUsesFPU() to give + * themselves an FPU context before using any FPU instructions. If + * configUSE_TASK_FPU_SUPPORT is set to 2 then all tasks will have an FPU context + * by default. */ +#if ( configUSE_TASK_FPU_SUPPORT != 2 ) void vPortTaskUsesFPU( void ); #else - /* Each task has an FPU context already, so define this function away to - nothing to prevent it being called accidentally. */ + +/* Each task has an FPU context already, so define this function away to + * nothing to prevent it being called accidentally. */ #define vPortTaskUsesFPU() #endif -#define portTASK_USES_FLOATING_POINT() vPortTaskUsesFPU() +#define portTASK_USES_FLOATING_POINT() vPortTaskUsesFPU() -#define portLOWEST_INTERRUPT_PRIORITY ( ( ( uint32_t ) configUNIQUE_INTERRUPT_PRIORITIES ) - 1UL ) -#define portLOWEST_USABLE_INTERRUPT_PRIORITY ( portLOWEST_INTERRUPT_PRIORITY - 1UL ) +#define portLOWEST_INTERRUPT_PRIORITY ( ( ( uint32_t ) configUNIQUE_INTERRUPT_PRIORITIES ) - 1UL ) +#define portLOWEST_USABLE_INTERRUPT_PRIORITY ( portLOWEST_INTERRUPT_PRIORITY - 1UL ) /* Architecture specific optimisations. */ #ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION - #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1 + #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1 #endif #if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 - /* Store/clear the ready priorities in a bit map. */ - #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) ) - #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) ) +/* Store/clear the ready priorities in a bit map. */ + #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) ) + #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) ) - /*-----------------------------------------------------------*/ +/*-----------------------------------------------------------*/ - #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - ( uint32_t ) __builtin_clz( uxReadyPriorities ) ) + #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - ( uint32_t ) __builtin_clz( uxReadyPriorities ) ) #endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */ #ifdef configASSERT void vPortValidateInterruptPriority( void ); - #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() vPortValidateInterruptPriority() + #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() vPortValidateInterruptPriority() #endif /* configASSERT */ -#define portNOP() __asm volatile( "NOP" ) -#define portINLINE __inline +#define portNOP() __asm volatile ( "NOP" ) +#define portINLINE __inline /* The number of bits to shift for an interrupt priority is dependent on the -number of bits implemented by the interrupt controller. */ + * number of bits implemented by the interrupt controller. */ #if configUNIQUE_INTERRUPT_PRIORITIES == 16 - #define portPRIORITY_SHIFT 4 - #define portMAX_BINARY_POINT_VALUE 3 + #define portPRIORITY_SHIFT 4 + #define portMAX_BINARY_POINT_VALUE 3 #elif configUNIQUE_INTERRUPT_PRIORITIES == 32 - #define portPRIORITY_SHIFT 3 - #define portMAX_BINARY_POINT_VALUE 2 + #define portPRIORITY_SHIFT 3 + #define portMAX_BINARY_POINT_VALUE 2 #elif configUNIQUE_INTERRUPT_PRIORITIES == 64 - #define portPRIORITY_SHIFT 2 - #define portMAX_BINARY_POINT_VALUE 1 + #define portPRIORITY_SHIFT 2 + #define portMAX_BINARY_POINT_VALUE 1 #elif configUNIQUE_INTERRUPT_PRIORITIES == 128 - #define portPRIORITY_SHIFT 1 - #define portMAX_BINARY_POINT_VALUE 0 + #define portPRIORITY_SHIFT 1 + #define portMAX_BINARY_POINT_VALUE 0 #elif configUNIQUE_INTERRUPT_PRIORITIES == 256 - #define portPRIORITY_SHIFT 0 - #define portMAX_BINARY_POINT_VALUE 0 -#else + #define portPRIORITY_SHIFT 0 + #define portMAX_BINARY_POINT_VALUE 0 +#else /* if configUNIQUE_INTERRUPT_PRIORITIES == 16 */ #error Invalid configUNIQUE_INTERRUPT_PRIORITIES setting. configUNIQUE_INTERRUPT_PRIORITIES must be set to the number of unique priorities implemented by the target hardware -#endif +#endif /* if configUNIQUE_INTERRUPT_PRIORITIES == 16 */ /* Interrupt controller access addresses. */ -#define portICCPMR_PRIORITY_MASK_OFFSET ( 0x04 ) -#define portICCIAR_INTERRUPT_ACKNOWLEDGE_OFFSET ( 0x0C ) -#define portICCEOIR_END_OF_INTERRUPT_OFFSET ( 0x10 ) -#define portICCBPR_BINARY_POINT_OFFSET ( 0x08 ) -#define portICCRPR_RUNNING_PRIORITY_OFFSET ( 0x14 ) - -#define portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS ( configINTERRUPT_CONTROLLER_BASE_ADDRESS + configINTERRUPT_CONTROLLER_CPU_INTERFACE_OFFSET ) -#define portICCPMR_PRIORITY_MASK_REGISTER ( *( ( volatile uint32_t * ) ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCPMR_PRIORITY_MASK_OFFSET ) ) ) -#define portICCIAR_INTERRUPT_ACKNOWLEDGE_REGISTER_ADDRESS ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCIAR_INTERRUPT_ACKNOWLEDGE_OFFSET ) -#define portICCEOIR_END_OF_INTERRUPT_REGISTER_ADDRESS ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCEOIR_END_OF_INTERRUPT_OFFSET ) -#define portICCPMR_PRIORITY_MASK_REGISTER_ADDRESS ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCPMR_PRIORITY_MASK_OFFSET ) -#define portICCBPR_BINARY_POINT_REGISTER ( *( ( const volatile uint32_t * ) ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCBPR_BINARY_POINT_OFFSET ) ) ) -#define portICCRPR_RUNNING_PRIORITY_REGISTER ( *( ( const volatile uint32_t * ) ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCRPR_RUNNING_PRIORITY_OFFSET ) ) ) - -#define portMEMORY_BARRIER() __asm volatile( "" ::: "memory" ) +#define portICCPMR_PRIORITY_MASK_OFFSET ( 0x04 ) +#define portICCIAR_INTERRUPT_ACKNOWLEDGE_OFFSET ( 0x0C ) +#define portICCEOIR_END_OF_INTERRUPT_OFFSET ( 0x10 ) +#define portICCBPR_BINARY_POINT_OFFSET ( 0x08 ) +#define portICCRPR_RUNNING_PRIORITY_OFFSET ( 0x14 ) + +#define portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS ( configINTERRUPT_CONTROLLER_BASE_ADDRESS + configINTERRUPT_CONTROLLER_CPU_INTERFACE_OFFSET ) +#define portICCPMR_PRIORITY_MASK_REGISTER ( *( ( volatile uint32_t * ) ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCPMR_PRIORITY_MASK_OFFSET ) ) ) +#define portICCIAR_INTERRUPT_ACKNOWLEDGE_REGISTER_ADDRESS ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCIAR_INTERRUPT_ACKNOWLEDGE_OFFSET ) +#define portICCEOIR_END_OF_INTERRUPT_REGISTER_ADDRESS ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCEOIR_END_OF_INTERRUPT_OFFSET ) +#define portICCPMR_PRIORITY_MASK_REGISTER_ADDRESS ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCPMR_PRIORITY_MASK_OFFSET ) +#define portICCBPR_BINARY_POINT_REGISTER ( *( ( const volatile uint32_t * ) ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCBPR_BINARY_POINT_OFFSET ) ) ) +#define portICCRPR_RUNNING_PRIORITY_REGISTER ( *( ( const volatile uint32_t * ) ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCRPR_RUNNING_PRIORITY_OFFSET ) ) ) + +#define portMEMORY_BARRIER() __asm volatile ( "" ::: "memory" ) /* *INDENT-OFF* */ #ifdef __cplusplus diff --git a/Source/portable/GCC/ARM_CM0/port.c b/Source/portable/GCC/ARM_CM0/port.c index 063a33ef6..c7115b7d1 100644 --- a/Source/portable/GCC/ARM_CM0/port.c +++ b/Source/portable/GCC/ARM_CM0/port.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -34,6 +34,9 @@ #include "FreeRTOS.h" #include "task.h" +/* Prototype of all Interrupt Service Routines (ISRs). */ +typedef void ( * portISR_t )( void ); + /* Constants required to manipulate the NVIC. */ #define portNVIC_SYSTICK_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000e010 ) ) #define portNVIC_SYSTICK_LOAD_REG ( *( ( volatile uint32_t * ) 0xe000e014 ) ) @@ -51,6 +54,10 @@ #define portNVIC_PENDSV_PRI ( portMIN_INTERRUPT_PRIORITY << 16UL ) #define portNVIC_SYSTICK_PRI ( portMIN_INTERRUPT_PRIORITY << 24UL ) +/* Constants used to check the installation of the FreeRTOS interrupt handlers. */ +#define portSCB_VTOR_REG ( *( ( portISR_t ** ) 0xe000ed08 ) ) +#define portVECTOR_INDEX_PENDSV ( 14 ) + /* Constants required to set up the initial stack. */ #define portINITIAL_XPSR ( 0x01000000 ) @@ -200,25 +207,25 @@ void vPortSVCHandler( void ) void vPortStartFirstTask( void ) { - /* The MSP stack is not reset as, unlike on M3/4 parts, there is no vector - * table offset register that can be used to locate the initial stack value. - * Not all M0 parts have the application vector table at address 0. */ + /* Don't reset the MSP stack as is done on CM3/4 devices. The vector table + * in some CM0 devices cannot be modified and thus may not hold the + * application's initial MSP value. */ __asm volatile ( " .syntax unified \n" - " ldr r2, pxCurrentTCBConst2 \n"/* Obtain location of pxCurrentTCB. */ + " ldr r2, pxCurrentTCBConst2 \n" /* Obtain location of pxCurrentTCB. */ " ldr r3, [r2] \n" - " ldr r0, [r3] \n"/* The first item in pxCurrentTCB is the task top of stack. */ - " adds r0, #32 \n"/* Discard everything up to r0. */ - " msr psp, r0 \n"/* This is now the new top of stack to use in the task. */ - " movs r0, #2 \n"/* Switch to the psp stack. */ - " msr CONTROL, r0 \n" + " ldr r0, [r3] \n" /* The first item in pxCurrentTCB is the task top of stack. */ + " adds r0, #32 \n" /* Discard everything up to r0. */ + " msr psp, r0 \n" /* This is now the new top of stack to use in the task. */ + " movs r0, #2 \n" /* Switch to the psp stack. */ + " msr CONTROL, r0 \n" " isb \n" - " pop {r0-r5} \n"/* Pop the registers that are saved automatically. */ - " mov lr, r5 \n"/* lr is now in r5. */ - " pop {r3} \n"/* Return address is now in r3. */ - " pop {r2} \n"/* Pop and discard XPSR. */ - " cpsie i \n"/* The first task has its context and interrupts can be enabled. */ - " bx r3 \n"/* Finally, jump to the user defined task code. */ + " pop {r0-r5} \n" /* Pop the registers that are saved automatically. */ + " mov lr, r5 \n" /* lr is now in r5. */ + " pop {r3} \n" /* Return address is now in r3. */ + " pop {r2} \n" /* Pop and discard XPSR. */ + " cpsie i \n" /* The first task has its context and interrupts can be enabled. */ + " bx r3 \n" /* Finally, jump to the user defined task code. */ " \n" " .align 4 \n" "pxCurrentTCBConst2: .word pxCurrentTCB " @@ -231,7 +238,42 @@ void vPortStartFirstTask( void ) */ BaseType_t xPortStartScheduler( void ) { - /* Make PendSV, CallSV and SysTick the same priority as the kernel. */ + /* An application can install FreeRTOS interrupt handlers in one of the + * folllowing ways: + * 1. Direct Routing - Install the function xPortPendSVHandler for PendSV + * interrupt. + * 2. Indirect Routing - Install separate handler for PendSV interrupt and + * route program control from that handler to xPortPendSVHandler function. + * + * Applications that use Indirect Routing must set + * configCHECK_HANDLER_INSTALLATION to 0 in their FreeRTOSConfig.h. Direct + * routing, which is validated here when configCHECK_HANDLER_INSTALLATION + * is 1, should be preferred when possible. */ + #if ( configCHECK_HANDLER_INSTALLATION == 1 ) + { + /* Point pxVectorTable to the interrupt vector table. Systems without + * a VTOR register provide the value zero in the VTOR register and + * the vector table itself is located at the address 0x00000000. */ + const portISR_t * const pxVectorTable = portSCB_VTOR_REG; + + /* Validate that the application has correctly installed the FreeRTOS + * handler for PendSV interrupt. We do not check the installation of the + * SysTick handler because the application may choose to drive the RTOS + * tick using a timer other than the SysTick timer by overriding the + * weak function vPortSetupTimerInterrupt(). + * + * Assertion failures here indicate incorrect installation of the + * FreeRTOS handler. For help installing the FreeRTOS handler, see + * https://www.FreeRTOS.org/FAQHelp.html. + * + * Systems with a configurable address for the interrupt vector table + * can also encounter assertion failures or even system faults here if + * VTOR is not set correctly to point to the application's vector table. */ + configASSERT( pxVectorTable[ portVECTOR_INDEX_PENDSV ] == xPortPendSVHandler ); + } + #endif /* configCHECK_HANDLER_INSTALLATION */ + + /* Make PendSV and SysTick the lowest priority interrupts. */ portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI; portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI; @@ -330,13 +372,13 @@ void xPortPendSVHandler( void ) " .syntax unified \n" " mrs r0, psp \n" " \n" - " ldr r3, pxCurrentTCBConst \n"/* Get the location of the current TCB. */ + " ldr r3, pxCurrentTCBConst \n" /* Get the location of the current TCB. */ " ldr r2, [r3] \n" " \n" - " subs r0, r0, #32 \n"/* Make space for the remaining low registers. */ - " str r0, [r2] \n"/* Save the new top of stack. */ - " stmia r0!, {r4-r7} \n"/* Store the low registers that are not saved automatically. */ - " mov r4, r8 \n"/* Store the high registers. */ + " subs r0, r0, #32 \n" /* Make space for the remaining low registers. */ + " str r0, [r2] \n" /* Save the new top of stack. */ + " stmia r0!, {r4-r7} \n" /* Store the low registers that are not saved automatically. */ + " mov r4, r8 \n" /* Store the high registers. */ " mov r5, r9 \n" " mov r6, r10 \n" " mov r7, r11 \n" @@ -346,21 +388,21 @@ void xPortPendSVHandler( void ) " cpsid i \n" " bl vTaskSwitchContext \n" " cpsie i \n" - " pop {r2, r3} \n"/* lr goes in r3. r2 now holds tcb pointer. */ + " pop {r2, r3} \n" /* lr goes in r3. r2 now holds tcb pointer. */ " \n" " ldr r1, [r2] \n" - " ldr r0, [r1] \n"/* The first item in pxCurrentTCB is the task top of stack. */ - " adds r0, r0, #16 \n"/* Move to the high registers. */ - " ldmia r0!, {r4-r7} \n"/* Pop the high registers. */ + " ldr r0, [r1] \n" /* The first item in pxCurrentTCB is the task top of stack. */ + " adds r0, r0, #16 \n" /* Move to the high registers. */ + " ldmia r0!, {r4-r7} \n" /* Pop the high registers. */ " mov r8, r4 \n" " mov r9, r5 \n" " mov r10, r6 \n" " mov r11, r7 \n" " \n" - " msr psp, r0 \n"/* Remember the new top of stack for the task. */ + " msr psp, r0 \n" /* Remember the new top of stack for the task. */ " \n" - " subs r0, r0, #32 \n"/* Go back for the low registers that are not automatically restored. */ - " ldmia r0!, {r4-r7} \n"/* Pop low registers. */ + " subs r0, r0, #32 \n" /* Go back for the low registers that are not automatically restored. */ + " ldmia r0!, {r4-r7} \n" /* Pop low registers. */ " \n" " bx r3 \n" " \n" @@ -375,13 +417,19 @@ void xPortSysTickHandler( void ) uint32_t ulPreviousMask; ulPreviousMask = portSET_INTERRUPT_MASK_FROM_ISR(); + traceISR_ENTER(); { /* Increment the RTOS tick. */ if( xTaskIncrementTick() != pdFALSE ) { + traceISR_EXIT_TO_SCHEDULER(); /* Pend a context switch. */ portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; } + else + { + traceISR_EXIT(); + } } portCLEAR_INTERRUPT_MASK_FROM_ISR( ulPreviousMask ); } diff --git a/Source/portable/GCC/ARM_CM0/portmacro.h b/Source/portable/GCC/ARM_CM0/portmacro.h index 46f308d85..41519997b 100644 --- a/Source/portable/GCC/ARM_CM0/portmacro.h +++ b/Source/portable/GCC/ARM_CM0/portmacro.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -87,9 +87,19 @@ extern void vPortYield( void ); #define portNVIC_INT_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed04 ) ) #define portNVIC_PENDSVSET_BIT ( 1UL << 28UL ) #define portYIELD() vPortYield() -#define portEND_SWITCHING_ISR( xSwitchRequired ) \ - do { if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; } \ - while( 0 ) +#define portEND_SWITCHING_ISR( xSwitchRequired ) \ + do \ + { \ + if( xSwitchRequired ) \ + { \ + traceISR_EXIT_TO_SCHEDULER(); \ + portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; \ + } \ + else \ + { \ + traceISR_EXIT(); \ + } \ + } while( 0 ) #define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x ) /*-----------------------------------------------------------*/ diff --git a/Source/portable/GCC/ARM_CM23/non_secure/mpu_wrappers_v2_asm.c b/Source/portable/GCC/ARM_CM23/non_secure/mpu_wrappers_v2_asm.c index b8164a001..451244845 100644 --- a/Source/portable/GCC/ARM_CM23/non_secure/mpu_wrappers_v2_asm.c +++ b/Source/portable/GCC/ARM_CM23/non_secure/mpu_wrappers_v2_asm.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -376,32 +376,6 @@ } /*-----------------------------------------------------------*/ - char * MPU_pcTaskGetName( TaskHandle_t xTaskToQuery ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; - - char * MPU_pcTaskGetName( TaskHandle_t xTaskToQuery ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ - { - __asm volatile - ( - " .syntax unified \n" - " .extern MPU_pcTaskGetNameImpl \n" - " \n" - " push {r0, r1} \n" - " mrs r0, control \n" - " movs r1, #1 \n" - " tst r0, r1 \n" - " bne MPU_pcTaskGetName_Unpriv \n" - " MPU_pcTaskGetName_Priv: \n" - " pop {r0, r1} \n" - " b MPU_pcTaskGetNameImpl \n" - " MPU_pcTaskGetName_Unpriv: \n" - " pop {r0, r1} \n" - " svc %0 \n" - " \n" - : : "i" ( SYSTEM_CALL_pcTaskGetName ) : "memory" - ); - } -/*-----------------------------------------------------------*/ - #if ( configGENERATE_RUN_TIME_STATS == 1 ) configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetRunTimeCounter( const TaskHandle_t xTask ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; @@ -1562,31 +1536,28 @@ #if ( configUSE_TIMERS == 1 ) - BaseType_t MPU_xTimerGenericCommandEntry( const xTimerGenericCommandParams_t * pxParams ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + BaseType_t MPU_xTimerGenericCommandFromTaskEntry( const xTimerGenericCommandFromTaskParams_t * pxParams ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; - BaseType_t MPU_xTimerGenericCommandEntry( const xTimerGenericCommandParams_t * pxParams ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + BaseType_t MPU_xTimerGenericCommandFromTaskEntry( const xTimerGenericCommandFromTaskParams_t * pxParams ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ { __asm volatile ( - " .syntax unified \n" - " .extern MPU_xTimerGenericCommandPrivImpl \n" - " \n" - " push {r0, r1} \n" - " mrs r0, ipsr \n" - " cmp r0, #0 \n" - " bne MPU_xTimerGenericCommand_Priv \n" - " mrs r0, control \n" - " movs r1, #1 \n" - " tst r0, r1 \n" - " beq MPU_xTimerGenericCommand_Priv \n" - " MPU_xTimerGenericCommand_Unpriv: \n" - " pop {r0, r1} \n" - " svc %0 \n" - " MPU_xTimerGenericCommand_Priv: \n" - " pop {r0, r1} \n" - " b MPU_xTimerGenericCommandPrivImpl \n" - " \n" - : : "i" ( SYSTEM_CALL_xTimerGenericCommand ) : "memory" + " .syntax unified \n" + " .extern MPU_xTimerGenericCommandFromTaskImpl \n" + " \n" + " push {r0, r1} \n" + " mrs r0, control \n" + " movs r1, #1 \n" + " tst r0, r1 \n" + " bne MPU_xTimerGenericCommandFromTask_Unpriv \n" + " MPU_xTimerGenericCommandFromTask_Priv: \n" + " pop {r0, r1} \n" + " b MPU_xTimerGenericCommandFromTaskImpl \n" + " MPU_xTimerGenericCommandFromTask_Unpriv: \n" + " pop {r0, r1} \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xTimerGenericCommandFromTask ) : "memory" ); } diff --git a/Source/portable/GCC/ARM_CM23/non_secure/port.c b/Source/portable/GCC/ARM_CM23/non_secure/port.c index 9712ac353..230fe5fc2 100644 --- a/Source/portable/GCC/ARM_CM23/non_secure/port.c +++ b/Source/portable/GCC/ARM_CM23/non_secure/port.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -68,6 +68,22 @@ #if ( ( configRUN_FREERTOS_SECURE_ONLY == 1 ) && ( configENABLE_TRUSTZONE == 1 ) ) #error TrustZone needs to be disabled in order to run FreeRTOS on the Secure Side. #endif + +/** + * Cortex-M23 does not have non-secure PSPLIM. We should use PSPLIM on Cortex-M23 + * only when FreeRTOS runs on secure side. + */ +#if ( ( portHAS_ARMV8M_MAIN_EXTENSION == 0 ) && ( configRUN_FREERTOS_SECURE_ONLY == 0 ) ) + #define portUSE_PSPLIM_REGISTER 0 +#else + #define portUSE_PSPLIM_REGISTER 1 +#endif +/*-----------------------------------------------------------*/ + +/** + * @brief Prototype of all Interrupt Service Routines (ISRs). + */ +typedef void ( * portISR_t )( void ); /*-----------------------------------------------------------*/ /** @@ -91,10 +107,18 @@ /** * @brief Constants required to manipulate the SCB. */ -#define portSCB_SYS_HANDLER_CTRL_STATE_REG ( *( volatile uint32_t * ) 0xe000ed24 ) +#define portSCB_VTOR_REG ( *( ( portISR_t ** ) 0xe000ed08 ) ) +#define portSCB_SYS_HANDLER_CTRL_STATE_REG ( *( ( volatile uint32_t * ) 0xe000ed24 ) ) #define portSCB_MEM_FAULT_ENABLE_BIT ( 1UL << 16UL ) /*-----------------------------------------------------------*/ +/** + * @brief Constants used to check the installation of the FreeRTOS interrupt handlers. + */ +#define portVECTOR_INDEX_SVC ( 11 ) +#define portVECTOR_INDEX_PENDSV ( 14 ) +/*-----------------------------------------------------------*/ + /** * @brief Constants required to check the validity of an interrupt priority. */ @@ -111,8 +135,8 @@ /** * @brief Constants used during system call enter and exit. */ -#define portPSR_STACK_PADDING_MASK ( 1UL << 9UL ) -#define portEXC_RETURN_STACK_FRAME_TYPE_MASK ( 1UL << 4UL ) +#define portPSR_STACK_PADDING_MASK ( 1UL << 9UL ) +#define portEXC_RETURN_STACK_FRAME_TYPE_MASK ( 1UL << 4UL ) /*-----------------------------------------------------------*/ /** @@ -134,81 +158,81 @@ /** * @brief Offsets in the stack to the parameters when inside the SVC handler. */ -#define portOFFSET_TO_LR ( 5 ) -#define portOFFSET_TO_PC ( 6 ) -#define portOFFSET_TO_PSR ( 7 ) +#define portOFFSET_TO_LR ( 5 ) +#define portOFFSET_TO_PC ( 6 ) +#define portOFFSET_TO_PSR ( 7 ) /*-----------------------------------------------------------*/ /** * @brief Constants required to manipulate the MPU. */ -#define portMPU_TYPE_REG ( *( ( volatile uint32_t * ) 0xe000ed90 ) ) -#define portMPU_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed94 ) ) -#define portMPU_RNR_REG ( *( ( volatile uint32_t * ) 0xe000ed98 ) ) +#define portMPU_TYPE_REG ( *( ( volatile uint32_t * ) 0xe000ed90 ) ) +#define portMPU_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed94 ) ) +#define portMPU_RNR_REG ( *( ( volatile uint32_t * ) 0xe000ed98 ) ) -#define portMPU_RBAR_REG ( *( ( volatile uint32_t * ) 0xe000ed9c ) ) -#define portMPU_RLAR_REG ( *( ( volatile uint32_t * ) 0xe000eda0 ) ) +#define portMPU_RBAR_REG ( *( ( volatile uint32_t * ) 0xe000ed9c ) ) +#define portMPU_RLAR_REG ( *( ( volatile uint32_t * ) 0xe000eda0 ) ) -#define portMPU_RBAR_A1_REG ( *( ( volatile uint32_t * ) 0xe000eda4 ) ) -#define portMPU_RLAR_A1_REG ( *( ( volatile uint32_t * ) 0xe000eda8 ) ) +#define portMPU_RBAR_A1_REG ( *( ( volatile uint32_t * ) 0xe000eda4 ) ) +#define portMPU_RLAR_A1_REG ( *( ( volatile uint32_t * ) 0xe000eda8 ) ) -#define portMPU_RBAR_A2_REG ( *( ( volatile uint32_t * ) 0xe000edac ) ) -#define portMPU_RLAR_A2_REG ( *( ( volatile uint32_t * ) 0xe000edb0 ) ) +#define portMPU_RBAR_A2_REG ( *( ( volatile uint32_t * ) 0xe000edac ) ) +#define portMPU_RLAR_A2_REG ( *( ( volatile uint32_t * ) 0xe000edb0 ) ) -#define portMPU_RBAR_A3_REG ( *( ( volatile uint32_t * ) 0xe000edb4 ) ) -#define portMPU_RLAR_A3_REG ( *( ( volatile uint32_t * ) 0xe000edb8 ) ) +#define portMPU_RBAR_A3_REG ( *( ( volatile uint32_t * ) 0xe000edb4 ) ) +#define portMPU_RLAR_A3_REG ( *( ( volatile uint32_t * ) 0xe000edb8 ) ) -#define portMPU_MAIR0_REG ( *( ( volatile uint32_t * ) 0xe000edc0 ) ) -#define portMPU_MAIR1_REG ( *( ( volatile uint32_t * ) 0xe000edc4 ) ) +#define portMPU_MAIR0_REG ( *( ( volatile uint32_t * ) 0xe000edc0 ) ) +#define portMPU_MAIR1_REG ( *( ( volatile uint32_t * ) 0xe000edc4 ) ) -#define portMPU_RBAR_ADDRESS_MASK ( 0xffffffe0 ) /* Must be 32-byte aligned. */ -#define portMPU_RLAR_ADDRESS_MASK ( 0xffffffe0 ) /* Must be 32-byte aligned. */ +#define portMPU_RBAR_ADDRESS_MASK ( 0xffffffe0 ) /* Must be 32-byte aligned. */ +#define portMPU_RLAR_ADDRESS_MASK ( 0xffffffe0 ) /* Must be 32-byte aligned. */ -#define portMPU_RBAR_ACCESS_PERMISSIONS_MASK ( 3UL << 1UL ) +#define portMPU_RBAR_ACCESS_PERMISSIONS_MASK ( 3UL << 1UL ) -#define portMPU_MAIR_ATTR0_POS ( 0UL ) -#define portMPU_MAIR_ATTR0_MASK ( 0x000000ff ) +#define portMPU_MAIR_ATTR0_POS ( 0UL ) +#define portMPU_MAIR_ATTR0_MASK ( 0x000000ff ) -#define portMPU_MAIR_ATTR1_POS ( 8UL ) -#define portMPU_MAIR_ATTR1_MASK ( 0x0000ff00 ) +#define portMPU_MAIR_ATTR1_POS ( 8UL ) +#define portMPU_MAIR_ATTR1_MASK ( 0x0000ff00 ) -#define portMPU_MAIR_ATTR2_POS ( 16UL ) -#define portMPU_MAIR_ATTR2_MASK ( 0x00ff0000 ) +#define portMPU_MAIR_ATTR2_POS ( 16UL ) +#define portMPU_MAIR_ATTR2_MASK ( 0x00ff0000 ) -#define portMPU_MAIR_ATTR3_POS ( 24UL ) -#define portMPU_MAIR_ATTR3_MASK ( 0xff000000 ) +#define portMPU_MAIR_ATTR3_POS ( 24UL ) +#define portMPU_MAIR_ATTR3_MASK ( 0xff000000 ) -#define portMPU_MAIR_ATTR4_POS ( 0UL ) -#define portMPU_MAIR_ATTR4_MASK ( 0x000000ff ) +#define portMPU_MAIR_ATTR4_POS ( 0UL ) +#define portMPU_MAIR_ATTR4_MASK ( 0x000000ff ) -#define portMPU_MAIR_ATTR5_POS ( 8UL ) -#define portMPU_MAIR_ATTR5_MASK ( 0x0000ff00 ) +#define portMPU_MAIR_ATTR5_POS ( 8UL ) +#define portMPU_MAIR_ATTR5_MASK ( 0x0000ff00 ) -#define portMPU_MAIR_ATTR6_POS ( 16UL ) -#define portMPU_MAIR_ATTR6_MASK ( 0x00ff0000 ) +#define portMPU_MAIR_ATTR6_POS ( 16UL ) +#define portMPU_MAIR_ATTR6_MASK ( 0x00ff0000 ) -#define portMPU_MAIR_ATTR7_POS ( 24UL ) -#define portMPU_MAIR_ATTR7_MASK ( 0xff000000 ) +#define portMPU_MAIR_ATTR7_POS ( 24UL ) +#define portMPU_MAIR_ATTR7_MASK ( 0xff000000 ) -#define portMPU_RLAR_ATTR_INDEX0 ( 0UL << 1UL ) -#define portMPU_RLAR_ATTR_INDEX1 ( 1UL << 1UL ) -#define portMPU_RLAR_ATTR_INDEX2 ( 2UL << 1UL ) -#define portMPU_RLAR_ATTR_INDEX3 ( 3UL << 1UL ) -#define portMPU_RLAR_ATTR_INDEX4 ( 4UL << 1UL ) -#define portMPU_RLAR_ATTR_INDEX5 ( 5UL << 1UL ) -#define portMPU_RLAR_ATTR_INDEX6 ( 6UL << 1UL ) -#define portMPU_RLAR_ATTR_INDEX7 ( 7UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX0 ( 0UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX1 ( 1UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX2 ( 2UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX3 ( 3UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX4 ( 4UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX5 ( 5UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX6 ( 6UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX7 ( 7UL << 1UL ) -#define portMPU_RLAR_REGION_ENABLE ( 1UL ) +#define portMPU_RLAR_REGION_ENABLE ( 1UL ) /* Enable privileged access to unmapped region. */ -#define portMPU_PRIV_BACKGROUND_ENABLE_BIT ( 1UL << 2UL ) +#define portMPU_PRIV_BACKGROUND_ENABLE_BIT ( 1UL << 2UL ) /* Enable MPU. */ -#define portMPU_ENABLE_BIT ( 1UL << 0UL ) +#define portMPU_ENABLE_BIT ( 1UL << 0UL ) /* Expected value of the portMPU_TYPE register. */ -#define portEXPECTED_MPU_TYPE_VALUE ( configTOTAL_MPU_REGIONS << 8UL ) +#define portEXPECTED_MPU_TYPE_VALUE ( configTOTAL_MPU_REGIONS << 8UL ) /* Extract first address of the MPU region as encoded in the * RBAR (Region Base Address Register) value. */ @@ -448,13 +472,13 @@ portDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIV #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) - /** - * @brief Sets up the task stack so that upon returning from - * SVC, the task stack is used again. - * - * @param pulSystemCallStack The current SP when the SVC was raised. - * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler. - */ +/** + * @brief Sets up the task stack so that upon returning from + * SVC, the task stack is used again. + * + * @param pulSystemCallStack The current SP when the SVC was raised. + * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler. + */ void vSystemCallExit( uint32_t * pulSystemCallStack, uint32_t ulLR ) PRIVILEGED_FUNCTION; @@ -462,11 +486,11 @@ portDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIV #if ( configENABLE_MPU == 1 ) - /** - * @brief Checks whether or not the calling task is privileged. - * - * @return pdTRUE if the calling task is privileged, pdFALSE otherwise. - */ +/** + * @brief Checks whether or not the calling task is privileged. + * + * @return pdTRUE if the calling task is privileged, pdFALSE otherwise. + */ BaseType_t xPortIsTaskPrivileged( void ) PRIVILEGED_FUNCTION; #endif /* configENABLE_MPU == 1 */ @@ -501,13 +525,13 @@ PRIVILEGED_DATA static volatile uint32_t ulCriticalNesting = 0xaaaaaaaaUL; * FreeRTOS API functions are not called from interrupts that have been assigned * a priority above configMAX_SYSCALL_INTERRUPT_PRIORITY. */ -#if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) ) +#if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) static uint8_t ucMaxSysCallPriority = 0; static uint32_t ulMaxPRIGROUPValue = 0; static const volatile uint8_t * const pcInterruptPriorityRegisters = ( const volatile uint8_t * ) portNVIC_IP_REGISTERS_OFFSET_16; -#endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) ) */ +#endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */ #if ( configUSE_TICKLESS_IDLE == 1 ) @@ -760,8 +784,15 @@ __attribute__( ( weak ) ) void vPortSetupTimerInterrupt( void ) /* PRIVILEGED_FU } #endif /* configUSE_TICKLESS_IDLE */ - /* Stop and reset the SysTick. */ - portNVIC_SYSTICK_CTRL_REG = 0UL; + /* Stop and reset SysTick. + * + * QEMU versions older than 7.0.0 contain a bug which causes an error if we + * enable SysTick without first selecting a valid clock source. We trigger + * the bug if we change clock sources from a clock with a zero clock period + * to one with a nonzero clock period and enable Systick at the same time. + * So we configure the CLKSOURCE bit here, prior to setting the ENABLE bit. + * This workaround avoids the bug in QEMU versions older than 7.0.0. */ + portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT_CONFIG; portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL; /* Configure SysTick to interrupt at the requested rate. */ @@ -819,6 +850,7 @@ static void prvTaskExitError( void ) static void prvSetupMPU( void ) /* PRIVILEGED_FUNCTION */ { #if defined( __ARMCC_VERSION ) + /* Declaration when these variable are defined in code instead of being * exported from linker scripts. */ extern uint32_t * __privileged_functions_start__; @@ -972,13 +1004,19 @@ void SysTick_Handler( void ) /* PRIVILEGED_FUNCTION */ uint32_t ulPreviousMask; ulPreviousMask = portSET_INTERRUPT_MASK_FROM_ISR(); + traceISR_ENTER(); { /* Increment the RTOS tick. */ if( xTaskIncrementTick() != pdFALSE ) { + traceISR_EXIT_TO_SCHEDULER(); /* Pend a context switch. */ portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; } + else + { + traceISR_EXIT(); + } } portCLEAR_INTERRUPT_MASK_FROM_ISR( ulPreviousMask ); } @@ -988,6 +1026,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO { #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) ) #if defined( __ARMCC_VERSION ) + /* Declaration when these variable are defined in code instead of being * exported from linker scripts. */ extern uint32_t * __syscalls_flash_start__; @@ -1083,18 +1122,24 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO vRestoreContextOfFirstTask(); break; - #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) ) - case portSVC_RAISE_PRIVILEGE: + #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) ) + case portSVC_RAISE_PRIVILEGE: - /* Only raise the privilege, if the svc was raised from any of - * the system calls. */ - if( ( ulPC >= ( uint32_t ) __syscalls_flash_start__ ) && - ( ulPC <= ( uint32_t ) __syscalls_flash_end__ ) ) - { - vRaisePrivilege(); - } - break; - #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) */ + /* Only raise the privilege, if the svc was raised from any of + * the system calls. */ + if( ( ulPC >= ( uint32_t ) __syscalls_flash_start__ ) && + ( ulPC <= ( uint32_t ) __syscalls_flash_end__ ) ) + { + vRaisePrivilege(); + } + break; + #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) */ + + #if ( configENABLE_MPU == 1 ) + case portSVC_YIELD: + vPortYield(); + break; + #endif /* configENABLE_MPU == 1 */ default: /* Incorrect SVC call. */ @@ -1154,12 +1199,11 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO { /* Extended frame i.e. FPU in use. */ ulStackFrameSize = 26; - __asm volatile - ( + __asm volatile ( " vpush {s0} \n" /* Trigger lazy stacking. */ " vpop {s0} \n" /* Nullify the affect of the above instruction. */ ::: "memory" - ); + ); } else { @@ -1171,7 +1215,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO { ulStackFrameSize = 8; } - #endif /* if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */ + #endif /* configENABLE_FPU || configENABLE_MVE */ /* Make space on the system call stack for the stack frame. */ pulSystemCallStack = pulSystemCallStack - ulStackFrameSize; @@ -1187,18 +1231,24 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO * point (i.e. the caller of the MPU_). We need to restore it * when we exit from the system call. */ pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry = pulTaskStack[ portOFFSET_TO_LR ]; - /* Store the value of the PSPLIM register before the SVC was raised. * We need to restore it when we exit from the system call. */ - __asm volatile ( "mrs %0, psplim" : "=r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) ); + #if ( portUSE_PSPLIM_REGISTER == 1 ) + { + __asm volatile ( "mrs %0, psplim" : "=r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) ); + } + #endif /* Use the pulSystemCallStack in thread mode. */ __asm volatile ( "msr psp, %0" : : "r" ( pulSystemCallStack ) ); - __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) ); + #if ( portUSE_PSPLIM_REGISTER == 1 ) + { + __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) ); + } + #endif /* Start executing the system call upon returning from this handler. */ pulSystemCallStack[ portOFFSET_TO_PC ] = uxSystemCallImplementations[ ucSystemCallNumber ]; - /* Raise a request to exit from the system call upon finishing the * system call. */ pulSystemCallStack[ portOFFSET_TO_LR ] = ( uint32_t ) vRequestSystemCallExit; @@ -1224,14 +1274,13 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO pulSystemCallStack[ portOFFSET_TO_PSR ] &= ( ~portPSR_STACK_PADDING_MASK ); /* Raise the privilege for the duration of the system call. */ - __asm volatile - ( + __asm volatile ( " mrs r0, control \n" /* Obtain current control value. */ " movs r1, #1 \n" /* r1 = 1. */ " bics r0, r1 \n" /* Clear nPRIV bit. */ " msr control, r0 \n" /* Write back new control value. */ ::: "r0", "r1", "memory" - ); + ); } } @@ -1293,12 +1342,11 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO { /* Extended frame i.e. FPU in use. */ ulStackFrameSize = 26; - __asm volatile - ( + __asm volatile ( " vpush {s0} \n" /* Trigger lazy stacking. */ " vpop {s0} \n" /* Nullify the affect of the above instruction. */ ::: "memory" - ); + ); } else { @@ -1310,7 +1358,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO { ulStackFrameSize = 8; } - #endif /* if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */ + #endif /* configENABLE_FPU || configENABLE_MVE */ /* Make space on the task stack for the stack frame. */ pulTaskStack = pulTaskStack - ulStackFrameSize; @@ -1332,7 +1380,11 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO /* Restore the PSPLIM register to what it was at the time of * system call entry. */ - __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) ); + #if ( portUSE_PSPLIM_REGISTER == 1 ) + { + __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) ); + } + #endif /* If the hardware used padding to force the stack pointer * to be double word aligned, set the stacked xPSR bit[9], @@ -1350,14 +1402,13 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO pxMpuSettings->xSystemCallStackInfo.pulTaskStack = NULL; /* Drop the privilege before returning to the thread mode. */ - __asm volatile - ( + __asm volatile ( " mrs r0, control \n" /* Obtain current control value. */ " movs r1, #1 \n" /* r1 = 1. */ " orrs r0, r1 \n" /* Set nPRIV bit. */ " msr control, r0 \n" /* Write back new control value. */ ::: "r0", "r1", "memory" - ); + ); } } @@ -1410,21 +1461,21 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO xMPUSettings->ulContext[ ulIndex ] = 0x11111111; /* r11. */ ulIndex++; - xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pvParameters; /* r0. */ + xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pvParameters; /* r0. */ ulIndex++; - xMPUSettings->ulContext[ ulIndex ] = 0x01010101; /* r1. */ + xMPUSettings->ulContext[ ulIndex ] = 0x01010101; /* r1. */ ulIndex++; - xMPUSettings->ulContext[ ulIndex ] = 0x02020202; /* r2. */ + xMPUSettings->ulContext[ ulIndex ] = 0x02020202; /* r2. */ ulIndex++; - xMPUSettings->ulContext[ ulIndex ] = 0x03030303; /* r3. */ + xMPUSettings->ulContext[ ulIndex ] = 0x03030303; /* r3. */ ulIndex++; - xMPUSettings->ulContext[ ulIndex ] = 0x12121212; /* r12. */ + xMPUSettings->ulContext[ ulIndex ] = 0x12121212; /* r12. */ ulIndex++; xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portTASK_RETURN_ADDRESS; /* LR. */ ulIndex++; - xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxCode; /* PC. */ + xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxCode; /* PC. */ ulIndex++; - xMPUSettings->ulContext[ ulIndex ] = portINITIAL_XPSR; /* xPSR. */ + xMPUSettings->ulContext[ ulIndex ] = portINITIAL_XPSR; /* xPSR. */ ulIndex++; #if ( configENABLE_TRUSTZONE == 1 ) @@ -1435,8 +1486,9 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO #endif /* configENABLE_TRUSTZONE */ xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) ( pxTopOfStack - 8 ); /* PSP with the hardware saved stack. */ ulIndex++; - xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxEndOfStack; /* PSPLIM. */ + xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxEndOfStack; /* PSPLIM. */ ulIndex++; + if( xRunPrivileged == pdTRUE ) { xMPUSettings->ulTaskFlags |= portTASK_IS_PRIVILEGED_FLAG; @@ -1449,6 +1501,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portINITIAL_CONTROL_UNPRIVILEGED; /* CONTROL. */ ulIndex++; } + xMPUSettings->ulContext[ ulIndex ] = portINITIAL_EXC_RETURN; /* LR (EXC_RETURN). */ ulIndex++; @@ -1483,7 +1536,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO * interrupt. */ #if ( portPRELOAD_REGISTERS == 0 ) { - pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */ + pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */ *pxTopOfStack = portINITIAL_XPSR; /* xPSR. */ pxTopOfStack--; *pxTopOfStack = ( StackType_t ) pxCode; /* PC. */ @@ -1505,7 +1558,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO } #else /* portPRELOAD_REGISTERS */ { - pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */ + pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */ *pxTopOfStack = portINITIAL_XPSR; /* xPSR. */ pxTopOfStack--; *pxTopOfStack = ( StackType_t ) pxCode; /* PC. */ @@ -1540,7 +1593,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO pxTopOfStack--; *pxTopOfStack = portINITIAL_EXC_RETURN; /* EXC_RETURN. */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */ + *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */ #if ( configENABLE_TRUSTZONE == 1 ) { @@ -1559,22 +1612,52 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */ { - #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) ) + /* An application can install FreeRTOS interrupt handlers in one of the + * folllowing ways: + * 1. Direct Routing - Install the functions SVC_Handler and PendSV_Handler + * for SVCall and PendSV interrupts respectively. + * 2. Indirect Routing - Install separate handlers for SVCall and PendSV + * interrupts and route program control from those handlers to + * SVC_Handler and PendSV_Handler functions. + * + * Applications that use Indirect Routing must set + * configCHECK_HANDLER_INSTALLATION to 0 in their FreeRTOSConfig.h. Direct + * routing, which is validated here when configCHECK_HANDLER_INSTALLATION + * is 1, should be preferred when possible. */ + #if ( configCHECK_HANDLER_INSTALLATION == 1 ) + { + const portISR_t * const pxVectorTable = portSCB_VTOR_REG; + + /* Validate that the application has correctly installed the FreeRTOS + * handlers for SVCall and PendSV interrupts. We do not check the + * installation of the SysTick handler because the application may + * choose to drive the RTOS tick using a timer other than the SysTick + * timer by overriding the weak function vPortSetupTimerInterrupt(). + * + * Assertion failures here indicate incorrect installation of the + * FreeRTOS handlers. For help installing the FreeRTOS handlers, see + * https://www.FreeRTOS.org/FAQHelp.html. + * + * Systems with a configurable address for the interrupt vector table + * can also encounter assertion failures or even system faults here if + * VTOR is not set correctly to point to the application's vector table. */ + configASSERT( pxVectorTable[ portVECTOR_INDEX_SVC ] == SVC_Handler ); + configASSERT( pxVectorTable[ portVECTOR_INDEX_PENDSV ] == PendSV_Handler ); + } + #endif /* configCHECK_HANDLER_INSTALLATION */ + + #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) { - volatile uint32_t ulOriginalPriority; volatile uint32_t ulImplementedPrioBits = 0; volatile uint8_t ucMaxPriorityValue; /* Determine the maximum priority from which ISR safe FreeRTOS API - * functions can be called. ISR safe functions are those that end in - * "FromISR". FreeRTOS maintains separate thread and ISR API functions to + * functions can be called. ISR safe functions are those that end in + * "FromISR". FreeRTOS maintains separate thread and ISR API functions to * ensure interrupt entry is as fast and simple as possible. * - * Save the interrupt priority value that is about to be clobbered. */ - ulOriginalPriority = portNVIC_SHPR2_REG; - - /* Determine the number of priority bits available. First write to all - * possible bits. */ + * First, determine the number of priority bits available. Write to all + * possible bits in the priority setting for SVCall. */ portNVIC_SHPR2_REG = 0xFF000000; /* Read the value back to see how many bits stuck. */ @@ -1593,11 +1676,10 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */ /* Check that the bits not implemented in hardware are zero in * configMAX_SYSCALL_INTERRUPT_PRIORITY. */ - configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( ~ucMaxPriorityValue ) ) == 0U ); + configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( uint8_t ) ( ~( uint32_t ) ucMaxPriorityValue ) ) == 0U ); /* Calculate the maximum acceptable priority group value for the number * of bits read back. */ - while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE ) { ulImplementedPrioBits++; @@ -1635,16 +1717,14 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */ * register. */ ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT; ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK; - - /* Restore the clobbered interrupt priority register to its original - * value. */ - portNVIC_SHPR2_REG = ulOriginalPriority; } - #endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) ) */ + #endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */ - /* Make PendSV, CallSV and SysTick the same priority as the kernel. */ + /* Make PendSV and SysTick the lowest priority interrupts, and make SVCall + * the highest priority. */ portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI; portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI; + portNVIC_SHPR2_REG = 0; #if ( configENABLE_MPU == 1 ) { @@ -1701,6 +1781,7 @@ void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */ int32_t lIndex = 0; #if defined( __ARMCC_VERSION ) + /* Declaration when these variable are defined in code instead of being * exported from linker scripts. */ extern uint32_t * __privileged_sram_start__; @@ -1886,7 +1967,7 @@ BaseType_t xPortIsInsideInterrupt( void ) } /*-----------------------------------------------------------*/ -#if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) ) +#if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) void vPortValidateInterruptPriority( void ) { @@ -1944,7 +2025,7 @@ BaseType_t xPortIsInsideInterrupt( void ) configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue ); } -#endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) ) */ +#endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */ /*-----------------------------------------------------------*/ #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) diff --git a/Source/portable/GCC/ARM_CM23/non_secure/portasm.c b/Source/portable/GCC/ARM_CM23/non_secure/portasm.c index b23defe79..8b62c201c 100644 --- a/Source/portable/GCC/ARM_CM23/non_secure/portasm.c +++ b/Source/portable/GCC/ARM_CM23/non_secure/portasm.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -112,7 +112,6 @@ " ldmia r2!, {r0, r3-r6} \n" /* r0 = xSecureContext, r3 = original PSP, r4 = PSPLIM, r5 = CONTROL, r6 = LR. */ " subs r2, #20 \n" " msr psp, r3 \n" - " msr psplim, r4 \n" " msr control, r5 \n" " mov lr, r6 \n" " ldr r4, xSecureContextConst2 \n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */ @@ -163,7 +162,6 @@ " ldm r0!, {r1-r3} \n" /* Read from stack - r1 = xSecureContext, r2 = PSPLIM and r3 = EXC_RETURN. */ " ldr r4, xSecureContextConst2 \n" " str r1, [r4] \n" /* Set xSecureContext to this task's value for the same. */ - " msr psplim, r2 \n" /* Set this task's PSPLIM value. */ " movs r1, #2 \n" /* r1 = 2. */ " msr CONTROL, r1 \n" /* Switch to use PSP in the thread mode. */ " adds r0, #32 \n" /* Discard everything up to r0. */ @@ -327,7 +325,7 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att " \n" " save_special_regs: \n" " mrs r3, psp \n" /* r3 = PSP. */ - " mrs r4, psplim \n" /* r4 = PSPLIM. */ + " movs r4, #0 \n" /* r4 = 0. 0 is stored in the PSPLIM slot. */ " mrs r5, control \n" /* r5 = CONTROL. */ " mov r6, lr \n" /* r6 = LR. */ " stmia r2!, {r0, r3-r6} \n" /* Store xSecureContext, original PSP (after hardware has saved context), PSPLIM, CONTROL and LR. */ @@ -395,7 +393,6 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att " ldmia r2!, {r0, r3-r6} \n" /* r0 = xSecureContext, r3 = original PSP, r4 = PSPLIM, r5 = CONTROL, r6 = LR. */ " subs r2, #20 \n" " msr psp, r3 \n" - " msr psplim, r4 \n" " msr control, r5 \n" " mov lr, r6 \n" " ldr r4, xSecureContextConst \n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */ @@ -470,7 +467,7 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att " ldr r1, [r3] \n" /* Read pxCurrentTCB. */ " subs r2, r2, #12 \n" /* Make space for xSecureContext, PSPLIM and LR on the stack. */ " str r2, [r1] \n" /* Save the new top of stack in TCB. */ - " mrs r1, psplim \n" /* r1 = PSPLIM. */ + " movs r1, #0 \n" /* r1 = 0. 0 is stored in the PSPLIM slot. */ " mov r3, lr \n" /* r3 = LR/EXC_RETURN. */ " stmia r2!, {r0, r1, r3} \n" /* Store xSecureContext, PSPLIM and LR on the stack. */ " b select_next_task \n" @@ -480,7 +477,7 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att " ldr r1, [r3] \n" /* Read pxCurrentTCB. */ " subs r2, r2, #44 \n" /* Make space for xSecureContext, PSPLIM, LR and the remaining registers on the stack. */ " str r2, [r1] \n" /* Save the new top of stack in TCB. */ - " mrs r1, psplim \n" /* r1 = PSPLIM. */ + " movs r1, #0 \n" /* r1 = 0. 0 is stored in the PSPLIM slot. */ " mov r3, lr \n" /* r3 = LR/EXC_RETURN. */ " stmia r2!, {r0, r1, r3-r7} \n" /* Store xSecureContext, PSPLIM, LR and the low registers that are not saved automatically. */ " mov r4, r8 \n" /* r4 = r8. */ @@ -499,7 +496,6 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att " ldr r2, [r1] \n" /* The first item in pxCurrentTCB is the task top of stack. r2 now points to the top of stack. */ " \n" " ldmia r2!, {r0, r1, r4} \n" /* Read from stack - r0 = xSecureContext, r1 = PSPLIM and r4 = LR. */ - " msr psplim, r1 \n" /* Restore the PSPLIM register value for the task. */ " mov lr, r4 \n" /* LR = r4. */ " ldr r3, xSecureContextConst \n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */ " str r0, [r3] \n" /* Restore the task's xSecureContext. */ diff --git a/Source/portable/GCC/ARM_CM23/non_secure/portasm.h b/Source/portable/GCC/ARM_CM23/non_secure/portasm.h index f64ceb525..c6d2ebd58 100644 --- a/Source/portable/GCC/ARM_CM23/non_secure/portasm.h +++ b/Source/portable/GCC/ARM_CM23/non_secure/portasm.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/Source/portable/GCC/ARM_CM23/non_secure/portmacro.h b/Source/portable/GCC/ARM_CM23/non_secure/portmacro.h index d8dab9285..8034aa3a7 100644 --- a/Source/portable/GCC/ARM_CM23/non_secure/portmacro.h +++ b/Source/portable/GCC/ARM_CM23/non_secure/portmacro.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -48,9 +48,9 @@ /** * Architecture specifics. */ -#define portARCH_NAME "Cortex-M23" -#define portHAS_BASEPRI 0 -#define portDONT_DISCARD __attribute__( ( used ) ) +#define portARCH_NAME "Cortex-M23" +#define portHAS_ARMV8M_MAIN_EXTENSION 0 +#define portDONT_DISCARD __attribute__( ( used ) ) /*-----------------------------------------------------------*/ /* ARMv8-M common port configurations. */ diff --git a/Source/portable/GCC/ARM_CM23/non_secure/portmacrocommon.h b/Source/portable/GCC/ARM_CM23/non_secure/portmacrocommon.h index 6f666da22..33f21d85b 100644 --- a/Source/portable/GCC/ARM_CM23/non_secure/portmacrocommon.h +++ b/Source/portable/GCC/ARM_CM23/non_secure/portmacrocommon.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -117,7 +117,7 @@ extern uint32_t ulSetInterruptMask( void ) /* __attribute__(( naked )) PRIVILEGE extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */; #if ( configENABLE_TRUSTZONE == 1 ) - extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize ); /* __attribute__ (( naked )) */ + extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize ); /* __attribute__ (( naked )) */ extern void vPortFreeSecureContext( uint32_t * pulTCB ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */; #endif /* configENABLE_TRUSTZONE */ @@ -188,13 +188,13 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P #if ( configENABLE_MPU == 1 ) - /** - * @brief Settings to define an MPU region. - */ +/** + * @brief Settings to define an MPU region. + */ typedef struct MPURegionSettings { - uint32_t ulRBAR; /**< RBAR for the region. */ - uint32_t ulRLAR; /**< RLAR for the region. */ + uint32_t ulRBAR; /**< RBAR for the region. */ + uint32_t ulRLAR; /**< RLAR for the region. */ } MPURegionSettings_t; #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) @@ -203,9 +203,9 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P #error configSYSTEM_CALL_STACK_SIZE must be defined to the desired size of the system call stack in words for using MPU wrappers v2. #endif - /** - * @brief System call stack. - */ +/** + * @brief System call stack. + */ typedef struct SYSTEM_CALL_STACK_INFO { uint32_t ulSystemCallStackBuffer[ configSYSTEM_CALL_STACK_SIZE ]; @@ -218,74 +218,74 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P #endif /* configUSE_MPU_WRAPPERS_V1 == 0 */ - /** - * @brief MPU settings as stored in the TCB. - */ +/** + * @brief MPU settings as stored in the TCB. + */ #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) - #if( configENABLE_TRUSTZONE == 1 ) + #if ( configENABLE_TRUSTZONE == 1 ) - /* - * +-----------+---------------+----------+-----------------+------------------------------+-----+ - * | s16-s31 | s0-s15, FPSCR | r4-r11 | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, | | - * | | | | PC, xPSR | CONTROL, EXC_RETURN | | - * +-----------+---------------+----------+-----------------+------------------------------+-----+ - * - * <-----------><--------------><---------><----------------><-----------------------------><----> - * 16 16 8 8 5 1 - */ - #define MAX_CONTEXT_SIZE 54 +/* + * +-----------+---------------+----------+-----------------+------------------------------+-----+ + * | s16-s31 | s0-s15, FPSCR | r4-r11 | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, | | + * | | | | PC, xPSR | CONTROL, EXC_RETURN | | + * +-----------+---------------+----------+-----------------+------------------------------+-----+ + * + * <-----------><--------------><---------><----------------><-----------------------------><----> + * 16 16 8 8 5 1 + */ + #define MAX_CONTEXT_SIZE 54 #else /* #if( configENABLE_TRUSTZONE == 1 ) */ - /* - * +-----------+---------------+----------+-----------------+----------------------+-----+ - * | s16-s31 | s0-s15, FPSCR | r4-r11 | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL | | - * | | | | PC, xPSR | EXC_RETURN | | - * +-----------+---------------+----------+-----------------+----------------------+-----+ - * - * <-----------><--------------><---------><----------------><---------------------><----> - * 16 16 8 8 4 1 - */ - #define MAX_CONTEXT_SIZE 53 +/* + * +-----------+---------------+----------+-----------------+----------------------+-----+ + * | s16-s31 | s0-s15, FPSCR | r4-r11 | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL | | + * | | | | PC, xPSR | EXC_RETURN | | + * +-----------+---------------+----------+-----------------+----------------------+-----+ + * + * <-----------><--------------><---------><----------------><---------------------><----> + * 16 16 8 8 4 1 + */ + #define MAX_CONTEXT_SIZE 53 #endif /* #if( configENABLE_TRUSTZONE == 1 ) */ #else /* #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */ - #if( configENABLE_TRUSTZONE == 1 ) + #if ( configENABLE_TRUSTZONE == 1 ) - /* - * +----------+-----------------+------------------------------+-----+ - * | r4-r11 | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, | | - * | | PC, xPSR | CONTROL, EXC_RETURN | | - * +----------+-----------------+------------------------------+-----+ - * - * <---------><----------------><------------------------------><----> - * 8 8 5 1 - */ - #define MAX_CONTEXT_SIZE 22 +/* + * +----------+-----------------+------------------------------+-----+ + * | r4-r11 | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, | | + * | | PC, xPSR | CONTROL, EXC_RETURN | | + * +----------+-----------------+------------------------------+-----+ + * + * <---------><----------------><------------------------------><----> + * 8 8 5 1 + */ + #define MAX_CONTEXT_SIZE 22 #else /* #if( configENABLE_TRUSTZONE == 1 ) */ - /* - * +----------+-----------------+----------------------+-----+ - * | r4-r11 | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL | | - * | | PC, xPSR | EXC_RETURN | | - * +----------+-----------------+----------------------+-----+ - * - * <---------><----------------><----------------------><----> - * 8 8 4 1 - */ - #define MAX_CONTEXT_SIZE 21 +/* + * +----------+-----------------+----------------------+-----+ + * | r4-r11 | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL | | + * | | PC, xPSR | EXC_RETURN | | + * +----------+-----------------+----------------------+-----+ + * + * <---------><----------------><----------------------><----> + * 8 8 4 1 + */ + #define MAX_CONTEXT_SIZE 21 #endif /* #if( configENABLE_TRUSTZONE == 1 ) */ #endif /* #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */ - /* Flags used for xMPU_SETTINGS.ulTaskFlags member. */ - #define portSTACK_FRAME_HAS_PADDING_FLAG ( 1UL << 0UL ) - #define portTASK_IS_PRIVILEGED_FLAG ( 1UL << 1UL ) +/* Flags used for xMPU_SETTINGS.ulTaskFlags member. */ + #define portSTACK_FRAME_HAS_PADDING_FLAG ( 1UL << 0UL ) + #define portTASK_IS_PRIVILEGED_FLAG ( 1UL << 1UL ) /* Size of an Access Control List (ACL) entry in bits. */ #define portACL_ENTRY_SIZE_BITS ( 32U ) @@ -313,7 +313,7 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P * system calls. */ #ifdef configASSERT - #if ( portHAS_BASEPRI == 1 ) + #if ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) void vPortValidateInterruptPriority( void ); #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() vPortValidateInterruptPriority() #endif @@ -333,12 +333,29 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P /** * @brief Scheduler utilities. */ -#define portYIELD() vPortYield() +#if ( configENABLE_MPU == 1 ) + #define portYIELD() __asm volatile ( "svc %0" ::"i" ( portSVC_YIELD ) : "memory" ) + #define portYIELD_WITHIN_API() vPortYield() +#else + #define portYIELD() vPortYield() + #define portYIELD_WITHIN_API() vPortYield() +#endif + #define portNVIC_INT_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed04 ) ) #define portNVIC_PENDSVSET_BIT ( 1UL << 28UL ) -#define portEND_SWITCHING_ISR( xSwitchRequired ) \ - do { if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; } \ - while( 0 ) +#define portEND_SWITCHING_ISR( xSwitchRequired ) \ + do \ + { \ + if( xSwitchRequired ) \ + { \ + traceISR_EXIT_TO_SCHEDULER(); \ + portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; \ + } \ + else \ + { \ + traceISR_EXIT(); \ + } \ + } while( 0 ) #define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x ) /*-----------------------------------------------------------*/ @@ -424,12 +441,12 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P extern BaseType_t xPortIsTaskPrivileged( void ); - /** - * @brief Checks whether or not the calling task is privileged. - * - * @return pdTRUE if the calling task is privileged, pdFALSE otherwise. - */ - #define portIS_TASK_PRIVILEGED() xPortIsTaskPrivileged() +/** + * @brief Checks whether or not the calling task is privileged. + * + * @return pdTRUE if the calling task is privileged, pdFALSE otherwise. + */ + #define portIS_TASK_PRIVILEGED() xPortIsTaskPrivileged() #endif /* configENABLE_MPU == 1 */ /*-----------------------------------------------------------*/ @@ -440,6 +457,56 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P #define portMEMORY_BARRIER() __asm volatile ( "" ::: "memory" ) /*-----------------------------------------------------------*/ +/* Select correct value of configUSE_PORT_OPTIMISED_TASK_SELECTION + * based on whether or not Mainline extension is implemented. */ +#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION + #if ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) + #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1 + #else + #define configUSE_PORT_OPTIMISED_TASK_SELECTION 0 + #endif +#endif /* #ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION */ + +/** + * @brief Port-optimised task selection. + */ +#if ( configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 ) + +/** + * @brief Count the number of leading zeros in a 32-bit value. + */ + static portFORCE_INLINE uint32_t ulPortCountLeadingZeros( uint32_t ulBitmap ) + { + uint32_t ulReturn; + + __asm volatile ( "clz %0, %1" : "=r" ( ulReturn ) : "r" ( ulBitmap ) : "memory" ); + + return ulReturn; + } + +/* Check the configuration. */ + #if ( configMAX_PRIORITIES > 32 ) + #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 different priorities as tasks that share a priority will time slice. + #endif + + #if ( portHAS_ARMV8M_MAIN_EXTENSION == 0 ) + #error ARMv8-M baseline implementations (such as Cortex-M23) do not support port-optimised task selection. Please set configUSE_PORT_OPTIMISED_TASK_SELECTION to 0 or leave it undefined. + #endif + +/** + * @brief Store/clear the ready priorities in a bit map. + */ + #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) ) + #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) ) + +/** + * @brief Get the priority of the highest-priority task that is ready to execute. + */ + #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - ulPortCountLeadingZeros( ( uxReadyPriorities ) ) ) + +#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */ +/*-----------------------------------------------------------*/ + /* *INDENT-OFF* */ #ifdef __cplusplus } diff --git a/Source/portable/GCC/ARM_CM23/secure/secure_context.c b/Source/portable/GCC/ARM_CM23/secure/secure_context.c index e37dd9672..83b3dbce1 100644 --- a/Source/portable/GCC/ARM_CM23/secure/secure_context.c +++ b/Source/portable/GCC/ARM_CM23/secure/secure_context.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -65,7 +65,7 @@ * @brief Maximum number of secure contexts. */ #ifndef secureconfigMAX_SECURE_CONTEXTS - #define secureconfigMAX_SECURE_CONTEXTS 8UL + #define secureconfigMAX_SECURE_CONTEXTS 8UL #endif /*-----------------------------------------------------------*/ @@ -164,15 +164,15 @@ secureportNON_SECURE_CALLABLE void SecureContext_Init( void ) } #if ( configENABLE_MPU == 1 ) - { - /* Configure thread mode to use PSP and to be unprivileged. */ - secureportSET_CONTROL( securecontextCONTROL_VALUE_UNPRIVILEGED ); - } + { + /* Configure thread mode to use PSP and to be unprivileged. */ + secureportSET_CONTROL( securecontextCONTROL_VALUE_UNPRIVILEGED ); + } #else /* configENABLE_MPU */ - { - /* Configure thread mode to use PSP and to be privileged. */ - secureportSET_CONTROL( securecontextCONTROL_VALUE_PRIVILEGED ); - } + { + /* Configure thread mode to use PSP and to be privileged. */ + secureportSET_CONTROL( securecontextCONTROL_VALUE_PRIVILEGED ); + } #endif /* configENABLE_MPU */ } } @@ -219,16 +219,16 @@ secureportNON_SECURE_CALLABLE void SecureContext_Init( void ) if( pucStackMemory != NULL ) { /* Since stack grows down, the starting point will be the last - * location. Note that this location is next to the last - * allocated byte for stack (excluding the space for seal values) - * because the hardware decrements the stack pointer before - * writing i.e. if stack pointer is 0x2, a push operation will - * decrement the stack pointer to 0x1 and then write at 0x1. */ + * location. Note that this location is next to the last + * allocated byte for stack (excluding the space for seal values) + * because the hardware decrements the stack pointer before + * writing i.e. if stack pointer is 0x2, a push operation will + * decrement the stack pointer to 0x1 and then write at 0x1. */ xSecureContexts[ ulSecureContextIndex ].pucStackStart = pucStackMemory + ulSecureStackSize; /* Seal the created secure process stack. */ - *( uint32_t * )( pucStackMemory + ulSecureStackSize ) = securecontextSTACK_SEAL_VALUE; - *( uint32_t * )( pucStackMemory + ulSecureStackSize + 4 ) = securecontextSTACK_SEAL_VALUE; + *( uint32_t * ) ( pucStackMemory + ulSecureStackSize ) = securecontextSTACK_SEAL_VALUE; + *( uint32_t * ) ( pucStackMemory + ulSecureStackSize + 4 ) = securecontextSTACK_SEAL_VALUE; /* The stack cannot go beyond this location. This value is * programmed in the PSPLIM register on context switch.*/ @@ -237,32 +237,32 @@ secureportNON_SECURE_CALLABLE void SecureContext_Init( void ) xSecureContexts[ ulSecureContextIndex ].pvTaskHandle = pvTaskHandle; #if ( configENABLE_MPU == 1 ) + { + /* Store the correct CONTROL value for the task on the stack. + * This value is programmed in the CONTROL register on + * context switch. */ + pulCurrentStackPointer = ( uint32_t * ) xSecureContexts[ ulSecureContextIndex ].pucStackStart; + pulCurrentStackPointer--; + + if( ulIsTaskPrivileged ) { - /* Store the correct CONTROL value for the task on the stack. - * This value is programmed in the CONTROL register on - * context switch. */ - pulCurrentStackPointer = ( uint32_t * ) xSecureContexts[ ulSecureContextIndex ].pucStackStart; - pulCurrentStackPointer--; - - if( ulIsTaskPrivileged ) - { - *( pulCurrentStackPointer ) = securecontextCONTROL_VALUE_PRIVILEGED; - } - else - { - *( pulCurrentStackPointer ) = securecontextCONTROL_VALUE_UNPRIVILEGED; - } - - /* Store the current stack pointer. This value is programmed in - * the PSP register on context switch. */ - xSecureContexts[ ulSecureContextIndex ].pucCurrentStackPointer = ( uint8_t * ) pulCurrentStackPointer; + *( pulCurrentStackPointer ) = securecontextCONTROL_VALUE_PRIVILEGED; } - #else /* configENABLE_MPU */ + else { - /* Current SP is set to the starting of the stack. This - * value programmed in the PSP register on context switch. */ - xSecureContexts[ ulSecureContextIndex ].pucCurrentStackPointer = xSecureContexts[ ulSecureContextIndex ].pucStackStart; + *( pulCurrentStackPointer ) = securecontextCONTROL_VALUE_UNPRIVILEGED; } + + /* Store the current stack pointer. This value is programmed in + * the PSP register on context switch. */ + xSecureContexts[ ulSecureContextIndex ].pucCurrentStackPointer = ( uint8_t * ) pulCurrentStackPointer; + } + #else /* configENABLE_MPU */ + { + /* Current SP is set to the starting of the stack. This + * value programmed in the PSP register on context switch. */ + xSecureContexts[ ulSecureContextIndex ].pucCurrentStackPointer = xSecureContexts[ ulSecureContextIndex ].pucStackStart; + } #endif /* configENABLE_MPU */ /* Ensure to never return 0 as a valid context handle. */ @@ -275,7 +275,8 @@ secureportNON_SECURE_CALLABLE void SecureContext_Init( void ) } /*-----------------------------------------------------------*/ -secureportNON_SECURE_CALLABLE void SecureContext_FreeContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle ) +secureportNON_SECURE_CALLABLE void SecureContext_FreeContext( SecureContextHandle_t xSecureContextHandle, + void * pvTaskHandle ) { uint32_t ulIPSR, ulSecureContextIndex; @@ -306,7 +307,8 @@ secureportNON_SECURE_CALLABLE void SecureContext_FreeContext( SecureContextHandl } /*-----------------------------------------------------------*/ -secureportNON_SECURE_CALLABLE void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle ) +secureportNON_SECURE_CALLABLE void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle, + void * pvTaskHandle ) { uint8_t * pucStackLimit; uint32_t ulSecureContextIndex; @@ -328,7 +330,8 @@ secureportNON_SECURE_CALLABLE void SecureContext_LoadContext( SecureContextHandl } /*-----------------------------------------------------------*/ -secureportNON_SECURE_CALLABLE void SecureContext_SaveContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle ) +secureportNON_SECURE_CALLABLE void SecureContext_SaveContext( SecureContextHandle_t xSecureContextHandle, + void * pvTaskHandle ) { uint8_t * pucStackLimit; uint32_t ulSecureContextIndex; diff --git a/Source/portable/GCC/ARM_CM23/secure/secure_context.h b/Source/portable/GCC/ARM_CM23/secure/secure_context.h index 2220ea646..40fdc276d 100644 --- a/Source/portable/GCC/ARM_CM23/secure/secure_context.h +++ b/Source/portable/GCC/ARM_CM23/secure/secure_context.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -38,12 +38,12 @@ /** * @brief PSP value when no secure context is loaded. */ -#define securecontextNO_STACK 0x0 +#define securecontextNO_STACK 0x0 /** * @brief Invalid context ID. */ -#define securecontextINVALID_CONTEXT_ID 0UL +#define securecontextINVALID_CONTEXT_ID 0UL /*-----------------------------------------------------------*/ /** @@ -108,7 +108,8 @@ void SecureContext_Init( void ); * @param[in] xSecureContextHandle Context handle corresponding to the * context to be freed. */ -void SecureContext_FreeContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle ); +void SecureContext_FreeContext( SecureContextHandle_t xSecureContextHandle, + void * pvTaskHandle ); /** * @brief Loads the given context. @@ -119,7 +120,8 @@ void SecureContext_FreeContext( SecureContextHandle_t xSecureContextHandle, void * @param[in] xSecureContextHandle Context handle corresponding to the context * to be loaded. */ -void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle ); +void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle, + void * pvTaskHandle ); /** * @brief Saves the given context. @@ -130,6 +132,7 @@ void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle, void * @param[in] xSecureContextHandle Context handle corresponding to the context * to be saved. */ -void SecureContext_SaveContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle ); +void SecureContext_SaveContext( SecureContextHandle_t xSecureContextHandle, + void * pvTaskHandle ); #endif /* __SECURE_CONTEXT_H__ */ diff --git a/Source/portable/GCC/ARM_CM23/secure/secure_context_port.c b/Source/portable/GCC/ARM_CM23/secure/secure_context_port.c index ce3534010..dbedd29eb 100644 --- a/Source/portable/GCC/ARM_CM23/secure/secure_context_port.c +++ b/Source/portable/GCC/ARM_CM23/secure/secure_context_port.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/Source/portable/GCC/ARM_CM23/secure/secure_heap.c b/Source/portable/GCC/ARM_CM23/secure/secure_heap.c index 19f7c2354..d9789404b 100644 --- a/Source/portable/GCC/ARM_CM23/secure/secure_heap.c +++ b/Source/portable/GCC/ARM_CM23/secure/secure_heap.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -62,6 +62,22 @@ /* Assumes 8bit bytes! */ #define secureheapBITS_PER_BYTE ( ( size_t ) 8 ) + +/* Max value that fits in a size_t type. */ +#define secureheapSIZE_MAX ( ~( ( size_t ) 0 ) ) + +/* Check if adding a and b will result in overflow. */ +#define secureheapADD_WILL_OVERFLOW( a, b ) ( ( a ) > ( secureheapSIZE_MAX - ( b ) ) ) + +/* MSB of the xBlockSize member of an BlockLink_t structure is used to track + * the allocation status of a block. When MSB of the xBlockSize member of + * an BlockLink_t structure is set then the block belongs to the application. + * When the bit is free the block is still part of the free heap space. */ +#define secureheapBLOCK_ALLOCATED_BITMASK ( ( ( size_t ) 1 ) << ( ( sizeof( size_t ) * secureheapBITS_PER_BYTE ) - 1 ) ) +#define secureheapBLOCK_SIZE_IS_VALID( xBlockSize ) ( ( ( xBlockSize ) & secureheapBLOCK_ALLOCATED_BITMASK ) == 0 ) +#define secureheapBLOCK_IS_ALLOCATED( pxBlock ) ( ( ( pxBlock->xBlockSize ) & secureheapBLOCK_ALLOCATED_BITMASK ) != 0 ) +#define secureheapALLOCATE_BLOCK( pxBlock ) ( ( pxBlock->xBlockSize ) |= secureheapBLOCK_ALLOCATED_BITMASK ) +#define secureheapFREE_BLOCK( pxBlock ) ( ( pxBlock->xBlockSize ) &= ~secureheapBLOCK_ALLOCATED_BITMASK ) /*-----------------------------------------------------------*/ /* Allocate the memory for the heap. */ @@ -123,14 +139,6 @@ static BlockLink_t * pxEnd = NULL; static size_t xFreeBytesRemaining = 0U; static size_t xMinimumEverFreeBytesRemaining = 0U; -/** - * @brief Gets set to the top bit of an size_t type. - * - * When this bit in the xBlockSize member of an BlockLink_t structure is set - * then the block belongs to the application. When the bit is free the block is - * still part of the free heap space. - */ -static size_t xBlockAllocatedBit = 0; /*-----------------------------------------------------------*/ static void prvHeapInit( void ) @@ -175,9 +183,6 @@ static void prvHeapInit( void ) /* Only one block exists - and it covers the entire usable heap space. */ xMinimumEverFreeBytesRemaining = pxFirstFreeBlock->xBlockSize; xFreeBytesRemaining = pxFirstFreeBlock->xBlockSize; - - /* Work out the position of the top bit in a size_t variable. */ - xBlockAllocatedBit = ( ( size_t ) 1 ) << ( ( sizeof( size_t ) * secureheapBITS_PER_BYTE ) - 1 ); } /*-----------------------------------------------------------*/ @@ -250,6 +255,7 @@ void * pvPortMalloc( size_t xWantedSize ) BlockLink_t * pxPreviousBlock; BlockLink_t * pxNewBlockLink; void * pvReturn = NULL; + size_t xAdditionalRequiredSize; /* If this is the first call to malloc then the heap will require * initialisation to setup the list of free blocks. */ @@ -262,25 +268,29 @@ void * pvPortMalloc( size_t xWantedSize ) mtCOVERAGE_TEST_MARKER(); } - /* Check the requested block size is not so large that the top bit is set. - * The top bit of the block size member of the BlockLink_t structure is used - * to determine who owns the block - the application or the kernel, so it - * must be free. */ - if( ( xWantedSize & xBlockAllocatedBit ) == 0 ) + if( xWantedSize > 0 ) { - /* The wanted size is increased so it can contain a BlockLink_t + /* The wanted size must be increased so it can contain a BlockLink_t * structure in addition to the requested amount of bytes. */ - if( xWantedSize > 0 ) + if( secureheapADD_WILL_OVERFLOW( xWantedSize, xHeapStructSize ) == 0 ) { xWantedSize += xHeapStructSize; - /* Ensure that blocks are always aligned to the required number of - * bytes. */ + /* Ensure that blocks are always aligned to the required number + * of bytes. */ if( ( xWantedSize & secureportBYTE_ALIGNMENT_MASK ) != 0x00 ) { /* Byte alignment required. */ - xWantedSize += ( secureportBYTE_ALIGNMENT - ( xWantedSize & secureportBYTE_ALIGNMENT_MASK ) ); - secureportASSERT( ( xWantedSize & secureportBYTE_ALIGNMENT_MASK ) == 0 ); + xAdditionalRequiredSize = secureportBYTE_ALIGNMENT - ( xWantedSize & secureportBYTE_ALIGNMENT_MASK ); + + if( secureheapADD_WILL_OVERFLOW( xWantedSize, xAdditionalRequiredSize ) == 0 ) + { + xWantedSize += xAdditionalRequiredSize; + } + else + { + xWantedSize = 0; + } } else { @@ -289,9 +299,20 @@ void * pvPortMalloc( size_t xWantedSize ) } else { - mtCOVERAGE_TEST_MARKER(); + xWantedSize = 0; } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + /* Check the requested block size is not so large that the top bit is set. + * The top bit of the block size member of the BlockLink_t structure is used + * to determine who owns the block - the application or the kernel, so it + * must be free. */ + if( secureheapBLOCK_SIZE_IS_VALID( xWantedSize ) != 0 ) + { if( ( xWantedSize > 0 ) && ( xWantedSize <= xFreeBytesRemaining ) ) { /* Traverse the list from the start (lowest address) block until @@ -334,7 +355,8 @@ void * pvPortMalloc( size_t xWantedSize ) pxBlock->xBlockSize = xWantedSize; /* Insert the new block into the list of free blocks. */ - prvInsertBlockIntoFreeList( pxNewBlockLink ); + pxNewBlockLink->pxNextFreeBlock = pxPreviousBlock->pxNextFreeBlock; + pxPreviousBlock->pxNextFreeBlock = pxNewBlockLink; } else { @@ -354,7 +376,7 @@ void * pvPortMalloc( size_t xWantedSize ) /* The block is being returned - it is allocated and owned by * the application and has no "next" block. */ - pxBlock->xBlockSize |= xBlockAllocatedBit; + secureheapALLOCATE_BLOCK( pxBlock ); pxBlock->pxNextFreeBlock = NULL; } else @@ -375,17 +397,17 @@ void * pvPortMalloc( size_t xWantedSize ) traceMALLOC( pvReturn, xWantedSize ); #if ( secureconfigUSE_MALLOC_FAILED_HOOK == 1 ) + { + if( pvReturn == NULL ) { - if( pvReturn == NULL ) - { - extern void vApplicationMallocFailedHook( void ); - vApplicationMallocFailedHook(); - } - else - { - mtCOVERAGE_TEST_MARKER(); - } + extern void vApplicationMallocFailedHook( void ); + vApplicationMallocFailedHook(); } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } #endif /* if ( secureconfigUSE_MALLOC_FAILED_HOOK == 1 ) */ secureportASSERT( ( ( ( size_t ) pvReturn ) & ( size_t ) secureportBYTE_ALIGNMENT_MASK ) == 0 ); @@ -408,16 +430,16 @@ void vPortFree( void * pv ) pxLink = ( void * ) puc; /* Check the block is actually allocated. */ - secureportASSERT( ( pxLink->xBlockSize & xBlockAllocatedBit ) != 0 ); + secureportASSERT( secureheapBLOCK_IS_ALLOCATED( pxLink ) != 0 ); secureportASSERT( pxLink->pxNextFreeBlock == NULL ); - if( ( pxLink->xBlockSize & xBlockAllocatedBit ) != 0 ) + if( secureheapBLOCK_IS_ALLOCATED( pxLink ) != 0 ) { if( pxLink->pxNextFreeBlock == NULL ) { /* The block is being returned to the heap - it is no longer * allocated. */ - pxLink->xBlockSize &= ~xBlockAllocatedBit; + secureheapFREE_BLOCK( pxLink ); secureportDISABLE_NON_SECURE_INTERRUPTS(); { diff --git a/Source/portable/GCC/ARM_CM23/secure/secure_heap.h b/Source/portable/GCC/ARM_CM23/secure/secure_heap.h index 75c9cb00b..cf5551046 100644 --- a/Source/portable/GCC/ARM_CM23/secure/secure_heap.h +++ b/Source/portable/GCC/ARM_CM23/secure/secure_heap.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/Source/portable/GCC/ARM_CM23/secure/secure_init.c b/Source/portable/GCC/ARM_CM23/secure/secure_init.c index f93bfce95..66d35eccc 100644 --- a/Source/portable/GCC/ARM_CM23/secure/secure_init.c +++ b/Source/portable/GCC/ARM_CM23/secure/secure_init.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -93,7 +93,7 @@ secureportNON_SECURE_CALLABLE void SecureInit_EnableNSFPUAccess( void ) * permitted. CP11 should be programmed to the same value as CP10. */ *( secureinitNSACR ) |= ( secureinitNSACR_CP10_MASK | secureinitNSACR_CP11_MASK ); - /* LSPENS = 0 ==> LSPEN is writable fron non-secure state. This ensures + /* LSPENS = 0 ==> LSPEN is writable from non-secure state. This ensures * that we can enable/disable lazy stacking in port.c file. */ *( secureinitFPCCR ) &= ~( secureinitFPCCR_LSPENS_MASK ); diff --git a/Source/portable/GCC/ARM_CM23/secure/secure_init.h b/Source/portable/GCC/ARM_CM23/secure/secure_init.h index e6c9da0b4..6404c5cc4 100644 --- a/Source/portable/GCC/ARM_CM23/secure/secure_init.h +++ b/Source/portable/GCC/ARM_CM23/secure/secure_init.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/Source/portable/GCC/ARM_CM23/secure/secure_port_macros.h b/Source/portable/GCC/ARM_CM23/secure/secure_port_macros.h index d7ac5833c..085108cc1 100644 --- a/Source/portable/GCC/ARM_CM23/secure/secure_port_macros.h +++ b/Source/portable/GCC/ARM_CM23/secure/secure_port_macros.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/Source/portable/GCC/ARM_CM23_NTZ/non_secure/mpu_wrappers_v2_asm.c b/Source/portable/GCC/ARM_CM23_NTZ/non_secure/mpu_wrappers_v2_asm.c index b8164a001..451244845 100644 --- a/Source/portable/GCC/ARM_CM23_NTZ/non_secure/mpu_wrappers_v2_asm.c +++ b/Source/portable/GCC/ARM_CM23_NTZ/non_secure/mpu_wrappers_v2_asm.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -376,32 +376,6 @@ } /*-----------------------------------------------------------*/ - char * MPU_pcTaskGetName( TaskHandle_t xTaskToQuery ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; - - char * MPU_pcTaskGetName( TaskHandle_t xTaskToQuery ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ - { - __asm volatile - ( - " .syntax unified \n" - " .extern MPU_pcTaskGetNameImpl \n" - " \n" - " push {r0, r1} \n" - " mrs r0, control \n" - " movs r1, #1 \n" - " tst r0, r1 \n" - " bne MPU_pcTaskGetName_Unpriv \n" - " MPU_pcTaskGetName_Priv: \n" - " pop {r0, r1} \n" - " b MPU_pcTaskGetNameImpl \n" - " MPU_pcTaskGetName_Unpriv: \n" - " pop {r0, r1} \n" - " svc %0 \n" - " \n" - : : "i" ( SYSTEM_CALL_pcTaskGetName ) : "memory" - ); - } -/*-----------------------------------------------------------*/ - #if ( configGENERATE_RUN_TIME_STATS == 1 ) configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetRunTimeCounter( const TaskHandle_t xTask ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; @@ -1562,31 +1536,28 @@ #if ( configUSE_TIMERS == 1 ) - BaseType_t MPU_xTimerGenericCommandEntry( const xTimerGenericCommandParams_t * pxParams ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + BaseType_t MPU_xTimerGenericCommandFromTaskEntry( const xTimerGenericCommandFromTaskParams_t * pxParams ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; - BaseType_t MPU_xTimerGenericCommandEntry( const xTimerGenericCommandParams_t * pxParams ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + BaseType_t MPU_xTimerGenericCommandFromTaskEntry( const xTimerGenericCommandFromTaskParams_t * pxParams ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ { __asm volatile ( - " .syntax unified \n" - " .extern MPU_xTimerGenericCommandPrivImpl \n" - " \n" - " push {r0, r1} \n" - " mrs r0, ipsr \n" - " cmp r0, #0 \n" - " bne MPU_xTimerGenericCommand_Priv \n" - " mrs r0, control \n" - " movs r1, #1 \n" - " tst r0, r1 \n" - " beq MPU_xTimerGenericCommand_Priv \n" - " MPU_xTimerGenericCommand_Unpriv: \n" - " pop {r0, r1} \n" - " svc %0 \n" - " MPU_xTimerGenericCommand_Priv: \n" - " pop {r0, r1} \n" - " b MPU_xTimerGenericCommandPrivImpl \n" - " \n" - : : "i" ( SYSTEM_CALL_xTimerGenericCommand ) : "memory" + " .syntax unified \n" + " .extern MPU_xTimerGenericCommandFromTaskImpl \n" + " \n" + " push {r0, r1} \n" + " mrs r0, control \n" + " movs r1, #1 \n" + " tst r0, r1 \n" + " bne MPU_xTimerGenericCommandFromTask_Unpriv \n" + " MPU_xTimerGenericCommandFromTask_Priv: \n" + " pop {r0, r1} \n" + " b MPU_xTimerGenericCommandFromTaskImpl \n" + " MPU_xTimerGenericCommandFromTask_Unpriv: \n" + " pop {r0, r1} \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xTimerGenericCommandFromTask ) : "memory" ); } diff --git a/Source/portable/GCC/ARM_CM23_NTZ/non_secure/port.c b/Source/portable/GCC/ARM_CM23_NTZ/non_secure/port.c index 9712ac353..230fe5fc2 100644 --- a/Source/portable/GCC/ARM_CM23_NTZ/non_secure/port.c +++ b/Source/portable/GCC/ARM_CM23_NTZ/non_secure/port.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -68,6 +68,22 @@ #if ( ( configRUN_FREERTOS_SECURE_ONLY == 1 ) && ( configENABLE_TRUSTZONE == 1 ) ) #error TrustZone needs to be disabled in order to run FreeRTOS on the Secure Side. #endif + +/** + * Cortex-M23 does not have non-secure PSPLIM. We should use PSPLIM on Cortex-M23 + * only when FreeRTOS runs on secure side. + */ +#if ( ( portHAS_ARMV8M_MAIN_EXTENSION == 0 ) && ( configRUN_FREERTOS_SECURE_ONLY == 0 ) ) + #define portUSE_PSPLIM_REGISTER 0 +#else + #define portUSE_PSPLIM_REGISTER 1 +#endif +/*-----------------------------------------------------------*/ + +/** + * @brief Prototype of all Interrupt Service Routines (ISRs). + */ +typedef void ( * portISR_t )( void ); /*-----------------------------------------------------------*/ /** @@ -91,10 +107,18 @@ /** * @brief Constants required to manipulate the SCB. */ -#define portSCB_SYS_HANDLER_CTRL_STATE_REG ( *( volatile uint32_t * ) 0xe000ed24 ) +#define portSCB_VTOR_REG ( *( ( portISR_t ** ) 0xe000ed08 ) ) +#define portSCB_SYS_HANDLER_CTRL_STATE_REG ( *( ( volatile uint32_t * ) 0xe000ed24 ) ) #define portSCB_MEM_FAULT_ENABLE_BIT ( 1UL << 16UL ) /*-----------------------------------------------------------*/ +/** + * @brief Constants used to check the installation of the FreeRTOS interrupt handlers. + */ +#define portVECTOR_INDEX_SVC ( 11 ) +#define portVECTOR_INDEX_PENDSV ( 14 ) +/*-----------------------------------------------------------*/ + /** * @brief Constants required to check the validity of an interrupt priority. */ @@ -111,8 +135,8 @@ /** * @brief Constants used during system call enter and exit. */ -#define portPSR_STACK_PADDING_MASK ( 1UL << 9UL ) -#define portEXC_RETURN_STACK_FRAME_TYPE_MASK ( 1UL << 4UL ) +#define portPSR_STACK_PADDING_MASK ( 1UL << 9UL ) +#define portEXC_RETURN_STACK_FRAME_TYPE_MASK ( 1UL << 4UL ) /*-----------------------------------------------------------*/ /** @@ -134,81 +158,81 @@ /** * @brief Offsets in the stack to the parameters when inside the SVC handler. */ -#define portOFFSET_TO_LR ( 5 ) -#define portOFFSET_TO_PC ( 6 ) -#define portOFFSET_TO_PSR ( 7 ) +#define portOFFSET_TO_LR ( 5 ) +#define portOFFSET_TO_PC ( 6 ) +#define portOFFSET_TO_PSR ( 7 ) /*-----------------------------------------------------------*/ /** * @brief Constants required to manipulate the MPU. */ -#define portMPU_TYPE_REG ( *( ( volatile uint32_t * ) 0xe000ed90 ) ) -#define portMPU_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed94 ) ) -#define portMPU_RNR_REG ( *( ( volatile uint32_t * ) 0xe000ed98 ) ) +#define portMPU_TYPE_REG ( *( ( volatile uint32_t * ) 0xe000ed90 ) ) +#define portMPU_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed94 ) ) +#define portMPU_RNR_REG ( *( ( volatile uint32_t * ) 0xe000ed98 ) ) -#define portMPU_RBAR_REG ( *( ( volatile uint32_t * ) 0xe000ed9c ) ) -#define portMPU_RLAR_REG ( *( ( volatile uint32_t * ) 0xe000eda0 ) ) +#define portMPU_RBAR_REG ( *( ( volatile uint32_t * ) 0xe000ed9c ) ) +#define portMPU_RLAR_REG ( *( ( volatile uint32_t * ) 0xe000eda0 ) ) -#define portMPU_RBAR_A1_REG ( *( ( volatile uint32_t * ) 0xe000eda4 ) ) -#define portMPU_RLAR_A1_REG ( *( ( volatile uint32_t * ) 0xe000eda8 ) ) +#define portMPU_RBAR_A1_REG ( *( ( volatile uint32_t * ) 0xe000eda4 ) ) +#define portMPU_RLAR_A1_REG ( *( ( volatile uint32_t * ) 0xe000eda8 ) ) -#define portMPU_RBAR_A2_REG ( *( ( volatile uint32_t * ) 0xe000edac ) ) -#define portMPU_RLAR_A2_REG ( *( ( volatile uint32_t * ) 0xe000edb0 ) ) +#define portMPU_RBAR_A2_REG ( *( ( volatile uint32_t * ) 0xe000edac ) ) +#define portMPU_RLAR_A2_REG ( *( ( volatile uint32_t * ) 0xe000edb0 ) ) -#define portMPU_RBAR_A3_REG ( *( ( volatile uint32_t * ) 0xe000edb4 ) ) -#define portMPU_RLAR_A3_REG ( *( ( volatile uint32_t * ) 0xe000edb8 ) ) +#define portMPU_RBAR_A3_REG ( *( ( volatile uint32_t * ) 0xe000edb4 ) ) +#define portMPU_RLAR_A3_REG ( *( ( volatile uint32_t * ) 0xe000edb8 ) ) -#define portMPU_MAIR0_REG ( *( ( volatile uint32_t * ) 0xe000edc0 ) ) -#define portMPU_MAIR1_REG ( *( ( volatile uint32_t * ) 0xe000edc4 ) ) +#define portMPU_MAIR0_REG ( *( ( volatile uint32_t * ) 0xe000edc0 ) ) +#define portMPU_MAIR1_REG ( *( ( volatile uint32_t * ) 0xe000edc4 ) ) -#define portMPU_RBAR_ADDRESS_MASK ( 0xffffffe0 ) /* Must be 32-byte aligned. */ -#define portMPU_RLAR_ADDRESS_MASK ( 0xffffffe0 ) /* Must be 32-byte aligned. */ +#define portMPU_RBAR_ADDRESS_MASK ( 0xffffffe0 ) /* Must be 32-byte aligned. */ +#define portMPU_RLAR_ADDRESS_MASK ( 0xffffffe0 ) /* Must be 32-byte aligned. */ -#define portMPU_RBAR_ACCESS_PERMISSIONS_MASK ( 3UL << 1UL ) +#define portMPU_RBAR_ACCESS_PERMISSIONS_MASK ( 3UL << 1UL ) -#define portMPU_MAIR_ATTR0_POS ( 0UL ) -#define portMPU_MAIR_ATTR0_MASK ( 0x000000ff ) +#define portMPU_MAIR_ATTR0_POS ( 0UL ) +#define portMPU_MAIR_ATTR0_MASK ( 0x000000ff ) -#define portMPU_MAIR_ATTR1_POS ( 8UL ) -#define portMPU_MAIR_ATTR1_MASK ( 0x0000ff00 ) +#define portMPU_MAIR_ATTR1_POS ( 8UL ) +#define portMPU_MAIR_ATTR1_MASK ( 0x0000ff00 ) -#define portMPU_MAIR_ATTR2_POS ( 16UL ) -#define portMPU_MAIR_ATTR2_MASK ( 0x00ff0000 ) +#define portMPU_MAIR_ATTR2_POS ( 16UL ) +#define portMPU_MAIR_ATTR2_MASK ( 0x00ff0000 ) -#define portMPU_MAIR_ATTR3_POS ( 24UL ) -#define portMPU_MAIR_ATTR3_MASK ( 0xff000000 ) +#define portMPU_MAIR_ATTR3_POS ( 24UL ) +#define portMPU_MAIR_ATTR3_MASK ( 0xff000000 ) -#define portMPU_MAIR_ATTR4_POS ( 0UL ) -#define portMPU_MAIR_ATTR4_MASK ( 0x000000ff ) +#define portMPU_MAIR_ATTR4_POS ( 0UL ) +#define portMPU_MAIR_ATTR4_MASK ( 0x000000ff ) -#define portMPU_MAIR_ATTR5_POS ( 8UL ) -#define portMPU_MAIR_ATTR5_MASK ( 0x0000ff00 ) +#define portMPU_MAIR_ATTR5_POS ( 8UL ) +#define portMPU_MAIR_ATTR5_MASK ( 0x0000ff00 ) -#define portMPU_MAIR_ATTR6_POS ( 16UL ) -#define portMPU_MAIR_ATTR6_MASK ( 0x00ff0000 ) +#define portMPU_MAIR_ATTR6_POS ( 16UL ) +#define portMPU_MAIR_ATTR6_MASK ( 0x00ff0000 ) -#define portMPU_MAIR_ATTR7_POS ( 24UL ) -#define portMPU_MAIR_ATTR7_MASK ( 0xff000000 ) +#define portMPU_MAIR_ATTR7_POS ( 24UL ) +#define portMPU_MAIR_ATTR7_MASK ( 0xff000000 ) -#define portMPU_RLAR_ATTR_INDEX0 ( 0UL << 1UL ) -#define portMPU_RLAR_ATTR_INDEX1 ( 1UL << 1UL ) -#define portMPU_RLAR_ATTR_INDEX2 ( 2UL << 1UL ) -#define portMPU_RLAR_ATTR_INDEX3 ( 3UL << 1UL ) -#define portMPU_RLAR_ATTR_INDEX4 ( 4UL << 1UL ) -#define portMPU_RLAR_ATTR_INDEX5 ( 5UL << 1UL ) -#define portMPU_RLAR_ATTR_INDEX6 ( 6UL << 1UL ) -#define portMPU_RLAR_ATTR_INDEX7 ( 7UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX0 ( 0UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX1 ( 1UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX2 ( 2UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX3 ( 3UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX4 ( 4UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX5 ( 5UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX6 ( 6UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX7 ( 7UL << 1UL ) -#define portMPU_RLAR_REGION_ENABLE ( 1UL ) +#define portMPU_RLAR_REGION_ENABLE ( 1UL ) /* Enable privileged access to unmapped region. */ -#define portMPU_PRIV_BACKGROUND_ENABLE_BIT ( 1UL << 2UL ) +#define portMPU_PRIV_BACKGROUND_ENABLE_BIT ( 1UL << 2UL ) /* Enable MPU. */ -#define portMPU_ENABLE_BIT ( 1UL << 0UL ) +#define portMPU_ENABLE_BIT ( 1UL << 0UL ) /* Expected value of the portMPU_TYPE register. */ -#define portEXPECTED_MPU_TYPE_VALUE ( configTOTAL_MPU_REGIONS << 8UL ) +#define portEXPECTED_MPU_TYPE_VALUE ( configTOTAL_MPU_REGIONS << 8UL ) /* Extract first address of the MPU region as encoded in the * RBAR (Region Base Address Register) value. */ @@ -448,13 +472,13 @@ portDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIV #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) - /** - * @brief Sets up the task stack so that upon returning from - * SVC, the task stack is used again. - * - * @param pulSystemCallStack The current SP when the SVC was raised. - * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler. - */ +/** + * @brief Sets up the task stack so that upon returning from + * SVC, the task stack is used again. + * + * @param pulSystemCallStack The current SP when the SVC was raised. + * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler. + */ void vSystemCallExit( uint32_t * pulSystemCallStack, uint32_t ulLR ) PRIVILEGED_FUNCTION; @@ -462,11 +486,11 @@ portDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIV #if ( configENABLE_MPU == 1 ) - /** - * @brief Checks whether or not the calling task is privileged. - * - * @return pdTRUE if the calling task is privileged, pdFALSE otherwise. - */ +/** + * @brief Checks whether or not the calling task is privileged. + * + * @return pdTRUE if the calling task is privileged, pdFALSE otherwise. + */ BaseType_t xPortIsTaskPrivileged( void ) PRIVILEGED_FUNCTION; #endif /* configENABLE_MPU == 1 */ @@ -501,13 +525,13 @@ PRIVILEGED_DATA static volatile uint32_t ulCriticalNesting = 0xaaaaaaaaUL; * FreeRTOS API functions are not called from interrupts that have been assigned * a priority above configMAX_SYSCALL_INTERRUPT_PRIORITY. */ -#if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) ) +#if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) static uint8_t ucMaxSysCallPriority = 0; static uint32_t ulMaxPRIGROUPValue = 0; static const volatile uint8_t * const pcInterruptPriorityRegisters = ( const volatile uint8_t * ) portNVIC_IP_REGISTERS_OFFSET_16; -#endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) ) */ +#endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */ #if ( configUSE_TICKLESS_IDLE == 1 ) @@ -760,8 +784,15 @@ __attribute__( ( weak ) ) void vPortSetupTimerInterrupt( void ) /* PRIVILEGED_FU } #endif /* configUSE_TICKLESS_IDLE */ - /* Stop and reset the SysTick. */ - portNVIC_SYSTICK_CTRL_REG = 0UL; + /* Stop and reset SysTick. + * + * QEMU versions older than 7.0.0 contain a bug which causes an error if we + * enable SysTick without first selecting a valid clock source. We trigger + * the bug if we change clock sources from a clock with a zero clock period + * to one with a nonzero clock period and enable Systick at the same time. + * So we configure the CLKSOURCE bit here, prior to setting the ENABLE bit. + * This workaround avoids the bug in QEMU versions older than 7.0.0. */ + portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT_CONFIG; portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL; /* Configure SysTick to interrupt at the requested rate. */ @@ -819,6 +850,7 @@ static void prvTaskExitError( void ) static void prvSetupMPU( void ) /* PRIVILEGED_FUNCTION */ { #if defined( __ARMCC_VERSION ) + /* Declaration when these variable are defined in code instead of being * exported from linker scripts. */ extern uint32_t * __privileged_functions_start__; @@ -972,13 +1004,19 @@ void SysTick_Handler( void ) /* PRIVILEGED_FUNCTION */ uint32_t ulPreviousMask; ulPreviousMask = portSET_INTERRUPT_MASK_FROM_ISR(); + traceISR_ENTER(); { /* Increment the RTOS tick. */ if( xTaskIncrementTick() != pdFALSE ) { + traceISR_EXIT_TO_SCHEDULER(); /* Pend a context switch. */ portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; } + else + { + traceISR_EXIT(); + } } portCLEAR_INTERRUPT_MASK_FROM_ISR( ulPreviousMask ); } @@ -988,6 +1026,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO { #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) ) #if defined( __ARMCC_VERSION ) + /* Declaration when these variable are defined in code instead of being * exported from linker scripts. */ extern uint32_t * __syscalls_flash_start__; @@ -1083,18 +1122,24 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO vRestoreContextOfFirstTask(); break; - #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) ) - case portSVC_RAISE_PRIVILEGE: + #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) ) + case portSVC_RAISE_PRIVILEGE: - /* Only raise the privilege, if the svc was raised from any of - * the system calls. */ - if( ( ulPC >= ( uint32_t ) __syscalls_flash_start__ ) && - ( ulPC <= ( uint32_t ) __syscalls_flash_end__ ) ) - { - vRaisePrivilege(); - } - break; - #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) */ + /* Only raise the privilege, if the svc was raised from any of + * the system calls. */ + if( ( ulPC >= ( uint32_t ) __syscalls_flash_start__ ) && + ( ulPC <= ( uint32_t ) __syscalls_flash_end__ ) ) + { + vRaisePrivilege(); + } + break; + #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) */ + + #if ( configENABLE_MPU == 1 ) + case portSVC_YIELD: + vPortYield(); + break; + #endif /* configENABLE_MPU == 1 */ default: /* Incorrect SVC call. */ @@ -1154,12 +1199,11 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO { /* Extended frame i.e. FPU in use. */ ulStackFrameSize = 26; - __asm volatile - ( + __asm volatile ( " vpush {s0} \n" /* Trigger lazy stacking. */ " vpop {s0} \n" /* Nullify the affect of the above instruction. */ ::: "memory" - ); + ); } else { @@ -1171,7 +1215,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO { ulStackFrameSize = 8; } - #endif /* if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */ + #endif /* configENABLE_FPU || configENABLE_MVE */ /* Make space on the system call stack for the stack frame. */ pulSystemCallStack = pulSystemCallStack - ulStackFrameSize; @@ -1187,18 +1231,24 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO * point (i.e. the caller of the MPU_). We need to restore it * when we exit from the system call. */ pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry = pulTaskStack[ portOFFSET_TO_LR ]; - /* Store the value of the PSPLIM register before the SVC was raised. * We need to restore it when we exit from the system call. */ - __asm volatile ( "mrs %0, psplim" : "=r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) ); + #if ( portUSE_PSPLIM_REGISTER == 1 ) + { + __asm volatile ( "mrs %0, psplim" : "=r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) ); + } + #endif /* Use the pulSystemCallStack in thread mode. */ __asm volatile ( "msr psp, %0" : : "r" ( pulSystemCallStack ) ); - __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) ); + #if ( portUSE_PSPLIM_REGISTER == 1 ) + { + __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) ); + } + #endif /* Start executing the system call upon returning from this handler. */ pulSystemCallStack[ portOFFSET_TO_PC ] = uxSystemCallImplementations[ ucSystemCallNumber ]; - /* Raise a request to exit from the system call upon finishing the * system call. */ pulSystemCallStack[ portOFFSET_TO_LR ] = ( uint32_t ) vRequestSystemCallExit; @@ -1224,14 +1274,13 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO pulSystemCallStack[ portOFFSET_TO_PSR ] &= ( ~portPSR_STACK_PADDING_MASK ); /* Raise the privilege for the duration of the system call. */ - __asm volatile - ( + __asm volatile ( " mrs r0, control \n" /* Obtain current control value. */ " movs r1, #1 \n" /* r1 = 1. */ " bics r0, r1 \n" /* Clear nPRIV bit. */ " msr control, r0 \n" /* Write back new control value. */ ::: "r0", "r1", "memory" - ); + ); } } @@ -1293,12 +1342,11 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO { /* Extended frame i.e. FPU in use. */ ulStackFrameSize = 26; - __asm volatile - ( + __asm volatile ( " vpush {s0} \n" /* Trigger lazy stacking. */ " vpop {s0} \n" /* Nullify the affect of the above instruction. */ ::: "memory" - ); + ); } else { @@ -1310,7 +1358,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO { ulStackFrameSize = 8; } - #endif /* if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */ + #endif /* configENABLE_FPU || configENABLE_MVE */ /* Make space on the task stack for the stack frame. */ pulTaskStack = pulTaskStack - ulStackFrameSize; @@ -1332,7 +1380,11 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO /* Restore the PSPLIM register to what it was at the time of * system call entry. */ - __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) ); + #if ( portUSE_PSPLIM_REGISTER == 1 ) + { + __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) ); + } + #endif /* If the hardware used padding to force the stack pointer * to be double word aligned, set the stacked xPSR bit[9], @@ -1350,14 +1402,13 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO pxMpuSettings->xSystemCallStackInfo.pulTaskStack = NULL; /* Drop the privilege before returning to the thread mode. */ - __asm volatile - ( + __asm volatile ( " mrs r0, control \n" /* Obtain current control value. */ " movs r1, #1 \n" /* r1 = 1. */ " orrs r0, r1 \n" /* Set nPRIV bit. */ " msr control, r0 \n" /* Write back new control value. */ ::: "r0", "r1", "memory" - ); + ); } } @@ -1410,21 +1461,21 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO xMPUSettings->ulContext[ ulIndex ] = 0x11111111; /* r11. */ ulIndex++; - xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pvParameters; /* r0. */ + xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pvParameters; /* r0. */ ulIndex++; - xMPUSettings->ulContext[ ulIndex ] = 0x01010101; /* r1. */ + xMPUSettings->ulContext[ ulIndex ] = 0x01010101; /* r1. */ ulIndex++; - xMPUSettings->ulContext[ ulIndex ] = 0x02020202; /* r2. */ + xMPUSettings->ulContext[ ulIndex ] = 0x02020202; /* r2. */ ulIndex++; - xMPUSettings->ulContext[ ulIndex ] = 0x03030303; /* r3. */ + xMPUSettings->ulContext[ ulIndex ] = 0x03030303; /* r3. */ ulIndex++; - xMPUSettings->ulContext[ ulIndex ] = 0x12121212; /* r12. */ + xMPUSettings->ulContext[ ulIndex ] = 0x12121212; /* r12. */ ulIndex++; xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portTASK_RETURN_ADDRESS; /* LR. */ ulIndex++; - xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxCode; /* PC. */ + xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxCode; /* PC. */ ulIndex++; - xMPUSettings->ulContext[ ulIndex ] = portINITIAL_XPSR; /* xPSR. */ + xMPUSettings->ulContext[ ulIndex ] = portINITIAL_XPSR; /* xPSR. */ ulIndex++; #if ( configENABLE_TRUSTZONE == 1 ) @@ -1435,8 +1486,9 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO #endif /* configENABLE_TRUSTZONE */ xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) ( pxTopOfStack - 8 ); /* PSP with the hardware saved stack. */ ulIndex++; - xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxEndOfStack; /* PSPLIM. */ + xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxEndOfStack; /* PSPLIM. */ ulIndex++; + if( xRunPrivileged == pdTRUE ) { xMPUSettings->ulTaskFlags |= portTASK_IS_PRIVILEGED_FLAG; @@ -1449,6 +1501,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portINITIAL_CONTROL_UNPRIVILEGED; /* CONTROL. */ ulIndex++; } + xMPUSettings->ulContext[ ulIndex ] = portINITIAL_EXC_RETURN; /* LR (EXC_RETURN). */ ulIndex++; @@ -1483,7 +1536,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO * interrupt. */ #if ( portPRELOAD_REGISTERS == 0 ) { - pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */ + pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */ *pxTopOfStack = portINITIAL_XPSR; /* xPSR. */ pxTopOfStack--; *pxTopOfStack = ( StackType_t ) pxCode; /* PC. */ @@ -1505,7 +1558,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO } #else /* portPRELOAD_REGISTERS */ { - pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */ + pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */ *pxTopOfStack = portINITIAL_XPSR; /* xPSR. */ pxTopOfStack--; *pxTopOfStack = ( StackType_t ) pxCode; /* PC. */ @@ -1540,7 +1593,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO pxTopOfStack--; *pxTopOfStack = portINITIAL_EXC_RETURN; /* EXC_RETURN. */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */ + *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */ #if ( configENABLE_TRUSTZONE == 1 ) { @@ -1559,22 +1612,52 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */ { - #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) ) + /* An application can install FreeRTOS interrupt handlers in one of the + * folllowing ways: + * 1. Direct Routing - Install the functions SVC_Handler and PendSV_Handler + * for SVCall and PendSV interrupts respectively. + * 2. Indirect Routing - Install separate handlers for SVCall and PendSV + * interrupts and route program control from those handlers to + * SVC_Handler and PendSV_Handler functions. + * + * Applications that use Indirect Routing must set + * configCHECK_HANDLER_INSTALLATION to 0 in their FreeRTOSConfig.h. Direct + * routing, which is validated here when configCHECK_HANDLER_INSTALLATION + * is 1, should be preferred when possible. */ + #if ( configCHECK_HANDLER_INSTALLATION == 1 ) + { + const portISR_t * const pxVectorTable = portSCB_VTOR_REG; + + /* Validate that the application has correctly installed the FreeRTOS + * handlers for SVCall and PendSV interrupts. We do not check the + * installation of the SysTick handler because the application may + * choose to drive the RTOS tick using a timer other than the SysTick + * timer by overriding the weak function vPortSetupTimerInterrupt(). + * + * Assertion failures here indicate incorrect installation of the + * FreeRTOS handlers. For help installing the FreeRTOS handlers, see + * https://www.FreeRTOS.org/FAQHelp.html. + * + * Systems with a configurable address for the interrupt vector table + * can also encounter assertion failures or even system faults here if + * VTOR is not set correctly to point to the application's vector table. */ + configASSERT( pxVectorTable[ portVECTOR_INDEX_SVC ] == SVC_Handler ); + configASSERT( pxVectorTable[ portVECTOR_INDEX_PENDSV ] == PendSV_Handler ); + } + #endif /* configCHECK_HANDLER_INSTALLATION */ + + #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) { - volatile uint32_t ulOriginalPriority; volatile uint32_t ulImplementedPrioBits = 0; volatile uint8_t ucMaxPriorityValue; /* Determine the maximum priority from which ISR safe FreeRTOS API - * functions can be called. ISR safe functions are those that end in - * "FromISR". FreeRTOS maintains separate thread and ISR API functions to + * functions can be called. ISR safe functions are those that end in + * "FromISR". FreeRTOS maintains separate thread and ISR API functions to * ensure interrupt entry is as fast and simple as possible. * - * Save the interrupt priority value that is about to be clobbered. */ - ulOriginalPriority = portNVIC_SHPR2_REG; - - /* Determine the number of priority bits available. First write to all - * possible bits. */ + * First, determine the number of priority bits available. Write to all + * possible bits in the priority setting for SVCall. */ portNVIC_SHPR2_REG = 0xFF000000; /* Read the value back to see how many bits stuck. */ @@ -1593,11 +1676,10 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */ /* Check that the bits not implemented in hardware are zero in * configMAX_SYSCALL_INTERRUPT_PRIORITY. */ - configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( ~ucMaxPriorityValue ) ) == 0U ); + configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( uint8_t ) ( ~( uint32_t ) ucMaxPriorityValue ) ) == 0U ); /* Calculate the maximum acceptable priority group value for the number * of bits read back. */ - while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE ) { ulImplementedPrioBits++; @@ -1635,16 +1717,14 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */ * register. */ ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT; ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK; - - /* Restore the clobbered interrupt priority register to its original - * value. */ - portNVIC_SHPR2_REG = ulOriginalPriority; } - #endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) ) */ + #endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */ - /* Make PendSV, CallSV and SysTick the same priority as the kernel. */ + /* Make PendSV and SysTick the lowest priority interrupts, and make SVCall + * the highest priority. */ portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI; portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI; + portNVIC_SHPR2_REG = 0; #if ( configENABLE_MPU == 1 ) { @@ -1701,6 +1781,7 @@ void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */ int32_t lIndex = 0; #if defined( __ARMCC_VERSION ) + /* Declaration when these variable are defined in code instead of being * exported from linker scripts. */ extern uint32_t * __privileged_sram_start__; @@ -1886,7 +1967,7 @@ BaseType_t xPortIsInsideInterrupt( void ) } /*-----------------------------------------------------------*/ -#if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) ) +#if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) void vPortValidateInterruptPriority( void ) { @@ -1944,7 +2025,7 @@ BaseType_t xPortIsInsideInterrupt( void ) configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue ); } -#endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) ) */ +#endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */ /*-----------------------------------------------------------*/ #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) diff --git a/Source/portable/GCC/ARM_CM23_NTZ/non_secure/portasm.c b/Source/portable/GCC/ARM_CM23_NTZ/non_secure/portasm.c index b90da71f3..6c5a74b5c 100644 --- a/Source/portable/GCC/ARM_CM23_NTZ/non_secure/portasm.c +++ b/Source/portable/GCC/ARM_CM23_NTZ/non_secure/portasm.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -112,7 +112,9 @@ " ldmia r1!, {r2-r5} \n" /* r2 = original PSP, r3 = PSPLIM, r4 = CONTROL, r5 = LR. */ " subs r1, #16 \n" " msr psp, r2 \n" - " msr psplim, r3 \n" + #if ( configRUN_FREERTOS_SECURE_ONLY == 1 ) + " msr psplim, r3 \n" + #endif " msr control, r4 \n" " mov lr, r5 \n" " \n" @@ -158,7 +160,9 @@ " ldr r0, [r1] \n" /* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */ " \n" " ldm r0!, {r1-r2} \n" /* Read from stack - r1 = PSPLIM and r2 = EXC_RETURN. */ - " msr psplim, r1 \n" /* Set this task's PSPLIM value. */ + #if ( configRUN_FREERTOS_SECURE_ONLY == 1 ) + " msr psplim, r1 \n" /* Set this task's PSPLIM value. */ + #endif " movs r1, #2 \n" /* r1 = 2. */ " msr CONTROL, r1 \n" /* Switch to use PSP in the thread mode. */ " adds r0, #32 \n" /* Discard everything up to r0. */ @@ -305,7 +309,11 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att " \n" " save_special_regs: \n" " mrs r2, psp \n" /* r2 = PSP. */ - " mrs r3, psplim \n" /* r3 = PSPLIM. */ + #if ( configRUN_FREERTOS_SECURE_ONLY == 1 ) + " mrs r3, psplim \n" /* r3 = PSPLIM. */ + #else + " movs r3, #0 \n" /* r3 = 0. 0 is stored in the PSPLIM slot. */ + #endif " mrs r4, control \n" /* r4 = CONTROL. */ " mov r5, lr \n" /* r5 = LR. */ " stmia r1!, {r2-r5} \n" /* Store original PSP (after hardware has saved context), PSPLIM, CONTROL and LR. */ @@ -373,7 +381,9 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att " ldmia r1!, {r2-r5} \n" /* r2 = original PSP, r3 = PSPLIM, r4 = CONTROL, r5 = LR. */ " subs r1, #16 \n" " msr psp, r2 \n" - " msr psplim, r3 \n" + #if ( configRUN_FREERTOS_SECURE_ONLY == 1 ) + " msr psplim, r3 \n" + #endif " msr control, r4 \n" " mov lr, r5 \n" " \n" @@ -419,7 +429,11 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att " ldr r1, [r2] \n" /* Read pxCurrentTCB. */ " subs r0, r0, #40 \n" /* Make space for PSPLIM, LR and the remaining registers on the stack. */ " str r0, [r1] \n" /* Save the new top of stack in TCB. */ - " mrs r2, psplim \n" /* r2 = PSPLIM. */ + #if ( configRUN_FREERTOS_SECURE_ONLY == 1 ) + " mrs r2, psplim \n" /* r2 = PSPLIM. */ + #else + " movs r2, #0 \n" /* r2 = 0. 0 is stored in the PSPLIM slot. */ + #endif " mov r3, lr \n" /* r3 = LR/EXC_RETURN. */ " stmia r0!, {r2-r7} \n" /* Store on the stack - PSPLIM, LR and low registers that are not automatically saved. */ " mov r4, r8 \n" /* r4 = r8. */ @@ -445,7 +459,9 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att " msr psp, r0 \n" /* Remember the new top of stack for the task. */ " subs r0, r0, #40 \n" /* Move to the starting of the saved context. */ " ldmia r0!, {r2-r7} \n" /* Read from stack - r2 = PSPLIM, r3 = LR and r4-r7 restored. */ - " msr psplim, r2 \n" /* Restore the PSPLIM register value for the task. */ + #if ( configRUN_FREERTOS_SECURE_ONLY == 1 ) + " msr psplim, r2 \n" /* Restore the PSPLIM register value for the task. */ + #endif " bx r3 \n" " \n" " .align 4 \n" diff --git a/Source/portable/GCC/ARM_CM23_NTZ/non_secure/portasm.h b/Source/portable/GCC/ARM_CM23_NTZ/non_secure/portasm.h index f64ceb525..c6d2ebd58 100644 --- a/Source/portable/GCC/ARM_CM23_NTZ/non_secure/portasm.h +++ b/Source/portable/GCC/ARM_CM23_NTZ/non_secure/portasm.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/Source/portable/GCC/ARM_CM23_NTZ/non_secure/portmacro.h b/Source/portable/GCC/ARM_CM23_NTZ/non_secure/portmacro.h index d8dab9285..8034aa3a7 100644 --- a/Source/portable/GCC/ARM_CM23_NTZ/non_secure/portmacro.h +++ b/Source/portable/GCC/ARM_CM23_NTZ/non_secure/portmacro.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -48,9 +48,9 @@ /** * Architecture specifics. */ -#define portARCH_NAME "Cortex-M23" -#define portHAS_BASEPRI 0 -#define portDONT_DISCARD __attribute__( ( used ) ) +#define portARCH_NAME "Cortex-M23" +#define portHAS_ARMV8M_MAIN_EXTENSION 0 +#define portDONT_DISCARD __attribute__( ( used ) ) /*-----------------------------------------------------------*/ /* ARMv8-M common port configurations. */ diff --git a/Source/portable/GCC/ARM_CM23_NTZ/non_secure/portmacrocommon.h b/Source/portable/GCC/ARM_CM23_NTZ/non_secure/portmacrocommon.h index 6f666da22..33f21d85b 100644 --- a/Source/portable/GCC/ARM_CM23_NTZ/non_secure/portmacrocommon.h +++ b/Source/portable/GCC/ARM_CM23_NTZ/non_secure/portmacrocommon.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -117,7 +117,7 @@ extern uint32_t ulSetInterruptMask( void ) /* __attribute__(( naked )) PRIVILEGE extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */; #if ( configENABLE_TRUSTZONE == 1 ) - extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize ); /* __attribute__ (( naked )) */ + extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize ); /* __attribute__ (( naked )) */ extern void vPortFreeSecureContext( uint32_t * pulTCB ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */; #endif /* configENABLE_TRUSTZONE */ @@ -188,13 +188,13 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P #if ( configENABLE_MPU == 1 ) - /** - * @brief Settings to define an MPU region. - */ +/** + * @brief Settings to define an MPU region. + */ typedef struct MPURegionSettings { - uint32_t ulRBAR; /**< RBAR for the region. */ - uint32_t ulRLAR; /**< RLAR for the region. */ + uint32_t ulRBAR; /**< RBAR for the region. */ + uint32_t ulRLAR; /**< RLAR for the region. */ } MPURegionSettings_t; #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) @@ -203,9 +203,9 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P #error configSYSTEM_CALL_STACK_SIZE must be defined to the desired size of the system call stack in words for using MPU wrappers v2. #endif - /** - * @brief System call stack. - */ +/** + * @brief System call stack. + */ typedef struct SYSTEM_CALL_STACK_INFO { uint32_t ulSystemCallStackBuffer[ configSYSTEM_CALL_STACK_SIZE ]; @@ -218,74 +218,74 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P #endif /* configUSE_MPU_WRAPPERS_V1 == 0 */ - /** - * @brief MPU settings as stored in the TCB. - */ +/** + * @brief MPU settings as stored in the TCB. + */ #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) - #if( configENABLE_TRUSTZONE == 1 ) + #if ( configENABLE_TRUSTZONE == 1 ) - /* - * +-----------+---------------+----------+-----------------+------------------------------+-----+ - * | s16-s31 | s0-s15, FPSCR | r4-r11 | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, | | - * | | | | PC, xPSR | CONTROL, EXC_RETURN | | - * +-----------+---------------+----------+-----------------+------------------------------+-----+ - * - * <-----------><--------------><---------><----------------><-----------------------------><----> - * 16 16 8 8 5 1 - */ - #define MAX_CONTEXT_SIZE 54 +/* + * +-----------+---------------+----------+-----------------+------------------------------+-----+ + * | s16-s31 | s0-s15, FPSCR | r4-r11 | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, | | + * | | | | PC, xPSR | CONTROL, EXC_RETURN | | + * +-----------+---------------+----------+-----------------+------------------------------+-----+ + * + * <-----------><--------------><---------><----------------><-----------------------------><----> + * 16 16 8 8 5 1 + */ + #define MAX_CONTEXT_SIZE 54 #else /* #if( configENABLE_TRUSTZONE == 1 ) */ - /* - * +-----------+---------------+----------+-----------------+----------------------+-----+ - * | s16-s31 | s0-s15, FPSCR | r4-r11 | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL | | - * | | | | PC, xPSR | EXC_RETURN | | - * +-----------+---------------+----------+-----------------+----------------------+-----+ - * - * <-----------><--------------><---------><----------------><---------------------><----> - * 16 16 8 8 4 1 - */ - #define MAX_CONTEXT_SIZE 53 +/* + * +-----------+---------------+----------+-----------------+----------------------+-----+ + * | s16-s31 | s0-s15, FPSCR | r4-r11 | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL | | + * | | | | PC, xPSR | EXC_RETURN | | + * +-----------+---------------+----------+-----------------+----------------------+-----+ + * + * <-----------><--------------><---------><----------------><---------------------><----> + * 16 16 8 8 4 1 + */ + #define MAX_CONTEXT_SIZE 53 #endif /* #if( configENABLE_TRUSTZONE == 1 ) */ #else /* #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */ - #if( configENABLE_TRUSTZONE == 1 ) + #if ( configENABLE_TRUSTZONE == 1 ) - /* - * +----------+-----------------+------------------------------+-----+ - * | r4-r11 | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, | | - * | | PC, xPSR | CONTROL, EXC_RETURN | | - * +----------+-----------------+------------------------------+-----+ - * - * <---------><----------------><------------------------------><----> - * 8 8 5 1 - */ - #define MAX_CONTEXT_SIZE 22 +/* + * +----------+-----------------+------------------------------+-----+ + * | r4-r11 | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, | | + * | | PC, xPSR | CONTROL, EXC_RETURN | | + * +----------+-----------------+------------------------------+-----+ + * + * <---------><----------------><------------------------------><----> + * 8 8 5 1 + */ + #define MAX_CONTEXT_SIZE 22 #else /* #if( configENABLE_TRUSTZONE == 1 ) */ - /* - * +----------+-----------------+----------------------+-----+ - * | r4-r11 | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL | | - * | | PC, xPSR | EXC_RETURN | | - * +----------+-----------------+----------------------+-----+ - * - * <---------><----------------><----------------------><----> - * 8 8 4 1 - */ - #define MAX_CONTEXT_SIZE 21 +/* + * +----------+-----------------+----------------------+-----+ + * | r4-r11 | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL | | + * | | PC, xPSR | EXC_RETURN | | + * +----------+-----------------+----------------------+-----+ + * + * <---------><----------------><----------------------><----> + * 8 8 4 1 + */ + #define MAX_CONTEXT_SIZE 21 #endif /* #if( configENABLE_TRUSTZONE == 1 ) */ #endif /* #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */ - /* Flags used for xMPU_SETTINGS.ulTaskFlags member. */ - #define portSTACK_FRAME_HAS_PADDING_FLAG ( 1UL << 0UL ) - #define portTASK_IS_PRIVILEGED_FLAG ( 1UL << 1UL ) +/* Flags used for xMPU_SETTINGS.ulTaskFlags member. */ + #define portSTACK_FRAME_HAS_PADDING_FLAG ( 1UL << 0UL ) + #define portTASK_IS_PRIVILEGED_FLAG ( 1UL << 1UL ) /* Size of an Access Control List (ACL) entry in bits. */ #define portACL_ENTRY_SIZE_BITS ( 32U ) @@ -313,7 +313,7 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P * system calls. */ #ifdef configASSERT - #if ( portHAS_BASEPRI == 1 ) + #if ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) void vPortValidateInterruptPriority( void ); #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() vPortValidateInterruptPriority() #endif @@ -333,12 +333,29 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P /** * @brief Scheduler utilities. */ -#define portYIELD() vPortYield() +#if ( configENABLE_MPU == 1 ) + #define portYIELD() __asm volatile ( "svc %0" ::"i" ( portSVC_YIELD ) : "memory" ) + #define portYIELD_WITHIN_API() vPortYield() +#else + #define portYIELD() vPortYield() + #define portYIELD_WITHIN_API() vPortYield() +#endif + #define portNVIC_INT_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed04 ) ) #define portNVIC_PENDSVSET_BIT ( 1UL << 28UL ) -#define portEND_SWITCHING_ISR( xSwitchRequired ) \ - do { if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; } \ - while( 0 ) +#define portEND_SWITCHING_ISR( xSwitchRequired ) \ + do \ + { \ + if( xSwitchRequired ) \ + { \ + traceISR_EXIT_TO_SCHEDULER(); \ + portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; \ + } \ + else \ + { \ + traceISR_EXIT(); \ + } \ + } while( 0 ) #define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x ) /*-----------------------------------------------------------*/ @@ -424,12 +441,12 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P extern BaseType_t xPortIsTaskPrivileged( void ); - /** - * @brief Checks whether or not the calling task is privileged. - * - * @return pdTRUE if the calling task is privileged, pdFALSE otherwise. - */ - #define portIS_TASK_PRIVILEGED() xPortIsTaskPrivileged() +/** + * @brief Checks whether or not the calling task is privileged. + * + * @return pdTRUE if the calling task is privileged, pdFALSE otherwise. + */ + #define portIS_TASK_PRIVILEGED() xPortIsTaskPrivileged() #endif /* configENABLE_MPU == 1 */ /*-----------------------------------------------------------*/ @@ -440,6 +457,56 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P #define portMEMORY_BARRIER() __asm volatile ( "" ::: "memory" ) /*-----------------------------------------------------------*/ +/* Select correct value of configUSE_PORT_OPTIMISED_TASK_SELECTION + * based on whether or not Mainline extension is implemented. */ +#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION + #if ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) + #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1 + #else + #define configUSE_PORT_OPTIMISED_TASK_SELECTION 0 + #endif +#endif /* #ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION */ + +/** + * @brief Port-optimised task selection. + */ +#if ( configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 ) + +/** + * @brief Count the number of leading zeros in a 32-bit value. + */ + static portFORCE_INLINE uint32_t ulPortCountLeadingZeros( uint32_t ulBitmap ) + { + uint32_t ulReturn; + + __asm volatile ( "clz %0, %1" : "=r" ( ulReturn ) : "r" ( ulBitmap ) : "memory" ); + + return ulReturn; + } + +/* Check the configuration. */ + #if ( configMAX_PRIORITIES > 32 ) + #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 different priorities as tasks that share a priority will time slice. + #endif + + #if ( portHAS_ARMV8M_MAIN_EXTENSION == 0 ) + #error ARMv8-M baseline implementations (such as Cortex-M23) do not support port-optimised task selection. Please set configUSE_PORT_OPTIMISED_TASK_SELECTION to 0 or leave it undefined. + #endif + +/** + * @brief Store/clear the ready priorities in a bit map. + */ + #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) ) + #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) ) + +/** + * @brief Get the priority of the highest-priority task that is ready to execute. + */ + #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - ulPortCountLeadingZeros( ( uxReadyPriorities ) ) ) + +#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */ +/*-----------------------------------------------------------*/ + /* *INDENT-OFF* */ #ifdef __cplusplus } diff --git a/Source/portable/GCC/ARM_CM3/port.c b/Source/portable/GCC/ARM_CM3/port.c index cae2c5355..660f71bbd 100644 --- a/Source/portable/GCC/ARM_CM3/port.c +++ b/Source/portable/GCC/ARM_CM3/port.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -34,10 +34,14 @@ #include "FreeRTOS.h" #include "task.h" +/* Prototype of all Interrupt Service Routines (ISRs). */ +typedef void ( * portISR_t )( void ); + /* Constants required to manipulate the core. Registers first... */ #define portNVIC_SYSTICK_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000e010 ) ) #define portNVIC_SYSTICK_LOAD_REG ( *( ( volatile uint32_t * ) 0xe000e014 ) ) #define portNVIC_SYSTICK_CURRENT_VALUE_REG ( *( ( volatile uint32_t * ) 0xe000e018 ) ) +#define portNVIC_SHPR2_REG ( *( ( volatile uint32_t * ) 0xe000ed1c ) ) #define portNVIC_SHPR3_REG ( *( ( volatile uint32_t * ) 0xe000ed20 ) ) /* ...then bits in the registers. */ #define portNVIC_SYSTICK_CLK_BIT ( 1UL << 2UL ) @@ -52,6 +56,11 @@ #define portNVIC_PENDSV_PRI ( ( ( uint32_t ) portMIN_INTERRUPT_PRIORITY ) << 16UL ) #define portNVIC_SYSTICK_PRI ( ( ( uint32_t ) portMIN_INTERRUPT_PRIORITY ) << 24UL ) +/* Constants used to check the installation of the FreeRTOS interrupt handlers. */ +#define portSCB_VTOR_REG ( *( ( portISR_t ** ) 0xE000ED08 ) ) +#define portVECTOR_INDEX_SVC ( 11 ) +#define portVECTOR_INDEX_PENDSV ( 14 ) + /* Constants required to check the validity of an interrupt priority. */ #define portFIRST_USER_INTERRUPT_NUMBER ( 16 ) #define portNVIC_IP_REGISTERS_OFFSET_16 ( 0xE000E3F0 ) @@ -219,11 +228,11 @@ static void prvTaskExitError( void ) void vPortSVCHandler( void ) { __asm volatile ( - " ldr r3, pxCurrentTCBConst2 \n"/* Restore the context. */ - " ldr r1, [r3] \n"/* Use pxCurrentTCBConst to get the pxCurrentTCB address. */ - " ldr r0, [r1] \n"/* The first item in pxCurrentTCB is the task top of stack. */ - " ldmia r0!, {r4-r11} \n"/* Pop the registers that are not automatically saved on exception entry and the critical nesting count. */ - " msr psp, r0 \n"/* Restore the task stack pointer. */ + " ldr r3, pxCurrentTCBConst2 \n" /* Restore the context. */ + " ldr r1, [r3] \n" /* Use pxCurrentTCBConst to get the pxCurrentTCB address. */ + " ldr r0, [r1] \n" /* The first item in pxCurrentTCB is the task top of stack. */ + " ldmia r0!, {r4-r11} \n" /* Pop the registers that are not automatically saved on exception entry and the critical nesting count. */ + " msr psp, r0 \n" /* Restore the task stack pointer. */ " isb \n" " mov r0, #0 \n" " msr basepri, r0 \n" @@ -239,15 +248,15 @@ void vPortSVCHandler( void ) static void prvPortStartFirstTask( void ) { __asm volatile ( - " ldr r0, =0xE000ED08 \n"/* Use the NVIC offset register to locate the stack. */ + " ldr r0, =0xE000ED08 \n" /* Use the NVIC offset register to locate the stack. */ " ldr r0, [r0] \n" " ldr r0, [r0] \n" - " msr msp, r0 \n"/* Set the msp back to the start of the stack. */ - " cpsie i \n"/* Globally enable interrupts. */ + " msr msp, r0 \n" /* Set the msp back to the start of the stack. */ + " cpsie i \n" /* Globally enable interrupts. */ " cpsie f \n" " dsb \n" " isb \n" - " svc 0 \n"/* System call to start first task. */ + " svc 0 \n" /* System call to start first task. */ " nop \n" " .ltorg \n" ); @@ -259,6 +268,40 @@ static void prvPortStartFirstTask( void ) */ BaseType_t xPortStartScheduler( void ) { + /* An application can install FreeRTOS interrupt handlers in one of the + * folllowing ways: + * 1. Direct Routing - Install the functions vPortSVCHandler and + * xPortPendSVHandler for SVCall and PendSV interrupts respectively. + * 2. Indirect Routing - Install separate handlers for SVCall and PendSV + * interrupts and route program control from those handlers to + * vPortSVCHandler and xPortPendSVHandler functions. + * + * Applications that use Indirect Routing must set + * configCHECK_HANDLER_INSTALLATION to 0 in their FreeRTOSConfig.h. Direct + * routing, which is validated here when configCHECK_HANDLER_INSTALLATION + * is 1, should be preferred when possible. */ + #if ( configCHECK_HANDLER_INSTALLATION == 1 ) + { + const portISR_t * const pxVectorTable = portSCB_VTOR_REG; + + /* Validate that the application has correctly installed the FreeRTOS + * handlers for SVCall and PendSV interrupts. We do not check the + * installation of the SysTick handler because the application may + * choose to drive the RTOS tick using a timer other than the SysTick + * timer by overriding the weak function vPortSetupTimerInterrupt(). + * + * Assertion failures here indicate incorrect installation of the + * FreeRTOS handlers. For help installing the FreeRTOS handlers, see + * https://www.FreeRTOS.org/FAQHelp.html. + * + * Systems with a configurable address for the interrupt vector table + * can also encounter assertion failures or even system faults here if + * VTOR is not set correctly to point to the application's vector table. */ + configASSERT( pxVectorTable[ portVECTOR_INDEX_SVC ] == vPortSVCHandler ); + configASSERT( pxVectorTable[ portVECTOR_INDEX_PENDSV ] == xPortPendSVHandler ); + } + #endif /* configCHECK_HANDLER_INSTALLATION */ + #if ( configASSERT_DEFINED == 1 ) { volatile uint8_t ucOriginalPriority; @@ -308,22 +351,22 @@ BaseType_t xPortStartScheduler( void ) if( ulImplementedPrioBits == 8 ) { /* When the hardware implements 8 priority bits, there is no way for - * the software to configure PRIGROUP to not have sub-priorities. As - * a result, the least significant bit is always used for sub-priority - * and there are 128 preemption priorities and 2 sub-priorities. - * - * This may cause some confusion in some cases - for example, if - * configMAX_SYSCALL_INTERRUPT_PRIORITY is set to 5, both 5 and 4 - * priority interrupts will be masked in Critical Sections as those - * are at the same preemption priority. This may appear confusing as - * 4 is higher (numerically lower) priority than - * configMAX_SYSCALL_INTERRUPT_PRIORITY and therefore, should not - * have been masked. Instead, if we set configMAX_SYSCALL_INTERRUPT_PRIORITY - * to 4, this confusion does not happen and the behaviour remains the same. - * - * The following assert ensures that the sub-priority bit in the - * configMAX_SYSCALL_INTERRUPT_PRIORITY is clear to avoid the above mentioned - * confusion. */ + * the software to configure PRIGROUP to not have sub-priorities. As + * a result, the least significant bit is always used for sub-priority + * and there are 128 preemption priorities and 2 sub-priorities. + * + * This may cause some confusion in some cases - for example, if + * configMAX_SYSCALL_INTERRUPT_PRIORITY is set to 5, both 5 and 4 + * priority interrupts will be masked in Critical Sections as those + * are at the same preemption priority. This may appear confusing as + * 4 is higher (numerically lower) priority than + * configMAX_SYSCALL_INTERRUPT_PRIORITY and therefore, should not + * have been masked. Instead, if we set configMAX_SYSCALL_INTERRUPT_PRIORITY + * to 4, this confusion does not happen and the behaviour remains the same. + * + * The following assert ensures that the sub-priority bit in the + * configMAX_SYSCALL_INTERRUPT_PRIORITY is clear to avoid the above mentioned + * confusion. */ configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & 0x1U ) == 0U ); ulMaxPRIGROUPValue = 0; } @@ -343,9 +386,11 @@ BaseType_t xPortStartScheduler( void ) } #endif /* configASSERT_DEFINED */ - /* Make PendSV and SysTick the lowest priority interrupts. */ + /* Make PendSV and SysTick the lowest priority interrupts, and make SVCall + * the highest priority. */ portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI; portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI; + portNVIC_SHPR2_REG = 0; /* Start the timer that generates the tick ISR. Interrupts are disabled * here already. */ @@ -417,11 +462,11 @@ void xPortPendSVHandler( void ) " mrs r0, psp \n" " isb \n" " \n" - " ldr r3, pxCurrentTCBConst \n"/* Get the location of the current TCB. */ + " ldr r3, pxCurrentTCBConst \n" /* Get the location of the current TCB. */ " ldr r2, [r3] \n" " \n" - " stmdb r0!, {r4-r11} \n"/* Save the remaining registers. */ - " str r0, [r2] \n"/* Save the new top of stack into the first member of the TCB. */ + " stmdb r0!, {r4-r11} \n" /* Save the remaining registers. */ + " str r0, [r2] \n" /* Save the new top of stack into the first member of the TCB. */ " \n" " stmdb sp!, {r3, r14} \n" " mov r0, %0 \n" @@ -430,10 +475,10 @@ void xPortPendSVHandler( void ) " mov r0, #0 \n" " msr basepri, r0 \n" " ldmia sp!, {r3, r14} \n" - " \n"/* Restore the context, including the critical nesting count. */ + " \n" /* Restore the context, including the critical nesting count. */ " ldr r1, [r3] \n" - " ldr r0, [r1] \n"/* The first item in pxCurrentTCB is the task top of stack. */ - " ldmia r0!, {r4-r11} \n"/* Pop the registers. */ + " ldr r0, [r1] \n" /* The first item in pxCurrentTCB is the task top of stack. */ + " ldmia r0!, {r4-r11} \n" /* Pop the registers. */ " msr psp, r0 \n" " isb \n" " bx r14 \n" @@ -452,14 +497,21 @@ void xPortSysTickHandler( void ) * save and then restore the interrupt mask value as its value is already * known. */ portDISABLE_INTERRUPTS(); + traceISR_ENTER(); { /* Increment the RTOS tick. */ if( xTaskIncrementTick() != pdFALSE ) { + traceISR_EXIT_TO_SCHEDULER(); + /* A context switch is required. Context switching is performed in * the PendSV interrupt. Pend the PendSV interrupt. */ portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; } + else + { + traceISR_EXIT(); + } } portENABLE_INTERRUPTS(); } @@ -769,4 +821,4 @@ __attribute__( ( weak ) ) void vPortSetupTimerInterrupt( void ) configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue ); } -#endif /* configASSERT_DEFINED */ \ No newline at end of file +#endif /* configASSERT_DEFINED */ diff --git a/Source/portable/GCC/ARM_CM3/portmacro.h b/Source/portable/GCC/ARM_CM3/portmacro.h index bdedf5a60..4f395f2ea 100644 --- a/Source/portable/GCC/ARM_CM3/portmacro.h +++ b/Source/portable/GCC/ARM_CM3/portmacro.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -28,7 +28,7 @@ #ifndef PORTMACRO_H - #define PORTMACRO_H +#define PORTMACRO_H /* *INDENT-OFF* */ #ifdef __cplusplus @@ -47,42 +47,42 @@ */ /* Type definitions. */ - #define portCHAR char - #define portFLOAT float - #define portDOUBLE double - #define portLONG long - #define portSHORT short - #define portSTACK_TYPE uint32_t - #define portBASE_TYPE long - - typedef portSTACK_TYPE StackType_t; - typedef long BaseType_t; - typedef unsigned long UBaseType_t; - - #if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS ) - typedef uint16_t TickType_t; - #define portMAX_DELAY ( TickType_t ) 0xffff - #elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS ) - typedef uint32_t TickType_t; - #define portMAX_DELAY ( TickType_t ) 0xffffffffUL +#define portCHAR char +#define portFLOAT float +#define portDOUBLE double +#define portLONG long +#define portSHORT short +#define portSTACK_TYPE uint32_t +#define portBASE_TYPE long + +typedef portSTACK_TYPE StackType_t; +typedef long BaseType_t; +typedef unsigned long UBaseType_t; + +#if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS ) + typedef uint16_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffff +#elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS ) + typedef uint32_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffffffffUL /* 32-bit tick type on a 32-bit architecture, so reads of the tick count do * not need to be guarded with a critical section. */ - #define portTICK_TYPE_IS_ATOMIC 1 - #else - #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width. - #endif + #define portTICK_TYPE_IS_ATOMIC 1 +#else + #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width. +#endif /*-----------------------------------------------------------*/ /* Architecture specifics. */ - #define portSTACK_GROWTH ( -1 ) - #define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) - #define portBYTE_ALIGNMENT 8 - #define portDONT_DISCARD __attribute__( ( used ) ) +#define portSTACK_GROWTH ( -1 ) +#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) +#define portBYTE_ALIGNMENT 8 +#define portDONT_DISCARD __attribute__( ( used ) ) /*-----------------------------------------------------------*/ /* Scheduler utilities. */ - #define portYIELD() \ +#define portYIELD() \ { \ /* Set a PendSV to request a context switch. */ \ portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; \ @@ -93,156 +93,168 @@ __asm volatile ( "isb" ); \ } - #define portNVIC_INT_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed04 ) ) - #define portNVIC_PENDSVSET_BIT ( 1UL << 28UL ) - #define portEND_SWITCHING_ISR( xSwitchRequired ) do { if( xSwitchRequired != pdFALSE ) portYIELD(); } while( 0 ) - #define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x ) +#define portNVIC_INT_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed04 ) ) +#define portNVIC_PENDSVSET_BIT ( 1UL << 28UL ) +#define portEND_SWITCHING_ISR( xSwitchRequired ) \ + do \ + { \ + if( xSwitchRequired != pdFALSE ) \ + { \ + traceISR_EXIT_TO_SCHEDULER(); \ + portYIELD(); \ + } \ + else \ + { \ + traceISR_EXIT(); \ + } \ + } while( 0 ) +#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x ) /*-----------------------------------------------------------*/ /* Critical section management. */ - extern void vPortEnterCritical( void ); - extern void vPortExitCritical( void ); - #define portSET_INTERRUPT_MASK_FROM_ISR() ulPortRaiseBASEPRI() - #define portCLEAR_INTERRUPT_MASK_FROM_ISR( x ) vPortSetBASEPRI( x ) - #define portDISABLE_INTERRUPTS() vPortRaiseBASEPRI() - #define portENABLE_INTERRUPTS() vPortSetBASEPRI( 0 ) - #define portENTER_CRITICAL() vPortEnterCritical() - #define portEXIT_CRITICAL() vPortExitCritical() +extern void vPortEnterCritical( void ); +extern void vPortExitCritical( void ); +#define portSET_INTERRUPT_MASK_FROM_ISR() ulPortRaiseBASEPRI() +#define portCLEAR_INTERRUPT_MASK_FROM_ISR( x ) vPortSetBASEPRI( x ) +#define portDISABLE_INTERRUPTS() vPortRaiseBASEPRI() +#define portENABLE_INTERRUPTS() vPortSetBASEPRI( 0 ) +#define portENTER_CRITICAL() vPortEnterCritical() +#define portEXIT_CRITICAL() vPortExitCritical() /*-----------------------------------------------------------*/ /* Task function macros as described on the FreeRTOS.org WEB site. These are * not necessary for to use this port. They are defined so the common demo files * (which build with all the ports) will build. */ - #define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters ) - #define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters ) +#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters ) +#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters ) /*-----------------------------------------------------------*/ /* Tickless idle/low power functionality. */ - #ifndef portSUPPRESS_TICKS_AND_SLEEP - extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime ); - #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime ) vPortSuppressTicksAndSleep( xExpectedIdleTime ) - #endif +#ifndef portSUPPRESS_TICKS_AND_SLEEP + extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime ); + #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime ) vPortSuppressTicksAndSleep( xExpectedIdleTime ) +#endif /*-----------------------------------------------------------*/ /* Architecture specific optimisations. */ - #ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION - #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1 - #endif +#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION + #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1 +#endif - #if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 +#if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 /* Generic helper function. */ - __attribute__( ( always_inline ) ) static inline uint8_t ucPortCountLeadingZeros( uint32_t ulBitmap ) - { - uint8_t ucReturn; + __attribute__( ( always_inline ) ) static inline uint8_t ucPortCountLeadingZeros( uint32_t ulBitmap ) + { + uint8_t ucReturn; - __asm volatile ( "clz %0, %1" : "=r" ( ucReturn ) : "r" ( ulBitmap ) : "memory" ); + __asm volatile ( "clz %0, %1" : "=r" ( ucReturn ) : "r" ( ulBitmap ) : "memory" ); - return ucReturn; - } + return ucReturn; + } /* Check the configuration. */ - #if ( configMAX_PRIORITIES > 32 ) - #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice. - #endif + #if ( configMAX_PRIORITIES > 32 ) + #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice. + #endif /* Store/clear the ready priorities in a bit map. */ - #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) ) - #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) ) + #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) ) + #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) ) /*-----------------------------------------------------------*/ - #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - ( uint32_t ) ucPortCountLeadingZeros( ( uxReadyPriorities ) ) ) + #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - ( uint32_t ) ucPortCountLeadingZeros( ( uxReadyPriorities ) ) ) - #endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */ +#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */ /*-----------------------------------------------------------*/ - #ifdef configASSERT - void vPortValidateInterruptPriority( void ); - #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() vPortValidateInterruptPriority() - #endif +#ifdef configASSERT + void vPortValidateInterruptPriority( void ); + #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() vPortValidateInterruptPriority() +#endif /* portNOP() is not required by this port. */ - #define portNOP() +#define portNOP() - #define portINLINE __inline +#define portINLINE __inline - #ifndef portFORCE_INLINE - #define portFORCE_INLINE inline __attribute__( ( always_inline ) ) - #endif +#ifndef portFORCE_INLINE + #define portFORCE_INLINE inline __attribute__( ( always_inline ) ) +#endif /*-----------------------------------------------------------*/ - portFORCE_INLINE static BaseType_t xPortIsInsideInterrupt( void ) +portFORCE_INLINE static BaseType_t xPortIsInsideInterrupt( void ) +{ + uint32_t ulCurrentInterrupt; + BaseType_t xReturn; + + /* Obtain the number of the currently executing interrupt. */ + __asm volatile ( "mrs %0, ipsr" : "=r" ( ulCurrentInterrupt )::"memory" ); + + if( ulCurrentInterrupt == 0 ) + { + xReturn = pdFALSE; + } + else { - uint32_t ulCurrentInterrupt; - BaseType_t xReturn; - - /* Obtain the number of the currently executing interrupt. */ - __asm volatile ( "mrs %0, ipsr" : "=r" ( ulCurrentInterrupt )::"memory" ); - - if( ulCurrentInterrupt == 0 ) - { - xReturn = pdFALSE; - } - else - { - xReturn = pdTRUE; - } - - return xReturn; + xReturn = pdTRUE; } + return xReturn; +} + /*-----------------------------------------------------------*/ - portFORCE_INLINE static void vPortRaiseBASEPRI( void ) - { - uint32_t ulNewBASEPRI; - - __asm volatile - ( - " mov %0, %1 \n"\ - " msr basepri, %0 \n"\ - " isb \n"\ - " dsb \n"\ - : "=r" ( ulNewBASEPRI ) : "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "memory" - ); - } +portFORCE_INLINE static void vPortRaiseBASEPRI( void ) +{ + uint32_t ulNewBASEPRI; + + __asm volatile + ( + " mov %0, %1 \n" \ + " msr basepri, %0 \n" \ + " isb \n" \ + " dsb \n" \ + : "=r" ( ulNewBASEPRI ) : "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "memory" + ); +} /*-----------------------------------------------------------*/ - portFORCE_INLINE static uint32_t ulPortRaiseBASEPRI( void ) - { - uint32_t ulOriginalBASEPRI, ulNewBASEPRI; - - __asm volatile - ( - " mrs %0, basepri \n"\ - " mov %1, %2 \n"\ - " msr basepri, %1 \n"\ - " isb \n"\ - " dsb \n"\ - : "=r" ( ulOriginalBASEPRI ), "=r" ( ulNewBASEPRI ) : "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "memory" - ); - - /* This return will not be reached but is necessary to prevent compiler - * warnings. */ - return ulOriginalBASEPRI; - } +portFORCE_INLINE static uint32_t ulPortRaiseBASEPRI( void ) +{ + uint32_t ulOriginalBASEPRI, ulNewBASEPRI; + + __asm volatile + ( + " mrs %0, basepri \n" \ + " mov %1, %2 \n" \ + " msr basepri, %1 \n" \ + " isb \n" \ + " dsb \n" \ + : "=r" ( ulOriginalBASEPRI ), "=r" ( ulNewBASEPRI ) : "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "memory" + ); + + /* This return will not be reached but is necessary to prevent compiler + * warnings. */ + return ulOriginalBASEPRI; +} /*-----------------------------------------------------------*/ - portFORCE_INLINE static void vPortSetBASEPRI( uint32_t ulNewMaskValue ) - { - __asm volatile - ( - " msr basepri, %0 "::"r" ( ulNewMaskValue ) : "memory" - ); - } +portFORCE_INLINE static void vPortSetBASEPRI( uint32_t ulNewMaskValue ) +{ + __asm volatile + ( + " msr basepri, %0 " ::"r" ( ulNewMaskValue ) : "memory" + ); +} /*-----------------------------------------------------------*/ - #define portMEMORY_BARRIER() __asm volatile ( "" ::: "memory" ) +#define portMEMORY_BARRIER() __asm volatile ( "" ::: "memory" ) /* *INDENT-OFF* */ #ifdef __cplusplus diff --git a/Source/portable/GCC/ARM_CM33/non_secure/mpu_wrappers_v2_asm.c b/Source/portable/GCC/ARM_CM33/non_secure/mpu_wrappers_v2_asm.c index d247c92e0..052f97850 100644 --- a/Source/portable/GCC/ARM_CM33/non_secure/mpu_wrappers_v2_asm.c +++ b/Source/portable/GCC/ARM_CM33/non_secure/mpu_wrappers_v2_asm.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -365,31 +365,6 @@ } /*-----------------------------------------------------------*/ - char * MPU_pcTaskGetName( TaskHandle_t xTaskToQuery ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; - - char * MPU_pcTaskGetName( TaskHandle_t xTaskToQuery ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ - { - __asm volatile - ( - " .syntax unified \n" - " .extern MPU_pcTaskGetNameImpl \n" - " \n" - " push {r0} \n" - " mrs r0, control \n" - " tst r0, #1 \n" - " bne MPU_pcTaskGetName_Unpriv \n" - " MPU_pcTaskGetName_Priv: \n" - " pop {r0} \n" - " b MPU_pcTaskGetNameImpl \n" - " MPU_pcTaskGetName_Unpriv: \n" - " pop {r0} \n" - " svc %0 \n" - " \n" - : : "i" ( SYSTEM_CALL_pcTaskGetName ) : "memory" - ); - } -/*-----------------------------------------------------------*/ - #if ( configGENERATE_RUN_TIME_STATS == 1 ) configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetRunTimeCounter( const TaskHandle_t xTask ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; @@ -1512,31 +1487,27 @@ #if ( configUSE_TIMERS == 1 ) - BaseType_t MPU_xTimerGenericCommandEntry( const xTimerGenericCommandParams_t * pxParams ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + BaseType_t MPU_xTimerGenericCommandFromTaskEntry( const xTimerGenericCommandFromTaskParams_t * pxParams ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; - BaseType_t MPU_xTimerGenericCommandEntry( const xTimerGenericCommandParams_t * pxParams ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + BaseType_t MPU_xTimerGenericCommandFromTaskEntry( const xTimerGenericCommandFromTaskParams_t * pxParams ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ { __asm volatile ( - " .syntax unified \n" - " .extern MPU_xTimerGenericCommandPrivImpl \n" - " \n" - " push {r0} \n" - " mrs r0, ipsr \n" - " cmp r0, #0 \n" - " bne MPU_xTimerGenericCommand_Priv \n" - " mrs r0, control \n" - " tst r0, #1 \n" - " beq MPU_xTimerGenericCommand_Priv \n" - " MPU_xTimerGenericCommand_Unpriv: \n" - " pop {r0} \n" - " svc %0 \n" - " MPU_xTimerGenericCommand_Priv: \n" - " pop {r0} \n" - " b MPU_xTimerGenericCommandPrivImpl \n" - " \n" - " \n" - : : "i" ( SYSTEM_CALL_xTimerGenericCommand ) : "memory" + " .syntax unified \n" + " .extern MPU_xTimerGenericCommandFromTaskImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " bne MPU_xTimerGenericCommandFromTask_Unpriv \n" + " MPU_xTimerGenericCommandFromTask_Priv: \n" + " pop {r0} \n" + " b MPU_xTimerGenericCommandFromTaskImpl \n" + " MPU_xTimerGenericCommandFromTask_Unpriv: \n" + " pop {r0} \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xTimerGenericCommandFromTask ) : "memory" ); } diff --git a/Source/portable/GCC/ARM_CM33/non_secure/port.c b/Source/portable/GCC/ARM_CM33/non_secure/port.c index 9712ac353..230fe5fc2 100644 --- a/Source/portable/GCC/ARM_CM33/non_secure/port.c +++ b/Source/portable/GCC/ARM_CM33/non_secure/port.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -68,6 +68,22 @@ #if ( ( configRUN_FREERTOS_SECURE_ONLY == 1 ) && ( configENABLE_TRUSTZONE == 1 ) ) #error TrustZone needs to be disabled in order to run FreeRTOS on the Secure Side. #endif + +/** + * Cortex-M23 does not have non-secure PSPLIM. We should use PSPLIM on Cortex-M23 + * only when FreeRTOS runs on secure side. + */ +#if ( ( portHAS_ARMV8M_MAIN_EXTENSION == 0 ) && ( configRUN_FREERTOS_SECURE_ONLY == 0 ) ) + #define portUSE_PSPLIM_REGISTER 0 +#else + #define portUSE_PSPLIM_REGISTER 1 +#endif +/*-----------------------------------------------------------*/ + +/** + * @brief Prototype of all Interrupt Service Routines (ISRs). + */ +typedef void ( * portISR_t )( void ); /*-----------------------------------------------------------*/ /** @@ -91,10 +107,18 @@ /** * @brief Constants required to manipulate the SCB. */ -#define portSCB_SYS_HANDLER_CTRL_STATE_REG ( *( volatile uint32_t * ) 0xe000ed24 ) +#define portSCB_VTOR_REG ( *( ( portISR_t ** ) 0xe000ed08 ) ) +#define portSCB_SYS_HANDLER_CTRL_STATE_REG ( *( ( volatile uint32_t * ) 0xe000ed24 ) ) #define portSCB_MEM_FAULT_ENABLE_BIT ( 1UL << 16UL ) /*-----------------------------------------------------------*/ +/** + * @brief Constants used to check the installation of the FreeRTOS interrupt handlers. + */ +#define portVECTOR_INDEX_SVC ( 11 ) +#define portVECTOR_INDEX_PENDSV ( 14 ) +/*-----------------------------------------------------------*/ + /** * @brief Constants required to check the validity of an interrupt priority. */ @@ -111,8 +135,8 @@ /** * @brief Constants used during system call enter and exit. */ -#define portPSR_STACK_PADDING_MASK ( 1UL << 9UL ) -#define portEXC_RETURN_STACK_FRAME_TYPE_MASK ( 1UL << 4UL ) +#define portPSR_STACK_PADDING_MASK ( 1UL << 9UL ) +#define portEXC_RETURN_STACK_FRAME_TYPE_MASK ( 1UL << 4UL ) /*-----------------------------------------------------------*/ /** @@ -134,81 +158,81 @@ /** * @brief Offsets in the stack to the parameters when inside the SVC handler. */ -#define portOFFSET_TO_LR ( 5 ) -#define portOFFSET_TO_PC ( 6 ) -#define portOFFSET_TO_PSR ( 7 ) +#define portOFFSET_TO_LR ( 5 ) +#define portOFFSET_TO_PC ( 6 ) +#define portOFFSET_TO_PSR ( 7 ) /*-----------------------------------------------------------*/ /** * @brief Constants required to manipulate the MPU. */ -#define portMPU_TYPE_REG ( *( ( volatile uint32_t * ) 0xe000ed90 ) ) -#define portMPU_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed94 ) ) -#define portMPU_RNR_REG ( *( ( volatile uint32_t * ) 0xe000ed98 ) ) +#define portMPU_TYPE_REG ( *( ( volatile uint32_t * ) 0xe000ed90 ) ) +#define portMPU_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed94 ) ) +#define portMPU_RNR_REG ( *( ( volatile uint32_t * ) 0xe000ed98 ) ) -#define portMPU_RBAR_REG ( *( ( volatile uint32_t * ) 0xe000ed9c ) ) -#define portMPU_RLAR_REG ( *( ( volatile uint32_t * ) 0xe000eda0 ) ) +#define portMPU_RBAR_REG ( *( ( volatile uint32_t * ) 0xe000ed9c ) ) +#define portMPU_RLAR_REG ( *( ( volatile uint32_t * ) 0xe000eda0 ) ) -#define portMPU_RBAR_A1_REG ( *( ( volatile uint32_t * ) 0xe000eda4 ) ) -#define portMPU_RLAR_A1_REG ( *( ( volatile uint32_t * ) 0xe000eda8 ) ) +#define portMPU_RBAR_A1_REG ( *( ( volatile uint32_t * ) 0xe000eda4 ) ) +#define portMPU_RLAR_A1_REG ( *( ( volatile uint32_t * ) 0xe000eda8 ) ) -#define portMPU_RBAR_A2_REG ( *( ( volatile uint32_t * ) 0xe000edac ) ) -#define portMPU_RLAR_A2_REG ( *( ( volatile uint32_t * ) 0xe000edb0 ) ) +#define portMPU_RBAR_A2_REG ( *( ( volatile uint32_t * ) 0xe000edac ) ) +#define portMPU_RLAR_A2_REG ( *( ( volatile uint32_t * ) 0xe000edb0 ) ) -#define portMPU_RBAR_A3_REG ( *( ( volatile uint32_t * ) 0xe000edb4 ) ) -#define portMPU_RLAR_A3_REG ( *( ( volatile uint32_t * ) 0xe000edb8 ) ) +#define portMPU_RBAR_A3_REG ( *( ( volatile uint32_t * ) 0xe000edb4 ) ) +#define portMPU_RLAR_A3_REG ( *( ( volatile uint32_t * ) 0xe000edb8 ) ) -#define portMPU_MAIR0_REG ( *( ( volatile uint32_t * ) 0xe000edc0 ) ) -#define portMPU_MAIR1_REG ( *( ( volatile uint32_t * ) 0xe000edc4 ) ) +#define portMPU_MAIR0_REG ( *( ( volatile uint32_t * ) 0xe000edc0 ) ) +#define portMPU_MAIR1_REG ( *( ( volatile uint32_t * ) 0xe000edc4 ) ) -#define portMPU_RBAR_ADDRESS_MASK ( 0xffffffe0 ) /* Must be 32-byte aligned. */ -#define portMPU_RLAR_ADDRESS_MASK ( 0xffffffe0 ) /* Must be 32-byte aligned. */ +#define portMPU_RBAR_ADDRESS_MASK ( 0xffffffe0 ) /* Must be 32-byte aligned. */ +#define portMPU_RLAR_ADDRESS_MASK ( 0xffffffe0 ) /* Must be 32-byte aligned. */ -#define portMPU_RBAR_ACCESS_PERMISSIONS_MASK ( 3UL << 1UL ) +#define portMPU_RBAR_ACCESS_PERMISSIONS_MASK ( 3UL << 1UL ) -#define portMPU_MAIR_ATTR0_POS ( 0UL ) -#define portMPU_MAIR_ATTR0_MASK ( 0x000000ff ) +#define portMPU_MAIR_ATTR0_POS ( 0UL ) +#define portMPU_MAIR_ATTR0_MASK ( 0x000000ff ) -#define portMPU_MAIR_ATTR1_POS ( 8UL ) -#define portMPU_MAIR_ATTR1_MASK ( 0x0000ff00 ) +#define portMPU_MAIR_ATTR1_POS ( 8UL ) +#define portMPU_MAIR_ATTR1_MASK ( 0x0000ff00 ) -#define portMPU_MAIR_ATTR2_POS ( 16UL ) -#define portMPU_MAIR_ATTR2_MASK ( 0x00ff0000 ) +#define portMPU_MAIR_ATTR2_POS ( 16UL ) +#define portMPU_MAIR_ATTR2_MASK ( 0x00ff0000 ) -#define portMPU_MAIR_ATTR3_POS ( 24UL ) -#define portMPU_MAIR_ATTR3_MASK ( 0xff000000 ) +#define portMPU_MAIR_ATTR3_POS ( 24UL ) +#define portMPU_MAIR_ATTR3_MASK ( 0xff000000 ) -#define portMPU_MAIR_ATTR4_POS ( 0UL ) -#define portMPU_MAIR_ATTR4_MASK ( 0x000000ff ) +#define portMPU_MAIR_ATTR4_POS ( 0UL ) +#define portMPU_MAIR_ATTR4_MASK ( 0x000000ff ) -#define portMPU_MAIR_ATTR5_POS ( 8UL ) -#define portMPU_MAIR_ATTR5_MASK ( 0x0000ff00 ) +#define portMPU_MAIR_ATTR5_POS ( 8UL ) +#define portMPU_MAIR_ATTR5_MASK ( 0x0000ff00 ) -#define portMPU_MAIR_ATTR6_POS ( 16UL ) -#define portMPU_MAIR_ATTR6_MASK ( 0x00ff0000 ) +#define portMPU_MAIR_ATTR6_POS ( 16UL ) +#define portMPU_MAIR_ATTR6_MASK ( 0x00ff0000 ) -#define portMPU_MAIR_ATTR7_POS ( 24UL ) -#define portMPU_MAIR_ATTR7_MASK ( 0xff000000 ) +#define portMPU_MAIR_ATTR7_POS ( 24UL ) +#define portMPU_MAIR_ATTR7_MASK ( 0xff000000 ) -#define portMPU_RLAR_ATTR_INDEX0 ( 0UL << 1UL ) -#define portMPU_RLAR_ATTR_INDEX1 ( 1UL << 1UL ) -#define portMPU_RLAR_ATTR_INDEX2 ( 2UL << 1UL ) -#define portMPU_RLAR_ATTR_INDEX3 ( 3UL << 1UL ) -#define portMPU_RLAR_ATTR_INDEX4 ( 4UL << 1UL ) -#define portMPU_RLAR_ATTR_INDEX5 ( 5UL << 1UL ) -#define portMPU_RLAR_ATTR_INDEX6 ( 6UL << 1UL ) -#define portMPU_RLAR_ATTR_INDEX7 ( 7UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX0 ( 0UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX1 ( 1UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX2 ( 2UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX3 ( 3UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX4 ( 4UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX5 ( 5UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX6 ( 6UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX7 ( 7UL << 1UL ) -#define portMPU_RLAR_REGION_ENABLE ( 1UL ) +#define portMPU_RLAR_REGION_ENABLE ( 1UL ) /* Enable privileged access to unmapped region. */ -#define portMPU_PRIV_BACKGROUND_ENABLE_BIT ( 1UL << 2UL ) +#define portMPU_PRIV_BACKGROUND_ENABLE_BIT ( 1UL << 2UL ) /* Enable MPU. */ -#define portMPU_ENABLE_BIT ( 1UL << 0UL ) +#define portMPU_ENABLE_BIT ( 1UL << 0UL ) /* Expected value of the portMPU_TYPE register. */ -#define portEXPECTED_MPU_TYPE_VALUE ( configTOTAL_MPU_REGIONS << 8UL ) +#define portEXPECTED_MPU_TYPE_VALUE ( configTOTAL_MPU_REGIONS << 8UL ) /* Extract first address of the MPU region as encoded in the * RBAR (Region Base Address Register) value. */ @@ -448,13 +472,13 @@ portDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIV #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) - /** - * @brief Sets up the task stack so that upon returning from - * SVC, the task stack is used again. - * - * @param pulSystemCallStack The current SP when the SVC was raised. - * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler. - */ +/** + * @brief Sets up the task stack so that upon returning from + * SVC, the task stack is used again. + * + * @param pulSystemCallStack The current SP when the SVC was raised. + * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler. + */ void vSystemCallExit( uint32_t * pulSystemCallStack, uint32_t ulLR ) PRIVILEGED_FUNCTION; @@ -462,11 +486,11 @@ portDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIV #if ( configENABLE_MPU == 1 ) - /** - * @brief Checks whether or not the calling task is privileged. - * - * @return pdTRUE if the calling task is privileged, pdFALSE otherwise. - */ +/** + * @brief Checks whether or not the calling task is privileged. + * + * @return pdTRUE if the calling task is privileged, pdFALSE otherwise. + */ BaseType_t xPortIsTaskPrivileged( void ) PRIVILEGED_FUNCTION; #endif /* configENABLE_MPU == 1 */ @@ -501,13 +525,13 @@ PRIVILEGED_DATA static volatile uint32_t ulCriticalNesting = 0xaaaaaaaaUL; * FreeRTOS API functions are not called from interrupts that have been assigned * a priority above configMAX_SYSCALL_INTERRUPT_PRIORITY. */ -#if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) ) +#if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) static uint8_t ucMaxSysCallPriority = 0; static uint32_t ulMaxPRIGROUPValue = 0; static const volatile uint8_t * const pcInterruptPriorityRegisters = ( const volatile uint8_t * ) portNVIC_IP_REGISTERS_OFFSET_16; -#endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) ) */ +#endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */ #if ( configUSE_TICKLESS_IDLE == 1 ) @@ -760,8 +784,15 @@ __attribute__( ( weak ) ) void vPortSetupTimerInterrupt( void ) /* PRIVILEGED_FU } #endif /* configUSE_TICKLESS_IDLE */ - /* Stop and reset the SysTick. */ - portNVIC_SYSTICK_CTRL_REG = 0UL; + /* Stop and reset SysTick. + * + * QEMU versions older than 7.0.0 contain a bug which causes an error if we + * enable SysTick without first selecting a valid clock source. We trigger + * the bug if we change clock sources from a clock with a zero clock period + * to one with a nonzero clock period and enable Systick at the same time. + * So we configure the CLKSOURCE bit here, prior to setting the ENABLE bit. + * This workaround avoids the bug in QEMU versions older than 7.0.0. */ + portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT_CONFIG; portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL; /* Configure SysTick to interrupt at the requested rate. */ @@ -819,6 +850,7 @@ static void prvTaskExitError( void ) static void prvSetupMPU( void ) /* PRIVILEGED_FUNCTION */ { #if defined( __ARMCC_VERSION ) + /* Declaration when these variable are defined in code instead of being * exported from linker scripts. */ extern uint32_t * __privileged_functions_start__; @@ -972,13 +1004,19 @@ void SysTick_Handler( void ) /* PRIVILEGED_FUNCTION */ uint32_t ulPreviousMask; ulPreviousMask = portSET_INTERRUPT_MASK_FROM_ISR(); + traceISR_ENTER(); { /* Increment the RTOS tick. */ if( xTaskIncrementTick() != pdFALSE ) { + traceISR_EXIT_TO_SCHEDULER(); /* Pend a context switch. */ portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; } + else + { + traceISR_EXIT(); + } } portCLEAR_INTERRUPT_MASK_FROM_ISR( ulPreviousMask ); } @@ -988,6 +1026,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO { #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) ) #if defined( __ARMCC_VERSION ) + /* Declaration when these variable are defined in code instead of being * exported from linker scripts. */ extern uint32_t * __syscalls_flash_start__; @@ -1083,18 +1122,24 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO vRestoreContextOfFirstTask(); break; - #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) ) - case portSVC_RAISE_PRIVILEGE: + #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) ) + case portSVC_RAISE_PRIVILEGE: - /* Only raise the privilege, if the svc was raised from any of - * the system calls. */ - if( ( ulPC >= ( uint32_t ) __syscalls_flash_start__ ) && - ( ulPC <= ( uint32_t ) __syscalls_flash_end__ ) ) - { - vRaisePrivilege(); - } - break; - #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) */ + /* Only raise the privilege, if the svc was raised from any of + * the system calls. */ + if( ( ulPC >= ( uint32_t ) __syscalls_flash_start__ ) && + ( ulPC <= ( uint32_t ) __syscalls_flash_end__ ) ) + { + vRaisePrivilege(); + } + break; + #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) */ + + #if ( configENABLE_MPU == 1 ) + case portSVC_YIELD: + vPortYield(); + break; + #endif /* configENABLE_MPU == 1 */ default: /* Incorrect SVC call. */ @@ -1154,12 +1199,11 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO { /* Extended frame i.e. FPU in use. */ ulStackFrameSize = 26; - __asm volatile - ( + __asm volatile ( " vpush {s0} \n" /* Trigger lazy stacking. */ " vpop {s0} \n" /* Nullify the affect of the above instruction. */ ::: "memory" - ); + ); } else { @@ -1171,7 +1215,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO { ulStackFrameSize = 8; } - #endif /* if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */ + #endif /* configENABLE_FPU || configENABLE_MVE */ /* Make space on the system call stack for the stack frame. */ pulSystemCallStack = pulSystemCallStack - ulStackFrameSize; @@ -1187,18 +1231,24 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO * point (i.e. the caller of the MPU_). We need to restore it * when we exit from the system call. */ pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry = pulTaskStack[ portOFFSET_TO_LR ]; - /* Store the value of the PSPLIM register before the SVC was raised. * We need to restore it when we exit from the system call. */ - __asm volatile ( "mrs %0, psplim" : "=r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) ); + #if ( portUSE_PSPLIM_REGISTER == 1 ) + { + __asm volatile ( "mrs %0, psplim" : "=r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) ); + } + #endif /* Use the pulSystemCallStack in thread mode. */ __asm volatile ( "msr psp, %0" : : "r" ( pulSystemCallStack ) ); - __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) ); + #if ( portUSE_PSPLIM_REGISTER == 1 ) + { + __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) ); + } + #endif /* Start executing the system call upon returning from this handler. */ pulSystemCallStack[ portOFFSET_TO_PC ] = uxSystemCallImplementations[ ucSystemCallNumber ]; - /* Raise a request to exit from the system call upon finishing the * system call. */ pulSystemCallStack[ portOFFSET_TO_LR ] = ( uint32_t ) vRequestSystemCallExit; @@ -1224,14 +1274,13 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO pulSystemCallStack[ portOFFSET_TO_PSR ] &= ( ~portPSR_STACK_PADDING_MASK ); /* Raise the privilege for the duration of the system call. */ - __asm volatile - ( + __asm volatile ( " mrs r0, control \n" /* Obtain current control value. */ " movs r1, #1 \n" /* r1 = 1. */ " bics r0, r1 \n" /* Clear nPRIV bit. */ " msr control, r0 \n" /* Write back new control value. */ ::: "r0", "r1", "memory" - ); + ); } } @@ -1293,12 +1342,11 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO { /* Extended frame i.e. FPU in use. */ ulStackFrameSize = 26; - __asm volatile - ( + __asm volatile ( " vpush {s0} \n" /* Trigger lazy stacking. */ " vpop {s0} \n" /* Nullify the affect of the above instruction. */ ::: "memory" - ); + ); } else { @@ -1310,7 +1358,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO { ulStackFrameSize = 8; } - #endif /* if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */ + #endif /* configENABLE_FPU || configENABLE_MVE */ /* Make space on the task stack for the stack frame. */ pulTaskStack = pulTaskStack - ulStackFrameSize; @@ -1332,7 +1380,11 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO /* Restore the PSPLIM register to what it was at the time of * system call entry. */ - __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) ); + #if ( portUSE_PSPLIM_REGISTER == 1 ) + { + __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) ); + } + #endif /* If the hardware used padding to force the stack pointer * to be double word aligned, set the stacked xPSR bit[9], @@ -1350,14 +1402,13 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO pxMpuSettings->xSystemCallStackInfo.pulTaskStack = NULL; /* Drop the privilege before returning to the thread mode. */ - __asm volatile - ( + __asm volatile ( " mrs r0, control \n" /* Obtain current control value. */ " movs r1, #1 \n" /* r1 = 1. */ " orrs r0, r1 \n" /* Set nPRIV bit. */ " msr control, r0 \n" /* Write back new control value. */ ::: "r0", "r1", "memory" - ); + ); } } @@ -1410,21 +1461,21 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO xMPUSettings->ulContext[ ulIndex ] = 0x11111111; /* r11. */ ulIndex++; - xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pvParameters; /* r0. */ + xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pvParameters; /* r0. */ ulIndex++; - xMPUSettings->ulContext[ ulIndex ] = 0x01010101; /* r1. */ + xMPUSettings->ulContext[ ulIndex ] = 0x01010101; /* r1. */ ulIndex++; - xMPUSettings->ulContext[ ulIndex ] = 0x02020202; /* r2. */ + xMPUSettings->ulContext[ ulIndex ] = 0x02020202; /* r2. */ ulIndex++; - xMPUSettings->ulContext[ ulIndex ] = 0x03030303; /* r3. */ + xMPUSettings->ulContext[ ulIndex ] = 0x03030303; /* r3. */ ulIndex++; - xMPUSettings->ulContext[ ulIndex ] = 0x12121212; /* r12. */ + xMPUSettings->ulContext[ ulIndex ] = 0x12121212; /* r12. */ ulIndex++; xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portTASK_RETURN_ADDRESS; /* LR. */ ulIndex++; - xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxCode; /* PC. */ + xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxCode; /* PC. */ ulIndex++; - xMPUSettings->ulContext[ ulIndex ] = portINITIAL_XPSR; /* xPSR. */ + xMPUSettings->ulContext[ ulIndex ] = portINITIAL_XPSR; /* xPSR. */ ulIndex++; #if ( configENABLE_TRUSTZONE == 1 ) @@ -1435,8 +1486,9 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO #endif /* configENABLE_TRUSTZONE */ xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) ( pxTopOfStack - 8 ); /* PSP with the hardware saved stack. */ ulIndex++; - xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxEndOfStack; /* PSPLIM. */ + xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxEndOfStack; /* PSPLIM. */ ulIndex++; + if( xRunPrivileged == pdTRUE ) { xMPUSettings->ulTaskFlags |= portTASK_IS_PRIVILEGED_FLAG; @@ -1449,6 +1501,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portINITIAL_CONTROL_UNPRIVILEGED; /* CONTROL. */ ulIndex++; } + xMPUSettings->ulContext[ ulIndex ] = portINITIAL_EXC_RETURN; /* LR (EXC_RETURN). */ ulIndex++; @@ -1483,7 +1536,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO * interrupt. */ #if ( portPRELOAD_REGISTERS == 0 ) { - pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */ + pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */ *pxTopOfStack = portINITIAL_XPSR; /* xPSR. */ pxTopOfStack--; *pxTopOfStack = ( StackType_t ) pxCode; /* PC. */ @@ -1505,7 +1558,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO } #else /* portPRELOAD_REGISTERS */ { - pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */ + pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */ *pxTopOfStack = portINITIAL_XPSR; /* xPSR. */ pxTopOfStack--; *pxTopOfStack = ( StackType_t ) pxCode; /* PC. */ @@ -1540,7 +1593,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO pxTopOfStack--; *pxTopOfStack = portINITIAL_EXC_RETURN; /* EXC_RETURN. */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */ + *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */ #if ( configENABLE_TRUSTZONE == 1 ) { @@ -1559,22 +1612,52 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */ { - #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) ) + /* An application can install FreeRTOS interrupt handlers in one of the + * folllowing ways: + * 1. Direct Routing - Install the functions SVC_Handler and PendSV_Handler + * for SVCall and PendSV interrupts respectively. + * 2. Indirect Routing - Install separate handlers for SVCall and PendSV + * interrupts and route program control from those handlers to + * SVC_Handler and PendSV_Handler functions. + * + * Applications that use Indirect Routing must set + * configCHECK_HANDLER_INSTALLATION to 0 in their FreeRTOSConfig.h. Direct + * routing, which is validated here when configCHECK_HANDLER_INSTALLATION + * is 1, should be preferred when possible. */ + #if ( configCHECK_HANDLER_INSTALLATION == 1 ) + { + const portISR_t * const pxVectorTable = portSCB_VTOR_REG; + + /* Validate that the application has correctly installed the FreeRTOS + * handlers for SVCall and PendSV interrupts. We do not check the + * installation of the SysTick handler because the application may + * choose to drive the RTOS tick using a timer other than the SysTick + * timer by overriding the weak function vPortSetupTimerInterrupt(). + * + * Assertion failures here indicate incorrect installation of the + * FreeRTOS handlers. For help installing the FreeRTOS handlers, see + * https://www.FreeRTOS.org/FAQHelp.html. + * + * Systems with a configurable address for the interrupt vector table + * can also encounter assertion failures or even system faults here if + * VTOR is not set correctly to point to the application's vector table. */ + configASSERT( pxVectorTable[ portVECTOR_INDEX_SVC ] == SVC_Handler ); + configASSERT( pxVectorTable[ portVECTOR_INDEX_PENDSV ] == PendSV_Handler ); + } + #endif /* configCHECK_HANDLER_INSTALLATION */ + + #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) { - volatile uint32_t ulOriginalPriority; volatile uint32_t ulImplementedPrioBits = 0; volatile uint8_t ucMaxPriorityValue; /* Determine the maximum priority from which ISR safe FreeRTOS API - * functions can be called. ISR safe functions are those that end in - * "FromISR". FreeRTOS maintains separate thread and ISR API functions to + * functions can be called. ISR safe functions are those that end in + * "FromISR". FreeRTOS maintains separate thread and ISR API functions to * ensure interrupt entry is as fast and simple as possible. * - * Save the interrupt priority value that is about to be clobbered. */ - ulOriginalPriority = portNVIC_SHPR2_REG; - - /* Determine the number of priority bits available. First write to all - * possible bits. */ + * First, determine the number of priority bits available. Write to all + * possible bits in the priority setting for SVCall. */ portNVIC_SHPR2_REG = 0xFF000000; /* Read the value back to see how many bits stuck. */ @@ -1593,11 +1676,10 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */ /* Check that the bits not implemented in hardware are zero in * configMAX_SYSCALL_INTERRUPT_PRIORITY. */ - configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( ~ucMaxPriorityValue ) ) == 0U ); + configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( uint8_t ) ( ~( uint32_t ) ucMaxPriorityValue ) ) == 0U ); /* Calculate the maximum acceptable priority group value for the number * of bits read back. */ - while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE ) { ulImplementedPrioBits++; @@ -1635,16 +1717,14 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */ * register. */ ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT; ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK; - - /* Restore the clobbered interrupt priority register to its original - * value. */ - portNVIC_SHPR2_REG = ulOriginalPriority; } - #endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) ) */ + #endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */ - /* Make PendSV, CallSV and SysTick the same priority as the kernel. */ + /* Make PendSV and SysTick the lowest priority interrupts, and make SVCall + * the highest priority. */ portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI; portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI; + portNVIC_SHPR2_REG = 0; #if ( configENABLE_MPU == 1 ) { @@ -1701,6 +1781,7 @@ void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */ int32_t lIndex = 0; #if defined( __ARMCC_VERSION ) + /* Declaration when these variable are defined in code instead of being * exported from linker scripts. */ extern uint32_t * __privileged_sram_start__; @@ -1886,7 +1967,7 @@ BaseType_t xPortIsInsideInterrupt( void ) } /*-----------------------------------------------------------*/ -#if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) ) +#if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) void vPortValidateInterruptPriority( void ) { @@ -1944,7 +2025,7 @@ BaseType_t xPortIsInsideInterrupt( void ) configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue ); } -#endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) ) */ +#endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */ /*-----------------------------------------------------------*/ #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) diff --git a/Source/portable/GCC/ARM_CM33/non_secure/portasm.c b/Source/portable/GCC/ARM_CM33/non_secure/portasm.c index 7431c98f1..451e0abb7 100644 --- a/Source/portable/GCC/ARM_CM33/non_secure/portasm.c +++ b/Source/portable/GCC/ARM_CM33/non_secure/portasm.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -75,16 +75,16 @@ " ldmia r0!, {r4-r11} \n" /* Read 4 set of RBAR/RLAR registers from TCB. */ " stmia r2, {r4-r11} \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */ " \n" - #if ( configTOTAL_MPU_REGIONS == 16 ) - " movs r3, #8 \n" /* r3 = 8. */ - " str r3, [r1] \n" /* Program RNR = 8. */ - " ldmia r0!, {r4-r11} \n" /* Read 4 set of RBAR/RLAR registers from TCB. */ - " stmia r2, {r4-r11} \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */ - " movs r3, #12 \n" /* r3 = 12. */ - " str r3, [r1] \n" /* Program RNR = 12. */ - " ldmia r0!, {r4-r11} \n" /* Read 4 set of RBAR/RLAR registers from TCB. */ - " stmia r2, {r4-r11} \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */ - #endif /* configTOTAL_MPU_REGIONS == 16 */ + #if ( configTOTAL_MPU_REGIONS == 16 ) + " movs r3, #8 \n" /* r3 = 8. */ + " str r3, [r1] \n" /* Program RNR = 8. */ + " ldmia r0!, {r4-r11} \n" /* Read 4 set of RBAR/RLAR registers from TCB. */ + " stmia r2, {r4-r11} \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */ + " movs r3, #12 \n" /* r3 = 12. */ + " str r3, [r1] \n" /* Program RNR = 12. */ + " ldmia r0!, {r4-r11} \n" /* Read 4 set of RBAR/RLAR registers from TCB. */ + " stmia r2, {r4-r11} \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */ + #endif /* configTOTAL_MPU_REGIONS == 16 */ " \n" " ldr r1, xMPUCTRLConst2 \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */ " ldr r2, [r1] \n" /* Read the value of MPU_CTRL. */ @@ -294,15 +294,15 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att " save_general_regs: \n" " mrs r3, psp \n" " \n" - #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) - " add r3, r3, #0x20 \n" /* Move r3 to location where s0 is saved. */ - " tst lr, #0x10 \n" - " ittt eq \n" - " vstmiaeq r2!, {s16-s31} \n" /* Store s16-s31. */ - " vldmiaeq r3, {s0-s16} \n" /* Copy hardware saved FP context into s0-s16. */ - " vstmiaeq r2!, {s0-s16} \n" /* Store hardware saved FP context. */ - " sub r3, r3, #0x20 \n" /* Set r3 back to the location of hardware saved context. */ - #endif /* configENABLE_FPU || configENABLE_MVE */ + #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) + " add r3, r3, #0x20 \n" /* Move r3 to location where s0 is saved. */ + " tst lr, #0x10 \n" + " ittt eq \n" + " vstmiaeq r2!, {s16-s31} \n" /* Store s16-s31. */ + " vldmiaeq r3, {s0-s16} \n" /* Copy hardware saved FP context into s0-s16. */ + " vstmiaeq r2!, {s0-s16} \n" /* Store hardware saved FP context. */ + " sub r3, r3, #0x20 \n" /* Set r3 back to the location of hardware saved context. */ + #endif /* configENABLE_FPU || configENABLE_MVE */ " \n" " stmia r2!, {r4-r11} \n" /* Store r4-r11. */ " ldmia r3, {r4-r11} \n" /* Copy the hardware saved context into r4-r11. */ @@ -348,16 +348,16 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att " ldmia r0!, {r4-r11} \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */ " stmia r2, {r4-r11} \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */ " \n" - #if ( configTOTAL_MPU_REGIONS == 16 ) - " movs r3, #8 \n" /* r3 = 8. */ - " str r3, [r1] \n" /* Program RNR = 8. */ - " ldmia r0!, {r4-r11} \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */ - " stmia r2, {r4-r11} \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */ - " movs r3, #12 \n" /* r3 = 12. */ - " str r3, [r1] \n" /* Program RNR = 12. */ - " ldmia r0!, {r4-r11} \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */ - " stmia r2, {r4-r11} \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */ - #endif /* configTOTAL_MPU_REGIONS == 16 */ + #if ( configTOTAL_MPU_REGIONS == 16 ) + " movs r3, #8 \n" /* r3 = 8. */ + " str r3, [r1] \n" /* Program RNR = 8. */ + " ldmia r0!, {r4-r11} \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */ + " stmia r2, {r4-r11} \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */ + " movs r3, #12 \n" /* r3 = 12. */ + " str r3, [r1] \n" /* Program RNR = 12. */ + " ldmia r0!, {r4-r11} \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */ + " stmia r2, {r4-r11} \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */ + #endif /* configTOTAL_MPU_REGIONS == 16 */ " \n" " ldr r1, xMPUCTRLConst \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */ " ldr r2, [r1] \n" /* Read the value of MPU_CTRL. */ @@ -393,13 +393,13 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att " ldmdb r2!, {r4-r11} \n" /* r4-r11 contain hardware saved context. */ " stmia r3!, {r4-r11} \n" /* Copy the hardware saved context on the task stack. */ " ldmdb r2!, {r4-r11} \n" /* r4-r11 restored. */ - #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) - " tst lr, #0x10 \n" - " ittt eq \n" - " vldmdbeq r2!, {s0-s16} \n" /* s0-s16 contain hardware saved FP context. */ - " vstmiaeq r3!, {s0-s16} \n" /* Copy hardware saved FP context on the task stack. */ - " vldmdbeq r2!, {s16-s31} \n" /* Restore s16-s31. */ - #endif /* configENABLE_FPU || configENABLE_MVE */ + #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) + " tst lr, #0x10 \n" + " ittt eq \n" + " vldmdbeq r2!, {s0-s16} \n" /* s0-s16 contain hardware saved FP context. */ + " vstmiaeq r3!, {s0-s16} \n" /* Copy hardware saved FP context on the task stack. */ + " vldmdbeq r2!, {s16-s31} \n" /* Restore s16-s31. */ + #endif /* configENABLE_FPU || configENABLE_MVE */ " \n" " restore_context_done: \n" " str r2, [r1] \n" /* Save the location where the context should be saved next as the first member of TCB. */ @@ -452,11 +452,11 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att " save_ns_context: \n" " ldr r3, pxCurrentTCBConst \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ " ldr r1, [r3] \n" /* Read pxCurrentTCB. */ - #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) - " tst lr, #0x10 \n" /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */ - " it eq \n" - " vstmdbeq r2!, {s16-s31} \n" /* Store the additional FP context registers which are not saved automatically. */ - #endif /* configENABLE_FPU || configENABLE_MVE */ + #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) + " tst lr, #0x10 \n" /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */ + " it eq \n" + " vstmdbeq r2!, {s16-s31} \n" /* Store the additional FP context registers which are not saved automatically. */ + #endif /* configENABLE_FPU || configENABLE_MVE */ " subs r2, r2, #44 \n" /* Make space for xSecureContext, PSPLIM, LR and the remaining registers on the stack. */ " str r2, [r1] \n" /* Save the new top of stack in TCB. */ " adds r2, r2, #12 \n" /* r2 = r2 + 12. */ @@ -498,11 +498,11 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att " \n" " restore_ns_context: \n" " ldmia r2!, {r4-r11} \n" /* Restore the registers that are not automatically restored. */ - #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) - " tst lr, #0x10 \n" /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */ - " it eq \n" - " vldmiaeq r2!, {s16-s31} \n" /* Restore the additional FP context registers which are not restored automatically. */ - #endif /* configENABLE_FPU || configENABLE_MVE */ + #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) + " tst lr, #0x10 \n" /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */ + " it eq \n" + " vldmiaeq r2!, {s16-s31} \n" /* Restore the additional FP context registers which are not restored automatically. */ + #endif /* configENABLE_FPU || configENABLE_MVE */ " msr psp, r2 \n" /* Remember the new top of stack for the task. */ " bx lr \n" " \n" diff --git a/Source/portable/GCC/ARM_CM33/non_secure/portasm.h b/Source/portable/GCC/ARM_CM33/non_secure/portasm.h index f64ceb525..c6d2ebd58 100644 --- a/Source/portable/GCC/ARM_CM33/non_secure/portasm.h +++ b/Source/portable/GCC/ARM_CM33/non_secure/portasm.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/Source/portable/GCC/ARM_CM33/non_secure/portmacro.h b/Source/portable/GCC/ARM_CM33/non_secure/portmacro.h index cc798707e..a5416a66a 100644 --- a/Source/portable/GCC/ARM_CM33/non_secure/portmacro.h +++ b/Source/portable/GCC/ARM_CM33/non_secure/portmacro.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -48,9 +48,9 @@ /** * Architecture specifics. */ -#define portARCH_NAME "Cortex-M33" -#define portHAS_BASEPRI 1 -#define portDONT_DISCARD __attribute__( ( used ) ) +#define portARCH_NAME "Cortex-M33" +#define portHAS_ARMV8M_MAIN_EXTENSION 1 +#define portDONT_DISCARD __attribute__( ( used ) ) /*-----------------------------------------------------------*/ /* ARMv8-M common port configurations. */ @@ -60,8 +60,8 @@ /** * @brief Critical section management. */ -#define portDISABLE_INTERRUPTS() ulSetInterruptMask() -#define portENABLE_INTERRUPTS() vClearInterruptMask( 0 ) +#define portDISABLE_INTERRUPTS() ulSetInterruptMask() +#define portENABLE_INTERRUPTS() vClearInterruptMask( 0 ) /*-----------------------------------------------------------*/ /* *INDENT-OFF* */ diff --git a/Source/portable/GCC/ARM_CM33/non_secure/portmacrocommon.h b/Source/portable/GCC/ARM_CM33/non_secure/portmacrocommon.h index 6f666da22..33f21d85b 100644 --- a/Source/portable/GCC/ARM_CM33/non_secure/portmacrocommon.h +++ b/Source/portable/GCC/ARM_CM33/non_secure/portmacrocommon.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -117,7 +117,7 @@ extern uint32_t ulSetInterruptMask( void ) /* __attribute__(( naked )) PRIVILEGE extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */; #if ( configENABLE_TRUSTZONE == 1 ) - extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize ); /* __attribute__ (( naked )) */ + extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize ); /* __attribute__ (( naked )) */ extern void vPortFreeSecureContext( uint32_t * pulTCB ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */; #endif /* configENABLE_TRUSTZONE */ @@ -188,13 +188,13 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P #if ( configENABLE_MPU == 1 ) - /** - * @brief Settings to define an MPU region. - */ +/** + * @brief Settings to define an MPU region. + */ typedef struct MPURegionSettings { - uint32_t ulRBAR; /**< RBAR for the region. */ - uint32_t ulRLAR; /**< RLAR for the region. */ + uint32_t ulRBAR; /**< RBAR for the region. */ + uint32_t ulRLAR; /**< RLAR for the region. */ } MPURegionSettings_t; #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) @@ -203,9 +203,9 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P #error configSYSTEM_CALL_STACK_SIZE must be defined to the desired size of the system call stack in words for using MPU wrappers v2. #endif - /** - * @brief System call stack. - */ +/** + * @brief System call stack. + */ typedef struct SYSTEM_CALL_STACK_INFO { uint32_t ulSystemCallStackBuffer[ configSYSTEM_CALL_STACK_SIZE ]; @@ -218,74 +218,74 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P #endif /* configUSE_MPU_WRAPPERS_V1 == 0 */ - /** - * @brief MPU settings as stored in the TCB. - */ +/** + * @brief MPU settings as stored in the TCB. + */ #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) - #if( configENABLE_TRUSTZONE == 1 ) + #if ( configENABLE_TRUSTZONE == 1 ) - /* - * +-----------+---------------+----------+-----------------+------------------------------+-----+ - * | s16-s31 | s0-s15, FPSCR | r4-r11 | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, | | - * | | | | PC, xPSR | CONTROL, EXC_RETURN | | - * +-----------+---------------+----------+-----------------+------------------------------+-----+ - * - * <-----------><--------------><---------><----------------><-----------------------------><----> - * 16 16 8 8 5 1 - */ - #define MAX_CONTEXT_SIZE 54 +/* + * +-----------+---------------+----------+-----------------+------------------------------+-----+ + * | s16-s31 | s0-s15, FPSCR | r4-r11 | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, | | + * | | | | PC, xPSR | CONTROL, EXC_RETURN | | + * +-----------+---------------+----------+-----------------+------------------------------+-----+ + * + * <-----------><--------------><---------><----------------><-----------------------------><----> + * 16 16 8 8 5 1 + */ + #define MAX_CONTEXT_SIZE 54 #else /* #if( configENABLE_TRUSTZONE == 1 ) */ - /* - * +-----------+---------------+----------+-----------------+----------------------+-----+ - * | s16-s31 | s0-s15, FPSCR | r4-r11 | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL | | - * | | | | PC, xPSR | EXC_RETURN | | - * +-----------+---------------+----------+-----------------+----------------------+-----+ - * - * <-----------><--------------><---------><----------------><---------------------><----> - * 16 16 8 8 4 1 - */ - #define MAX_CONTEXT_SIZE 53 +/* + * +-----------+---------------+----------+-----------------+----------------------+-----+ + * | s16-s31 | s0-s15, FPSCR | r4-r11 | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL | | + * | | | | PC, xPSR | EXC_RETURN | | + * +-----------+---------------+----------+-----------------+----------------------+-----+ + * + * <-----------><--------------><---------><----------------><---------------------><----> + * 16 16 8 8 4 1 + */ + #define MAX_CONTEXT_SIZE 53 #endif /* #if( configENABLE_TRUSTZONE == 1 ) */ #else /* #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */ - #if( configENABLE_TRUSTZONE == 1 ) + #if ( configENABLE_TRUSTZONE == 1 ) - /* - * +----------+-----------------+------------------------------+-----+ - * | r4-r11 | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, | | - * | | PC, xPSR | CONTROL, EXC_RETURN | | - * +----------+-----------------+------------------------------+-----+ - * - * <---------><----------------><------------------------------><----> - * 8 8 5 1 - */ - #define MAX_CONTEXT_SIZE 22 +/* + * +----------+-----------------+------------------------------+-----+ + * | r4-r11 | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, | | + * | | PC, xPSR | CONTROL, EXC_RETURN | | + * +----------+-----------------+------------------------------+-----+ + * + * <---------><----------------><------------------------------><----> + * 8 8 5 1 + */ + #define MAX_CONTEXT_SIZE 22 #else /* #if( configENABLE_TRUSTZONE == 1 ) */ - /* - * +----------+-----------------+----------------------+-----+ - * | r4-r11 | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL | | - * | | PC, xPSR | EXC_RETURN | | - * +----------+-----------------+----------------------+-----+ - * - * <---------><----------------><----------------------><----> - * 8 8 4 1 - */ - #define MAX_CONTEXT_SIZE 21 +/* + * +----------+-----------------+----------------------+-----+ + * | r4-r11 | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL | | + * | | PC, xPSR | EXC_RETURN | | + * +----------+-----------------+----------------------+-----+ + * + * <---------><----------------><----------------------><----> + * 8 8 4 1 + */ + #define MAX_CONTEXT_SIZE 21 #endif /* #if( configENABLE_TRUSTZONE == 1 ) */ #endif /* #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */ - /* Flags used for xMPU_SETTINGS.ulTaskFlags member. */ - #define portSTACK_FRAME_HAS_PADDING_FLAG ( 1UL << 0UL ) - #define portTASK_IS_PRIVILEGED_FLAG ( 1UL << 1UL ) +/* Flags used for xMPU_SETTINGS.ulTaskFlags member. */ + #define portSTACK_FRAME_HAS_PADDING_FLAG ( 1UL << 0UL ) + #define portTASK_IS_PRIVILEGED_FLAG ( 1UL << 1UL ) /* Size of an Access Control List (ACL) entry in bits. */ #define portACL_ENTRY_SIZE_BITS ( 32U ) @@ -313,7 +313,7 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P * system calls. */ #ifdef configASSERT - #if ( portHAS_BASEPRI == 1 ) + #if ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) void vPortValidateInterruptPriority( void ); #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() vPortValidateInterruptPriority() #endif @@ -333,12 +333,29 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P /** * @brief Scheduler utilities. */ -#define portYIELD() vPortYield() +#if ( configENABLE_MPU == 1 ) + #define portYIELD() __asm volatile ( "svc %0" ::"i" ( portSVC_YIELD ) : "memory" ) + #define portYIELD_WITHIN_API() vPortYield() +#else + #define portYIELD() vPortYield() + #define portYIELD_WITHIN_API() vPortYield() +#endif + #define portNVIC_INT_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed04 ) ) #define portNVIC_PENDSVSET_BIT ( 1UL << 28UL ) -#define portEND_SWITCHING_ISR( xSwitchRequired ) \ - do { if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; } \ - while( 0 ) +#define portEND_SWITCHING_ISR( xSwitchRequired ) \ + do \ + { \ + if( xSwitchRequired ) \ + { \ + traceISR_EXIT_TO_SCHEDULER(); \ + portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; \ + } \ + else \ + { \ + traceISR_EXIT(); \ + } \ + } while( 0 ) #define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x ) /*-----------------------------------------------------------*/ @@ -424,12 +441,12 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P extern BaseType_t xPortIsTaskPrivileged( void ); - /** - * @brief Checks whether or not the calling task is privileged. - * - * @return pdTRUE if the calling task is privileged, pdFALSE otherwise. - */ - #define portIS_TASK_PRIVILEGED() xPortIsTaskPrivileged() +/** + * @brief Checks whether or not the calling task is privileged. + * + * @return pdTRUE if the calling task is privileged, pdFALSE otherwise. + */ + #define portIS_TASK_PRIVILEGED() xPortIsTaskPrivileged() #endif /* configENABLE_MPU == 1 */ /*-----------------------------------------------------------*/ @@ -440,6 +457,56 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P #define portMEMORY_BARRIER() __asm volatile ( "" ::: "memory" ) /*-----------------------------------------------------------*/ +/* Select correct value of configUSE_PORT_OPTIMISED_TASK_SELECTION + * based on whether or not Mainline extension is implemented. */ +#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION + #if ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) + #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1 + #else + #define configUSE_PORT_OPTIMISED_TASK_SELECTION 0 + #endif +#endif /* #ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION */ + +/** + * @brief Port-optimised task selection. + */ +#if ( configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 ) + +/** + * @brief Count the number of leading zeros in a 32-bit value. + */ + static portFORCE_INLINE uint32_t ulPortCountLeadingZeros( uint32_t ulBitmap ) + { + uint32_t ulReturn; + + __asm volatile ( "clz %0, %1" : "=r" ( ulReturn ) : "r" ( ulBitmap ) : "memory" ); + + return ulReturn; + } + +/* Check the configuration. */ + #if ( configMAX_PRIORITIES > 32 ) + #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 different priorities as tasks that share a priority will time slice. + #endif + + #if ( portHAS_ARMV8M_MAIN_EXTENSION == 0 ) + #error ARMv8-M baseline implementations (such as Cortex-M23) do not support port-optimised task selection. Please set configUSE_PORT_OPTIMISED_TASK_SELECTION to 0 or leave it undefined. + #endif + +/** + * @brief Store/clear the ready priorities in a bit map. + */ + #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) ) + #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) ) + +/** + * @brief Get the priority of the highest-priority task that is ready to execute. + */ + #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - ulPortCountLeadingZeros( ( uxReadyPriorities ) ) ) + +#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */ +/*-----------------------------------------------------------*/ + /* *INDENT-OFF* */ #ifdef __cplusplus } diff --git a/Source/portable/GCC/ARM_CM33/secure/secure_context.c b/Source/portable/GCC/ARM_CM33/secure/secure_context.c index e37dd9672..83b3dbce1 100644 --- a/Source/portable/GCC/ARM_CM33/secure/secure_context.c +++ b/Source/portable/GCC/ARM_CM33/secure/secure_context.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -65,7 +65,7 @@ * @brief Maximum number of secure contexts. */ #ifndef secureconfigMAX_SECURE_CONTEXTS - #define secureconfigMAX_SECURE_CONTEXTS 8UL + #define secureconfigMAX_SECURE_CONTEXTS 8UL #endif /*-----------------------------------------------------------*/ @@ -164,15 +164,15 @@ secureportNON_SECURE_CALLABLE void SecureContext_Init( void ) } #if ( configENABLE_MPU == 1 ) - { - /* Configure thread mode to use PSP and to be unprivileged. */ - secureportSET_CONTROL( securecontextCONTROL_VALUE_UNPRIVILEGED ); - } + { + /* Configure thread mode to use PSP and to be unprivileged. */ + secureportSET_CONTROL( securecontextCONTROL_VALUE_UNPRIVILEGED ); + } #else /* configENABLE_MPU */ - { - /* Configure thread mode to use PSP and to be privileged. */ - secureportSET_CONTROL( securecontextCONTROL_VALUE_PRIVILEGED ); - } + { + /* Configure thread mode to use PSP and to be privileged. */ + secureportSET_CONTROL( securecontextCONTROL_VALUE_PRIVILEGED ); + } #endif /* configENABLE_MPU */ } } @@ -219,16 +219,16 @@ secureportNON_SECURE_CALLABLE void SecureContext_Init( void ) if( pucStackMemory != NULL ) { /* Since stack grows down, the starting point will be the last - * location. Note that this location is next to the last - * allocated byte for stack (excluding the space for seal values) - * because the hardware decrements the stack pointer before - * writing i.e. if stack pointer is 0x2, a push operation will - * decrement the stack pointer to 0x1 and then write at 0x1. */ + * location. Note that this location is next to the last + * allocated byte for stack (excluding the space for seal values) + * because the hardware decrements the stack pointer before + * writing i.e. if stack pointer is 0x2, a push operation will + * decrement the stack pointer to 0x1 and then write at 0x1. */ xSecureContexts[ ulSecureContextIndex ].pucStackStart = pucStackMemory + ulSecureStackSize; /* Seal the created secure process stack. */ - *( uint32_t * )( pucStackMemory + ulSecureStackSize ) = securecontextSTACK_SEAL_VALUE; - *( uint32_t * )( pucStackMemory + ulSecureStackSize + 4 ) = securecontextSTACK_SEAL_VALUE; + *( uint32_t * ) ( pucStackMemory + ulSecureStackSize ) = securecontextSTACK_SEAL_VALUE; + *( uint32_t * ) ( pucStackMemory + ulSecureStackSize + 4 ) = securecontextSTACK_SEAL_VALUE; /* The stack cannot go beyond this location. This value is * programmed in the PSPLIM register on context switch.*/ @@ -237,32 +237,32 @@ secureportNON_SECURE_CALLABLE void SecureContext_Init( void ) xSecureContexts[ ulSecureContextIndex ].pvTaskHandle = pvTaskHandle; #if ( configENABLE_MPU == 1 ) + { + /* Store the correct CONTROL value for the task on the stack. + * This value is programmed in the CONTROL register on + * context switch. */ + pulCurrentStackPointer = ( uint32_t * ) xSecureContexts[ ulSecureContextIndex ].pucStackStart; + pulCurrentStackPointer--; + + if( ulIsTaskPrivileged ) { - /* Store the correct CONTROL value for the task on the stack. - * This value is programmed in the CONTROL register on - * context switch. */ - pulCurrentStackPointer = ( uint32_t * ) xSecureContexts[ ulSecureContextIndex ].pucStackStart; - pulCurrentStackPointer--; - - if( ulIsTaskPrivileged ) - { - *( pulCurrentStackPointer ) = securecontextCONTROL_VALUE_PRIVILEGED; - } - else - { - *( pulCurrentStackPointer ) = securecontextCONTROL_VALUE_UNPRIVILEGED; - } - - /* Store the current stack pointer. This value is programmed in - * the PSP register on context switch. */ - xSecureContexts[ ulSecureContextIndex ].pucCurrentStackPointer = ( uint8_t * ) pulCurrentStackPointer; + *( pulCurrentStackPointer ) = securecontextCONTROL_VALUE_PRIVILEGED; } - #else /* configENABLE_MPU */ + else { - /* Current SP is set to the starting of the stack. This - * value programmed in the PSP register on context switch. */ - xSecureContexts[ ulSecureContextIndex ].pucCurrentStackPointer = xSecureContexts[ ulSecureContextIndex ].pucStackStart; + *( pulCurrentStackPointer ) = securecontextCONTROL_VALUE_UNPRIVILEGED; } + + /* Store the current stack pointer. This value is programmed in + * the PSP register on context switch. */ + xSecureContexts[ ulSecureContextIndex ].pucCurrentStackPointer = ( uint8_t * ) pulCurrentStackPointer; + } + #else /* configENABLE_MPU */ + { + /* Current SP is set to the starting of the stack. This + * value programmed in the PSP register on context switch. */ + xSecureContexts[ ulSecureContextIndex ].pucCurrentStackPointer = xSecureContexts[ ulSecureContextIndex ].pucStackStart; + } #endif /* configENABLE_MPU */ /* Ensure to never return 0 as a valid context handle. */ @@ -275,7 +275,8 @@ secureportNON_SECURE_CALLABLE void SecureContext_Init( void ) } /*-----------------------------------------------------------*/ -secureportNON_SECURE_CALLABLE void SecureContext_FreeContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle ) +secureportNON_SECURE_CALLABLE void SecureContext_FreeContext( SecureContextHandle_t xSecureContextHandle, + void * pvTaskHandle ) { uint32_t ulIPSR, ulSecureContextIndex; @@ -306,7 +307,8 @@ secureportNON_SECURE_CALLABLE void SecureContext_FreeContext( SecureContextHandl } /*-----------------------------------------------------------*/ -secureportNON_SECURE_CALLABLE void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle ) +secureportNON_SECURE_CALLABLE void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle, + void * pvTaskHandle ) { uint8_t * pucStackLimit; uint32_t ulSecureContextIndex; @@ -328,7 +330,8 @@ secureportNON_SECURE_CALLABLE void SecureContext_LoadContext( SecureContextHandl } /*-----------------------------------------------------------*/ -secureportNON_SECURE_CALLABLE void SecureContext_SaveContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle ) +secureportNON_SECURE_CALLABLE void SecureContext_SaveContext( SecureContextHandle_t xSecureContextHandle, + void * pvTaskHandle ) { uint8_t * pucStackLimit; uint32_t ulSecureContextIndex; diff --git a/Source/portable/GCC/ARM_CM33/secure/secure_context.h b/Source/portable/GCC/ARM_CM33/secure/secure_context.h index 2220ea646..40fdc276d 100644 --- a/Source/portable/GCC/ARM_CM33/secure/secure_context.h +++ b/Source/portable/GCC/ARM_CM33/secure/secure_context.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -38,12 +38,12 @@ /** * @brief PSP value when no secure context is loaded. */ -#define securecontextNO_STACK 0x0 +#define securecontextNO_STACK 0x0 /** * @brief Invalid context ID. */ -#define securecontextINVALID_CONTEXT_ID 0UL +#define securecontextINVALID_CONTEXT_ID 0UL /*-----------------------------------------------------------*/ /** @@ -108,7 +108,8 @@ void SecureContext_Init( void ); * @param[in] xSecureContextHandle Context handle corresponding to the * context to be freed. */ -void SecureContext_FreeContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle ); +void SecureContext_FreeContext( SecureContextHandle_t xSecureContextHandle, + void * pvTaskHandle ); /** * @brief Loads the given context. @@ -119,7 +120,8 @@ void SecureContext_FreeContext( SecureContextHandle_t xSecureContextHandle, void * @param[in] xSecureContextHandle Context handle corresponding to the context * to be loaded. */ -void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle ); +void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle, + void * pvTaskHandle ); /** * @brief Saves the given context. @@ -130,6 +132,7 @@ void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle, void * @param[in] xSecureContextHandle Context handle corresponding to the context * to be saved. */ -void SecureContext_SaveContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle ); +void SecureContext_SaveContext( SecureContextHandle_t xSecureContextHandle, + void * pvTaskHandle ); #endif /* __SECURE_CONTEXT_H__ */ diff --git a/Source/portable/GCC/ARM_CM33/secure/secure_context_port.c b/Source/portable/GCC/ARM_CM33/secure/secure_context_port.c index d70822c06..31c1f7331 100644 --- a/Source/portable/GCC/ARM_CM33/secure/secure_context_port.c +++ b/Source/portable/GCC/ARM_CM33/secure/secure_context_port.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/Source/portable/GCC/ARM_CM33/secure/secure_heap.c b/Source/portable/GCC/ARM_CM33/secure/secure_heap.c index 19f7c2354..d9789404b 100644 --- a/Source/portable/GCC/ARM_CM33/secure/secure_heap.c +++ b/Source/portable/GCC/ARM_CM33/secure/secure_heap.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -62,6 +62,22 @@ /* Assumes 8bit bytes! */ #define secureheapBITS_PER_BYTE ( ( size_t ) 8 ) + +/* Max value that fits in a size_t type. */ +#define secureheapSIZE_MAX ( ~( ( size_t ) 0 ) ) + +/* Check if adding a and b will result in overflow. */ +#define secureheapADD_WILL_OVERFLOW( a, b ) ( ( a ) > ( secureheapSIZE_MAX - ( b ) ) ) + +/* MSB of the xBlockSize member of an BlockLink_t structure is used to track + * the allocation status of a block. When MSB of the xBlockSize member of + * an BlockLink_t structure is set then the block belongs to the application. + * When the bit is free the block is still part of the free heap space. */ +#define secureheapBLOCK_ALLOCATED_BITMASK ( ( ( size_t ) 1 ) << ( ( sizeof( size_t ) * secureheapBITS_PER_BYTE ) - 1 ) ) +#define secureheapBLOCK_SIZE_IS_VALID( xBlockSize ) ( ( ( xBlockSize ) & secureheapBLOCK_ALLOCATED_BITMASK ) == 0 ) +#define secureheapBLOCK_IS_ALLOCATED( pxBlock ) ( ( ( pxBlock->xBlockSize ) & secureheapBLOCK_ALLOCATED_BITMASK ) != 0 ) +#define secureheapALLOCATE_BLOCK( pxBlock ) ( ( pxBlock->xBlockSize ) |= secureheapBLOCK_ALLOCATED_BITMASK ) +#define secureheapFREE_BLOCK( pxBlock ) ( ( pxBlock->xBlockSize ) &= ~secureheapBLOCK_ALLOCATED_BITMASK ) /*-----------------------------------------------------------*/ /* Allocate the memory for the heap. */ @@ -123,14 +139,6 @@ static BlockLink_t * pxEnd = NULL; static size_t xFreeBytesRemaining = 0U; static size_t xMinimumEverFreeBytesRemaining = 0U; -/** - * @brief Gets set to the top bit of an size_t type. - * - * When this bit in the xBlockSize member of an BlockLink_t structure is set - * then the block belongs to the application. When the bit is free the block is - * still part of the free heap space. - */ -static size_t xBlockAllocatedBit = 0; /*-----------------------------------------------------------*/ static void prvHeapInit( void ) @@ -175,9 +183,6 @@ static void prvHeapInit( void ) /* Only one block exists - and it covers the entire usable heap space. */ xMinimumEverFreeBytesRemaining = pxFirstFreeBlock->xBlockSize; xFreeBytesRemaining = pxFirstFreeBlock->xBlockSize; - - /* Work out the position of the top bit in a size_t variable. */ - xBlockAllocatedBit = ( ( size_t ) 1 ) << ( ( sizeof( size_t ) * secureheapBITS_PER_BYTE ) - 1 ); } /*-----------------------------------------------------------*/ @@ -250,6 +255,7 @@ void * pvPortMalloc( size_t xWantedSize ) BlockLink_t * pxPreviousBlock; BlockLink_t * pxNewBlockLink; void * pvReturn = NULL; + size_t xAdditionalRequiredSize; /* If this is the first call to malloc then the heap will require * initialisation to setup the list of free blocks. */ @@ -262,25 +268,29 @@ void * pvPortMalloc( size_t xWantedSize ) mtCOVERAGE_TEST_MARKER(); } - /* Check the requested block size is not so large that the top bit is set. - * The top bit of the block size member of the BlockLink_t structure is used - * to determine who owns the block - the application or the kernel, so it - * must be free. */ - if( ( xWantedSize & xBlockAllocatedBit ) == 0 ) + if( xWantedSize > 0 ) { - /* The wanted size is increased so it can contain a BlockLink_t + /* The wanted size must be increased so it can contain a BlockLink_t * structure in addition to the requested amount of bytes. */ - if( xWantedSize > 0 ) + if( secureheapADD_WILL_OVERFLOW( xWantedSize, xHeapStructSize ) == 0 ) { xWantedSize += xHeapStructSize; - /* Ensure that blocks are always aligned to the required number of - * bytes. */ + /* Ensure that blocks are always aligned to the required number + * of bytes. */ if( ( xWantedSize & secureportBYTE_ALIGNMENT_MASK ) != 0x00 ) { /* Byte alignment required. */ - xWantedSize += ( secureportBYTE_ALIGNMENT - ( xWantedSize & secureportBYTE_ALIGNMENT_MASK ) ); - secureportASSERT( ( xWantedSize & secureportBYTE_ALIGNMENT_MASK ) == 0 ); + xAdditionalRequiredSize = secureportBYTE_ALIGNMENT - ( xWantedSize & secureportBYTE_ALIGNMENT_MASK ); + + if( secureheapADD_WILL_OVERFLOW( xWantedSize, xAdditionalRequiredSize ) == 0 ) + { + xWantedSize += xAdditionalRequiredSize; + } + else + { + xWantedSize = 0; + } } else { @@ -289,9 +299,20 @@ void * pvPortMalloc( size_t xWantedSize ) } else { - mtCOVERAGE_TEST_MARKER(); + xWantedSize = 0; } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + /* Check the requested block size is not so large that the top bit is set. + * The top bit of the block size member of the BlockLink_t structure is used + * to determine who owns the block - the application or the kernel, so it + * must be free. */ + if( secureheapBLOCK_SIZE_IS_VALID( xWantedSize ) != 0 ) + { if( ( xWantedSize > 0 ) && ( xWantedSize <= xFreeBytesRemaining ) ) { /* Traverse the list from the start (lowest address) block until @@ -334,7 +355,8 @@ void * pvPortMalloc( size_t xWantedSize ) pxBlock->xBlockSize = xWantedSize; /* Insert the new block into the list of free blocks. */ - prvInsertBlockIntoFreeList( pxNewBlockLink ); + pxNewBlockLink->pxNextFreeBlock = pxPreviousBlock->pxNextFreeBlock; + pxPreviousBlock->pxNextFreeBlock = pxNewBlockLink; } else { @@ -354,7 +376,7 @@ void * pvPortMalloc( size_t xWantedSize ) /* The block is being returned - it is allocated and owned by * the application and has no "next" block. */ - pxBlock->xBlockSize |= xBlockAllocatedBit; + secureheapALLOCATE_BLOCK( pxBlock ); pxBlock->pxNextFreeBlock = NULL; } else @@ -375,17 +397,17 @@ void * pvPortMalloc( size_t xWantedSize ) traceMALLOC( pvReturn, xWantedSize ); #if ( secureconfigUSE_MALLOC_FAILED_HOOK == 1 ) + { + if( pvReturn == NULL ) { - if( pvReturn == NULL ) - { - extern void vApplicationMallocFailedHook( void ); - vApplicationMallocFailedHook(); - } - else - { - mtCOVERAGE_TEST_MARKER(); - } + extern void vApplicationMallocFailedHook( void ); + vApplicationMallocFailedHook(); } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } #endif /* if ( secureconfigUSE_MALLOC_FAILED_HOOK == 1 ) */ secureportASSERT( ( ( ( size_t ) pvReturn ) & ( size_t ) secureportBYTE_ALIGNMENT_MASK ) == 0 ); @@ -408,16 +430,16 @@ void vPortFree( void * pv ) pxLink = ( void * ) puc; /* Check the block is actually allocated. */ - secureportASSERT( ( pxLink->xBlockSize & xBlockAllocatedBit ) != 0 ); + secureportASSERT( secureheapBLOCK_IS_ALLOCATED( pxLink ) != 0 ); secureportASSERT( pxLink->pxNextFreeBlock == NULL ); - if( ( pxLink->xBlockSize & xBlockAllocatedBit ) != 0 ) + if( secureheapBLOCK_IS_ALLOCATED( pxLink ) != 0 ) { if( pxLink->pxNextFreeBlock == NULL ) { /* The block is being returned to the heap - it is no longer * allocated. */ - pxLink->xBlockSize &= ~xBlockAllocatedBit; + secureheapFREE_BLOCK( pxLink ); secureportDISABLE_NON_SECURE_INTERRUPTS(); { diff --git a/Source/portable/GCC/ARM_CM33/secure/secure_heap.h b/Source/portable/GCC/ARM_CM33/secure/secure_heap.h index 75c9cb00b..cf5551046 100644 --- a/Source/portable/GCC/ARM_CM33/secure/secure_heap.h +++ b/Source/portable/GCC/ARM_CM33/secure/secure_heap.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/Source/portable/GCC/ARM_CM33/secure/secure_init.c b/Source/portable/GCC/ARM_CM33/secure/secure_init.c index f93bfce95..66d35eccc 100644 --- a/Source/portable/GCC/ARM_CM33/secure/secure_init.c +++ b/Source/portable/GCC/ARM_CM33/secure/secure_init.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -93,7 +93,7 @@ secureportNON_SECURE_CALLABLE void SecureInit_EnableNSFPUAccess( void ) * permitted. CP11 should be programmed to the same value as CP10. */ *( secureinitNSACR ) |= ( secureinitNSACR_CP10_MASK | secureinitNSACR_CP11_MASK ); - /* LSPENS = 0 ==> LSPEN is writable fron non-secure state. This ensures + /* LSPENS = 0 ==> LSPEN is writable from non-secure state. This ensures * that we can enable/disable lazy stacking in port.c file. */ *( secureinitFPCCR ) &= ~( secureinitFPCCR_LSPENS_MASK ); diff --git a/Source/portable/GCC/ARM_CM33/secure/secure_init.h b/Source/portable/GCC/ARM_CM33/secure/secure_init.h index e6c9da0b4..6404c5cc4 100644 --- a/Source/portable/GCC/ARM_CM33/secure/secure_init.h +++ b/Source/portable/GCC/ARM_CM33/secure/secure_init.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/Source/portable/GCC/ARM_CM33/secure/secure_port_macros.h b/Source/portable/GCC/ARM_CM33/secure/secure_port_macros.h index d7ac5833c..085108cc1 100644 --- a/Source/portable/GCC/ARM_CM33/secure/secure_port_macros.h +++ b/Source/portable/GCC/ARM_CM33/secure/secure_port_macros.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/Source/portable/GCC/ARM_CM33_NTZ/non_secure/mpu_wrappers_v2_asm.c b/Source/portable/GCC/ARM_CM33_NTZ/non_secure/mpu_wrappers_v2_asm.c index d247c92e0..052f97850 100644 --- a/Source/portable/GCC/ARM_CM33_NTZ/non_secure/mpu_wrappers_v2_asm.c +++ b/Source/portable/GCC/ARM_CM33_NTZ/non_secure/mpu_wrappers_v2_asm.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -365,31 +365,6 @@ } /*-----------------------------------------------------------*/ - char * MPU_pcTaskGetName( TaskHandle_t xTaskToQuery ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; - - char * MPU_pcTaskGetName( TaskHandle_t xTaskToQuery ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ - { - __asm volatile - ( - " .syntax unified \n" - " .extern MPU_pcTaskGetNameImpl \n" - " \n" - " push {r0} \n" - " mrs r0, control \n" - " tst r0, #1 \n" - " bne MPU_pcTaskGetName_Unpriv \n" - " MPU_pcTaskGetName_Priv: \n" - " pop {r0} \n" - " b MPU_pcTaskGetNameImpl \n" - " MPU_pcTaskGetName_Unpriv: \n" - " pop {r0} \n" - " svc %0 \n" - " \n" - : : "i" ( SYSTEM_CALL_pcTaskGetName ) : "memory" - ); - } -/*-----------------------------------------------------------*/ - #if ( configGENERATE_RUN_TIME_STATS == 1 ) configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetRunTimeCounter( const TaskHandle_t xTask ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; @@ -1512,31 +1487,27 @@ #if ( configUSE_TIMERS == 1 ) - BaseType_t MPU_xTimerGenericCommandEntry( const xTimerGenericCommandParams_t * pxParams ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + BaseType_t MPU_xTimerGenericCommandFromTaskEntry( const xTimerGenericCommandFromTaskParams_t * pxParams ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; - BaseType_t MPU_xTimerGenericCommandEntry( const xTimerGenericCommandParams_t * pxParams ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + BaseType_t MPU_xTimerGenericCommandFromTaskEntry( const xTimerGenericCommandFromTaskParams_t * pxParams ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ { __asm volatile ( - " .syntax unified \n" - " .extern MPU_xTimerGenericCommandPrivImpl \n" - " \n" - " push {r0} \n" - " mrs r0, ipsr \n" - " cmp r0, #0 \n" - " bne MPU_xTimerGenericCommand_Priv \n" - " mrs r0, control \n" - " tst r0, #1 \n" - " beq MPU_xTimerGenericCommand_Priv \n" - " MPU_xTimerGenericCommand_Unpriv: \n" - " pop {r0} \n" - " svc %0 \n" - " MPU_xTimerGenericCommand_Priv: \n" - " pop {r0} \n" - " b MPU_xTimerGenericCommandPrivImpl \n" - " \n" - " \n" - : : "i" ( SYSTEM_CALL_xTimerGenericCommand ) : "memory" + " .syntax unified \n" + " .extern MPU_xTimerGenericCommandFromTaskImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " bne MPU_xTimerGenericCommandFromTask_Unpriv \n" + " MPU_xTimerGenericCommandFromTask_Priv: \n" + " pop {r0} \n" + " b MPU_xTimerGenericCommandFromTaskImpl \n" + " MPU_xTimerGenericCommandFromTask_Unpriv: \n" + " pop {r0} \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xTimerGenericCommandFromTask ) : "memory" ); } diff --git a/Source/portable/GCC/ARM_CM33_NTZ/non_secure/port.c b/Source/portable/GCC/ARM_CM33_NTZ/non_secure/port.c index 9712ac353..230fe5fc2 100644 --- a/Source/portable/GCC/ARM_CM33_NTZ/non_secure/port.c +++ b/Source/portable/GCC/ARM_CM33_NTZ/non_secure/port.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -68,6 +68,22 @@ #if ( ( configRUN_FREERTOS_SECURE_ONLY == 1 ) && ( configENABLE_TRUSTZONE == 1 ) ) #error TrustZone needs to be disabled in order to run FreeRTOS on the Secure Side. #endif + +/** + * Cortex-M23 does not have non-secure PSPLIM. We should use PSPLIM on Cortex-M23 + * only when FreeRTOS runs on secure side. + */ +#if ( ( portHAS_ARMV8M_MAIN_EXTENSION == 0 ) && ( configRUN_FREERTOS_SECURE_ONLY == 0 ) ) + #define portUSE_PSPLIM_REGISTER 0 +#else + #define portUSE_PSPLIM_REGISTER 1 +#endif +/*-----------------------------------------------------------*/ + +/** + * @brief Prototype of all Interrupt Service Routines (ISRs). + */ +typedef void ( * portISR_t )( void ); /*-----------------------------------------------------------*/ /** @@ -91,10 +107,18 @@ /** * @brief Constants required to manipulate the SCB. */ -#define portSCB_SYS_HANDLER_CTRL_STATE_REG ( *( volatile uint32_t * ) 0xe000ed24 ) +#define portSCB_VTOR_REG ( *( ( portISR_t ** ) 0xe000ed08 ) ) +#define portSCB_SYS_HANDLER_CTRL_STATE_REG ( *( ( volatile uint32_t * ) 0xe000ed24 ) ) #define portSCB_MEM_FAULT_ENABLE_BIT ( 1UL << 16UL ) /*-----------------------------------------------------------*/ +/** + * @brief Constants used to check the installation of the FreeRTOS interrupt handlers. + */ +#define portVECTOR_INDEX_SVC ( 11 ) +#define portVECTOR_INDEX_PENDSV ( 14 ) +/*-----------------------------------------------------------*/ + /** * @brief Constants required to check the validity of an interrupt priority. */ @@ -111,8 +135,8 @@ /** * @brief Constants used during system call enter and exit. */ -#define portPSR_STACK_PADDING_MASK ( 1UL << 9UL ) -#define portEXC_RETURN_STACK_FRAME_TYPE_MASK ( 1UL << 4UL ) +#define portPSR_STACK_PADDING_MASK ( 1UL << 9UL ) +#define portEXC_RETURN_STACK_FRAME_TYPE_MASK ( 1UL << 4UL ) /*-----------------------------------------------------------*/ /** @@ -134,81 +158,81 @@ /** * @brief Offsets in the stack to the parameters when inside the SVC handler. */ -#define portOFFSET_TO_LR ( 5 ) -#define portOFFSET_TO_PC ( 6 ) -#define portOFFSET_TO_PSR ( 7 ) +#define portOFFSET_TO_LR ( 5 ) +#define portOFFSET_TO_PC ( 6 ) +#define portOFFSET_TO_PSR ( 7 ) /*-----------------------------------------------------------*/ /** * @brief Constants required to manipulate the MPU. */ -#define portMPU_TYPE_REG ( *( ( volatile uint32_t * ) 0xe000ed90 ) ) -#define portMPU_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed94 ) ) -#define portMPU_RNR_REG ( *( ( volatile uint32_t * ) 0xe000ed98 ) ) +#define portMPU_TYPE_REG ( *( ( volatile uint32_t * ) 0xe000ed90 ) ) +#define portMPU_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed94 ) ) +#define portMPU_RNR_REG ( *( ( volatile uint32_t * ) 0xe000ed98 ) ) -#define portMPU_RBAR_REG ( *( ( volatile uint32_t * ) 0xe000ed9c ) ) -#define portMPU_RLAR_REG ( *( ( volatile uint32_t * ) 0xe000eda0 ) ) +#define portMPU_RBAR_REG ( *( ( volatile uint32_t * ) 0xe000ed9c ) ) +#define portMPU_RLAR_REG ( *( ( volatile uint32_t * ) 0xe000eda0 ) ) -#define portMPU_RBAR_A1_REG ( *( ( volatile uint32_t * ) 0xe000eda4 ) ) -#define portMPU_RLAR_A1_REG ( *( ( volatile uint32_t * ) 0xe000eda8 ) ) +#define portMPU_RBAR_A1_REG ( *( ( volatile uint32_t * ) 0xe000eda4 ) ) +#define portMPU_RLAR_A1_REG ( *( ( volatile uint32_t * ) 0xe000eda8 ) ) -#define portMPU_RBAR_A2_REG ( *( ( volatile uint32_t * ) 0xe000edac ) ) -#define portMPU_RLAR_A2_REG ( *( ( volatile uint32_t * ) 0xe000edb0 ) ) +#define portMPU_RBAR_A2_REG ( *( ( volatile uint32_t * ) 0xe000edac ) ) +#define portMPU_RLAR_A2_REG ( *( ( volatile uint32_t * ) 0xe000edb0 ) ) -#define portMPU_RBAR_A3_REG ( *( ( volatile uint32_t * ) 0xe000edb4 ) ) -#define portMPU_RLAR_A3_REG ( *( ( volatile uint32_t * ) 0xe000edb8 ) ) +#define portMPU_RBAR_A3_REG ( *( ( volatile uint32_t * ) 0xe000edb4 ) ) +#define portMPU_RLAR_A3_REG ( *( ( volatile uint32_t * ) 0xe000edb8 ) ) -#define portMPU_MAIR0_REG ( *( ( volatile uint32_t * ) 0xe000edc0 ) ) -#define portMPU_MAIR1_REG ( *( ( volatile uint32_t * ) 0xe000edc4 ) ) +#define portMPU_MAIR0_REG ( *( ( volatile uint32_t * ) 0xe000edc0 ) ) +#define portMPU_MAIR1_REG ( *( ( volatile uint32_t * ) 0xe000edc4 ) ) -#define portMPU_RBAR_ADDRESS_MASK ( 0xffffffe0 ) /* Must be 32-byte aligned. */ -#define portMPU_RLAR_ADDRESS_MASK ( 0xffffffe0 ) /* Must be 32-byte aligned. */ +#define portMPU_RBAR_ADDRESS_MASK ( 0xffffffe0 ) /* Must be 32-byte aligned. */ +#define portMPU_RLAR_ADDRESS_MASK ( 0xffffffe0 ) /* Must be 32-byte aligned. */ -#define portMPU_RBAR_ACCESS_PERMISSIONS_MASK ( 3UL << 1UL ) +#define portMPU_RBAR_ACCESS_PERMISSIONS_MASK ( 3UL << 1UL ) -#define portMPU_MAIR_ATTR0_POS ( 0UL ) -#define portMPU_MAIR_ATTR0_MASK ( 0x000000ff ) +#define portMPU_MAIR_ATTR0_POS ( 0UL ) +#define portMPU_MAIR_ATTR0_MASK ( 0x000000ff ) -#define portMPU_MAIR_ATTR1_POS ( 8UL ) -#define portMPU_MAIR_ATTR1_MASK ( 0x0000ff00 ) +#define portMPU_MAIR_ATTR1_POS ( 8UL ) +#define portMPU_MAIR_ATTR1_MASK ( 0x0000ff00 ) -#define portMPU_MAIR_ATTR2_POS ( 16UL ) -#define portMPU_MAIR_ATTR2_MASK ( 0x00ff0000 ) +#define portMPU_MAIR_ATTR2_POS ( 16UL ) +#define portMPU_MAIR_ATTR2_MASK ( 0x00ff0000 ) -#define portMPU_MAIR_ATTR3_POS ( 24UL ) -#define portMPU_MAIR_ATTR3_MASK ( 0xff000000 ) +#define portMPU_MAIR_ATTR3_POS ( 24UL ) +#define portMPU_MAIR_ATTR3_MASK ( 0xff000000 ) -#define portMPU_MAIR_ATTR4_POS ( 0UL ) -#define portMPU_MAIR_ATTR4_MASK ( 0x000000ff ) +#define portMPU_MAIR_ATTR4_POS ( 0UL ) +#define portMPU_MAIR_ATTR4_MASK ( 0x000000ff ) -#define portMPU_MAIR_ATTR5_POS ( 8UL ) -#define portMPU_MAIR_ATTR5_MASK ( 0x0000ff00 ) +#define portMPU_MAIR_ATTR5_POS ( 8UL ) +#define portMPU_MAIR_ATTR5_MASK ( 0x0000ff00 ) -#define portMPU_MAIR_ATTR6_POS ( 16UL ) -#define portMPU_MAIR_ATTR6_MASK ( 0x00ff0000 ) +#define portMPU_MAIR_ATTR6_POS ( 16UL ) +#define portMPU_MAIR_ATTR6_MASK ( 0x00ff0000 ) -#define portMPU_MAIR_ATTR7_POS ( 24UL ) -#define portMPU_MAIR_ATTR7_MASK ( 0xff000000 ) +#define portMPU_MAIR_ATTR7_POS ( 24UL ) +#define portMPU_MAIR_ATTR7_MASK ( 0xff000000 ) -#define portMPU_RLAR_ATTR_INDEX0 ( 0UL << 1UL ) -#define portMPU_RLAR_ATTR_INDEX1 ( 1UL << 1UL ) -#define portMPU_RLAR_ATTR_INDEX2 ( 2UL << 1UL ) -#define portMPU_RLAR_ATTR_INDEX3 ( 3UL << 1UL ) -#define portMPU_RLAR_ATTR_INDEX4 ( 4UL << 1UL ) -#define portMPU_RLAR_ATTR_INDEX5 ( 5UL << 1UL ) -#define portMPU_RLAR_ATTR_INDEX6 ( 6UL << 1UL ) -#define portMPU_RLAR_ATTR_INDEX7 ( 7UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX0 ( 0UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX1 ( 1UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX2 ( 2UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX3 ( 3UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX4 ( 4UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX5 ( 5UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX6 ( 6UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX7 ( 7UL << 1UL ) -#define portMPU_RLAR_REGION_ENABLE ( 1UL ) +#define portMPU_RLAR_REGION_ENABLE ( 1UL ) /* Enable privileged access to unmapped region. */ -#define portMPU_PRIV_BACKGROUND_ENABLE_BIT ( 1UL << 2UL ) +#define portMPU_PRIV_BACKGROUND_ENABLE_BIT ( 1UL << 2UL ) /* Enable MPU. */ -#define portMPU_ENABLE_BIT ( 1UL << 0UL ) +#define portMPU_ENABLE_BIT ( 1UL << 0UL ) /* Expected value of the portMPU_TYPE register. */ -#define portEXPECTED_MPU_TYPE_VALUE ( configTOTAL_MPU_REGIONS << 8UL ) +#define portEXPECTED_MPU_TYPE_VALUE ( configTOTAL_MPU_REGIONS << 8UL ) /* Extract first address of the MPU region as encoded in the * RBAR (Region Base Address Register) value. */ @@ -448,13 +472,13 @@ portDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIV #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) - /** - * @brief Sets up the task stack so that upon returning from - * SVC, the task stack is used again. - * - * @param pulSystemCallStack The current SP when the SVC was raised. - * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler. - */ +/** + * @brief Sets up the task stack so that upon returning from + * SVC, the task stack is used again. + * + * @param pulSystemCallStack The current SP when the SVC was raised. + * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler. + */ void vSystemCallExit( uint32_t * pulSystemCallStack, uint32_t ulLR ) PRIVILEGED_FUNCTION; @@ -462,11 +486,11 @@ portDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIV #if ( configENABLE_MPU == 1 ) - /** - * @brief Checks whether or not the calling task is privileged. - * - * @return pdTRUE if the calling task is privileged, pdFALSE otherwise. - */ +/** + * @brief Checks whether or not the calling task is privileged. + * + * @return pdTRUE if the calling task is privileged, pdFALSE otherwise. + */ BaseType_t xPortIsTaskPrivileged( void ) PRIVILEGED_FUNCTION; #endif /* configENABLE_MPU == 1 */ @@ -501,13 +525,13 @@ PRIVILEGED_DATA static volatile uint32_t ulCriticalNesting = 0xaaaaaaaaUL; * FreeRTOS API functions are not called from interrupts that have been assigned * a priority above configMAX_SYSCALL_INTERRUPT_PRIORITY. */ -#if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) ) +#if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) static uint8_t ucMaxSysCallPriority = 0; static uint32_t ulMaxPRIGROUPValue = 0; static const volatile uint8_t * const pcInterruptPriorityRegisters = ( const volatile uint8_t * ) portNVIC_IP_REGISTERS_OFFSET_16; -#endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) ) */ +#endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */ #if ( configUSE_TICKLESS_IDLE == 1 ) @@ -760,8 +784,15 @@ __attribute__( ( weak ) ) void vPortSetupTimerInterrupt( void ) /* PRIVILEGED_FU } #endif /* configUSE_TICKLESS_IDLE */ - /* Stop and reset the SysTick. */ - portNVIC_SYSTICK_CTRL_REG = 0UL; + /* Stop and reset SysTick. + * + * QEMU versions older than 7.0.0 contain a bug which causes an error if we + * enable SysTick without first selecting a valid clock source. We trigger + * the bug if we change clock sources from a clock with a zero clock period + * to one with a nonzero clock period and enable Systick at the same time. + * So we configure the CLKSOURCE bit here, prior to setting the ENABLE bit. + * This workaround avoids the bug in QEMU versions older than 7.0.0. */ + portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT_CONFIG; portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL; /* Configure SysTick to interrupt at the requested rate. */ @@ -819,6 +850,7 @@ static void prvTaskExitError( void ) static void prvSetupMPU( void ) /* PRIVILEGED_FUNCTION */ { #if defined( __ARMCC_VERSION ) + /* Declaration when these variable are defined in code instead of being * exported from linker scripts. */ extern uint32_t * __privileged_functions_start__; @@ -972,13 +1004,19 @@ void SysTick_Handler( void ) /* PRIVILEGED_FUNCTION */ uint32_t ulPreviousMask; ulPreviousMask = portSET_INTERRUPT_MASK_FROM_ISR(); + traceISR_ENTER(); { /* Increment the RTOS tick. */ if( xTaskIncrementTick() != pdFALSE ) { + traceISR_EXIT_TO_SCHEDULER(); /* Pend a context switch. */ portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; } + else + { + traceISR_EXIT(); + } } portCLEAR_INTERRUPT_MASK_FROM_ISR( ulPreviousMask ); } @@ -988,6 +1026,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO { #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) ) #if defined( __ARMCC_VERSION ) + /* Declaration when these variable are defined in code instead of being * exported from linker scripts. */ extern uint32_t * __syscalls_flash_start__; @@ -1083,18 +1122,24 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO vRestoreContextOfFirstTask(); break; - #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) ) - case portSVC_RAISE_PRIVILEGE: + #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) ) + case portSVC_RAISE_PRIVILEGE: - /* Only raise the privilege, if the svc was raised from any of - * the system calls. */ - if( ( ulPC >= ( uint32_t ) __syscalls_flash_start__ ) && - ( ulPC <= ( uint32_t ) __syscalls_flash_end__ ) ) - { - vRaisePrivilege(); - } - break; - #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) */ + /* Only raise the privilege, if the svc was raised from any of + * the system calls. */ + if( ( ulPC >= ( uint32_t ) __syscalls_flash_start__ ) && + ( ulPC <= ( uint32_t ) __syscalls_flash_end__ ) ) + { + vRaisePrivilege(); + } + break; + #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) */ + + #if ( configENABLE_MPU == 1 ) + case portSVC_YIELD: + vPortYield(); + break; + #endif /* configENABLE_MPU == 1 */ default: /* Incorrect SVC call. */ @@ -1154,12 +1199,11 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO { /* Extended frame i.e. FPU in use. */ ulStackFrameSize = 26; - __asm volatile - ( + __asm volatile ( " vpush {s0} \n" /* Trigger lazy stacking. */ " vpop {s0} \n" /* Nullify the affect of the above instruction. */ ::: "memory" - ); + ); } else { @@ -1171,7 +1215,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO { ulStackFrameSize = 8; } - #endif /* if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */ + #endif /* configENABLE_FPU || configENABLE_MVE */ /* Make space on the system call stack for the stack frame. */ pulSystemCallStack = pulSystemCallStack - ulStackFrameSize; @@ -1187,18 +1231,24 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO * point (i.e. the caller of the MPU_). We need to restore it * when we exit from the system call. */ pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry = pulTaskStack[ portOFFSET_TO_LR ]; - /* Store the value of the PSPLIM register before the SVC was raised. * We need to restore it when we exit from the system call. */ - __asm volatile ( "mrs %0, psplim" : "=r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) ); + #if ( portUSE_PSPLIM_REGISTER == 1 ) + { + __asm volatile ( "mrs %0, psplim" : "=r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) ); + } + #endif /* Use the pulSystemCallStack in thread mode. */ __asm volatile ( "msr psp, %0" : : "r" ( pulSystemCallStack ) ); - __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) ); + #if ( portUSE_PSPLIM_REGISTER == 1 ) + { + __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) ); + } + #endif /* Start executing the system call upon returning from this handler. */ pulSystemCallStack[ portOFFSET_TO_PC ] = uxSystemCallImplementations[ ucSystemCallNumber ]; - /* Raise a request to exit from the system call upon finishing the * system call. */ pulSystemCallStack[ portOFFSET_TO_LR ] = ( uint32_t ) vRequestSystemCallExit; @@ -1224,14 +1274,13 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO pulSystemCallStack[ portOFFSET_TO_PSR ] &= ( ~portPSR_STACK_PADDING_MASK ); /* Raise the privilege for the duration of the system call. */ - __asm volatile - ( + __asm volatile ( " mrs r0, control \n" /* Obtain current control value. */ " movs r1, #1 \n" /* r1 = 1. */ " bics r0, r1 \n" /* Clear nPRIV bit. */ " msr control, r0 \n" /* Write back new control value. */ ::: "r0", "r1", "memory" - ); + ); } } @@ -1293,12 +1342,11 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO { /* Extended frame i.e. FPU in use. */ ulStackFrameSize = 26; - __asm volatile - ( + __asm volatile ( " vpush {s0} \n" /* Trigger lazy stacking. */ " vpop {s0} \n" /* Nullify the affect of the above instruction. */ ::: "memory" - ); + ); } else { @@ -1310,7 +1358,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO { ulStackFrameSize = 8; } - #endif /* if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */ + #endif /* configENABLE_FPU || configENABLE_MVE */ /* Make space on the task stack for the stack frame. */ pulTaskStack = pulTaskStack - ulStackFrameSize; @@ -1332,7 +1380,11 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO /* Restore the PSPLIM register to what it was at the time of * system call entry. */ - __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) ); + #if ( portUSE_PSPLIM_REGISTER == 1 ) + { + __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) ); + } + #endif /* If the hardware used padding to force the stack pointer * to be double word aligned, set the stacked xPSR bit[9], @@ -1350,14 +1402,13 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO pxMpuSettings->xSystemCallStackInfo.pulTaskStack = NULL; /* Drop the privilege before returning to the thread mode. */ - __asm volatile - ( + __asm volatile ( " mrs r0, control \n" /* Obtain current control value. */ " movs r1, #1 \n" /* r1 = 1. */ " orrs r0, r1 \n" /* Set nPRIV bit. */ " msr control, r0 \n" /* Write back new control value. */ ::: "r0", "r1", "memory" - ); + ); } } @@ -1410,21 +1461,21 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO xMPUSettings->ulContext[ ulIndex ] = 0x11111111; /* r11. */ ulIndex++; - xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pvParameters; /* r0. */ + xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pvParameters; /* r0. */ ulIndex++; - xMPUSettings->ulContext[ ulIndex ] = 0x01010101; /* r1. */ + xMPUSettings->ulContext[ ulIndex ] = 0x01010101; /* r1. */ ulIndex++; - xMPUSettings->ulContext[ ulIndex ] = 0x02020202; /* r2. */ + xMPUSettings->ulContext[ ulIndex ] = 0x02020202; /* r2. */ ulIndex++; - xMPUSettings->ulContext[ ulIndex ] = 0x03030303; /* r3. */ + xMPUSettings->ulContext[ ulIndex ] = 0x03030303; /* r3. */ ulIndex++; - xMPUSettings->ulContext[ ulIndex ] = 0x12121212; /* r12. */ + xMPUSettings->ulContext[ ulIndex ] = 0x12121212; /* r12. */ ulIndex++; xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portTASK_RETURN_ADDRESS; /* LR. */ ulIndex++; - xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxCode; /* PC. */ + xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxCode; /* PC. */ ulIndex++; - xMPUSettings->ulContext[ ulIndex ] = portINITIAL_XPSR; /* xPSR. */ + xMPUSettings->ulContext[ ulIndex ] = portINITIAL_XPSR; /* xPSR. */ ulIndex++; #if ( configENABLE_TRUSTZONE == 1 ) @@ -1435,8 +1486,9 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO #endif /* configENABLE_TRUSTZONE */ xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) ( pxTopOfStack - 8 ); /* PSP with the hardware saved stack. */ ulIndex++; - xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxEndOfStack; /* PSPLIM. */ + xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxEndOfStack; /* PSPLIM. */ ulIndex++; + if( xRunPrivileged == pdTRUE ) { xMPUSettings->ulTaskFlags |= portTASK_IS_PRIVILEGED_FLAG; @@ -1449,6 +1501,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portINITIAL_CONTROL_UNPRIVILEGED; /* CONTROL. */ ulIndex++; } + xMPUSettings->ulContext[ ulIndex ] = portINITIAL_EXC_RETURN; /* LR (EXC_RETURN). */ ulIndex++; @@ -1483,7 +1536,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO * interrupt. */ #if ( portPRELOAD_REGISTERS == 0 ) { - pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */ + pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */ *pxTopOfStack = portINITIAL_XPSR; /* xPSR. */ pxTopOfStack--; *pxTopOfStack = ( StackType_t ) pxCode; /* PC. */ @@ -1505,7 +1558,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO } #else /* portPRELOAD_REGISTERS */ { - pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */ + pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */ *pxTopOfStack = portINITIAL_XPSR; /* xPSR. */ pxTopOfStack--; *pxTopOfStack = ( StackType_t ) pxCode; /* PC. */ @@ -1540,7 +1593,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO pxTopOfStack--; *pxTopOfStack = portINITIAL_EXC_RETURN; /* EXC_RETURN. */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */ + *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */ #if ( configENABLE_TRUSTZONE == 1 ) { @@ -1559,22 +1612,52 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */ { - #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) ) + /* An application can install FreeRTOS interrupt handlers in one of the + * folllowing ways: + * 1. Direct Routing - Install the functions SVC_Handler and PendSV_Handler + * for SVCall and PendSV interrupts respectively. + * 2. Indirect Routing - Install separate handlers for SVCall and PendSV + * interrupts and route program control from those handlers to + * SVC_Handler and PendSV_Handler functions. + * + * Applications that use Indirect Routing must set + * configCHECK_HANDLER_INSTALLATION to 0 in their FreeRTOSConfig.h. Direct + * routing, which is validated here when configCHECK_HANDLER_INSTALLATION + * is 1, should be preferred when possible. */ + #if ( configCHECK_HANDLER_INSTALLATION == 1 ) + { + const portISR_t * const pxVectorTable = portSCB_VTOR_REG; + + /* Validate that the application has correctly installed the FreeRTOS + * handlers for SVCall and PendSV interrupts. We do not check the + * installation of the SysTick handler because the application may + * choose to drive the RTOS tick using a timer other than the SysTick + * timer by overriding the weak function vPortSetupTimerInterrupt(). + * + * Assertion failures here indicate incorrect installation of the + * FreeRTOS handlers. For help installing the FreeRTOS handlers, see + * https://www.FreeRTOS.org/FAQHelp.html. + * + * Systems with a configurable address for the interrupt vector table + * can also encounter assertion failures or even system faults here if + * VTOR is not set correctly to point to the application's vector table. */ + configASSERT( pxVectorTable[ portVECTOR_INDEX_SVC ] == SVC_Handler ); + configASSERT( pxVectorTable[ portVECTOR_INDEX_PENDSV ] == PendSV_Handler ); + } + #endif /* configCHECK_HANDLER_INSTALLATION */ + + #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) { - volatile uint32_t ulOriginalPriority; volatile uint32_t ulImplementedPrioBits = 0; volatile uint8_t ucMaxPriorityValue; /* Determine the maximum priority from which ISR safe FreeRTOS API - * functions can be called. ISR safe functions are those that end in - * "FromISR". FreeRTOS maintains separate thread and ISR API functions to + * functions can be called. ISR safe functions are those that end in + * "FromISR". FreeRTOS maintains separate thread and ISR API functions to * ensure interrupt entry is as fast and simple as possible. * - * Save the interrupt priority value that is about to be clobbered. */ - ulOriginalPriority = portNVIC_SHPR2_REG; - - /* Determine the number of priority bits available. First write to all - * possible bits. */ + * First, determine the number of priority bits available. Write to all + * possible bits in the priority setting for SVCall. */ portNVIC_SHPR2_REG = 0xFF000000; /* Read the value back to see how many bits stuck. */ @@ -1593,11 +1676,10 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */ /* Check that the bits not implemented in hardware are zero in * configMAX_SYSCALL_INTERRUPT_PRIORITY. */ - configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( ~ucMaxPriorityValue ) ) == 0U ); + configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( uint8_t ) ( ~( uint32_t ) ucMaxPriorityValue ) ) == 0U ); /* Calculate the maximum acceptable priority group value for the number * of bits read back. */ - while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE ) { ulImplementedPrioBits++; @@ -1635,16 +1717,14 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */ * register. */ ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT; ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK; - - /* Restore the clobbered interrupt priority register to its original - * value. */ - portNVIC_SHPR2_REG = ulOriginalPriority; } - #endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) ) */ + #endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */ - /* Make PendSV, CallSV and SysTick the same priority as the kernel. */ + /* Make PendSV and SysTick the lowest priority interrupts, and make SVCall + * the highest priority. */ portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI; portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI; + portNVIC_SHPR2_REG = 0; #if ( configENABLE_MPU == 1 ) { @@ -1701,6 +1781,7 @@ void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */ int32_t lIndex = 0; #if defined( __ARMCC_VERSION ) + /* Declaration when these variable are defined in code instead of being * exported from linker scripts. */ extern uint32_t * __privileged_sram_start__; @@ -1886,7 +1967,7 @@ BaseType_t xPortIsInsideInterrupt( void ) } /*-----------------------------------------------------------*/ -#if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) ) +#if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) void vPortValidateInterruptPriority( void ) { @@ -1944,7 +2025,7 @@ BaseType_t xPortIsInsideInterrupt( void ) configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue ); } -#endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) ) */ +#endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */ /*-----------------------------------------------------------*/ #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) diff --git a/Source/portable/GCC/ARM_CM33_NTZ/non_secure/portasm.c b/Source/portable/GCC/ARM_CM33_NTZ/non_secure/portasm.c index b3f6a0aac..6169b9358 100644 --- a/Source/portable/GCC/ARM_CM33_NTZ/non_secure/portasm.c +++ b/Source/portable/GCC/ARM_CM33_NTZ/non_secure/portasm.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -75,16 +75,16 @@ " ldmia r0!, {r4-r11} \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */ " stmia r2, {r4-r11} \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */ " \n" - #if ( configTOTAL_MPU_REGIONS == 16 ) - " movs r3, #8 \n" /* r3 = 8. */ - " str r3, [r1] \n" /* Program RNR = 8. */ - " ldmia r0!, {r4-r11} \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */ - " stmia r2, {r4-r11} \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */ - " movs r3, #12 \n" /* r3 = 12. */ - " str r3, [r1] \n" /* Program RNR = 12. */ - " ldmia r0!, {r4-r11} \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */ - " stmia r2, {r4-r11} \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */ - #endif /* configTOTAL_MPU_REGIONS == 16 */ + #if ( configTOTAL_MPU_REGIONS == 16 ) + " movs r3, #8 \n" /* r3 = 8. */ + " str r3, [r1] \n" /* Program RNR = 8. */ + " ldmia r0!, {r4-r11} \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */ + " stmia r2, {r4-r11} \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */ + " movs r3, #12 \n" /* r3 = 12. */ + " str r3, [r1] \n" /* Program RNR = 12. */ + " ldmia r0!, {r4-r11} \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */ + " stmia r2, {r4-r11} \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */ + #endif /* configTOTAL_MPU_REGIONS == 16 */ " \n" " ldr r1, xMPUCTRLConst2 \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */ " ldr r2, [r1] \n" /* Read the value of MPU_CTRL. */ @@ -273,15 +273,15 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att " mrs r2, psp \n" /* r2 = PSP. */ " \n" " save_general_regs: \n" - #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) - " add r2, r2, #0x20 \n" /* Move r2 to location where s0 is saved. */ - " tst lr, #0x10 \n" - " ittt eq \n" - " vstmiaeq r1!, {s16-s31} \n" /* Store s16-s31. */ - " vldmiaeq r2, {s0-s16} \n" /* Copy hardware saved FP context into s0-s16. */ - " vstmiaeq r1!, {s0-s16} \n" /* Store hardware saved FP context. */ - " sub r2, r2, #0x20 \n" /* Set r2 back to the location of hardware saved context. */ - #endif /* configENABLE_FPU || configENABLE_MVE */ + #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) + " add r2, r2, #0x20 \n" /* Move r2 to location where s0 is saved. */ + " tst lr, #0x10 \n" + " ittt eq \n" + " vstmiaeq r1!, {s16-s31} \n" /* Store s16-s31. */ + " vldmiaeq r2, {s0-s16} \n" /* Copy hardware saved FP context into s0-s16. */ + " vstmiaeq r1!, {s0-s16} \n" /* Store hardware saved FP context. */ + " sub r2, r2, #0x20 \n" /* Set r2 back to the location of hardware saved context. */ + #endif /* configENABLE_FPU || configENABLE_MVE */ " \n" " stmia r1!, {r4-r11} \n" /* Store r4-r11. */ " ldmia r2, {r4-r11} \n" /* Copy the hardware saved context into r4-r11. */ @@ -326,16 +326,16 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att " ldmia r0!, {r4-r11} \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */ " stmia r2, {r4-r11} \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */ " \n" - #if ( configTOTAL_MPU_REGIONS == 16 ) - " movs r3, #8 \n" /* r3 = 8. */ - " str r3, [r1] \n" /* Program RNR = 8. */ - " ldmia r0!, {r4-r11} \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */ - " stmia r2, {r4-r11} \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */ - " movs r3, #12 \n" /* r3 = 12. */ - " str r3, [r1] \n" /* Program RNR = 12. */ - " ldmia r0!, {r4-r11} \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */ - " stmia r2, {r4-r11} \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */ - #endif /* configTOTAL_MPU_REGIONS == 16 */ + #if ( configTOTAL_MPU_REGIONS == 16 ) + " movs r3, #8 \n" /* r3 = 8. */ + " str r3, [r1] \n" /* Program RNR = 8. */ + " ldmia r0!, {r4-r11} \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */ + " stmia r2, {r4-r11} \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */ + " movs r3, #12 \n" /* r3 = 12. */ + " str r3, [r1] \n" /* Program RNR = 12. */ + " ldmia r0!, {r4-r11} \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */ + " stmia r2, {r4-r11} \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */ + #endif /* configTOTAL_MPU_REGIONS == 16 */ " \n" " ldr r1, xMPUCTRLConst \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */ " ldr r2, [r1] \n" /* Read the value of MPU_CTRL. */ @@ -358,13 +358,13 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att " ldmdb r1!, {r4-r11} \n" /* r4-r11 contain hardware saved context. */ " stmia r2!, {r4-r11} \n" /* Copy the hardware saved context on the task stack. */ " ldmdb r1!, {r4-r11} \n" /* r4-r11 restored. */ - #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) - " tst lr, #0x10 \n" - " ittt eq \n" - " vldmdbeq r1!, {s0-s16} \n" /* s0-s16 contain hardware saved FP context. */ - " vstmiaeq r2!, {s0-s16} \n" /* Copy hardware saved FP context on the task stack. */ - " vldmdbeq r1!, {s16-s31} \n" /* Restore s16-s31. */ - #endif /* configENABLE_FPU || configENABLE_MVE */ + #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) + " tst lr, #0x10 \n" + " ittt eq \n" + " vldmdbeq r1!, {s0-s16} \n" /* s0-s16 contain hardware saved FP context. */ + " vstmiaeq r2!, {s0-s16} \n" /* Copy hardware saved FP context on the task stack. */ + " vldmdbeq r1!, {s16-s31} \n" /* Restore s16-s31. */ + #endif /* configENABLE_FPU || configENABLE_MVE */ " \n" " restore_context_done: \n" " str r1, [r0] \n" /* Save the location where the context should be saved next as the first member of TCB. */ @@ -390,11 +390,11 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att " \n" " mrs r0, psp \n" /* Read PSP in r0. */ " \n" - #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) - " tst lr, #0x10 \n" /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */ - " it eq \n" - " vstmdbeq r0!, {s16-s31} \n" /* Store the additional FP context registers which are not saved automatically. */ - #endif /* configENABLE_FPU || configENABLE_MVE */ + #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) + " tst lr, #0x10 \n" /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */ + " it eq \n" + " vstmdbeq r0!, {s16-s31} \n" /* Store the additional FP context registers which are not saved automatically. */ + #endif /* configENABLE_FPU || configENABLE_MVE */ " \n" " mrs r2, psplim \n" /* r2 = PSPLIM. */ " mov r3, lr \n" /* r3 = LR/EXC_RETURN. */ @@ -418,11 +418,11 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att " \n" " ldmia r0!, {r2-r11} \n" /* Read from stack - r2 = PSPLIM, r3 = LR and r4-r11 restored. */ " \n" - #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) - " tst r3, #0x10 \n" /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */ - " it eq \n" - " vldmiaeq r0!, {s16-s31} \n" /* Restore the additional FP context registers which are not restored automatically. */ - #endif /* configENABLE_FPU || configENABLE_MVE */ + #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) + " tst r3, #0x10 \n" /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */ + " it eq \n" + " vldmiaeq r0!, {s16-s31} \n" /* Restore the additional FP context registers which are not restored automatically. */ + #endif /* configENABLE_FPU || configENABLE_MVE */ " \n" " msr psplim, r2 \n" /* Restore the PSPLIM register value for the task. */ " msr psp, r0 \n" /* Remember the new top of stack for the task. */ diff --git a/Source/portable/GCC/ARM_CM33_NTZ/non_secure/portasm.h b/Source/portable/GCC/ARM_CM33_NTZ/non_secure/portasm.h index f64ceb525..c6d2ebd58 100644 --- a/Source/portable/GCC/ARM_CM33_NTZ/non_secure/portasm.h +++ b/Source/portable/GCC/ARM_CM33_NTZ/non_secure/portasm.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/Source/portable/GCC/ARM_CM33_NTZ/non_secure/portmacro.h b/Source/portable/GCC/ARM_CM33_NTZ/non_secure/portmacro.h index cc798707e..a5416a66a 100644 --- a/Source/portable/GCC/ARM_CM33_NTZ/non_secure/portmacro.h +++ b/Source/portable/GCC/ARM_CM33_NTZ/non_secure/portmacro.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -48,9 +48,9 @@ /** * Architecture specifics. */ -#define portARCH_NAME "Cortex-M33" -#define portHAS_BASEPRI 1 -#define portDONT_DISCARD __attribute__( ( used ) ) +#define portARCH_NAME "Cortex-M33" +#define portHAS_ARMV8M_MAIN_EXTENSION 1 +#define portDONT_DISCARD __attribute__( ( used ) ) /*-----------------------------------------------------------*/ /* ARMv8-M common port configurations. */ @@ -60,8 +60,8 @@ /** * @brief Critical section management. */ -#define portDISABLE_INTERRUPTS() ulSetInterruptMask() -#define portENABLE_INTERRUPTS() vClearInterruptMask( 0 ) +#define portDISABLE_INTERRUPTS() ulSetInterruptMask() +#define portENABLE_INTERRUPTS() vClearInterruptMask( 0 ) /*-----------------------------------------------------------*/ /* *INDENT-OFF* */ diff --git a/Source/portable/GCC/ARM_CM33_NTZ/non_secure/portmacrocommon.h b/Source/portable/GCC/ARM_CM33_NTZ/non_secure/portmacrocommon.h index 6f666da22..33f21d85b 100644 --- a/Source/portable/GCC/ARM_CM33_NTZ/non_secure/portmacrocommon.h +++ b/Source/portable/GCC/ARM_CM33_NTZ/non_secure/portmacrocommon.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -117,7 +117,7 @@ extern uint32_t ulSetInterruptMask( void ) /* __attribute__(( naked )) PRIVILEGE extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */; #if ( configENABLE_TRUSTZONE == 1 ) - extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize ); /* __attribute__ (( naked )) */ + extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize ); /* __attribute__ (( naked )) */ extern void vPortFreeSecureContext( uint32_t * pulTCB ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */; #endif /* configENABLE_TRUSTZONE */ @@ -188,13 +188,13 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P #if ( configENABLE_MPU == 1 ) - /** - * @brief Settings to define an MPU region. - */ +/** + * @brief Settings to define an MPU region. + */ typedef struct MPURegionSettings { - uint32_t ulRBAR; /**< RBAR for the region. */ - uint32_t ulRLAR; /**< RLAR for the region. */ + uint32_t ulRBAR; /**< RBAR for the region. */ + uint32_t ulRLAR; /**< RLAR for the region. */ } MPURegionSettings_t; #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) @@ -203,9 +203,9 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P #error configSYSTEM_CALL_STACK_SIZE must be defined to the desired size of the system call stack in words for using MPU wrappers v2. #endif - /** - * @brief System call stack. - */ +/** + * @brief System call stack. + */ typedef struct SYSTEM_CALL_STACK_INFO { uint32_t ulSystemCallStackBuffer[ configSYSTEM_CALL_STACK_SIZE ]; @@ -218,74 +218,74 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P #endif /* configUSE_MPU_WRAPPERS_V1 == 0 */ - /** - * @brief MPU settings as stored in the TCB. - */ +/** + * @brief MPU settings as stored in the TCB. + */ #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) - #if( configENABLE_TRUSTZONE == 1 ) + #if ( configENABLE_TRUSTZONE == 1 ) - /* - * +-----------+---------------+----------+-----------------+------------------------------+-----+ - * | s16-s31 | s0-s15, FPSCR | r4-r11 | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, | | - * | | | | PC, xPSR | CONTROL, EXC_RETURN | | - * +-----------+---------------+----------+-----------------+------------------------------+-----+ - * - * <-----------><--------------><---------><----------------><-----------------------------><----> - * 16 16 8 8 5 1 - */ - #define MAX_CONTEXT_SIZE 54 +/* + * +-----------+---------------+----------+-----------------+------------------------------+-----+ + * | s16-s31 | s0-s15, FPSCR | r4-r11 | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, | | + * | | | | PC, xPSR | CONTROL, EXC_RETURN | | + * +-----------+---------------+----------+-----------------+------------------------------+-----+ + * + * <-----------><--------------><---------><----------------><-----------------------------><----> + * 16 16 8 8 5 1 + */ + #define MAX_CONTEXT_SIZE 54 #else /* #if( configENABLE_TRUSTZONE == 1 ) */ - /* - * +-----------+---------------+----------+-----------------+----------------------+-----+ - * | s16-s31 | s0-s15, FPSCR | r4-r11 | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL | | - * | | | | PC, xPSR | EXC_RETURN | | - * +-----------+---------------+----------+-----------------+----------------------+-----+ - * - * <-----------><--------------><---------><----------------><---------------------><----> - * 16 16 8 8 4 1 - */ - #define MAX_CONTEXT_SIZE 53 +/* + * +-----------+---------------+----------+-----------------+----------------------+-----+ + * | s16-s31 | s0-s15, FPSCR | r4-r11 | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL | | + * | | | | PC, xPSR | EXC_RETURN | | + * +-----------+---------------+----------+-----------------+----------------------+-----+ + * + * <-----------><--------------><---------><----------------><---------------------><----> + * 16 16 8 8 4 1 + */ + #define MAX_CONTEXT_SIZE 53 #endif /* #if( configENABLE_TRUSTZONE == 1 ) */ #else /* #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */ - #if( configENABLE_TRUSTZONE == 1 ) + #if ( configENABLE_TRUSTZONE == 1 ) - /* - * +----------+-----------------+------------------------------+-----+ - * | r4-r11 | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, | | - * | | PC, xPSR | CONTROL, EXC_RETURN | | - * +----------+-----------------+------------------------------+-----+ - * - * <---------><----------------><------------------------------><----> - * 8 8 5 1 - */ - #define MAX_CONTEXT_SIZE 22 +/* + * +----------+-----------------+------------------------------+-----+ + * | r4-r11 | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, | | + * | | PC, xPSR | CONTROL, EXC_RETURN | | + * +----------+-----------------+------------------------------+-----+ + * + * <---------><----------------><------------------------------><----> + * 8 8 5 1 + */ + #define MAX_CONTEXT_SIZE 22 #else /* #if( configENABLE_TRUSTZONE == 1 ) */ - /* - * +----------+-----------------+----------------------+-----+ - * | r4-r11 | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL | | - * | | PC, xPSR | EXC_RETURN | | - * +----------+-----------------+----------------------+-----+ - * - * <---------><----------------><----------------------><----> - * 8 8 4 1 - */ - #define MAX_CONTEXT_SIZE 21 +/* + * +----------+-----------------+----------------------+-----+ + * | r4-r11 | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL | | + * | | PC, xPSR | EXC_RETURN | | + * +----------+-----------------+----------------------+-----+ + * + * <---------><----------------><----------------------><----> + * 8 8 4 1 + */ + #define MAX_CONTEXT_SIZE 21 #endif /* #if( configENABLE_TRUSTZONE == 1 ) */ #endif /* #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */ - /* Flags used for xMPU_SETTINGS.ulTaskFlags member. */ - #define portSTACK_FRAME_HAS_PADDING_FLAG ( 1UL << 0UL ) - #define portTASK_IS_PRIVILEGED_FLAG ( 1UL << 1UL ) +/* Flags used for xMPU_SETTINGS.ulTaskFlags member. */ + #define portSTACK_FRAME_HAS_PADDING_FLAG ( 1UL << 0UL ) + #define portTASK_IS_PRIVILEGED_FLAG ( 1UL << 1UL ) /* Size of an Access Control List (ACL) entry in bits. */ #define portACL_ENTRY_SIZE_BITS ( 32U ) @@ -313,7 +313,7 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P * system calls. */ #ifdef configASSERT - #if ( portHAS_BASEPRI == 1 ) + #if ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) void vPortValidateInterruptPriority( void ); #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() vPortValidateInterruptPriority() #endif @@ -333,12 +333,29 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P /** * @brief Scheduler utilities. */ -#define portYIELD() vPortYield() +#if ( configENABLE_MPU == 1 ) + #define portYIELD() __asm volatile ( "svc %0" ::"i" ( portSVC_YIELD ) : "memory" ) + #define portYIELD_WITHIN_API() vPortYield() +#else + #define portYIELD() vPortYield() + #define portYIELD_WITHIN_API() vPortYield() +#endif + #define portNVIC_INT_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed04 ) ) #define portNVIC_PENDSVSET_BIT ( 1UL << 28UL ) -#define portEND_SWITCHING_ISR( xSwitchRequired ) \ - do { if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; } \ - while( 0 ) +#define portEND_SWITCHING_ISR( xSwitchRequired ) \ + do \ + { \ + if( xSwitchRequired ) \ + { \ + traceISR_EXIT_TO_SCHEDULER(); \ + portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; \ + } \ + else \ + { \ + traceISR_EXIT(); \ + } \ + } while( 0 ) #define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x ) /*-----------------------------------------------------------*/ @@ -424,12 +441,12 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P extern BaseType_t xPortIsTaskPrivileged( void ); - /** - * @brief Checks whether or not the calling task is privileged. - * - * @return pdTRUE if the calling task is privileged, pdFALSE otherwise. - */ - #define portIS_TASK_PRIVILEGED() xPortIsTaskPrivileged() +/** + * @brief Checks whether or not the calling task is privileged. + * + * @return pdTRUE if the calling task is privileged, pdFALSE otherwise. + */ + #define portIS_TASK_PRIVILEGED() xPortIsTaskPrivileged() #endif /* configENABLE_MPU == 1 */ /*-----------------------------------------------------------*/ @@ -440,6 +457,56 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P #define portMEMORY_BARRIER() __asm volatile ( "" ::: "memory" ) /*-----------------------------------------------------------*/ +/* Select correct value of configUSE_PORT_OPTIMISED_TASK_SELECTION + * based on whether or not Mainline extension is implemented. */ +#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION + #if ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) + #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1 + #else + #define configUSE_PORT_OPTIMISED_TASK_SELECTION 0 + #endif +#endif /* #ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION */ + +/** + * @brief Port-optimised task selection. + */ +#if ( configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 ) + +/** + * @brief Count the number of leading zeros in a 32-bit value. + */ + static portFORCE_INLINE uint32_t ulPortCountLeadingZeros( uint32_t ulBitmap ) + { + uint32_t ulReturn; + + __asm volatile ( "clz %0, %1" : "=r" ( ulReturn ) : "r" ( ulBitmap ) : "memory" ); + + return ulReturn; + } + +/* Check the configuration. */ + #if ( configMAX_PRIORITIES > 32 ) + #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 different priorities as tasks that share a priority will time slice. + #endif + + #if ( portHAS_ARMV8M_MAIN_EXTENSION == 0 ) + #error ARMv8-M baseline implementations (such as Cortex-M23) do not support port-optimised task selection. Please set configUSE_PORT_OPTIMISED_TASK_SELECTION to 0 or leave it undefined. + #endif + +/** + * @brief Store/clear the ready priorities in a bit map. + */ + #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) ) + #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) ) + +/** + * @brief Get the priority of the highest-priority task that is ready to execute. + */ + #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - ulPortCountLeadingZeros( ( uxReadyPriorities ) ) ) + +#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */ +/*-----------------------------------------------------------*/ + /* *INDENT-OFF* */ #ifdef __cplusplus } diff --git a/Source/portable/GCC/ARM_CM35P/non_secure/mpu_wrappers_v2_asm.c b/Source/portable/GCC/ARM_CM35P/non_secure/mpu_wrappers_v2_asm.c index d247c92e0..052f97850 100644 --- a/Source/portable/GCC/ARM_CM35P/non_secure/mpu_wrappers_v2_asm.c +++ b/Source/portable/GCC/ARM_CM35P/non_secure/mpu_wrappers_v2_asm.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -365,31 +365,6 @@ } /*-----------------------------------------------------------*/ - char * MPU_pcTaskGetName( TaskHandle_t xTaskToQuery ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; - - char * MPU_pcTaskGetName( TaskHandle_t xTaskToQuery ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ - { - __asm volatile - ( - " .syntax unified \n" - " .extern MPU_pcTaskGetNameImpl \n" - " \n" - " push {r0} \n" - " mrs r0, control \n" - " tst r0, #1 \n" - " bne MPU_pcTaskGetName_Unpriv \n" - " MPU_pcTaskGetName_Priv: \n" - " pop {r0} \n" - " b MPU_pcTaskGetNameImpl \n" - " MPU_pcTaskGetName_Unpriv: \n" - " pop {r0} \n" - " svc %0 \n" - " \n" - : : "i" ( SYSTEM_CALL_pcTaskGetName ) : "memory" - ); - } -/*-----------------------------------------------------------*/ - #if ( configGENERATE_RUN_TIME_STATS == 1 ) configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetRunTimeCounter( const TaskHandle_t xTask ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; @@ -1512,31 +1487,27 @@ #if ( configUSE_TIMERS == 1 ) - BaseType_t MPU_xTimerGenericCommandEntry( const xTimerGenericCommandParams_t * pxParams ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + BaseType_t MPU_xTimerGenericCommandFromTaskEntry( const xTimerGenericCommandFromTaskParams_t * pxParams ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; - BaseType_t MPU_xTimerGenericCommandEntry( const xTimerGenericCommandParams_t * pxParams ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + BaseType_t MPU_xTimerGenericCommandFromTaskEntry( const xTimerGenericCommandFromTaskParams_t * pxParams ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ { __asm volatile ( - " .syntax unified \n" - " .extern MPU_xTimerGenericCommandPrivImpl \n" - " \n" - " push {r0} \n" - " mrs r0, ipsr \n" - " cmp r0, #0 \n" - " bne MPU_xTimerGenericCommand_Priv \n" - " mrs r0, control \n" - " tst r0, #1 \n" - " beq MPU_xTimerGenericCommand_Priv \n" - " MPU_xTimerGenericCommand_Unpriv: \n" - " pop {r0} \n" - " svc %0 \n" - " MPU_xTimerGenericCommand_Priv: \n" - " pop {r0} \n" - " b MPU_xTimerGenericCommandPrivImpl \n" - " \n" - " \n" - : : "i" ( SYSTEM_CALL_xTimerGenericCommand ) : "memory" + " .syntax unified \n" + " .extern MPU_xTimerGenericCommandFromTaskImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " bne MPU_xTimerGenericCommandFromTask_Unpriv \n" + " MPU_xTimerGenericCommandFromTask_Priv: \n" + " pop {r0} \n" + " b MPU_xTimerGenericCommandFromTaskImpl \n" + " MPU_xTimerGenericCommandFromTask_Unpriv: \n" + " pop {r0} \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xTimerGenericCommandFromTask ) : "memory" ); } diff --git a/Source/portable/GCC/ARM_CM35P/non_secure/port.c b/Source/portable/GCC/ARM_CM35P/non_secure/port.c index 9712ac353..230fe5fc2 100644 --- a/Source/portable/GCC/ARM_CM35P/non_secure/port.c +++ b/Source/portable/GCC/ARM_CM35P/non_secure/port.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -68,6 +68,22 @@ #if ( ( configRUN_FREERTOS_SECURE_ONLY == 1 ) && ( configENABLE_TRUSTZONE == 1 ) ) #error TrustZone needs to be disabled in order to run FreeRTOS on the Secure Side. #endif + +/** + * Cortex-M23 does not have non-secure PSPLIM. We should use PSPLIM on Cortex-M23 + * only when FreeRTOS runs on secure side. + */ +#if ( ( portHAS_ARMV8M_MAIN_EXTENSION == 0 ) && ( configRUN_FREERTOS_SECURE_ONLY == 0 ) ) + #define portUSE_PSPLIM_REGISTER 0 +#else + #define portUSE_PSPLIM_REGISTER 1 +#endif +/*-----------------------------------------------------------*/ + +/** + * @brief Prototype of all Interrupt Service Routines (ISRs). + */ +typedef void ( * portISR_t )( void ); /*-----------------------------------------------------------*/ /** @@ -91,10 +107,18 @@ /** * @brief Constants required to manipulate the SCB. */ -#define portSCB_SYS_HANDLER_CTRL_STATE_REG ( *( volatile uint32_t * ) 0xe000ed24 ) +#define portSCB_VTOR_REG ( *( ( portISR_t ** ) 0xe000ed08 ) ) +#define portSCB_SYS_HANDLER_CTRL_STATE_REG ( *( ( volatile uint32_t * ) 0xe000ed24 ) ) #define portSCB_MEM_FAULT_ENABLE_BIT ( 1UL << 16UL ) /*-----------------------------------------------------------*/ +/** + * @brief Constants used to check the installation of the FreeRTOS interrupt handlers. + */ +#define portVECTOR_INDEX_SVC ( 11 ) +#define portVECTOR_INDEX_PENDSV ( 14 ) +/*-----------------------------------------------------------*/ + /** * @brief Constants required to check the validity of an interrupt priority. */ @@ -111,8 +135,8 @@ /** * @brief Constants used during system call enter and exit. */ -#define portPSR_STACK_PADDING_MASK ( 1UL << 9UL ) -#define portEXC_RETURN_STACK_FRAME_TYPE_MASK ( 1UL << 4UL ) +#define portPSR_STACK_PADDING_MASK ( 1UL << 9UL ) +#define portEXC_RETURN_STACK_FRAME_TYPE_MASK ( 1UL << 4UL ) /*-----------------------------------------------------------*/ /** @@ -134,81 +158,81 @@ /** * @brief Offsets in the stack to the parameters when inside the SVC handler. */ -#define portOFFSET_TO_LR ( 5 ) -#define portOFFSET_TO_PC ( 6 ) -#define portOFFSET_TO_PSR ( 7 ) +#define portOFFSET_TO_LR ( 5 ) +#define portOFFSET_TO_PC ( 6 ) +#define portOFFSET_TO_PSR ( 7 ) /*-----------------------------------------------------------*/ /** * @brief Constants required to manipulate the MPU. */ -#define portMPU_TYPE_REG ( *( ( volatile uint32_t * ) 0xe000ed90 ) ) -#define portMPU_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed94 ) ) -#define portMPU_RNR_REG ( *( ( volatile uint32_t * ) 0xe000ed98 ) ) +#define portMPU_TYPE_REG ( *( ( volatile uint32_t * ) 0xe000ed90 ) ) +#define portMPU_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed94 ) ) +#define portMPU_RNR_REG ( *( ( volatile uint32_t * ) 0xe000ed98 ) ) -#define portMPU_RBAR_REG ( *( ( volatile uint32_t * ) 0xe000ed9c ) ) -#define portMPU_RLAR_REG ( *( ( volatile uint32_t * ) 0xe000eda0 ) ) +#define portMPU_RBAR_REG ( *( ( volatile uint32_t * ) 0xe000ed9c ) ) +#define portMPU_RLAR_REG ( *( ( volatile uint32_t * ) 0xe000eda0 ) ) -#define portMPU_RBAR_A1_REG ( *( ( volatile uint32_t * ) 0xe000eda4 ) ) -#define portMPU_RLAR_A1_REG ( *( ( volatile uint32_t * ) 0xe000eda8 ) ) +#define portMPU_RBAR_A1_REG ( *( ( volatile uint32_t * ) 0xe000eda4 ) ) +#define portMPU_RLAR_A1_REG ( *( ( volatile uint32_t * ) 0xe000eda8 ) ) -#define portMPU_RBAR_A2_REG ( *( ( volatile uint32_t * ) 0xe000edac ) ) -#define portMPU_RLAR_A2_REG ( *( ( volatile uint32_t * ) 0xe000edb0 ) ) +#define portMPU_RBAR_A2_REG ( *( ( volatile uint32_t * ) 0xe000edac ) ) +#define portMPU_RLAR_A2_REG ( *( ( volatile uint32_t * ) 0xe000edb0 ) ) -#define portMPU_RBAR_A3_REG ( *( ( volatile uint32_t * ) 0xe000edb4 ) ) -#define portMPU_RLAR_A3_REG ( *( ( volatile uint32_t * ) 0xe000edb8 ) ) +#define portMPU_RBAR_A3_REG ( *( ( volatile uint32_t * ) 0xe000edb4 ) ) +#define portMPU_RLAR_A3_REG ( *( ( volatile uint32_t * ) 0xe000edb8 ) ) -#define portMPU_MAIR0_REG ( *( ( volatile uint32_t * ) 0xe000edc0 ) ) -#define portMPU_MAIR1_REG ( *( ( volatile uint32_t * ) 0xe000edc4 ) ) +#define portMPU_MAIR0_REG ( *( ( volatile uint32_t * ) 0xe000edc0 ) ) +#define portMPU_MAIR1_REG ( *( ( volatile uint32_t * ) 0xe000edc4 ) ) -#define portMPU_RBAR_ADDRESS_MASK ( 0xffffffe0 ) /* Must be 32-byte aligned. */ -#define portMPU_RLAR_ADDRESS_MASK ( 0xffffffe0 ) /* Must be 32-byte aligned. */ +#define portMPU_RBAR_ADDRESS_MASK ( 0xffffffe0 ) /* Must be 32-byte aligned. */ +#define portMPU_RLAR_ADDRESS_MASK ( 0xffffffe0 ) /* Must be 32-byte aligned. */ -#define portMPU_RBAR_ACCESS_PERMISSIONS_MASK ( 3UL << 1UL ) +#define portMPU_RBAR_ACCESS_PERMISSIONS_MASK ( 3UL << 1UL ) -#define portMPU_MAIR_ATTR0_POS ( 0UL ) -#define portMPU_MAIR_ATTR0_MASK ( 0x000000ff ) +#define portMPU_MAIR_ATTR0_POS ( 0UL ) +#define portMPU_MAIR_ATTR0_MASK ( 0x000000ff ) -#define portMPU_MAIR_ATTR1_POS ( 8UL ) -#define portMPU_MAIR_ATTR1_MASK ( 0x0000ff00 ) +#define portMPU_MAIR_ATTR1_POS ( 8UL ) +#define portMPU_MAIR_ATTR1_MASK ( 0x0000ff00 ) -#define portMPU_MAIR_ATTR2_POS ( 16UL ) -#define portMPU_MAIR_ATTR2_MASK ( 0x00ff0000 ) +#define portMPU_MAIR_ATTR2_POS ( 16UL ) +#define portMPU_MAIR_ATTR2_MASK ( 0x00ff0000 ) -#define portMPU_MAIR_ATTR3_POS ( 24UL ) -#define portMPU_MAIR_ATTR3_MASK ( 0xff000000 ) +#define portMPU_MAIR_ATTR3_POS ( 24UL ) +#define portMPU_MAIR_ATTR3_MASK ( 0xff000000 ) -#define portMPU_MAIR_ATTR4_POS ( 0UL ) -#define portMPU_MAIR_ATTR4_MASK ( 0x000000ff ) +#define portMPU_MAIR_ATTR4_POS ( 0UL ) +#define portMPU_MAIR_ATTR4_MASK ( 0x000000ff ) -#define portMPU_MAIR_ATTR5_POS ( 8UL ) -#define portMPU_MAIR_ATTR5_MASK ( 0x0000ff00 ) +#define portMPU_MAIR_ATTR5_POS ( 8UL ) +#define portMPU_MAIR_ATTR5_MASK ( 0x0000ff00 ) -#define portMPU_MAIR_ATTR6_POS ( 16UL ) -#define portMPU_MAIR_ATTR6_MASK ( 0x00ff0000 ) +#define portMPU_MAIR_ATTR6_POS ( 16UL ) +#define portMPU_MAIR_ATTR6_MASK ( 0x00ff0000 ) -#define portMPU_MAIR_ATTR7_POS ( 24UL ) -#define portMPU_MAIR_ATTR7_MASK ( 0xff000000 ) +#define portMPU_MAIR_ATTR7_POS ( 24UL ) +#define portMPU_MAIR_ATTR7_MASK ( 0xff000000 ) -#define portMPU_RLAR_ATTR_INDEX0 ( 0UL << 1UL ) -#define portMPU_RLAR_ATTR_INDEX1 ( 1UL << 1UL ) -#define portMPU_RLAR_ATTR_INDEX2 ( 2UL << 1UL ) -#define portMPU_RLAR_ATTR_INDEX3 ( 3UL << 1UL ) -#define portMPU_RLAR_ATTR_INDEX4 ( 4UL << 1UL ) -#define portMPU_RLAR_ATTR_INDEX5 ( 5UL << 1UL ) -#define portMPU_RLAR_ATTR_INDEX6 ( 6UL << 1UL ) -#define portMPU_RLAR_ATTR_INDEX7 ( 7UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX0 ( 0UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX1 ( 1UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX2 ( 2UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX3 ( 3UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX4 ( 4UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX5 ( 5UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX6 ( 6UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX7 ( 7UL << 1UL ) -#define portMPU_RLAR_REGION_ENABLE ( 1UL ) +#define portMPU_RLAR_REGION_ENABLE ( 1UL ) /* Enable privileged access to unmapped region. */ -#define portMPU_PRIV_BACKGROUND_ENABLE_BIT ( 1UL << 2UL ) +#define portMPU_PRIV_BACKGROUND_ENABLE_BIT ( 1UL << 2UL ) /* Enable MPU. */ -#define portMPU_ENABLE_BIT ( 1UL << 0UL ) +#define portMPU_ENABLE_BIT ( 1UL << 0UL ) /* Expected value of the portMPU_TYPE register. */ -#define portEXPECTED_MPU_TYPE_VALUE ( configTOTAL_MPU_REGIONS << 8UL ) +#define portEXPECTED_MPU_TYPE_VALUE ( configTOTAL_MPU_REGIONS << 8UL ) /* Extract first address of the MPU region as encoded in the * RBAR (Region Base Address Register) value. */ @@ -448,13 +472,13 @@ portDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIV #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) - /** - * @brief Sets up the task stack so that upon returning from - * SVC, the task stack is used again. - * - * @param pulSystemCallStack The current SP when the SVC was raised. - * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler. - */ +/** + * @brief Sets up the task stack so that upon returning from + * SVC, the task stack is used again. + * + * @param pulSystemCallStack The current SP when the SVC was raised. + * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler. + */ void vSystemCallExit( uint32_t * pulSystemCallStack, uint32_t ulLR ) PRIVILEGED_FUNCTION; @@ -462,11 +486,11 @@ portDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIV #if ( configENABLE_MPU == 1 ) - /** - * @brief Checks whether or not the calling task is privileged. - * - * @return pdTRUE if the calling task is privileged, pdFALSE otherwise. - */ +/** + * @brief Checks whether or not the calling task is privileged. + * + * @return pdTRUE if the calling task is privileged, pdFALSE otherwise. + */ BaseType_t xPortIsTaskPrivileged( void ) PRIVILEGED_FUNCTION; #endif /* configENABLE_MPU == 1 */ @@ -501,13 +525,13 @@ PRIVILEGED_DATA static volatile uint32_t ulCriticalNesting = 0xaaaaaaaaUL; * FreeRTOS API functions are not called from interrupts that have been assigned * a priority above configMAX_SYSCALL_INTERRUPT_PRIORITY. */ -#if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) ) +#if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) static uint8_t ucMaxSysCallPriority = 0; static uint32_t ulMaxPRIGROUPValue = 0; static const volatile uint8_t * const pcInterruptPriorityRegisters = ( const volatile uint8_t * ) portNVIC_IP_REGISTERS_OFFSET_16; -#endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) ) */ +#endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */ #if ( configUSE_TICKLESS_IDLE == 1 ) @@ -760,8 +784,15 @@ __attribute__( ( weak ) ) void vPortSetupTimerInterrupt( void ) /* PRIVILEGED_FU } #endif /* configUSE_TICKLESS_IDLE */ - /* Stop and reset the SysTick. */ - portNVIC_SYSTICK_CTRL_REG = 0UL; + /* Stop and reset SysTick. + * + * QEMU versions older than 7.0.0 contain a bug which causes an error if we + * enable SysTick without first selecting a valid clock source. We trigger + * the bug if we change clock sources from a clock with a zero clock period + * to one with a nonzero clock period and enable Systick at the same time. + * So we configure the CLKSOURCE bit here, prior to setting the ENABLE bit. + * This workaround avoids the bug in QEMU versions older than 7.0.0. */ + portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT_CONFIG; portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL; /* Configure SysTick to interrupt at the requested rate. */ @@ -819,6 +850,7 @@ static void prvTaskExitError( void ) static void prvSetupMPU( void ) /* PRIVILEGED_FUNCTION */ { #if defined( __ARMCC_VERSION ) + /* Declaration when these variable are defined in code instead of being * exported from linker scripts. */ extern uint32_t * __privileged_functions_start__; @@ -972,13 +1004,19 @@ void SysTick_Handler( void ) /* PRIVILEGED_FUNCTION */ uint32_t ulPreviousMask; ulPreviousMask = portSET_INTERRUPT_MASK_FROM_ISR(); + traceISR_ENTER(); { /* Increment the RTOS tick. */ if( xTaskIncrementTick() != pdFALSE ) { + traceISR_EXIT_TO_SCHEDULER(); /* Pend a context switch. */ portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; } + else + { + traceISR_EXIT(); + } } portCLEAR_INTERRUPT_MASK_FROM_ISR( ulPreviousMask ); } @@ -988,6 +1026,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO { #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) ) #if defined( __ARMCC_VERSION ) + /* Declaration when these variable are defined in code instead of being * exported from linker scripts. */ extern uint32_t * __syscalls_flash_start__; @@ -1083,18 +1122,24 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO vRestoreContextOfFirstTask(); break; - #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) ) - case portSVC_RAISE_PRIVILEGE: + #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) ) + case portSVC_RAISE_PRIVILEGE: - /* Only raise the privilege, if the svc was raised from any of - * the system calls. */ - if( ( ulPC >= ( uint32_t ) __syscalls_flash_start__ ) && - ( ulPC <= ( uint32_t ) __syscalls_flash_end__ ) ) - { - vRaisePrivilege(); - } - break; - #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) */ + /* Only raise the privilege, if the svc was raised from any of + * the system calls. */ + if( ( ulPC >= ( uint32_t ) __syscalls_flash_start__ ) && + ( ulPC <= ( uint32_t ) __syscalls_flash_end__ ) ) + { + vRaisePrivilege(); + } + break; + #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) */ + + #if ( configENABLE_MPU == 1 ) + case portSVC_YIELD: + vPortYield(); + break; + #endif /* configENABLE_MPU == 1 */ default: /* Incorrect SVC call. */ @@ -1154,12 +1199,11 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO { /* Extended frame i.e. FPU in use. */ ulStackFrameSize = 26; - __asm volatile - ( + __asm volatile ( " vpush {s0} \n" /* Trigger lazy stacking. */ " vpop {s0} \n" /* Nullify the affect of the above instruction. */ ::: "memory" - ); + ); } else { @@ -1171,7 +1215,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO { ulStackFrameSize = 8; } - #endif /* if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */ + #endif /* configENABLE_FPU || configENABLE_MVE */ /* Make space on the system call stack for the stack frame. */ pulSystemCallStack = pulSystemCallStack - ulStackFrameSize; @@ -1187,18 +1231,24 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO * point (i.e. the caller of the MPU_). We need to restore it * when we exit from the system call. */ pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry = pulTaskStack[ portOFFSET_TO_LR ]; - /* Store the value of the PSPLIM register before the SVC was raised. * We need to restore it when we exit from the system call. */ - __asm volatile ( "mrs %0, psplim" : "=r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) ); + #if ( portUSE_PSPLIM_REGISTER == 1 ) + { + __asm volatile ( "mrs %0, psplim" : "=r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) ); + } + #endif /* Use the pulSystemCallStack in thread mode. */ __asm volatile ( "msr psp, %0" : : "r" ( pulSystemCallStack ) ); - __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) ); + #if ( portUSE_PSPLIM_REGISTER == 1 ) + { + __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) ); + } + #endif /* Start executing the system call upon returning from this handler. */ pulSystemCallStack[ portOFFSET_TO_PC ] = uxSystemCallImplementations[ ucSystemCallNumber ]; - /* Raise a request to exit from the system call upon finishing the * system call. */ pulSystemCallStack[ portOFFSET_TO_LR ] = ( uint32_t ) vRequestSystemCallExit; @@ -1224,14 +1274,13 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO pulSystemCallStack[ portOFFSET_TO_PSR ] &= ( ~portPSR_STACK_PADDING_MASK ); /* Raise the privilege for the duration of the system call. */ - __asm volatile - ( + __asm volatile ( " mrs r0, control \n" /* Obtain current control value. */ " movs r1, #1 \n" /* r1 = 1. */ " bics r0, r1 \n" /* Clear nPRIV bit. */ " msr control, r0 \n" /* Write back new control value. */ ::: "r0", "r1", "memory" - ); + ); } } @@ -1293,12 +1342,11 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO { /* Extended frame i.e. FPU in use. */ ulStackFrameSize = 26; - __asm volatile - ( + __asm volatile ( " vpush {s0} \n" /* Trigger lazy stacking. */ " vpop {s0} \n" /* Nullify the affect of the above instruction. */ ::: "memory" - ); + ); } else { @@ -1310,7 +1358,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO { ulStackFrameSize = 8; } - #endif /* if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */ + #endif /* configENABLE_FPU || configENABLE_MVE */ /* Make space on the task stack for the stack frame. */ pulTaskStack = pulTaskStack - ulStackFrameSize; @@ -1332,7 +1380,11 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO /* Restore the PSPLIM register to what it was at the time of * system call entry. */ - __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) ); + #if ( portUSE_PSPLIM_REGISTER == 1 ) + { + __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) ); + } + #endif /* If the hardware used padding to force the stack pointer * to be double word aligned, set the stacked xPSR bit[9], @@ -1350,14 +1402,13 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO pxMpuSettings->xSystemCallStackInfo.pulTaskStack = NULL; /* Drop the privilege before returning to the thread mode. */ - __asm volatile - ( + __asm volatile ( " mrs r0, control \n" /* Obtain current control value. */ " movs r1, #1 \n" /* r1 = 1. */ " orrs r0, r1 \n" /* Set nPRIV bit. */ " msr control, r0 \n" /* Write back new control value. */ ::: "r0", "r1", "memory" - ); + ); } } @@ -1410,21 +1461,21 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO xMPUSettings->ulContext[ ulIndex ] = 0x11111111; /* r11. */ ulIndex++; - xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pvParameters; /* r0. */ + xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pvParameters; /* r0. */ ulIndex++; - xMPUSettings->ulContext[ ulIndex ] = 0x01010101; /* r1. */ + xMPUSettings->ulContext[ ulIndex ] = 0x01010101; /* r1. */ ulIndex++; - xMPUSettings->ulContext[ ulIndex ] = 0x02020202; /* r2. */ + xMPUSettings->ulContext[ ulIndex ] = 0x02020202; /* r2. */ ulIndex++; - xMPUSettings->ulContext[ ulIndex ] = 0x03030303; /* r3. */ + xMPUSettings->ulContext[ ulIndex ] = 0x03030303; /* r3. */ ulIndex++; - xMPUSettings->ulContext[ ulIndex ] = 0x12121212; /* r12. */ + xMPUSettings->ulContext[ ulIndex ] = 0x12121212; /* r12. */ ulIndex++; xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portTASK_RETURN_ADDRESS; /* LR. */ ulIndex++; - xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxCode; /* PC. */ + xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxCode; /* PC. */ ulIndex++; - xMPUSettings->ulContext[ ulIndex ] = portINITIAL_XPSR; /* xPSR. */ + xMPUSettings->ulContext[ ulIndex ] = portINITIAL_XPSR; /* xPSR. */ ulIndex++; #if ( configENABLE_TRUSTZONE == 1 ) @@ -1435,8 +1486,9 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO #endif /* configENABLE_TRUSTZONE */ xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) ( pxTopOfStack - 8 ); /* PSP with the hardware saved stack. */ ulIndex++; - xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxEndOfStack; /* PSPLIM. */ + xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxEndOfStack; /* PSPLIM. */ ulIndex++; + if( xRunPrivileged == pdTRUE ) { xMPUSettings->ulTaskFlags |= portTASK_IS_PRIVILEGED_FLAG; @@ -1449,6 +1501,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portINITIAL_CONTROL_UNPRIVILEGED; /* CONTROL. */ ulIndex++; } + xMPUSettings->ulContext[ ulIndex ] = portINITIAL_EXC_RETURN; /* LR (EXC_RETURN). */ ulIndex++; @@ -1483,7 +1536,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO * interrupt. */ #if ( portPRELOAD_REGISTERS == 0 ) { - pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */ + pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */ *pxTopOfStack = portINITIAL_XPSR; /* xPSR. */ pxTopOfStack--; *pxTopOfStack = ( StackType_t ) pxCode; /* PC. */ @@ -1505,7 +1558,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO } #else /* portPRELOAD_REGISTERS */ { - pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */ + pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */ *pxTopOfStack = portINITIAL_XPSR; /* xPSR. */ pxTopOfStack--; *pxTopOfStack = ( StackType_t ) pxCode; /* PC. */ @@ -1540,7 +1593,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO pxTopOfStack--; *pxTopOfStack = portINITIAL_EXC_RETURN; /* EXC_RETURN. */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */ + *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */ #if ( configENABLE_TRUSTZONE == 1 ) { @@ -1559,22 +1612,52 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */ { - #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) ) + /* An application can install FreeRTOS interrupt handlers in one of the + * folllowing ways: + * 1. Direct Routing - Install the functions SVC_Handler and PendSV_Handler + * for SVCall and PendSV interrupts respectively. + * 2. Indirect Routing - Install separate handlers for SVCall and PendSV + * interrupts and route program control from those handlers to + * SVC_Handler and PendSV_Handler functions. + * + * Applications that use Indirect Routing must set + * configCHECK_HANDLER_INSTALLATION to 0 in their FreeRTOSConfig.h. Direct + * routing, which is validated here when configCHECK_HANDLER_INSTALLATION + * is 1, should be preferred when possible. */ + #if ( configCHECK_HANDLER_INSTALLATION == 1 ) + { + const portISR_t * const pxVectorTable = portSCB_VTOR_REG; + + /* Validate that the application has correctly installed the FreeRTOS + * handlers for SVCall and PendSV interrupts. We do not check the + * installation of the SysTick handler because the application may + * choose to drive the RTOS tick using a timer other than the SysTick + * timer by overriding the weak function vPortSetupTimerInterrupt(). + * + * Assertion failures here indicate incorrect installation of the + * FreeRTOS handlers. For help installing the FreeRTOS handlers, see + * https://www.FreeRTOS.org/FAQHelp.html. + * + * Systems with a configurable address for the interrupt vector table + * can also encounter assertion failures or even system faults here if + * VTOR is not set correctly to point to the application's vector table. */ + configASSERT( pxVectorTable[ portVECTOR_INDEX_SVC ] == SVC_Handler ); + configASSERT( pxVectorTable[ portVECTOR_INDEX_PENDSV ] == PendSV_Handler ); + } + #endif /* configCHECK_HANDLER_INSTALLATION */ + + #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) { - volatile uint32_t ulOriginalPriority; volatile uint32_t ulImplementedPrioBits = 0; volatile uint8_t ucMaxPriorityValue; /* Determine the maximum priority from which ISR safe FreeRTOS API - * functions can be called. ISR safe functions are those that end in - * "FromISR". FreeRTOS maintains separate thread and ISR API functions to + * functions can be called. ISR safe functions are those that end in + * "FromISR". FreeRTOS maintains separate thread and ISR API functions to * ensure interrupt entry is as fast and simple as possible. * - * Save the interrupt priority value that is about to be clobbered. */ - ulOriginalPriority = portNVIC_SHPR2_REG; - - /* Determine the number of priority bits available. First write to all - * possible bits. */ + * First, determine the number of priority bits available. Write to all + * possible bits in the priority setting for SVCall. */ portNVIC_SHPR2_REG = 0xFF000000; /* Read the value back to see how many bits stuck. */ @@ -1593,11 +1676,10 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */ /* Check that the bits not implemented in hardware are zero in * configMAX_SYSCALL_INTERRUPT_PRIORITY. */ - configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( ~ucMaxPriorityValue ) ) == 0U ); + configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( uint8_t ) ( ~( uint32_t ) ucMaxPriorityValue ) ) == 0U ); /* Calculate the maximum acceptable priority group value for the number * of bits read back. */ - while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE ) { ulImplementedPrioBits++; @@ -1635,16 +1717,14 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */ * register. */ ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT; ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK; - - /* Restore the clobbered interrupt priority register to its original - * value. */ - portNVIC_SHPR2_REG = ulOriginalPriority; } - #endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) ) */ + #endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */ - /* Make PendSV, CallSV and SysTick the same priority as the kernel. */ + /* Make PendSV and SysTick the lowest priority interrupts, and make SVCall + * the highest priority. */ portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI; portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI; + portNVIC_SHPR2_REG = 0; #if ( configENABLE_MPU == 1 ) { @@ -1701,6 +1781,7 @@ void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */ int32_t lIndex = 0; #if defined( __ARMCC_VERSION ) + /* Declaration when these variable are defined in code instead of being * exported from linker scripts. */ extern uint32_t * __privileged_sram_start__; @@ -1886,7 +1967,7 @@ BaseType_t xPortIsInsideInterrupt( void ) } /*-----------------------------------------------------------*/ -#if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) ) +#if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) void vPortValidateInterruptPriority( void ) { @@ -1944,7 +2025,7 @@ BaseType_t xPortIsInsideInterrupt( void ) configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue ); } -#endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) ) */ +#endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */ /*-----------------------------------------------------------*/ #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) diff --git a/Source/portable/GCC/ARM_CM35P/non_secure/portasm.c b/Source/portable/GCC/ARM_CM35P/non_secure/portasm.c index 7431c98f1..451e0abb7 100644 --- a/Source/portable/GCC/ARM_CM35P/non_secure/portasm.c +++ b/Source/portable/GCC/ARM_CM35P/non_secure/portasm.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -75,16 +75,16 @@ " ldmia r0!, {r4-r11} \n" /* Read 4 set of RBAR/RLAR registers from TCB. */ " stmia r2, {r4-r11} \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */ " \n" - #if ( configTOTAL_MPU_REGIONS == 16 ) - " movs r3, #8 \n" /* r3 = 8. */ - " str r3, [r1] \n" /* Program RNR = 8. */ - " ldmia r0!, {r4-r11} \n" /* Read 4 set of RBAR/RLAR registers from TCB. */ - " stmia r2, {r4-r11} \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */ - " movs r3, #12 \n" /* r3 = 12. */ - " str r3, [r1] \n" /* Program RNR = 12. */ - " ldmia r0!, {r4-r11} \n" /* Read 4 set of RBAR/RLAR registers from TCB. */ - " stmia r2, {r4-r11} \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */ - #endif /* configTOTAL_MPU_REGIONS == 16 */ + #if ( configTOTAL_MPU_REGIONS == 16 ) + " movs r3, #8 \n" /* r3 = 8. */ + " str r3, [r1] \n" /* Program RNR = 8. */ + " ldmia r0!, {r4-r11} \n" /* Read 4 set of RBAR/RLAR registers from TCB. */ + " stmia r2, {r4-r11} \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */ + " movs r3, #12 \n" /* r3 = 12. */ + " str r3, [r1] \n" /* Program RNR = 12. */ + " ldmia r0!, {r4-r11} \n" /* Read 4 set of RBAR/RLAR registers from TCB. */ + " stmia r2, {r4-r11} \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */ + #endif /* configTOTAL_MPU_REGIONS == 16 */ " \n" " ldr r1, xMPUCTRLConst2 \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */ " ldr r2, [r1] \n" /* Read the value of MPU_CTRL. */ @@ -294,15 +294,15 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att " save_general_regs: \n" " mrs r3, psp \n" " \n" - #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) - " add r3, r3, #0x20 \n" /* Move r3 to location where s0 is saved. */ - " tst lr, #0x10 \n" - " ittt eq \n" - " vstmiaeq r2!, {s16-s31} \n" /* Store s16-s31. */ - " vldmiaeq r3, {s0-s16} \n" /* Copy hardware saved FP context into s0-s16. */ - " vstmiaeq r2!, {s0-s16} \n" /* Store hardware saved FP context. */ - " sub r3, r3, #0x20 \n" /* Set r3 back to the location of hardware saved context. */ - #endif /* configENABLE_FPU || configENABLE_MVE */ + #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) + " add r3, r3, #0x20 \n" /* Move r3 to location where s0 is saved. */ + " tst lr, #0x10 \n" + " ittt eq \n" + " vstmiaeq r2!, {s16-s31} \n" /* Store s16-s31. */ + " vldmiaeq r3, {s0-s16} \n" /* Copy hardware saved FP context into s0-s16. */ + " vstmiaeq r2!, {s0-s16} \n" /* Store hardware saved FP context. */ + " sub r3, r3, #0x20 \n" /* Set r3 back to the location of hardware saved context. */ + #endif /* configENABLE_FPU || configENABLE_MVE */ " \n" " stmia r2!, {r4-r11} \n" /* Store r4-r11. */ " ldmia r3, {r4-r11} \n" /* Copy the hardware saved context into r4-r11. */ @@ -348,16 +348,16 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att " ldmia r0!, {r4-r11} \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */ " stmia r2, {r4-r11} \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */ " \n" - #if ( configTOTAL_MPU_REGIONS == 16 ) - " movs r3, #8 \n" /* r3 = 8. */ - " str r3, [r1] \n" /* Program RNR = 8. */ - " ldmia r0!, {r4-r11} \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */ - " stmia r2, {r4-r11} \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */ - " movs r3, #12 \n" /* r3 = 12. */ - " str r3, [r1] \n" /* Program RNR = 12. */ - " ldmia r0!, {r4-r11} \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */ - " stmia r2, {r4-r11} \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */ - #endif /* configTOTAL_MPU_REGIONS == 16 */ + #if ( configTOTAL_MPU_REGIONS == 16 ) + " movs r3, #8 \n" /* r3 = 8. */ + " str r3, [r1] \n" /* Program RNR = 8. */ + " ldmia r0!, {r4-r11} \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */ + " stmia r2, {r4-r11} \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */ + " movs r3, #12 \n" /* r3 = 12. */ + " str r3, [r1] \n" /* Program RNR = 12. */ + " ldmia r0!, {r4-r11} \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */ + " stmia r2, {r4-r11} \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */ + #endif /* configTOTAL_MPU_REGIONS == 16 */ " \n" " ldr r1, xMPUCTRLConst \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */ " ldr r2, [r1] \n" /* Read the value of MPU_CTRL. */ @@ -393,13 +393,13 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att " ldmdb r2!, {r4-r11} \n" /* r4-r11 contain hardware saved context. */ " stmia r3!, {r4-r11} \n" /* Copy the hardware saved context on the task stack. */ " ldmdb r2!, {r4-r11} \n" /* r4-r11 restored. */ - #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) - " tst lr, #0x10 \n" - " ittt eq \n" - " vldmdbeq r2!, {s0-s16} \n" /* s0-s16 contain hardware saved FP context. */ - " vstmiaeq r3!, {s0-s16} \n" /* Copy hardware saved FP context on the task stack. */ - " vldmdbeq r2!, {s16-s31} \n" /* Restore s16-s31. */ - #endif /* configENABLE_FPU || configENABLE_MVE */ + #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) + " tst lr, #0x10 \n" + " ittt eq \n" + " vldmdbeq r2!, {s0-s16} \n" /* s0-s16 contain hardware saved FP context. */ + " vstmiaeq r3!, {s0-s16} \n" /* Copy hardware saved FP context on the task stack. */ + " vldmdbeq r2!, {s16-s31} \n" /* Restore s16-s31. */ + #endif /* configENABLE_FPU || configENABLE_MVE */ " \n" " restore_context_done: \n" " str r2, [r1] \n" /* Save the location where the context should be saved next as the first member of TCB. */ @@ -452,11 +452,11 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att " save_ns_context: \n" " ldr r3, pxCurrentTCBConst \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ " ldr r1, [r3] \n" /* Read pxCurrentTCB. */ - #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) - " tst lr, #0x10 \n" /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */ - " it eq \n" - " vstmdbeq r2!, {s16-s31} \n" /* Store the additional FP context registers which are not saved automatically. */ - #endif /* configENABLE_FPU || configENABLE_MVE */ + #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) + " tst lr, #0x10 \n" /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */ + " it eq \n" + " vstmdbeq r2!, {s16-s31} \n" /* Store the additional FP context registers which are not saved automatically. */ + #endif /* configENABLE_FPU || configENABLE_MVE */ " subs r2, r2, #44 \n" /* Make space for xSecureContext, PSPLIM, LR and the remaining registers on the stack. */ " str r2, [r1] \n" /* Save the new top of stack in TCB. */ " adds r2, r2, #12 \n" /* r2 = r2 + 12. */ @@ -498,11 +498,11 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att " \n" " restore_ns_context: \n" " ldmia r2!, {r4-r11} \n" /* Restore the registers that are not automatically restored. */ - #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) - " tst lr, #0x10 \n" /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */ - " it eq \n" - " vldmiaeq r2!, {s16-s31} \n" /* Restore the additional FP context registers which are not restored automatically. */ - #endif /* configENABLE_FPU || configENABLE_MVE */ + #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) + " tst lr, #0x10 \n" /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */ + " it eq \n" + " vldmiaeq r2!, {s16-s31} \n" /* Restore the additional FP context registers which are not restored automatically. */ + #endif /* configENABLE_FPU || configENABLE_MVE */ " msr psp, r2 \n" /* Remember the new top of stack for the task. */ " bx lr \n" " \n" diff --git a/Source/portable/GCC/ARM_CM35P/non_secure/portasm.h b/Source/portable/GCC/ARM_CM35P/non_secure/portasm.h index f64ceb525..c6d2ebd58 100644 --- a/Source/portable/GCC/ARM_CM35P/non_secure/portasm.h +++ b/Source/portable/GCC/ARM_CM35P/non_secure/portasm.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/Source/portable/GCC/ARM_CM35P/non_secure/portmacro.h b/Source/portable/GCC/ARM_CM35P/non_secure/portmacro.h index 557b542eb..ea29ac207 100644 --- a/Source/portable/GCC/ARM_CM35P/non_secure/portmacro.h +++ b/Source/portable/GCC/ARM_CM35P/non_secure/portmacro.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -48,9 +48,9 @@ /** * Architecture specifics. */ -#define portARCH_NAME "Cortex-M35P" -#define portHAS_BASEPRI 1 -#define portDONT_DISCARD __attribute__( ( used ) ) +#define portARCH_NAME "Cortex-M35P" +#define portHAS_ARMV8M_MAIN_EXTENSION 1 +#define portDONT_DISCARD __attribute__( ( used ) ) /*-----------------------------------------------------------*/ /* ARMv8-M common port configurations. */ @@ -60,8 +60,8 @@ /** * @brief Critical section management. */ -#define portDISABLE_INTERRUPTS() ulSetInterruptMask() -#define portENABLE_INTERRUPTS() vClearInterruptMask( 0 ) +#define portDISABLE_INTERRUPTS() ulSetInterruptMask() +#define portENABLE_INTERRUPTS() vClearInterruptMask( 0 ) /*-----------------------------------------------------------*/ /* *INDENT-OFF* */ diff --git a/Source/portable/GCC/ARM_CM35P/non_secure/portmacrocommon.h b/Source/portable/GCC/ARM_CM35P/non_secure/portmacrocommon.h index 6f666da22..33f21d85b 100644 --- a/Source/portable/GCC/ARM_CM35P/non_secure/portmacrocommon.h +++ b/Source/portable/GCC/ARM_CM35P/non_secure/portmacrocommon.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -117,7 +117,7 @@ extern uint32_t ulSetInterruptMask( void ) /* __attribute__(( naked )) PRIVILEGE extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */; #if ( configENABLE_TRUSTZONE == 1 ) - extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize ); /* __attribute__ (( naked )) */ + extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize ); /* __attribute__ (( naked )) */ extern void vPortFreeSecureContext( uint32_t * pulTCB ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */; #endif /* configENABLE_TRUSTZONE */ @@ -188,13 +188,13 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P #if ( configENABLE_MPU == 1 ) - /** - * @brief Settings to define an MPU region. - */ +/** + * @brief Settings to define an MPU region. + */ typedef struct MPURegionSettings { - uint32_t ulRBAR; /**< RBAR for the region. */ - uint32_t ulRLAR; /**< RLAR for the region. */ + uint32_t ulRBAR; /**< RBAR for the region. */ + uint32_t ulRLAR; /**< RLAR for the region. */ } MPURegionSettings_t; #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) @@ -203,9 +203,9 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P #error configSYSTEM_CALL_STACK_SIZE must be defined to the desired size of the system call stack in words for using MPU wrappers v2. #endif - /** - * @brief System call stack. - */ +/** + * @brief System call stack. + */ typedef struct SYSTEM_CALL_STACK_INFO { uint32_t ulSystemCallStackBuffer[ configSYSTEM_CALL_STACK_SIZE ]; @@ -218,74 +218,74 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P #endif /* configUSE_MPU_WRAPPERS_V1 == 0 */ - /** - * @brief MPU settings as stored in the TCB. - */ +/** + * @brief MPU settings as stored in the TCB. + */ #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) - #if( configENABLE_TRUSTZONE == 1 ) + #if ( configENABLE_TRUSTZONE == 1 ) - /* - * +-----------+---------------+----------+-----------------+------------------------------+-----+ - * | s16-s31 | s0-s15, FPSCR | r4-r11 | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, | | - * | | | | PC, xPSR | CONTROL, EXC_RETURN | | - * +-----------+---------------+----------+-----------------+------------------------------+-----+ - * - * <-----------><--------------><---------><----------------><-----------------------------><----> - * 16 16 8 8 5 1 - */ - #define MAX_CONTEXT_SIZE 54 +/* + * +-----------+---------------+----------+-----------------+------------------------------+-----+ + * | s16-s31 | s0-s15, FPSCR | r4-r11 | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, | | + * | | | | PC, xPSR | CONTROL, EXC_RETURN | | + * +-----------+---------------+----------+-----------------+------------------------------+-----+ + * + * <-----------><--------------><---------><----------------><-----------------------------><----> + * 16 16 8 8 5 1 + */ + #define MAX_CONTEXT_SIZE 54 #else /* #if( configENABLE_TRUSTZONE == 1 ) */ - /* - * +-----------+---------------+----------+-----------------+----------------------+-----+ - * | s16-s31 | s0-s15, FPSCR | r4-r11 | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL | | - * | | | | PC, xPSR | EXC_RETURN | | - * +-----------+---------------+----------+-----------------+----------------------+-----+ - * - * <-----------><--------------><---------><----------------><---------------------><----> - * 16 16 8 8 4 1 - */ - #define MAX_CONTEXT_SIZE 53 +/* + * +-----------+---------------+----------+-----------------+----------------------+-----+ + * | s16-s31 | s0-s15, FPSCR | r4-r11 | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL | | + * | | | | PC, xPSR | EXC_RETURN | | + * +-----------+---------------+----------+-----------------+----------------------+-----+ + * + * <-----------><--------------><---------><----------------><---------------------><----> + * 16 16 8 8 4 1 + */ + #define MAX_CONTEXT_SIZE 53 #endif /* #if( configENABLE_TRUSTZONE == 1 ) */ #else /* #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */ - #if( configENABLE_TRUSTZONE == 1 ) + #if ( configENABLE_TRUSTZONE == 1 ) - /* - * +----------+-----------------+------------------------------+-----+ - * | r4-r11 | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, | | - * | | PC, xPSR | CONTROL, EXC_RETURN | | - * +----------+-----------------+------------------------------+-----+ - * - * <---------><----------------><------------------------------><----> - * 8 8 5 1 - */ - #define MAX_CONTEXT_SIZE 22 +/* + * +----------+-----------------+------------------------------+-----+ + * | r4-r11 | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, | | + * | | PC, xPSR | CONTROL, EXC_RETURN | | + * +----------+-----------------+------------------------------+-----+ + * + * <---------><----------------><------------------------------><----> + * 8 8 5 1 + */ + #define MAX_CONTEXT_SIZE 22 #else /* #if( configENABLE_TRUSTZONE == 1 ) */ - /* - * +----------+-----------------+----------------------+-----+ - * | r4-r11 | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL | | - * | | PC, xPSR | EXC_RETURN | | - * +----------+-----------------+----------------------+-----+ - * - * <---------><----------------><----------------------><----> - * 8 8 4 1 - */ - #define MAX_CONTEXT_SIZE 21 +/* + * +----------+-----------------+----------------------+-----+ + * | r4-r11 | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL | | + * | | PC, xPSR | EXC_RETURN | | + * +----------+-----------------+----------------------+-----+ + * + * <---------><----------------><----------------------><----> + * 8 8 4 1 + */ + #define MAX_CONTEXT_SIZE 21 #endif /* #if( configENABLE_TRUSTZONE == 1 ) */ #endif /* #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */ - /* Flags used for xMPU_SETTINGS.ulTaskFlags member. */ - #define portSTACK_FRAME_HAS_PADDING_FLAG ( 1UL << 0UL ) - #define portTASK_IS_PRIVILEGED_FLAG ( 1UL << 1UL ) +/* Flags used for xMPU_SETTINGS.ulTaskFlags member. */ + #define portSTACK_FRAME_HAS_PADDING_FLAG ( 1UL << 0UL ) + #define portTASK_IS_PRIVILEGED_FLAG ( 1UL << 1UL ) /* Size of an Access Control List (ACL) entry in bits. */ #define portACL_ENTRY_SIZE_BITS ( 32U ) @@ -313,7 +313,7 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P * system calls. */ #ifdef configASSERT - #if ( portHAS_BASEPRI == 1 ) + #if ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) void vPortValidateInterruptPriority( void ); #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() vPortValidateInterruptPriority() #endif @@ -333,12 +333,29 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P /** * @brief Scheduler utilities. */ -#define portYIELD() vPortYield() +#if ( configENABLE_MPU == 1 ) + #define portYIELD() __asm volatile ( "svc %0" ::"i" ( portSVC_YIELD ) : "memory" ) + #define portYIELD_WITHIN_API() vPortYield() +#else + #define portYIELD() vPortYield() + #define portYIELD_WITHIN_API() vPortYield() +#endif + #define portNVIC_INT_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed04 ) ) #define portNVIC_PENDSVSET_BIT ( 1UL << 28UL ) -#define portEND_SWITCHING_ISR( xSwitchRequired ) \ - do { if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; } \ - while( 0 ) +#define portEND_SWITCHING_ISR( xSwitchRequired ) \ + do \ + { \ + if( xSwitchRequired ) \ + { \ + traceISR_EXIT_TO_SCHEDULER(); \ + portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; \ + } \ + else \ + { \ + traceISR_EXIT(); \ + } \ + } while( 0 ) #define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x ) /*-----------------------------------------------------------*/ @@ -424,12 +441,12 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P extern BaseType_t xPortIsTaskPrivileged( void ); - /** - * @brief Checks whether or not the calling task is privileged. - * - * @return pdTRUE if the calling task is privileged, pdFALSE otherwise. - */ - #define portIS_TASK_PRIVILEGED() xPortIsTaskPrivileged() +/** + * @brief Checks whether or not the calling task is privileged. + * + * @return pdTRUE if the calling task is privileged, pdFALSE otherwise. + */ + #define portIS_TASK_PRIVILEGED() xPortIsTaskPrivileged() #endif /* configENABLE_MPU == 1 */ /*-----------------------------------------------------------*/ @@ -440,6 +457,56 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P #define portMEMORY_BARRIER() __asm volatile ( "" ::: "memory" ) /*-----------------------------------------------------------*/ +/* Select correct value of configUSE_PORT_OPTIMISED_TASK_SELECTION + * based on whether or not Mainline extension is implemented. */ +#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION + #if ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) + #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1 + #else + #define configUSE_PORT_OPTIMISED_TASK_SELECTION 0 + #endif +#endif /* #ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION */ + +/** + * @brief Port-optimised task selection. + */ +#if ( configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 ) + +/** + * @brief Count the number of leading zeros in a 32-bit value. + */ + static portFORCE_INLINE uint32_t ulPortCountLeadingZeros( uint32_t ulBitmap ) + { + uint32_t ulReturn; + + __asm volatile ( "clz %0, %1" : "=r" ( ulReturn ) : "r" ( ulBitmap ) : "memory" ); + + return ulReturn; + } + +/* Check the configuration. */ + #if ( configMAX_PRIORITIES > 32 ) + #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 different priorities as tasks that share a priority will time slice. + #endif + + #if ( portHAS_ARMV8M_MAIN_EXTENSION == 0 ) + #error ARMv8-M baseline implementations (such as Cortex-M23) do not support port-optimised task selection. Please set configUSE_PORT_OPTIMISED_TASK_SELECTION to 0 or leave it undefined. + #endif + +/** + * @brief Store/clear the ready priorities in a bit map. + */ + #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) ) + #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) ) + +/** + * @brief Get the priority of the highest-priority task that is ready to execute. + */ + #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - ulPortCountLeadingZeros( ( uxReadyPriorities ) ) ) + +#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */ +/*-----------------------------------------------------------*/ + /* *INDENT-OFF* */ #ifdef __cplusplus } diff --git a/Source/portable/GCC/ARM_CM35P/secure/secure_context.c b/Source/portable/GCC/ARM_CM35P/secure/secure_context.c index e37dd9672..83b3dbce1 100644 --- a/Source/portable/GCC/ARM_CM35P/secure/secure_context.c +++ b/Source/portable/GCC/ARM_CM35P/secure/secure_context.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -65,7 +65,7 @@ * @brief Maximum number of secure contexts. */ #ifndef secureconfigMAX_SECURE_CONTEXTS - #define secureconfigMAX_SECURE_CONTEXTS 8UL + #define secureconfigMAX_SECURE_CONTEXTS 8UL #endif /*-----------------------------------------------------------*/ @@ -164,15 +164,15 @@ secureportNON_SECURE_CALLABLE void SecureContext_Init( void ) } #if ( configENABLE_MPU == 1 ) - { - /* Configure thread mode to use PSP and to be unprivileged. */ - secureportSET_CONTROL( securecontextCONTROL_VALUE_UNPRIVILEGED ); - } + { + /* Configure thread mode to use PSP and to be unprivileged. */ + secureportSET_CONTROL( securecontextCONTROL_VALUE_UNPRIVILEGED ); + } #else /* configENABLE_MPU */ - { - /* Configure thread mode to use PSP and to be privileged. */ - secureportSET_CONTROL( securecontextCONTROL_VALUE_PRIVILEGED ); - } + { + /* Configure thread mode to use PSP and to be privileged. */ + secureportSET_CONTROL( securecontextCONTROL_VALUE_PRIVILEGED ); + } #endif /* configENABLE_MPU */ } } @@ -219,16 +219,16 @@ secureportNON_SECURE_CALLABLE void SecureContext_Init( void ) if( pucStackMemory != NULL ) { /* Since stack grows down, the starting point will be the last - * location. Note that this location is next to the last - * allocated byte for stack (excluding the space for seal values) - * because the hardware decrements the stack pointer before - * writing i.e. if stack pointer is 0x2, a push operation will - * decrement the stack pointer to 0x1 and then write at 0x1. */ + * location. Note that this location is next to the last + * allocated byte for stack (excluding the space for seal values) + * because the hardware decrements the stack pointer before + * writing i.e. if stack pointer is 0x2, a push operation will + * decrement the stack pointer to 0x1 and then write at 0x1. */ xSecureContexts[ ulSecureContextIndex ].pucStackStart = pucStackMemory + ulSecureStackSize; /* Seal the created secure process stack. */ - *( uint32_t * )( pucStackMemory + ulSecureStackSize ) = securecontextSTACK_SEAL_VALUE; - *( uint32_t * )( pucStackMemory + ulSecureStackSize + 4 ) = securecontextSTACK_SEAL_VALUE; + *( uint32_t * ) ( pucStackMemory + ulSecureStackSize ) = securecontextSTACK_SEAL_VALUE; + *( uint32_t * ) ( pucStackMemory + ulSecureStackSize + 4 ) = securecontextSTACK_SEAL_VALUE; /* The stack cannot go beyond this location. This value is * programmed in the PSPLIM register on context switch.*/ @@ -237,32 +237,32 @@ secureportNON_SECURE_CALLABLE void SecureContext_Init( void ) xSecureContexts[ ulSecureContextIndex ].pvTaskHandle = pvTaskHandle; #if ( configENABLE_MPU == 1 ) + { + /* Store the correct CONTROL value for the task on the stack. + * This value is programmed in the CONTROL register on + * context switch. */ + pulCurrentStackPointer = ( uint32_t * ) xSecureContexts[ ulSecureContextIndex ].pucStackStart; + pulCurrentStackPointer--; + + if( ulIsTaskPrivileged ) { - /* Store the correct CONTROL value for the task on the stack. - * This value is programmed in the CONTROL register on - * context switch. */ - pulCurrentStackPointer = ( uint32_t * ) xSecureContexts[ ulSecureContextIndex ].pucStackStart; - pulCurrentStackPointer--; - - if( ulIsTaskPrivileged ) - { - *( pulCurrentStackPointer ) = securecontextCONTROL_VALUE_PRIVILEGED; - } - else - { - *( pulCurrentStackPointer ) = securecontextCONTROL_VALUE_UNPRIVILEGED; - } - - /* Store the current stack pointer. This value is programmed in - * the PSP register on context switch. */ - xSecureContexts[ ulSecureContextIndex ].pucCurrentStackPointer = ( uint8_t * ) pulCurrentStackPointer; + *( pulCurrentStackPointer ) = securecontextCONTROL_VALUE_PRIVILEGED; } - #else /* configENABLE_MPU */ + else { - /* Current SP is set to the starting of the stack. This - * value programmed in the PSP register on context switch. */ - xSecureContexts[ ulSecureContextIndex ].pucCurrentStackPointer = xSecureContexts[ ulSecureContextIndex ].pucStackStart; + *( pulCurrentStackPointer ) = securecontextCONTROL_VALUE_UNPRIVILEGED; } + + /* Store the current stack pointer. This value is programmed in + * the PSP register on context switch. */ + xSecureContexts[ ulSecureContextIndex ].pucCurrentStackPointer = ( uint8_t * ) pulCurrentStackPointer; + } + #else /* configENABLE_MPU */ + { + /* Current SP is set to the starting of the stack. This + * value programmed in the PSP register on context switch. */ + xSecureContexts[ ulSecureContextIndex ].pucCurrentStackPointer = xSecureContexts[ ulSecureContextIndex ].pucStackStart; + } #endif /* configENABLE_MPU */ /* Ensure to never return 0 as a valid context handle. */ @@ -275,7 +275,8 @@ secureportNON_SECURE_CALLABLE void SecureContext_Init( void ) } /*-----------------------------------------------------------*/ -secureportNON_SECURE_CALLABLE void SecureContext_FreeContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle ) +secureportNON_SECURE_CALLABLE void SecureContext_FreeContext( SecureContextHandle_t xSecureContextHandle, + void * pvTaskHandle ) { uint32_t ulIPSR, ulSecureContextIndex; @@ -306,7 +307,8 @@ secureportNON_SECURE_CALLABLE void SecureContext_FreeContext( SecureContextHandl } /*-----------------------------------------------------------*/ -secureportNON_SECURE_CALLABLE void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle ) +secureportNON_SECURE_CALLABLE void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle, + void * pvTaskHandle ) { uint8_t * pucStackLimit; uint32_t ulSecureContextIndex; @@ -328,7 +330,8 @@ secureportNON_SECURE_CALLABLE void SecureContext_LoadContext( SecureContextHandl } /*-----------------------------------------------------------*/ -secureportNON_SECURE_CALLABLE void SecureContext_SaveContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle ) +secureportNON_SECURE_CALLABLE void SecureContext_SaveContext( SecureContextHandle_t xSecureContextHandle, + void * pvTaskHandle ) { uint8_t * pucStackLimit; uint32_t ulSecureContextIndex; diff --git a/Source/portable/GCC/ARM_CM35P/secure/secure_context.h b/Source/portable/GCC/ARM_CM35P/secure/secure_context.h index 2220ea646..40fdc276d 100644 --- a/Source/portable/GCC/ARM_CM35P/secure/secure_context.h +++ b/Source/portable/GCC/ARM_CM35P/secure/secure_context.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -38,12 +38,12 @@ /** * @brief PSP value when no secure context is loaded. */ -#define securecontextNO_STACK 0x0 +#define securecontextNO_STACK 0x0 /** * @brief Invalid context ID. */ -#define securecontextINVALID_CONTEXT_ID 0UL +#define securecontextINVALID_CONTEXT_ID 0UL /*-----------------------------------------------------------*/ /** @@ -108,7 +108,8 @@ void SecureContext_Init( void ); * @param[in] xSecureContextHandle Context handle corresponding to the * context to be freed. */ -void SecureContext_FreeContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle ); +void SecureContext_FreeContext( SecureContextHandle_t xSecureContextHandle, + void * pvTaskHandle ); /** * @brief Loads the given context. @@ -119,7 +120,8 @@ void SecureContext_FreeContext( SecureContextHandle_t xSecureContextHandle, void * @param[in] xSecureContextHandle Context handle corresponding to the context * to be loaded. */ -void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle ); +void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle, + void * pvTaskHandle ); /** * @brief Saves the given context. @@ -130,6 +132,7 @@ void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle, void * @param[in] xSecureContextHandle Context handle corresponding to the context * to be saved. */ -void SecureContext_SaveContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle ); +void SecureContext_SaveContext( SecureContextHandle_t xSecureContextHandle, + void * pvTaskHandle ); #endif /* __SECURE_CONTEXT_H__ */ diff --git a/Source/portable/GCC/ARM_CM35P/secure/secure_context_port.c b/Source/portable/GCC/ARM_CM35P/secure/secure_context_port.c index d70822c06..31c1f7331 100644 --- a/Source/portable/GCC/ARM_CM35P/secure/secure_context_port.c +++ b/Source/portable/GCC/ARM_CM35P/secure/secure_context_port.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/Source/portable/GCC/ARM_CM35P/secure/secure_heap.c b/Source/portable/GCC/ARM_CM35P/secure/secure_heap.c index 19f7c2354..d9789404b 100644 --- a/Source/portable/GCC/ARM_CM35P/secure/secure_heap.c +++ b/Source/portable/GCC/ARM_CM35P/secure/secure_heap.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -62,6 +62,22 @@ /* Assumes 8bit bytes! */ #define secureheapBITS_PER_BYTE ( ( size_t ) 8 ) + +/* Max value that fits in a size_t type. */ +#define secureheapSIZE_MAX ( ~( ( size_t ) 0 ) ) + +/* Check if adding a and b will result in overflow. */ +#define secureheapADD_WILL_OVERFLOW( a, b ) ( ( a ) > ( secureheapSIZE_MAX - ( b ) ) ) + +/* MSB of the xBlockSize member of an BlockLink_t structure is used to track + * the allocation status of a block. When MSB of the xBlockSize member of + * an BlockLink_t structure is set then the block belongs to the application. + * When the bit is free the block is still part of the free heap space. */ +#define secureheapBLOCK_ALLOCATED_BITMASK ( ( ( size_t ) 1 ) << ( ( sizeof( size_t ) * secureheapBITS_PER_BYTE ) - 1 ) ) +#define secureheapBLOCK_SIZE_IS_VALID( xBlockSize ) ( ( ( xBlockSize ) & secureheapBLOCK_ALLOCATED_BITMASK ) == 0 ) +#define secureheapBLOCK_IS_ALLOCATED( pxBlock ) ( ( ( pxBlock->xBlockSize ) & secureheapBLOCK_ALLOCATED_BITMASK ) != 0 ) +#define secureheapALLOCATE_BLOCK( pxBlock ) ( ( pxBlock->xBlockSize ) |= secureheapBLOCK_ALLOCATED_BITMASK ) +#define secureheapFREE_BLOCK( pxBlock ) ( ( pxBlock->xBlockSize ) &= ~secureheapBLOCK_ALLOCATED_BITMASK ) /*-----------------------------------------------------------*/ /* Allocate the memory for the heap. */ @@ -123,14 +139,6 @@ static BlockLink_t * pxEnd = NULL; static size_t xFreeBytesRemaining = 0U; static size_t xMinimumEverFreeBytesRemaining = 0U; -/** - * @brief Gets set to the top bit of an size_t type. - * - * When this bit in the xBlockSize member of an BlockLink_t structure is set - * then the block belongs to the application. When the bit is free the block is - * still part of the free heap space. - */ -static size_t xBlockAllocatedBit = 0; /*-----------------------------------------------------------*/ static void prvHeapInit( void ) @@ -175,9 +183,6 @@ static void prvHeapInit( void ) /* Only one block exists - and it covers the entire usable heap space. */ xMinimumEverFreeBytesRemaining = pxFirstFreeBlock->xBlockSize; xFreeBytesRemaining = pxFirstFreeBlock->xBlockSize; - - /* Work out the position of the top bit in a size_t variable. */ - xBlockAllocatedBit = ( ( size_t ) 1 ) << ( ( sizeof( size_t ) * secureheapBITS_PER_BYTE ) - 1 ); } /*-----------------------------------------------------------*/ @@ -250,6 +255,7 @@ void * pvPortMalloc( size_t xWantedSize ) BlockLink_t * pxPreviousBlock; BlockLink_t * pxNewBlockLink; void * pvReturn = NULL; + size_t xAdditionalRequiredSize; /* If this is the first call to malloc then the heap will require * initialisation to setup the list of free blocks. */ @@ -262,25 +268,29 @@ void * pvPortMalloc( size_t xWantedSize ) mtCOVERAGE_TEST_MARKER(); } - /* Check the requested block size is not so large that the top bit is set. - * The top bit of the block size member of the BlockLink_t structure is used - * to determine who owns the block - the application or the kernel, so it - * must be free. */ - if( ( xWantedSize & xBlockAllocatedBit ) == 0 ) + if( xWantedSize > 0 ) { - /* The wanted size is increased so it can contain a BlockLink_t + /* The wanted size must be increased so it can contain a BlockLink_t * structure in addition to the requested amount of bytes. */ - if( xWantedSize > 0 ) + if( secureheapADD_WILL_OVERFLOW( xWantedSize, xHeapStructSize ) == 0 ) { xWantedSize += xHeapStructSize; - /* Ensure that blocks are always aligned to the required number of - * bytes. */ + /* Ensure that blocks are always aligned to the required number + * of bytes. */ if( ( xWantedSize & secureportBYTE_ALIGNMENT_MASK ) != 0x00 ) { /* Byte alignment required. */ - xWantedSize += ( secureportBYTE_ALIGNMENT - ( xWantedSize & secureportBYTE_ALIGNMENT_MASK ) ); - secureportASSERT( ( xWantedSize & secureportBYTE_ALIGNMENT_MASK ) == 0 ); + xAdditionalRequiredSize = secureportBYTE_ALIGNMENT - ( xWantedSize & secureportBYTE_ALIGNMENT_MASK ); + + if( secureheapADD_WILL_OVERFLOW( xWantedSize, xAdditionalRequiredSize ) == 0 ) + { + xWantedSize += xAdditionalRequiredSize; + } + else + { + xWantedSize = 0; + } } else { @@ -289,9 +299,20 @@ void * pvPortMalloc( size_t xWantedSize ) } else { - mtCOVERAGE_TEST_MARKER(); + xWantedSize = 0; } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + /* Check the requested block size is not so large that the top bit is set. + * The top bit of the block size member of the BlockLink_t structure is used + * to determine who owns the block - the application or the kernel, so it + * must be free. */ + if( secureheapBLOCK_SIZE_IS_VALID( xWantedSize ) != 0 ) + { if( ( xWantedSize > 0 ) && ( xWantedSize <= xFreeBytesRemaining ) ) { /* Traverse the list from the start (lowest address) block until @@ -334,7 +355,8 @@ void * pvPortMalloc( size_t xWantedSize ) pxBlock->xBlockSize = xWantedSize; /* Insert the new block into the list of free blocks. */ - prvInsertBlockIntoFreeList( pxNewBlockLink ); + pxNewBlockLink->pxNextFreeBlock = pxPreviousBlock->pxNextFreeBlock; + pxPreviousBlock->pxNextFreeBlock = pxNewBlockLink; } else { @@ -354,7 +376,7 @@ void * pvPortMalloc( size_t xWantedSize ) /* The block is being returned - it is allocated and owned by * the application and has no "next" block. */ - pxBlock->xBlockSize |= xBlockAllocatedBit; + secureheapALLOCATE_BLOCK( pxBlock ); pxBlock->pxNextFreeBlock = NULL; } else @@ -375,17 +397,17 @@ void * pvPortMalloc( size_t xWantedSize ) traceMALLOC( pvReturn, xWantedSize ); #if ( secureconfigUSE_MALLOC_FAILED_HOOK == 1 ) + { + if( pvReturn == NULL ) { - if( pvReturn == NULL ) - { - extern void vApplicationMallocFailedHook( void ); - vApplicationMallocFailedHook(); - } - else - { - mtCOVERAGE_TEST_MARKER(); - } + extern void vApplicationMallocFailedHook( void ); + vApplicationMallocFailedHook(); } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } #endif /* if ( secureconfigUSE_MALLOC_FAILED_HOOK == 1 ) */ secureportASSERT( ( ( ( size_t ) pvReturn ) & ( size_t ) secureportBYTE_ALIGNMENT_MASK ) == 0 ); @@ -408,16 +430,16 @@ void vPortFree( void * pv ) pxLink = ( void * ) puc; /* Check the block is actually allocated. */ - secureportASSERT( ( pxLink->xBlockSize & xBlockAllocatedBit ) != 0 ); + secureportASSERT( secureheapBLOCK_IS_ALLOCATED( pxLink ) != 0 ); secureportASSERT( pxLink->pxNextFreeBlock == NULL ); - if( ( pxLink->xBlockSize & xBlockAllocatedBit ) != 0 ) + if( secureheapBLOCK_IS_ALLOCATED( pxLink ) != 0 ) { if( pxLink->pxNextFreeBlock == NULL ) { /* The block is being returned to the heap - it is no longer * allocated. */ - pxLink->xBlockSize &= ~xBlockAllocatedBit; + secureheapFREE_BLOCK( pxLink ); secureportDISABLE_NON_SECURE_INTERRUPTS(); { diff --git a/Source/portable/GCC/ARM_CM35P/secure/secure_heap.h b/Source/portable/GCC/ARM_CM35P/secure/secure_heap.h index 75c9cb00b..cf5551046 100644 --- a/Source/portable/GCC/ARM_CM35P/secure/secure_heap.h +++ b/Source/portable/GCC/ARM_CM35P/secure/secure_heap.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/Source/portable/GCC/ARM_CM35P/secure/secure_init.c b/Source/portable/GCC/ARM_CM35P/secure/secure_init.c index f93bfce95..66d35eccc 100644 --- a/Source/portable/GCC/ARM_CM35P/secure/secure_init.c +++ b/Source/portable/GCC/ARM_CM35P/secure/secure_init.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -93,7 +93,7 @@ secureportNON_SECURE_CALLABLE void SecureInit_EnableNSFPUAccess( void ) * permitted. CP11 should be programmed to the same value as CP10. */ *( secureinitNSACR ) |= ( secureinitNSACR_CP10_MASK | secureinitNSACR_CP11_MASK ); - /* LSPENS = 0 ==> LSPEN is writable fron non-secure state. This ensures + /* LSPENS = 0 ==> LSPEN is writable from non-secure state. This ensures * that we can enable/disable lazy stacking in port.c file. */ *( secureinitFPCCR ) &= ~( secureinitFPCCR_LSPENS_MASK ); diff --git a/Source/portable/GCC/ARM_CM35P/secure/secure_init.h b/Source/portable/GCC/ARM_CM35P/secure/secure_init.h index e6c9da0b4..6404c5cc4 100644 --- a/Source/portable/GCC/ARM_CM35P/secure/secure_init.h +++ b/Source/portable/GCC/ARM_CM35P/secure/secure_init.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/Source/portable/GCC/ARM_CM35P/secure/secure_port_macros.h b/Source/portable/GCC/ARM_CM35P/secure/secure_port_macros.h index d7ac5833c..085108cc1 100644 --- a/Source/portable/GCC/ARM_CM35P/secure/secure_port_macros.h +++ b/Source/portable/GCC/ARM_CM35P/secure/secure_port_macros.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/Source/portable/GCC/ARM_CM35P_NTZ/non_secure/mpu_wrappers_v2_asm.c b/Source/portable/GCC/ARM_CM35P_NTZ/non_secure/mpu_wrappers_v2_asm.c index d247c92e0..052f97850 100644 --- a/Source/portable/GCC/ARM_CM35P_NTZ/non_secure/mpu_wrappers_v2_asm.c +++ b/Source/portable/GCC/ARM_CM35P_NTZ/non_secure/mpu_wrappers_v2_asm.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -365,31 +365,6 @@ } /*-----------------------------------------------------------*/ - char * MPU_pcTaskGetName( TaskHandle_t xTaskToQuery ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; - - char * MPU_pcTaskGetName( TaskHandle_t xTaskToQuery ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ - { - __asm volatile - ( - " .syntax unified \n" - " .extern MPU_pcTaskGetNameImpl \n" - " \n" - " push {r0} \n" - " mrs r0, control \n" - " tst r0, #1 \n" - " bne MPU_pcTaskGetName_Unpriv \n" - " MPU_pcTaskGetName_Priv: \n" - " pop {r0} \n" - " b MPU_pcTaskGetNameImpl \n" - " MPU_pcTaskGetName_Unpriv: \n" - " pop {r0} \n" - " svc %0 \n" - " \n" - : : "i" ( SYSTEM_CALL_pcTaskGetName ) : "memory" - ); - } -/*-----------------------------------------------------------*/ - #if ( configGENERATE_RUN_TIME_STATS == 1 ) configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetRunTimeCounter( const TaskHandle_t xTask ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; @@ -1512,31 +1487,27 @@ #if ( configUSE_TIMERS == 1 ) - BaseType_t MPU_xTimerGenericCommandEntry( const xTimerGenericCommandParams_t * pxParams ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + BaseType_t MPU_xTimerGenericCommandFromTaskEntry( const xTimerGenericCommandFromTaskParams_t * pxParams ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; - BaseType_t MPU_xTimerGenericCommandEntry( const xTimerGenericCommandParams_t * pxParams ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + BaseType_t MPU_xTimerGenericCommandFromTaskEntry( const xTimerGenericCommandFromTaskParams_t * pxParams ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ { __asm volatile ( - " .syntax unified \n" - " .extern MPU_xTimerGenericCommandPrivImpl \n" - " \n" - " push {r0} \n" - " mrs r0, ipsr \n" - " cmp r0, #0 \n" - " bne MPU_xTimerGenericCommand_Priv \n" - " mrs r0, control \n" - " tst r0, #1 \n" - " beq MPU_xTimerGenericCommand_Priv \n" - " MPU_xTimerGenericCommand_Unpriv: \n" - " pop {r0} \n" - " svc %0 \n" - " MPU_xTimerGenericCommand_Priv: \n" - " pop {r0} \n" - " b MPU_xTimerGenericCommandPrivImpl \n" - " \n" - " \n" - : : "i" ( SYSTEM_CALL_xTimerGenericCommand ) : "memory" + " .syntax unified \n" + " .extern MPU_xTimerGenericCommandFromTaskImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " bne MPU_xTimerGenericCommandFromTask_Unpriv \n" + " MPU_xTimerGenericCommandFromTask_Priv: \n" + " pop {r0} \n" + " b MPU_xTimerGenericCommandFromTaskImpl \n" + " MPU_xTimerGenericCommandFromTask_Unpriv: \n" + " pop {r0} \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xTimerGenericCommandFromTask ) : "memory" ); } diff --git a/Source/portable/GCC/ARM_CM35P_NTZ/non_secure/port.c b/Source/portable/GCC/ARM_CM35P_NTZ/non_secure/port.c index 9712ac353..230fe5fc2 100644 --- a/Source/portable/GCC/ARM_CM35P_NTZ/non_secure/port.c +++ b/Source/portable/GCC/ARM_CM35P_NTZ/non_secure/port.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -68,6 +68,22 @@ #if ( ( configRUN_FREERTOS_SECURE_ONLY == 1 ) && ( configENABLE_TRUSTZONE == 1 ) ) #error TrustZone needs to be disabled in order to run FreeRTOS on the Secure Side. #endif + +/** + * Cortex-M23 does not have non-secure PSPLIM. We should use PSPLIM on Cortex-M23 + * only when FreeRTOS runs on secure side. + */ +#if ( ( portHAS_ARMV8M_MAIN_EXTENSION == 0 ) && ( configRUN_FREERTOS_SECURE_ONLY == 0 ) ) + #define portUSE_PSPLIM_REGISTER 0 +#else + #define portUSE_PSPLIM_REGISTER 1 +#endif +/*-----------------------------------------------------------*/ + +/** + * @brief Prototype of all Interrupt Service Routines (ISRs). + */ +typedef void ( * portISR_t )( void ); /*-----------------------------------------------------------*/ /** @@ -91,10 +107,18 @@ /** * @brief Constants required to manipulate the SCB. */ -#define portSCB_SYS_HANDLER_CTRL_STATE_REG ( *( volatile uint32_t * ) 0xe000ed24 ) +#define portSCB_VTOR_REG ( *( ( portISR_t ** ) 0xe000ed08 ) ) +#define portSCB_SYS_HANDLER_CTRL_STATE_REG ( *( ( volatile uint32_t * ) 0xe000ed24 ) ) #define portSCB_MEM_FAULT_ENABLE_BIT ( 1UL << 16UL ) /*-----------------------------------------------------------*/ +/** + * @brief Constants used to check the installation of the FreeRTOS interrupt handlers. + */ +#define portVECTOR_INDEX_SVC ( 11 ) +#define portVECTOR_INDEX_PENDSV ( 14 ) +/*-----------------------------------------------------------*/ + /** * @brief Constants required to check the validity of an interrupt priority. */ @@ -111,8 +135,8 @@ /** * @brief Constants used during system call enter and exit. */ -#define portPSR_STACK_PADDING_MASK ( 1UL << 9UL ) -#define portEXC_RETURN_STACK_FRAME_TYPE_MASK ( 1UL << 4UL ) +#define portPSR_STACK_PADDING_MASK ( 1UL << 9UL ) +#define portEXC_RETURN_STACK_FRAME_TYPE_MASK ( 1UL << 4UL ) /*-----------------------------------------------------------*/ /** @@ -134,81 +158,81 @@ /** * @brief Offsets in the stack to the parameters when inside the SVC handler. */ -#define portOFFSET_TO_LR ( 5 ) -#define portOFFSET_TO_PC ( 6 ) -#define portOFFSET_TO_PSR ( 7 ) +#define portOFFSET_TO_LR ( 5 ) +#define portOFFSET_TO_PC ( 6 ) +#define portOFFSET_TO_PSR ( 7 ) /*-----------------------------------------------------------*/ /** * @brief Constants required to manipulate the MPU. */ -#define portMPU_TYPE_REG ( *( ( volatile uint32_t * ) 0xe000ed90 ) ) -#define portMPU_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed94 ) ) -#define portMPU_RNR_REG ( *( ( volatile uint32_t * ) 0xe000ed98 ) ) +#define portMPU_TYPE_REG ( *( ( volatile uint32_t * ) 0xe000ed90 ) ) +#define portMPU_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed94 ) ) +#define portMPU_RNR_REG ( *( ( volatile uint32_t * ) 0xe000ed98 ) ) -#define portMPU_RBAR_REG ( *( ( volatile uint32_t * ) 0xe000ed9c ) ) -#define portMPU_RLAR_REG ( *( ( volatile uint32_t * ) 0xe000eda0 ) ) +#define portMPU_RBAR_REG ( *( ( volatile uint32_t * ) 0xe000ed9c ) ) +#define portMPU_RLAR_REG ( *( ( volatile uint32_t * ) 0xe000eda0 ) ) -#define portMPU_RBAR_A1_REG ( *( ( volatile uint32_t * ) 0xe000eda4 ) ) -#define portMPU_RLAR_A1_REG ( *( ( volatile uint32_t * ) 0xe000eda8 ) ) +#define portMPU_RBAR_A1_REG ( *( ( volatile uint32_t * ) 0xe000eda4 ) ) +#define portMPU_RLAR_A1_REG ( *( ( volatile uint32_t * ) 0xe000eda8 ) ) -#define portMPU_RBAR_A2_REG ( *( ( volatile uint32_t * ) 0xe000edac ) ) -#define portMPU_RLAR_A2_REG ( *( ( volatile uint32_t * ) 0xe000edb0 ) ) +#define portMPU_RBAR_A2_REG ( *( ( volatile uint32_t * ) 0xe000edac ) ) +#define portMPU_RLAR_A2_REG ( *( ( volatile uint32_t * ) 0xe000edb0 ) ) -#define portMPU_RBAR_A3_REG ( *( ( volatile uint32_t * ) 0xe000edb4 ) ) -#define portMPU_RLAR_A3_REG ( *( ( volatile uint32_t * ) 0xe000edb8 ) ) +#define portMPU_RBAR_A3_REG ( *( ( volatile uint32_t * ) 0xe000edb4 ) ) +#define portMPU_RLAR_A3_REG ( *( ( volatile uint32_t * ) 0xe000edb8 ) ) -#define portMPU_MAIR0_REG ( *( ( volatile uint32_t * ) 0xe000edc0 ) ) -#define portMPU_MAIR1_REG ( *( ( volatile uint32_t * ) 0xe000edc4 ) ) +#define portMPU_MAIR0_REG ( *( ( volatile uint32_t * ) 0xe000edc0 ) ) +#define portMPU_MAIR1_REG ( *( ( volatile uint32_t * ) 0xe000edc4 ) ) -#define portMPU_RBAR_ADDRESS_MASK ( 0xffffffe0 ) /* Must be 32-byte aligned. */ -#define portMPU_RLAR_ADDRESS_MASK ( 0xffffffe0 ) /* Must be 32-byte aligned. */ +#define portMPU_RBAR_ADDRESS_MASK ( 0xffffffe0 ) /* Must be 32-byte aligned. */ +#define portMPU_RLAR_ADDRESS_MASK ( 0xffffffe0 ) /* Must be 32-byte aligned. */ -#define portMPU_RBAR_ACCESS_PERMISSIONS_MASK ( 3UL << 1UL ) +#define portMPU_RBAR_ACCESS_PERMISSIONS_MASK ( 3UL << 1UL ) -#define portMPU_MAIR_ATTR0_POS ( 0UL ) -#define portMPU_MAIR_ATTR0_MASK ( 0x000000ff ) +#define portMPU_MAIR_ATTR0_POS ( 0UL ) +#define portMPU_MAIR_ATTR0_MASK ( 0x000000ff ) -#define portMPU_MAIR_ATTR1_POS ( 8UL ) -#define portMPU_MAIR_ATTR1_MASK ( 0x0000ff00 ) +#define portMPU_MAIR_ATTR1_POS ( 8UL ) +#define portMPU_MAIR_ATTR1_MASK ( 0x0000ff00 ) -#define portMPU_MAIR_ATTR2_POS ( 16UL ) -#define portMPU_MAIR_ATTR2_MASK ( 0x00ff0000 ) +#define portMPU_MAIR_ATTR2_POS ( 16UL ) +#define portMPU_MAIR_ATTR2_MASK ( 0x00ff0000 ) -#define portMPU_MAIR_ATTR3_POS ( 24UL ) -#define portMPU_MAIR_ATTR3_MASK ( 0xff000000 ) +#define portMPU_MAIR_ATTR3_POS ( 24UL ) +#define portMPU_MAIR_ATTR3_MASK ( 0xff000000 ) -#define portMPU_MAIR_ATTR4_POS ( 0UL ) -#define portMPU_MAIR_ATTR4_MASK ( 0x000000ff ) +#define portMPU_MAIR_ATTR4_POS ( 0UL ) +#define portMPU_MAIR_ATTR4_MASK ( 0x000000ff ) -#define portMPU_MAIR_ATTR5_POS ( 8UL ) -#define portMPU_MAIR_ATTR5_MASK ( 0x0000ff00 ) +#define portMPU_MAIR_ATTR5_POS ( 8UL ) +#define portMPU_MAIR_ATTR5_MASK ( 0x0000ff00 ) -#define portMPU_MAIR_ATTR6_POS ( 16UL ) -#define portMPU_MAIR_ATTR6_MASK ( 0x00ff0000 ) +#define portMPU_MAIR_ATTR6_POS ( 16UL ) +#define portMPU_MAIR_ATTR6_MASK ( 0x00ff0000 ) -#define portMPU_MAIR_ATTR7_POS ( 24UL ) -#define portMPU_MAIR_ATTR7_MASK ( 0xff000000 ) +#define portMPU_MAIR_ATTR7_POS ( 24UL ) +#define portMPU_MAIR_ATTR7_MASK ( 0xff000000 ) -#define portMPU_RLAR_ATTR_INDEX0 ( 0UL << 1UL ) -#define portMPU_RLAR_ATTR_INDEX1 ( 1UL << 1UL ) -#define portMPU_RLAR_ATTR_INDEX2 ( 2UL << 1UL ) -#define portMPU_RLAR_ATTR_INDEX3 ( 3UL << 1UL ) -#define portMPU_RLAR_ATTR_INDEX4 ( 4UL << 1UL ) -#define portMPU_RLAR_ATTR_INDEX5 ( 5UL << 1UL ) -#define portMPU_RLAR_ATTR_INDEX6 ( 6UL << 1UL ) -#define portMPU_RLAR_ATTR_INDEX7 ( 7UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX0 ( 0UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX1 ( 1UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX2 ( 2UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX3 ( 3UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX4 ( 4UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX5 ( 5UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX6 ( 6UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX7 ( 7UL << 1UL ) -#define portMPU_RLAR_REGION_ENABLE ( 1UL ) +#define portMPU_RLAR_REGION_ENABLE ( 1UL ) /* Enable privileged access to unmapped region. */ -#define portMPU_PRIV_BACKGROUND_ENABLE_BIT ( 1UL << 2UL ) +#define portMPU_PRIV_BACKGROUND_ENABLE_BIT ( 1UL << 2UL ) /* Enable MPU. */ -#define portMPU_ENABLE_BIT ( 1UL << 0UL ) +#define portMPU_ENABLE_BIT ( 1UL << 0UL ) /* Expected value of the portMPU_TYPE register. */ -#define portEXPECTED_MPU_TYPE_VALUE ( configTOTAL_MPU_REGIONS << 8UL ) +#define portEXPECTED_MPU_TYPE_VALUE ( configTOTAL_MPU_REGIONS << 8UL ) /* Extract first address of the MPU region as encoded in the * RBAR (Region Base Address Register) value. */ @@ -448,13 +472,13 @@ portDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIV #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) - /** - * @brief Sets up the task stack so that upon returning from - * SVC, the task stack is used again. - * - * @param pulSystemCallStack The current SP when the SVC was raised. - * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler. - */ +/** + * @brief Sets up the task stack so that upon returning from + * SVC, the task stack is used again. + * + * @param pulSystemCallStack The current SP when the SVC was raised. + * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler. + */ void vSystemCallExit( uint32_t * pulSystemCallStack, uint32_t ulLR ) PRIVILEGED_FUNCTION; @@ -462,11 +486,11 @@ portDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIV #if ( configENABLE_MPU == 1 ) - /** - * @brief Checks whether or not the calling task is privileged. - * - * @return pdTRUE if the calling task is privileged, pdFALSE otherwise. - */ +/** + * @brief Checks whether or not the calling task is privileged. + * + * @return pdTRUE if the calling task is privileged, pdFALSE otherwise. + */ BaseType_t xPortIsTaskPrivileged( void ) PRIVILEGED_FUNCTION; #endif /* configENABLE_MPU == 1 */ @@ -501,13 +525,13 @@ PRIVILEGED_DATA static volatile uint32_t ulCriticalNesting = 0xaaaaaaaaUL; * FreeRTOS API functions are not called from interrupts that have been assigned * a priority above configMAX_SYSCALL_INTERRUPT_PRIORITY. */ -#if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) ) +#if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) static uint8_t ucMaxSysCallPriority = 0; static uint32_t ulMaxPRIGROUPValue = 0; static const volatile uint8_t * const pcInterruptPriorityRegisters = ( const volatile uint8_t * ) portNVIC_IP_REGISTERS_OFFSET_16; -#endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) ) */ +#endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */ #if ( configUSE_TICKLESS_IDLE == 1 ) @@ -760,8 +784,15 @@ __attribute__( ( weak ) ) void vPortSetupTimerInterrupt( void ) /* PRIVILEGED_FU } #endif /* configUSE_TICKLESS_IDLE */ - /* Stop and reset the SysTick. */ - portNVIC_SYSTICK_CTRL_REG = 0UL; + /* Stop and reset SysTick. + * + * QEMU versions older than 7.0.0 contain a bug which causes an error if we + * enable SysTick without first selecting a valid clock source. We trigger + * the bug if we change clock sources from a clock with a zero clock period + * to one with a nonzero clock period and enable Systick at the same time. + * So we configure the CLKSOURCE bit here, prior to setting the ENABLE bit. + * This workaround avoids the bug in QEMU versions older than 7.0.0. */ + portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT_CONFIG; portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL; /* Configure SysTick to interrupt at the requested rate. */ @@ -819,6 +850,7 @@ static void prvTaskExitError( void ) static void prvSetupMPU( void ) /* PRIVILEGED_FUNCTION */ { #if defined( __ARMCC_VERSION ) + /* Declaration when these variable are defined in code instead of being * exported from linker scripts. */ extern uint32_t * __privileged_functions_start__; @@ -972,13 +1004,19 @@ void SysTick_Handler( void ) /* PRIVILEGED_FUNCTION */ uint32_t ulPreviousMask; ulPreviousMask = portSET_INTERRUPT_MASK_FROM_ISR(); + traceISR_ENTER(); { /* Increment the RTOS tick. */ if( xTaskIncrementTick() != pdFALSE ) { + traceISR_EXIT_TO_SCHEDULER(); /* Pend a context switch. */ portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; } + else + { + traceISR_EXIT(); + } } portCLEAR_INTERRUPT_MASK_FROM_ISR( ulPreviousMask ); } @@ -988,6 +1026,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO { #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) ) #if defined( __ARMCC_VERSION ) + /* Declaration when these variable are defined in code instead of being * exported from linker scripts. */ extern uint32_t * __syscalls_flash_start__; @@ -1083,18 +1122,24 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO vRestoreContextOfFirstTask(); break; - #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) ) - case portSVC_RAISE_PRIVILEGE: + #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) ) + case portSVC_RAISE_PRIVILEGE: - /* Only raise the privilege, if the svc was raised from any of - * the system calls. */ - if( ( ulPC >= ( uint32_t ) __syscalls_flash_start__ ) && - ( ulPC <= ( uint32_t ) __syscalls_flash_end__ ) ) - { - vRaisePrivilege(); - } - break; - #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) */ + /* Only raise the privilege, if the svc was raised from any of + * the system calls. */ + if( ( ulPC >= ( uint32_t ) __syscalls_flash_start__ ) && + ( ulPC <= ( uint32_t ) __syscalls_flash_end__ ) ) + { + vRaisePrivilege(); + } + break; + #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) */ + + #if ( configENABLE_MPU == 1 ) + case portSVC_YIELD: + vPortYield(); + break; + #endif /* configENABLE_MPU == 1 */ default: /* Incorrect SVC call. */ @@ -1154,12 +1199,11 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO { /* Extended frame i.e. FPU in use. */ ulStackFrameSize = 26; - __asm volatile - ( + __asm volatile ( " vpush {s0} \n" /* Trigger lazy stacking. */ " vpop {s0} \n" /* Nullify the affect of the above instruction. */ ::: "memory" - ); + ); } else { @@ -1171,7 +1215,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO { ulStackFrameSize = 8; } - #endif /* if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */ + #endif /* configENABLE_FPU || configENABLE_MVE */ /* Make space on the system call stack for the stack frame. */ pulSystemCallStack = pulSystemCallStack - ulStackFrameSize; @@ -1187,18 +1231,24 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO * point (i.e. the caller of the MPU_). We need to restore it * when we exit from the system call. */ pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry = pulTaskStack[ portOFFSET_TO_LR ]; - /* Store the value of the PSPLIM register before the SVC was raised. * We need to restore it when we exit from the system call. */ - __asm volatile ( "mrs %0, psplim" : "=r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) ); + #if ( portUSE_PSPLIM_REGISTER == 1 ) + { + __asm volatile ( "mrs %0, psplim" : "=r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) ); + } + #endif /* Use the pulSystemCallStack in thread mode. */ __asm volatile ( "msr psp, %0" : : "r" ( pulSystemCallStack ) ); - __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) ); + #if ( portUSE_PSPLIM_REGISTER == 1 ) + { + __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) ); + } + #endif /* Start executing the system call upon returning from this handler. */ pulSystemCallStack[ portOFFSET_TO_PC ] = uxSystemCallImplementations[ ucSystemCallNumber ]; - /* Raise a request to exit from the system call upon finishing the * system call. */ pulSystemCallStack[ portOFFSET_TO_LR ] = ( uint32_t ) vRequestSystemCallExit; @@ -1224,14 +1274,13 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO pulSystemCallStack[ portOFFSET_TO_PSR ] &= ( ~portPSR_STACK_PADDING_MASK ); /* Raise the privilege for the duration of the system call. */ - __asm volatile - ( + __asm volatile ( " mrs r0, control \n" /* Obtain current control value. */ " movs r1, #1 \n" /* r1 = 1. */ " bics r0, r1 \n" /* Clear nPRIV bit. */ " msr control, r0 \n" /* Write back new control value. */ ::: "r0", "r1", "memory" - ); + ); } } @@ -1293,12 +1342,11 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO { /* Extended frame i.e. FPU in use. */ ulStackFrameSize = 26; - __asm volatile - ( + __asm volatile ( " vpush {s0} \n" /* Trigger lazy stacking. */ " vpop {s0} \n" /* Nullify the affect of the above instruction. */ ::: "memory" - ); + ); } else { @@ -1310,7 +1358,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO { ulStackFrameSize = 8; } - #endif /* if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */ + #endif /* configENABLE_FPU || configENABLE_MVE */ /* Make space on the task stack for the stack frame. */ pulTaskStack = pulTaskStack - ulStackFrameSize; @@ -1332,7 +1380,11 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO /* Restore the PSPLIM register to what it was at the time of * system call entry. */ - __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) ); + #if ( portUSE_PSPLIM_REGISTER == 1 ) + { + __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) ); + } + #endif /* If the hardware used padding to force the stack pointer * to be double word aligned, set the stacked xPSR bit[9], @@ -1350,14 +1402,13 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO pxMpuSettings->xSystemCallStackInfo.pulTaskStack = NULL; /* Drop the privilege before returning to the thread mode. */ - __asm volatile - ( + __asm volatile ( " mrs r0, control \n" /* Obtain current control value. */ " movs r1, #1 \n" /* r1 = 1. */ " orrs r0, r1 \n" /* Set nPRIV bit. */ " msr control, r0 \n" /* Write back new control value. */ ::: "r0", "r1", "memory" - ); + ); } } @@ -1410,21 +1461,21 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO xMPUSettings->ulContext[ ulIndex ] = 0x11111111; /* r11. */ ulIndex++; - xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pvParameters; /* r0. */ + xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pvParameters; /* r0. */ ulIndex++; - xMPUSettings->ulContext[ ulIndex ] = 0x01010101; /* r1. */ + xMPUSettings->ulContext[ ulIndex ] = 0x01010101; /* r1. */ ulIndex++; - xMPUSettings->ulContext[ ulIndex ] = 0x02020202; /* r2. */ + xMPUSettings->ulContext[ ulIndex ] = 0x02020202; /* r2. */ ulIndex++; - xMPUSettings->ulContext[ ulIndex ] = 0x03030303; /* r3. */ + xMPUSettings->ulContext[ ulIndex ] = 0x03030303; /* r3. */ ulIndex++; - xMPUSettings->ulContext[ ulIndex ] = 0x12121212; /* r12. */ + xMPUSettings->ulContext[ ulIndex ] = 0x12121212; /* r12. */ ulIndex++; xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portTASK_RETURN_ADDRESS; /* LR. */ ulIndex++; - xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxCode; /* PC. */ + xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxCode; /* PC. */ ulIndex++; - xMPUSettings->ulContext[ ulIndex ] = portINITIAL_XPSR; /* xPSR. */ + xMPUSettings->ulContext[ ulIndex ] = portINITIAL_XPSR; /* xPSR. */ ulIndex++; #if ( configENABLE_TRUSTZONE == 1 ) @@ -1435,8 +1486,9 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO #endif /* configENABLE_TRUSTZONE */ xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) ( pxTopOfStack - 8 ); /* PSP with the hardware saved stack. */ ulIndex++; - xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxEndOfStack; /* PSPLIM. */ + xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxEndOfStack; /* PSPLIM. */ ulIndex++; + if( xRunPrivileged == pdTRUE ) { xMPUSettings->ulTaskFlags |= portTASK_IS_PRIVILEGED_FLAG; @@ -1449,6 +1501,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portINITIAL_CONTROL_UNPRIVILEGED; /* CONTROL. */ ulIndex++; } + xMPUSettings->ulContext[ ulIndex ] = portINITIAL_EXC_RETURN; /* LR (EXC_RETURN). */ ulIndex++; @@ -1483,7 +1536,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO * interrupt. */ #if ( portPRELOAD_REGISTERS == 0 ) { - pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */ + pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */ *pxTopOfStack = portINITIAL_XPSR; /* xPSR. */ pxTopOfStack--; *pxTopOfStack = ( StackType_t ) pxCode; /* PC. */ @@ -1505,7 +1558,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO } #else /* portPRELOAD_REGISTERS */ { - pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */ + pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */ *pxTopOfStack = portINITIAL_XPSR; /* xPSR. */ pxTopOfStack--; *pxTopOfStack = ( StackType_t ) pxCode; /* PC. */ @@ -1540,7 +1593,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO pxTopOfStack--; *pxTopOfStack = portINITIAL_EXC_RETURN; /* EXC_RETURN. */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */ + *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */ #if ( configENABLE_TRUSTZONE == 1 ) { @@ -1559,22 +1612,52 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */ { - #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) ) + /* An application can install FreeRTOS interrupt handlers in one of the + * folllowing ways: + * 1. Direct Routing - Install the functions SVC_Handler and PendSV_Handler + * for SVCall and PendSV interrupts respectively. + * 2. Indirect Routing - Install separate handlers for SVCall and PendSV + * interrupts and route program control from those handlers to + * SVC_Handler and PendSV_Handler functions. + * + * Applications that use Indirect Routing must set + * configCHECK_HANDLER_INSTALLATION to 0 in their FreeRTOSConfig.h. Direct + * routing, which is validated here when configCHECK_HANDLER_INSTALLATION + * is 1, should be preferred when possible. */ + #if ( configCHECK_HANDLER_INSTALLATION == 1 ) + { + const portISR_t * const pxVectorTable = portSCB_VTOR_REG; + + /* Validate that the application has correctly installed the FreeRTOS + * handlers for SVCall and PendSV interrupts. We do not check the + * installation of the SysTick handler because the application may + * choose to drive the RTOS tick using a timer other than the SysTick + * timer by overriding the weak function vPortSetupTimerInterrupt(). + * + * Assertion failures here indicate incorrect installation of the + * FreeRTOS handlers. For help installing the FreeRTOS handlers, see + * https://www.FreeRTOS.org/FAQHelp.html. + * + * Systems with a configurable address for the interrupt vector table + * can also encounter assertion failures or even system faults here if + * VTOR is not set correctly to point to the application's vector table. */ + configASSERT( pxVectorTable[ portVECTOR_INDEX_SVC ] == SVC_Handler ); + configASSERT( pxVectorTable[ portVECTOR_INDEX_PENDSV ] == PendSV_Handler ); + } + #endif /* configCHECK_HANDLER_INSTALLATION */ + + #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) { - volatile uint32_t ulOriginalPriority; volatile uint32_t ulImplementedPrioBits = 0; volatile uint8_t ucMaxPriorityValue; /* Determine the maximum priority from which ISR safe FreeRTOS API - * functions can be called. ISR safe functions are those that end in - * "FromISR". FreeRTOS maintains separate thread and ISR API functions to + * functions can be called. ISR safe functions are those that end in + * "FromISR". FreeRTOS maintains separate thread and ISR API functions to * ensure interrupt entry is as fast and simple as possible. * - * Save the interrupt priority value that is about to be clobbered. */ - ulOriginalPriority = portNVIC_SHPR2_REG; - - /* Determine the number of priority bits available. First write to all - * possible bits. */ + * First, determine the number of priority bits available. Write to all + * possible bits in the priority setting for SVCall. */ portNVIC_SHPR2_REG = 0xFF000000; /* Read the value back to see how many bits stuck. */ @@ -1593,11 +1676,10 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */ /* Check that the bits not implemented in hardware are zero in * configMAX_SYSCALL_INTERRUPT_PRIORITY. */ - configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( ~ucMaxPriorityValue ) ) == 0U ); + configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( uint8_t ) ( ~( uint32_t ) ucMaxPriorityValue ) ) == 0U ); /* Calculate the maximum acceptable priority group value for the number * of bits read back. */ - while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE ) { ulImplementedPrioBits++; @@ -1635,16 +1717,14 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */ * register. */ ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT; ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK; - - /* Restore the clobbered interrupt priority register to its original - * value. */ - portNVIC_SHPR2_REG = ulOriginalPriority; } - #endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) ) */ + #endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */ - /* Make PendSV, CallSV and SysTick the same priority as the kernel. */ + /* Make PendSV and SysTick the lowest priority interrupts, and make SVCall + * the highest priority. */ portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI; portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI; + portNVIC_SHPR2_REG = 0; #if ( configENABLE_MPU == 1 ) { @@ -1701,6 +1781,7 @@ void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */ int32_t lIndex = 0; #if defined( __ARMCC_VERSION ) + /* Declaration when these variable are defined in code instead of being * exported from linker scripts. */ extern uint32_t * __privileged_sram_start__; @@ -1886,7 +1967,7 @@ BaseType_t xPortIsInsideInterrupt( void ) } /*-----------------------------------------------------------*/ -#if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) ) +#if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) void vPortValidateInterruptPriority( void ) { @@ -1944,7 +2025,7 @@ BaseType_t xPortIsInsideInterrupt( void ) configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue ); } -#endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) ) */ +#endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */ /*-----------------------------------------------------------*/ #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) diff --git a/Source/portable/GCC/ARM_CM35P_NTZ/non_secure/portasm.c b/Source/portable/GCC/ARM_CM35P_NTZ/non_secure/portasm.c index b3f6a0aac..6169b9358 100644 --- a/Source/portable/GCC/ARM_CM35P_NTZ/non_secure/portasm.c +++ b/Source/portable/GCC/ARM_CM35P_NTZ/non_secure/portasm.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -75,16 +75,16 @@ " ldmia r0!, {r4-r11} \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */ " stmia r2, {r4-r11} \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */ " \n" - #if ( configTOTAL_MPU_REGIONS == 16 ) - " movs r3, #8 \n" /* r3 = 8. */ - " str r3, [r1] \n" /* Program RNR = 8. */ - " ldmia r0!, {r4-r11} \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */ - " stmia r2, {r4-r11} \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */ - " movs r3, #12 \n" /* r3 = 12. */ - " str r3, [r1] \n" /* Program RNR = 12. */ - " ldmia r0!, {r4-r11} \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */ - " stmia r2, {r4-r11} \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */ - #endif /* configTOTAL_MPU_REGIONS == 16 */ + #if ( configTOTAL_MPU_REGIONS == 16 ) + " movs r3, #8 \n" /* r3 = 8. */ + " str r3, [r1] \n" /* Program RNR = 8. */ + " ldmia r0!, {r4-r11} \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */ + " stmia r2, {r4-r11} \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */ + " movs r3, #12 \n" /* r3 = 12. */ + " str r3, [r1] \n" /* Program RNR = 12. */ + " ldmia r0!, {r4-r11} \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */ + " stmia r2, {r4-r11} \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */ + #endif /* configTOTAL_MPU_REGIONS == 16 */ " \n" " ldr r1, xMPUCTRLConst2 \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */ " ldr r2, [r1] \n" /* Read the value of MPU_CTRL. */ @@ -273,15 +273,15 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att " mrs r2, psp \n" /* r2 = PSP. */ " \n" " save_general_regs: \n" - #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) - " add r2, r2, #0x20 \n" /* Move r2 to location where s0 is saved. */ - " tst lr, #0x10 \n" - " ittt eq \n" - " vstmiaeq r1!, {s16-s31} \n" /* Store s16-s31. */ - " vldmiaeq r2, {s0-s16} \n" /* Copy hardware saved FP context into s0-s16. */ - " vstmiaeq r1!, {s0-s16} \n" /* Store hardware saved FP context. */ - " sub r2, r2, #0x20 \n" /* Set r2 back to the location of hardware saved context. */ - #endif /* configENABLE_FPU || configENABLE_MVE */ + #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) + " add r2, r2, #0x20 \n" /* Move r2 to location where s0 is saved. */ + " tst lr, #0x10 \n" + " ittt eq \n" + " vstmiaeq r1!, {s16-s31} \n" /* Store s16-s31. */ + " vldmiaeq r2, {s0-s16} \n" /* Copy hardware saved FP context into s0-s16. */ + " vstmiaeq r1!, {s0-s16} \n" /* Store hardware saved FP context. */ + " sub r2, r2, #0x20 \n" /* Set r2 back to the location of hardware saved context. */ + #endif /* configENABLE_FPU || configENABLE_MVE */ " \n" " stmia r1!, {r4-r11} \n" /* Store r4-r11. */ " ldmia r2, {r4-r11} \n" /* Copy the hardware saved context into r4-r11. */ @@ -326,16 +326,16 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att " ldmia r0!, {r4-r11} \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */ " stmia r2, {r4-r11} \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */ " \n" - #if ( configTOTAL_MPU_REGIONS == 16 ) - " movs r3, #8 \n" /* r3 = 8. */ - " str r3, [r1] \n" /* Program RNR = 8. */ - " ldmia r0!, {r4-r11} \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */ - " stmia r2, {r4-r11} \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */ - " movs r3, #12 \n" /* r3 = 12. */ - " str r3, [r1] \n" /* Program RNR = 12. */ - " ldmia r0!, {r4-r11} \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */ - " stmia r2, {r4-r11} \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */ - #endif /* configTOTAL_MPU_REGIONS == 16 */ + #if ( configTOTAL_MPU_REGIONS == 16 ) + " movs r3, #8 \n" /* r3 = 8. */ + " str r3, [r1] \n" /* Program RNR = 8. */ + " ldmia r0!, {r4-r11} \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */ + " stmia r2, {r4-r11} \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */ + " movs r3, #12 \n" /* r3 = 12. */ + " str r3, [r1] \n" /* Program RNR = 12. */ + " ldmia r0!, {r4-r11} \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */ + " stmia r2, {r4-r11} \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */ + #endif /* configTOTAL_MPU_REGIONS == 16 */ " \n" " ldr r1, xMPUCTRLConst \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */ " ldr r2, [r1] \n" /* Read the value of MPU_CTRL. */ @@ -358,13 +358,13 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att " ldmdb r1!, {r4-r11} \n" /* r4-r11 contain hardware saved context. */ " stmia r2!, {r4-r11} \n" /* Copy the hardware saved context on the task stack. */ " ldmdb r1!, {r4-r11} \n" /* r4-r11 restored. */ - #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) - " tst lr, #0x10 \n" - " ittt eq \n" - " vldmdbeq r1!, {s0-s16} \n" /* s0-s16 contain hardware saved FP context. */ - " vstmiaeq r2!, {s0-s16} \n" /* Copy hardware saved FP context on the task stack. */ - " vldmdbeq r1!, {s16-s31} \n" /* Restore s16-s31. */ - #endif /* configENABLE_FPU || configENABLE_MVE */ + #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) + " tst lr, #0x10 \n" + " ittt eq \n" + " vldmdbeq r1!, {s0-s16} \n" /* s0-s16 contain hardware saved FP context. */ + " vstmiaeq r2!, {s0-s16} \n" /* Copy hardware saved FP context on the task stack. */ + " vldmdbeq r1!, {s16-s31} \n" /* Restore s16-s31. */ + #endif /* configENABLE_FPU || configENABLE_MVE */ " \n" " restore_context_done: \n" " str r1, [r0] \n" /* Save the location where the context should be saved next as the first member of TCB. */ @@ -390,11 +390,11 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att " \n" " mrs r0, psp \n" /* Read PSP in r0. */ " \n" - #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) - " tst lr, #0x10 \n" /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */ - " it eq \n" - " vstmdbeq r0!, {s16-s31} \n" /* Store the additional FP context registers which are not saved automatically. */ - #endif /* configENABLE_FPU || configENABLE_MVE */ + #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) + " tst lr, #0x10 \n" /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */ + " it eq \n" + " vstmdbeq r0!, {s16-s31} \n" /* Store the additional FP context registers which are not saved automatically. */ + #endif /* configENABLE_FPU || configENABLE_MVE */ " \n" " mrs r2, psplim \n" /* r2 = PSPLIM. */ " mov r3, lr \n" /* r3 = LR/EXC_RETURN. */ @@ -418,11 +418,11 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att " \n" " ldmia r0!, {r2-r11} \n" /* Read from stack - r2 = PSPLIM, r3 = LR and r4-r11 restored. */ " \n" - #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) - " tst r3, #0x10 \n" /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */ - " it eq \n" - " vldmiaeq r0!, {s16-s31} \n" /* Restore the additional FP context registers which are not restored automatically. */ - #endif /* configENABLE_FPU || configENABLE_MVE */ + #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) + " tst r3, #0x10 \n" /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */ + " it eq \n" + " vldmiaeq r0!, {s16-s31} \n" /* Restore the additional FP context registers which are not restored automatically. */ + #endif /* configENABLE_FPU || configENABLE_MVE */ " \n" " msr psplim, r2 \n" /* Restore the PSPLIM register value for the task. */ " msr psp, r0 \n" /* Remember the new top of stack for the task. */ diff --git a/Source/portable/GCC/ARM_CM35P_NTZ/non_secure/portasm.h b/Source/portable/GCC/ARM_CM35P_NTZ/non_secure/portasm.h index f64ceb525..c6d2ebd58 100644 --- a/Source/portable/GCC/ARM_CM35P_NTZ/non_secure/portasm.h +++ b/Source/portable/GCC/ARM_CM35P_NTZ/non_secure/portasm.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/Source/portable/GCC/ARM_CM35P_NTZ/non_secure/portmacro.h b/Source/portable/GCC/ARM_CM35P_NTZ/non_secure/portmacro.h index 557b542eb..ea29ac207 100644 --- a/Source/portable/GCC/ARM_CM35P_NTZ/non_secure/portmacro.h +++ b/Source/portable/GCC/ARM_CM35P_NTZ/non_secure/portmacro.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -48,9 +48,9 @@ /** * Architecture specifics. */ -#define portARCH_NAME "Cortex-M35P" -#define portHAS_BASEPRI 1 -#define portDONT_DISCARD __attribute__( ( used ) ) +#define portARCH_NAME "Cortex-M35P" +#define portHAS_ARMV8M_MAIN_EXTENSION 1 +#define portDONT_DISCARD __attribute__( ( used ) ) /*-----------------------------------------------------------*/ /* ARMv8-M common port configurations. */ @@ -60,8 +60,8 @@ /** * @brief Critical section management. */ -#define portDISABLE_INTERRUPTS() ulSetInterruptMask() -#define portENABLE_INTERRUPTS() vClearInterruptMask( 0 ) +#define portDISABLE_INTERRUPTS() ulSetInterruptMask() +#define portENABLE_INTERRUPTS() vClearInterruptMask( 0 ) /*-----------------------------------------------------------*/ /* *INDENT-OFF* */ diff --git a/Source/portable/GCC/ARM_CM35P_NTZ/non_secure/portmacrocommon.h b/Source/portable/GCC/ARM_CM35P_NTZ/non_secure/portmacrocommon.h index 6f666da22..33f21d85b 100644 --- a/Source/portable/GCC/ARM_CM35P_NTZ/non_secure/portmacrocommon.h +++ b/Source/portable/GCC/ARM_CM35P_NTZ/non_secure/portmacrocommon.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -117,7 +117,7 @@ extern uint32_t ulSetInterruptMask( void ) /* __attribute__(( naked )) PRIVILEGE extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */; #if ( configENABLE_TRUSTZONE == 1 ) - extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize ); /* __attribute__ (( naked )) */ + extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize ); /* __attribute__ (( naked )) */ extern void vPortFreeSecureContext( uint32_t * pulTCB ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */; #endif /* configENABLE_TRUSTZONE */ @@ -188,13 +188,13 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P #if ( configENABLE_MPU == 1 ) - /** - * @brief Settings to define an MPU region. - */ +/** + * @brief Settings to define an MPU region. + */ typedef struct MPURegionSettings { - uint32_t ulRBAR; /**< RBAR for the region. */ - uint32_t ulRLAR; /**< RLAR for the region. */ + uint32_t ulRBAR; /**< RBAR for the region. */ + uint32_t ulRLAR; /**< RLAR for the region. */ } MPURegionSettings_t; #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) @@ -203,9 +203,9 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P #error configSYSTEM_CALL_STACK_SIZE must be defined to the desired size of the system call stack in words for using MPU wrappers v2. #endif - /** - * @brief System call stack. - */ +/** + * @brief System call stack. + */ typedef struct SYSTEM_CALL_STACK_INFO { uint32_t ulSystemCallStackBuffer[ configSYSTEM_CALL_STACK_SIZE ]; @@ -218,74 +218,74 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P #endif /* configUSE_MPU_WRAPPERS_V1 == 0 */ - /** - * @brief MPU settings as stored in the TCB. - */ +/** + * @brief MPU settings as stored in the TCB. + */ #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) - #if( configENABLE_TRUSTZONE == 1 ) + #if ( configENABLE_TRUSTZONE == 1 ) - /* - * +-----------+---------------+----------+-----------------+------------------------------+-----+ - * | s16-s31 | s0-s15, FPSCR | r4-r11 | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, | | - * | | | | PC, xPSR | CONTROL, EXC_RETURN | | - * +-----------+---------------+----------+-----------------+------------------------------+-----+ - * - * <-----------><--------------><---------><----------------><-----------------------------><----> - * 16 16 8 8 5 1 - */ - #define MAX_CONTEXT_SIZE 54 +/* + * +-----------+---------------+----------+-----------------+------------------------------+-----+ + * | s16-s31 | s0-s15, FPSCR | r4-r11 | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, | | + * | | | | PC, xPSR | CONTROL, EXC_RETURN | | + * +-----------+---------------+----------+-----------------+------------------------------+-----+ + * + * <-----------><--------------><---------><----------------><-----------------------------><----> + * 16 16 8 8 5 1 + */ + #define MAX_CONTEXT_SIZE 54 #else /* #if( configENABLE_TRUSTZONE == 1 ) */ - /* - * +-----------+---------------+----------+-----------------+----------------------+-----+ - * | s16-s31 | s0-s15, FPSCR | r4-r11 | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL | | - * | | | | PC, xPSR | EXC_RETURN | | - * +-----------+---------------+----------+-----------------+----------------------+-----+ - * - * <-----------><--------------><---------><----------------><---------------------><----> - * 16 16 8 8 4 1 - */ - #define MAX_CONTEXT_SIZE 53 +/* + * +-----------+---------------+----------+-----------------+----------------------+-----+ + * | s16-s31 | s0-s15, FPSCR | r4-r11 | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL | | + * | | | | PC, xPSR | EXC_RETURN | | + * +-----------+---------------+----------+-----------------+----------------------+-----+ + * + * <-----------><--------------><---------><----------------><---------------------><----> + * 16 16 8 8 4 1 + */ + #define MAX_CONTEXT_SIZE 53 #endif /* #if( configENABLE_TRUSTZONE == 1 ) */ #else /* #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */ - #if( configENABLE_TRUSTZONE == 1 ) + #if ( configENABLE_TRUSTZONE == 1 ) - /* - * +----------+-----------------+------------------------------+-----+ - * | r4-r11 | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, | | - * | | PC, xPSR | CONTROL, EXC_RETURN | | - * +----------+-----------------+------------------------------+-----+ - * - * <---------><----------------><------------------------------><----> - * 8 8 5 1 - */ - #define MAX_CONTEXT_SIZE 22 +/* + * +----------+-----------------+------------------------------+-----+ + * | r4-r11 | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, | | + * | | PC, xPSR | CONTROL, EXC_RETURN | | + * +----------+-----------------+------------------------------+-----+ + * + * <---------><----------------><------------------------------><----> + * 8 8 5 1 + */ + #define MAX_CONTEXT_SIZE 22 #else /* #if( configENABLE_TRUSTZONE == 1 ) */ - /* - * +----------+-----------------+----------------------+-----+ - * | r4-r11 | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL | | - * | | PC, xPSR | EXC_RETURN | | - * +----------+-----------------+----------------------+-----+ - * - * <---------><----------------><----------------------><----> - * 8 8 4 1 - */ - #define MAX_CONTEXT_SIZE 21 +/* + * +----------+-----------------+----------------------+-----+ + * | r4-r11 | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL | | + * | | PC, xPSR | EXC_RETURN | | + * +----------+-----------------+----------------------+-----+ + * + * <---------><----------------><----------------------><----> + * 8 8 4 1 + */ + #define MAX_CONTEXT_SIZE 21 #endif /* #if( configENABLE_TRUSTZONE == 1 ) */ #endif /* #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */ - /* Flags used for xMPU_SETTINGS.ulTaskFlags member. */ - #define portSTACK_FRAME_HAS_PADDING_FLAG ( 1UL << 0UL ) - #define portTASK_IS_PRIVILEGED_FLAG ( 1UL << 1UL ) +/* Flags used for xMPU_SETTINGS.ulTaskFlags member. */ + #define portSTACK_FRAME_HAS_PADDING_FLAG ( 1UL << 0UL ) + #define portTASK_IS_PRIVILEGED_FLAG ( 1UL << 1UL ) /* Size of an Access Control List (ACL) entry in bits. */ #define portACL_ENTRY_SIZE_BITS ( 32U ) @@ -313,7 +313,7 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P * system calls. */ #ifdef configASSERT - #if ( portHAS_BASEPRI == 1 ) + #if ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) void vPortValidateInterruptPriority( void ); #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() vPortValidateInterruptPriority() #endif @@ -333,12 +333,29 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P /** * @brief Scheduler utilities. */ -#define portYIELD() vPortYield() +#if ( configENABLE_MPU == 1 ) + #define portYIELD() __asm volatile ( "svc %0" ::"i" ( portSVC_YIELD ) : "memory" ) + #define portYIELD_WITHIN_API() vPortYield() +#else + #define portYIELD() vPortYield() + #define portYIELD_WITHIN_API() vPortYield() +#endif + #define portNVIC_INT_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed04 ) ) #define portNVIC_PENDSVSET_BIT ( 1UL << 28UL ) -#define portEND_SWITCHING_ISR( xSwitchRequired ) \ - do { if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; } \ - while( 0 ) +#define portEND_SWITCHING_ISR( xSwitchRequired ) \ + do \ + { \ + if( xSwitchRequired ) \ + { \ + traceISR_EXIT_TO_SCHEDULER(); \ + portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; \ + } \ + else \ + { \ + traceISR_EXIT(); \ + } \ + } while( 0 ) #define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x ) /*-----------------------------------------------------------*/ @@ -424,12 +441,12 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P extern BaseType_t xPortIsTaskPrivileged( void ); - /** - * @brief Checks whether or not the calling task is privileged. - * - * @return pdTRUE if the calling task is privileged, pdFALSE otherwise. - */ - #define portIS_TASK_PRIVILEGED() xPortIsTaskPrivileged() +/** + * @brief Checks whether or not the calling task is privileged. + * + * @return pdTRUE if the calling task is privileged, pdFALSE otherwise. + */ + #define portIS_TASK_PRIVILEGED() xPortIsTaskPrivileged() #endif /* configENABLE_MPU == 1 */ /*-----------------------------------------------------------*/ @@ -440,6 +457,56 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P #define portMEMORY_BARRIER() __asm volatile ( "" ::: "memory" ) /*-----------------------------------------------------------*/ +/* Select correct value of configUSE_PORT_OPTIMISED_TASK_SELECTION + * based on whether or not Mainline extension is implemented. */ +#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION + #if ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) + #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1 + #else + #define configUSE_PORT_OPTIMISED_TASK_SELECTION 0 + #endif +#endif /* #ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION */ + +/** + * @brief Port-optimised task selection. + */ +#if ( configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 ) + +/** + * @brief Count the number of leading zeros in a 32-bit value. + */ + static portFORCE_INLINE uint32_t ulPortCountLeadingZeros( uint32_t ulBitmap ) + { + uint32_t ulReturn; + + __asm volatile ( "clz %0, %1" : "=r" ( ulReturn ) : "r" ( ulBitmap ) : "memory" ); + + return ulReturn; + } + +/* Check the configuration. */ + #if ( configMAX_PRIORITIES > 32 ) + #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 different priorities as tasks that share a priority will time slice. + #endif + + #if ( portHAS_ARMV8M_MAIN_EXTENSION == 0 ) + #error ARMv8-M baseline implementations (such as Cortex-M23) do not support port-optimised task selection. Please set configUSE_PORT_OPTIMISED_TASK_SELECTION to 0 or leave it undefined. + #endif + +/** + * @brief Store/clear the ready priorities in a bit map. + */ + #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) ) + #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) ) + +/** + * @brief Get the priority of the highest-priority task that is ready to execute. + */ + #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - ulPortCountLeadingZeros( ( uxReadyPriorities ) ) ) + +#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */ +/*-----------------------------------------------------------*/ + /* *INDENT-OFF* */ #ifdef __cplusplus } diff --git a/Source/portable/GCC/ARM_CM3_MPU/mpu_wrappers_v2_asm.c b/Source/portable/GCC/ARM_CM3_MPU/mpu_wrappers_v2_asm.c index 7aa81666d..6b808ee52 100644 --- a/Source/portable/GCC/ARM_CM3_MPU/mpu_wrappers_v2_asm.c +++ b/Source/portable/GCC/ARM_CM3_MPU/mpu_wrappers_v2_asm.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -365,31 +365,6 @@ } /*-----------------------------------------------------------*/ - char * MPU_pcTaskGetName( TaskHandle_t xTaskToQuery ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; - - char * MPU_pcTaskGetName( TaskHandle_t xTaskToQuery ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ - { - __asm volatile - ( - " .syntax unified \n" - " .extern MPU_pcTaskGetNameImpl \n" - " \n" - " push {r0} \n" - " mrs r0, control \n" - " tst r0, #1 \n" - " bne MPU_pcTaskGetName_Unpriv \n" - " MPU_pcTaskGetName_Priv: \n" - " pop {r0} \n" - " b MPU_pcTaskGetNameImpl \n" - " MPU_pcTaskGetName_Unpriv: \n" - " pop {r0} \n" - " svc %0 \n" - " \n" - : : "i" ( SYSTEM_CALL_pcTaskGetName ) : "memory" - ); - } -/*-----------------------------------------------------------*/ - #if ( configGENERATE_RUN_TIME_STATS == 1 ) configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetRunTimeCounter( const TaskHandle_t xTask ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; @@ -1512,30 +1487,27 @@ #if ( configUSE_TIMERS == 1 ) - BaseType_t MPU_xTimerGenericCommandEntry( const xTimerGenericCommandParams_t * pxParams ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + BaseType_t MPU_xTimerGenericCommandFromTaskEntry( const xTimerGenericCommandFromTaskParams_t * pxParams ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; - BaseType_t MPU_xTimerGenericCommandEntry( const xTimerGenericCommandParams_t * pxParams ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + BaseType_t MPU_xTimerGenericCommandFromTaskEntry( const xTimerGenericCommandFromTaskParams_t * pxParams ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ { __asm volatile ( - " .syntax unified \n" - " .extern MPU_xTimerGenericCommandPrivImpl \n" - " \n" - " push {r0} \n" - " mrs r0, ipsr \n" - " cmp r0, #0 \n" - " bne MPU_xTimerGenericCommand_Priv \n" - " mrs r0, control \n" - " tst r0, #1 \n" - " beq MPU_xTimerGenericCommand_Priv \n" - " MPU_xTimerGenericCommand_Unpriv: \n" - " pop {r0} \n" - " svc %0 \n" - " MPU_xTimerGenericCommand_Priv: \n" - " pop {r0} \n" - " b MPU_xTimerGenericCommandPrivImpl \n" - " \n" - : : "i" ( SYSTEM_CALL_xTimerGenericCommand ) : "memory" + " .syntax unified \n" + " .extern MPU_xTimerGenericCommandFromTaskImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " bne MPU_xTimerGenericCommandFromTask_Unpriv \n" + " MPU_xTimerGenericCommandFromTask_Priv: \n" + " pop {r0} \n" + " b MPU_xTimerGenericCommandFromTaskImpl \n" + " MPU_xTimerGenericCommandFromTask_Unpriv: \n" + " pop {r0} \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xTimerGenericCommandFromTask ) : "memory" ); } diff --git a/Source/portable/GCC/ARM_CM3_MPU/port.c b/Source/portable/GCC/ARM_CM3_MPU/port.c index f99acf5e1..ebd8745bf 100644 --- a/Source/portable/GCC/ARM_CM3_MPU/port.c +++ b/Source/portable/GCC/ARM_CM3_MPU/port.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -58,6 +58,9 @@ #define configALLOW_UNPRIVILEGED_CRITICAL_SECTIONS 1 #endif +/* Prototype of all Interrupt Service Routines (ISRs). */ +typedef void ( * portISR_t )( void ); + /* Constants required to access and manipulate the NVIC. */ #define portNVIC_SYSTICK_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000e010 ) ) #define portNVIC_SYSTICK_LOAD_REG ( *( ( volatile uint32_t * ) 0xe000e014 ) ) @@ -87,7 +90,6 @@ #define portMIN_INTERRUPT_PRIORITY ( 255UL ) #define portNVIC_PENDSV_PRI ( ( ( uint32_t ) portMIN_INTERRUPT_PRIORITY ) << 16UL ) #define portNVIC_SYSTICK_PRI ( ( ( uint32_t ) portMIN_INTERRUPT_PRIORITY ) << 24UL ) -#define portNVIC_SVC_PRI ( ( ( uint32_t ) configMAX_SYSCALL_INTERRUPT_PRIORITY - 1UL ) << 24UL ) /* Constants required to set up the initial stack. */ #define portINITIAL_XPSR ( 0x01000000 ) @@ -95,6 +97,11 @@ #define portINITIAL_CONTROL_IF_UNPRIVILEGED ( 0x03 ) #define portINITIAL_CONTROL_IF_PRIVILEGED ( 0x02 ) +/* Constants used to check the installation of the FreeRTOS interrupt handlers. */ +#define portSCB_VTOR_REG ( *( ( portISR_t ** ) 0xE000ED08 ) ) +#define portVECTOR_INDEX_SVC ( 11 ) +#define portVECTOR_INDEX_PENDSV ( 14 ) + /* Constants required to check the validity of an interrupt priority. */ #define portFIRST_USER_INTERRUPT_NUMBER ( 16 ) #define portNVIC_IP_REGISTERS_OFFSET_16 ( 0xE000E3F0 ) @@ -186,6 +193,11 @@ BaseType_t xIsPrivileged( void ) __attribute__( ( naked ) ); */ void vResetPrivilege( void ) __attribute__( ( naked ) ); +/** + * @brief Make a task unprivileged. + */ +void vPortSwitchToUserMode( void ); + /** * @brief Enter critical section. */ @@ -229,12 +241,12 @@ void vResetPrivilege( void ) __attribute__( ( naked ) ); #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) - /** - * @brief Sets up the task stack so that upon returning from - * SVC, the task stack is used again. - * - * @param pulSystemCallStack The current SP when the SVC was raised. - */ +/** + * @brief Sets up the task stack so that upon returning from + * SVC, the task stack is used again. + * + * @param pulSystemCallStack The current SP when the SVC was raised. + */ void vSystemCallExit( uint32_t * pulSystemCallStack ) PRIVILEGED_FUNCTION; #endif /* #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ @@ -289,28 +301,29 @@ StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, } else { - xMPUSettings->ulTaskFlags &= ( ~portTASK_IS_PRIVILEGED_FLAG ); + xMPUSettings->ulTaskFlags &= ( ~( portTASK_IS_PRIVILEGED_FLAG ) ); xMPUSettings->ulContext[ 0 ] = portINITIAL_CONTROL_IF_UNPRIVILEGED; } - xMPUSettings->ulContext[ 1 ] = 0x04040404; /* r4. */ - xMPUSettings->ulContext[ 2 ] = 0x05050505; /* r5. */ - xMPUSettings->ulContext[ 3 ] = 0x06060606; /* r6. */ - xMPUSettings->ulContext[ 4 ] = 0x07070707; /* r7. */ - xMPUSettings->ulContext[ 5 ] = 0x08080808; /* r8. */ - xMPUSettings->ulContext[ 6 ] = 0x09090909; /* r9. */ - xMPUSettings->ulContext[ 7 ] = 0x10101010; /* r10. */ - xMPUSettings->ulContext[ 8 ] = 0x11111111; /* r11. */ - xMPUSettings->ulContext[ 9 ] = portINITIAL_EXC_RETURN; /* EXC_RETURN. */ - - xMPUSettings->ulContext[ 10 ] = ( uint32_t ) ( pxTopOfStack - 8 ); /* PSP with the hardware saved stack. */ - xMPUSettings->ulContext[ 11 ] = ( uint32_t ) pvParameters; /* r0. */ - xMPUSettings->ulContext[ 12 ] = 0x01010101; /* r1. */ - xMPUSettings->ulContext[ 13 ] = 0x02020202; /* r2. */ - xMPUSettings->ulContext[ 14 ] = 0x03030303; /* r3. */ - xMPUSettings->ulContext[ 15 ] = 0x12121212; /* r12. */ - xMPUSettings->ulContext[ 16 ] = 0; /* LR. */ + + xMPUSettings->ulContext[ 1 ] = 0x04040404; /* r4. */ + xMPUSettings->ulContext[ 2 ] = 0x05050505; /* r5. */ + xMPUSettings->ulContext[ 3 ] = 0x06060606; /* r6. */ + xMPUSettings->ulContext[ 4 ] = 0x07070707; /* r7. */ + xMPUSettings->ulContext[ 5 ] = 0x08080808; /* r8. */ + xMPUSettings->ulContext[ 6 ] = 0x09090909; /* r9. */ + xMPUSettings->ulContext[ 7 ] = 0x10101010; /* r10. */ + xMPUSettings->ulContext[ 8 ] = 0x11111111; /* r11. */ + xMPUSettings->ulContext[ 9 ] = portINITIAL_EXC_RETURN; /* EXC_RETURN. */ + + xMPUSettings->ulContext[ 10 ] = ( uint32_t ) ( pxTopOfStack - 8 ); /* PSP with the hardware saved stack. */ + xMPUSettings->ulContext[ 11 ] = ( uint32_t ) pvParameters; /* r0. */ + xMPUSettings->ulContext[ 12 ] = 0x01010101; /* r1. */ + xMPUSettings->ulContext[ 13 ] = 0x02020202; /* r2. */ + xMPUSettings->ulContext[ 14 ] = 0x03030303; /* r3. */ + xMPUSettings->ulContext[ 15 ] = 0x12121212; /* r12. */ + xMPUSettings->ulContext[ 16 ] = 0; /* LR. */ xMPUSettings->ulContext[ 17 ] = ( ( uint32_t ) pxCode ) & portSTART_ADDRESS_MASK; /* PC. */ - xMPUSettings->ulContext[ 18 ] = portINITIAL_XPSR; /* xPSR. */ + xMPUSettings->ulContext[ 18 ] = portINITIAL_XPSR; /* xPSR. */ #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) { @@ -365,13 +378,13 @@ StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, /* Assumes psp was in use. */ __asm volatile ( - #ifndef USE_PROCESS_STACK /* Code should not be required if a main() is using the process stack. */ - " tst lr, #4 \n" - " ite eq \n" - " mrseq r0, msp \n" - " mrsne r0, psp \n" + #ifndef USE_PROCESS_STACK /* Code should not be required if a main() is using the process stack. */ + " tst lr, #4 \n" + " ite eq \n" + " mrseq r0, msp \n" + " mrsne r0, psp \n" #else - " mrs r0, psp \n" + " mrs r0, psp \n" #endif " b %0 \n" ::"i" ( vSVCHandler_C ) : "r0", "memory" @@ -388,6 +401,7 @@ void vSVCHandler_C( uint32_t * pulParam ) /* PRIVILEGED_FUNCTION */ #if ( ( configUSE_MPU_WRAPPERS_V1 == 1 ) && ( configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY == 1 ) ) #if defined( __ARMCC_VERSION ) + /* Declaration when these variable are defined in code instead of being * exported from linker scripts. */ extern uint32_t * __syscalls_flash_start__; @@ -407,7 +421,6 @@ void vSVCHandler_C( uint32_t * pulParam ) /* PRIVILEGED_FUNCTION */ switch( ucSVCNumber ) { case portSVC_START_SCHEDULER: - portNVIC_SHPR2_REG |= portNVIC_SVC_PRI; prvRestoreContextOfFirstTask(); break; @@ -519,13 +532,12 @@ void vSVCHandler_C( uint32_t * pulParam ) /* PRIVILEGED_FUNCTION */ __asm volatile ( "msr psp, %0" : : "r" ( pulSystemCallStack ) ); /* Raise the privilege for the duration of the system call. */ - __asm volatile - ( + __asm volatile ( " mrs r1, control \n" /* Obtain current control value. */ " bic r1, #1 \n" /* Clear nPRIV bit. */ " msr control, r1 \n" /* Write back new control value. */ ::: "r1", "memory" - ); + ); /* Remember the location where we should copy the stack frame when we exit from * the system call. */ @@ -539,7 +551,6 @@ void vSVCHandler_C( uint32_t * pulParam ) /* PRIVILEGED_FUNCTION */ /* Start executing the system call upon returning from this handler. */ pulSystemCallStack[ portOFFSET_TO_PC ] = uxSystemCallImplementations[ ucSystemCallNumber ]; - /* Raise a request to exit from the system call upon finishing the * system call. */ pulSystemCallStack[ portOFFSET_TO_LR ] = ( uint32_t ) vRequestSystemCallExit; @@ -627,13 +638,12 @@ void vSVCHandler_C( uint32_t * pulParam ) /* PRIVILEGED_FUNCTION */ __asm volatile ( "msr psp, %0" : : "r" ( pulTaskStack ) ); /* Drop the privilege before returning to the thread mode. */ - __asm volatile - ( + __asm volatile ( " mrs r1, control \n" /* Obtain current control value. */ " orr r1, #1 \n" /* Set nPRIV bit. */ " msr control, r1 \n" /* Write back new control value. */ ::: "r1", "memory" - ); + ); /* Return to the caller of the System Call entry point (i.e. the * caller of the MPU_). */ @@ -696,8 +706,8 @@ static void prvRestoreContextOfFirstTask( void ) " str r3, [r0] \n" /* Disable MPU. */ " \n" " ldr r0, =0xe000ed9c \n" /* Region Base Address register. */ - " ldmia r2!, {r4-r11} \n" /* Read 4 sets of MPU registers [MPU Region # 4 - 7]. */ - " stmia r0, {r4-r11} \n" /* Write 4 sets of MPU registers [MPU Region # 4 - 7]. */ + " ldmia r2!, {r4-r11} \n" /* Read 4 sets of MPU registers [MPU Region # 0 - 3]. */ + " stmia r0, {r4-r11} \n" /* Write 4 sets of MPU registers [MPU Region # 0 - 3]. */ " \n" " ldr r0, =0xe000ed94 \n" /* MPU_CTRL register. */ " ldr r3, [r0] \n" /* Read the value of MPU_CTRL. */ @@ -733,6 +743,40 @@ static void prvRestoreContextOfFirstTask( void ) */ BaseType_t xPortStartScheduler( void ) { + /* An application can install FreeRTOS interrupt handlers in one of the + * folllowing ways: + * 1. Direct Routing - Install the functions vPortSVCHandler and + * xPortPendSVHandler for SVCall and PendSV interrupts respectively. + * 2. Indirect Routing - Install separate handlers for SVCall and PendSV + * interrupts and route program control from those handlers to + * vPortSVCHandler and xPortPendSVHandler functions. + * + * Applications that use Indirect Routing must set + * configCHECK_HANDLER_INSTALLATION to 0 in their FreeRTOSConfig.h. Direct + * routing, which is validated here when configCHECK_HANDLER_INSTALLATION + * is 1, should be preferred when possible. */ + #if ( configCHECK_HANDLER_INSTALLATION == 1 ) + { + const portISR_t * const pxVectorTable = portSCB_VTOR_REG; + + /* Validate that the application has correctly installed the FreeRTOS + * handlers for SVCall and PendSV interrupts. We do not check the + * installation of the SysTick handler because the application may + * choose to drive the RTOS tick using a timer other than the SysTick + * timer by overriding the weak function vPortSetupTimerInterrupt(). + * + * Assertion failures here indicate incorrect installation of the + * FreeRTOS handlers. For help installing the FreeRTOS handlers, see + * https://www.FreeRTOS.org/FAQHelp.html. + * + * Systems with a configurable address for the interrupt vector table + * can also encounter assertion failures or even system faults here if + * VTOR is not set correctly to point to the application's vector table. */ + configASSERT( pxVectorTable[ portVECTOR_INDEX_SVC ] == vPortSVCHandler ); + configASSERT( pxVectorTable[ portVECTOR_INDEX_PENDSV ] == xPortPendSVHandler ); + } + #endif /* configCHECK_HANDLER_INSTALLATION */ + #if ( configASSERT_DEFINED == 1 ) { volatile uint8_t ucOriginalPriority; @@ -817,11 +861,12 @@ BaseType_t xPortStartScheduler( void ) } #endif /* configASSERT_DEFINED */ - /* Make PendSV and SysTick the same priority as the kernel, and the SVC - * handler higher priority so it can be used to exit a critical section (where - * lower priorities are masked). */ + /* Make PendSV and SysTick the lowest priority interrupts, and make SVCall + * the highest priority. */ portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI; portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI; + portNVIC_SHPR2_REG = 0; + /* Configure the regions in the MPU that are common to all tasks. */ prvSetupMPU(); @@ -840,8 +885,7 @@ BaseType_t xPortStartScheduler( void ) #endif /* Start the first task. */ - __asm volatile - ( + __asm volatile ( " ldr r0, =0xE000ED08 \n" /* Use the NVIC offset register to locate the stack. */ " ldr r0, [r0] \n" " ldr r0, [r0] \n" @@ -853,8 +897,7 @@ BaseType_t xPortStartScheduler( void ) " svc %0 \n" /* System call to start first task. */ " nop \n" " .ltorg \n" - ::"i" ( portSVC_START_SCHEDULER ) : "memory" - ); + ::"i" ( portSVC_START_SCHEDULER ) : "memory" ); /* Should not get here! */ return 0; @@ -980,8 +1023,8 @@ void xPortPendSVHandler( void ) " str r3, [r0] \n" /* Disable MPU. */ " \n" " ldr r0, =0xe000ed9c \n" /* Region Base Address register. */ - " ldmia r2!, {r4-r11} \n" /* Read 4 sets of MPU registers [MPU Region # 4 - 7]. */ - " stmia r0, {r4-r11} \n" /* Write 4 sets of MPU registers [MPU Region # 4 - 7]. */ + " ldmia r2!, {r4-r11} \n" /* Read 4 sets of MPU registers [MPU Region # 0 - 3]. */ + " stmia r0, {r4-r11} \n" /* Write 4 sets of MPU registers [MPU Region # 0 - 3]. */ " \n" " ldr r0, =0xe000ed94 \n" /* MPU_CTRL register. */ " ldr r3, [r0] \n" /* Read the value of MPU_CTRL. */ @@ -1016,13 +1059,19 @@ void xPortSysTickHandler( void ) uint32_t ulDummy; ulDummy = portSET_INTERRUPT_MASK_FROM_ISR(); + traceISR_ENTER(); { /* Increment the RTOS tick. */ if( xTaskIncrementTick() != pdFALSE ) { + traceISR_EXIT_TO_SCHEDULER(); /* Pend a context switch. */ portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; } + else + { + traceISR_EXIT(); + } } portCLEAR_INTERRUPT_MASK_FROM_ISR( ulDummy ); } @@ -1162,6 +1211,19 @@ void vResetPrivilege( void ) /* __attribute__ (( naked )) */ } /*-----------------------------------------------------------*/ +void vPortSwitchToUserMode( void ) +{ + /* Load the current task's MPU settings from its TCB. */ + xMPU_SETTINGS * xTaskMpuSettings = xTaskGetMPUSettings( NULL ); + + /* Mark the task as unprivileged. */ + xTaskMpuSettings->ulTaskFlags &= ( ~( portTASK_IS_PRIVILEGED_FLAG ) ); + + /* Lower the processor's privilege level. */ + vResetPrivilege(); +} +/*-----------------------------------------------------------*/ + void vPortStoreTaskMPUSettings( xMPU_SETTINGS * xMPUSettings, const struct xMEMORY_REGION * const xRegions, StackType_t * pxBottomOfStack, @@ -1180,7 +1242,7 @@ void vPortStoreTaskMPUSettings( xMPU_SETTINGS * xMPUSettings, xMPUSettings->xRegion[ 0 ].ulRegionBaseAddress = ( ( uint32_t ) __SRAM_segment_start__ ) | /* Base address. */ ( portMPU_REGION_VALID ) | - ( portSTACK_REGION ); /* Region number. */ + ( portSTACK_REGION ); /* Region number. */ xMPUSettings->xRegion[ 0 ].ulRegionAttribute = ( portMPU_REGION_READ_WRITE ) | @@ -1376,7 +1438,7 @@ BaseType_t xPortIsAuthorizedToAccessBuffer( const void * pvBuffer, * devices by calling NVIC_SetPriorityGrouping( 0 ); before starting the * scheduler. Note however that some vendor specific peripheral libraries * assume a non-zero priority group setting, in which cases using a value - * of zero will result in unpredicable behaviour. */ + * of zero will result in unpredictable behaviour. */ configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue ); } diff --git a/Source/portable/GCC/ARM_CM3_MPU/portmacro.h b/Source/portable/GCC/ARM_CM3_MPU/portmacro.h index 170a58c77..52bc1054d 100644 --- a/Source/portable/GCC/ARM_CM3_MPU/portmacro.h +++ b/Source/portable/GCC/ARM_CM3_MPU/portmacro.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -47,101 +47,99 @@ */ /* Type definitions. */ - #define portCHAR char - #define portFLOAT float - #define portDOUBLE double - #define portLONG long - #define portSHORT short - #define portSTACK_TYPE uint32_t - #define portBASE_TYPE long - - typedef portSTACK_TYPE StackType_t; - typedef long BaseType_t; - typedef unsigned long UBaseType_t; - - #if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS ) - typedef uint16_t TickType_t; - #define portMAX_DELAY ( TickType_t ) 0xffff - #elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS ) - typedef uint32_t TickType_t; - #define portMAX_DELAY ( TickType_t ) 0xffffffffUL +#define portCHAR char +#define portFLOAT float +#define portDOUBLE double +#define portLONG long +#define portSHORT short +#define portSTACK_TYPE uint32_t +#define portBASE_TYPE long + +typedef portSTACK_TYPE StackType_t; +typedef long BaseType_t; +typedef unsigned long UBaseType_t; + +#if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS ) + typedef uint16_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffff +#elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS ) + typedef uint32_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffffffffUL /* 32-bit tick type on a 32-bit architecture, so reads of the tick count do * not need to be guarded with a critical section. */ - #define portTICK_TYPE_IS_ATOMIC 1 - #else - #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width. - #endif + #define portTICK_TYPE_IS_ATOMIC 1 +#else + #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width. +#endif /*-----------------------------------------------------------*/ /* MPU specific constants. */ - #define portUSING_MPU_WRAPPERS 1 - #define portPRIVILEGE_BIT ( 0x80000000UL ) - - #define portMPU_REGION_READ_WRITE ( 0x03UL << 24UL ) - #define portMPU_REGION_PRIVILEGED_READ_ONLY ( 0x05UL << 24UL ) - #define portMPU_REGION_READ_ONLY ( 0x06UL << 24UL ) - #define portMPU_REGION_PRIVILEGED_READ_WRITE ( 0x01UL << 24UL ) - #define portMPU_REGION_PRIVILEGED_READ_WRITE_UNPRIV_READ_ONLY ( 0x02UL << 24UL ) - #define portMPU_REGION_CACHEABLE_BUFFERABLE ( 0x07UL << 16UL ) - #define portMPU_REGION_EXECUTE_NEVER ( 0x01UL << 28UL ) - - #define portGENERAL_PERIPHERALS_REGION ( 3UL ) - #define portSTACK_REGION ( 4UL ) - #define portUNPRIVILEGED_FLASH_REGION ( 5UL ) - #define portPRIVILEGED_FLASH_REGION ( 6UL ) - #define portPRIVILEGED_RAM_REGION ( 7UL ) - #define portFIRST_CONFIGURABLE_REGION ( 0UL ) - #define portLAST_CONFIGURABLE_REGION ( 2UL ) - #define portNUM_CONFIGURABLE_REGIONS ( ( portLAST_CONFIGURABLE_REGION - portFIRST_CONFIGURABLE_REGION ) + 1 ) - #define portTOTAL_NUM_REGIONS_IN_TCB ( portNUM_CONFIGURABLE_REGIONS + 1 ) /* Plus one to make space for the stack region. */ - - #define portSWITCH_TO_USER_MODE() __asm volatile ( " mrs r0, control \n orr r0, #1 \n msr control, r0 " ::: "r0", "memory" ) - - typedef struct MPU_REGION_REGISTERS - { - uint32_t ulRegionBaseAddress; - uint32_t ulRegionAttribute; - } xMPU_REGION_REGISTERS; +#define portUSING_MPU_WRAPPERS 1 +#define portPRIVILEGE_BIT ( 0x80000000UL ) + +#define portMPU_REGION_READ_WRITE ( 0x03UL << 24UL ) +#define portMPU_REGION_PRIVILEGED_READ_ONLY ( 0x05UL << 24UL ) +#define portMPU_REGION_READ_ONLY ( 0x06UL << 24UL ) +#define portMPU_REGION_PRIVILEGED_READ_WRITE ( 0x01UL << 24UL ) +#define portMPU_REGION_PRIVILEGED_READ_WRITE_UNPRIV_READ_ONLY ( 0x02UL << 24UL ) +#define portMPU_REGION_CACHEABLE_BUFFERABLE ( 0x07UL << 16UL ) +#define portMPU_REGION_EXECUTE_NEVER ( 0x01UL << 28UL ) + +#define portSTACK_REGION ( 3UL ) +#define portGENERAL_PERIPHERALS_REGION ( 4UL ) +#define portUNPRIVILEGED_FLASH_REGION ( 5UL ) +#define portPRIVILEGED_FLASH_REGION ( 6UL ) +#define portPRIVILEGED_RAM_REGION ( 7UL ) +#define portFIRST_CONFIGURABLE_REGION ( 0UL ) +#define portLAST_CONFIGURABLE_REGION ( 2UL ) +#define portNUM_CONFIGURABLE_REGIONS ( ( portLAST_CONFIGURABLE_REGION - portFIRST_CONFIGURABLE_REGION ) + 1 ) +#define portTOTAL_NUM_REGIONS_IN_TCB ( portNUM_CONFIGURABLE_REGIONS + 1 ) /* Plus one to make space for the stack region. */ + +typedef struct MPU_REGION_REGISTERS +{ + uint32_t ulRegionBaseAddress; + uint32_t ulRegionAttribute; +} xMPU_REGION_REGISTERS; + +typedef struct MPU_REGION_SETTINGS +{ + uint32_t ulRegionStartAddress; + uint32_t ulRegionEndAddress; + uint32_t ulRegionPermissions; +} xMPU_REGION_SETTINGS; + +#if ( configUSE_MPU_WRAPPERS_V1 == 0 ) + + #ifndef configSYSTEM_CALL_STACK_SIZE + #error configSYSTEM_CALL_STACK_SIZE must be defined to the desired size of the system call stack in words for using MPU wrappers v2. + #endif - typedef struct MPU_REGION_SETTINGS + typedef struct SYSTEM_CALL_STACK_INFO { - uint32_t ulRegionStartAddress; - uint32_t ulRegionEndAddress; - uint32_t ulRegionPermissions; - } xMPU_REGION_SETTINGS; - - #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) - - #ifndef configSYSTEM_CALL_STACK_SIZE - #error configSYSTEM_CALL_STACK_SIZE must be defined to the desired size of the system call stack in words for using MPU wrappers v2. - #endif + uint32_t ulSystemCallStackBuffer[ configSYSTEM_CALL_STACK_SIZE ]; + uint32_t * pulSystemCallStack; + uint32_t * pulTaskStack; + uint32_t ulLinkRegisterAtSystemCallEntry; + } xSYSTEM_CALL_STACK_INFO; - typedef struct SYSTEM_CALL_STACK_INFO - { - uint32_t ulSystemCallStackBuffer[ configSYSTEM_CALL_STACK_SIZE ]; - uint32_t * pulSystemCallStack; - uint32_t * pulTaskStack; - uint32_t ulLinkRegisterAtSystemCallEntry; - } xSYSTEM_CALL_STACK_INFO; - - #endif /* #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ +#endif /* #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ #define MAX_CONTEXT_SIZE ( 20 ) /* Size of an Access Control List (ACL) entry in bits. */ #define portACL_ENTRY_SIZE_BITS ( 32U ) - /* Flags used for xMPU_SETTINGS.ulTaskFlags member. */ - #define portSTACK_FRAME_HAS_PADDING_FLAG ( 1UL << 0UL ) - #define portTASK_IS_PRIVILEGED_FLAG ( 1UL << 1UL ) +/* Flags used for xMPU_SETTINGS.ulTaskFlags member. */ +#define portSTACK_FRAME_HAS_PADDING_FLAG ( 1UL << 0UL ) +#define portTASK_IS_PRIVILEGED_FLAG ( 1UL << 1UL ) - typedef struct MPU_SETTINGS - { - xMPU_REGION_REGISTERS xRegion[ portTOTAL_NUM_REGIONS_IN_TCB ]; - xMPU_REGION_SETTINGS xRegionSettings[ portTOTAL_NUM_REGIONS_IN_TCB ]; - uint32_t ulContext[ MAX_CONTEXT_SIZE ]; - uint32_t ulTaskFlags; +typedef struct MPU_SETTINGS +{ + xMPU_REGION_REGISTERS xRegion[ portTOTAL_NUM_REGIONS_IN_TCB ]; + xMPU_REGION_SETTINGS xRegionSettings[ portTOTAL_NUM_REGIONS_IN_TCB ]; + uint32_t ulContext[ MAX_CONTEXT_SIZE ]; + uint32_t ulTaskFlags; #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) xSYSTEM_CALL_STACK_INFO xSystemCallStackInfo; @@ -152,10 +150,10 @@ } xMPU_SETTINGS; /* Architecture specifics. */ - #define portSTACK_GROWTH ( -1 ) - #define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) - #define portBYTE_ALIGNMENT 8 - #define portDONT_DISCARD __attribute__( ( used ) ) +#define portSTACK_GROWTH ( -1 ) +#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) +#define portBYTE_ALIGNMENT 8 +#define portDONT_DISCARD __attribute__( ( used ) ) /*-----------------------------------------------------------*/ /* SVC numbers for various services. */ @@ -166,8 +164,8 @@ /* Scheduler utilities. */ - #define portYIELD() __asm volatile ( " SVC %0 \n"::"i" ( portSVC_YIELD ) : "memory" ) - #define portYIELD_WITHIN_API() \ +#define portYIELD() __asm volatile ( " SVC %0 \n" ::"i" ( portSVC_YIELD ) : "memory" ) +#define portYIELD_WITHIN_API() \ { \ /* Set a PendSV to request a context switch. */ \ portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; \ @@ -178,185 +176,206 @@ __asm volatile ( "isb" ); \ } - #define portNVIC_INT_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed04 ) ) - #define portNVIC_PENDSVSET_BIT ( 1UL << 28UL ) - #define portEND_SWITCHING_ISR( xSwitchRequired ) do { if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; } while( 0 ) - #define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x ) +#define portNVIC_INT_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed04 ) ) +#define portNVIC_PENDSVSET_BIT ( 1UL << 28UL ) +#define portEND_SWITCHING_ISR( xSwitchRequired ) \ + do \ + { \ + if( xSwitchRequired ) \ + { \ + traceISR_EXIT_TO_SCHEDULER(); \ + portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; \ + } \ + else \ + { \ + traceISR_EXIT(); \ + } \ + } while( 0 ) +#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x ) /*-----------------------------------------------------------*/ /* Critical section management. */ - extern void vPortEnterCritical( void ); - extern void vPortExitCritical( void ); - #define portSET_INTERRUPT_MASK_FROM_ISR() ulPortRaiseBASEPRI() - #define portCLEAR_INTERRUPT_MASK_FROM_ISR( x ) vPortSetBASEPRI( x ) - #define portDISABLE_INTERRUPTS() vPortRaiseBASEPRI() - #define portENABLE_INTERRUPTS() vPortSetBASEPRI( 0 ) - #define portENTER_CRITICAL() vPortEnterCritical() - #define portEXIT_CRITICAL() vPortExitCritical() +extern void vPortEnterCritical( void ); +extern void vPortExitCritical( void ); +#define portSET_INTERRUPT_MASK_FROM_ISR() ulPortRaiseBASEPRI() +#define portCLEAR_INTERRUPT_MASK_FROM_ISR( x ) vPortSetBASEPRI( x ) +#define portDISABLE_INTERRUPTS() vPortRaiseBASEPRI() +#define portENABLE_INTERRUPTS() vPortSetBASEPRI( 0 ) +#define portENTER_CRITICAL() vPortEnterCritical() +#define portEXIT_CRITICAL() vPortExitCritical() /*-----------------------------------------------------------*/ /* Task function macros as described on the FreeRTOS.org WEB site. These are * not necessary for to use this port. They are defined so the common demo files * (which build with all the ports) will build. */ - #define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters ) - #define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters ) +#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters ) +#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters ) /*-----------------------------------------------------------*/ /* Architecture specific optimisations. */ - #ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION - #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1 - #endif +#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION + #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1 +#endif - #if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 +#if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 /* Generic helper function. */ - __attribute__( ( always_inline ) ) static inline uint8_t ucPortCountLeadingZeros( uint32_t ulBitmap ) - { - uint8_t ucReturn; + __attribute__( ( always_inline ) ) static inline uint8_t ucPortCountLeadingZeros( uint32_t ulBitmap ) + { + uint8_t ucReturn; - __asm volatile ( "clz %0, %1" : "=r" ( ucReturn ) : "r" ( ulBitmap ) : "memory" ); + __asm volatile ( "clz %0, %1" : "=r" ( ucReturn ) : "r" ( ulBitmap ) : "memory" ); - return ucReturn; - } + return ucReturn; + } /* Check the configuration. */ - #if ( configMAX_PRIORITIES > 32 ) - #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice. - #endif + #if ( configMAX_PRIORITIES > 32 ) + #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice. + #endif /* Store/clear the ready priorities in a bit map. */ - #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) ) - #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) ) + #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) ) + #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) ) /*-----------------------------------------------------------*/ - #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - ( uint32_t ) ucPortCountLeadingZeros( ( uxReadyPriorities ) ) ) + #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - ( uint32_t ) ucPortCountLeadingZeros( ( uxReadyPriorities ) ) ) - #endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */ +#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */ /*-----------------------------------------------------------*/ - #ifdef configASSERT - void vPortValidateInterruptPriority( void ); - #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() vPortValidateInterruptPriority() - #endif +#ifdef configASSERT + void vPortValidateInterruptPriority( void ); + #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() vPortValidateInterruptPriority() +#endif /* portNOP() is not required by this port. */ - #define portNOP() +#define portNOP() - #define portINLINE __inline +#define portINLINE __inline - #ifndef portFORCE_INLINE - #define portFORCE_INLINE inline __attribute__( ( always_inline ) ) - #endif +#ifndef portFORCE_INLINE + #define portFORCE_INLINE inline __attribute__( ( always_inline ) ) +#endif /*-----------------------------------------------------------*/ - extern BaseType_t xIsPrivileged( void ); - extern void vResetPrivilege( void ); +extern BaseType_t xIsPrivileged( void ); +extern void vResetPrivilege( void ); +extern void vPortSwitchToUserMode( void ); /** * @brief Checks whether or not the processor is privileged. * * @return 1 if the processor is already privileged, 0 otherwise. */ - #define portIS_PRIVILEGED() xIsPrivileged() +#define portIS_PRIVILEGED() xIsPrivileged() /** * @brief Raise an SVC request to raise privilege. */ - #define portRAISE_PRIVILEGE() __asm volatile ( "svc %0 \n" ::"i" ( portSVC_RAISE_PRIVILEGE ) : "memory" ); +#define portRAISE_PRIVILEGE() __asm volatile ( "svc %0 \n" ::"i" ( portSVC_RAISE_PRIVILEGE ) : "memory" ); /** * @brief Lowers the privilege level by setting the bit 0 of the CONTROL * register. */ - #define portRESET_PRIVILEGE() vResetPrivilege() +#define portRESET_PRIVILEGE() vResetPrivilege() + +/** + * @brief Make a task unprivileged. + * + * It must be called from privileged tasks only. Calling it from unprivileged + * task will result in a memory protection fault. + */ +#define portSWITCH_TO_USER_MODE() vPortSwitchToUserMode() /*-----------------------------------------------------------*/ - extern BaseType_t xPortIsTaskPrivileged( void ); +extern BaseType_t xPortIsTaskPrivileged( void ); /** * @brief Checks whether or not the calling task is privileged. * * @return pdTRUE if the calling task is privileged, pdFALSE otherwise. */ - #define portIS_TASK_PRIVILEGED() xPortIsTaskPrivileged() +#define portIS_TASK_PRIVILEGED() xPortIsTaskPrivileged() /*-----------------------------------------------------------*/ - portFORCE_INLINE static BaseType_t xPortIsInsideInterrupt( void ) +portFORCE_INLINE static BaseType_t xPortIsInsideInterrupt( void ) +{ + uint32_t ulCurrentInterrupt; + BaseType_t xReturn; + + /* Obtain the number of the currently executing interrupt. */ + __asm volatile ( "mrs %0, ipsr" : "=r" ( ulCurrentInterrupt )::"memory" ); + + if( ulCurrentInterrupt == 0 ) { - uint32_t ulCurrentInterrupt; - BaseType_t xReturn; - - /* Obtain the number of the currently executing interrupt. */ - __asm volatile ( "mrs %0, ipsr" : "=r" ( ulCurrentInterrupt )::"memory" ); - - if( ulCurrentInterrupt == 0 ) - { - xReturn = pdFALSE; - } - else - { - xReturn = pdTRUE; - } - - return xReturn; + xReturn = pdFALSE; } + else + { + xReturn = pdTRUE; + } + + return xReturn; +} /*-----------------------------------------------------------*/ - portFORCE_INLINE static void vPortRaiseBASEPRI( void ) - { - uint32_t ulNewBASEPRI; - - __asm volatile - ( - " mov %0, %1 \n"\ - " msr basepri, %0 \n"\ - " isb \n"\ - " dsb \n"\ - : "=r" ( ulNewBASEPRI ) : "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "memory" - ); - } +portFORCE_INLINE static void vPortRaiseBASEPRI( void ) +{ + uint32_t ulNewBASEPRI; + + __asm volatile + ( + " mov %0, %1 \n" \ + " msr basepri, %0 \n" \ + " isb \n" \ + " dsb \n" \ + : "=r" ( ulNewBASEPRI ) : "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "memory" + ); +} /*-----------------------------------------------------------*/ - portFORCE_INLINE static uint32_t ulPortRaiseBASEPRI( void ) - { - uint32_t ulOriginalBASEPRI, ulNewBASEPRI; - - __asm volatile - ( - " mrs %0, basepri \n"\ - " mov %1, %2 \n"\ - " msr basepri, %1 \n"\ - " isb \n"\ - " dsb \n"\ - : "=r" ( ulOriginalBASEPRI ), "=r" ( ulNewBASEPRI ) : "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "memory" - ); - - /* This return will not be reached but is necessary to prevent compiler - * warnings. */ - return ulOriginalBASEPRI; - } +portFORCE_INLINE static uint32_t ulPortRaiseBASEPRI( void ) +{ + uint32_t ulOriginalBASEPRI, ulNewBASEPRI; + + __asm volatile + ( + " mrs %0, basepri \n" \ + " mov %1, %2 \n" \ + " msr basepri, %1 \n" \ + " isb \n" \ + " dsb \n" \ + : "=r" ( ulOriginalBASEPRI ), "=r" ( ulNewBASEPRI ) : "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "memory" + ); + + /* This return will not be reached but is necessary to prevent compiler + * warnings. */ + return ulOriginalBASEPRI; +} /*-----------------------------------------------------------*/ - portFORCE_INLINE static void vPortSetBASEPRI( uint32_t ulNewMaskValue ) - { - __asm volatile - ( - " msr basepri, %0 "::"r" ( ulNewMaskValue ) : "memory" - ); - } +portFORCE_INLINE static void vPortSetBASEPRI( uint32_t ulNewMaskValue ) +{ + __asm volatile + ( + " msr basepri, %0 " ::"r" ( ulNewMaskValue ) : "memory" + ); +} /*-----------------------------------------------------------*/ - #define portMEMORY_BARRIER() __asm volatile ( "" ::: "memory" ) +#define portMEMORY_BARRIER() __asm volatile ( "" ::: "memory" ) - #ifndef configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY - #warning "configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY is not defined. We recommend defining it to 1 in FreeRTOSConfig.h for better security. *www.FreeRTOS.org/FreeRTOS-V10.3.x.html" - #define configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY 0 - #endif +#ifndef configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY + #warning "configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY is not defined. We recommend defining it to 1 in FreeRTOSConfig.h for better security. *www.FreeRTOS.org/FreeRTOS-V10.3.x.html" + #define configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY 0 +#endif /*-----------------------------------------------------------*/ /* *INDENT-OFF* */ diff --git a/Source/portable/GCC/ARM_CM4F/port.c b/Source/portable/GCC/ARM_CM4F/port.c index 73430b5bf..2d7d81127 100644 --- a/Source/portable/GCC/ARM_CM4F/port.c +++ b/Source/portable/GCC/ARM_CM4F/port.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -38,10 +38,14 @@ #error This port can only be used when the project options are configured to enable hardware floating point support. #endif +/* Prototype of all Interrupt Service Routines (ISRs). */ +typedef void ( * portISR_t )( void ); + /* Constants required to manipulate the core. Registers first... */ #define portNVIC_SYSTICK_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000e010 ) ) #define portNVIC_SYSTICK_LOAD_REG ( *( ( volatile uint32_t * ) 0xe000e014 ) ) #define portNVIC_SYSTICK_CURRENT_VALUE_REG ( *( ( volatile uint32_t * ) 0xe000e018 ) ) +#define portNVIC_SHPR2_REG ( *( ( volatile uint32_t * ) 0xe000ed1c ) ) #define portNVIC_SHPR3_REG ( *( ( volatile uint32_t * ) 0xe000ed20 ) ) /* ...then bits in the registers. */ #define portNVIC_SYSTICK_CLK_BIT ( 1UL << 2UL ) @@ -62,6 +66,11 @@ #define portNVIC_PENDSV_PRI ( ( ( uint32_t ) portMIN_INTERRUPT_PRIORITY ) << 16UL ) #define portNVIC_SYSTICK_PRI ( ( ( uint32_t ) portMIN_INTERRUPT_PRIORITY ) << 24UL ) +/* Constants used to check the installation of the FreeRTOS interrupt handlers. */ +#define portSCB_VTOR_REG ( *( ( portISR_t ** ) 0xE000ED08 ) ) +#define portVECTOR_INDEX_SVC ( 11 ) +#define portVECTOR_INDEX_PENDSV ( 14 ) + /* Constants required to check the validity of an interrupt priority. */ #define portFIRST_USER_INTERRUPT_NUMBER ( 16 ) #define portNVIC_IP_REGISTERS_OFFSET_16 ( 0xE000E3F0 ) @@ -302,6 +311,40 @@ BaseType_t xPortStartScheduler( void ) configASSERT( portCPUID != portCORTEX_M7_r0p1_ID ); configASSERT( portCPUID != portCORTEX_M7_r0p0_ID ); + /* An application can install FreeRTOS interrupt handlers in one of the + * folllowing ways: + * 1. Direct Routing - Install the functions vPortSVCHandler and + * xPortPendSVHandler for SVCall and PendSV interrupts respectively. + * 2. Indirect Routing - Install separate handlers for SVCall and PendSV + * interrupts and route program control from those handlers to + * vPortSVCHandler and xPortPendSVHandler functions. + * + * Applications that use Indirect Routing must set + * configCHECK_HANDLER_INSTALLATION to 0 in their FreeRTOSConfig.h. Direct + * routing, which is validated here when configCHECK_HANDLER_INSTALLATION + * is 1, should be preferred when possible. */ + #if ( configCHECK_HANDLER_INSTALLATION == 1 ) + { + const portISR_t * const pxVectorTable = portSCB_VTOR_REG; + + /* Validate that the application has correctly installed the FreeRTOS + * handlers for SVCall and PendSV interrupts. We do not check the + * installation of the SysTick handler because the application may + * choose to drive the RTOS tick using a timer other than the SysTick + * timer by overriding the weak function vPortSetupTimerInterrupt(). + * + * Assertion failures here indicate incorrect installation of the + * FreeRTOS handlers. For help installing the FreeRTOS handlers, see + * https://www.FreeRTOS.org/FAQHelp.html. + * + * Systems with a configurable address for the interrupt vector table + * can also encounter assertion failures or even system faults here if + * VTOR is not set correctly to point to the application's vector table. */ + configASSERT( pxVectorTable[ portVECTOR_INDEX_SVC ] == vPortSVCHandler ); + configASSERT( pxVectorTable[ portVECTOR_INDEX_PENDSV ] == xPortPendSVHandler ); + } + #endif /* configCHECK_HANDLER_INSTALLATION */ + #if ( configASSERT_DEFINED == 1 ) { volatile uint8_t ucOriginalPriority; @@ -351,22 +394,22 @@ BaseType_t xPortStartScheduler( void ) if( ulImplementedPrioBits == 8 ) { /* When the hardware implements 8 priority bits, there is no way for - * the software to configure PRIGROUP to not have sub-priorities. As - * a result, the least significant bit is always used for sub-priority - * and there are 128 preemption priorities and 2 sub-priorities. - * - * This may cause some confusion in some cases - for example, if - * configMAX_SYSCALL_INTERRUPT_PRIORITY is set to 5, both 5 and 4 - * priority interrupts will be masked in Critical Sections as those - * are at the same preemption priority. This may appear confusing as - * 4 is higher (numerically lower) priority than - * configMAX_SYSCALL_INTERRUPT_PRIORITY and therefore, should not - * have been masked. Instead, if we set configMAX_SYSCALL_INTERRUPT_PRIORITY - * to 4, this confusion does not happen and the behaviour remains the same. - * - * The following assert ensures that the sub-priority bit in the - * configMAX_SYSCALL_INTERRUPT_PRIORITY is clear to avoid the above mentioned - * confusion. */ + * the software to configure PRIGROUP to not have sub-priorities. As + * a result, the least significant bit is always used for sub-priority + * and there are 128 preemption priorities and 2 sub-priorities. + * + * This may cause some confusion in some cases - for example, if + * configMAX_SYSCALL_INTERRUPT_PRIORITY is set to 5, both 5 and 4 + * priority interrupts will be masked in Critical Sections as those + * are at the same preemption priority. This may appear confusing as + * 4 is higher (numerically lower) priority than + * configMAX_SYSCALL_INTERRUPT_PRIORITY and therefore, should not + * have been masked. Instead, if we set configMAX_SYSCALL_INTERRUPT_PRIORITY + * to 4, this confusion does not happen and the behaviour remains the same. + * + * The following assert ensures that the sub-priority bit in the + * configMAX_SYSCALL_INTERRUPT_PRIORITY is clear to avoid the above mentioned + * confusion. */ configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & 0x1U ) == 0U ); ulMaxPRIGROUPValue = 0; } @@ -386,9 +429,11 @@ BaseType_t xPortStartScheduler( void ) } #endif /* configASSERT_DEFINED */ - /* Make PendSV and SysTick the lowest priority interrupts. */ + /* Make PendSV and SysTick the lowest priority interrupts, and make SVCall + * the highest priority. */ portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI; portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI; + portNVIC_SHPR2_REG = 0; /* Start the timer that generates the tick ISR. Interrupts are disabled * here already. */ @@ -521,14 +566,21 @@ void xPortSysTickHandler( void ) * save and then restore the interrupt mask value as its value is already * known. */ portDISABLE_INTERRUPTS(); + traceISR_ENTER(); { /* Increment the RTOS tick. */ if( xTaskIncrementTick() != pdFALSE ) { + traceISR_EXIT_TO_SCHEDULER(); + /* A context switch is required. Context switching is performed in * the PendSV interrupt. Pend the PendSV interrupt. */ portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; } + else + { + traceISR_EXIT(); + } } portENABLE_INTERRUPTS(); } diff --git a/Source/portable/GCC/ARM_CM4F/portmacro.h b/Source/portable/GCC/ARM_CM4F/portmacro.h index ec9cfc99f..ce54d93cc 100644 --- a/Source/portable/GCC/ARM_CM4F/portmacro.h +++ b/Source/portable/GCC/ARM_CM4F/portmacro.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -28,7 +28,7 @@ #ifndef PORTMACRO_H - #define PORTMACRO_H +#define PORTMACRO_H /* *INDENT-OFF* */ #ifdef __cplusplus @@ -47,45 +47,45 @@ */ /* Type definitions. */ - #define portCHAR char - #define portFLOAT float - #define portDOUBLE double - #define portLONG long - #define portSHORT short - #define portSTACK_TYPE uint32_t - #define portBASE_TYPE long - - typedef portSTACK_TYPE StackType_t; - typedef long BaseType_t; - typedef unsigned long UBaseType_t; - - #if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS ) - typedef uint16_t TickType_t; - #define portMAX_DELAY ( TickType_t ) 0xffff - #elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS ) - typedef uint32_t TickType_t; - #define portMAX_DELAY ( TickType_t ) 0xffffffffUL +#define portCHAR char +#define portFLOAT float +#define portDOUBLE double +#define portLONG long +#define portSHORT short +#define portSTACK_TYPE uint32_t +#define portBASE_TYPE long + +typedef portSTACK_TYPE StackType_t; +typedef long BaseType_t; +typedef unsigned long UBaseType_t; + +#if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS ) + typedef uint16_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffff +#elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS ) + typedef uint32_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffffffffUL /* 32-bit tick type on a 32-bit architecture, so reads of the tick count do * not need to be guarded with a critical section. */ - #define portTICK_TYPE_IS_ATOMIC 1 - #elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_64_BITS ) - typedef uint64_t TickType_t; - #define portMAX_DELAY ( TickType_t ) 0xffffffffffffffffULL - #else - #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width. - #endif + #define portTICK_TYPE_IS_ATOMIC 1 +#elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_64_BITS ) + typedef uint64_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffffffffffffffffULL +#else /* if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS ) */ + #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width. +#endif /* if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS ) */ /*-----------------------------------------------------------*/ /* Architecture specifics. */ - #define portSTACK_GROWTH ( -1 ) - #define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) - #define portBYTE_ALIGNMENT 8 - #define portDONT_DISCARD __attribute__( ( used ) ) +#define portSTACK_GROWTH ( -1 ) +#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) +#define portBYTE_ALIGNMENT 8 +#define portDONT_DISCARD __attribute__( ( used ) ) /*-----------------------------------------------------------*/ /* Scheduler utilities. */ - #define portYIELD() \ +#define portYIELD() \ { \ /* Set a PendSV to request a context switch. */ \ portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; \ @@ -96,154 +96,166 @@ __asm volatile ( "isb" ); \ } - #define portNVIC_INT_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed04 ) ) - #define portNVIC_PENDSVSET_BIT ( 1UL << 28UL ) - #define portEND_SWITCHING_ISR( xSwitchRequired ) do { if( xSwitchRequired != pdFALSE ) portYIELD(); } while( 0 ) - #define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x ) +#define portNVIC_INT_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed04 ) ) +#define portNVIC_PENDSVSET_BIT ( 1UL << 28UL ) +#define portEND_SWITCHING_ISR( xSwitchRequired ) \ + do \ + { \ + if( xSwitchRequired != pdFALSE ) \ + { \ + traceISR_EXIT_TO_SCHEDULER(); \ + portYIELD(); \ + } \ + else \ + { \ + traceISR_EXIT(); \ + } \ + } while( 0 ) +#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x ) /*-----------------------------------------------------------*/ /* Critical section management. */ - extern void vPortEnterCritical( void ); - extern void vPortExitCritical( void ); - #define portSET_INTERRUPT_MASK_FROM_ISR() ulPortRaiseBASEPRI() - #define portCLEAR_INTERRUPT_MASK_FROM_ISR( x ) vPortSetBASEPRI( x ) - #define portDISABLE_INTERRUPTS() vPortRaiseBASEPRI() - #define portENABLE_INTERRUPTS() vPortSetBASEPRI( 0 ) - #define portENTER_CRITICAL() vPortEnterCritical() - #define portEXIT_CRITICAL() vPortExitCritical() +extern void vPortEnterCritical( void ); +extern void vPortExitCritical( void ); +#define portSET_INTERRUPT_MASK_FROM_ISR() ulPortRaiseBASEPRI() +#define portCLEAR_INTERRUPT_MASK_FROM_ISR( x ) vPortSetBASEPRI( x ) +#define portDISABLE_INTERRUPTS() vPortRaiseBASEPRI() +#define portENABLE_INTERRUPTS() vPortSetBASEPRI( 0 ) +#define portENTER_CRITICAL() vPortEnterCritical() +#define portEXIT_CRITICAL() vPortExitCritical() /*-----------------------------------------------------------*/ /* Task function macros as described on the FreeRTOS.org WEB site. These are * not necessary for to use this port. They are defined so the common demo files * (which build with all the ports) will build. */ - #define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters ) - #define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters ) +#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters ) +#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters ) /*-----------------------------------------------------------*/ /* Tickless idle/low power functionality. */ - #ifndef portSUPPRESS_TICKS_AND_SLEEP - extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime ); - #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime ) vPortSuppressTicksAndSleep( xExpectedIdleTime ) - #endif +#ifndef portSUPPRESS_TICKS_AND_SLEEP + extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime ); + #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime ) vPortSuppressTicksAndSleep( xExpectedIdleTime ) +#endif /*-----------------------------------------------------------*/ /* Architecture specific optimisations. */ - #ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION - #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1 - #endif +#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION + #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1 +#endif - #if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 +#if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 /* Generic helper function. */ - __attribute__( ( always_inline ) ) static inline uint8_t ucPortCountLeadingZeros( uint32_t ulBitmap ) - { - uint8_t ucReturn; + __attribute__( ( always_inline ) ) static inline uint8_t ucPortCountLeadingZeros( uint32_t ulBitmap ) + { + uint8_t ucReturn; - __asm volatile ( "clz %0, %1" : "=r" ( ucReturn ) : "r" ( ulBitmap ) : "memory" ); + __asm volatile ( "clz %0, %1" : "=r" ( ucReturn ) : "r" ( ulBitmap ) : "memory" ); - return ucReturn; - } + return ucReturn; + } /* Check the configuration. */ - #if ( configMAX_PRIORITIES > 32 ) - #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice. - #endif + #if ( configMAX_PRIORITIES > 32 ) + #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice. + #endif /* Store/clear the ready priorities in a bit map. */ - #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) ) - #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) ) + #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) ) + #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) ) /*-----------------------------------------------------------*/ - #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - ( uint32_t ) ucPortCountLeadingZeros( ( uxReadyPriorities ) ) ) + #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - ( uint32_t ) ucPortCountLeadingZeros( ( uxReadyPriorities ) ) ) - #endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */ +#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */ /*-----------------------------------------------------------*/ - #ifdef configASSERT - void vPortValidateInterruptPriority( void ); - #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() vPortValidateInterruptPriority() - #endif +#ifdef configASSERT + void vPortValidateInterruptPriority( void ); + #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() vPortValidateInterruptPriority() +#endif /* portNOP() is not required by this port. */ - #define portNOP() +#define portNOP() - #define portINLINE __inline +#define portINLINE __inline - #ifndef portFORCE_INLINE - #define portFORCE_INLINE inline __attribute__( ( always_inline ) ) - #endif +#ifndef portFORCE_INLINE + #define portFORCE_INLINE inline __attribute__( ( always_inline ) ) +#endif - portFORCE_INLINE static BaseType_t xPortIsInsideInterrupt( void ) +portFORCE_INLINE static BaseType_t xPortIsInsideInterrupt( void ) +{ + uint32_t ulCurrentInterrupt; + BaseType_t xReturn; + + /* Obtain the number of the currently executing interrupt. */ + __asm volatile ( "mrs %0, ipsr" : "=r" ( ulCurrentInterrupt )::"memory" ); + + if( ulCurrentInterrupt == 0 ) + { + xReturn = pdFALSE; + } + else { - uint32_t ulCurrentInterrupt; - BaseType_t xReturn; - - /* Obtain the number of the currently executing interrupt. */ - __asm volatile ( "mrs %0, ipsr" : "=r" ( ulCurrentInterrupt )::"memory" ); - - if( ulCurrentInterrupt == 0 ) - { - xReturn = pdFALSE; - } - else - { - xReturn = pdTRUE; - } - - return xReturn; + xReturn = pdTRUE; } + return xReturn; +} + /*-----------------------------------------------------------*/ - portFORCE_INLINE static void vPortRaiseBASEPRI( void ) - { - uint32_t ulNewBASEPRI; - - __asm volatile - ( - " mov %0, %1 \n"\ - " msr basepri, %0 \n"\ - " isb \n"\ - " dsb \n"\ - : "=r" ( ulNewBASEPRI ) : "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "memory" - ); - } +portFORCE_INLINE static void vPortRaiseBASEPRI( void ) +{ + uint32_t ulNewBASEPRI; + + __asm volatile + ( + " mov %0, %1 \n" \ + " msr basepri, %0 \n" \ + " isb \n" \ + " dsb \n" \ + : "=r" ( ulNewBASEPRI ) : "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "memory" + ); +} /*-----------------------------------------------------------*/ - portFORCE_INLINE static uint32_t ulPortRaiseBASEPRI( void ) - { - uint32_t ulOriginalBASEPRI, ulNewBASEPRI; - - __asm volatile - ( - " mrs %0, basepri \n"\ - " mov %1, %2 \n"\ - " msr basepri, %1 \n"\ - " isb \n"\ - " dsb \n"\ - : "=r" ( ulOriginalBASEPRI ), "=r" ( ulNewBASEPRI ) : "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "memory" - ); - - /* This return will not be reached but is necessary to prevent compiler - * warnings. */ - return ulOriginalBASEPRI; - } +portFORCE_INLINE static uint32_t ulPortRaiseBASEPRI( void ) +{ + uint32_t ulOriginalBASEPRI, ulNewBASEPRI; + + __asm volatile + ( + " mrs %0, basepri \n" \ + " mov %1, %2 \n" \ + " msr basepri, %1 \n" \ + " isb \n" \ + " dsb \n" \ + : "=r" ( ulOriginalBASEPRI ), "=r" ( ulNewBASEPRI ) : "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "memory" + ); + + /* This return will not be reached but is necessary to prevent compiler + * warnings. */ + return ulOriginalBASEPRI; +} /*-----------------------------------------------------------*/ - portFORCE_INLINE static void vPortSetBASEPRI( uint32_t ulNewMaskValue ) - { - __asm volatile - ( - " msr basepri, %0 "::"r" ( ulNewMaskValue ) : "memory" - ); - } +portFORCE_INLINE static void vPortSetBASEPRI( uint32_t ulNewMaskValue ) +{ + __asm volatile + ( + " msr basepri, %0 " ::"r" ( ulNewMaskValue ) : "memory" + ); +} /*-----------------------------------------------------------*/ - #define portMEMORY_BARRIER() __asm volatile ( "" ::: "memory" ) +#define portMEMORY_BARRIER() __asm volatile ( "" ::: "memory" ) /* *INDENT-OFF* */ #ifdef __cplusplus diff --git a/Source/portable/GCC/ARM_CM4_MPU/mpu_wrappers_v2_asm.c b/Source/portable/GCC/ARM_CM4_MPU/mpu_wrappers_v2_asm.c index 7aa81666d..6b808ee52 100644 --- a/Source/portable/GCC/ARM_CM4_MPU/mpu_wrappers_v2_asm.c +++ b/Source/portable/GCC/ARM_CM4_MPU/mpu_wrappers_v2_asm.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -365,31 +365,6 @@ } /*-----------------------------------------------------------*/ - char * MPU_pcTaskGetName( TaskHandle_t xTaskToQuery ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; - - char * MPU_pcTaskGetName( TaskHandle_t xTaskToQuery ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ - { - __asm volatile - ( - " .syntax unified \n" - " .extern MPU_pcTaskGetNameImpl \n" - " \n" - " push {r0} \n" - " mrs r0, control \n" - " tst r0, #1 \n" - " bne MPU_pcTaskGetName_Unpriv \n" - " MPU_pcTaskGetName_Priv: \n" - " pop {r0} \n" - " b MPU_pcTaskGetNameImpl \n" - " MPU_pcTaskGetName_Unpriv: \n" - " pop {r0} \n" - " svc %0 \n" - " \n" - : : "i" ( SYSTEM_CALL_pcTaskGetName ) : "memory" - ); - } -/*-----------------------------------------------------------*/ - #if ( configGENERATE_RUN_TIME_STATS == 1 ) configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetRunTimeCounter( const TaskHandle_t xTask ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; @@ -1512,30 +1487,27 @@ #if ( configUSE_TIMERS == 1 ) - BaseType_t MPU_xTimerGenericCommandEntry( const xTimerGenericCommandParams_t * pxParams ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + BaseType_t MPU_xTimerGenericCommandFromTaskEntry( const xTimerGenericCommandFromTaskParams_t * pxParams ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; - BaseType_t MPU_xTimerGenericCommandEntry( const xTimerGenericCommandParams_t * pxParams ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + BaseType_t MPU_xTimerGenericCommandFromTaskEntry( const xTimerGenericCommandFromTaskParams_t * pxParams ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ { __asm volatile ( - " .syntax unified \n" - " .extern MPU_xTimerGenericCommandPrivImpl \n" - " \n" - " push {r0} \n" - " mrs r0, ipsr \n" - " cmp r0, #0 \n" - " bne MPU_xTimerGenericCommand_Priv \n" - " mrs r0, control \n" - " tst r0, #1 \n" - " beq MPU_xTimerGenericCommand_Priv \n" - " MPU_xTimerGenericCommand_Unpriv: \n" - " pop {r0} \n" - " svc %0 \n" - " MPU_xTimerGenericCommand_Priv: \n" - " pop {r0} \n" - " b MPU_xTimerGenericCommandPrivImpl \n" - " \n" - : : "i" ( SYSTEM_CALL_xTimerGenericCommand ) : "memory" + " .syntax unified \n" + " .extern MPU_xTimerGenericCommandFromTaskImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " bne MPU_xTimerGenericCommandFromTask_Unpriv \n" + " MPU_xTimerGenericCommandFromTask_Priv: \n" + " pop {r0} \n" + " b MPU_xTimerGenericCommandFromTaskImpl \n" + " MPU_xTimerGenericCommandFromTask_Unpriv: \n" + " pop {r0} \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xTimerGenericCommandFromTask ) : "memory" ); } diff --git a/Source/portable/GCC/ARM_CM4_MPU/port.c b/Source/portable/GCC/ARM_CM4_MPU/port.c index 575c5accb..ad45a291e 100644 --- a/Source/portable/GCC/ARM_CM4_MPU/port.c +++ b/Source/portable/GCC/ARM_CM4_MPU/port.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -62,6 +62,9 @@ #define configALLOW_UNPRIVILEGED_CRITICAL_SECTIONS 1 #endif +/* Prototype of all Interrupt Service Routines (ISRs). */ +typedef void ( * portISR_t )( void ); + /* Constants required to access and manipulate the NVIC. */ #define portNVIC_SYSTICK_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000e010 ) ) #define portNVIC_SYSTICK_LOAD_REG ( *( ( volatile uint32_t * ) 0xe000e014 ) ) @@ -97,7 +100,6 @@ #define portMIN_INTERRUPT_PRIORITY ( 255UL ) #define portNVIC_PENDSV_PRI ( ( ( uint32_t ) portMIN_INTERRUPT_PRIORITY ) << 16UL ) #define portNVIC_SYSTICK_PRI ( ( ( uint32_t ) portMIN_INTERRUPT_PRIORITY ) << 24UL ) -#define portNVIC_SVC_PRI ( ( ( uint32_t ) configMAX_SYSCALL_INTERRUPT_PRIORITY - 1UL ) << 24UL ) /* Constants required to manipulate the VFP. */ #define portFPCCR ( ( volatile uint32_t * ) 0xe000ef34UL ) /* Floating point context control register. */ @@ -109,6 +111,11 @@ #define portINITIAL_CONTROL_IF_UNPRIVILEGED ( 0x03 ) #define portINITIAL_CONTROL_IF_PRIVILEGED ( 0x02 ) +/* Constants used to check the installation of the FreeRTOS interrupt handlers. */ +#define portSCB_VTOR_REG ( *( ( portISR_t ** ) 0xE000ED08 ) ) +#define portVECTOR_INDEX_SVC ( 11 ) +#define portVECTOR_INDEX_PENDSV ( 14 ) + /* Constants required to check the validity of an interrupt priority. */ #define portFIRST_USER_INTERRUPT_NUMBER ( 16 ) #define portNVIC_IP_REGISTERS_OFFSET_16 ( 0xE000E3F0 ) @@ -131,7 +138,7 @@ /* For strict compliance with the Cortex-M spec the task start address should * have bit-0 clear, as it is loaded into the PC on exit from an ISR. */ -#define portSTART_ADDRESS_MASK ( ( StackType_t ) 0xfffffffeUL ) +#define portSTART_ADDRESS_MASK ( ( StackType_t ) 0xfffffffeUL ) /* Does addr lie within [start, end] address range? */ #define portIS_ADDRESS_WITHIN_RANGE( addr, start, end ) \ @@ -207,6 +214,11 @@ BaseType_t xIsPrivileged( void ) __attribute__( ( naked ) ); */ void vResetPrivilege( void ) __attribute__( ( naked ) ); +/** + * @brief Make a task unprivileged. + */ +void vPortSwitchToUserMode( void ); + /** * @brief Enter critical section. */ @@ -252,13 +264,13 @@ void vResetPrivilege( void ) __attribute__( ( naked ) ); #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) - /** - * @brief Sets up the task stack so that upon returning from - * SVC, the task stack is used again. - * - * @param pulSystemCallStack The current SP when the SVC was raised. - * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler. - */ +/** + * @brief Sets up the task stack so that upon returning from + * SVC, the task stack is used again. + * + * @param pulSystemCallStack The current SP when the SVC was raised. + * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler. + */ void vSystemCallExit( uint32_t * pulSystemCallStack, uint32_t ulLR ) PRIVILEGED_FUNCTION; @@ -315,28 +327,29 @@ StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, } else { - xMPUSettings->ulTaskFlags &= ( ~portTASK_IS_PRIVILEGED_FLAG ); + xMPUSettings->ulTaskFlags &= ( ~( portTASK_IS_PRIVILEGED_FLAG ) ); xMPUSettings->ulContext[ 0 ] = portINITIAL_CONTROL_IF_UNPRIVILEGED; } - xMPUSettings->ulContext[ 1 ] = 0x04040404; /* r4. */ - xMPUSettings->ulContext[ 2 ] = 0x05050505; /* r5. */ - xMPUSettings->ulContext[ 3 ] = 0x06060606; /* r6. */ - xMPUSettings->ulContext[ 4 ] = 0x07070707; /* r7. */ - xMPUSettings->ulContext[ 5 ] = 0x08080808; /* r8. */ - xMPUSettings->ulContext[ 6 ] = 0x09090909; /* r9. */ - xMPUSettings->ulContext[ 7 ] = 0x10101010; /* r10. */ - xMPUSettings->ulContext[ 8 ] = 0x11111111; /* r11. */ - xMPUSettings->ulContext[ 9 ] = portINITIAL_EXC_RETURN; /* EXC_RETURN. */ - - xMPUSettings->ulContext[ 10 ] = ( uint32_t ) ( pxTopOfStack - 8 ); /* PSP with the hardware saved stack. */ - xMPUSettings->ulContext[ 11 ] = ( uint32_t ) pvParameters; /* r0. */ - xMPUSettings->ulContext[ 12 ] = 0x01010101; /* r1. */ - xMPUSettings->ulContext[ 13 ] = 0x02020202; /* r2. */ - xMPUSettings->ulContext[ 14 ] = 0x03030303; /* r3. */ - xMPUSettings->ulContext[ 15 ] = 0x12121212; /* r12. */ - xMPUSettings->ulContext[ 16 ] = 0; /* LR. */ + + xMPUSettings->ulContext[ 1 ] = 0x04040404; /* r4. */ + xMPUSettings->ulContext[ 2 ] = 0x05050505; /* r5. */ + xMPUSettings->ulContext[ 3 ] = 0x06060606; /* r6. */ + xMPUSettings->ulContext[ 4 ] = 0x07070707; /* r7. */ + xMPUSettings->ulContext[ 5 ] = 0x08080808; /* r8. */ + xMPUSettings->ulContext[ 6 ] = 0x09090909; /* r9. */ + xMPUSettings->ulContext[ 7 ] = 0x10101010; /* r10. */ + xMPUSettings->ulContext[ 8 ] = 0x11111111; /* r11. */ + xMPUSettings->ulContext[ 9 ] = portINITIAL_EXC_RETURN; /* EXC_RETURN. */ + + xMPUSettings->ulContext[ 10 ] = ( uint32_t ) ( pxTopOfStack - 8 ); /* PSP with the hardware saved stack. */ + xMPUSettings->ulContext[ 11 ] = ( uint32_t ) pvParameters; /* r0. */ + xMPUSettings->ulContext[ 12 ] = 0x01010101; /* r1. */ + xMPUSettings->ulContext[ 13 ] = 0x02020202; /* r2. */ + xMPUSettings->ulContext[ 14 ] = 0x03030303; /* r3. */ + xMPUSettings->ulContext[ 15 ] = 0x12121212; /* r12. */ + xMPUSettings->ulContext[ 16 ] = 0; /* LR. */ xMPUSettings->ulContext[ 17 ] = ( ( uint32_t ) pxCode ) & portSTART_ADDRESS_MASK; /* PC. */ - xMPUSettings->ulContext[ 18 ] = portINITIAL_XPSR; /* xPSR. */ + xMPUSettings->ulContext[ 18 ] = portINITIAL_XPSR; /* xPSR. */ #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) { @@ -399,13 +412,13 @@ StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, /* Assumes psp was in use. */ __asm volatile ( - #ifndef USE_PROCESS_STACK /* Code should not be required if a main() is using the process stack. */ - " tst lr, #4 \n" - " ite eq \n" - " mrseq r0, msp \n" - " mrsne r0, psp \n" + #ifndef USE_PROCESS_STACK /* Code should not be required if a main() is using the process stack. */ + " tst lr, #4 \n" + " ite eq \n" + " mrseq r0, msp \n" + " mrsne r0, psp \n" #else - " mrs r0, psp \n" + " mrs r0, psp \n" #endif " b %0 \n" ::"i" ( vSVCHandler_C ) : "r0", "memory" @@ -422,6 +435,7 @@ void vSVCHandler_C( uint32_t * pulParam ) /* PRIVILEGED_FUNCTION */ #if ( ( configUSE_MPU_WRAPPERS_V1 == 1 ) && ( configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY == 1 ) ) #if defined( __ARMCC_VERSION ) + /* Declaration when these variable are defined in code instead of being * exported from linker scripts. */ extern uint32_t * __syscalls_flash_start__; @@ -441,7 +455,6 @@ void vSVCHandler_C( uint32_t * pulParam ) /* PRIVILEGED_FUNCTION */ switch( ucSVCNumber ) { case portSVC_START_SCHEDULER: - portNVIC_SHPR2_REG |= portNVIC_SVC_PRI; prvRestoreContextOfFirstTask(); break; @@ -544,12 +557,11 @@ void vSVCHandler_C( uint32_t * pulParam ) /* PRIVILEGED_FUNCTION */ { /* Extended frame i.e. FPU in use. */ ulStackFrameSize = 26; - __asm volatile - ( + __asm volatile ( " vpush {s0} \n" /* Trigger lazy stacking. */ " vpop {s0} \n" /* Nullify the affect of the above instruction. */ ::: "memory" - ); + ); } else { @@ -570,13 +582,12 @@ void vSVCHandler_C( uint32_t * pulParam ) /* PRIVILEGED_FUNCTION */ __asm volatile ( "msr psp, %0" : : "r" ( pulSystemCallStack ) ); /* Raise the privilege for the duration of the system call. */ - __asm volatile - ( + __asm volatile ( " mrs r1, control \n" /* Obtain current control value. */ " bic r1, #1 \n" /* Clear nPRIV bit. */ " msr control, r1 \n" /* Write back new control value. */ ::: "r1", "memory" - ); + ); /* Remember the location where we should copy the stack frame when we exit from * the system call. */ @@ -590,7 +601,6 @@ void vSVCHandler_C( uint32_t * pulParam ) /* PRIVILEGED_FUNCTION */ /* Start executing the system call upon returning from this handler. */ pulSystemCallStack[ portOFFSET_TO_PC ] = uxSystemCallImplementations[ ucSystemCallNumber ]; - /* Raise a request to exit from the system call upon finishing the * system call. */ pulSystemCallStack[ portOFFSET_TO_LR ] = ( uint32_t ) vRequestSystemCallExit; @@ -669,12 +679,11 @@ void vSVCHandler_C( uint32_t * pulParam ) /* PRIVILEGED_FUNCTION */ { /* Extended frame i.e. FPU in use. */ ulStackFrameSize = 26; - __asm volatile - ( + __asm volatile ( " vpush {s0} \n" /* Trigger lazy stacking. */ " vpop {s0} \n" /* Nullify the affect of the above instruction. */ ::: "memory" - ); + ); } else { @@ -695,13 +704,12 @@ void vSVCHandler_C( uint32_t * pulParam ) /* PRIVILEGED_FUNCTION */ __asm volatile ( "msr psp, %0" : : "r" ( pulTaskStack ) ); /* Drop the privilege before returning to the thread mode. */ - __asm volatile - ( + __asm volatile ( " mrs r1, control \n" /* Obtain current control value. */ " orr r1, #1 \n" /* Set nPRIV bit. */ " msr control, r1 \n" /* Write back new control value. */ ::: "r1", "memory" - ); + ); /* Return to the caller of the System Call entry point (i.e. the * caller of the MPU_). */ @@ -764,15 +772,15 @@ static void prvRestoreContextOfFirstTask( void ) " str r3, [r0] \n" /* Disable MPU. */ " \n" " ldr r0, =0xe000ed9c \n" /* Region Base Address register. */ - " ldmia r2!, {r4-r11} \n" /* Read 4 sets of MPU registers [MPU Region # 4 - 7]. */ - " stmia r0, {r4-r11} \n" /* Write 4 sets of MPU registers [MPU Region # 4 - 7]. */ + " ldmia r2!, {r4-r11} \n" /* Read 4 sets of MPU registers [MPU Region # 0 - 3]. */ + " stmia r0, {r4-r11} \n" /* Write 4 sets of MPU registers [MPU Region # 0 - 3]. */ " \n" - #if ( configTOTAL_MPU_REGIONS == 16 ) - " ldmia r2!, {r4-r11} \n" /* Read 4 sets of MPU registers [MPU Region # 8 - 11]. */ - " stmia r0, {r4-r11} \n" /* Write 4 sets of MPU registers. [MPU Region # 8 - 11]. */ - " ldmia r2!, {r4-r11} \n" /* Read 4 sets of MPU registers [MPU Region # 12 - 15]. */ - " stmia r0, {r4-r11} \n" /* Write 4 sets of MPU registers. [MPU Region # 12 - 15]. */ - #endif /* configTOTAL_MPU_REGIONS == 16. */ + #if ( configTOTAL_MPU_REGIONS == 16 ) + " ldmia r2!, {r4-r11} \n" /* Read 4 sets of MPU registers [MPU Region # 4 - 8]. */ + " stmia r0, {r4-r11} \n" /* Write 4 sets of MPU registers. [MPU Region # 4 - 8]. */ + " ldmia r2!, {r4-r11} \n" /* Read 4 sets of MPU registers [MPU Region # 9 - 12]. */ + " stmia r0, {r4-r11} \n" /* Write 4 sets of MPU registers. [MPU Region # 9 - 12]. */ + #endif /* configTOTAL_MPU_REGIONS == 16. */ " \n" " ldr r0, =0xe000ed94 \n" /* MPU_CTRL register. */ " ldr r3, [r0] \n" /* Read the value of MPU_CTRL. */ @@ -813,6 +821,7 @@ BaseType_t xPortStartScheduler( void ) #if ( configENABLE_ERRATA_837070_WORKAROUND == 1 ) configASSERT( ( portCPUID == portCORTEX_M7_r0p1_ID ) || ( portCPUID == portCORTEX_M7_r0p0_ID ) ); #else + /* When using this port on a Cortex-M7 r0p0 or r0p1 core, define * configENABLE_ERRATA_837070_WORKAROUND to 1 in your * FreeRTOSConfig.h. */ @@ -820,6 +829,40 @@ BaseType_t xPortStartScheduler( void ) configASSERT( portCPUID != portCORTEX_M7_r0p0_ID ); #endif + /* An application can install FreeRTOS interrupt handlers in one of the + * folllowing ways: + * 1. Direct Routing - Install the functions vPortSVCHandler and + * xPortPendSVHandler for SVCall and PendSV interrupts respectively. + * 2. Indirect Routing - Install separate handlers for SVCall and PendSV + * interrupts and route program control from those handlers to + * vPortSVCHandler and xPortPendSVHandler functions. + * + * Applications that use Indirect Routing must set + * configCHECK_HANDLER_INSTALLATION to 0 in their FreeRTOSConfig.h. Direct + * routing, which is validated here when configCHECK_HANDLER_INSTALLATION + * is 1, should be preferred when possible. */ + #if ( configCHECK_HANDLER_INSTALLATION == 1 ) + { + const portISR_t * const pxVectorTable = portSCB_VTOR_REG; + + /* Validate that the application has correctly installed the FreeRTOS + * handlers for SVCall and PendSV interrupts. We do not check the + * installation of the SysTick handler because the application may + * choose to drive the RTOS tick using a timer other than the SysTick + * timer by overriding the weak function vPortSetupTimerInterrupt(). + * + * Assertion failures here indicate incorrect installation of the + * FreeRTOS handlers. For help installing the FreeRTOS handlers, see + * https://www.FreeRTOS.org/FAQHelp.html. + * + * Systems with a configurable address for the interrupt vector table + * can also encounter assertion failures or even system faults here if + * VTOR is not set correctly to point to the application's vector table. */ + configASSERT( pxVectorTable[ portVECTOR_INDEX_SVC ] == vPortSVCHandler ); + configASSERT( pxVectorTable[ portVECTOR_INDEX_PENDSV ] == xPortPendSVHandler ); + } + #endif /* configCHECK_HANDLER_INSTALLATION */ + #if ( configASSERT_DEFINED == 1 ) { volatile uint8_t ucOriginalPriority; @@ -904,11 +947,11 @@ BaseType_t xPortStartScheduler( void ) } #endif /* configASSERT_DEFINED */ - /* Make PendSV and SysTick the same priority as the kernel, and the SVC - * handler higher priority so it can be used to exit a critical section (where - * lower priorities are masked). */ + /* Make PendSV and SysTick the lowest priority interrupts, and make SVCall + * the highest priority. */ portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI; portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI; + portNVIC_SHPR2_REG = 0; /* Configure the regions in the MPU that are common to all tasks. */ prvSetupMPU(); @@ -936,8 +979,7 @@ BaseType_t xPortStartScheduler( void ) * in use in case the FPU was used before the scheduler was started - which * would otherwise result in the unnecessary leaving of space in the SVC stack * for lazy saving of FPU registers. */ - __asm volatile - ( + __asm volatile ( " ldr r0, =0xE000ED08 \n" /* Use the NVIC offset register to locate the stack. */ " ldr r0, [r0] \n" " ldr r0, [r0] \n" @@ -951,8 +993,7 @@ BaseType_t xPortStartScheduler( void ) " svc %0 \n" /* System call to start first task. */ " nop \n" " .ltorg \n" - ::"i" ( portSVC_START_SCHEDULER ) : "memory" - ); + ::"i" ( portSVC_START_SCHEDULER ) : "memory" ); /* Should not get here! */ return 0; @@ -1067,15 +1108,15 @@ void xPortPendSVHandler( void ) " \n" /*---------- Select next task. --------- */ " mov r0, %0 \n" - #if ( configENABLE_ERRATA_837070_WORKAROUND == 1 ) - " cpsid i \n" /* ARM Cortex-M7 r0p1 Errata 837070 workaround. */ - #endif + #if ( configENABLE_ERRATA_837070_WORKAROUND == 1 ) + " cpsid i \n" /* ARM Cortex-M7 r0p1 Errata 837070 workaround. */ + #endif " msr basepri, r0 \n" " dsb \n" " isb \n" - #if ( configENABLE_ERRATA_837070_WORKAROUND == 1 ) - " cpsie i \n" /* ARM Cortex-M7 r0p1 Errata 837070 workaround. */ - #endif + #if ( configENABLE_ERRATA_837070_WORKAROUND == 1 ) + " cpsie i \n" /* ARM Cortex-M7 r0p1 Errata 837070 workaround. */ + #endif " bl vTaskSwitchContext \n" " mov r0, #0 \n" " msr basepri, r0 \n" @@ -1092,15 +1133,15 @@ void xPortPendSVHandler( void ) " str r3, [r0] \n" /* Disable MPU. */ " \n" " ldr r0, =0xe000ed9c \n" /* Region Base Address register. */ - " ldmia r2!, {r4-r11} \n" /* Read 4 sets of MPU registers [MPU Region # 4 - 7]. */ - " stmia r0, {r4-r11} \n" /* Write 4 sets of MPU registers [MPU Region # 4 - 7]. */ + " ldmia r2!, {r4-r11} \n" /* Read 4 sets of MPU registers [MPU Region # 0 - 3]. */ + " stmia r0, {r4-r11} \n" /* Write 4 sets of MPU registers [MPU Region # 0 - 3]. */ " \n" - #if ( configTOTAL_MPU_REGIONS == 16 ) - " ldmia r2!, {r4-r11} \n" /* Read 4 sets of MPU registers [MPU Region # 8 - 11]. */ - " stmia r0, {r4-r11} \n" /* Write 4 sets of MPU registers. [MPU Region # 8 - 11]. */ - " ldmia r2!, {r4-r11} \n" /* Read 4 sets of MPU registers [MPU Region # 12 - 15]. */ - " stmia r0, {r4-r11} \n" /* Write 4 sets of MPU registers. [MPU Region # 12 - 15]. */ - #endif /* configTOTAL_MPU_REGIONS == 16. */ + #if ( configTOTAL_MPU_REGIONS == 16 ) + " ldmia r2!, {r4-r11} \n" /* Read 4 sets of MPU registers [MPU Region # 4 - 7]. */ + " stmia r0, {r4-r11} \n" /* Write 4 sets of MPU registers. [MPU Region # 4 - 7]. */ + " ldmia r2!, {r4-r11} \n" /* Read 4 sets of MPU registers [MPU Region # 8 - 11]. */ + " stmia r0, {r4-r11} \n" /* Write 4 sets of MPU registers. [MPU Region # 8 - 11]. */ + #endif /* configTOTAL_MPU_REGIONS == 16. */ " \n" " ldr r0, =0xe000ed94 \n" /* MPU_CTRL register. */ " ldr r3, [r0] \n" /* Read the value of MPU_CTRL. */ @@ -1141,13 +1182,19 @@ void xPortSysTickHandler( void ) uint32_t ulDummy; ulDummy = portSET_INTERRUPT_MASK_FROM_ISR(); + traceISR_ENTER(); { /* Increment the RTOS tick. */ if( xTaskIncrementTick() != pdFALSE ) { + traceISR_EXIT_TO_SCHEDULER(); /* Pend a context switch. */ portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; } + else + { + traceISR_EXIT(); + } } portCLEAR_INTERRUPT_MASK_FROM_ISR( ulDummy ); } @@ -1188,6 +1235,7 @@ static void vPortEnableVFP( void ) static void prvSetupMPU( void ) { #if defined( __ARMCC_VERSION ) + /* Declaration when these variable are defined in code instead of being * exported from linker scripts. */ extern uint32_t * __privileged_functions_start__; @@ -1321,12 +1369,26 @@ void vResetPrivilege( void ) /* __attribute__ (( naked )) */ } /*-----------------------------------------------------------*/ +void vPortSwitchToUserMode( void ) +{ + /* Load the current task's MPU settings from its TCB. */ + xMPU_SETTINGS * xTaskMpuSettings = xTaskGetMPUSettings( NULL ); + + /* Mark the task as unprivileged. */ + xTaskMpuSettings->ulTaskFlags &= ( ~( portTASK_IS_PRIVILEGED_FLAG ) ); + + /* Lower the processor's privilege level. */ + vResetPrivilege(); +} +/*-----------------------------------------------------------*/ + void vPortStoreTaskMPUSettings( xMPU_SETTINGS * xMPUSettings, const struct xMEMORY_REGION * const xRegions, StackType_t * pxBottomOfStack, uint32_t ulStackDepth ) { #if defined( __ARMCC_VERSION ) + /* Declaration when these variable are defined in code instead of being * exported from linker scripts. */ extern uint32_t * __SRAM_segment_start__; @@ -1350,7 +1412,7 @@ void vPortStoreTaskMPUSettings( xMPU_SETTINGS * xMPUSettings, xMPUSettings->xRegion[ 0 ].ulRegionBaseAddress = ( ( uint32_t ) __SRAM_segment_start__ ) | /* Base address. */ ( portMPU_REGION_VALID ) | - ( portSTACK_REGION ); /* Region number. */ + ( portSTACK_REGION ); /* Region number. */ xMPUSettings->xRegion[ 0 ].ulRegionAttribute = ( portMPU_REGION_READ_WRITE ) | @@ -1547,7 +1609,7 @@ BaseType_t xPortIsAuthorizedToAccessBuffer( const void * pvBuffer, * devices by calling NVIC_SetPriorityGrouping( 0 ); before starting the * scheduler. Note however that some vendor specific peripheral libraries * assume a non-zero priority group setting, in which cases using a value - * of zero will result in unpredicable behaviour. */ + * of zero will result in unpredictable behaviour. */ configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue ); } diff --git a/Source/portable/GCC/ARM_CM4_MPU/portmacro.h b/Source/portable/GCC/ARM_CM4_MPU/portmacro.h index e76c68712..6d36b5c85 100644 --- a/Source/portable/GCC/ARM_CM4_MPU/portmacro.h +++ b/Source/portable/GCC/ARM_CM4_MPU/portmacro.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -63,7 +63,7 @@ typedef unsigned long UBaseType_t; #if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS ) typedef uint16_t TickType_t; #define portMAX_DELAY ( TickType_t ) 0xffff -#elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS ) +#elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS ) typedef uint32_t TickType_t; #define portMAX_DELAY ( TickType_t ) 0xffffffffUL @@ -71,9 +71,14 @@ typedef unsigned long UBaseType_t; * not need to be guarded with a critical section. */ #define portTICK_TYPE_IS_ATOMIC 1 #else - #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width. + #error "configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width." #endif +/* Errata 837070 workaround must be enabled on Cortex-M7 r0p0 + * and r0p1 cores. */ +#ifndef configENABLE_ERRATA_837070_WORKAROUND + #define configENABLE_ERRATA_837070_WORKAROUND 0 +#endif /*-----------------------------------------------------------*/ /* MPU specific constants. */ @@ -175,8 +180,8 @@ typedef unsigned long UBaseType_t; #define configTEX_S_C_B_SRAM ( 0x07UL ) #endif -#define portGENERAL_PERIPHERALS_REGION ( configTOTAL_MPU_REGIONS - 5UL ) -#define portSTACK_REGION ( configTOTAL_MPU_REGIONS - 4UL ) +#define portSTACK_REGION ( configTOTAL_MPU_REGIONS - 5UL ) +#define portGENERAL_PERIPHERALS_REGION ( configTOTAL_MPU_REGIONS - 4UL ) #define portUNPRIVILEGED_FLASH_REGION ( configTOTAL_MPU_REGIONS - 3UL ) #define portPRIVILEGED_FLASH_REGION ( configTOTAL_MPU_REGIONS - 2UL ) #define portPRIVILEGED_RAM_REGION ( configTOTAL_MPU_REGIONS - 1UL ) @@ -185,8 +190,6 @@ typedef unsigned long UBaseType_t; #define portNUM_CONFIGURABLE_REGIONS ( configTOTAL_MPU_REGIONS - 5UL ) #define portTOTAL_NUM_REGIONS_IN_TCB ( portNUM_CONFIGURABLE_REGIONS + 1 ) /* Plus 1 to create space for the stack region. */ -#define portSWITCH_TO_USER_MODE() __asm volatile ( " mrs r0, control \n orr r0, #1 \n msr control, r0 " ::: "r0", "memory" ) - typedef struct MPU_REGION_REGISTERS { uint32_t ulRegionBaseAddress; @@ -203,7 +206,7 @@ typedef struct MPU_REGION_SETTINGS #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) #ifndef configSYSTEM_CALL_STACK_SIZE - #error configSYSTEM_CALL_STACK_SIZE must be defined to the desired size of the system call stack in words for using MPU wrappers v2. + #error "configSYSTEM_CALL_STACK_SIZE must be defined to the desired size of the system call stack in words for using MPU wrappers v2." #endif typedef struct SYSTEM_CALL_STACK_INFO @@ -222,8 +225,8 @@ typedef struct MPU_REGION_SETTINGS #define portACL_ENTRY_SIZE_BITS ( 32U ) /* Flags used for xMPU_SETTINGS.ulTaskFlags member. */ -#define portSTACK_FRAME_HAS_PADDING_FLAG ( 1UL << 0UL ) -#define portTASK_IS_PRIVILEGED_FLAG ( 1UL << 1UL ) +#define portSTACK_FRAME_HAS_PADDING_FLAG ( 1UL << 0UL ) +#define portTASK_IS_PRIVILEGED_FLAG ( 1UL << 1UL ) typedef struct MPU_SETTINGS { @@ -255,7 +258,7 @@ typedef struct MPU_SETTINGS /* Scheduler utilities. */ -#define portYIELD() __asm volatile ( " SVC %0 \n"::"i" ( portSVC_YIELD ) : "memory" ) +#define portYIELD() __asm volatile ( " SVC %0 \n" ::"i" ( portSVC_YIELD ) : "memory" ) #define portYIELD_WITHIN_API() \ { \ /* Set a PendSV to request a context switch. */ \ @@ -269,8 +272,20 @@ typedef struct MPU_SETTINGS #define portNVIC_INT_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed04 ) ) #define portNVIC_PENDSVSET_BIT ( 1UL << 28UL ) -#define portEND_SWITCHING_ISR( xSwitchRequired ) do { if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; } while( 0 ) -#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x ) +#define portEND_SWITCHING_ISR( xSwitchRequired ) \ + do \ + { \ + if( xSwitchRequired ) \ + { \ + traceISR_EXIT_TO_SCHEDULER(); \ + portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; \ + } \ + else \ + { \ + traceISR_EXIT(); \ + } \ + } while( 0 ) +#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x ) /*-----------------------------------------------------------*/ /* Critical section management. */ @@ -311,7 +326,7 @@ extern void vPortExitCritical( void ); /* Check the configuration. */ #if ( configMAX_PRIORITIES > 32 ) - #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice. + #error "configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice." #endif /* Store/clear the ready priorities in a bit map. */ @@ -343,24 +358,33 @@ extern void vPortExitCritical( void ); extern BaseType_t xIsPrivileged( void ); extern void vResetPrivilege( void ); +extern void vPortSwitchToUserMode( void ); /** * @brief Checks whether or not the processor is privileged. * * @return 1 if the processor is already privileged, 0 otherwise. */ -#define portIS_PRIVILEGED() xIsPrivileged() +#define portIS_PRIVILEGED() xIsPrivileged() /** * @brief Raise an SVC request to raise privilege. */ -#define portRAISE_PRIVILEGE() __asm volatile ( "svc %0 \n" ::"i" ( portSVC_RAISE_PRIVILEGE ) : "memory" ); +#define portRAISE_PRIVILEGE() __asm volatile ( "svc %0 \n" ::"i" ( portSVC_RAISE_PRIVILEGE ) : "memory" ); /** * @brief Lowers the privilege level by setting the bit 0 of the CONTROL * register. */ -#define portRESET_PRIVILEGE() vResetPrivilege() +#define portRESET_PRIVILEGE() vResetPrivilege() + +/** + * @brief Make a task unprivileged. + * + * It must be called from privileged tasks only. Calling it from unprivileged + * task will result in a memory protection fault. + */ +#define portSWITCH_TO_USER_MODE() vPortSwitchToUserMode() /*-----------------------------------------------------------*/ extern BaseType_t xPortIsTaskPrivileged( void ); @@ -370,7 +394,7 @@ extern BaseType_t xPortIsTaskPrivileged( void ); * * @return pdTRUE if the calling task is privileged, pdFALSE otherwise. */ -#define portIS_TASK_PRIVILEGED() xPortIsTaskPrivileged() +#define portIS_TASK_PRIVILEGED() xPortIsTaskPrivileged() /*-----------------------------------------------------------*/ portFORCE_INLINE static BaseType_t xPortIsInsideInterrupt( void ) @@ -403,13 +427,13 @@ portFORCE_INLINE static void vPortRaiseBASEPRI( void ) ( " mov %0, %1 \n" #if ( configENABLE_ERRATA_837070_WORKAROUND == 1 ) - " cpsid i \n"/* ARM Cortex-M7 r0p1 Errata 837070 workaround. */ + " cpsid i \n" /* ARM Cortex-M7 r0p1 Errata 837070 workaround. */ #endif " msr basepri, %0 \n" " isb \n" " dsb \n" #if ( configENABLE_ERRATA_837070_WORKAROUND == 1 ) - " cpsie i \n"/* ARM Cortex-M7 r0p1 Errata 837070 workaround. */ + " cpsie i \n" /* ARM Cortex-M7 r0p1 Errata 837070 workaround. */ #endif : "=r" ( ulNewBASEPRI ) : "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "memory" ); @@ -426,13 +450,13 @@ portFORCE_INLINE static uint32_t ulPortRaiseBASEPRI( void ) " mrs %0, basepri \n" " mov %1, %2 \n" #if ( configENABLE_ERRATA_837070_WORKAROUND == 1 ) - " cpsid i \n"/* ARM Cortex-M7 r0p1 Errata 837070 workaround. */ + " cpsid i \n" /* ARM Cortex-M7 r0p1 Errata 837070 workaround. */ #endif " msr basepri, %1 \n" " isb \n" " dsb \n" #if ( configENABLE_ERRATA_837070_WORKAROUND == 1 ) - " cpsie i \n"/* ARM Cortex-M7 r0p1 Errata 837070 workaround. */ + " cpsie i \n" /* ARM Cortex-M7 r0p1 Errata 837070 workaround. */ #endif : "=r" ( ulOriginalBASEPRI ), "=r" ( ulNewBASEPRI ) : "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "memory" ); @@ -447,7 +471,7 @@ portFORCE_INLINE static void vPortSetBASEPRI( uint32_t ulNewMaskValue ) { __asm volatile ( - " msr basepri, %0 "::"r" ( ulNewMaskValue ) : "memory" + " msr basepri, %0 " ::"r" ( ulNewMaskValue ) : "memory" ); } /*-----------------------------------------------------------*/ @@ -455,7 +479,7 @@ portFORCE_INLINE static void vPortSetBASEPRI( uint32_t ulNewMaskValue ) #define portMEMORY_BARRIER() __asm volatile ( "" ::: "memory" ) #ifndef configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY - #warning "configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY is not defined. We recommend defining it to 1 in FreeRTOSConfig.h for better security. https://www.FreeRTOS.org/FreeRTOS-V10.3.x.html" + #warning "configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY is not defined. We recommend defining it to 1 in FreeRTOSConfig.h for better security. www.FreeRTOS.org/FreeRTOS-V10.3.x.html" #define configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY 0 #endif /*-----------------------------------------------------------*/ diff --git a/Source/portable/GCC/ARM_CM55/non_secure/mpu_wrappers_v2_asm.c b/Source/portable/GCC/ARM_CM55/non_secure/mpu_wrappers_v2_asm.c index d247c92e0..052f97850 100644 --- a/Source/portable/GCC/ARM_CM55/non_secure/mpu_wrappers_v2_asm.c +++ b/Source/portable/GCC/ARM_CM55/non_secure/mpu_wrappers_v2_asm.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -365,31 +365,6 @@ } /*-----------------------------------------------------------*/ - char * MPU_pcTaskGetName( TaskHandle_t xTaskToQuery ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; - - char * MPU_pcTaskGetName( TaskHandle_t xTaskToQuery ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ - { - __asm volatile - ( - " .syntax unified \n" - " .extern MPU_pcTaskGetNameImpl \n" - " \n" - " push {r0} \n" - " mrs r0, control \n" - " tst r0, #1 \n" - " bne MPU_pcTaskGetName_Unpriv \n" - " MPU_pcTaskGetName_Priv: \n" - " pop {r0} \n" - " b MPU_pcTaskGetNameImpl \n" - " MPU_pcTaskGetName_Unpriv: \n" - " pop {r0} \n" - " svc %0 \n" - " \n" - : : "i" ( SYSTEM_CALL_pcTaskGetName ) : "memory" - ); - } -/*-----------------------------------------------------------*/ - #if ( configGENERATE_RUN_TIME_STATS == 1 ) configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetRunTimeCounter( const TaskHandle_t xTask ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; @@ -1512,31 +1487,27 @@ #if ( configUSE_TIMERS == 1 ) - BaseType_t MPU_xTimerGenericCommandEntry( const xTimerGenericCommandParams_t * pxParams ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + BaseType_t MPU_xTimerGenericCommandFromTaskEntry( const xTimerGenericCommandFromTaskParams_t * pxParams ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; - BaseType_t MPU_xTimerGenericCommandEntry( const xTimerGenericCommandParams_t * pxParams ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + BaseType_t MPU_xTimerGenericCommandFromTaskEntry( const xTimerGenericCommandFromTaskParams_t * pxParams ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ { __asm volatile ( - " .syntax unified \n" - " .extern MPU_xTimerGenericCommandPrivImpl \n" - " \n" - " push {r0} \n" - " mrs r0, ipsr \n" - " cmp r0, #0 \n" - " bne MPU_xTimerGenericCommand_Priv \n" - " mrs r0, control \n" - " tst r0, #1 \n" - " beq MPU_xTimerGenericCommand_Priv \n" - " MPU_xTimerGenericCommand_Unpriv: \n" - " pop {r0} \n" - " svc %0 \n" - " MPU_xTimerGenericCommand_Priv: \n" - " pop {r0} \n" - " b MPU_xTimerGenericCommandPrivImpl \n" - " \n" - " \n" - : : "i" ( SYSTEM_CALL_xTimerGenericCommand ) : "memory" + " .syntax unified \n" + " .extern MPU_xTimerGenericCommandFromTaskImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " bne MPU_xTimerGenericCommandFromTask_Unpriv \n" + " MPU_xTimerGenericCommandFromTask_Priv: \n" + " pop {r0} \n" + " b MPU_xTimerGenericCommandFromTaskImpl \n" + " MPU_xTimerGenericCommandFromTask_Unpriv: \n" + " pop {r0} \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xTimerGenericCommandFromTask ) : "memory" ); } diff --git a/Source/portable/GCC/ARM_CM55/non_secure/port.c b/Source/portable/GCC/ARM_CM55/non_secure/port.c index 9712ac353..230fe5fc2 100644 --- a/Source/portable/GCC/ARM_CM55/non_secure/port.c +++ b/Source/portable/GCC/ARM_CM55/non_secure/port.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -68,6 +68,22 @@ #if ( ( configRUN_FREERTOS_SECURE_ONLY == 1 ) && ( configENABLE_TRUSTZONE == 1 ) ) #error TrustZone needs to be disabled in order to run FreeRTOS on the Secure Side. #endif + +/** + * Cortex-M23 does not have non-secure PSPLIM. We should use PSPLIM on Cortex-M23 + * only when FreeRTOS runs on secure side. + */ +#if ( ( portHAS_ARMV8M_MAIN_EXTENSION == 0 ) && ( configRUN_FREERTOS_SECURE_ONLY == 0 ) ) + #define portUSE_PSPLIM_REGISTER 0 +#else + #define portUSE_PSPLIM_REGISTER 1 +#endif +/*-----------------------------------------------------------*/ + +/** + * @brief Prototype of all Interrupt Service Routines (ISRs). + */ +typedef void ( * portISR_t )( void ); /*-----------------------------------------------------------*/ /** @@ -91,10 +107,18 @@ /** * @brief Constants required to manipulate the SCB. */ -#define portSCB_SYS_HANDLER_CTRL_STATE_REG ( *( volatile uint32_t * ) 0xe000ed24 ) +#define portSCB_VTOR_REG ( *( ( portISR_t ** ) 0xe000ed08 ) ) +#define portSCB_SYS_HANDLER_CTRL_STATE_REG ( *( ( volatile uint32_t * ) 0xe000ed24 ) ) #define portSCB_MEM_FAULT_ENABLE_BIT ( 1UL << 16UL ) /*-----------------------------------------------------------*/ +/** + * @brief Constants used to check the installation of the FreeRTOS interrupt handlers. + */ +#define portVECTOR_INDEX_SVC ( 11 ) +#define portVECTOR_INDEX_PENDSV ( 14 ) +/*-----------------------------------------------------------*/ + /** * @brief Constants required to check the validity of an interrupt priority. */ @@ -111,8 +135,8 @@ /** * @brief Constants used during system call enter and exit. */ -#define portPSR_STACK_PADDING_MASK ( 1UL << 9UL ) -#define portEXC_RETURN_STACK_FRAME_TYPE_MASK ( 1UL << 4UL ) +#define portPSR_STACK_PADDING_MASK ( 1UL << 9UL ) +#define portEXC_RETURN_STACK_FRAME_TYPE_MASK ( 1UL << 4UL ) /*-----------------------------------------------------------*/ /** @@ -134,81 +158,81 @@ /** * @brief Offsets in the stack to the parameters when inside the SVC handler. */ -#define portOFFSET_TO_LR ( 5 ) -#define portOFFSET_TO_PC ( 6 ) -#define portOFFSET_TO_PSR ( 7 ) +#define portOFFSET_TO_LR ( 5 ) +#define portOFFSET_TO_PC ( 6 ) +#define portOFFSET_TO_PSR ( 7 ) /*-----------------------------------------------------------*/ /** * @brief Constants required to manipulate the MPU. */ -#define portMPU_TYPE_REG ( *( ( volatile uint32_t * ) 0xe000ed90 ) ) -#define portMPU_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed94 ) ) -#define portMPU_RNR_REG ( *( ( volatile uint32_t * ) 0xe000ed98 ) ) +#define portMPU_TYPE_REG ( *( ( volatile uint32_t * ) 0xe000ed90 ) ) +#define portMPU_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed94 ) ) +#define portMPU_RNR_REG ( *( ( volatile uint32_t * ) 0xe000ed98 ) ) -#define portMPU_RBAR_REG ( *( ( volatile uint32_t * ) 0xe000ed9c ) ) -#define portMPU_RLAR_REG ( *( ( volatile uint32_t * ) 0xe000eda0 ) ) +#define portMPU_RBAR_REG ( *( ( volatile uint32_t * ) 0xe000ed9c ) ) +#define portMPU_RLAR_REG ( *( ( volatile uint32_t * ) 0xe000eda0 ) ) -#define portMPU_RBAR_A1_REG ( *( ( volatile uint32_t * ) 0xe000eda4 ) ) -#define portMPU_RLAR_A1_REG ( *( ( volatile uint32_t * ) 0xe000eda8 ) ) +#define portMPU_RBAR_A1_REG ( *( ( volatile uint32_t * ) 0xe000eda4 ) ) +#define portMPU_RLAR_A1_REG ( *( ( volatile uint32_t * ) 0xe000eda8 ) ) -#define portMPU_RBAR_A2_REG ( *( ( volatile uint32_t * ) 0xe000edac ) ) -#define portMPU_RLAR_A2_REG ( *( ( volatile uint32_t * ) 0xe000edb0 ) ) +#define portMPU_RBAR_A2_REG ( *( ( volatile uint32_t * ) 0xe000edac ) ) +#define portMPU_RLAR_A2_REG ( *( ( volatile uint32_t * ) 0xe000edb0 ) ) -#define portMPU_RBAR_A3_REG ( *( ( volatile uint32_t * ) 0xe000edb4 ) ) -#define portMPU_RLAR_A3_REG ( *( ( volatile uint32_t * ) 0xe000edb8 ) ) +#define portMPU_RBAR_A3_REG ( *( ( volatile uint32_t * ) 0xe000edb4 ) ) +#define portMPU_RLAR_A3_REG ( *( ( volatile uint32_t * ) 0xe000edb8 ) ) -#define portMPU_MAIR0_REG ( *( ( volatile uint32_t * ) 0xe000edc0 ) ) -#define portMPU_MAIR1_REG ( *( ( volatile uint32_t * ) 0xe000edc4 ) ) +#define portMPU_MAIR0_REG ( *( ( volatile uint32_t * ) 0xe000edc0 ) ) +#define portMPU_MAIR1_REG ( *( ( volatile uint32_t * ) 0xe000edc4 ) ) -#define portMPU_RBAR_ADDRESS_MASK ( 0xffffffe0 ) /* Must be 32-byte aligned. */ -#define portMPU_RLAR_ADDRESS_MASK ( 0xffffffe0 ) /* Must be 32-byte aligned. */ +#define portMPU_RBAR_ADDRESS_MASK ( 0xffffffe0 ) /* Must be 32-byte aligned. */ +#define portMPU_RLAR_ADDRESS_MASK ( 0xffffffe0 ) /* Must be 32-byte aligned. */ -#define portMPU_RBAR_ACCESS_PERMISSIONS_MASK ( 3UL << 1UL ) +#define portMPU_RBAR_ACCESS_PERMISSIONS_MASK ( 3UL << 1UL ) -#define portMPU_MAIR_ATTR0_POS ( 0UL ) -#define portMPU_MAIR_ATTR0_MASK ( 0x000000ff ) +#define portMPU_MAIR_ATTR0_POS ( 0UL ) +#define portMPU_MAIR_ATTR0_MASK ( 0x000000ff ) -#define portMPU_MAIR_ATTR1_POS ( 8UL ) -#define portMPU_MAIR_ATTR1_MASK ( 0x0000ff00 ) +#define portMPU_MAIR_ATTR1_POS ( 8UL ) +#define portMPU_MAIR_ATTR1_MASK ( 0x0000ff00 ) -#define portMPU_MAIR_ATTR2_POS ( 16UL ) -#define portMPU_MAIR_ATTR2_MASK ( 0x00ff0000 ) +#define portMPU_MAIR_ATTR2_POS ( 16UL ) +#define portMPU_MAIR_ATTR2_MASK ( 0x00ff0000 ) -#define portMPU_MAIR_ATTR3_POS ( 24UL ) -#define portMPU_MAIR_ATTR3_MASK ( 0xff000000 ) +#define portMPU_MAIR_ATTR3_POS ( 24UL ) +#define portMPU_MAIR_ATTR3_MASK ( 0xff000000 ) -#define portMPU_MAIR_ATTR4_POS ( 0UL ) -#define portMPU_MAIR_ATTR4_MASK ( 0x000000ff ) +#define portMPU_MAIR_ATTR4_POS ( 0UL ) +#define portMPU_MAIR_ATTR4_MASK ( 0x000000ff ) -#define portMPU_MAIR_ATTR5_POS ( 8UL ) -#define portMPU_MAIR_ATTR5_MASK ( 0x0000ff00 ) +#define portMPU_MAIR_ATTR5_POS ( 8UL ) +#define portMPU_MAIR_ATTR5_MASK ( 0x0000ff00 ) -#define portMPU_MAIR_ATTR6_POS ( 16UL ) -#define portMPU_MAIR_ATTR6_MASK ( 0x00ff0000 ) +#define portMPU_MAIR_ATTR6_POS ( 16UL ) +#define portMPU_MAIR_ATTR6_MASK ( 0x00ff0000 ) -#define portMPU_MAIR_ATTR7_POS ( 24UL ) -#define portMPU_MAIR_ATTR7_MASK ( 0xff000000 ) +#define portMPU_MAIR_ATTR7_POS ( 24UL ) +#define portMPU_MAIR_ATTR7_MASK ( 0xff000000 ) -#define portMPU_RLAR_ATTR_INDEX0 ( 0UL << 1UL ) -#define portMPU_RLAR_ATTR_INDEX1 ( 1UL << 1UL ) -#define portMPU_RLAR_ATTR_INDEX2 ( 2UL << 1UL ) -#define portMPU_RLAR_ATTR_INDEX3 ( 3UL << 1UL ) -#define portMPU_RLAR_ATTR_INDEX4 ( 4UL << 1UL ) -#define portMPU_RLAR_ATTR_INDEX5 ( 5UL << 1UL ) -#define portMPU_RLAR_ATTR_INDEX6 ( 6UL << 1UL ) -#define portMPU_RLAR_ATTR_INDEX7 ( 7UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX0 ( 0UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX1 ( 1UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX2 ( 2UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX3 ( 3UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX4 ( 4UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX5 ( 5UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX6 ( 6UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX7 ( 7UL << 1UL ) -#define portMPU_RLAR_REGION_ENABLE ( 1UL ) +#define portMPU_RLAR_REGION_ENABLE ( 1UL ) /* Enable privileged access to unmapped region. */ -#define portMPU_PRIV_BACKGROUND_ENABLE_BIT ( 1UL << 2UL ) +#define portMPU_PRIV_BACKGROUND_ENABLE_BIT ( 1UL << 2UL ) /* Enable MPU. */ -#define portMPU_ENABLE_BIT ( 1UL << 0UL ) +#define portMPU_ENABLE_BIT ( 1UL << 0UL ) /* Expected value of the portMPU_TYPE register. */ -#define portEXPECTED_MPU_TYPE_VALUE ( configTOTAL_MPU_REGIONS << 8UL ) +#define portEXPECTED_MPU_TYPE_VALUE ( configTOTAL_MPU_REGIONS << 8UL ) /* Extract first address of the MPU region as encoded in the * RBAR (Region Base Address Register) value. */ @@ -448,13 +472,13 @@ portDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIV #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) - /** - * @brief Sets up the task stack so that upon returning from - * SVC, the task stack is used again. - * - * @param pulSystemCallStack The current SP when the SVC was raised. - * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler. - */ +/** + * @brief Sets up the task stack so that upon returning from + * SVC, the task stack is used again. + * + * @param pulSystemCallStack The current SP when the SVC was raised. + * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler. + */ void vSystemCallExit( uint32_t * pulSystemCallStack, uint32_t ulLR ) PRIVILEGED_FUNCTION; @@ -462,11 +486,11 @@ portDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIV #if ( configENABLE_MPU == 1 ) - /** - * @brief Checks whether or not the calling task is privileged. - * - * @return pdTRUE if the calling task is privileged, pdFALSE otherwise. - */ +/** + * @brief Checks whether or not the calling task is privileged. + * + * @return pdTRUE if the calling task is privileged, pdFALSE otherwise. + */ BaseType_t xPortIsTaskPrivileged( void ) PRIVILEGED_FUNCTION; #endif /* configENABLE_MPU == 1 */ @@ -501,13 +525,13 @@ PRIVILEGED_DATA static volatile uint32_t ulCriticalNesting = 0xaaaaaaaaUL; * FreeRTOS API functions are not called from interrupts that have been assigned * a priority above configMAX_SYSCALL_INTERRUPT_PRIORITY. */ -#if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) ) +#if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) static uint8_t ucMaxSysCallPriority = 0; static uint32_t ulMaxPRIGROUPValue = 0; static const volatile uint8_t * const pcInterruptPriorityRegisters = ( const volatile uint8_t * ) portNVIC_IP_REGISTERS_OFFSET_16; -#endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) ) */ +#endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */ #if ( configUSE_TICKLESS_IDLE == 1 ) @@ -760,8 +784,15 @@ __attribute__( ( weak ) ) void vPortSetupTimerInterrupt( void ) /* PRIVILEGED_FU } #endif /* configUSE_TICKLESS_IDLE */ - /* Stop and reset the SysTick. */ - portNVIC_SYSTICK_CTRL_REG = 0UL; + /* Stop and reset SysTick. + * + * QEMU versions older than 7.0.0 contain a bug which causes an error if we + * enable SysTick without first selecting a valid clock source. We trigger + * the bug if we change clock sources from a clock with a zero clock period + * to one with a nonzero clock period and enable Systick at the same time. + * So we configure the CLKSOURCE bit here, prior to setting the ENABLE bit. + * This workaround avoids the bug in QEMU versions older than 7.0.0. */ + portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT_CONFIG; portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL; /* Configure SysTick to interrupt at the requested rate. */ @@ -819,6 +850,7 @@ static void prvTaskExitError( void ) static void prvSetupMPU( void ) /* PRIVILEGED_FUNCTION */ { #if defined( __ARMCC_VERSION ) + /* Declaration when these variable are defined in code instead of being * exported from linker scripts. */ extern uint32_t * __privileged_functions_start__; @@ -972,13 +1004,19 @@ void SysTick_Handler( void ) /* PRIVILEGED_FUNCTION */ uint32_t ulPreviousMask; ulPreviousMask = portSET_INTERRUPT_MASK_FROM_ISR(); + traceISR_ENTER(); { /* Increment the RTOS tick. */ if( xTaskIncrementTick() != pdFALSE ) { + traceISR_EXIT_TO_SCHEDULER(); /* Pend a context switch. */ portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; } + else + { + traceISR_EXIT(); + } } portCLEAR_INTERRUPT_MASK_FROM_ISR( ulPreviousMask ); } @@ -988,6 +1026,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO { #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) ) #if defined( __ARMCC_VERSION ) + /* Declaration when these variable are defined in code instead of being * exported from linker scripts. */ extern uint32_t * __syscalls_flash_start__; @@ -1083,18 +1122,24 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO vRestoreContextOfFirstTask(); break; - #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) ) - case portSVC_RAISE_PRIVILEGE: + #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) ) + case portSVC_RAISE_PRIVILEGE: - /* Only raise the privilege, if the svc was raised from any of - * the system calls. */ - if( ( ulPC >= ( uint32_t ) __syscalls_flash_start__ ) && - ( ulPC <= ( uint32_t ) __syscalls_flash_end__ ) ) - { - vRaisePrivilege(); - } - break; - #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) */ + /* Only raise the privilege, if the svc was raised from any of + * the system calls. */ + if( ( ulPC >= ( uint32_t ) __syscalls_flash_start__ ) && + ( ulPC <= ( uint32_t ) __syscalls_flash_end__ ) ) + { + vRaisePrivilege(); + } + break; + #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) */ + + #if ( configENABLE_MPU == 1 ) + case portSVC_YIELD: + vPortYield(); + break; + #endif /* configENABLE_MPU == 1 */ default: /* Incorrect SVC call. */ @@ -1154,12 +1199,11 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO { /* Extended frame i.e. FPU in use. */ ulStackFrameSize = 26; - __asm volatile - ( + __asm volatile ( " vpush {s0} \n" /* Trigger lazy stacking. */ " vpop {s0} \n" /* Nullify the affect of the above instruction. */ ::: "memory" - ); + ); } else { @@ -1171,7 +1215,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO { ulStackFrameSize = 8; } - #endif /* if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */ + #endif /* configENABLE_FPU || configENABLE_MVE */ /* Make space on the system call stack for the stack frame. */ pulSystemCallStack = pulSystemCallStack - ulStackFrameSize; @@ -1187,18 +1231,24 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO * point (i.e. the caller of the MPU_). We need to restore it * when we exit from the system call. */ pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry = pulTaskStack[ portOFFSET_TO_LR ]; - /* Store the value of the PSPLIM register before the SVC was raised. * We need to restore it when we exit from the system call. */ - __asm volatile ( "mrs %0, psplim" : "=r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) ); + #if ( portUSE_PSPLIM_REGISTER == 1 ) + { + __asm volatile ( "mrs %0, psplim" : "=r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) ); + } + #endif /* Use the pulSystemCallStack in thread mode. */ __asm volatile ( "msr psp, %0" : : "r" ( pulSystemCallStack ) ); - __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) ); + #if ( portUSE_PSPLIM_REGISTER == 1 ) + { + __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) ); + } + #endif /* Start executing the system call upon returning from this handler. */ pulSystemCallStack[ portOFFSET_TO_PC ] = uxSystemCallImplementations[ ucSystemCallNumber ]; - /* Raise a request to exit from the system call upon finishing the * system call. */ pulSystemCallStack[ portOFFSET_TO_LR ] = ( uint32_t ) vRequestSystemCallExit; @@ -1224,14 +1274,13 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO pulSystemCallStack[ portOFFSET_TO_PSR ] &= ( ~portPSR_STACK_PADDING_MASK ); /* Raise the privilege for the duration of the system call. */ - __asm volatile - ( + __asm volatile ( " mrs r0, control \n" /* Obtain current control value. */ " movs r1, #1 \n" /* r1 = 1. */ " bics r0, r1 \n" /* Clear nPRIV bit. */ " msr control, r0 \n" /* Write back new control value. */ ::: "r0", "r1", "memory" - ); + ); } } @@ -1293,12 +1342,11 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO { /* Extended frame i.e. FPU in use. */ ulStackFrameSize = 26; - __asm volatile - ( + __asm volatile ( " vpush {s0} \n" /* Trigger lazy stacking. */ " vpop {s0} \n" /* Nullify the affect of the above instruction. */ ::: "memory" - ); + ); } else { @@ -1310,7 +1358,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO { ulStackFrameSize = 8; } - #endif /* if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */ + #endif /* configENABLE_FPU || configENABLE_MVE */ /* Make space on the task stack for the stack frame. */ pulTaskStack = pulTaskStack - ulStackFrameSize; @@ -1332,7 +1380,11 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO /* Restore the PSPLIM register to what it was at the time of * system call entry. */ - __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) ); + #if ( portUSE_PSPLIM_REGISTER == 1 ) + { + __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) ); + } + #endif /* If the hardware used padding to force the stack pointer * to be double word aligned, set the stacked xPSR bit[9], @@ -1350,14 +1402,13 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO pxMpuSettings->xSystemCallStackInfo.pulTaskStack = NULL; /* Drop the privilege before returning to the thread mode. */ - __asm volatile - ( + __asm volatile ( " mrs r0, control \n" /* Obtain current control value. */ " movs r1, #1 \n" /* r1 = 1. */ " orrs r0, r1 \n" /* Set nPRIV bit. */ " msr control, r0 \n" /* Write back new control value. */ ::: "r0", "r1", "memory" - ); + ); } } @@ -1410,21 +1461,21 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO xMPUSettings->ulContext[ ulIndex ] = 0x11111111; /* r11. */ ulIndex++; - xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pvParameters; /* r0. */ + xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pvParameters; /* r0. */ ulIndex++; - xMPUSettings->ulContext[ ulIndex ] = 0x01010101; /* r1. */ + xMPUSettings->ulContext[ ulIndex ] = 0x01010101; /* r1. */ ulIndex++; - xMPUSettings->ulContext[ ulIndex ] = 0x02020202; /* r2. */ + xMPUSettings->ulContext[ ulIndex ] = 0x02020202; /* r2. */ ulIndex++; - xMPUSettings->ulContext[ ulIndex ] = 0x03030303; /* r3. */ + xMPUSettings->ulContext[ ulIndex ] = 0x03030303; /* r3. */ ulIndex++; - xMPUSettings->ulContext[ ulIndex ] = 0x12121212; /* r12. */ + xMPUSettings->ulContext[ ulIndex ] = 0x12121212; /* r12. */ ulIndex++; xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portTASK_RETURN_ADDRESS; /* LR. */ ulIndex++; - xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxCode; /* PC. */ + xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxCode; /* PC. */ ulIndex++; - xMPUSettings->ulContext[ ulIndex ] = portINITIAL_XPSR; /* xPSR. */ + xMPUSettings->ulContext[ ulIndex ] = portINITIAL_XPSR; /* xPSR. */ ulIndex++; #if ( configENABLE_TRUSTZONE == 1 ) @@ -1435,8 +1486,9 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO #endif /* configENABLE_TRUSTZONE */ xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) ( pxTopOfStack - 8 ); /* PSP with the hardware saved stack. */ ulIndex++; - xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxEndOfStack; /* PSPLIM. */ + xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxEndOfStack; /* PSPLIM. */ ulIndex++; + if( xRunPrivileged == pdTRUE ) { xMPUSettings->ulTaskFlags |= portTASK_IS_PRIVILEGED_FLAG; @@ -1449,6 +1501,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portINITIAL_CONTROL_UNPRIVILEGED; /* CONTROL. */ ulIndex++; } + xMPUSettings->ulContext[ ulIndex ] = portINITIAL_EXC_RETURN; /* LR (EXC_RETURN). */ ulIndex++; @@ -1483,7 +1536,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO * interrupt. */ #if ( portPRELOAD_REGISTERS == 0 ) { - pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */ + pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */ *pxTopOfStack = portINITIAL_XPSR; /* xPSR. */ pxTopOfStack--; *pxTopOfStack = ( StackType_t ) pxCode; /* PC. */ @@ -1505,7 +1558,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO } #else /* portPRELOAD_REGISTERS */ { - pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */ + pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */ *pxTopOfStack = portINITIAL_XPSR; /* xPSR. */ pxTopOfStack--; *pxTopOfStack = ( StackType_t ) pxCode; /* PC. */ @@ -1540,7 +1593,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO pxTopOfStack--; *pxTopOfStack = portINITIAL_EXC_RETURN; /* EXC_RETURN. */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */ + *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */ #if ( configENABLE_TRUSTZONE == 1 ) { @@ -1559,22 +1612,52 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */ { - #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) ) + /* An application can install FreeRTOS interrupt handlers in one of the + * folllowing ways: + * 1. Direct Routing - Install the functions SVC_Handler and PendSV_Handler + * for SVCall and PendSV interrupts respectively. + * 2. Indirect Routing - Install separate handlers for SVCall and PendSV + * interrupts and route program control from those handlers to + * SVC_Handler and PendSV_Handler functions. + * + * Applications that use Indirect Routing must set + * configCHECK_HANDLER_INSTALLATION to 0 in their FreeRTOSConfig.h. Direct + * routing, which is validated here when configCHECK_HANDLER_INSTALLATION + * is 1, should be preferred when possible. */ + #if ( configCHECK_HANDLER_INSTALLATION == 1 ) + { + const portISR_t * const pxVectorTable = portSCB_VTOR_REG; + + /* Validate that the application has correctly installed the FreeRTOS + * handlers for SVCall and PendSV interrupts. We do not check the + * installation of the SysTick handler because the application may + * choose to drive the RTOS tick using a timer other than the SysTick + * timer by overriding the weak function vPortSetupTimerInterrupt(). + * + * Assertion failures here indicate incorrect installation of the + * FreeRTOS handlers. For help installing the FreeRTOS handlers, see + * https://www.FreeRTOS.org/FAQHelp.html. + * + * Systems with a configurable address for the interrupt vector table + * can also encounter assertion failures or even system faults here if + * VTOR is not set correctly to point to the application's vector table. */ + configASSERT( pxVectorTable[ portVECTOR_INDEX_SVC ] == SVC_Handler ); + configASSERT( pxVectorTable[ portVECTOR_INDEX_PENDSV ] == PendSV_Handler ); + } + #endif /* configCHECK_HANDLER_INSTALLATION */ + + #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) { - volatile uint32_t ulOriginalPriority; volatile uint32_t ulImplementedPrioBits = 0; volatile uint8_t ucMaxPriorityValue; /* Determine the maximum priority from which ISR safe FreeRTOS API - * functions can be called. ISR safe functions are those that end in - * "FromISR". FreeRTOS maintains separate thread and ISR API functions to + * functions can be called. ISR safe functions are those that end in + * "FromISR". FreeRTOS maintains separate thread and ISR API functions to * ensure interrupt entry is as fast and simple as possible. * - * Save the interrupt priority value that is about to be clobbered. */ - ulOriginalPriority = portNVIC_SHPR2_REG; - - /* Determine the number of priority bits available. First write to all - * possible bits. */ + * First, determine the number of priority bits available. Write to all + * possible bits in the priority setting for SVCall. */ portNVIC_SHPR2_REG = 0xFF000000; /* Read the value back to see how many bits stuck. */ @@ -1593,11 +1676,10 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */ /* Check that the bits not implemented in hardware are zero in * configMAX_SYSCALL_INTERRUPT_PRIORITY. */ - configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( ~ucMaxPriorityValue ) ) == 0U ); + configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( uint8_t ) ( ~( uint32_t ) ucMaxPriorityValue ) ) == 0U ); /* Calculate the maximum acceptable priority group value for the number * of bits read back. */ - while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE ) { ulImplementedPrioBits++; @@ -1635,16 +1717,14 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */ * register. */ ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT; ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK; - - /* Restore the clobbered interrupt priority register to its original - * value. */ - portNVIC_SHPR2_REG = ulOriginalPriority; } - #endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) ) */ + #endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */ - /* Make PendSV, CallSV and SysTick the same priority as the kernel. */ + /* Make PendSV and SysTick the lowest priority interrupts, and make SVCall + * the highest priority. */ portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI; portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI; + portNVIC_SHPR2_REG = 0; #if ( configENABLE_MPU == 1 ) { @@ -1701,6 +1781,7 @@ void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */ int32_t lIndex = 0; #if defined( __ARMCC_VERSION ) + /* Declaration when these variable are defined in code instead of being * exported from linker scripts. */ extern uint32_t * __privileged_sram_start__; @@ -1886,7 +1967,7 @@ BaseType_t xPortIsInsideInterrupt( void ) } /*-----------------------------------------------------------*/ -#if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) ) +#if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) void vPortValidateInterruptPriority( void ) { @@ -1944,7 +2025,7 @@ BaseType_t xPortIsInsideInterrupt( void ) configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue ); } -#endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) ) */ +#endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */ /*-----------------------------------------------------------*/ #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) diff --git a/Source/portable/GCC/ARM_CM55/non_secure/portasm.c b/Source/portable/GCC/ARM_CM55/non_secure/portasm.c index 7431c98f1..451e0abb7 100644 --- a/Source/portable/GCC/ARM_CM55/non_secure/portasm.c +++ b/Source/portable/GCC/ARM_CM55/non_secure/portasm.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -75,16 +75,16 @@ " ldmia r0!, {r4-r11} \n" /* Read 4 set of RBAR/RLAR registers from TCB. */ " stmia r2, {r4-r11} \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */ " \n" - #if ( configTOTAL_MPU_REGIONS == 16 ) - " movs r3, #8 \n" /* r3 = 8. */ - " str r3, [r1] \n" /* Program RNR = 8. */ - " ldmia r0!, {r4-r11} \n" /* Read 4 set of RBAR/RLAR registers from TCB. */ - " stmia r2, {r4-r11} \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */ - " movs r3, #12 \n" /* r3 = 12. */ - " str r3, [r1] \n" /* Program RNR = 12. */ - " ldmia r0!, {r4-r11} \n" /* Read 4 set of RBAR/RLAR registers from TCB. */ - " stmia r2, {r4-r11} \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */ - #endif /* configTOTAL_MPU_REGIONS == 16 */ + #if ( configTOTAL_MPU_REGIONS == 16 ) + " movs r3, #8 \n" /* r3 = 8. */ + " str r3, [r1] \n" /* Program RNR = 8. */ + " ldmia r0!, {r4-r11} \n" /* Read 4 set of RBAR/RLAR registers from TCB. */ + " stmia r2, {r4-r11} \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */ + " movs r3, #12 \n" /* r3 = 12. */ + " str r3, [r1] \n" /* Program RNR = 12. */ + " ldmia r0!, {r4-r11} \n" /* Read 4 set of RBAR/RLAR registers from TCB. */ + " stmia r2, {r4-r11} \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */ + #endif /* configTOTAL_MPU_REGIONS == 16 */ " \n" " ldr r1, xMPUCTRLConst2 \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */ " ldr r2, [r1] \n" /* Read the value of MPU_CTRL. */ @@ -294,15 +294,15 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att " save_general_regs: \n" " mrs r3, psp \n" " \n" - #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) - " add r3, r3, #0x20 \n" /* Move r3 to location where s0 is saved. */ - " tst lr, #0x10 \n" - " ittt eq \n" - " vstmiaeq r2!, {s16-s31} \n" /* Store s16-s31. */ - " vldmiaeq r3, {s0-s16} \n" /* Copy hardware saved FP context into s0-s16. */ - " vstmiaeq r2!, {s0-s16} \n" /* Store hardware saved FP context. */ - " sub r3, r3, #0x20 \n" /* Set r3 back to the location of hardware saved context. */ - #endif /* configENABLE_FPU || configENABLE_MVE */ + #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) + " add r3, r3, #0x20 \n" /* Move r3 to location where s0 is saved. */ + " tst lr, #0x10 \n" + " ittt eq \n" + " vstmiaeq r2!, {s16-s31} \n" /* Store s16-s31. */ + " vldmiaeq r3, {s0-s16} \n" /* Copy hardware saved FP context into s0-s16. */ + " vstmiaeq r2!, {s0-s16} \n" /* Store hardware saved FP context. */ + " sub r3, r3, #0x20 \n" /* Set r3 back to the location of hardware saved context. */ + #endif /* configENABLE_FPU || configENABLE_MVE */ " \n" " stmia r2!, {r4-r11} \n" /* Store r4-r11. */ " ldmia r3, {r4-r11} \n" /* Copy the hardware saved context into r4-r11. */ @@ -348,16 +348,16 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att " ldmia r0!, {r4-r11} \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */ " stmia r2, {r4-r11} \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */ " \n" - #if ( configTOTAL_MPU_REGIONS == 16 ) - " movs r3, #8 \n" /* r3 = 8. */ - " str r3, [r1] \n" /* Program RNR = 8. */ - " ldmia r0!, {r4-r11} \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */ - " stmia r2, {r4-r11} \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */ - " movs r3, #12 \n" /* r3 = 12. */ - " str r3, [r1] \n" /* Program RNR = 12. */ - " ldmia r0!, {r4-r11} \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */ - " stmia r2, {r4-r11} \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */ - #endif /* configTOTAL_MPU_REGIONS == 16 */ + #if ( configTOTAL_MPU_REGIONS == 16 ) + " movs r3, #8 \n" /* r3 = 8. */ + " str r3, [r1] \n" /* Program RNR = 8. */ + " ldmia r0!, {r4-r11} \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */ + " stmia r2, {r4-r11} \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */ + " movs r3, #12 \n" /* r3 = 12. */ + " str r3, [r1] \n" /* Program RNR = 12. */ + " ldmia r0!, {r4-r11} \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */ + " stmia r2, {r4-r11} \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */ + #endif /* configTOTAL_MPU_REGIONS == 16 */ " \n" " ldr r1, xMPUCTRLConst \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */ " ldr r2, [r1] \n" /* Read the value of MPU_CTRL. */ @@ -393,13 +393,13 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att " ldmdb r2!, {r4-r11} \n" /* r4-r11 contain hardware saved context. */ " stmia r3!, {r4-r11} \n" /* Copy the hardware saved context on the task stack. */ " ldmdb r2!, {r4-r11} \n" /* r4-r11 restored. */ - #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) - " tst lr, #0x10 \n" - " ittt eq \n" - " vldmdbeq r2!, {s0-s16} \n" /* s0-s16 contain hardware saved FP context. */ - " vstmiaeq r3!, {s0-s16} \n" /* Copy hardware saved FP context on the task stack. */ - " vldmdbeq r2!, {s16-s31} \n" /* Restore s16-s31. */ - #endif /* configENABLE_FPU || configENABLE_MVE */ + #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) + " tst lr, #0x10 \n" + " ittt eq \n" + " vldmdbeq r2!, {s0-s16} \n" /* s0-s16 contain hardware saved FP context. */ + " vstmiaeq r3!, {s0-s16} \n" /* Copy hardware saved FP context on the task stack. */ + " vldmdbeq r2!, {s16-s31} \n" /* Restore s16-s31. */ + #endif /* configENABLE_FPU || configENABLE_MVE */ " \n" " restore_context_done: \n" " str r2, [r1] \n" /* Save the location where the context should be saved next as the first member of TCB. */ @@ -452,11 +452,11 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att " save_ns_context: \n" " ldr r3, pxCurrentTCBConst \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ " ldr r1, [r3] \n" /* Read pxCurrentTCB. */ - #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) - " tst lr, #0x10 \n" /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */ - " it eq \n" - " vstmdbeq r2!, {s16-s31} \n" /* Store the additional FP context registers which are not saved automatically. */ - #endif /* configENABLE_FPU || configENABLE_MVE */ + #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) + " tst lr, #0x10 \n" /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */ + " it eq \n" + " vstmdbeq r2!, {s16-s31} \n" /* Store the additional FP context registers which are not saved automatically. */ + #endif /* configENABLE_FPU || configENABLE_MVE */ " subs r2, r2, #44 \n" /* Make space for xSecureContext, PSPLIM, LR and the remaining registers on the stack. */ " str r2, [r1] \n" /* Save the new top of stack in TCB. */ " adds r2, r2, #12 \n" /* r2 = r2 + 12. */ @@ -498,11 +498,11 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att " \n" " restore_ns_context: \n" " ldmia r2!, {r4-r11} \n" /* Restore the registers that are not automatically restored. */ - #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) - " tst lr, #0x10 \n" /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */ - " it eq \n" - " vldmiaeq r2!, {s16-s31} \n" /* Restore the additional FP context registers which are not restored automatically. */ - #endif /* configENABLE_FPU || configENABLE_MVE */ + #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) + " tst lr, #0x10 \n" /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */ + " it eq \n" + " vldmiaeq r2!, {s16-s31} \n" /* Restore the additional FP context registers which are not restored automatically. */ + #endif /* configENABLE_FPU || configENABLE_MVE */ " msr psp, r2 \n" /* Remember the new top of stack for the task. */ " bx lr \n" " \n" diff --git a/Source/portable/GCC/ARM_CM55/non_secure/portasm.h b/Source/portable/GCC/ARM_CM55/non_secure/portasm.h index f64ceb525..c6d2ebd58 100644 --- a/Source/portable/GCC/ARM_CM55/non_secure/portasm.h +++ b/Source/portable/GCC/ARM_CM55/non_secure/portasm.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/Source/portable/GCC/ARM_CM55/non_secure/portmacro.h b/Source/portable/GCC/ARM_CM55/non_secure/portmacro.h index 880205cb1..9f2bdb433 100644 --- a/Source/portable/GCC/ARM_CM55/non_secure/portmacro.h +++ b/Source/portable/GCC/ARM_CM55/non_secure/portmacro.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -53,9 +53,9 @@ /** * Architecture specifics. */ -#define portARCH_NAME "Cortex-M55" -#define portHAS_BASEPRI 1 -#define portDONT_DISCARD __attribute__( ( used ) ) +#define portARCH_NAME "Cortex-M55" +#define portHAS_ARMV8M_MAIN_EXTENSION 1 +#define portDONT_DISCARD __attribute__( ( used ) ) /*-----------------------------------------------------------*/ /* ARMv8-M common port configurations. */ @@ -65,8 +65,8 @@ /** * @brief Critical section management. */ -#define portDISABLE_INTERRUPTS() ulSetInterruptMask() -#define portENABLE_INTERRUPTS() vClearInterruptMask( 0 ) +#define portDISABLE_INTERRUPTS() ulSetInterruptMask() +#define portENABLE_INTERRUPTS() vClearInterruptMask( 0 ) /*-----------------------------------------------------------*/ /* *INDENT-OFF* */ diff --git a/Source/portable/GCC/ARM_CM55/non_secure/portmacrocommon.h b/Source/portable/GCC/ARM_CM55/non_secure/portmacrocommon.h index 6f666da22..33f21d85b 100644 --- a/Source/portable/GCC/ARM_CM55/non_secure/portmacrocommon.h +++ b/Source/portable/GCC/ARM_CM55/non_secure/portmacrocommon.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -117,7 +117,7 @@ extern uint32_t ulSetInterruptMask( void ) /* __attribute__(( naked )) PRIVILEGE extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */; #if ( configENABLE_TRUSTZONE == 1 ) - extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize ); /* __attribute__ (( naked )) */ + extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize ); /* __attribute__ (( naked )) */ extern void vPortFreeSecureContext( uint32_t * pulTCB ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */; #endif /* configENABLE_TRUSTZONE */ @@ -188,13 +188,13 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P #if ( configENABLE_MPU == 1 ) - /** - * @brief Settings to define an MPU region. - */ +/** + * @brief Settings to define an MPU region. + */ typedef struct MPURegionSettings { - uint32_t ulRBAR; /**< RBAR for the region. */ - uint32_t ulRLAR; /**< RLAR for the region. */ + uint32_t ulRBAR; /**< RBAR for the region. */ + uint32_t ulRLAR; /**< RLAR for the region. */ } MPURegionSettings_t; #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) @@ -203,9 +203,9 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P #error configSYSTEM_CALL_STACK_SIZE must be defined to the desired size of the system call stack in words for using MPU wrappers v2. #endif - /** - * @brief System call stack. - */ +/** + * @brief System call stack. + */ typedef struct SYSTEM_CALL_STACK_INFO { uint32_t ulSystemCallStackBuffer[ configSYSTEM_CALL_STACK_SIZE ]; @@ -218,74 +218,74 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P #endif /* configUSE_MPU_WRAPPERS_V1 == 0 */ - /** - * @brief MPU settings as stored in the TCB. - */ +/** + * @brief MPU settings as stored in the TCB. + */ #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) - #if( configENABLE_TRUSTZONE == 1 ) + #if ( configENABLE_TRUSTZONE == 1 ) - /* - * +-----------+---------------+----------+-----------------+------------------------------+-----+ - * | s16-s31 | s0-s15, FPSCR | r4-r11 | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, | | - * | | | | PC, xPSR | CONTROL, EXC_RETURN | | - * +-----------+---------------+----------+-----------------+------------------------------+-----+ - * - * <-----------><--------------><---------><----------------><-----------------------------><----> - * 16 16 8 8 5 1 - */ - #define MAX_CONTEXT_SIZE 54 +/* + * +-----------+---------------+----------+-----------------+------------------------------+-----+ + * | s16-s31 | s0-s15, FPSCR | r4-r11 | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, | | + * | | | | PC, xPSR | CONTROL, EXC_RETURN | | + * +-----------+---------------+----------+-----------------+------------------------------+-----+ + * + * <-----------><--------------><---------><----------------><-----------------------------><----> + * 16 16 8 8 5 1 + */ + #define MAX_CONTEXT_SIZE 54 #else /* #if( configENABLE_TRUSTZONE == 1 ) */ - /* - * +-----------+---------------+----------+-----------------+----------------------+-----+ - * | s16-s31 | s0-s15, FPSCR | r4-r11 | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL | | - * | | | | PC, xPSR | EXC_RETURN | | - * +-----------+---------------+----------+-----------------+----------------------+-----+ - * - * <-----------><--------------><---------><----------------><---------------------><----> - * 16 16 8 8 4 1 - */ - #define MAX_CONTEXT_SIZE 53 +/* + * +-----------+---------------+----------+-----------------+----------------------+-----+ + * | s16-s31 | s0-s15, FPSCR | r4-r11 | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL | | + * | | | | PC, xPSR | EXC_RETURN | | + * +-----------+---------------+----------+-----------------+----------------------+-----+ + * + * <-----------><--------------><---------><----------------><---------------------><----> + * 16 16 8 8 4 1 + */ + #define MAX_CONTEXT_SIZE 53 #endif /* #if( configENABLE_TRUSTZONE == 1 ) */ #else /* #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */ - #if( configENABLE_TRUSTZONE == 1 ) + #if ( configENABLE_TRUSTZONE == 1 ) - /* - * +----------+-----------------+------------------------------+-----+ - * | r4-r11 | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, | | - * | | PC, xPSR | CONTROL, EXC_RETURN | | - * +----------+-----------------+------------------------------+-----+ - * - * <---------><----------------><------------------------------><----> - * 8 8 5 1 - */ - #define MAX_CONTEXT_SIZE 22 +/* + * +----------+-----------------+------------------------------+-----+ + * | r4-r11 | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, | | + * | | PC, xPSR | CONTROL, EXC_RETURN | | + * +----------+-----------------+------------------------------+-----+ + * + * <---------><----------------><------------------------------><----> + * 8 8 5 1 + */ + #define MAX_CONTEXT_SIZE 22 #else /* #if( configENABLE_TRUSTZONE == 1 ) */ - /* - * +----------+-----------------+----------------------+-----+ - * | r4-r11 | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL | | - * | | PC, xPSR | EXC_RETURN | | - * +----------+-----------------+----------------------+-----+ - * - * <---------><----------------><----------------------><----> - * 8 8 4 1 - */ - #define MAX_CONTEXT_SIZE 21 +/* + * +----------+-----------------+----------------------+-----+ + * | r4-r11 | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL | | + * | | PC, xPSR | EXC_RETURN | | + * +----------+-----------------+----------------------+-----+ + * + * <---------><----------------><----------------------><----> + * 8 8 4 1 + */ + #define MAX_CONTEXT_SIZE 21 #endif /* #if( configENABLE_TRUSTZONE == 1 ) */ #endif /* #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */ - /* Flags used for xMPU_SETTINGS.ulTaskFlags member. */ - #define portSTACK_FRAME_HAS_PADDING_FLAG ( 1UL << 0UL ) - #define portTASK_IS_PRIVILEGED_FLAG ( 1UL << 1UL ) +/* Flags used for xMPU_SETTINGS.ulTaskFlags member. */ + #define portSTACK_FRAME_HAS_PADDING_FLAG ( 1UL << 0UL ) + #define portTASK_IS_PRIVILEGED_FLAG ( 1UL << 1UL ) /* Size of an Access Control List (ACL) entry in bits. */ #define portACL_ENTRY_SIZE_BITS ( 32U ) @@ -313,7 +313,7 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P * system calls. */ #ifdef configASSERT - #if ( portHAS_BASEPRI == 1 ) + #if ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) void vPortValidateInterruptPriority( void ); #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() vPortValidateInterruptPriority() #endif @@ -333,12 +333,29 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P /** * @brief Scheduler utilities. */ -#define portYIELD() vPortYield() +#if ( configENABLE_MPU == 1 ) + #define portYIELD() __asm volatile ( "svc %0" ::"i" ( portSVC_YIELD ) : "memory" ) + #define portYIELD_WITHIN_API() vPortYield() +#else + #define portYIELD() vPortYield() + #define portYIELD_WITHIN_API() vPortYield() +#endif + #define portNVIC_INT_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed04 ) ) #define portNVIC_PENDSVSET_BIT ( 1UL << 28UL ) -#define portEND_SWITCHING_ISR( xSwitchRequired ) \ - do { if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; } \ - while( 0 ) +#define portEND_SWITCHING_ISR( xSwitchRequired ) \ + do \ + { \ + if( xSwitchRequired ) \ + { \ + traceISR_EXIT_TO_SCHEDULER(); \ + portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; \ + } \ + else \ + { \ + traceISR_EXIT(); \ + } \ + } while( 0 ) #define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x ) /*-----------------------------------------------------------*/ @@ -424,12 +441,12 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P extern BaseType_t xPortIsTaskPrivileged( void ); - /** - * @brief Checks whether or not the calling task is privileged. - * - * @return pdTRUE if the calling task is privileged, pdFALSE otherwise. - */ - #define portIS_TASK_PRIVILEGED() xPortIsTaskPrivileged() +/** + * @brief Checks whether or not the calling task is privileged. + * + * @return pdTRUE if the calling task is privileged, pdFALSE otherwise. + */ + #define portIS_TASK_PRIVILEGED() xPortIsTaskPrivileged() #endif /* configENABLE_MPU == 1 */ /*-----------------------------------------------------------*/ @@ -440,6 +457,56 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P #define portMEMORY_BARRIER() __asm volatile ( "" ::: "memory" ) /*-----------------------------------------------------------*/ +/* Select correct value of configUSE_PORT_OPTIMISED_TASK_SELECTION + * based on whether or not Mainline extension is implemented. */ +#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION + #if ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) + #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1 + #else + #define configUSE_PORT_OPTIMISED_TASK_SELECTION 0 + #endif +#endif /* #ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION */ + +/** + * @brief Port-optimised task selection. + */ +#if ( configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 ) + +/** + * @brief Count the number of leading zeros in a 32-bit value. + */ + static portFORCE_INLINE uint32_t ulPortCountLeadingZeros( uint32_t ulBitmap ) + { + uint32_t ulReturn; + + __asm volatile ( "clz %0, %1" : "=r" ( ulReturn ) : "r" ( ulBitmap ) : "memory" ); + + return ulReturn; + } + +/* Check the configuration. */ + #if ( configMAX_PRIORITIES > 32 ) + #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 different priorities as tasks that share a priority will time slice. + #endif + + #if ( portHAS_ARMV8M_MAIN_EXTENSION == 0 ) + #error ARMv8-M baseline implementations (such as Cortex-M23) do not support port-optimised task selection. Please set configUSE_PORT_OPTIMISED_TASK_SELECTION to 0 or leave it undefined. + #endif + +/** + * @brief Store/clear the ready priorities in a bit map. + */ + #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) ) + #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) ) + +/** + * @brief Get the priority of the highest-priority task that is ready to execute. + */ + #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - ulPortCountLeadingZeros( ( uxReadyPriorities ) ) ) + +#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */ +/*-----------------------------------------------------------*/ + /* *INDENT-OFF* */ #ifdef __cplusplus } diff --git a/Source/portable/GCC/ARM_CM55/secure/secure_context.c b/Source/portable/GCC/ARM_CM55/secure/secure_context.c index e37dd9672..83b3dbce1 100644 --- a/Source/portable/GCC/ARM_CM55/secure/secure_context.c +++ b/Source/portable/GCC/ARM_CM55/secure/secure_context.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -65,7 +65,7 @@ * @brief Maximum number of secure contexts. */ #ifndef secureconfigMAX_SECURE_CONTEXTS - #define secureconfigMAX_SECURE_CONTEXTS 8UL + #define secureconfigMAX_SECURE_CONTEXTS 8UL #endif /*-----------------------------------------------------------*/ @@ -164,15 +164,15 @@ secureportNON_SECURE_CALLABLE void SecureContext_Init( void ) } #if ( configENABLE_MPU == 1 ) - { - /* Configure thread mode to use PSP and to be unprivileged. */ - secureportSET_CONTROL( securecontextCONTROL_VALUE_UNPRIVILEGED ); - } + { + /* Configure thread mode to use PSP and to be unprivileged. */ + secureportSET_CONTROL( securecontextCONTROL_VALUE_UNPRIVILEGED ); + } #else /* configENABLE_MPU */ - { - /* Configure thread mode to use PSP and to be privileged. */ - secureportSET_CONTROL( securecontextCONTROL_VALUE_PRIVILEGED ); - } + { + /* Configure thread mode to use PSP and to be privileged. */ + secureportSET_CONTROL( securecontextCONTROL_VALUE_PRIVILEGED ); + } #endif /* configENABLE_MPU */ } } @@ -219,16 +219,16 @@ secureportNON_SECURE_CALLABLE void SecureContext_Init( void ) if( pucStackMemory != NULL ) { /* Since stack grows down, the starting point will be the last - * location. Note that this location is next to the last - * allocated byte for stack (excluding the space for seal values) - * because the hardware decrements the stack pointer before - * writing i.e. if stack pointer is 0x2, a push operation will - * decrement the stack pointer to 0x1 and then write at 0x1. */ + * location. Note that this location is next to the last + * allocated byte for stack (excluding the space for seal values) + * because the hardware decrements the stack pointer before + * writing i.e. if stack pointer is 0x2, a push operation will + * decrement the stack pointer to 0x1 and then write at 0x1. */ xSecureContexts[ ulSecureContextIndex ].pucStackStart = pucStackMemory + ulSecureStackSize; /* Seal the created secure process stack. */ - *( uint32_t * )( pucStackMemory + ulSecureStackSize ) = securecontextSTACK_SEAL_VALUE; - *( uint32_t * )( pucStackMemory + ulSecureStackSize + 4 ) = securecontextSTACK_SEAL_VALUE; + *( uint32_t * ) ( pucStackMemory + ulSecureStackSize ) = securecontextSTACK_SEAL_VALUE; + *( uint32_t * ) ( pucStackMemory + ulSecureStackSize + 4 ) = securecontextSTACK_SEAL_VALUE; /* The stack cannot go beyond this location. This value is * programmed in the PSPLIM register on context switch.*/ @@ -237,32 +237,32 @@ secureportNON_SECURE_CALLABLE void SecureContext_Init( void ) xSecureContexts[ ulSecureContextIndex ].pvTaskHandle = pvTaskHandle; #if ( configENABLE_MPU == 1 ) + { + /* Store the correct CONTROL value for the task on the stack. + * This value is programmed in the CONTROL register on + * context switch. */ + pulCurrentStackPointer = ( uint32_t * ) xSecureContexts[ ulSecureContextIndex ].pucStackStart; + pulCurrentStackPointer--; + + if( ulIsTaskPrivileged ) { - /* Store the correct CONTROL value for the task on the stack. - * This value is programmed in the CONTROL register on - * context switch. */ - pulCurrentStackPointer = ( uint32_t * ) xSecureContexts[ ulSecureContextIndex ].pucStackStart; - pulCurrentStackPointer--; - - if( ulIsTaskPrivileged ) - { - *( pulCurrentStackPointer ) = securecontextCONTROL_VALUE_PRIVILEGED; - } - else - { - *( pulCurrentStackPointer ) = securecontextCONTROL_VALUE_UNPRIVILEGED; - } - - /* Store the current stack pointer. This value is programmed in - * the PSP register on context switch. */ - xSecureContexts[ ulSecureContextIndex ].pucCurrentStackPointer = ( uint8_t * ) pulCurrentStackPointer; + *( pulCurrentStackPointer ) = securecontextCONTROL_VALUE_PRIVILEGED; } - #else /* configENABLE_MPU */ + else { - /* Current SP is set to the starting of the stack. This - * value programmed in the PSP register on context switch. */ - xSecureContexts[ ulSecureContextIndex ].pucCurrentStackPointer = xSecureContexts[ ulSecureContextIndex ].pucStackStart; + *( pulCurrentStackPointer ) = securecontextCONTROL_VALUE_UNPRIVILEGED; } + + /* Store the current stack pointer. This value is programmed in + * the PSP register on context switch. */ + xSecureContexts[ ulSecureContextIndex ].pucCurrentStackPointer = ( uint8_t * ) pulCurrentStackPointer; + } + #else /* configENABLE_MPU */ + { + /* Current SP is set to the starting of the stack. This + * value programmed in the PSP register on context switch. */ + xSecureContexts[ ulSecureContextIndex ].pucCurrentStackPointer = xSecureContexts[ ulSecureContextIndex ].pucStackStart; + } #endif /* configENABLE_MPU */ /* Ensure to never return 0 as a valid context handle. */ @@ -275,7 +275,8 @@ secureportNON_SECURE_CALLABLE void SecureContext_Init( void ) } /*-----------------------------------------------------------*/ -secureportNON_SECURE_CALLABLE void SecureContext_FreeContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle ) +secureportNON_SECURE_CALLABLE void SecureContext_FreeContext( SecureContextHandle_t xSecureContextHandle, + void * pvTaskHandle ) { uint32_t ulIPSR, ulSecureContextIndex; @@ -306,7 +307,8 @@ secureportNON_SECURE_CALLABLE void SecureContext_FreeContext( SecureContextHandl } /*-----------------------------------------------------------*/ -secureportNON_SECURE_CALLABLE void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle ) +secureportNON_SECURE_CALLABLE void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle, + void * pvTaskHandle ) { uint8_t * pucStackLimit; uint32_t ulSecureContextIndex; @@ -328,7 +330,8 @@ secureportNON_SECURE_CALLABLE void SecureContext_LoadContext( SecureContextHandl } /*-----------------------------------------------------------*/ -secureportNON_SECURE_CALLABLE void SecureContext_SaveContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle ) +secureportNON_SECURE_CALLABLE void SecureContext_SaveContext( SecureContextHandle_t xSecureContextHandle, + void * pvTaskHandle ) { uint8_t * pucStackLimit; uint32_t ulSecureContextIndex; diff --git a/Source/portable/GCC/ARM_CM55/secure/secure_context.h b/Source/portable/GCC/ARM_CM55/secure/secure_context.h index 2220ea646..40fdc276d 100644 --- a/Source/portable/GCC/ARM_CM55/secure/secure_context.h +++ b/Source/portable/GCC/ARM_CM55/secure/secure_context.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -38,12 +38,12 @@ /** * @brief PSP value when no secure context is loaded. */ -#define securecontextNO_STACK 0x0 +#define securecontextNO_STACK 0x0 /** * @brief Invalid context ID. */ -#define securecontextINVALID_CONTEXT_ID 0UL +#define securecontextINVALID_CONTEXT_ID 0UL /*-----------------------------------------------------------*/ /** @@ -108,7 +108,8 @@ void SecureContext_Init( void ); * @param[in] xSecureContextHandle Context handle corresponding to the * context to be freed. */ -void SecureContext_FreeContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle ); +void SecureContext_FreeContext( SecureContextHandle_t xSecureContextHandle, + void * pvTaskHandle ); /** * @brief Loads the given context. @@ -119,7 +120,8 @@ void SecureContext_FreeContext( SecureContextHandle_t xSecureContextHandle, void * @param[in] xSecureContextHandle Context handle corresponding to the context * to be loaded. */ -void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle ); +void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle, + void * pvTaskHandle ); /** * @brief Saves the given context. @@ -130,6 +132,7 @@ void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle, void * @param[in] xSecureContextHandle Context handle corresponding to the context * to be saved. */ -void SecureContext_SaveContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle ); +void SecureContext_SaveContext( SecureContextHandle_t xSecureContextHandle, + void * pvTaskHandle ); #endif /* __SECURE_CONTEXT_H__ */ diff --git a/Source/portable/GCC/ARM_CM55/secure/secure_context_port.c b/Source/portable/GCC/ARM_CM55/secure/secure_context_port.c index d70822c06..31c1f7331 100644 --- a/Source/portable/GCC/ARM_CM55/secure/secure_context_port.c +++ b/Source/portable/GCC/ARM_CM55/secure/secure_context_port.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/Source/portable/GCC/ARM_CM55/secure/secure_heap.c b/Source/portable/GCC/ARM_CM55/secure/secure_heap.c index 19f7c2354..d9789404b 100644 --- a/Source/portable/GCC/ARM_CM55/secure/secure_heap.c +++ b/Source/portable/GCC/ARM_CM55/secure/secure_heap.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -62,6 +62,22 @@ /* Assumes 8bit bytes! */ #define secureheapBITS_PER_BYTE ( ( size_t ) 8 ) + +/* Max value that fits in a size_t type. */ +#define secureheapSIZE_MAX ( ~( ( size_t ) 0 ) ) + +/* Check if adding a and b will result in overflow. */ +#define secureheapADD_WILL_OVERFLOW( a, b ) ( ( a ) > ( secureheapSIZE_MAX - ( b ) ) ) + +/* MSB of the xBlockSize member of an BlockLink_t structure is used to track + * the allocation status of a block. When MSB of the xBlockSize member of + * an BlockLink_t structure is set then the block belongs to the application. + * When the bit is free the block is still part of the free heap space. */ +#define secureheapBLOCK_ALLOCATED_BITMASK ( ( ( size_t ) 1 ) << ( ( sizeof( size_t ) * secureheapBITS_PER_BYTE ) - 1 ) ) +#define secureheapBLOCK_SIZE_IS_VALID( xBlockSize ) ( ( ( xBlockSize ) & secureheapBLOCK_ALLOCATED_BITMASK ) == 0 ) +#define secureheapBLOCK_IS_ALLOCATED( pxBlock ) ( ( ( pxBlock->xBlockSize ) & secureheapBLOCK_ALLOCATED_BITMASK ) != 0 ) +#define secureheapALLOCATE_BLOCK( pxBlock ) ( ( pxBlock->xBlockSize ) |= secureheapBLOCK_ALLOCATED_BITMASK ) +#define secureheapFREE_BLOCK( pxBlock ) ( ( pxBlock->xBlockSize ) &= ~secureheapBLOCK_ALLOCATED_BITMASK ) /*-----------------------------------------------------------*/ /* Allocate the memory for the heap. */ @@ -123,14 +139,6 @@ static BlockLink_t * pxEnd = NULL; static size_t xFreeBytesRemaining = 0U; static size_t xMinimumEverFreeBytesRemaining = 0U; -/** - * @brief Gets set to the top bit of an size_t type. - * - * When this bit in the xBlockSize member of an BlockLink_t structure is set - * then the block belongs to the application. When the bit is free the block is - * still part of the free heap space. - */ -static size_t xBlockAllocatedBit = 0; /*-----------------------------------------------------------*/ static void prvHeapInit( void ) @@ -175,9 +183,6 @@ static void prvHeapInit( void ) /* Only one block exists - and it covers the entire usable heap space. */ xMinimumEverFreeBytesRemaining = pxFirstFreeBlock->xBlockSize; xFreeBytesRemaining = pxFirstFreeBlock->xBlockSize; - - /* Work out the position of the top bit in a size_t variable. */ - xBlockAllocatedBit = ( ( size_t ) 1 ) << ( ( sizeof( size_t ) * secureheapBITS_PER_BYTE ) - 1 ); } /*-----------------------------------------------------------*/ @@ -250,6 +255,7 @@ void * pvPortMalloc( size_t xWantedSize ) BlockLink_t * pxPreviousBlock; BlockLink_t * pxNewBlockLink; void * pvReturn = NULL; + size_t xAdditionalRequiredSize; /* If this is the first call to malloc then the heap will require * initialisation to setup the list of free blocks. */ @@ -262,25 +268,29 @@ void * pvPortMalloc( size_t xWantedSize ) mtCOVERAGE_TEST_MARKER(); } - /* Check the requested block size is not so large that the top bit is set. - * The top bit of the block size member of the BlockLink_t structure is used - * to determine who owns the block - the application or the kernel, so it - * must be free. */ - if( ( xWantedSize & xBlockAllocatedBit ) == 0 ) + if( xWantedSize > 0 ) { - /* The wanted size is increased so it can contain a BlockLink_t + /* The wanted size must be increased so it can contain a BlockLink_t * structure in addition to the requested amount of bytes. */ - if( xWantedSize > 0 ) + if( secureheapADD_WILL_OVERFLOW( xWantedSize, xHeapStructSize ) == 0 ) { xWantedSize += xHeapStructSize; - /* Ensure that blocks are always aligned to the required number of - * bytes. */ + /* Ensure that blocks are always aligned to the required number + * of bytes. */ if( ( xWantedSize & secureportBYTE_ALIGNMENT_MASK ) != 0x00 ) { /* Byte alignment required. */ - xWantedSize += ( secureportBYTE_ALIGNMENT - ( xWantedSize & secureportBYTE_ALIGNMENT_MASK ) ); - secureportASSERT( ( xWantedSize & secureportBYTE_ALIGNMENT_MASK ) == 0 ); + xAdditionalRequiredSize = secureportBYTE_ALIGNMENT - ( xWantedSize & secureportBYTE_ALIGNMENT_MASK ); + + if( secureheapADD_WILL_OVERFLOW( xWantedSize, xAdditionalRequiredSize ) == 0 ) + { + xWantedSize += xAdditionalRequiredSize; + } + else + { + xWantedSize = 0; + } } else { @@ -289,9 +299,20 @@ void * pvPortMalloc( size_t xWantedSize ) } else { - mtCOVERAGE_TEST_MARKER(); + xWantedSize = 0; } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + /* Check the requested block size is not so large that the top bit is set. + * The top bit of the block size member of the BlockLink_t structure is used + * to determine who owns the block - the application or the kernel, so it + * must be free. */ + if( secureheapBLOCK_SIZE_IS_VALID( xWantedSize ) != 0 ) + { if( ( xWantedSize > 0 ) && ( xWantedSize <= xFreeBytesRemaining ) ) { /* Traverse the list from the start (lowest address) block until @@ -334,7 +355,8 @@ void * pvPortMalloc( size_t xWantedSize ) pxBlock->xBlockSize = xWantedSize; /* Insert the new block into the list of free blocks. */ - prvInsertBlockIntoFreeList( pxNewBlockLink ); + pxNewBlockLink->pxNextFreeBlock = pxPreviousBlock->pxNextFreeBlock; + pxPreviousBlock->pxNextFreeBlock = pxNewBlockLink; } else { @@ -354,7 +376,7 @@ void * pvPortMalloc( size_t xWantedSize ) /* The block is being returned - it is allocated and owned by * the application and has no "next" block. */ - pxBlock->xBlockSize |= xBlockAllocatedBit; + secureheapALLOCATE_BLOCK( pxBlock ); pxBlock->pxNextFreeBlock = NULL; } else @@ -375,17 +397,17 @@ void * pvPortMalloc( size_t xWantedSize ) traceMALLOC( pvReturn, xWantedSize ); #if ( secureconfigUSE_MALLOC_FAILED_HOOK == 1 ) + { + if( pvReturn == NULL ) { - if( pvReturn == NULL ) - { - extern void vApplicationMallocFailedHook( void ); - vApplicationMallocFailedHook(); - } - else - { - mtCOVERAGE_TEST_MARKER(); - } + extern void vApplicationMallocFailedHook( void ); + vApplicationMallocFailedHook(); } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } #endif /* if ( secureconfigUSE_MALLOC_FAILED_HOOK == 1 ) */ secureportASSERT( ( ( ( size_t ) pvReturn ) & ( size_t ) secureportBYTE_ALIGNMENT_MASK ) == 0 ); @@ -408,16 +430,16 @@ void vPortFree( void * pv ) pxLink = ( void * ) puc; /* Check the block is actually allocated. */ - secureportASSERT( ( pxLink->xBlockSize & xBlockAllocatedBit ) != 0 ); + secureportASSERT( secureheapBLOCK_IS_ALLOCATED( pxLink ) != 0 ); secureportASSERT( pxLink->pxNextFreeBlock == NULL ); - if( ( pxLink->xBlockSize & xBlockAllocatedBit ) != 0 ) + if( secureheapBLOCK_IS_ALLOCATED( pxLink ) != 0 ) { if( pxLink->pxNextFreeBlock == NULL ) { /* The block is being returned to the heap - it is no longer * allocated. */ - pxLink->xBlockSize &= ~xBlockAllocatedBit; + secureheapFREE_BLOCK( pxLink ); secureportDISABLE_NON_SECURE_INTERRUPTS(); { diff --git a/Source/portable/GCC/ARM_CM55/secure/secure_heap.h b/Source/portable/GCC/ARM_CM55/secure/secure_heap.h index 75c9cb00b..cf5551046 100644 --- a/Source/portable/GCC/ARM_CM55/secure/secure_heap.h +++ b/Source/portable/GCC/ARM_CM55/secure/secure_heap.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/Source/portable/GCC/ARM_CM55/secure/secure_init.c b/Source/portable/GCC/ARM_CM55/secure/secure_init.c index f93bfce95..66d35eccc 100644 --- a/Source/portable/GCC/ARM_CM55/secure/secure_init.c +++ b/Source/portable/GCC/ARM_CM55/secure/secure_init.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -93,7 +93,7 @@ secureportNON_SECURE_CALLABLE void SecureInit_EnableNSFPUAccess( void ) * permitted. CP11 should be programmed to the same value as CP10. */ *( secureinitNSACR ) |= ( secureinitNSACR_CP10_MASK | secureinitNSACR_CP11_MASK ); - /* LSPENS = 0 ==> LSPEN is writable fron non-secure state. This ensures + /* LSPENS = 0 ==> LSPEN is writable from non-secure state. This ensures * that we can enable/disable lazy stacking in port.c file. */ *( secureinitFPCCR ) &= ~( secureinitFPCCR_LSPENS_MASK ); diff --git a/Source/portable/GCC/ARM_CM55/secure/secure_init.h b/Source/portable/GCC/ARM_CM55/secure/secure_init.h index e6c9da0b4..6404c5cc4 100644 --- a/Source/portable/GCC/ARM_CM55/secure/secure_init.h +++ b/Source/portable/GCC/ARM_CM55/secure/secure_init.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/Source/portable/GCC/ARM_CM55/secure/secure_port_macros.h b/Source/portable/GCC/ARM_CM55/secure/secure_port_macros.h index d7ac5833c..085108cc1 100644 --- a/Source/portable/GCC/ARM_CM55/secure/secure_port_macros.h +++ b/Source/portable/GCC/ARM_CM55/secure/secure_port_macros.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/Source/portable/GCC/ARM_CM55_NTZ/non_secure/mpu_wrappers_v2_asm.c b/Source/portable/GCC/ARM_CM55_NTZ/non_secure/mpu_wrappers_v2_asm.c index d247c92e0..052f97850 100644 --- a/Source/portable/GCC/ARM_CM55_NTZ/non_secure/mpu_wrappers_v2_asm.c +++ b/Source/portable/GCC/ARM_CM55_NTZ/non_secure/mpu_wrappers_v2_asm.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -365,31 +365,6 @@ } /*-----------------------------------------------------------*/ - char * MPU_pcTaskGetName( TaskHandle_t xTaskToQuery ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; - - char * MPU_pcTaskGetName( TaskHandle_t xTaskToQuery ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ - { - __asm volatile - ( - " .syntax unified \n" - " .extern MPU_pcTaskGetNameImpl \n" - " \n" - " push {r0} \n" - " mrs r0, control \n" - " tst r0, #1 \n" - " bne MPU_pcTaskGetName_Unpriv \n" - " MPU_pcTaskGetName_Priv: \n" - " pop {r0} \n" - " b MPU_pcTaskGetNameImpl \n" - " MPU_pcTaskGetName_Unpriv: \n" - " pop {r0} \n" - " svc %0 \n" - " \n" - : : "i" ( SYSTEM_CALL_pcTaskGetName ) : "memory" - ); - } -/*-----------------------------------------------------------*/ - #if ( configGENERATE_RUN_TIME_STATS == 1 ) configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetRunTimeCounter( const TaskHandle_t xTask ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; @@ -1512,31 +1487,27 @@ #if ( configUSE_TIMERS == 1 ) - BaseType_t MPU_xTimerGenericCommandEntry( const xTimerGenericCommandParams_t * pxParams ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + BaseType_t MPU_xTimerGenericCommandFromTaskEntry( const xTimerGenericCommandFromTaskParams_t * pxParams ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; - BaseType_t MPU_xTimerGenericCommandEntry( const xTimerGenericCommandParams_t * pxParams ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + BaseType_t MPU_xTimerGenericCommandFromTaskEntry( const xTimerGenericCommandFromTaskParams_t * pxParams ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ { __asm volatile ( - " .syntax unified \n" - " .extern MPU_xTimerGenericCommandPrivImpl \n" - " \n" - " push {r0} \n" - " mrs r0, ipsr \n" - " cmp r0, #0 \n" - " bne MPU_xTimerGenericCommand_Priv \n" - " mrs r0, control \n" - " tst r0, #1 \n" - " beq MPU_xTimerGenericCommand_Priv \n" - " MPU_xTimerGenericCommand_Unpriv: \n" - " pop {r0} \n" - " svc %0 \n" - " MPU_xTimerGenericCommand_Priv: \n" - " pop {r0} \n" - " b MPU_xTimerGenericCommandPrivImpl \n" - " \n" - " \n" - : : "i" ( SYSTEM_CALL_xTimerGenericCommand ) : "memory" + " .syntax unified \n" + " .extern MPU_xTimerGenericCommandFromTaskImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " bne MPU_xTimerGenericCommandFromTask_Unpriv \n" + " MPU_xTimerGenericCommandFromTask_Priv: \n" + " pop {r0} \n" + " b MPU_xTimerGenericCommandFromTaskImpl \n" + " MPU_xTimerGenericCommandFromTask_Unpriv: \n" + " pop {r0} \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xTimerGenericCommandFromTask ) : "memory" ); } diff --git a/Source/portable/GCC/ARM_CM55_NTZ/non_secure/port.c b/Source/portable/GCC/ARM_CM55_NTZ/non_secure/port.c index 9712ac353..230fe5fc2 100644 --- a/Source/portable/GCC/ARM_CM55_NTZ/non_secure/port.c +++ b/Source/portable/GCC/ARM_CM55_NTZ/non_secure/port.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -68,6 +68,22 @@ #if ( ( configRUN_FREERTOS_SECURE_ONLY == 1 ) && ( configENABLE_TRUSTZONE == 1 ) ) #error TrustZone needs to be disabled in order to run FreeRTOS on the Secure Side. #endif + +/** + * Cortex-M23 does not have non-secure PSPLIM. We should use PSPLIM on Cortex-M23 + * only when FreeRTOS runs on secure side. + */ +#if ( ( portHAS_ARMV8M_MAIN_EXTENSION == 0 ) && ( configRUN_FREERTOS_SECURE_ONLY == 0 ) ) + #define portUSE_PSPLIM_REGISTER 0 +#else + #define portUSE_PSPLIM_REGISTER 1 +#endif +/*-----------------------------------------------------------*/ + +/** + * @brief Prototype of all Interrupt Service Routines (ISRs). + */ +typedef void ( * portISR_t )( void ); /*-----------------------------------------------------------*/ /** @@ -91,10 +107,18 @@ /** * @brief Constants required to manipulate the SCB. */ -#define portSCB_SYS_HANDLER_CTRL_STATE_REG ( *( volatile uint32_t * ) 0xe000ed24 ) +#define portSCB_VTOR_REG ( *( ( portISR_t ** ) 0xe000ed08 ) ) +#define portSCB_SYS_HANDLER_CTRL_STATE_REG ( *( ( volatile uint32_t * ) 0xe000ed24 ) ) #define portSCB_MEM_FAULT_ENABLE_BIT ( 1UL << 16UL ) /*-----------------------------------------------------------*/ +/** + * @brief Constants used to check the installation of the FreeRTOS interrupt handlers. + */ +#define portVECTOR_INDEX_SVC ( 11 ) +#define portVECTOR_INDEX_PENDSV ( 14 ) +/*-----------------------------------------------------------*/ + /** * @brief Constants required to check the validity of an interrupt priority. */ @@ -111,8 +135,8 @@ /** * @brief Constants used during system call enter and exit. */ -#define portPSR_STACK_PADDING_MASK ( 1UL << 9UL ) -#define portEXC_RETURN_STACK_FRAME_TYPE_MASK ( 1UL << 4UL ) +#define portPSR_STACK_PADDING_MASK ( 1UL << 9UL ) +#define portEXC_RETURN_STACK_FRAME_TYPE_MASK ( 1UL << 4UL ) /*-----------------------------------------------------------*/ /** @@ -134,81 +158,81 @@ /** * @brief Offsets in the stack to the parameters when inside the SVC handler. */ -#define portOFFSET_TO_LR ( 5 ) -#define portOFFSET_TO_PC ( 6 ) -#define portOFFSET_TO_PSR ( 7 ) +#define portOFFSET_TO_LR ( 5 ) +#define portOFFSET_TO_PC ( 6 ) +#define portOFFSET_TO_PSR ( 7 ) /*-----------------------------------------------------------*/ /** * @brief Constants required to manipulate the MPU. */ -#define portMPU_TYPE_REG ( *( ( volatile uint32_t * ) 0xe000ed90 ) ) -#define portMPU_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed94 ) ) -#define portMPU_RNR_REG ( *( ( volatile uint32_t * ) 0xe000ed98 ) ) +#define portMPU_TYPE_REG ( *( ( volatile uint32_t * ) 0xe000ed90 ) ) +#define portMPU_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed94 ) ) +#define portMPU_RNR_REG ( *( ( volatile uint32_t * ) 0xe000ed98 ) ) -#define portMPU_RBAR_REG ( *( ( volatile uint32_t * ) 0xe000ed9c ) ) -#define portMPU_RLAR_REG ( *( ( volatile uint32_t * ) 0xe000eda0 ) ) +#define portMPU_RBAR_REG ( *( ( volatile uint32_t * ) 0xe000ed9c ) ) +#define portMPU_RLAR_REG ( *( ( volatile uint32_t * ) 0xe000eda0 ) ) -#define portMPU_RBAR_A1_REG ( *( ( volatile uint32_t * ) 0xe000eda4 ) ) -#define portMPU_RLAR_A1_REG ( *( ( volatile uint32_t * ) 0xe000eda8 ) ) +#define portMPU_RBAR_A1_REG ( *( ( volatile uint32_t * ) 0xe000eda4 ) ) +#define portMPU_RLAR_A1_REG ( *( ( volatile uint32_t * ) 0xe000eda8 ) ) -#define portMPU_RBAR_A2_REG ( *( ( volatile uint32_t * ) 0xe000edac ) ) -#define portMPU_RLAR_A2_REG ( *( ( volatile uint32_t * ) 0xe000edb0 ) ) +#define portMPU_RBAR_A2_REG ( *( ( volatile uint32_t * ) 0xe000edac ) ) +#define portMPU_RLAR_A2_REG ( *( ( volatile uint32_t * ) 0xe000edb0 ) ) -#define portMPU_RBAR_A3_REG ( *( ( volatile uint32_t * ) 0xe000edb4 ) ) -#define portMPU_RLAR_A3_REG ( *( ( volatile uint32_t * ) 0xe000edb8 ) ) +#define portMPU_RBAR_A3_REG ( *( ( volatile uint32_t * ) 0xe000edb4 ) ) +#define portMPU_RLAR_A3_REG ( *( ( volatile uint32_t * ) 0xe000edb8 ) ) -#define portMPU_MAIR0_REG ( *( ( volatile uint32_t * ) 0xe000edc0 ) ) -#define portMPU_MAIR1_REG ( *( ( volatile uint32_t * ) 0xe000edc4 ) ) +#define portMPU_MAIR0_REG ( *( ( volatile uint32_t * ) 0xe000edc0 ) ) +#define portMPU_MAIR1_REG ( *( ( volatile uint32_t * ) 0xe000edc4 ) ) -#define portMPU_RBAR_ADDRESS_MASK ( 0xffffffe0 ) /* Must be 32-byte aligned. */ -#define portMPU_RLAR_ADDRESS_MASK ( 0xffffffe0 ) /* Must be 32-byte aligned. */ +#define portMPU_RBAR_ADDRESS_MASK ( 0xffffffe0 ) /* Must be 32-byte aligned. */ +#define portMPU_RLAR_ADDRESS_MASK ( 0xffffffe0 ) /* Must be 32-byte aligned. */ -#define portMPU_RBAR_ACCESS_PERMISSIONS_MASK ( 3UL << 1UL ) +#define portMPU_RBAR_ACCESS_PERMISSIONS_MASK ( 3UL << 1UL ) -#define portMPU_MAIR_ATTR0_POS ( 0UL ) -#define portMPU_MAIR_ATTR0_MASK ( 0x000000ff ) +#define portMPU_MAIR_ATTR0_POS ( 0UL ) +#define portMPU_MAIR_ATTR0_MASK ( 0x000000ff ) -#define portMPU_MAIR_ATTR1_POS ( 8UL ) -#define portMPU_MAIR_ATTR1_MASK ( 0x0000ff00 ) +#define portMPU_MAIR_ATTR1_POS ( 8UL ) +#define portMPU_MAIR_ATTR1_MASK ( 0x0000ff00 ) -#define portMPU_MAIR_ATTR2_POS ( 16UL ) -#define portMPU_MAIR_ATTR2_MASK ( 0x00ff0000 ) +#define portMPU_MAIR_ATTR2_POS ( 16UL ) +#define portMPU_MAIR_ATTR2_MASK ( 0x00ff0000 ) -#define portMPU_MAIR_ATTR3_POS ( 24UL ) -#define portMPU_MAIR_ATTR3_MASK ( 0xff000000 ) +#define portMPU_MAIR_ATTR3_POS ( 24UL ) +#define portMPU_MAIR_ATTR3_MASK ( 0xff000000 ) -#define portMPU_MAIR_ATTR4_POS ( 0UL ) -#define portMPU_MAIR_ATTR4_MASK ( 0x000000ff ) +#define portMPU_MAIR_ATTR4_POS ( 0UL ) +#define portMPU_MAIR_ATTR4_MASK ( 0x000000ff ) -#define portMPU_MAIR_ATTR5_POS ( 8UL ) -#define portMPU_MAIR_ATTR5_MASK ( 0x0000ff00 ) +#define portMPU_MAIR_ATTR5_POS ( 8UL ) +#define portMPU_MAIR_ATTR5_MASK ( 0x0000ff00 ) -#define portMPU_MAIR_ATTR6_POS ( 16UL ) -#define portMPU_MAIR_ATTR6_MASK ( 0x00ff0000 ) +#define portMPU_MAIR_ATTR6_POS ( 16UL ) +#define portMPU_MAIR_ATTR6_MASK ( 0x00ff0000 ) -#define portMPU_MAIR_ATTR7_POS ( 24UL ) -#define portMPU_MAIR_ATTR7_MASK ( 0xff000000 ) +#define portMPU_MAIR_ATTR7_POS ( 24UL ) +#define portMPU_MAIR_ATTR7_MASK ( 0xff000000 ) -#define portMPU_RLAR_ATTR_INDEX0 ( 0UL << 1UL ) -#define portMPU_RLAR_ATTR_INDEX1 ( 1UL << 1UL ) -#define portMPU_RLAR_ATTR_INDEX2 ( 2UL << 1UL ) -#define portMPU_RLAR_ATTR_INDEX3 ( 3UL << 1UL ) -#define portMPU_RLAR_ATTR_INDEX4 ( 4UL << 1UL ) -#define portMPU_RLAR_ATTR_INDEX5 ( 5UL << 1UL ) -#define portMPU_RLAR_ATTR_INDEX6 ( 6UL << 1UL ) -#define portMPU_RLAR_ATTR_INDEX7 ( 7UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX0 ( 0UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX1 ( 1UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX2 ( 2UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX3 ( 3UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX4 ( 4UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX5 ( 5UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX6 ( 6UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX7 ( 7UL << 1UL ) -#define portMPU_RLAR_REGION_ENABLE ( 1UL ) +#define portMPU_RLAR_REGION_ENABLE ( 1UL ) /* Enable privileged access to unmapped region. */ -#define portMPU_PRIV_BACKGROUND_ENABLE_BIT ( 1UL << 2UL ) +#define portMPU_PRIV_BACKGROUND_ENABLE_BIT ( 1UL << 2UL ) /* Enable MPU. */ -#define portMPU_ENABLE_BIT ( 1UL << 0UL ) +#define portMPU_ENABLE_BIT ( 1UL << 0UL ) /* Expected value of the portMPU_TYPE register. */ -#define portEXPECTED_MPU_TYPE_VALUE ( configTOTAL_MPU_REGIONS << 8UL ) +#define portEXPECTED_MPU_TYPE_VALUE ( configTOTAL_MPU_REGIONS << 8UL ) /* Extract first address of the MPU region as encoded in the * RBAR (Region Base Address Register) value. */ @@ -448,13 +472,13 @@ portDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIV #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) - /** - * @brief Sets up the task stack so that upon returning from - * SVC, the task stack is used again. - * - * @param pulSystemCallStack The current SP when the SVC was raised. - * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler. - */ +/** + * @brief Sets up the task stack so that upon returning from + * SVC, the task stack is used again. + * + * @param pulSystemCallStack The current SP when the SVC was raised. + * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler. + */ void vSystemCallExit( uint32_t * pulSystemCallStack, uint32_t ulLR ) PRIVILEGED_FUNCTION; @@ -462,11 +486,11 @@ portDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIV #if ( configENABLE_MPU == 1 ) - /** - * @brief Checks whether or not the calling task is privileged. - * - * @return pdTRUE if the calling task is privileged, pdFALSE otherwise. - */ +/** + * @brief Checks whether or not the calling task is privileged. + * + * @return pdTRUE if the calling task is privileged, pdFALSE otherwise. + */ BaseType_t xPortIsTaskPrivileged( void ) PRIVILEGED_FUNCTION; #endif /* configENABLE_MPU == 1 */ @@ -501,13 +525,13 @@ PRIVILEGED_DATA static volatile uint32_t ulCriticalNesting = 0xaaaaaaaaUL; * FreeRTOS API functions are not called from interrupts that have been assigned * a priority above configMAX_SYSCALL_INTERRUPT_PRIORITY. */ -#if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) ) +#if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) static uint8_t ucMaxSysCallPriority = 0; static uint32_t ulMaxPRIGROUPValue = 0; static const volatile uint8_t * const pcInterruptPriorityRegisters = ( const volatile uint8_t * ) portNVIC_IP_REGISTERS_OFFSET_16; -#endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) ) */ +#endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */ #if ( configUSE_TICKLESS_IDLE == 1 ) @@ -760,8 +784,15 @@ __attribute__( ( weak ) ) void vPortSetupTimerInterrupt( void ) /* PRIVILEGED_FU } #endif /* configUSE_TICKLESS_IDLE */ - /* Stop and reset the SysTick. */ - portNVIC_SYSTICK_CTRL_REG = 0UL; + /* Stop and reset SysTick. + * + * QEMU versions older than 7.0.0 contain a bug which causes an error if we + * enable SysTick without first selecting a valid clock source. We trigger + * the bug if we change clock sources from a clock with a zero clock period + * to one with a nonzero clock period and enable Systick at the same time. + * So we configure the CLKSOURCE bit here, prior to setting the ENABLE bit. + * This workaround avoids the bug in QEMU versions older than 7.0.0. */ + portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT_CONFIG; portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL; /* Configure SysTick to interrupt at the requested rate. */ @@ -819,6 +850,7 @@ static void prvTaskExitError( void ) static void prvSetupMPU( void ) /* PRIVILEGED_FUNCTION */ { #if defined( __ARMCC_VERSION ) + /* Declaration when these variable are defined in code instead of being * exported from linker scripts. */ extern uint32_t * __privileged_functions_start__; @@ -972,13 +1004,19 @@ void SysTick_Handler( void ) /* PRIVILEGED_FUNCTION */ uint32_t ulPreviousMask; ulPreviousMask = portSET_INTERRUPT_MASK_FROM_ISR(); + traceISR_ENTER(); { /* Increment the RTOS tick. */ if( xTaskIncrementTick() != pdFALSE ) { + traceISR_EXIT_TO_SCHEDULER(); /* Pend a context switch. */ portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; } + else + { + traceISR_EXIT(); + } } portCLEAR_INTERRUPT_MASK_FROM_ISR( ulPreviousMask ); } @@ -988,6 +1026,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO { #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) ) #if defined( __ARMCC_VERSION ) + /* Declaration when these variable are defined in code instead of being * exported from linker scripts. */ extern uint32_t * __syscalls_flash_start__; @@ -1083,18 +1122,24 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO vRestoreContextOfFirstTask(); break; - #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) ) - case portSVC_RAISE_PRIVILEGE: + #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) ) + case portSVC_RAISE_PRIVILEGE: - /* Only raise the privilege, if the svc was raised from any of - * the system calls. */ - if( ( ulPC >= ( uint32_t ) __syscalls_flash_start__ ) && - ( ulPC <= ( uint32_t ) __syscalls_flash_end__ ) ) - { - vRaisePrivilege(); - } - break; - #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) */ + /* Only raise the privilege, if the svc was raised from any of + * the system calls. */ + if( ( ulPC >= ( uint32_t ) __syscalls_flash_start__ ) && + ( ulPC <= ( uint32_t ) __syscalls_flash_end__ ) ) + { + vRaisePrivilege(); + } + break; + #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) */ + + #if ( configENABLE_MPU == 1 ) + case portSVC_YIELD: + vPortYield(); + break; + #endif /* configENABLE_MPU == 1 */ default: /* Incorrect SVC call. */ @@ -1154,12 +1199,11 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO { /* Extended frame i.e. FPU in use. */ ulStackFrameSize = 26; - __asm volatile - ( + __asm volatile ( " vpush {s0} \n" /* Trigger lazy stacking. */ " vpop {s0} \n" /* Nullify the affect of the above instruction. */ ::: "memory" - ); + ); } else { @@ -1171,7 +1215,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO { ulStackFrameSize = 8; } - #endif /* if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */ + #endif /* configENABLE_FPU || configENABLE_MVE */ /* Make space on the system call stack for the stack frame. */ pulSystemCallStack = pulSystemCallStack - ulStackFrameSize; @@ -1187,18 +1231,24 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO * point (i.e. the caller of the MPU_). We need to restore it * when we exit from the system call. */ pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry = pulTaskStack[ portOFFSET_TO_LR ]; - /* Store the value of the PSPLIM register before the SVC was raised. * We need to restore it when we exit from the system call. */ - __asm volatile ( "mrs %0, psplim" : "=r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) ); + #if ( portUSE_PSPLIM_REGISTER == 1 ) + { + __asm volatile ( "mrs %0, psplim" : "=r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) ); + } + #endif /* Use the pulSystemCallStack in thread mode. */ __asm volatile ( "msr psp, %0" : : "r" ( pulSystemCallStack ) ); - __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) ); + #if ( portUSE_PSPLIM_REGISTER == 1 ) + { + __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) ); + } + #endif /* Start executing the system call upon returning from this handler. */ pulSystemCallStack[ portOFFSET_TO_PC ] = uxSystemCallImplementations[ ucSystemCallNumber ]; - /* Raise a request to exit from the system call upon finishing the * system call. */ pulSystemCallStack[ portOFFSET_TO_LR ] = ( uint32_t ) vRequestSystemCallExit; @@ -1224,14 +1274,13 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO pulSystemCallStack[ portOFFSET_TO_PSR ] &= ( ~portPSR_STACK_PADDING_MASK ); /* Raise the privilege for the duration of the system call. */ - __asm volatile - ( + __asm volatile ( " mrs r0, control \n" /* Obtain current control value. */ " movs r1, #1 \n" /* r1 = 1. */ " bics r0, r1 \n" /* Clear nPRIV bit. */ " msr control, r0 \n" /* Write back new control value. */ ::: "r0", "r1", "memory" - ); + ); } } @@ -1293,12 +1342,11 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO { /* Extended frame i.e. FPU in use. */ ulStackFrameSize = 26; - __asm volatile - ( + __asm volatile ( " vpush {s0} \n" /* Trigger lazy stacking. */ " vpop {s0} \n" /* Nullify the affect of the above instruction. */ ::: "memory" - ); + ); } else { @@ -1310,7 +1358,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO { ulStackFrameSize = 8; } - #endif /* if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */ + #endif /* configENABLE_FPU || configENABLE_MVE */ /* Make space on the task stack for the stack frame. */ pulTaskStack = pulTaskStack - ulStackFrameSize; @@ -1332,7 +1380,11 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO /* Restore the PSPLIM register to what it was at the time of * system call entry. */ - __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) ); + #if ( portUSE_PSPLIM_REGISTER == 1 ) + { + __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) ); + } + #endif /* If the hardware used padding to force the stack pointer * to be double word aligned, set the stacked xPSR bit[9], @@ -1350,14 +1402,13 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO pxMpuSettings->xSystemCallStackInfo.pulTaskStack = NULL; /* Drop the privilege before returning to the thread mode. */ - __asm volatile - ( + __asm volatile ( " mrs r0, control \n" /* Obtain current control value. */ " movs r1, #1 \n" /* r1 = 1. */ " orrs r0, r1 \n" /* Set nPRIV bit. */ " msr control, r0 \n" /* Write back new control value. */ ::: "r0", "r1", "memory" - ); + ); } } @@ -1410,21 +1461,21 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO xMPUSettings->ulContext[ ulIndex ] = 0x11111111; /* r11. */ ulIndex++; - xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pvParameters; /* r0. */ + xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pvParameters; /* r0. */ ulIndex++; - xMPUSettings->ulContext[ ulIndex ] = 0x01010101; /* r1. */ + xMPUSettings->ulContext[ ulIndex ] = 0x01010101; /* r1. */ ulIndex++; - xMPUSettings->ulContext[ ulIndex ] = 0x02020202; /* r2. */ + xMPUSettings->ulContext[ ulIndex ] = 0x02020202; /* r2. */ ulIndex++; - xMPUSettings->ulContext[ ulIndex ] = 0x03030303; /* r3. */ + xMPUSettings->ulContext[ ulIndex ] = 0x03030303; /* r3. */ ulIndex++; - xMPUSettings->ulContext[ ulIndex ] = 0x12121212; /* r12. */ + xMPUSettings->ulContext[ ulIndex ] = 0x12121212; /* r12. */ ulIndex++; xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portTASK_RETURN_ADDRESS; /* LR. */ ulIndex++; - xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxCode; /* PC. */ + xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxCode; /* PC. */ ulIndex++; - xMPUSettings->ulContext[ ulIndex ] = portINITIAL_XPSR; /* xPSR. */ + xMPUSettings->ulContext[ ulIndex ] = portINITIAL_XPSR; /* xPSR. */ ulIndex++; #if ( configENABLE_TRUSTZONE == 1 ) @@ -1435,8 +1486,9 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO #endif /* configENABLE_TRUSTZONE */ xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) ( pxTopOfStack - 8 ); /* PSP with the hardware saved stack. */ ulIndex++; - xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxEndOfStack; /* PSPLIM. */ + xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxEndOfStack; /* PSPLIM. */ ulIndex++; + if( xRunPrivileged == pdTRUE ) { xMPUSettings->ulTaskFlags |= portTASK_IS_PRIVILEGED_FLAG; @@ -1449,6 +1501,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portINITIAL_CONTROL_UNPRIVILEGED; /* CONTROL. */ ulIndex++; } + xMPUSettings->ulContext[ ulIndex ] = portINITIAL_EXC_RETURN; /* LR (EXC_RETURN). */ ulIndex++; @@ -1483,7 +1536,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO * interrupt. */ #if ( portPRELOAD_REGISTERS == 0 ) { - pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */ + pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */ *pxTopOfStack = portINITIAL_XPSR; /* xPSR. */ pxTopOfStack--; *pxTopOfStack = ( StackType_t ) pxCode; /* PC. */ @@ -1505,7 +1558,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO } #else /* portPRELOAD_REGISTERS */ { - pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */ + pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */ *pxTopOfStack = portINITIAL_XPSR; /* xPSR. */ pxTopOfStack--; *pxTopOfStack = ( StackType_t ) pxCode; /* PC. */ @@ -1540,7 +1593,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO pxTopOfStack--; *pxTopOfStack = portINITIAL_EXC_RETURN; /* EXC_RETURN. */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */ + *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */ #if ( configENABLE_TRUSTZONE == 1 ) { @@ -1559,22 +1612,52 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */ { - #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) ) + /* An application can install FreeRTOS interrupt handlers in one of the + * folllowing ways: + * 1. Direct Routing - Install the functions SVC_Handler and PendSV_Handler + * for SVCall and PendSV interrupts respectively. + * 2. Indirect Routing - Install separate handlers for SVCall and PendSV + * interrupts and route program control from those handlers to + * SVC_Handler and PendSV_Handler functions. + * + * Applications that use Indirect Routing must set + * configCHECK_HANDLER_INSTALLATION to 0 in their FreeRTOSConfig.h. Direct + * routing, which is validated here when configCHECK_HANDLER_INSTALLATION + * is 1, should be preferred when possible. */ + #if ( configCHECK_HANDLER_INSTALLATION == 1 ) + { + const portISR_t * const pxVectorTable = portSCB_VTOR_REG; + + /* Validate that the application has correctly installed the FreeRTOS + * handlers for SVCall and PendSV interrupts. We do not check the + * installation of the SysTick handler because the application may + * choose to drive the RTOS tick using a timer other than the SysTick + * timer by overriding the weak function vPortSetupTimerInterrupt(). + * + * Assertion failures here indicate incorrect installation of the + * FreeRTOS handlers. For help installing the FreeRTOS handlers, see + * https://www.FreeRTOS.org/FAQHelp.html. + * + * Systems with a configurable address for the interrupt vector table + * can also encounter assertion failures or even system faults here if + * VTOR is not set correctly to point to the application's vector table. */ + configASSERT( pxVectorTable[ portVECTOR_INDEX_SVC ] == SVC_Handler ); + configASSERT( pxVectorTable[ portVECTOR_INDEX_PENDSV ] == PendSV_Handler ); + } + #endif /* configCHECK_HANDLER_INSTALLATION */ + + #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) { - volatile uint32_t ulOriginalPriority; volatile uint32_t ulImplementedPrioBits = 0; volatile uint8_t ucMaxPriorityValue; /* Determine the maximum priority from which ISR safe FreeRTOS API - * functions can be called. ISR safe functions are those that end in - * "FromISR". FreeRTOS maintains separate thread and ISR API functions to + * functions can be called. ISR safe functions are those that end in + * "FromISR". FreeRTOS maintains separate thread and ISR API functions to * ensure interrupt entry is as fast and simple as possible. * - * Save the interrupt priority value that is about to be clobbered. */ - ulOriginalPriority = portNVIC_SHPR2_REG; - - /* Determine the number of priority bits available. First write to all - * possible bits. */ + * First, determine the number of priority bits available. Write to all + * possible bits in the priority setting for SVCall. */ portNVIC_SHPR2_REG = 0xFF000000; /* Read the value back to see how many bits stuck. */ @@ -1593,11 +1676,10 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */ /* Check that the bits not implemented in hardware are zero in * configMAX_SYSCALL_INTERRUPT_PRIORITY. */ - configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( ~ucMaxPriorityValue ) ) == 0U ); + configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( uint8_t ) ( ~( uint32_t ) ucMaxPriorityValue ) ) == 0U ); /* Calculate the maximum acceptable priority group value for the number * of bits read back. */ - while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE ) { ulImplementedPrioBits++; @@ -1635,16 +1717,14 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */ * register. */ ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT; ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK; - - /* Restore the clobbered interrupt priority register to its original - * value. */ - portNVIC_SHPR2_REG = ulOriginalPriority; } - #endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) ) */ + #endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */ - /* Make PendSV, CallSV and SysTick the same priority as the kernel. */ + /* Make PendSV and SysTick the lowest priority interrupts, and make SVCall + * the highest priority. */ portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI; portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI; + portNVIC_SHPR2_REG = 0; #if ( configENABLE_MPU == 1 ) { @@ -1701,6 +1781,7 @@ void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */ int32_t lIndex = 0; #if defined( __ARMCC_VERSION ) + /* Declaration when these variable are defined in code instead of being * exported from linker scripts. */ extern uint32_t * __privileged_sram_start__; @@ -1886,7 +1967,7 @@ BaseType_t xPortIsInsideInterrupt( void ) } /*-----------------------------------------------------------*/ -#if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) ) +#if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) void vPortValidateInterruptPriority( void ) { @@ -1944,7 +2025,7 @@ BaseType_t xPortIsInsideInterrupt( void ) configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue ); } -#endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) ) */ +#endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */ /*-----------------------------------------------------------*/ #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) diff --git a/Source/portable/GCC/ARM_CM55_NTZ/non_secure/portasm.c b/Source/portable/GCC/ARM_CM55_NTZ/non_secure/portasm.c index b3f6a0aac..6169b9358 100644 --- a/Source/portable/GCC/ARM_CM55_NTZ/non_secure/portasm.c +++ b/Source/portable/GCC/ARM_CM55_NTZ/non_secure/portasm.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -75,16 +75,16 @@ " ldmia r0!, {r4-r11} \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */ " stmia r2, {r4-r11} \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */ " \n" - #if ( configTOTAL_MPU_REGIONS == 16 ) - " movs r3, #8 \n" /* r3 = 8. */ - " str r3, [r1] \n" /* Program RNR = 8. */ - " ldmia r0!, {r4-r11} \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */ - " stmia r2, {r4-r11} \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */ - " movs r3, #12 \n" /* r3 = 12. */ - " str r3, [r1] \n" /* Program RNR = 12. */ - " ldmia r0!, {r4-r11} \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */ - " stmia r2, {r4-r11} \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */ - #endif /* configTOTAL_MPU_REGIONS == 16 */ + #if ( configTOTAL_MPU_REGIONS == 16 ) + " movs r3, #8 \n" /* r3 = 8. */ + " str r3, [r1] \n" /* Program RNR = 8. */ + " ldmia r0!, {r4-r11} \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */ + " stmia r2, {r4-r11} \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */ + " movs r3, #12 \n" /* r3 = 12. */ + " str r3, [r1] \n" /* Program RNR = 12. */ + " ldmia r0!, {r4-r11} \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */ + " stmia r2, {r4-r11} \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */ + #endif /* configTOTAL_MPU_REGIONS == 16 */ " \n" " ldr r1, xMPUCTRLConst2 \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */ " ldr r2, [r1] \n" /* Read the value of MPU_CTRL. */ @@ -273,15 +273,15 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att " mrs r2, psp \n" /* r2 = PSP. */ " \n" " save_general_regs: \n" - #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) - " add r2, r2, #0x20 \n" /* Move r2 to location where s0 is saved. */ - " tst lr, #0x10 \n" - " ittt eq \n" - " vstmiaeq r1!, {s16-s31} \n" /* Store s16-s31. */ - " vldmiaeq r2, {s0-s16} \n" /* Copy hardware saved FP context into s0-s16. */ - " vstmiaeq r1!, {s0-s16} \n" /* Store hardware saved FP context. */ - " sub r2, r2, #0x20 \n" /* Set r2 back to the location of hardware saved context. */ - #endif /* configENABLE_FPU || configENABLE_MVE */ + #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) + " add r2, r2, #0x20 \n" /* Move r2 to location where s0 is saved. */ + " tst lr, #0x10 \n" + " ittt eq \n" + " vstmiaeq r1!, {s16-s31} \n" /* Store s16-s31. */ + " vldmiaeq r2, {s0-s16} \n" /* Copy hardware saved FP context into s0-s16. */ + " vstmiaeq r1!, {s0-s16} \n" /* Store hardware saved FP context. */ + " sub r2, r2, #0x20 \n" /* Set r2 back to the location of hardware saved context. */ + #endif /* configENABLE_FPU || configENABLE_MVE */ " \n" " stmia r1!, {r4-r11} \n" /* Store r4-r11. */ " ldmia r2, {r4-r11} \n" /* Copy the hardware saved context into r4-r11. */ @@ -326,16 +326,16 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att " ldmia r0!, {r4-r11} \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */ " stmia r2, {r4-r11} \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */ " \n" - #if ( configTOTAL_MPU_REGIONS == 16 ) - " movs r3, #8 \n" /* r3 = 8. */ - " str r3, [r1] \n" /* Program RNR = 8. */ - " ldmia r0!, {r4-r11} \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */ - " stmia r2, {r4-r11} \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */ - " movs r3, #12 \n" /* r3 = 12. */ - " str r3, [r1] \n" /* Program RNR = 12. */ - " ldmia r0!, {r4-r11} \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */ - " stmia r2, {r4-r11} \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */ - #endif /* configTOTAL_MPU_REGIONS == 16 */ + #if ( configTOTAL_MPU_REGIONS == 16 ) + " movs r3, #8 \n" /* r3 = 8. */ + " str r3, [r1] \n" /* Program RNR = 8. */ + " ldmia r0!, {r4-r11} \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */ + " stmia r2, {r4-r11} \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */ + " movs r3, #12 \n" /* r3 = 12. */ + " str r3, [r1] \n" /* Program RNR = 12. */ + " ldmia r0!, {r4-r11} \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */ + " stmia r2, {r4-r11} \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */ + #endif /* configTOTAL_MPU_REGIONS == 16 */ " \n" " ldr r1, xMPUCTRLConst \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */ " ldr r2, [r1] \n" /* Read the value of MPU_CTRL. */ @@ -358,13 +358,13 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att " ldmdb r1!, {r4-r11} \n" /* r4-r11 contain hardware saved context. */ " stmia r2!, {r4-r11} \n" /* Copy the hardware saved context on the task stack. */ " ldmdb r1!, {r4-r11} \n" /* r4-r11 restored. */ - #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) - " tst lr, #0x10 \n" - " ittt eq \n" - " vldmdbeq r1!, {s0-s16} \n" /* s0-s16 contain hardware saved FP context. */ - " vstmiaeq r2!, {s0-s16} \n" /* Copy hardware saved FP context on the task stack. */ - " vldmdbeq r1!, {s16-s31} \n" /* Restore s16-s31. */ - #endif /* configENABLE_FPU || configENABLE_MVE */ + #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) + " tst lr, #0x10 \n" + " ittt eq \n" + " vldmdbeq r1!, {s0-s16} \n" /* s0-s16 contain hardware saved FP context. */ + " vstmiaeq r2!, {s0-s16} \n" /* Copy hardware saved FP context on the task stack. */ + " vldmdbeq r1!, {s16-s31} \n" /* Restore s16-s31. */ + #endif /* configENABLE_FPU || configENABLE_MVE */ " \n" " restore_context_done: \n" " str r1, [r0] \n" /* Save the location where the context should be saved next as the first member of TCB. */ @@ -390,11 +390,11 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att " \n" " mrs r0, psp \n" /* Read PSP in r0. */ " \n" - #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) - " tst lr, #0x10 \n" /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */ - " it eq \n" - " vstmdbeq r0!, {s16-s31} \n" /* Store the additional FP context registers which are not saved automatically. */ - #endif /* configENABLE_FPU || configENABLE_MVE */ + #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) + " tst lr, #0x10 \n" /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */ + " it eq \n" + " vstmdbeq r0!, {s16-s31} \n" /* Store the additional FP context registers which are not saved automatically. */ + #endif /* configENABLE_FPU || configENABLE_MVE */ " \n" " mrs r2, psplim \n" /* r2 = PSPLIM. */ " mov r3, lr \n" /* r3 = LR/EXC_RETURN. */ @@ -418,11 +418,11 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att " \n" " ldmia r0!, {r2-r11} \n" /* Read from stack - r2 = PSPLIM, r3 = LR and r4-r11 restored. */ " \n" - #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) - " tst r3, #0x10 \n" /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */ - " it eq \n" - " vldmiaeq r0!, {s16-s31} \n" /* Restore the additional FP context registers which are not restored automatically. */ - #endif /* configENABLE_FPU || configENABLE_MVE */ + #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) + " tst r3, #0x10 \n" /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */ + " it eq \n" + " vldmiaeq r0!, {s16-s31} \n" /* Restore the additional FP context registers which are not restored automatically. */ + #endif /* configENABLE_FPU || configENABLE_MVE */ " \n" " msr psplim, r2 \n" /* Restore the PSPLIM register value for the task. */ " msr psp, r0 \n" /* Remember the new top of stack for the task. */ diff --git a/Source/portable/GCC/ARM_CM55_NTZ/non_secure/portasm.h b/Source/portable/GCC/ARM_CM55_NTZ/non_secure/portasm.h index f64ceb525..c6d2ebd58 100644 --- a/Source/portable/GCC/ARM_CM55_NTZ/non_secure/portasm.h +++ b/Source/portable/GCC/ARM_CM55_NTZ/non_secure/portasm.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/Source/portable/GCC/ARM_CM55_NTZ/non_secure/portmacro.h b/Source/portable/GCC/ARM_CM55_NTZ/non_secure/portmacro.h index 880205cb1..9f2bdb433 100644 --- a/Source/portable/GCC/ARM_CM55_NTZ/non_secure/portmacro.h +++ b/Source/portable/GCC/ARM_CM55_NTZ/non_secure/portmacro.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -53,9 +53,9 @@ /** * Architecture specifics. */ -#define portARCH_NAME "Cortex-M55" -#define portHAS_BASEPRI 1 -#define portDONT_DISCARD __attribute__( ( used ) ) +#define portARCH_NAME "Cortex-M55" +#define portHAS_ARMV8M_MAIN_EXTENSION 1 +#define portDONT_DISCARD __attribute__( ( used ) ) /*-----------------------------------------------------------*/ /* ARMv8-M common port configurations. */ @@ -65,8 +65,8 @@ /** * @brief Critical section management. */ -#define portDISABLE_INTERRUPTS() ulSetInterruptMask() -#define portENABLE_INTERRUPTS() vClearInterruptMask( 0 ) +#define portDISABLE_INTERRUPTS() ulSetInterruptMask() +#define portENABLE_INTERRUPTS() vClearInterruptMask( 0 ) /*-----------------------------------------------------------*/ /* *INDENT-OFF* */ diff --git a/Source/portable/GCC/ARM_CM55_NTZ/non_secure/portmacrocommon.h b/Source/portable/GCC/ARM_CM55_NTZ/non_secure/portmacrocommon.h index 6f666da22..33f21d85b 100644 --- a/Source/portable/GCC/ARM_CM55_NTZ/non_secure/portmacrocommon.h +++ b/Source/portable/GCC/ARM_CM55_NTZ/non_secure/portmacrocommon.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -117,7 +117,7 @@ extern uint32_t ulSetInterruptMask( void ) /* __attribute__(( naked )) PRIVILEGE extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */; #if ( configENABLE_TRUSTZONE == 1 ) - extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize ); /* __attribute__ (( naked )) */ + extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize ); /* __attribute__ (( naked )) */ extern void vPortFreeSecureContext( uint32_t * pulTCB ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */; #endif /* configENABLE_TRUSTZONE */ @@ -188,13 +188,13 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P #if ( configENABLE_MPU == 1 ) - /** - * @brief Settings to define an MPU region. - */ +/** + * @brief Settings to define an MPU region. + */ typedef struct MPURegionSettings { - uint32_t ulRBAR; /**< RBAR for the region. */ - uint32_t ulRLAR; /**< RLAR for the region. */ + uint32_t ulRBAR; /**< RBAR for the region. */ + uint32_t ulRLAR; /**< RLAR for the region. */ } MPURegionSettings_t; #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) @@ -203,9 +203,9 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P #error configSYSTEM_CALL_STACK_SIZE must be defined to the desired size of the system call stack in words for using MPU wrappers v2. #endif - /** - * @brief System call stack. - */ +/** + * @brief System call stack. + */ typedef struct SYSTEM_CALL_STACK_INFO { uint32_t ulSystemCallStackBuffer[ configSYSTEM_CALL_STACK_SIZE ]; @@ -218,74 +218,74 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P #endif /* configUSE_MPU_WRAPPERS_V1 == 0 */ - /** - * @brief MPU settings as stored in the TCB. - */ +/** + * @brief MPU settings as stored in the TCB. + */ #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) - #if( configENABLE_TRUSTZONE == 1 ) + #if ( configENABLE_TRUSTZONE == 1 ) - /* - * +-----------+---------------+----------+-----------------+------------------------------+-----+ - * | s16-s31 | s0-s15, FPSCR | r4-r11 | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, | | - * | | | | PC, xPSR | CONTROL, EXC_RETURN | | - * +-----------+---------------+----------+-----------------+------------------------------+-----+ - * - * <-----------><--------------><---------><----------------><-----------------------------><----> - * 16 16 8 8 5 1 - */ - #define MAX_CONTEXT_SIZE 54 +/* + * +-----------+---------------+----------+-----------------+------------------------------+-----+ + * | s16-s31 | s0-s15, FPSCR | r4-r11 | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, | | + * | | | | PC, xPSR | CONTROL, EXC_RETURN | | + * +-----------+---------------+----------+-----------------+------------------------------+-----+ + * + * <-----------><--------------><---------><----------------><-----------------------------><----> + * 16 16 8 8 5 1 + */ + #define MAX_CONTEXT_SIZE 54 #else /* #if( configENABLE_TRUSTZONE == 1 ) */ - /* - * +-----------+---------------+----------+-----------------+----------------------+-----+ - * | s16-s31 | s0-s15, FPSCR | r4-r11 | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL | | - * | | | | PC, xPSR | EXC_RETURN | | - * +-----------+---------------+----------+-----------------+----------------------+-----+ - * - * <-----------><--------------><---------><----------------><---------------------><----> - * 16 16 8 8 4 1 - */ - #define MAX_CONTEXT_SIZE 53 +/* + * +-----------+---------------+----------+-----------------+----------------------+-----+ + * | s16-s31 | s0-s15, FPSCR | r4-r11 | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL | | + * | | | | PC, xPSR | EXC_RETURN | | + * +-----------+---------------+----------+-----------------+----------------------+-----+ + * + * <-----------><--------------><---------><----------------><---------------------><----> + * 16 16 8 8 4 1 + */ + #define MAX_CONTEXT_SIZE 53 #endif /* #if( configENABLE_TRUSTZONE == 1 ) */ #else /* #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */ - #if( configENABLE_TRUSTZONE == 1 ) + #if ( configENABLE_TRUSTZONE == 1 ) - /* - * +----------+-----------------+------------------------------+-----+ - * | r4-r11 | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, | | - * | | PC, xPSR | CONTROL, EXC_RETURN | | - * +----------+-----------------+------------------------------+-----+ - * - * <---------><----------------><------------------------------><----> - * 8 8 5 1 - */ - #define MAX_CONTEXT_SIZE 22 +/* + * +----------+-----------------+------------------------------+-----+ + * | r4-r11 | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, | | + * | | PC, xPSR | CONTROL, EXC_RETURN | | + * +----------+-----------------+------------------------------+-----+ + * + * <---------><----------------><------------------------------><----> + * 8 8 5 1 + */ + #define MAX_CONTEXT_SIZE 22 #else /* #if( configENABLE_TRUSTZONE == 1 ) */ - /* - * +----------+-----------------+----------------------+-----+ - * | r4-r11 | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL | | - * | | PC, xPSR | EXC_RETURN | | - * +----------+-----------------+----------------------+-----+ - * - * <---------><----------------><----------------------><----> - * 8 8 4 1 - */ - #define MAX_CONTEXT_SIZE 21 +/* + * +----------+-----------------+----------------------+-----+ + * | r4-r11 | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL | | + * | | PC, xPSR | EXC_RETURN | | + * +----------+-----------------+----------------------+-----+ + * + * <---------><----------------><----------------------><----> + * 8 8 4 1 + */ + #define MAX_CONTEXT_SIZE 21 #endif /* #if( configENABLE_TRUSTZONE == 1 ) */ #endif /* #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */ - /* Flags used for xMPU_SETTINGS.ulTaskFlags member. */ - #define portSTACK_FRAME_HAS_PADDING_FLAG ( 1UL << 0UL ) - #define portTASK_IS_PRIVILEGED_FLAG ( 1UL << 1UL ) +/* Flags used for xMPU_SETTINGS.ulTaskFlags member. */ + #define portSTACK_FRAME_HAS_PADDING_FLAG ( 1UL << 0UL ) + #define portTASK_IS_PRIVILEGED_FLAG ( 1UL << 1UL ) /* Size of an Access Control List (ACL) entry in bits. */ #define portACL_ENTRY_SIZE_BITS ( 32U ) @@ -313,7 +313,7 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P * system calls. */ #ifdef configASSERT - #if ( portHAS_BASEPRI == 1 ) + #if ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) void vPortValidateInterruptPriority( void ); #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() vPortValidateInterruptPriority() #endif @@ -333,12 +333,29 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P /** * @brief Scheduler utilities. */ -#define portYIELD() vPortYield() +#if ( configENABLE_MPU == 1 ) + #define portYIELD() __asm volatile ( "svc %0" ::"i" ( portSVC_YIELD ) : "memory" ) + #define portYIELD_WITHIN_API() vPortYield() +#else + #define portYIELD() vPortYield() + #define portYIELD_WITHIN_API() vPortYield() +#endif + #define portNVIC_INT_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed04 ) ) #define portNVIC_PENDSVSET_BIT ( 1UL << 28UL ) -#define portEND_SWITCHING_ISR( xSwitchRequired ) \ - do { if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; } \ - while( 0 ) +#define portEND_SWITCHING_ISR( xSwitchRequired ) \ + do \ + { \ + if( xSwitchRequired ) \ + { \ + traceISR_EXIT_TO_SCHEDULER(); \ + portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; \ + } \ + else \ + { \ + traceISR_EXIT(); \ + } \ + } while( 0 ) #define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x ) /*-----------------------------------------------------------*/ @@ -424,12 +441,12 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P extern BaseType_t xPortIsTaskPrivileged( void ); - /** - * @brief Checks whether or not the calling task is privileged. - * - * @return pdTRUE if the calling task is privileged, pdFALSE otherwise. - */ - #define portIS_TASK_PRIVILEGED() xPortIsTaskPrivileged() +/** + * @brief Checks whether or not the calling task is privileged. + * + * @return pdTRUE if the calling task is privileged, pdFALSE otherwise. + */ + #define portIS_TASK_PRIVILEGED() xPortIsTaskPrivileged() #endif /* configENABLE_MPU == 1 */ /*-----------------------------------------------------------*/ @@ -440,6 +457,56 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P #define portMEMORY_BARRIER() __asm volatile ( "" ::: "memory" ) /*-----------------------------------------------------------*/ +/* Select correct value of configUSE_PORT_OPTIMISED_TASK_SELECTION + * based on whether or not Mainline extension is implemented. */ +#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION + #if ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) + #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1 + #else + #define configUSE_PORT_OPTIMISED_TASK_SELECTION 0 + #endif +#endif /* #ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION */ + +/** + * @brief Port-optimised task selection. + */ +#if ( configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 ) + +/** + * @brief Count the number of leading zeros in a 32-bit value. + */ + static portFORCE_INLINE uint32_t ulPortCountLeadingZeros( uint32_t ulBitmap ) + { + uint32_t ulReturn; + + __asm volatile ( "clz %0, %1" : "=r" ( ulReturn ) : "r" ( ulBitmap ) : "memory" ); + + return ulReturn; + } + +/* Check the configuration. */ + #if ( configMAX_PRIORITIES > 32 ) + #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 different priorities as tasks that share a priority will time slice. + #endif + + #if ( portHAS_ARMV8M_MAIN_EXTENSION == 0 ) + #error ARMv8-M baseline implementations (such as Cortex-M23) do not support port-optimised task selection. Please set configUSE_PORT_OPTIMISED_TASK_SELECTION to 0 or leave it undefined. + #endif + +/** + * @brief Store/clear the ready priorities in a bit map. + */ + #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) ) + #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) ) + +/** + * @brief Get the priority of the highest-priority task that is ready to execute. + */ + #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - ulPortCountLeadingZeros( ( uxReadyPriorities ) ) ) + +#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */ +/*-----------------------------------------------------------*/ + /* *INDENT-OFF* */ #ifdef __cplusplus } diff --git a/Source/portable/GCC/ARM_CM7/r0p1/port.c b/Source/portable/GCC/ARM_CM7/r0p1/port.c index afd4baa8e..4fc3a0650 100644 --- a/Source/portable/GCC/ARM_CM7/r0p1/port.c +++ b/Source/portable/GCC/ARM_CM7/r0p1/port.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -38,10 +38,14 @@ #error This port can only be used when the project options are configured to enable hardware floating point support. #endif +/* Prototype of all Interrupt Service Routines (ISRs). */ +typedef void ( * portISR_t )( void ); + /* Constants required to manipulate the core. Registers first... */ #define portNVIC_SYSTICK_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000e010 ) ) #define portNVIC_SYSTICK_LOAD_REG ( *( ( volatile uint32_t * ) 0xe000e014 ) ) #define portNVIC_SYSTICK_CURRENT_VALUE_REG ( *( ( volatile uint32_t * ) 0xe000e018 ) ) +#define portNVIC_SHPR2_REG ( *( ( volatile uint32_t * ) 0xe000ed1c ) ) #define portNVIC_SHPR3_REG ( *( ( volatile uint32_t * ) 0xe000ed20 ) ) /* ...then bits in the registers. */ #define portNVIC_SYSTICK_CLK_BIT ( 1UL << 2UL ) @@ -56,6 +60,11 @@ #define portNVIC_PENDSV_PRI ( ( ( uint32_t ) portMIN_INTERRUPT_PRIORITY ) << 16UL ) #define portNVIC_SYSTICK_PRI ( ( ( uint32_t ) portMIN_INTERRUPT_PRIORITY ) << 24UL ) +/* Constants used to check the installation of the FreeRTOS interrupt handlers. */ +#define portSCB_VTOR_REG ( *( ( portISR_t ** ) 0xE000ED08 ) ) +#define portVECTOR_INDEX_SVC ( 11 ) +#define portVECTOR_INDEX_PENDSV ( 14 ) + /* Constants required to check the validity of an interrupt priority. */ #define portFIRST_USER_INTERRUPT_NUMBER ( 16 ) #define portNVIC_IP_REGISTERS_OFFSET_16 ( 0xE000E3F0 ) @@ -290,6 +299,40 @@ static void prvPortStartFirstTask( void ) */ BaseType_t xPortStartScheduler( void ) { + /* An application can install FreeRTOS interrupt handlers in one of the + * folllowing ways: + * 1. Direct Routing - Install the functions vPortSVCHandler and + * xPortPendSVHandler for SVCall and PendSV interrupts respectively. + * 2. Indirect Routing - Install separate handlers for SVCall and PendSV + * interrupts and route program control from those handlers to + * vPortSVCHandler and xPortPendSVHandler functions. + * + * Applications that use Indirect Routing must set + * configCHECK_HANDLER_INSTALLATION to 0 in their FreeRTOSConfig.h. Direct + * routing, which is validated here when configCHECK_HANDLER_INSTALLATION + * is 1, should be preferred when possible. */ + #if ( configCHECK_HANDLER_INSTALLATION == 1 ) + { + const portISR_t * const pxVectorTable = portSCB_VTOR_REG; + + /* Validate that the application has correctly installed the FreeRTOS + * handlers for SVCall and PendSV interrupts. We do not check the + * installation of the SysTick handler because the application may + * choose to drive the RTOS tick using a timer other than the SysTick + * timer by overriding the weak function vPortSetupTimerInterrupt(). + * + * Assertion failures here indicate incorrect installation of the + * FreeRTOS handlers. For help installing the FreeRTOS handlers, see + * https://www.FreeRTOS.org/FAQHelp.html. + * + * Systems with a configurable address for the interrupt vector table + * can also encounter assertion failures or even system faults here if + * VTOR is not set correctly to point to the application's vector table. */ + configASSERT( pxVectorTable[ portVECTOR_INDEX_SVC ] == vPortSVCHandler ); + configASSERT( pxVectorTable[ portVECTOR_INDEX_PENDSV ] == xPortPendSVHandler ); + } + #endif /* configCHECK_HANDLER_INSTALLATION */ + #if ( configASSERT_DEFINED == 1 ) { volatile uint8_t ucOriginalPriority; @@ -339,22 +382,22 @@ BaseType_t xPortStartScheduler( void ) if( ulImplementedPrioBits == 8 ) { /* When the hardware implements 8 priority bits, there is no way for - * the software to configure PRIGROUP to not have sub-priorities. As - * a result, the least significant bit is always used for sub-priority - * and there are 128 preemption priorities and 2 sub-priorities. - * - * This may cause some confusion in some cases - for example, if - * configMAX_SYSCALL_INTERRUPT_PRIORITY is set to 5, both 5 and 4 - * priority interrupts will be masked in Critical Sections as those - * are at the same preemption priority. This may appear confusing as - * 4 is higher (numerically lower) priority than - * configMAX_SYSCALL_INTERRUPT_PRIORITY and therefore, should not - * have been masked. Instead, if we set configMAX_SYSCALL_INTERRUPT_PRIORITY - * to 4, this confusion does not happen and the behaviour remains the same. - * - * The following assert ensures that the sub-priority bit in the - * configMAX_SYSCALL_INTERRUPT_PRIORITY is clear to avoid the above mentioned - * confusion. */ + * the software to configure PRIGROUP to not have sub-priorities. As + * a result, the least significant bit is always used for sub-priority + * and there are 128 preemption priorities and 2 sub-priorities. + * + * This may cause some confusion in some cases - for example, if + * configMAX_SYSCALL_INTERRUPT_PRIORITY is set to 5, both 5 and 4 + * priority interrupts will be masked in Critical Sections as those + * are at the same preemption priority. This may appear confusing as + * 4 is higher (numerically lower) priority than + * configMAX_SYSCALL_INTERRUPT_PRIORITY and therefore, should not + * have been masked. Instead, if we set configMAX_SYSCALL_INTERRUPT_PRIORITY + * to 4, this confusion does not happen and the behaviour remains the same. + * + * The following assert ensures that the sub-priority bit in the + * configMAX_SYSCALL_INTERRUPT_PRIORITY is clear to avoid the above mentioned + * confusion. */ configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & 0x1U ) == 0U ); ulMaxPRIGROUPValue = 0; } @@ -374,9 +417,11 @@ BaseType_t xPortStartScheduler( void ) } #endif /* configASSERT_DEFINED */ - /* Make PendSV and SysTick the lowest priority interrupts. */ + /* Make PendSV and SysTick the lowest priority interrupts, and make SVCall + * the highest priority. */ portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI; portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI; + portNVIC_SHPR2_REG = 0; /* Start the timer that generates the tick ISR. Interrupts are disabled * here already. */ @@ -511,14 +556,21 @@ void xPortSysTickHandler( void ) * save and then restore the interrupt mask value as its value is already * known. */ portDISABLE_INTERRUPTS(); + traceISR_ENTER(); { /* Increment the RTOS tick. */ if( xTaskIncrementTick() != pdFALSE ) { + traceISR_EXIT_TO_SCHEDULER(); + /* A context switch is required. Context switching is performed in * the PendSV interrupt. Pend the PendSV interrupt. */ portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; } + else + { + traceISR_EXIT(); + } } portENABLE_INTERRUPTS(); } diff --git a/Source/portable/GCC/ARM_CM7/r0p1/portmacro.h b/Source/portable/GCC/ARM_CM7/r0p1/portmacro.h index 8f08bd072..da91837da 100644 --- a/Source/portable/GCC/ARM_CM7/r0p1/portmacro.h +++ b/Source/portable/GCC/ARM_CM7/r0p1/portmacro.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -28,7 +28,7 @@ #ifndef PORTMACRO_H - #define PORTMACRO_H +#define PORTMACRO_H /* *INDENT-OFF* */ #ifdef __cplusplus @@ -47,42 +47,42 @@ */ /* Type definitions. */ - #define portCHAR char - #define portFLOAT float - #define portDOUBLE double - #define portLONG long - #define portSHORT short - #define portSTACK_TYPE uint32_t - #define portBASE_TYPE long - - typedef portSTACK_TYPE StackType_t; - typedef long BaseType_t; - typedef unsigned long UBaseType_t; - - #if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS ) - typedef uint16_t TickType_t; - #define portMAX_DELAY ( TickType_t ) 0xffff - #elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS ) - typedef uint32_t TickType_t; - #define portMAX_DELAY ( TickType_t ) 0xffffffffUL +#define portCHAR char +#define portFLOAT float +#define portDOUBLE double +#define portLONG long +#define portSHORT short +#define portSTACK_TYPE uint32_t +#define portBASE_TYPE long + +typedef portSTACK_TYPE StackType_t; +typedef long BaseType_t; +typedef unsigned long UBaseType_t; + +#if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS ) + typedef uint16_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffff +#elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS ) + typedef uint32_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffffffffUL /* 32-bit tick type on a 32-bit architecture, so reads of the tick count do * not need to be guarded with a critical section. */ - #define portTICK_TYPE_IS_ATOMIC 1 - #else - #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width. - #endif + #define portTICK_TYPE_IS_ATOMIC 1 +#else + #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width. +#endif /*-----------------------------------------------------------*/ /* Architecture specifics. */ - #define portSTACK_GROWTH ( -1 ) - #define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) - #define portBYTE_ALIGNMENT 8 - #define portDONT_DISCARD __attribute__( ( used ) ) +#define portSTACK_GROWTH ( -1 ) +#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) +#define portBYTE_ALIGNMENT 8 +#define portDONT_DISCARD __attribute__( ( used ) ) /*-----------------------------------------------------------*/ /* Scheduler utilities. */ - #define portYIELD() \ +#define portYIELD() \ { \ /* Set a PendSV to request a context switch. */ \ portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; \ @@ -93,158 +93,170 @@ __asm volatile ( "isb" ); \ } - #define portNVIC_INT_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed04 ) ) - #define portNVIC_PENDSVSET_BIT ( 1UL << 28UL ) - #define portEND_SWITCHING_ISR( xSwitchRequired ) do { if( xSwitchRequired != pdFALSE ) portYIELD(); } while( 0 ) - #define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x ) +#define portNVIC_INT_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed04 ) ) +#define portNVIC_PENDSVSET_BIT ( 1UL << 28UL ) +#define portEND_SWITCHING_ISR( xSwitchRequired ) \ + do \ + { \ + if( xSwitchRequired != pdFALSE ) \ + { \ + traceISR_EXIT_TO_SCHEDULER(); \ + portYIELD(); \ + } \ + else \ + { \ + traceISR_EXIT(); \ + } \ + } while( 0 ) +#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x ) /*-----------------------------------------------------------*/ /* Critical section management. */ - extern void vPortEnterCritical( void ); - extern void vPortExitCritical( void ); - #define portSET_INTERRUPT_MASK_FROM_ISR() ulPortRaiseBASEPRI() - #define portCLEAR_INTERRUPT_MASK_FROM_ISR( x ) vPortSetBASEPRI( x ) - #define portDISABLE_INTERRUPTS() vPortRaiseBASEPRI() - #define portENABLE_INTERRUPTS() vPortSetBASEPRI( 0 ) - #define portENTER_CRITICAL() vPortEnterCritical() - #define portEXIT_CRITICAL() vPortExitCritical() +extern void vPortEnterCritical( void ); +extern void vPortExitCritical( void ); +#define portSET_INTERRUPT_MASK_FROM_ISR() ulPortRaiseBASEPRI() +#define portCLEAR_INTERRUPT_MASK_FROM_ISR( x ) vPortSetBASEPRI( x ) +#define portDISABLE_INTERRUPTS() vPortRaiseBASEPRI() +#define portENABLE_INTERRUPTS() vPortSetBASEPRI( 0 ) +#define portENTER_CRITICAL() vPortEnterCritical() +#define portEXIT_CRITICAL() vPortExitCritical() /*-----------------------------------------------------------*/ /* Task function macros as described on the FreeRTOS.org WEB site. These are * not necessary for to use this port. They are defined so the common demo files * (which build with all the ports) will build. */ - #define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters ) - #define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters ) +#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters ) +#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters ) /*-----------------------------------------------------------*/ /* Tickless idle/low power functionality. */ - #ifndef portSUPPRESS_TICKS_AND_SLEEP - extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime ); - #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime ) vPortSuppressTicksAndSleep( xExpectedIdleTime ) - #endif +#ifndef portSUPPRESS_TICKS_AND_SLEEP + extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime ); + #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime ) vPortSuppressTicksAndSleep( xExpectedIdleTime ) +#endif /*-----------------------------------------------------------*/ /* Architecture specific optimisations. */ - #ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION - #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1 - #endif +#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION + #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1 +#endif - #if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 +#if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 /* Generic helper function. */ - __attribute__( ( always_inline ) ) static inline uint8_t ucPortCountLeadingZeros( uint32_t ulBitmap ) - { - uint8_t ucReturn; + __attribute__( ( always_inline ) ) static inline uint8_t ucPortCountLeadingZeros( uint32_t ulBitmap ) + { + uint8_t ucReturn; - __asm volatile ( "clz %0, %1" : "=r" ( ucReturn ) : "r" ( ulBitmap ) : "memory" ); + __asm volatile ( "clz %0, %1" : "=r" ( ucReturn ) : "r" ( ulBitmap ) : "memory" ); - return ucReturn; - } + return ucReturn; + } /* Check the configuration. */ - #if ( configMAX_PRIORITIES > 32 ) - #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice. - #endif + #if ( configMAX_PRIORITIES > 32 ) + #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice. + #endif /* Store/clear the ready priorities in a bit map. */ - #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) ) - #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) ) + #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) ) + #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) ) /*-----------------------------------------------------------*/ - #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - ( uint32_t ) ucPortCountLeadingZeros( ( uxReadyPriorities ) ) ) + #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - ( uint32_t ) ucPortCountLeadingZeros( ( uxReadyPriorities ) ) ) - #endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */ +#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */ /*-----------------------------------------------------------*/ - #ifdef configASSERT - void vPortValidateInterruptPriority( void ); - #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() vPortValidateInterruptPriority() - #endif +#ifdef configASSERT + void vPortValidateInterruptPriority( void ); + #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() vPortValidateInterruptPriority() +#endif /* portNOP() is not required by this port. */ - #define portNOP() +#define portNOP() - #define portINLINE __inline +#define portINLINE __inline - #ifndef portFORCE_INLINE - #define portFORCE_INLINE inline __attribute__( ( always_inline ) ) - #endif +#ifndef portFORCE_INLINE + #define portFORCE_INLINE inline __attribute__( ( always_inline ) ) +#endif + +portFORCE_INLINE static BaseType_t xPortIsInsideInterrupt( void ) +{ + uint32_t ulCurrentInterrupt; + BaseType_t xReturn; + + /* Obtain the number of the currently executing interrupt. */ + __asm volatile ( "mrs %0, ipsr" : "=r" ( ulCurrentInterrupt )::"memory" ); - portFORCE_INLINE static BaseType_t xPortIsInsideInterrupt( void ) + if( ulCurrentInterrupt == 0 ) { - uint32_t ulCurrentInterrupt; - BaseType_t xReturn; - - /* Obtain the number of the currently executing interrupt. */ - __asm volatile ( "mrs %0, ipsr" : "=r" ( ulCurrentInterrupt )::"memory" ); - - if( ulCurrentInterrupt == 0 ) - { - xReturn = pdFALSE; - } - else - { - xReturn = pdTRUE; - } - - return xReturn; + xReturn = pdFALSE; } + else + { + xReturn = pdTRUE; + } + + return xReturn; +} /*-----------------------------------------------------------*/ - portFORCE_INLINE static void vPortRaiseBASEPRI( void ) - { - uint32_t ulNewBASEPRI; - - __asm volatile - ( - " mov %0, %1 \n"\ - " cpsid i \n"\ - " msr basepri, %0 \n"\ - " isb \n"\ - " dsb \n"\ - " cpsie i \n"\ - : "=r" ( ulNewBASEPRI ) : "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "memory" - ); - } +portFORCE_INLINE static void vPortRaiseBASEPRI( void ) +{ + uint32_t ulNewBASEPRI; + + __asm volatile + ( + " mov %0, %1 \n" \ + " cpsid i \n" \ + " msr basepri, %0 \n" \ + " isb \n" \ + " dsb \n" \ + " cpsie i \n" \ + : "=r" ( ulNewBASEPRI ) : "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "memory" + ); +} /*-----------------------------------------------------------*/ - portFORCE_INLINE static uint32_t ulPortRaiseBASEPRI( void ) - { - uint32_t ulOriginalBASEPRI, ulNewBASEPRI; - - __asm volatile - ( - " mrs %0, basepri \n"\ - " mov %1, %2 \n"\ - " cpsid i \n"\ - " msr basepri, %1 \n"\ - " isb \n"\ - " dsb \n"\ - " cpsie i \n"\ - : "=r" ( ulOriginalBASEPRI ), "=r" ( ulNewBASEPRI ) : "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "memory" - ); - - /* This return will not be reached but is necessary to prevent compiler - * warnings. */ - return ulOriginalBASEPRI; - } +portFORCE_INLINE static uint32_t ulPortRaiseBASEPRI( void ) +{ + uint32_t ulOriginalBASEPRI, ulNewBASEPRI; + + __asm volatile + ( + " mrs %0, basepri \n" \ + " mov %1, %2 \n" \ + " cpsid i \n" \ + " msr basepri, %1 \n" \ + " isb \n" \ + " dsb \n" \ + " cpsie i \n" \ + : "=r" ( ulOriginalBASEPRI ), "=r" ( ulNewBASEPRI ) : "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "memory" + ); + + /* This return will not be reached but is necessary to prevent compiler + * warnings. */ + return ulOriginalBASEPRI; +} /*-----------------------------------------------------------*/ - portFORCE_INLINE static void vPortSetBASEPRI( uint32_t ulNewMaskValue ) - { - __asm volatile - ( - " msr basepri, %0 "::"r" ( ulNewMaskValue ) : "memory" - ); - } +portFORCE_INLINE static void vPortSetBASEPRI( uint32_t ulNewMaskValue ) +{ + __asm volatile + ( + " msr basepri, %0 " ::"r" ( ulNewMaskValue ) : "memory" + ); +} /*-----------------------------------------------------------*/ - #define portMEMORY_BARRIER() __asm volatile ( "" ::: "memory" ) +#define portMEMORY_BARRIER() __asm volatile ( "" ::: "memory" ) /* *INDENT-OFF* */ #ifdef __cplusplus diff --git a/Source/portable/GCC/ARM_CM85/non_secure/mpu_wrappers_v2_asm.c b/Source/portable/GCC/ARM_CM85/non_secure/mpu_wrappers_v2_asm.c index d247c92e0..052f97850 100644 --- a/Source/portable/GCC/ARM_CM85/non_secure/mpu_wrappers_v2_asm.c +++ b/Source/portable/GCC/ARM_CM85/non_secure/mpu_wrappers_v2_asm.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -365,31 +365,6 @@ } /*-----------------------------------------------------------*/ - char * MPU_pcTaskGetName( TaskHandle_t xTaskToQuery ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; - - char * MPU_pcTaskGetName( TaskHandle_t xTaskToQuery ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ - { - __asm volatile - ( - " .syntax unified \n" - " .extern MPU_pcTaskGetNameImpl \n" - " \n" - " push {r0} \n" - " mrs r0, control \n" - " tst r0, #1 \n" - " bne MPU_pcTaskGetName_Unpriv \n" - " MPU_pcTaskGetName_Priv: \n" - " pop {r0} \n" - " b MPU_pcTaskGetNameImpl \n" - " MPU_pcTaskGetName_Unpriv: \n" - " pop {r0} \n" - " svc %0 \n" - " \n" - : : "i" ( SYSTEM_CALL_pcTaskGetName ) : "memory" - ); - } -/*-----------------------------------------------------------*/ - #if ( configGENERATE_RUN_TIME_STATS == 1 ) configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetRunTimeCounter( const TaskHandle_t xTask ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; @@ -1512,31 +1487,27 @@ #if ( configUSE_TIMERS == 1 ) - BaseType_t MPU_xTimerGenericCommandEntry( const xTimerGenericCommandParams_t * pxParams ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + BaseType_t MPU_xTimerGenericCommandFromTaskEntry( const xTimerGenericCommandFromTaskParams_t * pxParams ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; - BaseType_t MPU_xTimerGenericCommandEntry( const xTimerGenericCommandParams_t * pxParams ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + BaseType_t MPU_xTimerGenericCommandFromTaskEntry( const xTimerGenericCommandFromTaskParams_t * pxParams ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ { __asm volatile ( - " .syntax unified \n" - " .extern MPU_xTimerGenericCommandPrivImpl \n" - " \n" - " push {r0} \n" - " mrs r0, ipsr \n" - " cmp r0, #0 \n" - " bne MPU_xTimerGenericCommand_Priv \n" - " mrs r0, control \n" - " tst r0, #1 \n" - " beq MPU_xTimerGenericCommand_Priv \n" - " MPU_xTimerGenericCommand_Unpriv: \n" - " pop {r0} \n" - " svc %0 \n" - " MPU_xTimerGenericCommand_Priv: \n" - " pop {r0} \n" - " b MPU_xTimerGenericCommandPrivImpl \n" - " \n" - " \n" - : : "i" ( SYSTEM_CALL_xTimerGenericCommand ) : "memory" + " .syntax unified \n" + " .extern MPU_xTimerGenericCommandFromTaskImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " bne MPU_xTimerGenericCommandFromTask_Unpriv \n" + " MPU_xTimerGenericCommandFromTask_Priv: \n" + " pop {r0} \n" + " b MPU_xTimerGenericCommandFromTaskImpl \n" + " MPU_xTimerGenericCommandFromTask_Unpriv: \n" + " pop {r0} \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xTimerGenericCommandFromTask ) : "memory" ); } diff --git a/Source/portable/GCC/ARM_CM85/non_secure/port.c b/Source/portable/GCC/ARM_CM85/non_secure/port.c index 9712ac353..230fe5fc2 100644 --- a/Source/portable/GCC/ARM_CM85/non_secure/port.c +++ b/Source/portable/GCC/ARM_CM85/non_secure/port.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -68,6 +68,22 @@ #if ( ( configRUN_FREERTOS_SECURE_ONLY == 1 ) && ( configENABLE_TRUSTZONE == 1 ) ) #error TrustZone needs to be disabled in order to run FreeRTOS on the Secure Side. #endif + +/** + * Cortex-M23 does not have non-secure PSPLIM. We should use PSPLIM on Cortex-M23 + * only when FreeRTOS runs on secure side. + */ +#if ( ( portHAS_ARMV8M_MAIN_EXTENSION == 0 ) && ( configRUN_FREERTOS_SECURE_ONLY == 0 ) ) + #define portUSE_PSPLIM_REGISTER 0 +#else + #define portUSE_PSPLIM_REGISTER 1 +#endif +/*-----------------------------------------------------------*/ + +/** + * @brief Prototype of all Interrupt Service Routines (ISRs). + */ +typedef void ( * portISR_t )( void ); /*-----------------------------------------------------------*/ /** @@ -91,10 +107,18 @@ /** * @brief Constants required to manipulate the SCB. */ -#define portSCB_SYS_HANDLER_CTRL_STATE_REG ( *( volatile uint32_t * ) 0xe000ed24 ) +#define portSCB_VTOR_REG ( *( ( portISR_t ** ) 0xe000ed08 ) ) +#define portSCB_SYS_HANDLER_CTRL_STATE_REG ( *( ( volatile uint32_t * ) 0xe000ed24 ) ) #define portSCB_MEM_FAULT_ENABLE_BIT ( 1UL << 16UL ) /*-----------------------------------------------------------*/ +/** + * @brief Constants used to check the installation of the FreeRTOS interrupt handlers. + */ +#define portVECTOR_INDEX_SVC ( 11 ) +#define portVECTOR_INDEX_PENDSV ( 14 ) +/*-----------------------------------------------------------*/ + /** * @brief Constants required to check the validity of an interrupt priority. */ @@ -111,8 +135,8 @@ /** * @brief Constants used during system call enter and exit. */ -#define portPSR_STACK_PADDING_MASK ( 1UL << 9UL ) -#define portEXC_RETURN_STACK_FRAME_TYPE_MASK ( 1UL << 4UL ) +#define portPSR_STACK_PADDING_MASK ( 1UL << 9UL ) +#define portEXC_RETURN_STACK_FRAME_TYPE_MASK ( 1UL << 4UL ) /*-----------------------------------------------------------*/ /** @@ -134,81 +158,81 @@ /** * @brief Offsets in the stack to the parameters when inside the SVC handler. */ -#define portOFFSET_TO_LR ( 5 ) -#define portOFFSET_TO_PC ( 6 ) -#define portOFFSET_TO_PSR ( 7 ) +#define portOFFSET_TO_LR ( 5 ) +#define portOFFSET_TO_PC ( 6 ) +#define portOFFSET_TO_PSR ( 7 ) /*-----------------------------------------------------------*/ /** * @brief Constants required to manipulate the MPU. */ -#define portMPU_TYPE_REG ( *( ( volatile uint32_t * ) 0xe000ed90 ) ) -#define portMPU_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed94 ) ) -#define portMPU_RNR_REG ( *( ( volatile uint32_t * ) 0xe000ed98 ) ) +#define portMPU_TYPE_REG ( *( ( volatile uint32_t * ) 0xe000ed90 ) ) +#define portMPU_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed94 ) ) +#define portMPU_RNR_REG ( *( ( volatile uint32_t * ) 0xe000ed98 ) ) -#define portMPU_RBAR_REG ( *( ( volatile uint32_t * ) 0xe000ed9c ) ) -#define portMPU_RLAR_REG ( *( ( volatile uint32_t * ) 0xe000eda0 ) ) +#define portMPU_RBAR_REG ( *( ( volatile uint32_t * ) 0xe000ed9c ) ) +#define portMPU_RLAR_REG ( *( ( volatile uint32_t * ) 0xe000eda0 ) ) -#define portMPU_RBAR_A1_REG ( *( ( volatile uint32_t * ) 0xe000eda4 ) ) -#define portMPU_RLAR_A1_REG ( *( ( volatile uint32_t * ) 0xe000eda8 ) ) +#define portMPU_RBAR_A1_REG ( *( ( volatile uint32_t * ) 0xe000eda4 ) ) +#define portMPU_RLAR_A1_REG ( *( ( volatile uint32_t * ) 0xe000eda8 ) ) -#define portMPU_RBAR_A2_REG ( *( ( volatile uint32_t * ) 0xe000edac ) ) -#define portMPU_RLAR_A2_REG ( *( ( volatile uint32_t * ) 0xe000edb0 ) ) +#define portMPU_RBAR_A2_REG ( *( ( volatile uint32_t * ) 0xe000edac ) ) +#define portMPU_RLAR_A2_REG ( *( ( volatile uint32_t * ) 0xe000edb0 ) ) -#define portMPU_RBAR_A3_REG ( *( ( volatile uint32_t * ) 0xe000edb4 ) ) -#define portMPU_RLAR_A3_REG ( *( ( volatile uint32_t * ) 0xe000edb8 ) ) +#define portMPU_RBAR_A3_REG ( *( ( volatile uint32_t * ) 0xe000edb4 ) ) +#define portMPU_RLAR_A3_REG ( *( ( volatile uint32_t * ) 0xe000edb8 ) ) -#define portMPU_MAIR0_REG ( *( ( volatile uint32_t * ) 0xe000edc0 ) ) -#define portMPU_MAIR1_REG ( *( ( volatile uint32_t * ) 0xe000edc4 ) ) +#define portMPU_MAIR0_REG ( *( ( volatile uint32_t * ) 0xe000edc0 ) ) +#define portMPU_MAIR1_REG ( *( ( volatile uint32_t * ) 0xe000edc4 ) ) -#define portMPU_RBAR_ADDRESS_MASK ( 0xffffffe0 ) /* Must be 32-byte aligned. */ -#define portMPU_RLAR_ADDRESS_MASK ( 0xffffffe0 ) /* Must be 32-byte aligned. */ +#define portMPU_RBAR_ADDRESS_MASK ( 0xffffffe0 ) /* Must be 32-byte aligned. */ +#define portMPU_RLAR_ADDRESS_MASK ( 0xffffffe0 ) /* Must be 32-byte aligned. */ -#define portMPU_RBAR_ACCESS_PERMISSIONS_MASK ( 3UL << 1UL ) +#define portMPU_RBAR_ACCESS_PERMISSIONS_MASK ( 3UL << 1UL ) -#define portMPU_MAIR_ATTR0_POS ( 0UL ) -#define portMPU_MAIR_ATTR0_MASK ( 0x000000ff ) +#define portMPU_MAIR_ATTR0_POS ( 0UL ) +#define portMPU_MAIR_ATTR0_MASK ( 0x000000ff ) -#define portMPU_MAIR_ATTR1_POS ( 8UL ) -#define portMPU_MAIR_ATTR1_MASK ( 0x0000ff00 ) +#define portMPU_MAIR_ATTR1_POS ( 8UL ) +#define portMPU_MAIR_ATTR1_MASK ( 0x0000ff00 ) -#define portMPU_MAIR_ATTR2_POS ( 16UL ) -#define portMPU_MAIR_ATTR2_MASK ( 0x00ff0000 ) +#define portMPU_MAIR_ATTR2_POS ( 16UL ) +#define portMPU_MAIR_ATTR2_MASK ( 0x00ff0000 ) -#define portMPU_MAIR_ATTR3_POS ( 24UL ) -#define portMPU_MAIR_ATTR3_MASK ( 0xff000000 ) +#define portMPU_MAIR_ATTR3_POS ( 24UL ) +#define portMPU_MAIR_ATTR3_MASK ( 0xff000000 ) -#define portMPU_MAIR_ATTR4_POS ( 0UL ) -#define portMPU_MAIR_ATTR4_MASK ( 0x000000ff ) +#define portMPU_MAIR_ATTR4_POS ( 0UL ) +#define portMPU_MAIR_ATTR4_MASK ( 0x000000ff ) -#define portMPU_MAIR_ATTR5_POS ( 8UL ) -#define portMPU_MAIR_ATTR5_MASK ( 0x0000ff00 ) +#define portMPU_MAIR_ATTR5_POS ( 8UL ) +#define portMPU_MAIR_ATTR5_MASK ( 0x0000ff00 ) -#define portMPU_MAIR_ATTR6_POS ( 16UL ) -#define portMPU_MAIR_ATTR6_MASK ( 0x00ff0000 ) +#define portMPU_MAIR_ATTR6_POS ( 16UL ) +#define portMPU_MAIR_ATTR6_MASK ( 0x00ff0000 ) -#define portMPU_MAIR_ATTR7_POS ( 24UL ) -#define portMPU_MAIR_ATTR7_MASK ( 0xff000000 ) +#define portMPU_MAIR_ATTR7_POS ( 24UL ) +#define portMPU_MAIR_ATTR7_MASK ( 0xff000000 ) -#define portMPU_RLAR_ATTR_INDEX0 ( 0UL << 1UL ) -#define portMPU_RLAR_ATTR_INDEX1 ( 1UL << 1UL ) -#define portMPU_RLAR_ATTR_INDEX2 ( 2UL << 1UL ) -#define portMPU_RLAR_ATTR_INDEX3 ( 3UL << 1UL ) -#define portMPU_RLAR_ATTR_INDEX4 ( 4UL << 1UL ) -#define portMPU_RLAR_ATTR_INDEX5 ( 5UL << 1UL ) -#define portMPU_RLAR_ATTR_INDEX6 ( 6UL << 1UL ) -#define portMPU_RLAR_ATTR_INDEX7 ( 7UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX0 ( 0UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX1 ( 1UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX2 ( 2UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX3 ( 3UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX4 ( 4UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX5 ( 5UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX6 ( 6UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX7 ( 7UL << 1UL ) -#define portMPU_RLAR_REGION_ENABLE ( 1UL ) +#define portMPU_RLAR_REGION_ENABLE ( 1UL ) /* Enable privileged access to unmapped region. */ -#define portMPU_PRIV_BACKGROUND_ENABLE_BIT ( 1UL << 2UL ) +#define portMPU_PRIV_BACKGROUND_ENABLE_BIT ( 1UL << 2UL ) /* Enable MPU. */ -#define portMPU_ENABLE_BIT ( 1UL << 0UL ) +#define portMPU_ENABLE_BIT ( 1UL << 0UL ) /* Expected value of the portMPU_TYPE register. */ -#define portEXPECTED_MPU_TYPE_VALUE ( configTOTAL_MPU_REGIONS << 8UL ) +#define portEXPECTED_MPU_TYPE_VALUE ( configTOTAL_MPU_REGIONS << 8UL ) /* Extract first address of the MPU region as encoded in the * RBAR (Region Base Address Register) value. */ @@ -448,13 +472,13 @@ portDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIV #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) - /** - * @brief Sets up the task stack so that upon returning from - * SVC, the task stack is used again. - * - * @param pulSystemCallStack The current SP when the SVC was raised. - * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler. - */ +/** + * @brief Sets up the task stack so that upon returning from + * SVC, the task stack is used again. + * + * @param pulSystemCallStack The current SP when the SVC was raised. + * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler. + */ void vSystemCallExit( uint32_t * pulSystemCallStack, uint32_t ulLR ) PRIVILEGED_FUNCTION; @@ -462,11 +486,11 @@ portDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIV #if ( configENABLE_MPU == 1 ) - /** - * @brief Checks whether or not the calling task is privileged. - * - * @return pdTRUE if the calling task is privileged, pdFALSE otherwise. - */ +/** + * @brief Checks whether or not the calling task is privileged. + * + * @return pdTRUE if the calling task is privileged, pdFALSE otherwise. + */ BaseType_t xPortIsTaskPrivileged( void ) PRIVILEGED_FUNCTION; #endif /* configENABLE_MPU == 1 */ @@ -501,13 +525,13 @@ PRIVILEGED_DATA static volatile uint32_t ulCriticalNesting = 0xaaaaaaaaUL; * FreeRTOS API functions are not called from interrupts that have been assigned * a priority above configMAX_SYSCALL_INTERRUPT_PRIORITY. */ -#if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) ) +#if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) static uint8_t ucMaxSysCallPriority = 0; static uint32_t ulMaxPRIGROUPValue = 0; static const volatile uint8_t * const pcInterruptPriorityRegisters = ( const volatile uint8_t * ) portNVIC_IP_REGISTERS_OFFSET_16; -#endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) ) */ +#endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */ #if ( configUSE_TICKLESS_IDLE == 1 ) @@ -760,8 +784,15 @@ __attribute__( ( weak ) ) void vPortSetupTimerInterrupt( void ) /* PRIVILEGED_FU } #endif /* configUSE_TICKLESS_IDLE */ - /* Stop and reset the SysTick. */ - portNVIC_SYSTICK_CTRL_REG = 0UL; + /* Stop and reset SysTick. + * + * QEMU versions older than 7.0.0 contain a bug which causes an error if we + * enable SysTick without first selecting a valid clock source. We trigger + * the bug if we change clock sources from a clock with a zero clock period + * to one with a nonzero clock period and enable Systick at the same time. + * So we configure the CLKSOURCE bit here, prior to setting the ENABLE bit. + * This workaround avoids the bug in QEMU versions older than 7.0.0. */ + portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT_CONFIG; portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL; /* Configure SysTick to interrupt at the requested rate. */ @@ -819,6 +850,7 @@ static void prvTaskExitError( void ) static void prvSetupMPU( void ) /* PRIVILEGED_FUNCTION */ { #if defined( __ARMCC_VERSION ) + /* Declaration when these variable are defined in code instead of being * exported from linker scripts. */ extern uint32_t * __privileged_functions_start__; @@ -972,13 +1004,19 @@ void SysTick_Handler( void ) /* PRIVILEGED_FUNCTION */ uint32_t ulPreviousMask; ulPreviousMask = portSET_INTERRUPT_MASK_FROM_ISR(); + traceISR_ENTER(); { /* Increment the RTOS tick. */ if( xTaskIncrementTick() != pdFALSE ) { + traceISR_EXIT_TO_SCHEDULER(); /* Pend a context switch. */ portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; } + else + { + traceISR_EXIT(); + } } portCLEAR_INTERRUPT_MASK_FROM_ISR( ulPreviousMask ); } @@ -988,6 +1026,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO { #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) ) #if defined( __ARMCC_VERSION ) + /* Declaration when these variable are defined in code instead of being * exported from linker scripts. */ extern uint32_t * __syscalls_flash_start__; @@ -1083,18 +1122,24 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO vRestoreContextOfFirstTask(); break; - #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) ) - case portSVC_RAISE_PRIVILEGE: + #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) ) + case portSVC_RAISE_PRIVILEGE: - /* Only raise the privilege, if the svc was raised from any of - * the system calls. */ - if( ( ulPC >= ( uint32_t ) __syscalls_flash_start__ ) && - ( ulPC <= ( uint32_t ) __syscalls_flash_end__ ) ) - { - vRaisePrivilege(); - } - break; - #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) */ + /* Only raise the privilege, if the svc was raised from any of + * the system calls. */ + if( ( ulPC >= ( uint32_t ) __syscalls_flash_start__ ) && + ( ulPC <= ( uint32_t ) __syscalls_flash_end__ ) ) + { + vRaisePrivilege(); + } + break; + #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) */ + + #if ( configENABLE_MPU == 1 ) + case portSVC_YIELD: + vPortYield(); + break; + #endif /* configENABLE_MPU == 1 */ default: /* Incorrect SVC call. */ @@ -1154,12 +1199,11 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO { /* Extended frame i.e. FPU in use. */ ulStackFrameSize = 26; - __asm volatile - ( + __asm volatile ( " vpush {s0} \n" /* Trigger lazy stacking. */ " vpop {s0} \n" /* Nullify the affect of the above instruction. */ ::: "memory" - ); + ); } else { @@ -1171,7 +1215,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO { ulStackFrameSize = 8; } - #endif /* if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */ + #endif /* configENABLE_FPU || configENABLE_MVE */ /* Make space on the system call stack for the stack frame. */ pulSystemCallStack = pulSystemCallStack - ulStackFrameSize; @@ -1187,18 +1231,24 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO * point (i.e. the caller of the MPU_). We need to restore it * when we exit from the system call. */ pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry = pulTaskStack[ portOFFSET_TO_LR ]; - /* Store the value of the PSPLIM register before the SVC was raised. * We need to restore it when we exit from the system call. */ - __asm volatile ( "mrs %0, psplim" : "=r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) ); + #if ( portUSE_PSPLIM_REGISTER == 1 ) + { + __asm volatile ( "mrs %0, psplim" : "=r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) ); + } + #endif /* Use the pulSystemCallStack in thread mode. */ __asm volatile ( "msr psp, %0" : : "r" ( pulSystemCallStack ) ); - __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) ); + #if ( portUSE_PSPLIM_REGISTER == 1 ) + { + __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) ); + } + #endif /* Start executing the system call upon returning from this handler. */ pulSystemCallStack[ portOFFSET_TO_PC ] = uxSystemCallImplementations[ ucSystemCallNumber ]; - /* Raise a request to exit from the system call upon finishing the * system call. */ pulSystemCallStack[ portOFFSET_TO_LR ] = ( uint32_t ) vRequestSystemCallExit; @@ -1224,14 +1274,13 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO pulSystemCallStack[ portOFFSET_TO_PSR ] &= ( ~portPSR_STACK_PADDING_MASK ); /* Raise the privilege for the duration of the system call. */ - __asm volatile - ( + __asm volatile ( " mrs r0, control \n" /* Obtain current control value. */ " movs r1, #1 \n" /* r1 = 1. */ " bics r0, r1 \n" /* Clear nPRIV bit. */ " msr control, r0 \n" /* Write back new control value. */ ::: "r0", "r1", "memory" - ); + ); } } @@ -1293,12 +1342,11 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO { /* Extended frame i.e. FPU in use. */ ulStackFrameSize = 26; - __asm volatile - ( + __asm volatile ( " vpush {s0} \n" /* Trigger lazy stacking. */ " vpop {s0} \n" /* Nullify the affect of the above instruction. */ ::: "memory" - ); + ); } else { @@ -1310,7 +1358,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO { ulStackFrameSize = 8; } - #endif /* if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */ + #endif /* configENABLE_FPU || configENABLE_MVE */ /* Make space on the task stack for the stack frame. */ pulTaskStack = pulTaskStack - ulStackFrameSize; @@ -1332,7 +1380,11 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO /* Restore the PSPLIM register to what it was at the time of * system call entry. */ - __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) ); + #if ( portUSE_PSPLIM_REGISTER == 1 ) + { + __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) ); + } + #endif /* If the hardware used padding to force the stack pointer * to be double word aligned, set the stacked xPSR bit[9], @@ -1350,14 +1402,13 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO pxMpuSettings->xSystemCallStackInfo.pulTaskStack = NULL; /* Drop the privilege before returning to the thread mode. */ - __asm volatile - ( + __asm volatile ( " mrs r0, control \n" /* Obtain current control value. */ " movs r1, #1 \n" /* r1 = 1. */ " orrs r0, r1 \n" /* Set nPRIV bit. */ " msr control, r0 \n" /* Write back new control value. */ ::: "r0", "r1", "memory" - ); + ); } } @@ -1410,21 +1461,21 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO xMPUSettings->ulContext[ ulIndex ] = 0x11111111; /* r11. */ ulIndex++; - xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pvParameters; /* r0. */ + xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pvParameters; /* r0. */ ulIndex++; - xMPUSettings->ulContext[ ulIndex ] = 0x01010101; /* r1. */ + xMPUSettings->ulContext[ ulIndex ] = 0x01010101; /* r1. */ ulIndex++; - xMPUSettings->ulContext[ ulIndex ] = 0x02020202; /* r2. */ + xMPUSettings->ulContext[ ulIndex ] = 0x02020202; /* r2. */ ulIndex++; - xMPUSettings->ulContext[ ulIndex ] = 0x03030303; /* r3. */ + xMPUSettings->ulContext[ ulIndex ] = 0x03030303; /* r3. */ ulIndex++; - xMPUSettings->ulContext[ ulIndex ] = 0x12121212; /* r12. */ + xMPUSettings->ulContext[ ulIndex ] = 0x12121212; /* r12. */ ulIndex++; xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portTASK_RETURN_ADDRESS; /* LR. */ ulIndex++; - xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxCode; /* PC. */ + xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxCode; /* PC. */ ulIndex++; - xMPUSettings->ulContext[ ulIndex ] = portINITIAL_XPSR; /* xPSR. */ + xMPUSettings->ulContext[ ulIndex ] = portINITIAL_XPSR; /* xPSR. */ ulIndex++; #if ( configENABLE_TRUSTZONE == 1 ) @@ -1435,8 +1486,9 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO #endif /* configENABLE_TRUSTZONE */ xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) ( pxTopOfStack - 8 ); /* PSP with the hardware saved stack. */ ulIndex++; - xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxEndOfStack; /* PSPLIM. */ + xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxEndOfStack; /* PSPLIM. */ ulIndex++; + if( xRunPrivileged == pdTRUE ) { xMPUSettings->ulTaskFlags |= portTASK_IS_PRIVILEGED_FLAG; @@ -1449,6 +1501,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portINITIAL_CONTROL_UNPRIVILEGED; /* CONTROL. */ ulIndex++; } + xMPUSettings->ulContext[ ulIndex ] = portINITIAL_EXC_RETURN; /* LR (EXC_RETURN). */ ulIndex++; @@ -1483,7 +1536,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO * interrupt. */ #if ( portPRELOAD_REGISTERS == 0 ) { - pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */ + pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */ *pxTopOfStack = portINITIAL_XPSR; /* xPSR. */ pxTopOfStack--; *pxTopOfStack = ( StackType_t ) pxCode; /* PC. */ @@ -1505,7 +1558,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO } #else /* portPRELOAD_REGISTERS */ { - pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */ + pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */ *pxTopOfStack = portINITIAL_XPSR; /* xPSR. */ pxTopOfStack--; *pxTopOfStack = ( StackType_t ) pxCode; /* PC. */ @@ -1540,7 +1593,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO pxTopOfStack--; *pxTopOfStack = portINITIAL_EXC_RETURN; /* EXC_RETURN. */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */ + *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */ #if ( configENABLE_TRUSTZONE == 1 ) { @@ -1559,22 +1612,52 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */ { - #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) ) + /* An application can install FreeRTOS interrupt handlers in one of the + * folllowing ways: + * 1. Direct Routing - Install the functions SVC_Handler and PendSV_Handler + * for SVCall and PendSV interrupts respectively. + * 2. Indirect Routing - Install separate handlers for SVCall and PendSV + * interrupts and route program control from those handlers to + * SVC_Handler and PendSV_Handler functions. + * + * Applications that use Indirect Routing must set + * configCHECK_HANDLER_INSTALLATION to 0 in their FreeRTOSConfig.h. Direct + * routing, which is validated here when configCHECK_HANDLER_INSTALLATION + * is 1, should be preferred when possible. */ + #if ( configCHECK_HANDLER_INSTALLATION == 1 ) + { + const portISR_t * const pxVectorTable = portSCB_VTOR_REG; + + /* Validate that the application has correctly installed the FreeRTOS + * handlers for SVCall and PendSV interrupts. We do not check the + * installation of the SysTick handler because the application may + * choose to drive the RTOS tick using a timer other than the SysTick + * timer by overriding the weak function vPortSetupTimerInterrupt(). + * + * Assertion failures here indicate incorrect installation of the + * FreeRTOS handlers. For help installing the FreeRTOS handlers, see + * https://www.FreeRTOS.org/FAQHelp.html. + * + * Systems with a configurable address for the interrupt vector table + * can also encounter assertion failures or even system faults here if + * VTOR is not set correctly to point to the application's vector table. */ + configASSERT( pxVectorTable[ portVECTOR_INDEX_SVC ] == SVC_Handler ); + configASSERT( pxVectorTable[ portVECTOR_INDEX_PENDSV ] == PendSV_Handler ); + } + #endif /* configCHECK_HANDLER_INSTALLATION */ + + #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) { - volatile uint32_t ulOriginalPriority; volatile uint32_t ulImplementedPrioBits = 0; volatile uint8_t ucMaxPriorityValue; /* Determine the maximum priority from which ISR safe FreeRTOS API - * functions can be called. ISR safe functions are those that end in - * "FromISR". FreeRTOS maintains separate thread and ISR API functions to + * functions can be called. ISR safe functions are those that end in + * "FromISR". FreeRTOS maintains separate thread and ISR API functions to * ensure interrupt entry is as fast and simple as possible. * - * Save the interrupt priority value that is about to be clobbered. */ - ulOriginalPriority = portNVIC_SHPR2_REG; - - /* Determine the number of priority bits available. First write to all - * possible bits. */ + * First, determine the number of priority bits available. Write to all + * possible bits in the priority setting for SVCall. */ portNVIC_SHPR2_REG = 0xFF000000; /* Read the value back to see how many bits stuck. */ @@ -1593,11 +1676,10 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */ /* Check that the bits not implemented in hardware are zero in * configMAX_SYSCALL_INTERRUPT_PRIORITY. */ - configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( ~ucMaxPriorityValue ) ) == 0U ); + configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( uint8_t ) ( ~( uint32_t ) ucMaxPriorityValue ) ) == 0U ); /* Calculate the maximum acceptable priority group value for the number * of bits read back. */ - while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE ) { ulImplementedPrioBits++; @@ -1635,16 +1717,14 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */ * register. */ ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT; ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK; - - /* Restore the clobbered interrupt priority register to its original - * value. */ - portNVIC_SHPR2_REG = ulOriginalPriority; } - #endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) ) */ + #endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */ - /* Make PendSV, CallSV and SysTick the same priority as the kernel. */ + /* Make PendSV and SysTick the lowest priority interrupts, and make SVCall + * the highest priority. */ portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI; portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI; + portNVIC_SHPR2_REG = 0; #if ( configENABLE_MPU == 1 ) { @@ -1701,6 +1781,7 @@ void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */ int32_t lIndex = 0; #if defined( __ARMCC_VERSION ) + /* Declaration when these variable are defined in code instead of being * exported from linker scripts. */ extern uint32_t * __privileged_sram_start__; @@ -1886,7 +1967,7 @@ BaseType_t xPortIsInsideInterrupt( void ) } /*-----------------------------------------------------------*/ -#if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) ) +#if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) void vPortValidateInterruptPriority( void ) { @@ -1944,7 +2025,7 @@ BaseType_t xPortIsInsideInterrupt( void ) configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue ); } -#endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) ) */ +#endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */ /*-----------------------------------------------------------*/ #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) diff --git a/Source/portable/GCC/ARM_CM85/non_secure/portasm.c b/Source/portable/GCC/ARM_CM85/non_secure/portasm.c index 7431c98f1..451e0abb7 100644 --- a/Source/portable/GCC/ARM_CM85/non_secure/portasm.c +++ b/Source/portable/GCC/ARM_CM85/non_secure/portasm.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -75,16 +75,16 @@ " ldmia r0!, {r4-r11} \n" /* Read 4 set of RBAR/RLAR registers from TCB. */ " stmia r2, {r4-r11} \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */ " \n" - #if ( configTOTAL_MPU_REGIONS == 16 ) - " movs r3, #8 \n" /* r3 = 8. */ - " str r3, [r1] \n" /* Program RNR = 8. */ - " ldmia r0!, {r4-r11} \n" /* Read 4 set of RBAR/RLAR registers from TCB. */ - " stmia r2, {r4-r11} \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */ - " movs r3, #12 \n" /* r3 = 12. */ - " str r3, [r1] \n" /* Program RNR = 12. */ - " ldmia r0!, {r4-r11} \n" /* Read 4 set of RBAR/RLAR registers from TCB. */ - " stmia r2, {r4-r11} \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */ - #endif /* configTOTAL_MPU_REGIONS == 16 */ + #if ( configTOTAL_MPU_REGIONS == 16 ) + " movs r3, #8 \n" /* r3 = 8. */ + " str r3, [r1] \n" /* Program RNR = 8. */ + " ldmia r0!, {r4-r11} \n" /* Read 4 set of RBAR/RLAR registers from TCB. */ + " stmia r2, {r4-r11} \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */ + " movs r3, #12 \n" /* r3 = 12. */ + " str r3, [r1] \n" /* Program RNR = 12. */ + " ldmia r0!, {r4-r11} \n" /* Read 4 set of RBAR/RLAR registers from TCB. */ + " stmia r2, {r4-r11} \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */ + #endif /* configTOTAL_MPU_REGIONS == 16 */ " \n" " ldr r1, xMPUCTRLConst2 \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */ " ldr r2, [r1] \n" /* Read the value of MPU_CTRL. */ @@ -294,15 +294,15 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att " save_general_regs: \n" " mrs r3, psp \n" " \n" - #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) - " add r3, r3, #0x20 \n" /* Move r3 to location where s0 is saved. */ - " tst lr, #0x10 \n" - " ittt eq \n" - " vstmiaeq r2!, {s16-s31} \n" /* Store s16-s31. */ - " vldmiaeq r3, {s0-s16} \n" /* Copy hardware saved FP context into s0-s16. */ - " vstmiaeq r2!, {s0-s16} \n" /* Store hardware saved FP context. */ - " sub r3, r3, #0x20 \n" /* Set r3 back to the location of hardware saved context. */ - #endif /* configENABLE_FPU || configENABLE_MVE */ + #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) + " add r3, r3, #0x20 \n" /* Move r3 to location where s0 is saved. */ + " tst lr, #0x10 \n" + " ittt eq \n" + " vstmiaeq r2!, {s16-s31} \n" /* Store s16-s31. */ + " vldmiaeq r3, {s0-s16} \n" /* Copy hardware saved FP context into s0-s16. */ + " vstmiaeq r2!, {s0-s16} \n" /* Store hardware saved FP context. */ + " sub r3, r3, #0x20 \n" /* Set r3 back to the location of hardware saved context. */ + #endif /* configENABLE_FPU || configENABLE_MVE */ " \n" " stmia r2!, {r4-r11} \n" /* Store r4-r11. */ " ldmia r3, {r4-r11} \n" /* Copy the hardware saved context into r4-r11. */ @@ -348,16 +348,16 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att " ldmia r0!, {r4-r11} \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */ " stmia r2, {r4-r11} \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */ " \n" - #if ( configTOTAL_MPU_REGIONS == 16 ) - " movs r3, #8 \n" /* r3 = 8. */ - " str r3, [r1] \n" /* Program RNR = 8. */ - " ldmia r0!, {r4-r11} \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */ - " stmia r2, {r4-r11} \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */ - " movs r3, #12 \n" /* r3 = 12. */ - " str r3, [r1] \n" /* Program RNR = 12. */ - " ldmia r0!, {r4-r11} \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */ - " stmia r2, {r4-r11} \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */ - #endif /* configTOTAL_MPU_REGIONS == 16 */ + #if ( configTOTAL_MPU_REGIONS == 16 ) + " movs r3, #8 \n" /* r3 = 8. */ + " str r3, [r1] \n" /* Program RNR = 8. */ + " ldmia r0!, {r4-r11} \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */ + " stmia r2, {r4-r11} \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */ + " movs r3, #12 \n" /* r3 = 12. */ + " str r3, [r1] \n" /* Program RNR = 12. */ + " ldmia r0!, {r4-r11} \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */ + " stmia r2, {r4-r11} \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */ + #endif /* configTOTAL_MPU_REGIONS == 16 */ " \n" " ldr r1, xMPUCTRLConst \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */ " ldr r2, [r1] \n" /* Read the value of MPU_CTRL. */ @@ -393,13 +393,13 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att " ldmdb r2!, {r4-r11} \n" /* r4-r11 contain hardware saved context. */ " stmia r3!, {r4-r11} \n" /* Copy the hardware saved context on the task stack. */ " ldmdb r2!, {r4-r11} \n" /* r4-r11 restored. */ - #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) - " tst lr, #0x10 \n" - " ittt eq \n" - " vldmdbeq r2!, {s0-s16} \n" /* s0-s16 contain hardware saved FP context. */ - " vstmiaeq r3!, {s0-s16} \n" /* Copy hardware saved FP context on the task stack. */ - " vldmdbeq r2!, {s16-s31} \n" /* Restore s16-s31. */ - #endif /* configENABLE_FPU || configENABLE_MVE */ + #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) + " tst lr, #0x10 \n" + " ittt eq \n" + " vldmdbeq r2!, {s0-s16} \n" /* s0-s16 contain hardware saved FP context. */ + " vstmiaeq r3!, {s0-s16} \n" /* Copy hardware saved FP context on the task stack. */ + " vldmdbeq r2!, {s16-s31} \n" /* Restore s16-s31. */ + #endif /* configENABLE_FPU || configENABLE_MVE */ " \n" " restore_context_done: \n" " str r2, [r1] \n" /* Save the location where the context should be saved next as the first member of TCB. */ @@ -452,11 +452,11 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att " save_ns_context: \n" " ldr r3, pxCurrentTCBConst \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ " ldr r1, [r3] \n" /* Read pxCurrentTCB. */ - #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) - " tst lr, #0x10 \n" /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */ - " it eq \n" - " vstmdbeq r2!, {s16-s31} \n" /* Store the additional FP context registers which are not saved automatically. */ - #endif /* configENABLE_FPU || configENABLE_MVE */ + #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) + " tst lr, #0x10 \n" /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */ + " it eq \n" + " vstmdbeq r2!, {s16-s31} \n" /* Store the additional FP context registers which are not saved automatically. */ + #endif /* configENABLE_FPU || configENABLE_MVE */ " subs r2, r2, #44 \n" /* Make space for xSecureContext, PSPLIM, LR and the remaining registers on the stack. */ " str r2, [r1] \n" /* Save the new top of stack in TCB. */ " adds r2, r2, #12 \n" /* r2 = r2 + 12. */ @@ -498,11 +498,11 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att " \n" " restore_ns_context: \n" " ldmia r2!, {r4-r11} \n" /* Restore the registers that are not automatically restored. */ - #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) - " tst lr, #0x10 \n" /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */ - " it eq \n" - " vldmiaeq r2!, {s16-s31} \n" /* Restore the additional FP context registers which are not restored automatically. */ - #endif /* configENABLE_FPU || configENABLE_MVE */ + #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) + " tst lr, #0x10 \n" /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */ + " it eq \n" + " vldmiaeq r2!, {s16-s31} \n" /* Restore the additional FP context registers which are not restored automatically. */ + #endif /* configENABLE_FPU || configENABLE_MVE */ " msr psp, r2 \n" /* Remember the new top of stack for the task. */ " bx lr \n" " \n" diff --git a/Source/portable/GCC/ARM_CM85/non_secure/portasm.h b/Source/portable/GCC/ARM_CM85/non_secure/portasm.h index f64ceb525..c6d2ebd58 100644 --- a/Source/portable/GCC/ARM_CM85/non_secure/portasm.h +++ b/Source/portable/GCC/ARM_CM85/non_secure/portasm.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/Source/portable/GCC/ARM_CM85/non_secure/portmacro.h b/Source/portable/GCC/ARM_CM85/non_secure/portmacro.h index f606f817d..bd605f630 100644 --- a/Source/portable/GCC/ARM_CM85/non_secure/portmacro.h +++ b/Source/portable/GCC/ARM_CM85/non_secure/portmacro.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -53,9 +53,9 @@ /** * Architecture specifics. */ -#define portARCH_NAME "Cortex-M85" -#define portHAS_BASEPRI 1 -#define portDONT_DISCARD __attribute__( ( used ) ) +#define portARCH_NAME "Cortex-M85" +#define portHAS_ARMV8M_MAIN_EXTENSION 1 +#define portDONT_DISCARD __attribute__( ( used ) ) /*-----------------------------------------------------------*/ /* ARMv8-M common port configurations. */ @@ -65,8 +65,8 @@ /** * @brief Critical section management. */ -#define portDISABLE_INTERRUPTS() ulSetInterruptMask() -#define portENABLE_INTERRUPTS() vClearInterruptMask( 0 ) +#define portDISABLE_INTERRUPTS() ulSetInterruptMask() +#define portENABLE_INTERRUPTS() vClearInterruptMask( 0 ) /*-----------------------------------------------------------*/ /* *INDENT-OFF* */ diff --git a/Source/portable/GCC/ARM_CM85/non_secure/portmacrocommon.h b/Source/portable/GCC/ARM_CM85/non_secure/portmacrocommon.h index 6f666da22..33f21d85b 100644 --- a/Source/portable/GCC/ARM_CM85/non_secure/portmacrocommon.h +++ b/Source/portable/GCC/ARM_CM85/non_secure/portmacrocommon.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -117,7 +117,7 @@ extern uint32_t ulSetInterruptMask( void ) /* __attribute__(( naked )) PRIVILEGE extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */; #if ( configENABLE_TRUSTZONE == 1 ) - extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize ); /* __attribute__ (( naked )) */ + extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize ); /* __attribute__ (( naked )) */ extern void vPortFreeSecureContext( uint32_t * pulTCB ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */; #endif /* configENABLE_TRUSTZONE */ @@ -188,13 +188,13 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P #if ( configENABLE_MPU == 1 ) - /** - * @brief Settings to define an MPU region. - */ +/** + * @brief Settings to define an MPU region. + */ typedef struct MPURegionSettings { - uint32_t ulRBAR; /**< RBAR for the region. */ - uint32_t ulRLAR; /**< RLAR for the region. */ + uint32_t ulRBAR; /**< RBAR for the region. */ + uint32_t ulRLAR; /**< RLAR for the region. */ } MPURegionSettings_t; #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) @@ -203,9 +203,9 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P #error configSYSTEM_CALL_STACK_SIZE must be defined to the desired size of the system call stack in words for using MPU wrappers v2. #endif - /** - * @brief System call stack. - */ +/** + * @brief System call stack. + */ typedef struct SYSTEM_CALL_STACK_INFO { uint32_t ulSystemCallStackBuffer[ configSYSTEM_CALL_STACK_SIZE ]; @@ -218,74 +218,74 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P #endif /* configUSE_MPU_WRAPPERS_V1 == 0 */ - /** - * @brief MPU settings as stored in the TCB. - */ +/** + * @brief MPU settings as stored in the TCB. + */ #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) - #if( configENABLE_TRUSTZONE == 1 ) + #if ( configENABLE_TRUSTZONE == 1 ) - /* - * +-----------+---------------+----------+-----------------+------------------------------+-----+ - * | s16-s31 | s0-s15, FPSCR | r4-r11 | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, | | - * | | | | PC, xPSR | CONTROL, EXC_RETURN | | - * +-----------+---------------+----------+-----------------+------------------------------+-----+ - * - * <-----------><--------------><---------><----------------><-----------------------------><----> - * 16 16 8 8 5 1 - */ - #define MAX_CONTEXT_SIZE 54 +/* + * +-----------+---------------+----------+-----------------+------------------------------+-----+ + * | s16-s31 | s0-s15, FPSCR | r4-r11 | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, | | + * | | | | PC, xPSR | CONTROL, EXC_RETURN | | + * +-----------+---------------+----------+-----------------+------------------------------+-----+ + * + * <-----------><--------------><---------><----------------><-----------------------------><----> + * 16 16 8 8 5 1 + */ + #define MAX_CONTEXT_SIZE 54 #else /* #if( configENABLE_TRUSTZONE == 1 ) */ - /* - * +-----------+---------------+----------+-----------------+----------------------+-----+ - * | s16-s31 | s0-s15, FPSCR | r4-r11 | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL | | - * | | | | PC, xPSR | EXC_RETURN | | - * +-----------+---------------+----------+-----------------+----------------------+-----+ - * - * <-----------><--------------><---------><----------------><---------------------><----> - * 16 16 8 8 4 1 - */ - #define MAX_CONTEXT_SIZE 53 +/* + * +-----------+---------------+----------+-----------------+----------------------+-----+ + * | s16-s31 | s0-s15, FPSCR | r4-r11 | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL | | + * | | | | PC, xPSR | EXC_RETURN | | + * +-----------+---------------+----------+-----------------+----------------------+-----+ + * + * <-----------><--------------><---------><----------------><---------------------><----> + * 16 16 8 8 4 1 + */ + #define MAX_CONTEXT_SIZE 53 #endif /* #if( configENABLE_TRUSTZONE == 1 ) */ #else /* #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */ - #if( configENABLE_TRUSTZONE == 1 ) + #if ( configENABLE_TRUSTZONE == 1 ) - /* - * +----------+-----------------+------------------------------+-----+ - * | r4-r11 | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, | | - * | | PC, xPSR | CONTROL, EXC_RETURN | | - * +----------+-----------------+------------------------------+-----+ - * - * <---------><----------------><------------------------------><----> - * 8 8 5 1 - */ - #define MAX_CONTEXT_SIZE 22 +/* + * +----------+-----------------+------------------------------+-----+ + * | r4-r11 | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, | | + * | | PC, xPSR | CONTROL, EXC_RETURN | | + * +----------+-----------------+------------------------------+-----+ + * + * <---------><----------------><------------------------------><----> + * 8 8 5 1 + */ + #define MAX_CONTEXT_SIZE 22 #else /* #if( configENABLE_TRUSTZONE == 1 ) */ - /* - * +----------+-----------------+----------------------+-----+ - * | r4-r11 | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL | | - * | | PC, xPSR | EXC_RETURN | | - * +----------+-----------------+----------------------+-----+ - * - * <---------><----------------><----------------------><----> - * 8 8 4 1 - */ - #define MAX_CONTEXT_SIZE 21 +/* + * +----------+-----------------+----------------------+-----+ + * | r4-r11 | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL | | + * | | PC, xPSR | EXC_RETURN | | + * +----------+-----------------+----------------------+-----+ + * + * <---------><----------------><----------------------><----> + * 8 8 4 1 + */ + #define MAX_CONTEXT_SIZE 21 #endif /* #if( configENABLE_TRUSTZONE == 1 ) */ #endif /* #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */ - /* Flags used for xMPU_SETTINGS.ulTaskFlags member. */ - #define portSTACK_FRAME_HAS_PADDING_FLAG ( 1UL << 0UL ) - #define portTASK_IS_PRIVILEGED_FLAG ( 1UL << 1UL ) +/* Flags used for xMPU_SETTINGS.ulTaskFlags member. */ + #define portSTACK_FRAME_HAS_PADDING_FLAG ( 1UL << 0UL ) + #define portTASK_IS_PRIVILEGED_FLAG ( 1UL << 1UL ) /* Size of an Access Control List (ACL) entry in bits. */ #define portACL_ENTRY_SIZE_BITS ( 32U ) @@ -313,7 +313,7 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P * system calls. */ #ifdef configASSERT - #if ( portHAS_BASEPRI == 1 ) + #if ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) void vPortValidateInterruptPriority( void ); #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() vPortValidateInterruptPriority() #endif @@ -333,12 +333,29 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P /** * @brief Scheduler utilities. */ -#define portYIELD() vPortYield() +#if ( configENABLE_MPU == 1 ) + #define portYIELD() __asm volatile ( "svc %0" ::"i" ( portSVC_YIELD ) : "memory" ) + #define portYIELD_WITHIN_API() vPortYield() +#else + #define portYIELD() vPortYield() + #define portYIELD_WITHIN_API() vPortYield() +#endif + #define portNVIC_INT_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed04 ) ) #define portNVIC_PENDSVSET_BIT ( 1UL << 28UL ) -#define portEND_SWITCHING_ISR( xSwitchRequired ) \ - do { if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; } \ - while( 0 ) +#define portEND_SWITCHING_ISR( xSwitchRequired ) \ + do \ + { \ + if( xSwitchRequired ) \ + { \ + traceISR_EXIT_TO_SCHEDULER(); \ + portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; \ + } \ + else \ + { \ + traceISR_EXIT(); \ + } \ + } while( 0 ) #define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x ) /*-----------------------------------------------------------*/ @@ -424,12 +441,12 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P extern BaseType_t xPortIsTaskPrivileged( void ); - /** - * @brief Checks whether or not the calling task is privileged. - * - * @return pdTRUE if the calling task is privileged, pdFALSE otherwise. - */ - #define portIS_TASK_PRIVILEGED() xPortIsTaskPrivileged() +/** + * @brief Checks whether or not the calling task is privileged. + * + * @return pdTRUE if the calling task is privileged, pdFALSE otherwise. + */ + #define portIS_TASK_PRIVILEGED() xPortIsTaskPrivileged() #endif /* configENABLE_MPU == 1 */ /*-----------------------------------------------------------*/ @@ -440,6 +457,56 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P #define portMEMORY_BARRIER() __asm volatile ( "" ::: "memory" ) /*-----------------------------------------------------------*/ +/* Select correct value of configUSE_PORT_OPTIMISED_TASK_SELECTION + * based on whether or not Mainline extension is implemented. */ +#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION + #if ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) + #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1 + #else + #define configUSE_PORT_OPTIMISED_TASK_SELECTION 0 + #endif +#endif /* #ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION */ + +/** + * @brief Port-optimised task selection. + */ +#if ( configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 ) + +/** + * @brief Count the number of leading zeros in a 32-bit value. + */ + static portFORCE_INLINE uint32_t ulPortCountLeadingZeros( uint32_t ulBitmap ) + { + uint32_t ulReturn; + + __asm volatile ( "clz %0, %1" : "=r" ( ulReturn ) : "r" ( ulBitmap ) : "memory" ); + + return ulReturn; + } + +/* Check the configuration. */ + #if ( configMAX_PRIORITIES > 32 ) + #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 different priorities as tasks that share a priority will time slice. + #endif + + #if ( portHAS_ARMV8M_MAIN_EXTENSION == 0 ) + #error ARMv8-M baseline implementations (such as Cortex-M23) do not support port-optimised task selection. Please set configUSE_PORT_OPTIMISED_TASK_SELECTION to 0 or leave it undefined. + #endif + +/** + * @brief Store/clear the ready priorities in a bit map. + */ + #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) ) + #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) ) + +/** + * @brief Get the priority of the highest-priority task that is ready to execute. + */ + #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - ulPortCountLeadingZeros( ( uxReadyPriorities ) ) ) + +#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */ +/*-----------------------------------------------------------*/ + /* *INDENT-OFF* */ #ifdef __cplusplus } diff --git a/Source/portable/GCC/ARM_CM85/secure/secure_context.c b/Source/portable/GCC/ARM_CM85/secure/secure_context.c index e37dd9672..83b3dbce1 100644 --- a/Source/portable/GCC/ARM_CM85/secure/secure_context.c +++ b/Source/portable/GCC/ARM_CM85/secure/secure_context.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -65,7 +65,7 @@ * @brief Maximum number of secure contexts. */ #ifndef secureconfigMAX_SECURE_CONTEXTS - #define secureconfigMAX_SECURE_CONTEXTS 8UL + #define secureconfigMAX_SECURE_CONTEXTS 8UL #endif /*-----------------------------------------------------------*/ @@ -164,15 +164,15 @@ secureportNON_SECURE_CALLABLE void SecureContext_Init( void ) } #if ( configENABLE_MPU == 1 ) - { - /* Configure thread mode to use PSP and to be unprivileged. */ - secureportSET_CONTROL( securecontextCONTROL_VALUE_UNPRIVILEGED ); - } + { + /* Configure thread mode to use PSP and to be unprivileged. */ + secureportSET_CONTROL( securecontextCONTROL_VALUE_UNPRIVILEGED ); + } #else /* configENABLE_MPU */ - { - /* Configure thread mode to use PSP and to be privileged. */ - secureportSET_CONTROL( securecontextCONTROL_VALUE_PRIVILEGED ); - } + { + /* Configure thread mode to use PSP and to be privileged. */ + secureportSET_CONTROL( securecontextCONTROL_VALUE_PRIVILEGED ); + } #endif /* configENABLE_MPU */ } } @@ -219,16 +219,16 @@ secureportNON_SECURE_CALLABLE void SecureContext_Init( void ) if( pucStackMemory != NULL ) { /* Since stack grows down, the starting point will be the last - * location. Note that this location is next to the last - * allocated byte for stack (excluding the space for seal values) - * because the hardware decrements the stack pointer before - * writing i.e. if stack pointer is 0x2, a push operation will - * decrement the stack pointer to 0x1 and then write at 0x1. */ + * location. Note that this location is next to the last + * allocated byte for stack (excluding the space for seal values) + * because the hardware decrements the stack pointer before + * writing i.e. if stack pointer is 0x2, a push operation will + * decrement the stack pointer to 0x1 and then write at 0x1. */ xSecureContexts[ ulSecureContextIndex ].pucStackStart = pucStackMemory + ulSecureStackSize; /* Seal the created secure process stack. */ - *( uint32_t * )( pucStackMemory + ulSecureStackSize ) = securecontextSTACK_SEAL_VALUE; - *( uint32_t * )( pucStackMemory + ulSecureStackSize + 4 ) = securecontextSTACK_SEAL_VALUE; + *( uint32_t * ) ( pucStackMemory + ulSecureStackSize ) = securecontextSTACK_SEAL_VALUE; + *( uint32_t * ) ( pucStackMemory + ulSecureStackSize + 4 ) = securecontextSTACK_SEAL_VALUE; /* The stack cannot go beyond this location. This value is * programmed in the PSPLIM register on context switch.*/ @@ -237,32 +237,32 @@ secureportNON_SECURE_CALLABLE void SecureContext_Init( void ) xSecureContexts[ ulSecureContextIndex ].pvTaskHandle = pvTaskHandle; #if ( configENABLE_MPU == 1 ) + { + /* Store the correct CONTROL value for the task on the stack. + * This value is programmed in the CONTROL register on + * context switch. */ + pulCurrentStackPointer = ( uint32_t * ) xSecureContexts[ ulSecureContextIndex ].pucStackStart; + pulCurrentStackPointer--; + + if( ulIsTaskPrivileged ) { - /* Store the correct CONTROL value for the task on the stack. - * This value is programmed in the CONTROL register on - * context switch. */ - pulCurrentStackPointer = ( uint32_t * ) xSecureContexts[ ulSecureContextIndex ].pucStackStart; - pulCurrentStackPointer--; - - if( ulIsTaskPrivileged ) - { - *( pulCurrentStackPointer ) = securecontextCONTROL_VALUE_PRIVILEGED; - } - else - { - *( pulCurrentStackPointer ) = securecontextCONTROL_VALUE_UNPRIVILEGED; - } - - /* Store the current stack pointer. This value is programmed in - * the PSP register on context switch. */ - xSecureContexts[ ulSecureContextIndex ].pucCurrentStackPointer = ( uint8_t * ) pulCurrentStackPointer; + *( pulCurrentStackPointer ) = securecontextCONTROL_VALUE_PRIVILEGED; } - #else /* configENABLE_MPU */ + else { - /* Current SP is set to the starting of the stack. This - * value programmed in the PSP register on context switch. */ - xSecureContexts[ ulSecureContextIndex ].pucCurrentStackPointer = xSecureContexts[ ulSecureContextIndex ].pucStackStart; + *( pulCurrentStackPointer ) = securecontextCONTROL_VALUE_UNPRIVILEGED; } + + /* Store the current stack pointer. This value is programmed in + * the PSP register on context switch. */ + xSecureContexts[ ulSecureContextIndex ].pucCurrentStackPointer = ( uint8_t * ) pulCurrentStackPointer; + } + #else /* configENABLE_MPU */ + { + /* Current SP is set to the starting of the stack. This + * value programmed in the PSP register on context switch. */ + xSecureContexts[ ulSecureContextIndex ].pucCurrentStackPointer = xSecureContexts[ ulSecureContextIndex ].pucStackStart; + } #endif /* configENABLE_MPU */ /* Ensure to never return 0 as a valid context handle. */ @@ -275,7 +275,8 @@ secureportNON_SECURE_CALLABLE void SecureContext_Init( void ) } /*-----------------------------------------------------------*/ -secureportNON_SECURE_CALLABLE void SecureContext_FreeContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle ) +secureportNON_SECURE_CALLABLE void SecureContext_FreeContext( SecureContextHandle_t xSecureContextHandle, + void * pvTaskHandle ) { uint32_t ulIPSR, ulSecureContextIndex; @@ -306,7 +307,8 @@ secureportNON_SECURE_CALLABLE void SecureContext_FreeContext( SecureContextHandl } /*-----------------------------------------------------------*/ -secureportNON_SECURE_CALLABLE void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle ) +secureportNON_SECURE_CALLABLE void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle, + void * pvTaskHandle ) { uint8_t * pucStackLimit; uint32_t ulSecureContextIndex; @@ -328,7 +330,8 @@ secureportNON_SECURE_CALLABLE void SecureContext_LoadContext( SecureContextHandl } /*-----------------------------------------------------------*/ -secureportNON_SECURE_CALLABLE void SecureContext_SaveContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle ) +secureportNON_SECURE_CALLABLE void SecureContext_SaveContext( SecureContextHandle_t xSecureContextHandle, + void * pvTaskHandle ) { uint8_t * pucStackLimit; uint32_t ulSecureContextIndex; diff --git a/Source/portable/GCC/ARM_CM85/secure/secure_context.h b/Source/portable/GCC/ARM_CM85/secure/secure_context.h index 2220ea646..40fdc276d 100644 --- a/Source/portable/GCC/ARM_CM85/secure/secure_context.h +++ b/Source/portable/GCC/ARM_CM85/secure/secure_context.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -38,12 +38,12 @@ /** * @brief PSP value when no secure context is loaded. */ -#define securecontextNO_STACK 0x0 +#define securecontextNO_STACK 0x0 /** * @brief Invalid context ID. */ -#define securecontextINVALID_CONTEXT_ID 0UL +#define securecontextINVALID_CONTEXT_ID 0UL /*-----------------------------------------------------------*/ /** @@ -108,7 +108,8 @@ void SecureContext_Init( void ); * @param[in] xSecureContextHandle Context handle corresponding to the * context to be freed. */ -void SecureContext_FreeContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle ); +void SecureContext_FreeContext( SecureContextHandle_t xSecureContextHandle, + void * pvTaskHandle ); /** * @brief Loads the given context. @@ -119,7 +120,8 @@ void SecureContext_FreeContext( SecureContextHandle_t xSecureContextHandle, void * @param[in] xSecureContextHandle Context handle corresponding to the context * to be loaded. */ -void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle ); +void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle, + void * pvTaskHandle ); /** * @brief Saves the given context. @@ -130,6 +132,7 @@ void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle, void * @param[in] xSecureContextHandle Context handle corresponding to the context * to be saved. */ -void SecureContext_SaveContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle ); +void SecureContext_SaveContext( SecureContextHandle_t xSecureContextHandle, + void * pvTaskHandle ); #endif /* __SECURE_CONTEXT_H__ */ diff --git a/Source/portable/GCC/ARM_CM85/secure/secure_context_port.c b/Source/portable/GCC/ARM_CM85/secure/secure_context_port.c index d70822c06..31c1f7331 100644 --- a/Source/portable/GCC/ARM_CM85/secure/secure_context_port.c +++ b/Source/portable/GCC/ARM_CM85/secure/secure_context_port.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/Source/portable/GCC/ARM_CM85/secure/secure_heap.c b/Source/portable/GCC/ARM_CM85/secure/secure_heap.c index 19f7c2354..d9789404b 100644 --- a/Source/portable/GCC/ARM_CM85/secure/secure_heap.c +++ b/Source/portable/GCC/ARM_CM85/secure/secure_heap.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -62,6 +62,22 @@ /* Assumes 8bit bytes! */ #define secureheapBITS_PER_BYTE ( ( size_t ) 8 ) + +/* Max value that fits in a size_t type. */ +#define secureheapSIZE_MAX ( ~( ( size_t ) 0 ) ) + +/* Check if adding a and b will result in overflow. */ +#define secureheapADD_WILL_OVERFLOW( a, b ) ( ( a ) > ( secureheapSIZE_MAX - ( b ) ) ) + +/* MSB of the xBlockSize member of an BlockLink_t structure is used to track + * the allocation status of a block. When MSB of the xBlockSize member of + * an BlockLink_t structure is set then the block belongs to the application. + * When the bit is free the block is still part of the free heap space. */ +#define secureheapBLOCK_ALLOCATED_BITMASK ( ( ( size_t ) 1 ) << ( ( sizeof( size_t ) * secureheapBITS_PER_BYTE ) - 1 ) ) +#define secureheapBLOCK_SIZE_IS_VALID( xBlockSize ) ( ( ( xBlockSize ) & secureheapBLOCK_ALLOCATED_BITMASK ) == 0 ) +#define secureheapBLOCK_IS_ALLOCATED( pxBlock ) ( ( ( pxBlock->xBlockSize ) & secureheapBLOCK_ALLOCATED_BITMASK ) != 0 ) +#define secureheapALLOCATE_BLOCK( pxBlock ) ( ( pxBlock->xBlockSize ) |= secureheapBLOCK_ALLOCATED_BITMASK ) +#define secureheapFREE_BLOCK( pxBlock ) ( ( pxBlock->xBlockSize ) &= ~secureheapBLOCK_ALLOCATED_BITMASK ) /*-----------------------------------------------------------*/ /* Allocate the memory for the heap. */ @@ -123,14 +139,6 @@ static BlockLink_t * pxEnd = NULL; static size_t xFreeBytesRemaining = 0U; static size_t xMinimumEverFreeBytesRemaining = 0U; -/** - * @brief Gets set to the top bit of an size_t type. - * - * When this bit in the xBlockSize member of an BlockLink_t structure is set - * then the block belongs to the application. When the bit is free the block is - * still part of the free heap space. - */ -static size_t xBlockAllocatedBit = 0; /*-----------------------------------------------------------*/ static void prvHeapInit( void ) @@ -175,9 +183,6 @@ static void prvHeapInit( void ) /* Only one block exists - and it covers the entire usable heap space. */ xMinimumEverFreeBytesRemaining = pxFirstFreeBlock->xBlockSize; xFreeBytesRemaining = pxFirstFreeBlock->xBlockSize; - - /* Work out the position of the top bit in a size_t variable. */ - xBlockAllocatedBit = ( ( size_t ) 1 ) << ( ( sizeof( size_t ) * secureheapBITS_PER_BYTE ) - 1 ); } /*-----------------------------------------------------------*/ @@ -250,6 +255,7 @@ void * pvPortMalloc( size_t xWantedSize ) BlockLink_t * pxPreviousBlock; BlockLink_t * pxNewBlockLink; void * pvReturn = NULL; + size_t xAdditionalRequiredSize; /* If this is the first call to malloc then the heap will require * initialisation to setup the list of free blocks. */ @@ -262,25 +268,29 @@ void * pvPortMalloc( size_t xWantedSize ) mtCOVERAGE_TEST_MARKER(); } - /* Check the requested block size is not so large that the top bit is set. - * The top bit of the block size member of the BlockLink_t structure is used - * to determine who owns the block - the application or the kernel, so it - * must be free. */ - if( ( xWantedSize & xBlockAllocatedBit ) == 0 ) + if( xWantedSize > 0 ) { - /* The wanted size is increased so it can contain a BlockLink_t + /* The wanted size must be increased so it can contain a BlockLink_t * structure in addition to the requested amount of bytes. */ - if( xWantedSize > 0 ) + if( secureheapADD_WILL_OVERFLOW( xWantedSize, xHeapStructSize ) == 0 ) { xWantedSize += xHeapStructSize; - /* Ensure that blocks are always aligned to the required number of - * bytes. */ + /* Ensure that blocks are always aligned to the required number + * of bytes. */ if( ( xWantedSize & secureportBYTE_ALIGNMENT_MASK ) != 0x00 ) { /* Byte alignment required. */ - xWantedSize += ( secureportBYTE_ALIGNMENT - ( xWantedSize & secureportBYTE_ALIGNMENT_MASK ) ); - secureportASSERT( ( xWantedSize & secureportBYTE_ALIGNMENT_MASK ) == 0 ); + xAdditionalRequiredSize = secureportBYTE_ALIGNMENT - ( xWantedSize & secureportBYTE_ALIGNMENT_MASK ); + + if( secureheapADD_WILL_OVERFLOW( xWantedSize, xAdditionalRequiredSize ) == 0 ) + { + xWantedSize += xAdditionalRequiredSize; + } + else + { + xWantedSize = 0; + } } else { @@ -289,9 +299,20 @@ void * pvPortMalloc( size_t xWantedSize ) } else { - mtCOVERAGE_TEST_MARKER(); + xWantedSize = 0; } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + /* Check the requested block size is not so large that the top bit is set. + * The top bit of the block size member of the BlockLink_t structure is used + * to determine who owns the block - the application or the kernel, so it + * must be free. */ + if( secureheapBLOCK_SIZE_IS_VALID( xWantedSize ) != 0 ) + { if( ( xWantedSize > 0 ) && ( xWantedSize <= xFreeBytesRemaining ) ) { /* Traverse the list from the start (lowest address) block until @@ -334,7 +355,8 @@ void * pvPortMalloc( size_t xWantedSize ) pxBlock->xBlockSize = xWantedSize; /* Insert the new block into the list of free blocks. */ - prvInsertBlockIntoFreeList( pxNewBlockLink ); + pxNewBlockLink->pxNextFreeBlock = pxPreviousBlock->pxNextFreeBlock; + pxPreviousBlock->pxNextFreeBlock = pxNewBlockLink; } else { @@ -354,7 +376,7 @@ void * pvPortMalloc( size_t xWantedSize ) /* The block is being returned - it is allocated and owned by * the application and has no "next" block. */ - pxBlock->xBlockSize |= xBlockAllocatedBit; + secureheapALLOCATE_BLOCK( pxBlock ); pxBlock->pxNextFreeBlock = NULL; } else @@ -375,17 +397,17 @@ void * pvPortMalloc( size_t xWantedSize ) traceMALLOC( pvReturn, xWantedSize ); #if ( secureconfigUSE_MALLOC_FAILED_HOOK == 1 ) + { + if( pvReturn == NULL ) { - if( pvReturn == NULL ) - { - extern void vApplicationMallocFailedHook( void ); - vApplicationMallocFailedHook(); - } - else - { - mtCOVERAGE_TEST_MARKER(); - } + extern void vApplicationMallocFailedHook( void ); + vApplicationMallocFailedHook(); } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } #endif /* if ( secureconfigUSE_MALLOC_FAILED_HOOK == 1 ) */ secureportASSERT( ( ( ( size_t ) pvReturn ) & ( size_t ) secureportBYTE_ALIGNMENT_MASK ) == 0 ); @@ -408,16 +430,16 @@ void vPortFree( void * pv ) pxLink = ( void * ) puc; /* Check the block is actually allocated. */ - secureportASSERT( ( pxLink->xBlockSize & xBlockAllocatedBit ) != 0 ); + secureportASSERT( secureheapBLOCK_IS_ALLOCATED( pxLink ) != 0 ); secureportASSERT( pxLink->pxNextFreeBlock == NULL ); - if( ( pxLink->xBlockSize & xBlockAllocatedBit ) != 0 ) + if( secureheapBLOCK_IS_ALLOCATED( pxLink ) != 0 ) { if( pxLink->pxNextFreeBlock == NULL ) { /* The block is being returned to the heap - it is no longer * allocated. */ - pxLink->xBlockSize &= ~xBlockAllocatedBit; + secureheapFREE_BLOCK( pxLink ); secureportDISABLE_NON_SECURE_INTERRUPTS(); { diff --git a/Source/portable/GCC/ARM_CM85/secure/secure_heap.h b/Source/portable/GCC/ARM_CM85/secure/secure_heap.h index 75c9cb00b..cf5551046 100644 --- a/Source/portable/GCC/ARM_CM85/secure/secure_heap.h +++ b/Source/portable/GCC/ARM_CM85/secure/secure_heap.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/Source/portable/GCC/ARM_CM85/secure/secure_init.c b/Source/portable/GCC/ARM_CM85/secure/secure_init.c index f93bfce95..66d35eccc 100644 --- a/Source/portable/GCC/ARM_CM85/secure/secure_init.c +++ b/Source/portable/GCC/ARM_CM85/secure/secure_init.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -93,7 +93,7 @@ secureportNON_SECURE_CALLABLE void SecureInit_EnableNSFPUAccess( void ) * permitted. CP11 should be programmed to the same value as CP10. */ *( secureinitNSACR ) |= ( secureinitNSACR_CP10_MASK | secureinitNSACR_CP11_MASK ); - /* LSPENS = 0 ==> LSPEN is writable fron non-secure state. This ensures + /* LSPENS = 0 ==> LSPEN is writable from non-secure state. This ensures * that we can enable/disable lazy stacking in port.c file. */ *( secureinitFPCCR ) &= ~( secureinitFPCCR_LSPENS_MASK ); diff --git a/Source/portable/GCC/ARM_CM85/secure/secure_init.h b/Source/portable/GCC/ARM_CM85/secure/secure_init.h index e6c9da0b4..6404c5cc4 100644 --- a/Source/portable/GCC/ARM_CM85/secure/secure_init.h +++ b/Source/portable/GCC/ARM_CM85/secure/secure_init.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/Source/portable/GCC/ARM_CM85/secure/secure_port_macros.h b/Source/portable/GCC/ARM_CM85/secure/secure_port_macros.h index d7ac5833c..085108cc1 100644 --- a/Source/portable/GCC/ARM_CM85/secure/secure_port_macros.h +++ b/Source/portable/GCC/ARM_CM85/secure/secure_port_macros.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/Source/portable/GCC/ARM_CM85_NTZ/non_secure/mpu_wrappers_v2_asm.c b/Source/portable/GCC/ARM_CM85_NTZ/non_secure/mpu_wrappers_v2_asm.c index d247c92e0..052f97850 100644 --- a/Source/portable/GCC/ARM_CM85_NTZ/non_secure/mpu_wrappers_v2_asm.c +++ b/Source/portable/GCC/ARM_CM85_NTZ/non_secure/mpu_wrappers_v2_asm.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -365,31 +365,6 @@ } /*-----------------------------------------------------------*/ - char * MPU_pcTaskGetName( TaskHandle_t xTaskToQuery ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; - - char * MPU_pcTaskGetName( TaskHandle_t xTaskToQuery ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ - { - __asm volatile - ( - " .syntax unified \n" - " .extern MPU_pcTaskGetNameImpl \n" - " \n" - " push {r0} \n" - " mrs r0, control \n" - " tst r0, #1 \n" - " bne MPU_pcTaskGetName_Unpriv \n" - " MPU_pcTaskGetName_Priv: \n" - " pop {r0} \n" - " b MPU_pcTaskGetNameImpl \n" - " MPU_pcTaskGetName_Unpriv: \n" - " pop {r0} \n" - " svc %0 \n" - " \n" - : : "i" ( SYSTEM_CALL_pcTaskGetName ) : "memory" - ); - } -/*-----------------------------------------------------------*/ - #if ( configGENERATE_RUN_TIME_STATS == 1 ) configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetRunTimeCounter( const TaskHandle_t xTask ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; @@ -1512,31 +1487,27 @@ #if ( configUSE_TIMERS == 1 ) - BaseType_t MPU_xTimerGenericCommandEntry( const xTimerGenericCommandParams_t * pxParams ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + BaseType_t MPU_xTimerGenericCommandFromTaskEntry( const xTimerGenericCommandFromTaskParams_t * pxParams ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; - BaseType_t MPU_xTimerGenericCommandEntry( const xTimerGenericCommandParams_t * pxParams ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + BaseType_t MPU_xTimerGenericCommandFromTaskEntry( const xTimerGenericCommandFromTaskParams_t * pxParams ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ { __asm volatile ( - " .syntax unified \n" - " .extern MPU_xTimerGenericCommandPrivImpl \n" - " \n" - " push {r0} \n" - " mrs r0, ipsr \n" - " cmp r0, #0 \n" - " bne MPU_xTimerGenericCommand_Priv \n" - " mrs r0, control \n" - " tst r0, #1 \n" - " beq MPU_xTimerGenericCommand_Priv \n" - " MPU_xTimerGenericCommand_Unpriv: \n" - " pop {r0} \n" - " svc %0 \n" - " MPU_xTimerGenericCommand_Priv: \n" - " pop {r0} \n" - " b MPU_xTimerGenericCommandPrivImpl \n" - " \n" - " \n" - : : "i" ( SYSTEM_CALL_xTimerGenericCommand ) : "memory" + " .syntax unified \n" + " .extern MPU_xTimerGenericCommandFromTaskImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " bne MPU_xTimerGenericCommandFromTask_Unpriv \n" + " MPU_xTimerGenericCommandFromTask_Priv: \n" + " pop {r0} \n" + " b MPU_xTimerGenericCommandFromTaskImpl \n" + " MPU_xTimerGenericCommandFromTask_Unpriv: \n" + " pop {r0} \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xTimerGenericCommandFromTask ) : "memory" ); } diff --git a/Source/portable/GCC/ARM_CM85_NTZ/non_secure/port.c b/Source/portable/GCC/ARM_CM85_NTZ/non_secure/port.c index 9712ac353..230fe5fc2 100644 --- a/Source/portable/GCC/ARM_CM85_NTZ/non_secure/port.c +++ b/Source/portable/GCC/ARM_CM85_NTZ/non_secure/port.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -68,6 +68,22 @@ #if ( ( configRUN_FREERTOS_SECURE_ONLY == 1 ) && ( configENABLE_TRUSTZONE == 1 ) ) #error TrustZone needs to be disabled in order to run FreeRTOS on the Secure Side. #endif + +/** + * Cortex-M23 does not have non-secure PSPLIM. We should use PSPLIM on Cortex-M23 + * only when FreeRTOS runs on secure side. + */ +#if ( ( portHAS_ARMV8M_MAIN_EXTENSION == 0 ) && ( configRUN_FREERTOS_SECURE_ONLY == 0 ) ) + #define portUSE_PSPLIM_REGISTER 0 +#else + #define portUSE_PSPLIM_REGISTER 1 +#endif +/*-----------------------------------------------------------*/ + +/** + * @brief Prototype of all Interrupt Service Routines (ISRs). + */ +typedef void ( * portISR_t )( void ); /*-----------------------------------------------------------*/ /** @@ -91,10 +107,18 @@ /** * @brief Constants required to manipulate the SCB. */ -#define portSCB_SYS_HANDLER_CTRL_STATE_REG ( *( volatile uint32_t * ) 0xe000ed24 ) +#define portSCB_VTOR_REG ( *( ( portISR_t ** ) 0xe000ed08 ) ) +#define portSCB_SYS_HANDLER_CTRL_STATE_REG ( *( ( volatile uint32_t * ) 0xe000ed24 ) ) #define portSCB_MEM_FAULT_ENABLE_BIT ( 1UL << 16UL ) /*-----------------------------------------------------------*/ +/** + * @brief Constants used to check the installation of the FreeRTOS interrupt handlers. + */ +#define portVECTOR_INDEX_SVC ( 11 ) +#define portVECTOR_INDEX_PENDSV ( 14 ) +/*-----------------------------------------------------------*/ + /** * @brief Constants required to check the validity of an interrupt priority. */ @@ -111,8 +135,8 @@ /** * @brief Constants used during system call enter and exit. */ -#define portPSR_STACK_PADDING_MASK ( 1UL << 9UL ) -#define portEXC_RETURN_STACK_FRAME_TYPE_MASK ( 1UL << 4UL ) +#define portPSR_STACK_PADDING_MASK ( 1UL << 9UL ) +#define portEXC_RETURN_STACK_FRAME_TYPE_MASK ( 1UL << 4UL ) /*-----------------------------------------------------------*/ /** @@ -134,81 +158,81 @@ /** * @brief Offsets in the stack to the parameters when inside the SVC handler. */ -#define portOFFSET_TO_LR ( 5 ) -#define portOFFSET_TO_PC ( 6 ) -#define portOFFSET_TO_PSR ( 7 ) +#define portOFFSET_TO_LR ( 5 ) +#define portOFFSET_TO_PC ( 6 ) +#define portOFFSET_TO_PSR ( 7 ) /*-----------------------------------------------------------*/ /** * @brief Constants required to manipulate the MPU. */ -#define portMPU_TYPE_REG ( *( ( volatile uint32_t * ) 0xe000ed90 ) ) -#define portMPU_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed94 ) ) -#define portMPU_RNR_REG ( *( ( volatile uint32_t * ) 0xe000ed98 ) ) +#define portMPU_TYPE_REG ( *( ( volatile uint32_t * ) 0xe000ed90 ) ) +#define portMPU_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed94 ) ) +#define portMPU_RNR_REG ( *( ( volatile uint32_t * ) 0xe000ed98 ) ) -#define portMPU_RBAR_REG ( *( ( volatile uint32_t * ) 0xe000ed9c ) ) -#define portMPU_RLAR_REG ( *( ( volatile uint32_t * ) 0xe000eda0 ) ) +#define portMPU_RBAR_REG ( *( ( volatile uint32_t * ) 0xe000ed9c ) ) +#define portMPU_RLAR_REG ( *( ( volatile uint32_t * ) 0xe000eda0 ) ) -#define portMPU_RBAR_A1_REG ( *( ( volatile uint32_t * ) 0xe000eda4 ) ) -#define portMPU_RLAR_A1_REG ( *( ( volatile uint32_t * ) 0xe000eda8 ) ) +#define portMPU_RBAR_A1_REG ( *( ( volatile uint32_t * ) 0xe000eda4 ) ) +#define portMPU_RLAR_A1_REG ( *( ( volatile uint32_t * ) 0xe000eda8 ) ) -#define portMPU_RBAR_A2_REG ( *( ( volatile uint32_t * ) 0xe000edac ) ) -#define portMPU_RLAR_A2_REG ( *( ( volatile uint32_t * ) 0xe000edb0 ) ) +#define portMPU_RBAR_A2_REG ( *( ( volatile uint32_t * ) 0xe000edac ) ) +#define portMPU_RLAR_A2_REG ( *( ( volatile uint32_t * ) 0xe000edb0 ) ) -#define portMPU_RBAR_A3_REG ( *( ( volatile uint32_t * ) 0xe000edb4 ) ) -#define portMPU_RLAR_A3_REG ( *( ( volatile uint32_t * ) 0xe000edb8 ) ) +#define portMPU_RBAR_A3_REG ( *( ( volatile uint32_t * ) 0xe000edb4 ) ) +#define portMPU_RLAR_A3_REG ( *( ( volatile uint32_t * ) 0xe000edb8 ) ) -#define portMPU_MAIR0_REG ( *( ( volatile uint32_t * ) 0xe000edc0 ) ) -#define portMPU_MAIR1_REG ( *( ( volatile uint32_t * ) 0xe000edc4 ) ) +#define portMPU_MAIR0_REG ( *( ( volatile uint32_t * ) 0xe000edc0 ) ) +#define portMPU_MAIR1_REG ( *( ( volatile uint32_t * ) 0xe000edc4 ) ) -#define portMPU_RBAR_ADDRESS_MASK ( 0xffffffe0 ) /* Must be 32-byte aligned. */ -#define portMPU_RLAR_ADDRESS_MASK ( 0xffffffe0 ) /* Must be 32-byte aligned. */ +#define portMPU_RBAR_ADDRESS_MASK ( 0xffffffe0 ) /* Must be 32-byte aligned. */ +#define portMPU_RLAR_ADDRESS_MASK ( 0xffffffe0 ) /* Must be 32-byte aligned. */ -#define portMPU_RBAR_ACCESS_PERMISSIONS_MASK ( 3UL << 1UL ) +#define portMPU_RBAR_ACCESS_PERMISSIONS_MASK ( 3UL << 1UL ) -#define portMPU_MAIR_ATTR0_POS ( 0UL ) -#define portMPU_MAIR_ATTR0_MASK ( 0x000000ff ) +#define portMPU_MAIR_ATTR0_POS ( 0UL ) +#define portMPU_MAIR_ATTR0_MASK ( 0x000000ff ) -#define portMPU_MAIR_ATTR1_POS ( 8UL ) -#define portMPU_MAIR_ATTR1_MASK ( 0x0000ff00 ) +#define portMPU_MAIR_ATTR1_POS ( 8UL ) +#define portMPU_MAIR_ATTR1_MASK ( 0x0000ff00 ) -#define portMPU_MAIR_ATTR2_POS ( 16UL ) -#define portMPU_MAIR_ATTR2_MASK ( 0x00ff0000 ) +#define portMPU_MAIR_ATTR2_POS ( 16UL ) +#define portMPU_MAIR_ATTR2_MASK ( 0x00ff0000 ) -#define portMPU_MAIR_ATTR3_POS ( 24UL ) -#define portMPU_MAIR_ATTR3_MASK ( 0xff000000 ) +#define portMPU_MAIR_ATTR3_POS ( 24UL ) +#define portMPU_MAIR_ATTR3_MASK ( 0xff000000 ) -#define portMPU_MAIR_ATTR4_POS ( 0UL ) -#define portMPU_MAIR_ATTR4_MASK ( 0x000000ff ) +#define portMPU_MAIR_ATTR4_POS ( 0UL ) +#define portMPU_MAIR_ATTR4_MASK ( 0x000000ff ) -#define portMPU_MAIR_ATTR5_POS ( 8UL ) -#define portMPU_MAIR_ATTR5_MASK ( 0x0000ff00 ) +#define portMPU_MAIR_ATTR5_POS ( 8UL ) +#define portMPU_MAIR_ATTR5_MASK ( 0x0000ff00 ) -#define portMPU_MAIR_ATTR6_POS ( 16UL ) -#define portMPU_MAIR_ATTR6_MASK ( 0x00ff0000 ) +#define portMPU_MAIR_ATTR6_POS ( 16UL ) +#define portMPU_MAIR_ATTR6_MASK ( 0x00ff0000 ) -#define portMPU_MAIR_ATTR7_POS ( 24UL ) -#define portMPU_MAIR_ATTR7_MASK ( 0xff000000 ) +#define portMPU_MAIR_ATTR7_POS ( 24UL ) +#define portMPU_MAIR_ATTR7_MASK ( 0xff000000 ) -#define portMPU_RLAR_ATTR_INDEX0 ( 0UL << 1UL ) -#define portMPU_RLAR_ATTR_INDEX1 ( 1UL << 1UL ) -#define portMPU_RLAR_ATTR_INDEX2 ( 2UL << 1UL ) -#define portMPU_RLAR_ATTR_INDEX3 ( 3UL << 1UL ) -#define portMPU_RLAR_ATTR_INDEX4 ( 4UL << 1UL ) -#define portMPU_RLAR_ATTR_INDEX5 ( 5UL << 1UL ) -#define portMPU_RLAR_ATTR_INDEX6 ( 6UL << 1UL ) -#define portMPU_RLAR_ATTR_INDEX7 ( 7UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX0 ( 0UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX1 ( 1UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX2 ( 2UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX3 ( 3UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX4 ( 4UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX5 ( 5UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX6 ( 6UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX7 ( 7UL << 1UL ) -#define portMPU_RLAR_REGION_ENABLE ( 1UL ) +#define portMPU_RLAR_REGION_ENABLE ( 1UL ) /* Enable privileged access to unmapped region. */ -#define portMPU_PRIV_BACKGROUND_ENABLE_BIT ( 1UL << 2UL ) +#define portMPU_PRIV_BACKGROUND_ENABLE_BIT ( 1UL << 2UL ) /* Enable MPU. */ -#define portMPU_ENABLE_BIT ( 1UL << 0UL ) +#define portMPU_ENABLE_BIT ( 1UL << 0UL ) /* Expected value of the portMPU_TYPE register. */ -#define portEXPECTED_MPU_TYPE_VALUE ( configTOTAL_MPU_REGIONS << 8UL ) +#define portEXPECTED_MPU_TYPE_VALUE ( configTOTAL_MPU_REGIONS << 8UL ) /* Extract first address of the MPU region as encoded in the * RBAR (Region Base Address Register) value. */ @@ -448,13 +472,13 @@ portDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIV #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) - /** - * @brief Sets up the task stack so that upon returning from - * SVC, the task stack is used again. - * - * @param pulSystemCallStack The current SP when the SVC was raised. - * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler. - */ +/** + * @brief Sets up the task stack so that upon returning from + * SVC, the task stack is used again. + * + * @param pulSystemCallStack The current SP when the SVC was raised. + * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler. + */ void vSystemCallExit( uint32_t * pulSystemCallStack, uint32_t ulLR ) PRIVILEGED_FUNCTION; @@ -462,11 +486,11 @@ portDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIV #if ( configENABLE_MPU == 1 ) - /** - * @brief Checks whether or not the calling task is privileged. - * - * @return pdTRUE if the calling task is privileged, pdFALSE otherwise. - */ +/** + * @brief Checks whether or not the calling task is privileged. + * + * @return pdTRUE if the calling task is privileged, pdFALSE otherwise. + */ BaseType_t xPortIsTaskPrivileged( void ) PRIVILEGED_FUNCTION; #endif /* configENABLE_MPU == 1 */ @@ -501,13 +525,13 @@ PRIVILEGED_DATA static volatile uint32_t ulCriticalNesting = 0xaaaaaaaaUL; * FreeRTOS API functions are not called from interrupts that have been assigned * a priority above configMAX_SYSCALL_INTERRUPT_PRIORITY. */ -#if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) ) +#if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) static uint8_t ucMaxSysCallPriority = 0; static uint32_t ulMaxPRIGROUPValue = 0; static const volatile uint8_t * const pcInterruptPriorityRegisters = ( const volatile uint8_t * ) portNVIC_IP_REGISTERS_OFFSET_16; -#endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) ) */ +#endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */ #if ( configUSE_TICKLESS_IDLE == 1 ) @@ -760,8 +784,15 @@ __attribute__( ( weak ) ) void vPortSetupTimerInterrupt( void ) /* PRIVILEGED_FU } #endif /* configUSE_TICKLESS_IDLE */ - /* Stop and reset the SysTick. */ - portNVIC_SYSTICK_CTRL_REG = 0UL; + /* Stop and reset SysTick. + * + * QEMU versions older than 7.0.0 contain a bug which causes an error if we + * enable SysTick without first selecting a valid clock source. We trigger + * the bug if we change clock sources from a clock with a zero clock period + * to one with a nonzero clock period and enable Systick at the same time. + * So we configure the CLKSOURCE bit here, prior to setting the ENABLE bit. + * This workaround avoids the bug in QEMU versions older than 7.0.0. */ + portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT_CONFIG; portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL; /* Configure SysTick to interrupt at the requested rate. */ @@ -819,6 +850,7 @@ static void prvTaskExitError( void ) static void prvSetupMPU( void ) /* PRIVILEGED_FUNCTION */ { #if defined( __ARMCC_VERSION ) + /* Declaration when these variable are defined in code instead of being * exported from linker scripts. */ extern uint32_t * __privileged_functions_start__; @@ -972,13 +1004,19 @@ void SysTick_Handler( void ) /* PRIVILEGED_FUNCTION */ uint32_t ulPreviousMask; ulPreviousMask = portSET_INTERRUPT_MASK_FROM_ISR(); + traceISR_ENTER(); { /* Increment the RTOS tick. */ if( xTaskIncrementTick() != pdFALSE ) { + traceISR_EXIT_TO_SCHEDULER(); /* Pend a context switch. */ portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; } + else + { + traceISR_EXIT(); + } } portCLEAR_INTERRUPT_MASK_FROM_ISR( ulPreviousMask ); } @@ -988,6 +1026,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO { #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) ) #if defined( __ARMCC_VERSION ) + /* Declaration when these variable are defined in code instead of being * exported from linker scripts. */ extern uint32_t * __syscalls_flash_start__; @@ -1083,18 +1122,24 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO vRestoreContextOfFirstTask(); break; - #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) ) - case portSVC_RAISE_PRIVILEGE: + #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) ) + case portSVC_RAISE_PRIVILEGE: - /* Only raise the privilege, if the svc was raised from any of - * the system calls. */ - if( ( ulPC >= ( uint32_t ) __syscalls_flash_start__ ) && - ( ulPC <= ( uint32_t ) __syscalls_flash_end__ ) ) - { - vRaisePrivilege(); - } - break; - #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) */ + /* Only raise the privilege, if the svc was raised from any of + * the system calls. */ + if( ( ulPC >= ( uint32_t ) __syscalls_flash_start__ ) && + ( ulPC <= ( uint32_t ) __syscalls_flash_end__ ) ) + { + vRaisePrivilege(); + } + break; + #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) */ + + #if ( configENABLE_MPU == 1 ) + case portSVC_YIELD: + vPortYield(); + break; + #endif /* configENABLE_MPU == 1 */ default: /* Incorrect SVC call. */ @@ -1154,12 +1199,11 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO { /* Extended frame i.e. FPU in use. */ ulStackFrameSize = 26; - __asm volatile - ( + __asm volatile ( " vpush {s0} \n" /* Trigger lazy stacking. */ " vpop {s0} \n" /* Nullify the affect of the above instruction. */ ::: "memory" - ); + ); } else { @@ -1171,7 +1215,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO { ulStackFrameSize = 8; } - #endif /* if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */ + #endif /* configENABLE_FPU || configENABLE_MVE */ /* Make space on the system call stack for the stack frame. */ pulSystemCallStack = pulSystemCallStack - ulStackFrameSize; @@ -1187,18 +1231,24 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO * point (i.e. the caller of the MPU_). We need to restore it * when we exit from the system call. */ pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry = pulTaskStack[ portOFFSET_TO_LR ]; - /* Store the value of the PSPLIM register before the SVC was raised. * We need to restore it when we exit from the system call. */ - __asm volatile ( "mrs %0, psplim" : "=r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) ); + #if ( portUSE_PSPLIM_REGISTER == 1 ) + { + __asm volatile ( "mrs %0, psplim" : "=r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) ); + } + #endif /* Use the pulSystemCallStack in thread mode. */ __asm volatile ( "msr psp, %0" : : "r" ( pulSystemCallStack ) ); - __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) ); + #if ( portUSE_PSPLIM_REGISTER == 1 ) + { + __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) ); + } + #endif /* Start executing the system call upon returning from this handler. */ pulSystemCallStack[ portOFFSET_TO_PC ] = uxSystemCallImplementations[ ucSystemCallNumber ]; - /* Raise a request to exit from the system call upon finishing the * system call. */ pulSystemCallStack[ portOFFSET_TO_LR ] = ( uint32_t ) vRequestSystemCallExit; @@ -1224,14 +1274,13 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO pulSystemCallStack[ portOFFSET_TO_PSR ] &= ( ~portPSR_STACK_PADDING_MASK ); /* Raise the privilege for the duration of the system call. */ - __asm volatile - ( + __asm volatile ( " mrs r0, control \n" /* Obtain current control value. */ " movs r1, #1 \n" /* r1 = 1. */ " bics r0, r1 \n" /* Clear nPRIV bit. */ " msr control, r0 \n" /* Write back new control value. */ ::: "r0", "r1", "memory" - ); + ); } } @@ -1293,12 +1342,11 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO { /* Extended frame i.e. FPU in use. */ ulStackFrameSize = 26; - __asm volatile - ( + __asm volatile ( " vpush {s0} \n" /* Trigger lazy stacking. */ " vpop {s0} \n" /* Nullify the affect of the above instruction. */ ::: "memory" - ); + ); } else { @@ -1310,7 +1358,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO { ulStackFrameSize = 8; } - #endif /* if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */ + #endif /* configENABLE_FPU || configENABLE_MVE */ /* Make space on the task stack for the stack frame. */ pulTaskStack = pulTaskStack - ulStackFrameSize; @@ -1332,7 +1380,11 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO /* Restore the PSPLIM register to what it was at the time of * system call entry. */ - __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) ); + #if ( portUSE_PSPLIM_REGISTER == 1 ) + { + __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) ); + } + #endif /* If the hardware used padding to force the stack pointer * to be double word aligned, set the stacked xPSR bit[9], @@ -1350,14 +1402,13 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO pxMpuSettings->xSystemCallStackInfo.pulTaskStack = NULL; /* Drop the privilege before returning to the thread mode. */ - __asm volatile - ( + __asm volatile ( " mrs r0, control \n" /* Obtain current control value. */ " movs r1, #1 \n" /* r1 = 1. */ " orrs r0, r1 \n" /* Set nPRIV bit. */ " msr control, r0 \n" /* Write back new control value. */ ::: "r0", "r1", "memory" - ); + ); } } @@ -1410,21 +1461,21 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO xMPUSettings->ulContext[ ulIndex ] = 0x11111111; /* r11. */ ulIndex++; - xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pvParameters; /* r0. */ + xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pvParameters; /* r0. */ ulIndex++; - xMPUSettings->ulContext[ ulIndex ] = 0x01010101; /* r1. */ + xMPUSettings->ulContext[ ulIndex ] = 0x01010101; /* r1. */ ulIndex++; - xMPUSettings->ulContext[ ulIndex ] = 0x02020202; /* r2. */ + xMPUSettings->ulContext[ ulIndex ] = 0x02020202; /* r2. */ ulIndex++; - xMPUSettings->ulContext[ ulIndex ] = 0x03030303; /* r3. */ + xMPUSettings->ulContext[ ulIndex ] = 0x03030303; /* r3. */ ulIndex++; - xMPUSettings->ulContext[ ulIndex ] = 0x12121212; /* r12. */ + xMPUSettings->ulContext[ ulIndex ] = 0x12121212; /* r12. */ ulIndex++; xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portTASK_RETURN_ADDRESS; /* LR. */ ulIndex++; - xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxCode; /* PC. */ + xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxCode; /* PC. */ ulIndex++; - xMPUSettings->ulContext[ ulIndex ] = portINITIAL_XPSR; /* xPSR. */ + xMPUSettings->ulContext[ ulIndex ] = portINITIAL_XPSR; /* xPSR. */ ulIndex++; #if ( configENABLE_TRUSTZONE == 1 ) @@ -1435,8 +1486,9 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO #endif /* configENABLE_TRUSTZONE */ xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) ( pxTopOfStack - 8 ); /* PSP with the hardware saved stack. */ ulIndex++; - xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxEndOfStack; /* PSPLIM. */ + xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxEndOfStack; /* PSPLIM. */ ulIndex++; + if( xRunPrivileged == pdTRUE ) { xMPUSettings->ulTaskFlags |= portTASK_IS_PRIVILEGED_FLAG; @@ -1449,6 +1501,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portINITIAL_CONTROL_UNPRIVILEGED; /* CONTROL. */ ulIndex++; } + xMPUSettings->ulContext[ ulIndex ] = portINITIAL_EXC_RETURN; /* LR (EXC_RETURN). */ ulIndex++; @@ -1483,7 +1536,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO * interrupt. */ #if ( portPRELOAD_REGISTERS == 0 ) { - pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */ + pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */ *pxTopOfStack = portINITIAL_XPSR; /* xPSR. */ pxTopOfStack--; *pxTopOfStack = ( StackType_t ) pxCode; /* PC. */ @@ -1505,7 +1558,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO } #else /* portPRELOAD_REGISTERS */ { - pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */ + pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */ *pxTopOfStack = portINITIAL_XPSR; /* xPSR. */ pxTopOfStack--; *pxTopOfStack = ( StackType_t ) pxCode; /* PC. */ @@ -1540,7 +1593,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO pxTopOfStack--; *pxTopOfStack = portINITIAL_EXC_RETURN; /* EXC_RETURN. */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */ + *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */ #if ( configENABLE_TRUSTZONE == 1 ) { @@ -1559,22 +1612,52 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */ { - #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) ) + /* An application can install FreeRTOS interrupt handlers in one of the + * folllowing ways: + * 1. Direct Routing - Install the functions SVC_Handler and PendSV_Handler + * for SVCall and PendSV interrupts respectively. + * 2. Indirect Routing - Install separate handlers for SVCall and PendSV + * interrupts and route program control from those handlers to + * SVC_Handler and PendSV_Handler functions. + * + * Applications that use Indirect Routing must set + * configCHECK_HANDLER_INSTALLATION to 0 in their FreeRTOSConfig.h. Direct + * routing, which is validated here when configCHECK_HANDLER_INSTALLATION + * is 1, should be preferred when possible. */ + #if ( configCHECK_HANDLER_INSTALLATION == 1 ) + { + const portISR_t * const pxVectorTable = portSCB_VTOR_REG; + + /* Validate that the application has correctly installed the FreeRTOS + * handlers for SVCall and PendSV interrupts. We do not check the + * installation of the SysTick handler because the application may + * choose to drive the RTOS tick using a timer other than the SysTick + * timer by overriding the weak function vPortSetupTimerInterrupt(). + * + * Assertion failures here indicate incorrect installation of the + * FreeRTOS handlers. For help installing the FreeRTOS handlers, see + * https://www.FreeRTOS.org/FAQHelp.html. + * + * Systems with a configurable address for the interrupt vector table + * can also encounter assertion failures or even system faults here if + * VTOR is not set correctly to point to the application's vector table. */ + configASSERT( pxVectorTable[ portVECTOR_INDEX_SVC ] == SVC_Handler ); + configASSERT( pxVectorTable[ portVECTOR_INDEX_PENDSV ] == PendSV_Handler ); + } + #endif /* configCHECK_HANDLER_INSTALLATION */ + + #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) { - volatile uint32_t ulOriginalPriority; volatile uint32_t ulImplementedPrioBits = 0; volatile uint8_t ucMaxPriorityValue; /* Determine the maximum priority from which ISR safe FreeRTOS API - * functions can be called. ISR safe functions are those that end in - * "FromISR". FreeRTOS maintains separate thread and ISR API functions to + * functions can be called. ISR safe functions are those that end in + * "FromISR". FreeRTOS maintains separate thread and ISR API functions to * ensure interrupt entry is as fast and simple as possible. * - * Save the interrupt priority value that is about to be clobbered. */ - ulOriginalPriority = portNVIC_SHPR2_REG; - - /* Determine the number of priority bits available. First write to all - * possible bits. */ + * First, determine the number of priority bits available. Write to all + * possible bits in the priority setting for SVCall. */ portNVIC_SHPR2_REG = 0xFF000000; /* Read the value back to see how many bits stuck. */ @@ -1593,11 +1676,10 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */ /* Check that the bits not implemented in hardware are zero in * configMAX_SYSCALL_INTERRUPT_PRIORITY. */ - configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( ~ucMaxPriorityValue ) ) == 0U ); + configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( uint8_t ) ( ~( uint32_t ) ucMaxPriorityValue ) ) == 0U ); /* Calculate the maximum acceptable priority group value for the number * of bits read back. */ - while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE ) { ulImplementedPrioBits++; @@ -1635,16 +1717,14 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */ * register. */ ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT; ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK; - - /* Restore the clobbered interrupt priority register to its original - * value. */ - portNVIC_SHPR2_REG = ulOriginalPriority; } - #endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) ) */ + #endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */ - /* Make PendSV, CallSV and SysTick the same priority as the kernel. */ + /* Make PendSV and SysTick the lowest priority interrupts, and make SVCall + * the highest priority. */ portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI; portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI; + portNVIC_SHPR2_REG = 0; #if ( configENABLE_MPU == 1 ) { @@ -1701,6 +1781,7 @@ void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */ int32_t lIndex = 0; #if defined( __ARMCC_VERSION ) + /* Declaration when these variable are defined in code instead of being * exported from linker scripts. */ extern uint32_t * __privileged_sram_start__; @@ -1886,7 +1967,7 @@ BaseType_t xPortIsInsideInterrupt( void ) } /*-----------------------------------------------------------*/ -#if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) ) +#if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) void vPortValidateInterruptPriority( void ) { @@ -1944,7 +2025,7 @@ BaseType_t xPortIsInsideInterrupt( void ) configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue ); } -#endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) ) */ +#endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */ /*-----------------------------------------------------------*/ #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) diff --git a/Source/portable/GCC/ARM_CM85_NTZ/non_secure/portasm.c b/Source/portable/GCC/ARM_CM85_NTZ/non_secure/portasm.c index b3f6a0aac..6169b9358 100644 --- a/Source/portable/GCC/ARM_CM85_NTZ/non_secure/portasm.c +++ b/Source/portable/GCC/ARM_CM85_NTZ/non_secure/portasm.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -75,16 +75,16 @@ " ldmia r0!, {r4-r11} \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */ " stmia r2, {r4-r11} \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */ " \n" - #if ( configTOTAL_MPU_REGIONS == 16 ) - " movs r3, #8 \n" /* r3 = 8. */ - " str r3, [r1] \n" /* Program RNR = 8. */ - " ldmia r0!, {r4-r11} \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */ - " stmia r2, {r4-r11} \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */ - " movs r3, #12 \n" /* r3 = 12. */ - " str r3, [r1] \n" /* Program RNR = 12. */ - " ldmia r0!, {r4-r11} \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */ - " stmia r2, {r4-r11} \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */ - #endif /* configTOTAL_MPU_REGIONS == 16 */ + #if ( configTOTAL_MPU_REGIONS == 16 ) + " movs r3, #8 \n" /* r3 = 8. */ + " str r3, [r1] \n" /* Program RNR = 8. */ + " ldmia r0!, {r4-r11} \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */ + " stmia r2, {r4-r11} \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */ + " movs r3, #12 \n" /* r3 = 12. */ + " str r3, [r1] \n" /* Program RNR = 12. */ + " ldmia r0!, {r4-r11} \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */ + " stmia r2, {r4-r11} \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */ + #endif /* configTOTAL_MPU_REGIONS == 16 */ " \n" " ldr r1, xMPUCTRLConst2 \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */ " ldr r2, [r1] \n" /* Read the value of MPU_CTRL. */ @@ -273,15 +273,15 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att " mrs r2, psp \n" /* r2 = PSP. */ " \n" " save_general_regs: \n" - #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) - " add r2, r2, #0x20 \n" /* Move r2 to location where s0 is saved. */ - " tst lr, #0x10 \n" - " ittt eq \n" - " vstmiaeq r1!, {s16-s31} \n" /* Store s16-s31. */ - " vldmiaeq r2, {s0-s16} \n" /* Copy hardware saved FP context into s0-s16. */ - " vstmiaeq r1!, {s0-s16} \n" /* Store hardware saved FP context. */ - " sub r2, r2, #0x20 \n" /* Set r2 back to the location of hardware saved context. */ - #endif /* configENABLE_FPU || configENABLE_MVE */ + #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) + " add r2, r2, #0x20 \n" /* Move r2 to location where s0 is saved. */ + " tst lr, #0x10 \n" + " ittt eq \n" + " vstmiaeq r1!, {s16-s31} \n" /* Store s16-s31. */ + " vldmiaeq r2, {s0-s16} \n" /* Copy hardware saved FP context into s0-s16. */ + " vstmiaeq r1!, {s0-s16} \n" /* Store hardware saved FP context. */ + " sub r2, r2, #0x20 \n" /* Set r2 back to the location of hardware saved context. */ + #endif /* configENABLE_FPU || configENABLE_MVE */ " \n" " stmia r1!, {r4-r11} \n" /* Store r4-r11. */ " ldmia r2, {r4-r11} \n" /* Copy the hardware saved context into r4-r11. */ @@ -326,16 +326,16 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att " ldmia r0!, {r4-r11} \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */ " stmia r2, {r4-r11} \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */ " \n" - #if ( configTOTAL_MPU_REGIONS == 16 ) - " movs r3, #8 \n" /* r3 = 8. */ - " str r3, [r1] \n" /* Program RNR = 8. */ - " ldmia r0!, {r4-r11} \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */ - " stmia r2, {r4-r11} \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */ - " movs r3, #12 \n" /* r3 = 12. */ - " str r3, [r1] \n" /* Program RNR = 12. */ - " ldmia r0!, {r4-r11} \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */ - " stmia r2, {r4-r11} \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */ - #endif /* configTOTAL_MPU_REGIONS == 16 */ + #if ( configTOTAL_MPU_REGIONS == 16 ) + " movs r3, #8 \n" /* r3 = 8. */ + " str r3, [r1] \n" /* Program RNR = 8. */ + " ldmia r0!, {r4-r11} \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */ + " stmia r2, {r4-r11} \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */ + " movs r3, #12 \n" /* r3 = 12. */ + " str r3, [r1] \n" /* Program RNR = 12. */ + " ldmia r0!, {r4-r11} \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */ + " stmia r2, {r4-r11} \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */ + #endif /* configTOTAL_MPU_REGIONS == 16 */ " \n" " ldr r1, xMPUCTRLConst \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */ " ldr r2, [r1] \n" /* Read the value of MPU_CTRL. */ @@ -358,13 +358,13 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att " ldmdb r1!, {r4-r11} \n" /* r4-r11 contain hardware saved context. */ " stmia r2!, {r4-r11} \n" /* Copy the hardware saved context on the task stack. */ " ldmdb r1!, {r4-r11} \n" /* r4-r11 restored. */ - #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) - " tst lr, #0x10 \n" - " ittt eq \n" - " vldmdbeq r1!, {s0-s16} \n" /* s0-s16 contain hardware saved FP context. */ - " vstmiaeq r2!, {s0-s16} \n" /* Copy hardware saved FP context on the task stack. */ - " vldmdbeq r1!, {s16-s31} \n" /* Restore s16-s31. */ - #endif /* configENABLE_FPU || configENABLE_MVE */ + #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) + " tst lr, #0x10 \n" + " ittt eq \n" + " vldmdbeq r1!, {s0-s16} \n" /* s0-s16 contain hardware saved FP context. */ + " vstmiaeq r2!, {s0-s16} \n" /* Copy hardware saved FP context on the task stack. */ + " vldmdbeq r1!, {s16-s31} \n" /* Restore s16-s31. */ + #endif /* configENABLE_FPU || configENABLE_MVE */ " \n" " restore_context_done: \n" " str r1, [r0] \n" /* Save the location where the context should be saved next as the first member of TCB. */ @@ -390,11 +390,11 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att " \n" " mrs r0, psp \n" /* Read PSP in r0. */ " \n" - #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) - " tst lr, #0x10 \n" /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */ - " it eq \n" - " vstmdbeq r0!, {s16-s31} \n" /* Store the additional FP context registers which are not saved automatically. */ - #endif /* configENABLE_FPU || configENABLE_MVE */ + #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) + " tst lr, #0x10 \n" /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */ + " it eq \n" + " vstmdbeq r0!, {s16-s31} \n" /* Store the additional FP context registers which are not saved automatically. */ + #endif /* configENABLE_FPU || configENABLE_MVE */ " \n" " mrs r2, psplim \n" /* r2 = PSPLIM. */ " mov r3, lr \n" /* r3 = LR/EXC_RETURN. */ @@ -418,11 +418,11 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att " \n" " ldmia r0!, {r2-r11} \n" /* Read from stack - r2 = PSPLIM, r3 = LR and r4-r11 restored. */ " \n" - #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) - " tst r3, #0x10 \n" /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */ - " it eq \n" - " vldmiaeq r0!, {s16-s31} \n" /* Restore the additional FP context registers which are not restored automatically. */ - #endif /* configENABLE_FPU || configENABLE_MVE */ + #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) + " tst r3, #0x10 \n" /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */ + " it eq \n" + " vldmiaeq r0!, {s16-s31} \n" /* Restore the additional FP context registers which are not restored automatically. */ + #endif /* configENABLE_FPU || configENABLE_MVE */ " \n" " msr psplim, r2 \n" /* Restore the PSPLIM register value for the task. */ " msr psp, r0 \n" /* Remember the new top of stack for the task. */ diff --git a/Source/portable/GCC/ARM_CM85_NTZ/non_secure/portasm.h b/Source/portable/GCC/ARM_CM85_NTZ/non_secure/portasm.h index f64ceb525..c6d2ebd58 100644 --- a/Source/portable/GCC/ARM_CM85_NTZ/non_secure/portasm.h +++ b/Source/portable/GCC/ARM_CM85_NTZ/non_secure/portasm.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/Source/portable/GCC/ARM_CM85_NTZ/non_secure/portmacro.h b/Source/portable/GCC/ARM_CM85_NTZ/non_secure/portmacro.h index f606f817d..bd605f630 100644 --- a/Source/portable/GCC/ARM_CM85_NTZ/non_secure/portmacro.h +++ b/Source/portable/GCC/ARM_CM85_NTZ/non_secure/portmacro.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -53,9 +53,9 @@ /** * Architecture specifics. */ -#define portARCH_NAME "Cortex-M85" -#define portHAS_BASEPRI 1 -#define portDONT_DISCARD __attribute__( ( used ) ) +#define portARCH_NAME "Cortex-M85" +#define portHAS_ARMV8M_MAIN_EXTENSION 1 +#define portDONT_DISCARD __attribute__( ( used ) ) /*-----------------------------------------------------------*/ /* ARMv8-M common port configurations. */ @@ -65,8 +65,8 @@ /** * @brief Critical section management. */ -#define portDISABLE_INTERRUPTS() ulSetInterruptMask() -#define portENABLE_INTERRUPTS() vClearInterruptMask( 0 ) +#define portDISABLE_INTERRUPTS() ulSetInterruptMask() +#define portENABLE_INTERRUPTS() vClearInterruptMask( 0 ) /*-----------------------------------------------------------*/ /* *INDENT-OFF* */ diff --git a/Source/portable/GCC/ARM_CM85_NTZ/non_secure/portmacrocommon.h b/Source/portable/GCC/ARM_CM85_NTZ/non_secure/portmacrocommon.h index 6f666da22..33f21d85b 100644 --- a/Source/portable/GCC/ARM_CM85_NTZ/non_secure/portmacrocommon.h +++ b/Source/portable/GCC/ARM_CM85_NTZ/non_secure/portmacrocommon.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -117,7 +117,7 @@ extern uint32_t ulSetInterruptMask( void ) /* __attribute__(( naked )) PRIVILEGE extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */; #if ( configENABLE_TRUSTZONE == 1 ) - extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize ); /* __attribute__ (( naked )) */ + extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize ); /* __attribute__ (( naked )) */ extern void vPortFreeSecureContext( uint32_t * pulTCB ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */; #endif /* configENABLE_TRUSTZONE */ @@ -188,13 +188,13 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P #if ( configENABLE_MPU == 1 ) - /** - * @brief Settings to define an MPU region. - */ +/** + * @brief Settings to define an MPU region. + */ typedef struct MPURegionSettings { - uint32_t ulRBAR; /**< RBAR for the region. */ - uint32_t ulRLAR; /**< RLAR for the region. */ + uint32_t ulRBAR; /**< RBAR for the region. */ + uint32_t ulRLAR; /**< RLAR for the region. */ } MPURegionSettings_t; #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) @@ -203,9 +203,9 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P #error configSYSTEM_CALL_STACK_SIZE must be defined to the desired size of the system call stack in words for using MPU wrappers v2. #endif - /** - * @brief System call stack. - */ +/** + * @brief System call stack. + */ typedef struct SYSTEM_CALL_STACK_INFO { uint32_t ulSystemCallStackBuffer[ configSYSTEM_CALL_STACK_SIZE ]; @@ -218,74 +218,74 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P #endif /* configUSE_MPU_WRAPPERS_V1 == 0 */ - /** - * @brief MPU settings as stored in the TCB. - */ +/** + * @brief MPU settings as stored in the TCB. + */ #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) - #if( configENABLE_TRUSTZONE == 1 ) + #if ( configENABLE_TRUSTZONE == 1 ) - /* - * +-----------+---------------+----------+-----------------+------------------------------+-----+ - * | s16-s31 | s0-s15, FPSCR | r4-r11 | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, | | - * | | | | PC, xPSR | CONTROL, EXC_RETURN | | - * +-----------+---------------+----------+-----------------+------------------------------+-----+ - * - * <-----------><--------------><---------><----------------><-----------------------------><----> - * 16 16 8 8 5 1 - */ - #define MAX_CONTEXT_SIZE 54 +/* + * +-----------+---------------+----------+-----------------+------------------------------+-----+ + * | s16-s31 | s0-s15, FPSCR | r4-r11 | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, | | + * | | | | PC, xPSR | CONTROL, EXC_RETURN | | + * +-----------+---------------+----------+-----------------+------------------------------+-----+ + * + * <-----------><--------------><---------><----------------><-----------------------------><----> + * 16 16 8 8 5 1 + */ + #define MAX_CONTEXT_SIZE 54 #else /* #if( configENABLE_TRUSTZONE == 1 ) */ - /* - * +-----------+---------------+----------+-----------------+----------------------+-----+ - * | s16-s31 | s0-s15, FPSCR | r4-r11 | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL | | - * | | | | PC, xPSR | EXC_RETURN | | - * +-----------+---------------+----------+-----------------+----------------------+-----+ - * - * <-----------><--------------><---------><----------------><---------------------><----> - * 16 16 8 8 4 1 - */ - #define MAX_CONTEXT_SIZE 53 +/* + * +-----------+---------------+----------+-----------------+----------------------+-----+ + * | s16-s31 | s0-s15, FPSCR | r4-r11 | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL | | + * | | | | PC, xPSR | EXC_RETURN | | + * +-----------+---------------+----------+-----------------+----------------------+-----+ + * + * <-----------><--------------><---------><----------------><---------------------><----> + * 16 16 8 8 4 1 + */ + #define MAX_CONTEXT_SIZE 53 #endif /* #if( configENABLE_TRUSTZONE == 1 ) */ #else /* #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */ - #if( configENABLE_TRUSTZONE == 1 ) + #if ( configENABLE_TRUSTZONE == 1 ) - /* - * +----------+-----------------+------------------------------+-----+ - * | r4-r11 | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, | | - * | | PC, xPSR | CONTROL, EXC_RETURN | | - * +----------+-----------------+------------------------------+-----+ - * - * <---------><----------------><------------------------------><----> - * 8 8 5 1 - */ - #define MAX_CONTEXT_SIZE 22 +/* + * +----------+-----------------+------------------------------+-----+ + * | r4-r11 | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, | | + * | | PC, xPSR | CONTROL, EXC_RETURN | | + * +----------+-----------------+------------------------------+-----+ + * + * <---------><----------------><------------------------------><----> + * 8 8 5 1 + */ + #define MAX_CONTEXT_SIZE 22 #else /* #if( configENABLE_TRUSTZONE == 1 ) */ - /* - * +----------+-----------------+----------------------+-----+ - * | r4-r11 | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL | | - * | | PC, xPSR | EXC_RETURN | | - * +----------+-----------------+----------------------+-----+ - * - * <---------><----------------><----------------------><----> - * 8 8 4 1 - */ - #define MAX_CONTEXT_SIZE 21 +/* + * +----------+-----------------+----------------------+-----+ + * | r4-r11 | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL | | + * | | PC, xPSR | EXC_RETURN | | + * +----------+-----------------+----------------------+-----+ + * + * <---------><----------------><----------------------><----> + * 8 8 4 1 + */ + #define MAX_CONTEXT_SIZE 21 #endif /* #if( configENABLE_TRUSTZONE == 1 ) */ #endif /* #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */ - /* Flags used for xMPU_SETTINGS.ulTaskFlags member. */ - #define portSTACK_FRAME_HAS_PADDING_FLAG ( 1UL << 0UL ) - #define portTASK_IS_PRIVILEGED_FLAG ( 1UL << 1UL ) +/* Flags used for xMPU_SETTINGS.ulTaskFlags member. */ + #define portSTACK_FRAME_HAS_PADDING_FLAG ( 1UL << 0UL ) + #define portTASK_IS_PRIVILEGED_FLAG ( 1UL << 1UL ) /* Size of an Access Control List (ACL) entry in bits. */ #define portACL_ENTRY_SIZE_BITS ( 32U ) @@ -313,7 +313,7 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P * system calls. */ #ifdef configASSERT - #if ( portHAS_BASEPRI == 1 ) + #if ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) void vPortValidateInterruptPriority( void ); #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() vPortValidateInterruptPriority() #endif @@ -333,12 +333,29 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P /** * @brief Scheduler utilities. */ -#define portYIELD() vPortYield() +#if ( configENABLE_MPU == 1 ) + #define portYIELD() __asm volatile ( "svc %0" ::"i" ( portSVC_YIELD ) : "memory" ) + #define portYIELD_WITHIN_API() vPortYield() +#else + #define portYIELD() vPortYield() + #define portYIELD_WITHIN_API() vPortYield() +#endif + #define portNVIC_INT_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed04 ) ) #define portNVIC_PENDSVSET_BIT ( 1UL << 28UL ) -#define portEND_SWITCHING_ISR( xSwitchRequired ) \ - do { if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; } \ - while( 0 ) +#define portEND_SWITCHING_ISR( xSwitchRequired ) \ + do \ + { \ + if( xSwitchRequired ) \ + { \ + traceISR_EXIT_TO_SCHEDULER(); \ + portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; \ + } \ + else \ + { \ + traceISR_EXIT(); \ + } \ + } while( 0 ) #define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x ) /*-----------------------------------------------------------*/ @@ -424,12 +441,12 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P extern BaseType_t xPortIsTaskPrivileged( void ); - /** - * @brief Checks whether or not the calling task is privileged. - * - * @return pdTRUE if the calling task is privileged, pdFALSE otherwise. - */ - #define portIS_TASK_PRIVILEGED() xPortIsTaskPrivileged() +/** + * @brief Checks whether or not the calling task is privileged. + * + * @return pdTRUE if the calling task is privileged, pdFALSE otherwise. + */ + #define portIS_TASK_PRIVILEGED() xPortIsTaskPrivileged() #endif /* configENABLE_MPU == 1 */ /*-----------------------------------------------------------*/ @@ -440,6 +457,56 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P #define portMEMORY_BARRIER() __asm volatile ( "" ::: "memory" ) /*-----------------------------------------------------------*/ +/* Select correct value of configUSE_PORT_OPTIMISED_TASK_SELECTION + * based on whether or not Mainline extension is implemented. */ +#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION + #if ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) + #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1 + #else + #define configUSE_PORT_OPTIMISED_TASK_SELECTION 0 + #endif +#endif /* #ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION */ + +/** + * @brief Port-optimised task selection. + */ +#if ( configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 ) + +/** + * @brief Count the number of leading zeros in a 32-bit value. + */ + static portFORCE_INLINE uint32_t ulPortCountLeadingZeros( uint32_t ulBitmap ) + { + uint32_t ulReturn; + + __asm volatile ( "clz %0, %1" : "=r" ( ulReturn ) : "r" ( ulBitmap ) : "memory" ); + + return ulReturn; + } + +/* Check the configuration. */ + #if ( configMAX_PRIORITIES > 32 ) + #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 different priorities as tasks that share a priority will time slice. + #endif + + #if ( portHAS_ARMV8M_MAIN_EXTENSION == 0 ) + #error ARMv8-M baseline implementations (such as Cortex-M23) do not support port-optimised task selection. Please set configUSE_PORT_OPTIMISED_TASK_SELECTION to 0 or leave it undefined. + #endif + +/** + * @brief Store/clear the ready priorities in a bit map. + */ + #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) ) + #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) ) + +/** + * @brief Get the priority of the highest-priority task that is ready to execute. + */ + #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - ulPortCountLeadingZeros( ( uxReadyPriorities ) ) ) + +#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */ +/*-----------------------------------------------------------*/ + /* *INDENT-OFF* */ #ifdef __cplusplus } diff --git a/Source/portable/GCC/ARM_CR5/port.c b/Source/portable/GCC/ARM_CR5/port.c index e675bdf4d..781fb11e1 100644 --- a/Source/portable/GCC/ARM_CR5/port.c +++ b/Source/portable/GCC/ARM_CR5/port.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -161,7 +161,7 @@ portCPU_IRQ_DISABLE(); \ portICCPMR_PRIORITY_MASK_REGISTER = portUNMASK_VALUE; \ __asm volatile ( "DSB \n" \ - "ISB \n"); \ + "ISB \n" ); \ portCPU_IRQ_ENABLE(); \ } @@ -525,7 +525,7 @@ void vPortEnterCritical( void ) ulPortSetInterruptMask(); /* - * Now interrupts are disabled ulCriticalNesting can be accessed + * Now that interrupts are disabled, ulCriticalNesting can be accessed * directly. Increment ulCriticalNesting to keep a count of how many times * portENTER_CRITICAL() has been called. */ @@ -580,7 +580,7 @@ void FreeRTOS_Tick_Handler( void ) portCPU_IRQ_DISABLE(); portICCPMR_PRIORITY_MASK_REGISTER = ( uint32_t ) ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT ); __asm volatile ( "dsb \n" - "isb \n"::: "memory" ); + "isb \n" ::: "memory" ); portCPU_IRQ_ENABLE(); /* Increment the RTOS tick. */ @@ -640,7 +640,7 @@ uint32_t ulPortSetInterruptMask( void ) ulReturn = pdFALSE; portICCPMR_PRIORITY_MASK_REGISTER = ( uint32_t ) ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT ); __asm volatile ( "dsb \n" - "isb \n"::: "memory" ); + "isb \n" ::: "memory" ); } portCPU_IRQ_ENABLE(); diff --git a/Source/portable/GCC/ARM_CR5/portASM.S b/Source/portable/GCC/ARM_CR5/portASM.S index debc22f11..ccf7469a7 100644 --- a/Source/portable/GCC/ARM_CR5/portASM.S +++ b/Source/portable/GCC/ARM_CR5/portASM.S @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/Source/portable/GCC/ARM_CR5/portmacro.h b/Source/portable/GCC/ARM_CR5/portmacro.h index 374e11d5a..a2b60afaa 100644 --- a/Source/portable/GCC/ARM_CR5/portmacro.h +++ b/Source/portable/GCC/ARM_CR5/portmacro.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/Source/portable/GCC/ARM_CRx_No_GIC/port.c b/Source/portable/GCC/ARM_CRx_No_GIC/port.c index 75d0bf710..fd50d6b73 100644 --- a/Source/portable/GCC/ARM_CRx_No_GIC/port.c +++ b/Source/portable/GCC/ARM_CRx_No_GIC/port.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -35,7 +35,7 @@ #if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 /* Check the configuration. */ - #if( configMAX_PRIORITIES > 32 ) + #if ( configMAX_PRIORITIES > 32 ) #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice. #endif #endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */ @@ -49,35 +49,35 @@ #endif /* A critical section is exited when the critical section nesting count reaches -this value. */ -#define portNO_CRITICAL_NESTING ( ( uint32_t ) 0 ) + * this value. */ +#define portNO_CRITICAL_NESTING ( ( uint32_t ) 0 ) /* Tasks are not created with a floating point context, but can be given a -floating point context after they have been created. A variable is stored as -part of the tasks context that holds portNO_FLOATING_POINT_CONTEXT if the task -does not have an FPU context, or any other value if the task does have an FPU -context. */ -#define portNO_FLOATING_POINT_CONTEXT ( ( StackType_t ) 0 ) + * floating point context after they have been created. A variable is stored as + * part of the tasks context that holds portNO_FLOATING_POINT_CONTEXT if the task + * does not have an FPU context, or any other value if the task does have an FPU + * context. */ +#define portNO_FLOATING_POINT_CONTEXT ( ( StackType_t ) 0 ) /* Constants required to setup the initial task context. */ -#define portINITIAL_SPSR ( ( StackType_t ) 0x1f ) /* System mode, ARM mode, IRQ enabled FIQ enabled. */ -#define portTHUMB_MODE_BIT ( ( StackType_t ) 0x20 ) -#define portTHUMB_MODE_ADDRESS ( 0x01UL ) +#define portINITIAL_SPSR ( ( StackType_t ) 0x1f ) /* System mode, ARM mode, IRQ enabled FIQ enabled. */ +#define portTHUMB_MODE_BIT ( ( StackType_t ) 0x20 ) +#define portTHUMB_MODE_ADDRESS ( 0x01UL ) /* Masks all bits in the APSR other than the mode bits. */ -#define portAPSR_MODE_BITS_MASK ( 0x1F ) +#define portAPSR_MODE_BITS_MASK ( 0x1F ) /* The value of the mode bits in the APSR when the CPU is executing in user -mode. */ -#define portAPSR_USER_MODE ( 0x10 ) + * mode. */ +#define portAPSR_USER_MODE ( 0x10 ) /* Let the user override the pre-loading of the initial LR with the address of -prvTaskExitError() in case it messes up unwinding of the stack in the -debugger. */ + * prvTaskExitError() in case it messes up unwinding of the stack in the + * debugger. */ #ifdef configTASK_RETURN_ADDRESS - #define portTASK_RETURN_ADDRESS configTASK_RETURN_ADDRESS + #define portTASK_RETURN_ADDRESS configTASK_RETURN_ADDRESS #else - #define portTASK_RETURN_ADDRESS prvTaskExitError + #define portTASK_RETURN_ADDRESS prvTaskExitError #endif /*-----------------------------------------------------------*/ @@ -96,39 +96,41 @@ static void prvTaskExitError( void ); /*-----------------------------------------------------------*/ /* A variable is used to keep track of the critical section nesting. This -variable has to be stored as part of the task context and must be initialised to -a non zero value to ensure interrupts don't inadvertently become unmasked before -the scheduler starts. As it is stored as part of the task context it will -automatically be set to 0 when the first task is started. */ + * variable has to be stored as part of the task context and must be initialised to + * a non zero value to ensure interrupts don't inadvertently become unmasked before + * the scheduler starts. As it is stored as part of the task context it will + * automatically be set to 0 when the first task is started. */ volatile uint32_t ulCriticalNesting = 9999UL; /* Saved as part of the task context. If ulPortTaskHasFPUContext is non-zero then -a floating point context must be saved and restored for the task. */ + * a floating point context must be saved and restored for the task. */ volatile uint32_t ulPortTaskHasFPUContext = pdFALSE; /* Set to 1 to pend a context switch from an ISR. */ volatile uint32_t ulPortYieldRequired = pdFALSE; /* Counts the interrupt nesting depth. A context switch is only performed if -if the nesting depth is 0. */ + * if the nesting depth is 0. */ volatile uint32_t ulPortInterruptNesting = 0UL; /* Used in the asm file to clear an interrupt. */ -__attribute__(( used )) const uint32_t ulICCEOIR = configEOI_ADDRESS; +__attribute__( ( used ) ) const uint32_t ulICCEOIR = configEOI_ADDRESS; /*-----------------------------------------------------------*/ /* * See header file for description. */ -StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters ) +StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, + TaskFunction_t pxCode, + void * pvParameters ) { /* Setup the initial stack of the task. The stack is set exactly as - expected by the portRESTORE_CONTEXT() macro. - - The fist real value on the stack is the status register, which is set for - system mode, with interrupts enabled. A few NULLs are added first to ensure - GDB does not try decoding a non-existent return address. */ + * expected by the portRESTORE_CONTEXT() macro. + * + * The fist real value on the stack is the status register, which is set for + * system mode, with interrupts enabled. A few NULLs are added first to ensure + * GDB does not try decoding a non-existent return address. */ *pxTopOfStack = ( StackType_t ) NULL; pxTopOfStack--; *pxTopOfStack = ( StackType_t ) NULL; @@ -150,43 +152,43 @@ StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t px pxTopOfStack--; /* Next all the registers other than the stack pointer. */ - *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* R14 */ + *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* R14 */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x12121212; /* R12 */ + *pxTopOfStack = ( StackType_t ) 0x12121212; /* R12 */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x11111111; /* R11 */ + *pxTopOfStack = ( StackType_t ) 0x11111111; /* R11 */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x10101010; /* R10 */ + *pxTopOfStack = ( StackType_t ) 0x10101010; /* R10 */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x09090909; /* R9 */ + *pxTopOfStack = ( StackType_t ) 0x09090909; /* R9 */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x08080808; /* R8 */ + *pxTopOfStack = ( StackType_t ) 0x08080808; /* R8 */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x07070707; /* R7 */ + *pxTopOfStack = ( StackType_t ) 0x07070707; /* R7 */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x06060606; /* R6 */ + *pxTopOfStack = ( StackType_t ) 0x06060606; /* R6 */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x05050505; /* R5 */ + *pxTopOfStack = ( StackType_t ) 0x05050505; /* R5 */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x04040404; /* R4 */ + *pxTopOfStack = ( StackType_t ) 0x04040404; /* R4 */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x03030303; /* R3 */ + *pxTopOfStack = ( StackType_t ) 0x03030303; /* R3 */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x02020202; /* R2 */ + *pxTopOfStack = ( StackType_t ) 0x02020202; /* R2 */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x01010101; /* R1 */ + *pxTopOfStack = ( StackType_t ) 0x01010101; /* R1 */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */ + *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */ pxTopOfStack--; /* The task will start with a critical nesting count of 0 as interrupts are - enabled. */ + * enabled. */ *pxTopOfStack = portNO_CRITICAL_NESTING; pxTopOfStack--; /* The task will start without a floating point context. A task that uses - the floating point hardware must call vPortTaskUsesFPU() before executing - any floating point instructions. */ + * the floating point hardware must call vPortTaskUsesFPU() before executing + * any floating point instructions. */ *pxTopOfStack = portNO_FLOATING_POINT_CONTEXT; return pxTopOfStack; @@ -196,24 +198,28 @@ StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t px static void prvTaskExitError( void ) { /* A function that implements a task must not exit or attempt to return to - its caller as there is nothing to return to. If a task wants to exit it - should instead call vTaskDelete( NULL ). - - Artificially force an assert() to be triggered if configASSERT() is - defined, then stop here so application writers can catch the error. */ + * its caller as there is nothing to return to. If a task wants to exit it + * should instead call vTaskDelete( NULL ). + * + * Artificially force an assert() to be triggered if configASSERT() is + * defined, then stop here so application writers can catch the error. */ configASSERT( ulPortInterruptNesting == ~0UL ); portDISABLE_INTERRUPTS(); - for( ;; ); + + for( ; ; ) + { + } } /*-----------------------------------------------------------*/ BaseType_t xPortStartScheduler( void ) { -uint32_t ulAPSR; + uint32_t ulAPSR; /* Only continue if the CPU is not in User mode. The CPU must be in a - Privileged mode for the scheduler to start. */ - __asm volatile ( "MRS %0, APSR" : "=r" ( ulAPSR ) :: "memory" ); + * Privileged mode for the scheduler to start. */ + __asm volatile ( "MRS %0, APSR" : "=r" ( ulAPSR )::"memory" ); + ulAPSR &= portAPSR_MODE_BITS_MASK; configASSERT( ulAPSR != portAPSR_USER_MODE ); @@ -228,10 +234,10 @@ uint32_t ulAPSR; } /* Will only get here if vTaskStartScheduler() was called with the CPU in - a non-privileged mode or the binary point register was not set to its lowest - possible value. prvTaskExitError() is referenced to prevent a compiler - warning about it being defined but not referenced in the case that the user - defines their own exit address. */ + * a non-privileged mode or the binary point register was not set to its lowest + * possible value. prvTaskExitError() is referenced to prevent a compiler + * warning about it being defined but not referenced in the case that the user + * defines their own exit address. */ ( void ) prvTaskExitError; return 0; } @@ -240,7 +246,7 @@ uint32_t ulAPSR; void vPortEndScheduler( void ) { /* Not implemented in ports where there is nothing to return to. - Artificially force an assert. */ + * Artificially force an assert. */ configASSERT( ulCriticalNesting == 1000UL ); } /*-----------------------------------------------------------*/ @@ -249,16 +255,16 @@ void vPortEnterCritical( void ) { portDISABLE_INTERRUPTS(); - /* Now interrupts are disabled ulCriticalNesting can be accessed - directly. Increment ulCriticalNesting to keep a count of how many times - portENTER_CRITICAL() has been called. */ + /* Now that interrupts are disabled, ulCriticalNesting can be accessed + * directly. Increment ulCriticalNesting to keep a count of how many times + * portENTER_CRITICAL() has been called. */ ulCriticalNesting++; /* This is not the interrupt safe version of the enter critical function so - assert() if it is being called from an interrupt context. Only API - functions that end in "FromISR" can be used in an interrupt. Only assert if - the critical nesting count is 1 to protect against recursive calls if the - assert function also uses a critical section. */ + * assert() if it is being called from an interrupt context. Only API + * functions that end in "FromISR" can be used in an interrupt. Only assert if + * the critical nesting count is 1 to protect against recursive calls if the + * assert function also uses a critical section. */ if( ulCriticalNesting == 1 ) { configASSERT( ulPortInterruptNesting == 0 ); @@ -271,15 +277,15 @@ void vPortExitCritical( void ) if( ulCriticalNesting > portNO_CRITICAL_NESTING ) { /* Decrement the nesting count as the critical section is being - exited. */ + * exited. */ ulCriticalNesting--; /* If the nesting level has reached zero then all interrupt - priorities must be re-enabled. */ + * priorities must be re-enabled. */ if( ulCriticalNesting == portNO_CRITICAL_NESTING ) { /* Critical nesting has reached zero so all interrupt priorities - should be unmasked. */ + * should be unmasked. */ portENABLE_INTERRUPTS(); } } @@ -288,7 +294,7 @@ void vPortExitCritical( void ) void FreeRTOS_Tick_Handler( void ) { -uint32_t ulInterruptStatus; + uint32_t ulInterruptStatus; ulInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR(); @@ -306,13 +312,13 @@ uint32_t ulInterruptStatus; void vPortTaskUsesFPU( void ) { -uint32_t ulInitialFPSCR = 0; + uint32_t ulInitialFPSCR = 0; /* A task is registering the fact that it needs an FPU context. Set the - FPU flag (which is saved as part of the task context). */ + * FPU flag (which is saved as part of the task context). */ ulPortTaskHasFPUContext = pdTRUE; /* Initialise the floating point status register. */ - __asm volatile ( "FMXR FPSCR, %0" :: "r" (ulInitialFPSCR) : "memory" ); + __asm volatile ( "FMXR FPSCR, %0" ::"r" ( ulInitialFPSCR ) : "memory" ); } /*-----------------------------------------------------------*/ diff --git a/Source/portable/GCC/ARM_CRx_No_GIC/portASM.S b/Source/portable/GCC/ARM_CRx_No_GIC/portASM.S index e837af53d..e967d1d89 100644 --- a/Source/portable/GCC/ARM_CRx_No_GIC/portASM.S +++ b/Source/portable/GCC/ARM_CRx_No_GIC/portASM.S @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/Source/portable/GCC/ARM_CRx_No_GIC/portmacro.h b/Source/portable/GCC/ARM_CRx_No_GIC/portmacro.h index f0f7cb5b2..f4b9885c0 100644 --- a/Source/portable/GCC/ARM_CRx_No_GIC/portmacro.h +++ b/Source/portable/GCC/ARM_CRx_No_GIC/portmacro.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -46,55 +46,56 @@ */ /* Type definitions. */ -#define portCHAR char -#define portFLOAT float -#define portDOUBLE double -#define portLONG long -#define portSHORT short -#define portSTACK_TYPE uint32_t -#define portBASE_TYPE long +#define portCHAR char +#define portFLOAT float +#define portDOUBLE double +#define portLONG long +#define portSHORT short +#define portSTACK_TYPE uint32_t +#define portBASE_TYPE long -typedef portSTACK_TYPE StackType_t; -typedef long BaseType_t; -typedef unsigned long UBaseType_t; +typedef portSTACK_TYPE StackType_t; +typedef long BaseType_t; +typedef unsigned long UBaseType_t; -typedef uint32_t TickType_t; -#define portMAX_DELAY ( TickType_t ) 0xffffffffUL +typedef uint32_t TickType_t; +#define portMAX_DELAY ( TickType_t ) 0xffffffffUL /* 32-bit tick type on a 32-bit architecture, so reads of the tick count do -not need to be guarded with a critical section. */ -#define portTICK_TYPE_IS_ATOMIC 1 + * not need to be guarded with a critical section. */ +#define portTICK_TYPE_IS_ATOMIC 1 /*-----------------------------------------------------------*/ /* Hardware specifics. */ -#define portSTACK_GROWTH ( -1 ) -#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) -#define portBYTE_ALIGNMENT 8 +#define portSTACK_GROWTH ( -1 ) +#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) +#define portBYTE_ALIGNMENT 8 /*-----------------------------------------------------------*/ /* Task utilities. */ /* Called at the end of an ISR that can cause a context switch. */ -#define portEND_SWITCHING_ISR( xSwitchRequired )\ -{ \ -extern volatile uint32_t ulPortYieldRequired; \ - \ - if( xSwitchRequired != pdFALSE ) \ - { \ - ulPortYieldRequired = pdTRUE; \ - } \ -} +#define portEND_SWITCHING_ISR( xSwitchRequired ) \ + { \ + extern volatile uint32_t ulPortYieldRequired; \ + \ + if( xSwitchRequired != pdFALSE ) \ + { \ + ulPortYieldRequired = pdTRUE; \ + } \ + } -#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x ) -#define portYIELD() __asm volatile ( "SWI 0 \n" \ - "ISB " ::: "memory" ); +#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x ) +#define portYIELD() \ + __asm volatile ( "SWI 0 \n" \ + "ISB " ::: "memory" ); /*----------------------------------------------------------- - * Critical section control - *----------------------------------------------------------*/ +* Critical section control +*----------------------------------------------------------*/ extern void vPortEnterCritical( void ); extern void vPortExitCritical( void ); @@ -106,74 +107,76 @@ extern void vPortInstallFreeRTOSVectorTable( void ); #define portINTERRUPT_ENABLE_BIT ( 1 << 7 ) /* In the absence of a priority mask register, these functions and macros -globally enable and disable interrupts. */ -#define portENTER_CRITICAL() vPortEnterCritical(); -#define portEXIT_CRITICAL() vPortExitCritical(); -#define portENABLE_INTERRUPTS() __asm volatile ( "CPSIE i \n" ::: "memory" ); -#define portDISABLE_INTERRUPTS() __asm volatile ( "CPSID i \n" \ - "DSB \n" \ - "ISB " ::: "memory" ); + * globally enable and disable interrupts. */ +#define portENTER_CRITICAL() vPortEnterCritical(); +#define portEXIT_CRITICAL() vPortExitCritical(); +#define portENABLE_INTERRUPTS() __asm volatile ( "CPSIE i \n" ::: "memory" ); +#define portDISABLE_INTERRUPTS() \ + __asm volatile ( "CPSID i \n" \ + "DSB \n" \ + "ISB " ::: "memory" ); __attribute__( ( always_inline ) ) static __inline uint32_t portINLINE_SET_INTERRUPT_MASK_FROM_ISR( void ) { -volatile uint32_t ulCPSR; + volatile uint32_t ulCPSR; + + __asm volatile ( "MRS %0, CPSR" : "=r" ( ulCPSR )::"memory" ); - __asm volatile ( "MRS %0, CPSR" : "=r" (ulCPSR) :: "memory" ); ulCPSR &= portINTERRUPT_ENABLE_BIT; portDISABLE_INTERRUPTS(); return ulCPSR; } -#define portSET_INTERRUPT_MASK_FROM_ISR() portINLINE_SET_INTERRUPT_MASK_FROM_ISR() -#define portCLEAR_INTERRUPT_MASK_FROM_ISR(x) do { if( x == 0 ) portENABLE_INTERRUPTS(); } while( 0 ) +#define portSET_INTERRUPT_MASK_FROM_ISR() portINLINE_SET_INTERRUPT_MASK_FROM_ISR() +#define portCLEAR_INTERRUPT_MASK_FROM_ISR( x ) do { if( x == 0 ) portENABLE_INTERRUPTS( ); } while( 0 ) /*-----------------------------------------------------------*/ /* Task function macros as described on the FreeRTOS.org WEB site. These are -not required for this port but included in case common demo code that uses these -macros is used. */ -#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters ) -#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters ) + * not required for this port but included in case common demo code that uses these + * macros is used. */ +#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters ) +#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters ) /* Tickless idle/low power functionality. */ #ifndef portSUPPRESS_TICKS_AND_SLEEP extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime ); - #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime ) vPortSuppressTicksAndSleep( xExpectedIdleTime ) + #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime ) vPortSuppressTicksAndSleep( xExpectedIdleTime ) #endif /* Prototype of the FreeRTOS tick handler. This must be installed as the -handler for whichever peripheral is used to generate the RTOS tick. */ + * handler for whichever peripheral is used to generate the RTOS tick. */ void FreeRTOS_Tick_Handler( void ); /* Any task that uses the floating point unit MUST call vPortTaskUsesFPU() -before any floating point instructions are executed. */ + * before any floating point instructions are executed. */ void vPortTaskUsesFPU( void ); -#define portTASK_USES_FLOATING_POINT() vPortTaskUsesFPU() +#define portTASK_USES_FLOATING_POINT() vPortTaskUsesFPU() -#define portLOWEST_INTERRUPT_PRIORITY ( ( ( uint32_t ) configUNIQUE_INTERRUPT_PRIORITIES ) - 1UL ) -#define portLOWEST_USABLE_INTERRUPT_PRIORITY ( portLOWEST_INTERRUPT_PRIORITY - 1UL ) +#define portLOWEST_INTERRUPT_PRIORITY ( ( ( uint32_t ) configUNIQUE_INTERRUPT_PRIORITIES ) - 1UL ) +#define portLOWEST_USABLE_INTERRUPT_PRIORITY ( portLOWEST_INTERRUPT_PRIORITY - 1UL ) /* Architecture specific optimisations. */ #ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION - #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1 + #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1 #endif #if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 - /* Store/clear the ready priorities in a bit map. */ - #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) ) - #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) ) +/* Store/clear the ready priorities in a bit map. */ + #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) ) + #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) ) - /*-----------------------------------------------------------*/ +/*-----------------------------------------------------------*/ - #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - ( uint32_t ) __builtin_clz( uxReadyPriorities ) ) + #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - ( uint32_t ) __builtin_clz( uxReadyPriorities ) ) #endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */ -#define portNOP() __asm volatile( "NOP" ) -#define portINLINE __inline +#define portNOP() __asm volatile ( "NOP" ) +#define portINLINE __inline -#define portMEMORY_BARRIER() __asm volatile( "" ::: "memory" ) +#define portMEMORY_BARRIER() __asm volatile ( "" ::: "memory" ) /* *INDENT-OFF* */ #ifdef __cplusplus diff --git a/Source/portable/GCC/ATMega323/port.c b/Source/portable/GCC/ATMega323/port.c index c2b242520..3b8948895 100644 --- a/Source/portable/GCC/ATMega323/port.c +++ b/Source/portable/GCC/ATMega323/port.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -27,13 +27,13 @@ */ /* - -Changes from V2.6.0 - - + AVR port - Replaced the inb() and outb() functions with direct memory - access. This allows the port to be built with the 20050414 build of - WinAVR. -*/ + * + * Changes from V2.6.0 + * + + AVR port - Replaced the inb() and outb() functions with direct memory + + access. This allows the port to be built with the 20050414 build of + + WinAVR. + */ #include #include @@ -42,8 +42,8 @@ Changes from V2.6.0 #include "task.h" /*----------------------------------------------------------- - * Implementation of functions defined in portable.h for the AVR port. - *----------------------------------------------------------*/ +* Implementation of functions defined in portable.h for the AVR port. +*----------------------------------------------------------*/ /* Start tasks with interrupts enables. */ #define portFLAGS_INT_ENABLED ( ( StackType_t ) 0x80 ) @@ -57,7 +57,7 @@ Changes from V2.6.0 /*-----------------------------------------------------------*/ /* We require the address of the pxCurrentTCB variable, but don't want to know -any details of its type. */ + * any details of its type. */ typedef void TCB_t; extern volatile TCB_t * volatile pxCurrentTCB; @@ -79,98 +79,98 @@ extern volatile TCB_t * volatile pxCurrentTCB; * so we need not worry about reading/writing to the stack pointer. */ -#define portSAVE_CONTEXT() \ - asm volatile ( "push r0 \n\t" \ - "in r0, __SREG__ \n\t" \ - "cli \n\t" \ - "push r0 \n\t" \ - "push r1 \n\t" \ - "clr r1 \n\t" \ - "push r2 \n\t" \ - "push r3 \n\t" \ - "push r4 \n\t" \ - "push r5 \n\t" \ - "push r6 \n\t" \ - "push r7 \n\t" \ - "push r8 \n\t" \ - "push r9 \n\t" \ - "push r10 \n\t" \ - "push r11 \n\t" \ - "push r12 \n\t" \ - "push r13 \n\t" \ - "push r14 \n\t" \ - "push r15 \n\t" \ - "push r16 \n\t" \ - "push r17 \n\t" \ - "push r18 \n\t" \ - "push r19 \n\t" \ - "push r20 \n\t" \ - "push r21 \n\t" \ - "push r22 \n\t" \ - "push r23 \n\t" \ - "push r24 \n\t" \ - "push r25 \n\t" \ - "push r26 \n\t" \ - "push r27 \n\t" \ - "push r28 \n\t" \ - "push r29 \n\t" \ - "push r30 \n\t" \ - "push r31 \n\t" \ - "lds r26, pxCurrentTCB \n\t" \ - "lds r27, pxCurrentTCB + 1 \n\t" \ - "in r0, 0x3d \n\t" \ - "st x+, r0 \n\t" \ - "in r0, 0x3e \n\t" \ - "st x+, r0 \n\t" \ - ); +#define portSAVE_CONTEXT() \ + asm volatile ( "push r0 \n\t" \ + "in r0, __SREG__ \n\t" \ + "cli \n\t" \ + "push r0 \n\t" \ + "push r1 \n\t" \ + "clr r1 \n\t" \ + "push r2 \n\t" \ + "push r3 \n\t" \ + "push r4 \n\t" \ + "push r5 \n\t" \ + "push r6 \n\t" \ + "push r7 \n\t" \ + "push r8 \n\t" \ + "push r9 \n\t" \ + "push r10 \n\t" \ + "push r11 \n\t" \ + "push r12 \n\t" \ + "push r13 \n\t" \ + "push r14 \n\t" \ + "push r15 \n\t" \ + "push r16 \n\t" \ + "push r17 \n\t" \ + "push r18 \n\t" \ + "push r19 \n\t" \ + "push r20 \n\t" \ + "push r21 \n\t" \ + "push r22 \n\t" \ + "push r23 \n\t" \ + "push r24 \n\t" \ + "push r25 \n\t" \ + "push r26 \n\t" \ + "push r27 \n\t" \ + "push r28 \n\t" \ + "push r29 \n\t" \ + "push r30 \n\t" \ + "push r31 \n\t" \ + "lds r26, pxCurrentTCB \n\t" \ + "lds r27, pxCurrentTCB + 1 \n\t" \ + "in r0, 0x3d \n\t" \ + "st x+, r0 \n\t" \ + "in r0, 0x3e \n\t" \ + "st x+, r0 \n\t" \ + ); /* * Opposite to portSAVE_CONTEXT(). Interrupts will have been disabled during * the context save so we can write to the stack pointer. */ -#define portRESTORE_CONTEXT() \ - asm volatile ( "lds r26, pxCurrentTCB \n\t" \ - "lds r27, pxCurrentTCB + 1 \n\t" \ - "ld r28, x+ \n\t" \ - "out __SP_L__, r28 \n\t" \ - "ld r29, x+ \n\t" \ - "out __SP_H__, r29 \n\t" \ - "pop r31 \n\t" \ - "pop r30 \n\t" \ - "pop r29 \n\t" \ - "pop r28 \n\t" \ - "pop r27 \n\t" \ - "pop r26 \n\t" \ - "pop r25 \n\t" \ - "pop r24 \n\t" \ - "pop r23 \n\t" \ - "pop r22 \n\t" \ - "pop r21 \n\t" \ - "pop r20 \n\t" \ - "pop r19 \n\t" \ - "pop r18 \n\t" \ - "pop r17 \n\t" \ - "pop r16 \n\t" \ - "pop r15 \n\t" \ - "pop r14 \n\t" \ - "pop r13 \n\t" \ - "pop r12 \n\t" \ - "pop r11 \n\t" \ - "pop r10 \n\t" \ - "pop r9 \n\t" \ - "pop r8 \n\t" \ - "pop r7 \n\t" \ - "pop r6 \n\t" \ - "pop r5 \n\t" \ - "pop r4 \n\t" \ - "pop r3 \n\t" \ - "pop r2 \n\t" \ - "pop r1 \n\t" \ - "pop r0 \n\t" \ - "out __SREG__, r0 \n\t" \ - "pop r0 \n\t" \ - ); +#define portRESTORE_CONTEXT() \ + asm volatile ( "lds r26, pxCurrentTCB \n\t" \ + "lds r27, pxCurrentTCB + 1 \n\t" \ + "ld r28, x+ \n\t" \ + "out __SP_L__, r28 \n\t" \ + "ld r29, x+ \n\t" \ + "out __SP_H__, r29 \n\t" \ + "pop r31 \n\t" \ + "pop r30 \n\t" \ + "pop r29 \n\t" \ + "pop r28 \n\t" \ + "pop r27 \n\t" \ + "pop r26 \n\t" \ + "pop r25 \n\t" \ + "pop r24 \n\t" \ + "pop r23 \n\t" \ + "pop r22 \n\t" \ + "pop r21 \n\t" \ + "pop r20 \n\t" \ + "pop r19 \n\t" \ + "pop r18 \n\t" \ + "pop r17 \n\t" \ + "pop r16 \n\t" \ + "pop r15 \n\t" \ + "pop r14 \n\t" \ + "pop r13 \n\t" \ + "pop r12 \n\t" \ + "pop r11 \n\t" \ + "pop r10 \n\t" \ + "pop r9 \n\t" \ + "pop r8 \n\t" \ + "pop r7 \n\t" \ + "pop r6 \n\t" \ + "pop r5 \n\t" \ + "pop r4 \n\t" \ + "pop r3 \n\t" \ + "pop r2 \n\t" \ + "pop r1 \n\t" \ + "pop r0 \n\t" \ + "out __SREG__, r0 \n\t" \ + "pop r0 \n\t" \ + ); /*-----------------------------------------------------------*/ @@ -183,12 +183,14 @@ static void prvSetupTimerInterrupt( void ); /* * See header file for description. */ -StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters ) +StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, + TaskFunction_t pxCode, + void * pvParameters ) { -uint16_t usAddress; + uint16_t usAddress; /* Place a few bytes of known values on the bottom of the stack. - This is just useful for debugging. */ + * This is just useful for debugging. */ *pxTopOfStack = 0x11; pxTopOfStack--; @@ -198,12 +200,12 @@ uint16_t usAddress; pxTopOfStack--; /* Simulate how the stack would look after a call to vPortYield() generated by - the compiler. */ + * the compiler. */ /*lint -e950 -e611 -e923 Lint doesn't like this much - but nothing I can do about it. */ /* The start of the task code will be popped off the stack last, so place - it on first. */ + * it on first. */ usAddress = ( uint16_t ) pxCode; *pxTopOfStack = ( StackType_t ) ( usAddress & ( uint16_t ) 0x00ff ); pxTopOfStack--; @@ -213,61 +215,61 @@ uint16_t usAddress; pxTopOfStack--; /* Next simulate the stack as if after a call to portSAVE_CONTEXT(). - portSAVE_CONTEXT places the flags on the stack immediately after r0 - to ensure the interrupts get disabled as soon as possible, and so ensuring - the stack use is minimal should a context switch interrupt occur. */ - *pxTopOfStack = ( StackType_t ) 0x00; /* R0 */ + * portSAVE_CONTEXT places the flags on the stack immediately after r0 + * to ensure the interrupts get disabled as soon as possible, and so ensuring + * the stack use is minimal should a context switch interrupt occur. */ + *pxTopOfStack = ( StackType_t ) 0x00; /* R0 */ pxTopOfStack--; *pxTopOfStack = portFLAGS_INT_ENABLED; pxTopOfStack--; /* Now the remaining registers. The compiler expects R1 to be 0. */ - *pxTopOfStack = ( StackType_t ) 0x00; /* R1 */ + *pxTopOfStack = ( StackType_t ) 0x00; /* R1 */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x02; /* R2 */ + *pxTopOfStack = ( StackType_t ) 0x02; /* R2 */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x03; /* R3 */ + *pxTopOfStack = ( StackType_t ) 0x03; /* R3 */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x04; /* R4 */ + *pxTopOfStack = ( StackType_t ) 0x04; /* R4 */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x05; /* R5 */ + *pxTopOfStack = ( StackType_t ) 0x05; /* R5 */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x06; /* R6 */ + *pxTopOfStack = ( StackType_t ) 0x06; /* R6 */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x07; /* R7 */ + *pxTopOfStack = ( StackType_t ) 0x07; /* R7 */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x08; /* R8 */ + *pxTopOfStack = ( StackType_t ) 0x08; /* R8 */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x09; /* R9 */ + *pxTopOfStack = ( StackType_t ) 0x09; /* R9 */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x10; /* R10 */ + *pxTopOfStack = ( StackType_t ) 0x10; /* R10 */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x11; /* R11 */ + *pxTopOfStack = ( StackType_t ) 0x11; /* R11 */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x12; /* R12 */ + *pxTopOfStack = ( StackType_t ) 0x12; /* R12 */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x13; /* R13 */ + *pxTopOfStack = ( StackType_t ) 0x13; /* R13 */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x14; /* R14 */ + *pxTopOfStack = ( StackType_t ) 0x14; /* R14 */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x15; /* R15 */ + *pxTopOfStack = ( StackType_t ) 0x15; /* R15 */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x16; /* R16 */ + *pxTopOfStack = ( StackType_t ) 0x16; /* R16 */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x17; /* R17 */ + *pxTopOfStack = ( StackType_t ) 0x17; /* R17 */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x18; /* R18 */ + *pxTopOfStack = ( StackType_t ) 0x18; /* R18 */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x19; /* R19 */ + *pxTopOfStack = ( StackType_t ) 0x19; /* R19 */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x20; /* R20 */ + *pxTopOfStack = ( StackType_t ) 0x20; /* R20 */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x21; /* R21 */ + *pxTopOfStack = ( StackType_t ) 0x21; /* R21 */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x22; /* R22 */ + *pxTopOfStack = ( StackType_t ) 0x22; /* R22 */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x23; /* R23 */ + *pxTopOfStack = ( StackType_t ) 0x23; /* R23 */ pxTopOfStack--; /* Place the parameter on the stack in the expected location. */ @@ -279,17 +281,17 @@ uint16_t usAddress; *pxTopOfStack = ( StackType_t ) ( usAddress & ( uint16_t ) 0x00ff ); pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x26; /* R26 X */ + *pxTopOfStack = ( StackType_t ) 0x26; /* R26 X */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x27; /* R27 */ + *pxTopOfStack = ( StackType_t ) 0x27; /* R27 */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x28; /* R28 Y */ + *pxTopOfStack = ( StackType_t ) 0x28; /* R28 Y */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x29; /* R29 */ + *pxTopOfStack = ( StackType_t ) 0x29; /* R29 */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x30; /* R30 Z */ + *pxTopOfStack = ( StackType_t ) 0x30; /* R30 Z */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x031; /* R31 */ + *pxTopOfStack = ( StackType_t ) 0x031; /* R31 */ pxTopOfStack--; /*lint +e950 +e611 +e923 */ @@ -307,7 +309,7 @@ BaseType_t xPortStartScheduler( void ) portRESTORE_CONTEXT(); /* Simulate a function call end as generated by the compiler. We will now - jump to the start of the task the context of which we have just restored. */ + * jump to the start of the task the context of which we have just restored. */ asm volatile ( "ret" ); /* Should not get here. */ @@ -318,7 +320,7 @@ BaseType_t xPortStartScheduler( void ) void vPortEndScheduler( void ) { /* It is unlikely that the AVR port will get stopped. If required simply - disable the tick interrupt here. */ + * disable the tick interrupt here. */ } /*-----------------------------------------------------------*/ @@ -326,7 +328,7 @@ void vPortEndScheduler( void ) * Manual context switch. The first thing we do is save the registers so we * can use a naked attribute. */ -void vPortYield( void ) __attribute__ ( ( naked ) ); +void vPortYield( void ) __attribute__( ( naked ) ); void vPortYield( void ) { portSAVE_CONTEXT(); @@ -343,14 +345,16 @@ void vPortYield( void ) * difference from vPortYield() is the tick count is incremented as the * call comes from the tick ISR. */ -void vPortYieldFromTick( void ) __attribute__ ( ( naked ) ); +void vPortYieldFromTick( void ) __attribute__( ( naked ) ); void vPortYieldFromTick( void ) { portSAVE_CONTEXT(); + if( xTaskIncrementTick() != pdFALSE ) { vTaskSwitchContext(); } + portRESTORE_CONTEXT(); asm volatile ( "ret" ); @@ -362,11 +366,11 @@ void vPortYieldFromTick( void ) */ static void prvSetupTimerInterrupt( void ) { -uint32_t ulCompareMatch; -uint8_t ucHighByte, ucLowByte; + uint32_t ulCompareMatch; + uint8_t ucHighByte, ucLowByte; /* Using 16bit timer 1 to generate the tick. Correct fuses must be - selected for the configCPU_CLOCK_HZ clock. */ + * selected for the configCPU_CLOCK_HZ clock. */ ulCompareMatch = configCPU_CLOCK_HZ / configTICK_RATE_HZ; @@ -377,7 +381,7 @@ uint8_t ucHighByte, ucLowByte; ulCompareMatch -= ( uint32_t ) 1; /* Setup compare match value for compare match A. Interrupts are disabled - before this is called so we need not worry here. */ + * before this is called so we need not worry here. */ ucLowByte = ( uint8_t ) ( ulCompareMatch & ( uint32_t ) 0xff ); ulCompareMatch >>= 8; ucHighByte = ( uint8_t ) ( ulCompareMatch & ( uint32_t ) 0xff ); @@ -389,7 +393,7 @@ uint8_t ucHighByte, ucLowByte; TCCR1B = ucLowByte; /* Enable the interrupt - this is okay as interrupt are currently globally - disabled. */ + * disabled. */ ucLowByte = TIMSK; ucLowByte |= portCOMPARE_MATCH_A_INTERRUPT_ENABLE; TIMSK = ucLowByte; @@ -398,12 +402,12 @@ uint8_t ucHighByte, ucLowByte; #if configUSE_PREEMPTION == 1 - /* - * Tick ISR for preemptive scheduler. We can use a naked attribute as - * the context is saved at the start of vPortYieldFromTick(). The tick - * count is incremented after the context is saved. - */ - void TIMER1_COMPA_vect( void ) __attribute__ ( ( signal, naked ) ); +/* + * Tick ISR for preemptive scheduler. We can use a naked attribute as + * the context is saved at the start of vPortYieldFromTick(). The tick + * count is incremented after the context is saved. + */ + void TIMER1_COMPA_vect( void ) __attribute__( ( signal, naked ) ); void TIMER1_COMPA_vect( void ) { vPortYieldFromTick(); @@ -411,17 +415,14 @@ uint8_t ucHighByte, ucLowByte; } #else - /* - * Tick ISR for the cooperative scheduler. All this does is increment the - * tick count. We don't need to switch context, this can only be done by - * manual calls to taskYIELD(); - */ - void TIMER1_COMPA_vect( void ) __attribute__ ( ( signal ) ); +/* + * Tick ISR for the cooperative scheduler. All this does is increment the + * tick count. We don't need to switch context, this can only be done by + * manual calls to taskYIELD(); + */ + void TIMER1_COMPA_vect( void ) __attribute__( ( signal ) ); void TIMER1_COMPA_vect( void ) { xTaskIncrementTick(); } -#endif - - - +#endif /* if configUSE_PREEMPTION == 1 */ diff --git a/Source/portable/GCC/ATMega323/portmacro.h b/Source/portable/GCC/ATMega323/portmacro.h index 78d2b6020..dcb338d8a 100644 --- a/Source/portable/GCC/ATMega323/portmacro.h +++ b/Source/portable/GCC/ATMega323/portmacro.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -27,11 +27,11 @@ */ /* -Changes from V1.2.3 - - + portCPU_CLOSK_HZ definition changed to 8MHz base 10, previously it - base 16. -*/ + * Changes from V1.2.3 + * + + portCPU_CLOCK_HZ definition changed to 8MHz base 10, previously it + + base 16. + */ #ifndef PORTMACRO_H #define PORTMACRO_H @@ -53,58 +53,60 @@ Changes from V1.2.3 */ /* Type definitions. */ -#define portCHAR char -#define portFLOAT float -#define portDOUBLE double -#define portLONG long -#define portSHORT int -#define portSTACK_TYPE uint8_t -#define portBASE_TYPE char +#define portCHAR char +#define portFLOAT float +#define portDOUBLE double +#define portLONG long +#define portSHORT int +#define portSTACK_TYPE uint8_t +#define portBASE_TYPE char #define portPOINTER_SIZE_TYPE uint16_t -typedef portSTACK_TYPE StackType_t; -typedef signed char BaseType_t; -typedef unsigned char UBaseType_t; +typedef portSTACK_TYPE StackType_t; +typedef signed char BaseType_t; +typedef unsigned char UBaseType_t; -#if( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS ) - typedef uint16_t TickType_t; - #define portMAX_DELAY ( TickType_t ) 0xffff +#if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS ) + typedef uint16_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffff #elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS ) - typedef uint32_t TickType_t; - #define portMAX_DELAY ( TickType_t ) ( 0xFFFFFFFFUL ) + typedef uint32_t TickType_t; + #define portMAX_DELAY ( TickType_t ) ( 0xFFFFFFFFUL ) #else #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width. #endif /*-----------------------------------------------------------*/ /* Critical section management. */ -#define portENTER_CRITICAL() asm volatile ( "in __tmp_reg__, __SREG__" :: ); \ - asm volatile ( "cli" :: ); \ - asm volatile ( "push __tmp_reg__" :: ) +#define portENTER_CRITICAL() \ + asm volatile ( "in __tmp_reg__, __SREG__" ::); \ + asm volatile ( "cli" ::); \ + asm volatile ( "push __tmp_reg__" ::) -#define portEXIT_CRITICAL() asm volatile ( "pop __tmp_reg__" :: ); \ - asm volatile ( "out __SREG__, __tmp_reg__" :: ) +#define portEXIT_CRITICAL() \ + asm volatile ( "pop __tmp_reg__" ::); \ + asm volatile ( "out __SREG__, __tmp_reg__" ::) -#define portDISABLE_INTERRUPTS() asm volatile ( "cli" :: ); -#define portENABLE_INTERRUPTS() asm volatile ( "sei" :: ); +#define portDISABLE_INTERRUPTS() asm volatile ( "cli" ::); +#define portENABLE_INTERRUPTS() asm volatile ( "sei" ::); /*-----------------------------------------------------------*/ /* Architecture specifics. */ -#define portSTACK_GROWTH ( -1 ) -#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) -#define portBYTE_ALIGNMENT 1 -#define portNOP() asm volatile ( "nop" ); +#define portSTACK_GROWTH ( -1 ) +#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) +#define portBYTE_ALIGNMENT 1 +#define portNOP() asm volatile ( "nop" ); /*-----------------------------------------------------------*/ /* Kernel utilities. */ -extern void vPortYield( void ) __attribute__ ( ( naked ) ); -#define portYIELD() vPortYield() +extern void vPortYield( void ) __attribute__( ( naked ) ); +#define portYIELD() vPortYield() /*-----------------------------------------------------------*/ /* Task function macros as described on the FreeRTOS.org WEB site. */ -#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters ) -#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters ) +#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters ) +#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters ) /* *INDENT-OFF* */ #ifdef __cplusplus diff --git a/Source/portable/GCC/AVR32_UC3/exception.S b/Source/portable/GCC/AVR32_UC3/exception.S index df99bac08..a321d14a2 100644 --- a/Source/portable/GCC/AVR32_UC3/exception.S +++ b/Source/portable/GCC/AVR32_UC3/exception.S @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT AND BSD-3-Clause diff --git a/Source/portable/GCC/AVR32_UC3/port.c b/Source/portable/GCC/AVR32_UC3/port.c index c0533c3b1..45a4ed6bc 100644 --- a/Source/portable/GCC/AVR32_UC3/port.c +++ b/Source/portable/GCC/AVR32_UC3/port.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT AND BSD-3-Clause @@ -27,6 +27,7 @@ */ /*This file has been prepared for Doxygen automatic documentation generation.*/ + /*! \file ********************************************************************* * * \brief FreeRTOS port source for AVR32 UC3. @@ -81,20 +82,20 @@ /* AVR32 UC3 includes. */ #include #include "gpio.h" -#if( configTICK_USE_TC==1 ) +#if ( configTICK_USE_TC == 1 ) #include "tc.h" #endif /* Constants required to setup the task context. */ -#define portINITIAL_SR ( ( StackType_t ) 0x00400000 ) /* AVR32 : [M2:M0]=001 I1M=0 I0M=0, GM=0 */ -#define portINSTRUCTION_SIZE ( ( StackType_t ) 0 ) +#define portINITIAL_SR ( ( StackType_t ) 0x00400000 ) /* AVR32 : [M2:M0]=001 I1M=0 I0M=0, GM=0 */ +#define portINSTRUCTION_SIZE ( ( StackType_t ) 0 ) /* Each task maintains its own critical nesting variable. */ -#define portNO_CRITICAL_NESTING ( ( uint32_t ) 0 ) +#define portNO_CRITICAL_NESTING ( ( uint32_t ) 0 ) volatile uint32_t ulCriticalNesting = 9999UL; -#if( configTICK_USE_TC==0 ) +#if ( configTICK_USE_TC == 0 ) static void prvScheduleNextTick( void ); #else static void prvClearTcInt( void ); @@ -113,7 +114,7 @@ static void prvSetupTimerInterrupt( void ); * vectors are not compatible with the SCALL management in the current FreeRTOS * port. More low-level initializations are besides added here. */ -void _init_startup(void) +void _init_startup( void ) { /* Import the Exception Vector Base Address. */ extern void _evba; @@ -121,7 +122,7 @@ void _init_startup(void) #if configHEAP_INIT extern void __heap_start__; extern void __heap_end__; - BaseType_t *pxMem; + BaseType_t * pxMem; #endif /* Load the Exception Vector Base Address in the corresponding system register. */ @@ -134,13 +135,11 @@ void _init_startup(void) INTC_init_interrupts(); #if configHEAP_INIT - /* Initialize the heap used by malloc. */ - for( pxMem = &__heap_start__; pxMem < ( BaseType_t * )&__heap_end__; ) + for( pxMem = &__heap_start__; pxMem < ( BaseType_t * ) &__heap_end__; ) { *pxMem++ = 0xA5A5A5A5; } - #endif /* Give the used CPU clock frequency to Newlib, so it can work properly. */ @@ -158,10 +157,10 @@ void _init_startup(void) /* Initialize the USART used for the debug trace with the configured parameters. */ set_usart_base( ( void * ) configDBG_USART ); gpio_enable_module( DBG_USART_GPIO_MAP, - sizeof( DBG_USART_GPIO_MAP ) / sizeof( DBG_USART_GPIO_MAP[0] ) ); + sizeof( DBG_USART_GPIO_MAP ) / sizeof( DBG_USART_GPIO_MAP[ 0 ] ) ); usart_init( configDBG_USART_BAUDRATE ); } - #endif + #endif /* if configDBG */ } /*-----------------------------------------------------------*/ @@ -184,7 +183,7 @@ void _init_startup(void) * safe section as memory allocation management uses global data. * See the aforementioned details. */ -void __malloc_lock(struct _reent *ptr) +void __malloc_lock( struct _reent * ptr ) { vTaskSuspendAll(); } @@ -194,16 +193,17 @@ void __malloc_lock(struct _reent *ptr) * a safe section as memory allocation management uses global data. * See the aforementioned details. */ -void __malloc_unlock(struct _reent *ptr) +void __malloc_unlock( struct _reent * ptr ) { xTaskResumeAll(); } /*-----------------------------------------------------------*/ /* Added as there is no such function in FreeRTOS. */ -void *pvPortRealloc( void *pv, size_t xWantedSize ) +void * pvPortRealloc( void * pv, + size_t xWantedSize ) { -void *pvReturn; + void * pvReturn; vTaskSuspendAll(); { @@ -216,27 +216,29 @@ void *pvReturn; /*-----------------------------------------------------------*/ /* The cooperative scheduler requires a normal IRQ service routine to -simply increment the system tick. */ + * simply increment the system tick. */ + /* The preemptive scheduler is defined as "naked" as the full context is saved -on entry as part of the context switch. */ -__attribute__((__naked__)) static void vTick( void ) + * on entry as part of the context switch. */ +__attribute__( ( __naked__ ) ) static void vTick( void ) { /* Save the context of the interrupted task. */ portSAVE_CONTEXT_OS_INT(); - #if( configTICK_USE_TC==1 ) + #if ( configTICK_USE_TC == 1 ) /* Clear the interrupt flag. */ prvClearTcInt(); #else + /* Schedule the COUNT&COMPARE match interrupt in (configCPU_CLOCK_HZ/configTICK_RATE_HZ) - clock cycles from now. */ + * clock cycles from now. */ prvScheduleNextTick(); #endif /* Because FreeRTOS is not supposed to run with nested interrupts, put all OS - calls in a critical section . */ + * calls in a critical section . */ portENTER_CRITICAL(); - xTaskIncrementTick(); + xTaskIncrementTick(); portEXIT_CRITICAL(); /* Restore the context of the "elected task". */ @@ -244,7 +246,7 @@ __attribute__((__naked__)) static void vTick( void ) } /*-----------------------------------------------------------*/ -__attribute__((__naked__)) void SCALLYield( void ) +__attribute__( ( __naked__ ) ) void SCALLYield( void ) { /* Save the context of the interrupted task. */ portSAVE_CONTEXT_SCALL(); @@ -254,26 +256,27 @@ __attribute__((__naked__)) void SCALLYield( void ) /*-----------------------------------------------------------*/ /* The code generated by the GCC compiler uses the stack in different ways at -different optimisation levels. The interrupt flags can therefore not always -be saved to the stack. Instead the critical section nesting level is stored -in a variable, which is then saved as part of the stack context. */ -__attribute__((__noinline__)) void vPortEnterCritical( void ) + * different optimisation levels. The interrupt flags can therefore not always + * be saved to the stack. Instead the critical section nesting level is stored + * in a variable, which is then saved as part of the stack context. */ +__attribute__( ( __noinline__ ) ) void vPortEnterCritical( void ) { /* Disable interrupts */ portDISABLE_INTERRUPTS(); - /* Now interrupts are disabled ulCriticalNesting can be accessed - directly. Increment ulCriticalNesting to keep a count of how many times - portENTER_CRITICAL() has been called. */ + /* Now that interrupts are disabled, ulCriticalNesting can be accessed + * directly. Increment ulCriticalNesting to keep a count of how many times + * portENTER_CRITICAL() has been called. */ ulCriticalNesting++; } /*-----------------------------------------------------------*/ -__attribute__((__noinline__)) void vPortExitCritical( void ) +__attribute__( ( __noinline__ ) ) void vPortExitCritical( void ) { - if(ulCriticalNesting > portNO_CRITICAL_NESTING) + if( ulCriticalNesting > portNO_CRITICAL_NESTING ) { ulCriticalNesting--; + if( ulCriticalNesting == portNO_CRITICAL_NESTING ) { /* Enable all interrupt/exception. */ @@ -289,30 +292,32 @@ __attribute__((__noinline__)) void vPortExitCritical( void ) * * See header file for description. */ -StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters ) +StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, + TaskFunction_t pxCode, + void * pvParameters ) { /* Setup the initial stack of the task. The stack is set exactly as - expected by the portRESTORE_CONTEXT() macro. */ + * expected by the portRESTORE_CONTEXT() macro. */ /* When the task starts, it will expect to find the function parameter in R12. */ pxTopOfStack--; - *pxTopOfStack-- = ( StackType_t ) 0x08080808; /* R8 */ - *pxTopOfStack-- = ( StackType_t ) 0x09090909; /* R9 */ - *pxTopOfStack-- = ( StackType_t ) 0x0A0A0A0A; /* R10 */ - *pxTopOfStack-- = ( StackType_t ) 0x0B0B0B0B; /* R11 */ - *pxTopOfStack-- = ( StackType_t ) pvParameters; /* R12 */ - *pxTopOfStack-- = ( StackType_t ) 0xDEADBEEF; /* R14/LR */ + *pxTopOfStack-- = ( StackType_t ) 0x08080808; /* R8 */ + *pxTopOfStack-- = ( StackType_t ) 0x09090909; /* R9 */ + *pxTopOfStack-- = ( StackType_t ) 0x0A0A0A0A; /* R10 */ + *pxTopOfStack-- = ( StackType_t ) 0x0B0B0B0B; /* R11 */ + *pxTopOfStack-- = ( StackType_t ) pvParameters; /* R12 */ + *pxTopOfStack-- = ( StackType_t ) 0xDEADBEEF; /* R14/LR */ *pxTopOfStack-- = ( StackType_t ) pxCode + portINSTRUCTION_SIZE; /* R15/PC */ - *pxTopOfStack-- = ( StackType_t ) portINITIAL_SR; /* SR */ - *pxTopOfStack-- = ( StackType_t ) 0xFF0000FF; /* R0 */ - *pxTopOfStack-- = ( StackType_t ) 0x01010101; /* R1 */ - *pxTopOfStack-- = ( StackType_t ) 0x02020202; /* R2 */ - *pxTopOfStack-- = ( StackType_t ) 0x03030303; /* R3 */ - *pxTopOfStack-- = ( StackType_t ) 0x04040404; /* R4 */ - *pxTopOfStack-- = ( StackType_t ) 0x05050505; /* R5 */ - *pxTopOfStack-- = ( StackType_t ) 0x06060606; /* R6 */ - *pxTopOfStack-- = ( StackType_t ) 0x07070707; /* R7 */ - *pxTopOfStack = ( StackType_t ) portNO_CRITICAL_NESTING; /* ulCriticalNesting */ + *pxTopOfStack-- = ( StackType_t ) portINITIAL_SR; /* SR */ + *pxTopOfStack-- = ( StackType_t ) 0xFF0000FF; /* R0 */ + *pxTopOfStack-- = ( StackType_t ) 0x01010101; /* R1 */ + *pxTopOfStack-- = ( StackType_t ) 0x02020202; /* R2 */ + *pxTopOfStack-- = ( StackType_t ) 0x03030303; /* R3 */ + *pxTopOfStack-- = ( StackType_t ) 0x04040404; /* R4 */ + *pxTopOfStack-- = ( StackType_t ) 0x05050505; /* R5 */ + *pxTopOfStack-- = ( StackType_t ) 0x06060606; /* R6 */ + *pxTopOfStack-- = ( StackType_t ) 0x07070707; /* R7 */ + *pxTopOfStack = ( StackType_t ) portNO_CRITICAL_NESTING; /* ulCriticalNesting */ return pxTopOfStack; } @@ -321,7 +326,7 @@ StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t px BaseType_t xPortStartScheduler( void ) { /* Start the timer that generates the tick ISR. Interrupts are disabled - here already. */ + * here already. */ prvSetupTimerInterrupt(); /* Start the first task. */ @@ -335,130 +340,134 @@ BaseType_t xPortStartScheduler( void ) void vPortEndScheduler( void ) { /* It is unlikely that the AVR32 port will require this function as there - is nothing to return to. */ + * is nothing to return to. */ } /*-----------------------------------------------------------*/ /* Schedule the COUNT&COMPARE match interrupt in (configCPU_CLOCK_HZ/configTICK_RATE_HZ) -clock cycles from now. */ -#if( configTICK_USE_TC==0 ) - static void prvScheduleFirstTick(void) + * clock cycles from now. */ +#if ( configTICK_USE_TC == 0 ) + static void prvScheduleFirstTick( void ) { uint32_t lCycles; - lCycles = Get_system_register(AVR32_COUNT); - lCycles += (configCPU_CLOCK_HZ/configTICK_RATE_HZ); - // If lCycles ends up to be 0, make it 1 so that the COMPARE and exception - // generation feature does not get disabled. - if(0 == lCycles) + lCycles = Get_system_register( AVR32_COUNT ); + lCycles += ( configCPU_CLOCK_HZ / configTICK_RATE_HZ ); + + /* If lCycles ends up to be 0, make it 1 so that the COMPARE and exception */ + /* generation feature does not get disabled. */ + if( 0 == lCycles ) { lCycles++; } - Set_system_register(AVR32_COMPARE, lCycles); + + Set_system_register( AVR32_COMPARE, lCycles ); } - __attribute__((__noinline__)) static void prvScheduleNextTick(void) + __attribute__( ( __noinline__ ) ) static void prvScheduleNextTick( void ) { uint32_t lCycles, lCount; - lCycles = Get_system_register(AVR32_COMPARE); - lCycles += (configCPU_CLOCK_HZ/configTICK_RATE_HZ); - // If lCycles ends up to be 0, make it 1 so that the COMPARE and exception - // generation feature does not get disabled. - if(0 == lCycles) + lCycles = Get_system_register( AVR32_COMPARE ); + lCycles += ( configCPU_CLOCK_HZ / configTICK_RATE_HZ ); + + /* If lCycles ends up to be 0, make it 1 so that the COMPARE and exception */ + /* generation feature does not get disabled. */ + if( 0 == lCycles ) { lCycles++; } - lCount = Get_system_register(AVR32_COUNT); + + lCount = Get_system_register( AVR32_COUNT ); + if( lCycles < lCount ) - { // We missed a tick, recover for the next. - lCycles += (configCPU_CLOCK_HZ/configTICK_RATE_HZ); + { /* We missed a tick, recover for the next. */ + lCycles += ( configCPU_CLOCK_HZ / configTICK_RATE_HZ ); } - Set_system_register(AVR32_COMPARE, lCycles); + + Set_system_register( AVR32_COMPARE, lCycles ); } -#else - __attribute__((__noinline__)) static void prvClearTcInt(void) +#else /* if ( configTICK_USE_TC == 0 ) */ + __attribute__( ( __noinline__ ) ) static void prvClearTcInt( void ) { - AVR32_TC.channel[configTICK_TC_CHANNEL].sr; + AVR32_TC.channel[ configTICK_TC_CHANNEL ].sr; } -#endif +#endif /* if ( configTICK_USE_TC == 0 ) */ /*-----------------------------------------------------------*/ /* Setup the timer to generate the tick interrupts. */ -static void prvSetupTimerInterrupt(void) +static void prvSetupTimerInterrupt( void ) { -#if( configTICK_USE_TC==1 ) - - volatile avr32_tc_t *tc = &AVR32_TC; + #if ( configTICK_USE_TC == 1 ) + volatile avr32_tc_t * tc = &AVR32_TC; - // Options for waveform genration. - tc_waveform_opt_t waveform_opt = - { - .channel = configTICK_TC_CHANNEL, /* Channel selection. */ - - .bswtrg = TC_EVT_EFFECT_NOOP, /* Software trigger effect on TIOB. */ - .beevt = TC_EVT_EFFECT_NOOP, /* External event effect on TIOB. */ - .bcpc = TC_EVT_EFFECT_NOOP, /* RC compare effect on TIOB. */ - .bcpb = TC_EVT_EFFECT_NOOP, /* RB compare effect on TIOB. */ - - .aswtrg = TC_EVT_EFFECT_NOOP, /* Software trigger effect on TIOA. */ - .aeevt = TC_EVT_EFFECT_NOOP, /* External event effect on TIOA. */ - .acpc = TC_EVT_EFFECT_NOOP, /* RC compare effect on TIOA: toggle. */ - .acpa = TC_EVT_EFFECT_NOOP, /* RA compare effect on TIOA: toggle (other possibilities are none, set and clear). */ - - .wavsel = TC_WAVEFORM_SEL_UP_MODE_RC_TRIGGER,/* Waveform selection: Up mode without automatic trigger on RC compare. */ - .enetrg = FALSE, /* External event trigger enable. */ - .eevt = 0, /* External event selection. */ - .eevtedg = TC_SEL_NO_EDGE, /* External event edge selection. */ - .cpcdis = FALSE, /* Counter disable when RC compare. */ - .cpcstop = FALSE, /* Counter clock stopped with RC compare. */ - - .burst = FALSE, /* Burst signal selection. */ - .clki = FALSE, /* Clock inversion. */ - .tcclks = TC_CLOCK_SOURCE_TC2 /* Internal source clock 2. */ - }; - - tc_interrupt_t tc_interrupt = - { - .etrgs=0, - .ldrbs=0, - .ldras=0, - .cpcs =1, - .cpbs =0, - .cpas =0, - .lovrs=0, - .covfs=0, - }; + /* Options for waveform genration. */ + tc_waveform_opt_t waveform_opt = + { + .channel = configTICK_TC_CHANNEL, /* Channel selection. */ + + .bswtrg = TC_EVT_EFFECT_NOOP, /* Software trigger effect on TIOB. */ + .beevt = TC_EVT_EFFECT_NOOP, /* External event effect on TIOB. */ + .bcpc = TC_EVT_EFFECT_NOOP, /* RC compare effect on TIOB. */ + .bcpb = TC_EVT_EFFECT_NOOP, /* RB compare effect on TIOB. */ + + .aswtrg = TC_EVT_EFFECT_NOOP, /* Software trigger effect on TIOA. */ + .aeevt = TC_EVT_EFFECT_NOOP, /* External event effect on TIOA. */ + .acpc = TC_EVT_EFFECT_NOOP, /* RC compare effect on TIOA: toggle. */ + .acpa = TC_EVT_EFFECT_NOOP, /* RA compare effect on TIOA: toggle (other possibilities are none, set and clear). */ + + .wavsel = TC_WAVEFORM_SEL_UP_MODE_RC_TRIGGER, /* Waveform selection: Up mode without automatic trigger on RC compare. */ + .enetrg = FALSE, /* External event trigger enable. */ + .eevt = 0, /* External event selection. */ + .eevtedg = TC_SEL_NO_EDGE, /* External event edge selection. */ + .cpcdis = FALSE, /* Counter disable when RC compare. */ + .cpcstop = FALSE, /* Counter clock stopped with RC compare. */ + + .burst = FALSE, /* Burst signal selection. */ + .clki = FALSE, /* Clock inversion. */ + .tcclks = TC_CLOCK_SOURCE_TC2 /* Internal source clock 2. */ + }; -#endif + tc_interrupt_t tc_interrupt = + { + .etrgs = 0, + .ldrbs = 0, + .ldras = 0, + .cpcs = 1, + .cpbs = 0, + .cpas = 0, + .lovrs = 0, + .covfs = 0, + }; + #endif /* if ( configTICK_USE_TC == 1 ) */ /* Disable all interrupt/exception. */ portDISABLE_INTERRUPTS(); /* Register the compare interrupt handler to the interrupt controller and - enable the compare interrupt. */ + * enable the compare interrupt. */ - #if( configTICK_USE_TC==1 ) + #if ( configTICK_USE_TC == 1 ) { - INTC_register_interrupt(&vTick, configTICK_TC_IRQ, INT0); + INTC_register_interrupt( &vTick, configTICK_TC_IRQ, INT0 ); /* Initialize the timer/counter. */ - tc_init_waveform(tc, &waveform_opt); + tc_init_waveform( tc, &waveform_opt ); /* Set the compare triggers. - Remember TC counter is 16-bits, so counting second is not possible! - That's why we configure it to count ms. */ - tc_write_rc( tc, configTICK_TC_CHANNEL, ( configPBA_CLOCK_HZ / 4) / configTICK_RATE_HZ ); + * Remember TC counter is 16-bits, so counting second is not possible! + * That's why we configure it to count ms. */ + tc_write_rc( tc, configTICK_TC_CHANNEL, ( configPBA_CLOCK_HZ / 4 ) / configTICK_RATE_HZ ); tc_configure_interrupts( tc, configTICK_TC_CHANNEL, &tc_interrupt ); /* Start the timer/counter. */ - tc_start(tc, configTICK_TC_CHANNEL); + tc_start( tc, configTICK_TC_CHANNEL ); } - #else + #else /* if ( configTICK_USE_TC == 1 ) */ { - INTC_register_interrupt(&vTick, AVR32_CORE_COMPARE_IRQ, INT0); + INTC_register_interrupt( &vTick, AVR32_CORE_COMPARE_IRQ, INT0 ); prvScheduleFirstTick(); } - #endif + #endif /* if ( configTICK_USE_TC == 1 ) */ } diff --git a/Source/portable/GCC/AVR32_UC3/portmacro.h b/Source/portable/GCC/AVR32_UC3/portmacro.h index 9f07d6291..f63d44d84 100644 --- a/Source/portable/GCC/AVR32_UC3/portmacro.h +++ b/Source/portable/GCC/AVR32_UC3/portmacro.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT AND BSD-3-Clause @@ -27,6 +27,7 @@ */ /*This file has been prepared for Doxygen automatic documentation generation.*/ + /*! \file ********************************************************************* * * \brief FreeRTOS port source for AVR32 UC3. @@ -93,30 +94,30 @@ /* Type definitions. */ -#define portCHAR char -#define portFLOAT float -#define portDOUBLE double -#define portLONG long -#define portSHORT short -#define portSTACK_TYPE uint32_t -#define portBASE_TYPE long - -typedef portSTACK_TYPE StackType_t; -typedef long BaseType_t; -typedef unsigned long UBaseType_t; - -#define TASK_DELAY_MS(x) ( (x) /portTICK_PERIOD_MS ) -#define TASK_DELAY_S(x) ( (x)*1000 /portTICK_PERIOD_MS ) -#define TASK_DELAY_MIN(x) ( (x)*60*1000/portTICK_PERIOD_MS ) - -#define configTICK_TC_IRQ ATPASTE2(AVR32_TC_IRQ, configTICK_TC_CHANNEL) - -#if( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS ) - typedef uint16_t TickType_t; - #define portMAX_DELAY ( TickType_t ) 0xffff +#define portCHAR char +#define portFLOAT float +#define portDOUBLE double +#define portLONG long +#define portSHORT short +#define portSTACK_TYPE uint32_t +#define portBASE_TYPE long + +typedef portSTACK_TYPE StackType_t; +typedef long BaseType_t; +typedef unsigned long UBaseType_t; + +#define TASK_DELAY_MS( x ) ( ( x ) / portTICK_PERIOD_MS ) +#define TASK_DELAY_S( x ) ( ( x ) * 1000 / portTICK_PERIOD_MS ) +#define TASK_DELAY_MIN( x ) ( ( x ) * 60 * 1000 / portTICK_PERIOD_MS ) + +#define configTICK_TC_IRQ ATPASTE2( AVR32_TC_IRQ, configTICK_TC_CHANNEL ) + +#if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS ) + typedef uint16_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffff #elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS ) - typedef uint32_t TickType_t; - #define portMAX_DELAY ( TickType_t ) ( 0xFFFFFFFFUL ) + typedef uint32_t TickType_t; + #define portMAX_DELAY ( TickType_t ) ( 0xFFFFFFFFUL ) #else #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width. #endif @@ -124,23 +125,23 @@ typedef unsigned long UBaseType_t; /* Architecture specifics. */ #define portSTACK_GROWTH ( -1 ) -#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) +#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) #define portBYTE_ALIGNMENT 4 -#define portNOP() {__asm__ __volatile__ ("nop");} +#define portNOP() { __asm__ __volatile__ ( "nop" ); } /*-----------------------------------------------------------*/ /*-----------------------------------------------------------*/ /* INTC-specific. */ -#define DISABLE_ALL_EXCEPTIONS() Disable_global_exception() -#define ENABLE_ALL_EXCEPTIONS() Enable_global_exception() +#define DISABLE_ALL_EXCEPTIONS() Disable_global_exception() +#define ENABLE_ALL_EXCEPTIONS() Enable_global_exception() -#define DISABLE_ALL_INTERRUPTS() Disable_global_interrupt() -#define ENABLE_ALL_INTERRUPTS() Enable_global_interrupt() +#define DISABLE_ALL_INTERRUPTS() Disable_global_interrupt() +#define ENABLE_ALL_INTERRUPTS() Enable_global_interrupt() -#define DISABLE_INT_LEVEL(int_lev) Disable_interrupt_level(int_lev) -#define ENABLE_INT_LEVEL(int_lev) Enable_interrupt_level(int_lev) +#define DISABLE_INT_LEVEL( int_lev ) Disable_interrupt_level( int_lev ) +#define ENABLE_INT_LEVEL( int_lev ) Enable_interrupt_level( int_lev ) /* @@ -157,31 +158,32 @@ typedef unsigned long UBaseType_t; * which is interrupt-unsafe with the current __malloc_lock and __malloc_unlock. */ #if configDBG -#define portDBG_TRACE(...) \ -{\ - fputs(__FILE__ ":" ASTRINGZ(__LINE__) ": ", stdout);\ - printf(__VA_ARGS__);\ - fputs("\r\n", stdout);\ -} + #define portDBG_TRACE( ... ) \ + { \ + fputs( __FILE__ ":" ASTRINGZ( __LINE__ ) ": ", stdout ); \ + printf( __VA_ARGS__ ); \ + fputs( "\r\n", stdout ); \ + } #else -#define portDBG_TRACE(...) + #define portDBG_TRACE( ... ) #endif /* Critical section management. */ -#define portDISABLE_INTERRUPTS() DISABLE_ALL_INTERRUPTS() -#define portENABLE_INTERRUPTS() ENABLE_ALL_INTERRUPTS() +#define portDISABLE_INTERRUPTS() DISABLE_ALL_INTERRUPTS() +#define portENABLE_INTERRUPTS() ENABLE_ALL_INTERRUPTS() extern void vPortEnterCritical( void ); extern void vPortExitCritical( void ); -#define portENTER_CRITICAL() vPortEnterCritical(); -#define portEXIT_CRITICAL() vPortExitCritical(); +#define portENTER_CRITICAL() vPortEnterCritical(); +#define portEXIT_CRITICAL() vPortExitCritical(); /* Added as there is no such function in FreeRTOS. */ -extern void *pvPortRealloc( void *pv, size_t xSize ); +extern void * pvPortRealloc( void * pv, + size_t xSize ); /*-----------------------------------------------------------*/ @@ -190,44 +192,44 @@ extern void *pvPortRealloc( void *pv, size_t xSize ); /* * Restore Context for cases other than INTi. */ -#define portRESTORE_CONTEXT() \ -{ \ - extern volatile uint32_t ulCriticalNesting; \ - extern volatile void *volatile pxCurrentTCB; \ - \ - __asm__ __volatile__ ( \ - /* Set SP to point to new stack */ \ - "mov r8, LO(%[pxCurrentTCB]) \n\t"\ - "orh r8, HI(%[pxCurrentTCB]) \n\t"\ - "ld.w r0, r8[0] \n\t"\ - "ld.w sp, r0[0] \n\t"\ - \ - /* Restore ulCriticalNesting variable */ \ - "ld.w r0, sp++ \n\t"\ - "mov r8, LO(%[ulCriticalNesting]) \n\t"\ - "orh r8, HI(%[ulCriticalNesting]) \n\t"\ - "st.w r8[0], r0 \n\t"\ - \ - /* Restore R0..R7 */ \ - "ldm sp++, r0-r7 \n\t"\ - /* R0-R7 should not be used below this line */ \ - /* Skip PC and SR (will do it at the end) */ \ - "sub sp, -2*4 \n\t"\ - /* Restore R8..R12 and LR */ \ - "ldm sp++, r8-r12, lr \n\t"\ - /* Restore SR */ \ - "ld.w r0, sp[-8*4]\n\t" /* R0 is modified, is restored later. */ \ - "mtsr %[SR], r0 \n\t"\ - /* Restore r0 */ \ - "ld.w r0, sp[-9*4] \n\t"\ - /* Restore PC */ \ - "ld.w pc, sp[-7*4]" /* Get PC from stack - PC is the 7th register saved */ \ - : \ - : [ulCriticalNesting] "i" (&ulCriticalNesting), \ - [pxCurrentTCB] "i" (&pxCurrentTCB), \ - [SR] "i" (AVR32_SR) \ - ); \ -} +#define portRESTORE_CONTEXT() \ + { \ + extern volatile uint32_t ulCriticalNesting; \ + extern volatile void * volatile pxCurrentTCB; \ + \ + __asm__ __volatile__ ( \ + /* Set SP to point to new stack */ \ + "mov r8, LO(%[pxCurrentTCB]) \n\t" \ + "orh r8, HI(%[pxCurrentTCB]) \n\t" \ + "ld.w r0, r8[0] \n\t" \ + "ld.w sp, r0[0] \n\t" \ + \ + /* Restore ulCriticalNesting variable */ \ + "ld.w r0, sp++ \n\t" \ + "mov r8, LO(%[ulCriticalNesting]) \n\t" \ + "orh r8, HI(%[ulCriticalNesting]) \n\t" \ + "st.w r8[0], r0 \n\t" \ + \ + /* Restore R0..R7 */ \ + "ldm sp++, r0-r7 \n\t" \ + /* R0-R7 should not be used below this line */ \ + /* Skip PC and SR (will do it at the end) */ \ + "sub sp, -2*4 \n\t" \ + /* Restore R8..R12 and LR */ \ + "ldm sp++, r8-r12, lr \n\t" \ + /* Restore SR */ \ + "ld.w r0, sp[-8*4]\n\t" /* R0 is modified, is restored later. */ \ + "mtsr %[SR], r0 \n\t" \ + /* Restore r0 */ \ + "ld.w r0, sp[-9*4] \n\t" \ + /* Restore PC */ \ + "ld.w pc, sp[-7*4]" /* Get PC from stack - PC is the 7th register saved */ \ + : \ + :[ ulCriticalNesting ] "i" ( &ulCriticalNesting ), \ + [ pxCurrentTCB ] "i" ( &pxCurrentTCB ), \ + [ SR ] "i" ( AVR32_SR ) \ + ); \ + } /* @@ -238,25 +240,25 @@ extern void *pvPortRealloc( void *pv, size_t xSize ); * are not the same between INT0..3 exceptions and the scall exception. */ -// Task context stack layout: - // R8 (*) - // R9 (*) - // R10 (*) - // R11 (*) - // R12 (*) - // R14/LR (*) - // R15/PC (*) - // SR (*) - // R0 - // R1 - // R2 - // R3 - // R4 - // R5 - // R6 - // R7 - // ulCriticalNesting -// (*) automatically done for INT0..INT3, but not for SCALL +/* Task context stack layout: */ +/* R8 (*) */ +/* R9 (*) */ +/* R10 (*) */ +/* R11 (*) */ +/* R12 (*) */ +/* R14/LR (*) */ +/* R15/PC (*) */ +/* SR (*) */ +/* R0 */ +/* R1 */ +/* R2 */ +/* R3 */ +/* R4 */ +/* R5 */ +/* R6 */ +/* R7 */ +/* ulCriticalNesting */ +/* (*) automatically done for INT0..INT3, but not for SCALL */ /* * The ISR used for the scheduler tick depends on whether the cooperative or @@ -267,145 +269,145 @@ extern void *pvPortRealloc( void *pv, size_t xSize ); /* * portSAVE_CONTEXT_OS_INT() for OS Tick exception. */ -#define portSAVE_CONTEXT_OS_INT() \ -{ \ - /* Save R0..R7 */ \ - __asm__ __volatile__ ("stm --sp, r0-r7"); \ - \ - /* With the cooperative scheduler, as there is no context switch by interrupt, */ \ - /* there is also no context save. */ \ -} + #define portSAVE_CONTEXT_OS_INT() \ + { \ + /* Save R0..R7 */ \ + __asm__ __volatile__ ( "stm --sp, r0-r7" ); \ + \ + /* With the cooperative scheduler, as there is no context switch by interrupt, */ \ + /* there is also no context save. */ \ + } /* * portRESTORE_CONTEXT_OS_INT() for Tick exception. */ -#define portRESTORE_CONTEXT_OS_INT() \ -{ \ - __asm__ __volatile__ ( \ - /* Restore R0..R7 */ \ - "ldm sp++, r0-r7\n\t" \ - \ - /* With the cooperative scheduler, as there is no context switch by interrupt, */ \ - /* there is also no context restore. */ \ - "rete" \ - ); \ -} + #define portRESTORE_CONTEXT_OS_INT() \ + { \ + __asm__ __volatile__ ( \ + /* Restore R0..R7 */ \ + "ldm sp++, r0-r7\n\t" \ + \ + /* With the cooperative scheduler, as there is no context switch by interrupt, */ \ + /* there is also no context restore. */ \ + "rete" \ + ); \ + } -#else +#else /* if configUSE_PREEMPTION == 0 */ /* * portSAVE_CONTEXT_OS_INT() for OS Tick exception. */ -#define portSAVE_CONTEXT_OS_INT() \ -{ \ - extern volatile uint32_t ulCriticalNesting; \ - extern volatile void *volatile pxCurrentTCB; \ - \ - /* When we come here */ \ - /* Registers R8..R12, LR, PC and SR had already been pushed to system stack */ \ - \ - __asm__ __volatile__ ( \ - /* Save R0..R7 */ \ - "stm --sp, r0-r7 \n\t"\ - \ - /* Save ulCriticalNesting variable - R0 is overwritten */ \ - "mov r8, LO(%[ulCriticalNesting])\n\t" \ - "orh r8, HI(%[ulCriticalNesting])\n\t" \ - "ld.w r0, r8[0] \n\t"\ - "st.w --sp, r0 \n\t"\ - \ - /* Check if INT0 or higher were being handled (case where the OS tick interrupted another */ \ - /* interrupt handler (which was of a higher priority level but decided to lower its priority */ \ - /* level and allow other lower interrupt level to occur). */ \ - /* In this case we don't want to do a task switch because we don't know what the stack */ \ - /* currently looks like (we don't know what the interrupted interrupt handler was doing). */ \ - /* Saving SP in pxCurrentTCB and then later restoring it (thinking restoring the task) */ \ - /* will just be restoring the interrupt handler, no way!!! */ \ - /* So, since we won't do a vTaskSwitchContext(), it's of no use to save SP. */ \ - "ld.w r0, sp[9*4]\n\t" /* Read SR in stack */ \ - "bfextu r0, r0, 22, 3\n\t" /* Extract the mode bits to R0. */ \ - "cp.w r0, 1\n\t" /* Compare the mode bits with supervisor mode(b'001) */ \ - "brhi LABEL_INT_SKIP_SAVE_CONTEXT_%[LINE] \n\t"\ - \ - /* Store SP in the first member of the structure pointed to by pxCurrentTCB */ \ - /* NOTE: we don't enter a critical section here because all interrupt handlers */ \ - /* MUST perform a SAVE_CONTEXT/RESTORE_CONTEXT in the same way as */ \ - /* portSAVE_CONTEXT_OS_INT/port_RESTORE_CONTEXT_OS_INT if they call OS functions. */ \ - /* => all interrupt handlers must use portENTER_SWITCHING_ISR/portEXIT_SWITCHING_ISR. */ \ - "mov r8, LO(%[pxCurrentTCB])\n\t" \ - "orh r8, HI(%[pxCurrentTCB])\n\t" \ - "ld.w r0, r8[0]\n\t" \ - "st.w r0[0], sp\n" \ - \ - "LABEL_INT_SKIP_SAVE_CONTEXT_%[LINE]:" \ - : \ - : [ulCriticalNesting] "i" (&ulCriticalNesting), \ - [pxCurrentTCB] "i" (&pxCurrentTCB), \ - [LINE] "i" (__LINE__) \ - ); \ -} + #define portSAVE_CONTEXT_OS_INT() \ + { \ + extern volatile uint32_t ulCriticalNesting; \ + extern volatile void * volatile pxCurrentTCB; \ + \ + /* When we come here */ \ + /* Registers R8..R12, LR, PC and SR had already been pushed to system stack */ \ + \ + __asm__ __volatile__ ( \ + /* Save R0..R7 */ \ + "stm --sp, r0-r7 \n\t" \ + \ + /* Save ulCriticalNesting variable - R0 is overwritten */ \ + "mov r8, LO(%[ulCriticalNesting])\n\t" \ + "orh r8, HI(%[ulCriticalNesting])\n\t" \ + "ld.w r0, r8[0] \n\t" \ + "st.w --sp, r0 \n\t" \ + \ + /* Check if INT0 or higher were being handled (case where the OS tick interrupted another */ \ + /* interrupt handler (which was of a higher priority level but decided to lower its priority */ \ + /* level and allow other lower interrupt level to occur). */ \ + /* In this case we don't want to do a task switch because we don't know what the stack */ \ + /* currently looks like (we don't know what the interrupted interrupt handler was doing). */ \ + /* Saving SP in pxCurrentTCB and then later restoring it (thinking restoring the task) */ \ + /* will just be restoring the interrupt handler, no way!!! */ \ + /* So, since we won't do a vTaskSwitchContext(), it's of no use to save SP. */ \ + "ld.w r0, sp[9*4]\n\t" /* Read SR in stack */ \ + "bfextu r0, r0, 22, 3\n\t" /* Extract the mode bits to R0. */ \ + "cp.w r0, 1\n\t" /* Compare the mode bits with supervisor mode(b'001) */ \ + "brhi LABEL_INT_SKIP_SAVE_CONTEXT_%[LINE] \n\t" \ + \ + /* Store SP in the first member of the structure pointed to by pxCurrentTCB */ \ + /* NOTE: we don't enter a critical section here because all interrupt handlers */ \ + /* MUST perform a SAVE_CONTEXT/RESTORE_CONTEXT in the same way as */ \ + /* portSAVE_CONTEXT_OS_INT/port_RESTORE_CONTEXT_OS_INT if they call OS functions. */ \ + /* => all interrupt handlers must use portENTER_SWITCHING_ISR/portEXIT_SWITCHING_ISR. */ \ + "mov r8, LO(%[pxCurrentTCB])\n\t" \ + "orh r8, HI(%[pxCurrentTCB])\n\t" \ + "ld.w r0, r8[0]\n\t" \ + "st.w r0[0], sp\n" \ + \ + "LABEL_INT_SKIP_SAVE_CONTEXT_%[LINE]:" \ + : \ + :[ ulCriticalNesting ] "i" ( &ulCriticalNesting ), \ + [ pxCurrentTCB ] "i" ( &pxCurrentTCB ), \ + [ LINE ] "i" ( __LINE__ ) \ + ); \ + } /* * portRESTORE_CONTEXT_OS_INT() for Tick exception. */ -#define portRESTORE_CONTEXT_OS_INT() \ -{ \ - extern volatile uint32_t ulCriticalNesting; \ - extern volatile void *volatile pxCurrentTCB; \ - \ - /* Check if INT0 or higher were being handled (case where the OS tick interrupted another */ \ - /* interrupt handler (which was of a higher priority level but decided to lower its priority */ \ - /* level and allow other lower interrupt level to occur). */ \ - /* In this case we don't want to do a task switch because we don't know what the stack */ \ - /* currently looks like (we don't know what the interrupted interrupt handler was doing). */ \ - /* Saving SP in pxCurrentTCB and then later restoring it (thinking restoring the task) */ \ - /* will just be restoring the interrupt handler, no way!!! */ \ - __asm__ __volatile__ ( \ - "ld.w r0, sp[9*4]\n\t" /* Read SR in stack */ \ - "bfextu r0, r0, 22, 3\n\t" /* Extract the mode bits to R0. */ \ - "cp.w r0, 1\n\t" /* Compare the mode bits with supervisor mode(b'001) */ \ - "brhi LABEL_INT_SKIP_RESTORE_CONTEXT_%[LINE]" \ - : \ - : [LINE] "i" (__LINE__) \ - ); \ - \ - /* Else */ \ - /* because it is here safe, always call vTaskSwitchContext() since an OS tick occurred. */ \ - /* A critical section has to be used here because vTaskSwitchContext handles FreeRTOS linked lists. */\ - portENTER_CRITICAL(); \ - vTaskSwitchContext(); \ - portEXIT_CRITICAL(); \ - \ - /* Restore all registers */ \ - \ - __asm__ __volatile__ ( \ - /* Set SP to point to new stack */ \ - "mov r8, LO(%[pxCurrentTCB]) \n\t"\ - "orh r8, HI(%[pxCurrentTCB]) \n\t"\ - "ld.w r0, r8[0] \n\t"\ - "ld.w sp, r0[0] \n"\ - \ - "LABEL_INT_SKIP_RESTORE_CONTEXT_%[LINE]: \n\t"\ - \ - /* Restore ulCriticalNesting variable */ \ - "ld.w r0, sp++ \n\t" \ - "mov r8, LO(%[ulCriticalNesting]) \n\t"\ - "orh r8, HI(%[ulCriticalNesting]) \n\t"\ - "st.w r8[0], r0 \n\t"\ - \ - /* Restore R0..R7 */ \ - "ldm sp++, r0-r7 \n\t"\ - \ - /* Now, the stack should be R8..R12, LR, PC and SR */ \ - "rete" \ - : \ - : [ulCriticalNesting] "i" (&ulCriticalNesting), \ - [pxCurrentTCB] "i" (&pxCurrentTCB), \ - [LINE] "i" (__LINE__) \ - ); \ -} + #define portRESTORE_CONTEXT_OS_INT() \ + { \ + extern volatile uint32_t ulCriticalNesting; \ + extern volatile void * volatile pxCurrentTCB; \ + \ + /* Check if INT0 or higher were being handled (case where the OS tick interrupted another */ \ + /* interrupt handler (which was of a higher priority level but decided to lower its priority */ \ + /* level and allow other lower interrupt level to occur). */ \ + /* In this case we don't want to do a task switch because we don't know what the stack */ \ + /* currently looks like (we don't know what the interrupted interrupt handler was doing). */ \ + /* Saving SP in pxCurrentTCB and then later restoring it (thinking restoring the task) */ \ + /* will just be restoring the interrupt handler, no way!!! */ \ + __asm__ __volatile__ ( \ + "ld.w r0, sp[9*4]\n\t" /* Read SR in stack */ \ + "bfextu r0, r0, 22, 3\n\t" /* Extract the mode bits to R0. */ \ + "cp.w r0, 1\n\t" /* Compare the mode bits with supervisor mode(b'001) */ \ + "brhi LABEL_INT_SKIP_RESTORE_CONTEXT_%[LINE]" \ + : \ + :[ LINE ] "i" ( __LINE__ ) \ + ); \ + \ + /* Else */ \ + /* because it is here safe, always call vTaskSwitchContext() since an OS tick occurred. */ \ + /* A critical section has to be used here because vTaskSwitchContext handles FreeRTOS linked lists. */ \ + portENTER_CRITICAL(); \ + vTaskSwitchContext(); \ + portEXIT_CRITICAL(); \ + \ + /* Restore all registers */ \ + \ + __asm__ __volatile__ ( \ + /* Set SP to point to new stack */ \ + "mov r8, LO(%[pxCurrentTCB]) \n\t" \ + "orh r8, HI(%[pxCurrentTCB]) \n\t" \ + "ld.w r0, r8[0] \n\t" \ + "ld.w sp, r0[0] \n" \ + \ + "LABEL_INT_SKIP_RESTORE_CONTEXT_%[LINE]: \n\t" \ + \ + /* Restore ulCriticalNesting variable */ \ + "ld.w r0, sp++ \n\t" \ + "mov r8, LO(%[ulCriticalNesting]) \n\t" \ + "orh r8, HI(%[ulCriticalNesting]) \n\t" \ + "st.w r8[0], r0 \n\t" \ + \ + /* Restore R0..R7 */ \ + "ldm sp++, r0-r7 \n\t" \ + \ + /* Now, the stack should be R8..R12, LR, PC and SR */ \ + "rete" \ + : \ + :[ ulCriticalNesting ] "i" ( &ulCriticalNesting ), \ + [ pxCurrentTCB ] "i" ( &pxCurrentTCB ), \ + [ LINE ] "i" ( __LINE__ ) \ + ); \ + } -#endif +#endif /* if configUSE_PREEMPTION == 0 */ /* @@ -414,123 +416,123 @@ extern void *pvPortRealloc( void *pv, size_t xSize ); * NOTE: taskYIELD()(== SCALL) MUST NOT be called in a mode > supervisor mode. * */ -#define portSAVE_CONTEXT_SCALL() \ -{ \ - extern volatile uint32_t ulCriticalNesting; \ - extern volatile void *volatile pxCurrentTCB; \ - \ - /* Warning: the stack layout after SCALL doesn't match the one after an interrupt. */ \ - /* If SR[M2:M0] == 001 */ \ - /* PC and SR are on the stack. */ \ - /* Else (other modes) */ \ - /* Nothing on the stack. */ \ - \ - /* WARNING NOTE: the else case cannot happen as it is strictly forbidden to call */ \ - /* vTaskDelay() and vTaskDelayUntil() OS functions (that result in a taskYield()) */ \ - /* in an interrupt|exception handler. */ \ - \ - __asm__ __volatile__ ( \ - /* in order to save R0-R7 */ \ - "sub sp, 6*4 \n\t"\ - /* Save R0..R7 */ \ - "stm --sp, r0-r7 \n\t"\ - \ - /* in order to save R8-R12 and LR */ \ - /* do not use SP if interrupts occurs, SP must be left at bottom of stack */ \ - "sub r7, sp,-16*4 \n\t"\ - /* Copy PC and SR in other places in the stack. */ \ - "ld.w r0, r7[-2*4] \n\t" /* Read SR */\ - "st.w r7[-8*4], r0 \n\t" /* Copy SR */\ - "ld.w r0, r7[-1*4] \n\t" /* Read PC */\ - "st.w r7[-7*4], r0 \n\t" /* Copy PC */\ - \ - /* Save R8..R12 and LR on the stack. */ \ - "stm --r7, r8-r12, lr \n\t"\ - \ - /* Arriving here we have the following stack organizations: */ \ - /* R8..R12, LR, PC, SR, R0..R7. */ \ - \ - /* Now we can finalize the save. */ \ - \ - /* Save ulCriticalNesting variable - R0 is overwritten */ \ - "mov r8, LO(%[ulCriticalNesting]) \n\t"\ - "orh r8, HI(%[ulCriticalNesting]) \n\t"\ - "ld.w r0, r8[0] \n\t"\ - "st.w --sp, r0" \ - : \ - : [ulCriticalNesting] "i" (&ulCriticalNesting) \ - ); \ - \ - /* Disable the its which may cause a context switch (i.e. cause a change of */ \ - /* pxCurrentTCB). */ \ - /* Basically, all accesses to the pxCurrentTCB structure should be put in a */ \ - /* critical section because it is a global structure. */ \ - portENTER_CRITICAL(); \ - \ - /* Store SP in the first member of the structure pointed to by pxCurrentTCB */ \ - __asm__ __volatile__ ( \ - "mov r8, LO(%[pxCurrentTCB]) \n\t"\ - "orh r8, HI(%[pxCurrentTCB]) \n\t"\ - "ld.w r0, r8[0] \n\t"\ - "st.w r0[0], sp" \ - : \ - : [pxCurrentTCB] "i" (&pxCurrentTCB) \ - ); \ -} +#define portSAVE_CONTEXT_SCALL() \ + { \ + extern volatile uint32_t ulCriticalNesting; \ + extern volatile void * volatile pxCurrentTCB; \ + \ + /* Warning: the stack layout after SCALL doesn't match the one after an interrupt. */ \ + /* If SR[M2:M0] == 001 */ \ + /* PC and SR are on the stack. */ \ + /* Else (other modes) */ \ + /* Nothing on the stack. */ \ + \ + /* WARNING NOTE: the else case cannot happen as it is strictly forbidden to call */ \ + /* vTaskDelay() and vTaskDelayUntil() OS functions (that result in a taskYield()) */ \ + /* in an interrupt|exception handler. */ \ + \ + __asm__ __volatile__ ( \ + /* in order to save R0-R7 */ \ + "sub sp, 6*4 \n\t" \ + /* Save R0..R7 */ \ + "stm --sp, r0-r7 \n\t" \ + \ + /* in order to save R8-R12 and LR */ \ + /* do not use SP if interrupts occurs, SP must be left at bottom of stack */ \ + "sub r7, sp,-16*4 \n\t" \ + /* Copy PC and SR in other places in the stack. */ \ + "ld.w r0, r7[-2*4] \n\t" /* Read SR */ \ + "st.w r7[-8*4], r0 \n\t" /* Copy SR */ \ + "ld.w r0, r7[-1*4] \n\t" /* Read PC */ \ + "st.w r7[-7*4], r0 \n\t" /* Copy PC */ \ + \ + /* Save R8..R12 and LR on the stack. */ \ + "stm --r7, r8-r12, lr \n\t" \ + \ + /* Arriving here we have the following stack organizations: */ \ + /* R8..R12, LR, PC, SR, R0..R7. */ \ + \ + /* Now we can finalize the save. */ \ + \ + /* Save ulCriticalNesting variable - R0 is overwritten */ \ + "mov r8, LO(%[ulCriticalNesting]) \n\t" \ + "orh r8, HI(%[ulCriticalNesting]) \n\t" \ + "ld.w r0, r8[0] \n\t" \ + "st.w --sp, r0" \ + : \ + :[ ulCriticalNesting ] "i" ( &ulCriticalNesting ) \ + ); \ + \ + /* Disable the its which may cause a context switch (i.e. cause a change of */ \ + /* pxCurrentTCB). */ \ + /* Basically, all accesses to the pxCurrentTCB structure should be put in a */ \ + /* critical section because it is a global structure. */ \ + portENTER_CRITICAL(); \ + \ + /* Store SP in the first member of the structure pointed to by pxCurrentTCB */ \ + __asm__ __volatile__ ( \ + "mov r8, LO(%[pxCurrentTCB]) \n\t" \ + "orh r8, HI(%[pxCurrentTCB]) \n\t" \ + "ld.w r0, r8[0] \n\t" \ + "st.w r0[0], sp" \ + : \ + :[ pxCurrentTCB ] "i" ( &pxCurrentTCB ) \ + ); \ + } /* * portRESTORE_CONTEXT() for SupervisorCALL exception. */ -#define portRESTORE_CONTEXT_SCALL() \ -{ \ - extern volatile uint32_t ulCriticalNesting; \ - extern volatile void *volatile pxCurrentTCB; \ - \ - /* Restore all registers */ \ - \ - /* Set SP to point to new stack */ \ - __asm__ __volatile__ ( \ - "mov r8, LO(%[pxCurrentTCB]) \n\t"\ - "orh r8, HI(%[pxCurrentTCB]) \n\t"\ - "ld.w r0, r8[0] \n\t"\ - "ld.w sp, r0[0]" \ - : \ - : [pxCurrentTCB] "i" (&pxCurrentTCB) \ - ); \ - \ - /* Leave pxCurrentTCB variable access critical section */ \ - portEXIT_CRITICAL(); \ - \ - __asm__ __volatile__ ( \ - /* Restore ulCriticalNesting variable */ \ - "ld.w r0, sp++ \n\t"\ - "mov r8, LO(%[ulCriticalNesting]) \n\t"\ - "orh r8, HI(%[ulCriticalNesting]) \n\t"\ - "st.w r8[0], r0 \n\t"\ - \ - /* skip PC and SR */ \ - /* do not use SP if interrupts occurs, SP must be left at bottom of stack */ \ - "sub r7, sp, -10*4 \n\t"\ - /* Restore r8-r12 and LR */ \ - "ldm r7++, r8-r12, lr \n\t"\ - \ - /* RETS will take care of the extra PC and SR restore. */ \ - /* So, we have to prepare the stack for this. */ \ - "ld.w r0, r7[-8*4] \n\t" /* Read SR */\ - "st.w r7[-2*4], r0 \n\t" /* Copy SR */\ - "ld.w r0, r7[-7*4] \n\t" /* Read PC */\ - "st.w r7[-1*4], r0 \n\t" /* Copy PC */\ - \ - /* Restore R0..R7 */ \ - "ldm sp++, r0-r7 \n\t"\ - \ - "sub sp, -6*4 \n\t"\ - \ - "rets" \ - : \ - : [ulCriticalNesting] "i" (&ulCriticalNesting) \ - ); \ -} +#define portRESTORE_CONTEXT_SCALL() \ + { \ + extern volatile uint32_t ulCriticalNesting; \ + extern volatile void * volatile pxCurrentTCB; \ + \ + /* Restore all registers */ \ + \ + /* Set SP to point to new stack */ \ + __asm__ __volatile__ ( \ + "mov r8, LO(%[pxCurrentTCB]) \n\t" \ + "orh r8, HI(%[pxCurrentTCB]) \n\t" \ + "ld.w r0, r8[0] \n\t" \ + "ld.w sp, r0[0]" \ + : \ + :[ pxCurrentTCB ] "i" ( &pxCurrentTCB ) \ + ); \ + \ + /* Leave pxCurrentTCB variable access critical section */ \ + portEXIT_CRITICAL(); \ + \ + __asm__ __volatile__ ( \ + /* Restore ulCriticalNesting variable */ \ + "ld.w r0, sp++ \n\t" \ + "mov r8, LO(%[ulCriticalNesting]) \n\t" \ + "orh r8, HI(%[ulCriticalNesting]) \n\t" \ + "st.w r8[0], r0 \n\t" \ + \ + /* skip PC and SR */ \ + /* do not use SP if interrupts occurs, SP must be left at bottom of stack */ \ + "sub r7, sp, -10*4 \n\t" \ + /* Restore r8-r12 and LR */ \ + "ldm r7++, r8-r12, lr \n\t" \ + \ + /* RETS will take care of the extra PC and SR restore. */ \ + /* So, we have to prepare the stack for this. */ \ + "ld.w r0, r7[-8*4] \n\t" /* Read SR */ \ + "st.w r7[-2*4], r0 \n\t" /* Copy SR */ \ + "ld.w r0, r7[-7*4] \n\t" /* Read PC */ \ + "st.w r7[-1*4], r0 \n\t" /* Copy PC */ \ + \ + /* Restore R0..R7 */ \ + "ldm sp++, r0-r7 \n\t" \ + \ + "sub sp, -6*4 \n\t" \ + \ + "rets" \ + : \ + :[ ulCriticalNesting ] "i" ( &ulCriticalNesting ) \ + ); \ + } /* @@ -543,155 +545,155 @@ extern void *pvPortRealloc( void *pv, size_t xSize ); * ISR entry and exit macros. These are only required if a task switch * is required from the ISR. */ -#define portENTER_SWITCHING_ISR() \ -{ \ - /* Save R0..R7 */ \ - __asm__ __volatile__ ("stm --sp, r0-r7"); \ - \ - /* With the cooperative scheduler, as there is no context switch by interrupt, */ \ - /* there is also no context save. */ \ -} + #define portENTER_SWITCHING_ISR() \ + { \ + /* Save R0..R7 */ \ + __asm__ __volatile__ ( "stm --sp, r0-r7" ); \ + \ + /* With the cooperative scheduler, as there is no context switch by interrupt, */ \ + /* there is also no context save. */ \ + } /* * Input parameter: in R12, boolean. Perform a vTaskSwitchContext() if 1 */ -#define portEXIT_SWITCHING_ISR() \ -{ \ - __asm__ __volatile__ ( \ - /* Restore R0..R7 */ \ - "ldm sp++, r0-r7 \n\t"\ - \ - /* With the cooperative scheduler, as there is no context switch by interrupt, */ \ - /* there is also no context restore. */ \ - "rete" \ - ); \ -} + #define portEXIT_SWITCHING_ISR() \ + { \ + __asm__ __volatile__ ( \ + /* Restore R0..R7 */ \ + "ldm sp++, r0-r7 \n\t" \ + \ + /* With the cooperative scheduler, as there is no context switch by interrupt, */ \ + /* there is also no context restore. */ \ + "rete" \ + ); \ + } -#else +#else /* if configUSE_PREEMPTION == 0 */ /* * ISR entry and exit macros. These are only required if a task switch * is required from the ISR. */ -#define portENTER_SWITCHING_ISR() \ -{ \ - extern volatile uint32_t ulCriticalNesting; \ - extern volatile void *volatile pxCurrentTCB; \ - \ - /* When we come here */ \ - /* Registers R8..R12, LR, PC and SR had already been pushed to system stack */ \ - \ - __asm__ __volatile__ ( \ - /* Save R0..R7 */ \ - "stm --sp, r0-r7 \n\t"\ - \ - /* Save ulCriticalNesting variable - R0 is overwritten */ \ - "mov r8, LO(%[ulCriticalNesting]) \n\t"\ - "orh r8, HI(%[ulCriticalNesting]) \n\t"\ - "ld.w r0, r8[0] \n\t"\ - "st.w --sp, r0 \n\t"\ - \ - /* Check if INT0 or higher were being handled (case where the OS tick interrupted another */ \ - /* interrupt handler (which was of a higher priority level but decided to lower its priority */ \ - /* level and allow other lower interrupt level to occur). */ \ - /* In this case we don't want to do a task switch because we don't know what the stack */ \ - /* currently looks like (we don't know what the interrupted interrupt handler was doing). */ \ - /* Saving SP in pxCurrentTCB and then later restoring it (thinking restoring the task) */ \ - /* will just be restoring the interrupt handler, no way!!! */ \ - /* So, since we won't do a vTaskSwitchContext(), it's of no use to save SP. */ \ - "ld.w r0, sp[9*4] \n\t" /* Read SR in stack */\ - "bfextu r0, r0, 22, 3 \n\t" /* Extract the mode bits to R0. */\ - "cp.w r0, 1 \n\t" /* Compare the mode bits with supervisor mode(b'001) */\ - "brhi LABEL_ISR_SKIP_SAVE_CONTEXT_%[LINE] \n\t"\ - \ - /* Store SP in the first member of the structure pointed to by pxCurrentTCB */ \ - "mov r8, LO(%[pxCurrentTCB]) \n\t"\ - "orh r8, HI(%[pxCurrentTCB]) \n\t"\ - "ld.w r0, r8[0] \n\t"\ - "st.w r0[0], sp \n"\ - \ - "LABEL_ISR_SKIP_SAVE_CONTEXT_%[LINE]:" \ - : \ - : [ulCriticalNesting] "i" (&ulCriticalNesting), \ - [pxCurrentTCB] "i" (&pxCurrentTCB), \ - [LINE] "i" (__LINE__) \ - ); \ -} + #define portENTER_SWITCHING_ISR() \ + { \ + extern volatile uint32_t ulCriticalNesting; \ + extern volatile void * volatile pxCurrentTCB; \ + \ + /* When we come here */ \ + /* Registers R8..R12, LR, PC and SR had already been pushed to system stack */ \ + \ + __asm__ __volatile__ ( \ + /* Save R0..R7 */ \ + "stm --sp, r0-r7 \n\t" \ + \ + /* Save ulCriticalNesting variable - R0 is overwritten */ \ + "mov r8, LO(%[ulCriticalNesting]) \n\t" \ + "orh r8, HI(%[ulCriticalNesting]) \n\t" \ + "ld.w r0, r8[0] \n\t" \ + "st.w --sp, r0 \n\t" \ + \ + /* Check if INT0 or higher were being handled (case where the OS tick interrupted another */ \ + /* interrupt handler (which was of a higher priority level but decided to lower its priority */ \ + /* level and allow other lower interrupt level to occur). */ \ + /* In this case we don't want to do a task switch because we don't know what the stack */ \ + /* currently looks like (we don't know what the interrupted interrupt handler was doing). */ \ + /* Saving SP in pxCurrentTCB and then later restoring it (thinking restoring the task) */ \ + /* will just be restoring the interrupt handler, no way!!! */ \ + /* So, since we won't do a vTaskSwitchContext(), it's of no use to save SP. */ \ + "ld.w r0, sp[9*4] \n\t" /* Read SR in stack */ \ + "bfextu r0, r0, 22, 3 \n\t" /* Extract the mode bits to R0. */ \ + "cp.w r0, 1 \n\t" /* Compare the mode bits with supervisor mode(b'001) */ \ + "brhi LABEL_ISR_SKIP_SAVE_CONTEXT_%[LINE] \n\t" \ + \ + /* Store SP in the first member of the structure pointed to by pxCurrentTCB */ \ + "mov r8, LO(%[pxCurrentTCB]) \n\t" \ + "orh r8, HI(%[pxCurrentTCB]) \n\t" \ + "ld.w r0, r8[0] \n\t" \ + "st.w r0[0], sp \n" \ + \ + "LABEL_ISR_SKIP_SAVE_CONTEXT_%[LINE]:" \ + : \ + :[ ulCriticalNesting ] "i" ( &ulCriticalNesting ), \ + [ pxCurrentTCB ] "i" ( &pxCurrentTCB ), \ + [ LINE ] "i" ( __LINE__ ) \ + ); \ + } /* * Input parameter: in R12, boolean. Perform a vTaskSwitchContext() if 1 */ -#define portEXIT_SWITCHING_ISR() \ -{ \ - extern volatile uint32_t ulCriticalNesting; \ - extern volatile void *volatile pxCurrentTCB; \ - \ - __asm__ __volatile__ ( \ - /* Check if INT0 or higher were being handled (case where the OS tick interrupted another */ \ - /* interrupt handler (which was of a higher priority level but decided to lower its priority */ \ - /* level and allow other lower interrupt level to occur). */ \ - /* In this case it's of no use to switch context and restore a new SP because we purposedly */ \ - /* did not previously save SP in its TCB. */ \ - "ld.w r0, sp[9*4] \n\t" /* Read SR in stack */\ - "bfextu r0, r0, 22, 3 \n\t" /* Extract the mode bits to R0. */\ - "cp.w r0, 1 \n\t" /* Compare the mode bits with supervisor mode(b'001) */\ - "brhi LABEL_ISR_SKIP_RESTORE_CONTEXT_%[LINE] \n\t"\ - \ - /* If a switch is required then we just need to call */ \ - /* vTaskSwitchContext() as the context has already been */ \ - /* saved. */ \ - "cp.w r12, 1 \n\t" /* Check if Switch context is required. */\ - "brne LABEL_ISR_RESTORE_CONTEXT_%[LINE]" \ - : \ - : [LINE] "i" (__LINE__) \ - ); \ - \ - /* A critical section has to be used here because vTaskSwitchContext handles FreeRTOS linked lists. */ \ - portENTER_CRITICAL(); \ - vTaskSwitchContext(); \ - portEXIT_CRITICAL(); \ - \ - __asm__ __volatile__ ( \ - "LABEL_ISR_RESTORE_CONTEXT_%[LINE]: \n\t"\ - /* Restore the context of which ever task is now the highest */ \ - /* priority that is ready to run. */ \ - \ - /* Restore all registers */ \ - \ - /* Set SP to point to new stack */ \ - "mov r8, LO(%[pxCurrentTCB]) \n\t"\ - "orh r8, HI(%[pxCurrentTCB]) \n\t"\ - "ld.w r0, r8[0] \n\t"\ - "ld.w sp, r0[0] \n"\ - \ - "LABEL_ISR_SKIP_RESTORE_CONTEXT_%[LINE]: \n\t"\ - \ - /* Restore ulCriticalNesting variable */ \ - "ld.w r0, sp++ \n\t"\ - "mov r8, LO(%[ulCriticalNesting]) \n\t"\ - "orh r8, HI(%[ulCriticalNesting]) \n\t"\ - "st.w r8[0], r0 \n\t"\ - \ - /* Restore R0..R7 */ \ - "ldm sp++, r0-r7 \n\t"\ - \ - /* Now, the stack should be R8..R12, LR, PC and SR */ \ - "rete" \ - : \ - : [ulCriticalNesting] "i" (&ulCriticalNesting), \ - [pxCurrentTCB] "i" (&pxCurrentTCB), \ - [LINE] "i" (__LINE__) \ - ); \ -} + #define portEXIT_SWITCHING_ISR() \ + { \ + extern volatile uint32_t ulCriticalNesting; \ + extern volatile void * volatile pxCurrentTCB; \ + \ + __asm__ __volatile__ ( \ + /* Check if INT0 or higher were being handled (case where the OS tick interrupted another */ \ + /* interrupt handler (which was of a higher priority level but decided to lower its priority */ \ + /* level and allow other lower interrupt level to occur). */ \ + /* In this case it's of no use to switch context and restore a new SP because we purposely */ \ + /* did not previously save SP in its TCB. */ \ + "ld.w r0, sp[9*4] \n\t" /* Read SR in stack */ \ + "bfextu r0, r0, 22, 3 \n\t" /* Extract the mode bits to R0. */ \ + "cp.w r0, 1 \n\t" /* Compare the mode bits with supervisor mode(b'001) */ \ + "brhi LABEL_ISR_SKIP_RESTORE_CONTEXT_%[LINE] \n\t" \ + \ + /* If a switch is required then we just need to call */ \ + /* vTaskSwitchContext() as the context has already been */ \ + /* saved. */ \ + "cp.w r12, 1 \n\t" /* Check if Switch context is required. */ \ + "brne LABEL_ISR_RESTORE_CONTEXT_%[LINE]" \ + : \ + :[ LINE ] "i" ( __LINE__ ) \ + ); \ + \ + /* A critical section has to be used here because vTaskSwitchContext handles FreeRTOS linked lists. */ \ + portENTER_CRITICAL(); \ + vTaskSwitchContext(); \ + portEXIT_CRITICAL(); \ + \ + __asm__ __volatile__ ( \ + "LABEL_ISR_RESTORE_CONTEXT_%[LINE]: \n\t" \ + /* Restore the context of which ever task is now the highest */ \ + /* priority that is ready to run. */ \ + \ + /* Restore all registers */ \ + \ + /* Set SP to point to new stack */ \ + "mov r8, LO(%[pxCurrentTCB]) \n\t" \ + "orh r8, HI(%[pxCurrentTCB]) \n\t" \ + "ld.w r0, r8[0] \n\t" \ + "ld.w sp, r0[0] \n" \ + \ + "LABEL_ISR_SKIP_RESTORE_CONTEXT_%[LINE]: \n\t" \ + \ + /* Restore ulCriticalNesting variable */ \ + "ld.w r0, sp++ \n\t" \ + "mov r8, LO(%[ulCriticalNesting]) \n\t" \ + "orh r8, HI(%[ulCriticalNesting]) \n\t" \ + "st.w r8[0], r0 \n\t" \ + \ + /* Restore R0..R7 */ \ + "ldm sp++, r0-r7 \n\t" \ + \ + /* Now, the stack should be R8..R12, LR, PC and SR */ \ + "rete" \ + : \ + :[ ulCriticalNesting ] "i" ( &ulCriticalNesting ), \ + [ pxCurrentTCB ] "i" ( &pxCurrentTCB ), \ + [ LINE ] "i" ( __LINE__ ) \ + ); \ + } -#endif +#endif /* if configUSE_PREEMPTION == 0 */ -#define portYIELD() {__asm__ __volatile__ ("scall");} +#define portYIELD() { __asm__ __volatile__ ( "scall" ); } /* Task function macros as described on the FreeRTOS.org WEB site. */ -#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters ) -#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters ) +#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters ) +#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters ) /* *INDENT-OFF* */ #ifdef __cplusplus diff --git a/Source/portable/GCC/Arm_AARCH64/README.md b/Source/portable/GCC/Arm_AARCH64/README.md new file mode 100644 index 000000000..70552c202 --- /dev/null +++ b/Source/portable/GCC/Arm_AARCH64/README.md @@ -0,0 +1,23 @@ +# Armv8-A architecture support + +The Armv8-A architecture introduces the ability to use 64-bit and 32-bit +Execution states, known as AArch64 and AArch32 respectively. The AArch64 +Execution state supports the A64 instruction set. It holds addresses in 64-bit +registers and allows instructions in the base instruction set to use 64-bit +registers for their processing. + +The AArch32 Execution state is a 32-bit Execution state that preserves +backwards compatibility with the Armv7-A architecture, enhancing that profile +so that it can support some features included in the AArch64 state. It supports +the T32 and A32 instruction sets. Follow the +[link](https://developer.arm.com/Architectures/A-Profile%20Architecture) +for more information. + +## Arm_AARCH64 port + +This port adds support for Armv8-A architecture AArch64 execution state. +This port is generic and can be used as a starting point for Armv8-A +application processors. + +* Arm_AARCH64 + * Memory mapped interace to access Arm GIC registers diff --git a/Source/portable/GCC/ARM_CA53_64_BIT/port.c b/Source/portable/GCC/Arm_AARCH64/port.c similarity index 54% rename from Source/portable/GCC/ARM_CA53_64_BIT/port.c rename to Source/portable/GCC/Arm_AARCH64/port.c index 36f55d4d9..b3e879611 100644 --- a/Source/portable/GCC/ARM_CA53_64_BIT/port.c +++ b/Source/portable/GCC/Arm_AARCH64/port.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -34,104 +34,104 @@ #include "task.h" #ifndef configINTERRUPT_CONTROLLER_BASE_ADDRESS - #error configINTERRUPT_CONTROLLER_BASE_ADDRESS must be defined. See https://www.FreeRTOS.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html + #error "configINTERRUPT_CONTROLLER_BASE_ADDRESS must be defined. See www.FreeRTOS.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html" #endif #ifndef configINTERRUPT_CONTROLLER_CPU_INTERFACE_OFFSET - #error configINTERRUPT_CONTROLLER_CPU_INTERFACE_OFFSET must be defined. See https://www.FreeRTOS.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html + #error "configINTERRUPT_CONTROLLER_CPU_INTERFACE_OFFSET must be defined. See www.FreeRTOS.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html" #endif #ifndef configUNIQUE_INTERRUPT_PRIORITIES - #error configUNIQUE_INTERRUPT_PRIORITIES must be defined. See https://www.FreeRTOS.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html + #error "configUNIQUE_INTERRUPT_PRIORITIES must be defined. See www.FreeRTOS.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html" #endif #ifndef configSETUP_TICK_INTERRUPT - #error configSETUP_TICK_INTERRUPT() must be defined. See https://www.FreeRTOS.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html + #error "configSETUP_TICK_INTERRUPT() must be defined. See www.FreeRTOS.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html" #endif /* configSETUP_TICK_INTERRUPT */ #ifndef configMAX_API_CALL_INTERRUPT_PRIORITY - #error configMAX_API_CALL_INTERRUPT_PRIORITY must be defined. See https://www.FreeRTOS.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html + #error "configMAX_API_CALL_INTERRUPT_PRIORITY must be defined. See www.FreeRTOS.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html" #endif #if configMAX_API_CALL_INTERRUPT_PRIORITY == 0 - #error configMAX_API_CALL_INTERRUPT_PRIORITY must not be set to 0 + #error "configMAX_API_CALL_INTERRUPT_PRIORITY must not be set to 0" #endif #if configMAX_API_CALL_INTERRUPT_PRIORITY > configUNIQUE_INTERRUPT_PRIORITIES - #error configMAX_API_CALL_INTERRUPT_PRIORITY must be less than or equal to configUNIQUE_INTERRUPT_PRIORITIES as the lower the numeric priority value the higher the logical interrupt priority + #error "configMAX_API_CALL_INTERRUPT_PRIORITY must be less than or equal to configUNIQUE_INTERRUPT_PRIORITIES as the lower the numeric priority value the higher the logical interrupt priority" #endif #if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 /* Check the configuration. */ - #if( configMAX_PRIORITIES > 32 ) - #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice. + #if ( configMAX_PRIORITIES > 32 ) + #error "configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice." #endif #endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */ /* In case security extensions are implemented. */ #if configMAX_API_CALL_INTERRUPT_PRIORITY <= ( configUNIQUE_INTERRUPT_PRIORITIES / 2 ) - #error configMAX_API_CALL_INTERRUPT_PRIORITY must be greater than ( configUNIQUE_INTERRUPT_PRIORITIES / 2 ) + #error "configMAX_API_CALL_INTERRUPT_PRIORITY must be greater than ( configUNIQUE_INTERRUPT_PRIORITIES / 2 )" #endif /* Some vendor specific files default configCLEAR_TICK_INTERRUPT() in -portmacro.h. */ + * portmacro.h. */ #ifndef configCLEAR_TICK_INTERRUPT #define configCLEAR_TICK_INTERRUPT() #endif /* A critical section is exited when the critical section nesting count reaches -this value. */ -#define portNO_CRITICAL_NESTING ( ( size_t ) 0 ) + * this value. */ +#define portNO_CRITICAL_NESTING ( ( size_t ) 0 ) /* In all GICs 255 can be written to the priority mask register to unmask all -(but the lowest) interrupt priority. */ -#define portUNMASK_VALUE ( 0xFFUL ) + * (but the lowest) interrupt priority. */ +#define portUNMASK_VALUE ( 0xFFUL ) /* Tasks are not created with a floating point context, but can be given a -floating point context after they have been created. A variable is stored as -part of the tasks context that holds portNO_FLOATING_POINT_CONTEXT if the task -does not have an FPU context, or any other value if the task does have an FPU -context. */ -#define portNO_FLOATING_POINT_CONTEXT ( ( StackType_t ) 0 ) + * floating point context after they have been created. A variable is stored as + * part of the tasks context that holds portNO_FLOATING_POINT_CONTEXT if the task + * does not have an FPU context, or any other value if the task does have an FPU + * context. */ +#define portNO_FLOATING_POINT_CONTEXT ( ( StackType_t ) 0 ) /* Constants required to setup the initial task context. */ -#define portSP_ELx ( ( StackType_t ) 0x01 ) -#define portSP_EL0 ( ( StackType_t ) 0x00 ) +#define portSP_ELx ( ( StackType_t ) 0x01 ) +#define portSP_EL0 ( ( StackType_t ) 0x00 ) #if defined( GUEST ) - #define portEL1 ( ( StackType_t ) 0x04 ) - #define portINITIAL_PSTATE ( portEL1 | portSP_EL0 ) + #define portEL1 ( ( StackType_t ) 0x04 ) + #define portINITIAL_PSTATE ( portEL1 | portSP_EL0 ) #else - #define portEL3 ( ( StackType_t ) 0x0c ) + #define portEL3 ( ( StackType_t ) 0x0c ) /* At the time of writing, the BSP only supports EL3. */ - #define portINITIAL_PSTATE ( portEL3 | portSP_EL0 ) + #define portINITIAL_PSTATE ( portEL3 | portSP_EL0 ) #endif /* Used by portASSERT_IF_INTERRUPT_PRIORITY_INVALID() when ensuring the binary -point is zero. */ -#define portBINARY_POINT_BITS ( ( uint8_t ) 0x03 ) + * point is zero. */ +#define portBINARY_POINT_BITS ( ( uint8_t ) 0x03 ) /* Masks all bits in the APSR other than the mode bits. */ -#define portAPSR_MODE_BITS_MASK ( 0x0C ) +#define portAPSR_MODE_BITS_MASK ( 0x0C ) /* The I bit in the DAIF bits. */ -#define portDAIF_I ( 0x80 ) +#define portDAIF_I ( 0x80 ) /* Macro to unmask all interrupt priorities. */ -#define portCLEAR_INTERRUPT_MASK() \ -{ \ - portDISABLE_INTERRUPTS(); \ - portICCPMR_PRIORITY_MASK_REGISTER = portUNMASK_VALUE; \ - __asm volatile ( "DSB SY \n" \ - "ISB SY \n" ); \ - portENABLE_INTERRUPTS(); \ -} +#define portCLEAR_INTERRUPT_MASK() \ + { \ + portDISABLE_INTERRUPTS(); \ + portICCPMR_PRIORITY_MASK_REGISTER = portUNMASK_VALUE; \ + __asm volatile ( "DSB SY \n" \ + "ISB SY \n" ); \ + portENABLE_INTERRUPTS(); \ + } /* Hardware specifics used when sanity checking the configuration. */ -#define portINTERRUPT_PRIORITY_REGISTER_OFFSET 0x400UL -#define portMAX_8_BIT_VALUE ( ( uint8_t ) 0xff ) -#define portBIT_0_SET ( ( uint8_t ) 0x01 ) +#define portINTERRUPT_PRIORITY_REGISTER_OFFSET 0x400UL +#define portMAX_8_BIT_VALUE ( ( uint8_t ) 0xff ) +#define portBIT_0_SET ( ( uint8_t ) 0x01 ) /*-----------------------------------------------------------*/ @@ -144,104 +144,106 @@ extern void vPortRestoreTaskContext( void ); /*-----------------------------------------------------------*/ /* A variable is used to keep track of the critical section nesting. This -variable has to be stored as part of the task context and must be initialised to -a non zero value to ensure interrupts don't inadvertently become unmasked before -the scheduler starts. As it is stored as part of the task context it will -automatically be set to 0 when the first task is started. */ + * variable has to be stored as part of the task context and must be initialised to + * a non zero value to ensure interrupts don't inadvertently become unmasked before + * the scheduler starts. As it is stored as part of the task context it will + * automatically be set to 0 when the first task is started. */ volatile uint64_t ullCriticalNesting = 9999ULL; /* Saved as part of the task context. If ullPortTaskHasFPUContext is non-zero -then floating point context must be saved and restored for the task. */ + * then floating point context must be saved and restored for the task. */ uint64_t ullPortTaskHasFPUContext = pdFALSE; /* Set to 1 to pend a context switch from an ISR. */ uint64_t ullPortYieldRequired = pdFALSE; /* Counts the interrupt nesting depth. A context switch is only performed if -if the nesting depth is 0. */ + * if the nesting depth is 0. */ uint64_t ullPortInterruptNesting = 0; /* Used in the ASM code. */ -__attribute__(( used )) const uint64_t ullICCEOIR = portICCEOIR_END_OF_INTERRUPT_REGISTER_ADDRESS; -__attribute__(( used )) const uint64_t ullICCIAR = portICCIAR_INTERRUPT_ACKNOWLEDGE_REGISTER_ADDRESS; -__attribute__(( used )) const uint64_t ullICCPMR = portICCPMR_PRIORITY_MASK_REGISTER_ADDRESS; -__attribute__(( used )) const uint64_t ullMaxAPIPriorityMask = ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT ); +__attribute__( ( used ) ) const uint64_t ullICCEOIR = portICCEOIR_END_OF_INTERRUPT_REGISTER_ADDRESS; +__attribute__( ( used ) ) const uint64_t ullICCIAR = portICCIAR_INTERRUPT_ACKNOWLEDGE_REGISTER_ADDRESS; +__attribute__( ( used ) ) const uint64_t ullICCPMR = portICCPMR_PRIORITY_MASK_REGISTER_ADDRESS; +__attribute__( ( used ) ) const uint64_t ullMaxAPIPriorityMask = ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT ); /*-----------------------------------------------------------*/ /* * See header file for description. */ -StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters ) +StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, + TaskFunction_t pxCode, + void * pvParameters ) { /* Setup the initial stack of the task. The stack is set exactly as - expected by the portRESTORE_CONTEXT() macro. */ + * expected by the portRESTORE_CONTEXT() macro. */ /* First all the general purpose registers. */ pxTopOfStack--; - *pxTopOfStack = 0x0101010101010101ULL; /* R1 */ + *pxTopOfStack = 0x0101010101010101ULL; /* R1 */ pxTopOfStack--; *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */ pxTopOfStack--; - *pxTopOfStack = 0x0303030303030303ULL; /* R3 */ + *pxTopOfStack = 0x0303030303030303ULL; /* R3 */ pxTopOfStack--; - *pxTopOfStack = 0x0202020202020202ULL; /* R2 */ + *pxTopOfStack = 0x0202020202020202ULL; /* R2 */ pxTopOfStack--; - *pxTopOfStack = 0x0505050505050505ULL; /* R5 */ + *pxTopOfStack = 0x0505050505050505ULL; /* R5 */ pxTopOfStack--; - *pxTopOfStack = 0x0404040404040404ULL; /* R4 */ + *pxTopOfStack = 0x0404040404040404ULL; /* R4 */ pxTopOfStack--; - *pxTopOfStack = 0x0707070707070707ULL; /* R7 */ + *pxTopOfStack = 0x0707070707070707ULL; /* R7 */ pxTopOfStack--; - *pxTopOfStack = 0x0606060606060606ULL; /* R6 */ + *pxTopOfStack = 0x0606060606060606ULL; /* R6 */ pxTopOfStack--; - *pxTopOfStack = 0x0909090909090909ULL; /* R9 */ + *pxTopOfStack = 0x0909090909090909ULL; /* R9 */ pxTopOfStack--; - *pxTopOfStack = 0x0808080808080808ULL; /* R8 */ + *pxTopOfStack = 0x0808080808080808ULL; /* R8 */ pxTopOfStack--; - *pxTopOfStack = 0x1111111111111111ULL; /* R11 */ + *pxTopOfStack = 0x1111111111111111ULL; /* R11 */ pxTopOfStack--; - *pxTopOfStack = 0x1010101010101010ULL; /* R10 */ + *pxTopOfStack = 0x1010101010101010ULL; /* R10 */ pxTopOfStack--; - *pxTopOfStack = 0x1313131313131313ULL; /* R13 */ + *pxTopOfStack = 0x1313131313131313ULL; /* R13 */ pxTopOfStack--; - *pxTopOfStack = 0x1212121212121212ULL; /* R12 */ + *pxTopOfStack = 0x1212121212121212ULL; /* R12 */ pxTopOfStack--; - *pxTopOfStack = 0x1515151515151515ULL; /* R15 */ + *pxTopOfStack = 0x1515151515151515ULL; /* R15 */ pxTopOfStack--; - *pxTopOfStack = 0x1414141414141414ULL; /* R14 */ + *pxTopOfStack = 0x1414141414141414ULL; /* R14 */ pxTopOfStack--; - *pxTopOfStack = 0x1717171717171717ULL; /* R17 */ + *pxTopOfStack = 0x1717171717171717ULL; /* R17 */ pxTopOfStack--; - *pxTopOfStack = 0x1616161616161616ULL; /* R16 */ + *pxTopOfStack = 0x1616161616161616ULL; /* R16 */ pxTopOfStack--; - *pxTopOfStack = 0x1919191919191919ULL; /* R19 */ + *pxTopOfStack = 0x1919191919191919ULL; /* R19 */ pxTopOfStack--; - *pxTopOfStack = 0x1818181818181818ULL; /* R18 */ + *pxTopOfStack = 0x1818181818181818ULL; /* R18 */ pxTopOfStack--; - *pxTopOfStack = 0x2121212121212121ULL; /* R21 */ + *pxTopOfStack = 0x2121212121212121ULL; /* R21 */ pxTopOfStack--; - *pxTopOfStack = 0x2020202020202020ULL; /* R20 */ + *pxTopOfStack = 0x2020202020202020ULL; /* R20 */ pxTopOfStack--; - *pxTopOfStack = 0x2323232323232323ULL; /* R23 */ + *pxTopOfStack = 0x2323232323232323ULL; /* R23 */ pxTopOfStack--; - *pxTopOfStack = 0x2222222222222222ULL; /* R22 */ + *pxTopOfStack = 0x2222222222222222ULL; /* R22 */ pxTopOfStack--; - *pxTopOfStack = 0x2525252525252525ULL; /* R25 */ + *pxTopOfStack = 0x2525252525252525ULL; /* R25 */ pxTopOfStack--; - *pxTopOfStack = 0x2424242424242424ULL; /* R24 */ + *pxTopOfStack = 0x2424242424242424ULL; /* R24 */ pxTopOfStack--; - *pxTopOfStack = 0x2727272727272727ULL; /* R27 */ + *pxTopOfStack = 0x2727272727272727ULL; /* R27 */ pxTopOfStack--; - *pxTopOfStack = 0x2626262626262626ULL; /* R26 */ + *pxTopOfStack = 0x2626262626262626ULL; /* R26 */ pxTopOfStack--; - *pxTopOfStack = 0x2929292929292929ULL; /* R29 */ + *pxTopOfStack = 0x2929292929292929ULL; /* R29 */ pxTopOfStack--; - *pxTopOfStack = 0x2828282828282828ULL; /* R28 */ + *pxTopOfStack = 0x2828282828282828ULL; /* R28 */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x00; /* XZR - has no effect, used so there are an even number of registers. */ + *pxTopOfStack = ( StackType_t ) 0x00; /* XZR - has no effect, used so there are an even number of registers. */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x00; /* R30 - procedure call link register. */ + *pxTopOfStack = ( StackType_t ) 0x00; /* R30 - procedure call link register. */ pxTopOfStack--; *pxTopOfStack = portINITIAL_PSTATE; @@ -251,13 +253,13 @@ StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t px pxTopOfStack--; /* The task will start with a critical nesting count of 0 as interrupts are - enabled. */ + * enabled. */ *pxTopOfStack = portNO_CRITICAL_NESTING; pxTopOfStack--; /* The task will start without a floating point context. A task that uses - the floating point hardware must call vPortTaskUsesFPU() before executing - any floating point instructions. */ + * the floating point hardware must call vPortTaskUsesFPU() before executing + * any floating point instructions. */ *pxTopOfStack = portNO_FLOATING_POINT_CONTEXT; return pxTopOfStack; @@ -266,21 +268,21 @@ StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t px BaseType_t xPortStartScheduler( void ) { -uint32_t ulAPSR; + uint32_t ulAPSR; - #if( configASSERT_DEFINED == 1 ) + #if ( configASSERT_DEFINED == 1 ) { volatile uint8_t ucOriginalPriority; volatile uint8_t * const pucFirstUserPriorityRegister = ( volatile uint8_t * const ) ( configINTERRUPT_CONTROLLER_BASE_ADDRESS + portINTERRUPT_PRIORITY_REGISTER_OFFSET ); volatile uint8_t ucMaxPriorityValue; /* Determine how many priority bits are implemented in the GIC. - - Save the interrupt priority value that is about to be clobbered. */ + * + * Save the interrupt priority value that is about to be clobbered. */ ucOriginalPriority = *pucFirstUserPriorityRegister; /* Determine the number of priority bits available. First write to - all possible bits. */ + * all possible bits. */ *pucFirstUserPriorityRegister = portMAX_8_BIT_VALUE; /* Read the value back to see how many bits stuck. */ @@ -293,13 +295,13 @@ uint32_t ulAPSR; } /* Sanity check configUNIQUE_INTERRUPT_PRIORITIES matches the read - value. */ + * value. */ configASSERT( ucMaxPriorityValue >= portLOWEST_INTERRUPT_PRIORITY ); /* Restore the clobbered interrupt priority register to its original - value. */ + * value. */ *pucFirstUserPriorityRegister = ucOriginalPriority; } #endif /* configASSERT_DEFINED */ @@ -309,26 +311,28 @@ uint32_t ulAPSR; __asm volatile ( "MRS %0, CurrentEL" : "=r" ( ulAPSR ) ); ulAPSR &= portAPSR_MODE_BITS_MASK; -#if defined( GUEST ) - #warning Building for execution as a guest under XEN. THIS IS NOT A FULLY TESTED PATH. - configASSERT( ulAPSR == portEL1 ); - if( ulAPSR == portEL1 ) -#else - configASSERT( ulAPSR == portEL3 ); - if( ulAPSR == portEL3 ) -#endif + #if defined( GUEST ) + #warning "Building for execution as a guest under XEN. THIS IS NOT A FULLY TESTED PATH." + configASSERT( ulAPSR == portEL1 ); + + if( ulAPSR == portEL1 ) + #else + configASSERT( ulAPSR == portEL3 ); + + if( ulAPSR == portEL3 ) + #endif { /* Only continue if the binary point value is set to its lowest possible - setting. See the comments in vPortValidateInterruptPriority() below for - more information. */ + * setting. See the comments in vPortValidateInterruptPriority() below for + * more information. */ configASSERT( ( portICCBPR_BINARY_POINT_REGISTER & portBINARY_POINT_BITS ) <= portMAX_BINARY_POINT_VALUE ); if( ( portICCBPR_BINARY_POINT_REGISTER & portBINARY_POINT_BITS ) <= portMAX_BINARY_POINT_VALUE ) { /* Interrupts are turned off in the CPU itself to ensure a tick does - not execute while the scheduler is being started. Interrupts are - automatically turned back on in the CPU when the first task starts - executing. */ + * not execute while the scheduler is being started. Interrupts are + * automatically turned back on in the CPU when the first task starts + * executing. */ portDISABLE_INTERRUPTS(); /* Start the timer that generates the tick ISR. */ @@ -346,7 +350,7 @@ uint32_t ulAPSR; void vPortEndScheduler( void ) { /* Not implemented in ports where there is nothing to return to. - Artificially force an assert. */ + * Artificially force an assert. */ configASSERT( ullCriticalNesting == 1000ULL ); } /*-----------------------------------------------------------*/ @@ -357,15 +361,15 @@ void vPortEnterCritical( void ) uxPortSetInterruptMask(); /* Now interrupts are disabled ullCriticalNesting can be accessed - directly. Increment ullCriticalNesting to keep a count of how many times - portENTER_CRITICAL() has been called. */ + * directly. Increment ullCriticalNesting to keep a count of how many times + * portENTER_CRITICAL() has been called. */ ullCriticalNesting++; /* This is not the interrupt safe version of the enter critical function so - assert() if it is being called from an interrupt context. Only API - functions that end in "FromISR" can be used in an interrupt. Only assert if - the critical nesting count is 1 to protect against recursive calls if the - assert function also uses a critical section. */ + * assert() if it is being called from an interrupt context. Only API + * functions that end in "FromISR" can be used in an interrupt. Only assert if + * the critical nesting count is 1 to protect against recursive calls if the + * assert function also uses a critical section. */ if( ullCriticalNesting == 1ULL ) { configASSERT( ullPortInterruptNesting == 0 ); @@ -378,15 +382,15 @@ void vPortExitCritical( void ) if( ullCriticalNesting > portNO_CRITICAL_NESTING ) { /* Decrement the nesting count as the critical section is being - exited. */ + * exited. */ ullCriticalNesting--; /* If the nesting level has reached zero then all interrupt - priorities must be re-enabled. */ + * priorities must be re-enabled. */ if( ullCriticalNesting == portNO_CRITICAL_NESTING ) { /* Critical nesting has reached zero so all interrupt priorities - should be unmasked. */ + * should be unmasked. */ portCLEAR_INTERRUPT_MASK(); } } @@ -403,23 +407,23 @@ void FreeRTOS_Tick_Handler( void ) #endif /* Interrupts should not be enabled before this point. */ - #if( configASSERT_DEFINED == 1 ) + #if ( configASSERT_DEFINED == 1 ) { uint32_t ulMaskBits; - __asm volatile( "mrs %0, daif" : "=r"( ulMaskBits ) :: "memory" ); + __asm volatile ( "mrs %0, daif" : "=r" ( ulMaskBits )::"memory" ); configASSERT( ( ulMaskBits & portDAIF_I ) != 0 ); } #endif /* configASSERT_DEFINED */ /* Set interrupt mask before altering scheduler structures. The tick - handler runs at the lowest priority, so interrupts cannot already be masked, - so there is no need to save and restore the current mask value. It is - necessary to turn off interrupts in the CPU itself while the ICCPMR is being - updated. */ + * handler runs at the lowest priority, so interrupts cannot already be masked, + * so there is no need to save and restore the current mask value. It is + * necessary to turn off interrupts in the CPU itself while the ICCPMR is being + * updated. */ portICCPMR_PRIORITY_MASK_REGISTER = ( uint32_t ) ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT ); - __asm volatile ( "dsb sy \n" - "isb sy \n" ::: "memory" ); + __asm volatile ( "dsb sy \n" + "isb sy \n" ::: "memory" ); /* Ok to enable interrupts after the interrupt source has been cleared. */ configCLEAR_TICK_INTERRUPT(); @@ -439,11 +443,11 @@ void FreeRTOS_Tick_Handler( void ) void vPortTaskUsesFPU( void ) { /* A task is registering the fact that it needs an FPU context. Set the - FPU flag (which is saved as part of the task context). */ + * FPU flag (which is saved as part of the task context). */ ullPortTaskHasFPUContext = pdTRUE; /* Consider initialising the FPSR here - but probably not necessary in - AArch64. */ + * AArch64. */ } /*-----------------------------------------------------------*/ @@ -458,11 +462,12 @@ void vPortClearInterruptMask( UBaseType_t uxNewMaskValue ) UBaseType_t uxPortSetInterruptMask( void ) { -uint32_t ulReturn; + uint32_t ulReturn; /* Interrupt in the CPU must be turned off while the ICCPMR is being - updated. */ + * updated. */ portDISABLE_INTERRUPTS(); + if( portICCPMR_PRIORITY_MASK_REGISTER == ( uint32_t ) ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT ) ) { /* Interrupts were already masked. */ @@ -472,45 +477,46 @@ uint32_t ulReturn; { ulReturn = pdFALSE; portICCPMR_PRIORITY_MASK_REGISTER = ( uint32_t ) ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT ); - __asm volatile ( "dsb sy \n" - "isb sy \n" ::: "memory" ); + __asm volatile ( "dsb sy \n" + "isb sy \n" ::: "memory" ); } + portENABLE_INTERRUPTS(); return ulReturn; } /*-----------------------------------------------------------*/ -#if( configASSERT_DEFINED == 1 ) +#if ( configASSERT_DEFINED == 1 ) void vPortValidateInterruptPriority( void ) { /* The following assertion will fail if a service routine (ISR) for - an interrupt that has been assigned a priority above - configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API - function. ISR safe FreeRTOS API functions must *only* be called - from interrupts that have been assigned a priority at or below - configMAX_SYSCALL_INTERRUPT_PRIORITY. - - Numerically low interrupt priority numbers represent logically high - interrupt priorities, therefore the priority of the interrupt must - be set to a value equal to or numerically *higher* than - configMAX_SYSCALL_INTERRUPT_PRIORITY. - - FreeRTOS maintains separate thread and ISR API functions to ensure - interrupt entry is as fast and simple as possible. */ + * an interrupt that has been assigned a priority above + * configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API + * function. ISR safe FreeRTOS API functions must *only* be called + * from interrupts that have been assigned a priority at or below + * configMAX_SYSCALL_INTERRUPT_PRIORITY. + * + * Numerically low interrupt priority numbers represent logically high + * interrupt priorities, therefore the priority of the interrupt must + * be set to a value equal to or numerically *higher* than + * configMAX_SYSCALL_INTERRUPT_PRIORITY. + * + * FreeRTOS maintains separate thread and ISR API functions to ensure + * interrupt entry is as fast and simple as possible. */ configASSERT( portICCRPR_RUNNING_PRIORITY_REGISTER >= ( uint32_t ) ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT ) ); /* Priority grouping: The interrupt controller (GIC) allows the bits - that define each interrupt's priority to be split between bits that - define the interrupt's pre-emption priority bits and bits that define - the interrupt's sub-priority. For simplicity all bits must be defined - to be pre-emption priority bits. The following assertion will fail if - this is not the case (if some bits represent a sub-priority). - - The priority grouping is configured by the GIC's binary point register - (ICCBPR). Writting 0 to ICCBPR will ensure it is set to its lowest - possible value (which may be above 0). */ + * that define each interrupt's priority to be split between bits that + * define the interrupt's pre-emption priority bits and bits that define + * the interrupt's sub-priority. For simplicity all bits must be defined + * to be pre-emption priority bits. The following assertion will fail if + * this is not the case (if some bits represent a sub-priority). + * + * The priority grouping is configured by the GIC's binary point register + * (ICCBPR). Writting 0 to ICCBPR will ensure it is set to its lowest + * possible value (which may be above 0). */ configASSERT( ( portICCBPR_BINARY_POINT_REGISTER & portBINARY_POINT_BITS ) <= portMAX_BINARY_POINT_VALUE ); } diff --git a/Source/portable/GCC/ARM_CA53_64_BIT/portASM.S b/Source/portable/GCC/Arm_AARCH64/portASM.S similarity index 99% rename from Source/portable/GCC/ARM_CA53_64_BIT/portASM.S rename to Source/portable/GCC/Arm_AARCH64/portASM.S index 3422f0f20..242ed3cd4 100644 --- a/Source/portable/GCC/ARM_CA53_64_BIT/portASM.S +++ b/Source/portable/GCC/Arm_AARCH64/portASM.S @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/Source/portable/GCC/Arm_AARCH64/portmacro.h b/Source/portable/GCC/Arm_AARCH64/portmacro.h new file mode 100644 index 000000000..d474a1376 --- /dev/null +++ b/Source/portable/GCC/Arm_AARCH64/portmacro.h @@ -0,0 +1,215 @@ +/* + * FreeRTOS Kernel V11.0.1 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef PORTMACRO_H +#define PORTMACRO_H + +/* *INDENT-OFF* */ +#ifdef __cplusplus + extern "C" { +#endif +/* *INDENT-ON* */ + +/*----------------------------------------------------------- + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the given hardware + * and compiler. + * + * These settings should not be altered. + *----------------------------------------------------------- + */ + +/* Type definitions. */ +#define portCHAR char +#define portFLOAT float +#define portDOUBLE double +#define portLONG long +#define portSHORT short +#define portSTACK_TYPE size_t +#define portBASE_TYPE long + +typedef portSTACK_TYPE StackType_t; +typedef portBASE_TYPE BaseType_t; +typedef uint64_t UBaseType_t; + +typedef uint64_t TickType_t; +#define portMAX_DELAY ( ( TickType_t ) 0xffffffffffffffff ) + +/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do + * not need to be guarded with a critical section. */ +#define portTICK_TYPE_IS_ATOMIC 1 + +/*-----------------------------------------------------------*/ + +/* Hardware specifics. */ +#define portSTACK_GROWTH ( -1 ) +#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) +#define portBYTE_ALIGNMENT 16 +#define portPOINTER_SIZE_TYPE uint64_t + +/*-----------------------------------------------------------*/ + +/* Task utilities. */ + +/* Called at the end of an ISR that can cause a context switch. */ +#define portEND_SWITCHING_ISR( xSwitchRequired ) \ + { \ + extern uint64_t ullPortYieldRequired; \ + \ + if( xSwitchRequired != pdFALSE ) \ + { \ + ullPortYieldRequired = pdTRUE; \ + } \ + } + +#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x ) +#if defined( GUEST ) + #define portYIELD() __asm volatile ( "SVC 0" ::: "memory" ) +#else + #define portYIELD() __asm volatile ( "SMC 0" ::: "memory" ) +#endif + +/*----------------------------------------------------------- +* Critical section control +*----------------------------------------------------------*/ + +extern void vPortEnterCritical( void ); +extern void vPortExitCritical( void ); +extern UBaseType_t uxPortSetInterruptMask( void ); +extern void vPortClearInterruptMask( UBaseType_t uxNewMaskValue ); +extern void vPortInstallFreeRTOSVectorTable( void ); + +#define portDISABLE_INTERRUPTS() \ + __asm volatile ( "MSR DAIFSET, #2" ::: "memory" ); \ + __asm volatile ( "DSB SY" ); \ + __asm volatile ( "ISB SY" ); + +#define portENABLE_INTERRUPTS() \ + __asm volatile ( "MSR DAIFCLR, #2" ::: "memory" ); \ + __asm volatile ( "DSB SY" ); \ + __asm volatile ( "ISB SY" ); + + +/* These macros do not globally disable/enable interrupts. They do mask off + * interrupts that have a priority below configMAX_API_CALL_INTERRUPT_PRIORITY. */ +#define portENTER_CRITICAL() vPortEnterCritical(); +#define portEXIT_CRITICAL() vPortExitCritical(); +#define portSET_INTERRUPT_MASK_FROM_ISR() uxPortSetInterruptMask() +#define portCLEAR_INTERRUPT_MASK_FROM_ISR( x ) vPortClearInterruptMask( x ) + +/*-----------------------------------------------------------*/ + +/* Task function macros as described on the FreeRTOS.org WEB site. These are + * not required for this port but included in case common demo code that uses these + * macros is used. */ +#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters ) +#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters ) + +/* Prototype of the FreeRTOS tick handler. This must be installed as the + * handler for whichever peripheral is used to generate the RTOS tick. */ +void FreeRTOS_Tick_Handler( void ); + +/* Any task that uses the floating point unit MUST call vPortTaskUsesFPU() + * before any floating point instructions are executed. */ +void vPortTaskUsesFPU( void ); +#define portTASK_USES_FLOATING_POINT() vPortTaskUsesFPU() + +#define portLOWEST_INTERRUPT_PRIORITY ( ( ( uint32_t ) configUNIQUE_INTERRUPT_PRIORITIES ) - 1UL ) +#define portLOWEST_USABLE_INTERRUPT_PRIORITY ( portLOWEST_INTERRUPT_PRIORITY - 1UL ) + +/* Architecture specific optimisations. */ +#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION + #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1 +#endif + +#if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 + +/* Store/clear the ready priorities in a bit map. */ + #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) ) + #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) ) + +/*-----------------------------------------------------------*/ + + #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31 - __builtin_clz( uxReadyPriorities ) ) + +#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */ + +#ifdef configASSERT + void vPortValidateInterruptPriority( void ); + #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() vPortValidateInterruptPriority() +#endif /* configASSERT */ + +#define portNOP() __asm volatile ( "NOP" ) +#define portINLINE __inline + +/* The number of bits to shift for an interrupt priority is dependent on the + * number of bits implemented by the interrupt controller. */ +#if configUNIQUE_INTERRUPT_PRIORITIES == 16 + #define portPRIORITY_SHIFT 4 + #define portMAX_BINARY_POINT_VALUE 3 +#elif configUNIQUE_INTERRUPT_PRIORITIES == 32 + #define portPRIORITY_SHIFT 3 + #define portMAX_BINARY_POINT_VALUE 2 +#elif configUNIQUE_INTERRUPT_PRIORITIES == 64 + #define portPRIORITY_SHIFT 2 + #define portMAX_BINARY_POINT_VALUE 1 +#elif configUNIQUE_INTERRUPT_PRIORITIES == 128 + #define portPRIORITY_SHIFT 1 + #define portMAX_BINARY_POINT_VALUE 0 +#elif configUNIQUE_INTERRUPT_PRIORITIES == 256 + #define portPRIORITY_SHIFT 0 + #define portMAX_BINARY_POINT_VALUE 0 +#else /* if configUNIQUE_INTERRUPT_PRIORITIES == 16 */ + #error Invalid configUNIQUE_INTERRUPT_PRIORITIES setting. configUNIQUE_INTERRUPT_PRIORITIES must be set to the number of unique priorities implemented by the target hardware +#endif /* if configUNIQUE_INTERRUPT_PRIORITIES == 16 */ + +/* Interrupt controller access addresses. */ +#define portICCPMR_PRIORITY_MASK_OFFSET ( 0x04 ) +#define portICCIAR_INTERRUPT_ACKNOWLEDGE_OFFSET ( 0x0C ) +#define portICCEOIR_END_OF_INTERRUPT_OFFSET ( 0x10 ) +#define portICCBPR_BINARY_POINT_OFFSET ( 0x08 ) +#define portICCRPR_RUNNING_PRIORITY_OFFSET ( 0x14 ) + +#define portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS ( configINTERRUPT_CONTROLLER_BASE_ADDRESS + configINTERRUPT_CONTROLLER_CPU_INTERFACE_OFFSET ) +#define portICCPMR_PRIORITY_MASK_REGISTER ( *( ( volatile uint32_t * ) ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCPMR_PRIORITY_MASK_OFFSET ) ) ) +#define portICCIAR_INTERRUPT_ACKNOWLEDGE_REGISTER_ADDRESS ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCIAR_INTERRUPT_ACKNOWLEDGE_OFFSET ) +#define portICCEOIR_END_OF_INTERRUPT_REGISTER_ADDRESS ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCEOIR_END_OF_INTERRUPT_OFFSET ) +#define portICCPMR_PRIORITY_MASK_REGISTER_ADDRESS ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCPMR_PRIORITY_MASK_OFFSET ) +#define portICCBPR_BINARY_POINT_REGISTER ( *( ( const volatile uint32_t * ) ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCBPR_BINARY_POINT_OFFSET ) ) ) +#define portICCRPR_RUNNING_PRIORITY_REGISTER ( *( ( const volatile uint32_t * ) ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCRPR_RUNNING_PRIORITY_OFFSET ) ) ) + +#define portMEMORY_BARRIER() __asm volatile ( "" ::: "memory" ) + +/* *INDENT-OFF* */ +#ifdef __cplusplus + } +#endif +/* *INDENT-ON* */ + +#endif /* PORTMACRO_H */ diff --git a/Source/portable/GCC/Arm_AARCH64_SRE/README.md b/Source/portable/GCC/Arm_AARCH64_SRE/README.md new file mode 100644 index 000000000..0b2e0e485 --- /dev/null +++ b/Source/portable/GCC/Arm_AARCH64_SRE/README.md @@ -0,0 +1,23 @@ +# Armv8-A architecture support + +The Armv8-A architecture introduces the ability to use 64-bit and 32-bit +Execution states, known as AArch64 and AArch32 respectively. The AArch64 +Execution state supports the A64 instruction set. It holds addresses in 64-bit +registers and allows instructions in the base instruction set to use 64-bit +registers for their processing. + +The AArch32 Execution state is a 32-bit Execution state that preserves +backwards compatibility with the Armv7-A architecture, enhancing that profile +so that it can support some features included in the AArch64 state. It supports +the T32 and A32 instruction sets. Follow the +[link](https://developer.arm.com/Architectures/A-Profile%20Architecture) +for more information. + +## Arm_AARCH64_SRE port + +This port adds support for Armv8-A architecture AArch64 execution state. +This port is generic and can be used as a starting point for Armv8-A +application processors. + +* Arm_AARCH64_SRE + * System Register interace to access Arm GIC registers diff --git a/Source/portable/GCC/ARM_CA53_64_BIT_SRE/port.c b/Source/portable/GCC/Arm_AARCH64_SRE/port.c similarity index 55% rename from Source/portable/GCC/ARM_CA53_64_BIT_SRE/port.c rename to Source/portable/GCC/Arm_AARCH64_SRE/port.c index db39a2fd6..e8ea6ad95 100644 --- a/Source/portable/GCC/ARM_CA53_64_BIT_SRE/port.c +++ b/Source/portable/GCC/Arm_AARCH64_SRE/port.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -34,92 +34,92 @@ #include "task.h" #ifndef configUNIQUE_INTERRUPT_PRIORITIES - #error configUNIQUE_INTERRUPT_PRIORITIES must be defined. See https://www.FreeRTOS.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html + #error "configUNIQUE_INTERRUPT_PRIORITIES must be defined. See www.FreeRTOS.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html" #endif #ifndef configSETUP_TICK_INTERRUPT - #error configSETUP_TICK_INTERRUPT() must be defined. See https://www.FreeRTOS.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html + #error "configSETUP_TICK_INTERRUPT() must be defined. See www.FreeRTOS.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html" #endif /* configSETUP_TICK_INTERRUPT */ #ifndef configMAX_API_CALL_INTERRUPT_PRIORITY - #error configMAX_API_CALL_INTERRUPT_PRIORITY must be defined. See https://www.FreeRTOS.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html + #error "configMAX_API_CALL_INTERRUPT_PRIORITY must be defined. See www.FreeRTOS.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html" #endif #if configMAX_API_CALL_INTERRUPT_PRIORITY == 0 - #error configMAX_API_CALL_INTERRUPT_PRIORITY must not be set to 0 + #error "configMAX_API_CALL_INTERRUPT_PRIORITY must not be set to 0" #endif #if configMAX_API_CALL_INTERRUPT_PRIORITY > configUNIQUE_INTERRUPT_PRIORITIES - #error configMAX_API_CALL_INTERRUPT_PRIORITY must be less than or equal to configUNIQUE_INTERRUPT_PRIORITIES as the lower the numeric priority value the higher the logical interrupt priority + #error "configMAX_API_CALL_INTERRUPT_PRIORITY must be less than or equal to configUNIQUE_INTERRUPT_PRIORITIES as the lower the numeric priority value the higher the logical interrupt priority" #endif #if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 /* Check the configuration. */ - #if( configMAX_PRIORITIES > 32 ) - #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice. + #if ( configMAX_PRIORITIES > 32 ) + #error "configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice." #endif #endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */ /* In case security extensions are implemented. */ #if configMAX_API_CALL_INTERRUPT_PRIORITY <= ( configUNIQUE_INTERRUPT_PRIORITIES / 2 ) - #error configMAX_API_CALL_INTERRUPT_PRIORITY must be greater than ( configUNIQUE_INTERRUPT_PRIORITIES / 2 ) + #error "configMAX_API_CALL_INTERRUPT_PRIORITY must be greater than ( configUNIQUE_INTERRUPT_PRIORITIES / 2 )" #endif /* Some vendor specific files default configCLEAR_TICK_INTERRUPT() in -portmacro.h. */ + * portmacro.h. */ #ifndef configCLEAR_TICK_INTERRUPT #define configCLEAR_TICK_INTERRUPT() #endif /* A critical section is exited when the critical section nesting count reaches -this value. */ -#define portNO_CRITICAL_NESTING ( ( size_t ) 0 ) + * this value. */ +#define portNO_CRITICAL_NESTING ( ( size_t ) 0 ) /* In all GICs 255 can be written to the priority mask register to unmask all -(but the lowest) interrupt priority. */ -#define portUNMASK_VALUE ( 0xFFUL ) + * (but the lowest) interrupt priority. */ +#define portUNMASK_VALUE ( 0xFFUL ) /* Tasks are not created with a floating point context, but can be given a -floating point context after they have been created. A variable is stored as -part of the tasks context that holds portNO_FLOATING_POINT_CONTEXT if the task -does not have an FPU context, or any other value if the task does have an FPU -context. */ -#define portNO_FLOATING_POINT_CONTEXT ( ( StackType_t ) 0 ) + * floating point context after they have been created. A variable is stored as + * part of the tasks context that holds portNO_FLOATING_POINT_CONTEXT if the task + * does not have an FPU context, or any other value if the task does have an FPU + * context. */ +#define portNO_FLOATING_POINT_CONTEXT ( ( StackType_t ) 0 ) /* Constants required to setup the initial task context. */ -#define portSP_ELx ( ( StackType_t ) 0x01 ) -#define portSP_EL0 ( ( StackType_t ) 0x00 ) +#define portSP_ELx ( ( StackType_t ) 0x01 ) +#define portSP_EL0 ( ( StackType_t ) 0x00 ) #if defined( GUEST ) - #define portEL1 ( ( StackType_t ) 0x04 ) - #define portINITIAL_PSTATE ( portEL1 | portSP_EL0 ) + #define portEL1 ( ( StackType_t ) 0x04 ) + #define portINITIAL_PSTATE ( portEL1 | portSP_EL0 ) #else - #define portEL3 ( ( StackType_t ) 0x0c ) + #define portEL3 ( ( StackType_t ) 0x0c ) /* At the time of writing, the BSP only supports EL3. */ - #define portINITIAL_PSTATE ( portEL3 | portSP_EL0 ) + #define portINITIAL_PSTATE ( portEL3 | portSP_EL0 ) #endif /* Masks all bits in the APSR other than the mode bits. */ -#define portAPSR_MODE_BITS_MASK ( 0x0C ) +#define portAPSR_MODE_BITS_MASK ( 0x0C ) /* The I bit in the DAIF bits. */ -#define portDAIF_I ( 0x80 ) +#define portDAIF_I ( 0x80 ) /* Macro to unmask all interrupt priorities. */ /* s3_0_c4_c6_0 is ICC_PMR_EL1. */ -#define portCLEAR_INTERRUPT_MASK() \ -{ \ - __asm volatile ( "MSR DAIFSET, #2 \n" \ - "DSB SY \n" \ - "ISB SY \n" \ - "MSR s3_0_c4_c6_0, %0 \n" \ - "DSB SY \n" \ - "ISB SY \n" \ - "MSR DAIFCLR, #2 \n" \ - "DSB SY \n" \ - "ISB SY \n" \ - ::"r"( portUNMASK_VALUE ) ); \ -} +#define portCLEAR_INTERRUPT_MASK() \ + { \ + __asm volatile ( "MSR DAIFSET, #2 \n" \ + "DSB SY \n" \ + "ISB SY \n" \ + "MSR s3_0_c4_c6_0, %0 \n" \ + "DSB SY \n" \ + "ISB SY \n" \ + "MSR DAIFCLR, #2 \n" \ + "DSB SY \n" \ + "ISB SY \n" \ + ::"r" ( portUNMASK_VALUE ) ); \ + } /*-----------------------------------------------------------*/ @@ -132,101 +132,103 @@ extern void vPortRestoreTaskContext( void ); /*-----------------------------------------------------------*/ /* A variable is used to keep track of the critical section nesting. This -variable has to be stored as part of the task context and must be initialised to -a non zero value to ensure interrupts don't inadvertently become unmasked before -the scheduler starts. As it is stored as part of the task context it will -automatically be set to 0 when the first task is started. */ + * variable has to be stored as part of the task context and must be initialised to + * a non zero value to ensure interrupts don't inadvertently become unmasked before + * the scheduler starts. As it is stored as part of the task context it will + * automatically be set to 0 when the first task is started. */ volatile uint64_t ullCriticalNesting = 9999ULL; /* Saved as part of the task context. If ullPortTaskHasFPUContext is non-zero -then floating point context must be saved and restored for the task. */ + * then floating point context must be saved and restored for the task. */ uint64_t ullPortTaskHasFPUContext = pdFALSE; /* Set to 1 to pend a context switch from an ISR. */ uint64_t ullPortYieldRequired = pdFALSE; /* Counts the interrupt nesting depth. A context switch is only performed if -if the nesting depth is 0. */ + * if the nesting depth is 0. */ uint64_t ullPortInterruptNesting = 0; /* Used in the ASM code. */ -__attribute__(( used )) const uint64_t ullMaxAPIPriorityMask = ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT ); +__attribute__( ( used ) ) const uint64_t ullMaxAPIPriorityMask = ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT ); /*-----------------------------------------------------------*/ /* * See header file for description. */ -StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters ) +StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, + TaskFunction_t pxCode, + void * pvParameters ) { /* Setup the initial stack of the task. The stack is set exactly as - expected by the portRESTORE_CONTEXT() macro. */ + * expected by the portRESTORE_CONTEXT() macro. */ /* First all the general purpose registers. */ pxTopOfStack--; - *pxTopOfStack = 0x0101010101010101ULL; /* R1 */ + *pxTopOfStack = 0x0101010101010101ULL; /* R1 */ pxTopOfStack--; *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */ pxTopOfStack--; - *pxTopOfStack = 0x0303030303030303ULL; /* R3 */ + *pxTopOfStack = 0x0303030303030303ULL; /* R3 */ pxTopOfStack--; - *pxTopOfStack = 0x0202020202020202ULL; /* R2 */ + *pxTopOfStack = 0x0202020202020202ULL; /* R2 */ pxTopOfStack--; - *pxTopOfStack = 0x0505050505050505ULL; /* R5 */ + *pxTopOfStack = 0x0505050505050505ULL; /* R5 */ pxTopOfStack--; - *pxTopOfStack = 0x0404040404040404ULL; /* R4 */ + *pxTopOfStack = 0x0404040404040404ULL; /* R4 */ pxTopOfStack--; - *pxTopOfStack = 0x0707070707070707ULL; /* R7 */ + *pxTopOfStack = 0x0707070707070707ULL; /* R7 */ pxTopOfStack--; - *pxTopOfStack = 0x0606060606060606ULL; /* R6 */ + *pxTopOfStack = 0x0606060606060606ULL; /* R6 */ pxTopOfStack--; - *pxTopOfStack = 0x0909090909090909ULL; /* R9 */ + *pxTopOfStack = 0x0909090909090909ULL; /* R9 */ pxTopOfStack--; - *pxTopOfStack = 0x0808080808080808ULL; /* R8 */ + *pxTopOfStack = 0x0808080808080808ULL; /* R8 */ pxTopOfStack--; - *pxTopOfStack = 0x1111111111111111ULL; /* R11 */ + *pxTopOfStack = 0x1111111111111111ULL; /* R11 */ pxTopOfStack--; - *pxTopOfStack = 0x1010101010101010ULL; /* R10 */ + *pxTopOfStack = 0x1010101010101010ULL; /* R10 */ pxTopOfStack--; - *pxTopOfStack = 0x1313131313131313ULL; /* R13 */ + *pxTopOfStack = 0x1313131313131313ULL; /* R13 */ pxTopOfStack--; - *pxTopOfStack = 0x1212121212121212ULL; /* R12 */ + *pxTopOfStack = 0x1212121212121212ULL; /* R12 */ pxTopOfStack--; - *pxTopOfStack = 0x1515151515151515ULL; /* R15 */ + *pxTopOfStack = 0x1515151515151515ULL; /* R15 */ pxTopOfStack--; - *pxTopOfStack = 0x1414141414141414ULL; /* R14 */ + *pxTopOfStack = 0x1414141414141414ULL; /* R14 */ pxTopOfStack--; - *pxTopOfStack = 0x1717171717171717ULL; /* R17 */ + *pxTopOfStack = 0x1717171717171717ULL; /* R17 */ pxTopOfStack--; - *pxTopOfStack = 0x1616161616161616ULL; /* R16 */ + *pxTopOfStack = 0x1616161616161616ULL; /* R16 */ pxTopOfStack--; - *pxTopOfStack = 0x1919191919191919ULL; /* R19 */ + *pxTopOfStack = 0x1919191919191919ULL; /* R19 */ pxTopOfStack--; - *pxTopOfStack = 0x1818181818181818ULL; /* R18 */ + *pxTopOfStack = 0x1818181818181818ULL; /* R18 */ pxTopOfStack--; - *pxTopOfStack = 0x2121212121212121ULL; /* R21 */ + *pxTopOfStack = 0x2121212121212121ULL; /* R21 */ pxTopOfStack--; - *pxTopOfStack = 0x2020202020202020ULL; /* R20 */ + *pxTopOfStack = 0x2020202020202020ULL; /* R20 */ pxTopOfStack--; - *pxTopOfStack = 0x2323232323232323ULL; /* R23 */ + *pxTopOfStack = 0x2323232323232323ULL; /* R23 */ pxTopOfStack--; - *pxTopOfStack = 0x2222222222222222ULL; /* R22 */ + *pxTopOfStack = 0x2222222222222222ULL; /* R22 */ pxTopOfStack--; - *pxTopOfStack = 0x2525252525252525ULL; /* R25 */ + *pxTopOfStack = 0x2525252525252525ULL; /* R25 */ pxTopOfStack--; - *pxTopOfStack = 0x2424242424242424ULL; /* R24 */ + *pxTopOfStack = 0x2424242424242424ULL; /* R24 */ pxTopOfStack--; - *pxTopOfStack = 0x2727272727272727ULL; /* R27 */ + *pxTopOfStack = 0x2727272727272727ULL; /* R27 */ pxTopOfStack--; - *pxTopOfStack = 0x2626262626262626ULL; /* R26 */ + *pxTopOfStack = 0x2626262626262626ULL; /* R26 */ pxTopOfStack--; - *pxTopOfStack = 0x2929292929292929ULL; /* R29 */ + *pxTopOfStack = 0x2929292929292929ULL; /* R29 */ pxTopOfStack--; - *pxTopOfStack = 0x2828282828282828ULL; /* R28 */ + *pxTopOfStack = 0x2828282828282828ULL; /* R28 */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x00; /* XZR - has no effect, used so there are an even number of registers. */ + *pxTopOfStack = ( StackType_t ) 0x00; /* XZR - has no effect, used so there are an even number of registers. */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x00; /* R30 - procedure call link register. */ + *pxTopOfStack = ( StackType_t ) 0x00; /* R30 - procedure call link register. */ pxTopOfStack--; *pxTopOfStack = portINITIAL_PSTATE; @@ -236,13 +238,13 @@ StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t px pxTopOfStack--; /* The task will start with a critical nesting count of 0 as interrupts are - enabled. */ + * enabled. */ *pxTopOfStack = portNO_CRITICAL_NESTING; pxTopOfStack--; /* The task will start without a floating point context. A task that uses - the floating point hardware must call vPortTaskUsesFPU() before executing - any floating point instructions. */ + * the floating point hardware must call vPortTaskUsesFPU() before executing + * any floating point instructions. */ *pxTopOfStack = portNO_FLOATING_POINT_CONTEXT; return pxTopOfStack; @@ -251,23 +253,26 @@ StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t px BaseType_t xPortStartScheduler( void ) { -uint32_t ulAPSR; + uint32_t ulAPSR; __asm volatile ( "MRS %0, CurrentEL" : "=r" ( ulAPSR ) ); + ulAPSR &= portAPSR_MODE_BITS_MASK; -#if defined( GUEST ) - configASSERT( ulAPSR == portEL1 ); - if( ulAPSR == portEL1 ) -#else - configASSERT( ulAPSR == portEL3 ); - if( ulAPSR == portEL3 ) -#endif + #if defined( GUEST ) + configASSERT( ulAPSR == portEL1 ); + + if( ulAPSR == portEL1 ) + #else + configASSERT( ulAPSR == portEL3 ); + + if( ulAPSR == portEL3 ) + #endif { /* Interrupts are turned off in the CPU itself to ensure a tick does - not execute while the scheduler is being started. Interrupts are - automatically turned back on in the CPU when the first task starts - executing. */ + * not execute while the scheduler is being started. Interrupts are + * automatically turned back on in the CPU when the first task starts + * executing. */ portDISABLE_INTERRUPTS(); /* Start the timer that generates the tick ISR. */ @@ -284,7 +289,7 @@ uint32_t ulAPSR; void vPortEndScheduler( void ) { /* Not implemented in ports where there is nothing to return to. - Artificially force an assert. */ + * Artificially force an assert. */ configASSERT( ullCriticalNesting == 1000ULL ); } /*-----------------------------------------------------------*/ @@ -295,15 +300,15 @@ void vPortEnterCritical( void ) uxPortSetInterruptMask(); /* Now interrupts are disabled ullCriticalNesting can be accessed - directly. Increment ullCriticalNesting to keep a count of how many times - portENTER_CRITICAL() has been called. */ + * directly. Increment ullCriticalNesting to keep a count of how many times + * portENTER_CRITICAL() has been called. */ ullCriticalNesting++; /* This is not the interrupt safe version of the enter critical function so - assert() if it is being called from an interrupt context. Only API - functions that end in "FromISR" can be used in an interrupt. Only assert if - the critical nesting count is 1 to protect against recursive calls if the - assert function also uses a critical section. */ + * assert() if it is being called from an interrupt context. Only API + * functions that end in "FromISR" can be used in an interrupt. Only assert if + * the critical nesting count is 1 to protect against recursive calls if the + * assert function also uses a critical section. */ if( ullCriticalNesting == 1ULL ) { configASSERT( ullPortInterruptNesting == 0 ); @@ -316,15 +321,15 @@ void vPortExitCritical( void ) if( ullCriticalNesting > portNO_CRITICAL_NESTING ) { /* Decrement the nesting count as the critical section is being - exited. */ + * exited. */ ullCriticalNesting--; /* If the nesting level has reached zero then all interrupt - priorities must be re-enabled. */ + * priorities must be re-enabled. */ if( ullCriticalNesting == portNO_CRITICAL_NESTING ) { /* Critical nesting has reached zero so all interrupt priorities - should be unmasked. */ + * should be unmasked. */ portCLEAR_INTERRUPT_MASK(); } } @@ -344,25 +349,25 @@ void FreeRTOS_Tick_Handler( void ) #endif /* Interrupts should not be enabled before this point. */ - #if( configASSERT_DEFINED == 1 ) + #if ( configASSERT_DEFINED == 1 ) { uint32_t ulMaskBits; - __asm volatile( "MRS %0, DAIF" : "=r"( ulMaskBits ) :: "memory" ); + __asm volatile ( "MRS %0, DAIF" : "=r" ( ulMaskBits )::"memory" ); configASSERT( ( ulMaskBits & portDAIF_I ) != 0 ); } #endif /* configASSERT_DEFINED */ /* Set interrupt mask before altering scheduler structures. The tick - handler runs at the lowest priority, so interrupts cannot already be masked, - so there is no need to save and restore the current mask value. It is - necessary to turn off interrupts in the CPU itself while the ICCPMR is being - updated. */ + * handler runs at the lowest priority, so interrupts cannot already be masked, + * so there is no need to save and restore the current mask value. It is + * necessary to turn off interrupts in the CPU itself while the ICCPMR is being + * updated. */ /* s3_0_c4_c6_0 is ICC_PMR_EL1. */ __asm volatile ( "MSR s3_0_c4_c6_0, %0 \n" "DSB SY \n" "ISB SY \n" - :: "r" ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT ) : "memory" ); + ::"r" ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT ) : "memory" ); /* Ok to enable interrupts after the interrupt source has been cleared. */ configCLEAR_TICK_INTERRUPT(); @@ -382,11 +387,11 @@ void FreeRTOS_Tick_Handler( void ) void vPortTaskUsesFPU( void ) { /* A task is registering the fact that it needs an FPU context. Set the - FPU flag (which is saved as part of the task context). */ + * FPU flag (which is saved as part of the task context). */ ullPortTaskHasFPUContext = pdTRUE; /* Consider initialising the FPSR here - but probably not necessary in - AArch64. */ + * AArch64. */ } /*-----------------------------------------------------------*/ @@ -401,14 +406,15 @@ void vPortClearInterruptMask( UBaseType_t uxNewMaskValue ) UBaseType_t uxPortSetInterruptMask( void ) { -uint32_t ulReturn; -uint64_t ullPMRValue; + uint32_t ulReturn; + uint64_t ullPMRValue; /* Interrupt in the CPU must be turned off while the ICCPMR is being - updated. */ + * updated. */ portDISABLE_INTERRUPTS(); /* s3_0_c4_c6_0 is ICC_PMR_EL1. */ __asm volatile ( "MRS %0, s3_0_c4_c6_0" : "=r" ( ullPMRValue ) ); + if( ullPMRValue == ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT ) ) { /* Interrupts were already masked. */ @@ -421,7 +427,7 @@ uint64_t ullPMRValue; __asm volatile ( "MSR s3_0_c4_c6_0, %0 \n" "DSB SY \n" "ISB SY \n" - :: "r" ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT ) : "memory" ); + ::"r" ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT ) : "memory" ); } portENABLE_INTERRUPTS(); @@ -430,27 +436,28 @@ uint64_t ullPMRValue; } /*-----------------------------------------------------------*/ -#if( configASSERT_DEFINED == 1 ) +#if ( configASSERT_DEFINED == 1 ) void vPortValidateInterruptPriority( void ) { /* The following assertion will fail if a service routine (ISR) for - an interrupt that has been assigned a priority above - configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API - function. ISR safe FreeRTOS API functions must *only* be called - from interrupts that have been assigned a priority at or below - configMAX_SYSCALL_INTERRUPT_PRIORITY. - - Numerically low interrupt priority numbers represent logically high - interrupt priorities, therefore the priority of the interrupt must - be set to a value equal to or numerically *higher* than - configMAX_SYSCALL_INTERRUPT_PRIORITY. - - FreeRTOS maintains separate thread and ISR API functions to ensure - interrupt entry is as fast and simple as possible. */ + * an interrupt that has been assigned a priority above + * configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API + * function. ISR safe FreeRTOS API functions must *only* be called + * from interrupts that have been assigned a priority at or below + * configMAX_SYSCALL_INTERRUPT_PRIORITY. + * + * Numerically low interrupt priority numbers represent logically high + * interrupt priorities, therefore the priority of the interrupt must + * be set to a value equal to or numerically *higher* than + * configMAX_SYSCALL_INTERRUPT_PRIORITY. + * + * FreeRTOS maintains separate thread and ISR API functions to ensure + * interrupt entry is as fast and simple as possible. */ uint64_t ullRunningInterruptPriority; /* s3_0_c12_c11_3 is ICC_RPR_EL1. */ __asm volatile ( "MRS %0, s3_0_c12_c11_3" : "=r" ( ullRunningInterruptPriority ) ); + configASSERT( ullRunningInterruptPriority >= ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT ) ); } diff --git a/Source/portable/GCC/ARM_CA53_64_BIT_SRE/portASM.S b/Source/portable/GCC/Arm_AARCH64_SRE/portASM.S similarity index 99% rename from Source/portable/GCC/ARM_CA53_64_BIT_SRE/portASM.S rename to Source/portable/GCC/Arm_AARCH64_SRE/portASM.S index 491a32f0a..d4b88bd06 100644 --- a/Source/portable/GCC/ARM_CA53_64_BIT_SRE/portASM.S +++ b/Source/portable/GCC/Arm_AARCH64_SRE/portASM.S @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/Source/portable/GCC/Arm_AARCH64_SRE/portmacro.h b/Source/portable/GCC/Arm_AARCH64_SRE/portmacro.h new file mode 100644 index 000000000..dbbc67787 --- /dev/null +++ b/Source/portable/GCC/Arm_AARCH64_SRE/portmacro.h @@ -0,0 +1,200 @@ +/* + * FreeRTOS Kernel V11.0.1 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef PORTMACRO_H +#define PORTMACRO_H + +/* *INDENT-OFF* */ +#ifdef __cplusplus + extern "C" { +#endif +/* *INDENT-ON* */ + +/*----------------------------------------------------------- + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the given hardware + * and compiler. + * + * These settings should not be altered. + *----------------------------------------------------------- + */ + +/* Type definitions. */ +#define portCHAR char +#define portFLOAT float +#define portDOUBLE double +#define portLONG long +#define portSHORT short +#define portSTACK_TYPE size_t +#define portBASE_TYPE long + +typedef portSTACK_TYPE StackType_t; +typedef portBASE_TYPE BaseType_t; +typedef uint64_t UBaseType_t; + +typedef uint64_t TickType_t; +#define portMAX_DELAY ( ( TickType_t ) 0xffffffffffffffff ) + +/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do + * not need to be guarded with a critical section. */ +#define portTICK_TYPE_IS_ATOMIC 1 + +/*-----------------------------------------------------------*/ + +/* Hardware specifics. */ +#define portSTACK_GROWTH ( -1 ) +#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) +#define portBYTE_ALIGNMENT 16 +#define portPOINTER_SIZE_TYPE uint64_t + +/*-----------------------------------------------------------*/ + +/* Task utilities. */ + +/* Called at the end of an ISR that can cause a context switch. */ +#define portEND_SWITCHING_ISR( xSwitchRequired ) \ + { \ + extern uint64_t ullPortYieldRequired; \ + \ + if( xSwitchRequired != pdFALSE ) \ + { \ + ullPortYieldRequired = pdTRUE; \ + } \ + } + +#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x ) +#if defined( GUEST ) + #define portYIELD() __asm volatile ( "SVC 0" ::: "memory" ) +#else + #define portYIELD() __asm volatile ( "SMC 0" ::: "memory" ) +#endif + +/*----------------------------------------------------------- +* Critical section control +*----------------------------------------------------------*/ + +extern void vPortEnterCritical( void ); +extern void vPortExitCritical( void ); +extern UBaseType_t uxPortSetInterruptMask( void ); +extern void vPortClearInterruptMask( UBaseType_t uxNewMaskValue ); +extern void vPortInstallFreeRTOSVectorTable( void ); + +#define portDISABLE_INTERRUPTS() \ + __asm volatile ( "MSR DAIFSET, #2" ::: "memory" ); \ + __asm volatile ( "DSB SY" ); \ + __asm volatile ( "ISB SY" ); + +#define portENABLE_INTERRUPTS() \ + __asm volatile ( "MSR DAIFCLR, #2" ::: "memory" ); \ + __asm volatile ( "DSB SY" ); \ + __asm volatile ( "ISB SY" ); + + +/* These macros do not globally disable/enable interrupts. They do mask off + * interrupts that have a priority below configMAX_API_CALL_INTERRUPT_PRIORITY. */ +#define portENTER_CRITICAL() vPortEnterCritical(); +#define portEXIT_CRITICAL() vPortExitCritical(); +#define portSET_INTERRUPT_MASK_FROM_ISR() uxPortSetInterruptMask() +#define portCLEAR_INTERRUPT_MASK_FROM_ISR( x ) vPortClearInterruptMask( x ) + +/*-----------------------------------------------------------*/ + +/* Task function macros as described on the FreeRTOS.org WEB site. These are + * not required for this port but included in case common demo code that uses these + * macros is used. */ +#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters ) +#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters ) + +/* Prototype of the FreeRTOS tick handler. This must be installed as the + * handler for whichever peripheral is used to generate the RTOS tick. */ +void FreeRTOS_Tick_Handler( void ); + +/* Any task that uses the floating point unit MUST call vPortTaskUsesFPU() + * before any floating point instructions are executed. */ +void vPortTaskUsesFPU( void ); +#define portTASK_USES_FLOATING_POINT() vPortTaskUsesFPU() + +#define portLOWEST_INTERRUPT_PRIORITY ( ( ( uint32_t ) configUNIQUE_INTERRUPT_PRIORITIES ) - 1UL ) +#define portLOWEST_USABLE_INTERRUPT_PRIORITY ( portLOWEST_INTERRUPT_PRIORITY - 1UL ) + +/* Architecture specific optimisations. */ +#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION + #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1 +#endif + +#if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 + +/* Store/clear the ready priorities in a bit map. */ + #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) ) + #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) ) + +/*-----------------------------------------------------------*/ + + #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31 - __builtin_clz( uxReadyPriorities ) ) + +#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */ + +#ifdef configASSERT + void vPortValidateInterruptPriority( void ); + #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() vPortValidateInterruptPriority() +#endif /* configASSERT */ + +#define portNOP() __asm volatile ( "NOP" ) +#define portINLINE __inline + +/* The number of bits to shift for an interrupt priority is dependent on the + * number of bits implemented by the interrupt controller. */ +#if configUNIQUE_INTERRUPT_PRIORITIES == 16 + #define portPRIORITY_SHIFT 4 + #define portMAX_BINARY_POINT_VALUE 3 +#elif configUNIQUE_INTERRUPT_PRIORITIES == 32 + #define portPRIORITY_SHIFT 3 + #define portMAX_BINARY_POINT_VALUE 2 +#elif configUNIQUE_INTERRUPT_PRIORITIES == 64 + #define portPRIORITY_SHIFT 2 + #define portMAX_BINARY_POINT_VALUE 1 +#elif configUNIQUE_INTERRUPT_PRIORITIES == 128 + #define portPRIORITY_SHIFT 1 + #define portMAX_BINARY_POINT_VALUE 0 +#elif configUNIQUE_INTERRUPT_PRIORITIES == 256 + #define portPRIORITY_SHIFT 0 + #define portMAX_BINARY_POINT_VALUE 0 +#else /* if configUNIQUE_INTERRUPT_PRIORITIES == 16 */ + #error Invalid configUNIQUE_INTERRUPT_PRIORITIES setting. configUNIQUE_INTERRUPT_PRIORITIES must be set to the number of unique priorities implemented by the target hardware +#endif /* if configUNIQUE_INTERRUPT_PRIORITIES == 16 */ + +#define portMEMORY_BARRIER() __asm volatile ( "" ::: "memory" ) + +/* *INDENT-OFF* */ +#ifdef __cplusplus + } +#endif +/* *INDENT-ON* */ + +#endif /* PORTMACRO_H */ diff --git a/Source/portable/GCC/CORTUS_APS3/port.c b/Source/portable/GCC/CORTUS_APS3/port.c index e1687b743..9e06adb44 100644 --- a/Source/portable/GCC/CORTUS_APS3/port.c +++ b/Source/portable/GCC/CORTUS_APS3/port.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -39,7 +39,7 @@ /*-----------------------------------------------------------*/ /* The initial PSR has the Previous Interrupt Enabled (PIEN) flag set. */ -#define portINITIAL_PSR ( 0x00020000 ) +#define portINITIAL_PSR ( 0x00020000 ) /*-----------------------------------------------------------*/ @@ -49,10 +49,12 @@ static void prvSetupTimerInterrupt( void ); /*-----------------------------------------------------------*/ -StackType_t *pxPortInitialiseStack( StackType_t * pxTopOfStack, TaskFunction_t pxCode, void *pvParameters ) +StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, + TaskFunction_t pxCode, + void * pvParameters ) { /* Make space on the stack for the context - this leaves a couple of spaces - empty. */ + * empty. */ pxTopOfStack -= 20; /* Fill the registers with known values to assist debugging. */ @@ -107,7 +109,7 @@ static void prvSetupTimerInterrupt( void ) /*-----------------------------------------------------------*/ /* Trap 31 handler. */ -void interrupt31_handler( void ) __attribute__((naked)); +void interrupt31_handler( void ) __attribute__( ( naked ) ); void interrupt31_handler( void ) { portSAVE_CONTEXT(); @@ -116,7 +118,7 @@ void interrupt31_handler( void ) } /*-----------------------------------------------------------*/ -static void prvProcessTick( void ) __attribute__((noinline)); +static void prvProcessTick( void ) __attribute__( ( noinline ) ); static void prvProcessTick( void ) { if( xTaskIncrementTick() != pdFALSE ) @@ -130,7 +132,7 @@ static void prvProcessTick( void ) /*-----------------------------------------------------------*/ /* Timer 1 interrupt handler, used for tick interrupt. */ -void interrupt7_handler( void ) __attribute__((naked)); +void interrupt7_handler( void ) __attribute__( ( naked ) ); void interrupt7_handler( void ) { portSAVE_CONTEXT(); diff --git a/Source/portable/GCC/CORTUS_APS3/portmacro.h b/Source/portable/GCC/CORTUS_APS3/portmacro.h index 4ed01c896..fdec14952 100644 --- a/Source/portable/GCC/CORTUS_APS3/portmacro.h +++ b/Source/portable/GCC/CORTUS_APS3/portmacro.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -48,36 +48,36 @@ */ /* Type definitions. */ -#define portCHAR char -#define portFLOAT float -#define portDOUBLE double -#define portLONG long -#define portSHORT short -#define portSTACK_TYPE uint32_t -#define portBASE_TYPE long - -typedef portSTACK_TYPE StackType_t; -typedef long BaseType_t; -typedef unsigned long UBaseType_t; - -#if( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS ) - typedef uint16_t TickType_t; - #define portMAX_DELAY ( TickType_t ) 0xffff +#define portCHAR char +#define portFLOAT float +#define portDOUBLE double +#define portLONG long +#define portSHORT short +#define portSTACK_TYPE uint32_t +#define portBASE_TYPE long + +typedef portSTACK_TYPE StackType_t; +typedef long BaseType_t; +typedef unsigned long UBaseType_t; + +#if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS ) + typedef uint16_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffff #elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS ) - typedef uint32_t TickType_t; - #define portMAX_DELAY ( TickType_t ) ( 0xFFFFFFFFUL ) + typedef uint32_t TickType_t; + #define portMAX_DELAY ( TickType_t ) ( 0xFFFFFFFFUL ) #else #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width. #endif /*-----------------------------------------------------------*/ /* Architecture specifics. */ -#define portSTACK_GROWTH ( -1 ) -#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) -#define portBYTE_ALIGNMENT 4 -#define portNOP() __asm__ volatile ( "mov r0, r0" ) -#define portCRITICAL_NESTING_IN_TCB 1 -#define portIRQ_TRAP_YIELD 31 +#define portSTACK_GROWTH ( -1 ) +#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) +#define portBYTE_ALIGNMENT 4 +#define portNOP() __asm__ volatile ( "mov r0, r0" ) +#define portCRITICAL_NESTING_IN_TCB 1 +#define portIRQ_TRAP_YIELD 31 /*-----------------------------------------------------------*/ /* Task utilities. */ @@ -86,13 +86,13 @@ extern void vPortYield( void ); /*---------------------------------------------------------------------------*/ -#define portYIELD() asm __volatile__( " trap #%0 "::"i"(portIRQ_TRAP_YIELD):"memory") +#define portYIELD() asm __volatile__ ( " trap #%0 " : : "i" ( portIRQ_TRAP_YIELD ) : "memory" ) /*---------------------------------------------------------------------------*/ extern void vTaskEnterCritical( void ); extern void vTaskExitCritical( void ); -#define portENTER_CRITICAL() vTaskEnterCritical() -#define portEXIT_CRITICAL() vTaskExitCritical() +#define portENTER_CRITICAL() vTaskEnterCritical() +#define portEXIT_CRITICAL() vTaskExitCritical() /*---------------------------------------------------------------------------*/ /* Critical section management. */ @@ -101,53 +101,53 @@ extern void vTaskExitCritical( void ); /*---------------------------------------------------------------------------*/ -#define portYIELD_FROM_ISR( xHigherPriorityTaskWoken ) do { if( xHigherPriorityTaskWoken != pdFALSE ) vTaskSwitchContext(); } while( 0 ) +#define portYIELD_FROM_ISR( xHigherPriorityTaskWoken ) do { if( xHigherPriorityTaskWoken != pdFALSE ) vTaskSwitchContext( ); } while( 0 ) /*---------------------------------------------------------------------------*/ -#define portSAVE_CONTEXT() \ - asm __volatile__ \ - ( \ - "sub r1, #68 \n" /* Make space on the stack for the context. */ \ - "std r2, [r1] + 0 \n" \ - "stq r4, [r1] + 8 \n" \ - "stq r8, [r1] + 24 \n" \ - "stq r12, [r1] + 40 \n" \ - "mov r6, rtt \n" \ - "mov r7, psr \n" \ - "std r6, [r1] + 56 \n" \ - "movhi r2, #16384 \n" /* Set the pointer to the IC. */ \ - "ldub r3, [r2] + 2 \n" /* Load the current interrupt mask. */ \ - "st r3, [r1]+ 64 \n" /* Store the interrupt mask on the stack. */ \ - "ld r2, [r0]+short(pxCurrentTCB) \n" /* Load the pointer to the TCB. */ \ - "st r1, [r2] \n" /* Save the stack pointer into the TCB. */ \ - "mov r14, r1 \n" /* Compiler expects r14 to be set to the function stack. */ \ +#define portSAVE_CONTEXT() \ + asm __volatile__ \ + ( \ + "sub r1, #68 \n" /* Make space on the stack for the context. */ \ + "std r2, [r1] + 0 \n" \ + "stq r4, [r1] + 8 \n" \ + "stq r8, [r1] + 24 \n" \ + "stq r12, [r1] + 40 \n" \ + "mov r6, rtt \n" \ + "mov r7, psr \n" \ + "std r6, [r1] + 56 \n" \ + "movhi r2, #16384 \n" /* Set the pointer to the IC. */ \ + "ldub r3, [r2] + 2 \n" /* Load the current interrupt mask. */ \ + "st r3, [r1]+ 64 \n" /* Store the interrupt mask on the stack. */ \ + "ld r2, [r0]+short(pxCurrentTCB) \n" /* Load the pointer to the TCB. */ \ + "st r1, [r2] \n" /* Save the stack pointer into the TCB. */ \ + "mov r14, r1 \n" /* Compiler expects r14 to be set to the function stack. */ \ ); /*---------------------------------------------------------------------------*/ -#define portRESTORE_CONTEXT() \ - asm __volatile__( \ - "ld r2, [r0]+short(pxCurrentTCB) \n" /* Load the TCB to find the stack pointer and context. */ \ - "ld r1, [r2] \n" \ - "movhi r2, #16384 \n" /* Set the pointer to the IC. */ \ - "ld r3, [r1] + 64 \n" /* Load the previous interrupt mask. */ \ - "stb r3, [r2] + 2 \n" /* Set the current interrupt mask to be the previous. */ \ - "ldd r6, [r1] + 56 \n" /* Restore context. */ \ - "mov rtt, r6 \n" \ - "mov psr, r7 \n" \ - "ldd r2, [r1] + 0 \n" \ - "ldq r4, [r1] + 8 \n" \ - "ldq r8, [r1] + 24 \n" \ - "ldq r12, [r1] + 40 \n" \ - "add r1, #68 \n" \ - "rti \n" \ - ); +#define portRESTORE_CONTEXT() \ + asm __volatile__ ( \ + "ld r2, [r0]+short(pxCurrentTCB) \n" /* Load the TCB to find the stack pointer and context. */ \ + "ld r1, [r2] \n" \ + "movhi r2, #16384 \n" /* Set the pointer to the IC. */ \ + "ld r3, [r1] + 64 \n" /* Load the previous interrupt mask. */ \ + "stb r3, [r2] + 2 \n" /* Set the current interrupt mask to be the previous. */ \ + "ldd r6, [r1] + 56 \n" /* Restore context. */ \ + "mov rtt, r6 \n" \ + "mov psr, r7 \n" \ + "ldd r2, [r1] + 0 \n" \ + "ldq r4, [r1] + 8 \n" \ + "ldq r8, [r1] + 24 \n" \ + "ldq r12, [r1] + 40 \n" \ + "add r1, #68 \n" \ + "rti \n" \ + ); /*---------------------------------------------------------------------------*/ /* Task function macros as described on the FreeRTOS.org WEB site. */ -#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters ) -#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters ) +#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters ) +#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters ) /*---------------------------------------------------------------------------*/ /* *INDENT-OFF* */ diff --git a/Source/portable/GCC/ColdFire_V2/port.c b/Source/portable/GCC/ColdFire_V2/port.c index 04afbc173..8443b3b5e 100644 --- a/Source/portable/GCC/ColdFire_V2/port.c +++ b/Source/portable/GCC/ColdFire_V2/port.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -30,23 +30,25 @@ #include "FreeRTOS.h" #include "task.h" -#define portINITIAL_FORMAT_VECTOR ( ( StackType_t ) 0x4000 ) +#define portINITIAL_FORMAT_VECTOR ( ( StackType_t ) 0x4000 ) /* Supervisor mode set. */ -#define portINITIAL_STATUS_REGISTER ( ( StackType_t ) 0x2000) +#define portINITIAL_STATUS_REGISTER ( ( StackType_t ) 0x2000 ) /* Used to keep track of the number of nested calls to taskENTER_CRITICAL(). This -will be set to 0 prior to the first task being started. */ + * will be set to 0 prior to the first task being started. */ static uint32_t ulCriticalNesting = 0x9999UL; /*-----------------------------------------------------------*/ -StackType_t *pxPortInitialiseStack( StackType_t * pxTopOfStack, TaskFunction_t pxCode, void *pvParameters ) +StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, + TaskFunction_t pxCode, + void * pvParameters ) { *pxTopOfStack = ( StackType_t ) pvParameters; pxTopOfStack--; - *pxTopOfStack = (StackType_t) 0xDEADBEEF; + *pxTopOfStack = ( StackType_t ) 0xDEADBEEF; pxTopOfStack--; /* Exception stack frame starts with the return address. */ @@ -57,7 +59,7 @@ StackType_t *pxPortInitialiseStack( StackType_t * pxTopOfStack, TaskFunction_t p pxTopOfStack--; *pxTopOfStack = ( StackType_t ) 0x0; /*FP*/ - pxTopOfStack -= 14; /* A5 to D0. */ + pxTopOfStack -= 14; /* A5 to D0. */ return pxTopOfStack; } @@ -65,7 +67,7 @@ StackType_t *pxPortInitialiseStack( StackType_t * pxTopOfStack, TaskFunction_t p BaseType_t xPortStartScheduler( void ) { -extern void vPortStartFirstTask( void ); + extern void vPortStartFirstTask( void ); ulCriticalNesting = 0UL; @@ -90,19 +92,20 @@ void vPortEnterCritical( void ) if( ulCriticalNesting == 0UL ) { /* Guard against context switches being pended simultaneously with a - critical section being entered. */ + * critical section being entered. */ do { portDISABLE_INTERRUPTS(); + if( MCF_INTC0_INTFRCL == 0UL ) { break; } portENABLE_INTERRUPTS(); - } while( 1 ); } + ulCriticalNesting++; } /*-----------------------------------------------------------*/ @@ -110,6 +113,7 @@ void vPortEnterCritical( void ) void vPortExitCritical( void ) { ulCriticalNesting--; + if( ulCriticalNesting == 0 ) { portENABLE_INTERRUPTS(); @@ -119,11 +123,11 @@ void vPortExitCritical( void ) void vPortYieldHandler( void ) { -uint32_t ulSavedInterruptMask; + uint32_t ulSavedInterruptMask; ulSavedInterruptMask = portSET_INTERRUPT_MASK_FROM_ISR(); - /* Note this will clear all forced interrupts - this is done for speed. */ - MCF_INTC0_INTFRCL = 0; - vTaskSwitchContext(); + /* Note this will clear all forced interrupts - this is done for speed. */ + MCF_INTC0_INTFRCL = 0; + vTaskSwitchContext(); portCLEAR_INTERRUPT_MASK_FROM_ISR( ulSavedInterruptMask ); } diff --git a/Source/portable/GCC/ColdFire_V2/portasm.S b/Source/portable/GCC/ColdFire_V2/portasm.S index 67c548790..a32b857f2 100644 --- a/Source/portable/GCC/ColdFire_V2/portasm.S +++ b/Source/portable/GCC/ColdFire_V2/portasm.S @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/Source/portable/GCC/ColdFire_V2/portmacro.h b/Source/portable/GCC/ColdFire_V2/portmacro.h index 9fb44ccc3..75bcf076e 100644 --- a/Source/portable/GCC/ColdFire_V2/portmacro.h +++ b/Source/portable/GCC/ColdFire_V2/portmacro.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -46,33 +46,33 @@ */ /* Type definitions. */ -#define portCHAR char -#define portFLOAT float -#define portDOUBLE double -#define portLONG long -#define portSHORT short -#define portSTACK_TYPE uint32_t -#define portBASE_TYPE long - -typedef portSTACK_TYPE StackType_t; -typedef long BaseType_t; -typedef unsigned long UBaseType_t; - -#if( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS ) - typedef uint16_t TickType_t; - #define portMAX_DELAY ( TickType_t ) 0xffff +#define portCHAR char +#define portFLOAT float +#define portDOUBLE double +#define portLONG long +#define portSHORT short +#define portSTACK_TYPE uint32_t +#define portBASE_TYPE long + +typedef portSTACK_TYPE StackType_t; +typedef long BaseType_t; +typedef unsigned long UBaseType_t; + +#if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS ) + typedef uint16_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffff #elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS ) - typedef uint32_t TickType_t; - #define portMAX_DELAY ( TickType_t ) ( 0xFFFFFFFFUL ) + typedef uint32_t TickType_t; + #define portMAX_DELAY ( TickType_t ) ( 0xFFFFFFFFUL ) #else #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width. #endif /*-----------------------------------------------------------*/ /* Hardware specifics. */ -#define portBYTE_ALIGNMENT 4 -#define portSTACK_GROWTH -1 -#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) +#define portBYTE_ALIGNMENT 4 +#define portSTACK_GROWTH -1 +#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) /*-----------------------------------------------------------*/ uint32_t ulPortSetIPL( uint32_t ); #define portDISABLE_INTERRUPTS() ulPortSetIPL( configMAX_SYSCALL_INTERRUPT_PRIORITY ) @@ -81,31 +81,43 @@ uint32_t ulPortSetIPL( uint32_t ); extern void vPortEnterCritical( void ); extern void vPortExitCritical( void ); -#define portENTER_CRITICAL() vPortEnterCritical() -#define portEXIT_CRITICAL() vPortExitCritical() +#define portENTER_CRITICAL() vPortEnterCritical() +#define portEXIT_CRITICAL() vPortExitCritical() extern UBaseType_t uxPortSetInterruptMaskFromISR( void ); extern void vPortClearInterruptMaskFromISR( UBaseType_t ); -#define portSET_INTERRUPT_MASK_FROM_ISR() ulPortSetIPL( configMAX_SYSCALL_INTERRUPT_PRIORITY ) -#define portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedStatusRegister ) ulPortSetIPL( uxSavedStatusRegister ) +#define portSET_INTERRUPT_MASK_FROM_ISR() ulPortSetIPL( configMAX_SYSCALL_INTERRUPT_PRIORITY ) +#define portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedStatusRegister ) ulPortSetIPL( uxSavedStatusRegister ) /*-----------------------------------------------------------*/ /* Task utilities. */ -#define portNOP() asm volatile ( "nop" ) +#define portNOP() asm volatile ( "nop" ) /* Note this will overwrite all other bits in the force register, it is done this way for speed. */ -#define portYIELD() MCF_INTC0_INTFRCL = ( 1UL << configYIELD_INTERRUPT_VECTOR ); portNOP(); portNOP() +#define portYIELD() MCF_INTC0_INTFRCL = ( 1UL << configYIELD_INTERRUPT_VECTOR ); portNOP(); portNOP() /*-----------------------------------------------------------*/ /* Task function macros as described on the FreeRTOS.org WEB site. */ -#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters ) __attribute__((noreturn)) -#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters ) +#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters ) __attribute__( ( noreturn ) ) +#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters ) /*-----------------------------------------------------------*/ -#define portEND_SWITCHING_ISR( xSwitchRequired ) do { if( xSwitchRequired != pdFALSE ) { portYIELD(); } } while( 0 ) +#define portEND_SWITCHING_ISR( xSwitchRequired ) \ + do \ + { \ + if( xSwitchRequired != pdFALSE ) \ + { \ + traceISR_EXIT_TO_SCHEDULER(); \ + portYIELD(); \ + } \ + else \ + { \ + traceISR_EXIT(); \ + } \ + } while( 0 ) /* *INDENT-OFF* */ diff --git a/Source/portable/GCC/H8S2329/port.c b/Source/portable/GCC/H8S2329/port.c index c897f1263..61e4e0ab2 100644 --- a/Source/portable/GCC/H8S2329/port.c +++ b/Source/portable/GCC/H8S2329/port.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -32,22 +32,22 @@ /*----------------------------------------------------------- - * Implementation of functions defined in portable.h for the H8S port. - *----------------------------------------------------------*/ +* Implementation of functions defined in portable.h for the H8S port. +*----------------------------------------------------------*/ /*-----------------------------------------------------------*/ /* When the task starts interrupts should be enabled. */ -#define portINITIAL_CCR ( ( StackType_t ) 0x00 ) +#define portINITIAL_CCR ( ( StackType_t ) 0x00 ) /* Hardware specific constants used to generate the RTOS tick from the TPU. */ -#define portCLEAR_ON_TGRA_COMPARE_MATCH ( ( uint8_t ) 0x20 ) -#define portCLOCK_DIV_64 ( ( uint8_t ) 0x03 ) -#define portCLOCK_DIV ( ( uint32_t ) 64 ) -#define portTGRA_INTERRUPT_ENABLE ( ( uint8_t ) 0x01 ) -#define portTIMER_CHANNEL ( ( uint8_t ) 0x02 ) -#define portMSTP13 ( ( uint16_t ) 0x2000 ) +#define portCLEAR_ON_TGRA_COMPARE_MATCH ( ( uint8_t ) 0x20 ) +#define portCLOCK_DIV_64 ( ( uint8_t ) 0x03 ) +#define portCLOCK_DIV ( ( uint32_t ) 64 ) +#define portTGRA_INTERRUPT_ENABLE ( ( uint8_t ) 0x01 ) +#define portTIMER_CHANNEL ( ( uint8_t ) 0x02 ) +#define portMSTP13 ( ( uint16_t ) 0x2000 ) /* * Setup TPU channel one for the RTOS tick at the requested frequency. @@ -57,26 +57,29 @@ static void prvSetupTimerInterrupt( void ); /* * The ISR used by portYIELD(). This is installed as a trap handler. */ -void vPortYield( void ) __attribute__ ( ( saveall, interrupt_handler ) ); +void vPortYield( void ) __attribute__( ( saveall, interrupt_handler ) ); /*-----------------------------------------------------------*/ /* * See header file for description. */ -StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters ) +StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, + TaskFunction_t pxCode, + void * pvParameters ) { -uint32_t ulValue; + uint32_t ulValue; /* This requires an even address. */ ulValue = ( uint32_t ) pxTopOfStack; + if( ulValue & 1UL ) { pxTopOfStack = pxTopOfStack - 1; } /* Place a few bytes of known values on the bottom of the stack. - This is just useful for debugging. */ + * This is just useful for debugging. */ pxTopOfStack--; *pxTopOfStack = 0xaa; pxTopOfStack--; @@ -87,7 +90,7 @@ uint32_t ulValue; *pxTopOfStack = 0xdd; /* The initial stack mimics an interrupt stack. First there is the program - counter (24 bits). */ + * counter (24 bits). */ ulValue = ( uint32_t ) pxCode; pxTopOfStack--; @@ -104,8 +107,8 @@ uint32_t ulValue; *pxTopOfStack = portINITIAL_CCR; /* Next all the general purpose registers - with the parameters being passed - in ER0. The parameter order must match that used by the compiler when the - "saveall" function attribute is used. */ + * in ER0. The parameter order must match that used by the compiler when the + * "saveall" function attribute is used. */ /* ER6 */ pxTopOfStack--; @@ -188,22 +191,22 @@ uint32_t ulValue; BaseType_t xPortStartScheduler( void ) { -extern void * pxCurrentTCB; + extern void * pxCurrentTCB; /* Setup the hardware to generate the tick. */ prvSetupTimerInterrupt(); /* Restore the context of the first task that is going to run. This - mirrors the function epilogue code generated by the compiler when the - "saveall" function attribute is used. */ + * mirrors the function epilogue code generated by the compiler when the + * "saveall" function attribute is used. */ asm volatile ( - "MOV.L @_pxCurrentTCB, ER6 \n\t" - "MOV.L @ER6, ER7 \n\t" - "LDM.L @SP+, (ER4-ER5) \n\t" - "LDM.L @SP+, (ER0-ER3) \n\t" - "MOV.L @ER7+, ER6 \n\t" - "RTE \n\t" - ); + "MOV.L @_pxCurrentTCB, ER6 \n\t" + "MOV.L @ER6, ER7 \n\t" + "LDM.L @SP+, (ER4-ER5) \n\t" + "LDM.L @SP+, (ER0-ER3) \n\t" + "MOV.L @ER7+, ER6 \n\t" + "RTE \n\t" + ); ( void ) pxCurrentTCB; @@ -226,7 +229,7 @@ void vPortEndScheduler( void ) void vPortYield( void ) { portSAVE_STACK_POINTER(); - vTaskSwitchContext(); + vTaskSwitchContext(); portRESTORE_STACK_POINTER(); } /*-----------------------------------------------------------*/ @@ -235,14 +238,14 @@ void vPortYield( void ) * The interrupt handler installed for the RTOS tick depends on whether the * preemptive or cooperative scheduler is being used. */ -#if( configUSE_PREEMPTION == 1 ) - - /* - * The preemptive scheduler is used so the ISR calls vTaskSwitchContext(). - * The function prologue saves the context so all we have to do is save - * the stack pointer. - */ - void vTickISR( void ) __attribute__ ( ( saveall, interrupt_handler ) ); +#if ( configUSE_PREEMPTION == 1 ) + +/* + * The preemptive scheduler is used so the ISR calls vTaskSwitchContext(). + * The function prologue saves the context so all we have to do is save + * the stack pointer. + */ + void vTickISR( void ) __attribute__( ( saveall, interrupt_handler ) ); void vTickISR( void ) { portSAVE_STACK_POINTER(); @@ -258,14 +261,14 @@ void vPortYield( void ) portRESTORE_STACK_POINTER(); } -#else +#else /* if ( configUSE_PREEMPTION == 1 ) */ - /* - * The cooperative scheduler is being used so all we have to do is - * periodically increment the tick. This can just be a normal ISR and - * the "saveall" attribute is not required. - */ - void vTickISR( void ) __attribute__ ( ( interrupt_handler ) ); +/* + * The cooperative scheduler is being used so all we have to do is + * periodically increment the tick. This can just be a normal ISR and + * the "saveall" attribute is not required. + */ + void vTickISR( void ) __attribute__( ( interrupt_handler ) ); void vTickISR( void ) { xTaskIncrementTick(); @@ -274,7 +277,7 @@ void vPortYield( void ) TSR1 &= ~0x01; } -#endif +#endif /* if ( configUSE_PREEMPTION == 1 ) */ /*-----------------------------------------------------------*/ /* @@ -282,7 +285,7 @@ void vPortYield( void ) */ static void prvSetupTimerInterrupt( void ) { -const uint32_t ulCompareMatch = ( configCPU_CLOCK_HZ / configTICK_RATE_HZ ) / portCLOCK_DIV; + const uint32_t ulCompareMatch = ( configCPU_CLOCK_HZ / configTICK_RATE_HZ ) / portCLOCK_DIV; /* Turn the module on. */ MSTPCR &= ~portMSTP13; @@ -294,7 +297,7 @@ const uint32_t ulCompareMatch = ( configCPU_CLOCK_HZ / configTICK_RATE_HZ ) / po TGR1A = ulCompareMatch; /* Start the timer and enable the interrupt - we can do this here as - interrupts are globally disabled when this function is called. */ + * interrupts are globally disabled when this function is called. */ TIER1 |= portTGRA_INTERRUPT_ENABLE; TSTR |= portTIMER_CHANNEL; } diff --git a/Source/portable/GCC/H8S2329/portmacro.h b/Source/portable/GCC/H8S2329/portmacro.h index 035265587..c9d629b8f 100644 --- a/Source/portable/GCC/H8S2329/portmacro.h +++ b/Source/portable/GCC/H8S2329/portmacro.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -47,93 +47,94 @@ */ /* Type definitions. */ -#define portCHAR char -#define portFLOAT float -#define portDOUBLE double -#define portLONG long -#define portSHORT short -#define portSTACK_TYPE uint8_t -#define portBASE_TYPE char - -typedef portSTACK_TYPE StackType_t; -typedef signed char BaseType_t; -typedef unsigned char UBaseType_t; - -#if( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS ) - typedef uint16_t TickType_t; - #define portMAX_DELAY ( TickType_t ) 0xffff +#define portCHAR char +#define portFLOAT float +#define portDOUBLE double +#define portLONG long +#define portSHORT short +#define portSTACK_TYPE uint8_t +#define portBASE_TYPE char + +typedef portSTACK_TYPE StackType_t; +typedef signed char BaseType_t; +typedef unsigned char UBaseType_t; + +#if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS ) + typedef uint16_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffff #elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS ) - typedef uint32_t TickType_t; - #define portMAX_DELAY ( TickType_t ) ( 0xFFFFFFFFUL ) + typedef uint32_t TickType_t; + #define portMAX_DELAY ( TickType_t ) ( 0xFFFFFFFFUL ) #else #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width. #endif /*-----------------------------------------------------------*/ /* Hardware specifics. */ -#define portBYTE_ALIGNMENT 2 -#define portSTACK_GROWTH ( -1 ) -#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) -#define portYIELD() asm volatile( "TRAPA #0" ) -#define portNOP() asm volatile( "NOP" ) +#define portBYTE_ALIGNMENT 2 +#define portSTACK_GROWTH ( -1 ) +#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) +#define portYIELD() asm volatile ( "TRAPA #0" ) +#define portNOP() asm volatile ( "NOP" ) /*-----------------------------------------------------------*/ /* Critical section handling. */ -#define portENABLE_INTERRUPTS() asm volatile( "ANDC #0x7F, CCR" ); -#define portDISABLE_INTERRUPTS() asm volatile( "ORC #0x80, CCR" ); +#define portENABLE_INTERRUPTS() asm volatile ( "ANDC #0x7F, CCR" ); +#define portDISABLE_INTERRUPTS() asm volatile ( "ORC #0x80, CCR" ); /* Push the CCR then disable interrupts. */ -#define portENTER_CRITICAL() asm volatile( "STC CCR, @-ER7" ); \ - portDISABLE_INTERRUPTS(); +#define portENTER_CRITICAL() \ + asm volatile ( "STC CCR, @-ER7" ); \ + portDISABLE_INTERRUPTS(); /* Pop the CCR to set the interrupt masking back to its previous state. */ -#define portEXIT_CRITICAL() asm volatile( "LDC @ER7+, CCR" ); +#define portEXIT_CRITICAL() asm volatile ( "LDC @ER7+, CCR" ); /*-----------------------------------------------------------*/ /* Task utilities. */ /* Context switch macros. These macros are very simple as the context -is saved simply by selecting the saveall attribute of the context switch -interrupt service routines. These macros save and restore the stack -pointer to the TCB. */ - -#define portSAVE_STACK_POINTER() \ -extern void* pxCurrentTCB; \ - \ - asm volatile( \ - "MOV.L @_pxCurrentTCB, ER5 \n\t" \ - "MOV.L ER7, @ER5 \n\t" \ - ); \ + * is saved simply by selecting the saveall attribute of the context switch + * interrupt service routines. These macros save and restore the stack + * pointer to the TCB. */ + +#define portSAVE_STACK_POINTER() \ + extern void * pxCurrentTCB; \ + \ + asm volatile ( \ + "MOV.L @_pxCurrentTCB, ER5 \n\t" \ + "MOV.L ER7, @ER5 \n\t" \ + ); \ ( void ) pxCurrentTCB; -#define portRESTORE_STACK_POINTER() \ -extern void* pxCurrentTCB; \ - \ - asm volatile( \ - "MOV.L @_pxCurrentTCB, ER5 \n\t" \ - "MOV.L @ER5, ER7 \n\t" \ - ); \ +#define portRESTORE_STACK_POINTER() \ + extern void * pxCurrentTCB; \ + \ + asm volatile ( \ + "MOV.L @_pxCurrentTCB, ER5 \n\t" \ + "MOV.L @ER5, ER7 \n\t" \ + ); \ ( void ) pxCurrentTCB; /*-----------------------------------------------------------*/ /* Macros to allow a context switch from within an application ISR. */ -#define portENTER_SWITCHING_ISR() portSAVE_STACK_POINTER(); { - -#define portEXIT_SWITCHING_ISR( x ) \ - if( x ) \ - { \ - extern void vTaskSwitchContext( void ); \ - vTaskSwitchContext(); \ - } \ - } portRESTORE_STACK_POINTER(); +#define portENTER_SWITCHING_ISR() portSAVE_STACK_POINTER(); { +#define portEXIT_SWITCHING_ISR( x ) \ + if( x ) \ + { \ + extern void vTaskSwitchContext( void ); \ + vTaskSwitchContext(); \ + } \ +} \ + portRESTORE_STACK_POINTER(); /*-----------------------------------------------------------*/ /* Task function macros as described on the FreeRTOS.org WEB site. */ -#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters ) -#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters ) +#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters ) +#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters ) /* *INDENT-OFF* */ #ifdef __cplusplus diff --git a/Source/portable/GCC/HCS12/port.c b/Source/portable/GCC/HCS12/port.c index 7b47eb36d..53f052b71 100644 --- a/Source/portable/GCC/HCS12/port.c +++ b/Source/portable/GCC/HCS12/port.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -36,8 +36,8 @@ #include /*----------------------------------------------------------- - * Implementation of functions defined in portable.h for the HCS12 port. - *----------------------------------------------------------*/ +* Implementation of functions defined in portable.h for the HCS12 port. +*----------------------------------------------------------*/ /* @@ -47,45 +47,45 @@ static void prvSetupTimerInterrupt( void ); /* NOTE: Interrupt service routines must be in non-banked memory - as does the -scheduler startup function. */ -#define ATTR_NEAR __attribute__((near)) + * scheduler startup function. */ +#define ATTR_NEAR __attribute__( ( near ) ) /* Manual context switch function. This is the SWI ISR. */ -// __attribute__((interrupt)) +/* __attribute__((interrupt)) */ void ATTR_NEAR vPortYield( void ); /* Tick context switch function. This is the timer ISR. */ -// __attribute__((interrupt)) +/* __attribute__((interrupt)) */ void ATTR_NEAR vPortTickInterrupt( void ); /* Function in non-banked memory which actually switches to first task. */ BaseType_t ATTR_NEAR xStartSchedulerNear( void ); /* Calls to portENTER_CRITICAL() can be nested. When they are nested the -critical section should not be left (i.e. interrupts should not be re-enabled) -until the nesting depth reaches 0. This variable simply tracks the nesting -depth. Each task maintains it's own critical nesting depth variable so -uxCriticalNesting is saved and restored from the task stack during a context -switch. */ -volatile UBaseType_t uxCriticalNesting = 0x80; // un-initialized + * critical section should not be left (i.e. interrupts should not be re-enabled) + * until the nesting depth reaches 0. This variable simply tracks the nesting + * depth. Each task maintains it's own critical nesting depth variable so + * uxCriticalNesting is saved and restored from the task stack during a context + * switch. */ +volatile UBaseType_t uxCriticalNesting = 0x80; /* un-initialized */ /*-----------------------------------------------------------*/ /* * See header file for description. */ -StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters ) +StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, + TaskFunction_t pxCode, + void * pvParameters ) { - - /* Setup the initial stack of the task. The stack is set exactly as - expected by the portRESTORE_CONTEXT() macro. In this case the stack as - expected by the HCS12 RTI instruction. */ + * expected by the portRESTORE_CONTEXT() macro. In this case the stack as + * expected by the HCS12 RTI instruction. */ /* The address of the task function is placed in the stack byte at a time. */ - *pxTopOfStack = ( StackType_t ) *( ((StackType_t *) (&pxCode) ) + 1 ); - *--pxTopOfStack = ( StackType_t ) *( ((StackType_t *) (&pxCode) ) + 0 ); + *pxTopOfStack = ( StackType_t ) *( ( ( StackType_t * ) ( &pxCode ) ) + 1 ); + *--pxTopOfStack = ( StackType_t ) *( ( ( StackType_t * ) ( &pxCode ) ) + 0 ); /* Next are all the registers that form part of the task context. */ @@ -98,32 +98,32 @@ StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t px *--pxTopOfStack = ( StackType_t ) 0xcc; /* A register contains parameter high byte. */ - *--pxTopOfStack = ( StackType_t ) *( ((StackType_t *) (&pvParameters) ) + 0 ); + *--pxTopOfStack = ( StackType_t ) *( ( ( StackType_t * ) ( &pvParameters ) ) + 0 ); /* B register contains parameter low byte. */ - *--pxTopOfStack = ( StackType_t ) *( ((StackType_t *) (&pvParameters) ) + 1 ); + *--pxTopOfStack = ( StackType_t ) *( ( ( StackType_t * ) ( &pvParameters ) ) + 1 ); /* CCR: Note that when the task starts interrupts will be enabled since - "I" bit of CCR is cleared */ - *--pxTopOfStack = ( StackType_t ) 0x80; // keeps Stop disabled (MCU default) + * "I" bit of CCR is cleared */ + *--pxTopOfStack = ( StackType_t ) 0x80; /* keeps Stop disabled (MCU default) */ /* tmp softregs used by GCC. Values right now don't matter. */ - __asm("\n\ + __asm( "\n\ movw _.frame, 2,-%0 \n\ movw _.tmp, 2,-%0 \n\ movw _.z, 2,-%0 \n\ movw _.xy, 2,-%0 \n\ ;movw _.d2, 2,-%0 \n\ ;movw _.d1, 2,-%0 \n\ - ": "=A"(pxTopOfStack) : "0"(pxTopOfStack) ); + " : "=A" ( pxTopOfStack ) : "0" ( pxTopOfStack ) ); #ifdef BANKED_MODEL /* The page of the task. */ - *--pxTopOfStack = 0x30; // can only directly start in PPAGE 0x30 + *--pxTopOfStack = 0x30; /* can only directly start in PPAGE 0x30 */ #endif /* The critical nesting depth is initialised with 0 (meaning not in - a critical section). */ + * a critical section). */ *--pxTopOfStack = ( StackType_t ) 0x00; @@ -141,21 +141,22 @@ static void prvSetupTimerInterrupt( void ) { /* Enable hardware RTI timer */ /* Ignores configTICK_RATE_HZ */ - RTICTL = 0x50; // 16 MHz xtal: 976.56 Hz, 1024mS - CRGINT |= 0x80; // RTIE + RTICTL = 0x50; /* 16 MHz xtal: 976.56 Hz, 1024mS */ + CRGINT |= 0x80; /* RTIE */ } /*-----------------------------------------------------------*/ BaseType_t xPortStartScheduler( void ) { /* xPortStartScheduler() does not start the scheduler directly because - the header file containing the xPortStartScheduler() prototype is part - of the common kernel code, and therefore cannot use the CODE_SEG pragma. - Instead it simply calls the locally defined xNearStartScheduler() - - which does use the CODE_SEG pragma. */ + * the header file containing the xPortStartScheduler() prototype is part + * of the common kernel code, and therefore cannot use the CODE_SEG pragma. + * Instead it simply calls the locally defined xNearStartScheduler() - + * which does use the CODE_SEG pragma. */ int16_t register d; - __asm ("jmp xStartSchedulerNear ; will never return": "=d"(d)); + + __asm( "jmp xStartSchedulerNear ; will never return" : "=d" ( d ) ); return d; } /*-----------------------------------------------------------*/ @@ -163,7 +164,7 @@ BaseType_t xPortStartScheduler( void ) BaseType_t xStartSchedulerNear( void ) { /* Configure the timer that will generate the RTOS tick. Interrupts are - disabled when this function is called. */ + * disabled when this function is called. */ prvSetupTimerInterrupt(); /* Restore the context of the first task. */ @@ -187,9 +188,10 @@ BaseType_t xStartSchedulerNear( void ) void vPortYield( void ) { portISR_HEAD(); + /* NOTE: This is the trap routine (swi) although not defined as a trap. - It will fill the stack the same way as an ISR in order to mix preemtion - and cooperative yield. */ + * It will fill the stack the same way as an ISR in order to mix preemtion + * and cooperative yield. */ portSAVE_CONTEXT(); vTaskSwitchContext(); @@ -224,14 +226,14 @@ void vPortTickInterrupt( void ) } /* Restore the context of a task - which may be a different task - to that interrupted. */ + * to that interrupted. */ portRESTORE_CONTEXT(); } - #else + #else /* if configUSE_PREEMPTION == 1 */ { xTaskIncrementTick(); } - #endif + #endif /* if configUSE_PREEMPTION == 1 */ portISR_TAIL(); } diff --git a/Source/portable/GCC/HCS12/portmacro.h b/Source/portable/GCC/HCS12/portmacro.h index a732f4cda..de6b002e8 100644 --- a/Source/portable/GCC/HCS12/portmacro.h +++ b/Source/portable/GCC/HCS12/portmacro.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -47,40 +47,40 @@ */ /* Type definitions. */ -#define portCHAR char -#define portFLOAT float -#define portDOUBLE double -#define portLONG long -#define portSHORT short -#define portSTACK_TYPE uint8_t -#define portBASE_TYPE char - -typedef portSTACK_TYPE StackType_t; -typedef signed char BaseType_t; -typedef unsigned char UBaseType_t; - - -#if( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS ) - typedef uint16_t TickType_t; - #define portMAX_DELAY ( TickType_t ) 0xffff +#define portCHAR char +#define portFLOAT float +#define portDOUBLE double +#define portLONG long +#define portSHORT short +#define portSTACK_TYPE uint8_t +#define portBASE_TYPE char + +typedef portSTACK_TYPE StackType_t; +typedef signed char BaseType_t; +typedef unsigned char UBaseType_t; + + +#if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS ) + typedef uint16_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffff #elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS ) - typedef uint32_t TickType_t; - #define portMAX_DELAY ( TickType_t ) ( 0xFFFFFFFFUL ) + typedef uint32_t TickType_t; + #define portMAX_DELAY ( TickType_t ) ( 0xFFFFFFFFUL ) #else #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width. #endif /*-----------------------------------------------------------*/ /* Hardware specifics. */ -#define portBYTE_ALIGNMENT 1 -#define portSTACK_GROWTH ( -1 ) -#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) -#define portYIELD() __asm( "swi" ); +#define portBYTE_ALIGNMENT 1 +#define portSTACK_GROWTH ( -1 ) +#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) +#define portYIELD() __asm( "swi" ); /*-----------------------------------------------------------*/ /* Critical section handling. */ -#define portENABLE_INTERRUPTS() __asm( "cli" ) -#define portDISABLE_INTERRUPTS() __asm( "sei" ) +#define portENABLE_INTERRUPTS() __asm( "cli" ) +#define portDISABLE_INTERRUPTS() __asm( "sei" ) /* * Disable interrupts before incrementing the count of critical section nesting. @@ -88,29 +88,29 @@ typedef unsigned char UBaseType_t; * re-enabled. Once interrupts are disabled the nesting count can be accessed * directly. Each task maintains its own nesting count. */ -#define portENTER_CRITICAL() \ -{ \ - extern volatile UBaseType_t uxCriticalNesting; \ - \ - portDISABLE_INTERRUPTS(); \ - uxCriticalNesting++; \ -} +#define portENTER_CRITICAL() \ + { \ + extern volatile UBaseType_t uxCriticalNesting; \ + \ + portDISABLE_INTERRUPTS(); \ + uxCriticalNesting++; \ + } /* * Interrupts are disabled so we can access the nesting count directly. If the * nesting is found to be 0 (no nesting) then we are leaving the critical * section and interrupts can be re-enabled. */ -#define portEXIT_CRITICAL() \ -{ \ - extern volatile UBaseType_t uxCriticalNesting; \ - \ - uxCriticalNesting--; \ - if( uxCriticalNesting == 0 ) \ - { \ - portENABLE_INTERRUPTS(); \ - } \ -} +#define portEXIT_CRITICAL() \ + { \ + extern volatile UBaseType_t uxCriticalNesting; \ + \ + uxCriticalNesting--; \ + if( uxCriticalNesting == 0 ) \ + { \ + portENABLE_INTERRUPTS(); \ + } \ + } /*-----------------------------------------------------------*/ /* Task utilities. */ @@ -126,13 +126,14 @@ typedef unsigned char UBaseType_t; */ #ifdef BANKED_MODEL - /* - * Load the stack pointer for the task, then pull the critical nesting - * count and PPAGE register from the stack. The remains of the - * context are restored by the RTI instruction. - */ - #define portRESTORE_CONTEXT() \ - { \ + +/* + * Load the stack pointer for the task, then pull the critical nesting + * count and PPAGE register from the stack. The remains of the + * context are restored by the RTI instruction. + */ + #define portRESTORE_CONTEXT() \ + { \ __asm( " \n\ .globl pxCurrentTCB ; void * \n\ .globl uxCriticalNesting ; char \n\ @@ -142,16 +143,16 @@ typedef unsigned char UBaseType_t; \n\ movb 1,sp+,uxCriticalNesting \n\ movb 1,sp+,0x30 ; PPAGE \n\ - " ); \ + " ); \ } - /* - * By the time this macro is called the processor has already stacked the - * registers. Simply stack the nesting count and PPAGE value, then save - * the task stack pointer. - */ - #define portSAVE_CONTEXT() \ - { \ +/* + * By the time this macro is called the processor has already stacked the + * registers. Simply stack the nesting count and PPAGE value, then save + * the task stack pointer. + */ + #define portSAVE_CONTEXT() \ + { \ __asm( " \n\ .globl pxCurrentTCB ; void * \n\ .globl uxCriticalNesting ; char \n\ @@ -161,17 +162,17 @@ typedef unsigned char UBaseType_t; \n\ ldx pxCurrentTCB \n\ sts 0,x ; Stack \n\ - " ); \ + " ); \ } -#else +#else /* ifdef BANKED_MODEL */ - /* - * These macros are as per the BANKED versions above, but without saving - * and restoring the PPAGE register. - */ +/* + * These macros are as per the BANKED versions above, but without saving + * and restoring the PPAGE register. + */ - #define portRESTORE_CONTEXT() \ - { \ + #define portRESTORE_CONTEXT() \ + { \ __asm( " \n\ .globl pxCurrentTCB ; void * \n\ .globl uxCriticalNesting ; char \n\ @@ -180,11 +181,11 @@ typedef unsigned char UBaseType_t; lds 0,x ; Stack \n\ \n\ movb 1,sp+,uxCriticalNesting \n\ - " ); \ + " ); \ } - #define portSAVE_CONTEXT() \ - { \ + #define portSAVE_CONTEXT() \ + { \ __asm( " \n\ .globl pxCurrentTCB ; void * \n\ .globl uxCriticalNesting ; char \n\ @@ -193,29 +194,29 @@ typedef unsigned char UBaseType_t; \n\ ldx pxCurrentTCB \n\ sts 0,x ; Stack \n\ - " ); \ + " ); \ } -#endif +#endif /* ifdef BANKED_MODEL */ /* * Utility macros to save/restore correct software registers for GCC. This is * useful when GCC does not generate appropriate ISR head/tail code. */ -#define portISR_HEAD() \ -{ \ - __asm(" \n\ +#define portISR_HEAD() \ + { \ + __asm( " \n\ movw _.frame, 2,-sp \n\ movw _.tmp, 2,-sp \n\ movw _.z, 2,-sp \n\ movw _.xy, 2,-sp \n\ ;movw _.d2, 2,-sp \n\ ;movw _.d1, 2,-sp \n\ - "); \ -} + " ); \ + } -#define portISR_TAIL() \ -{ \ - __asm(" \n\ +#define portISR_TAIL() \ + { \ + __asm( " \n\ movw 2,sp+, _.xy \n\ movw 2,sp+, _.z \n\ movw 2,sp+, _.tmp \n\ @@ -223,8 +224,8 @@ typedef unsigned char UBaseType_t; ;movw 2,sp+, _.d1 \n\ ;movw 2,sp+, _.d2 \n\ rti \n\ - "); \ -} + " ); \ + } /* * Utility macro to call macros above in correct order in order to perform a @@ -233,15 +234,15 @@ typedef unsigned char UBaseType_t; * variables portYIELD() should be used in it's place. */ -#define portTASK_SWITCH_FROM_ISR() \ - portSAVE_CONTEXT(); \ - vTaskSwitchContext(); \ +#define portTASK_SWITCH_FROM_ISR() \ + portSAVE_CONTEXT(); \ + vTaskSwitchContext(); \ portRESTORE_CONTEXT(); /* Task function macros as described on the FreeRTOS.org WEB site. */ -#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters ) -#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters ) +#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters ) +#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters ) /* *INDENT-OFF* */ #ifdef __cplusplus diff --git a/Source/portable/GCC/IA32_flat/ISR_Support.h b/Source/portable/GCC/IA32_flat/ISR_Support.h index 76e2e5513..744d87b25 100644 --- a/Source/portable/GCC/IA32_flat/ISR_Support.h +++ b/Source/portable/GCC/IA32_flat/ISR_Support.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -26,103 +26,106 @@ * */ - .extern ulTopOfSystemStack - .extern ulInterruptNesting +.extern ulTopOfSystemStack + .extern ulInterruptNesting /*-----------------------------------------------------------*/ -.macro portFREERTOS_INTERRUPT_ENTRY + .macro portFREERTOS_INTERRUPT_ENTRY - /* Save general purpose registers. */ - pusha +/* Save general purpose registers. */ +pusha - /* If ulInterruptNesting is zero the rest of the task context will need - saving and a stack switch might be required. */ - movl ulInterruptNesting, %eax - test %eax, %eax - jne 2f +/* If ulInterruptNesting is zero the rest of the task context will need + * saving and a stack switch might be required. */ +movl ulInterruptNesting, % eax +test % eax, % eax +jne 2f - /* Interrupts are not nested, so save the rest of the task context. */ - .if configSUPPORT_FPU == 1 +/* Interrupts are not nested, so save the rest of the task context. */ + . - /* If the task has a buffer allocated to save the FPU context then - save the FPU context now. */ - movl pucPortTaskFPUContextBuffer, %eax - test %eax, %eax - je 1f - fnsave ( %eax ) /* Save FLOP context into ucTempFPUBuffer array. */ - fwait + if configSUPPORT_FPU == 1 - 1: - /* Save the address of the FPU context, if any. */ - push pucPortTaskFPUContextBuffer +/* If the task has a buffer allocated to save the FPU context then + * save the FPU context now. */ +movl pucPortTaskFPUContextBuffer, % eax +test % eax, % eax +je 1f +fnsave( % eax ) /* Save FLOP context into ucTempFPUBuffer array. */ +fwait - .endif /* configSUPPORT_FPU */ +1 : +/* Save the address of the FPU context, if any. */ +push pucPortTaskFPUContextBuffer - /* Find the TCB. */ - movl pxCurrentTCB, %eax + .endif /* configSUPPORT_FPU */ - /* Stack location is first item in the TCB. */ - movl %esp, (%eax) +/* Find the TCB. */ +movl pxCurrentTCB, % eax - /* Switch stacks. */ - movl ulTopOfSystemStack, %esp - movl %esp, %ebp +/* Stack location is first item in the TCB. */ + movl % esp, ( % eax ) - 2: - /* Increment nesting count. */ - add $1, ulInterruptNesting +/* Switch stacks. */ +movl ulTopOfSystemStack, % esp +movl % esp, % ebp -.endm +2 : +/* Increment nesting count. */ +add $1, ulInterruptNesting + + .endm /*-----------------------------------------------------------*/ -.macro portINTERRUPT_EPILOGUE + .macro portINTERRUPT_EPILOGUE + +cli +sub $1, ulInterruptNesting - cli - sub $1, ulInterruptNesting +/* If the nesting has unwound to zero. */ +movl ulInterruptNesting, % eax + test % eax, % eax + jne 2f - /* If the nesting has unwound to zero. */ - movl ulInterruptNesting, %eax - test %eax, %eax - jne 2f +/* If a yield was requested then select a new TCB now. */ +movl ulPortYieldPending, % eax + test % eax, % eax + je 1f +movl $0, ulPortYieldPending +call vTaskSwitchContext - /* If a yield was requested then select a new TCB now. */ - movl ulPortYieldPending, %eax - test %eax, %eax - je 1f - movl $0, ulPortYieldPending - call vTaskSwitchContext +1 : +/* Stack location is first item in the TCB. */ +movl pxCurrentTCB, % eax movl( % eax ), % esp - 1: - /* Stack location is first item in the TCB. */ - movl pxCurrentTCB, %eax - movl (%eax), %esp + . - .if configSUPPORT_FPU == 1 + if configSUPPORT_FPU == 1 - /* Restore address of task's FPU context buffer. */ - pop pucPortTaskFPUContextBuffer +/* Restore address of task's FPU context buffer. */ +pop pucPortTaskFPUContextBuffer - /* If the task has a buffer allocated in which its FPU context is saved, - then restore it now. */ - movl pucPortTaskFPUContextBuffer, %eax - test %eax, %eax - je 1f - frstor ( %eax ) - 1: - .endif +/* If the task has a buffer allocated in which its FPU context is saved, + * then restore it now. */ +movl pucPortTaskFPUContextBuffer, % eax +test % eax, % eax +je 1f +frstor( % eax ) +1 : +.endif - 2: - popa +2 : +popa -.endm + .endm /*-----------------------------------------------------------*/ -.macro portFREERTOS_INTERRUPT_EXIT + .macro portFREERTOS_INTERRUPT_EXIT - portINTERRUPT_EPILOGUE - /* EOI. */ - movl $0x00, (0xFEE000B0) - iret +portINTERRUPT_EPILOGUE +/* EOI. */ +movl $0x00, ( 0xFEE000B0 ) +iret -.endm + .endm diff --git a/Source/portable/GCC/IA32_flat/port.c b/Source/portable/GCC/IA32_flat/port.c index 8ecb60efc..84f9eb1e8 100644 --- a/Source/portable/GCC/IA32_flat/port.c +++ b/Source/portable/GCC/IA32_flat/port.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -35,60 +35,60 @@ #if ( configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 ) /* Check the configuration. */ - #if( configMAX_PRIORITIES > 32 ) + #if ( configMAX_PRIORITIES > 32 ) #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice. #endif #endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */ -#if( configISR_STACK_SIZE < ( configMINIMAL_STACK_SIZE * 2 ) ) +#if ( configISR_STACK_SIZE < ( configMINIMAL_STACK_SIZE * 2 ) ) #warning configISR_STACK_SIZE is probably too small! #endif /* ( configISR_STACK_SIZE < configMINIMAL_STACK_SIZE * 2 ) */ -#if( ( configMAX_API_CALL_INTERRUPT_PRIORITY > portMAX_PRIORITY ) || ( configMAX_API_CALL_INTERRUPT_PRIORITY < 2 ) ) +#if ( ( configMAX_API_CALL_INTERRUPT_PRIORITY > portMAX_PRIORITY ) || ( configMAX_API_CALL_INTERRUPT_PRIORITY < 2 ) ) #error configMAX_API_CALL_INTERRUPT_PRIORITY must be between 2 and 15 #endif -#if( ( configSUPPORT_FPU == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 0 ) ) +#if ( ( configSUPPORT_FPU == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 0 ) ) #error configSUPPORT_DYNAMIC_ALLOCATION must be set to 1 to use this port with an FPU #endif /* A critical section is exited when the critical section nesting count reaches -this value. */ -#define portNO_CRITICAL_NESTING ( ( uint32_t ) 0 ) + * this value. */ +#define portNO_CRITICAL_NESTING ( ( uint32_t ) 0 ) /* Tasks are not created with a floating point context, but can be given a -floating point context after they have been created. A variable is stored as -part of the tasks context that holds portNO_FLOATING_POINT_CONTEXT if the task -does not have an FPU context, or any other value if the task does have an FPU -context. */ -#define portNO_FLOATING_POINT_CONTEXT ( ( StackType_t ) 0 ) + * floating point context after they have been created. A variable is stored as + * part of the tasks context that holds portNO_FLOATING_POINT_CONTEXT if the task + * does not have an FPU context, or any other value if the task does have an FPU + * context. */ +#define portNO_FLOATING_POINT_CONTEXT ( ( StackType_t ) 0 ) /* Only the IF bit is set so tasks start with interrupts enabled. */ -#define portINITIAL_EFLAGS ( 0x200UL ) +#define portINITIAL_EFLAGS ( 0x200UL ) /* Error interrupts are at the highest priority vectors. */ -#define portAPIC_LVT_ERROR_VECTOR ( 0xfe ) -#define portAPIC_SPURIOUS_INT_VECTOR ( 0xff ) +#define portAPIC_LVT_ERROR_VECTOR ( 0xfe ) +#define portAPIC_SPURIOUS_INT_VECTOR ( 0xff ) /* EFLAGS bits. */ -#define portEFLAGS_IF ( 0x200UL ) +#define portEFLAGS_IF ( 0x200UL ) /* FPU context size if FSAVE is used. */ -#define portFPU_CONTEXT_SIZE_BYTES 108 +#define portFPU_CONTEXT_SIZE_BYTES 108 /* The expected size of each entry in the IDT. Used to check structure packing - is set correctly. */ -#define portEXPECTED_IDT_ENTRY_SIZE 8 + * is set correctly. */ +#define portEXPECTED_IDT_ENTRY_SIZE 8 /* Default flags setting for entries in the IDT. */ -#define portIDT_FLAGS ( 0x8E ) +#define portIDT_FLAGS ( 0x8E ) /* This is the lowest possible ISR vector available to application code. */ -#define portAPIC_MIN_ALLOWABLE_VECTOR ( 0x20 ) +#define portAPIC_MIN_ALLOWABLE_VECTOR ( 0x20 ) /* If configASSERT() is defined then the system stack is filled with this value -to allow for a crude stack overflow check. */ -#define portSTACK_WORD ( 0xecececec ) + * to allow for a crude stack overflow check. */ +#define portSTACK_WORD ( 0xecececec ) /*-----------------------------------------------------------*/ /* @@ -104,7 +104,9 @@ static void prvTaskExitError( void ); /* * Complete one descriptor in the IDT. */ -static void prvSetInterruptGate( uint8_t ucNumber, ISR_Handler_t pxHandlerFunction, uint8_t ucFlags ); +static void prvSetInterruptGate( uint8_t ucNumber, + ISR_Handler_t pxHandlerFunction, + uint8_t ucFlags ); /* * The default handler installed in each IDT position. @@ -135,78 +137,82 @@ static BaseType_t prvCheckValidityOfVectorNumber( uint32_t ulVectorNumber ); /*-----------------------------------------------------------*/ /* A variable is used to keep track of the critical section nesting. This -variable must be initialised to a non zero value to ensure interrupts don't -inadvertently become unmasked before the scheduler starts. It is set to zero -before the first task starts executing. */ + * variable must be initialised to a non zero value to ensure interrupts don't + * inadvertently become unmasked before the scheduler starts. It is set to zero + * before the first task starts executing. */ volatile uint32_t ulCriticalNesting = 9999UL; /* A structure used to map the various fields of an IDT entry into separate -structure members. */ + * structure members. */ struct IDTEntry { - uint16_t usISRLow; /* Low 16 bits of handler address. */ - uint16_t usSegmentSelector; /* Flat model means this is not changed. */ - uint8_t ucZero; /* Must be set to zero. */ - uint8_t ucFlags; /* Flags for this entry. */ - uint16_t usISRHigh; /* High 16 bits of handler address. */ -} __attribute__( ( packed ) ); + uint16_t usISRLow; /* Low 16 bits of handler address. */ + uint16_t usSegmentSelector; /* Flat model means this is not changed. */ + uint8_t ucZero; /* Must be set to zero. */ + uint8_t ucFlags; /* Flags for this entry. */ + uint16_t usISRHigh; /* High 16 bits of handler address. */ +} +__attribute__( ( packed ) ); typedef struct IDTEntry IDTEntry_t; /* Use to pass the location of the IDT to the CPU. */ struct IDTPointer { - uint16_t usTableLimit; - uint32_t ulTableBase; /* The address of the first entry in xInterruptDescriptorTable. */ -} __attribute__( ( __packed__ ) ); + uint16_t usTableLimit; + uint32_t ulTableBase; /* The address of the first entry in xInterruptDescriptorTable. */ +} +__attribute__( ( __packed__ ) ); typedef struct IDTPointer IDTPointer_t; /* The IDT itself. */ -static __attribute__ ( ( aligned( 32 ) ) ) IDTEntry_t xInterruptDescriptorTable[ portNUM_VECTORS ]; +static __attribute__( ( aligned( 32 ) ) ) IDTEntry_t xInterruptDescriptorTable[ portNUM_VECTORS ]; #if ( configUSE_COMMON_INTERRUPT_ENTRY_POINT == 1 ) - /* A table in which application defined interrupt handlers are stored. These - are called by the central interrupt handler if a common interrupt entry - point it used. */ - static ISR_Handler_t xInterruptHandlerTable[ portNUM_VECTORS ] = { NULL }; +/* A table in which application defined interrupt handlers are stored. These + * are called by the central interrupt handler if a common interrupt entry + * point it used. */ +static ISR_Handler_t xInterruptHandlerTable[ portNUM_VECTORS ] = { NULL }; #endif /* configUSE_COMMON_INTERRUPT_ENTRY_POINT */ #if ( configSUPPORT_FPU == 1 ) - /* Saved as part of the task context. If pucPortTaskFPUContextBuffer is NULL - then the task does not have an FPU context. If pucPortTaskFPUContextBuffer is - not NULL then it points to a buffer into which the FPU context can be saved. */ - uint8_t *pucPortTaskFPUContextBuffer __attribute__((used)) = pdFALSE; +/* Saved as part of the task context. If pucPortTaskFPUContextBuffer is NULL + * then the task does not have an FPU context. If pucPortTaskFPUContextBuffer is + * not NULL then it points to a buffer into which the FPU context can be saved. */ + uint8_t * pucPortTaskFPUContextBuffer __attribute__( ( used ) ) = pdFALSE; #endif /* configSUPPORT_FPU */ /* The stack used by interrupt handlers. */ -static uint32_t ulSystemStack[ configISR_STACK_SIZE ] __attribute__((used)) = { 0 }; +static uint32_t ulSystemStack[ configISR_STACK_SIZE ] __attribute__( ( used ) ) = { 0 }; /* Don't use the very top of the system stack so the return address -appears as 0 if the debugger tries to unwind the stack. */ -volatile uint32_t ulTopOfSystemStack __attribute__((used)) = ( uint32_t ) &( ulSystemStack[ configISR_STACK_SIZE - 5 ] ); + * appears as 0 if the debugger tries to unwind the stack. */ +volatile uint32_t ulTopOfSystemStack __attribute__( ( used ) ) = ( uint32_t ) &( ulSystemStack[ configISR_STACK_SIZE - 5 ] ); /* If a yield is requested from an interrupt or from a critical section then -the yield is not performed immediately, and ulPortYieldPending is set to pdTRUE -instead to indicate the yield should be performed at the end of the interrupt -when the critical section is exited. */ -volatile uint32_t ulPortYieldPending __attribute__((used)) = pdFALSE; + * the yield is not performed immediately, and ulPortYieldPending is set to pdTRUE + * instead to indicate the yield should be performed at the end of the interrupt + * when the critical section is exited. */ +volatile uint32_t ulPortYieldPending __attribute__( ( used ) ) = pdFALSE; /* Counts the interrupt nesting depth. Used to know when to switch to the -interrupt/system stack and when to save/restore a complete context. */ -volatile uint32_t ulInterruptNesting __attribute__((used)) = 0; + * interrupt/system stack and when to save/restore a complete context. */ +volatile uint32_t ulInterruptNesting __attribute__( ( used ) ) = 0; /*-----------------------------------------------------------*/ /* * See header file for description. */ -StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters ) +StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, + TaskFunction_t pxCode, + void * pvParameters ) { -uint32_t ulCodeSegment; + uint32_t ulCodeSegment; /* Setup the initial stack as expected by the portFREERTOS_INTERRUPT_EXIT macro. */ @@ -220,7 +226,7 @@ uint32_t ulCodeSegment; pxTopOfStack--; /* There is nothing to return to so assert if attempting to use the return - address. */ + * address. */ *pxTopOfStack = ( StackType_t ) prvTaskExitError; pxTopOfStack--; @@ -229,7 +235,7 @@ uint32_t ulCodeSegment; pxTopOfStack--; /* CS */ - __asm volatile( "movl %%cs, %0" : "=r" ( ulCodeSegment ) ); + __asm volatile ( "movl %%cs, %0" : "=r" ( ulCodeSegment ) ); *pxTopOfStack = ulCodeSegment; pxTopOfStack--; @@ -266,7 +272,7 @@ uint32_t ulCodeSegment; pxTopOfStack--; /* Buffer for FPU context, which is initialised to NULL as tasks are not - created with an FPU context. */ + * created with an FPU context. */ *pxTopOfStack = portNO_FLOATING_POINT_CONTEXT; } #endif /* configSUPPORT_FPU */ @@ -275,16 +281,18 @@ uint32_t ulCodeSegment; } /*-----------------------------------------------------------*/ -static void prvSetInterruptGate( uint8_t ucNumber, ISR_Handler_t pxHandlerFunction, uint8_t ucFlags ) +static void prvSetInterruptGate( uint8_t ucNumber, + ISR_Handler_t pxHandlerFunction, + uint8_t ucFlags ) { -uint16_t usCodeSegment; -uint32_t ulBase = ( uint32_t ) pxHandlerFunction; + uint16_t usCodeSegment; + uint32_t ulBase = ( uint32_t ) pxHandlerFunction; xInterruptDescriptorTable[ ucNumber ].usISRLow = ( uint16_t ) ( ulBase & USHRT_MAX ); xInterruptDescriptorTable[ ucNumber ].usISRHigh = ( uint16_t ) ( ( ulBase >> 16UL ) & USHRT_MAX ); /* When the flat model is used the CS will never change. */ - __asm volatile( "mov %%cs, %0" : "=r" ( usCodeSegment ) ); + __asm volatile ( "mov %%cs, %0" : "=r" ( usCodeSegment ) ); xInterruptDescriptorTable[ ucNumber ].usSegmentSelector = usCodeSegment; xInterruptDescriptorTable[ ucNumber ].ucZero = 0; xInterruptDescriptorTable[ ucNumber ].ucFlags = ucFlags; @@ -293,8 +301,8 @@ uint32_t ulBase = ( uint32_t ) pxHandlerFunction; void vPortSetupIDT( void ) { -uint32_t ulNum; -IDTPointer_t xIDT; + uint32_t ulNum; + IDTPointer_t xIDT; #if ( configUSE_COMMON_INTERRUPT_ENTRY_POINT == 1 ) { @@ -314,28 +322,31 @@ IDTPointer_t xIDT; xIDT.usTableLimit = sizeof( xInterruptDescriptorTable ) - 1; /* Set IDT in CPU. */ - __asm volatile( "lidt %0" :: "m" (xIDT) ); + __asm volatile ( "lidt %0" ::"m" ( xIDT ) ); } /*-----------------------------------------------------------*/ static void prvTaskExitError( void ) { /* A function that implements a task must not exit or attempt to return to - its caller as there is nothing to return to. If a task wants to exit it - should instead call vTaskDelete( NULL ). - - Artificially force an assert() to be triggered if configASSERT() is - defined, then stop here so application writers can catch the error. */ + * its caller as there is nothing to return to. If a task wants to exit it + * should instead call vTaskDelete( NULL ). + * + * Artificially force an assert() to be triggered if configASSERT() is + * defined, then stop here so application writers can catch the error. */ configASSERT( ulCriticalNesting == ~0UL ); portDISABLE_INTERRUPTS(); - for( ;; ); + + for( ; ; ) + { + } } /*-----------------------------------------------------------*/ static void prvSetupTimerInterrupt( void ) { -extern void vPortAPICErrorHandlerWrapper( void ); -extern void vPortAPICSpuriousHandler( void ); + extern void vPortAPICErrorHandlerWrapper( void ); + extern void vPortAPICSpuriousHandler( void ); /* Initialise LAPIC to a well known state. */ portAPIC_LDR = 0xFFFFFFFF; @@ -372,15 +383,15 @@ extern void vPortAPICSpuriousHandler( void ); BaseType_t xPortStartScheduler( void ) { -BaseType_t xWord; + BaseType_t xWord; /* Some versions of GCC require the -mno-ms-bitfields command line option - for packing to work. */ + * for packing to work. */ configASSERT( sizeof( struct IDTEntry ) == portEXPECTED_IDT_ENTRY_SIZE ); /* Fill part of the system stack with a known value to help detect stack - overflow. A few zeros are left so GDB doesn't get confused unwinding - the stack. */ + * overflow. A few zeros are left so GDB doesn't get confused unwinding + * the stack. */ for( xWord = 0; xWord < configISR_STACK_SIZE - 20; xWord++ ) { ulSystemStack[ xWord ] = portSTACK_WORD; @@ -404,7 +415,7 @@ BaseType_t xWord; portAPIC_TMRDIV = portAPIC_DIV_16; /* Should not return from the following function as the scheduler will then - be executing the tasks. */ + * be executing the tasks. */ vPortStartFirstTask(); return 0; @@ -414,7 +425,7 @@ BaseType_t xWord; void vPortEndScheduler( void ) { /* Not implemented in ports where there is nothing to return to. - Artificially force an assert. */ + * Artificially force an assert. */ configASSERT( ulCriticalNesting == 1000UL ); } /*-----------------------------------------------------------*/ @@ -423,9 +434,9 @@ void vPortEnterCritical( void ) { if( ulCriticalNesting == 0 ) { - #if( configMAX_API_CALL_INTERRUPT_PRIORITY == portMAX_PRIORITY ) + #if ( configMAX_API_CALL_INTERRUPT_PRIORITY == portMAX_PRIORITY ) { - __asm volatile( "cli" ); + __asm volatile ( "cli" ); } #else { @@ -435,9 +446,9 @@ void vPortEnterCritical( void ) #endif } - /* Now interrupts are disabled ulCriticalNesting can be accessed - directly. Increment ulCriticalNesting to keep a count of how many times - portENTER_CRITICAL() has been called. */ + /* Now that interrupts are disabled, ulCriticalNesting can be accessed + * directly. Increment ulCriticalNesting to keep a count of how many times + * portENTER_CRITICAL() has been called. */ ulCriticalNesting++; } /*-----------------------------------------------------------*/ @@ -447,18 +458,18 @@ void vPortExitCritical( void ) if( ulCriticalNesting > portNO_CRITICAL_NESTING ) { /* Decrement the nesting count as the critical section is being - exited. */ + * exited. */ ulCriticalNesting--; /* If the nesting level has reached zero then all interrupt - priorities must be re-enabled. */ + * priorities must be re-enabled. */ if( ulCriticalNesting == portNO_CRITICAL_NESTING ) { /* Critical nesting has reached zero so all interrupt priorities - should be unmasked. */ - #if( configMAX_API_CALL_INTERRUPT_PRIORITY == portMAX_PRIORITY ) + * should be unmasked. */ + #if ( configMAX_API_CALL_INTERRUPT_PRIORITY == portMAX_PRIORITY ) { - __asm volatile( "sti" ); + __asm volatile ( "sti" ); } #else { @@ -467,11 +478,11 @@ void vPortExitCritical( void ) #endif /* If a yield was pended from within the critical section then - perform the yield now. */ + * perform the yield now. */ if( ulPortYieldPending != pdFALSE ) { ulPortYieldPending = pdFALSE; - __asm volatile( portYIELD_INTERRUPT ); + __asm volatile ( portYIELD_INTERRUPT ); } } } @@ -480,17 +491,17 @@ void vPortExitCritical( void ) uint32_t ulPortSetInterruptMask( void ) { -volatile uint32_t ulOriginalMask; + volatile uint32_t ulOriginalMask; /* Set mask to max syscall priority. */ - #if( configMAX_API_CALL_INTERRUPT_PRIORITY == portMAX_PRIORITY ) + #if ( configMAX_API_CALL_INTERRUPT_PRIORITY == portMAX_PRIORITY ) { /* Return whether interrupts were already enabled or not. Pop adjusts - the stack first. */ - __asm volatile( "pushf \t\n" - "pop %0 \t\n" - "cli " - : "=rm" (ulOriginalMask) :: "memory" ); + * the stack first. */ + __asm volatile ( "pushf \t\n" + "pop %0 \t\n" + "cli " + : "=rm" ( ulOriginalMask )::"memory" ); ulOriginalMask &= portEFLAGS_IF; } @@ -501,7 +512,7 @@ volatile uint32_t ulOriginalMask; portAPIC_TASK_PRIORITY = portMAX_API_CALL_PRIORITY; configASSERT( portAPIC_TASK_PRIORITY == portMAX_API_CALL_PRIORITY ); } - #endif + #endif /* if ( configMAX_API_CALL_INTERRUPT_PRIORITY == portMAX_PRIORITY ) */ return ulOriginalMask; } @@ -509,11 +520,11 @@ volatile uint32_t ulOriginalMask; void vPortClearInterruptMask( uint32_t ulNewMaskValue ) { - #if( configMAX_API_CALL_INTERRUPT_PRIORITY == portMAX_PRIORITY ) + #if ( configMAX_API_CALL_INTERRUPT_PRIORITY == portMAX_PRIORITY ) { if( ulNewMaskValue != pdFALSE ) { - __asm volatile( "sti" ); + __asm volatile ( "sti" ); } } #else @@ -521,7 +532,7 @@ void vPortClearInterruptMask( uint32_t ulNewMaskValue ) portAPIC_TASK_PRIORITY = ulNewMaskValue; configASSERT( portAPIC_TASK_PRIORITY == ulNewMaskValue ); } - #endif + #endif /* if ( configMAX_API_CALL_INTERRUPT_PRIORITY == portMAX_PRIORITY ) */ } /*-----------------------------------------------------------*/ @@ -530,12 +541,12 @@ void vPortClearInterruptMask( uint32_t ulNewMaskValue ) void vPortTaskUsesFPU( void ) { /* A task is registering the fact that it needs an FPU context. Allocate a - buffer into which the context can be saved. */ + * buffer into which the context can be saved. */ pucPortTaskFPUContextBuffer = ( uint8_t * ) pvPortMalloc( portFPU_CONTEXT_SIZE_BYTES ); configASSERT( pucPortTaskFPUContextBuffer ); /* Initialise the floating point registers. */ - __asm volatile( "fninit" ); + __asm volatile ( "fninit" ); } #endif /* configSUPPORT_FPU */ @@ -544,7 +555,7 @@ void vPortClearInterruptMask( uint32_t ulNewMaskValue ) void vPortAPICErrorHandler( void ) { /* Variable to hold the APIC error status for viewing in the debugger. */ -volatile uint32_t ulErrorStatus = 0; + volatile uint32_t ulErrorStatus = 0; portAPIC_ERROR_STATUS = 0; ulErrorStatus = portAPIC_ERROR_STATUS; @@ -555,7 +566,7 @@ volatile uint32_t ulErrorStatus = 0; } /*-----------------------------------------------------------*/ -#if( configUSE_COMMON_INTERRUPT_ENTRY_POINT == 1 ) +#if ( configUSE_COMMON_INTERRUPT_ENTRY_POINT == 1 ) void vPortCentralInterruptHandler( uint32_t ulVector ) { @@ -578,17 +589,18 @@ volatile uint32_t ulErrorStatus = 0; #if ( configUSE_COMMON_INTERRUPT_ENTRY_POINT == 1 ) - BaseType_t xPortRegisterCInterruptHandler( ISR_Handler_t pxHandler, uint32_t ulVectorNumber ) + BaseType_t xPortRegisterCInterruptHandler( ISR_Handler_t pxHandler, + uint32_t ulVectorNumber ) { - BaseType_t xReturn; + BaseType_t xReturn; xReturn = prvCheckValidityOfVectorNumber( ulVectorNumber ); if( xReturn != pdFAIL ) { /* Save the handler passed in by the application in the vector number - passed in. The addresses are then called from the central interrupt - handler. */ + * passed in. The addresses are then called from the central interrupt + * handler. */ xInterruptHandlerTable[ ulVectorNumber ] = pxHandler; } @@ -598,9 +610,10 @@ volatile uint32_t ulErrorStatus = 0; #endif /* configUSE_COMMON_INTERRUPT_ENTRY_POINT */ /*-----------------------------------------------------------*/ -BaseType_t xPortInstallInterruptHandler( ISR_Handler_t pxHandler, uint32_t ulVectorNumber ) +BaseType_t xPortInstallInterruptHandler( ISR_Handler_t pxHandler, + uint32_t ulVectorNumber ) { -BaseType_t xReturn; + BaseType_t xReturn; xReturn = prvCheckValidityOfVectorNumber( ulVectorNumber ); @@ -620,7 +633,7 @@ BaseType_t xReturn; static BaseType_t prvCheckValidityOfVectorNumber( uint32_t ulVectorNumber ) { -BaseType_t xReturn; + BaseType_t xReturn; /* Check validity of vector number. */ if( ulVectorNumber >= portNUM_VECTORS ) @@ -669,5 +682,5 @@ BaseType_t xReturn; void vGenerateYieldInterrupt( void ) { - __asm volatile( portYIELD_INTERRUPT ); + __asm volatile ( portYIELD_INTERRUPT ); } diff --git a/Source/portable/GCC/IA32_flat/portASM.S b/Source/portable/GCC/IA32_flat/portASM.S index 8bf03db3f..02d546ce7 100644 --- a/Source/portable/GCC/IA32_flat/portASM.S +++ b/Source/portable/GCC/IA32_flat/portASM.S @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/Source/portable/GCC/IA32_flat/portmacro.h b/Source/portable/GCC/IA32_flat/portmacro.h index 823d96a28..40436a358 100644 --- a/Source/portable/GCC/IA32_flat/portmacro.h +++ b/Source/portable/GCC/IA32_flat/portmacro.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -46,42 +46,42 @@ */ /* Type definitions. */ -#define portCHAR char -#define portFLOAT float -#define portDOUBLE double -#define portLONG long -#define portSHORT short -#define portSTACK_TYPE uint32_t -#define portBASE_TYPE long +#define portCHAR char +#define portFLOAT float +#define portDOUBLE double +#define portLONG long +#define portSHORT short +#define portSTACK_TYPE uint32_t +#define portBASE_TYPE long -typedef portSTACK_TYPE StackType_t; -typedef long BaseType_t; -typedef unsigned long UBaseType_t; +typedef portSTACK_TYPE StackType_t; +typedef long BaseType_t; +typedef unsigned long UBaseType_t; -typedef uint32_t TickType_t; -#define portMAX_DELAY ( ( TickType_t ) 0xffffffffUL ) +typedef uint32_t TickType_t; +#define portMAX_DELAY ( ( TickType_t ) 0xffffffffUL ) /*-----------------------------------------------------------*/ /* Hardware specifics. */ -#define portSTACK_GROWTH ( -1 ) -#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) -#define portBYTE_ALIGNMENT 32 +#define portSTACK_GROWTH ( -1 ) +#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) +#define portBYTE_ALIGNMENT 32 /*-----------------------------------------------------------*/ /* Task utilities. */ /* The interrupt priority (for vectors 16 to 255) is determined using vector/16. -The quotient is rounded to the nearest integer with 1 being the lowest priority -and 15 is the highest. Therefore the following two interrupts are at the lowest -priority. *NOTE 1* If the yield vector is changed then it must also be changed -in the portYIELD_INTERRUPT definition immediately below. */ + * The quotient is rounded to the nearest integer with 1 being the lowest priority + * and 15 is the highest. Therefore the following two interrupts are at the lowest + * priority. *NOTE 1* If the yield vector is changed then it must also be changed + * in the portYIELD_INTERRUPT definition immediately below. */ #define portAPIC_TIMER_INT_VECTOR ( 0x21 ) #define portAPIC_YIELD_INT_VECTOR ( 0x20 ) /* Build yield interrupt instruction. */ -#define portYIELD_INTERRUPT "int $0x20" +#define portYIELD_INTERRUPT "int $0x20" /* APIC register addresses. */ #define portAPIC_EOI ( *( ( volatile uint32_t * ) 0xFEE000B0UL ) ) @@ -90,61 +90,61 @@ in the portYIELD_INTERRUPT definition immediately below. */ #define portAPIC_ENABLE_BIT ( 1UL << 8UL ) #define portAPIC_TIMER_PERIODIC ( 1UL << 17UL ) #define portAPIC_DISABLE ( 1UL << 16UL ) -#define portAPIC_NMI ( 4 << 8) +#define portAPIC_NMI ( 4 << 8 ) #define portAPIC_DIV_16 ( 0x03 ) /* Define local API register addresses. */ -#define portAPIC_ID_REGISTER ( *( ( volatile uint32_t * ) ( configAPIC_BASE + 0x20UL ) ) ) -#define portAPIC_SPURIOUS_INT ( *( ( volatile uint32_t * ) ( configAPIC_BASE + 0xF0UL ) ) ) +#define portAPIC_ID_REGISTER ( *( ( volatile uint32_t * ) ( configAPIC_BASE + 0x20UL ) ) ) +#define portAPIC_SPURIOUS_INT ( *( ( volatile uint32_t * ) ( configAPIC_BASE + 0xF0UL ) ) ) #define portAPIC_LVT_TIMER ( *( ( volatile uint32_t * ) ( configAPIC_BASE + 0x320UL ) ) ) #define portAPIC_TIMER_INITIAL_COUNT ( *( ( volatile uint32_t * ) ( configAPIC_BASE + 0x380UL ) ) ) #define portAPIC_TIMER_CURRENT_COUNT ( *( ( volatile uint32_t * ) ( configAPIC_BASE + 0x390UL ) ) ) -#define portAPIC_TASK_PRIORITY ( *( ( volatile uint32_t * ) ( configAPIC_BASE + 0x80UL ) ) ) +#define portAPIC_TASK_PRIORITY ( *( ( volatile uint32_t * ) ( configAPIC_BASE + 0x80UL ) ) ) #define portAPIC_LVT_ERROR ( *( ( volatile uint32_t * ) ( configAPIC_BASE + 0x370UL ) ) ) #define portAPIC_ERROR_STATUS ( *( ( volatile uint32_t * ) ( configAPIC_BASE + 0x280UL ) ) ) -#define portAPIC_LDR ( *( ( volatile uint32_t * ) ( configAPIC_BASE + 0xD0UL ) ) ) +#define portAPIC_LDR ( *( ( volatile uint32_t * ) ( configAPIC_BASE + 0xD0UL ) ) ) #define portAPIC_TMRDIV ( *( ( volatile uint32_t * ) ( configAPIC_BASE + 0x3E0UL ) ) ) #define portAPIC_LVT_PERF ( *( ( volatile uint32_t * ) ( configAPIC_BASE + 0x340UL ) ) ) #define portAPIC_LVT_LINT0 ( *( ( volatile uint32_t * ) ( configAPIC_BASE + 0x350UL ) ) ) #define portAPIC_LVT_LINT1 ( *( ( volatile uint32_t * ) ( configAPIC_BASE + 0x360UL ) ) ) /* Don't yield if inside a critical section - instead hold the yield pending -so it is performed when the critical section is exited. */ -#define portYIELD() \ -{ \ -extern volatile uint32_t ulCriticalNesting; \ -extern volatile uint32_t ulPortYieldPending; \ - if( ulCriticalNesting != 0 ) \ - { \ - ulPortYieldPending = pdTRUE; \ - } \ - else \ - { \ - __asm volatile( portYIELD_INTERRUPT ); \ - } \ -} + * so it is performed when the critical section is exited. */ +#define portYIELD() \ + { \ + extern volatile uint32_t ulCriticalNesting; \ + extern volatile uint32_t ulPortYieldPending; \ + if( ulCriticalNesting != 0 ) \ + { \ + ulPortYieldPending = pdTRUE; \ + } \ + else \ + { \ + __asm volatile ( portYIELD_INTERRUPT ); \ + } \ + } /* Called at the end of an ISR that can cause a context switch - pend a yield if -xSwithcRequired is not false. */ -#define portEND_SWITCHING_ISR( xSwitchRequired ) \ -{ \ -extern volatile uint32_t ulPortYieldPending; \ - if( xSwitchRequired != pdFALSE ) \ - { \ - ulPortYieldPending = 1; \ - } \ -} + * xSwitchRequired is not false. */ +#define portEND_SWITCHING_ISR( xSwitchRequired ) \ + { \ + extern volatile uint32_t ulPortYieldPending; \ + if( xSwitchRequired != pdFALSE ) \ + { \ + ulPortYieldPending = 1; \ + } \ + } /* Same as portEND_SWITCHING_ISR() - take your pick which name to use. */ -#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x ) +#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x ) /*----------------------------------------------------------- - * Critical section control - *----------------------------------------------------------*/ +* Critical section control +*----------------------------------------------------------*/ /* Critical sections for use in interrupts. */ -#define portSET_INTERRUPT_MASK_FROM_ISR() ulPortSetInterruptMask() -#define portCLEAR_INTERRUPT_MASK_FROM_ISR(x) vPortClearInterruptMask( x ) +#define portSET_INTERRUPT_MASK_FROM_ISR() ulPortSetInterruptMask() +#define portCLEAR_INTERRUPT_MASK_FROM_ISR( x ) vPortClearInterruptMask( x ) extern void vPortEnterCritical( void ); extern void vPortExitCritical( void ); @@ -152,139 +152,146 @@ extern uint32_t ulPortSetInterruptMask( void ); extern void vPortClearInterruptMask( uint32_t ulNewMaskValue ); /* These macros do not globally disable/enable interrupts. They do mask off -interrupts that have a priority below configMAX_API_CALL_INTERRUPT_PRIORITY. */ + * interrupts that have a priority below configMAX_API_CALL_INTERRUPT_PRIORITY. */ #define portENTER_CRITICAL() vPortEnterCritical() #define portEXIT_CRITICAL() vPortExitCritical() -#define portDISABLE_INTERRUPTS() __asm volatile( "cli" ) -#define portENABLE_INTERRUPTS() __asm volatile( "sti" ) +#define portDISABLE_INTERRUPTS() __asm volatile ( "cli" ) +#define portENABLE_INTERRUPTS() __asm volatile ( "sti" ) /*-----------------------------------------------------------*/ /* Task function macros as described on the FreeRTOS.org WEB site. These are -not required for this port but included in case common demo code that uses these -macros is used. */ -#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters ) -#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters ) + * not required for this port but included in case common demo code that uses these + * macros is used. */ +#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters ) +#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters ) /* Architecture specific optimisations. */ #if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 - /* Store/clear the ready priorities in a bit map. */ - #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) \ - __asm volatile( "bsr %1, %0\n\t" \ - :"=r"(uxTopPriority) : "rm"(uxReadyPriorities) : "cc" ) +/* Store/clear the ready priorities in a bit map. */ + #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) \ + __asm volatile ( "bsr %1, %0\n\t" \ + : "=r" ( uxTopPriority ) : "rm" ( uxReadyPriorities ) : "cc" ) - #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) ) - #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) ) + #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) ) + #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) ) #endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */ -#define portNOP() __asm volatile( "NOP" ) +#define portNOP() __asm volatile ( "NOP" ) /*----------------------------------------------------------- - * Misc - *----------------------------------------------------------*/ +* Misc +*----------------------------------------------------------*/ #define portNUM_VECTORS 256 #define portMAX_PRIORITY 15 -typedef void ( *ISR_Handler_t ) ( void ); +typedef void ( * ISR_Handler_t ) ( void ); /* Any task that uses the floating point unit MUST call vPortTaskUsesFPU() -before any floating point instructions are executed. */ + * before any floating point instructions are executed. */ #ifndef configSUPPORT_FPU - #define configSUPPORT_FPU 0 + #define configSUPPORT_FPU 0 #endif #if configSUPPORT_FPU == 1 void vPortTaskUsesFPU( void ); - #define portTASK_USES_FLOATING_POINT() vPortTaskUsesFPU() + #define portTASK_USES_FLOATING_POINT() vPortTaskUsesFPU() #endif /* See the comments under the configUSE_COMMON_INTERRUPT_ENTRY_POINT definition -below. */ -BaseType_t xPortRegisterCInterruptHandler( ISR_Handler_t pxHandler, uint32_t ulVectorNumber ); -BaseType_t xPortInstallInterruptHandler( ISR_Handler_t pxHandler, uint32_t ulVectorNumber ); + * below. */ +BaseType_t xPortRegisterCInterruptHandler( ISR_Handler_t pxHandler, + uint32_t ulVectorNumber ); +BaseType_t xPortInstallInterruptHandler( ISR_Handler_t pxHandler, + uint32_t ulVectorNumber ); #ifndef configAPIC_BASE - /* configAPIC_BASE_ADDRESS sets the base address of the local APIC. It can - be overridden in FreeRTOSConfig.h should it not be constant. */ - #define configAPIC_BASE 0xFEE00000UL + +/* configAPIC_BASE_ADDRESS sets the base address of the local APIC. It can + * be overridden in FreeRTOSConfig.h should it not be constant. */ + #define configAPIC_BASE 0xFEE00000UL #endif #ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION - /* The FreeRTOS scheduling algorithm selects the task that will enter the - Running state. configUSE_PORT_OPTIMISED_TASK_SELECTION is used to set how - that is done. - - If configUSE_PORT_OPTIMISED_TASK_SELECTION is set to 0 then the task to - enter the Running state is selected using a portable algorithm written in - C. This is the slowest method, but the algorithm does not restrict the - maximum number of unique RTOS task priorities that are available. - - If configUSE_PORT_OPTIMISED_TASK_SELECTION is set to 1 then the task to - enter the Running state is selected using a single assembly instruction. - This is the fastest method, but restricts the maximum number of unique RTOS - task priorities to 32 (the same task priority can be assigned to any number - of RTOS tasks). */ + +/* The FreeRTOS scheduling algorithm selects the task that will enter the + * Running state. configUSE_PORT_OPTIMISED_TASK_SELECTION is used to set how + * that is done. + * + * If configUSE_PORT_OPTIMISED_TASK_SELECTION is set to 0 then the task to + * enter the Running state is selected using a portable algorithm written in + * C. This is the slowest method, but the algorithm does not restrict the + * maximum number of unique RTOS task priorities that are available. + * + * If configUSE_PORT_OPTIMISED_TASK_SELECTION is set to 1 then the task to + * enter the Running state is selected using a single assembly instruction. + * This is the fastest method, but restricts the maximum number of unique RTOS + * task priorities to 32 (the same task priority can be assigned to any number + * of RTOS tasks). */ #warning configUSE_PORT_OPTIMISED_TASK_SELECTION was not defined in FreeRTOSConfig.h and has been defaulted to 1 - #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1 + #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1 #endif #ifndef configUSE_COMMON_INTERRUPT_ENTRY_POINT - /* There are two ways of implementing interrupt handlers: - - 1) As standard C functions - - - This method can only be used if configUSE_COMMON_INTERRUPT_ENTRY_POINT - is set to 1. The C function is installed using - xPortRegisterCInterruptHandler(). - - This is the simplest of the two methods but incurs a slightly longer - interrupt entry time. - 2) By using an assembly stub that wraps the handler in the FreeRTOS - portFREERTOS_INTERRUPT_ENTRY and portFREERTOS_INTERRUPT_EXIT macros. - - This method can always be used. It is slightly more complex than - method 1 but benefits from a faster interrupt entry time. */ +/* There are two ways of implementing interrupt handlers: + * + * 1) As standard C functions - + * + * This method can only be used if configUSE_COMMON_INTERRUPT_ENTRY_POINT + * is set to 1. The C function is installed using + * xPortRegisterCInterruptHandler(). + * + * This is the simplest of the two methods but incurs a slightly longer + * interrupt entry time. + * + * 2) By using an assembly stub that wraps the handler in the FreeRTOS + * portFREERTOS_INTERRUPT_ENTRY and portFREERTOS_INTERRUPT_EXIT macros. + * + * This method can always be used. It is slightly more complex than + * method 1 but benefits from a faster interrupt entry time. */ #warning configUSE_COMMON_INTERRUPT_ENTRY_POINT was not defined in FreeRTOSConfig.h and has been defaulted to 1. - #define configUSE_COMMON_INTERRUPT_ENTRY_POINT 1 + #define configUSE_COMMON_INTERRUPT_ENTRY_POINT 1 #endif #ifndef configISR_STACK_SIZE - /* Interrupt entry code will switch the stack in use to a dedicated system - stack. - configISR_STACK_SIZE defines the number of 32-bit values that can be stored - on the system stack, and must be large enough to hold a potentially nested - interrupt stack frame. */ +/* Interrupt entry code will switch the stack in use to a dedicated system + * stack. + * + * configISR_STACK_SIZE defines the number of 32-bit values that can be stored + * on the system stack, and must be large enough to hold a potentially nested + * interrupt stack frame. */ #error configISR_STACK_SIZE was not defined in FreeRTOSConfig.h. #endif #ifndef configMAX_API_CALL_INTERRUPT_PRIORITY - /* Interrupt safe FreeRTOS functions (those that end in "FromISR" must not - be called from an interrupt that has a priority above that set by - configMAX_API_CALL_INTERRUPT_PRIORITY. */ + +/* Interrupt safe FreeRTOS functions (those that end in "FromISR" must not + * be called from an interrupt that has a priority above that set by + * configMAX_API_CALL_INTERRUPT_PRIORITY. */ #warning configMAX_API_CALL_INTERRUPT_PRIORITY was not defined in FreeRTOSConfig.h and has been defaulted to 10 - #define configMAX_API_CALL_INTERRUPT_PRIORITY 10 + #define configMAX_API_CALL_INTERRUPT_PRIORITY 10 #endif #ifndef configSUPPORT_FPU #warning configSUPPORT_FPU was not defined in FreeRTOSConfig.h and has been defaulted to 0 - #define configSUPPORT_FPU 0 + #define configSUPPORT_FPU 0 #endif /* The value written to the task priority register to raise the interrupt mask -to the maximum from which FreeRTOS API calls can be made. */ -#define portAPIC_PRIORITY_SHIFT ( 4UL ) -#define portAPIC_MAX_SUB_PRIORITY ( 0x0fUL ) -#define portMAX_API_CALL_PRIORITY ( ( configMAX_API_CALL_INTERRUPT_PRIORITY << portAPIC_PRIORITY_SHIFT ) | portAPIC_MAX_SUB_PRIORITY ) + * to the maximum from which FreeRTOS API calls can be made. */ +#define portAPIC_PRIORITY_SHIFT ( 4UL ) +#define portAPIC_MAX_SUB_PRIORITY ( 0x0fUL ) +#define portMAX_API_CALL_PRIORITY ( ( configMAX_API_CALL_INTERRUPT_PRIORITY << portAPIC_PRIORITY_SHIFT ) | portAPIC_MAX_SUB_PRIORITY ) /* Asserts if interrupt safe FreeRTOS functions are called from a priority -above the max system call interrupt priority. */ -#define portAPIC_PROCESSOR_PRIORITY ( *( ( volatile uint32_t * ) ( configAPIC_BASE + 0xA0UL ) ) ) -#define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() configASSERT( ( portAPIC_PROCESSOR_PRIORITY ) <= ( portMAX_API_CALL_PRIORITY ) ) + * above the max system call interrupt priority. */ +#define portAPIC_PROCESSOR_PRIORITY ( *( ( volatile uint32_t * ) ( configAPIC_BASE + 0xA0UL ) ) ) +#define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() configASSERT( ( portAPIC_PROCESSOR_PRIORITY ) <= ( portMAX_API_CALL_PRIORITY ) ) /* *INDENT-OFF* */ #ifdef __cplusplus diff --git a/Source/portable/GCC/MSP430F449/port.c b/Source/portable/GCC/MSP430F449/port.c index d9d31915f..48df25397 100644 --- a/Source/portable/GCC/MSP430F449/port.c +++ b/Source/portable/GCC/MSP430F449/port.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -27,10 +27,10 @@ */ /* - Changes from V2.5.2 - - + usCriticalNesting now has a volatile qualifier. -*/ + * Changes from V2.5.2 + * + + usCriticalNesting now has a volatile qualifier. + */ /* Standard includes. */ #include @@ -41,32 +41,32 @@ #include "task.h" /*----------------------------------------------------------- - * Implementation of functions defined in portable.h for the MSP430 port. - *----------------------------------------------------------*/ +* Implementation of functions defined in portable.h for the MSP430 port. +*----------------------------------------------------------*/ /* Constants required for hardware setup. The tick ISR runs off the ACLK, -not the MCLK. */ + * not the MCLK. */ #define portACLK_FREQUENCY_HZ ( ( TickType_t ) 32768 ) #define portINITIAL_CRITICAL_NESTING ( ( uint16_t ) 10 ) -#define portFLAGS_INT_ENABLED ( ( StackType_t ) 0x08 ) +#define portFLAGS_INT_ENABLED ( ( StackType_t ) 0x08 ) /* We require the address of the pxCurrentTCB variable, but don't want to know -any details of its type. */ + * any details of its type. */ typedef void TCB_t; extern volatile TCB_t * volatile pxCurrentTCB; /* Most ports implement critical sections by placing the interrupt flags on -the stack before disabling interrupts. Exiting the critical section is then -simply a case of popping the flags from the stack. As mspgcc does not use -a frame pointer this cannot be done as modifying the stack will clobber all -the stack variables. Instead each task maintains a count of the critical -section nesting depth. Each time a critical section is entered the count is -incremented. Each time a critical section is left the count is decremented - -with interrupts only being re-enabled if the count is zero. - -usCriticalNesting will get set to zero when the scheduler starts, but must -not be initialised to zero as this will cause problems during the startup -sequence. */ + * the stack before disabling interrupts. Exiting the critical section is then + * simply a case of popping the flags from the stack. As mspgcc does not use + * a frame pointer this cannot be done as modifying the stack will clobber all + * the stack variables. Instead each task maintains a count of the critical + * section nesting depth. Each time a critical section is entered the count is + * incremented. Each time a critical section is left the count is decremented - + * with interrupts only being re-enabled if the count is zero. + * + * usCriticalNesting will get set to zero when the scheduler starts, but must + * not be initialised to zero as this will cause problems during the startup + * sequence. */ volatile uint16_t usCriticalNesting = portINITIAL_CRITICAL_NESTING; /*-----------------------------------------------------------*/ @@ -77,24 +77,24 @@ volatile uint16_t usCriticalNesting = portINITIAL_CRITICAL_NESTING; * pointer value is saved into the task control block so it can be retrieved * the next time the task executes. */ -#define portSAVE_CONTEXT() \ - asm volatile ( "push r4 \n\t" \ - "push r5 \n\t" \ - "push r6 \n\t" \ - "push r7 \n\t" \ - "push r8 \n\t" \ - "push r9 \n\t" \ - "push r10 \n\t" \ - "push r11 \n\t" \ - "push r12 \n\t" \ - "push r13 \n\t" \ - "push r14 \n\t" \ - "push r15 \n\t" \ - "mov.w usCriticalNesting, r14 \n\t" \ - "push r14 \n\t" \ - "mov.w pxCurrentTCB, r12 \n\t" \ - "mov.w r1, @r12 \n\t" \ - ); +#define portSAVE_CONTEXT() \ + asm volatile ( "push r4 \n\t" \ + "push r5 \n\t" \ + "push r6 \n\t" \ + "push r7 \n\t" \ + "push r8 \n\t" \ + "push r9 \n\t" \ + "push r10 \n\t" \ + "push r11 \n\t" \ + "push r12 \n\t" \ + "push r13 \n\t" \ + "push r14 \n\t" \ + "push r15 \n\t" \ + "mov.w usCriticalNesting, r14 \n\t" \ + "push r14 \n\t" \ + "mov.w pxCurrentTCB, r12 \n\t" \ + "mov.w r1, @r12 \n\t" \ + ); /* * Macro to restore a task context from the task stack. This is effectively @@ -106,26 +106,26 @@ volatile uint16_t usCriticalNesting = portINITIAL_CRITICAL_NESTING; * The bic instruction ensures there are no low power bits set in the status * register that is about to be popped from the stack. */ -#define portRESTORE_CONTEXT() \ - asm volatile ( "mov.w pxCurrentTCB, r12 \n\t" \ - "mov.w @r12, r1 \n\t" \ - "pop r15 \n\t" \ - "mov.w r15, usCriticalNesting \n\t" \ - "pop r15 \n\t" \ - "pop r14 \n\t" \ - "pop r13 \n\t" \ - "pop r12 \n\t" \ - "pop r11 \n\t" \ - "pop r10 \n\t" \ - "pop r9 \n\t" \ - "pop r8 \n\t" \ - "pop r7 \n\t" \ - "pop r6 \n\t" \ - "pop r5 \n\t" \ - "pop r4 \n\t" \ - "bic #(0xf0),0(r1) \n\t" \ - "reti \n\t" \ - ); +#define portRESTORE_CONTEXT() \ + asm volatile ( "mov.w pxCurrentTCB, r12 \n\t" \ + "mov.w @r12, r1 \n\t" \ + "pop r15 \n\t" \ + "mov.w r15, usCriticalNesting \n\t" \ + "pop r15 \n\t" \ + "pop r14 \n\t" \ + "pop r13 \n\t" \ + "pop r12 \n\t" \ + "pop r11 \n\t" \ + "pop r10 \n\t" \ + "pop r9 \n\t" \ + "pop r8 \n\t" \ + "pop r7 \n\t" \ + "pop r6 \n\t" \ + "pop r5 \n\t" \ + "pop r4 \n\t" \ + "bic #(0xf0),0(r1) \n\t" \ + "reti \n\t" \ + ); /*-----------------------------------------------------------*/ /* @@ -141,24 +141,26 @@ static void prvSetupTimerInterrupt( void ); * * See the header file portable.h. */ -StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters ) +StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, + TaskFunction_t pxCode, + void * pvParameters ) { /* - Place a few bytes of known values on the bottom of the stack. - This is just useful for debugging and can be included if required. - - *pxTopOfStack = ( StackType_t ) 0x1111; - pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x2222; - pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x3333; - pxTopOfStack--; - */ + * Place a few bytes of known values on the bottom of the stack. + * This is just useful for debugging and can be included if required. + * + * pxTopOfStack = ( StackType_t ) 0x1111; + * pxTopOfStack--; + * pxTopOfStack = ( StackType_t ) 0x2222; + * pxTopOfStack--; + * pxTopOfStack = ( StackType_t ) 0x3333; + * pxTopOfStack--; + */ /* The msp430 automatically pushes the PC then SR onto the stack before - executing an ISR. We want the stack to look just as if this has happened - so place a pointer to the start of the task on the stack first - followed - by the flags we want the task to use when it starts up. */ + * executing an ISR. We want the stack to look just as if this has happened + * so place a pointer to the start of the task on the stack first - followed + * by the flags we want the task to use when it starts up. */ *pxTopOfStack = ( StackType_t ) pxCode; pxTopOfStack--; *pxTopOfStack = portFLAGS_INT_ENABLED; @@ -189,19 +191,19 @@ StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t px pxTopOfStack--; /* When the task starts is will expect to find the function parameter in - R15. */ + * R15. */ *pxTopOfStack = ( StackType_t ) pvParameters; pxTopOfStack--; /* The code generated by the mspgcc compiler does not maintain separate - stack and frame pointers. The portENTER_CRITICAL macro cannot therefore - use the stack as per other ports. Instead a variable is used to keep - track of the critical section nesting. This variable has to be stored - as part of the task context and is initially set to zero. */ + * stack and frame pointers. The portENTER_CRITICAL macro cannot therefore + * use the stack as per other ports. Instead a variable is used to keep + * track of the critical section nesting. This variable has to be stored + * as part of the task context and is initially set to zero. */ *pxTopOfStack = ( StackType_t ) portNO_CRITICAL_SECTION_NESTING; /* Return a pointer to the top of the stack we have generated so this can - be stored in the task control block for the task. */ + * be stored in the task control block for the task. */ return pxTopOfStack; } /*-----------------------------------------------------------*/ @@ -209,7 +211,7 @@ StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t px BaseType_t xPortStartScheduler( void ) { /* Setup the hardware to generate the tick. Interrupts are disabled when - this function is called. */ + * this function is called. */ prvSetupTimerInterrupt(); /* Restore the context of the first task that is going to run. */ @@ -223,7 +225,7 @@ BaseType_t xPortStartScheduler( void ) void vPortEndScheduler( void ) { /* It is unlikely that the MSP430 port will get stopped. If required simply - disable the tick interrupt here. */ + * disable the tick interrupt here. */ } /*-----------------------------------------------------------*/ @@ -232,13 +234,13 @@ void vPortEndScheduler( void ) * * The first thing we do is save the registers so we can use a naked attribute. */ -void vPortYield( void ) __attribute__ ( ( naked ) ); +void vPortYield( void ) __attribute__( ( naked ) ); void vPortYield( void ) { /* We want the stack of the task being saved to look exactly as if the task - was saved during a pre-emptive RTOS tick ISR. Before calling an ISR the - msp430 places the status register onto the stack. As this is a function - call and not an ISR we have to do this manually. */ + * was saved during a pre-emptive RTOS tick ISR. Before calling an ISR the + * msp430 places the status register onto the stack. As this is a function + * call and not an ISR we have to do this manually. */ asm volatile ( "push r2" ); _DINT(); @@ -289,19 +291,19 @@ static void prvSetupTimerInterrupt( void ) #if configUSE_PREEMPTION == 1 - /* - * Tick ISR for preemptive scheduler. We can use a naked attribute as - * the context is saved at the start of vPortYieldFromTick(). The tick - * count is incremented after the context is saved. - */ - interrupt (TIMERA0_VECTOR) prvTickISR( void ) __attribute__ ( ( naked ) ); - interrupt (TIMERA0_VECTOR) prvTickISR( void ) +/* + * Tick ISR for preemptive scheduler. We can use a naked attribute as + * the context is saved at the start of vPortYieldFromTick(). The tick + * count is incremented after the context is saved. + */ + interrupt( TIMERA0_VECTOR ) prvTickISR( void ) __attribute__( ( naked ) ); + interrupt( TIMERA0_VECTOR ) prvTickISR( void ) { /* Save the context of the interrupted task. */ portSAVE_CONTEXT(); /* Increment the tick count then switch to the highest priority task - that is ready to run. */ + * that is ready to run. */ if( xTaskIncrementTick() != pdFALSE ) { vTaskSwitchContext(); @@ -311,19 +313,16 @@ static void prvSetupTimerInterrupt( void ) portRESTORE_CONTEXT(); } -#else +#else /* if configUSE_PREEMPTION == 1 */ - /* - * Tick ISR for the cooperative scheduler. All this does is increment the - * tick count. We don't need to switch context, this can only be done by - * manual calls to taskYIELD(); - */ - interrupt (TIMERA0_VECTOR) prvTickISR( void ); - interrupt (TIMERA0_VECTOR) prvTickISR( void ) +/* + * Tick ISR for the cooperative scheduler. All this does is increment the + * tick count. We don't need to switch context, this can only be done by + * manual calls to taskYIELD(); + */ + interrupt( TIMERA0_VECTOR ) prvTickISR( void ); + interrupt( TIMERA0_VECTOR ) prvTickISR( void ) { xTaskIncrementTick(); } -#endif - - - +#endif /* if configUSE_PREEMPTION == 1 */ diff --git a/Source/portable/GCC/MSP430F449/portmacro.h b/Source/portable/GCC/MSP430F449/portmacro.h index 29fa5318e..20417ad42 100644 --- a/Source/portable/GCC/MSP430F449/portmacro.h +++ b/Source/portable/GCC/MSP430F449/portmacro.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -46,24 +46,24 @@ */ /* Type definitions. */ -#define portCHAR char -#define portFLOAT float -#define portDOUBLE double -#define portLONG long -#define portSHORT int -#define portSTACK_TYPE uint16_t -#define portBASE_TYPE short +#define portCHAR char +#define portFLOAT float +#define portDOUBLE double +#define portLONG long +#define portSHORT int +#define portSTACK_TYPE uint16_t +#define portBASE_TYPE short -typedef portSTACK_TYPE StackType_t; -typedef short BaseType_t; -typedef unsigned short UBaseType_t; +typedef portSTACK_TYPE StackType_t; +typedef short BaseType_t; +typedef unsigned short UBaseType_t; -#if( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS ) - typedef uint16_t TickType_t; - #define portMAX_DELAY ( TickType_t ) 0xffff +#if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS ) + typedef uint16_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffff #elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS ) - typedef uint32_t TickType_t; - #define portMAX_DELAY ( TickType_t ) ( 0xFFFFFFFFUL ) + typedef uint32_t TickType_t; + #define portMAX_DELAY ( TickType_t ) ( 0xFFFFFFFFUL ) #else #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width. #endif @@ -75,54 +75,54 @@ typedef unsigned short UBaseType_t; /*-----------------------------------------------------------*/ /* Critical section control macros. */ -#define portNO_CRITICAL_SECTION_NESTING ( ( uint16_t ) 0 ) +#define portNO_CRITICAL_SECTION_NESTING ( ( uint16_t ) 0 ) -#define portENTER_CRITICAL() \ -{ \ -extern volatile uint16_t usCriticalNesting; \ - \ - portDISABLE_INTERRUPTS(); \ - \ - /* Now interrupts are disabled ulCriticalNesting can be accessed */ \ - /* directly. Increment ulCriticalNesting to keep a count of how many */ \ - /* times portENTER_CRITICAL() has been called. */ \ - usCriticalNesting++; \ -} +#define portENTER_CRITICAL() \ + { \ + extern volatile uint16_t usCriticalNesting; \ + \ + portDISABLE_INTERRUPTS(); \ + \ + /* Now that interrupts are disabled, ulCriticalNesting can be accessed */ \ + /* directly. Increment ulCriticalNesting to keep a count of how many */ \ + /* times portENTER_CRITICAL() has been called. */ \ + usCriticalNesting++; \ + } -#define portEXIT_CRITICAL() \ -{ \ -extern volatile uint16_t usCriticalNesting; \ - \ - if( usCriticalNesting > portNO_CRITICAL_SECTION_NESTING ) \ - { \ - /* Decrement the nesting count as we are leaving a critical section. */ \ - usCriticalNesting--; \ - \ - /* If the nesting level has reached zero then interrupts should be */ \ - /* re-enabled. */ \ - if( usCriticalNesting == portNO_CRITICAL_SECTION_NESTING ) \ - { \ - portENABLE_INTERRUPTS(); \ - } \ - } \ -} +#define portEXIT_CRITICAL() \ + { \ + extern volatile uint16_t usCriticalNesting; \ + \ + if( usCriticalNesting > portNO_CRITICAL_SECTION_NESTING ) \ + { \ + /* Decrement the nesting count as we are leaving a critical section. */ \ + usCriticalNesting--; \ + \ + /* If the nesting level has reached zero then interrupts should be */ \ + /* re-enabled. */ \ + if( usCriticalNesting == portNO_CRITICAL_SECTION_NESTING ) \ + { \ + portENABLE_INTERRUPTS(); \ + } \ + } \ + } /*-----------------------------------------------------------*/ /* Task utilities. */ -extern void vPortYield( void ) __attribute__ ( ( naked ) ); -#define portYIELD() vPortYield() -#define portNOP() asm volatile ( "NOP" ) +extern void vPortYield( void ) __attribute__( ( naked ) ); +#define portYIELD() vPortYield() +#define portNOP() asm volatile ( "NOP" ) /*-----------------------------------------------------------*/ -/* Hardwware specifics. */ -#define portBYTE_ALIGNMENT 2 -#define portSTACK_GROWTH ( -1 ) -#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) +/* Hardware specifics. */ +#define portBYTE_ALIGNMENT 2 +#define portSTACK_GROWTH ( -1 ) +#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) /*-----------------------------------------------------------*/ /* Task function macros as described on the FreeRTOS.org WEB site. */ -#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters ) -#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters ) +#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters ) +#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters ) /* *INDENT-OFF* */ #ifdef __cplusplus diff --git a/Source/portable/GCC/MicroBlaze/port.c b/Source/portable/GCC/MicroBlaze/port.c index ac1b84390..c5f640f11 100644 --- a/Source/portable/GCC/MicroBlaze/port.c +++ b/Source/portable/GCC/MicroBlaze/port.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -27,8 +27,8 @@ */ /*----------------------------------------------------------- - * Implementation of functions defined in portable.h for the MicroBlaze port. - *----------------------------------------------------------*/ +* Implementation of functions defined in portable.h for the MicroBlaze port. +*----------------------------------------------------------*/ /* Scheduler includes. */ @@ -43,33 +43,33 @@ #include #include -#if( configSUPPORT_DYNAMIC_ALLOCATION == 0 ) +#if ( configSUPPORT_DYNAMIC_ALLOCATION == 0 ) #error configSUPPORT_DYNAMIC_ALLOCATION must be set to 1 to use this port. #endif /* Tasks are started with interrupts enabled. */ -#define portINITIAL_MSR_STATE ( ( StackType_t ) 0x02 ) +#define portINITIAL_MSR_STATE ( ( StackType_t ) 0x02 ) /* Tasks are started with a critical section nesting of 0 - however prior -to the scheduler being commenced we don't want the critical nesting level -to reach zero, so it is initialised to a high value. */ -#define portINITIAL_NESTING_VALUE ( 0xff ) + * to the scheduler being commenced we don't want the critical nesting level + * to reach zero, so it is initialised to a high value. */ +#define portINITIAL_NESTING_VALUE ( 0xff ) /* Our hardware setup only uses one counter. */ -#define portCOUNTER_0 0 +#define portCOUNTER_0 0 /* The stack used by the ISR is filled with a known value to assist in -debugging. */ -#define portISR_STACK_FILL_VALUE 0x55555555 + * debugging. */ +#define portISR_STACK_FILL_VALUE 0x55555555 /* Counts the nesting depth of calls to portENTER_CRITICAL(). Each task -maintains it's own count, so this variable is saved as part of the task -context. */ + * maintains it's own count, so this variable is saved as part of the task + * context. */ volatile UBaseType_t uxCriticalNesting = portINITIAL_NESTING_VALUE; /* To limit the amount of stack required by each task, this port uses a -separate stack for interrupts. */ -uint32_t *pulISRStack; + * separate stack for interrupts. */ +uint32_t * pulISRStack; /*-----------------------------------------------------------*/ @@ -86,17 +86,19 @@ static void prvSetupTimerInterrupt( void ); * * See the header file portable.h. */ -StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters ) +StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, + TaskFunction_t pxCode, + void * pvParameters ) { -extern void * _SDA2_BASE_; -extern void * _SDA_BASE_; -const uint32_t ulR2 = ( uint32_t ) &_SDA2_BASE_; -const uint32_t ulR13 = ( uint32_t ) &_SDA_BASE_; + extern void * _SDA2_BASE_; + extern void * _SDA_BASE_; + const uint32_t ulR2 = ( uint32_t ) &_SDA2_BASE_; + const uint32_t ulR13 = ( uint32_t ) &_SDA_BASE_; /* Place a few bytes of known values on the bottom of the stack. - This is essential for the Microblaze port and these lines must - not be omitted. The parameter value will overwrite the - 0x22222222 value during the function prologue. */ + * This is essential for the Microblaze port and these lines must + * not be omitted. The parameter value will overwrite the + * 0x22222222 value during the function prologue. */ *pxTopOfStack = ( StackType_t ) 0x11111111; pxTopOfStack--; *pxTopOfStack = ( StackType_t ) 0x22222222; @@ -105,98 +107,98 @@ const uint32_t ulR13 = ( uint32_t ) &_SDA_BASE_; pxTopOfStack--; /* First stack an initial value for the critical section nesting. This - is initialised to zero as tasks are started with interrupts enabled. */ - *pxTopOfStack = ( StackType_t ) 0x00; /* R0. */ + * is initialised to zero as tasks are started with interrupts enabled. */ + *pxTopOfStack = ( StackType_t ) 0x00; /* R0. */ /* Place an initial value for all the general purpose registers. */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) ulR2; /* R2 - small data area. */ + *pxTopOfStack = ( StackType_t ) ulR2; /* R2 - small data area. */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x03; /* R3. */ + *pxTopOfStack = ( StackType_t ) 0x03; /* R3. */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x04; /* R4. */ + *pxTopOfStack = ( StackType_t ) 0x04; /* R4. */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) pvParameters;/* R5 contains the function call parameters. */ + *pxTopOfStack = ( StackType_t ) pvParameters; /* R5 contains the function call parameters. */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x06; /* R6. */ + *pxTopOfStack = ( StackType_t ) 0x06; /* R6. */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x07; /* R7. */ + *pxTopOfStack = ( StackType_t ) 0x07; /* R7. */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x08; /* R8. */ + *pxTopOfStack = ( StackType_t ) 0x08; /* R8. */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x09; /* R9. */ + *pxTopOfStack = ( StackType_t ) 0x09; /* R9. */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x0a; /* R10. */ + *pxTopOfStack = ( StackType_t ) 0x0a; /* R10. */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x0b; /* R11. */ + *pxTopOfStack = ( StackType_t ) 0x0b; /* R11. */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x0c; /* R12. */ + *pxTopOfStack = ( StackType_t ) 0x0c; /* R12. */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) ulR13; /* R13 - small data read write area. */ + *pxTopOfStack = ( StackType_t ) ulR13; /* R13 - small data read write area. */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) pxCode; /* R14. */ + *pxTopOfStack = ( StackType_t ) pxCode; /* R14. */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x0f; /* R15. */ + *pxTopOfStack = ( StackType_t ) 0x0f; /* R15. */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x10; /* R16. */ + *pxTopOfStack = ( StackType_t ) 0x10; /* R16. */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x11; /* R17. */ + *pxTopOfStack = ( StackType_t ) 0x11; /* R17. */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x12; /* R18. */ + *pxTopOfStack = ( StackType_t ) 0x12; /* R18. */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x13; /* R19. */ + *pxTopOfStack = ( StackType_t ) 0x13; /* R19. */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x14; /* R20. */ + *pxTopOfStack = ( StackType_t ) 0x14; /* R20. */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x15; /* R21. */ + *pxTopOfStack = ( StackType_t ) 0x15; /* R21. */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x16; /* R22. */ + *pxTopOfStack = ( StackType_t ) 0x16; /* R22. */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x17; /* R23. */ + *pxTopOfStack = ( StackType_t ) 0x17; /* R23. */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x18; /* R24. */ + *pxTopOfStack = ( StackType_t ) 0x18; /* R24. */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x19; /* R25. */ + *pxTopOfStack = ( StackType_t ) 0x19; /* R25. */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x1a; /* R26. */ + *pxTopOfStack = ( StackType_t ) 0x1a; /* R26. */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x1b; /* R27. */ + *pxTopOfStack = ( StackType_t ) 0x1b; /* R27. */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x1c; /* R28. */ + *pxTopOfStack = ( StackType_t ) 0x1c; /* R28. */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x1d; /* R29. */ + *pxTopOfStack = ( StackType_t ) 0x1d; /* R29. */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x1e; /* R30. */ + *pxTopOfStack = ( StackType_t ) 0x1e; /* R30. */ pxTopOfStack--; /* The MSR is stacked between R30 and R31. */ *pxTopOfStack = portINITIAL_MSR_STATE; pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x1f; /* R31. */ + *pxTopOfStack = ( StackType_t ) 0x1f; /* R31. */ pxTopOfStack--; /* Return a pointer to the top of the stack we have generated so this can - be stored in the task control block for the task. */ + * be stored in the task control block for the task. */ return pxTopOfStack; } /*-----------------------------------------------------------*/ BaseType_t xPortStartScheduler( void ) { -extern void ( __FreeRTOS_interrupt_Handler )( void ); -extern void ( vStartFirstTask )( void ); + extern void( __FreeRTOS_interrupt_Handler )( void ); + extern void( vStartFirstTask )( void ); /* Setup the FreeRTOS interrupt handler. Code copied from crt0.s. */ - asm volatile ( "la r6, r0, __FreeRTOS_interrupt_handler \n\t" \ - "sw r6, r1, r0 \n\t" \ - "lhu r7, r1, r0 \n\t" \ - "shi r7, r0, 0x12 \n\t" \ - "shi r6, r0, 0x16 " ); + asm volatile ( "la r6, r0, __FreeRTOS_interrupt_handler \n\t" \ + "sw r6, r1, r0 \n\t" \ + "lhu r7, r1, r0 \n\t" \ + "shi r7, r0, 0x12 \n\t" \ + "shi r6, r0, 0x16 " ); /* Setup the hardware to generate the tick. Interrupts are disabled when - this function is called. */ + * this function is called. */ prvSetupTimerInterrupt(); /* Allocate the stack to be used by the interrupt handler. */ @@ -229,16 +231,17 @@ void vPortEndScheduler( void ) */ void vPortYield( void ) { -extern void VPortYieldASM( void ); + extern void VPortYieldASM( void ); /* Perform the context switch in a critical section to assure it is - not interrupted by the tick ISR. It is not a problem to do this as - each task maintains it's own interrupt status. */ + * not interrupted by the tick ISR. It is not a problem to do this as + * each task maintains it's own interrupt status. */ portENTER_CRITICAL(); - /* Jump directly to the yield function to ensure there is no - compiler generated prologue code. */ - asm volatile ( "bralid r14, VPortYieldASM \n\t" \ - "or r0, r0, r0 \n\t" ); + + /* Jump directly to the yield function to ensure there is no + * compiler generated prologue code. */ + asm volatile ( "bralid r14, VPortYieldASM \n\t" \ + "or r0, r0, r0 \n\t" ); portEXIT_CRITICAL(); } /*-----------------------------------------------------------*/ @@ -248,25 +251,25 @@ extern void VPortYieldASM( void ); */ static void prvSetupTimerInterrupt( void ) { -XTmrCtr xTimer; -const uint32_t ulCounterValue = configCPU_CLOCK_HZ / configTICK_RATE_HZ; -UBaseType_t uxMask; + XTmrCtr xTimer; + const uint32_t ulCounterValue = configCPU_CLOCK_HZ / configTICK_RATE_HZ; + UBaseType_t uxMask; /* The OPB timer1 is used to generate the tick. Use the provided library - functions to enable the timer and set the tick frequency. */ + * functions to enable the timer and set the tick frequency. */ XTmrCtr_mDisable( XPAR_OPB_TIMER_1_BASEADDR, XPAR_OPB_TIMER_1_DEVICE_ID ); XTmrCtr_Initialize( &xTimer, XPAR_OPB_TIMER_1_DEVICE_ID ); XTmrCtr_mSetLoadReg( XPAR_OPB_TIMER_1_BASEADDR, portCOUNTER_0, ulCounterValue ); - XTmrCtr_mSetControlStatusReg( XPAR_OPB_TIMER_1_BASEADDR, portCOUNTER_0, XTC_CSR_LOAD_MASK | XTC_CSR_INT_OCCURED_MASK ); + XTmrCtr_mSetControlStatusReg( XPAR_OPB_TIMER_1_BASEADDR, portCOUNTER_0, XTC_CSR_LOAD_MASK | XTC_CSR_INT_occurred_MASK ); /* Set the timer interrupt enable bit while maintaining the other bit - states. */ + * states. */ uxMask = XIntc_In32( ( XPAR_OPB_INTC_0_BASEADDR + XIN_IER_OFFSET ) ); uxMask |= XPAR_OPB_TIMER_1_INTERRUPT_MASK; XIntc_Out32( ( XPAR_OPB_INTC_0_BASEADDR + XIN_IER_OFFSET ), ( uxMask ) ); XTmrCtr_Start( &xTimer, XPAR_OPB_TIMER_1_DEVICE_ID ); - XTmrCtr_mSetControlStatusReg(XPAR_OPB_TIMER_1_BASEADDR, portCOUNTER_0, XTC_CSR_ENABLE_TMR_MASK | XTC_CSR_ENABLE_INT_MASK | XTC_CSR_AUTO_RELOAD_MASK | XTC_CSR_DOWN_COUNT_MASK | XTC_CSR_INT_OCCURED_MASK ); + XTmrCtr_mSetControlStatusReg( XPAR_OPB_TIMER_1_BASEADDR, portCOUNTER_0, XTC_CSR_ENABLE_TMR_MASK | XTC_CSR_ENABLE_INT_MASK | XTC_CSR_AUTO_RELOAD_MASK | XTC_CSR_DOWN_COUNT_MASK | XTC_CSR_INT_occurred_MASK ); XIntc_mAckIntr( XPAR_INTC_SINGLE_BASEADDR, 1 ); } /*-----------------------------------------------------------*/ @@ -279,15 +282,15 @@ UBaseType_t uxMask; */ void vTaskISRHandler( void ) { -static uint32_t ulPending; + static uint32_t ulPending; /* Which interrupts are pending? */ ulPending = XIntc_In32( ( XPAR_INTC_SINGLE_BASEADDR + XIN_IVR_OFFSET ) ); if( ulPending < XPAR_INTC_MAX_NUM_INTR_INPUTS ) { - static XIntc_VectorTableEntry *pxTablePtr; - static XIntc_Config *pxConfig; + static XIntc_VectorTableEntry * pxTablePtr; + static XIntc_Config * pxConfig; static uint32_t ulInterruptMask; ulInterruptMask = ( uint32_t ) 1 << ulPending; @@ -296,7 +299,8 @@ static uint32_t ulPending; pxConfig = &XIntc_ConfigTable[ ( uint32_t ) XPAR_INTC_SINGLE_DEVICE_ID ]; pxTablePtr = &( pxConfig->HandlerTable[ ulPending ] ); - if( pxConfig->AckBeforeService & ( ulInterruptMask ) ) + + if( pxConfig->AckBeforeService & ( ulInterruptMask ) ) { XIntc_mAckIntr( pxConfig->BaseAddress, ulInterruptMask ); pxTablePtr->Handler( pxTablePtr->CallBackRef ); @@ -313,9 +317,9 @@ static uint32_t ulPending; /* * Handler for the timer interrupt. */ -void vTickISR( void *pvBaseAddress ) +void vTickISR( void * pvBaseAddress ) { -uint32_t ulCSR; + uint32_t ulCSR; /* Increment the RTOS tick - this might cause a task to unblock. */ if( xTaskIncrementTick() != pdFALSE ) @@ -324,7 +328,7 @@ uint32_t ulCSR; } /* Clear the timer interrupt */ - ulCSR = XTmrCtr_mGetControlStatusReg(XPAR_OPB_TIMER_1_BASEADDR, 0); + ulCSR = XTmrCtr_mGetControlStatusReg( XPAR_OPB_TIMER_1_BASEADDR, 0 ); XTmrCtr_mSetControlStatusReg( XPAR_OPB_TIMER_1_BASEADDR, portCOUNTER_0, ulCSR ); } /*-----------------------------------------------------------*/ diff --git a/Source/portable/GCC/MicroBlaze/portasm.s b/Source/portable/GCC/MicroBlaze/portasm.s index 1ae0ef751..77d5de15a 100644 --- a/Source/portable/GCC/MicroBlaze/portasm.s +++ b/Source/portable/GCC/MicroBlaze/portasm.s @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/Source/portable/GCC/MicroBlaze/portmacro.h b/Source/portable/GCC/MicroBlaze/portmacro.h index d741b16f7..69949aa62 100644 --- a/Source/portable/GCC/MicroBlaze/portmacro.h +++ b/Source/portable/GCC/MicroBlaze/portmacro.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -46,28 +46,28 @@ */ /* Type definitions. */ -#define portCHAR char -#define portFLOAT float -#define portDOUBLE double -#define portLONG long -#define portSHORT short -#define portSTACK_TYPE uint32_t -#define portBASE_TYPE long - -typedef portSTACK_TYPE StackType_t; -typedef long BaseType_t; -typedef unsigned long UBaseType_t; - -#if( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS ) - typedef uint16_t TickType_t; - #define portMAX_DELAY ( TickType_t ) 0xffff +#define portCHAR char +#define portFLOAT float +#define portDOUBLE double +#define portLONG long +#define portSHORT short +#define portSTACK_TYPE uint32_t +#define portBASE_TYPE long + +typedef portSTACK_TYPE StackType_t; +typedef long BaseType_t; +typedef unsigned long UBaseType_t; + +#if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS ) + typedef uint16_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffff #elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS ) - typedef uint32_t TickType_t; - #define portMAX_DELAY ( TickType_t ) 0xffffffffUL + typedef uint32_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffffffffUL - /* 32-bit tick type on a 32-bit architecture, so reads of the tick count do - not need to be guarded with a critical section. */ - #define portTICK_TYPE_IS_ATOMIC 1 +/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do + * not need to be guarded with a critical section. */ + #define portTICK_TYPE_IS_ATOMIC 1 #else #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width. #endif @@ -83,46 +83,48 @@ void microblaze_enable_interrupts( void ); /* Critical section macros. */ void vPortEnterCritical( void ); void vPortExitCritical( void ); -#define portENTER_CRITICAL() { \ - extern UBaseType_t uxCriticalNesting; \ - microblaze_disable_interrupts(); \ - uxCriticalNesting++; \ - } - -#define portEXIT_CRITICAL() { \ - extern UBaseType_t uxCriticalNesting; \ - /* Interrupts are disabled, so we can */ \ - /* access the variable directly. */ \ - uxCriticalNesting--; \ - if( uxCriticalNesting == 0 ) \ - { \ - /* The nesting has unwound and we \ - can enable interrupts again. */ \ - portENABLE_INTERRUPTS(); \ - } \ - } +#define portENTER_CRITICAL() \ + { \ + extern UBaseType_t uxCriticalNesting; \ + microblaze_disable_interrupts(); \ + uxCriticalNesting++; \ + } + +#define portEXIT_CRITICAL() \ + { \ + extern UBaseType_t uxCriticalNesting; \ + /* Interrupts are disabled, so we can */ \ + /* access the variable directly. */ \ + uxCriticalNesting--; \ + if( uxCriticalNesting == 0 ) \ + { \ + /* The nesting has unwound and we \ + * can enable interrupts again. */ \ + portENABLE_INTERRUPTS(); \ + } \ + } /*-----------------------------------------------------------*/ /* Task utilities. */ void vPortYield( void ); -#define portYIELD() vPortYield() +#define portYIELD() vPortYield() void vTaskSwitchContext(); -#define portYIELD_FROM_ISR() vTaskSwitchContext() +#define portYIELD_FROM_ISR() vTaskSwitchContext() /*-----------------------------------------------------------*/ /* Hardware specifics. */ -#define portBYTE_ALIGNMENT 4 -#define portSTACK_GROWTH ( -1 ) -#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) -#define portNOP() asm volatile ( "NOP" ) -#define portMEMORY_BARRIER() asm volatile ( "" ::: "memory" ) +#define portBYTE_ALIGNMENT 4 +#define portSTACK_GROWTH ( -1 ) +#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) +#define portNOP() asm volatile ( "NOP" ) +#define portMEMORY_BARRIER() asm volatile ( "" ::: "memory" ) /*-----------------------------------------------------------*/ /* Task function macros as described on the FreeRTOS.org WEB site. */ -#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters ) -#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters ) +#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters ) +#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters ) /* *INDENT-OFF* */ #ifdef __cplusplus diff --git a/Source/portable/GCC/MicroBlazeV8/port.c b/Source/portable/GCC/MicroBlazeV8/port.c index a542675c0..c6ba9514f 100644 --- a/Source/portable/GCC/MicroBlazeV8/port.c +++ b/Source/portable/GCC/MicroBlazeV8/port.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -27,8 +27,8 @@ */ /*----------------------------------------------------------- - * Implementation of functions defined in portable.h for the MicroBlaze port. - *----------------------------------------------------------*/ +* Implementation of functions defined in portable.h for the MicroBlaze port. +*----------------------------------------------------------*/ /* Scheduler includes. */ @@ -44,20 +44,20 @@ #include /* Tasks are started with a critical section nesting of 0 - however, prior to -the scheduler being commenced interrupts should not be enabled, so the critical -nesting variable is initialised to a non-zero value. */ -#define portINITIAL_NESTING_VALUE ( 0xff ) + * the scheduler being commenced interrupts should not be enabled, so the critical + * nesting variable is initialised to a non-zero value. */ +#define portINITIAL_NESTING_VALUE ( 0xff ) /* The bit within the MSR register that enabled/disables interrupts and -exceptions respectively. */ -#define portMSR_IE ( 0x02U ) -#define portMSR_EE ( 0x100U ) + * exceptions respectively. */ +#define portMSR_IE ( 0x02U ) +#define portMSR_EE ( 0x100U ) /* If the floating point unit is included in the MicroBlaze build, then the -FSR register is saved as part of the task context. portINITIAL_FSR is the value -given to the FSR register when the initial context is set up for a task being -created. */ -#define portINITIAL_FSR ( 0U ) + * FSR register is saved as part of the task context. portINITIAL_FSR is the value + * given to the FSR register when the initial context is set up for a task being + * created. */ +#define portINITIAL_FSR ( 0U ) /*-----------------------------------------------------------*/ /* @@ -73,27 +73,27 @@ static int32_t prvEnsureInterruptControllerIsInitialised( void ); /*-----------------------------------------------------------*/ /* Counts the nesting depth of calls to portENTER_CRITICAL(). Each task -maintains its own count, so this variable is saved as part of the task -context. */ + * maintains its own count, so this variable is saved as part of the task + * context. */ volatile UBaseType_t uxCriticalNesting = portINITIAL_NESTING_VALUE; /* This port uses a separate stack for interrupts. This prevents the stack of -every task needing to be large enough to hold an entire interrupt stack on top -of the task stack. */ -uint32_t *pulISRStack; + * every task needing to be large enough to hold an entire interrupt stack on top + * of the task stack. */ +uint32_t * pulISRStack; /* If an interrupt requests a context switch, then ulTaskSwitchRequested will -get set to 1. ulTaskSwitchRequested is inspected just before the main interrupt -handler exits. If, at that time, ulTaskSwitchRequested is set to 1, the kernel -will call vTaskSwitchContext() to ensure the task that runs immediately after -the interrupt exists is the highest priority task that is able to run. This is -an unusual mechanism, but is used for this port because a single interrupt can -cause the servicing of multiple peripherals - and it is inefficient to call -vTaskSwitchContext() multiple times as each peripheral is serviced. */ + * get set to 1. ulTaskSwitchRequested is inspected just before the main interrupt + * handler exits. If, at that time, ulTaskSwitchRequested is set to 1, the kernel + * will call vTaskSwitchContext() to ensure the task that runs immediately after + * the interrupt exists is the highest priority task that is able to run. This is + * an unusual mechanism, but is used for this port because a single interrupt can + * cause the servicing of multiple peripherals - and it is inefficient to call + * vTaskSwitchContext() multiple times as each peripheral is serviced. */ volatile uint32_t ulTaskSwitchRequested = 0UL; /* The instance of the interrupt controller used by this port. This is required -by the Xilinx library API functions. */ + * by the Xilinx library API functions. */ static XIntc xInterruptControllerInstance; /*-----------------------------------------------------------*/ @@ -104,16 +104,18 @@ static XIntc xInterruptControllerInstance; * * See the portable.h header file. */ -StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters ) +StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, + TaskFunction_t pxCode, + void * pvParameters ) { -extern void * _SDA2_BASE_; -extern void * _SDA_BASE_; -const uint32_t ulR2 = ( uint32_t ) &_SDA2_BASE_; -const uint32_t ulR13 = ( uint32_t ) &_SDA_BASE_; + extern void * _SDA2_BASE_; + extern void * _SDA_BASE_; + const uint32_t ulR2 = ( uint32_t ) &_SDA2_BASE_; + const uint32_t ulR13 = ( uint32_t ) &_SDA_BASE_; /* Place a few bytes of known values on the bottom of the stack. - This is essential for the Microblaze port and these lines must - not be omitted. */ + * This is essential for the Microblaze port and these lines must + * not be omitted. */ *pxTopOfStack = ( StackType_t ) 0x00000000; pxTopOfStack--; *pxTopOfStack = ( StackType_t ) 0x00000000; @@ -121,18 +123,18 @@ const uint32_t ulR13 = ( uint32_t ) &_SDA_BASE_; *pxTopOfStack = ( StackType_t ) 0x00000000; pxTopOfStack--; - #if( XPAR_MICROBLAZE_USE_FPU != 0 ) + #if ( XPAR_MICROBLAZE_USE_FPU != 0 ) /* The FSR value placed in the initial task context is just 0. */ *pxTopOfStack = portINITIAL_FSR; pxTopOfStack--; #endif /* The MSR value placed in the initial task context should have interrupts - disabled. Each task will enable interrupts automatically when it enters - the running state for the first time. */ + * disabled. Each task will enable interrupts automatically when it enters + * the running state for the first time. */ *pxTopOfStack = mfmsr() & ~portMSR_IE; - #if( MICROBLAZE_EXCEPTIONS_ENABLED == 1 ) + #if ( MICROBLAZE_EXCEPTIONS_ENABLED == 1 ) { /* Ensure exceptions are enabled for the task. */ *pxTopOfStack |= portMSR_EE; @@ -142,7 +144,7 @@ const uint32_t ulR13 = ( uint32_t ) &_SDA_BASE_; pxTopOfStack--; /* First stack an initial value for the critical section nesting. This - is initialised to zero. */ + * is initialised to zero. */ *pxTopOfStack = ( StackType_t ) 0x00; /* R0 is always zero. */ @@ -150,33 +152,33 @@ const uint32_t ulR13 = ( uint32_t ) &_SDA_BASE_; /* Place an initial value for all the general purpose registers. */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) ulR2; /* R2 - read only small data area. */ + *pxTopOfStack = ( StackType_t ) ulR2; /* R2 - read only small data area. */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x03; /* R3 - return values and temporaries. */ + *pxTopOfStack = ( StackType_t ) 0x03; /* R3 - return values and temporaries. */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x04; /* R4 - return values and temporaries. */ + *pxTopOfStack = ( StackType_t ) 0x04; /* R4 - return values and temporaries. */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) pvParameters;/* R5 contains the function call parameters. */ + *pxTopOfStack = ( StackType_t ) pvParameters; /* R5 contains the function call parameters. */ #ifdef portPRE_LOAD_STACK_FOR_DEBUGGING pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x06; /* R6 - other parameters and temporaries. Used as the return address from vPortTaskEntryPoint. */ + *pxTopOfStack = ( StackType_t ) 0x06; /* R6 - other parameters and temporaries. Used as the return address from vPortTaskEntryPoint. */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x07; /* R7 - other parameters and temporaries. */ + *pxTopOfStack = ( StackType_t ) 0x07; /* R7 - other parameters and temporaries. */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x08; /* R8 - other parameters and temporaries. */ + *pxTopOfStack = ( StackType_t ) 0x08; /* R8 - other parameters and temporaries. */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x09; /* R9 - other parameters and temporaries. */ + *pxTopOfStack = ( StackType_t ) 0x09; /* R9 - other parameters and temporaries. */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x0a; /* R10 - other parameters and temporaries. */ + *pxTopOfStack = ( StackType_t ) 0x0a; /* R10 - other parameters and temporaries. */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x0b; /* R11 - temporaries. */ + *pxTopOfStack = ( StackType_t ) 0x0b; /* R11 - temporaries. */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x0c; /* R12 - temporaries. */ + *pxTopOfStack = ( StackType_t ) 0x0c; /* R12 - temporaries. */ pxTopOfStack--; - #else - pxTopOfStack-= 8; - #endif + #else /* ifdef portPRE_LOAD_STACK_FOR_DEBUGGING */ + pxTopOfStack -= 8; + #endif /* ifdef portPRE_LOAD_STACK_FOR_DEBUGGING */ *pxTopOfStack = ( StackType_t ) ulR13; /* R13 - read/write small data area. */ pxTopOfStack--; @@ -186,79 +188,79 @@ const uint32_t ulR13 = ( uint32_t ) &_SDA_BASE_; #ifdef portPRE_LOAD_STACK_FOR_DEBUGGING pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x10; /* R16 - return address for trap (debugger). */ + *pxTopOfStack = ( StackType_t ) 0x10; /* R16 - return address for trap (debugger). */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x11; /* R17 - return address for exceptions, if configured. */ + *pxTopOfStack = ( StackType_t ) 0x11; /* R17 - return address for exceptions, if configured. */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x12; /* R18 - reserved for assembler and compiler temporaries. */ + *pxTopOfStack = ( StackType_t ) 0x12; /* R18 - reserved for assembler and compiler temporaries. */ pxTopOfStack--; #else pxTopOfStack -= 4; #endif - *pxTopOfStack = ( StackType_t ) 0x00; /* R19 - must be saved across function calls. Callee-save. Seems to be interpreted as the frame pointer. */ + *pxTopOfStack = ( StackType_t ) 0x00; /* R19 - must be saved across function calls. Callee-save. Seems to be interpreted as the frame pointer. */ #ifdef portPRE_LOAD_STACK_FOR_DEBUGGING pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x14; /* R20 - reserved for storing a pointer to the Global Offset Table (GOT) in Position Independent Code (PIC). Non-volatile in non-PIC code. Must be saved across function calls. Callee-save. Not used by FreeRTOS. */ + *pxTopOfStack = ( StackType_t ) 0x14; /* R20 - reserved for storing a pointer to the Global Offset Table (GOT) in Position Independent Code (PIC). Non-volatile in non-PIC code. Must be saved across function calls. Callee-save. Not used by FreeRTOS. */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x15; /* R21 - must be saved across function calls. Callee-save. */ + *pxTopOfStack = ( StackType_t ) 0x15; /* R21 - must be saved across function calls. Callee-save. */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x16; /* R22 - must be saved across function calls. Callee-save. */ + *pxTopOfStack = ( StackType_t ) 0x16; /* R22 - must be saved across function calls. Callee-save. */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x17; /* R23 - must be saved across function calls. Callee-save. */ + *pxTopOfStack = ( StackType_t ) 0x17; /* R23 - must be saved across function calls. Callee-save. */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x18; /* R24 - must be saved across function calls. Callee-save. */ + *pxTopOfStack = ( StackType_t ) 0x18; /* R24 - must be saved across function calls. Callee-save. */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x19; /* R25 - must be saved across function calls. Callee-save. */ + *pxTopOfStack = ( StackType_t ) 0x19; /* R25 - must be saved across function calls. Callee-save. */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x1a; /* R26 - must be saved across function calls. Callee-save. */ + *pxTopOfStack = ( StackType_t ) 0x1a; /* R26 - must be saved across function calls. Callee-save. */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x1b; /* R27 - must be saved across function calls. Callee-save. */ + *pxTopOfStack = ( StackType_t ) 0x1b; /* R27 - must be saved across function calls. Callee-save. */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x1c; /* R28 - must be saved across function calls. Callee-save. */ + *pxTopOfStack = ( StackType_t ) 0x1c; /* R28 - must be saved across function calls. Callee-save. */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x1d; /* R29 - must be saved across function calls. Callee-save. */ + *pxTopOfStack = ( StackType_t ) 0x1d; /* R29 - must be saved across function calls. Callee-save. */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x1e; /* R30 - must be saved across function calls. Callee-save. */ + *pxTopOfStack = ( StackType_t ) 0x1e; /* R30 - must be saved across function calls. Callee-save. */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x1f; /* R31 - must be saved across function calls. Callee-save. */ + *pxTopOfStack = ( StackType_t ) 0x1f; /* R31 - must be saved across function calls. Callee-save. */ pxTopOfStack--; - #else + #else /* ifdef portPRE_LOAD_STACK_FOR_DEBUGGING */ pxTopOfStack -= 13; - #endif + #endif /* ifdef portPRE_LOAD_STACK_FOR_DEBUGGING */ /* Return a pointer to the top of the stack that has been generated so this - can be stored in the task control block for the task. */ + * can be stored in the task control block for the task. */ return pxTopOfStack; } /*-----------------------------------------------------------*/ BaseType_t xPortStartScheduler( void ) { -extern void ( vPortStartFirstTask )( void ); -extern uint32_t _stack[]; + extern void( vPortStartFirstTask )( void ); + extern uint32_t _stack[]; /* Setup the hardware to generate the tick. Interrupts are disabled when - this function is called. - - This port uses an application defined callback function to install the tick - interrupt handler because the kernel will run on lots of different - MicroBlaze and FPGA configurations - not all of which will have the same - timer peripherals defined or available. An example definition of - vApplicationSetupTimerInterrupt() is provided in the official demo - application that accompanies this port. */ + * this function is called. + * + * This port uses an application defined callback function to install the tick + * interrupt handler because the kernel will run on lots of different + * MicroBlaze and FPGA configurations - not all of which will have the same + * timer peripherals defined or available. An example definition of + * vApplicationSetupTimerInterrupt() is provided in the official demo + * application that accompanies this port. */ vApplicationSetupTimerInterrupt(); /* Reuse the stack from main() as the stack for the interrupts/exceptions. */ pulISRStack = ( uint32_t * ) _stack; /* Ensure there is enough space for the functions called from the interrupt - service routines to write back into the stack frame of the caller. */ + * service routines to write back into the stack frame of the caller. */ pulISRStack -= 2; /* Restore the context of the first task that is going to run. From here - on, the created tasks will be executing. */ + * on, the created tasks will be executing. */ vPortStartFirstTask(); /* Should not get here as the tasks are now running! */ @@ -269,7 +271,7 @@ extern uint32_t _stack[]; void vPortEndScheduler( void ) { /* Not implemented in ports where there is nothing to return to. - Artificially force an assert. */ + * Artificially force an assert. */ configASSERT( uxCriticalNesting == 1000UL ); } /*-----------------------------------------------------------*/ @@ -279,17 +281,17 @@ void vPortEndScheduler( void ) */ void vPortYield( void ) { -extern void VPortYieldASM( void ); + extern void VPortYieldASM( void ); /* Perform the context switch in a critical section to assure it is - not interrupted by the tick ISR. It is not a problem to do this as - each task maintains its own interrupt status. */ + * not interrupted by the tick ISR. It is not a problem to do this as + * each task maintains its own interrupt status. */ portENTER_CRITICAL(); { /* Jump directly to the yield function to ensure there is no - compiler generated prologue code. */ - asm volatile ( "bralid r14, VPortYieldASM \n\t" \ - "or r0, r0, r0 \n\t" ); + * compiler generated prologue code. */ + asm volatile ( "bralid r14, VPortYieldASM \n\t" \ + "or r0, r0, r0 \n\t" ); } portEXIT_CRITICAL(); } @@ -297,12 +299,13 @@ extern void VPortYieldASM( void ); void vPortEnableInterrupt( uint8_t ucInterruptID ) { -int32_t lReturn; + int32_t lReturn; /* An API function is provided to enable an interrupt in the interrupt - controller because the interrupt controller instance variable is private - to this file. */ + * controller because the interrupt controller instance variable is private + * to this file. */ lReturn = prvEnsureInterruptControllerIsInitialised(); + if( lReturn == pdPASS ) { XIntc_Enable( &xInterruptControllerInstance, ucInterruptID ); @@ -314,11 +317,11 @@ int32_t lReturn; void vPortDisableInterrupt( uint8_t ucInterruptID ) { -int32_t lReturn; + int32_t lReturn; /* An API function is provided to disable an interrupt in the interrupt - controller because the interrupt controller instance variable is private - to this file. */ + * controller because the interrupt controller instance variable is private + * to this file. */ lReturn = prvEnsureInterruptControllerIsInitialised(); if( lReturn == pdPASS ) @@ -330,12 +333,14 @@ int32_t lReturn; } /*-----------------------------------------------------------*/ -BaseType_t xPortInstallInterruptHandler( uint8_t ucInterruptID, XInterruptHandler pxHandler, void *pvCallBackRef ) +BaseType_t xPortInstallInterruptHandler( uint8_t ucInterruptID, + XInterruptHandler pxHandler, + void * pvCallBackRef ) { -int32_t lReturn; + int32_t lReturn; /* An API function is provided to install an interrupt handler because the - interrupt controller instance variable is private to this file. */ + * interrupt controller instance variable is private to this file. */ lReturn = prvEnsureInterruptControllerIsInitialised(); @@ -357,11 +362,11 @@ int32_t lReturn; static int32_t prvEnsureInterruptControllerIsInitialised( void ) { -static int32_t lInterruptControllerInitialised = pdFALSE; -int32_t lReturn; + static int32_t lInterruptControllerInitialised = pdFALSE; + int32_t lReturn; /* Ensure the interrupt controller instance variable is initialised before - it is used, and that the initialisation only happens once. */ + * it is used, and that the initialisation only happens once. */ if( lInterruptControllerInitialised != pdTRUE ) { lReturn = prvInitialiseInterruptController(); @@ -384,19 +389,19 @@ int32_t lReturn; * Handler for the timer interrupt. This is the handler that the application * defined callback function vApplicationSetupTimerInterrupt() should install. */ -void vPortTickISR( void *pvUnused ) +void vPortTickISR( void * pvUnused ) { -extern void vApplicationClearTimerInterrupt( void ); + extern void vApplicationClearTimerInterrupt( void ); /* Ensure the unused parameter does not generate a compiler warning. */ ( void ) pvUnused; /* This port uses an application defined callback function to clear the tick - interrupt because the kernel will run on lots of different MicroBlaze and - FPGA configurations - not all of which will have the same timer peripherals - defined or available. An example definition of - vApplicationClearTimerInterrupt() is provided in the official demo - application that accompanies this port. */ + * interrupt because the kernel will run on lots of different MicroBlaze and + * FPGA configurations - not all of which will have the same timer peripherals + * defined or available. An example definition of + * vApplicationClearTimerInterrupt() is provided in the official demo + * application that accompanies this port. */ vApplicationClearTimerInterrupt(); /* Increment the RTOS tick - this might cause a task to unblock. */ @@ -410,7 +415,7 @@ extern void vApplicationClearTimerInterrupt( void ); static int32_t prvInitialiseInterruptController( void ) { -int32_t lStatus; + int32_t lStatus; lStatus = XIntc_Initialize( &xInterruptControllerInstance, configINTERRUPT_CONTROLLER_TO_USE ); @@ -423,8 +428,8 @@ int32_t lStatus; XIntc_SetIntrSvcOption( xInterruptControllerInstance.BaseAddress, XIN_SVC_ALL_ISRS_OPTION ); /* Install exception handlers if the MicroBlaze is configured to handle - exceptions, and the application defined constant - configINSTALL_EXCEPTION_HANDLERS is set to 1. */ + * exceptions, and the application defined constant + * configINSTALL_EXCEPTION_HANDLERS is set to 1. */ #if ( MICROBLAZE_EXCEPTIONS_ENABLED == 1 ) && ( configINSTALL_EXCEPTION_HANDLERS == 1 ) { vPortExceptionsInstallHandlers(); @@ -432,7 +437,7 @@ int32_t lStatus; #endif /* MICROBLAZE_EXCEPTIONS_ENABLED */ /* Start the interrupt controller. Interrupts are enabled when the - scheduler starts. */ + * scheduler starts. */ lStatus = XIntc_Start( &xInterruptControllerInstance, XIN_REAL_MODE ); if( lStatus == XST_SUCCESS ) diff --git a/Source/portable/GCC/MicroBlazeV8/port_exceptions.c b/Source/portable/GCC/MicroBlazeV8/port_exceptions.c index 2c6221dc5..e8cf8275f 100644 --- a/Source/portable/GCC/MicroBlazeV8/port_exceptions.c +++ b/Source/portable/GCC/MicroBlazeV8/port_exceptions.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -35,246 +35,244 @@ #include /* The Xilinx library defined exception entry point stacks a number of -registers. These definitions are offsets from the stack pointer to the various -stacked register values. */ -#define portexR3_STACK_OFFSET 4 -#define portexR4_STACK_OFFSET 5 -#define portexR5_STACK_OFFSET 6 -#define portexR6_STACK_OFFSET 7 -#define portexR7_STACK_OFFSET 8 -#define portexR8_STACK_OFFSET 9 -#define portexR9_STACK_OFFSET 10 -#define portexR10_STACK_OFFSET 11 -#define portexR11_STACK_OFFSET 12 -#define portexR12_STACK_OFFSET 13 -#define portexR15_STACK_OFFSET 16 -#define portexR18_STACK_OFFSET 19 -#define portexMSR_STACK_OFFSET 20 -#define portexR19_STACK_OFFSET -1 + * registers. These definitions are offsets from the stack pointer to the various + * stacked register values. */ +#define portexR3_STACK_OFFSET 4 +#define portexR4_STACK_OFFSET 5 +#define portexR5_STACK_OFFSET 6 +#define portexR6_STACK_OFFSET 7 +#define portexR7_STACK_OFFSET 8 +#define portexR8_STACK_OFFSET 9 +#define portexR9_STACK_OFFSET 10 +#define portexR10_STACK_OFFSET 11 +#define portexR11_STACK_OFFSET 12 +#define portexR12_STACK_OFFSET 13 +#define portexR15_STACK_OFFSET 16 +#define portexR18_STACK_OFFSET 19 +#define portexMSR_STACK_OFFSET 20 +#define portexR19_STACK_OFFSET -1 /* This is defined to equal the size, in bytes, of the stack frame generated by -the Xilinx standard library exception entry point. It is required to determine -the stack pointer value prior to the exception being entered. */ -#define portexASM_HANDLER_STACK_FRAME_SIZE 84UL + * the Xilinx standard library exception entry point. It is required to determine + * the stack pointer value prior to the exception being entered. */ +#define portexASM_HANDLER_STACK_FRAME_SIZE 84UL /* The number of bytes a MicroBlaze instruction consumes. */ -#define portexINSTRUCTION_SIZE 4 +#define portexINSTRUCTION_SIZE 4 /* Exclude this entire file if the MicroBlaze is not configured to handle -exceptions, or the application defined configuration constant -configINSTALL_EXCEPTION_HANDLERS is not set to 1. */ + * exceptions, or the application defined configuration constant + * configINSTALL_EXCEPTION_HANDLERS is not set to 1. */ #if ( MICROBLAZE_EXCEPTIONS_ENABLED == 1 ) && ( configINSTALL_EXCEPTION_HANDLERS == 1 ) /* This variable is set in the exception entry code, before -vPortExceptionHandler is called. */ -uint32_t *pulStackPointerOnFunctionEntry = NULL; + * vPortExceptionHandler is called. */ + uint32_t * pulStackPointerOnFunctionEntry = NULL; /* This is the structure that is filled with the MicroBlaze context as it -existed immediately prior to the exception occurrence. A pointer to this -structure is passed into the vApplicationExceptionRegisterDump() callback -function, if one is defined. */ -static xPortRegisterDump xRegisterDump; + * existed immediately prior to the exception occurrence. A pointer to this + * structure is passed into the vApplicationExceptionRegisterDump() callback + * function, if one is defined. */ + static xPortRegisterDump xRegisterDump; /* This is the FreeRTOS exception handler that is installed for all exception -types. It is called from vPortExceptionHanlderEntry() - which is itself defined -in portasm.S. */ -void vPortExceptionHandler( void *pvExceptionID ); -extern void vPortExceptionHandlerEntry( void *pvExceptionID ); + * types. It is called from vPortExceptionHandlerEntry() - which is itself defined + * in portasm.S. */ + void vPortExceptionHandler( void * pvExceptionID ); + extern void vPortExceptionHandlerEntry( void * pvExceptionID ); /*-----------------------------------------------------------*/ /* vApplicationExceptionRegisterDump() is a callback function that the -application can optionally define to receive a populated xPortRegisterDump -structure. If the application chooses not to define a version of -vApplicationExceptionRegisterDump() then this weekly defined default -implementation will be called instead. */ -extern void vApplicationExceptionRegisterDump( xPortRegisterDump *xRegisterDump ) __attribute__((weak)); -void vApplicationExceptionRegisterDump( xPortRegisterDump *xRegisterDump ) -{ - ( void ) xRegisterDump; - - for( ;; ) + * application can optionally define to receive a populated xPortRegisterDump + * structure. If the application chooses not to define a version of + * vApplicationExceptionRegisterDump() then this weekly defined default + * implementation will be called instead. */ + extern void vApplicationExceptionRegisterDump( xPortRegisterDump * xRegisterDump ) __attribute__( ( weak ) ); + void vApplicationExceptionRegisterDump( xPortRegisterDump * xRegisterDump ) { - portNOP(); - } -} -/*-----------------------------------------------------------*/ + ( void ) xRegisterDump; -void vPortExceptionHandler( void *pvExceptionID ) -{ -extern void *pxCurrentTCB; - - /* Fill an xPortRegisterDump structure with the MicroBlaze context as it - was immediately before the exception occurrence. */ - - /* First fill in the name and handle of the task that was in the Running - state when the exception occurred. */ - xRegisterDump.xCurrentTaskHandle = pxCurrentTCB; - xRegisterDump.pcCurrentTaskName = pcTaskGetName( NULL ); - - configASSERT( pulStackPointerOnFunctionEntry ); - - /* Obtain the values of registers that were stacked prior to this function - being called, and may have changed since they were stacked. */ - xRegisterDump.ulR3 = pulStackPointerOnFunctionEntry[ portexR3_STACK_OFFSET ]; - xRegisterDump.ulR4 = pulStackPointerOnFunctionEntry[ portexR4_STACK_OFFSET ]; - xRegisterDump.ulR5 = pulStackPointerOnFunctionEntry[ portexR5_STACK_OFFSET ]; - xRegisterDump.ulR6 = pulStackPointerOnFunctionEntry[ portexR6_STACK_OFFSET ]; - xRegisterDump.ulR7 = pulStackPointerOnFunctionEntry[ portexR7_STACK_OFFSET ]; - xRegisterDump.ulR8 = pulStackPointerOnFunctionEntry[ portexR8_STACK_OFFSET ]; - xRegisterDump.ulR9 = pulStackPointerOnFunctionEntry[ portexR9_STACK_OFFSET ]; - xRegisterDump.ulR10 = pulStackPointerOnFunctionEntry[ portexR10_STACK_OFFSET ]; - xRegisterDump.ulR11 = pulStackPointerOnFunctionEntry[ portexR11_STACK_OFFSET ]; - xRegisterDump.ulR12 = pulStackPointerOnFunctionEntry[ portexR12_STACK_OFFSET ]; - xRegisterDump.ulR15_return_address_from_subroutine = pulStackPointerOnFunctionEntry[ portexR15_STACK_OFFSET ]; - xRegisterDump.ulR18 = pulStackPointerOnFunctionEntry[ portexR18_STACK_OFFSET ]; - xRegisterDump.ulR19 = pulStackPointerOnFunctionEntry[ portexR19_STACK_OFFSET ]; - xRegisterDump.ulMSR = pulStackPointerOnFunctionEntry[ portexMSR_STACK_OFFSET ]; - - /* Obtain the value of all other registers. */ - xRegisterDump.ulR2_small_data_area = mfgpr( R2 ); - xRegisterDump.ulR13_read_write_small_data_area = mfgpr( R13 ); - xRegisterDump.ulR14_return_address_from_interrupt = mfgpr( R14 ); - xRegisterDump.ulR16_return_address_from_trap = mfgpr( R16 ); - xRegisterDump.ulR17_return_address_from_exceptions = mfgpr( R17 ); - xRegisterDump.ulR20 = mfgpr( R20 ); - xRegisterDump.ulR21 = mfgpr( R21 ); - xRegisterDump.ulR22 = mfgpr( R22 ); - xRegisterDump.ulR23 = mfgpr( R23 ); - xRegisterDump.ulR24 = mfgpr( R24 ); - xRegisterDump.ulR25 = mfgpr( R25 ); - xRegisterDump.ulR26 = mfgpr( R26 ); - xRegisterDump.ulR27 = mfgpr( R27 ); - xRegisterDump.ulR28 = mfgpr( R28 ); - xRegisterDump.ulR29 = mfgpr( R29 ); - xRegisterDump.ulR30 = mfgpr( R30 ); - xRegisterDump.ulR31 = mfgpr( R31 ); - xRegisterDump.ulR1_SP = ( ( uint32_t ) pulStackPointerOnFunctionEntry ) + portexASM_HANDLER_STACK_FRAME_SIZE; - xRegisterDump.ulEAR = mfear(); - xRegisterDump.ulESR = mfesr(); - xRegisterDump.ulEDR = mfedr(); - - /* Move the saved program counter back to the instruction that was executed - when the exception occurred. This is only valid for certain types of - exception. */ - xRegisterDump.ulPC = xRegisterDump.ulR17_return_address_from_exceptions - portexINSTRUCTION_SIZE; - - #if( XPAR_MICROBLAZE_USE_FPU != 0 ) - { - xRegisterDump.ulFSR = mffsr(); + for( ; ; ) + { + portNOP(); + } } - #else - { - xRegisterDump.ulFSR = 0UL; - } - #endif +/*-----------------------------------------------------------*/ - /* Also fill in a string that describes what type of exception this is. - The string uses the same ID names as defined in the MicroBlaze standard - library exception header files. */ - switch( ( uint32_t ) pvExceptionID ) + void vPortExceptionHandler( void * pvExceptionID ) { - case XEXC_ID_FSL : + extern void * pxCurrentTCB; + + /* Fill an xPortRegisterDump structure with the MicroBlaze context as it + * was immediately before the exception occurrence. */ + + /* First fill in the name and handle of the task that was in the Running + * state when the exception occurred. */ + xRegisterDump.xCurrentTaskHandle = pxCurrentTCB; + xRegisterDump.pcCurrentTaskName = pcTaskGetName( NULL ); + + configASSERT( pulStackPointerOnFunctionEntry ); + + /* Obtain the values of registers that were stacked prior to this function + * being called, and may have changed since they were stacked. */ + xRegisterDump.ulR3 = pulStackPointerOnFunctionEntry[ portexR3_STACK_OFFSET ]; + xRegisterDump.ulR4 = pulStackPointerOnFunctionEntry[ portexR4_STACK_OFFSET ]; + xRegisterDump.ulR5 = pulStackPointerOnFunctionEntry[ portexR5_STACK_OFFSET ]; + xRegisterDump.ulR6 = pulStackPointerOnFunctionEntry[ portexR6_STACK_OFFSET ]; + xRegisterDump.ulR7 = pulStackPointerOnFunctionEntry[ portexR7_STACK_OFFSET ]; + xRegisterDump.ulR8 = pulStackPointerOnFunctionEntry[ portexR8_STACK_OFFSET ]; + xRegisterDump.ulR9 = pulStackPointerOnFunctionEntry[ portexR9_STACK_OFFSET ]; + xRegisterDump.ulR10 = pulStackPointerOnFunctionEntry[ portexR10_STACK_OFFSET ]; + xRegisterDump.ulR11 = pulStackPointerOnFunctionEntry[ portexR11_STACK_OFFSET ]; + xRegisterDump.ulR12 = pulStackPointerOnFunctionEntry[ portexR12_STACK_OFFSET ]; + xRegisterDump.ulR15_return_address_from_subroutine = pulStackPointerOnFunctionEntry[ portexR15_STACK_OFFSET ]; + xRegisterDump.ulR18 = pulStackPointerOnFunctionEntry[ portexR18_STACK_OFFSET ]; + xRegisterDump.ulR19 = pulStackPointerOnFunctionEntry[ portexR19_STACK_OFFSET ]; + xRegisterDump.ulMSR = pulStackPointerOnFunctionEntry[ portexMSR_STACK_OFFSET ]; + + /* Obtain the value of all other registers. */ + xRegisterDump.ulR2_small_data_area = mfgpr( R2 ); + xRegisterDump.ulR13_read_write_small_data_area = mfgpr( R13 ); + xRegisterDump.ulR14_return_address_from_interrupt = mfgpr( R14 ); + xRegisterDump.ulR16_return_address_from_trap = mfgpr( R16 ); + xRegisterDump.ulR17_return_address_from_exceptions = mfgpr( R17 ); + xRegisterDump.ulR20 = mfgpr( R20 ); + xRegisterDump.ulR21 = mfgpr( R21 ); + xRegisterDump.ulR22 = mfgpr( R22 ); + xRegisterDump.ulR23 = mfgpr( R23 ); + xRegisterDump.ulR24 = mfgpr( R24 ); + xRegisterDump.ulR25 = mfgpr( R25 ); + xRegisterDump.ulR26 = mfgpr( R26 ); + xRegisterDump.ulR27 = mfgpr( R27 ); + xRegisterDump.ulR28 = mfgpr( R28 ); + xRegisterDump.ulR29 = mfgpr( R29 ); + xRegisterDump.ulR30 = mfgpr( R30 ); + xRegisterDump.ulR31 = mfgpr( R31 ); + xRegisterDump.ulR1_SP = ( ( uint32_t ) pulStackPointerOnFunctionEntry ) + portexASM_HANDLER_STACK_FRAME_SIZE; + xRegisterDump.ulEAR = mfear(); + xRegisterDump.ulESR = mfesr(); + xRegisterDump.ulEDR = mfedr(); + + /* Move the saved program counter back to the instruction that was executed + * when the exception occurred. This is only valid for certain types of + * exception. */ + xRegisterDump.ulPC = xRegisterDump.ulR17_return_address_from_exceptions - portexINSTRUCTION_SIZE; + + #if ( XPAR_MICROBLAZE_USE_FPU != 0 ) + { + xRegisterDump.ulFSR = mffsr(); + } + #else + { + xRegisterDump.ulFSR = 0UL; + } + #endif + + /* Also fill in a string that describes what type of exception this is. + * The string uses the same ID names as defined in the MicroBlaze standard + * library exception header files. */ + switch( ( uint32_t ) pvExceptionID ) + { + case XEXC_ID_FSL: xRegisterDump.pcExceptionCause = ( int8_t * const ) "XEXC_ID_FSL"; break; - case XEXC_ID_UNALIGNED_ACCESS : + case XEXC_ID_UNALIGNED_ACCESS: xRegisterDump.pcExceptionCause = ( int8_t * const ) "XEXC_ID_UNALIGNED_ACCESS"; break; - case XEXC_ID_ILLEGAL_OPCODE : + case XEXC_ID_ILLEGAL_OPCODE: xRegisterDump.pcExceptionCause = ( int8_t * const ) "XEXC_ID_ILLEGAL_OPCODE"; break; - case XEXC_ID_M_AXI_I_EXCEPTION : + case XEXC_ID_M_AXI_I_EXCEPTION: xRegisterDump.pcExceptionCause = ( int8_t * const ) "XEXC_ID_M_AXI_I_EXCEPTION or XEXC_ID_IPLB_EXCEPTION"; break; - case XEXC_ID_M_AXI_D_EXCEPTION : + case XEXC_ID_M_AXI_D_EXCEPTION: xRegisterDump.pcExceptionCause = ( int8_t * const ) "XEXC_ID_M_AXI_D_EXCEPTION or XEXC_ID_DPLB_EXCEPTION"; break; - case XEXC_ID_DIV_BY_ZERO : + case XEXC_ID_DIV_BY_ZERO: xRegisterDump.pcExceptionCause = ( int8_t * const ) "XEXC_ID_DIV_BY_ZERO"; break; - case XEXC_ID_STACK_VIOLATION : + case XEXC_ID_STACK_VIOLATION: xRegisterDump.pcExceptionCause = ( int8_t * const ) "XEXC_ID_STACK_VIOLATION or XEXC_ID_MMU"; break; - #if( XPAR_MICROBLAZE_USE_FPU != 0 ) - - case XEXC_ID_FPU : + #if ( XPAR_MICROBLAZE_USE_FPU != 0 ) + case XEXC_ID_FPU: xRegisterDump.pcExceptionCause = ( int8_t * const ) "XEXC_ID_FPU see ulFSR value"; break; - - #endif /* XPAR_MICROBLAZE_USE_FPU */ + #endif /* XPAR_MICROBLAZE_USE_FPU */ + } + + /* vApplicationExceptionRegisterDump() is a callback function that the + * application can optionally define to receive the populated xPortRegisterDump + * structure. If the application chooses not to define a version of + * vApplicationExceptionRegisterDump() then the weekly defined default + * implementation within this file will be called instead. */ + vApplicationExceptionRegisterDump( &xRegisterDump ); + + /* Must not attempt to leave this function! */ + for( ; ; ) + { + portNOP(); + } } - - /* vApplicationExceptionRegisterDump() is a callback function that the - application can optionally define to receive the populated xPortRegisterDump - structure. If the application chooses not to define a version of - vApplicationExceptionRegisterDump() then the weekly defined default - implementation within this file will be called instead. */ - vApplicationExceptionRegisterDump( &xRegisterDump ); - - /* Must not attempt to leave this function! */ - for( ;; ) - { - portNOP(); - } -} /*-----------------------------------------------------------*/ -void vPortExceptionsInstallHandlers( void ) -{ -static uint32_t ulHandlersAlreadyInstalled = pdFALSE; - - if( ulHandlersAlreadyInstalled == pdFALSE ) + void vPortExceptionsInstallHandlers( void ) { - ulHandlersAlreadyInstalled = pdTRUE; + static uint32_t ulHandlersAlreadyInstalled = pdFALSE; + + if( ulHandlersAlreadyInstalled == pdFALSE ) + { + ulHandlersAlreadyInstalled = pdTRUE; - #if XPAR_MICROBLAZE_UNALIGNED_EXCEPTIONS == 1 - microblaze_register_exception_handler( XEXC_ID_UNALIGNED_ACCESS, vPortExceptionHandlerEntry, ( void * ) XEXC_ID_UNALIGNED_ACCESS ); - #endif /* XPAR_MICROBLAZE_UNALIGNED_EXCEPTIONS*/ + #if XPAR_MICROBLAZE_UNALIGNED_EXCEPTIONS == 1 + microblaze_register_exception_handler( XEXC_ID_UNALIGNED_ACCESS, vPortExceptionHandlerEntry, ( void * ) XEXC_ID_UNALIGNED_ACCESS ); + #endif /* XPAR_MICROBLAZE_UNALIGNED_EXCEPTIONS*/ - #if XPAR_MICROBLAZE_ILL_OPCODE_EXCEPTION == 1 - microblaze_register_exception_handler( XEXC_ID_ILLEGAL_OPCODE, vPortExceptionHandlerEntry, ( void * ) XEXC_ID_ILLEGAL_OPCODE ); - #endif /* XPAR_MICROBLAZE_ILL_OPCODE_EXCEPTION */ + #if XPAR_MICROBLAZE_ILL_OPCODE_EXCEPTION == 1 + microblaze_register_exception_handler( XEXC_ID_ILLEGAL_OPCODE, vPortExceptionHandlerEntry, ( void * ) XEXC_ID_ILLEGAL_OPCODE ); + #endif /* XPAR_MICROBLAZE_ILL_OPCODE_EXCEPTION */ - #if XPAR_MICROBLAZE_M_AXI_I_BUS_EXCEPTION == 1 - microblaze_register_exception_handler( XEXC_ID_M_AXI_I_EXCEPTION, vPortExceptionHandlerEntry, ( void * ) XEXC_ID_M_AXI_I_EXCEPTION ); - #endif /* XPAR_MICROBLAZE_M_AXI_I_BUS_EXCEPTION */ + #if XPAR_MICROBLAZE_M_AXI_I_BUS_EXCEPTION == 1 + microblaze_register_exception_handler( XEXC_ID_M_AXI_I_EXCEPTION, vPortExceptionHandlerEntry, ( void * ) XEXC_ID_M_AXI_I_EXCEPTION ); + #endif /* XPAR_MICROBLAZE_M_AXI_I_BUS_EXCEPTION */ - #if XPAR_MICROBLAZE_M_AXI_D_BUS_EXCEPTION == 1 - microblaze_register_exception_handler( XEXC_ID_M_AXI_D_EXCEPTION, vPortExceptionHandlerEntry, ( void * ) XEXC_ID_M_AXI_D_EXCEPTION ); - #endif /* XPAR_MICROBLAZE_M_AXI_D_BUS_EXCEPTION */ + #if XPAR_MICROBLAZE_M_AXI_D_BUS_EXCEPTION == 1 + microblaze_register_exception_handler( XEXC_ID_M_AXI_D_EXCEPTION, vPortExceptionHandlerEntry, ( void * ) XEXC_ID_M_AXI_D_EXCEPTION ); + #endif /* XPAR_MICROBLAZE_M_AXI_D_BUS_EXCEPTION */ - #if XPAR_MICROBLAZE_IPLB_BUS_EXCEPTION == 1 - microblaze_register_exception_handler( XEXC_ID_IPLB_EXCEPTION, vPortExceptionHandlerEntry, ( void * ) XEXC_ID_IPLB_EXCEPTION ); - #endif /* XPAR_MICROBLAZE_IPLB_BUS_EXCEPTION */ + #if XPAR_MICROBLAZE_IPLB_BUS_EXCEPTION == 1 + microblaze_register_exception_handler( XEXC_ID_IPLB_EXCEPTION, vPortExceptionHandlerEntry, ( void * ) XEXC_ID_IPLB_EXCEPTION ); + #endif /* XPAR_MICROBLAZE_IPLB_BUS_EXCEPTION */ - #if XPAR_MICROBLAZE_DPLB_BUS_EXCEPTION == 1 - microblaze_register_exception_handler( XEXC_ID_DPLB_EXCEPTION, vPortExceptionHandlerEntry, ( void * ) XEXC_ID_DPLB_EXCEPTION ); - #endif /* XPAR_MICROBLAZE_DPLB_BUS_EXCEPTION */ + #if XPAR_MICROBLAZE_DPLB_BUS_EXCEPTION == 1 + microblaze_register_exception_handler( XEXC_ID_DPLB_EXCEPTION, vPortExceptionHandlerEntry, ( void * ) XEXC_ID_DPLB_EXCEPTION ); + #endif /* XPAR_MICROBLAZE_DPLB_BUS_EXCEPTION */ - #if XPAR_MICROBLAZE_DIV_ZERO_EXCEPTION == 1 - microblaze_register_exception_handler( XEXC_ID_DIV_BY_ZERO, vPortExceptionHandlerEntry, ( void * ) XEXC_ID_DIV_BY_ZERO ); - #endif /* XPAR_MICROBLAZE_DIV_ZERO_EXCEPTION */ + #if XPAR_MICROBLAZE_DIV_ZERO_EXCEPTION == 1 + microblaze_register_exception_handler( XEXC_ID_DIV_BY_ZERO, vPortExceptionHandlerEntry, ( void * ) XEXC_ID_DIV_BY_ZERO ); + #endif /* XPAR_MICROBLAZE_DIV_ZERO_EXCEPTION */ - #if XPAR_MICROBLAZE_FPU_EXCEPTION == 1 - microblaze_register_exception_handler( XEXC_ID_FPU, vPortExceptionHandlerEntry, ( void * ) XEXC_ID_FPU ); - #endif /* XPAR_MICROBLAZE_FPU_EXCEPTION */ + #if XPAR_MICROBLAZE_FPU_EXCEPTION == 1 + microblaze_register_exception_handler( XEXC_ID_FPU, vPortExceptionHandlerEntry, ( void * ) XEXC_ID_FPU ); + #endif /* XPAR_MICROBLAZE_FPU_EXCEPTION */ - #if XPAR_MICROBLAZE_FSL_EXCEPTION == 1 - microblaze_register_exception_handler( XEXC_ID_FSL, vPortExceptionHandlerEntry, ( void * ) XEXC_ID_FSL ); - #endif /* XPAR_MICROBLAZE_FSL_EXCEPTION */ + #if XPAR_MICROBLAZE_FSL_EXCEPTION == 1 + microblaze_register_exception_handler( XEXC_ID_FSL, vPortExceptionHandlerEntry, ( void * ) XEXC_ID_FSL ); + #endif /* XPAR_MICROBLAZE_FSL_EXCEPTION */ - microblaze_enable_exceptions(); + microblaze_enable_exceptions(); + } } -} /* Exclude the entire file if the MicroBlaze is not configured to handle -exceptions, or the application defined configuration item -configINSTALL_EXCEPTION_HANDLERS is not set to 1. */ + * exceptions, or the application defined configuration item + * configINSTALL_EXCEPTION_HANDLERS is not set to 1. */ #endif /* ( MICROBLAZE_EXCEPTIONS_ENABLED == 1 ) && ( configINSTALL_EXCEPTION_HANDLERS == 1 ) */ diff --git a/Source/portable/GCC/MicroBlazeV8/portasm.S b/Source/portable/GCC/MicroBlazeV8/portasm.S index 47fb86955..d73d744d2 100644 --- a/Source/portable/GCC/MicroBlazeV8/portasm.S +++ b/Source/portable/GCC/MicroBlazeV8/portasm.S @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/Source/portable/GCC/MicroBlazeV8/portmacro.h b/Source/portable/GCC/MicroBlazeV8/portmacro.h index 728731265..1d267dbd4 100644 --- a/Source/portable/GCC/MicroBlazeV8/portmacro.h +++ b/Source/portable/GCC/MicroBlazeV8/portmacro.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -50,28 +50,28 @@ */ /* Type definitions. */ -#define portCHAR char -#define portFLOAT float -#define portDOUBLE double -#define portLONG long -#define portSHORT short -#define portSTACK_TYPE uint32_t -#define portBASE_TYPE long - -typedef portSTACK_TYPE StackType_t; -typedef long BaseType_t; -typedef unsigned long UBaseType_t; - -#if( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS ) - typedef uint16_t TickType_t; - #define portMAX_DELAY ( TickType_t ) 0xffff +#define portCHAR char +#define portFLOAT float +#define portDOUBLE double +#define portLONG long +#define portSHORT short +#define portSTACK_TYPE uint32_t +#define portBASE_TYPE long + +typedef portSTACK_TYPE StackType_t; +typedef long BaseType_t; +typedef unsigned long UBaseType_t; + +#if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS ) + typedef uint16_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffff #elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS ) - typedef uint32_t TickType_t; - #define portMAX_DELAY ( TickType_t ) 0xffffffffUL + typedef uint32_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffffffffUL - /* 32-bit tick type on a 32-bit architecture, so reads of the tick count do - not need to be guarded with a critical section. */ - #define portTICK_TYPE_IS_ATOMIC 1 +/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do + * not need to be guarded with a critical section. */ + #define portTICK_TYPE_IS_ATOMIC 1 #else #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width. #endif @@ -87,88 +87,93 @@ void microblaze_enable_interrupts( void ); /* Critical section macros. */ void vPortEnterCritical( void ); void vPortExitCritical( void ); -#define portENTER_CRITICAL() { \ - extern volatile UBaseType_t uxCriticalNesting; \ - microblaze_disable_interrupts(); \ - uxCriticalNesting++; \ - } - -#define portEXIT_CRITICAL() { \ - extern volatile UBaseType_t uxCriticalNesting; \ - /* Interrupts are disabled, so we can */ \ - /* access the variable directly. */ \ - uxCriticalNesting--; \ - if( uxCriticalNesting == 0 ) \ - { \ - /* The nesting has unwound and we \ - can enable interrupts again. */ \ - portENABLE_INTERRUPTS(); \ - } \ - } +#define portENTER_CRITICAL() \ + { \ + extern volatile UBaseType_t uxCriticalNesting; \ + microblaze_disable_interrupts(); \ + uxCriticalNesting++; \ + } + +#define portEXIT_CRITICAL() \ + { \ + extern volatile UBaseType_t uxCriticalNesting; \ + /* Interrupts are disabled, so we can */ \ + /* access the variable directly. */ \ + uxCriticalNesting--; \ + if( uxCriticalNesting == 0 ) \ + { \ + /* The nesting has unwound and we \ + * can enable interrupts again. */ \ + portENABLE_INTERRUPTS(); \ + } \ + } /*-----------------------------------------------------------*/ /* The yield macro maps directly to the vPortYield() function. */ void vPortYield( void ); -#define portYIELD() vPortYield() +#define portYIELD() vPortYield() /* portYIELD_FROM_ISR() does not directly call vTaskSwitchContext(), but instead -sets a flag to say that a yield has been requested. The interrupt exit code -then checks this flag, and calls vTaskSwitchContext() before restoring a task -context, if the flag is not false. This is done to prevent multiple calls to -vTaskSwitchContext() being made from a single interrupt, as a single interrupt -can result in multiple peripherals being serviced. */ + * sets a flag to say that a yield has been requested. The interrupt exit code + * then checks this flag, and calls vTaskSwitchContext() before restoring a task + * context, if the flag is not false. This is done to prevent multiple calls to + * vTaskSwitchContext() being made from a single interrupt, as a single interrupt + * can result in multiple peripherals being serviced. */ extern volatile uint32_t ulTaskSwitchRequested; -#define portYIELD_FROM_ISR( x ) do { if( ( x ) != pdFALSE ) ulTaskSwitchRequested = 1; } while( 0 ) +#define portYIELD_FROM_ISR( x ) \ + do { if( ( x ) != pdFALSE ) ulTaskSwitchRequested = 1; } \ + while( 0 ) -#if( configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 ) +#if ( configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 ) - /* Generic helper function. */ +/* Generic helper function. */ __attribute__( ( always_inline ) ) static inline uint8_t ucPortCountLeadingZeros( uint32_t ulBitmap ) { - uint8_t ucReturn; + uint8_t ucReturn; __asm volatile ( "clz %0, %1" : "=r" ( ucReturn ) : "r" ( ulBitmap ) ); + return ucReturn; } - /* Check the configuration. */ - #if( configMAX_PRIORITIES > 32 ) +/* Check the configuration. */ + #if ( configMAX_PRIORITIES > 32 ) #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice. #endif - /* Store/clear the ready priorities in a bit map. */ - #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) ) - #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) ) +/* Store/clear the ready priorities in a bit map. */ + #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) ) + #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) ) - /*-----------------------------------------------------------*/ +/*-----------------------------------------------------------*/ - #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - ( uint32_t ) ucPortCountLeadingZeros( ( uxReadyPriorities ) ) ) + #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - ( uint32_t ) ucPortCountLeadingZeros( ( uxReadyPriorities ) ) ) #endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */ /*-----------------------------------------------------------*/ /* Hardware specifics. */ -#define portBYTE_ALIGNMENT 4 -#define portSTACK_GROWTH ( -1 ) -#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) -#define portNOP() asm volatile ( "NOP" ) -#define portMEMORY_BARRIER() asm volatile ( "" ::: "memory" ) +#define portBYTE_ALIGNMENT 4 +#define portSTACK_GROWTH ( -1 ) +#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) +#define portNOP() asm volatile ( "NOP" ) +#define portMEMORY_BARRIER() asm volatile ( "" ::: "memory" ) /*-----------------------------------------------------------*/ /* Task function macros as described on the FreeRTOS.org WEB site. */ -#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters ) -#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters ) +#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters ) +#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters ) /*-----------------------------------------------------------*/ /* The following structure is used by the FreeRTOS exception handler. It is -filled with the MicroBlaze context as it was at the time the exception occurred. -This is done as an aid to debugging exception occurrences. */ + * filled with the MicroBlaze context as it was at the time the exception occurred. + * This is done as an aid to debugging exception occurrences. */ typedef struct PORT_REGISTER_DUMP { /* The following structure members hold the values of the MicroBlaze - registers at the time the exception was raised. */ + * registers at the time the exception was raised. */ uint32_t ulR1_SP; uint32_t ulR2_small_data_area; uint32_t ulR3; @@ -208,19 +213,18 @@ typedef struct PORT_REGISTER_DUMP uint32_t ulEDR; /* A human readable description of the exception cause. The strings used - are the same as the #define constant names found in the - microblaze_exceptions_i.h header file */ - int8_t *pcExceptionCause; + * are the same as the #define constant names found in the + * microblaze_exceptions_i.h header file */ + int8_t * pcExceptionCause; /* The human readable name of the task that was running at the time the - exception occurred. This is the name that was given to the task when the - task was created using the FreeRTOS xTaskCreate() API function. */ - char *pcCurrentTaskName; + * exception occurred. This is the name that was given to the task when the + * task was created using the FreeRTOS xTaskCreate() API function. */ + char * pcCurrentTaskName; /* The handle of the task that was running a the time the exception - occurred. */ + * occurred. */ void * xCurrentTaskHandle; - } xPortRegisterDump; @@ -259,7 +263,9 @@ typedef struct PORT_REGISTER_DUMP * pdPASS is returned if the function executes successfully. Any other value * being returned indicates that the function did not execute correctly. */ -BaseType_t xPortInstallInterruptHandler( uint8_t ucInterruptID, XInterruptHandler pxHandler, void *pvCallBackRef ); +BaseType_t xPortInstallInterruptHandler( uint8_t ucInterruptID, + XInterruptHandler pxHandler, + void * pvCallBackRef ); /* @@ -364,7 +370,7 @@ void vPortExceptionsInstallHandlers( void ); * register dump information. For example, an implementation could be provided * that wrote the register dump data to a display, or a UART port. */ -void vApplicationExceptionRegisterDump( xPortRegisterDump *xRegisterDump ); +void vApplicationExceptionRegisterDump( xPortRegisterDump * xRegisterDump ); /* *INDENT-OFF* */ diff --git a/Source/portable/GCC/MicroBlazeV9/port.c b/Source/portable/GCC/MicroBlazeV9/port.c index e0b6e91dc..92eb4ee63 100644 --- a/Source/portable/GCC/MicroBlazeV9/port.c +++ b/Source/portable/GCC/MicroBlazeV9/port.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -27,8 +27,8 @@ */ /*----------------------------------------------------------- - * Implementation of functions defined in portable.h for the MicroBlaze port. - *----------------------------------------------------------*/ +* Implementation of functions defined in portable.h for the MicroBlaze port. +*----------------------------------------------------------*/ /* Scheduler includes. */ @@ -44,20 +44,20 @@ #include /* Tasks are started with a critical section nesting of 0 - however, prior to -the scheduler being commenced interrupts should not be enabled, so the critical -nesting variable is initialised to a non-zero value. */ -#define portINITIAL_NESTING_VALUE ( 0xff ) + * the scheduler being commenced interrupts should not be enabled, so the critical + * nesting variable is initialised to a non-zero value. */ +#define portINITIAL_NESTING_VALUE ( 0xff ) /* The bit within the MSR register that enabled/disables interrupts and -exceptions respectively. */ -#define portMSR_IE ( 0x02U ) -#define portMSR_EE ( 0x100U ) + * exceptions respectively. */ +#define portMSR_IE ( 0x02U ) +#define portMSR_EE ( 0x100U ) /* If the floating point unit is included in the MicroBlaze build, then the -FSR register is saved as part of the task context. portINITIAL_FSR is the value -given to the FSR register when the initial context is set up for a task being -created. */ -#define portINITIAL_FSR ( 0U ) + * FSR register is saved as part of the task context. portINITIAL_FSR is the value + * given to the FSR register when the initial context is set up for a task being + * created. */ +#define portINITIAL_FSR ( 0U ) /*-----------------------------------------------------------*/ @@ -74,27 +74,27 @@ static int32_t prvEnsureInterruptControllerIsInitialised( void ); /*-----------------------------------------------------------*/ /* Counts the nesting depth of calls to portENTER_CRITICAL(). Each task -maintains its own count, so this variable is saved as part of the task -context. */ + * maintains its own count, so this variable is saved as part of the task + * context. */ volatile UBaseType_t uxCriticalNesting = portINITIAL_NESTING_VALUE; /* This port uses a separate stack for interrupts. This prevents the stack of -every task needing to be large enough to hold an entire interrupt stack on top -of the task stack. */ -uint32_t *pulISRStack; + * every task needing to be large enough to hold an entire interrupt stack on top + * of the task stack. */ +uint32_t * pulISRStack; /* If an interrupt requests a context switch, then ulTaskSwitchRequested will -get set to 1. ulTaskSwitchRequested is inspected just before the main interrupt -handler exits. If, at that time, ulTaskSwitchRequested is set to 1, the kernel -will call vTaskSwitchContext() to ensure the task that runs immediately after -the interrupt exists is the highest priority task that is able to run. This is -an unusual mechanism, but is used for this port because a single interrupt can -cause the servicing of multiple peripherals - and it is inefficient to call -vTaskSwitchContext() multiple times as each peripheral is serviced. */ + * get set to 1. ulTaskSwitchRequested is inspected just before the main interrupt + * handler exits. If, at that time, ulTaskSwitchRequested is set to 1, the kernel + * will call vTaskSwitchContext() to ensure the task that runs immediately after + * the interrupt exists is the highest priority task that is able to run. This is + * an unusual mechanism, but is used for this port because a single interrupt can + * cause the servicing of multiple peripherals - and it is inefficient to call + * vTaskSwitchContext() multiple times as each peripheral is serviced. */ volatile uint32_t ulTaskSwitchRequested = 0UL; /* The instance of the interrupt controller used by this port. This is required -by the Xilinx library API functions. */ + * by the Xilinx library API functions. */ static XIntc xInterruptControllerInstance; /*-----------------------------------------------------------*/ @@ -106,20 +106,25 @@ static XIntc xInterruptControllerInstance; * See the portable.h header file. */ #if ( portHAS_STACK_OVERFLOW_CHECKING == 1 ) -StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, StackType_t *pxEndOfStack, TaskFunction_t pxCode, void *pvParameters ) + StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, + StackType_t * pxEndOfStack, + TaskFunction_t pxCode, + void * pvParameters ) #else -StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters ) + StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, + TaskFunction_t pxCode, + void * pvParameters ) #endif { -extern void * _SDA2_BASE_; -extern void * _SDA_BASE_; -const uint32_t ulR2 = ( uint32_t ) &_SDA2_BASE_; -const uint32_t ulR13 = ( uint32_t ) &_SDA_BASE_; -extern void _start1( void ); + extern void * _SDA2_BASE_; + extern void * _SDA_BASE_; + const uint32_t ulR2 = ( uint32_t ) &_SDA2_BASE_; + const uint32_t ulR13 = ( uint32_t ) &_SDA_BASE_; + extern void _start1( void ); /* Place a few bytes of known values on the bottom of the stack. - This is essential for the Microblaze port and these lines must - not be omitted. */ + * This is essential for the Microblaze port and these lines must + * not be omitted. */ *pxTopOfStack = ( StackType_t ) 0x00000000; pxTopOfStack--; *pxTopOfStack = ( StackType_t ) 0x00000000; @@ -129,24 +134,24 @@ extern void _start1( void ); #if ( portHAS_STACK_OVERFLOW_CHECKING == 1 ) /* Store the stack limits. */ - *pxTopOfStack = (StackType_t) (pxTopOfStack + 3); + *pxTopOfStack = ( StackType_t ) ( pxTopOfStack + 3 ); pxTopOfStack--; - *pxTopOfStack = (StackType_t) pxEndOfStack; + *pxTopOfStack = ( StackType_t ) pxEndOfStack; pxTopOfStack--; #endif - #if( XPAR_MICROBLAZE_USE_FPU != 0 ) + #if ( XPAR_MICROBLAZE_USE_FPU != 0 ) /* The FSR value placed in the initial task context is just 0. */ *pxTopOfStack = portINITIAL_FSR; pxTopOfStack--; #endif /* The MSR value placed in the initial task context should have interrupts - disabled. Each task will enable interrupts automatically when it enters - the running state for the first time. */ + * disabled. Each task will enable interrupts automatically when it enters + * the running state for the first time. */ *pxTopOfStack = mfmsr() & ~portMSR_IE; - #if( MICROBLAZE_EXCEPTIONS_ENABLED == 1 ) + #if ( MICROBLAZE_EXCEPTIONS_ENABLED == 1 ) { /* Ensure exceptions are enabled for the task. */ *pxTopOfStack |= portMSR_EE; @@ -156,7 +161,7 @@ extern void _start1( void ); pxTopOfStack--; /* First stack an initial value for the critical section nesting. This - is initialised to zero. */ + * is initialised to zero. */ *pxTopOfStack = ( StackType_t ) 0x00; /* R0 is always zero. */ @@ -164,13 +169,13 @@ extern void _start1( void ); /* Place an initial value for all the general purpose registers. */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) ulR2; /* R2 - read only small data area. */ + *pxTopOfStack = ( StackType_t ) ulR2; /* R2 - read only small data area. */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x03; /* R3 - return values and temporaries. */ + *pxTopOfStack = ( StackType_t ) 0x03; /* R3 - return values and temporaries. */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x04; /* R4 - return values and temporaries. */ + *pxTopOfStack = ( StackType_t ) 0x04; /* R4 - return values and temporaries. */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) pvParameters;/* R5 contains the function call parameters. */ + *pxTopOfStack = ( StackType_t ) pvParameters; /* R5 contains the function call parameters. */ #ifdef portPRE_LOAD_STACK_FOR_DEBUGGING pxTopOfStack--; @@ -188,15 +193,15 @@ extern void _start1( void ); pxTopOfStack--; *pxTopOfStack = ( StackType_t ) 0x0c; /* R12 - temporaries. */ pxTopOfStack--; - #else - pxTopOfStack-= 8; - #endif + #else /* ifdef portPRE_LOAD_STACK_FOR_DEBUGGING */ + pxTopOfStack -= 8; + #endif /* ifdef portPRE_LOAD_STACK_FOR_DEBUGGING */ - *pxTopOfStack = ( StackType_t ) ulR13; /* R13 - read/write small data area. */ + *pxTopOfStack = ( StackType_t ) ulR13; /* R13 - read/write small data area. */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) pxCode; /* R14 - return address for interrupt. */ + *pxTopOfStack = ( StackType_t ) pxCode; /* R14 - return address for interrupt. */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) _start1; /* R15 - return address for subroutine. */ + *pxTopOfStack = ( StackType_t ) _start1; /* R15 - return address for subroutine. */ #ifdef portPRE_LOAD_STACK_FOR_DEBUGGING pxTopOfStack--; @@ -238,41 +243,41 @@ extern void _start1( void ); pxTopOfStack--; *pxTopOfStack = ( StackType_t ) 0x1f; /* R31 - must be saved across function calls. Callee-save. */ pxTopOfStack--; - #else + #else /* ifdef portPRE_LOAD_STACK_FOR_DEBUGGING */ pxTopOfStack -= 13; - #endif + #endif /* ifdef portPRE_LOAD_STACK_FOR_DEBUGGING */ /* Return a pointer to the top of the stack that has been generated so this - can be stored in the task control block for the task. */ + * can be stored in the task control block for the task. */ return pxTopOfStack; } /*-----------------------------------------------------------*/ BaseType_t xPortStartScheduler( void ) { -extern void ( vPortStartFirstTask )( void ); -extern uint32_t _stack[]; + extern void( vPortStartFirstTask )( void ); + extern uint32_t _stack[]; /* Setup the hardware to generate the tick. Interrupts are disabled when - this function is called. - - This port uses an application defined callback function to install the tick - interrupt handler because the kernel will run on lots of different - MicroBlaze and FPGA configurations - not all of which will have the same - timer peripherals defined or available. An example definition of - vApplicationSetupTimerInterrupt() is provided in the official demo - application that accompanies this port. */ + * this function is called. + * + * This port uses an application defined callback function to install the tick + * interrupt handler because the kernel will run on lots of different + * MicroBlaze and FPGA configurations - not all of which will have the same + * timer peripherals defined or available. An example definition of + * vApplicationSetupTimerInterrupt() is provided in the official demo + * application that accompanies this port. */ vApplicationSetupTimerInterrupt(); /* Reuse the stack from main() as the stack for the interrupts/exceptions. */ pulISRStack = ( uint32_t * ) _stack; /* Ensure there is enough space for the functions called from the interrupt - service routines to write back into the stack frame of the caller. */ + * service routines to write back into the stack frame of the caller. */ pulISRStack -= 2; /* Restore the context of the first task that is going to run. From here - on, the created tasks will be executing. */ + * on, the created tasks will be executing. */ vPortStartFirstTask(); /* Should not get here as the tasks are now running! */ @@ -283,7 +288,7 @@ extern uint32_t _stack[]; void vPortEndScheduler( void ) { /* Not implemented in ports where there is nothing to return to. - Artificially force an assert. */ + * Artificially force an assert. */ configASSERT( uxCriticalNesting == 1000UL ); } /*-----------------------------------------------------------*/ @@ -293,17 +298,17 @@ void vPortEndScheduler( void ) */ void vPortYield( void ) { -extern void VPortYieldASM( void ); + extern void VPortYieldASM( void ); /* Perform the context switch in a critical section to assure it is - not interrupted by the tick ISR. It is not a problem to do this as - each task maintains its own interrupt status. */ + * not interrupted by the tick ISR. It is not a problem to do this as + * each task maintains its own interrupt status. */ portENTER_CRITICAL(); { /* Jump directly to the yield function to ensure there is no - compiler generated prologue code. */ - asm volatile ( "bralid r14, VPortYieldASM \n\t" \ - "or r0, r0, r0 \n\t" ); + * compiler generated prologue code. */ + asm volatile ( "bralid r14, VPortYieldASM \n\t" \ + "or r0, r0, r0 \n\t" ); } portEXIT_CRITICAL(); } @@ -311,16 +316,17 @@ extern void VPortYieldASM( void ); void vPortEnableInterrupt( uint8_t ucInterruptID ) { -int32_t lReturn; + int32_t lReturn; /* An API function is provided to enable an interrupt in the interrupt - controller because the interrupt controller instance variable is private - to this file. */ + * controller because the interrupt controller instance variable is private + * to this file. */ lReturn = prvEnsureInterruptControllerIsInitialised(); + if( lReturn == pdPASS ) { /* Critical section protects read/modify/writer operation inside - XIntc_Enable(). */ + * XIntc_Enable(). */ portENTER_CRITICAL(); { XIntc_Enable( &xInterruptControllerInstance, ucInterruptID ); @@ -334,11 +340,11 @@ int32_t lReturn; void vPortDisableInterrupt( uint8_t ucInterruptID ) { -int32_t lReturn; + int32_t lReturn; /* An API function is provided to disable an interrupt in the interrupt - controller because the interrupt controller instance variable is private - to this file. */ + * controller because the interrupt controller instance variable is private + * to this file. */ lReturn = prvEnsureInterruptControllerIsInitialised(); if( lReturn == pdPASS ) @@ -350,12 +356,14 @@ int32_t lReturn; } /*-----------------------------------------------------------*/ -BaseType_t xPortInstallInterruptHandler( uint8_t ucInterruptID, XInterruptHandler pxHandler, void *pvCallBackRef ) +BaseType_t xPortInstallInterruptHandler( uint8_t ucInterruptID, + XInterruptHandler pxHandler, + void * pvCallBackRef ) { -int32_t lReturn; + int32_t lReturn; /* An API function is provided to install an interrupt handler because the - interrupt controller instance variable is private to this file. */ + * interrupt controller instance variable is private to this file. */ lReturn = prvEnsureInterruptControllerIsInitialised(); @@ -377,10 +385,10 @@ int32_t lReturn; void vPortRemoveInterruptHandler( uint8_t ucInterruptID ) { -int32_t lReturn; + int32_t lReturn; /* An API function is provided to remove an interrupt handler because the - interrupt controller instance variable is private to this file. */ + * interrupt controller instance variable is private to this file. */ lReturn = prvEnsureInterruptControllerIsInitialised(); @@ -395,11 +403,11 @@ int32_t lReturn; static int32_t prvEnsureInterruptControllerIsInitialised( void ) { -static int32_t lInterruptControllerInitialised = pdFALSE; -int32_t lReturn; + static int32_t lInterruptControllerInitialised = pdFALSE; + int32_t lReturn; /* Ensure the interrupt controller instance variable is initialised before - it is used, and that the initialisation only happens once. */ + * it is used, and that the initialisation only happens once. */ if( lInterruptControllerInitialised != pdTRUE ) { lReturn = prvInitialiseInterruptController(); @@ -422,19 +430,19 @@ int32_t lReturn; * Handler for the timer interrupt. This is the handler that the application * defined callback function vApplicationSetupTimerInterrupt() should install. */ -void vPortTickISR( void *pvUnused ) +void vPortTickISR( void * pvUnused ) { -extern void vApplicationClearTimerInterrupt( void ); + extern void vApplicationClearTimerInterrupt( void ); /* Ensure the unused parameter does not generate a compiler warning. */ ( void ) pvUnused; /* This port uses an application defined callback function to clear the tick - interrupt because the kernel will run on lots of different MicroBlaze and - FPGA configurations - not all of which will have the same timer peripherals - defined or available. An example definition of - vApplicationClearTimerInterrupt() is provided in the official demo - application that accompanies this port. */ + * interrupt because the kernel will run on lots of different MicroBlaze and + * FPGA configurations - not all of which will have the same timer peripherals + * defined or available. An example definition of + * vApplicationClearTimerInterrupt() is provided in the official demo + * application that accompanies this port. */ vApplicationClearTimerInterrupt(); /* Increment the RTOS tick - this might cause a task to unblock. */ @@ -448,7 +456,7 @@ extern void vApplicationClearTimerInterrupt( void ); static int32_t prvInitialiseInterruptController( void ) { -int32_t lStatus; + int32_t lStatus; lStatus = XIntc_Initialize( &xInterruptControllerInstance, configINTERRUPT_CONTROLLER_TO_USE ); @@ -461,8 +469,8 @@ int32_t lStatus; XIntc_SetIntrSvcOption( xInterruptControllerInstance.BaseAddress, XIN_SVC_ALL_ISRS_OPTION ); /* Install exception handlers if the MicroBlaze is configured to handle - exceptions, and the application defined constant - configINSTALL_EXCEPTION_HANDLERS is set to 1. */ + * exceptions, and the application defined constant + * configINSTALL_EXCEPTION_HANDLERS is set to 1. */ #if ( MICROBLAZE_EXCEPTIONS_ENABLED == 1 ) && ( configINSTALL_EXCEPTION_HANDLERS == 1 ) { vPortExceptionsInstallHandlers(); @@ -470,7 +478,7 @@ int32_t lStatus; #endif /* MICROBLAZE_EXCEPTIONS_ENABLED */ /* Start the interrupt controller. Interrupts are enabled when the - scheduler starts. */ + * scheduler starts. */ lStatus = XIntc_Start( &xInterruptControllerInstance, XIN_REAL_MODE ); if( lStatus == XST_SUCCESS ) diff --git a/Source/portable/GCC/MicroBlazeV9/port_exceptions.c b/Source/portable/GCC/MicroBlazeV9/port_exceptions.c index 2c6221dc5..e8cf8275f 100644 --- a/Source/portable/GCC/MicroBlazeV9/port_exceptions.c +++ b/Source/portable/GCC/MicroBlazeV9/port_exceptions.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -35,246 +35,244 @@ #include /* The Xilinx library defined exception entry point stacks a number of -registers. These definitions are offsets from the stack pointer to the various -stacked register values. */ -#define portexR3_STACK_OFFSET 4 -#define portexR4_STACK_OFFSET 5 -#define portexR5_STACK_OFFSET 6 -#define portexR6_STACK_OFFSET 7 -#define portexR7_STACK_OFFSET 8 -#define portexR8_STACK_OFFSET 9 -#define portexR9_STACK_OFFSET 10 -#define portexR10_STACK_OFFSET 11 -#define portexR11_STACK_OFFSET 12 -#define portexR12_STACK_OFFSET 13 -#define portexR15_STACK_OFFSET 16 -#define portexR18_STACK_OFFSET 19 -#define portexMSR_STACK_OFFSET 20 -#define portexR19_STACK_OFFSET -1 + * registers. These definitions are offsets from the stack pointer to the various + * stacked register values. */ +#define portexR3_STACK_OFFSET 4 +#define portexR4_STACK_OFFSET 5 +#define portexR5_STACK_OFFSET 6 +#define portexR6_STACK_OFFSET 7 +#define portexR7_STACK_OFFSET 8 +#define portexR8_STACK_OFFSET 9 +#define portexR9_STACK_OFFSET 10 +#define portexR10_STACK_OFFSET 11 +#define portexR11_STACK_OFFSET 12 +#define portexR12_STACK_OFFSET 13 +#define portexR15_STACK_OFFSET 16 +#define portexR18_STACK_OFFSET 19 +#define portexMSR_STACK_OFFSET 20 +#define portexR19_STACK_OFFSET -1 /* This is defined to equal the size, in bytes, of the stack frame generated by -the Xilinx standard library exception entry point. It is required to determine -the stack pointer value prior to the exception being entered. */ -#define portexASM_HANDLER_STACK_FRAME_SIZE 84UL + * the Xilinx standard library exception entry point. It is required to determine + * the stack pointer value prior to the exception being entered. */ +#define portexASM_HANDLER_STACK_FRAME_SIZE 84UL /* The number of bytes a MicroBlaze instruction consumes. */ -#define portexINSTRUCTION_SIZE 4 +#define portexINSTRUCTION_SIZE 4 /* Exclude this entire file if the MicroBlaze is not configured to handle -exceptions, or the application defined configuration constant -configINSTALL_EXCEPTION_HANDLERS is not set to 1. */ + * exceptions, or the application defined configuration constant + * configINSTALL_EXCEPTION_HANDLERS is not set to 1. */ #if ( MICROBLAZE_EXCEPTIONS_ENABLED == 1 ) && ( configINSTALL_EXCEPTION_HANDLERS == 1 ) /* This variable is set in the exception entry code, before -vPortExceptionHandler is called. */ -uint32_t *pulStackPointerOnFunctionEntry = NULL; + * vPortExceptionHandler is called. */ + uint32_t * pulStackPointerOnFunctionEntry = NULL; /* This is the structure that is filled with the MicroBlaze context as it -existed immediately prior to the exception occurrence. A pointer to this -structure is passed into the vApplicationExceptionRegisterDump() callback -function, if one is defined. */ -static xPortRegisterDump xRegisterDump; + * existed immediately prior to the exception occurrence. A pointer to this + * structure is passed into the vApplicationExceptionRegisterDump() callback + * function, if one is defined. */ + static xPortRegisterDump xRegisterDump; /* This is the FreeRTOS exception handler that is installed for all exception -types. It is called from vPortExceptionHanlderEntry() - which is itself defined -in portasm.S. */ -void vPortExceptionHandler( void *pvExceptionID ); -extern void vPortExceptionHandlerEntry( void *pvExceptionID ); + * types. It is called from vPortExceptionHandlerEntry() - which is itself defined + * in portasm.S. */ + void vPortExceptionHandler( void * pvExceptionID ); + extern void vPortExceptionHandlerEntry( void * pvExceptionID ); /*-----------------------------------------------------------*/ /* vApplicationExceptionRegisterDump() is a callback function that the -application can optionally define to receive a populated xPortRegisterDump -structure. If the application chooses not to define a version of -vApplicationExceptionRegisterDump() then this weekly defined default -implementation will be called instead. */ -extern void vApplicationExceptionRegisterDump( xPortRegisterDump *xRegisterDump ) __attribute__((weak)); -void vApplicationExceptionRegisterDump( xPortRegisterDump *xRegisterDump ) -{ - ( void ) xRegisterDump; - - for( ;; ) + * application can optionally define to receive a populated xPortRegisterDump + * structure. If the application chooses not to define a version of + * vApplicationExceptionRegisterDump() then this weekly defined default + * implementation will be called instead. */ + extern void vApplicationExceptionRegisterDump( xPortRegisterDump * xRegisterDump ) __attribute__( ( weak ) ); + void vApplicationExceptionRegisterDump( xPortRegisterDump * xRegisterDump ) { - portNOP(); - } -} -/*-----------------------------------------------------------*/ + ( void ) xRegisterDump; -void vPortExceptionHandler( void *pvExceptionID ) -{ -extern void *pxCurrentTCB; - - /* Fill an xPortRegisterDump structure with the MicroBlaze context as it - was immediately before the exception occurrence. */ - - /* First fill in the name and handle of the task that was in the Running - state when the exception occurred. */ - xRegisterDump.xCurrentTaskHandle = pxCurrentTCB; - xRegisterDump.pcCurrentTaskName = pcTaskGetName( NULL ); - - configASSERT( pulStackPointerOnFunctionEntry ); - - /* Obtain the values of registers that were stacked prior to this function - being called, and may have changed since they were stacked. */ - xRegisterDump.ulR3 = pulStackPointerOnFunctionEntry[ portexR3_STACK_OFFSET ]; - xRegisterDump.ulR4 = pulStackPointerOnFunctionEntry[ portexR4_STACK_OFFSET ]; - xRegisterDump.ulR5 = pulStackPointerOnFunctionEntry[ portexR5_STACK_OFFSET ]; - xRegisterDump.ulR6 = pulStackPointerOnFunctionEntry[ portexR6_STACK_OFFSET ]; - xRegisterDump.ulR7 = pulStackPointerOnFunctionEntry[ portexR7_STACK_OFFSET ]; - xRegisterDump.ulR8 = pulStackPointerOnFunctionEntry[ portexR8_STACK_OFFSET ]; - xRegisterDump.ulR9 = pulStackPointerOnFunctionEntry[ portexR9_STACK_OFFSET ]; - xRegisterDump.ulR10 = pulStackPointerOnFunctionEntry[ portexR10_STACK_OFFSET ]; - xRegisterDump.ulR11 = pulStackPointerOnFunctionEntry[ portexR11_STACK_OFFSET ]; - xRegisterDump.ulR12 = pulStackPointerOnFunctionEntry[ portexR12_STACK_OFFSET ]; - xRegisterDump.ulR15_return_address_from_subroutine = pulStackPointerOnFunctionEntry[ portexR15_STACK_OFFSET ]; - xRegisterDump.ulR18 = pulStackPointerOnFunctionEntry[ portexR18_STACK_OFFSET ]; - xRegisterDump.ulR19 = pulStackPointerOnFunctionEntry[ portexR19_STACK_OFFSET ]; - xRegisterDump.ulMSR = pulStackPointerOnFunctionEntry[ portexMSR_STACK_OFFSET ]; - - /* Obtain the value of all other registers. */ - xRegisterDump.ulR2_small_data_area = mfgpr( R2 ); - xRegisterDump.ulR13_read_write_small_data_area = mfgpr( R13 ); - xRegisterDump.ulR14_return_address_from_interrupt = mfgpr( R14 ); - xRegisterDump.ulR16_return_address_from_trap = mfgpr( R16 ); - xRegisterDump.ulR17_return_address_from_exceptions = mfgpr( R17 ); - xRegisterDump.ulR20 = mfgpr( R20 ); - xRegisterDump.ulR21 = mfgpr( R21 ); - xRegisterDump.ulR22 = mfgpr( R22 ); - xRegisterDump.ulR23 = mfgpr( R23 ); - xRegisterDump.ulR24 = mfgpr( R24 ); - xRegisterDump.ulR25 = mfgpr( R25 ); - xRegisterDump.ulR26 = mfgpr( R26 ); - xRegisterDump.ulR27 = mfgpr( R27 ); - xRegisterDump.ulR28 = mfgpr( R28 ); - xRegisterDump.ulR29 = mfgpr( R29 ); - xRegisterDump.ulR30 = mfgpr( R30 ); - xRegisterDump.ulR31 = mfgpr( R31 ); - xRegisterDump.ulR1_SP = ( ( uint32_t ) pulStackPointerOnFunctionEntry ) + portexASM_HANDLER_STACK_FRAME_SIZE; - xRegisterDump.ulEAR = mfear(); - xRegisterDump.ulESR = mfesr(); - xRegisterDump.ulEDR = mfedr(); - - /* Move the saved program counter back to the instruction that was executed - when the exception occurred. This is only valid for certain types of - exception. */ - xRegisterDump.ulPC = xRegisterDump.ulR17_return_address_from_exceptions - portexINSTRUCTION_SIZE; - - #if( XPAR_MICROBLAZE_USE_FPU != 0 ) - { - xRegisterDump.ulFSR = mffsr(); + for( ; ; ) + { + portNOP(); + } } - #else - { - xRegisterDump.ulFSR = 0UL; - } - #endif +/*-----------------------------------------------------------*/ - /* Also fill in a string that describes what type of exception this is. - The string uses the same ID names as defined in the MicroBlaze standard - library exception header files. */ - switch( ( uint32_t ) pvExceptionID ) + void vPortExceptionHandler( void * pvExceptionID ) { - case XEXC_ID_FSL : + extern void * pxCurrentTCB; + + /* Fill an xPortRegisterDump structure with the MicroBlaze context as it + * was immediately before the exception occurrence. */ + + /* First fill in the name and handle of the task that was in the Running + * state when the exception occurred. */ + xRegisterDump.xCurrentTaskHandle = pxCurrentTCB; + xRegisterDump.pcCurrentTaskName = pcTaskGetName( NULL ); + + configASSERT( pulStackPointerOnFunctionEntry ); + + /* Obtain the values of registers that were stacked prior to this function + * being called, and may have changed since they were stacked. */ + xRegisterDump.ulR3 = pulStackPointerOnFunctionEntry[ portexR3_STACK_OFFSET ]; + xRegisterDump.ulR4 = pulStackPointerOnFunctionEntry[ portexR4_STACK_OFFSET ]; + xRegisterDump.ulR5 = pulStackPointerOnFunctionEntry[ portexR5_STACK_OFFSET ]; + xRegisterDump.ulR6 = pulStackPointerOnFunctionEntry[ portexR6_STACK_OFFSET ]; + xRegisterDump.ulR7 = pulStackPointerOnFunctionEntry[ portexR7_STACK_OFFSET ]; + xRegisterDump.ulR8 = pulStackPointerOnFunctionEntry[ portexR8_STACK_OFFSET ]; + xRegisterDump.ulR9 = pulStackPointerOnFunctionEntry[ portexR9_STACK_OFFSET ]; + xRegisterDump.ulR10 = pulStackPointerOnFunctionEntry[ portexR10_STACK_OFFSET ]; + xRegisterDump.ulR11 = pulStackPointerOnFunctionEntry[ portexR11_STACK_OFFSET ]; + xRegisterDump.ulR12 = pulStackPointerOnFunctionEntry[ portexR12_STACK_OFFSET ]; + xRegisterDump.ulR15_return_address_from_subroutine = pulStackPointerOnFunctionEntry[ portexR15_STACK_OFFSET ]; + xRegisterDump.ulR18 = pulStackPointerOnFunctionEntry[ portexR18_STACK_OFFSET ]; + xRegisterDump.ulR19 = pulStackPointerOnFunctionEntry[ portexR19_STACK_OFFSET ]; + xRegisterDump.ulMSR = pulStackPointerOnFunctionEntry[ portexMSR_STACK_OFFSET ]; + + /* Obtain the value of all other registers. */ + xRegisterDump.ulR2_small_data_area = mfgpr( R2 ); + xRegisterDump.ulR13_read_write_small_data_area = mfgpr( R13 ); + xRegisterDump.ulR14_return_address_from_interrupt = mfgpr( R14 ); + xRegisterDump.ulR16_return_address_from_trap = mfgpr( R16 ); + xRegisterDump.ulR17_return_address_from_exceptions = mfgpr( R17 ); + xRegisterDump.ulR20 = mfgpr( R20 ); + xRegisterDump.ulR21 = mfgpr( R21 ); + xRegisterDump.ulR22 = mfgpr( R22 ); + xRegisterDump.ulR23 = mfgpr( R23 ); + xRegisterDump.ulR24 = mfgpr( R24 ); + xRegisterDump.ulR25 = mfgpr( R25 ); + xRegisterDump.ulR26 = mfgpr( R26 ); + xRegisterDump.ulR27 = mfgpr( R27 ); + xRegisterDump.ulR28 = mfgpr( R28 ); + xRegisterDump.ulR29 = mfgpr( R29 ); + xRegisterDump.ulR30 = mfgpr( R30 ); + xRegisterDump.ulR31 = mfgpr( R31 ); + xRegisterDump.ulR1_SP = ( ( uint32_t ) pulStackPointerOnFunctionEntry ) + portexASM_HANDLER_STACK_FRAME_SIZE; + xRegisterDump.ulEAR = mfear(); + xRegisterDump.ulESR = mfesr(); + xRegisterDump.ulEDR = mfedr(); + + /* Move the saved program counter back to the instruction that was executed + * when the exception occurred. This is only valid for certain types of + * exception. */ + xRegisterDump.ulPC = xRegisterDump.ulR17_return_address_from_exceptions - portexINSTRUCTION_SIZE; + + #if ( XPAR_MICROBLAZE_USE_FPU != 0 ) + { + xRegisterDump.ulFSR = mffsr(); + } + #else + { + xRegisterDump.ulFSR = 0UL; + } + #endif + + /* Also fill in a string that describes what type of exception this is. + * The string uses the same ID names as defined in the MicroBlaze standard + * library exception header files. */ + switch( ( uint32_t ) pvExceptionID ) + { + case XEXC_ID_FSL: xRegisterDump.pcExceptionCause = ( int8_t * const ) "XEXC_ID_FSL"; break; - case XEXC_ID_UNALIGNED_ACCESS : + case XEXC_ID_UNALIGNED_ACCESS: xRegisterDump.pcExceptionCause = ( int8_t * const ) "XEXC_ID_UNALIGNED_ACCESS"; break; - case XEXC_ID_ILLEGAL_OPCODE : + case XEXC_ID_ILLEGAL_OPCODE: xRegisterDump.pcExceptionCause = ( int8_t * const ) "XEXC_ID_ILLEGAL_OPCODE"; break; - case XEXC_ID_M_AXI_I_EXCEPTION : + case XEXC_ID_M_AXI_I_EXCEPTION: xRegisterDump.pcExceptionCause = ( int8_t * const ) "XEXC_ID_M_AXI_I_EXCEPTION or XEXC_ID_IPLB_EXCEPTION"; break; - case XEXC_ID_M_AXI_D_EXCEPTION : + case XEXC_ID_M_AXI_D_EXCEPTION: xRegisterDump.pcExceptionCause = ( int8_t * const ) "XEXC_ID_M_AXI_D_EXCEPTION or XEXC_ID_DPLB_EXCEPTION"; break; - case XEXC_ID_DIV_BY_ZERO : + case XEXC_ID_DIV_BY_ZERO: xRegisterDump.pcExceptionCause = ( int8_t * const ) "XEXC_ID_DIV_BY_ZERO"; break; - case XEXC_ID_STACK_VIOLATION : + case XEXC_ID_STACK_VIOLATION: xRegisterDump.pcExceptionCause = ( int8_t * const ) "XEXC_ID_STACK_VIOLATION or XEXC_ID_MMU"; break; - #if( XPAR_MICROBLAZE_USE_FPU != 0 ) - - case XEXC_ID_FPU : + #if ( XPAR_MICROBLAZE_USE_FPU != 0 ) + case XEXC_ID_FPU: xRegisterDump.pcExceptionCause = ( int8_t * const ) "XEXC_ID_FPU see ulFSR value"; break; - - #endif /* XPAR_MICROBLAZE_USE_FPU */ + #endif /* XPAR_MICROBLAZE_USE_FPU */ + } + + /* vApplicationExceptionRegisterDump() is a callback function that the + * application can optionally define to receive the populated xPortRegisterDump + * structure. If the application chooses not to define a version of + * vApplicationExceptionRegisterDump() then the weekly defined default + * implementation within this file will be called instead. */ + vApplicationExceptionRegisterDump( &xRegisterDump ); + + /* Must not attempt to leave this function! */ + for( ; ; ) + { + portNOP(); + } } - - /* vApplicationExceptionRegisterDump() is a callback function that the - application can optionally define to receive the populated xPortRegisterDump - structure. If the application chooses not to define a version of - vApplicationExceptionRegisterDump() then the weekly defined default - implementation within this file will be called instead. */ - vApplicationExceptionRegisterDump( &xRegisterDump ); - - /* Must not attempt to leave this function! */ - for( ;; ) - { - portNOP(); - } -} /*-----------------------------------------------------------*/ -void vPortExceptionsInstallHandlers( void ) -{ -static uint32_t ulHandlersAlreadyInstalled = pdFALSE; - - if( ulHandlersAlreadyInstalled == pdFALSE ) + void vPortExceptionsInstallHandlers( void ) { - ulHandlersAlreadyInstalled = pdTRUE; + static uint32_t ulHandlersAlreadyInstalled = pdFALSE; + + if( ulHandlersAlreadyInstalled == pdFALSE ) + { + ulHandlersAlreadyInstalled = pdTRUE; - #if XPAR_MICROBLAZE_UNALIGNED_EXCEPTIONS == 1 - microblaze_register_exception_handler( XEXC_ID_UNALIGNED_ACCESS, vPortExceptionHandlerEntry, ( void * ) XEXC_ID_UNALIGNED_ACCESS ); - #endif /* XPAR_MICROBLAZE_UNALIGNED_EXCEPTIONS*/ + #if XPAR_MICROBLAZE_UNALIGNED_EXCEPTIONS == 1 + microblaze_register_exception_handler( XEXC_ID_UNALIGNED_ACCESS, vPortExceptionHandlerEntry, ( void * ) XEXC_ID_UNALIGNED_ACCESS ); + #endif /* XPAR_MICROBLAZE_UNALIGNED_EXCEPTIONS*/ - #if XPAR_MICROBLAZE_ILL_OPCODE_EXCEPTION == 1 - microblaze_register_exception_handler( XEXC_ID_ILLEGAL_OPCODE, vPortExceptionHandlerEntry, ( void * ) XEXC_ID_ILLEGAL_OPCODE ); - #endif /* XPAR_MICROBLAZE_ILL_OPCODE_EXCEPTION */ + #if XPAR_MICROBLAZE_ILL_OPCODE_EXCEPTION == 1 + microblaze_register_exception_handler( XEXC_ID_ILLEGAL_OPCODE, vPortExceptionHandlerEntry, ( void * ) XEXC_ID_ILLEGAL_OPCODE ); + #endif /* XPAR_MICROBLAZE_ILL_OPCODE_EXCEPTION */ - #if XPAR_MICROBLAZE_M_AXI_I_BUS_EXCEPTION == 1 - microblaze_register_exception_handler( XEXC_ID_M_AXI_I_EXCEPTION, vPortExceptionHandlerEntry, ( void * ) XEXC_ID_M_AXI_I_EXCEPTION ); - #endif /* XPAR_MICROBLAZE_M_AXI_I_BUS_EXCEPTION */ + #if XPAR_MICROBLAZE_M_AXI_I_BUS_EXCEPTION == 1 + microblaze_register_exception_handler( XEXC_ID_M_AXI_I_EXCEPTION, vPortExceptionHandlerEntry, ( void * ) XEXC_ID_M_AXI_I_EXCEPTION ); + #endif /* XPAR_MICROBLAZE_M_AXI_I_BUS_EXCEPTION */ - #if XPAR_MICROBLAZE_M_AXI_D_BUS_EXCEPTION == 1 - microblaze_register_exception_handler( XEXC_ID_M_AXI_D_EXCEPTION, vPortExceptionHandlerEntry, ( void * ) XEXC_ID_M_AXI_D_EXCEPTION ); - #endif /* XPAR_MICROBLAZE_M_AXI_D_BUS_EXCEPTION */ + #if XPAR_MICROBLAZE_M_AXI_D_BUS_EXCEPTION == 1 + microblaze_register_exception_handler( XEXC_ID_M_AXI_D_EXCEPTION, vPortExceptionHandlerEntry, ( void * ) XEXC_ID_M_AXI_D_EXCEPTION ); + #endif /* XPAR_MICROBLAZE_M_AXI_D_BUS_EXCEPTION */ - #if XPAR_MICROBLAZE_IPLB_BUS_EXCEPTION == 1 - microblaze_register_exception_handler( XEXC_ID_IPLB_EXCEPTION, vPortExceptionHandlerEntry, ( void * ) XEXC_ID_IPLB_EXCEPTION ); - #endif /* XPAR_MICROBLAZE_IPLB_BUS_EXCEPTION */ + #if XPAR_MICROBLAZE_IPLB_BUS_EXCEPTION == 1 + microblaze_register_exception_handler( XEXC_ID_IPLB_EXCEPTION, vPortExceptionHandlerEntry, ( void * ) XEXC_ID_IPLB_EXCEPTION ); + #endif /* XPAR_MICROBLAZE_IPLB_BUS_EXCEPTION */ - #if XPAR_MICROBLAZE_DPLB_BUS_EXCEPTION == 1 - microblaze_register_exception_handler( XEXC_ID_DPLB_EXCEPTION, vPortExceptionHandlerEntry, ( void * ) XEXC_ID_DPLB_EXCEPTION ); - #endif /* XPAR_MICROBLAZE_DPLB_BUS_EXCEPTION */ + #if XPAR_MICROBLAZE_DPLB_BUS_EXCEPTION == 1 + microblaze_register_exception_handler( XEXC_ID_DPLB_EXCEPTION, vPortExceptionHandlerEntry, ( void * ) XEXC_ID_DPLB_EXCEPTION ); + #endif /* XPAR_MICROBLAZE_DPLB_BUS_EXCEPTION */ - #if XPAR_MICROBLAZE_DIV_ZERO_EXCEPTION == 1 - microblaze_register_exception_handler( XEXC_ID_DIV_BY_ZERO, vPortExceptionHandlerEntry, ( void * ) XEXC_ID_DIV_BY_ZERO ); - #endif /* XPAR_MICROBLAZE_DIV_ZERO_EXCEPTION */ + #if XPAR_MICROBLAZE_DIV_ZERO_EXCEPTION == 1 + microblaze_register_exception_handler( XEXC_ID_DIV_BY_ZERO, vPortExceptionHandlerEntry, ( void * ) XEXC_ID_DIV_BY_ZERO ); + #endif /* XPAR_MICROBLAZE_DIV_ZERO_EXCEPTION */ - #if XPAR_MICROBLAZE_FPU_EXCEPTION == 1 - microblaze_register_exception_handler( XEXC_ID_FPU, vPortExceptionHandlerEntry, ( void * ) XEXC_ID_FPU ); - #endif /* XPAR_MICROBLAZE_FPU_EXCEPTION */ + #if XPAR_MICROBLAZE_FPU_EXCEPTION == 1 + microblaze_register_exception_handler( XEXC_ID_FPU, vPortExceptionHandlerEntry, ( void * ) XEXC_ID_FPU ); + #endif /* XPAR_MICROBLAZE_FPU_EXCEPTION */ - #if XPAR_MICROBLAZE_FSL_EXCEPTION == 1 - microblaze_register_exception_handler( XEXC_ID_FSL, vPortExceptionHandlerEntry, ( void * ) XEXC_ID_FSL ); - #endif /* XPAR_MICROBLAZE_FSL_EXCEPTION */ + #if XPAR_MICROBLAZE_FSL_EXCEPTION == 1 + microblaze_register_exception_handler( XEXC_ID_FSL, vPortExceptionHandlerEntry, ( void * ) XEXC_ID_FSL ); + #endif /* XPAR_MICROBLAZE_FSL_EXCEPTION */ - microblaze_enable_exceptions(); + microblaze_enable_exceptions(); + } } -} /* Exclude the entire file if the MicroBlaze is not configured to handle -exceptions, or the application defined configuration item -configINSTALL_EXCEPTION_HANDLERS is not set to 1. */ + * exceptions, or the application defined configuration item + * configINSTALL_EXCEPTION_HANDLERS is not set to 1. */ #endif /* ( MICROBLAZE_EXCEPTIONS_ENABLED == 1 ) && ( configINSTALL_EXCEPTION_HANDLERS == 1 ) */ diff --git a/Source/portable/GCC/MicroBlazeV9/portasm.S b/Source/portable/GCC/MicroBlazeV9/portasm.S index 24b7743cf..30706d16f 100644 --- a/Source/portable/GCC/MicroBlazeV9/portasm.S +++ b/Source/portable/GCC/MicroBlazeV9/portasm.S @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/Source/portable/GCC/MicroBlazeV9/portmacro.h b/Source/portable/GCC/MicroBlazeV9/portmacro.h index 684ae49b4..196c67fa6 100644 --- a/Source/portable/GCC/MicroBlazeV9/portmacro.h +++ b/Source/portable/GCC/MicroBlazeV9/portmacro.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -50,28 +50,28 @@ */ /* Type definitions. */ -#define portCHAR char -#define portFLOAT float -#define portDOUBLE double -#define portLONG long -#define portSHORT short -#define portSTACK_TYPE uint32_t -#define portBASE_TYPE long - -typedef portSTACK_TYPE StackType_t; -typedef long BaseType_t; -typedef unsigned long UBaseType_t; - -#if( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS ) - typedef uint16_t TickType_t; - #define portMAX_DELAY ( TickType_t ) 0xffff +#define portCHAR char +#define portFLOAT float +#define portDOUBLE double +#define portLONG long +#define portSHORT short +#define portSTACK_TYPE uint32_t +#define portBASE_TYPE long + +typedef portSTACK_TYPE StackType_t; +typedef long BaseType_t; +typedef unsigned long UBaseType_t; + +#if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS ) + typedef uint16_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffff #elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS ) - typedef uint32_t TickType_t; - #define portMAX_DELAY ( TickType_t ) 0xffffffffUL + typedef uint32_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffffffffUL - /* 32-bit tick type on a 32-bit architecture, so reads of the tick count do - not need to be guarded with a critical section. */ - #define portTICK_TYPE_IS_ATOMIC 1 +/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do + * not need to be guarded with a critical section. */ + #define portTICK_TYPE_IS_ATOMIC 1 #else #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width. #endif @@ -87,93 +87,98 @@ void microblaze_enable_interrupts( void ); /* Critical section macros. */ void vPortEnterCritical( void ); void vPortExitCritical( void ); -#define portENTER_CRITICAL() { \ - extern volatile UBaseType_t uxCriticalNesting; \ - microblaze_disable_interrupts(); \ - uxCriticalNesting++; \ - } - -#define portEXIT_CRITICAL() { \ - extern volatile UBaseType_t uxCriticalNesting; \ - /* Interrupts are disabled, so we can */ \ - /* access the variable directly. */ \ - uxCriticalNesting--; \ - if( uxCriticalNesting == 0 ) \ - { \ - /* The nesting has unwound and we \ - can enable interrupts again. */ \ - portENABLE_INTERRUPTS(); \ - } \ - } +#define portENTER_CRITICAL() \ + { \ + extern volatile UBaseType_t uxCriticalNesting; \ + microblaze_disable_interrupts(); \ + uxCriticalNesting++; \ + } + +#define portEXIT_CRITICAL() \ + { \ + extern volatile UBaseType_t uxCriticalNesting; \ + /* Interrupts are disabled, so we can */ \ + /* access the variable directly. */ \ + uxCriticalNesting--; \ + if( uxCriticalNesting == 0 ) \ + { \ + /* The nesting has unwound and we \ + * can enable interrupts again. */ \ + portENABLE_INTERRUPTS(); \ + } \ + } /*-----------------------------------------------------------*/ /* The yield macro maps directly to the vPortYield() function. */ void vPortYield( void ); -#define portYIELD() vPortYield() +#define portYIELD() vPortYield() /* portYIELD_FROM_ISR() does not directly call vTaskSwitchContext(), but instead -sets a flag to say that a yield has been requested. The interrupt exit code -then checks this flag, and calls vTaskSwitchContext() before restoring a task -context, if the flag is not false. This is done to prevent multiple calls to -vTaskSwitchContext() being made from a single interrupt, as a single interrupt -can result in multiple peripherals being serviced. */ + * sets a flag to say that a yield has been requested. The interrupt exit code + * then checks this flag, and calls vTaskSwitchContext() before restoring a task + * context, if the flag is not false. This is done to prevent multiple calls to + * vTaskSwitchContext() being made from a single interrupt, as a single interrupt + * can result in multiple peripherals being serviced. */ extern volatile uint32_t ulTaskSwitchRequested; -#define portYIELD_FROM_ISR( x ) do { if( ( x ) != pdFALSE ) ulTaskSwitchRequested = 1; } while( 0 ) +#define portYIELD_FROM_ISR( x ) \ + do { if( ( x ) != pdFALSE ) ulTaskSwitchRequested = 1; } \ + while( 0 ) -#if( configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 ) +#if ( configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 ) - /* Generic helper function. */ +/* Generic helper function. */ __attribute__( ( always_inline ) ) static inline uint8_t ucPortCountLeadingZeros( uint32_t ulBitmap ) { - uint8_t ucReturn; + uint8_t ucReturn; __asm volatile ( "clz %0, %1" : "=r" ( ucReturn ) : "r" ( ulBitmap ) ); + return ucReturn; } - /* Check the configuration. */ - #if( configMAX_PRIORITIES > 32 ) +/* Check the configuration. */ + #if ( configMAX_PRIORITIES > 32 ) #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice. #endif - /* Store/clear the ready priorities in a bit map. */ - #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) ) - #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) ) +/* Store/clear the ready priorities in a bit map. */ + #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) ) + #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) ) - /*-----------------------------------------------------------*/ +/*-----------------------------------------------------------*/ - #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - ( uint32_t ) ucPortCountLeadingZeros( ( uxReadyPriorities ) ) ) + #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - ( uint32_t ) ucPortCountLeadingZeros( ( uxReadyPriorities ) ) ) #endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */ /*-----------------------------------------------------------*/ /* Hardware specifics. */ -#define portBYTE_ALIGNMENT 4 -#define portSTACK_GROWTH ( -1 ) -#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) -#define portNOP() asm volatile ( "NOP" ) -#define portMEMORY_BARRIER() asm volatile ( "" ::: "memory" ) +#define portBYTE_ALIGNMENT 4 +#define portSTACK_GROWTH ( -1 ) +#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) +#define portNOP() asm volatile ( "NOP" ) +#define portMEMORY_BARRIER() asm volatile ( "" ::: "memory" ) /*-----------------------------------------------------------*/ -#if( XPAR_MICROBLAZE_USE_STACK_PROTECTION ) -#define portHAS_STACK_OVERFLOW_CHECKING 1 +#if ( XPAR_MICROBLAZE_USE_STACK_PROTECTION ) + #define portHAS_STACK_OVERFLOW_CHECKING 1 #endif /*-----------------------------------------------------------*/ /* Task function macros as described on the FreeRTOS.org WEB site. */ -#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters ) -#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters ) +#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters ) +#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters ) /*-----------------------------------------------------------*/ /* The following structure is used by the FreeRTOS exception handler. It is -filled with the MicroBlaze context as it was at the time the exception occurred. -This is done as an aid to debugging exception occurrences. */ + * filled with the MicroBlaze context as it was at the time the exception occurred. + * This is done as an aid to debugging exception occurrences. */ typedef struct PORT_REGISTER_DUMP { /* The following structure members hold the values of the MicroBlaze - registers at the time the exception was raised. */ + * registers at the time the exception was raised. */ uint32_t ulR1_SP; uint32_t ulR2_small_data_area; uint32_t ulR3; @@ -213,19 +218,18 @@ typedef struct PORT_REGISTER_DUMP uint32_t ulEDR; /* A human readable description of the exception cause. The strings used - are the same as the #define constant names found in the - microblaze_exceptions_i.h header file */ - int8_t *pcExceptionCause; + * are the same as the #define constant names found in the + * microblaze_exceptions_i.h header file */ + int8_t * pcExceptionCause; /* The human readable name of the task that was running at the time the - exception occurred. This is the name that was given to the task when the - task was created using the FreeRTOS xTaskCreate() API function. */ - char *pcCurrentTaskName; + * exception occurred. This is the name that was given to the task when the + * task was created using the FreeRTOS xTaskCreate() API function. */ + char * pcCurrentTaskName; /* The handle of the task that was running a the time the exception - occurred. */ + * occurred. */ void * xCurrentTaskHandle; - } xPortRegisterDump; @@ -264,7 +268,9 @@ typedef struct PORT_REGISTER_DUMP * pdPASS is returned if the function executes successfully. Any other value * being returned indicates that the function did not execute correctly. */ -BaseType_t xPortInstallInterruptHandler( uint8_t ucInterruptID, XInterruptHandler pxHandler, void *pvCallBackRef ); +BaseType_t xPortInstallInterruptHandler( uint8_t ucInterruptID, + XInterruptHandler pxHandler, + void * pvCallBackRef ); /* @@ -369,7 +375,7 @@ void vPortExceptionsInstallHandlers( void ); * register dump information. For example, an implementation could be provided * that wrote the register dump data to a display, or a UART port. */ -void vApplicationExceptionRegisterDump( xPortRegisterDump *xRegisterDump ); +void vApplicationExceptionRegisterDump( xPortRegisterDump * xRegisterDump ); /* *INDENT-OFF* */ diff --git a/Source/portable/GCC/NiosII/port.c b/Source/portable/GCC/NiosII/port.c index 8ecf1d23e..849096389 100644 --- a/Source/portable/GCC/NiosII/port.c +++ b/Source/portable/GCC/NiosII/port.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -27,8 +27,8 @@ */ /*----------------------------------------------------------- - * Implementation of functions defined in portable.h for the NIOS2 port. - *----------------------------------------------------------*/ +* Implementation of functions defined in portable.h for the NIOS2 port. +*----------------------------------------------------------*/ /* Standard Includes. */ #include @@ -45,10 +45,13 @@ #include "task.h" /* Interrupts are enabled. */ -#define portINITIAL_ESTATUS ( StackType_t ) 0x01 +#define portINITIAL_ESTATUS ( StackType_t ) 0x01 -int _alt_ic_isr_register(alt_u32 ic_id, alt_u32 irq, alt_isr_func isr, - void *isr_context, void *flags); +int _alt_ic_isr_register( alt_u32 ic_id, + alt_u32 irq, + alt_isr_func isr, + void * isr_context, + void * flags ); /*-----------------------------------------------------------*/ /* @@ -59,23 +62,25 @@ static void prvSetupTimerInterrupt( void ); /* * Call back for the alarm function. */ -void vPortSysTickHandler( void * context); +void vPortSysTickHandler( void * context ); /*-----------------------------------------------------------*/ -static void prvReadGp( uint32_t *ulValue ) +static void prvReadGp( uint32_t * ulValue ) { - asm( "stw gp, (%0)" :: "r"(ulValue) ); + asm ( "stw gp, (%0)" ::"r" ( ulValue ) ); } /*-----------------------------------------------------------*/ /* * See header file for description. */ -StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters ) +StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, + TaskFunction_t pxCode, + void * pvParameters ) { -StackType_t *pxFramePointer = pxTopOfStack - 1; -StackType_t xGlobalPointer; + StackType_t * pxFramePointer = pxTopOfStack - 1; + StackType_t xGlobalPointer; prvReadGp( &xGlobalPointer ); @@ -114,12 +119,12 @@ StackType_t xGlobalPointer; BaseType_t xPortStartScheduler( void ) { /* Start the timer that generates the tick ISR. Interrupts are disabled - here already. */ + * here already. */ prvSetupTimerInterrupt(); /* Start the first task. */ - asm volatile ( " movia r2, restore_sp_from_pxCurrentTCB \n" - " jmp r2 " ); + asm volatile ( " movia r2, restore_sp_from_pxCurrentTCB \n" + " jmp r2 " ); /* Should not get here! */ return 0; @@ -129,7 +134,7 @@ BaseType_t xPortStartScheduler( void ) void vPortEndScheduler( void ) { /* It is unlikely that the NIOS2 port will require this function as there - is nothing to return to. */ + * is nothing to return to. */ } /*-----------------------------------------------------------*/ @@ -140,10 +145,10 @@ void vPortEndScheduler( void ) void prvSetupTimerInterrupt( void ) { /* Try to register the interrupt handler. */ - if ( -EINVAL == _alt_ic_isr_register( SYS_CLK_IRQ_INTERRUPT_CONTROLLER_ID, SYS_CLK_IRQ, vPortSysTickHandler, 0x0, 0x0 ) ) + if( -EINVAL == _alt_ic_isr_register( SYS_CLK_IRQ_INTERRUPT_CONTROLLER_ID, SYS_CLK_IRQ, vPortSysTickHandler, 0x0, 0x0 ) ) { /* Failed to install the Interrupt Handler. */ - asm( "break" ); + asm ( "break" ); } else { @@ -159,7 +164,7 @@ void prvSetupTimerInterrupt( void ) } /*-----------------------------------------------------------*/ -void vPortSysTickHandler( void * context) +void vPortSysTickHandler( void * context ) { /* Increment the kernel tick. */ if( xTaskIncrementTick() != pdFALSE ) @@ -178,27 +183,30 @@ void vPortSysTickHandler( void * context) * kernel has its scheduler started so that contexts are saved and switched * correctly. */ -int _alt_ic_isr_register(alt_u32 ic_id, alt_u32 irq, alt_isr_func isr, - void *isr_context, void *flags) +int _alt_ic_isr_register( alt_u32 ic_id, + alt_u32 irq, + alt_isr_func isr, + void * isr_context, + void * flags ) { int rc = -EINVAL; alt_irq_context status; - int id = irq; /* IRQ interpreted as the interrupt ID. */ + int id = irq; /* IRQ interpreted as the interrupt ID. */ - if (id < ALT_NIRQ) + if( id < ALT_NIRQ ) { /* * interrupts are disabled while the handler tables are updated to ensure - * that an interrupt doesn't occur while the tables are in an inconsistant + * that an interrupt doesn't occur while the tables are in an inconsistent * state. */ - status = alt_irq_disable_all (); + status = alt_irq_disable_all(); - alt_irq[id].handler = isr; - alt_irq[id].context = isr_context; + alt_irq[ id ].handler = isr; + alt_irq[ id ].context = isr_context; - rc = (isr) ? alt_ic_irq_enable(ic_id, id) : alt_ic_irq_disable(ic_id, id); + rc = ( isr ) ? alt_ic_irq_enable( ic_id, id ) : alt_ic_irq_disable( ic_id, id ); /* alt_irq_enable_all(status); This line is removed to prevent the interrupt from being immediately enabled. */ } diff --git a/Source/portable/GCC/NiosII/port_asm.S b/Source/portable/GCC/NiosII/port_asm.S index 23bb73f24..699d7f12b 100644 --- a/Source/portable/GCC/NiosII/port_asm.S +++ b/Source/portable/GCC/NiosII/port_asm.S @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/Source/portable/GCC/NiosII/portmacro.h b/Source/portable/GCC/NiosII/portmacro.h index c20698e41..cc3cce907 100644 --- a/Source/portable/GCC/NiosII/portmacro.h +++ b/Source/portable/GCC/NiosII/portmacro.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -48,48 +48,59 @@ */ /* Type definitions. */ -#define portCHAR char -#define portFLOAT float -#define portDOUBLE double -#define portLONG long -#define portSHORT short -#define portSTACK_TYPE uint32_t -#define portBASE_TYPE long - -typedef portSTACK_TYPE StackType_t; -typedef long BaseType_t; -typedef unsigned long UBaseType_t; - -#if( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS ) - typedef uint16_t TickType_t; - #define portMAX_DELAY ( TickType_t ) 0xffff +#define portCHAR char +#define portFLOAT float +#define portDOUBLE double +#define portLONG long +#define portSHORT short +#define portSTACK_TYPE uint32_t +#define portBASE_TYPE long + +typedef portSTACK_TYPE StackType_t; +typedef long BaseType_t; +typedef unsigned long UBaseType_t; + +#if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS ) + typedef uint16_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffff #elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS ) - typedef uint32_t TickType_t; - #define portMAX_DELAY ( TickType_t ) 0xffffffffUL + typedef uint32_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffffffffUL - /* 32-bit tick type on a 32-bit architecture, so reads of the tick count do - not need to be guarded with a critical section. */ - #define portTICK_TYPE_IS_ATOMIC 1 +/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do + * not need to be guarded with a critical section. */ + #define portTICK_TYPE_IS_ATOMIC 1 #else #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width. #endif /*-----------------------------------------------------------*/ /* Architecture specifics. */ -#define portSTACK_GROWTH ( -1 ) -#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) -#define portBYTE_ALIGNMENT 4 -#define portNOP() asm volatile ( "NOP" ) -#define portCRITICAL_NESTING_IN_TCB 1 +#define portSTACK_GROWTH ( -1 ) +#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) +#define portBYTE_ALIGNMENT 4 +#define portNOP() asm volatile ( "NOP" ) +#define portCRITICAL_NESTING_IN_TCB 1 /*-----------------------------------------------------------*/ extern void vTaskSwitchContext( void ); -#define portYIELD() asm volatile ( "trap" ); -#define portEND_SWITCHING_ISR( xSwitchRequired ) do { if( xSwitchRequired ) vTaskSwitchContext(); } while( 0 ) - +#define portYIELD() asm volatile ( "trap" ); +#define portEND_SWITCHING_ISR( xSwitchRequired ) \ + do \ + { \ + if( xSwitchRequired != pdFALSE ) \ + { \ + traceISR_EXIT_TO_SCHEDULER(); \ + vTaskSwitchContext(); \ + } \ + else \ + { \ + traceISR_EXIT(); \ + } \ + } while( 0 ) /* Include the port_asm.S file where the Context saving/restoring is defined. */ -__asm__( "\n\t.globl save_context" ); +__asm__ ( "\n\t.globl save_context" ); /*-----------------------------------------------------------*/ @@ -103,8 +114,8 @@ extern void vTaskExitCritical( void ); /*-----------------------------------------------------------*/ /* Task function macros as described on the FreeRTOS.org WEB site. */ -#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters ) -#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters ) +#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters ) +#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters ) /* *INDENT-OFF* */ #ifdef __cplusplus diff --git a/Source/portable/GCC/PPC405_Xilinx/FPU_Macros.h b/Source/portable/GCC/PPC405_Xilinx/FPU_Macros.h index 153892add..bff1fa49a 100644 --- a/Source/portable/GCC/PPC405_Xilinx/FPU_Macros.h +++ b/Source/portable/GCC/PPC405_Xilinx/FPU_Macros.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -27,16 +27,16 @@ */ /* When switching out a task, if the task tag contains a buffer address then -save the flop context into the buffer. */ -#define traceTASK_SWITCHED_OUT() \ - if( pxCurrentTCB->pxTaskTag != NULL ) \ - { \ - extern void vPortSaveFPURegisters( void * ); \ - vPortSaveFPURegisters( ( void * ) ( pxCurrentTCB->pxTaskTag ) ); \ + * save the flop context into the buffer. */ +#define traceTASK_SWITCHED_OUT() \ + if( pxCurrentTCB->pxTaskTag != NULL ) \ + { \ + extern void vPortSaveFPURegisters( void * ); \ + vPortSaveFPURegisters( ( void * ) ( pxCurrentTCB->pxTaskTag ) ); \ } /* When switching in a task, if the task tag contains a buffer address then -load the flop context from the buffer. */ + * load the flop context from the buffer. */ #define traceTASK_SWITCHED_IN() \ if( pxCurrentTCB->pxTaskTag != NULL ) \ { \ diff --git a/Source/portable/GCC/PPC405_Xilinx/port.c b/Source/portable/GCC/PPC405_Xilinx/port.c index cba0f916b..36d8bb986 100644 --- a/Source/portable/GCC/PPC405_Xilinx/port.c +++ b/Source/portable/GCC/PPC405_Xilinx/port.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -27,8 +27,8 @@ */ /*----------------------------------------------------------- - * Implementation of functions defined in portable.h for the PPC405 port. - *----------------------------------------------------------*/ +* Implementation of functions defined in portable.h for the PPC405 port. +*----------------------------------------------------------*/ /* Scheduler includes. */ @@ -43,19 +43,19 @@ /*-----------------------------------------------------------*/ /* Definitions to set the initial MSR of each task. */ -#define portCRITICAL_INTERRUPT_ENABLE ( 1UL << 17UL ) -#define portEXTERNAL_INTERRUPT_ENABLE ( 1UL << 15UL ) -#define portMACHINE_CHECK_ENABLE ( 1UL << 12UL ) +#define portCRITICAL_INTERRUPT_ENABLE ( 1UL << 17UL ) +#define portEXTERNAL_INTERRUPT_ENABLE ( 1UL << 15UL ) +#define portMACHINE_CHECK_ENABLE ( 1UL << 12UL ) #if configUSE_FPU == 1 - #define portAPU_PRESENT ( 1UL << 25UL ) - #define portFCM_FPU_PRESENT ( 1UL << 13UL ) + #define portAPU_PRESENT ( 1UL << 25UL ) + #define portFCM_FPU_PRESENT ( 1UL << 13UL ) #else - #define portAPU_PRESENT ( 0UL ) - #define portFCM_FPU_PRESENT ( 0UL ) + #define portAPU_PRESENT ( 0UL ) + #define portFCM_FPU_PRESENT ( 0UL ) #endif -#define portINITIAL_MSR ( portCRITICAL_INTERRUPT_ENABLE | portEXTERNAL_INTERRUPT_ENABLE | portMACHINE_CHECK_ENABLE | portAPU_PRESENT | portFCM_FPU_PRESENT ) +#define portINITIAL_MSR ( portCRITICAL_INTERRUPT_ENABLE | portEXTERNAL_INTERRUPT_ENABLE | portMACHINE_CHECK_ENABLE | portAPU_PRESENT | portFCM_FPU_PRESENT ) extern const unsigned _SDA_BASE_; @@ -97,7 +97,9 @@ static XIntc xInterruptController; * * See the header file portable.h. */ -StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters ) +StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, + TaskFunction_t pxCode, + void * pvParameters ) { /* Place a known value at the bottom of the stack for debugging. */ *pxTopOfStack = 0xDEADBEEF; @@ -115,30 +117,30 @@ StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t px pxTopOfStack--; /* Parameters in R2. */ - *pxTopOfStack = ( StackType_t ) &_SDA2_BASE_; /* address of the second small data area */ + *pxTopOfStack = ( StackType_t ) &_SDA2_BASE_; /* address of the second small data area */ pxTopOfStack--; /* R1 is the stack pointer so is omitted. */ - *pxTopOfStack = 0x10000001UL;; /* R0. */ + *pxTopOfStack = 0x10000001UL; /* R0. */ pxTopOfStack--; - *pxTopOfStack = 0x00000000UL; /* USPRG0. */ + *pxTopOfStack = 0x00000000UL; /* USPRG0. */ pxTopOfStack--; - *pxTopOfStack = 0x00000000UL; /* CR. */ + *pxTopOfStack = 0x00000000UL; /* CR. */ pxTopOfStack--; - *pxTopOfStack = 0x00000000UL; /* XER. */ + *pxTopOfStack = 0x00000000UL; /* XER. */ pxTopOfStack--; - *pxTopOfStack = 0x00000000UL; /* CTR. */ + *pxTopOfStack = 0x00000000UL; /* CTR. */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) vPortEndScheduler; /* LR. */ + *pxTopOfStack = ( StackType_t ) vPortEndScheduler; /* LR. */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) pxCode; /* SRR0. */ + *pxTopOfStack = ( StackType_t ) pxCode; /* SRR0. */ pxTopOfStack--; - *pxTopOfStack = portINITIAL_MSR;/* SRR1. */ + *pxTopOfStack = portINITIAL_MSR; /* SRR1. */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) vPortEndScheduler;/* Next LR. */ + *pxTopOfStack = ( StackType_t ) vPortEndScheduler; /* Next LR. */ pxTopOfStack--; - *pxTopOfStack = 0x00000000UL;/* Backchain. */ + *pxTopOfStack = 0x00000000UL; /* Backchain. */ return pxTopOfStack; } @@ -158,7 +160,9 @@ BaseType_t xPortStartScheduler( void ) void vPortEndScheduler( void ) { /* Not implemented. */ - for( ;; ); + for( ; ; ) + { + } } /*-----------------------------------------------------------*/ @@ -167,7 +171,7 @@ void vPortEndScheduler( void ) */ static void prvSetupTimerInterrupt( void ) { -const uint32_t ulInterval = ( ( configCPU_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL ); + const uint32_t ulInterval = ( ( configCPU_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL ); XTime_PITClearInterrupt(); XTime_FITClearInterrupt(); @@ -183,18 +187,18 @@ const uint32_t ulInterval = ( ( configCPU_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL } /*-----------------------------------------------------------*/ -void vPortISRHandler( void *pvNullDoNotUse ) +void vPortISRHandler( void * pvNullDoNotUse ) { -uint32_t ulInterruptStatus, ulInterruptMask = 1UL; -BaseType_t xInterruptNumber; -XIntc_Config *pxInterruptController; -XIntc_VectorTableEntry *pxTable; + uint32_t ulInterruptStatus, ulInterruptMask = 1UL; + BaseType_t xInterruptNumber; + XIntc_Config * pxInterruptController; + XIntc_VectorTableEntry * pxTable; /* Just to remove compiler warning. */ ( void ) pvNullDoNotUse; /* Get the configuration by using the device ID - in this case it is - assumed that only one interrupt controller is being used. */ + * assumed that only one interrupt controller is being used. */ pxInterruptController = &XIntc_ConfigTable[ XPAR_XPS_INTC_0_DEVICE_ID ]; /* Which interrupts are pending? */ @@ -227,29 +231,31 @@ XIntc_VectorTableEntry *pxTable; void vPortSetupInterruptController( void ) { -extern void vPortISRWrapper( void ); + extern void vPortISRWrapper( void ); /* Perform all library calls necessary to initialise the exception table - and interrupt controller. This assumes only one interrupt controller is in - use. */ + * and interrupt controller. This assumes only one interrupt controller is in + * use. */ XExc_mDisableExceptions( XEXC_NON_CRITICAL ); XExc_Init(); /* The library functions save the context - we then jump to a wrapper to - save the stack into the TCB. The wrapper then calls the handler defined - above. */ + * save the stack into the TCB. The wrapper then calls the handler defined + * above. */ XExc_RegisterHandler( XEXC_ID_NON_CRITICAL_INT, ( XExceptionHandler ) vPortISRWrapper, NULL ); XIntc_Initialize( &xInterruptController, XPAR_XPS_INTC_0_DEVICE_ID ); XIntc_Start( &xInterruptController, XIN_REAL_MODE ); } /*-----------------------------------------------------------*/ -BaseType_t xPortInstallInterruptHandler( uint8_t ucInterruptID, XInterruptHandler pxHandler, void *pvCallBackRef ) +BaseType_t xPortInstallInterruptHandler( uint8_t ucInterruptID, + XInterruptHandler pxHandler, + void * pvCallBackRef ) { -BaseType_t xReturn = pdFAIL; + BaseType_t xReturn = pdFAIL; /* This function is defined here so the scope of xInterruptController can - remain within this file. */ + * remain within this file. */ if( XST_SUCCESS == XIntc_Connect( &xInterruptController, ucInterruptID, pxHandler, pvCallBackRef ) ) { diff --git a/Source/portable/GCC/PPC405_Xilinx/portasm.S b/Source/portable/GCC/PPC405_Xilinx/portasm.S index 26dcc5622..8ce77ca22 100644 --- a/Source/portable/GCC/PPC405_Xilinx/portasm.S +++ b/Source/portable/GCC/PPC405_Xilinx/portasm.S @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/Source/portable/GCC/PPC405_Xilinx/portmacro.h b/Source/portable/GCC/PPC405_Xilinx/portmacro.h index 0c119cbc5..d436440c5 100644 --- a/Source/portable/GCC/PPC405_Xilinx/portmacro.h +++ b/Source/portable/GCC/PPC405_Xilinx/portmacro.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -48,72 +48,74 @@ */ /* Type definitions. */ -#define portCHAR char -#define portFLOAT float -#define portDOUBLE double -#define portLONG long -#define portSHORT short -#define portSTACK_TYPE uint32_t -#define portBASE_TYPE long - -typedef portSTACK_TYPE StackType_t; -typedef long BaseType_t; -typedef unsigned long UBaseType_t; - -#if( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS ) - typedef uint16_t TickType_t; - #define portMAX_DELAY ( TickType_t ) 0xffff +#define portCHAR char +#define portFLOAT float +#define portDOUBLE double +#define portLONG long +#define portSHORT short +#define portSTACK_TYPE uint32_t +#define portBASE_TYPE long + +typedef portSTACK_TYPE StackType_t; +typedef long BaseType_t; +typedef unsigned long UBaseType_t; + +#if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS ) + typedef uint16_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffff #elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS ) - typedef uint32_t TickType_t; - #define portMAX_DELAY ( TickType_t ) ( 0xFFFFFFFFUL ) + typedef uint32_t TickType_t; + #define portMAX_DELAY ( TickType_t ) ( 0xFFFFFFFFUL ) #else #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width. #endif /*-----------------------------------------------------------*/ /* This port uses the critical nesting count from the TCB rather than -maintaining a separate value and then saving this value in the task stack. */ -#define portCRITICAL_NESTING_IN_TCB 1 + * maintaining a separate value and then saving this value in the task stack. */ +#define portCRITICAL_NESTING_IN_TCB 1 /* Interrupt control macros. */ -#define portDISABLE_INTERRUPTS() XExc_mDisableExceptions( XEXC_NON_CRITICAL ); -#define portENABLE_INTERRUPTS() XExc_mEnableExceptions( XEXC_NON_CRITICAL ); +#define portDISABLE_INTERRUPTS() XExc_mDisableExceptions( XEXC_NON_CRITICAL ); +#define portENABLE_INTERRUPTS() XExc_mEnableExceptions( XEXC_NON_CRITICAL ); /*-----------------------------------------------------------*/ /* Critical section macros. */ void vTaskEnterCritical( void ); void vTaskExitCritical( void ); -#define portENTER_CRITICAL() vTaskEnterCritical() -#define portEXIT_CRITICAL() vTaskExitCritical() +#define portENTER_CRITICAL() vTaskEnterCritical() +#define portEXIT_CRITICAL() vTaskExitCritical() /*-----------------------------------------------------------*/ /* Task utilities. */ void vPortYield( void ); -#define portYIELD() asm volatile ( "SC \n\t NOP" ) -#define portYIELD_FROM_ISR() vTaskSwitchContext() +#define portYIELD() asm volatile ( "SC \n\t NOP" ) +#define portYIELD_FROM_ISR() vTaskSwitchContext() /*-----------------------------------------------------------*/ /* Hardware specifics. */ -#define portBYTE_ALIGNMENT 8 -#define portSTACK_GROWTH ( -1 ) -#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) -#define portNOP() asm volatile ( "NOP" ) +#define portBYTE_ALIGNMENT 8 +#define portSTACK_GROWTH ( -1 ) +#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) +#define portNOP() asm volatile ( "NOP" ) -/* There are 32 * 32bit floating point regieters, plus the FPSCR to save. */ -#define portNO_FLOP_REGISTERS_TO_SAVE ( 32 + 1 ) +/* There are 32 * 32bit floating point registers, plus the FPSCR to save. */ +#define portNO_FLOP_REGISTERS_TO_SAVE ( 32 + 1 ) /*-----------------------------------------------------------*/ /* Task function macros as described on the FreeRTOS.org WEB site. */ -#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters ) -#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters ) +#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters ) +#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters ) /* Port specific interrupt handling functions. */ void vPortSetupInterruptController( void ); -BaseType_t xPortInstallInterruptHandler( uint8_t ucInterruptID, XInterruptHandler pxHandler, void *pvCallBackRef ); +BaseType_t xPortInstallInterruptHandler( uint8_t ucInterruptID, + XInterruptHandler pxHandler, + void * pvCallBackRef ); /* *INDENT-OFF* */ #ifdef __cplusplus diff --git a/Source/portable/GCC/PPC440_Xilinx/FPU_Macros.h b/Source/portable/GCC/PPC440_Xilinx/FPU_Macros.h index 153892add..bff1fa49a 100644 --- a/Source/portable/GCC/PPC440_Xilinx/FPU_Macros.h +++ b/Source/portable/GCC/PPC440_Xilinx/FPU_Macros.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -27,16 +27,16 @@ */ /* When switching out a task, if the task tag contains a buffer address then -save the flop context into the buffer. */ -#define traceTASK_SWITCHED_OUT() \ - if( pxCurrentTCB->pxTaskTag != NULL ) \ - { \ - extern void vPortSaveFPURegisters( void * ); \ - vPortSaveFPURegisters( ( void * ) ( pxCurrentTCB->pxTaskTag ) ); \ + * save the flop context into the buffer. */ +#define traceTASK_SWITCHED_OUT() \ + if( pxCurrentTCB->pxTaskTag != NULL ) \ + { \ + extern void vPortSaveFPURegisters( void * ); \ + vPortSaveFPURegisters( ( void * ) ( pxCurrentTCB->pxTaskTag ) ); \ } /* When switching in a task, if the task tag contains a buffer address then -load the flop context from the buffer. */ + * load the flop context from the buffer. */ #define traceTASK_SWITCHED_IN() \ if( pxCurrentTCB->pxTaskTag != NULL ) \ { \ diff --git a/Source/portable/GCC/PPC440_Xilinx/port.c b/Source/portable/GCC/PPC440_Xilinx/port.c index 6201d6738..218064020 100644 --- a/Source/portable/GCC/PPC440_Xilinx/port.c +++ b/Source/portable/GCC/PPC440_Xilinx/port.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -27,8 +27,8 @@ */ /*----------------------------------------------------------- - * Implementation of functions defined in portable.h for the PPC440 port. - *----------------------------------------------------------*/ +* Implementation of functions defined in portable.h for the PPC440 port. +*----------------------------------------------------------*/ /* Scheduler includes. */ @@ -43,19 +43,19 @@ /*-----------------------------------------------------------*/ /* Definitions to set the initial MSR of each task. */ -#define portCRITICAL_INTERRUPT_ENABLE ( 1UL << 17UL ) -#define portEXTERNAL_INTERRUPT_ENABLE ( 1UL << 15UL ) -#define portMACHINE_CHECK_ENABLE ( 1UL << 12UL ) +#define portCRITICAL_INTERRUPT_ENABLE ( 1UL << 17UL ) +#define portEXTERNAL_INTERRUPT_ENABLE ( 1UL << 15UL ) +#define portMACHINE_CHECK_ENABLE ( 1UL << 12UL ) #if configUSE_FPU == 1 - #define portAPU_PRESENT ( 1UL << 25UL ) - #define portFCM_FPU_PRESENT ( 1UL << 13UL ) + #define portAPU_PRESENT ( 1UL << 25UL ) + #define portFCM_FPU_PRESENT ( 1UL << 13UL ) #else - #define portAPU_PRESENT ( 0UL ) - #define portFCM_FPU_PRESENT ( 0UL ) + #define portAPU_PRESENT ( 0UL ) + #define portFCM_FPU_PRESENT ( 0UL ) #endif -#define portINITIAL_MSR ( portCRITICAL_INTERRUPT_ENABLE | portEXTERNAL_INTERRUPT_ENABLE | portMACHINE_CHECK_ENABLE | portAPU_PRESENT | portFCM_FPU_PRESENT ) +#define portINITIAL_MSR ( portCRITICAL_INTERRUPT_ENABLE | portEXTERNAL_INTERRUPT_ENABLE | portMACHINE_CHECK_ENABLE | portAPU_PRESENT | portFCM_FPU_PRESENT ) extern const unsigned _SDA_BASE_; @@ -97,7 +97,9 @@ static XIntc xInterruptController; * * See the header file portable.h. */ -StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters ) +StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, + TaskFunction_t pxCode, + void * pvParameters ) { /* Place a known value at the bottom of the stack for debugging. */ *pxTopOfStack = 0xDEADBEEF; @@ -115,30 +117,30 @@ StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t px pxTopOfStack--; /* Parameters in R2. */ - *pxTopOfStack = ( StackType_t ) &_SDA2_BASE_; /* address of the second small data area */ + *pxTopOfStack = ( StackType_t ) &_SDA2_BASE_; /* address of the second small data area */ pxTopOfStack--; /* R1 is the stack pointer so is omitted. */ - *pxTopOfStack = 0x10000001UL;; /* R0. */ + *pxTopOfStack = 0x10000001UL; /* R0. */ pxTopOfStack--; - *pxTopOfStack = 0x00000000UL; /* USPRG0. */ + *pxTopOfStack = 0x00000000UL; /* USPRG0. */ pxTopOfStack--; - *pxTopOfStack = 0x00000000UL; /* CR. */ + *pxTopOfStack = 0x00000000UL; /* CR. */ pxTopOfStack--; - *pxTopOfStack = 0x00000000UL; /* XER. */ + *pxTopOfStack = 0x00000000UL; /* XER. */ pxTopOfStack--; - *pxTopOfStack = 0x00000000UL; /* CTR. */ + *pxTopOfStack = 0x00000000UL; /* CTR. */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) vPortEndScheduler; /* LR. */ + *pxTopOfStack = ( StackType_t ) vPortEndScheduler; /* LR. */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) pxCode; /* SRR0. */ + *pxTopOfStack = ( StackType_t ) pxCode; /* SRR0. */ pxTopOfStack--; - *pxTopOfStack = portINITIAL_MSR;/* SRR1. */ + *pxTopOfStack = portINITIAL_MSR; /* SRR1. */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) vPortEndScheduler;/* Next LR. */ + *pxTopOfStack = ( StackType_t ) vPortEndScheduler; /* Next LR. */ pxTopOfStack--; - *pxTopOfStack = 0x00000000UL;/* Backchain. */ + *pxTopOfStack = 0x00000000UL; /* Backchain. */ return pxTopOfStack; } @@ -158,7 +160,9 @@ BaseType_t xPortStartScheduler( void ) void vPortEndScheduler( void ) { /* Not implemented. */ - for( ;; ); + for( ; ; ) + { + } } /*-----------------------------------------------------------*/ @@ -167,7 +171,7 @@ void vPortEndScheduler( void ) */ static void prvSetupTimerInterrupt( void ) { -const uint32_t ulInterval = ( ( configCPU_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL ); + const uint32_t ulInterval = ( ( configCPU_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL ); XTime_DECClearInterrupt(); XTime_FITClearInterrupt(); @@ -183,18 +187,18 @@ const uint32_t ulInterval = ( ( configCPU_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL } /*-----------------------------------------------------------*/ -void vPortISRHandler( void *pvNullDoNotUse ) +void vPortISRHandler( void * pvNullDoNotUse ) { -uint32_t ulInterruptStatus, ulInterruptMask = 1UL; -BaseType_t xInterruptNumber; -XIntc_Config *pxInterruptController; -XIntc_VectorTableEntry *pxTable; + uint32_t ulInterruptStatus, ulInterruptMask = 1UL; + BaseType_t xInterruptNumber; + XIntc_Config * pxInterruptController; + XIntc_VectorTableEntry * pxTable; /* Just to remove compiler warning. */ ( void ) pvNullDoNotUse; /* Get the configuration by using the device ID - in this case it is - assumed that only one interrupt controller is being used. */ + * assumed that only one interrupt controller is being used. */ pxInterruptController = &XIntc_ConfigTable[ XPAR_XPS_INTC_0_DEVICE_ID ]; /* Which interrupts are pending? */ @@ -227,29 +231,31 @@ XIntc_VectorTableEntry *pxTable; void vPortSetupInterruptController( void ) { -extern void vPortISRWrapper( void ); + extern void vPortISRWrapper( void ); /* Perform all library calls necessary to initialise the exception table - and interrupt controller. This assumes only one interrupt controller is in - use. */ + * and interrupt controller. This assumes only one interrupt controller is in + * use. */ XExc_mDisableExceptions( XEXC_NON_CRITICAL ); XExc_Init(); /* The library functions save the context - we then jump to a wrapper to - save the stack into the TCB. The wrapper then calls the handler defined - above. */ + * save the stack into the TCB. The wrapper then calls the handler defined + * above. */ XExc_RegisterHandler( XEXC_ID_NON_CRITICAL_INT, ( XExceptionHandler ) vPortISRWrapper, NULL ); XIntc_Initialize( &xInterruptController, XPAR_XPS_INTC_0_DEVICE_ID ); XIntc_Start( &xInterruptController, XIN_REAL_MODE ); } /*-----------------------------------------------------------*/ -BaseType_t xPortInstallInterruptHandler( uint8_t ucInterruptID, XInterruptHandler pxHandler, void *pvCallBackRef ) +BaseType_t xPortInstallInterruptHandler( uint8_t ucInterruptID, + XInterruptHandler pxHandler, + void * pvCallBackRef ) { -BaseType_t xReturn = pdFAIL; + BaseType_t xReturn = pdFAIL; /* This function is defined here so the scope of xInterruptController can - remain within this file. */ + * remain within this file. */ if( XST_SUCCESS == XIntc_Connect( &xInterruptController, ucInterruptID, pxHandler, pvCallBackRef ) ) { diff --git a/Source/portable/GCC/PPC440_Xilinx/portasm.S b/Source/portable/GCC/PPC440_Xilinx/portasm.S index 26dcc5622..8ce77ca22 100644 --- a/Source/portable/GCC/PPC440_Xilinx/portasm.S +++ b/Source/portable/GCC/PPC440_Xilinx/portasm.S @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/Source/portable/GCC/PPC440_Xilinx/portmacro.h b/Source/portable/GCC/PPC440_Xilinx/portmacro.h index 0c119cbc5..d436440c5 100644 --- a/Source/portable/GCC/PPC440_Xilinx/portmacro.h +++ b/Source/portable/GCC/PPC440_Xilinx/portmacro.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -48,72 +48,74 @@ */ /* Type definitions. */ -#define portCHAR char -#define portFLOAT float -#define portDOUBLE double -#define portLONG long -#define portSHORT short -#define portSTACK_TYPE uint32_t -#define portBASE_TYPE long - -typedef portSTACK_TYPE StackType_t; -typedef long BaseType_t; -typedef unsigned long UBaseType_t; - -#if( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS ) - typedef uint16_t TickType_t; - #define portMAX_DELAY ( TickType_t ) 0xffff +#define portCHAR char +#define portFLOAT float +#define portDOUBLE double +#define portLONG long +#define portSHORT short +#define portSTACK_TYPE uint32_t +#define portBASE_TYPE long + +typedef portSTACK_TYPE StackType_t; +typedef long BaseType_t; +typedef unsigned long UBaseType_t; + +#if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS ) + typedef uint16_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffff #elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS ) - typedef uint32_t TickType_t; - #define portMAX_DELAY ( TickType_t ) ( 0xFFFFFFFFUL ) + typedef uint32_t TickType_t; + #define portMAX_DELAY ( TickType_t ) ( 0xFFFFFFFFUL ) #else #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width. #endif /*-----------------------------------------------------------*/ /* This port uses the critical nesting count from the TCB rather than -maintaining a separate value and then saving this value in the task stack. */ -#define portCRITICAL_NESTING_IN_TCB 1 + * maintaining a separate value and then saving this value in the task stack. */ +#define portCRITICAL_NESTING_IN_TCB 1 /* Interrupt control macros. */ -#define portDISABLE_INTERRUPTS() XExc_mDisableExceptions( XEXC_NON_CRITICAL ); -#define portENABLE_INTERRUPTS() XExc_mEnableExceptions( XEXC_NON_CRITICAL ); +#define portDISABLE_INTERRUPTS() XExc_mDisableExceptions( XEXC_NON_CRITICAL ); +#define portENABLE_INTERRUPTS() XExc_mEnableExceptions( XEXC_NON_CRITICAL ); /*-----------------------------------------------------------*/ /* Critical section macros. */ void vTaskEnterCritical( void ); void vTaskExitCritical( void ); -#define portENTER_CRITICAL() vTaskEnterCritical() -#define portEXIT_CRITICAL() vTaskExitCritical() +#define portENTER_CRITICAL() vTaskEnterCritical() +#define portEXIT_CRITICAL() vTaskExitCritical() /*-----------------------------------------------------------*/ /* Task utilities. */ void vPortYield( void ); -#define portYIELD() asm volatile ( "SC \n\t NOP" ) -#define portYIELD_FROM_ISR() vTaskSwitchContext() +#define portYIELD() asm volatile ( "SC \n\t NOP" ) +#define portYIELD_FROM_ISR() vTaskSwitchContext() /*-----------------------------------------------------------*/ /* Hardware specifics. */ -#define portBYTE_ALIGNMENT 8 -#define portSTACK_GROWTH ( -1 ) -#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) -#define portNOP() asm volatile ( "NOP" ) +#define portBYTE_ALIGNMENT 8 +#define portSTACK_GROWTH ( -1 ) +#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) +#define portNOP() asm volatile ( "NOP" ) -/* There are 32 * 32bit floating point regieters, plus the FPSCR to save. */ -#define portNO_FLOP_REGISTERS_TO_SAVE ( 32 + 1 ) +/* There are 32 * 32bit floating point registers, plus the FPSCR to save. */ +#define portNO_FLOP_REGISTERS_TO_SAVE ( 32 + 1 ) /*-----------------------------------------------------------*/ /* Task function macros as described on the FreeRTOS.org WEB site. */ -#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters ) -#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters ) +#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters ) +#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters ) /* Port specific interrupt handling functions. */ void vPortSetupInterruptController( void ); -BaseType_t xPortInstallInterruptHandler( uint8_t ucInterruptID, XInterruptHandler pxHandler, void *pvCallBackRef ); +BaseType_t xPortInstallInterruptHandler( uint8_t ucInterruptID, + XInterruptHandler pxHandler, + void * pvCallBackRef ); /* *INDENT-OFF* */ #ifdef __cplusplus diff --git a/Source/portable/GCC/RISC-V/chip_extensions.cmake b/Source/portable/GCC/RISC-V/chip_extensions.cmake new file mode 100644 index 000000000..c0d2c0d86 --- /dev/null +++ b/Source/portable/GCC/RISC-V/chip_extensions.cmake @@ -0,0 +1,19 @@ +if( FREERTOS_PORT STREQUAL "GCC_RISC_V_GENERIC" ) + set( VALID_CHIP_EXTENSIONS + "Pulpino_Vega_RV32M1RM" + "RISCV_MTIME_CLINT_no_extensions" + "RISCV_no_extensions" + "RV32I_CLINT_no_extensions" ) + + if( ( NOT FREERTOS_RISCV_EXTENSION ) OR ( NOT ( ${FREERTOS_RISCV_EXTENSION} IN_LIST VALID_CHIP_EXTENSIONS ) ) ) + message(FATAL_ERROR + "FREERTOS_RISCV_EXTENSION \"${FREERTOS_RISCV_EXTENSION}\" is not set or unsupported.\n" + "Please specify it from top-level CMake file (example):\n" + " set(FREERTOS_RISCV_EXTENSION RISCV_MTIME_CLINT_no_extensions CACHE STRING \"\")\n" + " or from CMake command line option:\n" + " -DFREERTOS_RISCV_EXTENSION=RISCV_MTIME_CLINT_no_extensions\n" + "\n" + " Available extension options:\n" + " ${VALID_CHIP_EXTENSIONS} \n") + endif() +endif() diff --git a/Source/portable/GCC/RISC-V/chip_specific_extensions/Pulpino_Vega_RV32M1RM/freertos_risc_v_chip_specific_extensions.h b/Source/portable/GCC/RISC-V/chip_specific_extensions/Pulpino_Vega_RV32M1RM/freertos_risc_v_chip_specific_extensions.h index 3a2629906..5209b51e5 100644 --- a/Source/portable/GCC/RISC-V/chip_specific_extensions/Pulpino_Vega_RV32M1RM/freertos_risc_v_chip_specific_extensions.h +++ b/Source/portable/GCC/RISC-V/chip_specific_extensions/Pulpino_Vega_RV32M1RM/freertos_risc_v_chip_specific_extensions.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -58,51 +58,51 @@ #ifndef __FREERTOS_RISC_V_EXTENSIONS_H__ #define __FREERTOS_RISC_V_EXTENSIONS_H__ -#define portasmHAS_MTIME 0 +#define portasmHAS_MTIME 0 /* Constants to define the additional registers found on the Pulpino RI5KY. */ -#define lpstart0 0x7b0 -#define lpend0 0x7b1 -#define lpcount0 0x7b2 -#define lpstart1 0x7b4 -#define lpend1 0x7b5 -#define lpcount1 0x7b6 +#define lpstart0 0x7b0 +#define lpend0 0x7b1 +#define lpcount0 0x7b2 +#define lpstart1 0x7b4 +#define lpend1 0x7b5 +#define lpcount1 0x7b6 /* Six additional registers to save and restore, as per the #defines above. */ -#define portasmADDITIONAL_CONTEXT_SIZE 6 /* Must be even number on 32-bit cores. */ +#define portasmADDITIONAL_CONTEXT_SIZE 6 /* Must be even number on 32-bit cores. */ /* Save additional registers found on the Pulpino. */ .macro portasmSAVE_ADDITIONAL_REGISTERS - addi sp, sp, -(portasmADDITIONAL_CONTEXT_SIZE * portWORD_SIZE) /* Make room for the additional registers. */ - csrr t0, lpstart0 /* Load additional registers into accessible temporary registers. */ - csrr t1, lpend0 - csrr t2, lpcount0 - csrr t3, lpstart1 - csrr t4, lpend1 - csrr t5, lpcount1 - sw t0, 1 * portWORD_SIZE( sp ) - sw t1, 2 * portWORD_SIZE( sp ) - sw t2, 3 * portWORD_SIZE( sp ) - sw t3, 4 * portWORD_SIZE( sp ) - sw t4, 5 * portWORD_SIZE( sp ) - sw t5, 6 * portWORD_SIZE( sp ) - .endm +addi sp, sp, -( portasmADDITIONAL_CONTEXT_SIZE * portWORD_SIZE ) /* Make room for the additional registers. */ +csrr t0, lpstart0 /* Load additional registers into accessible temporary registers. */ +csrr t1, lpend0 +csrr t2, lpcount0 +csrr t3, lpstart1 +csrr t4, lpend1 +csrr t5, lpcount1 +sw t0, 1 * portWORD_SIZE( sp ) +sw t1, 2 * portWORD_SIZE( sp ) +sw t2, 3 * portWORD_SIZE( sp ) +sw t3, 4 * portWORD_SIZE( sp ) +sw t4, 5 * portWORD_SIZE( sp ) +sw t5, 6 * portWORD_SIZE( sp ) + .endm /* Restore the additional registers found on the Pulpino. */ -.macro portasmRESTORE_ADDITIONAL_REGISTERS - lw t0, 1 * portWORD_SIZE( sp ) /* Load additional registers into accessible temporary registers. */ - lw t1, 2 * portWORD_SIZE( sp ) - lw t2, 3 * portWORD_SIZE( sp ) - lw t3, 4 * portWORD_SIZE( sp ) - lw t4, 5 * portWORD_SIZE( sp ) - lw t5, 6 * portWORD_SIZE( sp ) - csrw lpstart0, t0 - csrw lpend0, t1 - csrw lpcount0, t2 - csrw lpstart1, t3 - csrw lpend1, t4 - csrw lpcount1, t5 - addi sp, sp, (portasmADDITIONAL_CONTEXT_SIZE * portWORD_SIZE )/* Remove space added for additional registers. */ - .endm + .macro portasmRESTORE_ADDITIONAL_REGISTERS +lw t0, 1 * portWORD_SIZE( sp ) /* Load additional registers into accessible temporary registers. */ +lw t1, 2 * portWORD_SIZE( sp ) +lw t2, 3 * portWORD_SIZE( sp ) +lw t3, 4 * portWORD_SIZE( sp ) +lw t4, 5 * portWORD_SIZE( sp ) +lw t5, 6 * portWORD_SIZE( sp ) +csrw lpstart0, t0 +csrw lpend0, t1 +csrw lpcount0, t2 +csrw lpstart1, t3 +csrw lpend1, t4 +csrw lpcount1, t5 +addi sp, sp, ( portasmADDITIONAL_CONTEXT_SIZE * portWORD_SIZE ) /* Remove space added for additional registers. */ + .endm #endif /* __FREERTOS_RISC_V_EXTENSIONS_H__ */ diff --git a/Source/portable/GCC/RISC-V/chip_specific_extensions/RISCV_MTIME_CLINT_no_extensions/freertos_risc_v_chip_specific_extensions.h b/Source/portable/GCC/RISC-V/chip_specific_extensions/RISCV_MTIME_CLINT_no_extensions/freertos_risc_v_chip_specific_extensions.h index 322e263f4..74b3bd460 100644 --- a/Source/portable/GCC/RISC-V/chip_specific_extensions/RISCV_MTIME_CLINT_no_extensions/freertos_risc_v_chip_specific_extensions.h +++ b/Source/portable/GCC/RISC-V/chip_specific_extensions/RISCV_MTIME_CLINT_no_extensions/freertos_risc_v_chip_specific_extensions.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -54,16 +54,16 @@ #ifndef __FREERTOS_RISC_V_EXTENSIONS_H__ #define __FREERTOS_RISC_V_EXTENSIONS_H__ -#define portasmHAS_SIFIVE_CLINT 1 -#define portasmHAS_MTIME 1 -#define portasmADDITIONAL_CONTEXT_SIZE 0 +#define portasmHAS_SIFIVE_CLINT 1 +#define portasmHAS_MTIME 1 +#define portasmADDITIONAL_CONTEXT_SIZE 0 .macro portasmSAVE_ADDITIONAL_REGISTERS - /* No additional registers to save, so this macro does nothing. */ - .endm +/* No additional registers to save, so this macro does nothing. */ + .endm -.macro portasmRESTORE_ADDITIONAL_REGISTERS - /* No additional registers to restore, so this macro does nothing. */ - .endm + .macro portasmRESTORE_ADDITIONAL_REGISTERS +/* No additional registers to restore, so this macro does nothing. */ + .endm #endif /* __FREERTOS_RISC_V_EXTENSIONS_H__ */ diff --git a/Source/portable/GCC/RISC-V/chip_specific_extensions/RISCV_no_extensions/freertos_risc_v_chip_specific_extensions.h b/Source/portable/GCC/RISC-V/chip_specific_extensions/RISCV_no_extensions/freertos_risc_v_chip_specific_extensions.h index c47b5923d..8a597343c 100644 --- a/Source/portable/GCC/RISC-V/chip_specific_extensions/RISCV_no_extensions/freertos_risc_v_chip_specific_extensions.h +++ b/Source/portable/GCC/RISC-V/chip_specific_extensions/RISCV_no_extensions/freertos_risc_v_chip_specific_extensions.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -54,16 +54,16 @@ #ifndef __FREERTOS_RISC_V_EXTENSIONS_H__ #define __FREERTOS_RISC_V_EXTENSIONS_H__ -#define portasmHAS_SIFIVE_CLINT 0 -#define portasmHAS_MTIME 0 -#define portasmADDITIONAL_CONTEXT_SIZE 0 +#define portasmHAS_SIFIVE_CLINT 0 +#define portasmHAS_MTIME 0 +#define portasmADDITIONAL_CONTEXT_SIZE 0 .macro portasmSAVE_ADDITIONAL_REGISTERS - /* No additional registers to save, so this macro does nothing. */ - .endm +/* No additional registers to save, so this macro does nothing. */ + .endm -.macro portasmRESTORE_ADDITIONAL_REGISTERS - /* No additional registers to restore, so this macro does nothing. */ - .endm + .macro portasmRESTORE_ADDITIONAL_REGISTERS +/* No additional registers to restore, so this macro does nothing. */ + .endm #endif /* __FREERTOS_RISC_V_EXTENSIONS_H__ */ diff --git a/Source/portable/GCC/RISC-V/chip_specific_extensions/RV32I_CLINT_no_extensions/freertos_risc_v_chip_specific_extensions.h b/Source/portable/GCC/RISC-V/chip_specific_extensions/RV32I_CLINT_no_extensions/freertos_risc_v_chip_specific_extensions.h index 9d905487c..47f6fd46a 100644 --- a/Source/portable/GCC/RISC-V/chip_specific_extensions/RV32I_CLINT_no_extensions/freertos_risc_v_chip_specific_extensions.h +++ b/Source/portable/GCC/RISC-V/chip_specific_extensions/RV32I_CLINT_no_extensions/freertos_risc_v_chip_specific_extensions.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -54,16 +54,16 @@ #ifndef __FREERTOS_RISC_V_EXTENSIONS_H__ #define __FREERTOS_RISC_V_EXTENSIONS_H__ -#define portasmHAS_SIFIVE_CLINT 1 -#define portasmHAS_MTIME 1 -#define portasmADDITIONAL_CONTEXT_SIZE 0 /* Must be even number on 32-bit cores. */ +#define portasmHAS_SIFIVE_CLINT 1 +#define portasmHAS_MTIME 1 +#define portasmADDITIONAL_CONTEXT_SIZE 0 /* Must be even number on 32-bit cores. */ .macro portasmSAVE_ADDITIONAL_REGISTERS - /* No additional registers to save, so this macro does nothing. */ - .endm +/* No additional registers to save, so this macro does nothing. */ + .endm -.macro portasmRESTORE_ADDITIONAL_REGISTERS - /* No additional registers to restore, so this macro does nothing. */ - .endm + .macro portasmRESTORE_ADDITIONAL_REGISTERS +/* No additional registers to restore, so this macro does nothing. */ + .endm #endif /* __FREERTOS_RISC_V_EXTENSIONS_H__ */ diff --git a/Source/portable/GCC/RISC-V/port.c b/Source/portable/GCC/RISC-V/port.c index caec66972..250d53064 100644 --- a/Source/portable/GCC/RISC-V/port.c +++ b/Source/portable/GCC/RISC-V/port.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -27,8 +27,8 @@ */ /*----------------------------------------------------------- - * Implementation of functions defined in portable.h for the RISC-V port. - *----------------------------------------------------------*/ +* Implementation of functions defined in portable.h for the RISC-V port. +*----------------------------------------------------------*/ /* Scheduler includes. */ #include "FreeRTOS.h" @@ -39,15 +39,15 @@ #include "string.h" #ifdef configCLINT_BASE_ADDRESS - #warning The configCLINT_BASE_ADDRESS constant has been deprecated. configMTIME_BASE_ADDRESS and configMTIMECMP_BASE_ADDRESS are currently being derived from the (possibly 0) configCLINT_BASE_ADDRESS setting. Please update to define configMTIME_BASE_ADDRESS and configMTIMECMP_BASE_ADDRESS dirctly in place of configCLINT_BASE_ADDRESS. See https://www.FreeRTOS.org/Using-FreeRTOS-on-RISC-V.html + #warning "The configCLINT_BASE_ADDRESS constant has been deprecated. configMTIME_BASE_ADDRESS and configMTIMECMP_BASE_ADDRESS are currently being derived from the (possibly 0) configCLINT_BASE_ADDRESS setting. Please update to define configMTIME_BASE_ADDRESS and configMTIMECMP_BASE_ADDRESS directly in place of configCLINT_BASE_ADDRESS. See www.FreeRTOS.org/Using-FreeRTOS-on-RISC-V.html" #endif #ifndef configMTIME_BASE_ADDRESS - #warning configMTIME_BASE_ADDRESS must be defined in FreeRTOSConfig.h. If the target chip includes a memory-mapped mtime register then set configMTIME_BASE_ADDRESS to the mapped address. Otherwise set configMTIME_BASE_ADDRESS to 0. See https://www.FreeRTOS.org/Using-FreeRTOS-on-RISC-V.html + #warning "configMTIME_BASE_ADDRESS must be defined in FreeRTOSConfig.h. If the target chip includes a memory-mapped mtime register then set configMTIME_BASE_ADDRESS to the mapped address. Otherwise set configMTIME_BASE_ADDRESS to 0. See www.FreeRTOS.org/Using-FreeRTOS-on-RISC-V.html" #endif #ifndef configMTIMECMP_BASE_ADDRESS - #warning configMTIMECMP_BASE_ADDRESS must be defined in FreeRTOSConfig.h. If the target chip includes a memory-mapped mtimecmp register then set configMTIMECMP_BASE_ADDRESS to the mapped address. Otherwise set configMTIMECMP_BASE_ADDRESS to 0. See https://www.FreeRTOS.org/Using-FreeRTOS-on-RISC-V.html + #warning "configMTIMECMP_BASE_ADDRESS must be defined in FreeRTOSConfig.h. If the target chip includes a memory-mapped mtimecmp register then set configMTIMECMP_BASE_ADDRESS to the mapped address. Otherwise set configMTIMECMP_BASE_ADDRESS to 0. See www.FreeRTOS.org/Using-FreeRTOS-on-RISC-V.html" #endif /* Let the user override the pre-loading of the initial RA. */ @@ -65,12 +65,12 @@ * stack that was used by main before the scheduler was started for use as the * interrupt stack after the scheduler has started. */ #ifdef configISR_STACK_SIZE_WORDS - static __attribute__ ((aligned(16))) StackType_t xISRStack[ configISR_STACK_SIZE_WORDS ] = { 0 }; - const StackType_t xISRStackTop = ( StackType_t ) &( xISRStack[ configISR_STACK_SIZE_WORDS & ~portBYTE_ALIGNMENT_MASK ] ); +static __attribute__( ( aligned( 16 ) ) ) StackType_t xISRStack[ configISR_STACK_SIZE_WORDS ] = { 0 }; +const StackType_t xISRStackTop = ( StackType_t ) &( xISRStack[ configISR_STACK_SIZE_WORDS & ~portBYTE_ALIGNMENT_MASK ] ); - /* Don't use 0xa5 as the stack fill bytes as that is used by the kernerl for - the task stacks, and so will legitimately appear in many positions within - the ISR stack. */ +/* Don't use 0xa5 as the stack fill bytes as that is used by the kernel for + * the task stacks, and so will legitimately appear in many positions within + * the ISR stack. */ #define portISR_STACK_FILL_BYTE 0xee #else extern const uint32_t __freertos_irq_stack_top[]; @@ -82,13 +82,13 @@ * file is weak to allow application writers to change the timer used to * generate the tick interrupt. */ -void vPortSetupTimerInterrupt( void ) __attribute__(( weak )); +void vPortSetupTimerInterrupt( void ) __attribute__( ( weak ) ); /*-----------------------------------------------------------*/ /* Used to program the machine timer compare register. */ uint64_t ullNextTime = 0ULL; -const uint64_t *pullNextTime = &ullNextTime; +const uint64_t * pullNextTime = &ullNextTime; const size_t uxTimerIncrementsForOneTick = ( size_t ) ( ( configCPU_CLOCK_HZ ) / ( configTICK_RATE_HZ ) ); /* Assumes increment won't go over 32-bits. */ uint32_t const ullMachineTimerCompareRegisterBase = configMTIMECMP_BASE_ADDRESS; volatile uint64_t * pullMachineTimerCompareRegister = NULL; @@ -96,7 +96,7 @@ volatile uint64_t * pullMachineTimerCompareRegister = NULL; /* Holds the critical nesting value - deliberately non-zero at start up to * ensure interrupts are not accidentally enabled before the scheduler starts. */ size_t xCriticalNesting = ( size_t ) 0xaaaaaaaa; -size_t *pxCriticalNesting = &xCriticalNesting; +size_t * pxCriticalNesting = &xCriticalNesting; /* Used to catch tasks that attempt to return from their implementing function. */ size_t xTaskReturnAddress = ( size_t ) portTASK_RETURN_ADDRESS; @@ -106,34 +106,37 @@ size_t xTaskReturnAddress = ( size_t ) portTASK_RETURN_ADDRESS; * the stack overflow hook function (because the stack overflow hook is specific * to a task stack, not the ISR stack). */ #if defined( configISR_STACK_SIZE_WORDS ) && ( configCHECK_FOR_STACK_OVERFLOW > 2 ) - #warning This path not tested, or even compiled yet. + #warning "This path not tested, or even compiled yet." - static const uint8_t ucExpectedStackBytes[] = { - portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, \ - portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, \ - portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, \ - portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, \ - portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE }; \ - - #define portCHECK_ISR_STACK() configASSERT( ( memcmp( ( void * ) xISRStack, ( void * ) ucExpectedStackBytes, sizeof( ucExpectedStackBytes ) ) == 0 ) ) -#else + static const uint8_t ucExpectedStackBytes[] = + { + portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, \ + portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, \ + portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, \ + portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, \ + portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE + }; \ + + #define portCHECK_ISR_STACK() configASSERT( ( memcmp( ( void * ) xISRStack, ( void * ) ucExpectedStackBytes, sizeof( ucExpectedStackBytes ) ) == 0 ) ) +#else /* if defined( configISR_STACK_SIZE_WORDS ) && ( configCHECK_FOR_STACK_OVERFLOW > 2 ) */ /* Define the function away. */ #define portCHECK_ISR_STACK() #endif /* configCHECK_FOR_STACK_OVERFLOW > 2 */ /*-----------------------------------------------------------*/ -#if( configMTIME_BASE_ADDRESS != 0 ) && ( configMTIMECMP_BASE_ADDRESS != 0 ) +#if ( configMTIME_BASE_ADDRESS != 0 ) && ( configMTIMECMP_BASE_ADDRESS != 0 ) void vPortSetupTimerInterrupt( void ) { - uint32_t ulCurrentTimeHigh, ulCurrentTimeLow; - volatile uint32_t * const pulTimeHigh = ( volatile uint32_t * const ) ( ( configMTIME_BASE_ADDRESS ) + 4UL ); /* 8-byte type so high 32-bit word is 4 bytes up. */ - volatile uint32_t * const pulTimeLow = ( volatile uint32_t * const ) ( configMTIME_BASE_ADDRESS ); - volatile uint32_t ulHartId; + uint32_t ulCurrentTimeHigh, ulCurrentTimeLow; + volatile uint32_t * const pulTimeHigh = ( volatile uint32_t * const ) ( ( configMTIME_BASE_ADDRESS ) + 4UL ); /* 8-byte type so high 32-bit word is 4 bytes up. */ + volatile uint32_t * const pulTimeLow = ( volatile uint32_t * const ) ( configMTIME_BASE_ADDRESS ); + volatile uint32_t ulHartId; - __asm volatile( "csrr %0, mhartid" : "=r"( ulHartId ) ); - pullMachineTimerCompareRegister = ( volatile uint64_t * ) ( ullMachineTimerCompareRegisterBase + ( ulHartId * sizeof( uint64_t ) ) ); + __asm volatile ( "csrr %0, mhartid" : "=r" ( ulHartId ) ); + + pullMachineTimerCompareRegister = ( volatile uint64_t * ) ( ullMachineTimerCompareRegisterBase + ( ulHartId * sizeof( uint64_t ) ) ); do { @@ -156,9 +159,9 @@ size_t xTaskReturnAddress = ( size_t ) portTASK_RETURN_ADDRESS; BaseType_t xPortStartScheduler( void ) { -extern void xPortStartFirstTask( void ); + extern void xPortStartFirstTask( void ); - #if( configASSERT_DEFINED == 1 ) + #if ( configASSERT_DEFINED == 1 ) { /* Check alignment of the interrupt stack - which is the same as the * stack that was being used by main() prior to the scheduler being @@ -178,12 +181,12 @@ extern void xPortStartFirstTask( void ); * configure whichever clock is to be used to generate the tick interrupt. */ vPortSetupTimerInterrupt(); - #if( ( configMTIME_BASE_ADDRESS != 0 ) && ( configMTIMECMP_BASE_ADDRESS != 0 ) ) + #if ( ( configMTIME_BASE_ADDRESS != 0 ) && ( configMTIMECMP_BASE_ADDRESS != 0 ) ) { /* Enable mtime and external interrupts. 1<<7 for timer interrupt, * 1<<11 for external interrupt. _RB_ What happens here when mtime is * not present as with pulpino? */ - __asm volatile( "csrs mie, %0" :: "r"(0x880) ); + __asm volatile ( "csrs mie, %0" ::"r" ( 0x880 ) ); } #endif /* ( configMTIME_BASE_ADDRESS != 0 ) && ( configMTIMECMP_BASE_ADDRESS != 0 ) */ @@ -198,6 +201,8 @@ extern void xPortStartFirstTask( void ); void vPortEndScheduler( void ) { /* Not implemented. */ - for( ;; ); + for( ; ; ) + { + } } /*-----------------------------------------------------------*/ diff --git a/Source/portable/GCC/RISC-V/portASM.S b/Source/portable/GCC/RISC-V/portASM.S index 150e91633..7d8bc7689 100644 --- a/Source/portable/GCC/RISC-V/portASM.S +++ b/Source/portable/GCC/RISC-V/portASM.S @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/Source/portable/GCC/RISC-V/portContext.h b/Source/portable/GCC/RISC-V/portContext.h index 8e855796a..5f075dfd5 100644 --- a/Source/portable/GCC/RISC-V/portContext.h +++ b/Source/portable/GCC/RISC-V/portContext.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -30,13 +30,13 @@ #define PORTCONTEXT_H #if __riscv_xlen == 64 - #define portWORD_SIZE 8 - #define store_x sd - #define load_x ld + #define portWORD_SIZE 8 + #define store_x sd + #define load_x ld #elif __riscv_xlen == 32 - #define store_x sw - #define load_x lw - #define portWORD_SIZE 4 + #define store_x sw + #define load_x lw + #define portWORD_SIZE 4 #else #error Assembler did not define __riscv_xlen #endif @@ -49,37 +49,37 @@ * specific version of freertos_risc_v_chip_specific_extensions.h. See the * notes at the top of portASM.S file. */ #ifdef __riscv_32e - #define portCONTEXT_SIZE ( 15 * portWORD_SIZE ) - #define portCRITICAL_NESTING_OFFSET 13 - #define portMSTATUS_OFFSET 14 + #define portCONTEXT_SIZE ( 15 * portWORD_SIZE ) + #define portCRITICAL_NESTING_OFFSET 13 + #define portMSTATUS_OFFSET 14 #else - #define portCONTEXT_SIZE ( 31 * portWORD_SIZE ) - #define portCRITICAL_NESTING_OFFSET 29 - #define portMSTATUS_OFFSET 30 + #define portCONTEXT_SIZE ( 31 * portWORD_SIZE ) + #define portCRITICAL_NESTING_OFFSET 29 + #define portMSTATUS_OFFSET 30 #endif /*-----------------------------------------------------------*/ .extern pxCurrentTCB -.extern xISRStackTop -.extern xCriticalNesting -.extern pxCriticalNesting + .extern xISRStackTop + .extern xCriticalNesting + .extern pxCriticalNesting /*-----------------------------------------------------------*/ -.macro portcontextSAVE_CONTEXT_INTERNAL - addi sp, sp, -portCONTEXT_SIZE - store_x x1, 1 * portWORD_SIZE( sp ) - store_x x5, 2 * portWORD_SIZE( sp ) - store_x x6, 3 * portWORD_SIZE( sp ) - store_x x7, 4 * portWORD_SIZE( sp ) - store_x x8, 5 * portWORD_SIZE( sp ) - store_x x9, 6 * portWORD_SIZE( sp ) - store_x x10, 7 * portWORD_SIZE( sp ) - store_x x11, 8 * portWORD_SIZE( sp ) - store_x x12, 9 * portWORD_SIZE( sp ) - store_x x13, 10 * portWORD_SIZE( sp ) - store_x x14, 11 * portWORD_SIZE( sp ) - store_x x15, 12 * portWORD_SIZE( sp ) + .macro portcontextSAVE_CONTEXT_INTERNAL +addi sp, sp, -portCONTEXT_SIZE +store_x x1, 1 * portWORD_SIZE( sp ) +store_x x5, 2 * portWORD_SIZE( sp ) +store_x x6, 3 * portWORD_SIZE( sp ) +store_x x7, 4 * portWORD_SIZE( sp ) +store_x x8, 5 * portWORD_SIZE( sp ) +store_x x9, 6 * portWORD_SIZE( sp ) +store_x x10, 7 * portWORD_SIZE( sp ) +store_x x11, 8 * portWORD_SIZE( sp ) +store_x x12, 9 * portWORD_SIZE( sp ) +store_x x13, 10 * portWORD_SIZE( sp ) +store_x x14, 11 * portWORD_SIZE( sp ) +store_x x15, 12 * portWORD_SIZE( sp ) #ifndef __riscv_32e store_x x16, 13 * portWORD_SIZE( sp ) store_x x17, 14 * portWORD_SIZE( sp ) @@ -97,96 +97,96 @@ store_x x29, 26 * portWORD_SIZE( sp ) store_x x30, 27 * portWORD_SIZE( sp ) store_x x31, 28 * portWORD_SIZE( sp ) -#endif +#endif /* ifndef __riscv_32e */ - load_x t0, xCriticalNesting /* Load the value of xCriticalNesting into t0. */ - store_x t0, portCRITICAL_NESTING_OFFSET * portWORD_SIZE( sp ) /* Store the critical nesting value to the stack. */ +load_x t0, xCriticalNesting /* Load the value of xCriticalNesting into t0. */ +store_x t0, portCRITICAL_NESTING_OFFSET * portWORD_SIZE( sp ) /* Store the critical nesting value to the stack. */ - csrr t0, mstatus /* Required for MPIE bit. */ - store_x t0, portMSTATUS_OFFSET * portWORD_SIZE( sp ) +csrr t0, mstatus /* Required for MPIE bit. */ +store_x t0, portMSTATUS_OFFSET * portWORD_SIZE( sp ) - portasmSAVE_ADDITIONAL_REGISTERS /* Defined in freertos_risc_v_chip_specific_extensions.h to save any registers unique to the RISC-V implementation. */ +portasmSAVE_ADDITIONAL_REGISTERS /* Defined in freertos_risc_v_chip_specific_extensions.h to save any registers unique to the RISC-V implementation. */ - load_x t0, pxCurrentTCB /* Load pxCurrentTCB. */ - store_x sp, 0( t0 ) /* Write sp to first TCB member. */ +load_x t0, pxCurrentTCB /* Load pxCurrentTCB. */ +store_x sp, 0 ( t0 ) /* Write sp to first TCB member. */ - .endm + .endm /*-----------------------------------------------------------*/ -.macro portcontextSAVE_EXCEPTION_CONTEXT - portcontextSAVE_CONTEXT_INTERNAL - csrr a0, mcause - csrr a1, mepc - addi a1, a1, 4 /* Synchronous so update exception return address to the instruction after the instruction that generated the exception. */ - store_x a1, 0( sp ) /* Save updated exception return address. */ - load_x sp, xISRStackTop /* Switch to ISR stack. */ - .endm + .macro portcontextSAVE_EXCEPTION_CONTEXT +portcontextSAVE_CONTEXT_INTERNAL +csrr a0, mcause +csrr a1, mepc +addi a1, a1, 4 /* Synchronous so update exception return address to the instruction after the instruction that generated the exception. */ +store_x a1, 0 ( sp ) /* Save updated exception return address. */ +load_x sp, xISRStackTop /* Switch to ISR stack. */ + .endm /*-----------------------------------------------------------*/ -.macro portcontextSAVE_INTERRUPT_CONTEXT - portcontextSAVE_CONTEXT_INTERNAL - csrr a0, mcause - csrr a1, mepc - store_x a1, 0( sp ) /* Asynchronous interrupt so save unmodified exception return address. */ - load_x sp, xISRStackTop /* Switch to ISR stack. */ - .endm + .macro portcontextSAVE_INTERRUPT_CONTEXT +portcontextSAVE_CONTEXT_INTERNAL +csrr a0, mcause +csrr a1, mepc +store_x a1, 0 ( sp ) /* Asynchronous interrupt so save unmodified exception return address. */ +load_x sp, xISRStackTop /* Switch to ISR stack. */ + .endm /*-----------------------------------------------------------*/ -.macro portcontextRESTORE_CONTEXT - load_x t1, pxCurrentTCB /* Load pxCurrentTCB. */ - load_x sp, 0( t1 ) /* Read sp from first TCB member. */ - - /* Load mepc with the address of the instruction in the task to run next. */ - load_x t0, 0( sp ) - csrw mepc, t0 - - /* Defined in freertos_risc_v_chip_specific_extensions.h to restore any registers unique to the RISC-V implementation. */ - portasmRESTORE_ADDITIONAL_REGISTERS - - /* Load mstatus with the interrupt enable bits used by the task. */ - load_x t0, portMSTATUS_OFFSET * portWORD_SIZE( sp ) - csrw mstatus, t0 /* Required for MPIE bit. */ - - load_x t0, portCRITICAL_NESTING_OFFSET * portWORD_SIZE( sp ) /* Obtain xCriticalNesting value for this task from task's stack. */ - load_x t1, pxCriticalNesting /* Load the address of xCriticalNesting into t1. */ - store_x t0, 0( t1 ) /* Restore the critical nesting value for this task. */ - - load_x x1, 1 * portWORD_SIZE( sp ) - load_x x5, 2 * portWORD_SIZE( sp ) - load_x x6, 3 * portWORD_SIZE( sp ) - load_x x7, 4 * portWORD_SIZE( sp ) - load_x x8, 5 * portWORD_SIZE( sp ) - load_x x9, 6 * portWORD_SIZE( sp ) - load_x x10, 7 * portWORD_SIZE( sp ) - load_x x11, 8 * portWORD_SIZE( sp ) - load_x x12, 9 * portWORD_SIZE( sp ) - load_x x13, 10 * portWORD_SIZE( sp ) - load_x x14, 11 * portWORD_SIZE( sp ) - load_x x15, 12 * portWORD_SIZE( sp ) + .macro portcontextRESTORE_CONTEXT +load_x t1, pxCurrentTCB /* Load pxCurrentTCB. */ +load_x sp, 0 ( t1 ) /* Read sp from first TCB member. */ + +/* Load mepc with the address of the instruction in the task to run next. */ +load_x t0, 0 ( sp ) +csrw mepc, t0 + +/* Defined in freertos_risc_v_chip_specific_extensions.h to restore any registers unique to the RISC-V implementation. */ +portasmRESTORE_ADDITIONAL_REGISTERS + +/* Load mstatus with the interrupt enable bits used by the task. */ +load_x t0, portMSTATUS_OFFSET * portWORD_SIZE( sp ) +csrw mstatus, t0 /* Required for MPIE bit. */ + +load_x t0, portCRITICAL_NESTING_OFFSET * portWORD_SIZE( sp ) /* Obtain xCriticalNesting value for this task from task's stack. */ +load_x t1, pxCriticalNesting /* Load the address of xCriticalNesting into t1. */ +store_x t0, 0 ( t1 ) /* Restore the critical nesting value for this task. */ + +load_x x1, 1 * portWORD_SIZE( sp ) +load_x x5, 2 * portWORD_SIZE( sp ) +load_x x6, 3 * portWORD_SIZE( sp ) +load_x x7, 4 * portWORD_SIZE( sp ) +load_x x8, 5 * portWORD_SIZE( sp ) +load_x x9, 6 * portWORD_SIZE( sp ) +load_x x10, 7 * portWORD_SIZE( sp ) +load_x x11, 8 * portWORD_SIZE( sp ) +load_x x12, 9 * portWORD_SIZE( sp ) +load_x x13, 10 * portWORD_SIZE( sp ) +load_x x14, 11 * portWORD_SIZE( sp ) +load_x x15, 12 * portWORD_SIZE( sp ) #ifndef __riscv_32e - load_x x16, 13 * portWORD_SIZE( sp ) - load_x x17, 14 * portWORD_SIZE( sp ) - load_x x18, 15 * portWORD_SIZE( sp ) - load_x x19, 16 * portWORD_SIZE( sp ) - load_x x20, 17 * portWORD_SIZE( sp ) - load_x x21, 18 * portWORD_SIZE( sp ) - load_x x22, 19 * portWORD_SIZE( sp ) - load_x x23, 20 * portWORD_SIZE( sp ) - load_x x24, 21 * portWORD_SIZE( sp ) - load_x x25, 22 * portWORD_SIZE( sp ) - load_x x26, 23 * portWORD_SIZE( sp ) - load_x x27, 24 * portWORD_SIZE( sp ) - load_x x28, 25 * portWORD_SIZE( sp ) - load_x x29, 26 * portWORD_SIZE( sp ) - load_x x30, 27 * portWORD_SIZE( sp ) - load_x x31, 28 * portWORD_SIZE( sp ) -#endif - addi sp, sp, portCONTEXT_SIZE - - mret - .endm + load_x x16, 13 * portWORD_SIZE( sp ) + load_x x17, 14 * portWORD_SIZE( sp ) + load_x x18, 15 * portWORD_SIZE( sp ) + load_x x19, 16 * portWORD_SIZE( sp ) + load_x x20, 17 * portWORD_SIZE( sp ) + load_x x21, 18 * portWORD_SIZE( sp ) + load_x x22, 19 * portWORD_SIZE( sp ) + load_x x23, 20 * portWORD_SIZE( sp ) + load_x x24, 21 * portWORD_SIZE( sp ) + load_x x25, 22 * portWORD_SIZE( sp ) + load_x x26, 23 * portWORD_SIZE( sp ) + load_x x27, 24 * portWORD_SIZE( sp ) + load_x x28, 25 * portWORD_SIZE( sp ) + load_x x29, 26 * portWORD_SIZE( sp ) + load_x x30, 27 * portWORD_SIZE( sp ) + load_x x31, 28 * portWORD_SIZE( sp ) +#endif /* ifndef __riscv_32e */ +addi sp, sp, portCONTEXT_SIZE + +mret + .endm /*-----------------------------------------------------------*/ #endif /* PORTCONTEXT_H */ diff --git a/Source/portable/GCC/RISC-V/portmacro.h b/Source/portable/GCC/RISC-V/portmacro.h index 163b72334..2942fe82d 100644 --- a/Source/portable/GCC/RISC-V/portmacro.h +++ b/Source/portable/GCC/RISC-V/portmacro.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -48,100 +48,112 @@ /* Type definitions. */ #if __riscv_xlen == 64 - #define portSTACK_TYPE uint64_t - #define portBASE_TYPE int64_t - #define portUBASE_TYPE uint64_t - #define portMAX_DELAY ( TickType_t ) 0xffffffffffffffffUL - #define portPOINTER_SIZE_TYPE uint64_t + #define portSTACK_TYPE uint64_t + #define portBASE_TYPE int64_t + #define portUBASE_TYPE uint64_t + #define portMAX_DELAY ( TickType_t ) 0xffffffffffffffffUL + #define portPOINTER_SIZE_TYPE uint64_t #elif __riscv_xlen == 32 - #define portSTACK_TYPE uint32_t - #define portBASE_TYPE int32_t - #define portUBASE_TYPE uint32_t - #define portMAX_DELAY ( TickType_t ) 0xffffffffUL -#else - #error Assembler did not define __riscv_xlen -#endif - -typedef portSTACK_TYPE StackType_t; -typedef portBASE_TYPE BaseType_t; -typedef portUBASE_TYPE UBaseType_t; -typedef portUBASE_TYPE TickType_t; + #define portSTACK_TYPE uint32_t + #define portBASE_TYPE int32_t + #define portUBASE_TYPE uint32_t + #define portMAX_DELAY ( TickType_t ) 0xffffffffUL +#else /* if __riscv_xlen == 64 */ + #error "Assembler did not define __riscv_xlen" +#endif /* if __riscv_xlen == 64 */ + +typedef portSTACK_TYPE StackType_t; +typedef portBASE_TYPE BaseType_t; +typedef portUBASE_TYPE UBaseType_t; +typedef portUBASE_TYPE TickType_t; /* Legacy type definitions. */ -#define portCHAR char -#define portFLOAT float -#define portDOUBLE double -#define portLONG long -#define portSHORT short +#define portCHAR char +#define portFLOAT float +#define portDOUBLE double +#define portLONG long +#define portSHORT short /* 32-bit tick type on a 32-bit architecture, so reads of the tick count do * not need to be guarded with a critical section. */ -#define portTICK_TYPE_IS_ATOMIC 1 +#define portTICK_TYPE_IS_ATOMIC 1 /*-----------------------------------------------------------*/ /* Architecture specifics. */ -#define portSTACK_GROWTH ( -1 ) -#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) +#define portSTACK_GROWTH ( -1 ) +#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) #ifdef __riscv_32e - #define portBYTE_ALIGNMENT 8 /* RV32E uses RISC-V EABI with reduced stack alignment requirements */ + #define portBYTE_ALIGNMENT 8 /* RV32E uses RISC-V EABI with reduced stack alignment requirements */ #else - #define portBYTE_ALIGNMENT 16 + #define portBYTE_ALIGNMENT 16 #endif /*-----------------------------------------------------------*/ /* Scheduler utilities. */ extern void vTaskSwitchContext( void ); -#define portYIELD() __asm volatile( "ecall" ); -#define portEND_SWITCHING_ISR( xSwitchRequired ) do { if( xSwitchRequired ) vTaskSwitchContext(); } while( 0 ) -#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x ) +#define portYIELD() __asm volatile ( "ecall" ); +#define portEND_SWITCHING_ISR( xSwitchRequired ) \ + do \ + { \ + if( xSwitchRequired != pdFALSE ) \ + { \ + traceISR_EXIT_TO_SCHEDULER(); \ + vTaskSwitchContext(); \ + } \ + else \ + { \ + traceISR_EXIT(); \ + } \ + } while( 0 ) +#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x ) /*-----------------------------------------------------------*/ /* Critical section management. */ -#define portCRITICAL_NESTING_IN_TCB 0 +#define portCRITICAL_NESTING_IN_TCB 0 -#define portSET_INTERRUPT_MASK_FROM_ISR() 0 -#define portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedStatusValue ) ( void ) uxSavedStatusValue +#define portSET_INTERRUPT_MASK_FROM_ISR() 0 +#define portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedStatusValue ) ( void ) uxSavedStatusValue -#define portDISABLE_INTERRUPTS() __asm volatile( "csrc mstatus, 8" ) -#define portENABLE_INTERRUPTS() __asm volatile( "csrs mstatus, 8" ) +#define portDISABLE_INTERRUPTS() __asm volatile ( "csrc mstatus, 8" ) +#define portENABLE_INTERRUPTS() __asm volatile ( "csrs mstatus, 8" ) extern size_t xCriticalNesting; -#define portENTER_CRITICAL() \ -{ \ - portDISABLE_INTERRUPTS(); \ - xCriticalNesting++; \ -} - -#define portEXIT_CRITICAL() \ -{ \ - xCriticalNesting--; \ - if( xCriticalNesting == 0 ) \ - { \ - portENABLE_INTERRUPTS(); \ - } \ -} +#define portENTER_CRITICAL() \ + { \ + portDISABLE_INTERRUPTS(); \ + xCriticalNesting++; \ + } + +#define portEXIT_CRITICAL() \ + { \ + xCriticalNesting--; \ + if( xCriticalNesting == 0 ) \ + { \ + portENABLE_INTERRUPTS(); \ + } \ + } /*-----------------------------------------------------------*/ /* Architecture specific optimisations. */ #ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION - #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1 + #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1 #endif -#if( configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 ) +#if ( configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 ) - /* Check the configuration. */ - #if( configMAX_PRIORITIES > 32 ) - #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice. +/* Check the configuration. */ + #if ( configMAX_PRIORITIES > 32 ) + #error "configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice." #endif - /* Store/clear the ready priorities in a bit map. */ - #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) ) - #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) ) +/* Store/clear the ready priorities in a bit map. */ + #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) ) + #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) ) - /*-----------------------------------------------------------*/ +/*-----------------------------------------------------------*/ - #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - __builtin_clz( uxReadyPriorities ) ) + #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - __builtin_clz( uxReadyPriorities ) ) #endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */ @@ -151,19 +163,19 @@ extern size_t xCriticalNesting; /* Task function macros as described on the FreeRTOS.org WEB site. These are * not necessary for to use this port. They are defined so the common demo * files (which build with all the ports) will build. */ -#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters ) -#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters ) +#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters ) +#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters ) /*-----------------------------------------------------------*/ -#define portNOP() __asm volatile( " nop " ) -#define portINLINE __inline +#define portNOP() __asm volatile ( " nop " ) +#define portINLINE __inline #ifndef portFORCE_INLINE - #define portFORCE_INLINE inline __attribute__(( always_inline)) + #define portFORCE_INLINE inline __attribute__( ( always_inline ) ) #endif -#define portMEMORY_BARRIER() __asm volatile( "" ::: "memory" ) +#define portMEMORY_BARRIER() __asm volatile ( "" ::: "memory" ) /*-----------------------------------------------------------*/ /* configCLINT_BASE_ADDRESS is a legacy definition that was replaced by the @@ -171,20 +183,22 @@ extern size_t xCriticalNesting; * backward compatibility derive the newer definitions from the old if the old * definition is found. */ #if defined( configCLINT_BASE_ADDRESS ) && !defined( configMTIME_BASE_ADDRESS ) && ( configCLINT_BASE_ADDRESS == 0 ) - /* Legacy case where configCLINT_BASE_ADDRESS was defined as 0 to indicate - * there was no CLINT. Equivalent now is to set the MTIME and MTIMECMP - * addresses to 0. */ - #define configMTIME_BASE_ADDRESS ( 0 ) - #define configMTIMECMP_BASE_ADDRESS ( 0 ) + +/* Legacy case where configCLINT_BASE_ADDRESS was defined as 0 to indicate + * there was no CLINT. Equivalent now is to set the MTIME and MTIMECMP + * addresses to 0. */ + #define configMTIME_BASE_ADDRESS ( 0 ) + #define configMTIMECMP_BASE_ADDRESS ( 0 ) #elif defined( configCLINT_BASE_ADDRESS ) && !defined( configMTIME_BASE_ADDRESS ) - /* Legacy case where configCLINT_BASE_ADDRESS was set to the base address of - * the CLINT. Equivalent now is to derive the MTIME and MTIMECMP addresses - * from the CLINT address. */ - #define configMTIME_BASE_ADDRESS ( ( configCLINT_BASE_ADDRESS ) + 0xBFF8UL ) - #define configMTIMECMP_BASE_ADDRESS ( ( configCLINT_BASE_ADDRESS ) + 0x4000UL ) + +/* Legacy case where configCLINT_BASE_ADDRESS was set to the base address of + * the CLINT. Equivalent now is to derive the MTIME and MTIMECMP addresses + * from the CLINT address. */ + #define configMTIME_BASE_ADDRESS ( ( configCLINT_BASE_ADDRESS ) + 0xBFF8UL ) + #define configMTIMECMP_BASE_ADDRESS ( ( configCLINT_BASE_ADDRESS ) + 0x4000UL ) #elif !defined( configMTIME_BASE_ADDRESS ) || !defined( configMTIMECMP_BASE_ADDRESS ) - #error configMTIME_BASE_ADDRESS and configMTIMECMP_BASE_ADDRESS must be defined in FreeRTOSConfig.h. Set them to zero if there is no MTIME (machine time) clock. See https://www.FreeRTOS.org/Using-FreeRTOS-on-RISC-V.html -#endif + #error "configMTIME_BASE_ADDRESS and configMTIMECMP_BASE_ADDRESS must be defined in FreeRTOSConfig.h. Set them to zero if there is no MTIME (machine time) clock. See www.FreeRTOS.org/Using-FreeRTOS-on-RISC-V.html" +#endif /* if defined( configCLINT_BASE_ADDRESS ) && !defined( configMTIME_BASE_ADDRESS ) && ( configCLINT_BASE_ADDRESS == 0 ) */ /* *INDENT-OFF* */ #ifdef __cplusplus diff --git a/Source/portable/GCC/RL78/isr_support.h b/Source/portable/GCC/RL78/isr_support.h index 61e3502a9..b081fe556 100644 --- a/Source/portable/GCC/RL78/isr_support.h +++ b/Source/portable/GCC/RL78/isr_support.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -27,8 +27,8 @@ */ /* Variables used by scheduler */ - .extern _pxCurrentTCB - .extern _usCriticalNesting +.extern _pxCurrentTCB + .extern _usCriticalNesting /* * portSAVE_CONTEXT MACRO @@ -36,47 +36,47 @@ * memory mode) registers the usCriticalNesting Value and the Stack Pointer * of the active Task onto the task stack */ - .macro portSAVE_CONTEXT + .macro portSAVE_CONTEXT - SEL RB0 +SEL RB0 - /* Save AX Register to stack. */ - PUSH AX - PUSH HL - /* Save CS register. */ - MOV A, CS - XCH A, X - /* Save ES register. */ - MOV A, ES - PUSH AX - /* Save the remaining general purpose registers from bank 0. */ - PUSH DE - PUSH BC - /* Save the other register banks - only necessary in the GCC port. */ - SEL RB1 - PUSH AX - PUSH BC - PUSH DE - PUSH HL - SEL RB2 - PUSH AX - PUSH BC - PUSH DE - PUSH HL - /* Registers in bank 3 are for ISR use only so don't need saving. */ - SEL RB0 - /* Save the usCriticalNesting value. */ - MOVW AX, !_usCriticalNesting - PUSH AX - /* Save the Stack pointer. */ - MOVW AX, !_pxCurrentTCB - MOVW HL, AX - MOVW AX, SP - MOVW [HL], AX - /* Switch stack pointers. */ - movw sp,#_stack /* Set stack pointer */ +/* Save AX Register to stack. */ +PUSH AX +PUSH HL +/* Save CS register. */ +MOV A, CS +XCH A, X +/* Save ES register. */ +MOV A, ES +PUSH AX +/* Save the remaining general purpose registers from bank 0. */ +PUSH DE +PUSH BC +/* Save the other register banks - only necessary in the GCC port. */ +SEL RB1 +PUSH AX +PUSH BC +PUSH DE +PUSH HL +SEL RB2 +PUSH AX +PUSH BC +PUSH DE +PUSH HL +/* Registers in bank 3 are for ISR use only so don't need saving. */ +SEL RB0 +/* Save the usCriticalNesting value. */ +MOVW AX, !_usCriticalNesting +PUSH AX +/* Save the Stack pointer. */ +MOVW AX, !_pxCurrentTCB +MOVW HL, AX +MOVW AX, SP +MOVW[ HL ], AX +/* Switch stack pointers. */ +movw sp, # _stack /* Set stack pointer */ - .endm + .endm /* @@ -85,42 +85,43 @@ * general purpose registers and the CS and ES (only in far memory mode) * of the selected task from the task stack */ -.macro portRESTORE_CONTEXT MACRO - SEL RB0 - /* Restore the Stack pointer. */ - MOVW AX, !_pxCurrentTCB - MOVW HL, AX - MOVW AX, [HL] - MOVW SP, AX - /* Restore usCriticalNesting value. */ - POP AX - MOVW !_usCriticalNesting, AX - /* Restore the alternative register banks - only necessary in the GCC - port. Register bank 3 is dedicated for interrupts use so is not saved or - restored. */ - SEL RB2 - POP HL - POP DE - POP BC - POP AX - SEL RB1 - POP HL - POP DE - POP BC - POP AX - SEL RB0 - /* Restore the necessary general purpose registers. */ - POP BC - POP DE - /* Restore the ES register. */ - POP AX - MOV ES, A - /* Restore the CS register. */ - XCH A, X - MOV CS, A - /* Restore general purpose register HL. */ - POP HL - /* Restore AX. */ - POP AX + .macro portRESTORE_CONTEXT MACRO +SEL RB0 +/* Restore the Stack pointer. */ +MOVW AX, !_pxCurrentTCB +MOVW HL, AX +MOVW AX, [ HL ] +MOVW SP, AX +/* Restore usCriticalNesting value. */ +POP AX +MOVW !_usCriticalNesting, AX - .endm +/* Restore the alternative register banks - only necessary in the GCC + * port. Register bank 3 is dedicated for interrupts use so is not saved or + * restored. */ +SEL RB2 +POP HL +POP DE +POP BC +POP AX +SEL RB1 +POP HL +POP DE +POP BC +POP AX +SEL RB0 +/* Restore the necessary general purpose registers. */ +POP BC +POP DE +/* Restore the ES register. */ +POP AX +MOV ES, A +/* Restore the CS register. */ +XCH A, X +MOV CS, A +/* Restore general purpose register HL. */ +POP HL +/* Restore AX. */ +POP AX + + .endm diff --git a/Source/portable/GCC/RL78/port.c b/Source/portable/GCC/RL78/port.c index 5ad8394d7..54026849f 100644 --- a/Source/portable/GCC/RL78/port.c +++ b/Source/portable/GCC/RL78/port.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -31,8 +31,8 @@ #include "task.h" /* The critical nesting value is initialised to a non zero value to ensure -interrupts don't accidentally become enabled before the scheduler is started. */ -#define portINITIAL_CRITICAL_NESTING ( ( uint16_t ) 10 ) + * interrupts don't accidentally become enabled before the scheduler is started. */ +#define portINITIAL_CRITICAL_NESTING ( ( uint16_t ) 10 ) /* Initial PSW value allocated to a newly created task. * 11000110 @@ -45,16 +45,16 @@ interrupts don't accidentally become enabled before the scheduler is started. */ * |--------------------- Zero Flag set * ---------------------- Global Interrupt Flag set (enabled) */ -#define portPSW ( 0xc6UL ) +#define portPSW ( 0xc6UL ) /* Each task maintains a count of the critical section nesting depth. Each time -a critical section is entered the count is incremented. Each time a critical -section is exited the count is decremented - with interrupts only being -re-enabled if the count is zero. - -usCriticalNesting will get set to zero when the scheduler starts, but must -not be initialised to zero as that could cause problems during the startup -sequence. */ + * a critical section is entered the count is incremented. Each time a critical + * section is exited the count is decremented - with interrupts only being + * re-enabled if the count is zero. + * + * usCriticalNesting will get set to zero when the scheduler starts, but must + * not be initialised to zero as that could cause problems during the startup + * sequence. */ volatile uint16_t usCriticalNesting = portINITIAL_CRITICAL_NESTING; /*-----------------------------------------------------------*/ @@ -62,7 +62,7 @@ volatile uint16_t usCriticalNesting = portINITIAL_CRITICAL_NESTING; /* * Sets up the periodic ISR used for the RTOS tick. */ -__attribute__((weak)) void vApplicationSetupTimerInterrupt( void ); +__attribute__( ( weak ) ) void vApplicationSetupTimerInterrupt( void ); /* * Starts the scheduler by loading the context of the first task to run. @@ -78,30 +78,32 @@ extern void vPortStartFirstTask( void ); * * See the header file portable.h. */ -StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters ) +StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, + TaskFunction_t pxCode, + void * pvParameters ) { -uint32_t *pulLocal; + uint32_t * pulLocal; /* Stack type and pointers to the stack type are both 2 bytes. */ /* Parameters are passed in on the stack, and written using a 32bit value - hence a space is left for the second two bytes. */ + * hence a space is left for the second two bytes. */ pxTopOfStack--; /* Write in the parameter value. */ - pulLocal = ( uint32_t * ) pxTopOfStack; + pulLocal = ( uint32_t * ) pxTopOfStack; *pulLocal = ( StackType_t ) pvParameters; pxTopOfStack--; /* The return address, leaving space for the first two bytes of the - 32-bit value. */ + * 32-bit value. */ pxTopOfStack--; pulLocal = ( uint32_t * ) pxTopOfStack; *pulLocal = ( uint32_t ) 0; pxTopOfStack--; /* The start address / PSW value is also written in as a 32bit value, - so leave a space for the second two bytes. */ + * so leave a space for the second two bytes. */ pxTopOfStack--; /* Task function start address combined with the PSW. */ @@ -122,24 +124,24 @@ uint32_t *pulLocal; pxTopOfStack--; /* The remaining general purpose registers bank 0 (DE and BC) and the other - two register banks...register bank 3 is dedicated for use by interrupts so - is not saved as part of the task context. */ + * two register banks...register bank 3 is dedicated for use by interrupts so + * is not saved as part of the task context. */ pxTopOfStack -= 10; /* Finally the critical section nesting count is set to zero when the task - first starts. */ + * first starts. */ *pxTopOfStack = ( StackType_t ) portNO_CRITICAL_SECTION_NESTING; - /* Return a pointer to the top of the stack that has beene generated so it - can be stored in the task control block for the task. */ + /* Return a pointer to the top of the stack that has been generated so it + * can be stored in the task control block for the task. */ return pxTopOfStack; } /*-----------------------------------------------------------*/ -portBASE_TYPE xPortStartScheduler( void ) +BaseType_t xPortStartScheduler( void ) { /* Setup the hardware to generate the tick. Interrupts are disabled when - this function is called. */ + * this function is called. */ vApplicationSetupTimerInterrupt(); /* Restore the context of the first task that is going to run. */ @@ -156,10 +158,10 @@ void vPortEndScheduler( void ) } /*-----------------------------------------------------------*/ -__attribute__((weak)) void vApplicationSetupTimerInterrupt( void ) +__attribute__( ( weak ) ) void vApplicationSetupTimerInterrupt( void ) { -const uint16_t usClockHz = 15000UL; /* Internal clock. */ -const uint16_t usCompareMatch = ( usClockHz / configTICK_RATE_HZ ) + 1UL; + const uint16_t usClockHz = 15000UL; /* Internal clock. */ + const uint16_t usCompareMatch = ( usClockHz / configTICK_RATE_HZ ) + 1UL; /* Use the internal 15K clock. */ OSMC = ( unsigned char ) 0x16; @@ -184,7 +186,7 @@ const uint16_t usCompareMatch = ( usClockHz / configTICK_RATE_HZ ) + 1UL; /* Enable INTIT interrupt. */ ITMK = ( unsigned char ) 0; } - #endif + #endif /* ifdef RTCEN */ #ifdef TMKAEN { @@ -206,6 +208,6 @@ const uint16_t usCompareMatch = ( usClockHz / configTICK_RATE_HZ ) + 1UL; /* Enable INTIT interrupt. */ TMKAMK = ( unsigned char ) 0; } - #endif + #endif /* ifdef TMKAEN */ } /*-----------------------------------------------------------*/ diff --git a/Source/portable/GCC/RL78/portasm.S b/Source/portable/GCC/RL78/portasm.S index 49ff24a75..1b6104938 100644 --- a/Source/portable/GCC/RL78/portasm.S +++ b/Source/portable/GCC/RL78/portasm.S @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/Source/portable/GCC/RL78/portmacro.h b/Source/portable/GCC/RL78/portmacro.h index 6e59572a4..2e980d57b 100644 --- a/Source/portable/GCC/RL78/portmacro.h +++ b/Source/portable/GCC/RL78/portmacro.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -41,83 +41,83 @@ /* Type definitions. */ -#define portCHAR char -#define portFLOAT float -#define portDOUBLE double -#define portLONG long -#define portSHORT short -#define portSTACK_TYPE uint16_t -#define portBASE_TYPE short -#define portPOINTER_SIZE_TYPE uint16_t +#define portCHAR char +#define portFLOAT float +#define portDOUBLE double +#define portLONG long +#define portSHORT short +#define portSTACK_TYPE uint16_t +#define portBASE_TYPE short +#define portPOINTER_SIZE_TYPE uint16_t -typedef portSTACK_TYPE StackType_t; -typedef short BaseType_t; -typedef unsigned short UBaseType_t; +typedef portSTACK_TYPE StackType_t; +typedef short BaseType_t; +typedef unsigned short UBaseType_t; -#if( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS ) - typedef uint16_t TickType_t; - #define portMAX_DELAY ( TickType_t ) 0xffff +#if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS ) + typedef uint16_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffff #elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS ) - typedef uint32_t TickType_t; - #define portMAX_DELAY ( TickType_t ) ( 0xFFFFFFFFUL ) + typedef uint32_t TickType_t; + #define portMAX_DELAY ( TickType_t ) ( 0xFFFFFFFFUL ) #else #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width. #endif /*-----------------------------------------------------------*/ /* Interrupt control macros. */ -#define portDISABLE_INTERRUPTS() __asm volatile ( "DI" ) -#define portENABLE_INTERRUPTS() __asm volatile ( "EI" ) +#define portDISABLE_INTERRUPTS() __asm volatile ( "DI" ) +#define portENABLE_INTERRUPTS() __asm volatile ( "EI" ) /*-----------------------------------------------------------*/ /* Critical section control macros. */ -#define portNO_CRITICAL_SECTION_NESTING ( ( unsigned short ) 0 ) +#define portNO_CRITICAL_SECTION_NESTING ( ( unsigned short ) 0 ) -#define portENTER_CRITICAL() \ -{ \ -extern volatile uint16_t usCriticalNesting; \ - \ - portDISABLE_INTERRUPTS(); \ - \ - /* Now interrupts are disabled ulCriticalNesting can be accessed */ \ - /* directly. Increment ulCriticalNesting to keep a count of how many */ \ - /* times portENTER_CRITICAL() has been called. */ \ - usCriticalNesting++; \ -} +#define portENTER_CRITICAL() \ + { \ + extern volatile uint16_t usCriticalNesting; \ + \ + portDISABLE_INTERRUPTS(); \ + \ + /* Now that interrupts are disabled, ulCriticalNesting can be accessed */ \ + /* directly. Increment ulCriticalNesting to keep a count of how many */ \ + /* times portENTER_CRITICAL() has been called. */ \ + usCriticalNesting++; \ + } -#define portEXIT_CRITICAL() \ -{ \ -extern volatile uint16_t usCriticalNesting; \ - \ - if( usCriticalNesting > portNO_CRITICAL_SECTION_NESTING ) \ - { \ - /* Decrement the nesting count as we are leaving a critical section. */ \ - usCriticalNesting--; \ - \ - /* If the nesting level has reached zero then interrupts should be */ \ - /* re-enabled. */ \ - if( usCriticalNesting == portNO_CRITICAL_SECTION_NESTING ) \ - { \ - portENABLE_INTERRUPTS(); \ - } \ - } \ -} +#define portEXIT_CRITICAL() \ + { \ + extern volatile uint16_t usCriticalNesting; \ + \ + if( usCriticalNesting > portNO_CRITICAL_SECTION_NESTING ) \ + { \ + /* Decrement the nesting count as we are leaving a critical section. */ \ + usCriticalNesting--; \ + \ + /* If the nesting level has reached zero then interrupts should be */ \ + /* re-enabled. */ \ + if( usCriticalNesting == portNO_CRITICAL_SECTION_NESTING ) \ + { \ + portENABLE_INTERRUPTS(); \ + } \ + } \ + } /*-----------------------------------------------------------*/ /* Task utilities. */ -#define portYIELD() __asm volatile ( "BRK" ) -#define portYIELD_FROM_ISR( xHigherPriorityTaskWoken ) do { if( xHigherPriorityTaskWoken ) vTaskSwitchContext(); } while( 0 ) -#define portNOP() __asm volatile ( "NOP" ) +#define portYIELD() __asm volatile ( "BRK" ) +#define portYIELD_FROM_ISR( xHigherPriorityTaskWoken ) do { if( xHigherPriorityTaskWoken ) vTaskSwitchContext( ); } while( 0 ) +#define portNOP() __asm volatile ( "NOP" ) /*-----------------------------------------------------------*/ -/* Hardwware specifics. */ -#define portBYTE_ALIGNMENT 2 -#define portSTACK_GROWTH ( -1 ) -#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) +/* Hardware specifics. */ +#define portBYTE_ALIGNMENT 2 +#define portSTACK_GROWTH ( -1 ) +#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) /*-----------------------------------------------------------*/ /* Task function macros as described on the FreeRTOS.org WEB site. */ -#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters ) -#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters ) +#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters ) +#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters ) #endif /* PORTMACRO_H */ diff --git a/Source/portable/GCC/RX100/port.c b/Source/portable/GCC/RX100/port.c index f7ef152c4..0916f29f5 100644 --- a/Source/portable/GCC/RX100/port.c +++ b/Source/portable/GCC/RX100/port.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -27,8 +27,8 @@ */ /*----------------------------------------------------------- - * Implementation of functions defined in portable.h for the SH2A port. - *----------------------------------------------------------*/ +* Implementation of functions defined in portable.h for the SH2A port. +*----------------------------------------------------------*/ /* Standard C includes. */ #include "limits.h" @@ -53,36 +53,36 @@ /*-----------------------------------------------------------*/ /* Tasks should start with interrupts enabled and in Supervisor mode, therefore -PSW is set with U and I set, and PM and IPL clear. */ -#define portINITIAL_PSW ( ( StackType_t ) 0x00030000 ) + * PSW is set with U and I set, and PM and IPL clear. */ +#define portINITIAL_PSW ( ( StackType_t ) 0x00030000 ) /* The peripheral clock is divided by this value before being supplying the -CMT. */ + * CMT. */ #if ( configUSE_TICKLESS_IDLE == 0 ) /* If tickless idle is not used then the divisor can be fixed. */ - #define portCLOCK_DIVISOR 8UL + #define portCLOCK_DIVISOR 8UL #elif ( configPERIPHERAL_CLOCK_HZ >= 12000000 ) - #define portCLOCK_DIVISOR 512UL + #define portCLOCK_DIVISOR 512UL #elif ( configPERIPHERAL_CLOCK_HZ >= 6000000 ) - #define portCLOCK_DIVISOR 128UL + #define portCLOCK_DIVISOR 128UL #elif ( configPERIPHERAL_CLOCK_HZ >= 1000000 ) - #define portCLOCK_DIVISOR 32UL + #define portCLOCK_DIVISOR 32UL #else - #define portCLOCK_DIVISOR 8UL + #define portCLOCK_DIVISOR 8UL #endif /* These macros allow a critical section to be added around the call to -xTaskIncrementTick(), which is only ever called from interrupts at the kernel -priority - ie a known priority. Therefore these local macros are a slight -optimisation compared to calling the global SET/CLEAR_INTERRUPT_MASK macros, -which would require the old IPL to be read first and stored in a local variable. */ -#define portDISABLE_INTERRUPTS_FROM_KERNEL_ISR() __asm volatile ( "MVTIPL %0" ::"i"(configMAX_SYSCALL_INTERRUPT_PRIORITY) ) -#define portENABLE_INTERRUPTS_FROM_KERNEL_ISR() __asm volatile ( "MVTIPL %0" ::"i"(configKERNEL_INTERRUPT_PRIORITY) ) + * xTaskIncrementTick(), which is only ever called from interrupts at the kernel + * priority - ie a known priority. Therefore these local macros are a slight + * optimisation compared to calling the global SET/CLEAR_INTERRUPT_MASK macros, + * which would require the old IPL to be read first and stored in a local variable. */ +#define portDISABLE_INTERRUPTS_FROM_KERNEL_ISR() __asm volatile ( "MVTIPL %0" ::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) ) +#define portENABLE_INTERRUPTS_FROM_KERNEL_ISR() __asm volatile ( "MVTIPL %0" ::"i" ( configKERNEL_INTERRUPT_PRIORITY ) ) /* Keys required to lock and unlock access to certain system registers -respectively. */ -#define portUNLOCK_KEY 0xA50B -#define portLOCK_KEY 0xA500 + * respectively. */ +#define portUNLOCK_KEY 0xA50B +#define portLOCK_KEY 0xA500 /*-----------------------------------------------------------*/ @@ -90,7 +90,7 @@ respectively. */ * Function to start the first task executing - written in asm code as direct * access to registers is required. */ -static void prvStartFirstTask( void ) __attribute__((naked)); +static void prvStartFirstTask( void ) __attribute__( ( naked ) ); /* * Software interrupt handler. Performs the actual context switch (saving and @@ -131,9 +131,10 @@ static void prvStartFirstTask( void ) __attribute__((naked)); */ static void prvSetupTimerInterrupt( void ); #ifndef configSETUP_TICK_INTERRUPT - /* The user has not provided their own tick interrupt configuration so use - the definition in this file (which uses the interval timer). */ - #define configSETUP_TICK_INTERRUPT() prvSetupTimerInterrupt() + +/* The user has not provided their own tick interrupt configuration so use + * the definition in this file (which uses the interval timer). */ + #define configSETUP_TICK_INTERRUPT() prvSetupTimerInterrupt() #endif /* configSETUP_TICK_INTERRUPT */ /* @@ -148,40 +149,42 @@ static void prvSetupTimerInterrupt( void ); /*-----------------------------------------------------------*/ /* Used in the context save and restore code. */ -extern void *pxCurrentTCB; +extern void * pxCurrentTCB; /* Calculate how many clock increments make up a single tick period. */ static const uint32_t ulMatchValueForOneTick = ( ( configPERIPHERAL_CLOCK_HZ / portCLOCK_DIVISOR ) / configTICK_RATE_HZ ); #if configUSE_TICKLESS_IDLE == 1 - /* Holds the maximum number of ticks that can be suppressed - which is - basically how far into the future an interrupt can be generated. Set - during initialisation. This is the maximum possible value that the - compare match register can hold divided by ulMatchValueForOneTick. */ +/* Holds the maximum number of ticks that can be suppressed - which is + * basically how far into the future an interrupt can be generated. Set + * during initialisation. This is the maximum possible value that the + * compare match register can hold divided by ulMatchValueForOneTick. */ static const TickType_t xMaximumPossibleSuppressedTicks = USHRT_MAX / ( ( configPERIPHERAL_CLOCK_HZ / portCLOCK_DIVISOR ) / configTICK_RATE_HZ ); - /* Flag set from the tick interrupt to allow the sleep processing to know if - sleep mode was exited because of a tick interrupt, or an interrupt - generated by something else. */ +/* Flag set from the tick interrupt to allow the sleep processing to know if + * sleep mode was exited because of a tick interrupt, or an interrupt + * generated by something else. */ static volatile uint32_t ulTickFlag = pdFALSE; - /* The CMT counter is stopped temporarily each time it is re-programmed. - The following constant offsets the CMT counter match value by the number of - CMT counts that would typically be missed while the counter was stopped to - compensate for the lost time. The large difference between the divided CMT - clock and the CPU clock means it is likely ulStoppedTimerCompensation will - equal zero - and be optimised away. */ +/* The CMT counter is stopped temporarily each time it is re-programmed. + * The following constant offsets the CMT counter match value by the number of + * CMT counts that would typically be missed while the counter was stopped to + * compensate for the lost time. The large difference between the divided CMT + * clock and the CPU clock means it is likely ulStoppedTimerCompensation will + * equal zero - and be optimised away. */ static const uint32_t ulStoppedTimerCompensation = 100UL / ( configCPU_CLOCK_HZ / ( configPERIPHERAL_CLOCK_HZ / portCLOCK_DIVISOR ) ); -#endif +#endif /* if configUSE_TICKLESS_IDLE == 1 */ /*-----------------------------------------------------------*/ /* * See header file for description. */ -StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters ) +StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, + TaskFunction_t pxCode, + void * pvParameters ) { /* Offset to end up on 8 byte boundary. */ pxTopOfStack--; @@ -196,8 +199,8 @@ StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t px *pxTopOfStack = ( StackType_t ) pxCode; /* When debugging it can be useful if every register is set to a known - value. Otherwise code space can be saved by just setting the registers - that need to be set. */ + * value. Otherwise code space can be saved by just setting the registers + * that need to be set. */ #ifdef USE_FULL_REGISTER_INITIALISATION { pxTopOfStack--; @@ -230,19 +233,19 @@ StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t px *pxTopOfStack = 0x22222222; pxTopOfStack--; } - #else + #else /* ifdef USE_FULL_REGISTER_INITIALISATION */ { /* Leave space for the registers that will get popped from the stack - when the task first starts executing. */ + * when the task first starts executing. */ pxTopOfStack -= 15; } - #endif + #endif /* ifdef USE_FULL_REGISTER_INITIALISATION */ *pxTopOfStack = ( StackType_t ) pvParameters; /* R1 */ pxTopOfStack--; - *pxTopOfStack = 0x12345678; /* Accumulator. */ + *pxTopOfStack = 0x12345678; /* Accumulator. */ pxTopOfStack--; - *pxTopOfStack = 0x87654321; /* Accumulator. */ + *pxTopOfStack = 0x87654321; /* Accumulator. */ return pxTopOfStack; } @@ -254,10 +257,10 @@ BaseType_t xPortStartScheduler( void ) if( pxCurrentTCB != NULL ) { /* Call an application function to set up the timer that will generate - the tick interrupt. This way the application can decide which - peripheral to use. If tickless mode is used then the default - implementation defined in this file (which uses CMT0) should not be - overridden. */ + * the tick interrupt. This way the application can decide which + * peripheral to use. If tickless mode is used then the default + * implementation defined in this file (which uses CMT0) should not be + * overridden. */ configSETUP_TICK_INTERRUPT(); /* Enable the software interrupt. */ @@ -274,11 +277,11 @@ BaseType_t xPortStartScheduler( void ) } /* Execution should not reach here as the tasks are now running! - prvSetupTimerInterrupt() is called here to prevent the compiler outputting - a warning about a statically declared function not being referenced in the - case that the application writer has provided their own tick interrupt - configuration routine (and defined configSETUP_TICK_INTERRUPT() such that - their own routine will be called in place of prvSetupTimerInterrupt()). */ + * prvSetupTimerInterrupt() is called here to prevent the compiler outputting + * a warning about a statically declared function not being referenced in the + * case that the application writer has provided their own tick interrupt + * configuration routine (and defined configSETUP_TICK_INTERRUPT() such that + * their own routine will be called in place of prvSetupTimerInterrupt()). */ prvSetupTimerInterrupt(); /* Should not get here. */ @@ -289,7 +292,7 @@ BaseType_t xPortStartScheduler( void ) void vPortEndScheduler( void ) { /* Not implemented in ports where there is nothing to return to. - Artificially force an assert. */ + * Artificially force an assert. */ configASSERT( pxCurrentTCB == NULL ); } /*-----------------------------------------------------------*/ @@ -298,19 +301,22 @@ static void prvStartFirstTask( void ) { __asm volatile ( + /* When starting the scheduler there is nothing that needs moving to the - interrupt stack because the function is not called from an interrupt. - Just ensure the current stack is the user stack. */ + * interrupt stack because the function is not called from an interrupt. + * Just ensure the current stack is the user stack. */ "SETPSW U \n" \ + /* Obtain the location of the stack associated with which ever task - pxCurrentTCB is currently pointing to. */ + * pxCurrentTCB is currently pointing to. */ "MOV.L #_pxCurrentTCB, R15 \n" \ "MOV.L [R15], R15 \n" \ "MOV.L [R15], R0 \n" \ + /* Restore the registers from the stack of the task pointed to by - pxCurrentTCB. */ + * pxCurrentTCB. */ "POP R15 \n" \ /* Accumulator low 32 bits. */ @@ -338,10 +344,11 @@ void vPortSoftwareInterruptISR( void ) /* Re-enable interrupts. */ "SETPSW I \n" \ - /* Move the data that was automatically pushed onto the interrupt stack when - the interrupt occurred from the interrupt stack to the user stack. - R15 is saved before it is clobbered. */ + /* Move the data that was automatically pushed onto the interrupt stack when + * the interrupt occurred from the interrupt stack to the user stack. + * + * R15 is saved before it is clobbered. */ "PUSH.L R15 \n" \ /* Read the user stack pointer. */ @@ -381,8 +388,9 @@ void vPortSoftwareInterruptISR( void ) "MOV.L [ R15 ], R15 \n" \ "MOV.L R0, [ R15 ] \n" \ + /* Ensure the interrupt mask is set to the syscall priority while the kernel - structures are being accessed. */ + * structures are being accessed. */ "MVTIPL %0 \n" \ /* Select the next task to run. */ @@ -391,14 +399,16 @@ void vPortSoftwareInterruptISR( void ) /* Reset the interrupt mask as no more data structure access is required. */ "MVTIPL %1 \n" \ + /* Load the stack pointer of the task that is now selected as the Running - state task from its TCB. */ + * state task from its TCB. */ "MOV.L #_pxCurrentTCB,R15 \n" \ "MOV.L [ R15 ], R15 \n" \ "MOV.L [ R15 ], R0 \n" \ + /* Restore the context of the new task. The PSW (Program Status Word) and - PC will be popped by the RTE instruction. */ + * PC will be popped by the RTE instruction. */ "POP R15 \n" \ "MVTACLO R15 \n" \ "POP R15 \n" \ @@ -407,7 +417,7 @@ void vPortSoftwareInterruptISR( void ) "RTE \n" \ "NOP \n" \ "NOP " - :: "i"(configMAX_SYSCALL_INTERRUPT_PRIORITY), "i"(configKERNEL_INTERRUPT_PRIORITY) + ::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ), "i" ( configKERNEL_INTERRUPT_PRIORITY ) ); } /*-----------------------------------------------------------*/ @@ -415,10 +425,10 @@ void vPortSoftwareInterruptISR( void ) void vPortTickISR( void ) { /* Re-enabled interrupts. */ - __asm volatile( "SETPSW I" ); + __asm volatile ( "SETPSW I" ); /* Increment the tick, and perform any processing the new tick value - necessitates. Ensure IPL is at the max syscall value first. */ + * necessitates. Ensure IPL is at the max syscall value first. */ portDISABLE_INTERRUPTS_FROM_KERNEL_ISR(); { if( xTaskIncrementTick() != pdFALSE ) @@ -434,7 +444,7 @@ void vPortTickISR( void ) ulTickFlag = pdTRUE; /* If this is the first tick since exiting tickless mode then the CMT - compare match value needs resetting. */ + * compare match value needs resetting. */ CMT0.CMCOR = ( uint16_t ) ulMatchValueForOneTick; } #endif @@ -467,7 +477,7 @@ void vPortSetIPL( uint32_t ulNewIPL ) "MVTC R5, PSW \n" \ "POP R5 \n" \ "RTS " - ); + ); } /*-----------------------------------------------------------*/ @@ -505,11 +515,11 @@ static void prvSetupTimerInterrupt( void ) { CMT0.CMCR.BIT.CKS = 0; } - #else + #else /* if portCLOCK_DIVISOR == 512 */ { #error Invalid portCLOCK_DIVISOR setting } - #endif + #endif /* if portCLOCK_DIVISOR == 512 */ /* Enable the interrupt... */ _IEN( _CMT0_CMI0 ) = 1; @@ -530,11 +540,11 @@ static void prvSetupTimerInterrupt( void ) configPRE_SLEEP_PROCESSING( xExpectedIdleTime ); /* xExpectedIdleTime being set to 0 by configPRE_SLEEP_PROCESSING() - means the application defined code has already executed the WAIT - instruction. */ + * means the application defined code has already executed the WAIT + * instruction. */ if( xExpectedIdleTime > 0 ) { - __asm volatile( "WAIT" ); + __asm volatile ( "WAIT" ); } /* Allow the application to define some post sleep processing. */ @@ -548,8 +558,8 @@ static void prvSetupTimerInterrupt( void ) void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime ) { - uint32_t ulMatchValue, ulCompleteTickPeriods, ulCurrentCount; - eSleepModeStatus eSleepAction; + uint32_t ulMatchValue, ulCompleteTickPeriods, ulCurrentCount; + eSleepModeStatus eSleepAction; /* THIS FUNCTION IS CALLED WITH THE SCHEDULER SUSPENDED. */ @@ -560,43 +570,46 @@ static void prvSetupTimerInterrupt( void ) } /* Calculate the reload value required to wait xExpectedIdleTime tick - periods. */ + * periods. */ ulMatchValue = ulMatchValueForOneTick * xExpectedIdleTime; + if( ulMatchValue > ulStoppedTimerCompensation ) { /* Compensate for the fact that the CMT is going to be stopped - momentarily. */ + * momentarily. */ ulMatchValue -= ulStoppedTimerCompensation; } /* Stop the CMT momentarily. The time the CMT is stopped for is - accounted for as best it can be, but using the tickless mode will - inevitably result in some tiny drift of the time maintained by the - kernel with respect to calendar time. */ + * accounted for as best it can be, but using the tickless mode will + * inevitably result in some tiny drift of the time maintained by the + * kernel with respect to calendar time. */ CMT.CMSTR0.BIT.STR0 = 0; + while( CMT.CMSTR0.BIT.STR0 == 1 ) { /* Nothing to do here. */ } /* Critical section using the global interrupt bit as the i bit is - automatically reset by the WAIT instruction. */ - __asm volatile( "CLRPSW i" ); + * automatically reset by the WAIT instruction. */ + __asm volatile ( "CLRPSW i" ); /* The tick flag is set to false before sleeping. If it is true when - sleep mode is exited then sleep mode was probably exited because the - tick was suppressed for the entire xExpectedIdleTime period. */ + * sleep mode is exited then sleep mode was probably exited because the + * tick was suppressed for the entire xExpectedIdleTime period. */ ulTickFlag = pdFALSE; /* If a context switch is pending then abandon the low power entry as - the context switch might have been pended by an external interrupt that - requires processing. */ + * the context switch might have been pended by an external interrupt that + * requires processing. */ eSleepAction = eTaskConfirmSleepModeStatus(); + if( eSleepAction == eAbortSleep ) { /* Restart tick. */ CMT.CMSTR0.BIT.STR0 = 1; - __asm volatile( "SETPSW i" ); + __asm volatile ( "SETPSW i" ); } else if( eSleepAction == eNoTasksWaitingTimeout ) { @@ -610,7 +623,7 @@ static void prvSetupTimerInterrupt( void ) SYSTEM.PRCR.WORD = portLOCK_KEY; /* Sleep until something happens. Calling prvSleep() will - automatically reset the i bit in the PSW. */ + * automatically reset the i bit in the PSW. */ prvSleep( xExpectedIdleTime ); /* Restart the CMT. */ @@ -630,7 +643,7 @@ static void prvSetupTimerInterrupt( void ) SYSTEM.PRCR.WORD = portLOCK_KEY; /* Adjust the match value to take into account that the current - time slice is already partially complete. */ + * time slice is already partially complete. */ ulMatchValue -= ( uint32_t ) CMT0.CMCNT; CMT0.CMCOR = ( uint16_t ) ulMatchValue; @@ -639,14 +652,15 @@ static void prvSetupTimerInterrupt( void ) CMT.CMSTR0.BIT.STR0 = 1; /* Sleep until something happens. Calling prvSleep() will - automatically reset the i bit in the PSW. */ + * automatically reset the i bit in the PSW. */ prvSleep( xExpectedIdleTime ); /* Stop CMT. Again, the time the SysTick is stopped for is - accounted for as best it can be, but using the tickless mode will - inevitably result in some tiny drift of the time maintained by the - kernel with respect to calendar time. */ + * accounted for as best it can be, but using the tickless mode will + * inevitably result in some tiny drift of the time maintained by the + * kernel with respect to calendar time. */ CMT.CMSTR0.BIT.STR0 = 0; + while( CMT.CMSTR0.BIT.STR0 == 1 ) { /* Nothing to do here. */ @@ -657,42 +671,42 @@ static void prvSetupTimerInterrupt( void ) if( ulTickFlag != pdFALSE ) { /* The tick interrupt has already executed, although because - this function is called with the scheduler suspended the actual - tick processing will not occur until after this function has - exited. Reset the match value with whatever remains of this - tick period. */ + * this function is called with the scheduler suspended the actual + * tick processing will not occur until after this function has + * exited. Reset the match value with whatever remains of this + * tick period. */ ulMatchValue = ulMatchValueForOneTick - ulCurrentCount; CMT0.CMCOR = ( uint16_t ) ulMatchValue; /* The tick interrupt handler will already have pended the tick - processing in the kernel. As the pending tick will be - processed as soon as this function exits, the tick value - maintained by the tick is stepped forward by one less than the - time spent sleeping. The actual stepping of the tick appears - later in this function. */ + * processing in the kernel. As the pending tick will be + * processed as soon as this function exits, the tick value + * maintained by the tick is stepped forward by one less than the + * time spent sleeping. The actual stepping of the tick appears + * later in this function. */ ulCompleteTickPeriods = xExpectedIdleTime - 1UL; } else { /* Something other than the tick interrupt ended the sleep. - How many complete tick periods passed while the processor was - sleeping? */ + * How many complete tick periods passed while the processor was + * sleeping? */ ulCompleteTickPeriods = ulCurrentCount / ulMatchValueForOneTick; /* The match value is set to whatever fraction of a single tick - period remains. */ + * period remains. */ ulMatchValue = ulCurrentCount - ( ulCompleteTickPeriods * ulMatchValueForOneTick ); CMT0.CMCOR = ( uint16_t ) ulMatchValue; } /* Restart the CMT so it runs up to the match value. The match value - will get set to the value required to generate exactly one tick period - the next time the CMT interrupt executes. */ + * will get set to the value required to generate exactly one tick period + * the next time the CMT interrupt executes. */ CMT0.CMCNT = 0; CMT.CMSTR0.BIT.STR0 = 1; /* Wind the tick forward by the number of tick periods that the CPU - remained in a low power state. */ + * remained in a low power state. */ vTaskStepTick( ulCompleteTickPeriods ); } } diff --git a/Source/portable/GCC/RX100/portmacro.h b/Source/portable/GCC/RX100/portmacro.h index eab1f353e..87c2d6ca9 100644 --- a/Source/portable/GCC/RX100/portmacro.h +++ b/Source/portable/GCC/RX100/portmacro.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -45,80 +45,81 @@ * These settings should not be altered. *----------------------------------------------------------- */ + /* When the FIT configurator or the Smart Configurator is used, platform.h has to be * used. */ #ifndef configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H - #define configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H 0 + #define configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H 0 #endif /* Type definitions - these are a bit legacy and not really used now, other than -portSTACK_TYPE and portBASE_TYPE. */ -#define portCHAR char -#define portFLOAT float -#define portDOUBLE double -#define portLONG long -#define portSHORT short -#define portSTACK_TYPE uint32_t -#define portBASE_TYPE long - -typedef portSTACK_TYPE StackType_t; -typedef long BaseType_t; -typedef unsigned long UBaseType_t; - -#if( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS ) - typedef uint16_t TickType_t; - #define portMAX_DELAY ( TickType_t ) 0xffff + * portSTACK_TYPE and portBASE_TYPE. */ +#define portCHAR char +#define portFLOAT float +#define portDOUBLE double +#define portLONG long +#define portSHORT short +#define portSTACK_TYPE uint32_t +#define portBASE_TYPE long + +typedef portSTACK_TYPE StackType_t; +typedef long BaseType_t; +typedef unsigned long UBaseType_t; + +#if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS ) + typedef uint16_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffff #elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS ) - typedef uint32_t TickType_t; - #define portMAX_DELAY ( TickType_t ) 0xffffffffUL + typedef uint32_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffffffffUL - /* 32-bit tick type on a 32-bit architecture, so reads of the tick count do - not need to be guarded with a critical section. */ - #define portTICK_TYPE_IS_ATOMIC 1 +/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do + * not need to be guarded with a critical section. */ + #define portTICK_TYPE_IS_ATOMIC 1 #else #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width. #endif /*-----------------------------------------------------------*/ /* Hardware specifics. */ -#define portBYTE_ALIGNMENT 8 /* Could make four, according to manual. */ -#define portSTACK_GROWTH -1 -#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) -#define portNOP() __asm volatile( "NOP" ) +#define portBYTE_ALIGNMENT 8 /* Could make four, according to manual. */ +#define portSTACK_GROWTH -1 +#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) +#define portNOP() __asm volatile ( "NOP" ) /* Save clobbered register, set ITU SWINR (at address 0x872E0), read the value -back to ensure it is set before continuing, then restore the clobbered -register. */ -#define portYIELD() \ - __asm volatile \ - ( \ - "MOV.L #0x872E0, r5 \n\t" \ - "MOV.B #1, [r5] \n\t" \ - "MOV.L [r5], r5 \n\t" \ - ::: "r5" \ + * back to ensure it is set before continuing, then restore the clobbered + * register. */ +#define portYIELD() \ + __asm volatile \ + ( \ + "MOV.L #0x872E0, r5 \n\t" \ + "MOV.B #1, [r5] \n\t" \ + "MOV.L [r5], r5 \n\t" \ + ::: "r5" \ ) -#define portYIELD_FROM_ISR( x ) do { if( x != pdFALSE ) { portYIELD(); } } while( 0 ) +#define portYIELD_FROM_ISR( x ) do { if( x != pdFALSE ) { portYIELD(); } } while( 0 ) /* These macros should not be called directly, but through the -taskENTER_CRITICAL() and taskEXIT_CRITICAL() macros. An extra check is -performed if configASSERT() is defined to ensure an assertion handler does not -inadvertently attempt to lower the IPL when the call to assert was triggered -because the IPL value was found to be above configMAX_SYSCALL_INTERRUPT_PRIORITY -when an ISR safe FreeRTOS API function was executed. ISR safe FreeRTOS API -functions are those that end in FromISR. FreeRTOS maintains a separate -interrupt API to ensure API function and interrupt entry is as fast and as -simple as possible. */ -#define portENABLE_INTERRUPTS() __asm volatile ( "MVTIPL #0" ) + * taskENTER_CRITICAL() and taskEXIT_CRITICAL() macros. An extra check is + * performed if configASSERT() is defined to ensure an assertion handler does not + * inadvertently attempt to lower the IPL when the call to assert was triggered + * because the IPL value was found to be above configMAX_SYSCALL_INTERRUPT_PRIORITY + * when an ISR safe FreeRTOS API function was executed. ISR safe FreeRTOS API + * functions are those that end in FromISR. FreeRTOS maintains a separate + * interrupt API to ensure API function and interrupt entry is as fast and as + * simple as possible. */ +#define portENABLE_INTERRUPTS() __asm volatile ( "MVTIPL #0" ) #ifdef configASSERT - #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() configASSERT( ( ulPortGetIPL() <= configMAX_SYSCALL_INTERRUPT_PRIORITY ) ) - #define portDISABLE_INTERRUPTS() if( ulPortGetIPL() < configMAX_SYSCALL_INTERRUPT_PRIORITY ) __asm volatile ( "MVTIPL %0" ::"i"(configMAX_SYSCALL_INTERRUPT_PRIORITY) ) + #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() configASSERT( ( ulPortGetIPL() <= configMAX_SYSCALL_INTERRUPT_PRIORITY ) ) + #define portDISABLE_INTERRUPTS() if( ulPortGetIPL() < configMAX_SYSCALL_INTERRUPT_PRIORITY ) __asm volatile( "MVTIPL %0" ::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) ) #else - #define portDISABLE_INTERRUPTS() __asm volatile ( "MVTIPL %0" ::"i"(configMAX_SYSCALL_INTERRUPT_PRIORITY) ) + #define portDISABLE_INTERRUPTS() __asm volatile ( "MVTIPL %0" ::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) ) #endif /* Critical nesting counts are stored in the TCB. */ -#define portCRITICAL_NESTING_IN_TCB ( 1 ) +#define portCRITICAL_NESTING_IN_TCB ( 1 ) /* The critical nesting functions defined within tasks.c. */ extern void vTaskEnterCritical( void ); @@ -127,24 +128,26 @@ extern void vTaskExitCritical( void ); #define portEXIT_CRITICAL() vTaskExitCritical() /* As this port allows interrupt nesting... */ -uint32_t ulPortGetIPL( void ) __attribute__((naked)); -void vPortSetIPL( uint32_t ulNewIPL ) __attribute__((naked)); -#define portSET_INTERRUPT_MASK_FROM_ISR() ulPortGetIPL(); portDISABLE_INTERRUPTS() -#define portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus ) vPortSetIPL( uxSavedInterruptStatus ) +uint32_t ulPortGetIPL( void ) __attribute__( ( naked ) ); +void vPortSetIPL( uint32_t ulNewIPL ) __attribute__( ( naked ) ); +#define portSET_INTERRUPT_MASK_FROM_ISR() ulPortGetIPL(); portDISABLE_INTERRUPTS() +#define portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus ) vPortSetIPL( uxSavedInterruptStatus ) /* Tickless idle/low power functionality. */ #if configUSE_TICKLESS_IDLE == 1 #ifndef portSUPPRESS_TICKS_AND_SLEEP extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime ); - #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime ) vPortSuppressTicksAndSleep( xExpectedIdleTime ) + #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime ) vPortSuppressTicksAndSleep( xExpectedIdleTime ) #endif #endif /*-----------------------------------------------------------*/ /* Task function macros as described on the FreeRTOS.org WEB site. */ -#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters ) -#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters ) +#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters ) +#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters ) + +#define portMEMORY_BARRIER() __asm volatile ( "" ::: "memory" ) /* *INDENT-OFF* */ #ifdef __cplusplus diff --git a/Source/portable/GCC/RX200/port.c b/Source/portable/GCC/RX200/port.c index d41ee89b0..0247727ab 100644 --- a/Source/portable/GCC/RX200/port.c +++ b/Source/portable/GCC/RX200/port.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -27,8 +27,8 @@ */ /*----------------------------------------------------------- - * Implementation of functions defined in portable.h for the SH2A port. - *----------------------------------------------------------*/ +* Implementation of functions defined in portable.h for the SH2A port. +*----------------------------------------------------------*/ /* Scheduler includes. */ #include "FreeRTOS.h" @@ -51,17 +51,17 @@ /*-----------------------------------------------------------*/ /* Tasks should start with interrupts enabled and in Supervisor mode, therefore -PSW is set with U and I set, and PM and IPL clear. */ + * PSW is set with U and I set, and PM and IPL clear. */ #define portINITIAL_PSW ( ( StackType_t ) 0x00030000 ) #define portINITIAL_FPSW ( ( StackType_t ) 0x00000100 ) /* These macros allow a critical section to be added around the call to -xTaskIncrementTick(), which is only ever called from interrupts at the kernel -priority - ie a known priority. Therefore these local macros are a slight -optimisation compared to calling the global SET/CLEAR_INTERRUPT_MASK macros, -which would require the old IPL to be read first and stored in a local variable. */ -#define portMASK_INTERRUPTS_FROM_KERNEL_ISR() __asm volatile ( "MVTIPL %0" ::"i"(configMAX_SYSCALL_INTERRUPT_PRIORITY) ) -#define portUNMASK_INTERRUPTS_FROM_KERNEL_ISR() __asm volatile ( "MVTIPL %0" ::"i"(configKERNEL_INTERRUPT_PRIORITY) ) + * xTaskIncrementTick(), which is only ever called from interrupts at the kernel + * priority - ie a known priority. Therefore these local macros are a slight + * optimisation compared to calling the global SET/CLEAR_INTERRUPT_MASK macros, + * which would require the old IPL to be read first and stored in a local variable. */ +#define portMASK_INTERRUPTS_FROM_KERNEL_ISR() __asm volatile ( "MVTIPL %0" ::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) ) +#define portUNMASK_INTERRUPTS_FROM_KERNEL_ISR() __asm volatile ( "MVTIPL %0" ::"i" ( configKERNEL_INTERRUPT_PRIORITY ) ) /*-----------------------------------------------------------*/ @@ -69,7 +69,7 @@ which would require the old IPL to be read first and stored in a local variable. * Function to start the first task executing - written in asm code as direct * access to registers is required. */ -static void prvStartFirstTask( void ) __attribute__((naked)); +static void prvStartFirstTask( void ) __attribute__( ( naked ) ); /* @@ -105,14 +105,16 @@ static void prvStartFirstTask( void ) __attribute__((naked)); /*-----------------------------------------------------------*/ -extern void *pxCurrentTCB; +extern void * pxCurrentTCB; /*-----------------------------------------------------------*/ /* * See header file for description. */ -StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters ) +StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, + TaskFunction_t pxCode, + void * pvParameters ) { /* R0 is not included as it is the stack pointer. */ @@ -123,8 +125,8 @@ StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t px *pxTopOfStack = ( StackType_t ) pxCode; /* When debugging it can be useful if every register is set to a known - value. Otherwise code space can be saved by just setting the registers - that need to be set. */ + * value. Otherwise code space can be saved by just setting the registers + * that need to be set. */ #ifdef USE_FULL_REGISTER_INITIALISATION { pxTopOfStack--; @@ -157,11 +159,11 @@ StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t px *pxTopOfStack = 0x22222222; pxTopOfStack--; } - #else + #else /* ifdef USE_FULL_REGISTER_INITIALISATION */ { pxTopOfStack -= 15; } - #endif + #endif /* ifdef USE_FULL_REGISTER_INITIALISATION */ *pxTopOfStack = ( StackType_t ) pvParameters; /* R1 */ pxTopOfStack--; @@ -185,14 +187,14 @@ StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t px BaseType_t xPortStartScheduler( void ) { -extern void vApplicationSetupTimerInterrupt( void ); + extern void vApplicationSetupTimerInterrupt( void ); /* Use pxCurrentTCB just so it does not get optimised away. */ if( pxCurrentTCB != NULL ) { /* Call an application function to set up the timer that will generate the - tick interrupt. This way the application can decide which peripheral to - use. A demo application is provided to show a suitable example. */ + * tick interrupt. This way the application can decide which peripheral to + * use. A demo application is provided to show a suitable example. */ vApplicationSetupTimerInterrupt(); /* Enable the software interrupt. */ @@ -216,7 +218,7 @@ extern void vApplicationSetupTimerInterrupt( void ); void vPortEndScheduler( void ) { /* Not implemented in ports where there is nothing to return to. - Artificially force an assert. */ + * Artificially force an assert. */ configASSERT( pxCurrentTCB == NULL ); } /*-----------------------------------------------------------*/ @@ -225,19 +227,22 @@ static void prvStartFirstTask( void ) { __asm volatile ( + /* When starting the scheduler there is nothing that needs moving to the - interrupt stack because the function is not called from an interrupt. - Just ensure the current stack is the user stack. */ + * interrupt stack because the function is not called from an interrupt. + * Just ensure the current stack is the user stack. */ "SETPSW U \n" \ + /* Obtain the location of the stack associated with which ever task - pxCurrentTCB is currently pointing to. */ + * pxCurrentTCB is currently pointing to. */ "MOV.L #_pxCurrentTCB, R15 \n" \ "MOV.L [R15], R15 \n" \ "MOV.L [R15], R0 \n" \ + /* Restore the registers from the stack of the task pointed to by - pxCurrentTCB. */ + * pxCurrentTCB. */ "POP R15 \n" \ /* Accumulator low 32 bits. */ @@ -285,10 +290,11 @@ void vSoftwareInterruptISR( void ) /* Re-enable interrupts. */ "SETPSW I \n" \ - /* Move the data that was automatically pushed onto the interrupt stack when - the interrupt occurred from the interrupt stack to the user stack. - R15 is saved before it is clobbered. */ + /* Move the data that was automatically pushed onto the interrupt stack when + * the interrupt occurred from the interrupt stack to the user stack. + * + * R15 is saved before it is clobbered. */ "PUSH.L R15 \n" \ /* Read the user stack pointer. */ @@ -335,8 +341,9 @@ void vSoftwareInterruptISR( void ) "MOV.L [ R15 ], R15 \n" \ "MOV.L R0, [ R15 ] \n" \ + /* Ensure the interrupt mask is set to the syscall priority while the kernel - structures are being accessed. */ + * structures are being accessed. */ "MVTIPL %0 \n" \ /* Select the next task to run. */ @@ -345,14 +352,16 @@ void vSoftwareInterruptISR( void ) /* Reset the interrupt mask as no more data structure access is required. */ "MVTIPL %1 \n" \ + /* Load the stack pointer of the task that is now selected as the Running - state task from its TCB. */ + * state task from its TCB. */ "MOV.L #_pxCurrentTCB,R15 \n" \ "MOV.L [ R15 ], R15 \n" \ "MOV.L [ R15 ], R0 \n" \ + /* Restore the context of the new task. The PSW (Program Status Word) and - PC will be popped by the RTE instruction. */ + * PC will be popped by the RTE instruction. */ "POP R15 \n" \ /* Accumulator low 32 bits. */ @@ -383,7 +392,7 @@ void vSoftwareInterruptISR( void ) "RTE \n" \ "NOP \n" \ "NOP " - :: "i"(configMAX_SYSCALL_INTERRUPT_PRIORITY), "i"(configKERNEL_INTERRUPT_PRIORITY) + ::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ), "i" ( configKERNEL_INTERRUPT_PRIORITY ) ); } /*-----------------------------------------------------------*/ @@ -391,10 +400,10 @@ void vSoftwareInterruptISR( void ) void vTickISR( void ) { /* Re-enabled interrupts. */ - __asm volatile( "SETPSW I" ); + __asm volatile ( "SETPSW I" ); /* Increment the tick, and perform any processing the new tick value - necessitates. Ensure IPL is at the max syscall value first. */ + * necessitates. Ensure IPL is at the max syscall value first. */ portMASK_INTERRUPTS_FROM_KERNEL_ISR(); { if( xTaskIncrementTick() != pdFALSE ) @@ -432,5 +441,5 @@ void vPortSetIPL( uint32_t ulNewIPL ) "MVTC R5, PSW \n" \ "POP R5 \n" \ "RTS " - ); + ); } diff --git a/Source/portable/GCC/RX200/portmacro.h b/Source/portable/GCC/RX200/portmacro.h index 726882ac8..98c633458 100644 --- a/Source/portable/GCC/RX200/portmacro.h +++ b/Source/portable/GCC/RX200/portmacro.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -49,79 +49,79 @@ /* When the FIT configurator or the Smart Configurator is used, platform.h has to be * used. */ #ifndef configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H - #define configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H 0 + #define configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H 0 #endif /* Type definitions - these are a bit legacy and not really used now, other than -portSTACK_TYPE and portBASE_TYPE. */ -#define portCHAR char -#define portFLOAT float -#define portDOUBLE double -#define portLONG long -#define portSHORT short -#define portSTACK_TYPE uint32_t -#define portBASE_TYPE long - -typedef portSTACK_TYPE StackType_t; -typedef long BaseType_t; -typedef unsigned long UBaseType_t; - -#if( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS ) - typedef uint16_t TickType_t; - #define portMAX_DELAY ( TickType_t ) 0xffff + * portSTACK_TYPE and portBASE_TYPE. */ +#define portCHAR char +#define portFLOAT float +#define portDOUBLE double +#define portLONG long +#define portSHORT short +#define portSTACK_TYPE uint32_t +#define portBASE_TYPE long + +typedef portSTACK_TYPE StackType_t; +typedef long BaseType_t; +typedef unsigned long UBaseType_t; + +#if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS ) + typedef uint16_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffff #elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS ) - typedef uint32_t TickType_t; - #define portMAX_DELAY ( TickType_t ) 0xffffffffUL + typedef uint32_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffffffffUL - /* 32-bit tick type on a 32-bit architecture, so reads of the tick count do - not need to be guarded with a critical section. */ - #define portTICK_TYPE_IS_ATOMIC 1 +/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do + * not need to be guarded with a critical section. */ + #define portTICK_TYPE_IS_ATOMIC 1 #else #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width. #endif /*-----------------------------------------------------------*/ /* Hardware specifics. */ -#define portBYTE_ALIGNMENT 8 /* Could make four, according to manual. */ -#define portSTACK_GROWTH -1 -#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) -#define portNOP() __asm volatile( "NOP" ) +#define portBYTE_ALIGNMENT 8 /* Could make four, according to manual. */ +#define portSTACK_GROWTH -1 +#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) +#define portNOP() __asm volatile ( "NOP" ) /* Yield equivalent to "*portITU_SWINTR = 0x01; ( void ) *portITU_SWINTR;" -where portITU_SWINTR is the location of the software interrupt register -(0x000872E0). Don't rely on the assembler to select a register, so instead -save and restore clobbered registers manually. */ -#define portYIELD() \ - __asm volatile \ - ( \ - "PUSH.L R10 \n" \ - "MOV.L #0x872E0, R10 \n" \ - "MOV.B #0x1, [R10] \n" \ - "MOV.L [R10], R10 \n" \ - "POP R10 \n" \ + * where portITU_SWINTR is the location of the software interrupt register + * (0x000872E0). Don't rely on the assembler to select a register, so instead + * save and restore clobbered registers manually. */ +#define portYIELD() \ + __asm volatile \ + ( \ + "PUSH.L R10 \n" \ + "MOV.L #0x872E0, R10 \n" \ + "MOV.B #0x1, [R10] \n" \ + "MOV.L [R10], R10 \n" \ + "POP R10 \n" \ ) -#define portYIELD_FROM_ISR( x ) if( x != pdFALSE ) portYIELD() +#define portYIELD_FROM_ISR( x ) if( x != pdFALSE ) portYIELD( ) /* These macros should not be called directly, but through the -taskENTER_CRITICAL() and taskEXIT_CRITICAL() macros. An extra check is -performed if configASSERT() is defined to ensure an assertion handler does not -inadvertently attempt to lower the IPL when the call to assert was triggered -because the IPL value was found to be above configMAX_SYSCALL_INTERRUPT_PRIORITY -when an ISR safe FreeRTOS API function was executed. ISR safe FreeRTOS API -functions are those that end in FromISR. FreeRTOS maintains a separate -interrupt API to ensure API function and interrupt entry is as fast and as -simple as possible. */ -#define portENABLE_INTERRUPTS() __asm volatile ( "MVTIPL #0" ) + * taskENTER_CRITICAL() and taskEXIT_CRITICAL() macros. An extra check is + * performed if configASSERT() is defined to ensure an assertion handler does not + * inadvertently attempt to lower the IPL when the call to assert was triggered + * because the IPL value was found to be above configMAX_SYSCALL_INTERRUPT_PRIORITY + * when an ISR safe FreeRTOS API function was executed. ISR safe FreeRTOS API + * functions are those that end in FromISR. FreeRTOS maintains a separate + * interrupt API to ensure API function and interrupt entry is as fast and as + * simple as possible. */ +#define portENABLE_INTERRUPTS() __asm volatile ( "MVTIPL #0" ) #ifdef configASSERT - #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() configASSERT( ( ulPortGetIPL() <= configMAX_SYSCALL_INTERRUPT_PRIORITY ) ) - #define portDISABLE_INTERRUPTS() if( ulPortGetIPL() < configMAX_SYSCALL_INTERRUPT_PRIORITY ) __asm volatile ( "MVTIPL %0" ::"i"(configMAX_SYSCALL_INTERRUPT_PRIORITY) ) + #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() configASSERT( ( ulPortGetIPL() <= configMAX_SYSCALL_INTERRUPT_PRIORITY ) ) + #define portDISABLE_INTERRUPTS() if( ulPortGetIPL() < configMAX_SYSCALL_INTERRUPT_PRIORITY ) __asm volatile( "MVTIPL %0" ::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) ) #else - #define portDISABLE_INTERRUPTS() __asm volatile ( "MVTIPL %0" ::"i"(configMAX_SYSCALL_INTERRUPT_PRIORITY) ) + #define portDISABLE_INTERRUPTS() __asm volatile ( "MVTIPL %0" ::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) ) #endif /* Critical nesting counts are stored in the TCB. */ -#define portCRITICAL_NESTING_IN_TCB ( 1 ) +#define portCRITICAL_NESTING_IN_TCB ( 1 ) /* The critical nesting functions defined within tasks.c. */ extern void vTaskEnterCritical( void ); @@ -130,16 +130,18 @@ extern void vTaskExitCritical( void ); #define portEXIT_CRITICAL() vTaskExitCritical() /* As this port allows interrupt nesting... */ -uint32_t ulPortGetIPL( void ) __attribute__((naked)); -void vPortSetIPL( uint32_t ulNewIPL ) __attribute__((naked)); -#define portSET_INTERRUPT_MASK_FROM_ISR() ulPortGetIPL(); portDISABLE_INTERRUPTS() -#define portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus ) vPortSetIPL( uxSavedInterruptStatus ) +uint32_t ulPortGetIPL( void ) __attribute__( ( naked ) ); +void vPortSetIPL( uint32_t ulNewIPL ) __attribute__( ( naked ) ); +#define portSET_INTERRUPT_MASK_FROM_ISR() ulPortGetIPL(); portDISABLE_INTERRUPTS() +#define portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus ) vPortSetIPL( uxSavedInterruptStatus ) /*-----------------------------------------------------------*/ /* Task function macros as described on the FreeRTOS.org WEB site. */ -#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters ) -#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters ) +#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters ) +#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters ) + +#define portMEMORY_BARRIER() __asm volatile ( "" ::: "memory" ) /* *INDENT-OFF* */ #ifdef __cplusplus diff --git a/Source/portable/GCC/RX600/port.c b/Source/portable/GCC/RX600/port.c index a0c85cdb1..fdaf34d8c 100644 --- a/Source/portable/GCC/RX600/port.c +++ b/Source/portable/GCC/RX600/port.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -27,8 +27,8 @@ */ /*----------------------------------------------------------- - * Implementation of functions defined in portable.h for the SH2A port. - *----------------------------------------------------------*/ +* Implementation of functions defined in portable.h for the SH2A port. +*----------------------------------------------------------*/ /* Scheduler includes. */ #include "FreeRTOS.h" @@ -52,17 +52,17 @@ /*-----------------------------------------------------------*/ /* Tasks should start with interrupts enabled and in Supervisor mode, therefore -PSW is set with U and I set, and PM and IPL clear. */ + * PSW is set with U and I set, and PM and IPL clear. */ #define portINITIAL_PSW ( ( StackType_t ) 0x00030000 ) #define portINITIAL_FPSW ( ( StackType_t ) 0x00000100 ) /* These macros allow a critical section to be added around the call to -xTaskIncrementTick(), which is only ever called from interrupts at the kernel -priority - ie a known priority. Therefore these local macros are a slight -optimisation compared to calling the global SET/CLEAR_INTERRUPT_MASK macros, -which would require the old IPL to be read first and stored in a local variable. */ -#define portDISABLE_INTERRUPTS_FROM_KERNEL_ISR() __asm volatile ( "MVTIPL %0" ::"i"(configMAX_SYSCALL_INTERRUPT_PRIORITY) ) -#define portENABLE_INTERRUPTS_FROM_KERNEL_ISR() __asm volatile ( "MVTIPL %0" ::"i"(configKERNEL_INTERRUPT_PRIORITY) ) + * xTaskIncrementTick(), which is only ever called from interrupts at the kernel + * priority - ie a known priority. Therefore these local macros are a slight + * optimisation compared to calling the global SET/CLEAR_INTERRUPT_MASK macros, + * which would require the old IPL to be read first and stored in a local variable. */ +#define portDISABLE_INTERRUPTS_FROM_KERNEL_ISR() __asm volatile ( "MVTIPL %0" ::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) ) +#define portENABLE_INTERRUPTS_FROM_KERNEL_ISR() __asm volatile ( "MVTIPL %0" ::"i" ( configKERNEL_INTERRUPT_PRIORITY ) ) /*-----------------------------------------------------------*/ @@ -70,7 +70,8 @@ which would require the old IPL to be read first and stored in a local variable. * Function to start the first task executing - written in asm code as direct * access to registers is required. */ -static void prvStartFirstTask( void ) __attribute__((naked)); +static void prvStartFirstTask( void ) __attribute__( ( naked ) ); + /* * Software interrupt handler. Performs the actual context switch (saving and * restoring of registers). Written in asm code as direct register access is @@ -104,14 +105,16 @@ static void prvStartFirstTask( void ) __attribute__((naked)); /*-----------------------------------------------------------*/ -extern void *pxCurrentTCB; +extern void * pxCurrentTCB; /*-----------------------------------------------------------*/ /* * See header file for description. */ -StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters ) +StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, + TaskFunction_t pxCode, + void * pvParameters ) { /* R0 is not included as it is the stack pointer. */ @@ -122,8 +125,8 @@ StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t px *pxTopOfStack = ( StackType_t ) pxCode; /* When debugging it can be useful if every register is set to a known - value. Otherwise code space can be saved by just setting the registers - that need to be set. */ + * value. Otherwise code space can be saved by just setting the registers + * that need to be set. */ #ifdef USE_FULL_REGISTER_INITIALISATION { pxTopOfStack--; @@ -156,11 +159,11 @@ StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t px *pxTopOfStack = 0x22222222; pxTopOfStack--; } - #else + #else /* ifdef USE_FULL_REGISTER_INITIALISATION */ { pxTopOfStack -= 15; } - #endif + #endif /* ifdef USE_FULL_REGISTER_INITIALISATION */ *pxTopOfStack = ( StackType_t ) pvParameters; /* R1 */ pxTopOfStack--; @@ -176,14 +179,14 @@ StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t px BaseType_t xPortStartScheduler( void ) { -extern void vApplicationSetupTimerInterrupt( void ); + extern void vApplicationSetupTimerInterrupt( void ); /* Use pxCurrentTCB just so it does not get optimised away. */ if( pxCurrentTCB != NULL ) { /* Call an application function to set up the timer that will generate the - tick interrupt. This way the application can decide which peripheral to - use. A demo application is provided to show a suitable example. */ + * tick interrupt. This way the application can decide which peripheral to + * use. A demo application is provided to show a suitable example. */ vApplicationSetupTimerInterrupt(); /* Enable the software interrupt. */ @@ -207,7 +210,7 @@ extern void vApplicationSetupTimerInterrupt( void ); void vPortEndScheduler( void ) { /* Not implemented in ports where there is nothing to return to. - Artificially force an assert. */ + * Artificially force an assert. */ configASSERT( pxCurrentTCB == NULL ); } /*-----------------------------------------------------------*/ @@ -216,19 +219,22 @@ static void prvStartFirstTask( void ) { __asm volatile ( + /* When starting the scheduler there is nothing that needs moving to the - interrupt stack because the function is not called from an interrupt. - Just ensure the current stack is the user stack. */ + * interrupt stack because the function is not called from an interrupt. + * Just ensure the current stack is the user stack. */ "SETPSW U \n" \ + /* Obtain the location of the stack associated with which ever task - pxCurrentTCB is currently pointing to. */ + * pxCurrentTCB is currently pointing to. */ "MOV.L #_pxCurrentTCB, R15 \n" \ "MOV.L [R15], R15 \n" \ "MOV.L [R15], R0 \n" \ + /* Restore the registers from the stack of the task pointed to by - pxCurrentTCB. */ + * pxCurrentTCB. */ "POP R15 \n" \ /* Accumulator low 32 bits. */ @@ -260,10 +266,11 @@ void vSoftwareInterruptISR( void ) /* Re-enable interrupts. */ "SETPSW I \n" \ - /* Move the data that was automatically pushed onto the interrupt stack when - the interrupt occurred from the interrupt stack to the user stack. - R15 is saved before it is clobbered. */ + /* Move the data that was automatically pushed onto the interrupt stack when + * the interrupt occurred from the interrupt stack to the user stack. + * + * R15 is saved before it is clobbered. */ "PUSH.L R15 \n" \ /* Read the user stack pointer. */ @@ -305,8 +312,9 @@ void vSoftwareInterruptISR( void ) "MOV.L [ R15 ], R15 \n" \ "MOV.L R0, [ R15 ] \n" \ + /* Ensure the interrupt mask is set to the syscall priority while the kernel - structures are being accessed. */ + * structures are being accessed. */ "MVTIPL %0 \n" \ /* Select the next task to run. */ @@ -315,14 +323,16 @@ void vSoftwareInterruptISR( void ) /* Reset the interrupt mask as no more data structure access is required. */ "MVTIPL %1 \n" \ + /* Load the stack pointer of the task that is now selected as the Running - state task from its TCB. */ + * state task from its TCB. */ "MOV.L #_pxCurrentTCB,R15 \n" \ "MOV.L [ R15 ], R15 \n" \ "MOV.L [ R15 ], R0 \n" \ + /* Restore the context of the new task. The PSW (Program Status Word) and - PC will be popped by the RTE instruction. */ + * PC will be popped by the RTE instruction. */ "POP R15 \n" \ "MVTACLO R15 \n" \ "POP R15 \n" \ @@ -333,7 +343,7 @@ void vSoftwareInterruptISR( void ) "RTE \n" \ "NOP \n" \ "NOP " - :: "i"(configMAX_SYSCALL_INTERRUPT_PRIORITY), "i"(configKERNEL_INTERRUPT_PRIORITY) + ::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ), "i" ( configKERNEL_INTERRUPT_PRIORITY ) ); } /*-----------------------------------------------------------*/ @@ -341,10 +351,10 @@ void vSoftwareInterruptISR( void ) void vTickISR( void ) { /* Re-enabled interrupts. */ - __asm volatile( "SETPSW I" ); + __asm volatile ( "SETPSW I" ); /* Increment the tick, and perform any processing the new tick value - necessitates. Ensure IPL is at the max syscall value first. */ + * necessitates. Ensure IPL is at the max syscall value first. */ portDISABLE_INTERRUPTS_FROM_KERNEL_ISR(); { if( xTaskIncrementTick() != pdFALSE ) @@ -385,5 +395,5 @@ void vPortSetIPL( uint32_t ulNewIPL ) "MVTC R5, PSW \n" \ "POP R5 \n" \ "RTS " - ); + ); } diff --git a/Source/portable/GCC/RX600/portmacro.h b/Source/portable/GCC/RX600/portmacro.h index 344afea1e..acb2ff542 100644 --- a/Source/portable/GCC/RX600/portmacro.h +++ b/Source/portable/GCC/RX600/portmacro.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -49,79 +49,79 @@ /* When the FIT configurator or the Smart Configurator is used, platform.h has to be * used. */ #ifndef configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H - #define configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H 0 + #define configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H 0 #endif /* Type definitions - these are a bit legacy and not really used now, other than -portSTACK_TYPE and portBASE_TYPE. */ -#define portCHAR char -#define portFLOAT float -#define portDOUBLE double -#define portLONG long -#define portSHORT short -#define portSTACK_TYPE uint32_t -#define portBASE_TYPE long - -typedef portSTACK_TYPE StackType_t; -typedef long BaseType_t; -typedef unsigned long UBaseType_t; - -#if( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS ) - typedef uint16_t TickType_t; - #define portMAX_DELAY ( TickType_t ) 0xffff + * portSTACK_TYPE and portBASE_TYPE. */ +#define portCHAR char +#define portFLOAT float +#define portDOUBLE double +#define portLONG long +#define portSHORT short +#define portSTACK_TYPE uint32_t +#define portBASE_TYPE long + +typedef portSTACK_TYPE StackType_t; +typedef long BaseType_t; +typedef unsigned long UBaseType_t; + +#if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS ) + typedef uint16_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffff #elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS ) - typedef uint32_t TickType_t; - #define portMAX_DELAY ( TickType_t ) 0xffffffffUL + typedef uint32_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffffffffUL - /* 32-bit tick type on a 32-bit architecture, so reads of the tick count do - not need to be guarded with a critical section. */ - #define portTICK_TYPE_IS_ATOMIC 1 +/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do + * not need to be guarded with a critical section. */ + #define portTICK_TYPE_IS_ATOMIC 1 #else #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width. #endif /*-----------------------------------------------------------*/ /* Hardware specifics. */ -#define portBYTE_ALIGNMENT 8 /* Could make four, according to manual. */ -#define portSTACK_GROWTH -1 -#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) -#define portNOP() __asm volatile( "NOP" ) +#define portBYTE_ALIGNMENT 8 /* Could make four, according to manual. */ +#define portSTACK_GROWTH -1 +#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) +#define portNOP() __asm volatile ( "NOP" ) /* Yield equivalent to "*portITU_SWINTR = 0x01; ( void ) *portITU_SWINTR;" -where portITU_SWINTR is the location of the software interrupt register -(0x000872E0). Don't rely on the assembler to select a register, so instead -save and restore clobbered registers manually. */ -#define portYIELD() \ - __asm volatile \ - ( \ - "PUSH.L R10 \n" \ - "MOV.L #0x872E0, R10 \n" \ - "MOV.B #0x1, [R10] \n" \ - "MOV.L [R10], R10 \n" \ - "POP R10 \n" \ + * where portITU_SWINTR is the location of the software interrupt register + * (0x000872E0). Don't rely on the assembler to select a register, so instead + * save and restore clobbered registers manually. */ +#define portYIELD() \ + __asm volatile \ + ( \ + "PUSH.L R10 \n" \ + "MOV.L #0x872E0, R10 \n" \ + "MOV.B #0x1, [R10] \n" \ + "MOV.L [R10], R10 \n" \ + "POP R10 \n" \ ) -#define portYIELD_FROM_ISR( x ) do { if( x != pdFALSE ) portYIELD(); } while( 0 ) +#define portYIELD_FROM_ISR( x ) do { if( x != pdFALSE ) portYIELD( ); } while( 0 ) /* These macros should not be called directly, but through the -taskENTER_CRITICAL() and taskEXIT_CRITICAL() macros. An extra check is -performed if configASSERT() is defined to ensure an assertion handler does not -inadvertently attempt to lower the IPL when the call to assert was triggered -because the IPL value was found to be above configMAX_SYSCALL_INTERRUPT_PRIORITY -when an ISR safe FreeRTOS API function was executed. ISR safe FreeRTOS API -functions are those that end in FromISR. FreeRTOS maintains a separate -interrupt API to ensure API function and interrupt entry is as fast and as -simple as possible. */ -#define portENABLE_INTERRUPTS() __asm volatile ( "MVTIPL #0" ) + * taskENTER_CRITICAL() and taskEXIT_CRITICAL() macros. An extra check is + * performed if configASSERT() is defined to ensure an assertion handler does not + * inadvertently attempt to lower the IPL when the call to assert was triggered + * because the IPL value was found to be above configMAX_SYSCALL_INTERRUPT_PRIORITY + * when an ISR safe FreeRTOS API function was executed. ISR safe FreeRTOS API + * functions are those that end in FromISR. FreeRTOS maintains a separate + * interrupt API to ensure API function and interrupt entry is as fast and as + * simple as possible. */ +#define portENABLE_INTERRUPTS() __asm volatile ( "MVTIPL #0" ) #ifdef configASSERT - #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() configASSERT( ( ulPortGetIPL() <= configMAX_SYSCALL_INTERRUPT_PRIORITY ) ) - #define portDISABLE_INTERRUPTS() if( ulPortGetIPL() < configMAX_SYSCALL_INTERRUPT_PRIORITY ) __asm volatile ( "MVTIPL %0" ::"i"(configMAX_SYSCALL_INTERRUPT_PRIORITY) ) + #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() configASSERT( ( ulPortGetIPL() <= configMAX_SYSCALL_INTERRUPT_PRIORITY ) ) + #define portDISABLE_INTERRUPTS() if( ulPortGetIPL() < configMAX_SYSCALL_INTERRUPT_PRIORITY ) __asm volatile( "MVTIPL %0" ::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) ) #else - #define portDISABLE_INTERRUPTS() __asm volatile ( "MVTIPL %0" ::"i"(configMAX_SYSCALL_INTERRUPT_PRIORITY) ) + #define portDISABLE_INTERRUPTS() __asm volatile ( "MVTIPL %0" ::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) ) #endif /* Critical nesting counts are stored in the TCB. */ -#define portCRITICAL_NESTING_IN_TCB ( 1 ) +#define portCRITICAL_NESTING_IN_TCB ( 1 ) /* The critical nesting functions defined within tasks.c. */ extern void vTaskEnterCritical( void ); @@ -130,16 +130,18 @@ extern void vTaskExitCritical( void ); #define portEXIT_CRITICAL() vTaskExitCritical() /* As this port allows interrupt nesting... */ -uint32_t ulPortGetIPL( void ) __attribute__((naked)); -void vPortSetIPL( uint32_t ulNewIPL ) __attribute__((naked)); -#define portSET_INTERRUPT_MASK_FROM_ISR() ulPortGetIPL(); portDISABLE_INTERRUPTS() -#define portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus ) vPortSetIPL( uxSavedInterruptStatus ) +uint32_t ulPortGetIPL( void ) __attribute__( ( naked ) ); +void vPortSetIPL( uint32_t ulNewIPL ) __attribute__( ( naked ) ); +#define portSET_INTERRUPT_MASK_FROM_ISR() ulPortGetIPL(); portDISABLE_INTERRUPTS() +#define portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus ) vPortSetIPL( uxSavedInterruptStatus ) /*-----------------------------------------------------------*/ /* Task function macros as described on the FreeRTOS.org WEB site. */ -#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters ) -#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters ) +#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters ) +#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters ) + +#define portMEMORY_BARRIER() __asm volatile ( "" ::: "memory" ) /* *INDENT-OFF* */ #ifdef __cplusplus diff --git a/Source/portable/GCC/RX600v2/port.c b/Source/portable/GCC/RX600v2/port.c index c6a00d2a0..fbbf96958 100644 --- a/Source/portable/GCC/RX600v2/port.c +++ b/Source/portable/GCC/RX600v2/port.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -27,8 +27,8 @@ */ /*----------------------------------------------------------- - * Implementation of functions defined in portable.h for the SH2A port. - *----------------------------------------------------------*/ +* Implementation of functions defined in portable.h for the SH2A port. +*----------------------------------------------------------*/ /* Scheduler includes. */ #include "FreeRTOS.h" @@ -51,17 +51,17 @@ /*-----------------------------------------------------------*/ /* Tasks should start with interrupts enabled and in Supervisor mode, therefore -PSW is set with U and I set, and PM and IPL clear. */ + * PSW is set with U and I set, and PM and IPL clear. */ #define portINITIAL_PSW ( ( StackType_t ) 0x00030000 ) #define portINITIAL_FPSW ( ( StackType_t ) 0x00000100 ) /* These macros allow a critical section to be added around the call to -xTaskIncrementTick(), which is only ever called from interrupts at the kernel -priority - ie a known priority. Therefore these local macros are a slight -optimisation compared to calling the global SET/CLEAR_INTERRUPT_MASK macros, -which would require the old IPL to be read first and stored in a local variable. */ -#define portMASK_INTERRUPTS_FROM_KERNEL_ISR() __asm volatile ( "MVTIPL %0" ::"i"(configMAX_SYSCALL_INTERRUPT_PRIORITY) ) -#define portUNMASK_INTERRUPTS_FROM_KERNEL_ISR() __asm volatile ( "MVTIPL %0" ::"i"(configKERNEL_INTERRUPT_PRIORITY) ) + * xTaskIncrementTick(), which is only ever called from interrupts at the kernel + * priority - ie a known priority. Therefore these local macros are a slight + * optimisation compared to calling the global SET/CLEAR_INTERRUPT_MASK macros, + * which would require the old IPL to be read first and stored in a local variable. */ +#define portMASK_INTERRUPTS_FROM_KERNEL_ISR() __asm volatile ( "MVTIPL %0" ::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) ) +#define portUNMASK_INTERRUPTS_FROM_KERNEL_ISR() __asm volatile ( "MVTIPL %0" ::"i" ( configKERNEL_INTERRUPT_PRIORITY ) ) /*-----------------------------------------------------------*/ @@ -69,7 +69,7 @@ which would require the old IPL to be read first and stored in a local variable. * Function to start the first task executing - written in asm code as direct * access to registers is required. */ -static void prvStartFirstTask( void ) __attribute__((naked)); +static void prvStartFirstTask( void ) __attribute__( ( naked ) ); /* * Software interrupt handler. Performs the actual context switch (saving and @@ -77,10 +77,10 @@ static void prvStartFirstTask( void ) __attribute__((naked)); * required. */ #if ( configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H == 1 ) -R_BSP_PRAGMA_INTERRUPT( vSoftwareInterruptISR, VECT( ICU, SWINT ) ) -R_BSP_ATTRIB_INTERRUPT void vSoftwareInterruptISR( void ) __attribute__( ( naked ) ); + R_BSP_PRAGMA_INTERRUPT( vSoftwareInterruptISR, VECT( ICU, SWINT ) ) + R_BSP_ATTRIB_INTERRUPT void vSoftwareInterruptISR( void ) __attribute__( ( naked ) ); #else /* configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H */ -void vSoftwareInterruptISR( void ) __attribute__((naked)); + void vSoftwareInterruptISR( void ) __attribute__( ( naked ) ); #endif /* configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H */ /* @@ -99,14 +99,16 @@ void vSoftwareInterruptISR( void ) __attribute__((naked)); #endif /* configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H */ /*-----------------------------------------------------------*/ -extern void *pxCurrentTCB; +extern void * pxCurrentTCB; /*-----------------------------------------------------------*/ /* * See header file for description. */ -StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters ) +StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, + TaskFunction_t pxCode, + void * pvParameters ) { /* R0 is not included as it is the stack pointer. */ @@ -117,8 +119,8 @@ StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t px *pxTopOfStack = ( StackType_t ) pxCode; /* When debugging it can be useful if every register is set to a known - value. Otherwise code space can be saved by just setting the registers - that need to be set. */ + * value. Otherwise code space can be saved by just setting the registers + * that need to be set. */ #ifdef USE_FULL_REGISTER_INITIALISATION { pxTopOfStack--; @@ -151,11 +153,11 @@ StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t px *pxTopOfStack = 0x22222222; pxTopOfStack--; } - #else + #else /* ifdef USE_FULL_REGISTER_INITIALISATION */ { pxTopOfStack -= 15; } - #endif + #endif /* ifdef USE_FULL_REGISTER_INITIALISATION */ *pxTopOfStack = ( StackType_t ) pvParameters; /* R1 */ pxTopOfStack--; @@ -179,14 +181,14 @@ StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t px BaseType_t xPortStartScheduler( void ) { -extern void vApplicationSetupTimerInterrupt( void ); + extern void vApplicationSetupTimerInterrupt( void ); /* Use pxCurrentTCB just so it does not get optimised away. */ if( pxCurrentTCB != NULL ) { /* Call an application function to set up the timer that will generate the - tick interrupt. This way the application can decide which peripheral to - use. A demo application is provided to show a suitable example. */ + * tick interrupt. This way the application can decide which peripheral to + * use. A demo application is provided to show a suitable example. */ vApplicationSetupTimerInterrupt(); /* Enable the software interrupt. */ @@ -210,7 +212,7 @@ extern void vApplicationSetupTimerInterrupt( void ); void vPortEndScheduler( void ) { /* Not implemented in ports where there is nothing to return to. - Artificially force an assert. */ + * Artificially force an assert. */ configASSERT( pxCurrentTCB == NULL ); } /*-----------------------------------------------------------*/ @@ -219,19 +221,22 @@ static void prvStartFirstTask( void ) { __asm volatile ( + /* When starting the scheduler there is nothing that needs moving to the - interrupt stack because the function is not called from an interrupt. - Just ensure the current stack is the user stack. */ + * interrupt stack because the function is not called from an interrupt. + * Just ensure the current stack is the user stack. */ "SETPSW U \n" \ + /* Obtain the location of the stack associated with which ever task - pxCurrentTCB is currently pointing to. */ + * pxCurrentTCB is currently pointing to. */ "MOV.L #_pxCurrentTCB, R15 \n" \ "MOV.L [R15], R15 \n" \ "MOV.L [R15], R0 \n" \ + /* Restore the registers from the stack of the task pointed to by - pxCurrentTCB. */ + * pxCurrentTCB. */ "POP R15 \n" \ /* Accumulator low 32 bits. */ @@ -279,10 +284,11 @@ void vSoftwareInterruptISR( void ) /* Re-enable interrupts. */ "SETPSW I \n" \ - /* Move the data that was automatically pushed onto the interrupt stack when - the interrupt occurred from the interrupt stack to the user stack. - R15 is saved before it is clobbered. */ + /* Move the data that was automatically pushed onto the interrupt stack when + * the interrupt occurred from the interrupt stack to the user stack. + * + * R15 is saved before it is clobbered. */ "PUSH.L R15 \n" \ /* Read the user stack pointer. */ @@ -329,8 +335,9 @@ void vSoftwareInterruptISR( void ) "MOV.L [ R15 ], R15 \n" \ "MOV.L R0, [ R15 ] \n" \ + /* Ensure the interrupt mask is set to the syscall priority while the kernel - structures are being accessed. */ + * structures are being accessed. */ "MVTIPL %0 \n" \ /* Select the next task to run. */ @@ -339,14 +346,16 @@ void vSoftwareInterruptISR( void ) /* Reset the interrupt mask as no more data structure access is required. */ "MVTIPL %1 \n" \ + /* Load the stack pointer of the task that is now selected as the Running - state task from its TCB. */ + * state task from its TCB. */ "MOV.L #_pxCurrentTCB,R15 \n" \ "MOV.L [ R15 ], R15 \n" \ "MOV.L [ R15 ], R0 \n" \ + /* Restore the context of the new task. The PSW (Program Status Word) and - PC will be popped by the RTE instruction. */ + * PC will be popped by the RTE instruction. */ "POP R15 \n" \ /* Accumulator low 32 bits. */ @@ -377,7 +386,7 @@ void vSoftwareInterruptISR( void ) "RTE \n" \ "NOP \n" \ "NOP " - :: "i"(configMAX_SYSCALL_INTERRUPT_PRIORITY), "i"(configKERNEL_INTERRUPT_PRIORITY) + ::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ), "i" ( configKERNEL_INTERRUPT_PRIORITY ) ); } /*-----------------------------------------------------------*/ @@ -385,10 +394,10 @@ void vSoftwareInterruptISR( void ) void vTickISR( void ) { /* Re-enabled interrupts. */ - __asm volatile( "SETPSW I" ); + __asm volatile ( "SETPSW I" ); /* Increment the tick, and perform any processing the new tick value - necessitates. Ensure IPL is at the max syscall value first. */ + * necessitates. Ensure IPL is at the max syscall value first. */ portMASK_INTERRUPTS_FROM_KERNEL_ISR(); { if( xTaskIncrementTick() != pdFALSE ) @@ -429,5 +438,5 @@ void vPortSetIPL( uint32_t ulNewIPL ) "MVTC R5, PSW \n" \ "POP R5 \n" \ "RTS " - ); + ); } diff --git a/Source/portable/GCC/RX600v2/portmacro.h b/Source/portable/GCC/RX600v2/portmacro.h index 344afea1e..acb2ff542 100644 --- a/Source/portable/GCC/RX600v2/portmacro.h +++ b/Source/portable/GCC/RX600v2/portmacro.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -49,79 +49,79 @@ /* When the FIT configurator or the Smart Configurator is used, platform.h has to be * used. */ #ifndef configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H - #define configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H 0 + #define configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H 0 #endif /* Type definitions - these are a bit legacy and not really used now, other than -portSTACK_TYPE and portBASE_TYPE. */ -#define portCHAR char -#define portFLOAT float -#define portDOUBLE double -#define portLONG long -#define portSHORT short -#define portSTACK_TYPE uint32_t -#define portBASE_TYPE long - -typedef portSTACK_TYPE StackType_t; -typedef long BaseType_t; -typedef unsigned long UBaseType_t; - -#if( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS ) - typedef uint16_t TickType_t; - #define portMAX_DELAY ( TickType_t ) 0xffff + * portSTACK_TYPE and portBASE_TYPE. */ +#define portCHAR char +#define portFLOAT float +#define portDOUBLE double +#define portLONG long +#define portSHORT short +#define portSTACK_TYPE uint32_t +#define portBASE_TYPE long + +typedef portSTACK_TYPE StackType_t; +typedef long BaseType_t; +typedef unsigned long UBaseType_t; + +#if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS ) + typedef uint16_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffff #elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS ) - typedef uint32_t TickType_t; - #define portMAX_DELAY ( TickType_t ) 0xffffffffUL + typedef uint32_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffffffffUL - /* 32-bit tick type on a 32-bit architecture, so reads of the tick count do - not need to be guarded with a critical section. */ - #define portTICK_TYPE_IS_ATOMIC 1 +/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do + * not need to be guarded with a critical section. */ + #define portTICK_TYPE_IS_ATOMIC 1 #else #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width. #endif /*-----------------------------------------------------------*/ /* Hardware specifics. */ -#define portBYTE_ALIGNMENT 8 /* Could make four, according to manual. */ -#define portSTACK_GROWTH -1 -#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) -#define portNOP() __asm volatile( "NOP" ) +#define portBYTE_ALIGNMENT 8 /* Could make four, according to manual. */ +#define portSTACK_GROWTH -1 +#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) +#define portNOP() __asm volatile ( "NOP" ) /* Yield equivalent to "*portITU_SWINTR = 0x01; ( void ) *portITU_SWINTR;" -where portITU_SWINTR is the location of the software interrupt register -(0x000872E0). Don't rely on the assembler to select a register, so instead -save and restore clobbered registers manually. */ -#define portYIELD() \ - __asm volatile \ - ( \ - "PUSH.L R10 \n" \ - "MOV.L #0x872E0, R10 \n" \ - "MOV.B #0x1, [R10] \n" \ - "MOV.L [R10], R10 \n" \ - "POP R10 \n" \ + * where portITU_SWINTR is the location of the software interrupt register + * (0x000872E0). Don't rely on the assembler to select a register, so instead + * save and restore clobbered registers manually. */ +#define portYIELD() \ + __asm volatile \ + ( \ + "PUSH.L R10 \n" \ + "MOV.L #0x872E0, R10 \n" \ + "MOV.B #0x1, [R10] \n" \ + "MOV.L [R10], R10 \n" \ + "POP R10 \n" \ ) -#define portYIELD_FROM_ISR( x ) do { if( x != pdFALSE ) portYIELD(); } while( 0 ) +#define portYIELD_FROM_ISR( x ) do { if( x != pdFALSE ) portYIELD( ); } while( 0 ) /* These macros should not be called directly, but through the -taskENTER_CRITICAL() and taskEXIT_CRITICAL() macros. An extra check is -performed if configASSERT() is defined to ensure an assertion handler does not -inadvertently attempt to lower the IPL when the call to assert was triggered -because the IPL value was found to be above configMAX_SYSCALL_INTERRUPT_PRIORITY -when an ISR safe FreeRTOS API function was executed. ISR safe FreeRTOS API -functions are those that end in FromISR. FreeRTOS maintains a separate -interrupt API to ensure API function and interrupt entry is as fast and as -simple as possible. */ -#define portENABLE_INTERRUPTS() __asm volatile ( "MVTIPL #0" ) + * taskENTER_CRITICAL() and taskEXIT_CRITICAL() macros. An extra check is + * performed if configASSERT() is defined to ensure an assertion handler does not + * inadvertently attempt to lower the IPL when the call to assert was triggered + * because the IPL value was found to be above configMAX_SYSCALL_INTERRUPT_PRIORITY + * when an ISR safe FreeRTOS API function was executed. ISR safe FreeRTOS API + * functions are those that end in FromISR. FreeRTOS maintains a separate + * interrupt API to ensure API function and interrupt entry is as fast and as + * simple as possible. */ +#define portENABLE_INTERRUPTS() __asm volatile ( "MVTIPL #0" ) #ifdef configASSERT - #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() configASSERT( ( ulPortGetIPL() <= configMAX_SYSCALL_INTERRUPT_PRIORITY ) ) - #define portDISABLE_INTERRUPTS() if( ulPortGetIPL() < configMAX_SYSCALL_INTERRUPT_PRIORITY ) __asm volatile ( "MVTIPL %0" ::"i"(configMAX_SYSCALL_INTERRUPT_PRIORITY) ) + #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() configASSERT( ( ulPortGetIPL() <= configMAX_SYSCALL_INTERRUPT_PRIORITY ) ) + #define portDISABLE_INTERRUPTS() if( ulPortGetIPL() < configMAX_SYSCALL_INTERRUPT_PRIORITY ) __asm volatile( "MVTIPL %0" ::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) ) #else - #define portDISABLE_INTERRUPTS() __asm volatile ( "MVTIPL %0" ::"i"(configMAX_SYSCALL_INTERRUPT_PRIORITY) ) + #define portDISABLE_INTERRUPTS() __asm volatile ( "MVTIPL %0" ::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) ) #endif /* Critical nesting counts are stored in the TCB. */ -#define portCRITICAL_NESTING_IN_TCB ( 1 ) +#define portCRITICAL_NESTING_IN_TCB ( 1 ) /* The critical nesting functions defined within tasks.c. */ extern void vTaskEnterCritical( void ); @@ -130,16 +130,18 @@ extern void vTaskExitCritical( void ); #define portEXIT_CRITICAL() vTaskExitCritical() /* As this port allows interrupt nesting... */ -uint32_t ulPortGetIPL( void ) __attribute__((naked)); -void vPortSetIPL( uint32_t ulNewIPL ) __attribute__((naked)); -#define portSET_INTERRUPT_MASK_FROM_ISR() ulPortGetIPL(); portDISABLE_INTERRUPTS() -#define portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus ) vPortSetIPL( uxSavedInterruptStatus ) +uint32_t ulPortGetIPL( void ) __attribute__( ( naked ) ); +void vPortSetIPL( uint32_t ulNewIPL ) __attribute__( ( naked ) ); +#define portSET_INTERRUPT_MASK_FROM_ISR() ulPortGetIPL(); portDISABLE_INTERRUPTS() +#define portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus ) vPortSetIPL( uxSavedInterruptStatus ) /*-----------------------------------------------------------*/ /* Task function macros as described on the FreeRTOS.org WEB site. */ -#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters ) -#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters ) +#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters ) +#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters ) + +#define portMEMORY_BARRIER() __asm volatile ( "" ::: "memory" ) /* *INDENT-OFF* */ #ifdef __cplusplus diff --git a/Source/portable/GCC/RX700v3_DPFPU/port.c b/Source/portable/GCC/RX700v3_DPFPU/port.c index 2f47d3017..cd37a58b6 100644 --- a/Source/portable/GCC/RX700v3_DPFPU/port.c +++ b/Source/portable/GCC/RX700v3_DPFPU/port.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -54,22 +54,22 @@ /* Tasks should start with interrupts enabled and in Supervisor mode, therefore * PSW is set with U and I set, and PM and IPL clear. */ -#define portINITIAL_PSW ( ( StackType_t ) 0x00030000 ) -#define portINITIAL_FPSW ( ( StackType_t ) 0x00000100 ) -#define portINITIAL_DPSW ( ( StackType_t ) 0x00000100 ) -#define portINITIAL_DCMR ( ( StackType_t ) 0x00000000 ) -#define portINITIAL_DECNT ( ( StackType_t ) 0x00000001 ) +#define portINITIAL_PSW ( ( StackType_t ) 0x00030000 ) +#define portINITIAL_FPSW ( ( StackType_t ) 0x00000100 ) +#define portINITIAL_DPSW ( ( StackType_t ) 0x00000100 ) +#define portINITIAL_DCMR ( ( StackType_t ) 0x00000000 ) +#define portINITIAL_DECNT ( ( StackType_t ) 0x00000001 ) /* Tasks are not created with a DPFPU context, but can be given a DPFPU context * after they have been created. A variable is stored as part of the tasks context * that holds portNO_DPFPU_CONTEXT if the task does not have a DPFPU context, or * any other value if the task does have a DPFPU context. */ -#define portNO_DPFPU_CONTEXT ( ( StackType_t ) 0 ) -#define portHAS_DPFPU_CONTEXT ( ( StackType_t ) 1 ) +#define portNO_DPFPU_CONTEXT ( ( StackType_t ) 0 ) +#define portHAS_DPFPU_CONTEXT ( ( StackType_t ) 1 ) /* The space on the stack required to hold the DPFPU data registers. This is 16 * 64-bit registers. */ -#define portDPFPU_DATA_REGISTER_WORDS ( 16 * 2 ) +#define portDPFPU_DATA_REGISTER_WORDS ( 16 * 2 ) /* These macros allow a critical section to be added around the call to * xTaskIncrementTick(), which is only ever called from interrupts at the kernel @@ -154,41 +154,41 @@ StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, * value. Otherwise code space can be saved by just setting the registers * that need to be set. */ #ifdef USE_FULL_REGISTER_INITIALISATION - { - pxTopOfStack--; - *pxTopOfStack = 0xffffffff; /* r15. */ - pxTopOfStack--; - *pxTopOfStack = 0xeeeeeeee; - pxTopOfStack--; - *pxTopOfStack = 0xdddddddd; - pxTopOfStack--; - *pxTopOfStack = 0xcccccccc; - pxTopOfStack--; - *pxTopOfStack = 0xbbbbbbbb; - pxTopOfStack--; - *pxTopOfStack = 0xaaaaaaaa; - pxTopOfStack--; - *pxTopOfStack = 0x99999999; - pxTopOfStack--; - *pxTopOfStack = 0x88888888; - pxTopOfStack--; - *pxTopOfStack = 0x77777777; - pxTopOfStack--; - *pxTopOfStack = 0x66666666; - pxTopOfStack--; - *pxTopOfStack = 0x55555555; - pxTopOfStack--; - *pxTopOfStack = 0x44444444; - pxTopOfStack--; - *pxTopOfStack = 0x33333333; - pxTopOfStack--; - *pxTopOfStack = 0x22222222; - pxTopOfStack--; - } + { + pxTopOfStack--; + *pxTopOfStack = 0xffffffff; /* r15. */ + pxTopOfStack--; + *pxTopOfStack = 0xeeeeeeee; + pxTopOfStack--; + *pxTopOfStack = 0xdddddddd; + pxTopOfStack--; + *pxTopOfStack = 0xcccccccc; + pxTopOfStack--; + *pxTopOfStack = 0xbbbbbbbb; + pxTopOfStack--; + *pxTopOfStack = 0xaaaaaaaa; + pxTopOfStack--; + *pxTopOfStack = 0x99999999; + pxTopOfStack--; + *pxTopOfStack = 0x88888888; + pxTopOfStack--; + *pxTopOfStack = 0x77777777; + pxTopOfStack--; + *pxTopOfStack = 0x66666666; + pxTopOfStack--; + *pxTopOfStack = 0x55555555; + pxTopOfStack--; + *pxTopOfStack = 0x44444444; + pxTopOfStack--; + *pxTopOfStack = 0x33333333; + pxTopOfStack--; + *pxTopOfStack = 0x22222222; + pxTopOfStack--; + } #else /* ifdef USE_FULL_REGISTER_INITIALISATION */ - { - pxTopOfStack -= 15; - } + { + pxTopOfStack -= 15; + } #endif /* ifdef USE_FULL_REGISTER_INITIALISATION */ *pxTopOfStack = ( StackType_t ) pvParameters; /* R1 */ @@ -208,73 +208,73 @@ StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, *pxTopOfStack = 0x66666666; /* Accumulator 0. */ #if ( configUSE_TASK_DPFPU_SUPPORT == 1 ) - { - /* The task will start without a DPFPU context. A task that - * uses the DPFPU hardware must call vPortTaskUsesDPFPU() before - * executing any floating point instructions. */ - pxTopOfStack--; - *pxTopOfStack = portNO_DPFPU_CONTEXT; - } + { + /* The task will start without a DPFPU context. A task that + * uses the DPFPU hardware must call vPortTaskUsesDPFPU() before + * executing any floating point instructions. */ + pxTopOfStack--; + *pxTopOfStack = portNO_DPFPU_CONTEXT; + } #elif ( configUSE_TASK_DPFPU_SUPPORT == 2 ) + { + /* The task will start with a DPFPU context. Leave enough + * space for the registers - and ensure they are initialised if desired. */ + #ifdef USE_FULL_REGISTER_INITIALISATION { - /* The task will start with a DPFPU context. Leave enough - * space for the registers - and ensure they are initialised if desired. */ - #ifdef USE_FULL_REGISTER_INITIALISATION - { - pxTopOfStack -= 2; - *(double *)pxTopOfStack = 1515.1515; /* DR15. */ - pxTopOfStack -= 2; - *(double *)pxTopOfStack = 1414.1414; /* DR14. */ - pxTopOfStack -= 2; - *(double *)pxTopOfStack = 1313.1313; /* DR13. */ - pxTopOfStack -= 2; - *(double *)pxTopOfStack = 1212.1212; /* DR12. */ - pxTopOfStack -= 2; - *(double *)pxTopOfStack = 1111.1111; /* DR11. */ - pxTopOfStack -= 2; - *(double *)pxTopOfStack = 1010.1010; /* DR10. */ - pxTopOfStack -= 2; - *(double *)pxTopOfStack = 909.0909; /* DR9. */ - pxTopOfStack -= 2; - *(double *)pxTopOfStack = 808.0808; /* DR8. */ - pxTopOfStack -= 2; - *(double *)pxTopOfStack = 707.0707; /* DR7. */ - pxTopOfStack -= 2; - *(double *)pxTopOfStack = 606.0606; /* DR6. */ - pxTopOfStack -= 2; - *(double *)pxTopOfStack = 505.0505; /* DR5. */ - pxTopOfStack -= 2; - *(double *)pxTopOfStack = 404.0404; /* DR4. */ - pxTopOfStack -= 2; - *(double *)pxTopOfStack = 303.0303; /* DR3. */ - pxTopOfStack -= 2; - *(double *)pxTopOfStack = 202.0202; /* DR2. */ - pxTopOfStack -= 2; - *(double *)pxTopOfStack = 101.0101; /* DR1. */ - pxTopOfStack -= 2; - *(double *)pxTopOfStack = 9876.54321;/* DR0. */ - } - #else /* ifdef USE_FULL_REGISTER_INITIALISATION */ - { - pxTopOfStack -= portDPFPU_DATA_REGISTER_WORDS; - memset( pxTopOfStack, 0x00, portDPFPU_DATA_REGISTER_WORDS * sizeof( StackType_t ) ); - } - #endif /* ifdef USE_FULL_REGISTER_INITIALISATION */ - pxTopOfStack--; - *pxTopOfStack = portINITIAL_DECNT; /* DECNT. */ - pxTopOfStack--; - *pxTopOfStack = portINITIAL_DCMR; /* DCMR. */ - pxTopOfStack--; - *pxTopOfStack = portINITIAL_DPSW; /* DPSW. */ + pxTopOfStack -= 2; + *( double * ) pxTopOfStack = 1515.1515; /* DR15. */ + pxTopOfStack -= 2; + *( double * ) pxTopOfStack = 1414.1414; /* DR14. */ + pxTopOfStack -= 2; + *( double * ) pxTopOfStack = 1313.1313; /* DR13. */ + pxTopOfStack -= 2; + *( double * ) pxTopOfStack = 1212.1212; /* DR12. */ + pxTopOfStack -= 2; + *( double * ) pxTopOfStack = 1111.1111; /* DR11. */ + pxTopOfStack -= 2; + *( double * ) pxTopOfStack = 1010.1010; /* DR10. */ + pxTopOfStack -= 2; + *( double * ) pxTopOfStack = 909.0909; /* DR9. */ + pxTopOfStack -= 2; + *( double * ) pxTopOfStack = 808.0808; /* DR8. */ + pxTopOfStack -= 2; + *( double * ) pxTopOfStack = 707.0707; /* DR7. */ + pxTopOfStack -= 2; + *( double * ) pxTopOfStack = 606.0606; /* DR6. */ + pxTopOfStack -= 2; + *( double * ) pxTopOfStack = 505.0505; /* DR5. */ + pxTopOfStack -= 2; + *( double * ) pxTopOfStack = 404.0404; /* DR4. */ + pxTopOfStack -= 2; + *( double * ) pxTopOfStack = 303.0303; /* DR3. */ + pxTopOfStack -= 2; + *( double * ) pxTopOfStack = 202.0202; /* DR2. */ + pxTopOfStack -= 2; + *( double * ) pxTopOfStack = 101.0101; /* DR1. */ + pxTopOfStack -= 2; + *( double * ) pxTopOfStack = 9876.54321; /* DR0. */ } - #elif ( configUSE_TASK_DPFPU_SUPPORT == 0 ) + #else /* ifdef USE_FULL_REGISTER_INITIALISATION */ { - /* Omit DPFPU support. */ + pxTopOfStack -= portDPFPU_DATA_REGISTER_WORDS; + memset( pxTopOfStack, 0x00, portDPFPU_DATA_REGISTER_WORDS * sizeof( StackType_t ) ); } + #endif /* ifdef USE_FULL_REGISTER_INITIALISATION */ + pxTopOfStack--; + *pxTopOfStack = portINITIAL_DECNT; /* DECNT. */ + pxTopOfStack--; + *pxTopOfStack = portINITIAL_DCMR; /* DCMR. */ + pxTopOfStack--; + *pxTopOfStack = portINITIAL_DPSW; /* DPSW. */ + } + #elif ( configUSE_TASK_DPFPU_SUPPORT == 0 ) + { + /* Omit DPFPU support. */ + } #else /* if ( configUSE_TASK_DPFPU_SUPPORT == 1 ) */ - { - #error Invalid configUSE_TASK_DPFPU_SUPPORT setting - configUSE_TASK_DPFPU_SUPPORT must be set to 0, 1, 2, or left undefined. - } + { + #error Invalid configUSE_TASK_DPFPU_SUPPORT setting - configUSE_TASK_DPFPU_SUPPORT must be set to 0, 1, 2, or left undefined. + } #endif /* if ( configUSE_TASK_DPFPU_SUPPORT == 1 ) */ return pxTopOfStack; @@ -339,14 +339,14 @@ static void prvStartFirstTask( void ) /* When starting the scheduler there is nothing that needs moving to the * interrupt stack because the function is not called from an interrupt. * Just ensure the current stack is the user stack. */ - "SETPSW U \n"\ + "SETPSW U \n" \ /* Obtain the location of the stack associated with which ever task * pxCurrentTCB is currently pointing to. */ - "MOV.L #_pxCurrentTCB, R15 \n"\ - "MOV.L [R15], R15 \n"\ - "MOV.L [R15], R0 \n"\ + "MOV.L #_pxCurrentTCB, R15 \n" \ + "MOV.L [R15], R15 \n" \ + "MOV.L [R15], R0 \n" \ /* Restore the registers from the stack of the task pointed to by @@ -356,53 +356,52 @@ static void prvStartFirstTask( void ) /* The restored ulPortTaskHasDPFPUContext is to be zero here. * So, it is never necessary to restore the DPFPU context here. */ - "POP R15 \n"\ - "MOV.L #_ulPortTaskHasDPFPUContext, R14 \n"\ - "MOV.L R15, [R14] \n"\ + "POP R15 \n" \ + "MOV.L #_ulPortTaskHasDPFPUContext, R14 \n" \ + "MOV.L R15, [R14] \n" \ #elif ( configUSE_TASK_DPFPU_SUPPORT == 2 ) - /* Restore the DPFPU context. */ - "DPOPM.L DPSW-DECNT \n"\ - "DPOPM.D DR0-DR15 \n"\ + "DPOPM.L DPSW-DECNT \n" \ + "DPOPM.D DR0-DR15 \n" \ #endif /* if ( configUSE_TASK_DPFPU_SUPPORT == 1 ) */ - "POP R15 \n"\ + "POP R15 \n" \ /* Accumulator low 32 bits. */ - "MVTACLO R15, A0 \n"\ - "POP R15 \n"\ + "MVTACLO R15, A0 \n" \ + "POP R15 \n" \ /* Accumulator high 32 bits. */ - "MVTACHI R15, A0 \n"\ - "POP R15 \n"\ + "MVTACHI R15, A0 \n" \ + "POP R15 \n" \ /* Accumulator guard. */ - "MVTACGU R15, A0 \n"\ - "POP R15 \n"\ + "MVTACGU R15, A0 \n" \ + "POP R15 \n" \ /* Accumulator low 32 bits. */ - "MVTACLO R15, A1 \n"\ - "POP R15 \n"\ + "MVTACLO R15, A1 \n" \ + "POP R15 \n" \ /* Accumulator high 32 bits. */ - "MVTACHI R15, A1 \n"\ - "POP R15 \n"\ + "MVTACHI R15, A1 \n" \ + "POP R15 \n" \ /* Accumulator guard. */ - "MVTACGU R15, A1 \n"\ - "POP R15 \n"\ + "MVTACGU R15, A1 \n" \ + "POP R15 \n" \ /* Floating point status word. */ - "MVTC R15, FPSW \n"\ + "MVTC R15, FPSW \n" \ /* R1 to R15 - R0 is not included as it is the SP. */ - "POPM R1-R15 \n"\ + "POPM R1-R15 \n" \ /* This pops the remaining registers. */ - "RTE \n"\ - "NOP \n"\ + "RTE \n" \ + "NOP \n" \ "NOP \n" ); } @@ -413,100 +412,99 @@ void vSoftwareInterruptISR( void ) __asm volatile ( /* Re-enable interrupts. */ - "SETPSW I \n"\ + "SETPSW I \n" \ /* Move the data that was automatically pushed onto the interrupt stack when * the interrupt occurred from the interrupt stack to the user stack. * * R15 is saved before it is clobbered. */ - "PUSH.L R15 \n"\ + "PUSH.L R15 \n" \ /* Read the user stack pointer. */ - "MVFC USP, R15 \n"\ + "MVFC USP, R15 \n" \ /* Move the address down to the data being moved. */ - "SUB #12, R15 \n"\ - "MVTC R15, USP \n"\ + "SUB #12, R15 \n" \ + "MVTC R15, USP \n" \ /* Copy the data across, R15, then PC, then PSW. */ - "MOV.L [ R0 ], [ R15 ] \n"\ - "MOV.L 4[ R0 ], 4[ R15 ] \n"\ - "MOV.L 8[ R0 ], 8[ R15 ] \n"\ + "MOV.L [ R0 ], [ R15 ] \n" \ + "MOV.L 4[ R0 ], 4[ R15 ] \n" \ + "MOV.L 8[ R0 ], 8[ R15 ] \n" \ /* Move the interrupt stack pointer to its new correct position. */ - "ADD #12, R0 \n"\ + "ADD #12, R0 \n" \ /* All the rest of the registers are saved directly to the user stack. */ - "SETPSW U \n"\ + "SETPSW U \n" \ /* Save the rest of the general registers (R15 has been saved already). */ - "PUSHM R1-R14 \n"\ + "PUSHM R1-R14 \n" \ /* Save the FPSW and accumulators. */ - "MVFC FPSW, R15 \n"\ - "PUSH.L R15 \n"\ - "MVFACGU #0, A1, R15 \n"\ - "PUSH.L R15 \n"\ - "MVFACHI #0, A1, R15 \n"\ - "PUSH.L R15 \n"\ + "MVFC FPSW, R15 \n" \ + "PUSH.L R15 \n" \ + "MVFACGU #0, A1, R15 \n" \ + "PUSH.L R15 \n" \ + "MVFACHI #0, A1, R15 \n" \ + "PUSH.L R15 \n" \ "MVFACLO #0, A1, R15 \n" /* Low order word. */ \ - "PUSH.L R15 \n"\ - "MVFACGU #0, A0, R15 \n"\ - "PUSH.L R15 \n"\ - "MVFACHI #0, A0, R15 \n"\ - "PUSH.L R15 \n"\ + "PUSH.L R15 \n" \ + "MVFACGU #0, A0, R15 \n" \ + "PUSH.L R15 \n" \ + "MVFACHI #0, A0, R15 \n" \ + "PUSH.L R15 \n" \ "MVFACLO #0, A0, R15 \n" /* Low order word. */ \ - "PUSH.L R15 \n"\ + "PUSH.L R15 \n" \ #if ( configUSE_TASK_DPFPU_SUPPORT == 1 ) /* Does the task have a DPFPU context that needs saving? If * ulPortTaskHasDPFPUContext is 0 then no. */ - "MOV.L #_ulPortTaskHasDPFPUContext, R15 \n"\ - "MOV.L [R15], R15 \n"\ - "CMP #0, R15 \n"\ + "MOV.L #_ulPortTaskHasDPFPUContext, R15 \n" \ + "MOV.L [R15], R15 \n" \ + "CMP #0, R15 \n" \ /* Save the DPFPU context, if any. */ - "BEQ.B ?+ \n"\ - "DPUSHM.D DR0-DR15 \n"\ - "DPUSHM.L DPSW-DECNT \n"\ - "?: \n"\ + "BEQ.B ?+ \n" \ + "DPUSHM.D DR0-DR15 \n" \ + "DPUSHM.L DPSW-DECNT \n" \ + "?: \n" \ /* Save ulPortTaskHasDPFPUContext itself. */ - "PUSH.L R15 \n"\ + "PUSH.L R15 \n" \ #elif ( configUSE_TASK_DPFPU_SUPPORT == 2 ) - /* Save the DPFPU context, always. */ - "DPUSHM.D DR0-DR15 \n"\ - "DPUSHM.L DPSW-DECNT \n"\ + "DPUSHM.D DR0-DR15 \n" \ + "DPUSHM.L DPSW-DECNT \n" \ #endif /* if ( configUSE_TASK_DPFPU_SUPPORT == 1 ) */ /* Save the stack pointer to the TCB. */ - "MOV.L #_pxCurrentTCB, R15 \n"\ - "MOV.L [ R15 ], R15 \n"\ - "MOV.L R0, [ R15 ] \n"\ + "MOV.L #_pxCurrentTCB, R15 \n" \ + "MOV.L [ R15 ], R15 \n" \ + "MOV.L R0, [ R15 ] \n" \ /* Ensure the interrupt mask is set to the syscall priority while the kernel * structures are being accessed. */ - "MVTIPL %0 \n"\ + "MVTIPL %0 \n" \ /* Select the next task to run. */ - "BSR.A _vTaskSwitchContext \n"\ + "BSR.A _vTaskSwitchContext \n" \ /* Reset the interrupt mask as no more data structure access is required. */ - "MVTIPL %1 \n"\ + "MVTIPL %1 \n" \ /* Load the stack pointer of the task that is now selected as the Running * state task from its TCB. */ - "MOV.L #_pxCurrentTCB,R15 \n"\ - "MOV.L [ R15 ], R15 \n"\ - "MOV.L [ R15 ], R0 \n"\ + "MOV.L #_pxCurrentTCB,R15 \n" \ + "MOV.L [ R15 ], R15 \n" \ + "MOV.L [ R15 ], R0 \n" \ /* Restore the context of the new task. The PSW (Program Status Word) and @@ -516,54 +514,53 @@ void vSoftwareInterruptISR( void ) /* Is there a DPFPU context to restore? If the restored * ulPortTaskHasDPFPUContext is zero then no. */ - "POP R15 \n"\ - "MOV.L #_ulPortTaskHasDPFPUContext, R14 \n"\ - "MOV.L R15, [R14] \n"\ - "CMP #0, R15 \n"\ + "POP R15 \n" \ + "MOV.L #_ulPortTaskHasDPFPUContext, R14 \n" \ + "MOV.L R15, [R14] \n" \ + "CMP #0, R15 \n" \ /* Restore the DPFPU context, if any. */ - "BEQ.B ?+ \n"\ - "DPOPM.L DPSW-DECNT \n"\ - "DPOPM.D DR0-DR15 \n"\ - "?: \n"\ + "BEQ.B ?+ \n" \ + "DPOPM.L DPSW-DECNT \n" \ + "DPOPM.D DR0-DR15 \n" \ + "?: \n" \ #elif ( configUSE_TASK_DPFPU_SUPPORT == 2 ) - /* Restore the DPFPU context, always. */ - "DPOPM.L DPSW-DECNT \n"\ - "DPOPM.D DR0-DR15 \n"\ + "DPOPM.L DPSW-DECNT \n" \ + "DPOPM.D DR0-DR15 \n" \ #endif /* if( configUSE_TASK_DPFPU_SUPPORT == 1 ) */ - "POP R15 \n"\ + "POP R15 \n" \ /* Accumulator low 32 bits. */ - "MVTACLO R15, A0 \n"\ - "POP R15 \n"\ + "MVTACLO R15, A0 \n" \ + "POP R15 \n" \ /* Accumulator high 32 bits. */ - "MVTACHI R15, A0 \n"\ - "POP R15 \n"\ + "MVTACHI R15, A0 \n" \ + "POP R15 \n" \ /* Accumulator guard. */ - "MVTACGU R15, A0 \n"\ - "POP R15 \n"\ + "MVTACGU R15, A0 \n" \ + "POP R15 \n" \ /* Accumulator low 32 bits. */ - "MVTACLO R15, A1 \n"\ - "POP R15 \n"\ + "MVTACLO R15, A1 \n" \ + "POP R15 \n" \ /* Accumulator high 32 bits. */ - "MVTACHI R15, A1 \n"\ - "POP R15 \n"\ + "MVTACHI R15, A1 \n" \ + "POP R15 \n" \ /* Accumulator guard. */ - "MVTACGU R15, A1 \n"\ - "POP R15 \n"\ - "MVTC R15, FPSW \n"\ - "POPM R1-R15 \n"\ - "RTE \n"\ - "NOP \n"\ + "MVTACGU R15, A1 \n" \ + "POP R15 \n" \ + "MVTC R15, FPSW \n" \ + "POPM R1-R15 \n" \ + "RTE \n" \ + "NOP \n" \ "NOP " ::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ), "i" ( configKERNEL_INTERRUPT_PRIORITY ) ); @@ -573,7 +570,7 @@ void vSoftwareInterruptISR( void ) void vTickISR( void ) { /* Re-enabled interrupts. */ - __asm volatile ( "SETPSW I"); + __asm volatile ( "SETPSW I" ); /* Increment the tick, and perform any processing the new tick value * necessitates. Ensure IPL is at the max syscall value first. */ @@ -592,8 +589,8 @@ uint32_t ulPortGetIPL( void ) { __asm volatile ( - "MVFC PSW, R1 \n"\ - "SHLR #24, R1 \n"\ + "MVFC PSW, R1 \n" \ + "SHLR #24, R1 \n" \ "RTS " ); @@ -609,13 +606,13 @@ void vPortSetIPL( uint32_t ulNewIPL ) __asm volatile ( - "PUSH R5 \n"\ - "MVFC PSW, R5 \n"\ - "SHLL #24, R1 \n"\ - "AND #-0F000001H, R5 \n"\ - "OR R1, R5 \n"\ - "MVTC R5, PSW \n"\ - "POP R5 \n"\ + "PUSH R5 \n" \ + "MVFC PSW, R5 \n" \ + "SHLL #24, R1 \n" \ + "AND #-0F000001H, R5 \n" \ + "OR R1, R5 \n" \ + "MVTC R5, PSW \n" \ + "POP R5 \n" \ "RTS " ); } diff --git a/Source/portable/GCC/RX700v3_DPFPU/portmacro.h b/Source/portable/GCC/RX700v3_DPFPU/portmacro.h index 5b17ccfcb..c6b1234fb 100644 --- a/Source/portable/GCC/RX700v3_DPFPU/portmacro.h +++ b/Source/portable/GCC/RX700v3_DPFPU/portmacro.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -28,7 +28,7 @@ #ifndef PORTMACRO_H - #define PORTMACRO_H +#define PORTMACRO_H /* *INDENT-OFF* */ #ifdef __cplusplus @@ -48,9 +48,9 @@ /* When the FIT configurator or the Smart Configurator is used, platform.h has to be * used. */ - #ifndef configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H - #define configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H 0 - #endif +#ifndef configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H + #define configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H 0 +#endif /* If configUSE_TASK_DPFPU_SUPPORT is set to 1 (or undefined) then each task will * be created without a DPFPU context, and a task must call vTaskUsesDPFPU() before @@ -58,74 +58,74 @@ * tasks are created with a DPFPU context by default, and calling vTaskUsesDPFPU() has * no effect. If configUSE_TASK_DPFPU_SUPPORT is set to 0 then tasks never take care * of any DPFPU context (even if DPFPU registers are used). */ - #ifndef configUSE_TASK_DPFPU_SUPPORT - #define configUSE_TASK_DPFPU_SUPPORT 1 - #endif +#ifndef configUSE_TASK_DPFPU_SUPPORT + #define configUSE_TASK_DPFPU_SUPPORT 1 +#endif /*-----------------------------------------------------------*/ /* Type definitions - these are a bit legacy and not really used now, other than * portSTACK_TYPE and portBASE_TYPE. */ - #define portCHAR char - #define portFLOAT float - #define portDOUBLE double - #define portLONG long - #define portSHORT short - #define portSTACK_TYPE uint32_t - #define portBASE_TYPE long - - typedef portSTACK_TYPE StackType_t; - typedef long BaseType_t; - typedef unsigned long UBaseType_t; - - #if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS ) - typedef uint16_t TickType_t; - #define portMAX_DELAY ( TickType_t ) 0xffff - #elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS ) - typedef uint32_t TickType_t; - #define portMAX_DELAY ( TickType_t ) 0xffffffffUL +#define portCHAR char +#define portFLOAT float +#define portDOUBLE double +#define portLONG long +#define portSHORT short +#define portSTACK_TYPE uint32_t +#define portBASE_TYPE long + +typedef portSTACK_TYPE StackType_t; +typedef long BaseType_t; +typedef unsigned long UBaseType_t; + +#if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS ) + typedef uint16_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffff +#elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS ) + typedef uint32_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffffffffUL /* 32-bit tick type on a 32-bit architecture, so reads of the tick count do * not need to be guarded with a critical section. */ - #define portTICK_TYPE_IS_ATOMIC 1 - #else - #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width. - #endif + #define portTICK_TYPE_IS_ATOMIC 1 +#else + #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width. +#endif /*-----------------------------------------------------------*/ /* Hardware specifics. */ - #define portBYTE_ALIGNMENT 8 /* Could make four, according to manual. */ - #define portSTACK_GROWTH -1 - #define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) - #define portNOP() __asm volatile ( "NOP" ) +#define portBYTE_ALIGNMENT 8 /* Could make four, according to manual. */ +#define portSTACK_GROWTH -1 +#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) +#define portNOP() __asm volatile ( "NOP" ) /* Yield equivalent to "*portITU_SWINTR = 0x01; ( void ) *portITU_SWINTR;" * where portITU_SWINTR is the location of the software interrupt register * (0x000872E0). Don't rely on the assembler to select a register, so instead * save and restore clobbered registers manually. */ - #define portYIELD() \ - __asm volatile \ - ( \ - "PUSH.L R10 \n"\ - "MOV.L #0x872E0, R10 \n"\ - "MOV.B #0x1, [R10] \n"\ - "CMP [R10].UB, R10 \n"\ - "POP R10 \n"\ - :::"cc" \ +#define portYIELD() \ + __asm volatile \ + ( \ + "PUSH.L R10 \n" \ + "MOV.L #0x872E0, R10 \n" \ + "MOV.B #0x1, [R10] \n" \ + "CMP [R10].UB, R10 \n" \ + "POP R10 \n" \ + ::: "cc" \ ) - #define portYIELD_FROM_ISR( x ) do { if( ( x ) != pdFALSE ) portYIELD(); } while( 0 ) +#define portYIELD_FROM_ISR( x ) do { if( ( x ) != pdFALSE ) portYIELD( ); } while( 0 ) /* Workaround to reduce errors/warnings caused by e2 studio CDT's INDEXER and CODAN. */ - #ifdef __CDT_PARSER__ +#ifdef __CDT_PARSER__ #ifndef __asm - #define __asm asm + #define __asm asm #endif #ifndef __attribute__ - #define __attribute__( ... ) - #endif + #define __attribute__( ... ) #endif +#endif /* These macros should not be called directly, but through the * taskENTER_CRITICAL() and taskEXIT_CRITICAL() macros. An extra check is @@ -136,34 +136,34 @@ * functions are those that end in FromISR. FreeRTOS maintains a separate * interrupt API to ensure API function and interrupt entry is as fast and as * simple as possible. */ - #define portENABLE_INTERRUPTS() __asm volatile ( "MVTIPL #0") - #ifdef configASSERT - #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() configASSERT( ( ulPortGetIPL() <= configMAX_SYSCALL_INTERRUPT_PRIORITY ) ) - #define portDISABLE_INTERRUPTS() if( ulPortGetIPL() < configMAX_SYSCALL_INTERRUPT_PRIORITY ) __asm volatile ( "MVTIPL %0"::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) ) - #else - #define portDISABLE_INTERRUPTS() __asm volatile ( "MVTIPL %0"::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) ) - #endif +#define portENABLE_INTERRUPTS() __asm volatile ( "MVTIPL #0" ) +#ifdef configASSERT + #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() configASSERT( ( ulPortGetIPL() <= configMAX_SYSCALL_INTERRUPT_PRIORITY ) ) + #define portDISABLE_INTERRUPTS() if( ulPortGetIPL() < configMAX_SYSCALL_INTERRUPT_PRIORITY ) __asm volatile( "MVTIPL %0" ::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) ) +#else + #define portDISABLE_INTERRUPTS() __asm volatile ( "MVTIPL %0" ::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) ) +#endif /* Critical nesting counts are stored in the TCB. */ - #define portCRITICAL_NESTING_IN_TCB ( 1 ) +#define portCRITICAL_NESTING_IN_TCB ( 1 ) /* The critical nesting functions defined within tasks.c. */ - extern void vTaskEnterCritical( void ); - extern void vTaskExitCritical( void ); - #define portENTER_CRITICAL() vTaskEnterCritical() - #define portEXIT_CRITICAL() vTaskExitCritical() +extern void vTaskEnterCritical( void ); +extern void vTaskExitCritical( void ); +#define portENTER_CRITICAL() vTaskEnterCritical() +#define portEXIT_CRITICAL() vTaskExitCritical() /* As this port allows interrupt nesting... */ - uint32_t ulPortGetIPL( void ) __attribute__( ( naked ) ); - void vPortSetIPL( uint32_t ulNewIPL ) __attribute__( ( naked ) ); - #define portSET_INTERRUPT_MASK_FROM_ISR() ulPortGetIPL(); portDISABLE_INTERRUPTS() - #define portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus ) vPortSetIPL( uxSavedInterruptStatus ) +uint32_t ulPortGetIPL( void ) __attribute__( ( naked ) ); +void vPortSetIPL( uint32_t ulNewIPL ) __attribute__( ( naked ) ); +#define portSET_INTERRUPT_MASK_FROM_ISR() ulPortGetIPL(); portDISABLE_INTERRUPTS() +#define portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus ) vPortSetIPL( uxSavedInterruptStatus ) /*-----------------------------------------------------------*/ /* Task function macros as described on the FreeRTOS.org WEB site. */ - #define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters ) - #define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters ) +#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters ) +#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters ) /*-----------------------------------------------------------*/ @@ -172,17 +172,20 @@ * themselves a DPFPU context before using any DPFPU instructions. If * configUSE_TASK_DPFPU_SUPPORT is set to 2 then all tasks will have a DPFPU context * by default. */ - #if( configUSE_TASK_DPFPU_SUPPORT == 1 ) - void vPortTaskUsesDPFPU( void ); - #else +#if ( configUSE_TASK_DPFPU_SUPPORT == 1 ) + void vPortTaskUsesDPFPU( void ); +#else + /* Each task has a DPFPU context already, so define this function away to * nothing to prevent it being called accidentally. */ - #define vPortTaskUsesDPFPU() - #endif - #define portTASK_USES_DPFPU() vPortTaskUsesDPFPU() + #define vPortTaskUsesDPFPU() +#endif +#define portTASK_USES_DPFPU() vPortTaskUsesDPFPU() /* Definition to allow compatibility with existing FreeRTOS Demo using flop.c. */ - #define portTASK_USES_FLOATING_POINT() vPortTaskUsesDPFPU() +#define portTASK_USES_FLOATING_POINT() vPortTaskUsesDPFPU() + +#define portMEMORY_BARRIER() __asm volatile ( "" ::: "memory" ) /* *INDENT-OFF* */ #ifdef __cplusplus diff --git a/Source/portable/GCC/STR75x/port.c b/Source/portable/GCC/STR75x/port.c index 781c8e2de..a9b1fa971 100644 --- a/Source/portable/GCC/STR75x/port.c +++ b/Source/portable/GCC/STR75x/port.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -27,9 +27,9 @@ */ /*----------------------------------------------------------- - * Implementation of functions defined in portable.h for the ST STR75x ARM7 - * port. - *----------------------------------------------------------*/ +* Implementation of functions defined in portable.h for the ST STR75x ARM7 +* port. +*----------------------------------------------------------*/ /* Library includes. */ #include "75x_tb.h" @@ -40,15 +40,15 @@ #include "task.h" /* Constants required to setup the initial stack. */ -#define portINITIAL_SPSR ( ( StackType_t ) 0x1f ) /* System mode, ARM mode, interrupts enabled. */ -#define portTHUMB_MODE_BIT ( ( StackType_t ) 0x20 ) -#define portINSTRUCTION_SIZE ( ( StackType_t ) 4 ) +#define portINITIAL_SPSR ( ( StackType_t ) 0x1f ) /* System mode, ARM mode, interrupts enabled. */ +#define portTHUMB_MODE_BIT ( ( StackType_t ) 0x20 ) +#define portINSTRUCTION_SIZE ( ( StackType_t ) 4 ) /* Constants required to handle critical sections. */ -#define portNO_CRITICAL_NESTING ( ( uint32_t ) 0 ) +#define portNO_CRITICAL_NESTING ( ( uint32_t ) 0 ) /* Prescale used on the timer clock when calculating the tick period. */ -#define portPRESCALE 20 +#define portPRESCALE 20 /*-----------------------------------------------------------*/ @@ -64,56 +64,58 @@ static void prvSetupTimerInterrupt( void ); * * See header file for description. */ -StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters ) +StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, + TaskFunction_t pxCode, + void * pvParameters ) { -StackType_t *pxOriginalTOS; + StackType_t * pxOriginalTOS; pxOriginalTOS = pxTopOfStack; /* To ensure asserts in tasks.c don't fail, although in this case the assert - is not really required. */ + * is not really required. */ pxTopOfStack--; /* Setup the initial stack of the task. The stack is set exactly as - expected by the portRESTORE_CONTEXT() macro. */ + * expected by the portRESTORE_CONTEXT() macro. */ /* First on the stack is the return address - which in this case is the - start of the task. The offset is added to make the return address appear - as it would within an IRQ ISR. */ + * start of the task. The offset is added to make the return address appear + * as it would within an IRQ ISR. */ *pxTopOfStack = ( StackType_t ) pxCode + portINSTRUCTION_SIZE; pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0xaaaaaaaa; /* R14 */ + *pxTopOfStack = ( StackType_t ) 0xaaaaaaaa; /* R14 */ pxTopOfStack--; *pxTopOfStack = ( StackType_t ) pxOriginalTOS; /* Stack used when task starts goes in R13. */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x12121212; /* R12 */ + *pxTopOfStack = ( StackType_t ) 0x12121212; /* R12 */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x11111111; /* R11 */ + *pxTopOfStack = ( StackType_t ) 0x11111111; /* R11 */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x10101010; /* R10 */ + *pxTopOfStack = ( StackType_t ) 0x10101010; /* R10 */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x09090909; /* R9 */ + *pxTopOfStack = ( StackType_t ) 0x09090909; /* R9 */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x08080808; /* R8 */ + *pxTopOfStack = ( StackType_t ) 0x08080808; /* R8 */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x07070707; /* R7 */ + *pxTopOfStack = ( StackType_t ) 0x07070707; /* R7 */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x06060606; /* R6 */ + *pxTopOfStack = ( StackType_t ) 0x06060606; /* R6 */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x05050505; /* R5 */ + *pxTopOfStack = ( StackType_t ) 0x05050505; /* R5 */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x04040404; /* R4 */ + *pxTopOfStack = ( StackType_t ) 0x04040404; /* R4 */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x03030303; /* R3 */ + *pxTopOfStack = ( StackType_t ) 0x03030303; /* R3 */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x02020202; /* R2 */ + *pxTopOfStack = ( StackType_t ) 0x02020202; /* R2 */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x01010101; /* R1 */ + *pxTopOfStack = ( StackType_t ) 0x01010101; /* R1 */ pxTopOfStack--; /* When the task starts is will expect to find the function parameter in - R0. */ + * R0. */ *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */ pxTopOfStack--; @@ -130,8 +132,8 @@ StackType_t *pxOriginalTOS; pxTopOfStack--; /* Interrupt flags cannot always be stored on the stack and will - instead be stored in a variable, which is then saved as part of the - tasks context. */ + * instead be stored in a variable, which is then saved as part of the + * tasks context. */ *pxTopOfStack = portNO_CRITICAL_NESTING; return pxTopOfStack; @@ -140,10 +142,10 @@ StackType_t *pxOriginalTOS; BaseType_t xPortStartScheduler( void ) { -extern void vPortISRStartFirstTask( void ); + extern void vPortISRStartFirstTask( void ); /* Start the timer that generates the tick ISR. Interrupts are disabled - here already. */ + * here already. */ prvSetupTimerInterrupt(); /* Start the first task. */ @@ -157,35 +159,35 @@ extern void vPortISRStartFirstTask( void ); void vPortEndScheduler( void ) { /* It is unlikely that the ARM port will require this function as there - is nothing to return to. */ + * is nothing to return to. */ } /*-----------------------------------------------------------*/ static void prvSetupTimerInterrupt( void ) { -EIC_IRQInitTypeDef EIC_IRQInitStructure; -TB_InitTypeDef TB_InitStructure; + EIC_IRQInitTypeDef EIC_IRQInitStructure; + TB_InitTypeDef TB_InitStructure; /* Setup the EIC for the TB. */ EIC_IRQInitStructure.EIC_IRQChannelCmd = ENABLE; EIC_IRQInitStructure.EIC_IRQChannel = TB_IRQChannel; EIC_IRQInitStructure.EIC_IRQChannelPriority = 1; - EIC_IRQInit(&EIC_IRQInitStructure); + EIC_IRQInit( &EIC_IRQInitStructure ); /* Setup the TB for the generation of the tick interrupt. */ TB_InitStructure.TB_Mode = TB_Mode_Timing; TB_InitStructure.TB_CounterMode = TB_CounterMode_Down; TB_InitStructure.TB_Prescaler = portPRESCALE - 1; TB_InitStructure.TB_AutoReload = ( ( configCPU_CLOCK_HZ / portPRESCALE ) / configTICK_RATE_HZ ); - TB_Init(&TB_InitStructure); + TB_Init( &TB_InitStructure ); /* Enable TB Update interrupt */ - TB_ITConfig(TB_IT_Update, ENABLE); + TB_ITConfig( TB_IT_Update, ENABLE ); /* Clear TB Update interrupt pending bit */ - TB_ClearITPendingBit(TB_IT_Update); + TB_ClearITPendingBit( TB_IT_Update ); /* Enable TB */ - TB_Cmd(ENABLE); + TB_Cmd( ENABLE ); } /*-----------------------------------------------------------*/ diff --git a/Source/portable/GCC/STR75x/portISR.c b/Source/portable/GCC/STR75x/portISR.c index 016cfc603..dcecfd83e 100644 --- a/Source/portable/GCC/STR75x/portISR.c +++ b/Source/portable/GCC/STR75x/portISR.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -28,20 +28,20 @@ /*----------------------------------------------------------- - * Components that can be compiled to either ARM or THUMB mode are - * contained in port.c The ISR routines, which can only be compiled - * to ARM mode, are contained in this file. - *----------------------------------------------------------*/ +* Components that can be compiled to either ARM or THUMB mode are +* contained in port.c The ISR routines, which can only be compiled +* to ARM mode, are contained in this file. +*----------------------------------------------------------*/ /* -*/ + */ /* Scheduler includes. */ #include "FreeRTOS.h" #include "task.h" /* Constants required to handle critical sections. */ -#define portNO_CRITICAL_NESTING ( ( uint32_t ) 0 ) +#define portNO_CRITICAL_NESTING ( ( uint32_t ) 0 ) volatile uint32_t ulCriticalNesting = 9999UL; @@ -57,40 +57,40 @@ void vPortISRStartFirstTask( void ); void vPortISRStartFirstTask( void ) { /* Simply start the scheduler. This is included here as it can only be - called from ARM mode. */ - asm volatile ( \ - "LDR R0, =pxCurrentTCB \n\t" \ - "LDR R0, [R0] \n\t" \ - "LDR LR, [R0] \n\t" \ - \ - /* The critical nesting depth is the first item on the stack. */ \ - /* Load it into the ulCriticalNesting variable. */ \ - "LDR R0, =ulCriticalNesting \n\t" \ - "LDMFD LR!, {R1} \n\t" \ - "STR R1, [R0] \n\t" \ - \ - /* Get the SPSR from the stack. */ \ - "LDMFD LR!, {R0} \n\t" \ - "MSR SPSR, R0 \n\t" \ - \ - /* Restore all system mode registers for the task. */ \ - "LDMFD LR, {R0-R14}^ \n\t" \ - "NOP \n\t" \ - \ - /* Restore the return address. */ \ - "LDR LR, [LR, #+60] \n\t" \ - \ - /* And return - correcting the offset in the LR to obtain the */ \ - /* correct address. */ \ - "SUBS PC, LR, #4 \n\t" \ - ); + * called from ARM mode. */ + asm volatile ( \ + "LDR R0, =pxCurrentTCB \n\t" \ + "LDR R0, [R0] \n\t" \ + "LDR LR, [R0] \n\t" \ + \ + /* The critical nesting depth is the first item on the stack. */ \ + /* Load it into the ulCriticalNesting variable. */ \ + "LDR R0, =ulCriticalNesting \n\t" \ + "LDMFD LR!, {R1} \n\t" \ + "STR R1, [R0] \n\t" \ + \ + /* Get the SPSR from the stack. */ \ + "LDMFD LR!, {R0} \n\t" \ + "MSR SPSR, R0 \n\t" \ + \ + /* Restore all system mode registers for the task. */ \ + "LDMFD LR, {R0-R14}^ \n\t" \ + "NOP \n\t" \ + \ + /* Restore the return address. */ \ + "LDR LR, [LR, #+60] \n\t" \ + \ + /* And return - correcting the offset in the LR to obtain the */ \ + /* correct address. */ \ + "SUBS PC, LR, #4 \n\t" \ + ); } /*-----------------------------------------------------------*/ void vPortTickISR( void ) { /* Increment the RTOS tick count, then look for the highest priority - task that is ready to run. */ + * task that is ready to run. */ if( xTaskIncrementTick() != pdFALSE ) { vTaskSwitchContext(); @@ -110,29 +110,29 @@ void vPortTickISR( void ) */ #ifdef THUMB_INTERWORK - void vPortDisableInterruptsFromThumb( void ) __attribute__ ((naked)); - void vPortEnableInterruptsFromThumb( void ) __attribute__ ((naked)); + void vPortDisableInterruptsFromThumb( void ) __attribute__( ( naked ) ); + void vPortEnableInterruptsFromThumb( void ) __attribute__( ( naked ) ); void vPortDisableInterruptsFromThumb( void ) { asm volatile ( - "STMDB SP!, {R0} \n\t" /* Push R0. */ - "MRS R0, CPSR \n\t" /* Get CPSR. */ - "ORR R0, R0, #0xC0 \n\t" /* Disable IRQ, FIQ. */ - "MSR CPSR, R0 \n\t" /* Write back modified value. */ - "LDMIA SP!, {R0} \n\t" /* Pop R0. */ - "BX R14" ); /* Return back to thumb. */ + "STMDB SP!, {R0} \n\t" /* Push R0. */ + "MRS R0, CPSR \n\t" /* Get CPSR. */ + "ORR R0, R0, #0xC0 \n\t" /* Disable IRQ, FIQ. */ + "MSR CPSR, R0 \n\t" /* Write back modified value. */ + "LDMIA SP!, {R0} \n\t" /* Pop R0. */ + "BX R14" ); /* Return back to thumb. */ } void vPortEnableInterruptsFromThumb( void ) { asm volatile ( - "STMDB SP!, {R0} \n\t" /* Push R0. */ - "MRS R0, CPSR \n\t" /* Get CPSR. */ - "BIC R0, R0, #0xC0 \n\t" /* Enable IRQ, FIQ. */ - "MSR CPSR, R0 \n\t" /* Write back modified value. */ - "LDMIA SP!, {R0} \n\t" /* Pop R0. */ - "BX R14" ); /* Return back to thumb. */ + "STMDB SP!, {R0} \n\t" /* Push R0. */ + "MRS R0, CPSR \n\t" /* Get CPSR. */ + "BIC R0, R0, #0xC0 \n\t" /* Enable IRQ, FIQ. */ + "MSR CPSR, R0 \n\t" /* Write back modified value. */ + "LDMIA SP!, {R0} \n\t" /* Pop R0. */ + "BX R14" ); /* Return back to thumb. */ } #endif /* THUMB_INTERWORK */ @@ -142,15 +142,15 @@ void vPortEnterCritical( void ) { /* Disable interrupts as per portDISABLE_INTERRUPTS(); */ asm volatile ( - "STMDB SP!, {R0} \n\t" /* Push R0. */ - "MRS R0, CPSR \n\t" /* Get CPSR. */ - "ORR R0, R0, #0xC0 \n\t" /* Disable IRQ, FIQ. */ - "MSR CPSR, R0 \n\t" /* Write back modified value. */ - "LDMIA SP!, {R0}" ); /* Pop R0. */ - - /* Now interrupts are disabled ulCriticalNesting can be accessed - directly. Increment ulCriticalNesting to keep a count of how many times - portENTER_CRITICAL() has been called. */ + "STMDB SP!, {R0} \n\t" /* Push R0. */ + "MRS R0, CPSR \n\t" /* Get CPSR. */ + "ORR R0, R0, #0xC0 \n\t" /* Disable IRQ, FIQ. */ + "MSR CPSR, R0 \n\t" /* Write back modified value. */ + "LDMIA SP!, {R0}" ); /* Pop R0. */ + + /* Now that interrupts are disabled, ulCriticalNesting can be accessed + * directly. Increment ulCriticalNesting to keep a count of how many times + * portENTER_CRITICAL() has been called. */ ulCriticalNesting++; } /*-----------------------------------------------------------*/ @@ -163,16 +163,16 @@ void vPortExitCritical( void ) ulCriticalNesting--; /* If the nesting level has reached zero then interrupts should be - re-enabled. */ + * re-enabled. */ if( ulCriticalNesting == portNO_CRITICAL_NESTING ) { /* Enable interrupts as per portEXIT_CRITICAL(). */ asm volatile ( - "STMDB SP!, {R0} \n\t" /* Push R0. */ - "MRS R0, CPSR \n\t" /* Get CPSR. */ - "BIC R0, R0, #0xC0 \n\t" /* Enable IRQ, FIQ. */ - "MSR CPSR, R0 \n\t" /* Write back modified value. */ - "LDMIA SP!, {R0}" ); /* Pop R0. */ + "STMDB SP!, {R0} \n\t" /* Push R0. */ + "MRS R0, CPSR \n\t" /* Get CPSR. */ + "BIC R0, R0, #0xC0 \n\t" /* Enable IRQ, FIQ. */ + "MSR CPSR, R0 \n\t" /* Write back modified value. */ + "LDMIA SP!, {R0}" ); /* Pop R0. */ } } } diff --git a/Source/portable/GCC/STR75x/portmacro.h b/Source/portable/GCC/STR75x/portmacro.h index 91b4daa79..6901bb993 100644 --- a/Source/portable/GCC/STR75x/portmacro.h +++ b/Source/portable/GCC/STR75x/portmacro.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -47,38 +47,39 @@ */ /* Type definitions. */ -#define portCHAR char -#define portFLOAT float -#define portDOUBLE double -#define portLONG long -#define portSHORT short -#define portSTACK_TYPE uint32_t -#define portBASE_TYPE long - -typedef portSTACK_TYPE StackType_t; -typedef long BaseType_t; -typedef unsigned long UBaseType_t; - -#if( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS ) - typedef uint16_t TickType_t; - #define portMAX_DELAY ( TickType_t ) 0xffff +#define portCHAR char +#define portFLOAT float +#define portDOUBLE double +#define portLONG long +#define portSHORT short +#define portSTACK_TYPE uint32_t +#define portBASE_TYPE long + +typedef portSTACK_TYPE StackType_t; +typedef long BaseType_t; +typedef unsigned long UBaseType_t; + +#if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS ) + typedef uint16_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffff #elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS ) - typedef uint32_t TickType_t; - #define portMAX_DELAY ( TickType_t ) ( 0xFFFFFFFFUL ) + typedef uint32_t TickType_t; + #define portMAX_DELAY ( TickType_t ) ( 0xFFFFFFFFUL ) #else #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width. #endif /*-----------------------------------------------------------*/ /* Hardware specifics. */ -#define portSTACK_GROWTH ( -1 ) -#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) -#define portBYTE_ALIGNMENT 8 -#define portYIELD() asm volatile ( "SWI 0" ) -#define portNOP() asm volatile ( "NOP" ) +#define portSTACK_GROWTH ( -1 ) +#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) +#define portBYTE_ALIGNMENT 8 +#define portYIELD() asm volatile ( "SWI 0" ) +#define portNOP() asm volatile ( "NOP" ) /*-----------------------------------------------------------*/ /* Critical section handling. */ + /* * The interrupt management utilities can only be called from ARM mode. When * THUMB_INTERWORK is defined the utilities are defined as functions in @@ -88,54 +89,59 @@ typedef unsigned long UBaseType_t; #ifdef THUMB_INTERWORK - extern void vPortDisableInterruptsFromThumb( void ) __attribute__ ((naked)); - extern void vPortEnableInterruptsFromThumb( void ) __attribute__ ((naked)); + extern void vPortDisableInterruptsFromThumb( void ) __attribute__( ( naked ) ); + extern void vPortEnableInterruptsFromThumb( void ) __attribute__( ( naked ) ); #define portDISABLE_INTERRUPTS() vPortDisableInterruptsFromThumb() #define portENABLE_INTERRUPTS() vPortEnableInterruptsFromThumb() #else - #define portDISABLE_INTERRUPTS() \ - asm volatile ( \ - "STMDB SP!, {R0} \n\t" /* Push R0. */ \ - "MRS R0, CPSR \n\t" /* Get CPSR. */ \ - "ORR R0, R0, #0xC0 \n\t" /* Disable IRQ, FIQ. */ \ - "MSR CPSR, R0 \n\t" /* Write back modified value. */ \ - "LDMIA SP!, {R0} " ) /* Pop R0. */ - - #define portENABLE_INTERRUPTS() \ - asm volatile ( \ - "STMDB SP!, {R0} \n\t" /* Push R0. */ \ - "MRS R0, CPSR \n\t" /* Get CPSR. */ \ - "BIC R0, R0, #0xC0 \n\t" /* Enable IRQ, FIQ. */ \ - "MSR CPSR, R0 \n\t" /* Write back modified value. */ \ - "LDMIA SP!, {R0} " ) /* Pop R0. */ + #define portDISABLE_INTERRUPTS() \ + asm volatile ( \ + "STMDB SP!, {R0} \n\t" /* Push R0. */ \ + "MRS R0, CPSR \n\t" /* Get CPSR. */ \ + "ORR R0, R0, #0xC0 \n\t" /* Disable IRQ, FIQ. */ \ + "MSR CPSR, R0 \n\t" /* Write back modified value. */ \ + "LDMIA SP!, {R0} " ) /* Pop R0. */ + + #define portENABLE_INTERRUPTS() \ + asm volatile ( \ + "STMDB SP!, {R0} \n\t" /* Push R0. */ \ + "MRS R0, CPSR \n\t" /* Get CPSR. */ \ + "BIC R0, R0, #0xC0 \n\t" /* Enable IRQ, FIQ. */ \ + "MSR CPSR, R0 \n\t" /* Write back modified value. */ \ + "LDMIA SP!, {R0} " ) /* Pop R0. */ #endif /* THUMB_INTERWORK */ extern void vPortEnterCritical( void ); extern void vPortExitCritical( void ); -#define portENTER_CRITICAL() vPortEnterCritical(); -#define portEXIT_CRITICAL() vPortExitCritical(); +#define portENTER_CRITICAL() vPortEnterCritical(); +#define portEXIT_CRITICAL() vPortExitCritical(); /*-----------------------------------------------------------*/ /* Task utilities. */ -#define portEND_SWITCHING_ISR( xSwitchRequired ) \ -{ \ -extern void vTaskSwitchContext( void ); \ - \ - if( xSwitchRequired ) \ - { \ - vTaskSwitchContext(); \ - } \ -} +#define portEND_SWITCHING_ISR( xSwitchRequired ) \ + { \ + extern void vTaskSwitchContext( void ); \ + \ + if( xSwitchRequired ) \ + { \ + traceISR_EXIT_TO_SCHEDULER(); \ + vTaskSwitchContext(); \ + } \ + else \ + { \ + traceISR_EXIT(); \ + } \ + } /*-----------------------------------------------------------*/ /* Task function macros as described on the FreeRTOS.org WEB site. */ -#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters ) -#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters ) +#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters ) +#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters ) /* *INDENT-OFF* */ #ifdef __cplusplus diff --git a/Source/portable/GCC/TriCore_1782/port.c b/Source/portable/GCC/TriCore_1782/port.c index 8675fdefa..6dc5a41fd 100644 --- a/Source/portable/GCC/TriCore_1782/port.c +++ b/Source/portable/GCC/TriCore_1782/port.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -57,23 +57,23 @@ #define portINITIAL_SYSCON ( 0x00000000UL ) /* MPU Disable. */ /* CSA manipulation macros. */ -#define portCSA_FCX_MASK ( 0x000FFFFFUL ) +#define portCSA_FCX_MASK ( 0x000FFFFFUL ) /* OS Interrupt and Trap mechanisms. */ -#define portRESTORE_PSW_MASK ( ~( 0x000000FFUL ) ) -#define portSYSCALL_TRAP ( 6 ) +#define portRESTORE_PSW_MASK ( ~( 0x000000FFUL ) ) +#define portSYSCALL_TRAP ( 6 ) /* Each CSA contains 16 words of data. */ -#define portNUM_WORDS_IN_CSA ( 16 ) +#define portNUM_WORDS_IN_CSA ( 16 ) /* The interrupt enable bit in the PCP_SRC register. */ -#define portENABLE_CPU_INTERRUPT ( 1U << 12U ) +#define portENABLE_CPU_INTERRUPT ( 1U << 12U ) /*-----------------------------------------------------------*/ /* * Perform any hardware configuration necessary to generate the tick interrupt. */ -static void prvSystemTickHandler( int ) __attribute__((longcall)); +static void prvSystemTickHandler( int ) __attribute__( ( longcall ) ); static void prvSetupTimerInterrupt( void ); /* @@ -89,37 +89,39 @@ static void prvInterruptYield( int iTrapIdentification ); /*-----------------------------------------------------------*/ /* This reference is required by the save/restore context macros. */ -extern volatile uint32_t *pxCurrentTCB; +extern volatile uint32_t * pxCurrentTCB; /* Precalculate the compare match value at compile time. */ static const uint32_t ulCompareMatchValue = ( configPERIPHERAL_CLOCK_HZ / configTICK_RATE_HZ ); /*-----------------------------------------------------------*/ -StackType_t *pxPortInitialiseStack( StackType_t * pxTopOfStack, TaskFunction_t pxCode, void *pvParameters ) +StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, + TaskFunction_t pxCode, + void * pvParameters ) { -uint32_t *pulUpperCSA = NULL; -uint32_t *pulLowerCSA = NULL; + uint32_t * pulUpperCSA = NULL; + uint32_t * pulLowerCSA = NULL; /* 16 Address Registers (4 Address registers are global), 16 Data - Registers, and 3 System Registers. - - There are 3 registers that track the CSAs. - FCX points to the head of globally free set of CSAs. - PCX for the task needs to point to Lower->Upper->NULL arrangement. - LCX points to the last free CSA so that corrective action can be taken. - - Need two CSAs to store the context of a task. - The upper context contains D8-D15, A10-A15, PSW and PCXI->NULL. - The lower context contains D0-D7, A2-A7, A11 and PCXI->UpperContext. - The pxCurrentTCB->pxTopOfStack points to the Lower Context RSLCX matching the initial BISR. - The Lower Context points to the Upper Context ready for the return from the interrupt handler. - - The Real stack pointer for the task is stored in the A10 which is restored - with the upper context. */ + * Registers, and 3 System Registers. + * + * There are 3 registers that track the CSAs. + * FCX points to the head of globally free set of CSAs. + * PCX for the task needs to point to Lower->Upper->NULL arrangement. + * LCX points to the last free CSA so that corrective action can be taken. + * + * Need two CSAs to store the context of a task. + * The upper context contains D8-D15, A10-A15, PSW and PCXI->NULL. + * The lower context contains D0-D7, A2-A7, A11 and PCXI->UpperContext. + * The pxCurrentTCB->pxTopOfStack points to the Lower Context RSLCX matching the initial BISR. + * The Lower Context points to the Upper Context ready for the return from the interrupt handler. + * + * The Real stack pointer for the task is stored in the A10 which is restored + * with the upper context. */ /* Have to disable interrupts here because the CSAs are going to be - manipulated. */ + * manipulated. */ portENTER_CRITICAL(); { /* DSync to ensure that buffering is not a problem. */ @@ -127,6 +129,7 @@ uint32_t *pulLowerCSA = NULL; /* Consume two free CSAs. */ pulLowerCSA = portCSA_TO_ADDRESS( __MFCR( $FCX ) ); + if( NULL != pulLowerCSA ) { /* The Lower Links to the Upper. */ @@ -155,21 +158,21 @@ uint32_t *pulLowerCSA = NULL; memset( pulUpperCSA, 0, portNUM_WORDS_IN_CSA * sizeof( uint32_t ) ); /* Upper Context. */ - pulUpperCSA[ 2 ] = ( uint32_t )pxTopOfStack; /* A10; Stack Return aka Stack Pointer */ - pulUpperCSA[ 1 ] = portSYSTEM_PROGRAM_STATUS_WORD; /* PSW */ + pulUpperCSA[ 2 ] = ( uint32_t ) pxTopOfStack; /* A10; Stack Return aka Stack Pointer */ + pulUpperCSA[ 1 ] = portSYSTEM_PROGRAM_STATUS_WORD; /* PSW */ /* Clear the lower CSA. */ memset( pulLowerCSA, 0, portNUM_WORDS_IN_CSA * sizeof( uint32_t ) ); /* Lower Context. */ - pulLowerCSA[ 8 ] = ( uint32_t ) pvParameters; /* A4; Address Type Parameter Register */ - pulLowerCSA[ 1 ] = ( uint32_t ) pxCode; /* A11; Return Address aka RA */ + pulLowerCSA[ 8 ] = ( uint32_t ) pvParameters; /* A4; Address Type Parameter Register */ + pulLowerCSA[ 1 ] = ( uint32_t ) pxCode; /* A11; Return Address aka RA */ /* PCXI pointing to the Upper context. */ pulLowerCSA[ 0 ] = ( portINITIAL_PCXI_UPPER_CONTEXT_WORD | ( uint32_t ) portADDRESS_TO_CSA( pulUpperCSA ) ); /* Save the link to the CSA in the top of stack. */ - pxTopOfStack = (uint32_t * ) portADDRESS_TO_CSA( pulLowerCSA ); + pxTopOfStack = ( uint32_t * ) portADDRESS_TO_CSA( pulLowerCSA ); /* DSync to ensure that buffering is not a problem. */ _dsync(); @@ -180,13 +183,13 @@ uint32_t *pulLowerCSA = NULL; int32_t xPortStartScheduler( void ) { -extern void vTrapInstallHandlers( void ); -uint32_t ulMFCR = 0UL; -uint32_t *pulUpperCSA = NULL; -uint32_t *pulLowerCSA = NULL; + extern void vTrapInstallHandlers( void ); + uint32_t ulMFCR = 0UL; + uint32_t * pulUpperCSA = NULL; + uint32_t * pulLowerCSA = NULL; /* Interrupts at or below configMAX_SYSCALL_INTERRUPT_PRIORITY are disable - when this function is called. */ + * when this function is called. */ /* Set-up the timer interrupt. */ prvSetupTimerInterrupt(); @@ -202,8 +205,9 @@ uint32_t *pulLowerCSA = NULL; } /* Enable then install the priority 1 interrupt for pending context - switches from an ISR. See mod_SRC in the TriCore manual. */ - CPU_SRC0.reg = ( portENABLE_CPU_INTERRUPT ) | ( configKERNEL_YIELD_PRIORITY ); + * switches from an ISR. See mod_SRC in the TriCore manual. */ + CPU_SRC0.reg = ( portENABLE_CPU_INTERRUPT ) | ( configKERNEL_YIELD_PRIORITY ); + if( 0 == _install_int_handler( configKERNEL_YIELD_PRIORITY, prvInterruptYield, 0 ) ) { /* Failed to install the yield handler, force an assert. */ @@ -219,7 +223,7 @@ uint32_t *pulLowerCSA = NULL; /* ENDINIT has already been applied in the 'cstart.c' code. */ /* Clear the PSW.CDC to enable the use of an RFE without it generating an - exception because this code is not genuinely in an exception. */ + * exception because this code is not genuinely in an exception. */ ulMFCR = __MFCR( $PSW ); ulMFCR &= portRESTORE_PSW_MASK; _dsync(); @@ -228,7 +232,7 @@ uint32_t *pulLowerCSA = NULL; /* Finally, perform the equivalent of a portRESTORE_CONTEXT() */ pulLowerCSA = portCSA_TO_ADDRESS( ( *pxCurrentTCB ) ); - pulUpperCSA = portCSA_TO_ADDRESS( pulLowerCSA[0] ); + pulUpperCSA = portCSA_TO_ADDRESS( pulLowerCSA[ 0 ] ); _dsync(); _mtcr( $PCXI, *pxCurrentTCB ); _isync(); @@ -237,7 +241,7 @@ uint32_t *pulLowerCSA = NULL; _nop(); /* Return to the first task selected to execute. */ - __asm volatile( "rfe" ); + __asm volatile ( "rfe" ); /* Will not get here. */ return 0; @@ -250,7 +254,9 @@ static void prvSetupTimerInterrupt( void ) unlock_wdtcon(); { /* Wait until access to Endint protected register is enabled. */ - while( 0 != ( WDT_CON0.reg & 0x1UL ) ); + while( 0 != ( WDT_CON0.reg & 0x1UL ) ) + { + } /* RMC == 1 so STM Clock == FPI */ STM_CLC.reg = ( 1UL << 8 ); @@ -285,11 +291,11 @@ static void prvSetupTimerInterrupt( void ) static void prvSystemTickHandler( int iArg ) { -uint32_t ulSavedInterruptMask; -uint32_t *pxUpperCSA = NULL; -uint32_t xUpperCSA = 0UL; -extern volatile uint32_t *pxCurrentTCB; -int32_t lYieldRequired; + uint32_t ulSavedInterruptMask; + uint32_t * pxUpperCSA = NULL; + uint32_t xUpperCSA = 0UL; + extern volatile uint32_t * pxCurrentTCB; + int32_t lYieldRequired; /* Just to avoid compiler warnings about unused parameters. */ ( void ) iArg; @@ -298,22 +304,22 @@ int32_t lYieldRequired; STM_ISRR.reg = 1UL; /* Reload the Compare Match register for X ticks into the future. - - If critical section or interrupt nesting budgets are exceeded, then - it is possible that the calculated next compare match value is in the - past. If this occurs (unlikely), it is possible that the resulting - time slippage will exceed a single tick period. Any adverse effect of - this is time bounded by the fact that only the first n bits of the 56 bit - STM timer are being used for a compare match, so another compare match - will occur after an overflow in just those n bits (not the entire 56 bits). - As an example, if the peripheral clock is 75MHz, and the tick rate is 1KHz, - a missed tick could result in the next tick interrupt occurring within a - time that is 1.7 times the desired period. The fact that this is greater - than a single tick period is an effect of using a timer that cannot be - automatically reset, in hardware, by the occurrence of a tick interrupt. - Changing the tick source to a timer that has an automatic reset on compare - match (such as a GPTA timer) will reduce the maximum possible additional - period to exactly 1 times the desired period. */ + * + * If critical section or interrupt nesting budgets are exceeded, then + * it is possible that the calculated next compare match value is in the + * past. If this occurs (unlikely), it is possible that the resulting + * time slippage will exceed a single tick period. Any adverse effect of + * this is time bounded by the fact that only the first n bits of the 56 bit + * STM timer are being used for a compare match, so another compare match + * will occur after an overflow in just those n bits (not the entire 56 bits). + * As an example, if the peripheral clock is 75MHz, and the tick rate is 1KHz, + * a missed tick could result in the next tick interrupt occurring within a + * time that is 1.7 times the desired period. The fact that this is greater + * than a single tick period is an effect of using a timer that cannot be + * automatically reset, in hardware, by the occurrence of a tick interrupt. + * Changing the tick source to a timer that has an automatic reset on compare + * match (such as a GPTA timer) will reduce the maximum possible additional + * period to exactly 1 times the desired period. */ STM_CMP0.reg += ulCompareMatchValue; /* Kernel API calls require Critical Sections. */ @@ -327,24 +333,24 @@ int32_t lYieldRequired; if( lYieldRequired != pdFALSE ) { /* Save the context of a task. - The upper context is automatically saved when entering a trap or interrupt. - Need to save the lower context as well and copy the PCXI CSA ID into - pxCurrentTCB->pxTopOfStack. Only Lower Context CSA IDs may be saved to the - TCB of a task. - - Call vTaskSwitchContext to select the next task, note that this changes the - value of pxCurrentTCB so that it needs to be reloaded. - - Call vPortSetMPURegisterSetOne to change the MPU mapping for the task - that has just been switched in. - - Load the context of the task. - Need to restore the lower context by loading the CSA from - pxCurrentTCB->pxTopOfStack into PCXI (effectively changing the call stack). - In the Interrupt handler post-amble, RSLCX will restore the lower context - of the task. RFE will restore the upper context of the task, jump to the - return address and restore the previous state of interrupts being - enabled/disabled. */ + * The upper context is automatically saved when entering a trap or interrupt. + * Need to save the lower context as well and copy the PCXI CSA ID into + * pxCurrentTCB->pxTopOfStack. Only Lower Context CSA IDs may be saved to the + * TCB of a task. + * + * Call vTaskSwitchContext to select the next task, note that this changes the + * value of pxCurrentTCB so that it needs to be reloaded. + * + * Call vPortSetMPURegisterSetOne to change the MPU mapping for the task + * that has just been switched in. + * + * Load the context of the task. + * Need to restore the lower context by loading the CSA from + * pxCurrentTCB->pxTopOfStack into PCXI (effectively changing the call stack). + * In the Interrupt handler post-amble, RSLCX will restore the lower context + * of the task. RFE will restore the upper context of the task, jump to the + * return address and restore the previous state of interrupts being + * enabled/disabled. */ _disable(); _dsync(); xUpperCSA = __MFCR( $PCXI ); @@ -376,34 +382,34 @@ int32_t lYieldRequired; * than they can be freed assuming that tasks are being spawned and * deleted frequently. */ -void vPortReclaimCSA( uint32_t *pxTCB ) +void vPortReclaimCSA( uint32_t * pxTCB ) { -uint32_t pxHeadCSA, pxTailCSA, pxFreeCSA; -uint32_t *pulNextCSA; + uint32_t pxHeadCSA, pxTailCSA, pxFreeCSA; + uint32_t * pulNextCSA; /* A pointer to the first CSA in the list of CSAs consumed by the task is - stored in the first element of the tasks TCB structure (where the stack - pointer would be on a traditional stack based architecture). */ + * stored in the first element of the tasks TCB structure (where the stack + * pointer would be on a traditional stack based architecture). */ pxHeadCSA = ( *pxTCB ) & portCSA_FCX_MASK; /* Mask off everything in the CSA link field other than the address. If - the address is NULL, then the CSA is not linking anywhere and there is - nothing to do. */ + * the address is NULL, then the CSA is not linking anywhere and there is + * nothing to do. */ pxTailCSA = pxHeadCSA; /* Convert the link value to contain just a raw address and store this - in a local variable. */ + * in a local variable. */ pulNextCSA = portCSA_TO_ADDRESS( pxTailCSA ); /* Iterate over the CSAs that were consumed as part of the task. The - first field in the CSA is the pointer to then next CSA. Mask off - everything in the pointer to the next CSA, other than the link address. - If this is NULL, then the CSA currently being pointed to is the last in - the chain. */ + * first field in the CSA is the pointer to then next CSA. Mask off + * everything in the pointer to the next CSA, other than the link address. + * If this is NULL, then the CSA currently being pointed to is the last in + * the chain. */ while( 0UL != ( pulNextCSA[ 0 ] & portCSA_FCX_MASK ) ) { /* Clear all bits of the pointer to the next in the chain, other - than the address bits themselves. */ + * than the address bits themselves. */ pulNextCSA[ 0 ] = pulNextCSA[ 0 ] & portCSA_FCX_MASK; /* Move the pointer to point to the next CSA in the list. */ @@ -439,32 +445,33 @@ void vPortEndScheduler( void ) static void prvTrapYield( int iTrapIdentification ) { -uint32_t *pxUpperCSA = NULL; -uint32_t xUpperCSA = 0UL; -extern volatile uint32_t *pxCurrentTCB; + uint32_t * pxUpperCSA = NULL; + uint32_t xUpperCSA = 0UL; + extern volatile uint32_t * pxCurrentTCB; switch( iTrapIdentification ) { case portSYSCALL_TASK_YIELD: + /* Save the context of a task. - The upper context is automatically saved when entering a trap or interrupt. - Need to save the lower context as well and copy the PCXI CSA ID into - pxCurrentTCB->pxTopOfStack. Only Lower Context CSA IDs may be saved to the - TCB of a task. - - Call vTaskSwitchContext to select the next task, note that this changes the - value of pxCurrentTCB so that it needs to be reloaded. - - Call vPortSetMPURegisterSetOne to change the MPU mapping for the task - that has just been switched in. - - Load the context of the task. - Need to restore the lower context by loading the CSA from - pxCurrentTCB->pxTopOfStack into PCXI (effectively changing the call stack). - In the Interrupt handler post-amble, RSLCX will restore the lower context - of the task. RFE will restore the upper context of the task, jump to the - return address and restore the previous state of interrupts being - enabled/disabled. */ + * The upper context is automatically saved when entering a trap or interrupt. + * Need to save the lower context as well and copy the PCXI CSA ID into + * pxCurrentTCB->pxTopOfStack. Only Lower Context CSA IDs may be saved to the + * TCB of a task. + * + * Call vTaskSwitchContext to select the next task, note that this changes the + * value of pxCurrentTCB so that it needs to be reloaded. + * + * Call vPortSetMPURegisterSetOne to change the MPU mapping for the task + * that has just been switched in. + * + * Load the context of the task. + * Need to restore the lower context by loading the CSA from + * pxCurrentTCB->pxTopOfStack into PCXI (effectively changing the call stack). + * In the Interrupt handler post-amble, RSLCX will restore the lower context + * of the task. RFE will restore the upper context of the task, jump to the + * return address and restore the previous state of interrupts being + * enabled/disabled. */ _disable(); _dsync(); xUpperCSA = __MFCR( $PCXI ); @@ -486,32 +493,32 @@ extern volatile uint32_t *pxCurrentTCB; static void prvInterruptYield( int iId ) { -uint32_t *pxUpperCSA = NULL; -uint32_t xUpperCSA = 0UL; -extern volatile uint32_t *pxCurrentTCB; + uint32_t * pxUpperCSA = NULL; + uint32_t xUpperCSA = 0UL; + extern volatile uint32_t * pxCurrentTCB; /* Just to remove compiler warnings. */ ( void ) iId; /* Save the context of a task. - The upper context is automatically saved when entering a trap or interrupt. - Need to save the lower context as well and copy the PCXI CSA ID into - pxCurrentTCB->pxTopOfStack. Only Lower Context CSA IDs may be saved to the - TCB of a task. - - Call vTaskSwitchContext to select the next task, note that this changes the - value of pxCurrentTCB so that it needs to be reloaded. - - Call vPortSetMPURegisterSetOne to change the MPU mapping for the task - that has just been switched in. - - Load the context of the task. - Need to restore the lower context by loading the CSA from - pxCurrentTCB->pxTopOfStack into PCXI (effectively changing the call stack). - In the Interrupt handler post-amble, RSLCX will restore the lower context - of the task. RFE will restore the upper context of the task, jump to the - return address and restore the previous state of interrupts being - enabled/disabled. */ + * The upper context is automatically saved when entering a trap or interrupt. + * Need to save the lower context as well and copy the PCXI CSA ID into + * pxCurrentTCB->pxTopOfStack. Only Lower Context CSA IDs may be saved to the + * TCB of a task. + * + * Call vTaskSwitchContext to select the next task, note that this changes the + * value of pxCurrentTCB so that it needs to be reloaded. + * + * Call vPortSetMPURegisterSetOne to change the MPU mapping for the task + * that has just been switched in. + * + * Load the context of the task. + * Need to restore the lower context by loading the CSA from + * pxCurrentTCB->pxTopOfStack into PCXI (effectively changing the call stack). + * In the Interrupt handler post-amble, RSLCX will restore the lower context + * of the task. RFE will restore the upper context of the task, jump to the + * return address and restore the previous state of interrupts being + * enabled/disabled. */ _disable(); _dsync(); xUpperCSA = __MFCR( $PCXI ); @@ -526,7 +533,7 @@ extern volatile uint32_t *pxCurrentTCB; uint32_t uxPortSetInterruptMaskFromISR( void ) { -uint32_t uxReturn = 0UL; + uint32_t uxReturn = 0UL; _disable(); uxReturn = __MFCR( $ICR ); @@ -535,6 +542,6 @@ uint32_t uxReturn = 0UL; _enable(); /* Return just the interrupt mask bits. */ - return ( uxReturn & portCCPN_MASK ); + return( uxReturn & portCCPN_MASK ); } /*-----------------------------------------------------------*/ diff --git a/Source/portable/GCC/TriCore_1782/portmacro.h b/Source/portable/GCC/TriCore_1782/portmacro.h index 9dc74a6c8..89242e5a8 100644 --- a/Source/portable/GCC/TriCore_1782/portmacro.h +++ b/Source/portable/GCC/TriCore_1782/portmacro.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -50,126 +50,132 @@ */ /* Type definitions. */ -#define portCHAR char -#define portFLOAT float -#define portDOUBLE double -#define portLONG long -#define portSHORT short -#define portSTACK_TYPE uint32_t -#define portBASE_TYPE long - -typedef portSTACK_TYPE StackType_t; -typedef long BaseType_t; -typedef unsigned long UBaseType_t; - -#if( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS ) - typedef uint16_t TickType_t; - #define portMAX_DELAY ( TickType_t ) 0xffff +#define portCHAR char +#define portFLOAT float +#define portDOUBLE double +#define portLONG long +#define portSHORT short +#define portSTACK_TYPE uint32_t +#define portBASE_TYPE long + +typedef portSTACK_TYPE StackType_t; +typedef long BaseType_t; +typedef unsigned long UBaseType_t; + +#if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS ) + typedef uint16_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffff #elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS ) - typedef uint32_t TickType_t; - #define portMAX_DELAY ( TickType_t ) 0xffffffffUL + typedef uint32_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffffffffUL - /* 32-bit tick type on a 32-bit architecture, so reads of the tick count do - not need to be guarded with a critical section. */ - #define portTICK_TYPE_IS_ATOMIC 1 +/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do + * not need to be guarded with a critical section. */ + #define portTICK_TYPE_IS_ATOMIC 1 #else #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width. #endif /*---------------------------------------------------------------------------*/ /* Architecture specifics. */ -#define portSTACK_GROWTH ( -1 ) -#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) -#define portBYTE_ALIGNMENT 4 -#define portNOP() __asm volatile( " nop " ) -#define portCRITICAL_NESTING_IN_TCB 1 -#define portRESTORE_FIRST_TASK_PRIORITY_LEVEL 1 +#define portSTACK_GROWTH ( -1 ) +#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) +#define portBYTE_ALIGNMENT 4 +#define portNOP() __asm volatile ( " nop " ) +#define portCRITICAL_NESTING_IN_TCB 1 +#define portRESTORE_FIRST_TASK_PRIORITY_LEVEL 1 /*---------------------------------------------------------------------------*/ -typedef struct MPU_SETTINGS { uint32_t ulNotUsed; } xMPU_SETTINGS; +typedef struct MPU_SETTINGS +{ + uint32_t ulNotUsed; +} xMPU_SETTINGS; /* Define away the instruction from the Restore Context Macro. */ -#define portPRIVILEGE_BIT 0x0UL +#define portPRIVILEGE_BIT 0x0UL -#define portCCPN_MASK ( 0x000000FFUL ) +#define portCCPN_MASK ( 0x000000FFUL ) extern void vTaskEnterCritical( void ); extern void vTaskExitCritical( void ); -#define portENTER_CRITICAL() vTaskEnterCritical() -#define portEXIT_CRITICAL() vTaskExitCritical() +#define portENTER_CRITICAL() vTaskEnterCritical() +#define portEXIT_CRITICAL() vTaskExitCritical() /*---------------------------------------------------------------------------*/ /* CSA Manipulation. */ -#define portCSA_TO_ADDRESS( pCSA ) ( ( uint32_t * )( ( ( ( pCSA ) & 0x000F0000 ) << 12 ) | ( ( ( pCSA ) & 0x0000FFFF ) << 6 ) ) ) -#define portADDRESS_TO_CSA( pAddress ) ( ( uint32_t )( ( ( ( (uint32_t)( pAddress ) ) & 0xF0000000 ) >> 12 ) | ( ( ( uint32_t )( pAddress ) & 0x003FFFC0 ) >> 6 ) ) ) +#define portCSA_TO_ADDRESS( pCSA ) ( ( uint32_t * ) ( ( ( ( pCSA ) & 0x000F0000 ) << 12 ) | ( ( ( pCSA ) & 0x0000FFFF ) << 6 ) ) ) +#define portADDRESS_TO_CSA( pAddress ) ( ( uint32_t ) ( ( ( ( ( uint32_t ) ( pAddress ) ) & 0xF0000000 ) >> 12 ) | ( ( ( uint32_t ) ( pAddress ) & 0x003FFFC0 ) >> 6 ) ) ) /*---------------------------------------------------------------------------*/ -#define portYIELD() _syscall( 0 ) +#define portYIELD() _syscall( 0 ) /* Port Restore is implicit in the platform when the function is returned from the original PSW is automatically replaced. */ -#define portSYSCALL_TASK_YIELD 0 -#define portSYSCALL_RAISE_PRIORITY 1 +#define portSYSCALL_TASK_YIELD 0 +#define portSYSCALL_RAISE_PRIORITY 1 /*---------------------------------------------------------------------------*/ /* Critical section management. */ /* Set ICR.CCPN to configMAX_SYSCALL_INTERRUPT_PRIORITY. */ -#define portDISABLE_INTERRUPTS() { \ - uint32_t ulICR; \ - _disable(); \ - ulICR = __MFCR( $ICR ); /* Get current ICR value. */ \ - ulICR &= ~portCCPN_MASK; /* Clear down mask bits. */ \ - ulICR |= configMAX_SYSCALL_INTERRUPT_PRIORITY; /* Set mask bits to required priority mask. */ \ - _mtcr( $ICR, ulICR ); /* Write back updated ICR. */ \ - _isync(); \ - _enable(); \ - } +#define portDISABLE_INTERRUPTS() \ + { \ + uint32_t ulICR; \ + _disable(); \ + ulICR = __MFCR( $ICR ); /* Get current ICR value. */ \ + ulICR &= ~portCCPN_MASK; /* Clear down mask bits. */ \ + ulICR |= configMAX_SYSCALL_INTERRUPT_PRIORITY; /* Set mask bits to required priority mask. */ \ + _mtcr( $ICR, ulICR ); /* Write back updated ICR. */ \ + _isync(); \ + _enable(); \ + } /* Clear ICR.CCPN to allow all interrupt priorities. */ -#define portENABLE_INTERRUPTS() { \ - uint32_t ulICR; \ - _disable(); \ - ulICR = __MFCR( $ICR ); /* Get current ICR value. */ \ - ulICR &= ~portCCPN_MASK; /* Clear down mask bits. */ \ - _mtcr( $ICR, ulICR ); /* Write back updated ICR. */ \ - _isync(); \ - _enable(); \ - } +#define portENABLE_INTERRUPTS() \ + { \ + uint32_t ulICR; \ + _disable(); \ + ulICR = __MFCR( $ICR ); /* Get current ICR value. */ \ + ulICR &= ~portCCPN_MASK; /* Clear down mask bits. */ \ + _mtcr( $ICR, ulICR ); /* Write back updated ICR. */ \ + _isync(); \ + _enable(); \ + } /* Set ICR.CCPN to uxSavedMaskValue. */ -#define portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedMaskValue ) { \ - uint32_t ulICR; \ - _disable(); \ - ulICR = __MFCR( $ICR ); /* Get current ICR value. */ \ - ulICR &= ~portCCPN_MASK; /* Clear down mask bits. */ \ - ulICR |= uxSavedMaskValue; /* Set mask bits to previously saved mask value. */ \ - _mtcr( $ICR, ulICR ); /* Write back updated ICR. */ \ - _isync(); \ - _enable(); \ - } +#define portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedMaskValue ) \ + { \ + uint32_t ulICR; \ + _disable(); \ + ulICR = __MFCR( $ICR ); /* Get current ICR value. */ \ + ulICR &= ~portCCPN_MASK; /* Clear down mask bits. */ \ + ulICR |= uxSavedMaskValue; /* Set mask bits to previously saved mask value. */ \ + _mtcr( $ICR, ulICR ); /* Write back updated ICR. */ \ + _isync(); \ + _enable(); \ + } /* Set ICR.CCPN to configMAX_SYSCALL_INTERRUPT_PRIORITY */ extern uint32_t uxPortSetInterruptMaskFromISR( void ); -#define portSET_INTERRUPT_MASK_FROM_ISR() uxPortSetInterruptMaskFromISR() +#define portSET_INTERRUPT_MASK_FROM_ISR() uxPortSetInterruptMaskFromISR() /* Pend a priority 1 interrupt, which will take care of the context switch. */ -#define portYIELD_FROM_ISR( xHigherPriorityTaskWoken ) do { if( xHigherPriorityTaskWoken != pdFALSE ) { CPU_SRC0.bits.SETR = 1; _isync(); } } while( 0 ) +#define portYIELD_FROM_ISR( xHigherPriorityTaskWoken ) do { if( xHigherPriorityTaskWoken != pdFALSE ) { CPU_SRC0.bits.SETR = 1; _isync(); } } while( 0 ) /*---------------------------------------------------------------------------*/ /* Task function macros as described on the FreeRTOS.org WEB site. */ -#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters ) -#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters ) +#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters ) +#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters ) /*---------------------------------------------------------------------------*/ /* * Port specific clean up macro required to free the CSAs that were consumed by * a task that has since been deleted. */ -void vPortReclaimCSA( uint32_t *pxTCB ); -#define portCLEAN_UP_TCB( pxTCB ) vPortReclaimCSA( ( uint32_t * ) ( pxTCB ) ) +void vPortReclaimCSA( uint32_t * pxTCB ); +#define portCLEAN_UP_TCB( pxTCB ) vPortReclaimCSA( ( uint32_t * ) ( pxTCB ) ) /* *INDENT-OFF* */ #ifdef __cplusplus diff --git a/Source/portable/GCC/TriCore_1782/porttrap.c b/Source/portable/GCC/TriCore_1782/porttrap.c index a3acb88d5..19f0dc8e0 100644 --- a/Source/portable/GCC/TriCore_1782/porttrap.c +++ b/Source/portable/GCC/TriCore_1782/porttrap.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -38,7 +38,7 @@ /* * This reference is required by the Save/Restore Context Macros. */ -extern volatile uint32_t *pxCurrentTCB; +extern volatile uint32_t * pxCurrentTCB; /*-----------------------------------------------------------*/ /* @@ -51,57 +51,57 @@ extern volatile uint32_t *pxCurrentTCB; */ /* The Trap Classes. */ -#define portMMU_TRAP 0 -#define portIPT_TRAP 1 -#define portIE_TRAP 2 -#define portCM_TRAP 3 -#define portSBP_TRAP 4 -#define portASSERT_TRAP 5 -#define portNMI_TRAP 7 +#define portMMU_TRAP 0 +#define portIPT_TRAP 1 +#define portIE_TRAP 2 +#define portCM_TRAP 3 +#define portSBP_TRAP 4 +#define portASSERT_TRAP 5 +#define portNMI_TRAP 7 /* MMU Trap Identifications. */ -#define portTIN_MMU_VIRTUAL_ADDRESS_FILL 0 -#define portTIN_MMU_VIRTUAL_ADDRESS_PROTECTION 1 +#define portTIN_MMU_VIRTUAL_ADDRESS_FILL 0 +#define portTIN_MMU_VIRTUAL_ADDRESS_PROTECTION 1 /* Internal Protection Trap Identifications. */ -#define portTIN_IPT_PRIVILIGED_INSTRUCTION 1 -#define portTIN_IPT_MEMORY_PROTECTION_READ 2 -#define portTIN_IPT_MEMORY_PROTECTION_WRITE 3 -#define portTIN_IPT_MEMORY_PROTECTION_EXECUTION 4 -#define portTIN_IPT_MEMORY_PROTECTION_PERIPHERAL_ACCESS 5 -#define portTIN_IPT_MEMORY_PROTECTION_NULL_ADDRESS 6 -#define portTIN_IPT_MEMORY_PROTECTION_GLOBAL_REGISTER_WRITE_PROTECTION 7 +#define portTIN_IPT_PRIVILEGED_INSTRUCTION 1 +#define portTIN_IPT_MEMORY_PROTECTION_READ 2 +#define portTIN_IPT_MEMORY_PROTECTION_WRITE 3 +#define portTIN_IPT_MEMORY_PROTECTION_EXECUTION 4 +#define portTIN_IPT_MEMORY_PROTECTION_PERIPHERAL_ACCESS 5 +#define portTIN_IPT_MEMORY_PROTECTION_NULL_ADDRESS 6 +#define portTIN_IPT_MEMORY_PROTECTION_GLOBAL_REGISTER_WRITE_PROTECTION 7 /* Instruction Error Trap Identifications. */ -#define portTIN_IE_ILLEGAL_OPCODE 1 -#define portTIN_IE_UNIMPLEMENTED_OPCODE 2 -#define portTIN_IE_INVALID_OPERAND 3 -#define portTIN_IE_DATA_ADDRESS_ALIGNMENT 4 -#define portTIN_IE_INVALID_LOCAL_MEMORY_ADDRESS 5 +#define portTIN_IE_ILLEGAL_OPCODE 1 +#define portTIN_IE_UNIMPLEMENTED_OPCODE 2 +#define portTIN_IE_INVALID_OPERAND 3 +#define portTIN_IE_DATA_ADDRESS_ALIGNMENT 4 +#define portTIN_IE_INVALID_LOCAL_MEMORY_ADDRESS 5 /* Context Management Trap Identifications. */ -#define portTIN_CM_FREE_CONTEXT_LIST_DEPLETION 1 -#define portTIN_CM_CALL_DEPTH_OVERFLOW 2 -#define portTIN_CM_CALL_DEPTH_UNDEFLOW 3 -#define portTIN_CM_FREE_CONTEXT_LIST_UNDERFLOW 4 -#define portTIN_CM_CALL_STACK_UNDERFLOW 5 -#define portTIN_CM_CONTEXT_TYPE 6 -#define portTIN_CM_NESTING_ERROR 7 +#define portTIN_CM_FREE_CONTEXT_LIST_DEPLETION 1 +#define portTIN_CM_CALL_DEPTH_OVERFLOW 2 +#define portTIN_CM_CALL_DEPTH_UNDEFLOW 3 +#define portTIN_CM_FREE_CONTEXT_LIST_UNDERFLOW 4 +#define portTIN_CM_CALL_STACK_UNDERFLOW 5 +#define portTIN_CM_CONTEXT_TYPE 6 +#define portTIN_CM_NESTING_ERROR 7 /* System Bus and Peripherals Trap Identifications. */ -#define portTIN_SBP_PROGRAM_FETCH_SYNCHRONOUS_ERROR 1 -#define portTIN_SBP_DATA_ACCESS_SYNCHRONOUS_ERROR 2 -#define portTIN_SBP_DATA_ACCESS_ASYNCHRONOUS_ERROR 3 -#define portTIN_SBP_COPROCESSOR_TRAP_ASYNCHRONOUS_ERROR 4 -#define portTIN_SBP_PROGRAM_MEMORY_INTEGRITY_ERROR 5 -#define portTIN_SBP_DATA_MEMORY_INTEGRITY_ERROR 6 +#define portTIN_SBP_PROGRAM_FETCH_SYNCHRONOUS_ERROR 1 +#define portTIN_SBP_DATA_ACCESS_SYNCHRONOUS_ERROR 2 +#define portTIN_SBP_DATA_ACCESS_ASYNCHRONOUS_ERROR 3 +#define portTIN_SBP_COPROCESSOR_TRAP_ASYNCHRONOUS_ERROR 4 +#define portTIN_SBP_PROGRAM_MEMORY_INTEGRITY_ERROR 5 +#define portTIN_SBP_DATA_MEMORY_INTEGRITY_ERROR 6 /* Assertion Trap Identifications. */ -#define portTIN_ASSERT_ARITHMETIC_OVERFLOW 1 -#define portTIN_ASSERT_STICKY_ARITHMETIC_OVERFLOW 2 +#define portTIN_ASSERT_ARITHMETIC_OVERFLOW 1 +#define portTIN_ASSERT_STICKY_ARITHMETIC_OVERFLOW 2 /* Non-maskable Interrupt Trap Identifications. */ -#define portTIN_NMI_NON_MASKABLE_INTERRUPT 0 +#define portTIN_NMI_NON_MASKABLE_INTERRUPT 0 /*---------------------------------------------------------------------------*/ void vMMUTrap( int iTrapIdentification ) __attribute__( ( longcall, weak ) ); @@ -115,37 +115,37 @@ void vNonMaskableInterruptTrap( int iTrapIdentification ) __attribute__( ( longc void vTrapInstallHandlers( void ) { - if( 0 == _install_trap_handler ( portMMU_TRAP, vMMUTrap ) ) + if( 0 == _install_trap_handler( portMMU_TRAP, vMMUTrap ) ) { _debug(); } - if( 0 == _install_trap_handler ( portIPT_TRAP, vInternalProtectionTrap ) ) + if( 0 == _install_trap_handler( portIPT_TRAP, vInternalProtectionTrap ) ) { _debug(); } - if( 0 == _install_trap_handler ( portIE_TRAP, vInstructionErrorTrap ) ) + if( 0 == _install_trap_handler( portIE_TRAP, vInstructionErrorTrap ) ) { _debug(); } - if( 0 == _install_trap_handler ( portCM_TRAP, vContextManagementTrap ) ) + if( 0 == _install_trap_handler( portCM_TRAP, vContextManagementTrap ) ) { _debug(); } - if( 0 == _install_trap_handler ( portSBP_TRAP, vSystemBusAndPeripheralsTrap ) ) + if( 0 == _install_trap_handler( portSBP_TRAP, vSystemBusAndPeripheralsTrap ) ) { _debug(); } - if( 0 == _install_trap_handler ( portASSERT_TRAP, vAssertionTrap ) ) + if( 0 == _install_trap_handler( portASSERT_TRAP, vAssertionTrap ) ) { _debug(); } - if( 0 == _install_trap_handler ( portNMI_TRAP, vNonMaskableInterruptTrap ) ) + if( 0 == _install_trap_handler( portNMI_TRAP, vNonMaskableInterruptTrap ) ) { _debug(); } @@ -156,11 +156,11 @@ void vMMUTrap( int iTrapIdentification ) { switch( iTrapIdentification ) { - case portTIN_MMU_VIRTUAL_ADDRESS_FILL: - case portTIN_MMU_VIRTUAL_ADDRESS_PROTECTION: - default: - _debug(); - break; + case portTIN_MMU_VIRTUAL_ADDRESS_FILL: + case portTIN_MMU_VIRTUAL_ADDRESS_PROTECTION: + default: + _debug(); + break; } } /*---------------------------------------------------------------------------*/ @@ -170,26 +170,26 @@ void vInternalProtectionTrap( int iTrapIdentification ) /* Deliberate fall through to default. */ switch( iTrapIdentification ) { - case portTIN_IPT_PRIVILIGED_INSTRUCTION: - /* Instruction is not allowed at current execution level, eg DISABLE at User-0. */ + case portTIN_IPT_PRIVILEGED_INSTRUCTION: + /* Instruction is not allowed at current execution level, eg DISABLE at User-0. */ case portTIN_IPT_MEMORY_PROTECTION_READ: - /* Load word using invalid address. */ + /* Load word using invalid address. */ case portTIN_IPT_MEMORY_PROTECTION_WRITE: - /* Store Word using invalid address. */ + /* Store Word using invalid address. */ case portTIN_IPT_MEMORY_PROTECTION_EXECUTION: - /* PC jumped to an address outside of the valid range. */ + /* PC jumped to an address outside of the valid range. */ case portTIN_IPT_MEMORY_PROTECTION_PERIPHERAL_ACCESS: - /* Access to a peripheral denied at current execution level. */ + /* Access to a peripheral denied at current execution level. */ case portTIN_IPT_MEMORY_PROTECTION_NULL_ADDRESS: - /* NULL Pointer. */ + /* NULL Pointer. */ case portTIN_IPT_MEMORY_PROTECTION_GLOBAL_REGISTER_WRITE_PROTECTION: - /* Tried to modify a global address pointer register. */ + /* Tried to modify a global address pointer register. */ default: diff --git a/Source/portable/IAR/78K0R/ISR_Support.h b/Source/portable/IAR/78K0R/ISR_Support.h index abee1e6e0..00165542d 100644 --- a/Source/portable/IAR/78K0R/ISR_Support.h +++ b/Source/portable/IAR/78K0R/ISR_Support.h @@ -1,83 +1,112 @@ -;/* -; * FreeRTOS Kernel V10.6.2 -; * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. -; * -; * SPDX-License-Identifier: MIT -; * -; * Permission is hereby granted, free of charge, to any person obtaining a copy of -; * this software and associated documentation files (the "Software"), to deal in -; * the Software without restriction, including without limitation the rights to -; * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of -; * the Software, and to permit persons to whom the Software is furnished to do so, -; * subject to the following conditions: -; * -; * The above copyright notice and this permission notice shall be included in all -; * copies or substantial portions of the Software. -; * -; * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -; * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS -; * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR -; * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER -; * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN -; * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. -; * -; * https://www.FreeRTOS.org -; * https://github.com/FreeRTOS -; * -; */ +; /* + * ; * FreeRTOS Kernel V11.0.1 + * ; * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * ; * + * ; * SPDX-License-Identifier: MIT + * ; * + * ; * Permission is hereby granted, free of charge, to any person obtaining a copy of + * ; * this software and associated documentation files (the "Software"), to deal in + * ; * the Software without restriction, including without limitation the rights to + * ; * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * ; * the Software, and to permit persons to whom the Software is furnished to do so, + * ; * subject to the following conditions: + * ; * + * ; * The above copyright notice and this permission notice shall be included in all + * ; * copies or substantial portions of the Software. + * ; * + * ; * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * ; * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * ; * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * ; * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * ; * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * ; * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * ; * + * ; * https://www.FreeRTOS.org + * ; * https://github.com/FreeRTOS + * ; * + * ; */ #include "FreeRTOSConfig.h" -; Variables used by scheduler -;------------------------------------------------------------------------------ - EXTERN pxCurrentTCB - EXTERN usCriticalNesting +; +Variables used by scheduler +; +------------------------------------------------------------------------------ +EXTERN pxCurrentTCB +EXTERN usCriticalNesting -;------------------------------------------------------------------------------ -; portSAVE_CONTEXT MACRO -; Saves the context of the general purpose registers, CS and ES (only in far -; memory mode) registers the usCriticalNesting Value and the Stack Pointer -; of the active Task onto the task stack -;------------------------------------------------------------------------------ +; +------------------------------------------------------------------------------ +; +portSAVE_CONTEXT MACRO +; +Saves the context of the general purpose registers, CS and ES( only in far + ; + memory mode ) registers the usCriticalNesting Value and the Stack Pointer +; +of the active Task onto the task stack +; +------------------------------------------------------------------------------ portSAVE_CONTEXT MACRO - PUSH AX ; Save AX Register to stack. - PUSH HL - MOV A, CS ; Save CS register. - XCH A, X - MOV A, ES ; Save ES register. - PUSH AX - PUSH DE ; Save the remaining general purpose registers. - PUSH BC - MOVW AX, usCriticalNesting ; Save the usCriticalNesting value. - PUSH AX - MOVW AX, pxCurrentTCB ; Save the Stack pointer. - MOVW HL, AX - MOVW AX, SP - MOVW [HL], AX - ENDM -;------------------------------------------------------------------------------ +PUSH AX; +Save AX Register to stack. + PUSH HL +MOV A, CS; +Save CS register. + XCH A, X +MOV A, ES; +Save ES register. + PUSH AX +PUSH DE; +Save the remaining general purpose registers. + PUSH BC +MOVW AX, usCriticalNesting; +Save the usCriticalNesting value. + PUSH AX +MOVW AX, pxCurrentTCB; +Save the Stack pointer. + MOVW HL, AX +MOVW AX, SP + MOVW[ HL ], AX + ENDM +; +------------------------------------------------------------------------------ -;------------------------------------------------------------------------------ -; portRESTORE_CONTEXT MACRO -; Restores the task Stack Pointer then use this to restore usCriticalNesting, -; general purpose registers and the CS and ES (only in far memory mode) -; of the selected task from the task stack -;------------------------------------------------------------------------------ +; +------------------------------------------------------------------------------ +; +portRESTORE_CONTEXT MACRO +; +Restores the task Stack Pointer then use this to restore usCriticalNesting, +; +general purpose registers and the CS and ES( only in far memory mode ) +; +of the selected task from the task stack +; +------------------------------------------------------------------------------ portRESTORE_CONTEXT MACRO - MOVW AX, pxCurrentTCB ; Restore the Stack pointer. - MOVW HL, AX - MOVW AX, [HL] - MOVW SP, AX - POP AX ; Restore usCriticalNesting value. - MOVW usCriticalNesting, AX - POP BC ; Restore the necessary general purpose registers. - POP DE - POP AX ; Restore the ES register. - MOV ES, A - XCH A, X ; Restore the CS register. - MOV CS, A - POP HL ; Restore general purpose register HL. - POP AX ; Restore AX. - ENDM -;------------------------------------------------------------------------------ +MOVW AX, pxCurrentTCB; +Restore the Stack pointer. + MOVW HL, AX +MOVW AX, [ HL ] +MOVW SP, AX +POP AX; +Restore usCriticalNesting value. + MOVW usCriticalNesting, AX +POP BC; +Restore the necessary general purpose registers. + POP DE +POP AX; +Restore the ES register. + MOV ES, A +XCH A, X; +Restore the CS register. + MOV CS, A +POP HL; +Restore general purpose register HL. + POP AX; +Restore AX. + ENDM +; +------------------------------------------------------------------------------ diff --git a/Source/portable/IAR/78K0R/port.c b/Source/portable/IAR/78K0R/port.c index 1d8bb9d17..928bc3de9 100644 --- a/Source/portable/IAR/78K0R/port.c +++ b/Source/portable/IAR/78K0R/port.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -34,8 +34,8 @@ #include "task.h" /* The critical nesting value is initialised to a non zero value to ensure -interrupts don't accidentally become enabled before the scheduler is started. */ -#define portINITIAL_CRITICAL_NESTING (( uint16_t ) 10) + * interrupts don't accidentally become enabled before the scheduler is started. */ +#define portINITIAL_CRITICAL_NESTING ( ( uint16_t ) 10 ) /* Initial PSW value allocated to a newly created task. * 1100011000000000 @@ -48,25 +48,25 @@ interrupts don't accidentally become enabled before the scheduler is started. */ * |--------------------- Zero Flag set * ---------------------- Global Interrupt Flag set (enabled) */ -#define portPSW (0xc6UL) +#define portPSW ( 0xc6UL ) /* We require the address of the pxCurrentTCB variable, but don't want to know -any details of its type. */ + * any details of its type. */ typedef void TCB_t; extern volatile TCB_t * volatile pxCurrentTCB; /* Most ports implement critical sections by placing the interrupt flags on -the stack before disabling interrupts. Exiting the critical section is then -simply a case of popping the flags from the stack. As 78K0 IAR does not use -a frame pointer this cannot be done as modifying the stack will clobber all -the stack variables. Instead each task maintains a count of the critical -section nesting depth. Each time a critical section is entered the count is -incremented. Each time a critical section is left the count is decremented - -with interrupts only being re-enabled if the count is zero. - -usCriticalNesting will get set to zero when the scheduler starts, but must -not be initialised to zero as this will cause problems during the startup -sequence. */ + * the stack before disabling interrupts. Exiting the critical section is then + * simply a case of popping the flags from the stack. As 78K0 IAR does not use + * a frame pointer this cannot be done as modifying the stack will clobber all + * the stack variables. Instead each task maintains a count of the critical + * section nesting depth. Each time a critical section is entered the count is + * incremented. Each time a critical section is left the count is decremented - + * with interrupts only being re-enabled if the count is zero. + * + * usCriticalNesting will get set to zero when the scheduler starts, but must + * not be initialised to zero as this will cause problems during the startup + * sequence. */ volatile uint16_t usCriticalNesting = portINITIAL_CRITICAL_NESTING; /*-----------------------------------------------------------*/ @@ -82,30 +82,32 @@ static void prvSetupTimerInterrupt( void ); * * See the header file portable.h. */ -StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters ) +StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, + TaskFunction_t pxCode, + void * pvParameters ) { -uint32_t *pulLocal; + uint32_t * pulLocal; #if configMEMORY_MODE == 1 { /* Parameters are passed in on the stack, and written using a 32bit value - hence a space is left for the second two bytes. */ + * hence a space is left for the second two bytes. */ pxTopOfStack--; /* Write in the parameter value. */ - pulLocal = ( uint32_t * ) pxTopOfStack; + pulLocal = ( uint32_t * ) pxTopOfStack; *pulLocal = ( uint32_t ) pvParameters; pxTopOfStack--; /* These values are just spacers. The return address of the function - would normally be written here. */ + * would normally be written here. */ *pxTopOfStack = ( StackType_t ) 0xcdcd; pxTopOfStack--; *pxTopOfStack = ( StackType_t ) 0xcdcd; pxTopOfStack--; /* The start address / PSW value is also written in as a 32bit value, - so leave a space for the second two bytes. */ + * so leave a space for the second two bytes. */ pxTopOfStack--; /* Task function start address combined with the PSW. */ @@ -117,11 +119,11 @@ uint32_t *pulLocal; *pxTopOfStack = ( StackType_t ) 0x1111; pxTopOfStack--; } - #else + #else /* if configMEMORY_MODE == 1 */ { /* Task function address is written to the stack first. As it is - written as a 32bit value a space is left on the stack for the second - two bytes. */ + * written as a 32bit value a space is left on the stack for the second + * two bytes. */ pxTopOfStack--; /* Task function start address combined with the PSW. */ @@ -133,7 +135,7 @@ uint32_t *pulLocal; *pxTopOfStack = ( StackType_t ) pvParameters; pxTopOfStack--; } - #endif + #endif /* if configMEMORY_MODE == 1 */ /* An initial value for the HL register. */ *pxTopOfStack = ( StackType_t ) 0x2222; @@ -150,11 +152,11 @@ uint32_t *pulLocal; pxTopOfStack--; /* Finally the critical section nesting count is set to zero when the task - first starts. */ + * first starts. */ *pxTopOfStack = ( StackType_t ) portNO_CRITICAL_SECTION_NESTING; /* Return a pointer to the top of the stack we have generated so this can - be stored in the task control block for the task. */ + * be stored in the task control block for the task. */ return pxTopOfStack; } /*-----------------------------------------------------------*/ @@ -162,7 +164,7 @@ uint32_t *pulLocal; BaseType_t xPortStartScheduler( void ) { /* Setup the hardware to generate the tick. Interrupts are disabled when - this function is called. */ + * this function is called. */ prvSetupTimerInterrupt(); /* Restore the context of the first task that is going to run. */ @@ -176,7 +178,7 @@ BaseType_t xPortStartScheduler( void ) void vPortEndScheduler( void ) { /* It is unlikely that the 78K0R port will get stopped. If required simply - disable the tick interrupt here. */ + * disable the tick interrupt here. */ } /*-----------------------------------------------------------*/ @@ -191,7 +193,7 @@ static void prvSetupTimerInterrupt( void ) TT0 = 0xff; /* Interrupt of Timer Array Unit Channel 5 is disabled to set the interrupt - priority. */ + * priority. */ TMMK05 = 1; /* Clear Timer Array Unit Channel 5 interrupt flag. */ diff --git a/Source/portable/IAR/78K0R/portasm.s26 b/Source/portable/IAR/78K0R/portasm.s26 index 69a4501d4..274cb423c 100644 --- a/Source/portable/IAR/78K0R/portasm.s26 +++ b/Source/portable/IAR/78K0R/portasm.s26 @@ -1,5 +1,5 @@ ;/* -; * FreeRTOS Kernel V10.6.2 +; * FreeRTOS Kernel V11.0.1 ; * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. ; * ; * SPDX-License-Identifier: MIT diff --git a/Source/portable/IAR/78K0R/portmacro.h b/Source/portable/IAR/78K0R/portmacro.h index 23e1856c1..46189737f 100644 --- a/Source/portable/IAR/78K0R/portmacro.h +++ b/Source/portable/IAR/78K0R/portmacro.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -47,100 +47,100 @@ /* Type definitions. */ -#define portCHAR char -#define portFLOAT float -#define portDOUBLE double -#define portLONG long -#define portSHORT short -#define portSTACK_TYPE uint16_t -#define portBASE_TYPE short +#define portCHAR char +#define portFLOAT float +#define portDOUBLE double +#define portLONG long +#define portSHORT short +#define portSTACK_TYPE uint16_t +#define portBASE_TYPE short -typedef portSTACK_TYPE StackType_t; -typedef short BaseType_t; -typedef unsigned short UBaseType_t; +typedef portSTACK_TYPE StackType_t; +typedef short BaseType_t; +typedef unsigned short UBaseType_t; #if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS ) - typedef unsigned int TickType_t; - #define portMAX_DELAY ( TickType_t ) 0xffff + typedef unsigned int TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffff #elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS ) - typedef uint32_t TickType_t; - #define portMAX_DELAY ( TickType_t ) ( 0xFFFFFFFFUL ) + typedef uint32_t TickType_t; + #define portMAX_DELAY ( TickType_t ) ( 0xFFFFFFFFUL ) #else #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width. #endif /*-----------------------------------------------------------*/ /* Interrupt control macros. */ -#define portDISABLE_INTERRUPTS() __asm ( "DI" ) -#define portENABLE_INTERRUPTS() __asm ( "EI" ) +#define portDISABLE_INTERRUPTS() __asm( "DI" ) +#define portENABLE_INTERRUPTS() __asm( "EI" ) /*-----------------------------------------------------------*/ /* Critical section control macros. */ -#define portNO_CRITICAL_SECTION_NESTING ( ( uint16_t ) 0 ) - -#define portENTER_CRITICAL() \ -{ \ -extern volatile uint16_t usCriticalNesting; \ - \ - portDISABLE_INTERRUPTS(); \ - \ - /* Now interrupts are disabled ulCriticalNesting can be accessed */ \ - /* directly. Increment ulCriticalNesting to keep a count of how many */ \ - /* times portENTER_CRITICAL() has been called. */ \ - usCriticalNesting++; \ -} - -#define portEXIT_CRITICAL() \ -{ \ -extern volatile uint16_t usCriticalNesting; \ - \ - if( usCriticalNesting > portNO_CRITICAL_SECTION_NESTING ) \ - { \ - /* Decrement the nesting count as we are leaving a critical section. */ \ - usCriticalNesting--; \ - \ - /* If the nesting level has reached zero then interrupts should be */ \ - /* re-enabled. */ \ - if( usCriticalNesting == portNO_CRITICAL_SECTION_NESTING ) \ - { \ - portENABLE_INTERRUPTS(); \ - } \ - } \ -} +#define portNO_CRITICAL_SECTION_NESTING ( ( uint16_t ) 0 ) + +#define portENTER_CRITICAL() \ + { \ + extern volatile uint16_t usCriticalNesting; \ + \ + portDISABLE_INTERRUPTS(); \ + \ + /* Now that interrupts are disabled, ulCriticalNesting can be accessed */ \ + /* directly. Increment ulCriticalNesting to keep a count of how many */ \ + /* times portENTER_CRITICAL() has been called. */ \ + usCriticalNesting++; \ + } + +#define portEXIT_CRITICAL() \ + { \ + extern volatile uint16_t usCriticalNesting; \ + \ + if( usCriticalNesting > portNO_CRITICAL_SECTION_NESTING ) \ + { \ + /* Decrement the nesting count as we are leaving a critical section. */ \ + usCriticalNesting--; \ + \ + /* If the nesting level has reached zero then interrupts should be */ \ + /* re-enabled. */ \ + if( usCriticalNesting == portNO_CRITICAL_SECTION_NESTING ) \ + { \ + portENABLE_INTERRUPTS(); \ + } \ + } \ + } /*-----------------------------------------------------------*/ /* Task utilities. */ extern void vPortStart( void ); -#define portYIELD() __asm( "BRK" ) -#define portYIELD_FROM_ISR( xHigherPriorityTaskWoken ) do { if( xHigherPriorityTaskWoken ) vTaskSwitchContext(); } while( 0 ) -#define portNOP() __asm( "NOP" ) +#define portYIELD() __asm( "BRK" ) +#define portYIELD_FROM_ISR( xHigherPriorityTaskWoken ) do { if( xHigherPriorityTaskWoken ) vTaskSwitchContext( ); } while( 0 ) +#define portNOP() __asm( "NOP" ) /*-----------------------------------------------------------*/ -/* Hardwware specifics. */ -#define portBYTE_ALIGNMENT 2 -#define portSTACK_GROWTH ( -1 ) -#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) +/* Hardware specifics. */ +#define portBYTE_ALIGNMENT 2 +#define portSTACK_GROWTH ( -1 ) +#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) /*-----------------------------------------------------------*/ /* Task function macros as described on the FreeRTOS.org WEB site. */ -#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters ) -#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters ) +#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters ) +#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters ) -static __interrupt void P0_isr (void); +static __interrupt void P0_isr( void ); /* --------------------------------------------------------------------------*/ /* Option-bytes and security ID */ /* --------------------------------------------------------------------------*/ -#define OPT_BYTES_SIZE 4 -#define SECU_ID_SIZE 10 -#define WATCHDOG_DISABLED 0x00 -#define LVI_ENABLED 0xFE -#define LVI_DISABLED 0xFF -#define RESERVED_FF 0xFF -#define OCD_DISABLED 0x04 -#define OCD_ENABLED 0x81 -#define OCD_ENABLED_ERASE 0x80 +#define OPT_BYTES_SIZE 4 +#define SECU_ID_SIZE 10 +#define WATCHDOG_DISABLED 0x00 +#define LVI_ENABLED 0xFE +#define LVI_DISABLED 0xFF +#define RESERVED_FF 0xFF +#define OCD_DISABLED 0x04 +#define OCD_ENABLED 0x81 +#define OCD_ENABLED_ERASE 0x80 /* *INDENT-OFF* */ #ifdef __cplusplus diff --git a/Source/portable/IAR/ARM_CA5_No_GIC/port.c b/Source/portable/IAR/ARM_CA5_No_GIC/port.c index bd4d324d0..e81475091 100644 --- a/Source/portable/IAR/ARM_CA5_No_GIC/port.c +++ b/Source/portable/IAR/ARM_CA5_No_GIC/port.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -35,7 +35,7 @@ #if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 /* Check the configuration. */ - #if( configMAX_PRIORITIES > 32 ) + #if ( configMAX_PRIORITIES > 32 ) #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice. #endif #endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */ @@ -49,27 +49,27 @@ #endif /* A critical section is exited when the critical section nesting count reaches -this value. */ -#define portNO_CRITICAL_NESTING ( ( uint32_t ) 0 ) + * this value. */ +#define portNO_CRITICAL_NESTING ( ( uint32_t ) 0 ) /* Tasks are not created with a floating point context, but can be given a -floating point context after they have been created. A variable is stored as -part of the tasks context that holds portNO_FLOATING_POINT_CONTEXT if the task -does not have an FPU context, or any other value if the task does have an FPU -context. */ -#define portNO_FLOATING_POINT_CONTEXT ( ( StackType_t ) 0 ) + * floating point context after they have been created. A variable is stored as + * part of the tasks context that holds portNO_FLOATING_POINT_CONTEXT if the task + * does not have an FPU context, or any other value if the task does have an FPU + * context. */ +#define portNO_FLOATING_POINT_CONTEXT ( ( StackType_t ) 0 ) /* Constants required to setup the initial task context. */ -#define portINITIAL_SPSR ( ( StackType_t ) 0x1f ) /* System mode, ARM mode, interrupts enabled. */ -#define portTHUMB_MODE_BIT ( ( StackType_t ) 0x20 ) -#define portTHUMB_MODE_ADDRESS ( 0x01UL ) +#define portINITIAL_SPSR ( ( StackType_t ) 0x1f ) /* System mode, ARM mode, interrupts enabled. */ +#define portTHUMB_MODE_BIT ( ( StackType_t ) 0x20 ) +#define portTHUMB_MODE_ADDRESS ( 0x01UL ) /* Masks all bits in the APSR other than the mode bits. */ -#define portAPSR_MODE_BITS_MASK ( 0x1F ) +#define portAPSR_MODE_BITS_MASK ( 0x1F ) /* The value of the mode bits in the APSR when the CPU is executing in user -mode. */ -#define portAPSR_USER_MODE ( 0x10 ) + * mode. */ +#define portAPSR_USER_MODE ( 0x10 ) /*-----------------------------------------------------------*/ @@ -87,21 +87,21 @@ static void prvTaskExitError( void ); /*-----------------------------------------------------------*/ /* A variable is used to keep track of the critical section nesting. This -variable has to be stored as part of the task context and must be initialised to -a non zero value to ensure interrupts don't inadvertently become unmasked before -the scheduler starts. As it is stored as part of the task context it will -automatically be set to 0 when the first task is started. */ + * variable has to be stored as part of the task context and must be initialised to + * a non zero value to ensure interrupts don't inadvertently become unmasked before + * the scheduler starts. As it is stored as part of the task context it will + * automatically be set to 0 when the first task is started. */ volatile uint32_t ulCriticalNesting = 9999UL; /* Saved as part of the task context. If ulPortTaskHasFPUContext is non-zero -then a floating point context must be saved and restored for the task. */ + * then a floating point context must be saved and restored for the task. */ uint32_t ulPortTaskHasFPUContext = pdFALSE; /* Set to 1 to pend a context switch from an ISR. */ uint32_t ulPortYieldRequired = pdFALSE; /* Counts the interrupt nesting depth. A context switch is only performed if -if the nesting depth is 0. */ + * if the nesting depth is 0. */ uint32_t ulPortInterruptNesting = 0UL; @@ -110,14 +110,16 @@ uint32_t ulPortInterruptNesting = 0UL; /* * See header file for description. */ -StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters ) +StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, + TaskFunction_t pxCode, + void * pvParameters ) { /* Setup the initial stack of the task. The stack is set exactly as - expected by the portRESTORE_CONTEXT() macro. - - The fist real value on the stack is the status register, which is set for - system mode, with interrupts enabled. A few NULLs are added first to ensure - GDB does not try decoding a non-existent return address. */ + * expected by the portRESTORE_CONTEXT() macro. + * + * The fist real value on the stack is the status register, which is set for + * system mode, with interrupts enabled. A few NULLs are added first to ensure + * GDB does not try decoding a non-existent return address. */ *pxTopOfStack = NULL; pxTopOfStack--; *pxTopOfStack = NULL; @@ -139,43 +141,43 @@ StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t px pxTopOfStack--; /* Next all the registers other than the stack pointer. */ - *pxTopOfStack = ( StackType_t ) prvTaskExitError; /* R14 */ + *pxTopOfStack = ( StackType_t ) prvTaskExitError; /* R14 */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x12121212; /* R12 */ + *pxTopOfStack = ( StackType_t ) 0x12121212; /* R12 */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x11111111; /* R11 */ + *pxTopOfStack = ( StackType_t ) 0x11111111; /* R11 */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x10101010; /* R10 */ + *pxTopOfStack = ( StackType_t ) 0x10101010; /* R10 */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x09090909; /* R9 */ + *pxTopOfStack = ( StackType_t ) 0x09090909; /* R9 */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x08080808; /* R8 */ + *pxTopOfStack = ( StackType_t ) 0x08080808; /* R8 */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x07070707; /* R7 */ + *pxTopOfStack = ( StackType_t ) 0x07070707; /* R7 */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x06060606; /* R6 */ + *pxTopOfStack = ( StackType_t ) 0x06060606; /* R6 */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x05050505; /* R5 */ + *pxTopOfStack = ( StackType_t ) 0x05050505; /* R5 */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x04040404; /* R4 */ + *pxTopOfStack = ( StackType_t ) 0x04040404; /* R4 */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x03030303; /* R3 */ + *pxTopOfStack = ( StackType_t ) 0x03030303; /* R3 */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x02020202; /* R2 */ + *pxTopOfStack = ( StackType_t ) 0x02020202; /* R2 */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x01010101; /* R1 */ + *pxTopOfStack = ( StackType_t ) 0x01010101; /* R1 */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */ + *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */ pxTopOfStack--; /* The task will start with a critical nesting count of 0 as interrupts are - enabled. */ + * enabled. */ *pxTopOfStack = portNO_CRITICAL_NESTING; pxTopOfStack--; /* The task will start without a floating point context. A task that uses - the floating point hardware must call vPortTaskUsesFPU() before executing - any floating point instructions. */ + * the floating point hardware must call vPortTaskUsesFPU() before executing + * any floating point instructions. */ *pxTopOfStack = portNO_FLOATING_POINT_CONTEXT; return pxTopOfStack; @@ -185,24 +187,28 @@ StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t px static void prvTaskExitError( void ) { /* A function that implements a task must not exit or attempt to return to - its caller as there is nothing to return to. If a task wants to exit it - should instead call vTaskDelete( NULL ). - - Artificially force an assert() to be triggered if configASSERT() is - defined, then stop here so application writers can catch the error. */ + * its caller as there is nothing to return to. If a task wants to exit it + * should instead call vTaskDelete( NULL ). + * + * Artificially force an assert() to be triggered if configASSERT() is + * defined, then stop here so application writers can catch the error. */ configASSERT( ulPortInterruptNesting == ~0UL ); portDISABLE_INTERRUPTS(); - for( ;; ); + + for( ; ; ) + { + } } /*-----------------------------------------------------------*/ BaseType_t xPortStartScheduler( void ) { -uint32_t ulAPSR; + uint32_t ulAPSR; /* Only continue if the CPU is not in User mode. The CPU must be in a - Privileged mode for the scheduler to start. */ + * Privileged mode for the scheduler to start. */ __asm volatile ( "MRS %0, APSR" : "=r" ( ulAPSR ) ); + ulAPSR &= portAPSR_MODE_BITS_MASK; configASSERT( ulAPSR != portAPSR_USER_MODE ); @@ -214,8 +220,8 @@ uint32_t ulAPSR; } /* Will only get here if vTaskStartScheduler() was called with the CPU in - a non-privileged mode or the binary point register was not set to its lowest - possible value. */ + * a non-privileged mode or the binary point register was not set to its lowest + * possible value. */ return 0; } /*-----------------------------------------------------------*/ @@ -223,7 +229,7 @@ uint32_t ulAPSR; void vPortEndScheduler( void ) { /* Not implemented in ports where there is nothing to return to. - Artificially force an assert. */ + * Artificially force an assert. */ configASSERT( ulCriticalNesting == 1000UL ); } /*-----------------------------------------------------------*/ @@ -232,16 +238,16 @@ void vPortEnterCritical( void ) { portDISABLE_INTERRUPTS(); - /* Now interrupts are disabled ulCriticalNesting can be accessed - directly. Increment ulCriticalNesting to keep a count of how many times - portENTER_CRITICAL() has been called. */ + /* Now that interrupts are disabled, ulCriticalNesting can be accessed + * directly. Increment ulCriticalNesting to keep a count of how many times + * portENTER_CRITICAL() has been called. */ ulCriticalNesting++; /* This is not the interrupt safe version of the enter critical function so - assert() if it is being called from an interrupt context. Only API - functions that end in "FromISR" can be used in an interrupt. Only assert if - the critical nesting count is 1 to protect against recursive calls if the - assert function also uses a critical section. */ + * assert() if it is being called from an interrupt context. Only API + * functions that end in "FromISR" can be used in an interrupt. Only assert if + * the critical nesting count is 1 to protect against recursive calls if the + * assert function also uses a critical section. */ if( ulCriticalNesting == 1 ) { configASSERT( ulPortInterruptNesting == 0 ); @@ -254,15 +260,15 @@ void vPortExitCritical( void ) if( ulCriticalNesting > portNO_CRITICAL_NESTING ) { /* Decrement the nesting count as the critical section is being - exited. */ + * exited. */ ulCriticalNesting--; /* If the nesting level has reached zero then all interrupt - priorities must be re-enabled. */ + * priorities must be re-enabled. */ if( ulCriticalNesting == portNO_CRITICAL_NESTING ) { /* Critical nesting has reached zero so all interrupt priorities - should be unmasked. */ + * should be unmasked. */ portENABLE_INTERRUPTS(); } } @@ -286,13 +292,13 @@ void FreeRTOS_Tick_Handler( void ) void vPortTaskUsesFPU( void ) { -uint32_t ulInitialFPSCR = 0; + uint32_t ulInitialFPSCR = 0; /* A task is registering the fact that it needs an FPU context. Set the - FPU flag (which is saved as part of the task context). */ + * FPU flag (which is saved as part of the task context). */ ulPortTaskHasFPUContext = pdTRUE; /* Initialise the floating point status register. */ - __asm( "FMXR FPSCR, %0" :: "r" (ulInitialFPSCR) ); + __asm( "FMXR FPSCR, %0" ::"r" ( ulInitialFPSCR ) ); } /*-----------------------------------------------------------*/ diff --git a/Source/portable/IAR/ARM_CA5_No_GIC/portASM.h b/Source/portable/IAR/ARM_CA5_No_GIC/portASM.h index dc299e727..65e792a3b 100644 --- a/Source/portable/IAR/ARM_CA5_No_GIC/portASM.h +++ b/Source/portable/IAR/ARM_CA5_No_GIC/portASM.h @@ -1,109 +1,158 @@ -;/* -; * FreeRTOS Kernel V10.6.2 -; * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. -; * -; * SPDX-License-Identifier: MIT -; * -; * Permission is hereby granted, free of charge, to any person obtaining a copy of -; * this software and associated documentation files (the "Software"), to deal in -; * the Software without restriction, including without limitation the rights to -; * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of -; * the Software, and to permit persons to whom the Software is furnished to do so, -; * subject to the following conditions: -; * -; * The above copyright notice and this permission notice shall be included in all -; * copies or substantial portions of the Software. -; * -; * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -; * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS -; * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR -; * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER -; * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN -; * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. -; * -; * https://www.FreeRTOS.org -; * https://github.com/FreeRTOS -; * -; */ - - EXTERN vTaskSwitchContext - EXTERN ulCriticalNesting - EXTERN pxCurrentTCB - EXTERN ulPortTaskHasFPUContext - EXTERN ulAsmAPIPriorityMask +; /* + * ; * FreeRTOS Kernel V11.0.1 + * ; * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * ; * + * ; * SPDX-License-Identifier: MIT + * ; * + * ; * Permission is hereby granted, free of charge, to any person obtaining a copy of + * ; * this software and associated documentation files (the "Software"), to deal in + * ; * the Software without restriction, including without limitation the rights to + * ; * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * ; * the Software, and to permit persons to whom the Software is furnished to do so, + * ; * subject to the following conditions: + * ; * + * ; * The above copyright notice and this permission notice shall be included in all + * ; * copies or substantial portions of the Software. + * ; * + * ; * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * ; * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * ; * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * ; * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * ; * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * ; * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * ; * + * ; * https://www.FreeRTOS.org + * ; * https://github.com/FreeRTOS + * ; * + * ; */ + +EXTERN vTaskSwitchContext +EXTERN ulCriticalNesting +EXTERN pxCurrentTCB +EXTERN ulPortTaskHasFPUContext +EXTERN ulAsmAPIPriorityMask portSAVE_CONTEXT macro - ; Save the LR and SPSR onto the system mode stack before switching to - ; system mode to save the remaining system mode registers - SRSDB sp!, #SYS_MODE - CPS #SYS_MODE - PUSH {R0-R12, R14} - - ; Push the critical nesting count - LDR R2, =ulCriticalNesting - LDR R1, [R2] - PUSH {R1} - - ; Does the task have a floating point context that needs saving? If - ; ulPortTaskHasFPUContext is 0 then no. - LDR R2, =ulPortTaskHasFPUContext - LDR R3, [R2] - CMP R3, #0 - - ; Save the floating point context, if any - FMRXNE R1, FPSCR - VPUSHNE {D0-D15} -#if configFPU_D32 == 1 - VPUSHNE {D16-D31} -#endif ; configFPU_D32 - PUSHNE {R1} - - ; Save ulPortTaskHasFPUContext itself - PUSH {R3} - - ; Save the stack pointer in the TCB - LDR R0, =pxCurrentTCB - LDR R1, [R0] - STR SP, [R1] +; +Save the LR and SPSR onto the system mode stack before switching to +; +system mode to save the remaining system mode registers +SRSDB sp !, # SYS_MODE + CPS # SYS_MODE + PUSH { + R0 - R12, R14 +} + +; +Push the critical nesting count +LDR R2, = ulCriticalNesting + LDR R1, [ R2 ] +PUSH { + R1 +} + +; +Does the task have a floating point context that needs saving ? If +; +ulPortTaskHasFPUContext is 0 then no. + LDR R2, = ulPortTaskHasFPUContext + LDR R3, [ R2 ] +CMP R3, # 0 + +; +Save the floating point context, + +if any +FMRXNE R1, FPSCR + VPUSHNE { + D0 - D15 +} - endm +#if configFPU_D32 == 1 +VPUSHNE { + D16 - D31 +} +#endif; configFPU_D32 +PUSHNE { + R1 +} + +; +Save ulPortTaskHasFPUContext itself + PUSH { + R3 +} + +; +Save the stack pointer in the TCB +LDR R0, = pxCurrentTCB + LDR R1, [ R0 ] +STR SP, [ R1 ] + +endm ; /**********************************************************************/ portRESTORE_CONTEXT macro - ; Set the SP to point to the stack of the task being restored. - LDR R0, =pxCurrentTCB - LDR R1, [R0] - LDR SP, [R1] - - ; Is there a floating point context to restore? If the restored - ; ulPortTaskHasFPUContext is zero then no. - LDR R0, =ulPortTaskHasFPUContext - POP {R1} - STR R1, [R0] - CMP R1, #0 +; +Set the SP to point to the stack of the task being restored. + LDR R0, = pxCurrentTCB + LDR R1, [ R0 ] +LDR SP, [ R1 ] + +; +Is there a floating point context to restore ? If the restored +; +ulPortTaskHasFPUContext is zero then no. + LDR R0, = ulPortTaskHasFPUContext + POP { + R1 +} +STR R1, [ R0 ] +CMP R1, # 0 + +; +Restore the floating point context, + +if any + POPNE { + R0 +} - ; Restore the floating point context, if any - POPNE {R0} #if configFPU_D32 == 1 - VPOPNE {D16-D31} -#endif ; configFPU_D32 - VPOPNE {D0-D15} - VMSRNE FPSCR, R0 - - ; Restore the critical section nesting depth - LDR R0, =ulCriticalNesting - POP {R1} - STR R1, [R0] - - ; Restore all system mode registers other than the SP (which is already - ; being used) - POP {R0-R12, R14} - - ; Return to the task code, loading CPSR on the way. CPSR has the interrupt - ; enable bit set appropriately for the task about to execute. - RFEIA sp! - - endm +VPOPNE { + D16 - D31 +} +#endif; configFPU_D32 +VPOPNE { + D0 - D15 +} +VMSRNE FPSCR, R0 + +; +Restore the critical section nesting depth +LDR R0, = ulCriticalNesting + POP { + R1 +} +STR R1, [ R0 ] + +; +Restore all system mode registers other than the SP( which is already + ; + being used ) +POP +{ + R0 - R12, R14 +} + +Return to the task code, loading CPSR on the way.CPSR has the interrupt +; +enable bit set appropriately + +for the task about to execute. + RFEIA sp ! + +endm diff --git a/Source/portable/IAR/ARM_CA5_No_GIC/portASM.s b/Source/portable/IAR/ARM_CA5_No_GIC/portASM.s index 8c3aa9f0e..e137df7e9 100644 --- a/Source/portable/IAR/ARM_CA5_No_GIC/portASM.s +++ b/Source/portable/IAR/ARM_CA5_No_GIC/portASM.s @@ -1,5 +1,5 @@ ;/* -; * FreeRTOS Kernel V10.6.2 +; * FreeRTOS Kernel V11.0.1 ; * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. ; * ; * SPDX-License-Identifier: MIT diff --git a/Source/portable/IAR/ARM_CA5_No_GIC/portmacro.h b/Source/portable/IAR/ARM_CA5_No_GIC/portmacro.h index 5695b6040..28f62b7f5 100644 --- a/Source/portable/IAR/ARM_CA5_No_GIC/portmacro.h +++ b/Source/portable/IAR/ARM_CA5_No_GIC/portmacro.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -42,117 +42,117 @@ - /*----------------------------------------------------------- - * Port specific definitions. - * - * The settings in this file configure FreeRTOS correctly for the given hardware - * and compiler. - * - * These settings should not be altered. - *----------------------------------------------------------- - */ - - /* Type definitions. */ - #define portCHAR char - #define portFLOAT float - #define portDOUBLE double - #define portLONG long - #define portSHORT short - #define portSTACK_TYPE uint32_t - #define portBASE_TYPE long - - typedef portSTACK_TYPE StackType_t; - typedef long BaseType_t; - typedef unsigned long UBaseType_t; - - typedef uint32_t TickType_t; - #define portMAX_DELAY ( TickType_t ) 0xffffffffUL - - /* 32-bit tick type on a 32-bit architecture, so reads of the tick count do - not need to be guarded with a critical section. */ - #define portTICK_TYPE_IS_ATOMIC 1 - - /*-----------------------------------------------------------*/ - - /* Hardware specifics. */ - #define portSTACK_GROWTH ( -1 ) - #define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) - #define portBYTE_ALIGNMENT 8 - - /*-----------------------------------------------------------*/ - - /* Task utilities. */ - - /* Called at the end of an ISR that can cause a context switch. */ - #define portEND_SWITCHING_ISR( xSwitchRequired )\ - { \ - extern uint32_t ulPortYieldRequired; \ - \ - if( xSwitchRequired != pdFALSE ) \ - { \ - ulPortYieldRequired = pdTRUE; \ - } \ +/*----------------------------------------------------------- + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the given hardware + * and compiler. + * + * These settings should not be altered. + *----------------------------------------------------------- + */ + +/* Type definitions. */ + #define portCHAR char + #define portFLOAT float + #define portDOUBLE double + #define portLONG long + #define portSHORT short + #define portSTACK_TYPE uint32_t + #define portBASE_TYPE long + + typedef portSTACK_TYPE StackType_t; + typedef long BaseType_t; + typedef unsigned long UBaseType_t; + + typedef uint32_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffffffffUL + +/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do + * not need to be guarded with a critical section. */ + #define portTICK_TYPE_IS_ATOMIC 1 + +/*-----------------------------------------------------------*/ + +/* Hardware specifics. */ + #define portSTACK_GROWTH ( -1 ) + #define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) + #define portBYTE_ALIGNMENT 8 + +/*-----------------------------------------------------------*/ + +/* Task utilities. */ + +/* Called at the end of an ISR that can cause a context switch. */ + #define portEND_SWITCHING_ISR( xSwitchRequired ) \ + { \ + extern uint32_t ulPortYieldRequired; \ + \ + if( xSwitchRequired != pdFALSE ) \ + { \ + ulPortYieldRequired = pdTRUE; \ + } \ } - #define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x ) - #define portYIELD() __asm volatile ( "SWI 0" ); __ISB() + #define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x ) + #define portYIELD() __asm volatile ( "SWI 0" ); __ISB() - /*----------------------------------------------------------- - * Critical section control - *----------------------------------------------------------*/ +/*----------------------------------------------------------- +* Critical section control +*----------------------------------------------------------*/ extern void vPortEnterCritical( void ); extern void vPortExitCritical( void ); extern uint32_t ulPortSetInterruptMask( void ); extern void vPortClearInterruptMask( uint32_t ulNewMaskValue ); - #define portENTER_CRITICAL() vPortEnterCritical(); - #define portEXIT_CRITICAL() vPortExitCritical(); - #define portDISABLE_INTERRUPTS() __disable_irq(); __DSB(); __ISB() /* No priority mask register so global disable is used. */ - #define portENABLE_INTERRUPTS() __enable_irq() - #define portSET_INTERRUPT_MASK_FROM_ISR() __get_interrupt_state(); __disable_irq() /* No priority mask register so global disable is used. */ - #define portCLEAR_INTERRUPT_MASK_FROM_ISR(x) __set_interrupt_state(x) + #define portENTER_CRITICAL() vPortEnterCritical(); + #define portEXIT_CRITICAL() vPortExitCritical(); + #define portDISABLE_INTERRUPTS() __disable_irq(); __DSB(); __ISB() /* No priority mask register so global disable is used. */ + #define portENABLE_INTERRUPTS() __enable_irq() + #define portSET_INTERRUPT_MASK_FROM_ISR() __get_interrupt_state(); __disable_irq() /* No priority mask register so global disable is used. */ + #define portCLEAR_INTERRUPT_MASK_FROM_ISR( x ) __set_interrupt_state( x ) - /*-----------------------------------------------------------*/ +/*-----------------------------------------------------------*/ - /* Task function macros as described on the FreeRTOS.org WEB site. These are - not required for this port but included in case common demo code that uses these - macros is used. */ - #define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters ) - #define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters ) +/* Task function macros as described on the FreeRTOS.org WEB site. These are + * not required for this port but included in case common demo code that uses these + * macros is used. */ + #define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters ) + #define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters ) - /* Prototype of the FreeRTOS tick handler. This must be installed as the - handler for whichever peripheral is used to generate the RTOS tick. */ +/* Prototype of the FreeRTOS tick handler. This must be installed as the + * handler for whichever peripheral is used to generate the RTOS tick. */ void FreeRTOS_Tick_Handler( void ); - /* Any task that uses the floating point unit MUST call vPortTaskUsesFPU() - before any floating point instructions are executed. */ +/* Any task that uses the floating point unit MUST call vPortTaskUsesFPU() + * before any floating point instructions are executed. */ void vPortTaskUsesFPU( void ); - #define portTASK_USES_FLOATING_POINT() vPortTaskUsesFPU() + #define portTASK_USES_FLOATING_POINT() vPortTaskUsesFPU() - /* Architecture specific optimisations. */ +/* Architecture specific optimisations. */ #ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION - #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1 + #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1 #endif #if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 - /* Store/clear the ready priorities in a bit map. */ - #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) ) - #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) ) +/* Store/clear the ready priorities in a bit map. */ + #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) ) + #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) ) - /*-----------------------------------------------------------*/ +/*-----------------------------------------------------------*/ - #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31 - __CLZ( uxReadyPriorities ) ) + #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31 - __CLZ( uxReadyPriorities ) ) #endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */ - #define portNOP() __asm volatile( "NOP" ) + #define portNOP() __asm volatile ( "NOP" ) - /* Suppress warnings that are generated by the IAR tools, but cannot be - fixed in the source code because to do so would cause other compilers to - generate warnings. */ +/* Suppress warnings that are generated by the IAR tools, but cannot be + * fixed in the source code because to do so would cause other compilers to + * generate warnings. */ #pragma diag_suppress=Pe191 #pragma diag_suppress=Pa082 diff --git a/Source/portable/IAR/ARM_CA9/port.c b/Source/portable/IAR/ARM_CA9/port.c index b9126a92f..127d46ba7 100644 --- a/Source/portable/IAR/ARM_CA9/port.c +++ b/Source/portable/IAR/ARM_CA9/port.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -37,43 +37,43 @@ #include "task.h" #ifndef configINTERRUPT_CONTROLLER_BASE_ADDRESS - #error configINTERRUPT_CONTROLLER_BASE_ADDRESS must be defined. See https://www.FreeRTOS.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html + #error "configINTERRUPT_CONTROLLER_BASE_ADDRESS must be defined. See www.FreeRTOS.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html" #endif #ifndef configINTERRUPT_CONTROLLER_CPU_INTERFACE_OFFSET - #error configINTERRUPT_CONTROLLER_CPU_INTERFACE_OFFSET must be defined. See https://www.FreeRTOS.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html + #error "configINTERRUPT_CONTROLLER_CPU_INTERFACE_OFFSET must be defined. See www.FreeRTOS.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html" #endif #ifndef configUNIQUE_INTERRUPT_PRIORITIES - #error configUNIQUE_INTERRUPT_PRIORITIES must be defined. See https://www.FreeRTOS.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html + #error "configUNIQUE_INTERRUPT_PRIORITIES must be defined. See www.FreeRTOS.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html" #endif #ifndef configSETUP_TICK_INTERRUPT - #error configSETUP_TICK_INTERRUPT() must be defined. See https://www.FreeRTOS.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html + #error "configSETUP_TICK_INTERRUPT() must be defined. See www.FreeRTOS.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html" #endif /* configSETUP_TICK_INTERRUPT */ #ifndef configMAX_API_CALL_INTERRUPT_PRIORITY - #error configMAX_API_CALL_INTERRUPT_PRIORITY must be defined. See https://www.FreeRTOS.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html + #error "configMAX_API_CALL_INTERRUPT_PRIORITY must be defined. See www.FreeRTOS.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html" #endif #if configMAX_API_CALL_INTERRUPT_PRIORITY == 0 - #error configMAX_API_CALL_INTERRUPT_PRIORITY must not be set to 0 + #error "configMAX_API_CALL_INTERRUPT_PRIORITY must not be set to 0" #endif #if configMAX_API_CALL_INTERRUPT_PRIORITY > configUNIQUE_INTERRUPT_PRIORITIES - #error configMAX_API_CALL_INTERRUPT_PRIORITY must be less than or equal to configUNIQUE_INTERRUPT_PRIORITIES as the lower the numeric priority value the higher the logical interrupt priority + #error "configMAX_API_CALL_INTERRUPT_PRIORITY must be less than or equal to configUNIQUE_INTERRUPT_PRIORITIES as the lower the numeric priority value the higher the logical interrupt priority" #endif #if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 /* Check the configuration. */ - #if( configMAX_PRIORITIES > 32 ) - #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice. + #if ( configMAX_PRIORITIES > 32 ) + #error "configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice." #endif #endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */ /* In case security extensions are implemented. */ #if configMAX_API_CALL_INTERRUPT_PRIORITY <= ( configUNIQUE_INTERRUPT_PRIORITIES / 2 ) - #error configMAX_API_CALL_INTERRUPT_PRIORITY must be greater than ( configUNIQUE_INTERRUPT_PRIORITIES / 2 ) + #error "configMAX_API_CALL_INTERRUPT_PRIORITY must be greater than ( configUNIQUE_INTERRUPT_PRIORITIES / 2 )" #endif #ifndef configCLEAR_TICK_INTERRUPT @@ -81,45 +81,45 @@ #endif /* A critical section is exited when the critical section nesting count reaches -this value. */ -#define portNO_CRITICAL_NESTING ( ( uint32_t ) 0 ) + * this value. */ +#define portNO_CRITICAL_NESTING ( ( uint32_t ) 0 ) /* In all GICs 255 can be written to the priority mask register to unmask all -(but the lowest) interrupt priority. */ -#define portUNMASK_VALUE ( 0xFFUL ) + * (but the lowest) interrupt priority. */ +#define portUNMASK_VALUE ( 0xFFUL ) /* Tasks are not created with a floating point context, but can be given a -floating point context after they have been created. A variable is stored as -part of the tasks context that holds portNO_FLOATING_POINT_CONTEXT if the task -does not have an FPU context, or any other value if the task does have an FPU -context. */ -#define portNO_FLOATING_POINT_CONTEXT ( ( StackType_t ) 0 ) + * floating point context after they have been created. A variable is stored as + * part of the tasks context that holds portNO_FLOATING_POINT_CONTEXT if the task + * does not have an FPU context, or any other value if the task does have an FPU + * context. */ +#define portNO_FLOATING_POINT_CONTEXT ( ( StackType_t ) 0 ) /* Constants required to setup the initial task context. */ -#define portINITIAL_SPSR ( ( StackType_t ) 0x1f ) /* System mode, ARM mode, interrupts enabled. */ -#define portTHUMB_MODE_BIT ( ( StackType_t ) 0x20 ) -#define portTHUMB_MODE_ADDRESS ( 0x01UL ) +#define portINITIAL_SPSR ( ( StackType_t ) 0x1f ) /* System mode, ARM mode, interrupts enabled. */ +#define portTHUMB_MODE_BIT ( ( StackType_t ) 0x20 ) +#define portTHUMB_MODE_ADDRESS ( 0x01UL ) /* Used by portASSERT_IF_INTERRUPT_PRIORITY_INVALID() when ensuring the binary -point is zero. */ -#define portBINARY_POINT_BITS ( ( uint8_t ) 0x03 ) + * point is zero. */ +#define portBINARY_POINT_BITS ( ( uint8_t ) 0x03 ) /* Masks all bits in the APSR other than the mode bits. */ -#define portAPSR_MODE_BITS_MASK ( 0x1F ) +#define portAPSR_MODE_BITS_MASK ( 0x1F ) /* The value of the mode bits in the APSR when the CPU is executing in user -mode. */ -#define portAPSR_USER_MODE ( 0x10 ) + * mode. */ +#define portAPSR_USER_MODE ( 0x10 ) /* Macro to unmask all interrupt priorities. */ -#define portCLEAR_INTERRUPT_MASK() \ -{ \ - __disable_irq(); \ - portICCPMR_PRIORITY_MASK_REGISTER = portUNMASK_VALUE; \ - __asm( "DSB \n" \ - "ISB \n" ); \ - __enable_irq(); \ -} +#define portCLEAR_INTERRUPT_MASK() \ + { \ + __disable_irq(); \ + portICCPMR_PRIORITY_MASK_REGISTER = portUNMASK_VALUE; \ + __asm( "DSB \n" \ + "ISB \n" ); \ + __enable_irq(); \ + } /*-----------------------------------------------------------*/ @@ -137,21 +137,21 @@ static void prvTaskExitError( void ); /*-----------------------------------------------------------*/ /* A variable is used to keep track of the critical section nesting. This -variable has to be stored as part of the task context and must be initialised to -a non zero value to ensure interrupts don't inadvertently become unmasked before -the scheduler starts. As it is stored as part of the task context it will -automatically be set to 0 when the first task is started. */ + * variable has to be stored as part of the task context and must be initialised to + * a non zero value to ensure interrupts don't inadvertently become unmasked before + * the scheduler starts. As it is stored as part of the task context it will + * automatically be set to 0 when the first task is started. */ volatile uint32_t ulCriticalNesting = 9999UL; /* Saved as part of the task context. If ulPortTaskHasFPUContext is non-zero -then a floating point context must be saved and restored for the task. */ + * then a floating point context must be saved and restored for the task. */ uint32_t ulPortTaskHasFPUContext = pdFALSE; /* Set to 1 to pend a context switch from an ISR. */ uint32_t ulPortYieldRequired = pdFALSE; /* Counts the interrupt nesting depth. A context switch is only performed if -if the nesting depth is 0. */ + * if the nesting depth is 0. */ uint32_t ulPortInterruptNesting = 0UL; @@ -160,14 +160,16 @@ uint32_t ulPortInterruptNesting = 0UL; /* * See header file for description. */ -StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters ) +StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, + TaskFunction_t pxCode, + void * pvParameters ) { /* Setup the initial stack of the task. The stack is set exactly as - expected by the portRESTORE_CONTEXT() macro. - - The fist real value on the stack is the status register, which is set for - system mode, with interrupts enabled. A few NULLs are added first to ensure - GDB does not try decoding a non-existent return address. */ + * expected by the portRESTORE_CONTEXT() macro. + * + * The fist real value on the stack is the status register, which is set for + * system mode, with interrupts enabled. A few NULLs are added first to ensure + * GDB does not try decoding a non-existent return address. */ *pxTopOfStack = NULL; pxTopOfStack--; *pxTopOfStack = NULL; @@ -189,43 +191,43 @@ StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t px pxTopOfStack--; /* Next all the registers other than the stack pointer. */ - *pxTopOfStack = ( StackType_t ) prvTaskExitError; /* R14 */ + *pxTopOfStack = ( StackType_t ) prvTaskExitError; /* R14 */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x12121212; /* R12 */ + *pxTopOfStack = ( StackType_t ) 0x12121212; /* R12 */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x11111111; /* R11 */ + *pxTopOfStack = ( StackType_t ) 0x11111111; /* R11 */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x10101010; /* R10 */ + *pxTopOfStack = ( StackType_t ) 0x10101010; /* R10 */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x09090909; /* R9 */ + *pxTopOfStack = ( StackType_t ) 0x09090909; /* R9 */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x08080808; /* R8 */ + *pxTopOfStack = ( StackType_t ) 0x08080808; /* R8 */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x07070707; /* R7 */ + *pxTopOfStack = ( StackType_t ) 0x07070707; /* R7 */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x06060606; /* R6 */ + *pxTopOfStack = ( StackType_t ) 0x06060606; /* R6 */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x05050505; /* R5 */ + *pxTopOfStack = ( StackType_t ) 0x05050505; /* R5 */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x04040404; /* R4 */ + *pxTopOfStack = ( StackType_t ) 0x04040404; /* R4 */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x03030303; /* R3 */ + *pxTopOfStack = ( StackType_t ) 0x03030303; /* R3 */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x02020202; /* R2 */ + *pxTopOfStack = ( StackType_t ) 0x02020202; /* R2 */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x01010101; /* R1 */ + *pxTopOfStack = ( StackType_t ) 0x01010101; /* R1 */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */ + *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */ pxTopOfStack--; /* The task will start with a critical nesting count of 0 as interrupts are - enabled. */ + * enabled. */ *pxTopOfStack = portNO_CRITICAL_NESTING; pxTopOfStack--; /* The task will start without a floating point context. A task that uses - the floating point hardware must call vPortTaskUsesFPU() before executing - any floating point instructions. */ + * the floating point hardware must call vPortTaskUsesFPU() before executing + * any floating point instructions. */ *pxTopOfStack = portNO_FLOATING_POINT_CONTEXT; return pxTopOfStack; @@ -235,32 +237,36 @@ StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t px static void prvTaskExitError( void ) { /* A function that implements a task must not exit or attempt to return to - its caller as there is nothing to return to. If a task wants to exit it - should instead call vTaskDelete( NULL ). - - Artificially force an assert() to be triggered if configASSERT() is - defined, then stop here so application writers can catch the error. */ + * its caller as there is nothing to return to. If a task wants to exit it + * should instead call vTaskDelete( NULL ). + * + * Artificially force an assert() to be triggered if configASSERT() is + * defined, then stop here so application writers can catch the error. */ configASSERT( ulPortInterruptNesting == ~0UL ); portDISABLE_INTERRUPTS(); - for( ;; ); + + for( ; ; ) + { + } } /*-----------------------------------------------------------*/ BaseType_t xPortStartScheduler( void ) { -uint32_t ulAPSR; + uint32_t ulAPSR; /* Only continue if the CPU is not in User mode. The CPU must be in a - Privileged mode for the scheduler to start. */ + * Privileged mode for the scheduler to start. */ __asm volatile ( "MRS %0, APSR" : "=r" ( ulAPSR ) ); + ulAPSR &= portAPSR_MODE_BITS_MASK; configASSERT( ulAPSR != portAPSR_USER_MODE ); if( ulAPSR != portAPSR_USER_MODE ) { /* Only continue if the binary point value is set to its lowest possible - setting. See the comments in vPortValidateInterruptPriority() below for - more information. */ + * setting. See the comments in vPortValidateInterruptPriority() below for + * more information. */ configASSERT( ( portICCBPR_BINARY_POINT_REGISTER & portBINARY_POINT_BITS ) <= portMAX_BINARY_POINT_VALUE ); if( ( portICCBPR_BINARY_POINT_REGISTER & portBINARY_POINT_BITS ) <= portMAX_BINARY_POINT_VALUE ) @@ -274,8 +280,8 @@ uint32_t ulAPSR; } /* Will only get here if vTaskStartScheduler() was called with the CPU in - a non-privileged mode or the binary point register was not set to its lowest - possible value. */ + * a non-privileged mode or the binary point register was not set to its lowest + * possible value. */ return 0; } /*-----------------------------------------------------------*/ @@ -283,7 +289,7 @@ uint32_t ulAPSR; void vPortEndScheduler( void ) { /* Not implemented in ports where there is nothing to return to. - Artificially force an assert. */ + * Artificially force an assert. */ configASSERT( ulCriticalNesting == 1000UL ); } /*-----------------------------------------------------------*/ @@ -293,16 +299,16 @@ void vPortEnterCritical( void ) /* Disable interrupts as per portDISABLE_INTERRUPTS(); */ ulPortSetInterruptMask(); - /* Now interrupts are disabled ulCriticalNesting can be accessed - directly. Increment ulCriticalNesting to keep a count of how many times - portENTER_CRITICAL() has been called. */ + /* Now that interrupts are disabled, ulCriticalNesting can be accessed + * directly. Increment ulCriticalNesting to keep a count of how many times + * portENTER_CRITICAL() has been called. */ ulCriticalNesting++; /* This is not the interrupt safe version of the enter critical function so - assert() if it is being called from an interrupt context. Only API - functions that end in "FromISR" can be used in an interrupt. Only assert if - the critical nesting count is 1 to protect against recursive calls if the - assert function also uses a critical section. */ + * assert() if it is being called from an interrupt context. Only API + * functions that end in "FromISR" can be used in an interrupt. Only assert if + * the critical nesting count is 1 to protect against recursive calls if the + * assert function also uses a critical section. */ if( ulCriticalNesting == 1 ) { configASSERT( ulPortInterruptNesting == 0 ); @@ -315,15 +321,15 @@ void vPortExitCritical( void ) if( ulCriticalNesting > portNO_CRITICAL_NESTING ) { /* Decrement the nesting count as the critical section is being - exited. */ + * exited. */ ulCriticalNesting--; /* If the nesting level has reached zero then all interrupt - priorities must be re-enabled. */ + * priorities must be re-enabled. */ if( ulCriticalNesting == portNO_CRITICAL_NESTING ) { /* Critical nesting has reached zero so all interrupt priorities - should be unmasked. */ + * should be unmasked. */ portCLEAR_INTERRUPT_MASK(); } } @@ -333,12 +339,12 @@ void vPortExitCritical( void ) void FreeRTOS_Tick_Handler( void ) { /* Set interrupt mask before altering scheduler structures. The tick - handler runs at the lowest priority, so interrupts cannot already be masked, - so there is no need to save and restore the current mask value. */ + * handler runs at the lowest priority, so interrupts cannot already be masked, + * so there is no need to save and restore the current mask value. */ __disable_irq(); portICCPMR_PRIORITY_MASK_REGISTER = ( uint32_t ) ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT ); - __asm( "DSB \n" - "ISB \n" ); + __asm( "DSB \n" + "ISB \n" ); __enable_irq(); /* Increment the RTOS tick. */ @@ -355,14 +361,14 @@ void FreeRTOS_Tick_Handler( void ) void vPortTaskUsesFPU( void ) { -uint32_t ulInitialFPSCR = 0; + uint32_t ulInitialFPSCR = 0; /* A task is registering the fact that it needs an FPU context. Set the - FPU flag (which is saved as part of the task context). */ + * FPU flag (which is saved as part of the task context). */ ulPortTaskHasFPUContext = pdTRUE; /* Initialise the floating point status register. */ - __asm( "FMXR FPSCR, %0" :: "r" (ulInitialFPSCR) ); + __asm( "FMXR FPSCR, %0" ::"r" ( ulInitialFPSCR ) ); } /*-----------------------------------------------------------*/ @@ -377,9 +383,10 @@ void vPortClearInterruptMask( uint32_t ulNewMaskValue ) uint32_t ulPortSetInterruptMask( void ) { -uint32_t ulReturn; + uint32_t ulReturn; __disable_irq(); + if( portICCPMR_PRIORITY_MASK_REGISTER == ( uint32_t ) ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT ) ) { /* Interrupts were already masked. */ @@ -389,49 +396,50 @@ uint32_t ulReturn; { ulReturn = pdFALSE; portICCPMR_PRIORITY_MASK_REGISTER = ( uint32_t ) ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT ); - __asm( "DSB \n" - "ISB \n" ); + __asm( "DSB \n" + "ISB \n" ); } + __enable_irq(); return ulReturn; } /*-----------------------------------------------------------*/ -#if( configASSERT_DEFINED == 1 ) +#if ( configASSERT_DEFINED == 1 ) void vPortValidateInterruptPriority( void ) { /* The following assertion will fail if a service routine (ISR) for - an interrupt that has been assigned a priority above - configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API - function. ISR safe FreeRTOS API functions must *only* be called - from interrupts that have been assigned a priority at or below - configMAX_SYSCALL_INTERRUPT_PRIORITY. - - Numerically low interrupt priority numbers represent logically high - interrupt priorities, therefore the priority of the interrupt must - be set to a value equal to or numerically *higher* than - configMAX_SYSCALL_INTERRUPT_PRIORITY. - - FreeRTOS maintains separate thread and ISR API functions to ensure - interrupt entry is as fast and simple as possible. - - The following links provide detailed information: - https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html - https://www.FreeRTOS.org/FAQHelp.html */ + * an interrupt that has been assigned a priority above + * configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API + * function. ISR safe FreeRTOS API functions must *only* be called + * from interrupts that have been assigned a priority at or below + * configMAX_SYSCALL_INTERRUPT_PRIORITY. + * + * Numerically low interrupt priority numbers represent logically high + * interrupt priorities, therefore the priority of the interrupt must + * be set to a value equal to or numerically *higher* than + * configMAX_SYSCALL_INTERRUPT_PRIORITY. + * + * FreeRTOS maintains separate thread and ISR API functions to ensure + * interrupt entry is as fast and simple as possible. + * + * The following links provide detailed information: + * https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html + * https://www.FreeRTOS.org/FAQHelp.html */ configASSERT( portICCRPR_RUNNING_PRIORITY_REGISTER >= ( uint32_t ) ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT ) ); /* Priority grouping: The interrupt controller (GIC) allows the bits - that define each interrupt's priority to be split between bits that - define the interrupt's pre-emption priority bits and bits that define - the interrupt's sub-priority. For simplicity all bits must be defined - to be pre-emption priority bits. The following assertion will fail if - this is not the case (if some bits represent a sub-priority). - - The priority grouping is configured by the GIC's binary point register - (ICCBPR). Writting 0 to ICCBPR will ensure it is set to its lowest - possible value (which may be above 0). */ + * that define each interrupt's priority to be split between bits that + * define the interrupt's pre-emption priority bits and bits that define + * the interrupt's sub-priority. For simplicity all bits must be defined + * to be pre-emption priority bits. The following assertion will fail if + * this is not the case (if some bits represent a sub-priority). + * + * The priority grouping is configured by the GIC's binary point register + * (ICCBPR). Writting 0 to ICCBPR will ensure it is set to its lowest + * possible value (which may be above 0). */ configASSERT( ( portICCBPR_BINARY_POINT_REGISTER & portBINARY_POINT_BITS ) <= portMAX_BINARY_POINT_VALUE ); } diff --git a/Source/portable/IAR/ARM_CA9/portASM.h b/Source/portable/IAR/ARM_CA9/portASM.h index 31229b76e..ec48e1527 100644 --- a/Source/portable/IAR/ARM_CA9/portASM.h +++ b/Source/portable/IAR/ARM_CA9/portASM.h @@ -1,111 +1,160 @@ -;/* -; * FreeRTOS Kernel V10.6.2 -; * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. -; * -; * SPDX-License-Identifier: MIT -; * -; * Permission is hereby granted, free of charge, to any person obtaining a copy of -; * this software and associated documentation files (the "Software"), to deal in -; * the Software without restriction, including without limitation the rights to -; * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of -; * the Software, and to permit persons to whom the Software is furnished to do so, -; * subject to the following conditions: -; * -; * The above copyright notice and this permission notice shall be included in all -; * copies or substantial portions of the Software. -; * -; * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -; * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS -; * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR -; * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER -; * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN -; * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. -; * -; * https://www.FreeRTOS.org -; * https://github.com/FreeRTOS -; * -; */ - - EXTERN vTaskSwitchContext - EXTERN ulCriticalNesting - EXTERN pxCurrentTCB - EXTERN ulPortTaskHasFPUContext - EXTERN ulAsmAPIPriorityMask +; /* + * ; * FreeRTOS Kernel V11.0.1 + * ; * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * ; * + * ; * SPDX-License-Identifier: MIT + * ; * + * ; * Permission is hereby granted, free of charge, to any person obtaining a copy of + * ; * this software and associated documentation files (the "Software"), to deal in + * ; * the Software without restriction, including without limitation the rights to + * ; * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * ; * the Software, and to permit persons to whom the Software is furnished to do so, + * ; * subject to the following conditions: + * ; * + * ; * The above copyright notice and this permission notice shall be included in all + * ; * copies or substantial portions of the Software. + * ; * + * ; * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * ; * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * ; * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * ; * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * ; * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * ; * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * ; * + * ; * https://www.FreeRTOS.org + * ; * https://github.com/FreeRTOS + * ; * + * ; */ + +EXTERN vTaskSwitchContext +EXTERN ulCriticalNesting +EXTERN pxCurrentTCB +EXTERN ulPortTaskHasFPUContext +EXTERN ulAsmAPIPriorityMask portSAVE_CONTEXT macro - ; Save the LR and SPSR onto the system mode stack before switching to - ; system mode to save the remaining system mode registers - SRSDB sp!, #SYS_MODE - CPS #SYS_MODE - PUSH {R0-R12, R14} - - ; Push the critical nesting count - LDR R2, =ulCriticalNesting - LDR R1, [R2] - PUSH {R1} - - ; Does the task have a floating point context that needs saving? If - ; ulPortTaskHasFPUContext is 0 then no. - LDR R2, =ulPortTaskHasFPUContext - LDR R3, [R2] - CMP R3, #0 - - ; Save the floating point context, if any - FMRXNE R1, FPSCR - VPUSHNE {D0-D15} - VPUSHNE {D16-D31} - PUSHNE {R1} - - ; Save ulPortTaskHasFPUContext itself - PUSH {R3} - - ; Save the stack pointer in the TCB - LDR R0, =pxCurrentTCB - LDR R1, [R0] - STR SP, [R1] - - endm +; +Save the LR and SPSR onto the system mode stack before switching to +; +system mode to save the remaining system mode registers +SRSDB sp !, # SYS_MODE + CPS # SYS_MODE + PUSH { + R0 - R12, R14 +} + +; +Push the critical nesting count +LDR R2, = ulCriticalNesting + LDR R1, [ R2 ] +PUSH { + R1 +} + +; +Does the task have a floating point context that needs saving ? If +; +ulPortTaskHasFPUContext is 0 then no. + LDR R2, = ulPortTaskHasFPUContext + LDR R3, [ R2 ] +CMP R3, # 0 + +; +Save the floating point context, + +if any +FMRXNE R1, FPSCR + VPUSHNE { + D0 - D15 +} + +VPUSHNE { + D16 - D31 +} +PUSHNE { + R1 +} + +; +Save ulPortTaskHasFPUContext itself + PUSH { + R3 +} + +; +Save the stack pointer in the TCB +LDR R0, = pxCurrentTCB + LDR R1, [ R0 ] +STR SP, [ R1 ] + +endm ; /**********************************************************************/ portRESTORE_CONTEXT macro - ; Set the SP to point to the stack of the task being restored. - LDR R0, =pxCurrentTCB - LDR R1, [R0] - LDR SP, [R1] - - ; Is there a floating point context to restore? If the restored - ; ulPortTaskHasFPUContext is zero then no. - LDR R0, =ulPortTaskHasFPUContext - POP {R1} - STR R1, [R0] - CMP R1, #0 - - ; Restore the floating point context, if any - POPNE {R0} - VPOPNE {D16-D31} - VPOPNE {D0-D15} - VMSRNE FPSCR, R0 - - ; Restore the critical section nesting depth - LDR R0, =ulCriticalNesting - POP {R1} - STR R1, [R0] - - ; Ensure the priority mask is correct for the critical nesting depth - LDR R2, =portICCPMR_PRIORITY_MASK_REGISTER_ADDRESS - CMP R1, #0 - MOVEQ R4, #255 - LDRNE R4, =( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT ) - STR R4, [r2] - - ; Restore all system mode registers other than the SP (which is already - ; being used) - POP {R0-R12, R14} - - ; Return to the task code, loading CPSR on the way. - RFEIA sp! - - endm +; +Set the SP to point to the stack of the task being restored. + LDR R0, = pxCurrentTCB + LDR R1, [ R0 ] +LDR SP, [ R1 ] + +; +Is there a floating point context to restore ? If the restored +; +ulPortTaskHasFPUContext is zero then no. + LDR R0, = ulPortTaskHasFPUContext + POP { + R1 +} +STR R1, [ R0 ] +CMP R1, # 0 + +; +Restore the floating point context, + +if any + POPNE { + R0 +} + +VPOPNE { + D16 - D31 +} +VPOPNE { + D0 - D15 +} +VMSRNE FPSCR, R0 + +; +Restore the critical section nesting depth +LDR R0, = ulCriticalNesting + POP { + R1 +} +STR R1, [ R0 ] + +; +Ensure the priority mask is correct + +for the critical nesting depth +LDR R2, = portICCPMR_PRIORITY_MASK_REGISTER_ADDRESS + CMP R1, # 0 +MOVEQ R4, # 255 +LDRNE R4, = ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT ) + STR R4, [ r2 ] + +; +Restore all system mode registers other than the SP( which is already + ; + being used ) +POP +{ + R0 - R12, R14 +} + +Return to the task code, loading CPSR on the way. + RFEIA sp ! + +endm diff --git a/Source/portable/IAR/ARM_CA9/portASM.s b/Source/portable/IAR/ARM_CA9/portASM.s index e9c87c6be..f81f959d1 100644 --- a/Source/portable/IAR/ARM_CA9/portASM.s +++ b/Source/portable/IAR/ARM_CA9/portASM.s @@ -1,5 +1,5 @@ ;/* -; * FreeRTOS Kernel V10.6.2 +; * FreeRTOS Kernel V11.0.1 ; * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. ; * ; * SPDX-License-Identifier: MIT diff --git a/Source/portable/IAR/ARM_CA9/portmacro.h b/Source/portable/IAR/ARM_CA9/portmacro.h index 244fd41d6..5e7480b89 100644 --- a/Source/portable/IAR/ARM_CA9/portmacro.h +++ b/Source/portable/IAR/ARM_CA9/portmacro.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -40,127 +40,127 @@ #include - /*----------------------------------------------------------- - * Port specific definitions. - * - * The settings in this file configure FreeRTOS correctly for the given hardware - * and compiler. - * - * These settings should not be altered. - *----------------------------------------------------------- - */ - - /* Type definitions. */ - #define portCHAR char - #define portFLOAT float - #define portDOUBLE double - #define portLONG long - #define portSHORT short - #define portSTACK_TYPE uint32_t - #define portBASE_TYPE long - - typedef portSTACK_TYPE StackType_t; - typedef long BaseType_t; - typedef unsigned long UBaseType_t; - - typedef uint32_t TickType_t; - #define portMAX_DELAY ( TickType_t ) 0xffffffffUL - - /* 32-bit tick type on a 32-bit architecture, so reads of the tick count do - not need to be guarded with a critical section. */ - #define portTICK_TYPE_IS_ATOMIC 1 - - /*-----------------------------------------------------------*/ - - /* Hardware specifics. */ - #define portSTACK_GROWTH ( -1 ) - #define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) - #define portBYTE_ALIGNMENT 8 - - /*-----------------------------------------------------------*/ - - /* Task utilities. */ - - /* Called at the end of an ISR that can cause a context switch. */ - #define portEND_SWITCHING_ISR( xSwitchRequired )\ - { \ - extern uint32_t ulPortYieldRequired; \ - \ - if( xSwitchRequired != pdFALSE ) \ - { \ - ulPortYieldRequired = pdTRUE; \ - } \ +/*----------------------------------------------------------- + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the given hardware + * and compiler. + * + * These settings should not be altered. + *----------------------------------------------------------- + */ + +/* Type definitions. */ + #define portCHAR char + #define portFLOAT float + #define portDOUBLE double + #define portLONG long + #define portSHORT short + #define portSTACK_TYPE uint32_t + #define portBASE_TYPE long + + typedef portSTACK_TYPE StackType_t; + typedef long BaseType_t; + typedef unsigned long UBaseType_t; + + typedef uint32_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffffffffUL + +/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do + * not need to be guarded with a critical section. */ + #define portTICK_TYPE_IS_ATOMIC 1 + +/*-----------------------------------------------------------*/ + +/* Hardware specifics. */ + #define portSTACK_GROWTH ( -1 ) + #define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) + #define portBYTE_ALIGNMENT 8 + +/*-----------------------------------------------------------*/ + +/* Task utilities. */ + +/* Called at the end of an ISR that can cause a context switch. */ + #define portEND_SWITCHING_ISR( xSwitchRequired ) \ + { \ + extern uint32_t ulPortYieldRequired; \ + \ + if( xSwitchRequired != pdFALSE ) \ + { \ + ulPortYieldRequired = pdTRUE; \ + } \ } - #define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x ) - #define portYIELD() __asm( "SWI 0" ); + #define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x ) + #define portYIELD() __asm( "SWI 0" ); - /*----------------------------------------------------------- - * Critical section control - *----------------------------------------------------------*/ +/*----------------------------------------------------------- +* Critical section control +*----------------------------------------------------------*/ extern void vPortEnterCritical( void ); extern void vPortExitCritical( void ); extern uint32_t ulPortSetInterruptMask( void ); extern void vPortClearInterruptMask( uint32_t ulNewMaskValue ); - /* These macros do not globally disable/enable interrupts. They do mask off - interrupts that have a priority below configMAX_API_CALL_INTERRUPT_PRIORITY. */ - #define portENTER_CRITICAL() vPortEnterCritical(); - #define portEXIT_CRITICAL() vPortExitCritical(); - #define portDISABLE_INTERRUPTS() ulPortSetInterruptMask() - #define portENABLE_INTERRUPTS() vPortClearInterruptMask( 0 ) - #define portSET_INTERRUPT_MASK_FROM_ISR() ulPortSetInterruptMask() - #define portCLEAR_INTERRUPT_MASK_FROM_ISR(x) vPortClearInterruptMask(x) - - /*-----------------------------------------------------------*/ - - /* Task function macros as described on the FreeRTOS.org WEB site. These are - not required for this port but included in case common demo code that uses these - macros is used. */ - #define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters ) - #define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters ) - - /* Prototype of the FreeRTOS tick handler. This must be installed as the - handler for whichever peripheral is used to generate the RTOS tick. */ +/* These macros do not globally disable/enable interrupts. They do mask off + * interrupts that have a priority below configMAX_API_CALL_INTERRUPT_PRIORITY. */ + #define portENTER_CRITICAL() vPortEnterCritical(); + #define portEXIT_CRITICAL() vPortExitCritical(); + #define portDISABLE_INTERRUPTS() ulPortSetInterruptMask() + #define portENABLE_INTERRUPTS() vPortClearInterruptMask( 0 ) + #define portSET_INTERRUPT_MASK_FROM_ISR() ulPortSetInterruptMask() + #define portCLEAR_INTERRUPT_MASK_FROM_ISR( x ) vPortClearInterruptMask( x ) + +/*-----------------------------------------------------------*/ + +/* Task function macros as described on the FreeRTOS.org WEB site. These are + * not required for this port but included in case common demo code that uses these + * macros is used. */ + #define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters ) + #define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters ) + +/* Prototype of the FreeRTOS tick handler. This must be installed as the + * handler for whichever peripheral is used to generate the RTOS tick. */ void FreeRTOS_Tick_Handler( void ); - /* Any task that uses the floating point unit MUST call vPortTaskUsesFPU() - before any floating point instructions are executed. */ +/* Any task that uses the floating point unit MUST call vPortTaskUsesFPU() + * before any floating point instructions are executed. */ void vPortTaskUsesFPU( void ); - #define portTASK_USES_FLOATING_POINT() vPortTaskUsesFPU() + #define portTASK_USES_FLOATING_POINT() vPortTaskUsesFPU() - #define portLOWEST_INTERRUPT_PRIORITY ( ( ( uint32_t ) configUNIQUE_INTERRUPT_PRIORITIES ) - 1UL ) - #define portLOWEST_USABLE_INTERRUPT_PRIORITY ( portLOWEST_INTERRUPT_PRIORITY - 1UL ) + #define portLOWEST_INTERRUPT_PRIORITY ( ( ( uint32_t ) configUNIQUE_INTERRUPT_PRIORITIES ) - 1UL ) + #define portLOWEST_USABLE_INTERRUPT_PRIORITY ( portLOWEST_INTERRUPT_PRIORITY - 1UL ) - /* Architecture specific optimisations. */ +/* Architecture specific optimisations. */ #ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION - #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1 + #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1 #endif #if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 - /* Store/clear the ready priorities in a bit map. */ - #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) ) - #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) ) +/* Store/clear the ready priorities in a bit map. */ + #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) ) + #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) ) - /*-----------------------------------------------------------*/ +/*-----------------------------------------------------------*/ - #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31 - __CLZ( uxReadyPriorities ) ) + #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31 - __CLZ( uxReadyPriorities ) ) #endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */ #ifdef configASSERT void vPortValidateInterruptPriority( void ); - #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() vPortValidateInterruptPriority() + #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() vPortValidateInterruptPriority() #endif /* configASSERT */ - #define portNOP() __asm volatile( "NOP" ) + #define portNOP() __asm volatile ( "NOP" ) - /* Suppress warnings that are generated by the IAR tools, but cannot be - fixed in the source code because to do so would cause other compilers to - generate warnings. */ +/* Suppress warnings that are generated by the IAR tools, but cannot be + * fixed in the source code because to do so would cause other compilers to + * generate warnings. */ #pragma diag_suppress=Pe191 #pragma diag_suppress=Pa082 @@ -168,40 +168,40 @@ /* The number of bits to shift for an interrupt priority is dependent on the -number of bits implemented by the interrupt controller. */ + * number of bits implemented by the interrupt controller. */ #if configUNIQUE_INTERRUPT_PRIORITIES == 16 - #define portPRIORITY_SHIFT 4 - #define portMAX_BINARY_POINT_VALUE 3 + #define portPRIORITY_SHIFT 4 + #define portMAX_BINARY_POINT_VALUE 3 #elif configUNIQUE_INTERRUPT_PRIORITIES == 32 - #define portPRIORITY_SHIFT 3 - #define portMAX_BINARY_POINT_VALUE 2 + #define portPRIORITY_SHIFT 3 + #define portMAX_BINARY_POINT_VALUE 2 #elif configUNIQUE_INTERRUPT_PRIORITIES == 64 - #define portPRIORITY_SHIFT 2 - #define portMAX_BINARY_POINT_VALUE 1 + #define portPRIORITY_SHIFT 2 + #define portMAX_BINARY_POINT_VALUE 1 #elif configUNIQUE_INTERRUPT_PRIORITIES == 128 - #define portPRIORITY_SHIFT 1 - #define portMAX_BINARY_POINT_VALUE 0 + #define portPRIORITY_SHIFT 1 + #define portMAX_BINARY_POINT_VALUE 0 #elif configUNIQUE_INTERRUPT_PRIORITIES == 256 - #define portPRIORITY_SHIFT 0 - #define portMAX_BINARY_POINT_VALUE 0 -#else + #define portPRIORITY_SHIFT 0 + #define portMAX_BINARY_POINT_VALUE 0 +#else /* if configUNIQUE_INTERRUPT_PRIORITIES == 16 */ #error Invalid configUNIQUE_INTERRUPT_PRIORITIES setting. configUNIQUE_INTERRUPT_PRIORITIES must be set to the number of unique priorities implemented by the target hardware -#endif +#endif /* if configUNIQUE_INTERRUPT_PRIORITIES == 16 */ /* Interrupt controller access addresses. */ -#define portICCPMR_PRIORITY_MASK_OFFSET ( 0x04 ) -#define portICCIAR_INTERRUPT_ACKNOWLEDGE_OFFSET ( 0x0C ) -#define portICCEOIR_END_OF_INTERRUPT_OFFSET ( 0x10 ) -#define portICCBPR_BINARY_POINT_OFFSET ( 0x08 ) -#define portICCRPR_RUNNING_PRIORITY_OFFSET ( 0x14 ) - -#define portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS ( configINTERRUPT_CONTROLLER_BASE_ADDRESS + configINTERRUPT_CONTROLLER_CPU_INTERFACE_OFFSET ) -#define portICCPMR_PRIORITY_MASK_REGISTER ( *( ( volatile uint32_t * ) ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCPMR_PRIORITY_MASK_OFFSET ) ) ) -#define portICCIAR_INTERRUPT_ACKNOWLEDGE_REGISTER_ADDRESS ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCIAR_INTERRUPT_ACKNOWLEDGE_OFFSET ) -#define portICCEOIR_END_OF_INTERRUPT_REGISTER_ADDRESS ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCEOIR_END_OF_INTERRUPT_OFFSET ) -#define portICCPMR_PRIORITY_MASK_REGISTER_ADDRESS ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCPMR_PRIORITY_MASK_OFFSET ) -#define portICCBPR_BINARY_POINT_REGISTER ( *( ( const volatile uint32_t * ) ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCBPR_BINARY_POINT_OFFSET ) ) ) -#define portICCRPR_RUNNING_PRIORITY_REGISTER ( *( ( const volatile uint32_t * ) ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCRPR_RUNNING_PRIORITY_OFFSET ) ) ) +#define portICCPMR_PRIORITY_MASK_OFFSET ( 0x04 ) +#define portICCIAR_INTERRUPT_ACKNOWLEDGE_OFFSET ( 0x0C ) +#define portICCEOIR_END_OF_INTERRUPT_OFFSET ( 0x10 ) +#define portICCBPR_BINARY_POINT_OFFSET ( 0x08 ) +#define portICCRPR_RUNNING_PRIORITY_OFFSET ( 0x14 ) + +#define portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS ( configINTERRUPT_CONTROLLER_BASE_ADDRESS + configINTERRUPT_CONTROLLER_CPU_INTERFACE_OFFSET ) +#define portICCPMR_PRIORITY_MASK_REGISTER ( *( ( volatile uint32_t * ) ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCPMR_PRIORITY_MASK_OFFSET ) ) ) +#define portICCIAR_INTERRUPT_ACKNOWLEDGE_REGISTER_ADDRESS ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCIAR_INTERRUPT_ACKNOWLEDGE_OFFSET ) +#define portICCEOIR_END_OF_INTERRUPT_REGISTER_ADDRESS ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCEOIR_END_OF_INTERRUPT_OFFSET ) +#define portICCPMR_PRIORITY_MASK_REGISTER_ADDRESS ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCPMR_PRIORITY_MASK_OFFSET ) +#define portICCBPR_BINARY_POINT_REGISTER ( *( ( const volatile uint32_t * ) ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCBPR_BINARY_POINT_OFFSET ) ) ) +#define portICCRPR_RUNNING_PRIORITY_REGISTER ( *( ( const volatile uint32_t * ) ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCRPR_RUNNING_PRIORITY_OFFSET ) ) ) /* *INDENT-OFF* */ #ifdef __cplusplus diff --git a/Source/portable/IAR/ARM_CM0/port.c b/Source/portable/IAR/ARM_CM0/port.c index b9999a028..f1373b849 100644 --- a/Source/portable/IAR/ARM_CM0/port.c +++ b/Source/portable/IAR/ARM_CM0/port.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -37,6 +37,9 @@ #include "FreeRTOS.h" #include "task.h" +/* Prototype of all Interrupt Service Routines (ISRs). */ +typedef void ( * portISR_t )( void ); + /* Constants required to manipulate the NVIC. */ #define portNVIC_SYSTICK_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000e010 ) ) #define portNVIC_SYSTICK_LOAD_REG ( *( ( volatile uint32_t * ) 0xe000e014 ) ) @@ -53,6 +56,10 @@ #define portNVIC_PENDSV_PRI ( portMIN_INTERRUPT_PRIORITY << 16UL ) #define portNVIC_SYSTICK_PRI ( portMIN_INTERRUPT_PRIORITY << 24UL ) +/* Constants used to check the installation of the FreeRTOS interrupt handlers. */ +#define portSCB_VTOR_REG ( *( ( portISR_t ** ) 0xe000ed08 ) ) +#define portVECTOR_INDEX_PENDSV ( 14 ) + /* Constants required to set up the initial stack. */ #define portINITIAL_XPSR ( 0x01000000 ) @@ -121,6 +128,10 @@ extern void vPortStartFirstTask( void ); */ static void prvTaskExitError( void ); +/* + * FreeRTOS handlers implemented in assembly. + */ +extern void xPortPendSVHandler( void ); /*-----------------------------------------------------------*/ /* @@ -168,6 +179,41 @@ static void prvTaskExitError( void ) */ BaseType_t xPortStartScheduler( void ) { + /* An application can install FreeRTOS interrupt handlers in one of the + * folllowing ways: + * 1. Direct Routing - Install the function xPortPendSVHandler for PendSV + * interrupt. + * 2. Indirect Routing - Install separate handler for PendSV interrupt and + * route program control from that handler to xPortPendSVHandler function. + * + * Applications that use Indirect Routing must set + * configCHECK_HANDLER_INSTALLATION to 0 in their FreeRTOSConfig.h. Direct + * routing, which is validated here when configCHECK_HANDLER_INSTALLATION + * is 1, should be preferred when possible. */ + #if ( configCHECK_HANDLER_INSTALLATION == 1 ) + { + /* Point pxVectorTable to the interrupt vector table. Systems without + * a VTOR register provide the value zero in the VTOR register and + * the vector table itself is located at the address 0x00000000. */ + const portISR_t * const pxVectorTable = portSCB_VTOR_REG; + + /* Validate that the application has correctly installed the FreeRTOS + * handler for PendSV interrupt. We do not check the installation of the + * SysTick handler because the application may choose to drive the RTOS + * tick using a timer other than the SysTick timer by overriding the + * weak function vPortSetupTimerInterrupt(). + * + * Assertion failures here indicate incorrect installation of the + * FreeRTOS handler. For help installing the FreeRTOS handler, see + * https://www.FreeRTOS.org/FAQHelp.html. + * + * Systems with a configurable address for the interrupt vector table + * can also encounter assertion failures or even system faults here if + * VTOR is not set correctly to point to the application's vector table. */ + configASSERT( pxVectorTable[ portVECTOR_INDEX_PENDSV ] == xPortPendSVHandler ); + } + #endif /* configCHECK_HANDLER_INSTALLATION */ + /* Make PendSV and SysTick the lowest priority interrupts. */ portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI; portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI; @@ -233,13 +279,19 @@ void xPortSysTickHandler( void ) uint32_t ulPreviousMask; ulPreviousMask = portSET_INTERRUPT_MASK_FROM_ISR(); + traceISR_ENTER(); { /* Increment the RTOS tick. */ if( xTaskIncrementTick() != pdFALSE ) { + traceISR_EXIT_TO_SCHEDULER(); /* Pend a context switch. */ portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET; } + else + { + traceISR_EXIT(); + } } portCLEAR_INTERRUPT_MASK_FROM_ISR( ulPreviousMask ); } diff --git a/Source/portable/IAR/ARM_CM0/portasm.s b/Source/portable/IAR/ARM_CM0/portasm.s index 8b5caf299..a8da53c84 100644 --- a/Source/portable/IAR/ARM_CM0/portasm.s +++ b/Source/portable/IAR/ARM_CM0/portasm.s @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -91,15 +91,15 @@ xPortPendSVHandler: vPortSVCHandler; /* This function is no longer used, but retained for backward - compatibility. */ + * compatibility. */ bx lr /*-----------------------------------------------------------*/ vPortStartFirstTask - /* The MSP stack is not reset as, unlike on M3/4 parts, there is no vector - table offset register that can be used to locate the initial stack value. - Not all M0 parts have the application vector table at address 0. */ + /* Don't reset the MSP stack as is done on CM3/4 devices. The vector table + * in some CM0 devices cannot be modified and thus may not hold the + * application's initial MSP value. */ ldr r3, =pxCurrentTCB /* Obtain location of pxCurrentTCB. */ ldr r1, [r3] diff --git a/Source/portable/IAR/ARM_CM0/portmacro.h b/Source/portable/IAR/ARM_CM0/portmacro.h index e0ccf6bc4..66cf85bc7 100644 --- a/Source/portable/IAR/ARM_CM0/portmacro.h +++ b/Source/portable/IAR/ARM_CM0/portmacro.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -86,9 +86,21 @@ typedef unsigned long UBaseType_t; extern void vPortYield( void ); #define portNVIC_INT_CTRL ( ( volatile uint32_t * ) 0xe000ed04 ) #define portNVIC_PENDSVSET 0x10000000 -#define portYIELD() vPortYield() -#define portEND_SWITCHING_ISR( xSwitchRequired ) if( xSwitchRequired ) *( portNVIC_INT_CTRL ) = portNVIC_PENDSVSET -#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x ) +#define portYIELD() vPortYield() +#define portEND_SWITCHING_ISR( xSwitchRequired ) \ + do \ + { \ + if( xSwitchRequired != pdFALSE ) \ + { \ + traceISR_EXIT_TO_SCHEDULER(); \ + *( portNVIC_INT_CTRL ) = portNVIC_PENDSVSET; \ + } \ + else \ + { \ + traceISR_EXIT(); \ + } \ + } while( 0 ) +#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x ) /*-----------------------------------------------------------*/ diff --git a/Source/portable/IAR/ARM_CM23/non_secure/mpu_wrappers_v2_asm.S b/Source/portable/IAR/ARM_CM23/non_secure/mpu_wrappers_v2_asm.S index 4d805f3e2..0b7d942e4 100644 --- a/Source/portable/IAR/ARM_CM23/non_secure/mpu_wrappers_v2_asm.S +++ b/Source/portable/IAR/ARM_CM23/non_secure/mpu_wrappers_v2_asm.S @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -207,21 +207,6 @@ MPU_uxTaskGetNumberOfTasks: svc #SYSTEM_CALL_uxTaskGetNumberOfTasks /*-----------------------------------------------------------*/ - PUBLIC MPU_pcTaskGetName -MPU_pcTaskGetName: - push {r0, r1} - mrs r0, control - movs r1, #1 - tst r0, r1 - bne MPU_pcTaskGetName_Unpriv - MPU_pcTaskGetName_Priv: - pop {r0, r1} - b MPU_pcTaskGetNameImpl - MPU_pcTaskGetName_Unpriv: - pop {r0, r1} - svc #SYSTEM_CALL_pcTaskGetName -/*-----------------------------------------------------------*/ - PUBLIC MPU_ulTaskGetRunTimeCounter MPU_ulTaskGetRunTimeCounter: push {r0, r1} @@ -792,25 +777,19 @@ MPU_xTimerGetTimerDaemonTaskHandle: svc #SYSTEM_CALL_xTimerGetTimerDaemonTaskHandle /*-----------------------------------------------------------*/ - PUBLIC MPU_xTimerGenericCommandEntry -MPU_xTimerGenericCommandEntry: + PUBLIC MPU_xTimerGenericCommandFromTaskEntry +MPU_xTimerGenericCommandFromTaskEntry: push {r0, r1} - /* This function can be called from ISR also and therefore, we need a check - * to take privileged path, if called from ISR. */ - mrs r0, ipsr - cmp r0, #0 - bne MPU_xTimerGenericCommand_Priv mrs r0, control movs r1, #1 tst r0, r1 - beq MPU_xTimerGenericCommand_Priv - MPU_xTimerGenericCommand_Unpriv: + bne MPU_xTimerGenericCommandFromTask_Unpriv + MPU_xTimerGenericCommandFromTask_Priv: pop {r0, r1} - svc #SYSTEM_CALL_xTimerGenericCommand - MPU_xTimerGenericCommand_Priv: + b MPU_xTimerGenericCommandFromTaskImpl + MPU_xTimerGenericCommandFromTask_Unpriv: pop {r0, r1} - b MPU_xTimerGenericCommandPrivImpl - + svc #SYSTEM_CALL_xTimerGenericCommandFromTask /*-----------------------------------------------------------*/ PUBLIC MPU_pcTimerGetName @@ -1160,10 +1139,6 @@ MPU_xTaskGetTickCountImpl: MPU_uxTaskGetNumberOfTasksImpl: b MPU_uxTaskGetNumberOfTasksImpl - PUBWEAK MPU_pcTaskGetNameImpl -MPU_pcTaskGetNameImpl: - b MPU_pcTaskGetNameImpl - PUBWEAK MPU_ulTaskGetRunTimeCounterImpl MPU_ulTaskGetRunTimeCounterImpl: b MPU_ulTaskGetRunTimeCounterImpl @@ -1316,9 +1291,9 @@ MPU_xTimerIsTimerActiveImpl: MPU_xTimerGetTimerDaemonTaskHandleImpl: b MPU_xTimerGetTimerDaemonTaskHandleImpl - PUBWEAK MPU_xTimerGenericCommandPrivImpl -MPU_xTimerGenericCommandPrivImpl: - b MPU_xTimerGenericCommandPrivImpl + PUBWEAK MPU_xTimerGenericCommandFromTaskImpl +MPU_xTimerGenericCommandFromTaskImpl: + b MPU_xTimerGenericCommandFromTaskImpl PUBWEAK MPU_pcTimerGetNameImpl MPU_pcTimerGetNameImpl: diff --git a/Source/portable/IAR/ARM_CM23/non_secure/port.c b/Source/portable/IAR/ARM_CM23/non_secure/port.c index 9712ac353..230fe5fc2 100644 --- a/Source/portable/IAR/ARM_CM23/non_secure/port.c +++ b/Source/portable/IAR/ARM_CM23/non_secure/port.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -68,6 +68,22 @@ #if ( ( configRUN_FREERTOS_SECURE_ONLY == 1 ) && ( configENABLE_TRUSTZONE == 1 ) ) #error TrustZone needs to be disabled in order to run FreeRTOS on the Secure Side. #endif + +/** + * Cortex-M23 does not have non-secure PSPLIM. We should use PSPLIM on Cortex-M23 + * only when FreeRTOS runs on secure side. + */ +#if ( ( portHAS_ARMV8M_MAIN_EXTENSION == 0 ) && ( configRUN_FREERTOS_SECURE_ONLY == 0 ) ) + #define portUSE_PSPLIM_REGISTER 0 +#else + #define portUSE_PSPLIM_REGISTER 1 +#endif +/*-----------------------------------------------------------*/ + +/** + * @brief Prototype of all Interrupt Service Routines (ISRs). + */ +typedef void ( * portISR_t )( void ); /*-----------------------------------------------------------*/ /** @@ -91,10 +107,18 @@ /** * @brief Constants required to manipulate the SCB. */ -#define portSCB_SYS_HANDLER_CTRL_STATE_REG ( *( volatile uint32_t * ) 0xe000ed24 ) +#define portSCB_VTOR_REG ( *( ( portISR_t ** ) 0xe000ed08 ) ) +#define portSCB_SYS_HANDLER_CTRL_STATE_REG ( *( ( volatile uint32_t * ) 0xe000ed24 ) ) #define portSCB_MEM_FAULT_ENABLE_BIT ( 1UL << 16UL ) /*-----------------------------------------------------------*/ +/** + * @brief Constants used to check the installation of the FreeRTOS interrupt handlers. + */ +#define portVECTOR_INDEX_SVC ( 11 ) +#define portVECTOR_INDEX_PENDSV ( 14 ) +/*-----------------------------------------------------------*/ + /** * @brief Constants required to check the validity of an interrupt priority. */ @@ -111,8 +135,8 @@ /** * @brief Constants used during system call enter and exit. */ -#define portPSR_STACK_PADDING_MASK ( 1UL << 9UL ) -#define portEXC_RETURN_STACK_FRAME_TYPE_MASK ( 1UL << 4UL ) +#define portPSR_STACK_PADDING_MASK ( 1UL << 9UL ) +#define portEXC_RETURN_STACK_FRAME_TYPE_MASK ( 1UL << 4UL ) /*-----------------------------------------------------------*/ /** @@ -134,81 +158,81 @@ /** * @brief Offsets in the stack to the parameters when inside the SVC handler. */ -#define portOFFSET_TO_LR ( 5 ) -#define portOFFSET_TO_PC ( 6 ) -#define portOFFSET_TO_PSR ( 7 ) +#define portOFFSET_TO_LR ( 5 ) +#define portOFFSET_TO_PC ( 6 ) +#define portOFFSET_TO_PSR ( 7 ) /*-----------------------------------------------------------*/ /** * @brief Constants required to manipulate the MPU. */ -#define portMPU_TYPE_REG ( *( ( volatile uint32_t * ) 0xe000ed90 ) ) -#define portMPU_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed94 ) ) -#define portMPU_RNR_REG ( *( ( volatile uint32_t * ) 0xe000ed98 ) ) +#define portMPU_TYPE_REG ( *( ( volatile uint32_t * ) 0xe000ed90 ) ) +#define portMPU_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed94 ) ) +#define portMPU_RNR_REG ( *( ( volatile uint32_t * ) 0xe000ed98 ) ) -#define portMPU_RBAR_REG ( *( ( volatile uint32_t * ) 0xe000ed9c ) ) -#define portMPU_RLAR_REG ( *( ( volatile uint32_t * ) 0xe000eda0 ) ) +#define portMPU_RBAR_REG ( *( ( volatile uint32_t * ) 0xe000ed9c ) ) +#define portMPU_RLAR_REG ( *( ( volatile uint32_t * ) 0xe000eda0 ) ) -#define portMPU_RBAR_A1_REG ( *( ( volatile uint32_t * ) 0xe000eda4 ) ) -#define portMPU_RLAR_A1_REG ( *( ( volatile uint32_t * ) 0xe000eda8 ) ) +#define portMPU_RBAR_A1_REG ( *( ( volatile uint32_t * ) 0xe000eda4 ) ) +#define portMPU_RLAR_A1_REG ( *( ( volatile uint32_t * ) 0xe000eda8 ) ) -#define portMPU_RBAR_A2_REG ( *( ( volatile uint32_t * ) 0xe000edac ) ) -#define portMPU_RLAR_A2_REG ( *( ( volatile uint32_t * ) 0xe000edb0 ) ) +#define portMPU_RBAR_A2_REG ( *( ( volatile uint32_t * ) 0xe000edac ) ) +#define portMPU_RLAR_A2_REG ( *( ( volatile uint32_t * ) 0xe000edb0 ) ) -#define portMPU_RBAR_A3_REG ( *( ( volatile uint32_t * ) 0xe000edb4 ) ) -#define portMPU_RLAR_A3_REG ( *( ( volatile uint32_t * ) 0xe000edb8 ) ) +#define portMPU_RBAR_A3_REG ( *( ( volatile uint32_t * ) 0xe000edb4 ) ) +#define portMPU_RLAR_A3_REG ( *( ( volatile uint32_t * ) 0xe000edb8 ) ) -#define portMPU_MAIR0_REG ( *( ( volatile uint32_t * ) 0xe000edc0 ) ) -#define portMPU_MAIR1_REG ( *( ( volatile uint32_t * ) 0xe000edc4 ) ) +#define portMPU_MAIR0_REG ( *( ( volatile uint32_t * ) 0xe000edc0 ) ) +#define portMPU_MAIR1_REG ( *( ( volatile uint32_t * ) 0xe000edc4 ) ) -#define portMPU_RBAR_ADDRESS_MASK ( 0xffffffe0 ) /* Must be 32-byte aligned. */ -#define portMPU_RLAR_ADDRESS_MASK ( 0xffffffe0 ) /* Must be 32-byte aligned. */ +#define portMPU_RBAR_ADDRESS_MASK ( 0xffffffe0 ) /* Must be 32-byte aligned. */ +#define portMPU_RLAR_ADDRESS_MASK ( 0xffffffe0 ) /* Must be 32-byte aligned. */ -#define portMPU_RBAR_ACCESS_PERMISSIONS_MASK ( 3UL << 1UL ) +#define portMPU_RBAR_ACCESS_PERMISSIONS_MASK ( 3UL << 1UL ) -#define portMPU_MAIR_ATTR0_POS ( 0UL ) -#define portMPU_MAIR_ATTR0_MASK ( 0x000000ff ) +#define portMPU_MAIR_ATTR0_POS ( 0UL ) +#define portMPU_MAIR_ATTR0_MASK ( 0x000000ff ) -#define portMPU_MAIR_ATTR1_POS ( 8UL ) -#define portMPU_MAIR_ATTR1_MASK ( 0x0000ff00 ) +#define portMPU_MAIR_ATTR1_POS ( 8UL ) +#define portMPU_MAIR_ATTR1_MASK ( 0x0000ff00 ) -#define portMPU_MAIR_ATTR2_POS ( 16UL ) -#define portMPU_MAIR_ATTR2_MASK ( 0x00ff0000 ) +#define portMPU_MAIR_ATTR2_POS ( 16UL ) +#define portMPU_MAIR_ATTR2_MASK ( 0x00ff0000 ) -#define portMPU_MAIR_ATTR3_POS ( 24UL ) -#define portMPU_MAIR_ATTR3_MASK ( 0xff000000 ) +#define portMPU_MAIR_ATTR3_POS ( 24UL ) +#define portMPU_MAIR_ATTR3_MASK ( 0xff000000 ) -#define portMPU_MAIR_ATTR4_POS ( 0UL ) -#define portMPU_MAIR_ATTR4_MASK ( 0x000000ff ) +#define portMPU_MAIR_ATTR4_POS ( 0UL ) +#define portMPU_MAIR_ATTR4_MASK ( 0x000000ff ) -#define portMPU_MAIR_ATTR5_POS ( 8UL ) -#define portMPU_MAIR_ATTR5_MASK ( 0x0000ff00 ) +#define portMPU_MAIR_ATTR5_POS ( 8UL ) +#define portMPU_MAIR_ATTR5_MASK ( 0x0000ff00 ) -#define portMPU_MAIR_ATTR6_POS ( 16UL ) -#define portMPU_MAIR_ATTR6_MASK ( 0x00ff0000 ) +#define portMPU_MAIR_ATTR6_POS ( 16UL ) +#define portMPU_MAIR_ATTR6_MASK ( 0x00ff0000 ) -#define portMPU_MAIR_ATTR7_POS ( 24UL ) -#define portMPU_MAIR_ATTR7_MASK ( 0xff000000 ) +#define portMPU_MAIR_ATTR7_POS ( 24UL ) +#define portMPU_MAIR_ATTR7_MASK ( 0xff000000 ) -#define portMPU_RLAR_ATTR_INDEX0 ( 0UL << 1UL ) -#define portMPU_RLAR_ATTR_INDEX1 ( 1UL << 1UL ) -#define portMPU_RLAR_ATTR_INDEX2 ( 2UL << 1UL ) -#define portMPU_RLAR_ATTR_INDEX3 ( 3UL << 1UL ) -#define portMPU_RLAR_ATTR_INDEX4 ( 4UL << 1UL ) -#define portMPU_RLAR_ATTR_INDEX5 ( 5UL << 1UL ) -#define portMPU_RLAR_ATTR_INDEX6 ( 6UL << 1UL ) -#define portMPU_RLAR_ATTR_INDEX7 ( 7UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX0 ( 0UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX1 ( 1UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX2 ( 2UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX3 ( 3UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX4 ( 4UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX5 ( 5UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX6 ( 6UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX7 ( 7UL << 1UL ) -#define portMPU_RLAR_REGION_ENABLE ( 1UL ) +#define portMPU_RLAR_REGION_ENABLE ( 1UL ) /* Enable privileged access to unmapped region. */ -#define portMPU_PRIV_BACKGROUND_ENABLE_BIT ( 1UL << 2UL ) +#define portMPU_PRIV_BACKGROUND_ENABLE_BIT ( 1UL << 2UL ) /* Enable MPU. */ -#define portMPU_ENABLE_BIT ( 1UL << 0UL ) +#define portMPU_ENABLE_BIT ( 1UL << 0UL ) /* Expected value of the portMPU_TYPE register. */ -#define portEXPECTED_MPU_TYPE_VALUE ( configTOTAL_MPU_REGIONS << 8UL ) +#define portEXPECTED_MPU_TYPE_VALUE ( configTOTAL_MPU_REGIONS << 8UL ) /* Extract first address of the MPU region as encoded in the * RBAR (Region Base Address Register) value. */ @@ -448,13 +472,13 @@ portDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIV #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) - /** - * @brief Sets up the task stack so that upon returning from - * SVC, the task stack is used again. - * - * @param pulSystemCallStack The current SP when the SVC was raised. - * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler. - */ +/** + * @brief Sets up the task stack so that upon returning from + * SVC, the task stack is used again. + * + * @param pulSystemCallStack The current SP when the SVC was raised. + * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler. + */ void vSystemCallExit( uint32_t * pulSystemCallStack, uint32_t ulLR ) PRIVILEGED_FUNCTION; @@ -462,11 +486,11 @@ portDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIV #if ( configENABLE_MPU == 1 ) - /** - * @brief Checks whether or not the calling task is privileged. - * - * @return pdTRUE if the calling task is privileged, pdFALSE otherwise. - */ +/** + * @brief Checks whether or not the calling task is privileged. + * + * @return pdTRUE if the calling task is privileged, pdFALSE otherwise. + */ BaseType_t xPortIsTaskPrivileged( void ) PRIVILEGED_FUNCTION; #endif /* configENABLE_MPU == 1 */ @@ -501,13 +525,13 @@ PRIVILEGED_DATA static volatile uint32_t ulCriticalNesting = 0xaaaaaaaaUL; * FreeRTOS API functions are not called from interrupts that have been assigned * a priority above configMAX_SYSCALL_INTERRUPT_PRIORITY. */ -#if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) ) +#if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) static uint8_t ucMaxSysCallPriority = 0; static uint32_t ulMaxPRIGROUPValue = 0; static const volatile uint8_t * const pcInterruptPriorityRegisters = ( const volatile uint8_t * ) portNVIC_IP_REGISTERS_OFFSET_16; -#endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) ) */ +#endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */ #if ( configUSE_TICKLESS_IDLE == 1 ) @@ -760,8 +784,15 @@ __attribute__( ( weak ) ) void vPortSetupTimerInterrupt( void ) /* PRIVILEGED_FU } #endif /* configUSE_TICKLESS_IDLE */ - /* Stop and reset the SysTick. */ - portNVIC_SYSTICK_CTRL_REG = 0UL; + /* Stop and reset SysTick. + * + * QEMU versions older than 7.0.0 contain a bug which causes an error if we + * enable SysTick without first selecting a valid clock source. We trigger + * the bug if we change clock sources from a clock with a zero clock period + * to one with a nonzero clock period and enable Systick at the same time. + * So we configure the CLKSOURCE bit here, prior to setting the ENABLE bit. + * This workaround avoids the bug in QEMU versions older than 7.0.0. */ + portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT_CONFIG; portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL; /* Configure SysTick to interrupt at the requested rate. */ @@ -819,6 +850,7 @@ static void prvTaskExitError( void ) static void prvSetupMPU( void ) /* PRIVILEGED_FUNCTION */ { #if defined( __ARMCC_VERSION ) + /* Declaration when these variable are defined in code instead of being * exported from linker scripts. */ extern uint32_t * __privileged_functions_start__; @@ -972,13 +1004,19 @@ void SysTick_Handler( void ) /* PRIVILEGED_FUNCTION */ uint32_t ulPreviousMask; ulPreviousMask = portSET_INTERRUPT_MASK_FROM_ISR(); + traceISR_ENTER(); { /* Increment the RTOS tick. */ if( xTaskIncrementTick() != pdFALSE ) { + traceISR_EXIT_TO_SCHEDULER(); /* Pend a context switch. */ portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; } + else + { + traceISR_EXIT(); + } } portCLEAR_INTERRUPT_MASK_FROM_ISR( ulPreviousMask ); } @@ -988,6 +1026,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO { #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) ) #if defined( __ARMCC_VERSION ) + /* Declaration when these variable are defined in code instead of being * exported from linker scripts. */ extern uint32_t * __syscalls_flash_start__; @@ -1083,18 +1122,24 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO vRestoreContextOfFirstTask(); break; - #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) ) - case portSVC_RAISE_PRIVILEGE: + #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) ) + case portSVC_RAISE_PRIVILEGE: - /* Only raise the privilege, if the svc was raised from any of - * the system calls. */ - if( ( ulPC >= ( uint32_t ) __syscalls_flash_start__ ) && - ( ulPC <= ( uint32_t ) __syscalls_flash_end__ ) ) - { - vRaisePrivilege(); - } - break; - #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) */ + /* Only raise the privilege, if the svc was raised from any of + * the system calls. */ + if( ( ulPC >= ( uint32_t ) __syscalls_flash_start__ ) && + ( ulPC <= ( uint32_t ) __syscalls_flash_end__ ) ) + { + vRaisePrivilege(); + } + break; + #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) */ + + #if ( configENABLE_MPU == 1 ) + case portSVC_YIELD: + vPortYield(); + break; + #endif /* configENABLE_MPU == 1 */ default: /* Incorrect SVC call. */ @@ -1154,12 +1199,11 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO { /* Extended frame i.e. FPU in use. */ ulStackFrameSize = 26; - __asm volatile - ( + __asm volatile ( " vpush {s0} \n" /* Trigger lazy stacking. */ " vpop {s0} \n" /* Nullify the affect of the above instruction. */ ::: "memory" - ); + ); } else { @@ -1171,7 +1215,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO { ulStackFrameSize = 8; } - #endif /* if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */ + #endif /* configENABLE_FPU || configENABLE_MVE */ /* Make space on the system call stack for the stack frame. */ pulSystemCallStack = pulSystemCallStack - ulStackFrameSize; @@ -1187,18 +1231,24 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO * point (i.e. the caller of the MPU_). We need to restore it * when we exit from the system call. */ pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry = pulTaskStack[ portOFFSET_TO_LR ]; - /* Store the value of the PSPLIM register before the SVC was raised. * We need to restore it when we exit from the system call. */ - __asm volatile ( "mrs %0, psplim" : "=r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) ); + #if ( portUSE_PSPLIM_REGISTER == 1 ) + { + __asm volatile ( "mrs %0, psplim" : "=r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) ); + } + #endif /* Use the pulSystemCallStack in thread mode. */ __asm volatile ( "msr psp, %0" : : "r" ( pulSystemCallStack ) ); - __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) ); + #if ( portUSE_PSPLIM_REGISTER == 1 ) + { + __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) ); + } + #endif /* Start executing the system call upon returning from this handler. */ pulSystemCallStack[ portOFFSET_TO_PC ] = uxSystemCallImplementations[ ucSystemCallNumber ]; - /* Raise a request to exit from the system call upon finishing the * system call. */ pulSystemCallStack[ portOFFSET_TO_LR ] = ( uint32_t ) vRequestSystemCallExit; @@ -1224,14 +1274,13 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO pulSystemCallStack[ portOFFSET_TO_PSR ] &= ( ~portPSR_STACK_PADDING_MASK ); /* Raise the privilege for the duration of the system call. */ - __asm volatile - ( + __asm volatile ( " mrs r0, control \n" /* Obtain current control value. */ " movs r1, #1 \n" /* r1 = 1. */ " bics r0, r1 \n" /* Clear nPRIV bit. */ " msr control, r0 \n" /* Write back new control value. */ ::: "r0", "r1", "memory" - ); + ); } } @@ -1293,12 +1342,11 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO { /* Extended frame i.e. FPU in use. */ ulStackFrameSize = 26; - __asm volatile - ( + __asm volatile ( " vpush {s0} \n" /* Trigger lazy stacking. */ " vpop {s0} \n" /* Nullify the affect of the above instruction. */ ::: "memory" - ); + ); } else { @@ -1310,7 +1358,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO { ulStackFrameSize = 8; } - #endif /* if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */ + #endif /* configENABLE_FPU || configENABLE_MVE */ /* Make space on the task stack for the stack frame. */ pulTaskStack = pulTaskStack - ulStackFrameSize; @@ -1332,7 +1380,11 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO /* Restore the PSPLIM register to what it was at the time of * system call entry. */ - __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) ); + #if ( portUSE_PSPLIM_REGISTER == 1 ) + { + __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) ); + } + #endif /* If the hardware used padding to force the stack pointer * to be double word aligned, set the stacked xPSR bit[9], @@ -1350,14 +1402,13 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO pxMpuSettings->xSystemCallStackInfo.pulTaskStack = NULL; /* Drop the privilege before returning to the thread mode. */ - __asm volatile - ( + __asm volatile ( " mrs r0, control \n" /* Obtain current control value. */ " movs r1, #1 \n" /* r1 = 1. */ " orrs r0, r1 \n" /* Set nPRIV bit. */ " msr control, r0 \n" /* Write back new control value. */ ::: "r0", "r1", "memory" - ); + ); } } @@ -1410,21 +1461,21 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO xMPUSettings->ulContext[ ulIndex ] = 0x11111111; /* r11. */ ulIndex++; - xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pvParameters; /* r0. */ + xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pvParameters; /* r0. */ ulIndex++; - xMPUSettings->ulContext[ ulIndex ] = 0x01010101; /* r1. */ + xMPUSettings->ulContext[ ulIndex ] = 0x01010101; /* r1. */ ulIndex++; - xMPUSettings->ulContext[ ulIndex ] = 0x02020202; /* r2. */ + xMPUSettings->ulContext[ ulIndex ] = 0x02020202; /* r2. */ ulIndex++; - xMPUSettings->ulContext[ ulIndex ] = 0x03030303; /* r3. */ + xMPUSettings->ulContext[ ulIndex ] = 0x03030303; /* r3. */ ulIndex++; - xMPUSettings->ulContext[ ulIndex ] = 0x12121212; /* r12. */ + xMPUSettings->ulContext[ ulIndex ] = 0x12121212; /* r12. */ ulIndex++; xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portTASK_RETURN_ADDRESS; /* LR. */ ulIndex++; - xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxCode; /* PC. */ + xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxCode; /* PC. */ ulIndex++; - xMPUSettings->ulContext[ ulIndex ] = portINITIAL_XPSR; /* xPSR. */ + xMPUSettings->ulContext[ ulIndex ] = portINITIAL_XPSR; /* xPSR. */ ulIndex++; #if ( configENABLE_TRUSTZONE == 1 ) @@ -1435,8 +1486,9 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO #endif /* configENABLE_TRUSTZONE */ xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) ( pxTopOfStack - 8 ); /* PSP with the hardware saved stack. */ ulIndex++; - xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxEndOfStack; /* PSPLIM. */ + xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxEndOfStack; /* PSPLIM. */ ulIndex++; + if( xRunPrivileged == pdTRUE ) { xMPUSettings->ulTaskFlags |= portTASK_IS_PRIVILEGED_FLAG; @@ -1449,6 +1501,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portINITIAL_CONTROL_UNPRIVILEGED; /* CONTROL. */ ulIndex++; } + xMPUSettings->ulContext[ ulIndex ] = portINITIAL_EXC_RETURN; /* LR (EXC_RETURN). */ ulIndex++; @@ -1483,7 +1536,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO * interrupt. */ #if ( portPRELOAD_REGISTERS == 0 ) { - pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */ + pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */ *pxTopOfStack = portINITIAL_XPSR; /* xPSR. */ pxTopOfStack--; *pxTopOfStack = ( StackType_t ) pxCode; /* PC. */ @@ -1505,7 +1558,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO } #else /* portPRELOAD_REGISTERS */ { - pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */ + pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */ *pxTopOfStack = portINITIAL_XPSR; /* xPSR. */ pxTopOfStack--; *pxTopOfStack = ( StackType_t ) pxCode; /* PC. */ @@ -1540,7 +1593,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO pxTopOfStack--; *pxTopOfStack = portINITIAL_EXC_RETURN; /* EXC_RETURN. */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */ + *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */ #if ( configENABLE_TRUSTZONE == 1 ) { @@ -1559,22 +1612,52 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */ { - #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) ) + /* An application can install FreeRTOS interrupt handlers in one of the + * folllowing ways: + * 1. Direct Routing - Install the functions SVC_Handler and PendSV_Handler + * for SVCall and PendSV interrupts respectively. + * 2. Indirect Routing - Install separate handlers for SVCall and PendSV + * interrupts and route program control from those handlers to + * SVC_Handler and PendSV_Handler functions. + * + * Applications that use Indirect Routing must set + * configCHECK_HANDLER_INSTALLATION to 0 in their FreeRTOSConfig.h. Direct + * routing, which is validated here when configCHECK_HANDLER_INSTALLATION + * is 1, should be preferred when possible. */ + #if ( configCHECK_HANDLER_INSTALLATION == 1 ) + { + const portISR_t * const pxVectorTable = portSCB_VTOR_REG; + + /* Validate that the application has correctly installed the FreeRTOS + * handlers for SVCall and PendSV interrupts. We do not check the + * installation of the SysTick handler because the application may + * choose to drive the RTOS tick using a timer other than the SysTick + * timer by overriding the weak function vPortSetupTimerInterrupt(). + * + * Assertion failures here indicate incorrect installation of the + * FreeRTOS handlers. For help installing the FreeRTOS handlers, see + * https://www.FreeRTOS.org/FAQHelp.html. + * + * Systems with a configurable address for the interrupt vector table + * can also encounter assertion failures or even system faults here if + * VTOR is not set correctly to point to the application's vector table. */ + configASSERT( pxVectorTable[ portVECTOR_INDEX_SVC ] == SVC_Handler ); + configASSERT( pxVectorTable[ portVECTOR_INDEX_PENDSV ] == PendSV_Handler ); + } + #endif /* configCHECK_HANDLER_INSTALLATION */ + + #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) { - volatile uint32_t ulOriginalPriority; volatile uint32_t ulImplementedPrioBits = 0; volatile uint8_t ucMaxPriorityValue; /* Determine the maximum priority from which ISR safe FreeRTOS API - * functions can be called. ISR safe functions are those that end in - * "FromISR". FreeRTOS maintains separate thread and ISR API functions to + * functions can be called. ISR safe functions are those that end in + * "FromISR". FreeRTOS maintains separate thread and ISR API functions to * ensure interrupt entry is as fast and simple as possible. * - * Save the interrupt priority value that is about to be clobbered. */ - ulOriginalPriority = portNVIC_SHPR2_REG; - - /* Determine the number of priority bits available. First write to all - * possible bits. */ + * First, determine the number of priority bits available. Write to all + * possible bits in the priority setting for SVCall. */ portNVIC_SHPR2_REG = 0xFF000000; /* Read the value back to see how many bits stuck. */ @@ -1593,11 +1676,10 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */ /* Check that the bits not implemented in hardware are zero in * configMAX_SYSCALL_INTERRUPT_PRIORITY. */ - configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( ~ucMaxPriorityValue ) ) == 0U ); + configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( uint8_t ) ( ~( uint32_t ) ucMaxPriorityValue ) ) == 0U ); /* Calculate the maximum acceptable priority group value for the number * of bits read back. */ - while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE ) { ulImplementedPrioBits++; @@ -1635,16 +1717,14 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */ * register. */ ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT; ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK; - - /* Restore the clobbered interrupt priority register to its original - * value. */ - portNVIC_SHPR2_REG = ulOriginalPriority; } - #endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) ) */ + #endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */ - /* Make PendSV, CallSV and SysTick the same priority as the kernel. */ + /* Make PendSV and SysTick the lowest priority interrupts, and make SVCall + * the highest priority. */ portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI; portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI; + portNVIC_SHPR2_REG = 0; #if ( configENABLE_MPU == 1 ) { @@ -1701,6 +1781,7 @@ void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */ int32_t lIndex = 0; #if defined( __ARMCC_VERSION ) + /* Declaration when these variable are defined in code instead of being * exported from linker scripts. */ extern uint32_t * __privileged_sram_start__; @@ -1886,7 +1967,7 @@ BaseType_t xPortIsInsideInterrupt( void ) } /*-----------------------------------------------------------*/ -#if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) ) +#if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) void vPortValidateInterruptPriority( void ) { @@ -1944,7 +2025,7 @@ BaseType_t xPortIsInsideInterrupt( void ) configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue ); } -#endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) ) */ +#endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */ /*-----------------------------------------------------------*/ #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) diff --git a/Source/portable/IAR/ARM_CM23/non_secure/portasm.h b/Source/portable/IAR/ARM_CM23/non_secure/portasm.h index f64ceb525..c6d2ebd58 100644 --- a/Source/portable/IAR/ARM_CM23/non_secure/portasm.h +++ b/Source/portable/IAR/ARM_CM23/non_secure/portasm.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/Source/portable/IAR/ARM_CM23/non_secure/portasm.s b/Source/portable/IAR/ARM_CM23/non_secure/portasm.s index 3c1788998..276fb3969 100644 --- a/Source/portable/IAR/ARM_CM23/non_secure/portasm.s +++ b/Source/portable/IAR/ARM_CM23/non_secure/portasm.s @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -40,6 +40,7 @@ files (__ICCARM__ is defined by the IAR C compiler but not by the IAR assembler. #define configUSE_MPU_WRAPPERS_V1 0 #endif + EXTERN pxCurrentTCB EXTERN xSecureContext EXTERN vTaskSwitchContext @@ -169,7 +170,6 @@ vRestoreContextOfFirstTask: ldmia r2!, {r0, r3-r6} /* r0 = xSecureContext, r3 = original PSP, r4 = PSPLIM, r5 = CONTROL, r6 = LR. */ subs r2, #20 msr psp, r3 - msr psplim, r4 msr control, r5 mov lr, r6 ldr r4, =xSecureContext /* Read the location of xSecureContext i.e. &( xSecureContext ). */ @@ -205,7 +205,6 @@ vRestoreContextOfFirstTask: ldm r0!, {r1-r3} /* Read from stack - r1 = xSecureContext, r2 = PSPLIM and r3 = EXC_RETURN. */ ldr r4, =xSecureContext str r1, [r4] /* Set xSecureContext to this task's value for the same. */ - msr psplim, r2 /* Set this task's PSPLIM value. */ movs r1, #2 /* r1 = 2. */ msr CONTROL, r1 /* Switch to use PSP in the thread mode. */ adds r0, #32 /* Discard everything up to r0. */ @@ -281,7 +280,7 @@ PendSV_Handler: save_special_regs: mrs r3, psp /* r3 = PSP. */ - mrs r4, psplim /* r4 = PSPLIM. */ + movs r4, #0 /* r4 = 0. 0 is stored in the PSPLIM slot. */ mrs r5, control /* r5 = CONTROL. */ mov r6, lr /* r6 = LR. */ stmia r2!, {r0, r3-r6} /* Store xSecureContext, original PSP (after hardware has saved context), PSPLIM, CONTROL and LR. */ @@ -349,7 +348,6 @@ PendSV_Handler: ldmia r2!, {r0, r3-r6} /* r0 = xSecureContext, r3 = original PSP, r4 = PSPLIM, r5 = CONTROL, r6 = LR. */ subs r2, #20 msr psp, r3 - msr psplim, r4 msr control, r5 mov lr, r6 ldr r4, =xSecureContext /* Read the location of xSecureContext i.e. &( xSecureContext ). */ @@ -408,7 +406,7 @@ PendSV_Handler: subs r2, r2, #12 /* Make space for xSecureContext, PSPLIM and LR on the stack. */ str r2, [r1] /* Save the new top of stack in TCB. */ - mrs r1, psplim /* r1 = PSPLIM. */ + movs r1, #0 /* r1 = 0. 0 is stored in the PSPLIM slot. */ mov r3, lr /* r3 = LR/EXC_RETURN. */ stmia r2!, {r0, r1, r3} /* Store xSecureContext, PSPLIM and LR on the stack. */ @@ -419,7 +417,7 @@ PendSV_Handler: ldr r1, [r3] /* Read pxCurrentTCB. */ subs r2, r2, #44 /* Make space for xSecureContext, PSPLIM, LR and the remaining registers on the stack. */ str r2, [r1] /* Save the new top of stack in TCB. */ - mrs r1, psplim /* r1 = PSPLIM. */ + movs r1, #0 /* r1 = 0. 0 is stored in the PSPLIM slot. */ mov r3, lr /* r3 = LR/EXC_RETURN. */ stmia r2!, {r0, r1, r3-r7} /* Store xSecureContext, PSPLIM, LR and the low registers that are not saved automatically. */ mov r4, r8 /* r4 = r8. */ @@ -438,7 +436,6 @@ PendSV_Handler: ldr r2, [r1] /* The first item in pxCurrentTCB is the task top of stack. r2 now points to the top of stack. */ ldmia r2!, {r0, r1, r4} /* Read from stack - r0 = xSecureContext, r1 = PSPLIM and r4 = LR. */ - msr psplim, r1 /* Restore the PSPLIM register value for the task. */ mov lr, r4 /* LR = r4. */ ldr r3, =xSecureContext /* Read the location of xSecureContext i.e. &( xSecureContext ). */ str r0, [r3] /* Restore the task's xSecureContext. */ diff --git a/Source/portable/IAR/ARM_CM23/non_secure/portmacro.h b/Source/portable/IAR/ARM_CM23/non_secure/portmacro.h index 19d7556fb..52ab2a3ac 100644 --- a/Source/portable/IAR/ARM_CM23/non_secure/portmacro.h +++ b/Source/portable/IAR/ARM_CM23/non_secure/portmacro.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -48,9 +48,9 @@ /** * Architecture specifics. */ -#define portARCH_NAME "Cortex-M23" -#define portHAS_BASEPRI 0 -#define portDONT_DISCARD __root +#define portARCH_NAME "Cortex-M23" +#define portHAS_ARMV8M_MAIN_EXTENSION 0 +#define portDONT_DISCARD __root /*-----------------------------------------------------------*/ /* ARMv8-M common port configurations. */ diff --git a/Source/portable/IAR/ARM_CM23/non_secure/portmacrocommon.h b/Source/portable/IAR/ARM_CM23/non_secure/portmacrocommon.h index 6f666da22..33f21d85b 100644 --- a/Source/portable/IAR/ARM_CM23/non_secure/portmacrocommon.h +++ b/Source/portable/IAR/ARM_CM23/non_secure/portmacrocommon.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -117,7 +117,7 @@ extern uint32_t ulSetInterruptMask( void ) /* __attribute__(( naked )) PRIVILEGE extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */; #if ( configENABLE_TRUSTZONE == 1 ) - extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize ); /* __attribute__ (( naked )) */ + extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize ); /* __attribute__ (( naked )) */ extern void vPortFreeSecureContext( uint32_t * pulTCB ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */; #endif /* configENABLE_TRUSTZONE */ @@ -188,13 +188,13 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P #if ( configENABLE_MPU == 1 ) - /** - * @brief Settings to define an MPU region. - */ +/** + * @brief Settings to define an MPU region. + */ typedef struct MPURegionSettings { - uint32_t ulRBAR; /**< RBAR for the region. */ - uint32_t ulRLAR; /**< RLAR for the region. */ + uint32_t ulRBAR; /**< RBAR for the region. */ + uint32_t ulRLAR; /**< RLAR for the region. */ } MPURegionSettings_t; #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) @@ -203,9 +203,9 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P #error configSYSTEM_CALL_STACK_SIZE must be defined to the desired size of the system call stack in words for using MPU wrappers v2. #endif - /** - * @brief System call stack. - */ +/** + * @brief System call stack. + */ typedef struct SYSTEM_CALL_STACK_INFO { uint32_t ulSystemCallStackBuffer[ configSYSTEM_CALL_STACK_SIZE ]; @@ -218,74 +218,74 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P #endif /* configUSE_MPU_WRAPPERS_V1 == 0 */ - /** - * @brief MPU settings as stored in the TCB. - */ +/** + * @brief MPU settings as stored in the TCB. + */ #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) - #if( configENABLE_TRUSTZONE == 1 ) + #if ( configENABLE_TRUSTZONE == 1 ) - /* - * +-----------+---------------+----------+-----------------+------------------------------+-----+ - * | s16-s31 | s0-s15, FPSCR | r4-r11 | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, | | - * | | | | PC, xPSR | CONTROL, EXC_RETURN | | - * +-----------+---------------+----------+-----------------+------------------------------+-----+ - * - * <-----------><--------------><---------><----------------><-----------------------------><----> - * 16 16 8 8 5 1 - */ - #define MAX_CONTEXT_SIZE 54 +/* + * +-----------+---------------+----------+-----------------+------------------------------+-----+ + * | s16-s31 | s0-s15, FPSCR | r4-r11 | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, | | + * | | | | PC, xPSR | CONTROL, EXC_RETURN | | + * +-----------+---------------+----------+-----------------+------------------------------+-----+ + * + * <-----------><--------------><---------><----------------><-----------------------------><----> + * 16 16 8 8 5 1 + */ + #define MAX_CONTEXT_SIZE 54 #else /* #if( configENABLE_TRUSTZONE == 1 ) */ - /* - * +-----------+---------------+----------+-----------------+----------------------+-----+ - * | s16-s31 | s0-s15, FPSCR | r4-r11 | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL | | - * | | | | PC, xPSR | EXC_RETURN | | - * +-----------+---------------+----------+-----------------+----------------------+-----+ - * - * <-----------><--------------><---------><----------------><---------------------><----> - * 16 16 8 8 4 1 - */ - #define MAX_CONTEXT_SIZE 53 +/* + * +-----------+---------------+----------+-----------------+----------------------+-----+ + * | s16-s31 | s0-s15, FPSCR | r4-r11 | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL | | + * | | | | PC, xPSR | EXC_RETURN | | + * +-----------+---------------+----------+-----------------+----------------------+-----+ + * + * <-----------><--------------><---------><----------------><---------------------><----> + * 16 16 8 8 4 1 + */ + #define MAX_CONTEXT_SIZE 53 #endif /* #if( configENABLE_TRUSTZONE == 1 ) */ #else /* #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */ - #if( configENABLE_TRUSTZONE == 1 ) + #if ( configENABLE_TRUSTZONE == 1 ) - /* - * +----------+-----------------+------------------------------+-----+ - * | r4-r11 | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, | | - * | | PC, xPSR | CONTROL, EXC_RETURN | | - * +----------+-----------------+------------------------------+-----+ - * - * <---------><----------------><------------------------------><----> - * 8 8 5 1 - */ - #define MAX_CONTEXT_SIZE 22 +/* + * +----------+-----------------+------------------------------+-----+ + * | r4-r11 | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, | | + * | | PC, xPSR | CONTROL, EXC_RETURN | | + * +----------+-----------------+------------------------------+-----+ + * + * <---------><----------------><------------------------------><----> + * 8 8 5 1 + */ + #define MAX_CONTEXT_SIZE 22 #else /* #if( configENABLE_TRUSTZONE == 1 ) */ - /* - * +----------+-----------------+----------------------+-----+ - * | r4-r11 | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL | | - * | | PC, xPSR | EXC_RETURN | | - * +----------+-----------------+----------------------+-----+ - * - * <---------><----------------><----------------------><----> - * 8 8 4 1 - */ - #define MAX_CONTEXT_SIZE 21 +/* + * +----------+-----------------+----------------------+-----+ + * | r4-r11 | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL | | + * | | PC, xPSR | EXC_RETURN | | + * +----------+-----------------+----------------------+-----+ + * + * <---------><----------------><----------------------><----> + * 8 8 4 1 + */ + #define MAX_CONTEXT_SIZE 21 #endif /* #if( configENABLE_TRUSTZONE == 1 ) */ #endif /* #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */ - /* Flags used for xMPU_SETTINGS.ulTaskFlags member. */ - #define portSTACK_FRAME_HAS_PADDING_FLAG ( 1UL << 0UL ) - #define portTASK_IS_PRIVILEGED_FLAG ( 1UL << 1UL ) +/* Flags used for xMPU_SETTINGS.ulTaskFlags member. */ + #define portSTACK_FRAME_HAS_PADDING_FLAG ( 1UL << 0UL ) + #define portTASK_IS_PRIVILEGED_FLAG ( 1UL << 1UL ) /* Size of an Access Control List (ACL) entry in bits. */ #define portACL_ENTRY_SIZE_BITS ( 32U ) @@ -313,7 +313,7 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P * system calls. */ #ifdef configASSERT - #if ( portHAS_BASEPRI == 1 ) + #if ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) void vPortValidateInterruptPriority( void ); #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() vPortValidateInterruptPriority() #endif @@ -333,12 +333,29 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P /** * @brief Scheduler utilities. */ -#define portYIELD() vPortYield() +#if ( configENABLE_MPU == 1 ) + #define portYIELD() __asm volatile ( "svc %0" ::"i" ( portSVC_YIELD ) : "memory" ) + #define portYIELD_WITHIN_API() vPortYield() +#else + #define portYIELD() vPortYield() + #define portYIELD_WITHIN_API() vPortYield() +#endif + #define portNVIC_INT_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed04 ) ) #define portNVIC_PENDSVSET_BIT ( 1UL << 28UL ) -#define portEND_SWITCHING_ISR( xSwitchRequired ) \ - do { if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; } \ - while( 0 ) +#define portEND_SWITCHING_ISR( xSwitchRequired ) \ + do \ + { \ + if( xSwitchRequired ) \ + { \ + traceISR_EXIT_TO_SCHEDULER(); \ + portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; \ + } \ + else \ + { \ + traceISR_EXIT(); \ + } \ + } while( 0 ) #define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x ) /*-----------------------------------------------------------*/ @@ -424,12 +441,12 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P extern BaseType_t xPortIsTaskPrivileged( void ); - /** - * @brief Checks whether or not the calling task is privileged. - * - * @return pdTRUE if the calling task is privileged, pdFALSE otherwise. - */ - #define portIS_TASK_PRIVILEGED() xPortIsTaskPrivileged() +/** + * @brief Checks whether or not the calling task is privileged. + * + * @return pdTRUE if the calling task is privileged, pdFALSE otherwise. + */ + #define portIS_TASK_PRIVILEGED() xPortIsTaskPrivileged() #endif /* configENABLE_MPU == 1 */ /*-----------------------------------------------------------*/ @@ -440,6 +457,56 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P #define portMEMORY_BARRIER() __asm volatile ( "" ::: "memory" ) /*-----------------------------------------------------------*/ +/* Select correct value of configUSE_PORT_OPTIMISED_TASK_SELECTION + * based on whether or not Mainline extension is implemented. */ +#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION + #if ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) + #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1 + #else + #define configUSE_PORT_OPTIMISED_TASK_SELECTION 0 + #endif +#endif /* #ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION */ + +/** + * @brief Port-optimised task selection. + */ +#if ( configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 ) + +/** + * @brief Count the number of leading zeros in a 32-bit value. + */ + static portFORCE_INLINE uint32_t ulPortCountLeadingZeros( uint32_t ulBitmap ) + { + uint32_t ulReturn; + + __asm volatile ( "clz %0, %1" : "=r" ( ulReturn ) : "r" ( ulBitmap ) : "memory" ); + + return ulReturn; + } + +/* Check the configuration. */ + #if ( configMAX_PRIORITIES > 32 ) + #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 different priorities as tasks that share a priority will time slice. + #endif + + #if ( portHAS_ARMV8M_MAIN_EXTENSION == 0 ) + #error ARMv8-M baseline implementations (such as Cortex-M23) do not support port-optimised task selection. Please set configUSE_PORT_OPTIMISED_TASK_SELECTION to 0 or leave it undefined. + #endif + +/** + * @brief Store/clear the ready priorities in a bit map. + */ + #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) ) + #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) ) + +/** + * @brief Get the priority of the highest-priority task that is ready to execute. + */ + #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - ulPortCountLeadingZeros( ( uxReadyPriorities ) ) ) + +#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */ +/*-----------------------------------------------------------*/ + /* *INDENT-OFF* */ #ifdef __cplusplus } diff --git a/Source/portable/IAR/ARM_CM23/secure/secure_context.c b/Source/portable/IAR/ARM_CM23/secure/secure_context.c index e37dd9672..83b3dbce1 100644 --- a/Source/portable/IAR/ARM_CM23/secure/secure_context.c +++ b/Source/portable/IAR/ARM_CM23/secure/secure_context.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -65,7 +65,7 @@ * @brief Maximum number of secure contexts. */ #ifndef secureconfigMAX_SECURE_CONTEXTS - #define secureconfigMAX_SECURE_CONTEXTS 8UL + #define secureconfigMAX_SECURE_CONTEXTS 8UL #endif /*-----------------------------------------------------------*/ @@ -164,15 +164,15 @@ secureportNON_SECURE_CALLABLE void SecureContext_Init( void ) } #if ( configENABLE_MPU == 1 ) - { - /* Configure thread mode to use PSP and to be unprivileged. */ - secureportSET_CONTROL( securecontextCONTROL_VALUE_UNPRIVILEGED ); - } + { + /* Configure thread mode to use PSP and to be unprivileged. */ + secureportSET_CONTROL( securecontextCONTROL_VALUE_UNPRIVILEGED ); + } #else /* configENABLE_MPU */ - { - /* Configure thread mode to use PSP and to be privileged. */ - secureportSET_CONTROL( securecontextCONTROL_VALUE_PRIVILEGED ); - } + { + /* Configure thread mode to use PSP and to be privileged. */ + secureportSET_CONTROL( securecontextCONTROL_VALUE_PRIVILEGED ); + } #endif /* configENABLE_MPU */ } } @@ -219,16 +219,16 @@ secureportNON_SECURE_CALLABLE void SecureContext_Init( void ) if( pucStackMemory != NULL ) { /* Since stack grows down, the starting point will be the last - * location. Note that this location is next to the last - * allocated byte for stack (excluding the space for seal values) - * because the hardware decrements the stack pointer before - * writing i.e. if stack pointer is 0x2, a push operation will - * decrement the stack pointer to 0x1 and then write at 0x1. */ + * location. Note that this location is next to the last + * allocated byte for stack (excluding the space for seal values) + * because the hardware decrements the stack pointer before + * writing i.e. if stack pointer is 0x2, a push operation will + * decrement the stack pointer to 0x1 and then write at 0x1. */ xSecureContexts[ ulSecureContextIndex ].pucStackStart = pucStackMemory + ulSecureStackSize; /* Seal the created secure process stack. */ - *( uint32_t * )( pucStackMemory + ulSecureStackSize ) = securecontextSTACK_SEAL_VALUE; - *( uint32_t * )( pucStackMemory + ulSecureStackSize + 4 ) = securecontextSTACK_SEAL_VALUE; + *( uint32_t * ) ( pucStackMemory + ulSecureStackSize ) = securecontextSTACK_SEAL_VALUE; + *( uint32_t * ) ( pucStackMemory + ulSecureStackSize + 4 ) = securecontextSTACK_SEAL_VALUE; /* The stack cannot go beyond this location. This value is * programmed in the PSPLIM register on context switch.*/ @@ -237,32 +237,32 @@ secureportNON_SECURE_CALLABLE void SecureContext_Init( void ) xSecureContexts[ ulSecureContextIndex ].pvTaskHandle = pvTaskHandle; #if ( configENABLE_MPU == 1 ) + { + /* Store the correct CONTROL value for the task on the stack. + * This value is programmed in the CONTROL register on + * context switch. */ + pulCurrentStackPointer = ( uint32_t * ) xSecureContexts[ ulSecureContextIndex ].pucStackStart; + pulCurrentStackPointer--; + + if( ulIsTaskPrivileged ) { - /* Store the correct CONTROL value for the task on the stack. - * This value is programmed in the CONTROL register on - * context switch. */ - pulCurrentStackPointer = ( uint32_t * ) xSecureContexts[ ulSecureContextIndex ].pucStackStart; - pulCurrentStackPointer--; - - if( ulIsTaskPrivileged ) - { - *( pulCurrentStackPointer ) = securecontextCONTROL_VALUE_PRIVILEGED; - } - else - { - *( pulCurrentStackPointer ) = securecontextCONTROL_VALUE_UNPRIVILEGED; - } - - /* Store the current stack pointer. This value is programmed in - * the PSP register on context switch. */ - xSecureContexts[ ulSecureContextIndex ].pucCurrentStackPointer = ( uint8_t * ) pulCurrentStackPointer; + *( pulCurrentStackPointer ) = securecontextCONTROL_VALUE_PRIVILEGED; } - #else /* configENABLE_MPU */ + else { - /* Current SP is set to the starting of the stack. This - * value programmed in the PSP register on context switch. */ - xSecureContexts[ ulSecureContextIndex ].pucCurrentStackPointer = xSecureContexts[ ulSecureContextIndex ].pucStackStart; + *( pulCurrentStackPointer ) = securecontextCONTROL_VALUE_UNPRIVILEGED; } + + /* Store the current stack pointer. This value is programmed in + * the PSP register on context switch. */ + xSecureContexts[ ulSecureContextIndex ].pucCurrentStackPointer = ( uint8_t * ) pulCurrentStackPointer; + } + #else /* configENABLE_MPU */ + { + /* Current SP is set to the starting of the stack. This + * value programmed in the PSP register on context switch. */ + xSecureContexts[ ulSecureContextIndex ].pucCurrentStackPointer = xSecureContexts[ ulSecureContextIndex ].pucStackStart; + } #endif /* configENABLE_MPU */ /* Ensure to never return 0 as a valid context handle. */ @@ -275,7 +275,8 @@ secureportNON_SECURE_CALLABLE void SecureContext_Init( void ) } /*-----------------------------------------------------------*/ -secureportNON_SECURE_CALLABLE void SecureContext_FreeContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle ) +secureportNON_SECURE_CALLABLE void SecureContext_FreeContext( SecureContextHandle_t xSecureContextHandle, + void * pvTaskHandle ) { uint32_t ulIPSR, ulSecureContextIndex; @@ -306,7 +307,8 @@ secureportNON_SECURE_CALLABLE void SecureContext_FreeContext( SecureContextHandl } /*-----------------------------------------------------------*/ -secureportNON_SECURE_CALLABLE void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle ) +secureportNON_SECURE_CALLABLE void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle, + void * pvTaskHandle ) { uint8_t * pucStackLimit; uint32_t ulSecureContextIndex; @@ -328,7 +330,8 @@ secureportNON_SECURE_CALLABLE void SecureContext_LoadContext( SecureContextHandl } /*-----------------------------------------------------------*/ -secureportNON_SECURE_CALLABLE void SecureContext_SaveContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle ) +secureportNON_SECURE_CALLABLE void SecureContext_SaveContext( SecureContextHandle_t xSecureContextHandle, + void * pvTaskHandle ) { uint8_t * pucStackLimit; uint32_t ulSecureContextIndex; diff --git a/Source/portable/IAR/ARM_CM23/secure/secure_context.h b/Source/portable/IAR/ARM_CM23/secure/secure_context.h index 2220ea646..40fdc276d 100644 --- a/Source/portable/IAR/ARM_CM23/secure/secure_context.h +++ b/Source/portable/IAR/ARM_CM23/secure/secure_context.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -38,12 +38,12 @@ /** * @brief PSP value when no secure context is loaded. */ -#define securecontextNO_STACK 0x0 +#define securecontextNO_STACK 0x0 /** * @brief Invalid context ID. */ -#define securecontextINVALID_CONTEXT_ID 0UL +#define securecontextINVALID_CONTEXT_ID 0UL /*-----------------------------------------------------------*/ /** @@ -108,7 +108,8 @@ void SecureContext_Init( void ); * @param[in] xSecureContextHandle Context handle corresponding to the * context to be freed. */ -void SecureContext_FreeContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle ); +void SecureContext_FreeContext( SecureContextHandle_t xSecureContextHandle, + void * pvTaskHandle ); /** * @brief Loads the given context. @@ -119,7 +120,8 @@ void SecureContext_FreeContext( SecureContextHandle_t xSecureContextHandle, void * @param[in] xSecureContextHandle Context handle corresponding to the context * to be loaded. */ -void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle ); +void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle, + void * pvTaskHandle ); /** * @brief Saves the given context. @@ -130,6 +132,7 @@ void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle, void * @param[in] xSecureContextHandle Context handle corresponding to the context * to be saved. */ -void SecureContext_SaveContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle ); +void SecureContext_SaveContext( SecureContextHandle_t xSecureContextHandle, + void * pvTaskHandle ); #endif /* __SECURE_CONTEXT_H__ */ diff --git a/Source/portable/IAR/ARM_CM23/secure/secure_context_port_asm.s b/Source/portable/IAR/ARM_CM23/secure/secure_context_port_asm.s index 1e4b3a57a..de0b495ae 100644 --- a/Source/portable/IAR/ARM_CM23/secure/secure_context_port_asm.s +++ b/Source/portable/IAR/ARM_CM23/secure/secure_context_port_asm.s @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/Source/portable/IAR/ARM_CM23/secure/secure_heap.c b/Source/portable/IAR/ARM_CM23/secure/secure_heap.c index 19f7c2354..d9789404b 100644 --- a/Source/portable/IAR/ARM_CM23/secure/secure_heap.c +++ b/Source/portable/IAR/ARM_CM23/secure/secure_heap.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -62,6 +62,22 @@ /* Assumes 8bit bytes! */ #define secureheapBITS_PER_BYTE ( ( size_t ) 8 ) + +/* Max value that fits in a size_t type. */ +#define secureheapSIZE_MAX ( ~( ( size_t ) 0 ) ) + +/* Check if adding a and b will result in overflow. */ +#define secureheapADD_WILL_OVERFLOW( a, b ) ( ( a ) > ( secureheapSIZE_MAX - ( b ) ) ) + +/* MSB of the xBlockSize member of an BlockLink_t structure is used to track + * the allocation status of a block. When MSB of the xBlockSize member of + * an BlockLink_t structure is set then the block belongs to the application. + * When the bit is free the block is still part of the free heap space. */ +#define secureheapBLOCK_ALLOCATED_BITMASK ( ( ( size_t ) 1 ) << ( ( sizeof( size_t ) * secureheapBITS_PER_BYTE ) - 1 ) ) +#define secureheapBLOCK_SIZE_IS_VALID( xBlockSize ) ( ( ( xBlockSize ) & secureheapBLOCK_ALLOCATED_BITMASK ) == 0 ) +#define secureheapBLOCK_IS_ALLOCATED( pxBlock ) ( ( ( pxBlock->xBlockSize ) & secureheapBLOCK_ALLOCATED_BITMASK ) != 0 ) +#define secureheapALLOCATE_BLOCK( pxBlock ) ( ( pxBlock->xBlockSize ) |= secureheapBLOCK_ALLOCATED_BITMASK ) +#define secureheapFREE_BLOCK( pxBlock ) ( ( pxBlock->xBlockSize ) &= ~secureheapBLOCK_ALLOCATED_BITMASK ) /*-----------------------------------------------------------*/ /* Allocate the memory for the heap. */ @@ -123,14 +139,6 @@ static BlockLink_t * pxEnd = NULL; static size_t xFreeBytesRemaining = 0U; static size_t xMinimumEverFreeBytesRemaining = 0U; -/** - * @brief Gets set to the top bit of an size_t type. - * - * When this bit in the xBlockSize member of an BlockLink_t structure is set - * then the block belongs to the application. When the bit is free the block is - * still part of the free heap space. - */ -static size_t xBlockAllocatedBit = 0; /*-----------------------------------------------------------*/ static void prvHeapInit( void ) @@ -175,9 +183,6 @@ static void prvHeapInit( void ) /* Only one block exists - and it covers the entire usable heap space. */ xMinimumEverFreeBytesRemaining = pxFirstFreeBlock->xBlockSize; xFreeBytesRemaining = pxFirstFreeBlock->xBlockSize; - - /* Work out the position of the top bit in a size_t variable. */ - xBlockAllocatedBit = ( ( size_t ) 1 ) << ( ( sizeof( size_t ) * secureheapBITS_PER_BYTE ) - 1 ); } /*-----------------------------------------------------------*/ @@ -250,6 +255,7 @@ void * pvPortMalloc( size_t xWantedSize ) BlockLink_t * pxPreviousBlock; BlockLink_t * pxNewBlockLink; void * pvReturn = NULL; + size_t xAdditionalRequiredSize; /* If this is the first call to malloc then the heap will require * initialisation to setup the list of free blocks. */ @@ -262,25 +268,29 @@ void * pvPortMalloc( size_t xWantedSize ) mtCOVERAGE_TEST_MARKER(); } - /* Check the requested block size is not so large that the top bit is set. - * The top bit of the block size member of the BlockLink_t structure is used - * to determine who owns the block - the application or the kernel, so it - * must be free. */ - if( ( xWantedSize & xBlockAllocatedBit ) == 0 ) + if( xWantedSize > 0 ) { - /* The wanted size is increased so it can contain a BlockLink_t + /* The wanted size must be increased so it can contain a BlockLink_t * structure in addition to the requested amount of bytes. */ - if( xWantedSize > 0 ) + if( secureheapADD_WILL_OVERFLOW( xWantedSize, xHeapStructSize ) == 0 ) { xWantedSize += xHeapStructSize; - /* Ensure that blocks are always aligned to the required number of - * bytes. */ + /* Ensure that blocks are always aligned to the required number + * of bytes. */ if( ( xWantedSize & secureportBYTE_ALIGNMENT_MASK ) != 0x00 ) { /* Byte alignment required. */ - xWantedSize += ( secureportBYTE_ALIGNMENT - ( xWantedSize & secureportBYTE_ALIGNMENT_MASK ) ); - secureportASSERT( ( xWantedSize & secureportBYTE_ALIGNMENT_MASK ) == 0 ); + xAdditionalRequiredSize = secureportBYTE_ALIGNMENT - ( xWantedSize & secureportBYTE_ALIGNMENT_MASK ); + + if( secureheapADD_WILL_OVERFLOW( xWantedSize, xAdditionalRequiredSize ) == 0 ) + { + xWantedSize += xAdditionalRequiredSize; + } + else + { + xWantedSize = 0; + } } else { @@ -289,9 +299,20 @@ void * pvPortMalloc( size_t xWantedSize ) } else { - mtCOVERAGE_TEST_MARKER(); + xWantedSize = 0; } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + /* Check the requested block size is not so large that the top bit is set. + * The top bit of the block size member of the BlockLink_t structure is used + * to determine who owns the block - the application or the kernel, so it + * must be free. */ + if( secureheapBLOCK_SIZE_IS_VALID( xWantedSize ) != 0 ) + { if( ( xWantedSize > 0 ) && ( xWantedSize <= xFreeBytesRemaining ) ) { /* Traverse the list from the start (lowest address) block until @@ -334,7 +355,8 @@ void * pvPortMalloc( size_t xWantedSize ) pxBlock->xBlockSize = xWantedSize; /* Insert the new block into the list of free blocks. */ - prvInsertBlockIntoFreeList( pxNewBlockLink ); + pxNewBlockLink->pxNextFreeBlock = pxPreviousBlock->pxNextFreeBlock; + pxPreviousBlock->pxNextFreeBlock = pxNewBlockLink; } else { @@ -354,7 +376,7 @@ void * pvPortMalloc( size_t xWantedSize ) /* The block is being returned - it is allocated and owned by * the application and has no "next" block. */ - pxBlock->xBlockSize |= xBlockAllocatedBit; + secureheapALLOCATE_BLOCK( pxBlock ); pxBlock->pxNextFreeBlock = NULL; } else @@ -375,17 +397,17 @@ void * pvPortMalloc( size_t xWantedSize ) traceMALLOC( pvReturn, xWantedSize ); #if ( secureconfigUSE_MALLOC_FAILED_HOOK == 1 ) + { + if( pvReturn == NULL ) { - if( pvReturn == NULL ) - { - extern void vApplicationMallocFailedHook( void ); - vApplicationMallocFailedHook(); - } - else - { - mtCOVERAGE_TEST_MARKER(); - } + extern void vApplicationMallocFailedHook( void ); + vApplicationMallocFailedHook(); } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } #endif /* if ( secureconfigUSE_MALLOC_FAILED_HOOK == 1 ) */ secureportASSERT( ( ( ( size_t ) pvReturn ) & ( size_t ) secureportBYTE_ALIGNMENT_MASK ) == 0 ); @@ -408,16 +430,16 @@ void vPortFree( void * pv ) pxLink = ( void * ) puc; /* Check the block is actually allocated. */ - secureportASSERT( ( pxLink->xBlockSize & xBlockAllocatedBit ) != 0 ); + secureportASSERT( secureheapBLOCK_IS_ALLOCATED( pxLink ) != 0 ); secureportASSERT( pxLink->pxNextFreeBlock == NULL ); - if( ( pxLink->xBlockSize & xBlockAllocatedBit ) != 0 ) + if( secureheapBLOCK_IS_ALLOCATED( pxLink ) != 0 ) { if( pxLink->pxNextFreeBlock == NULL ) { /* The block is being returned to the heap - it is no longer * allocated. */ - pxLink->xBlockSize &= ~xBlockAllocatedBit; + secureheapFREE_BLOCK( pxLink ); secureportDISABLE_NON_SECURE_INTERRUPTS(); { diff --git a/Source/portable/IAR/ARM_CM23/secure/secure_heap.h b/Source/portable/IAR/ARM_CM23/secure/secure_heap.h index 75c9cb00b..cf5551046 100644 --- a/Source/portable/IAR/ARM_CM23/secure/secure_heap.h +++ b/Source/portable/IAR/ARM_CM23/secure/secure_heap.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/Source/portable/IAR/ARM_CM23/secure/secure_init.c b/Source/portable/IAR/ARM_CM23/secure/secure_init.c index f93bfce95..66d35eccc 100644 --- a/Source/portable/IAR/ARM_CM23/secure/secure_init.c +++ b/Source/portable/IAR/ARM_CM23/secure/secure_init.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -93,7 +93,7 @@ secureportNON_SECURE_CALLABLE void SecureInit_EnableNSFPUAccess( void ) * permitted. CP11 should be programmed to the same value as CP10. */ *( secureinitNSACR ) |= ( secureinitNSACR_CP10_MASK | secureinitNSACR_CP11_MASK ); - /* LSPENS = 0 ==> LSPEN is writable fron non-secure state. This ensures + /* LSPENS = 0 ==> LSPEN is writable from non-secure state. This ensures * that we can enable/disable lazy stacking in port.c file. */ *( secureinitFPCCR ) &= ~( secureinitFPCCR_LSPENS_MASK ); diff --git a/Source/portable/IAR/ARM_CM23/secure/secure_init.h b/Source/portable/IAR/ARM_CM23/secure/secure_init.h index e6c9da0b4..6404c5cc4 100644 --- a/Source/portable/IAR/ARM_CM23/secure/secure_init.h +++ b/Source/portable/IAR/ARM_CM23/secure/secure_init.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/Source/portable/IAR/ARM_CM23/secure/secure_port_macros.h b/Source/portable/IAR/ARM_CM23/secure/secure_port_macros.h index d7ac5833c..085108cc1 100644 --- a/Source/portable/IAR/ARM_CM23/secure/secure_port_macros.h +++ b/Source/portable/IAR/ARM_CM23/secure/secure_port_macros.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/Source/portable/IAR/ARM_CM23_NTZ/non_secure/mpu_wrappers_v2_asm.S b/Source/portable/IAR/ARM_CM23_NTZ/non_secure/mpu_wrappers_v2_asm.S index 4d805f3e2..0b7d942e4 100644 --- a/Source/portable/IAR/ARM_CM23_NTZ/non_secure/mpu_wrappers_v2_asm.S +++ b/Source/portable/IAR/ARM_CM23_NTZ/non_secure/mpu_wrappers_v2_asm.S @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -207,21 +207,6 @@ MPU_uxTaskGetNumberOfTasks: svc #SYSTEM_CALL_uxTaskGetNumberOfTasks /*-----------------------------------------------------------*/ - PUBLIC MPU_pcTaskGetName -MPU_pcTaskGetName: - push {r0, r1} - mrs r0, control - movs r1, #1 - tst r0, r1 - bne MPU_pcTaskGetName_Unpriv - MPU_pcTaskGetName_Priv: - pop {r0, r1} - b MPU_pcTaskGetNameImpl - MPU_pcTaskGetName_Unpriv: - pop {r0, r1} - svc #SYSTEM_CALL_pcTaskGetName -/*-----------------------------------------------------------*/ - PUBLIC MPU_ulTaskGetRunTimeCounter MPU_ulTaskGetRunTimeCounter: push {r0, r1} @@ -792,25 +777,19 @@ MPU_xTimerGetTimerDaemonTaskHandle: svc #SYSTEM_CALL_xTimerGetTimerDaemonTaskHandle /*-----------------------------------------------------------*/ - PUBLIC MPU_xTimerGenericCommandEntry -MPU_xTimerGenericCommandEntry: + PUBLIC MPU_xTimerGenericCommandFromTaskEntry +MPU_xTimerGenericCommandFromTaskEntry: push {r0, r1} - /* This function can be called from ISR also and therefore, we need a check - * to take privileged path, if called from ISR. */ - mrs r0, ipsr - cmp r0, #0 - bne MPU_xTimerGenericCommand_Priv mrs r0, control movs r1, #1 tst r0, r1 - beq MPU_xTimerGenericCommand_Priv - MPU_xTimerGenericCommand_Unpriv: + bne MPU_xTimerGenericCommandFromTask_Unpriv + MPU_xTimerGenericCommandFromTask_Priv: pop {r0, r1} - svc #SYSTEM_CALL_xTimerGenericCommand - MPU_xTimerGenericCommand_Priv: + b MPU_xTimerGenericCommandFromTaskImpl + MPU_xTimerGenericCommandFromTask_Unpriv: pop {r0, r1} - b MPU_xTimerGenericCommandPrivImpl - + svc #SYSTEM_CALL_xTimerGenericCommandFromTask /*-----------------------------------------------------------*/ PUBLIC MPU_pcTimerGetName @@ -1160,10 +1139,6 @@ MPU_xTaskGetTickCountImpl: MPU_uxTaskGetNumberOfTasksImpl: b MPU_uxTaskGetNumberOfTasksImpl - PUBWEAK MPU_pcTaskGetNameImpl -MPU_pcTaskGetNameImpl: - b MPU_pcTaskGetNameImpl - PUBWEAK MPU_ulTaskGetRunTimeCounterImpl MPU_ulTaskGetRunTimeCounterImpl: b MPU_ulTaskGetRunTimeCounterImpl @@ -1316,9 +1291,9 @@ MPU_xTimerIsTimerActiveImpl: MPU_xTimerGetTimerDaemonTaskHandleImpl: b MPU_xTimerGetTimerDaemonTaskHandleImpl - PUBWEAK MPU_xTimerGenericCommandPrivImpl -MPU_xTimerGenericCommandPrivImpl: - b MPU_xTimerGenericCommandPrivImpl + PUBWEAK MPU_xTimerGenericCommandFromTaskImpl +MPU_xTimerGenericCommandFromTaskImpl: + b MPU_xTimerGenericCommandFromTaskImpl PUBWEAK MPU_pcTimerGetNameImpl MPU_pcTimerGetNameImpl: diff --git a/Source/portable/IAR/ARM_CM23_NTZ/non_secure/port.c b/Source/portable/IAR/ARM_CM23_NTZ/non_secure/port.c index 9712ac353..230fe5fc2 100644 --- a/Source/portable/IAR/ARM_CM23_NTZ/non_secure/port.c +++ b/Source/portable/IAR/ARM_CM23_NTZ/non_secure/port.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -68,6 +68,22 @@ #if ( ( configRUN_FREERTOS_SECURE_ONLY == 1 ) && ( configENABLE_TRUSTZONE == 1 ) ) #error TrustZone needs to be disabled in order to run FreeRTOS on the Secure Side. #endif + +/** + * Cortex-M23 does not have non-secure PSPLIM. We should use PSPLIM on Cortex-M23 + * only when FreeRTOS runs on secure side. + */ +#if ( ( portHAS_ARMV8M_MAIN_EXTENSION == 0 ) && ( configRUN_FREERTOS_SECURE_ONLY == 0 ) ) + #define portUSE_PSPLIM_REGISTER 0 +#else + #define portUSE_PSPLIM_REGISTER 1 +#endif +/*-----------------------------------------------------------*/ + +/** + * @brief Prototype of all Interrupt Service Routines (ISRs). + */ +typedef void ( * portISR_t )( void ); /*-----------------------------------------------------------*/ /** @@ -91,10 +107,18 @@ /** * @brief Constants required to manipulate the SCB. */ -#define portSCB_SYS_HANDLER_CTRL_STATE_REG ( *( volatile uint32_t * ) 0xe000ed24 ) +#define portSCB_VTOR_REG ( *( ( portISR_t ** ) 0xe000ed08 ) ) +#define portSCB_SYS_HANDLER_CTRL_STATE_REG ( *( ( volatile uint32_t * ) 0xe000ed24 ) ) #define portSCB_MEM_FAULT_ENABLE_BIT ( 1UL << 16UL ) /*-----------------------------------------------------------*/ +/** + * @brief Constants used to check the installation of the FreeRTOS interrupt handlers. + */ +#define portVECTOR_INDEX_SVC ( 11 ) +#define portVECTOR_INDEX_PENDSV ( 14 ) +/*-----------------------------------------------------------*/ + /** * @brief Constants required to check the validity of an interrupt priority. */ @@ -111,8 +135,8 @@ /** * @brief Constants used during system call enter and exit. */ -#define portPSR_STACK_PADDING_MASK ( 1UL << 9UL ) -#define portEXC_RETURN_STACK_FRAME_TYPE_MASK ( 1UL << 4UL ) +#define portPSR_STACK_PADDING_MASK ( 1UL << 9UL ) +#define portEXC_RETURN_STACK_FRAME_TYPE_MASK ( 1UL << 4UL ) /*-----------------------------------------------------------*/ /** @@ -134,81 +158,81 @@ /** * @brief Offsets in the stack to the parameters when inside the SVC handler. */ -#define portOFFSET_TO_LR ( 5 ) -#define portOFFSET_TO_PC ( 6 ) -#define portOFFSET_TO_PSR ( 7 ) +#define portOFFSET_TO_LR ( 5 ) +#define portOFFSET_TO_PC ( 6 ) +#define portOFFSET_TO_PSR ( 7 ) /*-----------------------------------------------------------*/ /** * @brief Constants required to manipulate the MPU. */ -#define portMPU_TYPE_REG ( *( ( volatile uint32_t * ) 0xe000ed90 ) ) -#define portMPU_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed94 ) ) -#define portMPU_RNR_REG ( *( ( volatile uint32_t * ) 0xe000ed98 ) ) +#define portMPU_TYPE_REG ( *( ( volatile uint32_t * ) 0xe000ed90 ) ) +#define portMPU_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed94 ) ) +#define portMPU_RNR_REG ( *( ( volatile uint32_t * ) 0xe000ed98 ) ) -#define portMPU_RBAR_REG ( *( ( volatile uint32_t * ) 0xe000ed9c ) ) -#define portMPU_RLAR_REG ( *( ( volatile uint32_t * ) 0xe000eda0 ) ) +#define portMPU_RBAR_REG ( *( ( volatile uint32_t * ) 0xe000ed9c ) ) +#define portMPU_RLAR_REG ( *( ( volatile uint32_t * ) 0xe000eda0 ) ) -#define portMPU_RBAR_A1_REG ( *( ( volatile uint32_t * ) 0xe000eda4 ) ) -#define portMPU_RLAR_A1_REG ( *( ( volatile uint32_t * ) 0xe000eda8 ) ) +#define portMPU_RBAR_A1_REG ( *( ( volatile uint32_t * ) 0xe000eda4 ) ) +#define portMPU_RLAR_A1_REG ( *( ( volatile uint32_t * ) 0xe000eda8 ) ) -#define portMPU_RBAR_A2_REG ( *( ( volatile uint32_t * ) 0xe000edac ) ) -#define portMPU_RLAR_A2_REG ( *( ( volatile uint32_t * ) 0xe000edb0 ) ) +#define portMPU_RBAR_A2_REG ( *( ( volatile uint32_t * ) 0xe000edac ) ) +#define portMPU_RLAR_A2_REG ( *( ( volatile uint32_t * ) 0xe000edb0 ) ) -#define portMPU_RBAR_A3_REG ( *( ( volatile uint32_t * ) 0xe000edb4 ) ) -#define portMPU_RLAR_A3_REG ( *( ( volatile uint32_t * ) 0xe000edb8 ) ) +#define portMPU_RBAR_A3_REG ( *( ( volatile uint32_t * ) 0xe000edb4 ) ) +#define portMPU_RLAR_A3_REG ( *( ( volatile uint32_t * ) 0xe000edb8 ) ) -#define portMPU_MAIR0_REG ( *( ( volatile uint32_t * ) 0xe000edc0 ) ) -#define portMPU_MAIR1_REG ( *( ( volatile uint32_t * ) 0xe000edc4 ) ) +#define portMPU_MAIR0_REG ( *( ( volatile uint32_t * ) 0xe000edc0 ) ) +#define portMPU_MAIR1_REG ( *( ( volatile uint32_t * ) 0xe000edc4 ) ) -#define portMPU_RBAR_ADDRESS_MASK ( 0xffffffe0 ) /* Must be 32-byte aligned. */ -#define portMPU_RLAR_ADDRESS_MASK ( 0xffffffe0 ) /* Must be 32-byte aligned. */ +#define portMPU_RBAR_ADDRESS_MASK ( 0xffffffe0 ) /* Must be 32-byte aligned. */ +#define portMPU_RLAR_ADDRESS_MASK ( 0xffffffe0 ) /* Must be 32-byte aligned. */ -#define portMPU_RBAR_ACCESS_PERMISSIONS_MASK ( 3UL << 1UL ) +#define portMPU_RBAR_ACCESS_PERMISSIONS_MASK ( 3UL << 1UL ) -#define portMPU_MAIR_ATTR0_POS ( 0UL ) -#define portMPU_MAIR_ATTR0_MASK ( 0x000000ff ) +#define portMPU_MAIR_ATTR0_POS ( 0UL ) +#define portMPU_MAIR_ATTR0_MASK ( 0x000000ff ) -#define portMPU_MAIR_ATTR1_POS ( 8UL ) -#define portMPU_MAIR_ATTR1_MASK ( 0x0000ff00 ) +#define portMPU_MAIR_ATTR1_POS ( 8UL ) +#define portMPU_MAIR_ATTR1_MASK ( 0x0000ff00 ) -#define portMPU_MAIR_ATTR2_POS ( 16UL ) -#define portMPU_MAIR_ATTR2_MASK ( 0x00ff0000 ) +#define portMPU_MAIR_ATTR2_POS ( 16UL ) +#define portMPU_MAIR_ATTR2_MASK ( 0x00ff0000 ) -#define portMPU_MAIR_ATTR3_POS ( 24UL ) -#define portMPU_MAIR_ATTR3_MASK ( 0xff000000 ) +#define portMPU_MAIR_ATTR3_POS ( 24UL ) +#define portMPU_MAIR_ATTR3_MASK ( 0xff000000 ) -#define portMPU_MAIR_ATTR4_POS ( 0UL ) -#define portMPU_MAIR_ATTR4_MASK ( 0x000000ff ) +#define portMPU_MAIR_ATTR4_POS ( 0UL ) +#define portMPU_MAIR_ATTR4_MASK ( 0x000000ff ) -#define portMPU_MAIR_ATTR5_POS ( 8UL ) -#define portMPU_MAIR_ATTR5_MASK ( 0x0000ff00 ) +#define portMPU_MAIR_ATTR5_POS ( 8UL ) +#define portMPU_MAIR_ATTR5_MASK ( 0x0000ff00 ) -#define portMPU_MAIR_ATTR6_POS ( 16UL ) -#define portMPU_MAIR_ATTR6_MASK ( 0x00ff0000 ) +#define portMPU_MAIR_ATTR6_POS ( 16UL ) +#define portMPU_MAIR_ATTR6_MASK ( 0x00ff0000 ) -#define portMPU_MAIR_ATTR7_POS ( 24UL ) -#define portMPU_MAIR_ATTR7_MASK ( 0xff000000 ) +#define portMPU_MAIR_ATTR7_POS ( 24UL ) +#define portMPU_MAIR_ATTR7_MASK ( 0xff000000 ) -#define portMPU_RLAR_ATTR_INDEX0 ( 0UL << 1UL ) -#define portMPU_RLAR_ATTR_INDEX1 ( 1UL << 1UL ) -#define portMPU_RLAR_ATTR_INDEX2 ( 2UL << 1UL ) -#define portMPU_RLAR_ATTR_INDEX3 ( 3UL << 1UL ) -#define portMPU_RLAR_ATTR_INDEX4 ( 4UL << 1UL ) -#define portMPU_RLAR_ATTR_INDEX5 ( 5UL << 1UL ) -#define portMPU_RLAR_ATTR_INDEX6 ( 6UL << 1UL ) -#define portMPU_RLAR_ATTR_INDEX7 ( 7UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX0 ( 0UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX1 ( 1UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX2 ( 2UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX3 ( 3UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX4 ( 4UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX5 ( 5UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX6 ( 6UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX7 ( 7UL << 1UL ) -#define portMPU_RLAR_REGION_ENABLE ( 1UL ) +#define portMPU_RLAR_REGION_ENABLE ( 1UL ) /* Enable privileged access to unmapped region. */ -#define portMPU_PRIV_BACKGROUND_ENABLE_BIT ( 1UL << 2UL ) +#define portMPU_PRIV_BACKGROUND_ENABLE_BIT ( 1UL << 2UL ) /* Enable MPU. */ -#define portMPU_ENABLE_BIT ( 1UL << 0UL ) +#define portMPU_ENABLE_BIT ( 1UL << 0UL ) /* Expected value of the portMPU_TYPE register. */ -#define portEXPECTED_MPU_TYPE_VALUE ( configTOTAL_MPU_REGIONS << 8UL ) +#define portEXPECTED_MPU_TYPE_VALUE ( configTOTAL_MPU_REGIONS << 8UL ) /* Extract first address of the MPU region as encoded in the * RBAR (Region Base Address Register) value. */ @@ -448,13 +472,13 @@ portDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIV #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) - /** - * @brief Sets up the task stack so that upon returning from - * SVC, the task stack is used again. - * - * @param pulSystemCallStack The current SP when the SVC was raised. - * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler. - */ +/** + * @brief Sets up the task stack so that upon returning from + * SVC, the task stack is used again. + * + * @param pulSystemCallStack The current SP when the SVC was raised. + * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler. + */ void vSystemCallExit( uint32_t * pulSystemCallStack, uint32_t ulLR ) PRIVILEGED_FUNCTION; @@ -462,11 +486,11 @@ portDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIV #if ( configENABLE_MPU == 1 ) - /** - * @brief Checks whether or not the calling task is privileged. - * - * @return pdTRUE if the calling task is privileged, pdFALSE otherwise. - */ +/** + * @brief Checks whether or not the calling task is privileged. + * + * @return pdTRUE if the calling task is privileged, pdFALSE otherwise. + */ BaseType_t xPortIsTaskPrivileged( void ) PRIVILEGED_FUNCTION; #endif /* configENABLE_MPU == 1 */ @@ -501,13 +525,13 @@ PRIVILEGED_DATA static volatile uint32_t ulCriticalNesting = 0xaaaaaaaaUL; * FreeRTOS API functions are not called from interrupts that have been assigned * a priority above configMAX_SYSCALL_INTERRUPT_PRIORITY. */ -#if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) ) +#if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) static uint8_t ucMaxSysCallPriority = 0; static uint32_t ulMaxPRIGROUPValue = 0; static const volatile uint8_t * const pcInterruptPriorityRegisters = ( const volatile uint8_t * ) portNVIC_IP_REGISTERS_OFFSET_16; -#endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) ) */ +#endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */ #if ( configUSE_TICKLESS_IDLE == 1 ) @@ -760,8 +784,15 @@ __attribute__( ( weak ) ) void vPortSetupTimerInterrupt( void ) /* PRIVILEGED_FU } #endif /* configUSE_TICKLESS_IDLE */ - /* Stop and reset the SysTick. */ - portNVIC_SYSTICK_CTRL_REG = 0UL; + /* Stop and reset SysTick. + * + * QEMU versions older than 7.0.0 contain a bug which causes an error if we + * enable SysTick without first selecting a valid clock source. We trigger + * the bug if we change clock sources from a clock with a zero clock period + * to one with a nonzero clock period and enable Systick at the same time. + * So we configure the CLKSOURCE bit here, prior to setting the ENABLE bit. + * This workaround avoids the bug in QEMU versions older than 7.0.0. */ + portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT_CONFIG; portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL; /* Configure SysTick to interrupt at the requested rate. */ @@ -819,6 +850,7 @@ static void prvTaskExitError( void ) static void prvSetupMPU( void ) /* PRIVILEGED_FUNCTION */ { #if defined( __ARMCC_VERSION ) + /* Declaration when these variable are defined in code instead of being * exported from linker scripts. */ extern uint32_t * __privileged_functions_start__; @@ -972,13 +1004,19 @@ void SysTick_Handler( void ) /* PRIVILEGED_FUNCTION */ uint32_t ulPreviousMask; ulPreviousMask = portSET_INTERRUPT_MASK_FROM_ISR(); + traceISR_ENTER(); { /* Increment the RTOS tick. */ if( xTaskIncrementTick() != pdFALSE ) { + traceISR_EXIT_TO_SCHEDULER(); /* Pend a context switch. */ portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; } + else + { + traceISR_EXIT(); + } } portCLEAR_INTERRUPT_MASK_FROM_ISR( ulPreviousMask ); } @@ -988,6 +1026,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO { #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) ) #if defined( __ARMCC_VERSION ) + /* Declaration when these variable are defined in code instead of being * exported from linker scripts. */ extern uint32_t * __syscalls_flash_start__; @@ -1083,18 +1122,24 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO vRestoreContextOfFirstTask(); break; - #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) ) - case portSVC_RAISE_PRIVILEGE: + #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) ) + case portSVC_RAISE_PRIVILEGE: - /* Only raise the privilege, if the svc was raised from any of - * the system calls. */ - if( ( ulPC >= ( uint32_t ) __syscalls_flash_start__ ) && - ( ulPC <= ( uint32_t ) __syscalls_flash_end__ ) ) - { - vRaisePrivilege(); - } - break; - #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) */ + /* Only raise the privilege, if the svc was raised from any of + * the system calls. */ + if( ( ulPC >= ( uint32_t ) __syscalls_flash_start__ ) && + ( ulPC <= ( uint32_t ) __syscalls_flash_end__ ) ) + { + vRaisePrivilege(); + } + break; + #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) */ + + #if ( configENABLE_MPU == 1 ) + case portSVC_YIELD: + vPortYield(); + break; + #endif /* configENABLE_MPU == 1 */ default: /* Incorrect SVC call. */ @@ -1154,12 +1199,11 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO { /* Extended frame i.e. FPU in use. */ ulStackFrameSize = 26; - __asm volatile - ( + __asm volatile ( " vpush {s0} \n" /* Trigger lazy stacking. */ " vpop {s0} \n" /* Nullify the affect of the above instruction. */ ::: "memory" - ); + ); } else { @@ -1171,7 +1215,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO { ulStackFrameSize = 8; } - #endif /* if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */ + #endif /* configENABLE_FPU || configENABLE_MVE */ /* Make space on the system call stack for the stack frame. */ pulSystemCallStack = pulSystemCallStack - ulStackFrameSize; @@ -1187,18 +1231,24 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO * point (i.e. the caller of the MPU_). We need to restore it * when we exit from the system call. */ pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry = pulTaskStack[ portOFFSET_TO_LR ]; - /* Store the value of the PSPLIM register before the SVC was raised. * We need to restore it when we exit from the system call. */ - __asm volatile ( "mrs %0, psplim" : "=r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) ); + #if ( portUSE_PSPLIM_REGISTER == 1 ) + { + __asm volatile ( "mrs %0, psplim" : "=r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) ); + } + #endif /* Use the pulSystemCallStack in thread mode. */ __asm volatile ( "msr psp, %0" : : "r" ( pulSystemCallStack ) ); - __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) ); + #if ( portUSE_PSPLIM_REGISTER == 1 ) + { + __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) ); + } + #endif /* Start executing the system call upon returning from this handler. */ pulSystemCallStack[ portOFFSET_TO_PC ] = uxSystemCallImplementations[ ucSystemCallNumber ]; - /* Raise a request to exit from the system call upon finishing the * system call. */ pulSystemCallStack[ portOFFSET_TO_LR ] = ( uint32_t ) vRequestSystemCallExit; @@ -1224,14 +1274,13 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO pulSystemCallStack[ portOFFSET_TO_PSR ] &= ( ~portPSR_STACK_PADDING_MASK ); /* Raise the privilege for the duration of the system call. */ - __asm volatile - ( + __asm volatile ( " mrs r0, control \n" /* Obtain current control value. */ " movs r1, #1 \n" /* r1 = 1. */ " bics r0, r1 \n" /* Clear nPRIV bit. */ " msr control, r0 \n" /* Write back new control value. */ ::: "r0", "r1", "memory" - ); + ); } } @@ -1293,12 +1342,11 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO { /* Extended frame i.e. FPU in use. */ ulStackFrameSize = 26; - __asm volatile - ( + __asm volatile ( " vpush {s0} \n" /* Trigger lazy stacking. */ " vpop {s0} \n" /* Nullify the affect of the above instruction. */ ::: "memory" - ); + ); } else { @@ -1310,7 +1358,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO { ulStackFrameSize = 8; } - #endif /* if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */ + #endif /* configENABLE_FPU || configENABLE_MVE */ /* Make space on the task stack for the stack frame. */ pulTaskStack = pulTaskStack - ulStackFrameSize; @@ -1332,7 +1380,11 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO /* Restore the PSPLIM register to what it was at the time of * system call entry. */ - __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) ); + #if ( portUSE_PSPLIM_REGISTER == 1 ) + { + __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) ); + } + #endif /* If the hardware used padding to force the stack pointer * to be double word aligned, set the stacked xPSR bit[9], @@ -1350,14 +1402,13 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO pxMpuSettings->xSystemCallStackInfo.pulTaskStack = NULL; /* Drop the privilege before returning to the thread mode. */ - __asm volatile - ( + __asm volatile ( " mrs r0, control \n" /* Obtain current control value. */ " movs r1, #1 \n" /* r1 = 1. */ " orrs r0, r1 \n" /* Set nPRIV bit. */ " msr control, r0 \n" /* Write back new control value. */ ::: "r0", "r1", "memory" - ); + ); } } @@ -1410,21 +1461,21 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO xMPUSettings->ulContext[ ulIndex ] = 0x11111111; /* r11. */ ulIndex++; - xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pvParameters; /* r0. */ + xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pvParameters; /* r0. */ ulIndex++; - xMPUSettings->ulContext[ ulIndex ] = 0x01010101; /* r1. */ + xMPUSettings->ulContext[ ulIndex ] = 0x01010101; /* r1. */ ulIndex++; - xMPUSettings->ulContext[ ulIndex ] = 0x02020202; /* r2. */ + xMPUSettings->ulContext[ ulIndex ] = 0x02020202; /* r2. */ ulIndex++; - xMPUSettings->ulContext[ ulIndex ] = 0x03030303; /* r3. */ + xMPUSettings->ulContext[ ulIndex ] = 0x03030303; /* r3. */ ulIndex++; - xMPUSettings->ulContext[ ulIndex ] = 0x12121212; /* r12. */ + xMPUSettings->ulContext[ ulIndex ] = 0x12121212; /* r12. */ ulIndex++; xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portTASK_RETURN_ADDRESS; /* LR. */ ulIndex++; - xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxCode; /* PC. */ + xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxCode; /* PC. */ ulIndex++; - xMPUSettings->ulContext[ ulIndex ] = portINITIAL_XPSR; /* xPSR. */ + xMPUSettings->ulContext[ ulIndex ] = portINITIAL_XPSR; /* xPSR. */ ulIndex++; #if ( configENABLE_TRUSTZONE == 1 ) @@ -1435,8 +1486,9 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO #endif /* configENABLE_TRUSTZONE */ xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) ( pxTopOfStack - 8 ); /* PSP with the hardware saved stack. */ ulIndex++; - xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxEndOfStack; /* PSPLIM. */ + xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxEndOfStack; /* PSPLIM. */ ulIndex++; + if( xRunPrivileged == pdTRUE ) { xMPUSettings->ulTaskFlags |= portTASK_IS_PRIVILEGED_FLAG; @@ -1449,6 +1501,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portINITIAL_CONTROL_UNPRIVILEGED; /* CONTROL. */ ulIndex++; } + xMPUSettings->ulContext[ ulIndex ] = portINITIAL_EXC_RETURN; /* LR (EXC_RETURN). */ ulIndex++; @@ -1483,7 +1536,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO * interrupt. */ #if ( portPRELOAD_REGISTERS == 0 ) { - pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */ + pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */ *pxTopOfStack = portINITIAL_XPSR; /* xPSR. */ pxTopOfStack--; *pxTopOfStack = ( StackType_t ) pxCode; /* PC. */ @@ -1505,7 +1558,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO } #else /* portPRELOAD_REGISTERS */ { - pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */ + pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */ *pxTopOfStack = portINITIAL_XPSR; /* xPSR. */ pxTopOfStack--; *pxTopOfStack = ( StackType_t ) pxCode; /* PC. */ @@ -1540,7 +1593,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO pxTopOfStack--; *pxTopOfStack = portINITIAL_EXC_RETURN; /* EXC_RETURN. */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */ + *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */ #if ( configENABLE_TRUSTZONE == 1 ) { @@ -1559,22 +1612,52 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */ { - #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) ) + /* An application can install FreeRTOS interrupt handlers in one of the + * folllowing ways: + * 1. Direct Routing - Install the functions SVC_Handler and PendSV_Handler + * for SVCall and PendSV interrupts respectively. + * 2. Indirect Routing - Install separate handlers for SVCall and PendSV + * interrupts and route program control from those handlers to + * SVC_Handler and PendSV_Handler functions. + * + * Applications that use Indirect Routing must set + * configCHECK_HANDLER_INSTALLATION to 0 in their FreeRTOSConfig.h. Direct + * routing, which is validated here when configCHECK_HANDLER_INSTALLATION + * is 1, should be preferred when possible. */ + #if ( configCHECK_HANDLER_INSTALLATION == 1 ) + { + const portISR_t * const pxVectorTable = portSCB_VTOR_REG; + + /* Validate that the application has correctly installed the FreeRTOS + * handlers for SVCall and PendSV interrupts. We do not check the + * installation of the SysTick handler because the application may + * choose to drive the RTOS tick using a timer other than the SysTick + * timer by overriding the weak function vPortSetupTimerInterrupt(). + * + * Assertion failures here indicate incorrect installation of the + * FreeRTOS handlers. For help installing the FreeRTOS handlers, see + * https://www.FreeRTOS.org/FAQHelp.html. + * + * Systems with a configurable address for the interrupt vector table + * can also encounter assertion failures or even system faults here if + * VTOR is not set correctly to point to the application's vector table. */ + configASSERT( pxVectorTable[ portVECTOR_INDEX_SVC ] == SVC_Handler ); + configASSERT( pxVectorTable[ portVECTOR_INDEX_PENDSV ] == PendSV_Handler ); + } + #endif /* configCHECK_HANDLER_INSTALLATION */ + + #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) { - volatile uint32_t ulOriginalPriority; volatile uint32_t ulImplementedPrioBits = 0; volatile uint8_t ucMaxPriorityValue; /* Determine the maximum priority from which ISR safe FreeRTOS API - * functions can be called. ISR safe functions are those that end in - * "FromISR". FreeRTOS maintains separate thread and ISR API functions to + * functions can be called. ISR safe functions are those that end in + * "FromISR". FreeRTOS maintains separate thread and ISR API functions to * ensure interrupt entry is as fast and simple as possible. * - * Save the interrupt priority value that is about to be clobbered. */ - ulOriginalPriority = portNVIC_SHPR2_REG; - - /* Determine the number of priority bits available. First write to all - * possible bits. */ + * First, determine the number of priority bits available. Write to all + * possible bits in the priority setting for SVCall. */ portNVIC_SHPR2_REG = 0xFF000000; /* Read the value back to see how many bits stuck. */ @@ -1593,11 +1676,10 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */ /* Check that the bits not implemented in hardware are zero in * configMAX_SYSCALL_INTERRUPT_PRIORITY. */ - configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( ~ucMaxPriorityValue ) ) == 0U ); + configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( uint8_t ) ( ~( uint32_t ) ucMaxPriorityValue ) ) == 0U ); /* Calculate the maximum acceptable priority group value for the number * of bits read back. */ - while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE ) { ulImplementedPrioBits++; @@ -1635,16 +1717,14 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */ * register. */ ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT; ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK; - - /* Restore the clobbered interrupt priority register to its original - * value. */ - portNVIC_SHPR2_REG = ulOriginalPriority; } - #endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) ) */ + #endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */ - /* Make PendSV, CallSV and SysTick the same priority as the kernel. */ + /* Make PendSV and SysTick the lowest priority interrupts, and make SVCall + * the highest priority. */ portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI; portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI; + portNVIC_SHPR2_REG = 0; #if ( configENABLE_MPU == 1 ) { @@ -1701,6 +1781,7 @@ void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */ int32_t lIndex = 0; #if defined( __ARMCC_VERSION ) + /* Declaration when these variable are defined in code instead of being * exported from linker scripts. */ extern uint32_t * __privileged_sram_start__; @@ -1886,7 +1967,7 @@ BaseType_t xPortIsInsideInterrupt( void ) } /*-----------------------------------------------------------*/ -#if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) ) +#if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) void vPortValidateInterruptPriority( void ) { @@ -1944,7 +2025,7 @@ BaseType_t xPortIsInsideInterrupt( void ) configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue ); } -#endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) ) */ +#endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */ /*-----------------------------------------------------------*/ #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) diff --git a/Source/portable/IAR/ARM_CM23_NTZ/non_secure/portasm.h b/Source/portable/IAR/ARM_CM23_NTZ/non_secure/portasm.h index f64ceb525..c6d2ebd58 100644 --- a/Source/portable/IAR/ARM_CM23_NTZ/non_secure/portasm.h +++ b/Source/portable/IAR/ARM_CM23_NTZ/non_secure/portasm.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/Source/portable/IAR/ARM_CM23_NTZ/non_secure/portasm.s b/Source/portable/IAR/ARM_CM23_NTZ/non_secure/portasm.s index cef6b8a66..78a97a558 100644 --- a/Source/portable/IAR/ARM_CM23_NTZ/non_secure/portasm.s +++ b/Source/portable/IAR/ARM_CM23_NTZ/non_secure/portasm.s @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -39,6 +39,10 @@ files (__ICCARM__ is defined by the IAR C compiler but not by the IAR assembler. #define configUSE_MPU_WRAPPERS_V1 0 #endif +#ifndef configRUN_FREERTOS_SECURE_ONLY + #define configRUN_FREERTOS_SECURE_ONLY 0 +#endif + EXTERN pxCurrentTCB EXTERN vTaskSwitchContext EXTERN vPortSVCHandler_C @@ -159,7 +163,9 @@ vRestoreContextOfFirstTask: ldmia r1!, {r2-r5} /* r2 = original PSP, r3 = PSPLIM, r4 = CONTROL, r5 = LR. */ subs r1, #16 msr psp, r2 + #if ( configRUN_FREERTOS_SECURE_ONLY == 1 ) msr psplim, r3 + #endif msr control, r4 mov lr, r5 @@ -191,7 +197,9 @@ vRestoreContextOfFirstTask: ldr r0, [r1] /* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */ ldm r0!, {r1-r2} /* Read from stack - r1 = PSPLIM and r2 = EXC_RETURN. */ +#if ( configRUN_FREERTOS_SECURE_ONLY == 1 ) msr psplim, r1 /* Set this task's PSPLIM value. */ +#endif movs r1, #2 /* r1 = 2. */ msr CONTROL, r1 /* Switch to use PSP in the thread mode. */ adds r0, #32 /* Discard everything up to r0. */ @@ -255,7 +263,11 @@ PendSV_Handler: save_special_regs: mrs r2, psp /* r2 = PSP. */ + #if ( configRUN_FREERTOS_SECURE_ONLY == 1 ) mrs r3, psplim /* r3 = PSPLIM. */ + #else + movs r3, #0 /* r3 = 0. 0 is stored in the PSPLIM slot. */ + #endif mrs r4, control /* r4 = CONTROL. */ mov r5, lr /* r5 = LR. */ stmia r1!, {r2-r5} /* Store original PSP (after hardware has saved context), PSPLIM, CONTROL and LR. */ @@ -323,7 +335,9 @@ PendSV_Handler: ldmia r1!, {r2-r5} /* r2 = original PSP, r3 = PSPLIM, r4 = CONTROL, r5 = LR. */ subs r1, #16 msr psp, r2 + #if ( configRUN_FREERTOS_SECURE_ONLY == 1 ) msr psplim, r3 + #endif msr control, r4 mov lr, r5 @@ -356,7 +370,11 @@ PendSV_Handler: subs r0, r0, #40 /* Make space for PSPLIM, LR and the remaining registers on the stack. */ str r0, [r1] /* Save the new top of stack in TCB. */ +#if ( configRUN_FREERTOS_SECURE_ONLY == 1 ) mrs r2, psplim /* r2 = PSPLIM. */ +#else + movs r2, #0 /* r0 = 0. 0 is stored in the PSPLIM slot. */ +#endif mov r3, lr /* r3 = LR/EXC_RETURN. */ stmia r0!, {r2-r7} /* Store on the stack - PSPLIM, LR and low registers that are not automatically saved. */ mov r4, r8 /* r4 = r8. */ @@ -382,7 +400,9 @@ PendSV_Handler: msr psp, r0 /* Remember the new top of stack for the task. */ subs r0, r0, #40 /* Move to the starting of the saved context. */ ldmia r0!, {r2-r7} /* Read from stack - r2 = PSPLIM, r3 = LR and r4-r7 restored. */ +#if ( configRUN_FREERTOS_SECURE_ONLY == 1 ) msr psplim, r2 /* Restore the PSPLIM register value for the task. */ +#endif bx r3 #endif /* configENABLE_MPU */ diff --git a/Source/portable/IAR/ARM_CM23_NTZ/non_secure/portmacro.h b/Source/portable/IAR/ARM_CM23_NTZ/non_secure/portmacro.h index 19d7556fb..52ab2a3ac 100644 --- a/Source/portable/IAR/ARM_CM23_NTZ/non_secure/portmacro.h +++ b/Source/portable/IAR/ARM_CM23_NTZ/non_secure/portmacro.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -48,9 +48,9 @@ /** * Architecture specifics. */ -#define portARCH_NAME "Cortex-M23" -#define portHAS_BASEPRI 0 -#define portDONT_DISCARD __root +#define portARCH_NAME "Cortex-M23" +#define portHAS_ARMV8M_MAIN_EXTENSION 0 +#define portDONT_DISCARD __root /*-----------------------------------------------------------*/ /* ARMv8-M common port configurations. */ diff --git a/Source/portable/IAR/ARM_CM23_NTZ/non_secure/portmacrocommon.h b/Source/portable/IAR/ARM_CM23_NTZ/non_secure/portmacrocommon.h index 6f666da22..33f21d85b 100644 --- a/Source/portable/IAR/ARM_CM23_NTZ/non_secure/portmacrocommon.h +++ b/Source/portable/IAR/ARM_CM23_NTZ/non_secure/portmacrocommon.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -117,7 +117,7 @@ extern uint32_t ulSetInterruptMask( void ) /* __attribute__(( naked )) PRIVILEGE extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */; #if ( configENABLE_TRUSTZONE == 1 ) - extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize ); /* __attribute__ (( naked )) */ + extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize ); /* __attribute__ (( naked )) */ extern void vPortFreeSecureContext( uint32_t * pulTCB ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */; #endif /* configENABLE_TRUSTZONE */ @@ -188,13 +188,13 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P #if ( configENABLE_MPU == 1 ) - /** - * @brief Settings to define an MPU region. - */ +/** + * @brief Settings to define an MPU region. + */ typedef struct MPURegionSettings { - uint32_t ulRBAR; /**< RBAR for the region. */ - uint32_t ulRLAR; /**< RLAR for the region. */ + uint32_t ulRBAR; /**< RBAR for the region. */ + uint32_t ulRLAR; /**< RLAR for the region. */ } MPURegionSettings_t; #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) @@ -203,9 +203,9 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P #error configSYSTEM_CALL_STACK_SIZE must be defined to the desired size of the system call stack in words for using MPU wrappers v2. #endif - /** - * @brief System call stack. - */ +/** + * @brief System call stack. + */ typedef struct SYSTEM_CALL_STACK_INFO { uint32_t ulSystemCallStackBuffer[ configSYSTEM_CALL_STACK_SIZE ]; @@ -218,74 +218,74 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P #endif /* configUSE_MPU_WRAPPERS_V1 == 0 */ - /** - * @brief MPU settings as stored in the TCB. - */ +/** + * @brief MPU settings as stored in the TCB. + */ #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) - #if( configENABLE_TRUSTZONE == 1 ) + #if ( configENABLE_TRUSTZONE == 1 ) - /* - * +-----------+---------------+----------+-----------------+------------------------------+-----+ - * | s16-s31 | s0-s15, FPSCR | r4-r11 | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, | | - * | | | | PC, xPSR | CONTROL, EXC_RETURN | | - * +-----------+---------------+----------+-----------------+------------------------------+-----+ - * - * <-----------><--------------><---------><----------------><-----------------------------><----> - * 16 16 8 8 5 1 - */ - #define MAX_CONTEXT_SIZE 54 +/* + * +-----------+---------------+----------+-----------------+------------------------------+-----+ + * | s16-s31 | s0-s15, FPSCR | r4-r11 | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, | | + * | | | | PC, xPSR | CONTROL, EXC_RETURN | | + * +-----------+---------------+----------+-----------------+------------------------------+-----+ + * + * <-----------><--------------><---------><----------------><-----------------------------><----> + * 16 16 8 8 5 1 + */ + #define MAX_CONTEXT_SIZE 54 #else /* #if( configENABLE_TRUSTZONE == 1 ) */ - /* - * +-----------+---------------+----------+-----------------+----------------------+-----+ - * | s16-s31 | s0-s15, FPSCR | r4-r11 | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL | | - * | | | | PC, xPSR | EXC_RETURN | | - * +-----------+---------------+----------+-----------------+----------------------+-----+ - * - * <-----------><--------------><---------><----------------><---------------------><----> - * 16 16 8 8 4 1 - */ - #define MAX_CONTEXT_SIZE 53 +/* + * +-----------+---------------+----------+-----------------+----------------------+-----+ + * | s16-s31 | s0-s15, FPSCR | r4-r11 | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL | | + * | | | | PC, xPSR | EXC_RETURN | | + * +-----------+---------------+----------+-----------------+----------------------+-----+ + * + * <-----------><--------------><---------><----------------><---------------------><----> + * 16 16 8 8 4 1 + */ + #define MAX_CONTEXT_SIZE 53 #endif /* #if( configENABLE_TRUSTZONE == 1 ) */ #else /* #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */ - #if( configENABLE_TRUSTZONE == 1 ) + #if ( configENABLE_TRUSTZONE == 1 ) - /* - * +----------+-----------------+------------------------------+-----+ - * | r4-r11 | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, | | - * | | PC, xPSR | CONTROL, EXC_RETURN | | - * +----------+-----------------+------------------------------+-----+ - * - * <---------><----------------><------------------------------><----> - * 8 8 5 1 - */ - #define MAX_CONTEXT_SIZE 22 +/* + * +----------+-----------------+------------------------------+-----+ + * | r4-r11 | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, | | + * | | PC, xPSR | CONTROL, EXC_RETURN | | + * +----------+-----------------+------------------------------+-----+ + * + * <---------><----------------><------------------------------><----> + * 8 8 5 1 + */ + #define MAX_CONTEXT_SIZE 22 #else /* #if( configENABLE_TRUSTZONE == 1 ) */ - /* - * +----------+-----------------+----------------------+-----+ - * | r4-r11 | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL | | - * | | PC, xPSR | EXC_RETURN | | - * +----------+-----------------+----------------------+-----+ - * - * <---------><----------------><----------------------><----> - * 8 8 4 1 - */ - #define MAX_CONTEXT_SIZE 21 +/* + * +----------+-----------------+----------------------+-----+ + * | r4-r11 | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL | | + * | | PC, xPSR | EXC_RETURN | | + * +----------+-----------------+----------------------+-----+ + * + * <---------><----------------><----------------------><----> + * 8 8 4 1 + */ + #define MAX_CONTEXT_SIZE 21 #endif /* #if( configENABLE_TRUSTZONE == 1 ) */ #endif /* #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */ - /* Flags used for xMPU_SETTINGS.ulTaskFlags member. */ - #define portSTACK_FRAME_HAS_PADDING_FLAG ( 1UL << 0UL ) - #define portTASK_IS_PRIVILEGED_FLAG ( 1UL << 1UL ) +/* Flags used for xMPU_SETTINGS.ulTaskFlags member. */ + #define portSTACK_FRAME_HAS_PADDING_FLAG ( 1UL << 0UL ) + #define portTASK_IS_PRIVILEGED_FLAG ( 1UL << 1UL ) /* Size of an Access Control List (ACL) entry in bits. */ #define portACL_ENTRY_SIZE_BITS ( 32U ) @@ -313,7 +313,7 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P * system calls. */ #ifdef configASSERT - #if ( portHAS_BASEPRI == 1 ) + #if ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) void vPortValidateInterruptPriority( void ); #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() vPortValidateInterruptPriority() #endif @@ -333,12 +333,29 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P /** * @brief Scheduler utilities. */ -#define portYIELD() vPortYield() +#if ( configENABLE_MPU == 1 ) + #define portYIELD() __asm volatile ( "svc %0" ::"i" ( portSVC_YIELD ) : "memory" ) + #define portYIELD_WITHIN_API() vPortYield() +#else + #define portYIELD() vPortYield() + #define portYIELD_WITHIN_API() vPortYield() +#endif + #define portNVIC_INT_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed04 ) ) #define portNVIC_PENDSVSET_BIT ( 1UL << 28UL ) -#define portEND_SWITCHING_ISR( xSwitchRequired ) \ - do { if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; } \ - while( 0 ) +#define portEND_SWITCHING_ISR( xSwitchRequired ) \ + do \ + { \ + if( xSwitchRequired ) \ + { \ + traceISR_EXIT_TO_SCHEDULER(); \ + portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; \ + } \ + else \ + { \ + traceISR_EXIT(); \ + } \ + } while( 0 ) #define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x ) /*-----------------------------------------------------------*/ @@ -424,12 +441,12 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P extern BaseType_t xPortIsTaskPrivileged( void ); - /** - * @brief Checks whether or not the calling task is privileged. - * - * @return pdTRUE if the calling task is privileged, pdFALSE otherwise. - */ - #define portIS_TASK_PRIVILEGED() xPortIsTaskPrivileged() +/** + * @brief Checks whether or not the calling task is privileged. + * + * @return pdTRUE if the calling task is privileged, pdFALSE otherwise. + */ + #define portIS_TASK_PRIVILEGED() xPortIsTaskPrivileged() #endif /* configENABLE_MPU == 1 */ /*-----------------------------------------------------------*/ @@ -440,6 +457,56 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P #define portMEMORY_BARRIER() __asm volatile ( "" ::: "memory" ) /*-----------------------------------------------------------*/ +/* Select correct value of configUSE_PORT_OPTIMISED_TASK_SELECTION + * based on whether or not Mainline extension is implemented. */ +#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION + #if ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) + #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1 + #else + #define configUSE_PORT_OPTIMISED_TASK_SELECTION 0 + #endif +#endif /* #ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION */ + +/** + * @brief Port-optimised task selection. + */ +#if ( configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 ) + +/** + * @brief Count the number of leading zeros in a 32-bit value. + */ + static portFORCE_INLINE uint32_t ulPortCountLeadingZeros( uint32_t ulBitmap ) + { + uint32_t ulReturn; + + __asm volatile ( "clz %0, %1" : "=r" ( ulReturn ) : "r" ( ulBitmap ) : "memory" ); + + return ulReturn; + } + +/* Check the configuration. */ + #if ( configMAX_PRIORITIES > 32 ) + #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 different priorities as tasks that share a priority will time slice. + #endif + + #if ( portHAS_ARMV8M_MAIN_EXTENSION == 0 ) + #error ARMv8-M baseline implementations (such as Cortex-M23) do not support port-optimised task selection. Please set configUSE_PORT_OPTIMISED_TASK_SELECTION to 0 or leave it undefined. + #endif + +/** + * @brief Store/clear the ready priorities in a bit map. + */ + #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) ) + #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) ) + +/** + * @brief Get the priority of the highest-priority task that is ready to execute. + */ + #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - ulPortCountLeadingZeros( ( uxReadyPriorities ) ) ) + +#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */ +/*-----------------------------------------------------------*/ + /* *INDENT-OFF* */ #ifdef __cplusplus } diff --git a/Source/portable/IAR/ARM_CM3/port.c b/Source/portable/IAR/ARM_CM3/port.c index 10ce8632a..e8b20aba2 100644 --- a/Source/portable/IAR/ARM_CM3/port.c +++ b/Source/portable/IAR/ARM_CM3/port.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -41,10 +41,14 @@ #error configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to 0. See http: /*www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */ #endif +/* Prototype of all Interrupt Service Routines (ISRs). */ +typedef void ( * portISR_t )( void ); + /* Constants required to manipulate the core. Registers first... */ #define portNVIC_SYSTICK_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000e010 ) ) #define portNVIC_SYSTICK_LOAD_REG ( *( ( volatile uint32_t * ) 0xe000e014 ) ) #define portNVIC_SYSTICK_CURRENT_VALUE_REG ( *( ( volatile uint32_t * ) 0xe000e018 ) ) +#define portNVIC_SHPR2_REG ( *( ( volatile uint32_t * ) 0xe000ed1c ) ) #define portNVIC_SHPR3_REG ( *( ( volatile uint32_t * ) 0xe000ed20 ) ) /* ...then bits in the registers. */ #define portNVIC_SYSTICK_CLK_BIT ( 1UL << 2UL ) @@ -59,6 +63,11 @@ #define portNVIC_PENDSV_PRI ( ( ( uint32_t ) portMIN_INTERRUPT_PRIORITY ) << 16UL ) #define portNVIC_SYSTICK_PRI ( ( ( uint32_t ) portMIN_INTERRUPT_PRIORITY ) << 24UL ) +/* Constants used to check the installation of the FreeRTOS interrupt handlers. */ +#define portSCB_VTOR_REG ( *( ( portISR_t ** ) 0xE000ED08 ) ) +#define portVECTOR_INDEX_SVC ( 11 ) +#define portVECTOR_INDEX_PENDSV ( 14 ) + /* Constants required to check the validity of an interrupt priority. */ #define portFIRST_USER_INTERRUPT_NUMBER ( 16 ) #define portNVIC_IP_REGISTERS_OFFSET_16 ( 0xE000E3F0 ) @@ -121,6 +130,11 @@ extern void vPortStartFirstTask( void ); */ static void prvTaskExitError( void ); +/* + * FreeRTOS handlers implemented in assembly. + */ +extern void vPortSVCHandler( void ); +extern void xPortPendSVHandler( void ); /*-----------------------------------------------------------*/ /* Each task maintains its own interrupt status in the critical nesting @@ -208,6 +222,40 @@ static void prvTaskExitError( void ) */ BaseType_t xPortStartScheduler( void ) { + /* An application can install FreeRTOS interrupt handlers in one of the + * folllowing ways: + * 1. Direct Routing - Install the functions vPortSVCHandler and + * xPortPendSVHandler for SVCall and PendSV interrupts respectively. + * 2. Indirect Routing - Install separate handlers for SVCall and PendSV + * interrupts and route program control from those handlers to + * vPortSVCHandler and xPortPendSVHandler functions. + * + * Applications that use Indirect Routing must set + * configCHECK_HANDLER_INSTALLATION to 0 in their FreeRTOSConfig.h. Direct + * routing, which is validated here when configCHECK_HANDLER_INSTALLATION + * is 1, should be preferred when possible. */ + #if ( configCHECK_HANDLER_INSTALLATION == 1 ) + { + const portISR_t * const pxVectorTable = portSCB_VTOR_REG; + + /* Validate that the application has correctly installed the FreeRTOS + * handlers for SVCall and PendSV interrupts. We do not check the + * installation of the SysTick handler because the application may + * choose to drive the RTOS tick using a timer other than the SysTick + * timer by overriding the weak function vPortSetupTimerInterrupt(). + * + * Assertion failures here indicate incorrect installation of the + * FreeRTOS handlers. For help installing the FreeRTOS handlers, see + * https://www.FreeRTOS.org/FAQHelp.html. + * + * Systems with a configurable address for the interrupt vector table + * can also encounter assertion failures or even system faults here if + * VTOR is not set correctly to point to the application's vector table. */ + configASSERT( pxVectorTable[ portVECTOR_INDEX_SVC ] == vPortSVCHandler ); + configASSERT( pxVectorTable[ portVECTOR_INDEX_PENDSV ] == xPortPendSVHandler ); + } + #endif /* configCHECK_HANDLER_INSTALLATION */ + #if ( configASSERT_DEFINED == 1 ) { volatile uint8_t ucOriginalPriority; @@ -243,7 +291,7 @@ BaseType_t xPortStartScheduler( void ) /* Check that the bits not implemented in hardware are zero in * configMAX_SYSCALL_INTERRUPT_PRIORITY. */ - configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( ~ucMaxPriorityValue ) ) == 0U ); + configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( uint8_t ) ( ~( uint32_t ) ucMaxPriorityValue ) ) == 0U ); /* Calculate the maximum acceptable priority group value for the number * of bits read back. */ @@ -257,22 +305,22 @@ BaseType_t xPortStartScheduler( void ) if( ulImplementedPrioBits == 8 ) { /* When the hardware implements 8 priority bits, there is no way for - * the software to configure PRIGROUP to not have sub-priorities. As - * a result, the least significant bit is always used for sub-priority - * and there are 128 preemption priorities and 2 sub-priorities. - * - * This may cause some confusion in some cases - for example, if - * configMAX_SYSCALL_INTERRUPT_PRIORITY is set to 5, both 5 and 4 - * priority interrupts will be masked in Critical Sections as those - * are at the same preemption priority. This may appear confusing as - * 4 is higher (numerically lower) priority than - * configMAX_SYSCALL_INTERRUPT_PRIORITY and therefore, should not - * have been masked. Instead, if we set configMAX_SYSCALL_INTERRUPT_PRIORITY - * to 4, this confusion does not happen and the behaviour remains the same. - * - * The following assert ensures that the sub-priority bit in the - * configMAX_SYSCALL_INTERRUPT_PRIORITY is clear to avoid the above mentioned - * confusion. */ + * the software to configure PRIGROUP to not have sub-priorities. As + * a result, the least significant bit is always used for sub-priority + * and there are 128 preemption priorities and 2 sub-priorities. + * + * This may cause some confusion in some cases - for example, if + * configMAX_SYSCALL_INTERRUPT_PRIORITY is set to 5, both 5 and 4 + * priority interrupts will be masked in Critical Sections as those + * are at the same preemption priority. This may appear confusing as + * 4 is higher (numerically lower) priority than + * configMAX_SYSCALL_INTERRUPT_PRIORITY and therefore, should not + * have been masked. Instead, if we set configMAX_SYSCALL_INTERRUPT_PRIORITY + * to 4, this confusion does not happen and the behaviour remains the same. + * + * The following assert ensures that the sub-priority bit in the + * configMAX_SYSCALL_INTERRUPT_PRIORITY is clear to avoid the above mentioned + * confusion. */ configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & 0x1U ) == 0U ); ulMaxPRIGROUPValue = 0; } @@ -292,9 +340,11 @@ BaseType_t xPortStartScheduler( void ) } #endif /* configASSERT_DEFINED */ - /* Make PendSV and SysTick the lowest priority interrupts. */ + /* Make PendSV and SysTick the lowest priority interrupts, and make SVCall + * the highest priority. */ portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI; portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI; + portNVIC_SHPR2_REG = 0; /* Start the timer that generates the tick ISR. Interrupts are disabled * here already. */ @@ -355,14 +405,21 @@ void xPortSysTickHandler( void ) * save and then restore the interrupt mask value as its value is already * known. */ portDISABLE_INTERRUPTS(); + traceISR_ENTER(); { /* Increment the RTOS tick. */ if( xTaskIncrementTick() != pdFALSE ) { + traceISR_EXIT_TO_SCHEDULER(); + /* A context switch is required. Context switching is performed in * the PendSV interrupt. Pend the PendSV interrupt. */ portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; } + else + { + traceISR_EXIT(); + } } portENABLE_INTERRUPTS(); } diff --git a/Source/portable/IAR/ARM_CM3/portasm.s b/Source/portable/IAR/ARM_CM3/portasm.s index dfaabc3b3..108af4468 100644 --- a/Source/portable/IAR/ARM_CM3/portasm.s +++ b/Source/portable/IAR/ARM_CM3/portasm.s @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/Source/portable/IAR/ARM_CM3/portmacro.h b/Source/portable/IAR/ARM_CM3/portmacro.h index 3e67345b1..7daa186b1 100644 --- a/Source/portable/IAR/ARM_CM3/portmacro.h +++ b/Source/portable/IAR/ARM_CM3/portmacro.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -28,7 +28,7 @@ #ifndef PORTMACRO_H - #define PORTMACRO_H +#define PORTMACRO_H /* *INDENT-OFF* */ #ifdef __cplusplus @@ -47,50 +47,50 @@ */ /* IAR includes. */ - #include +#include /* Type definitions. */ - #define portCHAR char - #define portFLOAT float - #define portDOUBLE double - #define portLONG long - #define portSHORT short - #define portSTACK_TYPE uint32_t - #define portBASE_TYPE long - - typedef portSTACK_TYPE StackType_t; - typedef long BaseType_t; - typedef unsigned long UBaseType_t; - - #if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS ) - typedef uint16_t TickType_t; - #define portMAX_DELAY ( TickType_t ) 0xffff - #elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS ) - typedef uint32_t TickType_t; - #define portMAX_DELAY ( TickType_t ) 0xffffffffUL +#define portCHAR char +#define portFLOAT float +#define portDOUBLE double +#define portLONG long +#define portSHORT short +#define portSTACK_TYPE uint32_t +#define portBASE_TYPE long + +typedef portSTACK_TYPE StackType_t; +typedef long BaseType_t; +typedef unsigned long UBaseType_t; + +#if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS ) + typedef uint16_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffff +#elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS ) + typedef uint32_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffffffffUL /* 32-bit tick type on a 32-bit architecture, so reads of the tick count do * not need to be guarded with a critical section. */ - #define portTICK_TYPE_IS_ATOMIC 1 - #else - #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width. - #endif + #define portTICK_TYPE_IS_ATOMIC 1 +#else + #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width. +#endif /*-----------------------------------------------------------*/ /* Architecture specifics. */ - #define portSTACK_GROWTH ( -1 ) - #define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) - #define portBYTE_ALIGNMENT 8 +#define portSTACK_GROWTH ( -1 ) +#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) +#define portBYTE_ALIGNMENT 8 /*-----------------------------------------------------------*/ /* Compiler directives. */ - #define portWEAK_SYMBOL __attribute__( ( weak ) ) +#define portWEAK_SYMBOL __attribute__( ( weak ) ) /*-----------------------------------------------------------*/ /* Scheduler utilities. */ - #define portYIELD() \ +#define portYIELD() \ { \ /* Set a PendSV to request a context switch. */ \ portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; \ @@ -98,112 +98,124 @@ __ISB(); \ } - #define portNVIC_INT_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed04 ) ) - #define portNVIC_PENDSVSET_BIT ( 1UL << 28UL ) - #define portEND_SWITCHING_ISR( xSwitchRequired ) do { if( xSwitchRequired != pdFALSE ) portYIELD(); } while( 0 ) - #define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x ) +#define portNVIC_INT_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed04 ) ) +#define portNVIC_PENDSVSET_BIT ( 1UL << 28UL ) +#define portEND_SWITCHING_ISR( xSwitchRequired ) \ + do \ + { \ + if( xSwitchRequired != pdFALSE ) \ + { \ + traceISR_EXIT_TO_SCHEDULER(); \ + portYIELD(); \ + } \ + else \ + { \ + traceISR_EXIT(); \ + } \ + } while( 0 ) +#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x ) /*-----------------------------------------------------------*/ /* Architecture specific optimisations. */ - #ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION - #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1 - #endif +#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION + #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1 +#endif - #if ( configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 ) +#if ( configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 ) /* Check the configuration. */ - #if ( configMAX_PRIORITIES > 32 ) - #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice. - #endif + #if ( configMAX_PRIORITIES > 32 ) + #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice. + #endif /* Store/clear the ready priorities in a bit map. */ - #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) ) - #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) ) + #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) ) + #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) ) /*-----------------------------------------------------------*/ - #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - ( ( uint32_t ) __CLZ( ( uxReadyPriorities ) ) ) ) + #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - ( ( uint32_t ) __CLZ( ( uxReadyPriorities ) ) ) ) - #endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */ +#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */ /*-----------------------------------------------------------*/ /* Critical section management. */ - extern void vPortEnterCritical( void ); - extern void vPortExitCritical( void ); +extern void vPortEnterCritical( void ); +extern void vPortExitCritical( void ); - #define portDISABLE_INTERRUPTS() \ +#define portDISABLE_INTERRUPTS() \ { \ __set_BASEPRI( configMAX_SYSCALL_INTERRUPT_PRIORITY ); \ __DSB(); \ __ISB(); \ } - #define portENABLE_INTERRUPTS() __set_BASEPRI( 0 ) - #define portENTER_CRITICAL() vPortEnterCritical() - #define portEXIT_CRITICAL() vPortExitCritical() - #define portSET_INTERRUPT_MASK_FROM_ISR() __get_BASEPRI(); portDISABLE_INTERRUPTS() - #define portCLEAR_INTERRUPT_MASK_FROM_ISR( x ) __set_BASEPRI( x ) +#define portENABLE_INTERRUPTS() __set_BASEPRI( 0 ) +#define portENTER_CRITICAL() vPortEnterCritical() +#define portEXIT_CRITICAL() vPortExitCritical() +#define portSET_INTERRUPT_MASK_FROM_ISR() __get_BASEPRI(); portDISABLE_INTERRUPTS() +#define portCLEAR_INTERRUPT_MASK_FROM_ISR( x ) __set_BASEPRI( x ) /*-----------------------------------------------------------*/ /* Tickless idle/low power functionality. */ - #ifndef portSUPPRESS_TICKS_AND_SLEEP - extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime ); - #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime ) vPortSuppressTicksAndSleep( xExpectedIdleTime ) - #endif +#ifndef portSUPPRESS_TICKS_AND_SLEEP + extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime ); + #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime ) vPortSuppressTicksAndSleep( xExpectedIdleTime ) +#endif /*-----------------------------------------------------------*/ /* Task function macros as described on the FreeRTOS.org WEB site. These are * not necessary for to use this port. They are defined so the common demo files * (which build with all the ports) will build. */ - #define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters ) - #define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters ) +#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters ) +#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters ) /*-----------------------------------------------------------*/ - #ifdef configASSERT - void vPortValidateInterruptPriority( void ); - #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() vPortValidateInterruptPriority() - #endif +#ifdef configASSERT + void vPortValidateInterruptPriority( void ); + #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() vPortValidateInterruptPriority() +#endif /* portNOP() is not required by this port. */ - #define portNOP() +#define portNOP() - #define portINLINE __inline +#define portINLINE __inline - #ifndef portFORCE_INLINE - #define portFORCE_INLINE inline __attribute__( ( always_inline ) ) - #endif +#ifndef portFORCE_INLINE + #define portFORCE_INLINE inline __attribute__( ( always_inline ) ) +#endif /*-----------------------------------------------------------*/ - portFORCE_INLINE static BaseType_t xPortIsInsideInterrupt( void ) +portFORCE_INLINE static BaseType_t xPortIsInsideInterrupt( void ) +{ + uint32_t ulCurrentInterrupt; + BaseType_t xReturn; + + /* Obtain the number of the currently executing interrupt. */ + __asm volatile ( "mrs %0, ipsr" : "=r" ( ulCurrentInterrupt )::"memory" ); + + if( ulCurrentInterrupt == 0 ) + { + xReturn = pdFALSE; + } + else { - uint32_t ulCurrentInterrupt; - BaseType_t xReturn; - - /* Obtain the number of the currently executing interrupt. */ - __asm volatile ( "mrs %0, ipsr" : "=r" ( ulCurrentInterrupt )::"memory" ); - - if( ulCurrentInterrupt == 0 ) - { - xReturn = pdFALSE; - } - else - { - xReturn = pdTRUE; - } - - return xReturn; + xReturn = pdTRUE; } + return xReturn; +} + /*-----------------------------------------------------------*/ /* Suppress warnings that are generated by the IAR tools, but cannot be fixed in * the source code because to do so would cause other compilers to generate * warnings. */ - #pragma diag_suppress=Pe191 - #pragma diag_suppress=Pa082 +#pragma diag_suppress=Pe191 +#pragma diag_suppress=Pa082 /* *INDENT-OFF* */ #ifdef __cplusplus diff --git a/Source/portable/IAR/ARM_CM33/non_secure/mpu_wrappers_v2_asm.S b/Source/portable/IAR/ARM_CM33/non_secure/mpu_wrappers_v2_asm.S index ef180bd91..b4f1fbc3b 100644 --- a/Source/portable/IAR/ARM_CM33/non_secure/mpu_wrappers_v2_asm.S +++ b/Source/portable/IAR/ARM_CM33/non_secure/mpu_wrappers_v2_asm.S @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -196,20 +196,6 @@ MPU_uxTaskGetNumberOfTasks: svc #SYSTEM_CALL_uxTaskGetNumberOfTasks /*-----------------------------------------------------------*/ - PUBLIC MPU_pcTaskGetName -MPU_pcTaskGetName: - push {r0} - mrs r0, control - tst r0, #1 - bne MPU_pcTaskGetName_Unpriv - MPU_pcTaskGetName_Priv: - pop {r0} - b MPU_pcTaskGetNameImpl - MPU_pcTaskGetName_Unpriv: - pop {r0} - svc #SYSTEM_CALL_pcTaskGetName -/*-----------------------------------------------------------*/ - PUBLIC MPU_ulTaskGetRunTimeCounter MPU_ulTaskGetRunTimeCounter: push {r0} @@ -742,24 +728,18 @@ MPU_xTimerGetTimerDaemonTaskHandle: svc #SYSTEM_CALL_xTimerGetTimerDaemonTaskHandle /*-----------------------------------------------------------*/ - PUBLIC MPU_xTimerGenericCommandEntry -MPU_xTimerGenericCommandEntry: + PUBLIC MPU_xTimerGenericCommandFromTaskEntry +MPU_xTimerGenericCommandFromTaskEntry: push {r0} - /* This function can be called from ISR also and therefore, we need a check - * to take privileged path, if called from ISR. */ - mrs r0, ipsr - cmp r0, #0 - bne MPU_xTimerGenericCommand_Priv mrs r0, control tst r0, #1 - beq MPU_xTimerGenericCommand_Priv - MPU_xTimerGenericCommand_Unpriv: + bne MPU_xTimerGenericCommandFromTask_Unpriv + MPU_xTimerGenericCommandFromTask_Priv: pop {r0} - svc #SYSTEM_CALL_xTimerGenericCommand - MPU_xTimerGenericCommand_Priv: + b MPU_xTimerGenericCommandFromTaskImpl + MPU_xTimerGenericCommandFromTask_Unpriv: pop {r0} - b MPU_xTimerGenericCommandPrivImpl - + svc #SYSTEM_CALL_xTimerGenericCommandFromTask /*-----------------------------------------------------------*/ PUBLIC MPU_pcTimerGetName @@ -1089,10 +1069,6 @@ MPU_xTaskGetTickCountImpl: MPU_uxTaskGetNumberOfTasksImpl: b MPU_uxTaskGetNumberOfTasksImpl - PUBWEAK MPU_pcTaskGetNameImpl -MPU_pcTaskGetNameImpl: - b MPU_pcTaskGetNameImpl - PUBWEAK MPU_ulTaskGetRunTimeCounterImpl MPU_ulTaskGetRunTimeCounterImpl: b MPU_ulTaskGetRunTimeCounterImpl @@ -1245,9 +1221,9 @@ MPU_xTimerIsTimerActiveImpl: MPU_xTimerGetTimerDaemonTaskHandleImpl: b MPU_xTimerGetTimerDaemonTaskHandleImpl - PUBWEAK MPU_xTimerGenericCommandPrivImpl -MPU_xTimerGenericCommandPrivImpl: - b MPU_xTimerGenericCommandPrivImpl + PUBWEAK MPU_xTimerGenericCommandFromTaskImpl +MPU_xTimerGenericCommandFromTaskImpl: + b MPU_xTimerGenericCommandFromTaskImpl PUBWEAK MPU_pcTimerGetNameImpl MPU_pcTimerGetNameImpl: diff --git a/Source/portable/IAR/ARM_CM33/non_secure/port.c b/Source/portable/IAR/ARM_CM33/non_secure/port.c index 9712ac353..230fe5fc2 100644 --- a/Source/portable/IAR/ARM_CM33/non_secure/port.c +++ b/Source/portable/IAR/ARM_CM33/non_secure/port.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -68,6 +68,22 @@ #if ( ( configRUN_FREERTOS_SECURE_ONLY == 1 ) && ( configENABLE_TRUSTZONE == 1 ) ) #error TrustZone needs to be disabled in order to run FreeRTOS on the Secure Side. #endif + +/** + * Cortex-M23 does not have non-secure PSPLIM. We should use PSPLIM on Cortex-M23 + * only when FreeRTOS runs on secure side. + */ +#if ( ( portHAS_ARMV8M_MAIN_EXTENSION == 0 ) && ( configRUN_FREERTOS_SECURE_ONLY == 0 ) ) + #define portUSE_PSPLIM_REGISTER 0 +#else + #define portUSE_PSPLIM_REGISTER 1 +#endif +/*-----------------------------------------------------------*/ + +/** + * @brief Prototype of all Interrupt Service Routines (ISRs). + */ +typedef void ( * portISR_t )( void ); /*-----------------------------------------------------------*/ /** @@ -91,10 +107,18 @@ /** * @brief Constants required to manipulate the SCB. */ -#define portSCB_SYS_HANDLER_CTRL_STATE_REG ( *( volatile uint32_t * ) 0xe000ed24 ) +#define portSCB_VTOR_REG ( *( ( portISR_t ** ) 0xe000ed08 ) ) +#define portSCB_SYS_HANDLER_CTRL_STATE_REG ( *( ( volatile uint32_t * ) 0xe000ed24 ) ) #define portSCB_MEM_FAULT_ENABLE_BIT ( 1UL << 16UL ) /*-----------------------------------------------------------*/ +/** + * @brief Constants used to check the installation of the FreeRTOS interrupt handlers. + */ +#define portVECTOR_INDEX_SVC ( 11 ) +#define portVECTOR_INDEX_PENDSV ( 14 ) +/*-----------------------------------------------------------*/ + /** * @brief Constants required to check the validity of an interrupt priority. */ @@ -111,8 +135,8 @@ /** * @brief Constants used during system call enter and exit. */ -#define portPSR_STACK_PADDING_MASK ( 1UL << 9UL ) -#define portEXC_RETURN_STACK_FRAME_TYPE_MASK ( 1UL << 4UL ) +#define portPSR_STACK_PADDING_MASK ( 1UL << 9UL ) +#define portEXC_RETURN_STACK_FRAME_TYPE_MASK ( 1UL << 4UL ) /*-----------------------------------------------------------*/ /** @@ -134,81 +158,81 @@ /** * @brief Offsets in the stack to the parameters when inside the SVC handler. */ -#define portOFFSET_TO_LR ( 5 ) -#define portOFFSET_TO_PC ( 6 ) -#define portOFFSET_TO_PSR ( 7 ) +#define portOFFSET_TO_LR ( 5 ) +#define portOFFSET_TO_PC ( 6 ) +#define portOFFSET_TO_PSR ( 7 ) /*-----------------------------------------------------------*/ /** * @brief Constants required to manipulate the MPU. */ -#define portMPU_TYPE_REG ( *( ( volatile uint32_t * ) 0xe000ed90 ) ) -#define portMPU_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed94 ) ) -#define portMPU_RNR_REG ( *( ( volatile uint32_t * ) 0xe000ed98 ) ) +#define portMPU_TYPE_REG ( *( ( volatile uint32_t * ) 0xe000ed90 ) ) +#define portMPU_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed94 ) ) +#define portMPU_RNR_REG ( *( ( volatile uint32_t * ) 0xe000ed98 ) ) -#define portMPU_RBAR_REG ( *( ( volatile uint32_t * ) 0xe000ed9c ) ) -#define portMPU_RLAR_REG ( *( ( volatile uint32_t * ) 0xe000eda0 ) ) +#define portMPU_RBAR_REG ( *( ( volatile uint32_t * ) 0xe000ed9c ) ) +#define portMPU_RLAR_REG ( *( ( volatile uint32_t * ) 0xe000eda0 ) ) -#define portMPU_RBAR_A1_REG ( *( ( volatile uint32_t * ) 0xe000eda4 ) ) -#define portMPU_RLAR_A1_REG ( *( ( volatile uint32_t * ) 0xe000eda8 ) ) +#define portMPU_RBAR_A1_REG ( *( ( volatile uint32_t * ) 0xe000eda4 ) ) +#define portMPU_RLAR_A1_REG ( *( ( volatile uint32_t * ) 0xe000eda8 ) ) -#define portMPU_RBAR_A2_REG ( *( ( volatile uint32_t * ) 0xe000edac ) ) -#define portMPU_RLAR_A2_REG ( *( ( volatile uint32_t * ) 0xe000edb0 ) ) +#define portMPU_RBAR_A2_REG ( *( ( volatile uint32_t * ) 0xe000edac ) ) +#define portMPU_RLAR_A2_REG ( *( ( volatile uint32_t * ) 0xe000edb0 ) ) -#define portMPU_RBAR_A3_REG ( *( ( volatile uint32_t * ) 0xe000edb4 ) ) -#define portMPU_RLAR_A3_REG ( *( ( volatile uint32_t * ) 0xe000edb8 ) ) +#define portMPU_RBAR_A3_REG ( *( ( volatile uint32_t * ) 0xe000edb4 ) ) +#define portMPU_RLAR_A3_REG ( *( ( volatile uint32_t * ) 0xe000edb8 ) ) -#define portMPU_MAIR0_REG ( *( ( volatile uint32_t * ) 0xe000edc0 ) ) -#define portMPU_MAIR1_REG ( *( ( volatile uint32_t * ) 0xe000edc4 ) ) +#define portMPU_MAIR0_REG ( *( ( volatile uint32_t * ) 0xe000edc0 ) ) +#define portMPU_MAIR1_REG ( *( ( volatile uint32_t * ) 0xe000edc4 ) ) -#define portMPU_RBAR_ADDRESS_MASK ( 0xffffffe0 ) /* Must be 32-byte aligned. */ -#define portMPU_RLAR_ADDRESS_MASK ( 0xffffffe0 ) /* Must be 32-byte aligned. */ +#define portMPU_RBAR_ADDRESS_MASK ( 0xffffffe0 ) /* Must be 32-byte aligned. */ +#define portMPU_RLAR_ADDRESS_MASK ( 0xffffffe0 ) /* Must be 32-byte aligned. */ -#define portMPU_RBAR_ACCESS_PERMISSIONS_MASK ( 3UL << 1UL ) +#define portMPU_RBAR_ACCESS_PERMISSIONS_MASK ( 3UL << 1UL ) -#define portMPU_MAIR_ATTR0_POS ( 0UL ) -#define portMPU_MAIR_ATTR0_MASK ( 0x000000ff ) +#define portMPU_MAIR_ATTR0_POS ( 0UL ) +#define portMPU_MAIR_ATTR0_MASK ( 0x000000ff ) -#define portMPU_MAIR_ATTR1_POS ( 8UL ) -#define portMPU_MAIR_ATTR1_MASK ( 0x0000ff00 ) +#define portMPU_MAIR_ATTR1_POS ( 8UL ) +#define portMPU_MAIR_ATTR1_MASK ( 0x0000ff00 ) -#define portMPU_MAIR_ATTR2_POS ( 16UL ) -#define portMPU_MAIR_ATTR2_MASK ( 0x00ff0000 ) +#define portMPU_MAIR_ATTR2_POS ( 16UL ) +#define portMPU_MAIR_ATTR2_MASK ( 0x00ff0000 ) -#define portMPU_MAIR_ATTR3_POS ( 24UL ) -#define portMPU_MAIR_ATTR3_MASK ( 0xff000000 ) +#define portMPU_MAIR_ATTR3_POS ( 24UL ) +#define portMPU_MAIR_ATTR3_MASK ( 0xff000000 ) -#define portMPU_MAIR_ATTR4_POS ( 0UL ) -#define portMPU_MAIR_ATTR4_MASK ( 0x000000ff ) +#define portMPU_MAIR_ATTR4_POS ( 0UL ) +#define portMPU_MAIR_ATTR4_MASK ( 0x000000ff ) -#define portMPU_MAIR_ATTR5_POS ( 8UL ) -#define portMPU_MAIR_ATTR5_MASK ( 0x0000ff00 ) +#define portMPU_MAIR_ATTR5_POS ( 8UL ) +#define portMPU_MAIR_ATTR5_MASK ( 0x0000ff00 ) -#define portMPU_MAIR_ATTR6_POS ( 16UL ) -#define portMPU_MAIR_ATTR6_MASK ( 0x00ff0000 ) +#define portMPU_MAIR_ATTR6_POS ( 16UL ) +#define portMPU_MAIR_ATTR6_MASK ( 0x00ff0000 ) -#define portMPU_MAIR_ATTR7_POS ( 24UL ) -#define portMPU_MAIR_ATTR7_MASK ( 0xff000000 ) +#define portMPU_MAIR_ATTR7_POS ( 24UL ) +#define portMPU_MAIR_ATTR7_MASK ( 0xff000000 ) -#define portMPU_RLAR_ATTR_INDEX0 ( 0UL << 1UL ) -#define portMPU_RLAR_ATTR_INDEX1 ( 1UL << 1UL ) -#define portMPU_RLAR_ATTR_INDEX2 ( 2UL << 1UL ) -#define portMPU_RLAR_ATTR_INDEX3 ( 3UL << 1UL ) -#define portMPU_RLAR_ATTR_INDEX4 ( 4UL << 1UL ) -#define portMPU_RLAR_ATTR_INDEX5 ( 5UL << 1UL ) -#define portMPU_RLAR_ATTR_INDEX6 ( 6UL << 1UL ) -#define portMPU_RLAR_ATTR_INDEX7 ( 7UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX0 ( 0UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX1 ( 1UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX2 ( 2UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX3 ( 3UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX4 ( 4UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX5 ( 5UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX6 ( 6UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX7 ( 7UL << 1UL ) -#define portMPU_RLAR_REGION_ENABLE ( 1UL ) +#define portMPU_RLAR_REGION_ENABLE ( 1UL ) /* Enable privileged access to unmapped region. */ -#define portMPU_PRIV_BACKGROUND_ENABLE_BIT ( 1UL << 2UL ) +#define portMPU_PRIV_BACKGROUND_ENABLE_BIT ( 1UL << 2UL ) /* Enable MPU. */ -#define portMPU_ENABLE_BIT ( 1UL << 0UL ) +#define portMPU_ENABLE_BIT ( 1UL << 0UL ) /* Expected value of the portMPU_TYPE register. */ -#define portEXPECTED_MPU_TYPE_VALUE ( configTOTAL_MPU_REGIONS << 8UL ) +#define portEXPECTED_MPU_TYPE_VALUE ( configTOTAL_MPU_REGIONS << 8UL ) /* Extract first address of the MPU region as encoded in the * RBAR (Region Base Address Register) value. */ @@ -448,13 +472,13 @@ portDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIV #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) - /** - * @brief Sets up the task stack so that upon returning from - * SVC, the task stack is used again. - * - * @param pulSystemCallStack The current SP when the SVC was raised. - * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler. - */ +/** + * @brief Sets up the task stack so that upon returning from + * SVC, the task stack is used again. + * + * @param pulSystemCallStack The current SP when the SVC was raised. + * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler. + */ void vSystemCallExit( uint32_t * pulSystemCallStack, uint32_t ulLR ) PRIVILEGED_FUNCTION; @@ -462,11 +486,11 @@ portDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIV #if ( configENABLE_MPU == 1 ) - /** - * @brief Checks whether or not the calling task is privileged. - * - * @return pdTRUE if the calling task is privileged, pdFALSE otherwise. - */ +/** + * @brief Checks whether or not the calling task is privileged. + * + * @return pdTRUE if the calling task is privileged, pdFALSE otherwise. + */ BaseType_t xPortIsTaskPrivileged( void ) PRIVILEGED_FUNCTION; #endif /* configENABLE_MPU == 1 */ @@ -501,13 +525,13 @@ PRIVILEGED_DATA static volatile uint32_t ulCriticalNesting = 0xaaaaaaaaUL; * FreeRTOS API functions are not called from interrupts that have been assigned * a priority above configMAX_SYSCALL_INTERRUPT_PRIORITY. */ -#if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) ) +#if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) static uint8_t ucMaxSysCallPriority = 0; static uint32_t ulMaxPRIGROUPValue = 0; static const volatile uint8_t * const pcInterruptPriorityRegisters = ( const volatile uint8_t * ) portNVIC_IP_REGISTERS_OFFSET_16; -#endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) ) */ +#endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */ #if ( configUSE_TICKLESS_IDLE == 1 ) @@ -760,8 +784,15 @@ __attribute__( ( weak ) ) void vPortSetupTimerInterrupt( void ) /* PRIVILEGED_FU } #endif /* configUSE_TICKLESS_IDLE */ - /* Stop and reset the SysTick. */ - portNVIC_SYSTICK_CTRL_REG = 0UL; + /* Stop and reset SysTick. + * + * QEMU versions older than 7.0.0 contain a bug which causes an error if we + * enable SysTick without first selecting a valid clock source. We trigger + * the bug if we change clock sources from a clock with a zero clock period + * to one with a nonzero clock period and enable Systick at the same time. + * So we configure the CLKSOURCE bit here, prior to setting the ENABLE bit. + * This workaround avoids the bug in QEMU versions older than 7.0.0. */ + portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT_CONFIG; portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL; /* Configure SysTick to interrupt at the requested rate. */ @@ -819,6 +850,7 @@ static void prvTaskExitError( void ) static void prvSetupMPU( void ) /* PRIVILEGED_FUNCTION */ { #if defined( __ARMCC_VERSION ) + /* Declaration when these variable are defined in code instead of being * exported from linker scripts. */ extern uint32_t * __privileged_functions_start__; @@ -972,13 +1004,19 @@ void SysTick_Handler( void ) /* PRIVILEGED_FUNCTION */ uint32_t ulPreviousMask; ulPreviousMask = portSET_INTERRUPT_MASK_FROM_ISR(); + traceISR_ENTER(); { /* Increment the RTOS tick. */ if( xTaskIncrementTick() != pdFALSE ) { + traceISR_EXIT_TO_SCHEDULER(); /* Pend a context switch. */ portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; } + else + { + traceISR_EXIT(); + } } portCLEAR_INTERRUPT_MASK_FROM_ISR( ulPreviousMask ); } @@ -988,6 +1026,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO { #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) ) #if defined( __ARMCC_VERSION ) + /* Declaration when these variable are defined in code instead of being * exported from linker scripts. */ extern uint32_t * __syscalls_flash_start__; @@ -1083,18 +1122,24 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO vRestoreContextOfFirstTask(); break; - #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) ) - case portSVC_RAISE_PRIVILEGE: + #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) ) + case portSVC_RAISE_PRIVILEGE: - /* Only raise the privilege, if the svc was raised from any of - * the system calls. */ - if( ( ulPC >= ( uint32_t ) __syscalls_flash_start__ ) && - ( ulPC <= ( uint32_t ) __syscalls_flash_end__ ) ) - { - vRaisePrivilege(); - } - break; - #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) */ + /* Only raise the privilege, if the svc was raised from any of + * the system calls. */ + if( ( ulPC >= ( uint32_t ) __syscalls_flash_start__ ) && + ( ulPC <= ( uint32_t ) __syscalls_flash_end__ ) ) + { + vRaisePrivilege(); + } + break; + #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) */ + + #if ( configENABLE_MPU == 1 ) + case portSVC_YIELD: + vPortYield(); + break; + #endif /* configENABLE_MPU == 1 */ default: /* Incorrect SVC call. */ @@ -1154,12 +1199,11 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO { /* Extended frame i.e. FPU in use. */ ulStackFrameSize = 26; - __asm volatile - ( + __asm volatile ( " vpush {s0} \n" /* Trigger lazy stacking. */ " vpop {s0} \n" /* Nullify the affect of the above instruction. */ ::: "memory" - ); + ); } else { @@ -1171,7 +1215,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO { ulStackFrameSize = 8; } - #endif /* if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */ + #endif /* configENABLE_FPU || configENABLE_MVE */ /* Make space on the system call stack for the stack frame. */ pulSystemCallStack = pulSystemCallStack - ulStackFrameSize; @@ -1187,18 +1231,24 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO * point (i.e. the caller of the MPU_). We need to restore it * when we exit from the system call. */ pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry = pulTaskStack[ portOFFSET_TO_LR ]; - /* Store the value of the PSPLIM register before the SVC was raised. * We need to restore it when we exit from the system call. */ - __asm volatile ( "mrs %0, psplim" : "=r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) ); + #if ( portUSE_PSPLIM_REGISTER == 1 ) + { + __asm volatile ( "mrs %0, psplim" : "=r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) ); + } + #endif /* Use the pulSystemCallStack in thread mode. */ __asm volatile ( "msr psp, %0" : : "r" ( pulSystemCallStack ) ); - __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) ); + #if ( portUSE_PSPLIM_REGISTER == 1 ) + { + __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) ); + } + #endif /* Start executing the system call upon returning from this handler. */ pulSystemCallStack[ portOFFSET_TO_PC ] = uxSystemCallImplementations[ ucSystemCallNumber ]; - /* Raise a request to exit from the system call upon finishing the * system call. */ pulSystemCallStack[ portOFFSET_TO_LR ] = ( uint32_t ) vRequestSystemCallExit; @@ -1224,14 +1274,13 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO pulSystemCallStack[ portOFFSET_TO_PSR ] &= ( ~portPSR_STACK_PADDING_MASK ); /* Raise the privilege for the duration of the system call. */ - __asm volatile - ( + __asm volatile ( " mrs r0, control \n" /* Obtain current control value. */ " movs r1, #1 \n" /* r1 = 1. */ " bics r0, r1 \n" /* Clear nPRIV bit. */ " msr control, r0 \n" /* Write back new control value. */ ::: "r0", "r1", "memory" - ); + ); } } @@ -1293,12 +1342,11 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO { /* Extended frame i.e. FPU in use. */ ulStackFrameSize = 26; - __asm volatile - ( + __asm volatile ( " vpush {s0} \n" /* Trigger lazy stacking. */ " vpop {s0} \n" /* Nullify the affect of the above instruction. */ ::: "memory" - ); + ); } else { @@ -1310,7 +1358,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO { ulStackFrameSize = 8; } - #endif /* if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */ + #endif /* configENABLE_FPU || configENABLE_MVE */ /* Make space on the task stack for the stack frame. */ pulTaskStack = pulTaskStack - ulStackFrameSize; @@ -1332,7 +1380,11 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO /* Restore the PSPLIM register to what it was at the time of * system call entry. */ - __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) ); + #if ( portUSE_PSPLIM_REGISTER == 1 ) + { + __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) ); + } + #endif /* If the hardware used padding to force the stack pointer * to be double word aligned, set the stacked xPSR bit[9], @@ -1350,14 +1402,13 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO pxMpuSettings->xSystemCallStackInfo.pulTaskStack = NULL; /* Drop the privilege before returning to the thread mode. */ - __asm volatile - ( + __asm volatile ( " mrs r0, control \n" /* Obtain current control value. */ " movs r1, #1 \n" /* r1 = 1. */ " orrs r0, r1 \n" /* Set nPRIV bit. */ " msr control, r0 \n" /* Write back new control value. */ ::: "r0", "r1", "memory" - ); + ); } } @@ -1410,21 +1461,21 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO xMPUSettings->ulContext[ ulIndex ] = 0x11111111; /* r11. */ ulIndex++; - xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pvParameters; /* r0. */ + xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pvParameters; /* r0. */ ulIndex++; - xMPUSettings->ulContext[ ulIndex ] = 0x01010101; /* r1. */ + xMPUSettings->ulContext[ ulIndex ] = 0x01010101; /* r1. */ ulIndex++; - xMPUSettings->ulContext[ ulIndex ] = 0x02020202; /* r2. */ + xMPUSettings->ulContext[ ulIndex ] = 0x02020202; /* r2. */ ulIndex++; - xMPUSettings->ulContext[ ulIndex ] = 0x03030303; /* r3. */ + xMPUSettings->ulContext[ ulIndex ] = 0x03030303; /* r3. */ ulIndex++; - xMPUSettings->ulContext[ ulIndex ] = 0x12121212; /* r12. */ + xMPUSettings->ulContext[ ulIndex ] = 0x12121212; /* r12. */ ulIndex++; xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portTASK_RETURN_ADDRESS; /* LR. */ ulIndex++; - xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxCode; /* PC. */ + xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxCode; /* PC. */ ulIndex++; - xMPUSettings->ulContext[ ulIndex ] = portINITIAL_XPSR; /* xPSR. */ + xMPUSettings->ulContext[ ulIndex ] = portINITIAL_XPSR; /* xPSR. */ ulIndex++; #if ( configENABLE_TRUSTZONE == 1 ) @@ -1435,8 +1486,9 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO #endif /* configENABLE_TRUSTZONE */ xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) ( pxTopOfStack - 8 ); /* PSP with the hardware saved stack. */ ulIndex++; - xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxEndOfStack; /* PSPLIM. */ + xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxEndOfStack; /* PSPLIM. */ ulIndex++; + if( xRunPrivileged == pdTRUE ) { xMPUSettings->ulTaskFlags |= portTASK_IS_PRIVILEGED_FLAG; @@ -1449,6 +1501,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portINITIAL_CONTROL_UNPRIVILEGED; /* CONTROL. */ ulIndex++; } + xMPUSettings->ulContext[ ulIndex ] = portINITIAL_EXC_RETURN; /* LR (EXC_RETURN). */ ulIndex++; @@ -1483,7 +1536,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO * interrupt. */ #if ( portPRELOAD_REGISTERS == 0 ) { - pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */ + pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */ *pxTopOfStack = portINITIAL_XPSR; /* xPSR. */ pxTopOfStack--; *pxTopOfStack = ( StackType_t ) pxCode; /* PC. */ @@ -1505,7 +1558,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO } #else /* portPRELOAD_REGISTERS */ { - pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */ + pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */ *pxTopOfStack = portINITIAL_XPSR; /* xPSR. */ pxTopOfStack--; *pxTopOfStack = ( StackType_t ) pxCode; /* PC. */ @@ -1540,7 +1593,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO pxTopOfStack--; *pxTopOfStack = portINITIAL_EXC_RETURN; /* EXC_RETURN. */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */ + *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */ #if ( configENABLE_TRUSTZONE == 1 ) { @@ -1559,22 +1612,52 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */ { - #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) ) + /* An application can install FreeRTOS interrupt handlers in one of the + * folllowing ways: + * 1. Direct Routing - Install the functions SVC_Handler and PendSV_Handler + * for SVCall and PendSV interrupts respectively. + * 2. Indirect Routing - Install separate handlers for SVCall and PendSV + * interrupts and route program control from those handlers to + * SVC_Handler and PendSV_Handler functions. + * + * Applications that use Indirect Routing must set + * configCHECK_HANDLER_INSTALLATION to 0 in their FreeRTOSConfig.h. Direct + * routing, which is validated here when configCHECK_HANDLER_INSTALLATION + * is 1, should be preferred when possible. */ + #if ( configCHECK_HANDLER_INSTALLATION == 1 ) + { + const portISR_t * const pxVectorTable = portSCB_VTOR_REG; + + /* Validate that the application has correctly installed the FreeRTOS + * handlers for SVCall and PendSV interrupts. We do not check the + * installation of the SysTick handler because the application may + * choose to drive the RTOS tick using a timer other than the SysTick + * timer by overriding the weak function vPortSetupTimerInterrupt(). + * + * Assertion failures here indicate incorrect installation of the + * FreeRTOS handlers. For help installing the FreeRTOS handlers, see + * https://www.FreeRTOS.org/FAQHelp.html. + * + * Systems with a configurable address for the interrupt vector table + * can also encounter assertion failures or even system faults here if + * VTOR is not set correctly to point to the application's vector table. */ + configASSERT( pxVectorTable[ portVECTOR_INDEX_SVC ] == SVC_Handler ); + configASSERT( pxVectorTable[ portVECTOR_INDEX_PENDSV ] == PendSV_Handler ); + } + #endif /* configCHECK_HANDLER_INSTALLATION */ + + #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) { - volatile uint32_t ulOriginalPriority; volatile uint32_t ulImplementedPrioBits = 0; volatile uint8_t ucMaxPriorityValue; /* Determine the maximum priority from which ISR safe FreeRTOS API - * functions can be called. ISR safe functions are those that end in - * "FromISR". FreeRTOS maintains separate thread and ISR API functions to + * functions can be called. ISR safe functions are those that end in + * "FromISR". FreeRTOS maintains separate thread and ISR API functions to * ensure interrupt entry is as fast and simple as possible. * - * Save the interrupt priority value that is about to be clobbered. */ - ulOriginalPriority = portNVIC_SHPR2_REG; - - /* Determine the number of priority bits available. First write to all - * possible bits. */ + * First, determine the number of priority bits available. Write to all + * possible bits in the priority setting for SVCall. */ portNVIC_SHPR2_REG = 0xFF000000; /* Read the value back to see how many bits stuck. */ @@ -1593,11 +1676,10 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */ /* Check that the bits not implemented in hardware are zero in * configMAX_SYSCALL_INTERRUPT_PRIORITY. */ - configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( ~ucMaxPriorityValue ) ) == 0U ); + configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( uint8_t ) ( ~( uint32_t ) ucMaxPriorityValue ) ) == 0U ); /* Calculate the maximum acceptable priority group value for the number * of bits read back. */ - while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE ) { ulImplementedPrioBits++; @@ -1635,16 +1717,14 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */ * register. */ ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT; ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK; - - /* Restore the clobbered interrupt priority register to its original - * value. */ - portNVIC_SHPR2_REG = ulOriginalPriority; } - #endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) ) */ + #endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */ - /* Make PendSV, CallSV and SysTick the same priority as the kernel. */ + /* Make PendSV and SysTick the lowest priority interrupts, and make SVCall + * the highest priority. */ portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI; portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI; + portNVIC_SHPR2_REG = 0; #if ( configENABLE_MPU == 1 ) { @@ -1701,6 +1781,7 @@ void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */ int32_t lIndex = 0; #if defined( __ARMCC_VERSION ) + /* Declaration when these variable are defined in code instead of being * exported from linker scripts. */ extern uint32_t * __privileged_sram_start__; @@ -1886,7 +1967,7 @@ BaseType_t xPortIsInsideInterrupt( void ) } /*-----------------------------------------------------------*/ -#if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) ) +#if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) void vPortValidateInterruptPriority( void ) { @@ -1944,7 +2025,7 @@ BaseType_t xPortIsInsideInterrupt( void ) configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue ); } -#endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) ) */ +#endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */ /*-----------------------------------------------------------*/ #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) diff --git a/Source/portable/IAR/ARM_CM33/non_secure/portasm.h b/Source/portable/IAR/ARM_CM33/non_secure/portasm.h index f64ceb525..c6d2ebd58 100644 --- a/Source/portable/IAR/ARM_CM33/non_secure/portasm.h +++ b/Source/portable/IAR/ARM_CM33/non_secure/portasm.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/Source/portable/IAR/ARM_CM33/non_secure/portasm.s b/Source/portable/IAR/ARM_CM33/non_secure/portasm.s index 530910341..6a6b677bf 100644 --- a/Source/portable/IAR/ARM_CM33/non_secure/portasm.s +++ b/Source/portable/IAR/ARM_CM33/non_secure/portasm.s @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/Source/portable/IAR/ARM_CM33/non_secure/portmacro.h b/Source/portable/IAR/ARM_CM33/non_secure/portmacro.h index 5afc234c1..ece523f2b 100644 --- a/Source/portable/IAR/ARM_CM33/non_secure/portmacro.h +++ b/Source/portable/IAR/ARM_CM33/non_secure/portmacro.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -48,12 +48,12 @@ /** * Architecture specifics. */ -#define portARCH_NAME "Cortex-M33" -#define portHAS_BASEPRI 1 -#define portDONT_DISCARD __root +#define portARCH_NAME "Cortex-M33" +#define portHAS_ARMV8M_MAIN_EXTENSION 1 +#define portDONT_DISCARD __root /*-----------------------------------------------------------*/ -#if( configTOTAL_MPU_REGIONS == 16 ) +#if ( configTOTAL_MPU_REGIONS == 16 ) #error 16 MPU regions are not yet supported for this port. #endif /*-----------------------------------------------------------*/ @@ -65,8 +65,8 @@ /** * @brief Critical section management. */ -#define portDISABLE_INTERRUPTS() ulSetInterruptMask() -#define portENABLE_INTERRUPTS() vClearInterruptMask( 0 ) +#define portDISABLE_INTERRUPTS() ulSetInterruptMask() +#define portENABLE_INTERRUPTS() vClearInterruptMask( 0 ) /*-----------------------------------------------------------*/ /* Suppress warnings that are generated by the IAR tools, but cannot be fixed in diff --git a/Source/portable/IAR/ARM_CM33/non_secure/portmacrocommon.h b/Source/portable/IAR/ARM_CM33/non_secure/portmacrocommon.h index 6f666da22..33f21d85b 100644 --- a/Source/portable/IAR/ARM_CM33/non_secure/portmacrocommon.h +++ b/Source/portable/IAR/ARM_CM33/non_secure/portmacrocommon.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -117,7 +117,7 @@ extern uint32_t ulSetInterruptMask( void ) /* __attribute__(( naked )) PRIVILEGE extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */; #if ( configENABLE_TRUSTZONE == 1 ) - extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize ); /* __attribute__ (( naked )) */ + extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize ); /* __attribute__ (( naked )) */ extern void vPortFreeSecureContext( uint32_t * pulTCB ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */; #endif /* configENABLE_TRUSTZONE */ @@ -188,13 +188,13 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P #if ( configENABLE_MPU == 1 ) - /** - * @brief Settings to define an MPU region. - */ +/** + * @brief Settings to define an MPU region. + */ typedef struct MPURegionSettings { - uint32_t ulRBAR; /**< RBAR for the region. */ - uint32_t ulRLAR; /**< RLAR for the region. */ + uint32_t ulRBAR; /**< RBAR for the region. */ + uint32_t ulRLAR; /**< RLAR for the region. */ } MPURegionSettings_t; #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) @@ -203,9 +203,9 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P #error configSYSTEM_CALL_STACK_SIZE must be defined to the desired size of the system call stack in words for using MPU wrappers v2. #endif - /** - * @brief System call stack. - */ +/** + * @brief System call stack. + */ typedef struct SYSTEM_CALL_STACK_INFO { uint32_t ulSystemCallStackBuffer[ configSYSTEM_CALL_STACK_SIZE ]; @@ -218,74 +218,74 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P #endif /* configUSE_MPU_WRAPPERS_V1 == 0 */ - /** - * @brief MPU settings as stored in the TCB. - */ +/** + * @brief MPU settings as stored in the TCB. + */ #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) - #if( configENABLE_TRUSTZONE == 1 ) + #if ( configENABLE_TRUSTZONE == 1 ) - /* - * +-----------+---------------+----------+-----------------+------------------------------+-----+ - * | s16-s31 | s0-s15, FPSCR | r4-r11 | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, | | - * | | | | PC, xPSR | CONTROL, EXC_RETURN | | - * +-----------+---------------+----------+-----------------+------------------------------+-----+ - * - * <-----------><--------------><---------><----------------><-----------------------------><----> - * 16 16 8 8 5 1 - */ - #define MAX_CONTEXT_SIZE 54 +/* + * +-----------+---------------+----------+-----------------+------------------------------+-----+ + * | s16-s31 | s0-s15, FPSCR | r4-r11 | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, | | + * | | | | PC, xPSR | CONTROL, EXC_RETURN | | + * +-----------+---------------+----------+-----------------+------------------------------+-----+ + * + * <-----------><--------------><---------><----------------><-----------------------------><----> + * 16 16 8 8 5 1 + */ + #define MAX_CONTEXT_SIZE 54 #else /* #if( configENABLE_TRUSTZONE == 1 ) */ - /* - * +-----------+---------------+----------+-----------------+----------------------+-----+ - * | s16-s31 | s0-s15, FPSCR | r4-r11 | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL | | - * | | | | PC, xPSR | EXC_RETURN | | - * +-----------+---------------+----------+-----------------+----------------------+-----+ - * - * <-----------><--------------><---------><----------------><---------------------><----> - * 16 16 8 8 4 1 - */ - #define MAX_CONTEXT_SIZE 53 +/* + * +-----------+---------------+----------+-----------------+----------------------+-----+ + * | s16-s31 | s0-s15, FPSCR | r4-r11 | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL | | + * | | | | PC, xPSR | EXC_RETURN | | + * +-----------+---------------+----------+-----------------+----------------------+-----+ + * + * <-----------><--------------><---------><----------------><---------------------><----> + * 16 16 8 8 4 1 + */ + #define MAX_CONTEXT_SIZE 53 #endif /* #if( configENABLE_TRUSTZONE == 1 ) */ #else /* #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */ - #if( configENABLE_TRUSTZONE == 1 ) + #if ( configENABLE_TRUSTZONE == 1 ) - /* - * +----------+-----------------+------------------------------+-----+ - * | r4-r11 | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, | | - * | | PC, xPSR | CONTROL, EXC_RETURN | | - * +----------+-----------------+------------------------------+-----+ - * - * <---------><----------------><------------------------------><----> - * 8 8 5 1 - */ - #define MAX_CONTEXT_SIZE 22 +/* + * +----------+-----------------+------------------------------+-----+ + * | r4-r11 | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, | | + * | | PC, xPSR | CONTROL, EXC_RETURN | | + * +----------+-----------------+------------------------------+-----+ + * + * <---------><----------------><------------------------------><----> + * 8 8 5 1 + */ + #define MAX_CONTEXT_SIZE 22 #else /* #if( configENABLE_TRUSTZONE == 1 ) */ - /* - * +----------+-----------------+----------------------+-----+ - * | r4-r11 | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL | | - * | | PC, xPSR | EXC_RETURN | | - * +----------+-----------------+----------------------+-----+ - * - * <---------><----------------><----------------------><----> - * 8 8 4 1 - */ - #define MAX_CONTEXT_SIZE 21 +/* + * +----------+-----------------+----------------------+-----+ + * | r4-r11 | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL | | + * | | PC, xPSR | EXC_RETURN | | + * +----------+-----------------+----------------------+-----+ + * + * <---------><----------------><----------------------><----> + * 8 8 4 1 + */ + #define MAX_CONTEXT_SIZE 21 #endif /* #if( configENABLE_TRUSTZONE == 1 ) */ #endif /* #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */ - /* Flags used for xMPU_SETTINGS.ulTaskFlags member. */ - #define portSTACK_FRAME_HAS_PADDING_FLAG ( 1UL << 0UL ) - #define portTASK_IS_PRIVILEGED_FLAG ( 1UL << 1UL ) +/* Flags used for xMPU_SETTINGS.ulTaskFlags member. */ + #define portSTACK_FRAME_HAS_PADDING_FLAG ( 1UL << 0UL ) + #define portTASK_IS_PRIVILEGED_FLAG ( 1UL << 1UL ) /* Size of an Access Control List (ACL) entry in bits. */ #define portACL_ENTRY_SIZE_BITS ( 32U ) @@ -313,7 +313,7 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P * system calls. */ #ifdef configASSERT - #if ( portHAS_BASEPRI == 1 ) + #if ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) void vPortValidateInterruptPriority( void ); #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() vPortValidateInterruptPriority() #endif @@ -333,12 +333,29 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P /** * @brief Scheduler utilities. */ -#define portYIELD() vPortYield() +#if ( configENABLE_MPU == 1 ) + #define portYIELD() __asm volatile ( "svc %0" ::"i" ( portSVC_YIELD ) : "memory" ) + #define portYIELD_WITHIN_API() vPortYield() +#else + #define portYIELD() vPortYield() + #define portYIELD_WITHIN_API() vPortYield() +#endif + #define portNVIC_INT_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed04 ) ) #define portNVIC_PENDSVSET_BIT ( 1UL << 28UL ) -#define portEND_SWITCHING_ISR( xSwitchRequired ) \ - do { if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; } \ - while( 0 ) +#define portEND_SWITCHING_ISR( xSwitchRequired ) \ + do \ + { \ + if( xSwitchRequired ) \ + { \ + traceISR_EXIT_TO_SCHEDULER(); \ + portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; \ + } \ + else \ + { \ + traceISR_EXIT(); \ + } \ + } while( 0 ) #define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x ) /*-----------------------------------------------------------*/ @@ -424,12 +441,12 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P extern BaseType_t xPortIsTaskPrivileged( void ); - /** - * @brief Checks whether or not the calling task is privileged. - * - * @return pdTRUE if the calling task is privileged, pdFALSE otherwise. - */ - #define portIS_TASK_PRIVILEGED() xPortIsTaskPrivileged() +/** + * @brief Checks whether or not the calling task is privileged. + * + * @return pdTRUE if the calling task is privileged, pdFALSE otherwise. + */ + #define portIS_TASK_PRIVILEGED() xPortIsTaskPrivileged() #endif /* configENABLE_MPU == 1 */ /*-----------------------------------------------------------*/ @@ -440,6 +457,56 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P #define portMEMORY_BARRIER() __asm volatile ( "" ::: "memory" ) /*-----------------------------------------------------------*/ +/* Select correct value of configUSE_PORT_OPTIMISED_TASK_SELECTION + * based on whether or not Mainline extension is implemented. */ +#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION + #if ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) + #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1 + #else + #define configUSE_PORT_OPTIMISED_TASK_SELECTION 0 + #endif +#endif /* #ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION */ + +/** + * @brief Port-optimised task selection. + */ +#if ( configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 ) + +/** + * @brief Count the number of leading zeros in a 32-bit value. + */ + static portFORCE_INLINE uint32_t ulPortCountLeadingZeros( uint32_t ulBitmap ) + { + uint32_t ulReturn; + + __asm volatile ( "clz %0, %1" : "=r" ( ulReturn ) : "r" ( ulBitmap ) : "memory" ); + + return ulReturn; + } + +/* Check the configuration. */ + #if ( configMAX_PRIORITIES > 32 ) + #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 different priorities as tasks that share a priority will time slice. + #endif + + #if ( portHAS_ARMV8M_MAIN_EXTENSION == 0 ) + #error ARMv8-M baseline implementations (such as Cortex-M23) do not support port-optimised task selection. Please set configUSE_PORT_OPTIMISED_TASK_SELECTION to 0 or leave it undefined. + #endif + +/** + * @brief Store/clear the ready priorities in a bit map. + */ + #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) ) + #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) ) + +/** + * @brief Get the priority of the highest-priority task that is ready to execute. + */ + #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - ulPortCountLeadingZeros( ( uxReadyPriorities ) ) ) + +#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */ +/*-----------------------------------------------------------*/ + /* *INDENT-OFF* */ #ifdef __cplusplus } diff --git a/Source/portable/IAR/ARM_CM33/secure/secure_context.c b/Source/portable/IAR/ARM_CM33/secure/secure_context.c index e37dd9672..83b3dbce1 100644 --- a/Source/portable/IAR/ARM_CM33/secure/secure_context.c +++ b/Source/portable/IAR/ARM_CM33/secure/secure_context.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -65,7 +65,7 @@ * @brief Maximum number of secure contexts. */ #ifndef secureconfigMAX_SECURE_CONTEXTS - #define secureconfigMAX_SECURE_CONTEXTS 8UL + #define secureconfigMAX_SECURE_CONTEXTS 8UL #endif /*-----------------------------------------------------------*/ @@ -164,15 +164,15 @@ secureportNON_SECURE_CALLABLE void SecureContext_Init( void ) } #if ( configENABLE_MPU == 1 ) - { - /* Configure thread mode to use PSP and to be unprivileged. */ - secureportSET_CONTROL( securecontextCONTROL_VALUE_UNPRIVILEGED ); - } + { + /* Configure thread mode to use PSP and to be unprivileged. */ + secureportSET_CONTROL( securecontextCONTROL_VALUE_UNPRIVILEGED ); + } #else /* configENABLE_MPU */ - { - /* Configure thread mode to use PSP and to be privileged. */ - secureportSET_CONTROL( securecontextCONTROL_VALUE_PRIVILEGED ); - } + { + /* Configure thread mode to use PSP and to be privileged. */ + secureportSET_CONTROL( securecontextCONTROL_VALUE_PRIVILEGED ); + } #endif /* configENABLE_MPU */ } } @@ -219,16 +219,16 @@ secureportNON_SECURE_CALLABLE void SecureContext_Init( void ) if( pucStackMemory != NULL ) { /* Since stack grows down, the starting point will be the last - * location. Note that this location is next to the last - * allocated byte for stack (excluding the space for seal values) - * because the hardware decrements the stack pointer before - * writing i.e. if stack pointer is 0x2, a push operation will - * decrement the stack pointer to 0x1 and then write at 0x1. */ + * location. Note that this location is next to the last + * allocated byte for stack (excluding the space for seal values) + * because the hardware decrements the stack pointer before + * writing i.e. if stack pointer is 0x2, a push operation will + * decrement the stack pointer to 0x1 and then write at 0x1. */ xSecureContexts[ ulSecureContextIndex ].pucStackStart = pucStackMemory + ulSecureStackSize; /* Seal the created secure process stack. */ - *( uint32_t * )( pucStackMemory + ulSecureStackSize ) = securecontextSTACK_SEAL_VALUE; - *( uint32_t * )( pucStackMemory + ulSecureStackSize + 4 ) = securecontextSTACK_SEAL_VALUE; + *( uint32_t * ) ( pucStackMemory + ulSecureStackSize ) = securecontextSTACK_SEAL_VALUE; + *( uint32_t * ) ( pucStackMemory + ulSecureStackSize + 4 ) = securecontextSTACK_SEAL_VALUE; /* The stack cannot go beyond this location. This value is * programmed in the PSPLIM register on context switch.*/ @@ -237,32 +237,32 @@ secureportNON_SECURE_CALLABLE void SecureContext_Init( void ) xSecureContexts[ ulSecureContextIndex ].pvTaskHandle = pvTaskHandle; #if ( configENABLE_MPU == 1 ) + { + /* Store the correct CONTROL value for the task on the stack. + * This value is programmed in the CONTROL register on + * context switch. */ + pulCurrentStackPointer = ( uint32_t * ) xSecureContexts[ ulSecureContextIndex ].pucStackStart; + pulCurrentStackPointer--; + + if( ulIsTaskPrivileged ) { - /* Store the correct CONTROL value for the task on the stack. - * This value is programmed in the CONTROL register on - * context switch. */ - pulCurrentStackPointer = ( uint32_t * ) xSecureContexts[ ulSecureContextIndex ].pucStackStart; - pulCurrentStackPointer--; - - if( ulIsTaskPrivileged ) - { - *( pulCurrentStackPointer ) = securecontextCONTROL_VALUE_PRIVILEGED; - } - else - { - *( pulCurrentStackPointer ) = securecontextCONTROL_VALUE_UNPRIVILEGED; - } - - /* Store the current stack pointer. This value is programmed in - * the PSP register on context switch. */ - xSecureContexts[ ulSecureContextIndex ].pucCurrentStackPointer = ( uint8_t * ) pulCurrentStackPointer; + *( pulCurrentStackPointer ) = securecontextCONTROL_VALUE_PRIVILEGED; } - #else /* configENABLE_MPU */ + else { - /* Current SP is set to the starting of the stack. This - * value programmed in the PSP register on context switch. */ - xSecureContexts[ ulSecureContextIndex ].pucCurrentStackPointer = xSecureContexts[ ulSecureContextIndex ].pucStackStart; + *( pulCurrentStackPointer ) = securecontextCONTROL_VALUE_UNPRIVILEGED; } + + /* Store the current stack pointer. This value is programmed in + * the PSP register on context switch. */ + xSecureContexts[ ulSecureContextIndex ].pucCurrentStackPointer = ( uint8_t * ) pulCurrentStackPointer; + } + #else /* configENABLE_MPU */ + { + /* Current SP is set to the starting of the stack. This + * value programmed in the PSP register on context switch. */ + xSecureContexts[ ulSecureContextIndex ].pucCurrentStackPointer = xSecureContexts[ ulSecureContextIndex ].pucStackStart; + } #endif /* configENABLE_MPU */ /* Ensure to never return 0 as a valid context handle. */ @@ -275,7 +275,8 @@ secureportNON_SECURE_CALLABLE void SecureContext_Init( void ) } /*-----------------------------------------------------------*/ -secureportNON_SECURE_CALLABLE void SecureContext_FreeContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle ) +secureportNON_SECURE_CALLABLE void SecureContext_FreeContext( SecureContextHandle_t xSecureContextHandle, + void * pvTaskHandle ) { uint32_t ulIPSR, ulSecureContextIndex; @@ -306,7 +307,8 @@ secureportNON_SECURE_CALLABLE void SecureContext_FreeContext( SecureContextHandl } /*-----------------------------------------------------------*/ -secureportNON_SECURE_CALLABLE void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle ) +secureportNON_SECURE_CALLABLE void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle, + void * pvTaskHandle ) { uint8_t * pucStackLimit; uint32_t ulSecureContextIndex; @@ -328,7 +330,8 @@ secureportNON_SECURE_CALLABLE void SecureContext_LoadContext( SecureContextHandl } /*-----------------------------------------------------------*/ -secureportNON_SECURE_CALLABLE void SecureContext_SaveContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle ) +secureportNON_SECURE_CALLABLE void SecureContext_SaveContext( SecureContextHandle_t xSecureContextHandle, + void * pvTaskHandle ) { uint8_t * pucStackLimit; uint32_t ulSecureContextIndex; diff --git a/Source/portable/IAR/ARM_CM33/secure/secure_context.h b/Source/portable/IAR/ARM_CM33/secure/secure_context.h index 2220ea646..40fdc276d 100644 --- a/Source/portable/IAR/ARM_CM33/secure/secure_context.h +++ b/Source/portable/IAR/ARM_CM33/secure/secure_context.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -38,12 +38,12 @@ /** * @brief PSP value when no secure context is loaded. */ -#define securecontextNO_STACK 0x0 +#define securecontextNO_STACK 0x0 /** * @brief Invalid context ID. */ -#define securecontextINVALID_CONTEXT_ID 0UL +#define securecontextINVALID_CONTEXT_ID 0UL /*-----------------------------------------------------------*/ /** @@ -108,7 +108,8 @@ void SecureContext_Init( void ); * @param[in] xSecureContextHandle Context handle corresponding to the * context to be freed. */ -void SecureContext_FreeContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle ); +void SecureContext_FreeContext( SecureContextHandle_t xSecureContextHandle, + void * pvTaskHandle ); /** * @brief Loads the given context. @@ -119,7 +120,8 @@ void SecureContext_FreeContext( SecureContextHandle_t xSecureContextHandle, void * @param[in] xSecureContextHandle Context handle corresponding to the context * to be loaded. */ -void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle ); +void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle, + void * pvTaskHandle ); /** * @brief Saves the given context. @@ -130,6 +132,7 @@ void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle, void * @param[in] xSecureContextHandle Context handle corresponding to the context * to be saved. */ -void SecureContext_SaveContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle ); +void SecureContext_SaveContext( SecureContextHandle_t xSecureContextHandle, + void * pvTaskHandle ); #endif /* __SECURE_CONTEXT_H__ */ diff --git a/Source/portable/IAR/ARM_CM33/secure/secure_context_port_asm.s b/Source/portable/IAR/ARM_CM33/secure/secure_context_port_asm.s index 0da3e0f12..5124d9246 100644 --- a/Source/portable/IAR/ARM_CM33/secure/secure_context_port_asm.s +++ b/Source/portable/IAR/ARM_CM33/secure/secure_context_port_asm.s @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/Source/portable/IAR/ARM_CM33/secure/secure_heap.c b/Source/portable/IAR/ARM_CM33/secure/secure_heap.c index 19f7c2354..d9789404b 100644 --- a/Source/portable/IAR/ARM_CM33/secure/secure_heap.c +++ b/Source/portable/IAR/ARM_CM33/secure/secure_heap.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -62,6 +62,22 @@ /* Assumes 8bit bytes! */ #define secureheapBITS_PER_BYTE ( ( size_t ) 8 ) + +/* Max value that fits in a size_t type. */ +#define secureheapSIZE_MAX ( ~( ( size_t ) 0 ) ) + +/* Check if adding a and b will result in overflow. */ +#define secureheapADD_WILL_OVERFLOW( a, b ) ( ( a ) > ( secureheapSIZE_MAX - ( b ) ) ) + +/* MSB of the xBlockSize member of an BlockLink_t structure is used to track + * the allocation status of a block. When MSB of the xBlockSize member of + * an BlockLink_t structure is set then the block belongs to the application. + * When the bit is free the block is still part of the free heap space. */ +#define secureheapBLOCK_ALLOCATED_BITMASK ( ( ( size_t ) 1 ) << ( ( sizeof( size_t ) * secureheapBITS_PER_BYTE ) - 1 ) ) +#define secureheapBLOCK_SIZE_IS_VALID( xBlockSize ) ( ( ( xBlockSize ) & secureheapBLOCK_ALLOCATED_BITMASK ) == 0 ) +#define secureheapBLOCK_IS_ALLOCATED( pxBlock ) ( ( ( pxBlock->xBlockSize ) & secureheapBLOCK_ALLOCATED_BITMASK ) != 0 ) +#define secureheapALLOCATE_BLOCK( pxBlock ) ( ( pxBlock->xBlockSize ) |= secureheapBLOCK_ALLOCATED_BITMASK ) +#define secureheapFREE_BLOCK( pxBlock ) ( ( pxBlock->xBlockSize ) &= ~secureheapBLOCK_ALLOCATED_BITMASK ) /*-----------------------------------------------------------*/ /* Allocate the memory for the heap. */ @@ -123,14 +139,6 @@ static BlockLink_t * pxEnd = NULL; static size_t xFreeBytesRemaining = 0U; static size_t xMinimumEverFreeBytesRemaining = 0U; -/** - * @brief Gets set to the top bit of an size_t type. - * - * When this bit in the xBlockSize member of an BlockLink_t structure is set - * then the block belongs to the application. When the bit is free the block is - * still part of the free heap space. - */ -static size_t xBlockAllocatedBit = 0; /*-----------------------------------------------------------*/ static void prvHeapInit( void ) @@ -175,9 +183,6 @@ static void prvHeapInit( void ) /* Only one block exists - and it covers the entire usable heap space. */ xMinimumEverFreeBytesRemaining = pxFirstFreeBlock->xBlockSize; xFreeBytesRemaining = pxFirstFreeBlock->xBlockSize; - - /* Work out the position of the top bit in a size_t variable. */ - xBlockAllocatedBit = ( ( size_t ) 1 ) << ( ( sizeof( size_t ) * secureheapBITS_PER_BYTE ) - 1 ); } /*-----------------------------------------------------------*/ @@ -250,6 +255,7 @@ void * pvPortMalloc( size_t xWantedSize ) BlockLink_t * pxPreviousBlock; BlockLink_t * pxNewBlockLink; void * pvReturn = NULL; + size_t xAdditionalRequiredSize; /* If this is the first call to malloc then the heap will require * initialisation to setup the list of free blocks. */ @@ -262,25 +268,29 @@ void * pvPortMalloc( size_t xWantedSize ) mtCOVERAGE_TEST_MARKER(); } - /* Check the requested block size is not so large that the top bit is set. - * The top bit of the block size member of the BlockLink_t structure is used - * to determine who owns the block - the application or the kernel, so it - * must be free. */ - if( ( xWantedSize & xBlockAllocatedBit ) == 0 ) + if( xWantedSize > 0 ) { - /* The wanted size is increased so it can contain a BlockLink_t + /* The wanted size must be increased so it can contain a BlockLink_t * structure in addition to the requested amount of bytes. */ - if( xWantedSize > 0 ) + if( secureheapADD_WILL_OVERFLOW( xWantedSize, xHeapStructSize ) == 0 ) { xWantedSize += xHeapStructSize; - /* Ensure that blocks are always aligned to the required number of - * bytes. */ + /* Ensure that blocks are always aligned to the required number + * of bytes. */ if( ( xWantedSize & secureportBYTE_ALIGNMENT_MASK ) != 0x00 ) { /* Byte alignment required. */ - xWantedSize += ( secureportBYTE_ALIGNMENT - ( xWantedSize & secureportBYTE_ALIGNMENT_MASK ) ); - secureportASSERT( ( xWantedSize & secureportBYTE_ALIGNMENT_MASK ) == 0 ); + xAdditionalRequiredSize = secureportBYTE_ALIGNMENT - ( xWantedSize & secureportBYTE_ALIGNMENT_MASK ); + + if( secureheapADD_WILL_OVERFLOW( xWantedSize, xAdditionalRequiredSize ) == 0 ) + { + xWantedSize += xAdditionalRequiredSize; + } + else + { + xWantedSize = 0; + } } else { @@ -289,9 +299,20 @@ void * pvPortMalloc( size_t xWantedSize ) } else { - mtCOVERAGE_TEST_MARKER(); + xWantedSize = 0; } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + /* Check the requested block size is not so large that the top bit is set. + * The top bit of the block size member of the BlockLink_t structure is used + * to determine who owns the block - the application or the kernel, so it + * must be free. */ + if( secureheapBLOCK_SIZE_IS_VALID( xWantedSize ) != 0 ) + { if( ( xWantedSize > 0 ) && ( xWantedSize <= xFreeBytesRemaining ) ) { /* Traverse the list from the start (lowest address) block until @@ -334,7 +355,8 @@ void * pvPortMalloc( size_t xWantedSize ) pxBlock->xBlockSize = xWantedSize; /* Insert the new block into the list of free blocks. */ - prvInsertBlockIntoFreeList( pxNewBlockLink ); + pxNewBlockLink->pxNextFreeBlock = pxPreviousBlock->pxNextFreeBlock; + pxPreviousBlock->pxNextFreeBlock = pxNewBlockLink; } else { @@ -354,7 +376,7 @@ void * pvPortMalloc( size_t xWantedSize ) /* The block is being returned - it is allocated and owned by * the application and has no "next" block. */ - pxBlock->xBlockSize |= xBlockAllocatedBit; + secureheapALLOCATE_BLOCK( pxBlock ); pxBlock->pxNextFreeBlock = NULL; } else @@ -375,17 +397,17 @@ void * pvPortMalloc( size_t xWantedSize ) traceMALLOC( pvReturn, xWantedSize ); #if ( secureconfigUSE_MALLOC_FAILED_HOOK == 1 ) + { + if( pvReturn == NULL ) { - if( pvReturn == NULL ) - { - extern void vApplicationMallocFailedHook( void ); - vApplicationMallocFailedHook(); - } - else - { - mtCOVERAGE_TEST_MARKER(); - } + extern void vApplicationMallocFailedHook( void ); + vApplicationMallocFailedHook(); } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } #endif /* if ( secureconfigUSE_MALLOC_FAILED_HOOK == 1 ) */ secureportASSERT( ( ( ( size_t ) pvReturn ) & ( size_t ) secureportBYTE_ALIGNMENT_MASK ) == 0 ); @@ -408,16 +430,16 @@ void vPortFree( void * pv ) pxLink = ( void * ) puc; /* Check the block is actually allocated. */ - secureportASSERT( ( pxLink->xBlockSize & xBlockAllocatedBit ) != 0 ); + secureportASSERT( secureheapBLOCK_IS_ALLOCATED( pxLink ) != 0 ); secureportASSERT( pxLink->pxNextFreeBlock == NULL ); - if( ( pxLink->xBlockSize & xBlockAllocatedBit ) != 0 ) + if( secureheapBLOCK_IS_ALLOCATED( pxLink ) != 0 ) { if( pxLink->pxNextFreeBlock == NULL ) { /* The block is being returned to the heap - it is no longer * allocated. */ - pxLink->xBlockSize &= ~xBlockAllocatedBit; + secureheapFREE_BLOCK( pxLink ); secureportDISABLE_NON_SECURE_INTERRUPTS(); { diff --git a/Source/portable/IAR/ARM_CM33/secure/secure_heap.h b/Source/portable/IAR/ARM_CM33/secure/secure_heap.h index 75c9cb00b..cf5551046 100644 --- a/Source/portable/IAR/ARM_CM33/secure/secure_heap.h +++ b/Source/portable/IAR/ARM_CM33/secure/secure_heap.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/Source/portable/IAR/ARM_CM33/secure/secure_init.c b/Source/portable/IAR/ARM_CM33/secure/secure_init.c index f93bfce95..66d35eccc 100644 --- a/Source/portable/IAR/ARM_CM33/secure/secure_init.c +++ b/Source/portable/IAR/ARM_CM33/secure/secure_init.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -93,7 +93,7 @@ secureportNON_SECURE_CALLABLE void SecureInit_EnableNSFPUAccess( void ) * permitted. CP11 should be programmed to the same value as CP10. */ *( secureinitNSACR ) |= ( secureinitNSACR_CP10_MASK | secureinitNSACR_CP11_MASK ); - /* LSPENS = 0 ==> LSPEN is writable fron non-secure state. This ensures + /* LSPENS = 0 ==> LSPEN is writable from non-secure state. This ensures * that we can enable/disable lazy stacking in port.c file. */ *( secureinitFPCCR ) &= ~( secureinitFPCCR_LSPENS_MASK ); diff --git a/Source/portable/IAR/ARM_CM33/secure/secure_init.h b/Source/portable/IAR/ARM_CM33/secure/secure_init.h index e6c9da0b4..6404c5cc4 100644 --- a/Source/portable/IAR/ARM_CM33/secure/secure_init.h +++ b/Source/portable/IAR/ARM_CM33/secure/secure_init.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/Source/portable/IAR/ARM_CM33/secure/secure_port_macros.h b/Source/portable/IAR/ARM_CM33/secure/secure_port_macros.h index d7ac5833c..085108cc1 100644 --- a/Source/portable/IAR/ARM_CM33/secure/secure_port_macros.h +++ b/Source/portable/IAR/ARM_CM33/secure/secure_port_macros.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/Source/portable/IAR/ARM_CM33_NTZ/non_secure/mpu_wrappers_v2_asm.S b/Source/portable/IAR/ARM_CM33_NTZ/non_secure/mpu_wrappers_v2_asm.S index ef180bd91..b4f1fbc3b 100644 --- a/Source/portable/IAR/ARM_CM33_NTZ/non_secure/mpu_wrappers_v2_asm.S +++ b/Source/portable/IAR/ARM_CM33_NTZ/non_secure/mpu_wrappers_v2_asm.S @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -196,20 +196,6 @@ MPU_uxTaskGetNumberOfTasks: svc #SYSTEM_CALL_uxTaskGetNumberOfTasks /*-----------------------------------------------------------*/ - PUBLIC MPU_pcTaskGetName -MPU_pcTaskGetName: - push {r0} - mrs r0, control - tst r0, #1 - bne MPU_pcTaskGetName_Unpriv - MPU_pcTaskGetName_Priv: - pop {r0} - b MPU_pcTaskGetNameImpl - MPU_pcTaskGetName_Unpriv: - pop {r0} - svc #SYSTEM_CALL_pcTaskGetName -/*-----------------------------------------------------------*/ - PUBLIC MPU_ulTaskGetRunTimeCounter MPU_ulTaskGetRunTimeCounter: push {r0} @@ -742,24 +728,18 @@ MPU_xTimerGetTimerDaemonTaskHandle: svc #SYSTEM_CALL_xTimerGetTimerDaemonTaskHandle /*-----------------------------------------------------------*/ - PUBLIC MPU_xTimerGenericCommandEntry -MPU_xTimerGenericCommandEntry: + PUBLIC MPU_xTimerGenericCommandFromTaskEntry +MPU_xTimerGenericCommandFromTaskEntry: push {r0} - /* This function can be called from ISR also and therefore, we need a check - * to take privileged path, if called from ISR. */ - mrs r0, ipsr - cmp r0, #0 - bne MPU_xTimerGenericCommand_Priv mrs r0, control tst r0, #1 - beq MPU_xTimerGenericCommand_Priv - MPU_xTimerGenericCommand_Unpriv: + bne MPU_xTimerGenericCommandFromTask_Unpriv + MPU_xTimerGenericCommandFromTask_Priv: pop {r0} - svc #SYSTEM_CALL_xTimerGenericCommand - MPU_xTimerGenericCommand_Priv: + b MPU_xTimerGenericCommandFromTaskImpl + MPU_xTimerGenericCommandFromTask_Unpriv: pop {r0} - b MPU_xTimerGenericCommandPrivImpl - + svc #SYSTEM_CALL_xTimerGenericCommandFromTask /*-----------------------------------------------------------*/ PUBLIC MPU_pcTimerGetName @@ -1089,10 +1069,6 @@ MPU_xTaskGetTickCountImpl: MPU_uxTaskGetNumberOfTasksImpl: b MPU_uxTaskGetNumberOfTasksImpl - PUBWEAK MPU_pcTaskGetNameImpl -MPU_pcTaskGetNameImpl: - b MPU_pcTaskGetNameImpl - PUBWEAK MPU_ulTaskGetRunTimeCounterImpl MPU_ulTaskGetRunTimeCounterImpl: b MPU_ulTaskGetRunTimeCounterImpl @@ -1245,9 +1221,9 @@ MPU_xTimerIsTimerActiveImpl: MPU_xTimerGetTimerDaemonTaskHandleImpl: b MPU_xTimerGetTimerDaemonTaskHandleImpl - PUBWEAK MPU_xTimerGenericCommandPrivImpl -MPU_xTimerGenericCommandPrivImpl: - b MPU_xTimerGenericCommandPrivImpl + PUBWEAK MPU_xTimerGenericCommandFromTaskImpl +MPU_xTimerGenericCommandFromTaskImpl: + b MPU_xTimerGenericCommandFromTaskImpl PUBWEAK MPU_pcTimerGetNameImpl MPU_pcTimerGetNameImpl: diff --git a/Source/portable/IAR/ARM_CM33_NTZ/non_secure/port.c b/Source/portable/IAR/ARM_CM33_NTZ/non_secure/port.c index 9712ac353..230fe5fc2 100644 --- a/Source/portable/IAR/ARM_CM33_NTZ/non_secure/port.c +++ b/Source/portable/IAR/ARM_CM33_NTZ/non_secure/port.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -68,6 +68,22 @@ #if ( ( configRUN_FREERTOS_SECURE_ONLY == 1 ) && ( configENABLE_TRUSTZONE == 1 ) ) #error TrustZone needs to be disabled in order to run FreeRTOS on the Secure Side. #endif + +/** + * Cortex-M23 does not have non-secure PSPLIM. We should use PSPLIM on Cortex-M23 + * only when FreeRTOS runs on secure side. + */ +#if ( ( portHAS_ARMV8M_MAIN_EXTENSION == 0 ) && ( configRUN_FREERTOS_SECURE_ONLY == 0 ) ) + #define portUSE_PSPLIM_REGISTER 0 +#else + #define portUSE_PSPLIM_REGISTER 1 +#endif +/*-----------------------------------------------------------*/ + +/** + * @brief Prototype of all Interrupt Service Routines (ISRs). + */ +typedef void ( * portISR_t )( void ); /*-----------------------------------------------------------*/ /** @@ -91,10 +107,18 @@ /** * @brief Constants required to manipulate the SCB. */ -#define portSCB_SYS_HANDLER_CTRL_STATE_REG ( *( volatile uint32_t * ) 0xe000ed24 ) +#define portSCB_VTOR_REG ( *( ( portISR_t ** ) 0xe000ed08 ) ) +#define portSCB_SYS_HANDLER_CTRL_STATE_REG ( *( ( volatile uint32_t * ) 0xe000ed24 ) ) #define portSCB_MEM_FAULT_ENABLE_BIT ( 1UL << 16UL ) /*-----------------------------------------------------------*/ +/** + * @brief Constants used to check the installation of the FreeRTOS interrupt handlers. + */ +#define portVECTOR_INDEX_SVC ( 11 ) +#define portVECTOR_INDEX_PENDSV ( 14 ) +/*-----------------------------------------------------------*/ + /** * @brief Constants required to check the validity of an interrupt priority. */ @@ -111,8 +135,8 @@ /** * @brief Constants used during system call enter and exit. */ -#define portPSR_STACK_PADDING_MASK ( 1UL << 9UL ) -#define portEXC_RETURN_STACK_FRAME_TYPE_MASK ( 1UL << 4UL ) +#define portPSR_STACK_PADDING_MASK ( 1UL << 9UL ) +#define portEXC_RETURN_STACK_FRAME_TYPE_MASK ( 1UL << 4UL ) /*-----------------------------------------------------------*/ /** @@ -134,81 +158,81 @@ /** * @brief Offsets in the stack to the parameters when inside the SVC handler. */ -#define portOFFSET_TO_LR ( 5 ) -#define portOFFSET_TO_PC ( 6 ) -#define portOFFSET_TO_PSR ( 7 ) +#define portOFFSET_TO_LR ( 5 ) +#define portOFFSET_TO_PC ( 6 ) +#define portOFFSET_TO_PSR ( 7 ) /*-----------------------------------------------------------*/ /** * @brief Constants required to manipulate the MPU. */ -#define portMPU_TYPE_REG ( *( ( volatile uint32_t * ) 0xe000ed90 ) ) -#define portMPU_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed94 ) ) -#define portMPU_RNR_REG ( *( ( volatile uint32_t * ) 0xe000ed98 ) ) +#define portMPU_TYPE_REG ( *( ( volatile uint32_t * ) 0xe000ed90 ) ) +#define portMPU_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed94 ) ) +#define portMPU_RNR_REG ( *( ( volatile uint32_t * ) 0xe000ed98 ) ) -#define portMPU_RBAR_REG ( *( ( volatile uint32_t * ) 0xe000ed9c ) ) -#define portMPU_RLAR_REG ( *( ( volatile uint32_t * ) 0xe000eda0 ) ) +#define portMPU_RBAR_REG ( *( ( volatile uint32_t * ) 0xe000ed9c ) ) +#define portMPU_RLAR_REG ( *( ( volatile uint32_t * ) 0xe000eda0 ) ) -#define portMPU_RBAR_A1_REG ( *( ( volatile uint32_t * ) 0xe000eda4 ) ) -#define portMPU_RLAR_A1_REG ( *( ( volatile uint32_t * ) 0xe000eda8 ) ) +#define portMPU_RBAR_A1_REG ( *( ( volatile uint32_t * ) 0xe000eda4 ) ) +#define portMPU_RLAR_A1_REG ( *( ( volatile uint32_t * ) 0xe000eda8 ) ) -#define portMPU_RBAR_A2_REG ( *( ( volatile uint32_t * ) 0xe000edac ) ) -#define portMPU_RLAR_A2_REG ( *( ( volatile uint32_t * ) 0xe000edb0 ) ) +#define portMPU_RBAR_A2_REG ( *( ( volatile uint32_t * ) 0xe000edac ) ) +#define portMPU_RLAR_A2_REG ( *( ( volatile uint32_t * ) 0xe000edb0 ) ) -#define portMPU_RBAR_A3_REG ( *( ( volatile uint32_t * ) 0xe000edb4 ) ) -#define portMPU_RLAR_A3_REG ( *( ( volatile uint32_t * ) 0xe000edb8 ) ) +#define portMPU_RBAR_A3_REG ( *( ( volatile uint32_t * ) 0xe000edb4 ) ) +#define portMPU_RLAR_A3_REG ( *( ( volatile uint32_t * ) 0xe000edb8 ) ) -#define portMPU_MAIR0_REG ( *( ( volatile uint32_t * ) 0xe000edc0 ) ) -#define portMPU_MAIR1_REG ( *( ( volatile uint32_t * ) 0xe000edc4 ) ) +#define portMPU_MAIR0_REG ( *( ( volatile uint32_t * ) 0xe000edc0 ) ) +#define portMPU_MAIR1_REG ( *( ( volatile uint32_t * ) 0xe000edc4 ) ) -#define portMPU_RBAR_ADDRESS_MASK ( 0xffffffe0 ) /* Must be 32-byte aligned. */ -#define portMPU_RLAR_ADDRESS_MASK ( 0xffffffe0 ) /* Must be 32-byte aligned. */ +#define portMPU_RBAR_ADDRESS_MASK ( 0xffffffe0 ) /* Must be 32-byte aligned. */ +#define portMPU_RLAR_ADDRESS_MASK ( 0xffffffe0 ) /* Must be 32-byte aligned. */ -#define portMPU_RBAR_ACCESS_PERMISSIONS_MASK ( 3UL << 1UL ) +#define portMPU_RBAR_ACCESS_PERMISSIONS_MASK ( 3UL << 1UL ) -#define portMPU_MAIR_ATTR0_POS ( 0UL ) -#define portMPU_MAIR_ATTR0_MASK ( 0x000000ff ) +#define portMPU_MAIR_ATTR0_POS ( 0UL ) +#define portMPU_MAIR_ATTR0_MASK ( 0x000000ff ) -#define portMPU_MAIR_ATTR1_POS ( 8UL ) -#define portMPU_MAIR_ATTR1_MASK ( 0x0000ff00 ) +#define portMPU_MAIR_ATTR1_POS ( 8UL ) +#define portMPU_MAIR_ATTR1_MASK ( 0x0000ff00 ) -#define portMPU_MAIR_ATTR2_POS ( 16UL ) -#define portMPU_MAIR_ATTR2_MASK ( 0x00ff0000 ) +#define portMPU_MAIR_ATTR2_POS ( 16UL ) +#define portMPU_MAIR_ATTR2_MASK ( 0x00ff0000 ) -#define portMPU_MAIR_ATTR3_POS ( 24UL ) -#define portMPU_MAIR_ATTR3_MASK ( 0xff000000 ) +#define portMPU_MAIR_ATTR3_POS ( 24UL ) +#define portMPU_MAIR_ATTR3_MASK ( 0xff000000 ) -#define portMPU_MAIR_ATTR4_POS ( 0UL ) -#define portMPU_MAIR_ATTR4_MASK ( 0x000000ff ) +#define portMPU_MAIR_ATTR4_POS ( 0UL ) +#define portMPU_MAIR_ATTR4_MASK ( 0x000000ff ) -#define portMPU_MAIR_ATTR5_POS ( 8UL ) -#define portMPU_MAIR_ATTR5_MASK ( 0x0000ff00 ) +#define portMPU_MAIR_ATTR5_POS ( 8UL ) +#define portMPU_MAIR_ATTR5_MASK ( 0x0000ff00 ) -#define portMPU_MAIR_ATTR6_POS ( 16UL ) -#define portMPU_MAIR_ATTR6_MASK ( 0x00ff0000 ) +#define portMPU_MAIR_ATTR6_POS ( 16UL ) +#define portMPU_MAIR_ATTR6_MASK ( 0x00ff0000 ) -#define portMPU_MAIR_ATTR7_POS ( 24UL ) -#define portMPU_MAIR_ATTR7_MASK ( 0xff000000 ) +#define portMPU_MAIR_ATTR7_POS ( 24UL ) +#define portMPU_MAIR_ATTR7_MASK ( 0xff000000 ) -#define portMPU_RLAR_ATTR_INDEX0 ( 0UL << 1UL ) -#define portMPU_RLAR_ATTR_INDEX1 ( 1UL << 1UL ) -#define portMPU_RLAR_ATTR_INDEX2 ( 2UL << 1UL ) -#define portMPU_RLAR_ATTR_INDEX3 ( 3UL << 1UL ) -#define portMPU_RLAR_ATTR_INDEX4 ( 4UL << 1UL ) -#define portMPU_RLAR_ATTR_INDEX5 ( 5UL << 1UL ) -#define portMPU_RLAR_ATTR_INDEX6 ( 6UL << 1UL ) -#define portMPU_RLAR_ATTR_INDEX7 ( 7UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX0 ( 0UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX1 ( 1UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX2 ( 2UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX3 ( 3UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX4 ( 4UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX5 ( 5UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX6 ( 6UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX7 ( 7UL << 1UL ) -#define portMPU_RLAR_REGION_ENABLE ( 1UL ) +#define portMPU_RLAR_REGION_ENABLE ( 1UL ) /* Enable privileged access to unmapped region. */ -#define portMPU_PRIV_BACKGROUND_ENABLE_BIT ( 1UL << 2UL ) +#define portMPU_PRIV_BACKGROUND_ENABLE_BIT ( 1UL << 2UL ) /* Enable MPU. */ -#define portMPU_ENABLE_BIT ( 1UL << 0UL ) +#define portMPU_ENABLE_BIT ( 1UL << 0UL ) /* Expected value of the portMPU_TYPE register. */ -#define portEXPECTED_MPU_TYPE_VALUE ( configTOTAL_MPU_REGIONS << 8UL ) +#define portEXPECTED_MPU_TYPE_VALUE ( configTOTAL_MPU_REGIONS << 8UL ) /* Extract first address of the MPU region as encoded in the * RBAR (Region Base Address Register) value. */ @@ -448,13 +472,13 @@ portDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIV #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) - /** - * @brief Sets up the task stack so that upon returning from - * SVC, the task stack is used again. - * - * @param pulSystemCallStack The current SP when the SVC was raised. - * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler. - */ +/** + * @brief Sets up the task stack so that upon returning from + * SVC, the task stack is used again. + * + * @param pulSystemCallStack The current SP when the SVC was raised. + * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler. + */ void vSystemCallExit( uint32_t * pulSystemCallStack, uint32_t ulLR ) PRIVILEGED_FUNCTION; @@ -462,11 +486,11 @@ portDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIV #if ( configENABLE_MPU == 1 ) - /** - * @brief Checks whether or not the calling task is privileged. - * - * @return pdTRUE if the calling task is privileged, pdFALSE otherwise. - */ +/** + * @brief Checks whether or not the calling task is privileged. + * + * @return pdTRUE if the calling task is privileged, pdFALSE otherwise. + */ BaseType_t xPortIsTaskPrivileged( void ) PRIVILEGED_FUNCTION; #endif /* configENABLE_MPU == 1 */ @@ -501,13 +525,13 @@ PRIVILEGED_DATA static volatile uint32_t ulCriticalNesting = 0xaaaaaaaaUL; * FreeRTOS API functions are not called from interrupts that have been assigned * a priority above configMAX_SYSCALL_INTERRUPT_PRIORITY. */ -#if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) ) +#if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) static uint8_t ucMaxSysCallPriority = 0; static uint32_t ulMaxPRIGROUPValue = 0; static const volatile uint8_t * const pcInterruptPriorityRegisters = ( const volatile uint8_t * ) portNVIC_IP_REGISTERS_OFFSET_16; -#endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) ) */ +#endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */ #if ( configUSE_TICKLESS_IDLE == 1 ) @@ -760,8 +784,15 @@ __attribute__( ( weak ) ) void vPortSetupTimerInterrupt( void ) /* PRIVILEGED_FU } #endif /* configUSE_TICKLESS_IDLE */ - /* Stop and reset the SysTick. */ - portNVIC_SYSTICK_CTRL_REG = 0UL; + /* Stop and reset SysTick. + * + * QEMU versions older than 7.0.0 contain a bug which causes an error if we + * enable SysTick without first selecting a valid clock source. We trigger + * the bug if we change clock sources from a clock with a zero clock period + * to one with a nonzero clock period and enable Systick at the same time. + * So we configure the CLKSOURCE bit here, prior to setting the ENABLE bit. + * This workaround avoids the bug in QEMU versions older than 7.0.0. */ + portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT_CONFIG; portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL; /* Configure SysTick to interrupt at the requested rate. */ @@ -819,6 +850,7 @@ static void prvTaskExitError( void ) static void prvSetupMPU( void ) /* PRIVILEGED_FUNCTION */ { #if defined( __ARMCC_VERSION ) + /* Declaration when these variable are defined in code instead of being * exported from linker scripts. */ extern uint32_t * __privileged_functions_start__; @@ -972,13 +1004,19 @@ void SysTick_Handler( void ) /* PRIVILEGED_FUNCTION */ uint32_t ulPreviousMask; ulPreviousMask = portSET_INTERRUPT_MASK_FROM_ISR(); + traceISR_ENTER(); { /* Increment the RTOS tick. */ if( xTaskIncrementTick() != pdFALSE ) { + traceISR_EXIT_TO_SCHEDULER(); /* Pend a context switch. */ portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; } + else + { + traceISR_EXIT(); + } } portCLEAR_INTERRUPT_MASK_FROM_ISR( ulPreviousMask ); } @@ -988,6 +1026,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO { #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) ) #if defined( __ARMCC_VERSION ) + /* Declaration when these variable are defined in code instead of being * exported from linker scripts. */ extern uint32_t * __syscalls_flash_start__; @@ -1083,18 +1122,24 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO vRestoreContextOfFirstTask(); break; - #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) ) - case portSVC_RAISE_PRIVILEGE: + #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) ) + case portSVC_RAISE_PRIVILEGE: - /* Only raise the privilege, if the svc was raised from any of - * the system calls. */ - if( ( ulPC >= ( uint32_t ) __syscalls_flash_start__ ) && - ( ulPC <= ( uint32_t ) __syscalls_flash_end__ ) ) - { - vRaisePrivilege(); - } - break; - #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) */ + /* Only raise the privilege, if the svc was raised from any of + * the system calls. */ + if( ( ulPC >= ( uint32_t ) __syscalls_flash_start__ ) && + ( ulPC <= ( uint32_t ) __syscalls_flash_end__ ) ) + { + vRaisePrivilege(); + } + break; + #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) */ + + #if ( configENABLE_MPU == 1 ) + case portSVC_YIELD: + vPortYield(); + break; + #endif /* configENABLE_MPU == 1 */ default: /* Incorrect SVC call. */ @@ -1154,12 +1199,11 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO { /* Extended frame i.e. FPU in use. */ ulStackFrameSize = 26; - __asm volatile - ( + __asm volatile ( " vpush {s0} \n" /* Trigger lazy stacking. */ " vpop {s0} \n" /* Nullify the affect of the above instruction. */ ::: "memory" - ); + ); } else { @@ -1171,7 +1215,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO { ulStackFrameSize = 8; } - #endif /* if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */ + #endif /* configENABLE_FPU || configENABLE_MVE */ /* Make space on the system call stack for the stack frame. */ pulSystemCallStack = pulSystemCallStack - ulStackFrameSize; @@ -1187,18 +1231,24 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO * point (i.e. the caller of the MPU_). We need to restore it * when we exit from the system call. */ pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry = pulTaskStack[ portOFFSET_TO_LR ]; - /* Store the value of the PSPLIM register before the SVC was raised. * We need to restore it when we exit from the system call. */ - __asm volatile ( "mrs %0, psplim" : "=r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) ); + #if ( portUSE_PSPLIM_REGISTER == 1 ) + { + __asm volatile ( "mrs %0, psplim" : "=r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) ); + } + #endif /* Use the pulSystemCallStack in thread mode. */ __asm volatile ( "msr psp, %0" : : "r" ( pulSystemCallStack ) ); - __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) ); + #if ( portUSE_PSPLIM_REGISTER == 1 ) + { + __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) ); + } + #endif /* Start executing the system call upon returning from this handler. */ pulSystemCallStack[ portOFFSET_TO_PC ] = uxSystemCallImplementations[ ucSystemCallNumber ]; - /* Raise a request to exit from the system call upon finishing the * system call. */ pulSystemCallStack[ portOFFSET_TO_LR ] = ( uint32_t ) vRequestSystemCallExit; @@ -1224,14 +1274,13 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO pulSystemCallStack[ portOFFSET_TO_PSR ] &= ( ~portPSR_STACK_PADDING_MASK ); /* Raise the privilege for the duration of the system call. */ - __asm volatile - ( + __asm volatile ( " mrs r0, control \n" /* Obtain current control value. */ " movs r1, #1 \n" /* r1 = 1. */ " bics r0, r1 \n" /* Clear nPRIV bit. */ " msr control, r0 \n" /* Write back new control value. */ ::: "r0", "r1", "memory" - ); + ); } } @@ -1293,12 +1342,11 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO { /* Extended frame i.e. FPU in use. */ ulStackFrameSize = 26; - __asm volatile - ( + __asm volatile ( " vpush {s0} \n" /* Trigger lazy stacking. */ " vpop {s0} \n" /* Nullify the affect of the above instruction. */ ::: "memory" - ); + ); } else { @@ -1310,7 +1358,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO { ulStackFrameSize = 8; } - #endif /* if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */ + #endif /* configENABLE_FPU || configENABLE_MVE */ /* Make space on the task stack for the stack frame. */ pulTaskStack = pulTaskStack - ulStackFrameSize; @@ -1332,7 +1380,11 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO /* Restore the PSPLIM register to what it was at the time of * system call entry. */ - __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) ); + #if ( portUSE_PSPLIM_REGISTER == 1 ) + { + __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) ); + } + #endif /* If the hardware used padding to force the stack pointer * to be double word aligned, set the stacked xPSR bit[9], @@ -1350,14 +1402,13 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO pxMpuSettings->xSystemCallStackInfo.pulTaskStack = NULL; /* Drop the privilege before returning to the thread mode. */ - __asm volatile - ( + __asm volatile ( " mrs r0, control \n" /* Obtain current control value. */ " movs r1, #1 \n" /* r1 = 1. */ " orrs r0, r1 \n" /* Set nPRIV bit. */ " msr control, r0 \n" /* Write back new control value. */ ::: "r0", "r1", "memory" - ); + ); } } @@ -1410,21 +1461,21 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO xMPUSettings->ulContext[ ulIndex ] = 0x11111111; /* r11. */ ulIndex++; - xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pvParameters; /* r0. */ + xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pvParameters; /* r0. */ ulIndex++; - xMPUSettings->ulContext[ ulIndex ] = 0x01010101; /* r1. */ + xMPUSettings->ulContext[ ulIndex ] = 0x01010101; /* r1. */ ulIndex++; - xMPUSettings->ulContext[ ulIndex ] = 0x02020202; /* r2. */ + xMPUSettings->ulContext[ ulIndex ] = 0x02020202; /* r2. */ ulIndex++; - xMPUSettings->ulContext[ ulIndex ] = 0x03030303; /* r3. */ + xMPUSettings->ulContext[ ulIndex ] = 0x03030303; /* r3. */ ulIndex++; - xMPUSettings->ulContext[ ulIndex ] = 0x12121212; /* r12. */ + xMPUSettings->ulContext[ ulIndex ] = 0x12121212; /* r12. */ ulIndex++; xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portTASK_RETURN_ADDRESS; /* LR. */ ulIndex++; - xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxCode; /* PC. */ + xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxCode; /* PC. */ ulIndex++; - xMPUSettings->ulContext[ ulIndex ] = portINITIAL_XPSR; /* xPSR. */ + xMPUSettings->ulContext[ ulIndex ] = portINITIAL_XPSR; /* xPSR. */ ulIndex++; #if ( configENABLE_TRUSTZONE == 1 ) @@ -1435,8 +1486,9 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO #endif /* configENABLE_TRUSTZONE */ xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) ( pxTopOfStack - 8 ); /* PSP with the hardware saved stack. */ ulIndex++; - xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxEndOfStack; /* PSPLIM. */ + xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxEndOfStack; /* PSPLIM. */ ulIndex++; + if( xRunPrivileged == pdTRUE ) { xMPUSettings->ulTaskFlags |= portTASK_IS_PRIVILEGED_FLAG; @@ -1449,6 +1501,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portINITIAL_CONTROL_UNPRIVILEGED; /* CONTROL. */ ulIndex++; } + xMPUSettings->ulContext[ ulIndex ] = portINITIAL_EXC_RETURN; /* LR (EXC_RETURN). */ ulIndex++; @@ -1483,7 +1536,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO * interrupt. */ #if ( portPRELOAD_REGISTERS == 0 ) { - pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */ + pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */ *pxTopOfStack = portINITIAL_XPSR; /* xPSR. */ pxTopOfStack--; *pxTopOfStack = ( StackType_t ) pxCode; /* PC. */ @@ -1505,7 +1558,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO } #else /* portPRELOAD_REGISTERS */ { - pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */ + pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */ *pxTopOfStack = portINITIAL_XPSR; /* xPSR. */ pxTopOfStack--; *pxTopOfStack = ( StackType_t ) pxCode; /* PC. */ @@ -1540,7 +1593,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO pxTopOfStack--; *pxTopOfStack = portINITIAL_EXC_RETURN; /* EXC_RETURN. */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */ + *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */ #if ( configENABLE_TRUSTZONE == 1 ) { @@ -1559,22 +1612,52 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */ { - #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) ) + /* An application can install FreeRTOS interrupt handlers in one of the + * folllowing ways: + * 1. Direct Routing - Install the functions SVC_Handler and PendSV_Handler + * for SVCall and PendSV interrupts respectively. + * 2. Indirect Routing - Install separate handlers for SVCall and PendSV + * interrupts and route program control from those handlers to + * SVC_Handler and PendSV_Handler functions. + * + * Applications that use Indirect Routing must set + * configCHECK_HANDLER_INSTALLATION to 0 in their FreeRTOSConfig.h. Direct + * routing, which is validated here when configCHECK_HANDLER_INSTALLATION + * is 1, should be preferred when possible. */ + #if ( configCHECK_HANDLER_INSTALLATION == 1 ) + { + const portISR_t * const pxVectorTable = portSCB_VTOR_REG; + + /* Validate that the application has correctly installed the FreeRTOS + * handlers for SVCall and PendSV interrupts. We do not check the + * installation of the SysTick handler because the application may + * choose to drive the RTOS tick using a timer other than the SysTick + * timer by overriding the weak function vPortSetupTimerInterrupt(). + * + * Assertion failures here indicate incorrect installation of the + * FreeRTOS handlers. For help installing the FreeRTOS handlers, see + * https://www.FreeRTOS.org/FAQHelp.html. + * + * Systems with a configurable address for the interrupt vector table + * can also encounter assertion failures or even system faults here if + * VTOR is not set correctly to point to the application's vector table. */ + configASSERT( pxVectorTable[ portVECTOR_INDEX_SVC ] == SVC_Handler ); + configASSERT( pxVectorTable[ portVECTOR_INDEX_PENDSV ] == PendSV_Handler ); + } + #endif /* configCHECK_HANDLER_INSTALLATION */ + + #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) { - volatile uint32_t ulOriginalPriority; volatile uint32_t ulImplementedPrioBits = 0; volatile uint8_t ucMaxPriorityValue; /* Determine the maximum priority from which ISR safe FreeRTOS API - * functions can be called. ISR safe functions are those that end in - * "FromISR". FreeRTOS maintains separate thread and ISR API functions to + * functions can be called. ISR safe functions are those that end in + * "FromISR". FreeRTOS maintains separate thread and ISR API functions to * ensure interrupt entry is as fast and simple as possible. * - * Save the interrupt priority value that is about to be clobbered. */ - ulOriginalPriority = portNVIC_SHPR2_REG; - - /* Determine the number of priority bits available. First write to all - * possible bits. */ + * First, determine the number of priority bits available. Write to all + * possible bits in the priority setting for SVCall. */ portNVIC_SHPR2_REG = 0xFF000000; /* Read the value back to see how many bits stuck. */ @@ -1593,11 +1676,10 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */ /* Check that the bits not implemented in hardware are zero in * configMAX_SYSCALL_INTERRUPT_PRIORITY. */ - configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( ~ucMaxPriorityValue ) ) == 0U ); + configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( uint8_t ) ( ~( uint32_t ) ucMaxPriorityValue ) ) == 0U ); /* Calculate the maximum acceptable priority group value for the number * of bits read back. */ - while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE ) { ulImplementedPrioBits++; @@ -1635,16 +1717,14 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */ * register. */ ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT; ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK; - - /* Restore the clobbered interrupt priority register to its original - * value. */ - portNVIC_SHPR2_REG = ulOriginalPriority; } - #endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) ) */ + #endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */ - /* Make PendSV, CallSV and SysTick the same priority as the kernel. */ + /* Make PendSV and SysTick the lowest priority interrupts, and make SVCall + * the highest priority. */ portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI; portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI; + portNVIC_SHPR2_REG = 0; #if ( configENABLE_MPU == 1 ) { @@ -1701,6 +1781,7 @@ void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */ int32_t lIndex = 0; #if defined( __ARMCC_VERSION ) + /* Declaration when these variable are defined in code instead of being * exported from linker scripts. */ extern uint32_t * __privileged_sram_start__; @@ -1886,7 +1967,7 @@ BaseType_t xPortIsInsideInterrupt( void ) } /*-----------------------------------------------------------*/ -#if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) ) +#if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) void vPortValidateInterruptPriority( void ) { @@ -1944,7 +2025,7 @@ BaseType_t xPortIsInsideInterrupt( void ) configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue ); } -#endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) ) */ +#endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */ /*-----------------------------------------------------------*/ #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) diff --git a/Source/portable/IAR/ARM_CM33_NTZ/non_secure/portasm.h b/Source/portable/IAR/ARM_CM33_NTZ/non_secure/portasm.h index f64ceb525..c6d2ebd58 100644 --- a/Source/portable/IAR/ARM_CM33_NTZ/non_secure/portasm.h +++ b/Source/portable/IAR/ARM_CM33_NTZ/non_secure/portasm.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/Source/portable/IAR/ARM_CM33_NTZ/non_secure/portasm.s b/Source/portable/IAR/ARM_CM33_NTZ/non_secure/portasm.s index 00ee5a5cb..cb3ad91f9 100644 --- a/Source/portable/IAR/ARM_CM33_NTZ/non_secure/portasm.s +++ b/Source/portable/IAR/ARM_CM33_NTZ/non_secure/portasm.s @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/Source/portable/IAR/ARM_CM33_NTZ/non_secure/portmacro.h b/Source/portable/IAR/ARM_CM33_NTZ/non_secure/portmacro.h index 84e86d9f9..5f81b5fe8 100644 --- a/Source/portable/IAR/ARM_CM33_NTZ/non_secure/portmacro.h +++ b/Source/portable/IAR/ARM_CM33_NTZ/non_secure/portmacro.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -48,16 +48,16 @@ /** * Architecture specifics. */ -#define portARCH_NAME "Cortex-M33" -#define portHAS_BASEPRI 1 -#define portDONT_DISCARD __root +#define portARCH_NAME "Cortex-M33" +#define portHAS_ARMV8M_MAIN_EXTENSION 1 +#define portDONT_DISCARD __root /*-----------------------------------------------------------*/ /* ARMv8-M common port configurations. */ #include "portmacrocommon.h" /*-----------------------------------------------------------*/ -#if( configTOTAL_MPU_REGIONS == 16 ) +#if ( configTOTAL_MPU_REGIONS == 16 ) #error 16 MPU regions are not yet supported for this port. #endif /*-----------------------------------------------------------*/ @@ -65,8 +65,8 @@ /** * @brief Critical section management. */ -#define portDISABLE_INTERRUPTS() ulSetInterruptMask() -#define portENABLE_INTERRUPTS() vClearInterruptMask( 0 ) +#define portDISABLE_INTERRUPTS() ulSetInterruptMask() +#define portENABLE_INTERRUPTS() vClearInterruptMask( 0 ) /*-----------------------------------------------------------*/ /* Suppress warnings that are generated by the IAR tools, but cannot be fixed in diff --git a/Source/portable/IAR/ARM_CM33_NTZ/non_secure/portmacrocommon.h b/Source/portable/IAR/ARM_CM33_NTZ/non_secure/portmacrocommon.h index 6f666da22..33f21d85b 100644 --- a/Source/portable/IAR/ARM_CM33_NTZ/non_secure/portmacrocommon.h +++ b/Source/portable/IAR/ARM_CM33_NTZ/non_secure/portmacrocommon.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -117,7 +117,7 @@ extern uint32_t ulSetInterruptMask( void ) /* __attribute__(( naked )) PRIVILEGE extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */; #if ( configENABLE_TRUSTZONE == 1 ) - extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize ); /* __attribute__ (( naked )) */ + extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize ); /* __attribute__ (( naked )) */ extern void vPortFreeSecureContext( uint32_t * pulTCB ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */; #endif /* configENABLE_TRUSTZONE */ @@ -188,13 +188,13 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P #if ( configENABLE_MPU == 1 ) - /** - * @brief Settings to define an MPU region. - */ +/** + * @brief Settings to define an MPU region. + */ typedef struct MPURegionSettings { - uint32_t ulRBAR; /**< RBAR for the region. */ - uint32_t ulRLAR; /**< RLAR for the region. */ + uint32_t ulRBAR; /**< RBAR for the region. */ + uint32_t ulRLAR; /**< RLAR for the region. */ } MPURegionSettings_t; #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) @@ -203,9 +203,9 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P #error configSYSTEM_CALL_STACK_SIZE must be defined to the desired size of the system call stack in words for using MPU wrappers v2. #endif - /** - * @brief System call stack. - */ +/** + * @brief System call stack. + */ typedef struct SYSTEM_CALL_STACK_INFO { uint32_t ulSystemCallStackBuffer[ configSYSTEM_CALL_STACK_SIZE ]; @@ -218,74 +218,74 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P #endif /* configUSE_MPU_WRAPPERS_V1 == 0 */ - /** - * @brief MPU settings as stored in the TCB. - */ +/** + * @brief MPU settings as stored in the TCB. + */ #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) - #if( configENABLE_TRUSTZONE == 1 ) + #if ( configENABLE_TRUSTZONE == 1 ) - /* - * +-----------+---------------+----------+-----------------+------------------------------+-----+ - * | s16-s31 | s0-s15, FPSCR | r4-r11 | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, | | - * | | | | PC, xPSR | CONTROL, EXC_RETURN | | - * +-----------+---------------+----------+-----------------+------------------------------+-----+ - * - * <-----------><--------------><---------><----------------><-----------------------------><----> - * 16 16 8 8 5 1 - */ - #define MAX_CONTEXT_SIZE 54 +/* + * +-----------+---------------+----------+-----------------+------------------------------+-----+ + * | s16-s31 | s0-s15, FPSCR | r4-r11 | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, | | + * | | | | PC, xPSR | CONTROL, EXC_RETURN | | + * +-----------+---------------+----------+-----------------+------------------------------+-----+ + * + * <-----------><--------------><---------><----------------><-----------------------------><----> + * 16 16 8 8 5 1 + */ + #define MAX_CONTEXT_SIZE 54 #else /* #if( configENABLE_TRUSTZONE == 1 ) */ - /* - * +-----------+---------------+----------+-----------------+----------------------+-----+ - * | s16-s31 | s0-s15, FPSCR | r4-r11 | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL | | - * | | | | PC, xPSR | EXC_RETURN | | - * +-----------+---------------+----------+-----------------+----------------------+-----+ - * - * <-----------><--------------><---------><----------------><---------------------><----> - * 16 16 8 8 4 1 - */ - #define MAX_CONTEXT_SIZE 53 +/* + * +-----------+---------------+----------+-----------------+----------------------+-----+ + * | s16-s31 | s0-s15, FPSCR | r4-r11 | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL | | + * | | | | PC, xPSR | EXC_RETURN | | + * +-----------+---------------+----------+-----------------+----------------------+-----+ + * + * <-----------><--------------><---------><----------------><---------------------><----> + * 16 16 8 8 4 1 + */ + #define MAX_CONTEXT_SIZE 53 #endif /* #if( configENABLE_TRUSTZONE == 1 ) */ #else /* #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */ - #if( configENABLE_TRUSTZONE == 1 ) + #if ( configENABLE_TRUSTZONE == 1 ) - /* - * +----------+-----------------+------------------------------+-----+ - * | r4-r11 | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, | | - * | | PC, xPSR | CONTROL, EXC_RETURN | | - * +----------+-----------------+------------------------------+-----+ - * - * <---------><----------------><------------------------------><----> - * 8 8 5 1 - */ - #define MAX_CONTEXT_SIZE 22 +/* + * +----------+-----------------+------------------------------+-----+ + * | r4-r11 | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, | | + * | | PC, xPSR | CONTROL, EXC_RETURN | | + * +----------+-----------------+------------------------------+-----+ + * + * <---------><----------------><------------------------------><----> + * 8 8 5 1 + */ + #define MAX_CONTEXT_SIZE 22 #else /* #if( configENABLE_TRUSTZONE == 1 ) */ - /* - * +----------+-----------------+----------------------+-----+ - * | r4-r11 | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL | | - * | | PC, xPSR | EXC_RETURN | | - * +----------+-----------------+----------------------+-----+ - * - * <---------><----------------><----------------------><----> - * 8 8 4 1 - */ - #define MAX_CONTEXT_SIZE 21 +/* + * +----------+-----------------+----------------------+-----+ + * | r4-r11 | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL | | + * | | PC, xPSR | EXC_RETURN | | + * +----------+-----------------+----------------------+-----+ + * + * <---------><----------------><----------------------><----> + * 8 8 4 1 + */ + #define MAX_CONTEXT_SIZE 21 #endif /* #if( configENABLE_TRUSTZONE == 1 ) */ #endif /* #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */ - /* Flags used for xMPU_SETTINGS.ulTaskFlags member. */ - #define portSTACK_FRAME_HAS_PADDING_FLAG ( 1UL << 0UL ) - #define portTASK_IS_PRIVILEGED_FLAG ( 1UL << 1UL ) +/* Flags used for xMPU_SETTINGS.ulTaskFlags member. */ + #define portSTACK_FRAME_HAS_PADDING_FLAG ( 1UL << 0UL ) + #define portTASK_IS_PRIVILEGED_FLAG ( 1UL << 1UL ) /* Size of an Access Control List (ACL) entry in bits. */ #define portACL_ENTRY_SIZE_BITS ( 32U ) @@ -313,7 +313,7 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P * system calls. */ #ifdef configASSERT - #if ( portHAS_BASEPRI == 1 ) + #if ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) void vPortValidateInterruptPriority( void ); #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() vPortValidateInterruptPriority() #endif @@ -333,12 +333,29 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P /** * @brief Scheduler utilities. */ -#define portYIELD() vPortYield() +#if ( configENABLE_MPU == 1 ) + #define portYIELD() __asm volatile ( "svc %0" ::"i" ( portSVC_YIELD ) : "memory" ) + #define portYIELD_WITHIN_API() vPortYield() +#else + #define portYIELD() vPortYield() + #define portYIELD_WITHIN_API() vPortYield() +#endif + #define portNVIC_INT_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed04 ) ) #define portNVIC_PENDSVSET_BIT ( 1UL << 28UL ) -#define portEND_SWITCHING_ISR( xSwitchRequired ) \ - do { if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; } \ - while( 0 ) +#define portEND_SWITCHING_ISR( xSwitchRequired ) \ + do \ + { \ + if( xSwitchRequired ) \ + { \ + traceISR_EXIT_TO_SCHEDULER(); \ + portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; \ + } \ + else \ + { \ + traceISR_EXIT(); \ + } \ + } while( 0 ) #define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x ) /*-----------------------------------------------------------*/ @@ -424,12 +441,12 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P extern BaseType_t xPortIsTaskPrivileged( void ); - /** - * @brief Checks whether or not the calling task is privileged. - * - * @return pdTRUE if the calling task is privileged, pdFALSE otherwise. - */ - #define portIS_TASK_PRIVILEGED() xPortIsTaskPrivileged() +/** + * @brief Checks whether or not the calling task is privileged. + * + * @return pdTRUE if the calling task is privileged, pdFALSE otherwise. + */ + #define portIS_TASK_PRIVILEGED() xPortIsTaskPrivileged() #endif /* configENABLE_MPU == 1 */ /*-----------------------------------------------------------*/ @@ -440,6 +457,56 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P #define portMEMORY_BARRIER() __asm volatile ( "" ::: "memory" ) /*-----------------------------------------------------------*/ +/* Select correct value of configUSE_PORT_OPTIMISED_TASK_SELECTION + * based on whether or not Mainline extension is implemented. */ +#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION + #if ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) + #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1 + #else + #define configUSE_PORT_OPTIMISED_TASK_SELECTION 0 + #endif +#endif /* #ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION */ + +/** + * @brief Port-optimised task selection. + */ +#if ( configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 ) + +/** + * @brief Count the number of leading zeros in a 32-bit value. + */ + static portFORCE_INLINE uint32_t ulPortCountLeadingZeros( uint32_t ulBitmap ) + { + uint32_t ulReturn; + + __asm volatile ( "clz %0, %1" : "=r" ( ulReturn ) : "r" ( ulBitmap ) : "memory" ); + + return ulReturn; + } + +/* Check the configuration. */ + #if ( configMAX_PRIORITIES > 32 ) + #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 different priorities as tasks that share a priority will time slice. + #endif + + #if ( portHAS_ARMV8M_MAIN_EXTENSION == 0 ) + #error ARMv8-M baseline implementations (such as Cortex-M23) do not support port-optimised task selection. Please set configUSE_PORT_OPTIMISED_TASK_SELECTION to 0 or leave it undefined. + #endif + +/** + * @brief Store/clear the ready priorities in a bit map. + */ + #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) ) + #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) ) + +/** + * @brief Get the priority of the highest-priority task that is ready to execute. + */ + #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - ulPortCountLeadingZeros( ( uxReadyPriorities ) ) ) + +#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */ +/*-----------------------------------------------------------*/ + /* *INDENT-OFF* */ #ifdef __cplusplus } diff --git a/Source/portable/IAR/ARM_CM35P/non_secure/mpu_wrappers_v2_asm.S b/Source/portable/IAR/ARM_CM35P/non_secure/mpu_wrappers_v2_asm.S index ef180bd91..b4f1fbc3b 100644 --- a/Source/portable/IAR/ARM_CM35P/non_secure/mpu_wrappers_v2_asm.S +++ b/Source/portable/IAR/ARM_CM35P/non_secure/mpu_wrappers_v2_asm.S @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -196,20 +196,6 @@ MPU_uxTaskGetNumberOfTasks: svc #SYSTEM_CALL_uxTaskGetNumberOfTasks /*-----------------------------------------------------------*/ - PUBLIC MPU_pcTaskGetName -MPU_pcTaskGetName: - push {r0} - mrs r0, control - tst r0, #1 - bne MPU_pcTaskGetName_Unpriv - MPU_pcTaskGetName_Priv: - pop {r0} - b MPU_pcTaskGetNameImpl - MPU_pcTaskGetName_Unpriv: - pop {r0} - svc #SYSTEM_CALL_pcTaskGetName -/*-----------------------------------------------------------*/ - PUBLIC MPU_ulTaskGetRunTimeCounter MPU_ulTaskGetRunTimeCounter: push {r0} @@ -742,24 +728,18 @@ MPU_xTimerGetTimerDaemonTaskHandle: svc #SYSTEM_CALL_xTimerGetTimerDaemonTaskHandle /*-----------------------------------------------------------*/ - PUBLIC MPU_xTimerGenericCommandEntry -MPU_xTimerGenericCommandEntry: + PUBLIC MPU_xTimerGenericCommandFromTaskEntry +MPU_xTimerGenericCommandFromTaskEntry: push {r0} - /* This function can be called from ISR also and therefore, we need a check - * to take privileged path, if called from ISR. */ - mrs r0, ipsr - cmp r0, #0 - bne MPU_xTimerGenericCommand_Priv mrs r0, control tst r0, #1 - beq MPU_xTimerGenericCommand_Priv - MPU_xTimerGenericCommand_Unpriv: + bne MPU_xTimerGenericCommandFromTask_Unpriv + MPU_xTimerGenericCommandFromTask_Priv: pop {r0} - svc #SYSTEM_CALL_xTimerGenericCommand - MPU_xTimerGenericCommand_Priv: + b MPU_xTimerGenericCommandFromTaskImpl + MPU_xTimerGenericCommandFromTask_Unpriv: pop {r0} - b MPU_xTimerGenericCommandPrivImpl - + svc #SYSTEM_CALL_xTimerGenericCommandFromTask /*-----------------------------------------------------------*/ PUBLIC MPU_pcTimerGetName @@ -1089,10 +1069,6 @@ MPU_xTaskGetTickCountImpl: MPU_uxTaskGetNumberOfTasksImpl: b MPU_uxTaskGetNumberOfTasksImpl - PUBWEAK MPU_pcTaskGetNameImpl -MPU_pcTaskGetNameImpl: - b MPU_pcTaskGetNameImpl - PUBWEAK MPU_ulTaskGetRunTimeCounterImpl MPU_ulTaskGetRunTimeCounterImpl: b MPU_ulTaskGetRunTimeCounterImpl @@ -1245,9 +1221,9 @@ MPU_xTimerIsTimerActiveImpl: MPU_xTimerGetTimerDaemonTaskHandleImpl: b MPU_xTimerGetTimerDaemonTaskHandleImpl - PUBWEAK MPU_xTimerGenericCommandPrivImpl -MPU_xTimerGenericCommandPrivImpl: - b MPU_xTimerGenericCommandPrivImpl + PUBWEAK MPU_xTimerGenericCommandFromTaskImpl +MPU_xTimerGenericCommandFromTaskImpl: + b MPU_xTimerGenericCommandFromTaskImpl PUBWEAK MPU_pcTimerGetNameImpl MPU_pcTimerGetNameImpl: diff --git a/Source/portable/IAR/ARM_CM35P/non_secure/port.c b/Source/portable/IAR/ARM_CM35P/non_secure/port.c index 9712ac353..230fe5fc2 100644 --- a/Source/portable/IAR/ARM_CM35P/non_secure/port.c +++ b/Source/portable/IAR/ARM_CM35P/non_secure/port.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -68,6 +68,22 @@ #if ( ( configRUN_FREERTOS_SECURE_ONLY == 1 ) && ( configENABLE_TRUSTZONE == 1 ) ) #error TrustZone needs to be disabled in order to run FreeRTOS on the Secure Side. #endif + +/** + * Cortex-M23 does not have non-secure PSPLIM. We should use PSPLIM on Cortex-M23 + * only when FreeRTOS runs on secure side. + */ +#if ( ( portHAS_ARMV8M_MAIN_EXTENSION == 0 ) && ( configRUN_FREERTOS_SECURE_ONLY == 0 ) ) + #define portUSE_PSPLIM_REGISTER 0 +#else + #define portUSE_PSPLIM_REGISTER 1 +#endif +/*-----------------------------------------------------------*/ + +/** + * @brief Prototype of all Interrupt Service Routines (ISRs). + */ +typedef void ( * portISR_t )( void ); /*-----------------------------------------------------------*/ /** @@ -91,10 +107,18 @@ /** * @brief Constants required to manipulate the SCB. */ -#define portSCB_SYS_HANDLER_CTRL_STATE_REG ( *( volatile uint32_t * ) 0xe000ed24 ) +#define portSCB_VTOR_REG ( *( ( portISR_t ** ) 0xe000ed08 ) ) +#define portSCB_SYS_HANDLER_CTRL_STATE_REG ( *( ( volatile uint32_t * ) 0xe000ed24 ) ) #define portSCB_MEM_FAULT_ENABLE_BIT ( 1UL << 16UL ) /*-----------------------------------------------------------*/ +/** + * @brief Constants used to check the installation of the FreeRTOS interrupt handlers. + */ +#define portVECTOR_INDEX_SVC ( 11 ) +#define portVECTOR_INDEX_PENDSV ( 14 ) +/*-----------------------------------------------------------*/ + /** * @brief Constants required to check the validity of an interrupt priority. */ @@ -111,8 +135,8 @@ /** * @brief Constants used during system call enter and exit. */ -#define portPSR_STACK_PADDING_MASK ( 1UL << 9UL ) -#define portEXC_RETURN_STACK_FRAME_TYPE_MASK ( 1UL << 4UL ) +#define portPSR_STACK_PADDING_MASK ( 1UL << 9UL ) +#define portEXC_RETURN_STACK_FRAME_TYPE_MASK ( 1UL << 4UL ) /*-----------------------------------------------------------*/ /** @@ -134,81 +158,81 @@ /** * @brief Offsets in the stack to the parameters when inside the SVC handler. */ -#define portOFFSET_TO_LR ( 5 ) -#define portOFFSET_TO_PC ( 6 ) -#define portOFFSET_TO_PSR ( 7 ) +#define portOFFSET_TO_LR ( 5 ) +#define portOFFSET_TO_PC ( 6 ) +#define portOFFSET_TO_PSR ( 7 ) /*-----------------------------------------------------------*/ /** * @brief Constants required to manipulate the MPU. */ -#define portMPU_TYPE_REG ( *( ( volatile uint32_t * ) 0xe000ed90 ) ) -#define portMPU_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed94 ) ) -#define portMPU_RNR_REG ( *( ( volatile uint32_t * ) 0xe000ed98 ) ) +#define portMPU_TYPE_REG ( *( ( volatile uint32_t * ) 0xe000ed90 ) ) +#define portMPU_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed94 ) ) +#define portMPU_RNR_REG ( *( ( volatile uint32_t * ) 0xe000ed98 ) ) -#define portMPU_RBAR_REG ( *( ( volatile uint32_t * ) 0xe000ed9c ) ) -#define portMPU_RLAR_REG ( *( ( volatile uint32_t * ) 0xe000eda0 ) ) +#define portMPU_RBAR_REG ( *( ( volatile uint32_t * ) 0xe000ed9c ) ) +#define portMPU_RLAR_REG ( *( ( volatile uint32_t * ) 0xe000eda0 ) ) -#define portMPU_RBAR_A1_REG ( *( ( volatile uint32_t * ) 0xe000eda4 ) ) -#define portMPU_RLAR_A1_REG ( *( ( volatile uint32_t * ) 0xe000eda8 ) ) +#define portMPU_RBAR_A1_REG ( *( ( volatile uint32_t * ) 0xe000eda4 ) ) +#define portMPU_RLAR_A1_REG ( *( ( volatile uint32_t * ) 0xe000eda8 ) ) -#define portMPU_RBAR_A2_REG ( *( ( volatile uint32_t * ) 0xe000edac ) ) -#define portMPU_RLAR_A2_REG ( *( ( volatile uint32_t * ) 0xe000edb0 ) ) +#define portMPU_RBAR_A2_REG ( *( ( volatile uint32_t * ) 0xe000edac ) ) +#define portMPU_RLAR_A2_REG ( *( ( volatile uint32_t * ) 0xe000edb0 ) ) -#define portMPU_RBAR_A3_REG ( *( ( volatile uint32_t * ) 0xe000edb4 ) ) -#define portMPU_RLAR_A3_REG ( *( ( volatile uint32_t * ) 0xe000edb8 ) ) +#define portMPU_RBAR_A3_REG ( *( ( volatile uint32_t * ) 0xe000edb4 ) ) +#define portMPU_RLAR_A3_REG ( *( ( volatile uint32_t * ) 0xe000edb8 ) ) -#define portMPU_MAIR0_REG ( *( ( volatile uint32_t * ) 0xe000edc0 ) ) -#define portMPU_MAIR1_REG ( *( ( volatile uint32_t * ) 0xe000edc4 ) ) +#define portMPU_MAIR0_REG ( *( ( volatile uint32_t * ) 0xe000edc0 ) ) +#define portMPU_MAIR1_REG ( *( ( volatile uint32_t * ) 0xe000edc4 ) ) -#define portMPU_RBAR_ADDRESS_MASK ( 0xffffffe0 ) /* Must be 32-byte aligned. */ -#define portMPU_RLAR_ADDRESS_MASK ( 0xffffffe0 ) /* Must be 32-byte aligned. */ +#define portMPU_RBAR_ADDRESS_MASK ( 0xffffffe0 ) /* Must be 32-byte aligned. */ +#define portMPU_RLAR_ADDRESS_MASK ( 0xffffffe0 ) /* Must be 32-byte aligned. */ -#define portMPU_RBAR_ACCESS_PERMISSIONS_MASK ( 3UL << 1UL ) +#define portMPU_RBAR_ACCESS_PERMISSIONS_MASK ( 3UL << 1UL ) -#define portMPU_MAIR_ATTR0_POS ( 0UL ) -#define portMPU_MAIR_ATTR0_MASK ( 0x000000ff ) +#define portMPU_MAIR_ATTR0_POS ( 0UL ) +#define portMPU_MAIR_ATTR0_MASK ( 0x000000ff ) -#define portMPU_MAIR_ATTR1_POS ( 8UL ) -#define portMPU_MAIR_ATTR1_MASK ( 0x0000ff00 ) +#define portMPU_MAIR_ATTR1_POS ( 8UL ) +#define portMPU_MAIR_ATTR1_MASK ( 0x0000ff00 ) -#define portMPU_MAIR_ATTR2_POS ( 16UL ) -#define portMPU_MAIR_ATTR2_MASK ( 0x00ff0000 ) +#define portMPU_MAIR_ATTR2_POS ( 16UL ) +#define portMPU_MAIR_ATTR2_MASK ( 0x00ff0000 ) -#define portMPU_MAIR_ATTR3_POS ( 24UL ) -#define portMPU_MAIR_ATTR3_MASK ( 0xff000000 ) +#define portMPU_MAIR_ATTR3_POS ( 24UL ) +#define portMPU_MAIR_ATTR3_MASK ( 0xff000000 ) -#define portMPU_MAIR_ATTR4_POS ( 0UL ) -#define portMPU_MAIR_ATTR4_MASK ( 0x000000ff ) +#define portMPU_MAIR_ATTR4_POS ( 0UL ) +#define portMPU_MAIR_ATTR4_MASK ( 0x000000ff ) -#define portMPU_MAIR_ATTR5_POS ( 8UL ) -#define portMPU_MAIR_ATTR5_MASK ( 0x0000ff00 ) +#define portMPU_MAIR_ATTR5_POS ( 8UL ) +#define portMPU_MAIR_ATTR5_MASK ( 0x0000ff00 ) -#define portMPU_MAIR_ATTR6_POS ( 16UL ) -#define portMPU_MAIR_ATTR6_MASK ( 0x00ff0000 ) +#define portMPU_MAIR_ATTR6_POS ( 16UL ) +#define portMPU_MAIR_ATTR6_MASK ( 0x00ff0000 ) -#define portMPU_MAIR_ATTR7_POS ( 24UL ) -#define portMPU_MAIR_ATTR7_MASK ( 0xff000000 ) +#define portMPU_MAIR_ATTR7_POS ( 24UL ) +#define portMPU_MAIR_ATTR7_MASK ( 0xff000000 ) -#define portMPU_RLAR_ATTR_INDEX0 ( 0UL << 1UL ) -#define portMPU_RLAR_ATTR_INDEX1 ( 1UL << 1UL ) -#define portMPU_RLAR_ATTR_INDEX2 ( 2UL << 1UL ) -#define portMPU_RLAR_ATTR_INDEX3 ( 3UL << 1UL ) -#define portMPU_RLAR_ATTR_INDEX4 ( 4UL << 1UL ) -#define portMPU_RLAR_ATTR_INDEX5 ( 5UL << 1UL ) -#define portMPU_RLAR_ATTR_INDEX6 ( 6UL << 1UL ) -#define portMPU_RLAR_ATTR_INDEX7 ( 7UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX0 ( 0UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX1 ( 1UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX2 ( 2UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX3 ( 3UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX4 ( 4UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX5 ( 5UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX6 ( 6UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX7 ( 7UL << 1UL ) -#define portMPU_RLAR_REGION_ENABLE ( 1UL ) +#define portMPU_RLAR_REGION_ENABLE ( 1UL ) /* Enable privileged access to unmapped region. */ -#define portMPU_PRIV_BACKGROUND_ENABLE_BIT ( 1UL << 2UL ) +#define portMPU_PRIV_BACKGROUND_ENABLE_BIT ( 1UL << 2UL ) /* Enable MPU. */ -#define portMPU_ENABLE_BIT ( 1UL << 0UL ) +#define portMPU_ENABLE_BIT ( 1UL << 0UL ) /* Expected value of the portMPU_TYPE register. */ -#define portEXPECTED_MPU_TYPE_VALUE ( configTOTAL_MPU_REGIONS << 8UL ) +#define portEXPECTED_MPU_TYPE_VALUE ( configTOTAL_MPU_REGIONS << 8UL ) /* Extract first address of the MPU region as encoded in the * RBAR (Region Base Address Register) value. */ @@ -448,13 +472,13 @@ portDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIV #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) - /** - * @brief Sets up the task stack so that upon returning from - * SVC, the task stack is used again. - * - * @param pulSystemCallStack The current SP when the SVC was raised. - * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler. - */ +/** + * @brief Sets up the task stack so that upon returning from + * SVC, the task stack is used again. + * + * @param pulSystemCallStack The current SP when the SVC was raised. + * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler. + */ void vSystemCallExit( uint32_t * pulSystemCallStack, uint32_t ulLR ) PRIVILEGED_FUNCTION; @@ -462,11 +486,11 @@ portDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIV #if ( configENABLE_MPU == 1 ) - /** - * @brief Checks whether or not the calling task is privileged. - * - * @return pdTRUE if the calling task is privileged, pdFALSE otherwise. - */ +/** + * @brief Checks whether or not the calling task is privileged. + * + * @return pdTRUE if the calling task is privileged, pdFALSE otherwise. + */ BaseType_t xPortIsTaskPrivileged( void ) PRIVILEGED_FUNCTION; #endif /* configENABLE_MPU == 1 */ @@ -501,13 +525,13 @@ PRIVILEGED_DATA static volatile uint32_t ulCriticalNesting = 0xaaaaaaaaUL; * FreeRTOS API functions are not called from interrupts that have been assigned * a priority above configMAX_SYSCALL_INTERRUPT_PRIORITY. */ -#if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) ) +#if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) static uint8_t ucMaxSysCallPriority = 0; static uint32_t ulMaxPRIGROUPValue = 0; static const volatile uint8_t * const pcInterruptPriorityRegisters = ( const volatile uint8_t * ) portNVIC_IP_REGISTERS_OFFSET_16; -#endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) ) */ +#endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */ #if ( configUSE_TICKLESS_IDLE == 1 ) @@ -760,8 +784,15 @@ __attribute__( ( weak ) ) void vPortSetupTimerInterrupt( void ) /* PRIVILEGED_FU } #endif /* configUSE_TICKLESS_IDLE */ - /* Stop and reset the SysTick. */ - portNVIC_SYSTICK_CTRL_REG = 0UL; + /* Stop and reset SysTick. + * + * QEMU versions older than 7.0.0 contain a bug which causes an error if we + * enable SysTick without first selecting a valid clock source. We trigger + * the bug if we change clock sources from a clock with a zero clock period + * to one with a nonzero clock period and enable Systick at the same time. + * So we configure the CLKSOURCE bit here, prior to setting the ENABLE bit. + * This workaround avoids the bug in QEMU versions older than 7.0.0. */ + portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT_CONFIG; portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL; /* Configure SysTick to interrupt at the requested rate. */ @@ -819,6 +850,7 @@ static void prvTaskExitError( void ) static void prvSetupMPU( void ) /* PRIVILEGED_FUNCTION */ { #if defined( __ARMCC_VERSION ) + /* Declaration when these variable are defined in code instead of being * exported from linker scripts. */ extern uint32_t * __privileged_functions_start__; @@ -972,13 +1004,19 @@ void SysTick_Handler( void ) /* PRIVILEGED_FUNCTION */ uint32_t ulPreviousMask; ulPreviousMask = portSET_INTERRUPT_MASK_FROM_ISR(); + traceISR_ENTER(); { /* Increment the RTOS tick. */ if( xTaskIncrementTick() != pdFALSE ) { + traceISR_EXIT_TO_SCHEDULER(); /* Pend a context switch. */ portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; } + else + { + traceISR_EXIT(); + } } portCLEAR_INTERRUPT_MASK_FROM_ISR( ulPreviousMask ); } @@ -988,6 +1026,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO { #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) ) #if defined( __ARMCC_VERSION ) + /* Declaration when these variable are defined in code instead of being * exported from linker scripts. */ extern uint32_t * __syscalls_flash_start__; @@ -1083,18 +1122,24 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO vRestoreContextOfFirstTask(); break; - #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) ) - case portSVC_RAISE_PRIVILEGE: + #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) ) + case portSVC_RAISE_PRIVILEGE: - /* Only raise the privilege, if the svc was raised from any of - * the system calls. */ - if( ( ulPC >= ( uint32_t ) __syscalls_flash_start__ ) && - ( ulPC <= ( uint32_t ) __syscalls_flash_end__ ) ) - { - vRaisePrivilege(); - } - break; - #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) */ + /* Only raise the privilege, if the svc was raised from any of + * the system calls. */ + if( ( ulPC >= ( uint32_t ) __syscalls_flash_start__ ) && + ( ulPC <= ( uint32_t ) __syscalls_flash_end__ ) ) + { + vRaisePrivilege(); + } + break; + #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) */ + + #if ( configENABLE_MPU == 1 ) + case portSVC_YIELD: + vPortYield(); + break; + #endif /* configENABLE_MPU == 1 */ default: /* Incorrect SVC call. */ @@ -1154,12 +1199,11 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO { /* Extended frame i.e. FPU in use. */ ulStackFrameSize = 26; - __asm volatile - ( + __asm volatile ( " vpush {s0} \n" /* Trigger lazy stacking. */ " vpop {s0} \n" /* Nullify the affect of the above instruction. */ ::: "memory" - ); + ); } else { @@ -1171,7 +1215,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO { ulStackFrameSize = 8; } - #endif /* if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */ + #endif /* configENABLE_FPU || configENABLE_MVE */ /* Make space on the system call stack for the stack frame. */ pulSystemCallStack = pulSystemCallStack - ulStackFrameSize; @@ -1187,18 +1231,24 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO * point (i.e. the caller of the MPU_). We need to restore it * when we exit from the system call. */ pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry = pulTaskStack[ portOFFSET_TO_LR ]; - /* Store the value of the PSPLIM register before the SVC was raised. * We need to restore it when we exit from the system call. */ - __asm volatile ( "mrs %0, psplim" : "=r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) ); + #if ( portUSE_PSPLIM_REGISTER == 1 ) + { + __asm volatile ( "mrs %0, psplim" : "=r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) ); + } + #endif /* Use the pulSystemCallStack in thread mode. */ __asm volatile ( "msr psp, %0" : : "r" ( pulSystemCallStack ) ); - __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) ); + #if ( portUSE_PSPLIM_REGISTER == 1 ) + { + __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) ); + } + #endif /* Start executing the system call upon returning from this handler. */ pulSystemCallStack[ portOFFSET_TO_PC ] = uxSystemCallImplementations[ ucSystemCallNumber ]; - /* Raise a request to exit from the system call upon finishing the * system call. */ pulSystemCallStack[ portOFFSET_TO_LR ] = ( uint32_t ) vRequestSystemCallExit; @@ -1224,14 +1274,13 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO pulSystemCallStack[ portOFFSET_TO_PSR ] &= ( ~portPSR_STACK_PADDING_MASK ); /* Raise the privilege for the duration of the system call. */ - __asm volatile - ( + __asm volatile ( " mrs r0, control \n" /* Obtain current control value. */ " movs r1, #1 \n" /* r1 = 1. */ " bics r0, r1 \n" /* Clear nPRIV bit. */ " msr control, r0 \n" /* Write back new control value. */ ::: "r0", "r1", "memory" - ); + ); } } @@ -1293,12 +1342,11 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO { /* Extended frame i.e. FPU in use. */ ulStackFrameSize = 26; - __asm volatile - ( + __asm volatile ( " vpush {s0} \n" /* Trigger lazy stacking. */ " vpop {s0} \n" /* Nullify the affect of the above instruction. */ ::: "memory" - ); + ); } else { @@ -1310,7 +1358,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO { ulStackFrameSize = 8; } - #endif /* if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */ + #endif /* configENABLE_FPU || configENABLE_MVE */ /* Make space on the task stack for the stack frame. */ pulTaskStack = pulTaskStack - ulStackFrameSize; @@ -1332,7 +1380,11 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO /* Restore the PSPLIM register to what it was at the time of * system call entry. */ - __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) ); + #if ( portUSE_PSPLIM_REGISTER == 1 ) + { + __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) ); + } + #endif /* If the hardware used padding to force the stack pointer * to be double word aligned, set the stacked xPSR bit[9], @@ -1350,14 +1402,13 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO pxMpuSettings->xSystemCallStackInfo.pulTaskStack = NULL; /* Drop the privilege before returning to the thread mode. */ - __asm volatile - ( + __asm volatile ( " mrs r0, control \n" /* Obtain current control value. */ " movs r1, #1 \n" /* r1 = 1. */ " orrs r0, r1 \n" /* Set nPRIV bit. */ " msr control, r0 \n" /* Write back new control value. */ ::: "r0", "r1", "memory" - ); + ); } } @@ -1410,21 +1461,21 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO xMPUSettings->ulContext[ ulIndex ] = 0x11111111; /* r11. */ ulIndex++; - xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pvParameters; /* r0. */ + xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pvParameters; /* r0. */ ulIndex++; - xMPUSettings->ulContext[ ulIndex ] = 0x01010101; /* r1. */ + xMPUSettings->ulContext[ ulIndex ] = 0x01010101; /* r1. */ ulIndex++; - xMPUSettings->ulContext[ ulIndex ] = 0x02020202; /* r2. */ + xMPUSettings->ulContext[ ulIndex ] = 0x02020202; /* r2. */ ulIndex++; - xMPUSettings->ulContext[ ulIndex ] = 0x03030303; /* r3. */ + xMPUSettings->ulContext[ ulIndex ] = 0x03030303; /* r3. */ ulIndex++; - xMPUSettings->ulContext[ ulIndex ] = 0x12121212; /* r12. */ + xMPUSettings->ulContext[ ulIndex ] = 0x12121212; /* r12. */ ulIndex++; xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portTASK_RETURN_ADDRESS; /* LR. */ ulIndex++; - xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxCode; /* PC. */ + xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxCode; /* PC. */ ulIndex++; - xMPUSettings->ulContext[ ulIndex ] = portINITIAL_XPSR; /* xPSR. */ + xMPUSettings->ulContext[ ulIndex ] = portINITIAL_XPSR; /* xPSR. */ ulIndex++; #if ( configENABLE_TRUSTZONE == 1 ) @@ -1435,8 +1486,9 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO #endif /* configENABLE_TRUSTZONE */ xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) ( pxTopOfStack - 8 ); /* PSP with the hardware saved stack. */ ulIndex++; - xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxEndOfStack; /* PSPLIM. */ + xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxEndOfStack; /* PSPLIM. */ ulIndex++; + if( xRunPrivileged == pdTRUE ) { xMPUSettings->ulTaskFlags |= portTASK_IS_PRIVILEGED_FLAG; @@ -1449,6 +1501,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portINITIAL_CONTROL_UNPRIVILEGED; /* CONTROL. */ ulIndex++; } + xMPUSettings->ulContext[ ulIndex ] = portINITIAL_EXC_RETURN; /* LR (EXC_RETURN). */ ulIndex++; @@ -1483,7 +1536,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO * interrupt. */ #if ( portPRELOAD_REGISTERS == 0 ) { - pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */ + pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */ *pxTopOfStack = portINITIAL_XPSR; /* xPSR. */ pxTopOfStack--; *pxTopOfStack = ( StackType_t ) pxCode; /* PC. */ @@ -1505,7 +1558,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO } #else /* portPRELOAD_REGISTERS */ { - pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */ + pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */ *pxTopOfStack = portINITIAL_XPSR; /* xPSR. */ pxTopOfStack--; *pxTopOfStack = ( StackType_t ) pxCode; /* PC. */ @@ -1540,7 +1593,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO pxTopOfStack--; *pxTopOfStack = portINITIAL_EXC_RETURN; /* EXC_RETURN. */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */ + *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */ #if ( configENABLE_TRUSTZONE == 1 ) { @@ -1559,22 +1612,52 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */ { - #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) ) + /* An application can install FreeRTOS interrupt handlers in one of the + * folllowing ways: + * 1. Direct Routing - Install the functions SVC_Handler and PendSV_Handler + * for SVCall and PendSV interrupts respectively. + * 2. Indirect Routing - Install separate handlers for SVCall and PendSV + * interrupts and route program control from those handlers to + * SVC_Handler and PendSV_Handler functions. + * + * Applications that use Indirect Routing must set + * configCHECK_HANDLER_INSTALLATION to 0 in their FreeRTOSConfig.h. Direct + * routing, which is validated here when configCHECK_HANDLER_INSTALLATION + * is 1, should be preferred when possible. */ + #if ( configCHECK_HANDLER_INSTALLATION == 1 ) + { + const portISR_t * const pxVectorTable = portSCB_VTOR_REG; + + /* Validate that the application has correctly installed the FreeRTOS + * handlers for SVCall and PendSV interrupts. We do not check the + * installation of the SysTick handler because the application may + * choose to drive the RTOS tick using a timer other than the SysTick + * timer by overriding the weak function vPortSetupTimerInterrupt(). + * + * Assertion failures here indicate incorrect installation of the + * FreeRTOS handlers. For help installing the FreeRTOS handlers, see + * https://www.FreeRTOS.org/FAQHelp.html. + * + * Systems with a configurable address for the interrupt vector table + * can also encounter assertion failures or even system faults here if + * VTOR is not set correctly to point to the application's vector table. */ + configASSERT( pxVectorTable[ portVECTOR_INDEX_SVC ] == SVC_Handler ); + configASSERT( pxVectorTable[ portVECTOR_INDEX_PENDSV ] == PendSV_Handler ); + } + #endif /* configCHECK_HANDLER_INSTALLATION */ + + #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) { - volatile uint32_t ulOriginalPriority; volatile uint32_t ulImplementedPrioBits = 0; volatile uint8_t ucMaxPriorityValue; /* Determine the maximum priority from which ISR safe FreeRTOS API - * functions can be called. ISR safe functions are those that end in - * "FromISR". FreeRTOS maintains separate thread and ISR API functions to + * functions can be called. ISR safe functions are those that end in + * "FromISR". FreeRTOS maintains separate thread and ISR API functions to * ensure interrupt entry is as fast and simple as possible. * - * Save the interrupt priority value that is about to be clobbered. */ - ulOriginalPriority = portNVIC_SHPR2_REG; - - /* Determine the number of priority bits available. First write to all - * possible bits. */ + * First, determine the number of priority bits available. Write to all + * possible bits in the priority setting for SVCall. */ portNVIC_SHPR2_REG = 0xFF000000; /* Read the value back to see how many bits stuck. */ @@ -1593,11 +1676,10 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */ /* Check that the bits not implemented in hardware are zero in * configMAX_SYSCALL_INTERRUPT_PRIORITY. */ - configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( ~ucMaxPriorityValue ) ) == 0U ); + configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( uint8_t ) ( ~( uint32_t ) ucMaxPriorityValue ) ) == 0U ); /* Calculate the maximum acceptable priority group value for the number * of bits read back. */ - while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE ) { ulImplementedPrioBits++; @@ -1635,16 +1717,14 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */ * register. */ ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT; ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK; - - /* Restore the clobbered interrupt priority register to its original - * value. */ - portNVIC_SHPR2_REG = ulOriginalPriority; } - #endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) ) */ + #endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */ - /* Make PendSV, CallSV and SysTick the same priority as the kernel. */ + /* Make PendSV and SysTick the lowest priority interrupts, and make SVCall + * the highest priority. */ portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI; portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI; + portNVIC_SHPR2_REG = 0; #if ( configENABLE_MPU == 1 ) { @@ -1701,6 +1781,7 @@ void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */ int32_t lIndex = 0; #if defined( __ARMCC_VERSION ) + /* Declaration when these variable are defined in code instead of being * exported from linker scripts. */ extern uint32_t * __privileged_sram_start__; @@ -1886,7 +1967,7 @@ BaseType_t xPortIsInsideInterrupt( void ) } /*-----------------------------------------------------------*/ -#if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) ) +#if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) void vPortValidateInterruptPriority( void ) { @@ -1944,7 +2025,7 @@ BaseType_t xPortIsInsideInterrupt( void ) configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue ); } -#endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) ) */ +#endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */ /*-----------------------------------------------------------*/ #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) diff --git a/Source/portable/IAR/ARM_CM35P/non_secure/portasm.h b/Source/portable/IAR/ARM_CM35P/non_secure/portasm.h index f64ceb525..c6d2ebd58 100644 --- a/Source/portable/IAR/ARM_CM35P/non_secure/portasm.h +++ b/Source/portable/IAR/ARM_CM35P/non_secure/portasm.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/Source/portable/IAR/ARM_CM35P/non_secure/portasm.s b/Source/portable/IAR/ARM_CM35P/non_secure/portasm.s index 530910341..6a6b677bf 100644 --- a/Source/portable/IAR/ARM_CM35P/non_secure/portasm.s +++ b/Source/portable/IAR/ARM_CM35P/non_secure/portasm.s @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/Source/portable/IAR/ARM_CM35P/non_secure/portmacro.h b/Source/portable/IAR/ARM_CM35P/non_secure/portmacro.h index 247468478..e24fabc75 100644 --- a/Source/portable/IAR/ARM_CM35P/non_secure/portmacro.h +++ b/Source/portable/IAR/ARM_CM35P/non_secure/portmacro.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -48,16 +48,16 @@ /** * Architecture specifics. */ -#define portARCH_NAME "Cortex-M35P" -#define portHAS_BASEPRI 1 -#define portDONT_DISCARD __root +#define portARCH_NAME "Cortex-M35P" +#define portHAS_ARMV8M_MAIN_EXTENSION 1 +#define portDONT_DISCARD __root /*-----------------------------------------------------------*/ /* ARMv8-M common port configurations. */ #include "portmacrocommon.h" /*-----------------------------------------------------------*/ -#if( configTOTAL_MPU_REGIONS == 16 ) +#if ( configTOTAL_MPU_REGIONS == 16 ) #error 16 MPU regions are not yet supported for this port. #endif /*-----------------------------------------------------------*/ @@ -65,8 +65,8 @@ /** * @brief Critical section management. */ -#define portDISABLE_INTERRUPTS() ulSetInterruptMask() -#define portENABLE_INTERRUPTS() vClearInterruptMask( 0 ) +#define portDISABLE_INTERRUPTS() ulSetInterruptMask() +#define portENABLE_INTERRUPTS() vClearInterruptMask( 0 ) /*-----------------------------------------------------------*/ /* Suppress warnings that are generated by the IAR tools, but cannot be fixed in diff --git a/Source/portable/IAR/ARM_CM35P/non_secure/portmacrocommon.h b/Source/portable/IAR/ARM_CM35P/non_secure/portmacrocommon.h index 6f666da22..33f21d85b 100644 --- a/Source/portable/IAR/ARM_CM35P/non_secure/portmacrocommon.h +++ b/Source/portable/IAR/ARM_CM35P/non_secure/portmacrocommon.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -117,7 +117,7 @@ extern uint32_t ulSetInterruptMask( void ) /* __attribute__(( naked )) PRIVILEGE extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */; #if ( configENABLE_TRUSTZONE == 1 ) - extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize ); /* __attribute__ (( naked )) */ + extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize ); /* __attribute__ (( naked )) */ extern void vPortFreeSecureContext( uint32_t * pulTCB ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */; #endif /* configENABLE_TRUSTZONE */ @@ -188,13 +188,13 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P #if ( configENABLE_MPU == 1 ) - /** - * @brief Settings to define an MPU region. - */ +/** + * @brief Settings to define an MPU region. + */ typedef struct MPURegionSettings { - uint32_t ulRBAR; /**< RBAR for the region. */ - uint32_t ulRLAR; /**< RLAR for the region. */ + uint32_t ulRBAR; /**< RBAR for the region. */ + uint32_t ulRLAR; /**< RLAR for the region. */ } MPURegionSettings_t; #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) @@ -203,9 +203,9 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P #error configSYSTEM_CALL_STACK_SIZE must be defined to the desired size of the system call stack in words for using MPU wrappers v2. #endif - /** - * @brief System call stack. - */ +/** + * @brief System call stack. + */ typedef struct SYSTEM_CALL_STACK_INFO { uint32_t ulSystemCallStackBuffer[ configSYSTEM_CALL_STACK_SIZE ]; @@ -218,74 +218,74 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P #endif /* configUSE_MPU_WRAPPERS_V1 == 0 */ - /** - * @brief MPU settings as stored in the TCB. - */ +/** + * @brief MPU settings as stored in the TCB. + */ #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) - #if( configENABLE_TRUSTZONE == 1 ) + #if ( configENABLE_TRUSTZONE == 1 ) - /* - * +-----------+---------------+----------+-----------------+------------------------------+-----+ - * | s16-s31 | s0-s15, FPSCR | r4-r11 | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, | | - * | | | | PC, xPSR | CONTROL, EXC_RETURN | | - * +-----------+---------------+----------+-----------------+------------------------------+-----+ - * - * <-----------><--------------><---------><----------------><-----------------------------><----> - * 16 16 8 8 5 1 - */ - #define MAX_CONTEXT_SIZE 54 +/* + * +-----------+---------------+----------+-----------------+------------------------------+-----+ + * | s16-s31 | s0-s15, FPSCR | r4-r11 | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, | | + * | | | | PC, xPSR | CONTROL, EXC_RETURN | | + * +-----------+---------------+----------+-----------------+------------------------------+-----+ + * + * <-----------><--------------><---------><----------------><-----------------------------><----> + * 16 16 8 8 5 1 + */ + #define MAX_CONTEXT_SIZE 54 #else /* #if( configENABLE_TRUSTZONE == 1 ) */ - /* - * +-----------+---------------+----------+-----------------+----------------------+-----+ - * | s16-s31 | s0-s15, FPSCR | r4-r11 | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL | | - * | | | | PC, xPSR | EXC_RETURN | | - * +-----------+---------------+----------+-----------------+----------------------+-----+ - * - * <-----------><--------------><---------><----------------><---------------------><----> - * 16 16 8 8 4 1 - */ - #define MAX_CONTEXT_SIZE 53 +/* + * +-----------+---------------+----------+-----------------+----------------------+-----+ + * | s16-s31 | s0-s15, FPSCR | r4-r11 | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL | | + * | | | | PC, xPSR | EXC_RETURN | | + * +-----------+---------------+----------+-----------------+----------------------+-----+ + * + * <-----------><--------------><---------><----------------><---------------------><----> + * 16 16 8 8 4 1 + */ + #define MAX_CONTEXT_SIZE 53 #endif /* #if( configENABLE_TRUSTZONE == 1 ) */ #else /* #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */ - #if( configENABLE_TRUSTZONE == 1 ) + #if ( configENABLE_TRUSTZONE == 1 ) - /* - * +----------+-----------------+------------------------------+-----+ - * | r4-r11 | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, | | - * | | PC, xPSR | CONTROL, EXC_RETURN | | - * +----------+-----------------+------------------------------+-----+ - * - * <---------><----------------><------------------------------><----> - * 8 8 5 1 - */ - #define MAX_CONTEXT_SIZE 22 +/* + * +----------+-----------------+------------------------------+-----+ + * | r4-r11 | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, | | + * | | PC, xPSR | CONTROL, EXC_RETURN | | + * +----------+-----------------+------------------------------+-----+ + * + * <---------><----------------><------------------------------><----> + * 8 8 5 1 + */ + #define MAX_CONTEXT_SIZE 22 #else /* #if( configENABLE_TRUSTZONE == 1 ) */ - /* - * +----------+-----------------+----------------------+-----+ - * | r4-r11 | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL | | - * | | PC, xPSR | EXC_RETURN | | - * +----------+-----------------+----------------------+-----+ - * - * <---------><----------------><----------------------><----> - * 8 8 4 1 - */ - #define MAX_CONTEXT_SIZE 21 +/* + * +----------+-----------------+----------------------+-----+ + * | r4-r11 | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL | | + * | | PC, xPSR | EXC_RETURN | | + * +----------+-----------------+----------------------+-----+ + * + * <---------><----------------><----------------------><----> + * 8 8 4 1 + */ + #define MAX_CONTEXT_SIZE 21 #endif /* #if( configENABLE_TRUSTZONE == 1 ) */ #endif /* #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */ - /* Flags used for xMPU_SETTINGS.ulTaskFlags member. */ - #define portSTACK_FRAME_HAS_PADDING_FLAG ( 1UL << 0UL ) - #define portTASK_IS_PRIVILEGED_FLAG ( 1UL << 1UL ) +/* Flags used for xMPU_SETTINGS.ulTaskFlags member. */ + #define portSTACK_FRAME_HAS_PADDING_FLAG ( 1UL << 0UL ) + #define portTASK_IS_PRIVILEGED_FLAG ( 1UL << 1UL ) /* Size of an Access Control List (ACL) entry in bits. */ #define portACL_ENTRY_SIZE_BITS ( 32U ) @@ -313,7 +313,7 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P * system calls. */ #ifdef configASSERT - #if ( portHAS_BASEPRI == 1 ) + #if ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) void vPortValidateInterruptPriority( void ); #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() vPortValidateInterruptPriority() #endif @@ -333,12 +333,29 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P /** * @brief Scheduler utilities. */ -#define portYIELD() vPortYield() +#if ( configENABLE_MPU == 1 ) + #define portYIELD() __asm volatile ( "svc %0" ::"i" ( portSVC_YIELD ) : "memory" ) + #define portYIELD_WITHIN_API() vPortYield() +#else + #define portYIELD() vPortYield() + #define portYIELD_WITHIN_API() vPortYield() +#endif + #define portNVIC_INT_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed04 ) ) #define portNVIC_PENDSVSET_BIT ( 1UL << 28UL ) -#define portEND_SWITCHING_ISR( xSwitchRequired ) \ - do { if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; } \ - while( 0 ) +#define portEND_SWITCHING_ISR( xSwitchRequired ) \ + do \ + { \ + if( xSwitchRequired ) \ + { \ + traceISR_EXIT_TO_SCHEDULER(); \ + portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; \ + } \ + else \ + { \ + traceISR_EXIT(); \ + } \ + } while( 0 ) #define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x ) /*-----------------------------------------------------------*/ @@ -424,12 +441,12 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P extern BaseType_t xPortIsTaskPrivileged( void ); - /** - * @brief Checks whether or not the calling task is privileged. - * - * @return pdTRUE if the calling task is privileged, pdFALSE otherwise. - */ - #define portIS_TASK_PRIVILEGED() xPortIsTaskPrivileged() +/** + * @brief Checks whether or not the calling task is privileged. + * + * @return pdTRUE if the calling task is privileged, pdFALSE otherwise. + */ + #define portIS_TASK_PRIVILEGED() xPortIsTaskPrivileged() #endif /* configENABLE_MPU == 1 */ /*-----------------------------------------------------------*/ @@ -440,6 +457,56 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P #define portMEMORY_BARRIER() __asm volatile ( "" ::: "memory" ) /*-----------------------------------------------------------*/ +/* Select correct value of configUSE_PORT_OPTIMISED_TASK_SELECTION + * based on whether or not Mainline extension is implemented. */ +#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION + #if ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) + #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1 + #else + #define configUSE_PORT_OPTIMISED_TASK_SELECTION 0 + #endif +#endif /* #ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION */ + +/** + * @brief Port-optimised task selection. + */ +#if ( configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 ) + +/** + * @brief Count the number of leading zeros in a 32-bit value. + */ + static portFORCE_INLINE uint32_t ulPortCountLeadingZeros( uint32_t ulBitmap ) + { + uint32_t ulReturn; + + __asm volatile ( "clz %0, %1" : "=r" ( ulReturn ) : "r" ( ulBitmap ) : "memory" ); + + return ulReturn; + } + +/* Check the configuration. */ + #if ( configMAX_PRIORITIES > 32 ) + #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 different priorities as tasks that share a priority will time slice. + #endif + + #if ( portHAS_ARMV8M_MAIN_EXTENSION == 0 ) + #error ARMv8-M baseline implementations (such as Cortex-M23) do not support port-optimised task selection. Please set configUSE_PORT_OPTIMISED_TASK_SELECTION to 0 or leave it undefined. + #endif + +/** + * @brief Store/clear the ready priorities in a bit map. + */ + #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) ) + #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) ) + +/** + * @brief Get the priority of the highest-priority task that is ready to execute. + */ + #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - ulPortCountLeadingZeros( ( uxReadyPriorities ) ) ) + +#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */ +/*-----------------------------------------------------------*/ + /* *INDENT-OFF* */ #ifdef __cplusplus } diff --git a/Source/portable/IAR/ARM_CM35P/secure/secure_context.c b/Source/portable/IAR/ARM_CM35P/secure/secure_context.c index e37dd9672..83b3dbce1 100644 --- a/Source/portable/IAR/ARM_CM35P/secure/secure_context.c +++ b/Source/portable/IAR/ARM_CM35P/secure/secure_context.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -65,7 +65,7 @@ * @brief Maximum number of secure contexts. */ #ifndef secureconfigMAX_SECURE_CONTEXTS - #define secureconfigMAX_SECURE_CONTEXTS 8UL + #define secureconfigMAX_SECURE_CONTEXTS 8UL #endif /*-----------------------------------------------------------*/ @@ -164,15 +164,15 @@ secureportNON_SECURE_CALLABLE void SecureContext_Init( void ) } #if ( configENABLE_MPU == 1 ) - { - /* Configure thread mode to use PSP and to be unprivileged. */ - secureportSET_CONTROL( securecontextCONTROL_VALUE_UNPRIVILEGED ); - } + { + /* Configure thread mode to use PSP and to be unprivileged. */ + secureportSET_CONTROL( securecontextCONTROL_VALUE_UNPRIVILEGED ); + } #else /* configENABLE_MPU */ - { - /* Configure thread mode to use PSP and to be privileged. */ - secureportSET_CONTROL( securecontextCONTROL_VALUE_PRIVILEGED ); - } + { + /* Configure thread mode to use PSP and to be privileged. */ + secureportSET_CONTROL( securecontextCONTROL_VALUE_PRIVILEGED ); + } #endif /* configENABLE_MPU */ } } @@ -219,16 +219,16 @@ secureportNON_SECURE_CALLABLE void SecureContext_Init( void ) if( pucStackMemory != NULL ) { /* Since stack grows down, the starting point will be the last - * location. Note that this location is next to the last - * allocated byte for stack (excluding the space for seal values) - * because the hardware decrements the stack pointer before - * writing i.e. if stack pointer is 0x2, a push operation will - * decrement the stack pointer to 0x1 and then write at 0x1. */ + * location. Note that this location is next to the last + * allocated byte for stack (excluding the space for seal values) + * because the hardware decrements the stack pointer before + * writing i.e. if stack pointer is 0x2, a push operation will + * decrement the stack pointer to 0x1 and then write at 0x1. */ xSecureContexts[ ulSecureContextIndex ].pucStackStart = pucStackMemory + ulSecureStackSize; /* Seal the created secure process stack. */ - *( uint32_t * )( pucStackMemory + ulSecureStackSize ) = securecontextSTACK_SEAL_VALUE; - *( uint32_t * )( pucStackMemory + ulSecureStackSize + 4 ) = securecontextSTACK_SEAL_VALUE; + *( uint32_t * ) ( pucStackMemory + ulSecureStackSize ) = securecontextSTACK_SEAL_VALUE; + *( uint32_t * ) ( pucStackMemory + ulSecureStackSize + 4 ) = securecontextSTACK_SEAL_VALUE; /* The stack cannot go beyond this location. This value is * programmed in the PSPLIM register on context switch.*/ @@ -237,32 +237,32 @@ secureportNON_SECURE_CALLABLE void SecureContext_Init( void ) xSecureContexts[ ulSecureContextIndex ].pvTaskHandle = pvTaskHandle; #if ( configENABLE_MPU == 1 ) + { + /* Store the correct CONTROL value for the task on the stack. + * This value is programmed in the CONTROL register on + * context switch. */ + pulCurrentStackPointer = ( uint32_t * ) xSecureContexts[ ulSecureContextIndex ].pucStackStart; + pulCurrentStackPointer--; + + if( ulIsTaskPrivileged ) { - /* Store the correct CONTROL value for the task on the stack. - * This value is programmed in the CONTROL register on - * context switch. */ - pulCurrentStackPointer = ( uint32_t * ) xSecureContexts[ ulSecureContextIndex ].pucStackStart; - pulCurrentStackPointer--; - - if( ulIsTaskPrivileged ) - { - *( pulCurrentStackPointer ) = securecontextCONTROL_VALUE_PRIVILEGED; - } - else - { - *( pulCurrentStackPointer ) = securecontextCONTROL_VALUE_UNPRIVILEGED; - } - - /* Store the current stack pointer. This value is programmed in - * the PSP register on context switch. */ - xSecureContexts[ ulSecureContextIndex ].pucCurrentStackPointer = ( uint8_t * ) pulCurrentStackPointer; + *( pulCurrentStackPointer ) = securecontextCONTROL_VALUE_PRIVILEGED; } - #else /* configENABLE_MPU */ + else { - /* Current SP is set to the starting of the stack. This - * value programmed in the PSP register on context switch. */ - xSecureContexts[ ulSecureContextIndex ].pucCurrentStackPointer = xSecureContexts[ ulSecureContextIndex ].pucStackStart; + *( pulCurrentStackPointer ) = securecontextCONTROL_VALUE_UNPRIVILEGED; } + + /* Store the current stack pointer. This value is programmed in + * the PSP register on context switch. */ + xSecureContexts[ ulSecureContextIndex ].pucCurrentStackPointer = ( uint8_t * ) pulCurrentStackPointer; + } + #else /* configENABLE_MPU */ + { + /* Current SP is set to the starting of the stack. This + * value programmed in the PSP register on context switch. */ + xSecureContexts[ ulSecureContextIndex ].pucCurrentStackPointer = xSecureContexts[ ulSecureContextIndex ].pucStackStart; + } #endif /* configENABLE_MPU */ /* Ensure to never return 0 as a valid context handle. */ @@ -275,7 +275,8 @@ secureportNON_SECURE_CALLABLE void SecureContext_Init( void ) } /*-----------------------------------------------------------*/ -secureportNON_SECURE_CALLABLE void SecureContext_FreeContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle ) +secureportNON_SECURE_CALLABLE void SecureContext_FreeContext( SecureContextHandle_t xSecureContextHandle, + void * pvTaskHandle ) { uint32_t ulIPSR, ulSecureContextIndex; @@ -306,7 +307,8 @@ secureportNON_SECURE_CALLABLE void SecureContext_FreeContext( SecureContextHandl } /*-----------------------------------------------------------*/ -secureportNON_SECURE_CALLABLE void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle ) +secureportNON_SECURE_CALLABLE void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle, + void * pvTaskHandle ) { uint8_t * pucStackLimit; uint32_t ulSecureContextIndex; @@ -328,7 +330,8 @@ secureportNON_SECURE_CALLABLE void SecureContext_LoadContext( SecureContextHandl } /*-----------------------------------------------------------*/ -secureportNON_SECURE_CALLABLE void SecureContext_SaveContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle ) +secureportNON_SECURE_CALLABLE void SecureContext_SaveContext( SecureContextHandle_t xSecureContextHandle, + void * pvTaskHandle ) { uint8_t * pucStackLimit; uint32_t ulSecureContextIndex; diff --git a/Source/portable/IAR/ARM_CM35P/secure/secure_context.h b/Source/portable/IAR/ARM_CM35P/secure/secure_context.h index 2220ea646..40fdc276d 100644 --- a/Source/portable/IAR/ARM_CM35P/secure/secure_context.h +++ b/Source/portable/IAR/ARM_CM35P/secure/secure_context.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -38,12 +38,12 @@ /** * @brief PSP value when no secure context is loaded. */ -#define securecontextNO_STACK 0x0 +#define securecontextNO_STACK 0x0 /** * @brief Invalid context ID. */ -#define securecontextINVALID_CONTEXT_ID 0UL +#define securecontextINVALID_CONTEXT_ID 0UL /*-----------------------------------------------------------*/ /** @@ -108,7 +108,8 @@ void SecureContext_Init( void ); * @param[in] xSecureContextHandle Context handle corresponding to the * context to be freed. */ -void SecureContext_FreeContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle ); +void SecureContext_FreeContext( SecureContextHandle_t xSecureContextHandle, + void * pvTaskHandle ); /** * @brief Loads the given context. @@ -119,7 +120,8 @@ void SecureContext_FreeContext( SecureContextHandle_t xSecureContextHandle, void * @param[in] xSecureContextHandle Context handle corresponding to the context * to be loaded. */ -void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle ); +void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle, + void * pvTaskHandle ); /** * @brief Saves the given context. @@ -130,6 +132,7 @@ void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle, void * @param[in] xSecureContextHandle Context handle corresponding to the context * to be saved. */ -void SecureContext_SaveContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle ); +void SecureContext_SaveContext( SecureContextHandle_t xSecureContextHandle, + void * pvTaskHandle ); #endif /* __SECURE_CONTEXT_H__ */ diff --git a/Source/portable/IAR/ARM_CM35P/secure/secure_context_port_asm.s b/Source/portable/IAR/ARM_CM35P/secure/secure_context_port_asm.s index 0da3e0f12..5124d9246 100644 --- a/Source/portable/IAR/ARM_CM35P/secure/secure_context_port_asm.s +++ b/Source/portable/IAR/ARM_CM35P/secure/secure_context_port_asm.s @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/Source/portable/IAR/ARM_CM35P/secure/secure_heap.c b/Source/portable/IAR/ARM_CM35P/secure/secure_heap.c index 19f7c2354..d9789404b 100644 --- a/Source/portable/IAR/ARM_CM35P/secure/secure_heap.c +++ b/Source/portable/IAR/ARM_CM35P/secure/secure_heap.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -62,6 +62,22 @@ /* Assumes 8bit bytes! */ #define secureheapBITS_PER_BYTE ( ( size_t ) 8 ) + +/* Max value that fits in a size_t type. */ +#define secureheapSIZE_MAX ( ~( ( size_t ) 0 ) ) + +/* Check if adding a and b will result in overflow. */ +#define secureheapADD_WILL_OVERFLOW( a, b ) ( ( a ) > ( secureheapSIZE_MAX - ( b ) ) ) + +/* MSB of the xBlockSize member of an BlockLink_t structure is used to track + * the allocation status of a block. When MSB of the xBlockSize member of + * an BlockLink_t structure is set then the block belongs to the application. + * When the bit is free the block is still part of the free heap space. */ +#define secureheapBLOCK_ALLOCATED_BITMASK ( ( ( size_t ) 1 ) << ( ( sizeof( size_t ) * secureheapBITS_PER_BYTE ) - 1 ) ) +#define secureheapBLOCK_SIZE_IS_VALID( xBlockSize ) ( ( ( xBlockSize ) & secureheapBLOCK_ALLOCATED_BITMASK ) == 0 ) +#define secureheapBLOCK_IS_ALLOCATED( pxBlock ) ( ( ( pxBlock->xBlockSize ) & secureheapBLOCK_ALLOCATED_BITMASK ) != 0 ) +#define secureheapALLOCATE_BLOCK( pxBlock ) ( ( pxBlock->xBlockSize ) |= secureheapBLOCK_ALLOCATED_BITMASK ) +#define secureheapFREE_BLOCK( pxBlock ) ( ( pxBlock->xBlockSize ) &= ~secureheapBLOCK_ALLOCATED_BITMASK ) /*-----------------------------------------------------------*/ /* Allocate the memory for the heap. */ @@ -123,14 +139,6 @@ static BlockLink_t * pxEnd = NULL; static size_t xFreeBytesRemaining = 0U; static size_t xMinimumEverFreeBytesRemaining = 0U; -/** - * @brief Gets set to the top bit of an size_t type. - * - * When this bit in the xBlockSize member of an BlockLink_t structure is set - * then the block belongs to the application. When the bit is free the block is - * still part of the free heap space. - */ -static size_t xBlockAllocatedBit = 0; /*-----------------------------------------------------------*/ static void prvHeapInit( void ) @@ -175,9 +183,6 @@ static void prvHeapInit( void ) /* Only one block exists - and it covers the entire usable heap space. */ xMinimumEverFreeBytesRemaining = pxFirstFreeBlock->xBlockSize; xFreeBytesRemaining = pxFirstFreeBlock->xBlockSize; - - /* Work out the position of the top bit in a size_t variable. */ - xBlockAllocatedBit = ( ( size_t ) 1 ) << ( ( sizeof( size_t ) * secureheapBITS_PER_BYTE ) - 1 ); } /*-----------------------------------------------------------*/ @@ -250,6 +255,7 @@ void * pvPortMalloc( size_t xWantedSize ) BlockLink_t * pxPreviousBlock; BlockLink_t * pxNewBlockLink; void * pvReturn = NULL; + size_t xAdditionalRequiredSize; /* If this is the first call to malloc then the heap will require * initialisation to setup the list of free blocks. */ @@ -262,25 +268,29 @@ void * pvPortMalloc( size_t xWantedSize ) mtCOVERAGE_TEST_MARKER(); } - /* Check the requested block size is not so large that the top bit is set. - * The top bit of the block size member of the BlockLink_t structure is used - * to determine who owns the block - the application or the kernel, so it - * must be free. */ - if( ( xWantedSize & xBlockAllocatedBit ) == 0 ) + if( xWantedSize > 0 ) { - /* The wanted size is increased so it can contain a BlockLink_t + /* The wanted size must be increased so it can contain a BlockLink_t * structure in addition to the requested amount of bytes. */ - if( xWantedSize > 0 ) + if( secureheapADD_WILL_OVERFLOW( xWantedSize, xHeapStructSize ) == 0 ) { xWantedSize += xHeapStructSize; - /* Ensure that blocks are always aligned to the required number of - * bytes. */ + /* Ensure that blocks are always aligned to the required number + * of bytes. */ if( ( xWantedSize & secureportBYTE_ALIGNMENT_MASK ) != 0x00 ) { /* Byte alignment required. */ - xWantedSize += ( secureportBYTE_ALIGNMENT - ( xWantedSize & secureportBYTE_ALIGNMENT_MASK ) ); - secureportASSERT( ( xWantedSize & secureportBYTE_ALIGNMENT_MASK ) == 0 ); + xAdditionalRequiredSize = secureportBYTE_ALIGNMENT - ( xWantedSize & secureportBYTE_ALIGNMENT_MASK ); + + if( secureheapADD_WILL_OVERFLOW( xWantedSize, xAdditionalRequiredSize ) == 0 ) + { + xWantedSize += xAdditionalRequiredSize; + } + else + { + xWantedSize = 0; + } } else { @@ -289,9 +299,20 @@ void * pvPortMalloc( size_t xWantedSize ) } else { - mtCOVERAGE_TEST_MARKER(); + xWantedSize = 0; } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + /* Check the requested block size is not so large that the top bit is set. + * The top bit of the block size member of the BlockLink_t structure is used + * to determine who owns the block - the application or the kernel, so it + * must be free. */ + if( secureheapBLOCK_SIZE_IS_VALID( xWantedSize ) != 0 ) + { if( ( xWantedSize > 0 ) && ( xWantedSize <= xFreeBytesRemaining ) ) { /* Traverse the list from the start (lowest address) block until @@ -334,7 +355,8 @@ void * pvPortMalloc( size_t xWantedSize ) pxBlock->xBlockSize = xWantedSize; /* Insert the new block into the list of free blocks. */ - prvInsertBlockIntoFreeList( pxNewBlockLink ); + pxNewBlockLink->pxNextFreeBlock = pxPreviousBlock->pxNextFreeBlock; + pxPreviousBlock->pxNextFreeBlock = pxNewBlockLink; } else { @@ -354,7 +376,7 @@ void * pvPortMalloc( size_t xWantedSize ) /* The block is being returned - it is allocated and owned by * the application and has no "next" block. */ - pxBlock->xBlockSize |= xBlockAllocatedBit; + secureheapALLOCATE_BLOCK( pxBlock ); pxBlock->pxNextFreeBlock = NULL; } else @@ -375,17 +397,17 @@ void * pvPortMalloc( size_t xWantedSize ) traceMALLOC( pvReturn, xWantedSize ); #if ( secureconfigUSE_MALLOC_FAILED_HOOK == 1 ) + { + if( pvReturn == NULL ) { - if( pvReturn == NULL ) - { - extern void vApplicationMallocFailedHook( void ); - vApplicationMallocFailedHook(); - } - else - { - mtCOVERAGE_TEST_MARKER(); - } + extern void vApplicationMallocFailedHook( void ); + vApplicationMallocFailedHook(); } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } #endif /* if ( secureconfigUSE_MALLOC_FAILED_HOOK == 1 ) */ secureportASSERT( ( ( ( size_t ) pvReturn ) & ( size_t ) secureportBYTE_ALIGNMENT_MASK ) == 0 ); @@ -408,16 +430,16 @@ void vPortFree( void * pv ) pxLink = ( void * ) puc; /* Check the block is actually allocated. */ - secureportASSERT( ( pxLink->xBlockSize & xBlockAllocatedBit ) != 0 ); + secureportASSERT( secureheapBLOCK_IS_ALLOCATED( pxLink ) != 0 ); secureportASSERT( pxLink->pxNextFreeBlock == NULL ); - if( ( pxLink->xBlockSize & xBlockAllocatedBit ) != 0 ) + if( secureheapBLOCK_IS_ALLOCATED( pxLink ) != 0 ) { if( pxLink->pxNextFreeBlock == NULL ) { /* The block is being returned to the heap - it is no longer * allocated. */ - pxLink->xBlockSize &= ~xBlockAllocatedBit; + secureheapFREE_BLOCK( pxLink ); secureportDISABLE_NON_SECURE_INTERRUPTS(); { diff --git a/Source/portable/IAR/ARM_CM35P/secure/secure_heap.h b/Source/portable/IAR/ARM_CM35P/secure/secure_heap.h index 75c9cb00b..cf5551046 100644 --- a/Source/portable/IAR/ARM_CM35P/secure/secure_heap.h +++ b/Source/portable/IAR/ARM_CM35P/secure/secure_heap.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/Source/portable/IAR/ARM_CM35P/secure/secure_init.c b/Source/portable/IAR/ARM_CM35P/secure/secure_init.c index f93bfce95..66d35eccc 100644 --- a/Source/portable/IAR/ARM_CM35P/secure/secure_init.c +++ b/Source/portable/IAR/ARM_CM35P/secure/secure_init.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -93,7 +93,7 @@ secureportNON_SECURE_CALLABLE void SecureInit_EnableNSFPUAccess( void ) * permitted. CP11 should be programmed to the same value as CP10. */ *( secureinitNSACR ) |= ( secureinitNSACR_CP10_MASK | secureinitNSACR_CP11_MASK ); - /* LSPENS = 0 ==> LSPEN is writable fron non-secure state. This ensures + /* LSPENS = 0 ==> LSPEN is writable from non-secure state. This ensures * that we can enable/disable lazy stacking in port.c file. */ *( secureinitFPCCR ) &= ~( secureinitFPCCR_LSPENS_MASK ); diff --git a/Source/portable/IAR/ARM_CM35P/secure/secure_init.h b/Source/portable/IAR/ARM_CM35P/secure/secure_init.h index e6c9da0b4..6404c5cc4 100644 --- a/Source/portable/IAR/ARM_CM35P/secure/secure_init.h +++ b/Source/portable/IAR/ARM_CM35P/secure/secure_init.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/Source/portable/IAR/ARM_CM35P/secure/secure_port_macros.h b/Source/portable/IAR/ARM_CM35P/secure/secure_port_macros.h index d7ac5833c..085108cc1 100644 --- a/Source/portable/IAR/ARM_CM35P/secure/secure_port_macros.h +++ b/Source/portable/IAR/ARM_CM35P/secure/secure_port_macros.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/Source/portable/IAR/ARM_CM35P_NTZ/non_secure/mpu_wrappers_v2_asm.S b/Source/portable/IAR/ARM_CM35P_NTZ/non_secure/mpu_wrappers_v2_asm.S index ef180bd91..b4f1fbc3b 100644 --- a/Source/portable/IAR/ARM_CM35P_NTZ/non_secure/mpu_wrappers_v2_asm.S +++ b/Source/portable/IAR/ARM_CM35P_NTZ/non_secure/mpu_wrappers_v2_asm.S @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -196,20 +196,6 @@ MPU_uxTaskGetNumberOfTasks: svc #SYSTEM_CALL_uxTaskGetNumberOfTasks /*-----------------------------------------------------------*/ - PUBLIC MPU_pcTaskGetName -MPU_pcTaskGetName: - push {r0} - mrs r0, control - tst r0, #1 - bne MPU_pcTaskGetName_Unpriv - MPU_pcTaskGetName_Priv: - pop {r0} - b MPU_pcTaskGetNameImpl - MPU_pcTaskGetName_Unpriv: - pop {r0} - svc #SYSTEM_CALL_pcTaskGetName -/*-----------------------------------------------------------*/ - PUBLIC MPU_ulTaskGetRunTimeCounter MPU_ulTaskGetRunTimeCounter: push {r0} @@ -742,24 +728,18 @@ MPU_xTimerGetTimerDaemonTaskHandle: svc #SYSTEM_CALL_xTimerGetTimerDaemonTaskHandle /*-----------------------------------------------------------*/ - PUBLIC MPU_xTimerGenericCommandEntry -MPU_xTimerGenericCommandEntry: + PUBLIC MPU_xTimerGenericCommandFromTaskEntry +MPU_xTimerGenericCommandFromTaskEntry: push {r0} - /* This function can be called from ISR also and therefore, we need a check - * to take privileged path, if called from ISR. */ - mrs r0, ipsr - cmp r0, #0 - bne MPU_xTimerGenericCommand_Priv mrs r0, control tst r0, #1 - beq MPU_xTimerGenericCommand_Priv - MPU_xTimerGenericCommand_Unpriv: + bne MPU_xTimerGenericCommandFromTask_Unpriv + MPU_xTimerGenericCommandFromTask_Priv: pop {r0} - svc #SYSTEM_CALL_xTimerGenericCommand - MPU_xTimerGenericCommand_Priv: + b MPU_xTimerGenericCommandFromTaskImpl + MPU_xTimerGenericCommandFromTask_Unpriv: pop {r0} - b MPU_xTimerGenericCommandPrivImpl - + svc #SYSTEM_CALL_xTimerGenericCommandFromTask /*-----------------------------------------------------------*/ PUBLIC MPU_pcTimerGetName @@ -1089,10 +1069,6 @@ MPU_xTaskGetTickCountImpl: MPU_uxTaskGetNumberOfTasksImpl: b MPU_uxTaskGetNumberOfTasksImpl - PUBWEAK MPU_pcTaskGetNameImpl -MPU_pcTaskGetNameImpl: - b MPU_pcTaskGetNameImpl - PUBWEAK MPU_ulTaskGetRunTimeCounterImpl MPU_ulTaskGetRunTimeCounterImpl: b MPU_ulTaskGetRunTimeCounterImpl @@ -1245,9 +1221,9 @@ MPU_xTimerIsTimerActiveImpl: MPU_xTimerGetTimerDaemonTaskHandleImpl: b MPU_xTimerGetTimerDaemonTaskHandleImpl - PUBWEAK MPU_xTimerGenericCommandPrivImpl -MPU_xTimerGenericCommandPrivImpl: - b MPU_xTimerGenericCommandPrivImpl + PUBWEAK MPU_xTimerGenericCommandFromTaskImpl +MPU_xTimerGenericCommandFromTaskImpl: + b MPU_xTimerGenericCommandFromTaskImpl PUBWEAK MPU_pcTimerGetNameImpl MPU_pcTimerGetNameImpl: diff --git a/Source/portable/IAR/ARM_CM35P_NTZ/non_secure/port.c b/Source/portable/IAR/ARM_CM35P_NTZ/non_secure/port.c index 9712ac353..230fe5fc2 100644 --- a/Source/portable/IAR/ARM_CM35P_NTZ/non_secure/port.c +++ b/Source/portable/IAR/ARM_CM35P_NTZ/non_secure/port.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -68,6 +68,22 @@ #if ( ( configRUN_FREERTOS_SECURE_ONLY == 1 ) && ( configENABLE_TRUSTZONE == 1 ) ) #error TrustZone needs to be disabled in order to run FreeRTOS on the Secure Side. #endif + +/** + * Cortex-M23 does not have non-secure PSPLIM. We should use PSPLIM on Cortex-M23 + * only when FreeRTOS runs on secure side. + */ +#if ( ( portHAS_ARMV8M_MAIN_EXTENSION == 0 ) && ( configRUN_FREERTOS_SECURE_ONLY == 0 ) ) + #define portUSE_PSPLIM_REGISTER 0 +#else + #define portUSE_PSPLIM_REGISTER 1 +#endif +/*-----------------------------------------------------------*/ + +/** + * @brief Prototype of all Interrupt Service Routines (ISRs). + */ +typedef void ( * portISR_t )( void ); /*-----------------------------------------------------------*/ /** @@ -91,10 +107,18 @@ /** * @brief Constants required to manipulate the SCB. */ -#define portSCB_SYS_HANDLER_CTRL_STATE_REG ( *( volatile uint32_t * ) 0xe000ed24 ) +#define portSCB_VTOR_REG ( *( ( portISR_t ** ) 0xe000ed08 ) ) +#define portSCB_SYS_HANDLER_CTRL_STATE_REG ( *( ( volatile uint32_t * ) 0xe000ed24 ) ) #define portSCB_MEM_FAULT_ENABLE_BIT ( 1UL << 16UL ) /*-----------------------------------------------------------*/ +/** + * @brief Constants used to check the installation of the FreeRTOS interrupt handlers. + */ +#define portVECTOR_INDEX_SVC ( 11 ) +#define portVECTOR_INDEX_PENDSV ( 14 ) +/*-----------------------------------------------------------*/ + /** * @brief Constants required to check the validity of an interrupt priority. */ @@ -111,8 +135,8 @@ /** * @brief Constants used during system call enter and exit. */ -#define portPSR_STACK_PADDING_MASK ( 1UL << 9UL ) -#define portEXC_RETURN_STACK_FRAME_TYPE_MASK ( 1UL << 4UL ) +#define portPSR_STACK_PADDING_MASK ( 1UL << 9UL ) +#define portEXC_RETURN_STACK_FRAME_TYPE_MASK ( 1UL << 4UL ) /*-----------------------------------------------------------*/ /** @@ -134,81 +158,81 @@ /** * @brief Offsets in the stack to the parameters when inside the SVC handler. */ -#define portOFFSET_TO_LR ( 5 ) -#define portOFFSET_TO_PC ( 6 ) -#define portOFFSET_TO_PSR ( 7 ) +#define portOFFSET_TO_LR ( 5 ) +#define portOFFSET_TO_PC ( 6 ) +#define portOFFSET_TO_PSR ( 7 ) /*-----------------------------------------------------------*/ /** * @brief Constants required to manipulate the MPU. */ -#define portMPU_TYPE_REG ( *( ( volatile uint32_t * ) 0xe000ed90 ) ) -#define portMPU_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed94 ) ) -#define portMPU_RNR_REG ( *( ( volatile uint32_t * ) 0xe000ed98 ) ) +#define portMPU_TYPE_REG ( *( ( volatile uint32_t * ) 0xe000ed90 ) ) +#define portMPU_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed94 ) ) +#define portMPU_RNR_REG ( *( ( volatile uint32_t * ) 0xe000ed98 ) ) -#define portMPU_RBAR_REG ( *( ( volatile uint32_t * ) 0xe000ed9c ) ) -#define portMPU_RLAR_REG ( *( ( volatile uint32_t * ) 0xe000eda0 ) ) +#define portMPU_RBAR_REG ( *( ( volatile uint32_t * ) 0xe000ed9c ) ) +#define portMPU_RLAR_REG ( *( ( volatile uint32_t * ) 0xe000eda0 ) ) -#define portMPU_RBAR_A1_REG ( *( ( volatile uint32_t * ) 0xe000eda4 ) ) -#define portMPU_RLAR_A1_REG ( *( ( volatile uint32_t * ) 0xe000eda8 ) ) +#define portMPU_RBAR_A1_REG ( *( ( volatile uint32_t * ) 0xe000eda4 ) ) +#define portMPU_RLAR_A1_REG ( *( ( volatile uint32_t * ) 0xe000eda8 ) ) -#define portMPU_RBAR_A2_REG ( *( ( volatile uint32_t * ) 0xe000edac ) ) -#define portMPU_RLAR_A2_REG ( *( ( volatile uint32_t * ) 0xe000edb0 ) ) +#define portMPU_RBAR_A2_REG ( *( ( volatile uint32_t * ) 0xe000edac ) ) +#define portMPU_RLAR_A2_REG ( *( ( volatile uint32_t * ) 0xe000edb0 ) ) -#define portMPU_RBAR_A3_REG ( *( ( volatile uint32_t * ) 0xe000edb4 ) ) -#define portMPU_RLAR_A3_REG ( *( ( volatile uint32_t * ) 0xe000edb8 ) ) +#define portMPU_RBAR_A3_REG ( *( ( volatile uint32_t * ) 0xe000edb4 ) ) +#define portMPU_RLAR_A3_REG ( *( ( volatile uint32_t * ) 0xe000edb8 ) ) -#define portMPU_MAIR0_REG ( *( ( volatile uint32_t * ) 0xe000edc0 ) ) -#define portMPU_MAIR1_REG ( *( ( volatile uint32_t * ) 0xe000edc4 ) ) +#define portMPU_MAIR0_REG ( *( ( volatile uint32_t * ) 0xe000edc0 ) ) +#define portMPU_MAIR1_REG ( *( ( volatile uint32_t * ) 0xe000edc4 ) ) -#define portMPU_RBAR_ADDRESS_MASK ( 0xffffffe0 ) /* Must be 32-byte aligned. */ -#define portMPU_RLAR_ADDRESS_MASK ( 0xffffffe0 ) /* Must be 32-byte aligned. */ +#define portMPU_RBAR_ADDRESS_MASK ( 0xffffffe0 ) /* Must be 32-byte aligned. */ +#define portMPU_RLAR_ADDRESS_MASK ( 0xffffffe0 ) /* Must be 32-byte aligned. */ -#define portMPU_RBAR_ACCESS_PERMISSIONS_MASK ( 3UL << 1UL ) +#define portMPU_RBAR_ACCESS_PERMISSIONS_MASK ( 3UL << 1UL ) -#define portMPU_MAIR_ATTR0_POS ( 0UL ) -#define portMPU_MAIR_ATTR0_MASK ( 0x000000ff ) +#define portMPU_MAIR_ATTR0_POS ( 0UL ) +#define portMPU_MAIR_ATTR0_MASK ( 0x000000ff ) -#define portMPU_MAIR_ATTR1_POS ( 8UL ) -#define portMPU_MAIR_ATTR1_MASK ( 0x0000ff00 ) +#define portMPU_MAIR_ATTR1_POS ( 8UL ) +#define portMPU_MAIR_ATTR1_MASK ( 0x0000ff00 ) -#define portMPU_MAIR_ATTR2_POS ( 16UL ) -#define portMPU_MAIR_ATTR2_MASK ( 0x00ff0000 ) +#define portMPU_MAIR_ATTR2_POS ( 16UL ) +#define portMPU_MAIR_ATTR2_MASK ( 0x00ff0000 ) -#define portMPU_MAIR_ATTR3_POS ( 24UL ) -#define portMPU_MAIR_ATTR3_MASK ( 0xff000000 ) +#define portMPU_MAIR_ATTR3_POS ( 24UL ) +#define portMPU_MAIR_ATTR3_MASK ( 0xff000000 ) -#define portMPU_MAIR_ATTR4_POS ( 0UL ) -#define portMPU_MAIR_ATTR4_MASK ( 0x000000ff ) +#define portMPU_MAIR_ATTR4_POS ( 0UL ) +#define portMPU_MAIR_ATTR4_MASK ( 0x000000ff ) -#define portMPU_MAIR_ATTR5_POS ( 8UL ) -#define portMPU_MAIR_ATTR5_MASK ( 0x0000ff00 ) +#define portMPU_MAIR_ATTR5_POS ( 8UL ) +#define portMPU_MAIR_ATTR5_MASK ( 0x0000ff00 ) -#define portMPU_MAIR_ATTR6_POS ( 16UL ) -#define portMPU_MAIR_ATTR6_MASK ( 0x00ff0000 ) +#define portMPU_MAIR_ATTR6_POS ( 16UL ) +#define portMPU_MAIR_ATTR6_MASK ( 0x00ff0000 ) -#define portMPU_MAIR_ATTR7_POS ( 24UL ) -#define portMPU_MAIR_ATTR7_MASK ( 0xff000000 ) +#define portMPU_MAIR_ATTR7_POS ( 24UL ) +#define portMPU_MAIR_ATTR7_MASK ( 0xff000000 ) -#define portMPU_RLAR_ATTR_INDEX0 ( 0UL << 1UL ) -#define portMPU_RLAR_ATTR_INDEX1 ( 1UL << 1UL ) -#define portMPU_RLAR_ATTR_INDEX2 ( 2UL << 1UL ) -#define portMPU_RLAR_ATTR_INDEX3 ( 3UL << 1UL ) -#define portMPU_RLAR_ATTR_INDEX4 ( 4UL << 1UL ) -#define portMPU_RLAR_ATTR_INDEX5 ( 5UL << 1UL ) -#define portMPU_RLAR_ATTR_INDEX6 ( 6UL << 1UL ) -#define portMPU_RLAR_ATTR_INDEX7 ( 7UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX0 ( 0UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX1 ( 1UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX2 ( 2UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX3 ( 3UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX4 ( 4UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX5 ( 5UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX6 ( 6UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX7 ( 7UL << 1UL ) -#define portMPU_RLAR_REGION_ENABLE ( 1UL ) +#define portMPU_RLAR_REGION_ENABLE ( 1UL ) /* Enable privileged access to unmapped region. */ -#define portMPU_PRIV_BACKGROUND_ENABLE_BIT ( 1UL << 2UL ) +#define portMPU_PRIV_BACKGROUND_ENABLE_BIT ( 1UL << 2UL ) /* Enable MPU. */ -#define portMPU_ENABLE_BIT ( 1UL << 0UL ) +#define portMPU_ENABLE_BIT ( 1UL << 0UL ) /* Expected value of the portMPU_TYPE register. */ -#define portEXPECTED_MPU_TYPE_VALUE ( configTOTAL_MPU_REGIONS << 8UL ) +#define portEXPECTED_MPU_TYPE_VALUE ( configTOTAL_MPU_REGIONS << 8UL ) /* Extract first address of the MPU region as encoded in the * RBAR (Region Base Address Register) value. */ @@ -448,13 +472,13 @@ portDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIV #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) - /** - * @brief Sets up the task stack so that upon returning from - * SVC, the task stack is used again. - * - * @param pulSystemCallStack The current SP when the SVC was raised. - * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler. - */ +/** + * @brief Sets up the task stack so that upon returning from + * SVC, the task stack is used again. + * + * @param pulSystemCallStack The current SP when the SVC was raised. + * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler. + */ void vSystemCallExit( uint32_t * pulSystemCallStack, uint32_t ulLR ) PRIVILEGED_FUNCTION; @@ -462,11 +486,11 @@ portDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIV #if ( configENABLE_MPU == 1 ) - /** - * @brief Checks whether or not the calling task is privileged. - * - * @return pdTRUE if the calling task is privileged, pdFALSE otherwise. - */ +/** + * @brief Checks whether or not the calling task is privileged. + * + * @return pdTRUE if the calling task is privileged, pdFALSE otherwise. + */ BaseType_t xPortIsTaskPrivileged( void ) PRIVILEGED_FUNCTION; #endif /* configENABLE_MPU == 1 */ @@ -501,13 +525,13 @@ PRIVILEGED_DATA static volatile uint32_t ulCriticalNesting = 0xaaaaaaaaUL; * FreeRTOS API functions are not called from interrupts that have been assigned * a priority above configMAX_SYSCALL_INTERRUPT_PRIORITY. */ -#if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) ) +#if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) static uint8_t ucMaxSysCallPriority = 0; static uint32_t ulMaxPRIGROUPValue = 0; static const volatile uint8_t * const pcInterruptPriorityRegisters = ( const volatile uint8_t * ) portNVIC_IP_REGISTERS_OFFSET_16; -#endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) ) */ +#endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */ #if ( configUSE_TICKLESS_IDLE == 1 ) @@ -760,8 +784,15 @@ __attribute__( ( weak ) ) void vPortSetupTimerInterrupt( void ) /* PRIVILEGED_FU } #endif /* configUSE_TICKLESS_IDLE */ - /* Stop and reset the SysTick. */ - portNVIC_SYSTICK_CTRL_REG = 0UL; + /* Stop and reset SysTick. + * + * QEMU versions older than 7.0.0 contain a bug which causes an error if we + * enable SysTick without first selecting a valid clock source. We trigger + * the bug if we change clock sources from a clock with a zero clock period + * to one with a nonzero clock period and enable Systick at the same time. + * So we configure the CLKSOURCE bit here, prior to setting the ENABLE bit. + * This workaround avoids the bug in QEMU versions older than 7.0.0. */ + portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT_CONFIG; portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL; /* Configure SysTick to interrupt at the requested rate. */ @@ -819,6 +850,7 @@ static void prvTaskExitError( void ) static void prvSetupMPU( void ) /* PRIVILEGED_FUNCTION */ { #if defined( __ARMCC_VERSION ) + /* Declaration when these variable are defined in code instead of being * exported from linker scripts. */ extern uint32_t * __privileged_functions_start__; @@ -972,13 +1004,19 @@ void SysTick_Handler( void ) /* PRIVILEGED_FUNCTION */ uint32_t ulPreviousMask; ulPreviousMask = portSET_INTERRUPT_MASK_FROM_ISR(); + traceISR_ENTER(); { /* Increment the RTOS tick. */ if( xTaskIncrementTick() != pdFALSE ) { + traceISR_EXIT_TO_SCHEDULER(); /* Pend a context switch. */ portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; } + else + { + traceISR_EXIT(); + } } portCLEAR_INTERRUPT_MASK_FROM_ISR( ulPreviousMask ); } @@ -988,6 +1026,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO { #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) ) #if defined( __ARMCC_VERSION ) + /* Declaration when these variable are defined in code instead of being * exported from linker scripts. */ extern uint32_t * __syscalls_flash_start__; @@ -1083,18 +1122,24 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO vRestoreContextOfFirstTask(); break; - #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) ) - case portSVC_RAISE_PRIVILEGE: + #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) ) + case portSVC_RAISE_PRIVILEGE: - /* Only raise the privilege, if the svc was raised from any of - * the system calls. */ - if( ( ulPC >= ( uint32_t ) __syscalls_flash_start__ ) && - ( ulPC <= ( uint32_t ) __syscalls_flash_end__ ) ) - { - vRaisePrivilege(); - } - break; - #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) */ + /* Only raise the privilege, if the svc was raised from any of + * the system calls. */ + if( ( ulPC >= ( uint32_t ) __syscalls_flash_start__ ) && + ( ulPC <= ( uint32_t ) __syscalls_flash_end__ ) ) + { + vRaisePrivilege(); + } + break; + #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) */ + + #if ( configENABLE_MPU == 1 ) + case portSVC_YIELD: + vPortYield(); + break; + #endif /* configENABLE_MPU == 1 */ default: /* Incorrect SVC call. */ @@ -1154,12 +1199,11 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO { /* Extended frame i.e. FPU in use. */ ulStackFrameSize = 26; - __asm volatile - ( + __asm volatile ( " vpush {s0} \n" /* Trigger lazy stacking. */ " vpop {s0} \n" /* Nullify the affect of the above instruction. */ ::: "memory" - ); + ); } else { @@ -1171,7 +1215,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO { ulStackFrameSize = 8; } - #endif /* if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */ + #endif /* configENABLE_FPU || configENABLE_MVE */ /* Make space on the system call stack for the stack frame. */ pulSystemCallStack = pulSystemCallStack - ulStackFrameSize; @@ -1187,18 +1231,24 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO * point (i.e. the caller of the MPU_). We need to restore it * when we exit from the system call. */ pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry = pulTaskStack[ portOFFSET_TO_LR ]; - /* Store the value of the PSPLIM register before the SVC was raised. * We need to restore it when we exit from the system call. */ - __asm volatile ( "mrs %0, psplim" : "=r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) ); + #if ( portUSE_PSPLIM_REGISTER == 1 ) + { + __asm volatile ( "mrs %0, psplim" : "=r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) ); + } + #endif /* Use the pulSystemCallStack in thread mode. */ __asm volatile ( "msr psp, %0" : : "r" ( pulSystemCallStack ) ); - __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) ); + #if ( portUSE_PSPLIM_REGISTER == 1 ) + { + __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) ); + } + #endif /* Start executing the system call upon returning from this handler. */ pulSystemCallStack[ portOFFSET_TO_PC ] = uxSystemCallImplementations[ ucSystemCallNumber ]; - /* Raise a request to exit from the system call upon finishing the * system call. */ pulSystemCallStack[ portOFFSET_TO_LR ] = ( uint32_t ) vRequestSystemCallExit; @@ -1224,14 +1274,13 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO pulSystemCallStack[ portOFFSET_TO_PSR ] &= ( ~portPSR_STACK_PADDING_MASK ); /* Raise the privilege for the duration of the system call. */ - __asm volatile - ( + __asm volatile ( " mrs r0, control \n" /* Obtain current control value. */ " movs r1, #1 \n" /* r1 = 1. */ " bics r0, r1 \n" /* Clear nPRIV bit. */ " msr control, r0 \n" /* Write back new control value. */ ::: "r0", "r1", "memory" - ); + ); } } @@ -1293,12 +1342,11 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO { /* Extended frame i.e. FPU in use. */ ulStackFrameSize = 26; - __asm volatile - ( + __asm volatile ( " vpush {s0} \n" /* Trigger lazy stacking. */ " vpop {s0} \n" /* Nullify the affect of the above instruction. */ ::: "memory" - ); + ); } else { @@ -1310,7 +1358,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO { ulStackFrameSize = 8; } - #endif /* if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */ + #endif /* configENABLE_FPU || configENABLE_MVE */ /* Make space on the task stack for the stack frame. */ pulTaskStack = pulTaskStack - ulStackFrameSize; @@ -1332,7 +1380,11 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO /* Restore the PSPLIM register to what it was at the time of * system call entry. */ - __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) ); + #if ( portUSE_PSPLIM_REGISTER == 1 ) + { + __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) ); + } + #endif /* If the hardware used padding to force the stack pointer * to be double word aligned, set the stacked xPSR bit[9], @@ -1350,14 +1402,13 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO pxMpuSettings->xSystemCallStackInfo.pulTaskStack = NULL; /* Drop the privilege before returning to the thread mode. */ - __asm volatile - ( + __asm volatile ( " mrs r0, control \n" /* Obtain current control value. */ " movs r1, #1 \n" /* r1 = 1. */ " orrs r0, r1 \n" /* Set nPRIV bit. */ " msr control, r0 \n" /* Write back new control value. */ ::: "r0", "r1", "memory" - ); + ); } } @@ -1410,21 +1461,21 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO xMPUSettings->ulContext[ ulIndex ] = 0x11111111; /* r11. */ ulIndex++; - xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pvParameters; /* r0. */ + xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pvParameters; /* r0. */ ulIndex++; - xMPUSettings->ulContext[ ulIndex ] = 0x01010101; /* r1. */ + xMPUSettings->ulContext[ ulIndex ] = 0x01010101; /* r1. */ ulIndex++; - xMPUSettings->ulContext[ ulIndex ] = 0x02020202; /* r2. */ + xMPUSettings->ulContext[ ulIndex ] = 0x02020202; /* r2. */ ulIndex++; - xMPUSettings->ulContext[ ulIndex ] = 0x03030303; /* r3. */ + xMPUSettings->ulContext[ ulIndex ] = 0x03030303; /* r3. */ ulIndex++; - xMPUSettings->ulContext[ ulIndex ] = 0x12121212; /* r12. */ + xMPUSettings->ulContext[ ulIndex ] = 0x12121212; /* r12. */ ulIndex++; xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portTASK_RETURN_ADDRESS; /* LR. */ ulIndex++; - xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxCode; /* PC. */ + xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxCode; /* PC. */ ulIndex++; - xMPUSettings->ulContext[ ulIndex ] = portINITIAL_XPSR; /* xPSR. */ + xMPUSettings->ulContext[ ulIndex ] = portINITIAL_XPSR; /* xPSR. */ ulIndex++; #if ( configENABLE_TRUSTZONE == 1 ) @@ -1435,8 +1486,9 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO #endif /* configENABLE_TRUSTZONE */ xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) ( pxTopOfStack - 8 ); /* PSP with the hardware saved stack. */ ulIndex++; - xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxEndOfStack; /* PSPLIM. */ + xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxEndOfStack; /* PSPLIM. */ ulIndex++; + if( xRunPrivileged == pdTRUE ) { xMPUSettings->ulTaskFlags |= portTASK_IS_PRIVILEGED_FLAG; @@ -1449,6 +1501,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portINITIAL_CONTROL_UNPRIVILEGED; /* CONTROL. */ ulIndex++; } + xMPUSettings->ulContext[ ulIndex ] = portINITIAL_EXC_RETURN; /* LR (EXC_RETURN). */ ulIndex++; @@ -1483,7 +1536,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO * interrupt. */ #if ( portPRELOAD_REGISTERS == 0 ) { - pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */ + pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */ *pxTopOfStack = portINITIAL_XPSR; /* xPSR. */ pxTopOfStack--; *pxTopOfStack = ( StackType_t ) pxCode; /* PC. */ @@ -1505,7 +1558,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO } #else /* portPRELOAD_REGISTERS */ { - pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */ + pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */ *pxTopOfStack = portINITIAL_XPSR; /* xPSR. */ pxTopOfStack--; *pxTopOfStack = ( StackType_t ) pxCode; /* PC. */ @@ -1540,7 +1593,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO pxTopOfStack--; *pxTopOfStack = portINITIAL_EXC_RETURN; /* EXC_RETURN. */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */ + *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */ #if ( configENABLE_TRUSTZONE == 1 ) { @@ -1559,22 +1612,52 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */ { - #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) ) + /* An application can install FreeRTOS interrupt handlers in one of the + * folllowing ways: + * 1. Direct Routing - Install the functions SVC_Handler and PendSV_Handler + * for SVCall and PendSV interrupts respectively. + * 2. Indirect Routing - Install separate handlers for SVCall and PendSV + * interrupts and route program control from those handlers to + * SVC_Handler and PendSV_Handler functions. + * + * Applications that use Indirect Routing must set + * configCHECK_HANDLER_INSTALLATION to 0 in their FreeRTOSConfig.h. Direct + * routing, which is validated here when configCHECK_HANDLER_INSTALLATION + * is 1, should be preferred when possible. */ + #if ( configCHECK_HANDLER_INSTALLATION == 1 ) + { + const portISR_t * const pxVectorTable = portSCB_VTOR_REG; + + /* Validate that the application has correctly installed the FreeRTOS + * handlers for SVCall and PendSV interrupts. We do not check the + * installation of the SysTick handler because the application may + * choose to drive the RTOS tick using a timer other than the SysTick + * timer by overriding the weak function vPortSetupTimerInterrupt(). + * + * Assertion failures here indicate incorrect installation of the + * FreeRTOS handlers. For help installing the FreeRTOS handlers, see + * https://www.FreeRTOS.org/FAQHelp.html. + * + * Systems with a configurable address for the interrupt vector table + * can also encounter assertion failures or even system faults here if + * VTOR is not set correctly to point to the application's vector table. */ + configASSERT( pxVectorTable[ portVECTOR_INDEX_SVC ] == SVC_Handler ); + configASSERT( pxVectorTable[ portVECTOR_INDEX_PENDSV ] == PendSV_Handler ); + } + #endif /* configCHECK_HANDLER_INSTALLATION */ + + #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) { - volatile uint32_t ulOriginalPriority; volatile uint32_t ulImplementedPrioBits = 0; volatile uint8_t ucMaxPriorityValue; /* Determine the maximum priority from which ISR safe FreeRTOS API - * functions can be called. ISR safe functions are those that end in - * "FromISR". FreeRTOS maintains separate thread and ISR API functions to + * functions can be called. ISR safe functions are those that end in + * "FromISR". FreeRTOS maintains separate thread and ISR API functions to * ensure interrupt entry is as fast and simple as possible. * - * Save the interrupt priority value that is about to be clobbered. */ - ulOriginalPriority = portNVIC_SHPR2_REG; - - /* Determine the number of priority bits available. First write to all - * possible bits. */ + * First, determine the number of priority bits available. Write to all + * possible bits in the priority setting for SVCall. */ portNVIC_SHPR2_REG = 0xFF000000; /* Read the value back to see how many bits stuck. */ @@ -1593,11 +1676,10 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */ /* Check that the bits not implemented in hardware are zero in * configMAX_SYSCALL_INTERRUPT_PRIORITY. */ - configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( ~ucMaxPriorityValue ) ) == 0U ); + configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( uint8_t ) ( ~( uint32_t ) ucMaxPriorityValue ) ) == 0U ); /* Calculate the maximum acceptable priority group value for the number * of bits read back. */ - while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE ) { ulImplementedPrioBits++; @@ -1635,16 +1717,14 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */ * register. */ ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT; ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK; - - /* Restore the clobbered interrupt priority register to its original - * value. */ - portNVIC_SHPR2_REG = ulOriginalPriority; } - #endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) ) */ + #endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */ - /* Make PendSV, CallSV and SysTick the same priority as the kernel. */ + /* Make PendSV and SysTick the lowest priority interrupts, and make SVCall + * the highest priority. */ portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI; portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI; + portNVIC_SHPR2_REG = 0; #if ( configENABLE_MPU == 1 ) { @@ -1701,6 +1781,7 @@ void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */ int32_t lIndex = 0; #if defined( __ARMCC_VERSION ) + /* Declaration when these variable are defined in code instead of being * exported from linker scripts. */ extern uint32_t * __privileged_sram_start__; @@ -1886,7 +1967,7 @@ BaseType_t xPortIsInsideInterrupt( void ) } /*-----------------------------------------------------------*/ -#if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) ) +#if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) void vPortValidateInterruptPriority( void ) { @@ -1944,7 +2025,7 @@ BaseType_t xPortIsInsideInterrupt( void ) configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue ); } -#endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) ) */ +#endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */ /*-----------------------------------------------------------*/ #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) diff --git a/Source/portable/IAR/ARM_CM35P_NTZ/non_secure/portasm.h b/Source/portable/IAR/ARM_CM35P_NTZ/non_secure/portasm.h index f64ceb525..c6d2ebd58 100644 --- a/Source/portable/IAR/ARM_CM35P_NTZ/non_secure/portasm.h +++ b/Source/portable/IAR/ARM_CM35P_NTZ/non_secure/portasm.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/Source/portable/IAR/ARM_CM35P_NTZ/non_secure/portasm.s b/Source/portable/IAR/ARM_CM35P_NTZ/non_secure/portasm.s index 00ee5a5cb..cb3ad91f9 100644 --- a/Source/portable/IAR/ARM_CM35P_NTZ/non_secure/portasm.s +++ b/Source/portable/IAR/ARM_CM35P_NTZ/non_secure/portasm.s @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/Source/portable/IAR/ARM_CM35P_NTZ/non_secure/portmacro.h b/Source/portable/IAR/ARM_CM35P_NTZ/non_secure/portmacro.h index 247468478..e24fabc75 100644 --- a/Source/portable/IAR/ARM_CM35P_NTZ/non_secure/portmacro.h +++ b/Source/portable/IAR/ARM_CM35P_NTZ/non_secure/portmacro.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -48,16 +48,16 @@ /** * Architecture specifics. */ -#define portARCH_NAME "Cortex-M35P" -#define portHAS_BASEPRI 1 -#define portDONT_DISCARD __root +#define portARCH_NAME "Cortex-M35P" +#define portHAS_ARMV8M_MAIN_EXTENSION 1 +#define portDONT_DISCARD __root /*-----------------------------------------------------------*/ /* ARMv8-M common port configurations. */ #include "portmacrocommon.h" /*-----------------------------------------------------------*/ -#if( configTOTAL_MPU_REGIONS == 16 ) +#if ( configTOTAL_MPU_REGIONS == 16 ) #error 16 MPU regions are not yet supported for this port. #endif /*-----------------------------------------------------------*/ @@ -65,8 +65,8 @@ /** * @brief Critical section management. */ -#define portDISABLE_INTERRUPTS() ulSetInterruptMask() -#define portENABLE_INTERRUPTS() vClearInterruptMask( 0 ) +#define portDISABLE_INTERRUPTS() ulSetInterruptMask() +#define portENABLE_INTERRUPTS() vClearInterruptMask( 0 ) /*-----------------------------------------------------------*/ /* Suppress warnings that are generated by the IAR tools, but cannot be fixed in diff --git a/Source/portable/IAR/ARM_CM35P_NTZ/non_secure/portmacrocommon.h b/Source/portable/IAR/ARM_CM35P_NTZ/non_secure/portmacrocommon.h index 6f666da22..33f21d85b 100644 --- a/Source/portable/IAR/ARM_CM35P_NTZ/non_secure/portmacrocommon.h +++ b/Source/portable/IAR/ARM_CM35P_NTZ/non_secure/portmacrocommon.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -117,7 +117,7 @@ extern uint32_t ulSetInterruptMask( void ) /* __attribute__(( naked )) PRIVILEGE extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */; #if ( configENABLE_TRUSTZONE == 1 ) - extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize ); /* __attribute__ (( naked )) */ + extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize ); /* __attribute__ (( naked )) */ extern void vPortFreeSecureContext( uint32_t * pulTCB ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */; #endif /* configENABLE_TRUSTZONE */ @@ -188,13 +188,13 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P #if ( configENABLE_MPU == 1 ) - /** - * @brief Settings to define an MPU region. - */ +/** + * @brief Settings to define an MPU region. + */ typedef struct MPURegionSettings { - uint32_t ulRBAR; /**< RBAR for the region. */ - uint32_t ulRLAR; /**< RLAR for the region. */ + uint32_t ulRBAR; /**< RBAR for the region. */ + uint32_t ulRLAR; /**< RLAR for the region. */ } MPURegionSettings_t; #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) @@ -203,9 +203,9 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P #error configSYSTEM_CALL_STACK_SIZE must be defined to the desired size of the system call stack in words for using MPU wrappers v2. #endif - /** - * @brief System call stack. - */ +/** + * @brief System call stack. + */ typedef struct SYSTEM_CALL_STACK_INFO { uint32_t ulSystemCallStackBuffer[ configSYSTEM_CALL_STACK_SIZE ]; @@ -218,74 +218,74 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P #endif /* configUSE_MPU_WRAPPERS_V1 == 0 */ - /** - * @brief MPU settings as stored in the TCB. - */ +/** + * @brief MPU settings as stored in the TCB. + */ #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) - #if( configENABLE_TRUSTZONE == 1 ) + #if ( configENABLE_TRUSTZONE == 1 ) - /* - * +-----------+---------------+----------+-----------------+------------------------------+-----+ - * | s16-s31 | s0-s15, FPSCR | r4-r11 | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, | | - * | | | | PC, xPSR | CONTROL, EXC_RETURN | | - * +-----------+---------------+----------+-----------------+------------------------------+-----+ - * - * <-----------><--------------><---------><----------------><-----------------------------><----> - * 16 16 8 8 5 1 - */ - #define MAX_CONTEXT_SIZE 54 +/* + * +-----------+---------------+----------+-----------------+------------------------------+-----+ + * | s16-s31 | s0-s15, FPSCR | r4-r11 | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, | | + * | | | | PC, xPSR | CONTROL, EXC_RETURN | | + * +-----------+---------------+----------+-----------------+------------------------------+-----+ + * + * <-----------><--------------><---------><----------------><-----------------------------><----> + * 16 16 8 8 5 1 + */ + #define MAX_CONTEXT_SIZE 54 #else /* #if( configENABLE_TRUSTZONE == 1 ) */ - /* - * +-----------+---------------+----------+-----------------+----------------------+-----+ - * | s16-s31 | s0-s15, FPSCR | r4-r11 | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL | | - * | | | | PC, xPSR | EXC_RETURN | | - * +-----------+---------------+----------+-----------------+----------------------+-----+ - * - * <-----------><--------------><---------><----------------><---------------------><----> - * 16 16 8 8 4 1 - */ - #define MAX_CONTEXT_SIZE 53 +/* + * +-----------+---------------+----------+-----------------+----------------------+-----+ + * | s16-s31 | s0-s15, FPSCR | r4-r11 | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL | | + * | | | | PC, xPSR | EXC_RETURN | | + * +-----------+---------------+----------+-----------------+----------------------+-----+ + * + * <-----------><--------------><---------><----------------><---------------------><----> + * 16 16 8 8 4 1 + */ + #define MAX_CONTEXT_SIZE 53 #endif /* #if( configENABLE_TRUSTZONE == 1 ) */ #else /* #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */ - #if( configENABLE_TRUSTZONE == 1 ) + #if ( configENABLE_TRUSTZONE == 1 ) - /* - * +----------+-----------------+------------------------------+-----+ - * | r4-r11 | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, | | - * | | PC, xPSR | CONTROL, EXC_RETURN | | - * +----------+-----------------+------------------------------+-----+ - * - * <---------><----------------><------------------------------><----> - * 8 8 5 1 - */ - #define MAX_CONTEXT_SIZE 22 +/* + * +----------+-----------------+------------------------------+-----+ + * | r4-r11 | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, | | + * | | PC, xPSR | CONTROL, EXC_RETURN | | + * +----------+-----------------+------------------------------+-----+ + * + * <---------><----------------><------------------------------><----> + * 8 8 5 1 + */ + #define MAX_CONTEXT_SIZE 22 #else /* #if( configENABLE_TRUSTZONE == 1 ) */ - /* - * +----------+-----------------+----------------------+-----+ - * | r4-r11 | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL | | - * | | PC, xPSR | EXC_RETURN | | - * +----------+-----------------+----------------------+-----+ - * - * <---------><----------------><----------------------><----> - * 8 8 4 1 - */ - #define MAX_CONTEXT_SIZE 21 +/* + * +----------+-----------------+----------------------+-----+ + * | r4-r11 | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL | | + * | | PC, xPSR | EXC_RETURN | | + * +----------+-----------------+----------------------+-----+ + * + * <---------><----------------><----------------------><----> + * 8 8 4 1 + */ + #define MAX_CONTEXT_SIZE 21 #endif /* #if( configENABLE_TRUSTZONE == 1 ) */ #endif /* #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */ - /* Flags used for xMPU_SETTINGS.ulTaskFlags member. */ - #define portSTACK_FRAME_HAS_PADDING_FLAG ( 1UL << 0UL ) - #define portTASK_IS_PRIVILEGED_FLAG ( 1UL << 1UL ) +/* Flags used for xMPU_SETTINGS.ulTaskFlags member. */ + #define portSTACK_FRAME_HAS_PADDING_FLAG ( 1UL << 0UL ) + #define portTASK_IS_PRIVILEGED_FLAG ( 1UL << 1UL ) /* Size of an Access Control List (ACL) entry in bits. */ #define portACL_ENTRY_SIZE_BITS ( 32U ) @@ -313,7 +313,7 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P * system calls. */ #ifdef configASSERT - #if ( portHAS_BASEPRI == 1 ) + #if ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) void vPortValidateInterruptPriority( void ); #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() vPortValidateInterruptPriority() #endif @@ -333,12 +333,29 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P /** * @brief Scheduler utilities. */ -#define portYIELD() vPortYield() +#if ( configENABLE_MPU == 1 ) + #define portYIELD() __asm volatile ( "svc %0" ::"i" ( portSVC_YIELD ) : "memory" ) + #define portYIELD_WITHIN_API() vPortYield() +#else + #define portYIELD() vPortYield() + #define portYIELD_WITHIN_API() vPortYield() +#endif + #define portNVIC_INT_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed04 ) ) #define portNVIC_PENDSVSET_BIT ( 1UL << 28UL ) -#define portEND_SWITCHING_ISR( xSwitchRequired ) \ - do { if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; } \ - while( 0 ) +#define portEND_SWITCHING_ISR( xSwitchRequired ) \ + do \ + { \ + if( xSwitchRequired ) \ + { \ + traceISR_EXIT_TO_SCHEDULER(); \ + portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; \ + } \ + else \ + { \ + traceISR_EXIT(); \ + } \ + } while( 0 ) #define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x ) /*-----------------------------------------------------------*/ @@ -424,12 +441,12 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P extern BaseType_t xPortIsTaskPrivileged( void ); - /** - * @brief Checks whether or not the calling task is privileged. - * - * @return pdTRUE if the calling task is privileged, pdFALSE otherwise. - */ - #define portIS_TASK_PRIVILEGED() xPortIsTaskPrivileged() +/** + * @brief Checks whether or not the calling task is privileged. + * + * @return pdTRUE if the calling task is privileged, pdFALSE otherwise. + */ + #define portIS_TASK_PRIVILEGED() xPortIsTaskPrivileged() #endif /* configENABLE_MPU == 1 */ /*-----------------------------------------------------------*/ @@ -440,6 +457,56 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P #define portMEMORY_BARRIER() __asm volatile ( "" ::: "memory" ) /*-----------------------------------------------------------*/ +/* Select correct value of configUSE_PORT_OPTIMISED_TASK_SELECTION + * based on whether or not Mainline extension is implemented. */ +#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION + #if ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) + #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1 + #else + #define configUSE_PORT_OPTIMISED_TASK_SELECTION 0 + #endif +#endif /* #ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION */ + +/** + * @brief Port-optimised task selection. + */ +#if ( configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 ) + +/** + * @brief Count the number of leading zeros in a 32-bit value. + */ + static portFORCE_INLINE uint32_t ulPortCountLeadingZeros( uint32_t ulBitmap ) + { + uint32_t ulReturn; + + __asm volatile ( "clz %0, %1" : "=r" ( ulReturn ) : "r" ( ulBitmap ) : "memory" ); + + return ulReturn; + } + +/* Check the configuration. */ + #if ( configMAX_PRIORITIES > 32 ) + #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 different priorities as tasks that share a priority will time slice. + #endif + + #if ( portHAS_ARMV8M_MAIN_EXTENSION == 0 ) + #error ARMv8-M baseline implementations (such as Cortex-M23) do not support port-optimised task selection. Please set configUSE_PORT_OPTIMISED_TASK_SELECTION to 0 or leave it undefined. + #endif + +/** + * @brief Store/clear the ready priorities in a bit map. + */ + #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) ) + #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) ) + +/** + * @brief Get the priority of the highest-priority task that is ready to execute. + */ + #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - ulPortCountLeadingZeros( ( uxReadyPriorities ) ) ) + +#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */ +/*-----------------------------------------------------------*/ + /* *INDENT-OFF* */ #ifdef __cplusplus } diff --git a/Source/portable/IAR/ARM_CM4F/port.c b/Source/portable/IAR/ARM_CM4F/port.c index 692400b2a..e2c5a2269 100644 --- a/Source/portable/IAR/ARM_CM4F/port.c +++ b/Source/portable/IAR/ARM_CM4F/port.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -45,10 +45,14 @@ #error configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to 0. See http: /*www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */ #endif +/* Prototype of all Interrupt Service Routines (ISRs). */ +typedef void ( * portISR_t )( void ); + /* Constants required to manipulate the core. Registers first... */ #define portNVIC_SYSTICK_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000e010 ) ) #define portNVIC_SYSTICK_LOAD_REG ( *( ( volatile uint32_t * ) 0xe000e014 ) ) #define portNVIC_SYSTICK_CURRENT_VALUE_REG ( *( ( volatile uint32_t * ) 0xe000e018 ) ) +#define portNVIC_SHPR2_REG ( *( ( volatile uint32_t * ) 0xe000ed1c ) ) #define portNVIC_SHPR3_REG ( *( ( volatile uint32_t * ) 0xe000ed20 ) ) /* ...then bits in the registers. */ #define portNVIC_SYSTICK_CLK_BIT ( 1UL << 2UL ) @@ -69,6 +73,11 @@ #define portNVIC_PENDSV_PRI ( ( ( uint32_t ) portMIN_INTERRUPT_PRIORITY ) << 16UL ) #define portNVIC_SYSTICK_PRI ( ( ( uint32_t ) portMIN_INTERRUPT_PRIORITY ) << 24UL ) +/* Constants used to check the installation of the FreeRTOS interrupt handlers. */ +#define portSCB_VTOR_REG ( *( ( portISR_t ** ) 0xE000ED08 ) ) +#define portVECTOR_INDEX_SVC ( 11 ) +#define portVECTOR_INDEX_PENDSV ( 14 ) + /* Constants required to check the validity of an interrupt priority. */ #define portFIRST_USER_INTERRUPT_NUMBER ( 16 ) #define portNVIC_IP_REGISTERS_OFFSET_16 ( 0xE000E3F0 ) @@ -141,6 +150,11 @@ extern void vPortEnableVFP( void ); */ static void prvTaskExitError( void ); +/* + * FreeRTOS handlers implemented in assembly. + */ +extern void vPortSVCHandler( void ); +extern void xPortPendSVHandler( void ); /*-----------------------------------------------------------*/ /* Each task maintains its own interrupt status in the critical nesting @@ -246,6 +260,40 @@ BaseType_t xPortStartScheduler( void ) configASSERT( portCPUID != portCORTEX_M7_r0p1_ID ); configASSERT( portCPUID != portCORTEX_M7_r0p0_ID ); + /* An application can install FreeRTOS interrupt handlers in one of the + * folllowing ways: + * 1. Direct Routing - Install the functions vPortSVCHandler and + * xPortPendSVHandler for SVCall and PendSV interrupts respectively. + * 2. Indirect Routing - Install separate handlers for SVCall and PendSV + * interrupts and route program control from those handlers to + * vPortSVCHandler and xPortPendSVHandler functions. + * + * Applications that use Indirect Routing must set + * configCHECK_HANDLER_INSTALLATION to 0 in their FreeRTOSConfig.h. Direct + * routing, which is validated here when configCHECK_HANDLER_INSTALLATION + * is 1, should be preferred when possible. */ + #if ( configCHECK_HANDLER_INSTALLATION == 1 ) + { + const portISR_t * const pxVectorTable = portSCB_VTOR_REG; + + /* Validate that the application has correctly installed the FreeRTOS + * handlers for SVCall and PendSV interrupts. We do not check the + * installation of the SysTick handler because the application may + * choose to drive the RTOS tick using a timer other than the SysTick + * timer by overriding the weak function vPortSetupTimerInterrupt(). + * + * Assertion failures here indicate incorrect installation of the + * FreeRTOS handlers. For help installing the FreeRTOS handlers, see + * https://www.FreeRTOS.org/FAQHelp.html. + * + * Systems with a configurable address for the interrupt vector table + * can also encounter assertion failures or even system faults here if + * VTOR is not set correctly to point to the application's vector table. */ + configASSERT( pxVectorTable[ portVECTOR_INDEX_SVC ] == vPortSVCHandler ); + configASSERT( pxVectorTable[ portVECTOR_INDEX_PENDSV ] == xPortPendSVHandler ); + } + #endif /* configCHECK_HANDLER_INSTALLATION */ + #if ( configASSERT_DEFINED == 1 ) { volatile uint8_t ucOriginalPriority; @@ -281,7 +329,7 @@ BaseType_t xPortStartScheduler( void ) /* Check that the bits not implemented in hardware are zero in * configMAX_SYSCALL_INTERRUPT_PRIORITY. */ - configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( ~ucMaxPriorityValue ) ) == 0U ); + configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( uint8_t ) ( ~( uint32_t ) ucMaxPriorityValue ) ) == 0U ); /* Calculate the maximum acceptable priority group value for the number * of bits read back. */ @@ -295,22 +343,22 @@ BaseType_t xPortStartScheduler( void ) if( ulImplementedPrioBits == 8 ) { /* When the hardware implements 8 priority bits, there is no way for - * the software to configure PRIGROUP to not have sub-priorities. As - * a result, the least significant bit is always used for sub-priority - * and there are 128 preemption priorities and 2 sub-priorities. - * - * This may cause some confusion in some cases - for example, if - * configMAX_SYSCALL_INTERRUPT_PRIORITY is set to 5, both 5 and 4 - * priority interrupts will be masked in Critical Sections as those - * are at the same preemption priority. This may appear confusing as - * 4 is higher (numerically lower) priority than - * configMAX_SYSCALL_INTERRUPT_PRIORITY and therefore, should not - * have been masked. Instead, if we set configMAX_SYSCALL_INTERRUPT_PRIORITY - * to 4, this confusion does not happen and the behaviour remains the same. - * - * The following assert ensures that the sub-priority bit in the - * configMAX_SYSCALL_INTERRUPT_PRIORITY is clear to avoid the above mentioned - * confusion. */ + * the software to configure PRIGROUP to not have sub-priorities. As + * a result, the least significant bit is always used for sub-priority + * and there are 128 preemption priorities and 2 sub-priorities. + * + * This may cause some confusion in some cases - for example, if + * configMAX_SYSCALL_INTERRUPT_PRIORITY is set to 5, both 5 and 4 + * priority interrupts will be masked in Critical Sections as those + * are at the same preemption priority. This may appear confusing as + * 4 is higher (numerically lower) priority than + * configMAX_SYSCALL_INTERRUPT_PRIORITY and therefore, should not + * have been masked. Instead, if we set configMAX_SYSCALL_INTERRUPT_PRIORITY + * to 4, this confusion does not happen and the behaviour remains the same. + * + * The following assert ensures that the sub-priority bit in the + * configMAX_SYSCALL_INTERRUPT_PRIORITY is clear to avoid the above mentioned + * confusion. */ configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & 0x1U ) == 0U ); ulMaxPRIGROUPValue = 0; } @@ -330,9 +378,11 @@ BaseType_t xPortStartScheduler( void ) } #endif /* configASSERT_DEFINED */ - /* Make PendSV and SysTick the lowest priority interrupts. */ + /* Make PendSV and SysTick the lowest priority interrupts, and make SVCall + * the highest priority. */ portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI; portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI; + portNVIC_SHPR2_REG = 0; /* Start the timer that generates the tick ISR. Interrupts are disabled * here already. */ @@ -399,14 +449,21 @@ void xPortSysTickHandler( void ) * save and then restore the interrupt mask value as its value is already * known. */ portDISABLE_INTERRUPTS(); + traceISR_ENTER(); { /* Increment the RTOS tick. */ if( xTaskIncrementTick() != pdFALSE ) { + traceISR_EXIT_TO_SCHEDULER(); + /* A context switch is required. Context switching is performed in * the PendSV interrupt. Pend the PendSV interrupt. */ portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; } + else + { + traceISR_EXIT(); + } } portENABLE_INTERRUPTS(); } diff --git a/Source/portable/IAR/ARM_CM4F/portasm.s b/Source/portable/IAR/ARM_CM4F/portasm.s index 89b72b259..2239796e0 100644 --- a/Source/portable/IAR/ARM_CM4F/portasm.s +++ b/Source/portable/IAR/ARM_CM4F/portasm.s @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/Source/portable/IAR/ARM_CM4F/portmacro.h b/Source/portable/IAR/ARM_CM4F/portmacro.h index 92cb7c770..65275a1c3 100644 --- a/Source/portable/IAR/ARM_CM4F/portmacro.h +++ b/Source/portable/IAR/ARM_CM4F/portmacro.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -27,7 +27,7 @@ */ #ifndef PORTMACRO_H - #define PORTMACRO_H +#define PORTMACRO_H /* *INDENT-OFF* */ #ifdef __cplusplus @@ -46,50 +46,50 @@ */ /* IAR includes. */ - #include +#include /* Type definitions. */ - #define portCHAR char - #define portFLOAT float - #define portDOUBLE double - #define portLONG long - #define portSHORT short - #define portSTACK_TYPE uint32_t - #define portBASE_TYPE long - - typedef portSTACK_TYPE StackType_t; - typedef long BaseType_t; - typedef unsigned long UBaseType_t; - - #if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS ) - typedef uint16_t TickType_t; - #define portMAX_DELAY ( TickType_t ) 0xffff - #elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS ) - typedef uint32_t TickType_t; - #define portMAX_DELAY ( TickType_t ) 0xffffffffUL +#define portCHAR char +#define portFLOAT float +#define portDOUBLE double +#define portLONG long +#define portSHORT short +#define portSTACK_TYPE uint32_t +#define portBASE_TYPE long + +typedef portSTACK_TYPE StackType_t; +typedef long BaseType_t; +typedef unsigned long UBaseType_t; + +#if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS ) + typedef uint16_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffff +#elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS ) + typedef uint32_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffffffffUL /* 32-bit tick type on a 32-bit architecture, so reads of the tick count do * not need to be guarded with a critical section. */ - #define portTICK_TYPE_IS_ATOMIC 1 - #else - #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width. - #endif + #define portTICK_TYPE_IS_ATOMIC 1 +#else + #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width. +#endif /*-----------------------------------------------------------*/ /* Architecture specifics. */ - #define portSTACK_GROWTH ( -1 ) - #define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) - #define portBYTE_ALIGNMENT 8 +#define portSTACK_GROWTH ( -1 ) +#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) +#define portBYTE_ALIGNMENT 8 /*-----------------------------------------------------------*/ /* Compiler directives. */ - #define portWEAK_SYMBOL __attribute__( ( weak ) ) +#define portWEAK_SYMBOL __attribute__( ( weak ) ) /*-----------------------------------------------------------*/ /* Scheduler utilities. */ - #define portYIELD() \ +#define portYIELD() \ { \ /* Set a PendSV to request a context switch. */ \ portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; \ @@ -97,112 +97,124 @@ __ISB(); \ } - #define portNVIC_INT_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed04 ) ) - #define portNVIC_PENDSVSET_BIT ( 1UL << 28UL ) - #define portEND_SWITCHING_ISR( xSwitchRequired ) do { if( xSwitchRequired != pdFALSE ) portYIELD(); } while( 0 ) - #define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x ) +#define portNVIC_INT_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed04 ) ) +#define portNVIC_PENDSVSET_BIT ( 1UL << 28UL ) +#define portEND_SWITCHING_ISR( xSwitchRequired ) \ + do \ + { \ + if( xSwitchRequired != pdFALSE ) \ + { \ + traceISR_EXIT_TO_SCHEDULER(); \ + portYIELD(); \ + } \ + else \ + { \ + traceISR_EXIT(); \ + } \ + } while( 0 ) +#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x ) /*-----------------------------------------------------------*/ /* Architecture specific optimisations. */ - #ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION - #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1 - #endif +#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION + #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1 +#endif - #if ( configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 ) +#if ( configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 ) /* Check the configuration. */ - #if ( configMAX_PRIORITIES > 32 ) - #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice. - #endif + #if ( configMAX_PRIORITIES > 32 ) + #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice. + #endif /* Store/clear the ready priorities in a bit map. */ - #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) ) - #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) ) + #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) ) + #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) ) /*-----------------------------------------------------------*/ - #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - ( ( uint32_t ) __CLZ( ( uxReadyPriorities ) ) ) ) + #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - ( ( uint32_t ) __CLZ( ( uxReadyPriorities ) ) ) ) - #endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */ +#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */ /*-----------------------------------------------------------*/ /* Critical section management. */ - extern void vPortEnterCritical( void ); - extern void vPortExitCritical( void ); +extern void vPortEnterCritical( void ); +extern void vPortExitCritical( void ); - #define portDISABLE_INTERRUPTS() \ +#define portDISABLE_INTERRUPTS() \ { \ __set_BASEPRI( configMAX_SYSCALL_INTERRUPT_PRIORITY ); \ __DSB(); \ __ISB(); \ } - #define portENABLE_INTERRUPTS() __set_BASEPRI( 0 ) - #define portENTER_CRITICAL() vPortEnterCritical() - #define portEXIT_CRITICAL() vPortExitCritical() - #define portSET_INTERRUPT_MASK_FROM_ISR() __get_BASEPRI(); portDISABLE_INTERRUPTS() - #define portCLEAR_INTERRUPT_MASK_FROM_ISR( x ) __set_BASEPRI( x ) +#define portENABLE_INTERRUPTS() __set_BASEPRI( 0 ) +#define portENTER_CRITICAL() vPortEnterCritical() +#define portEXIT_CRITICAL() vPortExitCritical() +#define portSET_INTERRUPT_MASK_FROM_ISR() __get_BASEPRI(); portDISABLE_INTERRUPTS() +#define portCLEAR_INTERRUPT_MASK_FROM_ISR( x ) __set_BASEPRI( x ) /*-----------------------------------------------------------*/ /* Tickless idle/low power functionality. */ - #ifndef portSUPPRESS_TICKS_AND_SLEEP - extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime ); - #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime ) vPortSuppressTicksAndSleep( xExpectedIdleTime ) - #endif +#ifndef portSUPPRESS_TICKS_AND_SLEEP + extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime ); + #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime ) vPortSuppressTicksAndSleep( xExpectedIdleTime ) +#endif /*-----------------------------------------------------------*/ /* Task function macros as described on the FreeRTOS.org WEB site. These are * not necessary for to use this port. They are defined so the common demo files * (which build with all the ports) will build. */ - #define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters ) - #define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters ) +#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters ) +#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters ) /*-----------------------------------------------------------*/ - #ifdef configASSERT - void vPortValidateInterruptPriority( void ); - #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() vPortValidateInterruptPriority() - #endif +#ifdef configASSERT + void vPortValidateInterruptPriority( void ); + #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() vPortValidateInterruptPriority() +#endif /* portNOP() is not required by this port. */ - #define portNOP() +#define portNOP() - #define portINLINE __inline +#define portINLINE __inline - #ifndef portFORCE_INLINE - #define portFORCE_INLINE inline __attribute__( ( always_inline ) ) - #endif +#ifndef portFORCE_INLINE + #define portFORCE_INLINE inline __attribute__( ( always_inline ) ) +#endif /*-----------------------------------------------------------*/ - portFORCE_INLINE static BaseType_t xPortIsInsideInterrupt( void ) +portFORCE_INLINE static BaseType_t xPortIsInsideInterrupt( void ) +{ + uint32_t ulCurrentInterrupt; + BaseType_t xReturn; + + /* Obtain the number of the currently executing interrupt. */ + __asm volatile ( "mrs %0, ipsr" : "=r" ( ulCurrentInterrupt )::"memory" ); + + if( ulCurrentInterrupt == 0 ) + { + xReturn = pdFALSE; + } + else { - uint32_t ulCurrentInterrupt; - BaseType_t xReturn; - - /* Obtain the number of the currently executing interrupt. */ - __asm volatile ( "mrs %0, ipsr" : "=r" ( ulCurrentInterrupt )::"memory" ); - - if( ulCurrentInterrupt == 0 ) - { - xReturn = pdFALSE; - } - else - { - xReturn = pdTRUE; - } - - return xReturn; + xReturn = pdTRUE; } + return xReturn; +} + /*-----------------------------------------------------------*/ /* Suppress warnings that are generated by the IAR tools, but cannot be fixed in * the source code because to do so would cause other compilers to generate * warnings. */ - #pragma diag_suppress=Pe191 - #pragma diag_suppress=Pa082 +#pragma diag_suppress=Pe191 +#pragma diag_suppress=Pa082 /* *INDENT-OFF* */ #ifdef __cplusplus diff --git a/Source/portable/IAR/ARM_CM4F_MPU/mpu_wrappers_v2_asm.S b/Source/portable/IAR/ARM_CM4F_MPU/mpu_wrappers_v2_asm.S index 276a1cf00..ff5a5878c 100644 --- a/Source/portable/IAR/ARM_CM4F_MPU/mpu_wrappers_v2_asm.S +++ b/Source/portable/IAR/ARM_CM4F_MPU/mpu_wrappers_v2_asm.S @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -200,20 +200,6 @@ MPU_uxTaskGetNumberOfTasks: svc #SYSTEM_CALL_uxTaskGetNumberOfTasks /*-----------------------------------------------------------*/ - PUBLIC MPU_pcTaskGetName -MPU_pcTaskGetName: - push {r0} - mrs r0, control - tst r0, #1 - bne MPU_pcTaskGetName_Unpriv - MPU_pcTaskGetName_Priv: - pop {r0} - b MPU_pcTaskGetNameImpl - MPU_pcTaskGetName_Unpriv: - pop {r0} - svc #SYSTEM_CALL_pcTaskGetName -/*-----------------------------------------------------------*/ - PUBLIC MPU_ulTaskGetRunTimeCounter MPU_ulTaskGetRunTimeCounter: push {r0} @@ -746,24 +732,18 @@ MPU_xTimerGetTimerDaemonTaskHandle: svc #SYSTEM_CALL_xTimerGetTimerDaemonTaskHandle /*-----------------------------------------------------------*/ - PUBLIC MPU_xTimerGenericCommandEntry -MPU_xTimerGenericCommandEntry: + PUBLIC MPU_xTimerGenericCommandFromTaskEntry +MPU_xTimerGenericCommandFromTaskEntry: push {r0} - /* This function can be called from ISR also and therefore, we need a check - * to take privileged path, if called from ISR. */ - mrs r0, ipsr - cmp r0, #0 - bne MPU_xTimerGenericCommand_Priv mrs r0, control tst r0, #1 - beq MPU_xTimerGenericCommand_Priv - MPU_xTimerGenericCommand_Unpriv: + bne MPU_xTimerGenericCommandFromTask_Unpriv + MPU_xTimerGenericCommandFromTask_Priv: pop {r0} - svc #SYSTEM_CALL_xTimerGenericCommand - MPU_xTimerGenericCommand_Priv: + b MPU_xTimerGenericCommandFromTaskImpl + MPU_xTimerGenericCommandFromTask_Unpriv: pop {r0} - b MPU_xTimerGenericCommandPrivImpl - + svc #SYSTEM_CALL_xTimerGenericCommandFromTask /*-----------------------------------------------------------*/ PUBLIC MPU_pcTimerGetName @@ -1093,10 +1073,6 @@ MPU_xTaskGetTickCountImpl: MPU_uxTaskGetNumberOfTasksImpl: b MPU_uxTaskGetNumberOfTasksImpl - PUBWEAK MPU_pcTaskGetNameImpl -MPU_pcTaskGetNameImpl: - b MPU_pcTaskGetNameImpl - PUBWEAK MPU_ulTaskGetRunTimeCounterImpl MPU_ulTaskGetRunTimeCounterImpl: b MPU_ulTaskGetRunTimeCounterImpl @@ -1249,9 +1225,9 @@ MPU_xTimerIsTimerActiveImpl: MPU_xTimerGetTimerDaemonTaskHandleImpl: b MPU_xTimerGetTimerDaemonTaskHandleImpl - PUBWEAK MPU_xTimerGenericCommandPrivImpl -MPU_xTimerGenericCommandPrivImpl: - b MPU_xTimerGenericCommandPrivImpl + PUBWEAK MPU_xTimerGenericCommandFromTaskImpl +MPU_xTimerGenericCommandFromTaskImpl: + b MPU_xTimerGenericCommandFromTaskImpl PUBWEAK MPU_pcTimerGetNameImpl MPU_pcTimerGetNameImpl: diff --git a/Source/portable/IAR/ARM_CM4F_MPU/port.c b/Source/portable/IAR/ARM_CM4F_MPU/port.c index 518dfbccd..f32bbd5e0 100644 --- a/Source/portable/IAR/ARM_CM4F_MPU/port.c +++ b/Source/portable/IAR/ARM_CM4F_MPU/port.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -69,6 +69,9 @@ #define configALLOW_UNPRIVILEGED_CRITICAL_SECTIONS 1 #endif +/* Prototype of all Interrupt Service Routines (ISRs). */ +typedef void ( * portISR_t )( void ); + /* Constants required to manipulate the core. Registers first... */ #define portNVIC_SYSTICK_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000e010 ) ) #define portNVIC_SYSTICK_LOAD_REG ( *( ( volatile uint32_t * ) 0xe000e014 ) ) @@ -108,7 +111,11 @@ #define portMIN_INTERRUPT_PRIORITY ( 255UL ) #define portNVIC_PENDSV_PRI ( ( ( uint32_t ) portMIN_INTERRUPT_PRIORITY ) << 16UL ) #define portNVIC_SYSTICK_PRI ( ( ( uint32_t ) portMIN_INTERRUPT_PRIORITY ) << 24UL ) -#define portNVIC_SVC_PRI ( ( ( uint32_t ) configMAX_SYSCALL_INTERRUPT_PRIORITY - 1UL ) << 24UL ) + +/* Constants used to check the installation of the FreeRTOS interrupt handlers. */ +#define portSCB_VTOR_REG ( *( ( portISR_t ** ) 0xE000ED08 ) ) +#define portVECTOR_INDEX_SVC ( 11 ) +#define portVECTOR_INDEX_PENDSV ( 14 ) /* Constants required to check the validity of an interrupt priority. */ #define portFIRST_USER_INTERRUPT_NUMBER ( 16 ) @@ -258,13 +265,13 @@ extern void vPortRestoreContextOfFirstTask( void ) PRIVILEGED_FUNCTION; #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) - /** - * @brief Sets up the task stack so that upon returning from - * SVC, the task stack is used again. - * - * @param pulSystemCallStack The current SP when the SVC was raised. - * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler. - */ +/** + * @brief Sets up the task stack so that upon returning from + * SVC, the task stack is used again. + * + * @param pulSystemCallStack The current SP when the SVC was raised. + * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler. + */ void vSystemCallExit( uint32_t * pulSystemCallStack, uint32_t ulLR ) PRIVILEGED_FUNCTION; @@ -277,6 +284,16 @@ extern void vPortRestoreContextOfFirstTask( void ) PRIVILEGED_FUNCTION; */ BaseType_t xPortIsTaskPrivileged( void ) PRIVILEGED_FUNCTION; +/** + * @brief Make a task unprivileged. + */ +void vPortSwitchToUserMode( void ); + +/* + * FreeRTOS handlers implemented in assembly. + */ +extern void vPortSVCHandler( void ) PRIVILEGED_FUNCTION; +extern void xPortPendSVHandler( void ) PRIVILEGED_FUNCTION; /*-----------------------------------------------------------*/ /* Each task maintains its own interrupt status in the critical nesting @@ -321,28 +338,29 @@ StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, } else { - xMPUSettings->ulTaskFlags &= ( ~portTASK_IS_PRIVILEGED_FLAG ); + xMPUSettings->ulTaskFlags &= ( ~( portTASK_IS_PRIVILEGED_FLAG ) ); xMPUSettings->ulContext[ 0 ] = portINITIAL_CONTROL_IF_UNPRIVILEGED; } - xMPUSettings->ulContext[ 1 ] = 0x04040404; /* r4. */ - xMPUSettings->ulContext[ 2 ] = 0x05050505; /* r5. */ - xMPUSettings->ulContext[ 3 ] = 0x06060606; /* r6. */ - xMPUSettings->ulContext[ 4 ] = 0x07070707; /* r7. */ - xMPUSettings->ulContext[ 5 ] = 0x08080808; /* r8. */ - xMPUSettings->ulContext[ 6 ] = 0x09090909; /* r9. */ - xMPUSettings->ulContext[ 7 ] = 0x10101010; /* r10. */ - xMPUSettings->ulContext[ 8 ] = 0x11111111; /* r11. */ - xMPUSettings->ulContext[ 9 ] = portINITIAL_EXC_RETURN; /* EXC_RETURN. */ - - xMPUSettings->ulContext[ 10 ] = ( uint32_t ) ( pxTopOfStack - 8 ); /* PSP with the hardware saved stack. */ - xMPUSettings->ulContext[ 11 ] = ( uint32_t ) pvParameters; /* r0. */ - xMPUSettings->ulContext[ 12 ] = 0x01010101; /* r1. */ - xMPUSettings->ulContext[ 13 ] = 0x02020202; /* r2. */ - xMPUSettings->ulContext[ 14 ] = 0x03030303; /* r3. */ - xMPUSettings->ulContext[ 15 ] = 0x12121212; /* r12. */ - xMPUSettings->ulContext[ 16 ] = 0; /* LR. */ + + xMPUSettings->ulContext[ 1 ] = 0x04040404; /* r4. */ + xMPUSettings->ulContext[ 2 ] = 0x05050505; /* r5. */ + xMPUSettings->ulContext[ 3 ] = 0x06060606; /* r6. */ + xMPUSettings->ulContext[ 4 ] = 0x07070707; /* r7. */ + xMPUSettings->ulContext[ 5 ] = 0x08080808; /* r8. */ + xMPUSettings->ulContext[ 6 ] = 0x09090909; /* r9. */ + xMPUSettings->ulContext[ 7 ] = 0x10101010; /* r10. */ + xMPUSettings->ulContext[ 8 ] = 0x11111111; /* r11. */ + xMPUSettings->ulContext[ 9 ] = portINITIAL_EXC_RETURN; /* EXC_RETURN. */ + + xMPUSettings->ulContext[ 10 ] = ( uint32_t ) ( pxTopOfStack - 8 ); /* PSP with the hardware saved stack. */ + xMPUSettings->ulContext[ 11 ] = ( uint32_t ) pvParameters; /* r0. */ + xMPUSettings->ulContext[ 12 ] = 0x01010101; /* r1. */ + xMPUSettings->ulContext[ 13 ] = 0x02020202; /* r2. */ + xMPUSettings->ulContext[ 14 ] = 0x03030303; /* r3. */ + xMPUSettings->ulContext[ 15 ] = 0x12121212; /* r12. */ + xMPUSettings->ulContext[ 16 ] = 0; /* LR. */ xMPUSettings->ulContext[ 17 ] = ( ( uint32_t ) pxCode ) & portSTART_ADDRESS_MASK; /* PC. */ - xMPUSettings->ulContext[ 18 ] = portINITIAL_XPSR; /* xPSR. */ + xMPUSettings->ulContext[ 18 ] = portINITIAL_XPSR; /* xPSR. */ #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) { @@ -378,7 +396,6 @@ void vPortSVCHandler_C( uint32_t * pulParam ) /* PRIVILEGED_FUNCTION */ switch( ucSVCNumber ) { case portSVC_START_SCHEDULER: - portNVIC_SHPR2_REG |= portNVIC_SVC_PRI; vPortRestoreContextOfFirstTask(); break; @@ -481,12 +498,11 @@ void vPortSVCHandler_C( uint32_t * pulParam ) /* PRIVILEGED_FUNCTION */ { /* Extended frame i.e. FPU in use. */ ulStackFrameSize = 26; - __asm volatile - ( + __asm volatile ( " vpush {s0} \n" /* Trigger lazy stacking. */ " vpop {s0} \n" /* Nullify the affect of the above instruction. */ ::: "memory" - ); + ); } else { @@ -507,13 +523,12 @@ void vPortSVCHandler_C( uint32_t * pulParam ) /* PRIVILEGED_FUNCTION */ __asm volatile ( "msr psp, %0" : : "r" ( pulSystemCallStack ) ); /* Raise the privilege for the duration of the system call. */ - __asm volatile - ( + __asm volatile ( " mrs r1, control \n" /* Obtain current control value. */ " bic r1, #1 \n" /* Clear nPRIV bit. */ " msr control, r1 \n" /* Write back new control value. */ ::: "r1", "memory" - ); + ); /* Remember the location where we should copy the stack frame when we exit from * the system call. */ @@ -528,7 +543,6 @@ void vPortSVCHandler_C( uint32_t * pulParam ) /* PRIVILEGED_FUNCTION */ /* Start executing the system call upon returning from this handler. */ pulSystemCallStack[ portOFFSET_TO_PC ] = uxSystemCallImplementations[ ucSystemCallNumber ]; - /* Raise a request to exit from the system call upon finishing the * system call. */ pulSystemCallStack[ portOFFSET_TO_LR ] = ( uint32_t ) vRequestSystemCallExit; @@ -607,12 +621,11 @@ void vPortSVCHandler_C( uint32_t * pulParam ) /* PRIVILEGED_FUNCTION */ { /* Extended frame i.e. FPU in use. */ ulStackFrameSize = 26; - __asm volatile - ( + __asm volatile ( " vpush {s0} \n" /* Trigger lazy stacking. */ " vpop {s0} \n" /* Nullify the affect of the above instruction. */ ::: "memory" - ); + ); } else { @@ -633,13 +646,12 @@ void vPortSVCHandler_C( uint32_t * pulParam ) /* PRIVILEGED_FUNCTION */ __asm volatile ( "msr psp, %0" : : "r" ( pulTaskStack ) ); /* Drop the privilege before returning to the thread mode. */ - __asm volatile - ( + __asm volatile ( " mrs r1, control \n" /* Obtain current control value. */ " orr r1, #1 \n" /* Set nPRIV bit. */ " msr control, r1 \n" /* Write back new control value. */ ::: "r1", "memory" - ); + ); /* Return to the caller of the System Call entry point (i.e. the * caller of the MPU_). */ @@ -681,6 +693,19 @@ BaseType_t xPortIsTaskPrivileged( void ) /* PRIVILEGED_FUNCTION */ } /*-----------------------------------------------------------*/ +void vPortSwitchToUserMode( void ) +{ + /* Load the current task's MPU settings from its TCB. */ + xMPU_SETTINGS * xTaskMpuSettings = xTaskGetMPUSettings( NULL ); + + /* Mark the task as unprivileged. */ + xTaskMpuSettings->ulTaskFlags &= ( ~( portTASK_IS_PRIVILEGED_FLAG ) ); + + /* Lower the processor's privilege level. */ + vResetPrivilege(); +} +/*-----------------------------------------------------------*/ + /* * See header file for description. */ @@ -691,6 +716,7 @@ BaseType_t xPortStartScheduler( void ) #if ( configENABLE_ERRATA_837070_WORKAROUND == 1 ) configASSERT( ( portCPUID == portCORTEX_M7_r0p1_ID ) || ( portCPUID == portCORTEX_M7_r0p0_ID ) ); #else + /* When using this port on a Cortex-M7 r0p0 or r0p1 core, define * configENABLE_ERRATA_837070_WORKAROUND to 1 in your * FreeRTOSConfig.h. */ @@ -698,6 +724,40 @@ BaseType_t xPortStartScheduler( void ) configASSERT( portCPUID != portCORTEX_M7_r0p0_ID ); #endif + /* An application can install FreeRTOS interrupt handlers in one of the + * folllowing ways: + * 1. Direct Routing - Install the functions vPortSVCHandler and + * xPortPendSVHandler for SVCall and PendSV interrupts respectively. + * 2. Indirect Routing - Install separate handlers for SVCall and PendSV + * interrupts and route program control from those handlers to + * vPortSVCHandler and xPortPendSVHandler functions. + * + * Applications that use Indirect Routing must set + * configCHECK_HANDLER_INSTALLATION to 0 in their FreeRTOSConfig.h. Direct + * routing, which is validated here when configCHECK_HANDLER_INSTALLATION + * is 1, should be preferred when possible. */ + #if ( configCHECK_HANDLER_INSTALLATION == 1 ) + { + const portISR_t * const pxVectorTable = portSCB_VTOR_REG; + + /* Validate that the application has correctly installed the FreeRTOS + * handlers for SVCall and PendSV interrupts. We do not check the + * installation of the SysTick handler because the application may + * choose to drive the RTOS tick using a timer other than the SysTick + * timer by overriding the weak function vPortSetupTimerInterrupt(). + * + * Assertion failures here indicate incorrect installation of the + * FreeRTOS handlers. For help installing the FreeRTOS handlers, see + * https://www.FreeRTOS.org/FAQHelp.html. + * + * Systems with a configurable address for the interrupt vector table + * can also encounter assertion failures or even system faults here if + * VTOR is not set correctly to point to the application's vector table. */ + configASSERT( pxVectorTable[ portVECTOR_INDEX_SVC ] == vPortSVCHandler ); + configASSERT( pxVectorTable[ portVECTOR_INDEX_PENDSV ] == xPortPendSVHandler ); + } + #endif /* configCHECK_HANDLER_INSTALLATION */ + #if ( configASSERT_DEFINED == 1 ) { volatile uint8_t ucOriginalPriority; @@ -733,7 +793,7 @@ BaseType_t xPortStartScheduler( void ) /* Check that the bits not implemented in hardware are zero in * configMAX_SYSCALL_INTERRUPT_PRIORITY. */ - configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( ~ucMaxPriorityValue ) ) == 0U ); + configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( uint8_t ) ( ~( uint32_t ) ucMaxPriorityValue ) ) == 0U ); /* Calculate the maximum acceptable priority group value for the number * of bits read back. */ @@ -782,9 +842,11 @@ BaseType_t xPortStartScheduler( void ) } #endif /* configASSERT_DEFINED */ - /* Make PendSV and SysTick the lowest priority interrupts. */ + /* Make PendSV and SysTick the lowest priority interrupts, and make SVCall + * the highest priority. */ portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI; portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI; + portNVIC_SHPR2_REG = 0; /* Configure the regions in the MPU that are common to all tasks. */ prvSetupMPU(); @@ -932,14 +994,21 @@ void xPortSysTickHandler( void ) * save and then restore the interrupt mask value as its value is already * known. */ portDISABLE_INTERRUPTS(); + traceISR_ENTER(); { /* Increment the RTOS tick. */ if( xTaskIncrementTick() != pdFALSE ) { + traceISR_EXIT_TO_SCHEDULER(); + /* A context switch is required. Context switching is performed in * the PendSV interrupt. Pend the PendSV interrupt. */ portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; } + else + { + traceISR_EXIT(); + } } portENABLE_INTERRUPTS(); } diff --git a/Source/portable/IAR/ARM_CM4F_MPU/portasm.s b/Source/portable/IAR/ARM_CM4F_MPU/portasm.s index 0da9a4f97..a48500326 100644 --- a/Source/portable/IAR/ARM_CM4F_MPU/portasm.s +++ b/Source/portable/IAR/ARM_CM4F_MPU/portasm.s @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -57,6 +57,12 @@ files (__ICCARM__ is defined by the IAR C compiler but not by the IAR assembler. #define configUSE_MPU_WRAPPERS_V1 0 #endif +/* Errata 837070 workaround must be enabled on Cortex-M7 r0p0 + * and r0p1 cores. */ +#ifndef configENABLE_ERRATA_837070_WORKAROUND + #define configENABLE_ERRATA_837070_WORKAROUND 0 +#endif + /* These must be in sync with portmacro.h. */ #define portSVC_START_SCHEDULER 100 #define portSVC_SYSTEM_CALL_EXIT 103 @@ -113,15 +119,15 @@ xPortPendSVHandler: str r3, [r0] /* Disable MPU. */ ldr r0, =0xe000ed9c /* Region Base Address register. */ - ldmia r2!, {r4-r11} /* Read 4 sets of MPU registers [MPU Region # 4 - 7]. */ - stmia r0, {r4-r11} /* Write 4 sets of MPU registers [MPU Region # 4 - 7]. */ + ldmia r2!, {r4-r11} /* Read 4 sets of MPU registers [MPU Region # 0 - 3]. */ + stmia r0, {r4-r11} /* Write 4 sets of MPU registers [MPU Region # 0 - 3]. */ #ifdef configTOTAL_MPU_REGIONS #if ( configTOTAL_MPU_REGIONS == 16 ) + ldmia r2!, {r4-r11} /* Read 4 sets of MPU registers [MPU Region # 4 - 7]. */ + stmia r0, {r4-r11} /* Write 4 sets of MPU registers. [MPU Region # 4 - 7]. */ ldmia r2!, {r4-r11} /* Read 4 sets of MPU registers [MPU Region # 8 - 11]. */ stmia r0, {r4-r11} /* Write 4 sets of MPU registers. [MPU Region # 8 - 11]. */ - ldmia r2!, {r4-r11} /* Read 4 sets of MPU registers [MPU Region # 12 - 15]. */ - stmia r0, {r4-r11} /* Write 4 sets of MPU registers. [MPU Region # 12 - 15]. */ #endif /* configTOTAL_MPU_REGIONS == 16. */ #endif @@ -233,15 +239,15 @@ vPortRestoreContextOfFirstTask: str r3, [r0] /* Disable MPU. */ ldr r0, =0xe000ed9c /* Region Base Address register. */ - ldmia r2!, {r4-r11} /* Read 4 sets of MPU registers [MPU Region # 4 - 7]. */ - stmia r0, {r4-r11} /* Write 4 sets of MPU registers [MPU Region # 4 - 7]. */ + ldmia r2!, {r4-r11} /* Read 4 sets of MPU registers [MPU Region # 0 - 3]. */ + stmia r0, {r4-r11} /* Write 4 sets of MPU registers [MPU Region # 0 - 3]. */ #ifdef configTOTAL_MPU_REGIONS #if ( configTOTAL_MPU_REGIONS == 16 ) + ldmia r2!, {r4-r11} /* Read 4 sets of MPU registers [MPU Region # 4 - 7]. */ + stmia r0, {r4-r11} /* Write 4 sets of MPU registers. [MPU Region # 4 - 7]. */ ldmia r2!, {r4-r11} /* Read 4 sets of MPU registers [MPU Region # 8 - 11]. */ stmia r0, {r4-r11} /* Write 4 sets of MPU registers. [MPU Region # 8 - 11]. */ - ldmia r2!, {r4-r11} /* Read 4 sets of MPU registers [MPU Region # 12 - 15]. */ - stmia r0, {r4-r11} /* Write 4 sets of MPU registers. [MPU Region # 12 - 15]. */ #endif /* configTOTAL_MPU_REGIONS == 16. */ #endif diff --git a/Source/portable/IAR/ARM_CM4F_MPU/portmacro.h b/Source/portable/IAR/ARM_CM4F_MPU/portmacro.h index cae9bcc73..7da13777e 100644 --- a/Source/portable/IAR/ARM_CM4F_MPU/portmacro.h +++ b/Source/portable/IAR/ARM_CM4F_MPU/portmacro.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -65,7 +65,7 @@ typedef unsigned long UBaseType_t; #if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS ) typedef uint16_t TickType_t; #define portMAX_DELAY ( TickType_t ) 0xffff -#elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS ) +#elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS ) typedef uint32_t TickType_t; #define portMAX_DELAY ( TickType_t ) 0xffffffffUL @@ -73,9 +73,14 @@ typedef unsigned long UBaseType_t; * not need to be guarded with a critical section. */ #define portTICK_TYPE_IS_ATOMIC 1 #else - #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width. + #error "configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width." #endif +/* Errata 837070 workaround must be enabled on Cortex-M7 r0p0 + * and r0p1 cores. */ +#ifndef configENABLE_ERRATA_837070_WORKAROUND + #define configENABLE_ERRATA_837070_WORKAROUND 0 +#endif /*-----------------------------------------------------------*/ /* MPU specific constants. */ @@ -177,8 +182,8 @@ typedef unsigned long UBaseType_t; #define configTEX_S_C_B_SRAM ( 0x07UL ) #endif -#define portGENERAL_PERIPHERALS_REGION ( configTOTAL_MPU_REGIONS - 5UL ) -#define portSTACK_REGION ( configTOTAL_MPU_REGIONS - 4UL ) +#define portSTACK_REGION ( configTOTAL_MPU_REGIONS - 5UL ) +#define portGENERAL_PERIPHERALS_REGION ( configTOTAL_MPU_REGIONS - 4UL ) #define portUNPRIVILEGED_FLASH_REGION ( configTOTAL_MPU_REGIONS - 3UL ) #define portPRIVILEGED_FLASH_REGION ( configTOTAL_MPU_REGIONS - 2UL ) #define portPRIVILEGED_RAM_REGION ( configTOTAL_MPU_REGIONS - 1UL ) @@ -187,8 +192,6 @@ typedef unsigned long UBaseType_t; #define portNUM_CONFIGURABLE_REGIONS ( configTOTAL_MPU_REGIONS - 5UL ) #define portTOTAL_NUM_REGIONS_IN_TCB ( portNUM_CONFIGURABLE_REGIONS + 1 ) /* Plus 1 to create space for the stack region. */ -#define portSWITCH_TO_USER_MODE() __asm volatile ( " mrs r0, control \n orr r0, r0, #1 \n msr control, r0 " ::: "r0", "memory" ) - typedef struct MPU_REGION_REGISTERS { uint32_t ulRegionBaseAddress; @@ -205,7 +208,7 @@ typedef struct MPU_REGION_SETTINGS #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) #ifndef configSYSTEM_CALL_STACK_SIZE - #error configSYSTEM_CALL_STACK_SIZE must be defined to the desired size of the system call stack in words for using MPU wrappers v2. + #error "configSYSTEM_CALL_STACK_SIZE must be defined to the desired size of the system call stack in words for using MPU wrappers v2." #endif typedef struct SYSTEM_CALL_STACK_INFO @@ -224,8 +227,8 @@ typedef struct MPU_REGION_SETTINGS #define portACL_ENTRY_SIZE_BITS ( 32U ) /* Flags used for xMPU_SETTINGS.ulTaskFlags member. */ -#define portSTACK_FRAME_HAS_PADDING_FLAG ( 1UL << 0UL ) -#define portTASK_IS_PRIVILEGED_FLAG ( 1UL << 1UL ) +#define portSTACK_FRAME_HAS_PADDING_FLAG ( 1UL << 0UL ) +#define portTASK_IS_PRIVILEGED_FLAG ( 1UL << 1UL ) typedef struct MPU_SETTINGS { @@ -256,7 +259,7 @@ typedef struct MPU_SETTINGS /* Scheduler utilities. */ -#define portYIELD() __asm volatile ( " SVC %0 \n"::"i" ( portSVC_YIELD ) : "memory" ) +#define portYIELD() __asm volatile ( " SVC %0 \n" ::"i" ( portSVC_YIELD ) : "memory" ) #define portYIELD_WITHIN_API() \ { \ /* Set a PendSV to request a context switch. */ \ @@ -267,8 +270,20 @@ typedef struct MPU_SETTINGS #define portNVIC_INT_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed04 ) ) #define portNVIC_PENDSVSET_BIT ( 1UL << 28UL ) -#define portEND_SWITCHING_ISR( xSwitchRequired ) do { if( xSwitchRequired != pdFALSE ) portYIELD_WITHIN_API(); } while( 0 ) -#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x ) +#define portEND_SWITCHING_ISR( xSwitchRequired ) \ + do \ + { \ + if( xSwitchRequired != pdFALSE ) \ + { \ + traceISR_EXIT_TO_SCHEDULER(); \ + portYIELD_WITHIN_API(); \ + } \ + else \ + { \ + traceISR_EXIT(); \ + } \ + } while( 0 ) +#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x ) /*-----------------------------------------------------------*/ /* Architecture specific optimisations. */ @@ -280,7 +295,7 @@ typedef struct MPU_SETTINGS /* Check the configuration. */ #if ( configMAX_PRIORITIES > 32 ) - #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice. + #error "configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice." #endif /* Store/clear the ready priorities in a bit map. */ @@ -298,23 +313,23 @@ typedef struct MPU_SETTINGS extern void vPortEnterCritical( void ); extern void vPortExitCritical( void ); -#if( configENABLE_ERRATA_837070_WORKAROUND == 1 ) - #define portDISABLE_INTERRUPTS() \ - { \ - __disable_interrupt(); \ - __set_BASEPRI( configMAX_SYSCALL_INTERRUPT_PRIORITY ); \ - __DSB(); \ - __ISB(); \ - __enable_interrupt(); \ - } +#if ( configENABLE_ERRATA_837070_WORKAROUND == 1 ) + #define portDISABLE_INTERRUPTS() \ + { \ + __disable_interrupt(); \ + __set_BASEPRI( configMAX_SYSCALL_INTERRUPT_PRIORITY ); \ + __DSB(); \ + __ISB(); \ + __enable_interrupt(); \ + } #else - #define portDISABLE_INTERRUPTS() \ - { \ - __set_BASEPRI( configMAX_SYSCALL_INTERRUPT_PRIORITY ); \ - __DSB(); \ - __ISB(); \ - } -#endif + #define portDISABLE_INTERRUPTS() \ + { \ + __set_BASEPRI( configMAX_SYSCALL_INTERRUPT_PRIORITY ); \ + __DSB(); \ + __ISB(); \ + } +#endif /* if ( configENABLE_ERRATA_837070_WORKAROUND == 1 ) */ #define portENABLE_INTERRUPTS() __set_BASEPRI( 0 ) #define portENTER_CRITICAL() vPortEnterCritical() @@ -371,24 +386,33 @@ portFORCE_INLINE static BaseType_t xPortIsInsideInterrupt( void ) extern BaseType_t xIsPrivileged( void ); extern void vResetPrivilege( void ); +extern void vPortSwitchToUserMode( void ); /** * @brief Checks whether or not the processor is privileged. * * @return 1 if the processor is already privileged, 0 otherwise. */ -#define portIS_PRIVILEGED() xIsPrivileged() +#define portIS_PRIVILEGED() xIsPrivileged() /** * @brief Raise an SVC request to raise privilege. */ -#define portRAISE_PRIVILEGE() __asm volatile ( "svc %0 \n" ::"i" ( portSVC_RAISE_PRIVILEGE ) : "memory" ); +#define portRAISE_PRIVILEGE() __asm volatile ( "svc %0 \n" ::"i" ( portSVC_RAISE_PRIVILEGE ) : "memory" ); /** * @brief Lowers the privilege level by setting the bit 0 of the CONTROL * register. */ -#define portRESET_PRIVILEGE() vResetPrivilege() +#define portRESET_PRIVILEGE() vResetPrivilege() + +/** + * @brief Make a task unprivileged. + * + * It must be called from privileged tasks only. Calling it from unprivileged + * task will result in a memory protection fault. + */ +#define portSWITCH_TO_USER_MODE() vPortSwitchToUserMode() /*-----------------------------------------------------------*/ extern BaseType_t xPortIsTaskPrivileged( void ); @@ -398,11 +422,11 @@ extern BaseType_t xPortIsTaskPrivileged( void ); * * @return pdTRUE if the calling task is privileged, pdFALSE otherwise. */ -#define portIS_TASK_PRIVILEGED() xPortIsTaskPrivileged() +#define portIS_TASK_PRIVILEGED() xPortIsTaskPrivileged() /*-----------------------------------------------------------*/ #ifndef configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY - #warning "configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY is not defined. We recommend defining it to 1 in FreeRTOSConfig.h for better security. https://www.FreeRTOS.org/FreeRTOS-V10.3.x.html" + #warning "configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY is not defined. We recommend defining it to 1 in FreeRTOSConfig.h for better security. www.FreeRTOS.org/FreeRTOS-V10.3.x.html" #define configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY 0 #endif /*-----------------------------------------------------------*/ diff --git a/Source/portable/IAR/ARM_CM55/non_secure/mpu_wrappers_v2_asm.S b/Source/portable/IAR/ARM_CM55/non_secure/mpu_wrappers_v2_asm.S index ef180bd91..b4f1fbc3b 100644 --- a/Source/portable/IAR/ARM_CM55/non_secure/mpu_wrappers_v2_asm.S +++ b/Source/portable/IAR/ARM_CM55/non_secure/mpu_wrappers_v2_asm.S @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -196,20 +196,6 @@ MPU_uxTaskGetNumberOfTasks: svc #SYSTEM_CALL_uxTaskGetNumberOfTasks /*-----------------------------------------------------------*/ - PUBLIC MPU_pcTaskGetName -MPU_pcTaskGetName: - push {r0} - mrs r0, control - tst r0, #1 - bne MPU_pcTaskGetName_Unpriv - MPU_pcTaskGetName_Priv: - pop {r0} - b MPU_pcTaskGetNameImpl - MPU_pcTaskGetName_Unpriv: - pop {r0} - svc #SYSTEM_CALL_pcTaskGetName -/*-----------------------------------------------------------*/ - PUBLIC MPU_ulTaskGetRunTimeCounter MPU_ulTaskGetRunTimeCounter: push {r0} @@ -742,24 +728,18 @@ MPU_xTimerGetTimerDaemonTaskHandle: svc #SYSTEM_CALL_xTimerGetTimerDaemonTaskHandle /*-----------------------------------------------------------*/ - PUBLIC MPU_xTimerGenericCommandEntry -MPU_xTimerGenericCommandEntry: + PUBLIC MPU_xTimerGenericCommandFromTaskEntry +MPU_xTimerGenericCommandFromTaskEntry: push {r0} - /* This function can be called from ISR also and therefore, we need a check - * to take privileged path, if called from ISR. */ - mrs r0, ipsr - cmp r0, #0 - bne MPU_xTimerGenericCommand_Priv mrs r0, control tst r0, #1 - beq MPU_xTimerGenericCommand_Priv - MPU_xTimerGenericCommand_Unpriv: + bne MPU_xTimerGenericCommandFromTask_Unpriv + MPU_xTimerGenericCommandFromTask_Priv: pop {r0} - svc #SYSTEM_CALL_xTimerGenericCommand - MPU_xTimerGenericCommand_Priv: + b MPU_xTimerGenericCommandFromTaskImpl + MPU_xTimerGenericCommandFromTask_Unpriv: pop {r0} - b MPU_xTimerGenericCommandPrivImpl - + svc #SYSTEM_CALL_xTimerGenericCommandFromTask /*-----------------------------------------------------------*/ PUBLIC MPU_pcTimerGetName @@ -1089,10 +1069,6 @@ MPU_xTaskGetTickCountImpl: MPU_uxTaskGetNumberOfTasksImpl: b MPU_uxTaskGetNumberOfTasksImpl - PUBWEAK MPU_pcTaskGetNameImpl -MPU_pcTaskGetNameImpl: - b MPU_pcTaskGetNameImpl - PUBWEAK MPU_ulTaskGetRunTimeCounterImpl MPU_ulTaskGetRunTimeCounterImpl: b MPU_ulTaskGetRunTimeCounterImpl @@ -1245,9 +1221,9 @@ MPU_xTimerIsTimerActiveImpl: MPU_xTimerGetTimerDaemonTaskHandleImpl: b MPU_xTimerGetTimerDaemonTaskHandleImpl - PUBWEAK MPU_xTimerGenericCommandPrivImpl -MPU_xTimerGenericCommandPrivImpl: - b MPU_xTimerGenericCommandPrivImpl + PUBWEAK MPU_xTimerGenericCommandFromTaskImpl +MPU_xTimerGenericCommandFromTaskImpl: + b MPU_xTimerGenericCommandFromTaskImpl PUBWEAK MPU_pcTimerGetNameImpl MPU_pcTimerGetNameImpl: diff --git a/Source/portable/IAR/ARM_CM55/non_secure/port.c b/Source/portable/IAR/ARM_CM55/non_secure/port.c index 9712ac353..230fe5fc2 100644 --- a/Source/portable/IAR/ARM_CM55/non_secure/port.c +++ b/Source/portable/IAR/ARM_CM55/non_secure/port.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -68,6 +68,22 @@ #if ( ( configRUN_FREERTOS_SECURE_ONLY == 1 ) && ( configENABLE_TRUSTZONE == 1 ) ) #error TrustZone needs to be disabled in order to run FreeRTOS on the Secure Side. #endif + +/** + * Cortex-M23 does not have non-secure PSPLIM. We should use PSPLIM on Cortex-M23 + * only when FreeRTOS runs on secure side. + */ +#if ( ( portHAS_ARMV8M_MAIN_EXTENSION == 0 ) && ( configRUN_FREERTOS_SECURE_ONLY == 0 ) ) + #define portUSE_PSPLIM_REGISTER 0 +#else + #define portUSE_PSPLIM_REGISTER 1 +#endif +/*-----------------------------------------------------------*/ + +/** + * @brief Prototype of all Interrupt Service Routines (ISRs). + */ +typedef void ( * portISR_t )( void ); /*-----------------------------------------------------------*/ /** @@ -91,10 +107,18 @@ /** * @brief Constants required to manipulate the SCB. */ -#define portSCB_SYS_HANDLER_CTRL_STATE_REG ( *( volatile uint32_t * ) 0xe000ed24 ) +#define portSCB_VTOR_REG ( *( ( portISR_t ** ) 0xe000ed08 ) ) +#define portSCB_SYS_HANDLER_CTRL_STATE_REG ( *( ( volatile uint32_t * ) 0xe000ed24 ) ) #define portSCB_MEM_FAULT_ENABLE_BIT ( 1UL << 16UL ) /*-----------------------------------------------------------*/ +/** + * @brief Constants used to check the installation of the FreeRTOS interrupt handlers. + */ +#define portVECTOR_INDEX_SVC ( 11 ) +#define portVECTOR_INDEX_PENDSV ( 14 ) +/*-----------------------------------------------------------*/ + /** * @brief Constants required to check the validity of an interrupt priority. */ @@ -111,8 +135,8 @@ /** * @brief Constants used during system call enter and exit. */ -#define portPSR_STACK_PADDING_MASK ( 1UL << 9UL ) -#define portEXC_RETURN_STACK_FRAME_TYPE_MASK ( 1UL << 4UL ) +#define portPSR_STACK_PADDING_MASK ( 1UL << 9UL ) +#define portEXC_RETURN_STACK_FRAME_TYPE_MASK ( 1UL << 4UL ) /*-----------------------------------------------------------*/ /** @@ -134,81 +158,81 @@ /** * @brief Offsets in the stack to the parameters when inside the SVC handler. */ -#define portOFFSET_TO_LR ( 5 ) -#define portOFFSET_TO_PC ( 6 ) -#define portOFFSET_TO_PSR ( 7 ) +#define portOFFSET_TO_LR ( 5 ) +#define portOFFSET_TO_PC ( 6 ) +#define portOFFSET_TO_PSR ( 7 ) /*-----------------------------------------------------------*/ /** * @brief Constants required to manipulate the MPU. */ -#define portMPU_TYPE_REG ( *( ( volatile uint32_t * ) 0xe000ed90 ) ) -#define portMPU_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed94 ) ) -#define portMPU_RNR_REG ( *( ( volatile uint32_t * ) 0xe000ed98 ) ) +#define portMPU_TYPE_REG ( *( ( volatile uint32_t * ) 0xe000ed90 ) ) +#define portMPU_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed94 ) ) +#define portMPU_RNR_REG ( *( ( volatile uint32_t * ) 0xe000ed98 ) ) -#define portMPU_RBAR_REG ( *( ( volatile uint32_t * ) 0xe000ed9c ) ) -#define portMPU_RLAR_REG ( *( ( volatile uint32_t * ) 0xe000eda0 ) ) +#define portMPU_RBAR_REG ( *( ( volatile uint32_t * ) 0xe000ed9c ) ) +#define portMPU_RLAR_REG ( *( ( volatile uint32_t * ) 0xe000eda0 ) ) -#define portMPU_RBAR_A1_REG ( *( ( volatile uint32_t * ) 0xe000eda4 ) ) -#define portMPU_RLAR_A1_REG ( *( ( volatile uint32_t * ) 0xe000eda8 ) ) +#define portMPU_RBAR_A1_REG ( *( ( volatile uint32_t * ) 0xe000eda4 ) ) +#define portMPU_RLAR_A1_REG ( *( ( volatile uint32_t * ) 0xe000eda8 ) ) -#define portMPU_RBAR_A2_REG ( *( ( volatile uint32_t * ) 0xe000edac ) ) -#define portMPU_RLAR_A2_REG ( *( ( volatile uint32_t * ) 0xe000edb0 ) ) +#define portMPU_RBAR_A2_REG ( *( ( volatile uint32_t * ) 0xe000edac ) ) +#define portMPU_RLAR_A2_REG ( *( ( volatile uint32_t * ) 0xe000edb0 ) ) -#define portMPU_RBAR_A3_REG ( *( ( volatile uint32_t * ) 0xe000edb4 ) ) -#define portMPU_RLAR_A3_REG ( *( ( volatile uint32_t * ) 0xe000edb8 ) ) +#define portMPU_RBAR_A3_REG ( *( ( volatile uint32_t * ) 0xe000edb4 ) ) +#define portMPU_RLAR_A3_REG ( *( ( volatile uint32_t * ) 0xe000edb8 ) ) -#define portMPU_MAIR0_REG ( *( ( volatile uint32_t * ) 0xe000edc0 ) ) -#define portMPU_MAIR1_REG ( *( ( volatile uint32_t * ) 0xe000edc4 ) ) +#define portMPU_MAIR0_REG ( *( ( volatile uint32_t * ) 0xe000edc0 ) ) +#define portMPU_MAIR1_REG ( *( ( volatile uint32_t * ) 0xe000edc4 ) ) -#define portMPU_RBAR_ADDRESS_MASK ( 0xffffffe0 ) /* Must be 32-byte aligned. */ -#define portMPU_RLAR_ADDRESS_MASK ( 0xffffffe0 ) /* Must be 32-byte aligned. */ +#define portMPU_RBAR_ADDRESS_MASK ( 0xffffffe0 ) /* Must be 32-byte aligned. */ +#define portMPU_RLAR_ADDRESS_MASK ( 0xffffffe0 ) /* Must be 32-byte aligned. */ -#define portMPU_RBAR_ACCESS_PERMISSIONS_MASK ( 3UL << 1UL ) +#define portMPU_RBAR_ACCESS_PERMISSIONS_MASK ( 3UL << 1UL ) -#define portMPU_MAIR_ATTR0_POS ( 0UL ) -#define portMPU_MAIR_ATTR0_MASK ( 0x000000ff ) +#define portMPU_MAIR_ATTR0_POS ( 0UL ) +#define portMPU_MAIR_ATTR0_MASK ( 0x000000ff ) -#define portMPU_MAIR_ATTR1_POS ( 8UL ) -#define portMPU_MAIR_ATTR1_MASK ( 0x0000ff00 ) +#define portMPU_MAIR_ATTR1_POS ( 8UL ) +#define portMPU_MAIR_ATTR1_MASK ( 0x0000ff00 ) -#define portMPU_MAIR_ATTR2_POS ( 16UL ) -#define portMPU_MAIR_ATTR2_MASK ( 0x00ff0000 ) +#define portMPU_MAIR_ATTR2_POS ( 16UL ) +#define portMPU_MAIR_ATTR2_MASK ( 0x00ff0000 ) -#define portMPU_MAIR_ATTR3_POS ( 24UL ) -#define portMPU_MAIR_ATTR3_MASK ( 0xff000000 ) +#define portMPU_MAIR_ATTR3_POS ( 24UL ) +#define portMPU_MAIR_ATTR3_MASK ( 0xff000000 ) -#define portMPU_MAIR_ATTR4_POS ( 0UL ) -#define portMPU_MAIR_ATTR4_MASK ( 0x000000ff ) +#define portMPU_MAIR_ATTR4_POS ( 0UL ) +#define portMPU_MAIR_ATTR4_MASK ( 0x000000ff ) -#define portMPU_MAIR_ATTR5_POS ( 8UL ) -#define portMPU_MAIR_ATTR5_MASK ( 0x0000ff00 ) +#define portMPU_MAIR_ATTR5_POS ( 8UL ) +#define portMPU_MAIR_ATTR5_MASK ( 0x0000ff00 ) -#define portMPU_MAIR_ATTR6_POS ( 16UL ) -#define portMPU_MAIR_ATTR6_MASK ( 0x00ff0000 ) +#define portMPU_MAIR_ATTR6_POS ( 16UL ) +#define portMPU_MAIR_ATTR6_MASK ( 0x00ff0000 ) -#define portMPU_MAIR_ATTR7_POS ( 24UL ) -#define portMPU_MAIR_ATTR7_MASK ( 0xff000000 ) +#define portMPU_MAIR_ATTR7_POS ( 24UL ) +#define portMPU_MAIR_ATTR7_MASK ( 0xff000000 ) -#define portMPU_RLAR_ATTR_INDEX0 ( 0UL << 1UL ) -#define portMPU_RLAR_ATTR_INDEX1 ( 1UL << 1UL ) -#define portMPU_RLAR_ATTR_INDEX2 ( 2UL << 1UL ) -#define portMPU_RLAR_ATTR_INDEX3 ( 3UL << 1UL ) -#define portMPU_RLAR_ATTR_INDEX4 ( 4UL << 1UL ) -#define portMPU_RLAR_ATTR_INDEX5 ( 5UL << 1UL ) -#define portMPU_RLAR_ATTR_INDEX6 ( 6UL << 1UL ) -#define portMPU_RLAR_ATTR_INDEX7 ( 7UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX0 ( 0UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX1 ( 1UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX2 ( 2UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX3 ( 3UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX4 ( 4UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX5 ( 5UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX6 ( 6UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX7 ( 7UL << 1UL ) -#define portMPU_RLAR_REGION_ENABLE ( 1UL ) +#define portMPU_RLAR_REGION_ENABLE ( 1UL ) /* Enable privileged access to unmapped region. */ -#define portMPU_PRIV_BACKGROUND_ENABLE_BIT ( 1UL << 2UL ) +#define portMPU_PRIV_BACKGROUND_ENABLE_BIT ( 1UL << 2UL ) /* Enable MPU. */ -#define portMPU_ENABLE_BIT ( 1UL << 0UL ) +#define portMPU_ENABLE_BIT ( 1UL << 0UL ) /* Expected value of the portMPU_TYPE register. */ -#define portEXPECTED_MPU_TYPE_VALUE ( configTOTAL_MPU_REGIONS << 8UL ) +#define portEXPECTED_MPU_TYPE_VALUE ( configTOTAL_MPU_REGIONS << 8UL ) /* Extract first address of the MPU region as encoded in the * RBAR (Region Base Address Register) value. */ @@ -448,13 +472,13 @@ portDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIV #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) - /** - * @brief Sets up the task stack so that upon returning from - * SVC, the task stack is used again. - * - * @param pulSystemCallStack The current SP when the SVC was raised. - * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler. - */ +/** + * @brief Sets up the task stack so that upon returning from + * SVC, the task stack is used again. + * + * @param pulSystemCallStack The current SP when the SVC was raised. + * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler. + */ void vSystemCallExit( uint32_t * pulSystemCallStack, uint32_t ulLR ) PRIVILEGED_FUNCTION; @@ -462,11 +486,11 @@ portDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIV #if ( configENABLE_MPU == 1 ) - /** - * @brief Checks whether or not the calling task is privileged. - * - * @return pdTRUE if the calling task is privileged, pdFALSE otherwise. - */ +/** + * @brief Checks whether or not the calling task is privileged. + * + * @return pdTRUE if the calling task is privileged, pdFALSE otherwise. + */ BaseType_t xPortIsTaskPrivileged( void ) PRIVILEGED_FUNCTION; #endif /* configENABLE_MPU == 1 */ @@ -501,13 +525,13 @@ PRIVILEGED_DATA static volatile uint32_t ulCriticalNesting = 0xaaaaaaaaUL; * FreeRTOS API functions are not called from interrupts that have been assigned * a priority above configMAX_SYSCALL_INTERRUPT_PRIORITY. */ -#if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) ) +#if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) static uint8_t ucMaxSysCallPriority = 0; static uint32_t ulMaxPRIGROUPValue = 0; static const volatile uint8_t * const pcInterruptPriorityRegisters = ( const volatile uint8_t * ) portNVIC_IP_REGISTERS_OFFSET_16; -#endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) ) */ +#endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */ #if ( configUSE_TICKLESS_IDLE == 1 ) @@ -760,8 +784,15 @@ __attribute__( ( weak ) ) void vPortSetupTimerInterrupt( void ) /* PRIVILEGED_FU } #endif /* configUSE_TICKLESS_IDLE */ - /* Stop and reset the SysTick. */ - portNVIC_SYSTICK_CTRL_REG = 0UL; + /* Stop and reset SysTick. + * + * QEMU versions older than 7.0.0 contain a bug which causes an error if we + * enable SysTick without first selecting a valid clock source. We trigger + * the bug if we change clock sources from a clock with a zero clock period + * to one with a nonzero clock period and enable Systick at the same time. + * So we configure the CLKSOURCE bit here, prior to setting the ENABLE bit. + * This workaround avoids the bug in QEMU versions older than 7.0.0. */ + portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT_CONFIG; portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL; /* Configure SysTick to interrupt at the requested rate. */ @@ -819,6 +850,7 @@ static void prvTaskExitError( void ) static void prvSetupMPU( void ) /* PRIVILEGED_FUNCTION */ { #if defined( __ARMCC_VERSION ) + /* Declaration when these variable are defined in code instead of being * exported from linker scripts. */ extern uint32_t * __privileged_functions_start__; @@ -972,13 +1004,19 @@ void SysTick_Handler( void ) /* PRIVILEGED_FUNCTION */ uint32_t ulPreviousMask; ulPreviousMask = portSET_INTERRUPT_MASK_FROM_ISR(); + traceISR_ENTER(); { /* Increment the RTOS tick. */ if( xTaskIncrementTick() != pdFALSE ) { + traceISR_EXIT_TO_SCHEDULER(); /* Pend a context switch. */ portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; } + else + { + traceISR_EXIT(); + } } portCLEAR_INTERRUPT_MASK_FROM_ISR( ulPreviousMask ); } @@ -988,6 +1026,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO { #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) ) #if defined( __ARMCC_VERSION ) + /* Declaration when these variable are defined in code instead of being * exported from linker scripts. */ extern uint32_t * __syscalls_flash_start__; @@ -1083,18 +1122,24 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO vRestoreContextOfFirstTask(); break; - #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) ) - case portSVC_RAISE_PRIVILEGE: + #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) ) + case portSVC_RAISE_PRIVILEGE: - /* Only raise the privilege, if the svc was raised from any of - * the system calls. */ - if( ( ulPC >= ( uint32_t ) __syscalls_flash_start__ ) && - ( ulPC <= ( uint32_t ) __syscalls_flash_end__ ) ) - { - vRaisePrivilege(); - } - break; - #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) */ + /* Only raise the privilege, if the svc was raised from any of + * the system calls. */ + if( ( ulPC >= ( uint32_t ) __syscalls_flash_start__ ) && + ( ulPC <= ( uint32_t ) __syscalls_flash_end__ ) ) + { + vRaisePrivilege(); + } + break; + #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) */ + + #if ( configENABLE_MPU == 1 ) + case portSVC_YIELD: + vPortYield(); + break; + #endif /* configENABLE_MPU == 1 */ default: /* Incorrect SVC call. */ @@ -1154,12 +1199,11 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO { /* Extended frame i.e. FPU in use. */ ulStackFrameSize = 26; - __asm volatile - ( + __asm volatile ( " vpush {s0} \n" /* Trigger lazy stacking. */ " vpop {s0} \n" /* Nullify the affect of the above instruction. */ ::: "memory" - ); + ); } else { @@ -1171,7 +1215,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO { ulStackFrameSize = 8; } - #endif /* if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */ + #endif /* configENABLE_FPU || configENABLE_MVE */ /* Make space on the system call stack for the stack frame. */ pulSystemCallStack = pulSystemCallStack - ulStackFrameSize; @@ -1187,18 +1231,24 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO * point (i.e. the caller of the MPU_). We need to restore it * when we exit from the system call. */ pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry = pulTaskStack[ portOFFSET_TO_LR ]; - /* Store the value of the PSPLIM register before the SVC was raised. * We need to restore it when we exit from the system call. */ - __asm volatile ( "mrs %0, psplim" : "=r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) ); + #if ( portUSE_PSPLIM_REGISTER == 1 ) + { + __asm volatile ( "mrs %0, psplim" : "=r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) ); + } + #endif /* Use the pulSystemCallStack in thread mode. */ __asm volatile ( "msr psp, %0" : : "r" ( pulSystemCallStack ) ); - __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) ); + #if ( portUSE_PSPLIM_REGISTER == 1 ) + { + __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) ); + } + #endif /* Start executing the system call upon returning from this handler. */ pulSystemCallStack[ portOFFSET_TO_PC ] = uxSystemCallImplementations[ ucSystemCallNumber ]; - /* Raise a request to exit from the system call upon finishing the * system call. */ pulSystemCallStack[ portOFFSET_TO_LR ] = ( uint32_t ) vRequestSystemCallExit; @@ -1224,14 +1274,13 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO pulSystemCallStack[ portOFFSET_TO_PSR ] &= ( ~portPSR_STACK_PADDING_MASK ); /* Raise the privilege for the duration of the system call. */ - __asm volatile - ( + __asm volatile ( " mrs r0, control \n" /* Obtain current control value. */ " movs r1, #1 \n" /* r1 = 1. */ " bics r0, r1 \n" /* Clear nPRIV bit. */ " msr control, r0 \n" /* Write back new control value. */ ::: "r0", "r1", "memory" - ); + ); } } @@ -1293,12 +1342,11 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO { /* Extended frame i.e. FPU in use. */ ulStackFrameSize = 26; - __asm volatile - ( + __asm volatile ( " vpush {s0} \n" /* Trigger lazy stacking. */ " vpop {s0} \n" /* Nullify the affect of the above instruction. */ ::: "memory" - ); + ); } else { @@ -1310,7 +1358,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO { ulStackFrameSize = 8; } - #endif /* if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */ + #endif /* configENABLE_FPU || configENABLE_MVE */ /* Make space on the task stack for the stack frame. */ pulTaskStack = pulTaskStack - ulStackFrameSize; @@ -1332,7 +1380,11 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO /* Restore the PSPLIM register to what it was at the time of * system call entry. */ - __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) ); + #if ( portUSE_PSPLIM_REGISTER == 1 ) + { + __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) ); + } + #endif /* If the hardware used padding to force the stack pointer * to be double word aligned, set the stacked xPSR bit[9], @@ -1350,14 +1402,13 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO pxMpuSettings->xSystemCallStackInfo.pulTaskStack = NULL; /* Drop the privilege before returning to the thread mode. */ - __asm volatile - ( + __asm volatile ( " mrs r0, control \n" /* Obtain current control value. */ " movs r1, #1 \n" /* r1 = 1. */ " orrs r0, r1 \n" /* Set nPRIV bit. */ " msr control, r0 \n" /* Write back new control value. */ ::: "r0", "r1", "memory" - ); + ); } } @@ -1410,21 +1461,21 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO xMPUSettings->ulContext[ ulIndex ] = 0x11111111; /* r11. */ ulIndex++; - xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pvParameters; /* r0. */ + xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pvParameters; /* r0. */ ulIndex++; - xMPUSettings->ulContext[ ulIndex ] = 0x01010101; /* r1. */ + xMPUSettings->ulContext[ ulIndex ] = 0x01010101; /* r1. */ ulIndex++; - xMPUSettings->ulContext[ ulIndex ] = 0x02020202; /* r2. */ + xMPUSettings->ulContext[ ulIndex ] = 0x02020202; /* r2. */ ulIndex++; - xMPUSettings->ulContext[ ulIndex ] = 0x03030303; /* r3. */ + xMPUSettings->ulContext[ ulIndex ] = 0x03030303; /* r3. */ ulIndex++; - xMPUSettings->ulContext[ ulIndex ] = 0x12121212; /* r12. */ + xMPUSettings->ulContext[ ulIndex ] = 0x12121212; /* r12. */ ulIndex++; xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portTASK_RETURN_ADDRESS; /* LR. */ ulIndex++; - xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxCode; /* PC. */ + xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxCode; /* PC. */ ulIndex++; - xMPUSettings->ulContext[ ulIndex ] = portINITIAL_XPSR; /* xPSR. */ + xMPUSettings->ulContext[ ulIndex ] = portINITIAL_XPSR; /* xPSR. */ ulIndex++; #if ( configENABLE_TRUSTZONE == 1 ) @@ -1435,8 +1486,9 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO #endif /* configENABLE_TRUSTZONE */ xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) ( pxTopOfStack - 8 ); /* PSP with the hardware saved stack. */ ulIndex++; - xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxEndOfStack; /* PSPLIM. */ + xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxEndOfStack; /* PSPLIM. */ ulIndex++; + if( xRunPrivileged == pdTRUE ) { xMPUSettings->ulTaskFlags |= portTASK_IS_PRIVILEGED_FLAG; @@ -1449,6 +1501,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portINITIAL_CONTROL_UNPRIVILEGED; /* CONTROL. */ ulIndex++; } + xMPUSettings->ulContext[ ulIndex ] = portINITIAL_EXC_RETURN; /* LR (EXC_RETURN). */ ulIndex++; @@ -1483,7 +1536,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO * interrupt. */ #if ( portPRELOAD_REGISTERS == 0 ) { - pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */ + pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */ *pxTopOfStack = portINITIAL_XPSR; /* xPSR. */ pxTopOfStack--; *pxTopOfStack = ( StackType_t ) pxCode; /* PC. */ @@ -1505,7 +1558,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO } #else /* portPRELOAD_REGISTERS */ { - pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */ + pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */ *pxTopOfStack = portINITIAL_XPSR; /* xPSR. */ pxTopOfStack--; *pxTopOfStack = ( StackType_t ) pxCode; /* PC. */ @@ -1540,7 +1593,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO pxTopOfStack--; *pxTopOfStack = portINITIAL_EXC_RETURN; /* EXC_RETURN. */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */ + *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */ #if ( configENABLE_TRUSTZONE == 1 ) { @@ -1559,22 +1612,52 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */ { - #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) ) + /* An application can install FreeRTOS interrupt handlers in one of the + * folllowing ways: + * 1. Direct Routing - Install the functions SVC_Handler and PendSV_Handler + * for SVCall and PendSV interrupts respectively. + * 2. Indirect Routing - Install separate handlers for SVCall and PendSV + * interrupts and route program control from those handlers to + * SVC_Handler and PendSV_Handler functions. + * + * Applications that use Indirect Routing must set + * configCHECK_HANDLER_INSTALLATION to 0 in their FreeRTOSConfig.h. Direct + * routing, which is validated here when configCHECK_HANDLER_INSTALLATION + * is 1, should be preferred when possible. */ + #if ( configCHECK_HANDLER_INSTALLATION == 1 ) + { + const portISR_t * const pxVectorTable = portSCB_VTOR_REG; + + /* Validate that the application has correctly installed the FreeRTOS + * handlers for SVCall and PendSV interrupts. We do not check the + * installation of the SysTick handler because the application may + * choose to drive the RTOS tick using a timer other than the SysTick + * timer by overriding the weak function vPortSetupTimerInterrupt(). + * + * Assertion failures here indicate incorrect installation of the + * FreeRTOS handlers. For help installing the FreeRTOS handlers, see + * https://www.FreeRTOS.org/FAQHelp.html. + * + * Systems with a configurable address for the interrupt vector table + * can also encounter assertion failures or even system faults here if + * VTOR is not set correctly to point to the application's vector table. */ + configASSERT( pxVectorTable[ portVECTOR_INDEX_SVC ] == SVC_Handler ); + configASSERT( pxVectorTable[ portVECTOR_INDEX_PENDSV ] == PendSV_Handler ); + } + #endif /* configCHECK_HANDLER_INSTALLATION */ + + #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) { - volatile uint32_t ulOriginalPriority; volatile uint32_t ulImplementedPrioBits = 0; volatile uint8_t ucMaxPriorityValue; /* Determine the maximum priority from which ISR safe FreeRTOS API - * functions can be called. ISR safe functions are those that end in - * "FromISR". FreeRTOS maintains separate thread and ISR API functions to + * functions can be called. ISR safe functions are those that end in + * "FromISR". FreeRTOS maintains separate thread and ISR API functions to * ensure interrupt entry is as fast and simple as possible. * - * Save the interrupt priority value that is about to be clobbered. */ - ulOriginalPriority = portNVIC_SHPR2_REG; - - /* Determine the number of priority bits available. First write to all - * possible bits. */ + * First, determine the number of priority bits available. Write to all + * possible bits in the priority setting for SVCall. */ portNVIC_SHPR2_REG = 0xFF000000; /* Read the value back to see how many bits stuck. */ @@ -1593,11 +1676,10 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */ /* Check that the bits not implemented in hardware are zero in * configMAX_SYSCALL_INTERRUPT_PRIORITY. */ - configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( ~ucMaxPriorityValue ) ) == 0U ); + configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( uint8_t ) ( ~( uint32_t ) ucMaxPriorityValue ) ) == 0U ); /* Calculate the maximum acceptable priority group value for the number * of bits read back. */ - while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE ) { ulImplementedPrioBits++; @@ -1635,16 +1717,14 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */ * register. */ ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT; ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK; - - /* Restore the clobbered interrupt priority register to its original - * value. */ - portNVIC_SHPR2_REG = ulOriginalPriority; } - #endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) ) */ + #endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */ - /* Make PendSV, CallSV and SysTick the same priority as the kernel. */ + /* Make PendSV and SysTick the lowest priority interrupts, and make SVCall + * the highest priority. */ portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI; portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI; + portNVIC_SHPR2_REG = 0; #if ( configENABLE_MPU == 1 ) { @@ -1701,6 +1781,7 @@ void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */ int32_t lIndex = 0; #if defined( __ARMCC_VERSION ) + /* Declaration when these variable are defined in code instead of being * exported from linker scripts. */ extern uint32_t * __privileged_sram_start__; @@ -1886,7 +1967,7 @@ BaseType_t xPortIsInsideInterrupt( void ) } /*-----------------------------------------------------------*/ -#if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) ) +#if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) void vPortValidateInterruptPriority( void ) { @@ -1944,7 +2025,7 @@ BaseType_t xPortIsInsideInterrupt( void ) configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue ); } -#endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) ) */ +#endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */ /*-----------------------------------------------------------*/ #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) diff --git a/Source/portable/IAR/ARM_CM55/non_secure/portasm.h b/Source/portable/IAR/ARM_CM55/non_secure/portasm.h index f64ceb525..c6d2ebd58 100644 --- a/Source/portable/IAR/ARM_CM55/non_secure/portasm.h +++ b/Source/portable/IAR/ARM_CM55/non_secure/portasm.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/Source/portable/IAR/ARM_CM55/non_secure/portasm.s b/Source/portable/IAR/ARM_CM55/non_secure/portasm.s index 530910341..6a6b677bf 100644 --- a/Source/portable/IAR/ARM_CM55/non_secure/portasm.s +++ b/Source/portable/IAR/ARM_CM55/non_secure/portasm.s @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/Source/portable/IAR/ARM_CM55/non_secure/portmacro.h b/Source/portable/IAR/ARM_CM55/non_secure/portmacro.h index d8d08f155..771a1bb3d 100644 --- a/Source/portable/IAR/ARM_CM55/non_secure/portmacro.h +++ b/Source/portable/IAR/ARM_CM55/non_secure/portmacro.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -53,16 +53,16 @@ /** * Architecture specifics. */ -#define portARCH_NAME "Cortex-M55" -#define portHAS_BASEPRI 1 -#define portDONT_DISCARD __root +#define portARCH_NAME "Cortex-M55" +#define portHAS_ARMV8M_MAIN_EXTENSION 1 +#define portDONT_DISCARD __root /*-----------------------------------------------------------*/ /* ARMv8-M common port configurations. */ #include "portmacrocommon.h" /*-----------------------------------------------------------*/ -#if( configTOTAL_MPU_REGIONS == 16 ) +#if ( configTOTAL_MPU_REGIONS == 16 ) #error 16 MPU regions are not yet supported for this port. #endif /*-----------------------------------------------------------*/ @@ -70,8 +70,8 @@ /** * @brief Critical section management. */ -#define portDISABLE_INTERRUPTS() ulSetInterruptMask() -#define portENABLE_INTERRUPTS() vClearInterruptMask( 0 ) +#define portDISABLE_INTERRUPTS() ulSetInterruptMask() +#define portENABLE_INTERRUPTS() vClearInterruptMask( 0 ) /*-----------------------------------------------------------*/ /* Suppress warnings that are generated by the IAR tools, but cannot be fixed in diff --git a/Source/portable/IAR/ARM_CM55/non_secure/portmacrocommon.h b/Source/portable/IAR/ARM_CM55/non_secure/portmacrocommon.h index 6f666da22..33f21d85b 100644 --- a/Source/portable/IAR/ARM_CM55/non_secure/portmacrocommon.h +++ b/Source/portable/IAR/ARM_CM55/non_secure/portmacrocommon.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -117,7 +117,7 @@ extern uint32_t ulSetInterruptMask( void ) /* __attribute__(( naked )) PRIVILEGE extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */; #if ( configENABLE_TRUSTZONE == 1 ) - extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize ); /* __attribute__ (( naked )) */ + extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize ); /* __attribute__ (( naked )) */ extern void vPortFreeSecureContext( uint32_t * pulTCB ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */; #endif /* configENABLE_TRUSTZONE */ @@ -188,13 +188,13 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P #if ( configENABLE_MPU == 1 ) - /** - * @brief Settings to define an MPU region. - */ +/** + * @brief Settings to define an MPU region. + */ typedef struct MPURegionSettings { - uint32_t ulRBAR; /**< RBAR for the region. */ - uint32_t ulRLAR; /**< RLAR for the region. */ + uint32_t ulRBAR; /**< RBAR for the region. */ + uint32_t ulRLAR; /**< RLAR for the region. */ } MPURegionSettings_t; #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) @@ -203,9 +203,9 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P #error configSYSTEM_CALL_STACK_SIZE must be defined to the desired size of the system call stack in words for using MPU wrappers v2. #endif - /** - * @brief System call stack. - */ +/** + * @brief System call stack. + */ typedef struct SYSTEM_CALL_STACK_INFO { uint32_t ulSystemCallStackBuffer[ configSYSTEM_CALL_STACK_SIZE ]; @@ -218,74 +218,74 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P #endif /* configUSE_MPU_WRAPPERS_V1 == 0 */ - /** - * @brief MPU settings as stored in the TCB. - */ +/** + * @brief MPU settings as stored in the TCB. + */ #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) - #if( configENABLE_TRUSTZONE == 1 ) + #if ( configENABLE_TRUSTZONE == 1 ) - /* - * +-----------+---------------+----------+-----------------+------------------------------+-----+ - * | s16-s31 | s0-s15, FPSCR | r4-r11 | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, | | - * | | | | PC, xPSR | CONTROL, EXC_RETURN | | - * +-----------+---------------+----------+-----------------+------------------------------+-----+ - * - * <-----------><--------------><---------><----------------><-----------------------------><----> - * 16 16 8 8 5 1 - */ - #define MAX_CONTEXT_SIZE 54 +/* + * +-----------+---------------+----------+-----------------+------------------------------+-----+ + * | s16-s31 | s0-s15, FPSCR | r4-r11 | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, | | + * | | | | PC, xPSR | CONTROL, EXC_RETURN | | + * +-----------+---------------+----------+-----------------+------------------------------+-----+ + * + * <-----------><--------------><---------><----------------><-----------------------------><----> + * 16 16 8 8 5 1 + */ + #define MAX_CONTEXT_SIZE 54 #else /* #if( configENABLE_TRUSTZONE == 1 ) */ - /* - * +-----------+---------------+----------+-----------------+----------------------+-----+ - * | s16-s31 | s0-s15, FPSCR | r4-r11 | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL | | - * | | | | PC, xPSR | EXC_RETURN | | - * +-----------+---------------+----------+-----------------+----------------------+-----+ - * - * <-----------><--------------><---------><----------------><---------------------><----> - * 16 16 8 8 4 1 - */ - #define MAX_CONTEXT_SIZE 53 +/* + * +-----------+---------------+----------+-----------------+----------------------+-----+ + * | s16-s31 | s0-s15, FPSCR | r4-r11 | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL | | + * | | | | PC, xPSR | EXC_RETURN | | + * +-----------+---------------+----------+-----------------+----------------------+-----+ + * + * <-----------><--------------><---------><----------------><---------------------><----> + * 16 16 8 8 4 1 + */ + #define MAX_CONTEXT_SIZE 53 #endif /* #if( configENABLE_TRUSTZONE == 1 ) */ #else /* #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */ - #if( configENABLE_TRUSTZONE == 1 ) + #if ( configENABLE_TRUSTZONE == 1 ) - /* - * +----------+-----------------+------------------------------+-----+ - * | r4-r11 | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, | | - * | | PC, xPSR | CONTROL, EXC_RETURN | | - * +----------+-----------------+------------------------------+-----+ - * - * <---------><----------------><------------------------------><----> - * 8 8 5 1 - */ - #define MAX_CONTEXT_SIZE 22 +/* + * +----------+-----------------+------------------------------+-----+ + * | r4-r11 | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, | | + * | | PC, xPSR | CONTROL, EXC_RETURN | | + * +----------+-----------------+------------------------------+-----+ + * + * <---------><----------------><------------------------------><----> + * 8 8 5 1 + */ + #define MAX_CONTEXT_SIZE 22 #else /* #if( configENABLE_TRUSTZONE == 1 ) */ - /* - * +----------+-----------------+----------------------+-----+ - * | r4-r11 | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL | | - * | | PC, xPSR | EXC_RETURN | | - * +----------+-----------------+----------------------+-----+ - * - * <---------><----------------><----------------------><----> - * 8 8 4 1 - */ - #define MAX_CONTEXT_SIZE 21 +/* + * +----------+-----------------+----------------------+-----+ + * | r4-r11 | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL | | + * | | PC, xPSR | EXC_RETURN | | + * +----------+-----------------+----------------------+-----+ + * + * <---------><----------------><----------------------><----> + * 8 8 4 1 + */ + #define MAX_CONTEXT_SIZE 21 #endif /* #if( configENABLE_TRUSTZONE == 1 ) */ #endif /* #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */ - /* Flags used for xMPU_SETTINGS.ulTaskFlags member. */ - #define portSTACK_FRAME_HAS_PADDING_FLAG ( 1UL << 0UL ) - #define portTASK_IS_PRIVILEGED_FLAG ( 1UL << 1UL ) +/* Flags used for xMPU_SETTINGS.ulTaskFlags member. */ + #define portSTACK_FRAME_HAS_PADDING_FLAG ( 1UL << 0UL ) + #define portTASK_IS_PRIVILEGED_FLAG ( 1UL << 1UL ) /* Size of an Access Control List (ACL) entry in bits. */ #define portACL_ENTRY_SIZE_BITS ( 32U ) @@ -313,7 +313,7 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P * system calls. */ #ifdef configASSERT - #if ( portHAS_BASEPRI == 1 ) + #if ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) void vPortValidateInterruptPriority( void ); #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() vPortValidateInterruptPriority() #endif @@ -333,12 +333,29 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P /** * @brief Scheduler utilities. */ -#define portYIELD() vPortYield() +#if ( configENABLE_MPU == 1 ) + #define portYIELD() __asm volatile ( "svc %0" ::"i" ( portSVC_YIELD ) : "memory" ) + #define portYIELD_WITHIN_API() vPortYield() +#else + #define portYIELD() vPortYield() + #define portYIELD_WITHIN_API() vPortYield() +#endif + #define portNVIC_INT_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed04 ) ) #define portNVIC_PENDSVSET_BIT ( 1UL << 28UL ) -#define portEND_SWITCHING_ISR( xSwitchRequired ) \ - do { if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; } \ - while( 0 ) +#define portEND_SWITCHING_ISR( xSwitchRequired ) \ + do \ + { \ + if( xSwitchRequired ) \ + { \ + traceISR_EXIT_TO_SCHEDULER(); \ + portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; \ + } \ + else \ + { \ + traceISR_EXIT(); \ + } \ + } while( 0 ) #define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x ) /*-----------------------------------------------------------*/ @@ -424,12 +441,12 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P extern BaseType_t xPortIsTaskPrivileged( void ); - /** - * @brief Checks whether or not the calling task is privileged. - * - * @return pdTRUE if the calling task is privileged, pdFALSE otherwise. - */ - #define portIS_TASK_PRIVILEGED() xPortIsTaskPrivileged() +/** + * @brief Checks whether or not the calling task is privileged. + * + * @return pdTRUE if the calling task is privileged, pdFALSE otherwise. + */ + #define portIS_TASK_PRIVILEGED() xPortIsTaskPrivileged() #endif /* configENABLE_MPU == 1 */ /*-----------------------------------------------------------*/ @@ -440,6 +457,56 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P #define portMEMORY_BARRIER() __asm volatile ( "" ::: "memory" ) /*-----------------------------------------------------------*/ +/* Select correct value of configUSE_PORT_OPTIMISED_TASK_SELECTION + * based on whether or not Mainline extension is implemented. */ +#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION + #if ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) + #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1 + #else + #define configUSE_PORT_OPTIMISED_TASK_SELECTION 0 + #endif +#endif /* #ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION */ + +/** + * @brief Port-optimised task selection. + */ +#if ( configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 ) + +/** + * @brief Count the number of leading zeros in a 32-bit value. + */ + static portFORCE_INLINE uint32_t ulPortCountLeadingZeros( uint32_t ulBitmap ) + { + uint32_t ulReturn; + + __asm volatile ( "clz %0, %1" : "=r" ( ulReturn ) : "r" ( ulBitmap ) : "memory" ); + + return ulReturn; + } + +/* Check the configuration. */ + #if ( configMAX_PRIORITIES > 32 ) + #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 different priorities as tasks that share a priority will time slice. + #endif + + #if ( portHAS_ARMV8M_MAIN_EXTENSION == 0 ) + #error ARMv8-M baseline implementations (such as Cortex-M23) do not support port-optimised task selection. Please set configUSE_PORT_OPTIMISED_TASK_SELECTION to 0 or leave it undefined. + #endif + +/** + * @brief Store/clear the ready priorities in a bit map. + */ + #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) ) + #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) ) + +/** + * @brief Get the priority of the highest-priority task that is ready to execute. + */ + #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - ulPortCountLeadingZeros( ( uxReadyPriorities ) ) ) + +#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */ +/*-----------------------------------------------------------*/ + /* *INDENT-OFF* */ #ifdef __cplusplus } diff --git a/Source/portable/IAR/ARM_CM55/secure/secure_context.c b/Source/portable/IAR/ARM_CM55/secure/secure_context.c index e37dd9672..83b3dbce1 100644 --- a/Source/portable/IAR/ARM_CM55/secure/secure_context.c +++ b/Source/portable/IAR/ARM_CM55/secure/secure_context.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -65,7 +65,7 @@ * @brief Maximum number of secure contexts. */ #ifndef secureconfigMAX_SECURE_CONTEXTS - #define secureconfigMAX_SECURE_CONTEXTS 8UL + #define secureconfigMAX_SECURE_CONTEXTS 8UL #endif /*-----------------------------------------------------------*/ @@ -164,15 +164,15 @@ secureportNON_SECURE_CALLABLE void SecureContext_Init( void ) } #if ( configENABLE_MPU == 1 ) - { - /* Configure thread mode to use PSP and to be unprivileged. */ - secureportSET_CONTROL( securecontextCONTROL_VALUE_UNPRIVILEGED ); - } + { + /* Configure thread mode to use PSP and to be unprivileged. */ + secureportSET_CONTROL( securecontextCONTROL_VALUE_UNPRIVILEGED ); + } #else /* configENABLE_MPU */ - { - /* Configure thread mode to use PSP and to be privileged. */ - secureportSET_CONTROL( securecontextCONTROL_VALUE_PRIVILEGED ); - } + { + /* Configure thread mode to use PSP and to be privileged. */ + secureportSET_CONTROL( securecontextCONTROL_VALUE_PRIVILEGED ); + } #endif /* configENABLE_MPU */ } } @@ -219,16 +219,16 @@ secureportNON_SECURE_CALLABLE void SecureContext_Init( void ) if( pucStackMemory != NULL ) { /* Since stack grows down, the starting point will be the last - * location. Note that this location is next to the last - * allocated byte for stack (excluding the space for seal values) - * because the hardware decrements the stack pointer before - * writing i.e. if stack pointer is 0x2, a push operation will - * decrement the stack pointer to 0x1 and then write at 0x1. */ + * location. Note that this location is next to the last + * allocated byte for stack (excluding the space for seal values) + * because the hardware decrements the stack pointer before + * writing i.e. if stack pointer is 0x2, a push operation will + * decrement the stack pointer to 0x1 and then write at 0x1. */ xSecureContexts[ ulSecureContextIndex ].pucStackStart = pucStackMemory + ulSecureStackSize; /* Seal the created secure process stack. */ - *( uint32_t * )( pucStackMemory + ulSecureStackSize ) = securecontextSTACK_SEAL_VALUE; - *( uint32_t * )( pucStackMemory + ulSecureStackSize + 4 ) = securecontextSTACK_SEAL_VALUE; + *( uint32_t * ) ( pucStackMemory + ulSecureStackSize ) = securecontextSTACK_SEAL_VALUE; + *( uint32_t * ) ( pucStackMemory + ulSecureStackSize + 4 ) = securecontextSTACK_SEAL_VALUE; /* The stack cannot go beyond this location. This value is * programmed in the PSPLIM register on context switch.*/ @@ -237,32 +237,32 @@ secureportNON_SECURE_CALLABLE void SecureContext_Init( void ) xSecureContexts[ ulSecureContextIndex ].pvTaskHandle = pvTaskHandle; #if ( configENABLE_MPU == 1 ) + { + /* Store the correct CONTROL value for the task on the stack. + * This value is programmed in the CONTROL register on + * context switch. */ + pulCurrentStackPointer = ( uint32_t * ) xSecureContexts[ ulSecureContextIndex ].pucStackStart; + pulCurrentStackPointer--; + + if( ulIsTaskPrivileged ) { - /* Store the correct CONTROL value for the task on the stack. - * This value is programmed in the CONTROL register on - * context switch. */ - pulCurrentStackPointer = ( uint32_t * ) xSecureContexts[ ulSecureContextIndex ].pucStackStart; - pulCurrentStackPointer--; - - if( ulIsTaskPrivileged ) - { - *( pulCurrentStackPointer ) = securecontextCONTROL_VALUE_PRIVILEGED; - } - else - { - *( pulCurrentStackPointer ) = securecontextCONTROL_VALUE_UNPRIVILEGED; - } - - /* Store the current stack pointer. This value is programmed in - * the PSP register on context switch. */ - xSecureContexts[ ulSecureContextIndex ].pucCurrentStackPointer = ( uint8_t * ) pulCurrentStackPointer; + *( pulCurrentStackPointer ) = securecontextCONTROL_VALUE_PRIVILEGED; } - #else /* configENABLE_MPU */ + else { - /* Current SP is set to the starting of the stack. This - * value programmed in the PSP register on context switch. */ - xSecureContexts[ ulSecureContextIndex ].pucCurrentStackPointer = xSecureContexts[ ulSecureContextIndex ].pucStackStart; + *( pulCurrentStackPointer ) = securecontextCONTROL_VALUE_UNPRIVILEGED; } + + /* Store the current stack pointer. This value is programmed in + * the PSP register on context switch. */ + xSecureContexts[ ulSecureContextIndex ].pucCurrentStackPointer = ( uint8_t * ) pulCurrentStackPointer; + } + #else /* configENABLE_MPU */ + { + /* Current SP is set to the starting of the stack. This + * value programmed in the PSP register on context switch. */ + xSecureContexts[ ulSecureContextIndex ].pucCurrentStackPointer = xSecureContexts[ ulSecureContextIndex ].pucStackStart; + } #endif /* configENABLE_MPU */ /* Ensure to never return 0 as a valid context handle. */ @@ -275,7 +275,8 @@ secureportNON_SECURE_CALLABLE void SecureContext_Init( void ) } /*-----------------------------------------------------------*/ -secureportNON_SECURE_CALLABLE void SecureContext_FreeContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle ) +secureportNON_SECURE_CALLABLE void SecureContext_FreeContext( SecureContextHandle_t xSecureContextHandle, + void * pvTaskHandle ) { uint32_t ulIPSR, ulSecureContextIndex; @@ -306,7 +307,8 @@ secureportNON_SECURE_CALLABLE void SecureContext_FreeContext( SecureContextHandl } /*-----------------------------------------------------------*/ -secureportNON_SECURE_CALLABLE void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle ) +secureportNON_SECURE_CALLABLE void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle, + void * pvTaskHandle ) { uint8_t * pucStackLimit; uint32_t ulSecureContextIndex; @@ -328,7 +330,8 @@ secureportNON_SECURE_CALLABLE void SecureContext_LoadContext( SecureContextHandl } /*-----------------------------------------------------------*/ -secureportNON_SECURE_CALLABLE void SecureContext_SaveContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle ) +secureportNON_SECURE_CALLABLE void SecureContext_SaveContext( SecureContextHandle_t xSecureContextHandle, + void * pvTaskHandle ) { uint8_t * pucStackLimit; uint32_t ulSecureContextIndex; diff --git a/Source/portable/IAR/ARM_CM55/secure/secure_context.h b/Source/portable/IAR/ARM_CM55/secure/secure_context.h index 2220ea646..40fdc276d 100644 --- a/Source/portable/IAR/ARM_CM55/secure/secure_context.h +++ b/Source/portable/IAR/ARM_CM55/secure/secure_context.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -38,12 +38,12 @@ /** * @brief PSP value when no secure context is loaded. */ -#define securecontextNO_STACK 0x0 +#define securecontextNO_STACK 0x0 /** * @brief Invalid context ID. */ -#define securecontextINVALID_CONTEXT_ID 0UL +#define securecontextINVALID_CONTEXT_ID 0UL /*-----------------------------------------------------------*/ /** @@ -108,7 +108,8 @@ void SecureContext_Init( void ); * @param[in] xSecureContextHandle Context handle corresponding to the * context to be freed. */ -void SecureContext_FreeContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle ); +void SecureContext_FreeContext( SecureContextHandle_t xSecureContextHandle, + void * pvTaskHandle ); /** * @brief Loads the given context. @@ -119,7 +120,8 @@ void SecureContext_FreeContext( SecureContextHandle_t xSecureContextHandle, void * @param[in] xSecureContextHandle Context handle corresponding to the context * to be loaded. */ -void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle ); +void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle, + void * pvTaskHandle ); /** * @brief Saves the given context. @@ -130,6 +132,7 @@ void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle, void * @param[in] xSecureContextHandle Context handle corresponding to the context * to be saved. */ -void SecureContext_SaveContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle ); +void SecureContext_SaveContext( SecureContextHandle_t xSecureContextHandle, + void * pvTaskHandle ); #endif /* __SECURE_CONTEXT_H__ */ diff --git a/Source/portable/IAR/ARM_CM55/secure/secure_context_port_asm.s b/Source/portable/IAR/ARM_CM55/secure/secure_context_port_asm.s index 0da3e0f12..5124d9246 100644 --- a/Source/portable/IAR/ARM_CM55/secure/secure_context_port_asm.s +++ b/Source/portable/IAR/ARM_CM55/secure/secure_context_port_asm.s @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/Source/portable/IAR/ARM_CM55/secure/secure_heap.c b/Source/portable/IAR/ARM_CM55/secure/secure_heap.c index 19f7c2354..d9789404b 100644 --- a/Source/portable/IAR/ARM_CM55/secure/secure_heap.c +++ b/Source/portable/IAR/ARM_CM55/secure/secure_heap.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -62,6 +62,22 @@ /* Assumes 8bit bytes! */ #define secureheapBITS_PER_BYTE ( ( size_t ) 8 ) + +/* Max value that fits in a size_t type. */ +#define secureheapSIZE_MAX ( ~( ( size_t ) 0 ) ) + +/* Check if adding a and b will result in overflow. */ +#define secureheapADD_WILL_OVERFLOW( a, b ) ( ( a ) > ( secureheapSIZE_MAX - ( b ) ) ) + +/* MSB of the xBlockSize member of an BlockLink_t structure is used to track + * the allocation status of a block. When MSB of the xBlockSize member of + * an BlockLink_t structure is set then the block belongs to the application. + * When the bit is free the block is still part of the free heap space. */ +#define secureheapBLOCK_ALLOCATED_BITMASK ( ( ( size_t ) 1 ) << ( ( sizeof( size_t ) * secureheapBITS_PER_BYTE ) - 1 ) ) +#define secureheapBLOCK_SIZE_IS_VALID( xBlockSize ) ( ( ( xBlockSize ) & secureheapBLOCK_ALLOCATED_BITMASK ) == 0 ) +#define secureheapBLOCK_IS_ALLOCATED( pxBlock ) ( ( ( pxBlock->xBlockSize ) & secureheapBLOCK_ALLOCATED_BITMASK ) != 0 ) +#define secureheapALLOCATE_BLOCK( pxBlock ) ( ( pxBlock->xBlockSize ) |= secureheapBLOCK_ALLOCATED_BITMASK ) +#define secureheapFREE_BLOCK( pxBlock ) ( ( pxBlock->xBlockSize ) &= ~secureheapBLOCK_ALLOCATED_BITMASK ) /*-----------------------------------------------------------*/ /* Allocate the memory for the heap. */ @@ -123,14 +139,6 @@ static BlockLink_t * pxEnd = NULL; static size_t xFreeBytesRemaining = 0U; static size_t xMinimumEverFreeBytesRemaining = 0U; -/** - * @brief Gets set to the top bit of an size_t type. - * - * When this bit in the xBlockSize member of an BlockLink_t structure is set - * then the block belongs to the application. When the bit is free the block is - * still part of the free heap space. - */ -static size_t xBlockAllocatedBit = 0; /*-----------------------------------------------------------*/ static void prvHeapInit( void ) @@ -175,9 +183,6 @@ static void prvHeapInit( void ) /* Only one block exists - and it covers the entire usable heap space. */ xMinimumEverFreeBytesRemaining = pxFirstFreeBlock->xBlockSize; xFreeBytesRemaining = pxFirstFreeBlock->xBlockSize; - - /* Work out the position of the top bit in a size_t variable. */ - xBlockAllocatedBit = ( ( size_t ) 1 ) << ( ( sizeof( size_t ) * secureheapBITS_PER_BYTE ) - 1 ); } /*-----------------------------------------------------------*/ @@ -250,6 +255,7 @@ void * pvPortMalloc( size_t xWantedSize ) BlockLink_t * pxPreviousBlock; BlockLink_t * pxNewBlockLink; void * pvReturn = NULL; + size_t xAdditionalRequiredSize; /* If this is the first call to malloc then the heap will require * initialisation to setup the list of free blocks. */ @@ -262,25 +268,29 @@ void * pvPortMalloc( size_t xWantedSize ) mtCOVERAGE_TEST_MARKER(); } - /* Check the requested block size is not so large that the top bit is set. - * The top bit of the block size member of the BlockLink_t structure is used - * to determine who owns the block - the application or the kernel, so it - * must be free. */ - if( ( xWantedSize & xBlockAllocatedBit ) == 0 ) + if( xWantedSize > 0 ) { - /* The wanted size is increased so it can contain a BlockLink_t + /* The wanted size must be increased so it can contain a BlockLink_t * structure in addition to the requested amount of bytes. */ - if( xWantedSize > 0 ) + if( secureheapADD_WILL_OVERFLOW( xWantedSize, xHeapStructSize ) == 0 ) { xWantedSize += xHeapStructSize; - /* Ensure that blocks are always aligned to the required number of - * bytes. */ + /* Ensure that blocks are always aligned to the required number + * of bytes. */ if( ( xWantedSize & secureportBYTE_ALIGNMENT_MASK ) != 0x00 ) { /* Byte alignment required. */ - xWantedSize += ( secureportBYTE_ALIGNMENT - ( xWantedSize & secureportBYTE_ALIGNMENT_MASK ) ); - secureportASSERT( ( xWantedSize & secureportBYTE_ALIGNMENT_MASK ) == 0 ); + xAdditionalRequiredSize = secureportBYTE_ALIGNMENT - ( xWantedSize & secureportBYTE_ALIGNMENT_MASK ); + + if( secureheapADD_WILL_OVERFLOW( xWantedSize, xAdditionalRequiredSize ) == 0 ) + { + xWantedSize += xAdditionalRequiredSize; + } + else + { + xWantedSize = 0; + } } else { @@ -289,9 +299,20 @@ void * pvPortMalloc( size_t xWantedSize ) } else { - mtCOVERAGE_TEST_MARKER(); + xWantedSize = 0; } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + /* Check the requested block size is not so large that the top bit is set. + * The top bit of the block size member of the BlockLink_t structure is used + * to determine who owns the block - the application or the kernel, so it + * must be free. */ + if( secureheapBLOCK_SIZE_IS_VALID( xWantedSize ) != 0 ) + { if( ( xWantedSize > 0 ) && ( xWantedSize <= xFreeBytesRemaining ) ) { /* Traverse the list from the start (lowest address) block until @@ -334,7 +355,8 @@ void * pvPortMalloc( size_t xWantedSize ) pxBlock->xBlockSize = xWantedSize; /* Insert the new block into the list of free blocks. */ - prvInsertBlockIntoFreeList( pxNewBlockLink ); + pxNewBlockLink->pxNextFreeBlock = pxPreviousBlock->pxNextFreeBlock; + pxPreviousBlock->pxNextFreeBlock = pxNewBlockLink; } else { @@ -354,7 +376,7 @@ void * pvPortMalloc( size_t xWantedSize ) /* The block is being returned - it is allocated and owned by * the application and has no "next" block. */ - pxBlock->xBlockSize |= xBlockAllocatedBit; + secureheapALLOCATE_BLOCK( pxBlock ); pxBlock->pxNextFreeBlock = NULL; } else @@ -375,17 +397,17 @@ void * pvPortMalloc( size_t xWantedSize ) traceMALLOC( pvReturn, xWantedSize ); #if ( secureconfigUSE_MALLOC_FAILED_HOOK == 1 ) + { + if( pvReturn == NULL ) { - if( pvReturn == NULL ) - { - extern void vApplicationMallocFailedHook( void ); - vApplicationMallocFailedHook(); - } - else - { - mtCOVERAGE_TEST_MARKER(); - } + extern void vApplicationMallocFailedHook( void ); + vApplicationMallocFailedHook(); } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } #endif /* if ( secureconfigUSE_MALLOC_FAILED_HOOK == 1 ) */ secureportASSERT( ( ( ( size_t ) pvReturn ) & ( size_t ) secureportBYTE_ALIGNMENT_MASK ) == 0 ); @@ -408,16 +430,16 @@ void vPortFree( void * pv ) pxLink = ( void * ) puc; /* Check the block is actually allocated. */ - secureportASSERT( ( pxLink->xBlockSize & xBlockAllocatedBit ) != 0 ); + secureportASSERT( secureheapBLOCK_IS_ALLOCATED( pxLink ) != 0 ); secureportASSERT( pxLink->pxNextFreeBlock == NULL ); - if( ( pxLink->xBlockSize & xBlockAllocatedBit ) != 0 ) + if( secureheapBLOCK_IS_ALLOCATED( pxLink ) != 0 ) { if( pxLink->pxNextFreeBlock == NULL ) { /* The block is being returned to the heap - it is no longer * allocated. */ - pxLink->xBlockSize &= ~xBlockAllocatedBit; + secureheapFREE_BLOCK( pxLink ); secureportDISABLE_NON_SECURE_INTERRUPTS(); { diff --git a/Source/portable/IAR/ARM_CM55/secure/secure_heap.h b/Source/portable/IAR/ARM_CM55/secure/secure_heap.h index 75c9cb00b..cf5551046 100644 --- a/Source/portable/IAR/ARM_CM55/secure/secure_heap.h +++ b/Source/portable/IAR/ARM_CM55/secure/secure_heap.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/Source/portable/IAR/ARM_CM55/secure/secure_init.c b/Source/portable/IAR/ARM_CM55/secure/secure_init.c index f93bfce95..66d35eccc 100644 --- a/Source/portable/IAR/ARM_CM55/secure/secure_init.c +++ b/Source/portable/IAR/ARM_CM55/secure/secure_init.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -93,7 +93,7 @@ secureportNON_SECURE_CALLABLE void SecureInit_EnableNSFPUAccess( void ) * permitted. CP11 should be programmed to the same value as CP10. */ *( secureinitNSACR ) |= ( secureinitNSACR_CP10_MASK | secureinitNSACR_CP11_MASK ); - /* LSPENS = 0 ==> LSPEN is writable fron non-secure state. This ensures + /* LSPENS = 0 ==> LSPEN is writable from non-secure state. This ensures * that we can enable/disable lazy stacking in port.c file. */ *( secureinitFPCCR ) &= ~( secureinitFPCCR_LSPENS_MASK ); diff --git a/Source/portable/IAR/ARM_CM55/secure/secure_init.h b/Source/portable/IAR/ARM_CM55/secure/secure_init.h index e6c9da0b4..6404c5cc4 100644 --- a/Source/portable/IAR/ARM_CM55/secure/secure_init.h +++ b/Source/portable/IAR/ARM_CM55/secure/secure_init.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/Source/portable/IAR/ARM_CM55/secure/secure_port_macros.h b/Source/portable/IAR/ARM_CM55/secure/secure_port_macros.h index d7ac5833c..085108cc1 100644 --- a/Source/portable/IAR/ARM_CM55/secure/secure_port_macros.h +++ b/Source/portable/IAR/ARM_CM55/secure/secure_port_macros.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/Source/portable/IAR/ARM_CM55_NTZ/non_secure/mpu_wrappers_v2_asm.S b/Source/portable/IAR/ARM_CM55_NTZ/non_secure/mpu_wrappers_v2_asm.S index ef180bd91..b4f1fbc3b 100644 --- a/Source/portable/IAR/ARM_CM55_NTZ/non_secure/mpu_wrappers_v2_asm.S +++ b/Source/portable/IAR/ARM_CM55_NTZ/non_secure/mpu_wrappers_v2_asm.S @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -196,20 +196,6 @@ MPU_uxTaskGetNumberOfTasks: svc #SYSTEM_CALL_uxTaskGetNumberOfTasks /*-----------------------------------------------------------*/ - PUBLIC MPU_pcTaskGetName -MPU_pcTaskGetName: - push {r0} - mrs r0, control - tst r0, #1 - bne MPU_pcTaskGetName_Unpriv - MPU_pcTaskGetName_Priv: - pop {r0} - b MPU_pcTaskGetNameImpl - MPU_pcTaskGetName_Unpriv: - pop {r0} - svc #SYSTEM_CALL_pcTaskGetName -/*-----------------------------------------------------------*/ - PUBLIC MPU_ulTaskGetRunTimeCounter MPU_ulTaskGetRunTimeCounter: push {r0} @@ -742,24 +728,18 @@ MPU_xTimerGetTimerDaemonTaskHandle: svc #SYSTEM_CALL_xTimerGetTimerDaemonTaskHandle /*-----------------------------------------------------------*/ - PUBLIC MPU_xTimerGenericCommandEntry -MPU_xTimerGenericCommandEntry: + PUBLIC MPU_xTimerGenericCommandFromTaskEntry +MPU_xTimerGenericCommandFromTaskEntry: push {r0} - /* This function can be called from ISR also and therefore, we need a check - * to take privileged path, if called from ISR. */ - mrs r0, ipsr - cmp r0, #0 - bne MPU_xTimerGenericCommand_Priv mrs r0, control tst r0, #1 - beq MPU_xTimerGenericCommand_Priv - MPU_xTimerGenericCommand_Unpriv: + bne MPU_xTimerGenericCommandFromTask_Unpriv + MPU_xTimerGenericCommandFromTask_Priv: pop {r0} - svc #SYSTEM_CALL_xTimerGenericCommand - MPU_xTimerGenericCommand_Priv: + b MPU_xTimerGenericCommandFromTaskImpl + MPU_xTimerGenericCommandFromTask_Unpriv: pop {r0} - b MPU_xTimerGenericCommandPrivImpl - + svc #SYSTEM_CALL_xTimerGenericCommandFromTask /*-----------------------------------------------------------*/ PUBLIC MPU_pcTimerGetName @@ -1089,10 +1069,6 @@ MPU_xTaskGetTickCountImpl: MPU_uxTaskGetNumberOfTasksImpl: b MPU_uxTaskGetNumberOfTasksImpl - PUBWEAK MPU_pcTaskGetNameImpl -MPU_pcTaskGetNameImpl: - b MPU_pcTaskGetNameImpl - PUBWEAK MPU_ulTaskGetRunTimeCounterImpl MPU_ulTaskGetRunTimeCounterImpl: b MPU_ulTaskGetRunTimeCounterImpl @@ -1245,9 +1221,9 @@ MPU_xTimerIsTimerActiveImpl: MPU_xTimerGetTimerDaemonTaskHandleImpl: b MPU_xTimerGetTimerDaemonTaskHandleImpl - PUBWEAK MPU_xTimerGenericCommandPrivImpl -MPU_xTimerGenericCommandPrivImpl: - b MPU_xTimerGenericCommandPrivImpl + PUBWEAK MPU_xTimerGenericCommandFromTaskImpl +MPU_xTimerGenericCommandFromTaskImpl: + b MPU_xTimerGenericCommandFromTaskImpl PUBWEAK MPU_pcTimerGetNameImpl MPU_pcTimerGetNameImpl: diff --git a/Source/portable/IAR/ARM_CM55_NTZ/non_secure/port.c b/Source/portable/IAR/ARM_CM55_NTZ/non_secure/port.c index 9712ac353..230fe5fc2 100644 --- a/Source/portable/IAR/ARM_CM55_NTZ/non_secure/port.c +++ b/Source/portable/IAR/ARM_CM55_NTZ/non_secure/port.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -68,6 +68,22 @@ #if ( ( configRUN_FREERTOS_SECURE_ONLY == 1 ) && ( configENABLE_TRUSTZONE == 1 ) ) #error TrustZone needs to be disabled in order to run FreeRTOS on the Secure Side. #endif + +/** + * Cortex-M23 does not have non-secure PSPLIM. We should use PSPLIM on Cortex-M23 + * only when FreeRTOS runs on secure side. + */ +#if ( ( portHAS_ARMV8M_MAIN_EXTENSION == 0 ) && ( configRUN_FREERTOS_SECURE_ONLY == 0 ) ) + #define portUSE_PSPLIM_REGISTER 0 +#else + #define portUSE_PSPLIM_REGISTER 1 +#endif +/*-----------------------------------------------------------*/ + +/** + * @brief Prototype of all Interrupt Service Routines (ISRs). + */ +typedef void ( * portISR_t )( void ); /*-----------------------------------------------------------*/ /** @@ -91,10 +107,18 @@ /** * @brief Constants required to manipulate the SCB. */ -#define portSCB_SYS_HANDLER_CTRL_STATE_REG ( *( volatile uint32_t * ) 0xe000ed24 ) +#define portSCB_VTOR_REG ( *( ( portISR_t ** ) 0xe000ed08 ) ) +#define portSCB_SYS_HANDLER_CTRL_STATE_REG ( *( ( volatile uint32_t * ) 0xe000ed24 ) ) #define portSCB_MEM_FAULT_ENABLE_BIT ( 1UL << 16UL ) /*-----------------------------------------------------------*/ +/** + * @brief Constants used to check the installation of the FreeRTOS interrupt handlers. + */ +#define portVECTOR_INDEX_SVC ( 11 ) +#define portVECTOR_INDEX_PENDSV ( 14 ) +/*-----------------------------------------------------------*/ + /** * @brief Constants required to check the validity of an interrupt priority. */ @@ -111,8 +135,8 @@ /** * @brief Constants used during system call enter and exit. */ -#define portPSR_STACK_PADDING_MASK ( 1UL << 9UL ) -#define portEXC_RETURN_STACK_FRAME_TYPE_MASK ( 1UL << 4UL ) +#define portPSR_STACK_PADDING_MASK ( 1UL << 9UL ) +#define portEXC_RETURN_STACK_FRAME_TYPE_MASK ( 1UL << 4UL ) /*-----------------------------------------------------------*/ /** @@ -134,81 +158,81 @@ /** * @brief Offsets in the stack to the parameters when inside the SVC handler. */ -#define portOFFSET_TO_LR ( 5 ) -#define portOFFSET_TO_PC ( 6 ) -#define portOFFSET_TO_PSR ( 7 ) +#define portOFFSET_TO_LR ( 5 ) +#define portOFFSET_TO_PC ( 6 ) +#define portOFFSET_TO_PSR ( 7 ) /*-----------------------------------------------------------*/ /** * @brief Constants required to manipulate the MPU. */ -#define portMPU_TYPE_REG ( *( ( volatile uint32_t * ) 0xe000ed90 ) ) -#define portMPU_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed94 ) ) -#define portMPU_RNR_REG ( *( ( volatile uint32_t * ) 0xe000ed98 ) ) +#define portMPU_TYPE_REG ( *( ( volatile uint32_t * ) 0xe000ed90 ) ) +#define portMPU_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed94 ) ) +#define portMPU_RNR_REG ( *( ( volatile uint32_t * ) 0xe000ed98 ) ) -#define portMPU_RBAR_REG ( *( ( volatile uint32_t * ) 0xe000ed9c ) ) -#define portMPU_RLAR_REG ( *( ( volatile uint32_t * ) 0xe000eda0 ) ) +#define portMPU_RBAR_REG ( *( ( volatile uint32_t * ) 0xe000ed9c ) ) +#define portMPU_RLAR_REG ( *( ( volatile uint32_t * ) 0xe000eda0 ) ) -#define portMPU_RBAR_A1_REG ( *( ( volatile uint32_t * ) 0xe000eda4 ) ) -#define portMPU_RLAR_A1_REG ( *( ( volatile uint32_t * ) 0xe000eda8 ) ) +#define portMPU_RBAR_A1_REG ( *( ( volatile uint32_t * ) 0xe000eda4 ) ) +#define portMPU_RLAR_A1_REG ( *( ( volatile uint32_t * ) 0xe000eda8 ) ) -#define portMPU_RBAR_A2_REG ( *( ( volatile uint32_t * ) 0xe000edac ) ) -#define portMPU_RLAR_A2_REG ( *( ( volatile uint32_t * ) 0xe000edb0 ) ) +#define portMPU_RBAR_A2_REG ( *( ( volatile uint32_t * ) 0xe000edac ) ) +#define portMPU_RLAR_A2_REG ( *( ( volatile uint32_t * ) 0xe000edb0 ) ) -#define portMPU_RBAR_A3_REG ( *( ( volatile uint32_t * ) 0xe000edb4 ) ) -#define portMPU_RLAR_A3_REG ( *( ( volatile uint32_t * ) 0xe000edb8 ) ) +#define portMPU_RBAR_A3_REG ( *( ( volatile uint32_t * ) 0xe000edb4 ) ) +#define portMPU_RLAR_A3_REG ( *( ( volatile uint32_t * ) 0xe000edb8 ) ) -#define portMPU_MAIR0_REG ( *( ( volatile uint32_t * ) 0xe000edc0 ) ) -#define portMPU_MAIR1_REG ( *( ( volatile uint32_t * ) 0xe000edc4 ) ) +#define portMPU_MAIR0_REG ( *( ( volatile uint32_t * ) 0xe000edc0 ) ) +#define portMPU_MAIR1_REG ( *( ( volatile uint32_t * ) 0xe000edc4 ) ) -#define portMPU_RBAR_ADDRESS_MASK ( 0xffffffe0 ) /* Must be 32-byte aligned. */ -#define portMPU_RLAR_ADDRESS_MASK ( 0xffffffe0 ) /* Must be 32-byte aligned. */ +#define portMPU_RBAR_ADDRESS_MASK ( 0xffffffe0 ) /* Must be 32-byte aligned. */ +#define portMPU_RLAR_ADDRESS_MASK ( 0xffffffe0 ) /* Must be 32-byte aligned. */ -#define portMPU_RBAR_ACCESS_PERMISSIONS_MASK ( 3UL << 1UL ) +#define portMPU_RBAR_ACCESS_PERMISSIONS_MASK ( 3UL << 1UL ) -#define portMPU_MAIR_ATTR0_POS ( 0UL ) -#define portMPU_MAIR_ATTR0_MASK ( 0x000000ff ) +#define portMPU_MAIR_ATTR0_POS ( 0UL ) +#define portMPU_MAIR_ATTR0_MASK ( 0x000000ff ) -#define portMPU_MAIR_ATTR1_POS ( 8UL ) -#define portMPU_MAIR_ATTR1_MASK ( 0x0000ff00 ) +#define portMPU_MAIR_ATTR1_POS ( 8UL ) +#define portMPU_MAIR_ATTR1_MASK ( 0x0000ff00 ) -#define portMPU_MAIR_ATTR2_POS ( 16UL ) -#define portMPU_MAIR_ATTR2_MASK ( 0x00ff0000 ) +#define portMPU_MAIR_ATTR2_POS ( 16UL ) +#define portMPU_MAIR_ATTR2_MASK ( 0x00ff0000 ) -#define portMPU_MAIR_ATTR3_POS ( 24UL ) -#define portMPU_MAIR_ATTR3_MASK ( 0xff000000 ) +#define portMPU_MAIR_ATTR3_POS ( 24UL ) +#define portMPU_MAIR_ATTR3_MASK ( 0xff000000 ) -#define portMPU_MAIR_ATTR4_POS ( 0UL ) -#define portMPU_MAIR_ATTR4_MASK ( 0x000000ff ) +#define portMPU_MAIR_ATTR4_POS ( 0UL ) +#define portMPU_MAIR_ATTR4_MASK ( 0x000000ff ) -#define portMPU_MAIR_ATTR5_POS ( 8UL ) -#define portMPU_MAIR_ATTR5_MASK ( 0x0000ff00 ) +#define portMPU_MAIR_ATTR5_POS ( 8UL ) +#define portMPU_MAIR_ATTR5_MASK ( 0x0000ff00 ) -#define portMPU_MAIR_ATTR6_POS ( 16UL ) -#define portMPU_MAIR_ATTR6_MASK ( 0x00ff0000 ) +#define portMPU_MAIR_ATTR6_POS ( 16UL ) +#define portMPU_MAIR_ATTR6_MASK ( 0x00ff0000 ) -#define portMPU_MAIR_ATTR7_POS ( 24UL ) -#define portMPU_MAIR_ATTR7_MASK ( 0xff000000 ) +#define portMPU_MAIR_ATTR7_POS ( 24UL ) +#define portMPU_MAIR_ATTR7_MASK ( 0xff000000 ) -#define portMPU_RLAR_ATTR_INDEX0 ( 0UL << 1UL ) -#define portMPU_RLAR_ATTR_INDEX1 ( 1UL << 1UL ) -#define portMPU_RLAR_ATTR_INDEX2 ( 2UL << 1UL ) -#define portMPU_RLAR_ATTR_INDEX3 ( 3UL << 1UL ) -#define portMPU_RLAR_ATTR_INDEX4 ( 4UL << 1UL ) -#define portMPU_RLAR_ATTR_INDEX5 ( 5UL << 1UL ) -#define portMPU_RLAR_ATTR_INDEX6 ( 6UL << 1UL ) -#define portMPU_RLAR_ATTR_INDEX7 ( 7UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX0 ( 0UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX1 ( 1UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX2 ( 2UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX3 ( 3UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX4 ( 4UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX5 ( 5UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX6 ( 6UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX7 ( 7UL << 1UL ) -#define portMPU_RLAR_REGION_ENABLE ( 1UL ) +#define portMPU_RLAR_REGION_ENABLE ( 1UL ) /* Enable privileged access to unmapped region. */ -#define portMPU_PRIV_BACKGROUND_ENABLE_BIT ( 1UL << 2UL ) +#define portMPU_PRIV_BACKGROUND_ENABLE_BIT ( 1UL << 2UL ) /* Enable MPU. */ -#define portMPU_ENABLE_BIT ( 1UL << 0UL ) +#define portMPU_ENABLE_BIT ( 1UL << 0UL ) /* Expected value of the portMPU_TYPE register. */ -#define portEXPECTED_MPU_TYPE_VALUE ( configTOTAL_MPU_REGIONS << 8UL ) +#define portEXPECTED_MPU_TYPE_VALUE ( configTOTAL_MPU_REGIONS << 8UL ) /* Extract first address of the MPU region as encoded in the * RBAR (Region Base Address Register) value. */ @@ -448,13 +472,13 @@ portDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIV #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) - /** - * @brief Sets up the task stack so that upon returning from - * SVC, the task stack is used again. - * - * @param pulSystemCallStack The current SP when the SVC was raised. - * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler. - */ +/** + * @brief Sets up the task stack so that upon returning from + * SVC, the task stack is used again. + * + * @param pulSystemCallStack The current SP when the SVC was raised. + * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler. + */ void vSystemCallExit( uint32_t * pulSystemCallStack, uint32_t ulLR ) PRIVILEGED_FUNCTION; @@ -462,11 +486,11 @@ portDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIV #if ( configENABLE_MPU == 1 ) - /** - * @brief Checks whether or not the calling task is privileged. - * - * @return pdTRUE if the calling task is privileged, pdFALSE otherwise. - */ +/** + * @brief Checks whether or not the calling task is privileged. + * + * @return pdTRUE if the calling task is privileged, pdFALSE otherwise. + */ BaseType_t xPortIsTaskPrivileged( void ) PRIVILEGED_FUNCTION; #endif /* configENABLE_MPU == 1 */ @@ -501,13 +525,13 @@ PRIVILEGED_DATA static volatile uint32_t ulCriticalNesting = 0xaaaaaaaaUL; * FreeRTOS API functions are not called from interrupts that have been assigned * a priority above configMAX_SYSCALL_INTERRUPT_PRIORITY. */ -#if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) ) +#if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) static uint8_t ucMaxSysCallPriority = 0; static uint32_t ulMaxPRIGROUPValue = 0; static const volatile uint8_t * const pcInterruptPriorityRegisters = ( const volatile uint8_t * ) portNVIC_IP_REGISTERS_OFFSET_16; -#endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) ) */ +#endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */ #if ( configUSE_TICKLESS_IDLE == 1 ) @@ -760,8 +784,15 @@ __attribute__( ( weak ) ) void vPortSetupTimerInterrupt( void ) /* PRIVILEGED_FU } #endif /* configUSE_TICKLESS_IDLE */ - /* Stop and reset the SysTick. */ - portNVIC_SYSTICK_CTRL_REG = 0UL; + /* Stop and reset SysTick. + * + * QEMU versions older than 7.0.0 contain a bug which causes an error if we + * enable SysTick without first selecting a valid clock source. We trigger + * the bug if we change clock sources from a clock with a zero clock period + * to one with a nonzero clock period and enable Systick at the same time. + * So we configure the CLKSOURCE bit here, prior to setting the ENABLE bit. + * This workaround avoids the bug in QEMU versions older than 7.0.0. */ + portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT_CONFIG; portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL; /* Configure SysTick to interrupt at the requested rate. */ @@ -819,6 +850,7 @@ static void prvTaskExitError( void ) static void prvSetupMPU( void ) /* PRIVILEGED_FUNCTION */ { #if defined( __ARMCC_VERSION ) + /* Declaration when these variable are defined in code instead of being * exported from linker scripts. */ extern uint32_t * __privileged_functions_start__; @@ -972,13 +1004,19 @@ void SysTick_Handler( void ) /* PRIVILEGED_FUNCTION */ uint32_t ulPreviousMask; ulPreviousMask = portSET_INTERRUPT_MASK_FROM_ISR(); + traceISR_ENTER(); { /* Increment the RTOS tick. */ if( xTaskIncrementTick() != pdFALSE ) { + traceISR_EXIT_TO_SCHEDULER(); /* Pend a context switch. */ portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; } + else + { + traceISR_EXIT(); + } } portCLEAR_INTERRUPT_MASK_FROM_ISR( ulPreviousMask ); } @@ -988,6 +1026,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO { #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) ) #if defined( __ARMCC_VERSION ) + /* Declaration when these variable are defined in code instead of being * exported from linker scripts. */ extern uint32_t * __syscalls_flash_start__; @@ -1083,18 +1122,24 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO vRestoreContextOfFirstTask(); break; - #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) ) - case portSVC_RAISE_PRIVILEGE: + #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) ) + case portSVC_RAISE_PRIVILEGE: - /* Only raise the privilege, if the svc was raised from any of - * the system calls. */ - if( ( ulPC >= ( uint32_t ) __syscalls_flash_start__ ) && - ( ulPC <= ( uint32_t ) __syscalls_flash_end__ ) ) - { - vRaisePrivilege(); - } - break; - #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) */ + /* Only raise the privilege, if the svc was raised from any of + * the system calls. */ + if( ( ulPC >= ( uint32_t ) __syscalls_flash_start__ ) && + ( ulPC <= ( uint32_t ) __syscalls_flash_end__ ) ) + { + vRaisePrivilege(); + } + break; + #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) */ + + #if ( configENABLE_MPU == 1 ) + case portSVC_YIELD: + vPortYield(); + break; + #endif /* configENABLE_MPU == 1 */ default: /* Incorrect SVC call. */ @@ -1154,12 +1199,11 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO { /* Extended frame i.e. FPU in use. */ ulStackFrameSize = 26; - __asm volatile - ( + __asm volatile ( " vpush {s0} \n" /* Trigger lazy stacking. */ " vpop {s0} \n" /* Nullify the affect of the above instruction. */ ::: "memory" - ); + ); } else { @@ -1171,7 +1215,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO { ulStackFrameSize = 8; } - #endif /* if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */ + #endif /* configENABLE_FPU || configENABLE_MVE */ /* Make space on the system call stack for the stack frame. */ pulSystemCallStack = pulSystemCallStack - ulStackFrameSize; @@ -1187,18 +1231,24 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO * point (i.e. the caller of the MPU_). We need to restore it * when we exit from the system call. */ pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry = pulTaskStack[ portOFFSET_TO_LR ]; - /* Store the value of the PSPLIM register before the SVC was raised. * We need to restore it when we exit from the system call. */ - __asm volatile ( "mrs %0, psplim" : "=r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) ); + #if ( portUSE_PSPLIM_REGISTER == 1 ) + { + __asm volatile ( "mrs %0, psplim" : "=r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) ); + } + #endif /* Use the pulSystemCallStack in thread mode. */ __asm volatile ( "msr psp, %0" : : "r" ( pulSystemCallStack ) ); - __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) ); + #if ( portUSE_PSPLIM_REGISTER == 1 ) + { + __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) ); + } + #endif /* Start executing the system call upon returning from this handler. */ pulSystemCallStack[ portOFFSET_TO_PC ] = uxSystemCallImplementations[ ucSystemCallNumber ]; - /* Raise a request to exit from the system call upon finishing the * system call. */ pulSystemCallStack[ portOFFSET_TO_LR ] = ( uint32_t ) vRequestSystemCallExit; @@ -1224,14 +1274,13 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO pulSystemCallStack[ portOFFSET_TO_PSR ] &= ( ~portPSR_STACK_PADDING_MASK ); /* Raise the privilege for the duration of the system call. */ - __asm volatile - ( + __asm volatile ( " mrs r0, control \n" /* Obtain current control value. */ " movs r1, #1 \n" /* r1 = 1. */ " bics r0, r1 \n" /* Clear nPRIV bit. */ " msr control, r0 \n" /* Write back new control value. */ ::: "r0", "r1", "memory" - ); + ); } } @@ -1293,12 +1342,11 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO { /* Extended frame i.e. FPU in use. */ ulStackFrameSize = 26; - __asm volatile - ( + __asm volatile ( " vpush {s0} \n" /* Trigger lazy stacking. */ " vpop {s0} \n" /* Nullify the affect of the above instruction. */ ::: "memory" - ); + ); } else { @@ -1310,7 +1358,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO { ulStackFrameSize = 8; } - #endif /* if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */ + #endif /* configENABLE_FPU || configENABLE_MVE */ /* Make space on the task stack for the stack frame. */ pulTaskStack = pulTaskStack - ulStackFrameSize; @@ -1332,7 +1380,11 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO /* Restore the PSPLIM register to what it was at the time of * system call entry. */ - __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) ); + #if ( portUSE_PSPLIM_REGISTER == 1 ) + { + __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) ); + } + #endif /* If the hardware used padding to force the stack pointer * to be double word aligned, set the stacked xPSR bit[9], @@ -1350,14 +1402,13 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO pxMpuSettings->xSystemCallStackInfo.pulTaskStack = NULL; /* Drop the privilege before returning to the thread mode. */ - __asm volatile - ( + __asm volatile ( " mrs r0, control \n" /* Obtain current control value. */ " movs r1, #1 \n" /* r1 = 1. */ " orrs r0, r1 \n" /* Set nPRIV bit. */ " msr control, r0 \n" /* Write back new control value. */ ::: "r0", "r1", "memory" - ); + ); } } @@ -1410,21 +1461,21 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO xMPUSettings->ulContext[ ulIndex ] = 0x11111111; /* r11. */ ulIndex++; - xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pvParameters; /* r0. */ + xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pvParameters; /* r0. */ ulIndex++; - xMPUSettings->ulContext[ ulIndex ] = 0x01010101; /* r1. */ + xMPUSettings->ulContext[ ulIndex ] = 0x01010101; /* r1. */ ulIndex++; - xMPUSettings->ulContext[ ulIndex ] = 0x02020202; /* r2. */ + xMPUSettings->ulContext[ ulIndex ] = 0x02020202; /* r2. */ ulIndex++; - xMPUSettings->ulContext[ ulIndex ] = 0x03030303; /* r3. */ + xMPUSettings->ulContext[ ulIndex ] = 0x03030303; /* r3. */ ulIndex++; - xMPUSettings->ulContext[ ulIndex ] = 0x12121212; /* r12. */ + xMPUSettings->ulContext[ ulIndex ] = 0x12121212; /* r12. */ ulIndex++; xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portTASK_RETURN_ADDRESS; /* LR. */ ulIndex++; - xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxCode; /* PC. */ + xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxCode; /* PC. */ ulIndex++; - xMPUSettings->ulContext[ ulIndex ] = portINITIAL_XPSR; /* xPSR. */ + xMPUSettings->ulContext[ ulIndex ] = portINITIAL_XPSR; /* xPSR. */ ulIndex++; #if ( configENABLE_TRUSTZONE == 1 ) @@ -1435,8 +1486,9 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO #endif /* configENABLE_TRUSTZONE */ xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) ( pxTopOfStack - 8 ); /* PSP with the hardware saved stack. */ ulIndex++; - xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxEndOfStack; /* PSPLIM. */ + xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxEndOfStack; /* PSPLIM. */ ulIndex++; + if( xRunPrivileged == pdTRUE ) { xMPUSettings->ulTaskFlags |= portTASK_IS_PRIVILEGED_FLAG; @@ -1449,6 +1501,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portINITIAL_CONTROL_UNPRIVILEGED; /* CONTROL. */ ulIndex++; } + xMPUSettings->ulContext[ ulIndex ] = portINITIAL_EXC_RETURN; /* LR (EXC_RETURN). */ ulIndex++; @@ -1483,7 +1536,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO * interrupt. */ #if ( portPRELOAD_REGISTERS == 0 ) { - pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */ + pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */ *pxTopOfStack = portINITIAL_XPSR; /* xPSR. */ pxTopOfStack--; *pxTopOfStack = ( StackType_t ) pxCode; /* PC. */ @@ -1505,7 +1558,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO } #else /* portPRELOAD_REGISTERS */ { - pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */ + pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */ *pxTopOfStack = portINITIAL_XPSR; /* xPSR. */ pxTopOfStack--; *pxTopOfStack = ( StackType_t ) pxCode; /* PC. */ @@ -1540,7 +1593,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO pxTopOfStack--; *pxTopOfStack = portINITIAL_EXC_RETURN; /* EXC_RETURN. */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */ + *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */ #if ( configENABLE_TRUSTZONE == 1 ) { @@ -1559,22 +1612,52 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */ { - #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) ) + /* An application can install FreeRTOS interrupt handlers in one of the + * folllowing ways: + * 1. Direct Routing - Install the functions SVC_Handler and PendSV_Handler + * for SVCall and PendSV interrupts respectively. + * 2. Indirect Routing - Install separate handlers for SVCall and PendSV + * interrupts and route program control from those handlers to + * SVC_Handler and PendSV_Handler functions. + * + * Applications that use Indirect Routing must set + * configCHECK_HANDLER_INSTALLATION to 0 in their FreeRTOSConfig.h. Direct + * routing, which is validated here when configCHECK_HANDLER_INSTALLATION + * is 1, should be preferred when possible. */ + #if ( configCHECK_HANDLER_INSTALLATION == 1 ) + { + const portISR_t * const pxVectorTable = portSCB_VTOR_REG; + + /* Validate that the application has correctly installed the FreeRTOS + * handlers for SVCall and PendSV interrupts. We do not check the + * installation of the SysTick handler because the application may + * choose to drive the RTOS tick using a timer other than the SysTick + * timer by overriding the weak function vPortSetupTimerInterrupt(). + * + * Assertion failures here indicate incorrect installation of the + * FreeRTOS handlers. For help installing the FreeRTOS handlers, see + * https://www.FreeRTOS.org/FAQHelp.html. + * + * Systems with a configurable address for the interrupt vector table + * can also encounter assertion failures or even system faults here if + * VTOR is not set correctly to point to the application's vector table. */ + configASSERT( pxVectorTable[ portVECTOR_INDEX_SVC ] == SVC_Handler ); + configASSERT( pxVectorTable[ portVECTOR_INDEX_PENDSV ] == PendSV_Handler ); + } + #endif /* configCHECK_HANDLER_INSTALLATION */ + + #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) { - volatile uint32_t ulOriginalPriority; volatile uint32_t ulImplementedPrioBits = 0; volatile uint8_t ucMaxPriorityValue; /* Determine the maximum priority from which ISR safe FreeRTOS API - * functions can be called. ISR safe functions are those that end in - * "FromISR". FreeRTOS maintains separate thread and ISR API functions to + * functions can be called. ISR safe functions are those that end in + * "FromISR". FreeRTOS maintains separate thread and ISR API functions to * ensure interrupt entry is as fast and simple as possible. * - * Save the interrupt priority value that is about to be clobbered. */ - ulOriginalPriority = portNVIC_SHPR2_REG; - - /* Determine the number of priority bits available. First write to all - * possible bits. */ + * First, determine the number of priority bits available. Write to all + * possible bits in the priority setting for SVCall. */ portNVIC_SHPR2_REG = 0xFF000000; /* Read the value back to see how many bits stuck. */ @@ -1593,11 +1676,10 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */ /* Check that the bits not implemented in hardware are zero in * configMAX_SYSCALL_INTERRUPT_PRIORITY. */ - configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( ~ucMaxPriorityValue ) ) == 0U ); + configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( uint8_t ) ( ~( uint32_t ) ucMaxPriorityValue ) ) == 0U ); /* Calculate the maximum acceptable priority group value for the number * of bits read back. */ - while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE ) { ulImplementedPrioBits++; @@ -1635,16 +1717,14 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */ * register. */ ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT; ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK; - - /* Restore the clobbered interrupt priority register to its original - * value. */ - portNVIC_SHPR2_REG = ulOriginalPriority; } - #endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) ) */ + #endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */ - /* Make PendSV, CallSV and SysTick the same priority as the kernel. */ + /* Make PendSV and SysTick the lowest priority interrupts, and make SVCall + * the highest priority. */ portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI; portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI; + portNVIC_SHPR2_REG = 0; #if ( configENABLE_MPU == 1 ) { @@ -1701,6 +1781,7 @@ void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */ int32_t lIndex = 0; #if defined( __ARMCC_VERSION ) + /* Declaration when these variable are defined in code instead of being * exported from linker scripts. */ extern uint32_t * __privileged_sram_start__; @@ -1886,7 +1967,7 @@ BaseType_t xPortIsInsideInterrupt( void ) } /*-----------------------------------------------------------*/ -#if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) ) +#if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) void vPortValidateInterruptPriority( void ) { @@ -1944,7 +2025,7 @@ BaseType_t xPortIsInsideInterrupt( void ) configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue ); } -#endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) ) */ +#endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */ /*-----------------------------------------------------------*/ #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) diff --git a/Source/portable/IAR/ARM_CM55_NTZ/non_secure/portasm.h b/Source/portable/IAR/ARM_CM55_NTZ/non_secure/portasm.h index f64ceb525..c6d2ebd58 100644 --- a/Source/portable/IAR/ARM_CM55_NTZ/non_secure/portasm.h +++ b/Source/portable/IAR/ARM_CM55_NTZ/non_secure/portasm.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/Source/portable/IAR/ARM_CM55_NTZ/non_secure/portasm.s b/Source/portable/IAR/ARM_CM55_NTZ/non_secure/portasm.s index 00ee5a5cb..cb3ad91f9 100644 --- a/Source/portable/IAR/ARM_CM55_NTZ/non_secure/portasm.s +++ b/Source/portable/IAR/ARM_CM55_NTZ/non_secure/portasm.s @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/Source/portable/IAR/ARM_CM55_NTZ/non_secure/portmacro.h b/Source/portable/IAR/ARM_CM55_NTZ/non_secure/portmacro.h index d8d08f155..771a1bb3d 100644 --- a/Source/portable/IAR/ARM_CM55_NTZ/non_secure/portmacro.h +++ b/Source/portable/IAR/ARM_CM55_NTZ/non_secure/portmacro.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -53,16 +53,16 @@ /** * Architecture specifics. */ -#define portARCH_NAME "Cortex-M55" -#define portHAS_BASEPRI 1 -#define portDONT_DISCARD __root +#define portARCH_NAME "Cortex-M55" +#define portHAS_ARMV8M_MAIN_EXTENSION 1 +#define portDONT_DISCARD __root /*-----------------------------------------------------------*/ /* ARMv8-M common port configurations. */ #include "portmacrocommon.h" /*-----------------------------------------------------------*/ -#if( configTOTAL_MPU_REGIONS == 16 ) +#if ( configTOTAL_MPU_REGIONS == 16 ) #error 16 MPU regions are not yet supported for this port. #endif /*-----------------------------------------------------------*/ @@ -70,8 +70,8 @@ /** * @brief Critical section management. */ -#define portDISABLE_INTERRUPTS() ulSetInterruptMask() -#define portENABLE_INTERRUPTS() vClearInterruptMask( 0 ) +#define portDISABLE_INTERRUPTS() ulSetInterruptMask() +#define portENABLE_INTERRUPTS() vClearInterruptMask( 0 ) /*-----------------------------------------------------------*/ /* Suppress warnings that are generated by the IAR tools, but cannot be fixed in diff --git a/Source/portable/IAR/ARM_CM55_NTZ/non_secure/portmacrocommon.h b/Source/portable/IAR/ARM_CM55_NTZ/non_secure/portmacrocommon.h index 6f666da22..33f21d85b 100644 --- a/Source/portable/IAR/ARM_CM55_NTZ/non_secure/portmacrocommon.h +++ b/Source/portable/IAR/ARM_CM55_NTZ/non_secure/portmacrocommon.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -117,7 +117,7 @@ extern uint32_t ulSetInterruptMask( void ) /* __attribute__(( naked )) PRIVILEGE extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */; #if ( configENABLE_TRUSTZONE == 1 ) - extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize ); /* __attribute__ (( naked )) */ + extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize ); /* __attribute__ (( naked )) */ extern void vPortFreeSecureContext( uint32_t * pulTCB ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */; #endif /* configENABLE_TRUSTZONE */ @@ -188,13 +188,13 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P #if ( configENABLE_MPU == 1 ) - /** - * @brief Settings to define an MPU region. - */ +/** + * @brief Settings to define an MPU region. + */ typedef struct MPURegionSettings { - uint32_t ulRBAR; /**< RBAR for the region. */ - uint32_t ulRLAR; /**< RLAR for the region. */ + uint32_t ulRBAR; /**< RBAR for the region. */ + uint32_t ulRLAR; /**< RLAR for the region. */ } MPURegionSettings_t; #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) @@ -203,9 +203,9 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P #error configSYSTEM_CALL_STACK_SIZE must be defined to the desired size of the system call stack in words for using MPU wrappers v2. #endif - /** - * @brief System call stack. - */ +/** + * @brief System call stack. + */ typedef struct SYSTEM_CALL_STACK_INFO { uint32_t ulSystemCallStackBuffer[ configSYSTEM_CALL_STACK_SIZE ]; @@ -218,74 +218,74 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P #endif /* configUSE_MPU_WRAPPERS_V1 == 0 */ - /** - * @brief MPU settings as stored in the TCB. - */ +/** + * @brief MPU settings as stored in the TCB. + */ #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) - #if( configENABLE_TRUSTZONE == 1 ) + #if ( configENABLE_TRUSTZONE == 1 ) - /* - * +-----------+---------------+----------+-----------------+------------------------------+-----+ - * | s16-s31 | s0-s15, FPSCR | r4-r11 | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, | | - * | | | | PC, xPSR | CONTROL, EXC_RETURN | | - * +-----------+---------------+----------+-----------------+------------------------------+-----+ - * - * <-----------><--------------><---------><----------------><-----------------------------><----> - * 16 16 8 8 5 1 - */ - #define MAX_CONTEXT_SIZE 54 +/* + * +-----------+---------------+----------+-----------------+------------------------------+-----+ + * | s16-s31 | s0-s15, FPSCR | r4-r11 | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, | | + * | | | | PC, xPSR | CONTROL, EXC_RETURN | | + * +-----------+---------------+----------+-----------------+------------------------------+-----+ + * + * <-----------><--------------><---------><----------------><-----------------------------><----> + * 16 16 8 8 5 1 + */ + #define MAX_CONTEXT_SIZE 54 #else /* #if( configENABLE_TRUSTZONE == 1 ) */ - /* - * +-----------+---------------+----------+-----------------+----------------------+-----+ - * | s16-s31 | s0-s15, FPSCR | r4-r11 | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL | | - * | | | | PC, xPSR | EXC_RETURN | | - * +-----------+---------------+----------+-----------------+----------------------+-----+ - * - * <-----------><--------------><---------><----------------><---------------------><----> - * 16 16 8 8 4 1 - */ - #define MAX_CONTEXT_SIZE 53 +/* + * +-----------+---------------+----------+-----------------+----------------------+-----+ + * | s16-s31 | s0-s15, FPSCR | r4-r11 | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL | | + * | | | | PC, xPSR | EXC_RETURN | | + * +-----------+---------------+----------+-----------------+----------------------+-----+ + * + * <-----------><--------------><---------><----------------><---------------------><----> + * 16 16 8 8 4 1 + */ + #define MAX_CONTEXT_SIZE 53 #endif /* #if( configENABLE_TRUSTZONE == 1 ) */ #else /* #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */ - #if( configENABLE_TRUSTZONE == 1 ) + #if ( configENABLE_TRUSTZONE == 1 ) - /* - * +----------+-----------------+------------------------------+-----+ - * | r4-r11 | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, | | - * | | PC, xPSR | CONTROL, EXC_RETURN | | - * +----------+-----------------+------------------------------+-----+ - * - * <---------><----------------><------------------------------><----> - * 8 8 5 1 - */ - #define MAX_CONTEXT_SIZE 22 +/* + * +----------+-----------------+------------------------------+-----+ + * | r4-r11 | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, | | + * | | PC, xPSR | CONTROL, EXC_RETURN | | + * +----------+-----------------+------------------------------+-----+ + * + * <---------><----------------><------------------------------><----> + * 8 8 5 1 + */ + #define MAX_CONTEXT_SIZE 22 #else /* #if( configENABLE_TRUSTZONE == 1 ) */ - /* - * +----------+-----------------+----------------------+-----+ - * | r4-r11 | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL | | - * | | PC, xPSR | EXC_RETURN | | - * +----------+-----------------+----------------------+-----+ - * - * <---------><----------------><----------------------><----> - * 8 8 4 1 - */ - #define MAX_CONTEXT_SIZE 21 +/* + * +----------+-----------------+----------------------+-----+ + * | r4-r11 | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL | | + * | | PC, xPSR | EXC_RETURN | | + * +----------+-----------------+----------------------+-----+ + * + * <---------><----------------><----------------------><----> + * 8 8 4 1 + */ + #define MAX_CONTEXT_SIZE 21 #endif /* #if( configENABLE_TRUSTZONE == 1 ) */ #endif /* #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */ - /* Flags used for xMPU_SETTINGS.ulTaskFlags member. */ - #define portSTACK_FRAME_HAS_PADDING_FLAG ( 1UL << 0UL ) - #define portTASK_IS_PRIVILEGED_FLAG ( 1UL << 1UL ) +/* Flags used for xMPU_SETTINGS.ulTaskFlags member. */ + #define portSTACK_FRAME_HAS_PADDING_FLAG ( 1UL << 0UL ) + #define portTASK_IS_PRIVILEGED_FLAG ( 1UL << 1UL ) /* Size of an Access Control List (ACL) entry in bits. */ #define portACL_ENTRY_SIZE_BITS ( 32U ) @@ -313,7 +313,7 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P * system calls. */ #ifdef configASSERT - #if ( portHAS_BASEPRI == 1 ) + #if ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) void vPortValidateInterruptPriority( void ); #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() vPortValidateInterruptPriority() #endif @@ -333,12 +333,29 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P /** * @brief Scheduler utilities. */ -#define portYIELD() vPortYield() +#if ( configENABLE_MPU == 1 ) + #define portYIELD() __asm volatile ( "svc %0" ::"i" ( portSVC_YIELD ) : "memory" ) + #define portYIELD_WITHIN_API() vPortYield() +#else + #define portYIELD() vPortYield() + #define portYIELD_WITHIN_API() vPortYield() +#endif + #define portNVIC_INT_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed04 ) ) #define portNVIC_PENDSVSET_BIT ( 1UL << 28UL ) -#define portEND_SWITCHING_ISR( xSwitchRequired ) \ - do { if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; } \ - while( 0 ) +#define portEND_SWITCHING_ISR( xSwitchRequired ) \ + do \ + { \ + if( xSwitchRequired ) \ + { \ + traceISR_EXIT_TO_SCHEDULER(); \ + portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; \ + } \ + else \ + { \ + traceISR_EXIT(); \ + } \ + } while( 0 ) #define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x ) /*-----------------------------------------------------------*/ @@ -424,12 +441,12 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P extern BaseType_t xPortIsTaskPrivileged( void ); - /** - * @brief Checks whether or not the calling task is privileged. - * - * @return pdTRUE if the calling task is privileged, pdFALSE otherwise. - */ - #define portIS_TASK_PRIVILEGED() xPortIsTaskPrivileged() +/** + * @brief Checks whether or not the calling task is privileged. + * + * @return pdTRUE if the calling task is privileged, pdFALSE otherwise. + */ + #define portIS_TASK_PRIVILEGED() xPortIsTaskPrivileged() #endif /* configENABLE_MPU == 1 */ /*-----------------------------------------------------------*/ @@ -440,6 +457,56 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P #define portMEMORY_BARRIER() __asm volatile ( "" ::: "memory" ) /*-----------------------------------------------------------*/ +/* Select correct value of configUSE_PORT_OPTIMISED_TASK_SELECTION + * based on whether or not Mainline extension is implemented. */ +#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION + #if ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) + #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1 + #else + #define configUSE_PORT_OPTIMISED_TASK_SELECTION 0 + #endif +#endif /* #ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION */ + +/** + * @brief Port-optimised task selection. + */ +#if ( configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 ) + +/** + * @brief Count the number of leading zeros in a 32-bit value. + */ + static portFORCE_INLINE uint32_t ulPortCountLeadingZeros( uint32_t ulBitmap ) + { + uint32_t ulReturn; + + __asm volatile ( "clz %0, %1" : "=r" ( ulReturn ) : "r" ( ulBitmap ) : "memory" ); + + return ulReturn; + } + +/* Check the configuration. */ + #if ( configMAX_PRIORITIES > 32 ) + #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 different priorities as tasks that share a priority will time slice. + #endif + + #if ( portHAS_ARMV8M_MAIN_EXTENSION == 0 ) + #error ARMv8-M baseline implementations (such as Cortex-M23) do not support port-optimised task selection. Please set configUSE_PORT_OPTIMISED_TASK_SELECTION to 0 or leave it undefined. + #endif + +/** + * @brief Store/clear the ready priorities in a bit map. + */ + #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) ) + #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) ) + +/** + * @brief Get the priority of the highest-priority task that is ready to execute. + */ + #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - ulPortCountLeadingZeros( ( uxReadyPriorities ) ) ) + +#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */ +/*-----------------------------------------------------------*/ + /* *INDENT-OFF* */ #ifdef __cplusplus } diff --git a/Source/portable/IAR/ARM_CM7/r0p1/port.c b/Source/portable/IAR/ARM_CM7/r0p1/port.c index a04532b07..0d986aebd 100644 --- a/Source/portable/IAR/ARM_CM7/r0p1/port.c +++ b/Source/portable/IAR/ARM_CM7/r0p1/port.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -45,10 +45,14 @@ #error configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to 0. See http: /*www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */ #endif +/* Prototype of all Interrupt Service Routines (ISRs). */ +typedef void ( * portISR_t )( void ); + /* Constants required to manipulate the core. Registers first... */ #define portNVIC_SYSTICK_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000e010 ) ) #define portNVIC_SYSTICK_LOAD_REG ( *( ( volatile uint32_t * ) 0xe000e014 ) ) #define portNVIC_SYSTICK_CURRENT_VALUE_REG ( *( ( volatile uint32_t * ) 0xe000e018 ) ) +#define portNVIC_SHPR2_REG ( *( ( volatile uint32_t * ) 0xe000ed1c ) ) #define portNVIC_SHPR3_REG ( *( ( volatile uint32_t * ) 0xe000ed20 ) ) /* ...then bits in the registers. */ #define portNVIC_SYSTICK_CLK_BIT ( 1UL << 2UL ) @@ -63,6 +67,11 @@ #define portNVIC_PENDSV_PRI ( ( ( uint32_t ) portMIN_INTERRUPT_PRIORITY ) << 16UL ) #define portNVIC_SYSTICK_PRI ( ( ( uint32_t ) portMIN_INTERRUPT_PRIORITY ) << 24UL ) +/* Constants used to check the installation of the FreeRTOS interrupt handlers. */ +#define portSCB_VTOR_REG ( *( ( portISR_t ** ) 0xE000ED08 ) ) +#define portVECTOR_INDEX_SVC ( 11 ) +#define portVECTOR_INDEX_PENDSV ( 14 ) + /* Constants required to check the validity of an interrupt priority. */ #define portFIRST_USER_INTERRUPT_NUMBER ( 16 ) #define portNVIC_IP_REGISTERS_OFFSET_16 ( 0xE000E3F0 ) @@ -135,6 +144,11 @@ extern void vPortEnableVFP( void ); */ static void prvTaskExitError( void ); +/* + * FreeRTOS handlers implemented in assembly. + */ +extern void vPortSVCHandler( void ); +extern void xPortPendSVHandler( void ); /*-----------------------------------------------------------*/ /* Each task maintains its own interrupt status in the critical nesting @@ -234,6 +248,40 @@ static void prvTaskExitError( void ) */ BaseType_t xPortStartScheduler( void ) { + /* An application can install FreeRTOS interrupt handlers in one of the + * folllowing ways: + * 1. Direct Routing - Install the functions vPortSVCHandler and + * xPortPendSVHandler for SVCall and PendSV interrupts respectively. + * 2. Indirect Routing - Install separate handlers for SVCall and PendSV + * interrupts and route program control from those handlers to + * vPortSVCHandler and xPortPendSVHandler functions. + * + * Applications that use Indirect Routing must set + * configCHECK_HANDLER_INSTALLATION to 0 in their FreeRTOSConfig.h. Direct + * routing, which is validated here when configCHECK_HANDLER_INSTALLATION + * is 1, should be preferred when possible. */ + #if ( configCHECK_HANDLER_INSTALLATION == 1 ) + { + const portISR_t * const pxVectorTable = portSCB_VTOR_REG; + + /* Validate that the application has correctly installed the FreeRTOS + * handlers for SVCall and PendSV interrupts. We do not check the + * installation of the SysTick handler because the application may + * choose to drive the RTOS tick using a timer other than the SysTick + * timer by overriding the weak function vPortSetupTimerInterrupt(). + * + * Assertion failures here indicate incorrect installation of the + * FreeRTOS handlers. For help installing the FreeRTOS handlers, see + * https://www.FreeRTOS.org/FAQHelp.html. + * + * Systems with a configurable address for the interrupt vector table + * can also encounter assertion failures or even system faults here if + * VTOR is not set correctly to point to the application's vector table. */ + configASSERT( pxVectorTable[ portVECTOR_INDEX_SVC ] == vPortSVCHandler ); + configASSERT( pxVectorTable[ portVECTOR_INDEX_PENDSV ] == xPortPendSVHandler ); + } + #endif /* configCHECK_HANDLER_INSTALLATION */ + #if ( configASSERT_DEFINED == 1 ) { volatile uint8_t ucOriginalPriority; @@ -269,7 +317,7 @@ BaseType_t xPortStartScheduler( void ) /* Check that the bits not implemented in hardware are zero in * configMAX_SYSCALL_INTERRUPT_PRIORITY. */ - configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( ~ucMaxPriorityValue ) ) == 0U ); + configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( uint8_t ) ( ~( uint32_t ) ucMaxPriorityValue ) ) == 0U ); /* Calculate the maximum acceptable priority group value for the number * of bits read back. */ @@ -283,22 +331,22 @@ BaseType_t xPortStartScheduler( void ) if( ulImplementedPrioBits == 8 ) { /* When the hardware implements 8 priority bits, there is no way for - * the software to configure PRIGROUP to not have sub-priorities. As - * a result, the least significant bit is always used for sub-priority - * and there are 128 preemption priorities and 2 sub-priorities. - * - * This may cause some confusion in some cases - for example, if - * configMAX_SYSCALL_INTERRUPT_PRIORITY is set to 5, both 5 and 4 - * priority interrupts will be masked in Critical Sections as those - * are at the same preemption priority. This may appear confusing as - * 4 is higher (numerically lower) priority than - * configMAX_SYSCALL_INTERRUPT_PRIORITY and therefore, should not - * have been masked. Instead, if we set configMAX_SYSCALL_INTERRUPT_PRIORITY - * to 4, this confusion does not happen and the behaviour remains the same. - * - * The following assert ensures that the sub-priority bit in the - * configMAX_SYSCALL_INTERRUPT_PRIORITY is clear to avoid the above mentioned - * confusion. */ + * the software to configure PRIGROUP to not have sub-priorities. As + * a result, the least significant bit is always used for sub-priority + * and there are 128 preemption priorities and 2 sub-priorities. + * + * This may cause some confusion in some cases - for example, if + * configMAX_SYSCALL_INTERRUPT_PRIORITY is set to 5, both 5 and 4 + * priority interrupts will be masked in Critical Sections as those + * are at the same preemption priority. This may appear confusing as + * 4 is higher (numerically lower) priority than + * configMAX_SYSCALL_INTERRUPT_PRIORITY and therefore, should not + * have been masked. Instead, if we set configMAX_SYSCALL_INTERRUPT_PRIORITY + * to 4, this confusion does not happen and the behaviour remains the same. + * + * The following assert ensures that the sub-priority bit in the + * configMAX_SYSCALL_INTERRUPT_PRIORITY is clear to avoid the above mentioned + * confusion. */ configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & 0x1U ) == 0U ); ulMaxPRIGROUPValue = 0; } @@ -318,9 +366,11 @@ BaseType_t xPortStartScheduler( void ) } #endif /* configASSERT_DEFINED */ - /* Make PendSV and SysTick the lowest priority interrupts. */ + /* Make PendSV and SysTick the lowest priority interrupts, and make SVCall + * the highest priority. */ portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI; portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI; + portNVIC_SHPR2_REG = 0; /* Start the timer that generates the tick ISR. Interrupts are disabled * here already. */ @@ -387,14 +437,21 @@ void xPortSysTickHandler( void ) * save and then restore the interrupt mask value as its value is already * known. */ portDISABLE_INTERRUPTS(); + traceISR_ENTER(); { /* Increment the RTOS tick. */ if( xTaskIncrementTick() != pdFALSE ) { + traceISR_EXIT_TO_SCHEDULER(); + /* A context switch is required. Context switching is performed in * the PendSV interrupt. Pend the PendSV interrupt. */ portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; } + else + { + traceISR_EXIT(); + } } portENABLE_INTERRUPTS(); } diff --git a/Source/portable/IAR/ARM_CM7/r0p1/portasm.s b/Source/portable/IAR/ARM_CM7/r0p1/portasm.s index 19cc6cdc3..2aa190760 100644 --- a/Source/portable/IAR/ARM_CM7/r0p1/portasm.s +++ b/Source/portable/IAR/ARM_CM7/r0p1/portasm.s @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/Source/portable/IAR/ARM_CM7/r0p1/portmacro.h b/Source/portable/IAR/ARM_CM7/r0p1/portmacro.h index f93146e8f..990392893 100644 --- a/Source/portable/IAR/ARM_CM7/r0p1/portmacro.h +++ b/Source/portable/IAR/ARM_CM7/r0p1/portmacro.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -27,7 +27,7 @@ */ #ifndef PORTMACRO_H - #define PORTMACRO_H +#define PORTMACRO_H /* *INDENT-OFF* */ #ifdef __cplusplus @@ -46,50 +46,50 @@ */ /* IAR includes. */ - #include +#include /* Type definitions. */ - #define portCHAR char - #define portFLOAT float - #define portDOUBLE double - #define portLONG long - #define portSHORT short - #define portSTACK_TYPE uint32_t - #define portBASE_TYPE long - - typedef portSTACK_TYPE StackType_t; - typedef long BaseType_t; - typedef unsigned long UBaseType_t; - - #if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS ) - typedef uint16_t TickType_t; - #define portMAX_DELAY ( TickType_t ) 0xffff - #elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS ) - typedef uint32_t TickType_t; - #define portMAX_DELAY ( TickType_t ) 0xffffffffUL +#define portCHAR char +#define portFLOAT float +#define portDOUBLE double +#define portLONG long +#define portSHORT short +#define portSTACK_TYPE uint32_t +#define portBASE_TYPE long + +typedef portSTACK_TYPE StackType_t; +typedef long BaseType_t; +typedef unsigned long UBaseType_t; + +#if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS ) + typedef uint16_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffff +#elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS ) + typedef uint32_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffffffffUL /* 32-bit tick type on a 32-bit architecture, so reads of the tick count do * not need to be guarded with a critical section. */ - #define portTICK_TYPE_IS_ATOMIC 1 - #else - #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width. - #endif + #define portTICK_TYPE_IS_ATOMIC 1 +#else + #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width. +#endif /*-----------------------------------------------------------*/ /* Architecture specifics. */ - #define portSTACK_GROWTH ( -1 ) - #define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) - #define portBYTE_ALIGNMENT 8 +#define portSTACK_GROWTH ( -1 ) +#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) +#define portBYTE_ALIGNMENT 8 /*-----------------------------------------------------------*/ /* Compiler directives. */ - #define portWEAK_SYMBOL __attribute__( ( weak ) ) +#define portWEAK_SYMBOL __attribute__( ( weak ) ) /*-----------------------------------------------------------*/ /* Scheduler utilities. */ - #define portYIELD() \ +#define portYIELD() \ { \ /* Set a PendSV to request a context switch. */ \ portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; \ @@ -97,41 +97,53 @@ __ISB(); \ } - #define portNVIC_INT_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed04 ) ) - #define portNVIC_PENDSVSET_BIT ( 1UL << 28UL ) - #define portEND_SWITCHING_ISR( xSwitchRequired ) do { if( xSwitchRequired != pdFALSE ) portYIELD(); } while( 0 ) - #define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x ) +#define portNVIC_INT_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed04 ) ) +#define portNVIC_PENDSVSET_BIT ( 1UL << 28UL ) +#define portEND_SWITCHING_ISR( xSwitchRequired ) \ + do \ + { \ + if( xSwitchRequired != pdFALSE ) \ + { \ + traceISR_EXIT_TO_SCHEDULER(); \ + portYIELD(); \ + } \ + else \ + { \ + traceISR_EXIT(); \ + } \ + } while( 0 ) +#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x ) /*-----------------------------------------------------------*/ /* Architecture specific optimisations. */ - #ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION - #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1 - #endif +#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION + #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1 +#endif - #if ( configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 ) +#if ( configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 ) /* Check the configuration. */ - #if ( configMAX_PRIORITIES > 32 ) - #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice. - #endif + #if ( configMAX_PRIORITIES > 32 ) + #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice. + #endif /* Store/clear the ready priorities in a bit map. */ - #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) ) - #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) ) + #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) ) + #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) ) /*-----------------------------------------------------------*/ - #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - ( ( uint32_t ) __CLZ( ( uxReadyPriorities ) ) ) ) + #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - ( ( uint32_t ) __CLZ( ( uxReadyPriorities ) ) ) ) - #endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */ +#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */ /*-----------------------------------------------------------*/ /* Critical section management. */ - extern void vPortEnterCritical( void ); - extern void vPortExitCritical( void ); +extern void vPortEnterCritical( void ); +extern void vPortExitCritical( void ); - #define portDISABLE_INTERRUPTS() \ +#define portDISABLE_INTERRUPTS() \ { \ /* Errata work around. */ \ __disable_interrupt(); \ @@ -141,71 +153,71 @@ __enable_interrupt(); \ } - #define portENABLE_INTERRUPTS() __set_BASEPRI( 0 ) - #define portENTER_CRITICAL() vPortEnterCritical() - #define portEXIT_CRITICAL() vPortExitCritical() - #define portSET_INTERRUPT_MASK_FROM_ISR() __get_BASEPRI(); portDISABLE_INTERRUPTS() - #define portCLEAR_INTERRUPT_MASK_FROM_ISR( x ) __set_BASEPRI( x ) +#define portENABLE_INTERRUPTS() __set_BASEPRI( 0 ) +#define portENTER_CRITICAL() vPortEnterCritical() +#define portEXIT_CRITICAL() vPortExitCritical() +#define portSET_INTERRUPT_MASK_FROM_ISR() __get_BASEPRI(); portDISABLE_INTERRUPTS() +#define portCLEAR_INTERRUPT_MASK_FROM_ISR( x ) __set_BASEPRI( x ) /*-----------------------------------------------------------*/ /* Tickless idle/low power functionality. */ - #ifndef portSUPPRESS_TICKS_AND_SLEEP - extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime ); - #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime ) vPortSuppressTicksAndSleep( xExpectedIdleTime ) - #endif +#ifndef portSUPPRESS_TICKS_AND_SLEEP + extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime ); + #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime ) vPortSuppressTicksAndSleep( xExpectedIdleTime ) +#endif /*-----------------------------------------------------------*/ /* Task function macros as described on the FreeRTOS.org WEB site. These are * not necessary for to use this port. They are defined so the common demo files * (which build with all the ports) will build. */ - #define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters ) - #define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters ) +#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters ) +#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters ) /*-----------------------------------------------------------*/ - #ifdef configASSERT - void vPortValidateInterruptPriority( void ); - #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() vPortValidateInterruptPriority() - #endif +#ifdef configASSERT + void vPortValidateInterruptPriority( void ); + #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() vPortValidateInterruptPriority() +#endif /* portNOP() is not required by this port. */ - #define portNOP() +#define portNOP() - #define portINLINE __inline +#define portINLINE __inline - #ifndef portFORCE_INLINE - #define portFORCE_INLINE inline __attribute__( ( always_inline ) ) - #endif +#ifndef portFORCE_INLINE + #define portFORCE_INLINE inline __attribute__( ( always_inline ) ) +#endif /*-----------------------------------------------------------*/ - portFORCE_INLINE static BaseType_t xPortIsInsideInterrupt( void ) +portFORCE_INLINE static BaseType_t xPortIsInsideInterrupt( void ) +{ + uint32_t ulCurrentInterrupt; + BaseType_t xReturn; + + /* Obtain the number of the currently executing interrupt. */ + __asm volatile ( "mrs %0, ipsr" : "=r" ( ulCurrentInterrupt )::"memory" ); + + if( ulCurrentInterrupt == 0 ) + { + xReturn = pdFALSE; + } + else { - uint32_t ulCurrentInterrupt; - BaseType_t xReturn; - - /* Obtain the number of the currently executing interrupt. */ - __asm volatile ( "mrs %0, ipsr" : "=r" ( ulCurrentInterrupt )::"memory" ); - - if( ulCurrentInterrupt == 0 ) - { - xReturn = pdFALSE; - } - else - { - xReturn = pdTRUE; - } - - return xReturn; + xReturn = pdTRUE; } + return xReturn; +} + /*-----------------------------------------------------------*/ /* Suppress warnings that are generated by the IAR tools, but cannot be fixed in * the source code because to do so would cause other compilers to generate * warnings. */ - #pragma diag_suppress=Pe191 - #pragma diag_suppress=Pa082 +#pragma diag_suppress=Pe191 +#pragma diag_suppress=Pa082 /* *INDENT-OFF* */ #ifdef __cplusplus diff --git a/Source/portable/IAR/ARM_CM85/non_secure/mpu_wrappers_v2_asm.S b/Source/portable/IAR/ARM_CM85/non_secure/mpu_wrappers_v2_asm.S index ef180bd91..b4f1fbc3b 100644 --- a/Source/portable/IAR/ARM_CM85/non_secure/mpu_wrappers_v2_asm.S +++ b/Source/portable/IAR/ARM_CM85/non_secure/mpu_wrappers_v2_asm.S @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -196,20 +196,6 @@ MPU_uxTaskGetNumberOfTasks: svc #SYSTEM_CALL_uxTaskGetNumberOfTasks /*-----------------------------------------------------------*/ - PUBLIC MPU_pcTaskGetName -MPU_pcTaskGetName: - push {r0} - mrs r0, control - tst r0, #1 - bne MPU_pcTaskGetName_Unpriv - MPU_pcTaskGetName_Priv: - pop {r0} - b MPU_pcTaskGetNameImpl - MPU_pcTaskGetName_Unpriv: - pop {r0} - svc #SYSTEM_CALL_pcTaskGetName -/*-----------------------------------------------------------*/ - PUBLIC MPU_ulTaskGetRunTimeCounter MPU_ulTaskGetRunTimeCounter: push {r0} @@ -742,24 +728,18 @@ MPU_xTimerGetTimerDaemonTaskHandle: svc #SYSTEM_CALL_xTimerGetTimerDaemonTaskHandle /*-----------------------------------------------------------*/ - PUBLIC MPU_xTimerGenericCommandEntry -MPU_xTimerGenericCommandEntry: + PUBLIC MPU_xTimerGenericCommandFromTaskEntry +MPU_xTimerGenericCommandFromTaskEntry: push {r0} - /* This function can be called from ISR also and therefore, we need a check - * to take privileged path, if called from ISR. */ - mrs r0, ipsr - cmp r0, #0 - bne MPU_xTimerGenericCommand_Priv mrs r0, control tst r0, #1 - beq MPU_xTimerGenericCommand_Priv - MPU_xTimerGenericCommand_Unpriv: + bne MPU_xTimerGenericCommandFromTask_Unpriv + MPU_xTimerGenericCommandFromTask_Priv: pop {r0} - svc #SYSTEM_CALL_xTimerGenericCommand - MPU_xTimerGenericCommand_Priv: + b MPU_xTimerGenericCommandFromTaskImpl + MPU_xTimerGenericCommandFromTask_Unpriv: pop {r0} - b MPU_xTimerGenericCommandPrivImpl - + svc #SYSTEM_CALL_xTimerGenericCommandFromTask /*-----------------------------------------------------------*/ PUBLIC MPU_pcTimerGetName @@ -1089,10 +1069,6 @@ MPU_xTaskGetTickCountImpl: MPU_uxTaskGetNumberOfTasksImpl: b MPU_uxTaskGetNumberOfTasksImpl - PUBWEAK MPU_pcTaskGetNameImpl -MPU_pcTaskGetNameImpl: - b MPU_pcTaskGetNameImpl - PUBWEAK MPU_ulTaskGetRunTimeCounterImpl MPU_ulTaskGetRunTimeCounterImpl: b MPU_ulTaskGetRunTimeCounterImpl @@ -1245,9 +1221,9 @@ MPU_xTimerIsTimerActiveImpl: MPU_xTimerGetTimerDaemonTaskHandleImpl: b MPU_xTimerGetTimerDaemonTaskHandleImpl - PUBWEAK MPU_xTimerGenericCommandPrivImpl -MPU_xTimerGenericCommandPrivImpl: - b MPU_xTimerGenericCommandPrivImpl + PUBWEAK MPU_xTimerGenericCommandFromTaskImpl +MPU_xTimerGenericCommandFromTaskImpl: + b MPU_xTimerGenericCommandFromTaskImpl PUBWEAK MPU_pcTimerGetNameImpl MPU_pcTimerGetNameImpl: diff --git a/Source/portable/IAR/ARM_CM85/non_secure/port.c b/Source/portable/IAR/ARM_CM85/non_secure/port.c index 9712ac353..230fe5fc2 100644 --- a/Source/portable/IAR/ARM_CM85/non_secure/port.c +++ b/Source/portable/IAR/ARM_CM85/non_secure/port.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -68,6 +68,22 @@ #if ( ( configRUN_FREERTOS_SECURE_ONLY == 1 ) && ( configENABLE_TRUSTZONE == 1 ) ) #error TrustZone needs to be disabled in order to run FreeRTOS on the Secure Side. #endif + +/** + * Cortex-M23 does not have non-secure PSPLIM. We should use PSPLIM on Cortex-M23 + * only when FreeRTOS runs on secure side. + */ +#if ( ( portHAS_ARMV8M_MAIN_EXTENSION == 0 ) && ( configRUN_FREERTOS_SECURE_ONLY == 0 ) ) + #define portUSE_PSPLIM_REGISTER 0 +#else + #define portUSE_PSPLIM_REGISTER 1 +#endif +/*-----------------------------------------------------------*/ + +/** + * @brief Prototype of all Interrupt Service Routines (ISRs). + */ +typedef void ( * portISR_t )( void ); /*-----------------------------------------------------------*/ /** @@ -91,10 +107,18 @@ /** * @brief Constants required to manipulate the SCB. */ -#define portSCB_SYS_HANDLER_CTRL_STATE_REG ( *( volatile uint32_t * ) 0xe000ed24 ) +#define portSCB_VTOR_REG ( *( ( portISR_t ** ) 0xe000ed08 ) ) +#define portSCB_SYS_HANDLER_CTRL_STATE_REG ( *( ( volatile uint32_t * ) 0xe000ed24 ) ) #define portSCB_MEM_FAULT_ENABLE_BIT ( 1UL << 16UL ) /*-----------------------------------------------------------*/ +/** + * @brief Constants used to check the installation of the FreeRTOS interrupt handlers. + */ +#define portVECTOR_INDEX_SVC ( 11 ) +#define portVECTOR_INDEX_PENDSV ( 14 ) +/*-----------------------------------------------------------*/ + /** * @brief Constants required to check the validity of an interrupt priority. */ @@ -111,8 +135,8 @@ /** * @brief Constants used during system call enter and exit. */ -#define portPSR_STACK_PADDING_MASK ( 1UL << 9UL ) -#define portEXC_RETURN_STACK_FRAME_TYPE_MASK ( 1UL << 4UL ) +#define portPSR_STACK_PADDING_MASK ( 1UL << 9UL ) +#define portEXC_RETURN_STACK_FRAME_TYPE_MASK ( 1UL << 4UL ) /*-----------------------------------------------------------*/ /** @@ -134,81 +158,81 @@ /** * @brief Offsets in the stack to the parameters when inside the SVC handler. */ -#define portOFFSET_TO_LR ( 5 ) -#define portOFFSET_TO_PC ( 6 ) -#define portOFFSET_TO_PSR ( 7 ) +#define portOFFSET_TO_LR ( 5 ) +#define portOFFSET_TO_PC ( 6 ) +#define portOFFSET_TO_PSR ( 7 ) /*-----------------------------------------------------------*/ /** * @brief Constants required to manipulate the MPU. */ -#define portMPU_TYPE_REG ( *( ( volatile uint32_t * ) 0xe000ed90 ) ) -#define portMPU_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed94 ) ) -#define portMPU_RNR_REG ( *( ( volatile uint32_t * ) 0xe000ed98 ) ) +#define portMPU_TYPE_REG ( *( ( volatile uint32_t * ) 0xe000ed90 ) ) +#define portMPU_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed94 ) ) +#define portMPU_RNR_REG ( *( ( volatile uint32_t * ) 0xe000ed98 ) ) -#define portMPU_RBAR_REG ( *( ( volatile uint32_t * ) 0xe000ed9c ) ) -#define portMPU_RLAR_REG ( *( ( volatile uint32_t * ) 0xe000eda0 ) ) +#define portMPU_RBAR_REG ( *( ( volatile uint32_t * ) 0xe000ed9c ) ) +#define portMPU_RLAR_REG ( *( ( volatile uint32_t * ) 0xe000eda0 ) ) -#define portMPU_RBAR_A1_REG ( *( ( volatile uint32_t * ) 0xe000eda4 ) ) -#define portMPU_RLAR_A1_REG ( *( ( volatile uint32_t * ) 0xe000eda8 ) ) +#define portMPU_RBAR_A1_REG ( *( ( volatile uint32_t * ) 0xe000eda4 ) ) +#define portMPU_RLAR_A1_REG ( *( ( volatile uint32_t * ) 0xe000eda8 ) ) -#define portMPU_RBAR_A2_REG ( *( ( volatile uint32_t * ) 0xe000edac ) ) -#define portMPU_RLAR_A2_REG ( *( ( volatile uint32_t * ) 0xe000edb0 ) ) +#define portMPU_RBAR_A2_REG ( *( ( volatile uint32_t * ) 0xe000edac ) ) +#define portMPU_RLAR_A2_REG ( *( ( volatile uint32_t * ) 0xe000edb0 ) ) -#define portMPU_RBAR_A3_REG ( *( ( volatile uint32_t * ) 0xe000edb4 ) ) -#define portMPU_RLAR_A3_REG ( *( ( volatile uint32_t * ) 0xe000edb8 ) ) +#define portMPU_RBAR_A3_REG ( *( ( volatile uint32_t * ) 0xe000edb4 ) ) +#define portMPU_RLAR_A3_REG ( *( ( volatile uint32_t * ) 0xe000edb8 ) ) -#define portMPU_MAIR0_REG ( *( ( volatile uint32_t * ) 0xe000edc0 ) ) -#define portMPU_MAIR1_REG ( *( ( volatile uint32_t * ) 0xe000edc4 ) ) +#define portMPU_MAIR0_REG ( *( ( volatile uint32_t * ) 0xe000edc0 ) ) +#define portMPU_MAIR1_REG ( *( ( volatile uint32_t * ) 0xe000edc4 ) ) -#define portMPU_RBAR_ADDRESS_MASK ( 0xffffffe0 ) /* Must be 32-byte aligned. */ -#define portMPU_RLAR_ADDRESS_MASK ( 0xffffffe0 ) /* Must be 32-byte aligned. */ +#define portMPU_RBAR_ADDRESS_MASK ( 0xffffffe0 ) /* Must be 32-byte aligned. */ +#define portMPU_RLAR_ADDRESS_MASK ( 0xffffffe0 ) /* Must be 32-byte aligned. */ -#define portMPU_RBAR_ACCESS_PERMISSIONS_MASK ( 3UL << 1UL ) +#define portMPU_RBAR_ACCESS_PERMISSIONS_MASK ( 3UL << 1UL ) -#define portMPU_MAIR_ATTR0_POS ( 0UL ) -#define portMPU_MAIR_ATTR0_MASK ( 0x000000ff ) +#define portMPU_MAIR_ATTR0_POS ( 0UL ) +#define portMPU_MAIR_ATTR0_MASK ( 0x000000ff ) -#define portMPU_MAIR_ATTR1_POS ( 8UL ) -#define portMPU_MAIR_ATTR1_MASK ( 0x0000ff00 ) +#define portMPU_MAIR_ATTR1_POS ( 8UL ) +#define portMPU_MAIR_ATTR1_MASK ( 0x0000ff00 ) -#define portMPU_MAIR_ATTR2_POS ( 16UL ) -#define portMPU_MAIR_ATTR2_MASK ( 0x00ff0000 ) +#define portMPU_MAIR_ATTR2_POS ( 16UL ) +#define portMPU_MAIR_ATTR2_MASK ( 0x00ff0000 ) -#define portMPU_MAIR_ATTR3_POS ( 24UL ) -#define portMPU_MAIR_ATTR3_MASK ( 0xff000000 ) +#define portMPU_MAIR_ATTR3_POS ( 24UL ) +#define portMPU_MAIR_ATTR3_MASK ( 0xff000000 ) -#define portMPU_MAIR_ATTR4_POS ( 0UL ) -#define portMPU_MAIR_ATTR4_MASK ( 0x000000ff ) +#define portMPU_MAIR_ATTR4_POS ( 0UL ) +#define portMPU_MAIR_ATTR4_MASK ( 0x000000ff ) -#define portMPU_MAIR_ATTR5_POS ( 8UL ) -#define portMPU_MAIR_ATTR5_MASK ( 0x0000ff00 ) +#define portMPU_MAIR_ATTR5_POS ( 8UL ) +#define portMPU_MAIR_ATTR5_MASK ( 0x0000ff00 ) -#define portMPU_MAIR_ATTR6_POS ( 16UL ) -#define portMPU_MAIR_ATTR6_MASK ( 0x00ff0000 ) +#define portMPU_MAIR_ATTR6_POS ( 16UL ) +#define portMPU_MAIR_ATTR6_MASK ( 0x00ff0000 ) -#define portMPU_MAIR_ATTR7_POS ( 24UL ) -#define portMPU_MAIR_ATTR7_MASK ( 0xff000000 ) +#define portMPU_MAIR_ATTR7_POS ( 24UL ) +#define portMPU_MAIR_ATTR7_MASK ( 0xff000000 ) -#define portMPU_RLAR_ATTR_INDEX0 ( 0UL << 1UL ) -#define portMPU_RLAR_ATTR_INDEX1 ( 1UL << 1UL ) -#define portMPU_RLAR_ATTR_INDEX2 ( 2UL << 1UL ) -#define portMPU_RLAR_ATTR_INDEX3 ( 3UL << 1UL ) -#define portMPU_RLAR_ATTR_INDEX4 ( 4UL << 1UL ) -#define portMPU_RLAR_ATTR_INDEX5 ( 5UL << 1UL ) -#define portMPU_RLAR_ATTR_INDEX6 ( 6UL << 1UL ) -#define portMPU_RLAR_ATTR_INDEX7 ( 7UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX0 ( 0UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX1 ( 1UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX2 ( 2UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX3 ( 3UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX4 ( 4UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX5 ( 5UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX6 ( 6UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX7 ( 7UL << 1UL ) -#define portMPU_RLAR_REGION_ENABLE ( 1UL ) +#define portMPU_RLAR_REGION_ENABLE ( 1UL ) /* Enable privileged access to unmapped region. */ -#define portMPU_PRIV_BACKGROUND_ENABLE_BIT ( 1UL << 2UL ) +#define portMPU_PRIV_BACKGROUND_ENABLE_BIT ( 1UL << 2UL ) /* Enable MPU. */ -#define portMPU_ENABLE_BIT ( 1UL << 0UL ) +#define portMPU_ENABLE_BIT ( 1UL << 0UL ) /* Expected value of the portMPU_TYPE register. */ -#define portEXPECTED_MPU_TYPE_VALUE ( configTOTAL_MPU_REGIONS << 8UL ) +#define portEXPECTED_MPU_TYPE_VALUE ( configTOTAL_MPU_REGIONS << 8UL ) /* Extract first address of the MPU region as encoded in the * RBAR (Region Base Address Register) value. */ @@ -448,13 +472,13 @@ portDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIV #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) - /** - * @brief Sets up the task stack so that upon returning from - * SVC, the task stack is used again. - * - * @param pulSystemCallStack The current SP when the SVC was raised. - * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler. - */ +/** + * @brief Sets up the task stack so that upon returning from + * SVC, the task stack is used again. + * + * @param pulSystemCallStack The current SP when the SVC was raised. + * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler. + */ void vSystemCallExit( uint32_t * pulSystemCallStack, uint32_t ulLR ) PRIVILEGED_FUNCTION; @@ -462,11 +486,11 @@ portDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIV #if ( configENABLE_MPU == 1 ) - /** - * @brief Checks whether or not the calling task is privileged. - * - * @return pdTRUE if the calling task is privileged, pdFALSE otherwise. - */ +/** + * @brief Checks whether or not the calling task is privileged. + * + * @return pdTRUE if the calling task is privileged, pdFALSE otherwise. + */ BaseType_t xPortIsTaskPrivileged( void ) PRIVILEGED_FUNCTION; #endif /* configENABLE_MPU == 1 */ @@ -501,13 +525,13 @@ PRIVILEGED_DATA static volatile uint32_t ulCriticalNesting = 0xaaaaaaaaUL; * FreeRTOS API functions are not called from interrupts that have been assigned * a priority above configMAX_SYSCALL_INTERRUPT_PRIORITY. */ -#if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) ) +#if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) static uint8_t ucMaxSysCallPriority = 0; static uint32_t ulMaxPRIGROUPValue = 0; static const volatile uint8_t * const pcInterruptPriorityRegisters = ( const volatile uint8_t * ) portNVIC_IP_REGISTERS_OFFSET_16; -#endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) ) */ +#endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */ #if ( configUSE_TICKLESS_IDLE == 1 ) @@ -760,8 +784,15 @@ __attribute__( ( weak ) ) void vPortSetupTimerInterrupt( void ) /* PRIVILEGED_FU } #endif /* configUSE_TICKLESS_IDLE */ - /* Stop and reset the SysTick. */ - portNVIC_SYSTICK_CTRL_REG = 0UL; + /* Stop and reset SysTick. + * + * QEMU versions older than 7.0.0 contain a bug which causes an error if we + * enable SysTick without first selecting a valid clock source. We trigger + * the bug if we change clock sources from a clock with a zero clock period + * to one with a nonzero clock period and enable Systick at the same time. + * So we configure the CLKSOURCE bit here, prior to setting the ENABLE bit. + * This workaround avoids the bug in QEMU versions older than 7.0.0. */ + portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT_CONFIG; portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL; /* Configure SysTick to interrupt at the requested rate. */ @@ -819,6 +850,7 @@ static void prvTaskExitError( void ) static void prvSetupMPU( void ) /* PRIVILEGED_FUNCTION */ { #if defined( __ARMCC_VERSION ) + /* Declaration when these variable are defined in code instead of being * exported from linker scripts. */ extern uint32_t * __privileged_functions_start__; @@ -972,13 +1004,19 @@ void SysTick_Handler( void ) /* PRIVILEGED_FUNCTION */ uint32_t ulPreviousMask; ulPreviousMask = portSET_INTERRUPT_MASK_FROM_ISR(); + traceISR_ENTER(); { /* Increment the RTOS tick. */ if( xTaskIncrementTick() != pdFALSE ) { + traceISR_EXIT_TO_SCHEDULER(); /* Pend a context switch. */ portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; } + else + { + traceISR_EXIT(); + } } portCLEAR_INTERRUPT_MASK_FROM_ISR( ulPreviousMask ); } @@ -988,6 +1026,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO { #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) ) #if defined( __ARMCC_VERSION ) + /* Declaration when these variable are defined in code instead of being * exported from linker scripts. */ extern uint32_t * __syscalls_flash_start__; @@ -1083,18 +1122,24 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO vRestoreContextOfFirstTask(); break; - #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) ) - case portSVC_RAISE_PRIVILEGE: + #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) ) + case portSVC_RAISE_PRIVILEGE: - /* Only raise the privilege, if the svc was raised from any of - * the system calls. */ - if( ( ulPC >= ( uint32_t ) __syscalls_flash_start__ ) && - ( ulPC <= ( uint32_t ) __syscalls_flash_end__ ) ) - { - vRaisePrivilege(); - } - break; - #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) */ + /* Only raise the privilege, if the svc was raised from any of + * the system calls. */ + if( ( ulPC >= ( uint32_t ) __syscalls_flash_start__ ) && + ( ulPC <= ( uint32_t ) __syscalls_flash_end__ ) ) + { + vRaisePrivilege(); + } + break; + #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) */ + + #if ( configENABLE_MPU == 1 ) + case portSVC_YIELD: + vPortYield(); + break; + #endif /* configENABLE_MPU == 1 */ default: /* Incorrect SVC call. */ @@ -1154,12 +1199,11 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO { /* Extended frame i.e. FPU in use. */ ulStackFrameSize = 26; - __asm volatile - ( + __asm volatile ( " vpush {s0} \n" /* Trigger lazy stacking. */ " vpop {s0} \n" /* Nullify the affect of the above instruction. */ ::: "memory" - ); + ); } else { @@ -1171,7 +1215,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO { ulStackFrameSize = 8; } - #endif /* if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */ + #endif /* configENABLE_FPU || configENABLE_MVE */ /* Make space on the system call stack for the stack frame. */ pulSystemCallStack = pulSystemCallStack - ulStackFrameSize; @@ -1187,18 +1231,24 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO * point (i.e. the caller of the MPU_). We need to restore it * when we exit from the system call. */ pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry = pulTaskStack[ portOFFSET_TO_LR ]; - /* Store the value of the PSPLIM register before the SVC was raised. * We need to restore it when we exit from the system call. */ - __asm volatile ( "mrs %0, psplim" : "=r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) ); + #if ( portUSE_PSPLIM_REGISTER == 1 ) + { + __asm volatile ( "mrs %0, psplim" : "=r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) ); + } + #endif /* Use the pulSystemCallStack in thread mode. */ __asm volatile ( "msr psp, %0" : : "r" ( pulSystemCallStack ) ); - __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) ); + #if ( portUSE_PSPLIM_REGISTER == 1 ) + { + __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) ); + } + #endif /* Start executing the system call upon returning from this handler. */ pulSystemCallStack[ portOFFSET_TO_PC ] = uxSystemCallImplementations[ ucSystemCallNumber ]; - /* Raise a request to exit from the system call upon finishing the * system call. */ pulSystemCallStack[ portOFFSET_TO_LR ] = ( uint32_t ) vRequestSystemCallExit; @@ -1224,14 +1274,13 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO pulSystemCallStack[ portOFFSET_TO_PSR ] &= ( ~portPSR_STACK_PADDING_MASK ); /* Raise the privilege for the duration of the system call. */ - __asm volatile - ( + __asm volatile ( " mrs r0, control \n" /* Obtain current control value. */ " movs r1, #1 \n" /* r1 = 1. */ " bics r0, r1 \n" /* Clear nPRIV bit. */ " msr control, r0 \n" /* Write back new control value. */ ::: "r0", "r1", "memory" - ); + ); } } @@ -1293,12 +1342,11 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO { /* Extended frame i.e. FPU in use. */ ulStackFrameSize = 26; - __asm volatile - ( + __asm volatile ( " vpush {s0} \n" /* Trigger lazy stacking. */ " vpop {s0} \n" /* Nullify the affect of the above instruction. */ ::: "memory" - ); + ); } else { @@ -1310,7 +1358,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO { ulStackFrameSize = 8; } - #endif /* if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */ + #endif /* configENABLE_FPU || configENABLE_MVE */ /* Make space on the task stack for the stack frame. */ pulTaskStack = pulTaskStack - ulStackFrameSize; @@ -1332,7 +1380,11 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO /* Restore the PSPLIM register to what it was at the time of * system call entry. */ - __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) ); + #if ( portUSE_PSPLIM_REGISTER == 1 ) + { + __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) ); + } + #endif /* If the hardware used padding to force the stack pointer * to be double word aligned, set the stacked xPSR bit[9], @@ -1350,14 +1402,13 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO pxMpuSettings->xSystemCallStackInfo.pulTaskStack = NULL; /* Drop the privilege before returning to the thread mode. */ - __asm volatile - ( + __asm volatile ( " mrs r0, control \n" /* Obtain current control value. */ " movs r1, #1 \n" /* r1 = 1. */ " orrs r0, r1 \n" /* Set nPRIV bit. */ " msr control, r0 \n" /* Write back new control value. */ ::: "r0", "r1", "memory" - ); + ); } } @@ -1410,21 +1461,21 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO xMPUSettings->ulContext[ ulIndex ] = 0x11111111; /* r11. */ ulIndex++; - xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pvParameters; /* r0. */ + xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pvParameters; /* r0. */ ulIndex++; - xMPUSettings->ulContext[ ulIndex ] = 0x01010101; /* r1. */ + xMPUSettings->ulContext[ ulIndex ] = 0x01010101; /* r1. */ ulIndex++; - xMPUSettings->ulContext[ ulIndex ] = 0x02020202; /* r2. */ + xMPUSettings->ulContext[ ulIndex ] = 0x02020202; /* r2. */ ulIndex++; - xMPUSettings->ulContext[ ulIndex ] = 0x03030303; /* r3. */ + xMPUSettings->ulContext[ ulIndex ] = 0x03030303; /* r3. */ ulIndex++; - xMPUSettings->ulContext[ ulIndex ] = 0x12121212; /* r12. */ + xMPUSettings->ulContext[ ulIndex ] = 0x12121212; /* r12. */ ulIndex++; xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portTASK_RETURN_ADDRESS; /* LR. */ ulIndex++; - xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxCode; /* PC. */ + xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxCode; /* PC. */ ulIndex++; - xMPUSettings->ulContext[ ulIndex ] = portINITIAL_XPSR; /* xPSR. */ + xMPUSettings->ulContext[ ulIndex ] = portINITIAL_XPSR; /* xPSR. */ ulIndex++; #if ( configENABLE_TRUSTZONE == 1 ) @@ -1435,8 +1486,9 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO #endif /* configENABLE_TRUSTZONE */ xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) ( pxTopOfStack - 8 ); /* PSP with the hardware saved stack. */ ulIndex++; - xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxEndOfStack; /* PSPLIM. */ + xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxEndOfStack; /* PSPLIM. */ ulIndex++; + if( xRunPrivileged == pdTRUE ) { xMPUSettings->ulTaskFlags |= portTASK_IS_PRIVILEGED_FLAG; @@ -1449,6 +1501,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portINITIAL_CONTROL_UNPRIVILEGED; /* CONTROL. */ ulIndex++; } + xMPUSettings->ulContext[ ulIndex ] = portINITIAL_EXC_RETURN; /* LR (EXC_RETURN). */ ulIndex++; @@ -1483,7 +1536,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO * interrupt. */ #if ( portPRELOAD_REGISTERS == 0 ) { - pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */ + pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */ *pxTopOfStack = portINITIAL_XPSR; /* xPSR. */ pxTopOfStack--; *pxTopOfStack = ( StackType_t ) pxCode; /* PC. */ @@ -1505,7 +1558,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO } #else /* portPRELOAD_REGISTERS */ { - pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */ + pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */ *pxTopOfStack = portINITIAL_XPSR; /* xPSR. */ pxTopOfStack--; *pxTopOfStack = ( StackType_t ) pxCode; /* PC. */ @@ -1540,7 +1593,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO pxTopOfStack--; *pxTopOfStack = portINITIAL_EXC_RETURN; /* EXC_RETURN. */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */ + *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */ #if ( configENABLE_TRUSTZONE == 1 ) { @@ -1559,22 +1612,52 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */ { - #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) ) + /* An application can install FreeRTOS interrupt handlers in one of the + * folllowing ways: + * 1. Direct Routing - Install the functions SVC_Handler and PendSV_Handler + * for SVCall and PendSV interrupts respectively. + * 2. Indirect Routing - Install separate handlers for SVCall and PendSV + * interrupts and route program control from those handlers to + * SVC_Handler and PendSV_Handler functions. + * + * Applications that use Indirect Routing must set + * configCHECK_HANDLER_INSTALLATION to 0 in their FreeRTOSConfig.h. Direct + * routing, which is validated here when configCHECK_HANDLER_INSTALLATION + * is 1, should be preferred when possible. */ + #if ( configCHECK_HANDLER_INSTALLATION == 1 ) + { + const portISR_t * const pxVectorTable = portSCB_VTOR_REG; + + /* Validate that the application has correctly installed the FreeRTOS + * handlers for SVCall and PendSV interrupts. We do not check the + * installation of the SysTick handler because the application may + * choose to drive the RTOS tick using a timer other than the SysTick + * timer by overriding the weak function vPortSetupTimerInterrupt(). + * + * Assertion failures here indicate incorrect installation of the + * FreeRTOS handlers. For help installing the FreeRTOS handlers, see + * https://www.FreeRTOS.org/FAQHelp.html. + * + * Systems with a configurable address for the interrupt vector table + * can also encounter assertion failures or even system faults here if + * VTOR is not set correctly to point to the application's vector table. */ + configASSERT( pxVectorTable[ portVECTOR_INDEX_SVC ] == SVC_Handler ); + configASSERT( pxVectorTable[ portVECTOR_INDEX_PENDSV ] == PendSV_Handler ); + } + #endif /* configCHECK_HANDLER_INSTALLATION */ + + #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) { - volatile uint32_t ulOriginalPriority; volatile uint32_t ulImplementedPrioBits = 0; volatile uint8_t ucMaxPriorityValue; /* Determine the maximum priority from which ISR safe FreeRTOS API - * functions can be called. ISR safe functions are those that end in - * "FromISR". FreeRTOS maintains separate thread and ISR API functions to + * functions can be called. ISR safe functions are those that end in + * "FromISR". FreeRTOS maintains separate thread and ISR API functions to * ensure interrupt entry is as fast and simple as possible. * - * Save the interrupt priority value that is about to be clobbered. */ - ulOriginalPriority = portNVIC_SHPR2_REG; - - /* Determine the number of priority bits available. First write to all - * possible bits. */ + * First, determine the number of priority bits available. Write to all + * possible bits in the priority setting for SVCall. */ portNVIC_SHPR2_REG = 0xFF000000; /* Read the value back to see how many bits stuck. */ @@ -1593,11 +1676,10 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */ /* Check that the bits not implemented in hardware are zero in * configMAX_SYSCALL_INTERRUPT_PRIORITY. */ - configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( ~ucMaxPriorityValue ) ) == 0U ); + configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( uint8_t ) ( ~( uint32_t ) ucMaxPriorityValue ) ) == 0U ); /* Calculate the maximum acceptable priority group value for the number * of bits read back. */ - while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE ) { ulImplementedPrioBits++; @@ -1635,16 +1717,14 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */ * register. */ ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT; ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK; - - /* Restore the clobbered interrupt priority register to its original - * value. */ - portNVIC_SHPR2_REG = ulOriginalPriority; } - #endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) ) */ + #endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */ - /* Make PendSV, CallSV and SysTick the same priority as the kernel. */ + /* Make PendSV and SysTick the lowest priority interrupts, and make SVCall + * the highest priority. */ portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI; portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI; + portNVIC_SHPR2_REG = 0; #if ( configENABLE_MPU == 1 ) { @@ -1701,6 +1781,7 @@ void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */ int32_t lIndex = 0; #if defined( __ARMCC_VERSION ) + /* Declaration when these variable are defined in code instead of being * exported from linker scripts. */ extern uint32_t * __privileged_sram_start__; @@ -1886,7 +1967,7 @@ BaseType_t xPortIsInsideInterrupt( void ) } /*-----------------------------------------------------------*/ -#if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) ) +#if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) void vPortValidateInterruptPriority( void ) { @@ -1944,7 +2025,7 @@ BaseType_t xPortIsInsideInterrupt( void ) configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue ); } -#endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) ) */ +#endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */ /*-----------------------------------------------------------*/ #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) diff --git a/Source/portable/IAR/ARM_CM85/non_secure/portasm.h b/Source/portable/IAR/ARM_CM85/non_secure/portasm.h index f64ceb525..c6d2ebd58 100644 --- a/Source/portable/IAR/ARM_CM85/non_secure/portasm.h +++ b/Source/portable/IAR/ARM_CM85/non_secure/portasm.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/Source/portable/IAR/ARM_CM85/non_secure/portasm.s b/Source/portable/IAR/ARM_CM85/non_secure/portasm.s index 530910341..6a6b677bf 100644 --- a/Source/portable/IAR/ARM_CM85/non_secure/portasm.s +++ b/Source/portable/IAR/ARM_CM85/non_secure/portasm.s @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/Source/portable/IAR/ARM_CM85/non_secure/portmacro.h b/Source/portable/IAR/ARM_CM85/non_secure/portmacro.h index 4f7cf2bc0..024ce2b15 100644 --- a/Source/portable/IAR/ARM_CM85/non_secure/portmacro.h +++ b/Source/portable/IAR/ARM_CM85/non_secure/portmacro.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -53,16 +53,16 @@ /** * Architecture specifics. */ -#define portARCH_NAME "Cortex-M85" -#define portHAS_BASEPRI 1 -#define portDONT_DISCARD __root +#define portARCH_NAME "Cortex-M85" +#define portHAS_ARMV8M_MAIN_EXTENSION 1 +#define portDONT_DISCARD __root /*-----------------------------------------------------------*/ /* ARMv8-M common port configurations. */ #include "portmacrocommon.h" /*-----------------------------------------------------------*/ -#if( configTOTAL_MPU_REGIONS == 16 ) +#if ( configTOTAL_MPU_REGIONS == 16 ) #error 16 MPU regions are not yet supported for this port. #endif /*-----------------------------------------------------------*/ @@ -70,8 +70,8 @@ /** * @brief Critical section management. */ -#define portDISABLE_INTERRUPTS() ulSetInterruptMask() -#define portENABLE_INTERRUPTS() vClearInterruptMask( 0 ) +#define portDISABLE_INTERRUPTS() ulSetInterruptMask() +#define portENABLE_INTERRUPTS() vClearInterruptMask( 0 ) /*-----------------------------------------------------------*/ /* Suppress warnings that are generated by the IAR tools, but cannot be fixed in diff --git a/Source/portable/IAR/ARM_CM85/non_secure/portmacrocommon.h b/Source/portable/IAR/ARM_CM85/non_secure/portmacrocommon.h index 6f666da22..33f21d85b 100644 --- a/Source/portable/IAR/ARM_CM85/non_secure/portmacrocommon.h +++ b/Source/portable/IAR/ARM_CM85/non_secure/portmacrocommon.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -117,7 +117,7 @@ extern uint32_t ulSetInterruptMask( void ) /* __attribute__(( naked )) PRIVILEGE extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */; #if ( configENABLE_TRUSTZONE == 1 ) - extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize ); /* __attribute__ (( naked )) */ + extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize ); /* __attribute__ (( naked )) */ extern void vPortFreeSecureContext( uint32_t * pulTCB ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */; #endif /* configENABLE_TRUSTZONE */ @@ -188,13 +188,13 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P #if ( configENABLE_MPU == 1 ) - /** - * @brief Settings to define an MPU region. - */ +/** + * @brief Settings to define an MPU region. + */ typedef struct MPURegionSettings { - uint32_t ulRBAR; /**< RBAR for the region. */ - uint32_t ulRLAR; /**< RLAR for the region. */ + uint32_t ulRBAR; /**< RBAR for the region. */ + uint32_t ulRLAR; /**< RLAR for the region. */ } MPURegionSettings_t; #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) @@ -203,9 +203,9 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P #error configSYSTEM_CALL_STACK_SIZE must be defined to the desired size of the system call stack in words for using MPU wrappers v2. #endif - /** - * @brief System call stack. - */ +/** + * @brief System call stack. + */ typedef struct SYSTEM_CALL_STACK_INFO { uint32_t ulSystemCallStackBuffer[ configSYSTEM_CALL_STACK_SIZE ]; @@ -218,74 +218,74 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P #endif /* configUSE_MPU_WRAPPERS_V1 == 0 */ - /** - * @brief MPU settings as stored in the TCB. - */ +/** + * @brief MPU settings as stored in the TCB. + */ #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) - #if( configENABLE_TRUSTZONE == 1 ) + #if ( configENABLE_TRUSTZONE == 1 ) - /* - * +-----------+---------------+----------+-----------------+------------------------------+-----+ - * | s16-s31 | s0-s15, FPSCR | r4-r11 | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, | | - * | | | | PC, xPSR | CONTROL, EXC_RETURN | | - * +-----------+---------------+----------+-----------------+------------------------------+-----+ - * - * <-----------><--------------><---------><----------------><-----------------------------><----> - * 16 16 8 8 5 1 - */ - #define MAX_CONTEXT_SIZE 54 +/* + * +-----------+---------------+----------+-----------------+------------------------------+-----+ + * | s16-s31 | s0-s15, FPSCR | r4-r11 | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, | | + * | | | | PC, xPSR | CONTROL, EXC_RETURN | | + * +-----------+---------------+----------+-----------------+------------------------------+-----+ + * + * <-----------><--------------><---------><----------------><-----------------------------><----> + * 16 16 8 8 5 1 + */ + #define MAX_CONTEXT_SIZE 54 #else /* #if( configENABLE_TRUSTZONE == 1 ) */ - /* - * +-----------+---------------+----------+-----------------+----------------------+-----+ - * | s16-s31 | s0-s15, FPSCR | r4-r11 | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL | | - * | | | | PC, xPSR | EXC_RETURN | | - * +-----------+---------------+----------+-----------------+----------------------+-----+ - * - * <-----------><--------------><---------><----------------><---------------------><----> - * 16 16 8 8 4 1 - */ - #define MAX_CONTEXT_SIZE 53 +/* + * +-----------+---------------+----------+-----------------+----------------------+-----+ + * | s16-s31 | s0-s15, FPSCR | r4-r11 | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL | | + * | | | | PC, xPSR | EXC_RETURN | | + * +-----------+---------------+----------+-----------------+----------------------+-----+ + * + * <-----------><--------------><---------><----------------><---------------------><----> + * 16 16 8 8 4 1 + */ + #define MAX_CONTEXT_SIZE 53 #endif /* #if( configENABLE_TRUSTZONE == 1 ) */ #else /* #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */ - #if( configENABLE_TRUSTZONE == 1 ) + #if ( configENABLE_TRUSTZONE == 1 ) - /* - * +----------+-----------------+------------------------------+-----+ - * | r4-r11 | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, | | - * | | PC, xPSR | CONTROL, EXC_RETURN | | - * +----------+-----------------+------------------------------+-----+ - * - * <---------><----------------><------------------------------><----> - * 8 8 5 1 - */ - #define MAX_CONTEXT_SIZE 22 +/* + * +----------+-----------------+------------------------------+-----+ + * | r4-r11 | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, | | + * | | PC, xPSR | CONTROL, EXC_RETURN | | + * +----------+-----------------+------------------------------+-----+ + * + * <---------><----------------><------------------------------><----> + * 8 8 5 1 + */ + #define MAX_CONTEXT_SIZE 22 #else /* #if( configENABLE_TRUSTZONE == 1 ) */ - /* - * +----------+-----------------+----------------------+-----+ - * | r4-r11 | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL | | - * | | PC, xPSR | EXC_RETURN | | - * +----------+-----------------+----------------------+-----+ - * - * <---------><----------------><----------------------><----> - * 8 8 4 1 - */ - #define MAX_CONTEXT_SIZE 21 +/* + * +----------+-----------------+----------------------+-----+ + * | r4-r11 | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL | | + * | | PC, xPSR | EXC_RETURN | | + * +----------+-----------------+----------------------+-----+ + * + * <---------><----------------><----------------------><----> + * 8 8 4 1 + */ + #define MAX_CONTEXT_SIZE 21 #endif /* #if( configENABLE_TRUSTZONE == 1 ) */ #endif /* #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */ - /* Flags used for xMPU_SETTINGS.ulTaskFlags member. */ - #define portSTACK_FRAME_HAS_PADDING_FLAG ( 1UL << 0UL ) - #define portTASK_IS_PRIVILEGED_FLAG ( 1UL << 1UL ) +/* Flags used for xMPU_SETTINGS.ulTaskFlags member. */ + #define portSTACK_FRAME_HAS_PADDING_FLAG ( 1UL << 0UL ) + #define portTASK_IS_PRIVILEGED_FLAG ( 1UL << 1UL ) /* Size of an Access Control List (ACL) entry in bits. */ #define portACL_ENTRY_SIZE_BITS ( 32U ) @@ -313,7 +313,7 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P * system calls. */ #ifdef configASSERT - #if ( portHAS_BASEPRI == 1 ) + #if ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) void vPortValidateInterruptPriority( void ); #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() vPortValidateInterruptPriority() #endif @@ -333,12 +333,29 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P /** * @brief Scheduler utilities. */ -#define portYIELD() vPortYield() +#if ( configENABLE_MPU == 1 ) + #define portYIELD() __asm volatile ( "svc %0" ::"i" ( portSVC_YIELD ) : "memory" ) + #define portYIELD_WITHIN_API() vPortYield() +#else + #define portYIELD() vPortYield() + #define portYIELD_WITHIN_API() vPortYield() +#endif + #define portNVIC_INT_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed04 ) ) #define portNVIC_PENDSVSET_BIT ( 1UL << 28UL ) -#define portEND_SWITCHING_ISR( xSwitchRequired ) \ - do { if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; } \ - while( 0 ) +#define portEND_SWITCHING_ISR( xSwitchRequired ) \ + do \ + { \ + if( xSwitchRequired ) \ + { \ + traceISR_EXIT_TO_SCHEDULER(); \ + portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; \ + } \ + else \ + { \ + traceISR_EXIT(); \ + } \ + } while( 0 ) #define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x ) /*-----------------------------------------------------------*/ @@ -424,12 +441,12 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P extern BaseType_t xPortIsTaskPrivileged( void ); - /** - * @brief Checks whether or not the calling task is privileged. - * - * @return pdTRUE if the calling task is privileged, pdFALSE otherwise. - */ - #define portIS_TASK_PRIVILEGED() xPortIsTaskPrivileged() +/** + * @brief Checks whether or not the calling task is privileged. + * + * @return pdTRUE if the calling task is privileged, pdFALSE otherwise. + */ + #define portIS_TASK_PRIVILEGED() xPortIsTaskPrivileged() #endif /* configENABLE_MPU == 1 */ /*-----------------------------------------------------------*/ @@ -440,6 +457,56 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P #define portMEMORY_BARRIER() __asm volatile ( "" ::: "memory" ) /*-----------------------------------------------------------*/ +/* Select correct value of configUSE_PORT_OPTIMISED_TASK_SELECTION + * based on whether or not Mainline extension is implemented. */ +#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION + #if ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) + #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1 + #else + #define configUSE_PORT_OPTIMISED_TASK_SELECTION 0 + #endif +#endif /* #ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION */ + +/** + * @brief Port-optimised task selection. + */ +#if ( configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 ) + +/** + * @brief Count the number of leading zeros in a 32-bit value. + */ + static portFORCE_INLINE uint32_t ulPortCountLeadingZeros( uint32_t ulBitmap ) + { + uint32_t ulReturn; + + __asm volatile ( "clz %0, %1" : "=r" ( ulReturn ) : "r" ( ulBitmap ) : "memory" ); + + return ulReturn; + } + +/* Check the configuration. */ + #if ( configMAX_PRIORITIES > 32 ) + #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 different priorities as tasks that share a priority will time slice. + #endif + + #if ( portHAS_ARMV8M_MAIN_EXTENSION == 0 ) + #error ARMv8-M baseline implementations (such as Cortex-M23) do not support port-optimised task selection. Please set configUSE_PORT_OPTIMISED_TASK_SELECTION to 0 or leave it undefined. + #endif + +/** + * @brief Store/clear the ready priorities in a bit map. + */ + #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) ) + #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) ) + +/** + * @brief Get the priority of the highest-priority task that is ready to execute. + */ + #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - ulPortCountLeadingZeros( ( uxReadyPriorities ) ) ) + +#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */ +/*-----------------------------------------------------------*/ + /* *INDENT-OFF* */ #ifdef __cplusplus } diff --git a/Source/portable/IAR/ARM_CM85/secure/secure_context.c b/Source/portable/IAR/ARM_CM85/secure/secure_context.c index e37dd9672..83b3dbce1 100644 --- a/Source/portable/IAR/ARM_CM85/secure/secure_context.c +++ b/Source/portable/IAR/ARM_CM85/secure/secure_context.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -65,7 +65,7 @@ * @brief Maximum number of secure contexts. */ #ifndef secureconfigMAX_SECURE_CONTEXTS - #define secureconfigMAX_SECURE_CONTEXTS 8UL + #define secureconfigMAX_SECURE_CONTEXTS 8UL #endif /*-----------------------------------------------------------*/ @@ -164,15 +164,15 @@ secureportNON_SECURE_CALLABLE void SecureContext_Init( void ) } #if ( configENABLE_MPU == 1 ) - { - /* Configure thread mode to use PSP and to be unprivileged. */ - secureportSET_CONTROL( securecontextCONTROL_VALUE_UNPRIVILEGED ); - } + { + /* Configure thread mode to use PSP and to be unprivileged. */ + secureportSET_CONTROL( securecontextCONTROL_VALUE_UNPRIVILEGED ); + } #else /* configENABLE_MPU */ - { - /* Configure thread mode to use PSP and to be privileged. */ - secureportSET_CONTROL( securecontextCONTROL_VALUE_PRIVILEGED ); - } + { + /* Configure thread mode to use PSP and to be privileged. */ + secureportSET_CONTROL( securecontextCONTROL_VALUE_PRIVILEGED ); + } #endif /* configENABLE_MPU */ } } @@ -219,16 +219,16 @@ secureportNON_SECURE_CALLABLE void SecureContext_Init( void ) if( pucStackMemory != NULL ) { /* Since stack grows down, the starting point will be the last - * location. Note that this location is next to the last - * allocated byte for stack (excluding the space for seal values) - * because the hardware decrements the stack pointer before - * writing i.e. if stack pointer is 0x2, a push operation will - * decrement the stack pointer to 0x1 and then write at 0x1. */ + * location. Note that this location is next to the last + * allocated byte for stack (excluding the space for seal values) + * because the hardware decrements the stack pointer before + * writing i.e. if stack pointer is 0x2, a push operation will + * decrement the stack pointer to 0x1 and then write at 0x1. */ xSecureContexts[ ulSecureContextIndex ].pucStackStart = pucStackMemory + ulSecureStackSize; /* Seal the created secure process stack. */ - *( uint32_t * )( pucStackMemory + ulSecureStackSize ) = securecontextSTACK_SEAL_VALUE; - *( uint32_t * )( pucStackMemory + ulSecureStackSize + 4 ) = securecontextSTACK_SEAL_VALUE; + *( uint32_t * ) ( pucStackMemory + ulSecureStackSize ) = securecontextSTACK_SEAL_VALUE; + *( uint32_t * ) ( pucStackMemory + ulSecureStackSize + 4 ) = securecontextSTACK_SEAL_VALUE; /* The stack cannot go beyond this location. This value is * programmed in the PSPLIM register on context switch.*/ @@ -237,32 +237,32 @@ secureportNON_SECURE_CALLABLE void SecureContext_Init( void ) xSecureContexts[ ulSecureContextIndex ].pvTaskHandle = pvTaskHandle; #if ( configENABLE_MPU == 1 ) + { + /* Store the correct CONTROL value for the task on the stack. + * This value is programmed in the CONTROL register on + * context switch. */ + pulCurrentStackPointer = ( uint32_t * ) xSecureContexts[ ulSecureContextIndex ].pucStackStart; + pulCurrentStackPointer--; + + if( ulIsTaskPrivileged ) { - /* Store the correct CONTROL value for the task on the stack. - * This value is programmed in the CONTROL register on - * context switch. */ - pulCurrentStackPointer = ( uint32_t * ) xSecureContexts[ ulSecureContextIndex ].pucStackStart; - pulCurrentStackPointer--; - - if( ulIsTaskPrivileged ) - { - *( pulCurrentStackPointer ) = securecontextCONTROL_VALUE_PRIVILEGED; - } - else - { - *( pulCurrentStackPointer ) = securecontextCONTROL_VALUE_UNPRIVILEGED; - } - - /* Store the current stack pointer. This value is programmed in - * the PSP register on context switch. */ - xSecureContexts[ ulSecureContextIndex ].pucCurrentStackPointer = ( uint8_t * ) pulCurrentStackPointer; + *( pulCurrentStackPointer ) = securecontextCONTROL_VALUE_PRIVILEGED; } - #else /* configENABLE_MPU */ + else { - /* Current SP is set to the starting of the stack. This - * value programmed in the PSP register on context switch. */ - xSecureContexts[ ulSecureContextIndex ].pucCurrentStackPointer = xSecureContexts[ ulSecureContextIndex ].pucStackStart; + *( pulCurrentStackPointer ) = securecontextCONTROL_VALUE_UNPRIVILEGED; } + + /* Store the current stack pointer. This value is programmed in + * the PSP register on context switch. */ + xSecureContexts[ ulSecureContextIndex ].pucCurrentStackPointer = ( uint8_t * ) pulCurrentStackPointer; + } + #else /* configENABLE_MPU */ + { + /* Current SP is set to the starting of the stack. This + * value programmed in the PSP register on context switch. */ + xSecureContexts[ ulSecureContextIndex ].pucCurrentStackPointer = xSecureContexts[ ulSecureContextIndex ].pucStackStart; + } #endif /* configENABLE_MPU */ /* Ensure to never return 0 as a valid context handle. */ @@ -275,7 +275,8 @@ secureportNON_SECURE_CALLABLE void SecureContext_Init( void ) } /*-----------------------------------------------------------*/ -secureportNON_SECURE_CALLABLE void SecureContext_FreeContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle ) +secureportNON_SECURE_CALLABLE void SecureContext_FreeContext( SecureContextHandle_t xSecureContextHandle, + void * pvTaskHandle ) { uint32_t ulIPSR, ulSecureContextIndex; @@ -306,7 +307,8 @@ secureportNON_SECURE_CALLABLE void SecureContext_FreeContext( SecureContextHandl } /*-----------------------------------------------------------*/ -secureportNON_SECURE_CALLABLE void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle ) +secureportNON_SECURE_CALLABLE void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle, + void * pvTaskHandle ) { uint8_t * pucStackLimit; uint32_t ulSecureContextIndex; @@ -328,7 +330,8 @@ secureportNON_SECURE_CALLABLE void SecureContext_LoadContext( SecureContextHandl } /*-----------------------------------------------------------*/ -secureportNON_SECURE_CALLABLE void SecureContext_SaveContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle ) +secureportNON_SECURE_CALLABLE void SecureContext_SaveContext( SecureContextHandle_t xSecureContextHandle, + void * pvTaskHandle ) { uint8_t * pucStackLimit; uint32_t ulSecureContextIndex; diff --git a/Source/portable/IAR/ARM_CM85/secure/secure_context.h b/Source/portable/IAR/ARM_CM85/secure/secure_context.h index 2220ea646..40fdc276d 100644 --- a/Source/portable/IAR/ARM_CM85/secure/secure_context.h +++ b/Source/portable/IAR/ARM_CM85/secure/secure_context.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -38,12 +38,12 @@ /** * @brief PSP value when no secure context is loaded. */ -#define securecontextNO_STACK 0x0 +#define securecontextNO_STACK 0x0 /** * @brief Invalid context ID. */ -#define securecontextINVALID_CONTEXT_ID 0UL +#define securecontextINVALID_CONTEXT_ID 0UL /*-----------------------------------------------------------*/ /** @@ -108,7 +108,8 @@ void SecureContext_Init( void ); * @param[in] xSecureContextHandle Context handle corresponding to the * context to be freed. */ -void SecureContext_FreeContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle ); +void SecureContext_FreeContext( SecureContextHandle_t xSecureContextHandle, + void * pvTaskHandle ); /** * @brief Loads the given context. @@ -119,7 +120,8 @@ void SecureContext_FreeContext( SecureContextHandle_t xSecureContextHandle, void * @param[in] xSecureContextHandle Context handle corresponding to the context * to be loaded. */ -void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle ); +void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle, + void * pvTaskHandle ); /** * @brief Saves the given context. @@ -130,6 +132,7 @@ void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle, void * @param[in] xSecureContextHandle Context handle corresponding to the context * to be saved. */ -void SecureContext_SaveContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle ); +void SecureContext_SaveContext( SecureContextHandle_t xSecureContextHandle, + void * pvTaskHandle ); #endif /* __SECURE_CONTEXT_H__ */ diff --git a/Source/portable/IAR/ARM_CM85/secure/secure_context_port_asm.s b/Source/portable/IAR/ARM_CM85/secure/secure_context_port_asm.s index 0da3e0f12..5124d9246 100644 --- a/Source/portable/IAR/ARM_CM85/secure/secure_context_port_asm.s +++ b/Source/portable/IAR/ARM_CM85/secure/secure_context_port_asm.s @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/Source/portable/IAR/ARM_CM85/secure/secure_heap.c b/Source/portable/IAR/ARM_CM85/secure/secure_heap.c index 19f7c2354..d9789404b 100644 --- a/Source/portable/IAR/ARM_CM85/secure/secure_heap.c +++ b/Source/portable/IAR/ARM_CM85/secure/secure_heap.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -62,6 +62,22 @@ /* Assumes 8bit bytes! */ #define secureheapBITS_PER_BYTE ( ( size_t ) 8 ) + +/* Max value that fits in a size_t type. */ +#define secureheapSIZE_MAX ( ~( ( size_t ) 0 ) ) + +/* Check if adding a and b will result in overflow. */ +#define secureheapADD_WILL_OVERFLOW( a, b ) ( ( a ) > ( secureheapSIZE_MAX - ( b ) ) ) + +/* MSB of the xBlockSize member of an BlockLink_t structure is used to track + * the allocation status of a block. When MSB of the xBlockSize member of + * an BlockLink_t structure is set then the block belongs to the application. + * When the bit is free the block is still part of the free heap space. */ +#define secureheapBLOCK_ALLOCATED_BITMASK ( ( ( size_t ) 1 ) << ( ( sizeof( size_t ) * secureheapBITS_PER_BYTE ) - 1 ) ) +#define secureheapBLOCK_SIZE_IS_VALID( xBlockSize ) ( ( ( xBlockSize ) & secureheapBLOCK_ALLOCATED_BITMASK ) == 0 ) +#define secureheapBLOCK_IS_ALLOCATED( pxBlock ) ( ( ( pxBlock->xBlockSize ) & secureheapBLOCK_ALLOCATED_BITMASK ) != 0 ) +#define secureheapALLOCATE_BLOCK( pxBlock ) ( ( pxBlock->xBlockSize ) |= secureheapBLOCK_ALLOCATED_BITMASK ) +#define secureheapFREE_BLOCK( pxBlock ) ( ( pxBlock->xBlockSize ) &= ~secureheapBLOCK_ALLOCATED_BITMASK ) /*-----------------------------------------------------------*/ /* Allocate the memory for the heap. */ @@ -123,14 +139,6 @@ static BlockLink_t * pxEnd = NULL; static size_t xFreeBytesRemaining = 0U; static size_t xMinimumEverFreeBytesRemaining = 0U; -/** - * @brief Gets set to the top bit of an size_t type. - * - * When this bit in the xBlockSize member of an BlockLink_t structure is set - * then the block belongs to the application. When the bit is free the block is - * still part of the free heap space. - */ -static size_t xBlockAllocatedBit = 0; /*-----------------------------------------------------------*/ static void prvHeapInit( void ) @@ -175,9 +183,6 @@ static void prvHeapInit( void ) /* Only one block exists - and it covers the entire usable heap space. */ xMinimumEverFreeBytesRemaining = pxFirstFreeBlock->xBlockSize; xFreeBytesRemaining = pxFirstFreeBlock->xBlockSize; - - /* Work out the position of the top bit in a size_t variable. */ - xBlockAllocatedBit = ( ( size_t ) 1 ) << ( ( sizeof( size_t ) * secureheapBITS_PER_BYTE ) - 1 ); } /*-----------------------------------------------------------*/ @@ -250,6 +255,7 @@ void * pvPortMalloc( size_t xWantedSize ) BlockLink_t * pxPreviousBlock; BlockLink_t * pxNewBlockLink; void * pvReturn = NULL; + size_t xAdditionalRequiredSize; /* If this is the first call to malloc then the heap will require * initialisation to setup the list of free blocks. */ @@ -262,25 +268,29 @@ void * pvPortMalloc( size_t xWantedSize ) mtCOVERAGE_TEST_MARKER(); } - /* Check the requested block size is not so large that the top bit is set. - * The top bit of the block size member of the BlockLink_t structure is used - * to determine who owns the block - the application or the kernel, so it - * must be free. */ - if( ( xWantedSize & xBlockAllocatedBit ) == 0 ) + if( xWantedSize > 0 ) { - /* The wanted size is increased so it can contain a BlockLink_t + /* The wanted size must be increased so it can contain a BlockLink_t * structure in addition to the requested amount of bytes. */ - if( xWantedSize > 0 ) + if( secureheapADD_WILL_OVERFLOW( xWantedSize, xHeapStructSize ) == 0 ) { xWantedSize += xHeapStructSize; - /* Ensure that blocks are always aligned to the required number of - * bytes. */ + /* Ensure that blocks are always aligned to the required number + * of bytes. */ if( ( xWantedSize & secureportBYTE_ALIGNMENT_MASK ) != 0x00 ) { /* Byte alignment required. */ - xWantedSize += ( secureportBYTE_ALIGNMENT - ( xWantedSize & secureportBYTE_ALIGNMENT_MASK ) ); - secureportASSERT( ( xWantedSize & secureportBYTE_ALIGNMENT_MASK ) == 0 ); + xAdditionalRequiredSize = secureportBYTE_ALIGNMENT - ( xWantedSize & secureportBYTE_ALIGNMENT_MASK ); + + if( secureheapADD_WILL_OVERFLOW( xWantedSize, xAdditionalRequiredSize ) == 0 ) + { + xWantedSize += xAdditionalRequiredSize; + } + else + { + xWantedSize = 0; + } } else { @@ -289,9 +299,20 @@ void * pvPortMalloc( size_t xWantedSize ) } else { - mtCOVERAGE_TEST_MARKER(); + xWantedSize = 0; } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + /* Check the requested block size is not so large that the top bit is set. + * The top bit of the block size member of the BlockLink_t structure is used + * to determine who owns the block - the application or the kernel, so it + * must be free. */ + if( secureheapBLOCK_SIZE_IS_VALID( xWantedSize ) != 0 ) + { if( ( xWantedSize > 0 ) && ( xWantedSize <= xFreeBytesRemaining ) ) { /* Traverse the list from the start (lowest address) block until @@ -334,7 +355,8 @@ void * pvPortMalloc( size_t xWantedSize ) pxBlock->xBlockSize = xWantedSize; /* Insert the new block into the list of free blocks. */ - prvInsertBlockIntoFreeList( pxNewBlockLink ); + pxNewBlockLink->pxNextFreeBlock = pxPreviousBlock->pxNextFreeBlock; + pxPreviousBlock->pxNextFreeBlock = pxNewBlockLink; } else { @@ -354,7 +376,7 @@ void * pvPortMalloc( size_t xWantedSize ) /* The block is being returned - it is allocated and owned by * the application and has no "next" block. */ - pxBlock->xBlockSize |= xBlockAllocatedBit; + secureheapALLOCATE_BLOCK( pxBlock ); pxBlock->pxNextFreeBlock = NULL; } else @@ -375,17 +397,17 @@ void * pvPortMalloc( size_t xWantedSize ) traceMALLOC( pvReturn, xWantedSize ); #if ( secureconfigUSE_MALLOC_FAILED_HOOK == 1 ) + { + if( pvReturn == NULL ) { - if( pvReturn == NULL ) - { - extern void vApplicationMallocFailedHook( void ); - vApplicationMallocFailedHook(); - } - else - { - mtCOVERAGE_TEST_MARKER(); - } + extern void vApplicationMallocFailedHook( void ); + vApplicationMallocFailedHook(); } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } #endif /* if ( secureconfigUSE_MALLOC_FAILED_HOOK == 1 ) */ secureportASSERT( ( ( ( size_t ) pvReturn ) & ( size_t ) secureportBYTE_ALIGNMENT_MASK ) == 0 ); @@ -408,16 +430,16 @@ void vPortFree( void * pv ) pxLink = ( void * ) puc; /* Check the block is actually allocated. */ - secureportASSERT( ( pxLink->xBlockSize & xBlockAllocatedBit ) != 0 ); + secureportASSERT( secureheapBLOCK_IS_ALLOCATED( pxLink ) != 0 ); secureportASSERT( pxLink->pxNextFreeBlock == NULL ); - if( ( pxLink->xBlockSize & xBlockAllocatedBit ) != 0 ) + if( secureheapBLOCK_IS_ALLOCATED( pxLink ) != 0 ) { if( pxLink->pxNextFreeBlock == NULL ) { /* The block is being returned to the heap - it is no longer * allocated. */ - pxLink->xBlockSize &= ~xBlockAllocatedBit; + secureheapFREE_BLOCK( pxLink ); secureportDISABLE_NON_SECURE_INTERRUPTS(); { diff --git a/Source/portable/IAR/ARM_CM85/secure/secure_heap.h b/Source/portable/IAR/ARM_CM85/secure/secure_heap.h index 75c9cb00b..cf5551046 100644 --- a/Source/portable/IAR/ARM_CM85/secure/secure_heap.h +++ b/Source/portable/IAR/ARM_CM85/secure/secure_heap.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/Source/portable/IAR/ARM_CM85/secure/secure_init.c b/Source/portable/IAR/ARM_CM85/secure/secure_init.c index f93bfce95..66d35eccc 100644 --- a/Source/portable/IAR/ARM_CM85/secure/secure_init.c +++ b/Source/portable/IAR/ARM_CM85/secure/secure_init.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -93,7 +93,7 @@ secureportNON_SECURE_CALLABLE void SecureInit_EnableNSFPUAccess( void ) * permitted. CP11 should be programmed to the same value as CP10. */ *( secureinitNSACR ) |= ( secureinitNSACR_CP10_MASK | secureinitNSACR_CP11_MASK ); - /* LSPENS = 0 ==> LSPEN is writable fron non-secure state. This ensures + /* LSPENS = 0 ==> LSPEN is writable from non-secure state. This ensures * that we can enable/disable lazy stacking in port.c file. */ *( secureinitFPCCR ) &= ~( secureinitFPCCR_LSPENS_MASK ); diff --git a/Source/portable/IAR/ARM_CM85/secure/secure_init.h b/Source/portable/IAR/ARM_CM85/secure/secure_init.h index e6c9da0b4..6404c5cc4 100644 --- a/Source/portable/IAR/ARM_CM85/secure/secure_init.h +++ b/Source/portable/IAR/ARM_CM85/secure/secure_init.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/Source/portable/IAR/ARM_CM85/secure/secure_port_macros.h b/Source/portable/IAR/ARM_CM85/secure/secure_port_macros.h index d7ac5833c..085108cc1 100644 --- a/Source/portable/IAR/ARM_CM85/secure/secure_port_macros.h +++ b/Source/portable/IAR/ARM_CM85/secure/secure_port_macros.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/Source/portable/IAR/ARM_CM85_NTZ/non_secure/mpu_wrappers_v2_asm.S b/Source/portable/IAR/ARM_CM85_NTZ/non_secure/mpu_wrappers_v2_asm.S index ef180bd91..b4f1fbc3b 100644 --- a/Source/portable/IAR/ARM_CM85_NTZ/non_secure/mpu_wrappers_v2_asm.S +++ b/Source/portable/IAR/ARM_CM85_NTZ/non_secure/mpu_wrappers_v2_asm.S @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -196,20 +196,6 @@ MPU_uxTaskGetNumberOfTasks: svc #SYSTEM_CALL_uxTaskGetNumberOfTasks /*-----------------------------------------------------------*/ - PUBLIC MPU_pcTaskGetName -MPU_pcTaskGetName: - push {r0} - mrs r0, control - tst r0, #1 - bne MPU_pcTaskGetName_Unpriv - MPU_pcTaskGetName_Priv: - pop {r0} - b MPU_pcTaskGetNameImpl - MPU_pcTaskGetName_Unpriv: - pop {r0} - svc #SYSTEM_CALL_pcTaskGetName -/*-----------------------------------------------------------*/ - PUBLIC MPU_ulTaskGetRunTimeCounter MPU_ulTaskGetRunTimeCounter: push {r0} @@ -742,24 +728,18 @@ MPU_xTimerGetTimerDaemonTaskHandle: svc #SYSTEM_CALL_xTimerGetTimerDaemonTaskHandle /*-----------------------------------------------------------*/ - PUBLIC MPU_xTimerGenericCommandEntry -MPU_xTimerGenericCommandEntry: + PUBLIC MPU_xTimerGenericCommandFromTaskEntry +MPU_xTimerGenericCommandFromTaskEntry: push {r0} - /* This function can be called from ISR also and therefore, we need a check - * to take privileged path, if called from ISR. */ - mrs r0, ipsr - cmp r0, #0 - bne MPU_xTimerGenericCommand_Priv mrs r0, control tst r0, #1 - beq MPU_xTimerGenericCommand_Priv - MPU_xTimerGenericCommand_Unpriv: + bne MPU_xTimerGenericCommandFromTask_Unpriv + MPU_xTimerGenericCommandFromTask_Priv: pop {r0} - svc #SYSTEM_CALL_xTimerGenericCommand - MPU_xTimerGenericCommand_Priv: + b MPU_xTimerGenericCommandFromTaskImpl + MPU_xTimerGenericCommandFromTask_Unpriv: pop {r0} - b MPU_xTimerGenericCommandPrivImpl - + svc #SYSTEM_CALL_xTimerGenericCommandFromTask /*-----------------------------------------------------------*/ PUBLIC MPU_pcTimerGetName @@ -1089,10 +1069,6 @@ MPU_xTaskGetTickCountImpl: MPU_uxTaskGetNumberOfTasksImpl: b MPU_uxTaskGetNumberOfTasksImpl - PUBWEAK MPU_pcTaskGetNameImpl -MPU_pcTaskGetNameImpl: - b MPU_pcTaskGetNameImpl - PUBWEAK MPU_ulTaskGetRunTimeCounterImpl MPU_ulTaskGetRunTimeCounterImpl: b MPU_ulTaskGetRunTimeCounterImpl @@ -1245,9 +1221,9 @@ MPU_xTimerIsTimerActiveImpl: MPU_xTimerGetTimerDaemonTaskHandleImpl: b MPU_xTimerGetTimerDaemonTaskHandleImpl - PUBWEAK MPU_xTimerGenericCommandPrivImpl -MPU_xTimerGenericCommandPrivImpl: - b MPU_xTimerGenericCommandPrivImpl + PUBWEAK MPU_xTimerGenericCommandFromTaskImpl +MPU_xTimerGenericCommandFromTaskImpl: + b MPU_xTimerGenericCommandFromTaskImpl PUBWEAK MPU_pcTimerGetNameImpl MPU_pcTimerGetNameImpl: diff --git a/Source/portable/IAR/ARM_CM85_NTZ/non_secure/port.c b/Source/portable/IAR/ARM_CM85_NTZ/non_secure/port.c index 9712ac353..230fe5fc2 100644 --- a/Source/portable/IAR/ARM_CM85_NTZ/non_secure/port.c +++ b/Source/portable/IAR/ARM_CM85_NTZ/non_secure/port.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -68,6 +68,22 @@ #if ( ( configRUN_FREERTOS_SECURE_ONLY == 1 ) && ( configENABLE_TRUSTZONE == 1 ) ) #error TrustZone needs to be disabled in order to run FreeRTOS on the Secure Side. #endif + +/** + * Cortex-M23 does not have non-secure PSPLIM. We should use PSPLIM on Cortex-M23 + * only when FreeRTOS runs on secure side. + */ +#if ( ( portHAS_ARMV8M_MAIN_EXTENSION == 0 ) && ( configRUN_FREERTOS_SECURE_ONLY == 0 ) ) + #define portUSE_PSPLIM_REGISTER 0 +#else + #define portUSE_PSPLIM_REGISTER 1 +#endif +/*-----------------------------------------------------------*/ + +/** + * @brief Prototype of all Interrupt Service Routines (ISRs). + */ +typedef void ( * portISR_t )( void ); /*-----------------------------------------------------------*/ /** @@ -91,10 +107,18 @@ /** * @brief Constants required to manipulate the SCB. */ -#define portSCB_SYS_HANDLER_CTRL_STATE_REG ( *( volatile uint32_t * ) 0xe000ed24 ) +#define portSCB_VTOR_REG ( *( ( portISR_t ** ) 0xe000ed08 ) ) +#define portSCB_SYS_HANDLER_CTRL_STATE_REG ( *( ( volatile uint32_t * ) 0xe000ed24 ) ) #define portSCB_MEM_FAULT_ENABLE_BIT ( 1UL << 16UL ) /*-----------------------------------------------------------*/ +/** + * @brief Constants used to check the installation of the FreeRTOS interrupt handlers. + */ +#define portVECTOR_INDEX_SVC ( 11 ) +#define portVECTOR_INDEX_PENDSV ( 14 ) +/*-----------------------------------------------------------*/ + /** * @brief Constants required to check the validity of an interrupt priority. */ @@ -111,8 +135,8 @@ /** * @brief Constants used during system call enter and exit. */ -#define portPSR_STACK_PADDING_MASK ( 1UL << 9UL ) -#define portEXC_RETURN_STACK_FRAME_TYPE_MASK ( 1UL << 4UL ) +#define portPSR_STACK_PADDING_MASK ( 1UL << 9UL ) +#define portEXC_RETURN_STACK_FRAME_TYPE_MASK ( 1UL << 4UL ) /*-----------------------------------------------------------*/ /** @@ -134,81 +158,81 @@ /** * @brief Offsets in the stack to the parameters when inside the SVC handler. */ -#define portOFFSET_TO_LR ( 5 ) -#define portOFFSET_TO_PC ( 6 ) -#define portOFFSET_TO_PSR ( 7 ) +#define portOFFSET_TO_LR ( 5 ) +#define portOFFSET_TO_PC ( 6 ) +#define portOFFSET_TO_PSR ( 7 ) /*-----------------------------------------------------------*/ /** * @brief Constants required to manipulate the MPU. */ -#define portMPU_TYPE_REG ( *( ( volatile uint32_t * ) 0xe000ed90 ) ) -#define portMPU_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed94 ) ) -#define portMPU_RNR_REG ( *( ( volatile uint32_t * ) 0xe000ed98 ) ) +#define portMPU_TYPE_REG ( *( ( volatile uint32_t * ) 0xe000ed90 ) ) +#define portMPU_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed94 ) ) +#define portMPU_RNR_REG ( *( ( volatile uint32_t * ) 0xe000ed98 ) ) -#define portMPU_RBAR_REG ( *( ( volatile uint32_t * ) 0xe000ed9c ) ) -#define portMPU_RLAR_REG ( *( ( volatile uint32_t * ) 0xe000eda0 ) ) +#define portMPU_RBAR_REG ( *( ( volatile uint32_t * ) 0xe000ed9c ) ) +#define portMPU_RLAR_REG ( *( ( volatile uint32_t * ) 0xe000eda0 ) ) -#define portMPU_RBAR_A1_REG ( *( ( volatile uint32_t * ) 0xe000eda4 ) ) -#define portMPU_RLAR_A1_REG ( *( ( volatile uint32_t * ) 0xe000eda8 ) ) +#define portMPU_RBAR_A1_REG ( *( ( volatile uint32_t * ) 0xe000eda4 ) ) +#define portMPU_RLAR_A1_REG ( *( ( volatile uint32_t * ) 0xe000eda8 ) ) -#define portMPU_RBAR_A2_REG ( *( ( volatile uint32_t * ) 0xe000edac ) ) -#define portMPU_RLAR_A2_REG ( *( ( volatile uint32_t * ) 0xe000edb0 ) ) +#define portMPU_RBAR_A2_REG ( *( ( volatile uint32_t * ) 0xe000edac ) ) +#define portMPU_RLAR_A2_REG ( *( ( volatile uint32_t * ) 0xe000edb0 ) ) -#define portMPU_RBAR_A3_REG ( *( ( volatile uint32_t * ) 0xe000edb4 ) ) -#define portMPU_RLAR_A3_REG ( *( ( volatile uint32_t * ) 0xe000edb8 ) ) +#define portMPU_RBAR_A3_REG ( *( ( volatile uint32_t * ) 0xe000edb4 ) ) +#define portMPU_RLAR_A3_REG ( *( ( volatile uint32_t * ) 0xe000edb8 ) ) -#define portMPU_MAIR0_REG ( *( ( volatile uint32_t * ) 0xe000edc0 ) ) -#define portMPU_MAIR1_REG ( *( ( volatile uint32_t * ) 0xe000edc4 ) ) +#define portMPU_MAIR0_REG ( *( ( volatile uint32_t * ) 0xe000edc0 ) ) +#define portMPU_MAIR1_REG ( *( ( volatile uint32_t * ) 0xe000edc4 ) ) -#define portMPU_RBAR_ADDRESS_MASK ( 0xffffffe0 ) /* Must be 32-byte aligned. */ -#define portMPU_RLAR_ADDRESS_MASK ( 0xffffffe0 ) /* Must be 32-byte aligned. */ +#define portMPU_RBAR_ADDRESS_MASK ( 0xffffffe0 ) /* Must be 32-byte aligned. */ +#define portMPU_RLAR_ADDRESS_MASK ( 0xffffffe0 ) /* Must be 32-byte aligned. */ -#define portMPU_RBAR_ACCESS_PERMISSIONS_MASK ( 3UL << 1UL ) +#define portMPU_RBAR_ACCESS_PERMISSIONS_MASK ( 3UL << 1UL ) -#define portMPU_MAIR_ATTR0_POS ( 0UL ) -#define portMPU_MAIR_ATTR0_MASK ( 0x000000ff ) +#define portMPU_MAIR_ATTR0_POS ( 0UL ) +#define portMPU_MAIR_ATTR0_MASK ( 0x000000ff ) -#define portMPU_MAIR_ATTR1_POS ( 8UL ) -#define portMPU_MAIR_ATTR1_MASK ( 0x0000ff00 ) +#define portMPU_MAIR_ATTR1_POS ( 8UL ) +#define portMPU_MAIR_ATTR1_MASK ( 0x0000ff00 ) -#define portMPU_MAIR_ATTR2_POS ( 16UL ) -#define portMPU_MAIR_ATTR2_MASK ( 0x00ff0000 ) +#define portMPU_MAIR_ATTR2_POS ( 16UL ) +#define portMPU_MAIR_ATTR2_MASK ( 0x00ff0000 ) -#define portMPU_MAIR_ATTR3_POS ( 24UL ) -#define portMPU_MAIR_ATTR3_MASK ( 0xff000000 ) +#define portMPU_MAIR_ATTR3_POS ( 24UL ) +#define portMPU_MAIR_ATTR3_MASK ( 0xff000000 ) -#define portMPU_MAIR_ATTR4_POS ( 0UL ) -#define portMPU_MAIR_ATTR4_MASK ( 0x000000ff ) +#define portMPU_MAIR_ATTR4_POS ( 0UL ) +#define portMPU_MAIR_ATTR4_MASK ( 0x000000ff ) -#define portMPU_MAIR_ATTR5_POS ( 8UL ) -#define portMPU_MAIR_ATTR5_MASK ( 0x0000ff00 ) +#define portMPU_MAIR_ATTR5_POS ( 8UL ) +#define portMPU_MAIR_ATTR5_MASK ( 0x0000ff00 ) -#define portMPU_MAIR_ATTR6_POS ( 16UL ) -#define portMPU_MAIR_ATTR6_MASK ( 0x00ff0000 ) +#define portMPU_MAIR_ATTR6_POS ( 16UL ) +#define portMPU_MAIR_ATTR6_MASK ( 0x00ff0000 ) -#define portMPU_MAIR_ATTR7_POS ( 24UL ) -#define portMPU_MAIR_ATTR7_MASK ( 0xff000000 ) +#define portMPU_MAIR_ATTR7_POS ( 24UL ) +#define portMPU_MAIR_ATTR7_MASK ( 0xff000000 ) -#define portMPU_RLAR_ATTR_INDEX0 ( 0UL << 1UL ) -#define portMPU_RLAR_ATTR_INDEX1 ( 1UL << 1UL ) -#define portMPU_RLAR_ATTR_INDEX2 ( 2UL << 1UL ) -#define portMPU_RLAR_ATTR_INDEX3 ( 3UL << 1UL ) -#define portMPU_RLAR_ATTR_INDEX4 ( 4UL << 1UL ) -#define portMPU_RLAR_ATTR_INDEX5 ( 5UL << 1UL ) -#define portMPU_RLAR_ATTR_INDEX6 ( 6UL << 1UL ) -#define portMPU_RLAR_ATTR_INDEX7 ( 7UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX0 ( 0UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX1 ( 1UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX2 ( 2UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX3 ( 3UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX4 ( 4UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX5 ( 5UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX6 ( 6UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX7 ( 7UL << 1UL ) -#define portMPU_RLAR_REGION_ENABLE ( 1UL ) +#define portMPU_RLAR_REGION_ENABLE ( 1UL ) /* Enable privileged access to unmapped region. */ -#define portMPU_PRIV_BACKGROUND_ENABLE_BIT ( 1UL << 2UL ) +#define portMPU_PRIV_BACKGROUND_ENABLE_BIT ( 1UL << 2UL ) /* Enable MPU. */ -#define portMPU_ENABLE_BIT ( 1UL << 0UL ) +#define portMPU_ENABLE_BIT ( 1UL << 0UL ) /* Expected value of the portMPU_TYPE register. */ -#define portEXPECTED_MPU_TYPE_VALUE ( configTOTAL_MPU_REGIONS << 8UL ) +#define portEXPECTED_MPU_TYPE_VALUE ( configTOTAL_MPU_REGIONS << 8UL ) /* Extract first address of the MPU region as encoded in the * RBAR (Region Base Address Register) value. */ @@ -448,13 +472,13 @@ portDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIV #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) - /** - * @brief Sets up the task stack so that upon returning from - * SVC, the task stack is used again. - * - * @param pulSystemCallStack The current SP when the SVC was raised. - * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler. - */ +/** + * @brief Sets up the task stack so that upon returning from + * SVC, the task stack is used again. + * + * @param pulSystemCallStack The current SP when the SVC was raised. + * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler. + */ void vSystemCallExit( uint32_t * pulSystemCallStack, uint32_t ulLR ) PRIVILEGED_FUNCTION; @@ -462,11 +486,11 @@ portDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIV #if ( configENABLE_MPU == 1 ) - /** - * @brief Checks whether or not the calling task is privileged. - * - * @return pdTRUE if the calling task is privileged, pdFALSE otherwise. - */ +/** + * @brief Checks whether or not the calling task is privileged. + * + * @return pdTRUE if the calling task is privileged, pdFALSE otherwise. + */ BaseType_t xPortIsTaskPrivileged( void ) PRIVILEGED_FUNCTION; #endif /* configENABLE_MPU == 1 */ @@ -501,13 +525,13 @@ PRIVILEGED_DATA static volatile uint32_t ulCriticalNesting = 0xaaaaaaaaUL; * FreeRTOS API functions are not called from interrupts that have been assigned * a priority above configMAX_SYSCALL_INTERRUPT_PRIORITY. */ -#if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) ) +#if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) static uint8_t ucMaxSysCallPriority = 0; static uint32_t ulMaxPRIGROUPValue = 0; static const volatile uint8_t * const pcInterruptPriorityRegisters = ( const volatile uint8_t * ) portNVIC_IP_REGISTERS_OFFSET_16; -#endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) ) */ +#endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */ #if ( configUSE_TICKLESS_IDLE == 1 ) @@ -760,8 +784,15 @@ __attribute__( ( weak ) ) void vPortSetupTimerInterrupt( void ) /* PRIVILEGED_FU } #endif /* configUSE_TICKLESS_IDLE */ - /* Stop and reset the SysTick. */ - portNVIC_SYSTICK_CTRL_REG = 0UL; + /* Stop and reset SysTick. + * + * QEMU versions older than 7.0.0 contain a bug which causes an error if we + * enable SysTick without first selecting a valid clock source. We trigger + * the bug if we change clock sources from a clock with a zero clock period + * to one with a nonzero clock period and enable Systick at the same time. + * So we configure the CLKSOURCE bit here, prior to setting the ENABLE bit. + * This workaround avoids the bug in QEMU versions older than 7.0.0. */ + portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT_CONFIG; portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL; /* Configure SysTick to interrupt at the requested rate. */ @@ -819,6 +850,7 @@ static void prvTaskExitError( void ) static void prvSetupMPU( void ) /* PRIVILEGED_FUNCTION */ { #if defined( __ARMCC_VERSION ) + /* Declaration when these variable are defined in code instead of being * exported from linker scripts. */ extern uint32_t * __privileged_functions_start__; @@ -972,13 +1004,19 @@ void SysTick_Handler( void ) /* PRIVILEGED_FUNCTION */ uint32_t ulPreviousMask; ulPreviousMask = portSET_INTERRUPT_MASK_FROM_ISR(); + traceISR_ENTER(); { /* Increment the RTOS tick. */ if( xTaskIncrementTick() != pdFALSE ) { + traceISR_EXIT_TO_SCHEDULER(); /* Pend a context switch. */ portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; } + else + { + traceISR_EXIT(); + } } portCLEAR_INTERRUPT_MASK_FROM_ISR( ulPreviousMask ); } @@ -988,6 +1026,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO { #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) ) #if defined( __ARMCC_VERSION ) + /* Declaration when these variable are defined in code instead of being * exported from linker scripts. */ extern uint32_t * __syscalls_flash_start__; @@ -1083,18 +1122,24 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO vRestoreContextOfFirstTask(); break; - #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) ) - case portSVC_RAISE_PRIVILEGE: + #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) ) + case portSVC_RAISE_PRIVILEGE: - /* Only raise the privilege, if the svc was raised from any of - * the system calls. */ - if( ( ulPC >= ( uint32_t ) __syscalls_flash_start__ ) && - ( ulPC <= ( uint32_t ) __syscalls_flash_end__ ) ) - { - vRaisePrivilege(); - } - break; - #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) */ + /* Only raise the privilege, if the svc was raised from any of + * the system calls. */ + if( ( ulPC >= ( uint32_t ) __syscalls_flash_start__ ) && + ( ulPC <= ( uint32_t ) __syscalls_flash_end__ ) ) + { + vRaisePrivilege(); + } + break; + #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) */ + + #if ( configENABLE_MPU == 1 ) + case portSVC_YIELD: + vPortYield(); + break; + #endif /* configENABLE_MPU == 1 */ default: /* Incorrect SVC call. */ @@ -1154,12 +1199,11 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO { /* Extended frame i.e. FPU in use. */ ulStackFrameSize = 26; - __asm volatile - ( + __asm volatile ( " vpush {s0} \n" /* Trigger lazy stacking. */ " vpop {s0} \n" /* Nullify the affect of the above instruction. */ ::: "memory" - ); + ); } else { @@ -1171,7 +1215,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO { ulStackFrameSize = 8; } - #endif /* if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */ + #endif /* configENABLE_FPU || configENABLE_MVE */ /* Make space on the system call stack for the stack frame. */ pulSystemCallStack = pulSystemCallStack - ulStackFrameSize; @@ -1187,18 +1231,24 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO * point (i.e. the caller of the MPU_). We need to restore it * when we exit from the system call. */ pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry = pulTaskStack[ portOFFSET_TO_LR ]; - /* Store the value of the PSPLIM register before the SVC was raised. * We need to restore it when we exit from the system call. */ - __asm volatile ( "mrs %0, psplim" : "=r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) ); + #if ( portUSE_PSPLIM_REGISTER == 1 ) + { + __asm volatile ( "mrs %0, psplim" : "=r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) ); + } + #endif /* Use the pulSystemCallStack in thread mode. */ __asm volatile ( "msr psp, %0" : : "r" ( pulSystemCallStack ) ); - __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) ); + #if ( portUSE_PSPLIM_REGISTER == 1 ) + { + __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) ); + } + #endif /* Start executing the system call upon returning from this handler. */ pulSystemCallStack[ portOFFSET_TO_PC ] = uxSystemCallImplementations[ ucSystemCallNumber ]; - /* Raise a request to exit from the system call upon finishing the * system call. */ pulSystemCallStack[ portOFFSET_TO_LR ] = ( uint32_t ) vRequestSystemCallExit; @@ -1224,14 +1274,13 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO pulSystemCallStack[ portOFFSET_TO_PSR ] &= ( ~portPSR_STACK_PADDING_MASK ); /* Raise the privilege for the duration of the system call. */ - __asm volatile - ( + __asm volatile ( " mrs r0, control \n" /* Obtain current control value. */ " movs r1, #1 \n" /* r1 = 1. */ " bics r0, r1 \n" /* Clear nPRIV bit. */ " msr control, r0 \n" /* Write back new control value. */ ::: "r0", "r1", "memory" - ); + ); } } @@ -1293,12 +1342,11 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO { /* Extended frame i.e. FPU in use. */ ulStackFrameSize = 26; - __asm volatile - ( + __asm volatile ( " vpush {s0} \n" /* Trigger lazy stacking. */ " vpop {s0} \n" /* Nullify the affect of the above instruction. */ ::: "memory" - ); + ); } else { @@ -1310,7 +1358,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO { ulStackFrameSize = 8; } - #endif /* if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */ + #endif /* configENABLE_FPU || configENABLE_MVE */ /* Make space on the task stack for the stack frame. */ pulTaskStack = pulTaskStack - ulStackFrameSize; @@ -1332,7 +1380,11 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO /* Restore the PSPLIM register to what it was at the time of * system call entry. */ - __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) ); + #if ( portUSE_PSPLIM_REGISTER == 1 ) + { + __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) ); + } + #endif /* If the hardware used padding to force the stack pointer * to be double word aligned, set the stacked xPSR bit[9], @@ -1350,14 +1402,13 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO pxMpuSettings->xSystemCallStackInfo.pulTaskStack = NULL; /* Drop the privilege before returning to the thread mode. */ - __asm volatile - ( + __asm volatile ( " mrs r0, control \n" /* Obtain current control value. */ " movs r1, #1 \n" /* r1 = 1. */ " orrs r0, r1 \n" /* Set nPRIV bit. */ " msr control, r0 \n" /* Write back new control value. */ ::: "r0", "r1", "memory" - ); + ); } } @@ -1410,21 +1461,21 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO xMPUSettings->ulContext[ ulIndex ] = 0x11111111; /* r11. */ ulIndex++; - xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pvParameters; /* r0. */ + xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pvParameters; /* r0. */ ulIndex++; - xMPUSettings->ulContext[ ulIndex ] = 0x01010101; /* r1. */ + xMPUSettings->ulContext[ ulIndex ] = 0x01010101; /* r1. */ ulIndex++; - xMPUSettings->ulContext[ ulIndex ] = 0x02020202; /* r2. */ + xMPUSettings->ulContext[ ulIndex ] = 0x02020202; /* r2. */ ulIndex++; - xMPUSettings->ulContext[ ulIndex ] = 0x03030303; /* r3. */ + xMPUSettings->ulContext[ ulIndex ] = 0x03030303; /* r3. */ ulIndex++; - xMPUSettings->ulContext[ ulIndex ] = 0x12121212; /* r12. */ + xMPUSettings->ulContext[ ulIndex ] = 0x12121212; /* r12. */ ulIndex++; xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portTASK_RETURN_ADDRESS; /* LR. */ ulIndex++; - xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxCode; /* PC. */ + xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxCode; /* PC. */ ulIndex++; - xMPUSettings->ulContext[ ulIndex ] = portINITIAL_XPSR; /* xPSR. */ + xMPUSettings->ulContext[ ulIndex ] = portINITIAL_XPSR; /* xPSR. */ ulIndex++; #if ( configENABLE_TRUSTZONE == 1 ) @@ -1435,8 +1486,9 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO #endif /* configENABLE_TRUSTZONE */ xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) ( pxTopOfStack - 8 ); /* PSP with the hardware saved stack. */ ulIndex++; - xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxEndOfStack; /* PSPLIM. */ + xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxEndOfStack; /* PSPLIM. */ ulIndex++; + if( xRunPrivileged == pdTRUE ) { xMPUSettings->ulTaskFlags |= portTASK_IS_PRIVILEGED_FLAG; @@ -1449,6 +1501,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portINITIAL_CONTROL_UNPRIVILEGED; /* CONTROL. */ ulIndex++; } + xMPUSettings->ulContext[ ulIndex ] = portINITIAL_EXC_RETURN; /* LR (EXC_RETURN). */ ulIndex++; @@ -1483,7 +1536,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO * interrupt. */ #if ( portPRELOAD_REGISTERS == 0 ) { - pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */ + pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */ *pxTopOfStack = portINITIAL_XPSR; /* xPSR. */ pxTopOfStack--; *pxTopOfStack = ( StackType_t ) pxCode; /* PC. */ @@ -1505,7 +1558,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO } #else /* portPRELOAD_REGISTERS */ { - pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */ + pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */ *pxTopOfStack = portINITIAL_XPSR; /* xPSR. */ pxTopOfStack--; *pxTopOfStack = ( StackType_t ) pxCode; /* PC. */ @@ -1540,7 +1593,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO pxTopOfStack--; *pxTopOfStack = portINITIAL_EXC_RETURN; /* EXC_RETURN. */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */ + *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */ #if ( configENABLE_TRUSTZONE == 1 ) { @@ -1559,22 +1612,52 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */ { - #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) ) + /* An application can install FreeRTOS interrupt handlers in one of the + * folllowing ways: + * 1. Direct Routing - Install the functions SVC_Handler and PendSV_Handler + * for SVCall and PendSV interrupts respectively. + * 2. Indirect Routing - Install separate handlers for SVCall and PendSV + * interrupts and route program control from those handlers to + * SVC_Handler and PendSV_Handler functions. + * + * Applications that use Indirect Routing must set + * configCHECK_HANDLER_INSTALLATION to 0 in their FreeRTOSConfig.h. Direct + * routing, which is validated here when configCHECK_HANDLER_INSTALLATION + * is 1, should be preferred when possible. */ + #if ( configCHECK_HANDLER_INSTALLATION == 1 ) + { + const portISR_t * const pxVectorTable = portSCB_VTOR_REG; + + /* Validate that the application has correctly installed the FreeRTOS + * handlers for SVCall and PendSV interrupts. We do not check the + * installation of the SysTick handler because the application may + * choose to drive the RTOS tick using a timer other than the SysTick + * timer by overriding the weak function vPortSetupTimerInterrupt(). + * + * Assertion failures here indicate incorrect installation of the + * FreeRTOS handlers. For help installing the FreeRTOS handlers, see + * https://www.FreeRTOS.org/FAQHelp.html. + * + * Systems with a configurable address for the interrupt vector table + * can also encounter assertion failures or even system faults here if + * VTOR is not set correctly to point to the application's vector table. */ + configASSERT( pxVectorTable[ portVECTOR_INDEX_SVC ] == SVC_Handler ); + configASSERT( pxVectorTable[ portVECTOR_INDEX_PENDSV ] == PendSV_Handler ); + } + #endif /* configCHECK_HANDLER_INSTALLATION */ + + #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) { - volatile uint32_t ulOriginalPriority; volatile uint32_t ulImplementedPrioBits = 0; volatile uint8_t ucMaxPriorityValue; /* Determine the maximum priority from which ISR safe FreeRTOS API - * functions can be called. ISR safe functions are those that end in - * "FromISR". FreeRTOS maintains separate thread and ISR API functions to + * functions can be called. ISR safe functions are those that end in + * "FromISR". FreeRTOS maintains separate thread and ISR API functions to * ensure interrupt entry is as fast and simple as possible. * - * Save the interrupt priority value that is about to be clobbered. */ - ulOriginalPriority = portNVIC_SHPR2_REG; - - /* Determine the number of priority bits available. First write to all - * possible bits. */ + * First, determine the number of priority bits available. Write to all + * possible bits in the priority setting for SVCall. */ portNVIC_SHPR2_REG = 0xFF000000; /* Read the value back to see how many bits stuck. */ @@ -1593,11 +1676,10 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */ /* Check that the bits not implemented in hardware are zero in * configMAX_SYSCALL_INTERRUPT_PRIORITY. */ - configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( ~ucMaxPriorityValue ) ) == 0U ); + configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( uint8_t ) ( ~( uint32_t ) ucMaxPriorityValue ) ) == 0U ); /* Calculate the maximum acceptable priority group value for the number * of bits read back. */ - while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE ) { ulImplementedPrioBits++; @@ -1635,16 +1717,14 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */ * register. */ ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT; ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK; - - /* Restore the clobbered interrupt priority register to its original - * value. */ - portNVIC_SHPR2_REG = ulOriginalPriority; } - #endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) ) */ + #endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */ - /* Make PendSV, CallSV and SysTick the same priority as the kernel. */ + /* Make PendSV and SysTick the lowest priority interrupts, and make SVCall + * the highest priority. */ portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI; portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI; + portNVIC_SHPR2_REG = 0; #if ( configENABLE_MPU == 1 ) { @@ -1701,6 +1781,7 @@ void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */ int32_t lIndex = 0; #if defined( __ARMCC_VERSION ) + /* Declaration when these variable are defined in code instead of being * exported from linker scripts. */ extern uint32_t * __privileged_sram_start__; @@ -1886,7 +1967,7 @@ BaseType_t xPortIsInsideInterrupt( void ) } /*-----------------------------------------------------------*/ -#if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) ) +#if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) void vPortValidateInterruptPriority( void ) { @@ -1944,7 +2025,7 @@ BaseType_t xPortIsInsideInterrupt( void ) configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue ); } -#endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) ) */ +#endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */ /*-----------------------------------------------------------*/ #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) diff --git a/Source/portable/IAR/ARM_CM85_NTZ/non_secure/portasm.h b/Source/portable/IAR/ARM_CM85_NTZ/non_secure/portasm.h index f64ceb525..c6d2ebd58 100644 --- a/Source/portable/IAR/ARM_CM85_NTZ/non_secure/portasm.h +++ b/Source/portable/IAR/ARM_CM85_NTZ/non_secure/portasm.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/Source/portable/IAR/ARM_CM85_NTZ/non_secure/portasm.s b/Source/portable/IAR/ARM_CM85_NTZ/non_secure/portasm.s index 00ee5a5cb..cb3ad91f9 100644 --- a/Source/portable/IAR/ARM_CM85_NTZ/non_secure/portasm.s +++ b/Source/portable/IAR/ARM_CM85_NTZ/non_secure/portasm.s @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/Source/portable/IAR/ARM_CM85_NTZ/non_secure/portmacro.h b/Source/portable/IAR/ARM_CM85_NTZ/non_secure/portmacro.h index 4f7cf2bc0..024ce2b15 100644 --- a/Source/portable/IAR/ARM_CM85_NTZ/non_secure/portmacro.h +++ b/Source/portable/IAR/ARM_CM85_NTZ/non_secure/portmacro.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -53,16 +53,16 @@ /** * Architecture specifics. */ -#define portARCH_NAME "Cortex-M85" -#define portHAS_BASEPRI 1 -#define portDONT_DISCARD __root +#define portARCH_NAME "Cortex-M85" +#define portHAS_ARMV8M_MAIN_EXTENSION 1 +#define portDONT_DISCARD __root /*-----------------------------------------------------------*/ /* ARMv8-M common port configurations. */ #include "portmacrocommon.h" /*-----------------------------------------------------------*/ -#if( configTOTAL_MPU_REGIONS == 16 ) +#if ( configTOTAL_MPU_REGIONS == 16 ) #error 16 MPU regions are not yet supported for this port. #endif /*-----------------------------------------------------------*/ @@ -70,8 +70,8 @@ /** * @brief Critical section management. */ -#define portDISABLE_INTERRUPTS() ulSetInterruptMask() -#define portENABLE_INTERRUPTS() vClearInterruptMask( 0 ) +#define portDISABLE_INTERRUPTS() ulSetInterruptMask() +#define portENABLE_INTERRUPTS() vClearInterruptMask( 0 ) /*-----------------------------------------------------------*/ /* Suppress warnings that are generated by the IAR tools, but cannot be fixed in diff --git a/Source/portable/IAR/ARM_CM85_NTZ/non_secure/portmacrocommon.h b/Source/portable/IAR/ARM_CM85_NTZ/non_secure/portmacrocommon.h index 6f666da22..33f21d85b 100644 --- a/Source/portable/IAR/ARM_CM85_NTZ/non_secure/portmacrocommon.h +++ b/Source/portable/IAR/ARM_CM85_NTZ/non_secure/portmacrocommon.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -117,7 +117,7 @@ extern uint32_t ulSetInterruptMask( void ) /* __attribute__(( naked )) PRIVILEGE extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */; #if ( configENABLE_TRUSTZONE == 1 ) - extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize ); /* __attribute__ (( naked )) */ + extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize ); /* __attribute__ (( naked )) */ extern void vPortFreeSecureContext( uint32_t * pulTCB ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */; #endif /* configENABLE_TRUSTZONE */ @@ -188,13 +188,13 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P #if ( configENABLE_MPU == 1 ) - /** - * @brief Settings to define an MPU region. - */ +/** + * @brief Settings to define an MPU region. + */ typedef struct MPURegionSettings { - uint32_t ulRBAR; /**< RBAR for the region. */ - uint32_t ulRLAR; /**< RLAR for the region. */ + uint32_t ulRBAR; /**< RBAR for the region. */ + uint32_t ulRLAR; /**< RLAR for the region. */ } MPURegionSettings_t; #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) @@ -203,9 +203,9 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P #error configSYSTEM_CALL_STACK_SIZE must be defined to the desired size of the system call stack in words for using MPU wrappers v2. #endif - /** - * @brief System call stack. - */ +/** + * @brief System call stack. + */ typedef struct SYSTEM_CALL_STACK_INFO { uint32_t ulSystemCallStackBuffer[ configSYSTEM_CALL_STACK_SIZE ]; @@ -218,74 +218,74 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P #endif /* configUSE_MPU_WRAPPERS_V1 == 0 */ - /** - * @brief MPU settings as stored in the TCB. - */ +/** + * @brief MPU settings as stored in the TCB. + */ #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) - #if( configENABLE_TRUSTZONE == 1 ) + #if ( configENABLE_TRUSTZONE == 1 ) - /* - * +-----------+---------------+----------+-----------------+------------------------------+-----+ - * | s16-s31 | s0-s15, FPSCR | r4-r11 | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, | | - * | | | | PC, xPSR | CONTROL, EXC_RETURN | | - * +-----------+---------------+----------+-----------------+------------------------------+-----+ - * - * <-----------><--------------><---------><----------------><-----------------------------><----> - * 16 16 8 8 5 1 - */ - #define MAX_CONTEXT_SIZE 54 +/* + * +-----------+---------------+----------+-----------------+------------------------------+-----+ + * | s16-s31 | s0-s15, FPSCR | r4-r11 | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, | | + * | | | | PC, xPSR | CONTROL, EXC_RETURN | | + * +-----------+---------------+----------+-----------------+------------------------------+-----+ + * + * <-----------><--------------><---------><----------------><-----------------------------><----> + * 16 16 8 8 5 1 + */ + #define MAX_CONTEXT_SIZE 54 #else /* #if( configENABLE_TRUSTZONE == 1 ) */ - /* - * +-----------+---------------+----------+-----------------+----------------------+-----+ - * | s16-s31 | s0-s15, FPSCR | r4-r11 | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL | | - * | | | | PC, xPSR | EXC_RETURN | | - * +-----------+---------------+----------+-----------------+----------------------+-----+ - * - * <-----------><--------------><---------><----------------><---------------------><----> - * 16 16 8 8 4 1 - */ - #define MAX_CONTEXT_SIZE 53 +/* + * +-----------+---------------+----------+-----------------+----------------------+-----+ + * | s16-s31 | s0-s15, FPSCR | r4-r11 | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL | | + * | | | | PC, xPSR | EXC_RETURN | | + * +-----------+---------------+----------+-----------------+----------------------+-----+ + * + * <-----------><--------------><---------><----------------><---------------------><----> + * 16 16 8 8 4 1 + */ + #define MAX_CONTEXT_SIZE 53 #endif /* #if( configENABLE_TRUSTZONE == 1 ) */ #else /* #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */ - #if( configENABLE_TRUSTZONE == 1 ) + #if ( configENABLE_TRUSTZONE == 1 ) - /* - * +----------+-----------------+------------------------------+-----+ - * | r4-r11 | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, | | - * | | PC, xPSR | CONTROL, EXC_RETURN | | - * +----------+-----------------+------------------------------+-----+ - * - * <---------><----------------><------------------------------><----> - * 8 8 5 1 - */ - #define MAX_CONTEXT_SIZE 22 +/* + * +----------+-----------------+------------------------------+-----+ + * | r4-r11 | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, | | + * | | PC, xPSR | CONTROL, EXC_RETURN | | + * +----------+-----------------+------------------------------+-----+ + * + * <---------><----------------><------------------------------><----> + * 8 8 5 1 + */ + #define MAX_CONTEXT_SIZE 22 #else /* #if( configENABLE_TRUSTZONE == 1 ) */ - /* - * +----------+-----------------+----------------------+-----+ - * | r4-r11 | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL | | - * | | PC, xPSR | EXC_RETURN | | - * +----------+-----------------+----------------------+-----+ - * - * <---------><----------------><----------------------><----> - * 8 8 4 1 - */ - #define MAX_CONTEXT_SIZE 21 +/* + * +----------+-----------------+----------------------+-----+ + * | r4-r11 | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL | | + * | | PC, xPSR | EXC_RETURN | | + * +----------+-----------------+----------------------+-----+ + * + * <---------><----------------><----------------------><----> + * 8 8 4 1 + */ + #define MAX_CONTEXT_SIZE 21 #endif /* #if( configENABLE_TRUSTZONE == 1 ) */ #endif /* #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */ - /* Flags used for xMPU_SETTINGS.ulTaskFlags member. */ - #define portSTACK_FRAME_HAS_PADDING_FLAG ( 1UL << 0UL ) - #define portTASK_IS_PRIVILEGED_FLAG ( 1UL << 1UL ) +/* Flags used for xMPU_SETTINGS.ulTaskFlags member. */ + #define portSTACK_FRAME_HAS_PADDING_FLAG ( 1UL << 0UL ) + #define portTASK_IS_PRIVILEGED_FLAG ( 1UL << 1UL ) /* Size of an Access Control List (ACL) entry in bits. */ #define portACL_ENTRY_SIZE_BITS ( 32U ) @@ -313,7 +313,7 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P * system calls. */ #ifdef configASSERT - #if ( portHAS_BASEPRI == 1 ) + #if ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) void vPortValidateInterruptPriority( void ); #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() vPortValidateInterruptPriority() #endif @@ -333,12 +333,29 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P /** * @brief Scheduler utilities. */ -#define portYIELD() vPortYield() +#if ( configENABLE_MPU == 1 ) + #define portYIELD() __asm volatile ( "svc %0" ::"i" ( portSVC_YIELD ) : "memory" ) + #define portYIELD_WITHIN_API() vPortYield() +#else + #define portYIELD() vPortYield() + #define portYIELD_WITHIN_API() vPortYield() +#endif + #define portNVIC_INT_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed04 ) ) #define portNVIC_PENDSVSET_BIT ( 1UL << 28UL ) -#define portEND_SWITCHING_ISR( xSwitchRequired ) \ - do { if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; } \ - while( 0 ) +#define portEND_SWITCHING_ISR( xSwitchRequired ) \ + do \ + { \ + if( xSwitchRequired ) \ + { \ + traceISR_EXIT_TO_SCHEDULER(); \ + portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; \ + } \ + else \ + { \ + traceISR_EXIT(); \ + } \ + } while( 0 ) #define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x ) /*-----------------------------------------------------------*/ @@ -424,12 +441,12 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P extern BaseType_t xPortIsTaskPrivileged( void ); - /** - * @brief Checks whether or not the calling task is privileged. - * - * @return pdTRUE if the calling task is privileged, pdFALSE otherwise. - */ - #define portIS_TASK_PRIVILEGED() xPortIsTaskPrivileged() +/** + * @brief Checks whether or not the calling task is privileged. + * + * @return pdTRUE if the calling task is privileged, pdFALSE otherwise. + */ + #define portIS_TASK_PRIVILEGED() xPortIsTaskPrivileged() #endif /* configENABLE_MPU == 1 */ /*-----------------------------------------------------------*/ @@ -440,6 +457,56 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P #define portMEMORY_BARRIER() __asm volatile ( "" ::: "memory" ) /*-----------------------------------------------------------*/ +/* Select correct value of configUSE_PORT_OPTIMISED_TASK_SELECTION + * based on whether or not Mainline extension is implemented. */ +#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION + #if ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) + #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1 + #else + #define configUSE_PORT_OPTIMISED_TASK_SELECTION 0 + #endif +#endif /* #ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION */ + +/** + * @brief Port-optimised task selection. + */ +#if ( configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 ) + +/** + * @brief Count the number of leading zeros in a 32-bit value. + */ + static portFORCE_INLINE uint32_t ulPortCountLeadingZeros( uint32_t ulBitmap ) + { + uint32_t ulReturn; + + __asm volatile ( "clz %0, %1" : "=r" ( ulReturn ) : "r" ( ulBitmap ) : "memory" ); + + return ulReturn; + } + +/* Check the configuration. */ + #if ( configMAX_PRIORITIES > 32 ) + #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 different priorities as tasks that share a priority will time slice. + #endif + + #if ( portHAS_ARMV8M_MAIN_EXTENSION == 0 ) + #error ARMv8-M baseline implementations (such as Cortex-M23) do not support port-optimised task selection. Please set configUSE_PORT_OPTIMISED_TASK_SELECTION to 0 or leave it undefined. + #endif + +/** + * @brief Store/clear the ready priorities in a bit map. + */ + #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) ) + #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) ) + +/** + * @brief Get the priority of the highest-priority task that is ready to execute. + */ + #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - ulPortCountLeadingZeros( ( uxReadyPriorities ) ) ) + +#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */ +/*-----------------------------------------------------------*/ + /* *INDENT-OFF* */ #ifdef __cplusplus } diff --git a/Source/portable/IAR/ARM_CRx_No_GIC/port.c b/Source/portable/IAR/ARM_CRx_No_GIC/port.c index bd810aab3..2549b4e0d 100644 --- a/Source/portable/IAR/ARM_CRx_No_GIC/port.c +++ b/Source/portable/IAR/ARM_CRx_No_GIC/port.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -35,7 +35,7 @@ #if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 /* Check the configuration. */ - #if( configMAX_PRIORITIES > 32 ) + #if ( configMAX_PRIORITIES > 32 ) #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice. #endif #endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */ @@ -49,35 +49,35 @@ #endif /* A critical section is exited when the critical section nesting count reaches -this value. */ -#define portNO_CRITICAL_NESTING ( ( uint32_t ) 0 ) + * this value. */ +#define portNO_CRITICAL_NESTING ( ( uint32_t ) 0 ) /* Tasks are not created with a floating point context, but can be given a -floating point context after they have been created. A variable is stored as -part of the tasks context that holds portNO_FLOATING_POINT_CONTEXT if the task -does not have an FPU context, or any other value if the task does have an FPU -context. */ -#define portNO_FLOATING_POINT_CONTEXT ( ( StackType_t ) 0 ) + * floating point context after they have been created. A variable is stored as + * part of the tasks context that holds portNO_FLOATING_POINT_CONTEXT if the task + * does not have an FPU context, or any other value if the task does have an FPU + * context. */ +#define portNO_FLOATING_POINT_CONTEXT ( ( StackType_t ) 0 ) /* Constants required to setup the initial task context. */ -#define portINITIAL_SPSR ( ( StackType_t ) 0x1f ) /* System mode, ARM mode, IRQ enabled FIQ enabled. */ -#define portTHUMB_MODE_BIT ( ( StackType_t ) 0x20 ) -#define portTHUMB_MODE_ADDRESS ( 0x01UL ) +#define portINITIAL_SPSR ( ( StackType_t ) 0x1f ) /* System mode, ARM mode, IRQ enabled FIQ enabled. */ +#define portTHUMB_MODE_BIT ( ( StackType_t ) 0x20 ) +#define portTHUMB_MODE_ADDRESS ( 0x01UL ) /* Masks all bits in the APSR other than the mode bits. */ -#define portAPSR_MODE_BITS_MASK ( 0x1F ) +#define portAPSR_MODE_BITS_MASK ( 0x1F ) /* The value of the mode bits in the APSR when the CPU is executing in user -mode. */ -#define portAPSR_USER_MODE ( 0x10 ) + * mode. */ +#define portAPSR_USER_MODE ( 0x10 ) /* Let the user override the pre-loading of the initial LR with the address of -prvTaskExitError() in case it messes up unwinding of the stack in the -debugger. */ + * prvTaskExitError() in case it messes up unwinding of the stack in the + * debugger. */ #ifdef configTASK_RETURN_ADDRESS - #define portTASK_RETURN_ADDRESS configTASK_RETURN_ADDRESS + #define portTASK_RETURN_ADDRESS configTASK_RETURN_ADDRESS #else - #define portTASK_RETURN_ADDRESS prvTaskExitError + #define portTASK_RETURN_ADDRESS prvTaskExitError #endif /*-----------------------------------------------------------*/ @@ -96,21 +96,21 @@ static void prvTaskExitError( void ); /*-----------------------------------------------------------*/ /* A variable is used to keep track of the critical section nesting. This -variable has to be stored as part of the task context and must be initialised to -a non zero value to ensure interrupts don't inadvertently become unmasked before -the scheduler starts. As it is stored as part of the task context it will -automatically be set to 0 when the first task is started. */ + * variable has to be stored as part of the task context and must be initialised to + * a non zero value to ensure interrupts don't inadvertently become unmasked before + * the scheduler starts. As it is stored as part of the task context it will + * automatically be set to 0 when the first task is started. */ volatile uint32_t ulCriticalNesting = 9999UL; /* Saved as part of the task context. If ulPortTaskHasFPUContext is non-zero then -a floating point context must be saved and restored for the task. */ + * a floating point context must be saved and restored for the task. */ volatile uint32_t ulPortTaskHasFPUContext = pdFALSE; /* Set to 1 to pend a context switch from an ISR. */ volatile uint32_t ulPortYieldRequired = pdFALSE; /* Counts the interrupt nesting depth. A context switch is only performed if -if the nesting depth is 0. */ + * if the nesting depth is 0. */ volatile uint32_t ulPortInterruptNesting = 0UL; /*-----------------------------------------------------------*/ @@ -118,14 +118,16 @@ volatile uint32_t ulPortInterruptNesting = 0UL; /* * See header file for description. */ -StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters ) +StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, + TaskFunction_t pxCode, + void * pvParameters ) { /* Setup the initial stack of the task. The stack is set exactly as - expected by the portRESTORE_CONTEXT() macro. - - The fist real value on the stack is the status register, which is set for - system mode, with interrupts enabled. A few NULLs are added first to ensure - GDB does not try decoding a non-existent return address. */ + * expected by the portRESTORE_CONTEXT() macro. + * + * The fist real value on the stack is the status register, which is set for + * system mode, with interrupts enabled. A few NULLs are added first to ensure + * GDB does not try decoding a non-existent return address. */ *pxTopOfStack = ( StackType_t ) NULL; pxTopOfStack--; *pxTopOfStack = ( StackType_t ) NULL; @@ -147,43 +149,43 @@ StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t px pxTopOfStack--; /* Next all the registers other than the stack pointer. */ - *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* R14 */ + *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* R14 */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x12121212; /* R12 */ + *pxTopOfStack = ( StackType_t ) 0x12121212; /* R12 */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x11111111; /* R11 */ + *pxTopOfStack = ( StackType_t ) 0x11111111; /* R11 */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x10101010; /* R10 */ + *pxTopOfStack = ( StackType_t ) 0x10101010; /* R10 */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x09090909; /* R9 */ + *pxTopOfStack = ( StackType_t ) 0x09090909; /* R9 */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x08080808; /* R8 */ + *pxTopOfStack = ( StackType_t ) 0x08080808; /* R8 */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x07070707; /* R7 */ + *pxTopOfStack = ( StackType_t ) 0x07070707; /* R7 */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x06060606; /* R6 */ + *pxTopOfStack = ( StackType_t ) 0x06060606; /* R6 */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x05050505; /* R5 */ + *pxTopOfStack = ( StackType_t ) 0x05050505; /* R5 */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x04040404; /* R4 */ + *pxTopOfStack = ( StackType_t ) 0x04040404; /* R4 */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x03030303; /* R3 */ + *pxTopOfStack = ( StackType_t ) 0x03030303; /* R3 */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x02020202; /* R2 */ + *pxTopOfStack = ( StackType_t ) 0x02020202; /* R2 */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x01010101; /* R1 */ + *pxTopOfStack = ( StackType_t ) 0x01010101; /* R1 */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */ + *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */ pxTopOfStack--; /* The task will start with a critical nesting count of 0 as interrupts are - enabled. */ + * enabled. */ *pxTopOfStack = portNO_CRITICAL_NESTING; pxTopOfStack--; /* The task will start without a floating point context. A task that uses - the floating point hardware must call vPortTaskUsesFPU() before executing - any floating point instructions. */ + * the floating point hardware must call vPortTaskUsesFPU() before executing + * any floating point instructions. */ *pxTopOfStack = portNO_FLOATING_POINT_CONTEXT; return pxTopOfStack; @@ -193,24 +195,28 @@ StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t px static void prvTaskExitError( void ) { /* A function that implements a task must not exit or attempt to return to - its caller as there is nothing to return to. If a task wants to exit it - should instead call vTaskDelete( NULL ). - - Artificially force an assert() to be triggered if configASSERT() is - defined, then stop here so application writers can catch the error. */ + * its caller as there is nothing to return to. If a task wants to exit it + * should instead call vTaskDelete( NULL ). + * + * Artificially force an assert() to be triggered if configASSERT() is + * defined, then stop here so application writers can catch the error. */ configASSERT( ulPortInterruptNesting == ~0UL ); portDISABLE_INTERRUPTS(); - for( ;; ); + + for( ; ; ) + { + } } /*-----------------------------------------------------------*/ BaseType_t xPortStartScheduler( void ) { -uint32_t ulAPSR; + uint32_t ulAPSR; /* Only continue if the CPU is not in User mode. The CPU must be in a - Privileged mode for the scheduler to start. */ + * Privileged mode for the scheduler to start. */ __asm volatile ( "MRS %0, APSR" : "=r" ( ulAPSR ) ); + ulAPSR &= portAPSR_MODE_BITS_MASK; configASSERT( ulAPSR != portAPSR_USER_MODE ); @@ -225,10 +231,10 @@ uint32_t ulAPSR; } /* Will only get here if vTaskStartScheduler() was called with the CPU in - a non-privileged mode or the binary point register was not set to its lowest - possible value. prvTaskExitError() is referenced to prevent a compiler - warning about it being defined but not referenced in the case that the user - defines their own exit address. */ + * a non-privileged mode or the binary point register was not set to its lowest + * possible value. prvTaskExitError() is referenced to prevent a compiler + * warning about it being defined but not referenced in the case that the user + * defines their own exit address. */ ( void ) prvTaskExitError; return 0; } @@ -237,7 +243,7 @@ uint32_t ulAPSR; void vPortEndScheduler( void ) { /* Not implemented in ports where there is nothing to return to. - Artificially force an assert. */ + * Artificially force an assert. */ configASSERT( ulCriticalNesting == 1000UL ); } /*-----------------------------------------------------------*/ @@ -246,16 +252,16 @@ void vPortEnterCritical( void ) { portDISABLE_INTERRUPTS(); - /* Now interrupts are disabled ulCriticalNesting can be accessed - directly. Increment ulCriticalNesting to keep a count of how many times - portENTER_CRITICAL() has been called. */ + /* Now that interrupts are disabled, ulCriticalNesting can be accessed + * directly. Increment ulCriticalNesting to keep a count of how many times + * portENTER_CRITICAL() has been called. */ ulCriticalNesting++; /* This is not the interrupt safe version of the enter critical function so - assert() if it is being called from an interrupt context. Only API - functions that end in "FromISR" can be used in an interrupt. Only assert if - the critical nesting count is 1 to protect against recursive calls if the - assert function also uses a critical section. */ + * assert() if it is being called from an interrupt context. Only API + * functions that end in "FromISR" can be used in an interrupt. Only assert if + * the critical nesting count is 1 to protect against recursive calls if the + * assert function also uses a critical section. */ if( ulCriticalNesting == 1 ) { configASSERT( ulPortInterruptNesting == 0 ); @@ -268,15 +274,15 @@ void vPortExitCritical( void ) if( ulCriticalNesting > portNO_CRITICAL_NESTING ) { /* Decrement the nesting count as the critical section is being - exited. */ + * exited. */ ulCriticalNesting--; /* If the nesting level has reached zero then all interrupt - priorities must be re-enabled. */ + * priorities must be re-enabled. */ if( ulCriticalNesting == portNO_CRITICAL_NESTING ) { /* Critical nesting has reached zero so all interrupt priorities - should be unmasked. */ + * should be unmasked. */ portENABLE_INTERRUPTS(); } } @@ -285,7 +291,7 @@ void vPortExitCritical( void ) void FreeRTOS_Tick_Handler( void ) { -uint32_t ulInterruptStatus; + uint32_t ulInterruptStatus; ulInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR(); @@ -303,13 +309,13 @@ uint32_t ulInterruptStatus; void vPortTaskUsesFPU( void ) { -uint32_t ulInitialFPSCR = 0; + uint32_t ulInitialFPSCR = 0; /* A task is registering the fact that it needs an FPU context. Set the - FPU flag (which is saved as part of the task context). */ + * FPU flag (which is saved as part of the task context). */ ulPortTaskHasFPUContext = pdTRUE; /* Initialise the floating point status register. */ - __asm volatile ( "FMXR FPSCR, %0" :: "r" (ulInitialFPSCR) ); + __asm volatile ( "FMXR FPSCR, %0" ::"r" ( ulInitialFPSCR ) ); } /*-----------------------------------------------------------*/ diff --git a/Source/portable/IAR/ARM_CRx_No_GIC/portASM.s b/Source/portable/IAR/ARM_CRx_No_GIC/portASM.s index bc9f112cb..b93382d9e 100644 --- a/Source/portable/IAR/ARM_CRx_No_GIC/portASM.s +++ b/Source/portable/IAR/ARM_CRx_No_GIC/portASM.s @@ -1,5 +1,5 @@ ;/* -; * FreeRTOS Kernel V10.6.2 +; * FreeRTOS Kernel V11.0.1 ; * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. ; * ; * SPDX-License-Identifier: MIT diff --git a/Source/portable/IAR/ARM_CRx_No_GIC/portmacro.h b/Source/portable/IAR/ARM_CRx_No_GIC/portmacro.h index a7dce0f83..5ed002c34 100644 --- a/Source/portable/IAR/ARM_CRx_No_GIC/portmacro.h +++ b/Source/portable/IAR/ARM_CRx_No_GIC/portmacro.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -48,55 +48,56 @@ */ /* Type definitions. */ -#define portCHAR char -#define portFLOAT float -#define portDOUBLE double -#define portLONG long -#define portSHORT short -#define portSTACK_TYPE uint32_t -#define portBASE_TYPE long +#define portCHAR char +#define portFLOAT float +#define portDOUBLE double +#define portLONG long +#define portSHORT short +#define portSTACK_TYPE uint32_t +#define portBASE_TYPE long -typedef portSTACK_TYPE StackType_t; -typedef long BaseType_t; -typedef unsigned long UBaseType_t; +typedef portSTACK_TYPE StackType_t; +typedef long BaseType_t; +typedef unsigned long UBaseType_t; -typedef uint32_t TickType_t; -#define portMAX_DELAY ( TickType_t ) 0xffffffffUL +typedef uint32_t TickType_t; +#define portMAX_DELAY ( TickType_t ) 0xffffffffUL /* 32-bit tick type on a 32-bit architecture, so reads of the tick count do -not need to be guarded with a critical section. */ -#define portTICK_TYPE_IS_ATOMIC 1 + * not need to be guarded with a critical section. */ +#define portTICK_TYPE_IS_ATOMIC 1 /*-----------------------------------------------------------*/ /* Hardware specifics. */ -#define portSTACK_GROWTH ( -1 ) -#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) -#define portBYTE_ALIGNMENT 8 +#define portSTACK_GROWTH ( -1 ) +#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) +#define portBYTE_ALIGNMENT 8 /*-----------------------------------------------------------*/ /* Task utilities. */ /* Called at the end of an ISR that can cause a context switch. */ -#define portEND_SWITCHING_ISR( xSwitchRequired )\ -{ \ -extern volatile uint32_t ulPortYieldRequired; \ - \ - if( xSwitchRequired != pdFALSE ) \ - { \ - ulPortYieldRequired = pdTRUE; \ - } \ -} +#define portEND_SWITCHING_ISR( xSwitchRequired ) \ + { \ + extern volatile uint32_t ulPortYieldRequired; \ + \ + if( xSwitchRequired != pdFALSE ) \ + { \ + ulPortYieldRequired = pdTRUE; \ + } \ + } -#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x ) -#define portYIELD() __asm volatile ( "SWI 0 \n" \ - "ISB " ); +#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x ) +#define portYIELD() \ + __asm volatile ( "SWI 0 \n" \ + "ISB " ); /*----------------------------------------------------------- - * Critical section control - *----------------------------------------------------------*/ +* Critical section control +*----------------------------------------------------------*/ extern void vPortEnterCritical( void ); extern void vPortExitCritical( void ); @@ -108,70 +109,72 @@ extern void vPortInstallFreeRTOSVectorTable( void ); #define portINTERRUPT_ENABLE_BIT ( 1 << 7 ) /* In the absence of a priority mask register, these functions and macros -globally enable and disable interrupts. */ -#define portENTER_CRITICAL() vPortEnterCritical(); -#define portEXIT_CRITICAL() vPortExitCritical(); -#define portENABLE_INTERRUPTS() __asm volatile ( "CPSIE i \n" ); -#define portDISABLE_INTERRUPTS() __asm volatile ( "CPSID i \n" \ - "DSB \n" \ - "ISB " ); + * globally enable and disable interrupts. */ +#define portENTER_CRITICAL() vPortEnterCritical(); +#define portEXIT_CRITICAL() vPortExitCritical(); +#define portENABLE_INTERRUPTS() __asm volatile ( "CPSIE i \n" ); +#define portDISABLE_INTERRUPTS() \ + __asm volatile ( "CPSID i \n" \ + "DSB \n" \ + "ISB " ); #pragma inline static inline uint32_t portINLINE_SET_INTERRUPT_MASK_FROM_ISR( void ) { -volatile uint32_t ulCPSR; + volatile uint32_t ulCPSR; + + __asm volatile ( "MRS %0, CPSR" : "=r" ( ulCPSR ) ); - __asm volatile ( "MRS %0, CPSR" : "=r" (ulCPSR) ); ulCPSR &= portINTERRUPT_ENABLE_BIT; portDISABLE_INTERRUPTS(); return ulCPSR; } -#define portSET_INTERRUPT_MASK_FROM_ISR() portINLINE_SET_INTERRUPT_MASK_FROM_ISR() -#define portCLEAR_INTERRUPT_MASK_FROM_ISR(x) do { if( x == 0 ) portENABLE_INTERRUPTS(); } while( 0 ) +#define portSET_INTERRUPT_MASK_FROM_ISR() portINLINE_SET_INTERRUPT_MASK_FROM_ISR() +#define portCLEAR_INTERRUPT_MASK_FROM_ISR( x ) do { if( x == 0 ) portENABLE_INTERRUPTS( ); } while( 0 ) /*-----------------------------------------------------------*/ /* Task function macros as described on the FreeRTOS.org WEB site. These are -not required for this port but included in case common demo code that uses these -macros is used. */ -#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters ) -#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters ) + * not required for this port but included in case common demo code that uses these + * macros is used. */ +#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters ) +#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters ) /* Prototype of the FreeRTOS tick handler. This must be installed as the -handler for whichever peripheral is used to generate the RTOS tick. */ + * handler for whichever peripheral is used to generate the RTOS tick. */ void FreeRTOS_Tick_Handler( void ); /* Any task that uses the floating point unit MUST call vPortTaskUsesFPU() -before any floating point instructions are executed. */ + * before any floating point instructions are executed. */ void vPortTaskUsesFPU( void ); -#define portTASK_USES_FLOATING_POINT() vPortTaskUsesFPU() +#define portTASK_USES_FLOATING_POINT() vPortTaskUsesFPU() -#define portLOWEST_INTERRUPT_PRIORITY ( ( ( uint32_t ) configUNIQUE_INTERRUPT_PRIORITIES ) - 1UL ) -#define portLOWEST_USABLE_INTERRUPT_PRIORITY ( portLOWEST_INTERRUPT_PRIORITY - 1UL ) +#define portLOWEST_INTERRUPT_PRIORITY ( ( ( uint32_t ) configUNIQUE_INTERRUPT_PRIORITIES ) - 1UL ) +#define portLOWEST_USABLE_INTERRUPT_PRIORITY ( portLOWEST_INTERRUPT_PRIORITY - 1UL ) /* Architecture specific optimisations. */ #ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION - #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1 + #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1 #endif #if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 - /* Store/clear the ready priorities in a bit map. */ - #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) ) - #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) ) +/* Store/clear the ready priorities in a bit map. */ + #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) ) + #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) ) - /*-----------------------------------------------------------*/ +/*-----------------------------------------------------------*/ - #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - ( uint32_t ) __CLZ( uxReadyPriorities ) ) + #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - ( uint32_t ) __CLZ( uxReadyPriorities ) ) #endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */ -#define portNOP() __asm volatile( "NOP" ) -#define portINLINE inline +#define portNOP() __asm volatile ( "NOP" ) +#define portINLINE inline /* Suppress warnings that are generated by the IAR tools, but cannot be fixed in -the source code because to do so would cause other compilers to generate -warnings. */ + * the source code because to do so would cause other compilers to generate + * warnings. */ #pragma diag_suppress=Pe191 #pragma diag_suppress=Pa082 diff --git a/Source/portable/IAR/ATMega323/port.c b/Source/portable/IAR/ATMega323/port.c index 0b93e5d85..4d47e309c 100644 --- a/Source/portable/IAR/ATMega323/port.c +++ b/Source/portable/IAR/ATMega323/port.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -32,8 +32,8 @@ #include "task.h" /*----------------------------------------------------------- - * Implementation of functions defined in portable.h for the AVR/IAR port. - *----------------------------------------------------------*/ +* Implementation of functions defined in portable.h for the AVR/IAR port. +*----------------------------------------------------------*/ /* Start tasks with interrupts enables. */ #define portFLAGS_INT_ENABLED ( ( StackType_t ) 0x80 ) @@ -49,8 +49,8 @@ /*-----------------------------------------------------------*/ /* Stores the critical section nesting. This must not be initialised to 0. -It will be initialised when a task starts. */ -#define portNO_CRITICAL_NESTING ( ( UBaseType_t ) 0 ) + * It will be initialised when a task starts. */ +#define portNO_CRITICAL_NESTING ( ( UBaseType_t ) 0 ) UBaseType_t uxCriticalNesting = 0x50; @@ -71,13 +71,15 @@ extern void vPortStart( void ); /* * See header file for description. */ -StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters ) +StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, + TaskFunction_t pxCode, + void * pvParameters ) { -uint16_t usAddress; -StackType_t *pxTopOfHardwareStack; + uint16_t usAddress; + StackType_t * pxTopOfHardwareStack; /* Place a few bytes of known values on the bottom of the stack. - This is just useful for debugging. */ + * This is just useful for debugging. */ *pxTopOfStack = 0x11; pxTopOfStack--; @@ -87,7 +89,7 @@ StackType_t *pxTopOfHardwareStack; pxTopOfStack--; /* Remember where the top of the hardware stack is - this is required - below. */ + * below. */ pxTopOfHardwareStack = pxTopOfStack; @@ -98,20 +100,20 @@ StackType_t *pxTopOfHardwareStack; /* The IAR compiler requires two stacks per task. First there is the - hardware call stack which uses the AVR stack pointer. Second there is the - software stack (local variables, parameter passing, etc.) which uses the - AVR Y register. - - This function places both stacks within the memory block passed in as the - first parameter. The hardware stack is placed at the bottom of the memory - block. A gap is then left for the hardware stack to grow. Next the software - stack is placed. The amount of space between the software and hardware - stacks is defined by configCALL_STACK_SIZE. - - - - The first part of the stack is the hardware stack. Place the start - address of the task on the hardware stack. */ + * hardware call stack which uses the AVR stack pointer. Second there is the + * software stack (local variables, parameter passing, etc.) which uses the + * AVR Y register. + * + * This function places both stacks within the memory block passed in as the + * first parameter. The hardware stack is placed at the bottom of the memory + * block. A gap is then left for the hardware stack to grow. Next the software + * stack is placed. The amount of space between the software and hardware + * stacks is defined by configCALL_STACK_SIZE. + * + * + * + * The first part of the stack is the hardware stack. Place the start + * address of the task on the hardware stack. */ usAddress = ( uint16_t ) pxCode; *pxTopOfStack = ( StackType_t ) ( usAddress & ( uint16_t ) 0x00ff ); pxTopOfStack--; @@ -122,23 +124,23 @@ StackType_t *pxTopOfHardwareStack; /* Leave enough space for the hardware stack before starting the software - stack. The '- 2' is because we have already used two spaces for the - address of the start of the task. */ + * stack. The '- 2' is because we have already used two spaces for the + * address of the start of the task. */ pxTopOfStack -= ( configCALL_STACK_SIZE - 2 ); /* Next simulate the stack as if after a call to portSAVE_CONTEXT(). - portSAVE_CONTEXT places the flags on the stack immediately after r0 - to ensure the interrupts get disabled as soon as possible, and so ensuring - the stack use is minimal should a context switch interrupt occur. */ - *pxTopOfStack = ( StackType_t ) 0x00; /* R0 */ + * portSAVE_CONTEXT places the flags on the stack immediately after r0 + * to ensure the interrupts get disabled as soon as possible, and so ensuring + * the stack use is minimal should a context switch interrupt occur. */ + *pxTopOfStack = ( StackType_t ) 0x00; /* R0 */ pxTopOfStack--; *pxTopOfStack = portFLAGS_INT_ENABLED; pxTopOfStack--; /* Next place the address of the hardware stack. This is required so - the AVR stack pointer can be restored to point to the hardware stack. */ + * the AVR stack pointer can be restored to point to the hardware stack. */ pxTopOfHardwareStack -= portBYTES_USED_BY_RETURN_ADDRESS; usAddress = ( uint16_t ) pxTopOfHardwareStack; @@ -153,37 +155,36 @@ StackType_t *pxTopOfHardwareStack; - /* Now the remaining registers. */ - *pxTopOfStack = ( StackType_t ) 0x01; /* R1 */ + *pxTopOfStack = ( StackType_t ) 0x01; /* R1 */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x02; /* R2 */ + *pxTopOfStack = ( StackType_t ) 0x02; /* R2 */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x03; /* R3 */ + *pxTopOfStack = ( StackType_t ) 0x03; /* R3 */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x04; /* R4 */ + *pxTopOfStack = ( StackType_t ) 0x04; /* R4 */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x05; /* R5 */ + *pxTopOfStack = ( StackType_t ) 0x05; /* R5 */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x06; /* R6 */ + *pxTopOfStack = ( StackType_t ) 0x06; /* R6 */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x07; /* R7 */ + *pxTopOfStack = ( StackType_t ) 0x07; /* R7 */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x08; /* R8 */ + *pxTopOfStack = ( StackType_t ) 0x08; /* R8 */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x09; /* R9 */ + *pxTopOfStack = ( StackType_t ) 0x09; /* R9 */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x10; /* R10 */ + *pxTopOfStack = ( StackType_t ) 0x10; /* R10 */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x11; /* R11 */ + *pxTopOfStack = ( StackType_t ) 0x11; /* R11 */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x12; /* R12 */ + *pxTopOfStack = ( StackType_t ) 0x12; /* R12 */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x13; /* R13 */ + *pxTopOfStack = ( StackType_t ) 0x13; /* R13 */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x14; /* R14 */ + *pxTopOfStack = ( StackType_t ) 0x14; /* R14 */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x15; /* R15 */ + *pxTopOfStack = ( StackType_t ) 0x15; /* R15 */ pxTopOfStack--; /* Place the parameter on the stack in the expected location. */ @@ -195,36 +196,36 @@ StackType_t *pxTopOfHardwareStack; *pxTopOfStack = ( StackType_t ) ( usAddress & ( uint16_t ) 0x00ff ); pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x18; /* R18 */ + *pxTopOfStack = ( StackType_t ) 0x18; /* R18 */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x19; /* R19 */ + *pxTopOfStack = ( StackType_t ) 0x19; /* R19 */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x20; /* R20 */ + *pxTopOfStack = ( StackType_t ) 0x20; /* R20 */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x21; /* R21 */ + *pxTopOfStack = ( StackType_t ) 0x21; /* R21 */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x22; /* R22 */ + *pxTopOfStack = ( StackType_t ) 0x22; /* R22 */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x23; /* R23 */ + *pxTopOfStack = ( StackType_t ) 0x23; /* R23 */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x24; /* R24 */ + *pxTopOfStack = ( StackType_t ) 0x24; /* R24 */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x25; /* R25 */ + *pxTopOfStack = ( StackType_t ) 0x25; /* R25 */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x26; /* R26 X */ + *pxTopOfStack = ( StackType_t ) 0x26; /* R26 X */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x27; /* R27 */ + *pxTopOfStack = ( StackType_t ) 0x27; /* R27 */ pxTopOfStack--; /* The Y register is not stored as it is used as the software stack and - gets saved into the task control block. */ + * gets saved into the task control block. */ - *pxTopOfStack = ( StackType_t ) 0x30; /* R30 Z */ + *pxTopOfStack = ( StackType_t ) 0x30; /* R30 Z */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x031; /* R31 */ + *pxTopOfStack = ( StackType_t ) 0x031; /* R31 */ pxTopOfStack--; - *pxTopOfStack = portNO_CRITICAL_NESTING; /* Critical nesting is zero when the task starts. */ + *pxTopOfStack = portNO_CRITICAL_NESTING; /* Critical nesting is zero when the task starts. */ /*lint +e950 +e611 +e923 */ @@ -238,8 +239,8 @@ BaseType_t xPortStartScheduler( void ) prvSetupTimerInterrupt(); /* Restore the context of the first task that is going to run. - Normally we would just call portRESTORE_CONTEXT() here, but as the IAR - compiler does not fully support inline assembler we have to make a call.*/ + * Normally we would just call portRESTORE_CONTEXT() here, but as the IAR + * compiler does not fully support inline assembler we have to make a call.*/ vPortStart(); /* Should not get here! */ @@ -250,7 +251,7 @@ BaseType_t xPortStartScheduler( void ) void vPortEndScheduler( void ) { /* It is unlikely that the AVR port will get stopped. If required simply - disable the tick interrupt here. */ + * disable the tick interrupt here. */ } /*-----------------------------------------------------------*/ @@ -259,11 +260,11 @@ void vPortEndScheduler( void ) */ static void prvSetupTimerInterrupt( void ) { -uint32_t ulCompareMatch; -uint8_t ucHighByte, ucLowByte; + uint32_t ulCompareMatch; + uint8_t ucHighByte, ucLowByte; /* Using 16bit timer 1 to generate the tick. Correct fuses must be - selected for the configCPU_CLOCK_HZ clock. */ + * selected for the configCPU_CLOCK_HZ clock. */ ulCompareMatch = configCPU_CLOCK_HZ / configTICK_RATE_HZ; @@ -274,7 +275,7 @@ uint8_t ucHighByte, ucLowByte; ulCompareMatch -= ( uint32_t ) 1; /* Setup compare match value for compare match A. Interrupts are disabled - before this is called so we need not worry here. */ + * before this is called so we need not worry here. */ ucLowByte = ( uint8_t ) ( ulCompareMatch & ( uint32_t ) 0xff ); ulCompareMatch >>= 8; ucHighByte = ( uint8_t ) ( ulCompareMatch & ( uint32_t ) 0xff ); @@ -286,39 +287,39 @@ uint8_t ucHighByte, ucLowByte; TCCR1B = ucLowByte; /* Enable the interrupt - this is okay as interrupt are currently globally - disabled. */ + * disabled. */ TIMSK |= portCOMPARE_MATCH_A_INTERRUPT_ENABLE; } /*-----------------------------------------------------------*/ #if configUSE_PREEMPTION == 1 - /* - * Tick ISR for preemptive scheduler. We can use a __task attribute as - * the context is saved at the start of vPortYieldFromTick(). The tick - * count is incremented after the context is saved. - */ +/* + * Tick ISR for preemptive scheduler. We can use a __task attribute as + * the context is saved at the start of vPortYieldFromTick(). The tick + * count is incremented after the context is saved. + */ __task void SIG_OUTPUT_COMPARE1A( void ) { vPortYieldFromTick(); - asm( "reti" ); + asm ( "reti" ); } #else - /* - * Tick ISR for the cooperative scheduler. All this does is increment the - * tick count. We don't need to switch context, this can only be done by - * manual calls to taskYIELD(); - * - * THE INTERRUPT VECTOR IS POPULATED IN portmacro.s90. DO NOT INSTALL - * IT HERE USING THE USUAL PRAGMA. - */ +/* + * Tick ISR for the cooperative scheduler. All this does is increment the + * tick count. We don't need to switch context, this can only be done by + * manual calls to taskYIELD(); + * + * THE INTERRUPT VECTOR IS POPULATED IN portmacro.s90. DO NOT INSTALL + * IT HERE USING THE USUAL PRAGMA. + */ __interrupt void SIG_OUTPUT_COMPARE1A( void ) { xTaskIncrementTick(); } -#endif +#endif /* if configUSE_PREEMPTION == 1 */ /*-----------------------------------------------------------*/ void vPortEnterCritical( void ) @@ -331,6 +332,7 @@ void vPortEnterCritical( void ) void vPortExitCritical( void ) { uxCriticalNesting--; + if( uxCriticalNesting == portNO_CRITICAL_NESTING ) { portENABLE_INTERRUPTS(); diff --git a/Source/portable/IAR/ATMega323/portmacro.h b/Source/portable/IAR/ATMega323/portmacro.h index 2bbd50042..341c27577 100644 --- a/Source/portable/IAR/ATMega323/portmacro.h +++ b/Source/portable/IAR/ATMega323/portmacro.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -27,11 +27,11 @@ */ /* -Changes from V1.2.3 - - + portCPU_CLOSK_HZ definition changed to 8MHz base 10, previously it - base 16. -*/ + * Changes from V1.2.3 + * + + portCPU_CLOCK_HZ definition changed to 8MHz base 10, previously it + + base 16. + */ #ifndef PORTMACRO_H #define PORTMACRO_H @@ -53,25 +53,25 @@ Changes from V1.2.3 */ /* Type definitions. */ -#define portCHAR char -#define portFLOAT float -#define portDOUBLE double -#define portLONG long -#define portSHORT int -#define portSTACK_TYPE uint8_t -#define portBASE_TYPE char -#define portPOINTER_SIZE_TYPE uint16_t - -typedef portSTACK_TYPE StackType_t; -typedef signed char BaseType_t; -typedef unsigned char UBaseType_t; - -#if( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS ) - typedef uint16_t TickType_t; - #define portMAX_DELAY ( TickType_t ) 0xffff +#define portCHAR char +#define portFLOAT float +#define portDOUBLE double +#define portLONG long +#define portSHORT int +#define portSTACK_TYPE uint8_t +#define portBASE_TYPE char +#define portPOINTER_SIZE_TYPE uint16_t + +typedef portSTACK_TYPE StackType_t; +typedef signed char BaseType_t; +typedef unsigned char UBaseType_t; + +#if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS ) + typedef uint16_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffff #elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS ) - typedef uint32_t TickType_t; - #define portMAX_DELAY ( TickType_t ) ( 0xFFFFFFFFUL ) + typedef uint32_t TickType_t; + #define portMAX_DELAY ( TickType_t ) ( 0xFFFFFFFFUL ) #else #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width. #endif @@ -81,32 +81,32 @@ typedef unsigned char UBaseType_t; /* Critical section management. */ extern void vPortEnterCritical( void ); extern void vPortExitCritical( void ); -#define portENTER_CRITICAL() vPortEnterCritical() -#define portEXIT_CRITICAL() vPortExitCritical() +#define portENTER_CRITICAL() vPortEnterCritical() +#define portEXIT_CRITICAL() vPortExitCritical() -#define portDISABLE_INTERRUPTS() asm( "cli" ) -#define portENABLE_INTERRUPTS() asm( "sei" ) +#define portDISABLE_INTERRUPTS() asm ( "cli" ) +#define portENABLE_INTERRUPTS() asm ( "sei" ) /*-----------------------------------------------------------*/ /* Architecture specifics. */ -#define portSTACK_GROWTH ( -1 ) -#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) -#define portBYTE_ALIGNMENT 1 -#define portNOP() asm( "nop" ) +#define portSTACK_GROWTH ( -1 ) +#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) +#define portBYTE_ALIGNMENT 1 +#define portNOP() asm ( "nop" ) /*-----------------------------------------------------------*/ /* Kernel utilities. */ void vPortYield( void ); -#define portYIELD() vPortYield() +#define portYIELD() vPortYield() #ifdef IAR_MEGA_AVR - #define outb( PORT, VALUE ) PORT = VALUE + #define outb( PORT, VALUE ) PORT = VALUE #endif /*-----------------------------------------------------------*/ /* Task function macros as described on the FreeRTOS.org WEB site. */ -#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters ) -#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters ) +#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters ) +#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters ) /* *INDENT-OFF* */ #ifdef __cplusplus diff --git a/Source/portable/IAR/ATMega323/portmacro.s90 b/Source/portable/IAR/ATMega323/portmacro.s90 index 631b9afe8..644b22323 100644 --- a/Source/portable/IAR/ATMega323/portmacro.s90 +++ b/Source/portable/IAR/ATMega323/portmacro.s90 @@ -1,5 +1,5 @@ ;/* -; * FreeRTOS Kernel V10.6.2 +; * FreeRTOS Kernel V11.0.1 ; * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. ; * ; * SPDX-License-Identifier: MIT diff --git a/Source/portable/IAR/AVR32_UC3/exception.s82 b/Source/portable/IAR/AVR32_UC3/exception.s82 index d884fae49..1806a6560 100644 --- a/Source/portable/IAR/AVR32_UC3/exception.s82 +++ b/Source/portable/IAR/AVR32_UC3/exception.s82 @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT AND BSD-3-Clause diff --git a/Source/portable/IAR/AVR32_UC3/port.c b/Source/portable/IAR/AVR32_UC3/port.c index 805d7ce71..6a4932751 100644 --- a/Source/portable/IAR/AVR32_UC3/port.c +++ b/Source/portable/IAR/AVR32_UC3/port.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT AND BSD-3-Clause @@ -27,6 +27,7 @@ */ /*This file has been prepared for Doxygen automatic documentation generation.*/ + /*! \file ********************************************************************* * * \brief FreeRTOS port source for AVR32 UC3. @@ -82,20 +83,20 @@ #include "usart.h" #endif -#if( configTICK_USE_TC==1 ) +#if ( configTICK_USE_TC == 1 ) #include "tc.h" #endif /* Constants required to setup the task context. */ -#define portINITIAL_SR ( ( StackType_t ) 0x00400000 ) /* AVR32 : [M2:M0]=001 I1M=0 I0M=0, GM=0 */ -#define portINSTRUCTION_SIZE ( ( StackType_t ) 0 ) +#define portINITIAL_SR ( ( StackType_t ) 0x00400000 ) /* AVR32 : [M2:M0]=001 I1M=0 I0M=0, GM=0 */ +#define portINSTRUCTION_SIZE ( ( StackType_t ) 0 ) /* Each task maintains its own critical nesting variable. */ -#define portNO_CRITICAL_NESTING ( ( uint32_t ) 0 ) +#define portNO_CRITICAL_NESTING ( ( uint32_t ) 0 ) volatile uint32_t ulCriticalNesting = 9999UL; -#if( configTICK_USE_TC==0 ) +#if ( configTICK_USE_TC == 0 ) static void prvScheduleNextTick( void ); #else static void prvClearTcInt( void ); @@ -110,11 +111,11 @@ static void prvSetupTimerInterrupt( void ); * Low-level initialization routine called during startup, before the main * function. */ -int __low_level_init(void) +int __low_level_init( void ) { #if configHEAP_INIT - #pragma segment = "HEAP" - BaseType_t *pxMem; + #pragma segment = "HEAP" + BaseType_t * pxMem; #endif /* Enable exceptions. */ @@ -144,21 +145,21 @@ int __low_level_init(void) static const usart_options_t DBG_USART_OPTIONS = { - .baudrate = configDBG_USART_BAUDRATE, - .charlength = 8, - .paritytype = USART_NO_PARITY, - .stopbits = USART_1_STOPBIT, + .baudrate = configDBG_USART_BAUDRATE, + .charlength = 8, + .paritytype = USART_NO_PARITY, + .stopbits = USART_1_STOPBIT, .channelmode = USART_NORMAL_CHMODE }; /* Initialize the USART used for the debug trace with the configured parameters. */ - extern volatile avr32_usart_t *volatile stdio_usart_base; + extern volatile avr32_usart_t * volatile stdio_usart_base; stdio_usart_base = configDBG_USART; gpio_enable_module( DBG_USART_GPIO_MAP, - sizeof( DBG_USART_GPIO_MAP ) / sizeof( DBG_USART_GPIO_MAP[0] ) ); - usart_init_rs232(configDBG_USART, &DBG_USART_OPTIONS, configCPU_CLOCK_HZ); + sizeof( DBG_USART_GPIO_MAP ) / sizeof( DBG_USART_GPIO_MAP[ 0 ] ) ); + usart_init_rs232( configDBG_USART, &DBG_USART_OPTIONS, configCPU_CLOCK_HZ ); } - #endif + #endif /* if configDBG */ /* Request initialization of data segments. */ return 1; @@ -166,9 +167,10 @@ int __low_level_init(void) /*-----------------------------------------------------------*/ /* Added as there is no such function in FreeRTOS. */ -void *pvPortRealloc( void *pv, size_t xWantedSize ) +void * pvPortRealloc( void * pv, + size_t xWantedSize ) { -void *pvReturn; + void * pvReturn; vTaskSuspendAll(); { @@ -181,28 +183,30 @@ void *pvReturn; /*-----------------------------------------------------------*/ /* The cooperative scheduler requires a normal IRQ service routine to -simply increment the system tick. */ + * simply increment the system tick. */ + /* The preemptive scheduler is defined as "naked" as the full context is saved -on entry as part of the context switch. */ -#pragma shadow_registers = full // Naked. + * on entry as part of the context switch. */ +#pragma shadow_registers = full /* Naked. */ static void vTick( void ) { /* Save the context of the interrupted task. */ portSAVE_CONTEXT_OS_INT(); - #if( configTICK_USE_TC==1 ) + #if ( configTICK_USE_TC == 1 ) /* Clear the interrupt flag. */ prvClearTcInt(); #else + /* Schedule the COUNT&COMPARE match interrupt in (configCPU_CLOCK_HZ/configTICK_RATE_HZ) - clock cycles from now. */ + * clock cycles from now. */ prvScheduleNextTick(); #endif /* Because FreeRTOS is not supposed to run with nested interrupts, put all OS - calls in a critical section . */ + * calls in a critical section . */ portENTER_CRITICAL(); - xTaskIncrementTick(); + xTaskIncrementTick(); portEXIT_CRITICAL(); /* Restore the context of the "elected task". */ @@ -210,7 +214,7 @@ static void vTick( void ) } /*-----------------------------------------------------------*/ -#pragma shadow_registers = full // Naked. +#pragma shadow_registers = full /* Naked. */ void SCALLYield( void ) { /* Save the context of the interrupted task. */ @@ -221,18 +225,18 @@ void SCALLYield( void ) /*-----------------------------------------------------------*/ /* The code generated by the GCC compiler uses the stack in different ways at -different optimisation levels. The interrupt flags can therefore not always -be saved to the stack. Instead the critical section nesting level is stored -in a variable, which is then saved as part of the stack context. */ + * different optimisation levels. The interrupt flags can therefore not always + * be saved to the stack. Instead the critical section nesting level is stored + * in a variable, which is then saved as part of the stack context. */ #pragma optimize = no_inline void vPortEnterCritical( void ) { /* Disable interrupts */ portDISABLE_INTERRUPTS(); - /* Now interrupts are disabled ulCriticalNesting can be accessed - directly. Increment ulCriticalNesting to keep a count of how many times - portENTER_CRITICAL() has been called. */ + /* Now that interrupts are disabled, ulCriticalNesting can be accessed + * directly. Increment ulCriticalNesting to keep a count of how many times + * portENTER_CRITICAL() has been called. */ ulCriticalNesting++; } /*-----------------------------------------------------------*/ @@ -240,9 +244,10 @@ void vPortEnterCritical( void ) #pragma optimize = no_inline void vPortExitCritical( void ) { - if(ulCriticalNesting > portNO_CRITICAL_NESTING) + if( ulCriticalNesting > portNO_CRITICAL_NESTING ) { ulCriticalNesting--; + if( ulCriticalNesting == portNO_CRITICAL_NESTING ) { /* Enable all interrupt/exception. */ @@ -258,30 +263,32 @@ void vPortExitCritical( void ) * * See header file for description. */ -StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters ) +StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, + TaskFunction_t pxCode, + void * pvParameters ) { /* Setup the initial stack of the task. The stack is set exactly as - expected by the portRESTORE_CONTEXT() macro. */ + * expected by the portRESTORE_CONTEXT() macro. */ /* When the task starts, it will expect to find the function parameter in R12. */ pxTopOfStack--; - *pxTopOfStack-- = ( StackType_t ) 0x08080808; /* R8 */ - *pxTopOfStack-- = ( StackType_t ) 0x09090909; /* R9 */ - *pxTopOfStack-- = ( StackType_t ) 0x0A0A0A0A; /* R10 */ - *pxTopOfStack-- = ( StackType_t ) 0x0B0B0B0B; /* R11 */ - *pxTopOfStack-- = ( StackType_t ) pvParameters; /* R12 */ - *pxTopOfStack-- = ( StackType_t ) 0xDEADBEEF; /* R14/LR */ + *pxTopOfStack-- = ( StackType_t ) 0x08080808; /* R8 */ + *pxTopOfStack-- = ( StackType_t ) 0x09090909; /* R9 */ + *pxTopOfStack-- = ( StackType_t ) 0x0A0A0A0A; /* R10 */ + *pxTopOfStack-- = ( StackType_t ) 0x0B0B0B0B; /* R11 */ + *pxTopOfStack-- = ( StackType_t ) pvParameters; /* R12 */ + *pxTopOfStack-- = ( StackType_t ) 0xDEADBEEF; /* R14/LR */ *pxTopOfStack-- = ( StackType_t ) pxCode + portINSTRUCTION_SIZE; /* R15/PC */ - *pxTopOfStack-- = ( StackType_t ) portINITIAL_SR; /* SR */ - *pxTopOfStack-- = ( StackType_t ) 0xFF0000FF; /* R0 */ - *pxTopOfStack-- = ( StackType_t ) 0x01010101; /* R1 */ - *pxTopOfStack-- = ( StackType_t ) 0x02020202; /* R2 */ - *pxTopOfStack-- = ( StackType_t ) 0x03030303; /* R3 */ - *pxTopOfStack-- = ( StackType_t ) 0x04040404; /* R4 */ - *pxTopOfStack-- = ( StackType_t ) 0x05050505; /* R5 */ - *pxTopOfStack-- = ( StackType_t ) 0x06060606; /* R6 */ - *pxTopOfStack-- = ( StackType_t ) 0x07070707; /* R7 */ - *pxTopOfStack = ( StackType_t ) portNO_CRITICAL_NESTING; /* ulCriticalNesting */ + *pxTopOfStack-- = ( StackType_t ) portINITIAL_SR; /* SR */ + *pxTopOfStack-- = ( StackType_t ) 0xFF0000FF; /* R0 */ + *pxTopOfStack-- = ( StackType_t ) 0x01010101; /* R1 */ + *pxTopOfStack-- = ( StackType_t ) 0x02020202; /* R2 */ + *pxTopOfStack-- = ( StackType_t ) 0x03030303; /* R3 */ + *pxTopOfStack-- = ( StackType_t ) 0x04040404; /* R4 */ + *pxTopOfStack-- = ( StackType_t ) 0x05050505; /* R5 */ + *pxTopOfStack-- = ( StackType_t ) 0x06060606; /* R6 */ + *pxTopOfStack-- = ( StackType_t ) 0x07070707; /* R7 */ + *pxTopOfStack = ( StackType_t ) portNO_CRITICAL_NESTING; /* ulCriticalNesting */ return pxTopOfStack; } @@ -290,7 +297,7 @@ StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t px BaseType_t xPortStartScheduler( void ) { /* Start the timer that generates the tick ISR. Interrupts are disabled - here already. */ + * here already. */ prvSetupTimerInterrupt(); /* Start the first task. */ @@ -304,132 +311,136 @@ BaseType_t xPortStartScheduler( void ) void vPortEndScheduler( void ) { /* It is unlikely that the AVR32 port will require this function as there - is nothing to return to. */ + * is nothing to return to. */ } /*-----------------------------------------------------------*/ /* Schedule the COUNT&COMPARE match interrupt in (configCPU_CLOCK_HZ/configTICK_RATE_HZ) -clock cycles from now. */ -#if( configTICK_USE_TC==0 ) - static void prvScheduleFirstTick(void) + * clock cycles from now. */ +#if ( configTICK_USE_TC == 0 ) + static void prvScheduleFirstTick( void ) { uint32_t lCycles; - lCycles = Get_system_register(AVR32_COUNT); - lCycles += (configCPU_CLOCK_HZ/configTICK_RATE_HZ); - // If lCycles ends up to be 0, make it 1 so that the COMPARE and exception - // generation feature does not get disabled. - if(0 == lCycles) + lCycles = Get_system_register( AVR32_COUNT ); + lCycles += ( configCPU_CLOCK_HZ / configTICK_RATE_HZ ); + + /* If lCycles ends up to be 0, make it 1 so that the COMPARE and exception */ + /* generation feature does not get disabled. */ + if( 0 == lCycles ) { lCycles++; } - Set_system_register(AVR32_COMPARE, lCycles); + + Set_system_register( AVR32_COMPARE, lCycles ); } #pragma optimize = no_inline - static void prvScheduleNextTick(void) + static void prvScheduleNextTick( void ) { uint32_t lCycles, lCount; - lCycles = Get_system_register(AVR32_COMPARE); - lCycles += (configCPU_CLOCK_HZ/configTICK_RATE_HZ); - // If lCycles ends up to be 0, make it 1 so that the COMPARE and exception - // generation feature does not get disabled. - if(0 == lCycles) + lCycles = Get_system_register( AVR32_COMPARE ); + lCycles += ( configCPU_CLOCK_HZ / configTICK_RATE_HZ ); + + /* If lCycles ends up to be 0, make it 1 so that the COMPARE and exception */ + /* generation feature does not get disabled. */ + if( 0 == lCycles ) { lCycles++; } - lCount = Get_system_register(AVR32_COUNT); + + lCount = Get_system_register( AVR32_COUNT ); + if( lCycles < lCount ) - { // We missed a tick, recover for the next. - lCycles += (configCPU_CLOCK_HZ/configTICK_RATE_HZ); + { /* We missed a tick, recover for the next. */ + lCycles += ( configCPU_CLOCK_HZ / configTICK_RATE_HZ ); } - Set_system_register(AVR32_COMPARE, lCycles); + + Set_system_register( AVR32_COMPARE, lCycles ); } -#else +#else /* if ( configTICK_USE_TC == 0 ) */ #pragma optimize = no_inline - static void prvClearTcInt(void) + static void prvClearTcInt( void ) { - AVR32_TC.channel[configTICK_TC_CHANNEL].sr; + AVR32_TC.channel[ configTICK_TC_CHANNEL ].sr; } -#endif +#endif /* if ( configTICK_USE_TC == 0 ) */ /*-----------------------------------------------------------*/ /* Setup the timer to generate the tick interrupts. */ -static void prvSetupTimerInterrupt(void) +static void prvSetupTimerInterrupt( void ) { - #if( configTICK_USE_TC==1 ) - - volatile avr32_tc_t *tc = &AVR32_TC; + #if ( configTICK_USE_TC == 1 ) + volatile avr32_tc_t * tc = &AVR32_TC; - // Options for waveform genration. + /* Options for waveform genration. */ tc_waveform_opt_t waveform_opt = { - .channel = configTICK_TC_CHANNEL, /* Channel selection. */ - - .bswtrg = TC_EVT_EFFECT_NOOP, /* Software trigger effect on TIOB. */ - .beevt = TC_EVT_EFFECT_NOOP, /* External event effect on TIOB. */ - .bcpc = TC_EVT_EFFECT_NOOP, /* RC compare effect on TIOB. */ - .bcpb = TC_EVT_EFFECT_NOOP, /* RB compare effect on TIOB. */ - - .aswtrg = TC_EVT_EFFECT_NOOP, /* Software trigger effect on TIOA. */ - .aeevt = TC_EVT_EFFECT_NOOP, /* External event effect on TIOA. */ - .acpc = TC_EVT_EFFECT_NOOP, /* RC compare effect on TIOA: toggle. */ - .acpa = TC_EVT_EFFECT_NOOP, /* RA compare effect on TIOA: toggle (other possibilities are none, set and clear). */ - - .wavsel = TC_WAVEFORM_SEL_UP_MODE_RC_TRIGGER,/* Waveform selection: Up mode without automatic trigger on RC compare. */ - .enetrg = FALSE, /* External event trigger enable. */ - .eevt = 0, /* External event selection. */ - .eevtedg = TC_SEL_NO_EDGE, /* External event edge selection. */ - .cpcdis = FALSE, /* Counter disable when RC compare. */ - .cpcstop = FALSE, /* Counter clock stopped with RC compare. */ - - .burst = FALSE, /* Burst signal selection. */ - .clki = FALSE, /* Clock inversion. */ - .tcclks = TC_CLOCK_SOURCE_TC2 /* Internal source clock 2. */ + .channel = configTICK_TC_CHANNEL, /* Channel selection. */ + + .bswtrg = TC_EVT_EFFECT_NOOP, /* Software trigger effect on TIOB. */ + .beevt = TC_EVT_EFFECT_NOOP, /* External event effect on TIOB. */ + .bcpc = TC_EVT_EFFECT_NOOP, /* RC compare effect on TIOB. */ + .bcpb = TC_EVT_EFFECT_NOOP, /* RB compare effect on TIOB. */ + + .aswtrg = TC_EVT_EFFECT_NOOP, /* Software trigger effect on TIOA. */ + .aeevt = TC_EVT_EFFECT_NOOP, /* External event effect on TIOA. */ + .acpc = TC_EVT_EFFECT_NOOP, /* RC compare effect on TIOA: toggle. */ + .acpa = TC_EVT_EFFECT_NOOP, /* RA compare effect on TIOA: toggle (other possibilities are none, set and clear). */ + + .wavsel = TC_WAVEFORM_SEL_UP_MODE_RC_TRIGGER, /* Waveform selection: Up mode without automatic trigger on RC compare. */ + .enetrg = FALSE, /* External event trigger enable. */ + .eevt = 0, /* External event selection. */ + .eevtedg = TC_SEL_NO_EDGE, /* External event edge selection. */ + .cpcdis = FALSE, /* Counter disable when RC compare. */ + .cpcstop = FALSE, /* Counter clock stopped with RC compare. */ + + .burst = FALSE, /* Burst signal selection. */ + .clki = FALSE, /* Clock inversion. */ + .tcclks = TC_CLOCK_SOURCE_TC2 /* Internal source clock 2. */ }; tc_interrupt_t tc_interrupt = { - .etrgs=0, - .ldrbs=0, - .ldras=0, - .cpcs =1, - .cpbs =0, - .cpas =0, - .lovrs=0, - .covfs=0, + .etrgs = 0, + .ldrbs = 0, + .ldras = 0, + .cpcs = 1, + .cpbs = 0, + .cpas = 0, + .lovrs = 0, + .covfs = 0, }; - - #endif + #endif /* if ( configTICK_USE_TC == 1 ) */ /* Disable all interrupt/exception. */ portDISABLE_INTERRUPTS(); /* Register the compare interrupt handler to the interrupt controller and - enable the compare interrupt. */ + * enable the compare interrupt. */ - #if( configTICK_USE_TC==1 ) + #if ( configTICK_USE_TC == 1 ) { - INTC_register_interrupt((__int_handler)&vTick, configTICK_TC_IRQ, INT0); + INTC_register_interrupt( ( __int_handler ) & vTick, configTICK_TC_IRQ, INT0 ); /* Initialize the timer/counter. */ - tc_init_waveform(tc, &waveform_opt); + tc_init_waveform( tc, &waveform_opt ); /* Set the compare triggers. - Remember TC counter is 16-bits, so counting second is not possible! - That's why we configure it to count ms. */ - tc_write_rc( tc, configTICK_TC_CHANNEL, ( configPBA_CLOCK_HZ / 4) / configTICK_RATE_HZ ); + * Remember TC counter is 16-bits, so counting second is not possible! + * That's why we configure it to count ms. */ + tc_write_rc( tc, configTICK_TC_CHANNEL, ( configPBA_CLOCK_HZ / 4 ) / configTICK_RATE_HZ ); tc_configure_interrupts( tc, configTICK_TC_CHANNEL, &tc_interrupt ); /* Start the timer/counter. */ - tc_start(tc, configTICK_TC_CHANNEL); + tc_start( tc, configTICK_TC_CHANNEL ); } - #else + #else /* if ( configTICK_USE_TC == 1 ) */ { - INTC_register_interrupt((__int_handler)&vTick, AVR32_CORE_COMPARE_IRQ, INT0); + INTC_register_interrupt( ( __int_handler ) & vTick, AVR32_CORE_COMPARE_IRQ, INT0 ); prvScheduleFirstTick(); } - #endif + #endif /* if ( configTICK_USE_TC == 1 ) */ } diff --git a/Source/portable/IAR/AVR32_UC3/portmacro.h b/Source/portable/IAR/AVR32_UC3/portmacro.h index ad5b9d1a3..6cf1a1420 100644 --- a/Source/portable/IAR/AVR32_UC3/portmacro.h +++ b/Source/portable/IAR/AVR32_UC3/portmacro.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT AND BSD-3-Clause @@ -27,6 +27,7 @@ */ /*This file has been prepared for Doxygen automatic documentation generation.*/ + /*! \file ********************************************************************* * * \brief FreeRTOS port header for AVR32 UC3. @@ -95,31 +96,31 @@ /* Type definitions. */ -#define portCHAR char -#define portFLOAT float -#define portDOUBLE double -#define portLONG long -#define portSHORT short -#define portSTACK_TYPE uint32_t -#define portBASE_TYPE long +#define portCHAR char +#define portFLOAT float +#define portDOUBLE double +#define portLONG long +#define portSHORT short +#define portSTACK_TYPE uint32_t +#define portBASE_TYPE long -typedef portSTACK_TYPE StackType_t; -typedef long BaseType_t; -typedef unsigned long UBaseType_t; +typedef portSTACK_TYPE StackType_t; +typedef long BaseType_t; +typedef unsigned long UBaseType_t; -#define TASK_DELAY_MS(x) ( (x) /portTICK_PERIOD_MS ) -#define TASK_DELAY_S(x) ( (x)*1000 /portTICK_PERIOD_MS ) -#define TASK_DELAY_MIN(x) ( (x)*60*1000/portTICK_PERIOD_MS ) +#define TASK_DELAY_MS( x ) ( ( x ) / portTICK_PERIOD_MS ) +#define TASK_DELAY_S( x ) ( ( x ) * 1000 / portTICK_PERIOD_MS ) +#define TASK_DELAY_MIN( x ) ( ( x ) * 60 * 1000 / portTICK_PERIOD_MS ) -#define configTICK_TC_IRQ ATPASTE2(AVR32_TC_IRQ, configTICK_TC_CHANNEL) +#define configTICK_TC_IRQ ATPASTE2( AVR32_TC_IRQ, configTICK_TC_CHANNEL ) -#if( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS ) - typedef uint16_t TickType_t; - #define portMAX_DELAY ( TickType_t ) 0xffff +#if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS ) + typedef uint16_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffff #elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS ) - typedef uint32_t TickType_t; - #define portMAX_DELAY ( TickType_t ) ( 0xFFFFFFFFUL ) + typedef uint32_t TickType_t; + #define portMAX_DELAY ( TickType_t ) ( 0xFFFFFFFFUL ) #else #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width. #endif @@ -127,23 +128,23 @@ typedef unsigned long UBaseType_t; /* Architecture specifics. */ #define portSTACK_GROWTH ( -1 ) -#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) -#define portBYTE_ALIGNMENT 4 -#define portNOP() {__asm__ __volatile__ ("nop");} +#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) +#define portBYTE_ALIGNMENT 4 +#define portNOP() { __asm__ __volatile__ ( "nop" ); } /*-----------------------------------------------------------*/ /*-----------------------------------------------------------*/ /* INTC-specific. */ -#define DISABLE_ALL_EXCEPTIONS() Disable_global_exception() -#define ENABLE_ALL_EXCEPTIONS() Enable_global_exception() +#define DISABLE_ALL_EXCEPTIONS() Disable_global_exception() +#define ENABLE_ALL_EXCEPTIONS() Enable_global_exception() -#define DISABLE_ALL_INTERRUPTS() Disable_global_interrupt() -#define ENABLE_ALL_INTERRUPTS() Enable_global_interrupt() +#define DISABLE_ALL_INTERRUPTS() Disable_global_interrupt() +#define ENABLE_ALL_INTERRUPTS() Enable_global_interrupt() -#define DISABLE_INT_LEVEL(int_lev) Disable_interrupt_level(int_lev) -#define ENABLE_INT_LEVEL(int_lev) Enable_interrupt_level(int_lev) +#define DISABLE_INT_LEVEL( int_lev ) Disable_interrupt_level( int_lev ) +#define ENABLE_INT_LEVEL( int_lev ) Enable_interrupt_level( int_lev ) /* @@ -160,31 +161,32 @@ typedef unsigned long UBaseType_t; * which is interrupt-unsafe with the current __malloc_lock and __malloc_unlock. */ #if configDBG - #define portDBG_TRACE(...) \ - { \ - fputs(__FILE__ ":" ASTRINGZ(__LINE__) ": ", stdout); \ - printf(__VA_ARGS__); \ - fputs("\r\n", stdout); \ + #define portDBG_TRACE( ... ) \ + { \ + fputs( __FILE__ ":" ASTRINGZ( __LINE__ ) ": ", stdout ); \ + printf( __VA_ARGS__ ); \ + fputs( "\r\n", stdout ); \ } #else - #define portDBG_TRACE(...) + #define portDBG_TRACE( ... ) #endif /* Critical section management. */ -#define portDISABLE_INTERRUPTS() DISABLE_ALL_INTERRUPTS() -#define portENABLE_INTERRUPTS() ENABLE_ALL_INTERRUPTS() +#define portDISABLE_INTERRUPTS() DISABLE_ALL_INTERRUPTS() +#define portENABLE_INTERRUPTS() ENABLE_ALL_INTERRUPTS() extern void vPortEnterCritical( void ); extern void vPortExitCritical( void ); -#define portENTER_CRITICAL() vPortEnterCritical(); -#define portEXIT_CRITICAL() vPortExitCritical(); +#define portENTER_CRITICAL() vPortEnterCritical(); +#define portEXIT_CRITICAL() vPortExitCritical(); /* Added as there is no such function in FreeRTOS. */ -extern void *pvPortRealloc( void *pv, size_t xSize ); +extern void * pvPortRealloc( void * pv, + size_t xSize ); /*-----------------------------------------------------------*/ @@ -193,44 +195,44 @@ extern void *pvPortRealloc( void *pv, size_t xSize ); /* * Restore Context for cases other than INTi. */ -#define portRESTORE_CONTEXT() \ -{ \ - extern volatile uint32_t ulCriticalNesting; \ - extern volatile void *volatile pxCurrentTCB; \ - \ - __asm__ __volatile__ ( \ - /* Set SP to point to new stack */ \ - "mov r8, LWRD("ASTRINGZ(pxCurrentTCB)") \n\t"\ - "orh r8, HWRD("ASTRINGZ(pxCurrentTCB)") \n\t"\ - "ld.w r0, r8[0] \n\t"\ - "ld.w sp, r0[0] \n\t"\ - \ - /* Restore ulCriticalNesting variable */ \ - "ld.w r0, sp++ \n\t"\ - "mov r8, LWRD("ASTRINGZ(ulCriticalNesting)") \n\t"\ - "orh r8, HWRD("ASTRINGZ(ulCriticalNesting)") \n\t"\ - "st.w r8[0], r0 \n\t"\ - \ - /* Restore R0..R7 */ \ - "ldm sp++, r0-r7 \n\t"\ - /* R0-R7 should not be used below this line */ \ - /* Skip PC and SR (will do it at the end) */ \ - "sub sp, -2*4 \n\t"\ - /* Restore R8..R12 and LR */ \ - "ldm sp++, r8-r12, lr \n\t"\ - /* Restore SR */ \ - "ld.w r0, sp[-8*4] \n\t" /* R0 is modified, is restored later. */\ - "mtsr "ASTRINGZ(AVR32_SR)", r0 \n\t"\ - /* Restore r0 */ \ - "ld.w r0, sp[-9*4] \n\t"\ - /* Restore PC */ \ - "ld.w pc, sp[-7*4]" /* Get PC from stack - PC is the 7th register saved */ \ - ); \ - \ - /* Force import of global symbols from assembly */ \ - ulCriticalNesting; \ - pxCurrentTCB; \ -} +#define portRESTORE_CONTEXT() \ + { \ + extern volatile uint32_t ulCriticalNesting; \ + extern volatile void * volatile pxCurrentTCB; \ + \ + __asm__ __volatile__ ( \ + /* Set SP to point to new stack */ \ + "mov r8, LWRD("ASTRINGZ ( pxCurrentTCB ) ") \n\t" \ + "orh r8, HWRD("ASTRINGZ ( pxCurrentTCB ) ") \n\t" \ + "ld.w r0, r8[0] \n\t" \ + "ld.w sp, r0[0] \n\t" \ + \ + /* Restore ulCriticalNesting variable */ \ + "ld.w r0, sp++ \n\t" \ + "mov r8, LWRD("ASTRINGZ ( ulCriticalNesting ) ") \n\t" \ + "orh r8, HWRD("ASTRINGZ ( ulCriticalNesting ) ") \n\t" \ + "st.w r8[0], r0 \n\t" \ + \ + /* Restore R0..R7 */ \ + "ldm sp++, r0-r7 \n\t" \ + /* R0-R7 should not be used below this line */ \ + /* Skip PC and SR (will do it at the end) */ \ + "sub sp, -2*4 \n\t" \ + /* Restore R8..R12 and LR */ \ + "ldm sp++, r8-r12, lr \n\t" \ + /* Restore SR */ \ + "ld.w r0, sp[-8*4] \n\t" /* R0 is modified, is restored later. */ \ + "mtsr "ASTRINGZ ( AVR32_SR ) ", r0 \n\t" \ + /* Restore r0 */ \ + "ld.w r0, sp[-9*4] \n\t" \ + /* Restore PC */ \ + "ld.w pc, sp[-7*4]" /* Get PC from stack - PC is the 7th register saved */ \ + ); \ + \ + /* Force import of global symbols from assembly */ \ + ulCriticalNesting; \ + pxCurrentTCB; \ + } /* @@ -241,25 +243,25 @@ extern void *pvPortRealloc( void *pv, size_t xSize ); * are not the same between INT0..3 exceptions and the scall exception. */ -// Task context stack layout: - // R8 (*) - // R9 (*) - // R10 (*) - // R11 (*) - // R12 (*) - // R14/LR (*) - // R15/PC (*) - // SR (*) - // R0 - // R1 - // R2 - // R3 - // R4 - // R5 - // R6 - // R7 - // ulCriticalNesting -// (*) automatically done for INT0..INT3, but not for SCALL +/* Task context stack layout: */ +/* R8 (*) */ +/* R9 (*) */ +/* R10 (*) */ +/* R11 (*) */ +/* R12 (*) */ +/* R14/LR (*) */ +/* R15/PC (*) */ +/* SR (*) */ +/* R0 */ +/* R1 */ +/* R2 */ +/* R3 */ +/* R4 */ +/* R5 */ +/* R6 */ +/* R7 */ +/* ulCriticalNesting */ +/* (*) automatically done for INT0..INT3, but not for SCALL */ /* * The ISR used for the scheduler tick depends on whether the cooperative or @@ -270,139 +272,139 @@ extern void *pvPortRealloc( void *pv, size_t xSize ); /* * portSAVE_CONTEXT_OS_INT() for OS Tick exception. */ -#define portSAVE_CONTEXT_OS_INT() \ -{ \ - /* Save R0..R7 */ \ - __asm__ __volatile__ ("stm --sp, r0-r7"); \ - \ - /* With the cooperative scheduler, as there is no context switch by interrupt, */ \ - /* there is also no context save. */ \ -} + #define portSAVE_CONTEXT_OS_INT() \ + { \ + /* Save R0..R7 */ \ + __asm__ __volatile__ ( "stm --sp, r0-r7" ); \ + \ + /* With the cooperative scheduler, as there is no context switch by interrupt, */ \ + /* there is also no context save. */ \ + } /* * portRESTORE_CONTEXT_OS_INT() for Tick exception. */ -#define portRESTORE_CONTEXT_OS_INT() \ -{ \ - __asm__ __volatile__ ( \ - /* Restore R0..R7 */ \ - "ldm sp++, r0-r7 \n\t"\ - \ - /* With the cooperative scheduler, as there is no context switch by interrupt, */ \ - /* there is also no context restore. */ \ - "rete" \ - ); \ -} + #define portRESTORE_CONTEXT_OS_INT() \ + { \ + __asm__ __volatile__ ( \ + /* Restore R0..R7 */ \ + "ldm sp++, r0-r7 \n\t" \ + \ + /* With the cooperative scheduler, as there is no context switch by interrupt, */ \ + /* there is also no context restore. */ \ + "rete" \ + ); \ + } -#else +#else /* if configUSE_PREEMPTION == 0 */ /* * portSAVE_CONTEXT_OS_INT() for OS Tick exception. */ -#define portSAVE_CONTEXT_OS_INT() \ -{ \ - extern volatile uint32_t ulCriticalNesting; \ - extern volatile void *volatile pxCurrentTCB; \ - \ - /* When we come here */ \ - /* Registers R8..R12, LR, PC and SR had already been pushed to system stack */ \ - \ - __asm__ __volatile__ ( \ - /* Save R0..R7 */ \ - "stm --sp, r0-r7 \n\t"\ - \ - /* Save ulCriticalNesting variable - R0 is overwritten */ \ - "mov r8, LWRD("ASTRINGZ(ulCriticalNesting)") \n\t"\ - "orh r8, HWRD("ASTRINGZ(ulCriticalNesting)") \n\t"\ - "ld.w r0, r8[0] \n\t"\ - "st.w --sp, r0 \n\t"\ - \ - /* Check if INT0 or higher were being handled (case where the OS tick interrupted another */ \ - /* interrupt handler (which was of a higher priority level but decided to lower its priority */ \ - /* level and allow other lower interrupt level to occur). */ \ - /* In this case we don't want to do a task switch because we don't know what the stack */ \ - /* currently looks like (we don't know what the interrupted interrupt handler was doing). */ \ - /* Saving SP in pxCurrentTCB and then later restoring it (thinking restoring the task) */ \ - /* will just be restoring the interrupt handler, no way!!! */ \ - /* So, since we won't do a vTaskSwitchContext(), it's of no use to save SP. */ \ - "ld.w r0, sp[9*4] \n\t" /* Read SR in stack */\ - "bfextu r0, r0, 22, 3 \n\t" /* Extract the mode bits to R0. */\ - "cp.w r0, 1 \n\t" /* Compare the mode bits with supervisor mode(b'001) */\ - "brhi LABEL_INT_SKIP_SAVE_CONTEXT_"ASTRINGZ(__LINE__)" \n\t"\ - \ - /* Store SP in the first member of the structure pointed to by pxCurrentTCB */ \ - /* NOTE: we don't enter a critical section here because all interrupt handlers */ \ - /* MUST perform a SAVE_CONTEXT/RESTORE_CONTEXT in the same way as */ \ - /* portSAVE_CONTEXT_OS_INT/port_RESTORE_CONTEXT_OS_INT if they call OS functions. */ \ - /* => all interrupt handlers must use portENTER_SWITCHING_ISR/portEXIT_SWITCHING_ISR. */ \ - "mov r8, LWRD("ASTRINGZ(pxCurrentTCB)") \n\t"\ - "orh r8, HWRD("ASTRINGZ(pxCurrentTCB)") \n\t"\ - "ld.w r0, r8[0] \n\t"\ - "st.w r0[0], sp \n"\ - \ - "LABEL_INT_SKIP_SAVE_CONTEXT_"ASTRINGZ(__LINE__)":" \ - ); \ -} + #define portSAVE_CONTEXT_OS_INT() \ + { \ + extern volatile uint32_t ulCriticalNesting; \ + extern volatile void * volatile pxCurrentTCB; \ + \ + /* When we come here */ \ + /* Registers R8..R12, LR, PC and SR had already been pushed to system stack */ \ + \ + __asm__ __volatile__ ( \ + /* Save R0..R7 */ \ + "stm --sp, r0-r7 \n\t" \ + \ + /* Save ulCriticalNesting variable - R0 is overwritten */ \ + "mov r8, LWRD("ASTRINGZ ( ulCriticalNesting ) ") \n\t" \ + "orh r8, HWRD("ASTRINGZ ( ulCriticalNesting ) ") \n\t" \ + "ld.w r0, r8[0] \n\t" \ + "st.w --sp, r0 \n\t" \ + \ + /* Check if INT0 or higher were being handled (case where the OS tick interrupted another */ \ + /* interrupt handler (which was of a higher priority level but decided to lower its priority */ \ + /* level and allow other lower interrupt level to occur). */ \ + /* In this case we don't want to do a task switch because we don't know what the stack */ \ + /* currently looks like (we don't know what the interrupted interrupt handler was doing). */ \ + /* Saving SP in pxCurrentTCB and then later restoring it (thinking restoring the task) */ \ + /* will just be restoring the interrupt handler, no way!!! */ \ + /* So, since we won't do a vTaskSwitchContext(), it's of no use to save SP. */ \ + "ld.w r0, sp[9*4] \n\t" /* Read SR in stack */ \ + "bfextu r0, r0, 22, 3 \n\t" /* Extract the mode bits to R0. */ \ + "cp.w r0, 1 \n\t" /* Compare the mode bits with supervisor mode(b'001) */ \ + "brhi LABEL_INT_SKIP_SAVE_CONTEXT_"ASTRINGZ ( __LINE__ ) " \n\t" \ + \ + /* Store SP in the first member of the structure pointed to by pxCurrentTCB */ \ + /* NOTE: we don't enter a critical section here because all interrupt handlers */ \ + /* MUST perform a SAVE_CONTEXT/RESTORE_CONTEXT in the same way as */ \ + /* portSAVE_CONTEXT_OS_INT/port_RESTORE_CONTEXT_OS_INT if they call OS functions. */ \ + /* => all interrupt handlers must use portENTER_SWITCHING_ISR/portEXIT_SWITCHING_ISR. */ \ + "mov r8, LWRD("ASTRINGZ ( pxCurrentTCB ) ") \n\t" \ + "orh r8, HWRD("ASTRINGZ ( pxCurrentTCB ) ") \n\t" \ + "ld.w r0, r8[0] \n\t" \ + "st.w r0[0], sp \n" \ + \ + "LABEL_INT_SKIP_SAVE_CONTEXT_"ASTRINGZ ( __LINE__ ) ":" \ + ); \ + } /* * portRESTORE_CONTEXT_OS_INT() for Tick exception. */ -#define portRESTORE_CONTEXT_OS_INT() \ -{ \ - extern volatile uint32_t ulCriticalNesting; \ - extern volatile void *volatile pxCurrentTCB; \ - \ - /* Check if INT0 or higher were being handled (case where the OS tick interrupted another */ \ - /* interrupt handler (which was of a higher priority level but decided to lower its priority */ \ - /* level and allow other lower interrupt level to occur). */ \ - /* In this case we don't want to do a task switch because we don't know what the stack */ \ - /* currently looks like (we don't know what the interrupted interrupt handler was doing). */ \ - /* Saving SP in pxCurrentTCB and then later restoring it (thinking restoring the task) */ \ - /* will just be restoring the interrupt handler, no way!!! */ \ - __asm__ __volatile__ ( \ - "ld.w r0, sp[9*4] \n\t" /* Read SR in stack */\ - "bfextu r0, r0, 22, 3 \n\t" /* Extract the mode bits to R0. */\ - "cp.w r0, 1 \n\t" /* Compare the mode bits with supervisor mode(b'001) */\ - "brhi LABEL_INT_SKIP_RESTORE_CONTEXT_"ASTRINGZ(__LINE__) \ - ); \ - \ - /* Else */ \ - /* because it is here safe, always call vTaskSwitchContext() since an OS tick occurred. */ \ - /* A critical section has to be used here because vTaskSwitchContext handles FreeRTOS linked lists. */\ - portENTER_CRITICAL(); \ - vTaskSwitchContext(); \ - portEXIT_CRITICAL(); \ - \ - /* Restore all registers */ \ - \ - __asm__ __volatile__ ( \ - /* Set SP to point to new stack */ \ - "mov r8, LWRD("ASTRINGZ(pxCurrentTCB)") \n\t"\ - "orh r8, HWRD("ASTRINGZ(pxCurrentTCB)") \n\t"\ - "ld.w r0, r8[0] \n\t"\ - "ld.w sp, r0[0] \n"\ - \ - "LABEL_INT_SKIP_RESTORE_CONTEXT_"ASTRINGZ(__LINE__)": \n\t"\ - \ - /* Restore ulCriticalNesting variable */ \ - "ld.w r0, sp++ \n\t"\ - "mov r8, LWRD("ASTRINGZ(ulCriticalNesting)") \n\t"\ - "orh r8, HWRD("ASTRINGZ(ulCriticalNesting)") \n\t"\ - "st.w r8[0], r0 \n\t"\ - \ - /* Restore R0..R7 */ \ - "ldm sp++, r0-r7 \n\t"\ - \ - /* Now, the stack should be R8..R12, LR, PC and SR */ \ - "rete" \ - ); \ - \ - /* Force import of global symbols from assembly */ \ - ulCriticalNesting; \ - pxCurrentTCB; \ -} + #define portRESTORE_CONTEXT_OS_INT() \ + { \ + extern volatile uint32_t ulCriticalNesting; \ + extern volatile void * volatile pxCurrentTCB; \ + \ + /* Check if INT0 or higher were being handled (case where the OS tick interrupted another */ \ + /* interrupt handler (which was of a higher priority level but decided to lower its priority */ \ + /* level and allow other lower interrupt level to occur). */ \ + /* In this case we don't want to do a task switch because we don't know what the stack */ \ + /* currently looks like (we don't know what the interrupted interrupt handler was doing). */ \ + /* Saving SP in pxCurrentTCB and then later restoring it (thinking restoring the task) */ \ + /* will just be restoring the interrupt handler, no way!!! */ \ + __asm__ __volatile__ ( \ + "ld.w r0, sp[9*4] \n\t" /* Read SR in stack */ \ + "bfextu r0, r0, 22, 3 \n\t" /* Extract the mode bits to R0. */ \ + "cp.w r0, 1 \n\t" /* Compare the mode bits with supervisor mode(b'001) */ \ + "brhi LABEL_INT_SKIP_RESTORE_CONTEXT_"ASTRINGZ ( __LINE__ ) \ + ); \ + \ + /* Else */ \ + /* because it is here safe, always call vTaskSwitchContext() since an OS tick occurred. */ \ + /* A critical section has to be used here because vTaskSwitchContext handles FreeRTOS linked lists. */ \ + portENTER_CRITICAL(); \ + vTaskSwitchContext(); \ + portEXIT_CRITICAL(); \ + \ + /* Restore all registers */ \ + \ + __asm__ __volatile__ ( \ + /* Set SP to point to new stack */ \ + "mov r8, LWRD("ASTRINGZ ( pxCurrentTCB ) ") \n\t" \ + "orh r8, HWRD("ASTRINGZ ( pxCurrentTCB ) ") \n\t" \ + "ld.w r0, r8[0] \n\t" \ + "ld.w sp, r0[0] \n" \ + \ + "LABEL_INT_SKIP_RESTORE_CONTEXT_"ASTRINGZ ( __LINE__ ) ": \n\t" \ + \ + /* Restore ulCriticalNesting variable */ \ + "ld.w r0, sp++ \n\t" \ + "mov r8, LWRD("ASTRINGZ ( ulCriticalNesting ) ") \n\t" \ + "orh r8, HWRD("ASTRINGZ ( ulCriticalNesting ) ") \n\t" \ + "st.w r8[0], r0 \n\t" \ + \ + /* Restore R0..R7 */ \ + "ldm sp++, r0-r7 \n\t" \ + \ + /* Now, the stack should be R8..R12, LR, PC and SR */ \ + "rete" \ + ); \ + \ + /* Force import of global symbols from assembly */ \ + ulCriticalNesting; \ + pxCurrentTCB; \ + } -#endif +#endif /* if configUSE_PREEMPTION == 0 */ /* @@ -411,119 +413,119 @@ extern void *pvPortRealloc( void *pv, size_t xSize ); * NOTE: taskYIELD()(== SCALL) MUST NOT be called in a mode > supervisor mode. * */ -#define portSAVE_CONTEXT_SCALL() \ -{ \ - extern volatile uint32_t ulCriticalNesting; \ - extern volatile void *volatile pxCurrentTCB; \ - \ - /* Warning: the stack layout after SCALL doesn't match the one after an interrupt. */ \ - /* If SR[M2:M0] == 001 */ \ - /* PC and SR are on the stack. */ \ - /* Else (other modes) */ \ - /* Nothing on the stack. */ \ - \ - /* WARNING NOTE: the else case cannot happen as it is strictly forbidden to call */ \ - /* vTaskDelay() and vTaskDelayUntil() OS functions (that result in a taskYield()) */ \ - /* in an interrupt|exception handler. */ \ - \ - __asm__ __volatile__ ( \ - /* in order to save R0-R7 */ \ - "sub sp, 6*4 \n\t"\ - /* Save R0..R7 */ \ - "stm --sp, r0-r7 \n\t"\ - \ - /* in order to save R8-R12 and LR */ \ - /* do not use SP if interrupts occurs, SP must be left at bottom of stack */ \ - "sub r7, sp,-16*4 \n\t"\ - /* Copy PC and SR in other places in the stack. */ \ - "ld.w r0, r7[-2*4] \n\t" /* Read SR */\ - "st.w r7[-8*4], r0 \n\t" /* Copy SR */\ - "ld.w r0, r7[-1*4] \n\t" /* Read PC */\ - "st.w r7[-7*4], r0 \n\t" /* Copy PC */\ - \ - /* Save R8..R12 and LR on the stack. */ \ - "stm --r7, r8-r12, lr \n\t"\ - \ - /* Arriving here we have the following stack organizations: */ \ - /* R8..R12, LR, PC, SR, R0..R7. */ \ - \ - /* Now we can finalize the save. */ \ - \ - /* Save ulCriticalNesting variable - R0 is overwritten */ \ - "mov r8, LWRD("ASTRINGZ(ulCriticalNesting)") \n\t"\ - "orh r8, HWRD("ASTRINGZ(ulCriticalNesting)") \n\t"\ - "ld.w r0, r8[0] \n\t"\ - "st.w --sp, r0" \ - ); \ - \ - /* Disable the its which may cause a context switch (i.e. cause a change of */ \ - /* pxCurrentTCB). */ \ - /* Basically, all accesses to the pxCurrentTCB structure should be put in a */ \ - /* critical section because it is a global structure. */ \ - portENTER_CRITICAL(); \ - \ - /* Store SP in the first member of the structure pointed to by pxCurrentTCB */ \ - __asm__ __volatile__ ( \ - "mov r8, LWRD("ASTRINGZ(pxCurrentTCB)") \n\t"\ - "orh r8, HWRD("ASTRINGZ(pxCurrentTCB)") \n\t"\ - "ld.w r0, r8[0] \n\t"\ - "st.w r0[0], sp" \ - ); \ -} +#define portSAVE_CONTEXT_SCALL() \ + { \ + extern volatile uint32_t ulCriticalNesting; \ + extern volatile void * volatile pxCurrentTCB; \ + \ + /* Warning: the stack layout after SCALL doesn't match the one after an interrupt. */ \ + /* If SR[M2:M0] == 001 */ \ + /* PC and SR are on the stack. */ \ + /* Else (other modes) */ \ + /* Nothing on the stack. */ \ + \ + /* WARNING NOTE: the else case cannot happen as it is strictly forbidden to call */ \ + /* vTaskDelay() and vTaskDelayUntil() OS functions (that result in a taskYield()) */ \ + /* in an interrupt|exception handler. */ \ + \ + __asm__ __volatile__ ( \ + /* in order to save R0-R7 */ \ + "sub sp, 6*4 \n\t" \ + /* Save R0..R7 */ \ + "stm --sp, r0-r7 \n\t" \ + \ + /* in order to save R8-R12 and LR */ \ + /* do not use SP if interrupts occurs, SP must be left at bottom of stack */ \ + "sub r7, sp,-16*4 \n\t" \ + /* Copy PC and SR in other places in the stack. */ \ + "ld.w r0, r7[-2*4] \n\t" /* Read SR */ \ + "st.w r7[-8*4], r0 \n\t" /* Copy SR */ \ + "ld.w r0, r7[-1*4] \n\t" /* Read PC */ \ + "st.w r7[-7*4], r0 \n\t" /* Copy PC */ \ + \ + /* Save R8..R12 and LR on the stack. */ \ + "stm --r7, r8-r12, lr \n\t" \ + \ + /* Arriving here we have the following stack organizations: */ \ + /* R8..R12, LR, PC, SR, R0..R7. */ \ + \ + /* Now we can finalize the save. */ \ + \ + /* Save ulCriticalNesting variable - R0 is overwritten */ \ + "mov r8, LWRD("ASTRINGZ ( ulCriticalNesting ) ") \n\t" \ + "orh r8, HWRD("ASTRINGZ ( ulCriticalNesting ) ") \n\t" \ + "ld.w r0, r8[0] \n\t" \ + "st.w --sp, r0" \ + ); \ + \ + /* Disable the its which may cause a context switch (i.e. cause a change of */ \ + /* pxCurrentTCB). */ \ + /* Basically, all accesses to the pxCurrentTCB structure should be put in a */ \ + /* critical section because it is a global structure. */ \ + portENTER_CRITICAL(); \ + \ + /* Store SP in the first member of the structure pointed to by pxCurrentTCB */ \ + __asm__ __volatile__ ( \ + "mov r8, LWRD("ASTRINGZ ( pxCurrentTCB ) ") \n\t" \ + "orh r8, HWRD("ASTRINGZ ( pxCurrentTCB ) ") \n\t" \ + "ld.w r0, r8[0] \n\t" \ + "st.w r0[0], sp" \ + ); \ + } /* * portRESTORE_CONTEXT() for SupervisorCALL exception. */ -#define portRESTORE_CONTEXT_SCALL() \ -{ \ - extern volatile uint32_t ulCriticalNesting; \ - extern volatile void *volatile pxCurrentTCB; \ - \ - /* Restore all registers */ \ - \ - /* Set SP to point to new stack */ \ - __asm__ __volatile__ ( \ - "mov r8, LWRD("ASTRINGZ(pxCurrentTCB)") \n\t"\ - "orh r8, HWRD("ASTRINGZ(pxCurrentTCB)") \n\t"\ - "ld.w r0, r8[0] \n\t"\ - "ld.w sp, r0[0]" \ - ); \ - \ - /* Leave pxCurrentTCB variable access critical section */ \ - portEXIT_CRITICAL(); \ - \ - __asm__ __volatile__ ( \ - /* Restore ulCriticalNesting variable */ \ - "ld.w r0, sp++ \n\t"\ - "mov r8, LWRD("ASTRINGZ(ulCriticalNesting)") \n\t"\ - "orh r8, HWRD("ASTRINGZ(ulCriticalNesting)") \n\t"\ - "st.w r8[0], r0 \n\t"\ - \ - /* skip PC and SR */ \ - /* do not use SP if interrupts occurs, SP must be left at bottom of stack */ \ - "sub r7, sp, -10*4 \n\t"\ - /* Restore r8-r12 and LR */ \ - "ldm r7++, r8-r12, lr \n\t"\ - \ - /* RETS will take care of the extra PC and SR restore. */ \ - /* So, we have to prepare the stack for this. */ \ - "ld.w r0, r7[-8*4] \n\t" /* Read SR */\ - "st.w r7[-2*4], r0 \n\t" /* Copy SR */\ - "ld.w r0, r7[-7*4] \n\t" /* Read PC */\ - "st.w r7[-1*4], r0 \n\t" /* Copy PC */\ - \ - /* Restore R0..R7 */ \ - "ldm sp++, r0-r7 \n\t"\ - \ - "sub sp, -6*4 \n\t"\ - \ - "rets" \ - ); \ - \ - /* Force import of global symbols from assembly */ \ - ulCriticalNesting; \ - pxCurrentTCB; \ -} +#define portRESTORE_CONTEXT_SCALL() \ + { \ + extern volatile uint32_t ulCriticalNesting; \ + extern volatile void * volatile pxCurrentTCB; \ + \ + /* Restore all registers */ \ + \ + /* Set SP to point to new stack */ \ + __asm__ __volatile__ ( \ + "mov r8, LWRD("ASTRINGZ ( pxCurrentTCB ) ") \n\t" \ + "orh r8, HWRD("ASTRINGZ ( pxCurrentTCB ) ") \n\t" \ + "ld.w r0, r8[0] \n\t" \ + "ld.w sp, r0[0]" \ + ); \ + \ + /* Leave pxCurrentTCB variable access critical section */ \ + portEXIT_CRITICAL(); \ + \ + __asm__ __volatile__ ( \ + /* Restore ulCriticalNesting variable */ \ + "ld.w r0, sp++ \n\t" \ + "mov r8, LWRD("ASTRINGZ ( ulCriticalNesting ) ") \n\t" \ + "orh r8, HWRD("ASTRINGZ ( ulCriticalNesting ) ") \n\t" \ + "st.w r8[0], r0 \n\t" \ + \ + /* skip PC and SR */ \ + /* do not use SP if interrupts occurs, SP must be left at bottom of stack */ \ + "sub r7, sp, -10*4 \n\t" \ + /* Restore r8-r12 and LR */ \ + "ldm r7++, r8-r12, lr \n\t" \ + \ + /* RETS will take care of the extra PC and SR restore. */ \ + /* So, we have to prepare the stack for this. */ \ + "ld.w r0, r7[-8*4] \n\t" /* Read SR */ \ + "st.w r7[-2*4], r0 \n\t" /* Copy SR */ \ + "ld.w r0, r7[-7*4] \n\t" /* Read PC */ \ + "st.w r7[-1*4], r0 \n\t" /* Copy PC */ \ + \ + /* Restore R0..R7 */ \ + "ldm sp++, r0-r7 \n\t" \ + \ + "sub sp, -6*4 \n\t" \ + \ + "rets" \ + ); \ + \ + /* Force import of global symbols from assembly */ \ + ulCriticalNesting; \ + pxCurrentTCB; \ + } /* @@ -536,150 +538,150 @@ extern void *pvPortRealloc( void *pv, size_t xSize ); * ISR entry and exit macros. These are only required if a task switch * is required from the ISR. */ -#define portENTER_SWITCHING_ISR() \ -{ \ - /* Save R0..R7 */ \ - __asm__ __volatile__ ("stm --sp, r0-r7"); \ - \ - /* With the cooperative scheduler, as there is no context switch by interrupt, */ \ - /* there is also no context save. */ \ -} + #define portENTER_SWITCHING_ISR() \ + { \ + /* Save R0..R7 */ \ + __asm__ __volatile__ ( "stm --sp, r0-r7" ); \ + \ + /* With the cooperative scheduler, as there is no context switch by interrupt, */ \ + /* there is also no context save. */ \ + } /* * Input parameter: in R12, boolean. Perform a vTaskSwitchContext() if 1 */ -#define portEXIT_SWITCHING_ISR() \ -{ \ - __asm__ __volatile__ ( \ - /* Restore R0..R7 */ \ - "ldm sp++, r0-r7 \n\t"\ - \ - /* With the cooperative scheduler, as there is no context switch by interrupt, */ \ - /* there is also no context restore. */ \ - "rete" \ - ); \ -} + #define portEXIT_SWITCHING_ISR() \ + { \ + __asm__ __volatile__ ( \ + /* Restore R0..R7 */ \ + "ldm sp++, r0-r7 \n\t" \ + \ + /* With the cooperative scheduler, as there is no context switch by interrupt, */ \ + /* there is also no context restore. */ \ + "rete" \ + ); \ + } -#else +#else /* if configUSE_PREEMPTION == 0 */ /* * ISR entry and exit macros. These are only required if a task switch * is required from the ISR. */ -#define portENTER_SWITCHING_ISR() \ -{ \ - extern volatile uint32_t ulCriticalNesting; \ - extern volatile void *volatile pxCurrentTCB; \ - \ - /* When we come here */ \ - /* Registers R8..R12, LR, PC and SR had already been pushed to system stack */ \ - \ - __asm__ __volatile__ ( \ - /* Save R0..R7 */ \ - "stm --sp, r0-r7 \n\t"\ - \ - /* Save ulCriticalNesting variable - R0 is overwritten */ \ - "mov r8, LWRD("ASTRINGZ(ulCriticalNesting)") \n\t"\ - "orh r8, HWRD("ASTRINGZ(ulCriticalNesting)") \n\t"\ - "ld.w r0, r8[0] \n\t"\ - "st.w --sp, r0 \n\t"\ - \ - /* Check if INT0 or higher were being handled (case where the OS tick interrupted another */ \ - /* interrupt handler (which was of a higher priority level but decided to lower its priority */ \ - /* level and allow other lower interrupt level to occur). */ \ - /* In this case we don't want to do a task switch because we don't know what the stack */ \ - /* currently looks like (we don't know what the interrupted interrupt handler was doing). */ \ - /* Saving SP in pxCurrentTCB and then later restoring it (thinking restoring the task) */ \ - /* will just be restoring the interrupt handler, no way!!! */ \ - /* So, since we won't do a vTaskSwitchContext(), it's of no use to save SP. */ \ - "ld.w r0, sp[9*4] \n\t" /* Read SR in stack */\ - "bfextu r0, r0, 22, 3 \n\t" /* Extract the mode bits to R0. */\ - "cp.w r0, 1 \n\t" /* Compare the mode bits with supervisor mode(b'001) */\ - "brhi LABEL_ISR_SKIP_SAVE_CONTEXT_"ASTRINGZ(__LINE__)" \n\t"\ - \ - /* Store SP in the first member of the structure pointed to by pxCurrentTCB */ \ - "mov r8, LWRD("ASTRINGZ(pxCurrentTCB)") \n\t"\ - "orh r8, HWRD("ASTRINGZ(pxCurrentTCB)") \n\t"\ - "ld.w r0, r8[0] \n\t"\ - "st.w r0[0], sp \n"\ - \ - "LABEL_ISR_SKIP_SAVE_CONTEXT_"ASTRINGZ(__LINE__)":" \ - ); \ -} + #define portENTER_SWITCHING_ISR() \ + { \ + extern volatile uint32_t ulCriticalNesting; \ + extern volatile void * volatile pxCurrentTCB; \ + \ + /* When we come here */ \ + /* Registers R8..R12, LR, PC and SR had already been pushed to system stack */ \ + \ + __asm__ __volatile__ ( \ + /* Save R0..R7 */ \ + "stm --sp, r0-r7 \n\t" \ + \ + /* Save ulCriticalNesting variable - R0 is overwritten */ \ + "mov r8, LWRD("ASTRINGZ ( ulCriticalNesting ) ") \n\t" \ + "orh r8, HWRD("ASTRINGZ ( ulCriticalNesting ) ") \n\t" \ + "ld.w r0, r8[0] \n\t" \ + "st.w --sp, r0 \n\t" \ + \ + /* Check if INT0 or higher were being handled (case where the OS tick interrupted another */ \ + /* interrupt handler (which was of a higher priority level but decided to lower its priority */ \ + /* level and allow other lower interrupt level to occur). */ \ + /* In this case we don't want to do a task switch because we don't know what the stack */ \ + /* currently looks like (we don't know what the interrupted interrupt handler was doing). */ \ + /* Saving SP in pxCurrentTCB and then later restoring it (thinking restoring the task) */ \ + /* will just be restoring the interrupt handler, no way!!! */ \ + /* So, since we won't do a vTaskSwitchContext(), it's of no use to save SP. */ \ + "ld.w r0, sp[9*4] \n\t" /* Read SR in stack */ \ + "bfextu r0, r0, 22, 3 \n\t" /* Extract the mode bits to R0. */ \ + "cp.w r0, 1 \n\t" /* Compare the mode bits with supervisor mode(b'001) */ \ + "brhi LABEL_ISR_SKIP_SAVE_CONTEXT_"ASTRINGZ ( __LINE__ ) " \n\t" \ + \ + /* Store SP in the first member of the structure pointed to by pxCurrentTCB */ \ + "mov r8, LWRD("ASTRINGZ ( pxCurrentTCB ) ") \n\t" \ + "orh r8, HWRD("ASTRINGZ ( pxCurrentTCB ) ") \n\t" \ + "ld.w r0, r8[0] \n\t" \ + "st.w r0[0], sp \n" \ + \ + "LABEL_ISR_SKIP_SAVE_CONTEXT_"ASTRINGZ ( __LINE__ ) ":" \ + ); \ + } /* * Input parameter: in R12, boolean. Perform a vTaskSwitchContext() if 1 */ -#define portEXIT_SWITCHING_ISR() \ -{ \ - extern volatile uint32_t ulCriticalNesting; \ - extern volatile void *volatile pxCurrentTCB; \ - \ - __asm__ __volatile__ ( \ - /* Check if INT0 or higher were being handled (case where the OS tick interrupted another */ \ - /* interrupt handler (which was of a higher priority level but decided to lower its priority */ \ - /* level and allow other lower interrupt level to occur). */ \ - /* In this case it's of no use to switch context and restore a new SP because we purposedly */ \ - /* did not previously save SP in its TCB. */ \ - "ld.w r0, sp[9*4] \n\t" /* Read SR in stack */\ - "bfextu r0, r0, 22, 3 \n\t" /* Extract the mode bits to R0. */\ - "cp.w r0, 1 \n\t" /* Compare the mode bits with supervisor mode(b'001) */\ - "brhi LABEL_ISR_SKIP_RESTORE_CONTEXT_"ASTRINGZ(__LINE__)" \n\t"\ - \ - /* If a switch is required then we just need to call */ \ - /* vTaskSwitchContext() as the context has already been */ \ - /* saved. */ \ - "cp.w r12, 1 \n\t" /* Check if Switch context is required. */\ - "brne LABEL_ISR_RESTORE_CONTEXT_"ASTRINGZ(__LINE__)":C" \ - ); \ - \ - /* A critical section has to be used here because vTaskSwitchContext handles FreeRTOS linked lists. */\ - portENTER_CRITICAL(); \ - vTaskSwitchContext(); \ - portEXIT_CRITICAL(); \ - \ - __asm__ __volatile__ ( \ - "LABEL_ISR_RESTORE_CONTEXT_"ASTRINGZ(__LINE__)": \n\t"\ - /* Restore the context of which ever task is now the highest */ \ - /* priority that is ready to run. */ \ - \ - /* Restore all registers */ \ - \ - /* Set SP to point to new stack */ \ - "mov r8, LWRD("ASTRINGZ(pxCurrentTCB)") \n\t"\ - "orh r8, HWRD("ASTRINGZ(pxCurrentTCB)") \n\t"\ - "ld.w r0, r8[0] \n\t"\ - "ld.w sp, r0[0] \n"\ - \ - "LABEL_ISR_SKIP_RESTORE_CONTEXT_"ASTRINGZ(__LINE__)": \n\t"\ - \ - /* Restore ulCriticalNesting variable */ \ - "ld.w r0, sp++ \n\t"\ - "mov r8, LWRD("ASTRINGZ(ulCriticalNesting)") \n\t"\ - "orh r8, HWRD("ASTRINGZ(ulCriticalNesting)") \n\t"\ - "st.w r8[0], r0 \n\t"\ - \ - /* Restore R0..R7 */ \ - "ldm sp++, r0-r7 \n\t"\ - \ - /* Now, the stack should be R8..R12, LR, PC and SR */ \ - "rete" \ - ); \ - \ - /* Force import of global symbols from assembly */ \ - ulCriticalNesting; \ - pxCurrentTCB; \ -} + #define portEXIT_SWITCHING_ISR() \ + { \ + extern volatile uint32_t ulCriticalNesting; \ + extern volatile void * volatile pxCurrentTCB; \ + \ + __asm__ __volatile__ ( \ + /* Check if INT0 or higher were being handled (case where the OS tick interrupted another */ \ + /* interrupt handler (which was of a higher priority level but decided to lower its priority */ \ + /* level and allow other lower interrupt level to occur). */ \ + /* In this case it's of no use to switch context and restore a new SP because we purposely */ \ + /* did not previously save SP in its TCB. */ \ + "ld.w r0, sp[9*4] \n\t" /* Read SR in stack */ \ + "bfextu r0, r0, 22, 3 \n\t" /* Extract the mode bits to R0. */ \ + "cp.w r0, 1 \n\t" /* Compare the mode bits with supervisor mode(b'001) */ \ + "brhi LABEL_ISR_SKIP_RESTORE_CONTEXT_"ASTRINGZ ( __LINE__ ) " \n\t" \ + \ + /* If a switch is required then we just need to call */ \ + /* vTaskSwitchContext() as the context has already been */ \ + /* saved. */ \ + "cp.w r12, 1 \n\t" /* Check if Switch context is required. */ \ + "brne LABEL_ISR_RESTORE_CONTEXT_"ASTRINGZ ( __LINE__ ) ":C" \ + ); \ + \ + /* A critical section has to be used here because vTaskSwitchContext handles FreeRTOS linked lists. */ \ + portENTER_CRITICAL(); \ + vTaskSwitchContext(); \ + portEXIT_CRITICAL(); \ + \ + __asm__ __volatile__ ( \ + "LABEL_ISR_RESTORE_CONTEXT_"ASTRINGZ ( __LINE__ ) ": \n\t" \ + /* Restore the context of which ever task is now the highest */ \ + /* priority that is ready to run. */ \ + \ + /* Restore all registers */ \ + \ + /* Set SP to point to new stack */ \ + "mov r8, LWRD("ASTRINGZ ( pxCurrentTCB ) ") \n\t" \ + "orh r8, HWRD("ASTRINGZ ( pxCurrentTCB ) ") \n\t" \ + "ld.w r0, r8[0] \n\t" \ + "ld.w sp, r0[0] \n" \ + \ + "LABEL_ISR_SKIP_RESTORE_CONTEXT_"ASTRINGZ ( __LINE__ ) ": \n\t" \ + \ + /* Restore ulCriticalNesting variable */ \ + "ld.w r0, sp++ \n\t" \ + "mov r8, LWRD("ASTRINGZ ( ulCriticalNesting ) ") \n\t" \ + "orh r8, HWRD("ASTRINGZ ( ulCriticalNesting ) ") \n\t" \ + "st.w r8[0], r0 \n\t" \ + \ + /* Restore R0..R7 */ \ + "ldm sp++, r0-r7 \n\t" \ + \ + /* Now, the stack should be R8..R12, LR, PC and SR */ \ + "rete" \ + ); \ + \ + /* Force import of global symbols from assembly */ \ + ulCriticalNesting; \ + pxCurrentTCB; \ + } -#endif +#endif /* if configUSE_PREEMPTION == 0 */ -#define portYIELD() {__asm__ __volatile__ ("scall");} +#define portYIELD() { __asm__ __volatile__ ( "scall" ); } /* Task function macros as described on the FreeRTOS.org WEB site. */ -#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters ) -#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters ) +#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters ) +#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters ) /* *INDENT-OFF* */ #ifdef __cplusplus diff --git a/Source/portable/IAR/AVR32_UC3/read.c b/Source/portable/IAR/AVR32_UC3/read.c index 329382e6a..7c8981e96 100644 --- a/Source/portable/IAR/AVR32_UC3/read.c +++ b/Source/portable/IAR/AVR32_UC3/read.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT AND BSD-3-Clause @@ -27,20 +27,21 @@ */ /*This file is prepared for Doxygen automatic documentation generation.*/ + /*! \file ********************************************************************* - * - * \brief System-specific implementation of the \ref __read function used by - the standard library. - * - * - Compiler: IAR EWAVR32 - * - Supported devices: All AVR32 devices with a USART module can be used. - * - AppNote: - * - * \author Atmel Corporation (Now Microchip): - * https://www.microchip.com \n - * Support and FAQ: https://www.microchip.com/support/ - * - ******************************************************************************/ +* +* \brief System-specific implementation of the \ref __read function used by +* the standard library. +* +* - Compiler: IAR EWAVR32 +* - Supported devices: All AVR32 devices with a USART module can be used. +* - AppNote: +* +* \author Atmel Corporation (Now Microchip): +* https://www.microchip.com \n +* Support and FAQ: https://www.microchip.com/support/ +* +******************************************************************************/ /* * Copyright (c) 2007, Atmel Corporation All rights reserved. @@ -82,7 +83,7 @@ _STD_BEGIN #pragma module_name = "?__read" -extern volatile avr32_usart_t *volatile stdio_usart_base; +extern volatile avr32_usart_t * volatile stdio_usart_base; /*! \brief Reads a number of bytes, at most \a size, into the memory area @@ -95,28 +96,33 @@ extern volatile avr32_usart_t *volatile stdio_usart_base; * \return The number of bytes read, \c 0 at the end of the file, or * \c _LLIO_ERROR on failure. */ -size_t __read(int handle, uint8_t *buffer, size_t size) +size_t __read( int handle, + uint8_t * buffer, + size_t size ) { - int nChars = 0; - - // This implementation only reads from stdin. - // For all other file handles, it returns failure. - if (handle != _LLIO_STDIN) - { - return _LLIO_ERROR; - } - - for (; size > 0; --size) - { - int c = usart_getchar(stdio_usart_base); - if (c < 0) - break; - - *buffer++ = c; - ++nChars; - } - - return nChars; + int nChars = 0; + + /* This implementation only reads from stdin. */ + /* For all other file handles, it returns failure. */ + if( handle != _LLIO_STDIN ) + { + return _LLIO_ERROR; + } + + for( ; size > 0; --size ) + { + int c = usart_getchar( stdio_usart_base ); + + if( c < 0 ) + { + break; + } + + *buffer++ = c; + ++nChars; + } + + return nChars; } diff --git a/Source/portable/IAR/AVR32_UC3/write.c b/Source/portable/IAR/AVR32_UC3/write.c index 7ce7f2e03..661a4bcb7 100644 --- a/Source/portable/IAR/AVR32_UC3/write.c +++ b/Source/portable/IAR/AVR32_UC3/write.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT AND BSD-3-Clause @@ -27,20 +27,21 @@ */ /*This file is prepared for Doxygen automatic documentation generation.*/ + /*! \file ********************************************************************* - * - * \brief System-specific implementation of the \ref __write function used by - the standard library. - * - * - Compiler: IAR EWAVR32 - * - Supported devices: All AVR32 devices with a USART module can be used. - * - AppNote: - * - * \author Atmel Corporation (Now Microchip): - * https://www.microchip.com \n - * Support and FAQ: https://www.microchip.com/support - * - ******************************************************************************/ +* +* \brief System-specific implementation of the \ref __write function used by +* the standard library. +* +* - Compiler: IAR EWAVR32 +* - Supported devices: All AVR32 devices with a USART module can be used. +* - AppNote: +* +* \author Atmel Corporation (Now Microchip): +* https://www.microchip.com \n +* Support and FAQ: https://www.microchip.com/support +* +******************************************************************************/ /* * Copyright (c) 2007, Atmel Corporation All rights reserved. @@ -82,8 +83,8 @@ _STD_BEGIN #pragma module_name = "?__write" -//! Pointer to the base of the USART module instance to use for stdio. -__no_init volatile avr32_usart_t *volatile stdio_usart_base; +/*! Pointer to the base of the USART module instance to use for stdio. */ +__no_init volatile avr32_usart_t * volatile stdio_usart_base; /*! \brief Writes a number of bytes, at most \a size, from the memory area @@ -99,34 +100,36 @@ __no_init volatile avr32_usart_t *volatile stdio_usart_base; * * \return The number of bytes written, or \c _LLIO_ERROR on failure. */ -size_t __write(int handle, const uint8_t *buffer, size_t size) +size_t __write( int handle, + const uint8_t * buffer, + size_t size ) { - size_t nChars = 0; - - if (buffer == 0) - { - // This means that we should flush internal buffers. - return 0; - } - - // This implementation only writes to stdout and stderr. - // For all other file handles, it returns failure. - if (handle != _LLIO_STDOUT && handle != _LLIO_STDERR) - { - return _LLIO_ERROR; - } - - for (; size != 0; --size) - { - if (usart_putchar(stdio_usart_base, *buffer++) < 0) + size_t nChars = 0; + + if( buffer == 0 ) { - return _LLIO_ERROR; + /* This means that we should flush internal buffers. */ + return 0; } - ++nChars; - } + /* This implementation only writes to stdout and stderr. */ + /* For all other file handles, it returns failure. */ + if( ( handle != _LLIO_STDOUT ) && ( handle != _LLIO_STDERR ) ) + { + return _LLIO_ERROR; + } + + for( ; size != 0; --size ) + { + if( usart_putchar( stdio_usart_base, *buffer++ ) < 0 ) + { + return _LLIO_ERROR; + } + + ++nChars; + } - return nChars; + return nChars; } diff --git a/Source/portable/IAR/AVR_AVRDx/port.c b/Source/portable/IAR/AVR_AVRDx/port.c index 9baad85b6..062aa73b4 100644 --- a/Source/portable/IAR/AVR_AVRDx/port.c +++ b/Source/portable/IAR/AVR_AVRDx/port.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/Source/portable/IAR/AVR_AVRDx/porthardware.h b/Source/portable/IAR/AVR_AVRDx/porthardware.h index be222e2c2..b839fd088 100644 --- a/Source/portable/IAR/AVR_AVRDx/porthardware.h +++ b/Source/portable/IAR/AVR_AVRDx/porthardware.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/Source/portable/IAR/AVR_AVRDx/portmacro.h b/Source/portable/IAR/AVR_AVRDx/portmacro.h index 404253bd5..a973fa57a 100644 --- a/Source/portable/IAR/AVR_AVRDx/portmacro.h +++ b/Source/portable/IAR/AVR_AVRDx/portmacro.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -64,8 +64,8 @@ typedef unsigned char UBaseType_t; typedef uint16_t TickType_t; #define portMAX_DELAY ( TickType_t ) 0xffff #elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS ) - typedef uint32_t TickType_t; - #define portMAX_DELAY ( TickType_t ) ( 0xFFFFFFFFUL ) + typedef uint32_t TickType_t; + #define portMAX_DELAY ( TickType_t ) ( 0xFFFFFFFFUL ) #else #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width. #endif diff --git a/Source/portable/IAR/AVR_AVRDx/portmacro.s90 b/Source/portable/IAR/AVR_AVRDx/portmacro.s90 index 5cf302ff4..3271b6fa6 100644 --- a/Source/portable/IAR/AVR_AVRDx/portmacro.s90 +++ b/Source/portable/IAR/AVR_AVRDx/portmacro.s90 @@ -1,5 +1,5 @@ ;/* -; * FreeRTOS Kernel V10.6.2 +; * FreeRTOS Kernel V11.0.1 ; * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. ; * ; * SPDX-License-Identifier: MIT diff --git a/Source/portable/IAR/AVR_Mega0/port.c b/Source/portable/IAR/AVR_Mega0/port.c index 839f2a965..78d1fe231 100644 --- a/Source/portable/IAR/AVR_Mega0/port.c +++ b/Source/portable/IAR/AVR_Mega0/port.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/Source/portable/IAR/AVR_Mega0/porthardware.h b/Source/portable/IAR/AVR_Mega0/porthardware.h index 4e39ad3e0..21c430641 100644 --- a/Source/portable/IAR/AVR_Mega0/porthardware.h +++ b/Source/portable/IAR/AVR_Mega0/porthardware.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/Source/portable/IAR/AVR_Mega0/portmacro.h b/Source/portable/IAR/AVR_Mega0/portmacro.h index 404253bd5..a973fa57a 100644 --- a/Source/portable/IAR/AVR_Mega0/portmacro.h +++ b/Source/portable/IAR/AVR_Mega0/portmacro.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -64,8 +64,8 @@ typedef unsigned char UBaseType_t; typedef uint16_t TickType_t; #define portMAX_DELAY ( TickType_t ) 0xffff #elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS ) - typedef uint32_t TickType_t; - #define portMAX_DELAY ( TickType_t ) ( 0xFFFFFFFFUL ) + typedef uint32_t TickType_t; + #define portMAX_DELAY ( TickType_t ) ( 0xFFFFFFFFUL ) #else #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width. #endif diff --git a/Source/portable/IAR/AVR_Mega0/portmacro.s90 b/Source/portable/IAR/AVR_Mega0/portmacro.s90 index ed847773d..46e6977d8 100644 --- a/Source/portable/IAR/AVR_Mega0/portmacro.s90 +++ b/Source/portable/IAR/AVR_Mega0/portmacro.s90 @@ -1,5 +1,5 @@ ;/* -; * FreeRTOS Kernel V10.6.2 +; * FreeRTOS Kernel V11.0.1 ; * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. ; * ; * SPDX-License-Identifier: MIT diff --git a/Source/portable/IAR/AtmelSAM7S64/AT91SAM7S64.h b/Source/portable/IAR/AtmelSAM7S64/AT91SAM7S64.h index 107754719..2dbceba43 100644 --- a/Source/portable/IAR/AtmelSAM7S64/AT91SAM7S64.h +++ b/Source/portable/IAR/AtmelSAM7S64/AT91SAM7S64.h @@ -1,1914 +1,1936 @@ -// ---------------------------------------------------------------------------- -// ATMEL Microcontroller Software Support - ROUSSET - -// ---------------------------------------------------------------------------- -// The software is delivered "AS IS" without warranty or condition of any -// kind, either express, implied or statutory. This includes without -// limitation any warranty or condition with respect to merchantability or -// fitness for any particular purpose, or against the infringements of -// intellectual property rights of others. -// ---------------------------------------------------------------------------- -// File Name : AT91SAM7S64.h -// Object : AT91SAM7S64 definitions -// Generated : AT91 SW Application Group 07/16/2004 (07:43:08) -// -// CVS Reference : /AT91SAM7S64.pl/1.12/Mon Jul 12 13:02:30 2004// -// CVS Reference : /SYSC_SAM7Sxx.pl/1.5/Mon Jul 12 16:22:12 2004// -// CVS Reference : /MC_SAM02.pl/1.3/Wed Mar 10 08:37:04 2004// -// CVS Reference : /UDP_1765B.pl/1.3/Fri Aug 2 14:45:38 2002// -// CVS Reference : /AIC_1796B.pl/1.1.1.1/Fri Jun 28 09:36:48 2002// -// CVS Reference : /lib_pmc_SAM.h/1.6/Tue Apr 27 13:53:52 2004// -// CVS Reference : /PIO_1725D.pl/1.1.1.1/Fri Jun 28 09:36:48 2002// -// CVS Reference : /DBGU_1754A.pl/1.4/Fri Jan 31 12:18:24 2003// -// CVS Reference : /US_1739C.pl/1.2/Mon Jul 12 17:26:24 2004// -// CVS Reference : /SPI2.pl/1.2/Fri Oct 17 08:13:40 2003// -// CVS Reference : /SSC_1762A.pl/1.2/Fri Nov 8 13:26:40 2002// -// CVS Reference : /lib_tc_1753b.h/1.1/Fri Jan 31 12:20:02 2003// -// CVS Reference : /TWI_1761B.pl/1.4/Fri Feb 7 10:30:08 2003// -// CVS Reference : /PDC_1734B.pl/1.2/Thu Nov 21 16:38:24 2002// -// CVS Reference : /ADC_SAM.pl/1.7/Fri Oct 17 08:12:38 2003// -// CVS Reference : /lib_PWM_SAM.h/1.3/Thu Jan 22 10:10:50 2004// -// ---------------------------------------------------------------------------- +/* ---------------------------------------------------------------------------- */ +/* ATMEL Microcontroller Software Support - ROUSSET - */ +/* ---------------------------------------------------------------------------- */ +/* The software is delivered "AS IS" without warranty or condition of any */ +/* kind, either express, implied or statutory. This includes without */ +/* limitation any warranty or condition with respect to merchantability or */ +/* fitness for any particular purpose, or against the infringements of */ +/* intellectual property rights of others. */ +/* ---------------------------------------------------------------------------- */ +/* File Name : AT91SAM7S64.h */ +/* Object : AT91SAM7S64 definitions */ +/* Generated : AT91 SW Application Group 07/16/2004 (07:43:08) */ +/* */ +/* CVS Reference : /AT91SAM7S64.pl/1.12/Mon Jul 12 13:02:30 2004// */ +/* CVS Reference : /SYSC_SAM7Sxx.pl/1.5/Mon Jul 12 16:22:12 2004// */ +/* CVS Reference : /MC_SAM02.pl/1.3/Wed Mar 10 08:37:04 2004// */ +/* CVS Reference : /UDP_1765B.pl/1.3/Fri Aug 2 14:45:38 2002// */ +/* CVS Reference : /AIC_1796B.pl/1.1.1.1/Fri Jun 28 09:36:48 2002// */ +/* CVS Reference : /lib_pmc_SAM.h/1.6/Tue Apr 27 13:53:52 2004// */ +/* CVS Reference : /PIO_1725D.pl/1.1.1.1/Fri Jun 28 09:36:48 2002// */ +/* CVS Reference : /DBGU_1754A.pl/1.4/Fri Jan 31 12:18:24 2003// */ +/* CVS Reference : /US_1739C.pl/1.2/Mon Jul 12 17:26:24 2004// */ +/* CVS Reference : /SPI2.pl/1.2/Fri Oct 17 08:13:40 2003// */ +/* CVS Reference : /SSC_1762A.pl/1.2/Fri Nov 8 13:26:40 2002// */ +/* CVS Reference : /lib_tc_1753b.h/1.1/Fri Jan 31 12:20:02 2003// */ +/* CVS Reference : /TWI_1761B.pl/1.4/Fri Feb 7 10:30:08 2003// */ +/* CVS Reference : /PDC_1734B.pl/1.2/Thu Nov 21 16:38:24 2002// */ +/* CVS Reference : /ADC_SAM.pl/1.7/Fri Oct 17 08:12:38 2003// */ +/* CVS Reference : /lib_PWM_SAM.h/1.3/Thu Jan 22 10:10:50 2004// */ +/* ---------------------------------------------------------------------------- */ #ifndef AT91SAM7S64_H #define AT91SAM7S64_H -typedef volatile unsigned int AT91_REG;// Hardware register definition +typedef volatile unsigned int AT91_REG; /* Hardware register definition */ -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR System Peripherals -// ***************************************************************************** -typedef struct _AT91S_SYSC { - AT91_REG SYSC_AIC_SMR[32]; // Source Mode Register - AT91_REG SYSC_AIC_SVR[32]; // Source Vector Register - AT91_REG SYSC_AIC_IVR; // IRQ Vector Register - AT91_REG SYSC_AIC_FVR; // FIQ Vector Register - AT91_REG SYSC_AIC_ISR; // Interrupt Status Register - AT91_REG SYSC_AIC_IPR; // Interrupt Pending Register - AT91_REG SYSC_AIC_IMR; // Interrupt Mask Register - AT91_REG SYSC_AIC_CISR; // Core Interrupt Status Register - AT91_REG Reserved0[2]; // - AT91_REG SYSC_AIC_IECR; // Interrupt Enable Command Register - AT91_REG SYSC_AIC_IDCR; // Interrupt Disable Command Register - AT91_REG SYSC_AIC_ICCR; // Interrupt Clear Command Register - AT91_REG SYSC_AIC_ISCR; // Interrupt Set Command Register - AT91_REG SYSC_AIC_EOICR; // End of Interrupt Command Register - AT91_REG SYSC_AIC_SPU; // Spurious Vector Register - AT91_REG SYSC_AIC_DCR; // Debug Control Register (Protect) - AT91_REG Reserved1[1]; // - AT91_REG SYSC_AIC_FFER; // Fast Forcing Enable Register - AT91_REG SYSC_AIC_FFDR; // Fast Forcing Disable Register - AT91_REG SYSC_AIC_FFSR; // Fast Forcing Status Register - AT91_REG Reserved2[45]; // - AT91_REG SYSC_DBGU_CR; // Control Register - AT91_REG SYSC_DBGU_MR; // Mode Register - AT91_REG SYSC_DBGU_IER; // Interrupt Enable Register - AT91_REG SYSC_DBGU_IDR; // Interrupt Disable Register - AT91_REG SYSC_DBGU_IMR; // Interrupt Mask Register - AT91_REG SYSC_DBGU_CSR; // Channel Status Register - AT91_REG SYSC_DBGU_RHR; // Receiver Holding Register - AT91_REG SYSC_DBGU_THR; // Transmitter Holding Register - AT91_REG SYSC_DBGU_BRGR; // Baud Rate Generator Register - AT91_REG Reserved3[7]; // - AT91_REG SYSC_DBGU_C1R; // Chip ID1 Register - AT91_REG SYSC_DBGU_C2R; // Chip ID2 Register - AT91_REG SYSC_DBGU_FNTR; // Force NTRST Register - AT91_REG Reserved4[45]; // - AT91_REG SYSC_DBGU_RPR; // Receive Pointer Register - AT91_REG SYSC_DBGU_RCR; // Receive Counter Register - AT91_REG SYSC_DBGU_TPR; // Transmit Pointer Register - AT91_REG SYSC_DBGU_TCR; // Transmit Counter Register - AT91_REG SYSC_DBGU_RNPR; // Receive Next Pointer Register - AT91_REG SYSC_DBGU_RNCR; // Receive Next Counter Register - AT91_REG SYSC_DBGU_TNPR; // Transmit Next Pointer Register - AT91_REG SYSC_DBGU_TNCR; // Transmit Next Counter Register - AT91_REG SYSC_DBGU_PTCR; // PDC Transfer Control Register - AT91_REG SYSC_DBGU_PTSR; // PDC Transfer Status Register - AT91_REG Reserved5[54]; // - AT91_REG SYSC_PIOA_PER; // PIO Enable Register - AT91_REG SYSC_PIOA_PDR; // PIO Disable Register - AT91_REG SYSC_PIOA_PSR; // PIO Status Register - AT91_REG Reserved6[1]; // - AT91_REG SYSC_PIOA_OER; // Output Enable Register - AT91_REG SYSC_PIOA_ODR; // Output Disable Registerr - AT91_REG SYSC_PIOA_OSR; // Output Status Register - AT91_REG Reserved7[1]; // - AT91_REG SYSC_PIOA_IFER; // Input Filter Enable Register - AT91_REG SYSC_PIOA_IFDR; // Input Filter Disable Register - AT91_REG SYSC_PIOA_IFSR; // Input Filter Status Register - AT91_REG Reserved8[1]; // - AT91_REG SYSC_PIOA_SODR; // Set Output Data Register - AT91_REG SYSC_PIOA_CODR; // Clear Output Data Register - AT91_REG SYSC_PIOA_ODSR; // Output Data Status Register - AT91_REG SYSC_PIOA_PDSR; // Pin Data Status Register - AT91_REG SYSC_PIOA_IER; // Interrupt Enable Register - AT91_REG SYSC_PIOA_IDR; // Interrupt Disable Register - AT91_REG SYSC_PIOA_IMR; // Interrupt Mask Register - AT91_REG SYSC_PIOA_ISR; // Interrupt Status Register - AT91_REG SYSC_PIOA_MDER; // Multi-driver Enable Register - AT91_REG SYSC_PIOA_MDDR; // Multi-driver Disable Register - AT91_REG SYSC_PIOA_MDSR; // Multi-driver Status Register - AT91_REG Reserved9[1]; // - AT91_REG SYSC_PIOA_PPUDR; // Pull-up Disable Register - AT91_REG SYSC_PIOA_PPUER; // Pull-up Enable Register - AT91_REG SYSC_PIOA_PPUSR; // Pad Pull-up Status Register - AT91_REG Reserved10[1]; // - AT91_REG SYSC_PIOA_ASR; // Select A Register - AT91_REG SYSC_PIOA_BSR; // Select B Register - AT91_REG SYSC_PIOA_ABSR; // AB Select Status Register - AT91_REG Reserved11[9]; // - AT91_REG SYSC_PIOA_OWER; // Output Write Enable Register - AT91_REG SYSC_PIOA_OWDR; // Output Write Disable Register - AT91_REG SYSC_PIOA_OWSR; // Output Write Status Register - AT91_REG Reserved12[469]; // - AT91_REG SYSC_PMC_SCER; // System Clock Enable Register - AT91_REG SYSC_PMC_SCDR; // System Clock Disable Register - AT91_REG SYSC_PMC_SCSR; // System Clock Status Register - AT91_REG Reserved13[1]; // - AT91_REG SYSC_PMC_PCER; // Peripheral Clock Enable Register - AT91_REG SYSC_PMC_PCDR; // Peripheral Clock Disable Register - AT91_REG SYSC_PMC_PCSR; // Peripheral Clock Status Register - AT91_REG Reserved14[1]; // - AT91_REG SYSC_PMC_MOR; // Main Oscillator Register - AT91_REG SYSC_PMC_MCFR; // Main Clock Frequency Register - AT91_REG Reserved15[1]; // - AT91_REG SYSC_PMC_PLLR; // PLL Register - AT91_REG SYSC_PMC_MCKR; // Master Clock Register - AT91_REG Reserved16[3]; // - AT91_REG SYSC_PMC_PCKR[8]; // Programmable Clock Register - AT91_REG SYSC_PMC_IER; // Interrupt Enable Register - AT91_REG SYSC_PMC_IDR; // Interrupt Disable Register - AT91_REG SYSC_PMC_SR; // Status Register - AT91_REG SYSC_PMC_IMR; // Interrupt Mask Register - AT91_REG Reserved17[36]; // - AT91_REG SYSC_RSTC_RCR; // Reset Control Register - AT91_REG SYSC_RSTC_RSR; // Reset Status Register - AT91_REG SYSC_RSTC_RMR; // Reset Mode Register - AT91_REG Reserved18[5]; // - AT91_REG SYSC_RTTC_RTMR; // Real-time Mode Register - AT91_REG SYSC_RTTC_RTAR; // Real-time Alarm Register - AT91_REG SYSC_RTTC_RTVR; // Real-time Value Register - AT91_REG SYSC_RTTC_RTSR; // Real-time Status Register - AT91_REG SYSC_PITC_PIMR; // Period Interval Mode Register - AT91_REG SYSC_PITC_PISR; // Period Interval Status Register - AT91_REG SYSC_PITC_PIVR; // Period Interval Value Register - AT91_REG SYSC_PITC_PIIR; // Period Interval Image Register - AT91_REG SYSC_WDTC_WDCR; // Watchdog Control Register - AT91_REG SYSC_WDTC_WDMR; // Watchdog Mode Register - AT91_REG SYSC_WDTC_WDSR; // Watchdog Status Register - AT91_REG Reserved19[5]; // - AT91_REG SYSC_SYSC_VRPM; // Voltage Regulator Power Mode Register -} AT91S_SYSC, *AT91PS_SYSC; +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR System Peripherals */ +/* ***************************************************************************** */ +typedef struct _AT91S_SYSC +{ + AT91_REG SYSC_AIC_SMR[ 32 ]; /* Source Mode Register */ + AT91_REG SYSC_AIC_SVR[ 32 ]; /* Source Vector Register */ + AT91_REG SYSC_AIC_IVR; /* IRQ Vector Register */ + AT91_REG SYSC_AIC_FVR; /* FIQ Vector Register */ + AT91_REG SYSC_AIC_ISR; /* Interrupt Status Register */ + AT91_REG SYSC_AIC_IPR; /* Interrupt Pending Register */ + AT91_REG SYSC_AIC_IMR; /* Interrupt Mask Register */ + AT91_REG SYSC_AIC_CISR; /* Core Interrupt Status Register */ + AT91_REG Reserved0[ 2 ]; /* */ + AT91_REG SYSC_AIC_IECR; /* Interrupt Enable Command Register */ + AT91_REG SYSC_AIC_IDCR; /* Interrupt Disable Command Register */ + AT91_REG SYSC_AIC_ICCR; /* Interrupt Clear Command Register */ + AT91_REG SYSC_AIC_ISCR; /* Interrupt Set Command Register */ + AT91_REG SYSC_AIC_EOICR; /* End of Interrupt Command Register */ + AT91_REG SYSC_AIC_SPU; /* Spurious Vector Register */ + AT91_REG SYSC_AIC_DCR; /* Debug Control Register (Protect) */ + AT91_REG Reserved1[ 1 ]; /* */ + AT91_REG SYSC_AIC_FFER; /* Fast Forcing Enable Register */ + AT91_REG SYSC_AIC_FFDR; /* Fast Forcing Disable Register */ + AT91_REG SYSC_AIC_FFSR; /* Fast Forcing Status Register */ + AT91_REG Reserved2[ 45 ]; /* */ + AT91_REG SYSC_DBGU_CR; /* Control Register */ + AT91_REG SYSC_DBGU_MR; /* Mode Register */ + AT91_REG SYSC_DBGU_IER; /* Interrupt Enable Register */ + AT91_REG SYSC_DBGU_IDR; /* Interrupt Disable Register */ + AT91_REG SYSC_DBGU_IMR; /* Interrupt Mask Register */ + AT91_REG SYSC_DBGU_CSR; /* Channel Status Register */ + AT91_REG SYSC_DBGU_RHR; /* Receiver Holding Register */ + AT91_REG SYSC_DBGU_THR; /* Transmitter Holding Register */ + AT91_REG SYSC_DBGU_BRGR; /* Baud Rate Generator Register */ + AT91_REG Reserved3[ 7 ]; /* */ + AT91_REG SYSC_DBGU_C1R; /* Chip ID1 Register */ + AT91_REG SYSC_DBGU_C2R; /* Chip ID2 Register */ + AT91_REG SYSC_DBGU_FNTR; /* Force NTRST Register */ + AT91_REG Reserved4[ 45 ]; /* */ + AT91_REG SYSC_DBGU_RPR; /* Receive Pointer Register */ + AT91_REG SYSC_DBGU_RCR; /* Receive Counter Register */ + AT91_REG SYSC_DBGU_TPR; /* Transmit Pointer Register */ + AT91_REG SYSC_DBGU_TCR; /* Transmit Counter Register */ + AT91_REG SYSC_DBGU_RNPR; /* Receive Next Pointer Register */ + AT91_REG SYSC_DBGU_RNCR; /* Receive Next Counter Register */ + AT91_REG SYSC_DBGU_TNPR; /* Transmit Next Pointer Register */ + AT91_REG SYSC_DBGU_TNCR; /* Transmit Next Counter Register */ + AT91_REG SYSC_DBGU_PTCR; /* PDC Transfer Control Register */ + AT91_REG SYSC_DBGU_PTSR; /* PDC Transfer Status Register */ + AT91_REG Reserved5[ 54 ]; /* */ + AT91_REG SYSC_PIOA_PER; /* PIO Enable Register */ + AT91_REG SYSC_PIOA_PDR; /* PIO Disable Register */ + AT91_REG SYSC_PIOA_PSR; /* PIO Status Register */ + AT91_REG Reserved6[ 1 ]; /* */ + AT91_REG SYSC_PIOA_OER; /* Output Enable Register */ + AT91_REG SYSC_PIOA_ODR; /* Output Disable Registerr */ + AT91_REG SYSC_PIOA_OSR; /* Output Status Register */ + AT91_REG Reserved7[ 1 ]; /* */ + AT91_REG SYSC_PIOA_IFER; /* Input Filter Enable Register */ + AT91_REG SYSC_PIOA_IFDR; /* Input Filter Disable Register */ + AT91_REG SYSC_PIOA_IFSR; /* Input Filter Status Register */ + AT91_REG Reserved8[ 1 ]; /* */ + AT91_REG SYSC_PIOA_SODR; /* Set Output Data Register */ + AT91_REG SYSC_PIOA_CODR; /* Clear Output Data Register */ + AT91_REG SYSC_PIOA_ODSR; /* Output Data Status Register */ + AT91_REG SYSC_PIOA_PDSR; /* Pin Data Status Register */ + AT91_REG SYSC_PIOA_IER; /* Interrupt Enable Register */ + AT91_REG SYSC_PIOA_IDR; /* Interrupt Disable Register */ + AT91_REG SYSC_PIOA_IMR; /* Interrupt Mask Register */ + AT91_REG SYSC_PIOA_ISR; /* Interrupt Status Register */ + AT91_REG SYSC_PIOA_MDER; /* Multi-driver Enable Register */ + AT91_REG SYSC_PIOA_MDDR; /* Multi-driver Disable Register */ + AT91_REG SYSC_PIOA_MDSR; /* Multi-driver Status Register */ + AT91_REG Reserved9[ 1 ]; /* */ + AT91_REG SYSC_PIOA_PPUDR; /* Pull-up Disable Register */ + AT91_REG SYSC_PIOA_PPUER; /* Pull-up Enable Register */ + AT91_REG SYSC_PIOA_PPUSR; /* Pad Pull-up Status Register */ + AT91_REG Reserved10[ 1 ]; /* */ + AT91_REG SYSC_PIOA_ASR; /* Select A Register */ + AT91_REG SYSC_PIOA_BSR; /* Select B Register */ + AT91_REG SYSC_PIOA_ABSR; /* AB Select Status Register */ + AT91_REG Reserved11[ 9 ]; /* */ + AT91_REG SYSC_PIOA_OWER; /* Output Write Enable Register */ + AT91_REG SYSC_PIOA_OWDR; /* Output Write Disable Register */ + AT91_REG SYSC_PIOA_OWSR; /* Output Write Status Register */ + AT91_REG Reserved12[ 469 ]; /* */ + AT91_REG SYSC_PMC_SCER; /* System Clock Enable Register */ + AT91_REG SYSC_PMC_SCDR; /* System Clock Disable Register */ + AT91_REG SYSC_PMC_SCSR; /* System Clock Status Register */ + AT91_REG Reserved13[ 1 ]; /* */ + AT91_REG SYSC_PMC_PCER; /* Peripheral Clock Enable Register */ + AT91_REG SYSC_PMC_PCDR; /* Peripheral Clock Disable Register */ + AT91_REG SYSC_PMC_PCSR; /* Peripheral Clock Status Register */ + AT91_REG Reserved14[ 1 ]; /* */ + AT91_REG SYSC_PMC_MOR; /* Main Oscillator Register */ + AT91_REG SYSC_PMC_MCFR; /* Main Clock Frequency Register */ + AT91_REG Reserved15[ 1 ]; /* */ + AT91_REG SYSC_PMC_PLLR; /* PLL Register */ + AT91_REG SYSC_PMC_MCKR; /* Master Clock Register */ + AT91_REG Reserved16[ 3 ]; /* */ + AT91_REG SYSC_PMC_PCKR[ 8 ]; /* Programmable Clock Register */ + AT91_REG SYSC_PMC_IER; /* Interrupt Enable Register */ + AT91_REG SYSC_PMC_IDR; /* Interrupt Disable Register */ + AT91_REG SYSC_PMC_SR; /* Status Register */ + AT91_REG SYSC_PMC_IMR; /* Interrupt Mask Register */ + AT91_REG Reserved17[ 36 ]; /* */ + AT91_REG SYSC_RSTC_RCR; /* Reset Control Register */ + AT91_REG SYSC_RSTC_RSR; /* Reset Status Register */ + AT91_REG SYSC_RSTC_RMR; /* Reset Mode Register */ + AT91_REG Reserved18[ 5 ]; /* */ + AT91_REG SYSC_RTTC_RTMR; /* Real-time Mode Register */ + AT91_REG SYSC_RTTC_RTAR; /* Real-time Alarm Register */ + AT91_REG SYSC_RTTC_RTVR; /* Real-time Value Register */ + AT91_REG SYSC_RTTC_RTSR; /* Real-time Status Register */ + AT91_REG SYSC_PITC_PIMR; /* Period Interval Mode Register */ + AT91_REG SYSC_PITC_PISR; /* Period Interval Status Register */ + AT91_REG SYSC_PITC_PIVR; /* Period Interval Value Register */ + AT91_REG SYSC_PITC_PIIR; /* Period Interval Image Register */ + AT91_REG SYSC_WDTC_WDCR; /* Watchdog Control Register */ + AT91_REG SYSC_WDTC_WDMR; /* Watchdog Mode Register */ + AT91_REG SYSC_WDTC_WDSR; /* Watchdog Status Register */ + AT91_REG Reserved19[ 5 ]; /* */ + AT91_REG SYSC_SYSC_VRPM; /* Voltage Regulator Power Mode Register */ +} AT91S_SYSC, * AT91PS_SYSC; -// -------- VRPM : (SYSC Offset: 0xd60) Voltage Regulator Power Mode Register -------- -#define AT91C_SYSC_PSTDBY ((unsigned int) 0x1 << 0) // (SYSC) Voltage Regulator Power Mode +/* -------- VRPM : (SYSC Offset: 0xd60) Voltage Regulator Power Mode Register -------- */ +#define AT91C_SYSC_PSTDBY ( ( unsigned int ) 0x1 << 0 ) /* (SYSC) Voltage Regulator Power Mode */ -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Advanced Interrupt Controller -// ***************************************************************************** -typedef struct _AT91S_AIC { - AT91_REG AIC_SMR[32]; // Source Mode Register - AT91_REG AIC_SVR[32]; // Source Vector Register - AT91_REG AIC_IVR; // IRQ Vector Register - AT91_REG AIC_FVR; // FIQ Vector Register - AT91_REG AIC_ISR; // Interrupt Status Register - AT91_REG AIC_IPR; // Interrupt Pending Register - AT91_REG AIC_IMR; // Interrupt Mask Register - AT91_REG AIC_CISR; // Core Interrupt Status Register - AT91_REG Reserved0[2]; // - AT91_REG AIC_IECR; // Interrupt Enable Command Register - AT91_REG AIC_IDCR; // Interrupt Disable Command Register - AT91_REG AIC_ICCR; // Interrupt Clear Command Register - AT91_REG AIC_ISCR; // Interrupt Set Command Register - AT91_REG AIC_EOICR; // End of Interrupt Command Register - AT91_REG AIC_SPU; // Spurious Vector Register - AT91_REG AIC_DCR; // Debug Control Register (Protect) - AT91_REG Reserved1[1]; // - AT91_REG AIC_FFER; // Fast Forcing Enable Register - AT91_REG AIC_FFDR; // Fast Forcing Disable Register - AT91_REG AIC_FFSR; // Fast Forcing Status Register -} AT91S_AIC, *AT91PS_AIC; +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR Advanced Interrupt Controller */ +/* ***************************************************************************** */ +typedef struct _AT91S_AIC +{ + AT91_REG AIC_SMR[ 32 ]; /* Source Mode Register */ + AT91_REG AIC_SVR[ 32 ]; /* Source Vector Register */ + AT91_REG AIC_IVR; /* IRQ Vector Register */ + AT91_REG AIC_FVR; /* FIQ Vector Register */ + AT91_REG AIC_ISR; /* Interrupt Status Register */ + AT91_REG AIC_IPR; /* Interrupt Pending Register */ + AT91_REG AIC_IMR; /* Interrupt Mask Register */ + AT91_REG AIC_CISR; /* Core Interrupt Status Register */ + AT91_REG Reserved0[ 2 ]; /* */ + AT91_REG AIC_IECR; /* Interrupt Enable Command Register */ + AT91_REG AIC_IDCR; /* Interrupt Disable Command Register */ + AT91_REG AIC_ICCR; /* Interrupt Clear Command Register */ + AT91_REG AIC_ISCR; /* Interrupt Set Command Register */ + AT91_REG AIC_EOICR; /* End of Interrupt Command Register */ + AT91_REG AIC_SPU; /* Spurious Vector Register */ + AT91_REG AIC_DCR; /* Debug Control Register (Protect) */ + AT91_REG Reserved1[ 1 ]; /* */ + AT91_REG AIC_FFER; /* Fast Forcing Enable Register */ + AT91_REG AIC_FFDR; /* Fast Forcing Disable Register */ + AT91_REG AIC_FFSR; /* Fast Forcing Status Register */ +} AT91S_AIC, * AT91PS_AIC; -// -------- AIC_SMR : (AIC Offset: 0x0) Control Register -------- -#define AT91C_AIC_PRIOR ((unsigned int) 0x7 << 0) // (AIC) Priority Level -#define AT91C_AIC_PRIOR_LOWEST ((unsigned int) 0x0) // (AIC) Lowest priority level -#define AT91C_AIC_PRIOR_HIGHEST ((unsigned int) 0x7) // (AIC) Highest priority level -#define AT91C_AIC_SRCTYPE ((unsigned int) 0x3 << 5) // (AIC) Interrupt Source Type -#define AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE ((unsigned int) 0x0 << 5) // (AIC) Internal Sources Code Label Level Sensitive -#define AT91C_AIC_SRCTYPE_INT_EDGE_TRIGGERED ((unsigned int) 0x1 << 5) // (AIC) Internal Sources Code Label Edge triggered -#define AT91C_AIC_SRCTYPE_EXT_HIGH_LEVEL ((unsigned int) 0x2 << 5) // (AIC) External Sources Code Label High-level Sensitive -#define AT91C_AIC_SRCTYPE_EXT_POSITIVE_EDGE ((unsigned int) 0x3 << 5) // (AIC) External Sources Code Label Positive Edge triggered -// -------- AIC_CISR : (AIC Offset: 0x114) AIC Core Interrupt Status Register -------- -#define AT91C_AIC_NFIQ ((unsigned int) 0x1 << 0) // (AIC) NFIQ Status -#define AT91C_AIC_NIRQ ((unsigned int) 0x1 << 1) // (AIC) NIRQ Status -// -------- AIC_DCR : (AIC Offset: 0x138) AIC Debug Control Register (Protect) -------- -#define AT91C_AIC_DCR_PROT ((unsigned int) 0x1 << 0) // (AIC) Protection Mode -#define AT91C_AIC_DCR_GMSK ((unsigned int) 0x1 << 1) // (AIC) General Mask +/* -------- AIC_SMR : (AIC Offset: 0x0) Control Register -------- */ +#define AT91C_AIC_PRIOR ( ( unsigned int ) 0x7 << 0 ) /* (AIC) Priority Level */ +#define AT91C_AIC_PRIOR_LOWEST ( ( unsigned int ) 0x0 ) /* (AIC) Lowest priority level */ +#define AT91C_AIC_PRIOR_HIGHEST ( ( unsigned int ) 0x7 ) /* (AIC) Highest priority level */ +#define AT91C_AIC_SRCTYPE ( ( unsigned int ) 0x3 << 5 ) /* (AIC) Interrupt Source Type */ +#define AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE ( ( unsigned int ) 0x0 << 5 ) /* (AIC) Internal Sources Code Label Level Sensitive */ +#define AT91C_AIC_SRCTYPE_INT_EDGE_TRIGGERED ( ( unsigned int ) 0x1 << 5 ) /* (AIC) Internal Sources Code Label Edge triggered */ +#define AT91C_AIC_SRCTYPE_EXT_HIGH_LEVEL ( ( unsigned int ) 0x2 << 5 ) /* (AIC) External Sources Code Label High-level Sensitive */ +#define AT91C_AIC_SRCTYPE_EXT_POSITIVE_EDGE ( ( unsigned int ) 0x3 << 5 ) /* (AIC) External Sources Code Label Positive Edge triggered */ +/* -------- AIC_CISR : (AIC Offset: 0x114) AIC Core Interrupt Status Register -------- */ +#define AT91C_AIC_NFIQ ( ( unsigned int ) 0x1 << 0 ) /* (AIC) NFIQ Status */ +#define AT91C_AIC_NIRQ ( ( unsigned int ) 0x1 << 1 ) /* (AIC) NIRQ Status */ +/* -------- AIC_DCR : (AIC Offset: 0x138) AIC Debug Control Register (Protect) -------- */ +#define AT91C_AIC_DCR_PROT ( ( unsigned int ) 0x1 << 0 ) /* (AIC) Protection Mode */ +#define AT91C_AIC_DCR_GMSK ( ( unsigned int ) 0x1 << 1 ) /* (AIC) General Mask */ -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Debug Unit -// ***************************************************************************** -typedef struct _AT91S_DBGU { - AT91_REG DBGU_CR; // Control Register - AT91_REG DBGU_MR; // Mode Register - AT91_REG DBGU_IER; // Interrupt Enable Register - AT91_REG DBGU_IDR; // Interrupt Disable Register - AT91_REG DBGU_IMR; // Interrupt Mask Register - AT91_REG DBGU_CSR; // Channel Status Register - AT91_REG DBGU_RHR; // Receiver Holding Register - AT91_REG DBGU_THR; // Transmitter Holding Register - AT91_REG DBGU_BRGR; // Baud Rate Generator Register - AT91_REG Reserved0[7]; // - AT91_REG DBGU_C1R; // Chip ID1 Register - AT91_REG DBGU_C2R; // Chip ID2 Register - AT91_REG DBGU_FNTR; // Force NTRST Register - AT91_REG Reserved1[45]; // - AT91_REG DBGU_RPR; // Receive Pointer Register - AT91_REG DBGU_RCR; // Receive Counter Register - AT91_REG DBGU_TPR; // Transmit Pointer Register - AT91_REG DBGU_TCR; // Transmit Counter Register - AT91_REG DBGU_RNPR; // Receive Next Pointer Register - AT91_REG DBGU_RNCR; // Receive Next Counter Register - AT91_REG DBGU_TNPR; // Transmit Next Pointer Register - AT91_REG DBGU_TNCR; // Transmit Next Counter Register - AT91_REG DBGU_PTCR; // PDC Transfer Control Register - AT91_REG DBGU_PTSR; // PDC Transfer Status Register -} AT91S_DBGU, *AT91PS_DBGU; +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR Debug Unit */ +/* ***************************************************************************** */ +typedef struct _AT91S_DBGU +{ + AT91_REG DBGU_CR; /* Control Register */ + AT91_REG DBGU_MR; /* Mode Register */ + AT91_REG DBGU_IER; /* Interrupt Enable Register */ + AT91_REG DBGU_IDR; /* Interrupt Disable Register */ + AT91_REG DBGU_IMR; /* Interrupt Mask Register */ + AT91_REG DBGU_CSR; /* Channel Status Register */ + AT91_REG DBGU_RHR; /* Receiver Holding Register */ + AT91_REG DBGU_THR; /* Transmitter Holding Register */ + AT91_REG DBGU_BRGR; /* Baud Rate Generator Register */ + AT91_REG Reserved0[ 7 ]; /* */ + AT91_REG DBGU_C1R; /* Chip ID1 Register */ + AT91_REG DBGU_C2R; /* Chip ID2 Register */ + AT91_REG DBGU_FNTR; /* Force NTRST Register */ + AT91_REG Reserved1[ 45 ]; /* */ + AT91_REG DBGU_RPR; /* Receive Pointer Register */ + AT91_REG DBGU_RCR; /* Receive Counter Register */ + AT91_REG DBGU_TPR; /* Transmit Pointer Register */ + AT91_REG DBGU_TCR; /* Transmit Counter Register */ + AT91_REG DBGU_RNPR; /* Receive Next Pointer Register */ + AT91_REG DBGU_RNCR; /* Receive Next Counter Register */ + AT91_REG DBGU_TNPR; /* Transmit Next Pointer Register */ + AT91_REG DBGU_TNCR; /* Transmit Next Counter Register */ + AT91_REG DBGU_PTCR; /* PDC Transfer Control Register */ + AT91_REG DBGU_PTSR; /* PDC Transfer Status Register */ +} AT91S_DBGU, * AT91PS_DBGU; -// -------- DBGU_CR : (DBGU Offset: 0x0) Debug Unit Control Register -------- -#define AT91C_US_RSTRX ((unsigned int) 0x1 << 2) // (DBGU) Reset Receiver -#define AT91C_US_RSTTX ((unsigned int) 0x1 << 3) // (DBGU) Reset Transmitter -#define AT91C_US_RXEN ((unsigned int) 0x1 << 4) // (DBGU) Receiver Enable -#define AT91C_US_RXDIS ((unsigned int) 0x1 << 5) // (DBGU) Receiver Disable -#define AT91C_US_TXEN ((unsigned int) 0x1 << 6) // (DBGU) Transmitter Enable -#define AT91C_US_TXDIS ((unsigned int) 0x1 << 7) // (DBGU) Transmitter Disable -// -------- DBGU_MR : (DBGU Offset: 0x4) Debug Unit Mode Register -------- -#define AT91C_US_PAR ((unsigned int) 0x7 << 9) // (DBGU) Parity type -#define AT91C_US_PAR_EVEN ((unsigned int) 0x0 << 9) // (DBGU) Even Parity -#define AT91C_US_PAR_ODD ((unsigned int) 0x1 << 9) // (DBGU) Odd Parity -#define AT91C_US_PAR_SPACE ((unsigned int) 0x2 << 9) // (DBGU) Parity forced to 0 (Space) -#define AT91C_US_PAR_MARK ((unsigned int) 0x3 << 9) // (DBGU) Parity forced to 1 (Mark) -#define AT91C_US_PAR_NONE ((unsigned int) 0x4 << 9) // (DBGU) No Parity -#define AT91C_US_PAR_MULTI_DROP ((unsigned int) 0x6 << 9) // (DBGU) Multi-drop mode -#define AT91C_US_CHMODE ((unsigned int) 0x3 << 14) // (DBGU) Channel Mode -#define AT91C_US_CHMODE_NORMAL ((unsigned int) 0x0 << 14) // (DBGU) Normal Mode: The USART channel operates as an RX/TX USART. -#define AT91C_US_CHMODE_AUTO ((unsigned int) 0x1 << 14) // (DBGU) Automatic Echo: Receiver Data Input is connected to the TXD pin. -#define AT91C_US_CHMODE_LOCAL ((unsigned int) 0x2 << 14) // (DBGU) Local Loopback: Transmitter Output Signal is connected to Receiver Input Signal. -#define AT91C_US_CHMODE_REMOTE ((unsigned int) 0x3 << 14) // (DBGU) Remote Loopback: RXD pin is internally connected to TXD pin. -// -------- DBGU_IER : (DBGU Offset: 0x8) Debug Unit Interrupt Enable Register -------- -#define AT91C_US_RXRDY ((unsigned int) 0x1 << 0) // (DBGU) RXRDY Interrupt -#define AT91C_US_TXRDY ((unsigned int) 0x1 << 1) // (DBGU) TXRDY Interrupt -#define AT91C_US_ENDRX ((unsigned int) 0x1 << 3) // (DBGU) End of Receive Transfer Interrupt -#define AT91C_US_ENDTX ((unsigned int) 0x1 << 4) // (DBGU) End of Transmit Interrupt -#define AT91C_US_OVRE ((unsigned int) 0x1 << 5) // (DBGU) Overrun Interrupt -#define AT91C_US_FRAME ((unsigned int) 0x1 << 6) // (DBGU) Framing Error Interrupt -#define AT91C_US_PARE ((unsigned int) 0x1 << 7) // (DBGU) Parity Error Interrupt -#define AT91C_US_TXEMPTY ((unsigned int) 0x1 << 9) // (DBGU) TXEMPTY Interrupt -#define AT91C_US_TXBUFE ((unsigned int) 0x1 << 11) // (DBGU) TXBUFE Interrupt -#define AT91C_US_RXBUFF ((unsigned int) 0x1 << 12) // (DBGU) RXBUFF Interrupt -#define AT91C_US_COMM_TX ((unsigned int) 0x1 << 30) // (DBGU) COMM_TX Interrupt -#define AT91C_US_COMM_RX ((unsigned int) 0x1 << 31) // (DBGU) COMM_RX Interrupt -// -------- DBGU_IDR : (DBGU Offset: 0xc) Debug Unit Interrupt Disable Register -------- -// -------- DBGU_IMR : (DBGU Offset: 0x10) Debug Unit Interrupt Mask Register -------- -// -------- DBGU_CSR : (DBGU Offset: 0x14) Debug Unit Channel Status Register -------- -// -------- DBGU_FNTR : (DBGU Offset: 0x48) Debug Unit FORCE_NTRST Register -------- -#define AT91C_US_FORCE_NTRST ((unsigned int) 0x1 << 0) // (DBGU) Force NTRST in JTAG +/* -------- DBGU_CR : (DBGU Offset: 0x0) Debug Unit Control Register -------- */ +#define AT91C_US_RSTRX ( ( unsigned int ) 0x1 << 2 ) /* (DBGU) Reset Receiver */ +#define AT91C_US_RSTTX ( ( unsigned int ) 0x1 << 3 ) /* (DBGU) Reset Transmitter */ +#define AT91C_US_RXEN ( ( unsigned int ) 0x1 << 4 ) /* (DBGU) Receiver Enable */ +#define AT91C_US_RXDIS ( ( unsigned int ) 0x1 << 5 ) /* (DBGU) Receiver Disable */ +#define AT91C_US_TXEN ( ( unsigned int ) 0x1 << 6 ) /* (DBGU) Transmitter Enable */ +#define AT91C_US_TXDIS ( ( unsigned int ) 0x1 << 7 ) /* (DBGU) Transmitter Disable */ +/* -------- DBGU_MR : (DBGU Offset: 0x4) Debug Unit Mode Register -------- */ +#define AT91C_US_PAR ( ( unsigned int ) 0x7 << 9 ) /* (DBGU) Parity type */ +#define AT91C_US_PAR_EVEN ( ( unsigned int ) 0x0 << 9 ) /* (DBGU) Even Parity */ +#define AT91C_US_PAR_ODD ( ( unsigned int ) 0x1 << 9 ) /* (DBGU) Odd Parity */ +#define AT91C_US_PAR_SPACE ( ( unsigned int ) 0x2 << 9 ) /* (DBGU) Parity forced to 0 (Space) */ +#define AT91C_US_PAR_MARK ( ( unsigned int ) 0x3 << 9 ) /* (DBGU) Parity forced to 1 (Mark) */ +#define AT91C_US_PAR_NONE ( ( unsigned int ) 0x4 << 9 ) /* (DBGU) No Parity */ +#define AT91C_US_PAR_MULTI_DROP ( ( unsigned int ) 0x6 << 9 ) /* (DBGU) Multi-drop mode */ +#define AT91C_US_CHMODE ( ( unsigned int ) 0x3 << 14 ) /* (DBGU) Channel Mode */ +#define AT91C_US_CHMODE_NORMAL ( ( unsigned int ) 0x0 << 14 ) /* (DBGU) Normal Mode: The USART channel operates as an RX/TX USART. */ +#define AT91C_US_CHMODE_AUTO ( ( unsigned int ) 0x1 << 14 ) /* (DBGU) Automatic Echo: Receiver Data Input is connected to the TXD pin. */ +#define AT91C_US_CHMODE_LOCAL ( ( unsigned int ) 0x2 << 14 ) /* (DBGU) Local Loopback: Transmitter Output Signal is connected to Receiver Input Signal. */ +#define AT91C_US_CHMODE_REMOTE ( ( unsigned int ) 0x3 << 14 ) /* (DBGU) Remote Loopback: RXD pin is internally connected to TXD pin. */ +/* -------- DBGU_IER : (DBGU Offset: 0x8) Debug Unit Interrupt Enable Register -------- */ +#define AT91C_US_RXRDY ( ( unsigned int ) 0x1 << 0 ) /* (DBGU) RXRDY Interrupt */ +#define AT91C_US_TXRDY ( ( unsigned int ) 0x1 << 1 ) /* (DBGU) TXRDY Interrupt */ +#define AT91C_US_ENDRX ( ( unsigned int ) 0x1 << 3 ) /* (DBGU) End of Receive Transfer Interrupt */ +#define AT91C_US_ENDTX ( ( unsigned int ) 0x1 << 4 ) /* (DBGU) End of Transmit Interrupt */ +#define AT91C_US_OVRE ( ( unsigned int ) 0x1 << 5 ) /* (DBGU) Overrun Interrupt */ +#define AT91C_US_FRAME ( ( unsigned int ) 0x1 << 6 ) /* (DBGU) Framing Error Interrupt */ +#define AT91C_US_PARE ( ( unsigned int ) 0x1 << 7 ) /* (DBGU) Parity Error Interrupt */ +#define AT91C_US_TXEMPTY ( ( unsigned int ) 0x1 << 9 ) /* (DBGU) TXEMPTY Interrupt */ +#define AT91C_US_TXBUFE ( ( unsigned int ) 0x1 << 11 ) /* (DBGU) TXBUFE Interrupt */ +#define AT91C_US_RXBUFF ( ( unsigned int ) 0x1 << 12 ) /* (DBGU) RXBUFF Interrupt */ +#define AT91C_US_COMM_TX ( ( unsigned int ) 0x1 << 30 ) /* (DBGU) COMM_TX Interrupt */ +#define AT91C_US_COMM_RX ( ( unsigned int ) 0x1 << 31 ) /* (DBGU) COMM_RX Interrupt */ +/* -------- DBGU_IDR : (DBGU Offset: 0xc) Debug Unit Interrupt Disable Register -------- */ +/* -------- DBGU_IMR : (DBGU Offset: 0x10) Debug Unit Interrupt Mask Register -------- */ +/* -------- DBGU_CSR : (DBGU Offset: 0x14) Debug Unit Channel Status Register -------- */ +/* -------- DBGU_FNTR : (DBGU Offset: 0x48) Debug Unit FORCE_NTRST Register -------- */ +#define AT91C_US_FORCE_NTRST ( ( unsigned int ) 0x1 << 0 ) /* (DBGU) Force NTRST in JTAG */ -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Peripheral Data Controller -// ***************************************************************************** -typedef struct _AT91S_PDC { - AT91_REG PDC_RPR; // Receive Pointer Register - AT91_REG PDC_RCR; // Receive Counter Register - AT91_REG PDC_TPR; // Transmit Pointer Register - AT91_REG PDC_TCR; // Transmit Counter Register - AT91_REG PDC_RNPR; // Receive Next Pointer Register - AT91_REG PDC_RNCR; // Receive Next Counter Register - AT91_REG PDC_TNPR; // Transmit Next Pointer Register - AT91_REG PDC_TNCR; // Transmit Next Counter Register - AT91_REG PDC_PTCR; // PDC Transfer Control Register - AT91_REG PDC_PTSR; // PDC Transfer Status Register -} AT91S_PDC, *AT91PS_PDC; +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR Peripheral Data Controller */ +/* ***************************************************************************** */ +typedef struct _AT91S_PDC +{ + AT91_REG PDC_RPR; /* Receive Pointer Register */ + AT91_REG PDC_RCR; /* Receive Counter Register */ + AT91_REG PDC_TPR; /* Transmit Pointer Register */ + AT91_REG PDC_TCR; /* Transmit Counter Register */ + AT91_REG PDC_RNPR; /* Receive Next Pointer Register */ + AT91_REG PDC_RNCR; /* Receive Next Counter Register */ + AT91_REG PDC_TNPR; /* Transmit Next Pointer Register */ + AT91_REG PDC_TNCR; /* Transmit Next Counter Register */ + AT91_REG PDC_PTCR; /* PDC Transfer Control Register */ + AT91_REG PDC_PTSR; /* PDC Transfer Status Register */ +} AT91S_PDC, * AT91PS_PDC; -// -------- PDC_PTCR : (PDC Offset: 0x20) PDC Transfer Control Register -------- -#define AT91C_PDC_RXTEN ((unsigned int) 0x1 << 0) // (PDC) Receiver Transfer Enable -#define AT91C_PDC_RXTDIS ((unsigned int) 0x1 << 1) // (PDC) Receiver Transfer Disable -#define AT91C_PDC_TXTEN ((unsigned int) 0x1 << 8) // (PDC) Transmitter Transfer Enable -#define AT91C_PDC_TXTDIS ((unsigned int) 0x1 << 9) // (PDC) Transmitter Transfer Disable -// -------- PDC_PTSR : (PDC Offset: 0x24) PDC Transfer Status Register -------- +/* -------- PDC_PTCR : (PDC Offset: 0x20) PDC Transfer Control Register -------- */ +#define AT91C_PDC_RXTEN ( ( unsigned int ) 0x1 << 0 ) /* (PDC) Receiver Transfer Enable */ +#define AT91C_PDC_RXTDIS ( ( unsigned int ) 0x1 << 1 ) /* (PDC) Receiver Transfer Disable */ +#define AT91C_PDC_TXTEN ( ( unsigned int ) 0x1 << 8 ) /* (PDC) Transmitter Transfer Enable */ +#define AT91C_PDC_TXTDIS ( ( unsigned int ) 0x1 << 9 ) /* (PDC) Transmitter Transfer Disable */ +/* -------- PDC_PTSR : (PDC Offset: 0x24) PDC Transfer Status Register -------- */ -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Parallel Input Output Controler -// ***************************************************************************** -typedef struct _AT91S_PIO { - AT91_REG PIO_PER; // PIO Enable Register - AT91_REG PIO_PDR; // PIO Disable Register - AT91_REG PIO_PSR; // PIO Status Register - AT91_REG Reserved0[1]; // - AT91_REG PIO_OER; // Output Enable Register - AT91_REG PIO_ODR; // Output Disable Registerr - AT91_REG PIO_OSR; // Output Status Register - AT91_REG Reserved1[1]; // - AT91_REG PIO_IFER; // Input Filter Enable Register - AT91_REG PIO_IFDR; // Input Filter Disable Register - AT91_REG PIO_IFSR; // Input Filter Status Register - AT91_REG Reserved2[1]; // - AT91_REG PIO_SODR; // Set Output Data Register - AT91_REG PIO_CODR; // Clear Output Data Register - AT91_REG PIO_ODSR; // Output Data Status Register - AT91_REG PIO_PDSR; // Pin Data Status Register - AT91_REG PIO_IER; // Interrupt Enable Register - AT91_REG PIO_IDR; // Interrupt Disable Register - AT91_REG PIO_IMR; // Interrupt Mask Register - AT91_REG PIO_ISR; // Interrupt Status Register - AT91_REG PIO_MDER; // Multi-driver Enable Register - AT91_REG PIO_MDDR; // Multi-driver Disable Register - AT91_REG PIO_MDSR; // Multi-driver Status Register - AT91_REG Reserved3[1]; // - AT91_REG PIO_PPUDR; // Pull-up Disable Register - AT91_REG PIO_PPUER; // Pull-up Enable Register - AT91_REG PIO_PPUSR; // Pad Pull-up Status Register - AT91_REG Reserved4[1]; // - AT91_REG PIO_ASR; // Select A Register - AT91_REG PIO_BSR; // Select B Register - AT91_REG PIO_ABSR; // AB Select Status Register - AT91_REG Reserved5[9]; // - AT91_REG PIO_OWER; // Output Write Enable Register - AT91_REG PIO_OWDR; // Output Write Disable Register - AT91_REG PIO_OWSR; // Output Write Status Register -} AT91S_PIO, *AT91PS_PIO; +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR Parallel Input Output Controller */ +/* ***************************************************************************** */ +typedef struct _AT91S_PIO +{ + AT91_REG PIO_PER; /* PIO Enable Register */ + AT91_REG PIO_PDR; /* PIO Disable Register */ + AT91_REG PIO_PSR; /* PIO Status Register */ + AT91_REG Reserved0[ 1 ]; /* */ + AT91_REG PIO_OER; /* Output Enable Register */ + AT91_REG PIO_ODR; /* Output Disable Registerr */ + AT91_REG PIO_OSR; /* Output Status Register */ + AT91_REG Reserved1[ 1 ]; /* */ + AT91_REG PIO_IFER; /* Input Filter Enable Register */ + AT91_REG PIO_IFDR; /* Input Filter Disable Register */ + AT91_REG PIO_IFSR; /* Input Filter Status Register */ + AT91_REG Reserved2[ 1 ]; /* */ + AT91_REG PIO_SODR; /* Set Output Data Register */ + AT91_REG PIO_CODR; /* Clear Output Data Register */ + AT91_REG PIO_ODSR; /* Output Data Status Register */ + AT91_REG PIO_PDSR; /* Pin Data Status Register */ + AT91_REG PIO_IER; /* Interrupt Enable Register */ + AT91_REG PIO_IDR; /* Interrupt Disable Register */ + AT91_REG PIO_IMR; /* Interrupt Mask Register */ + AT91_REG PIO_ISR; /* Interrupt Status Register */ + AT91_REG PIO_MDER; /* Multi-driver Enable Register */ + AT91_REG PIO_MDDR; /* Multi-driver Disable Register */ + AT91_REG PIO_MDSR; /* Multi-driver Status Register */ + AT91_REG Reserved3[ 1 ]; /* */ + AT91_REG PIO_PPUDR; /* Pull-up Disable Register */ + AT91_REG PIO_PPUER; /* Pull-up Enable Register */ + AT91_REG PIO_PPUSR; /* Pad Pull-up Status Register */ + AT91_REG Reserved4[ 1 ]; /* */ + AT91_REG PIO_ASR; /* Select A Register */ + AT91_REG PIO_BSR; /* Select B Register */ + AT91_REG PIO_ABSR; /* AB Select Status Register */ + AT91_REG Reserved5[ 9 ]; /* */ + AT91_REG PIO_OWER; /* Output Write Enable Register */ + AT91_REG PIO_OWDR; /* Output Write Disable Register */ + AT91_REG PIO_OWSR; /* Output Write Status Register */ +} AT91S_PIO, * AT91PS_PIO; -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Clock Generator Controler -// ***************************************************************************** -typedef struct _AT91S_CKGR { - AT91_REG CKGR_MOR; // Main Oscillator Register - AT91_REG CKGR_MCFR; // Main Clock Frequency Register - AT91_REG Reserved0[1]; // - AT91_REG CKGR_PLLR; // PLL Register -} AT91S_CKGR, *AT91PS_CKGR; +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR Clock Generator Controller */ +/* ***************************************************************************** */ +typedef struct _AT91S_CKGR +{ + AT91_REG CKGR_MOR; /* Main Oscillator Register */ + AT91_REG CKGR_MCFR; /* Main Clock Frequency Register */ + AT91_REG Reserved0[ 1 ]; /* */ + AT91_REG CKGR_PLLR; /* PLL Register */ +} AT91S_CKGR, * AT91PS_CKGR; -// -------- CKGR_MOR : (CKGR Offset: 0x0) Main Oscillator Register -------- -#define AT91C_CKGR_MOSCEN ((unsigned int) 0x1 << 0) // (CKGR) Main Oscillator Enable -#define AT91C_CKGR_OSCBYPASS ((unsigned int) 0x1 << 1) // (CKGR) Main Oscillator Bypass -#define AT91C_CKGR_OSCOUNT ((unsigned int) 0xFF << 8) // (CKGR) Main Oscillator Start-up Time -// -------- CKGR_MCFR : (CKGR Offset: 0x4) Main Clock Frequency Register -------- -#define AT91C_CKGR_MAINF ((unsigned int) 0xFFFF << 0) // (CKGR) Main Clock Frequency -#define AT91C_CKGR_MAINRDY ((unsigned int) 0x1 << 16) // (CKGR) Main Clock Ready -// -------- CKGR_PLLR : (CKGR Offset: 0xc) PLL B Register -------- -#define AT91C_CKGR_DIV ((unsigned int) 0xFF << 0) // (CKGR) Divider Selected -#define AT91C_CKGR_DIV_0 ((unsigned int) 0x0) // (CKGR) Divider output is 0 -#define AT91C_CKGR_DIV_BYPASS ((unsigned int) 0x1) // (CKGR) Divider is bypassed -#define AT91C_CKGR_PLLCOUNT ((unsigned int) 0x3F << 8) // (CKGR) PLL Counter -#define AT91C_CKGR_OUT ((unsigned int) 0x3 << 14) // (CKGR) PLL Output Frequency Range -#define AT91C_CKGR_OUT_0 ((unsigned int) 0x0 << 14) // (CKGR) Please refer to the PLL datasheet -#define AT91C_CKGR_OUT_1 ((unsigned int) 0x1 << 14) // (CKGR) Please refer to the PLL datasheet -#define AT91C_CKGR_OUT_2 ((unsigned int) 0x2 << 14) // (CKGR) Please refer to the PLL datasheet -#define AT91C_CKGR_OUT_3 ((unsigned int) 0x3 << 14) // (CKGR) Please refer to the PLL datasheet -#define AT91C_CKGR_MUL ((unsigned int) 0x7FF << 16) // (CKGR) PLL Multiplier -#define AT91C_CKGR_USBDIV ((unsigned int) 0x3 << 28) // (CKGR) Divider for USB Clocks -#define AT91C_CKGR_USBDIV_0 ((unsigned int) 0x0 << 28) // (CKGR) Divider output is PLL clock output -#define AT91C_CKGR_USBDIV_1 ((unsigned int) 0x1 << 28) // (CKGR) Divider output is PLL clock output divided by 2 -#define AT91C_CKGR_USBDIV_2 ((unsigned int) 0x2 << 28) // (CKGR) Divider output is PLL clock output divided by 4 +/* -------- CKGR_MOR : (CKGR Offset: 0x0) Main Oscillator Register -------- */ +#define AT91C_CKGR_MOSCEN ( ( unsigned int ) 0x1 << 0 ) /* (CKGR) Main Oscillator Enable */ +#define AT91C_CKGR_OSCBYPASS ( ( unsigned int ) 0x1 << 1 ) /* (CKGR) Main Oscillator Bypass */ +#define AT91C_CKGR_OSCOUNT ( ( unsigned int ) 0xFF << 8 ) /* (CKGR) Main Oscillator Start-up Time */ +/* -------- CKGR_MCFR : (CKGR Offset: 0x4) Main Clock Frequency Register -------- */ +#define AT91C_CKGR_MAINF ( ( unsigned int ) 0xFFFF << 0 ) /* (CKGR) Main Clock Frequency */ +#define AT91C_CKGR_MAINRDY ( ( unsigned int ) 0x1 << 16 ) /* (CKGR) Main Clock Ready */ +/* -------- CKGR_PLLR : (CKGR Offset: 0xc) PLL B Register -------- */ +#define AT91C_CKGR_DIV ( ( unsigned int ) 0xFF << 0 ) /* (CKGR) Divider Selected */ +#define AT91C_CKGR_DIV_0 ( ( unsigned int ) 0x0 ) /* (CKGR) Divider output is 0 */ +#define AT91C_CKGR_DIV_BYPASS ( ( unsigned int ) 0x1 ) /* (CKGR) Divider is bypassed */ +#define AT91C_CKGR_PLLCOUNT ( ( unsigned int ) 0x3F << 8 ) /* (CKGR) PLL Counter */ +#define AT91C_CKGR_OUT ( ( unsigned int ) 0x3 << 14 ) /* (CKGR) PLL Output Frequency Range */ +#define AT91C_CKGR_OUT_0 ( ( unsigned int ) 0x0 << 14 ) /* (CKGR) Please refer to the PLL datasheet */ +#define AT91C_CKGR_OUT_1 ( ( unsigned int ) 0x1 << 14 ) /* (CKGR) Please refer to the PLL datasheet */ +#define AT91C_CKGR_OUT_2 ( ( unsigned int ) 0x2 << 14 ) /* (CKGR) Please refer to the PLL datasheet */ +#define AT91C_CKGR_OUT_3 ( ( unsigned int ) 0x3 << 14 ) /* (CKGR) Please refer to the PLL datasheet */ +#define AT91C_CKGR_MUL ( ( unsigned int ) 0x7FF << 16 ) /* (CKGR) PLL Multiplier */ +#define AT91C_CKGR_USBDIV ( ( unsigned int ) 0x3 << 28 ) /* (CKGR) Divider for USB Clocks */ +#define AT91C_CKGR_USBDIV_0 ( ( unsigned int ) 0x0 << 28 ) /* (CKGR) Divider output is PLL clock output */ +#define AT91C_CKGR_USBDIV_1 ( ( unsigned int ) 0x1 << 28 ) /* (CKGR) Divider output is PLL clock output divided by 2 */ +#define AT91C_CKGR_USBDIV_2 ( ( unsigned int ) 0x2 << 28 ) /* (CKGR) Divider output is PLL clock output divided by 4 */ -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Power Management Controler -// ***************************************************************************** -typedef struct _AT91S_PMC { - AT91_REG PMC_SCER; // System Clock Enable Register - AT91_REG PMC_SCDR; // System Clock Disable Register - AT91_REG PMC_SCSR; // System Clock Status Register - AT91_REG Reserved0[1]; // - AT91_REG PMC_PCER; // Peripheral Clock Enable Register - AT91_REG PMC_PCDR; // Peripheral Clock Disable Register - AT91_REG PMC_PCSR; // Peripheral Clock Status Register - AT91_REG Reserved1[1]; // - AT91_REG PMC_MOR; // Main Oscillator Register - AT91_REG PMC_MCFR; // Main Clock Frequency Register - AT91_REG Reserved2[1]; // - AT91_REG PMC_PLLR; // PLL Register - AT91_REG PMC_MCKR; // Master Clock Register - AT91_REG Reserved3[3]; // - AT91_REG PMC_PCKR[8]; // Programmable Clock Register - AT91_REG PMC_IER; // Interrupt Enable Register - AT91_REG PMC_IDR; // Interrupt Disable Register - AT91_REG PMC_SR; // Status Register - AT91_REG PMC_IMR; // Interrupt Mask Register -} AT91S_PMC, *AT91PS_PMC; +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR Power Management Controller */ +/* ***************************************************************************** */ +typedef struct _AT91S_PMC +{ + AT91_REG PMC_SCER; /* System Clock Enable Register */ + AT91_REG PMC_SCDR; /* System Clock Disable Register */ + AT91_REG PMC_SCSR; /* System Clock Status Register */ + AT91_REG Reserved0[ 1 ]; /* */ + AT91_REG PMC_PCER; /* Peripheral Clock Enable Register */ + AT91_REG PMC_PCDR; /* Peripheral Clock Disable Register */ + AT91_REG PMC_PCSR; /* Peripheral Clock Status Register */ + AT91_REG Reserved1[ 1 ]; /* */ + AT91_REG PMC_MOR; /* Main Oscillator Register */ + AT91_REG PMC_MCFR; /* Main Clock Frequency Register */ + AT91_REG Reserved2[ 1 ]; /* */ + AT91_REG PMC_PLLR; /* PLL Register */ + AT91_REG PMC_MCKR; /* Master Clock Register */ + AT91_REG Reserved3[ 3 ]; /* */ + AT91_REG PMC_PCKR[ 8 ]; /* Programmable Clock Register */ + AT91_REG PMC_IER; /* Interrupt Enable Register */ + AT91_REG PMC_IDR; /* Interrupt Disable Register */ + AT91_REG PMC_SR; /* Status Register */ + AT91_REG PMC_IMR; /* Interrupt Mask Register */ +} AT91S_PMC, * AT91PS_PMC; -// -------- PMC_SCER : (PMC Offset: 0x0) System Clock Enable Register -------- -#define AT91C_PMC_PCK ((unsigned int) 0x1 << 0) // (PMC) Processor Clock -#define AT91C_PMC_UDP ((unsigned int) 0x1 << 7) // (PMC) USB Device Port Clock -#define AT91C_PMC_PCK0 ((unsigned int) 0x1 << 8) // (PMC) Programmable Clock Output -#define AT91C_PMC_PCK1 ((unsigned int) 0x1 << 9) // (PMC) Programmable Clock Output -#define AT91C_PMC_PCK2 ((unsigned int) 0x1 << 10) // (PMC) Programmable Clock Output -#define AT91C_PMC_PCK3 ((unsigned int) 0x1 << 11) // (PMC) Programmable Clock Output -// -------- PMC_SCDR : (PMC Offset: 0x4) System Clock Disable Register -------- -// -------- PMC_SCSR : (PMC Offset: 0x8) System Clock Status Register -------- -// -------- CKGR_MOR : (PMC Offset: 0x20) Main Oscillator Register -------- -// -------- CKGR_MCFR : (PMC Offset: 0x24) Main Clock Frequency Register -------- -// -------- CKGR_PLLR : (PMC Offset: 0x2c) PLL B Register -------- -// -------- PMC_MCKR : (PMC Offset: 0x30) Master Clock Register -------- -#define AT91C_PMC_CSS ((unsigned int) 0x3 << 0) // (PMC) Programmable Clock Selection -#define AT91C_PMC_CSS_SLOW_CLK ((unsigned int) 0x0) // (PMC) Slow Clock is selected -#define AT91C_PMC_CSS_MAIN_CLK ((unsigned int) 0x1) // (PMC) Main Clock is selected -#define AT91C_PMC_CSS_PLL_CLK ((unsigned int) 0x3) // (PMC) Clock from PLL is selected -#define AT91C_PMC_PRES ((unsigned int) 0x7 << 2) // (PMC) Programmable Clock Prescaler -#define AT91C_PMC_PRES_CLK ((unsigned int) 0x0 << 2) // (PMC) Selected clock -#define AT91C_PMC_PRES_CLK_2 ((unsigned int) 0x1 << 2) // (PMC) Selected clock divided by 2 -#define AT91C_PMC_PRES_CLK_4 ((unsigned int) 0x2 << 2) // (PMC) Selected clock divided by 4 -#define AT91C_PMC_PRES_CLK_8 ((unsigned int) 0x3 << 2) // (PMC) Selected clock divided by 8 -#define AT91C_PMC_PRES_CLK_16 ((unsigned int) 0x4 << 2) // (PMC) Selected clock divided by 16 -#define AT91C_PMC_PRES_CLK_32 ((unsigned int) 0x5 << 2) // (PMC) Selected clock divided by 32 -#define AT91C_PMC_PRES_CLK_64 ((unsigned int) 0x6 << 2) // (PMC) Selected clock divided by 64 -// -------- PMC_PCKR : (PMC Offset: 0x40) Programmable Clock Register -------- -// -------- PMC_IER : (PMC Offset: 0x60) PMC Interrupt Enable Register -------- -#define AT91C_PMC_MOSCS ((unsigned int) 0x1 << 0) // (PMC) MOSC Status/Enable/Disable/Mask -#define AT91C_PMC_LOCK ((unsigned int) 0x1 << 2) // (PMC) PLL Status/Enable/Disable/Mask -#define AT91C_PMC_MCKRDY ((unsigned int) 0x1 << 3) // (PMC) MCK_RDY Status/Enable/Disable/Mask -#define AT91C_PMC_PCK0RDY ((unsigned int) 0x1 << 8) // (PMC) PCK0_RDY Status/Enable/Disable/Mask -#define AT91C_PMC_PCK1RDY ((unsigned int) 0x1 << 9) // (PMC) PCK1_RDY Status/Enable/Disable/Mask -#define AT91C_PMC_PCK2RDY ((unsigned int) 0x1 << 10) // (PMC) PCK2_RDY Status/Enable/Disable/Mask -#define AT91C_PMC_PCK3RDY ((unsigned int) 0x1 << 11) // (PMC) PCK3_RDY Status/Enable/Disable/Mask -// -------- PMC_IDR : (PMC Offset: 0x64) PMC Interrupt Disable Register -------- -// -------- PMC_SR : (PMC Offset: 0x68) PMC Status Register -------- -// -------- PMC_IMR : (PMC Offset: 0x6c) PMC Interrupt Mask Register -------- +/* -------- PMC_SCER : (PMC Offset: 0x0) System Clock Enable Register -------- */ +#define AT91C_PMC_PCK ( ( unsigned int ) 0x1 << 0 ) /* (PMC) Processor Clock */ +#define AT91C_PMC_UDP ( ( unsigned int ) 0x1 << 7 ) /* (PMC) USB Device Port Clock */ +#define AT91C_PMC_PCK0 ( ( unsigned int ) 0x1 << 8 ) /* (PMC) Programmable Clock Output */ +#define AT91C_PMC_PCK1 ( ( unsigned int ) 0x1 << 9 ) /* (PMC) Programmable Clock Output */ +#define AT91C_PMC_PCK2 ( ( unsigned int ) 0x1 << 10 ) /* (PMC) Programmable Clock Output */ +#define AT91C_PMC_PCK3 ( ( unsigned int ) 0x1 << 11 ) /* (PMC) Programmable Clock Output */ +/* -------- PMC_SCDR : (PMC Offset: 0x4) System Clock Disable Register -------- */ +/* -------- PMC_SCSR : (PMC Offset: 0x8) System Clock Status Register -------- */ +/* -------- CKGR_MOR : (PMC Offset: 0x20) Main Oscillator Register -------- */ +/* -------- CKGR_MCFR : (PMC Offset: 0x24) Main Clock Frequency Register -------- */ +/* -------- CKGR_PLLR : (PMC Offset: 0x2c) PLL B Register -------- */ +/* -------- PMC_MCKR : (PMC Offset: 0x30) Master Clock Register -------- */ +#define AT91C_PMC_CSS ( ( unsigned int ) 0x3 << 0 ) /* (PMC) Programmable Clock Selection */ +#define AT91C_PMC_CSS_SLOW_CLK ( ( unsigned int ) 0x0 ) /* (PMC) Slow Clock is selected */ +#define AT91C_PMC_CSS_MAIN_CLK ( ( unsigned int ) 0x1 ) /* (PMC) Main Clock is selected */ +#define AT91C_PMC_CSS_PLL_CLK ( ( unsigned int ) 0x3 ) /* (PMC) Clock from PLL is selected */ +#define AT91C_PMC_PRES ( ( unsigned int ) 0x7 << 2 ) /* (PMC) Programmable Clock Prescaler */ +#define AT91C_PMC_PRES_CLK ( ( unsigned int ) 0x0 << 2 ) /* (PMC) Selected clock */ +#define AT91C_PMC_PRES_CLK_2 ( ( unsigned int ) 0x1 << 2 ) /* (PMC) Selected clock divided by 2 */ +#define AT91C_PMC_PRES_CLK_4 ( ( unsigned int ) 0x2 << 2 ) /* (PMC) Selected clock divided by 4 */ +#define AT91C_PMC_PRES_CLK_8 ( ( unsigned int ) 0x3 << 2 ) /* (PMC) Selected clock divided by 8 */ +#define AT91C_PMC_PRES_CLK_16 ( ( unsigned int ) 0x4 << 2 ) /* (PMC) Selected clock divided by 16 */ +#define AT91C_PMC_PRES_CLK_32 ( ( unsigned int ) 0x5 << 2 ) /* (PMC) Selected clock divided by 32 */ +#define AT91C_PMC_PRES_CLK_64 ( ( unsigned int ) 0x6 << 2 ) /* (PMC) Selected clock divided by 64 */ +/* -------- PMC_PCKR : (PMC Offset: 0x40) Programmable Clock Register -------- */ +/* -------- PMC_IER : (PMC Offset: 0x60) PMC Interrupt Enable Register -------- */ +#define AT91C_PMC_MOSCS ( ( unsigned int ) 0x1 << 0 ) /* (PMC) MOSC Status/Enable/Disable/Mask */ +#define AT91C_PMC_LOCK ( ( unsigned int ) 0x1 << 2 ) /* (PMC) PLL Status/Enable/Disable/Mask */ +#define AT91C_PMC_MCKRDY ( ( unsigned int ) 0x1 << 3 ) /* (PMC) MCK_RDY Status/Enable/Disable/Mask */ +#define AT91C_PMC_PCK0RDY ( ( unsigned int ) 0x1 << 8 ) /* (PMC) PCK0_RDY Status/Enable/Disable/Mask */ +#define AT91C_PMC_PCK1RDY ( ( unsigned int ) 0x1 << 9 ) /* (PMC) PCK1_RDY Status/Enable/Disable/Mask */ +#define AT91C_PMC_PCK2RDY ( ( unsigned int ) 0x1 << 10 ) /* (PMC) PCK2_RDY Status/Enable/Disable/Mask */ +#define AT91C_PMC_PCK3RDY ( ( unsigned int ) 0x1 << 11 ) /* (PMC) PCK3_RDY Status/Enable/Disable/Mask */ +/* -------- PMC_IDR : (PMC Offset: 0x64) PMC Interrupt Disable Register -------- */ +/* -------- PMC_SR : (PMC Offset: 0x68) PMC Status Register -------- */ +/* -------- PMC_IMR : (PMC Offset: 0x6c) PMC Interrupt Mask Register -------- */ -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Reset Controller Interface -// ***************************************************************************** -typedef struct _AT91S_RSTC { - AT91_REG RSTC_RCR; // Reset Control Register - AT91_REG RSTC_RSR; // Reset Status Register - AT91_REG RSTC_RMR; // Reset Mode Register -} AT91S_RSTC, *AT91PS_RSTC; +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR Reset Controller Interface */ +/* ***************************************************************************** */ +typedef struct _AT91S_RSTC +{ + AT91_REG RSTC_RCR; /* Reset Control Register */ + AT91_REG RSTC_RSR; /* Reset Status Register */ + AT91_REG RSTC_RMR; /* Reset Mode Register */ +} AT91S_RSTC, * AT91PS_RSTC; -// -------- SYSC_RCR : (RSTC Offset: 0x0) Reset Control Register -------- -#define AT91C_SYSC_PROCRST ((unsigned int) 0x1 << 0) // (RSTC) Processor Reset -#define AT91C_SYSC_ICERST ((unsigned int) 0x1 << 1) // (RSTC) ICE Interface Reset -#define AT91C_SYSC_PERRST ((unsigned int) 0x1 << 2) // (RSTC) Peripheral Reset -#define AT91C_SYSC_EXTRST ((unsigned int) 0x1 << 3) // (RSTC) External Reset -#define AT91C_SYSC_KEY ((unsigned int) 0xFF << 24) // (RSTC) Password -// -------- SYSC_RSR : (RSTC Offset: 0x4) Reset Status Register -------- -#define AT91C_SYSC_URSTS ((unsigned int) 0x1 << 0) // (RSTC) User Reset Status -#define AT91C_SYSC_BODSTS ((unsigned int) 0x1 << 1) // (RSTC) Brown-out Detection Status -#define AT91C_SYSC_RSTTYP ((unsigned int) 0x7 << 8) // (RSTC) Reset Type -#define AT91C_SYSC_RSTTYP_POWERUP ((unsigned int) 0x0 << 8) // (RSTC) Power-up Reset. VDDCORE rising. -#define AT91C_SYSC_RSTTYP_WATCHDOG ((unsigned int) 0x2 << 8) // (RSTC) Watchdog Reset. Watchdog overflow occured. -#define AT91C_SYSC_RSTTYP_SOFTWARE ((unsigned int) 0x3 << 8) // (RSTC) Software Reset. Processor reset required by the software. -#define AT91C_SYSC_RSTTYP_USER ((unsigned int) 0x4 << 8) // (RSTC) User Reset. NRST pin detected low. -#define AT91C_SYSC_RSTTYP_BROWNOUT ((unsigned int) 0x5 << 8) // (RSTC) Brown-out Reset. -#define AT91C_SYSC_NRSTL ((unsigned int) 0x1 << 16) // (RSTC) NRST pin level -#define AT91C_SYSC_SRCMP ((unsigned int) 0x1 << 17) // (RSTC) Software Reset Command in Progress. -// -------- SYSC_RMR : (RSTC Offset: 0x8) Reset Mode Register -------- -#define AT91C_SYSC_URSTEN ((unsigned int) 0x1 << 0) // (RSTC) User Reset Enable -#define AT91C_SYSC_URSTIEN ((unsigned int) 0x1 << 4) // (RSTC) User Reset Interrupt Enable -#define AT91C_SYSC_ERSTL ((unsigned int) 0xF << 8) // (RSTC) User Reset Enable -#define AT91C_SYSC_BODIEN ((unsigned int) 0x1 << 16) // (RSTC) Brown-out Detection Interrupt Enable +/* -------- SYSC_RCR : (RSTC Offset: 0x0) Reset Control Register -------- */ +#define AT91C_SYSC_PROCRST ( ( unsigned int ) 0x1 << 0 ) /* (RSTC) Processor Reset */ +#define AT91C_SYSC_ICERST ( ( unsigned int ) 0x1 << 1 ) /* (RSTC) ICE Interface Reset */ +#define AT91C_SYSC_PERRST ( ( unsigned int ) 0x1 << 2 ) /* (RSTC) Peripheral Reset */ +#define AT91C_SYSC_EXTRST ( ( unsigned int ) 0x1 << 3 ) /* (RSTC) External Reset */ +#define AT91C_SYSC_KEY ( ( unsigned int ) 0xFF << 24 ) /* (RSTC) Password */ +/* -------- SYSC_RSR : (RSTC Offset: 0x4) Reset Status Register -------- */ +#define AT91C_SYSC_URSTS ( ( unsigned int ) 0x1 << 0 ) /* (RSTC) User Reset Status */ +#define AT91C_SYSC_BODSTS ( ( unsigned int ) 0x1 << 1 ) /* (RSTC) Brown-out Detection Status */ +#define AT91C_SYSC_RSTTYP ( ( unsigned int ) 0x7 << 8 ) /* (RSTC) Reset Type */ +#define AT91C_SYSC_RSTTYP_POWERUP ( ( unsigned int ) 0x0 << 8 ) /* (RSTC) Power-up Reset. VDDCORE rising. */ +#define AT91C_SYSC_RSTTYP_WATCHDOG ( ( unsigned int ) 0x2 << 8 ) /* (RSTC) Watchdog Reset. Watchdog overflow occurred. */ +#define AT91C_SYSC_RSTTYP_SOFTWARE ( ( unsigned int ) 0x3 << 8 ) /* (RSTC) Software Reset. Processor reset required by the software. */ +#define AT91C_SYSC_RSTTYP_USER ( ( unsigned int ) 0x4 << 8 ) /* (RSTC) User Reset. NRST pin detected low. */ +#define AT91C_SYSC_RSTTYP_BROWNOUT ( ( unsigned int ) 0x5 << 8 ) /* (RSTC) Brown-out Reset. */ +#define AT91C_SYSC_NRSTL ( ( unsigned int ) 0x1 << 16 ) /* (RSTC) NRST pin level */ +#define AT91C_SYSC_SRCMP ( ( unsigned int ) 0x1 << 17 ) /* (RSTC) Software Reset Command in Progress. */ +/* -------- SYSC_RMR : (RSTC Offset: 0x8) Reset Mode Register -------- */ +#define AT91C_SYSC_URSTEN ( ( unsigned int ) 0x1 << 0 ) /* (RSTC) User Reset Enable */ +#define AT91C_SYSC_URSTIEN ( ( unsigned int ) 0x1 << 4 ) /* (RSTC) User Reset Interrupt Enable */ +#define AT91C_SYSC_ERSTL ( ( unsigned int ) 0xF << 8 ) /* (RSTC) User Reset Enable */ +#define AT91C_SYSC_BODIEN ( ( unsigned int ) 0x1 << 16 ) /* (RSTC) Brown-out Detection Interrupt Enable */ -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Real Time Timer Controller Interface -// ***************************************************************************** -typedef struct _AT91S_RTTC { - AT91_REG RTTC_RTMR; // Real-time Mode Register - AT91_REG RTTC_RTAR; // Real-time Alarm Register - AT91_REG RTTC_RTVR; // Real-time Value Register - AT91_REG RTTC_RTSR; // Real-time Status Register -} AT91S_RTTC, *AT91PS_RTTC; +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR Real Time Timer Controller Interface */ +/* ***************************************************************************** */ +typedef struct _AT91S_RTTC +{ + AT91_REG RTTC_RTMR; /* Real-time Mode Register */ + AT91_REG RTTC_RTAR; /* Real-time Alarm Register */ + AT91_REG RTTC_RTVR; /* Real-time Value Register */ + AT91_REG RTTC_RTSR; /* Real-time Status Register */ +} AT91S_RTTC, * AT91PS_RTTC; -// -------- SYSC_RTMR : (RTTC Offset: 0x0) Real-time Mode Register -------- -#define AT91C_SYSC_RTPRES ((unsigned int) 0xFFFF << 0) // (RTTC) Real-time Timer Prescaler Value -#define AT91C_SYSC_ALMIEN ((unsigned int) 0x1 << 16) // (RTTC) Alarm Interrupt Enable -#define AT91C_SYSC_RTTINCIEN ((unsigned int) 0x1 << 17) // (RTTC) Real Time Timer Increment Interrupt Enable -#define AT91C_SYSC_RTTRST ((unsigned int) 0x1 << 18) // (RTTC) Real Time Timer Restart -// -------- SYSC_RTAR : (RTTC Offset: 0x4) Real-time Alarm Register -------- -#define AT91C_SYSC_ALMV ((unsigned int) 0x0 << 0) // (RTTC) Alarm Value -// -------- SYSC_RTVR : (RTTC Offset: 0x8) Current Real-time Value Register -------- -#define AT91C_SYSC_CRTV ((unsigned int) 0x0 << 0) // (RTTC) Current Real-time Value -// -------- SYSC_RTSR : (RTTC Offset: 0xc) Real-time Status Register -------- -#define AT91C_SYSC_ALMS ((unsigned int) 0x1 << 0) // (RTTC) Real-time Alarm Status -#define AT91C_SYSC_RTTINC ((unsigned int) 0x1 << 1) // (RTTC) Real-time Timer Increment +/* -------- SYSC_RTMR : (RTTC Offset: 0x0) Real-time Mode Register -------- */ +#define AT91C_SYSC_RTPRES ( ( unsigned int ) 0xFFFF << 0 ) /* (RTTC) Real-time Timer Prescaler Value */ +#define AT91C_SYSC_ALMIEN ( ( unsigned int ) 0x1 << 16 ) /* (RTTC) Alarm Interrupt Enable */ +#define AT91C_SYSC_RTTINCIEN ( ( unsigned int ) 0x1 << 17 ) /* (RTTC) Real Time Timer Increment Interrupt Enable */ +#define AT91C_SYSC_RTTRST ( ( unsigned int ) 0x1 << 18 ) /* (RTTC) Real Time Timer Restart */ +/* -------- SYSC_RTAR : (RTTC Offset: 0x4) Real-time Alarm Register -------- */ +#define AT91C_SYSC_ALMV ( ( unsigned int ) 0x0 << 0 ) /* (RTTC) Alarm Value */ +/* -------- SYSC_RTVR : (RTTC Offset: 0x8) Current Real-time Value Register -------- */ +#define AT91C_SYSC_CRTV ( ( unsigned int ) 0x0 << 0 ) /* (RTTC) Current Real-time Value */ +/* -------- SYSC_RTSR : (RTTC Offset: 0xc) Real-time Status Register -------- */ +#define AT91C_SYSC_ALMS ( ( unsigned int ) 0x1 << 0 ) /* (RTTC) Real-time Alarm Status */ +#define AT91C_SYSC_RTTINC ( ( unsigned int ) 0x1 << 1 ) /* (RTTC) Real-time Timer Increment */ -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Periodic Interval Timer Controller Interface -// ***************************************************************************** -typedef struct _AT91S_PITC { - AT91_REG PITC_PIMR; // Period Interval Mode Register - AT91_REG PITC_PISR; // Period Interval Status Register - AT91_REG PITC_PIVR; // Period Interval Value Register - AT91_REG PITC_PIIR; // Period Interval Image Register -} AT91S_PITC, *AT91PS_PITC; +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR Periodic Interval Timer Controller Interface */ +/* ***************************************************************************** */ +typedef struct _AT91S_PITC +{ + AT91_REG PITC_PIMR; /* Period Interval Mode Register */ + AT91_REG PITC_PISR; /* Period Interval Status Register */ + AT91_REG PITC_PIVR; /* Period Interval Value Register */ + AT91_REG PITC_PIIR; /* Period Interval Image Register */ +} AT91S_PITC, * AT91PS_PITC; -// -------- SYSC_PIMR : (PITC Offset: 0x0) Periodic Interval Mode Register -------- -#define AT91C_SYSC_PIV ((unsigned int) 0xFFFFF << 0) // (PITC) Periodic Interval Value -#define AT91C_SYSC_PITEN ((unsigned int) 0x1 << 24) // (PITC) Periodic Interval Timer Enabled -#define AT91C_SYSC_PITIEN ((unsigned int) 0x1 << 25) // (PITC) Periodic Interval Timer Interrupt Enable -// -------- SYSC_PISR : (PITC Offset: 0x4) Periodic Interval Status Register -------- -#define AT91C_SYSC_PITS ((unsigned int) 0x1 << 0) // (PITC) Periodic Interval Timer Status -// -------- SYSC_PIVR : (PITC Offset: 0x8) Periodic Interval Value Register -------- -#define AT91C_SYSC_CPIV ((unsigned int) 0xFFFFF << 0) // (PITC) Current Periodic Interval Value -#define AT91C_SYSC_PICNT ((unsigned int) 0xFFF << 20) // (PITC) Periodic Interval Counter -// -------- SYSC_PIIR : (PITC Offset: 0xc) Periodic Interval Image Register -------- +/* -------- SYSC_PIMR : (PITC Offset: 0x0) Periodic Interval Mode Register -------- */ +#define AT91C_SYSC_PIV ( ( unsigned int ) 0xFFFFF << 0 ) /* (PITC) Periodic Interval Value */ +#define AT91C_SYSC_PITEN ( ( unsigned int ) 0x1 << 24 ) /* (PITC) Periodic Interval Timer Enabled */ +#define AT91C_SYSC_PITIEN ( ( unsigned int ) 0x1 << 25 ) /* (PITC) Periodic Interval Timer Interrupt Enable */ +/* -------- SYSC_PISR : (PITC Offset: 0x4) Periodic Interval Status Register -------- */ +#define AT91C_SYSC_PITS ( ( unsigned int ) 0x1 << 0 ) /* (PITC) Periodic Interval Timer Status */ +/* -------- SYSC_PIVR : (PITC Offset: 0x8) Periodic Interval Value Register -------- */ +#define AT91C_SYSC_CPIV ( ( unsigned int ) 0xFFFFF << 0 ) /* (PITC) Current Periodic Interval Value */ +#define AT91C_SYSC_PICNT ( ( unsigned int ) 0xFFF << 20 ) /* (PITC) Periodic Interval Counter */ +/* -------- SYSC_PIIR : (PITC Offset: 0xc) Periodic Interval Image Register -------- */ -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Watchdog Timer Controller Interface -// ***************************************************************************** -typedef struct _AT91S_WDTC { - AT91_REG WDTC_WDCR; // Watchdog Control Register - AT91_REG WDTC_WDMR; // Watchdog Mode Register - AT91_REG WDTC_WDSR; // Watchdog Status Register -} AT91S_WDTC, *AT91PS_WDTC; +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR Watchdog Timer Controller Interface */ +/* ***************************************************************************** */ +typedef struct _AT91S_WDTC +{ + AT91_REG WDTC_WDCR; /* Watchdog Control Register */ + AT91_REG WDTC_WDMR; /* Watchdog Mode Register */ + AT91_REG WDTC_WDSR; /* Watchdog Status Register */ +} AT91S_WDTC, * AT91PS_WDTC; -// -------- SYSC_WDCR : (WDTC Offset: 0x0) Periodic Interval Image Register -------- -#define AT91C_SYSC_WDRSTT ((unsigned int) 0x1 << 0) // (WDTC) Watchdog Restart -// -------- SYSC_WDMR : (WDTC Offset: 0x4) Watchdog Mode Register -------- -#define AT91C_SYSC_WDV ((unsigned int) 0xFFF << 0) // (WDTC) Watchdog Timer Restart -#define AT91C_SYSC_WDFIEN ((unsigned int) 0x1 << 12) // (WDTC) Watchdog Fault Interrupt Enable -#define AT91C_SYSC_WDRSTEN ((unsigned int) 0x1 << 13) // (WDTC) Watchdog Reset Enable -#define AT91C_SYSC_WDRPROC ((unsigned int) 0x1 << 14) // (WDTC) Watchdog Timer Restart -#define AT91C_SYSC_WDDIS ((unsigned int) 0x1 << 15) // (WDTC) Watchdog Disable -#define AT91C_SYSC_WDD ((unsigned int) 0xFFF << 16) // (WDTC) Watchdog Delta Value -#define AT91C_SYSC_WDDBGHLT ((unsigned int) 0x1 << 28) // (WDTC) Watchdog Debug Halt -#define AT91C_SYSC_WDIDLEHLT ((unsigned int) 0x1 << 29) // (WDTC) Watchdog Idle Halt -// -------- SYSC_WDSR : (WDTC Offset: 0x8) Watchdog Status Register -------- -#define AT91C_SYSC_WDUNF ((unsigned int) 0x1 << 0) // (WDTC) Watchdog Underflow -#define AT91C_SYSC_WDERR ((unsigned int) 0x1 << 1) // (WDTC) Watchdog Error +/* -------- SYSC_WDCR : (WDTC Offset: 0x0) Periodic Interval Image Register -------- */ +#define AT91C_SYSC_WDRSTT ( ( unsigned int ) 0x1 << 0 ) /* (WDTC) Watchdog Restart */ +/* -------- SYSC_WDMR : (WDTC Offset: 0x4) Watchdog Mode Register -------- */ +#define AT91C_SYSC_WDV ( ( unsigned int ) 0xFFF << 0 ) /* (WDTC) Watchdog Timer Restart */ +#define AT91C_SYSC_WDFIEN ( ( unsigned int ) 0x1 << 12 ) /* (WDTC) Watchdog Fault Interrupt Enable */ +#define AT91C_SYSC_WDRSTEN ( ( unsigned int ) 0x1 << 13 ) /* (WDTC) Watchdog Reset Enable */ +#define AT91C_SYSC_WDRPROC ( ( unsigned int ) 0x1 << 14 ) /* (WDTC) Watchdog Timer Restart */ +#define AT91C_SYSC_WDDIS ( ( unsigned int ) 0x1 << 15 ) /* (WDTC) Watchdog Disable */ +#define AT91C_SYSC_WDD ( ( unsigned int ) 0xFFF << 16 ) /* (WDTC) Watchdog Delta Value */ +#define AT91C_SYSC_WDDBGHLT ( ( unsigned int ) 0x1 << 28 ) /* (WDTC) Watchdog Debug Halt */ +#define AT91C_SYSC_WDIDLEHLT ( ( unsigned int ) 0x1 << 29 ) /* (WDTC) Watchdog Idle Halt */ +/* -------- SYSC_WDSR : (WDTC Offset: 0x8) Watchdog Status Register -------- */ +#define AT91C_SYSC_WDUNF ( ( unsigned int ) 0x1 << 0 ) /* (WDTC) Watchdog Underflow */ +#define AT91C_SYSC_WDERR ( ( unsigned int ) 0x1 << 1 ) /* (WDTC) Watchdog Error */ -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Memory Controller Interface -// ***************************************************************************** -typedef struct _AT91S_MC { - AT91_REG MC_RCR; // MC Remap Control Register - AT91_REG MC_ASR; // MC Abort Status Register - AT91_REG MC_AASR; // MC Abort Address Status Register - AT91_REG Reserved0[21]; // - AT91_REG MC_FMR; // MC Flash Mode Register - AT91_REG MC_FCR; // MC Flash Command Register - AT91_REG MC_FSR; // MC Flash Status Register -} AT91S_MC, *AT91PS_MC; +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR Memory Controller Interface */ +/* ***************************************************************************** */ +typedef struct _AT91S_MC +{ + AT91_REG MC_RCR; /* MC Remap Control Register */ + AT91_REG MC_ASR; /* MC Abort Status Register */ + AT91_REG MC_AASR; /* MC Abort Address Status Register */ + AT91_REG Reserved0[ 21 ]; /* */ + AT91_REG MC_FMR; /* MC Flash Mode Register */ + AT91_REG MC_FCR; /* MC Flash Command Register */ + AT91_REG MC_FSR; /* MC Flash Status Register */ +} AT91S_MC, * AT91PS_MC; -// -------- MC_RCR : (MC Offset: 0x0) MC Remap Control Register -------- -#define AT91C_MC_RCB ((unsigned int) 0x1 << 0) // (MC) Remap Command Bit -// -------- MC_ASR : (MC Offset: 0x4) MC Abort Status Register -------- -#define AT91C_MC_UNDADD ((unsigned int) 0x1 << 0) // (MC) Undefined Addess Abort Status -#define AT91C_MC_MISADD ((unsigned int) 0x1 << 1) // (MC) Misaligned Addess Abort Status -#define AT91C_MC_ABTSZ ((unsigned int) 0x3 << 8) // (MC) Abort Size Status -#define AT91C_MC_ABTSZ_BYTE ((unsigned int) 0x0 << 8) // (MC) Byte -#define AT91C_MC_ABTSZ_HWORD ((unsigned int) 0x1 << 8) // (MC) Half-word -#define AT91C_MC_ABTSZ_WORD ((unsigned int) 0x2 << 8) // (MC) Word -#define AT91C_MC_ABTTYP ((unsigned int) 0x3 << 10) // (MC) Abort Type Status -#define AT91C_MC_ABTTYP_DATAR ((unsigned int) 0x0 << 10) // (MC) Data Read -#define AT91C_MC_ABTTYP_DATAW ((unsigned int) 0x1 << 10) // (MC) Data Write -#define AT91C_MC_ABTTYP_FETCH ((unsigned int) 0x2 << 10) // (MC) Code Fetch -#define AT91C_MC_MST0 ((unsigned int) 0x1 << 16) // (MC) Master 0 Abort Source -#define AT91C_MC_MST1 ((unsigned int) 0x1 << 17) // (MC) Master 1 Abort Source -#define AT91C_MC_SVMST0 ((unsigned int) 0x1 << 24) // (MC) Saved Master 0 Abort Source -#define AT91C_MC_SVMST1 ((unsigned int) 0x1 << 25) // (MC) Saved Master 1 Abort Source -// -------- MC_FMR : (MC Offset: 0x60) MC Flash Mode Register -------- -#define AT91C_MC_FRDY ((unsigned int) 0x1 << 0) // (MC) Flash Ready -#define AT91C_MC_LOCKE ((unsigned int) 0x1 << 2) // (MC) Lock Error -#define AT91C_MC_PROGE ((unsigned int) 0x1 << 3) // (MC) Programming Error -#define AT91C_MC_NEBP ((unsigned int) 0x1 << 7) // (MC) No Erase Before Programming -#define AT91C_MC_FWS ((unsigned int) 0x3 << 8) // (MC) Flash Wait State -#define AT91C_MC_FWS_0FWS ((unsigned int) 0x0 << 8) // (MC) 1 cycle for Read, 2 for Write operations -#define AT91C_MC_FWS_1FWS ((unsigned int) 0x1 << 8) // (MC) 2 cycles for Read, 3 for Write operations -#define AT91C_MC_FWS_2FWS ((unsigned int) 0x2 << 8) // (MC) 3 cycles for Read, 4 for Write operations -#define AT91C_MC_FWS_3FWS ((unsigned int) 0x3 << 8) // (MC) 4 cycles for Read, 4 for Write operations -#define AT91C_MC_FMCN ((unsigned int) 0xFF << 16) // (MC) Flash Microsecond Cycle Number -// -------- MC_FCR : (MC Offset: 0x64) MC Flash Command Register -------- -#define AT91C_MC_FCMD ((unsigned int) 0xF << 0) // (MC) Flash Command -#define AT91C_MC_FCMD_START_PROG ((unsigned int) 0x1) // (MC) Starts the programming of th epage specified by PAGEN. -#define AT91C_MC_FCMD_LOCK ((unsigned int) 0x2) // (MC) Starts a lock sequence of the sector defined by the bits 4 to 7 of the field PAGEN. -#define AT91C_MC_FCMD_PROG_AND_LOCK ((unsigned int) 0x3) // (MC) The lock sequence automatically happens after the programming sequence is completed. -#define AT91C_MC_FCMD_UNLOCK ((unsigned int) 0x4) // (MC) Starts an unlock sequence of the sector defined by the bits 4 to 7 of the field PAGEN. -#define AT91C_MC_FCMD_ERASE_ALL ((unsigned int) 0x8) // (MC) Starts the erase of the entire flash.If at least a page is locked, the command is cancelled. -#define AT91C_MC_FCMD_SET_GP_NVM ((unsigned int) 0xB) // (MC) Set General Purpose NVM bits. -#define AT91C_MC_FCMD_CLR_GP_NVM ((unsigned int) 0xD) // (MC) Clear General Purpose NVM bits. -#define AT91C_MC_FCMD_SET_SECURITY ((unsigned int) 0xF) // (MC) Set Security Bit. -#define AT91C_MC_PAGEN ((unsigned int) 0x3FF << 8) // (MC) Page Number -#define AT91C_MC_KEY ((unsigned int) 0xFF << 24) // (MC) Writing Protect Key -// -------- MC_FSR : (MC Offset: 0x68) MC Flash Command Register -------- -#define AT91C_MC_SECURITY ((unsigned int) 0x1 << 4) // (MC) Security Bit Status -#define AT91C_MC_GPNVM0 ((unsigned int) 0x1 << 8) // (MC) Sector 0 Lock Status -#define AT91C_MC_GPNVM1 ((unsigned int) 0x1 << 9) // (MC) Sector 1 Lock Status -#define AT91C_MC_GPNVM2 ((unsigned int) 0x1 << 10) // (MC) Sector 2 Lock Status -#define AT91C_MC_GPNVM3 ((unsigned int) 0x1 << 11) // (MC) Sector 3 Lock Status -#define AT91C_MC_GPNVM4 ((unsigned int) 0x1 << 12) // (MC) Sector 4 Lock Status -#define AT91C_MC_GPNVM5 ((unsigned int) 0x1 << 13) // (MC) Sector 5 Lock Status -#define AT91C_MC_GPNVM6 ((unsigned int) 0x1 << 14) // (MC) Sector 6 Lock Status -#define AT91C_MC_GPNVM7 ((unsigned int) 0x1 << 15) // (MC) Sector 7 Lock Status -#define AT91C_MC_LOCKS0 ((unsigned int) 0x1 << 16) // (MC) Sector 0 Lock Status -#define AT91C_MC_LOCKS1 ((unsigned int) 0x1 << 17) // (MC) Sector 1 Lock Status -#define AT91C_MC_LOCKS2 ((unsigned int) 0x1 << 18) // (MC) Sector 2 Lock Status -#define AT91C_MC_LOCKS3 ((unsigned int) 0x1 << 19) // (MC) Sector 3 Lock Status -#define AT91C_MC_LOCKS4 ((unsigned int) 0x1 << 20) // (MC) Sector 4 Lock Status -#define AT91C_MC_LOCKS5 ((unsigned int) 0x1 << 21) // (MC) Sector 5 Lock Status -#define AT91C_MC_LOCKS6 ((unsigned int) 0x1 << 22) // (MC) Sector 6 Lock Status -#define AT91C_MC_LOCKS7 ((unsigned int) 0x1 << 23) // (MC) Sector 7 Lock Status -#define AT91C_MC_LOCKS8 ((unsigned int) 0x1 << 24) // (MC) Sector 8 Lock Status -#define AT91C_MC_LOCKS9 ((unsigned int) 0x1 << 25) // (MC) Sector 9 Lock Status -#define AT91C_MC_LOCKS10 ((unsigned int) 0x1 << 26) // (MC) Sector 10 Lock Status -#define AT91C_MC_LOCKS11 ((unsigned int) 0x1 << 27) // (MC) Sector 11 Lock Status -#define AT91C_MC_LOCKS12 ((unsigned int) 0x1 << 28) // (MC) Sector 12 Lock Status -#define AT91C_MC_LOCKS13 ((unsigned int) 0x1 << 29) // (MC) Sector 13 Lock Status -#define AT91C_MC_LOCKS14 ((unsigned int) 0x1 << 30) // (MC) Sector 14 Lock Status -#define AT91C_MC_LOCKS15 ((unsigned int) 0x1 << 31) // (MC) Sector 15 Lock Status +/* -------- MC_RCR : (MC Offset: 0x0) MC Remap Control Register -------- */ +#define AT91C_MC_RCB ( ( unsigned int ) 0x1 << 0 ) /* (MC) Remap Command Bit */ +/* -------- MC_ASR : (MC Offset: 0x4) MC Abort Status Register -------- */ +#define AT91C_MC_UNDADD ( ( unsigned int ) 0x1 << 0 ) /* (MC) Undefined Addess Abort Status */ +#define AT91C_MC_MISADD ( ( unsigned int ) 0x1 << 1 ) /* (MC) Misaligned Addess Abort Status */ +#define AT91C_MC_ABTSZ ( ( unsigned int ) 0x3 << 8 ) /* (MC) Abort Size Status */ +#define AT91C_MC_ABTSZ_BYTE ( ( unsigned int ) 0x0 << 8 ) /* (MC) Byte */ +#define AT91C_MC_ABTSZ_HWORD ( ( unsigned int ) 0x1 << 8 ) /* (MC) Half-word */ +#define AT91C_MC_ABTSZ_WORD ( ( unsigned int ) 0x2 << 8 ) /* (MC) Word */ +#define AT91C_MC_ABTTYP ( ( unsigned int ) 0x3 << 10 ) /* (MC) Abort Type Status */ +#define AT91C_MC_ABTTYP_DATAR ( ( unsigned int ) 0x0 << 10 ) /* (MC) Data Read */ +#define AT91C_MC_ABTTYP_DATAW ( ( unsigned int ) 0x1 << 10 ) /* (MC) Data Write */ +#define AT91C_MC_ABTTYP_FETCH ( ( unsigned int ) 0x2 << 10 ) /* (MC) Code Fetch */ +#define AT91C_MC_MST0 ( ( unsigned int ) 0x1 << 16 ) /* (MC) Master 0 Abort Source */ +#define AT91C_MC_MST1 ( ( unsigned int ) 0x1 << 17 ) /* (MC) Master 1 Abort Source */ +#define AT91C_MC_SVMST0 ( ( unsigned int ) 0x1 << 24 ) /* (MC) Saved Master 0 Abort Source */ +#define AT91C_MC_SVMST1 ( ( unsigned int ) 0x1 << 25 ) /* (MC) Saved Master 1 Abort Source */ +/* -------- MC_FMR : (MC Offset: 0x60) MC Flash Mode Register -------- */ +#define AT91C_MC_FRDY ( ( unsigned int ) 0x1 << 0 ) /* (MC) Flash Ready */ +#define AT91C_MC_LOCKE ( ( unsigned int ) 0x1 << 2 ) /* (MC) Lock Error */ +#define AT91C_MC_PROGE ( ( unsigned int ) 0x1 << 3 ) /* (MC) Programming Error */ +#define AT91C_MC_NEBP ( ( unsigned int ) 0x1 << 7 ) /* (MC) No Erase Before Programming */ +#define AT91C_MC_FWS ( ( unsigned int ) 0x3 << 8 ) /* (MC) Flash Wait State */ +#define AT91C_MC_FWS_0FWS ( ( unsigned int ) 0x0 << 8 ) /* (MC) 1 cycle for Read, 2 for Write operations */ +#define AT91C_MC_FWS_1FWS ( ( unsigned int ) 0x1 << 8 ) /* (MC) 2 cycles for Read, 3 for Write operations */ +#define AT91C_MC_FWS_2FWS ( ( unsigned int ) 0x2 << 8 ) /* (MC) 3 cycles for Read, 4 for Write operations */ +#define AT91C_MC_FWS_3FWS ( ( unsigned int ) 0x3 << 8 ) /* (MC) 4 cycles for Read, 4 for Write operations */ +#define AT91C_MC_FMCN ( ( unsigned int ) 0xFF << 16 ) /* (MC) Flash Microsecond Cycle Number */ +/* -------- MC_FCR : (MC Offset: 0x64) MC Flash Command Register -------- */ +#define AT91C_MC_FCMD ( ( unsigned int ) 0xF << 0 ) /* (MC) Flash Command */ +#define AT91C_MC_FCMD_START_PROG ( ( unsigned int ) 0x1 ) /* (MC) Starts the programming of th epage specified by PAGEN. */ +#define AT91C_MC_FCMD_LOCK ( ( unsigned int ) 0x2 ) /* (MC) Starts a lock sequence of the sector defined by the bits 4 to 7 of the field PAGEN. */ +#define AT91C_MC_FCMD_PROG_AND_LOCK ( ( unsigned int ) 0x3 ) /* (MC) The lock sequence automatically happens after the programming sequence is completed. */ +#define AT91C_MC_FCMD_UNLOCK ( ( unsigned int ) 0x4 ) /* (MC) Starts an unlock sequence of the sector defined by the bits 4 to 7 of the field PAGEN. */ +#define AT91C_MC_FCMD_ERASE_ALL ( ( unsigned int ) 0x8 ) /* (MC) Starts the erase of the entire flash.If at least a page is locked, the command is cancelled. */ +#define AT91C_MC_FCMD_SET_GP_NVM ( ( unsigned int ) 0xB ) /* (MC) Set General Purpose NVM bits. */ +#define AT91C_MC_FCMD_CLR_GP_NVM ( ( unsigned int ) 0xD ) /* (MC) Clear General Purpose NVM bits. */ +#define AT91C_MC_FCMD_SET_SECURITY ( ( unsigned int ) 0xF ) /* (MC) Set Security Bit. */ +#define AT91C_MC_PAGEN ( ( unsigned int ) 0x3FF << 8 ) /* (MC) Page Number */ +#define AT91C_MC_KEY ( ( unsigned int ) 0xFF << 24 ) /* (MC) Writing Protect Key */ +/* -------- MC_FSR : (MC Offset: 0x68) MC Flash Command Register -------- */ +#define AT91C_MC_SECURITY ( ( unsigned int ) 0x1 << 4 ) /* (MC) Security Bit Status */ +#define AT91C_MC_GPNVM0 ( ( unsigned int ) 0x1 << 8 ) /* (MC) Sector 0 Lock Status */ +#define AT91C_MC_GPNVM1 ( ( unsigned int ) 0x1 << 9 ) /* (MC) Sector 1 Lock Status */ +#define AT91C_MC_GPNVM2 ( ( unsigned int ) 0x1 << 10 ) /* (MC) Sector 2 Lock Status */ +#define AT91C_MC_GPNVM3 ( ( unsigned int ) 0x1 << 11 ) /* (MC) Sector 3 Lock Status */ +#define AT91C_MC_GPNVM4 ( ( unsigned int ) 0x1 << 12 ) /* (MC) Sector 4 Lock Status */ +#define AT91C_MC_GPNVM5 ( ( unsigned int ) 0x1 << 13 ) /* (MC) Sector 5 Lock Status */ +#define AT91C_MC_GPNVM6 ( ( unsigned int ) 0x1 << 14 ) /* (MC) Sector 6 Lock Status */ +#define AT91C_MC_GPNVM7 ( ( unsigned int ) 0x1 << 15 ) /* (MC) Sector 7 Lock Status */ +#define AT91C_MC_LOCKS0 ( ( unsigned int ) 0x1 << 16 ) /* (MC) Sector 0 Lock Status */ +#define AT91C_MC_LOCKS1 ( ( unsigned int ) 0x1 << 17 ) /* (MC) Sector 1 Lock Status */ +#define AT91C_MC_LOCKS2 ( ( unsigned int ) 0x1 << 18 ) /* (MC) Sector 2 Lock Status */ +#define AT91C_MC_LOCKS3 ( ( unsigned int ) 0x1 << 19 ) /* (MC) Sector 3 Lock Status */ +#define AT91C_MC_LOCKS4 ( ( unsigned int ) 0x1 << 20 ) /* (MC) Sector 4 Lock Status */ +#define AT91C_MC_LOCKS5 ( ( unsigned int ) 0x1 << 21 ) /* (MC) Sector 5 Lock Status */ +#define AT91C_MC_LOCKS6 ( ( unsigned int ) 0x1 << 22 ) /* (MC) Sector 6 Lock Status */ +#define AT91C_MC_LOCKS7 ( ( unsigned int ) 0x1 << 23 ) /* (MC) Sector 7 Lock Status */ +#define AT91C_MC_LOCKS8 ( ( unsigned int ) 0x1 << 24 ) /* (MC) Sector 8 Lock Status */ +#define AT91C_MC_LOCKS9 ( ( unsigned int ) 0x1 << 25 ) /* (MC) Sector 9 Lock Status */ +#define AT91C_MC_LOCKS10 ( ( unsigned int ) 0x1 << 26 ) /* (MC) Sector 10 Lock Status */ +#define AT91C_MC_LOCKS11 ( ( unsigned int ) 0x1 << 27 ) /* (MC) Sector 11 Lock Status */ +#define AT91C_MC_LOCKS12 ( ( unsigned int ) 0x1 << 28 ) /* (MC) Sector 12 Lock Status */ +#define AT91C_MC_LOCKS13 ( ( unsigned int ) 0x1 << 29 ) /* (MC) Sector 13 Lock Status */ +#define AT91C_MC_LOCKS14 ( ( unsigned int ) 0x1 << 30 ) /* (MC) Sector 14 Lock Status */ +#define AT91C_MC_LOCKS15 ( ( unsigned int ) 0x1 << 31 ) /* (MC) Sector 15 Lock Status */ -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Serial Parallel Interface -// ***************************************************************************** -typedef struct _AT91S_SPI { - AT91_REG SPI_CR; // Control Register - AT91_REG SPI_MR; // Mode Register - AT91_REG SPI_RDR; // Receive Data Register - AT91_REG SPI_TDR; // Transmit Data Register - AT91_REG SPI_SR; // Status Register - AT91_REG SPI_IER; // Interrupt Enable Register - AT91_REG SPI_IDR; // Interrupt Disable Register - AT91_REG SPI_IMR; // Interrupt Mask Register - AT91_REG Reserved0[4]; // - AT91_REG SPI_CSR[4]; // Chip Select Register - AT91_REG Reserved1[48]; // - AT91_REG SPI_RPR; // Receive Pointer Register - AT91_REG SPI_RCR; // Receive Counter Register - AT91_REG SPI_TPR; // Transmit Pointer Register - AT91_REG SPI_TCR; // Transmit Counter Register - AT91_REG SPI_RNPR; // Receive Next Pointer Register - AT91_REG SPI_RNCR; // Receive Next Counter Register - AT91_REG SPI_TNPR; // Transmit Next Pointer Register - AT91_REG SPI_TNCR; // Transmit Next Counter Register - AT91_REG SPI_PTCR; // PDC Transfer Control Register - AT91_REG SPI_PTSR; // PDC Transfer Status Register -} AT91S_SPI, *AT91PS_SPI; +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR Serial Parallel Interface */ +/* ***************************************************************************** */ +typedef struct _AT91S_SPI +{ + AT91_REG SPI_CR; /* Control Register */ + AT91_REG SPI_MR; /* Mode Register */ + AT91_REG SPI_RDR; /* Receive Data Register */ + AT91_REG SPI_TDR; /* Transmit Data Register */ + AT91_REG SPI_SR; /* Status Register */ + AT91_REG SPI_IER; /* Interrupt Enable Register */ + AT91_REG SPI_IDR; /* Interrupt Disable Register */ + AT91_REG SPI_IMR; /* Interrupt Mask Register */ + AT91_REG Reserved0[ 4 ]; /* */ + AT91_REG SPI_CSR[ 4 ]; /* Chip Select Register */ + AT91_REG Reserved1[ 48 ]; /* */ + AT91_REG SPI_RPR; /* Receive Pointer Register */ + AT91_REG SPI_RCR; /* Receive Counter Register */ + AT91_REG SPI_TPR; /* Transmit Pointer Register */ + AT91_REG SPI_TCR; /* Transmit Counter Register */ + AT91_REG SPI_RNPR; /* Receive Next Pointer Register */ + AT91_REG SPI_RNCR; /* Receive Next Counter Register */ + AT91_REG SPI_TNPR; /* Transmit Next Pointer Register */ + AT91_REG SPI_TNCR; /* Transmit Next Counter Register */ + AT91_REG SPI_PTCR; /* PDC Transfer Control Register */ + AT91_REG SPI_PTSR; /* PDC Transfer Status Register */ +} AT91S_SPI, * AT91PS_SPI; -// -------- SPI_CR : (SPI Offset: 0x0) SPI Control Register -------- -#define AT91C_SPI_SPIEN ((unsigned int) 0x1 << 0) // (SPI) SPI Enable -#define AT91C_SPI_SPIDIS ((unsigned int) 0x1 << 1) // (SPI) SPI Disable -#define AT91C_SPI_SWRST ((unsigned int) 0x1 << 7) // (SPI) SPI Software reset -#define AT91C_SPI_LASTXFER ((unsigned int) 0x1 << 24) // (SPI) SPI Last Transfer -// -------- SPI_MR : (SPI Offset: 0x4) SPI Mode Register -------- -#define AT91C_SPI_MSTR ((unsigned int) 0x1 << 0) // (SPI) Master/Slave Mode -#define AT91C_SPI_PS ((unsigned int) 0x1 << 1) // (SPI) Peripheral Select -#define AT91C_SPI_PS_FIXED ((unsigned int) 0x0 << 1) // (SPI) Fixed Peripheral Select -#define AT91C_SPI_PS_VARIABLE ((unsigned int) 0x1 << 1) // (SPI) Variable Peripheral Select -#define AT91C_SPI_PCSDEC ((unsigned int) 0x1 << 2) // (SPI) Chip Select Decode -#define AT91C_SPI_FDIV ((unsigned int) 0x1 << 3) // (SPI) Clock Selection -#define AT91C_SPI_MODFDIS ((unsigned int) 0x1 << 4) // (SPI) Mode Fault Detection -#define AT91C_SPI_LLB ((unsigned int) 0x1 << 7) // (SPI) Clock Selection -#define AT91C_SPI_PCS ((unsigned int) 0xF << 16) // (SPI) Peripheral Chip Select -#define AT91C_SPI_DLYBCS ((unsigned int) 0xFF << 24) // (SPI) Delay Between Chip Selects -// -------- SPI_RDR : (SPI Offset: 0x8) Receive Data Register -------- -#define AT91C_SPI_RD ((unsigned int) 0xFFFF << 0) // (SPI) Receive Data -#define AT91C_SPI_RPCS ((unsigned int) 0xF << 16) // (SPI) Peripheral Chip Select Status -// -------- SPI_TDR : (SPI Offset: 0xc) Transmit Data Register -------- -#define AT91C_SPI_TD ((unsigned int) 0xFFFF << 0) // (SPI) Transmit Data -#define AT91C_SPI_TPCS ((unsigned int) 0xF << 16) // (SPI) Peripheral Chip Select Status -// -------- SPI_SR : (SPI Offset: 0x10) Status Register -------- -#define AT91C_SPI_RDRF ((unsigned int) 0x1 << 0) // (SPI) Receive Data Register Full -#define AT91C_SPI_TDRE ((unsigned int) 0x1 << 1) // (SPI) Transmit Data Register Empty -#define AT91C_SPI_MODF ((unsigned int) 0x1 << 2) // (SPI) Mode Fault Error -#define AT91C_SPI_OVRES ((unsigned int) 0x1 << 3) // (SPI) Overrun Error Status -#define AT91C_SPI_ENDRX ((unsigned int) 0x1 << 4) // (SPI) End of Receiver Transfer -#define AT91C_SPI_ENDTX ((unsigned int) 0x1 << 5) // (SPI) End of Receiver Transfer -#define AT91C_SPI_RXBUFF ((unsigned int) 0x1 << 6) // (SPI) RXBUFF Interrupt -#define AT91C_SPI_TXBUFE ((unsigned int) 0x1 << 7) // (SPI) TXBUFE Interrupt -#define AT91C_SPI_NSSR ((unsigned int) 0x1 << 8) // (SPI) NSSR Interrupt -#define AT91C_SPI_TXEMPTY ((unsigned int) 0x1 << 9) // (SPI) TXEMPTY Interrupt -#define AT91C_SPI_SPIENS ((unsigned int) 0x1 << 16) // (SPI) Enable Status -// -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register -------- -// -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register -------- -// -------- SPI_IMR : (SPI Offset: 0x1c) Interrupt Mask Register -------- -// -------- SPI_CSR : (SPI Offset: 0x30) Chip Select Register -------- -#define AT91C_SPI_CPOL ((unsigned int) 0x1 << 0) // (SPI) Clock Polarity -#define AT91C_SPI_NCPHA ((unsigned int) 0x1 << 1) // (SPI) Clock Phase -#define AT91C_SPI_CSAAT ((unsigned int) 0x1 << 2) // (SPI) Chip Select Active After Transfer -#define AT91C_SPI_BITS ((unsigned int) 0xF << 4) // (SPI) Bits Per Transfer -#define AT91C_SPI_BITS_8 ((unsigned int) 0x0 << 4) // (SPI) 8 Bits Per transfer -#define AT91C_SPI_BITS_9 ((unsigned int) 0x1 << 4) // (SPI) 9 Bits Per transfer -#define AT91C_SPI_BITS_10 ((unsigned int) 0x2 << 4) // (SPI) 10 Bits Per transfer -#define AT91C_SPI_BITS_11 ((unsigned int) 0x3 << 4) // (SPI) 11 Bits Per transfer -#define AT91C_SPI_BITS_12 ((unsigned int) 0x4 << 4) // (SPI) 12 Bits Per transfer -#define AT91C_SPI_BITS_13 ((unsigned int) 0x5 << 4) // (SPI) 13 Bits Per transfer -#define AT91C_SPI_BITS_14 ((unsigned int) 0x6 << 4) // (SPI) 14 Bits Per transfer -#define AT91C_SPI_BITS_15 ((unsigned int) 0x7 << 4) // (SPI) 15 Bits Per transfer -#define AT91C_SPI_BITS_16 ((unsigned int) 0x8 << 4) // (SPI) 16 Bits Per transfer -#define AT91C_SPI_SCBR ((unsigned int) 0xFF << 8) // (SPI) Serial Clock Baud Rate -#define AT91C_SPI_DLYBS ((unsigned int) 0xFF << 16) // (SPI) Serial Clock Baud Rate -#define AT91C_SPI_DLYBCT ((unsigned int) 0xFF << 24) // (SPI) Delay Between Consecutive Transfers +/* -------- SPI_CR : (SPI Offset: 0x0) SPI Control Register -------- */ +#define AT91C_SPI_SPIEN ( ( unsigned int ) 0x1 << 0 ) /* (SPI) SPI Enable */ +#define AT91C_SPI_SPIDIS ( ( unsigned int ) 0x1 << 1 ) /* (SPI) SPI Disable */ +#define AT91C_SPI_SWRST ( ( unsigned int ) 0x1 << 7 ) /* (SPI) SPI Software reset */ +#define AT91C_SPI_LASTXFER ( ( unsigned int ) 0x1 << 24 ) /* (SPI) SPI Last Transfer */ +/* -------- SPI_MR : (SPI Offset: 0x4) SPI Mode Register -------- */ +#define AT91C_SPI_MSTR ( ( unsigned int ) 0x1 << 0 ) /* (SPI) Master/Slave Mode */ +#define AT91C_SPI_PS ( ( unsigned int ) 0x1 << 1 ) /* (SPI) Peripheral Select */ +#define AT91C_SPI_PS_FIXED ( ( unsigned int ) 0x0 << 1 ) /* (SPI) Fixed Peripheral Select */ +#define AT91C_SPI_PS_VARIABLE ( ( unsigned int ) 0x1 << 1 ) /* (SPI) Variable Peripheral Select */ +#define AT91C_SPI_PCSDEC ( ( unsigned int ) 0x1 << 2 ) /* (SPI) Chip Select Decode */ +#define AT91C_SPI_FDIV ( ( unsigned int ) 0x1 << 3 ) /* (SPI) Clock Selection */ +#define AT91C_SPI_MODFDIS ( ( unsigned int ) 0x1 << 4 ) /* (SPI) Mode Fault Detection */ +#define AT91C_SPI_LLB ( ( unsigned int ) 0x1 << 7 ) /* (SPI) Clock Selection */ +#define AT91C_SPI_PCS ( ( unsigned int ) 0xF << 16 ) /* (SPI) Peripheral Chip Select */ +#define AT91C_SPI_DLYBCS ( ( unsigned int ) 0xFF << 24 ) /* (SPI) Delay Between Chip Selects */ +/* -------- SPI_RDR : (SPI Offset: 0x8) Receive Data Register -------- */ +#define AT91C_SPI_RD ( ( unsigned int ) 0xFFFF << 0 ) /* (SPI) Receive Data */ +#define AT91C_SPI_RPCS ( ( unsigned int ) 0xF << 16 ) /* (SPI) Peripheral Chip Select Status */ +/* -------- SPI_TDR : (SPI Offset: 0xc) Transmit Data Register -------- */ +#define AT91C_SPI_TD ( ( unsigned int ) 0xFFFF << 0 ) /* (SPI) Transmit Data */ +#define AT91C_SPI_TPCS ( ( unsigned int ) 0xF << 16 ) /* (SPI) Peripheral Chip Select Status */ +/* -------- SPI_SR : (SPI Offset: 0x10) Status Register -------- */ +#define AT91C_SPI_RDRF ( ( unsigned int ) 0x1 << 0 ) /* (SPI) Receive Data Register Full */ +#define AT91C_SPI_TDRE ( ( unsigned int ) 0x1 << 1 ) /* (SPI) Transmit Data Register Empty */ +#define AT91C_SPI_MODF ( ( unsigned int ) 0x1 << 2 ) /* (SPI) Mode Fault Error */ +#define AT91C_SPI_OVRES ( ( unsigned int ) 0x1 << 3 ) /* (SPI) Overrun Error Status */ +#define AT91C_SPI_ENDRX ( ( unsigned int ) 0x1 << 4 ) /* (SPI) End of Receiver Transfer */ +#define AT91C_SPI_ENDTX ( ( unsigned int ) 0x1 << 5 ) /* (SPI) End of Receiver Transfer */ +#define AT91C_SPI_RXBUFF ( ( unsigned int ) 0x1 << 6 ) /* (SPI) RXBUFF Interrupt */ +#define AT91C_SPI_TXBUFE ( ( unsigned int ) 0x1 << 7 ) /* (SPI) TXBUFE Interrupt */ +#define AT91C_SPI_NSSR ( ( unsigned int ) 0x1 << 8 ) /* (SPI) NSSR Interrupt */ +#define AT91C_SPI_TXEMPTY ( ( unsigned int ) 0x1 << 9 ) /* (SPI) TXEMPTY Interrupt */ +#define AT91C_SPI_SPIENS ( ( unsigned int ) 0x1 << 16 ) /* (SPI) Enable Status */ +/* -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register -------- */ +/* -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register -------- */ +/* -------- SPI_IMR : (SPI Offset: 0x1c) Interrupt Mask Register -------- */ +/* -------- SPI_CSR : (SPI Offset: 0x30) Chip Select Register -------- */ +#define AT91C_SPI_CPOL ( ( unsigned int ) 0x1 << 0 ) /* (SPI) Clock Polarity */ +#define AT91C_SPI_NCPHA ( ( unsigned int ) 0x1 << 1 ) /* (SPI) Clock Phase */ +#define AT91C_SPI_CSAAT ( ( unsigned int ) 0x1 << 2 ) /* (SPI) Chip Select Active After Transfer */ +#define AT91C_SPI_BITS ( ( unsigned int ) 0xF << 4 ) /* (SPI) Bits Per Transfer */ +#define AT91C_SPI_BITS_8 ( ( unsigned int ) 0x0 << 4 ) /* (SPI) 8 Bits Per transfer */ +#define AT91C_SPI_BITS_9 ( ( unsigned int ) 0x1 << 4 ) /* (SPI) 9 Bits Per transfer */ +#define AT91C_SPI_BITS_10 ( ( unsigned int ) 0x2 << 4 ) /* (SPI) 10 Bits Per transfer */ +#define AT91C_SPI_BITS_11 ( ( unsigned int ) 0x3 << 4 ) /* (SPI) 11 Bits Per transfer */ +#define AT91C_SPI_BITS_12 ( ( unsigned int ) 0x4 << 4 ) /* (SPI) 12 Bits Per transfer */ +#define AT91C_SPI_BITS_13 ( ( unsigned int ) 0x5 << 4 ) /* (SPI) 13 Bits Per transfer */ +#define AT91C_SPI_BITS_14 ( ( unsigned int ) 0x6 << 4 ) /* (SPI) 14 Bits Per transfer */ +#define AT91C_SPI_BITS_15 ( ( unsigned int ) 0x7 << 4 ) /* (SPI) 15 Bits Per transfer */ +#define AT91C_SPI_BITS_16 ( ( unsigned int ) 0x8 << 4 ) /* (SPI) 16 Bits Per transfer */ +#define AT91C_SPI_SCBR ( ( unsigned int ) 0xFF << 8 ) /* (SPI) Serial Clock Baud Rate */ +#define AT91C_SPI_DLYBS ( ( unsigned int ) 0xFF << 16 ) /* (SPI) Serial Clock Baud Rate */ +#define AT91C_SPI_DLYBCT ( ( unsigned int ) 0xFF << 24 ) /* (SPI) Delay Between Consecutive Transfers */ -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Analog to Digital Convertor -// ***************************************************************************** -typedef struct _AT91S_ADC { - AT91_REG ADC_CR; // ADC Control Register - AT91_REG ADC_MR; // ADC Mode Register - AT91_REG Reserved0[2]; // - AT91_REG ADC_CHER; // ADC Channel Enable Register - AT91_REG ADC_CHDR; // ADC Channel Disable Register - AT91_REG ADC_CHSR; // ADC Channel Status Register - AT91_REG ADC_SR; // ADC Status Register - AT91_REG ADC_LCDR; // ADC Last Converted Data Register - AT91_REG ADC_IER; // ADC Interrupt Enable Register - AT91_REG ADC_IDR; // ADC Interrupt Disable Register - AT91_REG ADC_IMR; // ADC Interrupt Mask Register - AT91_REG ADC_CDR0; // ADC Channel Data Register 0 - AT91_REG ADC_CDR1; // ADC Channel Data Register 1 - AT91_REG ADC_CDR2; // ADC Channel Data Register 2 - AT91_REG ADC_CDR3; // ADC Channel Data Register 3 - AT91_REG ADC_CDR4; // ADC Channel Data Register 4 - AT91_REG ADC_CDR5; // ADC Channel Data Register 5 - AT91_REG ADC_CDR6; // ADC Channel Data Register 6 - AT91_REG ADC_CDR7; // ADC Channel Data Register 7 - AT91_REG Reserved1[44]; // - AT91_REG ADC_RPR; // Receive Pointer Register - AT91_REG ADC_RCR; // Receive Counter Register - AT91_REG ADC_TPR; // Transmit Pointer Register - AT91_REG ADC_TCR; // Transmit Counter Register - AT91_REG ADC_RNPR; // Receive Next Pointer Register - AT91_REG ADC_RNCR; // Receive Next Counter Register - AT91_REG ADC_TNPR; // Transmit Next Pointer Register - AT91_REG ADC_TNCR; // Transmit Next Counter Register - AT91_REG ADC_PTCR; // PDC Transfer Control Register - AT91_REG ADC_PTSR; // PDC Transfer Status Register -} AT91S_ADC, *AT91PS_ADC; +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR Analog to Digital Convertor */ +/* ***************************************************************************** */ +typedef struct _AT91S_ADC +{ + AT91_REG ADC_CR; /* ADC Control Register */ + AT91_REG ADC_MR; /* ADC Mode Register */ + AT91_REG Reserved0[ 2 ]; /* */ + AT91_REG ADC_CHER; /* ADC Channel Enable Register */ + AT91_REG ADC_CHDR; /* ADC Channel Disable Register */ + AT91_REG ADC_CHSR; /* ADC Channel Status Register */ + AT91_REG ADC_SR; /* ADC Status Register */ + AT91_REG ADC_LCDR; /* ADC Last Converted Data Register */ + AT91_REG ADC_IER; /* ADC Interrupt Enable Register */ + AT91_REG ADC_IDR; /* ADC Interrupt Disable Register */ + AT91_REG ADC_IMR; /* ADC Interrupt Mask Register */ + AT91_REG ADC_CDR0; /* ADC Channel Data Register 0 */ + AT91_REG ADC_CDR1; /* ADC Channel Data Register 1 */ + AT91_REG ADC_CDR2; /* ADC Channel Data Register 2 */ + AT91_REG ADC_CDR3; /* ADC Channel Data Register 3 */ + AT91_REG ADC_CDR4; /* ADC Channel Data Register 4 */ + AT91_REG ADC_CDR5; /* ADC Channel Data Register 5 */ + AT91_REG ADC_CDR6; /* ADC Channel Data Register 6 */ + AT91_REG ADC_CDR7; /* ADC Channel Data Register 7 */ + AT91_REG Reserved1[ 44 ]; /* */ + AT91_REG ADC_RPR; /* Receive Pointer Register */ + AT91_REG ADC_RCR; /* Receive Counter Register */ + AT91_REG ADC_TPR; /* Transmit Pointer Register */ + AT91_REG ADC_TCR; /* Transmit Counter Register */ + AT91_REG ADC_RNPR; /* Receive Next Pointer Register */ + AT91_REG ADC_RNCR; /* Receive Next Counter Register */ + AT91_REG ADC_TNPR; /* Transmit Next Pointer Register */ + AT91_REG ADC_TNCR; /* Transmit Next Counter Register */ + AT91_REG ADC_PTCR; /* PDC Transfer Control Register */ + AT91_REG ADC_PTSR; /* PDC Transfer Status Register */ +} AT91S_ADC, * AT91PS_ADC; -// -------- ADC_CR : (ADC Offset: 0x0) ADC Control Register -------- -#define AT91C_ADC_SWRST ((unsigned int) 0x1 << 0) // (ADC) Software Reset -#define AT91C_ADC_START ((unsigned int) 0x1 << 1) // (ADC) Start Conversion -// -------- ADC_MR : (ADC Offset: 0x4) ADC Mode Register -------- -#define AT91C_ADC_TRGEN ((unsigned int) 0x1 << 0) // (ADC) Trigger Enable -#define AT91C_ADC_TRGEN_DIS ((unsigned int) 0x0) // (ADC) Hradware triggers are disabled. Starting a conversion is only possible by software -#define AT91C_ADC_TRGEN_EN ((unsigned int) 0x1) // (ADC) Hardware trigger selected by TRGSEL field is enabled. -#define AT91C_ADC_TRGSEL ((unsigned int) 0x7 << 1) // (ADC) Trigger Selection -#define AT91C_ADC_TRGSEL_TIOA0 ((unsigned int) 0x0 << 1) // (ADC) Selected TRGSEL = TIAO0 -#define AT91C_ADC_TRGSEL_TIOA1 ((unsigned int) 0x1 << 1) // (ADC) Selected TRGSEL = TIAO1 -#define AT91C_ADC_TRGSEL_TIOA2 ((unsigned int) 0x2 << 1) // (ADC) Selected TRGSEL = TIAO2 -#define AT91C_ADC_TRGSEL_TIOA3 ((unsigned int) 0x3 << 1) // (ADC) Selected TRGSEL = TIAO3 -#define AT91C_ADC_TRGSEL_TIOA4 ((unsigned int) 0x4 << 1) // (ADC) Selected TRGSEL = TIAO4 -#define AT91C_ADC_TRGSEL_TIOA5 ((unsigned int) 0x5 << 1) // (ADC) Selected TRGSEL = TIAO5 -#define AT91C_ADC_TRGSEL_EXT ((unsigned int) 0x6 << 1) // (ADC) Selected TRGSEL = External Trigger -#define AT91C_ADC_LOWRES ((unsigned int) 0x1 << 4) // (ADC) Resolution. -#define AT91C_ADC_LOWRES_10_BIT ((unsigned int) 0x0 << 4) // (ADC) 10-bit resolution -#define AT91C_ADC_LOWRES_8_BIT ((unsigned int) 0x1 << 4) // (ADC) 8-bit resolution -#define AT91C_ADC_SLEEP ((unsigned int) 0x1 << 5) // (ADC) Sleep Mode -#define AT91C_ADC_SLEEP_NORMAL_MODE ((unsigned int) 0x0 << 5) // (ADC) Normal Mode -#define AT91C_ADC_SLEEP_MODE ((unsigned int) 0x1 << 5) // (ADC) Sleep Mode -#define AT91C_ADC_PRESCAL ((unsigned int) 0x3F << 8) // (ADC) Prescaler rate selection -#define AT91C_ADC_STARTUP ((unsigned int) 0x1F << 16) // (ADC) Startup Time -#define AT91C_ADC_SHTIM ((unsigned int) 0xF << 24) // (ADC) Sample & Hold Time -// -------- ADC_CHER : (ADC Offset: 0x10) ADC Channel Enable Register -------- -#define AT91C_ADC_CH0 ((unsigned int) 0x1 << 0) // (ADC) Channel 0 -#define AT91C_ADC_CH1 ((unsigned int) 0x1 << 1) // (ADC) Channel 1 -#define AT91C_ADC_CH2 ((unsigned int) 0x1 << 2) // (ADC) Channel 2 -#define AT91C_ADC_CH3 ((unsigned int) 0x1 << 3) // (ADC) Channel 3 -#define AT91C_ADC_CH4 ((unsigned int) 0x1 << 4) // (ADC) Channel 4 -#define AT91C_ADC_CH5 ((unsigned int) 0x1 << 5) // (ADC) Channel 5 -#define AT91C_ADC_CH6 ((unsigned int) 0x1 << 6) // (ADC) Channel 6 -#define AT91C_ADC_CH7 ((unsigned int) 0x1 << 7) // (ADC) Channel 7 -// -------- ADC_CHDR : (ADC Offset: 0x14) ADC Channel Disable Register -------- -// -------- ADC_CHSR : (ADC Offset: 0x18) ADC Channel Status Register -------- -// -------- ADC_SR : (ADC Offset: 0x1c) ADC Status Register -------- -#define AT91C_ADC_EOC0 ((unsigned int) 0x1 << 0) // (ADC) End of Conversion -#define AT91C_ADC_EOC1 ((unsigned int) 0x1 << 1) // (ADC) End of Conversion -#define AT91C_ADC_EOC2 ((unsigned int) 0x1 << 2) // (ADC) End of Conversion -#define AT91C_ADC_EOC3 ((unsigned int) 0x1 << 3) // (ADC) End of Conversion -#define AT91C_ADC_EOC4 ((unsigned int) 0x1 << 4) // (ADC) End of Conversion -#define AT91C_ADC_EOC5 ((unsigned int) 0x1 << 5) // (ADC) End of Conversion -#define AT91C_ADC_EOC6 ((unsigned int) 0x1 << 6) // (ADC) End of Conversion -#define AT91C_ADC_EOC7 ((unsigned int) 0x1 << 7) // (ADC) End of Conversion -#define AT91C_ADC_OVRE0 ((unsigned int) 0x1 << 8) // (ADC) Overrun Error -#define AT91C_ADC_OVRE1 ((unsigned int) 0x1 << 9) // (ADC) Overrun Error -#define AT91C_ADC_OVRE2 ((unsigned int) 0x1 << 10) // (ADC) Overrun Error -#define AT91C_ADC_OVRE3 ((unsigned int) 0x1 << 11) // (ADC) Overrun Error -#define AT91C_ADC_OVRE4 ((unsigned int) 0x1 << 12) // (ADC) Overrun Error -#define AT91C_ADC_OVRE5 ((unsigned int) 0x1 << 13) // (ADC) Overrun Error -#define AT91C_ADC_OVRE6 ((unsigned int) 0x1 << 14) // (ADC) Overrun Error -#define AT91C_ADC_OVRE7 ((unsigned int) 0x1 << 15) // (ADC) Overrun Error -#define AT91C_ADC_DRDY ((unsigned int) 0x1 << 16) // (ADC) Data Ready -#define AT91C_ADC_GOVRE ((unsigned int) 0x1 << 17) // (ADC) General Overrun -#define AT91C_ADC_ENDRX ((unsigned int) 0x1 << 18) // (ADC) End of Receiver Transfer -#define AT91C_ADC_RXBUFF ((unsigned int) 0x1 << 19) // (ADC) RXBUFF Interrupt -// -------- ADC_LCDR : (ADC Offset: 0x20) ADC Last Converted Data Register -------- -#define AT91C_ADC_LDATA ((unsigned int) 0x3FF << 0) // (ADC) Last Data Converted -// -------- ADC_IER : (ADC Offset: 0x24) ADC Interrupt Enable Register -------- -// -------- ADC_IDR : (ADC Offset: 0x28) ADC Interrupt Disable Register -------- -// -------- ADC_IMR : (ADC Offset: 0x2c) ADC Interrupt Mask Register -------- -// -------- ADC_CDR0 : (ADC Offset: 0x30) ADC Channel Data Register 0 -------- -#define AT91C_ADC_DATA ((unsigned int) 0x3FF << 0) // (ADC) Converted Data -// -------- ADC_CDR1 : (ADC Offset: 0x34) ADC Channel Data Register 1 -------- -// -------- ADC_CDR2 : (ADC Offset: 0x38) ADC Channel Data Register 2 -------- -// -------- ADC_CDR3 : (ADC Offset: 0x3c) ADC Channel Data Register 3 -------- -// -------- ADC_CDR4 : (ADC Offset: 0x40) ADC Channel Data Register 4 -------- -// -------- ADC_CDR5 : (ADC Offset: 0x44) ADC Channel Data Register 5 -------- -// -------- ADC_CDR6 : (ADC Offset: 0x48) ADC Channel Data Register 6 -------- -// -------- ADC_CDR7 : (ADC Offset: 0x4c) ADC Channel Data Register 7 -------- +/* -------- ADC_CR : (ADC Offset: 0x0) ADC Control Register -------- */ +#define AT91C_ADC_SWRST ( ( unsigned int ) 0x1 << 0 ) /* (ADC) Software Reset */ +#define AT91C_ADC_START ( ( unsigned int ) 0x1 << 1 ) /* (ADC) Start Conversion */ +/* -------- ADC_MR : (ADC Offset: 0x4) ADC Mode Register -------- */ +#define AT91C_ADC_TRGEN ( ( unsigned int ) 0x1 << 0 ) /* (ADC) Trigger Enable */ +#define AT91C_ADC_TRGEN_DIS ( ( unsigned int ) 0x0 ) /* (ADC) Hardware triggers are disabled. Starting a conversion is only possible by software */ +#define AT91C_ADC_TRGEN_EN ( ( unsigned int ) 0x1 ) /* (ADC) Hardware trigger selected by TRGSEL field is enabled. */ +#define AT91C_ADC_TRGSEL ( ( unsigned int ) 0x7 << 1 ) /* (ADC) Trigger Selection */ +#define AT91C_ADC_TRGSEL_TIOA0 ( ( unsigned int ) 0x0 << 1 ) /* (ADC) Selected TRGSEL = TIAO0 */ +#define AT91C_ADC_TRGSEL_TIOA1 ( ( unsigned int ) 0x1 << 1 ) /* (ADC) Selected TRGSEL = TIAO1 */ +#define AT91C_ADC_TRGSEL_TIOA2 ( ( unsigned int ) 0x2 << 1 ) /* (ADC) Selected TRGSEL = TIAO2 */ +#define AT91C_ADC_TRGSEL_TIOA3 ( ( unsigned int ) 0x3 << 1 ) /* (ADC) Selected TRGSEL = TIAO3 */ +#define AT91C_ADC_TRGSEL_TIOA4 ( ( unsigned int ) 0x4 << 1 ) /* (ADC) Selected TRGSEL = TIAO4 */ +#define AT91C_ADC_TRGSEL_TIOA5 ( ( unsigned int ) 0x5 << 1 ) /* (ADC) Selected TRGSEL = TIAO5 */ +#define AT91C_ADC_TRGSEL_EXT ( ( unsigned int ) 0x6 << 1 ) /* (ADC) Selected TRGSEL = External Trigger */ +#define AT91C_ADC_LOWRES ( ( unsigned int ) 0x1 << 4 ) /* (ADC) Resolution. */ +#define AT91C_ADC_LOWRES_10_BIT ( ( unsigned int ) 0x0 << 4 ) /* (ADC) 10-bit resolution */ +#define AT91C_ADC_LOWRES_8_BIT ( ( unsigned int ) 0x1 << 4 ) /* (ADC) 8-bit resolution */ +#define AT91C_ADC_SLEEP ( ( unsigned int ) 0x1 << 5 ) /* (ADC) Sleep Mode */ +#define AT91C_ADC_SLEEP_NORMAL_MODE ( ( unsigned int ) 0x0 << 5 ) /* (ADC) Normal Mode */ +#define AT91C_ADC_SLEEP_MODE ( ( unsigned int ) 0x1 << 5 ) /* (ADC) Sleep Mode */ +#define AT91C_ADC_PRESCAL ( ( unsigned int ) 0x3F << 8 ) /* (ADC) Prescaler rate selection */ +#define AT91C_ADC_STARTUP ( ( unsigned int ) 0x1F << 16 ) /* (ADC) Startup Time */ +#define AT91C_ADC_SHTIM ( ( unsigned int ) 0xF << 24 ) /* (ADC) Sample & Hold Time */ +/* -------- ADC_CHER : (ADC Offset: 0x10) ADC Channel Enable Register -------- */ +#define AT91C_ADC_CH0 ( ( unsigned int ) 0x1 << 0 ) /* (ADC) Channel 0 */ +#define AT91C_ADC_CH1 ( ( unsigned int ) 0x1 << 1 ) /* (ADC) Channel 1 */ +#define AT91C_ADC_CH2 ( ( unsigned int ) 0x1 << 2 ) /* (ADC) Channel 2 */ +#define AT91C_ADC_CH3 ( ( unsigned int ) 0x1 << 3 ) /* (ADC) Channel 3 */ +#define AT91C_ADC_CH4 ( ( unsigned int ) 0x1 << 4 ) /* (ADC) Channel 4 */ +#define AT91C_ADC_CH5 ( ( unsigned int ) 0x1 << 5 ) /* (ADC) Channel 5 */ +#define AT91C_ADC_CH6 ( ( unsigned int ) 0x1 << 6 ) /* (ADC) Channel 6 */ +#define AT91C_ADC_CH7 ( ( unsigned int ) 0x1 << 7 ) /* (ADC) Channel 7 */ +/* -------- ADC_CHDR : (ADC Offset: 0x14) ADC Channel Disable Register -------- */ +/* -------- ADC_CHSR : (ADC Offset: 0x18) ADC Channel Status Register -------- */ +/* -------- ADC_SR : (ADC Offset: 0x1c) ADC Status Register -------- */ +#define AT91C_ADC_EOC0 ( ( unsigned int ) 0x1 << 0 ) /* (ADC) End of Conversion */ +#define AT91C_ADC_EOC1 ( ( unsigned int ) 0x1 << 1 ) /* (ADC) End of Conversion */ +#define AT91C_ADC_EOC2 ( ( unsigned int ) 0x1 << 2 ) /* (ADC) End of Conversion */ +#define AT91C_ADC_EOC3 ( ( unsigned int ) 0x1 << 3 ) /* (ADC) End of Conversion */ +#define AT91C_ADC_EOC4 ( ( unsigned int ) 0x1 << 4 ) /* (ADC) End of Conversion */ +#define AT91C_ADC_EOC5 ( ( unsigned int ) 0x1 << 5 ) /* (ADC) End of Conversion */ +#define AT91C_ADC_EOC6 ( ( unsigned int ) 0x1 << 6 ) /* (ADC) End of Conversion */ +#define AT91C_ADC_EOC7 ( ( unsigned int ) 0x1 << 7 ) /* (ADC) End of Conversion */ +#define AT91C_ADC_OVRE0 ( ( unsigned int ) 0x1 << 8 ) /* (ADC) Overrun Error */ +#define AT91C_ADC_OVRE1 ( ( unsigned int ) 0x1 << 9 ) /* (ADC) Overrun Error */ +#define AT91C_ADC_OVRE2 ( ( unsigned int ) 0x1 << 10 ) /* (ADC) Overrun Error */ +#define AT91C_ADC_OVRE3 ( ( unsigned int ) 0x1 << 11 ) /* (ADC) Overrun Error */ +#define AT91C_ADC_OVRE4 ( ( unsigned int ) 0x1 << 12 ) /* (ADC) Overrun Error */ +#define AT91C_ADC_OVRE5 ( ( unsigned int ) 0x1 << 13 ) /* (ADC) Overrun Error */ +#define AT91C_ADC_OVRE6 ( ( unsigned int ) 0x1 << 14 ) /* (ADC) Overrun Error */ +#define AT91C_ADC_OVRE7 ( ( unsigned int ) 0x1 << 15 ) /* (ADC) Overrun Error */ +#define AT91C_ADC_DRDY ( ( unsigned int ) 0x1 << 16 ) /* (ADC) Data Ready */ +#define AT91C_ADC_GOVRE ( ( unsigned int ) 0x1 << 17 ) /* (ADC) General Overrun */ +#define AT91C_ADC_ENDRX ( ( unsigned int ) 0x1 << 18 ) /* (ADC) End of Receiver Transfer */ +#define AT91C_ADC_RXBUFF ( ( unsigned int ) 0x1 << 19 ) /* (ADC) RXBUFF Interrupt */ +/* -------- ADC_LCDR : (ADC Offset: 0x20) ADC Last Converted Data Register -------- */ +#define AT91C_ADC_LDATA ( ( unsigned int ) 0x3FF << 0 ) /* (ADC) Last Data Converted */ +/* -------- ADC_IER : (ADC Offset: 0x24) ADC Interrupt Enable Register -------- */ +/* -------- ADC_IDR : (ADC Offset: 0x28) ADC Interrupt Disable Register -------- */ +/* -------- ADC_IMR : (ADC Offset: 0x2c) ADC Interrupt Mask Register -------- */ +/* -------- ADC_CDR0 : (ADC Offset: 0x30) ADC Channel Data Register 0 -------- */ +#define AT91C_ADC_DATA ( ( unsigned int ) 0x3FF << 0 ) /* (ADC) Converted Data */ +/* -------- ADC_CDR1 : (ADC Offset: 0x34) ADC Channel Data Register 1 -------- */ +/* -------- ADC_CDR2 : (ADC Offset: 0x38) ADC Channel Data Register 2 -------- */ +/* -------- ADC_CDR3 : (ADC Offset: 0x3c) ADC Channel Data Register 3 -------- */ +/* -------- ADC_CDR4 : (ADC Offset: 0x40) ADC Channel Data Register 4 -------- */ +/* -------- ADC_CDR5 : (ADC Offset: 0x44) ADC Channel Data Register 5 -------- */ +/* -------- ADC_CDR6 : (ADC Offset: 0x48) ADC Channel Data Register 6 -------- */ +/* -------- ADC_CDR7 : (ADC Offset: 0x4c) ADC Channel Data Register 7 -------- */ -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Synchronous Serial Controller Interface -// ***************************************************************************** -typedef struct _AT91S_SSC { - AT91_REG SSC_CR; // Control Register - AT91_REG SSC_CMR; // Clock Mode Register - AT91_REG Reserved0[2]; // - AT91_REG SSC_RCMR; // Receive Clock ModeRegister - AT91_REG SSC_RFMR; // Receive Frame Mode Register - AT91_REG SSC_TCMR; // Transmit Clock Mode Register - AT91_REG SSC_TFMR; // Transmit Frame Mode Register - AT91_REG SSC_RHR; // Receive Holding Register - AT91_REG SSC_THR; // Transmit Holding Register - AT91_REG Reserved1[2]; // - AT91_REG SSC_RSHR; // Receive Sync Holding Register - AT91_REG SSC_TSHR; // Transmit Sync Holding Register - AT91_REG SSC_RC0R; // Receive Compare 0 Register - AT91_REG SSC_RC1R; // Receive Compare 1 Register - AT91_REG SSC_SR; // Status Register - AT91_REG SSC_IER; // Interrupt Enable Register - AT91_REG SSC_IDR; // Interrupt Disable Register - AT91_REG SSC_IMR; // Interrupt Mask Register - AT91_REG Reserved2[44]; // - AT91_REG SSC_RPR; // Receive Pointer Register - AT91_REG SSC_RCR; // Receive Counter Register - AT91_REG SSC_TPR; // Transmit Pointer Register - AT91_REG SSC_TCR; // Transmit Counter Register - AT91_REG SSC_RNPR; // Receive Next Pointer Register - AT91_REG SSC_RNCR; // Receive Next Counter Register - AT91_REG SSC_TNPR; // Transmit Next Pointer Register - AT91_REG SSC_TNCR; // Transmit Next Counter Register - AT91_REG SSC_PTCR; // PDC Transfer Control Register - AT91_REG SSC_PTSR; // PDC Transfer Status Register -} AT91S_SSC, *AT91PS_SSC; +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR Synchronous Serial Controller Interface */ +/* ***************************************************************************** */ +typedef struct _AT91S_SSC +{ + AT91_REG SSC_CR; /* Control Register */ + AT91_REG SSC_CMR; /* Clock Mode Register */ + AT91_REG Reserved0[ 2 ]; /* */ + AT91_REG SSC_RCMR; /* Receive Clock ModeRegister */ + AT91_REG SSC_RFMR; /* Receive Frame Mode Register */ + AT91_REG SSC_TCMR; /* Transmit Clock Mode Register */ + AT91_REG SSC_TFMR; /* Transmit Frame Mode Register */ + AT91_REG SSC_RHR; /* Receive Holding Register */ + AT91_REG SSC_THR; /* Transmit Holding Register */ + AT91_REG Reserved1[ 2 ]; /* */ + AT91_REG SSC_RSHR; /* Receive Sync Holding Register */ + AT91_REG SSC_TSHR; /* Transmit Sync Holding Register */ + AT91_REG SSC_RC0R; /* Receive Compare 0 Register */ + AT91_REG SSC_RC1R; /* Receive Compare 1 Register */ + AT91_REG SSC_SR; /* Status Register */ + AT91_REG SSC_IER; /* Interrupt Enable Register */ + AT91_REG SSC_IDR; /* Interrupt Disable Register */ + AT91_REG SSC_IMR; /* Interrupt Mask Register */ + AT91_REG Reserved2[ 44 ]; /* */ + AT91_REG SSC_RPR; /* Receive Pointer Register */ + AT91_REG SSC_RCR; /* Receive Counter Register */ + AT91_REG SSC_TPR; /* Transmit Pointer Register */ + AT91_REG SSC_TCR; /* Transmit Counter Register */ + AT91_REG SSC_RNPR; /* Receive Next Pointer Register */ + AT91_REG SSC_RNCR; /* Receive Next Counter Register */ + AT91_REG SSC_TNPR; /* Transmit Next Pointer Register */ + AT91_REG SSC_TNCR; /* Transmit Next Counter Register */ + AT91_REG SSC_PTCR; /* PDC Transfer Control Register */ + AT91_REG SSC_PTSR; /* PDC Transfer Status Register */ +} AT91S_SSC, * AT91PS_SSC; -// -------- SSC_CR : (SSC Offset: 0x0) SSC Control Register -------- -#define AT91C_SSC_RXEN ((unsigned int) 0x1 << 0) // (SSC) Receive Enable -#define AT91C_SSC_RXDIS ((unsigned int) 0x1 << 1) // (SSC) Receive Disable -#define AT91C_SSC_TXEN ((unsigned int) 0x1 << 8) // (SSC) Transmit Enable -#define AT91C_SSC_TXDIS ((unsigned int) 0x1 << 9) // (SSC) Transmit Disable -#define AT91C_SSC_SWRST ((unsigned int) 0x1 << 15) // (SSC) Software Reset -// -------- SSC_RCMR : (SSC Offset: 0x10) SSC Receive Clock Mode Register -------- -#define AT91C_SSC_CKS ((unsigned int) 0x3 << 0) // (SSC) Receive/Transmit Clock Selection -#define AT91C_SSC_CKS_DIV ((unsigned int) 0x0) // (SSC) Divided Clock -#define AT91C_SSC_CKS_TK ((unsigned int) 0x1) // (SSC) TK Clock signal -#define AT91C_SSC_CKS_RK ((unsigned int) 0x2) // (SSC) RK pin -#define AT91C_SSC_CKO ((unsigned int) 0x7 << 2) // (SSC) Receive/Transmit Clock Output Mode Selection -#define AT91C_SSC_CKO_NONE ((unsigned int) 0x0 << 2) // (SSC) Receive/Transmit Clock Output Mode: None RK pin: Input-only -#define AT91C_SSC_CKO_CONTINOUS ((unsigned int) 0x1 << 2) // (SSC) Continuous Receive/Transmit Clock RK pin: Output -#define AT91C_SSC_CKO_DATA_TX ((unsigned int) 0x2 << 2) // (SSC) Receive/Transmit Clock only during data transfers RK pin: Output -#define AT91C_SSC_CKI ((unsigned int) 0x1 << 5) // (SSC) Receive/Transmit Clock Inversion -#define AT91C_SSC_CKG ((unsigned int) 0x3 << 6) // (SSC) Receive/Transmit Clock Gating Selection -#define AT91C_SSC_CKG_NONE ((unsigned int) 0x0 << 6) // (SSC) Receive/Transmit Clock Gating: None, continuous clock -#define AT91C_SSC_CKG_LOW ((unsigned int) 0x1 << 6) // (SSC) Receive/Transmit Clock enabled only if RF Low -#define AT91C_SSC_CKG_HIGH ((unsigned int) 0x2 << 6) // (SSC) Receive/Transmit Clock enabled only if RF High -#define AT91C_SSC_START ((unsigned int) 0xF << 8) // (SSC) Receive/Transmit Start Selection -#define AT91C_SSC_START_CONTINOUS ((unsigned int) 0x0 << 8) // (SSC) Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data. -#define AT91C_SSC_START_TX ((unsigned int) 0x1 << 8) // (SSC) Transmit/Receive start -#define AT91C_SSC_START_LOW_RF ((unsigned int) 0x2 << 8) // (SSC) Detection of a low level on RF input -#define AT91C_SSC_START_HIGH_RF ((unsigned int) 0x3 << 8) // (SSC) Detection of a high level on RF input -#define AT91C_SSC_START_FALL_RF ((unsigned int) 0x4 << 8) // (SSC) Detection of a falling edge on RF input -#define AT91C_SSC_START_RISE_RF ((unsigned int) 0x5 << 8) // (SSC) Detection of a rising edge on RF input -#define AT91C_SSC_START_LEVEL_RF ((unsigned int) 0x6 << 8) // (SSC) Detection of any level change on RF input -#define AT91C_SSC_START_EDGE_RF ((unsigned int) 0x7 << 8) // (SSC) Detection of any edge on RF input -#define AT91C_SSC_START_0 ((unsigned int) 0x8 << 8) // (SSC) Compare 0 -#define AT91C_SSC_STOP ((unsigned int) 0x1 << 12) // (SSC) Receive Stop Selection -#define AT91C_SSC_STTOUT ((unsigned int) 0x1 << 15) // (SSC) Receive/Transmit Start Output Selection -#define AT91C_SSC_STTDLY ((unsigned int) 0xFF << 16) // (SSC) Receive/Transmit Start Delay -#define AT91C_SSC_PERIOD ((unsigned int) 0xFF << 24) // (SSC) Receive/Transmit Period Divider Selection -// -------- SSC_RFMR : (SSC Offset: 0x14) SSC Receive Frame Mode Register -------- -#define AT91C_SSC_DATLEN ((unsigned int) 0x1F << 0) // (SSC) Data Length -#define AT91C_SSC_LOOP ((unsigned int) 0x1 << 5) // (SSC) Loop Mode -#define AT91C_SSC_MSBF ((unsigned int) 0x1 << 7) // (SSC) Most Significant Bit First -#define AT91C_SSC_DATNB ((unsigned int) 0xF << 8) // (SSC) Data Number per Frame -#define AT91C_SSC_FSLEN ((unsigned int) 0xF << 16) // (SSC) Receive/Transmit Frame Sync length -#define AT91C_SSC_FSOS ((unsigned int) 0x7 << 20) // (SSC) Receive/Transmit Frame Sync Output Selection -#define AT91C_SSC_FSOS_NONE ((unsigned int) 0x0 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: None RK pin Input-only -#define AT91C_SSC_FSOS_NEGATIVE ((unsigned int) 0x1 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Negative Pulse -#define AT91C_SSC_FSOS_POSITIVE ((unsigned int) 0x2 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Positive Pulse -#define AT91C_SSC_FSOS_LOW ((unsigned int) 0x3 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver Low during data transfer -#define AT91C_SSC_FSOS_HIGH ((unsigned int) 0x4 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver High during data transfer -#define AT91C_SSC_FSOS_TOGGLE ((unsigned int) 0x5 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Toggling at each start of data transfer -#define AT91C_SSC_FSEDGE ((unsigned int) 0x1 << 24) // (SSC) Frame Sync Edge Detection -// -------- SSC_TCMR : (SSC Offset: 0x18) SSC Transmit Clock Mode Register -------- -// -------- SSC_TFMR : (SSC Offset: 0x1c) SSC Transmit Frame Mode Register -------- -#define AT91C_SSC_DATDEF ((unsigned int) 0x1 << 5) // (SSC) Data Default Value -#define AT91C_SSC_FSDEN ((unsigned int) 0x1 << 23) // (SSC) Frame Sync Data Enable -// -------- SSC_SR : (SSC Offset: 0x40) SSC Status Register -------- -#define AT91C_SSC_TXRDY ((unsigned int) 0x1 << 0) // (SSC) Transmit Ready -#define AT91C_SSC_TXEMPTY ((unsigned int) 0x1 << 1) // (SSC) Transmit Empty -#define AT91C_SSC_ENDTX ((unsigned int) 0x1 << 2) // (SSC) End Of Transmission -#define AT91C_SSC_TXBUFE ((unsigned int) 0x1 << 3) // (SSC) Transmit Buffer Empty -#define AT91C_SSC_RXRDY ((unsigned int) 0x1 << 4) // (SSC) Receive Ready -#define AT91C_SSC_OVRUN ((unsigned int) 0x1 << 5) // (SSC) Receive Overrun -#define AT91C_SSC_ENDRX ((unsigned int) 0x1 << 6) // (SSC) End of Reception -#define AT91C_SSC_RXBUFF ((unsigned int) 0x1 << 7) // (SSC) Receive Buffer Full -#define AT91C_SSC_CP0 ((unsigned int) 0x1 << 8) // (SSC) Compare 0 -#define AT91C_SSC_CP1 ((unsigned int) 0x1 << 9) // (SSC) Compare 1 -#define AT91C_SSC_TXSYN ((unsigned int) 0x1 << 10) // (SSC) Transmit Sync -#define AT91C_SSC_RXSYN ((unsigned int) 0x1 << 11) // (SSC) Receive Sync -#define AT91C_SSC_TXENA ((unsigned int) 0x1 << 16) // (SSC) Transmit Enable -#define AT91C_SSC_RXENA ((unsigned int) 0x1 << 17) // (SSC) Receive Enable -// -------- SSC_IER : (SSC Offset: 0x44) SSC Interrupt Enable Register -------- -// -------- SSC_IDR : (SSC Offset: 0x48) SSC Interrupt Disable Register -------- -// -------- SSC_IMR : (SSC Offset: 0x4c) SSC Interrupt Mask Register -------- +/* -------- SSC_CR : (SSC Offset: 0x0) SSC Control Register -------- */ +#define AT91C_SSC_RXEN ( ( unsigned int ) 0x1 << 0 ) /* (SSC) Receive Enable */ +#define AT91C_SSC_RXDIS ( ( unsigned int ) 0x1 << 1 ) /* (SSC) Receive Disable */ +#define AT91C_SSC_TXEN ( ( unsigned int ) 0x1 << 8 ) /* (SSC) Transmit Enable */ +#define AT91C_SSC_TXDIS ( ( unsigned int ) 0x1 << 9 ) /* (SSC) Transmit Disable */ +#define AT91C_SSC_SWRST ( ( unsigned int ) 0x1 << 15 ) /* (SSC) Software Reset */ +/* -------- SSC_RCMR : (SSC Offset: 0x10) SSC Receive Clock Mode Register -------- */ +#define AT91C_SSC_CKS ( ( unsigned int ) 0x3 << 0 ) /* (SSC) Receive/Transmit Clock Selection */ +#define AT91C_SSC_CKS_DIV ( ( unsigned int ) 0x0 ) /* (SSC) Divided Clock */ +#define AT91C_SSC_CKS_TK ( ( unsigned int ) 0x1 ) /* (SSC) TK Clock signal */ +#define AT91C_SSC_CKS_RK ( ( unsigned int ) 0x2 ) /* (SSC) RK pin */ +#define AT91C_SSC_CKO ( ( unsigned int ) 0x7 << 2 ) /* (SSC) Receive/Transmit Clock Output Mode Selection */ +#define AT91C_SSC_CKO_NONE ( ( unsigned int ) 0x0 << 2 ) /* (SSC) Receive/Transmit Clock Output Mode: None RK pin: Input-only */ +#define AT91C_SSC_CKO_CONTINUOUS ( ( unsigned int ) 0x1 << 2 ) /* (SSC) Continuous Receive/Transmit Clock RK pin: Output */ +#define AT91C_SSC_CKO_DATA_TX ( ( unsigned int ) 0x2 << 2 ) /* (SSC) Receive/Transmit Clock only during data transfers RK pin: Output */ +#define AT91C_SSC_CKI ( ( unsigned int ) 0x1 << 5 ) /* (SSC) Receive/Transmit Clock Inversion */ +#define AT91C_SSC_CKG ( ( unsigned int ) 0x3 << 6 ) /* (SSC) Receive/Transmit Clock Gating Selection */ +#define AT91C_SSC_CKG_NONE ( ( unsigned int ) 0x0 << 6 ) /* (SSC) Receive/Transmit Clock Gating: None, continuous clock */ +#define AT91C_SSC_CKG_LOW ( ( unsigned int ) 0x1 << 6 ) /* (SSC) Receive/Transmit Clock enabled only if RF Low */ +#define AT91C_SSC_CKG_HIGH ( ( unsigned int ) 0x2 << 6 ) /* (SSC) Receive/Transmit Clock enabled only if RF High */ +#define AT91C_SSC_START ( ( unsigned int ) 0xF << 8 ) /* (SSC) Receive/Transmit Start Selection */ +#define AT91C_SSC_START_CONTINUOUS ( ( unsigned int ) 0x0 << 8 ) /* (SSC) Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data. */ +#define AT91C_SSC_START_TX ( ( unsigned int ) 0x1 << 8 ) /* (SSC) Transmit/Receive start */ +#define AT91C_SSC_START_LOW_RF ( ( unsigned int ) 0x2 << 8 ) /* (SSC) Detection of a low level on RF input */ +#define AT91C_SSC_START_HIGH_RF ( ( unsigned int ) 0x3 << 8 ) /* (SSC) Detection of a high level on RF input */ +#define AT91C_SSC_START_FALL_RF ( ( unsigned int ) 0x4 << 8 ) /* (SSC) Detection of a falling edge on RF input */ +#define AT91C_SSC_START_RISE_RF ( ( unsigned int ) 0x5 << 8 ) /* (SSC) Detection of a rising edge on RF input */ +#define AT91C_SSC_START_LEVEL_RF ( ( unsigned int ) 0x6 << 8 ) /* (SSC) Detection of any level change on RF input */ +#define AT91C_SSC_START_EDGE_RF ( ( unsigned int ) 0x7 << 8 ) /* (SSC) Detection of any edge on RF input */ +#define AT91C_SSC_START_0 ( ( unsigned int ) 0x8 << 8 ) /* (SSC) Compare 0 */ +#define AT91C_SSC_STOP ( ( unsigned int ) 0x1 << 12 ) /* (SSC) Receive Stop Selection */ +#define AT91C_SSC_STTOUT ( ( unsigned int ) 0x1 << 15 ) /* (SSC) Receive/Transmit Start Output Selection */ +#define AT91C_SSC_STTDLY ( ( unsigned int ) 0xFF << 16 ) /* (SSC) Receive/Transmit Start Delay */ +#define AT91C_SSC_PERIOD ( ( unsigned int ) 0xFF << 24 ) /* (SSC) Receive/Transmit Period Divider Selection */ +/* -------- SSC_RFMR : (SSC Offset: 0x14) SSC Receive Frame Mode Register -------- */ +#define AT91C_SSC_DATLEN ( ( unsigned int ) 0x1F << 0 ) /* (SSC) Data Length */ +#define AT91C_SSC_LOOP ( ( unsigned int ) 0x1 << 5 ) /* (SSC) Loop Mode */ +#define AT91C_SSC_MSBF ( ( unsigned int ) 0x1 << 7 ) /* (SSC) Most Significant Bit First */ +#define AT91C_SSC_DATNB ( ( unsigned int ) 0xF << 8 ) /* (SSC) Data Number per Frame */ +#define AT91C_SSC_FSLEN ( ( unsigned int ) 0xF << 16 ) /* (SSC) Receive/Transmit Frame Sync length */ +#define AT91C_SSC_FSOS ( ( unsigned int ) 0x7 << 20 ) /* (SSC) Receive/Transmit Frame Sync Output Selection */ +#define AT91C_SSC_FSOS_NONE ( ( unsigned int ) 0x0 << 20 ) /* (SSC) Selected Receive/Transmit Frame Sync Signal: None RK pin Input-only */ +#define AT91C_SSC_FSOS_NEGATIVE ( ( unsigned int ) 0x1 << 20 ) /* (SSC) Selected Receive/Transmit Frame Sync Signal: Negative Pulse */ +#define AT91C_SSC_FSOS_POSITIVE ( ( unsigned int ) 0x2 << 20 ) /* (SSC) Selected Receive/Transmit Frame Sync Signal: Positive Pulse */ +#define AT91C_SSC_FSOS_LOW ( ( unsigned int ) 0x3 << 20 ) /* (SSC) Selected Receive/Transmit Frame Sync Signal: Driver Low during data transfer */ +#define AT91C_SSC_FSOS_HIGH ( ( unsigned int ) 0x4 << 20 ) /* (SSC) Selected Receive/Transmit Frame Sync Signal: Driver High during data transfer */ +#define AT91C_SSC_FSOS_TOGGLE ( ( unsigned int ) 0x5 << 20 ) /* (SSC) Selected Receive/Transmit Frame Sync Signal: Toggling at each start of data transfer */ +#define AT91C_SSC_FSEDGE ( ( unsigned int ) 0x1 << 24 ) /* (SSC) Frame Sync Edge Detection */ +/* -------- SSC_TCMR : (SSC Offset: 0x18) SSC Transmit Clock Mode Register -------- */ +/* -------- SSC_TFMR : (SSC Offset: 0x1c) SSC Transmit Frame Mode Register -------- */ +#define AT91C_SSC_DATDEF ( ( unsigned int ) 0x1 << 5 ) /* (SSC) Data Default Value */ +#define AT91C_SSC_FSDEN ( ( unsigned int ) 0x1 << 23 ) /* (SSC) Frame Sync Data Enable */ +/* -------- SSC_SR : (SSC Offset: 0x40) SSC Status Register -------- */ +#define AT91C_SSC_TXRDY ( ( unsigned int ) 0x1 << 0 ) /* (SSC) Transmit Ready */ +#define AT91C_SSC_TXEMPTY ( ( unsigned int ) 0x1 << 1 ) /* (SSC) Transmit Empty */ +#define AT91C_SSC_ENDTX ( ( unsigned int ) 0x1 << 2 ) /* (SSC) End Of Transmission */ +#define AT91C_SSC_TXBUFE ( ( unsigned int ) 0x1 << 3 ) /* (SSC) Transmit Buffer Empty */ +#define AT91C_SSC_RXRDY ( ( unsigned int ) 0x1 << 4 ) /* (SSC) Receive Ready */ +#define AT91C_SSC_OVRUN ( ( unsigned int ) 0x1 << 5 ) /* (SSC) Receive Overrun */ +#define AT91C_SSC_ENDRX ( ( unsigned int ) 0x1 << 6 ) /* (SSC) End of Reception */ +#define AT91C_SSC_RXBUFF ( ( unsigned int ) 0x1 << 7 ) /* (SSC) Receive Buffer Full */ +#define AT91C_SSC_CP0 ( ( unsigned int ) 0x1 << 8 ) /* (SSC) Compare 0 */ +#define AT91C_SSC_CP1 ( ( unsigned int ) 0x1 << 9 ) /* (SSC) Compare 1 */ +#define AT91C_SSC_TXSYN ( ( unsigned int ) 0x1 << 10 ) /* (SSC) Transmit Sync */ +#define AT91C_SSC_RXSYN ( ( unsigned int ) 0x1 << 11 ) /* (SSC) Receive Sync */ +#define AT91C_SSC_TXENA ( ( unsigned int ) 0x1 << 16 ) /* (SSC) Transmit Enable */ +#define AT91C_SSC_RXENA ( ( unsigned int ) 0x1 << 17 ) /* (SSC) Receive Enable */ +/* -------- SSC_IER : (SSC Offset: 0x44) SSC Interrupt Enable Register -------- */ +/* -------- SSC_IDR : (SSC Offset: 0x48) SSC Interrupt Disable Register -------- */ +/* -------- SSC_IMR : (SSC Offset: 0x4c) SSC Interrupt Mask Register -------- */ -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Usart -// ***************************************************************************** -typedef struct _AT91S_USART { - AT91_REG US_CR; // Control Register - AT91_REG US_MR; // Mode Register - AT91_REG US_IER; // Interrupt Enable Register - AT91_REG US_IDR; // Interrupt Disable Register - AT91_REG US_IMR; // Interrupt Mask Register - AT91_REG US_CSR; // Channel Status Register - AT91_REG US_RHR; // Receiver Holding Register - AT91_REG US_THR; // Transmitter Holding Register - AT91_REG US_BRGR; // Baud Rate Generator Register - AT91_REG US_RTOR; // Receiver Time-out Register - AT91_REG US_TTGR; // Transmitter Time-guard Register - AT91_REG Reserved0[5]; // - AT91_REG US_FIDI; // FI_DI_Ratio Register - AT91_REG US_NER; // Nb Errors Register - AT91_REG US_XXR; // XON_XOFF Register - AT91_REG US_IF; // IRDA_FILTER Register - AT91_REG Reserved1[44]; // - AT91_REG US_RPR; // Receive Pointer Register - AT91_REG US_RCR; // Receive Counter Register - AT91_REG US_TPR; // Transmit Pointer Register - AT91_REG US_TCR; // Transmit Counter Register - AT91_REG US_RNPR; // Receive Next Pointer Register - AT91_REG US_RNCR; // Receive Next Counter Register - AT91_REG US_TNPR; // Transmit Next Pointer Register - AT91_REG US_TNCR; // Transmit Next Counter Register - AT91_REG US_PTCR; // PDC Transfer Control Register - AT91_REG US_PTSR; // PDC Transfer Status Register -} AT91S_USART, *AT91PS_USART; +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR Usart */ +/* ***************************************************************************** */ +typedef struct _AT91S_USART +{ + AT91_REG US_CR; /* Control Register */ + AT91_REG US_MR; /* Mode Register */ + AT91_REG US_IER; /* Interrupt Enable Register */ + AT91_REG US_IDR; /* Interrupt Disable Register */ + AT91_REG US_IMR; /* Interrupt Mask Register */ + AT91_REG US_CSR; /* Channel Status Register */ + AT91_REG US_RHR; /* Receiver Holding Register */ + AT91_REG US_THR; /* Transmitter Holding Register */ + AT91_REG US_BRGR; /* Baud Rate Generator Register */ + AT91_REG US_RTOR; /* Receiver Time-out Register */ + AT91_REG US_TTGR; /* Transmitter Time-guard Register */ + AT91_REG Reserved0[ 5 ]; /* */ + AT91_REG US_FIDI; /* FI_DI_Ratio Register */ + AT91_REG US_NER; /* Nb Errors Register */ + AT91_REG US_XXR; /* XON_XOFF Register */ + AT91_REG US_IF; /* IRDA_FILTER Register */ + AT91_REG Reserved1[ 44 ]; /* */ + AT91_REG US_RPR; /* Receive Pointer Register */ + AT91_REG US_RCR; /* Receive Counter Register */ + AT91_REG US_TPR; /* Transmit Pointer Register */ + AT91_REG US_TCR; /* Transmit Counter Register */ + AT91_REG US_RNPR; /* Receive Next Pointer Register */ + AT91_REG US_RNCR; /* Receive Next Counter Register */ + AT91_REG US_TNPR; /* Transmit Next Pointer Register */ + AT91_REG US_TNCR; /* Transmit Next Counter Register */ + AT91_REG US_PTCR; /* PDC Transfer Control Register */ + AT91_REG US_PTSR; /* PDC Transfer Status Register */ +} AT91S_USART, * AT91PS_USART; -// -------- US_CR : (USART Offset: 0x0) Debug Unit Control Register -------- -#define AT91C_US_RSTSTA ((unsigned int) 0x1 << 8) // (USART) Reset Status Bits -#define AT91C_US_STTBRK ((unsigned int) 0x1 << 9) // (USART) Start Break -#define AT91C_US_STPBRK ((unsigned int) 0x1 << 10) // (USART) Stop Break -#define AT91C_US_STTTO ((unsigned int) 0x1 << 11) // (USART) Start Time-out -#define AT91C_US_SENDA ((unsigned int) 0x1 << 12) // (USART) Send Address -#define AT91C_US_RSTIT ((unsigned int) 0x1 << 13) // (USART) Reset Iterations -#define AT91C_US_RSTNACK ((unsigned int) 0x1 << 14) // (USART) Reset Non Acknowledge -#define AT91C_US_RETTO ((unsigned int) 0x1 << 15) // (USART) Rearm Time-out -#define AT91C_US_DTREN ((unsigned int) 0x1 << 16) // (USART) Data Terminal ready Enable -#define AT91C_US_DTRDIS ((unsigned int) 0x1 << 17) // (USART) Data Terminal ready Disable -#define AT91C_US_RTSEN ((unsigned int) 0x1 << 18) // (USART) Request to Send enable -#define AT91C_US_RTSDIS ((unsigned int) 0x1 << 19) // (USART) Request to Send Disable -// -------- US_MR : (USART Offset: 0x4) Debug Unit Mode Register -------- -#define AT91C_US_USMODE ((unsigned int) 0xF << 0) // (USART) Usart mode -#define AT91C_US_USMODE_NORMAL ((unsigned int) 0x0) // (USART) Normal -#define AT91C_US_USMODE_RS485 ((unsigned int) 0x1) // (USART) RS485 -#define AT91C_US_USMODE_HWHSH ((unsigned int) 0x2) // (USART) Hardware Handshaking -#define AT91C_US_USMODE_MODEM ((unsigned int) 0x3) // (USART) Modem -#define AT91C_US_USMODE_ISO7816_0 ((unsigned int) 0x4) // (USART) ISO7816 protocol: T = 0 -#define AT91C_US_USMODE_ISO7816_1 ((unsigned int) 0x6) // (USART) ISO7816 protocol: T = 1 -#define AT91C_US_USMODE_IRDA ((unsigned int) 0x8) // (USART) IrDA -#define AT91C_US_USMODE_SWHSH ((unsigned int) 0xC) // (USART) Software Handshaking -#define AT91C_US_CLKS ((unsigned int) 0x3 << 4) // (USART) Clock Selection (Baud Rate generator Input Clock -#define AT91C_US_CLKS_CLOCK ((unsigned int) 0x0 << 4) // (USART) Clock -#define AT91C_US_CLKS_FDIV1 ((unsigned int) 0x1 << 4) // (USART) fdiv1 -#define AT91C_US_CLKS_SLOW ((unsigned int) 0x2 << 4) // (USART) slow_clock (ARM) -#define AT91C_US_CLKS_EXT ((unsigned int) 0x3 << 4) // (USART) External (SCK) -#define AT91C_US_CHRL ((unsigned int) 0x3 << 6) // (USART) Clock Selection (Baud Rate generator Input Clock -#define AT91C_US_CHRL_5_BITS ((unsigned int) 0x0 << 6) // (USART) Character Length: 5 bits -#define AT91C_US_CHRL_6_BITS ((unsigned int) 0x1 << 6) // (USART) Character Length: 6 bits -#define AT91C_US_CHRL_7_BITS ((unsigned int) 0x2 << 6) // (USART) Character Length: 7 bits -#define AT91C_US_CHRL_8_BITS ((unsigned int) 0x3 << 6) // (USART) Character Length: 8 bits -#define AT91C_US_SYNC ((unsigned int) 0x1 << 8) // (USART) Synchronous Mode Select -#define AT91C_US_NBSTOP ((unsigned int) 0x3 << 12) // (USART) Number of Stop bits -#define AT91C_US_NBSTOP_1_BIT ((unsigned int) 0x0 << 12) // (USART) 1 stop bit -#define AT91C_US_NBSTOP_15_BIT ((unsigned int) 0x1 << 12) // (USART) Asynchronous (SYNC=0) 2 stop bits Synchronous (SYNC=1) 2 stop bits -#define AT91C_US_NBSTOP_2_BIT ((unsigned int) 0x2 << 12) // (USART) 2 stop bits -#define AT91C_US_MSBF ((unsigned int) 0x1 << 16) // (USART) Bit Order -#define AT91C_US_MODE9 ((unsigned int) 0x1 << 17) // (USART) 9-bit Character length -#define AT91C_US_CKLO ((unsigned int) 0x1 << 18) // (USART) Clock Output Select -#define AT91C_US_OVER ((unsigned int) 0x1 << 19) // (USART) Over Sampling Mode -#define AT91C_US_INACK ((unsigned int) 0x1 << 20) // (USART) Inhibit Non Acknowledge -#define AT91C_US_DSNACK ((unsigned int) 0x1 << 21) // (USART) Disable Successive NACK -#define AT91C_US_MAX_ITER ((unsigned int) 0x1 << 24) // (USART) Number of Repetitions -#define AT91C_US_FILTER ((unsigned int) 0x1 << 28) // (USART) Receive Line Filter -// -------- US_IER : (USART Offset: 0x8) Debug Unit Interrupt Enable Register -------- -#define AT91C_US_RXBRK ((unsigned int) 0x1 << 2) // (USART) Break Received/End of Break -#define AT91C_US_TIMEOUT ((unsigned int) 0x1 << 8) // (USART) Receiver Time-out -#define AT91C_US_ITERATION ((unsigned int) 0x1 << 10) // (USART) Max number of Repetitions Reached -#define AT91C_US_NACK ((unsigned int) 0x1 << 13) // (USART) Non Acknowledge -#define AT91C_US_RIIC ((unsigned int) 0x1 << 16) // (USART) Ring INdicator Input Change Flag -#define AT91C_US_DSRIC ((unsigned int) 0x1 << 17) // (USART) Data Set Ready Input Change Flag -#define AT91C_US_DCDIC ((unsigned int) 0x1 << 18) // (USART) Data Carrier Flag -#define AT91C_US_CTSIC ((unsigned int) 0x1 << 19) // (USART) Clear To Send Input Change Flag -// -------- US_IDR : (USART Offset: 0xc) Debug Unit Interrupt Disable Register -------- -// -------- US_IMR : (USART Offset: 0x10) Debug Unit Interrupt Mask Register -------- -// -------- US_CSR : (USART Offset: 0x14) Debug Unit Channel Status Register -------- -#define AT91C_US_RI ((unsigned int) 0x1 << 20) // (USART) Image of RI Input -#define AT91C_US_DSR ((unsigned int) 0x1 << 21) // (USART) Image of DSR Input -#define AT91C_US_DCD ((unsigned int) 0x1 << 22) // (USART) Image of DCD Input -#define AT91C_US_CTS ((unsigned int) 0x1 << 23) // (USART) Image of CTS Input +/* -------- US_CR : (USART Offset: 0x0) Debug Unit Control Register -------- */ +#define AT91C_US_RSTSTA ( ( unsigned int ) 0x1 << 8 ) /* (USART) Reset Status Bits */ +#define AT91C_US_STTBRK ( ( unsigned int ) 0x1 << 9 ) /* (USART) Start Break */ +#define AT91C_US_STPBRK ( ( unsigned int ) 0x1 << 10 ) /* (USART) Stop Break */ +#define AT91C_US_STTTO ( ( unsigned int ) 0x1 << 11 ) /* (USART) Start Time-out */ +#define AT91C_US_SENDA ( ( unsigned int ) 0x1 << 12 ) /* (USART) Send Address */ +#define AT91C_US_RSTIT ( ( unsigned int ) 0x1 << 13 ) /* (USART) Reset Iterations */ +#define AT91C_US_RSTNACK ( ( unsigned int ) 0x1 << 14 ) /* (USART) Reset Non Acknowledge */ +#define AT91C_US_RETTO ( ( unsigned int ) 0x1 << 15 ) /* (USART) Rearm Time-out */ +#define AT91C_US_DTREN ( ( unsigned int ) 0x1 << 16 ) /* (USART) Data Terminal ready Enable */ +#define AT91C_US_DTRDIS ( ( unsigned int ) 0x1 << 17 ) /* (USART) Data Terminal ready Disable */ +#define AT91C_US_RTSEN ( ( unsigned int ) 0x1 << 18 ) /* (USART) Request to Send enable */ +#define AT91C_US_RTSDIS ( ( unsigned int ) 0x1 << 19 ) /* (USART) Request to Send Disable */ +/* -------- US_MR : (USART Offset: 0x4) Debug Unit Mode Register -------- */ +#define AT91C_US_USMODE ( ( unsigned int ) 0xF << 0 ) /* (USART) Usart mode */ +#define AT91C_US_USMODE_NORMAL ( ( unsigned int ) 0x0 ) /* (USART) Normal */ +#define AT91C_US_USMODE_RS485 ( ( unsigned int ) 0x1 ) /* (USART) RS485 */ +#define AT91C_US_USMODE_HWHSH ( ( unsigned int ) 0x2 ) /* (USART) Hardware Handshaking */ +#define AT91C_US_USMODE_MODEM ( ( unsigned int ) 0x3 ) /* (USART) Modem */ +#define AT91C_US_USMODE_ISO7816_0 ( ( unsigned int ) 0x4 ) /* (USART) ISO7816 protocol: T = 0 */ +#define AT91C_US_USMODE_ISO7816_1 ( ( unsigned int ) 0x6 ) /* (USART) ISO7816 protocol: T = 1 */ +#define AT91C_US_USMODE_IRDA ( ( unsigned int ) 0x8 ) /* (USART) IrDA */ +#define AT91C_US_USMODE_SWHSH ( ( unsigned int ) 0xC ) /* (USART) Software Handshaking */ +#define AT91C_US_CLKS ( ( unsigned int ) 0x3 << 4 ) /* (USART) Clock Selection (Baud Rate generator Input Clock */ +#define AT91C_US_CLKS_CLOCK ( ( unsigned int ) 0x0 << 4 ) /* (USART) Clock */ +#define AT91C_US_CLKS_FDIV1 ( ( unsigned int ) 0x1 << 4 ) /* (USART) fdiv1 */ +#define AT91C_US_CLKS_SLOW ( ( unsigned int ) 0x2 << 4 ) /* (USART) slow_clock (ARM) */ +#define AT91C_US_CLKS_EXT ( ( unsigned int ) 0x3 << 4 ) /* (USART) External (SCK) */ +#define AT91C_US_CHRL ( ( unsigned int ) 0x3 << 6 ) /* (USART) Clock Selection (Baud Rate generator Input Clock */ +#define AT91C_US_CHRL_5_BITS ( ( unsigned int ) 0x0 << 6 ) /* (USART) Character Length: 5 bits */ +#define AT91C_US_CHRL_6_BITS ( ( unsigned int ) 0x1 << 6 ) /* (USART) Character Length: 6 bits */ +#define AT91C_US_CHRL_7_BITS ( ( unsigned int ) 0x2 << 6 ) /* (USART) Character Length: 7 bits */ +#define AT91C_US_CHRL_8_BITS ( ( unsigned int ) 0x3 << 6 ) /* (USART) Character Length: 8 bits */ +#define AT91C_US_SYNC ( ( unsigned int ) 0x1 << 8 ) /* (USART) Synchronous Mode Select */ +#define AT91C_US_NBSTOP ( ( unsigned int ) 0x3 << 12 ) /* (USART) Number of Stop bits */ +#define AT91C_US_NBSTOP_1_BIT ( ( unsigned int ) 0x0 << 12 ) /* (USART) 1 stop bit */ +#define AT91C_US_NBSTOP_15_BIT ( ( unsigned int ) 0x1 << 12 ) /* (USART) Asynchronous (SYNC=0) 2 stop bits Synchronous (SYNC=1) 2 stop bits */ +#define AT91C_US_NBSTOP_2_BIT ( ( unsigned int ) 0x2 << 12 ) /* (USART) 2 stop bits */ +#define AT91C_US_MSBF ( ( unsigned int ) 0x1 << 16 ) /* (USART) Bit Order */ +#define AT91C_US_MODE9 ( ( unsigned int ) 0x1 << 17 ) /* (USART) 9-bit Character length */ +#define AT91C_US_CKLO ( ( unsigned int ) 0x1 << 18 ) /* (USART) Clock Output Select */ +#define AT91C_US_OVER ( ( unsigned int ) 0x1 << 19 ) /* (USART) Over Sampling Mode */ +#define AT91C_US_INACK ( ( unsigned int ) 0x1 << 20 ) /* (USART) Inhibit Non Acknowledge */ +#define AT91C_US_DSNACK ( ( unsigned int ) 0x1 << 21 ) /* (USART) Disable Successive NACK */ +#define AT91C_US_MAX_ITER ( ( unsigned int ) 0x1 << 24 ) /* (USART) Number of Repetitions */ +#define AT91C_US_FILTER ( ( unsigned int ) 0x1 << 28 ) /* (USART) Receive Line Filter */ +/* -------- US_IER : (USART Offset: 0x8) Debug Unit Interrupt Enable Register -------- */ +#define AT91C_US_RXBRK ( ( unsigned int ) 0x1 << 2 ) /* (USART) Break Received/End of Break */ +#define AT91C_US_TIMEOUT ( ( unsigned int ) 0x1 << 8 ) /* (USART) Receiver Time-out */ +#define AT91C_US_ITERATION ( ( unsigned int ) 0x1 << 10 ) /* (USART) Max number of Repetitions Reached */ +#define AT91C_US_NACK ( ( unsigned int ) 0x1 << 13 ) /* (USART) Non Acknowledge */ +#define AT91C_US_RIIC ( ( unsigned int ) 0x1 << 16 ) /* (USART) Ring INdicator Input Change Flag */ +#define AT91C_US_DSRIC ( ( unsigned int ) 0x1 << 17 ) /* (USART) Data Set Ready Input Change Flag */ +#define AT91C_US_DCDIC ( ( unsigned int ) 0x1 << 18 ) /* (USART) Data Carrier Flag */ +#define AT91C_US_CTSIC ( ( unsigned int ) 0x1 << 19 ) /* (USART) Clear To Send Input Change Flag */ +/* -------- US_IDR : (USART Offset: 0xc) Debug Unit Interrupt Disable Register -------- */ +/* -------- US_IMR : (USART Offset: 0x10) Debug Unit Interrupt Mask Register -------- */ +/* -------- US_CSR : (USART Offset: 0x14) Debug Unit Channel Status Register -------- */ +#define AT91C_US_RI ( ( unsigned int ) 0x1 << 20 ) /* (USART) Image of RI Input */ +#define AT91C_US_DSR ( ( unsigned int ) 0x1 << 21 ) /* (USART) Image of DSR Input */ +#define AT91C_US_DCD ( ( unsigned int ) 0x1 << 22 ) /* (USART) Image of DCD Input */ +#define AT91C_US_CTS ( ( unsigned int ) 0x1 << 23 ) /* (USART) Image of CTS Input */ -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Two-wire Interface -// ***************************************************************************** -typedef struct _AT91S_TWI { - AT91_REG TWI_CR; // Control Register - AT91_REG TWI_MMR; // Master Mode Register - AT91_REG TWI_SMR; // Slave Mode Register - AT91_REG TWI_IADR; // Internal Address Register - AT91_REG TWI_CWGR; // Clock Waveform Generator Register - AT91_REG Reserved0[3]; // - AT91_REG TWI_SR; // Status Register - AT91_REG TWI_IER; // Interrupt Enable Register - AT91_REG TWI_IDR; // Interrupt Disable Register - AT91_REG TWI_IMR; // Interrupt Mask Register - AT91_REG TWI_RHR; // Receive Holding Register - AT91_REG TWI_THR; // Transmit Holding Register -} AT91S_TWI, *AT91PS_TWI; +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR Two-wire Interface */ +/* ***************************************************************************** */ +typedef struct _AT91S_TWI +{ + AT91_REG TWI_CR; /* Control Register */ + AT91_REG TWI_MMR; /* Master Mode Register */ + AT91_REG TWI_SMR; /* Slave Mode Register */ + AT91_REG TWI_IADR; /* Internal Address Register */ + AT91_REG TWI_CWGR; /* Clock Waveform Generator Register */ + AT91_REG Reserved0[ 3 ]; /* */ + AT91_REG TWI_SR; /* Status Register */ + AT91_REG TWI_IER; /* Interrupt Enable Register */ + AT91_REG TWI_IDR; /* Interrupt Disable Register */ + AT91_REG TWI_IMR; /* Interrupt Mask Register */ + AT91_REG TWI_RHR; /* Receive Holding Register */ + AT91_REG TWI_THR; /* Transmit Holding Register */ +} AT91S_TWI, * AT91PS_TWI; -// -------- TWI_CR : (TWI Offset: 0x0) TWI Control Register -------- -#define AT91C_TWI_START ((unsigned int) 0x1 << 0) // (TWI) Send a START Condition -#define AT91C_TWI_STOP ((unsigned int) 0x1 << 1) // (TWI) Send a STOP Condition -#define AT91C_TWI_MSEN ((unsigned int) 0x1 << 2) // (TWI) TWI Master Transfer Enabled -#define AT91C_TWI_MSDIS ((unsigned int) 0x1 << 3) // (TWI) TWI Master Transfer Disabled -#define AT91C_TWI_SVEN ((unsigned int) 0x1 << 4) // (TWI) TWI Slave Transfer Enabled -#define AT91C_TWI_SVDIS ((unsigned int) 0x1 << 5) // (TWI) TWI Slave Transfer Disabled -#define AT91C_TWI_SWRST ((unsigned int) 0x1 << 7) // (TWI) Software Reset -// -------- TWI_MMR : (TWI Offset: 0x4) TWI Master Mode Register -------- -#define AT91C_TWI_IADRSZ ((unsigned int) 0x3 << 8) // (TWI) Internal Device Address Size -#define AT91C_TWI_IADRSZ_NO ((unsigned int) 0x0 << 8) // (TWI) No internal device address -#define AT91C_TWI_IADRSZ_1_BYTE ((unsigned int) 0x1 << 8) // (TWI) One-byte internal device address -#define AT91C_TWI_IADRSZ_2_BYTE ((unsigned int) 0x2 << 8) // (TWI) Two-byte internal device address -#define AT91C_TWI_IADRSZ_3_BYTE ((unsigned int) 0x3 << 8) // (TWI) Three-byte internal device address -#define AT91C_TWI_MREAD ((unsigned int) 0x1 << 12) // (TWI) Master Read Direction -#define AT91C_TWI_DADR ((unsigned int) 0x7F << 16) // (TWI) Device Address -// -------- TWI_SMR : (TWI Offset: 0x8) TWI Slave Mode Register -------- -#define AT91C_TWI_SADR ((unsigned int) 0x7F << 16) // (TWI) Slave Device Address -// -------- TWI_CWGR : (TWI Offset: 0x10) TWI Clock Waveform Generator Register -------- -#define AT91C_TWI_CLDIV ((unsigned int) 0xFF << 0) // (TWI) Clock Low Divider -#define AT91C_TWI_CHDIV ((unsigned int) 0xFF << 8) // (TWI) Clock High Divider -#define AT91C_TWI_CKDIV ((unsigned int) 0x7 << 16) // (TWI) Clock Divider -// -------- TWI_SR : (TWI Offset: 0x20) TWI Status Register -------- -#define AT91C_TWI_TXCOMP ((unsigned int) 0x1 << 0) // (TWI) Transmission Completed -#define AT91C_TWI_RXRDY ((unsigned int) 0x1 << 1) // (TWI) Receive holding register ReaDY -#define AT91C_TWI_TXRDY ((unsigned int) 0x1 << 2) // (TWI) Transmit holding register ReaDY -#define AT91C_TWI_SVREAD ((unsigned int) 0x1 << 3) // (TWI) Slave Read -#define AT91C_TWI_SVACC ((unsigned int) 0x1 << 4) // (TWI) Slave Access -#define AT91C_TWI_GCACC ((unsigned int) 0x1 << 5) // (TWI) General Call Access -#define AT91C_TWI_OVRE ((unsigned int) 0x1 << 6) // (TWI) Overrun Error -#define AT91C_TWI_UNRE ((unsigned int) 0x1 << 7) // (TWI) Underrun Error -#define AT91C_TWI_NACK ((unsigned int) 0x1 << 8) // (TWI) Not Acknowledged -#define AT91C_TWI_ARBLST ((unsigned int) 0x1 << 9) // (TWI) Arbitration Lost -// -------- TWI_IER : (TWI Offset: 0x24) TWI Interrupt Enable Register -------- -// -------- TWI_IDR : (TWI Offset: 0x28) TWI Interrupt Disable Register -------- -// -------- TWI_IMR : (TWI Offset: 0x2c) TWI Interrupt Mask Register -------- +/* -------- TWI_CR : (TWI Offset: 0x0) TWI Control Register -------- */ +#define AT91C_TWI_START ( ( unsigned int ) 0x1 << 0 ) /* (TWI) Send a START Condition */ +#define AT91C_TWI_STOP ( ( unsigned int ) 0x1 << 1 ) /* (TWI) Send a STOP Condition */ +#define AT91C_TWI_MSEN ( ( unsigned int ) 0x1 << 2 ) /* (TWI) TWI Master Transfer Enabled */ +#define AT91C_TWI_MSDIS ( ( unsigned int ) 0x1 << 3 ) /* (TWI) TWI Master Transfer Disabled */ +#define AT91C_TWI_SVEN ( ( unsigned int ) 0x1 << 4 ) /* (TWI) TWI Slave Transfer Enabled */ +#define AT91C_TWI_SVDIS ( ( unsigned int ) 0x1 << 5 ) /* (TWI) TWI Slave Transfer Disabled */ +#define AT91C_TWI_SWRST ( ( unsigned int ) 0x1 << 7 ) /* (TWI) Software Reset */ +/* -------- TWI_MMR : (TWI Offset: 0x4) TWI Master Mode Register -------- */ +#define AT91C_TWI_IADRSZ ( ( unsigned int ) 0x3 << 8 ) /* (TWI) Internal Device Address Size */ +#define AT91C_TWI_IADRSZ_NO ( ( unsigned int ) 0x0 << 8 ) /* (TWI) No internal device address */ +#define AT91C_TWI_IADRSZ_1_BYTE ( ( unsigned int ) 0x1 << 8 ) /* (TWI) One-byte internal device address */ +#define AT91C_TWI_IADRSZ_2_BYTE ( ( unsigned int ) 0x2 << 8 ) /* (TWI) Two-byte internal device address */ +#define AT91C_TWI_IADRSZ_3_BYTE ( ( unsigned int ) 0x3 << 8 ) /* (TWI) Three-byte internal device address */ +#define AT91C_TWI_MREAD ( ( unsigned int ) 0x1 << 12 ) /* (TWI) Master Read Direction */ +#define AT91C_TWI_DADR ( ( unsigned int ) 0x7F << 16 ) /* (TWI) Device Address */ +/* -------- TWI_SMR : (TWI Offset: 0x8) TWI Slave Mode Register -------- */ +#define AT91C_TWI_SADR ( ( unsigned int ) 0x7F << 16 ) /* (TWI) Slave Device Address */ +/* -------- TWI_CWGR : (TWI Offset: 0x10) TWI Clock Waveform Generator Register -------- */ +#define AT91C_TWI_CLDIV ( ( unsigned int ) 0xFF << 0 ) /* (TWI) Clock Low Divider */ +#define AT91C_TWI_CHDIV ( ( unsigned int ) 0xFF << 8 ) /* (TWI) Clock High Divider */ +#define AT91C_TWI_CKDIV ( ( unsigned int ) 0x7 << 16 ) /* (TWI) Clock Divider */ +/* -------- TWI_SR : (TWI Offset: 0x20) TWI Status Register -------- */ +#define AT91C_TWI_TXCOMP ( ( unsigned int ) 0x1 << 0 ) /* (TWI) Transmission Completed */ +#define AT91C_TWI_RXRDY ( ( unsigned int ) 0x1 << 1 ) /* (TWI) Receive holding register ReaDY */ +#define AT91C_TWI_TXRDY ( ( unsigned int ) 0x1 << 2 ) /* (TWI) Transmit holding register ReaDY */ +#define AT91C_TWI_SVREAD ( ( unsigned int ) 0x1 << 3 ) /* (TWI) Slave Read */ +#define AT91C_TWI_SVACC ( ( unsigned int ) 0x1 << 4 ) /* (TWI) Slave Access */ +#define AT91C_TWI_GCACC ( ( unsigned int ) 0x1 << 5 ) /* (TWI) General Call Access */ +#define AT91C_TWI_OVRE ( ( unsigned int ) 0x1 << 6 ) /* (TWI) Overrun Error */ +#define AT91C_TWI_UNRE ( ( unsigned int ) 0x1 << 7 ) /* (TWI) Underrun Error */ +#define AT91C_TWI_NACK ( ( unsigned int ) 0x1 << 8 ) /* (TWI) Not Acknowledged */ +#define AT91C_TWI_ARBLST ( ( unsigned int ) 0x1 << 9 ) /* (TWI) Arbitration Lost */ +/* -------- TWI_IER : (TWI Offset: 0x24) TWI Interrupt Enable Register -------- */ +/* -------- TWI_IDR : (TWI Offset: 0x28) TWI Interrupt Disable Register -------- */ +/* -------- TWI_IMR : (TWI Offset: 0x2c) TWI Interrupt Mask Register -------- */ -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Timer Counter Channel Interface -// ***************************************************************************** -typedef struct _AT91S_TC { - AT91_REG TC_CCR; // Channel Control Register - AT91_REG TC_CMR; // Channel Mode Register (Capture Mode / Waveform Mode) - AT91_REG Reserved0[2]; // - AT91_REG TC_CV; // Counter Value - AT91_REG TC_RA; // Register A - AT91_REG TC_RB; // Register B - AT91_REG TC_RC; // Register C - AT91_REG TC_SR; // Status Register - AT91_REG TC_IER; // Interrupt Enable Register - AT91_REG TC_IDR; // Interrupt Disable Register - AT91_REG TC_IMR; // Interrupt Mask Register -} AT91S_TC, *AT91PS_TC; +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR Timer Counter Channel Interface */ +/* ***************************************************************************** */ +typedef struct _AT91S_TC +{ + AT91_REG TC_CCR; /* Channel Control Register */ + AT91_REG TC_CMR; /* Channel Mode Register (Capture Mode / Waveform Mode) */ + AT91_REG Reserved0[ 2 ]; /* */ + AT91_REG TC_CV; /* Counter Value */ + AT91_REG TC_RA; /* Register A */ + AT91_REG TC_RB; /* Register B */ + AT91_REG TC_RC; /* Register C */ + AT91_REG TC_SR; /* Status Register */ + AT91_REG TC_IER; /* Interrupt Enable Register */ + AT91_REG TC_IDR; /* Interrupt Disable Register */ + AT91_REG TC_IMR; /* Interrupt Mask Register */ +} AT91S_TC, * AT91PS_TC; -// -------- TC_CCR : (TC Offset: 0x0) TC Channel Control Register -------- -#define AT91C_TC_CLKEN ((unsigned int) 0x1 << 0) // (TC) Counter Clock Enable Command -#define AT91C_TC_CLKDIS ((unsigned int) 0x1 << 1) // (TC) Counter Clock Disable Command -#define AT91C_TC_SWTRG ((unsigned int) 0x1 << 2) // (TC) Software Trigger Command -// -------- TC_CMR : (TC Offset: 0x4) TC Channel Mode Register: Capture Mode / Waveform Mode -------- -#define AT91C_TC_CLKS ((unsigned int) 0x7 << 0) // (TC) Clock Selection -#define AT91C_TC_CLKS_TIMER_DIV1_CLOCK ((unsigned int) 0x0) // (TC) Clock selected: TIMER_DIV1_CLOCK -#define AT91C_TC_CLKS_TIMER_DIV2_CLOCK ((unsigned int) 0x1) // (TC) Clock selected: TIMER_DIV2_CLOCK -#define AT91C_TC_CLKS_TIMER_DIV3_CLOCK ((unsigned int) 0x2) // (TC) Clock selected: TIMER_DIV3_CLOCK -#define AT91C_TC_CLKS_TIMER_DIV4_CLOCK ((unsigned int) 0x3) // (TC) Clock selected: TIMER_DIV4_CLOCK -#define AT91C_TC_CLKS_TIMER_DIV5_CLOCK ((unsigned int) 0x4) // (TC) Clock selected: TIMER_DIV5_CLOCK -#define AT91C_TC_CLKS_XC0 ((unsigned int) 0x5) // (TC) Clock selected: XC0 -#define AT91C_TC_CLKS_XC1 ((unsigned int) 0x6) // (TC) Clock selected: XC1 -#define AT91C_TC_CLKS_XC2 ((unsigned int) 0x7) // (TC) Clock selected: XC2 -#define AT91C_TC_CLKI ((unsigned int) 0x1 << 3) // (TC) Clock Invert -#define AT91C_TC_BURST ((unsigned int) 0x3 << 4) // (TC) Burst Signal Selection -#define AT91C_TC_BURST_NONE ((unsigned int) 0x0 << 4) // (TC) The clock is not gated by an external signal -#define AT91C_TC_BURST_XC0 ((unsigned int) 0x1 << 4) // (TC) XC0 is ANDed with the selected clock -#define AT91C_TC_BURST_XC1 ((unsigned int) 0x2 << 4) // (TC) XC1 is ANDed with the selected clock -#define AT91C_TC_BURST_XC2 ((unsigned int) 0x3 << 4) // (TC) XC2 is ANDed with the selected clock -#define AT91C_TC_CPCSTOP ((unsigned int) 0x1 << 6) // (TC) Counter Clock Stopped with RC Compare -#define AT91C_TC_LDBSTOP ((unsigned int) 0x1 << 6) // (TC) Counter Clock Stopped with RB Loading -#define AT91C_TC_LDBDIS ((unsigned int) 0x1 << 7) // (TC) Counter Clock Disabled with RB Loading -#define AT91C_TC_CPCDIS ((unsigned int) 0x1 << 7) // (TC) Counter Clock Disable with RC Compare -#define AT91C_TC_ETRGEDG ((unsigned int) 0x3 << 8) // (TC) External Trigger Edge Selection -#define AT91C_TC_ETRGEDG_NONE ((unsigned int) 0x0 << 8) // (TC) Edge: None -#define AT91C_TC_ETRGEDG_RISING ((unsigned int) 0x1 << 8) // (TC) Edge: rising edge -#define AT91C_TC_ETRGEDG_FALLING ((unsigned int) 0x2 << 8) // (TC) Edge: falling edge -#define AT91C_TC_ETRGEDG_BOTH ((unsigned int) 0x3 << 8) // (TC) Edge: each edge -#define AT91C_TC_EEVTEDG ((unsigned int) 0x3 << 8) // (TC) External Event Edge Selection -#define AT91C_TC_EEVTEDG_NONE ((unsigned int) 0x0 << 8) // (TC) Edge: None -#define AT91C_TC_EEVTEDG_RISING ((unsigned int) 0x1 << 8) // (TC) Edge: rising edge -#define AT91C_TC_EEVTEDG_FALLING ((unsigned int) 0x2 << 8) // (TC) Edge: falling edge -#define AT91C_TC_EEVTEDG_BOTH ((unsigned int) 0x3 << 8) // (TC) Edge: each edge -#define AT91C_TC_ABETRG ((unsigned int) 0x1 << 10) // (TC) TIOA or TIOB External Trigger Selection -#define AT91C_TC_EEVT ((unsigned int) 0x3 << 10) // (TC) External Event Selection -#define AT91C_TC_EEVT_NONE ((unsigned int) 0x0 << 10) // (TC) Signal selected as external event: TIOB TIOB direction: input -#define AT91C_TC_EEVT_RISING ((unsigned int) 0x1 << 10) // (TC) Signal selected as external event: XC0 TIOB direction: output -#define AT91C_TC_EEVT_FALLING ((unsigned int) 0x2 << 10) // (TC) Signal selected as external event: XC1 TIOB direction: output -#define AT91C_TC_EEVT_BOTH ((unsigned int) 0x3 << 10) // (TC) Signal selected as external event: XC2 TIOB direction: output -#define AT91C_TC_ENETRG ((unsigned int) 0x1 << 12) // (TC) External Event Trigger enable -#define AT91C_TC_WAVESEL ((unsigned int) 0x3 << 13) // (TC) Waveform Selection -#define AT91C_TC_WAVESEL_UP ((unsigned int) 0x0 << 13) // (TC) UP mode without atomatic trigger on RC Compare -#define AT91C_TC_WAVESEL_UPDOWN ((unsigned int) 0x1 << 13) // (TC) UPDOWN mode without automatic trigger on RC Compare -#define AT91C_TC_WAVESEL_UP_AUTO ((unsigned int) 0x2 << 13) // (TC) UP mode with automatic trigger on RC Compare -#define AT91C_TC_WAVESEL_UPDOWN_AUTO ((unsigned int) 0x3 << 13) // (TC) UPDOWN mode with automatic trigger on RC Compare -#define AT91C_TC_CPCTRG ((unsigned int) 0x1 << 14) // (TC) RC Compare Trigger Enable -#define AT91C_TC_WAVE ((unsigned int) 0x1 << 15) // (TC) -#define AT91C_TC_LDRA ((unsigned int) 0x3 << 16) // (TC) RA Loading Selection -#define AT91C_TC_LDRA_NONE ((unsigned int) 0x0 << 16) // (TC) Edge: None -#define AT91C_TC_LDRA_RISING ((unsigned int) 0x1 << 16) // (TC) Edge: rising edge of TIOA -#define AT91C_TC_LDRA_FALLING ((unsigned int) 0x2 << 16) // (TC) Edge: falling edge of TIOA -#define AT91C_TC_LDRA_BOTH ((unsigned int) 0x3 << 16) // (TC) Edge: each edge of TIOA -#define AT91C_TC_ACPA ((unsigned int) 0x3 << 16) // (TC) RA Compare Effect on TIOA -#define AT91C_TC_ACPA_NONE ((unsigned int) 0x0 << 16) // (TC) Effect: none -#define AT91C_TC_ACPA_SET ((unsigned int) 0x1 << 16) // (TC) Effect: set -#define AT91C_TC_ACPA_CLEAR ((unsigned int) 0x2 << 16) // (TC) Effect: clear -#define AT91C_TC_ACPA_TOGGLE ((unsigned int) 0x3 << 16) // (TC) Effect: toggle -#define AT91C_TC_LDRB ((unsigned int) 0x3 << 18) // (TC) RB Loading Selection -#define AT91C_TC_LDRB_NONE ((unsigned int) 0x0 << 18) // (TC) Edge: None -#define AT91C_TC_LDRB_RISING ((unsigned int) 0x1 << 18) // (TC) Edge: rising edge of TIOA -#define AT91C_TC_LDRB_FALLING ((unsigned int) 0x2 << 18) // (TC) Edge: falling edge of TIOA -#define AT91C_TC_LDRB_BOTH ((unsigned int) 0x3 << 18) // (TC) Edge: each edge of TIOA -#define AT91C_TC_ACPC ((unsigned int) 0x3 << 18) // (TC) RC Compare Effect on TIOA -#define AT91C_TC_ACPC_NONE ((unsigned int) 0x0 << 18) // (TC) Effect: none -#define AT91C_TC_ACPC_SET ((unsigned int) 0x1 << 18) // (TC) Effect: set -#define AT91C_TC_ACPC_CLEAR ((unsigned int) 0x2 << 18) // (TC) Effect: clear -#define AT91C_TC_ACPC_TOGGLE ((unsigned int) 0x3 << 18) // (TC) Effect: toggle -#define AT91C_TC_AEEVT ((unsigned int) 0x3 << 20) // (TC) External Event Effect on TIOA -#define AT91C_TC_AEEVT_NONE ((unsigned int) 0x0 << 20) // (TC) Effect: none -#define AT91C_TC_AEEVT_SET ((unsigned int) 0x1 << 20) // (TC) Effect: set -#define AT91C_TC_AEEVT_CLEAR ((unsigned int) 0x2 << 20) // (TC) Effect: clear -#define AT91C_TC_AEEVT_TOGGLE ((unsigned int) 0x3 << 20) // (TC) Effect: toggle -#define AT91C_TC_ASWTRG ((unsigned int) 0x3 << 22) // (TC) Software Trigger Effect on TIOA -#define AT91C_TC_ASWTRG_NONE ((unsigned int) 0x0 << 22) // (TC) Effect: none -#define AT91C_TC_ASWTRG_SET ((unsigned int) 0x1 << 22) // (TC) Effect: set -#define AT91C_TC_ASWTRG_CLEAR ((unsigned int) 0x2 << 22) // (TC) Effect: clear -#define AT91C_TC_ASWTRG_TOGGLE ((unsigned int) 0x3 << 22) // (TC) Effect: toggle -#define AT91C_TC_BCPB ((unsigned int) 0x3 << 24) // (TC) RB Compare Effect on TIOB -#define AT91C_TC_BCPB_NONE ((unsigned int) 0x0 << 24) // (TC) Effect: none -#define AT91C_TC_BCPB_SET ((unsigned int) 0x1 << 24) // (TC) Effect: set -#define AT91C_TC_BCPB_CLEAR ((unsigned int) 0x2 << 24) // (TC) Effect: clear -#define AT91C_TC_BCPB_TOGGLE ((unsigned int) 0x3 << 24) // (TC) Effect: toggle -#define AT91C_TC_BCPC ((unsigned int) 0x3 << 26) // (TC) RC Compare Effect on TIOB -#define AT91C_TC_BCPC_NONE ((unsigned int) 0x0 << 26) // (TC) Effect: none -#define AT91C_TC_BCPC_SET ((unsigned int) 0x1 << 26) // (TC) Effect: set -#define AT91C_TC_BCPC_CLEAR ((unsigned int) 0x2 << 26) // (TC) Effect: clear -#define AT91C_TC_BCPC_TOGGLE ((unsigned int) 0x3 << 26) // (TC) Effect: toggle -#define AT91C_TC_BEEVT ((unsigned int) 0x3 << 28) // (TC) External Event Effect on TIOB -#define AT91C_TC_BEEVT_NONE ((unsigned int) 0x0 << 28) // (TC) Effect: none -#define AT91C_TC_BEEVT_SET ((unsigned int) 0x1 << 28) // (TC) Effect: set -#define AT91C_TC_BEEVT_CLEAR ((unsigned int) 0x2 << 28) // (TC) Effect: clear -#define AT91C_TC_BEEVT_TOGGLE ((unsigned int) 0x3 << 28) // (TC) Effect: toggle -#define AT91C_TC_BSWTRG ((unsigned int) 0x3 << 30) // (TC) Software Trigger Effect on TIOB -#define AT91C_TC_BSWTRG_NONE ((unsigned int) 0x0 << 30) // (TC) Effect: none -#define AT91C_TC_BSWTRG_SET ((unsigned int) 0x1 << 30) // (TC) Effect: set -#define AT91C_TC_BSWTRG_CLEAR ((unsigned int) 0x2 << 30) // (TC) Effect: clear -#define AT91C_TC_BSWTRG_TOGGLE ((unsigned int) 0x3 << 30) // (TC) Effect: toggle -// -------- TC_SR : (TC Offset: 0x20) TC Channel Status Register -------- -#define AT91C_TC_COVFS ((unsigned int) 0x1 << 0) // (TC) Counter Overflow -#define AT91C_TC_LOVRS ((unsigned int) 0x1 << 1) // (TC) Load Overrun -#define AT91C_TC_CPAS ((unsigned int) 0x1 << 2) // (TC) RA Compare -#define AT91C_TC_CPBS ((unsigned int) 0x1 << 3) // (TC) RB Compare -#define AT91C_TC_CPCS ((unsigned int) 0x1 << 4) // (TC) RC Compare -#define AT91C_TC_LDRAS ((unsigned int) 0x1 << 5) // (TC) RA Loading -#define AT91C_TC_LDRBS ((unsigned int) 0x1 << 6) // (TC) RB Loading -#define AT91C_TC_ETRCS ((unsigned int) 0x1 << 7) // (TC) External Trigger -#define AT91C_TC_ETRGS ((unsigned int) 0x1 << 16) // (TC) Clock Enabling -#define AT91C_TC_MTIOA ((unsigned int) 0x1 << 17) // (TC) TIOA Mirror -#define AT91C_TC_MTIOB ((unsigned int) 0x1 << 18) // (TC) TIOA Mirror -// -------- TC_IER : (TC Offset: 0x24) TC Channel Interrupt Enable Register -------- -// -------- TC_IDR : (TC Offset: 0x28) TC Channel Interrupt Disable Register -------- -// -------- TC_IMR : (TC Offset: 0x2c) TC Channel Interrupt Mask Register -------- +/* -------- TC_CCR : (TC Offset: 0x0) TC Channel Control Register -------- */ +#define AT91C_TC_CLKEN ( ( unsigned int ) 0x1 << 0 ) /* (TC) Counter Clock Enable Command */ +#define AT91C_TC_CLKDIS ( ( unsigned int ) 0x1 << 1 ) /* (TC) Counter Clock Disable Command */ +#define AT91C_TC_SWTRG ( ( unsigned int ) 0x1 << 2 ) /* (TC) Software Trigger Command */ +/* -------- TC_CMR : (TC Offset: 0x4) TC Channel Mode Register: Capture Mode / Waveform Mode -------- */ +#define AT91C_TC_CLKS ( ( unsigned int ) 0x7 << 0 ) /* (TC) Clock Selection */ +#define AT91C_TC_CLKS_TIMER_DIV1_CLOCK ( ( unsigned int ) 0x0 ) /* (TC) Clock selected: TIMER_DIV1_CLOCK */ +#define AT91C_TC_CLKS_TIMER_DIV2_CLOCK ( ( unsigned int ) 0x1 ) /* (TC) Clock selected: TIMER_DIV2_CLOCK */ +#define AT91C_TC_CLKS_TIMER_DIV3_CLOCK ( ( unsigned int ) 0x2 ) /* (TC) Clock selected: TIMER_DIV3_CLOCK */ +#define AT91C_TC_CLKS_TIMER_DIV4_CLOCK ( ( unsigned int ) 0x3 ) /* (TC) Clock selected: TIMER_DIV4_CLOCK */ +#define AT91C_TC_CLKS_TIMER_DIV5_CLOCK ( ( unsigned int ) 0x4 ) /* (TC) Clock selected: TIMER_DIV5_CLOCK */ +#define AT91C_TC_CLKS_XC0 ( ( unsigned int ) 0x5 ) /* (TC) Clock selected: XC0 */ +#define AT91C_TC_CLKS_XC1 ( ( unsigned int ) 0x6 ) /* (TC) Clock selected: XC1 */ +#define AT91C_TC_CLKS_XC2 ( ( unsigned int ) 0x7 ) /* (TC) Clock selected: XC2 */ +#define AT91C_TC_CLKI ( ( unsigned int ) 0x1 << 3 ) /* (TC) Clock Invert */ +#define AT91C_TC_BURST ( ( unsigned int ) 0x3 << 4 ) /* (TC) Burst Signal Selection */ +#define AT91C_TC_BURST_NONE ( ( unsigned int ) 0x0 << 4 ) /* (TC) The clock is not gated by an external signal */ +#define AT91C_TC_BURST_XC0 ( ( unsigned int ) 0x1 << 4 ) /* (TC) XC0 is ANDed with the selected clock */ +#define AT91C_TC_BURST_XC1 ( ( unsigned int ) 0x2 << 4 ) /* (TC) XC1 is ANDed with the selected clock */ +#define AT91C_TC_BURST_XC2 ( ( unsigned int ) 0x3 << 4 ) /* (TC) XC2 is ANDed with the selected clock */ +#define AT91C_TC_CPCSTOP ( ( unsigned int ) 0x1 << 6 ) /* (TC) Counter Clock Stopped with RC Compare */ +#define AT91C_TC_LDBSTOP ( ( unsigned int ) 0x1 << 6 ) /* (TC) Counter Clock Stopped with RB Loading */ +#define AT91C_TC_LDBDIS ( ( unsigned int ) 0x1 << 7 ) /* (TC) Counter Clock Disabled with RB Loading */ +#define AT91C_TC_CPCDIS ( ( unsigned int ) 0x1 << 7 ) /* (TC) Counter Clock Disable with RC Compare */ +#define AT91C_TC_ETRGEDG ( ( unsigned int ) 0x3 << 8 ) /* (TC) External Trigger Edge Selection */ +#define AT91C_TC_ETRGEDG_NONE ( ( unsigned int ) 0x0 << 8 ) /* (TC) Edge: None */ +#define AT91C_TC_ETRGEDG_RISING ( ( unsigned int ) 0x1 << 8 ) /* (TC) Edge: rising edge */ +#define AT91C_TC_ETRGEDG_FALLING ( ( unsigned int ) 0x2 << 8 ) /* (TC) Edge: falling edge */ +#define AT91C_TC_ETRGEDG_BOTH ( ( unsigned int ) 0x3 << 8 ) /* (TC) Edge: each edge */ +#define AT91C_TC_EEVTEDG ( ( unsigned int ) 0x3 << 8 ) /* (TC) External Event Edge Selection */ +#define AT91C_TC_EEVTEDG_NONE ( ( unsigned int ) 0x0 << 8 ) /* (TC) Edge: None */ +#define AT91C_TC_EEVTEDG_RISING ( ( unsigned int ) 0x1 << 8 ) /* (TC) Edge: rising edge */ +#define AT91C_TC_EEVTEDG_FALLING ( ( unsigned int ) 0x2 << 8 ) /* (TC) Edge: falling edge */ +#define AT91C_TC_EEVTEDG_BOTH ( ( unsigned int ) 0x3 << 8 ) /* (TC) Edge: each edge */ +#define AT91C_TC_ABETRG ( ( unsigned int ) 0x1 << 10 ) /* (TC) TIOA or TIOB External Trigger Selection */ +#define AT91C_TC_EEVT ( ( unsigned int ) 0x3 << 10 ) /* (TC) External Event Selection */ +#define AT91C_TC_EEVT_NONE ( ( unsigned int ) 0x0 << 10 ) /* (TC) Signal selected as external event: TIOB TIOB direction: input */ +#define AT91C_TC_EEVT_RISING ( ( unsigned int ) 0x1 << 10 ) /* (TC) Signal selected as external event: XC0 TIOB direction: output */ +#define AT91C_TC_EEVT_FALLING ( ( unsigned int ) 0x2 << 10 ) /* (TC) Signal selected as external event: XC1 TIOB direction: output */ +#define AT91C_TC_EEVT_BOTH ( ( unsigned int ) 0x3 << 10 ) /* (TC) Signal selected as external event: XC2 TIOB direction: output */ +#define AT91C_TC_ENETRG ( ( unsigned int ) 0x1 << 12 ) /* (TC) External Event Trigger enable */ +#define AT91C_TC_WAVESEL ( ( unsigned int ) 0x3 << 13 ) /* (TC) Waveform Selection */ +#define AT91C_TC_WAVESEL_UP ( ( unsigned int ) 0x0 << 13 ) /* (TC) UP mode without atomatic trigger on RC Compare */ +#define AT91C_TC_WAVESEL_UPDOWN ( ( unsigned int ) 0x1 << 13 ) /* (TC) UPDOWN mode without automatic trigger on RC Compare */ +#define AT91C_TC_WAVESEL_UP_AUTO ( ( unsigned int ) 0x2 << 13 ) /* (TC) UP mode with automatic trigger on RC Compare */ +#define AT91C_TC_WAVESEL_UPDOWN_AUTO ( ( unsigned int ) 0x3 << 13 ) /* (TC) UPDOWN mode with automatic trigger on RC Compare */ +#define AT91C_TC_CPCTRG ( ( unsigned int ) 0x1 << 14 ) /* (TC) RC Compare Trigger Enable */ +#define AT91C_TC_WAVE ( ( unsigned int ) 0x1 << 15 ) /* (TC) */ +#define AT91C_TC_LDRA ( ( unsigned int ) 0x3 << 16 ) /* (TC) RA Loading Selection */ +#define AT91C_TC_LDRA_NONE ( ( unsigned int ) 0x0 << 16 ) /* (TC) Edge: None */ +#define AT91C_TC_LDRA_RISING ( ( unsigned int ) 0x1 << 16 ) /* (TC) Edge: rising edge of TIOA */ +#define AT91C_TC_LDRA_FALLING ( ( unsigned int ) 0x2 << 16 ) /* (TC) Edge: falling edge of TIOA */ +#define AT91C_TC_LDRA_BOTH ( ( unsigned int ) 0x3 << 16 ) /* (TC) Edge: each edge of TIOA */ +#define AT91C_TC_ACPA ( ( unsigned int ) 0x3 << 16 ) /* (TC) RA Compare Effect on TIOA */ +#define AT91C_TC_ACPA_NONE ( ( unsigned int ) 0x0 << 16 ) /* (TC) Effect: none */ +#define AT91C_TC_ACPA_SET ( ( unsigned int ) 0x1 << 16 ) /* (TC) Effect: set */ +#define AT91C_TC_ACPA_CLEAR ( ( unsigned int ) 0x2 << 16 ) /* (TC) Effect: clear */ +#define AT91C_TC_ACPA_TOGGLE ( ( unsigned int ) 0x3 << 16 ) /* (TC) Effect: toggle */ +#define AT91C_TC_LDRB ( ( unsigned int ) 0x3 << 18 ) /* (TC) RB Loading Selection */ +#define AT91C_TC_LDRB_NONE ( ( unsigned int ) 0x0 << 18 ) /* (TC) Edge: None */ +#define AT91C_TC_LDRB_RISING ( ( unsigned int ) 0x1 << 18 ) /* (TC) Edge: rising edge of TIOA */ +#define AT91C_TC_LDRB_FALLING ( ( unsigned int ) 0x2 << 18 ) /* (TC) Edge: falling edge of TIOA */ +#define AT91C_TC_LDRB_BOTH ( ( unsigned int ) 0x3 << 18 ) /* (TC) Edge: each edge of TIOA */ +#define AT91C_TC_ACPC ( ( unsigned int ) 0x3 << 18 ) /* (TC) RC Compare Effect on TIOA */ +#define AT91C_TC_ACPC_NONE ( ( unsigned int ) 0x0 << 18 ) /* (TC) Effect: none */ +#define AT91C_TC_ACPC_SET ( ( unsigned int ) 0x1 << 18 ) /* (TC) Effect: set */ +#define AT91C_TC_ACPC_CLEAR ( ( unsigned int ) 0x2 << 18 ) /* (TC) Effect: clear */ +#define AT91C_TC_ACPC_TOGGLE ( ( unsigned int ) 0x3 << 18 ) /* (TC) Effect: toggle */ +#define AT91C_TC_AEEVT ( ( unsigned int ) 0x3 << 20 ) /* (TC) External Event Effect on TIOA */ +#define AT91C_TC_AEEVT_NONE ( ( unsigned int ) 0x0 << 20 ) /* (TC) Effect: none */ +#define AT91C_TC_AEEVT_SET ( ( unsigned int ) 0x1 << 20 ) /* (TC) Effect: set */ +#define AT91C_TC_AEEVT_CLEAR ( ( unsigned int ) 0x2 << 20 ) /* (TC) Effect: clear */ +#define AT91C_TC_AEEVT_TOGGLE ( ( unsigned int ) 0x3 << 20 ) /* (TC) Effect: toggle */ +#define AT91C_TC_ASWTRG ( ( unsigned int ) 0x3 << 22 ) /* (TC) Software Trigger Effect on TIOA */ +#define AT91C_TC_ASWTRG_NONE ( ( unsigned int ) 0x0 << 22 ) /* (TC) Effect: none */ +#define AT91C_TC_ASWTRG_SET ( ( unsigned int ) 0x1 << 22 ) /* (TC) Effect: set */ +#define AT91C_TC_ASWTRG_CLEAR ( ( unsigned int ) 0x2 << 22 ) /* (TC) Effect: clear */ +#define AT91C_TC_ASWTRG_TOGGLE ( ( unsigned int ) 0x3 << 22 ) /* (TC) Effect: toggle */ +#define AT91C_TC_BCPB ( ( unsigned int ) 0x3 << 24 ) /* (TC) RB Compare Effect on TIOB */ +#define AT91C_TC_BCPB_NONE ( ( unsigned int ) 0x0 << 24 ) /* (TC) Effect: none */ +#define AT91C_TC_BCPB_SET ( ( unsigned int ) 0x1 << 24 ) /* (TC) Effect: set */ +#define AT91C_TC_BCPB_CLEAR ( ( unsigned int ) 0x2 << 24 ) /* (TC) Effect: clear */ +#define AT91C_TC_BCPB_TOGGLE ( ( unsigned int ) 0x3 << 24 ) /* (TC) Effect: toggle */ +#define AT91C_TC_BCPC ( ( unsigned int ) 0x3 << 26 ) /* (TC) RC Compare Effect on TIOB */ +#define AT91C_TC_BCPC_NONE ( ( unsigned int ) 0x0 << 26 ) /* (TC) Effect: none */ +#define AT91C_TC_BCPC_SET ( ( unsigned int ) 0x1 << 26 ) /* (TC) Effect: set */ +#define AT91C_TC_BCPC_CLEAR ( ( unsigned int ) 0x2 << 26 ) /* (TC) Effect: clear */ +#define AT91C_TC_BCPC_TOGGLE ( ( unsigned int ) 0x3 << 26 ) /* (TC) Effect: toggle */ +#define AT91C_TC_BEEVT ( ( unsigned int ) 0x3 << 28 ) /* (TC) External Event Effect on TIOB */ +#define AT91C_TC_BEEVT_NONE ( ( unsigned int ) 0x0 << 28 ) /* (TC) Effect: none */ +#define AT91C_TC_BEEVT_SET ( ( unsigned int ) 0x1 << 28 ) /* (TC) Effect: set */ +#define AT91C_TC_BEEVT_CLEAR ( ( unsigned int ) 0x2 << 28 ) /* (TC) Effect: clear */ +#define AT91C_TC_BEEVT_TOGGLE ( ( unsigned int ) 0x3 << 28 ) /* (TC) Effect: toggle */ +#define AT91C_TC_BSWTRG ( ( unsigned int ) 0x3 << 30 ) /* (TC) Software Trigger Effect on TIOB */ +#define AT91C_TC_BSWTRG_NONE ( ( unsigned int ) 0x0 << 30 ) /* (TC) Effect: none */ +#define AT91C_TC_BSWTRG_SET ( ( unsigned int ) 0x1 << 30 ) /* (TC) Effect: set */ +#define AT91C_TC_BSWTRG_CLEAR ( ( unsigned int ) 0x2 << 30 ) /* (TC) Effect: clear */ +#define AT91C_TC_BSWTRG_TOGGLE ( ( unsigned int ) 0x3 << 30 ) /* (TC) Effect: toggle */ +/* -------- TC_SR : (TC Offset: 0x20) TC Channel Status Register -------- */ +#define AT91C_TC_COVFS ( ( unsigned int ) 0x1 << 0 ) /* (TC) Counter Overflow */ +#define AT91C_TC_LOVRS ( ( unsigned int ) 0x1 << 1 ) /* (TC) Load Overrun */ +#define AT91C_TC_CPAS ( ( unsigned int ) 0x1 << 2 ) /* (TC) RA Compare */ +#define AT91C_TC_CPBS ( ( unsigned int ) 0x1 << 3 ) /* (TC) RB Compare */ +#define AT91C_TC_CPCS ( ( unsigned int ) 0x1 << 4 ) /* (TC) RC Compare */ +#define AT91C_TC_LDRAS ( ( unsigned int ) 0x1 << 5 ) /* (TC) RA Loading */ +#define AT91C_TC_LDRBS ( ( unsigned int ) 0x1 << 6 ) /* (TC) RB Loading */ +#define AT91C_TC_ETRCS ( ( unsigned int ) 0x1 << 7 ) /* (TC) External Trigger */ +#define AT91C_TC_ETRGS ( ( unsigned int ) 0x1 << 16 ) /* (TC) Clock Enabling */ +#define AT91C_TC_MTIOA ( ( unsigned int ) 0x1 << 17 ) /* (TC) TIOA Mirror */ +#define AT91C_TC_MTIOB ( ( unsigned int ) 0x1 << 18 ) /* (TC) TIOA Mirror */ +/* -------- TC_IER : (TC Offset: 0x24) TC Channel Interrupt Enable Register -------- */ +/* -------- TC_IDR : (TC Offset: 0x28) TC Channel Interrupt Disable Register -------- */ +/* -------- TC_IMR : (TC Offset: 0x2c) TC Channel Interrupt Mask Register -------- */ -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Timer Counter Interface -// ***************************************************************************** -typedef struct _AT91S_TCB { - AT91S_TC TCB_TC0; // TC Channel 0 - AT91_REG Reserved0[4]; // - AT91S_TC TCB_TC1; // TC Channel 1 - AT91_REG Reserved1[4]; // - AT91S_TC TCB_TC2; // TC Channel 2 - AT91_REG Reserved2[4]; // - AT91_REG TCB_BCR; // TC Block Control Register - AT91_REG TCB_BMR; // TC Block Mode Register -} AT91S_TCB, *AT91PS_TCB; +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR Timer Counter Interface */ +/* ***************************************************************************** */ +typedef struct _AT91S_TCB +{ + AT91S_TC TCB_TC0; /* TC Channel 0 */ + AT91_REG Reserved0[ 4 ]; /* */ + AT91S_TC TCB_TC1; /* TC Channel 1 */ + AT91_REG Reserved1[ 4 ]; /* */ + AT91S_TC TCB_TC2; /* TC Channel 2 */ + AT91_REG Reserved2[ 4 ]; /* */ + AT91_REG TCB_BCR; /* TC Block Control Register */ + AT91_REG TCB_BMR; /* TC Block Mode Register */ +} AT91S_TCB, * AT91PS_TCB; -// -------- TCB_BCR : (TCB Offset: 0xc0) TC Block Control Register -------- -#define AT91C_TCB_SYNC ((unsigned int) 0x1 << 0) // (TCB) Synchro Command -// -------- TCB_BMR : (TCB Offset: 0xc4) TC Block Mode Register -------- -#define AT91C_TCB_TC0XC0S ((unsigned int) 0x1 << 0) // (TCB) External Clock Signal 0 Selection -#define AT91C_TCB_TC0XC0S_TCLK0 ((unsigned int) 0x0) // (TCB) TCLK0 connected to XC0 -#define AT91C_TCB_TC0XC0S_NONE ((unsigned int) 0x1) // (TCB) None signal connected to XC0 -#define AT91C_TCB_TC0XC0S_TIOA1 ((unsigned int) 0x2) // (TCB) TIOA1 connected to XC0 -#define AT91C_TCB_TC0XC0S_TIOA2 ((unsigned int) 0x3) // (TCB) TIOA2 connected to XC0 -#define AT91C_TCB_TC1XC1S ((unsigned int) 0x1 << 2) // (TCB) External Clock Signal 1 Selection -#define AT91C_TCB_TC1XC1S_TCLK1 ((unsigned int) 0x0 << 2) // (TCB) TCLK1 connected to XC1 -#define AT91C_TCB_TC1XC1S_NONE ((unsigned int) 0x1 << 2) // (TCB) None signal connected to XC1 -#define AT91C_TCB_TC1XC1S_TIOA0 ((unsigned int) 0x2 << 2) // (TCB) TIOA0 connected to XC1 -#define AT91C_TCB_TC1XC1S_TIOA2 ((unsigned int) 0x3 << 2) // (TCB) TIOA2 connected to XC1 -#define AT91C_TCB_TC2XC2S ((unsigned int) 0x1 << 4) // (TCB) External Clock Signal 2 Selection -#define AT91C_TCB_TC2XC2S_TCLK2 ((unsigned int) 0x0 << 4) // (TCB) TCLK2 connected to XC2 -#define AT91C_TCB_TC2XC2S_NONE ((unsigned int) 0x1 << 4) // (TCB) None signal connected to XC2 -#define AT91C_TCB_TC2XC2S_TIOA0 ((unsigned int) 0x2 << 4) // (TCB) TIOA0 connected to XC2 -#define AT91C_TCB_TC2XC2S_TIOA2 ((unsigned int) 0x3 << 4) // (TCB) TIOA2 connected to XC2 +/* -------- TCB_BCR : (TCB Offset: 0xc0) TC Block Control Register -------- */ +#define AT91C_TCB_SYNC ( ( unsigned int ) 0x1 << 0 ) /* (TCB) Synchro Command */ +/* -------- TCB_BMR : (TCB Offset: 0xc4) TC Block Mode Register -------- */ +#define AT91C_TCB_TC0XC0S ( ( unsigned int ) 0x1 << 0 ) /* (TCB) External Clock Signal 0 Selection */ +#define AT91C_TCB_TC0XC0S_TCLK0 ( ( unsigned int ) 0x0 ) /* (TCB) TCLK0 connected to XC0 */ +#define AT91C_TCB_TC0XC0S_NONE ( ( unsigned int ) 0x1 ) /* (TCB) None signal connected to XC0 */ +#define AT91C_TCB_TC0XC0S_TIOA1 ( ( unsigned int ) 0x2 ) /* (TCB) TIOA1 connected to XC0 */ +#define AT91C_TCB_TC0XC0S_TIOA2 ( ( unsigned int ) 0x3 ) /* (TCB) TIOA2 connected to XC0 */ +#define AT91C_TCB_TC1XC1S ( ( unsigned int ) 0x1 << 2 ) /* (TCB) External Clock Signal 1 Selection */ +#define AT91C_TCB_TC1XC1S_TCLK1 ( ( unsigned int ) 0x0 << 2 ) /* (TCB) TCLK1 connected to XC1 */ +#define AT91C_TCB_TC1XC1S_NONE ( ( unsigned int ) 0x1 << 2 ) /* (TCB) None signal connected to XC1 */ +#define AT91C_TCB_TC1XC1S_TIOA0 ( ( unsigned int ) 0x2 << 2 ) /* (TCB) TIOA0 connected to XC1 */ +#define AT91C_TCB_TC1XC1S_TIOA2 ( ( unsigned int ) 0x3 << 2 ) /* (TCB) TIOA2 connected to XC1 */ +#define AT91C_TCB_TC2XC2S ( ( unsigned int ) 0x1 << 4 ) /* (TCB) External Clock Signal 2 Selection */ +#define AT91C_TCB_TC2XC2S_TCLK2 ( ( unsigned int ) 0x0 << 4 ) /* (TCB) TCLK2 connected to XC2 */ +#define AT91C_TCB_TC2XC2S_NONE ( ( unsigned int ) 0x1 << 4 ) /* (TCB) None signal connected to XC2 */ +#define AT91C_TCB_TC2XC2S_TIOA0 ( ( unsigned int ) 0x2 << 4 ) /* (TCB) TIOA0 connected to XC2 */ +#define AT91C_TCB_TC2XC2S_TIOA2 ( ( unsigned int ) 0x3 << 4 ) /* (TCB) TIOA2 connected to XC2 */ -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR PWMC Channel Interface -// ***************************************************************************** -typedef struct _AT91S_PWMC_CH { - AT91_REG PWMC_CMR; // Channel Mode Register - AT91_REG PWMC_CDTYR; // Channel Duty Cycle Register - AT91_REG PWMC_CPRDR; // Channel Period Register - AT91_REG PWMC_CCNTR; // Channel Counter Register - AT91_REG PWMC_CUPDR; // Channel Update Register - AT91_REG PWMC_Reserved[3]; // Reserved -} AT91S_PWMC_CH, *AT91PS_PWMC_CH; +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR PWMC Channel Interface */ +/* ***************************************************************************** */ +typedef struct _AT91S_PWMC_CH +{ + AT91_REG PWMC_CMR; /* Channel Mode Register */ + AT91_REG PWMC_CDTYR; /* Channel Duty Cycle Register */ + AT91_REG PWMC_CPRDR; /* Channel Period Register */ + AT91_REG PWMC_CCNTR; /* Channel Counter Register */ + AT91_REG PWMC_CUPDR; /* Channel Update Register */ + AT91_REG PWMC_Reserved[ 3 ]; /* Reserved */ +} AT91S_PWMC_CH, * AT91PS_PWMC_CH; -// -------- PWMC_CMR : (PWMC_CH Offset: 0x0) PWMC Channel Mode Register -------- -#define AT91C_PWMC_CPRE ((unsigned int) 0xF << 0) // (PWMC_CH) Channel Pre-scaler : PWMC_CLKx -#define AT91C_PWMC_CPRE_MCK ((unsigned int) 0x0) // (PWMC_CH) -#define AT91C_PWMC_CPRE_MCKA ((unsigned int) 0xB) // (PWMC_CH) -#define AT91C_PWMC_CPRE_MCKB ((unsigned int) 0xC) // (PWMC_CH) -#define AT91C_PWMC_CALG ((unsigned int) 0x1 << 8) // (PWMC_CH) Channel Alignment -#define AT91C_PWMC_CPOL ((unsigned int) 0x1 << 9) // (PWMC_CH) Channel Polarity -#define AT91C_PWMC_CPD ((unsigned int) 0x1 << 10) // (PWMC_CH) Channel Update Period -// -------- PWMC_CDTYR : (PWMC_CH Offset: 0x4) PWMC Channel Duty Cycle Register -------- -#define AT91C_PWMC_CDTY ((unsigned int) 0x0 << 0) // (PWMC_CH) Channel Duty Cycle -// -------- PWMC_CPRDR : (PWMC_CH Offset: 0x8) PWMC Channel Period Register -------- -#define AT91C_PWMC_CPRD ((unsigned int) 0x0 << 0) // (PWMC_CH) Channel Period -// -------- PWMC_CCNTR : (PWMC_CH Offset: 0xc) PWMC Channel Counter Register -------- -#define AT91C_PWMC_CCNT ((unsigned int) 0x0 << 0) // (PWMC_CH) Channel Counter -// -------- PWMC_CUPDR : (PWMC_CH Offset: 0x10) PWMC Channel Update Register -------- -#define AT91C_PWMC_CUPD ((unsigned int) 0x0 << 0) // (PWMC_CH) Channel Update +/* -------- PWMC_CMR : (PWMC_CH Offset: 0x0) PWMC Channel Mode Register -------- */ +#define AT91C_PWMC_CPRE ( ( unsigned int ) 0xF << 0 ) /* (PWMC_CH) Channel Pre-scaler : PWMC_CLKx */ +#define AT91C_PWMC_CPRE_MCK ( ( unsigned int ) 0x0 ) /* (PWMC_CH) */ +#define AT91C_PWMC_CPRE_MCKA ( ( unsigned int ) 0xB ) /* (PWMC_CH) */ +#define AT91C_PWMC_CPRE_MCKB ( ( unsigned int ) 0xC ) /* (PWMC_CH) */ +#define AT91C_PWMC_CALG ( ( unsigned int ) 0x1 << 8 ) /* (PWMC_CH) Channel Alignment */ +#define AT91C_PWMC_CPOL ( ( unsigned int ) 0x1 << 9 ) /* (PWMC_CH) Channel Polarity */ +#define AT91C_PWMC_CPD ( ( unsigned int ) 0x1 << 10 ) /* (PWMC_CH) Channel Update Period */ +/* -------- PWMC_CDTYR : (PWMC_CH Offset: 0x4) PWMC Channel Duty Cycle Register -------- */ +#define AT91C_PWMC_CDTY ( ( unsigned int ) 0x0 << 0 ) /* (PWMC_CH) Channel Duty Cycle */ +/* -------- PWMC_CPRDR : (PWMC_CH Offset: 0x8) PWMC Channel Period Register -------- */ +#define AT91C_PWMC_CPRD ( ( unsigned int ) 0x0 << 0 ) /* (PWMC_CH) Channel Period */ +/* -------- PWMC_CCNTR : (PWMC_CH Offset: 0xc) PWMC Channel Counter Register -------- */ +#define AT91C_PWMC_CCNT ( ( unsigned int ) 0x0 << 0 ) /* (PWMC_CH) Channel Counter */ +/* -------- PWMC_CUPDR : (PWMC_CH Offset: 0x10) PWMC Channel Update Register -------- */ +#define AT91C_PWMC_CUPD ( ( unsigned int ) 0x0 << 0 ) /* (PWMC_CH) Channel Update */ -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Pulse Width Modulation Controller Interface -// ***************************************************************************** -typedef struct _AT91S_PWMC { - AT91_REG PWMC_MR; // PWMC Mode Register - AT91_REG PWMC_ENA; // PWMC Enable Register - AT91_REG PWMC_DIS; // PWMC Disable Register - AT91_REG PWMC_SR; // PWMC Status Register - AT91_REG PWMC_IER; // PWMC Interrupt Enable Register - AT91_REG PWMC_IDR; // PWMC Interrupt Disable Register - AT91_REG PWMC_IMR; // PWMC Interrupt Mask Register - AT91_REG PWMC_ISR; // PWMC Interrupt Status Register - AT91_REG Reserved0[55]; // - AT91_REG PWMC_VR; // PWMC Version Register - AT91_REG Reserved1[64]; // - AT91S_PWMC_CH PWMC_CH[32]; // PWMC Channel 0 -} AT91S_PWMC, *AT91PS_PWMC; +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR Pulse Width Modulation Controller Interface */ +/* ***************************************************************************** */ +typedef struct _AT91S_PWMC +{ + AT91_REG PWMC_MR; /* PWMC Mode Register */ + AT91_REG PWMC_ENA; /* PWMC Enable Register */ + AT91_REG PWMC_DIS; /* PWMC Disable Register */ + AT91_REG PWMC_SR; /* PWMC Status Register */ + AT91_REG PWMC_IER; /* PWMC Interrupt Enable Register */ + AT91_REG PWMC_IDR; /* PWMC Interrupt Disable Register */ + AT91_REG PWMC_IMR; /* PWMC Interrupt Mask Register */ + AT91_REG PWMC_ISR; /* PWMC Interrupt Status Register */ + AT91_REG Reserved0[ 55 ]; /* */ + AT91_REG PWMC_VR; /* PWMC Version Register */ + AT91_REG Reserved1[ 64 ]; /* */ + AT91S_PWMC_CH PWMC_CH[ 32 ]; /* PWMC Channel 0 */ +} AT91S_PWMC, * AT91PS_PWMC; -// -------- PWMC_MR : (PWMC Offset: 0x0) PWMC Mode Register -------- -#define AT91C_PWMC_DIVA ((unsigned int) 0xFF << 0) // (PWMC) CLKA divide factor. -#define AT91C_PWMC_PREA ((unsigned int) 0xF << 8) // (PWMC) Divider Input Clock Prescaler A -#define AT91C_PWMC_PREA_MCK ((unsigned int) 0x0 << 8) // (PWMC) -#define AT91C_PWMC_DIVB ((unsigned int) 0xFF << 16) // (PWMC) CLKB divide factor. -#define AT91C_PWMC_PREB ((unsigned int) 0xF << 24) // (PWMC) Divider Input Clock Prescaler B -#define AT91C_PWMC_PREB_MCK ((unsigned int) 0x0 << 24) // (PWMC) -// -------- PWMC_ENA : (PWMC Offset: 0x4) PWMC Enable Register -------- -#define AT91C_PWMC_CHID0 ((unsigned int) 0x1 << 0) // (PWMC) Channel ID 0 -#define AT91C_PWMC_CHID1 ((unsigned int) 0x1 << 1) // (PWMC) Channel ID 1 -#define AT91C_PWMC_CHID2 ((unsigned int) 0x1 << 2) // (PWMC) Channel ID 2 -#define AT91C_PWMC_CHID3 ((unsigned int) 0x1 << 3) // (PWMC) Channel ID 3 -#define AT91C_PWMC_CHID4 ((unsigned int) 0x1 << 4) // (PWMC) Channel ID 4 -#define AT91C_PWMC_CHID5 ((unsigned int) 0x1 << 5) // (PWMC) Channel ID 5 -#define AT91C_PWMC_CHID6 ((unsigned int) 0x1 << 6) // (PWMC) Channel ID 6 -#define AT91C_PWMC_CHID7 ((unsigned int) 0x1 << 7) // (PWMC) Channel ID 7 -// -------- PWMC_DIS : (PWMC Offset: 0x8) PWMC Disable Register -------- -// -------- PWMC_SR : (PWMC Offset: 0xc) PWMC Status Register -------- -// -------- PWMC_IER : (PWMC Offset: 0x10) PWMC Interrupt Enable Register -------- -// -------- PWMC_IDR : (PWMC Offset: 0x14) PWMC Interrupt Disable Register -------- -// -------- PWMC_IMR : (PWMC Offset: 0x18) PWMC Interrupt Mask Register -------- -// -------- PWMC_ISR : (PWMC Offset: 0x1c) PWMC Interrupt Status Register -------- +/* -------- PWMC_MR : (PWMC Offset: 0x0) PWMC Mode Register -------- */ +#define AT91C_PWMC_DIVA ( ( unsigned int ) 0xFF << 0 ) /* (PWMC) CLKA divide factor. */ +#define AT91C_PWMC_PREA ( ( unsigned int ) 0xF << 8 ) /* (PWMC) Divider Input Clock Prescaler A */ +#define AT91C_PWMC_PREA_MCK ( ( unsigned int ) 0x0 << 8 ) /* (PWMC) */ +#define AT91C_PWMC_DIVB ( ( unsigned int ) 0xFF << 16 ) /* (PWMC) CLKB divide factor. */ +#define AT91C_PWMC_PREB ( ( unsigned int ) 0xF << 24 ) /* (PWMC) Divider Input Clock Prescaler B */ +#define AT91C_PWMC_PREB_MCK ( ( unsigned int ) 0x0 << 24 ) /* (PWMC) */ +/* -------- PWMC_ENA : (PWMC Offset: 0x4) PWMC Enable Register -------- */ +#define AT91C_PWMC_CHID0 ( ( unsigned int ) 0x1 << 0 ) /* (PWMC) Channel ID 0 */ +#define AT91C_PWMC_CHID1 ( ( unsigned int ) 0x1 << 1 ) /* (PWMC) Channel ID 1 */ +#define AT91C_PWMC_CHID2 ( ( unsigned int ) 0x1 << 2 ) /* (PWMC) Channel ID 2 */ +#define AT91C_PWMC_CHID3 ( ( unsigned int ) 0x1 << 3 ) /* (PWMC) Channel ID 3 */ +#define AT91C_PWMC_CHID4 ( ( unsigned int ) 0x1 << 4 ) /* (PWMC) Channel ID 4 */ +#define AT91C_PWMC_CHID5 ( ( unsigned int ) 0x1 << 5 ) /* (PWMC) Channel ID 5 */ +#define AT91C_PWMC_CHID6 ( ( unsigned int ) 0x1 << 6 ) /* (PWMC) Channel ID 6 */ +#define AT91C_PWMC_CHID7 ( ( unsigned int ) 0x1 << 7 ) /* (PWMC) Channel ID 7 */ +/* -------- PWMC_DIS : (PWMC Offset: 0x8) PWMC Disable Register -------- */ +/* -------- PWMC_SR : (PWMC Offset: 0xc) PWMC Status Register -------- */ +/* -------- PWMC_IER : (PWMC Offset: 0x10) PWMC Interrupt Enable Register -------- */ +/* -------- PWMC_IDR : (PWMC Offset: 0x14) PWMC Interrupt Disable Register -------- */ +/* -------- PWMC_IMR : (PWMC Offset: 0x18) PWMC Interrupt Mask Register -------- */ +/* -------- PWMC_ISR : (PWMC Offset: 0x1c) PWMC Interrupt Status Register -------- */ -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR USB Device Interface -// ***************************************************************************** -typedef struct _AT91S_UDP { - AT91_REG UDP_NUM; // Frame Number Register - AT91_REG UDP_GLBSTATE; // Global State Register - AT91_REG UDP_FADDR; // Function Address Register - AT91_REG Reserved0[1]; // - AT91_REG UDP_IER; // Interrupt Enable Register - AT91_REG UDP_IDR; // Interrupt Disable Register - AT91_REG UDP_IMR; // Interrupt Mask Register - AT91_REG UDP_ISR; // Interrupt Status Register - AT91_REG UDP_ICR; // Interrupt Clear Register - AT91_REG Reserved1[1]; // - AT91_REG UDP_RSTEP; // Reset Endpoint Register - AT91_REG Reserved2[1]; // - AT91_REG UDP_CSR[8]; // Endpoint Control and Status Register - AT91_REG UDP_FDR[8]; // Endpoint FIFO Data Register -} AT91S_UDP, *AT91PS_UDP; +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR USB Device Interface */ +/* ***************************************************************************** */ +typedef struct _AT91S_UDP +{ + AT91_REG UDP_NUM; /* Frame Number Register */ + AT91_REG UDP_GLBSTATE; /* Global State Register */ + AT91_REG UDP_FADDR; /* Function Address Register */ + AT91_REG Reserved0[ 1 ]; /* */ + AT91_REG UDP_IER; /* Interrupt Enable Register */ + AT91_REG UDP_IDR; /* Interrupt Disable Register */ + AT91_REG UDP_IMR; /* Interrupt Mask Register */ + AT91_REG UDP_ISR; /* Interrupt Status Register */ + AT91_REG UDP_ICR; /* Interrupt Clear Register */ + AT91_REG Reserved1[ 1 ]; /* */ + AT91_REG UDP_RSTEP; /* Reset Endpoint Register */ + AT91_REG Reserved2[ 1 ]; /* */ + AT91_REG UDP_CSR[ 8 ]; /* Endpoint Control and Status Register */ + AT91_REG UDP_FDR[ 8 ]; /* Endpoint FIFO Data Register */ +} AT91S_UDP, * AT91PS_UDP; -// -------- UDP_FRM_NUM : (UDP Offset: 0x0) USB Frame Number Register -------- -#define AT91C_UDP_FRM_NUM ((unsigned int) 0x7FF << 0) // (UDP) Frame Number as Defined in the Packet Field Formats -#define AT91C_UDP_FRM_ERR ((unsigned int) 0x1 << 16) // (UDP) Frame Error -#define AT91C_UDP_FRM_OK ((unsigned int) 0x1 << 17) // (UDP) Frame OK -// -------- UDP_GLB_STATE : (UDP Offset: 0x4) USB Global State Register -------- -#define AT91C_UDP_FADDEN ((unsigned int) 0x1 << 0) // (UDP) Function Address Enable -#define AT91C_UDP_CONFG ((unsigned int) 0x1 << 1) // (UDP) Configured -#define AT91C_UDP_RMWUPE ((unsigned int) 0x1 << 2) // (UDP) Remote Wake Up Enable -#define AT91C_UDP_RSMINPR ((unsigned int) 0x1 << 3) // (UDP) A Resume Has Been Sent to the Host -// -------- UDP_FADDR : (UDP Offset: 0x8) USB Function Address Register -------- -#define AT91C_UDP_FADD ((unsigned int) 0xFF << 0) // (UDP) Function Address Value -#define AT91C_UDP_FEN ((unsigned int) 0x1 << 8) // (UDP) Function Enable -// -------- UDP_IER : (UDP Offset: 0x10) USB Interrupt Enable Register -------- -#define AT91C_UDP_EPINT0 ((unsigned int) 0x1 << 0) // (UDP) Endpoint 0 Interrupt -#define AT91C_UDP_EPINT1 ((unsigned int) 0x1 << 1) // (UDP) Endpoint 0 Interrupt -#define AT91C_UDP_EPINT2 ((unsigned int) 0x1 << 2) // (UDP) Endpoint 2 Interrupt -#define AT91C_UDP_EPINT3 ((unsigned int) 0x1 << 3) // (UDP) Endpoint 3 Interrupt -#define AT91C_UDP_EPINT4 ((unsigned int) 0x1 << 4) // (UDP) Endpoint 4 Interrupt -#define AT91C_UDP_EPINT5 ((unsigned int) 0x1 << 5) // (UDP) Endpoint 5 Interrupt -#define AT91C_UDP_EPINT6 ((unsigned int) 0x1 << 6) // (UDP) Endpoint 6 Interrupt -#define AT91C_UDP_EPINT7 ((unsigned int) 0x1 << 7) // (UDP) Endpoint 7 Interrupt -#define AT91C_UDP_RXSUSP ((unsigned int) 0x1 << 8) // (UDP) USB Suspend Interrupt -#define AT91C_UDP_RXRSM ((unsigned int) 0x1 << 9) // (UDP) USB Resume Interrupt -#define AT91C_UDP_EXTRSM ((unsigned int) 0x1 << 10) // (UDP) USB External Resume Interrupt -#define AT91C_UDP_SOFINT ((unsigned int) 0x1 << 11) // (UDP) USB Start Of frame Interrupt -#define AT91C_UDP_WAKEUP ((unsigned int) 0x1 << 13) // (UDP) USB Resume Interrupt -// -------- UDP_IDR : (UDP Offset: 0x14) USB Interrupt Disable Register -------- -// -------- UDP_IMR : (UDP Offset: 0x18) USB Interrupt Mask Register -------- -// -------- UDP_ISR : (UDP Offset: 0x1c) USB Interrupt Status Register -------- -#define AT91C_UDP_ENDBUSRES ((unsigned int) 0x1 << 12) // (UDP) USB End Of Bus Reset Interrupt -// -------- UDP_ICR : (UDP Offset: 0x20) USB Interrupt Clear Register -------- -// -------- UDP_RST_EP : (UDP Offset: 0x28) USB Reset Endpoint Register -------- -#define AT91C_UDP_EP0 ((unsigned int) 0x1 << 0) // (UDP) Reset Endpoint 0 -#define AT91C_UDP_EP1 ((unsigned int) 0x1 << 1) // (UDP) Reset Endpoint 1 -#define AT91C_UDP_EP2 ((unsigned int) 0x1 << 2) // (UDP) Reset Endpoint 2 -#define AT91C_UDP_EP3 ((unsigned int) 0x1 << 3) // (UDP) Reset Endpoint 3 -#define AT91C_UDP_EP4 ((unsigned int) 0x1 << 4) // (UDP) Reset Endpoint 4 -#define AT91C_UDP_EP5 ((unsigned int) 0x1 << 5) // (UDP) Reset Endpoint 5 -#define AT91C_UDP_EP6 ((unsigned int) 0x1 << 6) // (UDP) Reset Endpoint 6 -#define AT91C_UDP_EP7 ((unsigned int) 0x1 << 7) // (UDP) Reset Endpoint 7 -// -------- UDP_CSR : (UDP Offset: 0x30) USB Endpoint Control and Status Register -------- -#define AT91C_UDP_TXCOMP ((unsigned int) 0x1 << 0) // (UDP) Generates an IN packet with data previously written in the DPR -#define AT91C_UDP_RX_DATA_BK0 ((unsigned int) 0x1 << 1) // (UDP) Receive Data Bank 0 -#define AT91C_UDP_RXSETUP ((unsigned int) 0x1 << 2) // (UDP) Sends STALL to the Host (Control endpoints) -#define AT91C_UDP_ISOERROR ((unsigned int) 0x1 << 3) // (UDP) Isochronous error (Isochronous endpoints) -#define AT91C_UDP_TXPKTRDY ((unsigned int) 0x1 << 4) // (UDP) Transmit Packet Ready -#define AT91C_UDP_FORCESTALL ((unsigned int) 0x1 << 5) // (UDP) Force Stall (used by Control, Bulk and Isochronous endpoints). -#define AT91C_UDP_RX_DATA_BK1 ((unsigned int) 0x1 << 6) // (UDP) Receive Data Bank 1 (only used by endpoints with ping-pong attributes). -#define AT91C_UDP_DIR ((unsigned int) 0x1 << 7) // (UDP) Transfer Direction -#define AT91C_UDP_EPTYPE ((unsigned int) 0x7 << 8) // (UDP) Endpoint type -#define AT91C_UDP_EPTYPE_CTRL ((unsigned int) 0x0 << 8) // (UDP) Control -#define AT91C_UDP_EPTYPE_ISO_OUT ((unsigned int) 0x1 << 8) // (UDP) Isochronous OUT -#define AT91C_UDP_EPTYPE_BULK_OUT ((unsigned int) 0x2 << 8) // (UDP) Bulk OUT -#define AT91C_UDP_EPTYPE_INT_OUT ((unsigned int) 0x3 << 8) // (UDP) Interrupt OUT -#define AT91C_UDP_EPTYPE_ISO_IN ((unsigned int) 0x5 << 8) // (UDP) Isochronous IN -#define AT91C_UDP_EPTYPE_BULK_IN ((unsigned int) 0x6 << 8) // (UDP) Bulk IN -#define AT91C_UDP_EPTYPE_INT_IN ((unsigned int) 0x7 << 8) // (UDP) Interrupt IN -#define AT91C_UDP_DTGLE ((unsigned int) 0x1 << 11) // (UDP) Data Toggle -#define AT91C_UDP_EPEDS ((unsigned int) 0x1 << 15) // (UDP) Endpoint Enable Disable -#define AT91C_UDP_RXBYTECNT ((unsigned int) 0x7FF << 16) // (UDP) Number Of Bytes Available in the FIFO +/* -------- UDP_FRM_NUM : (UDP Offset: 0x0) USB Frame Number Register -------- */ +#define AT91C_UDP_FRM_NUM ( ( unsigned int ) 0x7FF << 0 ) /* (UDP) Frame Number as Defined in the Packet Field Formats */ +#define AT91C_UDP_FRM_ERR ( ( unsigned int ) 0x1 << 16 ) /* (UDP) Frame Error */ +#define AT91C_UDP_FRM_OK ( ( unsigned int ) 0x1 << 17 ) /* (UDP) Frame OK */ +/* -------- UDP_GLB_STATE : (UDP Offset: 0x4) USB Global State Register -------- */ +#define AT91C_UDP_FADDEN ( ( unsigned int ) 0x1 << 0 ) /* (UDP) Function Address Enable */ +#define AT91C_UDP_CONFG ( ( unsigned int ) 0x1 << 1 ) /* (UDP) Configured */ +#define AT91C_UDP_RMWUPE ( ( unsigned int ) 0x1 << 2 ) /* (UDP) Remote Wake Up Enable */ +#define AT91C_UDP_RSMINPR ( ( unsigned int ) 0x1 << 3 ) /* (UDP) A Resume Has Been Sent to the Host */ +/* -------- UDP_FADDR : (UDP Offset: 0x8) USB Function Address Register -------- */ +#define AT91C_UDP_FADD ( ( unsigned int ) 0xFF << 0 ) /* (UDP) Function Address Value */ +#define AT91C_UDP_FEN ( ( unsigned int ) 0x1 << 8 ) /* (UDP) Function Enable */ +/* -------- UDP_IER : (UDP Offset: 0x10) USB Interrupt Enable Register -------- */ +#define AT91C_UDP_EPINT0 ( ( unsigned int ) 0x1 << 0 ) /* (UDP) Endpoint 0 Interrupt */ +#define AT91C_UDP_EPINT1 ( ( unsigned int ) 0x1 << 1 ) /* (UDP) Endpoint 0 Interrupt */ +#define AT91C_UDP_EPINT2 ( ( unsigned int ) 0x1 << 2 ) /* (UDP) Endpoint 2 Interrupt */ +#define AT91C_UDP_EPINT3 ( ( unsigned int ) 0x1 << 3 ) /* (UDP) Endpoint 3 Interrupt */ +#define AT91C_UDP_EPINT4 ( ( unsigned int ) 0x1 << 4 ) /* (UDP) Endpoint 4 Interrupt */ +#define AT91C_UDP_EPINT5 ( ( unsigned int ) 0x1 << 5 ) /* (UDP) Endpoint 5 Interrupt */ +#define AT91C_UDP_EPINT6 ( ( unsigned int ) 0x1 << 6 ) /* (UDP) Endpoint 6 Interrupt */ +#define AT91C_UDP_EPINT7 ( ( unsigned int ) 0x1 << 7 ) /* (UDP) Endpoint 7 Interrupt */ +#define AT91C_UDP_RXSUSP ( ( unsigned int ) 0x1 << 8 ) /* (UDP) USB Suspend Interrupt */ +#define AT91C_UDP_RXRSM ( ( unsigned int ) 0x1 << 9 ) /* (UDP) USB Resume Interrupt */ +#define AT91C_UDP_EXTRSM ( ( unsigned int ) 0x1 << 10 ) /* (UDP) USB External Resume Interrupt */ +#define AT91C_UDP_SOFINT ( ( unsigned int ) 0x1 << 11 ) /* (UDP) USB Start Of frame Interrupt */ +#define AT91C_UDP_WAKEUP ( ( unsigned int ) 0x1 << 13 ) /* (UDP) USB Resume Interrupt */ +/* -------- UDP_IDR : (UDP Offset: 0x14) USB Interrupt Disable Register -------- */ +/* -------- UDP_IMR : (UDP Offset: 0x18) USB Interrupt Mask Register -------- */ +/* -------- UDP_ISR : (UDP Offset: 0x1c) USB Interrupt Status Register -------- */ +#define AT91C_UDP_ENDBUSRES ( ( unsigned int ) 0x1 << 12 ) /* (UDP) USB End Of Bus Reset Interrupt */ +/* -------- UDP_ICR : (UDP Offset: 0x20) USB Interrupt Clear Register -------- */ +/* -------- UDP_RST_EP : (UDP Offset: 0x28) USB Reset Endpoint Register -------- */ +#define AT91C_UDP_EP0 ( ( unsigned int ) 0x1 << 0 ) /* (UDP) Reset Endpoint 0 */ +#define AT91C_UDP_EP1 ( ( unsigned int ) 0x1 << 1 ) /* (UDP) Reset Endpoint 1 */ +#define AT91C_UDP_EP2 ( ( unsigned int ) 0x1 << 2 ) /* (UDP) Reset Endpoint 2 */ +#define AT91C_UDP_EP3 ( ( unsigned int ) 0x1 << 3 ) /* (UDP) Reset Endpoint 3 */ +#define AT91C_UDP_EP4 ( ( unsigned int ) 0x1 << 4 ) /* (UDP) Reset Endpoint 4 */ +#define AT91C_UDP_EP5 ( ( unsigned int ) 0x1 << 5 ) /* (UDP) Reset Endpoint 5 */ +#define AT91C_UDP_EP6 ( ( unsigned int ) 0x1 << 6 ) /* (UDP) Reset Endpoint 6 */ +#define AT91C_UDP_EP7 ( ( unsigned int ) 0x1 << 7 ) /* (UDP) Reset Endpoint 7 */ +/* -------- UDP_CSR : (UDP Offset: 0x30) USB Endpoint Control and Status Register -------- */ +#define AT91C_UDP_TXCOMP ( ( unsigned int ) 0x1 << 0 ) /* (UDP) Generates an IN packet with data previously written in the DPR */ +#define AT91C_UDP_RX_DATA_BK0 ( ( unsigned int ) 0x1 << 1 ) /* (UDP) Receive Data Bank 0 */ +#define AT91C_UDP_RXSETUP ( ( unsigned int ) 0x1 << 2 ) /* (UDP) Sends STALL to the Host (Control endpoints) */ +#define AT91C_UDP_ISOERROR ( ( unsigned int ) 0x1 << 3 ) /* (UDP) Isochronous error (Isochronous endpoints) */ +#define AT91C_UDP_TXPKTRDY ( ( unsigned int ) 0x1 << 4 ) /* (UDP) Transmit Packet Ready */ +#define AT91C_UDP_FORCESTALL ( ( unsigned int ) 0x1 << 5 ) /* (UDP) Force Stall (used by Control, Bulk and Isochronous endpoints). */ +#define AT91C_UDP_RX_DATA_BK1 ( ( unsigned int ) 0x1 << 6 ) /* (UDP) Receive Data Bank 1 (only used by endpoints with ping-pong attributes). */ +#define AT91C_UDP_DIR ( ( unsigned int ) 0x1 << 7 ) /* (UDP) Transfer Direction */ +#define AT91C_UDP_EPTYPE ( ( unsigned int ) 0x7 << 8 ) /* (UDP) Endpoint type */ +#define AT91C_UDP_EPTYPE_CTRL ( ( unsigned int ) 0x0 << 8 ) /* (UDP) Control */ +#define AT91C_UDP_EPTYPE_ISO_OUT ( ( unsigned int ) 0x1 << 8 ) /* (UDP) Isochronous OUT */ +#define AT91C_UDP_EPTYPE_BULK_OUT ( ( unsigned int ) 0x2 << 8 ) /* (UDP) Bulk OUT */ +#define AT91C_UDP_EPTYPE_INT_OUT ( ( unsigned int ) 0x3 << 8 ) /* (UDP) Interrupt OUT */ +#define AT91C_UDP_EPTYPE_ISO_IN ( ( unsigned int ) 0x5 << 8 ) /* (UDP) Isochronous IN */ +#define AT91C_UDP_EPTYPE_BULK_IN ( ( unsigned int ) 0x6 << 8 ) /* (UDP) Bulk IN */ +#define AT91C_UDP_EPTYPE_INT_IN ( ( unsigned int ) 0x7 << 8 ) /* (UDP) Interrupt IN */ +#define AT91C_UDP_DTGLE ( ( unsigned int ) 0x1 << 11 ) /* (UDP) Data Toggle */ +#define AT91C_UDP_EPEDS ( ( unsigned int ) 0x1 << 15 ) /* (UDP) Endpoint Enable Disable */ +#define AT91C_UDP_RXBYTECNT ( ( unsigned int ) 0x7FF << 16 ) /* (UDP) Number Of Bytes Available in the FIFO */ -// ***************************************************************************** -// REGISTER ADDRESS DEFINITION FOR AT91SAM7S64 -// ***************************************************************************** -// ========== Register definition for SYSC peripheral ========== -#define AT91C_SYSC_SYSC_VRPM ((AT91_REG *) 0xFFFFFD60) // (SYSC) Voltage Regulator Power Mode Register -// ========== Register definition for AIC peripheral ========== -#define AT91C_AIC_ICCR ((AT91_REG *) 0xFFFFF128) // (AIC) Interrupt Clear Command Register -#define AT91C_AIC_IECR ((AT91_REG *) 0xFFFFF120) // (AIC) Interrupt Enable Command Register -#define AT91C_AIC_SMR ((AT91_REG *) 0xFFFFF000) // (AIC) Source Mode Register -#define AT91C_AIC_ISCR ((AT91_REG *) 0xFFFFF12C) // (AIC) Interrupt Set Command Register -#define AT91C_AIC_EOICR ((AT91_REG *) 0xFFFFF130) // (AIC) End of Interrupt Command Register -#define AT91C_AIC_DCR ((AT91_REG *) 0xFFFFF138) // (AIC) Debug Control Register (Protect) -#define AT91C_AIC_FFER ((AT91_REG *) 0xFFFFF140) // (AIC) Fast Forcing Enable Register -#define AT91C_AIC_SVR ((AT91_REG *) 0xFFFFF080) // (AIC) Source Vector Register -#define AT91C_AIC_SPU ((AT91_REG *) 0xFFFFF134) // (AIC) Spurious Vector Register -#define AT91C_AIC_FFDR ((AT91_REG *) 0xFFFFF144) // (AIC) Fast Forcing Disable Register -#define AT91C_AIC_FVR ((AT91_REG *) 0xFFFFF104) // (AIC) FIQ Vector Register -#define AT91C_AIC_FFSR ((AT91_REG *) 0xFFFFF148) // (AIC) Fast Forcing Status Register -#define AT91C_AIC_IMR ((AT91_REG *) 0xFFFFF110) // (AIC) Interrupt Mask Register -#define AT91C_AIC_ISR ((AT91_REG *) 0xFFFFF108) // (AIC) Interrupt Status Register -#define AT91C_AIC_IVR ((AT91_REG *) 0xFFFFF100) // (AIC) IRQ Vector Register -#define AT91C_AIC_IDCR ((AT91_REG *) 0xFFFFF124) // (AIC) Interrupt Disable Command Register -#define AT91C_AIC_CISR ((AT91_REG *) 0xFFFFF114) // (AIC) Core Interrupt Status Register -#define AT91C_AIC_IPR ((AT91_REG *) 0xFFFFF10C) // (AIC) Interrupt Pending Register -// ========== Register definition for DBGU peripheral ========== -#define AT91C_DBGU_C2R ((AT91_REG *) 0xFFFFF244) // (DBGU) Chip ID2 Register -#define AT91C_DBGU_THR ((AT91_REG *) 0xFFFFF21C) // (DBGU) Transmitter Holding Register -#define AT91C_DBGU_CSR ((AT91_REG *) 0xFFFFF214) // (DBGU) Channel Status Register -#define AT91C_DBGU_IDR ((AT91_REG *) 0xFFFFF20C) // (DBGU) Interrupt Disable Register -#define AT91C_DBGU_MR ((AT91_REG *) 0xFFFFF204) // (DBGU) Mode Register -#define AT91C_DBGU_FNTR ((AT91_REG *) 0xFFFFF248) // (DBGU) Force NTRST Register -#define AT91C_DBGU_C1R ((AT91_REG *) 0xFFFFF240) // (DBGU) Chip ID1 Register -#define AT91C_DBGU_BRGR ((AT91_REG *) 0xFFFFF220) // (DBGU) Baud Rate Generator Register -#define AT91C_DBGU_RHR ((AT91_REG *) 0xFFFFF218) // (DBGU) Receiver Holding Register -#define AT91C_DBGU_IMR ((AT91_REG *) 0xFFFFF210) // (DBGU) Interrupt Mask Register -#define AT91C_DBGU_IER ((AT91_REG *) 0xFFFFF208) // (DBGU) Interrupt Enable Register -#define AT91C_DBGU_CR ((AT91_REG *) 0xFFFFF200) // (DBGU) Control Register -// ========== Register definition for PDC_DBGU peripheral ========== -#define AT91C_DBGU_TNCR ((AT91_REG *) 0xFFFFF31C) // (PDC_DBGU) Transmit Next Counter Register -#define AT91C_DBGU_RNCR ((AT91_REG *) 0xFFFFF314) // (PDC_DBGU) Receive Next Counter Register -#define AT91C_DBGU_PTCR ((AT91_REG *) 0xFFFFF320) // (PDC_DBGU) PDC Transfer Control Register -#define AT91C_DBGU_PTSR ((AT91_REG *) 0xFFFFF324) // (PDC_DBGU) PDC Transfer Status Register -#define AT91C_DBGU_RCR ((AT91_REG *) 0xFFFFF304) // (PDC_DBGU) Receive Counter Register -#define AT91C_DBGU_TCR ((AT91_REG *) 0xFFFFF30C) // (PDC_DBGU) Transmit Counter Register -#define AT91C_DBGU_RPR ((AT91_REG *) 0xFFFFF300) // (PDC_DBGU) Receive Pointer Register -#define AT91C_DBGU_TPR ((AT91_REG *) 0xFFFFF308) // (PDC_DBGU) Transmit Pointer Register -#define AT91C_DBGU_RNPR ((AT91_REG *) 0xFFFFF310) // (PDC_DBGU) Receive Next Pointer Register -#define AT91C_DBGU_TNPR ((AT91_REG *) 0xFFFFF318) // (PDC_DBGU) Transmit Next Pointer Register -// ========== Register definition for PIOA peripheral ========== -#define AT91C_PIOA_IMR ((AT91_REG *) 0xFFFFF448) // (PIOA) Interrupt Mask Register -#define AT91C_PIOA_IER ((AT91_REG *) 0xFFFFF440) // (PIOA) Interrupt Enable Register -#define AT91C_PIOA_OWDR ((AT91_REG *) 0xFFFFF4A4) // (PIOA) Output Write Disable Register -#define AT91C_PIOA_ISR ((AT91_REG *) 0xFFFFF44C) // (PIOA) Interrupt Status Register -#define AT91C_PIOA_PPUDR ((AT91_REG *) 0xFFFFF460) // (PIOA) Pull-up Disable Register -#define AT91C_PIOA_MDSR ((AT91_REG *) 0xFFFFF458) // (PIOA) Multi-driver Status Register -#define AT91C_PIOA_MDER ((AT91_REG *) 0xFFFFF450) // (PIOA) Multi-driver Enable Register -#define AT91C_PIOA_PER ((AT91_REG *) 0xFFFFF400) // (PIOA) PIO Enable Register -#define AT91C_PIOA_PSR ((AT91_REG *) 0xFFFFF408) // (PIOA) PIO Status Register -#define AT91C_PIOA_OER ((AT91_REG *) 0xFFFFF410) // (PIOA) Output Enable Register -#define AT91C_PIOA_BSR ((AT91_REG *) 0xFFFFF474) // (PIOA) Select B Register -#define AT91C_PIOA_PPUER ((AT91_REG *) 0xFFFFF464) // (PIOA) Pull-up Enable Register -#define AT91C_PIOA_MDDR ((AT91_REG *) 0xFFFFF454) // (PIOA) Multi-driver Disable Register -#define AT91C_PIOA_PDR ((AT91_REG *) 0xFFFFF404) // (PIOA) PIO Disable Register -#define AT91C_PIOA_ODR ((AT91_REG *) 0xFFFFF414) // (PIOA) Output Disable Registerr -#define AT91C_PIOA_IFDR ((AT91_REG *) 0xFFFFF424) // (PIOA) Input Filter Disable Register -#define AT91C_PIOA_ABSR ((AT91_REG *) 0xFFFFF478) // (PIOA) AB Select Status Register -#define AT91C_PIOA_ASR ((AT91_REG *) 0xFFFFF470) // (PIOA) Select A Register -#define AT91C_PIOA_PPUSR ((AT91_REG *) 0xFFFFF468) // (PIOA) Pad Pull-up Status Register -#define AT91C_PIOA_ODSR ((AT91_REG *) 0xFFFFF438) // (PIOA) Output Data Status Register -#define AT91C_PIOA_SODR ((AT91_REG *) 0xFFFFF430) // (PIOA) Set Output Data Register -#define AT91C_PIOA_IFSR ((AT91_REG *) 0xFFFFF428) // (PIOA) Input Filter Status Register -#define AT91C_PIOA_IFER ((AT91_REG *) 0xFFFFF420) // (PIOA) Input Filter Enable Register -#define AT91C_PIOA_OSR ((AT91_REG *) 0xFFFFF418) // (PIOA) Output Status Register -#define AT91C_PIOA_IDR ((AT91_REG *) 0xFFFFF444) // (PIOA) Interrupt Disable Register -#define AT91C_PIOA_PDSR ((AT91_REG *) 0xFFFFF43C) // (PIOA) Pin Data Status Register -#define AT91C_PIOA_CODR ((AT91_REG *) 0xFFFFF434) // (PIOA) Clear Output Data Register -#define AT91C_PIOA_OWSR ((AT91_REG *) 0xFFFFF4A8) // (PIOA) Output Write Status Register -#define AT91C_PIOA_OWER ((AT91_REG *) 0xFFFFF4A0) // (PIOA) Output Write Enable Register -// ========== Register definition for CKGR peripheral ========== -#define AT91C_CKGR_PLLR ((AT91_REG *) 0xFFFFFC2C) // (CKGR) PLL Register -#define AT91C_CKGR_MCFR ((AT91_REG *) 0xFFFFFC24) // (CKGR) Main Clock Frequency Register -#define AT91C_CKGR_MOR ((AT91_REG *) 0xFFFFFC20) // (CKGR) Main Oscillator Register -// ========== Register definition for PMC peripheral ========== -#define AT91C_PMC_SCSR ((AT91_REG *) 0xFFFFFC08) // (PMC) System Clock Status Register -#define AT91C_PMC_SCER ((AT91_REG *) 0xFFFFFC00) // (PMC) System Clock Enable Register -#define AT91C_PMC_IMR ((AT91_REG *) 0xFFFFFC6C) // (PMC) Interrupt Mask Register -#define AT91C_PMC_IDR ((AT91_REG *) 0xFFFFFC64) // (PMC) Interrupt Disable Register -#define AT91C_PMC_PCDR ((AT91_REG *) 0xFFFFFC14) // (PMC) Peripheral Clock Disable Register -#define AT91C_PMC_SCDR ((AT91_REG *) 0xFFFFFC04) // (PMC) System Clock Disable Register -#define AT91C_PMC_SR ((AT91_REG *) 0xFFFFFC68) // (PMC) Status Register -#define AT91C_PMC_IER ((AT91_REG *) 0xFFFFFC60) // (PMC) Interrupt Enable Register -#define AT91C_PMC_MCKR ((AT91_REG *) 0xFFFFFC30) // (PMC) Master Clock Register -#define AT91C_PMC_MOR ((AT91_REG *) 0xFFFFFC20) // (PMC) Main Oscillator Register -#define AT91C_PMC_PCER ((AT91_REG *) 0xFFFFFC10) // (PMC) Peripheral Clock Enable Register -#define AT91C_PMC_PCSR ((AT91_REG *) 0xFFFFFC18) // (PMC) Peripheral Clock Status Register -#define AT91C_PMC_PLLR ((AT91_REG *) 0xFFFFFC2C) // (PMC) PLL Register -#define AT91C_PMC_MCFR ((AT91_REG *) 0xFFFFFC24) // (PMC) Main Clock Frequency Register -#define AT91C_PMC_PCKR ((AT91_REG *) 0xFFFFFC40) // (PMC) Programmable Clock Register -// ========== Register definition for RSTC peripheral ========== -#define AT91C_RSTC_RSR ((AT91_REG *) 0xFFFFFD04) // (RSTC) Reset Status Register -#define AT91C_RSTC_RMR ((AT91_REG *) 0xFFFFFD08) // (RSTC) Reset Mode Register -#define AT91C_RSTC_RCR ((AT91_REG *) 0xFFFFFD00) // (RSTC) Reset Control Register -// ========== Register definition for RTTC peripheral ========== -#define AT91C_RTTC_RTSR ((AT91_REG *) 0xFFFFFD2C) // (RTTC) Real-time Status Register -#define AT91C_RTTC_RTAR ((AT91_REG *) 0xFFFFFD24) // (RTTC) Real-time Alarm Register -#define AT91C_RTTC_RTVR ((AT91_REG *) 0xFFFFFD28) // (RTTC) Real-time Value Register -#define AT91C_RTTC_RTMR ((AT91_REG *) 0xFFFFFD20) // (RTTC) Real-time Mode Register -// ========== Register definition for PITC peripheral ========== -#define AT91C_PITC_PIIR ((AT91_REG *) 0xFFFFFD3C) // (PITC) Period Interval Image Register -#define AT91C_PITC_PISR ((AT91_REG *) 0xFFFFFD34) // (PITC) Period Interval Status Register -#define AT91C_PITC_PIVR ((AT91_REG *) 0xFFFFFD38) // (PITC) Period Interval Value Register -#define AT91C_PITC_PIMR ((AT91_REG *) 0xFFFFFD30) // (PITC) Period Interval Mode Register -// ========== Register definition for WDTC peripheral ========== -#define AT91C_WDTC_WDMR ((AT91_REG *) 0xFFFFFD44) // (WDTC) Watchdog Mode Register -#define AT91C_WDTC_WDSR ((AT91_REG *) 0xFFFFFD48) // (WDTC) Watchdog Status Register -#define AT91C_WDTC_WDCR ((AT91_REG *) 0xFFFFFD40) // (WDTC) Watchdog Control Register -// ========== Register definition for MC peripheral ========== -#define AT91C_MC_FCR ((AT91_REG *) 0xFFFFFF64) // (MC) MC Flash Command Register -#define AT91C_MC_ASR ((AT91_REG *) 0xFFFFFF04) // (MC) MC Abort Status Register -#define AT91C_MC_FSR ((AT91_REG *) 0xFFFFFF68) // (MC) MC Flash Status Register -#define AT91C_MC_FMR ((AT91_REG *) 0xFFFFFF60) // (MC) MC Flash Mode Register -#define AT91C_MC_AASR ((AT91_REG *) 0xFFFFFF08) // (MC) MC Abort Address Status Register -#define AT91C_MC_RCR ((AT91_REG *) 0xFFFFFF00) // (MC) MC Remap Control Register -// ========== Register definition for PDC_SPI peripheral ========== -#define AT91C_SPI_PTCR ((AT91_REG *) 0xFFFE0120) // (PDC_SPI) PDC Transfer Control Register -#define AT91C_SPI_TNPR ((AT91_REG *) 0xFFFE0118) // (PDC_SPI) Transmit Next Pointer Register -#define AT91C_SPI_RNPR ((AT91_REG *) 0xFFFE0110) // (PDC_SPI) Receive Next Pointer Register -#define AT91C_SPI_TPR ((AT91_REG *) 0xFFFE0108) // (PDC_SPI) Transmit Pointer Register -#define AT91C_SPI_RPR ((AT91_REG *) 0xFFFE0100) // (PDC_SPI) Receive Pointer Register -#define AT91C_SPI_PTSR ((AT91_REG *) 0xFFFE0124) // (PDC_SPI) PDC Transfer Status Register -#define AT91C_SPI_TNCR ((AT91_REG *) 0xFFFE011C) // (PDC_SPI) Transmit Next Counter Register -#define AT91C_SPI_RNCR ((AT91_REG *) 0xFFFE0114) // (PDC_SPI) Receive Next Counter Register -#define AT91C_SPI_TCR ((AT91_REG *) 0xFFFE010C) // (PDC_SPI) Transmit Counter Register -#define AT91C_SPI_RCR ((AT91_REG *) 0xFFFE0104) // (PDC_SPI) Receive Counter Register -// ========== Register definition for SPI peripheral ========== -#define AT91C_SPI_CSR ((AT91_REG *) 0xFFFE0030) // (SPI) Chip Select Register -#define AT91C_SPI_IDR ((AT91_REG *) 0xFFFE0018) // (SPI) Interrupt Disable Register -#define AT91C_SPI_SR ((AT91_REG *) 0xFFFE0010) // (SPI) Status Register -#define AT91C_SPI_RDR ((AT91_REG *) 0xFFFE0008) // (SPI) Receive Data Register -#define AT91C_SPI_CR ((AT91_REG *) 0xFFFE0000) // (SPI) Control Register -#define AT91C_SPI_IMR ((AT91_REG *) 0xFFFE001C) // (SPI) Interrupt Mask Register -#define AT91C_SPI_IER ((AT91_REG *) 0xFFFE0014) // (SPI) Interrupt Enable Register -#define AT91C_SPI_TDR ((AT91_REG *) 0xFFFE000C) // (SPI) Transmit Data Register -#define AT91C_SPI_MR ((AT91_REG *) 0xFFFE0004) // (SPI) Mode Register -// ========== Register definition for PDC_ADC peripheral ========== -#define AT91C_ADC_PTCR ((AT91_REG *) 0xFFFD8120) // (PDC_ADC) PDC Transfer Control Register -#define AT91C_ADC_TNPR ((AT91_REG *) 0xFFFD8118) // (PDC_ADC) Transmit Next Pointer Register -#define AT91C_ADC_RNPR ((AT91_REG *) 0xFFFD8110) // (PDC_ADC) Receive Next Pointer Register -#define AT91C_ADC_TPR ((AT91_REG *) 0xFFFD8108) // (PDC_ADC) Transmit Pointer Register -#define AT91C_ADC_RPR ((AT91_REG *) 0xFFFD8100) // (PDC_ADC) Receive Pointer Register -#define AT91C_ADC_PTSR ((AT91_REG *) 0xFFFD8124) // (PDC_ADC) PDC Transfer Status Register -#define AT91C_ADC_TNCR ((AT91_REG *) 0xFFFD811C) // (PDC_ADC) Transmit Next Counter Register -#define AT91C_ADC_RNCR ((AT91_REG *) 0xFFFD8114) // (PDC_ADC) Receive Next Counter Register -#define AT91C_ADC_TCR ((AT91_REG *) 0xFFFD810C) // (PDC_ADC) Transmit Counter Register -#define AT91C_ADC_RCR ((AT91_REG *) 0xFFFD8104) // (PDC_ADC) Receive Counter Register -// ========== Register definition for ADC peripheral ========== -#define AT91C_ADC_IMR ((AT91_REG *) 0xFFFD802C) // (ADC) ADC Interrupt Mask Register -#define AT91C_ADC_CDR4 ((AT91_REG *) 0xFFFD8040) // (ADC) ADC Channel Data Register 4 -#define AT91C_ADC_CDR2 ((AT91_REG *) 0xFFFD8038) // (ADC) ADC Channel Data Register 2 -#define AT91C_ADC_CDR0 ((AT91_REG *) 0xFFFD8030) // (ADC) ADC Channel Data Register 0 -#define AT91C_ADC_CDR7 ((AT91_REG *) 0xFFFD804C) // (ADC) ADC Channel Data Register 7 -#define AT91C_ADC_CDR1 ((AT91_REG *) 0xFFFD8034) // (ADC) ADC Channel Data Register 1 -#define AT91C_ADC_CDR3 ((AT91_REG *) 0xFFFD803C) // (ADC) ADC Channel Data Register 3 -#define AT91C_ADC_CDR5 ((AT91_REG *) 0xFFFD8044) // (ADC) ADC Channel Data Register 5 -#define AT91C_ADC_MR ((AT91_REG *) 0xFFFD8004) // (ADC) ADC Mode Register -#define AT91C_ADC_CDR6 ((AT91_REG *) 0xFFFD8048) // (ADC) ADC Channel Data Register 6 -#define AT91C_ADC_CR ((AT91_REG *) 0xFFFD8000) // (ADC) ADC Control Register -#define AT91C_ADC_CHER ((AT91_REG *) 0xFFFD8010) // (ADC) ADC Channel Enable Register -#define AT91C_ADC_CHSR ((AT91_REG *) 0xFFFD8018) // (ADC) ADC Channel Status Register -#define AT91C_ADC_IER ((AT91_REG *) 0xFFFD8024) // (ADC) ADC Interrupt Enable Register -#define AT91C_ADC_SR ((AT91_REG *) 0xFFFD801C) // (ADC) ADC Status Register -#define AT91C_ADC_CHDR ((AT91_REG *) 0xFFFD8014) // (ADC) ADC Channel Disable Register -#define AT91C_ADC_IDR ((AT91_REG *) 0xFFFD8028) // (ADC) ADC Interrupt Disable Register -#define AT91C_ADC_LCDR ((AT91_REG *) 0xFFFD8020) // (ADC) ADC Last Converted Data Register -// ========== Register definition for PDC_SSC peripheral ========== -#define AT91C_SSC_PTCR ((AT91_REG *) 0xFFFD4120) // (PDC_SSC) PDC Transfer Control Register -#define AT91C_SSC_TNPR ((AT91_REG *) 0xFFFD4118) // (PDC_SSC) Transmit Next Pointer Register -#define AT91C_SSC_RNPR ((AT91_REG *) 0xFFFD4110) // (PDC_SSC) Receive Next Pointer Register -#define AT91C_SSC_TPR ((AT91_REG *) 0xFFFD4108) // (PDC_SSC) Transmit Pointer Register -#define AT91C_SSC_RPR ((AT91_REG *) 0xFFFD4100) // (PDC_SSC) Receive Pointer Register -#define AT91C_SSC_PTSR ((AT91_REG *) 0xFFFD4124) // (PDC_SSC) PDC Transfer Status Register -#define AT91C_SSC_TNCR ((AT91_REG *) 0xFFFD411C) // (PDC_SSC) Transmit Next Counter Register -#define AT91C_SSC_RNCR ((AT91_REG *) 0xFFFD4114) // (PDC_SSC) Receive Next Counter Register -#define AT91C_SSC_TCR ((AT91_REG *) 0xFFFD410C) // (PDC_SSC) Transmit Counter Register -#define AT91C_SSC_RCR ((AT91_REG *) 0xFFFD4104) // (PDC_SSC) Receive Counter Register -// ========== Register definition for SSC peripheral ========== -#define AT91C_SSC_RFMR ((AT91_REG *) 0xFFFD4014) // (SSC) Receive Frame Mode Register -#define AT91C_SSC_CMR ((AT91_REG *) 0xFFFD4004) // (SSC) Clock Mode Register -#define AT91C_SSC_IDR ((AT91_REG *) 0xFFFD4048) // (SSC) Interrupt Disable Register -#define AT91C_SSC_SR ((AT91_REG *) 0xFFFD4040) // (SSC) Status Register -#define AT91C_SSC_RC0R ((AT91_REG *) 0xFFFD4038) // (SSC) Receive Compare 0 Register -#define AT91C_SSC_RSHR ((AT91_REG *) 0xFFFD4030) // (SSC) Receive Sync Holding Register -#define AT91C_SSC_RHR ((AT91_REG *) 0xFFFD4020) // (SSC) Receive Holding Register -#define AT91C_SSC_TCMR ((AT91_REG *) 0xFFFD4018) // (SSC) Transmit Clock Mode Register -#define AT91C_SSC_RCMR ((AT91_REG *) 0xFFFD4010) // (SSC) Receive Clock ModeRegister -#define AT91C_SSC_CR ((AT91_REG *) 0xFFFD4000) // (SSC) Control Register -#define AT91C_SSC_IMR ((AT91_REG *) 0xFFFD404C) // (SSC) Interrupt Mask Register -#define AT91C_SSC_IER ((AT91_REG *) 0xFFFD4044) // (SSC) Interrupt Enable Register -#define AT91C_SSC_RC1R ((AT91_REG *) 0xFFFD403C) // (SSC) Receive Compare 1 Register -#define AT91C_SSC_TSHR ((AT91_REG *) 0xFFFD4034) // (SSC) Transmit Sync Holding Register -#define AT91C_SSC_THR ((AT91_REG *) 0xFFFD4024) // (SSC) Transmit Holding Register -#define AT91C_SSC_TFMR ((AT91_REG *) 0xFFFD401C) // (SSC) Transmit Frame Mode Register -// ========== Register definition for PDC_US1 peripheral ========== -#define AT91C_US1_PTSR ((AT91_REG *) 0xFFFC4124) // (PDC_US1) PDC Transfer Status Register -#define AT91C_US1_TNCR ((AT91_REG *) 0xFFFC411C) // (PDC_US1) Transmit Next Counter Register -#define AT91C_US1_RNCR ((AT91_REG *) 0xFFFC4114) // (PDC_US1) Receive Next Counter Register -#define AT91C_US1_TCR ((AT91_REG *) 0xFFFC410C) // (PDC_US1) Transmit Counter Register -#define AT91C_US1_RCR ((AT91_REG *) 0xFFFC4104) // (PDC_US1) Receive Counter Register -#define AT91C_US1_PTCR ((AT91_REG *) 0xFFFC4120) // (PDC_US1) PDC Transfer Control Register -#define AT91C_US1_TNPR ((AT91_REG *) 0xFFFC4118) // (PDC_US1) Transmit Next Pointer Register -#define AT91C_US1_RNPR ((AT91_REG *) 0xFFFC4110) // (PDC_US1) Receive Next Pointer Register -#define AT91C_US1_TPR ((AT91_REG *) 0xFFFC4108) // (PDC_US1) Transmit Pointer Register -#define AT91C_US1_RPR ((AT91_REG *) 0xFFFC4100) // (PDC_US1) Receive Pointer Register -// ========== Register definition for US1 peripheral ========== -#define AT91C_US1_XXR ((AT91_REG *) 0xFFFC4048) // (US1) XON_XOFF Register -#define AT91C_US1_RHR ((AT91_REG *) 0xFFFC4018) // (US1) Receiver Holding Register -#define AT91C_US1_IMR ((AT91_REG *) 0xFFFC4010) // (US1) Interrupt Mask Register -#define AT91C_US1_IER ((AT91_REG *) 0xFFFC4008) // (US1) Interrupt Enable Register -#define AT91C_US1_CR ((AT91_REG *) 0xFFFC4000) // (US1) Control Register -#define AT91C_US1_RTOR ((AT91_REG *) 0xFFFC4024) // (US1) Receiver Time-out Register -#define AT91C_US1_THR ((AT91_REG *) 0xFFFC401C) // (US1) Transmitter Holding Register -#define AT91C_US1_CSR ((AT91_REG *) 0xFFFC4014) // (US1) Channel Status Register -#define AT91C_US1_IDR ((AT91_REG *) 0xFFFC400C) // (US1) Interrupt Disable Register -#define AT91C_US1_FIDI ((AT91_REG *) 0xFFFC4040) // (US1) FI_DI_Ratio Register -#define AT91C_US1_BRGR ((AT91_REG *) 0xFFFC4020) // (US1) Baud Rate Generator Register -#define AT91C_US1_TTGR ((AT91_REG *) 0xFFFC4028) // (US1) Transmitter Time-guard Register -#define AT91C_US1_IF ((AT91_REG *) 0xFFFC404C) // (US1) IRDA_FILTER Register -#define AT91C_US1_NER ((AT91_REG *) 0xFFFC4044) // (US1) Nb Errors Register -#define AT91C_US1_MR ((AT91_REG *) 0xFFFC4004) // (US1) Mode Register -// ========== Register definition for PDC_US0 peripheral ========== -#define AT91C_US0_PTCR ((AT91_REG *) 0xFFFC0120) // (PDC_US0) PDC Transfer Control Register -#define AT91C_US0_TNPR ((AT91_REG *) 0xFFFC0118) // (PDC_US0) Transmit Next Pointer Register -#define AT91C_US0_RNPR ((AT91_REG *) 0xFFFC0110) // (PDC_US0) Receive Next Pointer Register -#define AT91C_US0_TPR ((AT91_REG *) 0xFFFC0108) // (PDC_US0) Transmit Pointer Register -#define AT91C_US0_RPR ((AT91_REG *) 0xFFFC0100) // (PDC_US0) Receive Pointer Register -#define AT91C_US0_PTSR ((AT91_REG *) 0xFFFC0124) // (PDC_US0) PDC Transfer Status Register -#define AT91C_US0_TNCR ((AT91_REG *) 0xFFFC011C) // (PDC_US0) Transmit Next Counter Register -#define AT91C_US0_RNCR ((AT91_REG *) 0xFFFC0114) // (PDC_US0) Receive Next Counter Register -#define AT91C_US0_TCR ((AT91_REG *) 0xFFFC010C) // (PDC_US0) Transmit Counter Register -#define AT91C_US0_RCR ((AT91_REG *) 0xFFFC0104) // (PDC_US0) Receive Counter Register -// ========== Register definition for US0 peripheral ========== -#define AT91C_US0_TTGR ((AT91_REG *) 0xFFFC0028) // (US0) Transmitter Time-guard Register -#define AT91C_US0_BRGR ((AT91_REG *) 0xFFFC0020) // (US0) Baud Rate Generator Register -#define AT91C_US0_RHR ((AT91_REG *) 0xFFFC0018) // (US0) Receiver Holding Register -#define AT91C_US0_IMR ((AT91_REG *) 0xFFFC0010) // (US0) Interrupt Mask Register -#define AT91C_US0_NER ((AT91_REG *) 0xFFFC0044) // (US0) Nb Errors Register -#define AT91C_US0_RTOR ((AT91_REG *) 0xFFFC0024) // (US0) Receiver Time-out Register -#define AT91C_US0_XXR ((AT91_REG *) 0xFFFC0048) // (US0) XON_XOFF Register -#define AT91C_US0_FIDI ((AT91_REG *) 0xFFFC0040) // (US0) FI_DI_Ratio Register -#define AT91C_US0_CR ((AT91_REG *) 0xFFFC0000) // (US0) Control Register -#define AT91C_US0_IER ((AT91_REG *) 0xFFFC0008) // (US0) Interrupt Enable Register -#define AT91C_US0_IF ((AT91_REG *) 0xFFFC004C) // (US0) IRDA_FILTER Register -#define AT91C_US0_MR ((AT91_REG *) 0xFFFC0004) // (US0) Mode Register -#define AT91C_US0_IDR ((AT91_REG *) 0xFFFC000C) // (US0) Interrupt Disable Register -#define AT91C_US0_CSR ((AT91_REG *) 0xFFFC0014) // (US0) Channel Status Register -#define AT91C_US0_THR ((AT91_REG *) 0xFFFC001C) // (US0) Transmitter Holding Register -// ========== Register definition for TWI peripheral ========== -#define AT91C_TWI_RHR ((AT91_REG *) 0xFFFB8030) // (TWI) Receive Holding Register -#define AT91C_TWI_IDR ((AT91_REG *) 0xFFFB8028) // (TWI) Interrupt Disable Register -#define AT91C_TWI_SR ((AT91_REG *) 0xFFFB8020) // (TWI) Status Register -#define AT91C_TWI_CWGR ((AT91_REG *) 0xFFFB8010) // (TWI) Clock Waveform Generator Register -#define AT91C_TWI_SMR ((AT91_REG *) 0xFFFB8008) // (TWI) Slave Mode Register -#define AT91C_TWI_CR ((AT91_REG *) 0xFFFB8000) // (TWI) Control Register -#define AT91C_TWI_THR ((AT91_REG *) 0xFFFB8034) // (TWI) Transmit Holding Register -#define AT91C_TWI_IMR ((AT91_REG *) 0xFFFB802C) // (TWI) Interrupt Mask Register -#define AT91C_TWI_IER ((AT91_REG *) 0xFFFB8024) // (TWI) Interrupt Enable Register -#define AT91C_TWI_IADR ((AT91_REG *) 0xFFFB800C) // (TWI) Internal Address Register -#define AT91C_TWI_MMR ((AT91_REG *) 0xFFFB8004) // (TWI) Master Mode Register -// ========== Register definition for TC2 peripheral ========== -#define AT91C_TC2_IMR ((AT91_REG *) 0xFFFA00AC) // (TC2) Interrupt Mask Register -#define AT91C_TC2_IER ((AT91_REG *) 0xFFFA00A4) // (TC2) Interrupt Enable Register -#define AT91C_TC2_RC ((AT91_REG *) 0xFFFA009C) // (TC2) Register C -#define AT91C_TC2_RA ((AT91_REG *) 0xFFFA0094) // (TC2) Register A -#define AT91C_TC2_CMR ((AT91_REG *) 0xFFFA0084) // (TC2) Channel Mode Register (Capture Mode / Waveform Mode) -#define AT91C_TC2_IDR ((AT91_REG *) 0xFFFA00A8) // (TC2) Interrupt Disable Register -#define AT91C_TC2_SR ((AT91_REG *) 0xFFFA00A0) // (TC2) Status Register -#define AT91C_TC2_RB ((AT91_REG *) 0xFFFA0098) // (TC2) Register B -#define AT91C_TC2_CV ((AT91_REG *) 0xFFFA0090) // (TC2) Counter Value -#define AT91C_TC2_CCR ((AT91_REG *) 0xFFFA0080) // (TC2) Channel Control Register -// ========== Register definition for TC1 peripheral ========== -#define AT91C_TC1_IMR ((AT91_REG *) 0xFFFA006C) // (TC1) Interrupt Mask Register -#define AT91C_TC1_IER ((AT91_REG *) 0xFFFA0064) // (TC1) Interrupt Enable Register -#define AT91C_TC1_RC ((AT91_REG *) 0xFFFA005C) // (TC1) Register C -#define AT91C_TC1_RA ((AT91_REG *) 0xFFFA0054) // (TC1) Register A -#define AT91C_TC1_CMR ((AT91_REG *) 0xFFFA0044) // (TC1) Channel Mode Register (Capture Mode / Waveform Mode) -#define AT91C_TC1_IDR ((AT91_REG *) 0xFFFA0068) // (TC1) Interrupt Disable Register -#define AT91C_TC1_SR ((AT91_REG *) 0xFFFA0060) // (TC1) Status Register -#define AT91C_TC1_RB ((AT91_REG *) 0xFFFA0058) // (TC1) Register B -#define AT91C_TC1_CV ((AT91_REG *) 0xFFFA0050) // (TC1) Counter Value -#define AT91C_TC1_CCR ((AT91_REG *) 0xFFFA0040) // (TC1) Channel Control Register -// ========== Register definition for TC0 peripheral ========== -#define AT91C_TC0_IMR ((AT91_REG *) 0xFFFA002C) // (TC0) Interrupt Mask Register -#define AT91C_TC0_IER ((AT91_REG *) 0xFFFA0024) // (TC0) Interrupt Enable Register -#define AT91C_TC0_RC ((AT91_REG *) 0xFFFA001C) // (TC0) Register C -#define AT91C_TC0_RA ((AT91_REG *) 0xFFFA0014) // (TC0) Register A -#define AT91C_TC0_CMR ((AT91_REG *) 0xFFFA0004) // (TC0) Channel Mode Register (Capture Mode / Waveform Mode) -#define AT91C_TC0_IDR ((AT91_REG *) 0xFFFA0028) // (TC0) Interrupt Disable Register -#define AT91C_TC0_SR ((AT91_REG *) 0xFFFA0020) // (TC0) Status Register -#define AT91C_TC0_RB ((AT91_REG *) 0xFFFA0018) // (TC0) Register B -#define AT91C_TC0_CV ((AT91_REG *) 0xFFFA0010) // (TC0) Counter Value -#define AT91C_TC0_CCR ((AT91_REG *) 0xFFFA0000) // (TC0) Channel Control Register -// ========== Register definition for TCB peripheral ========== -#define AT91C_TCB_BMR ((AT91_REG *) 0xFFFA00C4) // (TCB) TC Block Mode Register -#define AT91C_TCB_BCR ((AT91_REG *) 0xFFFA00C0) // (TCB) TC Block Control Register -// ========== Register definition for PWMC_CH3 peripheral ========== -#define AT91C_CH3_CUPDR ((AT91_REG *) 0xFFFCC270) // (PWMC_CH3) Channel Update Register -#define AT91C_CH3_CPRDR ((AT91_REG *) 0xFFFCC268) // (PWMC_CH3) Channel Period Register -#define AT91C_CH3_CMR ((AT91_REG *) 0xFFFCC260) // (PWMC_CH3) Channel Mode Register -#define AT91C_CH3_Reserved ((AT91_REG *) 0xFFFCC274) // (PWMC_CH3) Reserved -#define AT91C_CH3_CCNTR ((AT91_REG *) 0xFFFCC26C) // (PWMC_CH3) Channel Counter Register -#define AT91C_CH3_CDTYR ((AT91_REG *) 0xFFFCC264) // (PWMC_CH3) Channel Duty Cycle Register -// ========== Register definition for PWMC_CH2 peripheral ========== -#define AT91C_CH2_CUPDR ((AT91_REG *) 0xFFFCC250) // (PWMC_CH2) Channel Update Register -#define AT91C_CH2_CPRDR ((AT91_REG *) 0xFFFCC248) // (PWMC_CH2) Channel Period Register -#define AT91C_CH2_CMR ((AT91_REG *) 0xFFFCC240) // (PWMC_CH2) Channel Mode Register -#define AT91C_CH2_Reserved ((AT91_REG *) 0xFFFCC254) // (PWMC_CH2) Reserved -#define AT91C_CH2_CCNTR ((AT91_REG *) 0xFFFCC24C) // (PWMC_CH2) Channel Counter Register -#define AT91C_CH2_CDTYR ((AT91_REG *) 0xFFFCC244) // (PWMC_CH2) Channel Duty Cycle Register -// ========== Register definition for PWMC_CH1 peripheral ========== -#define AT91C_CH1_CUPDR ((AT91_REG *) 0xFFFCC230) // (PWMC_CH1) Channel Update Register -#define AT91C_CH1_CPRDR ((AT91_REG *) 0xFFFCC228) // (PWMC_CH1) Channel Period Register -#define AT91C_CH1_CMR ((AT91_REG *) 0xFFFCC220) // (PWMC_CH1) Channel Mode Register -#define AT91C_CH1_Reserved ((AT91_REG *) 0xFFFCC234) // (PWMC_CH1) Reserved -#define AT91C_CH1_CCNTR ((AT91_REG *) 0xFFFCC22C) // (PWMC_CH1) Channel Counter Register -#define AT91C_CH1_CDTYR ((AT91_REG *) 0xFFFCC224) // (PWMC_CH1) Channel Duty Cycle Register -// ========== Register definition for PWMC_CH0 peripheral ========== -#define AT91C_CH0_CUPDR ((AT91_REG *) 0xFFFCC210) // (PWMC_CH0) Channel Update Register -#define AT91C_CH0_CPRDR ((AT91_REG *) 0xFFFCC208) // (PWMC_CH0) Channel Period Register -#define AT91C_CH0_CMR ((AT91_REG *) 0xFFFCC200) // (PWMC_CH0) Channel Mode Register -#define AT91C_CH0_Reserved ((AT91_REG *) 0xFFFCC214) // (PWMC_CH0) Reserved -#define AT91C_CH0_CCNTR ((AT91_REG *) 0xFFFCC20C) // (PWMC_CH0) Channel Counter Register -#define AT91C_CH0_CDTYR ((AT91_REG *) 0xFFFCC204) // (PWMC_CH0) Channel Duty Cycle Register -// ========== Register definition for PWMC peripheral ========== -#define AT91C_PWMC_VR ((AT91_REG *) 0xFFFCC0FC) // (PWMC) PWMC Version Register -#define AT91C_PWMC_ISR ((AT91_REG *) 0xFFFCC01C) // (PWMC) PWMC Interrupt Status Register -#define AT91C_PWMC_IDR ((AT91_REG *) 0xFFFCC014) // (PWMC) PWMC Interrupt Disable Register -#define AT91C_PWMC_SR ((AT91_REG *) 0xFFFCC00C) // (PWMC) PWMC Status Register -#define AT91C_PWMC_ENA ((AT91_REG *) 0xFFFCC004) // (PWMC) PWMC Enable Register -#define AT91C_PWMC_IMR ((AT91_REG *) 0xFFFCC018) // (PWMC) PWMC Interrupt Mask Register -#define AT91C_PWMC_MR ((AT91_REG *) 0xFFFCC000) // (PWMC) PWMC Mode Register -#define AT91C_PWMC_DIS ((AT91_REG *) 0xFFFCC008) // (PWMC) PWMC Disable Register -#define AT91C_PWMC_IER ((AT91_REG *) 0xFFFCC010) // (PWMC) PWMC Interrupt Enable Register -// ========== Register definition for UDP peripheral ========== -#define AT91C_UDP_ISR ((AT91_REG *) 0xFFFB001C) // (UDP) Interrupt Status Register -#define AT91C_UDP_IDR ((AT91_REG *) 0xFFFB0014) // (UDP) Interrupt Disable Register -#define AT91C_UDP_GLBSTATE ((AT91_REG *) 0xFFFB0004) // (UDP) Global State Register -#define AT91C_UDP_FDR ((AT91_REG *) 0xFFFB0050) // (UDP) Endpoint FIFO Data Register -#define AT91C_UDP_CSR ((AT91_REG *) 0xFFFB0030) // (UDP) Endpoint Control and Status Register -#define AT91C_UDP_RSTEP ((AT91_REG *) 0xFFFB0028) // (UDP) Reset Endpoint Register -#define AT91C_UDP_ICR ((AT91_REG *) 0xFFFB0020) // (UDP) Interrupt Clear Register -#define AT91C_UDP_IMR ((AT91_REG *) 0xFFFB0018) // (UDP) Interrupt Mask Register -#define AT91C_UDP_IER ((AT91_REG *) 0xFFFB0010) // (UDP) Interrupt Enable Register -#define AT91C_UDP_FADDR ((AT91_REG *) 0xFFFB0008) // (UDP) Function Address Register -#define AT91C_UDP_NUM ((AT91_REG *) 0xFFFB0000) // (UDP) Frame Number Register +/* ***************************************************************************** */ +/* REGISTER ADDRESS DEFINITION FOR AT91SAM7S64 */ +/* ***************************************************************************** */ +/* ========== Register definition for SYSC peripheral ========== */ +#define AT91C_SYSC_SYSC_VRPM ( ( AT91_REG * ) 0xFFFFFD60 ) /* (SYSC) Voltage Regulator Power Mode Register */ +/* ========== Register definition for AIC peripheral ========== */ +#define AT91C_AIC_ICCR ( ( AT91_REG * ) 0xFFFFF128 ) /* (AIC) Interrupt Clear Command Register */ +#define AT91C_AIC_IECR ( ( AT91_REG * ) 0xFFFFF120 ) /* (AIC) Interrupt Enable Command Register */ +#define AT91C_AIC_SMR ( ( AT91_REG * ) 0xFFFFF000 ) /* (AIC) Source Mode Register */ +#define AT91C_AIC_ISCR ( ( AT91_REG * ) 0xFFFFF12C ) /* (AIC) Interrupt Set Command Register */ +#define AT91C_AIC_EOICR ( ( AT91_REG * ) 0xFFFFF130 ) /* (AIC) End of Interrupt Command Register */ +#define AT91C_AIC_DCR ( ( AT91_REG * ) 0xFFFFF138 ) /* (AIC) Debug Control Register (Protect) */ +#define AT91C_AIC_FFER ( ( AT91_REG * ) 0xFFFFF140 ) /* (AIC) Fast Forcing Enable Register */ +#define AT91C_AIC_SVR ( ( AT91_REG * ) 0xFFFFF080 ) /* (AIC) Source Vector Register */ +#define AT91C_AIC_SPU ( ( AT91_REG * ) 0xFFFFF134 ) /* (AIC) Spurious Vector Register */ +#define AT91C_AIC_FFDR ( ( AT91_REG * ) 0xFFFFF144 ) /* (AIC) Fast Forcing Disable Register */ +#define AT91C_AIC_FVR ( ( AT91_REG * ) 0xFFFFF104 ) /* (AIC) FIQ Vector Register */ +#define AT91C_AIC_FFSR ( ( AT91_REG * ) 0xFFFFF148 ) /* (AIC) Fast Forcing Status Register */ +#define AT91C_AIC_IMR ( ( AT91_REG * ) 0xFFFFF110 ) /* (AIC) Interrupt Mask Register */ +#define AT91C_AIC_ISR ( ( AT91_REG * ) 0xFFFFF108 ) /* (AIC) Interrupt Status Register */ +#define AT91C_AIC_IVR ( ( AT91_REG * ) 0xFFFFF100 ) /* (AIC) IRQ Vector Register */ +#define AT91C_AIC_IDCR ( ( AT91_REG * ) 0xFFFFF124 ) /* (AIC) Interrupt Disable Command Register */ +#define AT91C_AIC_CISR ( ( AT91_REG * ) 0xFFFFF114 ) /* (AIC) Core Interrupt Status Register */ +#define AT91C_AIC_IPR ( ( AT91_REG * ) 0xFFFFF10C ) /* (AIC) Interrupt Pending Register */ +/* ========== Register definition for DBGU peripheral ========== */ +#define AT91C_DBGU_C2R ( ( AT91_REG * ) 0xFFFFF244 ) /* (DBGU) Chip ID2 Register */ +#define AT91C_DBGU_THR ( ( AT91_REG * ) 0xFFFFF21C ) /* (DBGU) Transmitter Holding Register */ +#define AT91C_DBGU_CSR ( ( AT91_REG * ) 0xFFFFF214 ) /* (DBGU) Channel Status Register */ +#define AT91C_DBGU_IDR ( ( AT91_REG * ) 0xFFFFF20C ) /* (DBGU) Interrupt Disable Register */ +#define AT91C_DBGU_MR ( ( AT91_REG * ) 0xFFFFF204 ) /* (DBGU) Mode Register */ +#define AT91C_DBGU_FNTR ( ( AT91_REG * ) 0xFFFFF248 ) /* (DBGU) Force NTRST Register */ +#define AT91C_DBGU_C1R ( ( AT91_REG * ) 0xFFFFF240 ) /* (DBGU) Chip ID1 Register */ +#define AT91C_DBGU_BRGR ( ( AT91_REG * ) 0xFFFFF220 ) /* (DBGU) Baud Rate Generator Register */ +#define AT91C_DBGU_RHR ( ( AT91_REG * ) 0xFFFFF218 ) /* (DBGU) Receiver Holding Register */ +#define AT91C_DBGU_IMR ( ( AT91_REG * ) 0xFFFFF210 ) /* (DBGU) Interrupt Mask Register */ +#define AT91C_DBGU_IER ( ( AT91_REG * ) 0xFFFFF208 ) /* (DBGU) Interrupt Enable Register */ +#define AT91C_DBGU_CR ( ( AT91_REG * ) 0xFFFFF200 ) /* (DBGU) Control Register */ +/* ========== Register definition for PDC_DBGU peripheral ========== */ +#define AT91C_DBGU_TNCR ( ( AT91_REG * ) 0xFFFFF31C ) /* (PDC_DBGU) Transmit Next Counter Register */ +#define AT91C_DBGU_RNCR ( ( AT91_REG * ) 0xFFFFF314 ) /* (PDC_DBGU) Receive Next Counter Register */ +#define AT91C_DBGU_PTCR ( ( AT91_REG * ) 0xFFFFF320 ) /* (PDC_DBGU) PDC Transfer Control Register */ +#define AT91C_DBGU_PTSR ( ( AT91_REG * ) 0xFFFFF324 ) /* (PDC_DBGU) PDC Transfer Status Register */ +#define AT91C_DBGU_RCR ( ( AT91_REG * ) 0xFFFFF304 ) /* (PDC_DBGU) Receive Counter Register */ +#define AT91C_DBGU_TCR ( ( AT91_REG * ) 0xFFFFF30C ) /* (PDC_DBGU) Transmit Counter Register */ +#define AT91C_DBGU_RPR ( ( AT91_REG * ) 0xFFFFF300 ) /* (PDC_DBGU) Receive Pointer Register */ +#define AT91C_DBGU_TPR ( ( AT91_REG * ) 0xFFFFF308 ) /* (PDC_DBGU) Transmit Pointer Register */ +#define AT91C_DBGU_RNPR ( ( AT91_REG * ) 0xFFFFF310 ) /* (PDC_DBGU) Receive Next Pointer Register */ +#define AT91C_DBGU_TNPR ( ( AT91_REG * ) 0xFFFFF318 ) /* (PDC_DBGU) Transmit Next Pointer Register */ +/* ========== Register definition for PIOA peripheral ========== */ +#define AT91C_PIOA_IMR ( ( AT91_REG * ) 0xFFFFF448 ) /* (PIOA) Interrupt Mask Register */ +#define AT91C_PIOA_IER ( ( AT91_REG * ) 0xFFFFF440 ) /* (PIOA) Interrupt Enable Register */ +#define AT91C_PIOA_OWDR ( ( AT91_REG * ) 0xFFFFF4A4 ) /* (PIOA) Output Write Disable Register */ +#define AT91C_PIOA_ISR ( ( AT91_REG * ) 0xFFFFF44C ) /* (PIOA) Interrupt Status Register */ +#define AT91C_PIOA_PPUDR ( ( AT91_REG * ) 0xFFFFF460 ) /* (PIOA) Pull-up Disable Register */ +#define AT91C_PIOA_MDSR ( ( AT91_REG * ) 0xFFFFF458 ) /* (PIOA) Multi-driver Status Register */ +#define AT91C_PIOA_MDER ( ( AT91_REG * ) 0xFFFFF450 ) /* (PIOA) Multi-driver Enable Register */ +#define AT91C_PIOA_PER ( ( AT91_REG * ) 0xFFFFF400 ) /* (PIOA) PIO Enable Register */ +#define AT91C_PIOA_PSR ( ( AT91_REG * ) 0xFFFFF408 ) /* (PIOA) PIO Status Register */ +#define AT91C_PIOA_OER ( ( AT91_REG * ) 0xFFFFF410 ) /* (PIOA) Output Enable Register */ +#define AT91C_PIOA_BSR ( ( AT91_REG * ) 0xFFFFF474 ) /* (PIOA) Select B Register */ +#define AT91C_PIOA_PPUER ( ( AT91_REG * ) 0xFFFFF464 ) /* (PIOA) Pull-up Enable Register */ +#define AT91C_PIOA_MDDR ( ( AT91_REG * ) 0xFFFFF454 ) /* (PIOA) Multi-driver Disable Register */ +#define AT91C_PIOA_PDR ( ( AT91_REG * ) 0xFFFFF404 ) /* (PIOA) PIO Disable Register */ +#define AT91C_PIOA_ODR ( ( AT91_REG * ) 0xFFFFF414 ) /* (PIOA) Output Disable Registerr */ +#define AT91C_PIOA_IFDR ( ( AT91_REG * ) 0xFFFFF424 ) /* (PIOA) Input Filter Disable Register */ +#define AT91C_PIOA_ABSR ( ( AT91_REG * ) 0xFFFFF478 ) /* (PIOA) AB Select Status Register */ +#define AT91C_PIOA_ASR ( ( AT91_REG * ) 0xFFFFF470 ) /* (PIOA) Select A Register */ +#define AT91C_PIOA_PPUSR ( ( AT91_REG * ) 0xFFFFF468 ) /* (PIOA) Pad Pull-up Status Register */ +#define AT91C_PIOA_ODSR ( ( AT91_REG * ) 0xFFFFF438 ) /* (PIOA) Output Data Status Register */ +#define AT91C_PIOA_SODR ( ( AT91_REG * ) 0xFFFFF430 ) /* (PIOA) Set Output Data Register */ +#define AT91C_PIOA_IFSR ( ( AT91_REG * ) 0xFFFFF428 ) /* (PIOA) Input Filter Status Register */ +#define AT91C_PIOA_IFER ( ( AT91_REG * ) 0xFFFFF420 ) /* (PIOA) Input Filter Enable Register */ +#define AT91C_PIOA_OSR ( ( AT91_REG * ) 0xFFFFF418 ) /* (PIOA) Output Status Register */ +#define AT91C_PIOA_IDR ( ( AT91_REG * ) 0xFFFFF444 ) /* (PIOA) Interrupt Disable Register */ +#define AT91C_PIOA_PDSR ( ( AT91_REG * ) 0xFFFFF43C ) /* (PIOA) Pin Data Status Register */ +#define AT91C_PIOA_CODR ( ( AT91_REG * ) 0xFFFFF434 ) /* (PIOA) Clear Output Data Register */ +#define AT91C_PIOA_OWSR ( ( AT91_REG * ) 0xFFFFF4A8 ) /* (PIOA) Output Write Status Register */ +#define AT91C_PIOA_OWER ( ( AT91_REG * ) 0xFFFFF4A0 ) /* (PIOA) Output Write Enable Register */ +/* ========== Register definition for CKGR peripheral ========== */ +#define AT91C_CKGR_PLLR ( ( AT91_REG * ) 0xFFFFFC2C ) /* (CKGR) PLL Register */ +#define AT91C_CKGR_MCFR ( ( AT91_REG * ) 0xFFFFFC24 ) /* (CKGR) Main Clock Frequency Register */ +#define AT91C_CKGR_MOR ( ( AT91_REG * ) 0xFFFFFC20 ) /* (CKGR) Main Oscillator Register */ +/* ========== Register definition for PMC peripheral ========== */ +#define AT91C_PMC_SCSR ( ( AT91_REG * ) 0xFFFFFC08 ) /* (PMC) System Clock Status Register */ +#define AT91C_PMC_SCER ( ( AT91_REG * ) 0xFFFFFC00 ) /* (PMC) System Clock Enable Register */ +#define AT91C_PMC_IMR ( ( AT91_REG * ) 0xFFFFFC6C ) /* (PMC) Interrupt Mask Register */ +#define AT91C_PMC_IDR ( ( AT91_REG * ) 0xFFFFFC64 ) /* (PMC) Interrupt Disable Register */ +#define AT91C_PMC_PCDR ( ( AT91_REG * ) 0xFFFFFC14 ) /* (PMC) Peripheral Clock Disable Register */ +#define AT91C_PMC_SCDR ( ( AT91_REG * ) 0xFFFFFC04 ) /* (PMC) System Clock Disable Register */ +#define AT91C_PMC_SR ( ( AT91_REG * ) 0xFFFFFC68 ) /* (PMC) Status Register */ +#define AT91C_PMC_IER ( ( AT91_REG * ) 0xFFFFFC60 ) /* (PMC) Interrupt Enable Register */ +#define AT91C_PMC_MCKR ( ( AT91_REG * ) 0xFFFFFC30 ) /* (PMC) Master Clock Register */ +#define AT91C_PMC_MOR ( ( AT91_REG * ) 0xFFFFFC20 ) /* (PMC) Main Oscillator Register */ +#define AT91C_PMC_PCER ( ( AT91_REG * ) 0xFFFFFC10 ) /* (PMC) Peripheral Clock Enable Register */ +#define AT91C_PMC_PCSR ( ( AT91_REG * ) 0xFFFFFC18 ) /* (PMC) Peripheral Clock Status Register */ +#define AT91C_PMC_PLLR ( ( AT91_REG * ) 0xFFFFFC2C ) /* (PMC) PLL Register */ +#define AT91C_PMC_MCFR ( ( AT91_REG * ) 0xFFFFFC24 ) /* (PMC) Main Clock Frequency Register */ +#define AT91C_PMC_PCKR ( ( AT91_REG * ) 0xFFFFFC40 ) /* (PMC) Programmable Clock Register */ +/* ========== Register definition for RSTC peripheral ========== */ +#define AT91C_RSTC_RSR ( ( AT91_REG * ) 0xFFFFFD04 ) /* (RSTC) Reset Status Register */ +#define AT91C_RSTC_RMR ( ( AT91_REG * ) 0xFFFFFD08 ) /* (RSTC) Reset Mode Register */ +#define AT91C_RSTC_RCR ( ( AT91_REG * ) 0xFFFFFD00 ) /* (RSTC) Reset Control Register */ +/* ========== Register definition for RTTC peripheral ========== */ +#define AT91C_RTTC_RTSR ( ( AT91_REG * ) 0xFFFFFD2C ) /* (RTTC) Real-time Status Register */ +#define AT91C_RTTC_RTAR ( ( AT91_REG * ) 0xFFFFFD24 ) /* (RTTC) Real-time Alarm Register */ +#define AT91C_RTTC_RTVR ( ( AT91_REG * ) 0xFFFFFD28 ) /* (RTTC) Real-time Value Register */ +#define AT91C_RTTC_RTMR ( ( AT91_REG * ) 0xFFFFFD20 ) /* (RTTC) Real-time Mode Register */ +/* ========== Register definition for PITC peripheral ========== */ +#define AT91C_PITC_PIIR ( ( AT91_REG * ) 0xFFFFFD3C ) /* (PITC) Period Interval Image Register */ +#define AT91C_PITC_PISR ( ( AT91_REG * ) 0xFFFFFD34 ) /* (PITC) Period Interval Status Register */ +#define AT91C_PITC_PIVR ( ( AT91_REG * ) 0xFFFFFD38 ) /* (PITC) Period Interval Value Register */ +#define AT91C_PITC_PIMR ( ( AT91_REG * ) 0xFFFFFD30 ) /* (PITC) Period Interval Mode Register */ +/* ========== Register definition for WDTC peripheral ========== */ +#define AT91C_WDTC_WDMR ( ( AT91_REG * ) 0xFFFFFD44 ) /* (WDTC) Watchdog Mode Register */ +#define AT91C_WDTC_WDSR ( ( AT91_REG * ) 0xFFFFFD48 ) /* (WDTC) Watchdog Status Register */ +#define AT91C_WDTC_WDCR ( ( AT91_REG * ) 0xFFFFFD40 ) /* (WDTC) Watchdog Control Register */ +/* ========== Register definition for MC peripheral ========== */ +#define AT91C_MC_FCR ( ( AT91_REG * ) 0xFFFFFF64 ) /* (MC) MC Flash Command Register */ +#define AT91C_MC_ASR ( ( AT91_REG * ) 0xFFFFFF04 ) /* (MC) MC Abort Status Register */ +#define AT91C_MC_FSR ( ( AT91_REG * ) 0xFFFFFF68 ) /* (MC) MC Flash Status Register */ +#define AT91C_MC_FMR ( ( AT91_REG * ) 0xFFFFFF60 ) /* (MC) MC Flash Mode Register */ +#define AT91C_MC_AASR ( ( AT91_REG * ) 0xFFFFFF08 ) /* (MC) MC Abort Address Status Register */ +#define AT91C_MC_RCR ( ( AT91_REG * ) 0xFFFFFF00 ) /* (MC) MC Remap Control Register */ +/* ========== Register definition for PDC_SPI peripheral ========== */ +#define AT91C_SPI_PTCR ( ( AT91_REG * ) 0xFFFE0120 ) /* (PDC_SPI) PDC Transfer Control Register */ +#define AT91C_SPI_TNPR ( ( AT91_REG * ) 0xFFFE0118 ) /* (PDC_SPI) Transmit Next Pointer Register */ +#define AT91C_SPI_RNPR ( ( AT91_REG * ) 0xFFFE0110 ) /* (PDC_SPI) Receive Next Pointer Register */ +#define AT91C_SPI_TPR ( ( AT91_REG * ) 0xFFFE0108 ) /* (PDC_SPI) Transmit Pointer Register */ +#define AT91C_SPI_RPR ( ( AT91_REG * ) 0xFFFE0100 ) /* (PDC_SPI) Receive Pointer Register */ +#define AT91C_SPI_PTSR ( ( AT91_REG * ) 0xFFFE0124 ) /* (PDC_SPI) PDC Transfer Status Register */ +#define AT91C_SPI_TNCR ( ( AT91_REG * ) 0xFFFE011C ) /* (PDC_SPI) Transmit Next Counter Register */ +#define AT91C_SPI_RNCR ( ( AT91_REG * ) 0xFFFE0114 ) /* (PDC_SPI) Receive Next Counter Register */ +#define AT91C_SPI_TCR ( ( AT91_REG * ) 0xFFFE010C ) /* (PDC_SPI) Transmit Counter Register */ +#define AT91C_SPI_RCR ( ( AT91_REG * ) 0xFFFE0104 ) /* (PDC_SPI) Receive Counter Register */ +/* ========== Register definition for SPI peripheral ========== */ +#define AT91C_SPI_CSR ( ( AT91_REG * ) 0xFFFE0030 ) /* (SPI) Chip Select Register */ +#define AT91C_SPI_IDR ( ( AT91_REG * ) 0xFFFE0018 ) /* (SPI) Interrupt Disable Register */ +#define AT91C_SPI_SR ( ( AT91_REG * ) 0xFFFE0010 ) /* (SPI) Status Register */ +#define AT91C_SPI_RDR ( ( AT91_REG * ) 0xFFFE0008 ) /* (SPI) Receive Data Register */ +#define AT91C_SPI_CR ( ( AT91_REG * ) 0xFFFE0000 ) /* (SPI) Control Register */ +#define AT91C_SPI_IMR ( ( AT91_REG * ) 0xFFFE001C ) /* (SPI) Interrupt Mask Register */ +#define AT91C_SPI_IER ( ( AT91_REG * ) 0xFFFE0014 ) /* (SPI) Interrupt Enable Register */ +#define AT91C_SPI_TDR ( ( AT91_REG * ) 0xFFFE000C ) /* (SPI) Transmit Data Register */ +#define AT91C_SPI_MR ( ( AT91_REG * ) 0xFFFE0004 ) /* (SPI) Mode Register */ +/* ========== Register definition for PDC_ADC peripheral ========== */ +#define AT91C_ADC_PTCR ( ( AT91_REG * ) 0xFFFD8120 ) /* (PDC_ADC) PDC Transfer Control Register */ +#define AT91C_ADC_TNPR ( ( AT91_REG * ) 0xFFFD8118 ) /* (PDC_ADC) Transmit Next Pointer Register */ +#define AT91C_ADC_RNPR ( ( AT91_REG * ) 0xFFFD8110 ) /* (PDC_ADC) Receive Next Pointer Register */ +#define AT91C_ADC_TPR ( ( AT91_REG * ) 0xFFFD8108 ) /* (PDC_ADC) Transmit Pointer Register */ +#define AT91C_ADC_RPR ( ( AT91_REG * ) 0xFFFD8100 ) /* (PDC_ADC) Receive Pointer Register */ +#define AT91C_ADC_PTSR ( ( AT91_REG * ) 0xFFFD8124 ) /* (PDC_ADC) PDC Transfer Status Register */ +#define AT91C_ADC_TNCR ( ( AT91_REG * ) 0xFFFD811C ) /* (PDC_ADC) Transmit Next Counter Register */ +#define AT91C_ADC_RNCR ( ( AT91_REG * ) 0xFFFD8114 ) /* (PDC_ADC) Receive Next Counter Register */ +#define AT91C_ADC_TCR ( ( AT91_REG * ) 0xFFFD810C ) /* (PDC_ADC) Transmit Counter Register */ +#define AT91C_ADC_RCR ( ( AT91_REG * ) 0xFFFD8104 ) /* (PDC_ADC) Receive Counter Register */ +/* ========== Register definition for ADC peripheral ========== */ +#define AT91C_ADC_IMR ( ( AT91_REG * ) 0xFFFD802C ) /* (ADC) ADC Interrupt Mask Register */ +#define AT91C_ADC_CDR4 ( ( AT91_REG * ) 0xFFFD8040 ) /* (ADC) ADC Channel Data Register 4 */ +#define AT91C_ADC_CDR2 ( ( AT91_REG * ) 0xFFFD8038 ) /* (ADC) ADC Channel Data Register 2 */ +#define AT91C_ADC_CDR0 ( ( AT91_REG * ) 0xFFFD8030 ) /* (ADC) ADC Channel Data Register 0 */ +#define AT91C_ADC_CDR7 ( ( AT91_REG * ) 0xFFFD804C ) /* (ADC) ADC Channel Data Register 7 */ +#define AT91C_ADC_CDR1 ( ( AT91_REG * ) 0xFFFD8034 ) /* (ADC) ADC Channel Data Register 1 */ +#define AT91C_ADC_CDR3 ( ( AT91_REG * ) 0xFFFD803C ) /* (ADC) ADC Channel Data Register 3 */ +#define AT91C_ADC_CDR5 ( ( AT91_REG * ) 0xFFFD8044 ) /* (ADC) ADC Channel Data Register 5 */ +#define AT91C_ADC_MR ( ( AT91_REG * ) 0xFFFD8004 ) /* (ADC) ADC Mode Register */ +#define AT91C_ADC_CDR6 ( ( AT91_REG * ) 0xFFFD8048 ) /* (ADC) ADC Channel Data Register 6 */ +#define AT91C_ADC_CR ( ( AT91_REG * ) 0xFFFD8000 ) /* (ADC) ADC Control Register */ +#define AT91C_ADC_CHER ( ( AT91_REG * ) 0xFFFD8010 ) /* (ADC) ADC Channel Enable Register */ +#define AT91C_ADC_CHSR ( ( AT91_REG * ) 0xFFFD8018 ) /* (ADC) ADC Channel Status Register */ +#define AT91C_ADC_IER ( ( AT91_REG * ) 0xFFFD8024 ) /* (ADC) ADC Interrupt Enable Register */ +#define AT91C_ADC_SR ( ( AT91_REG * ) 0xFFFD801C ) /* (ADC) ADC Status Register */ +#define AT91C_ADC_CHDR ( ( AT91_REG * ) 0xFFFD8014 ) /* (ADC) ADC Channel Disable Register */ +#define AT91C_ADC_IDR ( ( AT91_REG * ) 0xFFFD8028 ) /* (ADC) ADC Interrupt Disable Register */ +#define AT91C_ADC_LCDR ( ( AT91_REG * ) 0xFFFD8020 ) /* (ADC) ADC Last Converted Data Register */ +/* ========== Register definition for PDC_SSC peripheral ========== */ +#define AT91C_SSC_PTCR ( ( AT91_REG * ) 0xFFFD4120 ) /* (PDC_SSC) PDC Transfer Control Register */ +#define AT91C_SSC_TNPR ( ( AT91_REG * ) 0xFFFD4118 ) /* (PDC_SSC) Transmit Next Pointer Register */ +#define AT91C_SSC_RNPR ( ( AT91_REG * ) 0xFFFD4110 ) /* (PDC_SSC) Receive Next Pointer Register */ +#define AT91C_SSC_TPR ( ( AT91_REG * ) 0xFFFD4108 ) /* (PDC_SSC) Transmit Pointer Register */ +#define AT91C_SSC_RPR ( ( AT91_REG * ) 0xFFFD4100 ) /* (PDC_SSC) Receive Pointer Register */ +#define AT91C_SSC_PTSR ( ( AT91_REG * ) 0xFFFD4124 ) /* (PDC_SSC) PDC Transfer Status Register */ +#define AT91C_SSC_TNCR ( ( AT91_REG * ) 0xFFFD411C ) /* (PDC_SSC) Transmit Next Counter Register */ +#define AT91C_SSC_RNCR ( ( AT91_REG * ) 0xFFFD4114 ) /* (PDC_SSC) Receive Next Counter Register */ +#define AT91C_SSC_TCR ( ( AT91_REG * ) 0xFFFD410C ) /* (PDC_SSC) Transmit Counter Register */ +#define AT91C_SSC_RCR ( ( AT91_REG * ) 0xFFFD4104 ) /* (PDC_SSC) Receive Counter Register */ +/* ========== Register definition for SSC peripheral ========== */ +#define AT91C_SSC_RFMR ( ( AT91_REG * ) 0xFFFD4014 ) /* (SSC) Receive Frame Mode Register */ +#define AT91C_SSC_CMR ( ( AT91_REG * ) 0xFFFD4004 ) /* (SSC) Clock Mode Register */ +#define AT91C_SSC_IDR ( ( AT91_REG * ) 0xFFFD4048 ) /* (SSC) Interrupt Disable Register */ +#define AT91C_SSC_SR ( ( AT91_REG * ) 0xFFFD4040 ) /* (SSC) Status Register */ +#define AT91C_SSC_RC0R ( ( AT91_REG * ) 0xFFFD4038 ) /* (SSC) Receive Compare 0 Register */ +#define AT91C_SSC_RSHR ( ( AT91_REG * ) 0xFFFD4030 ) /* (SSC) Receive Sync Holding Register */ +#define AT91C_SSC_RHR ( ( AT91_REG * ) 0xFFFD4020 ) /* (SSC) Receive Holding Register */ +#define AT91C_SSC_TCMR ( ( AT91_REG * ) 0xFFFD4018 ) /* (SSC) Transmit Clock Mode Register */ +#define AT91C_SSC_RCMR ( ( AT91_REG * ) 0xFFFD4010 ) /* (SSC) Receive Clock ModeRegister */ +#define AT91C_SSC_CR ( ( AT91_REG * ) 0xFFFD4000 ) /* (SSC) Control Register */ +#define AT91C_SSC_IMR ( ( AT91_REG * ) 0xFFFD404C ) /* (SSC) Interrupt Mask Register */ +#define AT91C_SSC_IER ( ( AT91_REG * ) 0xFFFD4044 ) /* (SSC) Interrupt Enable Register */ +#define AT91C_SSC_RC1R ( ( AT91_REG * ) 0xFFFD403C ) /* (SSC) Receive Compare 1 Register */ +#define AT91C_SSC_TSHR ( ( AT91_REG * ) 0xFFFD4034 ) /* (SSC) Transmit Sync Holding Register */ +#define AT91C_SSC_THR ( ( AT91_REG * ) 0xFFFD4024 ) /* (SSC) Transmit Holding Register */ +#define AT91C_SSC_TFMR ( ( AT91_REG * ) 0xFFFD401C ) /* (SSC) Transmit Frame Mode Register */ +/* ========== Register definition for PDC_US1 peripheral ========== */ +#define AT91C_US1_PTSR ( ( AT91_REG * ) 0xFFFC4124 ) /* (PDC_US1) PDC Transfer Status Register */ +#define AT91C_US1_TNCR ( ( AT91_REG * ) 0xFFFC411C ) /* (PDC_US1) Transmit Next Counter Register */ +#define AT91C_US1_RNCR ( ( AT91_REG * ) 0xFFFC4114 ) /* (PDC_US1) Receive Next Counter Register */ +#define AT91C_US1_TCR ( ( AT91_REG * ) 0xFFFC410C ) /* (PDC_US1) Transmit Counter Register */ +#define AT91C_US1_RCR ( ( AT91_REG * ) 0xFFFC4104 ) /* (PDC_US1) Receive Counter Register */ +#define AT91C_US1_PTCR ( ( AT91_REG * ) 0xFFFC4120 ) /* (PDC_US1) PDC Transfer Control Register */ +#define AT91C_US1_TNPR ( ( AT91_REG * ) 0xFFFC4118 ) /* (PDC_US1) Transmit Next Pointer Register */ +#define AT91C_US1_RNPR ( ( AT91_REG * ) 0xFFFC4110 ) /* (PDC_US1) Receive Next Pointer Register */ +#define AT91C_US1_TPR ( ( AT91_REG * ) 0xFFFC4108 ) /* (PDC_US1) Transmit Pointer Register */ +#define AT91C_US1_RPR ( ( AT91_REG * ) 0xFFFC4100 ) /* (PDC_US1) Receive Pointer Register */ +/* ========== Register definition for US1 peripheral ========== */ +#define AT91C_US1_XXR ( ( AT91_REG * ) 0xFFFC4048 ) /* (US1) XON_XOFF Register */ +#define AT91C_US1_RHR ( ( AT91_REG * ) 0xFFFC4018 ) /* (US1) Receiver Holding Register */ +#define AT91C_US1_IMR ( ( AT91_REG * ) 0xFFFC4010 ) /* (US1) Interrupt Mask Register */ +#define AT91C_US1_IER ( ( AT91_REG * ) 0xFFFC4008 ) /* (US1) Interrupt Enable Register */ +#define AT91C_US1_CR ( ( AT91_REG * ) 0xFFFC4000 ) /* (US1) Control Register */ +#define AT91C_US1_RTOR ( ( AT91_REG * ) 0xFFFC4024 ) /* (US1) Receiver Time-out Register */ +#define AT91C_US1_THR ( ( AT91_REG * ) 0xFFFC401C ) /* (US1) Transmitter Holding Register */ +#define AT91C_US1_CSR ( ( AT91_REG * ) 0xFFFC4014 ) /* (US1) Channel Status Register */ +#define AT91C_US1_IDR ( ( AT91_REG * ) 0xFFFC400C ) /* (US1) Interrupt Disable Register */ +#define AT91C_US1_FIDI ( ( AT91_REG * ) 0xFFFC4040 ) /* (US1) FI_DI_Ratio Register */ +#define AT91C_US1_BRGR ( ( AT91_REG * ) 0xFFFC4020 ) /* (US1) Baud Rate Generator Register */ +#define AT91C_US1_TTGR ( ( AT91_REG * ) 0xFFFC4028 ) /* (US1) Transmitter Time-guard Register */ +#define AT91C_US1_IF ( ( AT91_REG * ) 0xFFFC404C ) /* (US1) IRDA_FILTER Register */ +#define AT91C_US1_NER ( ( AT91_REG * ) 0xFFFC4044 ) /* (US1) Nb Errors Register */ +#define AT91C_US1_MR ( ( AT91_REG * ) 0xFFFC4004 ) /* (US1) Mode Register */ +/* ========== Register definition for PDC_US0 peripheral ========== */ +#define AT91C_US0_PTCR ( ( AT91_REG * ) 0xFFFC0120 ) /* (PDC_US0) PDC Transfer Control Register */ +#define AT91C_US0_TNPR ( ( AT91_REG * ) 0xFFFC0118 ) /* (PDC_US0) Transmit Next Pointer Register */ +#define AT91C_US0_RNPR ( ( AT91_REG * ) 0xFFFC0110 ) /* (PDC_US0) Receive Next Pointer Register */ +#define AT91C_US0_TPR ( ( AT91_REG * ) 0xFFFC0108 ) /* (PDC_US0) Transmit Pointer Register */ +#define AT91C_US0_RPR ( ( AT91_REG * ) 0xFFFC0100 ) /* (PDC_US0) Receive Pointer Register */ +#define AT91C_US0_PTSR ( ( AT91_REG * ) 0xFFFC0124 ) /* (PDC_US0) PDC Transfer Status Register */ +#define AT91C_US0_TNCR ( ( AT91_REG * ) 0xFFFC011C ) /* (PDC_US0) Transmit Next Counter Register */ +#define AT91C_US0_RNCR ( ( AT91_REG * ) 0xFFFC0114 ) /* (PDC_US0) Receive Next Counter Register */ +#define AT91C_US0_TCR ( ( AT91_REG * ) 0xFFFC010C ) /* (PDC_US0) Transmit Counter Register */ +#define AT91C_US0_RCR ( ( AT91_REG * ) 0xFFFC0104 ) /* (PDC_US0) Receive Counter Register */ +/* ========== Register definition for US0 peripheral ========== */ +#define AT91C_US0_TTGR ( ( AT91_REG * ) 0xFFFC0028 ) /* (US0) Transmitter Time-guard Register */ +#define AT91C_US0_BRGR ( ( AT91_REG * ) 0xFFFC0020 ) /* (US0) Baud Rate Generator Register */ +#define AT91C_US0_RHR ( ( AT91_REG * ) 0xFFFC0018 ) /* (US0) Receiver Holding Register */ +#define AT91C_US0_IMR ( ( AT91_REG * ) 0xFFFC0010 ) /* (US0) Interrupt Mask Register */ +#define AT91C_US0_NER ( ( AT91_REG * ) 0xFFFC0044 ) /* (US0) Nb Errors Register */ +#define AT91C_US0_RTOR ( ( AT91_REG * ) 0xFFFC0024 ) /* (US0) Receiver Time-out Register */ +#define AT91C_US0_XXR ( ( AT91_REG * ) 0xFFFC0048 ) /* (US0) XON_XOFF Register */ +#define AT91C_US0_FIDI ( ( AT91_REG * ) 0xFFFC0040 ) /* (US0) FI_DI_Ratio Register */ +#define AT91C_US0_CR ( ( AT91_REG * ) 0xFFFC0000 ) /* (US0) Control Register */ +#define AT91C_US0_IER ( ( AT91_REG * ) 0xFFFC0008 ) /* (US0) Interrupt Enable Register */ +#define AT91C_US0_IF ( ( AT91_REG * ) 0xFFFC004C ) /* (US0) IRDA_FILTER Register */ +#define AT91C_US0_MR ( ( AT91_REG * ) 0xFFFC0004 ) /* (US0) Mode Register */ +#define AT91C_US0_IDR ( ( AT91_REG * ) 0xFFFC000C ) /* (US0) Interrupt Disable Register */ +#define AT91C_US0_CSR ( ( AT91_REG * ) 0xFFFC0014 ) /* (US0) Channel Status Register */ +#define AT91C_US0_THR ( ( AT91_REG * ) 0xFFFC001C ) /* (US0) Transmitter Holding Register */ +/* ========== Register definition for TWI peripheral ========== */ +#define AT91C_TWI_RHR ( ( AT91_REG * ) 0xFFFB8030 ) /* (TWI) Receive Holding Register */ +#define AT91C_TWI_IDR ( ( AT91_REG * ) 0xFFFB8028 ) /* (TWI) Interrupt Disable Register */ +#define AT91C_TWI_SR ( ( AT91_REG * ) 0xFFFB8020 ) /* (TWI) Status Register */ +#define AT91C_TWI_CWGR ( ( AT91_REG * ) 0xFFFB8010 ) /* (TWI) Clock Waveform Generator Register */ +#define AT91C_TWI_SMR ( ( AT91_REG * ) 0xFFFB8008 ) /* (TWI) Slave Mode Register */ +#define AT91C_TWI_CR ( ( AT91_REG * ) 0xFFFB8000 ) /* (TWI) Control Register */ +#define AT91C_TWI_THR ( ( AT91_REG * ) 0xFFFB8034 ) /* (TWI) Transmit Holding Register */ +#define AT91C_TWI_IMR ( ( AT91_REG * ) 0xFFFB802C ) /* (TWI) Interrupt Mask Register */ +#define AT91C_TWI_IER ( ( AT91_REG * ) 0xFFFB8024 ) /* (TWI) Interrupt Enable Register */ +#define AT91C_TWI_IADR ( ( AT91_REG * ) 0xFFFB800C ) /* (TWI) Internal Address Register */ +#define AT91C_TWI_MMR ( ( AT91_REG * ) 0xFFFB8004 ) /* (TWI) Master Mode Register */ +/* ========== Register definition for TC2 peripheral ========== */ +#define AT91C_TC2_IMR ( ( AT91_REG * ) 0xFFFA00AC ) /* (TC2) Interrupt Mask Register */ +#define AT91C_TC2_IER ( ( AT91_REG * ) 0xFFFA00A4 ) /* (TC2) Interrupt Enable Register */ +#define AT91C_TC2_RC ( ( AT91_REG * ) 0xFFFA009C ) /* (TC2) Register C */ +#define AT91C_TC2_RA ( ( AT91_REG * ) 0xFFFA0094 ) /* (TC2) Register A */ +#define AT91C_TC2_CMR ( ( AT91_REG * ) 0xFFFA0084 ) /* (TC2) Channel Mode Register (Capture Mode / Waveform Mode) */ +#define AT91C_TC2_IDR ( ( AT91_REG * ) 0xFFFA00A8 ) /* (TC2) Interrupt Disable Register */ +#define AT91C_TC2_SR ( ( AT91_REG * ) 0xFFFA00A0 ) /* (TC2) Status Register */ +#define AT91C_TC2_RB ( ( AT91_REG * ) 0xFFFA0098 ) /* (TC2) Register B */ +#define AT91C_TC2_CV ( ( AT91_REG * ) 0xFFFA0090 ) /* (TC2) Counter Value */ +#define AT91C_TC2_CCR ( ( AT91_REG * ) 0xFFFA0080 ) /* (TC2) Channel Control Register */ +/* ========== Register definition for TC1 peripheral ========== */ +#define AT91C_TC1_IMR ( ( AT91_REG * ) 0xFFFA006C ) /* (TC1) Interrupt Mask Register */ +#define AT91C_TC1_IER ( ( AT91_REG * ) 0xFFFA0064 ) /* (TC1) Interrupt Enable Register */ +#define AT91C_TC1_RC ( ( AT91_REG * ) 0xFFFA005C ) /* (TC1) Register C */ +#define AT91C_TC1_RA ( ( AT91_REG * ) 0xFFFA0054 ) /* (TC1) Register A */ +#define AT91C_TC1_CMR ( ( AT91_REG * ) 0xFFFA0044 ) /* (TC1) Channel Mode Register (Capture Mode / Waveform Mode) */ +#define AT91C_TC1_IDR ( ( AT91_REG * ) 0xFFFA0068 ) /* (TC1) Interrupt Disable Register */ +#define AT91C_TC1_SR ( ( AT91_REG * ) 0xFFFA0060 ) /* (TC1) Status Register */ +#define AT91C_TC1_RB ( ( AT91_REG * ) 0xFFFA0058 ) /* (TC1) Register B */ +#define AT91C_TC1_CV ( ( AT91_REG * ) 0xFFFA0050 ) /* (TC1) Counter Value */ +#define AT91C_TC1_CCR ( ( AT91_REG * ) 0xFFFA0040 ) /* (TC1) Channel Control Register */ +/* ========== Register definition for TC0 peripheral ========== */ +#define AT91C_TC0_IMR ( ( AT91_REG * ) 0xFFFA002C ) /* (TC0) Interrupt Mask Register */ +#define AT91C_TC0_IER ( ( AT91_REG * ) 0xFFFA0024 ) /* (TC0) Interrupt Enable Register */ +#define AT91C_TC0_RC ( ( AT91_REG * ) 0xFFFA001C ) /* (TC0) Register C */ +#define AT91C_TC0_RA ( ( AT91_REG * ) 0xFFFA0014 ) /* (TC0) Register A */ +#define AT91C_TC0_CMR ( ( AT91_REG * ) 0xFFFA0004 ) /* (TC0) Channel Mode Register (Capture Mode / Waveform Mode) */ +#define AT91C_TC0_IDR ( ( AT91_REG * ) 0xFFFA0028 ) /* (TC0) Interrupt Disable Register */ +#define AT91C_TC0_SR ( ( AT91_REG * ) 0xFFFA0020 ) /* (TC0) Status Register */ +#define AT91C_TC0_RB ( ( AT91_REG * ) 0xFFFA0018 ) /* (TC0) Register B */ +#define AT91C_TC0_CV ( ( AT91_REG * ) 0xFFFA0010 ) /* (TC0) Counter Value */ +#define AT91C_TC0_CCR ( ( AT91_REG * ) 0xFFFA0000 ) /* (TC0) Channel Control Register */ +/* ========== Register definition for TCB peripheral ========== */ +#define AT91C_TCB_BMR ( ( AT91_REG * ) 0xFFFA00C4 ) /* (TCB) TC Block Mode Register */ +#define AT91C_TCB_BCR ( ( AT91_REG * ) 0xFFFA00C0 ) /* (TCB) TC Block Control Register */ +/* ========== Register definition for PWMC_CH3 peripheral ========== */ +#define AT91C_CH3_CUPDR ( ( AT91_REG * ) 0xFFFCC270 ) /* (PWMC_CH3) Channel Update Register */ +#define AT91C_CH3_CPRDR ( ( AT91_REG * ) 0xFFFCC268 ) /* (PWMC_CH3) Channel Period Register */ +#define AT91C_CH3_CMR ( ( AT91_REG * ) 0xFFFCC260 ) /* (PWMC_CH3) Channel Mode Register */ +#define AT91C_CH3_Reserved ( ( AT91_REG * ) 0xFFFCC274 ) /* (PWMC_CH3) Reserved */ +#define AT91C_CH3_CCNTR ( ( AT91_REG * ) 0xFFFCC26C ) /* (PWMC_CH3) Channel Counter Register */ +#define AT91C_CH3_CDTYR ( ( AT91_REG * ) 0xFFFCC264 ) /* (PWMC_CH3) Channel Duty Cycle Register */ +/* ========== Register definition for PWMC_CH2 peripheral ========== */ +#define AT91C_CH2_CUPDR ( ( AT91_REG * ) 0xFFFCC250 ) /* (PWMC_CH2) Channel Update Register */ +#define AT91C_CH2_CPRDR ( ( AT91_REG * ) 0xFFFCC248 ) /* (PWMC_CH2) Channel Period Register */ +#define AT91C_CH2_CMR ( ( AT91_REG * ) 0xFFFCC240 ) /* (PWMC_CH2) Channel Mode Register */ +#define AT91C_CH2_Reserved ( ( AT91_REG * ) 0xFFFCC254 ) /* (PWMC_CH2) Reserved */ +#define AT91C_CH2_CCNTR ( ( AT91_REG * ) 0xFFFCC24C ) /* (PWMC_CH2) Channel Counter Register */ +#define AT91C_CH2_CDTYR ( ( AT91_REG * ) 0xFFFCC244 ) /* (PWMC_CH2) Channel Duty Cycle Register */ +/* ========== Register definition for PWMC_CH1 peripheral ========== */ +#define AT91C_CH1_CUPDR ( ( AT91_REG * ) 0xFFFCC230 ) /* (PWMC_CH1) Channel Update Register */ +#define AT91C_CH1_CPRDR ( ( AT91_REG * ) 0xFFFCC228 ) /* (PWMC_CH1) Channel Period Register */ +#define AT91C_CH1_CMR ( ( AT91_REG * ) 0xFFFCC220 ) /* (PWMC_CH1) Channel Mode Register */ +#define AT91C_CH1_Reserved ( ( AT91_REG * ) 0xFFFCC234 ) /* (PWMC_CH1) Reserved */ +#define AT91C_CH1_CCNTR ( ( AT91_REG * ) 0xFFFCC22C ) /* (PWMC_CH1) Channel Counter Register */ +#define AT91C_CH1_CDTYR ( ( AT91_REG * ) 0xFFFCC224 ) /* (PWMC_CH1) Channel Duty Cycle Register */ +/* ========== Register definition for PWMC_CH0 peripheral ========== */ +#define AT91C_CH0_CUPDR ( ( AT91_REG * ) 0xFFFCC210 ) /* (PWMC_CH0) Channel Update Register */ +#define AT91C_CH0_CPRDR ( ( AT91_REG * ) 0xFFFCC208 ) /* (PWMC_CH0) Channel Period Register */ +#define AT91C_CH0_CMR ( ( AT91_REG * ) 0xFFFCC200 ) /* (PWMC_CH0) Channel Mode Register */ +#define AT91C_CH0_Reserved ( ( AT91_REG * ) 0xFFFCC214 ) /* (PWMC_CH0) Reserved */ +#define AT91C_CH0_CCNTR ( ( AT91_REG * ) 0xFFFCC20C ) /* (PWMC_CH0) Channel Counter Register */ +#define AT91C_CH0_CDTYR ( ( AT91_REG * ) 0xFFFCC204 ) /* (PWMC_CH0) Channel Duty Cycle Register */ +/* ========== Register definition for PWMC peripheral ========== */ +#define AT91C_PWMC_VR ( ( AT91_REG * ) 0xFFFCC0FC ) /* (PWMC) PWMC Version Register */ +#define AT91C_PWMC_ISR ( ( AT91_REG * ) 0xFFFCC01C ) /* (PWMC) PWMC Interrupt Status Register */ +#define AT91C_PWMC_IDR ( ( AT91_REG * ) 0xFFFCC014 ) /* (PWMC) PWMC Interrupt Disable Register */ +#define AT91C_PWMC_SR ( ( AT91_REG * ) 0xFFFCC00C ) /* (PWMC) PWMC Status Register */ +#define AT91C_PWMC_ENA ( ( AT91_REG * ) 0xFFFCC004 ) /* (PWMC) PWMC Enable Register */ +#define AT91C_PWMC_IMR ( ( AT91_REG * ) 0xFFFCC018 ) /* (PWMC) PWMC Interrupt Mask Register */ +#define AT91C_PWMC_MR ( ( AT91_REG * ) 0xFFFCC000 ) /* (PWMC) PWMC Mode Register */ +#define AT91C_PWMC_DIS ( ( AT91_REG * ) 0xFFFCC008 ) /* (PWMC) PWMC Disable Register */ +#define AT91C_PWMC_IER ( ( AT91_REG * ) 0xFFFCC010 ) /* (PWMC) PWMC Interrupt Enable Register */ +/* ========== Register definition for UDP peripheral ========== */ +#define AT91C_UDP_ISR ( ( AT91_REG * ) 0xFFFB001C ) /* (UDP) Interrupt Status Register */ +#define AT91C_UDP_IDR ( ( AT91_REG * ) 0xFFFB0014 ) /* (UDP) Interrupt Disable Register */ +#define AT91C_UDP_GLBSTATE ( ( AT91_REG * ) 0xFFFB0004 ) /* (UDP) Global State Register */ +#define AT91C_UDP_FDR ( ( AT91_REG * ) 0xFFFB0050 ) /* (UDP) Endpoint FIFO Data Register */ +#define AT91C_UDP_CSR ( ( AT91_REG * ) 0xFFFB0030 ) /* (UDP) Endpoint Control and Status Register */ +#define AT91C_UDP_RSTEP ( ( AT91_REG * ) 0xFFFB0028 ) /* (UDP) Reset Endpoint Register */ +#define AT91C_UDP_ICR ( ( AT91_REG * ) 0xFFFB0020 ) /* (UDP) Interrupt Clear Register */ +#define AT91C_UDP_IMR ( ( AT91_REG * ) 0xFFFB0018 ) /* (UDP) Interrupt Mask Register */ +#define AT91C_UDP_IER ( ( AT91_REG * ) 0xFFFB0010 ) /* (UDP) Interrupt Enable Register */ +#define AT91C_UDP_FADDR ( ( AT91_REG * ) 0xFFFB0008 ) /* (UDP) Function Address Register */ +#define AT91C_UDP_NUM ( ( AT91_REG * ) 0xFFFB0000 ) /* (UDP) Frame Number Register */ -// ***************************************************************************** -// PIO DEFINITIONS FOR AT91SAM7S64 -// ***************************************************************************** -#define AT91C_PIO_PA0 ((unsigned int) 1 << 0) // Pin Controlled by PA0 -#define AT91C_PA0_PWM0 ((unsigned int) AT91C_PIO_PA0) // PWM Channel 0 -#define AT91C_PA0_TIOA0 ((unsigned int) AT91C_PIO_PA0) // Timer Counter 0 Multipurpose Timer I/O Pin A -#define AT91C_PIO_PA1 ((unsigned int) 1 << 1) // Pin Controlled by PA1 -#define AT91C_PA1_PWM1 ((unsigned int) AT91C_PIO_PA1) // PWM Channel 1 -#define AT91C_PA1_TIOB0 ((unsigned int) AT91C_PIO_PA1) // Timer Counter 0 Multipurpose Timer I/O Pin B -#define AT91C_PIO_PA10 ((unsigned int) 1 << 10) // Pin Controlled by PA10 -#define AT91C_PA10_DTXD ((unsigned int) AT91C_PIO_PA10) // DBGU Debug Transmit Data -#define AT91C_PA10_NPCS2 ((unsigned int) AT91C_PIO_PA10) // SPI Peripheral Chip Select 2 -#define AT91C_PIO_PA11 ((unsigned int) 1 << 11) // Pin Controlled by PA11 -#define AT91C_PA11_NPCS0 ((unsigned int) AT91C_PIO_PA11) // SPI Peripheral Chip Select 0 -#define AT91C_PA11_PWM0 ((unsigned int) AT91C_PIO_PA11) // PWM Channel 0 -#define AT91C_PIO_PA12 ((unsigned int) 1 << 12) // Pin Controlled by PA12 -#define AT91C_PA12_MISO ((unsigned int) AT91C_PIO_PA12) // SPI Master In Slave -#define AT91C_PA12_PWM1 ((unsigned int) AT91C_PIO_PA12) // PWM Channel 1 -#define AT91C_PIO_PA13 ((unsigned int) 1 << 13) // Pin Controlled by PA13 -#define AT91C_PA13_MOSI ((unsigned int) AT91C_PIO_PA13) // SPI Master Out Slave -#define AT91C_PA13_PWM2 ((unsigned int) AT91C_PIO_PA13) // PWM Channel 2 -#define AT91C_PIO_PA14 ((unsigned int) 1 << 14) // Pin Controlled by PA14 -#define AT91C_PA14_SPCK ((unsigned int) AT91C_PIO_PA14) // SPI Serial Clock -#define AT91C_PA14_PWM3 ((unsigned int) AT91C_PIO_PA14) // PWM Channel 3 -#define AT91C_PIO_PA15 ((unsigned int) 1 << 15) // Pin Controlled by PA15 -#define AT91C_PA15_TF ((unsigned int) AT91C_PIO_PA15) // SSC Transmit Frame Sync -#define AT91C_PA15_TIOA1 ((unsigned int) AT91C_PIO_PA15) // Timer Counter 1 Multipurpose Timer I/O Pin A -#define AT91C_PIO_PA16 ((unsigned int) 1 << 16) // Pin Controlled by PA16 -#define AT91C_PA16_TK ((unsigned int) AT91C_PIO_PA16) // SSC Transmit Clock -#define AT91C_PA16_TIOB1 ((unsigned int) AT91C_PIO_PA16) // Timer Counter 1 Multipurpose Timer I/O Pin B -#define AT91C_PIO_PA17 ((unsigned int) 1 << 17) // Pin Controlled by PA17 -#define AT91C_PA17_TD ((unsigned int) AT91C_PIO_PA17) // SSC Transmit data -#define AT91C_PA17_PCK1 ((unsigned int) AT91C_PIO_PA17) // PMC Programmable Clock Output 1 -#define AT91C_PIO_PA18 ((unsigned int) 1 << 18) // Pin Controlled by PA18 -#define AT91C_PA18_RD ((unsigned int) AT91C_PIO_PA18) // SSC Receive Data -#define AT91C_PA18_PCK2 ((unsigned int) AT91C_PIO_PA18) // PMC Programmable Clock Output 2 -#define AT91C_PIO_PA19 ((unsigned int) 1 << 19) // Pin Controlled by PA19 -#define AT91C_PA19_RK ((unsigned int) AT91C_PIO_PA19) // SSC Receive Clock -#define AT91C_PA19_FIQ ((unsigned int) AT91C_PIO_PA19) // AIC Fast Interrupt Input -#define AT91C_PIO_PA2 ((unsigned int) 1 << 2) // Pin Controlled by PA2 -#define AT91C_PA2_PWM2 ((unsigned int) AT91C_PIO_PA2) // PWM Channel 2 -#define AT91C_PA2_SCK0 ((unsigned int) AT91C_PIO_PA2) // USART 0 Serial Clock -#define AT91C_PIO_PA20 ((unsigned int) 1 << 20) // Pin Controlled by PA20 -#define AT91C_PA20_RF ((unsigned int) AT91C_PIO_PA20) // SSC Receive Frame Sync -#define AT91C_PA20_IRQ0 ((unsigned int) AT91C_PIO_PA20) // External Interrupt 0 -#define AT91C_PIO_PA21 ((unsigned int) 1 << 21) // Pin Controlled by PA21 -#define AT91C_PA21_RXD1 ((unsigned int) AT91C_PIO_PA21) // USART 1 Receive Data -#define AT91C_PA21_PCK1 ((unsigned int) AT91C_PIO_PA21) // PMC Programmable Clock Output 1 -#define AT91C_PIO_PA22 ((unsigned int) 1 << 22) // Pin Controlled by PA22 -#define AT91C_PA22_TXD1 ((unsigned int) AT91C_PIO_PA22) // USART 1 Transmit Data -#define AT91C_PA22_NPCS3 ((unsigned int) AT91C_PIO_PA22) // SPI Peripheral Chip Select 3 -#define AT91C_PIO_PA23 ((unsigned int) 1 << 23) // Pin Controlled by PA23 -#define AT91C_PA23_SCK1 ((unsigned int) AT91C_PIO_PA23) // USART 1 Serial Clock -#define AT91C_PA23_PWM0 ((unsigned int) AT91C_PIO_PA23) // PWM Channel 0 -#define AT91C_PIO_PA24 ((unsigned int) 1 << 24) // Pin Controlled by PA24 -#define AT91C_PA24_RTS1 ((unsigned int) AT91C_PIO_PA24) // USART 1 Ready To Send -#define AT91C_PA24_PWM1 ((unsigned int) AT91C_PIO_PA24) // PWM Channel 1 -#define AT91C_PIO_PA25 ((unsigned int) 1 << 25) // Pin Controlled by PA25 -#define AT91C_PA25_CTS1 ((unsigned int) AT91C_PIO_PA25) // USART 1 Clear To Send -#define AT91C_PA25_PWM2 ((unsigned int) AT91C_PIO_PA25) // PWM Channel 2 -#define AT91C_PIO_PA26 ((unsigned int) 1 << 26) // Pin Controlled by PA26 -#define AT91C_PA26_DCD1 ((unsigned int) AT91C_PIO_PA26) // USART 1 Data Carrier Detect -#define AT91C_PA26_TIOA2 ((unsigned int) AT91C_PIO_PA26) // Timer Counter 2 Multipurpose Timer I/O Pin A -#define AT91C_PIO_PA27 ((unsigned int) 1 << 27) // Pin Controlled by PA27 -#define AT91C_PA27_DTR1 ((unsigned int) AT91C_PIO_PA27) // USART 1 Data Terminal ready -#define AT91C_PA27_TIOB2 ((unsigned int) AT91C_PIO_PA27) // Timer Counter 2 Multipurpose Timer I/O Pin B -#define AT91C_PIO_PA28 ((unsigned int) 1 << 28) // Pin Controlled by PA28 -#define AT91C_PA28_DSR1 ((unsigned int) AT91C_PIO_PA28) // USART 1 Data Set ready -#define AT91C_PA28_TCLK1 ((unsigned int) AT91C_PIO_PA28) // Timer Counter 1 external clock input -#define AT91C_PIO_PA29 ((unsigned int) 1 << 29) // Pin Controlled by PA29 -#define AT91C_PA29_RI1 ((unsigned int) AT91C_PIO_PA29) // USART 1 Ring Indicator -#define AT91C_PA29_TCLK2 ((unsigned int) AT91C_PIO_PA29) // Timer Counter 2 external clock input -#define AT91C_PIO_PA3 ((unsigned int) 1 << 3) // Pin Controlled by PA3 -#define AT91C_PA3_TWD ((unsigned int) AT91C_PIO_PA3) // TWI Two-wire Serial Data -#define AT91C_PA3_NPCS3 ((unsigned int) AT91C_PIO_PA3) // SPI Peripheral Chip Select 3 -#define AT91C_PIO_PA30 ((unsigned int) 1 << 30) // Pin Controlled by PA30 -#define AT91C_PA30_IRQ1 ((unsigned int) AT91C_PIO_PA30) // External Interrupt 1 -#define AT91C_PA30_NPCS2 ((unsigned int) AT91C_PIO_PA30) // SPI Peripheral Chip Select 2 -#define AT91C_PIO_PA31 ((unsigned int) 1 << 31) // Pin Controlled by PA31 -#define AT91C_PA31_NPCS1 ((unsigned int) AT91C_PIO_PA31) // SPI Peripheral Chip Select 1 -#define AT91C_PA31_PCK2 ((unsigned int) AT91C_PIO_PA31) // PMC Programmable Clock Output 2 -#define AT91C_PIO_PA4 ((unsigned int) 1 << 4) // Pin Controlled by PA4 -#define AT91C_PA4_TWCK ((unsigned int) AT91C_PIO_PA4) // TWI Two-wire Serial Clock -#define AT91C_PA4_TCLK0 ((unsigned int) AT91C_PIO_PA4) // Timer Counter 0 external clock input -#define AT91C_PIO_PA5 ((unsigned int) 1 << 5) // Pin Controlled by PA5 -#define AT91C_PA5_RXD0 ((unsigned int) AT91C_PIO_PA5) // USART 0 Receive Data -#define AT91C_PA5_NPCS3 ((unsigned int) AT91C_PIO_PA5) // SPI Peripheral Chip Select 3 -#define AT91C_PIO_PA6 ((unsigned int) 1 << 6) // Pin Controlled by PA6 -#define AT91C_PA6_TXD0 ((unsigned int) AT91C_PIO_PA6) // USART 0 Transmit Data -#define AT91C_PA6_PCK0 ((unsigned int) AT91C_PIO_PA6) // PMC Programmable Clock Output 0 -#define AT91C_PIO_PA7 ((unsigned int) 1 << 7) // Pin Controlled by PA7 -#define AT91C_PA7_RTS0 ((unsigned int) AT91C_PIO_PA7) // USART 0 Ready To Send -#define AT91C_PA7_PWM3 ((unsigned int) AT91C_PIO_PA7) // PWM Channel 3 -#define AT91C_PIO_PA8 ((unsigned int) 1 << 8) // Pin Controlled by PA8 -#define AT91C_PA8_CTS0 ((unsigned int) AT91C_PIO_PA8) // USART 0 Clear To Send -#define AT91C_PA8_ADTRG ((unsigned int) AT91C_PIO_PA8) // ADC External Trigger -#define AT91C_PIO_PA9 ((unsigned int) 1 << 9) // Pin Controlled by PA9 -#define AT91C_PA9_DRXD ((unsigned int) AT91C_PIO_PA9) // DBGU Debug Receive Data -#define AT91C_PA9_NPCS1 ((unsigned int) AT91C_PIO_PA9) // SPI Peripheral Chip Select 1 +/* ***************************************************************************** */ +/* PIO DEFINITIONS FOR AT91SAM7S64 */ +/* ***************************************************************************** */ +#define AT91C_PIO_PA0 ( ( unsigned int ) 1 << 0 ) /* Pin Controlled by PA0 */ +#define AT91C_PA0_PWM0 ( ( unsigned int ) AT91C_PIO_PA0 ) /* PWM Channel 0 */ +#define AT91C_PA0_TIOA0 ( ( unsigned int ) AT91C_PIO_PA0 ) /* Timer Counter 0 Multipurpose Timer I/O Pin A */ +#define AT91C_PIO_PA1 ( ( unsigned int ) 1 << 1 ) /* Pin Controlled by PA1 */ +#define AT91C_PA1_PWM1 ( ( unsigned int ) AT91C_PIO_PA1 ) /* PWM Channel 1 */ +#define AT91C_PA1_TIOB0 ( ( unsigned int ) AT91C_PIO_PA1 ) /* Timer Counter 0 Multipurpose Timer I/O Pin B */ +#define AT91C_PIO_PA10 ( ( unsigned int ) 1 << 10 ) /* Pin Controlled by PA10 */ +#define AT91C_PA10_DTXD ( ( unsigned int ) AT91C_PIO_PA10 ) /* DBGU Debug Transmit Data */ +#define AT91C_PA10_NPCS2 ( ( unsigned int ) AT91C_PIO_PA10 ) /* SPI Peripheral Chip Select 2 */ +#define AT91C_PIO_PA11 ( ( unsigned int ) 1 << 11 ) /* Pin Controlled by PA11 */ +#define AT91C_PA11_NPCS0 ( ( unsigned int ) AT91C_PIO_PA11 ) /* SPI Peripheral Chip Select 0 */ +#define AT91C_PA11_PWM0 ( ( unsigned int ) AT91C_PIO_PA11 ) /* PWM Channel 0 */ +#define AT91C_PIO_PA12 ( ( unsigned int ) 1 << 12 ) /* Pin Controlled by PA12 */ +#define AT91C_PA12_MISO ( ( unsigned int ) AT91C_PIO_PA12 ) /* SPI Master In Slave */ +#define AT91C_PA12_PWM1 ( ( unsigned int ) AT91C_PIO_PA12 ) /* PWM Channel 1 */ +#define AT91C_PIO_PA13 ( ( unsigned int ) 1 << 13 ) /* Pin Controlled by PA13 */ +#define AT91C_PA13_MOSI ( ( unsigned int ) AT91C_PIO_PA13 ) /* SPI Master Out Slave */ +#define AT91C_PA13_PWM2 ( ( unsigned int ) AT91C_PIO_PA13 ) /* PWM Channel 2 */ +#define AT91C_PIO_PA14 ( ( unsigned int ) 1 << 14 ) /* Pin Controlled by PA14 */ +#define AT91C_PA14_SPCK ( ( unsigned int ) AT91C_PIO_PA14 ) /* SPI Serial Clock */ +#define AT91C_PA14_PWM3 ( ( unsigned int ) AT91C_PIO_PA14 ) /* PWM Channel 3 */ +#define AT91C_PIO_PA15 ( ( unsigned int ) 1 << 15 ) /* Pin Controlled by PA15 */ +#define AT91C_PA15_TF ( ( unsigned int ) AT91C_PIO_PA15 ) /* SSC Transmit Frame Sync */ +#define AT91C_PA15_TIOA1 ( ( unsigned int ) AT91C_PIO_PA15 ) /* Timer Counter 1 Multipurpose Timer I/O Pin A */ +#define AT91C_PIO_PA16 ( ( unsigned int ) 1 << 16 ) /* Pin Controlled by PA16 */ +#define AT91C_PA16_TK ( ( unsigned int ) AT91C_PIO_PA16 ) /* SSC Transmit Clock */ +#define AT91C_PA16_TIOB1 ( ( unsigned int ) AT91C_PIO_PA16 ) /* Timer Counter 1 Multipurpose Timer I/O Pin B */ +#define AT91C_PIO_PA17 ( ( unsigned int ) 1 << 17 ) /* Pin Controlled by PA17 */ +#define AT91C_PA17_TD ( ( unsigned int ) AT91C_PIO_PA17 ) /* SSC Transmit data */ +#define AT91C_PA17_PCK1 ( ( unsigned int ) AT91C_PIO_PA17 ) /* PMC Programmable Clock Output 1 */ +#define AT91C_PIO_PA18 ( ( unsigned int ) 1 << 18 ) /* Pin Controlled by PA18 */ +#define AT91C_PA18_RD ( ( unsigned int ) AT91C_PIO_PA18 ) /* SSC Receive Data */ +#define AT91C_PA18_PCK2 ( ( unsigned int ) AT91C_PIO_PA18 ) /* PMC Programmable Clock Output 2 */ +#define AT91C_PIO_PA19 ( ( unsigned int ) 1 << 19 ) /* Pin Controlled by PA19 */ +#define AT91C_PA19_RK ( ( unsigned int ) AT91C_PIO_PA19 ) /* SSC Receive Clock */ +#define AT91C_PA19_FIQ ( ( unsigned int ) AT91C_PIO_PA19 ) /* AIC Fast Interrupt Input */ +#define AT91C_PIO_PA2 ( ( unsigned int ) 1 << 2 ) /* Pin Controlled by PA2 */ +#define AT91C_PA2_PWM2 ( ( unsigned int ) AT91C_PIO_PA2 ) /* PWM Channel 2 */ +#define AT91C_PA2_SCK0 ( ( unsigned int ) AT91C_PIO_PA2 ) /* USART 0 Serial Clock */ +#define AT91C_PIO_PA20 ( ( unsigned int ) 1 << 20 ) /* Pin Controlled by PA20 */ +#define AT91C_PA20_RF ( ( unsigned int ) AT91C_PIO_PA20 ) /* SSC Receive Frame Sync */ +#define AT91C_PA20_IRQ0 ( ( unsigned int ) AT91C_PIO_PA20 ) /* External Interrupt 0 */ +#define AT91C_PIO_PA21 ( ( unsigned int ) 1 << 21 ) /* Pin Controlled by PA21 */ +#define AT91C_PA21_RXD1 ( ( unsigned int ) AT91C_PIO_PA21 ) /* USART 1 Receive Data */ +#define AT91C_PA21_PCK1 ( ( unsigned int ) AT91C_PIO_PA21 ) /* PMC Programmable Clock Output 1 */ +#define AT91C_PIO_PA22 ( ( unsigned int ) 1 << 22 ) /* Pin Controlled by PA22 */ +#define AT91C_PA22_TXD1 ( ( unsigned int ) AT91C_PIO_PA22 ) /* USART 1 Transmit Data */ +#define AT91C_PA22_NPCS3 ( ( unsigned int ) AT91C_PIO_PA22 ) /* SPI Peripheral Chip Select 3 */ +#define AT91C_PIO_PA23 ( ( unsigned int ) 1 << 23 ) /* Pin Controlled by PA23 */ +#define AT91C_PA23_SCK1 ( ( unsigned int ) AT91C_PIO_PA23 ) /* USART 1 Serial Clock */ +#define AT91C_PA23_PWM0 ( ( unsigned int ) AT91C_PIO_PA23 ) /* PWM Channel 0 */ +#define AT91C_PIO_PA24 ( ( unsigned int ) 1 << 24 ) /* Pin Controlled by PA24 */ +#define AT91C_PA24_RTS1 ( ( unsigned int ) AT91C_PIO_PA24 ) /* USART 1 Ready To Send */ +#define AT91C_PA24_PWM1 ( ( unsigned int ) AT91C_PIO_PA24 ) /* PWM Channel 1 */ +#define AT91C_PIO_PA25 ( ( unsigned int ) 1 << 25 ) /* Pin Controlled by PA25 */ +#define AT91C_PA25_CTS1 ( ( unsigned int ) AT91C_PIO_PA25 ) /* USART 1 Clear To Send */ +#define AT91C_PA25_PWM2 ( ( unsigned int ) AT91C_PIO_PA25 ) /* PWM Channel 2 */ +#define AT91C_PIO_PA26 ( ( unsigned int ) 1 << 26 ) /* Pin Controlled by PA26 */ +#define AT91C_PA26_DCD1 ( ( unsigned int ) AT91C_PIO_PA26 ) /* USART 1 Data Carrier Detect */ +#define AT91C_PA26_TIOA2 ( ( unsigned int ) AT91C_PIO_PA26 ) /* Timer Counter 2 Multipurpose Timer I/O Pin A */ +#define AT91C_PIO_PA27 ( ( unsigned int ) 1 << 27 ) /* Pin Controlled by PA27 */ +#define AT91C_PA27_DTR1 ( ( unsigned int ) AT91C_PIO_PA27 ) /* USART 1 Data Terminal ready */ +#define AT91C_PA27_TIOB2 ( ( unsigned int ) AT91C_PIO_PA27 ) /* Timer Counter 2 Multipurpose Timer I/O Pin B */ +#define AT91C_PIO_PA28 ( ( unsigned int ) 1 << 28 ) /* Pin Controlled by PA28 */ +#define AT91C_PA28_DSR1 ( ( unsigned int ) AT91C_PIO_PA28 ) /* USART 1 Data Set ready */ +#define AT91C_PA28_TCLK1 ( ( unsigned int ) AT91C_PIO_PA28 ) /* Timer Counter 1 external clock input */ +#define AT91C_PIO_PA29 ( ( unsigned int ) 1 << 29 ) /* Pin Controlled by PA29 */ +#define AT91C_PA29_RI1 ( ( unsigned int ) AT91C_PIO_PA29 ) /* USART 1 Ring Indicator */ +#define AT91C_PA29_TCLK2 ( ( unsigned int ) AT91C_PIO_PA29 ) /* Timer Counter 2 external clock input */ +#define AT91C_PIO_PA3 ( ( unsigned int ) 1 << 3 ) /* Pin Controlled by PA3 */ +#define AT91C_PA3_TWD ( ( unsigned int ) AT91C_PIO_PA3 ) /* TWI Two-wire Serial Data */ +#define AT91C_PA3_NPCS3 ( ( unsigned int ) AT91C_PIO_PA3 ) /* SPI Peripheral Chip Select 3 */ +#define AT91C_PIO_PA30 ( ( unsigned int ) 1 << 30 ) /* Pin Controlled by PA30 */ +#define AT91C_PA30_IRQ1 ( ( unsigned int ) AT91C_PIO_PA30 ) /* External Interrupt 1 */ +#define AT91C_PA30_NPCS2 ( ( unsigned int ) AT91C_PIO_PA30 ) /* SPI Peripheral Chip Select 2 */ +#define AT91C_PIO_PA31 ( ( unsigned int ) 1 << 31 ) /* Pin Controlled by PA31 */ +#define AT91C_PA31_NPCS1 ( ( unsigned int ) AT91C_PIO_PA31 ) /* SPI Peripheral Chip Select 1 */ +#define AT91C_PA31_PCK2 ( ( unsigned int ) AT91C_PIO_PA31 ) /* PMC Programmable Clock Output 2 */ +#define AT91C_PIO_PA4 ( ( unsigned int ) 1 << 4 ) /* Pin Controlled by PA4 */ +#define AT91C_PA4_TWCK ( ( unsigned int ) AT91C_PIO_PA4 ) /* TWI Two-wire Serial Clock */ +#define AT91C_PA4_TCLK0 ( ( unsigned int ) AT91C_PIO_PA4 ) /* Timer Counter 0 external clock input */ +#define AT91C_PIO_PA5 ( ( unsigned int ) 1 << 5 ) /* Pin Controlled by PA5 */ +#define AT91C_PA5_RXD0 ( ( unsigned int ) AT91C_PIO_PA5 ) /* USART 0 Receive Data */ +#define AT91C_PA5_NPCS3 ( ( unsigned int ) AT91C_PIO_PA5 ) /* SPI Peripheral Chip Select 3 */ +#define AT91C_PIO_PA6 ( ( unsigned int ) 1 << 6 ) /* Pin Controlled by PA6 */ +#define AT91C_PA6_TXD0 ( ( unsigned int ) AT91C_PIO_PA6 ) /* USART 0 Transmit Data */ +#define AT91C_PA6_PCK0 ( ( unsigned int ) AT91C_PIO_PA6 ) /* PMC Programmable Clock Output 0 */ +#define AT91C_PIO_PA7 ( ( unsigned int ) 1 << 7 ) /* Pin Controlled by PA7 */ +#define AT91C_PA7_RTS0 ( ( unsigned int ) AT91C_PIO_PA7 ) /* USART 0 Ready To Send */ +#define AT91C_PA7_PWM3 ( ( unsigned int ) AT91C_PIO_PA7 ) /* PWM Channel 3 */ +#define AT91C_PIO_PA8 ( ( unsigned int ) 1 << 8 ) /* Pin Controlled by PA8 */ +#define AT91C_PA8_CTS0 ( ( unsigned int ) AT91C_PIO_PA8 ) /* USART 0 Clear To Send */ +#define AT91C_PA8_ADTRG ( ( unsigned int ) AT91C_PIO_PA8 ) /* ADC External Trigger */ +#define AT91C_PIO_PA9 ( ( unsigned int ) 1 << 9 ) /* Pin Controlled by PA9 */ +#define AT91C_PA9_DRXD ( ( unsigned int ) AT91C_PIO_PA9 ) /* DBGU Debug Receive Data */ +#define AT91C_PA9_NPCS1 ( ( unsigned int ) AT91C_PIO_PA9 ) /* SPI Peripheral Chip Select 1 */ -// ***************************************************************************** -// PERIPHERAL ID DEFINITIONS FOR AT91SAM7S64 -// ***************************************************************************** -#define AT91C_ID_FIQ ((unsigned int) 0) // Advanced Interrupt Controller (FIQ) -#define AT91C_ID_SYS ((unsigned int) 1) // System Peripheral -#define AT91C_ID_PIOA ((unsigned int) 2) // Parallel IO Controller -#define AT91C_ID_3_Reserved ((unsigned int) 3) // Reserved -#define AT91C_ID_ADC ((unsigned int) 4) // Analog-to-Digital Converter -#define AT91C_ID_SPI ((unsigned int) 5) // Serial Peripheral Interface -#define AT91C_ID_US0 ((unsigned int) 6) // USART 0 -#define AT91C_ID_US1 ((unsigned int) 7) // USART 1 -#define AT91C_ID_SSC ((unsigned int) 8) // Serial Synchronous Controller -#define AT91C_ID_TWI ((unsigned int) 9) // Two-Wire Interface -#define AT91C_ID_PWMC ((unsigned int) 10) // PWM Controller -#define AT91C_ID_UDP ((unsigned int) 11) // USB Device Port -#define AT91C_ID_TC0 ((unsigned int) 12) // Timer Counter 0 -#define AT91C_ID_TC1 ((unsigned int) 13) // Timer Counter 1 -#define AT91C_ID_TC2 ((unsigned int) 14) // Timer Counter 2 -#define AT91C_ID_15_Reserved ((unsigned int) 15) // Reserved -#define AT91C_ID_16_Reserved ((unsigned int) 16) // Reserved -#define AT91C_ID_17_Reserved ((unsigned int) 17) // Reserved -#define AT91C_ID_18_Reserved ((unsigned int) 18) // Reserved -#define AT91C_ID_19_Reserved ((unsigned int) 19) // Reserved -#define AT91C_ID_20_Reserved ((unsigned int) 20) // Reserved -#define AT91C_ID_21_Reserved ((unsigned int) 21) // Reserved -#define AT91C_ID_22_Reserved ((unsigned int) 22) // Reserved -#define AT91C_ID_23_Reserved ((unsigned int) 23) // Reserved -#define AT91C_ID_24_Reserved ((unsigned int) 24) // Reserved -#define AT91C_ID_25_Reserved ((unsigned int) 25) // Reserved -#define AT91C_ID_26_Reserved ((unsigned int) 26) // Reserved -#define AT91C_ID_27_Reserved ((unsigned int) 27) // Reserved -#define AT91C_ID_28_Reserved ((unsigned int) 28) // Reserved -#define AT91C_ID_29_Reserved ((unsigned int) 29) // Reserved -#define AT91C_ID_IRQ0 ((unsigned int) 30) // Advanced Interrupt Controller (IRQ0) -#define AT91C_ID_IRQ1 ((unsigned int) 31) // Advanced Interrupt Controller (IRQ1) +/* ***************************************************************************** */ +/* PERIPHERAL ID DEFINITIONS FOR AT91SAM7S64 */ +/* ***************************************************************************** */ +#define AT91C_ID_FIQ ( ( unsigned int ) 0 ) /* Advanced Interrupt Controller (FIQ) */ +#define AT91C_ID_SYS ( ( unsigned int ) 1 ) /* System Peripheral */ +#define AT91C_ID_PIOA ( ( unsigned int ) 2 ) /* Parallel IO Controller */ +#define AT91C_ID_3_Reserved ( ( unsigned int ) 3 ) /* Reserved */ +#define AT91C_ID_ADC ( ( unsigned int ) 4 ) /* Analog-to-Digital Converter */ +#define AT91C_ID_SPI ( ( unsigned int ) 5 ) /* Serial Peripheral Interface */ +#define AT91C_ID_US0 ( ( unsigned int ) 6 ) /* USART 0 */ +#define AT91C_ID_US1 ( ( unsigned int ) 7 ) /* USART 1 */ +#define AT91C_ID_SSC ( ( unsigned int ) 8 ) /* Serial Synchronous Controller */ +#define AT91C_ID_TWI ( ( unsigned int ) 9 ) /* Two-Wire Interface */ +#define AT91C_ID_PWMC ( ( unsigned int ) 10 ) /* PWM Controller */ +#define AT91C_ID_UDP ( ( unsigned int ) 11 ) /* USB Device Port */ +#define AT91C_ID_TC0 ( ( unsigned int ) 12 ) /* Timer Counter 0 */ +#define AT91C_ID_TC1 ( ( unsigned int ) 13 ) /* Timer Counter 1 */ +#define AT91C_ID_TC2 ( ( unsigned int ) 14 ) /* Timer Counter 2 */ +#define AT91C_ID_15_Reserved ( ( unsigned int ) 15 ) /* Reserved */ +#define AT91C_ID_16_Reserved ( ( unsigned int ) 16 ) /* Reserved */ +#define AT91C_ID_17_Reserved ( ( unsigned int ) 17 ) /* Reserved */ +#define AT91C_ID_18_Reserved ( ( unsigned int ) 18 ) /* Reserved */ +#define AT91C_ID_19_Reserved ( ( unsigned int ) 19 ) /* Reserved */ +#define AT91C_ID_20_Reserved ( ( unsigned int ) 20 ) /* Reserved */ +#define AT91C_ID_21_Reserved ( ( unsigned int ) 21 ) /* Reserved */ +#define AT91C_ID_22_Reserved ( ( unsigned int ) 22 ) /* Reserved */ +#define AT91C_ID_23_Reserved ( ( unsigned int ) 23 ) /* Reserved */ +#define AT91C_ID_24_Reserved ( ( unsigned int ) 24 ) /* Reserved */ +#define AT91C_ID_25_Reserved ( ( unsigned int ) 25 ) /* Reserved */ +#define AT91C_ID_26_Reserved ( ( unsigned int ) 26 ) /* Reserved */ +#define AT91C_ID_27_Reserved ( ( unsigned int ) 27 ) /* Reserved */ +#define AT91C_ID_28_Reserved ( ( unsigned int ) 28 ) /* Reserved */ +#define AT91C_ID_29_Reserved ( ( unsigned int ) 29 ) /* Reserved */ +#define AT91C_ID_IRQ0 ( ( unsigned int ) 30 ) /* Advanced Interrupt Controller (IRQ0) */ +#define AT91C_ID_IRQ1 ( ( unsigned int ) 31 ) /* Advanced Interrupt Controller (IRQ1) */ -// ***************************************************************************** -// BASE ADDRESS DEFINITIONS FOR AT91SAM7S64 -// ***************************************************************************** -#define AT91C_BASE_SYSC ((AT91PS_SYSC) 0xFFFFF000) // (SYSC) Base Address -#define AT91C_BASE_AIC ((AT91PS_AIC) 0xFFFFF000) // (AIC) Base Address -#define AT91C_BASE_DBGU ((AT91PS_DBGU) 0xFFFFF200) // (DBGU) Base Address -#define AT91C_BASE_PDC_DBGU ((AT91PS_PDC) 0xFFFFF300) // (PDC_DBGU) Base Address -#define AT91C_BASE_PIOA ((AT91PS_PIO) 0xFFFFF400) // (PIOA) Base Address -#define AT91C_BASE_CKGR ((AT91PS_CKGR) 0xFFFFFC20) // (CKGR) Base Address -#define AT91C_BASE_PMC ((AT91PS_PMC) 0xFFFFFC00) // (PMC) Base Address -#define AT91C_BASE_RSTC ((AT91PS_RSTC) 0xFFFFFD00) // (RSTC) Base Address -#define AT91C_BASE_RTTC ((AT91PS_RTTC) 0xFFFFFD20) // (RTTC) Base Address -#define AT91C_BASE_PITC ((AT91PS_PITC) 0xFFFFFD30) // (PITC) Base Address -#define AT91C_BASE_WDTC ((AT91PS_WDTC) 0xFFFFFD40) // (WDTC) Base Address -#define AT91C_BASE_MC ((AT91PS_MC) 0xFFFFFF00) // (MC) Base Address -#define AT91C_BASE_PDC_SPI ((AT91PS_PDC) 0xFFFE0100) // (PDC_SPI) Base Address -#define AT91C_BASE_SPI ((AT91PS_SPI) 0xFFFE0000) // (SPI) Base Address -#define AT91C_BASE_PDC_ADC ((AT91PS_PDC) 0xFFFD8100) // (PDC_ADC) Base Address -#define AT91C_BASE_ADC ((AT91PS_ADC) 0xFFFD8000) // (ADC) Base Address -#define AT91C_BASE_PDC_SSC ((AT91PS_PDC) 0xFFFD4100) // (PDC_SSC) Base Address -#define AT91C_BASE_SSC ((AT91PS_SSC) 0xFFFD4000) // (SSC) Base Address -#define AT91C_BASE_PDC_US1 ((AT91PS_PDC) 0xFFFC4100) // (PDC_US1) Base Address -#define AT91C_BASE_US1 ((AT91PS_USART) 0xFFFC4000) // (US1) Base Address -#define AT91C_BASE_PDC_US0 ((AT91PS_PDC) 0xFFFC0100) // (PDC_US0) Base Address -#define AT91C_BASE_US0 ((AT91PS_USART) 0xFFFC0000) // (US0) Base Address -#define AT91C_BASE_TWI ((AT91PS_TWI) 0xFFFB8000) // (TWI) Base Address -#define AT91C_BASE_TC2 ((AT91PS_TC) 0xFFFA0080) // (TC2) Base Address -#define AT91C_BASE_TC1 ((AT91PS_TC) 0xFFFA0040) // (TC1) Base Address -#define AT91C_BASE_TC0 ((AT91PS_TC) 0xFFFA0000) // (TC0) Base Address -#define AT91C_BASE_TCB ((AT91PS_TCB) 0xFFFA0000) // (TCB) Base Address -#define AT91C_BASE_PWMC_CH3 ((AT91PS_PWMC_CH) 0xFFFCC260) // (PWMC_CH3) Base Address -#define AT91C_BASE_PWMC_CH2 ((AT91PS_PWMC_CH) 0xFFFCC240) // (PWMC_CH2) Base Address -#define AT91C_BASE_PWMC_CH1 ((AT91PS_PWMC_CH) 0xFFFCC220) // (PWMC_CH1) Base Address -#define AT91C_BASE_PWMC_CH0 ((AT91PS_PWMC_CH) 0xFFFCC200) // (PWMC_CH0) Base Address -#define AT91C_BASE_PWMC ((AT91PS_PWMC) 0xFFFCC000) // (PWMC) Base Address -#define AT91C_BASE_UDP ((AT91PS_UDP) 0xFFFB0000) // (UDP) Base Address +/* ***************************************************************************** */ +/* BASE ADDRESS DEFINITIONS FOR AT91SAM7S64 */ +/* ***************************************************************************** */ +#define AT91C_BASE_SYSC ( ( AT91PS_SYSC ) 0xFFFFF000 ) /* (SYSC) Base Address */ +#define AT91C_BASE_AIC ( ( AT91PS_AIC ) 0xFFFFF000 ) /* (AIC) Base Address */ +#define AT91C_BASE_DBGU ( ( AT91PS_DBGU ) 0xFFFFF200 ) /* (DBGU) Base Address */ +#define AT91C_BASE_PDC_DBGU ( ( AT91PS_PDC ) 0xFFFFF300 ) /* (PDC_DBGU) Base Address */ +#define AT91C_BASE_PIOA ( ( AT91PS_PIO ) 0xFFFFF400 ) /* (PIOA) Base Address */ +#define AT91C_BASE_CKGR ( ( AT91PS_CKGR ) 0xFFFFFC20 ) /* (CKGR) Base Address */ +#define AT91C_BASE_PMC ( ( AT91PS_PMC ) 0xFFFFFC00 ) /* (PMC) Base Address */ +#define AT91C_BASE_RSTC ( ( AT91PS_RSTC ) 0xFFFFFD00 ) /* (RSTC) Base Address */ +#define AT91C_BASE_RTTC ( ( AT91PS_RTTC ) 0xFFFFFD20 ) /* (RTTC) Base Address */ +#define AT91C_BASE_PITC ( ( AT91PS_PITC ) 0xFFFFFD30 ) /* (PITC) Base Address */ +#define AT91C_BASE_WDTC ( ( AT91PS_WDTC ) 0xFFFFFD40 ) /* (WDTC) Base Address */ +#define AT91C_BASE_MC ( ( AT91PS_MC ) 0xFFFFFF00 ) /* (MC) Base Address */ +#define AT91C_BASE_PDC_SPI ( ( AT91PS_PDC ) 0xFFFE0100 ) /* (PDC_SPI) Base Address */ +#define AT91C_BASE_SPI ( ( AT91PS_SPI ) 0xFFFE0000 ) /* (SPI) Base Address */ +#define AT91C_BASE_PDC_ADC ( ( AT91PS_PDC ) 0xFFFD8100 ) /* (PDC_ADC) Base Address */ +#define AT91C_BASE_ADC ( ( AT91PS_ADC ) 0xFFFD8000 ) /* (ADC) Base Address */ +#define AT91C_BASE_PDC_SSC ( ( AT91PS_PDC ) 0xFFFD4100 ) /* (PDC_SSC) Base Address */ +#define AT91C_BASE_SSC ( ( AT91PS_SSC ) 0xFFFD4000 ) /* (SSC) Base Address */ +#define AT91C_BASE_PDC_US1 ( ( AT91PS_PDC ) 0xFFFC4100 ) /* (PDC_US1) Base Address */ +#define AT91C_BASE_US1 ( ( AT91PS_USART ) 0xFFFC4000 ) /* (US1) Base Address */ +#define AT91C_BASE_PDC_US0 ( ( AT91PS_PDC ) 0xFFFC0100 ) /* (PDC_US0) Base Address */ +#define AT91C_BASE_US0 ( ( AT91PS_USART ) 0xFFFC0000 ) /* (US0) Base Address */ +#define AT91C_BASE_TWI ( ( AT91PS_TWI ) 0xFFFB8000 ) /* (TWI) Base Address */ +#define AT91C_BASE_TC2 ( ( AT91PS_TC ) 0xFFFA0080 ) /* (TC2) Base Address */ +#define AT91C_BASE_TC1 ( ( AT91PS_TC ) 0xFFFA0040 ) /* (TC1) Base Address */ +#define AT91C_BASE_TC0 ( ( AT91PS_TC ) 0xFFFA0000 ) /* (TC0) Base Address */ +#define AT91C_BASE_TCB ( ( AT91PS_TCB ) 0xFFFA0000 ) /* (TCB) Base Address */ +#define AT91C_BASE_PWMC_CH3 ( ( AT91PS_PWMC_CH ) 0xFFFCC260 ) /* (PWMC_CH3) Base Address */ +#define AT91C_BASE_PWMC_CH2 ( ( AT91PS_PWMC_CH ) 0xFFFCC240 ) /* (PWMC_CH2) Base Address */ +#define AT91C_BASE_PWMC_CH1 ( ( AT91PS_PWMC_CH ) 0xFFFCC220 ) /* (PWMC_CH1) Base Address */ +#define AT91C_BASE_PWMC_CH0 ( ( AT91PS_PWMC_CH ) 0xFFFCC200 ) /* (PWMC_CH0) Base Address */ +#define AT91C_BASE_PWMC ( ( AT91PS_PWMC ) 0xFFFCC000 ) /* (PWMC) Base Address */ +#define AT91C_BASE_UDP ( ( AT91PS_UDP ) 0xFFFB0000 ) /* (UDP) Base Address */ -// ***************************************************************************** -// MEMORY MAPPING DEFINITIONS FOR AT91SAM7S64 -// ***************************************************************************** -#define AT91C_ISRAM ((char *) 0x00200000) // Internal SRAM base address -#define AT91C_ISRAM_SIZE ((unsigned int) 0x00004000) // Internal SRAM size in byte (16 Kbyte) -#define AT91C_IFLASH ((char *) 0x00100000) // Internal ROM base address -#define AT91C_IFLASH_SIZE ((unsigned int) 0x00010000) // Internal ROM size in byte (64 Kbyte) +/* ***************************************************************************** */ +/* MEMORY MAPPING DEFINITIONS FOR AT91SAM7S64 */ +/* ***************************************************************************** */ +#define AT91C_ISRAM ( ( char * ) 0x00200000 ) /* Internal SRAM base address */ +#define AT91C_ISRAM_SIZE ( ( unsigned int ) 0x00004000 ) /* Internal SRAM size in byte (16 Kbyte) */ +#define AT91C_IFLASH ( ( char * ) 0x00100000 ) /* Internal ROM base address */ +#define AT91C_IFLASH_SIZE ( ( unsigned int ) 0x00010000 ) /* Internal ROM size in byte (64 Kbyte) */ -#endif +#endif /* ifndef AT91SAM7S64_H */ diff --git a/Source/portable/IAR/AtmelSAM7S64/AT91SAM7S64_inc.h b/Source/portable/IAR/AtmelSAM7S64/AT91SAM7S64_inc.h index 77e866941..9d95f3eb7 100644 --- a/Source/portable/IAR/AtmelSAM7S64/AT91SAM7S64_inc.h +++ b/Source/portable/IAR/AtmelSAM7S64/AT91SAM7S64_inc.h @@ -1,1810 +1,1810 @@ -// ---------------------------------------------------------------------------- -// ATMEL Microcontroller Software Support - ROUSSET - -// ---------------------------------------------------------------------------- -// The software is delivered "AS IS" without warranty or condition of any -// kind, either express, implied or statutory. This includes without -// limitation any warranty or condition with respect to merchantability or -// fitness for any particular purpose, or against the infringements of -// intellectual property rights of others. -// ---------------------------------------------------------------------------- -// File Name : AT91SAM7S64.h -// Object : AT91SAM7S64 definitions -// Generated : AT91 SW Application Group 07/16/2004 (07:43:09) -// -// CVS Reference : /AT91SAM7S64.pl/1.12/Mon Jul 12 13:02:30 2004// -// CVS Reference : /SYSC_SAM7Sxx.pl/1.5/Mon Jul 12 16:22:12 2004// -// CVS Reference : /MC_SAM02.pl/1.3/Wed Mar 10 08:37:04 2004// -// CVS Reference : /UDP_1765B.pl/1.3/Fri Aug 2 14:45:38 2002// -// CVS Reference : /AIC_1796B.pl/1.1.1.1/Fri Jun 28 09:36:48 2002// -// CVS Reference : /lib_pmc_SAM.h/1.6/Tue Apr 27 13:53:52 2004// -// CVS Reference : /PIO_1725D.pl/1.1.1.1/Fri Jun 28 09:36:48 2002// -// CVS Reference : /DBGU_1754A.pl/1.4/Fri Jan 31 12:18:24 2003// -// CVS Reference : /US_1739C.pl/1.2/Mon Jul 12 17:26:24 2004// -// CVS Reference : /SPI2.pl/1.2/Fri Oct 17 08:13:40 2003// -// CVS Reference : /SSC_1762A.pl/1.2/Fri Nov 8 13:26:40 2002// -// CVS Reference : /lib_tc_1753b.h/1.1/Fri Jan 31 12:20:02 2003// -// CVS Reference : /TWI_1761B.pl/1.4/Fri Feb 7 10:30:08 2003// -// CVS Reference : /PDC_1734B.pl/1.2/Thu Nov 21 16:38:24 2002// -// CVS Reference : /ADC_SAM.pl/1.7/Fri Oct 17 08:12:38 2003// -// CVS Reference : /lib_PWM_SAM.h/1.3/Thu Jan 22 10:10:50 2004// -// ---------------------------------------------------------------------------- +/* ---------------------------------------------------------------------------- */ +/* ATMEL Microcontroller Software Support - ROUSSET - */ +/* ---------------------------------------------------------------------------- */ +/* The software is delivered "AS IS" without warranty or condition of any */ +/* kind, either express, implied or statutory. This includes without */ +/* limitation any warranty or condition with respect to merchantability or */ +/* fitness for any particular purpose, or against the infringements of */ +/* intellectual property rights of others. */ +/* ---------------------------------------------------------------------------- */ +/* File Name : AT91SAM7S64.h */ +/* Object : AT91SAM7S64 definitions */ +/* Generated : AT91 SW Application Group 07/16/2004 (07:43:09) */ +/* */ +/* CVS Reference : /AT91SAM7S64.pl/1.12/Mon Jul 12 13:02:30 2004// */ +/* CVS Reference : /SYSC_SAM7Sxx.pl/1.5/Mon Jul 12 16:22:12 2004// */ +/* CVS Reference : /MC_SAM02.pl/1.3/Wed Mar 10 08:37:04 2004// */ +/* CVS Reference : /UDP_1765B.pl/1.3/Fri Aug 2 14:45:38 2002// */ +/* CVS Reference : /AIC_1796B.pl/1.1.1.1/Fri Jun 28 09:36:48 2002// */ +/* CVS Reference : /lib_pmc_SAM.h/1.6/Tue Apr 27 13:53:52 2004// */ +/* CVS Reference : /PIO_1725D.pl/1.1.1.1/Fri Jun 28 09:36:48 2002// */ +/* CVS Reference : /DBGU_1754A.pl/1.4/Fri Jan 31 12:18:24 2003// */ +/* CVS Reference : /US_1739C.pl/1.2/Mon Jul 12 17:26:24 2004// */ +/* CVS Reference : /SPI2.pl/1.2/Fri Oct 17 08:13:40 2003// */ +/* CVS Reference : /SSC_1762A.pl/1.2/Fri Nov 8 13:26:40 2002// */ +/* CVS Reference : /lib_tc_1753b.h/1.1/Fri Jan 31 12:20:02 2003// */ +/* CVS Reference : /TWI_1761B.pl/1.4/Fri Feb 7 10:30:08 2003// */ +/* CVS Reference : /PDC_1734B.pl/1.2/Thu Nov 21 16:38:24 2002// */ +/* CVS Reference : /ADC_SAM.pl/1.7/Fri Oct 17 08:12:38 2003// */ +/* CVS Reference : /lib_PWM_SAM.h/1.3/Thu Jan 22 10:10:50 2004// */ +/* ---------------------------------------------------------------------------- */ -// Hardware register definition +/* Hardware register definition */ -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR System Peripherals -// ***************************************************************************** -// *** Register offset in AT91S_SYSC structure *** -#define SYSC_AIC_SMR ( 0) // Source Mode Register -#define SYSC_AIC_SVR (128) // Source Vector Register -#define SYSC_AIC_IVR (256) // IRQ Vector Register -#define SYSC_AIC_FVR (260) // FIQ Vector Register -#define SYSC_AIC_ISR (264) // Interrupt Status Register -#define SYSC_AIC_IPR (268) // Interrupt Pending Register -#define SYSC_AIC_IMR (272) // Interrupt Mask Register -#define SYSC_AIC_CISR (276) // Core Interrupt Status Register -#define SYSC_AIC_IECR (288) // Interrupt Enable Command Register -#define SYSC_AIC_IDCR (292) // Interrupt Disable Command Register -#define SYSC_AIC_ICCR (296) // Interrupt Clear Command Register -#define SYSC_AIC_ISCR (300) // Interrupt Set Command Register -#define SYSC_AIC_EOICR (304) // End of Interrupt Command Register -#define SYSC_AIC_SPU (308) // Spurious Vector Register -#define SYSC_AIC_DCR (312) // Debug Control Register (Protect) -#define SYSC_AIC_FFER (320) // Fast Forcing Enable Register -#define SYSC_AIC_FFDR (324) // Fast Forcing Disable Register -#define SYSC_AIC_FFSR (328) // Fast Forcing Status Register -#define SYSC_DBGU_CR (512) // Control Register -#define SYSC_DBGU_MR (516) // Mode Register -#define SYSC_DBGU_IER (520) // Interrupt Enable Register -#define SYSC_DBGU_IDR (524) // Interrupt Disable Register -#define SYSC_DBGU_IMR (528) // Interrupt Mask Register -#define SYSC_DBGU_CSR (532) // Channel Status Register -#define SYSC_DBGU_RHR (536) // Receiver Holding Register -#define SYSC_DBGU_THR (540) // Transmitter Holding Register -#define SYSC_DBGU_BRGR (544) // Baud Rate Generator Register -#define SYSC_DBGU_C1R (576) // Chip ID1 Register -#define SYSC_DBGU_C2R (580) // Chip ID2 Register -#define SYSC_DBGU_FNTR (584) // Force NTRST Register -#define SYSC_DBGU_RPR (768) // Receive Pointer Register -#define SYSC_DBGU_RCR (772) // Receive Counter Register -#define SYSC_DBGU_TPR (776) // Transmit Pointer Register -#define SYSC_DBGU_TCR (780) // Transmit Counter Register -#define SYSC_DBGU_RNPR (784) // Receive Next Pointer Register -#define SYSC_DBGU_RNCR (788) // Receive Next Counter Register -#define SYSC_DBGU_TNPR (792) // Transmit Next Pointer Register -#define SYSC_DBGU_TNCR (796) // Transmit Next Counter Register -#define SYSC_DBGU_PTCR (800) // PDC Transfer Control Register -#define SYSC_DBGU_PTSR (804) // PDC Transfer Status Register -#define SYSC_PIOA_PER (1024) // PIO Enable Register -#define SYSC_PIOA_PDR (1028) // PIO Disable Register -#define SYSC_PIOA_PSR (1032) // PIO Status Register -#define SYSC_PIOA_OER (1040) // Output Enable Register -#define SYSC_PIOA_ODR (1044) // Output Disable Registerr -#define SYSC_PIOA_OSR (1048) // Output Status Register -#define SYSC_PIOA_IFER (1056) // Input Filter Enable Register -#define SYSC_PIOA_IFDR (1060) // Input Filter Disable Register -#define SYSC_PIOA_IFSR (1064) // Input Filter Status Register -#define SYSC_PIOA_SODR (1072) // Set Output Data Register -#define SYSC_PIOA_CODR (1076) // Clear Output Data Register -#define SYSC_PIOA_ODSR (1080) // Output Data Status Register -#define SYSC_PIOA_PDSR (1084) // Pin Data Status Register -#define SYSC_PIOA_IER (1088) // Interrupt Enable Register -#define SYSC_PIOA_IDR (1092) // Interrupt Disable Register -#define SYSC_PIOA_IMR (1096) // Interrupt Mask Register -#define SYSC_PIOA_ISR (1100) // Interrupt Status Register -#define SYSC_PIOA_MDER (1104) // Multi-driver Enable Register -#define SYSC_PIOA_MDDR (1108) // Multi-driver Disable Register -#define SYSC_PIOA_MDSR (1112) // Multi-driver Status Register -#define SYSC_PIOA_PPUDR (1120) // Pull-up Disable Register -#define SYSC_PIOA_PPUER (1124) // Pull-up Enable Register -#define SYSC_PIOA_PPUSR (1128) // Pad Pull-up Status Register -#define SYSC_PIOA_ASR (1136) // Select A Register -#define SYSC_PIOA_BSR (1140) // Select B Register -#define SYSC_PIOA_ABSR (1144) // AB Select Status Register -#define SYSC_PIOA_OWER (1184) // Output Write Enable Register -#define SYSC_PIOA_OWDR (1188) // Output Write Disable Register -#define SYSC_PIOA_OWSR (1192) // Output Write Status Register -#define SYSC_PMC_SCER (3072) // System Clock Enable Register -#define SYSC_PMC_SCDR (3076) // System Clock Disable Register -#define SYSC_PMC_SCSR (3080) // System Clock Status Register -#define SYSC_PMC_PCER (3088) // Peripheral Clock Enable Register -#define SYSC_PMC_PCDR (3092) // Peripheral Clock Disable Register -#define SYSC_PMC_PCSR (3096) // Peripheral Clock Status Register -#define SYSC_PMC_MOR (3104) // Main Oscillator Register -#define SYSC_PMC_MCFR (3108) // Main Clock Frequency Register -#define SYSC_PMC_PLLR (3116) // PLL Register -#define SYSC_PMC_MCKR (3120) // Master Clock Register -#define SYSC_PMC_PCKR (3136) // Programmable Clock Register -#define SYSC_PMC_IER (3168) // Interrupt Enable Register -#define SYSC_PMC_IDR (3172) // Interrupt Disable Register -#define SYSC_PMC_SR (3176) // Status Register -#define SYSC_PMC_IMR (3180) // Interrupt Mask Register -#define SYSC_RSTC_RCR (3328) // Reset Control Register -#define SYSC_RSTC_RSR (3332) // Reset Status Register -#define SYSC_RSTC_RMR (3336) // Reset Mode Register -#define SYSC_RTTC_RTMR (3360) // Real-time Mode Register -#define SYSC_RTTC_RTAR (3364) // Real-time Alarm Register -#define SYSC_RTTC_RTVR (3368) // Real-time Value Register -#define SYSC_RTTC_RTSR (3372) // Real-time Status Register -#define SYSC_PITC_PIMR (3376) // Period Interval Mode Register -#define SYSC_PITC_PISR (3380) // Period Interval Status Register -#define SYSC_PITC_PIVR (3384) // Period Interval Value Register -#define SYSC_PITC_PIIR (3388) // Period Interval Image Register -#define SYSC_WDTC_WDCR (3392) // Watchdog Control Register -#define SYSC_WDTC_WDMR (3396) // Watchdog Mode Register -#define SYSC_WDTC_WDSR (3400) // Watchdog Status Register -#define SYSC_SYSC_VRPM (3424) // Voltage Regulator Power Mode Register -// -------- VRPM : (SYSC Offset: 0xd60) Voltage Regulator Power Mode Register -------- -#define AT91C_SYSC_PSTDBY (0x1 << 0) // (SYSC) Voltage Regulator Power Mode +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR System Peripherals */ +/* ***************************************************************************** */ +/* *** Register offset in AT91S_SYSC structure *** */ +#define SYSC_AIC_SMR ( 0 ) /* Source Mode Register */ +#define SYSC_AIC_SVR ( 128 ) /* Source Vector Register */ +#define SYSC_AIC_IVR ( 256 ) /* IRQ Vector Register */ +#define SYSC_AIC_FVR ( 260 ) /* FIQ Vector Register */ +#define SYSC_AIC_ISR ( 264 ) /* Interrupt Status Register */ +#define SYSC_AIC_IPR ( 268 ) /* Interrupt Pending Register */ +#define SYSC_AIC_IMR ( 272 ) /* Interrupt Mask Register */ +#define SYSC_AIC_CISR ( 276 ) /* Core Interrupt Status Register */ +#define SYSC_AIC_IECR ( 288 ) /* Interrupt Enable Command Register */ +#define SYSC_AIC_IDCR ( 292 ) /* Interrupt Disable Command Register */ +#define SYSC_AIC_ICCR ( 296 ) /* Interrupt Clear Command Register */ +#define SYSC_AIC_ISCR ( 300 ) /* Interrupt Set Command Register */ +#define SYSC_AIC_EOICR ( 304 ) /* End of Interrupt Command Register */ +#define SYSC_AIC_SPU ( 308 ) /* Spurious Vector Register */ +#define SYSC_AIC_DCR ( 312 ) /* Debug Control Register (Protect) */ +#define SYSC_AIC_FFER ( 320 ) /* Fast Forcing Enable Register */ +#define SYSC_AIC_FFDR ( 324 ) /* Fast Forcing Disable Register */ +#define SYSC_AIC_FFSR ( 328 ) /* Fast Forcing Status Register */ +#define SYSC_DBGU_CR ( 512 ) /* Control Register */ +#define SYSC_DBGU_MR ( 516 ) /* Mode Register */ +#define SYSC_DBGU_IER ( 520 ) /* Interrupt Enable Register */ +#define SYSC_DBGU_IDR ( 524 ) /* Interrupt Disable Register */ +#define SYSC_DBGU_IMR ( 528 ) /* Interrupt Mask Register */ +#define SYSC_DBGU_CSR ( 532 ) /* Channel Status Register */ +#define SYSC_DBGU_RHR ( 536 ) /* Receiver Holding Register */ +#define SYSC_DBGU_THR ( 540 ) /* Transmitter Holding Register */ +#define SYSC_DBGU_BRGR ( 544 ) /* Baud Rate Generator Register */ +#define SYSC_DBGU_C1R ( 576 ) /* Chip ID1 Register */ +#define SYSC_DBGU_C2R ( 580 ) /* Chip ID2 Register */ +#define SYSC_DBGU_FNTR ( 584 ) /* Force NTRST Register */ +#define SYSC_DBGU_RPR ( 768 ) /* Receive Pointer Register */ +#define SYSC_DBGU_RCR ( 772 ) /* Receive Counter Register */ +#define SYSC_DBGU_TPR ( 776 ) /* Transmit Pointer Register */ +#define SYSC_DBGU_TCR ( 780 ) /* Transmit Counter Register */ +#define SYSC_DBGU_RNPR ( 784 ) /* Receive Next Pointer Register */ +#define SYSC_DBGU_RNCR ( 788 ) /* Receive Next Counter Register */ +#define SYSC_DBGU_TNPR ( 792 ) /* Transmit Next Pointer Register */ +#define SYSC_DBGU_TNCR ( 796 ) /* Transmit Next Counter Register */ +#define SYSC_DBGU_PTCR ( 800 ) /* PDC Transfer Control Register */ +#define SYSC_DBGU_PTSR ( 804 ) /* PDC Transfer Status Register */ +#define SYSC_PIOA_PER ( 1024 ) /* PIO Enable Register */ +#define SYSC_PIOA_PDR ( 1028 ) /* PIO Disable Register */ +#define SYSC_PIOA_PSR ( 1032 ) /* PIO Status Register */ +#define SYSC_PIOA_OER ( 1040 ) /* Output Enable Register */ +#define SYSC_PIOA_ODR ( 1044 ) /* Output Disable Registerr */ +#define SYSC_PIOA_OSR ( 1048 ) /* Output Status Register */ +#define SYSC_PIOA_IFER ( 1056 ) /* Input Filter Enable Register */ +#define SYSC_PIOA_IFDR ( 1060 ) /* Input Filter Disable Register */ +#define SYSC_PIOA_IFSR ( 1064 ) /* Input Filter Status Register */ +#define SYSC_PIOA_SODR ( 1072 ) /* Set Output Data Register */ +#define SYSC_PIOA_CODR ( 1076 ) /* Clear Output Data Register */ +#define SYSC_PIOA_ODSR ( 1080 ) /* Output Data Status Register */ +#define SYSC_PIOA_PDSR ( 1084 ) /* Pin Data Status Register */ +#define SYSC_PIOA_IER ( 1088 ) /* Interrupt Enable Register */ +#define SYSC_PIOA_IDR ( 1092 ) /* Interrupt Disable Register */ +#define SYSC_PIOA_IMR ( 1096 ) /* Interrupt Mask Register */ +#define SYSC_PIOA_ISR ( 1100 ) /* Interrupt Status Register */ +#define SYSC_PIOA_MDER ( 1104 ) /* Multi-driver Enable Register */ +#define SYSC_PIOA_MDDR ( 1108 ) /* Multi-driver Disable Register */ +#define SYSC_PIOA_MDSR ( 1112 ) /* Multi-driver Status Register */ +#define SYSC_PIOA_PPUDR ( 1120 ) /* Pull-up Disable Register */ +#define SYSC_PIOA_PPUER ( 1124 ) /* Pull-up Enable Register */ +#define SYSC_PIOA_PPUSR ( 1128 ) /* Pad Pull-up Status Register */ +#define SYSC_PIOA_ASR ( 1136 ) /* Select A Register */ +#define SYSC_PIOA_BSR ( 1140 ) /* Select B Register */ +#define SYSC_PIOA_ABSR ( 1144 ) /* AB Select Status Register */ +#define SYSC_PIOA_OWER ( 1184 ) /* Output Write Enable Register */ +#define SYSC_PIOA_OWDR ( 1188 ) /* Output Write Disable Register */ +#define SYSC_PIOA_OWSR ( 1192 ) /* Output Write Status Register */ +#define SYSC_PMC_SCER ( 3072 ) /* System Clock Enable Register */ +#define SYSC_PMC_SCDR ( 3076 ) /* System Clock Disable Register */ +#define SYSC_PMC_SCSR ( 3080 ) /* System Clock Status Register */ +#define SYSC_PMC_PCER ( 3088 ) /* Peripheral Clock Enable Register */ +#define SYSC_PMC_PCDR ( 3092 ) /* Peripheral Clock Disable Register */ +#define SYSC_PMC_PCSR ( 3096 ) /* Peripheral Clock Status Register */ +#define SYSC_PMC_MOR ( 3104 ) /* Main Oscillator Register */ +#define SYSC_PMC_MCFR ( 3108 ) /* Main Clock Frequency Register */ +#define SYSC_PMC_PLLR ( 3116 ) /* PLL Register */ +#define SYSC_PMC_MCKR ( 3120 ) /* Master Clock Register */ +#define SYSC_PMC_PCKR ( 3136 ) /* Programmable Clock Register */ +#define SYSC_PMC_IER ( 3168 ) /* Interrupt Enable Register */ +#define SYSC_PMC_IDR ( 3172 ) /* Interrupt Disable Register */ +#define SYSC_PMC_SR ( 3176 ) /* Status Register */ +#define SYSC_PMC_IMR ( 3180 ) /* Interrupt Mask Register */ +#define SYSC_RSTC_RCR ( 3328 ) /* Reset Control Register */ +#define SYSC_RSTC_RSR ( 3332 ) /* Reset Status Register */ +#define SYSC_RSTC_RMR ( 3336 ) /* Reset Mode Register */ +#define SYSC_RTTC_RTMR ( 3360 ) /* Real-time Mode Register */ +#define SYSC_RTTC_RTAR ( 3364 ) /* Real-time Alarm Register */ +#define SYSC_RTTC_RTVR ( 3368 ) /* Real-time Value Register */ +#define SYSC_RTTC_RTSR ( 3372 ) /* Real-time Status Register */ +#define SYSC_PITC_PIMR ( 3376 ) /* Period Interval Mode Register */ +#define SYSC_PITC_PISR ( 3380 ) /* Period Interval Status Register */ +#define SYSC_PITC_PIVR ( 3384 ) /* Period Interval Value Register */ +#define SYSC_PITC_PIIR ( 3388 ) /* Period Interval Image Register */ +#define SYSC_WDTC_WDCR ( 3392 ) /* Watchdog Control Register */ +#define SYSC_WDTC_WDMR ( 3396 ) /* Watchdog Mode Register */ +#define SYSC_WDTC_WDSR ( 3400 ) /* Watchdog Status Register */ +#define SYSC_SYSC_VRPM ( 3424 ) /* Voltage Regulator Power Mode Register */ +/* -------- VRPM : (SYSC Offset: 0xd60) Voltage Regulator Power Mode Register -------- */ +#define AT91C_SYSC_PSTDBY ( 0x1 << 0 ) /* (SYSC) Voltage Regulator Power Mode */ -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Advanced Interrupt Controller -// ***************************************************************************** -// *** Register offset in AT91S_AIC structure *** -#define AIC_SMR ( 0) // Source Mode Register -#define AIC_SVR (128) // Source Vector Register -#define AIC_IVR (256) // IRQ Vector Register -#define AIC_FVR (260) // FIQ Vector Register -#define AIC_ISR (264) // Interrupt Status Register -#define AIC_IPR (268) // Interrupt Pending Register -#define AIC_IMR (272) // Interrupt Mask Register -#define AIC_CISR (276) // Core Interrupt Status Register -#define AIC_IECR (288) // Interrupt Enable Command Register -#define AIC_IDCR (292) // Interrupt Disable Command Register -#define AIC_ICCR (296) // Interrupt Clear Command Register -#define AIC_ISCR (300) // Interrupt Set Command Register -#define AIC_EOICR (304) // End of Interrupt Command Register -#define AIC_SPU (308) // Spurious Vector Register -#define AIC_DCR (312) // Debug Control Register (Protect) -#define AIC_FFER (320) // Fast Forcing Enable Register -#define AIC_FFDR (324) // Fast Forcing Disable Register -#define AIC_FFSR (328) // Fast Forcing Status Register -// -------- AIC_SMR : (AIC Offset: 0x0) Control Register -------- -#define AT91C_AIC_PRIOR (0x7 << 0) // (AIC) Priority Level -#define AT91C_AIC_PRIOR_LOWEST (0x0) // (AIC) Lowest priority level -#define AT91C_AIC_PRIOR_HIGHEST (0x7) // (AIC) Highest priority level -#define AT91C_AIC_SRCTYPE (0x3 << 5) // (AIC) Interrupt Source Type -#define AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE (0x0 << 5) // (AIC) Internal Sources Code Label Level Sensitive -#define AT91C_AIC_SRCTYPE_INT_EDGE_TRIGGERED (0x1 << 5) // (AIC) Internal Sources Code Label Edge triggered -#define AT91C_AIC_SRCTYPE_EXT_HIGH_LEVEL (0x2 << 5) // (AIC) External Sources Code Label High-level Sensitive -#define AT91C_AIC_SRCTYPE_EXT_POSITIVE_EDGE (0x3 << 5) // (AIC) External Sources Code Label Positive Edge triggered -// -------- AIC_CISR : (AIC Offset: 0x114) AIC Core Interrupt Status Register -------- -#define AT91C_AIC_NFIQ (0x1 << 0) // (AIC) NFIQ Status -#define AT91C_AIC_NIRQ (0x1 << 1) // (AIC) NIRQ Status -// -------- AIC_DCR : (AIC Offset: 0x138) AIC Debug Control Register (Protect) -------- -#define AT91C_AIC_DCR_PROT (0x1 << 0) // (AIC) Protection Mode -#define AT91C_AIC_DCR_GMSK (0x1 << 1) // (AIC) General Mask +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR Advanced Interrupt Controller */ +/* ***************************************************************************** */ +/* *** Register offset in AT91S_AIC structure *** */ +#define AIC_SMR ( 0 ) /* Source Mode Register */ +#define AIC_SVR ( 128 ) /* Source Vector Register */ +#define AIC_IVR ( 256 ) /* IRQ Vector Register */ +#define AIC_FVR ( 260 ) /* FIQ Vector Register */ +#define AIC_ISR ( 264 ) /* Interrupt Status Register */ +#define AIC_IPR ( 268 ) /* Interrupt Pending Register */ +#define AIC_IMR ( 272 ) /* Interrupt Mask Register */ +#define AIC_CISR ( 276 ) /* Core Interrupt Status Register */ +#define AIC_IECR ( 288 ) /* Interrupt Enable Command Register */ +#define AIC_IDCR ( 292 ) /* Interrupt Disable Command Register */ +#define AIC_ICCR ( 296 ) /* Interrupt Clear Command Register */ +#define AIC_ISCR ( 300 ) /* Interrupt Set Command Register */ +#define AIC_EOICR ( 304 ) /* End of Interrupt Command Register */ +#define AIC_SPU ( 308 ) /* Spurious Vector Register */ +#define AIC_DCR ( 312 ) /* Debug Control Register (Protect) */ +#define AIC_FFER ( 320 ) /* Fast Forcing Enable Register */ +#define AIC_FFDR ( 324 ) /* Fast Forcing Disable Register */ +#define AIC_FFSR ( 328 ) /* Fast Forcing Status Register */ +/* -------- AIC_SMR : (AIC Offset: 0x0) Control Register -------- */ +#define AT91C_AIC_PRIOR ( 0x7 << 0 ) /* (AIC) Priority Level */ +#define AT91C_AIC_PRIOR_LOWEST ( 0x0 ) /* (AIC) Lowest priority level */ +#define AT91C_AIC_PRIOR_HIGHEST ( 0x7 ) /* (AIC) Highest priority level */ +#define AT91C_AIC_SRCTYPE ( 0x3 << 5 ) /* (AIC) Interrupt Source Type */ +#define AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE ( 0x0 << 5 ) /* (AIC) Internal Sources Code Label Level Sensitive */ +#define AT91C_AIC_SRCTYPE_INT_EDGE_TRIGGERED ( 0x1 << 5 ) /* (AIC) Internal Sources Code Label Edge triggered */ +#define AT91C_AIC_SRCTYPE_EXT_HIGH_LEVEL ( 0x2 << 5 ) /* (AIC) External Sources Code Label High-level Sensitive */ +#define AT91C_AIC_SRCTYPE_EXT_POSITIVE_EDGE ( 0x3 << 5 ) /* (AIC) External Sources Code Label Positive Edge triggered */ +/* -------- AIC_CISR : (AIC Offset: 0x114) AIC Core Interrupt Status Register -------- */ +#define AT91C_AIC_NFIQ ( 0x1 << 0 ) /* (AIC) NFIQ Status */ +#define AT91C_AIC_NIRQ ( 0x1 << 1 ) /* (AIC) NIRQ Status */ +/* -------- AIC_DCR : (AIC Offset: 0x138) AIC Debug Control Register (Protect) -------- */ +#define AT91C_AIC_DCR_PROT ( 0x1 << 0 ) /* (AIC) Protection Mode */ +#define AT91C_AIC_DCR_GMSK ( 0x1 << 1 ) /* (AIC) General Mask */ -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Debug Unit -// ***************************************************************************** -// *** Register offset in AT91S_DBGU structure *** -#define DBGU_CR ( 0) // Control Register -#define DBGU_MR ( 4) // Mode Register -#define DBGU_IER ( 8) // Interrupt Enable Register -#define DBGU_IDR (12) // Interrupt Disable Register -#define DBGU_IMR (16) // Interrupt Mask Register -#define DBGU_CSR (20) // Channel Status Register -#define DBGU_RHR (24) // Receiver Holding Register -#define DBGU_THR (28) // Transmitter Holding Register -#define DBGU_BRGR (32) // Baud Rate Generator Register -#define DBGU_C1R (64) // Chip ID1 Register -#define DBGU_C2R (68) // Chip ID2 Register -#define DBGU_FNTR (72) // Force NTRST Register -#define DBGU_RPR (256) // Receive Pointer Register -#define DBGU_RCR (260) // Receive Counter Register -#define DBGU_TPR (264) // Transmit Pointer Register -#define DBGU_TCR (268) // Transmit Counter Register -#define DBGU_RNPR (272) // Receive Next Pointer Register -#define DBGU_RNCR (276) // Receive Next Counter Register -#define DBGU_TNPR (280) // Transmit Next Pointer Register -#define DBGU_TNCR (284) // Transmit Next Counter Register -#define DBGU_PTCR (288) // PDC Transfer Control Register -#define DBGU_PTSR (292) // PDC Transfer Status Register -// -------- DBGU_CR : (DBGU Offset: 0x0) Debug Unit Control Register -------- -#define AT91C_US_RSTRX (0x1 << 2) // (DBGU) Reset Receiver -#define AT91C_US_RSTTX (0x1 << 3) // (DBGU) Reset Transmitter -#define AT91C_US_RXEN (0x1 << 4) // (DBGU) Receiver Enable -#define AT91C_US_RXDIS (0x1 << 5) // (DBGU) Receiver Disable -#define AT91C_US_TXEN (0x1 << 6) // (DBGU) Transmitter Enable -#define AT91C_US_TXDIS (0x1 << 7) // (DBGU) Transmitter Disable -// -------- DBGU_MR : (DBGU Offset: 0x4) Debug Unit Mode Register -------- -#define AT91C_US_PAR (0x7 << 9) // (DBGU) Parity type -#define AT91C_US_PAR_EVEN (0x0 << 9) // (DBGU) Even Parity -#define AT91C_US_PAR_ODD (0x1 << 9) // (DBGU) Odd Parity -#define AT91C_US_PAR_SPACE (0x2 << 9) // (DBGU) Parity forced to 0 (Space) -#define AT91C_US_PAR_MARK (0x3 << 9) // (DBGU) Parity forced to 1 (Mark) -#define AT91C_US_PAR_NONE (0x4 << 9) // (DBGU) No Parity -#define AT91C_US_PAR_MULTI_DROP (0x6 << 9) // (DBGU) Multi-drop mode -#define AT91C_US_CHMODE (0x3 << 14) // (DBGU) Channel Mode -#define AT91C_US_CHMODE_NORMAL (0x0 << 14) // (DBGU) Normal Mode: The USART channel operates as an RX/TX USART. -#define AT91C_US_CHMODE_AUTO (0x1 << 14) // (DBGU) Automatic Echo: Receiver Data Input is connected to the TXD pin. -#define AT91C_US_CHMODE_LOCAL (0x2 << 14) // (DBGU) Local Loopback: Transmitter Output Signal is connected to Receiver Input Signal. -#define AT91C_US_CHMODE_REMOTE (0x3 << 14) // (DBGU) Remote Loopback: RXD pin is internally connected to TXD pin. -// -------- DBGU_IER : (DBGU Offset: 0x8) Debug Unit Interrupt Enable Register -------- -#define AT91C_US_RXRDY (0x1 << 0) // (DBGU) RXRDY Interrupt -#define AT91C_US_TXRDY (0x1 << 1) // (DBGU) TXRDY Interrupt -#define AT91C_US_ENDRX (0x1 << 3) // (DBGU) End of Receive Transfer Interrupt -#define AT91C_US_ENDTX (0x1 << 4) // (DBGU) End of Transmit Interrupt -#define AT91C_US_OVRE (0x1 << 5) // (DBGU) Overrun Interrupt -#define AT91C_US_FRAME (0x1 << 6) // (DBGU) Framing Error Interrupt -#define AT91C_US_PARE (0x1 << 7) // (DBGU) Parity Error Interrupt -#define AT91C_US_TXEMPTY (0x1 << 9) // (DBGU) TXEMPTY Interrupt -#define AT91C_US_TXBUFE (0x1 << 11) // (DBGU) TXBUFE Interrupt -#define AT91C_US_RXBUFF (0x1 << 12) // (DBGU) RXBUFF Interrupt -#define AT91C_US_COMM_TX (0x1 << 30) // (DBGU) COMM_TX Interrupt -#define AT91C_US_COMM_RX (0x1 << 31) // (DBGU) COMM_RX Interrupt -// -------- DBGU_IDR : (DBGU Offset: 0xc) Debug Unit Interrupt Disable Register -------- -// -------- DBGU_IMR : (DBGU Offset: 0x10) Debug Unit Interrupt Mask Register -------- -// -------- DBGU_CSR : (DBGU Offset: 0x14) Debug Unit Channel Status Register -------- -// -------- DBGU_FNTR : (DBGU Offset: 0x48) Debug Unit FORCE_NTRST Register -------- -#define AT91C_US_FORCE_NTRST (0x1 << 0) // (DBGU) Force NTRST in JTAG +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR Debug Unit */ +/* ***************************************************************************** */ +/* *** Register offset in AT91S_DBGU structure *** */ +#define DBGU_CR ( 0 ) /* Control Register */ +#define DBGU_MR ( 4 ) /* Mode Register */ +#define DBGU_IER ( 8 ) /* Interrupt Enable Register */ +#define DBGU_IDR ( 12 ) /* Interrupt Disable Register */ +#define DBGU_IMR ( 16 ) /* Interrupt Mask Register */ +#define DBGU_CSR ( 20 ) /* Channel Status Register */ +#define DBGU_RHR ( 24 ) /* Receiver Holding Register */ +#define DBGU_THR ( 28 ) /* Transmitter Holding Register */ +#define DBGU_BRGR ( 32 ) /* Baud Rate Generator Register */ +#define DBGU_C1R ( 64 ) /* Chip ID1 Register */ +#define DBGU_C2R ( 68 ) /* Chip ID2 Register */ +#define DBGU_FNTR ( 72 ) /* Force NTRST Register */ +#define DBGU_RPR ( 256 ) /* Receive Pointer Register */ +#define DBGU_RCR ( 260 ) /* Receive Counter Register */ +#define DBGU_TPR ( 264 ) /* Transmit Pointer Register */ +#define DBGU_TCR ( 268 ) /* Transmit Counter Register */ +#define DBGU_RNPR ( 272 ) /* Receive Next Pointer Register */ +#define DBGU_RNCR ( 276 ) /* Receive Next Counter Register */ +#define DBGU_TNPR ( 280 ) /* Transmit Next Pointer Register */ +#define DBGU_TNCR ( 284 ) /* Transmit Next Counter Register */ +#define DBGU_PTCR ( 288 ) /* PDC Transfer Control Register */ +#define DBGU_PTSR ( 292 ) /* PDC Transfer Status Register */ +/* -------- DBGU_CR : (DBGU Offset: 0x0) Debug Unit Control Register -------- */ +#define AT91C_US_RSTRX ( 0x1 << 2 ) /* (DBGU) Reset Receiver */ +#define AT91C_US_RSTTX ( 0x1 << 3 ) /* (DBGU) Reset Transmitter */ +#define AT91C_US_RXEN ( 0x1 << 4 ) /* (DBGU) Receiver Enable */ +#define AT91C_US_RXDIS ( 0x1 << 5 ) /* (DBGU) Receiver Disable */ +#define AT91C_US_TXEN ( 0x1 << 6 ) /* (DBGU) Transmitter Enable */ +#define AT91C_US_TXDIS ( 0x1 << 7 ) /* (DBGU) Transmitter Disable */ +/* -------- DBGU_MR : (DBGU Offset: 0x4) Debug Unit Mode Register -------- */ +#define AT91C_US_PAR ( 0x7 << 9 ) /* (DBGU) Parity type */ +#define AT91C_US_PAR_EVEN ( 0x0 << 9 ) /* (DBGU) Even Parity */ +#define AT91C_US_PAR_ODD ( 0x1 << 9 ) /* (DBGU) Odd Parity */ +#define AT91C_US_PAR_SPACE ( 0x2 << 9 ) /* (DBGU) Parity forced to 0 (Space) */ +#define AT91C_US_PAR_MARK ( 0x3 << 9 ) /* (DBGU) Parity forced to 1 (Mark) */ +#define AT91C_US_PAR_NONE ( 0x4 << 9 ) /* (DBGU) No Parity */ +#define AT91C_US_PAR_MULTI_DROP ( 0x6 << 9 ) /* (DBGU) Multi-drop mode */ +#define AT91C_US_CHMODE ( 0x3 << 14 ) /* (DBGU) Channel Mode */ +#define AT91C_US_CHMODE_NORMAL ( 0x0 << 14 ) /* (DBGU) Normal Mode: The USART channel operates as an RX/TX USART. */ +#define AT91C_US_CHMODE_AUTO ( 0x1 << 14 ) /* (DBGU) Automatic Echo: Receiver Data Input is connected to the TXD pin. */ +#define AT91C_US_CHMODE_LOCAL ( 0x2 << 14 ) /* (DBGU) Local Loopback: Transmitter Output Signal is connected to Receiver Input Signal. */ +#define AT91C_US_CHMODE_REMOTE ( 0x3 << 14 ) /* (DBGU) Remote Loopback: RXD pin is internally connected to TXD pin. */ +/* -------- DBGU_IER : (DBGU Offset: 0x8) Debug Unit Interrupt Enable Register -------- */ +#define AT91C_US_RXRDY ( 0x1 << 0 ) /* (DBGU) RXRDY Interrupt */ +#define AT91C_US_TXRDY ( 0x1 << 1 ) /* (DBGU) TXRDY Interrupt */ +#define AT91C_US_ENDRX ( 0x1 << 3 ) /* (DBGU) End of Receive Transfer Interrupt */ +#define AT91C_US_ENDTX ( 0x1 << 4 ) /* (DBGU) End of Transmit Interrupt */ +#define AT91C_US_OVRE ( 0x1 << 5 ) /* (DBGU) Overrun Interrupt */ +#define AT91C_US_FRAME ( 0x1 << 6 ) /* (DBGU) Framing Error Interrupt */ +#define AT91C_US_PARE ( 0x1 << 7 ) /* (DBGU) Parity Error Interrupt */ +#define AT91C_US_TXEMPTY ( 0x1 << 9 ) /* (DBGU) TXEMPTY Interrupt */ +#define AT91C_US_TXBUFE ( 0x1 << 11 ) /* (DBGU) TXBUFE Interrupt */ +#define AT91C_US_RXBUFF ( 0x1 << 12 ) /* (DBGU) RXBUFF Interrupt */ +#define AT91C_US_COMM_TX ( 0x1 << 30 ) /* (DBGU) COMM_TX Interrupt */ +#define AT91C_US_COMM_RX ( 0x1 << 31 ) /* (DBGU) COMM_RX Interrupt */ +/* -------- DBGU_IDR : (DBGU Offset: 0xc) Debug Unit Interrupt Disable Register -------- */ +/* -------- DBGU_IMR : (DBGU Offset: 0x10) Debug Unit Interrupt Mask Register -------- */ +/* -------- DBGU_CSR : (DBGU Offset: 0x14) Debug Unit Channel Status Register -------- */ +/* -------- DBGU_FNTR : (DBGU Offset: 0x48) Debug Unit FORCE_NTRST Register -------- */ +#define AT91C_US_FORCE_NTRST ( 0x1 << 0 ) /* (DBGU) Force NTRST in JTAG */ -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Peripheral Data Controller -// ***************************************************************************** -// *** Register offset in AT91S_PDC structure *** -#define PDC_RPR ( 0) // Receive Pointer Register -#define PDC_RCR ( 4) // Receive Counter Register -#define PDC_TPR ( 8) // Transmit Pointer Register -#define PDC_TCR (12) // Transmit Counter Register -#define PDC_RNPR (16) // Receive Next Pointer Register -#define PDC_RNCR (20) // Receive Next Counter Register -#define PDC_TNPR (24) // Transmit Next Pointer Register -#define PDC_TNCR (28) // Transmit Next Counter Register -#define PDC_PTCR (32) // PDC Transfer Control Register -#define PDC_PTSR (36) // PDC Transfer Status Register -// -------- PDC_PTCR : (PDC Offset: 0x20) PDC Transfer Control Register -------- -#define AT91C_PDC_RXTEN (0x1 << 0) // (PDC) Receiver Transfer Enable -#define AT91C_PDC_RXTDIS (0x1 << 1) // (PDC) Receiver Transfer Disable -#define AT91C_PDC_TXTEN (0x1 << 8) // (PDC) Transmitter Transfer Enable -#define AT91C_PDC_TXTDIS (0x1 << 9) // (PDC) Transmitter Transfer Disable -// -------- PDC_PTSR : (PDC Offset: 0x24) PDC Transfer Status Register -------- +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR Peripheral Data Controller */ +/* ***************************************************************************** */ +/* *** Register offset in AT91S_PDC structure *** */ +#define PDC_RPR ( 0 ) /* Receive Pointer Register */ +#define PDC_RCR ( 4 ) /* Receive Counter Register */ +#define PDC_TPR ( 8 ) /* Transmit Pointer Register */ +#define PDC_TCR ( 12 ) /* Transmit Counter Register */ +#define PDC_RNPR ( 16 ) /* Receive Next Pointer Register */ +#define PDC_RNCR ( 20 ) /* Receive Next Counter Register */ +#define PDC_TNPR ( 24 ) /* Transmit Next Pointer Register */ +#define PDC_TNCR ( 28 ) /* Transmit Next Counter Register */ +#define PDC_PTCR ( 32 ) /* PDC Transfer Control Register */ +#define PDC_PTSR ( 36 ) /* PDC Transfer Status Register */ +/* -------- PDC_PTCR : (PDC Offset: 0x20) PDC Transfer Control Register -------- */ +#define AT91C_PDC_RXTEN ( 0x1 << 0 ) /* (PDC) Receiver Transfer Enable */ +#define AT91C_PDC_RXTDIS ( 0x1 << 1 ) /* (PDC) Receiver Transfer Disable */ +#define AT91C_PDC_TXTEN ( 0x1 << 8 ) /* (PDC) Transmitter Transfer Enable */ +#define AT91C_PDC_TXTDIS ( 0x1 << 9 ) /* (PDC) Transmitter Transfer Disable */ +/* -------- PDC_PTSR : (PDC Offset: 0x24) PDC Transfer Status Register -------- */ -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Parallel Input Output Controler -// ***************************************************************************** -// *** Register offset in AT91S_PIO structure *** -#define PIO_PER ( 0) // PIO Enable Register -#define PIO_PDR ( 4) // PIO Disable Register -#define PIO_PSR ( 8) // PIO Status Register -#define PIO_OER (16) // Output Enable Register -#define PIO_ODR (20) // Output Disable Registerr -#define PIO_OSR (24) // Output Status Register -#define PIO_IFER (32) // Input Filter Enable Register -#define PIO_IFDR (36) // Input Filter Disable Register -#define PIO_IFSR (40) // Input Filter Status Register -#define PIO_SODR (48) // Set Output Data Register -#define PIO_CODR (52) // Clear Output Data Register -#define PIO_ODSR (56) // Output Data Status Register -#define PIO_PDSR (60) // Pin Data Status Register -#define PIO_IER (64) // Interrupt Enable Register -#define PIO_IDR (68) // Interrupt Disable Register -#define PIO_IMR (72) // Interrupt Mask Register -#define PIO_ISR (76) // Interrupt Status Register -#define PIO_MDER (80) // Multi-driver Enable Register -#define PIO_MDDR (84) // Multi-driver Disable Register -#define PIO_MDSR (88) // Multi-driver Status Register -#define PIO_PPUDR (96) // Pull-up Disable Register -#define PIO_PPUER (100) // Pull-up Enable Register -#define PIO_PPUSR (104) // Pad Pull-up Status Register -#define PIO_ASR (112) // Select A Register -#define PIO_BSR (116) // Select B Register -#define PIO_ABSR (120) // AB Select Status Register -#define PIO_OWER (160) // Output Write Enable Register -#define PIO_OWDR (164) // Output Write Disable Register -#define PIO_OWSR (168) // Output Write Status Register +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR Parallel Input Output Controller */ +/* ***************************************************************************** */ +/* *** Register offset in AT91S_PIO structure *** */ +#define PIO_PER ( 0 ) /* PIO Enable Register */ +#define PIO_PDR ( 4 ) /* PIO Disable Register */ +#define PIO_PSR ( 8 ) /* PIO Status Register */ +#define PIO_OER ( 16 ) /* Output Enable Register */ +#define PIO_ODR ( 20 ) /* Output Disable Registerr */ +#define PIO_OSR ( 24 ) /* Output Status Register */ +#define PIO_IFER ( 32 ) /* Input Filter Enable Register */ +#define PIO_IFDR ( 36 ) /* Input Filter Disable Register */ +#define PIO_IFSR ( 40 ) /* Input Filter Status Register */ +#define PIO_SODR ( 48 ) /* Set Output Data Register */ +#define PIO_CODR ( 52 ) /* Clear Output Data Register */ +#define PIO_ODSR ( 56 ) /* Output Data Status Register */ +#define PIO_PDSR ( 60 ) /* Pin Data Status Register */ +#define PIO_IER ( 64 ) /* Interrupt Enable Register */ +#define PIO_IDR ( 68 ) /* Interrupt Disable Register */ +#define PIO_IMR ( 72 ) /* Interrupt Mask Register */ +#define PIO_ISR ( 76 ) /* Interrupt Status Register */ +#define PIO_MDER ( 80 ) /* Multi-driver Enable Register */ +#define PIO_MDDR ( 84 ) /* Multi-driver Disable Register */ +#define PIO_MDSR ( 88 ) /* Multi-driver Status Register */ +#define PIO_PPUDR ( 96 ) /* Pull-up Disable Register */ +#define PIO_PPUER ( 100 ) /* Pull-up Enable Register */ +#define PIO_PPUSR ( 104 ) /* Pad Pull-up Status Register */ +#define PIO_ASR ( 112 ) /* Select A Register */ +#define PIO_BSR ( 116 ) /* Select B Register */ +#define PIO_ABSR ( 120 ) /* AB Select Status Register */ +#define PIO_OWER ( 160 ) /* Output Write Enable Register */ +#define PIO_OWDR ( 164 ) /* Output Write Disable Register */ +#define PIO_OWSR ( 168 ) /* Output Write Status Register */ -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Clock Generator Controler -// ***************************************************************************** -// *** Register offset in AT91S_CKGR structure *** -#define CKGR_MOR ( 0) // Main Oscillator Register -#define CKGR_MCFR ( 4) // Main Clock Frequency Register -#define CKGR_PLLR (12) // PLL Register -// -------- CKGR_MOR : (CKGR Offset: 0x0) Main Oscillator Register -------- -#define AT91C_CKGR_MOSCEN (0x1 << 0) // (CKGR) Main Oscillator Enable -#define AT91C_CKGR_OSCBYPASS (0x1 << 1) // (CKGR) Main Oscillator Bypass -#define AT91C_CKGR_OSCOUNT (0xFF << 8) // (CKGR) Main Oscillator Start-up Time -// -------- CKGR_MCFR : (CKGR Offset: 0x4) Main Clock Frequency Register -------- -#define AT91C_CKGR_MAINF (0xFFFF << 0) // (CKGR) Main Clock Frequency -#define AT91C_CKGR_MAINRDY (0x1 << 16) // (CKGR) Main Clock Ready -// -------- CKGR_PLLR : (CKGR Offset: 0xc) PLL B Register -------- -#define AT91C_CKGR_DIV (0xFF << 0) // (CKGR) Divider Selected -#define AT91C_CKGR_DIV_0 (0x0) // (CKGR) Divider output is 0 -#define AT91C_CKGR_DIV_BYPASS (0x1) // (CKGR) Divider is bypassed -#define AT91C_CKGR_PLLCOUNT (0x3F << 8) // (CKGR) PLL Counter -#define AT91C_CKGR_OUT (0x3 << 14) // (CKGR) PLL Output Frequency Range -#define AT91C_CKGR_OUT_0 (0x0 << 14) // (CKGR) Please refer to the PLL datasheet -#define AT91C_CKGR_OUT_1 (0x1 << 14) // (CKGR) Please refer to the PLL datasheet -#define AT91C_CKGR_OUT_2 (0x2 << 14) // (CKGR) Please refer to the PLL datasheet -#define AT91C_CKGR_OUT_3 (0x3 << 14) // (CKGR) Please refer to the PLL datasheet -#define AT91C_CKGR_MUL (0x7FF << 16) // (CKGR) PLL Multiplier -#define AT91C_CKGR_USBDIV (0x3 << 28) // (CKGR) Divider for USB Clocks -#define AT91C_CKGR_USBDIV_0 (0x0 << 28) // (CKGR) Divider output is PLL clock output -#define AT91C_CKGR_USBDIV_1 (0x1 << 28) // (CKGR) Divider output is PLL clock output divided by 2 -#define AT91C_CKGR_USBDIV_2 (0x2 << 28) // (CKGR) Divider output is PLL clock output divided by 4 +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR Clock Generator Controller */ +/* ***************************************************************************** */ +/* *** Register offset in AT91S_CKGR structure *** */ +#define CKGR_MOR ( 0 ) /* Main Oscillator Register */ +#define CKGR_MCFR ( 4 ) /* Main Clock Frequency Register */ +#define CKGR_PLLR ( 12 ) /* PLL Register */ +/* -------- CKGR_MOR : (CKGR Offset: 0x0) Main Oscillator Register -------- */ +#define AT91C_CKGR_MOSCEN ( 0x1 << 0 ) /* (CKGR) Main Oscillator Enable */ +#define AT91C_CKGR_OSCBYPASS ( 0x1 << 1 ) /* (CKGR) Main Oscillator Bypass */ +#define AT91C_CKGR_OSCOUNT ( 0xFF << 8 ) /* (CKGR) Main Oscillator Start-up Time */ +/* -------- CKGR_MCFR : (CKGR Offset: 0x4) Main Clock Frequency Register -------- */ +#define AT91C_CKGR_MAINF ( 0xFFFF << 0 ) /* (CKGR) Main Clock Frequency */ +#define AT91C_CKGR_MAINRDY ( 0x1 << 16 ) /* (CKGR) Main Clock Ready */ +/* -------- CKGR_PLLR : (CKGR Offset: 0xc) PLL B Register -------- */ +#define AT91C_CKGR_DIV ( 0xFF << 0 ) /* (CKGR) Divider Selected */ +#define AT91C_CKGR_DIV_0 ( 0x0 ) /* (CKGR) Divider output is 0 */ +#define AT91C_CKGR_DIV_BYPASS ( 0x1 ) /* (CKGR) Divider is bypassed */ +#define AT91C_CKGR_PLLCOUNT ( 0x3F << 8 ) /* (CKGR) PLL Counter */ +#define AT91C_CKGR_OUT ( 0x3 << 14 ) /* (CKGR) PLL Output Frequency Range */ +#define AT91C_CKGR_OUT_0 ( 0x0 << 14 ) /* (CKGR) Please refer to the PLL datasheet */ +#define AT91C_CKGR_OUT_1 ( 0x1 << 14 ) /* (CKGR) Please refer to the PLL datasheet */ +#define AT91C_CKGR_OUT_2 ( 0x2 << 14 ) /* (CKGR) Please refer to the PLL datasheet */ +#define AT91C_CKGR_OUT_3 ( 0x3 << 14 ) /* (CKGR) Please refer to the PLL datasheet */ +#define AT91C_CKGR_MUL ( 0x7FF << 16 ) /* (CKGR) PLL Multiplier */ +#define AT91C_CKGR_USBDIV ( 0x3 << 28 ) /* (CKGR) Divider for USB Clocks */ +#define AT91C_CKGR_USBDIV_0 ( 0x0 << 28 ) /* (CKGR) Divider output is PLL clock output */ +#define AT91C_CKGR_USBDIV_1 ( 0x1 << 28 ) /* (CKGR) Divider output is PLL clock output divided by 2 */ +#define AT91C_CKGR_USBDIV_2 ( 0x2 << 28 ) /* (CKGR) Divider output is PLL clock output divided by 4 */ -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Power Management Controler -// ***************************************************************************** -// *** Register offset in AT91S_PMC structure *** -#define PMC_SCER ( 0) // System Clock Enable Register -#define PMC_SCDR ( 4) // System Clock Disable Register -#define PMC_SCSR ( 8) // System Clock Status Register -#define PMC_PCER (16) // Peripheral Clock Enable Register -#define PMC_PCDR (20) // Peripheral Clock Disable Register -#define PMC_PCSR (24) // Peripheral Clock Status Register -#define PMC_MOR (32) // Main Oscillator Register -#define PMC_MCFR (36) // Main Clock Frequency Register -#define PMC_PLLR (44) // PLL Register -#define PMC_MCKR (48) // Master Clock Register -#define PMC_PCKR (64) // Programmable Clock Register -#define PMC_IER (96) // Interrupt Enable Register -#define PMC_IDR (100) // Interrupt Disable Register -#define PMC_SR (104) // Status Register -#define PMC_IMR (108) // Interrupt Mask Register -// -------- PMC_SCER : (PMC Offset: 0x0) System Clock Enable Register -------- -#define AT91C_PMC_PCK (0x1 << 0) // (PMC) Processor Clock -#define AT91C_PMC_UDP (0x1 << 7) // (PMC) USB Device Port Clock -#define AT91C_PMC_PCK0 (0x1 << 8) // (PMC) Programmable Clock Output -#define AT91C_PMC_PCK1 (0x1 << 9) // (PMC) Programmable Clock Output -#define AT91C_PMC_PCK2 (0x1 << 10) // (PMC) Programmable Clock Output -#define AT91C_PMC_PCK3 (0x1 << 11) // (PMC) Programmable Clock Output -// -------- PMC_SCDR : (PMC Offset: 0x4) System Clock Disable Register -------- -// -------- PMC_SCSR : (PMC Offset: 0x8) System Clock Status Register -------- -// -------- CKGR_MOR : (PMC Offset: 0x20) Main Oscillator Register -------- -// -------- CKGR_MCFR : (PMC Offset: 0x24) Main Clock Frequency Register -------- -// -------- CKGR_PLLR : (PMC Offset: 0x2c) PLL B Register -------- -// -------- PMC_MCKR : (PMC Offset: 0x30) Master Clock Register -------- -#define AT91C_PMC_CSS (0x3 << 0) // (PMC) Programmable Clock Selection -#define AT91C_PMC_CSS_SLOW_CLK (0x0) // (PMC) Slow Clock is selected -#define AT91C_PMC_CSS_MAIN_CLK (0x1) // (PMC) Main Clock is selected -#define AT91C_PMC_CSS_PLL_CLK (0x3) // (PMC) Clock from PLL is selected -#define AT91C_PMC_PRES (0x7 << 2) // (PMC) Programmable Clock Prescaler -#define AT91C_PMC_PRES_CLK (0x0 << 2) // (PMC) Selected clock -#define AT91C_PMC_PRES_CLK_2 (0x1 << 2) // (PMC) Selected clock divided by 2 -#define AT91C_PMC_PRES_CLK_4 (0x2 << 2) // (PMC) Selected clock divided by 4 -#define AT91C_PMC_PRES_CLK_8 (0x3 << 2) // (PMC) Selected clock divided by 8 -#define AT91C_PMC_PRES_CLK_16 (0x4 << 2) // (PMC) Selected clock divided by 16 -#define AT91C_PMC_PRES_CLK_32 (0x5 << 2) // (PMC) Selected clock divided by 32 -#define AT91C_PMC_PRES_CLK_64 (0x6 << 2) // (PMC) Selected clock divided by 64 -// -------- PMC_PCKR : (PMC Offset: 0x40) Programmable Clock Register -------- -// -------- PMC_IER : (PMC Offset: 0x60) PMC Interrupt Enable Register -------- -#define AT91C_PMC_MOSCS (0x1 << 0) // (PMC) MOSC Status/Enable/Disable/Mask -#define AT91C_PMC_LOCK (0x1 << 2) // (PMC) PLL Status/Enable/Disable/Mask -#define AT91C_PMC_MCKRDY (0x1 << 3) // (PMC) MCK_RDY Status/Enable/Disable/Mask -#define AT91C_PMC_PCK0RDY (0x1 << 8) // (PMC) PCK0_RDY Status/Enable/Disable/Mask -#define AT91C_PMC_PCK1RDY (0x1 << 9) // (PMC) PCK1_RDY Status/Enable/Disable/Mask -#define AT91C_PMC_PCK2RDY (0x1 << 10) // (PMC) PCK2_RDY Status/Enable/Disable/Mask -#define AT91C_PMC_PCK3RDY (0x1 << 11) // (PMC) PCK3_RDY Status/Enable/Disable/Mask -// -------- PMC_IDR : (PMC Offset: 0x64) PMC Interrupt Disable Register -------- -// -------- PMC_SR : (PMC Offset: 0x68) PMC Status Register -------- -// -------- PMC_IMR : (PMC Offset: 0x6c) PMC Interrupt Mask Register -------- +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR Power Management Controller */ +/* ***************************************************************************** */ +/* *** Register offset in AT91S_PMC structure *** */ +#define PMC_SCER ( 0 ) /* System Clock Enable Register */ +#define PMC_SCDR ( 4 ) /* System Clock Disable Register */ +#define PMC_SCSR ( 8 ) /* System Clock Status Register */ +#define PMC_PCER ( 16 ) /* Peripheral Clock Enable Register */ +#define PMC_PCDR ( 20 ) /* Peripheral Clock Disable Register */ +#define PMC_PCSR ( 24 ) /* Peripheral Clock Status Register */ +#define PMC_MOR ( 32 ) /* Main Oscillator Register */ +#define PMC_MCFR ( 36 ) /* Main Clock Frequency Register */ +#define PMC_PLLR ( 44 ) /* PLL Register */ +#define PMC_MCKR ( 48 ) /* Master Clock Register */ +#define PMC_PCKR ( 64 ) /* Programmable Clock Register */ +#define PMC_IER ( 96 ) /* Interrupt Enable Register */ +#define PMC_IDR ( 100 ) /* Interrupt Disable Register */ +#define PMC_SR ( 104 ) /* Status Register */ +#define PMC_IMR ( 108 ) /* Interrupt Mask Register */ +/* -------- PMC_SCER : (PMC Offset: 0x0) System Clock Enable Register -------- */ +#define AT91C_PMC_PCK ( 0x1 << 0 ) /* (PMC) Processor Clock */ +#define AT91C_PMC_UDP ( 0x1 << 7 ) /* (PMC) USB Device Port Clock */ +#define AT91C_PMC_PCK0 ( 0x1 << 8 ) /* (PMC) Programmable Clock Output */ +#define AT91C_PMC_PCK1 ( 0x1 << 9 ) /* (PMC) Programmable Clock Output */ +#define AT91C_PMC_PCK2 ( 0x1 << 10 ) /* (PMC) Programmable Clock Output */ +#define AT91C_PMC_PCK3 ( 0x1 << 11 ) /* (PMC) Programmable Clock Output */ +/* -------- PMC_SCDR : (PMC Offset: 0x4) System Clock Disable Register -------- */ +/* -------- PMC_SCSR : (PMC Offset: 0x8) System Clock Status Register -------- */ +/* -------- CKGR_MOR : (PMC Offset: 0x20) Main Oscillator Register -------- */ +/* -------- CKGR_MCFR : (PMC Offset: 0x24) Main Clock Frequency Register -------- */ +/* -------- CKGR_PLLR : (PMC Offset: 0x2c) PLL B Register -------- */ +/* -------- PMC_MCKR : (PMC Offset: 0x30) Master Clock Register -------- */ +#define AT91C_PMC_CSS ( 0x3 << 0 ) /* (PMC) Programmable Clock Selection */ +#define AT91C_PMC_CSS_SLOW_CLK ( 0x0 ) /* (PMC) Slow Clock is selected */ +#define AT91C_PMC_CSS_MAIN_CLK ( 0x1 ) /* (PMC) Main Clock is selected */ +#define AT91C_PMC_CSS_PLL_CLK ( 0x3 ) /* (PMC) Clock from PLL is selected */ +#define AT91C_PMC_PRES ( 0x7 << 2 ) /* (PMC) Programmable Clock Prescaler */ +#define AT91C_PMC_PRES_CLK ( 0x0 << 2 ) /* (PMC) Selected clock */ +#define AT91C_PMC_PRES_CLK_2 ( 0x1 << 2 ) /* (PMC) Selected clock divided by 2 */ +#define AT91C_PMC_PRES_CLK_4 ( 0x2 << 2 ) /* (PMC) Selected clock divided by 4 */ +#define AT91C_PMC_PRES_CLK_8 ( 0x3 << 2 ) /* (PMC) Selected clock divided by 8 */ +#define AT91C_PMC_PRES_CLK_16 ( 0x4 << 2 ) /* (PMC) Selected clock divided by 16 */ +#define AT91C_PMC_PRES_CLK_32 ( 0x5 << 2 ) /* (PMC) Selected clock divided by 32 */ +#define AT91C_PMC_PRES_CLK_64 ( 0x6 << 2 ) /* (PMC) Selected clock divided by 64 */ +/* -------- PMC_PCKR : (PMC Offset: 0x40) Programmable Clock Register -------- */ +/* -------- PMC_IER : (PMC Offset: 0x60) PMC Interrupt Enable Register -------- */ +#define AT91C_PMC_MOSCS ( 0x1 << 0 ) /* (PMC) MOSC Status/Enable/Disable/Mask */ +#define AT91C_PMC_LOCK ( 0x1 << 2 ) /* (PMC) PLL Status/Enable/Disable/Mask */ +#define AT91C_PMC_MCKRDY ( 0x1 << 3 ) /* (PMC) MCK_RDY Status/Enable/Disable/Mask */ +#define AT91C_PMC_PCK0RDY ( 0x1 << 8 ) /* (PMC) PCK0_RDY Status/Enable/Disable/Mask */ +#define AT91C_PMC_PCK1RDY ( 0x1 << 9 ) /* (PMC) PCK1_RDY Status/Enable/Disable/Mask */ +#define AT91C_PMC_PCK2RDY ( 0x1 << 10 ) /* (PMC) PCK2_RDY Status/Enable/Disable/Mask */ +#define AT91C_PMC_PCK3RDY ( 0x1 << 11 ) /* (PMC) PCK3_RDY Status/Enable/Disable/Mask */ +/* -------- PMC_IDR : (PMC Offset: 0x64) PMC Interrupt Disable Register -------- */ +/* -------- PMC_SR : (PMC Offset: 0x68) PMC Status Register -------- */ +/* -------- PMC_IMR : (PMC Offset: 0x6c) PMC Interrupt Mask Register -------- */ -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Reset Controller Interface -// ***************************************************************************** -// *** Register offset in AT91S_RSTC structure *** -#define RSTC_RCR ( 0) // Reset Control Register -#define RSTC_RSR ( 4) // Reset Status Register -#define RSTC_RMR ( 8) // Reset Mode Register -// -------- SYSC_RCR : (RSTC Offset: 0x0) Reset Control Register -------- -#define AT91C_SYSC_PROCRST (0x1 << 0) // (RSTC) Processor Reset -#define AT91C_SYSC_ICERST (0x1 << 1) // (RSTC) ICE Interface Reset -#define AT91C_SYSC_PERRST (0x1 << 2) // (RSTC) Peripheral Reset -#define AT91C_SYSC_EXTRST (0x1 << 3) // (RSTC) External Reset -#define AT91C_SYSC_KEY (0xFF << 24) // (RSTC) Password -// -------- SYSC_RSR : (RSTC Offset: 0x4) Reset Status Register -------- -#define AT91C_SYSC_URSTS (0x1 << 0) // (RSTC) User Reset Status -#define AT91C_SYSC_BODSTS (0x1 << 1) // (RSTC) Brown-out Detection Status -#define AT91C_SYSC_RSTTYP (0x7 << 8) // (RSTC) Reset Type -#define AT91C_SYSC_RSTTYP_POWERUP (0x0 << 8) // (RSTC) Power-up Reset. VDDCORE rising. -#define AT91C_SYSC_RSTTYP_WATCHDOG (0x2 << 8) // (RSTC) Watchdog Reset. Watchdog overflow occured. -#define AT91C_SYSC_RSTTYP_SOFTWARE (0x3 << 8) // (RSTC) Software Reset. Processor reset required by the software. -#define AT91C_SYSC_RSTTYP_USER (0x4 << 8) // (RSTC) User Reset. NRST pin detected low. -#define AT91C_SYSC_RSTTYP_BROWNOUT (0x5 << 8) // (RSTC) Brown-out Reset. -#define AT91C_SYSC_NRSTL (0x1 << 16) // (RSTC) NRST pin level -#define AT91C_SYSC_SRCMP (0x1 << 17) // (RSTC) Software Reset Command in Progress. -// -------- SYSC_RMR : (RSTC Offset: 0x8) Reset Mode Register -------- -#define AT91C_SYSC_URSTEN (0x1 << 0) // (RSTC) User Reset Enable -#define AT91C_SYSC_URSTIEN (0x1 << 4) // (RSTC) User Reset Interrupt Enable -#define AT91C_SYSC_ERSTL (0xF << 8) // (RSTC) User Reset Enable -#define AT91C_SYSC_BODIEN (0x1 << 16) // (RSTC) Brown-out Detection Interrupt Enable +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR Reset Controller Interface */ +/* ***************************************************************************** */ +/* *** Register offset in AT91S_RSTC structure *** */ +#define RSTC_RCR ( 0 ) /* Reset Control Register */ +#define RSTC_RSR ( 4 ) /* Reset Status Register */ +#define RSTC_RMR ( 8 ) /* Reset Mode Register */ +/* -------- SYSC_RCR : (RSTC Offset: 0x0) Reset Control Register -------- */ +#define AT91C_SYSC_PROCRST ( 0x1 << 0 ) /* (RSTC) Processor Reset */ +#define AT91C_SYSC_ICERST ( 0x1 << 1 ) /* (RSTC) ICE Interface Reset */ +#define AT91C_SYSC_PERRST ( 0x1 << 2 ) /* (RSTC) Peripheral Reset */ +#define AT91C_SYSC_EXTRST ( 0x1 << 3 ) /* (RSTC) External Reset */ +#define AT91C_SYSC_KEY ( 0xFF << 24 ) /* (RSTC) Password */ +/* -------- SYSC_RSR : (RSTC Offset: 0x4) Reset Status Register -------- */ +#define AT91C_SYSC_URSTS ( 0x1 << 0 ) /* (RSTC) User Reset Status */ +#define AT91C_SYSC_BODSTS ( 0x1 << 1 ) /* (RSTC) Brown-out Detection Status */ +#define AT91C_SYSC_RSTTYP ( 0x7 << 8 ) /* (RSTC) Reset Type */ +#define AT91C_SYSC_RSTTYP_POWERUP ( 0x0 << 8 ) /* (RSTC) Power-up Reset. VDDCORE rising. */ +#define AT91C_SYSC_RSTTYP_WATCHDOG ( 0x2 << 8 ) /* (RSTC) Watchdog Reset. Watchdog overflow occurred. */ +#define AT91C_SYSC_RSTTYP_SOFTWARE ( 0x3 << 8 ) /* (RSTC) Software Reset. Processor reset required by the software. */ +#define AT91C_SYSC_RSTTYP_USER ( 0x4 << 8 ) /* (RSTC) User Reset. NRST pin detected low. */ +#define AT91C_SYSC_RSTTYP_BROWNOUT ( 0x5 << 8 ) /* (RSTC) Brown-out Reset. */ +#define AT91C_SYSC_NRSTL ( 0x1 << 16 ) /* (RSTC) NRST pin level */ +#define AT91C_SYSC_SRCMP ( 0x1 << 17 ) /* (RSTC) Software Reset Command in Progress. */ +/* -------- SYSC_RMR : (RSTC Offset: 0x8) Reset Mode Register -------- */ +#define AT91C_SYSC_URSTEN ( 0x1 << 0 ) /* (RSTC) User Reset Enable */ +#define AT91C_SYSC_URSTIEN ( 0x1 << 4 ) /* (RSTC) User Reset Interrupt Enable */ +#define AT91C_SYSC_ERSTL ( 0xF << 8 ) /* (RSTC) User Reset Enable */ +#define AT91C_SYSC_BODIEN ( 0x1 << 16 ) /* (RSTC) Brown-out Detection Interrupt Enable */ -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Real Time Timer Controller Interface -// ***************************************************************************** -// *** Register offset in AT91S_RTTC structure *** -#define RTTC_RTMR ( 0) // Real-time Mode Register -#define RTTC_RTAR ( 4) // Real-time Alarm Register -#define RTTC_RTVR ( 8) // Real-time Value Register -#define RTTC_RTSR (12) // Real-time Status Register -// -------- SYSC_RTMR : (RTTC Offset: 0x0) Real-time Mode Register -------- -#define AT91C_SYSC_RTPRES (0xFFFF << 0) // (RTTC) Real-time Timer Prescaler Value -#define AT91C_SYSC_ALMIEN (0x1 << 16) // (RTTC) Alarm Interrupt Enable -#define AT91C_SYSC_RTTINCIEN (0x1 << 17) // (RTTC) Real Time Timer Increment Interrupt Enable -#define AT91C_SYSC_RTTRST (0x1 << 18) // (RTTC) Real Time Timer Restart -// -------- SYSC_RTAR : (RTTC Offset: 0x4) Real-time Alarm Register -------- -#define AT91C_SYSC_ALMV (0x0 << 0) // (RTTC) Alarm Value -// -------- SYSC_RTVR : (RTTC Offset: 0x8) Current Real-time Value Register -------- -#define AT91C_SYSC_CRTV (0x0 << 0) // (RTTC) Current Real-time Value -// -------- SYSC_RTSR : (RTTC Offset: 0xc) Real-time Status Register -------- -#define AT91C_SYSC_ALMS (0x1 << 0) // (RTTC) Real-time Alarm Status -#define AT91C_SYSC_RTTINC (0x1 << 1) // (RTTC) Real-time Timer Increment +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR Real Time Timer Controller Interface */ +/* ***************************************************************************** */ +/* *** Register offset in AT91S_RTTC structure *** */ +#define RTTC_RTMR ( 0 ) /* Real-time Mode Register */ +#define RTTC_RTAR ( 4 ) /* Real-time Alarm Register */ +#define RTTC_RTVR ( 8 ) /* Real-time Value Register */ +#define RTTC_RTSR ( 12 ) /* Real-time Status Register */ +/* -------- SYSC_RTMR : (RTTC Offset: 0x0) Real-time Mode Register -------- */ +#define AT91C_SYSC_RTPRES ( 0xFFFF << 0 ) /* (RTTC) Real-time Timer Prescaler Value */ +#define AT91C_SYSC_ALMIEN ( 0x1 << 16 ) /* (RTTC) Alarm Interrupt Enable */ +#define AT91C_SYSC_RTTINCIEN ( 0x1 << 17 ) /* (RTTC) Real Time Timer Increment Interrupt Enable */ +#define AT91C_SYSC_RTTRST ( 0x1 << 18 ) /* (RTTC) Real Time Timer Restart */ +/* -------- SYSC_RTAR : (RTTC Offset: 0x4) Real-time Alarm Register -------- */ +#define AT91C_SYSC_ALMV ( 0x0 << 0 ) /* (RTTC) Alarm Value */ +/* -------- SYSC_RTVR : (RTTC Offset: 0x8) Current Real-time Value Register -------- */ +#define AT91C_SYSC_CRTV ( 0x0 << 0 ) /* (RTTC) Current Real-time Value */ +/* -------- SYSC_RTSR : (RTTC Offset: 0xc) Real-time Status Register -------- */ +#define AT91C_SYSC_ALMS ( 0x1 << 0 ) /* (RTTC) Real-time Alarm Status */ +#define AT91C_SYSC_RTTINC ( 0x1 << 1 ) /* (RTTC) Real-time Timer Increment */ -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Periodic Interval Timer Controller Interface -// ***************************************************************************** -// *** Register offset in AT91S_PITC structure *** -#define PITC_PIMR ( 0) // Period Interval Mode Register -#define PITC_PISR ( 4) // Period Interval Status Register -#define PITC_PIVR ( 8) // Period Interval Value Register -#define PITC_PIIR (12) // Period Interval Image Register -// -------- SYSC_PIMR : (PITC Offset: 0x0) Periodic Interval Mode Register -------- -#define AT91C_SYSC_PIV (0xFFFFF << 0) // (PITC) Periodic Interval Value -#define AT91C_SYSC_PITEN (0x1 << 24) // (PITC) Periodic Interval Timer Enabled -#define AT91C_SYSC_PITIEN (0x1 << 25) // (PITC) Periodic Interval Timer Interrupt Enable -// -------- SYSC_PISR : (PITC Offset: 0x4) Periodic Interval Status Register -------- -#define AT91C_SYSC_PITS (0x1 << 0) // (PITC) Periodic Interval Timer Status -// -------- SYSC_PIVR : (PITC Offset: 0x8) Periodic Interval Value Register -------- -#define AT91C_SYSC_CPIV (0xFFFFF << 0) // (PITC) Current Periodic Interval Value -#define AT91C_SYSC_PICNT (0xFFF << 20) // (PITC) Periodic Interval Counter -// -------- SYSC_PIIR : (PITC Offset: 0xc) Periodic Interval Image Register -------- +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR Periodic Interval Timer Controller Interface */ +/* ***************************************************************************** */ +/* *** Register offset in AT91S_PITC structure *** */ +#define PITC_PIMR ( 0 ) /* Period Interval Mode Register */ +#define PITC_PISR ( 4 ) /* Period Interval Status Register */ +#define PITC_PIVR ( 8 ) /* Period Interval Value Register */ +#define PITC_PIIR ( 12 ) /* Period Interval Image Register */ +/* -------- SYSC_PIMR : (PITC Offset: 0x0) Periodic Interval Mode Register -------- */ +#define AT91C_SYSC_PIV ( 0xFFFFF << 0 ) /* (PITC) Periodic Interval Value */ +#define AT91C_SYSC_PITEN ( 0x1 << 24 ) /* (PITC) Periodic Interval Timer Enabled */ +#define AT91C_SYSC_PITIEN ( 0x1 << 25 ) /* (PITC) Periodic Interval Timer Interrupt Enable */ +/* -------- SYSC_PISR : (PITC Offset: 0x4) Periodic Interval Status Register -------- */ +#define AT91C_SYSC_PITS ( 0x1 << 0 ) /* (PITC) Periodic Interval Timer Status */ +/* -------- SYSC_PIVR : (PITC Offset: 0x8) Periodic Interval Value Register -------- */ +#define AT91C_SYSC_CPIV ( 0xFFFFF << 0 ) /* (PITC) Current Periodic Interval Value */ +#define AT91C_SYSC_PICNT ( 0xFFF << 20 ) /* (PITC) Periodic Interval Counter */ +/* -------- SYSC_PIIR : (PITC Offset: 0xc) Periodic Interval Image Register -------- */ -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Watchdog Timer Controller Interface -// ***************************************************************************** -// *** Register offset in AT91S_WDTC structure *** -#define WDTC_WDCR ( 0) // Watchdog Control Register -#define WDTC_WDMR ( 4) // Watchdog Mode Register -#define WDTC_WDSR ( 8) // Watchdog Status Register -// -------- SYSC_WDCR : (WDTC Offset: 0x0) Periodic Interval Image Register -------- -#define AT91C_SYSC_WDRSTT (0x1 << 0) // (WDTC) Watchdog Restart -// -------- SYSC_WDMR : (WDTC Offset: 0x4) Watchdog Mode Register -------- -#define AT91C_SYSC_WDV (0xFFF << 0) // (WDTC) Watchdog Timer Restart -#define AT91C_SYSC_WDFIEN (0x1 << 12) // (WDTC) Watchdog Fault Interrupt Enable -#define AT91C_SYSC_WDRSTEN (0x1 << 13) // (WDTC) Watchdog Reset Enable -#define AT91C_SYSC_WDRPROC (0x1 << 14) // (WDTC) Watchdog Timer Restart -#define AT91C_SYSC_WDDIS (0x1 << 15) // (WDTC) Watchdog Disable -#define AT91C_SYSC_WDD (0xFFF << 16) // (WDTC) Watchdog Delta Value -#define AT91C_SYSC_WDDBGHLT (0x1 << 28) // (WDTC) Watchdog Debug Halt -#define AT91C_SYSC_WDIDLEHLT (0x1 << 29) // (WDTC) Watchdog Idle Halt -// -------- SYSC_WDSR : (WDTC Offset: 0x8) Watchdog Status Register -------- -#define AT91C_SYSC_WDUNF (0x1 << 0) // (WDTC) Watchdog Underflow -#define AT91C_SYSC_WDERR (0x1 << 1) // (WDTC) Watchdog Error +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR Watchdog Timer Controller Interface */ +/* ***************************************************************************** */ +/* *** Register offset in AT91S_WDTC structure *** */ +#define WDTC_WDCR ( 0 ) /* Watchdog Control Register */ +#define WDTC_WDMR ( 4 ) /* Watchdog Mode Register */ +#define WDTC_WDSR ( 8 ) /* Watchdog Status Register */ +/* -------- SYSC_WDCR : (WDTC Offset: 0x0) Periodic Interval Image Register -------- */ +#define AT91C_SYSC_WDRSTT ( 0x1 << 0 ) /* (WDTC) Watchdog Restart */ +/* -------- SYSC_WDMR : (WDTC Offset: 0x4) Watchdog Mode Register -------- */ +#define AT91C_SYSC_WDV ( 0xFFF << 0 ) /* (WDTC) Watchdog Timer Restart */ +#define AT91C_SYSC_WDFIEN ( 0x1 << 12 ) /* (WDTC) Watchdog Fault Interrupt Enable */ +#define AT91C_SYSC_WDRSTEN ( 0x1 << 13 ) /* (WDTC) Watchdog Reset Enable */ +#define AT91C_SYSC_WDRPROC ( 0x1 << 14 ) /* (WDTC) Watchdog Timer Restart */ +#define AT91C_SYSC_WDDIS ( 0x1 << 15 ) /* (WDTC) Watchdog Disable */ +#define AT91C_SYSC_WDD ( 0xFFF << 16 ) /* (WDTC) Watchdog Delta Value */ +#define AT91C_SYSC_WDDBGHLT ( 0x1 << 28 ) /* (WDTC) Watchdog Debug Halt */ +#define AT91C_SYSC_WDIDLEHLT ( 0x1 << 29 ) /* (WDTC) Watchdog Idle Halt */ +/* -------- SYSC_WDSR : (WDTC Offset: 0x8) Watchdog Status Register -------- */ +#define AT91C_SYSC_WDUNF ( 0x1 << 0 ) /* (WDTC) Watchdog Underflow */ +#define AT91C_SYSC_WDERR ( 0x1 << 1 ) /* (WDTC) Watchdog Error */ -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Memory Controller Interface -// ***************************************************************************** -// *** Register offset in AT91S_MC structure *** -#define MC_RCR ( 0) // MC Remap Control Register -#define MC_ASR ( 4) // MC Abort Status Register -#define MC_AASR ( 8) // MC Abort Address Status Register -#define MC_FMR (96) // MC Flash Mode Register -#define MC_FCR (100) // MC Flash Command Register -#define MC_FSR (104) // MC Flash Status Register -// -------- MC_RCR : (MC Offset: 0x0) MC Remap Control Register -------- -#define AT91C_MC_RCB (0x1 << 0) // (MC) Remap Command Bit -// -------- MC_ASR : (MC Offset: 0x4) MC Abort Status Register -------- -#define AT91C_MC_UNDADD (0x1 << 0) // (MC) Undefined Addess Abort Status -#define AT91C_MC_MISADD (0x1 << 1) // (MC) Misaligned Addess Abort Status -#define AT91C_MC_ABTSZ (0x3 << 8) // (MC) Abort Size Status -#define AT91C_MC_ABTSZ_BYTE (0x0 << 8) // (MC) Byte -#define AT91C_MC_ABTSZ_HWORD (0x1 << 8) // (MC) Half-word -#define AT91C_MC_ABTSZ_WORD (0x2 << 8) // (MC) Word -#define AT91C_MC_ABTTYP (0x3 << 10) // (MC) Abort Type Status -#define AT91C_MC_ABTTYP_DATAR (0x0 << 10) // (MC) Data Read -#define AT91C_MC_ABTTYP_DATAW (0x1 << 10) // (MC) Data Write -#define AT91C_MC_ABTTYP_FETCH (0x2 << 10) // (MC) Code Fetch -#define AT91C_MC_MST0 (0x1 << 16) // (MC) Master 0 Abort Source -#define AT91C_MC_MST1 (0x1 << 17) // (MC) Master 1 Abort Source -#define AT91C_MC_SVMST0 (0x1 << 24) // (MC) Saved Master 0 Abort Source -#define AT91C_MC_SVMST1 (0x1 << 25) // (MC) Saved Master 1 Abort Source -// -------- MC_FMR : (MC Offset: 0x60) MC Flash Mode Register -------- -#define AT91C_MC_FRDY (0x1 << 0) // (MC) Flash Ready -#define AT91C_MC_LOCKE (0x1 << 2) // (MC) Lock Error -#define AT91C_MC_PROGE (0x1 << 3) // (MC) Programming Error -#define AT91C_MC_NEBP (0x1 << 7) // (MC) No Erase Before Programming -#define AT91C_MC_FWS (0x3 << 8) // (MC) Flash Wait State -#define AT91C_MC_FWS_0FWS (0x0 << 8) // (MC) 1 cycle for Read, 2 for Write operations -#define AT91C_MC_FWS_1FWS (0x1 << 8) // (MC) 2 cycles for Read, 3 for Write operations -#define AT91C_MC_FWS_2FWS (0x2 << 8) // (MC) 3 cycles for Read, 4 for Write operations -#define AT91C_MC_FWS_3FWS (0x3 << 8) // (MC) 4 cycles for Read, 4 for Write operations -#define AT91C_MC_FMCN (0xFF << 16) // (MC) Flash Microsecond Cycle Number -// -------- MC_FCR : (MC Offset: 0x64) MC Flash Command Register -------- -#define AT91C_MC_FCMD (0xF << 0) // (MC) Flash Command -#define AT91C_MC_FCMD_START_PROG (0x1) // (MC) Starts the programming of th epage specified by PAGEN. -#define AT91C_MC_FCMD_LOCK (0x2) // (MC) Starts a lock sequence of the sector defined by the bits 4 to 7 of the field PAGEN. -#define AT91C_MC_FCMD_PROG_AND_LOCK (0x3) // (MC) The lock sequence automatically happens after the programming sequence is completed. -#define AT91C_MC_FCMD_UNLOCK (0x4) // (MC) Starts an unlock sequence of the sector defined by the bits 4 to 7 of the field PAGEN. -#define AT91C_MC_FCMD_ERASE_ALL (0x8) // (MC) Starts the erase of the entire flash.If at least a page is locked, the command is cancelled. -#define AT91C_MC_FCMD_SET_GP_NVM (0xB) // (MC) Set General Purpose NVM bits. -#define AT91C_MC_FCMD_CLR_GP_NVM (0xD) // (MC) Clear General Purpose NVM bits. -#define AT91C_MC_FCMD_SET_SECURITY (0xF) // (MC) Set Security Bit. -#define AT91C_MC_PAGEN (0x3FF << 8) // (MC) Page Number -#define AT91C_MC_KEY (0xFF << 24) // (MC) Writing Protect Key -// -------- MC_FSR : (MC Offset: 0x68) MC Flash Command Register -------- -#define AT91C_MC_SECURITY (0x1 << 4) // (MC) Security Bit Status -#define AT91C_MC_GPNVM0 (0x1 << 8) // (MC) Sector 0 Lock Status -#define AT91C_MC_GPNVM1 (0x1 << 9) // (MC) Sector 1 Lock Status -#define AT91C_MC_GPNVM2 (0x1 << 10) // (MC) Sector 2 Lock Status -#define AT91C_MC_GPNVM3 (0x1 << 11) // (MC) Sector 3 Lock Status -#define AT91C_MC_GPNVM4 (0x1 << 12) // (MC) Sector 4 Lock Status -#define AT91C_MC_GPNVM5 (0x1 << 13) // (MC) Sector 5 Lock Status -#define AT91C_MC_GPNVM6 (0x1 << 14) // (MC) Sector 6 Lock Status -#define AT91C_MC_GPNVM7 (0x1 << 15) // (MC) Sector 7 Lock Status -#define AT91C_MC_LOCKS0 (0x1 << 16) // (MC) Sector 0 Lock Status -#define AT91C_MC_LOCKS1 (0x1 << 17) // (MC) Sector 1 Lock Status -#define AT91C_MC_LOCKS2 (0x1 << 18) // (MC) Sector 2 Lock Status -#define AT91C_MC_LOCKS3 (0x1 << 19) // (MC) Sector 3 Lock Status -#define AT91C_MC_LOCKS4 (0x1 << 20) // (MC) Sector 4 Lock Status -#define AT91C_MC_LOCKS5 (0x1 << 21) // (MC) Sector 5 Lock Status -#define AT91C_MC_LOCKS6 (0x1 << 22) // (MC) Sector 6 Lock Status -#define AT91C_MC_LOCKS7 (0x1 << 23) // (MC) Sector 7 Lock Status -#define AT91C_MC_LOCKS8 (0x1 << 24) // (MC) Sector 8 Lock Status -#define AT91C_MC_LOCKS9 (0x1 << 25) // (MC) Sector 9 Lock Status -#define AT91C_MC_LOCKS10 (0x1 << 26) // (MC) Sector 10 Lock Status -#define AT91C_MC_LOCKS11 (0x1 << 27) // (MC) Sector 11 Lock Status -#define AT91C_MC_LOCKS12 (0x1 << 28) // (MC) Sector 12 Lock Status -#define AT91C_MC_LOCKS13 (0x1 << 29) // (MC) Sector 13 Lock Status -#define AT91C_MC_LOCKS14 (0x1 << 30) // (MC) Sector 14 Lock Status -#define AT91C_MC_LOCKS15 (0x1 << 31) // (MC) Sector 15 Lock Status +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR Memory Controller Interface */ +/* ***************************************************************************** */ +/* *** Register offset in AT91S_MC structure *** */ +#define MC_RCR ( 0 ) /* MC Remap Control Register */ +#define MC_ASR ( 4 ) /* MC Abort Status Register */ +#define MC_AASR ( 8 ) /* MC Abort Address Status Register */ +#define MC_FMR ( 96 ) /* MC Flash Mode Register */ +#define MC_FCR ( 100 ) /* MC Flash Command Register */ +#define MC_FSR ( 104 ) /* MC Flash Status Register */ +/* -------- MC_RCR : (MC Offset: 0x0) MC Remap Control Register -------- */ +#define AT91C_MC_RCB ( 0x1 << 0 ) /* (MC) Remap Command Bit */ +/* -------- MC_ASR : (MC Offset: 0x4) MC Abort Status Register -------- */ +#define AT91C_MC_UNDADD ( 0x1 << 0 ) /* (MC) Undefined Addess Abort Status */ +#define AT91C_MC_MISADD ( 0x1 << 1 ) /* (MC) Misaligned Addess Abort Status */ +#define AT91C_MC_ABTSZ ( 0x3 << 8 ) /* (MC) Abort Size Status */ +#define AT91C_MC_ABTSZ_BYTE ( 0x0 << 8 ) /* (MC) Byte */ +#define AT91C_MC_ABTSZ_HWORD ( 0x1 << 8 ) /* (MC) Half-word */ +#define AT91C_MC_ABTSZ_WORD ( 0x2 << 8 ) /* (MC) Word */ +#define AT91C_MC_ABTTYP ( 0x3 << 10 ) /* (MC) Abort Type Status */ +#define AT91C_MC_ABTTYP_DATAR ( 0x0 << 10 ) /* (MC) Data Read */ +#define AT91C_MC_ABTTYP_DATAW ( 0x1 << 10 ) /* (MC) Data Write */ +#define AT91C_MC_ABTTYP_FETCH ( 0x2 << 10 ) /* (MC) Code Fetch */ +#define AT91C_MC_MST0 ( 0x1 << 16 ) /* (MC) Master 0 Abort Source */ +#define AT91C_MC_MST1 ( 0x1 << 17 ) /* (MC) Master 1 Abort Source */ +#define AT91C_MC_SVMST0 ( 0x1 << 24 ) /* (MC) Saved Master 0 Abort Source */ +#define AT91C_MC_SVMST1 ( 0x1 << 25 ) /* (MC) Saved Master 1 Abort Source */ +/* -------- MC_FMR : (MC Offset: 0x60) MC Flash Mode Register -------- */ +#define AT91C_MC_FRDY ( 0x1 << 0 ) /* (MC) Flash Ready */ +#define AT91C_MC_LOCKE ( 0x1 << 2 ) /* (MC) Lock Error */ +#define AT91C_MC_PROGE ( 0x1 << 3 ) /* (MC) Programming Error */ +#define AT91C_MC_NEBP ( 0x1 << 7 ) /* (MC) No Erase Before Programming */ +#define AT91C_MC_FWS ( 0x3 << 8 ) /* (MC) Flash Wait State */ +#define AT91C_MC_FWS_0FWS ( 0x0 << 8 ) /* (MC) 1 cycle for Read, 2 for Write operations */ +#define AT91C_MC_FWS_1FWS ( 0x1 << 8 ) /* (MC) 2 cycles for Read, 3 for Write operations */ +#define AT91C_MC_FWS_2FWS ( 0x2 << 8 ) /* (MC) 3 cycles for Read, 4 for Write operations */ +#define AT91C_MC_FWS_3FWS ( 0x3 << 8 ) /* (MC) 4 cycles for Read, 4 for Write operations */ +#define AT91C_MC_FMCN ( 0xFF << 16 ) /* (MC) Flash Microsecond Cycle Number */ +/* -------- MC_FCR : (MC Offset: 0x64) MC Flash Command Register -------- */ +#define AT91C_MC_FCMD ( 0xF << 0 ) /* (MC) Flash Command */ +#define AT91C_MC_FCMD_START_PROG ( 0x1 ) /* (MC) Starts the programming of th epage specified by PAGEN. */ +#define AT91C_MC_FCMD_LOCK ( 0x2 ) /* (MC) Starts a lock sequence of the sector defined by the bits 4 to 7 of the field PAGEN. */ +#define AT91C_MC_FCMD_PROG_AND_LOCK ( 0x3 ) /* (MC) The lock sequence automatically happens after the programming sequence is completed. */ +#define AT91C_MC_FCMD_UNLOCK ( 0x4 ) /* (MC) Starts an unlock sequence of the sector defined by the bits 4 to 7 of the field PAGEN. */ +#define AT91C_MC_FCMD_ERASE_ALL ( 0x8 ) /* (MC) Starts the erase of the entire flash.If at least a page is locked, the command is cancelled. */ +#define AT91C_MC_FCMD_SET_GP_NVM ( 0xB ) /* (MC) Set General Purpose NVM bits. */ +#define AT91C_MC_FCMD_CLR_GP_NVM ( 0xD ) /* (MC) Clear General Purpose NVM bits. */ +#define AT91C_MC_FCMD_SET_SECURITY ( 0xF ) /* (MC) Set Security Bit. */ +#define AT91C_MC_PAGEN ( 0x3FF << 8 ) /* (MC) Page Number */ +#define AT91C_MC_KEY ( 0xFF << 24 ) /* (MC) Writing Protect Key */ +/* -------- MC_FSR : (MC Offset: 0x68) MC Flash Command Register -------- */ +#define AT91C_MC_SECURITY ( 0x1 << 4 ) /* (MC) Security Bit Status */ +#define AT91C_MC_GPNVM0 ( 0x1 << 8 ) /* (MC) Sector 0 Lock Status */ +#define AT91C_MC_GPNVM1 ( 0x1 << 9 ) /* (MC) Sector 1 Lock Status */ +#define AT91C_MC_GPNVM2 ( 0x1 << 10 ) /* (MC) Sector 2 Lock Status */ +#define AT91C_MC_GPNVM3 ( 0x1 << 11 ) /* (MC) Sector 3 Lock Status */ +#define AT91C_MC_GPNVM4 ( 0x1 << 12 ) /* (MC) Sector 4 Lock Status */ +#define AT91C_MC_GPNVM5 ( 0x1 << 13 ) /* (MC) Sector 5 Lock Status */ +#define AT91C_MC_GPNVM6 ( 0x1 << 14 ) /* (MC) Sector 6 Lock Status */ +#define AT91C_MC_GPNVM7 ( 0x1 << 15 ) /* (MC) Sector 7 Lock Status */ +#define AT91C_MC_LOCKS0 ( 0x1 << 16 ) /* (MC) Sector 0 Lock Status */ +#define AT91C_MC_LOCKS1 ( 0x1 << 17 ) /* (MC) Sector 1 Lock Status */ +#define AT91C_MC_LOCKS2 ( 0x1 << 18 ) /* (MC) Sector 2 Lock Status */ +#define AT91C_MC_LOCKS3 ( 0x1 << 19 ) /* (MC) Sector 3 Lock Status */ +#define AT91C_MC_LOCKS4 ( 0x1 << 20 ) /* (MC) Sector 4 Lock Status */ +#define AT91C_MC_LOCKS5 ( 0x1 << 21 ) /* (MC) Sector 5 Lock Status */ +#define AT91C_MC_LOCKS6 ( 0x1 << 22 ) /* (MC) Sector 6 Lock Status */ +#define AT91C_MC_LOCKS7 ( 0x1 << 23 ) /* (MC) Sector 7 Lock Status */ +#define AT91C_MC_LOCKS8 ( 0x1 << 24 ) /* (MC) Sector 8 Lock Status */ +#define AT91C_MC_LOCKS9 ( 0x1 << 25 ) /* (MC) Sector 9 Lock Status */ +#define AT91C_MC_LOCKS10 ( 0x1 << 26 ) /* (MC) Sector 10 Lock Status */ +#define AT91C_MC_LOCKS11 ( 0x1 << 27 ) /* (MC) Sector 11 Lock Status */ +#define AT91C_MC_LOCKS12 ( 0x1 << 28 ) /* (MC) Sector 12 Lock Status */ +#define AT91C_MC_LOCKS13 ( 0x1 << 29 ) /* (MC) Sector 13 Lock Status */ +#define AT91C_MC_LOCKS14 ( 0x1 << 30 ) /* (MC) Sector 14 Lock Status */ +#define AT91C_MC_LOCKS15 ( 0x1 << 31 ) /* (MC) Sector 15 Lock Status */ -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Serial Parallel Interface -// ***************************************************************************** -// *** Register offset in AT91S_SPI structure *** -#define SPI_CR ( 0) // Control Register -#define SPI_MR ( 4) // Mode Register -#define SPI_RDR ( 8) // Receive Data Register -#define SPI_TDR (12) // Transmit Data Register -#define SPI_SR (16) // Status Register -#define SPI_IER (20) // Interrupt Enable Register -#define SPI_IDR (24) // Interrupt Disable Register -#define SPI_IMR (28) // Interrupt Mask Register -#define SPI_CSR (48) // Chip Select Register -#define SPI_RPR (256) // Receive Pointer Register -#define SPI_RCR (260) // Receive Counter Register -#define SPI_TPR (264) // Transmit Pointer Register -#define SPI_TCR (268) // Transmit Counter Register -#define SPI_RNPR (272) // Receive Next Pointer Register -#define SPI_RNCR (276) // Receive Next Counter Register -#define SPI_TNPR (280) // Transmit Next Pointer Register -#define SPI_TNCR (284) // Transmit Next Counter Register -#define SPI_PTCR (288) // PDC Transfer Control Register -#define SPI_PTSR (292) // PDC Transfer Status Register -// -------- SPI_CR : (SPI Offset: 0x0) SPI Control Register -------- -#define AT91C_SPI_SPIEN (0x1 << 0) // (SPI) SPI Enable -#define AT91C_SPI_SPIDIS (0x1 << 1) // (SPI) SPI Disable -#define AT91C_SPI_SWRST (0x1 << 7) // (SPI) SPI Software reset -#define AT91C_SPI_LASTXFER (0x1 << 24) // (SPI) SPI Last Transfer -// -------- SPI_MR : (SPI Offset: 0x4) SPI Mode Register -------- -#define AT91C_SPI_MSTR (0x1 << 0) // (SPI) Master/Slave Mode -#define AT91C_SPI_PS (0x1 << 1) // (SPI) Peripheral Select -#define AT91C_SPI_PS_FIXED (0x0 << 1) // (SPI) Fixed Peripheral Select -#define AT91C_SPI_PS_VARIABLE (0x1 << 1) // (SPI) Variable Peripheral Select -#define AT91C_SPI_PCSDEC (0x1 << 2) // (SPI) Chip Select Decode -#define AT91C_SPI_FDIV (0x1 << 3) // (SPI) Clock Selection -#define AT91C_SPI_MODFDIS (0x1 << 4) // (SPI) Mode Fault Detection -#define AT91C_SPI_LLB (0x1 << 7) // (SPI) Clock Selection -#define AT91C_SPI_PCS (0xF << 16) // (SPI) Peripheral Chip Select -#define AT91C_SPI_DLYBCS (0xFF << 24) // (SPI) Delay Between Chip Selects -// -------- SPI_RDR : (SPI Offset: 0x8) Receive Data Register -------- -#define AT91C_SPI_RD (0xFFFF << 0) // (SPI) Receive Data -#define AT91C_SPI_RPCS (0xF << 16) // (SPI) Peripheral Chip Select Status -// -------- SPI_TDR : (SPI Offset: 0xc) Transmit Data Register -------- -#define AT91C_SPI_TD (0xFFFF << 0) // (SPI) Transmit Data -#define AT91C_SPI_TPCS (0xF << 16) // (SPI) Peripheral Chip Select Status -// -------- SPI_SR : (SPI Offset: 0x10) Status Register -------- -#define AT91C_SPI_RDRF (0x1 << 0) // (SPI) Receive Data Register Full -#define AT91C_SPI_TDRE (0x1 << 1) // (SPI) Transmit Data Register Empty -#define AT91C_SPI_MODF (0x1 << 2) // (SPI) Mode Fault Error -#define AT91C_SPI_OVRES (0x1 << 3) // (SPI) Overrun Error Status -#define AT91C_SPI_ENDRX (0x1 << 4) // (SPI) End of Receiver Transfer -#define AT91C_SPI_ENDTX (0x1 << 5) // (SPI) End of Receiver Transfer -#define AT91C_SPI_RXBUFF (0x1 << 6) // (SPI) RXBUFF Interrupt -#define AT91C_SPI_TXBUFE (0x1 << 7) // (SPI) TXBUFE Interrupt -#define AT91C_SPI_NSSR (0x1 << 8) // (SPI) NSSR Interrupt -#define AT91C_SPI_TXEMPTY (0x1 << 9) // (SPI) TXEMPTY Interrupt -#define AT91C_SPI_SPIENS (0x1 << 16) // (SPI) Enable Status -// -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register -------- -// -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register -------- -// -------- SPI_IMR : (SPI Offset: 0x1c) Interrupt Mask Register -------- -// -------- SPI_CSR : (SPI Offset: 0x30) Chip Select Register -------- -#define AT91C_SPI_CPOL (0x1 << 0) // (SPI) Clock Polarity -#define AT91C_SPI_NCPHA (0x1 << 1) // (SPI) Clock Phase -#define AT91C_SPI_CSAAT (0x1 << 2) // (SPI) Chip Select Active After Transfer -#define AT91C_SPI_BITS (0xF << 4) // (SPI) Bits Per Transfer -#define AT91C_SPI_BITS_8 (0x0 << 4) // (SPI) 8 Bits Per transfer -#define AT91C_SPI_BITS_9 (0x1 << 4) // (SPI) 9 Bits Per transfer -#define AT91C_SPI_BITS_10 (0x2 << 4) // (SPI) 10 Bits Per transfer -#define AT91C_SPI_BITS_11 (0x3 << 4) // (SPI) 11 Bits Per transfer -#define AT91C_SPI_BITS_12 (0x4 << 4) // (SPI) 12 Bits Per transfer -#define AT91C_SPI_BITS_13 (0x5 << 4) // (SPI) 13 Bits Per transfer -#define AT91C_SPI_BITS_14 (0x6 << 4) // (SPI) 14 Bits Per transfer -#define AT91C_SPI_BITS_15 (0x7 << 4) // (SPI) 15 Bits Per transfer -#define AT91C_SPI_BITS_16 (0x8 << 4) // (SPI) 16 Bits Per transfer -#define AT91C_SPI_SCBR (0xFF << 8) // (SPI) Serial Clock Baud Rate -#define AT91C_SPI_DLYBS (0xFF << 16) // (SPI) Serial Clock Baud Rate -#define AT91C_SPI_DLYBCT (0xFF << 24) // (SPI) Delay Between Consecutive Transfers +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR Serial Parallel Interface */ +/* ***************************************************************************** */ +/* *** Register offset in AT91S_SPI structure *** */ +#define SPI_CR ( 0 ) /* Control Register */ +#define SPI_MR ( 4 ) /* Mode Register */ +#define SPI_RDR ( 8 ) /* Receive Data Register */ +#define SPI_TDR ( 12 ) /* Transmit Data Register */ +#define SPI_SR ( 16 ) /* Status Register */ +#define SPI_IER ( 20 ) /* Interrupt Enable Register */ +#define SPI_IDR ( 24 ) /* Interrupt Disable Register */ +#define SPI_IMR ( 28 ) /* Interrupt Mask Register */ +#define SPI_CSR ( 48 ) /* Chip Select Register */ +#define SPI_RPR ( 256 ) /* Receive Pointer Register */ +#define SPI_RCR ( 260 ) /* Receive Counter Register */ +#define SPI_TPR ( 264 ) /* Transmit Pointer Register */ +#define SPI_TCR ( 268 ) /* Transmit Counter Register */ +#define SPI_RNPR ( 272 ) /* Receive Next Pointer Register */ +#define SPI_RNCR ( 276 ) /* Receive Next Counter Register */ +#define SPI_TNPR ( 280 ) /* Transmit Next Pointer Register */ +#define SPI_TNCR ( 284 ) /* Transmit Next Counter Register */ +#define SPI_PTCR ( 288 ) /* PDC Transfer Control Register */ +#define SPI_PTSR ( 292 ) /* PDC Transfer Status Register */ +/* -------- SPI_CR : (SPI Offset: 0x0) SPI Control Register -------- */ +#define AT91C_SPI_SPIEN ( 0x1 << 0 ) /* (SPI) SPI Enable */ +#define AT91C_SPI_SPIDIS ( 0x1 << 1 ) /* (SPI) SPI Disable */ +#define AT91C_SPI_SWRST ( 0x1 << 7 ) /* (SPI) SPI Software reset */ +#define AT91C_SPI_LASTXFER ( 0x1 << 24 ) /* (SPI) SPI Last Transfer */ +/* -------- SPI_MR : (SPI Offset: 0x4) SPI Mode Register -------- */ +#define AT91C_SPI_MSTR ( 0x1 << 0 ) /* (SPI) Master/Slave Mode */ +#define AT91C_SPI_PS ( 0x1 << 1 ) /* (SPI) Peripheral Select */ +#define AT91C_SPI_PS_FIXED ( 0x0 << 1 ) /* (SPI) Fixed Peripheral Select */ +#define AT91C_SPI_PS_VARIABLE ( 0x1 << 1 ) /* (SPI) Variable Peripheral Select */ +#define AT91C_SPI_PCSDEC ( 0x1 << 2 ) /* (SPI) Chip Select Decode */ +#define AT91C_SPI_FDIV ( 0x1 << 3 ) /* (SPI) Clock Selection */ +#define AT91C_SPI_MODFDIS ( 0x1 << 4 ) /* (SPI) Mode Fault Detection */ +#define AT91C_SPI_LLB ( 0x1 << 7 ) /* (SPI) Clock Selection */ +#define AT91C_SPI_PCS ( 0xF << 16 ) /* (SPI) Peripheral Chip Select */ +#define AT91C_SPI_DLYBCS ( 0xFF << 24 ) /* (SPI) Delay Between Chip Selects */ +/* -------- SPI_RDR : (SPI Offset: 0x8) Receive Data Register -------- */ +#define AT91C_SPI_RD ( 0xFFFF << 0 ) /* (SPI) Receive Data */ +#define AT91C_SPI_RPCS ( 0xF << 16 ) /* (SPI) Peripheral Chip Select Status */ +/* -------- SPI_TDR : (SPI Offset: 0xc) Transmit Data Register -------- */ +#define AT91C_SPI_TD ( 0xFFFF << 0 ) /* (SPI) Transmit Data */ +#define AT91C_SPI_TPCS ( 0xF << 16 ) /* (SPI) Peripheral Chip Select Status */ +/* -------- SPI_SR : (SPI Offset: 0x10) Status Register -------- */ +#define AT91C_SPI_RDRF ( 0x1 << 0 ) /* (SPI) Receive Data Register Full */ +#define AT91C_SPI_TDRE ( 0x1 << 1 ) /* (SPI) Transmit Data Register Empty */ +#define AT91C_SPI_MODF ( 0x1 << 2 ) /* (SPI) Mode Fault Error */ +#define AT91C_SPI_OVRES ( 0x1 << 3 ) /* (SPI) Overrun Error Status */ +#define AT91C_SPI_ENDRX ( 0x1 << 4 ) /* (SPI) End of Receiver Transfer */ +#define AT91C_SPI_ENDTX ( 0x1 << 5 ) /* (SPI) End of Receiver Transfer */ +#define AT91C_SPI_RXBUFF ( 0x1 << 6 ) /* (SPI) RXBUFF Interrupt */ +#define AT91C_SPI_TXBUFE ( 0x1 << 7 ) /* (SPI) TXBUFE Interrupt */ +#define AT91C_SPI_NSSR ( 0x1 << 8 ) /* (SPI) NSSR Interrupt */ +#define AT91C_SPI_TXEMPTY ( 0x1 << 9 ) /* (SPI) TXEMPTY Interrupt */ +#define AT91C_SPI_SPIENS ( 0x1 << 16 ) /* (SPI) Enable Status */ +/* -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register -------- */ +/* -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register -------- */ +/* -------- SPI_IMR : (SPI Offset: 0x1c) Interrupt Mask Register -------- */ +/* -------- SPI_CSR : (SPI Offset: 0x30) Chip Select Register -------- */ +#define AT91C_SPI_CPOL ( 0x1 << 0 ) /* (SPI) Clock Polarity */ +#define AT91C_SPI_NCPHA ( 0x1 << 1 ) /* (SPI) Clock Phase */ +#define AT91C_SPI_CSAAT ( 0x1 << 2 ) /* (SPI) Chip Select Active After Transfer */ +#define AT91C_SPI_BITS ( 0xF << 4 ) /* (SPI) Bits Per Transfer */ +#define AT91C_SPI_BITS_8 ( 0x0 << 4 ) /* (SPI) 8 Bits Per transfer */ +#define AT91C_SPI_BITS_9 ( 0x1 << 4 ) /* (SPI) 9 Bits Per transfer */ +#define AT91C_SPI_BITS_10 ( 0x2 << 4 ) /* (SPI) 10 Bits Per transfer */ +#define AT91C_SPI_BITS_11 ( 0x3 << 4 ) /* (SPI) 11 Bits Per transfer */ +#define AT91C_SPI_BITS_12 ( 0x4 << 4 ) /* (SPI) 12 Bits Per transfer */ +#define AT91C_SPI_BITS_13 ( 0x5 << 4 ) /* (SPI) 13 Bits Per transfer */ +#define AT91C_SPI_BITS_14 ( 0x6 << 4 ) /* (SPI) 14 Bits Per transfer */ +#define AT91C_SPI_BITS_15 ( 0x7 << 4 ) /* (SPI) 15 Bits Per transfer */ +#define AT91C_SPI_BITS_16 ( 0x8 << 4 ) /* (SPI) 16 Bits Per transfer */ +#define AT91C_SPI_SCBR ( 0xFF << 8 ) /* (SPI) Serial Clock Baud Rate */ +#define AT91C_SPI_DLYBS ( 0xFF << 16 ) /* (SPI) Serial Clock Baud Rate */ +#define AT91C_SPI_DLYBCT ( 0xFF << 24 ) /* (SPI) Delay Between Consecutive Transfers */ -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Analog to Digital Convertor -// ***************************************************************************** -// *** Register offset in AT91S_ADC structure *** -#define ADC_CR ( 0) // ADC Control Register -#define ADC_MR ( 4) // ADC Mode Register -#define ADC_CHER (16) // ADC Channel Enable Register -#define ADC_CHDR (20) // ADC Channel Disable Register -#define ADC_CHSR (24) // ADC Channel Status Register -#define ADC_SR (28) // ADC Status Register -#define ADC_LCDR (32) // ADC Last Converted Data Register -#define ADC_IER (36) // ADC Interrupt Enable Register -#define ADC_IDR (40) // ADC Interrupt Disable Register -#define ADC_IMR (44) // ADC Interrupt Mask Register -#define ADC_CDR0 (48) // ADC Channel Data Register 0 -#define ADC_CDR1 (52) // ADC Channel Data Register 1 -#define ADC_CDR2 (56) // ADC Channel Data Register 2 -#define ADC_CDR3 (60) // ADC Channel Data Register 3 -#define ADC_CDR4 (64) // ADC Channel Data Register 4 -#define ADC_CDR5 (68) // ADC Channel Data Register 5 -#define ADC_CDR6 (72) // ADC Channel Data Register 6 -#define ADC_CDR7 (76) // ADC Channel Data Register 7 -#define ADC_RPR (256) // Receive Pointer Register -#define ADC_RCR (260) // Receive Counter Register -#define ADC_TPR (264) // Transmit Pointer Register -#define ADC_TCR (268) // Transmit Counter Register -#define ADC_RNPR (272) // Receive Next Pointer Register -#define ADC_RNCR (276) // Receive Next Counter Register -#define ADC_TNPR (280) // Transmit Next Pointer Register -#define ADC_TNCR (284) // Transmit Next Counter Register -#define ADC_PTCR (288) // PDC Transfer Control Register -#define ADC_PTSR (292) // PDC Transfer Status Register -// -------- ADC_CR : (ADC Offset: 0x0) ADC Control Register -------- -#define AT91C_ADC_SWRST (0x1 << 0) // (ADC) Software Reset -#define AT91C_ADC_START (0x1 << 1) // (ADC) Start Conversion -// -------- ADC_MR : (ADC Offset: 0x4) ADC Mode Register -------- -#define AT91C_ADC_TRGEN (0x1 << 0) // (ADC) Trigger Enable -#define AT91C_ADC_TRGEN_DIS (0x0) // (ADC) Hradware triggers are disabled. Starting a conversion is only possible by software -#define AT91C_ADC_TRGEN_EN (0x1) // (ADC) Hardware trigger selected by TRGSEL field is enabled. -#define AT91C_ADC_TRGSEL (0x7 << 1) // (ADC) Trigger Selection -#define AT91C_ADC_TRGSEL_TIOA0 (0x0 << 1) // (ADC) Selected TRGSEL = TIAO0 -#define AT91C_ADC_TRGSEL_TIOA1 (0x1 << 1) // (ADC) Selected TRGSEL = TIAO1 -#define AT91C_ADC_TRGSEL_TIOA2 (0x2 << 1) // (ADC) Selected TRGSEL = TIAO2 -#define AT91C_ADC_TRGSEL_TIOA3 (0x3 << 1) // (ADC) Selected TRGSEL = TIAO3 -#define AT91C_ADC_TRGSEL_TIOA4 (0x4 << 1) // (ADC) Selected TRGSEL = TIAO4 -#define AT91C_ADC_TRGSEL_TIOA5 (0x5 << 1) // (ADC) Selected TRGSEL = TIAO5 -#define AT91C_ADC_TRGSEL_EXT (0x6 << 1) // (ADC) Selected TRGSEL = External Trigger -#define AT91C_ADC_LOWRES (0x1 << 4) // (ADC) Resolution. -#define AT91C_ADC_LOWRES_10_BIT (0x0 << 4) // (ADC) 10-bit resolution -#define AT91C_ADC_LOWRES_8_BIT (0x1 << 4) // (ADC) 8-bit resolution -#define AT91C_ADC_SLEEP (0x1 << 5) // (ADC) Sleep Mode -#define AT91C_ADC_SLEEP_NORMAL_MODE (0x0 << 5) // (ADC) Normal Mode -#define AT91C_ADC_SLEEP_MODE (0x1 << 5) // (ADC) Sleep Mode -#define AT91C_ADC_PRESCAL (0x3F << 8) // (ADC) Prescaler rate selection -#define AT91C_ADC_STARTUP (0x1F << 16) // (ADC) Startup Time -#define AT91C_ADC_SHTIM (0xF << 24) // (ADC) Sample & Hold Time -// -------- ADC_CHER : (ADC Offset: 0x10) ADC Channel Enable Register -------- -#define AT91C_ADC_CH0 (0x1 << 0) // (ADC) Channel 0 -#define AT91C_ADC_CH1 (0x1 << 1) // (ADC) Channel 1 -#define AT91C_ADC_CH2 (0x1 << 2) // (ADC) Channel 2 -#define AT91C_ADC_CH3 (0x1 << 3) // (ADC) Channel 3 -#define AT91C_ADC_CH4 (0x1 << 4) // (ADC) Channel 4 -#define AT91C_ADC_CH5 (0x1 << 5) // (ADC) Channel 5 -#define AT91C_ADC_CH6 (0x1 << 6) // (ADC) Channel 6 -#define AT91C_ADC_CH7 (0x1 << 7) // (ADC) Channel 7 -// -------- ADC_CHDR : (ADC Offset: 0x14) ADC Channel Disable Register -------- -// -------- ADC_CHSR : (ADC Offset: 0x18) ADC Channel Status Register -------- -// -------- ADC_SR : (ADC Offset: 0x1c) ADC Status Register -------- -#define AT91C_ADC_EOC0 (0x1 << 0) // (ADC) End of Conversion -#define AT91C_ADC_EOC1 (0x1 << 1) // (ADC) End of Conversion -#define AT91C_ADC_EOC2 (0x1 << 2) // (ADC) End of Conversion -#define AT91C_ADC_EOC3 (0x1 << 3) // (ADC) End of Conversion -#define AT91C_ADC_EOC4 (0x1 << 4) // (ADC) End of Conversion -#define AT91C_ADC_EOC5 (0x1 << 5) // (ADC) End of Conversion -#define AT91C_ADC_EOC6 (0x1 << 6) // (ADC) End of Conversion -#define AT91C_ADC_EOC7 (0x1 << 7) // (ADC) End of Conversion -#define AT91C_ADC_OVRE0 (0x1 << 8) // (ADC) Overrun Error -#define AT91C_ADC_OVRE1 (0x1 << 9) // (ADC) Overrun Error -#define AT91C_ADC_OVRE2 (0x1 << 10) // (ADC) Overrun Error -#define AT91C_ADC_OVRE3 (0x1 << 11) // (ADC) Overrun Error -#define AT91C_ADC_OVRE4 (0x1 << 12) // (ADC) Overrun Error -#define AT91C_ADC_OVRE5 (0x1 << 13) // (ADC) Overrun Error -#define AT91C_ADC_OVRE6 (0x1 << 14) // (ADC) Overrun Error -#define AT91C_ADC_OVRE7 (0x1 << 15) // (ADC) Overrun Error -#define AT91C_ADC_DRDY (0x1 << 16) // (ADC) Data Ready -#define AT91C_ADC_GOVRE (0x1 << 17) // (ADC) General Overrun -#define AT91C_ADC_ENDRX (0x1 << 18) // (ADC) End of Receiver Transfer -#define AT91C_ADC_RXBUFF (0x1 << 19) // (ADC) RXBUFF Interrupt -// -------- ADC_LCDR : (ADC Offset: 0x20) ADC Last Converted Data Register -------- -#define AT91C_ADC_LDATA (0x3FF << 0) // (ADC) Last Data Converted -// -------- ADC_IER : (ADC Offset: 0x24) ADC Interrupt Enable Register -------- -// -------- ADC_IDR : (ADC Offset: 0x28) ADC Interrupt Disable Register -------- -// -------- ADC_IMR : (ADC Offset: 0x2c) ADC Interrupt Mask Register -------- -// -------- ADC_CDR0 : (ADC Offset: 0x30) ADC Channel Data Register 0 -------- -#define AT91C_ADC_DATA (0x3FF << 0) // (ADC) Converted Data -// -------- ADC_CDR1 : (ADC Offset: 0x34) ADC Channel Data Register 1 -------- -// -------- ADC_CDR2 : (ADC Offset: 0x38) ADC Channel Data Register 2 -------- -// -------- ADC_CDR3 : (ADC Offset: 0x3c) ADC Channel Data Register 3 -------- -// -------- ADC_CDR4 : (ADC Offset: 0x40) ADC Channel Data Register 4 -------- -// -------- ADC_CDR5 : (ADC Offset: 0x44) ADC Channel Data Register 5 -------- -// -------- ADC_CDR6 : (ADC Offset: 0x48) ADC Channel Data Register 6 -------- -// -------- ADC_CDR7 : (ADC Offset: 0x4c) ADC Channel Data Register 7 -------- +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR Analog to Digital Convertor */ +/* ***************************************************************************** */ +/* *** Register offset in AT91S_ADC structure *** */ +#define ADC_CR ( 0 ) /* ADC Control Register */ +#define ADC_MR ( 4 ) /* ADC Mode Register */ +#define ADC_CHER ( 16 ) /* ADC Channel Enable Register */ +#define ADC_CHDR ( 20 ) /* ADC Channel Disable Register */ +#define ADC_CHSR ( 24 ) /* ADC Channel Status Register */ +#define ADC_SR ( 28 ) /* ADC Status Register */ +#define ADC_LCDR ( 32 ) /* ADC Last Converted Data Register */ +#define ADC_IER ( 36 ) /* ADC Interrupt Enable Register */ +#define ADC_IDR ( 40 ) /* ADC Interrupt Disable Register */ +#define ADC_IMR ( 44 ) /* ADC Interrupt Mask Register */ +#define ADC_CDR0 ( 48 ) /* ADC Channel Data Register 0 */ +#define ADC_CDR1 ( 52 ) /* ADC Channel Data Register 1 */ +#define ADC_CDR2 ( 56 ) /* ADC Channel Data Register 2 */ +#define ADC_CDR3 ( 60 ) /* ADC Channel Data Register 3 */ +#define ADC_CDR4 ( 64 ) /* ADC Channel Data Register 4 */ +#define ADC_CDR5 ( 68 ) /* ADC Channel Data Register 5 */ +#define ADC_CDR6 ( 72 ) /* ADC Channel Data Register 6 */ +#define ADC_CDR7 ( 76 ) /* ADC Channel Data Register 7 */ +#define ADC_RPR ( 256 ) /* Receive Pointer Register */ +#define ADC_RCR ( 260 ) /* Receive Counter Register */ +#define ADC_TPR ( 264 ) /* Transmit Pointer Register */ +#define ADC_TCR ( 268 ) /* Transmit Counter Register */ +#define ADC_RNPR ( 272 ) /* Receive Next Pointer Register */ +#define ADC_RNCR ( 276 ) /* Receive Next Counter Register */ +#define ADC_TNPR ( 280 ) /* Transmit Next Pointer Register */ +#define ADC_TNCR ( 284 ) /* Transmit Next Counter Register */ +#define ADC_PTCR ( 288 ) /* PDC Transfer Control Register */ +#define ADC_PTSR ( 292 ) /* PDC Transfer Status Register */ +/* -------- ADC_CR : (ADC Offset: 0x0) ADC Control Register -------- */ +#define AT91C_ADC_SWRST ( 0x1 << 0 ) /* (ADC) Software Reset */ +#define AT91C_ADC_START ( 0x1 << 1 ) /* (ADC) Start Conversion */ +/* -------- ADC_MR : (ADC Offset: 0x4) ADC Mode Register -------- */ +#define AT91C_ADC_TRGEN ( 0x1 << 0 ) /* (ADC) Trigger Enable */ +#define AT91C_ADC_TRGEN_DIS ( 0x0 ) /* (ADC) Hardware triggers are disabled. Starting a conversion is only possible by software */ +#define AT91C_ADC_TRGEN_EN ( 0x1 ) /* (ADC) Hardware trigger selected by TRGSEL field is enabled. */ +#define AT91C_ADC_TRGSEL ( 0x7 << 1 ) /* (ADC) Trigger Selection */ +#define AT91C_ADC_TRGSEL_TIOA0 ( 0x0 << 1 ) /* (ADC) Selected TRGSEL = TIAO0 */ +#define AT91C_ADC_TRGSEL_TIOA1 ( 0x1 << 1 ) /* (ADC) Selected TRGSEL = TIAO1 */ +#define AT91C_ADC_TRGSEL_TIOA2 ( 0x2 << 1 ) /* (ADC) Selected TRGSEL = TIAO2 */ +#define AT91C_ADC_TRGSEL_TIOA3 ( 0x3 << 1 ) /* (ADC) Selected TRGSEL = TIAO3 */ +#define AT91C_ADC_TRGSEL_TIOA4 ( 0x4 << 1 ) /* (ADC) Selected TRGSEL = TIAO4 */ +#define AT91C_ADC_TRGSEL_TIOA5 ( 0x5 << 1 ) /* (ADC) Selected TRGSEL = TIAO5 */ +#define AT91C_ADC_TRGSEL_EXT ( 0x6 << 1 ) /* (ADC) Selected TRGSEL = External Trigger */ +#define AT91C_ADC_LOWRES ( 0x1 << 4 ) /* (ADC) Resolution. */ +#define AT91C_ADC_LOWRES_10_BIT ( 0x0 << 4 ) /* (ADC) 10-bit resolution */ +#define AT91C_ADC_LOWRES_8_BIT ( 0x1 << 4 ) /* (ADC) 8-bit resolution */ +#define AT91C_ADC_SLEEP ( 0x1 << 5 ) /* (ADC) Sleep Mode */ +#define AT91C_ADC_SLEEP_NORMAL_MODE ( 0x0 << 5 ) /* (ADC) Normal Mode */ +#define AT91C_ADC_SLEEP_MODE ( 0x1 << 5 ) /* (ADC) Sleep Mode */ +#define AT91C_ADC_PRESCAL ( 0x3F << 8 ) /* (ADC) Prescaler rate selection */ +#define AT91C_ADC_STARTUP ( 0x1F << 16 ) /* (ADC) Startup Time */ +#define AT91C_ADC_SHTIM ( 0xF << 24 ) /* (ADC) Sample & Hold Time */ +/* -------- ADC_CHER : (ADC Offset: 0x10) ADC Channel Enable Register -------- */ +#define AT91C_ADC_CH0 ( 0x1 << 0 ) /* (ADC) Channel 0 */ +#define AT91C_ADC_CH1 ( 0x1 << 1 ) /* (ADC) Channel 1 */ +#define AT91C_ADC_CH2 ( 0x1 << 2 ) /* (ADC) Channel 2 */ +#define AT91C_ADC_CH3 ( 0x1 << 3 ) /* (ADC) Channel 3 */ +#define AT91C_ADC_CH4 ( 0x1 << 4 ) /* (ADC) Channel 4 */ +#define AT91C_ADC_CH5 ( 0x1 << 5 ) /* (ADC) Channel 5 */ +#define AT91C_ADC_CH6 ( 0x1 << 6 ) /* (ADC) Channel 6 */ +#define AT91C_ADC_CH7 ( 0x1 << 7 ) /* (ADC) Channel 7 */ +/* -------- ADC_CHDR : (ADC Offset: 0x14) ADC Channel Disable Register -------- */ +/* -------- ADC_CHSR : (ADC Offset: 0x18) ADC Channel Status Register -------- */ +/* -------- ADC_SR : (ADC Offset: 0x1c) ADC Status Register -------- */ +#define AT91C_ADC_EOC0 ( 0x1 << 0 ) /* (ADC) End of Conversion */ +#define AT91C_ADC_EOC1 ( 0x1 << 1 ) /* (ADC) End of Conversion */ +#define AT91C_ADC_EOC2 ( 0x1 << 2 ) /* (ADC) End of Conversion */ +#define AT91C_ADC_EOC3 ( 0x1 << 3 ) /* (ADC) End of Conversion */ +#define AT91C_ADC_EOC4 ( 0x1 << 4 ) /* (ADC) End of Conversion */ +#define AT91C_ADC_EOC5 ( 0x1 << 5 ) /* (ADC) End of Conversion */ +#define AT91C_ADC_EOC6 ( 0x1 << 6 ) /* (ADC) End of Conversion */ +#define AT91C_ADC_EOC7 ( 0x1 << 7 ) /* (ADC) End of Conversion */ +#define AT91C_ADC_OVRE0 ( 0x1 << 8 ) /* (ADC) Overrun Error */ +#define AT91C_ADC_OVRE1 ( 0x1 << 9 ) /* (ADC) Overrun Error */ +#define AT91C_ADC_OVRE2 ( 0x1 << 10 ) /* (ADC) Overrun Error */ +#define AT91C_ADC_OVRE3 ( 0x1 << 11 ) /* (ADC) Overrun Error */ +#define AT91C_ADC_OVRE4 ( 0x1 << 12 ) /* (ADC) Overrun Error */ +#define AT91C_ADC_OVRE5 ( 0x1 << 13 ) /* (ADC) Overrun Error */ +#define AT91C_ADC_OVRE6 ( 0x1 << 14 ) /* (ADC) Overrun Error */ +#define AT91C_ADC_OVRE7 ( 0x1 << 15 ) /* (ADC) Overrun Error */ +#define AT91C_ADC_DRDY ( 0x1 << 16 ) /* (ADC) Data Ready */ +#define AT91C_ADC_GOVRE ( 0x1 << 17 ) /* (ADC) General Overrun */ +#define AT91C_ADC_ENDRX ( 0x1 << 18 ) /* (ADC) End of Receiver Transfer */ +#define AT91C_ADC_RXBUFF ( 0x1 << 19 ) /* (ADC) RXBUFF Interrupt */ +/* -------- ADC_LCDR : (ADC Offset: 0x20) ADC Last Converted Data Register -------- */ +#define AT91C_ADC_LDATA ( 0x3FF << 0 ) /* (ADC) Last Data Converted */ +/* -------- ADC_IER : (ADC Offset: 0x24) ADC Interrupt Enable Register -------- */ +/* -------- ADC_IDR : (ADC Offset: 0x28) ADC Interrupt Disable Register -------- */ +/* -------- ADC_IMR : (ADC Offset: 0x2c) ADC Interrupt Mask Register -------- */ +/* -------- ADC_CDR0 : (ADC Offset: 0x30) ADC Channel Data Register 0 -------- */ +#define AT91C_ADC_DATA ( 0x3FF << 0 ) /* (ADC) Converted Data */ +/* -------- ADC_CDR1 : (ADC Offset: 0x34) ADC Channel Data Register 1 -------- */ +/* -------- ADC_CDR2 : (ADC Offset: 0x38) ADC Channel Data Register 2 -------- */ +/* -------- ADC_CDR3 : (ADC Offset: 0x3c) ADC Channel Data Register 3 -------- */ +/* -------- ADC_CDR4 : (ADC Offset: 0x40) ADC Channel Data Register 4 -------- */ +/* -------- ADC_CDR5 : (ADC Offset: 0x44) ADC Channel Data Register 5 -------- */ +/* -------- ADC_CDR6 : (ADC Offset: 0x48) ADC Channel Data Register 6 -------- */ +/* -------- ADC_CDR7 : (ADC Offset: 0x4c) ADC Channel Data Register 7 -------- */ -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Synchronous Serial Controller Interface -// ***************************************************************************** -// *** Register offset in AT91S_SSC structure *** -#define SSC_CR ( 0) // Control Register -#define SSC_CMR ( 4) // Clock Mode Register -#define SSC_RCMR (16) // Receive Clock ModeRegister -#define SSC_RFMR (20) // Receive Frame Mode Register -#define SSC_TCMR (24) // Transmit Clock Mode Register -#define SSC_TFMR (28) // Transmit Frame Mode Register -#define SSC_RHR (32) // Receive Holding Register -#define SSC_THR (36) // Transmit Holding Register -#define SSC_RSHR (48) // Receive Sync Holding Register -#define SSC_TSHR (52) // Transmit Sync Holding Register -#define SSC_RC0R (56) // Receive Compare 0 Register -#define SSC_RC1R (60) // Receive Compare 1 Register -#define SSC_SR (64) // Status Register -#define SSC_IER (68) // Interrupt Enable Register -#define SSC_IDR (72) // Interrupt Disable Register -#define SSC_IMR (76) // Interrupt Mask Register -#define SSC_RPR (256) // Receive Pointer Register -#define SSC_RCR (260) // Receive Counter Register -#define SSC_TPR (264) // Transmit Pointer Register -#define SSC_TCR (268) // Transmit Counter Register -#define SSC_RNPR (272) // Receive Next Pointer Register -#define SSC_RNCR (276) // Receive Next Counter Register -#define SSC_TNPR (280) // Transmit Next Pointer Register -#define SSC_TNCR (284) // Transmit Next Counter Register -#define SSC_PTCR (288) // PDC Transfer Control Register -#define SSC_PTSR (292) // PDC Transfer Status Register -// -------- SSC_CR : (SSC Offset: 0x0) SSC Control Register -------- -#define AT91C_SSC_RXEN (0x1 << 0) // (SSC) Receive Enable -#define AT91C_SSC_RXDIS (0x1 << 1) // (SSC) Receive Disable -#define AT91C_SSC_TXEN (0x1 << 8) // (SSC) Transmit Enable -#define AT91C_SSC_TXDIS (0x1 << 9) // (SSC) Transmit Disable -#define AT91C_SSC_SWRST (0x1 << 15) // (SSC) Software Reset -// -------- SSC_RCMR : (SSC Offset: 0x10) SSC Receive Clock Mode Register -------- -#define AT91C_SSC_CKS (0x3 << 0) // (SSC) Receive/Transmit Clock Selection -#define AT91C_SSC_CKS_DIV (0x0) // (SSC) Divided Clock -#define AT91C_SSC_CKS_TK (0x1) // (SSC) TK Clock signal -#define AT91C_SSC_CKS_RK (0x2) // (SSC) RK pin -#define AT91C_SSC_CKO (0x7 << 2) // (SSC) Receive/Transmit Clock Output Mode Selection -#define AT91C_SSC_CKO_NONE (0x0 << 2) // (SSC) Receive/Transmit Clock Output Mode: None RK pin: Input-only -#define AT91C_SSC_CKO_CONTINOUS (0x1 << 2) // (SSC) Continuous Receive/Transmit Clock RK pin: Output -#define AT91C_SSC_CKO_DATA_TX (0x2 << 2) // (SSC) Receive/Transmit Clock only during data transfers RK pin: Output -#define AT91C_SSC_CKI (0x1 << 5) // (SSC) Receive/Transmit Clock Inversion -#define AT91C_SSC_CKG (0x3 << 6) // (SSC) Receive/Transmit Clock Gating Selection -#define AT91C_SSC_CKG_NONE (0x0 << 6) // (SSC) Receive/Transmit Clock Gating: None, continuous clock -#define AT91C_SSC_CKG_LOW (0x1 << 6) // (SSC) Receive/Transmit Clock enabled only if RF Low -#define AT91C_SSC_CKG_HIGH (0x2 << 6) // (SSC) Receive/Transmit Clock enabled only if RF High -#define AT91C_SSC_START (0xF << 8) // (SSC) Receive/Transmit Start Selection -#define AT91C_SSC_START_CONTINOUS (0x0 << 8) // (SSC) Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data. -#define AT91C_SSC_START_TX (0x1 << 8) // (SSC) Transmit/Receive start -#define AT91C_SSC_START_LOW_RF (0x2 << 8) // (SSC) Detection of a low level on RF input -#define AT91C_SSC_START_HIGH_RF (0x3 << 8) // (SSC) Detection of a high level on RF input -#define AT91C_SSC_START_FALL_RF (0x4 << 8) // (SSC) Detection of a falling edge on RF input -#define AT91C_SSC_START_RISE_RF (0x5 << 8) // (SSC) Detection of a rising edge on RF input -#define AT91C_SSC_START_LEVEL_RF (0x6 << 8) // (SSC) Detection of any level change on RF input -#define AT91C_SSC_START_EDGE_RF (0x7 << 8) // (SSC) Detection of any edge on RF input -#define AT91C_SSC_START_0 (0x8 << 8) // (SSC) Compare 0 -#define AT91C_SSC_STOP (0x1 << 12) // (SSC) Receive Stop Selection -#define AT91C_SSC_STTOUT (0x1 << 15) // (SSC) Receive/Transmit Start Output Selection -#define AT91C_SSC_STTDLY (0xFF << 16) // (SSC) Receive/Transmit Start Delay -#define AT91C_SSC_PERIOD (0xFF << 24) // (SSC) Receive/Transmit Period Divider Selection -// -------- SSC_RFMR : (SSC Offset: 0x14) SSC Receive Frame Mode Register -------- -#define AT91C_SSC_DATLEN (0x1F << 0) // (SSC) Data Length -#define AT91C_SSC_LOOP (0x1 << 5) // (SSC) Loop Mode -#define AT91C_SSC_MSBF (0x1 << 7) // (SSC) Most Significant Bit First -#define AT91C_SSC_DATNB (0xF << 8) // (SSC) Data Number per Frame -#define AT91C_SSC_FSLEN (0xF << 16) // (SSC) Receive/Transmit Frame Sync length -#define AT91C_SSC_FSOS (0x7 << 20) // (SSC) Receive/Transmit Frame Sync Output Selection -#define AT91C_SSC_FSOS_NONE (0x0 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: None RK pin Input-only -#define AT91C_SSC_FSOS_NEGATIVE (0x1 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Negative Pulse -#define AT91C_SSC_FSOS_POSITIVE (0x2 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Positive Pulse -#define AT91C_SSC_FSOS_LOW (0x3 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver Low during data transfer -#define AT91C_SSC_FSOS_HIGH (0x4 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver High during data transfer -#define AT91C_SSC_FSOS_TOGGLE (0x5 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Toggling at each start of data transfer -#define AT91C_SSC_FSEDGE (0x1 << 24) // (SSC) Frame Sync Edge Detection -// -------- SSC_TCMR : (SSC Offset: 0x18) SSC Transmit Clock Mode Register -------- -// -------- SSC_TFMR : (SSC Offset: 0x1c) SSC Transmit Frame Mode Register -------- -#define AT91C_SSC_DATDEF (0x1 << 5) // (SSC) Data Default Value -#define AT91C_SSC_FSDEN (0x1 << 23) // (SSC) Frame Sync Data Enable -// -------- SSC_SR : (SSC Offset: 0x40) SSC Status Register -------- -#define AT91C_SSC_TXRDY (0x1 << 0) // (SSC) Transmit Ready -#define AT91C_SSC_TXEMPTY (0x1 << 1) // (SSC) Transmit Empty -#define AT91C_SSC_ENDTX (0x1 << 2) // (SSC) End Of Transmission -#define AT91C_SSC_TXBUFE (0x1 << 3) // (SSC) Transmit Buffer Empty -#define AT91C_SSC_RXRDY (0x1 << 4) // (SSC) Receive Ready -#define AT91C_SSC_OVRUN (0x1 << 5) // (SSC) Receive Overrun -#define AT91C_SSC_ENDRX (0x1 << 6) // (SSC) End of Reception -#define AT91C_SSC_RXBUFF (0x1 << 7) // (SSC) Receive Buffer Full -#define AT91C_SSC_CP0 (0x1 << 8) // (SSC) Compare 0 -#define AT91C_SSC_CP1 (0x1 << 9) // (SSC) Compare 1 -#define AT91C_SSC_TXSYN (0x1 << 10) // (SSC) Transmit Sync -#define AT91C_SSC_RXSYN (0x1 << 11) // (SSC) Receive Sync -#define AT91C_SSC_TXENA (0x1 << 16) // (SSC) Transmit Enable -#define AT91C_SSC_RXENA (0x1 << 17) // (SSC) Receive Enable -// -------- SSC_IER : (SSC Offset: 0x44) SSC Interrupt Enable Register -------- -// -------- SSC_IDR : (SSC Offset: 0x48) SSC Interrupt Disable Register -------- -// -------- SSC_IMR : (SSC Offset: 0x4c) SSC Interrupt Mask Register -------- +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR Synchronous Serial Controller Interface */ +/* ***************************************************************************** */ +/* *** Register offset in AT91S_SSC structure *** */ +#define SSC_CR ( 0 ) /* Control Register */ +#define SSC_CMR ( 4 ) /* Clock Mode Register */ +#define SSC_RCMR ( 16 ) /* Receive Clock ModeRegister */ +#define SSC_RFMR ( 20 ) /* Receive Frame Mode Register */ +#define SSC_TCMR ( 24 ) /* Transmit Clock Mode Register */ +#define SSC_TFMR ( 28 ) /* Transmit Frame Mode Register */ +#define SSC_RHR ( 32 ) /* Receive Holding Register */ +#define SSC_THR ( 36 ) /* Transmit Holding Register */ +#define SSC_RSHR ( 48 ) /* Receive Sync Holding Register */ +#define SSC_TSHR ( 52 ) /* Transmit Sync Holding Register */ +#define SSC_RC0R ( 56 ) /* Receive Compare 0 Register */ +#define SSC_RC1R ( 60 ) /* Receive Compare 1 Register */ +#define SSC_SR ( 64 ) /* Status Register */ +#define SSC_IER ( 68 ) /* Interrupt Enable Register */ +#define SSC_IDR ( 72 ) /* Interrupt Disable Register */ +#define SSC_IMR ( 76 ) /* Interrupt Mask Register */ +#define SSC_RPR ( 256 ) /* Receive Pointer Register */ +#define SSC_RCR ( 260 ) /* Receive Counter Register */ +#define SSC_TPR ( 264 ) /* Transmit Pointer Register */ +#define SSC_TCR ( 268 ) /* Transmit Counter Register */ +#define SSC_RNPR ( 272 ) /* Receive Next Pointer Register */ +#define SSC_RNCR ( 276 ) /* Receive Next Counter Register */ +#define SSC_TNPR ( 280 ) /* Transmit Next Pointer Register */ +#define SSC_TNCR ( 284 ) /* Transmit Next Counter Register */ +#define SSC_PTCR ( 288 ) /* PDC Transfer Control Register */ +#define SSC_PTSR ( 292 ) /* PDC Transfer Status Register */ +/* -------- SSC_CR : (SSC Offset: 0x0) SSC Control Register -------- */ +#define AT91C_SSC_RXEN ( 0x1 << 0 ) /* (SSC) Receive Enable */ +#define AT91C_SSC_RXDIS ( 0x1 << 1 ) /* (SSC) Receive Disable */ +#define AT91C_SSC_TXEN ( 0x1 << 8 ) /* (SSC) Transmit Enable */ +#define AT91C_SSC_TXDIS ( 0x1 << 9 ) /* (SSC) Transmit Disable */ +#define AT91C_SSC_SWRST ( 0x1 << 15 ) /* (SSC) Software Reset */ +/* -------- SSC_RCMR : (SSC Offset: 0x10) SSC Receive Clock Mode Register -------- */ +#define AT91C_SSC_CKS ( 0x3 << 0 ) /* (SSC) Receive/Transmit Clock Selection */ +#define AT91C_SSC_CKS_DIV ( 0x0 ) /* (SSC) Divided Clock */ +#define AT91C_SSC_CKS_TK ( 0x1 ) /* (SSC) TK Clock signal */ +#define AT91C_SSC_CKS_RK ( 0x2 ) /* (SSC) RK pin */ +#define AT91C_SSC_CKO ( 0x7 << 2 ) /* (SSC) Receive/Transmit Clock Output Mode Selection */ +#define AT91C_SSC_CKO_NONE ( 0x0 << 2 ) /* (SSC) Receive/Transmit Clock Output Mode: None RK pin: Input-only */ +#define AT91C_SSC_CKO_CONTINUOUS ( 0x1 << 2 ) /* (SSC) Continuous Receive/Transmit Clock RK pin: Output */ +#define AT91C_SSC_CKO_DATA_TX ( 0x2 << 2 ) /* (SSC) Receive/Transmit Clock only during data transfers RK pin: Output */ +#define AT91C_SSC_CKI ( 0x1 << 5 ) /* (SSC) Receive/Transmit Clock Inversion */ +#define AT91C_SSC_CKG ( 0x3 << 6 ) /* (SSC) Receive/Transmit Clock Gating Selection */ +#define AT91C_SSC_CKG_NONE ( 0x0 << 6 ) /* (SSC) Receive/Transmit Clock Gating: None, continuous clock */ +#define AT91C_SSC_CKG_LOW ( 0x1 << 6 ) /* (SSC) Receive/Transmit Clock enabled only if RF Low */ +#define AT91C_SSC_CKG_HIGH ( 0x2 << 6 ) /* (SSC) Receive/Transmit Clock enabled only if RF High */ +#define AT91C_SSC_START ( 0xF << 8 ) /* (SSC) Receive/Transmit Start Selection */ +#define AT91C_SSC_START_CONTINUOUS ( 0x0 << 8 ) /* (SSC) Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data. */ +#define AT91C_SSC_START_TX ( 0x1 << 8 ) /* (SSC) Transmit/Receive start */ +#define AT91C_SSC_START_LOW_RF ( 0x2 << 8 ) /* (SSC) Detection of a low level on RF input */ +#define AT91C_SSC_START_HIGH_RF ( 0x3 << 8 ) /* (SSC) Detection of a high level on RF input */ +#define AT91C_SSC_START_FALL_RF ( 0x4 << 8 ) /* (SSC) Detection of a falling edge on RF input */ +#define AT91C_SSC_START_RISE_RF ( 0x5 << 8 ) /* (SSC) Detection of a rising edge on RF input */ +#define AT91C_SSC_START_LEVEL_RF ( 0x6 << 8 ) /* (SSC) Detection of any level change on RF input */ +#define AT91C_SSC_START_EDGE_RF ( 0x7 << 8 ) /* (SSC) Detection of any edge on RF input */ +#define AT91C_SSC_START_0 ( 0x8 << 8 ) /* (SSC) Compare 0 */ +#define AT91C_SSC_STOP ( 0x1 << 12 ) /* (SSC) Receive Stop Selection */ +#define AT91C_SSC_STTOUT ( 0x1 << 15 ) /* (SSC) Receive/Transmit Start Output Selection */ +#define AT91C_SSC_STTDLY ( 0xFF << 16 ) /* (SSC) Receive/Transmit Start Delay */ +#define AT91C_SSC_PERIOD ( 0xFF << 24 ) /* (SSC) Receive/Transmit Period Divider Selection */ +/* -------- SSC_RFMR : (SSC Offset: 0x14) SSC Receive Frame Mode Register -------- */ +#define AT91C_SSC_DATLEN ( 0x1F << 0 ) /* (SSC) Data Length */ +#define AT91C_SSC_LOOP ( 0x1 << 5 ) /* (SSC) Loop Mode */ +#define AT91C_SSC_MSBF ( 0x1 << 7 ) /* (SSC) Most Significant Bit First */ +#define AT91C_SSC_DATNB ( 0xF << 8 ) /* (SSC) Data Number per Frame */ +#define AT91C_SSC_FSLEN ( 0xF << 16 ) /* (SSC) Receive/Transmit Frame Sync length */ +#define AT91C_SSC_FSOS ( 0x7 << 20 ) /* (SSC) Receive/Transmit Frame Sync Output Selection */ +#define AT91C_SSC_FSOS_NONE ( 0x0 << 20 ) /* (SSC) Selected Receive/Transmit Frame Sync Signal: None RK pin Input-only */ +#define AT91C_SSC_FSOS_NEGATIVE ( 0x1 << 20 ) /* (SSC) Selected Receive/Transmit Frame Sync Signal: Negative Pulse */ +#define AT91C_SSC_FSOS_POSITIVE ( 0x2 << 20 ) /* (SSC) Selected Receive/Transmit Frame Sync Signal: Positive Pulse */ +#define AT91C_SSC_FSOS_LOW ( 0x3 << 20 ) /* (SSC) Selected Receive/Transmit Frame Sync Signal: Driver Low during data transfer */ +#define AT91C_SSC_FSOS_HIGH ( 0x4 << 20 ) /* (SSC) Selected Receive/Transmit Frame Sync Signal: Driver High during data transfer */ +#define AT91C_SSC_FSOS_TOGGLE ( 0x5 << 20 ) /* (SSC) Selected Receive/Transmit Frame Sync Signal: Toggling at each start of data transfer */ +#define AT91C_SSC_FSEDGE ( 0x1 << 24 ) /* (SSC) Frame Sync Edge Detection */ +/* -------- SSC_TCMR : (SSC Offset: 0x18) SSC Transmit Clock Mode Register -------- */ +/* -------- SSC_TFMR : (SSC Offset: 0x1c) SSC Transmit Frame Mode Register -------- */ +#define AT91C_SSC_DATDEF ( 0x1 << 5 ) /* (SSC) Data Default Value */ +#define AT91C_SSC_FSDEN ( 0x1 << 23 ) /* (SSC) Frame Sync Data Enable */ +/* -------- SSC_SR : (SSC Offset: 0x40) SSC Status Register -------- */ +#define AT91C_SSC_TXRDY ( 0x1 << 0 ) /* (SSC) Transmit Ready */ +#define AT91C_SSC_TXEMPTY ( 0x1 << 1 ) /* (SSC) Transmit Empty */ +#define AT91C_SSC_ENDTX ( 0x1 << 2 ) /* (SSC) End Of Transmission */ +#define AT91C_SSC_TXBUFE ( 0x1 << 3 ) /* (SSC) Transmit Buffer Empty */ +#define AT91C_SSC_RXRDY ( 0x1 << 4 ) /* (SSC) Receive Ready */ +#define AT91C_SSC_OVRUN ( 0x1 << 5 ) /* (SSC) Receive Overrun */ +#define AT91C_SSC_ENDRX ( 0x1 << 6 ) /* (SSC) End of Reception */ +#define AT91C_SSC_RXBUFF ( 0x1 << 7 ) /* (SSC) Receive Buffer Full */ +#define AT91C_SSC_CP0 ( 0x1 << 8 ) /* (SSC) Compare 0 */ +#define AT91C_SSC_CP1 ( 0x1 << 9 ) /* (SSC) Compare 1 */ +#define AT91C_SSC_TXSYN ( 0x1 << 10 ) /* (SSC) Transmit Sync */ +#define AT91C_SSC_RXSYN ( 0x1 << 11 ) /* (SSC) Receive Sync */ +#define AT91C_SSC_TXENA ( 0x1 << 16 ) /* (SSC) Transmit Enable */ +#define AT91C_SSC_RXENA ( 0x1 << 17 ) /* (SSC) Receive Enable */ +/* -------- SSC_IER : (SSC Offset: 0x44) SSC Interrupt Enable Register -------- */ +/* -------- SSC_IDR : (SSC Offset: 0x48) SSC Interrupt Disable Register -------- */ +/* -------- SSC_IMR : (SSC Offset: 0x4c) SSC Interrupt Mask Register -------- */ -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Usart -// ***************************************************************************** -// *** Register offset in AT91S_USART structure *** -#define US_CR ( 0) // Control Register -#define US_MR ( 4) // Mode Register -#define US_IER ( 8) // Interrupt Enable Register -#define US_IDR (12) // Interrupt Disable Register -#define US_IMR (16) // Interrupt Mask Register -#define US_CSR (20) // Channel Status Register -#define US_RHR (24) // Receiver Holding Register -#define US_THR (28) // Transmitter Holding Register -#define US_BRGR (32) // Baud Rate Generator Register -#define US_RTOR (36) // Receiver Time-out Register -#define US_TTGR (40) // Transmitter Time-guard Register -#define US_FIDI (64) // FI_DI_Ratio Register -#define US_NER (68) // Nb Errors Register -#define US_XXR (72) // XON_XOFF Register -#define US_IF (76) // IRDA_FILTER Register -#define US_RPR (256) // Receive Pointer Register -#define US_RCR (260) // Receive Counter Register -#define US_TPR (264) // Transmit Pointer Register -#define US_TCR (268) // Transmit Counter Register -#define US_RNPR (272) // Receive Next Pointer Register -#define US_RNCR (276) // Receive Next Counter Register -#define US_TNPR (280) // Transmit Next Pointer Register -#define US_TNCR (284) // Transmit Next Counter Register -#define US_PTCR (288) // PDC Transfer Control Register -#define US_PTSR (292) // PDC Transfer Status Register -// -------- US_CR : (USART Offset: 0x0) Debug Unit Control Register -------- -#define AT91C_US_RSTSTA (0x1 << 8) // (USART) Reset Status Bits -#define AT91C_US_STTBRK (0x1 << 9) // (USART) Start Break -#define AT91C_US_STPBRK (0x1 << 10) // (USART) Stop Break -#define AT91C_US_STTTO (0x1 << 11) // (USART) Start Time-out -#define AT91C_US_SENDA (0x1 << 12) // (USART) Send Address -#define AT91C_US_RSTIT (0x1 << 13) // (USART) Reset Iterations -#define AT91C_US_RSTNACK (0x1 << 14) // (USART) Reset Non Acknowledge -#define AT91C_US_RETTO (0x1 << 15) // (USART) Rearm Time-out -#define AT91C_US_DTREN (0x1 << 16) // (USART) Data Terminal ready Enable -#define AT91C_US_DTRDIS (0x1 << 17) // (USART) Data Terminal ready Disable -#define AT91C_US_RTSEN (0x1 << 18) // (USART) Request to Send enable -#define AT91C_US_RTSDIS (0x1 << 19) // (USART) Request to Send Disable -// -------- US_MR : (USART Offset: 0x4) Debug Unit Mode Register -------- -#define AT91C_US_USMODE (0xF << 0) // (USART) Usart mode -#define AT91C_US_USMODE_NORMAL (0x0) // (USART) Normal -#define AT91C_US_USMODE_RS485 (0x1) // (USART) RS485 -#define AT91C_US_USMODE_HWHSH (0x2) // (USART) Hardware Handshaking -#define AT91C_US_USMODE_MODEM (0x3) // (USART) Modem -#define AT91C_US_USMODE_ISO7816_0 (0x4) // (USART) ISO7816 protocol: T = 0 -#define AT91C_US_USMODE_ISO7816_1 (0x6) // (USART) ISO7816 protocol: T = 1 -#define AT91C_US_USMODE_IRDA (0x8) // (USART) IrDA -#define AT91C_US_USMODE_SWHSH (0xC) // (USART) Software Handshaking -#define AT91C_US_CLKS (0x3 << 4) // (USART) Clock Selection (Baud Rate generator Input Clock -#define AT91C_US_CLKS_CLOCK (0x0 << 4) // (USART) Clock -#define AT91C_US_CLKS_FDIV1 (0x1 << 4) // (USART) fdiv1 -#define AT91C_US_CLKS_SLOW (0x2 << 4) // (USART) slow_clock (ARM) -#define AT91C_US_CLKS_EXT (0x3 << 4) // (USART) External (SCK) -#define AT91C_US_CHRL (0x3 << 6) // (USART) Clock Selection (Baud Rate generator Input Clock -#define AT91C_US_CHRL_5_BITS (0x0 << 6) // (USART) Character Length: 5 bits -#define AT91C_US_CHRL_6_BITS (0x1 << 6) // (USART) Character Length: 6 bits -#define AT91C_US_CHRL_7_BITS (0x2 << 6) // (USART) Character Length: 7 bits -#define AT91C_US_CHRL_8_BITS (0x3 << 6) // (USART) Character Length: 8 bits -#define AT91C_US_SYNC (0x1 << 8) // (USART) Synchronous Mode Select -#define AT91C_US_NBSTOP (0x3 << 12) // (USART) Number of Stop bits -#define AT91C_US_NBSTOP_1_BIT (0x0 << 12) // (USART) 1 stop bit -#define AT91C_US_NBSTOP_15_BIT (0x1 << 12) // (USART) Asynchronous (SYNC=0) 2 stop bits Synchronous (SYNC=1) 2 stop bits -#define AT91C_US_NBSTOP_2_BIT (0x2 << 12) // (USART) 2 stop bits -#define AT91C_US_MSBF (0x1 << 16) // (USART) Bit Order -#define AT91C_US_MODE9 (0x1 << 17) // (USART) 9-bit Character length -#define AT91C_US_CKLO (0x1 << 18) // (USART) Clock Output Select -#define AT91C_US_OVER (0x1 << 19) // (USART) Over Sampling Mode -#define AT91C_US_INACK (0x1 << 20) // (USART) Inhibit Non Acknowledge -#define AT91C_US_DSNACK (0x1 << 21) // (USART) Disable Successive NACK -#define AT91C_US_MAX_ITER (0x1 << 24) // (USART) Number of Repetitions -#define AT91C_US_FILTER (0x1 << 28) // (USART) Receive Line Filter -// -------- US_IER : (USART Offset: 0x8) Debug Unit Interrupt Enable Register -------- -#define AT91C_US_RXBRK (0x1 << 2) // (USART) Break Received/End of Break -#define AT91C_US_TIMEOUT (0x1 << 8) // (USART) Receiver Time-out -#define AT91C_US_ITERATION (0x1 << 10) // (USART) Max number of Repetitions Reached -#define AT91C_US_NACK (0x1 << 13) // (USART) Non Acknowledge -#define AT91C_US_RIIC (0x1 << 16) // (USART) Ring INdicator Input Change Flag -#define AT91C_US_DSRIC (0x1 << 17) // (USART) Data Set Ready Input Change Flag -#define AT91C_US_DCDIC (0x1 << 18) // (USART) Data Carrier Flag -#define AT91C_US_CTSIC (0x1 << 19) // (USART) Clear To Send Input Change Flag -// -------- US_IDR : (USART Offset: 0xc) Debug Unit Interrupt Disable Register -------- -// -------- US_IMR : (USART Offset: 0x10) Debug Unit Interrupt Mask Register -------- -// -------- US_CSR : (USART Offset: 0x14) Debug Unit Channel Status Register -------- -#define AT91C_US_RI (0x1 << 20) // (USART) Image of RI Input -#define AT91C_US_DSR (0x1 << 21) // (USART) Image of DSR Input -#define AT91C_US_DCD (0x1 << 22) // (USART) Image of DCD Input -#define AT91C_US_CTS (0x1 << 23) // (USART) Image of CTS Input +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR Usart */ +/* ***************************************************************************** */ +/* *** Register offset in AT91S_USART structure *** */ +#define US_CR ( 0 ) /* Control Register */ +#define US_MR ( 4 ) /* Mode Register */ +#define US_IER ( 8 ) /* Interrupt Enable Register */ +#define US_IDR ( 12 ) /* Interrupt Disable Register */ +#define US_IMR ( 16 ) /* Interrupt Mask Register */ +#define US_CSR ( 20 ) /* Channel Status Register */ +#define US_RHR ( 24 ) /* Receiver Holding Register */ +#define US_THR ( 28 ) /* Transmitter Holding Register */ +#define US_BRGR ( 32 ) /* Baud Rate Generator Register */ +#define US_RTOR ( 36 ) /* Receiver Time-out Register */ +#define US_TTGR ( 40 ) /* Transmitter Time-guard Register */ +#define US_FIDI ( 64 ) /* FI_DI_Ratio Register */ +#define US_NER ( 68 ) /* Nb Errors Register */ +#define US_XXR ( 72 ) /* XON_XOFF Register */ +#define US_IF ( 76 ) /* IRDA_FILTER Register */ +#define US_RPR ( 256 ) /* Receive Pointer Register */ +#define US_RCR ( 260 ) /* Receive Counter Register */ +#define US_TPR ( 264 ) /* Transmit Pointer Register */ +#define US_TCR ( 268 ) /* Transmit Counter Register */ +#define US_RNPR ( 272 ) /* Receive Next Pointer Register */ +#define US_RNCR ( 276 ) /* Receive Next Counter Register */ +#define US_TNPR ( 280 ) /* Transmit Next Pointer Register */ +#define US_TNCR ( 284 ) /* Transmit Next Counter Register */ +#define US_PTCR ( 288 ) /* PDC Transfer Control Register */ +#define US_PTSR ( 292 ) /* PDC Transfer Status Register */ +/* -------- US_CR : (USART Offset: 0x0) Debug Unit Control Register -------- */ +#define AT91C_US_RSTSTA ( 0x1 << 8 ) /* (USART) Reset Status Bits */ +#define AT91C_US_STTBRK ( 0x1 << 9 ) /* (USART) Start Break */ +#define AT91C_US_STPBRK ( 0x1 << 10 ) /* (USART) Stop Break */ +#define AT91C_US_STTTO ( 0x1 << 11 ) /* (USART) Start Time-out */ +#define AT91C_US_SENDA ( 0x1 << 12 ) /* (USART) Send Address */ +#define AT91C_US_RSTIT ( 0x1 << 13 ) /* (USART) Reset Iterations */ +#define AT91C_US_RSTNACK ( 0x1 << 14 ) /* (USART) Reset Non Acknowledge */ +#define AT91C_US_RETTO ( 0x1 << 15 ) /* (USART) Rearm Time-out */ +#define AT91C_US_DTREN ( 0x1 << 16 ) /* (USART) Data Terminal ready Enable */ +#define AT91C_US_DTRDIS ( 0x1 << 17 ) /* (USART) Data Terminal ready Disable */ +#define AT91C_US_RTSEN ( 0x1 << 18 ) /* (USART) Request to Send enable */ +#define AT91C_US_RTSDIS ( 0x1 << 19 ) /* (USART) Request to Send Disable */ +/* -------- US_MR : (USART Offset: 0x4) Debug Unit Mode Register -------- */ +#define AT91C_US_USMODE ( 0xF << 0 ) /* (USART) Usart mode */ +#define AT91C_US_USMODE_NORMAL ( 0x0 ) /* (USART) Normal */ +#define AT91C_US_USMODE_RS485 ( 0x1 ) /* (USART) RS485 */ +#define AT91C_US_USMODE_HWHSH ( 0x2 ) /* (USART) Hardware Handshaking */ +#define AT91C_US_USMODE_MODEM ( 0x3 ) /* (USART) Modem */ +#define AT91C_US_USMODE_ISO7816_0 ( 0x4 ) /* (USART) ISO7816 protocol: T = 0 */ +#define AT91C_US_USMODE_ISO7816_1 ( 0x6 ) /* (USART) ISO7816 protocol: T = 1 */ +#define AT91C_US_USMODE_IRDA ( 0x8 ) /* (USART) IrDA */ +#define AT91C_US_USMODE_SWHSH ( 0xC ) /* (USART) Software Handshaking */ +#define AT91C_US_CLKS ( 0x3 << 4 ) /* (USART) Clock Selection (Baud Rate generator Input Clock */ +#define AT91C_US_CLKS_CLOCK ( 0x0 << 4 ) /* (USART) Clock */ +#define AT91C_US_CLKS_FDIV1 ( 0x1 << 4 ) /* (USART) fdiv1 */ +#define AT91C_US_CLKS_SLOW ( 0x2 << 4 ) /* (USART) slow_clock (ARM) */ +#define AT91C_US_CLKS_EXT ( 0x3 << 4 ) /* (USART) External (SCK) */ +#define AT91C_US_CHRL ( 0x3 << 6 ) /* (USART) Clock Selection (Baud Rate generator Input Clock */ +#define AT91C_US_CHRL_5_BITS ( 0x0 << 6 ) /* (USART) Character Length: 5 bits */ +#define AT91C_US_CHRL_6_BITS ( 0x1 << 6 ) /* (USART) Character Length: 6 bits */ +#define AT91C_US_CHRL_7_BITS ( 0x2 << 6 ) /* (USART) Character Length: 7 bits */ +#define AT91C_US_CHRL_8_BITS ( 0x3 << 6 ) /* (USART) Character Length: 8 bits */ +#define AT91C_US_SYNC ( 0x1 << 8 ) /* (USART) Synchronous Mode Select */ +#define AT91C_US_NBSTOP ( 0x3 << 12 ) /* (USART) Number of Stop bits */ +#define AT91C_US_NBSTOP_1_BIT ( 0x0 << 12 ) /* (USART) 1 stop bit */ +#define AT91C_US_NBSTOP_15_BIT ( 0x1 << 12 ) /* (USART) Asynchronous (SYNC=0) 2 stop bits Synchronous (SYNC=1) 2 stop bits */ +#define AT91C_US_NBSTOP_2_BIT ( 0x2 << 12 ) /* (USART) 2 stop bits */ +#define AT91C_US_MSBF ( 0x1 << 16 ) /* (USART) Bit Order */ +#define AT91C_US_MODE9 ( 0x1 << 17 ) /* (USART) 9-bit Character length */ +#define AT91C_US_CKLO ( 0x1 << 18 ) /* (USART) Clock Output Select */ +#define AT91C_US_OVER ( 0x1 << 19 ) /* (USART) Over Sampling Mode */ +#define AT91C_US_INACK ( 0x1 << 20 ) /* (USART) Inhibit Non Acknowledge */ +#define AT91C_US_DSNACK ( 0x1 << 21 ) /* (USART) Disable Successive NACK */ +#define AT91C_US_MAX_ITER ( 0x1 << 24 ) /* (USART) Number of Repetitions */ +#define AT91C_US_FILTER ( 0x1 << 28 ) /* (USART) Receive Line Filter */ +/* -------- US_IER : (USART Offset: 0x8) Debug Unit Interrupt Enable Register -------- */ +#define AT91C_US_RXBRK ( 0x1 << 2 ) /* (USART) Break Received/End of Break */ +#define AT91C_US_TIMEOUT ( 0x1 << 8 ) /* (USART) Receiver Time-out */ +#define AT91C_US_ITERATION ( 0x1 << 10 ) /* (USART) Max number of Repetitions Reached */ +#define AT91C_US_NACK ( 0x1 << 13 ) /* (USART) Non Acknowledge */ +#define AT91C_US_RIIC ( 0x1 << 16 ) /* (USART) Ring INdicator Input Change Flag */ +#define AT91C_US_DSRIC ( 0x1 << 17 ) /* (USART) Data Set Ready Input Change Flag */ +#define AT91C_US_DCDIC ( 0x1 << 18 ) /* (USART) Data Carrier Flag */ +#define AT91C_US_CTSIC ( 0x1 << 19 ) /* (USART) Clear To Send Input Change Flag */ +/* -------- US_IDR : (USART Offset: 0xc) Debug Unit Interrupt Disable Register -------- */ +/* -------- US_IMR : (USART Offset: 0x10) Debug Unit Interrupt Mask Register -------- */ +/* -------- US_CSR : (USART Offset: 0x14) Debug Unit Channel Status Register -------- */ +#define AT91C_US_RI ( 0x1 << 20 ) /* (USART) Image of RI Input */ +#define AT91C_US_DSR ( 0x1 << 21 ) /* (USART) Image of DSR Input */ +#define AT91C_US_DCD ( 0x1 << 22 ) /* (USART) Image of DCD Input */ +#define AT91C_US_CTS ( 0x1 << 23 ) /* (USART) Image of CTS Input */ -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Two-wire Interface -// ***************************************************************************** -// *** Register offset in AT91S_TWI structure *** -#define TWI_CR ( 0) // Control Register -#define TWI_MMR ( 4) // Master Mode Register -#define TWI_SMR ( 8) // Slave Mode Register -#define TWI_IADR (12) // Internal Address Register -#define TWI_CWGR (16) // Clock Waveform Generator Register -#define TWI_SR (32) // Status Register -#define TWI_IER (36) // Interrupt Enable Register -#define TWI_IDR (40) // Interrupt Disable Register -#define TWI_IMR (44) // Interrupt Mask Register -#define TWI_RHR (48) // Receive Holding Register -#define TWI_THR (52) // Transmit Holding Register -// -------- TWI_CR : (TWI Offset: 0x0) TWI Control Register -------- -#define AT91C_TWI_START (0x1 << 0) // (TWI) Send a START Condition -#define AT91C_TWI_STOP (0x1 << 1) // (TWI) Send a STOP Condition -#define AT91C_TWI_MSEN (0x1 << 2) // (TWI) TWI Master Transfer Enabled -#define AT91C_TWI_MSDIS (0x1 << 3) // (TWI) TWI Master Transfer Disabled -#define AT91C_TWI_SVEN (0x1 << 4) // (TWI) TWI Slave Transfer Enabled -#define AT91C_TWI_SVDIS (0x1 << 5) // (TWI) TWI Slave Transfer Disabled -#define AT91C_TWI_SWRST (0x1 << 7) // (TWI) Software Reset -// -------- TWI_MMR : (TWI Offset: 0x4) TWI Master Mode Register -------- -#define AT91C_TWI_IADRSZ (0x3 << 8) // (TWI) Internal Device Address Size -#define AT91C_TWI_IADRSZ_NO (0x0 << 8) // (TWI) No internal device address -#define AT91C_TWI_IADRSZ_1_BYTE (0x1 << 8) // (TWI) One-byte internal device address -#define AT91C_TWI_IADRSZ_2_BYTE (0x2 << 8) // (TWI) Two-byte internal device address -#define AT91C_TWI_IADRSZ_3_BYTE (0x3 << 8) // (TWI) Three-byte internal device address -#define AT91C_TWI_MREAD (0x1 << 12) // (TWI) Master Read Direction -#define AT91C_TWI_DADR (0x7F << 16) // (TWI) Device Address -// -------- TWI_SMR : (TWI Offset: 0x8) TWI Slave Mode Register -------- -#define AT91C_TWI_SADR (0x7F << 16) // (TWI) Slave Device Address -// -------- TWI_CWGR : (TWI Offset: 0x10) TWI Clock Waveform Generator Register -------- -#define AT91C_TWI_CLDIV (0xFF << 0) // (TWI) Clock Low Divider -#define AT91C_TWI_CHDIV (0xFF << 8) // (TWI) Clock High Divider -#define AT91C_TWI_CKDIV (0x7 << 16) // (TWI) Clock Divider -// -------- TWI_SR : (TWI Offset: 0x20) TWI Status Register -------- -#define AT91C_TWI_TXCOMP (0x1 << 0) // (TWI) Transmission Completed -#define AT91C_TWI_RXRDY (0x1 << 1) // (TWI) Receive holding register ReaDY -#define AT91C_TWI_TXRDY (0x1 << 2) // (TWI) Transmit holding register ReaDY -#define AT91C_TWI_SVREAD (0x1 << 3) // (TWI) Slave Read -#define AT91C_TWI_SVACC (0x1 << 4) // (TWI) Slave Access -#define AT91C_TWI_GCACC (0x1 << 5) // (TWI) General Call Access -#define AT91C_TWI_OVRE (0x1 << 6) // (TWI) Overrun Error -#define AT91C_TWI_UNRE (0x1 << 7) // (TWI) Underrun Error -#define AT91C_TWI_NACK (0x1 << 8) // (TWI) Not Acknowledged -#define AT91C_TWI_ARBLST (0x1 << 9) // (TWI) Arbitration Lost -// -------- TWI_IER : (TWI Offset: 0x24) TWI Interrupt Enable Register -------- -// -------- TWI_IDR : (TWI Offset: 0x28) TWI Interrupt Disable Register -------- -// -------- TWI_IMR : (TWI Offset: 0x2c) TWI Interrupt Mask Register -------- +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR Two-wire Interface */ +/* ***************************************************************************** */ +/* *** Register offset in AT91S_TWI structure *** */ +#define TWI_CR ( 0 ) /* Control Register */ +#define TWI_MMR ( 4 ) /* Master Mode Register */ +#define TWI_SMR ( 8 ) /* Slave Mode Register */ +#define TWI_IADR ( 12 ) /* Internal Address Register */ +#define TWI_CWGR ( 16 ) /* Clock Waveform Generator Register */ +#define TWI_SR ( 32 ) /* Status Register */ +#define TWI_IER ( 36 ) /* Interrupt Enable Register */ +#define TWI_IDR ( 40 ) /* Interrupt Disable Register */ +#define TWI_IMR ( 44 ) /* Interrupt Mask Register */ +#define TWI_RHR ( 48 ) /* Receive Holding Register */ +#define TWI_THR ( 52 ) /* Transmit Holding Register */ +/* -------- TWI_CR : (TWI Offset: 0x0) TWI Control Register -------- */ +#define AT91C_TWI_START ( 0x1 << 0 ) /* (TWI) Send a START Condition */ +#define AT91C_TWI_STOP ( 0x1 << 1 ) /* (TWI) Send a STOP Condition */ +#define AT91C_TWI_MSEN ( 0x1 << 2 ) /* (TWI) TWI Master Transfer Enabled */ +#define AT91C_TWI_MSDIS ( 0x1 << 3 ) /* (TWI) TWI Master Transfer Disabled */ +#define AT91C_TWI_SVEN ( 0x1 << 4 ) /* (TWI) TWI Slave Transfer Enabled */ +#define AT91C_TWI_SVDIS ( 0x1 << 5 ) /* (TWI) TWI Slave Transfer Disabled */ +#define AT91C_TWI_SWRST ( 0x1 << 7 ) /* (TWI) Software Reset */ +/* -------- TWI_MMR : (TWI Offset: 0x4) TWI Master Mode Register -------- */ +#define AT91C_TWI_IADRSZ ( 0x3 << 8 ) /* (TWI) Internal Device Address Size */ +#define AT91C_TWI_IADRSZ_NO ( 0x0 << 8 ) /* (TWI) No internal device address */ +#define AT91C_TWI_IADRSZ_1_BYTE ( 0x1 << 8 ) /* (TWI) One-byte internal device address */ +#define AT91C_TWI_IADRSZ_2_BYTE ( 0x2 << 8 ) /* (TWI) Two-byte internal device address */ +#define AT91C_TWI_IADRSZ_3_BYTE ( 0x3 << 8 ) /* (TWI) Three-byte internal device address */ +#define AT91C_TWI_MREAD ( 0x1 << 12 ) /* (TWI) Master Read Direction */ +#define AT91C_TWI_DADR ( 0x7F << 16 ) /* (TWI) Device Address */ +/* -------- TWI_SMR : (TWI Offset: 0x8) TWI Slave Mode Register -------- */ +#define AT91C_TWI_SADR ( 0x7F << 16 ) /* (TWI) Slave Device Address */ +/* -------- TWI_CWGR : (TWI Offset: 0x10) TWI Clock Waveform Generator Register -------- */ +#define AT91C_TWI_CLDIV ( 0xFF << 0 ) /* (TWI) Clock Low Divider */ +#define AT91C_TWI_CHDIV ( 0xFF << 8 ) /* (TWI) Clock High Divider */ +#define AT91C_TWI_CKDIV ( 0x7 << 16 ) /* (TWI) Clock Divider */ +/* -------- TWI_SR : (TWI Offset: 0x20) TWI Status Register -------- */ +#define AT91C_TWI_TXCOMP ( 0x1 << 0 ) /* (TWI) Transmission Completed */ +#define AT91C_TWI_RXRDY ( 0x1 << 1 ) /* (TWI) Receive holding register ReaDY */ +#define AT91C_TWI_TXRDY ( 0x1 << 2 ) /* (TWI) Transmit holding register ReaDY */ +#define AT91C_TWI_SVREAD ( 0x1 << 3 ) /* (TWI) Slave Read */ +#define AT91C_TWI_SVACC ( 0x1 << 4 ) /* (TWI) Slave Access */ +#define AT91C_TWI_GCACC ( 0x1 << 5 ) /* (TWI) General Call Access */ +#define AT91C_TWI_OVRE ( 0x1 << 6 ) /* (TWI) Overrun Error */ +#define AT91C_TWI_UNRE ( 0x1 << 7 ) /* (TWI) Underrun Error */ +#define AT91C_TWI_NACK ( 0x1 << 8 ) /* (TWI) Not Acknowledged */ +#define AT91C_TWI_ARBLST ( 0x1 << 9 ) /* (TWI) Arbitration Lost */ +/* -------- TWI_IER : (TWI Offset: 0x24) TWI Interrupt Enable Register -------- */ +/* -------- TWI_IDR : (TWI Offset: 0x28) TWI Interrupt Disable Register -------- */ +/* -------- TWI_IMR : (TWI Offset: 0x2c) TWI Interrupt Mask Register -------- */ -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Timer Counter Channel Interface -// ***************************************************************************** -// *** Register offset in AT91S_TC structure *** -#define TC_CCR ( 0) // Channel Control Register -#define TC_CMR ( 4) // Channel Mode Register (Capture Mode / Waveform Mode) -#define TC_CV (16) // Counter Value -#define TC_RA (20) // Register A -#define TC_RB (24) // Register B -#define TC_RC (28) // Register C -#define TC_SR (32) // Status Register -#define TC_IER (36) // Interrupt Enable Register -#define TC_IDR (40) // Interrupt Disable Register -#define TC_IMR (44) // Interrupt Mask Register -// -------- TC_CCR : (TC Offset: 0x0) TC Channel Control Register -------- -#define AT91C_TC_CLKEN (0x1 << 0) // (TC) Counter Clock Enable Command -#define AT91C_TC_CLKDIS (0x1 << 1) // (TC) Counter Clock Disable Command -#define AT91C_TC_SWTRG (0x1 << 2) // (TC) Software Trigger Command -// -------- TC_CMR : (TC Offset: 0x4) TC Channel Mode Register: Capture Mode / Waveform Mode -------- -#define AT91C_TC_CLKS (0x7 << 0) // (TC) Clock Selection -#define AT91C_TC_CLKS_TIMER_DIV1_CLOCK (0x0) // (TC) Clock selected: TIMER_DIV1_CLOCK -#define AT91C_TC_CLKS_TIMER_DIV2_CLOCK (0x1) // (TC) Clock selected: TIMER_DIV2_CLOCK -#define AT91C_TC_CLKS_TIMER_DIV3_CLOCK (0x2) // (TC) Clock selected: TIMER_DIV3_CLOCK -#define AT91C_TC_CLKS_TIMER_DIV4_CLOCK (0x3) // (TC) Clock selected: TIMER_DIV4_CLOCK -#define AT91C_TC_CLKS_TIMER_DIV5_CLOCK (0x4) // (TC) Clock selected: TIMER_DIV5_CLOCK -#define AT91C_TC_CLKS_XC0 (0x5) // (TC) Clock selected: XC0 -#define AT91C_TC_CLKS_XC1 (0x6) // (TC) Clock selected: XC1 -#define AT91C_TC_CLKS_XC2 (0x7) // (TC) Clock selected: XC2 -#define AT91C_TC_CLKI (0x1 << 3) // (TC) Clock Invert -#define AT91C_TC_BURST (0x3 << 4) // (TC) Burst Signal Selection -#define AT91C_TC_BURST_NONE (0x0 << 4) // (TC) The clock is not gated by an external signal -#define AT91C_TC_BURST_XC0 (0x1 << 4) // (TC) XC0 is ANDed with the selected clock -#define AT91C_TC_BURST_XC1 (0x2 << 4) // (TC) XC1 is ANDed with the selected clock -#define AT91C_TC_BURST_XC2 (0x3 << 4) // (TC) XC2 is ANDed with the selected clock -#define AT91C_TC_CPCSTOP (0x1 << 6) // (TC) Counter Clock Stopped with RC Compare -#define AT91C_TC_LDBSTOP (0x1 << 6) // (TC) Counter Clock Stopped with RB Loading -#define AT91C_TC_LDBDIS (0x1 << 7) // (TC) Counter Clock Disabled with RB Loading -#define AT91C_TC_CPCDIS (0x1 << 7) // (TC) Counter Clock Disable with RC Compare -#define AT91C_TC_ETRGEDG (0x3 << 8) // (TC) External Trigger Edge Selection -#define AT91C_TC_ETRGEDG_NONE (0x0 << 8) // (TC) Edge: None -#define AT91C_TC_ETRGEDG_RISING (0x1 << 8) // (TC) Edge: rising edge -#define AT91C_TC_ETRGEDG_FALLING (0x2 << 8) // (TC) Edge: falling edge -#define AT91C_TC_ETRGEDG_BOTH (0x3 << 8) // (TC) Edge: each edge -#define AT91C_TC_EEVTEDG (0x3 << 8) // (TC) External Event Edge Selection -#define AT91C_TC_EEVTEDG_NONE (0x0 << 8) // (TC) Edge: None -#define AT91C_TC_EEVTEDG_RISING (0x1 << 8) // (TC) Edge: rising edge -#define AT91C_TC_EEVTEDG_FALLING (0x2 << 8) // (TC) Edge: falling edge -#define AT91C_TC_EEVTEDG_BOTH (0x3 << 8) // (TC) Edge: each edge -#define AT91C_TC_ABETRG (0x1 << 10) // (TC) TIOA or TIOB External Trigger Selection -#define AT91C_TC_EEVT (0x3 << 10) // (TC) External Event Selection -#define AT91C_TC_EEVT_NONE (0x0 << 10) // (TC) Signal selected as external event: TIOB TIOB direction: input -#define AT91C_TC_EEVT_RISING (0x1 << 10) // (TC) Signal selected as external event: XC0 TIOB direction: output -#define AT91C_TC_EEVT_FALLING (0x2 << 10) // (TC) Signal selected as external event: XC1 TIOB direction: output -#define AT91C_TC_EEVT_BOTH (0x3 << 10) // (TC) Signal selected as external event: XC2 TIOB direction: output -#define AT91C_TC_ENETRG (0x1 << 12) // (TC) External Event Trigger enable -#define AT91C_TC_WAVESEL (0x3 << 13) // (TC) Waveform Selection -#define AT91C_TC_WAVESEL_UP (0x0 << 13) // (TC) UP mode without atomatic trigger on RC Compare -#define AT91C_TC_WAVESEL_UPDOWN (0x1 << 13) // (TC) UPDOWN mode without automatic trigger on RC Compare -#define AT91C_TC_WAVESEL_UP_AUTO (0x2 << 13) // (TC) UP mode with automatic trigger on RC Compare -#define AT91C_TC_WAVESEL_UPDOWN_AUTO (0x3 << 13) // (TC) UPDOWN mode with automatic trigger on RC Compare -#define AT91C_TC_CPCTRG (0x1 << 14) // (TC) RC Compare Trigger Enable -#define AT91C_TC_WAVE (0x1 << 15) // (TC) -#define AT91C_TC_LDRA (0x3 << 16) // (TC) RA Loading Selection -#define AT91C_TC_LDRA_NONE (0x0 << 16) // (TC) Edge: None -#define AT91C_TC_LDRA_RISING (0x1 << 16) // (TC) Edge: rising edge of TIOA -#define AT91C_TC_LDRA_FALLING (0x2 << 16) // (TC) Edge: falling edge of TIOA -#define AT91C_TC_LDRA_BOTH (0x3 << 16) // (TC) Edge: each edge of TIOA -#define AT91C_TC_ACPA (0x3 << 16) // (TC) RA Compare Effect on TIOA -#define AT91C_TC_ACPA_NONE (0x0 << 16) // (TC) Effect: none -#define AT91C_TC_ACPA_SET (0x1 << 16) // (TC) Effect: set -#define AT91C_TC_ACPA_CLEAR (0x2 << 16) // (TC) Effect: clear -#define AT91C_TC_ACPA_TOGGLE (0x3 << 16) // (TC) Effect: toggle -#define AT91C_TC_LDRB (0x3 << 18) // (TC) RB Loading Selection -#define AT91C_TC_LDRB_NONE (0x0 << 18) // (TC) Edge: None -#define AT91C_TC_LDRB_RISING (0x1 << 18) // (TC) Edge: rising edge of TIOA -#define AT91C_TC_LDRB_FALLING (0x2 << 18) // (TC) Edge: falling edge of TIOA -#define AT91C_TC_LDRB_BOTH (0x3 << 18) // (TC) Edge: each edge of TIOA -#define AT91C_TC_ACPC (0x3 << 18) // (TC) RC Compare Effect on TIOA -#define AT91C_TC_ACPC_NONE (0x0 << 18) // (TC) Effect: none -#define AT91C_TC_ACPC_SET (0x1 << 18) // (TC) Effect: set -#define AT91C_TC_ACPC_CLEAR (0x2 << 18) // (TC) Effect: clear -#define AT91C_TC_ACPC_TOGGLE (0x3 << 18) // (TC) Effect: toggle -#define AT91C_TC_AEEVT (0x3 << 20) // (TC) External Event Effect on TIOA -#define AT91C_TC_AEEVT_NONE (0x0 << 20) // (TC) Effect: none -#define AT91C_TC_AEEVT_SET (0x1 << 20) // (TC) Effect: set -#define AT91C_TC_AEEVT_CLEAR (0x2 << 20) // (TC) Effect: clear -#define AT91C_TC_AEEVT_TOGGLE (0x3 << 20) // (TC) Effect: toggle -#define AT91C_TC_ASWTRG (0x3 << 22) // (TC) Software Trigger Effect on TIOA -#define AT91C_TC_ASWTRG_NONE (0x0 << 22) // (TC) Effect: none -#define AT91C_TC_ASWTRG_SET (0x1 << 22) // (TC) Effect: set -#define AT91C_TC_ASWTRG_CLEAR (0x2 << 22) // (TC) Effect: clear -#define AT91C_TC_ASWTRG_TOGGLE (0x3 << 22) // (TC) Effect: toggle -#define AT91C_TC_BCPB (0x3 << 24) // (TC) RB Compare Effect on TIOB -#define AT91C_TC_BCPB_NONE (0x0 << 24) // (TC) Effect: none -#define AT91C_TC_BCPB_SET (0x1 << 24) // (TC) Effect: set -#define AT91C_TC_BCPB_CLEAR (0x2 << 24) // (TC) Effect: clear -#define AT91C_TC_BCPB_TOGGLE (0x3 << 24) // (TC) Effect: toggle -#define AT91C_TC_BCPC (0x3 << 26) // (TC) RC Compare Effect on TIOB -#define AT91C_TC_BCPC_NONE (0x0 << 26) // (TC) Effect: none -#define AT91C_TC_BCPC_SET (0x1 << 26) // (TC) Effect: set -#define AT91C_TC_BCPC_CLEAR (0x2 << 26) // (TC) Effect: clear -#define AT91C_TC_BCPC_TOGGLE (0x3 << 26) // (TC) Effect: toggle -#define AT91C_TC_BEEVT (0x3 << 28) // (TC) External Event Effect on TIOB -#define AT91C_TC_BEEVT_NONE (0x0 << 28) // (TC) Effect: none -#define AT91C_TC_BEEVT_SET (0x1 << 28) // (TC) Effect: set -#define AT91C_TC_BEEVT_CLEAR (0x2 << 28) // (TC) Effect: clear -#define AT91C_TC_BEEVT_TOGGLE (0x3 << 28) // (TC) Effect: toggle -#define AT91C_TC_BSWTRG (0x3 << 30) // (TC) Software Trigger Effect on TIOB -#define AT91C_TC_BSWTRG_NONE (0x0 << 30) // (TC) Effect: none -#define AT91C_TC_BSWTRG_SET (0x1 << 30) // (TC) Effect: set -#define AT91C_TC_BSWTRG_CLEAR (0x2 << 30) // (TC) Effect: clear -#define AT91C_TC_BSWTRG_TOGGLE (0x3 << 30) // (TC) Effect: toggle -// -------- TC_SR : (TC Offset: 0x20) TC Channel Status Register -------- -#define AT91C_TC_COVFS (0x1 << 0) // (TC) Counter Overflow -#define AT91C_TC_LOVRS (0x1 << 1) // (TC) Load Overrun -#define AT91C_TC_CPAS (0x1 << 2) // (TC) RA Compare -#define AT91C_TC_CPBS (0x1 << 3) // (TC) RB Compare -#define AT91C_TC_CPCS (0x1 << 4) // (TC) RC Compare -#define AT91C_TC_LDRAS (0x1 << 5) // (TC) RA Loading -#define AT91C_TC_LDRBS (0x1 << 6) // (TC) RB Loading -#define AT91C_TC_ETRCS (0x1 << 7) // (TC) External Trigger -#define AT91C_TC_ETRGS (0x1 << 16) // (TC) Clock Enabling -#define AT91C_TC_MTIOA (0x1 << 17) // (TC) TIOA Mirror -#define AT91C_TC_MTIOB (0x1 << 18) // (TC) TIOA Mirror -// -------- TC_IER : (TC Offset: 0x24) TC Channel Interrupt Enable Register -------- -// -------- TC_IDR : (TC Offset: 0x28) TC Channel Interrupt Disable Register -------- -// -------- TC_IMR : (TC Offset: 0x2c) TC Channel Interrupt Mask Register -------- +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR Timer Counter Channel Interface */ +/* ***************************************************************************** */ +/* *** Register offset in AT91S_TC structure *** */ +#define TC_CCR ( 0 ) /* Channel Control Register */ +#define TC_CMR ( 4 ) /* Channel Mode Register (Capture Mode / Waveform Mode) */ +#define TC_CV ( 16 ) /* Counter Value */ +#define TC_RA ( 20 ) /* Register A */ +#define TC_RB ( 24 ) /* Register B */ +#define TC_RC ( 28 ) /* Register C */ +#define TC_SR ( 32 ) /* Status Register */ +#define TC_IER ( 36 ) /* Interrupt Enable Register */ +#define TC_IDR ( 40 ) /* Interrupt Disable Register */ +#define TC_IMR ( 44 ) /* Interrupt Mask Register */ +/* -------- TC_CCR : (TC Offset: 0x0) TC Channel Control Register -------- */ +#define AT91C_TC_CLKEN ( 0x1 << 0 ) /* (TC) Counter Clock Enable Command */ +#define AT91C_TC_CLKDIS ( 0x1 << 1 ) /* (TC) Counter Clock Disable Command */ +#define AT91C_TC_SWTRG ( 0x1 << 2 ) /* (TC) Software Trigger Command */ +/* -------- TC_CMR : (TC Offset: 0x4) TC Channel Mode Register: Capture Mode / Waveform Mode -------- */ +#define AT91C_TC_CLKS ( 0x7 << 0 ) /* (TC) Clock Selection */ +#define AT91C_TC_CLKS_TIMER_DIV1_CLOCK ( 0x0 ) /* (TC) Clock selected: TIMER_DIV1_CLOCK */ +#define AT91C_TC_CLKS_TIMER_DIV2_CLOCK ( 0x1 ) /* (TC) Clock selected: TIMER_DIV2_CLOCK */ +#define AT91C_TC_CLKS_TIMER_DIV3_CLOCK ( 0x2 ) /* (TC) Clock selected: TIMER_DIV3_CLOCK */ +#define AT91C_TC_CLKS_TIMER_DIV4_CLOCK ( 0x3 ) /* (TC) Clock selected: TIMER_DIV4_CLOCK */ +#define AT91C_TC_CLKS_TIMER_DIV5_CLOCK ( 0x4 ) /* (TC) Clock selected: TIMER_DIV5_CLOCK */ +#define AT91C_TC_CLKS_XC0 ( 0x5 ) /* (TC) Clock selected: XC0 */ +#define AT91C_TC_CLKS_XC1 ( 0x6 ) /* (TC) Clock selected: XC1 */ +#define AT91C_TC_CLKS_XC2 ( 0x7 ) /* (TC) Clock selected: XC2 */ +#define AT91C_TC_CLKI ( 0x1 << 3 ) /* (TC) Clock Invert */ +#define AT91C_TC_BURST ( 0x3 << 4 ) /* (TC) Burst Signal Selection */ +#define AT91C_TC_BURST_NONE ( 0x0 << 4 ) /* (TC) The clock is not gated by an external signal */ +#define AT91C_TC_BURST_XC0 ( 0x1 << 4 ) /* (TC) XC0 is ANDed with the selected clock */ +#define AT91C_TC_BURST_XC1 ( 0x2 << 4 ) /* (TC) XC1 is ANDed with the selected clock */ +#define AT91C_TC_BURST_XC2 ( 0x3 << 4 ) /* (TC) XC2 is ANDed with the selected clock */ +#define AT91C_TC_CPCSTOP ( 0x1 << 6 ) /* (TC) Counter Clock Stopped with RC Compare */ +#define AT91C_TC_LDBSTOP ( 0x1 << 6 ) /* (TC) Counter Clock Stopped with RB Loading */ +#define AT91C_TC_LDBDIS ( 0x1 << 7 ) /* (TC) Counter Clock Disabled with RB Loading */ +#define AT91C_TC_CPCDIS ( 0x1 << 7 ) /* (TC) Counter Clock Disable with RC Compare */ +#define AT91C_TC_ETRGEDG ( 0x3 << 8 ) /* (TC) External Trigger Edge Selection */ +#define AT91C_TC_ETRGEDG_NONE ( 0x0 << 8 ) /* (TC) Edge: None */ +#define AT91C_TC_ETRGEDG_RISING ( 0x1 << 8 ) /* (TC) Edge: rising edge */ +#define AT91C_TC_ETRGEDG_FALLING ( 0x2 << 8 ) /* (TC) Edge: falling edge */ +#define AT91C_TC_ETRGEDG_BOTH ( 0x3 << 8 ) /* (TC) Edge: each edge */ +#define AT91C_TC_EEVTEDG ( 0x3 << 8 ) /* (TC) External Event Edge Selection */ +#define AT91C_TC_EEVTEDG_NONE ( 0x0 << 8 ) /* (TC) Edge: None */ +#define AT91C_TC_EEVTEDG_RISING ( 0x1 << 8 ) /* (TC) Edge: rising edge */ +#define AT91C_TC_EEVTEDG_FALLING ( 0x2 << 8 ) /* (TC) Edge: falling edge */ +#define AT91C_TC_EEVTEDG_BOTH ( 0x3 << 8 ) /* (TC) Edge: each edge */ +#define AT91C_TC_ABETRG ( 0x1 << 10 ) /* (TC) TIOA or TIOB External Trigger Selection */ +#define AT91C_TC_EEVT ( 0x3 << 10 ) /* (TC) External Event Selection */ +#define AT91C_TC_EEVT_NONE ( 0x0 << 10 ) /* (TC) Signal selected as external event: TIOB TIOB direction: input */ +#define AT91C_TC_EEVT_RISING ( 0x1 << 10 ) /* (TC) Signal selected as external event: XC0 TIOB direction: output */ +#define AT91C_TC_EEVT_FALLING ( 0x2 << 10 ) /* (TC) Signal selected as external event: XC1 TIOB direction: output */ +#define AT91C_TC_EEVT_BOTH ( 0x3 << 10 ) /* (TC) Signal selected as external event: XC2 TIOB direction: output */ +#define AT91C_TC_ENETRG ( 0x1 << 12 ) /* (TC) External Event Trigger enable */ +#define AT91C_TC_WAVESEL ( 0x3 << 13 ) /* (TC) Waveform Selection */ +#define AT91C_TC_WAVESEL_UP ( 0x0 << 13 ) /* (TC) UP mode without atomatic trigger on RC Compare */ +#define AT91C_TC_WAVESEL_UPDOWN ( 0x1 << 13 ) /* (TC) UPDOWN mode without automatic trigger on RC Compare */ +#define AT91C_TC_WAVESEL_UP_AUTO ( 0x2 << 13 ) /* (TC) UP mode with automatic trigger on RC Compare */ +#define AT91C_TC_WAVESEL_UPDOWN_AUTO ( 0x3 << 13 ) /* (TC) UPDOWN mode with automatic trigger on RC Compare */ +#define AT91C_TC_CPCTRG ( 0x1 << 14 ) /* (TC) RC Compare Trigger Enable */ +#define AT91C_TC_WAVE ( 0x1 << 15 ) /* (TC) */ +#define AT91C_TC_LDRA ( 0x3 << 16 ) /* (TC) RA Loading Selection */ +#define AT91C_TC_LDRA_NONE ( 0x0 << 16 ) /* (TC) Edge: None */ +#define AT91C_TC_LDRA_RISING ( 0x1 << 16 ) /* (TC) Edge: rising edge of TIOA */ +#define AT91C_TC_LDRA_FALLING ( 0x2 << 16 ) /* (TC) Edge: falling edge of TIOA */ +#define AT91C_TC_LDRA_BOTH ( 0x3 << 16 ) /* (TC) Edge: each edge of TIOA */ +#define AT91C_TC_ACPA ( 0x3 << 16 ) /* (TC) RA Compare Effect on TIOA */ +#define AT91C_TC_ACPA_NONE ( 0x0 << 16 ) /* (TC) Effect: none */ +#define AT91C_TC_ACPA_SET ( 0x1 << 16 ) /* (TC) Effect: set */ +#define AT91C_TC_ACPA_CLEAR ( 0x2 << 16 ) /* (TC) Effect: clear */ +#define AT91C_TC_ACPA_TOGGLE ( 0x3 << 16 ) /* (TC) Effect: toggle */ +#define AT91C_TC_LDRB ( 0x3 << 18 ) /* (TC) RB Loading Selection */ +#define AT91C_TC_LDRB_NONE ( 0x0 << 18 ) /* (TC) Edge: None */ +#define AT91C_TC_LDRB_RISING ( 0x1 << 18 ) /* (TC) Edge: rising edge of TIOA */ +#define AT91C_TC_LDRB_FALLING ( 0x2 << 18 ) /* (TC) Edge: falling edge of TIOA */ +#define AT91C_TC_LDRB_BOTH ( 0x3 << 18 ) /* (TC) Edge: each edge of TIOA */ +#define AT91C_TC_ACPC ( 0x3 << 18 ) /* (TC) RC Compare Effect on TIOA */ +#define AT91C_TC_ACPC_NONE ( 0x0 << 18 ) /* (TC) Effect: none */ +#define AT91C_TC_ACPC_SET ( 0x1 << 18 ) /* (TC) Effect: set */ +#define AT91C_TC_ACPC_CLEAR ( 0x2 << 18 ) /* (TC) Effect: clear */ +#define AT91C_TC_ACPC_TOGGLE ( 0x3 << 18 ) /* (TC) Effect: toggle */ +#define AT91C_TC_AEEVT ( 0x3 << 20 ) /* (TC) External Event Effect on TIOA */ +#define AT91C_TC_AEEVT_NONE ( 0x0 << 20 ) /* (TC) Effect: none */ +#define AT91C_TC_AEEVT_SET ( 0x1 << 20 ) /* (TC) Effect: set */ +#define AT91C_TC_AEEVT_CLEAR ( 0x2 << 20 ) /* (TC) Effect: clear */ +#define AT91C_TC_AEEVT_TOGGLE ( 0x3 << 20 ) /* (TC) Effect: toggle */ +#define AT91C_TC_ASWTRG ( 0x3 << 22 ) /* (TC) Software Trigger Effect on TIOA */ +#define AT91C_TC_ASWTRG_NONE ( 0x0 << 22 ) /* (TC) Effect: none */ +#define AT91C_TC_ASWTRG_SET ( 0x1 << 22 ) /* (TC) Effect: set */ +#define AT91C_TC_ASWTRG_CLEAR ( 0x2 << 22 ) /* (TC) Effect: clear */ +#define AT91C_TC_ASWTRG_TOGGLE ( 0x3 << 22 ) /* (TC) Effect: toggle */ +#define AT91C_TC_BCPB ( 0x3 << 24 ) /* (TC) RB Compare Effect on TIOB */ +#define AT91C_TC_BCPB_NONE ( 0x0 << 24 ) /* (TC) Effect: none */ +#define AT91C_TC_BCPB_SET ( 0x1 << 24 ) /* (TC) Effect: set */ +#define AT91C_TC_BCPB_CLEAR ( 0x2 << 24 ) /* (TC) Effect: clear */ +#define AT91C_TC_BCPB_TOGGLE ( 0x3 << 24 ) /* (TC) Effect: toggle */ +#define AT91C_TC_BCPC ( 0x3 << 26 ) /* (TC) RC Compare Effect on TIOB */ +#define AT91C_TC_BCPC_NONE ( 0x0 << 26 ) /* (TC) Effect: none */ +#define AT91C_TC_BCPC_SET ( 0x1 << 26 ) /* (TC) Effect: set */ +#define AT91C_TC_BCPC_CLEAR ( 0x2 << 26 ) /* (TC) Effect: clear */ +#define AT91C_TC_BCPC_TOGGLE ( 0x3 << 26 ) /* (TC) Effect: toggle */ +#define AT91C_TC_BEEVT ( 0x3 << 28 ) /* (TC) External Event Effect on TIOB */ +#define AT91C_TC_BEEVT_NONE ( 0x0 << 28 ) /* (TC) Effect: none */ +#define AT91C_TC_BEEVT_SET ( 0x1 << 28 ) /* (TC) Effect: set */ +#define AT91C_TC_BEEVT_CLEAR ( 0x2 << 28 ) /* (TC) Effect: clear */ +#define AT91C_TC_BEEVT_TOGGLE ( 0x3 << 28 ) /* (TC) Effect: toggle */ +#define AT91C_TC_BSWTRG ( 0x3 << 30 ) /* (TC) Software Trigger Effect on TIOB */ +#define AT91C_TC_BSWTRG_NONE ( 0x0 << 30 ) /* (TC) Effect: none */ +#define AT91C_TC_BSWTRG_SET ( 0x1 << 30 ) /* (TC) Effect: set */ +#define AT91C_TC_BSWTRG_CLEAR ( 0x2 << 30 ) /* (TC) Effect: clear */ +#define AT91C_TC_BSWTRG_TOGGLE ( 0x3 << 30 ) /* (TC) Effect: toggle */ +/* -------- TC_SR : (TC Offset: 0x20) TC Channel Status Register -------- */ +#define AT91C_TC_COVFS ( 0x1 << 0 ) /* (TC) Counter Overflow */ +#define AT91C_TC_LOVRS ( 0x1 << 1 ) /* (TC) Load Overrun */ +#define AT91C_TC_CPAS ( 0x1 << 2 ) /* (TC) RA Compare */ +#define AT91C_TC_CPBS ( 0x1 << 3 ) /* (TC) RB Compare */ +#define AT91C_TC_CPCS ( 0x1 << 4 ) /* (TC) RC Compare */ +#define AT91C_TC_LDRAS ( 0x1 << 5 ) /* (TC) RA Loading */ +#define AT91C_TC_LDRBS ( 0x1 << 6 ) /* (TC) RB Loading */ +#define AT91C_TC_ETRCS ( 0x1 << 7 ) /* (TC) External Trigger */ +#define AT91C_TC_ETRGS ( 0x1 << 16 ) /* (TC) Clock Enabling */ +#define AT91C_TC_MTIOA ( 0x1 << 17 ) /* (TC) TIOA Mirror */ +#define AT91C_TC_MTIOB ( 0x1 << 18 ) /* (TC) TIOA Mirror */ +/* -------- TC_IER : (TC Offset: 0x24) TC Channel Interrupt Enable Register -------- */ +/* -------- TC_IDR : (TC Offset: 0x28) TC Channel Interrupt Disable Register -------- */ +/* -------- TC_IMR : (TC Offset: 0x2c) TC Channel Interrupt Mask Register -------- */ -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Timer Counter Interface -// ***************************************************************************** -// *** Register offset in AT91S_TCB structure *** -#define TCB_TC0 ( 0) // TC Channel 0 -#define TCB_TC1 (64) // TC Channel 1 -#define TCB_TC2 (128) // TC Channel 2 -#define TCB_BCR (192) // TC Block Control Register -#define TCB_BMR (196) // TC Block Mode Register -// -------- TCB_BCR : (TCB Offset: 0xc0) TC Block Control Register -------- -#define AT91C_TCB_SYNC (0x1 << 0) // (TCB) Synchro Command -// -------- TCB_BMR : (TCB Offset: 0xc4) TC Block Mode Register -------- -#define AT91C_TCB_TC0XC0S (0x1 << 0) // (TCB) External Clock Signal 0 Selection -#define AT91C_TCB_TC0XC0S_TCLK0 (0x0) // (TCB) TCLK0 connected to XC0 -#define AT91C_TCB_TC0XC0S_NONE (0x1) // (TCB) None signal connected to XC0 -#define AT91C_TCB_TC0XC0S_TIOA1 (0x2) // (TCB) TIOA1 connected to XC0 -#define AT91C_TCB_TC0XC0S_TIOA2 (0x3) // (TCB) TIOA2 connected to XC0 -#define AT91C_TCB_TC1XC1S (0x1 << 2) // (TCB) External Clock Signal 1 Selection -#define AT91C_TCB_TC1XC1S_TCLK1 (0x0 << 2) // (TCB) TCLK1 connected to XC1 -#define AT91C_TCB_TC1XC1S_NONE (0x1 << 2) // (TCB) None signal connected to XC1 -#define AT91C_TCB_TC1XC1S_TIOA0 (0x2 << 2) // (TCB) TIOA0 connected to XC1 -#define AT91C_TCB_TC1XC1S_TIOA2 (0x3 << 2) // (TCB) TIOA2 connected to XC1 -#define AT91C_TCB_TC2XC2S (0x1 << 4) // (TCB) External Clock Signal 2 Selection -#define AT91C_TCB_TC2XC2S_TCLK2 (0x0 << 4) // (TCB) TCLK2 connected to XC2 -#define AT91C_TCB_TC2XC2S_NONE (0x1 << 4) // (TCB) None signal connected to XC2 -#define AT91C_TCB_TC2XC2S_TIOA0 (0x2 << 4) // (TCB) TIOA0 connected to XC2 -#define AT91C_TCB_TC2XC2S_TIOA2 (0x3 << 4) // (TCB) TIOA2 connected to XC2 +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR Timer Counter Interface */ +/* ***************************************************************************** */ +/* *** Register offset in AT91S_TCB structure *** */ +#define TCB_TC0 ( 0 ) /* TC Channel 0 */ +#define TCB_TC1 ( 64 ) /* TC Channel 1 */ +#define TCB_TC2 ( 128 ) /* TC Channel 2 */ +#define TCB_BCR ( 192 ) /* TC Block Control Register */ +#define TCB_BMR ( 196 ) /* TC Block Mode Register */ +/* -------- TCB_BCR : (TCB Offset: 0xc0) TC Block Control Register -------- */ +#define AT91C_TCB_SYNC ( 0x1 << 0 ) /* (TCB) Synchro Command */ +/* -------- TCB_BMR : (TCB Offset: 0xc4) TC Block Mode Register -------- */ +#define AT91C_TCB_TC0XC0S ( 0x1 << 0 ) /* (TCB) External Clock Signal 0 Selection */ +#define AT91C_TCB_TC0XC0S_TCLK0 ( 0x0 ) /* (TCB) TCLK0 connected to XC0 */ +#define AT91C_TCB_TC0XC0S_NONE ( 0x1 ) /* (TCB) None signal connected to XC0 */ +#define AT91C_TCB_TC0XC0S_TIOA1 ( 0x2 ) /* (TCB) TIOA1 connected to XC0 */ +#define AT91C_TCB_TC0XC0S_TIOA2 ( 0x3 ) /* (TCB) TIOA2 connected to XC0 */ +#define AT91C_TCB_TC1XC1S ( 0x1 << 2 ) /* (TCB) External Clock Signal 1 Selection */ +#define AT91C_TCB_TC1XC1S_TCLK1 ( 0x0 << 2 ) /* (TCB) TCLK1 connected to XC1 */ +#define AT91C_TCB_TC1XC1S_NONE ( 0x1 << 2 ) /* (TCB) None signal connected to XC1 */ +#define AT91C_TCB_TC1XC1S_TIOA0 ( 0x2 << 2 ) /* (TCB) TIOA0 connected to XC1 */ +#define AT91C_TCB_TC1XC1S_TIOA2 ( 0x3 << 2 ) /* (TCB) TIOA2 connected to XC1 */ +#define AT91C_TCB_TC2XC2S ( 0x1 << 4 ) /* (TCB) External Clock Signal 2 Selection */ +#define AT91C_TCB_TC2XC2S_TCLK2 ( 0x0 << 4 ) /* (TCB) TCLK2 connected to XC2 */ +#define AT91C_TCB_TC2XC2S_NONE ( 0x1 << 4 ) /* (TCB) None signal connected to XC2 */ +#define AT91C_TCB_TC2XC2S_TIOA0 ( 0x2 << 4 ) /* (TCB) TIOA0 connected to XC2 */ +#define AT91C_TCB_TC2XC2S_TIOA2 ( 0x3 << 4 ) /* (TCB) TIOA2 connected to XC2 */ -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR PWMC Channel Interface -// ***************************************************************************** -// *** Register offset in AT91S_PWMC_CH structure *** -#define PWMC_CMR ( 0) // Channel Mode Register -#define PWMC_CDTYR ( 4) // Channel Duty Cycle Register -#define PWMC_CPRDR ( 8) // Channel Period Register -#define PWMC_CCNTR (12) // Channel Counter Register -#define PWMC_CUPDR (16) // Channel Update Register -#define PWMC_Reserved (20) // Reserved -// -------- PWMC_CMR : (PWMC_CH Offset: 0x0) PWMC Channel Mode Register -------- -#define AT91C_PWMC_CPRE (0xF << 0) // (PWMC_CH) Channel Pre-scaler : PWMC_CLKx -#define AT91C_PWMC_CPRE_MCK (0x0) // (PWMC_CH) -#define AT91C_PWMC_CPRE_MCKA (0xB) // (PWMC_CH) -#define AT91C_PWMC_CPRE_MCKB (0xC) // (PWMC_CH) -#define AT91C_PWMC_CALG (0x1 << 8) // (PWMC_CH) Channel Alignment -#define AT91C_PWMC_CPOL (0x1 << 9) // (PWMC_CH) Channel Polarity -#define AT91C_PWMC_CPD (0x1 << 10) // (PWMC_CH) Channel Update Period -// -------- PWMC_CDTYR : (PWMC_CH Offset: 0x4) PWMC Channel Duty Cycle Register -------- -#define AT91C_PWMC_CDTY (0x0 << 0) // (PWMC_CH) Channel Duty Cycle -// -------- PWMC_CPRDR : (PWMC_CH Offset: 0x8) PWMC Channel Period Register -------- -#define AT91C_PWMC_CPRD (0x0 << 0) // (PWMC_CH) Channel Period -// -------- PWMC_CCNTR : (PWMC_CH Offset: 0xc) PWMC Channel Counter Register -------- -#define AT91C_PWMC_CCNT (0x0 << 0) // (PWMC_CH) Channel Counter -// -------- PWMC_CUPDR : (PWMC_CH Offset: 0x10) PWMC Channel Update Register -------- -#define AT91C_PWMC_CUPD (0x0 << 0) // (PWMC_CH) Channel Update +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR PWMC Channel Interface */ +/* ***************************************************************************** */ +/* *** Register offset in AT91S_PWMC_CH structure *** */ +#define PWMC_CMR ( 0 ) /* Channel Mode Register */ +#define PWMC_CDTYR ( 4 ) /* Channel Duty Cycle Register */ +#define PWMC_CPRDR ( 8 ) /* Channel Period Register */ +#define PWMC_CCNTR ( 12 ) /* Channel Counter Register */ +#define PWMC_CUPDR ( 16 ) /* Channel Update Register */ +#define PWMC_Reserved ( 20 ) /* Reserved */ +/* -------- PWMC_CMR : (PWMC_CH Offset: 0x0) PWMC Channel Mode Register -------- */ +#define AT91C_PWMC_CPRE ( 0xF << 0 ) /* (PWMC_CH) Channel Pre-scaler : PWMC_CLKx */ +#define AT91C_PWMC_CPRE_MCK ( 0x0 ) /* (PWMC_CH) */ +#define AT91C_PWMC_CPRE_MCKA ( 0xB ) /* (PWMC_CH) */ +#define AT91C_PWMC_CPRE_MCKB ( 0xC ) /* (PWMC_CH) */ +#define AT91C_PWMC_CALG ( 0x1 << 8 ) /* (PWMC_CH) Channel Alignment */ +#define AT91C_PWMC_CPOL ( 0x1 << 9 ) /* (PWMC_CH) Channel Polarity */ +#define AT91C_PWMC_CPD ( 0x1 << 10 ) /* (PWMC_CH) Channel Update Period */ +/* -------- PWMC_CDTYR : (PWMC_CH Offset: 0x4) PWMC Channel Duty Cycle Register -------- */ +#define AT91C_PWMC_CDTY ( 0x0 << 0 ) /* (PWMC_CH) Channel Duty Cycle */ +/* -------- PWMC_CPRDR : (PWMC_CH Offset: 0x8) PWMC Channel Period Register -------- */ +#define AT91C_PWMC_CPRD ( 0x0 << 0 ) /* (PWMC_CH) Channel Period */ +/* -------- PWMC_CCNTR : (PWMC_CH Offset: 0xc) PWMC Channel Counter Register -------- */ +#define AT91C_PWMC_CCNT ( 0x0 << 0 ) /* (PWMC_CH) Channel Counter */ +/* -------- PWMC_CUPDR : (PWMC_CH Offset: 0x10) PWMC Channel Update Register -------- */ +#define AT91C_PWMC_CUPD ( 0x0 << 0 ) /* (PWMC_CH) Channel Update */ -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Pulse Width Modulation Controller Interface -// ***************************************************************************** -// *** Register offset in AT91S_PWMC structure *** -#define PWMC_MR ( 0) // PWMC Mode Register -#define PWMC_ENA ( 4) // PWMC Enable Register -#define PWMC_DIS ( 8) // PWMC Disable Register -#define PWMC_SR (12) // PWMC Status Register -#define PWMC_IER (16) // PWMC Interrupt Enable Register -#define PWMC_IDR (20) // PWMC Interrupt Disable Register -#define PWMC_IMR (24) // PWMC Interrupt Mask Register -#define PWMC_ISR (28) // PWMC Interrupt Status Register -#define PWMC_VR (252) // PWMC Version Register -#define PWMC_CH (512) // PWMC Channel 0 -// -------- PWMC_MR : (PWMC Offset: 0x0) PWMC Mode Register -------- -#define AT91C_PWMC_DIVA (0xFF << 0) // (PWMC) CLKA divide factor. -#define AT91C_PWMC_PREA (0xF << 8) // (PWMC) Divider Input Clock Prescaler A -#define AT91C_PWMC_PREA_MCK (0x0 << 8) // (PWMC) -#define AT91C_PWMC_DIVB (0xFF << 16) // (PWMC) CLKB divide factor. -#define AT91C_PWMC_PREB (0xF << 24) // (PWMC) Divider Input Clock Prescaler B -#define AT91C_PWMC_PREB_MCK (0x0 << 24) // (PWMC) -// -------- PWMC_ENA : (PWMC Offset: 0x4) PWMC Enable Register -------- -#define AT91C_PWMC_CHID0 (0x1 << 0) // (PWMC) Channel ID 0 -#define AT91C_PWMC_CHID1 (0x1 << 1) // (PWMC) Channel ID 1 -#define AT91C_PWMC_CHID2 (0x1 << 2) // (PWMC) Channel ID 2 -#define AT91C_PWMC_CHID3 (0x1 << 3) // (PWMC) Channel ID 3 -#define AT91C_PWMC_CHID4 (0x1 << 4) // (PWMC) Channel ID 4 -#define AT91C_PWMC_CHID5 (0x1 << 5) // (PWMC) Channel ID 5 -#define AT91C_PWMC_CHID6 (0x1 << 6) // (PWMC) Channel ID 6 -#define AT91C_PWMC_CHID7 (0x1 << 7) // (PWMC) Channel ID 7 -// -------- PWMC_DIS : (PWMC Offset: 0x8) PWMC Disable Register -------- -// -------- PWMC_SR : (PWMC Offset: 0xc) PWMC Status Register -------- -// -------- PWMC_IER : (PWMC Offset: 0x10) PWMC Interrupt Enable Register -------- -// -------- PWMC_IDR : (PWMC Offset: 0x14) PWMC Interrupt Disable Register -------- -// -------- PWMC_IMR : (PWMC Offset: 0x18) PWMC Interrupt Mask Register -------- -// -------- PWMC_ISR : (PWMC Offset: 0x1c) PWMC Interrupt Status Register -------- +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR Pulse Width Modulation Controller Interface */ +/* ***************************************************************************** */ +/* *** Register offset in AT91S_PWMC structure *** */ +#define PWMC_MR ( 0 ) /* PWMC Mode Register */ +#define PWMC_ENA ( 4 ) /* PWMC Enable Register */ +#define PWMC_DIS ( 8 ) /* PWMC Disable Register */ +#define PWMC_SR ( 12 ) /* PWMC Status Register */ +#define PWMC_IER ( 16 ) /* PWMC Interrupt Enable Register */ +#define PWMC_IDR ( 20 ) /* PWMC Interrupt Disable Register */ +#define PWMC_IMR ( 24 ) /* PWMC Interrupt Mask Register */ +#define PWMC_ISR ( 28 ) /* PWMC Interrupt Status Register */ +#define PWMC_VR ( 252 ) /* PWMC Version Register */ +#define PWMC_CH ( 512 ) /* PWMC Channel 0 */ +/* -------- PWMC_MR : (PWMC Offset: 0x0) PWMC Mode Register -------- */ +#define AT91C_PWMC_DIVA ( 0xFF << 0 ) /* (PWMC) CLKA divide factor. */ +#define AT91C_PWMC_PREA ( 0xF << 8 ) /* (PWMC) Divider Input Clock Prescaler A */ +#define AT91C_PWMC_PREA_MCK ( 0x0 << 8 ) /* (PWMC) */ +#define AT91C_PWMC_DIVB ( 0xFF << 16 ) /* (PWMC) CLKB divide factor. */ +#define AT91C_PWMC_PREB ( 0xF << 24 ) /* (PWMC) Divider Input Clock Prescaler B */ +#define AT91C_PWMC_PREB_MCK ( 0x0 << 24 ) /* (PWMC) */ +/* -------- PWMC_ENA : (PWMC Offset: 0x4) PWMC Enable Register -------- */ +#define AT91C_PWMC_CHID0 ( 0x1 << 0 ) /* (PWMC) Channel ID 0 */ +#define AT91C_PWMC_CHID1 ( 0x1 << 1 ) /* (PWMC) Channel ID 1 */ +#define AT91C_PWMC_CHID2 ( 0x1 << 2 ) /* (PWMC) Channel ID 2 */ +#define AT91C_PWMC_CHID3 ( 0x1 << 3 ) /* (PWMC) Channel ID 3 */ +#define AT91C_PWMC_CHID4 ( 0x1 << 4 ) /* (PWMC) Channel ID 4 */ +#define AT91C_PWMC_CHID5 ( 0x1 << 5 ) /* (PWMC) Channel ID 5 */ +#define AT91C_PWMC_CHID6 ( 0x1 << 6 ) /* (PWMC) Channel ID 6 */ +#define AT91C_PWMC_CHID7 ( 0x1 << 7 ) /* (PWMC) Channel ID 7 */ +/* -------- PWMC_DIS : (PWMC Offset: 0x8) PWMC Disable Register -------- */ +/* -------- PWMC_SR : (PWMC Offset: 0xc) PWMC Status Register -------- */ +/* -------- PWMC_IER : (PWMC Offset: 0x10) PWMC Interrupt Enable Register -------- */ +/* -------- PWMC_IDR : (PWMC Offset: 0x14) PWMC Interrupt Disable Register -------- */ +/* -------- PWMC_IMR : (PWMC Offset: 0x18) PWMC Interrupt Mask Register -------- */ +/* -------- PWMC_ISR : (PWMC Offset: 0x1c) PWMC Interrupt Status Register -------- */ -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR USB Device Interface -// ***************************************************************************** -// *** Register offset in AT91S_UDP structure *** -#define UDP_NUM ( 0) // Frame Number Register -#define UDP_GLBSTATE ( 4) // Global State Register -#define UDP_FADDR ( 8) // Function Address Register -#define UDP_IER (16) // Interrupt Enable Register -#define UDP_IDR (20) // Interrupt Disable Register -#define UDP_IMR (24) // Interrupt Mask Register -#define UDP_ISR (28) // Interrupt Status Register -#define UDP_ICR (32) // Interrupt Clear Register -#define UDP_RSTEP (40) // Reset Endpoint Register -#define UDP_CSR (48) // Endpoint Control and Status Register -#define UDP_FDR (80) // Endpoint FIFO Data Register -// -------- UDP_FRM_NUM : (UDP Offset: 0x0) USB Frame Number Register -------- -#define AT91C_UDP_FRM_NUM (0x7FF << 0) // (UDP) Frame Number as Defined in the Packet Field Formats -#define AT91C_UDP_FRM_ERR (0x1 << 16) // (UDP) Frame Error -#define AT91C_UDP_FRM_OK (0x1 << 17) // (UDP) Frame OK -// -------- UDP_GLB_STATE : (UDP Offset: 0x4) USB Global State Register -------- -#define AT91C_UDP_FADDEN (0x1 << 0) // (UDP) Function Address Enable -#define AT91C_UDP_CONFG (0x1 << 1) // (UDP) Configured -#define AT91C_UDP_RMWUPE (0x1 << 2) // (UDP) Remote Wake Up Enable -#define AT91C_UDP_RSMINPR (0x1 << 3) // (UDP) A Resume Has Been Sent to the Host -// -------- UDP_FADDR : (UDP Offset: 0x8) USB Function Address Register -------- -#define AT91C_UDP_FADD (0xFF << 0) // (UDP) Function Address Value -#define AT91C_UDP_FEN (0x1 << 8) // (UDP) Function Enable -// -------- UDP_IER : (UDP Offset: 0x10) USB Interrupt Enable Register -------- -#define AT91C_UDP_EPINT0 (0x1 << 0) // (UDP) Endpoint 0 Interrupt -#define AT91C_UDP_EPINT1 (0x1 << 1) // (UDP) Endpoint 0 Interrupt -#define AT91C_UDP_EPINT2 (0x1 << 2) // (UDP) Endpoint 2 Interrupt -#define AT91C_UDP_EPINT3 (0x1 << 3) // (UDP) Endpoint 3 Interrupt -#define AT91C_UDP_EPINT4 (0x1 << 4) // (UDP) Endpoint 4 Interrupt -#define AT91C_UDP_EPINT5 (0x1 << 5) // (UDP) Endpoint 5 Interrupt -#define AT91C_UDP_EPINT6 (0x1 << 6) // (UDP) Endpoint 6 Interrupt -#define AT91C_UDP_EPINT7 (0x1 << 7) // (UDP) Endpoint 7 Interrupt -#define AT91C_UDP_RXSUSP (0x1 << 8) // (UDP) USB Suspend Interrupt -#define AT91C_UDP_RXRSM (0x1 << 9) // (UDP) USB Resume Interrupt -#define AT91C_UDP_EXTRSM (0x1 << 10) // (UDP) USB External Resume Interrupt -#define AT91C_UDP_SOFINT (0x1 << 11) // (UDP) USB Start Of frame Interrupt -#define AT91C_UDP_WAKEUP (0x1 << 13) // (UDP) USB Resume Interrupt -// -------- UDP_IDR : (UDP Offset: 0x14) USB Interrupt Disable Register -------- -// -------- UDP_IMR : (UDP Offset: 0x18) USB Interrupt Mask Register -------- -// -------- UDP_ISR : (UDP Offset: 0x1c) USB Interrupt Status Register -------- -#define AT91C_UDP_ENDBUSRES (0x1 << 12) // (UDP) USB End Of Bus Reset Interrupt -// -------- UDP_ICR : (UDP Offset: 0x20) USB Interrupt Clear Register -------- -// -------- UDP_RST_EP : (UDP Offset: 0x28) USB Reset Endpoint Register -------- -#define AT91C_UDP_EP0 (0x1 << 0) // (UDP) Reset Endpoint 0 -#define AT91C_UDP_EP1 (0x1 << 1) // (UDP) Reset Endpoint 1 -#define AT91C_UDP_EP2 (0x1 << 2) // (UDP) Reset Endpoint 2 -#define AT91C_UDP_EP3 (0x1 << 3) // (UDP) Reset Endpoint 3 -#define AT91C_UDP_EP4 (0x1 << 4) // (UDP) Reset Endpoint 4 -#define AT91C_UDP_EP5 (0x1 << 5) // (UDP) Reset Endpoint 5 -#define AT91C_UDP_EP6 (0x1 << 6) // (UDP) Reset Endpoint 6 -#define AT91C_UDP_EP7 (0x1 << 7) // (UDP) Reset Endpoint 7 -// -------- UDP_CSR : (UDP Offset: 0x30) USB Endpoint Control and Status Register -------- -#define AT91C_UDP_TXCOMP (0x1 << 0) // (UDP) Generates an IN packet with data previously written in the DPR -#define AT91C_UDP_RX_DATA_BK0 (0x1 << 1) // (UDP) Receive Data Bank 0 -#define AT91C_UDP_RXSETUP (0x1 << 2) // (UDP) Sends STALL to the Host (Control endpoints) -#define AT91C_UDP_ISOERROR (0x1 << 3) // (UDP) Isochronous error (Isochronous endpoints) -#define AT91C_UDP_TXPKTRDY (0x1 << 4) // (UDP) Transmit Packet Ready -#define AT91C_UDP_FORCESTALL (0x1 << 5) // (UDP) Force Stall (used by Control, Bulk and Isochronous endpoints). -#define AT91C_UDP_RX_DATA_BK1 (0x1 << 6) // (UDP) Receive Data Bank 1 (only used by endpoints with ping-pong attributes). -#define AT91C_UDP_DIR (0x1 << 7) // (UDP) Transfer Direction -#define AT91C_UDP_EPTYPE (0x7 << 8) // (UDP) Endpoint type -#define AT91C_UDP_EPTYPE_CTRL (0x0 << 8) // (UDP) Control -#define AT91C_UDP_EPTYPE_ISO_OUT (0x1 << 8) // (UDP) Isochronous OUT -#define AT91C_UDP_EPTYPE_BULK_OUT (0x2 << 8) // (UDP) Bulk OUT -#define AT91C_UDP_EPTYPE_INT_OUT (0x3 << 8) // (UDP) Interrupt OUT -#define AT91C_UDP_EPTYPE_ISO_IN (0x5 << 8) // (UDP) Isochronous IN -#define AT91C_UDP_EPTYPE_BULK_IN (0x6 << 8) // (UDP) Bulk IN -#define AT91C_UDP_EPTYPE_INT_IN (0x7 << 8) // (UDP) Interrupt IN -#define AT91C_UDP_DTGLE (0x1 << 11) // (UDP) Data Toggle -#define AT91C_UDP_EPEDS (0x1 << 15) // (UDP) Endpoint Enable Disable -#define AT91C_UDP_RXBYTECNT (0x7FF << 16) // (UDP) Number Of Bytes Available in the FIFO +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR USB Device Interface */ +/* ***************************************************************************** */ +/* *** Register offset in AT91S_UDP structure *** */ +#define UDP_NUM ( 0 ) /* Frame Number Register */ +#define UDP_GLBSTATE ( 4 ) /* Global State Register */ +#define UDP_FADDR ( 8 ) /* Function Address Register */ +#define UDP_IER ( 16 ) /* Interrupt Enable Register */ +#define UDP_IDR ( 20 ) /* Interrupt Disable Register */ +#define UDP_IMR ( 24 ) /* Interrupt Mask Register */ +#define UDP_ISR ( 28 ) /* Interrupt Status Register */ +#define UDP_ICR ( 32 ) /* Interrupt Clear Register */ +#define UDP_RSTEP ( 40 ) /* Reset Endpoint Register */ +#define UDP_CSR ( 48 ) /* Endpoint Control and Status Register */ +#define UDP_FDR ( 80 ) /* Endpoint FIFO Data Register */ +/* -------- UDP_FRM_NUM : (UDP Offset: 0x0) USB Frame Number Register -------- */ +#define AT91C_UDP_FRM_NUM ( 0x7FF << 0 ) /* (UDP) Frame Number as Defined in the Packet Field Formats */ +#define AT91C_UDP_FRM_ERR ( 0x1 << 16 ) /* (UDP) Frame Error */ +#define AT91C_UDP_FRM_OK ( 0x1 << 17 ) /* (UDP) Frame OK */ +/* -------- UDP_GLB_STATE : (UDP Offset: 0x4) USB Global State Register -------- */ +#define AT91C_UDP_FADDEN ( 0x1 << 0 ) /* (UDP) Function Address Enable */ +#define AT91C_UDP_CONFG ( 0x1 << 1 ) /* (UDP) Configured */ +#define AT91C_UDP_RMWUPE ( 0x1 << 2 ) /* (UDP) Remote Wake Up Enable */ +#define AT91C_UDP_RSMINPR ( 0x1 << 3 ) /* (UDP) A Resume Has Been Sent to the Host */ +/* -------- UDP_FADDR : (UDP Offset: 0x8) USB Function Address Register -------- */ +#define AT91C_UDP_FADD ( 0xFF << 0 ) /* (UDP) Function Address Value */ +#define AT91C_UDP_FEN ( 0x1 << 8 ) /* (UDP) Function Enable */ +/* -------- UDP_IER : (UDP Offset: 0x10) USB Interrupt Enable Register -------- */ +#define AT91C_UDP_EPINT0 ( 0x1 << 0 ) /* (UDP) Endpoint 0 Interrupt */ +#define AT91C_UDP_EPINT1 ( 0x1 << 1 ) /* (UDP) Endpoint 0 Interrupt */ +#define AT91C_UDP_EPINT2 ( 0x1 << 2 ) /* (UDP) Endpoint 2 Interrupt */ +#define AT91C_UDP_EPINT3 ( 0x1 << 3 ) /* (UDP) Endpoint 3 Interrupt */ +#define AT91C_UDP_EPINT4 ( 0x1 << 4 ) /* (UDP) Endpoint 4 Interrupt */ +#define AT91C_UDP_EPINT5 ( 0x1 << 5 ) /* (UDP) Endpoint 5 Interrupt */ +#define AT91C_UDP_EPINT6 ( 0x1 << 6 ) /* (UDP) Endpoint 6 Interrupt */ +#define AT91C_UDP_EPINT7 ( 0x1 << 7 ) /* (UDP) Endpoint 7 Interrupt */ +#define AT91C_UDP_RXSUSP ( 0x1 << 8 ) /* (UDP) USB Suspend Interrupt */ +#define AT91C_UDP_RXRSM ( 0x1 << 9 ) /* (UDP) USB Resume Interrupt */ +#define AT91C_UDP_EXTRSM ( 0x1 << 10 ) /* (UDP) USB External Resume Interrupt */ +#define AT91C_UDP_SOFINT ( 0x1 << 11 ) /* (UDP) USB Start Of frame Interrupt */ +#define AT91C_UDP_WAKEUP ( 0x1 << 13 ) /* (UDP) USB Resume Interrupt */ +/* -------- UDP_IDR : (UDP Offset: 0x14) USB Interrupt Disable Register -------- */ +/* -------- UDP_IMR : (UDP Offset: 0x18) USB Interrupt Mask Register -------- */ +/* -------- UDP_ISR : (UDP Offset: 0x1c) USB Interrupt Status Register -------- */ +#define AT91C_UDP_ENDBUSRES ( 0x1 << 12 ) /* (UDP) USB End Of Bus Reset Interrupt */ +/* -------- UDP_ICR : (UDP Offset: 0x20) USB Interrupt Clear Register -------- */ +/* -------- UDP_RST_EP : (UDP Offset: 0x28) USB Reset Endpoint Register -------- */ +#define AT91C_UDP_EP0 ( 0x1 << 0 ) /* (UDP) Reset Endpoint 0 */ +#define AT91C_UDP_EP1 ( 0x1 << 1 ) /* (UDP) Reset Endpoint 1 */ +#define AT91C_UDP_EP2 ( 0x1 << 2 ) /* (UDP) Reset Endpoint 2 */ +#define AT91C_UDP_EP3 ( 0x1 << 3 ) /* (UDP) Reset Endpoint 3 */ +#define AT91C_UDP_EP4 ( 0x1 << 4 ) /* (UDP) Reset Endpoint 4 */ +#define AT91C_UDP_EP5 ( 0x1 << 5 ) /* (UDP) Reset Endpoint 5 */ +#define AT91C_UDP_EP6 ( 0x1 << 6 ) /* (UDP) Reset Endpoint 6 */ +#define AT91C_UDP_EP7 ( 0x1 << 7 ) /* (UDP) Reset Endpoint 7 */ +/* -------- UDP_CSR : (UDP Offset: 0x30) USB Endpoint Control and Status Register -------- */ +#define AT91C_UDP_TXCOMP ( 0x1 << 0 ) /* (UDP) Generates an IN packet with data previously written in the DPR */ +#define AT91C_UDP_RX_DATA_BK0 ( 0x1 << 1 ) /* (UDP) Receive Data Bank 0 */ +#define AT91C_UDP_RXSETUP ( 0x1 << 2 ) /* (UDP) Sends STALL to the Host (Control endpoints) */ +#define AT91C_UDP_ISOERROR ( 0x1 << 3 ) /* (UDP) Isochronous error (Isochronous endpoints) */ +#define AT91C_UDP_TXPKTRDY ( 0x1 << 4 ) /* (UDP) Transmit Packet Ready */ +#define AT91C_UDP_FORCESTALL ( 0x1 << 5 ) /* (UDP) Force Stall (used by Control, Bulk and Isochronous endpoints). */ +#define AT91C_UDP_RX_DATA_BK1 ( 0x1 << 6 ) /* (UDP) Receive Data Bank 1 (only used by endpoints with ping-pong attributes). */ +#define AT91C_UDP_DIR ( 0x1 << 7 ) /* (UDP) Transfer Direction */ +#define AT91C_UDP_EPTYPE ( 0x7 << 8 ) /* (UDP) Endpoint type */ +#define AT91C_UDP_EPTYPE_CTRL ( 0x0 << 8 ) /* (UDP) Control */ +#define AT91C_UDP_EPTYPE_ISO_OUT ( 0x1 << 8 ) /* (UDP) Isochronous OUT */ +#define AT91C_UDP_EPTYPE_BULK_OUT ( 0x2 << 8 ) /* (UDP) Bulk OUT */ +#define AT91C_UDP_EPTYPE_INT_OUT ( 0x3 << 8 ) /* (UDP) Interrupt OUT */ +#define AT91C_UDP_EPTYPE_ISO_IN ( 0x5 << 8 ) /* (UDP) Isochronous IN */ +#define AT91C_UDP_EPTYPE_BULK_IN ( 0x6 << 8 ) /* (UDP) Bulk IN */ +#define AT91C_UDP_EPTYPE_INT_IN ( 0x7 << 8 ) /* (UDP) Interrupt IN */ +#define AT91C_UDP_DTGLE ( 0x1 << 11 ) /* (UDP) Data Toggle */ +#define AT91C_UDP_EPEDS ( 0x1 << 15 ) /* (UDP) Endpoint Enable Disable */ +#define AT91C_UDP_RXBYTECNT ( 0x7FF << 16 ) /* (UDP) Number Of Bytes Available in the FIFO */ -// ***************************************************************************** -// REGISTER ADDRESS DEFINITION FOR AT91SAM7S64 -// ***************************************************************************** -// ========== Register definition for SYSC peripheral ========== -#define AT91C_SYSC_SYSC_VRPM (0xFFFFFD60) // (SYSC) Voltage Regulator Power Mode Register -// ========== Register definition for AIC peripheral ========== -#define AT91C_AIC_ICCR (0xFFFFF128) // (AIC) Interrupt Clear Command Register -#define AT91C_AIC_IECR (0xFFFFF120) // (AIC) Interrupt Enable Command Register -#define AT91C_AIC_SMR (0xFFFFF000) // (AIC) Source Mode Register -#define AT91C_AIC_ISCR (0xFFFFF12C) // (AIC) Interrupt Set Command Register -#define AT91C_AIC_EOICR (0xFFFFF130) // (AIC) End of Interrupt Command Register -#define AT91C_AIC_DCR (0xFFFFF138) // (AIC) Debug Control Register (Protect) -#define AT91C_AIC_FFER (0xFFFFF140) // (AIC) Fast Forcing Enable Register -#define AT91C_AIC_SVR (0xFFFFF080) // (AIC) Source Vector Register -#define AT91C_AIC_SPU (0xFFFFF134) // (AIC) Spurious Vector Register -#define AT91C_AIC_FFDR (0xFFFFF144) // (AIC) Fast Forcing Disable Register -#define AT91C_AIC_FVR (0xFFFFF104) // (AIC) FIQ Vector Register -#define AT91C_AIC_FFSR (0xFFFFF148) // (AIC) Fast Forcing Status Register -#define AT91C_AIC_IMR (0xFFFFF110) // (AIC) Interrupt Mask Register -#define AT91C_AIC_ISR (0xFFFFF108) // (AIC) Interrupt Status Register -#define AT91C_AIC_IVR (0xFFFFF100) // (AIC) IRQ Vector Register -#define AT91C_AIC_IDCR (0xFFFFF124) // (AIC) Interrupt Disable Command Register -#define AT91C_AIC_CISR (0xFFFFF114) // (AIC) Core Interrupt Status Register -#define AT91C_AIC_IPR (0xFFFFF10C) // (AIC) Interrupt Pending Register -// ========== Register definition for DBGU peripheral ========== -#define AT91C_DBGU_C2R (0xFFFFF244) // (DBGU) Chip ID2 Register -#define AT91C_DBGU_THR (0xFFFFF21C) // (DBGU) Transmitter Holding Register -#define AT91C_DBGU_CSR (0xFFFFF214) // (DBGU) Channel Status Register -#define AT91C_DBGU_IDR (0xFFFFF20C) // (DBGU) Interrupt Disable Register -#define AT91C_DBGU_MR (0xFFFFF204) // (DBGU) Mode Register -#define AT91C_DBGU_FNTR (0xFFFFF248) // (DBGU) Force NTRST Register -#define AT91C_DBGU_C1R (0xFFFFF240) // (DBGU) Chip ID1 Register -#define AT91C_DBGU_BRGR (0xFFFFF220) // (DBGU) Baud Rate Generator Register -#define AT91C_DBGU_RHR (0xFFFFF218) // (DBGU) Receiver Holding Register -#define AT91C_DBGU_IMR (0xFFFFF210) // (DBGU) Interrupt Mask Register -#define AT91C_DBGU_IER (0xFFFFF208) // (DBGU) Interrupt Enable Register -#define AT91C_DBGU_CR (0xFFFFF200) // (DBGU) Control Register -// ========== Register definition for PDC_DBGU peripheral ========== -#define AT91C_DBGU_TNCR (0xFFFFF31C) // (PDC_DBGU) Transmit Next Counter Register -#define AT91C_DBGU_RNCR (0xFFFFF314) // (PDC_DBGU) Receive Next Counter Register -#define AT91C_DBGU_PTCR (0xFFFFF320) // (PDC_DBGU) PDC Transfer Control Register -#define AT91C_DBGU_PTSR (0xFFFFF324) // (PDC_DBGU) PDC Transfer Status Register -#define AT91C_DBGU_RCR (0xFFFFF304) // (PDC_DBGU) Receive Counter Register -#define AT91C_DBGU_TCR (0xFFFFF30C) // (PDC_DBGU) Transmit Counter Register -#define AT91C_DBGU_RPR (0xFFFFF300) // (PDC_DBGU) Receive Pointer Register -#define AT91C_DBGU_TPR (0xFFFFF308) // (PDC_DBGU) Transmit Pointer Register -#define AT91C_DBGU_RNPR (0xFFFFF310) // (PDC_DBGU) Receive Next Pointer Register -#define AT91C_DBGU_TNPR (0xFFFFF318) // (PDC_DBGU) Transmit Next Pointer Register -// ========== Register definition for PIOA peripheral ========== -#define AT91C_PIOA_IMR (0xFFFFF448) // (PIOA) Interrupt Mask Register -#define AT91C_PIOA_IER (0xFFFFF440) // (PIOA) Interrupt Enable Register -#define AT91C_PIOA_OWDR (0xFFFFF4A4) // (PIOA) Output Write Disable Register -#define AT91C_PIOA_ISR (0xFFFFF44C) // (PIOA) Interrupt Status Register -#define AT91C_PIOA_PPUDR (0xFFFFF460) // (PIOA) Pull-up Disable Register -#define AT91C_PIOA_MDSR (0xFFFFF458) // (PIOA) Multi-driver Status Register -#define AT91C_PIOA_MDER (0xFFFFF450) // (PIOA) Multi-driver Enable Register -#define AT91C_PIOA_PER (0xFFFFF400) // (PIOA) PIO Enable Register -#define AT91C_PIOA_PSR (0xFFFFF408) // (PIOA) PIO Status Register -#define AT91C_PIOA_OER (0xFFFFF410) // (PIOA) Output Enable Register -#define AT91C_PIOA_BSR (0xFFFFF474) // (PIOA) Select B Register -#define AT91C_PIOA_PPUER (0xFFFFF464) // (PIOA) Pull-up Enable Register -#define AT91C_PIOA_MDDR (0xFFFFF454) // (PIOA) Multi-driver Disable Register -#define AT91C_PIOA_PDR (0xFFFFF404) // (PIOA) PIO Disable Register -#define AT91C_PIOA_ODR (0xFFFFF414) // (PIOA) Output Disable Registerr -#define AT91C_PIOA_IFDR (0xFFFFF424) // (PIOA) Input Filter Disable Register -#define AT91C_PIOA_ABSR (0xFFFFF478) // (PIOA) AB Select Status Register -#define AT91C_PIOA_ASR (0xFFFFF470) // (PIOA) Select A Register -#define AT91C_PIOA_PPUSR (0xFFFFF468) // (PIOA) Pad Pull-up Status Register -#define AT91C_PIOA_ODSR (0xFFFFF438) // (PIOA) Output Data Status Register -#define AT91C_PIOA_SODR (0xFFFFF430) // (PIOA) Set Output Data Register -#define AT91C_PIOA_IFSR (0xFFFFF428) // (PIOA) Input Filter Status Register -#define AT91C_PIOA_IFER (0xFFFFF420) // (PIOA) Input Filter Enable Register -#define AT91C_PIOA_OSR (0xFFFFF418) // (PIOA) Output Status Register -#define AT91C_PIOA_IDR (0xFFFFF444) // (PIOA) Interrupt Disable Register -#define AT91C_PIOA_PDSR (0xFFFFF43C) // (PIOA) Pin Data Status Register -#define AT91C_PIOA_CODR (0xFFFFF434) // (PIOA) Clear Output Data Register -#define AT91C_PIOA_OWSR (0xFFFFF4A8) // (PIOA) Output Write Status Register -#define AT91C_PIOA_OWER (0xFFFFF4A0) // (PIOA) Output Write Enable Register -// ========== Register definition for CKGR peripheral ========== -#define AT91C_CKGR_PLLR (0xFFFFFC2C) // (CKGR) PLL Register -#define AT91C_CKGR_MCFR (0xFFFFFC24) // (CKGR) Main Clock Frequency Register -#define AT91C_CKGR_MOR (0xFFFFFC20) // (CKGR) Main Oscillator Register -// ========== Register definition for PMC peripheral ========== -#define AT91C_PMC_SCSR (0xFFFFFC08) // (PMC) System Clock Status Register -#define AT91C_PMC_SCER (0xFFFFFC00) // (PMC) System Clock Enable Register -#define AT91C_PMC_IMR (0xFFFFFC6C) // (PMC) Interrupt Mask Register -#define AT91C_PMC_IDR (0xFFFFFC64) // (PMC) Interrupt Disable Register -#define AT91C_PMC_PCDR (0xFFFFFC14) // (PMC) Peripheral Clock Disable Register -#define AT91C_PMC_SCDR (0xFFFFFC04) // (PMC) System Clock Disable Register -#define AT91C_PMC_SR (0xFFFFFC68) // (PMC) Status Register -#define AT91C_PMC_IER (0xFFFFFC60) // (PMC) Interrupt Enable Register -#define AT91C_PMC_MCKR (0xFFFFFC30) // (PMC) Master Clock Register -#define AT91C_PMC_MOR (0xFFFFFC20) // (PMC) Main Oscillator Register -#define AT91C_PMC_PCER (0xFFFFFC10) // (PMC) Peripheral Clock Enable Register -#define AT91C_PMC_PCSR (0xFFFFFC18) // (PMC) Peripheral Clock Status Register -#define AT91C_PMC_PLLR (0xFFFFFC2C) // (PMC) PLL Register -#define AT91C_PMC_MCFR (0xFFFFFC24) // (PMC) Main Clock Frequency Register -#define AT91C_PMC_PCKR (0xFFFFFC40) // (PMC) Programmable Clock Register -// ========== Register definition for RSTC peripheral ========== -#define AT91C_RSTC_RSR (0xFFFFFD04) // (RSTC) Reset Status Register -#define AT91C_RSTC_RMR (0xFFFFFD08) // (RSTC) Reset Mode Register -#define AT91C_RSTC_RCR (0xFFFFFD00) // (RSTC) Reset Control Register -// ========== Register definition for RTTC peripheral ========== -#define AT91C_RTTC_RTSR (0xFFFFFD2C) // (RTTC) Real-time Status Register -#define AT91C_RTTC_RTAR (0xFFFFFD24) // (RTTC) Real-time Alarm Register -#define AT91C_RTTC_RTVR (0xFFFFFD28) // (RTTC) Real-time Value Register -#define AT91C_RTTC_RTMR (0xFFFFFD20) // (RTTC) Real-time Mode Register -// ========== Register definition for PITC peripheral ========== -#define AT91C_PITC_PIIR (0xFFFFFD3C) // (PITC) Period Interval Image Register -#define AT91C_PITC_PISR (0xFFFFFD34) // (PITC) Period Interval Status Register -#define AT91C_PITC_PIVR (0xFFFFFD38) // (PITC) Period Interval Value Register -#define AT91C_PITC_PIMR (0xFFFFFD30) // (PITC) Period Interval Mode Register -// ========== Register definition for WDTC peripheral ========== -#define AT91C_WDTC_WDMR (0xFFFFFD44) // (WDTC) Watchdog Mode Register -#define AT91C_WDTC_WDSR (0xFFFFFD48) // (WDTC) Watchdog Status Register -#define AT91C_WDTC_WDCR (0xFFFFFD40) // (WDTC) Watchdog Control Register -// ========== Register definition for MC peripheral ========== -#define AT91C_MC_FCR (0xFFFFFF64) // (MC) MC Flash Command Register -#define AT91C_MC_ASR (0xFFFFFF04) // (MC) MC Abort Status Register -#define AT91C_MC_FSR (0xFFFFFF68) // (MC) MC Flash Status Register -#define AT91C_MC_FMR (0xFFFFFF60) // (MC) MC Flash Mode Register -#define AT91C_MC_AASR (0xFFFFFF08) // (MC) MC Abort Address Status Register -#define AT91C_MC_RCR (0xFFFFFF00) // (MC) MC Remap Control Register -// ========== Register definition for PDC_SPI peripheral ========== -#define AT91C_SPI_PTCR (0xFFFE0120) // (PDC_SPI) PDC Transfer Control Register -#define AT91C_SPI_TNPR (0xFFFE0118) // (PDC_SPI) Transmit Next Pointer Register -#define AT91C_SPI_RNPR (0xFFFE0110) // (PDC_SPI) Receive Next Pointer Register -#define AT91C_SPI_TPR (0xFFFE0108) // (PDC_SPI) Transmit Pointer Register -#define AT91C_SPI_RPR (0xFFFE0100) // (PDC_SPI) Receive Pointer Register -#define AT91C_SPI_PTSR (0xFFFE0124) // (PDC_SPI) PDC Transfer Status Register -#define AT91C_SPI_TNCR (0xFFFE011C) // (PDC_SPI) Transmit Next Counter Register -#define AT91C_SPI_RNCR (0xFFFE0114) // (PDC_SPI) Receive Next Counter Register -#define AT91C_SPI_TCR (0xFFFE010C) // (PDC_SPI) Transmit Counter Register -#define AT91C_SPI_RCR (0xFFFE0104) // (PDC_SPI) Receive Counter Register -// ========== Register definition for SPI peripheral ========== -#define AT91C_SPI_CSR (0xFFFE0030) // (SPI) Chip Select Register -#define AT91C_SPI_IDR (0xFFFE0018) // (SPI) Interrupt Disable Register -#define AT91C_SPI_SR (0xFFFE0010) // (SPI) Status Register -#define AT91C_SPI_RDR (0xFFFE0008) // (SPI) Receive Data Register -#define AT91C_SPI_CR (0xFFFE0000) // (SPI) Control Register -#define AT91C_SPI_IMR (0xFFFE001C) // (SPI) Interrupt Mask Register -#define AT91C_SPI_IER (0xFFFE0014) // (SPI) Interrupt Enable Register -#define AT91C_SPI_TDR (0xFFFE000C) // (SPI) Transmit Data Register -#define AT91C_SPI_MR (0xFFFE0004) // (SPI) Mode Register -// ========== Register definition for PDC_ADC peripheral ========== -#define AT91C_ADC_PTCR (0xFFFD8120) // (PDC_ADC) PDC Transfer Control Register -#define AT91C_ADC_TNPR (0xFFFD8118) // (PDC_ADC) Transmit Next Pointer Register -#define AT91C_ADC_RNPR (0xFFFD8110) // (PDC_ADC) Receive Next Pointer Register -#define AT91C_ADC_TPR (0xFFFD8108) // (PDC_ADC) Transmit Pointer Register -#define AT91C_ADC_RPR (0xFFFD8100) // (PDC_ADC) Receive Pointer Register -#define AT91C_ADC_PTSR (0xFFFD8124) // (PDC_ADC) PDC Transfer Status Register -#define AT91C_ADC_TNCR (0xFFFD811C) // (PDC_ADC) Transmit Next Counter Register -#define AT91C_ADC_RNCR (0xFFFD8114) // (PDC_ADC) Receive Next Counter Register -#define AT91C_ADC_TCR (0xFFFD810C) // (PDC_ADC) Transmit Counter Register -#define AT91C_ADC_RCR (0xFFFD8104) // (PDC_ADC) Receive Counter Register -// ========== Register definition for ADC peripheral ========== -#define AT91C_ADC_IMR (0xFFFD802C) // (ADC) ADC Interrupt Mask Register -#define AT91C_ADC_CDR4 (0xFFFD8040) // (ADC) ADC Channel Data Register 4 -#define AT91C_ADC_CDR2 (0xFFFD8038) // (ADC) ADC Channel Data Register 2 -#define AT91C_ADC_CDR0 (0xFFFD8030) // (ADC) ADC Channel Data Register 0 -#define AT91C_ADC_CDR7 (0xFFFD804C) // (ADC) ADC Channel Data Register 7 -#define AT91C_ADC_CDR1 (0xFFFD8034) // (ADC) ADC Channel Data Register 1 -#define AT91C_ADC_CDR3 (0xFFFD803C) // (ADC) ADC Channel Data Register 3 -#define AT91C_ADC_CDR5 (0xFFFD8044) // (ADC) ADC Channel Data Register 5 -#define AT91C_ADC_MR (0xFFFD8004) // (ADC) ADC Mode Register -#define AT91C_ADC_CDR6 (0xFFFD8048) // (ADC) ADC Channel Data Register 6 -#define AT91C_ADC_CR (0xFFFD8000) // (ADC) ADC Control Register -#define AT91C_ADC_CHER (0xFFFD8010) // (ADC) ADC Channel Enable Register -#define AT91C_ADC_CHSR (0xFFFD8018) // (ADC) ADC Channel Status Register -#define AT91C_ADC_IER (0xFFFD8024) // (ADC) ADC Interrupt Enable Register -#define AT91C_ADC_SR (0xFFFD801C) // (ADC) ADC Status Register -#define AT91C_ADC_CHDR (0xFFFD8014) // (ADC) ADC Channel Disable Register -#define AT91C_ADC_IDR (0xFFFD8028) // (ADC) ADC Interrupt Disable Register -#define AT91C_ADC_LCDR (0xFFFD8020) // (ADC) ADC Last Converted Data Register -// ========== Register definition for PDC_SSC peripheral ========== -#define AT91C_SSC_PTCR (0xFFFD4120) // (PDC_SSC) PDC Transfer Control Register -#define AT91C_SSC_TNPR (0xFFFD4118) // (PDC_SSC) Transmit Next Pointer Register -#define AT91C_SSC_RNPR (0xFFFD4110) // (PDC_SSC) Receive Next Pointer Register -#define AT91C_SSC_TPR (0xFFFD4108) // (PDC_SSC) Transmit Pointer Register -#define AT91C_SSC_RPR (0xFFFD4100) // (PDC_SSC) Receive Pointer Register -#define AT91C_SSC_PTSR (0xFFFD4124) // (PDC_SSC) PDC Transfer Status Register -#define AT91C_SSC_TNCR (0xFFFD411C) // (PDC_SSC) Transmit Next Counter Register -#define AT91C_SSC_RNCR (0xFFFD4114) // (PDC_SSC) Receive Next Counter Register -#define AT91C_SSC_TCR (0xFFFD410C) // (PDC_SSC) Transmit Counter Register -#define AT91C_SSC_RCR (0xFFFD4104) // (PDC_SSC) Receive Counter Register -// ========== Register definition for SSC peripheral ========== -#define AT91C_SSC_RFMR (0xFFFD4014) // (SSC) Receive Frame Mode Register -#define AT91C_SSC_CMR (0xFFFD4004) // (SSC) Clock Mode Register -#define AT91C_SSC_IDR (0xFFFD4048) // (SSC) Interrupt Disable Register -#define AT91C_SSC_SR (0xFFFD4040) // (SSC) Status Register -#define AT91C_SSC_RC0R (0xFFFD4038) // (SSC) Receive Compare 0 Register -#define AT91C_SSC_RSHR (0xFFFD4030) // (SSC) Receive Sync Holding Register -#define AT91C_SSC_RHR (0xFFFD4020) // (SSC) Receive Holding Register -#define AT91C_SSC_TCMR (0xFFFD4018) // (SSC) Transmit Clock Mode Register -#define AT91C_SSC_RCMR (0xFFFD4010) // (SSC) Receive Clock ModeRegister -#define AT91C_SSC_CR (0xFFFD4000) // (SSC) Control Register -#define AT91C_SSC_IMR (0xFFFD404C) // (SSC) Interrupt Mask Register -#define AT91C_SSC_IER (0xFFFD4044) // (SSC) Interrupt Enable Register -#define AT91C_SSC_RC1R (0xFFFD403C) // (SSC) Receive Compare 1 Register -#define AT91C_SSC_TSHR (0xFFFD4034) // (SSC) Transmit Sync Holding Register -#define AT91C_SSC_THR (0xFFFD4024) // (SSC) Transmit Holding Register -#define AT91C_SSC_TFMR (0xFFFD401C) // (SSC) Transmit Frame Mode Register -// ========== Register definition for PDC_US1 peripheral ========== -#define AT91C_US1_PTSR (0xFFFC4124) // (PDC_US1) PDC Transfer Status Register -#define AT91C_US1_TNCR (0xFFFC411C) // (PDC_US1) Transmit Next Counter Register -#define AT91C_US1_RNCR (0xFFFC4114) // (PDC_US1) Receive Next Counter Register -#define AT91C_US1_TCR (0xFFFC410C) // (PDC_US1) Transmit Counter Register -#define AT91C_US1_RCR (0xFFFC4104) // (PDC_US1) Receive Counter Register -#define AT91C_US1_PTCR (0xFFFC4120) // (PDC_US1) PDC Transfer Control Register -#define AT91C_US1_TNPR (0xFFFC4118) // (PDC_US1) Transmit Next Pointer Register -#define AT91C_US1_RNPR (0xFFFC4110) // (PDC_US1) Receive Next Pointer Register -#define AT91C_US1_TPR (0xFFFC4108) // (PDC_US1) Transmit Pointer Register -#define AT91C_US1_RPR (0xFFFC4100) // (PDC_US1) Receive Pointer Register -// ========== Register definition for US1 peripheral ========== -#define AT91C_US1_XXR (0xFFFC4048) // (US1) XON_XOFF Register -#define AT91C_US1_RHR (0xFFFC4018) // (US1) Receiver Holding Register -#define AT91C_US1_IMR (0xFFFC4010) // (US1) Interrupt Mask Register -#define AT91C_US1_IER (0xFFFC4008) // (US1) Interrupt Enable Register -#define AT91C_US1_CR (0xFFFC4000) // (US1) Control Register -#define AT91C_US1_RTOR (0xFFFC4024) // (US1) Receiver Time-out Register -#define AT91C_US1_THR (0xFFFC401C) // (US1) Transmitter Holding Register -#define AT91C_US1_CSR (0xFFFC4014) // (US1) Channel Status Register -#define AT91C_US1_IDR (0xFFFC400C) // (US1) Interrupt Disable Register -#define AT91C_US1_FIDI (0xFFFC4040) // (US1) FI_DI_Ratio Register -#define AT91C_US1_BRGR (0xFFFC4020) // (US1) Baud Rate Generator Register -#define AT91C_US1_TTGR (0xFFFC4028) // (US1) Transmitter Time-guard Register -#define AT91C_US1_IF (0xFFFC404C) // (US1) IRDA_FILTER Register -#define AT91C_US1_NER (0xFFFC4044) // (US1) Nb Errors Register -#define AT91C_US1_MR (0xFFFC4004) // (US1) Mode Register -// ========== Register definition for PDC_US0 peripheral ========== -#define AT91C_US0_PTCR (0xFFFC0120) // (PDC_US0) PDC Transfer Control Register -#define AT91C_US0_TNPR (0xFFFC0118) // (PDC_US0) Transmit Next Pointer Register -#define AT91C_US0_RNPR (0xFFFC0110) // (PDC_US0) Receive Next Pointer Register -#define AT91C_US0_TPR (0xFFFC0108) // (PDC_US0) Transmit Pointer Register -#define AT91C_US0_RPR (0xFFFC0100) // (PDC_US0) Receive Pointer Register -#define AT91C_US0_PTSR (0xFFFC0124) // (PDC_US0) PDC Transfer Status Register -#define AT91C_US0_TNCR (0xFFFC011C) // (PDC_US0) Transmit Next Counter Register -#define AT91C_US0_RNCR (0xFFFC0114) // (PDC_US0) Receive Next Counter Register -#define AT91C_US0_TCR (0xFFFC010C) // (PDC_US0) Transmit Counter Register -#define AT91C_US0_RCR (0xFFFC0104) // (PDC_US0) Receive Counter Register -// ========== Register definition for US0 peripheral ========== -#define AT91C_US0_TTGR (0xFFFC0028) // (US0) Transmitter Time-guard Register -#define AT91C_US0_BRGR (0xFFFC0020) // (US0) Baud Rate Generator Register -#define AT91C_US0_RHR (0xFFFC0018) // (US0) Receiver Holding Register -#define AT91C_US0_IMR (0xFFFC0010) // (US0) Interrupt Mask Register -#define AT91C_US0_NER (0xFFFC0044) // (US0) Nb Errors Register -#define AT91C_US0_RTOR (0xFFFC0024) // (US0) Receiver Time-out Register -#define AT91C_US0_XXR (0xFFFC0048) // (US0) XON_XOFF Register -#define AT91C_US0_FIDI (0xFFFC0040) // (US0) FI_DI_Ratio Register -#define AT91C_US0_CR (0xFFFC0000) // (US0) Control Register -#define AT91C_US0_IER (0xFFFC0008) // (US0) Interrupt Enable Register -#define AT91C_US0_IF (0xFFFC004C) // (US0) IRDA_FILTER Register -#define AT91C_US0_MR (0xFFFC0004) // (US0) Mode Register -#define AT91C_US0_IDR (0xFFFC000C) // (US0) Interrupt Disable Register -#define AT91C_US0_CSR (0xFFFC0014) // (US0) Channel Status Register -#define AT91C_US0_THR (0xFFFC001C) // (US0) Transmitter Holding Register -// ========== Register definition for TWI peripheral ========== -#define AT91C_TWI_RHR (0xFFFB8030) // (TWI) Receive Holding Register -#define AT91C_TWI_IDR (0xFFFB8028) // (TWI) Interrupt Disable Register -#define AT91C_TWI_SR (0xFFFB8020) // (TWI) Status Register -#define AT91C_TWI_CWGR (0xFFFB8010) // (TWI) Clock Waveform Generator Register -#define AT91C_TWI_SMR (0xFFFB8008) // (TWI) Slave Mode Register -#define AT91C_TWI_CR (0xFFFB8000) // (TWI) Control Register -#define AT91C_TWI_THR (0xFFFB8034) // (TWI) Transmit Holding Register -#define AT91C_TWI_IMR (0xFFFB802C) // (TWI) Interrupt Mask Register -#define AT91C_TWI_IER (0xFFFB8024) // (TWI) Interrupt Enable Register -#define AT91C_TWI_IADR (0xFFFB800C) // (TWI) Internal Address Register -#define AT91C_TWI_MMR (0xFFFB8004) // (TWI) Master Mode Register -// ========== Register definition for TC2 peripheral ========== -#define AT91C_TC2_IMR (0xFFFA00AC) // (TC2) Interrupt Mask Register -#define AT91C_TC2_IER (0xFFFA00A4) // (TC2) Interrupt Enable Register -#define AT91C_TC2_RC (0xFFFA009C) // (TC2) Register C -#define AT91C_TC2_RA (0xFFFA0094) // (TC2) Register A -#define AT91C_TC2_CMR (0xFFFA0084) // (TC2) Channel Mode Register (Capture Mode / Waveform Mode) -#define AT91C_TC2_IDR (0xFFFA00A8) // (TC2) Interrupt Disable Register -#define AT91C_TC2_SR (0xFFFA00A0) // (TC2) Status Register -#define AT91C_TC2_RB (0xFFFA0098) // (TC2) Register B -#define AT91C_TC2_CV (0xFFFA0090) // (TC2) Counter Value -#define AT91C_TC2_CCR (0xFFFA0080) // (TC2) Channel Control Register -// ========== Register definition for TC1 peripheral ========== -#define AT91C_TC1_IMR (0xFFFA006C) // (TC1) Interrupt Mask Register -#define AT91C_TC1_IER (0xFFFA0064) // (TC1) Interrupt Enable Register -#define AT91C_TC1_RC (0xFFFA005C) // (TC1) Register C -#define AT91C_TC1_RA (0xFFFA0054) // (TC1) Register A -#define AT91C_TC1_CMR (0xFFFA0044) // (TC1) Channel Mode Register (Capture Mode / Waveform Mode) -#define AT91C_TC1_IDR (0xFFFA0068) // (TC1) Interrupt Disable Register -#define AT91C_TC1_SR (0xFFFA0060) // (TC1) Status Register -#define AT91C_TC1_RB (0xFFFA0058) // (TC1) Register B -#define AT91C_TC1_CV (0xFFFA0050) // (TC1) Counter Value -#define AT91C_TC1_CCR (0xFFFA0040) // (TC1) Channel Control Register -// ========== Register definition for TC0 peripheral ========== -#define AT91C_TC0_IMR (0xFFFA002C) // (TC0) Interrupt Mask Register -#define AT91C_TC0_IER (0xFFFA0024) // (TC0) Interrupt Enable Register -#define AT91C_TC0_RC (0xFFFA001C) // (TC0) Register C -#define AT91C_TC0_RA (0xFFFA0014) // (TC0) Register A -#define AT91C_TC0_CMR (0xFFFA0004) // (TC0) Channel Mode Register (Capture Mode / Waveform Mode) -#define AT91C_TC0_IDR (0xFFFA0028) // (TC0) Interrupt Disable Register -#define AT91C_TC0_SR (0xFFFA0020) // (TC0) Status Register -#define AT91C_TC0_RB (0xFFFA0018) // (TC0) Register B -#define AT91C_TC0_CV (0xFFFA0010) // (TC0) Counter Value -#define AT91C_TC0_CCR (0xFFFA0000) // (TC0) Channel Control Register -// ========== Register definition for TCB peripheral ========== -#define AT91C_TCB_BMR (0xFFFA00C4) // (TCB) TC Block Mode Register -#define AT91C_TCB_BCR (0xFFFA00C0) // (TCB) TC Block Control Register -// ========== Register definition for PWMC_CH3 peripheral ========== -#define AT91C_CH3_CUPDR (0xFFFCC270) // (PWMC_CH3) Channel Update Register -#define AT91C_CH3_CPRDR (0xFFFCC268) // (PWMC_CH3) Channel Period Register -#define AT91C_CH3_CMR (0xFFFCC260) // (PWMC_CH3) Channel Mode Register -#define AT91C_CH3_Reserved (0xFFFCC274) // (PWMC_CH3) Reserved -#define AT91C_CH3_CCNTR (0xFFFCC26C) // (PWMC_CH3) Channel Counter Register -#define AT91C_CH3_CDTYR (0xFFFCC264) // (PWMC_CH3) Channel Duty Cycle Register -// ========== Register definition for PWMC_CH2 peripheral ========== -#define AT91C_CH2_CUPDR (0xFFFCC250) // (PWMC_CH2) Channel Update Register -#define AT91C_CH2_CPRDR (0xFFFCC248) // (PWMC_CH2) Channel Period Register -#define AT91C_CH2_CMR (0xFFFCC240) // (PWMC_CH2) Channel Mode Register -#define AT91C_CH2_Reserved (0xFFFCC254) // (PWMC_CH2) Reserved -#define AT91C_CH2_CCNTR (0xFFFCC24C) // (PWMC_CH2) Channel Counter Register -#define AT91C_CH2_CDTYR (0xFFFCC244) // (PWMC_CH2) Channel Duty Cycle Register -// ========== Register definition for PWMC_CH1 peripheral ========== -#define AT91C_CH1_CUPDR (0xFFFCC230) // (PWMC_CH1) Channel Update Register -#define AT91C_CH1_CPRDR (0xFFFCC228) // (PWMC_CH1) Channel Period Register -#define AT91C_CH1_CMR (0xFFFCC220) // (PWMC_CH1) Channel Mode Register -#define AT91C_CH1_Reserved (0xFFFCC234) // (PWMC_CH1) Reserved -#define AT91C_CH1_CCNTR (0xFFFCC22C) // (PWMC_CH1) Channel Counter Register -#define AT91C_CH1_CDTYR (0xFFFCC224) // (PWMC_CH1) Channel Duty Cycle Register -// ========== Register definition for PWMC_CH0 peripheral ========== -#define AT91C_CH0_CUPDR (0xFFFCC210) // (PWMC_CH0) Channel Update Register -#define AT91C_CH0_CPRDR (0xFFFCC208) // (PWMC_CH0) Channel Period Register -#define AT91C_CH0_CMR (0xFFFCC200) // (PWMC_CH0) Channel Mode Register -#define AT91C_CH0_Reserved (0xFFFCC214) // (PWMC_CH0) Reserved -#define AT91C_CH0_CCNTR (0xFFFCC20C) // (PWMC_CH0) Channel Counter Register -#define AT91C_CH0_CDTYR (0xFFFCC204) // (PWMC_CH0) Channel Duty Cycle Register -// ========== Register definition for PWMC peripheral ========== -#define AT91C_PWMC_VR (0xFFFCC0FC) // (PWMC) PWMC Version Register -#define AT91C_PWMC_ISR (0xFFFCC01C) // (PWMC) PWMC Interrupt Status Register -#define AT91C_PWMC_IDR (0xFFFCC014) // (PWMC) PWMC Interrupt Disable Register -#define AT91C_PWMC_SR (0xFFFCC00C) // (PWMC) PWMC Status Register -#define AT91C_PWMC_ENA (0xFFFCC004) // (PWMC) PWMC Enable Register -#define AT91C_PWMC_IMR (0xFFFCC018) // (PWMC) PWMC Interrupt Mask Register -#define AT91C_PWMC_MR (0xFFFCC000) // (PWMC) PWMC Mode Register -#define AT91C_PWMC_DIS (0xFFFCC008) // (PWMC) PWMC Disable Register -#define AT91C_PWMC_IER (0xFFFCC010) // (PWMC) PWMC Interrupt Enable Register -// ========== Register definition for UDP peripheral ========== -#define AT91C_UDP_ISR (0xFFFB001C) // (UDP) Interrupt Status Register -#define AT91C_UDP_IDR (0xFFFB0014) // (UDP) Interrupt Disable Register -#define AT91C_UDP_GLBSTATE (0xFFFB0004) // (UDP) Global State Register -#define AT91C_UDP_FDR (0xFFFB0050) // (UDP) Endpoint FIFO Data Register -#define AT91C_UDP_CSR (0xFFFB0030) // (UDP) Endpoint Control and Status Register -#define AT91C_UDP_RSTEP (0xFFFB0028) // (UDP) Reset Endpoint Register -#define AT91C_UDP_ICR (0xFFFB0020) // (UDP) Interrupt Clear Register -#define AT91C_UDP_IMR (0xFFFB0018) // (UDP) Interrupt Mask Register -#define AT91C_UDP_IER (0xFFFB0010) // (UDP) Interrupt Enable Register -#define AT91C_UDP_FADDR (0xFFFB0008) // (UDP) Function Address Register -#define AT91C_UDP_NUM (0xFFFB0000) // (UDP) Frame Number Register +/* ***************************************************************************** */ +/* REGISTER ADDRESS DEFINITION FOR AT91SAM7S64 */ +/* ***************************************************************************** */ +/* ========== Register definition for SYSC peripheral ========== */ +#define AT91C_SYSC_SYSC_VRPM ( 0xFFFFFD60 ) /* (SYSC) Voltage Regulator Power Mode Register */ +/* ========== Register definition for AIC peripheral ========== */ +#define AT91C_AIC_ICCR ( 0xFFFFF128 ) /* (AIC) Interrupt Clear Command Register */ +#define AT91C_AIC_IECR ( 0xFFFFF120 ) /* (AIC) Interrupt Enable Command Register */ +#define AT91C_AIC_SMR ( 0xFFFFF000 ) /* (AIC) Source Mode Register */ +#define AT91C_AIC_ISCR ( 0xFFFFF12C ) /* (AIC) Interrupt Set Command Register */ +#define AT91C_AIC_EOICR ( 0xFFFFF130 ) /* (AIC) End of Interrupt Command Register */ +#define AT91C_AIC_DCR ( 0xFFFFF138 ) /* (AIC) Debug Control Register (Protect) */ +#define AT91C_AIC_FFER ( 0xFFFFF140 ) /* (AIC) Fast Forcing Enable Register */ +#define AT91C_AIC_SVR ( 0xFFFFF080 ) /* (AIC) Source Vector Register */ +#define AT91C_AIC_SPU ( 0xFFFFF134 ) /* (AIC) Spurious Vector Register */ +#define AT91C_AIC_FFDR ( 0xFFFFF144 ) /* (AIC) Fast Forcing Disable Register */ +#define AT91C_AIC_FVR ( 0xFFFFF104 ) /* (AIC) FIQ Vector Register */ +#define AT91C_AIC_FFSR ( 0xFFFFF148 ) /* (AIC) Fast Forcing Status Register */ +#define AT91C_AIC_IMR ( 0xFFFFF110 ) /* (AIC) Interrupt Mask Register */ +#define AT91C_AIC_ISR ( 0xFFFFF108 ) /* (AIC) Interrupt Status Register */ +#define AT91C_AIC_IVR ( 0xFFFFF100 ) /* (AIC) IRQ Vector Register */ +#define AT91C_AIC_IDCR ( 0xFFFFF124 ) /* (AIC) Interrupt Disable Command Register */ +#define AT91C_AIC_CISR ( 0xFFFFF114 ) /* (AIC) Core Interrupt Status Register */ +#define AT91C_AIC_IPR ( 0xFFFFF10C ) /* (AIC) Interrupt Pending Register */ +/* ========== Register definition for DBGU peripheral ========== */ +#define AT91C_DBGU_C2R ( 0xFFFFF244 ) /* (DBGU) Chip ID2 Register */ +#define AT91C_DBGU_THR ( 0xFFFFF21C ) /* (DBGU) Transmitter Holding Register */ +#define AT91C_DBGU_CSR ( 0xFFFFF214 ) /* (DBGU) Channel Status Register */ +#define AT91C_DBGU_IDR ( 0xFFFFF20C ) /* (DBGU) Interrupt Disable Register */ +#define AT91C_DBGU_MR ( 0xFFFFF204 ) /* (DBGU) Mode Register */ +#define AT91C_DBGU_FNTR ( 0xFFFFF248 ) /* (DBGU) Force NTRST Register */ +#define AT91C_DBGU_C1R ( 0xFFFFF240 ) /* (DBGU) Chip ID1 Register */ +#define AT91C_DBGU_BRGR ( 0xFFFFF220 ) /* (DBGU) Baud Rate Generator Register */ +#define AT91C_DBGU_RHR ( 0xFFFFF218 ) /* (DBGU) Receiver Holding Register */ +#define AT91C_DBGU_IMR ( 0xFFFFF210 ) /* (DBGU) Interrupt Mask Register */ +#define AT91C_DBGU_IER ( 0xFFFFF208 ) /* (DBGU) Interrupt Enable Register */ +#define AT91C_DBGU_CR ( 0xFFFFF200 ) /* (DBGU) Control Register */ +/* ========== Register definition for PDC_DBGU peripheral ========== */ +#define AT91C_DBGU_TNCR ( 0xFFFFF31C ) /* (PDC_DBGU) Transmit Next Counter Register */ +#define AT91C_DBGU_RNCR ( 0xFFFFF314 ) /* (PDC_DBGU) Receive Next Counter Register */ +#define AT91C_DBGU_PTCR ( 0xFFFFF320 ) /* (PDC_DBGU) PDC Transfer Control Register */ +#define AT91C_DBGU_PTSR ( 0xFFFFF324 ) /* (PDC_DBGU) PDC Transfer Status Register */ +#define AT91C_DBGU_RCR ( 0xFFFFF304 ) /* (PDC_DBGU) Receive Counter Register */ +#define AT91C_DBGU_TCR ( 0xFFFFF30C ) /* (PDC_DBGU) Transmit Counter Register */ +#define AT91C_DBGU_RPR ( 0xFFFFF300 ) /* (PDC_DBGU) Receive Pointer Register */ +#define AT91C_DBGU_TPR ( 0xFFFFF308 ) /* (PDC_DBGU) Transmit Pointer Register */ +#define AT91C_DBGU_RNPR ( 0xFFFFF310 ) /* (PDC_DBGU) Receive Next Pointer Register */ +#define AT91C_DBGU_TNPR ( 0xFFFFF318 ) /* (PDC_DBGU) Transmit Next Pointer Register */ +/* ========== Register definition for PIOA peripheral ========== */ +#define AT91C_PIOA_IMR ( 0xFFFFF448 ) /* (PIOA) Interrupt Mask Register */ +#define AT91C_PIOA_IER ( 0xFFFFF440 ) /* (PIOA) Interrupt Enable Register */ +#define AT91C_PIOA_OWDR ( 0xFFFFF4A4 ) /* (PIOA) Output Write Disable Register */ +#define AT91C_PIOA_ISR ( 0xFFFFF44C ) /* (PIOA) Interrupt Status Register */ +#define AT91C_PIOA_PPUDR ( 0xFFFFF460 ) /* (PIOA) Pull-up Disable Register */ +#define AT91C_PIOA_MDSR ( 0xFFFFF458 ) /* (PIOA) Multi-driver Status Register */ +#define AT91C_PIOA_MDER ( 0xFFFFF450 ) /* (PIOA) Multi-driver Enable Register */ +#define AT91C_PIOA_PER ( 0xFFFFF400 ) /* (PIOA) PIO Enable Register */ +#define AT91C_PIOA_PSR ( 0xFFFFF408 ) /* (PIOA) PIO Status Register */ +#define AT91C_PIOA_OER ( 0xFFFFF410 ) /* (PIOA) Output Enable Register */ +#define AT91C_PIOA_BSR ( 0xFFFFF474 ) /* (PIOA) Select B Register */ +#define AT91C_PIOA_PPUER ( 0xFFFFF464 ) /* (PIOA) Pull-up Enable Register */ +#define AT91C_PIOA_MDDR ( 0xFFFFF454 ) /* (PIOA) Multi-driver Disable Register */ +#define AT91C_PIOA_PDR ( 0xFFFFF404 ) /* (PIOA) PIO Disable Register */ +#define AT91C_PIOA_ODR ( 0xFFFFF414 ) /* (PIOA) Output Disable Registerr */ +#define AT91C_PIOA_IFDR ( 0xFFFFF424 ) /* (PIOA) Input Filter Disable Register */ +#define AT91C_PIOA_ABSR ( 0xFFFFF478 ) /* (PIOA) AB Select Status Register */ +#define AT91C_PIOA_ASR ( 0xFFFFF470 ) /* (PIOA) Select A Register */ +#define AT91C_PIOA_PPUSR ( 0xFFFFF468 ) /* (PIOA) Pad Pull-up Status Register */ +#define AT91C_PIOA_ODSR ( 0xFFFFF438 ) /* (PIOA) Output Data Status Register */ +#define AT91C_PIOA_SODR ( 0xFFFFF430 ) /* (PIOA) Set Output Data Register */ +#define AT91C_PIOA_IFSR ( 0xFFFFF428 ) /* (PIOA) Input Filter Status Register */ +#define AT91C_PIOA_IFER ( 0xFFFFF420 ) /* (PIOA) Input Filter Enable Register */ +#define AT91C_PIOA_OSR ( 0xFFFFF418 ) /* (PIOA) Output Status Register */ +#define AT91C_PIOA_IDR ( 0xFFFFF444 ) /* (PIOA) Interrupt Disable Register */ +#define AT91C_PIOA_PDSR ( 0xFFFFF43C ) /* (PIOA) Pin Data Status Register */ +#define AT91C_PIOA_CODR ( 0xFFFFF434 ) /* (PIOA) Clear Output Data Register */ +#define AT91C_PIOA_OWSR ( 0xFFFFF4A8 ) /* (PIOA) Output Write Status Register */ +#define AT91C_PIOA_OWER ( 0xFFFFF4A0 ) /* (PIOA) Output Write Enable Register */ +/* ========== Register definition for CKGR peripheral ========== */ +#define AT91C_CKGR_PLLR ( 0xFFFFFC2C ) /* (CKGR) PLL Register */ +#define AT91C_CKGR_MCFR ( 0xFFFFFC24 ) /* (CKGR) Main Clock Frequency Register */ +#define AT91C_CKGR_MOR ( 0xFFFFFC20 ) /* (CKGR) Main Oscillator Register */ +/* ========== Register definition for PMC peripheral ========== */ +#define AT91C_PMC_SCSR ( 0xFFFFFC08 ) /* (PMC) System Clock Status Register */ +#define AT91C_PMC_SCER ( 0xFFFFFC00 ) /* (PMC) System Clock Enable Register */ +#define AT91C_PMC_IMR ( 0xFFFFFC6C ) /* (PMC) Interrupt Mask Register */ +#define AT91C_PMC_IDR ( 0xFFFFFC64 ) /* (PMC) Interrupt Disable Register */ +#define AT91C_PMC_PCDR ( 0xFFFFFC14 ) /* (PMC) Peripheral Clock Disable Register */ +#define AT91C_PMC_SCDR ( 0xFFFFFC04 ) /* (PMC) System Clock Disable Register */ +#define AT91C_PMC_SR ( 0xFFFFFC68 ) /* (PMC) Status Register */ +#define AT91C_PMC_IER ( 0xFFFFFC60 ) /* (PMC) Interrupt Enable Register */ +#define AT91C_PMC_MCKR ( 0xFFFFFC30 ) /* (PMC) Master Clock Register */ +#define AT91C_PMC_MOR ( 0xFFFFFC20 ) /* (PMC) Main Oscillator Register */ +#define AT91C_PMC_PCER ( 0xFFFFFC10 ) /* (PMC) Peripheral Clock Enable Register */ +#define AT91C_PMC_PCSR ( 0xFFFFFC18 ) /* (PMC) Peripheral Clock Status Register */ +#define AT91C_PMC_PLLR ( 0xFFFFFC2C ) /* (PMC) PLL Register */ +#define AT91C_PMC_MCFR ( 0xFFFFFC24 ) /* (PMC) Main Clock Frequency Register */ +#define AT91C_PMC_PCKR ( 0xFFFFFC40 ) /* (PMC) Programmable Clock Register */ +/* ========== Register definition for RSTC peripheral ========== */ +#define AT91C_RSTC_RSR ( 0xFFFFFD04 ) /* (RSTC) Reset Status Register */ +#define AT91C_RSTC_RMR ( 0xFFFFFD08 ) /* (RSTC) Reset Mode Register */ +#define AT91C_RSTC_RCR ( 0xFFFFFD00 ) /* (RSTC) Reset Control Register */ +/* ========== Register definition for RTTC peripheral ========== */ +#define AT91C_RTTC_RTSR ( 0xFFFFFD2C ) /* (RTTC) Real-time Status Register */ +#define AT91C_RTTC_RTAR ( 0xFFFFFD24 ) /* (RTTC) Real-time Alarm Register */ +#define AT91C_RTTC_RTVR ( 0xFFFFFD28 ) /* (RTTC) Real-time Value Register */ +#define AT91C_RTTC_RTMR ( 0xFFFFFD20 ) /* (RTTC) Real-time Mode Register */ +/* ========== Register definition for PITC peripheral ========== */ +#define AT91C_PITC_PIIR ( 0xFFFFFD3C ) /* (PITC) Period Interval Image Register */ +#define AT91C_PITC_PISR ( 0xFFFFFD34 ) /* (PITC) Period Interval Status Register */ +#define AT91C_PITC_PIVR ( 0xFFFFFD38 ) /* (PITC) Period Interval Value Register */ +#define AT91C_PITC_PIMR ( 0xFFFFFD30 ) /* (PITC) Period Interval Mode Register */ +/* ========== Register definition for WDTC peripheral ========== */ +#define AT91C_WDTC_WDMR ( 0xFFFFFD44 ) /* (WDTC) Watchdog Mode Register */ +#define AT91C_WDTC_WDSR ( 0xFFFFFD48 ) /* (WDTC) Watchdog Status Register */ +#define AT91C_WDTC_WDCR ( 0xFFFFFD40 ) /* (WDTC) Watchdog Control Register */ +/* ========== Register definition for MC peripheral ========== */ +#define AT91C_MC_FCR ( 0xFFFFFF64 ) /* (MC) MC Flash Command Register */ +#define AT91C_MC_ASR ( 0xFFFFFF04 ) /* (MC) MC Abort Status Register */ +#define AT91C_MC_FSR ( 0xFFFFFF68 ) /* (MC) MC Flash Status Register */ +#define AT91C_MC_FMR ( 0xFFFFFF60 ) /* (MC) MC Flash Mode Register */ +#define AT91C_MC_AASR ( 0xFFFFFF08 ) /* (MC) MC Abort Address Status Register */ +#define AT91C_MC_RCR ( 0xFFFFFF00 ) /* (MC) MC Remap Control Register */ +/* ========== Register definition for PDC_SPI peripheral ========== */ +#define AT91C_SPI_PTCR ( 0xFFFE0120 ) /* (PDC_SPI) PDC Transfer Control Register */ +#define AT91C_SPI_TNPR ( 0xFFFE0118 ) /* (PDC_SPI) Transmit Next Pointer Register */ +#define AT91C_SPI_RNPR ( 0xFFFE0110 ) /* (PDC_SPI) Receive Next Pointer Register */ +#define AT91C_SPI_TPR ( 0xFFFE0108 ) /* (PDC_SPI) Transmit Pointer Register */ +#define AT91C_SPI_RPR ( 0xFFFE0100 ) /* (PDC_SPI) Receive Pointer Register */ +#define AT91C_SPI_PTSR ( 0xFFFE0124 ) /* (PDC_SPI) PDC Transfer Status Register */ +#define AT91C_SPI_TNCR ( 0xFFFE011C ) /* (PDC_SPI) Transmit Next Counter Register */ +#define AT91C_SPI_RNCR ( 0xFFFE0114 ) /* (PDC_SPI) Receive Next Counter Register */ +#define AT91C_SPI_TCR ( 0xFFFE010C ) /* (PDC_SPI) Transmit Counter Register */ +#define AT91C_SPI_RCR ( 0xFFFE0104 ) /* (PDC_SPI) Receive Counter Register */ +/* ========== Register definition for SPI peripheral ========== */ +#define AT91C_SPI_CSR ( 0xFFFE0030 ) /* (SPI) Chip Select Register */ +#define AT91C_SPI_IDR ( 0xFFFE0018 ) /* (SPI) Interrupt Disable Register */ +#define AT91C_SPI_SR ( 0xFFFE0010 ) /* (SPI) Status Register */ +#define AT91C_SPI_RDR ( 0xFFFE0008 ) /* (SPI) Receive Data Register */ +#define AT91C_SPI_CR ( 0xFFFE0000 ) /* (SPI) Control Register */ +#define AT91C_SPI_IMR ( 0xFFFE001C ) /* (SPI) Interrupt Mask Register */ +#define AT91C_SPI_IER ( 0xFFFE0014 ) /* (SPI) Interrupt Enable Register */ +#define AT91C_SPI_TDR ( 0xFFFE000C ) /* (SPI) Transmit Data Register */ +#define AT91C_SPI_MR ( 0xFFFE0004 ) /* (SPI) Mode Register */ +/* ========== Register definition for PDC_ADC peripheral ========== */ +#define AT91C_ADC_PTCR ( 0xFFFD8120 ) /* (PDC_ADC) PDC Transfer Control Register */ +#define AT91C_ADC_TNPR ( 0xFFFD8118 ) /* (PDC_ADC) Transmit Next Pointer Register */ +#define AT91C_ADC_RNPR ( 0xFFFD8110 ) /* (PDC_ADC) Receive Next Pointer Register */ +#define AT91C_ADC_TPR ( 0xFFFD8108 ) /* (PDC_ADC) Transmit Pointer Register */ +#define AT91C_ADC_RPR ( 0xFFFD8100 ) /* (PDC_ADC) Receive Pointer Register */ +#define AT91C_ADC_PTSR ( 0xFFFD8124 ) /* (PDC_ADC) PDC Transfer Status Register */ +#define AT91C_ADC_TNCR ( 0xFFFD811C ) /* (PDC_ADC) Transmit Next Counter Register */ +#define AT91C_ADC_RNCR ( 0xFFFD8114 ) /* (PDC_ADC) Receive Next Counter Register */ +#define AT91C_ADC_TCR ( 0xFFFD810C ) /* (PDC_ADC) Transmit Counter Register */ +#define AT91C_ADC_RCR ( 0xFFFD8104 ) /* (PDC_ADC) Receive Counter Register */ +/* ========== Register definition for ADC peripheral ========== */ +#define AT91C_ADC_IMR ( 0xFFFD802C ) /* (ADC) ADC Interrupt Mask Register */ +#define AT91C_ADC_CDR4 ( 0xFFFD8040 ) /* (ADC) ADC Channel Data Register 4 */ +#define AT91C_ADC_CDR2 ( 0xFFFD8038 ) /* (ADC) ADC Channel Data Register 2 */ +#define AT91C_ADC_CDR0 ( 0xFFFD8030 ) /* (ADC) ADC Channel Data Register 0 */ +#define AT91C_ADC_CDR7 ( 0xFFFD804C ) /* (ADC) ADC Channel Data Register 7 */ +#define AT91C_ADC_CDR1 ( 0xFFFD8034 ) /* (ADC) ADC Channel Data Register 1 */ +#define AT91C_ADC_CDR3 ( 0xFFFD803C ) /* (ADC) ADC Channel Data Register 3 */ +#define AT91C_ADC_CDR5 ( 0xFFFD8044 ) /* (ADC) ADC Channel Data Register 5 */ +#define AT91C_ADC_MR ( 0xFFFD8004 ) /* (ADC) ADC Mode Register */ +#define AT91C_ADC_CDR6 ( 0xFFFD8048 ) /* (ADC) ADC Channel Data Register 6 */ +#define AT91C_ADC_CR ( 0xFFFD8000 ) /* (ADC) ADC Control Register */ +#define AT91C_ADC_CHER ( 0xFFFD8010 ) /* (ADC) ADC Channel Enable Register */ +#define AT91C_ADC_CHSR ( 0xFFFD8018 ) /* (ADC) ADC Channel Status Register */ +#define AT91C_ADC_IER ( 0xFFFD8024 ) /* (ADC) ADC Interrupt Enable Register */ +#define AT91C_ADC_SR ( 0xFFFD801C ) /* (ADC) ADC Status Register */ +#define AT91C_ADC_CHDR ( 0xFFFD8014 ) /* (ADC) ADC Channel Disable Register */ +#define AT91C_ADC_IDR ( 0xFFFD8028 ) /* (ADC) ADC Interrupt Disable Register */ +#define AT91C_ADC_LCDR ( 0xFFFD8020 ) /* (ADC) ADC Last Converted Data Register */ +/* ========== Register definition for PDC_SSC peripheral ========== */ +#define AT91C_SSC_PTCR ( 0xFFFD4120 ) /* (PDC_SSC) PDC Transfer Control Register */ +#define AT91C_SSC_TNPR ( 0xFFFD4118 ) /* (PDC_SSC) Transmit Next Pointer Register */ +#define AT91C_SSC_RNPR ( 0xFFFD4110 ) /* (PDC_SSC) Receive Next Pointer Register */ +#define AT91C_SSC_TPR ( 0xFFFD4108 ) /* (PDC_SSC) Transmit Pointer Register */ +#define AT91C_SSC_RPR ( 0xFFFD4100 ) /* (PDC_SSC) Receive Pointer Register */ +#define AT91C_SSC_PTSR ( 0xFFFD4124 ) /* (PDC_SSC) PDC Transfer Status Register */ +#define AT91C_SSC_TNCR ( 0xFFFD411C ) /* (PDC_SSC) Transmit Next Counter Register */ +#define AT91C_SSC_RNCR ( 0xFFFD4114 ) /* (PDC_SSC) Receive Next Counter Register */ +#define AT91C_SSC_TCR ( 0xFFFD410C ) /* (PDC_SSC) Transmit Counter Register */ +#define AT91C_SSC_RCR ( 0xFFFD4104 ) /* (PDC_SSC) Receive Counter Register */ +/* ========== Register definition for SSC peripheral ========== */ +#define AT91C_SSC_RFMR ( 0xFFFD4014 ) /* (SSC) Receive Frame Mode Register */ +#define AT91C_SSC_CMR ( 0xFFFD4004 ) /* (SSC) Clock Mode Register */ +#define AT91C_SSC_IDR ( 0xFFFD4048 ) /* (SSC) Interrupt Disable Register */ +#define AT91C_SSC_SR ( 0xFFFD4040 ) /* (SSC) Status Register */ +#define AT91C_SSC_RC0R ( 0xFFFD4038 ) /* (SSC) Receive Compare 0 Register */ +#define AT91C_SSC_RSHR ( 0xFFFD4030 ) /* (SSC) Receive Sync Holding Register */ +#define AT91C_SSC_RHR ( 0xFFFD4020 ) /* (SSC) Receive Holding Register */ +#define AT91C_SSC_TCMR ( 0xFFFD4018 ) /* (SSC) Transmit Clock Mode Register */ +#define AT91C_SSC_RCMR ( 0xFFFD4010 ) /* (SSC) Receive Clock ModeRegister */ +#define AT91C_SSC_CR ( 0xFFFD4000 ) /* (SSC) Control Register */ +#define AT91C_SSC_IMR ( 0xFFFD404C ) /* (SSC) Interrupt Mask Register */ +#define AT91C_SSC_IER ( 0xFFFD4044 ) /* (SSC) Interrupt Enable Register */ +#define AT91C_SSC_RC1R ( 0xFFFD403C ) /* (SSC) Receive Compare 1 Register */ +#define AT91C_SSC_TSHR ( 0xFFFD4034 ) /* (SSC) Transmit Sync Holding Register */ +#define AT91C_SSC_THR ( 0xFFFD4024 ) /* (SSC) Transmit Holding Register */ +#define AT91C_SSC_TFMR ( 0xFFFD401C ) /* (SSC) Transmit Frame Mode Register */ +/* ========== Register definition for PDC_US1 peripheral ========== */ +#define AT91C_US1_PTSR ( 0xFFFC4124 ) /* (PDC_US1) PDC Transfer Status Register */ +#define AT91C_US1_TNCR ( 0xFFFC411C ) /* (PDC_US1) Transmit Next Counter Register */ +#define AT91C_US1_RNCR ( 0xFFFC4114 ) /* (PDC_US1) Receive Next Counter Register */ +#define AT91C_US1_TCR ( 0xFFFC410C ) /* (PDC_US1) Transmit Counter Register */ +#define AT91C_US1_RCR ( 0xFFFC4104 ) /* (PDC_US1) Receive Counter Register */ +#define AT91C_US1_PTCR ( 0xFFFC4120 ) /* (PDC_US1) PDC Transfer Control Register */ +#define AT91C_US1_TNPR ( 0xFFFC4118 ) /* (PDC_US1) Transmit Next Pointer Register */ +#define AT91C_US1_RNPR ( 0xFFFC4110 ) /* (PDC_US1) Receive Next Pointer Register */ +#define AT91C_US1_TPR ( 0xFFFC4108 ) /* (PDC_US1) Transmit Pointer Register */ +#define AT91C_US1_RPR ( 0xFFFC4100 ) /* (PDC_US1) Receive Pointer Register */ +/* ========== Register definition for US1 peripheral ========== */ +#define AT91C_US1_XXR ( 0xFFFC4048 ) /* (US1) XON_XOFF Register */ +#define AT91C_US1_RHR ( 0xFFFC4018 ) /* (US1) Receiver Holding Register */ +#define AT91C_US1_IMR ( 0xFFFC4010 ) /* (US1) Interrupt Mask Register */ +#define AT91C_US1_IER ( 0xFFFC4008 ) /* (US1) Interrupt Enable Register */ +#define AT91C_US1_CR ( 0xFFFC4000 ) /* (US1) Control Register */ +#define AT91C_US1_RTOR ( 0xFFFC4024 ) /* (US1) Receiver Time-out Register */ +#define AT91C_US1_THR ( 0xFFFC401C ) /* (US1) Transmitter Holding Register */ +#define AT91C_US1_CSR ( 0xFFFC4014 ) /* (US1) Channel Status Register */ +#define AT91C_US1_IDR ( 0xFFFC400C ) /* (US1) Interrupt Disable Register */ +#define AT91C_US1_FIDI ( 0xFFFC4040 ) /* (US1) FI_DI_Ratio Register */ +#define AT91C_US1_BRGR ( 0xFFFC4020 ) /* (US1) Baud Rate Generator Register */ +#define AT91C_US1_TTGR ( 0xFFFC4028 ) /* (US1) Transmitter Time-guard Register */ +#define AT91C_US1_IF ( 0xFFFC404C ) /* (US1) IRDA_FILTER Register */ +#define AT91C_US1_NER ( 0xFFFC4044 ) /* (US1) Nb Errors Register */ +#define AT91C_US1_MR ( 0xFFFC4004 ) /* (US1) Mode Register */ +/* ========== Register definition for PDC_US0 peripheral ========== */ +#define AT91C_US0_PTCR ( 0xFFFC0120 ) /* (PDC_US0) PDC Transfer Control Register */ +#define AT91C_US0_TNPR ( 0xFFFC0118 ) /* (PDC_US0) Transmit Next Pointer Register */ +#define AT91C_US0_RNPR ( 0xFFFC0110 ) /* (PDC_US0) Receive Next Pointer Register */ +#define AT91C_US0_TPR ( 0xFFFC0108 ) /* (PDC_US0) Transmit Pointer Register */ +#define AT91C_US0_RPR ( 0xFFFC0100 ) /* (PDC_US0) Receive Pointer Register */ +#define AT91C_US0_PTSR ( 0xFFFC0124 ) /* (PDC_US0) PDC Transfer Status Register */ +#define AT91C_US0_TNCR ( 0xFFFC011C ) /* (PDC_US0) Transmit Next Counter Register */ +#define AT91C_US0_RNCR ( 0xFFFC0114 ) /* (PDC_US0) Receive Next Counter Register */ +#define AT91C_US0_TCR ( 0xFFFC010C ) /* (PDC_US0) Transmit Counter Register */ +#define AT91C_US0_RCR ( 0xFFFC0104 ) /* (PDC_US0) Receive Counter Register */ +/* ========== Register definition for US0 peripheral ========== */ +#define AT91C_US0_TTGR ( 0xFFFC0028 ) /* (US0) Transmitter Time-guard Register */ +#define AT91C_US0_BRGR ( 0xFFFC0020 ) /* (US0) Baud Rate Generator Register */ +#define AT91C_US0_RHR ( 0xFFFC0018 ) /* (US0) Receiver Holding Register */ +#define AT91C_US0_IMR ( 0xFFFC0010 ) /* (US0) Interrupt Mask Register */ +#define AT91C_US0_NER ( 0xFFFC0044 ) /* (US0) Nb Errors Register */ +#define AT91C_US0_RTOR ( 0xFFFC0024 ) /* (US0) Receiver Time-out Register */ +#define AT91C_US0_XXR ( 0xFFFC0048 ) /* (US0) XON_XOFF Register */ +#define AT91C_US0_FIDI ( 0xFFFC0040 ) /* (US0) FI_DI_Ratio Register */ +#define AT91C_US0_CR ( 0xFFFC0000 ) /* (US0) Control Register */ +#define AT91C_US0_IER ( 0xFFFC0008 ) /* (US0) Interrupt Enable Register */ +#define AT91C_US0_IF ( 0xFFFC004C ) /* (US0) IRDA_FILTER Register */ +#define AT91C_US0_MR ( 0xFFFC0004 ) /* (US0) Mode Register */ +#define AT91C_US0_IDR ( 0xFFFC000C ) /* (US0) Interrupt Disable Register */ +#define AT91C_US0_CSR ( 0xFFFC0014 ) /* (US0) Channel Status Register */ +#define AT91C_US0_THR ( 0xFFFC001C ) /* (US0) Transmitter Holding Register */ +/* ========== Register definition for TWI peripheral ========== */ +#define AT91C_TWI_RHR ( 0xFFFB8030 ) /* (TWI) Receive Holding Register */ +#define AT91C_TWI_IDR ( 0xFFFB8028 ) /* (TWI) Interrupt Disable Register */ +#define AT91C_TWI_SR ( 0xFFFB8020 ) /* (TWI) Status Register */ +#define AT91C_TWI_CWGR ( 0xFFFB8010 ) /* (TWI) Clock Waveform Generator Register */ +#define AT91C_TWI_SMR ( 0xFFFB8008 ) /* (TWI) Slave Mode Register */ +#define AT91C_TWI_CR ( 0xFFFB8000 ) /* (TWI) Control Register */ +#define AT91C_TWI_THR ( 0xFFFB8034 ) /* (TWI) Transmit Holding Register */ +#define AT91C_TWI_IMR ( 0xFFFB802C ) /* (TWI) Interrupt Mask Register */ +#define AT91C_TWI_IER ( 0xFFFB8024 ) /* (TWI) Interrupt Enable Register */ +#define AT91C_TWI_IADR ( 0xFFFB800C ) /* (TWI) Internal Address Register */ +#define AT91C_TWI_MMR ( 0xFFFB8004 ) /* (TWI) Master Mode Register */ +/* ========== Register definition for TC2 peripheral ========== */ +#define AT91C_TC2_IMR ( 0xFFFA00AC ) /* (TC2) Interrupt Mask Register */ +#define AT91C_TC2_IER ( 0xFFFA00A4 ) /* (TC2) Interrupt Enable Register */ +#define AT91C_TC2_RC ( 0xFFFA009C ) /* (TC2) Register C */ +#define AT91C_TC2_RA ( 0xFFFA0094 ) /* (TC2) Register A */ +#define AT91C_TC2_CMR ( 0xFFFA0084 ) /* (TC2) Channel Mode Register (Capture Mode / Waveform Mode) */ +#define AT91C_TC2_IDR ( 0xFFFA00A8 ) /* (TC2) Interrupt Disable Register */ +#define AT91C_TC2_SR ( 0xFFFA00A0 ) /* (TC2) Status Register */ +#define AT91C_TC2_RB ( 0xFFFA0098 ) /* (TC2) Register B */ +#define AT91C_TC2_CV ( 0xFFFA0090 ) /* (TC2) Counter Value */ +#define AT91C_TC2_CCR ( 0xFFFA0080 ) /* (TC2) Channel Control Register */ +/* ========== Register definition for TC1 peripheral ========== */ +#define AT91C_TC1_IMR ( 0xFFFA006C ) /* (TC1) Interrupt Mask Register */ +#define AT91C_TC1_IER ( 0xFFFA0064 ) /* (TC1) Interrupt Enable Register */ +#define AT91C_TC1_RC ( 0xFFFA005C ) /* (TC1) Register C */ +#define AT91C_TC1_RA ( 0xFFFA0054 ) /* (TC1) Register A */ +#define AT91C_TC1_CMR ( 0xFFFA0044 ) /* (TC1) Channel Mode Register (Capture Mode / Waveform Mode) */ +#define AT91C_TC1_IDR ( 0xFFFA0068 ) /* (TC1) Interrupt Disable Register */ +#define AT91C_TC1_SR ( 0xFFFA0060 ) /* (TC1) Status Register */ +#define AT91C_TC1_RB ( 0xFFFA0058 ) /* (TC1) Register B */ +#define AT91C_TC1_CV ( 0xFFFA0050 ) /* (TC1) Counter Value */ +#define AT91C_TC1_CCR ( 0xFFFA0040 ) /* (TC1) Channel Control Register */ +/* ========== Register definition for TC0 peripheral ========== */ +#define AT91C_TC0_IMR ( 0xFFFA002C ) /* (TC0) Interrupt Mask Register */ +#define AT91C_TC0_IER ( 0xFFFA0024 ) /* (TC0) Interrupt Enable Register */ +#define AT91C_TC0_RC ( 0xFFFA001C ) /* (TC0) Register C */ +#define AT91C_TC0_RA ( 0xFFFA0014 ) /* (TC0) Register A */ +#define AT91C_TC0_CMR ( 0xFFFA0004 ) /* (TC0) Channel Mode Register (Capture Mode / Waveform Mode) */ +#define AT91C_TC0_IDR ( 0xFFFA0028 ) /* (TC0) Interrupt Disable Register */ +#define AT91C_TC0_SR ( 0xFFFA0020 ) /* (TC0) Status Register */ +#define AT91C_TC0_RB ( 0xFFFA0018 ) /* (TC0) Register B */ +#define AT91C_TC0_CV ( 0xFFFA0010 ) /* (TC0) Counter Value */ +#define AT91C_TC0_CCR ( 0xFFFA0000 ) /* (TC0) Channel Control Register */ +/* ========== Register definition for TCB peripheral ========== */ +#define AT91C_TCB_BMR ( 0xFFFA00C4 ) /* (TCB) TC Block Mode Register */ +#define AT91C_TCB_BCR ( 0xFFFA00C0 ) /* (TCB) TC Block Control Register */ +/* ========== Register definition for PWMC_CH3 peripheral ========== */ +#define AT91C_CH3_CUPDR ( 0xFFFCC270 ) /* (PWMC_CH3) Channel Update Register */ +#define AT91C_CH3_CPRDR ( 0xFFFCC268 ) /* (PWMC_CH3) Channel Period Register */ +#define AT91C_CH3_CMR ( 0xFFFCC260 ) /* (PWMC_CH3) Channel Mode Register */ +#define AT91C_CH3_Reserved ( 0xFFFCC274 ) /* (PWMC_CH3) Reserved */ +#define AT91C_CH3_CCNTR ( 0xFFFCC26C ) /* (PWMC_CH3) Channel Counter Register */ +#define AT91C_CH3_CDTYR ( 0xFFFCC264 ) /* (PWMC_CH3) Channel Duty Cycle Register */ +/* ========== Register definition for PWMC_CH2 peripheral ========== */ +#define AT91C_CH2_CUPDR ( 0xFFFCC250 ) /* (PWMC_CH2) Channel Update Register */ +#define AT91C_CH2_CPRDR ( 0xFFFCC248 ) /* (PWMC_CH2) Channel Period Register */ +#define AT91C_CH2_CMR ( 0xFFFCC240 ) /* (PWMC_CH2) Channel Mode Register */ +#define AT91C_CH2_Reserved ( 0xFFFCC254 ) /* (PWMC_CH2) Reserved */ +#define AT91C_CH2_CCNTR ( 0xFFFCC24C ) /* (PWMC_CH2) Channel Counter Register */ +#define AT91C_CH2_CDTYR ( 0xFFFCC244 ) /* (PWMC_CH2) Channel Duty Cycle Register */ +/* ========== Register definition for PWMC_CH1 peripheral ========== */ +#define AT91C_CH1_CUPDR ( 0xFFFCC230 ) /* (PWMC_CH1) Channel Update Register */ +#define AT91C_CH1_CPRDR ( 0xFFFCC228 ) /* (PWMC_CH1) Channel Period Register */ +#define AT91C_CH1_CMR ( 0xFFFCC220 ) /* (PWMC_CH1) Channel Mode Register */ +#define AT91C_CH1_Reserved ( 0xFFFCC234 ) /* (PWMC_CH1) Reserved */ +#define AT91C_CH1_CCNTR ( 0xFFFCC22C ) /* (PWMC_CH1) Channel Counter Register */ +#define AT91C_CH1_CDTYR ( 0xFFFCC224 ) /* (PWMC_CH1) Channel Duty Cycle Register */ +/* ========== Register definition for PWMC_CH0 peripheral ========== */ +#define AT91C_CH0_CUPDR ( 0xFFFCC210 ) /* (PWMC_CH0) Channel Update Register */ +#define AT91C_CH0_CPRDR ( 0xFFFCC208 ) /* (PWMC_CH0) Channel Period Register */ +#define AT91C_CH0_CMR ( 0xFFFCC200 ) /* (PWMC_CH0) Channel Mode Register */ +#define AT91C_CH0_Reserved ( 0xFFFCC214 ) /* (PWMC_CH0) Reserved */ +#define AT91C_CH0_CCNTR ( 0xFFFCC20C ) /* (PWMC_CH0) Channel Counter Register */ +#define AT91C_CH0_CDTYR ( 0xFFFCC204 ) /* (PWMC_CH0) Channel Duty Cycle Register */ +/* ========== Register definition for PWMC peripheral ========== */ +#define AT91C_PWMC_VR ( 0xFFFCC0FC ) /* (PWMC) PWMC Version Register */ +#define AT91C_PWMC_ISR ( 0xFFFCC01C ) /* (PWMC) PWMC Interrupt Status Register */ +#define AT91C_PWMC_IDR ( 0xFFFCC014 ) /* (PWMC) PWMC Interrupt Disable Register */ +#define AT91C_PWMC_SR ( 0xFFFCC00C ) /* (PWMC) PWMC Status Register */ +#define AT91C_PWMC_ENA ( 0xFFFCC004 ) /* (PWMC) PWMC Enable Register */ +#define AT91C_PWMC_IMR ( 0xFFFCC018 ) /* (PWMC) PWMC Interrupt Mask Register */ +#define AT91C_PWMC_MR ( 0xFFFCC000 ) /* (PWMC) PWMC Mode Register */ +#define AT91C_PWMC_DIS ( 0xFFFCC008 ) /* (PWMC) PWMC Disable Register */ +#define AT91C_PWMC_IER ( 0xFFFCC010 ) /* (PWMC) PWMC Interrupt Enable Register */ +/* ========== Register definition for UDP peripheral ========== */ +#define AT91C_UDP_ISR ( 0xFFFB001C ) /* (UDP) Interrupt Status Register */ +#define AT91C_UDP_IDR ( 0xFFFB0014 ) /* (UDP) Interrupt Disable Register */ +#define AT91C_UDP_GLBSTATE ( 0xFFFB0004 ) /* (UDP) Global State Register */ +#define AT91C_UDP_FDR ( 0xFFFB0050 ) /* (UDP) Endpoint FIFO Data Register */ +#define AT91C_UDP_CSR ( 0xFFFB0030 ) /* (UDP) Endpoint Control and Status Register */ +#define AT91C_UDP_RSTEP ( 0xFFFB0028 ) /* (UDP) Reset Endpoint Register */ +#define AT91C_UDP_ICR ( 0xFFFB0020 ) /* (UDP) Interrupt Clear Register */ +#define AT91C_UDP_IMR ( 0xFFFB0018 ) /* (UDP) Interrupt Mask Register */ +#define AT91C_UDP_IER ( 0xFFFB0010 ) /* (UDP) Interrupt Enable Register */ +#define AT91C_UDP_FADDR ( 0xFFFB0008 ) /* (UDP) Function Address Register */ +#define AT91C_UDP_NUM ( 0xFFFB0000 ) /* (UDP) Frame Number Register */ -// ***************************************************************************** -// PIO DEFINITIONS FOR AT91SAM7S64 -// ***************************************************************************** -#define AT91C_PIO_PA0 (1 << 0) // Pin Controlled by PA0 -#define AT91C_PA0_PWM0 (AT91C_PIO_PA0) // PWM Channel 0 -#define AT91C_PA0_TIOA0 (AT91C_PIO_PA0) // Timer Counter 0 Multipurpose Timer I/O Pin A -#define AT91C_PIO_PA1 (1 << 1) // Pin Controlled by PA1 -#define AT91C_PA1_PWM1 (AT91C_PIO_PA1) // PWM Channel 1 -#define AT91C_PA1_TIOB0 (AT91C_PIO_PA1) // Timer Counter 0 Multipurpose Timer I/O Pin B -#define AT91C_PIO_PA10 (1 << 10) // Pin Controlled by PA10 -#define AT91C_PA10_DTXD (AT91C_PIO_PA10) // DBGU Debug Transmit Data -#define AT91C_PA10_NPCS2 (AT91C_PIO_PA10) // SPI Peripheral Chip Select 2 -#define AT91C_PIO_PA11 (1 << 11) // Pin Controlled by PA11 -#define AT91C_PA11_NPCS0 (AT91C_PIO_PA11) // SPI Peripheral Chip Select 0 -#define AT91C_PA11_PWM0 (AT91C_PIO_PA11) // PWM Channel 0 -#define AT91C_PIO_PA12 (1 << 12) // Pin Controlled by PA12 -#define AT91C_PA12_MISO (AT91C_PIO_PA12) // SPI Master In Slave -#define AT91C_PA12_PWM1 (AT91C_PIO_PA12) // PWM Channel 1 -#define AT91C_PIO_PA13 (1 << 13) // Pin Controlled by PA13 -#define AT91C_PA13_MOSI (AT91C_PIO_PA13) // SPI Master Out Slave -#define AT91C_PA13_PWM2 (AT91C_PIO_PA13) // PWM Channel 2 -#define AT91C_PIO_PA14 (1 << 14) // Pin Controlled by PA14 -#define AT91C_PA14_SPCK (AT91C_PIO_PA14) // SPI Serial Clock -#define AT91C_PA14_PWM3 (AT91C_PIO_PA14) // PWM Channel 3 -#define AT91C_PIO_PA15 (1 << 15) // Pin Controlled by PA15 -#define AT91C_PA15_TF (AT91C_PIO_PA15) // SSC Transmit Frame Sync -#define AT91C_PA15_TIOA1 (AT91C_PIO_PA15) // Timer Counter 1 Multipurpose Timer I/O Pin A -#define AT91C_PIO_PA16 (1 << 16) // Pin Controlled by PA16 -#define AT91C_PA16_TK (AT91C_PIO_PA16) // SSC Transmit Clock -#define AT91C_PA16_TIOB1 (AT91C_PIO_PA16) // Timer Counter 1 Multipurpose Timer I/O Pin B -#define AT91C_PIO_PA17 (1 << 17) // Pin Controlled by PA17 -#define AT91C_PA17_TD (AT91C_PIO_PA17) // SSC Transmit data -#define AT91C_PA17_PCK1 (AT91C_PIO_PA17) // PMC Programmable Clock Output 1 -#define AT91C_PIO_PA18 (1 << 18) // Pin Controlled by PA18 -#define AT91C_PA18_RD (AT91C_PIO_PA18) // SSC Receive Data -#define AT91C_PA18_PCK2 (AT91C_PIO_PA18) // PMC Programmable Clock Output 2 -#define AT91C_PIO_PA19 (1 << 19) // Pin Controlled by PA19 -#define AT91C_PA19_RK (AT91C_PIO_PA19) // SSC Receive Clock -#define AT91C_PA19_FIQ (AT91C_PIO_PA19) // AIC Fast Interrupt Input -#define AT91C_PIO_PA2 (1 << 2) // Pin Controlled by PA2 -#define AT91C_PA2_PWM2 (AT91C_PIO_PA2) // PWM Channel 2 -#define AT91C_PA2_SCK0 (AT91C_PIO_PA2) // USART 0 Serial Clock -#define AT91C_PIO_PA20 (1 << 20) // Pin Controlled by PA20 -#define AT91C_PA20_RF (AT91C_PIO_PA20) // SSC Receive Frame Sync -#define AT91C_PA20_IRQ0 (AT91C_PIO_PA20) // External Interrupt 0 -#define AT91C_PIO_PA21 (1 << 21) // Pin Controlled by PA21 -#define AT91C_PA21_RXD1 (AT91C_PIO_PA21) // USART 1 Receive Data -#define AT91C_PA21_PCK1 (AT91C_PIO_PA21) // PMC Programmable Clock Output 1 -#define AT91C_PIO_PA22 (1 << 22) // Pin Controlled by PA22 -#define AT91C_PA22_TXD1 (AT91C_PIO_PA22) // USART 1 Transmit Data -#define AT91C_PA22_NPCS3 (AT91C_PIO_PA22) // SPI Peripheral Chip Select 3 -#define AT91C_PIO_PA23 (1 << 23) // Pin Controlled by PA23 -#define AT91C_PA23_SCK1 (AT91C_PIO_PA23) // USART 1 Serial Clock -#define AT91C_PA23_PWM0 (AT91C_PIO_PA23) // PWM Channel 0 -#define AT91C_PIO_PA24 (1 << 24) // Pin Controlled by PA24 -#define AT91C_PA24_RTS1 (AT91C_PIO_PA24) // USART 1 Ready To Send -#define AT91C_PA24_PWM1 (AT91C_PIO_PA24) // PWM Channel 1 -#define AT91C_PIO_PA25 (1 << 25) // Pin Controlled by PA25 -#define AT91C_PA25_CTS1 (AT91C_PIO_PA25) // USART 1 Clear To Send -#define AT91C_PA25_PWM2 (AT91C_PIO_PA25) // PWM Channel 2 -#define AT91C_PIO_PA26 (1 << 26) // Pin Controlled by PA26 -#define AT91C_PA26_DCD1 (AT91C_PIO_PA26) // USART 1 Data Carrier Detect -#define AT91C_PA26_TIOA2 (AT91C_PIO_PA26) // Timer Counter 2 Multipurpose Timer I/O Pin A -#define AT91C_PIO_PA27 (1 << 27) // Pin Controlled by PA27 -#define AT91C_PA27_DTR1 (AT91C_PIO_PA27) // USART 1 Data Terminal ready -#define AT91C_PA27_TIOB2 (AT91C_PIO_PA27) // Timer Counter 2 Multipurpose Timer I/O Pin B -#define AT91C_PIO_PA28 (1 << 28) // Pin Controlled by PA28 -#define AT91C_PA28_DSR1 (AT91C_PIO_PA28) // USART 1 Data Set ready -#define AT91C_PA28_TCLK1 (AT91C_PIO_PA28) // Timer Counter 1 external clock input -#define AT91C_PIO_PA29 (1 << 29) // Pin Controlled by PA29 -#define AT91C_PA29_RI1 (AT91C_PIO_PA29) // USART 1 Ring Indicator -#define AT91C_PA29_TCLK2 (AT91C_PIO_PA29) // Timer Counter 2 external clock input -#define AT91C_PIO_PA3 (1 << 3) // Pin Controlled by PA3 -#define AT91C_PA3_TWD (AT91C_PIO_PA3) // TWI Two-wire Serial Data -#define AT91C_PA3_NPCS3 (AT91C_PIO_PA3) // SPI Peripheral Chip Select 3 -#define AT91C_PIO_PA30 (1 << 30) // Pin Controlled by PA30 -#define AT91C_PA30_IRQ1 (AT91C_PIO_PA30) // External Interrupt 1 -#define AT91C_PA30_NPCS2 (AT91C_PIO_PA30) // SPI Peripheral Chip Select 2 -#define AT91C_PIO_PA31 (1 << 31) // Pin Controlled by PA31 -#define AT91C_PA31_NPCS1 (AT91C_PIO_PA31) // SPI Peripheral Chip Select 1 -#define AT91C_PA31_PCK2 (AT91C_PIO_PA31) // PMC Programmable Clock Output 2 -#define AT91C_PIO_PA4 (1 << 4) // Pin Controlled by PA4 -#define AT91C_PA4_TWCK (AT91C_PIO_PA4) // TWI Two-wire Serial Clock -#define AT91C_PA4_TCLK0 (AT91C_PIO_PA4) // Timer Counter 0 external clock input -#define AT91C_PIO_PA5 (1 << 5) // Pin Controlled by PA5 -#define AT91C_PA5_RXD0 (AT91C_PIO_PA5) // USART 0 Receive Data -#define AT91C_PA5_NPCS3 (AT91C_PIO_PA5) // SPI Peripheral Chip Select 3 -#define AT91C_PIO_PA6 (1 << 6) // Pin Controlled by PA6 -#define AT91C_PA6_TXD0 (AT91C_PIO_PA6) // USART 0 Transmit Data -#define AT91C_PA6_PCK0 (AT91C_PIO_PA6) // PMC Programmable Clock Output 0 -#define AT91C_PIO_PA7 (1 << 7) // Pin Controlled by PA7 -#define AT91C_PA7_RTS0 (AT91C_PIO_PA7) // USART 0 Ready To Send -#define AT91C_PA7_PWM3 (AT91C_PIO_PA7) // PWM Channel 3 -#define AT91C_PIO_PA8 (1 << 8) // Pin Controlled by PA8 -#define AT91C_PA8_CTS0 (AT91C_PIO_PA8) // USART 0 Clear To Send -#define AT91C_PA8_ADTRG (AT91C_PIO_PA8) // ADC External Trigger -#define AT91C_PIO_PA9 (1 << 9) // Pin Controlled by PA9 -#define AT91C_PA9_DRXD (AT91C_PIO_PA9) // DBGU Debug Receive Data -#define AT91C_PA9_NPCS1 (AT91C_PIO_PA9) // SPI Peripheral Chip Select 1 +/* ***************************************************************************** */ +/* PIO DEFINITIONS FOR AT91SAM7S64 */ +/* ***************************************************************************** */ +#define AT91C_PIO_PA0 ( 1 << 0 ) /* Pin Controlled by PA0 */ +#define AT91C_PA0_PWM0 ( AT91C_PIO_PA0 ) /* PWM Channel 0 */ +#define AT91C_PA0_TIOA0 ( AT91C_PIO_PA0 ) /* Timer Counter 0 Multipurpose Timer I/O Pin A */ +#define AT91C_PIO_PA1 ( 1 << 1 ) /* Pin Controlled by PA1 */ +#define AT91C_PA1_PWM1 ( AT91C_PIO_PA1 ) /* PWM Channel 1 */ +#define AT91C_PA1_TIOB0 ( AT91C_PIO_PA1 ) /* Timer Counter 0 Multipurpose Timer I/O Pin B */ +#define AT91C_PIO_PA10 ( 1 << 10 ) /* Pin Controlled by PA10 */ +#define AT91C_PA10_DTXD ( AT91C_PIO_PA10 ) /* DBGU Debug Transmit Data */ +#define AT91C_PA10_NPCS2 ( AT91C_PIO_PA10 ) /* SPI Peripheral Chip Select 2 */ +#define AT91C_PIO_PA11 ( 1 << 11 ) /* Pin Controlled by PA11 */ +#define AT91C_PA11_NPCS0 ( AT91C_PIO_PA11 ) /* SPI Peripheral Chip Select 0 */ +#define AT91C_PA11_PWM0 ( AT91C_PIO_PA11 ) /* PWM Channel 0 */ +#define AT91C_PIO_PA12 ( 1 << 12 ) /* Pin Controlled by PA12 */ +#define AT91C_PA12_MISO ( AT91C_PIO_PA12 ) /* SPI Master In Slave */ +#define AT91C_PA12_PWM1 ( AT91C_PIO_PA12 ) /* PWM Channel 1 */ +#define AT91C_PIO_PA13 ( 1 << 13 ) /* Pin Controlled by PA13 */ +#define AT91C_PA13_MOSI ( AT91C_PIO_PA13 ) /* SPI Master Out Slave */ +#define AT91C_PA13_PWM2 ( AT91C_PIO_PA13 ) /* PWM Channel 2 */ +#define AT91C_PIO_PA14 ( 1 << 14 ) /* Pin Controlled by PA14 */ +#define AT91C_PA14_SPCK ( AT91C_PIO_PA14 ) /* SPI Serial Clock */ +#define AT91C_PA14_PWM3 ( AT91C_PIO_PA14 ) /* PWM Channel 3 */ +#define AT91C_PIO_PA15 ( 1 << 15 ) /* Pin Controlled by PA15 */ +#define AT91C_PA15_TF ( AT91C_PIO_PA15 ) /* SSC Transmit Frame Sync */ +#define AT91C_PA15_TIOA1 ( AT91C_PIO_PA15 ) /* Timer Counter 1 Multipurpose Timer I/O Pin A */ +#define AT91C_PIO_PA16 ( 1 << 16 ) /* Pin Controlled by PA16 */ +#define AT91C_PA16_TK ( AT91C_PIO_PA16 ) /* SSC Transmit Clock */ +#define AT91C_PA16_TIOB1 ( AT91C_PIO_PA16 ) /* Timer Counter 1 Multipurpose Timer I/O Pin B */ +#define AT91C_PIO_PA17 ( 1 << 17 ) /* Pin Controlled by PA17 */ +#define AT91C_PA17_TD ( AT91C_PIO_PA17 ) /* SSC Transmit data */ +#define AT91C_PA17_PCK1 ( AT91C_PIO_PA17 ) /* PMC Programmable Clock Output 1 */ +#define AT91C_PIO_PA18 ( 1 << 18 ) /* Pin Controlled by PA18 */ +#define AT91C_PA18_RD ( AT91C_PIO_PA18 ) /* SSC Receive Data */ +#define AT91C_PA18_PCK2 ( AT91C_PIO_PA18 ) /* PMC Programmable Clock Output 2 */ +#define AT91C_PIO_PA19 ( 1 << 19 ) /* Pin Controlled by PA19 */ +#define AT91C_PA19_RK ( AT91C_PIO_PA19 ) /* SSC Receive Clock */ +#define AT91C_PA19_FIQ ( AT91C_PIO_PA19 ) /* AIC Fast Interrupt Input */ +#define AT91C_PIO_PA2 ( 1 << 2 ) /* Pin Controlled by PA2 */ +#define AT91C_PA2_PWM2 ( AT91C_PIO_PA2 ) /* PWM Channel 2 */ +#define AT91C_PA2_SCK0 ( AT91C_PIO_PA2 ) /* USART 0 Serial Clock */ +#define AT91C_PIO_PA20 ( 1 << 20 ) /* Pin Controlled by PA20 */ +#define AT91C_PA20_RF ( AT91C_PIO_PA20 ) /* SSC Receive Frame Sync */ +#define AT91C_PA20_IRQ0 ( AT91C_PIO_PA20 ) /* External Interrupt 0 */ +#define AT91C_PIO_PA21 ( 1 << 21 ) /* Pin Controlled by PA21 */ +#define AT91C_PA21_RXD1 ( AT91C_PIO_PA21 ) /* USART 1 Receive Data */ +#define AT91C_PA21_PCK1 ( AT91C_PIO_PA21 ) /* PMC Programmable Clock Output 1 */ +#define AT91C_PIO_PA22 ( 1 << 22 ) /* Pin Controlled by PA22 */ +#define AT91C_PA22_TXD1 ( AT91C_PIO_PA22 ) /* USART 1 Transmit Data */ +#define AT91C_PA22_NPCS3 ( AT91C_PIO_PA22 ) /* SPI Peripheral Chip Select 3 */ +#define AT91C_PIO_PA23 ( 1 << 23 ) /* Pin Controlled by PA23 */ +#define AT91C_PA23_SCK1 ( AT91C_PIO_PA23 ) /* USART 1 Serial Clock */ +#define AT91C_PA23_PWM0 ( AT91C_PIO_PA23 ) /* PWM Channel 0 */ +#define AT91C_PIO_PA24 ( 1 << 24 ) /* Pin Controlled by PA24 */ +#define AT91C_PA24_RTS1 ( AT91C_PIO_PA24 ) /* USART 1 Ready To Send */ +#define AT91C_PA24_PWM1 ( AT91C_PIO_PA24 ) /* PWM Channel 1 */ +#define AT91C_PIO_PA25 ( 1 << 25 ) /* Pin Controlled by PA25 */ +#define AT91C_PA25_CTS1 ( AT91C_PIO_PA25 ) /* USART 1 Clear To Send */ +#define AT91C_PA25_PWM2 ( AT91C_PIO_PA25 ) /* PWM Channel 2 */ +#define AT91C_PIO_PA26 ( 1 << 26 ) /* Pin Controlled by PA26 */ +#define AT91C_PA26_DCD1 ( AT91C_PIO_PA26 ) /* USART 1 Data Carrier Detect */ +#define AT91C_PA26_TIOA2 ( AT91C_PIO_PA26 ) /* Timer Counter 2 Multipurpose Timer I/O Pin A */ +#define AT91C_PIO_PA27 ( 1 << 27 ) /* Pin Controlled by PA27 */ +#define AT91C_PA27_DTR1 ( AT91C_PIO_PA27 ) /* USART 1 Data Terminal ready */ +#define AT91C_PA27_TIOB2 ( AT91C_PIO_PA27 ) /* Timer Counter 2 Multipurpose Timer I/O Pin B */ +#define AT91C_PIO_PA28 ( 1 << 28 ) /* Pin Controlled by PA28 */ +#define AT91C_PA28_DSR1 ( AT91C_PIO_PA28 ) /* USART 1 Data Set ready */ +#define AT91C_PA28_TCLK1 ( AT91C_PIO_PA28 ) /* Timer Counter 1 external clock input */ +#define AT91C_PIO_PA29 ( 1 << 29 ) /* Pin Controlled by PA29 */ +#define AT91C_PA29_RI1 ( AT91C_PIO_PA29 ) /* USART 1 Ring Indicator */ +#define AT91C_PA29_TCLK2 ( AT91C_PIO_PA29 ) /* Timer Counter 2 external clock input */ +#define AT91C_PIO_PA3 ( 1 << 3 ) /* Pin Controlled by PA3 */ +#define AT91C_PA3_TWD ( AT91C_PIO_PA3 ) /* TWI Two-wire Serial Data */ +#define AT91C_PA3_NPCS3 ( AT91C_PIO_PA3 ) /* SPI Peripheral Chip Select 3 */ +#define AT91C_PIO_PA30 ( 1 << 30 ) /* Pin Controlled by PA30 */ +#define AT91C_PA30_IRQ1 ( AT91C_PIO_PA30 ) /* External Interrupt 1 */ +#define AT91C_PA30_NPCS2 ( AT91C_PIO_PA30 ) /* SPI Peripheral Chip Select 2 */ +#define AT91C_PIO_PA31 ( 1 << 31 ) /* Pin Controlled by PA31 */ +#define AT91C_PA31_NPCS1 ( AT91C_PIO_PA31 ) /* SPI Peripheral Chip Select 1 */ +#define AT91C_PA31_PCK2 ( AT91C_PIO_PA31 ) /* PMC Programmable Clock Output 2 */ +#define AT91C_PIO_PA4 ( 1 << 4 ) /* Pin Controlled by PA4 */ +#define AT91C_PA4_TWCK ( AT91C_PIO_PA4 ) /* TWI Two-wire Serial Clock */ +#define AT91C_PA4_TCLK0 ( AT91C_PIO_PA4 ) /* Timer Counter 0 external clock input */ +#define AT91C_PIO_PA5 ( 1 << 5 ) /* Pin Controlled by PA5 */ +#define AT91C_PA5_RXD0 ( AT91C_PIO_PA5 ) /* USART 0 Receive Data */ +#define AT91C_PA5_NPCS3 ( AT91C_PIO_PA5 ) /* SPI Peripheral Chip Select 3 */ +#define AT91C_PIO_PA6 ( 1 << 6 ) /* Pin Controlled by PA6 */ +#define AT91C_PA6_TXD0 ( AT91C_PIO_PA6 ) /* USART 0 Transmit Data */ +#define AT91C_PA6_PCK0 ( AT91C_PIO_PA6 ) /* PMC Programmable Clock Output 0 */ +#define AT91C_PIO_PA7 ( 1 << 7 ) /* Pin Controlled by PA7 */ +#define AT91C_PA7_RTS0 ( AT91C_PIO_PA7 ) /* USART 0 Ready To Send */ +#define AT91C_PA7_PWM3 ( AT91C_PIO_PA7 ) /* PWM Channel 3 */ +#define AT91C_PIO_PA8 ( 1 << 8 ) /* Pin Controlled by PA8 */ +#define AT91C_PA8_CTS0 ( AT91C_PIO_PA8 ) /* USART 0 Clear To Send */ +#define AT91C_PA8_ADTRG ( AT91C_PIO_PA8 ) /* ADC External Trigger */ +#define AT91C_PIO_PA9 ( 1 << 9 ) /* Pin Controlled by PA9 */ +#define AT91C_PA9_DRXD ( AT91C_PIO_PA9 ) /* DBGU Debug Receive Data */ +#define AT91C_PA9_NPCS1 ( AT91C_PIO_PA9 ) /* SPI Peripheral Chip Select 1 */ -// ***************************************************************************** -// PERIPHERAL ID DEFINITIONS FOR AT91SAM7S64 -// ***************************************************************************** -#define AT91C_ID_FIQ ( 0) // Advanced Interrupt Controller (FIQ) -#define AT91C_ID_SYS ( 1) // System Peripheral -#define AT91C_ID_PIOA ( 2) // Parallel IO Controller -#define AT91C_ID_3_Reserved ( 3) // Reserved -#define AT91C_ID_ADC ( 4) // Analog-to-Digital Converter -#define AT91C_ID_SPI ( 5) // Serial Peripheral Interface -#define AT91C_ID_US0 ( 6) // USART 0 -#define AT91C_ID_US1 ( 7) // USART 1 -#define AT91C_ID_SSC ( 8) // Serial Synchronous Controller -#define AT91C_ID_TWI ( 9) // Two-Wire Interface -#define AT91C_ID_PWMC (10) // PWM Controller -#define AT91C_ID_UDP (11) // USB Device Port -#define AT91C_ID_TC0 (12) // Timer Counter 0 -#define AT91C_ID_TC1 (13) // Timer Counter 1 -#define AT91C_ID_TC2 (14) // Timer Counter 2 -#define AT91C_ID_15_Reserved (15) // Reserved -#define AT91C_ID_16_Reserved (16) // Reserved -#define AT91C_ID_17_Reserved (17) // Reserved -#define AT91C_ID_18_Reserved (18) // Reserved -#define AT91C_ID_19_Reserved (19) // Reserved -#define AT91C_ID_20_Reserved (20) // Reserved -#define AT91C_ID_21_Reserved (21) // Reserved -#define AT91C_ID_22_Reserved (22) // Reserved -#define AT91C_ID_23_Reserved (23) // Reserved -#define AT91C_ID_24_Reserved (24) // Reserved -#define AT91C_ID_25_Reserved (25) // Reserved -#define AT91C_ID_26_Reserved (26) // Reserved -#define AT91C_ID_27_Reserved (27) // Reserved -#define AT91C_ID_28_Reserved (28) // Reserved -#define AT91C_ID_29_Reserved (29) // Reserved -#define AT91C_ID_IRQ0 (30) // Advanced Interrupt Controller (IRQ0) -#define AT91C_ID_IRQ1 (31) // Advanced Interrupt Controller (IRQ1) +/* ***************************************************************************** */ +/* PERIPHERAL ID DEFINITIONS FOR AT91SAM7S64 */ +/* ***************************************************************************** */ +#define AT91C_ID_FIQ ( 0 ) /* Advanced Interrupt Controller (FIQ) */ +#define AT91C_ID_SYS ( 1 ) /* System Peripheral */ +#define AT91C_ID_PIOA ( 2 ) /* Parallel IO Controller */ +#define AT91C_ID_3_Reserved ( 3 ) /* Reserved */ +#define AT91C_ID_ADC ( 4 ) /* Analog-to-Digital Converter */ +#define AT91C_ID_SPI ( 5 ) /* Serial Peripheral Interface */ +#define AT91C_ID_US0 ( 6 ) /* USART 0 */ +#define AT91C_ID_US1 ( 7 ) /* USART 1 */ +#define AT91C_ID_SSC ( 8 ) /* Serial Synchronous Controller */ +#define AT91C_ID_TWI ( 9 ) /* Two-Wire Interface */ +#define AT91C_ID_PWMC ( 10 ) /* PWM Controller */ +#define AT91C_ID_UDP ( 11 ) /* USB Device Port */ +#define AT91C_ID_TC0 ( 12 ) /* Timer Counter 0 */ +#define AT91C_ID_TC1 ( 13 ) /* Timer Counter 1 */ +#define AT91C_ID_TC2 ( 14 ) /* Timer Counter 2 */ +#define AT91C_ID_15_Reserved ( 15 ) /* Reserved */ +#define AT91C_ID_16_Reserved ( 16 ) /* Reserved */ +#define AT91C_ID_17_Reserved ( 17 ) /* Reserved */ +#define AT91C_ID_18_Reserved ( 18 ) /* Reserved */ +#define AT91C_ID_19_Reserved ( 19 ) /* Reserved */ +#define AT91C_ID_20_Reserved ( 20 ) /* Reserved */ +#define AT91C_ID_21_Reserved ( 21 ) /* Reserved */ +#define AT91C_ID_22_Reserved ( 22 ) /* Reserved */ +#define AT91C_ID_23_Reserved ( 23 ) /* Reserved */ +#define AT91C_ID_24_Reserved ( 24 ) /* Reserved */ +#define AT91C_ID_25_Reserved ( 25 ) /* Reserved */ +#define AT91C_ID_26_Reserved ( 26 ) /* Reserved */ +#define AT91C_ID_27_Reserved ( 27 ) /* Reserved */ +#define AT91C_ID_28_Reserved ( 28 ) /* Reserved */ +#define AT91C_ID_29_Reserved ( 29 ) /* Reserved */ +#define AT91C_ID_IRQ0 ( 30 ) /* Advanced Interrupt Controller (IRQ0) */ +#define AT91C_ID_IRQ1 ( 31 ) /* Advanced Interrupt Controller (IRQ1) */ -// ***************************************************************************** -// BASE ADDRESS DEFINITIONS FOR AT91SAM7S64 -// ***************************************************************************** -#define AT91C_BASE_SYSC (0xFFFFF000) // (SYSC) Base Address -#define AT91C_BASE_AIC (0xFFFFF000) // (AIC) Base Address -#define AT91C_BASE_DBGU (0xFFFFF200) // (DBGU) Base Address -#define AT91C_BASE_PDC_DBGU (0xFFFFF300) // (PDC_DBGU) Base Address -#define AT91C_BASE_PIOA (0xFFFFF400) // (PIOA) Base Address -#define AT91C_BASE_CKGR (0xFFFFFC20) // (CKGR) Base Address -#define AT91C_BASE_PMC (0xFFFFFC00) // (PMC) Base Address -#define AT91C_BASE_RSTC (0xFFFFFD00) // (RSTC) Base Address -#define AT91C_BASE_RTTC (0xFFFFFD20) // (RTTC) Base Address -#define AT91C_BASE_PITC (0xFFFFFD30) // (PITC) Base Address -#define AT91C_BASE_WDTC (0xFFFFFD40) // (WDTC) Base Address -#define AT91C_BASE_MC (0xFFFFFF00) // (MC) Base Address -#define AT91C_BASE_PDC_SPI (0xFFFE0100) // (PDC_SPI) Base Address -#define AT91C_BASE_SPI (0xFFFE0000) // (SPI) Base Address -#define AT91C_BASE_PDC_ADC (0xFFFD8100) // (PDC_ADC) Base Address -#define AT91C_BASE_ADC (0xFFFD8000) // (ADC) Base Address -#define AT91C_BASE_PDC_SSC (0xFFFD4100) // (PDC_SSC) Base Address -#define AT91C_BASE_SSC (0xFFFD4000) // (SSC) Base Address -#define AT91C_BASE_PDC_US1 (0xFFFC4100) // (PDC_US1) Base Address -#define AT91C_BASE_US1 (0xFFFC4000) // (US1) Base Address -#define AT91C_BASE_PDC_US0 (0xFFFC0100) // (PDC_US0) Base Address -#define AT91C_BASE_US0 (0xFFFC0000) // (US0) Base Address -#define AT91C_BASE_TWI (0xFFFB8000) // (TWI) Base Address -#define AT91C_BASE_TC2 (0xFFFA0080) // (TC2) Base Address -#define AT91C_BASE_TC1 (0xFFFA0040) // (TC1) Base Address -#define AT91C_BASE_TC0 (0xFFFA0000) // (TC0) Base Address -#define AT91C_BASE_TCB (0xFFFA0000) // (TCB) Base Address -#define AT91C_BASE_PWMC_CH3 (0xFFFCC260) // (PWMC_CH3) Base Address -#define AT91C_BASE_PWMC_CH2 (0xFFFCC240) // (PWMC_CH2) Base Address -#define AT91C_BASE_PWMC_CH1 (0xFFFCC220) // (PWMC_CH1) Base Address -#define AT91C_BASE_PWMC_CH0 (0xFFFCC200) // (PWMC_CH0) Base Address -#define AT91C_BASE_PWMC (0xFFFCC000) // (PWMC) Base Address -#define AT91C_BASE_UDP (0xFFFB0000) // (UDP) Base Address +/* ***************************************************************************** */ +/* BASE ADDRESS DEFINITIONS FOR AT91SAM7S64 */ +/* ***************************************************************************** */ +#define AT91C_BASE_SYSC ( 0xFFFFF000 ) /* (SYSC) Base Address */ +#define AT91C_BASE_AIC ( 0xFFFFF000 ) /* (AIC) Base Address */ +#define AT91C_BASE_DBGU ( 0xFFFFF200 ) /* (DBGU) Base Address */ +#define AT91C_BASE_PDC_DBGU ( 0xFFFFF300 ) /* (PDC_DBGU) Base Address */ +#define AT91C_BASE_PIOA ( 0xFFFFF400 ) /* (PIOA) Base Address */ +#define AT91C_BASE_CKGR ( 0xFFFFFC20 ) /* (CKGR) Base Address */ +#define AT91C_BASE_PMC ( 0xFFFFFC00 ) /* (PMC) Base Address */ +#define AT91C_BASE_RSTC ( 0xFFFFFD00 ) /* (RSTC) Base Address */ +#define AT91C_BASE_RTTC ( 0xFFFFFD20 ) /* (RTTC) Base Address */ +#define AT91C_BASE_PITC ( 0xFFFFFD30 ) /* (PITC) Base Address */ +#define AT91C_BASE_WDTC ( 0xFFFFFD40 ) /* (WDTC) Base Address */ +#define AT91C_BASE_MC ( 0xFFFFFF00 ) /* (MC) Base Address */ +#define AT91C_BASE_PDC_SPI ( 0xFFFE0100 ) /* (PDC_SPI) Base Address */ +#define AT91C_BASE_SPI ( 0xFFFE0000 ) /* (SPI) Base Address */ +#define AT91C_BASE_PDC_ADC ( 0xFFFD8100 ) /* (PDC_ADC) Base Address */ +#define AT91C_BASE_ADC ( 0xFFFD8000 ) /* (ADC) Base Address */ +#define AT91C_BASE_PDC_SSC ( 0xFFFD4100 ) /* (PDC_SSC) Base Address */ +#define AT91C_BASE_SSC ( 0xFFFD4000 ) /* (SSC) Base Address */ +#define AT91C_BASE_PDC_US1 ( 0xFFFC4100 ) /* (PDC_US1) Base Address */ +#define AT91C_BASE_US1 ( 0xFFFC4000 ) /* (US1) Base Address */ +#define AT91C_BASE_PDC_US0 ( 0xFFFC0100 ) /* (PDC_US0) Base Address */ +#define AT91C_BASE_US0 ( 0xFFFC0000 ) /* (US0) Base Address */ +#define AT91C_BASE_TWI ( 0xFFFB8000 ) /* (TWI) Base Address */ +#define AT91C_BASE_TC2 ( 0xFFFA0080 ) /* (TC2) Base Address */ +#define AT91C_BASE_TC1 ( 0xFFFA0040 ) /* (TC1) Base Address */ +#define AT91C_BASE_TC0 ( 0xFFFA0000 ) /* (TC0) Base Address */ +#define AT91C_BASE_TCB ( 0xFFFA0000 ) /* (TCB) Base Address */ +#define AT91C_BASE_PWMC_CH3 ( 0xFFFCC260 ) /* (PWMC_CH3) Base Address */ +#define AT91C_BASE_PWMC_CH2 ( 0xFFFCC240 ) /* (PWMC_CH2) Base Address */ +#define AT91C_BASE_PWMC_CH1 ( 0xFFFCC220 ) /* (PWMC_CH1) Base Address */ +#define AT91C_BASE_PWMC_CH0 ( 0xFFFCC200 ) /* (PWMC_CH0) Base Address */ +#define AT91C_BASE_PWMC ( 0xFFFCC000 ) /* (PWMC) Base Address */ +#define AT91C_BASE_UDP ( 0xFFFB0000 ) /* (UDP) Base Address */ -// ***************************************************************************** -// MEMORY MAPPING DEFINITIONS FOR AT91SAM7S64 -// ***************************************************************************** -#define AT91C_ISRAM (0x00200000) // Internal SRAM base address -#define AT91C_ISRAM_SIZE (0x00004000) // Internal SRAM size in byte (16 Kbyte) -#define AT91C_IFLASH (0x00100000) // Internal ROM base address -#define AT91C_IFLASH_SIZE (0x00010000) // Internal ROM size in byte (64 Kbyte) +/* ***************************************************************************** */ +/* MEMORY MAPPING DEFINITIONS FOR AT91SAM7S64 */ +/* ***************************************************************************** */ +#define AT91C_ISRAM ( 0x00200000 ) /* Internal SRAM base address */ +#define AT91C_ISRAM_SIZE ( 0x00004000 ) /* Internal SRAM size in byte (16 Kbyte) */ +#define AT91C_IFLASH ( 0x00100000 ) /* Internal ROM base address */ +#define AT91C_IFLASH_SIZE ( 0x00010000 ) /* Internal ROM size in byte (64 Kbyte) */ diff --git a/Source/portable/IAR/AtmelSAM7S64/AT91SAM7X128.h b/Source/portable/IAR/AtmelSAM7S64/AT91SAM7X128.h index 3ebad2527..b8a7652f4 100644 --- a/Source/portable/IAR/AtmelSAM7S64/AT91SAM7X128.h +++ b/Source/portable/IAR/AtmelSAM7S64/AT91SAM7X128.h @@ -1,2715 +1,2743 @@ -// ---------------------------------------------------------------------------- -// ATMEL Microcontroller Software Support - ROUSSET - -// ---------------------------------------------------------------------------- -// DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR -// IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF -// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE -// DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, -// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, -// OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF -// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING -// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, -// EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// ---------------------------------------------------------------------------- -// File Name : AT91SAM7X128.h -// Object : AT91SAM7X128 definitions -// Generated : AT91 SW Application Group 05/20/2005 (16:22:23) -// -// CVS Reference : /AT91SAM7X128.pl/1.14/Tue May 10 12:12:05 2005// -// CVS Reference : /SYS_SAM7X.pl/1.3/Tue Feb 1 17:01:43 2005// -// CVS Reference : /MC_SAM7X.pl/1.2/Fri May 20 14:13:04 2005// -// CVS Reference : /PMC_SAM7X.pl/1.4/Tue Feb 8 13:58:10 2005// -// CVS Reference : /RSTC_SAM7X.pl/1.1/Tue Feb 1 16:16:26 2005// -// CVS Reference : /UDP_SAM7X.pl/1.1/Tue May 10 11:35:35 2005// -// CVS Reference : /PWM_SAM7X.pl/1.1/Tue May 10 11:53:07 2005// -// CVS Reference : /AIC_6075B.pl/1.3/Fri May 20 14:01:30 2005// -// CVS Reference : /PIO_6057A.pl/1.2/Thu Feb 3 10:18:28 2005// -// CVS Reference : /RTTC_6081A.pl/1.2/Tue Nov 9 14:43:58 2004// -// CVS Reference : /PITC_6079A.pl/1.2/Tue Nov 9 14:43:56 2004// -// CVS Reference : /WDTC_6080A.pl/1.3/Tue Nov 9 14:44:00 2004// -// CVS Reference : /VREG_6085B.pl/1.1/Tue Feb 1 16:05:48 2005// -// CVS Reference : /PDC_6074C.pl/1.2/Thu Feb 3 08:48:54 2005// -// CVS Reference : /DBGU_6059D.pl/1.1/Mon Jan 31 13:15:32 2005// -// CVS Reference : /SPI_6088D.pl/1.3/Fri May 20 14:08:59 2005// -// CVS Reference : /US_6089C.pl/1.1/Mon Jul 12 18:23:26 2004// -// CVS Reference : /SSC_6078A.pl/1.1/Tue Jul 13 07:45:40 2004// -// CVS Reference : /TWI_6061A.pl/1.1/Tue Jul 13 07:38:06 2004// -// CVS Reference : /TC_6082A.pl/1.7/Fri Mar 11 12:52:17 2005// -// CVS Reference : /CAN_6019B.pl/1.1/Tue Mar 8 12:42:22 2005// -// CVS Reference : /EMACB_6119A.pl/1.5/Thu Feb 3 15:52:04 2005// -// CVS Reference : /ADC_6051C.pl/1.1/Fri Oct 17 09:12:38 2003// -// CVS Reference : /AES_6149A.pl/1.10/Mon Feb 7 09:44:25 2005// -// CVS Reference : /DES3_6150A.pl/1.1/Mon Jan 17 08:34:31 2005// -// ---------------------------------------------------------------------------- +/* ---------------------------------------------------------------------------- */ +/* ATMEL Microcontroller Software Support - ROUSSET - */ +/* ---------------------------------------------------------------------------- */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ +/* File Name : AT91SAM7X128.h */ +/* Object : AT91SAM7X128 definitions */ +/* Generated : AT91 SW Application Group 05/20/2005 (16:22:23) */ +/* */ +/* CVS Reference : /AT91SAM7X128.pl/1.14/Tue May 10 12:12:05 2005// */ +/* CVS Reference : /SYS_SAM7X.pl/1.3/Tue Feb 1 17:01:43 2005// */ +/* CVS Reference : /MC_SAM7X.pl/1.2/Fri May 20 14:13:04 2005// */ +/* CVS Reference : /PMC_SAM7X.pl/1.4/Tue Feb 8 13:58:10 2005// */ +/* CVS Reference : /RSTC_SAM7X.pl/1.1/Tue Feb 1 16:16:26 2005// */ +/* CVS Reference : /UDP_SAM7X.pl/1.1/Tue May 10 11:35:35 2005// */ +/* CVS Reference : /PWM_SAM7X.pl/1.1/Tue May 10 11:53:07 2005// */ +/* CVS Reference : /AIC_6075B.pl/1.3/Fri May 20 14:01:30 2005// */ +/* CVS Reference : /PIO_6057A.pl/1.2/Thu Feb 3 10:18:28 2005// */ +/* CVS Reference : /RTTC_6081A.pl/1.2/Tue Nov 9 14:43:58 2004// */ +/* CVS Reference : /PITC_6079A.pl/1.2/Tue Nov 9 14:43:56 2004// */ +/* CVS Reference : /WDTC_6080A.pl/1.3/Tue Nov 9 14:44:00 2004// */ +/* CVS Reference : /VREG_6085B.pl/1.1/Tue Feb 1 16:05:48 2005// */ +/* CVS Reference : /PDC_6074C.pl/1.2/Thu Feb 3 08:48:54 2005// */ +/* CVS Reference : /DBGU_6059D.pl/1.1/Mon Jan 31 13:15:32 2005// */ +/* CVS Reference : /SPI_6088D.pl/1.3/Fri May 20 14:08:59 2005// */ +/* CVS Reference : /US_6089C.pl/1.1/Mon Jul 12 18:23:26 2004// */ +/* CVS Reference : /SSC_6078A.pl/1.1/Tue Jul 13 07:45:40 2004// */ +/* CVS Reference : /TWI_6061A.pl/1.1/Tue Jul 13 07:38:06 2004// */ +/* CVS Reference : /TC_6082A.pl/1.7/Fri Mar 11 12:52:17 2005// */ +/* CVS Reference : /CAN_6019B.pl/1.1/Tue Mar 8 12:42:22 2005// */ +/* CVS Reference : /EMACB_6119A.pl/1.5/Thu Feb 3 15:52:04 2005// */ +/* CVS Reference : /ADC_6051C.pl/1.1/Fri Oct 17 09:12:38 2003// */ +/* CVS Reference : /AES_6149A.pl/1.10/Mon Feb 7 09:44:25 2005// */ +/* CVS Reference : /DES3_6150A.pl/1.1/Mon Jan 17 08:34:31 2005// */ +/* ---------------------------------------------------------------------------- */ #ifndef AT91SAM7X128_H #define AT91SAM7X128_H -typedef volatile unsigned int AT91_REG;// Hardware register definition - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR System Peripherals -// ***************************************************************************** -typedef struct _AT91S_SYS { - AT91_REG AIC_SMR[32]; // Source Mode Register - AT91_REG AIC_SVR[32]; // Source Vector Register - AT91_REG AIC_IVR; // IRQ Vector Register - AT91_REG AIC_FVR; // FIQ Vector Register - AT91_REG AIC_ISR; // Interrupt Status Register - AT91_REG AIC_IPR; // Interrupt Pending Register - AT91_REG AIC_IMR; // Interrupt Mask Register - AT91_REG AIC_CISR; // Core Interrupt Status Register - AT91_REG Reserved0[2]; // - AT91_REG AIC_IECR; // Interrupt Enable Command Register - AT91_REG AIC_IDCR; // Interrupt Disable Command Register - AT91_REG AIC_ICCR; // Interrupt Clear Command Register - AT91_REG AIC_ISCR; // Interrupt Set Command Register - AT91_REG AIC_EOICR; // End of Interrupt Command Register - AT91_REG AIC_SPU; // Spurious Vector Register - AT91_REG AIC_DCR; // Debug Control Register (Protect) - AT91_REG Reserved1[1]; // - AT91_REG AIC_FFER; // Fast Forcing Enable Register - AT91_REG AIC_FFDR; // Fast Forcing Disable Register - AT91_REG AIC_FFSR; // Fast Forcing Status Register - AT91_REG Reserved2[45]; // - AT91_REG DBGU_CR; // Control Register - AT91_REG DBGU_MR; // Mode Register - AT91_REG DBGU_IER; // Interrupt Enable Register - AT91_REG DBGU_IDR; // Interrupt Disable Register - AT91_REG DBGU_IMR; // Interrupt Mask Register - AT91_REG DBGU_CSR; // Channel Status Register - AT91_REG DBGU_RHR; // Receiver Holding Register - AT91_REG DBGU_THR; // Transmitter Holding Register - AT91_REG DBGU_BRGR; // Baud Rate Generator Register - AT91_REG Reserved3[7]; // - AT91_REG DBGU_CIDR; // Chip ID Register - AT91_REG DBGU_EXID; // Chip ID Extension Register - AT91_REG DBGU_FNTR; // Force NTRST Register - AT91_REG Reserved4[45]; // - AT91_REG DBGU_RPR; // Receive Pointer Register - AT91_REG DBGU_RCR; // Receive Counter Register - AT91_REG DBGU_TPR; // Transmit Pointer Register - AT91_REG DBGU_TCR; // Transmit Counter Register - AT91_REG DBGU_RNPR; // Receive Next Pointer Register - AT91_REG DBGU_RNCR; // Receive Next Counter Register - AT91_REG DBGU_TNPR; // Transmit Next Pointer Register - AT91_REG DBGU_TNCR; // Transmit Next Counter Register - AT91_REG DBGU_PTCR; // PDC Transfer Control Register - AT91_REG DBGU_PTSR; // PDC Transfer Status Register - AT91_REG Reserved5[54]; // - AT91_REG PIOA_PER; // PIO Enable Register - AT91_REG PIOA_PDR; // PIO Disable Register - AT91_REG PIOA_PSR; // PIO Status Register - AT91_REG Reserved6[1]; // - AT91_REG PIOA_OER; // Output Enable Register - AT91_REG PIOA_ODR; // Output Disable Registerr - AT91_REG PIOA_OSR; // Output Status Register - AT91_REG Reserved7[1]; // - AT91_REG PIOA_IFER; // Input Filter Enable Register - AT91_REG PIOA_IFDR; // Input Filter Disable Register - AT91_REG PIOA_IFSR; // Input Filter Status Register - AT91_REG Reserved8[1]; // - AT91_REG PIOA_SODR; // Set Output Data Register - AT91_REG PIOA_CODR; // Clear Output Data Register - AT91_REG PIOA_ODSR; // Output Data Status Register - AT91_REG PIOA_PDSR; // Pin Data Status Register - AT91_REG PIOA_IER; // Interrupt Enable Register - AT91_REG PIOA_IDR; // Interrupt Disable Register - AT91_REG PIOA_IMR; // Interrupt Mask Register - AT91_REG PIOA_ISR; // Interrupt Status Register - AT91_REG PIOA_MDER; // Multi-driver Enable Register - AT91_REG PIOA_MDDR; // Multi-driver Disable Register - AT91_REG PIOA_MDSR; // Multi-driver Status Register - AT91_REG Reserved9[1]; // - AT91_REG PIOA_PPUDR; // Pull-up Disable Register - AT91_REG PIOA_PPUER; // Pull-up Enable Register - AT91_REG PIOA_PPUSR; // Pull-up Status Register - AT91_REG Reserved10[1]; // - AT91_REG PIOA_ASR; // Select A Register - AT91_REG PIOA_BSR; // Select B Register - AT91_REG PIOA_ABSR; // AB Select Status Register - AT91_REG Reserved11[9]; // - AT91_REG PIOA_OWER; // Output Write Enable Register - AT91_REG PIOA_OWDR; // Output Write Disable Register - AT91_REG PIOA_OWSR; // Output Write Status Register - AT91_REG Reserved12[85]; // - AT91_REG PIOB_PER; // PIO Enable Register - AT91_REG PIOB_PDR; // PIO Disable Register - AT91_REG PIOB_PSR; // PIO Status Register - AT91_REG Reserved13[1]; // - AT91_REG PIOB_OER; // Output Enable Register - AT91_REG PIOB_ODR; // Output Disable Registerr - AT91_REG PIOB_OSR; // Output Status Register - AT91_REG Reserved14[1]; // - AT91_REG PIOB_IFER; // Input Filter Enable Register - AT91_REG PIOB_IFDR; // Input Filter Disable Register - AT91_REG PIOB_IFSR; // Input Filter Status Register - AT91_REG Reserved15[1]; // - AT91_REG PIOB_SODR; // Set Output Data Register - AT91_REG PIOB_CODR; // Clear Output Data Register - AT91_REG PIOB_ODSR; // Output Data Status Register - AT91_REG PIOB_PDSR; // Pin Data Status Register - AT91_REG PIOB_IER; // Interrupt Enable Register - AT91_REG PIOB_IDR; // Interrupt Disable Register - AT91_REG PIOB_IMR; // Interrupt Mask Register - AT91_REG PIOB_ISR; // Interrupt Status Register - AT91_REG PIOB_MDER; // Multi-driver Enable Register - AT91_REG PIOB_MDDR; // Multi-driver Disable Register - AT91_REG PIOB_MDSR; // Multi-driver Status Register - AT91_REG Reserved16[1]; // - AT91_REG PIOB_PPUDR; // Pull-up Disable Register - AT91_REG PIOB_PPUER; // Pull-up Enable Register - AT91_REG PIOB_PPUSR; // Pull-up Status Register - AT91_REG Reserved17[1]; // - AT91_REG PIOB_ASR; // Select A Register - AT91_REG PIOB_BSR; // Select B Register - AT91_REG PIOB_ABSR; // AB Select Status Register - AT91_REG Reserved18[9]; // - AT91_REG PIOB_OWER; // Output Write Enable Register - AT91_REG PIOB_OWDR; // Output Write Disable Register - AT91_REG PIOB_OWSR; // Output Write Status Register - AT91_REG Reserved19[341]; // - AT91_REG PMC_SCER; // System Clock Enable Register - AT91_REG PMC_SCDR; // System Clock Disable Register - AT91_REG PMC_SCSR; // System Clock Status Register - AT91_REG Reserved20[1]; // - AT91_REG PMC_PCER; // Peripheral Clock Enable Register - AT91_REG PMC_PCDR; // Peripheral Clock Disable Register - AT91_REG PMC_PCSR; // Peripheral Clock Status Register - AT91_REG Reserved21[1]; // - AT91_REG PMC_MOR; // Main Oscillator Register - AT91_REG PMC_MCFR; // Main Clock Frequency Register - AT91_REG Reserved22[1]; // - AT91_REG PMC_PLLR; // PLL Register - AT91_REG PMC_MCKR; // Master Clock Register - AT91_REG Reserved23[3]; // - AT91_REG PMC_PCKR[4]; // Programmable Clock Register - AT91_REG Reserved24[4]; // - AT91_REG PMC_IER; // Interrupt Enable Register - AT91_REG PMC_IDR; // Interrupt Disable Register - AT91_REG PMC_SR; // Status Register - AT91_REG PMC_IMR; // Interrupt Mask Register - AT91_REG Reserved25[36]; // - AT91_REG RSTC_RCR; // Reset Control Register - AT91_REG RSTC_RSR; // Reset Status Register - AT91_REG RSTC_RMR; // Reset Mode Register - AT91_REG Reserved26[5]; // - AT91_REG RTTC_RTMR; // Real-time Mode Register - AT91_REG RTTC_RTAR; // Real-time Alarm Register - AT91_REG RTTC_RTVR; // Real-time Value Register - AT91_REG RTTC_RTSR; // Real-time Status Register - AT91_REG PITC_PIMR; // Period Interval Mode Register - AT91_REG PITC_PISR; // Period Interval Status Register - AT91_REG PITC_PIVR; // Period Interval Value Register - AT91_REG PITC_PIIR; // Period Interval Image Register - AT91_REG WDTC_WDCR; // Watchdog Control Register - AT91_REG WDTC_WDMR; // Watchdog Mode Register - AT91_REG WDTC_WDSR; // Watchdog Status Register - AT91_REG Reserved27[5]; // - AT91_REG VREG_MR; // Voltage Regulator Mode Register -} AT91S_SYS, *AT91PS_SYS; - - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Advanced Interrupt Controller -// ***************************************************************************** -typedef struct _AT91S_AIC { - AT91_REG AIC_SMR[32]; // Source Mode Register - AT91_REG AIC_SVR[32]; // Source Vector Register - AT91_REG AIC_IVR; // IRQ Vector Register - AT91_REG AIC_FVR; // FIQ Vector Register - AT91_REG AIC_ISR; // Interrupt Status Register - AT91_REG AIC_IPR; // Interrupt Pending Register - AT91_REG AIC_IMR; // Interrupt Mask Register - AT91_REG AIC_CISR; // Core Interrupt Status Register - AT91_REG Reserved0[2]; // - AT91_REG AIC_IECR; // Interrupt Enable Command Register - AT91_REG AIC_IDCR; // Interrupt Disable Command Register - AT91_REG AIC_ICCR; // Interrupt Clear Command Register - AT91_REG AIC_ISCR; // Interrupt Set Command Register - AT91_REG AIC_EOICR; // End of Interrupt Command Register - AT91_REG AIC_SPU; // Spurious Vector Register - AT91_REG AIC_DCR; // Debug Control Register (Protect) - AT91_REG Reserved1[1]; // - AT91_REG AIC_FFER; // Fast Forcing Enable Register - AT91_REG AIC_FFDR; // Fast Forcing Disable Register - AT91_REG AIC_FFSR; // Fast Forcing Status Register -} AT91S_AIC, *AT91PS_AIC; - -// -------- AIC_SMR : (AIC Offset: 0x0) Control Register -------- -#define AT91C_AIC_PRIOR ((unsigned int) 0x7 << 0) // (AIC) Priority Level -#define AT91C_AIC_PRIOR_LOWEST ((unsigned int) 0x0) // (AIC) Lowest priority level -#define AT91C_AIC_PRIOR_HIGHEST ((unsigned int) 0x7) // (AIC) Highest priority level -#define AT91C_AIC_SRCTYPE ((unsigned int) 0x3 << 5) // (AIC) Interrupt Source Type -#define AT91C_AIC_SRCTYPE_INT_HIGH_LEVEL ((unsigned int) 0x0 << 5) // (AIC) Internal Sources Code Label High-level Sensitive -#define AT91C_AIC_SRCTYPE_EXT_LOW_LEVEL ((unsigned int) 0x0 << 5) // (AIC) External Sources Code Label Low-level Sensitive -#define AT91C_AIC_SRCTYPE_INT_POSITIVE_EDGE ((unsigned int) 0x1 << 5) // (AIC) Internal Sources Code Label Positive Edge triggered -#define AT91C_AIC_SRCTYPE_EXT_NEGATIVE_EDGE ((unsigned int) 0x1 << 5) // (AIC) External Sources Code Label Negative Edge triggered -#define AT91C_AIC_SRCTYPE_HIGH_LEVEL ((unsigned int) 0x2 << 5) // (AIC) Internal Or External Sources Code Label High-level Sensitive -#define AT91C_AIC_SRCTYPE_POSITIVE_EDGE ((unsigned int) 0x3 << 5) // (AIC) Internal Or External Sources Code Label Positive Edge triggered -// -------- AIC_CISR : (AIC Offset: 0x114) AIC Core Interrupt Status Register -------- -#define AT91C_AIC_NFIQ ((unsigned int) 0x1 << 0) // (AIC) NFIQ Status -#define AT91C_AIC_NIRQ ((unsigned int) 0x1 << 1) // (AIC) NIRQ Status -// -------- AIC_DCR : (AIC Offset: 0x138) AIC Debug Control Register (Protect) -------- -#define AT91C_AIC_DCR_PROT ((unsigned int) 0x1 << 0) // (AIC) Protection Mode -#define AT91C_AIC_DCR_GMSK ((unsigned int) 0x1 << 1) // (AIC) General Mask - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Peripheral DMA Controller -// ***************************************************************************** -typedef struct _AT91S_PDC { - AT91_REG PDC_RPR; // Receive Pointer Register - AT91_REG PDC_RCR; // Receive Counter Register - AT91_REG PDC_TPR; // Transmit Pointer Register - AT91_REG PDC_TCR; // Transmit Counter Register - AT91_REG PDC_RNPR; // Receive Next Pointer Register - AT91_REG PDC_RNCR; // Receive Next Counter Register - AT91_REG PDC_TNPR; // Transmit Next Pointer Register - AT91_REG PDC_TNCR; // Transmit Next Counter Register - AT91_REG PDC_PTCR; // PDC Transfer Control Register - AT91_REG PDC_PTSR; // PDC Transfer Status Register -} AT91S_PDC, *AT91PS_PDC; - -// -------- PDC_PTCR : (PDC Offset: 0x20) PDC Transfer Control Register -------- -#define AT91C_PDC_RXTEN ((unsigned int) 0x1 << 0) // (PDC) Receiver Transfer Enable -#define AT91C_PDC_RXTDIS ((unsigned int) 0x1 << 1) // (PDC) Receiver Transfer Disable -#define AT91C_PDC_TXTEN ((unsigned int) 0x1 << 8) // (PDC) Transmitter Transfer Enable -#define AT91C_PDC_TXTDIS ((unsigned int) 0x1 << 9) // (PDC) Transmitter Transfer Disable -// -------- PDC_PTSR : (PDC Offset: 0x24) PDC Transfer Status Register -------- - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Debug Unit -// ***************************************************************************** -typedef struct _AT91S_DBGU { - AT91_REG DBGU_CR; // Control Register - AT91_REG DBGU_MR; // Mode Register - AT91_REG DBGU_IER; // Interrupt Enable Register - AT91_REG DBGU_IDR; // Interrupt Disable Register - AT91_REG DBGU_IMR; // Interrupt Mask Register - AT91_REG DBGU_CSR; // Channel Status Register - AT91_REG DBGU_RHR; // Receiver Holding Register - AT91_REG DBGU_THR; // Transmitter Holding Register - AT91_REG DBGU_BRGR; // Baud Rate Generator Register - AT91_REG Reserved0[7]; // - AT91_REG DBGU_CIDR; // Chip ID Register - AT91_REG DBGU_EXID; // Chip ID Extension Register - AT91_REG DBGU_FNTR; // Force NTRST Register - AT91_REG Reserved1[45]; // - AT91_REG DBGU_RPR; // Receive Pointer Register - AT91_REG DBGU_RCR; // Receive Counter Register - AT91_REG DBGU_TPR; // Transmit Pointer Register - AT91_REG DBGU_TCR; // Transmit Counter Register - AT91_REG DBGU_RNPR; // Receive Next Pointer Register - AT91_REG DBGU_RNCR; // Receive Next Counter Register - AT91_REG DBGU_TNPR; // Transmit Next Pointer Register - AT91_REG DBGU_TNCR; // Transmit Next Counter Register - AT91_REG DBGU_PTCR; // PDC Transfer Control Register - AT91_REG DBGU_PTSR; // PDC Transfer Status Register -} AT91S_DBGU, *AT91PS_DBGU; - -// -------- DBGU_CR : (DBGU Offset: 0x0) Debug Unit Control Register -------- -#define AT91C_US_RSTRX ((unsigned int) 0x1 << 2) // (DBGU) Reset Receiver -#define AT91C_US_RSTTX ((unsigned int) 0x1 << 3) // (DBGU) Reset Transmitter -#define AT91C_US_RXEN ((unsigned int) 0x1 << 4) // (DBGU) Receiver Enable -#define AT91C_US_RXDIS ((unsigned int) 0x1 << 5) // (DBGU) Receiver Disable -#define AT91C_US_TXEN ((unsigned int) 0x1 << 6) // (DBGU) Transmitter Enable -#define AT91C_US_TXDIS ((unsigned int) 0x1 << 7) // (DBGU) Transmitter Disable -#define AT91C_US_RSTSTA ((unsigned int) 0x1 << 8) // (DBGU) Reset Status Bits -// -------- DBGU_MR : (DBGU Offset: 0x4) Debug Unit Mode Register -------- -#define AT91C_US_PAR ((unsigned int) 0x7 << 9) // (DBGU) Parity type -#define AT91C_US_PAR_EVEN ((unsigned int) 0x0 << 9) // (DBGU) Even Parity -#define AT91C_US_PAR_ODD ((unsigned int) 0x1 << 9) // (DBGU) Odd Parity -#define AT91C_US_PAR_SPACE ((unsigned int) 0x2 << 9) // (DBGU) Parity forced to 0 (Space) -#define AT91C_US_PAR_MARK ((unsigned int) 0x3 << 9) // (DBGU) Parity forced to 1 (Mark) -#define AT91C_US_PAR_NONE ((unsigned int) 0x4 << 9) // (DBGU) No Parity -#define AT91C_US_PAR_MULTI_DROP ((unsigned int) 0x6 << 9) // (DBGU) Multi-drop mode -#define AT91C_US_CHMODE ((unsigned int) 0x3 << 14) // (DBGU) Channel Mode -#define AT91C_US_CHMODE_NORMAL ((unsigned int) 0x0 << 14) // (DBGU) Normal Mode: The USART channel operates as an RX/TX USART. -#define AT91C_US_CHMODE_AUTO ((unsigned int) 0x1 << 14) // (DBGU) Automatic Echo: Receiver Data Input is connected to the TXD pin. -#define AT91C_US_CHMODE_LOCAL ((unsigned int) 0x2 << 14) // (DBGU) Local Loopback: Transmitter Output Signal is connected to Receiver Input Signal. -#define AT91C_US_CHMODE_REMOTE ((unsigned int) 0x3 << 14) // (DBGU) Remote Loopback: RXD pin is internally connected to TXD pin. -// -------- DBGU_IER : (DBGU Offset: 0x8) Debug Unit Interrupt Enable Register -------- -#define AT91C_US_RXRDY ((unsigned int) 0x1 << 0) // (DBGU) RXRDY Interrupt -#define AT91C_US_TXRDY ((unsigned int) 0x1 << 1) // (DBGU) TXRDY Interrupt -#define AT91C_US_ENDRX ((unsigned int) 0x1 << 3) // (DBGU) End of Receive Transfer Interrupt -#define AT91C_US_ENDTX ((unsigned int) 0x1 << 4) // (DBGU) End of Transmit Interrupt -#define AT91C_US_OVRE ((unsigned int) 0x1 << 5) // (DBGU) Overrun Interrupt -#define AT91C_US_FRAME ((unsigned int) 0x1 << 6) // (DBGU) Framing Error Interrupt -#define AT91C_US_PARE ((unsigned int) 0x1 << 7) // (DBGU) Parity Error Interrupt -#define AT91C_US_TXEMPTY ((unsigned int) 0x1 << 9) // (DBGU) TXEMPTY Interrupt -#define AT91C_US_TXBUFE ((unsigned int) 0x1 << 11) // (DBGU) TXBUFE Interrupt -#define AT91C_US_RXBUFF ((unsigned int) 0x1 << 12) // (DBGU) RXBUFF Interrupt -#define AT91C_US_COMM_TX ((unsigned int) 0x1 << 30) // (DBGU) COMM_TX Interrupt -#define AT91C_US_COMM_RX ((unsigned int) 0x1 << 31) // (DBGU) COMM_RX Interrupt -// -------- DBGU_IDR : (DBGU Offset: 0xc) Debug Unit Interrupt Disable Register -------- -// -------- DBGU_IMR : (DBGU Offset: 0x10) Debug Unit Interrupt Mask Register -------- -// -------- DBGU_CSR : (DBGU Offset: 0x14) Debug Unit Channel Status Register -------- -// -------- DBGU_FNTR : (DBGU Offset: 0x48) Debug Unit FORCE_NTRST Register -------- -#define AT91C_US_FORCE_NTRST ((unsigned int) 0x1 << 0) // (DBGU) Force NTRST in JTAG - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Parallel Input Output Controler -// ***************************************************************************** -typedef struct _AT91S_PIO { - AT91_REG PIO_PER; // PIO Enable Register - AT91_REG PIO_PDR; // PIO Disable Register - AT91_REG PIO_PSR; // PIO Status Register - AT91_REG Reserved0[1]; // - AT91_REG PIO_OER; // Output Enable Register - AT91_REG PIO_ODR; // Output Disable Registerr - AT91_REG PIO_OSR; // Output Status Register - AT91_REG Reserved1[1]; // - AT91_REG PIO_IFER; // Input Filter Enable Register - AT91_REG PIO_IFDR; // Input Filter Disable Register - AT91_REG PIO_IFSR; // Input Filter Status Register - AT91_REG Reserved2[1]; // - AT91_REG PIO_SODR; // Set Output Data Register - AT91_REG PIO_CODR; // Clear Output Data Register - AT91_REG PIO_ODSR; // Output Data Status Register - AT91_REG PIO_PDSR; // Pin Data Status Register - AT91_REG PIO_IER; // Interrupt Enable Register - AT91_REG PIO_IDR; // Interrupt Disable Register - AT91_REG PIO_IMR; // Interrupt Mask Register - AT91_REG PIO_ISR; // Interrupt Status Register - AT91_REG PIO_MDER; // Multi-driver Enable Register - AT91_REG PIO_MDDR; // Multi-driver Disable Register - AT91_REG PIO_MDSR; // Multi-driver Status Register - AT91_REG Reserved3[1]; // - AT91_REG PIO_PPUDR; // Pull-up Disable Register - AT91_REG PIO_PPUER; // Pull-up Enable Register - AT91_REG PIO_PPUSR; // Pull-up Status Register - AT91_REG Reserved4[1]; // - AT91_REG PIO_ASR; // Select A Register - AT91_REG PIO_BSR; // Select B Register - AT91_REG PIO_ABSR; // AB Select Status Register - AT91_REG Reserved5[9]; // - AT91_REG PIO_OWER; // Output Write Enable Register - AT91_REG PIO_OWDR; // Output Write Disable Register - AT91_REG PIO_OWSR; // Output Write Status Register -} AT91S_PIO, *AT91PS_PIO; - - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Clock Generator Controler -// ***************************************************************************** -typedef struct _AT91S_CKGR { - AT91_REG CKGR_MOR; // Main Oscillator Register - AT91_REG CKGR_MCFR; // Main Clock Frequency Register - AT91_REG Reserved0[1]; // - AT91_REG CKGR_PLLR; // PLL Register -} AT91S_CKGR, *AT91PS_CKGR; - -// -------- CKGR_MOR : (CKGR Offset: 0x0) Main Oscillator Register -------- -#define AT91C_CKGR_MOSCEN ((unsigned int) 0x1 << 0) // (CKGR) Main Oscillator Enable -#define AT91C_CKGR_OSCBYPASS ((unsigned int) 0x1 << 1) // (CKGR) Main Oscillator Bypass -#define AT91C_CKGR_OSCOUNT ((unsigned int) 0xFF << 8) // (CKGR) Main Oscillator Start-up Time -// -------- CKGR_MCFR : (CKGR Offset: 0x4) Main Clock Frequency Register -------- -#define AT91C_CKGR_MAINF ((unsigned int) 0xFFFF << 0) // (CKGR) Main Clock Frequency -#define AT91C_CKGR_MAINRDY ((unsigned int) 0x1 << 16) // (CKGR) Main Clock Ready -// -------- CKGR_PLLR : (CKGR Offset: 0xc) PLL B Register -------- -#define AT91C_CKGR_DIV ((unsigned int) 0xFF << 0) // (CKGR) Divider Selected -#define AT91C_CKGR_DIV_0 ((unsigned int) 0x0) // (CKGR) Divider output is 0 -#define AT91C_CKGR_DIV_BYPASS ((unsigned int) 0x1) // (CKGR) Divider is bypassed -#define AT91C_CKGR_PLLCOUNT ((unsigned int) 0x3F << 8) // (CKGR) PLL Counter -#define AT91C_CKGR_OUT ((unsigned int) 0x3 << 14) // (CKGR) PLL Output Frequency Range -#define AT91C_CKGR_OUT_0 ((unsigned int) 0x0 << 14) // (CKGR) Please refer to the PLL datasheet -#define AT91C_CKGR_OUT_1 ((unsigned int) 0x1 << 14) // (CKGR) Please refer to the PLL datasheet -#define AT91C_CKGR_OUT_2 ((unsigned int) 0x2 << 14) // (CKGR) Please refer to the PLL datasheet -#define AT91C_CKGR_OUT_3 ((unsigned int) 0x3 << 14) // (CKGR) Please refer to the PLL datasheet -#define AT91C_CKGR_MUL ((unsigned int) 0x7FF << 16) // (CKGR) PLL Multiplier -#define AT91C_CKGR_USBDIV ((unsigned int) 0x3 << 28) // (CKGR) Divider for USB Clocks -#define AT91C_CKGR_USBDIV_0 ((unsigned int) 0x0 << 28) // (CKGR) Divider output is PLL clock output -#define AT91C_CKGR_USBDIV_1 ((unsigned int) 0x1 << 28) // (CKGR) Divider output is PLL clock output divided by 2 -#define AT91C_CKGR_USBDIV_2 ((unsigned int) 0x2 << 28) // (CKGR) Divider output is PLL clock output divided by 4 - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Power Management Controler -// ***************************************************************************** -typedef struct _AT91S_PMC { - AT91_REG PMC_SCER; // System Clock Enable Register - AT91_REG PMC_SCDR; // System Clock Disable Register - AT91_REG PMC_SCSR; // System Clock Status Register - AT91_REG Reserved0[1]; // - AT91_REG PMC_PCER; // Peripheral Clock Enable Register - AT91_REG PMC_PCDR; // Peripheral Clock Disable Register - AT91_REG PMC_PCSR; // Peripheral Clock Status Register - AT91_REG Reserved1[1]; // - AT91_REG PMC_MOR; // Main Oscillator Register - AT91_REG PMC_MCFR; // Main Clock Frequency Register - AT91_REG Reserved2[1]; // - AT91_REG PMC_PLLR; // PLL Register - AT91_REG PMC_MCKR; // Master Clock Register - AT91_REG Reserved3[3]; // - AT91_REG PMC_PCKR[4]; // Programmable Clock Register - AT91_REG Reserved4[4]; // - AT91_REG PMC_IER; // Interrupt Enable Register - AT91_REG PMC_IDR; // Interrupt Disable Register - AT91_REG PMC_SR; // Status Register - AT91_REG PMC_IMR; // Interrupt Mask Register -} AT91S_PMC, *AT91PS_PMC; - -// -------- PMC_SCER : (PMC Offset: 0x0) System Clock Enable Register -------- -#define AT91C_PMC_PCK ((unsigned int) 0x1 << 0) // (PMC) Processor Clock -#define AT91C_PMC_UDP ((unsigned int) 0x1 << 7) // (PMC) USB Device Port Clock -#define AT91C_PMC_PCK0 ((unsigned int) 0x1 << 8) // (PMC) Programmable Clock Output -#define AT91C_PMC_PCK1 ((unsigned int) 0x1 << 9) // (PMC) Programmable Clock Output -#define AT91C_PMC_PCK2 ((unsigned int) 0x1 << 10) // (PMC) Programmable Clock Output -#define AT91C_PMC_PCK3 ((unsigned int) 0x1 << 11) // (PMC) Programmable Clock Output -// -------- PMC_SCDR : (PMC Offset: 0x4) System Clock Disable Register -------- -// -------- PMC_SCSR : (PMC Offset: 0x8) System Clock Status Register -------- -// -------- CKGR_MOR : (PMC Offset: 0x20) Main Oscillator Register -------- -// -------- CKGR_MCFR : (PMC Offset: 0x24) Main Clock Frequency Register -------- -// -------- CKGR_PLLR : (PMC Offset: 0x2c) PLL B Register -------- -// -------- PMC_MCKR : (PMC Offset: 0x30) Master Clock Register -------- -#define AT91C_PMC_CSS ((unsigned int) 0x3 << 0) // (PMC) Programmable Clock Selection -#define AT91C_PMC_CSS_SLOW_CLK ((unsigned int) 0x0) // (PMC) Slow Clock is selected -#define AT91C_PMC_CSS_MAIN_CLK ((unsigned int) 0x1) // (PMC) Main Clock is selected -#define AT91C_PMC_CSS_PLL_CLK ((unsigned int) 0x3) // (PMC) Clock from PLL is selected -#define AT91C_PMC_PRES ((unsigned int) 0x7 << 2) // (PMC) Programmable Clock Prescaler -#define AT91C_PMC_PRES_CLK ((unsigned int) 0x0 << 2) // (PMC) Selected clock -#define AT91C_PMC_PRES_CLK_2 ((unsigned int) 0x1 << 2) // (PMC) Selected clock divided by 2 -#define AT91C_PMC_PRES_CLK_4 ((unsigned int) 0x2 << 2) // (PMC) Selected clock divided by 4 -#define AT91C_PMC_PRES_CLK_8 ((unsigned int) 0x3 << 2) // (PMC) Selected clock divided by 8 -#define AT91C_PMC_PRES_CLK_16 ((unsigned int) 0x4 << 2) // (PMC) Selected clock divided by 16 -#define AT91C_PMC_PRES_CLK_32 ((unsigned int) 0x5 << 2) // (PMC) Selected clock divided by 32 -#define AT91C_PMC_PRES_CLK_64 ((unsigned int) 0x6 << 2) // (PMC) Selected clock divided by 64 -// -------- PMC_PCKR : (PMC Offset: 0x40) Programmable Clock Register -------- -// -------- PMC_IER : (PMC Offset: 0x60) PMC Interrupt Enable Register -------- -#define AT91C_PMC_MOSCS ((unsigned int) 0x1 << 0) // (PMC) MOSC Status/Enable/Disable/Mask -#define AT91C_PMC_LOCK ((unsigned int) 0x1 << 2) // (PMC) PLL Status/Enable/Disable/Mask -#define AT91C_PMC_MCKRDY ((unsigned int) 0x1 << 3) // (PMC) MCK_RDY Status/Enable/Disable/Mask -#define AT91C_PMC_PCK0RDY ((unsigned int) 0x1 << 8) // (PMC) PCK0_RDY Status/Enable/Disable/Mask -#define AT91C_PMC_PCK1RDY ((unsigned int) 0x1 << 9) // (PMC) PCK1_RDY Status/Enable/Disable/Mask -#define AT91C_PMC_PCK2RDY ((unsigned int) 0x1 << 10) // (PMC) PCK2_RDY Status/Enable/Disable/Mask -#define AT91C_PMC_PCK3RDY ((unsigned int) 0x1 << 11) // (PMC) PCK3_RDY Status/Enable/Disable/Mask -// -------- PMC_IDR : (PMC Offset: 0x64) PMC Interrupt Disable Register -------- -// -------- PMC_SR : (PMC Offset: 0x68) PMC Status Register -------- -// -------- PMC_IMR : (PMC Offset: 0x6c) PMC Interrupt Mask Register -------- - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Reset Controller Interface -// ***************************************************************************** -typedef struct _AT91S_RSTC { - AT91_REG RSTC_RCR; // Reset Control Register - AT91_REG RSTC_RSR; // Reset Status Register - AT91_REG RSTC_RMR; // Reset Mode Register -} AT91S_RSTC, *AT91PS_RSTC; - -// -------- RSTC_RCR : (RSTC Offset: 0x0) Reset Control Register -------- -#define AT91C_RSTC_PROCRST ((unsigned int) 0x1 << 0) // (RSTC) Processor Reset -#define AT91C_RSTC_PERRST ((unsigned int) 0x1 << 2) // (RSTC) Peripheral Reset -#define AT91C_RSTC_EXTRST ((unsigned int) 0x1 << 3) // (RSTC) External Reset -#define AT91C_RSTC_KEY ((unsigned int) 0xFF << 24) // (RSTC) Password -// -------- RSTC_RSR : (RSTC Offset: 0x4) Reset Status Register -------- -#define AT91C_RSTC_URSTS ((unsigned int) 0x1 << 0) // (RSTC) User Reset Status -#define AT91C_RSTC_BODSTS ((unsigned int) 0x1 << 1) // (RSTC) Brownout Detection Status -#define AT91C_RSTC_RSTTYP ((unsigned int) 0x7 << 8) // (RSTC) Reset Type -#define AT91C_RSTC_RSTTYP_POWERUP ((unsigned int) 0x0 << 8) // (RSTC) Power-up Reset. VDDCORE rising. -#define AT91C_RSTC_RSTTYP_WAKEUP ((unsigned int) 0x1 << 8) // (RSTC) WakeUp Reset. VDDCORE rising. -#define AT91C_RSTC_RSTTYP_WATCHDOG ((unsigned int) 0x2 << 8) // (RSTC) Watchdog Reset. Watchdog overflow occured. -#define AT91C_RSTC_RSTTYP_SOFTWARE ((unsigned int) 0x3 << 8) // (RSTC) Software Reset. Processor reset required by the software. -#define AT91C_RSTC_RSTTYP_USER ((unsigned int) 0x4 << 8) // (RSTC) User Reset. NRST pin detected low. -#define AT91C_RSTC_RSTTYP_BROWNOUT ((unsigned int) 0x5 << 8) // (RSTC) Brownout Reset occured. -#define AT91C_RSTC_NRSTL ((unsigned int) 0x1 << 16) // (RSTC) NRST pin level -#define AT91C_RSTC_SRCMP ((unsigned int) 0x1 << 17) // (RSTC) Software Reset Command in Progress. -// -------- RSTC_RMR : (RSTC Offset: 0x8) Reset Mode Register -------- -#define AT91C_RSTC_URSTEN ((unsigned int) 0x1 << 0) // (RSTC) User Reset Enable -#define AT91C_RSTC_URSTIEN ((unsigned int) 0x1 << 4) // (RSTC) User Reset Interrupt Enable -#define AT91C_RSTC_ERSTL ((unsigned int) 0xF << 8) // (RSTC) User Reset Enable -#define AT91C_RSTC_BODIEN ((unsigned int) 0x1 << 16) // (RSTC) Brownout Detection Interrupt Enable - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Real Time Timer Controller Interface -// ***************************************************************************** -typedef struct _AT91S_RTTC { - AT91_REG RTTC_RTMR; // Real-time Mode Register - AT91_REG RTTC_RTAR; // Real-time Alarm Register - AT91_REG RTTC_RTVR; // Real-time Value Register - AT91_REG RTTC_RTSR; // Real-time Status Register -} AT91S_RTTC, *AT91PS_RTTC; - -// -------- RTTC_RTMR : (RTTC Offset: 0x0) Real-time Mode Register -------- -#define AT91C_RTTC_RTPRES ((unsigned int) 0xFFFF << 0) // (RTTC) Real-time Timer Prescaler Value -#define AT91C_RTTC_ALMIEN ((unsigned int) 0x1 << 16) // (RTTC) Alarm Interrupt Enable -#define AT91C_RTTC_RTTINCIEN ((unsigned int) 0x1 << 17) // (RTTC) Real Time Timer Increment Interrupt Enable -#define AT91C_RTTC_RTTRST ((unsigned int) 0x1 << 18) // (RTTC) Real Time Timer Restart -// -------- RTTC_RTAR : (RTTC Offset: 0x4) Real-time Alarm Register -------- -#define AT91C_RTTC_ALMV ((unsigned int) 0x0 << 0) // (RTTC) Alarm Value -// -------- RTTC_RTVR : (RTTC Offset: 0x8) Current Real-time Value Register -------- -#define AT91C_RTTC_CRTV ((unsigned int) 0x0 << 0) // (RTTC) Current Real-time Value -// -------- RTTC_RTSR : (RTTC Offset: 0xc) Real-time Status Register -------- -#define AT91C_RTTC_ALMS ((unsigned int) 0x1 << 0) // (RTTC) Real-time Alarm Status -#define AT91C_RTTC_RTTINC ((unsigned int) 0x1 << 1) // (RTTC) Real-time Timer Increment - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Periodic Interval Timer Controller Interface -// ***************************************************************************** -typedef struct _AT91S_PITC { - AT91_REG PITC_PIMR; // Period Interval Mode Register - AT91_REG PITC_PISR; // Period Interval Status Register - AT91_REG PITC_PIVR; // Period Interval Value Register - AT91_REG PITC_PIIR; // Period Interval Image Register -} AT91S_PITC, *AT91PS_PITC; - -// -------- PITC_PIMR : (PITC Offset: 0x0) Periodic Interval Mode Register -------- -#define AT91C_PITC_PIV ((unsigned int) 0xFFFFF << 0) // (PITC) Periodic Interval Value -#define AT91C_PITC_PITEN ((unsigned int) 0x1 << 24) // (PITC) Periodic Interval Timer Enabled -#define AT91C_PITC_PITIEN ((unsigned int) 0x1 << 25) // (PITC) Periodic Interval Timer Interrupt Enable -// -------- PITC_PISR : (PITC Offset: 0x4) Periodic Interval Status Register -------- -#define AT91C_PITC_PITS ((unsigned int) 0x1 << 0) // (PITC) Periodic Interval Timer Status -// -------- PITC_PIVR : (PITC Offset: 0x8) Periodic Interval Value Register -------- -#define AT91C_PITC_CPIV ((unsigned int) 0xFFFFF << 0) // (PITC) Current Periodic Interval Value -#define AT91C_PITC_PICNT ((unsigned int) 0xFFF << 20) // (PITC) Periodic Interval Counter -// -------- PITC_PIIR : (PITC Offset: 0xc) Periodic Interval Image Register -------- - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Watchdog Timer Controller Interface -// ***************************************************************************** -typedef struct _AT91S_WDTC { - AT91_REG WDTC_WDCR; // Watchdog Control Register - AT91_REG WDTC_WDMR; // Watchdog Mode Register - AT91_REG WDTC_WDSR; // Watchdog Status Register -} AT91S_WDTC, *AT91PS_WDTC; - -// -------- WDTC_WDCR : (WDTC Offset: 0x0) Periodic Interval Image Register -------- -#define AT91C_WDTC_WDRSTT ((unsigned int) 0x1 << 0) // (WDTC) Watchdog Restart -#define AT91C_WDTC_KEY ((unsigned int) 0xFF << 24) // (WDTC) Watchdog KEY Password -// -------- WDTC_WDMR : (WDTC Offset: 0x4) Watchdog Mode Register -------- -#define AT91C_WDTC_WDV ((unsigned int) 0xFFF << 0) // (WDTC) Watchdog Timer Restart -#define AT91C_WDTC_WDFIEN ((unsigned int) 0x1 << 12) // (WDTC) Watchdog Fault Interrupt Enable -#define AT91C_WDTC_WDRSTEN ((unsigned int) 0x1 << 13) // (WDTC) Watchdog Reset Enable -#define AT91C_WDTC_WDRPROC ((unsigned int) 0x1 << 14) // (WDTC) Watchdog Timer Restart -#define AT91C_WDTC_WDDIS ((unsigned int) 0x1 << 15) // (WDTC) Watchdog Disable -#define AT91C_WDTC_WDD ((unsigned int) 0xFFF << 16) // (WDTC) Watchdog Delta Value -#define AT91C_WDTC_WDDBGHLT ((unsigned int) 0x1 << 28) // (WDTC) Watchdog Debug Halt -#define AT91C_WDTC_WDIDLEHLT ((unsigned int) 0x1 << 29) // (WDTC) Watchdog Idle Halt -// -------- WDTC_WDSR : (WDTC Offset: 0x8) Watchdog Status Register -------- -#define AT91C_WDTC_WDUNF ((unsigned int) 0x1 << 0) // (WDTC) Watchdog Underflow -#define AT91C_WDTC_WDERR ((unsigned int) 0x1 << 1) // (WDTC) Watchdog Error - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Voltage Regulator Mode Controller Interface -// ***************************************************************************** -typedef struct _AT91S_VREG { - AT91_REG VREG_MR; // Voltage Regulator Mode Register -} AT91S_VREG, *AT91PS_VREG; - -// -------- VREG_MR : (VREG Offset: 0x0) Voltage Regulator Mode Register -------- -#define AT91C_VREG_PSTDBY ((unsigned int) 0x1 << 0) // (VREG) Voltage Regulator Power Standby Mode - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Memory Controller Interface -// ***************************************************************************** -typedef struct _AT91S_MC { - AT91_REG MC_RCR; // MC Remap Control Register - AT91_REG MC_ASR; // MC Abort Status Register - AT91_REG MC_AASR; // MC Abort Address Status Register - AT91_REG Reserved0[21]; // - AT91_REG MC_FMR; // MC Flash Mode Register - AT91_REG MC_FCR; // MC Flash Command Register - AT91_REG MC_FSR; // MC Flash Status Register -} AT91S_MC, *AT91PS_MC; - -// -------- MC_RCR : (MC Offset: 0x0) MC Remap Control Register -------- -#define AT91C_MC_RCB ((unsigned int) 0x1 << 0) // (MC) Remap Command Bit -// -------- MC_ASR : (MC Offset: 0x4) MC Abort Status Register -------- -#define AT91C_MC_UNDADD ((unsigned int) 0x1 << 0) // (MC) Undefined Addess Abort Status -#define AT91C_MC_MISADD ((unsigned int) 0x1 << 1) // (MC) Misaligned Addess Abort Status -#define AT91C_MC_ABTSZ ((unsigned int) 0x3 << 8) // (MC) Abort Size Status -#define AT91C_MC_ABTSZ_BYTE ((unsigned int) 0x0 << 8) // (MC) Byte -#define AT91C_MC_ABTSZ_HWORD ((unsigned int) 0x1 << 8) // (MC) Half-word -#define AT91C_MC_ABTSZ_WORD ((unsigned int) 0x2 << 8) // (MC) Word -#define AT91C_MC_ABTTYP ((unsigned int) 0x3 << 10) // (MC) Abort Type Status -#define AT91C_MC_ABTTYP_DATAR ((unsigned int) 0x0 << 10) // (MC) Data Read -#define AT91C_MC_ABTTYP_DATAW ((unsigned int) 0x1 << 10) // (MC) Data Write -#define AT91C_MC_ABTTYP_FETCH ((unsigned int) 0x2 << 10) // (MC) Code Fetch -#define AT91C_MC_MST0 ((unsigned int) 0x1 << 16) // (MC) Master 0 Abort Source -#define AT91C_MC_MST1 ((unsigned int) 0x1 << 17) // (MC) Master 1 Abort Source -#define AT91C_MC_SVMST0 ((unsigned int) 0x1 << 24) // (MC) Saved Master 0 Abort Source -#define AT91C_MC_SVMST1 ((unsigned int) 0x1 << 25) // (MC) Saved Master 1 Abort Source -// -------- MC_FMR : (MC Offset: 0x60) MC Flash Mode Register -------- -#define AT91C_MC_FRDY ((unsigned int) 0x1 << 0) // (MC) Flash Ready -#define AT91C_MC_LOCKE ((unsigned int) 0x1 << 2) // (MC) Lock Error -#define AT91C_MC_PROGE ((unsigned int) 0x1 << 3) // (MC) Programming Error -#define AT91C_MC_NEBP ((unsigned int) 0x1 << 7) // (MC) No Erase Before Programming -#define AT91C_MC_FWS ((unsigned int) 0x3 << 8) // (MC) Flash Wait State -#define AT91C_MC_FWS_0FWS ((unsigned int) 0x0 << 8) // (MC) 1 cycle for Read, 2 for Write operations -#define AT91C_MC_FWS_1FWS ((unsigned int) 0x1 << 8) // (MC) 2 cycles for Read, 3 for Write operations -#define AT91C_MC_FWS_2FWS ((unsigned int) 0x2 << 8) // (MC) 3 cycles for Read, 4 for Write operations -#define AT91C_MC_FWS_3FWS ((unsigned int) 0x3 << 8) // (MC) 4 cycles for Read, 4 for Write operations -#define AT91C_MC_FMCN ((unsigned int) 0xFF << 16) // (MC) Flash Microsecond Cycle Number -// -------- MC_FCR : (MC Offset: 0x64) MC Flash Command Register -------- -#define AT91C_MC_FCMD ((unsigned int) 0xF << 0) // (MC) Flash Command -#define AT91C_MC_FCMD_START_PROG ((unsigned int) 0x1) // (MC) Starts the programming of th epage specified by PAGEN. -#define AT91C_MC_FCMD_LOCK ((unsigned int) 0x2) // (MC) Starts a lock sequence of the sector defined by the bits 4 to 7 of the field PAGEN. -#define AT91C_MC_FCMD_PROG_AND_LOCK ((unsigned int) 0x3) // (MC) The lock sequence automatically happens after the programming sequence is completed. -#define AT91C_MC_FCMD_UNLOCK ((unsigned int) 0x4) // (MC) Starts an unlock sequence of the sector defined by the bits 4 to 7 of the field PAGEN. -#define AT91C_MC_FCMD_ERASE_ALL ((unsigned int) 0x8) // (MC) Starts the erase of the entire flash.If at least a page is locked, the command is cancelled. -#define AT91C_MC_FCMD_SET_GP_NVM ((unsigned int) 0xB) // (MC) Set General Purpose NVM bits. -#define AT91C_MC_FCMD_CLR_GP_NVM ((unsigned int) 0xD) // (MC) Clear General Purpose NVM bits. -#define AT91C_MC_FCMD_SET_SECURITY ((unsigned int) 0xF) // (MC) Set Security Bit. -#define AT91C_MC_PAGEN ((unsigned int) 0x3FF << 8) // (MC) Page Number -#define AT91C_MC_KEY ((unsigned int) 0xFF << 24) // (MC) Writing Protect Key -// -------- MC_FSR : (MC Offset: 0x68) MC Flash Command Register -------- -#define AT91C_MC_SECURITY ((unsigned int) 0x1 << 4) // (MC) Security Bit Status -#define AT91C_MC_GPNVM0 ((unsigned int) 0x1 << 8) // (MC) Sector 0 Lock Status -#define AT91C_MC_GPNVM1 ((unsigned int) 0x1 << 9) // (MC) Sector 1 Lock Status -#define AT91C_MC_GPNVM2 ((unsigned int) 0x1 << 10) // (MC) Sector 2 Lock Status -#define AT91C_MC_GPNVM3 ((unsigned int) 0x1 << 11) // (MC) Sector 3 Lock Status -#define AT91C_MC_GPNVM4 ((unsigned int) 0x1 << 12) // (MC) Sector 4 Lock Status -#define AT91C_MC_GPNVM5 ((unsigned int) 0x1 << 13) // (MC) Sector 5 Lock Status -#define AT91C_MC_GPNVM6 ((unsigned int) 0x1 << 14) // (MC) Sector 6 Lock Status -#define AT91C_MC_GPNVM7 ((unsigned int) 0x1 << 15) // (MC) Sector 7 Lock Status -#define AT91C_MC_LOCKS0 ((unsigned int) 0x1 << 16) // (MC) Sector 0 Lock Status -#define AT91C_MC_LOCKS1 ((unsigned int) 0x1 << 17) // (MC) Sector 1 Lock Status -#define AT91C_MC_LOCKS2 ((unsigned int) 0x1 << 18) // (MC) Sector 2 Lock Status -#define AT91C_MC_LOCKS3 ((unsigned int) 0x1 << 19) // (MC) Sector 3 Lock Status -#define AT91C_MC_LOCKS4 ((unsigned int) 0x1 << 20) // (MC) Sector 4 Lock Status -#define AT91C_MC_LOCKS5 ((unsigned int) 0x1 << 21) // (MC) Sector 5 Lock Status -#define AT91C_MC_LOCKS6 ((unsigned int) 0x1 << 22) // (MC) Sector 6 Lock Status -#define AT91C_MC_LOCKS7 ((unsigned int) 0x1 << 23) // (MC) Sector 7 Lock Status -#define AT91C_MC_LOCKS8 ((unsigned int) 0x1 << 24) // (MC) Sector 8 Lock Status -#define AT91C_MC_LOCKS9 ((unsigned int) 0x1 << 25) // (MC) Sector 9 Lock Status -#define AT91C_MC_LOCKS10 ((unsigned int) 0x1 << 26) // (MC) Sector 10 Lock Status -#define AT91C_MC_LOCKS11 ((unsigned int) 0x1 << 27) // (MC) Sector 11 Lock Status -#define AT91C_MC_LOCKS12 ((unsigned int) 0x1 << 28) // (MC) Sector 12 Lock Status -#define AT91C_MC_LOCKS13 ((unsigned int) 0x1 << 29) // (MC) Sector 13 Lock Status -#define AT91C_MC_LOCKS14 ((unsigned int) 0x1 << 30) // (MC) Sector 14 Lock Status -#define AT91C_MC_LOCKS15 ((unsigned int) 0x1 << 31) // (MC) Sector 15 Lock Status - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Serial Parallel Interface -// ***************************************************************************** -typedef struct _AT91S_SPI { - AT91_REG SPI_CR; // Control Register - AT91_REG SPI_MR; // Mode Register - AT91_REG SPI_RDR; // Receive Data Register - AT91_REG SPI_TDR; // Transmit Data Register - AT91_REG SPI_SR; // Status Register - AT91_REG SPI_IER; // Interrupt Enable Register - AT91_REG SPI_IDR; // Interrupt Disable Register - AT91_REG SPI_IMR; // Interrupt Mask Register - AT91_REG Reserved0[4]; // - AT91_REG SPI_CSR[4]; // Chip Select Register - AT91_REG Reserved1[48]; // - AT91_REG SPI_RPR; // Receive Pointer Register - AT91_REG SPI_RCR; // Receive Counter Register - AT91_REG SPI_TPR; // Transmit Pointer Register - AT91_REG SPI_TCR; // Transmit Counter Register - AT91_REG SPI_RNPR; // Receive Next Pointer Register - AT91_REG SPI_RNCR; // Receive Next Counter Register - AT91_REG SPI_TNPR; // Transmit Next Pointer Register - AT91_REG SPI_TNCR; // Transmit Next Counter Register - AT91_REG SPI_PTCR; // PDC Transfer Control Register - AT91_REG SPI_PTSR; // PDC Transfer Status Register -} AT91S_SPI, *AT91PS_SPI; - -// -------- SPI_CR : (SPI Offset: 0x0) SPI Control Register -------- -#define AT91C_SPI_SPIEN ((unsigned int) 0x1 << 0) // (SPI) SPI Enable -#define AT91C_SPI_SPIDIS ((unsigned int) 0x1 << 1) // (SPI) SPI Disable -#define AT91C_SPI_SWRST ((unsigned int) 0x1 << 7) // (SPI) SPI Software reset -#define AT91C_SPI_LASTXFER ((unsigned int) 0x1 << 24) // (SPI) SPI Last Transfer -// -------- SPI_MR : (SPI Offset: 0x4) SPI Mode Register -------- -#define AT91C_SPI_MSTR ((unsigned int) 0x1 << 0) // (SPI) Master/Slave Mode -#define AT91C_SPI_PS ((unsigned int) 0x1 << 1) // (SPI) Peripheral Select -#define AT91C_SPI_PS_FIXED ((unsigned int) 0x0 << 1) // (SPI) Fixed Peripheral Select -#define AT91C_SPI_PS_VARIABLE ((unsigned int) 0x1 << 1) // (SPI) Variable Peripheral Select -#define AT91C_SPI_PCSDEC ((unsigned int) 0x1 << 2) // (SPI) Chip Select Decode -#define AT91C_SPI_FDIV ((unsigned int) 0x1 << 3) // (SPI) Clock Selection -#define AT91C_SPI_MODFDIS ((unsigned int) 0x1 << 4) // (SPI) Mode Fault Detection -#define AT91C_SPI_LLB ((unsigned int) 0x1 << 7) // (SPI) Clock Selection -#define AT91C_SPI_PCS ((unsigned int) 0xF << 16) // (SPI) Peripheral Chip Select -#define AT91C_SPI_DLYBCS ((unsigned int) 0xFF << 24) // (SPI) Delay Between Chip Selects -// -------- SPI_RDR : (SPI Offset: 0x8) Receive Data Register -------- -#define AT91C_SPI_RD ((unsigned int) 0xFFFF << 0) // (SPI) Receive Data -#define AT91C_SPI_RPCS ((unsigned int) 0xF << 16) // (SPI) Peripheral Chip Select Status -// -------- SPI_TDR : (SPI Offset: 0xc) Transmit Data Register -------- -#define AT91C_SPI_TD ((unsigned int) 0xFFFF << 0) // (SPI) Transmit Data -#define AT91C_SPI_TPCS ((unsigned int) 0xF << 16) // (SPI) Peripheral Chip Select Status -// -------- SPI_SR : (SPI Offset: 0x10) Status Register -------- -#define AT91C_SPI_RDRF ((unsigned int) 0x1 << 0) // (SPI) Receive Data Register Full -#define AT91C_SPI_TDRE ((unsigned int) 0x1 << 1) // (SPI) Transmit Data Register Empty -#define AT91C_SPI_MODF ((unsigned int) 0x1 << 2) // (SPI) Mode Fault Error -#define AT91C_SPI_OVRES ((unsigned int) 0x1 << 3) // (SPI) Overrun Error Status -#define AT91C_SPI_ENDRX ((unsigned int) 0x1 << 4) // (SPI) End of Receiver Transfer -#define AT91C_SPI_ENDTX ((unsigned int) 0x1 << 5) // (SPI) End of Receiver Transfer -#define AT91C_SPI_RXBUFF ((unsigned int) 0x1 << 6) // (SPI) RXBUFF Interrupt -#define AT91C_SPI_TXBUFE ((unsigned int) 0x1 << 7) // (SPI) TXBUFE Interrupt -#define AT91C_SPI_NSSR ((unsigned int) 0x1 << 8) // (SPI) NSSR Interrupt -#define AT91C_SPI_TXEMPTY ((unsigned int) 0x1 << 9) // (SPI) TXEMPTY Interrupt -#define AT91C_SPI_SPIENS ((unsigned int) 0x1 << 16) // (SPI) Enable Status -// -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register -------- -// -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register -------- -// -------- SPI_IMR : (SPI Offset: 0x1c) Interrupt Mask Register -------- -// -------- SPI_CSR : (SPI Offset: 0x30) Chip Select Register -------- -#define AT91C_SPI_CPOL ((unsigned int) 0x1 << 0) // (SPI) Clock Polarity -#define AT91C_SPI_NCPHA ((unsigned int) 0x1 << 1) // (SPI) Clock Phase -#define AT91C_SPI_CSAAT ((unsigned int) 0x1 << 3) // (SPI) Chip Select Active After Transfer -#define AT91C_SPI_BITS ((unsigned int) 0xF << 4) // (SPI) Bits Per Transfer -#define AT91C_SPI_BITS_8 ((unsigned int) 0x0 << 4) // (SPI) 8 Bits Per transfer -#define AT91C_SPI_BITS_9 ((unsigned int) 0x1 << 4) // (SPI) 9 Bits Per transfer -#define AT91C_SPI_BITS_10 ((unsigned int) 0x2 << 4) // (SPI) 10 Bits Per transfer -#define AT91C_SPI_BITS_11 ((unsigned int) 0x3 << 4) // (SPI) 11 Bits Per transfer -#define AT91C_SPI_BITS_12 ((unsigned int) 0x4 << 4) // (SPI) 12 Bits Per transfer -#define AT91C_SPI_BITS_13 ((unsigned int) 0x5 << 4) // (SPI) 13 Bits Per transfer -#define AT91C_SPI_BITS_14 ((unsigned int) 0x6 << 4) // (SPI) 14 Bits Per transfer -#define AT91C_SPI_BITS_15 ((unsigned int) 0x7 << 4) // (SPI) 15 Bits Per transfer -#define AT91C_SPI_BITS_16 ((unsigned int) 0x8 << 4) // (SPI) 16 Bits Per transfer -#define AT91C_SPI_SCBR ((unsigned int) 0xFF << 8) // (SPI) Serial Clock Baud Rate -#define AT91C_SPI_DLYBS ((unsigned int) 0xFF << 16) // (SPI) Delay Before SPCK -#define AT91C_SPI_DLYBCT ((unsigned int) 0xFF << 24) // (SPI) Delay Between Consecutive Transfers - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Usart -// ***************************************************************************** -typedef struct _AT91S_USART { - AT91_REG US_CR; // Control Register - AT91_REG US_MR; // Mode Register - AT91_REG US_IER; // Interrupt Enable Register - AT91_REG US_IDR; // Interrupt Disable Register - AT91_REG US_IMR; // Interrupt Mask Register - AT91_REG US_CSR; // Channel Status Register - AT91_REG US_RHR; // Receiver Holding Register - AT91_REG US_THR; // Transmitter Holding Register - AT91_REG US_BRGR; // Baud Rate Generator Register - AT91_REG US_RTOR; // Receiver Time-out Register - AT91_REG US_TTGR; // Transmitter Time-guard Register - AT91_REG Reserved0[5]; // - AT91_REG US_FIDI; // FI_DI_Ratio Register - AT91_REG US_NER; // Nb Errors Register - AT91_REG Reserved1[1]; // - AT91_REG US_IF; // IRDA_FILTER Register - AT91_REG Reserved2[44]; // - AT91_REG US_RPR; // Receive Pointer Register - AT91_REG US_RCR; // Receive Counter Register - AT91_REG US_TPR; // Transmit Pointer Register - AT91_REG US_TCR; // Transmit Counter Register - AT91_REG US_RNPR; // Receive Next Pointer Register - AT91_REG US_RNCR; // Receive Next Counter Register - AT91_REG US_TNPR; // Transmit Next Pointer Register - AT91_REG US_TNCR; // Transmit Next Counter Register - AT91_REG US_PTCR; // PDC Transfer Control Register - AT91_REG US_PTSR; // PDC Transfer Status Register -} AT91S_USART, *AT91PS_USART; - -// -------- US_CR : (USART Offset: 0x0) Debug Unit Control Register -------- -#define AT91C_US_STTBRK ((unsigned int) 0x1 << 9) // (USART) Start Break -#define AT91C_US_STPBRK ((unsigned int) 0x1 << 10) // (USART) Stop Break -#define AT91C_US_STTTO ((unsigned int) 0x1 << 11) // (USART) Start Time-out -#define AT91C_US_SENDA ((unsigned int) 0x1 << 12) // (USART) Send Address -#define AT91C_US_RSTIT ((unsigned int) 0x1 << 13) // (USART) Reset Iterations -#define AT91C_US_RSTNACK ((unsigned int) 0x1 << 14) // (USART) Reset Non Acknowledge -#define AT91C_US_RETTO ((unsigned int) 0x1 << 15) // (USART) Rearm Time-out -#define AT91C_US_DTREN ((unsigned int) 0x1 << 16) // (USART) Data Terminal ready Enable -#define AT91C_US_DTRDIS ((unsigned int) 0x1 << 17) // (USART) Data Terminal ready Disable -#define AT91C_US_RTSEN ((unsigned int) 0x1 << 18) // (USART) Request to Send enable -#define AT91C_US_RTSDIS ((unsigned int) 0x1 << 19) // (USART) Request to Send Disable -// -------- US_MR : (USART Offset: 0x4) Debug Unit Mode Register -------- -#define AT91C_US_USMODE ((unsigned int) 0xF << 0) // (USART) Usart mode -#define AT91C_US_USMODE_NORMAL ((unsigned int) 0x0) // (USART) Normal -#define AT91C_US_USMODE_RS485 ((unsigned int) 0x1) // (USART) RS485 -#define AT91C_US_USMODE_HWHSH ((unsigned int) 0x2) // (USART) Hardware Handshaking -#define AT91C_US_USMODE_MODEM ((unsigned int) 0x3) // (USART) Modem -#define AT91C_US_USMODE_ISO7816_0 ((unsigned int) 0x4) // (USART) ISO7816 protocol: T = 0 -#define AT91C_US_USMODE_ISO7816_1 ((unsigned int) 0x6) // (USART) ISO7816 protocol: T = 1 -#define AT91C_US_USMODE_IRDA ((unsigned int) 0x8) // (USART) IrDA -#define AT91C_US_USMODE_SWHSH ((unsigned int) 0xC) // (USART) Software Handshaking -#define AT91C_US_CLKS ((unsigned int) 0x3 << 4) // (USART) Clock Selection (Baud Rate generator Input Clock -#define AT91C_US_CLKS_CLOCK ((unsigned int) 0x0 << 4) // (USART) Clock -#define AT91C_US_CLKS_FDIV1 ((unsigned int) 0x1 << 4) // (USART) fdiv1 -#define AT91C_US_CLKS_SLOW ((unsigned int) 0x2 << 4) // (USART) slow_clock (ARM) -#define AT91C_US_CLKS_EXT ((unsigned int) 0x3 << 4) // (USART) External (SCK) -#define AT91C_US_CHRL ((unsigned int) 0x3 << 6) // (USART) Clock Selection (Baud Rate generator Input Clock -#define AT91C_US_CHRL_5_BITS ((unsigned int) 0x0 << 6) // (USART) Character Length: 5 bits -#define AT91C_US_CHRL_6_BITS ((unsigned int) 0x1 << 6) // (USART) Character Length: 6 bits -#define AT91C_US_CHRL_7_BITS ((unsigned int) 0x2 << 6) // (USART) Character Length: 7 bits -#define AT91C_US_CHRL_8_BITS ((unsigned int) 0x3 << 6) // (USART) Character Length: 8 bits -#define AT91C_US_SYNC ((unsigned int) 0x1 << 8) // (USART) Synchronous Mode Select -#define AT91C_US_NBSTOP ((unsigned int) 0x3 << 12) // (USART) Number of Stop bits -#define AT91C_US_NBSTOP_1_BIT ((unsigned int) 0x0 << 12) // (USART) 1 stop bit -#define AT91C_US_NBSTOP_15_BIT ((unsigned int) 0x1 << 12) // (USART) Asynchronous (SYNC=0) 2 stop bits Synchronous (SYNC=1) 2 stop bits -#define AT91C_US_NBSTOP_2_BIT ((unsigned int) 0x2 << 12) // (USART) 2 stop bits -#define AT91C_US_MSBF ((unsigned int) 0x1 << 16) // (USART) Bit Order -#define AT91C_US_MODE9 ((unsigned int) 0x1 << 17) // (USART) 9-bit Character length -#define AT91C_US_CKLO ((unsigned int) 0x1 << 18) // (USART) Clock Output Select -#define AT91C_US_OVER ((unsigned int) 0x1 << 19) // (USART) Over Sampling Mode -#define AT91C_US_INACK ((unsigned int) 0x1 << 20) // (USART) Inhibit Non Acknowledge -#define AT91C_US_DSNACK ((unsigned int) 0x1 << 21) // (USART) Disable Successive NACK -#define AT91C_US_MAX_ITER ((unsigned int) 0x1 << 24) // (USART) Number of Repetitions -#define AT91C_US_FILTER ((unsigned int) 0x1 << 28) // (USART) Receive Line Filter -// -------- US_IER : (USART Offset: 0x8) Debug Unit Interrupt Enable Register -------- -#define AT91C_US_RXBRK ((unsigned int) 0x1 << 2) // (USART) Break Received/End of Break -#define AT91C_US_TIMEOUT ((unsigned int) 0x1 << 8) // (USART) Receiver Time-out -#define AT91C_US_ITERATION ((unsigned int) 0x1 << 10) // (USART) Max number of Repetitions Reached -#define AT91C_US_NACK ((unsigned int) 0x1 << 13) // (USART) Non Acknowledge -#define AT91C_US_RIIC ((unsigned int) 0x1 << 16) // (USART) Ring INdicator Input Change Flag -#define AT91C_US_DSRIC ((unsigned int) 0x1 << 17) // (USART) Data Set Ready Input Change Flag -#define AT91C_US_DCDIC ((unsigned int) 0x1 << 18) // (USART) Data Carrier Flag -#define AT91C_US_CTSIC ((unsigned int) 0x1 << 19) // (USART) Clear To Send Input Change Flag -// -------- US_IDR : (USART Offset: 0xc) Debug Unit Interrupt Disable Register -------- -// -------- US_IMR : (USART Offset: 0x10) Debug Unit Interrupt Mask Register -------- -// -------- US_CSR : (USART Offset: 0x14) Debug Unit Channel Status Register -------- -#define AT91C_US_RI ((unsigned int) 0x1 << 20) // (USART) Image of RI Input -#define AT91C_US_DSR ((unsigned int) 0x1 << 21) // (USART) Image of DSR Input -#define AT91C_US_DCD ((unsigned int) 0x1 << 22) // (USART) Image of DCD Input -#define AT91C_US_CTS ((unsigned int) 0x1 << 23) // (USART) Image of CTS Input - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Synchronous Serial Controller Interface -// ***************************************************************************** -typedef struct _AT91S_SSC { - AT91_REG SSC_CR; // Control Register - AT91_REG SSC_CMR; // Clock Mode Register - AT91_REG Reserved0[2]; // - AT91_REG SSC_RCMR; // Receive Clock ModeRegister - AT91_REG SSC_RFMR; // Receive Frame Mode Register - AT91_REG SSC_TCMR; // Transmit Clock Mode Register - AT91_REG SSC_TFMR; // Transmit Frame Mode Register - AT91_REG SSC_RHR; // Receive Holding Register - AT91_REG SSC_THR; // Transmit Holding Register - AT91_REG Reserved1[2]; // - AT91_REG SSC_RSHR; // Receive Sync Holding Register - AT91_REG SSC_TSHR; // Transmit Sync Holding Register - AT91_REG Reserved2[2]; // - AT91_REG SSC_SR; // Status Register - AT91_REG SSC_IER; // Interrupt Enable Register - AT91_REG SSC_IDR; // Interrupt Disable Register - AT91_REG SSC_IMR; // Interrupt Mask Register - AT91_REG Reserved3[44]; // - AT91_REG SSC_RPR; // Receive Pointer Register - AT91_REG SSC_RCR; // Receive Counter Register - AT91_REG SSC_TPR; // Transmit Pointer Register - AT91_REG SSC_TCR; // Transmit Counter Register - AT91_REG SSC_RNPR; // Receive Next Pointer Register - AT91_REG SSC_RNCR; // Receive Next Counter Register - AT91_REG SSC_TNPR; // Transmit Next Pointer Register - AT91_REG SSC_TNCR; // Transmit Next Counter Register - AT91_REG SSC_PTCR; // PDC Transfer Control Register - AT91_REG SSC_PTSR; // PDC Transfer Status Register -} AT91S_SSC, *AT91PS_SSC; - -// -------- SSC_CR : (SSC Offset: 0x0) SSC Control Register -------- -#define AT91C_SSC_RXEN ((unsigned int) 0x1 << 0) // (SSC) Receive Enable -#define AT91C_SSC_RXDIS ((unsigned int) 0x1 << 1) // (SSC) Receive Disable -#define AT91C_SSC_TXEN ((unsigned int) 0x1 << 8) // (SSC) Transmit Enable -#define AT91C_SSC_TXDIS ((unsigned int) 0x1 << 9) // (SSC) Transmit Disable -#define AT91C_SSC_SWRST ((unsigned int) 0x1 << 15) // (SSC) Software Reset -// -------- SSC_RCMR : (SSC Offset: 0x10) SSC Receive Clock Mode Register -------- -#define AT91C_SSC_CKS ((unsigned int) 0x3 << 0) // (SSC) Receive/Transmit Clock Selection -#define AT91C_SSC_CKS_DIV ((unsigned int) 0x0) // (SSC) Divided Clock -#define AT91C_SSC_CKS_TK ((unsigned int) 0x1) // (SSC) TK Clock signal -#define AT91C_SSC_CKS_RK ((unsigned int) 0x2) // (SSC) RK pin -#define AT91C_SSC_CKO ((unsigned int) 0x7 << 2) // (SSC) Receive/Transmit Clock Output Mode Selection -#define AT91C_SSC_CKO_NONE ((unsigned int) 0x0 << 2) // (SSC) Receive/Transmit Clock Output Mode: None RK pin: Input-only -#define AT91C_SSC_CKO_CONTINOUS ((unsigned int) 0x1 << 2) // (SSC) Continuous Receive/Transmit Clock RK pin: Output -#define AT91C_SSC_CKO_DATA_TX ((unsigned int) 0x2 << 2) // (SSC) Receive/Transmit Clock only during data transfers RK pin: Output -#define AT91C_SSC_CKI ((unsigned int) 0x1 << 5) // (SSC) Receive/Transmit Clock Inversion -#define AT91C_SSC_START ((unsigned int) 0xF << 8) // (SSC) Receive/Transmit Start Selection -#define AT91C_SSC_START_CONTINOUS ((unsigned int) 0x0 << 8) // (SSC) Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data. -#define AT91C_SSC_START_TX ((unsigned int) 0x1 << 8) // (SSC) Transmit/Receive start -#define AT91C_SSC_START_LOW_RF ((unsigned int) 0x2 << 8) // (SSC) Detection of a low level on RF input -#define AT91C_SSC_START_HIGH_RF ((unsigned int) 0x3 << 8) // (SSC) Detection of a high level on RF input -#define AT91C_SSC_START_FALL_RF ((unsigned int) 0x4 << 8) // (SSC) Detection of a falling edge on RF input -#define AT91C_SSC_START_RISE_RF ((unsigned int) 0x5 << 8) // (SSC) Detection of a rising edge on RF input -#define AT91C_SSC_START_LEVEL_RF ((unsigned int) 0x6 << 8) // (SSC) Detection of any level change on RF input -#define AT91C_SSC_START_EDGE_RF ((unsigned int) 0x7 << 8) // (SSC) Detection of any edge on RF input -#define AT91C_SSC_START_0 ((unsigned int) 0x8 << 8) // (SSC) Compare 0 -#define AT91C_SSC_STTDLY ((unsigned int) 0xFF << 16) // (SSC) Receive/Transmit Start Delay -#define AT91C_SSC_PERIOD ((unsigned int) 0xFF << 24) // (SSC) Receive/Transmit Period Divider Selection -// -------- SSC_RFMR : (SSC Offset: 0x14) SSC Receive Frame Mode Register -------- -#define AT91C_SSC_DATLEN ((unsigned int) 0x1F << 0) // (SSC) Data Length -#define AT91C_SSC_LOOP ((unsigned int) 0x1 << 5) // (SSC) Loop Mode -#define AT91C_SSC_MSBF ((unsigned int) 0x1 << 7) // (SSC) Most Significant Bit First -#define AT91C_SSC_DATNB ((unsigned int) 0xF << 8) // (SSC) Data Number per Frame -#define AT91C_SSC_FSLEN ((unsigned int) 0xF << 16) // (SSC) Receive/Transmit Frame Sync length -#define AT91C_SSC_FSOS ((unsigned int) 0x7 << 20) // (SSC) Receive/Transmit Frame Sync Output Selection -#define AT91C_SSC_FSOS_NONE ((unsigned int) 0x0 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: None RK pin Input-only -#define AT91C_SSC_FSOS_NEGATIVE ((unsigned int) 0x1 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Negative Pulse -#define AT91C_SSC_FSOS_POSITIVE ((unsigned int) 0x2 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Positive Pulse -#define AT91C_SSC_FSOS_LOW ((unsigned int) 0x3 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver Low during data transfer -#define AT91C_SSC_FSOS_HIGH ((unsigned int) 0x4 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver High during data transfer -#define AT91C_SSC_FSOS_TOGGLE ((unsigned int) 0x5 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Toggling at each start of data transfer -#define AT91C_SSC_FSEDGE ((unsigned int) 0x1 << 24) // (SSC) Frame Sync Edge Detection -// -------- SSC_TCMR : (SSC Offset: 0x18) SSC Transmit Clock Mode Register -------- -// -------- SSC_TFMR : (SSC Offset: 0x1c) SSC Transmit Frame Mode Register -------- -#define AT91C_SSC_DATDEF ((unsigned int) 0x1 << 5) // (SSC) Data Default Value -#define AT91C_SSC_FSDEN ((unsigned int) 0x1 << 23) // (SSC) Frame Sync Data Enable -// -------- SSC_SR : (SSC Offset: 0x40) SSC Status Register -------- -#define AT91C_SSC_TXRDY ((unsigned int) 0x1 << 0) // (SSC) Transmit Ready -#define AT91C_SSC_TXEMPTY ((unsigned int) 0x1 << 1) // (SSC) Transmit Empty -#define AT91C_SSC_ENDTX ((unsigned int) 0x1 << 2) // (SSC) End Of Transmission -#define AT91C_SSC_TXBUFE ((unsigned int) 0x1 << 3) // (SSC) Transmit Buffer Empty -#define AT91C_SSC_RXRDY ((unsigned int) 0x1 << 4) // (SSC) Receive Ready -#define AT91C_SSC_OVRUN ((unsigned int) 0x1 << 5) // (SSC) Receive Overrun -#define AT91C_SSC_ENDRX ((unsigned int) 0x1 << 6) // (SSC) End of Reception -#define AT91C_SSC_RXBUFF ((unsigned int) 0x1 << 7) // (SSC) Receive Buffer Full -#define AT91C_SSC_TXSYN ((unsigned int) 0x1 << 10) // (SSC) Transmit Sync -#define AT91C_SSC_RXSYN ((unsigned int) 0x1 << 11) // (SSC) Receive Sync -#define AT91C_SSC_TXENA ((unsigned int) 0x1 << 16) // (SSC) Transmit Enable -#define AT91C_SSC_RXENA ((unsigned int) 0x1 << 17) // (SSC) Receive Enable -// -------- SSC_IER : (SSC Offset: 0x44) SSC Interrupt Enable Register -------- -// -------- SSC_IDR : (SSC Offset: 0x48) SSC Interrupt Disable Register -------- -// -------- SSC_IMR : (SSC Offset: 0x4c) SSC Interrupt Mask Register -------- - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Two-wire Interface -// ***************************************************************************** -typedef struct _AT91S_TWI { - AT91_REG TWI_CR; // Control Register - AT91_REG TWI_MMR; // Master Mode Register - AT91_REG Reserved0[1]; // - AT91_REG TWI_IADR; // Internal Address Register - AT91_REG TWI_CWGR; // Clock Waveform Generator Register - AT91_REG Reserved1[3]; // - AT91_REG TWI_SR; // Status Register - AT91_REG TWI_IER; // Interrupt Enable Register - AT91_REG TWI_IDR; // Interrupt Disable Register - AT91_REG TWI_IMR; // Interrupt Mask Register - AT91_REG TWI_RHR; // Receive Holding Register - AT91_REG TWI_THR; // Transmit Holding Register -} AT91S_TWI, *AT91PS_TWI; - -// -------- TWI_CR : (TWI Offset: 0x0) TWI Control Register -------- -#define AT91C_TWI_START ((unsigned int) 0x1 << 0) // (TWI) Send a START Condition -#define AT91C_TWI_STOP ((unsigned int) 0x1 << 1) // (TWI) Send a STOP Condition -#define AT91C_TWI_MSEN ((unsigned int) 0x1 << 2) // (TWI) TWI Master Transfer Enabled -#define AT91C_TWI_MSDIS ((unsigned int) 0x1 << 3) // (TWI) TWI Master Transfer Disabled -#define AT91C_TWI_SWRST ((unsigned int) 0x1 << 7) // (TWI) Software Reset -// -------- TWI_MMR : (TWI Offset: 0x4) TWI Master Mode Register -------- -#define AT91C_TWI_IADRSZ ((unsigned int) 0x3 << 8) // (TWI) Internal Device Address Size -#define AT91C_TWI_IADRSZ_NO ((unsigned int) 0x0 << 8) // (TWI) No internal device address -#define AT91C_TWI_IADRSZ_1_BYTE ((unsigned int) 0x1 << 8) // (TWI) One-byte internal device address -#define AT91C_TWI_IADRSZ_2_BYTE ((unsigned int) 0x2 << 8) // (TWI) Two-byte internal device address -#define AT91C_TWI_IADRSZ_3_BYTE ((unsigned int) 0x3 << 8) // (TWI) Three-byte internal device address -#define AT91C_TWI_MREAD ((unsigned int) 0x1 << 12) // (TWI) Master Read Direction -#define AT91C_TWI_DADR ((unsigned int) 0x7F << 16) // (TWI) Device Address -// -------- TWI_CWGR : (TWI Offset: 0x10) TWI Clock Waveform Generator Register -------- -#define AT91C_TWI_CLDIV ((unsigned int) 0xFF << 0) // (TWI) Clock Low Divider -#define AT91C_TWI_CHDIV ((unsigned int) 0xFF << 8) // (TWI) Clock High Divider -#define AT91C_TWI_CKDIV ((unsigned int) 0x7 << 16) // (TWI) Clock Divider -// -------- TWI_SR : (TWI Offset: 0x20) TWI Status Register -------- -#define AT91C_TWI_TXCOMP ((unsigned int) 0x1 << 0) // (TWI) Transmission Completed -#define AT91C_TWI_RXRDY ((unsigned int) 0x1 << 1) // (TWI) Receive holding register ReaDY -#define AT91C_TWI_TXRDY ((unsigned int) 0x1 << 2) // (TWI) Transmit holding register ReaDY -#define AT91C_TWI_OVRE ((unsigned int) 0x1 << 6) // (TWI) Overrun Error -#define AT91C_TWI_UNRE ((unsigned int) 0x1 << 7) // (TWI) Underrun Error -#define AT91C_TWI_NACK ((unsigned int) 0x1 << 8) // (TWI) Not Acknowledged -// -------- TWI_IER : (TWI Offset: 0x24) TWI Interrupt Enable Register -------- -// -------- TWI_IDR : (TWI Offset: 0x28) TWI Interrupt Disable Register -------- -// -------- TWI_IMR : (TWI Offset: 0x2c) TWI Interrupt Mask Register -------- - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR PWMC Channel Interface -// ***************************************************************************** -typedef struct _AT91S_PWMC_CH { - AT91_REG PWMC_CMR; // Channel Mode Register - AT91_REG PWMC_CDTYR; // Channel Duty Cycle Register - AT91_REG PWMC_CPRDR; // Channel Period Register - AT91_REG PWMC_CCNTR; // Channel Counter Register - AT91_REG PWMC_CUPDR; // Channel Update Register - AT91_REG PWMC_Reserved[3]; // Reserved -} AT91S_PWMC_CH, *AT91PS_PWMC_CH; - -// -------- PWMC_CMR : (PWMC_CH Offset: 0x0) PWMC Channel Mode Register -------- -#define AT91C_PWMC_CPRE ((unsigned int) 0xF << 0) // (PWMC_CH) Channel Pre-scaler : PWMC_CLKx -#define AT91C_PWMC_CPRE_MCK ((unsigned int) 0x0) // (PWMC_CH) -#define AT91C_PWMC_CPRE_MCKA ((unsigned int) 0xB) // (PWMC_CH) -#define AT91C_PWMC_CPRE_MCKB ((unsigned int) 0xC) // (PWMC_CH) -#define AT91C_PWMC_CALG ((unsigned int) 0x1 << 8) // (PWMC_CH) Channel Alignment -#define AT91C_PWMC_CPOL ((unsigned int) 0x1 << 9) // (PWMC_CH) Channel Polarity -#define AT91C_PWMC_CPD ((unsigned int) 0x1 << 10) // (PWMC_CH) Channel Update Period -// -------- PWMC_CDTYR : (PWMC_CH Offset: 0x4) PWMC Channel Duty Cycle Register -------- -#define AT91C_PWMC_CDTY ((unsigned int) 0x0 << 0) // (PWMC_CH) Channel Duty Cycle -// -------- PWMC_CPRDR : (PWMC_CH Offset: 0x8) PWMC Channel Period Register -------- -#define AT91C_PWMC_CPRD ((unsigned int) 0x0 << 0) // (PWMC_CH) Channel Period -// -------- PWMC_CCNTR : (PWMC_CH Offset: 0xc) PWMC Channel Counter Register -------- -#define AT91C_PWMC_CCNT ((unsigned int) 0x0 << 0) // (PWMC_CH) Channel Counter -// -------- PWMC_CUPDR : (PWMC_CH Offset: 0x10) PWMC Channel Update Register -------- -#define AT91C_PWMC_CUPD ((unsigned int) 0x0 << 0) // (PWMC_CH) Channel Update - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Pulse Width Modulation Controller Interface -// ***************************************************************************** -typedef struct _AT91S_PWMC { - AT91_REG PWMC_MR; // PWMC Mode Register - AT91_REG PWMC_ENA; // PWMC Enable Register - AT91_REG PWMC_DIS; // PWMC Disable Register - AT91_REG PWMC_SR; // PWMC Status Register - AT91_REG PWMC_IER; // PWMC Interrupt Enable Register - AT91_REG PWMC_IDR; // PWMC Interrupt Disable Register - AT91_REG PWMC_IMR; // PWMC Interrupt Mask Register - AT91_REG PWMC_ISR; // PWMC Interrupt Status Register - AT91_REG Reserved0[55]; // - AT91_REG PWMC_VR; // PWMC Version Register - AT91_REG Reserved1[64]; // - AT91S_PWMC_CH PWMC_CH[4]; // PWMC Channel -} AT91S_PWMC, *AT91PS_PWMC; - -// -------- PWMC_MR : (PWMC Offset: 0x0) PWMC Mode Register -------- -#define AT91C_PWMC_DIVA ((unsigned int) 0xFF << 0) // (PWMC) CLKA divide factor. -#define AT91C_PWMC_PREA ((unsigned int) 0xF << 8) // (PWMC) Divider Input Clock Prescaler A -#define AT91C_PWMC_PREA_MCK ((unsigned int) 0x0 << 8) // (PWMC) -#define AT91C_PWMC_DIVB ((unsigned int) 0xFF << 16) // (PWMC) CLKB divide factor. -#define AT91C_PWMC_PREB ((unsigned int) 0xF << 24) // (PWMC) Divider Input Clock Prescaler B -#define AT91C_PWMC_PREB_MCK ((unsigned int) 0x0 << 24) // (PWMC) -// -------- PWMC_ENA : (PWMC Offset: 0x4) PWMC Enable Register -------- -#define AT91C_PWMC_CHID0 ((unsigned int) 0x1 << 0) // (PWMC) Channel ID 0 -#define AT91C_PWMC_CHID1 ((unsigned int) 0x1 << 1) // (PWMC) Channel ID 1 -#define AT91C_PWMC_CHID2 ((unsigned int) 0x1 << 2) // (PWMC) Channel ID 2 -#define AT91C_PWMC_CHID3 ((unsigned int) 0x1 << 3) // (PWMC) Channel ID 3 -// -------- PWMC_DIS : (PWMC Offset: 0x8) PWMC Disable Register -------- -// -------- PWMC_SR : (PWMC Offset: 0xc) PWMC Status Register -------- -// -------- PWMC_IER : (PWMC Offset: 0x10) PWMC Interrupt Enable Register -------- -// -------- PWMC_IDR : (PWMC Offset: 0x14) PWMC Interrupt Disable Register -------- -// -------- PWMC_IMR : (PWMC Offset: 0x18) PWMC Interrupt Mask Register -------- -// -------- PWMC_ISR : (PWMC Offset: 0x1c) PWMC Interrupt Status Register -------- - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR USB Device Interface -// ***************************************************************************** -typedef struct _AT91S_UDP { - AT91_REG UDP_NUM; // Frame Number Register - AT91_REG UDP_GLBSTATE; // Global State Register - AT91_REG UDP_FADDR; // Function Address Register - AT91_REG Reserved0[1]; // - AT91_REG UDP_IER; // Interrupt Enable Register - AT91_REG UDP_IDR; // Interrupt Disable Register - AT91_REG UDP_IMR; // Interrupt Mask Register - AT91_REG UDP_ISR; // Interrupt Status Register - AT91_REG UDP_ICR; // Interrupt Clear Register - AT91_REG Reserved1[1]; // - AT91_REG UDP_RSTEP; // Reset Endpoint Register - AT91_REG Reserved2[1]; // - AT91_REG UDP_CSR[6]; // Endpoint Control and Status Register - AT91_REG Reserved3[2]; // - AT91_REG UDP_FDR[6]; // Endpoint FIFO Data Register - AT91_REG Reserved4[3]; // - AT91_REG UDP_TXVC; // Transceiver Control Register -} AT91S_UDP, *AT91PS_UDP; - -// -------- UDP_FRM_NUM : (UDP Offset: 0x0) USB Frame Number Register -------- -#define AT91C_UDP_FRM_NUM ((unsigned int) 0x7FF << 0) // (UDP) Frame Number as Defined in the Packet Field Formats -#define AT91C_UDP_FRM_ERR ((unsigned int) 0x1 << 16) // (UDP) Frame Error -#define AT91C_UDP_FRM_OK ((unsigned int) 0x1 << 17) // (UDP) Frame OK -// -------- UDP_GLB_STATE : (UDP Offset: 0x4) USB Global State Register -------- -#define AT91C_UDP_FADDEN ((unsigned int) 0x1 << 0) // (UDP) Function Address Enable -#define AT91C_UDP_CONFG ((unsigned int) 0x1 << 1) // (UDP) Configured -#define AT91C_UDP_ESR ((unsigned int) 0x1 << 2) // (UDP) Enable Send Resume -#define AT91C_UDP_RSMINPR ((unsigned int) 0x1 << 3) // (UDP) A Resume Has Been Sent to the Host -#define AT91C_UDP_RMWUPE ((unsigned int) 0x1 << 4) // (UDP) Remote Wake Up Enable -// -------- UDP_FADDR : (UDP Offset: 0x8) USB Function Address Register -------- -#define AT91C_UDP_FADD ((unsigned int) 0xFF << 0) // (UDP) Function Address Value -#define AT91C_UDP_FEN ((unsigned int) 0x1 << 8) // (UDP) Function Enable -// -------- UDP_IER : (UDP Offset: 0x10) USB Interrupt Enable Register -------- -#define AT91C_UDP_EPINT0 ((unsigned int) 0x1 << 0) // (UDP) Endpoint 0 Interrupt -#define AT91C_UDP_EPINT1 ((unsigned int) 0x1 << 1) // (UDP) Endpoint 0 Interrupt -#define AT91C_UDP_EPINT2 ((unsigned int) 0x1 << 2) // (UDP) Endpoint 2 Interrupt -#define AT91C_UDP_EPINT3 ((unsigned int) 0x1 << 3) // (UDP) Endpoint 3 Interrupt -#define AT91C_UDP_EPINT4 ((unsigned int) 0x1 << 4) // (UDP) Endpoint 4 Interrupt -#define AT91C_UDP_EPINT5 ((unsigned int) 0x1 << 5) // (UDP) Endpoint 5 Interrupt -#define AT91C_UDP_RXSUSP ((unsigned int) 0x1 << 8) // (UDP) USB Suspend Interrupt -#define AT91C_UDP_RXRSM ((unsigned int) 0x1 << 9) // (UDP) USB Resume Interrupt -#define AT91C_UDP_EXTRSM ((unsigned int) 0x1 << 10) // (UDP) USB External Resume Interrupt -#define AT91C_UDP_SOFINT ((unsigned int) 0x1 << 11) // (UDP) USB Start Of frame Interrupt -#define AT91C_UDP_WAKEUP ((unsigned int) 0x1 << 13) // (UDP) USB Resume Interrupt -// -------- UDP_IDR : (UDP Offset: 0x14) USB Interrupt Disable Register -------- -// -------- UDP_IMR : (UDP Offset: 0x18) USB Interrupt Mask Register -------- -// -------- UDP_ISR : (UDP Offset: 0x1c) USB Interrupt Status Register -------- -#define AT91C_UDP_ENDBUSRES ((unsigned int) 0x1 << 12) // (UDP) USB End Of Bus Reset Interrupt -// -------- UDP_ICR : (UDP Offset: 0x20) USB Interrupt Clear Register -------- -// -------- UDP_RST_EP : (UDP Offset: 0x28) USB Reset Endpoint Register -------- -#define AT91C_UDP_EP0 ((unsigned int) 0x1 << 0) // (UDP) Reset Endpoint 0 -#define AT91C_UDP_EP1 ((unsigned int) 0x1 << 1) // (UDP) Reset Endpoint 1 -#define AT91C_UDP_EP2 ((unsigned int) 0x1 << 2) // (UDP) Reset Endpoint 2 -#define AT91C_UDP_EP3 ((unsigned int) 0x1 << 3) // (UDP) Reset Endpoint 3 -#define AT91C_UDP_EP4 ((unsigned int) 0x1 << 4) // (UDP) Reset Endpoint 4 -#define AT91C_UDP_EP5 ((unsigned int) 0x1 << 5) // (UDP) Reset Endpoint 5 -// -------- UDP_CSR : (UDP Offset: 0x30) USB Endpoint Control and Status Register -------- -#define AT91C_UDP_TXCOMP ((unsigned int) 0x1 << 0) // (UDP) Generates an IN packet with data previously written in the DPR -#define AT91C_UDP_RX_DATA_BK0 ((unsigned int) 0x1 << 1) // (UDP) Receive Data Bank 0 -#define AT91C_UDP_RXSETUP ((unsigned int) 0x1 << 2) // (UDP) Sends STALL to the Host (Control endpoints) -#define AT91C_UDP_ISOERROR ((unsigned int) 0x1 << 3) // (UDP) Isochronous error (Isochronous endpoints) -#define AT91C_UDP_TXPKTRDY ((unsigned int) 0x1 << 4) // (UDP) Transmit Packet Ready -#define AT91C_UDP_FORCESTALL ((unsigned int) 0x1 << 5) // (UDP) Force Stall (used by Control, Bulk and Isochronous endpoints). -#define AT91C_UDP_RX_DATA_BK1 ((unsigned int) 0x1 << 6) // (UDP) Receive Data Bank 1 (only used by endpoints with ping-pong attributes). -#define AT91C_UDP_DIR ((unsigned int) 0x1 << 7) // (UDP) Transfer Direction -#define AT91C_UDP_EPTYPE ((unsigned int) 0x7 << 8) // (UDP) Endpoint type -#define AT91C_UDP_EPTYPE_CTRL ((unsigned int) 0x0 << 8) // (UDP) Control -#define AT91C_UDP_EPTYPE_ISO_OUT ((unsigned int) 0x1 << 8) // (UDP) Isochronous OUT -#define AT91C_UDP_EPTYPE_BULK_OUT ((unsigned int) 0x2 << 8) // (UDP) Bulk OUT -#define AT91C_UDP_EPTYPE_INT_OUT ((unsigned int) 0x3 << 8) // (UDP) Interrupt OUT -#define AT91C_UDP_EPTYPE_ISO_IN ((unsigned int) 0x5 << 8) // (UDP) Isochronous IN -#define AT91C_UDP_EPTYPE_BULK_IN ((unsigned int) 0x6 << 8) // (UDP) Bulk IN -#define AT91C_UDP_EPTYPE_INT_IN ((unsigned int) 0x7 << 8) // (UDP) Interrupt IN -#define AT91C_UDP_DTGLE ((unsigned int) 0x1 << 11) // (UDP) Data Toggle -#define AT91C_UDP_EPEDS ((unsigned int) 0x1 << 15) // (UDP) Endpoint Enable Disable -#define AT91C_UDP_RXBYTECNT ((unsigned int) 0x7FF << 16) // (UDP) Number Of Bytes Available in the FIFO -// -------- UDP_TXVC : (UDP Offset: 0x74) Transceiver Control Register -------- -#define AT91C_UDP_TXVDIS ((unsigned int) 0x1 << 8) // (UDP) -#define AT91C_UDP_PUON ((unsigned int) 0x1 << 9) // (UDP) Pull-up ON - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Timer Counter Channel Interface -// ***************************************************************************** -typedef struct _AT91S_TC { - AT91_REG TC_CCR; // Channel Control Register - AT91_REG TC_CMR; // Channel Mode Register (Capture Mode / Waveform Mode) - AT91_REG Reserved0[2]; // - AT91_REG TC_CV; // Counter Value - AT91_REG TC_RA; // Register A - AT91_REG TC_RB; // Register B - AT91_REG TC_RC; // Register C - AT91_REG TC_SR; // Status Register - AT91_REG TC_IER; // Interrupt Enable Register - AT91_REG TC_IDR; // Interrupt Disable Register - AT91_REG TC_IMR; // Interrupt Mask Register -} AT91S_TC, *AT91PS_TC; - -// -------- TC_CCR : (TC Offset: 0x0) TC Channel Control Register -------- -#define AT91C_TC_CLKEN ((unsigned int) 0x1 << 0) // (TC) Counter Clock Enable Command -#define AT91C_TC_CLKDIS ((unsigned int) 0x1 << 1) // (TC) Counter Clock Disable Command -#define AT91C_TC_SWTRG ((unsigned int) 0x1 << 2) // (TC) Software Trigger Command -// -------- TC_CMR : (TC Offset: 0x4) TC Channel Mode Register: Capture Mode / Waveform Mode -------- -#define AT91C_TC_CLKS ((unsigned int) 0x7 << 0) // (TC) Clock Selection -#define AT91C_TC_CLKS_TIMER_DIV1_CLOCK ((unsigned int) 0x0) // (TC) Clock selected: TIMER_DIV1_CLOCK -#define AT91C_TC_CLKS_TIMER_DIV2_CLOCK ((unsigned int) 0x1) // (TC) Clock selected: TIMER_DIV2_CLOCK -#define AT91C_TC_CLKS_TIMER_DIV3_CLOCK ((unsigned int) 0x2) // (TC) Clock selected: TIMER_DIV3_CLOCK -#define AT91C_TC_CLKS_TIMER_DIV4_CLOCK ((unsigned int) 0x3) // (TC) Clock selected: TIMER_DIV4_CLOCK -#define AT91C_TC_CLKS_TIMER_DIV5_CLOCK ((unsigned int) 0x4) // (TC) Clock selected: TIMER_DIV5_CLOCK -#define AT91C_TC_CLKS_XC0 ((unsigned int) 0x5) // (TC) Clock selected: XC0 -#define AT91C_TC_CLKS_XC1 ((unsigned int) 0x6) // (TC) Clock selected: XC1 -#define AT91C_TC_CLKS_XC2 ((unsigned int) 0x7) // (TC) Clock selected: XC2 -#define AT91C_TC_CLKI ((unsigned int) 0x1 << 3) // (TC) Clock Invert -#define AT91C_TC_BURST ((unsigned int) 0x3 << 4) // (TC) Burst Signal Selection -#define AT91C_TC_BURST_NONE ((unsigned int) 0x0 << 4) // (TC) The clock is not gated by an external signal -#define AT91C_TC_BURST_XC0 ((unsigned int) 0x1 << 4) // (TC) XC0 is ANDed with the selected clock -#define AT91C_TC_BURST_XC1 ((unsigned int) 0x2 << 4) // (TC) XC1 is ANDed with the selected clock -#define AT91C_TC_BURST_XC2 ((unsigned int) 0x3 << 4) // (TC) XC2 is ANDed with the selected clock -#define AT91C_TC_CPCSTOP ((unsigned int) 0x1 << 6) // (TC) Counter Clock Stopped with RC Compare -#define AT91C_TC_LDBSTOP ((unsigned int) 0x1 << 6) // (TC) Counter Clock Stopped with RB Loading -#define AT91C_TC_CPCDIS ((unsigned int) 0x1 << 7) // (TC) Counter Clock Disable with RC Compare -#define AT91C_TC_LDBDIS ((unsigned int) 0x1 << 7) // (TC) Counter Clock Disabled with RB Loading -#define AT91C_TC_ETRGEDG ((unsigned int) 0x3 << 8) // (TC) External Trigger Edge Selection -#define AT91C_TC_ETRGEDG_NONE ((unsigned int) 0x0 << 8) // (TC) Edge: None -#define AT91C_TC_ETRGEDG_RISING ((unsigned int) 0x1 << 8) // (TC) Edge: rising edge -#define AT91C_TC_ETRGEDG_FALLING ((unsigned int) 0x2 << 8) // (TC) Edge: falling edge -#define AT91C_TC_ETRGEDG_BOTH ((unsigned int) 0x3 << 8) // (TC) Edge: each edge -#define AT91C_TC_EEVTEDG ((unsigned int) 0x3 << 8) // (TC) External Event Edge Selection -#define AT91C_TC_EEVTEDG_NONE ((unsigned int) 0x0 << 8) // (TC) Edge: None -#define AT91C_TC_EEVTEDG_RISING ((unsigned int) 0x1 << 8) // (TC) Edge: rising edge -#define AT91C_TC_EEVTEDG_FALLING ((unsigned int) 0x2 << 8) // (TC) Edge: falling edge -#define AT91C_TC_EEVTEDG_BOTH ((unsigned int) 0x3 << 8) // (TC) Edge: each edge -#define AT91C_TC_EEVT ((unsigned int) 0x3 << 10) // (TC) External Event Selection -#define AT91C_TC_EEVT_TIOB ((unsigned int) 0x0 << 10) // (TC) Signal selected as external event: TIOB TIOB direction: input -#define AT91C_TC_EEVT_XC0 ((unsigned int) 0x1 << 10) // (TC) Signal selected as external event: XC0 TIOB direction: output -#define AT91C_TC_EEVT_XC1 ((unsigned int) 0x2 << 10) // (TC) Signal selected as external event: XC1 TIOB direction: output -#define AT91C_TC_EEVT_XC2 ((unsigned int) 0x3 << 10) // (TC) Signal selected as external event: XC2 TIOB direction: output -#define AT91C_TC_ABETRG ((unsigned int) 0x1 << 10) // (TC) TIOA or TIOB External Trigger Selection -#define AT91C_TC_ENETRG ((unsigned int) 0x1 << 12) // (TC) External Event Trigger enable -#define AT91C_TC_WAVESEL ((unsigned int) 0x3 << 13) // (TC) Waveform Selection -#define AT91C_TC_WAVESEL_UP ((unsigned int) 0x0 << 13) // (TC) UP mode without atomatic trigger on RC Compare -#define AT91C_TC_WAVESEL_UPDOWN ((unsigned int) 0x1 << 13) // (TC) UPDOWN mode without automatic trigger on RC Compare -#define AT91C_TC_WAVESEL_UP_AUTO ((unsigned int) 0x2 << 13) // (TC) UP mode with automatic trigger on RC Compare -#define AT91C_TC_WAVESEL_UPDOWN_AUTO ((unsigned int) 0x3 << 13) // (TC) UPDOWN mode with automatic trigger on RC Compare -#define AT91C_TC_CPCTRG ((unsigned int) 0x1 << 14) // (TC) RC Compare Trigger Enable -#define AT91C_TC_WAVE ((unsigned int) 0x1 << 15) // (TC) -#define AT91C_TC_ACPA ((unsigned int) 0x3 << 16) // (TC) RA Compare Effect on TIOA -#define AT91C_TC_ACPA_NONE ((unsigned int) 0x0 << 16) // (TC) Effect: none -#define AT91C_TC_ACPA_SET ((unsigned int) 0x1 << 16) // (TC) Effect: set -#define AT91C_TC_ACPA_CLEAR ((unsigned int) 0x2 << 16) // (TC) Effect: clear -#define AT91C_TC_ACPA_TOGGLE ((unsigned int) 0x3 << 16) // (TC) Effect: toggle -#define AT91C_TC_LDRA ((unsigned int) 0x3 << 16) // (TC) RA Loading Selection -#define AT91C_TC_LDRA_NONE ((unsigned int) 0x0 << 16) // (TC) Edge: None -#define AT91C_TC_LDRA_RISING ((unsigned int) 0x1 << 16) // (TC) Edge: rising edge of TIOA -#define AT91C_TC_LDRA_FALLING ((unsigned int) 0x2 << 16) // (TC) Edge: falling edge of TIOA -#define AT91C_TC_LDRA_BOTH ((unsigned int) 0x3 << 16) // (TC) Edge: each edge of TIOA -#define AT91C_TC_ACPC ((unsigned int) 0x3 << 18) // (TC) RC Compare Effect on TIOA -#define AT91C_TC_ACPC_NONE ((unsigned int) 0x0 << 18) // (TC) Effect: none -#define AT91C_TC_ACPC_SET ((unsigned int) 0x1 << 18) // (TC) Effect: set -#define AT91C_TC_ACPC_CLEAR ((unsigned int) 0x2 << 18) // (TC) Effect: clear -#define AT91C_TC_ACPC_TOGGLE ((unsigned int) 0x3 << 18) // (TC) Effect: toggle -#define AT91C_TC_LDRB ((unsigned int) 0x3 << 18) // (TC) RB Loading Selection -#define AT91C_TC_LDRB_NONE ((unsigned int) 0x0 << 18) // (TC) Edge: None -#define AT91C_TC_LDRB_RISING ((unsigned int) 0x1 << 18) // (TC) Edge: rising edge of TIOA -#define AT91C_TC_LDRB_FALLING ((unsigned int) 0x2 << 18) // (TC) Edge: falling edge of TIOA -#define AT91C_TC_LDRB_BOTH ((unsigned int) 0x3 << 18) // (TC) Edge: each edge of TIOA -#define AT91C_TC_AEEVT ((unsigned int) 0x3 << 20) // (TC) External Event Effect on TIOA -#define AT91C_TC_AEEVT_NONE ((unsigned int) 0x0 << 20) // (TC) Effect: none -#define AT91C_TC_AEEVT_SET ((unsigned int) 0x1 << 20) // (TC) Effect: set -#define AT91C_TC_AEEVT_CLEAR ((unsigned int) 0x2 << 20) // (TC) Effect: clear -#define AT91C_TC_AEEVT_TOGGLE ((unsigned int) 0x3 << 20) // (TC) Effect: toggle -#define AT91C_TC_ASWTRG ((unsigned int) 0x3 << 22) // (TC) Software Trigger Effect on TIOA -#define AT91C_TC_ASWTRG_NONE ((unsigned int) 0x0 << 22) // (TC) Effect: none -#define AT91C_TC_ASWTRG_SET ((unsigned int) 0x1 << 22) // (TC) Effect: set -#define AT91C_TC_ASWTRG_CLEAR ((unsigned int) 0x2 << 22) // (TC) Effect: clear -#define AT91C_TC_ASWTRG_TOGGLE ((unsigned int) 0x3 << 22) // (TC) Effect: toggle -#define AT91C_TC_BCPB ((unsigned int) 0x3 << 24) // (TC) RB Compare Effect on TIOB -#define AT91C_TC_BCPB_NONE ((unsigned int) 0x0 << 24) // (TC) Effect: none -#define AT91C_TC_BCPB_SET ((unsigned int) 0x1 << 24) // (TC) Effect: set -#define AT91C_TC_BCPB_CLEAR ((unsigned int) 0x2 << 24) // (TC) Effect: clear -#define AT91C_TC_BCPB_TOGGLE ((unsigned int) 0x3 << 24) // (TC) Effect: toggle -#define AT91C_TC_BCPC ((unsigned int) 0x3 << 26) // (TC) RC Compare Effect on TIOB -#define AT91C_TC_BCPC_NONE ((unsigned int) 0x0 << 26) // (TC) Effect: none -#define AT91C_TC_BCPC_SET ((unsigned int) 0x1 << 26) // (TC) Effect: set -#define AT91C_TC_BCPC_CLEAR ((unsigned int) 0x2 << 26) // (TC) Effect: clear -#define AT91C_TC_BCPC_TOGGLE ((unsigned int) 0x3 << 26) // (TC) Effect: toggle -#define AT91C_TC_BEEVT ((unsigned int) 0x3 << 28) // (TC) External Event Effect on TIOB -#define AT91C_TC_BEEVT_NONE ((unsigned int) 0x0 << 28) // (TC) Effect: none -#define AT91C_TC_BEEVT_SET ((unsigned int) 0x1 << 28) // (TC) Effect: set -#define AT91C_TC_BEEVT_CLEAR ((unsigned int) 0x2 << 28) // (TC) Effect: clear -#define AT91C_TC_BEEVT_TOGGLE ((unsigned int) 0x3 << 28) // (TC) Effect: toggle -#define AT91C_TC_BSWTRG ((unsigned int) 0x3 << 30) // (TC) Software Trigger Effect on TIOB -#define AT91C_TC_BSWTRG_NONE ((unsigned int) 0x0 << 30) // (TC) Effect: none -#define AT91C_TC_BSWTRG_SET ((unsigned int) 0x1 << 30) // (TC) Effect: set -#define AT91C_TC_BSWTRG_CLEAR ((unsigned int) 0x2 << 30) // (TC) Effect: clear -#define AT91C_TC_BSWTRG_TOGGLE ((unsigned int) 0x3 << 30) // (TC) Effect: toggle -// -------- TC_SR : (TC Offset: 0x20) TC Channel Status Register -------- -#define AT91C_TC_COVFS ((unsigned int) 0x1 << 0) // (TC) Counter Overflow -#define AT91C_TC_LOVRS ((unsigned int) 0x1 << 1) // (TC) Load Overrun -#define AT91C_TC_CPAS ((unsigned int) 0x1 << 2) // (TC) RA Compare -#define AT91C_TC_CPBS ((unsigned int) 0x1 << 3) // (TC) RB Compare -#define AT91C_TC_CPCS ((unsigned int) 0x1 << 4) // (TC) RC Compare -#define AT91C_TC_LDRAS ((unsigned int) 0x1 << 5) // (TC) RA Loading -#define AT91C_TC_LDRBS ((unsigned int) 0x1 << 6) // (TC) RB Loading -#define AT91C_TC_ETRGS ((unsigned int) 0x1 << 7) // (TC) External Trigger -#define AT91C_TC_CLKSTA ((unsigned int) 0x1 << 16) // (TC) Clock Enabling -#define AT91C_TC_MTIOA ((unsigned int) 0x1 << 17) // (TC) TIOA Mirror -#define AT91C_TC_MTIOB ((unsigned int) 0x1 << 18) // (TC) TIOA Mirror -// -------- TC_IER : (TC Offset: 0x24) TC Channel Interrupt Enable Register -------- -// -------- TC_IDR : (TC Offset: 0x28) TC Channel Interrupt Disable Register -------- -// -------- TC_IMR : (TC Offset: 0x2c) TC Channel Interrupt Mask Register -------- - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Timer Counter Interface -// ***************************************************************************** -typedef struct _AT91S_TCB { - AT91S_TC TCB_TC0; // TC Channel 0 - AT91_REG Reserved0[4]; // - AT91S_TC TCB_TC1; // TC Channel 1 - AT91_REG Reserved1[4]; // - AT91S_TC TCB_TC2; // TC Channel 2 - AT91_REG Reserved2[4]; // - AT91_REG TCB_BCR; // TC Block Control Register - AT91_REG TCB_BMR; // TC Block Mode Register -} AT91S_TCB, *AT91PS_TCB; - -// -------- TCB_BCR : (TCB Offset: 0xc0) TC Block Control Register -------- -#define AT91C_TCB_SYNC ((unsigned int) 0x1 << 0) // (TCB) Synchro Command -// -------- TCB_BMR : (TCB Offset: 0xc4) TC Block Mode Register -------- -#define AT91C_TCB_TC0XC0S ((unsigned int) 0x3 << 0) // (TCB) External Clock Signal 0 Selection -#define AT91C_TCB_TC0XC0S_TCLK0 ((unsigned int) 0x0) // (TCB) TCLK0 connected to XC0 -#define AT91C_TCB_TC0XC0S_NONE ((unsigned int) 0x1) // (TCB) None signal connected to XC0 -#define AT91C_TCB_TC0XC0S_TIOA1 ((unsigned int) 0x2) // (TCB) TIOA1 connected to XC0 -#define AT91C_TCB_TC0XC0S_TIOA2 ((unsigned int) 0x3) // (TCB) TIOA2 connected to XC0 -#define AT91C_TCB_TC1XC1S ((unsigned int) 0x3 << 2) // (TCB) External Clock Signal 1 Selection -#define AT91C_TCB_TC1XC1S_TCLK1 ((unsigned int) 0x0 << 2) // (TCB) TCLK1 connected to XC1 -#define AT91C_TCB_TC1XC1S_NONE ((unsigned int) 0x1 << 2) // (TCB) None signal connected to XC1 -#define AT91C_TCB_TC1XC1S_TIOA0 ((unsigned int) 0x2 << 2) // (TCB) TIOA0 connected to XC1 -#define AT91C_TCB_TC1XC1S_TIOA2 ((unsigned int) 0x3 << 2) // (TCB) TIOA2 connected to XC1 -#define AT91C_TCB_TC2XC2S ((unsigned int) 0x3 << 4) // (TCB) External Clock Signal 2 Selection -#define AT91C_TCB_TC2XC2S_TCLK2 ((unsigned int) 0x0 << 4) // (TCB) TCLK2 connected to XC2 -#define AT91C_TCB_TC2XC2S_NONE ((unsigned int) 0x1 << 4) // (TCB) None signal connected to XC2 -#define AT91C_TCB_TC2XC2S_TIOA0 ((unsigned int) 0x2 << 4) // (TCB) TIOA0 connected to XC2 -#define AT91C_TCB_TC2XC2S_TIOA1 ((unsigned int) 0x3 << 4) // (TCB) TIOA2 connected to XC2 - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Control Area Network MailBox Interface -// ***************************************************************************** -typedef struct _AT91S_CAN_MB { - AT91_REG CAN_MB_MMR; // MailBox Mode Register - AT91_REG CAN_MB_MAM; // MailBox Acceptance Mask Register - AT91_REG CAN_MB_MID; // MailBox ID Register - AT91_REG CAN_MB_MFID; // MailBox Family ID Register - AT91_REG CAN_MB_MSR; // MailBox Status Register - AT91_REG CAN_MB_MDL; // MailBox Data Low Register - AT91_REG CAN_MB_MDH; // MailBox Data High Register - AT91_REG CAN_MB_MCR; // MailBox Control Register -} AT91S_CAN_MB, *AT91PS_CAN_MB; - -// -------- CAN_MMR : (CAN_MB Offset: 0x0) CAN Message Mode Register -------- -#define AT91C_CAN_MTIMEMARK ((unsigned int) 0xFFFF << 0) // (CAN_MB) Mailbox Timemark -#define AT91C_CAN_PRIOR ((unsigned int) 0xF << 16) // (CAN_MB) Mailbox Priority -#define AT91C_CAN_MOT ((unsigned int) 0x7 << 24) // (CAN_MB) Mailbox Object Type -#define AT91C_CAN_MOT_DIS ((unsigned int) 0x0 << 24) // (CAN_MB) -#define AT91C_CAN_MOT_RX ((unsigned int) 0x1 << 24) // (CAN_MB) -#define AT91C_CAN_MOT_RXOVERWRITE ((unsigned int) 0x2 << 24) // (CAN_MB) -#define AT91C_CAN_MOT_TX ((unsigned int) 0x3 << 24) // (CAN_MB) -#define AT91C_CAN_MOT_CONSUMER ((unsigned int) 0x4 << 24) // (CAN_MB) -#define AT91C_CAN_MOT_PRODUCER ((unsigned int) 0x5 << 24) // (CAN_MB) -// -------- CAN_MAM : (CAN_MB Offset: 0x4) CAN Message Acceptance Mask Register -------- -#define AT91C_CAN_MIDvB ((unsigned int) 0x3FFFF << 0) // (CAN_MB) Complementary bits for identifier in extended mode -#define AT91C_CAN_MIDvA ((unsigned int) 0x7FF << 18) // (CAN_MB) Identifier for standard frame mode -#define AT91C_CAN_MIDE ((unsigned int) 0x1 << 29) // (CAN_MB) Identifier Version -// -------- CAN_MID : (CAN_MB Offset: 0x8) CAN Message ID Register -------- -// -------- CAN_MFID : (CAN_MB Offset: 0xc) CAN Message Family ID Register -------- -// -------- CAN_MSR : (CAN_MB Offset: 0x10) CAN Message Status Register -------- -#define AT91C_CAN_MTIMESTAMP ((unsigned int) 0xFFFF << 0) // (CAN_MB) Timer Value -#define AT91C_CAN_MDLC ((unsigned int) 0xF << 16) // (CAN_MB) Mailbox Data Length Code -#define AT91C_CAN_MRTR ((unsigned int) 0x1 << 20) // (CAN_MB) Mailbox Remote Transmission Request -#define AT91C_CAN_MABT ((unsigned int) 0x1 << 22) // (CAN_MB) Mailbox Message Abort -#define AT91C_CAN_MRDY ((unsigned int) 0x1 << 23) // (CAN_MB) Mailbox Ready -#define AT91C_CAN_MMI ((unsigned int) 0x1 << 24) // (CAN_MB) Mailbox Message Ignored -// -------- CAN_MDL : (CAN_MB Offset: 0x14) CAN Message Data Low Register -------- -// -------- CAN_MDH : (CAN_MB Offset: 0x18) CAN Message Data High Register -------- -// -------- CAN_MCR : (CAN_MB Offset: 0x1c) CAN Message Control Register -------- -#define AT91C_CAN_MACR ((unsigned int) 0x1 << 22) // (CAN_MB) Abort Request for Mailbox -#define AT91C_CAN_MTCR ((unsigned int) 0x1 << 23) // (CAN_MB) Mailbox Transfer Command - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Control Area Network Interface -// ***************************************************************************** -typedef struct _AT91S_CAN { - AT91_REG CAN_MR; // Mode Register - AT91_REG CAN_IER; // Interrupt Enable Register - AT91_REG CAN_IDR; // Interrupt Disable Register - AT91_REG CAN_IMR; // Interrupt Mask Register - AT91_REG CAN_SR; // Status Register - AT91_REG CAN_BR; // Baudrate Register - AT91_REG CAN_TIM; // Timer Register - AT91_REG CAN_TIMESTP; // Time Stamp Register - AT91_REG CAN_ECR; // Error Counter Register - AT91_REG CAN_TCR; // Transfer Command Register - AT91_REG CAN_ACR; // Abort Command Register - AT91_REG Reserved0[52]; // - AT91_REG CAN_VR; // Version Register - AT91_REG Reserved1[64]; // - AT91S_CAN_MB CAN_MB0; // CAN Mailbox 0 - AT91S_CAN_MB CAN_MB1; // CAN Mailbox 1 - AT91S_CAN_MB CAN_MB2; // CAN Mailbox 2 - AT91S_CAN_MB CAN_MB3; // CAN Mailbox 3 - AT91S_CAN_MB CAN_MB4; // CAN Mailbox 4 - AT91S_CAN_MB CAN_MB5; // CAN Mailbox 5 - AT91S_CAN_MB CAN_MB6; // CAN Mailbox 6 - AT91S_CAN_MB CAN_MB7; // CAN Mailbox 7 - AT91S_CAN_MB CAN_MB8; // CAN Mailbox 8 - AT91S_CAN_MB CAN_MB9; // CAN Mailbox 9 - AT91S_CAN_MB CAN_MB10; // CAN Mailbox 10 - AT91S_CAN_MB CAN_MB11; // CAN Mailbox 11 - AT91S_CAN_MB CAN_MB12; // CAN Mailbox 12 - AT91S_CAN_MB CAN_MB13; // CAN Mailbox 13 - AT91S_CAN_MB CAN_MB14; // CAN Mailbox 14 - AT91S_CAN_MB CAN_MB15; // CAN Mailbox 15 -} AT91S_CAN, *AT91PS_CAN; - -// -------- CAN_MR : (CAN Offset: 0x0) CAN Mode Register -------- -#define AT91C_CAN_CANEN ((unsigned int) 0x1 << 0) // (CAN) CAN Controller Enable -#define AT91C_CAN_LPM ((unsigned int) 0x1 << 1) // (CAN) Disable/Enable Low Power Mode -#define AT91C_CAN_ABM ((unsigned int) 0x1 << 2) // (CAN) Disable/Enable Autobaud/Listen Mode -#define AT91C_CAN_OVL ((unsigned int) 0x1 << 3) // (CAN) Disable/Enable Overload Frame -#define AT91C_CAN_TEOF ((unsigned int) 0x1 << 4) // (CAN) Time Stamp messages at each end of Frame -#define AT91C_CAN_TTM ((unsigned int) 0x1 << 5) // (CAN) Disable/Enable Time Trigger Mode -#define AT91C_CAN_TIMFRZ ((unsigned int) 0x1 << 6) // (CAN) Enable Timer Freeze -#define AT91C_CAN_DRPT ((unsigned int) 0x1 << 7) // (CAN) Disable Repeat -// -------- CAN_IER : (CAN Offset: 0x4) CAN Interrupt Enable Register -------- -#define AT91C_CAN_MB0 ((unsigned int) 0x1 << 0) // (CAN) Mailbox 0 Flag -#define AT91C_CAN_MB1 ((unsigned int) 0x1 << 1) // (CAN) Mailbox 1 Flag -#define AT91C_CAN_MB2 ((unsigned int) 0x1 << 2) // (CAN) Mailbox 2 Flag -#define AT91C_CAN_MB3 ((unsigned int) 0x1 << 3) // (CAN) Mailbox 3 Flag -#define AT91C_CAN_MB4 ((unsigned int) 0x1 << 4) // (CAN) Mailbox 4 Flag -#define AT91C_CAN_MB5 ((unsigned int) 0x1 << 5) // (CAN) Mailbox 5 Flag -#define AT91C_CAN_MB6 ((unsigned int) 0x1 << 6) // (CAN) Mailbox 6 Flag -#define AT91C_CAN_MB7 ((unsigned int) 0x1 << 7) // (CAN) Mailbox 7 Flag -#define AT91C_CAN_MB8 ((unsigned int) 0x1 << 8) // (CAN) Mailbox 8 Flag -#define AT91C_CAN_MB9 ((unsigned int) 0x1 << 9) // (CAN) Mailbox 9 Flag -#define AT91C_CAN_MB10 ((unsigned int) 0x1 << 10) // (CAN) Mailbox 10 Flag -#define AT91C_CAN_MB11 ((unsigned int) 0x1 << 11) // (CAN) Mailbox 11 Flag -#define AT91C_CAN_MB12 ((unsigned int) 0x1 << 12) // (CAN) Mailbox 12 Flag -#define AT91C_CAN_MB13 ((unsigned int) 0x1 << 13) // (CAN) Mailbox 13 Flag -#define AT91C_CAN_MB14 ((unsigned int) 0x1 << 14) // (CAN) Mailbox 14 Flag -#define AT91C_CAN_MB15 ((unsigned int) 0x1 << 15) // (CAN) Mailbox 15 Flag -#define AT91C_CAN_ERRA ((unsigned int) 0x1 << 16) // (CAN) Error Active Mode Flag -#define AT91C_CAN_WARN ((unsigned int) 0x1 << 17) // (CAN) Warning Limit Flag -#define AT91C_CAN_ERRP ((unsigned int) 0x1 << 18) // (CAN) Error Passive Mode Flag -#define AT91C_CAN_BOFF ((unsigned int) 0x1 << 19) // (CAN) Bus Off Mode Flag -#define AT91C_CAN_SLEEP ((unsigned int) 0x1 << 20) // (CAN) Sleep Flag -#define AT91C_CAN_WAKEUP ((unsigned int) 0x1 << 21) // (CAN) Wakeup Flag -#define AT91C_CAN_TOVF ((unsigned int) 0x1 << 22) // (CAN) Timer Overflow Flag -#define AT91C_CAN_TSTP ((unsigned int) 0x1 << 23) // (CAN) Timestamp Flag -#define AT91C_CAN_CERR ((unsigned int) 0x1 << 24) // (CAN) CRC Error -#define AT91C_CAN_SERR ((unsigned int) 0x1 << 25) // (CAN) Stuffing Error -#define AT91C_CAN_AERR ((unsigned int) 0x1 << 26) // (CAN) Acknowledgment Error -#define AT91C_CAN_FERR ((unsigned int) 0x1 << 27) // (CAN) Form Error -#define AT91C_CAN_BERR ((unsigned int) 0x1 << 28) // (CAN) Bit Error -// -------- CAN_IDR : (CAN Offset: 0x8) CAN Interrupt Disable Register -------- -// -------- CAN_IMR : (CAN Offset: 0xc) CAN Interrupt Mask Register -------- -// -------- CAN_SR : (CAN Offset: 0x10) CAN Status Register -------- -#define AT91C_CAN_RBSY ((unsigned int) 0x1 << 29) // (CAN) Receiver Busy -#define AT91C_CAN_TBSY ((unsigned int) 0x1 << 30) // (CAN) Transmitter Busy -#define AT91C_CAN_OVLY ((unsigned int) 0x1 << 31) // (CAN) Overload Busy -// -------- CAN_BR : (CAN Offset: 0x14) CAN Baudrate Register -------- -#define AT91C_CAN_PHASE2 ((unsigned int) 0x7 << 0) // (CAN) Phase 2 segment -#define AT91C_CAN_PHASE1 ((unsigned int) 0x7 << 4) // (CAN) Phase 1 segment -#define AT91C_CAN_PROPAG ((unsigned int) 0x7 << 8) // (CAN) Programmation time segment -#define AT91C_CAN_SYNC ((unsigned int) 0x3 << 12) // (CAN) Re-synchronization jump width segment -#define AT91C_CAN_BRP ((unsigned int) 0x7F << 16) // (CAN) Baudrate Prescaler -#define AT91C_CAN_SMP ((unsigned int) 0x1 << 24) // (CAN) Sampling mode -// -------- CAN_TIM : (CAN Offset: 0x18) CAN Timer Register -------- -#define AT91C_CAN_TIMER ((unsigned int) 0xFFFF << 0) // (CAN) Timer field -// -------- CAN_TIMESTP : (CAN Offset: 0x1c) CAN Timestamp Register -------- -// -------- CAN_ECR : (CAN Offset: 0x20) CAN Error Counter Register -------- -#define AT91C_CAN_REC ((unsigned int) 0xFF << 0) // (CAN) Receive Error Counter -#define AT91C_CAN_TEC ((unsigned int) 0xFF << 16) // (CAN) Transmit Error Counter -// -------- CAN_TCR : (CAN Offset: 0x24) CAN Transfer Command Register -------- -#define AT91C_CAN_TIMRST ((unsigned int) 0x1 << 31) // (CAN) Timer Reset Field -// -------- CAN_ACR : (CAN Offset: 0x28) CAN Abort Command Register -------- - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Ethernet MAC 10/100 -// ***************************************************************************** -typedef struct _AT91S_EMAC { - AT91_REG EMAC_NCR; // Network Control Register - AT91_REG EMAC_NCFGR; // Network Configuration Register - AT91_REG EMAC_NSR; // Network Status Register - AT91_REG Reserved0[2]; // - AT91_REG EMAC_TSR; // Transmit Status Register - AT91_REG EMAC_RBQP; // Receive Buffer Queue Pointer - AT91_REG EMAC_TBQP; // Transmit Buffer Queue Pointer - AT91_REG EMAC_RSR; // Receive Status Register - AT91_REG EMAC_ISR; // Interrupt Status Register - AT91_REG EMAC_IER; // Interrupt Enable Register - AT91_REG EMAC_IDR; // Interrupt Disable Register - AT91_REG EMAC_IMR; // Interrupt Mask Register - AT91_REG EMAC_MAN; // PHY Maintenance Register - AT91_REG EMAC_PTR; // Pause Time Register - AT91_REG EMAC_PFR; // Pause Frames received Register - AT91_REG EMAC_FTO; // Frames Transmitted OK Register - AT91_REG EMAC_SCF; // Single Collision Frame Register - AT91_REG EMAC_MCF; // Multiple Collision Frame Register - AT91_REG EMAC_FRO; // Frames Received OK Register - AT91_REG EMAC_FCSE; // Frame Check Sequence Error Register - AT91_REG EMAC_ALE; // Alignment Error Register - AT91_REG EMAC_DTF; // Deferred Transmission Frame Register - AT91_REG EMAC_LCOL; // Late Collision Register - AT91_REG EMAC_ECOL; // Excessive Collision Register - AT91_REG EMAC_TUND; // Transmit Underrun Error Register - AT91_REG EMAC_CSE; // Carrier Sense Error Register - AT91_REG EMAC_RRE; // Receive Ressource Error Register - AT91_REG EMAC_ROV; // Receive Overrun Errors Register - AT91_REG EMAC_RSE; // Receive Symbol Errors Register - AT91_REG EMAC_ELE; // Excessive Length Errors Register - AT91_REG EMAC_RJA; // Receive Jabbers Register - AT91_REG EMAC_USF; // Undersize Frames Register - AT91_REG EMAC_STE; // SQE Test Error Register - AT91_REG EMAC_RLE; // Receive Length Field Mismatch Register - AT91_REG EMAC_TPF; // Transmitted Pause Frames Register - AT91_REG EMAC_HRB; // Hash Address Bottom[31:0] - AT91_REG EMAC_HRT; // Hash Address Top[63:32] - AT91_REG EMAC_SA1L; // Specific Address 1 Bottom, First 4 bytes - AT91_REG EMAC_SA1H; // Specific Address 1 Top, Last 2 bytes - AT91_REG EMAC_SA2L; // Specific Address 2 Bottom, First 4 bytes - AT91_REG EMAC_SA2H; // Specific Address 2 Top, Last 2 bytes - AT91_REG EMAC_SA3L; // Specific Address 3 Bottom, First 4 bytes - AT91_REG EMAC_SA3H; // Specific Address 3 Top, Last 2 bytes - AT91_REG EMAC_SA4L; // Specific Address 4 Bottom, First 4 bytes - AT91_REG EMAC_SA4H; // Specific Address 4 Top, Last 2 bytes - AT91_REG EMAC_TID; // Type ID Checking Register - AT91_REG EMAC_TPQ; // Transmit Pause Quantum Register - AT91_REG EMAC_USRIO; // USER Input/Output Register - AT91_REG EMAC_WOL; // Wake On LAN Register - AT91_REG Reserved1[13]; // - AT91_REG EMAC_REV; // Revision Register -} AT91S_EMAC, *AT91PS_EMAC; - -// -------- EMAC_NCR : (EMAC Offset: 0x0) -------- -#define AT91C_EMAC_LB ((unsigned int) 0x1 << 0) // (EMAC) Loopback. Optional. When set, loopback signal is at high level. -#define AT91C_EMAC_LLB ((unsigned int) 0x1 << 1) // (EMAC) Loopback local. -#define AT91C_EMAC_RE ((unsigned int) 0x1 << 2) // (EMAC) Receive enable. -#define AT91C_EMAC_TE ((unsigned int) 0x1 << 3) // (EMAC) Transmit enable. -#define AT91C_EMAC_MPE ((unsigned int) 0x1 << 4) // (EMAC) Management port enable. -#define AT91C_EMAC_CLRSTAT ((unsigned int) 0x1 << 5) // (EMAC) Clear statistics registers. -#define AT91C_EMAC_INCSTAT ((unsigned int) 0x1 << 6) // (EMAC) Increment statistics registers. -#define AT91C_EMAC_WESTAT ((unsigned int) 0x1 << 7) // (EMAC) Write enable for statistics registers. -#define AT91C_EMAC_BP ((unsigned int) 0x1 << 8) // (EMAC) Back pressure. -#define AT91C_EMAC_TSTART ((unsigned int) 0x1 << 9) // (EMAC) Start Transmission. -#define AT91C_EMAC_THALT ((unsigned int) 0x1 << 10) // (EMAC) Transmission Halt. -#define AT91C_EMAC_TPFR ((unsigned int) 0x1 << 11) // (EMAC) Transmit pause frame -#define AT91C_EMAC_TZQ ((unsigned int) 0x1 << 12) // (EMAC) Transmit zero quantum pause frame -// -------- EMAC_NCFGR : (EMAC Offset: 0x4) Network Configuration Register -------- -#define AT91C_EMAC_SPD ((unsigned int) 0x1 << 0) // (EMAC) Speed. -#define AT91C_EMAC_FD ((unsigned int) 0x1 << 1) // (EMAC) Full duplex. -#define AT91C_EMAC_JFRAME ((unsigned int) 0x1 << 3) // (EMAC) Jumbo Frames. -#define AT91C_EMAC_CAF ((unsigned int) 0x1 << 4) // (EMAC) Copy all frames. -#define AT91C_EMAC_NBC ((unsigned int) 0x1 << 5) // (EMAC) No broadcast. -#define AT91C_EMAC_MTI ((unsigned int) 0x1 << 6) // (EMAC) Multicast hash event enable -#define AT91C_EMAC_UNI ((unsigned int) 0x1 << 7) // (EMAC) Unicast hash enable. -#define AT91C_EMAC_BIG ((unsigned int) 0x1 << 8) // (EMAC) Receive 1522 bytes. -#define AT91C_EMAC_EAE ((unsigned int) 0x1 << 9) // (EMAC) External address match enable. -#define AT91C_EMAC_CLK ((unsigned int) 0x3 << 10) // (EMAC) -#define AT91C_EMAC_CLK_HCLK_8 ((unsigned int) 0x0 << 10) // (EMAC) HCLK divided by 8 -#define AT91C_EMAC_CLK_HCLK_16 ((unsigned int) 0x1 << 10) // (EMAC) HCLK divided by 16 -#define AT91C_EMAC_CLK_HCLK_32 ((unsigned int) 0x2 << 10) // (EMAC) HCLK divided by 32 -#define AT91C_EMAC_CLK_HCLK_64 ((unsigned int) 0x3 << 10) // (EMAC) HCLK divided by 64 -#define AT91C_EMAC_RTY ((unsigned int) 0x1 << 12) // (EMAC) -#define AT91C_EMAC_PAE ((unsigned int) 0x1 << 13) // (EMAC) -#define AT91C_EMAC_RBOF ((unsigned int) 0x3 << 14) // (EMAC) -#define AT91C_EMAC_RBOF_OFFSET_0 ((unsigned int) 0x0 << 14) // (EMAC) no offset from start of receive buffer -#define AT91C_EMAC_RBOF_OFFSET_1 ((unsigned int) 0x1 << 14) // (EMAC) one byte offset from start of receive buffer -#define AT91C_EMAC_RBOF_OFFSET_2 ((unsigned int) 0x2 << 14) // (EMAC) two bytes offset from start of receive buffer -#define AT91C_EMAC_RBOF_OFFSET_3 ((unsigned int) 0x3 << 14) // (EMAC) three bytes offset from start of receive buffer -#define AT91C_EMAC_RLCE ((unsigned int) 0x1 << 16) // (EMAC) Receive Length field Checking Enable -#define AT91C_EMAC_DRFCS ((unsigned int) 0x1 << 17) // (EMAC) Discard Receive FCS -#define AT91C_EMAC_EFRHD ((unsigned int) 0x1 << 18) // (EMAC) -#define AT91C_EMAC_IRXFCS ((unsigned int) 0x1 << 19) // (EMAC) Ignore RX FCS -// -------- EMAC_NSR : (EMAC Offset: 0x8) Network Status Register -------- -#define AT91C_EMAC_LINKR ((unsigned int) 0x1 << 0) // (EMAC) -#define AT91C_EMAC_MDIO ((unsigned int) 0x1 << 1) // (EMAC) -#define AT91C_EMAC_IDLE ((unsigned int) 0x1 << 2) // (EMAC) -// -------- EMAC_TSR : (EMAC Offset: 0x14) Transmit Status Register -------- -#define AT91C_EMAC_UBR ((unsigned int) 0x1 << 0) // (EMAC) -#define AT91C_EMAC_COL ((unsigned int) 0x1 << 1) // (EMAC) -#define AT91C_EMAC_RLES ((unsigned int) 0x1 << 2) // (EMAC) -#define AT91C_EMAC_TGO ((unsigned int) 0x1 << 3) // (EMAC) Transmit Go -#define AT91C_EMAC_BEX ((unsigned int) 0x1 << 4) // (EMAC) Buffers exhausted mid frame -#define AT91C_EMAC_COMP ((unsigned int) 0x1 << 5) // (EMAC) -#define AT91C_EMAC_UND ((unsigned int) 0x1 << 6) // (EMAC) -// -------- EMAC_RSR : (EMAC Offset: 0x20) Receive Status Register -------- -#define AT91C_EMAC_BNA ((unsigned int) 0x1 << 0) // (EMAC) -#define AT91C_EMAC_REC ((unsigned int) 0x1 << 1) // (EMAC) -#define AT91C_EMAC_OVR ((unsigned int) 0x1 << 2) // (EMAC) -// -------- EMAC_ISR : (EMAC Offset: 0x24) Interrupt Status Register -------- -#define AT91C_EMAC_MFD ((unsigned int) 0x1 << 0) // (EMAC) -#define AT91C_EMAC_RCOMP ((unsigned int) 0x1 << 1) // (EMAC) -#define AT91C_EMAC_RXUBR ((unsigned int) 0x1 << 2) // (EMAC) -#define AT91C_EMAC_TXUBR ((unsigned int) 0x1 << 3) // (EMAC) -#define AT91C_EMAC_TUNDR ((unsigned int) 0x1 << 4) // (EMAC) -#define AT91C_EMAC_RLEX ((unsigned int) 0x1 << 5) // (EMAC) -#define AT91C_EMAC_TXERR ((unsigned int) 0x1 << 6) // (EMAC) -#define AT91C_EMAC_TCOMP ((unsigned int) 0x1 << 7) // (EMAC) -#define AT91C_EMAC_LINK ((unsigned int) 0x1 << 9) // (EMAC) -#define AT91C_EMAC_ROVR ((unsigned int) 0x1 << 10) // (EMAC) -#define AT91C_EMAC_HRESP ((unsigned int) 0x1 << 11) // (EMAC) -#define AT91C_EMAC_PFRE ((unsigned int) 0x1 << 12) // (EMAC) -#define AT91C_EMAC_PTZ ((unsigned int) 0x1 << 13) // (EMAC) -// -------- EMAC_IER : (EMAC Offset: 0x28) Interrupt Enable Register -------- -// -------- EMAC_IDR : (EMAC Offset: 0x2c) Interrupt Disable Register -------- -// -------- EMAC_IMR : (EMAC Offset: 0x30) Interrupt Mask Register -------- -// -------- EMAC_MAN : (EMAC Offset: 0x34) PHY Maintenance Register -------- -#define AT91C_EMAC_DATA ((unsigned int) 0xFFFF << 0) // (EMAC) -#define AT91C_EMAC_CODE ((unsigned int) 0x3 << 16) // (EMAC) -#define AT91C_EMAC_REGA ((unsigned int) 0x1F << 18) // (EMAC) -#define AT91C_EMAC_PHYA ((unsigned int) 0x1F << 23) // (EMAC) -#define AT91C_EMAC_RW ((unsigned int) 0x3 << 28) // (EMAC) -#define AT91C_EMAC_SOF ((unsigned int) 0x3 << 30) // (EMAC) -// -------- EMAC_USRIO : (EMAC Offset: 0xc0) USER Input Output Register -------- -#define AT91C_EMAC_RMII ((unsigned int) 0x1 << 0) // (EMAC) Reduce MII -// -------- EMAC_WOL : (EMAC Offset: 0xc4) Wake On LAN Register -------- -#define AT91C_EMAC_IP ((unsigned int) 0xFFFF << 0) // (EMAC) ARP request IP address -#define AT91C_EMAC_MAG ((unsigned int) 0x1 << 16) // (EMAC) Magic packet event enable -#define AT91C_EMAC_ARP ((unsigned int) 0x1 << 17) // (EMAC) ARP request event enable -#define AT91C_EMAC_SA1 ((unsigned int) 0x1 << 18) // (EMAC) Specific address register 1 event enable -// -------- EMAC_REV : (EMAC Offset: 0xfc) Revision Register -------- -#define AT91C_EMAC_REVREF ((unsigned int) 0xFFFF << 0) // (EMAC) -#define AT91C_EMAC_PARTREF ((unsigned int) 0xFFFF << 16) // (EMAC) - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Analog to Digital Convertor -// ***************************************************************************** -typedef struct _AT91S_ADC { - AT91_REG ADC_CR; // ADC Control Register - AT91_REG ADC_MR; // ADC Mode Register - AT91_REG Reserved0[2]; // - AT91_REG ADC_CHER; // ADC Channel Enable Register - AT91_REG ADC_CHDR; // ADC Channel Disable Register - AT91_REG ADC_CHSR; // ADC Channel Status Register - AT91_REG ADC_SR; // ADC Status Register - AT91_REG ADC_LCDR; // ADC Last Converted Data Register - AT91_REG ADC_IER; // ADC Interrupt Enable Register - AT91_REG ADC_IDR; // ADC Interrupt Disable Register - AT91_REG ADC_IMR; // ADC Interrupt Mask Register - AT91_REG ADC_CDR0; // ADC Channel Data Register 0 - AT91_REG ADC_CDR1; // ADC Channel Data Register 1 - AT91_REG ADC_CDR2; // ADC Channel Data Register 2 - AT91_REG ADC_CDR3; // ADC Channel Data Register 3 - AT91_REG ADC_CDR4; // ADC Channel Data Register 4 - AT91_REG ADC_CDR5; // ADC Channel Data Register 5 - AT91_REG ADC_CDR6; // ADC Channel Data Register 6 - AT91_REG ADC_CDR7; // ADC Channel Data Register 7 - AT91_REG Reserved1[44]; // - AT91_REG ADC_RPR; // Receive Pointer Register - AT91_REG ADC_RCR; // Receive Counter Register - AT91_REG ADC_TPR; // Transmit Pointer Register - AT91_REG ADC_TCR; // Transmit Counter Register - AT91_REG ADC_RNPR; // Receive Next Pointer Register - AT91_REG ADC_RNCR; // Receive Next Counter Register - AT91_REG ADC_TNPR; // Transmit Next Pointer Register - AT91_REG ADC_TNCR; // Transmit Next Counter Register - AT91_REG ADC_PTCR; // PDC Transfer Control Register - AT91_REG ADC_PTSR; // PDC Transfer Status Register -} AT91S_ADC, *AT91PS_ADC; - -// -------- ADC_CR : (ADC Offset: 0x0) ADC Control Register -------- -#define AT91C_ADC_SWRST ((unsigned int) 0x1 << 0) // (ADC) Software Reset -#define AT91C_ADC_START ((unsigned int) 0x1 << 1) // (ADC) Start Conversion -// -------- ADC_MR : (ADC Offset: 0x4) ADC Mode Register -------- -#define AT91C_ADC_TRGEN ((unsigned int) 0x1 << 0) // (ADC) Trigger Enable -#define AT91C_ADC_TRGEN_DIS ((unsigned int) 0x0) // (ADC) Hradware triggers are disabled. Starting a conversion is only possible by software -#define AT91C_ADC_TRGEN_EN ((unsigned int) 0x1) // (ADC) Hardware trigger selected by TRGSEL field is enabled. -#define AT91C_ADC_TRGSEL ((unsigned int) 0x7 << 1) // (ADC) Trigger Selection -#define AT91C_ADC_TRGSEL_TIOA0 ((unsigned int) 0x0 << 1) // (ADC) Selected TRGSEL = TIAO0 -#define AT91C_ADC_TRGSEL_TIOA1 ((unsigned int) 0x1 << 1) // (ADC) Selected TRGSEL = TIAO1 -#define AT91C_ADC_TRGSEL_TIOA2 ((unsigned int) 0x2 << 1) // (ADC) Selected TRGSEL = TIAO2 -#define AT91C_ADC_TRGSEL_TIOA3 ((unsigned int) 0x3 << 1) // (ADC) Selected TRGSEL = TIAO3 -#define AT91C_ADC_TRGSEL_TIOA4 ((unsigned int) 0x4 << 1) // (ADC) Selected TRGSEL = TIAO4 -#define AT91C_ADC_TRGSEL_TIOA5 ((unsigned int) 0x5 << 1) // (ADC) Selected TRGSEL = TIAO5 -#define AT91C_ADC_TRGSEL_EXT ((unsigned int) 0x6 << 1) // (ADC) Selected TRGSEL = External Trigger -#define AT91C_ADC_LOWRES ((unsigned int) 0x1 << 4) // (ADC) Resolution. -#define AT91C_ADC_LOWRES_10_BIT ((unsigned int) 0x0 << 4) // (ADC) 10-bit resolution -#define AT91C_ADC_LOWRES_8_BIT ((unsigned int) 0x1 << 4) // (ADC) 8-bit resolution -#define AT91C_ADC_SLEEP ((unsigned int) 0x1 << 5) // (ADC) Sleep Mode -#define AT91C_ADC_SLEEP_NORMAL_MODE ((unsigned int) 0x0 << 5) // (ADC) Normal Mode -#define AT91C_ADC_SLEEP_MODE ((unsigned int) 0x1 << 5) // (ADC) Sleep Mode -#define AT91C_ADC_PRESCAL ((unsigned int) 0x3F << 8) // (ADC) Prescaler rate selection -#define AT91C_ADC_STARTUP ((unsigned int) 0x1F << 16) // (ADC) Startup Time -#define AT91C_ADC_SHTIM ((unsigned int) 0xF << 24) // (ADC) Sample & Hold Time -// -------- ADC_CHER : (ADC Offset: 0x10) ADC Channel Enable Register -------- -#define AT91C_ADC_CH0 ((unsigned int) 0x1 << 0) // (ADC) Channel 0 -#define AT91C_ADC_CH1 ((unsigned int) 0x1 << 1) // (ADC) Channel 1 -#define AT91C_ADC_CH2 ((unsigned int) 0x1 << 2) // (ADC) Channel 2 -#define AT91C_ADC_CH3 ((unsigned int) 0x1 << 3) // (ADC) Channel 3 -#define AT91C_ADC_CH4 ((unsigned int) 0x1 << 4) // (ADC) Channel 4 -#define AT91C_ADC_CH5 ((unsigned int) 0x1 << 5) // (ADC) Channel 5 -#define AT91C_ADC_CH6 ((unsigned int) 0x1 << 6) // (ADC) Channel 6 -#define AT91C_ADC_CH7 ((unsigned int) 0x1 << 7) // (ADC) Channel 7 -// -------- ADC_CHDR : (ADC Offset: 0x14) ADC Channel Disable Register -------- -// -------- ADC_CHSR : (ADC Offset: 0x18) ADC Channel Status Register -------- -// -------- ADC_SR : (ADC Offset: 0x1c) ADC Status Register -------- -#define AT91C_ADC_EOC0 ((unsigned int) 0x1 << 0) // (ADC) End of Conversion -#define AT91C_ADC_EOC1 ((unsigned int) 0x1 << 1) // (ADC) End of Conversion -#define AT91C_ADC_EOC2 ((unsigned int) 0x1 << 2) // (ADC) End of Conversion -#define AT91C_ADC_EOC3 ((unsigned int) 0x1 << 3) // (ADC) End of Conversion -#define AT91C_ADC_EOC4 ((unsigned int) 0x1 << 4) // (ADC) End of Conversion -#define AT91C_ADC_EOC5 ((unsigned int) 0x1 << 5) // (ADC) End of Conversion -#define AT91C_ADC_EOC6 ((unsigned int) 0x1 << 6) // (ADC) End of Conversion -#define AT91C_ADC_EOC7 ((unsigned int) 0x1 << 7) // (ADC) End of Conversion -#define AT91C_ADC_OVRE0 ((unsigned int) 0x1 << 8) // (ADC) Overrun Error -#define AT91C_ADC_OVRE1 ((unsigned int) 0x1 << 9) // (ADC) Overrun Error -#define AT91C_ADC_OVRE2 ((unsigned int) 0x1 << 10) // (ADC) Overrun Error -#define AT91C_ADC_OVRE3 ((unsigned int) 0x1 << 11) // (ADC) Overrun Error -#define AT91C_ADC_OVRE4 ((unsigned int) 0x1 << 12) // (ADC) Overrun Error -#define AT91C_ADC_OVRE5 ((unsigned int) 0x1 << 13) // (ADC) Overrun Error -#define AT91C_ADC_OVRE6 ((unsigned int) 0x1 << 14) // (ADC) Overrun Error -#define AT91C_ADC_OVRE7 ((unsigned int) 0x1 << 15) // (ADC) Overrun Error -#define AT91C_ADC_DRDY ((unsigned int) 0x1 << 16) // (ADC) Data Ready -#define AT91C_ADC_GOVRE ((unsigned int) 0x1 << 17) // (ADC) General Overrun -#define AT91C_ADC_ENDRX ((unsigned int) 0x1 << 18) // (ADC) End of Receiver Transfer -#define AT91C_ADC_RXBUFF ((unsigned int) 0x1 << 19) // (ADC) RXBUFF Interrupt -// -------- ADC_LCDR : (ADC Offset: 0x20) ADC Last Converted Data Register -------- -#define AT91C_ADC_LDATA ((unsigned int) 0x3FF << 0) // (ADC) Last Data Converted -// -------- ADC_IER : (ADC Offset: 0x24) ADC Interrupt Enable Register -------- -// -------- ADC_IDR : (ADC Offset: 0x28) ADC Interrupt Disable Register -------- -// -------- ADC_IMR : (ADC Offset: 0x2c) ADC Interrupt Mask Register -------- -// -------- ADC_CDR0 : (ADC Offset: 0x30) ADC Channel Data Register 0 -------- -#define AT91C_ADC_DATA ((unsigned int) 0x3FF << 0) // (ADC) Converted Data -// -------- ADC_CDR1 : (ADC Offset: 0x34) ADC Channel Data Register 1 -------- -// -------- ADC_CDR2 : (ADC Offset: 0x38) ADC Channel Data Register 2 -------- -// -------- ADC_CDR3 : (ADC Offset: 0x3c) ADC Channel Data Register 3 -------- -// -------- ADC_CDR4 : (ADC Offset: 0x40) ADC Channel Data Register 4 -------- -// -------- ADC_CDR5 : (ADC Offset: 0x44) ADC Channel Data Register 5 -------- -// -------- ADC_CDR6 : (ADC Offset: 0x48) ADC Channel Data Register 6 -------- -// -------- ADC_CDR7 : (ADC Offset: 0x4c) ADC Channel Data Register 7 -------- - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Advanced Encryption Standard -// ***************************************************************************** -typedef struct _AT91S_AES { - AT91_REG AES_CR; // Control Register - AT91_REG AES_MR; // Mode Register - AT91_REG Reserved0[2]; // - AT91_REG AES_IER; // Interrupt Enable Register - AT91_REG AES_IDR; // Interrupt Disable Register - AT91_REG AES_IMR; // Interrupt Mask Register - AT91_REG AES_ISR; // Interrupt Status Register - AT91_REG AES_KEYWxR[4]; // Key Word x Register - AT91_REG Reserved1[4]; // - AT91_REG AES_IDATAxR[4]; // Input Data x Register - AT91_REG AES_ODATAxR[4]; // Output Data x Register - AT91_REG AES_IVxR[4]; // Initialization Vector x Register - AT91_REG Reserved2[35]; // - AT91_REG AES_VR; // AES Version Register - AT91_REG AES_RPR; // Receive Pointer Register - AT91_REG AES_RCR; // Receive Counter Register - AT91_REG AES_TPR; // Transmit Pointer Register - AT91_REG AES_TCR; // Transmit Counter Register - AT91_REG AES_RNPR; // Receive Next Pointer Register - AT91_REG AES_RNCR; // Receive Next Counter Register - AT91_REG AES_TNPR; // Transmit Next Pointer Register - AT91_REG AES_TNCR; // Transmit Next Counter Register - AT91_REG AES_PTCR; // PDC Transfer Control Register - AT91_REG AES_PTSR; // PDC Transfer Status Register -} AT91S_AES, *AT91PS_AES; - -// -------- AES_CR : (AES Offset: 0x0) Control Register -------- -#define AT91C_AES_START ((unsigned int) 0x1 << 0) // (AES) Starts Processing -#define AT91C_AES_SWRST ((unsigned int) 0x1 << 8) // (AES) Software Reset -#define AT91C_AES_LOADSEED ((unsigned int) 0x1 << 16) // (AES) Random Number Generator Seed Loading -// -------- AES_MR : (AES Offset: 0x4) Mode Register -------- -#define AT91C_AES_CIPHER ((unsigned int) 0x1 << 0) // (AES) Processing Mode -#define AT91C_AES_PROCDLY ((unsigned int) 0xF << 4) // (AES) Processing Delay -#define AT91C_AES_SMOD ((unsigned int) 0x3 << 8) // (AES) Start Mode -#define AT91C_AES_SMOD_MANUAL ((unsigned int) 0x0 << 8) // (AES) Manual Mode: The START bit in register AES_CR must be set to begin encryption or decryption. -#define AT91C_AES_SMOD_AUTO ((unsigned int) 0x1 << 8) // (AES) Auto Mode: no action in AES_CR is necessary (cf datasheet). -#define AT91C_AES_SMOD_PDC ((unsigned int) 0x2 << 8) // (AES) PDC Mode (cf datasheet). -#define AT91C_AES_OPMOD ((unsigned int) 0x7 << 12) // (AES) Operation Mode -#define AT91C_AES_OPMOD_ECB ((unsigned int) 0x0 << 12) // (AES) ECB Electronic CodeBook mode. -#define AT91C_AES_OPMOD_CBC ((unsigned int) 0x1 << 12) // (AES) CBC Cipher Block Chaining mode. -#define AT91C_AES_OPMOD_OFB ((unsigned int) 0x2 << 12) // (AES) OFB Output Feedback mode. -#define AT91C_AES_OPMOD_CFB ((unsigned int) 0x3 << 12) // (AES) CFB Cipher Feedback mode. -#define AT91C_AES_OPMOD_CTR ((unsigned int) 0x4 << 12) // (AES) CTR Counter mode. -#define AT91C_AES_LOD ((unsigned int) 0x1 << 15) // (AES) Last Output Data Mode -#define AT91C_AES_CFBS ((unsigned int) 0x7 << 16) // (AES) Cipher Feedback Data Size -#define AT91C_AES_CFBS_128_BIT ((unsigned int) 0x0 << 16) // (AES) 128-bit. -#define AT91C_AES_CFBS_64_BIT ((unsigned int) 0x1 << 16) // (AES) 64-bit. -#define AT91C_AES_CFBS_32_BIT ((unsigned int) 0x2 << 16) // (AES) 32-bit. -#define AT91C_AES_CFBS_16_BIT ((unsigned int) 0x3 << 16) // (AES) 16-bit. -#define AT91C_AES_CFBS_8_BIT ((unsigned int) 0x4 << 16) // (AES) 8-bit. -#define AT91C_AES_CKEY ((unsigned int) 0xF << 20) // (AES) Countermeasure Key -#define AT91C_AES_CTYPE ((unsigned int) 0x1F << 24) // (AES) Countermeasure Type -#define AT91C_AES_CTYPE_TYPE1_EN ((unsigned int) 0x1 << 24) // (AES) Countermeasure type 1 is enabled. -#define AT91C_AES_CTYPE_TYPE2_EN ((unsigned int) 0x2 << 24) // (AES) Countermeasure type 2 is enabled. -#define AT91C_AES_CTYPE_TYPE3_EN ((unsigned int) 0x4 << 24) // (AES) Countermeasure type 3 is enabled. -#define AT91C_AES_CTYPE_TYPE4_EN ((unsigned int) 0x8 << 24) // (AES) Countermeasure type 4 is enabled. -#define AT91C_AES_CTYPE_TYPE5_EN ((unsigned int) 0x10 << 24) // (AES) Countermeasure type 5 is enabled. -// -------- AES_IER : (AES Offset: 0x10) Interrupt Enable Register -------- -#define AT91C_AES_DATRDY ((unsigned int) 0x1 << 0) // (AES) DATRDY -#define AT91C_AES_ENDRX ((unsigned int) 0x1 << 1) // (AES) PDC Read Buffer End -#define AT91C_AES_ENDTX ((unsigned int) 0x1 << 2) // (AES) PDC Write Buffer End -#define AT91C_AES_RXBUFF ((unsigned int) 0x1 << 3) // (AES) PDC Read Buffer Full -#define AT91C_AES_TXBUFE ((unsigned int) 0x1 << 4) // (AES) PDC Write Buffer Empty -#define AT91C_AES_URAD ((unsigned int) 0x1 << 8) // (AES) Unspecified Register Access Detection -// -------- AES_IDR : (AES Offset: 0x14) Interrupt Disable Register -------- -// -------- AES_IMR : (AES Offset: 0x18) Interrupt Mask Register -------- -// -------- AES_ISR : (AES Offset: 0x1c) Interrupt Status Register -------- -#define AT91C_AES_URAT ((unsigned int) 0x7 << 12) // (AES) Unspecified Register Access Type Status -#define AT91C_AES_URAT_IN_DAT_WRITE_DATPROC ((unsigned int) 0x0 << 12) // (AES) Input data register written during the data processing in PDC mode. -#define AT91C_AES_URAT_OUT_DAT_READ_DATPROC ((unsigned int) 0x1 << 12) // (AES) Output data register read during the data processing. -#define AT91C_AES_URAT_MODEREG_WRITE_DATPROC ((unsigned int) 0x2 << 12) // (AES) Mode register written during the data processing. -#define AT91C_AES_URAT_OUT_DAT_READ_SUBKEY ((unsigned int) 0x3 << 12) // (AES) Output data register read during the sub-keys generation. -#define AT91C_AES_URAT_MODEREG_WRITE_SUBKEY ((unsigned int) 0x4 << 12) // (AES) Mode register written during the sub-keys generation. -#define AT91C_AES_URAT_WO_REG_READ ((unsigned int) 0x5 << 12) // (AES) Write-only register read access. - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Triple Data Encryption Standard -// ***************************************************************************** -typedef struct _AT91S_TDES { - AT91_REG TDES_CR; // Control Register - AT91_REG TDES_MR; // Mode Register - AT91_REG Reserved0[2]; // - AT91_REG TDES_IER; // Interrupt Enable Register - AT91_REG TDES_IDR; // Interrupt Disable Register - AT91_REG TDES_IMR; // Interrupt Mask Register - AT91_REG TDES_ISR; // Interrupt Status Register - AT91_REG TDES_KEY1WxR[2]; // Key 1 Word x Register - AT91_REG TDES_KEY2WxR[2]; // Key 2 Word x Register - AT91_REG TDES_KEY3WxR[2]; // Key 3 Word x Register - AT91_REG Reserved1[2]; // - AT91_REG TDES_IDATAxR[2]; // Input Data x Register - AT91_REG Reserved2[2]; // - AT91_REG TDES_ODATAxR[2]; // Output Data x Register - AT91_REG Reserved3[2]; // - AT91_REG TDES_IVxR[2]; // Initialization Vector x Register - AT91_REG Reserved4[37]; // - AT91_REG TDES_VR; // TDES Version Register - AT91_REG TDES_RPR; // Receive Pointer Register - AT91_REG TDES_RCR; // Receive Counter Register - AT91_REG TDES_TPR; // Transmit Pointer Register - AT91_REG TDES_TCR; // Transmit Counter Register - AT91_REG TDES_RNPR; // Receive Next Pointer Register - AT91_REG TDES_RNCR; // Receive Next Counter Register - AT91_REG TDES_TNPR; // Transmit Next Pointer Register - AT91_REG TDES_TNCR; // Transmit Next Counter Register - AT91_REG TDES_PTCR; // PDC Transfer Control Register - AT91_REG TDES_PTSR; // PDC Transfer Status Register -} AT91S_TDES, *AT91PS_TDES; - -// -------- TDES_CR : (TDES Offset: 0x0) Control Register -------- -#define AT91C_TDES_START ((unsigned int) 0x1 << 0) // (TDES) Starts Processing -#define AT91C_TDES_SWRST ((unsigned int) 0x1 << 8) // (TDES) Software Reset -// -------- TDES_MR : (TDES Offset: 0x4) Mode Register -------- -#define AT91C_TDES_CIPHER ((unsigned int) 0x1 << 0) // (TDES) Processing Mode -#define AT91C_TDES_TDESMOD ((unsigned int) 0x1 << 1) // (TDES) Single or Triple DES Mode -#define AT91C_TDES_KEYMOD ((unsigned int) 0x1 << 4) // (TDES) Key Mode -#define AT91C_TDES_SMOD ((unsigned int) 0x3 << 8) // (TDES) Start Mode -#define AT91C_TDES_SMOD_MANUAL ((unsigned int) 0x0 << 8) // (TDES) Manual Mode: The START bit in register TDES_CR must be set to begin encryption or decryption. -#define AT91C_TDES_SMOD_AUTO ((unsigned int) 0x1 << 8) // (TDES) Auto Mode: no action in TDES_CR is necessary (cf datasheet). -#define AT91C_TDES_SMOD_PDC ((unsigned int) 0x2 << 8) // (TDES) PDC Mode (cf datasheet). -#define AT91C_TDES_OPMOD ((unsigned int) 0x3 << 12) // (TDES) Operation Mode -#define AT91C_TDES_OPMOD_ECB ((unsigned int) 0x0 << 12) // (TDES) ECB Electronic CodeBook mode. -#define AT91C_TDES_OPMOD_CBC ((unsigned int) 0x1 << 12) // (TDES) CBC Cipher Block Chaining mode. -#define AT91C_TDES_OPMOD_OFB ((unsigned int) 0x2 << 12) // (TDES) OFB Output Feedback mode. -#define AT91C_TDES_OPMOD_CFB ((unsigned int) 0x3 << 12) // (TDES) CFB Cipher Feedback mode. -#define AT91C_TDES_LOD ((unsigned int) 0x1 << 15) // (TDES) Last Output Data Mode -#define AT91C_TDES_CFBS ((unsigned int) 0x3 << 16) // (TDES) Cipher Feedback Data Size -#define AT91C_TDES_CFBS_64_BIT ((unsigned int) 0x0 << 16) // (TDES) 64-bit. -#define AT91C_TDES_CFBS_32_BIT ((unsigned int) 0x1 << 16) // (TDES) 32-bit. -#define AT91C_TDES_CFBS_16_BIT ((unsigned int) 0x2 << 16) // (TDES) 16-bit. -#define AT91C_TDES_CFBS_8_BIT ((unsigned int) 0x3 << 16) // (TDES) 8-bit. -// -------- TDES_IER : (TDES Offset: 0x10) Interrupt Enable Register -------- -#define AT91C_TDES_DATRDY ((unsigned int) 0x1 << 0) // (TDES) DATRDY -#define AT91C_TDES_ENDRX ((unsigned int) 0x1 << 1) // (TDES) PDC Read Buffer End -#define AT91C_TDES_ENDTX ((unsigned int) 0x1 << 2) // (TDES) PDC Write Buffer End -#define AT91C_TDES_RXBUFF ((unsigned int) 0x1 << 3) // (TDES) PDC Read Buffer Full -#define AT91C_TDES_TXBUFE ((unsigned int) 0x1 << 4) // (TDES) PDC Write Buffer Empty -#define AT91C_TDES_URAD ((unsigned int) 0x1 << 8) // (TDES) Unspecified Register Access Detection -// -------- TDES_IDR : (TDES Offset: 0x14) Interrupt Disable Register -------- -// -------- TDES_IMR : (TDES Offset: 0x18) Interrupt Mask Register -------- -// -------- TDES_ISR : (TDES Offset: 0x1c) Interrupt Status Register -------- -#define AT91C_TDES_URAT ((unsigned int) 0x3 << 12) // (TDES) Unspecified Register Access Type Status -#define AT91C_TDES_URAT_IN_DAT_WRITE_DATPROC ((unsigned int) 0x0 << 12) // (TDES) Input data register written during the data processing in PDC mode. -#define AT91C_TDES_URAT_OUT_DAT_READ_DATPROC ((unsigned int) 0x1 << 12) // (TDES) Output data register read during the data processing. -#define AT91C_TDES_URAT_MODEREG_WRITE_DATPROC ((unsigned int) 0x2 << 12) // (TDES) Mode register written during the data processing. -#define AT91C_TDES_URAT_WO_REG_READ ((unsigned int) 0x3 << 12) // (TDES) Write-only register read access. - -// ***************************************************************************** -// REGISTER ADDRESS DEFINITION FOR AT91SAM7X128 -// ***************************************************************************** -// ========== Register definition for SYS peripheral ========== -// ========== Register definition for AIC peripheral ========== -#define AT91C_AIC_IVR ((AT91_REG *) 0xFFFFF100) // (AIC) IRQ Vector Register -#define AT91C_AIC_SMR ((AT91_REG *) 0xFFFFF000) // (AIC) Source Mode Register -#define AT91C_AIC_FVR ((AT91_REG *) 0xFFFFF104) // (AIC) FIQ Vector Register -#define AT91C_AIC_DCR ((AT91_REG *) 0xFFFFF138) // (AIC) Debug Control Register (Protect) -#define AT91C_AIC_EOICR ((AT91_REG *) 0xFFFFF130) // (AIC) End of Interrupt Command Register -#define AT91C_AIC_SVR ((AT91_REG *) 0xFFFFF080) // (AIC) Source Vector Register -#define AT91C_AIC_FFSR ((AT91_REG *) 0xFFFFF148) // (AIC) Fast Forcing Status Register -#define AT91C_AIC_ICCR ((AT91_REG *) 0xFFFFF128) // (AIC) Interrupt Clear Command Register -#define AT91C_AIC_ISR ((AT91_REG *) 0xFFFFF108) // (AIC) Interrupt Status Register -#define AT91C_AIC_IMR ((AT91_REG *) 0xFFFFF110) // (AIC) Interrupt Mask Register -#define AT91C_AIC_IPR ((AT91_REG *) 0xFFFFF10C) // (AIC) Interrupt Pending Register -#define AT91C_AIC_FFER ((AT91_REG *) 0xFFFFF140) // (AIC) Fast Forcing Enable Register -#define AT91C_AIC_IECR ((AT91_REG *) 0xFFFFF120) // (AIC) Interrupt Enable Command Register -#define AT91C_AIC_ISCR ((AT91_REG *) 0xFFFFF12C) // (AIC) Interrupt Set Command Register -#define AT91C_AIC_FFDR ((AT91_REG *) 0xFFFFF144) // (AIC) Fast Forcing Disable Register -#define AT91C_AIC_CISR ((AT91_REG *) 0xFFFFF114) // (AIC) Core Interrupt Status Register -#define AT91C_AIC_IDCR ((AT91_REG *) 0xFFFFF124) // (AIC) Interrupt Disable Command Register -#define AT91C_AIC_SPU ((AT91_REG *) 0xFFFFF134) // (AIC) Spurious Vector Register -// ========== Register definition for PDC_DBGU peripheral ========== -#define AT91C_DBGU_TCR ((AT91_REG *) 0xFFFFF30C) // (PDC_DBGU) Transmit Counter Register -#define AT91C_DBGU_RNPR ((AT91_REG *) 0xFFFFF310) // (PDC_DBGU) Receive Next Pointer Register -#define AT91C_DBGU_TNPR ((AT91_REG *) 0xFFFFF318) // (PDC_DBGU) Transmit Next Pointer Register -#define AT91C_DBGU_TPR ((AT91_REG *) 0xFFFFF308) // (PDC_DBGU) Transmit Pointer Register -#define AT91C_DBGU_RPR ((AT91_REG *) 0xFFFFF300) // (PDC_DBGU) Receive Pointer Register -#define AT91C_DBGU_RCR ((AT91_REG *) 0xFFFFF304) // (PDC_DBGU) Receive Counter Register -#define AT91C_DBGU_RNCR ((AT91_REG *) 0xFFFFF314) // (PDC_DBGU) Receive Next Counter Register -#define AT91C_DBGU_PTCR ((AT91_REG *) 0xFFFFF320) // (PDC_DBGU) PDC Transfer Control Register -#define AT91C_DBGU_PTSR ((AT91_REG *) 0xFFFFF324) // (PDC_DBGU) PDC Transfer Status Register -#define AT91C_DBGU_TNCR ((AT91_REG *) 0xFFFFF31C) // (PDC_DBGU) Transmit Next Counter Register -// ========== Register definition for DBGU peripheral ========== -#define AT91C_DBGU_EXID ((AT91_REG *) 0xFFFFF244) // (DBGU) Chip ID Extension Register -#define AT91C_DBGU_BRGR ((AT91_REG *) 0xFFFFF220) // (DBGU) Baud Rate Generator Register -#define AT91C_DBGU_IDR ((AT91_REG *) 0xFFFFF20C) // (DBGU) Interrupt Disable Register -#define AT91C_DBGU_CSR ((AT91_REG *) 0xFFFFF214) // (DBGU) Channel Status Register -#define AT91C_DBGU_CIDR ((AT91_REG *) 0xFFFFF240) // (DBGU) Chip ID Register -#define AT91C_DBGU_MR ((AT91_REG *) 0xFFFFF204) // (DBGU) Mode Register -#define AT91C_DBGU_IMR ((AT91_REG *) 0xFFFFF210) // (DBGU) Interrupt Mask Register -#define AT91C_DBGU_CR ((AT91_REG *) 0xFFFFF200) // (DBGU) Control Register -#define AT91C_DBGU_FNTR ((AT91_REG *) 0xFFFFF248) // (DBGU) Force NTRST Register -#define AT91C_DBGU_THR ((AT91_REG *) 0xFFFFF21C) // (DBGU) Transmitter Holding Register -#define AT91C_DBGU_RHR ((AT91_REG *) 0xFFFFF218) // (DBGU) Receiver Holding Register -#define AT91C_DBGU_IER ((AT91_REG *) 0xFFFFF208) // (DBGU) Interrupt Enable Register -// ========== Register definition for PIOA peripheral ========== -#define AT91C_PIOA_ODR ((AT91_REG *) 0xFFFFF414) // (PIOA) Output Disable Registerr -#define AT91C_PIOA_SODR ((AT91_REG *) 0xFFFFF430) // (PIOA) Set Output Data Register -#define AT91C_PIOA_ISR ((AT91_REG *) 0xFFFFF44C) // (PIOA) Interrupt Status Register -#define AT91C_PIOA_ABSR ((AT91_REG *) 0xFFFFF478) // (PIOA) AB Select Status Register -#define AT91C_PIOA_IER ((AT91_REG *) 0xFFFFF440) // (PIOA) Interrupt Enable Register -#define AT91C_PIOA_PPUDR ((AT91_REG *) 0xFFFFF460) // (PIOA) Pull-up Disable Register -#define AT91C_PIOA_IMR ((AT91_REG *) 0xFFFFF448) // (PIOA) Interrupt Mask Register -#define AT91C_PIOA_PER ((AT91_REG *) 0xFFFFF400) // (PIOA) PIO Enable Register -#define AT91C_PIOA_IFDR ((AT91_REG *) 0xFFFFF424) // (PIOA) Input Filter Disable Register -#define AT91C_PIOA_OWDR ((AT91_REG *) 0xFFFFF4A4) // (PIOA) Output Write Disable Register -#define AT91C_PIOA_MDSR ((AT91_REG *) 0xFFFFF458) // (PIOA) Multi-driver Status Register -#define AT91C_PIOA_IDR ((AT91_REG *) 0xFFFFF444) // (PIOA) Interrupt Disable Register -#define AT91C_PIOA_ODSR ((AT91_REG *) 0xFFFFF438) // (PIOA) Output Data Status Register -#define AT91C_PIOA_PPUSR ((AT91_REG *) 0xFFFFF468) // (PIOA) Pull-up Status Register -#define AT91C_PIOA_OWSR ((AT91_REG *) 0xFFFFF4A8) // (PIOA) Output Write Status Register -#define AT91C_PIOA_BSR ((AT91_REG *) 0xFFFFF474) // (PIOA) Select B Register -#define AT91C_PIOA_OWER ((AT91_REG *) 0xFFFFF4A0) // (PIOA) Output Write Enable Register -#define AT91C_PIOA_IFER ((AT91_REG *) 0xFFFFF420) // (PIOA) Input Filter Enable Register -#define AT91C_PIOA_PDSR ((AT91_REG *) 0xFFFFF43C) // (PIOA) Pin Data Status Register -#define AT91C_PIOA_PPUER ((AT91_REG *) 0xFFFFF464) // (PIOA) Pull-up Enable Register -#define AT91C_PIOA_OSR ((AT91_REG *) 0xFFFFF418) // (PIOA) Output Status Register -#define AT91C_PIOA_ASR ((AT91_REG *) 0xFFFFF470) // (PIOA) Select A Register -#define AT91C_PIOA_MDDR ((AT91_REG *) 0xFFFFF454) // (PIOA) Multi-driver Disable Register -#define AT91C_PIOA_CODR ((AT91_REG *) 0xFFFFF434) // (PIOA) Clear Output Data Register -#define AT91C_PIOA_MDER ((AT91_REG *) 0xFFFFF450) // (PIOA) Multi-driver Enable Register -#define AT91C_PIOA_PDR ((AT91_REG *) 0xFFFFF404) // (PIOA) PIO Disable Register -#define AT91C_PIOA_IFSR ((AT91_REG *) 0xFFFFF428) // (PIOA) Input Filter Status Register -#define AT91C_PIOA_OER ((AT91_REG *) 0xFFFFF410) // (PIOA) Output Enable Register -#define AT91C_PIOA_PSR ((AT91_REG *) 0xFFFFF408) // (PIOA) PIO Status Register -// ========== Register definition for PIOB peripheral ========== -#define AT91C_PIOB_OWDR ((AT91_REG *) 0xFFFFF6A4) // (PIOB) Output Write Disable Register -#define AT91C_PIOB_MDER ((AT91_REG *) 0xFFFFF650) // (PIOB) Multi-driver Enable Register -#define AT91C_PIOB_PPUSR ((AT91_REG *) 0xFFFFF668) // (PIOB) Pull-up Status Register -#define AT91C_PIOB_IMR ((AT91_REG *) 0xFFFFF648) // (PIOB) Interrupt Mask Register -#define AT91C_PIOB_ASR ((AT91_REG *) 0xFFFFF670) // (PIOB) Select A Register -#define AT91C_PIOB_PPUDR ((AT91_REG *) 0xFFFFF660) // (PIOB) Pull-up Disable Register -#define AT91C_PIOB_PSR ((AT91_REG *) 0xFFFFF608) // (PIOB) PIO Status Register -#define AT91C_PIOB_IER ((AT91_REG *) 0xFFFFF640) // (PIOB) Interrupt Enable Register -#define AT91C_PIOB_CODR ((AT91_REG *) 0xFFFFF634) // (PIOB) Clear Output Data Register -#define AT91C_PIOB_OWER ((AT91_REG *) 0xFFFFF6A0) // (PIOB) Output Write Enable Register -#define AT91C_PIOB_ABSR ((AT91_REG *) 0xFFFFF678) // (PIOB) AB Select Status Register -#define AT91C_PIOB_IFDR ((AT91_REG *) 0xFFFFF624) // (PIOB) Input Filter Disable Register -#define AT91C_PIOB_PDSR ((AT91_REG *) 0xFFFFF63C) // (PIOB) Pin Data Status Register -#define AT91C_PIOB_IDR ((AT91_REG *) 0xFFFFF644) // (PIOB) Interrupt Disable Register -#define AT91C_PIOB_OWSR ((AT91_REG *) 0xFFFFF6A8) // (PIOB) Output Write Status Register -#define AT91C_PIOB_PDR ((AT91_REG *) 0xFFFFF604) // (PIOB) PIO Disable Register -#define AT91C_PIOB_ODR ((AT91_REG *) 0xFFFFF614) // (PIOB) Output Disable Registerr -#define AT91C_PIOB_IFSR ((AT91_REG *) 0xFFFFF628) // (PIOB) Input Filter Status Register -#define AT91C_PIOB_PPUER ((AT91_REG *) 0xFFFFF664) // (PIOB) Pull-up Enable Register -#define AT91C_PIOB_SODR ((AT91_REG *) 0xFFFFF630) // (PIOB) Set Output Data Register -#define AT91C_PIOB_ISR ((AT91_REG *) 0xFFFFF64C) // (PIOB) Interrupt Status Register -#define AT91C_PIOB_ODSR ((AT91_REG *) 0xFFFFF638) // (PIOB) Output Data Status Register -#define AT91C_PIOB_OSR ((AT91_REG *) 0xFFFFF618) // (PIOB) Output Status Register -#define AT91C_PIOB_MDSR ((AT91_REG *) 0xFFFFF658) // (PIOB) Multi-driver Status Register -#define AT91C_PIOB_IFER ((AT91_REG *) 0xFFFFF620) // (PIOB) Input Filter Enable Register -#define AT91C_PIOB_BSR ((AT91_REG *) 0xFFFFF674) // (PIOB) Select B Register -#define AT91C_PIOB_MDDR ((AT91_REG *) 0xFFFFF654) // (PIOB) Multi-driver Disable Register -#define AT91C_PIOB_OER ((AT91_REG *) 0xFFFFF610) // (PIOB) Output Enable Register -#define AT91C_PIOB_PER ((AT91_REG *) 0xFFFFF600) // (PIOB) PIO Enable Register -// ========== Register definition for CKGR peripheral ========== -#define AT91C_CKGR_MOR ((AT91_REG *) 0xFFFFFC20) // (CKGR) Main Oscillator Register -#define AT91C_CKGR_PLLR ((AT91_REG *) 0xFFFFFC2C) // (CKGR) PLL Register -#define AT91C_CKGR_MCFR ((AT91_REG *) 0xFFFFFC24) // (CKGR) Main Clock Frequency Register -// ========== Register definition for PMC peripheral ========== -#define AT91C_PMC_IDR ((AT91_REG *) 0xFFFFFC64) // (PMC) Interrupt Disable Register -#define AT91C_PMC_MOR ((AT91_REG *) 0xFFFFFC20) // (PMC) Main Oscillator Register -#define AT91C_PMC_PLLR ((AT91_REG *) 0xFFFFFC2C) // (PMC) PLL Register -#define AT91C_PMC_PCER ((AT91_REG *) 0xFFFFFC10) // (PMC) Peripheral Clock Enable Register -#define AT91C_PMC_PCKR ((AT91_REG *) 0xFFFFFC40) // (PMC) Programmable Clock Register -#define AT91C_PMC_MCKR ((AT91_REG *) 0xFFFFFC30) // (PMC) Master Clock Register -#define AT91C_PMC_SCDR ((AT91_REG *) 0xFFFFFC04) // (PMC) System Clock Disable Register -#define AT91C_PMC_PCDR ((AT91_REG *) 0xFFFFFC14) // (PMC) Peripheral Clock Disable Register -#define AT91C_PMC_SCSR ((AT91_REG *) 0xFFFFFC08) // (PMC) System Clock Status Register -#define AT91C_PMC_PCSR ((AT91_REG *) 0xFFFFFC18) // (PMC) Peripheral Clock Status Register -#define AT91C_PMC_MCFR ((AT91_REG *) 0xFFFFFC24) // (PMC) Main Clock Frequency Register -#define AT91C_PMC_SCER ((AT91_REG *) 0xFFFFFC00) // (PMC) System Clock Enable Register -#define AT91C_PMC_IMR ((AT91_REG *) 0xFFFFFC6C) // (PMC) Interrupt Mask Register -#define AT91C_PMC_IER ((AT91_REG *) 0xFFFFFC60) // (PMC) Interrupt Enable Register -#define AT91C_PMC_SR ((AT91_REG *) 0xFFFFFC68) // (PMC) Status Register -// ========== Register definition for RSTC peripheral ========== -#define AT91C_RSTC_RCR ((AT91_REG *) 0xFFFFFD00) // (RSTC) Reset Control Register -#define AT91C_RSTC_RMR ((AT91_REG *) 0xFFFFFD08) // (RSTC) Reset Mode Register -#define AT91C_RSTC_RSR ((AT91_REG *) 0xFFFFFD04) // (RSTC) Reset Status Register -// ========== Register definition for RTTC peripheral ========== -#define AT91C_RTTC_RTSR ((AT91_REG *) 0xFFFFFD2C) // (RTTC) Real-time Status Register -#define AT91C_RTTC_RTMR ((AT91_REG *) 0xFFFFFD20) // (RTTC) Real-time Mode Register -#define AT91C_RTTC_RTVR ((AT91_REG *) 0xFFFFFD28) // (RTTC) Real-time Value Register -#define AT91C_RTTC_RTAR ((AT91_REG *) 0xFFFFFD24) // (RTTC) Real-time Alarm Register -// ========== Register definition for PITC peripheral ========== -#define AT91C_PITC_PIVR ((AT91_REG *) 0xFFFFFD38) // (PITC) Period Interval Value Register -#define AT91C_PITC_PISR ((AT91_REG *) 0xFFFFFD34) // (PITC) Period Interval Status Register -#define AT91C_PITC_PIIR ((AT91_REG *) 0xFFFFFD3C) // (PITC) Period Interval Image Register -#define AT91C_PITC_PIMR ((AT91_REG *) 0xFFFFFD30) // (PITC) Period Interval Mode Register -// ========== Register definition for WDTC peripheral ========== -#define AT91C_WDTC_WDCR ((AT91_REG *) 0xFFFFFD40) // (WDTC) Watchdog Control Register -#define AT91C_WDTC_WDSR ((AT91_REG *) 0xFFFFFD48) // (WDTC) Watchdog Status Register -#define AT91C_WDTC_WDMR ((AT91_REG *) 0xFFFFFD44) // (WDTC) Watchdog Mode Register -// ========== Register definition for VREG peripheral ========== -#define AT91C_VREG_MR ((AT91_REG *) 0xFFFFFD60) // (VREG) Voltage Regulator Mode Register -// ========== Register definition for MC peripheral ========== -#define AT91C_MC_ASR ((AT91_REG *) 0xFFFFFF04) // (MC) MC Abort Status Register -#define AT91C_MC_RCR ((AT91_REG *) 0xFFFFFF00) // (MC) MC Remap Control Register -#define AT91C_MC_FCR ((AT91_REG *) 0xFFFFFF64) // (MC) MC Flash Command Register -#define AT91C_MC_AASR ((AT91_REG *) 0xFFFFFF08) // (MC) MC Abort Address Status Register -#define AT91C_MC_FSR ((AT91_REG *) 0xFFFFFF68) // (MC) MC Flash Status Register -#define AT91C_MC_FMR ((AT91_REG *) 0xFFFFFF60) // (MC) MC Flash Mode Register -// ========== Register definition for PDC_SPI1 peripheral ========== -#define AT91C_SPI1_PTCR ((AT91_REG *) 0xFFFE4120) // (PDC_SPI1) PDC Transfer Control Register -#define AT91C_SPI1_RPR ((AT91_REG *) 0xFFFE4100) // (PDC_SPI1) Receive Pointer Register -#define AT91C_SPI1_TNCR ((AT91_REG *) 0xFFFE411C) // (PDC_SPI1) Transmit Next Counter Register -#define AT91C_SPI1_TPR ((AT91_REG *) 0xFFFE4108) // (PDC_SPI1) Transmit Pointer Register -#define AT91C_SPI1_TNPR ((AT91_REG *) 0xFFFE4118) // (PDC_SPI1) Transmit Next Pointer Register -#define AT91C_SPI1_TCR ((AT91_REG *) 0xFFFE410C) // (PDC_SPI1) Transmit Counter Register -#define AT91C_SPI1_RCR ((AT91_REG *) 0xFFFE4104) // (PDC_SPI1) Receive Counter Register -#define AT91C_SPI1_RNPR ((AT91_REG *) 0xFFFE4110) // (PDC_SPI1) Receive Next Pointer Register -#define AT91C_SPI1_RNCR ((AT91_REG *) 0xFFFE4114) // (PDC_SPI1) Receive Next Counter Register -#define AT91C_SPI1_PTSR ((AT91_REG *) 0xFFFE4124) // (PDC_SPI1) PDC Transfer Status Register -// ========== Register definition for SPI1 peripheral ========== -#define AT91C_SPI1_IMR ((AT91_REG *) 0xFFFE401C) // (SPI1) Interrupt Mask Register -#define AT91C_SPI1_IER ((AT91_REG *) 0xFFFE4014) // (SPI1) Interrupt Enable Register -#define AT91C_SPI1_MR ((AT91_REG *) 0xFFFE4004) // (SPI1) Mode Register -#define AT91C_SPI1_RDR ((AT91_REG *) 0xFFFE4008) // (SPI1) Receive Data Register -#define AT91C_SPI1_IDR ((AT91_REG *) 0xFFFE4018) // (SPI1) Interrupt Disable Register -#define AT91C_SPI1_SR ((AT91_REG *) 0xFFFE4010) // (SPI1) Status Register -#define AT91C_SPI1_TDR ((AT91_REG *) 0xFFFE400C) // (SPI1) Transmit Data Register -#define AT91C_SPI1_CR ((AT91_REG *) 0xFFFE4000) // (SPI1) Control Register -#define AT91C_SPI1_CSR ((AT91_REG *) 0xFFFE4030) // (SPI1) Chip Select Register -// ========== Register definition for PDC_SPI0 peripheral ========== -#define AT91C_SPI0_PTCR ((AT91_REG *) 0xFFFE0120) // (PDC_SPI0) PDC Transfer Control Register -#define AT91C_SPI0_TPR ((AT91_REG *) 0xFFFE0108) // (PDC_SPI0) Transmit Pointer Register -#define AT91C_SPI0_TCR ((AT91_REG *) 0xFFFE010C) // (PDC_SPI0) Transmit Counter Register -#define AT91C_SPI0_RCR ((AT91_REG *) 0xFFFE0104) // (PDC_SPI0) Receive Counter Register -#define AT91C_SPI0_PTSR ((AT91_REG *) 0xFFFE0124) // (PDC_SPI0) PDC Transfer Status Register -#define AT91C_SPI0_RNPR ((AT91_REG *) 0xFFFE0110) // (PDC_SPI0) Receive Next Pointer Register -#define AT91C_SPI0_RPR ((AT91_REG *) 0xFFFE0100) // (PDC_SPI0) Receive Pointer Register -#define AT91C_SPI0_TNCR ((AT91_REG *) 0xFFFE011C) // (PDC_SPI0) Transmit Next Counter Register -#define AT91C_SPI0_RNCR ((AT91_REG *) 0xFFFE0114) // (PDC_SPI0) Receive Next Counter Register -#define AT91C_SPI0_TNPR ((AT91_REG *) 0xFFFE0118) // (PDC_SPI0) Transmit Next Pointer Register -// ========== Register definition for SPI0 peripheral ========== -#define AT91C_SPI0_IER ((AT91_REG *) 0xFFFE0014) // (SPI0) Interrupt Enable Register -#define AT91C_SPI0_SR ((AT91_REG *) 0xFFFE0010) // (SPI0) Status Register -#define AT91C_SPI0_IDR ((AT91_REG *) 0xFFFE0018) // (SPI0) Interrupt Disable Register -#define AT91C_SPI0_CR ((AT91_REG *) 0xFFFE0000) // (SPI0) Control Register -#define AT91C_SPI0_MR ((AT91_REG *) 0xFFFE0004) // (SPI0) Mode Register -#define AT91C_SPI0_IMR ((AT91_REG *) 0xFFFE001C) // (SPI0) Interrupt Mask Register -#define AT91C_SPI0_TDR ((AT91_REG *) 0xFFFE000C) // (SPI0) Transmit Data Register -#define AT91C_SPI0_RDR ((AT91_REG *) 0xFFFE0008) // (SPI0) Receive Data Register -#define AT91C_SPI0_CSR ((AT91_REG *) 0xFFFE0030) // (SPI0) Chip Select Register -// ========== Register definition for PDC_US1 peripheral ========== -#define AT91C_US1_RNCR ((AT91_REG *) 0xFFFC4114) // (PDC_US1) Receive Next Counter Register -#define AT91C_US1_PTCR ((AT91_REG *) 0xFFFC4120) // (PDC_US1) PDC Transfer Control Register -#define AT91C_US1_TCR ((AT91_REG *) 0xFFFC410C) // (PDC_US1) Transmit Counter Register -#define AT91C_US1_PTSR ((AT91_REG *) 0xFFFC4124) // (PDC_US1) PDC Transfer Status Register -#define AT91C_US1_TNPR ((AT91_REG *) 0xFFFC4118) // (PDC_US1) Transmit Next Pointer Register -#define AT91C_US1_RCR ((AT91_REG *) 0xFFFC4104) // (PDC_US1) Receive Counter Register -#define AT91C_US1_RNPR ((AT91_REG *) 0xFFFC4110) // (PDC_US1) Receive Next Pointer Register -#define AT91C_US1_RPR ((AT91_REG *) 0xFFFC4100) // (PDC_US1) Receive Pointer Register -#define AT91C_US1_TNCR ((AT91_REG *) 0xFFFC411C) // (PDC_US1) Transmit Next Counter Register -#define AT91C_US1_TPR ((AT91_REG *) 0xFFFC4108) // (PDC_US1) Transmit Pointer Register -// ========== Register definition for US1 peripheral ========== -#define AT91C_US1_IF ((AT91_REG *) 0xFFFC404C) // (US1) IRDA_FILTER Register -#define AT91C_US1_NER ((AT91_REG *) 0xFFFC4044) // (US1) Nb Errors Register -#define AT91C_US1_RTOR ((AT91_REG *) 0xFFFC4024) // (US1) Receiver Time-out Register -#define AT91C_US1_CSR ((AT91_REG *) 0xFFFC4014) // (US1) Channel Status Register -#define AT91C_US1_IDR ((AT91_REG *) 0xFFFC400C) // (US1) Interrupt Disable Register -#define AT91C_US1_IER ((AT91_REG *) 0xFFFC4008) // (US1) Interrupt Enable Register -#define AT91C_US1_THR ((AT91_REG *) 0xFFFC401C) // (US1) Transmitter Holding Register -#define AT91C_US1_TTGR ((AT91_REG *) 0xFFFC4028) // (US1) Transmitter Time-guard Register -#define AT91C_US1_RHR ((AT91_REG *) 0xFFFC4018) // (US1) Receiver Holding Register -#define AT91C_US1_BRGR ((AT91_REG *) 0xFFFC4020) // (US1) Baud Rate Generator Register -#define AT91C_US1_IMR ((AT91_REG *) 0xFFFC4010) // (US1) Interrupt Mask Register -#define AT91C_US1_FIDI ((AT91_REG *) 0xFFFC4040) // (US1) FI_DI_Ratio Register -#define AT91C_US1_CR ((AT91_REG *) 0xFFFC4000) // (US1) Control Register -#define AT91C_US1_MR ((AT91_REG *) 0xFFFC4004) // (US1) Mode Register -// ========== Register definition for PDC_US0 peripheral ========== -#define AT91C_US0_TNPR ((AT91_REG *) 0xFFFC0118) // (PDC_US0) Transmit Next Pointer Register -#define AT91C_US0_RNPR ((AT91_REG *) 0xFFFC0110) // (PDC_US0) Receive Next Pointer Register -#define AT91C_US0_TCR ((AT91_REG *) 0xFFFC010C) // (PDC_US0) Transmit Counter Register -#define AT91C_US0_PTCR ((AT91_REG *) 0xFFFC0120) // (PDC_US0) PDC Transfer Control Register -#define AT91C_US0_PTSR ((AT91_REG *) 0xFFFC0124) // (PDC_US0) PDC Transfer Status Register -#define AT91C_US0_TNCR ((AT91_REG *) 0xFFFC011C) // (PDC_US0) Transmit Next Counter Register -#define AT91C_US0_TPR ((AT91_REG *) 0xFFFC0108) // (PDC_US0) Transmit Pointer Register -#define AT91C_US0_RCR ((AT91_REG *) 0xFFFC0104) // (PDC_US0) Receive Counter Register -#define AT91C_US0_RPR ((AT91_REG *) 0xFFFC0100) // (PDC_US0) Receive Pointer Register -#define AT91C_US0_RNCR ((AT91_REG *) 0xFFFC0114) // (PDC_US0) Receive Next Counter Register -// ========== Register definition for US0 peripheral ========== -#define AT91C_US0_BRGR ((AT91_REG *) 0xFFFC0020) // (US0) Baud Rate Generator Register -#define AT91C_US0_NER ((AT91_REG *) 0xFFFC0044) // (US0) Nb Errors Register -#define AT91C_US0_CR ((AT91_REG *) 0xFFFC0000) // (US0) Control Register -#define AT91C_US0_IMR ((AT91_REG *) 0xFFFC0010) // (US0) Interrupt Mask Register -#define AT91C_US0_FIDI ((AT91_REG *) 0xFFFC0040) // (US0) FI_DI_Ratio Register -#define AT91C_US0_TTGR ((AT91_REG *) 0xFFFC0028) // (US0) Transmitter Time-guard Register -#define AT91C_US0_MR ((AT91_REG *) 0xFFFC0004) // (US0) Mode Register -#define AT91C_US0_RTOR ((AT91_REG *) 0xFFFC0024) // (US0) Receiver Time-out Register -#define AT91C_US0_CSR ((AT91_REG *) 0xFFFC0014) // (US0) Channel Status Register -#define AT91C_US0_RHR ((AT91_REG *) 0xFFFC0018) // (US0) Receiver Holding Register -#define AT91C_US0_IDR ((AT91_REG *) 0xFFFC000C) // (US0) Interrupt Disable Register -#define AT91C_US0_THR ((AT91_REG *) 0xFFFC001C) // (US0) Transmitter Holding Register -#define AT91C_US0_IF ((AT91_REG *) 0xFFFC004C) // (US0) IRDA_FILTER Register -#define AT91C_US0_IER ((AT91_REG *) 0xFFFC0008) // (US0) Interrupt Enable Register -// ========== Register definition for PDC_SSC peripheral ========== -#define AT91C_SSC_TNCR ((AT91_REG *) 0xFFFD411C) // (PDC_SSC) Transmit Next Counter Register -#define AT91C_SSC_RPR ((AT91_REG *) 0xFFFD4100) // (PDC_SSC) Receive Pointer Register -#define AT91C_SSC_RNCR ((AT91_REG *) 0xFFFD4114) // (PDC_SSC) Receive Next Counter Register -#define AT91C_SSC_TPR ((AT91_REG *) 0xFFFD4108) // (PDC_SSC) Transmit Pointer Register -#define AT91C_SSC_PTCR ((AT91_REG *) 0xFFFD4120) // (PDC_SSC) PDC Transfer Control Register -#define AT91C_SSC_TCR ((AT91_REG *) 0xFFFD410C) // (PDC_SSC) Transmit Counter Register -#define AT91C_SSC_RCR ((AT91_REG *) 0xFFFD4104) // (PDC_SSC) Receive Counter Register -#define AT91C_SSC_RNPR ((AT91_REG *) 0xFFFD4110) // (PDC_SSC) Receive Next Pointer Register -#define AT91C_SSC_TNPR ((AT91_REG *) 0xFFFD4118) // (PDC_SSC) Transmit Next Pointer Register -#define AT91C_SSC_PTSR ((AT91_REG *) 0xFFFD4124) // (PDC_SSC) PDC Transfer Status Register -// ========== Register definition for SSC peripheral ========== -#define AT91C_SSC_RHR ((AT91_REG *) 0xFFFD4020) // (SSC) Receive Holding Register -#define AT91C_SSC_RSHR ((AT91_REG *) 0xFFFD4030) // (SSC) Receive Sync Holding Register -#define AT91C_SSC_TFMR ((AT91_REG *) 0xFFFD401C) // (SSC) Transmit Frame Mode Register -#define AT91C_SSC_IDR ((AT91_REG *) 0xFFFD4048) // (SSC) Interrupt Disable Register -#define AT91C_SSC_THR ((AT91_REG *) 0xFFFD4024) // (SSC) Transmit Holding Register -#define AT91C_SSC_RCMR ((AT91_REG *) 0xFFFD4010) // (SSC) Receive Clock ModeRegister -#define AT91C_SSC_IER ((AT91_REG *) 0xFFFD4044) // (SSC) Interrupt Enable Register -#define AT91C_SSC_TSHR ((AT91_REG *) 0xFFFD4034) // (SSC) Transmit Sync Holding Register -#define AT91C_SSC_SR ((AT91_REG *) 0xFFFD4040) // (SSC) Status Register -#define AT91C_SSC_CMR ((AT91_REG *) 0xFFFD4004) // (SSC) Clock Mode Register -#define AT91C_SSC_TCMR ((AT91_REG *) 0xFFFD4018) // (SSC) Transmit Clock Mode Register -#define AT91C_SSC_CR ((AT91_REG *) 0xFFFD4000) // (SSC) Control Register -#define AT91C_SSC_IMR ((AT91_REG *) 0xFFFD404C) // (SSC) Interrupt Mask Register -#define AT91C_SSC_RFMR ((AT91_REG *) 0xFFFD4014) // (SSC) Receive Frame Mode Register -// ========== Register definition for TWI peripheral ========== -#define AT91C_TWI_IER ((AT91_REG *) 0xFFFB8024) // (TWI) Interrupt Enable Register -#define AT91C_TWI_CR ((AT91_REG *) 0xFFFB8000) // (TWI) Control Register -#define AT91C_TWI_SR ((AT91_REG *) 0xFFFB8020) // (TWI) Status Register -#define AT91C_TWI_IMR ((AT91_REG *) 0xFFFB802C) // (TWI) Interrupt Mask Register -#define AT91C_TWI_THR ((AT91_REG *) 0xFFFB8034) // (TWI) Transmit Holding Register -#define AT91C_TWI_IDR ((AT91_REG *) 0xFFFB8028) // (TWI) Interrupt Disable Register -#define AT91C_TWI_IADR ((AT91_REG *) 0xFFFB800C) // (TWI) Internal Address Register -#define AT91C_TWI_MMR ((AT91_REG *) 0xFFFB8004) // (TWI) Master Mode Register -#define AT91C_TWI_CWGR ((AT91_REG *) 0xFFFB8010) // (TWI) Clock Waveform Generator Register -#define AT91C_TWI_RHR ((AT91_REG *) 0xFFFB8030) // (TWI) Receive Holding Register -// ========== Register definition for PWMC_CH3 peripheral ========== -#define AT91C_PWMC_CH3_CUPDR ((AT91_REG *) 0xFFFCC270) // (PWMC_CH3) Channel Update Register -#define AT91C_PWMC_CH3_Reserved ((AT91_REG *) 0xFFFCC274) // (PWMC_CH3) Reserved -#define AT91C_PWMC_CH3_CPRDR ((AT91_REG *) 0xFFFCC268) // (PWMC_CH3) Channel Period Register -#define AT91C_PWMC_CH3_CDTYR ((AT91_REG *) 0xFFFCC264) // (PWMC_CH3) Channel Duty Cycle Register -#define AT91C_PWMC_CH3_CCNTR ((AT91_REG *) 0xFFFCC26C) // (PWMC_CH3) Channel Counter Register -#define AT91C_PWMC_CH3_CMR ((AT91_REG *) 0xFFFCC260) // (PWMC_CH3) Channel Mode Register -// ========== Register definition for PWMC_CH2 peripheral ========== -#define AT91C_PWMC_CH2_Reserved ((AT91_REG *) 0xFFFCC254) // (PWMC_CH2) Reserved -#define AT91C_PWMC_CH2_CMR ((AT91_REG *) 0xFFFCC240) // (PWMC_CH2) Channel Mode Register -#define AT91C_PWMC_CH2_CCNTR ((AT91_REG *) 0xFFFCC24C) // (PWMC_CH2) Channel Counter Register -#define AT91C_PWMC_CH2_CPRDR ((AT91_REG *) 0xFFFCC248) // (PWMC_CH2) Channel Period Register -#define AT91C_PWMC_CH2_CUPDR ((AT91_REG *) 0xFFFCC250) // (PWMC_CH2) Channel Update Register -#define AT91C_PWMC_CH2_CDTYR ((AT91_REG *) 0xFFFCC244) // (PWMC_CH2) Channel Duty Cycle Register -// ========== Register definition for PWMC_CH1 peripheral ========== -#define AT91C_PWMC_CH1_Reserved ((AT91_REG *) 0xFFFCC234) // (PWMC_CH1) Reserved -#define AT91C_PWMC_CH1_CUPDR ((AT91_REG *) 0xFFFCC230) // (PWMC_CH1) Channel Update Register -#define AT91C_PWMC_CH1_CPRDR ((AT91_REG *) 0xFFFCC228) // (PWMC_CH1) Channel Period Register -#define AT91C_PWMC_CH1_CCNTR ((AT91_REG *) 0xFFFCC22C) // (PWMC_CH1) Channel Counter Register -#define AT91C_PWMC_CH1_CDTYR ((AT91_REG *) 0xFFFCC224) // (PWMC_CH1) Channel Duty Cycle Register -#define AT91C_PWMC_CH1_CMR ((AT91_REG *) 0xFFFCC220) // (PWMC_CH1) Channel Mode Register -// ========== Register definition for PWMC_CH0 peripheral ========== -#define AT91C_PWMC_CH0_Reserved ((AT91_REG *) 0xFFFCC214) // (PWMC_CH0) Reserved -#define AT91C_PWMC_CH0_CPRDR ((AT91_REG *) 0xFFFCC208) // (PWMC_CH0) Channel Period Register -#define AT91C_PWMC_CH0_CDTYR ((AT91_REG *) 0xFFFCC204) // (PWMC_CH0) Channel Duty Cycle Register -#define AT91C_PWMC_CH0_CMR ((AT91_REG *) 0xFFFCC200) // (PWMC_CH0) Channel Mode Register -#define AT91C_PWMC_CH0_CUPDR ((AT91_REG *) 0xFFFCC210) // (PWMC_CH0) Channel Update Register -#define AT91C_PWMC_CH0_CCNTR ((AT91_REG *) 0xFFFCC20C) // (PWMC_CH0) Channel Counter Register -// ========== Register definition for PWMC peripheral ========== -#define AT91C_PWMC_IDR ((AT91_REG *) 0xFFFCC014) // (PWMC) PWMC Interrupt Disable Register -#define AT91C_PWMC_DIS ((AT91_REG *) 0xFFFCC008) // (PWMC) PWMC Disable Register -#define AT91C_PWMC_IER ((AT91_REG *) 0xFFFCC010) // (PWMC) PWMC Interrupt Enable Register -#define AT91C_PWMC_VR ((AT91_REG *) 0xFFFCC0FC) // (PWMC) PWMC Version Register -#define AT91C_PWMC_ISR ((AT91_REG *) 0xFFFCC01C) // (PWMC) PWMC Interrupt Status Register -#define AT91C_PWMC_SR ((AT91_REG *) 0xFFFCC00C) // (PWMC) PWMC Status Register -#define AT91C_PWMC_IMR ((AT91_REG *) 0xFFFCC018) // (PWMC) PWMC Interrupt Mask Register -#define AT91C_PWMC_MR ((AT91_REG *) 0xFFFCC000) // (PWMC) PWMC Mode Register -#define AT91C_PWMC_ENA ((AT91_REG *) 0xFFFCC004) // (PWMC) PWMC Enable Register -// ========== Register definition for UDP peripheral ========== -#define AT91C_UDP_IMR ((AT91_REG *) 0xFFFB0018) // (UDP) Interrupt Mask Register -#define AT91C_UDP_FADDR ((AT91_REG *) 0xFFFB0008) // (UDP) Function Address Register -#define AT91C_UDP_NUM ((AT91_REG *) 0xFFFB0000) // (UDP) Frame Number Register -#define AT91C_UDP_FDR ((AT91_REG *) 0xFFFB0050) // (UDP) Endpoint FIFO Data Register -#define AT91C_UDP_ISR ((AT91_REG *) 0xFFFB001C) // (UDP) Interrupt Status Register -#define AT91C_UDP_CSR ((AT91_REG *) 0xFFFB0030) // (UDP) Endpoint Control and Status Register -#define AT91C_UDP_IDR ((AT91_REG *) 0xFFFB0014) // (UDP) Interrupt Disable Register -#define AT91C_UDP_ICR ((AT91_REG *) 0xFFFB0020) // (UDP) Interrupt Clear Register -#define AT91C_UDP_RSTEP ((AT91_REG *) 0xFFFB0028) // (UDP) Reset Endpoint Register -#define AT91C_UDP_TXVC ((AT91_REG *) 0xFFFB0074) // (UDP) Transceiver Control Register -#define AT91C_UDP_GLBSTATE ((AT91_REG *) 0xFFFB0004) // (UDP) Global State Register -#define AT91C_UDP_IER ((AT91_REG *) 0xFFFB0010) // (UDP) Interrupt Enable Register -// ========== Register definition for TC0 peripheral ========== -#define AT91C_TC0_SR ((AT91_REG *) 0xFFFA0020) // (TC0) Status Register -#define AT91C_TC0_RC ((AT91_REG *) 0xFFFA001C) // (TC0) Register C -#define AT91C_TC0_RB ((AT91_REG *) 0xFFFA0018) // (TC0) Register B -#define AT91C_TC0_CCR ((AT91_REG *) 0xFFFA0000) // (TC0) Channel Control Register -#define AT91C_TC0_CMR ((AT91_REG *) 0xFFFA0004) // (TC0) Channel Mode Register (Capture Mode / Waveform Mode) -#define AT91C_TC0_IER ((AT91_REG *) 0xFFFA0024) // (TC0) Interrupt Enable Register -#define AT91C_TC0_RA ((AT91_REG *) 0xFFFA0014) // (TC0) Register A -#define AT91C_TC0_IDR ((AT91_REG *) 0xFFFA0028) // (TC0) Interrupt Disable Register -#define AT91C_TC0_CV ((AT91_REG *) 0xFFFA0010) // (TC0) Counter Value -#define AT91C_TC0_IMR ((AT91_REG *) 0xFFFA002C) // (TC0) Interrupt Mask Register -// ========== Register definition for TC1 peripheral ========== -#define AT91C_TC1_RB ((AT91_REG *) 0xFFFA0058) // (TC1) Register B -#define AT91C_TC1_CCR ((AT91_REG *) 0xFFFA0040) // (TC1) Channel Control Register -#define AT91C_TC1_IER ((AT91_REG *) 0xFFFA0064) // (TC1) Interrupt Enable Register -#define AT91C_TC1_IDR ((AT91_REG *) 0xFFFA0068) // (TC1) Interrupt Disable Register -#define AT91C_TC1_SR ((AT91_REG *) 0xFFFA0060) // (TC1) Status Register -#define AT91C_TC1_CMR ((AT91_REG *) 0xFFFA0044) // (TC1) Channel Mode Register (Capture Mode / Waveform Mode) -#define AT91C_TC1_RA ((AT91_REG *) 0xFFFA0054) // (TC1) Register A -#define AT91C_TC1_RC ((AT91_REG *) 0xFFFA005C) // (TC1) Register C -#define AT91C_TC1_IMR ((AT91_REG *) 0xFFFA006C) // (TC1) Interrupt Mask Register -#define AT91C_TC1_CV ((AT91_REG *) 0xFFFA0050) // (TC1) Counter Value -// ========== Register definition for TC2 peripheral ========== -#define AT91C_TC2_CMR ((AT91_REG *) 0xFFFA0084) // (TC2) Channel Mode Register (Capture Mode / Waveform Mode) -#define AT91C_TC2_CCR ((AT91_REG *) 0xFFFA0080) // (TC2) Channel Control Register -#define AT91C_TC2_CV ((AT91_REG *) 0xFFFA0090) // (TC2) Counter Value -#define AT91C_TC2_RA ((AT91_REG *) 0xFFFA0094) // (TC2) Register A -#define AT91C_TC2_RB ((AT91_REG *) 0xFFFA0098) // (TC2) Register B -#define AT91C_TC2_IDR ((AT91_REG *) 0xFFFA00A8) // (TC2) Interrupt Disable Register -#define AT91C_TC2_IMR ((AT91_REG *) 0xFFFA00AC) // (TC2) Interrupt Mask Register -#define AT91C_TC2_RC ((AT91_REG *) 0xFFFA009C) // (TC2) Register C -#define AT91C_TC2_IER ((AT91_REG *) 0xFFFA00A4) // (TC2) Interrupt Enable Register -#define AT91C_TC2_SR ((AT91_REG *) 0xFFFA00A0) // (TC2) Status Register -// ========== Register definition for TCB peripheral ========== -#define AT91C_TCB_BMR ((AT91_REG *) 0xFFFA00C4) // (TCB) TC Block Mode Register -#define AT91C_TCB_BCR ((AT91_REG *) 0xFFFA00C0) // (TCB) TC Block Control Register -// ========== Register definition for CAN_MB0 peripheral ========== -#define AT91C_CAN_MB0_MDL ((AT91_REG *) 0xFFFD0214) // (CAN_MB0) MailBox Data Low Register -#define AT91C_CAN_MB0_MAM ((AT91_REG *) 0xFFFD0204) // (CAN_MB0) MailBox Acceptance Mask Register -#define AT91C_CAN_MB0_MCR ((AT91_REG *) 0xFFFD021C) // (CAN_MB0) MailBox Control Register -#define AT91C_CAN_MB0_MID ((AT91_REG *) 0xFFFD0208) // (CAN_MB0) MailBox ID Register -#define AT91C_CAN_MB0_MSR ((AT91_REG *) 0xFFFD0210) // (CAN_MB0) MailBox Status Register -#define AT91C_CAN_MB0_MFID ((AT91_REG *) 0xFFFD020C) // (CAN_MB0) MailBox Family ID Register -#define AT91C_CAN_MB0_MDH ((AT91_REG *) 0xFFFD0218) // (CAN_MB0) MailBox Data High Register -#define AT91C_CAN_MB0_MMR ((AT91_REG *) 0xFFFD0200) // (CAN_MB0) MailBox Mode Register -// ========== Register definition for CAN_MB1 peripheral ========== -#define AT91C_CAN_MB1_MDL ((AT91_REG *) 0xFFFD0234) // (CAN_MB1) MailBox Data Low Register -#define AT91C_CAN_MB1_MID ((AT91_REG *) 0xFFFD0228) // (CAN_MB1) MailBox ID Register -#define AT91C_CAN_MB1_MMR ((AT91_REG *) 0xFFFD0220) // (CAN_MB1) MailBox Mode Register -#define AT91C_CAN_MB1_MSR ((AT91_REG *) 0xFFFD0230) // (CAN_MB1) MailBox Status Register -#define AT91C_CAN_MB1_MAM ((AT91_REG *) 0xFFFD0224) // (CAN_MB1) MailBox Acceptance Mask Register -#define AT91C_CAN_MB1_MDH ((AT91_REG *) 0xFFFD0238) // (CAN_MB1) MailBox Data High Register -#define AT91C_CAN_MB1_MCR ((AT91_REG *) 0xFFFD023C) // (CAN_MB1) MailBox Control Register -#define AT91C_CAN_MB1_MFID ((AT91_REG *) 0xFFFD022C) // (CAN_MB1) MailBox Family ID Register -// ========== Register definition for CAN_MB2 peripheral ========== -#define AT91C_CAN_MB2_MCR ((AT91_REG *) 0xFFFD025C) // (CAN_MB2) MailBox Control Register -#define AT91C_CAN_MB2_MDH ((AT91_REG *) 0xFFFD0258) // (CAN_MB2) MailBox Data High Register -#define AT91C_CAN_MB2_MID ((AT91_REG *) 0xFFFD0248) // (CAN_MB2) MailBox ID Register -#define AT91C_CAN_MB2_MDL ((AT91_REG *) 0xFFFD0254) // (CAN_MB2) MailBox Data Low Register -#define AT91C_CAN_MB2_MMR ((AT91_REG *) 0xFFFD0240) // (CAN_MB2) MailBox Mode Register -#define AT91C_CAN_MB2_MAM ((AT91_REG *) 0xFFFD0244) // (CAN_MB2) MailBox Acceptance Mask Register -#define AT91C_CAN_MB2_MFID ((AT91_REG *) 0xFFFD024C) // (CAN_MB2) MailBox Family ID Register -#define AT91C_CAN_MB2_MSR ((AT91_REG *) 0xFFFD0250) // (CAN_MB2) MailBox Status Register -// ========== Register definition for CAN_MB3 peripheral ========== -#define AT91C_CAN_MB3_MFID ((AT91_REG *) 0xFFFD026C) // (CAN_MB3) MailBox Family ID Register -#define AT91C_CAN_MB3_MAM ((AT91_REG *) 0xFFFD0264) // (CAN_MB3) MailBox Acceptance Mask Register -#define AT91C_CAN_MB3_MID ((AT91_REG *) 0xFFFD0268) // (CAN_MB3) MailBox ID Register -#define AT91C_CAN_MB3_MCR ((AT91_REG *) 0xFFFD027C) // (CAN_MB3) MailBox Control Register -#define AT91C_CAN_MB3_MMR ((AT91_REG *) 0xFFFD0260) // (CAN_MB3) MailBox Mode Register -#define AT91C_CAN_MB3_MSR ((AT91_REG *) 0xFFFD0270) // (CAN_MB3) MailBox Status Register -#define AT91C_CAN_MB3_MDL ((AT91_REG *) 0xFFFD0274) // (CAN_MB3) MailBox Data Low Register -#define AT91C_CAN_MB3_MDH ((AT91_REG *) 0xFFFD0278) // (CAN_MB3) MailBox Data High Register -// ========== Register definition for CAN_MB4 peripheral ========== -#define AT91C_CAN_MB4_MID ((AT91_REG *) 0xFFFD0288) // (CAN_MB4) MailBox ID Register -#define AT91C_CAN_MB4_MMR ((AT91_REG *) 0xFFFD0280) // (CAN_MB4) MailBox Mode Register -#define AT91C_CAN_MB4_MDH ((AT91_REG *) 0xFFFD0298) // (CAN_MB4) MailBox Data High Register -#define AT91C_CAN_MB4_MFID ((AT91_REG *) 0xFFFD028C) // (CAN_MB4) MailBox Family ID Register -#define AT91C_CAN_MB4_MSR ((AT91_REG *) 0xFFFD0290) // (CAN_MB4) MailBox Status Register -#define AT91C_CAN_MB4_MCR ((AT91_REG *) 0xFFFD029C) // (CAN_MB4) MailBox Control Register -#define AT91C_CAN_MB4_MDL ((AT91_REG *) 0xFFFD0294) // (CAN_MB4) MailBox Data Low Register -#define AT91C_CAN_MB4_MAM ((AT91_REG *) 0xFFFD0284) // (CAN_MB4) MailBox Acceptance Mask Register -// ========== Register definition for CAN_MB5 peripheral ========== -#define AT91C_CAN_MB5_MSR ((AT91_REG *) 0xFFFD02B0) // (CAN_MB5) MailBox Status Register -#define AT91C_CAN_MB5_MCR ((AT91_REG *) 0xFFFD02BC) // (CAN_MB5) MailBox Control Register -#define AT91C_CAN_MB5_MFID ((AT91_REG *) 0xFFFD02AC) // (CAN_MB5) MailBox Family ID Register -#define AT91C_CAN_MB5_MDH ((AT91_REG *) 0xFFFD02B8) // (CAN_MB5) MailBox Data High Register -#define AT91C_CAN_MB5_MID ((AT91_REG *) 0xFFFD02A8) // (CAN_MB5) MailBox ID Register -#define AT91C_CAN_MB5_MMR ((AT91_REG *) 0xFFFD02A0) // (CAN_MB5) MailBox Mode Register -#define AT91C_CAN_MB5_MDL ((AT91_REG *) 0xFFFD02B4) // (CAN_MB5) MailBox Data Low Register -#define AT91C_CAN_MB5_MAM ((AT91_REG *) 0xFFFD02A4) // (CAN_MB5) MailBox Acceptance Mask Register -// ========== Register definition for CAN_MB6 peripheral ========== -#define AT91C_CAN_MB6_MFID ((AT91_REG *) 0xFFFD02CC) // (CAN_MB6) MailBox Family ID Register -#define AT91C_CAN_MB6_MID ((AT91_REG *) 0xFFFD02C8) // (CAN_MB6) MailBox ID Register -#define AT91C_CAN_MB6_MAM ((AT91_REG *) 0xFFFD02C4) // (CAN_MB6) MailBox Acceptance Mask Register -#define AT91C_CAN_MB6_MSR ((AT91_REG *) 0xFFFD02D0) // (CAN_MB6) MailBox Status Register -#define AT91C_CAN_MB6_MDL ((AT91_REG *) 0xFFFD02D4) // (CAN_MB6) MailBox Data Low Register -#define AT91C_CAN_MB6_MCR ((AT91_REG *) 0xFFFD02DC) // (CAN_MB6) MailBox Control Register -#define AT91C_CAN_MB6_MDH ((AT91_REG *) 0xFFFD02D8) // (CAN_MB6) MailBox Data High Register -#define AT91C_CAN_MB6_MMR ((AT91_REG *) 0xFFFD02C0) // (CAN_MB6) MailBox Mode Register -// ========== Register definition for CAN_MB7 peripheral ========== -#define AT91C_CAN_MB7_MCR ((AT91_REG *) 0xFFFD02FC) // (CAN_MB7) MailBox Control Register -#define AT91C_CAN_MB7_MDH ((AT91_REG *) 0xFFFD02F8) // (CAN_MB7) MailBox Data High Register -#define AT91C_CAN_MB7_MFID ((AT91_REG *) 0xFFFD02EC) // (CAN_MB7) MailBox Family ID Register -#define AT91C_CAN_MB7_MDL ((AT91_REG *) 0xFFFD02F4) // (CAN_MB7) MailBox Data Low Register -#define AT91C_CAN_MB7_MID ((AT91_REG *) 0xFFFD02E8) // (CAN_MB7) MailBox ID Register -#define AT91C_CAN_MB7_MMR ((AT91_REG *) 0xFFFD02E0) // (CAN_MB7) MailBox Mode Register -#define AT91C_CAN_MB7_MAM ((AT91_REG *) 0xFFFD02E4) // (CAN_MB7) MailBox Acceptance Mask Register -#define AT91C_CAN_MB7_MSR ((AT91_REG *) 0xFFFD02F0) // (CAN_MB7) MailBox Status Register -// ========== Register definition for CAN peripheral ========== -#define AT91C_CAN_TCR ((AT91_REG *) 0xFFFD0024) // (CAN) Transfer Command Register -#define AT91C_CAN_IMR ((AT91_REG *) 0xFFFD000C) // (CAN) Interrupt Mask Register -#define AT91C_CAN_IER ((AT91_REG *) 0xFFFD0004) // (CAN) Interrupt Enable Register -#define AT91C_CAN_ECR ((AT91_REG *) 0xFFFD0020) // (CAN) Error Counter Register -#define AT91C_CAN_TIMESTP ((AT91_REG *) 0xFFFD001C) // (CAN) Time Stamp Register -#define AT91C_CAN_MR ((AT91_REG *) 0xFFFD0000) // (CAN) Mode Register -#define AT91C_CAN_IDR ((AT91_REG *) 0xFFFD0008) // (CAN) Interrupt Disable Register -#define AT91C_CAN_ACR ((AT91_REG *) 0xFFFD0028) // (CAN) Abort Command Register -#define AT91C_CAN_TIM ((AT91_REG *) 0xFFFD0018) // (CAN) Timer Register -#define AT91C_CAN_SR ((AT91_REG *) 0xFFFD0010) // (CAN) Status Register -#define AT91C_CAN_BR ((AT91_REG *) 0xFFFD0014) // (CAN) Baudrate Register -#define AT91C_CAN_VR ((AT91_REG *) 0xFFFD00FC) // (CAN) Version Register -// ========== Register definition for EMAC peripheral ========== -#define AT91C_EMAC_ISR ((AT91_REG *) 0xFFFDC024) // (EMAC) Interrupt Status Register -#define AT91C_EMAC_SA4H ((AT91_REG *) 0xFFFDC0B4) // (EMAC) Specific Address 4 Top, Last 2 bytes -#define AT91C_EMAC_SA1L ((AT91_REG *) 0xFFFDC098) // (EMAC) Specific Address 1 Bottom, First 4 bytes -#define AT91C_EMAC_ELE ((AT91_REG *) 0xFFFDC078) // (EMAC) Excessive Length Errors Register -#define AT91C_EMAC_LCOL ((AT91_REG *) 0xFFFDC05C) // (EMAC) Late Collision Register -#define AT91C_EMAC_RLE ((AT91_REG *) 0xFFFDC088) // (EMAC) Receive Length Field Mismatch Register -#define AT91C_EMAC_WOL ((AT91_REG *) 0xFFFDC0C4) // (EMAC) Wake On LAN Register -#define AT91C_EMAC_DTF ((AT91_REG *) 0xFFFDC058) // (EMAC) Deferred Transmission Frame Register -#define AT91C_EMAC_TUND ((AT91_REG *) 0xFFFDC064) // (EMAC) Transmit Underrun Error Register -#define AT91C_EMAC_NCR ((AT91_REG *) 0xFFFDC000) // (EMAC) Network Control Register -#define AT91C_EMAC_SA4L ((AT91_REG *) 0xFFFDC0B0) // (EMAC) Specific Address 4 Bottom, First 4 bytes -#define AT91C_EMAC_RSR ((AT91_REG *) 0xFFFDC020) // (EMAC) Receive Status Register -#define AT91C_EMAC_SA3L ((AT91_REG *) 0xFFFDC0A8) // (EMAC) Specific Address 3 Bottom, First 4 bytes -#define AT91C_EMAC_TSR ((AT91_REG *) 0xFFFDC014) // (EMAC) Transmit Status Register -#define AT91C_EMAC_IDR ((AT91_REG *) 0xFFFDC02C) // (EMAC) Interrupt Disable Register -#define AT91C_EMAC_RSE ((AT91_REG *) 0xFFFDC074) // (EMAC) Receive Symbol Errors Register -#define AT91C_EMAC_ECOL ((AT91_REG *) 0xFFFDC060) // (EMAC) Excessive Collision Register -#define AT91C_EMAC_TID ((AT91_REG *) 0xFFFDC0B8) // (EMAC) Type ID Checking Register -#define AT91C_EMAC_HRB ((AT91_REG *) 0xFFFDC090) // (EMAC) Hash Address Bottom[31:0] -#define AT91C_EMAC_TBQP ((AT91_REG *) 0xFFFDC01C) // (EMAC) Transmit Buffer Queue Pointer -#define AT91C_EMAC_USRIO ((AT91_REG *) 0xFFFDC0C0) // (EMAC) USER Input/Output Register -#define AT91C_EMAC_PTR ((AT91_REG *) 0xFFFDC038) // (EMAC) Pause Time Register -#define AT91C_EMAC_SA2H ((AT91_REG *) 0xFFFDC0A4) // (EMAC) Specific Address 2 Top, Last 2 bytes -#define AT91C_EMAC_ROV ((AT91_REG *) 0xFFFDC070) // (EMAC) Receive Overrun Errors Register -#define AT91C_EMAC_ALE ((AT91_REG *) 0xFFFDC054) // (EMAC) Alignment Error Register -#define AT91C_EMAC_RJA ((AT91_REG *) 0xFFFDC07C) // (EMAC) Receive Jabbers Register -#define AT91C_EMAC_RBQP ((AT91_REG *) 0xFFFDC018) // (EMAC) Receive Buffer Queue Pointer -#define AT91C_EMAC_TPF ((AT91_REG *) 0xFFFDC08C) // (EMAC) Transmitted Pause Frames Register -#define AT91C_EMAC_NCFGR ((AT91_REG *) 0xFFFDC004) // (EMAC) Network Configuration Register -#define AT91C_EMAC_HRT ((AT91_REG *) 0xFFFDC094) // (EMAC) Hash Address Top[63:32] -#define AT91C_EMAC_USF ((AT91_REG *) 0xFFFDC080) // (EMAC) Undersize Frames Register -#define AT91C_EMAC_FCSE ((AT91_REG *) 0xFFFDC050) // (EMAC) Frame Check Sequence Error Register -#define AT91C_EMAC_TPQ ((AT91_REG *) 0xFFFDC0BC) // (EMAC) Transmit Pause Quantum Register -#define AT91C_EMAC_MAN ((AT91_REG *) 0xFFFDC034) // (EMAC) PHY Maintenance Register -#define AT91C_EMAC_FTO ((AT91_REG *) 0xFFFDC040) // (EMAC) Frames Transmitted OK Register -#define AT91C_EMAC_REV ((AT91_REG *) 0xFFFDC0FC) // (EMAC) Revision Register -#define AT91C_EMAC_IMR ((AT91_REG *) 0xFFFDC030) // (EMAC) Interrupt Mask Register -#define AT91C_EMAC_SCF ((AT91_REG *) 0xFFFDC044) // (EMAC) Single Collision Frame Register -#define AT91C_EMAC_PFR ((AT91_REG *) 0xFFFDC03C) // (EMAC) Pause Frames received Register -#define AT91C_EMAC_MCF ((AT91_REG *) 0xFFFDC048) // (EMAC) Multiple Collision Frame Register -#define AT91C_EMAC_NSR ((AT91_REG *) 0xFFFDC008) // (EMAC) Network Status Register -#define AT91C_EMAC_SA2L ((AT91_REG *) 0xFFFDC0A0) // (EMAC) Specific Address 2 Bottom, First 4 bytes -#define AT91C_EMAC_FRO ((AT91_REG *) 0xFFFDC04C) // (EMAC) Frames Received OK Register -#define AT91C_EMAC_IER ((AT91_REG *) 0xFFFDC028) // (EMAC) Interrupt Enable Register -#define AT91C_EMAC_SA1H ((AT91_REG *) 0xFFFDC09C) // (EMAC) Specific Address 1 Top, Last 2 bytes -#define AT91C_EMAC_CSE ((AT91_REG *) 0xFFFDC068) // (EMAC) Carrier Sense Error Register -#define AT91C_EMAC_SA3H ((AT91_REG *) 0xFFFDC0AC) // (EMAC) Specific Address 3 Top, Last 2 bytes -#define AT91C_EMAC_RRE ((AT91_REG *) 0xFFFDC06C) // (EMAC) Receive Ressource Error Register -#define AT91C_EMAC_STE ((AT91_REG *) 0xFFFDC084) // (EMAC) SQE Test Error Register -// ========== Register definition for PDC_ADC peripheral ========== -#define AT91C_ADC_PTSR ((AT91_REG *) 0xFFFD8124) // (PDC_ADC) PDC Transfer Status Register -#define AT91C_ADC_PTCR ((AT91_REG *) 0xFFFD8120) // (PDC_ADC) PDC Transfer Control Register -#define AT91C_ADC_TNPR ((AT91_REG *) 0xFFFD8118) // (PDC_ADC) Transmit Next Pointer Register -#define AT91C_ADC_TNCR ((AT91_REG *) 0xFFFD811C) // (PDC_ADC) Transmit Next Counter Register -#define AT91C_ADC_RNPR ((AT91_REG *) 0xFFFD8110) // (PDC_ADC) Receive Next Pointer Register -#define AT91C_ADC_RNCR ((AT91_REG *) 0xFFFD8114) // (PDC_ADC) Receive Next Counter Register -#define AT91C_ADC_RPR ((AT91_REG *) 0xFFFD8100) // (PDC_ADC) Receive Pointer Register -#define AT91C_ADC_TCR ((AT91_REG *) 0xFFFD810C) // (PDC_ADC) Transmit Counter Register -#define AT91C_ADC_TPR ((AT91_REG *) 0xFFFD8108) // (PDC_ADC) Transmit Pointer Register -#define AT91C_ADC_RCR ((AT91_REG *) 0xFFFD8104) // (PDC_ADC) Receive Counter Register -// ========== Register definition for ADC peripheral ========== -#define AT91C_ADC_CDR2 ((AT91_REG *) 0xFFFD8038) // (ADC) ADC Channel Data Register 2 -#define AT91C_ADC_CDR3 ((AT91_REG *) 0xFFFD803C) // (ADC) ADC Channel Data Register 3 -#define AT91C_ADC_CDR0 ((AT91_REG *) 0xFFFD8030) // (ADC) ADC Channel Data Register 0 -#define AT91C_ADC_CDR5 ((AT91_REG *) 0xFFFD8044) // (ADC) ADC Channel Data Register 5 -#define AT91C_ADC_CHDR ((AT91_REG *) 0xFFFD8014) // (ADC) ADC Channel Disable Register -#define AT91C_ADC_SR ((AT91_REG *) 0xFFFD801C) // (ADC) ADC Status Register -#define AT91C_ADC_CDR4 ((AT91_REG *) 0xFFFD8040) // (ADC) ADC Channel Data Register 4 -#define AT91C_ADC_CDR1 ((AT91_REG *) 0xFFFD8034) // (ADC) ADC Channel Data Register 1 -#define AT91C_ADC_LCDR ((AT91_REG *) 0xFFFD8020) // (ADC) ADC Last Converted Data Register -#define AT91C_ADC_IDR ((AT91_REG *) 0xFFFD8028) // (ADC) ADC Interrupt Disable Register -#define AT91C_ADC_CR ((AT91_REG *) 0xFFFD8000) // (ADC) ADC Control Register -#define AT91C_ADC_CDR7 ((AT91_REG *) 0xFFFD804C) // (ADC) ADC Channel Data Register 7 -#define AT91C_ADC_CDR6 ((AT91_REG *) 0xFFFD8048) // (ADC) ADC Channel Data Register 6 -#define AT91C_ADC_IER ((AT91_REG *) 0xFFFD8024) // (ADC) ADC Interrupt Enable Register -#define AT91C_ADC_CHER ((AT91_REG *) 0xFFFD8010) // (ADC) ADC Channel Enable Register -#define AT91C_ADC_CHSR ((AT91_REG *) 0xFFFD8018) // (ADC) ADC Channel Status Register -#define AT91C_ADC_MR ((AT91_REG *) 0xFFFD8004) // (ADC) ADC Mode Register -#define AT91C_ADC_IMR ((AT91_REG *) 0xFFFD802C) // (ADC) ADC Interrupt Mask Register -// ========== Register definition for PDC_AES peripheral ========== -#define AT91C_AES_TPR ((AT91_REG *) 0xFFFA4108) // (PDC_AES) Transmit Pointer Register -#define AT91C_AES_PTCR ((AT91_REG *) 0xFFFA4120) // (PDC_AES) PDC Transfer Control Register -#define AT91C_AES_RNPR ((AT91_REG *) 0xFFFA4110) // (PDC_AES) Receive Next Pointer Register -#define AT91C_AES_TNCR ((AT91_REG *) 0xFFFA411C) // (PDC_AES) Transmit Next Counter Register -#define AT91C_AES_TCR ((AT91_REG *) 0xFFFA410C) // (PDC_AES) Transmit Counter Register -#define AT91C_AES_RCR ((AT91_REG *) 0xFFFA4104) // (PDC_AES) Receive Counter Register -#define AT91C_AES_RNCR ((AT91_REG *) 0xFFFA4114) // (PDC_AES) Receive Next Counter Register -#define AT91C_AES_TNPR ((AT91_REG *) 0xFFFA4118) // (PDC_AES) Transmit Next Pointer Register -#define AT91C_AES_RPR ((AT91_REG *) 0xFFFA4100) // (PDC_AES) Receive Pointer Register -#define AT91C_AES_PTSR ((AT91_REG *) 0xFFFA4124) // (PDC_AES) PDC Transfer Status Register -// ========== Register definition for AES peripheral ========== -#define AT91C_AES_IVxR ((AT91_REG *) 0xFFFA4060) // (AES) Initialization Vector x Register -#define AT91C_AES_MR ((AT91_REG *) 0xFFFA4004) // (AES) Mode Register -#define AT91C_AES_VR ((AT91_REG *) 0xFFFA40FC) // (AES) AES Version Register -#define AT91C_AES_ODATAxR ((AT91_REG *) 0xFFFA4050) // (AES) Output Data x Register -#define AT91C_AES_IDATAxR ((AT91_REG *) 0xFFFA4040) // (AES) Input Data x Register -#define AT91C_AES_CR ((AT91_REG *) 0xFFFA4000) // (AES) Control Register -#define AT91C_AES_IDR ((AT91_REG *) 0xFFFA4014) // (AES) Interrupt Disable Register -#define AT91C_AES_IMR ((AT91_REG *) 0xFFFA4018) // (AES) Interrupt Mask Register -#define AT91C_AES_IER ((AT91_REG *) 0xFFFA4010) // (AES) Interrupt Enable Register -#define AT91C_AES_KEYWxR ((AT91_REG *) 0xFFFA4020) // (AES) Key Word x Register -#define AT91C_AES_ISR ((AT91_REG *) 0xFFFA401C) // (AES) Interrupt Status Register -// ========== Register definition for PDC_TDES peripheral ========== -#define AT91C_TDES_RNCR ((AT91_REG *) 0xFFFA8114) // (PDC_TDES) Receive Next Counter Register -#define AT91C_TDES_TCR ((AT91_REG *) 0xFFFA810C) // (PDC_TDES) Transmit Counter Register -#define AT91C_TDES_RCR ((AT91_REG *) 0xFFFA8104) // (PDC_TDES) Receive Counter Register -#define AT91C_TDES_TNPR ((AT91_REG *) 0xFFFA8118) // (PDC_TDES) Transmit Next Pointer Register -#define AT91C_TDES_RNPR ((AT91_REG *) 0xFFFA8110) // (PDC_TDES) Receive Next Pointer Register -#define AT91C_TDES_RPR ((AT91_REG *) 0xFFFA8100) // (PDC_TDES) Receive Pointer Register -#define AT91C_TDES_TNCR ((AT91_REG *) 0xFFFA811C) // (PDC_TDES) Transmit Next Counter Register -#define AT91C_TDES_TPR ((AT91_REG *) 0xFFFA8108) // (PDC_TDES) Transmit Pointer Register -#define AT91C_TDES_PTSR ((AT91_REG *) 0xFFFA8124) // (PDC_TDES) PDC Transfer Status Register -#define AT91C_TDES_PTCR ((AT91_REG *) 0xFFFA8120) // (PDC_TDES) PDC Transfer Control Register -// ========== Register definition for TDES peripheral ========== -#define AT91C_TDES_KEY2WxR ((AT91_REG *) 0xFFFA8028) // (TDES) Key 2 Word x Register -#define AT91C_TDES_KEY3WxR ((AT91_REG *) 0xFFFA8030) // (TDES) Key 3 Word x Register -#define AT91C_TDES_IDR ((AT91_REG *) 0xFFFA8014) // (TDES) Interrupt Disable Register -#define AT91C_TDES_VR ((AT91_REG *) 0xFFFA80FC) // (TDES) TDES Version Register -#define AT91C_TDES_IVxR ((AT91_REG *) 0xFFFA8060) // (TDES) Initialization Vector x Register -#define AT91C_TDES_ODATAxR ((AT91_REG *) 0xFFFA8050) // (TDES) Output Data x Register -#define AT91C_TDES_IMR ((AT91_REG *) 0xFFFA8018) // (TDES) Interrupt Mask Register -#define AT91C_TDES_MR ((AT91_REG *) 0xFFFA8004) // (TDES) Mode Register -#define AT91C_TDES_CR ((AT91_REG *) 0xFFFA8000) // (TDES) Control Register -#define AT91C_TDES_IER ((AT91_REG *) 0xFFFA8010) // (TDES) Interrupt Enable Register -#define AT91C_TDES_ISR ((AT91_REG *) 0xFFFA801C) // (TDES) Interrupt Status Register -#define AT91C_TDES_IDATAxR ((AT91_REG *) 0xFFFA8040) // (TDES) Input Data x Register -#define AT91C_TDES_KEY1WxR ((AT91_REG *) 0xFFFA8020) // (TDES) Key 1 Word x Register - -// ***************************************************************************** -// PIO DEFINITIONS FOR AT91SAM7X128 -// ***************************************************************************** -#define AT91C_PIO_PA0 ((unsigned int) 1 << 0) // Pin Controlled by PA0 -#define AT91C_PA0_RXD0 ((unsigned int) AT91C_PIO_PA0) // USART 0 Receive Data -#define AT91C_PIO_PA1 ((unsigned int) 1 << 1) // Pin Controlled by PA1 -#define AT91C_PA1_TXD0 ((unsigned int) AT91C_PIO_PA1) // USART 0 Transmit Data -#define AT91C_PIO_PA10 ((unsigned int) 1 << 10) // Pin Controlled by PA10 -#define AT91C_PA10_TWD ((unsigned int) AT91C_PIO_PA10) // TWI Two-wire Serial Data -#define AT91C_PIO_PA11 ((unsigned int) 1 << 11) // Pin Controlled by PA11 -#define AT91C_PA11_TWCK ((unsigned int) AT91C_PIO_PA11) // TWI Two-wire Serial Clock -#define AT91C_PIO_PA12 ((unsigned int) 1 << 12) // Pin Controlled by PA12 -#define AT91C_PA12_NPCS00 ((unsigned int) AT91C_PIO_PA12) // SPI 0 Peripheral Chip Select 0 -#define AT91C_PIO_PA13 ((unsigned int) 1 << 13) // Pin Controlled by PA13 -#define AT91C_PA13_NPCS01 ((unsigned int) AT91C_PIO_PA13) // SPI 0 Peripheral Chip Select 1 -#define AT91C_PA13_PCK1 ((unsigned int) AT91C_PIO_PA13) // PMC Programmable Clock Output 1 -#define AT91C_PIO_PA14 ((unsigned int) 1 << 14) // Pin Controlled by PA14 -#define AT91C_PA14_NPCS02 ((unsigned int) AT91C_PIO_PA14) // SPI 0 Peripheral Chip Select 2 -#define AT91C_PA14_IRQ1 ((unsigned int) AT91C_PIO_PA14) // External Interrupt 1 -#define AT91C_PIO_PA15 ((unsigned int) 1 << 15) // Pin Controlled by PA15 -#define AT91C_PA15_NPCS03 ((unsigned int) AT91C_PIO_PA15) // SPI 0 Peripheral Chip Select 3 -#define AT91C_PA15_TCLK2 ((unsigned int) AT91C_PIO_PA15) // Timer Counter 2 external clock input -#define AT91C_PIO_PA16 ((unsigned int) 1 << 16) // Pin Controlled by PA16 -#define AT91C_PA16_MISO0 ((unsigned int) AT91C_PIO_PA16) // SPI 0 Master In Slave -#define AT91C_PIO_PA17 ((unsigned int) 1 << 17) // Pin Controlled by PA17 -#define AT91C_PA17_MOSI0 ((unsigned int) AT91C_PIO_PA17) // SPI 0 Master Out Slave -#define AT91C_PIO_PA18 ((unsigned int) 1 << 18) // Pin Controlled by PA18 -#define AT91C_PA18_SPCK0 ((unsigned int) AT91C_PIO_PA18) // SPI 0 Serial Clock -#define AT91C_PIO_PA19 ((unsigned int) 1 << 19) // Pin Controlled by PA19 -#define AT91C_PA19_CANRX ((unsigned int) AT91C_PIO_PA19) // CAN Receive -#define AT91C_PIO_PA2 ((unsigned int) 1 << 2) // Pin Controlled by PA2 -#define AT91C_PA2_SCK0 ((unsigned int) AT91C_PIO_PA2) // USART 0 Serial Clock -#define AT91C_PA2_NPCS11 ((unsigned int) AT91C_PIO_PA2) // SPI 1 Peripheral Chip Select 1 -#define AT91C_PIO_PA20 ((unsigned int) 1 << 20) // Pin Controlled by PA20 -#define AT91C_PA20_CANTX ((unsigned int) AT91C_PIO_PA20) // CAN Transmit -#define AT91C_PIO_PA21 ((unsigned int) 1 << 21) // Pin Controlled by PA21 -#define AT91C_PA21_TF ((unsigned int) AT91C_PIO_PA21) // SSC Transmit Frame Sync -#define AT91C_PA21_NPCS10 ((unsigned int) AT91C_PIO_PA21) // SPI 1 Peripheral Chip Select 0 -#define AT91C_PIO_PA22 ((unsigned int) 1 << 22) // Pin Controlled by PA22 -#define AT91C_PA22_TK ((unsigned int) AT91C_PIO_PA22) // SSC Transmit Clock -#define AT91C_PA22_SPCK1 ((unsigned int) AT91C_PIO_PA22) // SPI 1 Serial Clock -#define AT91C_PIO_PA23 ((unsigned int) 1 << 23) // Pin Controlled by PA23 -#define AT91C_PA23_TD ((unsigned int) AT91C_PIO_PA23) // SSC Transmit data -#define AT91C_PA23_MOSI1 ((unsigned int) AT91C_PIO_PA23) // SPI 1 Master Out Slave -#define AT91C_PIO_PA24 ((unsigned int) 1 << 24) // Pin Controlled by PA24 -#define AT91C_PA24_RD ((unsigned int) AT91C_PIO_PA24) // SSC Receive Data -#define AT91C_PA24_MISO1 ((unsigned int) AT91C_PIO_PA24) // SPI 1 Master In Slave -#define AT91C_PIO_PA25 ((unsigned int) 1 << 25) // Pin Controlled by PA25 -#define AT91C_PA25_RK ((unsigned int) AT91C_PIO_PA25) // SSC Receive Clock -#define AT91C_PA25_NPCS11 ((unsigned int) AT91C_PIO_PA25) // SPI 1 Peripheral Chip Select 1 -#define AT91C_PIO_PA26 ((unsigned int) 1 << 26) // Pin Controlled by PA26 -#define AT91C_PA26_RF ((unsigned int) AT91C_PIO_PA26) // SSC Receive Frame Sync -#define AT91C_PA26_NPCS12 ((unsigned int) AT91C_PIO_PA26) // SPI 1 Peripheral Chip Select 2 -#define AT91C_PIO_PA27 ((unsigned int) 1 << 27) // Pin Controlled by PA27 -#define AT91C_PA27_DRXD ((unsigned int) AT91C_PIO_PA27) // DBGU Debug Receive Data -#define AT91C_PA27_PCK3 ((unsigned int) AT91C_PIO_PA27) // PMC Programmable Clock Output 3 -#define AT91C_PIO_PA28 ((unsigned int) 1 << 28) // Pin Controlled by PA28 -#define AT91C_PA28_DTXD ((unsigned int) AT91C_PIO_PA28) // DBGU Debug Transmit Data -#define AT91C_PIO_PA29 ((unsigned int) 1 << 29) // Pin Controlled by PA29 -#define AT91C_PA29_FIQ ((unsigned int) AT91C_PIO_PA29) // AIC Fast Interrupt Input -#define AT91C_PA29_NPCS13 ((unsigned int) AT91C_PIO_PA29) // SPI 1 Peripheral Chip Select 3 -#define AT91C_PIO_PA3 ((unsigned int) 1 << 3) // Pin Controlled by PA3 -#define AT91C_PA3_RTS0 ((unsigned int) AT91C_PIO_PA3) // USART 0 Ready To Send -#define AT91C_PA3_NPCS12 ((unsigned int) AT91C_PIO_PA3) // SPI 1 Peripheral Chip Select 2 -#define AT91C_PIO_PA30 ((unsigned int) 1 << 30) // Pin Controlled by PA30 -#define AT91C_PA30_IRQ0 ((unsigned int) AT91C_PIO_PA30) // External Interrupt 0 -#define AT91C_PA30_PCK2 ((unsigned int) AT91C_PIO_PA30) // PMC Programmable Clock Output 2 -#define AT91C_PIO_PA4 ((unsigned int) 1 << 4) // Pin Controlled by PA4 -#define AT91C_PA4_CTS0 ((unsigned int) AT91C_PIO_PA4) // USART 0 Clear To Send -#define AT91C_PA4_NPCS13 ((unsigned int) AT91C_PIO_PA4) // SPI 1 Peripheral Chip Select 3 -#define AT91C_PIO_PA5 ((unsigned int) 1 << 5) // Pin Controlled by PA5 -#define AT91C_PA5_RXD1 ((unsigned int) AT91C_PIO_PA5) // USART 1 Receive Data -#define AT91C_PIO_PA6 ((unsigned int) 1 << 6) // Pin Controlled by PA6 -#define AT91C_PA6_TXD1 ((unsigned int) AT91C_PIO_PA6) // USART 1 Transmit Data -#define AT91C_PIO_PA7 ((unsigned int) 1 << 7) // Pin Controlled by PA7 -#define AT91C_PA7_SCK1 ((unsigned int) AT91C_PIO_PA7) // USART 1 Serial Clock -#define AT91C_PA7_NPCS01 ((unsigned int) AT91C_PIO_PA7) // SPI 0 Peripheral Chip Select 1 -#define AT91C_PIO_PA8 ((unsigned int) 1 << 8) // Pin Controlled by PA8 -#define AT91C_PA8_RTS1 ((unsigned int) AT91C_PIO_PA8) // USART 1 Ready To Send -#define AT91C_PA8_NPCS02 ((unsigned int) AT91C_PIO_PA8) // SPI 0 Peripheral Chip Select 2 -#define AT91C_PIO_PA9 ((unsigned int) 1 << 9) // Pin Controlled by PA9 -#define AT91C_PA9_CTS1 ((unsigned int) AT91C_PIO_PA9) // USART 1 Clear To Send -#define AT91C_PA9_NPCS03 ((unsigned int) AT91C_PIO_PA9) // SPI 0 Peripheral Chip Select 3 -#define AT91C_PIO_PB0 ((unsigned int) 1 << 0) // Pin Controlled by PB0 -#define AT91C_PB0_ETXCK_EREFCK ((unsigned int) AT91C_PIO_PB0) // Ethernet MAC Transmit Clock/Reference Clock -#define AT91C_PB0_PCK0 ((unsigned int) AT91C_PIO_PB0) // PMC Programmable Clock Output 0 -#define AT91C_PIO_PB1 ((unsigned int) 1 << 1) // Pin Controlled by PB1 -#define AT91C_PB1_ETXEN ((unsigned int) AT91C_PIO_PB1) // Ethernet MAC Transmit Enable -#define AT91C_PIO_PB10 ((unsigned int) 1 << 10) // Pin Controlled by PB10 -#define AT91C_PB10_ETX2 ((unsigned int) AT91C_PIO_PB10) // Ethernet MAC Transmit Data 2 -#define AT91C_PB10_NPCS11 ((unsigned int) AT91C_PIO_PB10) // SPI 1 Peripheral Chip Select 1 -#define AT91C_PIO_PB11 ((unsigned int) 1 << 11) // Pin Controlled by PB11 -#define AT91C_PB11_ETX3 ((unsigned int) AT91C_PIO_PB11) // Ethernet MAC Transmit Data 3 -#define AT91C_PB11_NPCS12 ((unsigned int) AT91C_PIO_PB11) // SPI 1 Peripheral Chip Select 2 -#define AT91C_PIO_PB12 ((unsigned int) 1 << 12) // Pin Controlled by PB12 -#define AT91C_PB12_ETXER ((unsigned int) AT91C_PIO_PB12) // Ethernet MAC Transmikt Coding Error -#define AT91C_PB12_TCLK0 ((unsigned int) AT91C_PIO_PB12) // Timer Counter 0 external clock input -#define AT91C_PIO_PB13 ((unsigned int) 1 << 13) // Pin Controlled by PB13 -#define AT91C_PB13_ERX2 ((unsigned int) AT91C_PIO_PB13) // Ethernet MAC Receive Data 2 -#define AT91C_PB13_NPCS01 ((unsigned int) AT91C_PIO_PB13) // SPI 0 Peripheral Chip Select 1 -#define AT91C_PIO_PB14 ((unsigned int) 1 << 14) // Pin Controlled by PB14 -#define AT91C_PB14_ERX3 ((unsigned int) AT91C_PIO_PB14) // Ethernet MAC Receive Data 3 -#define AT91C_PB14_NPCS02 ((unsigned int) AT91C_PIO_PB14) // SPI 0 Peripheral Chip Select 2 -#define AT91C_PIO_PB15 ((unsigned int) 1 << 15) // Pin Controlled by PB15 -#define AT91C_PB15_ERXDV ((unsigned int) AT91C_PIO_PB15) // Ethernet MAC Receive Data Valid -#define AT91C_PIO_PB16 ((unsigned int) 1 << 16) // Pin Controlled by PB16 -#define AT91C_PB16_ECOL ((unsigned int) AT91C_PIO_PB16) // Ethernet MAC Collision Detected -#define AT91C_PB16_NPCS13 ((unsigned int) AT91C_PIO_PB16) // SPI 1 Peripheral Chip Select 3 -#define AT91C_PIO_PB17 ((unsigned int) 1 << 17) // Pin Controlled by PB17 -#define AT91C_PB17_ERXCK ((unsigned int) AT91C_PIO_PB17) // Ethernet MAC Receive Clock -#define AT91C_PB17_NPCS03 ((unsigned int) AT91C_PIO_PB17) // SPI 0 Peripheral Chip Select 3 -#define AT91C_PIO_PB18 ((unsigned int) 1 << 18) // Pin Controlled by PB18 -#define AT91C_PB18_EF100 ((unsigned int) AT91C_PIO_PB18) // Ethernet MAC Force 100 Mbits/sec -#define AT91C_PB18_ADTRG ((unsigned int) AT91C_PIO_PB18) // ADC External Trigger -#define AT91C_PIO_PB19 ((unsigned int) 1 << 19) // Pin Controlled by PB19 -#define AT91C_PB19_PWM0 ((unsigned int) AT91C_PIO_PB19) // PWM Channel 0 -#define AT91C_PB19_TCLK1 ((unsigned int) AT91C_PIO_PB19) // Timer Counter 1 external clock input -#define AT91C_PIO_PB2 ((unsigned int) 1 << 2) // Pin Controlled by PB2 -#define AT91C_PB2_ETX0 ((unsigned int) AT91C_PIO_PB2) // Ethernet MAC Transmit Data 0 -#define AT91C_PIO_PB20 ((unsigned int) 1 << 20) // Pin Controlled by PB20 -#define AT91C_PB20_PWM1 ((unsigned int) AT91C_PIO_PB20) // PWM Channel 1 -#define AT91C_PB20_PCK0 ((unsigned int) AT91C_PIO_PB20) // PMC Programmable Clock Output 0 -#define AT91C_PIO_PB21 ((unsigned int) 1 << 21) // Pin Controlled by PB21 -#define AT91C_PB21_PWM2 ((unsigned int) AT91C_PIO_PB21) // PWM Channel 2 -#define AT91C_PB21_PCK1 ((unsigned int) AT91C_PIO_PB21) // PMC Programmable Clock Output 1 -#define AT91C_PIO_PB22 ((unsigned int) 1 << 22) // Pin Controlled by PB22 -#define AT91C_PB22_PWM3 ((unsigned int) AT91C_PIO_PB22) // PWM Channel 3 -#define AT91C_PB22_PCK2 ((unsigned int) AT91C_PIO_PB22) // PMC Programmable Clock Output 2 -#define AT91C_PIO_PB23 ((unsigned int) 1 << 23) // Pin Controlled by PB23 -#define AT91C_PB23_TIOA0 ((unsigned int) AT91C_PIO_PB23) // Timer Counter 0 Multipurpose Timer I/O Pin A -#define AT91C_PB23_DCD1 ((unsigned int) AT91C_PIO_PB23) // USART 1 Data Carrier Detect -#define AT91C_PIO_PB24 ((unsigned int) 1 << 24) // Pin Controlled by PB24 -#define AT91C_PB24_TIOB0 ((unsigned int) AT91C_PIO_PB24) // Timer Counter 0 Multipurpose Timer I/O Pin B -#define AT91C_PB24_DSR1 ((unsigned int) AT91C_PIO_PB24) // USART 1 Data Set ready -#define AT91C_PIO_PB25 ((unsigned int) 1 << 25) // Pin Controlled by PB25 -#define AT91C_PB25_TIOA1 ((unsigned int) AT91C_PIO_PB25) // Timer Counter 1 Multipurpose Timer I/O Pin A -#define AT91C_PB25_DTR1 ((unsigned int) AT91C_PIO_PB25) // USART 1 Data Terminal ready -#define AT91C_PIO_PB26 ((unsigned int) 1 << 26) // Pin Controlled by PB26 -#define AT91C_PB26_TIOB1 ((unsigned int) AT91C_PIO_PB26) // Timer Counter 1 Multipurpose Timer I/O Pin B -#define AT91C_PB26_RI1 ((unsigned int) AT91C_PIO_PB26) // USART 1 Ring Indicator -#define AT91C_PIO_PB27 ((unsigned int) 1 << 27) // Pin Controlled by PB27 -#define AT91C_PB27_TIOA2 ((unsigned int) AT91C_PIO_PB27) // Timer Counter 2 Multipurpose Timer I/O Pin A -#define AT91C_PB27_PWM0 ((unsigned int) AT91C_PIO_PB27) // PWM Channel 0 -#define AT91C_PIO_PB28 ((unsigned int) 1 << 28) // Pin Controlled by PB28 -#define AT91C_PB28_TIOB2 ((unsigned int) AT91C_PIO_PB28) // Timer Counter 2 Multipurpose Timer I/O Pin B -#define AT91C_PB28_PWM1 ((unsigned int) AT91C_PIO_PB28) // PWM Channel 1 -#define AT91C_PIO_PB29 ((unsigned int) 1 << 29) // Pin Controlled by PB29 -#define AT91C_PB29_PCK1 ((unsigned int) AT91C_PIO_PB29) // PMC Programmable Clock Output 1 -#define AT91C_PB29_PWM2 ((unsigned int) AT91C_PIO_PB29) // PWM Channel 2 -#define AT91C_PIO_PB3 ((unsigned int) 1 << 3) // Pin Controlled by PB3 -#define AT91C_PB3_ETX1 ((unsigned int) AT91C_PIO_PB3) // Ethernet MAC Transmit Data 1 -#define AT91C_PIO_PB30 ((unsigned int) 1 << 30) // Pin Controlled by PB30 -#define AT91C_PB30_PCK2 ((unsigned int) AT91C_PIO_PB30) // PMC Programmable Clock Output 2 -#define AT91C_PB30_PWM3 ((unsigned int) AT91C_PIO_PB30) // PWM Channel 3 -#define AT91C_PIO_PB4 ((unsigned int) 1 << 4) // Pin Controlled by PB4 -#define AT91C_PB4_ECRS_ECRSDV ((unsigned int) AT91C_PIO_PB4) // Ethernet MAC Carrier Sense/Carrier Sense and Data Valid -#define AT91C_PIO_PB5 ((unsigned int) 1 << 5) // Pin Controlled by PB5 -#define AT91C_PB5_ERX0 ((unsigned int) AT91C_PIO_PB5) // Ethernet MAC Receive Data 0 -#define AT91C_PIO_PB6 ((unsigned int) 1 << 6) // Pin Controlled by PB6 -#define AT91C_PB6_ERX1 ((unsigned int) AT91C_PIO_PB6) // Ethernet MAC Receive Data 1 -#define AT91C_PIO_PB7 ((unsigned int) 1 << 7) // Pin Controlled by PB7 -#define AT91C_PB7_ERXER ((unsigned int) AT91C_PIO_PB7) // Ethernet MAC Receive Error -#define AT91C_PIO_PB8 ((unsigned int) 1 << 8) // Pin Controlled by PB8 -#define AT91C_PB8_EMDC ((unsigned int) AT91C_PIO_PB8) // Ethernet MAC Management Data Clock -#define AT91C_PIO_PB9 ((unsigned int) 1 << 9) // Pin Controlled by PB9 -#define AT91C_PB9_EMDIO ((unsigned int) AT91C_PIO_PB9) // Ethernet MAC Management Data Input/Output - -// ***************************************************************************** -// PERIPHERAL ID DEFINITIONS FOR AT91SAM7X128 -// ***************************************************************************** -#define AT91C_ID_FIQ ((unsigned int) 0) // Advanced Interrupt Controller (FIQ) -#define AT91C_ID_SYS ((unsigned int) 1) // System Peripheral -#define AT91C_ID_PIOA ((unsigned int) 2) // Parallel IO Controller A -#define AT91C_ID_PIOB ((unsigned int) 3) // Parallel IO Controller B -#define AT91C_ID_SPI0 ((unsigned int) 4) // Serial Peripheral Interface 0 -#define AT91C_ID_SPI1 ((unsigned int) 5) // Serial Peripheral Interface 1 -#define AT91C_ID_US0 ((unsigned int) 6) // USART 0 -#define AT91C_ID_US1 ((unsigned int) 7) // USART 1 -#define AT91C_ID_SSC ((unsigned int) 8) // Serial Synchronous Controller -#define AT91C_ID_TWI ((unsigned int) 9) // Two-Wire Interface -#define AT91C_ID_PWMC ((unsigned int) 10) // PWM Controller -#define AT91C_ID_UDP ((unsigned int) 11) // USB Device Port -#define AT91C_ID_TC0 ((unsigned int) 12) // Timer Counter 0 -#define AT91C_ID_TC1 ((unsigned int) 13) // Timer Counter 1 -#define AT91C_ID_TC2 ((unsigned int) 14) // Timer Counter 2 -#define AT91C_ID_CAN ((unsigned int) 15) // Control Area Network Controller -#define AT91C_ID_EMAC ((unsigned int) 16) // Ethernet MAC -#define AT91C_ID_ADC ((unsigned int) 17) // Analog-to-Digital Converter -#define AT91C_ID_AES ((unsigned int) 18) // Advanced Encryption Standard 128-bit -#define AT91C_ID_TDES ((unsigned int) 19) // Triple Data Encryption Standard -#define AT91C_ID_20_Reserved ((unsigned int) 20) // Reserved -#define AT91C_ID_21_Reserved ((unsigned int) 21) // Reserved -#define AT91C_ID_22_Reserved ((unsigned int) 22) // Reserved -#define AT91C_ID_23_Reserved ((unsigned int) 23) // Reserved -#define AT91C_ID_24_Reserved ((unsigned int) 24) // Reserved -#define AT91C_ID_25_Reserved ((unsigned int) 25) // Reserved -#define AT91C_ID_26_Reserved ((unsigned int) 26) // Reserved -#define AT91C_ID_27_Reserved ((unsigned int) 27) // Reserved -#define AT91C_ID_28_Reserved ((unsigned int) 28) // Reserved -#define AT91C_ID_29_Reserved ((unsigned int) 29) // Reserved -#define AT91C_ID_IRQ0 ((unsigned int) 30) // Advanced Interrupt Controller (IRQ0) -#define AT91C_ID_IRQ1 ((unsigned int) 31) // Advanced Interrupt Controller (IRQ1) - -// ***************************************************************************** -// BASE ADDRESS DEFINITIONS FOR AT91SAM7X128 -// ***************************************************************************** -#define AT91C_BASE_SYS ((AT91PS_SYS) 0xFFFFF000) // (SYS) Base Address -#define AT91C_BASE_AIC ((AT91PS_AIC) 0xFFFFF000) // (AIC) Base Address -#define AT91C_BASE_PDC_DBGU ((AT91PS_PDC) 0xFFFFF300) // (PDC_DBGU) Base Address -#define AT91C_BASE_DBGU ((AT91PS_DBGU) 0xFFFFF200) // (DBGU) Base Address -#define AT91C_BASE_PIOA ((AT91PS_PIO) 0xFFFFF400) // (PIOA) Base Address -#define AT91C_BASE_PIOB ((AT91PS_PIO) 0xFFFFF600) // (PIOB) Base Address -#define AT91C_BASE_CKGR ((AT91PS_CKGR) 0xFFFFFC20) // (CKGR) Base Address -#define AT91C_BASE_PMC ((AT91PS_PMC) 0xFFFFFC00) // (PMC) Base Address -#define AT91C_BASE_RSTC ((AT91PS_RSTC) 0xFFFFFD00) // (RSTC) Base Address -#define AT91C_BASE_RTTC ((AT91PS_RTTC) 0xFFFFFD20) // (RTTC) Base Address -#define AT91C_BASE_PITC ((AT91PS_PITC) 0xFFFFFD30) // (PITC) Base Address -#define AT91C_BASE_WDTC ((AT91PS_WDTC) 0xFFFFFD40) // (WDTC) Base Address -#define AT91C_BASE_VREG ((AT91PS_VREG) 0xFFFFFD60) // (VREG) Base Address -#define AT91C_BASE_MC ((AT91PS_MC) 0xFFFFFF00) // (MC) Base Address -#define AT91C_BASE_PDC_SPI1 ((AT91PS_PDC) 0xFFFE4100) // (PDC_SPI1) Base Address -#define AT91C_BASE_SPI1 ((AT91PS_SPI) 0xFFFE4000) // (SPI1) Base Address -#define AT91C_BASE_PDC_SPI0 ((AT91PS_PDC) 0xFFFE0100) // (PDC_SPI0) Base Address -#define AT91C_BASE_SPI0 ((AT91PS_SPI) 0xFFFE0000) // (SPI0) Base Address -#define AT91C_BASE_PDC_US1 ((AT91PS_PDC) 0xFFFC4100) // (PDC_US1) Base Address -#define AT91C_BASE_US1 ((AT91PS_USART) 0xFFFC4000) // (US1) Base Address -#define AT91C_BASE_PDC_US0 ((AT91PS_PDC) 0xFFFC0100) // (PDC_US0) Base Address -#define AT91C_BASE_US0 ((AT91PS_USART) 0xFFFC0000) // (US0) Base Address -#define AT91C_BASE_PDC_SSC ((AT91PS_PDC) 0xFFFD4100) // (PDC_SSC) Base Address -#define AT91C_BASE_SSC ((AT91PS_SSC) 0xFFFD4000) // (SSC) Base Address -#define AT91C_BASE_TWI ((AT91PS_TWI) 0xFFFB8000) // (TWI) Base Address -#define AT91C_BASE_PWMC_CH3 ((AT91PS_PWMC_CH) 0xFFFCC260) // (PWMC_CH3) Base Address -#define AT91C_BASE_PWMC_CH2 ((AT91PS_PWMC_CH) 0xFFFCC240) // (PWMC_CH2) Base Address -#define AT91C_BASE_PWMC_CH1 ((AT91PS_PWMC_CH) 0xFFFCC220) // (PWMC_CH1) Base Address -#define AT91C_BASE_PWMC_CH0 ((AT91PS_PWMC_CH) 0xFFFCC200) // (PWMC_CH0) Base Address -#define AT91C_BASE_PWMC ((AT91PS_PWMC) 0xFFFCC000) // (PWMC) Base Address -#define AT91C_BASE_UDP ((AT91PS_UDP) 0xFFFB0000) // (UDP) Base Address -#define AT91C_BASE_TC0 ((AT91PS_TC) 0xFFFA0000) // (TC0) Base Address -#define AT91C_BASE_TC1 ((AT91PS_TC) 0xFFFA0040) // (TC1) Base Address -#define AT91C_BASE_TC2 ((AT91PS_TC) 0xFFFA0080) // (TC2) Base Address -#define AT91C_BASE_TCB ((AT91PS_TCB) 0xFFFA0000) // (TCB) Base Address -#define AT91C_BASE_CAN_MB0 ((AT91PS_CAN_MB) 0xFFFD0200) // (CAN_MB0) Base Address -#define AT91C_BASE_CAN_MB1 ((AT91PS_CAN_MB) 0xFFFD0220) // (CAN_MB1) Base Address -#define AT91C_BASE_CAN_MB2 ((AT91PS_CAN_MB) 0xFFFD0240) // (CAN_MB2) Base Address -#define AT91C_BASE_CAN_MB3 ((AT91PS_CAN_MB) 0xFFFD0260) // (CAN_MB3) Base Address -#define AT91C_BASE_CAN_MB4 ((AT91PS_CAN_MB) 0xFFFD0280) // (CAN_MB4) Base Address -#define AT91C_BASE_CAN_MB5 ((AT91PS_CAN_MB) 0xFFFD02A0) // (CAN_MB5) Base Address -#define AT91C_BASE_CAN_MB6 ((AT91PS_CAN_MB) 0xFFFD02C0) // (CAN_MB6) Base Address -#define AT91C_BASE_CAN_MB7 ((AT91PS_CAN_MB) 0xFFFD02E0) // (CAN_MB7) Base Address -#define AT91C_BASE_CAN ((AT91PS_CAN) 0xFFFD0000) // (CAN) Base Address -#define AT91C_BASE_EMAC ((AT91PS_EMAC) 0xFFFDC000) // (EMAC) Base Address -#define AT91C_BASE_PDC_ADC ((AT91PS_PDC) 0xFFFD8100) // (PDC_ADC) Base Address -#define AT91C_BASE_ADC ((AT91PS_ADC) 0xFFFD8000) // (ADC) Base Address -#define AT91C_BASE_PDC_AES ((AT91PS_PDC) 0xFFFA4100) // (PDC_AES) Base Address -#define AT91C_BASE_AES ((AT91PS_AES) 0xFFFA4000) // (AES) Base Address -#define AT91C_BASE_PDC_TDES ((AT91PS_PDC) 0xFFFA8100) // (PDC_TDES) Base Address -#define AT91C_BASE_TDES ((AT91PS_TDES) 0xFFFA8000) // (TDES) Base Address - -// ***************************************************************************** -// MEMORY MAPPING DEFINITIONS FOR AT91SAM7X128 -// ***************************************************************************** -#define AT91C_ISRAM ((char *) 0x00200000) // Internal SRAM base address -#define AT91C_ISRAM_SIZE ((unsigned int) 0x00008000) // Internal SRAM size in byte (32 Kbyte) -#define AT91C_IFLASH ((char *) 0x00100000) // Internal ROM base address -#define AT91C_IFLASH_SIZE ((unsigned int) 0x00020000) // Internal ROM size in byte (128 Kbyte) - -#endif +typedef volatile unsigned int AT91_REG; /* Hardware register definition */ + +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR System Peripherals */ +/* ***************************************************************************** */ +typedef struct _AT91S_SYS +{ + AT91_REG AIC_SMR[ 32 ]; /* Source Mode Register */ + AT91_REG AIC_SVR[ 32 ]; /* Source Vector Register */ + AT91_REG AIC_IVR; /* IRQ Vector Register */ + AT91_REG AIC_FVR; /* FIQ Vector Register */ + AT91_REG AIC_ISR; /* Interrupt Status Register */ + AT91_REG AIC_IPR; /* Interrupt Pending Register */ + AT91_REG AIC_IMR; /* Interrupt Mask Register */ + AT91_REG AIC_CISR; /* Core Interrupt Status Register */ + AT91_REG Reserved0[ 2 ]; /* */ + AT91_REG AIC_IECR; /* Interrupt Enable Command Register */ + AT91_REG AIC_IDCR; /* Interrupt Disable Command Register */ + AT91_REG AIC_ICCR; /* Interrupt Clear Command Register */ + AT91_REG AIC_ISCR; /* Interrupt Set Command Register */ + AT91_REG AIC_EOICR; /* End of Interrupt Command Register */ + AT91_REG AIC_SPU; /* Spurious Vector Register */ + AT91_REG AIC_DCR; /* Debug Control Register (Protect) */ + AT91_REG Reserved1[ 1 ]; /* */ + AT91_REG AIC_FFER; /* Fast Forcing Enable Register */ + AT91_REG AIC_FFDR; /* Fast Forcing Disable Register */ + AT91_REG AIC_FFSR; /* Fast Forcing Status Register */ + AT91_REG Reserved2[ 45 ]; /* */ + AT91_REG DBGU_CR; /* Control Register */ + AT91_REG DBGU_MR; /* Mode Register */ + AT91_REG DBGU_IER; /* Interrupt Enable Register */ + AT91_REG DBGU_IDR; /* Interrupt Disable Register */ + AT91_REG DBGU_IMR; /* Interrupt Mask Register */ + AT91_REG DBGU_CSR; /* Channel Status Register */ + AT91_REG DBGU_RHR; /* Receiver Holding Register */ + AT91_REG DBGU_THR; /* Transmitter Holding Register */ + AT91_REG DBGU_BRGR; /* Baud Rate Generator Register */ + AT91_REG Reserved3[ 7 ]; /* */ + AT91_REG DBGU_CIDR; /* Chip ID Register */ + AT91_REG DBGU_EXID; /* Chip ID Extension Register */ + AT91_REG DBGU_FNTR; /* Force NTRST Register */ + AT91_REG Reserved4[ 45 ]; /* */ + AT91_REG DBGU_RPR; /* Receive Pointer Register */ + AT91_REG DBGU_RCR; /* Receive Counter Register */ + AT91_REG DBGU_TPR; /* Transmit Pointer Register */ + AT91_REG DBGU_TCR; /* Transmit Counter Register */ + AT91_REG DBGU_RNPR; /* Receive Next Pointer Register */ + AT91_REG DBGU_RNCR; /* Receive Next Counter Register */ + AT91_REG DBGU_TNPR; /* Transmit Next Pointer Register */ + AT91_REG DBGU_TNCR; /* Transmit Next Counter Register */ + AT91_REG DBGU_PTCR; /* PDC Transfer Control Register */ + AT91_REG DBGU_PTSR; /* PDC Transfer Status Register */ + AT91_REG Reserved5[ 54 ]; /* */ + AT91_REG PIOA_PER; /* PIO Enable Register */ + AT91_REG PIOA_PDR; /* PIO Disable Register */ + AT91_REG PIOA_PSR; /* PIO Status Register */ + AT91_REG Reserved6[ 1 ]; /* */ + AT91_REG PIOA_OER; /* Output Enable Register */ + AT91_REG PIOA_ODR; /* Output Disable Registerr */ + AT91_REG PIOA_OSR; /* Output Status Register */ + AT91_REG Reserved7[ 1 ]; /* */ + AT91_REG PIOA_IFER; /* Input Filter Enable Register */ + AT91_REG PIOA_IFDR; /* Input Filter Disable Register */ + AT91_REG PIOA_IFSR; /* Input Filter Status Register */ + AT91_REG Reserved8[ 1 ]; /* */ + AT91_REG PIOA_SODR; /* Set Output Data Register */ + AT91_REG PIOA_CODR; /* Clear Output Data Register */ + AT91_REG PIOA_ODSR; /* Output Data Status Register */ + AT91_REG PIOA_PDSR; /* Pin Data Status Register */ + AT91_REG PIOA_IER; /* Interrupt Enable Register */ + AT91_REG PIOA_IDR; /* Interrupt Disable Register */ + AT91_REG PIOA_IMR; /* Interrupt Mask Register */ + AT91_REG PIOA_ISR; /* Interrupt Status Register */ + AT91_REG PIOA_MDER; /* Multi-driver Enable Register */ + AT91_REG PIOA_MDDR; /* Multi-driver Disable Register */ + AT91_REG PIOA_MDSR; /* Multi-driver Status Register */ + AT91_REG Reserved9[ 1 ]; /* */ + AT91_REG PIOA_PPUDR; /* Pull-up Disable Register */ + AT91_REG PIOA_PPUER; /* Pull-up Enable Register */ + AT91_REG PIOA_PPUSR; /* Pull-up Status Register */ + AT91_REG Reserved10[ 1 ]; /* */ + AT91_REG PIOA_ASR; /* Select A Register */ + AT91_REG PIOA_BSR; /* Select B Register */ + AT91_REG PIOA_ABSR; /* AB Select Status Register */ + AT91_REG Reserved11[ 9 ]; /* */ + AT91_REG PIOA_OWER; /* Output Write Enable Register */ + AT91_REG PIOA_OWDR; /* Output Write Disable Register */ + AT91_REG PIOA_OWSR; /* Output Write Status Register */ + AT91_REG Reserved12[ 85 ]; /* */ + AT91_REG PIOB_PER; /* PIO Enable Register */ + AT91_REG PIOB_PDR; /* PIO Disable Register */ + AT91_REG PIOB_PSR; /* PIO Status Register */ + AT91_REG Reserved13[ 1 ]; /* */ + AT91_REG PIOB_OER; /* Output Enable Register */ + AT91_REG PIOB_ODR; /* Output Disable Registerr */ + AT91_REG PIOB_OSR; /* Output Status Register */ + AT91_REG Reserved14[ 1 ]; /* */ + AT91_REG PIOB_IFER; /* Input Filter Enable Register */ + AT91_REG PIOB_IFDR; /* Input Filter Disable Register */ + AT91_REG PIOB_IFSR; /* Input Filter Status Register */ + AT91_REG Reserved15[ 1 ]; /* */ + AT91_REG PIOB_SODR; /* Set Output Data Register */ + AT91_REG PIOB_CODR; /* Clear Output Data Register */ + AT91_REG PIOB_ODSR; /* Output Data Status Register */ + AT91_REG PIOB_PDSR; /* Pin Data Status Register */ + AT91_REG PIOB_IER; /* Interrupt Enable Register */ + AT91_REG PIOB_IDR; /* Interrupt Disable Register */ + AT91_REG PIOB_IMR; /* Interrupt Mask Register */ + AT91_REG PIOB_ISR; /* Interrupt Status Register */ + AT91_REG PIOB_MDER; /* Multi-driver Enable Register */ + AT91_REG PIOB_MDDR; /* Multi-driver Disable Register */ + AT91_REG PIOB_MDSR; /* Multi-driver Status Register */ + AT91_REG Reserved16[ 1 ]; /* */ + AT91_REG PIOB_PPUDR; /* Pull-up Disable Register */ + AT91_REG PIOB_PPUER; /* Pull-up Enable Register */ + AT91_REG PIOB_PPUSR; /* Pull-up Status Register */ + AT91_REG Reserved17[ 1 ]; /* */ + AT91_REG PIOB_ASR; /* Select A Register */ + AT91_REG PIOB_BSR; /* Select B Register */ + AT91_REG PIOB_ABSR; /* AB Select Status Register */ + AT91_REG Reserved18[ 9 ]; /* */ + AT91_REG PIOB_OWER; /* Output Write Enable Register */ + AT91_REG PIOB_OWDR; /* Output Write Disable Register */ + AT91_REG PIOB_OWSR; /* Output Write Status Register */ + AT91_REG Reserved19[ 341 ]; /* */ + AT91_REG PMC_SCER; /* System Clock Enable Register */ + AT91_REG PMC_SCDR; /* System Clock Disable Register */ + AT91_REG PMC_SCSR; /* System Clock Status Register */ + AT91_REG Reserved20[ 1 ]; /* */ + AT91_REG PMC_PCER; /* Peripheral Clock Enable Register */ + AT91_REG PMC_PCDR; /* Peripheral Clock Disable Register */ + AT91_REG PMC_PCSR; /* Peripheral Clock Status Register */ + AT91_REG Reserved21[ 1 ]; /* */ + AT91_REG PMC_MOR; /* Main Oscillator Register */ + AT91_REG PMC_MCFR; /* Main Clock Frequency Register */ + AT91_REG Reserved22[ 1 ]; /* */ + AT91_REG PMC_PLLR; /* PLL Register */ + AT91_REG PMC_MCKR; /* Master Clock Register */ + AT91_REG Reserved23[ 3 ]; /* */ + AT91_REG PMC_PCKR[ 4 ]; /* Programmable Clock Register */ + AT91_REG Reserved24[ 4 ]; /* */ + AT91_REG PMC_IER; /* Interrupt Enable Register */ + AT91_REG PMC_IDR; /* Interrupt Disable Register */ + AT91_REG PMC_SR; /* Status Register */ + AT91_REG PMC_IMR; /* Interrupt Mask Register */ + AT91_REG Reserved25[ 36 ]; /* */ + AT91_REG RSTC_RCR; /* Reset Control Register */ + AT91_REG RSTC_RSR; /* Reset Status Register */ + AT91_REG RSTC_RMR; /* Reset Mode Register */ + AT91_REG Reserved26[ 5 ]; /* */ + AT91_REG RTTC_RTMR; /* Real-time Mode Register */ + AT91_REG RTTC_RTAR; /* Real-time Alarm Register */ + AT91_REG RTTC_RTVR; /* Real-time Value Register */ + AT91_REG RTTC_RTSR; /* Real-time Status Register */ + AT91_REG PITC_PIMR; /* Period Interval Mode Register */ + AT91_REG PITC_PISR; /* Period Interval Status Register */ + AT91_REG PITC_PIVR; /* Period Interval Value Register */ + AT91_REG PITC_PIIR; /* Period Interval Image Register */ + AT91_REG WDTC_WDCR; /* Watchdog Control Register */ + AT91_REG WDTC_WDMR; /* Watchdog Mode Register */ + AT91_REG WDTC_WDSR; /* Watchdog Status Register */ + AT91_REG Reserved27[ 5 ]; /* */ + AT91_REG VREG_MR; /* Voltage Regulator Mode Register */ +} AT91S_SYS, * AT91PS_SYS; + + +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR Advanced Interrupt Controller */ +/* ***************************************************************************** */ +typedef struct _AT91S_AIC +{ + AT91_REG AIC_SMR[ 32 ]; /* Source Mode Register */ + AT91_REG AIC_SVR[ 32 ]; /* Source Vector Register */ + AT91_REG AIC_IVR; /* IRQ Vector Register */ + AT91_REG AIC_FVR; /* FIQ Vector Register */ + AT91_REG AIC_ISR; /* Interrupt Status Register */ + AT91_REG AIC_IPR; /* Interrupt Pending Register */ + AT91_REG AIC_IMR; /* Interrupt Mask Register */ + AT91_REG AIC_CISR; /* Core Interrupt Status Register */ + AT91_REG Reserved0[ 2 ]; /* */ + AT91_REG AIC_IECR; /* Interrupt Enable Command Register */ + AT91_REG AIC_IDCR; /* Interrupt Disable Command Register */ + AT91_REG AIC_ICCR; /* Interrupt Clear Command Register */ + AT91_REG AIC_ISCR; /* Interrupt Set Command Register */ + AT91_REG AIC_EOICR; /* End of Interrupt Command Register */ + AT91_REG AIC_SPU; /* Spurious Vector Register */ + AT91_REG AIC_DCR; /* Debug Control Register (Protect) */ + AT91_REG Reserved1[ 1 ]; /* */ + AT91_REG AIC_FFER; /* Fast Forcing Enable Register */ + AT91_REG AIC_FFDR; /* Fast Forcing Disable Register */ + AT91_REG AIC_FFSR; /* Fast Forcing Status Register */ +} AT91S_AIC, * AT91PS_AIC; + +/* -------- AIC_SMR : (AIC Offset: 0x0) Control Register -------- */ +#define AT91C_AIC_PRIOR ( ( unsigned int ) 0x7 << 0 ) /* (AIC) Priority Level */ +#define AT91C_AIC_PRIOR_LOWEST ( ( unsigned int ) 0x0 ) /* (AIC) Lowest priority level */ +#define AT91C_AIC_PRIOR_HIGHEST ( ( unsigned int ) 0x7 ) /* (AIC) Highest priority level */ +#define AT91C_AIC_SRCTYPE ( ( unsigned int ) 0x3 << 5 ) /* (AIC) Interrupt Source Type */ +#define AT91C_AIC_SRCTYPE_INT_HIGH_LEVEL ( ( unsigned int ) 0x0 << 5 ) /* (AIC) Internal Sources Code Label High-level Sensitive */ +#define AT91C_AIC_SRCTYPE_EXT_LOW_LEVEL ( ( unsigned int ) 0x0 << 5 ) /* (AIC) External Sources Code Label Low-level Sensitive */ +#define AT91C_AIC_SRCTYPE_INT_POSITIVE_EDGE ( ( unsigned int ) 0x1 << 5 ) /* (AIC) Internal Sources Code Label Positive Edge triggered */ +#define AT91C_AIC_SRCTYPE_EXT_NEGATIVE_EDGE ( ( unsigned int ) 0x1 << 5 ) /* (AIC) External Sources Code Label Negative Edge triggered */ +#define AT91C_AIC_SRCTYPE_HIGH_LEVEL ( ( unsigned int ) 0x2 << 5 ) /* (AIC) Internal Or External Sources Code Label High-level Sensitive */ +#define AT91C_AIC_SRCTYPE_POSITIVE_EDGE ( ( unsigned int ) 0x3 << 5 ) /* (AIC) Internal Or External Sources Code Label Positive Edge triggered */ +/* -------- AIC_CISR : (AIC Offset: 0x114) AIC Core Interrupt Status Register -------- */ +#define AT91C_AIC_NFIQ ( ( unsigned int ) 0x1 << 0 ) /* (AIC) NFIQ Status */ +#define AT91C_AIC_NIRQ ( ( unsigned int ) 0x1 << 1 ) /* (AIC) NIRQ Status */ +/* -------- AIC_DCR : (AIC Offset: 0x138) AIC Debug Control Register (Protect) -------- */ +#define AT91C_AIC_DCR_PROT ( ( unsigned int ) 0x1 << 0 ) /* (AIC) Protection Mode */ +#define AT91C_AIC_DCR_GMSK ( ( unsigned int ) 0x1 << 1 ) /* (AIC) General Mask */ + +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR Peripheral DMA Controller */ +/* ***************************************************************************** */ +typedef struct _AT91S_PDC +{ + AT91_REG PDC_RPR; /* Receive Pointer Register */ + AT91_REG PDC_RCR; /* Receive Counter Register */ + AT91_REG PDC_TPR; /* Transmit Pointer Register */ + AT91_REG PDC_TCR; /* Transmit Counter Register */ + AT91_REG PDC_RNPR; /* Receive Next Pointer Register */ + AT91_REG PDC_RNCR; /* Receive Next Counter Register */ + AT91_REG PDC_TNPR; /* Transmit Next Pointer Register */ + AT91_REG PDC_TNCR; /* Transmit Next Counter Register */ + AT91_REG PDC_PTCR; /* PDC Transfer Control Register */ + AT91_REG PDC_PTSR; /* PDC Transfer Status Register */ +} AT91S_PDC, * AT91PS_PDC; + +/* -------- PDC_PTCR : (PDC Offset: 0x20) PDC Transfer Control Register -------- */ +#define AT91C_PDC_RXTEN ( ( unsigned int ) 0x1 << 0 ) /* (PDC) Receiver Transfer Enable */ +#define AT91C_PDC_RXTDIS ( ( unsigned int ) 0x1 << 1 ) /* (PDC) Receiver Transfer Disable */ +#define AT91C_PDC_TXTEN ( ( unsigned int ) 0x1 << 8 ) /* (PDC) Transmitter Transfer Enable */ +#define AT91C_PDC_TXTDIS ( ( unsigned int ) 0x1 << 9 ) /* (PDC) Transmitter Transfer Disable */ +/* -------- PDC_PTSR : (PDC Offset: 0x24) PDC Transfer Status Register -------- */ + +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR Debug Unit */ +/* ***************************************************************************** */ +typedef struct _AT91S_DBGU +{ + AT91_REG DBGU_CR; /* Control Register */ + AT91_REG DBGU_MR; /* Mode Register */ + AT91_REG DBGU_IER; /* Interrupt Enable Register */ + AT91_REG DBGU_IDR; /* Interrupt Disable Register */ + AT91_REG DBGU_IMR; /* Interrupt Mask Register */ + AT91_REG DBGU_CSR; /* Channel Status Register */ + AT91_REG DBGU_RHR; /* Receiver Holding Register */ + AT91_REG DBGU_THR; /* Transmitter Holding Register */ + AT91_REG DBGU_BRGR; /* Baud Rate Generator Register */ + AT91_REG Reserved0[ 7 ]; /* */ + AT91_REG DBGU_CIDR; /* Chip ID Register */ + AT91_REG DBGU_EXID; /* Chip ID Extension Register */ + AT91_REG DBGU_FNTR; /* Force NTRST Register */ + AT91_REG Reserved1[ 45 ]; /* */ + AT91_REG DBGU_RPR; /* Receive Pointer Register */ + AT91_REG DBGU_RCR; /* Receive Counter Register */ + AT91_REG DBGU_TPR; /* Transmit Pointer Register */ + AT91_REG DBGU_TCR; /* Transmit Counter Register */ + AT91_REG DBGU_RNPR; /* Receive Next Pointer Register */ + AT91_REG DBGU_RNCR; /* Receive Next Counter Register */ + AT91_REG DBGU_TNPR; /* Transmit Next Pointer Register */ + AT91_REG DBGU_TNCR; /* Transmit Next Counter Register */ + AT91_REG DBGU_PTCR; /* PDC Transfer Control Register */ + AT91_REG DBGU_PTSR; /* PDC Transfer Status Register */ +} AT91S_DBGU, * AT91PS_DBGU; + +/* -------- DBGU_CR : (DBGU Offset: 0x0) Debug Unit Control Register -------- */ +#define AT91C_US_RSTRX ( ( unsigned int ) 0x1 << 2 ) /* (DBGU) Reset Receiver */ +#define AT91C_US_RSTTX ( ( unsigned int ) 0x1 << 3 ) /* (DBGU) Reset Transmitter */ +#define AT91C_US_RXEN ( ( unsigned int ) 0x1 << 4 ) /* (DBGU) Receiver Enable */ +#define AT91C_US_RXDIS ( ( unsigned int ) 0x1 << 5 ) /* (DBGU) Receiver Disable */ +#define AT91C_US_TXEN ( ( unsigned int ) 0x1 << 6 ) /* (DBGU) Transmitter Enable */ +#define AT91C_US_TXDIS ( ( unsigned int ) 0x1 << 7 ) /* (DBGU) Transmitter Disable */ +#define AT91C_US_RSTSTA ( ( unsigned int ) 0x1 << 8 ) /* (DBGU) Reset Status Bits */ +/* -------- DBGU_MR : (DBGU Offset: 0x4) Debug Unit Mode Register -------- */ +#define AT91C_US_PAR ( ( unsigned int ) 0x7 << 9 ) /* (DBGU) Parity type */ +#define AT91C_US_PAR_EVEN ( ( unsigned int ) 0x0 << 9 ) /* (DBGU) Even Parity */ +#define AT91C_US_PAR_ODD ( ( unsigned int ) 0x1 << 9 ) /* (DBGU) Odd Parity */ +#define AT91C_US_PAR_SPACE ( ( unsigned int ) 0x2 << 9 ) /* (DBGU) Parity forced to 0 (Space) */ +#define AT91C_US_PAR_MARK ( ( unsigned int ) 0x3 << 9 ) /* (DBGU) Parity forced to 1 (Mark) */ +#define AT91C_US_PAR_NONE ( ( unsigned int ) 0x4 << 9 ) /* (DBGU) No Parity */ +#define AT91C_US_PAR_MULTI_DROP ( ( unsigned int ) 0x6 << 9 ) /* (DBGU) Multi-drop mode */ +#define AT91C_US_CHMODE ( ( unsigned int ) 0x3 << 14 ) /* (DBGU) Channel Mode */ +#define AT91C_US_CHMODE_NORMAL ( ( unsigned int ) 0x0 << 14 ) /* (DBGU) Normal Mode: The USART channel operates as an RX/TX USART. */ +#define AT91C_US_CHMODE_AUTO ( ( unsigned int ) 0x1 << 14 ) /* (DBGU) Automatic Echo: Receiver Data Input is connected to the TXD pin. */ +#define AT91C_US_CHMODE_LOCAL ( ( unsigned int ) 0x2 << 14 ) /* (DBGU) Local Loopback: Transmitter Output Signal is connected to Receiver Input Signal. */ +#define AT91C_US_CHMODE_REMOTE ( ( unsigned int ) 0x3 << 14 ) /* (DBGU) Remote Loopback: RXD pin is internally connected to TXD pin. */ +/* -------- DBGU_IER : (DBGU Offset: 0x8) Debug Unit Interrupt Enable Register -------- */ +#define AT91C_US_RXRDY ( ( unsigned int ) 0x1 << 0 ) /* (DBGU) RXRDY Interrupt */ +#define AT91C_US_TXRDY ( ( unsigned int ) 0x1 << 1 ) /* (DBGU) TXRDY Interrupt */ +#define AT91C_US_ENDRX ( ( unsigned int ) 0x1 << 3 ) /* (DBGU) End of Receive Transfer Interrupt */ +#define AT91C_US_ENDTX ( ( unsigned int ) 0x1 << 4 ) /* (DBGU) End of Transmit Interrupt */ +#define AT91C_US_OVRE ( ( unsigned int ) 0x1 << 5 ) /* (DBGU) Overrun Interrupt */ +#define AT91C_US_FRAME ( ( unsigned int ) 0x1 << 6 ) /* (DBGU) Framing Error Interrupt */ +#define AT91C_US_PARE ( ( unsigned int ) 0x1 << 7 ) /* (DBGU) Parity Error Interrupt */ +#define AT91C_US_TXEMPTY ( ( unsigned int ) 0x1 << 9 ) /* (DBGU) TXEMPTY Interrupt */ +#define AT91C_US_TXBUFE ( ( unsigned int ) 0x1 << 11 ) /* (DBGU) TXBUFE Interrupt */ +#define AT91C_US_RXBUFF ( ( unsigned int ) 0x1 << 12 ) /* (DBGU) RXBUFF Interrupt */ +#define AT91C_US_COMM_TX ( ( unsigned int ) 0x1 << 30 ) /* (DBGU) COMM_TX Interrupt */ +#define AT91C_US_COMM_RX ( ( unsigned int ) 0x1 << 31 ) /* (DBGU) COMM_RX Interrupt */ +/* -------- DBGU_IDR : (DBGU Offset: 0xc) Debug Unit Interrupt Disable Register -------- */ +/* -------- DBGU_IMR : (DBGU Offset: 0x10) Debug Unit Interrupt Mask Register -------- */ +/* -------- DBGU_CSR : (DBGU Offset: 0x14) Debug Unit Channel Status Register -------- */ +/* -------- DBGU_FNTR : (DBGU Offset: 0x48) Debug Unit FORCE_NTRST Register -------- */ +#define AT91C_US_FORCE_NTRST ( ( unsigned int ) 0x1 << 0 ) /* (DBGU) Force NTRST in JTAG */ + +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR Parallel Input Output Controller */ +/* ***************************************************************************** */ +typedef struct _AT91S_PIO +{ + AT91_REG PIO_PER; /* PIO Enable Register */ + AT91_REG PIO_PDR; /* PIO Disable Register */ + AT91_REG PIO_PSR; /* PIO Status Register */ + AT91_REG Reserved0[ 1 ]; /* */ + AT91_REG PIO_OER; /* Output Enable Register */ + AT91_REG PIO_ODR; /* Output Disable Registerr */ + AT91_REG PIO_OSR; /* Output Status Register */ + AT91_REG Reserved1[ 1 ]; /* */ + AT91_REG PIO_IFER; /* Input Filter Enable Register */ + AT91_REG PIO_IFDR; /* Input Filter Disable Register */ + AT91_REG PIO_IFSR; /* Input Filter Status Register */ + AT91_REG Reserved2[ 1 ]; /* */ + AT91_REG PIO_SODR; /* Set Output Data Register */ + AT91_REG PIO_CODR; /* Clear Output Data Register */ + AT91_REG PIO_ODSR; /* Output Data Status Register */ + AT91_REG PIO_PDSR; /* Pin Data Status Register */ + AT91_REG PIO_IER; /* Interrupt Enable Register */ + AT91_REG PIO_IDR; /* Interrupt Disable Register */ + AT91_REG PIO_IMR; /* Interrupt Mask Register */ + AT91_REG PIO_ISR; /* Interrupt Status Register */ + AT91_REG PIO_MDER; /* Multi-driver Enable Register */ + AT91_REG PIO_MDDR; /* Multi-driver Disable Register */ + AT91_REG PIO_MDSR; /* Multi-driver Status Register */ + AT91_REG Reserved3[ 1 ]; /* */ + AT91_REG PIO_PPUDR; /* Pull-up Disable Register */ + AT91_REG PIO_PPUER; /* Pull-up Enable Register */ + AT91_REG PIO_PPUSR; /* Pull-up Status Register */ + AT91_REG Reserved4[ 1 ]; /* */ + AT91_REG PIO_ASR; /* Select A Register */ + AT91_REG PIO_BSR; /* Select B Register */ + AT91_REG PIO_ABSR; /* AB Select Status Register */ + AT91_REG Reserved5[ 9 ]; /* */ + AT91_REG PIO_OWER; /* Output Write Enable Register */ + AT91_REG PIO_OWDR; /* Output Write Disable Register */ + AT91_REG PIO_OWSR; /* Output Write Status Register */ +} AT91S_PIO, * AT91PS_PIO; + + +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR Clock Generator Controller */ +/* ***************************************************************************** */ +typedef struct _AT91S_CKGR +{ + AT91_REG CKGR_MOR; /* Main Oscillator Register */ + AT91_REG CKGR_MCFR; /* Main Clock Frequency Register */ + AT91_REG Reserved0[ 1 ]; /* */ + AT91_REG CKGR_PLLR; /* PLL Register */ +} AT91S_CKGR, * AT91PS_CKGR; + +/* -------- CKGR_MOR : (CKGR Offset: 0x0) Main Oscillator Register -------- */ +#define AT91C_CKGR_MOSCEN ( ( unsigned int ) 0x1 << 0 ) /* (CKGR) Main Oscillator Enable */ +#define AT91C_CKGR_OSCBYPASS ( ( unsigned int ) 0x1 << 1 ) /* (CKGR) Main Oscillator Bypass */ +#define AT91C_CKGR_OSCOUNT ( ( unsigned int ) 0xFF << 8 ) /* (CKGR) Main Oscillator Start-up Time */ +/* -------- CKGR_MCFR : (CKGR Offset: 0x4) Main Clock Frequency Register -------- */ +#define AT91C_CKGR_MAINF ( ( unsigned int ) 0xFFFF << 0 ) /* (CKGR) Main Clock Frequency */ +#define AT91C_CKGR_MAINRDY ( ( unsigned int ) 0x1 << 16 ) /* (CKGR) Main Clock Ready */ +/* -------- CKGR_PLLR : (CKGR Offset: 0xc) PLL B Register -------- */ +#define AT91C_CKGR_DIV ( ( unsigned int ) 0xFF << 0 ) /* (CKGR) Divider Selected */ +#define AT91C_CKGR_DIV_0 ( ( unsigned int ) 0x0 ) /* (CKGR) Divider output is 0 */ +#define AT91C_CKGR_DIV_BYPASS ( ( unsigned int ) 0x1 ) /* (CKGR) Divider is bypassed */ +#define AT91C_CKGR_PLLCOUNT ( ( unsigned int ) 0x3F << 8 ) /* (CKGR) PLL Counter */ +#define AT91C_CKGR_OUT ( ( unsigned int ) 0x3 << 14 ) /* (CKGR) PLL Output Frequency Range */ +#define AT91C_CKGR_OUT_0 ( ( unsigned int ) 0x0 << 14 ) /* (CKGR) Please refer to the PLL datasheet */ +#define AT91C_CKGR_OUT_1 ( ( unsigned int ) 0x1 << 14 ) /* (CKGR) Please refer to the PLL datasheet */ +#define AT91C_CKGR_OUT_2 ( ( unsigned int ) 0x2 << 14 ) /* (CKGR) Please refer to the PLL datasheet */ +#define AT91C_CKGR_OUT_3 ( ( unsigned int ) 0x3 << 14 ) /* (CKGR) Please refer to the PLL datasheet */ +#define AT91C_CKGR_MUL ( ( unsigned int ) 0x7FF << 16 ) /* (CKGR) PLL Multiplier */ +#define AT91C_CKGR_USBDIV ( ( unsigned int ) 0x3 << 28 ) /* (CKGR) Divider for USB Clocks */ +#define AT91C_CKGR_USBDIV_0 ( ( unsigned int ) 0x0 << 28 ) /* (CKGR) Divider output is PLL clock output */ +#define AT91C_CKGR_USBDIV_1 ( ( unsigned int ) 0x1 << 28 ) /* (CKGR) Divider output is PLL clock output divided by 2 */ +#define AT91C_CKGR_USBDIV_2 ( ( unsigned int ) 0x2 << 28 ) /* (CKGR) Divider output is PLL clock output divided by 4 */ + +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR Power Management Controller */ +/* ***************************************************************************** */ +typedef struct _AT91S_PMC +{ + AT91_REG PMC_SCER; /* System Clock Enable Register */ + AT91_REG PMC_SCDR; /* System Clock Disable Register */ + AT91_REG PMC_SCSR; /* System Clock Status Register */ + AT91_REG Reserved0[ 1 ]; /* */ + AT91_REG PMC_PCER; /* Peripheral Clock Enable Register */ + AT91_REG PMC_PCDR; /* Peripheral Clock Disable Register */ + AT91_REG PMC_PCSR; /* Peripheral Clock Status Register */ + AT91_REG Reserved1[ 1 ]; /* */ + AT91_REG PMC_MOR; /* Main Oscillator Register */ + AT91_REG PMC_MCFR; /* Main Clock Frequency Register */ + AT91_REG Reserved2[ 1 ]; /* */ + AT91_REG PMC_PLLR; /* PLL Register */ + AT91_REG PMC_MCKR; /* Master Clock Register */ + AT91_REG Reserved3[ 3 ]; /* */ + AT91_REG PMC_PCKR[ 4 ]; /* Programmable Clock Register */ + AT91_REG Reserved4[ 4 ]; /* */ + AT91_REG PMC_IER; /* Interrupt Enable Register */ + AT91_REG PMC_IDR; /* Interrupt Disable Register */ + AT91_REG PMC_SR; /* Status Register */ + AT91_REG PMC_IMR; /* Interrupt Mask Register */ +} AT91S_PMC, * AT91PS_PMC; + +/* -------- PMC_SCER : (PMC Offset: 0x0) System Clock Enable Register -------- */ +#define AT91C_PMC_PCK ( ( unsigned int ) 0x1 << 0 ) /* (PMC) Processor Clock */ +#define AT91C_PMC_UDP ( ( unsigned int ) 0x1 << 7 ) /* (PMC) USB Device Port Clock */ +#define AT91C_PMC_PCK0 ( ( unsigned int ) 0x1 << 8 ) /* (PMC) Programmable Clock Output */ +#define AT91C_PMC_PCK1 ( ( unsigned int ) 0x1 << 9 ) /* (PMC) Programmable Clock Output */ +#define AT91C_PMC_PCK2 ( ( unsigned int ) 0x1 << 10 ) /* (PMC) Programmable Clock Output */ +#define AT91C_PMC_PCK3 ( ( unsigned int ) 0x1 << 11 ) /* (PMC) Programmable Clock Output */ +/* -------- PMC_SCDR : (PMC Offset: 0x4) System Clock Disable Register -------- */ +/* -------- PMC_SCSR : (PMC Offset: 0x8) System Clock Status Register -------- */ +/* -------- CKGR_MOR : (PMC Offset: 0x20) Main Oscillator Register -------- */ +/* -------- CKGR_MCFR : (PMC Offset: 0x24) Main Clock Frequency Register -------- */ +/* -------- CKGR_PLLR : (PMC Offset: 0x2c) PLL B Register -------- */ +/* -------- PMC_MCKR : (PMC Offset: 0x30) Master Clock Register -------- */ +#define AT91C_PMC_CSS ( ( unsigned int ) 0x3 << 0 ) /* (PMC) Programmable Clock Selection */ +#define AT91C_PMC_CSS_SLOW_CLK ( ( unsigned int ) 0x0 ) /* (PMC) Slow Clock is selected */ +#define AT91C_PMC_CSS_MAIN_CLK ( ( unsigned int ) 0x1 ) /* (PMC) Main Clock is selected */ +#define AT91C_PMC_CSS_PLL_CLK ( ( unsigned int ) 0x3 ) /* (PMC) Clock from PLL is selected */ +#define AT91C_PMC_PRES ( ( unsigned int ) 0x7 << 2 ) /* (PMC) Programmable Clock Prescaler */ +#define AT91C_PMC_PRES_CLK ( ( unsigned int ) 0x0 << 2 ) /* (PMC) Selected clock */ +#define AT91C_PMC_PRES_CLK_2 ( ( unsigned int ) 0x1 << 2 ) /* (PMC) Selected clock divided by 2 */ +#define AT91C_PMC_PRES_CLK_4 ( ( unsigned int ) 0x2 << 2 ) /* (PMC) Selected clock divided by 4 */ +#define AT91C_PMC_PRES_CLK_8 ( ( unsigned int ) 0x3 << 2 ) /* (PMC) Selected clock divided by 8 */ +#define AT91C_PMC_PRES_CLK_16 ( ( unsigned int ) 0x4 << 2 ) /* (PMC) Selected clock divided by 16 */ +#define AT91C_PMC_PRES_CLK_32 ( ( unsigned int ) 0x5 << 2 ) /* (PMC) Selected clock divided by 32 */ +#define AT91C_PMC_PRES_CLK_64 ( ( unsigned int ) 0x6 << 2 ) /* (PMC) Selected clock divided by 64 */ +/* -------- PMC_PCKR : (PMC Offset: 0x40) Programmable Clock Register -------- */ +/* -------- PMC_IER : (PMC Offset: 0x60) PMC Interrupt Enable Register -------- */ +#define AT91C_PMC_MOSCS ( ( unsigned int ) 0x1 << 0 ) /* (PMC) MOSC Status/Enable/Disable/Mask */ +#define AT91C_PMC_LOCK ( ( unsigned int ) 0x1 << 2 ) /* (PMC) PLL Status/Enable/Disable/Mask */ +#define AT91C_PMC_MCKRDY ( ( unsigned int ) 0x1 << 3 ) /* (PMC) MCK_RDY Status/Enable/Disable/Mask */ +#define AT91C_PMC_PCK0RDY ( ( unsigned int ) 0x1 << 8 ) /* (PMC) PCK0_RDY Status/Enable/Disable/Mask */ +#define AT91C_PMC_PCK1RDY ( ( unsigned int ) 0x1 << 9 ) /* (PMC) PCK1_RDY Status/Enable/Disable/Mask */ +#define AT91C_PMC_PCK2RDY ( ( unsigned int ) 0x1 << 10 ) /* (PMC) PCK2_RDY Status/Enable/Disable/Mask */ +#define AT91C_PMC_PCK3RDY ( ( unsigned int ) 0x1 << 11 ) /* (PMC) PCK3_RDY Status/Enable/Disable/Mask */ +/* -------- PMC_IDR : (PMC Offset: 0x64) PMC Interrupt Disable Register -------- */ +/* -------- PMC_SR : (PMC Offset: 0x68) PMC Status Register -------- */ +/* -------- PMC_IMR : (PMC Offset: 0x6c) PMC Interrupt Mask Register -------- */ + +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR Reset Controller Interface */ +/* ***************************************************************************** */ +typedef struct _AT91S_RSTC +{ + AT91_REG RSTC_RCR; /* Reset Control Register */ + AT91_REG RSTC_RSR; /* Reset Status Register */ + AT91_REG RSTC_RMR; /* Reset Mode Register */ +} AT91S_RSTC, * AT91PS_RSTC; + +/* -------- RSTC_RCR : (RSTC Offset: 0x0) Reset Control Register -------- */ +#define AT91C_RSTC_PROCRST ( ( unsigned int ) 0x1 << 0 ) /* (RSTC) Processor Reset */ +#define AT91C_RSTC_PERRST ( ( unsigned int ) 0x1 << 2 ) /* (RSTC) Peripheral Reset */ +#define AT91C_RSTC_EXTRST ( ( unsigned int ) 0x1 << 3 ) /* (RSTC) External Reset */ +#define AT91C_RSTC_KEY ( ( unsigned int ) 0xFF << 24 ) /* (RSTC) Password */ +/* -------- RSTC_RSR : (RSTC Offset: 0x4) Reset Status Register -------- */ +#define AT91C_RSTC_URSTS ( ( unsigned int ) 0x1 << 0 ) /* (RSTC) User Reset Status */ +#define AT91C_RSTC_BODSTS ( ( unsigned int ) 0x1 << 1 ) /* (RSTC) Brownout Detection Status */ +#define AT91C_RSTC_RSTTYP ( ( unsigned int ) 0x7 << 8 ) /* (RSTC) Reset Type */ +#define AT91C_RSTC_RSTTYP_POWERUP ( ( unsigned int ) 0x0 << 8 ) /* (RSTC) Power-up Reset. VDDCORE rising. */ +#define AT91C_RSTC_RSTTYP_WAKEUP ( ( unsigned int ) 0x1 << 8 ) /* (RSTC) WakeUp Reset. VDDCORE rising. */ +#define AT91C_RSTC_RSTTYP_WATCHDOG ( ( unsigned int ) 0x2 << 8 ) /* (RSTC) Watchdog Reset. Watchdog overflow occurred. */ +#define AT91C_RSTC_RSTTYP_SOFTWARE ( ( unsigned int ) 0x3 << 8 ) /* (RSTC) Software Reset. Processor reset required by the software. */ +#define AT91C_RSTC_RSTTYP_USER ( ( unsigned int ) 0x4 << 8 ) /* (RSTC) User Reset. NRST pin detected low. */ +#define AT91C_RSTC_RSTTYP_BROWNOUT ( ( unsigned int ) 0x5 << 8 ) /* (RSTC) Brownout Reset occurred. */ +#define AT91C_RSTC_NRSTL ( ( unsigned int ) 0x1 << 16 ) /* (RSTC) NRST pin level */ +#define AT91C_RSTC_SRCMP ( ( unsigned int ) 0x1 << 17 ) /* (RSTC) Software Reset Command in Progress. */ +/* -------- RSTC_RMR : (RSTC Offset: 0x8) Reset Mode Register -------- */ +#define AT91C_RSTC_URSTEN ( ( unsigned int ) 0x1 << 0 ) /* (RSTC) User Reset Enable */ +#define AT91C_RSTC_URSTIEN ( ( unsigned int ) 0x1 << 4 ) /* (RSTC) User Reset Interrupt Enable */ +#define AT91C_RSTC_ERSTL ( ( unsigned int ) 0xF << 8 ) /* (RSTC) User Reset Enable */ +#define AT91C_RSTC_BODIEN ( ( unsigned int ) 0x1 << 16 ) /* (RSTC) Brownout Detection Interrupt Enable */ + +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR Real Time Timer Controller Interface */ +/* ***************************************************************************** */ +typedef struct _AT91S_RTTC +{ + AT91_REG RTTC_RTMR; /* Real-time Mode Register */ + AT91_REG RTTC_RTAR; /* Real-time Alarm Register */ + AT91_REG RTTC_RTVR; /* Real-time Value Register */ + AT91_REG RTTC_RTSR; /* Real-time Status Register */ +} AT91S_RTTC, * AT91PS_RTTC; + +/* -------- RTTC_RTMR : (RTTC Offset: 0x0) Real-time Mode Register -------- */ +#define AT91C_RTTC_RTPRES ( ( unsigned int ) 0xFFFF << 0 ) /* (RTTC) Real-time Timer Prescaler Value */ +#define AT91C_RTTC_ALMIEN ( ( unsigned int ) 0x1 << 16 ) /* (RTTC) Alarm Interrupt Enable */ +#define AT91C_RTTC_RTTINCIEN ( ( unsigned int ) 0x1 << 17 ) /* (RTTC) Real Time Timer Increment Interrupt Enable */ +#define AT91C_RTTC_RTTRST ( ( unsigned int ) 0x1 << 18 ) /* (RTTC) Real Time Timer Restart */ +/* -------- RTTC_RTAR : (RTTC Offset: 0x4) Real-time Alarm Register -------- */ +#define AT91C_RTTC_ALMV ( ( unsigned int ) 0x0 << 0 ) /* (RTTC) Alarm Value */ +/* -------- RTTC_RTVR : (RTTC Offset: 0x8) Current Real-time Value Register -------- */ +#define AT91C_RTTC_CRTV ( ( unsigned int ) 0x0 << 0 ) /* (RTTC) Current Real-time Value */ +/* -------- RTTC_RTSR : (RTTC Offset: 0xc) Real-time Status Register -------- */ +#define AT91C_RTTC_ALMS ( ( unsigned int ) 0x1 << 0 ) /* (RTTC) Real-time Alarm Status */ +#define AT91C_RTTC_RTTINC ( ( unsigned int ) 0x1 << 1 ) /* (RTTC) Real-time Timer Increment */ + +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR Periodic Interval Timer Controller Interface */ +/* ***************************************************************************** */ +typedef struct _AT91S_PITC +{ + AT91_REG PITC_PIMR; /* Period Interval Mode Register */ + AT91_REG PITC_PISR; /* Period Interval Status Register */ + AT91_REG PITC_PIVR; /* Period Interval Value Register */ + AT91_REG PITC_PIIR; /* Period Interval Image Register */ +} AT91S_PITC, * AT91PS_PITC; + +/* -------- PITC_PIMR : (PITC Offset: 0x0) Periodic Interval Mode Register -------- */ +#define AT91C_PITC_PIV ( ( unsigned int ) 0xFFFFF << 0 ) /* (PITC) Periodic Interval Value */ +#define AT91C_PITC_PITEN ( ( unsigned int ) 0x1 << 24 ) /* (PITC) Periodic Interval Timer Enabled */ +#define AT91C_PITC_PITIEN ( ( unsigned int ) 0x1 << 25 ) /* (PITC) Periodic Interval Timer Interrupt Enable */ +/* -------- PITC_PISR : (PITC Offset: 0x4) Periodic Interval Status Register -------- */ +#define AT91C_PITC_PITS ( ( unsigned int ) 0x1 << 0 ) /* (PITC) Periodic Interval Timer Status */ +/* -------- PITC_PIVR : (PITC Offset: 0x8) Periodic Interval Value Register -------- */ +#define AT91C_PITC_CPIV ( ( unsigned int ) 0xFFFFF << 0 ) /* (PITC) Current Periodic Interval Value */ +#define AT91C_PITC_PICNT ( ( unsigned int ) 0xFFF << 20 ) /* (PITC) Periodic Interval Counter */ +/* -------- PITC_PIIR : (PITC Offset: 0xc) Periodic Interval Image Register -------- */ + +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR Watchdog Timer Controller Interface */ +/* ***************************************************************************** */ +typedef struct _AT91S_WDTC +{ + AT91_REG WDTC_WDCR; /* Watchdog Control Register */ + AT91_REG WDTC_WDMR; /* Watchdog Mode Register */ + AT91_REG WDTC_WDSR; /* Watchdog Status Register */ +} AT91S_WDTC, * AT91PS_WDTC; + +/* -------- WDTC_WDCR : (WDTC Offset: 0x0) Periodic Interval Image Register -------- */ +#define AT91C_WDTC_WDRSTT ( ( unsigned int ) 0x1 << 0 ) /* (WDTC) Watchdog Restart */ +#define AT91C_WDTC_KEY ( ( unsigned int ) 0xFF << 24 ) /* (WDTC) Watchdog KEY Password */ +/* -------- WDTC_WDMR : (WDTC Offset: 0x4) Watchdog Mode Register -------- */ +#define AT91C_WDTC_WDV ( ( unsigned int ) 0xFFF << 0 ) /* (WDTC) Watchdog Timer Restart */ +#define AT91C_WDTC_WDFIEN ( ( unsigned int ) 0x1 << 12 ) /* (WDTC) Watchdog Fault Interrupt Enable */ +#define AT91C_WDTC_WDRSTEN ( ( unsigned int ) 0x1 << 13 ) /* (WDTC) Watchdog Reset Enable */ +#define AT91C_WDTC_WDRPROC ( ( unsigned int ) 0x1 << 14 ) /* (WDTC) Watchdog Timer Restart */ +#define AT91C_WDTC_WDDIS ( ( unsigned int ) 0x1 << 15 ) /* (WDTC) Watchdog Disable */ +#define AT91C_WDTC_WDD ( ( unsigned int ) 0xFFF << 16 ) /* (WDTC) Watchdog Delta Value */ +#define AT91C_WDTC_WDDBGHLT ( ( unsigned int ) 0x1 << 28 ) /* (WDTC) Watchdog Debug Halt */ +#define AT91C_WDTC_WDIDLEHLT ( ( unsigned int ) 0x1 << 29 ) /* (WDTC) Watchdog Idle Halt */ +/* -------- WDTC_WDSR : (WDTC Offset: 0x8) Watchdog Status Register -------- */ +#define AT91C_WDTC_WDUNF ( ( unsigned int ) 0x1 << 0 ) /* (WDTC) Watchdog Underflow */ +#define AT91C_WDTC_WDERR ( ( unsigned int ) 0x1 << 1 ) /* (WDTC) Watchdog Error */ + +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR Voltage Regulator Mode Controller Interface */ +/* ***************************************************************************** */ +typedef struct _AT91S_VREG +{ + AT91_REG VREG_MR; /* Voltage Regulator Mode Register */ +} AT91S_VREG, * AT91PS_VREG; + +/* -------- VREG_MR : (VREG Offset: 0x0) Voltage Regulator Mode Register -------- */ +#define AT91C_VREG_PSTDBY ( ( unsigned int ) 0x1 << 0 ) /* (VREG) Voltage Regulator Power Standby Mode */ + +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR Memory Controller Interface */ +/* ***************************************************************************** */ +typedef struct _AT91S_MC +{ + AT91_REG MC_RCR; /* MC Remap Control Register */ + AT91_REG MC_ASR; /* MC Abort Status Register */ + AT91_REG MC_AASR; /* MC Abort Address Status Register */ + AT91_REG Reserved0[ 21 ]; /* */ + AT91_REG MC_FMR; /* MC Flash Mode Register */ + AT91_REG MC_FCR; /* MC Flash Command Register */ + AT91_REG MC_FSR; /* MC Flash Status Register */ +} AT91S_MC, * AT91PS_MC; + +/* -------- MC_RCR : (MC Offset: 0x0) MC Remap Control Register -------- */ +#define AT91C_MC_RCB ( ( unsigned int ) 0x1 << 0 ) /* (MC) Remap Command Bit */ +/* -------- MC_ASR : (MC Offset: 0x4) MC Abort Status Register -------- */ +#define AT91C_MC_UNDADD ( ( unsigned int ) 0x1 << 0 ) /* (MC) Undefined Addess Abort Status */ +#define AT91C_MC_MISADD ( ( unsigned int ) 0x1 << 1 ) /* (MC) Misaligned Addess Abort Status */ +#define AT91C_MC_ABTSZ ( ( unsigned int ) 0x3 << 8 ) /* (MC) Abort Size Status */ +#define AT91C_MC_ABTSZ_BYTE ( ( unsigned int ) 0x0 << 8 ) /* (MC) Byte */ +#define AT91C_MC_ABTSZ_HWORD ( ( unsigned int ) 0x1 << 8 ) /* (MC) Half-word */ +#define AT91C_MC_ABTSZ_WORD ( ( unsigned int ) 0x2 << 8 ) /* (MC) Word */ +#define AT91C_MC_ABTTYP ( ( unsigned int ) 0x3 << 10 ) /* (MC) Abort Type Status */ +#define AT91C_MC_ABTTYP_DATAR ( ( unsigned int ) 0x0 << 10 ) /* (MC) Data Read */ +#define AT91C_MC_ABTTYP_DATAW ( ( unsigned int ) 0x1 << 10 ) /* (MC) Data Write */ +#define AT91C_MC_ABTTYP_FETCH ( ( unsigned int ) 0x2 << 10 ) /* (MC) Code Fetch */ +#define AT91C_MC_MST0 ( ( unsigned int ) 0x1 << 16 ) /* (MC) Master 0 Abort Source */ +#define AT91C_MC_MST1 ( ( unsigned int ) 0x1 << 17 ) /* (MC) Master 1 Abort Source */ +#define AT91C_MC_SVMST0 ( ( unsigned int ) 0x1 << 24 ) /* (MC) Saved Master 0 Abort Source */ +#define AT91C_MC_SVMST1 ( ( unsigned int ) 0x1 << 25 ) /* (MC) Saved Master 1 Abort Source */ +/* -------- MC_FMR : (MC Offset: 0x60) MC Flash Mode Register -------- */ +#define AT91C_MC_FRDY ( ( unsigned int ) 0x1 << 0 ) /* (MC) Flash Ready */ +#define AT91C_MC_LOCKE ( ( unsigned int ) 0x1 << 2 ) /* (MC) Lock Error */ +#define AT91C_MC_PROGE ( ( unsigned int ) 0x1 << 3 ) /* (MC) Programming Error */ +#define AT91C_MC_NEBP ( ( unsigned int ) 0x1 << 7 ) /* (MC) No Erase Before Programming */ +#define AT91C_MC_FWS ( ( unsigned int ) 0x3 << 8 ) /* (MC) Flash Wait State */ +#define AT91C_MC_FWS_0FWS ( ( unsigned int ) 0x0 << 8 ) /* (MC) 1 cycle for Read, 2 for Write operations */ +#define AT91C_MC_FWS_1FWS ( ( unsigned int ) 0x1 << 8 ) /* (MC) 2 cycles for Read, 3 for Write operations */ +#define AT91C_MC_FWS_2FWS ( ( unsigned int ) 0x2 << 8 ) /* (MC) 3 cycles for Read, 4 for Write operations */ +#define AT91C_MC_FWS_3FWS ( ( unsigned int ) 0x3 << 8 ) /* (MC) 4 cycles for Read, 4 for Write operations */ +#define AT91C_MC_FMCN ( ( unsigned int ) 0xFF << 16 ) /* (MC) Flash Microsecond Cycle Number */ +/* -------- MC_FCR : (MC Offset: 0x64) MC Flash Command Register -------- */ +#define AT91C_MC_FCMD ( ( unsigned int ) 0xF << 0 ) /* (MC) Flash Command */ +#define AT91C_MC_FCMD_START_PROG ( ( unsigned int ) 0x1 ) /* (MC) Starts the programming of th epage specified by PAGEN. */ +#define AT91C_MC_FCMD_LOCK ( ( unsigned int ) 0x2 ) /* (MC) Starts a lock sequence of the sector defined by the bits 4 to 7 of the field PAGEN. */ +#define AT91C_MC_FCMD_PROG_AND_LOCK ( ( unsigned int ) 0x3 ) /* (MC) The lock sequence automatically happens after the programming sequence is completed. */ +#define AT91C_MC_FCMD_UNLOCK ( ( unsigned int ) 0x4 ) /* (MC) Starts an unlock sequence of the sector defined by the bits 4 to 7 of the field PAGEN. */ +#define AT91C_MC_FCMD_ERASE_ALL ( ( unsigned int ) 0x8 ) /* (MC) Starts the erase of the entire flash.If at least a page is locked, the command is cancelled. */ +#define AT91C_MC_FCMD_SET_GP_NVM ( ( unsigned int ) 0xB ) /* (MC) Set General Purpose NVM bits. */ +#define AT91C_MC_FCMD_CLR_GP_NVM ( ( unsigned int ) 0xD ) /* (MC) Clear General Purpose NVM bits. */ +#define AT91C_MC_FCMD_SET_SECURITY ( ( unsigned int ) 0xF ) /* (MC) Set Security Bit. */ +#define AT91C_MC_PAGEN ( ( unsigned int ) 0x3FF << 8 ) /* (MC) Page Number */ +#define AT91C_MC_KEY ( ( unsigned int ) 0xFF << 24 ) /* (MC) Writing Protect Key */ +/* -------- MC_FSR : (MC Offset: 0x68) MC Flash Command Register -------- */ +#define AT91C_MC_SECURITY ( ( unsigned int ) 0x1 << 4 ) /* (MC) Security Bit Status */ +#define AT91C_MC_GPNVM0 ( ( unsigned int ) 0x1 << 8 ) /* (MC) Sector 0 Lock Status */ +#define AT91C_MC_GPNVM1 ( ( unsigned int ) 0x1 << 9 ) /* (MC) Sector 1 Lock Status */ +#define AT91C_MC_GPNVM2 ( ( unsigned int ) 0x1 << 10 ) /* (MC) Sector 2 Lock Status */ +#define AT91C_MC_GPNVM3 ( ( unsigned int ) 0x1 << 11 ) /* (MC) Sector 3 Lock Status */ +#define AT91C_MC_GPNVM4 ( ( unsigned int ) 0x1 << 12 ) /* (MC) Sector 4 Lock Status */ +#define AT91C_MC_GPNVM5 ( ( unsigned int ) 0x1 << 13 ) /* (MC) Sector 5 Lock Status */ +#define AT91C_MC_GPNVM6 ( ( unsigned int ) 0x1 << 14 ) /* (MC) Sector 6 Lock Status */ +#define AT91C_MC_GPNVM7 ( ( unsigned int ) 0x1 << 15 ) /* (MC) Sector 7 Lock Status */ +#define AT91C_MC_LOCKS0 ( ( unsigned int ) 0x1 << 16 ) /* (MC) Sector 0 Lock Status */ +#define AT91C_MC_LOCKS1 ( ( unsigned int ) 0x1 << 17 ) /* (MC) Sector 1 Lock Status */ +#define AT91C_MC_LOCKS2 ( ( unsigned int ) 0x1 << 18 ) /* (MC) Sector 2 Lock Status */ +#define AT91C_MC_LOCKS3 ( ( unsigned int ) 0x1 << 19 ) /* (MC) Sector 3 Lock Status */ +#define AT91C_MC_LOCKS4 ( ( unsigned int ) 0x1 << 20 ) /* (MC) Sector 4 Lock Status */ +#define AT91C_MC_LOCKS5 ( ( unsigned int ) 0x1 << 21 ) /* (MC) Sector 5 Lock Status */ +#define AT91C_MC_LOCKS6 ( ( unsigned int ) 0x1 << 22 ) /* (MC) Sector 6 Lock Status */ +#define AT91C_MC_LOCKS7 ( ( unsigned int ) 0x1 << 23 ) /* (MC) Sector 7 Lock Status */ +#define AT91C_MC_LOCKS8 ( ( unsigned int ) 0x1 << 24 ) /* (MC) Sector 8 Lock Status */ +#define AT91C_MC_LOCKS9 ( ( unsigned int ) 0x1 << 25 ) /* (MC) Sector 9 Lock Status */ +#define AT91C_MC_LOCKS10 ( ( unsigned int ) 0x1 << 26 ) /* (MC) Sector 10 Lock Status */ +#define AT91C_MC_LOCKS11 ( ( unsigned int ) 0x1 << 27 ) /* (MC) Sector 11 Lock Status */ +#define AT91C_MC_LOCKS12 ( ( unsigned int ) 0x1 << 28 ) /* (MC) Sector 12 Lock Status */ +#define AT91C_MC_LOCKS13 ( ( unsigned int ) 0x1 << 29 ) /* (MC) Sector 13 Lock Status */ +#define AT91C_MC_LOCKS14 ( ( unsigned int ) 0x1 << 30 ) /* (MC) Sector 14 Lock Status */ +#define AT91C_MC_LOCKS15 ( ( unsigned int ) 0x1 << 31 ) /* (MC) Sector 15 Lock Status */ + +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR Serial Parallel Interface */ +/* ***************************************************************************** */ +typedef struct _AT91S_SPI +{ + AT91_REG SPI_CR; /* Control Register */ + AT91_REG SPI_MR; /* Mode Register */ + AT91_REG SPI_RDR; /* Receive Data Register */ + AT91_REG SPI_TDR; /* Transmit Data Register */ + AT91_REG SPI_SR; /* Status Register */ + AT91_REG SPI_IER; /* Interrupt Enable Register */ + AT91_REG SPI_IDR; /* Interrupt Disable Register */ + AT91_REG SPI_IMR; /* Interrupt Mask Register */ + AT91_REG Reserved0[ 4 ]; /* */ + AT91_REG SPI_CSR[ 4 ]; /* Chip Select Register */ + AT91_REG Reserved1[ 48 ]; /* */ + AT91_REG SPI_RPR; /* Receive Pointer Register */ + AT91_REG SPI_RCR; /* Receive Counter Register */ + AT91_REG SPI_TPR; /* Transmit Pointer Register */ + AT91_REG SPI_TCR; /* Transmit Counter Register */ + AT91_REG SPI_RNPR; /* Receive Next Pointer Register */ + AT91_REG SPI_RNCR; /* Receive Next Counter Register */ + AT91_REG SPI_TNPR; /* Transmit Next Pointer Register */ + AT91_REG SPI_TNCR; /* Transmit Next Counter Register */ + AT91_REG SPI_PTCR; /* PDC Transfer Control Register */ + AT91_REG SPI_PTSR; /* PDC Transfer Status Register */ +} AT91S_SPI, * AT91PS_SPI; + +/* -------- SPI_CR : (SPI Offset: 0x0) SPI Control Register -------- */ +#define AT91C_SPI_SPIEN ( ( unsigned int ) 0x1 << 0 ) /* (SPI) SPI Enable */ +#define AT91C_SPI_SPIDIS ( ( unsigned int ) 0x1 << 1 ) /* (SPI) SPI Disable */ +#define AT91C_SPI_SWRST ( ( unsigned int ) 0x1 << 7 ) /* (SPI) SPI Software reset */ +#define AT91C_SPI_LASTXFER ( ( unsigned int ) 0x1 << 24 ) /* (SPI) SPI Last Transfer */ +/* -------- SPI_MR : (SPI Offset: 0x4) SPI Mode Register -------- */ +#define AT91C_SPI_MSTR ( ( unsigned int ) 0x1 << 0 ) /* (SPI) Master/Slave Mode */ +#define AT91C_SPI_PS ( ( unsigned int ) 0x1 << 1 ) /* (SPI) Peripheral Select */ +#define AT91C_SPI_PS_FIXED ( ( unsigned int ) 0x0 << 1 ) /* (SPI) Fixed Peripheral Select */ +#define AT91C_SPI_PS_VARIABLE ( ( unsigned int ) 0x1 << 1 ) /* (SPI) Variable Peripheral Select */ +#define AT91C_SPI_PCSDEC ( ( unsigned int ) 0x1 << 2 ) /* (SPI) Chip Select Decode */ +#define AT91C_SPI_FDIV ( ( unsigned int ) 0x1 << 3 ) /* (SPI) Clock Selection */ +#define AT91C_SPI_MODFDIS ( ( unsigned int ) 0x1 << 4 ) /* (SPI) Mode Fault Detection */ +#define AT91C_SPI_LLB ( ( unsigned int ) 0x1 << 7 ) /* (SPI) Clock Selection */ +#define AT91C_SPI_PCS ( ( unsigned int ) 0xF << 16 ) /* (SPI) Peripheral Chip Select */ +#define AT91C_SPI_DLYBCS ( ( unsigned int ) 0xFF << 24 ) /* (SPI) Delay Between Chip Selects */ +/* -------- SPI_RDR : (SPI Offset: 0x8) Receive Data Register -------- */ +#define AT91C_SPI_RD ( ( unsigned int ) 0xFFFF << 0 ) /* (SPI) Receive Data */ +#define AT91C_SPI_RPCS ( ( unsigned int ) 0xF << 16 ) /* (SPI) Peripheral Chip Select Status */ +/* -------- SPI_TDR : (SPI Offset: 0xc) Transmit Data Register -------- */ +#define AT91C_SPI_TD ( ( unsigned int ) 0xFFFF << 0 ) /* (SPI) Transmit Data */ +#define AT91C_SPI_TPCS ( ( unsigned int ) 0xF << 16 ) /* (SPI) Peripheral Chip Select Status */ +/* -------- SPI_SR : (SPI Offset: 0x10) Status Register -------- */ +#define AT91C_SPI_RDRF ( ( unsigned int ) 0x1 << 0 ) /* (SPI) Receive Data Register Full */ +#define AT91C_SPI_TDRE ( ( unsigned int ) 0x1 << 1 ) /* (SPI) Transmit Data Register Empty */ +#define AT91C_SPI_MODF ( ( unsigned int ) 0x1 << 2 ) /* (SPI) Mode Fault Error */ +#define AT91C_SPI_OVRES ( ( unsigned int ) 0x1 << 3 ) /* (SPI) Overrun Error Status */ +#define AT91C_SPI_ENDRX ( ( unsigned int ) 0x1 << 4 ) /* (SPI) End of Receiver Transfer */ +#define AT91C_SPI_ENDTX ( ( unsigned int ) 0x1 << 5 ) /* (SPI) End of Receiver Transfer */ +#define AT91C_SPI_RXBUFF ( ( unsigned int ) 0x1 << 6 ) /* (SPI) RXBUFF Interrupt */ +#define AT91C_SPI_TXBUFE ( ( unsigned int ) 0x1 << 7 ) /* (SPI) TXBUFE Interrupt */ +#define AT91C_SPI_NSSR ( ( unsigned int ) 0x1 << 8 ) /* (SPI) NSSR Interrupt */ +#define AT91C_SPI_TXEMPTY ( ( unsigned int ) 0x1 << 9 ) /* (SPI) TXEMPTY Interrupt */ +#define AT91C_SPI_SPIENS ( ( unsigned int ) 0x1 << 16 ) /* (SPI) Enable Status */ +/* -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register -------- */ +/* -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register -------- */ +/* -------- SPI_IMR : (SPI Offset: 0x1c) Interrupt Mask Register -------- */ +/* -------- SPI_CSR : (SPI Offset: 0x30) Chip Select Register -------- */ +#define AT91C_SPI_CPOL ( ( unsigned int ) 0x1 << 0 ) /* (SPI) Clock Polarity */ +#define AT91C_SPI_NCPHA ( ( unsigned int ) 0x1 << 1 ) /* (SPI) Clock Phase */ +#define AT91C_SPI_CSAAT ( ( unsigned int ) 0x1 << 3 ) /* (SPI) Chip Select Active After Transfer */ +#define AT91C_SPI_BITS ( ( unsigned int ) 0xF << 4 ) /* (SPI) Bits Per Transfer */ +#define AT91C_SPI_BITS_8 ( ( unsigned int ) 0x0 << 4 ) /* (SPI) 8 Bits Per transfer */ +#define AT91C_SPI_BITS_9 ( ( unsigned int ) 0x1 << 4 ) /* (SPI) 9 Bits Per transfer */ +#define AT91C_SPI_BITS_10 ( ( unsigned int ) 0x2 << 4 ) /* (SPI) 10 Bits Per transfer */ +#define AT91C_SPI_BITS_11 ( ( unsigned int ) 0x3 << 4 ) /* (SPI) 11 Bits Per transfer */ +#define AT91C_SPI_BITS_12 ( ( unsigned int ) 0x4 << 4 ) /* (SPI) 12 Bits Per transfer */ +#define AT91C_SPI_BITS_13 ( ( unsigned int ) 0x5 << 4 ) /* (SPI) 13 Bits Per transfer */ +#define AT91C_SPI_BITS_14 ( ( unsigned int ) 0x6 << 4 ) /* (SPI) 14 Bits Per transfer */ +#define AT91C_SPI_BITS_15 ( ( unsigned int ) 0x7 << 4 ) /* (SPI) 15 Bits Per transfer */ +#define AT91C_SPI_BITS_16 ( ( unsigned int ) 0x8 << 4 ) /* (SPI) 16 Bits Per transfer */ +#define AT91C_SPI_SCBR ( ( unsigned int ) 0xFF << 8 ) /* (SPI) Serial Clock Baud Rate */ +#define AT91C_SPI_DLYBS ( ( unsigned int ) 0xFF << 16 ) /* (SPI) Delay Before SPCK */ +#define AT91C_SPI_DLYBCT ( ( unsigned int ) 0xFF << 24 ) /* (SPI) Delay Between Consecutive Transfers */ + +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR Usart */ +/* ***************************************************************************** */ +typedef struct _AT91S_USART +{ + AT91_REG US_CR; /* Control Register */ + AT91_REG US_MR; /* Mode Register */ + AT91_REG US_IER; /* Interrupt Enable Register */ + AT91_REG US_IDR; /* Interrupt Disable Register */ + AT91_REG US_IMR; /* Interrupt Mask Register */ + AT91_REG US_CSR; /* Channel Status Register */ + AT91_REG US_RHR; /* Receiver Holding Register */ + AT91_REG US_THR; /* Transmitter Holding Register */ + AT91_REG US_BRGR; /* Baud Rate Generator Register */ + AT91_REG US_RTOR; /* Receiver Time-out Register */ + AT91_REG US_TTGR; /* Transmitter Time-guard Register */ + AT91_REG Reserved0[ 5 ]; /* */ + AT91_REG US_FIDI; /* FI_DI_Ratio Register */ + AT91_REG US_NER; /* Nb Errors Register */ + AT91_REG Reserved1[ 1 ]; /* */ + AT91_REG US_IF; /* IRDA_FILTER Register */ + AT91_REG Reserved2[ 44 ]; /* */ + AT91_REG US_RPR; /* Receive Pointer Register */ + AT91_REG US_RCR; /* Receive Counter Register */ + AT91_REG US_TPR; /* Transmit Pointer Register */ + AT91_REG US_TCR; /* Transmit Counter Register */ + AT91_REG US_RNPR; /* Receive Next Pointer Register */ + AT91_REG US_RNCR; /* Receive Next Counter Register */ + AT91_REG US_TNPR; /* Transmit Next Pointer Register */ + AT91_REG US_TNCR; /* Transmit Next Counter Register */ + AT91_REG US_PTCR; /* PDC Transfer Control Register */ + AT91_REG US_PTSR; /* PDC Transfer Status Register */ +} AT91S_USART, * AT91PS_USART; + +/* -------- US_CR : (USART Offset: 0x0) Debug Unit Control Register -------- */ +#define AT91C_US_STTBRK ( ( unsigned int ) 0x1 << 9 ) /* (USART) Start Break */ +#define AT91C_US_STPBRK ( ( unsigned int ) 0x1 << 10 ) /* (USART) Stop Break */ +#define AT91C_US_STTTO ( ( unsigned int ) 0x1 << 11 ) /* (USART) Start Time-out */ +#define AT91C_US_SENDA ( ( unsigned int ) 0x1 << 12 ) /* (USART) Send Address */ +#define AT91C_US_RSTIT ( ( unsigned int ) 0x1 << 13 ) /* (USART) Reset Iterations */ +#define AT91C_US_RSTNACK ( ( unsigned int ) 0x1 << 14 ) /* (USART) Reset Non Acknowledge */ +#define AT91C_US_RETTO ( ( unsigned int ) 0x1 << 15 ) /* (USART) Rearm Time-out */ +#define AT91C_US_DTREN ( ( unsigned int ) 0x1 << 16 ) /* (USART) Data Terminal ready Enable */ +#define AT91C_US_DTRDIS ( ( unsigned int ) 0x1 << 17 ) /* (USART) Data Terminal ready Disable */ +#define AT91C_US_RTSEN ( ( unsigned int ) 0x1 << 18 ) /* (USART) Request to Send enable */ +#define AT91C_US_RTSDIS ( ( unsigned int ) 0x1 << 19 ) /* (USART) Request to Send Disable */ +/* -------- US_MR : (USART Offset: 0x4) Debug Unit Mode Register -------- */ +#define AT91C_US_USMODE ( ( unsigned int ) 0xF << 0 ) /* (USART) Usart mode */ +#define AT91C_US_USMODE_NORMAL ( ( unsigned int ) 0x0 ) /* (USART) Normal */ +#define AT91C_US_USMODE_RS485 ( ( unsigned int ) 0x1 ) /* (USART) RS485 */ +#define AT91C_US_USMODE_HWHSH ( ( unsigned int ) 0x2 ) /* (USART) Hardware Handshaking */ +#define AT91C_US_USMODE_MODEM ( ( unsigned int ) 0x3 ) /* (USART) Modem */ +#define AT91C_US_USMODE_ISO7816_0 ( ( unsigned int ) 0x4 ) /* (USART) ISO7816 protocol: T = 0 */ +#define AT91C_US_USMODE_ISO7816_1 ( ( unsigned int ) 0x6 ) /* (USART) ISO7816 protocol: T = 1 */ +#define AT91C_US_USMODE_IRDA ( ( unsigned int ) 0x8 ) /* (USART) IrDA */ +#define AT91C_US_USMODE_SWHSH ( ( unsigned int ) 0xC ) /* (USART) Software Handshaking */ +#define AT91C_US_CLKS ( ( unsigned int ) 0x3 << 4 ) /* (USART) Clock Selection (Baud Rate generator Input Clock */ +#define AT91C_US_CLKS_CLOCK ( ( unsigned int ) 0x0 << 4 ) /* (USART) Clock */ +#define AT91C_US_CLKS_FDIV1 ( ( unsigned int ) 0x1 << 4 ) /* (USART) fdiv1 */ +#define AT91C_US_CLKS_SLOW ( ( unsigned int ) 0x2 << 4 ) /* (USART) slow_clock (ARM) */ +#define AT91C_US_CLKS_EXT ( ( unsigned int ) 0x3 << 4 ) /* (USART) External (SCK) */ +#define AT91C_US_CHRL ( ( unsigned int ) 0x3 << 6 ) /* (USART) Clock Selection (Baud Rate generator Input Clock */ +#define AT91C_US_CHRL_5_BITS ( ( unsigned int ) 0x0 << 6 ) /* (USART) Character Length: 5 bits */ +#define AT91C_US_CHRL_6_BITS ( ( unsigned int ) 0x1 << 6 ) /* (USART) Character Length: 6 bits */ +#define AT91C_US_CHRL_7_BITS ( ( unsigned int ) 0x2 << 6 ) /* (USART) Character Length: 7 bits */ +#define AT91C_US_CHRL_8_BITS ( ( unsigned int ) 0x3 << 6 ) /* (USART) Character Length: 8 bits */ +#define AT91C_US_SYNC ( ( unsigned int ) 0x1 << 8 ) /* (USART) Synchronous Mode Select */ +#define AT91C_US_NBSTOP ( ( unsigned int ) 0x3 << 12 ) /* (USART) Number of Stop bits */ +#define AT91C_US_NBSTOP_1_BIT ( ( unsigned int ) 0x0 << 12 ) /* (USART) 1 stop bit */ +#define AT91C_US_NBSTOP_15_BIT ( ( unsigned int ) 0x1 << 12 ) /* (USART) Asynchronous (SYNC=0) 2 stop bits Synchronous (SYNC=1) 2 stop bits */ +#define AT91C_US_NBSTOP_2_BIT ( ( unsigned int ) 0x2 << 12 ) /* (USART) 2 stop bits */ +#define AT91C_US_MSBF ( ( unsigned int ) 0x1 << 16 ) /* (USART) Bit Order */ +#define AT91C_US_MODE9 ( ( unsigned int ) 0x1 << 17 ) /* (USART) 9-bit Character length */ +#define AT91C_US_CKLO ( ( unsigned int ) 0x1 << 18 ) /* (USART) Clock Output Select */ +#define AT91C_US_OVER ( ( unsigned int ) 0x1 << 19 ) /* (USART) Over Sampling Mode */ +#define AT91C_US_INACK ( ( unsigned int ) 0x1 << 20 ) /* (USART) Inhibit Non Acknowledge */ +#define AT91C_US_DSNACK ( ( unsigned int ) 0x1 << 21 ) /* (USART) Disable Successive NACK */ +#define AT91C_US_MAX_ITER ( ( unsigned int ) 0x1 << 24 ) /* (USART) Number of Repetitions */ +#define AT91C_US_FILTER ( ( unsigned int ) 0x1 << 28 ) /* (USART) Receive Line Filter */ +/* -------- US_IER : (USART Offset: 0x8) Debug Unit Interrupt Enable Register -------- */ +#define AT91C_US_RXBRK ( ( unsigned int ) 0x1 << 2 ) /* (USART) Break Received/End of Break */ +#define AT91C_US_TIMEOUT ( ( unsigned int ) 0x1 << 8 ) /* (USART) Receiver Time-out */ +#define AT91C_US_ITERATION ( ( unsigned int ) 0x1 << 10 ) /* (USART) Max number of Repetitions Reached */ +#define AT91C_US_NACK ( ( unsigned int ) 0x1 << 13 ) /* (USART) Non Acknowledge */ +#define AT91C_US_RIIC ( ( unsigned int ) 0x1 << 16 ) /* (USART) Ring INdicator Input Change Flag */ +#define AT91C_US_DSRIC ( ( unsigned int ) 0x1 << 17 ) /* (USART) Data Set Ready Input Change Flag */ +#define AT91C_US_DCDIC ( ( unsigned int ) 0x1 << 18 ) /* (USART) Data Carrier Flag */ +#define AT91C_US_CTSIC ( ( unsigned int ) 0x1 << 19 ) /* (USART) Clear To Send Input Change Flag */ +/* -------- US_IDR : (USART Offset: 0xc) Debug Unit Interrupt Disable Register -------- */ +/* -------- US_IMR : (USART Offset: 0x10) Debug Unit Interrupt Mask Register -------- */ +/* -------- US_CSR : (USART Offset: 0x14) Debug Unit Channel Status Register -------- */ +#define AT91C_US_RI ( ( unsigned int ) 0x1 << 20 ) /* (USART) Image of RI Input */ +#define AT91C_US_DSR ( ( unsigned int ) 0x1 << 21 ) /* (USART) Image of DSR Input */ +#define AT91C_US_DCD ( ( unsigned int ) 0x1 << 22 ) /* (USART) Image of DCD Input */ +#define AT91C_US_CTS ( ( unsigned int ) 0x1 << 23 ) /* (USART) Image of CTS Input */ + +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR Synchronous Serial Controller Interface */ +/* ***************************************************************************** */ +typedef struct _AT91S_SSC +{ + AT91_REG SSC_CR; /* Control Register */ + AT91_REG SSC_CMR; /* Clock Mode Register */ + AT91_REG Reserved0[ 2 ]; /* */ + AT91_REG SSC_RCMR; /* Receive Clock ModeRegister */ + AT91_REG SSC_RFMR; /* Receive Frame Mode Register */ + AT91_REG SSC_TCMR; /* Transmit Clock Mode Register */ + AT91_REG SSC_TFMR; /* Transmit Frame Mode Register */ + AT91_REG SSC_RHR; /* Receive Holding Register */ + AT91_REG SSC_THR; /* Transmit Holding Register */ + AT91_REG Reserved1[ 2 ]; /* */ + AT91_REG SSC_RSHR; /* Receive Sync Holding Register */ + AT91_REG SSC_TSHR; /* Transmit Sync Holding Register */ + AT91_REG Reserved2[ 2 ]; /* */ + AT91_REG SSC_SR; /* Status Register */ + AT91_REG SSC_IER; /* Interrupt Enable Register */ + AT91_REG SSC_IDR; /* Interrupt Disable Register */ + AT91_REG SSC_IMR; /* Interrupt Mask Register */ + AT91_REG Reserved3[ 44 ]; /* */ + AT91_REG SSC_RPR; /* Receive Pointer Register */ + AT91_REG SSC_RCR; /* Receive Counter Register */ + AT91_REG SSC_TPR; /* Transmit Pointer Register */ + AT91_REG SSC_TCR; /* Transmit Counter Register */ + AT91_REG SSC_RNPR; /* Receive Next Pointer Register */ + AT91_REG SSC_RNCR; /* Receive Next Counter Register */ + AT91_REG SSC_TNPR; /* Transmit Next Pointer Register */ + AT91_REG SSC_TNCR; /* Transmit Next Counter Register */ + AT91_REG SSC_PTCR; /* PDC Transfer Control Register */ + AT91_REG SSC_PTSR; /* PDC Transfer Status Register */ +} AT91S_SSC, * AT91PS_SSC; + +/* -------- SSC_CR : (SSC Offset: 0x0) SSC Control Register -------- */ +#define AT91C_SSC_RXEN ( ( unsigned int ) 0x1 << 0 ) /* (SSC) Receive Enable */ +#define AT91C_SSC_RXDIS ( ( unsigned int ) 0x1 << 1 ) /* (SSC) Receive Disable */ +#define AT91C_SSC_TXEN ( ( unsigned int ) 0x1 << 8 ) /* (SSC) Transmit Enable */ +#define AT91C_SSC_TXDIS ( ( unsigned int ) 0x1 << 9 ) /* (SSC) Transmit Disable */ +#define AT91C_SSC_SWRST ( ( unsigned int ) 0x1 << 15 ) /* (SSC) Software Reset */ +/* -------- SSC_RCMR : (SSC Offset: 0x10) SSC Receive Clock Mode Register -------- */ +#define AT91C_SSC_CKS ( ( unsigned int ) 0x3 << 0 ) /* (SSC) Receive/Transmit Clock Selection */ +#define AT91C_SSC_CKS_DIV ( ( unsigned int ) 0x0 ) /* (SSC) Divided Clock */ +#define AT91C_SSC_CKS_TK ( ( unsigned int ) 0x1 ) /* (SSC) TK Clock signal */ +#define AT91C_SSC_CKS_RK ( ( unsigned int ) 0x2 ) /* (SSC) RK pin */ +#define AT91C_SSC_CKO ( ( unsigned int ) 0x7 << 2 ) /* (SSC) Receive/Transmit Clock Output Mode Selection */ +#define AT91C_SSC_CKO_NONE ( ( unsigned int ) 0x0 << 2 ) /* (SSC) Receive/Transmit Clock Output Mode: None RK pin: Input-only */ +#define AT91C_SSC_CKO_CONTINUOUS ( ( unsigned int ) 0x1 << 2 ) /* (SSC) Continuous Receive/Transmit Clock RK pin: Output */ +#define AT91C_SSC_CKO_DATA_TX ( ( unsigned int ) 0x2 << 2 ) /* (SSC) Receive/Transmit Clock only during data transfers RK pin: Output */ +#define AT91C_SSC_CKI ( ( unsigned int ) 0x1 << 5 ) /* (SSC) Receive/Transmit Clock Inversion */ +#define AT91C_SSC_START ( ( unsigned int ) 0xF << 8 ) /* (SSC) Receive/Transmit Start Selection */ +#define AT91C_SSC_START_CONTINUOUS ( ( unsigned int ) 0x0 << 8 ) /* (SSC) Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data. */ +#define AT91C_SSC_START_TX ( ( unsigned int ) 0x1 << 8 ) /* (SSC) Transmit/Receive start */ +#define AT91C_SSC_START_LOW_RF ( ( unsigned int ) 0x2 << 8 ) /* (SSC) Detection of a low level on RF input */ +#define AT91C_SSC_START_HIGH_RF ( ( unsigned int ) 0x3 << 8 ) /* (SSC) Detection of a high level on RF input */ +#define AT91C_SSC_START_FALL_RF ( ( unsigned int ) 0x4 << 8 ) /* (SSC) Detection of a falling edge on RF input */ +#define AT91C_SSC_START_RISE_RF ( ( unsigned int ) 0x5 << 8 ) /* (SSC) Detection of a rising edge on RF input */ +#define AT91C_SSC_START_LEVEL_RF ( ( unsigned int ) 0x6 << 8 ) /* (SSC) Detection of any level change on RF input */ +#define AT91C_SSC_START_EDGE_RF ( ( unsigned int ) 0x7 << 8 ) /* (SSC) Detection of any edge on RF input */ +#define AT91C_SSC_START_0 ( ( unsigned int ) 0x8 << 8 ) /* (SSC) Compare 0 */ +#define AT91C_SSC_STTDLY ( ( unsigned int ) 0xFF << 16 ) /* (SSC) Receive/Transmit Start Delay */ +#define AT91C_SSC_PERIOD ( ( unsigned int ) 0xFF << 24 ) /* (SSC) Receive/Transmit Period Divider Selection */ +/* -------- SSC_RFMR : (SSC Offset: 0x14) SSC Receive Frame Mode Register -------- */ +#define AT91C_SSC_DATLEN ( ( unsigned int ) 0x1F << 0 ) /* (SSC) Data Length */ +#define AT91C_SSC_LOOP ( ( unsigned int ) 0x1 << 5 ) /* (SSC) Loop Mode */ +#define AT91C_SSC_MSBF ( ( unsigned int ) 0x1 << 7 ) /* (SSC) Most Significant Bit First */ +#define AT91C_SSC_DATNB ( ( unsigned int ) 0xF << 8 ) /* (SSC) Data Number per Frame */ +#define AT91C_SSC_FSLEN ( ( unsigned int ) 0xF << 16 ) /* (SSC) Receive/Transmit Frame Sync length */ +#define AT91C_SSC_FSOS ( ( unsigned int ) 0x7 << 20 ) /* (SSC) Receive/Transmit Frame Sync Output Selection */ +#define AT91C_SSC_FSOS_NONE ( ( unsigned int ) 0x0 << 20 ) /* (SSC) Selected Receive/Transmit Frame Sync Signal: None RK pin Input-only */ +#define AT91C_SSC_FSOS_NEGATIVE ( ( unsigned int ) 0x1 << 20 ) /* (SSC) Selected Receive/Transmit Frame Sync Signal: Negative Pulse */ +#define AT91C_SSC_FSOS_POSITIVE ( ( unsigned int ) 0x2 << 20 ) /* (SSC) Selected Receive/Transmit Frame Sync Signal: Positive Pulse */ +#define AT91C_SSC_FSOS_LOW ( ( unsigned int ) 0x3 << 20 ) /* (SSC) Selected Receive/Transmit Frame Sync Signal: Driver Low during data transfer */ +#define AT91C_SSC_FSOS_HIGH ( ( unsigned int ) 0x4 << 20 ) /* (SSC) Selected Receive/Transmit Frame Sync Signal: Driver High during data transfer */ +#define AT91C_SSC_FSOS_TOGGLE ( ( unsigned int ) 0x5 << 20 ) /* (SSC) Selected Receive/Transmit Frame Sync Signal: Toggling at each start of data transfer */ +#define AT91C_SSC_FSEDGE ( ( unsigned int ) 0x1 << 24 ) /* (SSC) Frame Sync Edge Detection */ +/* -------- SSC_TCMR : (SSC Offset: 0x18) SSC Transmit Clock Mode Register -------- */ +/* -------- SSC_TFMR : (SSC Offset: 0x1c) SSC Transmit Frame Mode Register -------- */ +#define AT91C_SSC_DATDEF ( ( unsigned int ) 0x1 << 5 ) /* (SSC) Data Default Value */ +#define AT91C_SSC_FSDEN ( ( unsigned int ) 0x1 << 23 ) /* (SSC) Frame Sync Data Enable */ +/* -------- SSC_SR : (SSC Offset: 0x40) SSC Status Register -------- */ +#define AT91C_SSC_TXRDY ( ( unsigned int ) 0x1 << 0 ) /* (SSC) Transmit Ready */ +#define AT91C_SSC_TXEMPTY ( ( unsigned int ) 0x1 << 1 ) /* (SSC) Transmit Empty */ +#define AT91C_SSC_ENDTX ( ( unsigned int ) 0x1 << 2 ) /* (SSC) End Of Transmission */ +#define AT91C_SSC_TXBUFE ( ( unsigned int ) 0x1 << 3 ) /* (SSC) Transmit Buffer Empty */ +#define AT91C_SSC_RXRDY ( ( unsigned int ) 0x1 << 4 ) /* (SSC) Receive Ready */ +#define AT91C_SSC_OVRUN ( ( unsigned int ) 0x1 << 5 ) /* (SSC) Receive Overrun */ +#define AT91C_SSC_ENDRX ( ( unsigned int ) 0x1 << 6 ) /* (SSC) End of Reception */ +#define AT91C_SSC_RXBUFF ( ( unsigned int ) 0x1 << 7 ) /* (SSC) Receive Buffer Full */ +#define AT91C_SSC_TXSYN ( ( unsigned int ) 0x1 << 10 ) /* (SSC) Transmit Sync */ +#define AT91C_SSC_RXSYN ( ( unsigned int ) 0x1 << 11 ) /* (SSC) Receive Sync */ +#define AT91C_SSC_TXENA ( ( unsigned int ) 0x1 << 16 ) /* (SSC) Transmit Enable */ +#define AT91C_SSC_RXENA ( ( unsigned int ) 0x1 << 17 ) /* (SSC) Receive Enable */ +/* -------- SSC_IER : (SSC Offset: 0x44) SSC Interrupt Enable Register -------- */ +/* -------- SSC_IDR : (SSC Offset: 0x48) SSC Interrupt Disable Register -------- */ +/* -------- SSC_IMR : (SSC Offset: 0x4c) SSC Interrupt Mask Register -------- */ + +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR Two-wire Interface */ +/* ***************************************************************************** */ +typedef struct _AT91S_TWI +{ + AT91_REG TWI_CR; /* Control Register */ + AT91_REG TWI_MMR; /* Master Mode Register */ + AT91_REG Reserved0[ 1 ]; /* */ + AT91_REG TWI_IADR; /* Internal Address Register */ + AT91_REG TWI_CWGR; /* Clock Waveform Generator Register */ + AT91_REG Reserved1[ 3 ]; /* */ + AT91_REG TWI_SR; /* Status Register */ + AT91_REG TWI_IER; /* Interrupt Enable Register */ + AT91_REG TWI_IDR; /* Interrupt Disable Register */ + AT91_REG TWI_IMR; /* Interrupt Mask Register */ + AT91_REG TWI_RHR; /* Receive Holding Register */ + AT91_REG TWI_THR; /* Transmit Holding Register */ +} AT91S_TWI, * AT91PS_TWI; + +/* -------- TWI_CR : (TWI Offset: 0x0) TWI Control Register -------- */ +#define AT91C_TWI_START ( ( unsigned int ) 0x1 << 0 ) /* (TWI) Send a START Condition */ +#define AT91C_TWI_STOP ( ( unsigned int ) 0x1 << 1 ) /* (TWI) Send a STOP Condition */ +#define AT91C_TWI_MSEN ( ( unsigned int ) 0x1 << 2 ) /* (TWI) TWI Master Transfer Enabled */ +#define AT91C_TWI_MSDIS ( ( unsigned int ) 0x1 << 3 ) /* (TWI) TWI Master Transfer Disabled */ +#define AT91C_TWI_SWRST ( ( unsigned int ) 0x1 << 7 ) /* (TWI) Software Reset */ +/* -------- TWI_MMR : (TWI Offset: 0x4) TWI Master Mode Register -------- */ +#define AT91C_TWI_IADRSZ ( ( unsigned int ) 0x3 << 8 ) /* (TWI) Internal Device Address Size */ +#define AT91C_TWI_IADRSZ_NO ( ( unsigned int ) 0x0 << 8 ) /* (TWI) No internal device address */ +#define AT91C_TWI_IADRSZ_1_BYTE ( ( unsigned int ) 0x1 << 8 ) /* (TWI) One-byte internal device address */ +#define AT91C_TWI_IADRSZ_2_BYTE ( ( unsigned int ) 0x2 << 8 ) /* (TWI) Two-byte internal device address */ +#define AT91C_TWI_IADRSZ_3_BYTE ( ( unsigned int ) 0x3 << 8 ) /* (TWI) Three-byte internal device address */ +#define AT91C_TWI_MREAD ( ( unsigned int ) 0x1 << 12 ) /* (TWI) Master Read Direction */ +#define AT91C_TWI_DADR ( ( unsigned int ) 0x7F << 16 ) /* (TWI) Device Address */ +/* -------- TWI_CWGR : (TWI Offset: 0x10) TWI Clock Waveform Generator Register -------- */ +#define AT91C_TWI_CLDIV ( ( unsigned int ) 0xFF << 0 ) /* (TWI) Clock Low Divider */ +#define AT91C_TWI_CHDIV ( ( unsigned int ) 0xFF << 8 ) /* (TWI) Clock High Divider */ +#define AT91C_TWI_CKDIV ( ( unsigned int ) 0x7 << 16 ) /* (TWI) Clock Divider */ +/* -------- TWI_SR : (TWI Offset: 0x20) TWI Status Register -------- */ +#define AT91C_TWI_TXCOMP ( ( unsigned int ) 0x1 << 0 ) /* (TWI) Transmission Completed */ +#define AT91C_TWI_RXRDY ( ( unsigned int ) 0x1 << 1 ) /* (TWI) Receive holding register ReaDY */ +#define AT91C_TWI_TXRDY ( ( unsigned int ) 0x1 << 2 ) /* (TWI) Transmit holding register ReaDY */ +#define AT91C_TWI_OVRE ( ( unsigned int ) 0x1 << 6 ) /* (TWI) Overrun Error */ +#define AT91C_TWI_UNRE ( ( unsigned int ) 0x1 << 7 ) /* (TWI) Underrun Error */ +#define AT91C_TWI_NACK ( ( unsigned int ) 0x1 << 8 ) /* (TWI) Not Acknowledged */ +/* -------- TWI_IER : (TWI Offset: 0x24) TWI Interrupt Enable Register -------- */ +/* -------- TWI_IDR : (TWI Offset: 0x28) TWI Interrupt Disable Register -------- */ +/* -------- TWI_IMR : (TWI Offset: 0x2c) TWI Interrupt Mask Register -------- */ + +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR PWMC Channel Interface */ +/* ***************************************************************************** */ +typedef struct _AT91S_PWMC_CH +{ + AT91_REG PWMC_CMR; /* Channel Mode Register */ + AT91_REG PWMC_CDTYR; /* Channel Duty Cycle Register */ + AT91_REG PWMC_CPRDR; /* Channel Period Register */ + AT91_REG PWMC_CCNTR; /* Channel Counter Register */ + AT91_REG PWMC_CUPDR; /* Channel Update Register */ + AT91_REG PWMC_Reserved[ 3 ]; /* Reserved */ +} AT91S_PWMC_CH, * AT91PS_PWMC_CH; + +/* -------- PWMC_CMR : (PWMC_CH Offset: 0x0) PWMC Channel Mode Register -------- */ +#define AT91C_PWMC_CPRE ( ( unsigned int ) 0xF << 0 ) /* (PWMC_CH) Channel Pre-scaler : PWMC_CLKx */ +#define AT91C_PWMC_CPRE_MCK ( ( unsigned int ) 0x0 ) /* (PWMC_CH) */ +#define AT91C_PWMC_CPRE_MCKA ( ( unsigned int ) 0xB ) /* (PWMC_CH) */ +#define AT91C_PWMC_CPRE_MCKB ( ( unsigned int ) 0xC ) /* (PWMC_CH) */ +#define AT91C_PWMC_CALG ( ( unsigned int ) 0x1 << 8 ) /* (PWMC_CH) Channel Alignment */ +#define AT91C_PWMC_CPOL ( ( unsigned int ) 0x1 << 9 ) /* (PWMC_CH) Channel Polarity */ +#define AT91C_PWMC_CPD ( ( unsigned int ) 0x1 << 10 ) /* (PWMC_CH) Channel Update Period */ +/* -------- PWMC_CDTYR : (PWMC_CH Offset: 0x4) PWMC Channel Duty Cycle Register -------- */ +#define AT91C_PWMC_CDTY ( ( unsigned int ) 0x0 << 0 ) /* (PWMC_CH) Channel Duty Cycle */ +/* -------- PWMC_CPRDR : (PWMC_CH Offset: 0x8) PWMC Channel Period Register -------- */ +#define AT91C_PWMC_CPRD ( ( unsigned int ) 0x0 << 0 ) /* (PWMC_CH) Channel Period */ +/* -------- PWMC_CCNTR : (PWMC_CH Offset: 0xc) PWMC Channel Counter Register -------- */ +#define AT91C_PWMC_CCNT ( ( unsigned int ) 0x0 << 0 ) /* (PWMC_CH) Channel Counter */ +/* -------- PWMC_CUPDR : (PWMC_CH Offset: 0x10) PWMC Channel Update Register -------- */ +#define AT91C_PWMC_CUPD ( ( unsigned int ) 0x0 << 0 ) /* (PWMC_CH) Channel Update */ + +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR Pulse Width Modulation Controller Interface */ +/* ***************************************************************************** */ +typedef struct _AT91S_PWMC +{ + AT91_REG PWMC_MR; /* PWMC Mode Register */ + AT91_REG PWMC_ENA; /* PWMC Enable Register */ + AT91_REG PWMC_DIS; /* PWMC Disable Register */ + AT91_REG PWMC_SR; /* PWMC Status Register */ + AT91_REG PWMC_IER; /* PWMC Interrupt Enable Register */ + AT91_REG PWMC_IDR; /* PWMC Interrupt Disable Register */ + AT91_REG PWMC_IMR; /* PWMC Interrupt Mask Register */ + AT91_REG PWMC_ISR; /* PWMC Interrupt Status Register */ + AT91_REG Reserved0[ 55 ]; /* */ + AT91_REG PWMC_VR; /* PWMC Version Register */ + AT91_REG Reserved1[ 64 ]; /* */ + AT91S_PWMC_CH PWMC_CH[ 4 ]; /* PWMC Channel */ +} AT91S_PWMC, * AT91PS_PWMC; + +/* -------- PWMC_MR : (PWMC Offset: 0x0) PWMC Mode Register -------- */ +#define AT91C_PWMC_DIVA ( ( unsigned int ) 0xFF << 0 ) /* (PWMC) CLKA divide factor. */ +#define AT91C_PWMC_PREA ( ( unsigned int ) 0xF << 8 ) /* (PWMC) Divider Input Clock Prescaler A */ +#define AT91C_PWMC_PREA_MCK ( ( unsigned int ) 0x0 << 8 ) /* (PWMC) */ +#define AT91C_PWMC_DIVB ( ( unsigned int ) 0xFF << 16 ) /* (PWMC) CLKB divide factor. */ +#define AT91C_PWMC_PREB ( ( unsigned int ) 0xF << 24 ) /* (PWMC) Divider Input Clock Prescaler B */ +#define AT91C_PWMC_PREB_MCK ( ( unsigned int ) 0x0 << 24 ) /* (PWMC) */ +/* -------- PWMC_ENA : (PWMC Offset: 0x4) PWMC Enable Register -------- */ +#define AT91C_PWMC_CHID0 ( ( unsigned int ) 0x1 << 0 ) /* (PWMC) Channel ID 0 */ +#define AT91C_PWMC_CHID1 ( ( unsigned int ) 0x1 << 1 ) /* (PWMC) Channel ID 1 */ +#define AT91C_PWMC_CHID2 ( ( unsigned int ) 0x1 << 2 ) /* (PWMC) Channel ID 2 */ +#define AT91C_PWMC_CHID3 ( ( unsigned int ) 0x1 << 3 ) /* (PWMC) Channel ID 3 */ +/* -------- PWMC_DIS : (PWMC Offset: 0x8) PWMC Disable Register -------- */ +/* -------- PWMC_SR : (PWMC Offset: 0xc) PWMC Status Register -------- */ +/* -------- PWMC_IER : (PWMC Offset: 0x10) PWMC Interrupt Enable Register -------- */ +/* -------- PWMC_IDR : (PWMC Offset: 0x14) PWMC Interrupt Disable Register -------- */ +/* -------- PWMC_IMR : (PWMC Offset: 0x18) PWMC Interrupt Mask Register -------- */ +/* -------- PWMC_ISR : (PWMC Offset: 0x1c) PWMC Interrupt Status Register -------- */ + +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR USB Device Interface */ +/* ***************************************************************************** */ +typedef struct _AT91S_UDP +{ + AT91_REG UDP_NUM; /* Frame Number Register */ + AT91_REG UDP_GLBSTATE; /* Global State Register */ + AT91_REG UDP_FADDR; /* Function Address Register */ + AT91_REG Reserved0[ 1 ]; /* */ + AT91_REG UDP_IER; /* Interrupt Enable Register */ + AT91_REG UDP_IDR; /* Interrupt Disable Register */ + AT91_REG UDP_IMR; /* Interrupt Mask Register */ + AT91_REG UDP_ISR; /* Interrupt Status Register */ + AT91_REG UDP_ICR; /* Interrupt Clear Register */ + AT91_REG Reserved1[ 1 ]; /* */ + AT91_REG UDP_RSTEP; /* Reset Endpoint Register */ + AT91_REG Reserved2[ 1 ]; /* */ + AT91_REG UDP_CSR[ 6 ]; /* Endpoint Control and Status Register */ + AT91_REG Reserved3[ 2 ]; /* */ + AT91_REG UDP_FDR[ 6 ]; /* Endpoint FIFO Data Register */ + AT91_REG Reserved4[ 3 ]; /* */ + AT91_REG UDP_TXVC; /* Transceiver Control Register */ +} AT91S_UDP, * AT91PS_UDP; + +/* -------- UDP_FRM_NUM : (UDP Offset: 0x0) USB Frame Number Register -------- */ +#define AT91C_UDP_FRM_NUM ( ( unsigned int ) 0x7FF << 0 ) /* (UDP) Frame Number as Defined in the Packet Field Formats */ +#define AT91C_UDP_FRM_ERR ( ( unsigned int ) 0x1 << 16 ) /* (UDP) Frame Error */ +#define AT91C_UDP_FRM_OK ( ( unsigned int ) 0x1 << 17 ) /* (UDP) Frame OK */ +/* -------- UDP_GLB_STATE : (UDP Offset: 0x4) USB Global State Register -------- */ +#define AT91C_UDP_FADDEN ( ( unsigned int ) 0x1 << 0 ) /* (UDP) Function Address Enable */ +#define AT91C_UDP_CONFG ( ( unsigned int ) 0x1 << 1 ) /* (UDP) Configured */ +#define AT91C_UDP_ESR ( ( unsigned int ) 0x1 << 2 ) /* (UDP) Enable Send Resume */ +#define AT91C_UDP_RSMINPR ( ( unsigned int ) 0x1 << 3 ) /* (UDP) A Resume Has Been Sent to the Host */ +#define AT91C_UDP_RMWUPE ( ( unsigned int ) 0x1 << 4 ) /* (UDP) Remote Wake Up Enable */ +/* -------- UDP_FADDR : (UDP Offset: 0x8) USB Function Address Register -------- */ +#define AT91C_UDP_FADD ( ( unsigned int ) 0xFF << 0 ) /* (UDP) Function Address Value */ +#define AT91C_UDP_FEN ( ( unsigned int ) 0x1 << 8 ) /* (UDP) Function Enable */ +/* -------- UDP_IER : (UDP Offset: 0x10) USB Interrupt Enable Register -------- */ +#define AT91C_UDP_EPINT0 ( ( unsigned int ) 0x1 << 0 ) /* (UDP) Endpoint 0 Interrupt */ +#define AT91C_UDP_EPINT1 ( ( unsigned int ) 0x1 << 1 ) /* (UDP) Endpoint 0 Interrupt */ +#define AT91C_UDP_EPINT2 ( ( unsigned int ) 0x1 << 2 ) /* (UDP) Endpoint 2 Interrupt */ +#define AT91C_UDP_EPINT3 ( ( unsigned int ) 0x1 << 3 ) /* (UDP) Endpoint 3 Interrupt */ +#define AT91C_UDP_EPINT4 ( ( unsigned int ) 0x1 << 4 ) /* (UDP) Endpoint 4 Interrupt */ +#define AT91C_UDP_EPINT5 ( ( unsigned int ) 0x1 << 5 ) /* (UDP) Endpoint 5 Interrupt */ +#define AT91C_UDP_RXSUSP ( ( unsigned int ) 0x1 << 8 ) /* (UDP) USB Suspend Interrupt */ +#define AT91C_UDP_RXRSM ( ( unsigned int ) 0x1 << 9 ) /* (UDP) USB Resume Interrupt */ +#define AT91C_UDP_EXTRSM ( ( unsigned int ) 0x1 << 10 ) /* (UDP) USB External Resume Interrupt */ +#define AT91C_UDP_SOFINT ( ( unsigned int ) 0x1 << 11 ) /* (UDP) USB Start Of frame Interrupt */ +#define AT91C_UDP_WAKEUP ( ( unsigned int ) 0x1 << 13 ) /* (UDP) USB Resume Interrupt */ +/* -------- UDP_IDR : (UDP Offset: 0x14) USB Interrupt Disable Register -------- */ +/* -------- UDP_IMR : (UDP Offset: 0x18) USB Interrupt Mask Register -------- */ +/* -------- UDP_ISR : (UDP Offset: 0x1c) USB Interrupt Status Register -------- */ +#define AT91C_UDP_ENDBUSRES ( ( unsigned int ) 0x1 << 12 ) /* (UDP) USB End Of Bus Reset Interrupt */ +/* -------- UDP_ICR : (UDP Offset: 0x20) USB Interrupt Clear Register -------- */ +/* -------- UDP_RST_EP : (UDP Offset: 0x28) USB Reset Endpoint Register -------- */ +#define AT91C_UDP_EP0 ( ( unsigned int ) 0x1 << 0 ) /* (UDP) Reset Endpoint 0 */ +#define AT91C_UDP_EP1 ( ( unsigned int ) 0x1 << 1 ) /* (UDP) Reset Endpoint 1 */ +#define AT91C_UDP_EP2 ( ( unsigned int ) 0x1 << 2 ) /* (UDP) Reset Endpoint 2 */ +#define AT91C_UDP_EP3 ( ( unsigned int ) 0x1 << 3 ) /* (UDP) Reset Endpoint 3 */ +#define AT91C_UDP_EP4 ( ( unsigned int ) 0x1 << 4 ) /* (UDP) Reset Endpoint 4 */ +#define AT91C_UDP_EP5 ( ( unsigned int ) 0x1 << 5 ) /* (UDP) Reset Endpoint 5 */ +/* -------- UDP_CSR : (UDP Offset: 0x30) USB Endpoint Control and Status Register -------- */ +#define AT91C_UDP_TXCOMP ( ( unsigned int ) 0x1 << 0 ) /* (UDP) Generates an IN packet with data previously written in the DPR */ +#define AT91C_UDP_RX_DATA_BK0 ( ( unsigned int ) 0x1 << 1 ) /* (UDP) Receive Data Bank 0 */ +#define AT91C_UDP_RXSETUP ( ( unsigned int ) 0x1 << 2 ) /* (UDP) Sends STALL to the Host (Control endpoints) */ +#define AT91C_UDP_ISOERROR ( ( unsigned int ) 0x1 << 3 ) /* (UDP) Isochronous error (Isochronous endpoints) */ +#define AT91C_UDP_TXPKTRDY ( ( unsigned int ) 0x1 << 4 ) /* (UDP) Transmit Packet Ready */ +#define AT91C_UDP_FORCESTALL ( ( unsigned int ) 0x1 << 5 ) /* (UDP) Force Stall (used by Control, Bulk and Isochronous endpoints). */ +#define AT91C_UDP_RX_DATA_BK1 ( ( unsigned int ) 0x1 << 6 ) /* (UDP) Receive Data Bank 1 (only used by endpoints with ping-pong attributes). */ +#define AT91C_UDP_DIR ( ( unsigned int ) 0x1 << 7 ) /* (UDP) Transfer Direction */ +#define AT91C_UDP_EPTYPE ( ( unsigned int ) 0x7 << 8 ) /* (UDP) Endpoint type */ +#define AT91C_UDP_EPTYPE_CTRL ( ( unsigned int ) 0x0 << 8 ) /* (UDP) Control */ +#define AT91C_UDP_EPTYPE_ISO_OUT ( ( unsigned int ) 0x1 << 8 ) /* (UDP) Isochronous OUT */ +#define AT91C_UDP_EPTYPE_BULK_OUT ( ( unsigned int ) 0x2 << 8 ) /* (UDP) Bulk OUT */ +#define AT91C_UDP_EPTYPE_INT_OUT ( ( unsigned int ) 0x3 << 8 ) /* (UDP) Interrupt OUT */ +#define AT91C_UDP_EPTYPE_ISO_IN ( ( unsigned int ) 0x5 << 8 ) /* (UDP) Isochronous IN */ +#define AT91C_UDP_EPTYPE_BULK_IN ( ( unsigned int ) 0x6 << 8 ) /* (UDP) Bulk IN */ +#define AT91C_UDP_EPTYPE_INT_IN ( ( unsigned int ) 0x7 << 8 ) /* (UDP) Interrupt IN */ +#define AT91C_UDP_DTGLE ( ( unsigned int ) 0x1 << 11 ) /* (UDP) Data Toggle */ +#define AT91C_UDP_EPEDS ( ( unsigned int ) 0x1 << 15 ) /* (UDP) Endpoint Enable Disable */ +#define AT91C_UDP_RXBYTECNT ( ( unsigned int ) 0x7FF << 16 ) /* (UDP) Number Of Bytes Available in the FIFO */ +/* -------- UDP_TXVC : (UDP Offset: 0x74) Transceiver Control Register -------- */ +#define AT91C_UDP_TXVDIS ( ( unsigned int ) 0x1 << 8 ) /* (UDP) */ +#define AT91C_UDP_PUON ( ( unsigned int ) 0x1 << 9 ) /* (UDP) Pull-up ON */ + +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR Timer Counter Channel Interface */ +/* ***************************************************************************** */ +typedef struct _AT91S_TC +{ + AT91_REG TC_CCR; /* Channel Control Register */ + AT91_REG TC_CMR; /* Channel Mode Register (Capture Mode / Waveform Mode) */ + AT91_REG Reserved0[ 2 ]; /* */ + AT91_REG TC_CV; /* Counter Value */ + AT91_REG TC_RA; /* Register A */ + AT91_REG TC_RB; /* Register B */ + AT91_REG TC_RC; /* Register C */ + AT91_REG TC_SR; /* Status Register */ + AT91_REG TC_IER; /* Interrupt Enable Register */ + AT91_REG TC_IDR; /* Interrupt Disable Register */ + AT91_REG TC_IMR; /* Interrupt Mask Register */ +} AT91S_TC, * AT91PS_TC; + +/* -------- TC_CCR : (TC Offset: 0x0) TC Channel Control Register -------- */ +#define AT91C_TC_CLKEN ( ( unsigned int ) 0x1 << 0 ) /* (TC) Counter Clock Enable Command */ +#define AT91C_TC_CLKDIS ( ( unsigned int ) 0x1 << 1 ) /* (TC) Counter Clock Disable Command */ +#define AT91C_TC_SWTRG ( ( unsigned int ) 0x1 << 2 ) /* (TC) Software Trigger Command */ +/* -------- TC_CMR : (TC Offset: 0x4) TC Channel Mode Register: Capture Mode / Waveform Mode -------- */ +#define AT91C_TC_CLKS ( ( unsigned int ) 0x7 << 0 ) /* (TC) Clock Selection */ +#define AT91C_TC_CLKS_TIMER_DIV1_CLOCK ( ( unsigned int ) 0x0 ) /* (TC) Clock selected: TIMER_DIV1_CLOCK */ +#define AT91C_TC_CLKS_TIMER_DIV2_CLOCK ( ( unsigned int ) 0x1 ) /* (TC) Clock selected: TIMER_DIV2_CLOCK */ +#define AT91C_TC_CLKS_TIMER_DIV3_CLOCK ( ( unsigned int ) 0x2 ) /* (TC) Clock selected: TIMER_DIV3_CLOCK */ +#define AT91C_TC_CLKS_TIMER_DIV4_CLOCK ( ( unsigned int ) 0x3 ) /* (TC) Clock selected: TIMER_DIV4_CLOCK */ +#define AT91C_TC_CLKS_TIMER_DIV5_CLOCK ( ( unsigned int ) 0x4 ) /* (TC) Clock selected: TIMER_DIV5_CLOCK */ +#define AT91C_TC_CLKS_XC0 ( ( unsigned int ) 0x5 ) /* (TC) Clock selected: XC0 */ +#define AT91C_TC_CLKS_XC1 ( ( unsigned int ) 0x6 ) /* (TC) Clock selected: XC1 */ +#define AT91C_TC_CLKS_XC2 ( ( unsigned int ) 0x7 ) /* (TC) Clock selected: XC2 */ +#define AT91C_TC_CLKI ( ( unsigned int ) 0x1 << 3 ) /* (TC) Clock Invert */ +#define AT91C_TC_BURST ( ( unsigned int ) 0x3 << 4 ) /* (TC) Burst Signal Selection */ +#define AT91C_TC_BURST_NONE ( ( unsigned int ) 0x0 << 4 ) /* (TC) The clock is not gated by an external signal */ +#define AT91C_TC_BURST_XC0 ( ( unsigned int ) 0x1 << 4 ) /* (TC) XC0 is ANDed with the selected clock */ +#define AT91C_TC_BURST_XC1 ( ( unsigned int ) 0x2 << 4 ) /* (TC) XC1 is ANDed with the selected clock */ +#define AT91C_TC_BURST_XC2 ( ( unsigned int ) 0x3 << 4 ) /* (TC) XC2 is ANDed with the selected clock */ +#define AT91C_TC_CPCSTOP ( ( unsigned int ) 0x1 << 6 ) /* (TC) Counter Clock Stopped with RC Compare */ +#define AT91C_TC_LDBSTOP ( ( unsigned int ) 0x1 << 6 ) /* (TC) Counter Clock Stopped with RB Loading */ +#define AT91C_TC_CPCDIS ( ( unsigned int ) 0x1 << 7 ) /* (TC) Counter Clock Disable with RC Compare */ +#define AT91C_TC_LDBDIS ( ( unsigned int ) 0x1 << 7 ) /* (TC) Counter Clock Disabled with RB Loading */ +#define AT91C_TC_ETRGEDG ( ( unsigned int ) 0x3 << 8 ) /* (TC) External Trigger Edge Selection */ +#define AT91C_TC_ETRGEDG_NONE ( ( unsigned int ) 0x0 << 8 ) /* (TC) Edge: None */ +#define AT91C_TC_ETRGEDG_RISING ( ( unsigned int ) 0x1 << 8 ) /* (TC) Edge: rising edge */ +#define AT91C_TC_ETRGEDG_FALLING ( ( unsigned int ) 0x2 << 8 ) /* (TC) Edge: falling edge */ +#define AT91C_TC_ETRGEDG_BOTH ( ( unsigned int ) 0x3 << 8 ) /* (TC) Edge: each edge */ +#define AT91C_TC_EEVTEDG ( ( unsigned int ) 0x3 << 8 ) /* (TC) External Event Edge Selection */ +#define AT91C_TC_EEVTEDG_NONE ( ( unsigned int ) 0x0 << 8 ) /* (TC) Edge: None */ +#define AT91C_TC_EEVTEDG_RISING ( ( unsigned int ) 0x1 << 8 ) /* (TC) Edge: rising edge */ +#define AT91C_TC_EEVTEDG_FALLING ( ( unsigned int ) 0x2 << 8 ) /* (TC) Edge: falling edge */ +#define AT91C_TC_EEVTEDG_BOTH ( ( unsigned int ) 0x3 << 8 ) /* (TC) Edge: each edge */ +#define AT91C_TC_EEVT ( ( unsigned int ) 0x3 << 10 ) /* (TC) External Event Selection */ +#define AT91C_TC_EEVT_TIOB ( ( unsigned int ) 0x0 << 10 ) /* (TC) Signal selected as external event: TIOB TIOB direction: input */ +#define AT91C_TC_EEVT_XC0 ( ( unsigned int ) 0x1 << 10 ) /* (TC) Signal selected as external event: XC0 TIOB direction: output */ +#define AT91C_TC_EEVT_XC1 ( ( unsigned int ) 0x2 << 10 ) /* (TC) Signal selected as external event: XC1 TIOB direction: output */ +#define AT91C_TC_EEVT_XC2 ( ( unsigned int ) 0x3 << 10 ) /* (TC) Signal selected as external event: XC2 TIOB direction: output */ +#define AT91C_TC_ABETRG ( ( unsigned int ) 0x1 << 10 ) /* (TC) TIOA or TIOB External Trigger Selection */ +#define AT91C_TC_ENETRG ( ( unsigned int ) 0x1 << 12 ) /* (TC) External Event Trigger enable */ +#define AT91C_TC_WAVESEL ( ( unsigned int ) 0x3 << 13 ) /* (TC) Waveform Selection */ +#define AT91C_TC_WAVESEL_UP ( ( unsigned int ) 0x0 << 13 ) /* (TC) UP mode without atomatic trigger on RC Compare */ +#define AT91C_TC_WAVESEL_UPDOWN ( ( unsigned int ) 0x1 << 13 ) /* (TC) UPDOWN mode without automatic trigger on RC Compare */ +#define AT91C_TC_WAVESEL_UP_AUTO ( ( unsigned int ) 0x2 << 13 ) /* (TC) UP mode with automatic trigger on RC Compare */ +#define AT91C_TC_WAVESEL_UPDOWN_AUTO ( ( unsigned int ) 0x3 << 13 ) /* (TC) UPDOWN mode with automatic trigger on RC Compare */ +#define AT91C_TC_CPCTRG ( ( unsigned int ) 0x1 << 14 ) /* (TC) RC Compare Trigger Enable */ +#define AT91C_TC_WAVE ( ( unsigned int ) 0x1 << 15 ) /* (TC) */ +#define AT91C_TC_ACPA ( ( unsigned int ) 0x3 << 16 ) /* (TC) RA Compare Effect on TIOA */ +#define AT91C_TC_ACPA_NONE ( ( unsigned int ) 0x0 << 16 ) /* (TC) Effect: none */ +#define AT91C_TC_ACPA_SET ( ( unsigned int ) 0x1 << 16 ) /* (TC) Effect: set */ +#define AT91C_TC_ACPA_CLEAR ( ( unsigned int ) 0x2 << 16 ) /* (TC) Effect: clear */ +#define AT91C_TC_ACPA_TOGGLE ( ( unsigned int ) 0x3 << 16 ) /* (TC) Effect: toggle */ +#define AT91C_TC_LDRA ( ( unsigned int ) 0x3 << 16 ) /* (TC) RA Loading Selection */ +#define AT91C_TC_LDRA_NONE ( ( unsigned int ) 0x0 << 16 ) /* (TC) Edge: None */ +#define AT91C_TC_LDRA_RISING ( ( unsigned int ) 0x1 << 16 ) /* (TC) Edge: rising edge of TIOA */ +#define AT91C_TC_LDRA_FALLING ( ( unsigned int ) 0x2 << 16 ) /* (TC) Edge: falling edge of TIOA */ +#define AT91C_TC_LDRA_BOTH ( ( unsigned int ) 0x3 << 16 ) /* (TC) Edge: each edge of TIOA */ +#define AT91C_TC_ACPC ( ( unsigned int ) 0x3 << 18 ) /* (TC) RC Compare Effect on TIOA */ +#define AT91C_TC_ACPC_NONE ( ( unsigned int ) 0x0 << 18 ) /* (TC) Effect: none */ +#define AT91C_TC_ACPC_SET ( ( unsigned int ) 0x1 << 18 ) /* (TC) Effect: set */ +#define AT91C_TC_ACPC_CLEAR ( ( unsigned int ) 0x2 << 18 ) /* (TC) Effect: clear */ +#define AT91C_TC_ACPC_TOGGLE ( ( unsigned int ) 0x3 << 18 ) /* (TC) Effect: toggle */ +#define AT91C_TC_LDRB ( ( unsigned int ) 0x3 << 18 ) /* (TC) RB Loading Selection */ +#define AT91C_TC_LDRB_NONE ( ( unsigned int ) 0x0 << 18 ) /* (TC) Edge: None */ +#define AT91C_TC_LDRB_RISING ( ( unsigned int ) 0x1 << 18 ) /* (TC) Edge: rising edge of TIOA */ +#define AT91C_TC_LDRB_FALLING ( ( unsigned int ) 0x2 << 18 ) /* (TC) Edge: falling edge of TIOA */ +#define AT91C_TC_LDRB_BOTH ( ( unsigned int ) 0x3 << 18 ) /* (TC) Edge: each edge of TIOA */ +#define AT91C_TC_AEEVT ( ( unsigned int ) 0x3 << 20 ) /* (TC) External Event Effect on TIOA */ +#define AT91C_TC_AEEVT_NONE ( ( unsigned int ) 0x0 << 20 ) /* (TC) Effect: none */ +#define AT91C_TC_AEEVT_SET ( ( unsigned int ) 0x1 << 20 ) /* (TC) Effect: set */ +#define AT91C_TC_AEEVT_CLEAR ( ( unsigned int ) 0x2 << 20 ) /* (TC) Effect: clear */ +#define AT91C_TC_AEEVT_TOGGLE ( ( unsigned int ) 0x3 << 20 ) /* (TC) Effect: toggle */ +#define AT91C_TC_ASWTRG ( ( unsigned int ) 0x3 << 22 ) /* (TC) Software Trigger Effect on TIOA */ +#define AT91C_TC_ASWTRG_NONE ( ( unsigned int ) 0x0 << 22 ) /* (TC) Effect: none */ +#define AT91C_TC_ASWTRG_SET ( ( unsigned int ) 0x1 << 22 ) /* (TC) Effect: set */ +#define AT91C_TC_ASWTRG_CLEAR ( ( unsigned int ) 0x2 << 22 ) /* (TC) Effect: clear */ +#define AT91C_TC_ASWTRG_TOGGLE ( ( unsigned int ) 0x3 << 22 ) /* (TC) Effect: toggle */ +#define AT91C_TC_BCPB ( ( unsigned int ) 0x3 << 24 ) /* (TC) RB Compare Effect on TIOB */ +#define AT91C_TC_BCPB_NONE ( ( unsigned int ) 0x0 << 24 ) /* (TC) Effect: none */ +#define AT91C_TC_BCPB_SET ( ( unsigned int ) 0x1 << 24 ) /* (TC) Effect: set */ +#define AT91C_TC_BCPB_CLEAR ( ( unsigned int ) 0x2 << 24 ) /* (TC) Effect: clear */ +#define AT91C_TC_BCPB_TOGGLE ( ( unsigned int ) 0x3 << 24 ) /* (TC) Effect: toggle */ +#define AT91C_TC_BCPC ( ( unsigned int ) 0x3 << 26 ) /* (TC) RC Compare Effect on TIOB */ +#define AT91C_TC_BCPC_NONE ( ( unsigned int ) 0x0 << 26 ) /* (TC) Effect: none */ +#define AT91C_TC_BCPC_SET ( ( unsigned int ) 0x1 << 26 ) /* (TC) Effect: set */ +#define AT91C_TC_BCPC_CLEAR ( ( unsigned int ) 0x2 << 26 ) /* (TC) Effect: clear */ +#define AT91C_TC_BCPC_TOGGLE ( ( unsigned int ) 0x3 << 26 ) /* (TC) Effect: toggle */ +#define AT91C_TC_BEEVT ( ( unsigned int ) 0x3 << 28 ) /* (TC) External Event Effect on TIOB */ +#define AT91C_TC_BEEVT_NONE ( ( unsigned int ) 0x0 << 28 ) /* (TC) Effect: none */ +#define AT91C_TC_BEEVT_SET ( ( unsigned int ) 0x1 << 28 ) /* (TC) Effect: set */ +#define AT91C_TC_BEEVT_CLEAR ( ( unsigned int ) 0x2 << 28 ) /* (TC) Effect: clear */ +#define AT91C_TC_BEEVT_TOGGLE ( ( unsigned int ) 0x3 << 28 ) /* (TC) Effect: toggle */ +#define AT91C_TC_BSWTRG ( ( unsigned int ) 0x3 << 30 ) /* (TC) Software Trigger Effect on TIOB */ +#define AT91C_TC_BSWTRG_NONE ( ( unsigned int ) 0x0 << 30 ) /* (TC) Effect: none */ +#define AT91C_TC_BSWTRG_SET ( ( unsigned int ) 0x1 << 30 ) /* (TC) Effect: set */ +#define AT91C_TC_BSWTRG_CLEAR ( ( unsigned int ) 0x2 << 30 ) /* (TC) Effect: clear */ +#define AT91C_TC_BSWTRG_TOGGLE ( ( unsigned int ) 0x3 << 30 ) /* (TC) Effect: toggle */ +/* -------- TC_SR : (TC Offset: 0x20) TC Channel Status Register -------- */ +#define AT91C_TC_COVFS ( ( unsigned int ) 0x1 << 0 ) /* (TC) Counter Overflow */ +#define AT91C_TC_LOVRS ( ( unsigned int ) 0x1 << 1 ) /* (TC) Load Overrun */ +#define AT91C_TC_CPAS ( ( unsigned int ) 0x1 << 2 ) /* (TC) RA Compare */ +#define AT91C_TC_CPBS ( ( unsigned int ) 0x1 << 3 ) /* (TC) RB Compare */ +#define AT91C_TC_CPCS ( ( unsigned int ) 0x1 << 4 ) /* (TC) RC Compare */ +#define AT91C_TC_LDRAS ( ( unsigned int ) 0x1 << 5 ) /* (TC) RA Loading */ +#define AT91C_TC_LDRBS ( ( unsigned int ) 0x1 << 6 ) /* (TC) RB Loading */ +#define AT91C_TC_ETRGS ( ( unsigned int ) 0x1 << 7 ) /* (TC) External Trigger */ +#define AT91C_TC_CLKSTA ( ( unsigned int ) 0x1 << 16 ) /* (TC) Clock Enabling */ +#define AT91C_TC_MTIOA ( ( unsigned int ) 0x1 << 17 ) /* (TC) TIOA Mirror */ +#define AT91C_TC_MTIOB ( ( unsigned int ) 0x1 << 18 ) /* (TC) TIOA Mirror */ +/* -------- TC_IER : (TC Offset: 0x24) TC Channel Interrupt Enable Register -------- */ +/* -------- TC_IDR : (TC Offset: 0x28) TC Channel Interrupt Disable Register -------- */ +/* -------- TC_IMR : (TC Offset: 0x2c) TC Channel Interrupt Mask Register -------- */ + +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR Timer Counter Interface */ +/* ***************************************************************************** */ +typedef struct _AT91S_TCB +{ + AT91S_TC TCB_TC0; /* TC Channel 0 */ + AT91_REG Reserved0[ 4 ]; /* */ + AT91S_TC TCB_TC1; /* TC Channel 1 */ + AT91_REG Reserved1[ 4 ]; /* */ + AT91S_TC TCB_TC2; /* TC Channel 2 */ + AT91_REG Reserved2[ 4 ]; /* */ + AT91_REG TCB_BCR; /* TC Block Control Register */ + AT91_REG TCB_BMR; /* TC Block Mode Register */ +} AT91S_TCB, * AT91PS_TCB; + +/* -------- TCB_BCR : (TCB Offset: 0xc0) TC Block Control Register -------- */ +#define AT91C_TCB_SYNC ( ( unsigned int ) 0x1 << 0 ) /* (TCB) Synchro Command */ +/* -------- TCB_BMR : (TCB Offset: 0xc4) TC Block Mode Register -------- */ +#define AT91C_TCB_TC0XC0S ( ( unsigned int ) 0x3 << 0 ) /* (TCB) External Clock Signal 0 Selection */ +#define AT91C_TCB_TC0XC0S_TCLK0 ( ( unsigned int ) 0x0 ) /* (TCB) TCLK0 connected to XC0 */ +#define AT91C_TCB_TC0XC0S_NONE ( ( unsigned int ) 0x1 ) /* (TCB) None signal connected to XC0 */ +#define AT91C_TCB_TC0XC0S_TIOA1 ( ( unsigned int ) 0x2 ) /* (TCB) TIOA1 connected to XC0 */ +#define AT91C_TCB_TC0XC0S_TIOA2 ( ( unsigned int ) 0x3 ) /* (TCB) TIOA2 connected to XC0 */ +#define AT91C_TCB_TC1XC1S ( ( unsigned int ) 0x3 << 2 ) /* (TCB) External Clock Signal 1 Selection */ +#define AT91C_TCB_TC1XC1S_TCLK1 ( ( unsigned int ) 0x0 << 2 ) /* (TCB) TCLK1 connected to XC1 */ +#define AT91C_TCB_TC1XC1S_NONE ( ( unsigned int ) 0x1 << 2 ) /* (TCB) None signal connected to XC1 */ +#define AT91C_TCB_TC1XC1S_TIOA0 ( ( unsigned int ) 0x2 << 2 ) /* (TCB) TIOA0 connected to XC1 */ +#define AT91C_TCB_TC1XC1S_TIOA2 ( ( unsigned int ) 0x3 << 2 ) /* (TCB) TIOA2 connected to XC1 */ +#define AT91C_TCB_TC2XC2S ( ( unsigned int ) 0x3 << 4 ) /* (TCB) External Clock Signal 2 Selection */ +#define AT91C_TCB_TC2XC2S_TCLK2 ( ( unsigned int ) 0x0 << 4 ) /* (TCB) TCLK2 connected to XC2 */ +#define AT91C_TCB_TC2XC2S_NONE ( ( unsigned int ) 0x1 << 4 ) /* (TCB) None signal connected to XC2 */ +#define AT91C_TCB_TC2XC2S_TIOA0 ( ( unsigned int ) 0x2 << 4 ) /* (TCB) TIOA0 connected to XC2 */ +#define AT91C_TCB_TC2XC2S_TIOA1 ( ( unsigned int ) 0x3 << 4 ) /* (TCB) TIOA2 connected to XC2 */ + +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR Control Area Network MailBox Interface */ +/* ***************************************************************************** */ +typedef struct _AT91S_CAN_MB +{ + AT91_REG CAN_MB_MMR; /* MailBox Mode Register */ + AT91_REG CAN_MB_MAM; /* MailBox Acceptance Mask Register */ + AT91_REG CAN_MB_MID; /* MailBox ID Register */ + AT91_REG CAN_MB_MFID; /* MailBox Family ID Register */ + AT91_REG CAN_MB_MSR; /* MailBox Status Register */ + AT91_REG CAN_MB_MDL; /* MailBox Data Low Register */ + AT91_REG CAN_MB_MDH; /* MailBox Data High Register */ + AT91_REG CAN_MB_MCR; /* MailBox Control Register */ +} AT91S_CAN_MB, * AT91PS_CAN_MB; + +/* -------- CAN_MMR : (CAN_MB Offset: 0x0) CAN Message Mode Register -------- */ +#define AT91C_CAN_MTIMEMARK ( ( unsigned int ) 0xFFFF << 0 ) /* (CAN_MB) Mailbox Timemark */ +#define AT91C_CAN_PRIOR ( ( unsigned int ) 0xF << 16 ) /* (CAN_MB) Mailbox Priority */ +#define AT91C_CAN_MOT ( ( unsigned int ) 0x7 << 24 ) /* (CAN_MB) Mailbox Object Type */ +#define AT91C_CAN_MOT_DIS ( ( unsigned int ) 0x0 << 24 ) /* (CAN_MB) */ +#define AT91C_CAN_MOT_RX ( ( unsigned int ) 0x1 << 24 ) /* (CAN_MB) */ +#define AT91C_CAN_MOT_RXOVERWRITE ( ( unsigned int ) 0x2 << 24 ) /* (CAN_MB) */ +#define AT91C_CAN_MOT_TX ( ( unsigned int ) 0x3 << 24 ) /* (CAN_MB) */ +#define AT91C_CAN_MOT_CONSUMER ( ( unsigned int ) 0x4 << 24 ) /* (CAN_MB) */ +#define AT91C_CAN_MOT_PRODUCER ( ( unsigned int ) 0x5 << 24 ) /* (CAN_MB) */ +/* -------- CAN_MAM : (CAN_MB Offset: 0x4) CAN Message Acceptance Mask Register -------- */ +#define AT91C_CAN_MIDvB ( ( unsigned int ) 0x3FFFF << 0 ) /* (CAN_MB) Complementary bits for identifier in extended mode */ +#define AT91C_CAN_MIDvA ( ( unsigned int ) 0x7FF << 18 ) /* (CAN_MB) Identifier for standard frame mode */ +#define AT91C_CAN_MIDE ( ( unsigned int ) 0x1 << 29 ) /* (CAN_MB) Identifier Version */ +/* -------- CAN_MID : (CAN_MB Offset: 0x8) CAN Message ID Register -------- */ +/* -------- CAN_MFID : (CAN_MB Offset: 0xc) CAN Message Family ID Register -------- */ +/* -------- CAN_MSR : (CAN_MB Offset: 0x10) CAN Message Status Register -------- */ +#define AT91C_CAN_MTIMESTAMP ( ( unsigned int ) 0xFFFF << 0 ) /* (CAN_MB) Timer Value */ +#define AT91C_CAN_MDLC ( ( unsigned int ) 0xF << 16 ) /* (CAN_MB) Mailbox Data Length Code */ +#define AT91C_CAN_MRTR ( ( unsigned int ) 0x1 << 20 ) /* (CAN_MB) Mailbox Remote Transmission Request */ +#define AT91C_CAN_MABT ( ( unsigned int ) 0x1 << 22 ) /* (CAN_MB) Mailbox Message Abort */ +#define AT91C_CAN_MRDY ( ( unsigned int ) 0x1 << 23 ) /* (CAN_MB) Mailbox Ready */ +#define AT91C_CAN_MMI ( ( unsigned int ) 0x1 << 24 ) /* (CAN_MB) Mailbox Message Ignored */ +/* -------- CAN_MDL : (CAN_MB Offset: 0x14) CAN Message Data Low Register -------- */ +/* -------- CAN_MDH : (CAN_MB Offset: 0x18) CAN Message Data High Register -------- */ +/* -------- CAN_MCR : (CAN_MB Offset: 0x1c) CAN Message Control Register -------- */ +#define AT91C_CAN_MACR ( ( unsigned int ) 0x1 << 22 ) /* (CAN_MB) Abort Request for Mailbox */ +#define AT91C_CAN_MTCR ( ( unsigned int ) 0x1 << 23 ) /* (CAN_MB) Mailbox Transfer Command */ + +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR Control Area Network Interface */ +/* ***************************************************************************** */ +typedef struct _AT91S_CAN +{ + AT91_REG CAN_MR; /* Mode Register */ + AT91_REG CAN_IER; /* Interrupt Enable Register */ + AT91_REG CAN_IDR; /* Interrupt Disable Register */ + AT91_REG CAN_IMR; /* Interrupt Mask Register */ + AT91_REG CAN_SR; /* Status Register */ + AT91_REG CAN_BR; /* Baudrate Register */ + AT91_REG CAN_TIM; /* Timer Register */ + AT91_REG CAN_TIMESTP; /* Time Stamp Register */ + AT91_REG CAN_ECR; /* Error Counter Register */ + AT91_REG CAN_TCR; /* Transfer Command Register */ + AT91_REG CAN_ACR; /* Abort Command Register */ + AT91_REG Reserved0[ 52 ]; /* */ + AT91_REG CAN_VR; /* Version Register */ + AT91_REG Reserved1[ 64 ]; /* */ + AT91S_CAN_MB CAN_MB0; /* CAN Mailbox 0 */ + AT91S_CAN_MB CAN_MB1; /* CAN Mailbox 1 */ + AT91S_CAN_MB CAN_MB2; /* CAN Mailbox 2 */ + AT91S_CAN_MB CAN_MB3; /* CAN Mailbox 3 */ + AT91S_CAN_MB CAN_MB4; /* CAN Mailbox 4 */ + AT91S_CAN_MB CAN_MB5; /* CAN Mailbox 5 */ + AT91S_CAN_MB CAN_MB6; /* CAN Mailbox 6 */ + AT91S_CAN_MB CAN_MB7; /* CAN Mailbox 7 */ + AT91S_CAN_MB CAN_MB8; /* CAN Mailbox 8 */ + AT91S_CAN_MB CAN_MB9; /* CAN Mailbox 9 */ + AT91S_CAN_MB CAN_MB10; /* CAN Mailbox 10 */ + AT91S_CAN_MB CAN_MB11; /* CAN Mailbox 11 */ + AT91S_CAN_MB CAN_MB12; /* CAN Mailbox 12 */ + AT91S_CAN_MB CAN_MB13; /* CAN Mailbox 13 */ + AT91S_CAN_MB CAN_MB14; /* CAN Mailbox 14 */ + AT91S_CAN_MB CAN_MB15; /* CAN Mailbox 15 */ +} AT91S_CAN, * AT91PS_CAN; + +/* -------- CAN_MR : (CAN Offset: 0x0) CAN Mode Register -------- */ +#define AT91C_CAN_CANEN ( ( unsigned int ) 0x1 << 0 ) /* (CAN) CAN Controller Enable */ +#define AT91C_CAN_LPM ( ( unsigned int ) 0x1 << 1 ) /* (CAN) Disable/Enable Low Power Mode */ +#define AT91C_CAN_ABM ( ( unsigned int ) 0x1 << 2 ) /* (CAN) Disable/Enable Autobaud/Listen Mode */ +#define AT91C_CAN_OVL ( ( unsigned int ) 0x1 << 3 ) /* (CAN) Disable/Enable Overload Frame */ +#define AT91C_CAN_TEOF ( ( unsigned int ) 0x1 << 4 ) /* (CAN) Time Stamp messages at each end of Frame */ +#define AT91C_CAN_TTM ( ( unsigned int ) 0x1 << 5 ) /* (CAN) Disable/Enable Time Trigger Mode */ +#define AT91C_CAN_TIMFRZ ( ( unsigned int ) 0x1 << 6 ) /* (CAN) Enable Timer Freeze */ +#define AT91C_CAN_DRPT ( ( unsigned int ) 0x1 << 7 ) /* (CAN) Disable Repeat */ +/* -------- CAN_IER : (CAN Offset: 0x4) CAN Interrupt Enable Register -------- */ +#define AT91C_CAN_MB0 ( ( unsigned int ) 0x1 << 0 ) /* (CAN) Mailbox 0 Flag */ +#define AT91C_CAN_MB1 ( ( unsigned int ) 0x1 << 1 ) /* (CAN) Mailbox 1 Flag */ +#define AT91C_CAN_MB2 ( ( unsigned int ) 0x1 << 2 ) /* (CAN) Mailbox 2 Flag */ +#define AT91C_CAN_MB3 ( ( unsigned int ) 0x1 << 3 ) /* (CAN) Mailbox 3 Flag */ +#define AT91C_CAN_MB4 ( ( unsigned int ) 0x1 << 4 ) /* (CAN) Mailbox 4 Flag */ +#define AT91C_CAN_MB5 ( ( unsigned int ) 0x1 << 5 ) /* (CAN) Mailbox 5 Flag */ +#define AT91C_CAN_MB6 ( ( unsigned int ) 0x1 << 6 ) /* (CAN) Mailbox 6 Flag */ +#define AT91C_CAN_MB7 ( ( unsigned int ) 0x1 << 7 ) /* (CAN) Mailbox 7 Flag */ +#define AT91C_CAN_MB8 ( ( unsigned int ) 0x1 << 8 ) /* (CAN) Mailbox 8 Flag */ +#define AT91C_CAN_MB9 ( ( unsigned int ) 0x1 << 9 ) /* (CAN) Mailbox 9 Flag */ +#define AT91C_CAN_MB10 ( ( unsigned int ) 0x1 << 10 ) /* (CAN) Mailbox 10 Flag */ +#define AT91C_CAN_MB11 ( ( unsigned int ) 0x1 << 11 ) /* (CAN) Mailbox 11 Flag */ +#define AT91C_CAN_MB12 ( ( unsigned int ) 0x1 << 12 ) /* (CAN) Mailbox 12 Flag */ +#define AT91C_CAN_MB13 ( ( unsigned int ) 0x1 << 13 ) /* (CAN) Mailbox 13 Flag */ +#define AT91C_CAN_MB14 ( ( unsigned int ) 0x1 << 14 ) /* (CAN) Mailbox 14 Flag */ +#define AT91C_CAN_MB15 ( ( unsigned int ) 0x1 << 15 ) /* (CAN) Mailbox 15 Flag */ +#define AT91C_CAN_ERRA ( ( unsigned int ) 0x1 << 16 ) /* (CAN) Error Active Mode Flag */ +#define AT91C_CAN_WARN ( ( unsigned int ) 0x1 << 17 ) /* (CAN) Warning Limit Flag */ +#define AT91C_CAN_ERRP ( ( unsigned int ) 0x1 << 18 ) /* (CAN) Error Passive Mode Flag */ +#define AT91C_CAN_BOFF ( ( unsigned int ) 0x1 << 19 ) /* (CAN) Bus Off Mode Flag */ +#define AT91C_CAN_SLEEP ( ( unsigned int ) 0x1 << 20 ) /* (CAN) Sleep Flag */ +#define AT91C_CAN_WAKEUP ( ( unsigned int ) 0x1 << 21 ) /* (CAN) Wakeup Flag */ +#define AT91C_CAN_TOVF ( ( unsigned int ) 0x1 << 22 ) /* (CAN) Timer Overflow Flag */ +#define AT91C_CAN_TSTP ( ( unsigned int ) 0x1 << 23 ) /* (CAN) Timestamp Flag */ +#define AT91C_CAN_CERR ( ( unsigned int ) 0x1 << 24 ) /* (CAN) CRC Error */ +#define AT91C_CAN_SERR ( ( unsigned int ) 0x1 << 25 ) /* (CAN) Stuffing Error */ +#define AT91C_CAN_AERR ( ( unsigned int ) 0x1 << 26 ) /* (CAN) Acknowledgment Error */ +#define AT91C_CAN_FERR ( ( unsigned int ) 0x1 << 27 ) /* (CAN) Form Error */ +#define AT91C_CAN_BERR ( ( unsigned int ) 0x1 << 28 ) /* (CAN) Bit Error */ +/* -------- CAN_IDR : (CAN Offset: 0x8) CAN Interrupt Disable Register -------- */ +/* -------- CAN_IMR : (CAN Offset: 0xc) CAN Interrupt Mask Register -------- */ +/* -------- CAN_SR : (CAN Offset: 0x10) CAN Status Register -------- */ +#define AT91C_CAN_RBSY ( ( unsigned int ) 0x1 << 29 ) /* (CAN) Receiver Busy */ +#define AT91C_CAN_TBSY ( ( unsigned int ) 0x1 << 30 ) /* (CAN) Transmitter Busy */ +#define AT91C_CAN_OVLY ( ( unsigned int ) 0x1 << 31 ) /* (CAN) Overload Busy */ +/* -------- CAN_BR : (CAN Offset: 0x14) CAN Baudrate Register -------- */ +#define AT91C_CAN_PHASE2 ( ( unsigned int ) 0x7 << 0 ) /* (CAN) Phase 2 segment */ +#define AT91C_CAN_PHASE1 ( ( unsigned int ) 0x7 << 4 ) /* (CAN) Phase 1 segment */ +#define AT91C_CAN_PROPAG ( ( unsigned int ) 0x7 << 8 ) /* (CAN) Programmation time segment */ +#define AT91C_CAN_SYNC ( ( unsigned int ) 0x3 << 12 ) /* (CAN) Re-synchronization jump width segment */ +#define AT91C_CAN_BRP ( ( unsigned int ) 0x7F << 16 ) /* (CAN) Baudrate Prescaler */ +#define AT91C_CAN_SMP ( ( unsigned int ) 0x1 << 24 ) /* (CAN) Sampling mode */ +/* -------- CAN_TIM : (CAN Offset: 0x18) CAN Timer Register -------- */ +#define AT91C_CAN_TIMER ( ( unsigned int ) 0xFFFF << 0 ) /* (CAN) Timer field */ +/* -------- CAN_TIMESTP : (CAN Offset: 0x1c) CAN Timestamp Register -------- */ +/* -------- CAN_ECR : (CAN Offset: 0x20) CAN Error Counter Register -------- */ +#define AT91C_CAN_REC ( ( unsigned int ) 0xFF << 0 ) /* (CAN) Receive Error Counter */ +#define AT91C_CAN_TEC ( ( unsigned int ) 0xFF << 16 ) /* (CAN) Transmit Error Counter */ +/* -------- CAN_TCR : (CAN Offset: 0x24) CAN Transfer Command Register -------- */ +#define AT91C_CAN_TIMRST ( ( unsigned int ) 0x1 << 31 ) /* (CAN) Timer Reset Field */ +/* -------- CAN_ACR : (CAN Offset: 0x28) CAN Abort Command Register -------- */ + +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR Ethernet MAC 10/100 */ +/* ***************************************************************************** */ +typedef struct _AT91S_EMAC +{ + AT91_REG EMAC_NCR; /* Network Control Register */ + AT91_REG EMAC_NCFGR; /* Network Configuration Register */ + AT91_REG EMAC_NSR; /* Network Status Register */ + AT91_REG Reserved0[ 2 ]; /* */ + AT91_REG EMAC_TSR; /* Transmit Status Register */ + AT91_REG EMAC_RBQP; /* Receive Buffer Queue Pointer */ + AT91_REG EMAC_TBQP; /* Transmit Buffer Queue Pointer */ + AT91_REG EMAC_RSR; /* Receive Status Register */ + AT91_REG EMAC_ISR; /* Interrupt Status Register */ + AT91_REG EMAC_IER; /* Interrupt Enable Register */ + AT91_REG EMAC_IDR; /* Interrupt Disable Register */ + AT91_REG EMAC_IMR; /* Interrupt Mask Register */ + AT91_REG EMAC_MAN; /* PHY Maintenance Register */ + AT91_REG EMAC_PTR; /* Pause Time Register */ + AT91_REG EMAC_PFR; /* Pause Frames received Register */ + AT91_REG EMAC_FTO; /* Frames Transmitted OK Register */ + AT91_REG EMAC_SCF; /* Single Collision Frame Register */ + AT91_REG EMAC_MCF; /* Multiple Collision Frame Register */ + AT91_REG EMAC_FRO; /* Frames Received OK Register */ + AT91_REG EMAC_FCSE; /* Frame Check Sequence Error Register */ + AT91_REG EMAC_ALE; /* Alignment Error Register */ + AT91_REG EMAC_DTF; /* Deferred Transmission Frame Register */ + AT91_REG EMAC_LCOL; /* Late Collision Register */ + AT91_REG EMAC_ECOL; /* Excessive Collision Register */ + AT91_REG EMAC_TUND; /* Transmit Underrun Error Register */ + AT91_REG EMAC_CSE; /* Carrier Sense Error Register */ + AT91_REG EMAC_RRE; /* Receive Ressource Error Register */ + AT91_REG EMAC_ROV; /* Receive Overrun Errors Register */ + AT91_REG EMAC_RSE; /* Receive Symbol Errors Register */ + AT91_REG EMAC_ELE; /* Excessive Length Errors Register */ + AT91_REG EMAC_RJA; /* Receive Jabbers Register */ + AT91_REG EMAC_USF; /* Undersize Frames Register */ + AT91_REG EMAC_STE; /* SQE Test Error Register */ + AT91_REG EMAC_RLE; /* Receive Length Field Mismatch Register */ + AT91_REG EMAC_TPF; /* Transmitted Pause Frames Register */ + AT91_REG EMAC_HRB; /* Hash Address Bottom[31:0] */ + AT91_REG EMAC_HRT; /* Hash Address Top[63:32] */ + AT91_REG EMAC_SA1L; /* Specific Address 1 Bottom, First 4 bytes */ + AT91_REG EMAC_SA1H; /* Specific Address 1 Top, Last 2 bytes */ + AT91_REG EMAC_SA2L; /* Specific Address 2 Bottom, First 4 bytes */ + AT91_REG EMAC_SA2H; /* Specific Address 2 Top, Last 2 bytes */ + AT91_REG EMAC_SA3L; /* Specific Address 3 Bottom, First 4 bytes */ + AT91_REG EMAC_SA3H; /* Specific Address 3 Top, Last 2 bytes */ + AT91_REG EMAC_SA4L; /* Specific Address 4 Bottom, First 4 bytes */ + AT91_REG EMAC_SA4H; /* Specific Address 4 Top, Last 2 bytes */ + AT91_REG EMAC_TID; /* Type ID Checking Register */ + AT91_REG EMAC_TPQ; /* Transmit Pause Quantum Register */ + AT91_REG EMAC_USRIO; /* USER Input/Output Register */ + AT91_REG EMAC_WOL; /* Wake On LAN Register */ + AT91_REG Reserved1[ 13 ]; /* */ + AT91_REG EMAC_REV; /* Revision Register */ +} AT91S_EMAC, * AT91PS_EMAC; + +/* -------- EMAC_NCR : (EMAC Offset: 0x0) -------- */ +#define AT91C_EMAC_LB ( ( unsigned int ) 0x1 << 0 ) /* (EMAC) Loopback. Optional. When set, loopback signal is at high level. */ +#define AT91C_EMAC_LLB ( ( unsigned int ) 0x1 << 1 ) /* (EMAC) Loopback local. */ +#define AT91C_EMAC_RE ( ( unsigned int ) 0x1 << 2 ) /* (EMAC) Receive enable. */ +#define AT91C_EMAC_TE ( ( unsigned int ) 0x1 << 3 ) /* (EMAC) Transmit enable. */ +#define AT91C_EMAC_MPE ( ( unsigned int ) 0x1 << 4 ) /* (EMAC) Management port enable. */ +#define AT91C_EMAC_CLRSTAT ( ( unsigned int ) 0x1 << 5 ) /* (EMAC) Clear statistics registers. */ +#define AT91C_EMAC_INCSTAT ( ( unsigned int ) 0x1 << 6 ) /* (EMAC) Increment statistics registers. */ +#define AT91C_EMAC_WESTAT ( ( unsigned int ) 0x1 << 7 ) /* (EMAC) Write enable for statistics registers. */ +#define AT91C_EMAC_BP ( ( unsigned int ) 0x1 << 8 ) /* (EMAC) Back pressure. */ +#define AT91C_EMAC_TSTART ( ( unsigned int ) 0x1 << 9 ) /* (EMAC) Start Transmission. */ +#define AT91C_EMAC_THALT ( ( unsigned int ) 0x1 << 10 ) /* (EMAC) Transmission Halt. */ +#define AT91C_EMAC_TPFR ( ( unsigned int ) 0x1 << 11 ) /* (EMAC) Transmit pause frame */ +#define AT91C_EMAC_TZQ ( ( unsigned int ) 0x1 << 12 ) /* (EMAC) Transmit zero quantum pause frame */ +/* -------- EMAC_NCFGR : (EMAC Offset: 0x4) Network Configuration Register -------- */ +#define AT91C_EMAC_SPD ( ( unsigned int ) 0x1 << 0 ) /* (EMAC) Speed. */ +#define AT91C_EMAC_FD ( ( unsigned int ) 0x1 << 1 ) /* (EMAC) Full duplex. */ +#define AT91C_EMAC_JFRAME ( ( unsigned int ) 0x1 << 3 ) /* (EMAC) Jumbo Frames. */ +#define AT91C_EMAC_CAF ( ( unsigned int ) 0x1 << 4 ) /* (EMAC) Copy all frames. */ +#define AT91C_EMAC_NBC ( ( unsigned int ) 0x1 << 5 ) /* (EMAC) No broadcast. */ +#define AT91C_EMAC_MTI ( ( unsigned int ) 0x1 << 6 ) /* (EMAC) Multicast hash event enable */ +#define AT91C_EMAC_UNI ( ( unsigned int ) 0x1 << 7 ) /* (EMAC) Unicast hash enable. */ +#define AT91C_EMAC_BIG ( ( unsigned int ) 0x1 << 8 ) /* (EMAC) Receive 1522 bytes. */ +#define AT91C_EMAC_EAE ( ( unsigned int ) 0x1 << 9 ) /* (EMAC) External address match enable. */ +#define AT91C_EMAC_CLK ( ( unsigned int ) 0x3 << 10 ) /* (EMAC) */ +#define AT91C_EMAC_CLK_HCLK_8 ( ( unsigned int ) 0x0 << 10 ) /* (EMAC) HCLK divided by 8 */ +#define AT91C_EMAC_CLK_HCLK_16 ( ( unsigned int ) 0x1 << 10 ) /* (EMAC) HCLK divided by 16 */ +#define AT91C_EMAC_CLK_HCLK_32 ( ( unsigned int ) 0x2 << 10 ) /* (EMAC) HCLK divided by 32 */ +#define AT91C_EMAC_CLK_HCLK_64 ( ( unsigned int ) 0x3 << 10 ) /* (EMAC) HCLK divided by 64 */ +#define AT91C_EMAC_RTY ( ( unsigned int ) 0x1 << 12 ) /* (EMAC) */ +#define AT91C_EMAC_PAE ( ( unsigned int ) 0x1 << 13 ) /* (EMAC) */ +#define AT91C_EMAC_RBOF ( ( unsigned int ) 0x3 << 14 ) /* (EMAC) */ +#define AT91C_EMAC_RBOF_OFFSET_0 ( ( unsigned int ) 0x0 << 14 ) /* (EMAC) no offset from start of receive buffer */ +#define AT91C_EMAC_RBOF_OFFSET_1 ( ( unsigned int ) 0x1 << 14 ) /* (EMAC) one byte offset from start of receive buffer */ +#define AT91C_EMAC_RBOF_OFFSET_2 ( ( unsigned int ) 0x2 << 14 ) /* (EMAC) two bytes offset from start of receive buffer */ +#define AT91C_EMAC_RBOF_OFFSET_3 ( ( unsigned int ) 0x3 << 14 ) /* (EMAC) three bytes offset from start of receive buffer */ +#define AT91C_EMAC_RLCE ( ( unsigned int ) 0x1 << 16 ) /* (EMAC) Receive Length field Checking Enable */ +#define AT91C_EMAC_DRFCS ( ( unsigned int ) 0x1 << 17 ) /* (EMAC) Discard Receive FCS */ +#define AT91C_EMAC_EFRHD ( ( unsigned int ) 0x1 << 18 ) /* (EMAC) */ +#define AT91C_EMAC_IRXFCS ( ( unsigned int ) 0x1 << 19 ) /* (EMAC) Ignore RX FCS */ +/* -------- EMAC_NSR : (EMAC Offset: 0x8) Network Status Register -------- */ +#define AT91C_EMAC_LINKR ( ( unsigned int ) 0x1 << 0 ) /* (EMAC) */ +#define AT91C_EMAC_MDIO ( ( unsigned int ) 0x1 << 1 ) /* (EMAC) */ +#define AT91C_EMAC_IDLE ( ( unsigned int ) 0x1 << 2 ) /* (EMAC) */ +/* -------- EMAC_TSR : (EMAC Offset: 0x14) Transmit Status Register -------- */ +#define AT91C_EMAC_UBR ( ( unsigned int ) 0x1 << 0 ) /* (EMAC) */ +#define AT91C_EMAC_COL ( ( unsigned int ) 0x1 << 1 ) /* (EMAC) */ +#define AT91C_EMAC_RLES ( ( unsigned int ) 0x1 << 2 ) /* (EMAC) */ +#define AT91C_EMAC_TGO ( ( unsigned int ) 0x1 << 3 ) /* (EMAC) Transmit Go */ +#define AT91C_EMAC_BEX ( ( unsigned int ) 0x1 << 4 ) /* (EMAC) Buffers exhausted mid frame */ +#define AT91C_EMAC_COMP ( ( unsigned int ) 0x1 << 5 ) /* (EMAC) */ +#define AT91C_EMAC_UND ( ( unsigned int ) 0x1 << 6 ) /* (EMAC) */ +/* -------- EMAC_RSR : (EMAC Offset: 0x20) Receive Status Register -------- */ +#define AT91C_EMAC_BNA ( ( unsigned int ) 0x1 << 0 ) /* (EMAC) */ +#define AT91C_EMAC_REC ( ( unsigned int ) 0x1 << 1 ) /* (EMAC) */ +#define AT91C_EMAC_OVR ( ( unsigned int ) 0x1 << 2 ) /* (EMAC) */ +/* -------- EMAC_ISR : (EMAC Offset: 0x24) Interrupt Status Register -------- */ +#define AT91C_EMAC_MFD ( ( unsigned int ) 0x1 << 0 ) /* (EMAC) */ +#define AT91C_EMAC_RCOMP ( ( unsigned int ) 0x1 << 1 ) /* (EMAC) */ +#define AT91C_EMAC_RXUBR ( ( unsigned int ) 0x1 << 2 ) /* (EMAC) */ +#define AT91C_EMAC_TXUBR ( ( unsigned int ) 0x1 << 3 ) /* (EMAC) */ +#define AT91C_EMAC_TUNDR ( ( unsigned int ) 0x1 << 4 ) /* (EMAC) */ +#define AT91C_EMAC_RLEX ( ( unsigned int ) 0x1 << 5 ) /* (EMAC) */ +#define AT91C_EMAC_TXERR ( ( unsigned int ) 0x1 << 6 ) /* (EMAC) */ +#define AT91C_EMAC_TCOMP ( ( unsigned int ) 0x1 << 7 ) /* (EMAC) */ +#define AT91C_EMAC_LINK ( ( unsigned int ) 0x1 << 9 ) /* (EMAC) */ +#define AT91C_EMAC_ROVR ( ( unsigned int ) 0x1 << 10 ) /* (EMAC) */ +#define AT91C_EMAC_HRESP ( ( unsigned int ) 0x1 << 11 ) /* (EMAC) */ +#define AT91C_EMAC_PFRE ( ( unsigned int ) 0x1 << 12 ) /* (EMAC) */ +#define AT91C_EMAC_PTZ ( ( unsigned int ) 0x1 << 13 ) /* (EMAC) */ +/* -------- EMAC_IER : (EMAC Offset: 0x28) Interrupt Enable Register -------- */ +/* -------- EMAC_IDR : (EMAC Offset: 0x2c) Interrupt Disable Register -------- */ +/* -------- EMAC_IMR : (EMAC Offset: 0x30) Interrupt Mask Register -------- */ +/* -------- EMAC_MAN : (EMAC Offset: 0x34) PHY Maintenance Register -------- */ +#define AT91C_EMAC_DATA ( ( unsigned int ) 0xFFFF << 0 ) /* (EMAC) */ +#define AT91C_EMAC_CODE ( ( unsigned int ) 0x3 << 16 ) /* (EMAC) */ +#define AT91C_EMAC_REGA ( ( unsigned int ) 0x1F << 18 ) /* (EMAC) */ +#define AT91C_EMAC_PHYA ( ( unsigned int ) 0x1F << 23 ) /* (EMAC) */ +#define AT91C_EMAC_RW ( ( unsigned int ) 0x3 << 28 ) /* (EMAC) */ +#define AT91C_EMAC_SOF ( ( unsigned int ) 0x3 << 30 ) /* (EMAC) */ +/* -------- EMAC_USRIO : (EMAC Offset: 0xc0) USER Input Output Register -------- */ +#define AT91C_EMAC_RMII ( ( unsigned int ) 0x1 << 0 ) /* (EMAC) Reduce MII */ +/* -------- EMAC_WOL : (EMAC Offset: 0xc4) Wake On LAN Register -------- */ +#define AT91C_EMAC_IP ( ( unsigned int ) 0xFFFF << 0 ) /* (EMAC) ARP request IP address */ +#define AT91C_EMAC_MAG ( ( unsigned int ) 0x1 << 16 ) /* (EMAC) Magic packet event enable */ +#define AT91C_EMAC_ARP ( ( unsigned int ) 0x1 << 17 ) /* (EMAC) ARP request event enable */ +#define AT91C_EMAC_SA1 ( ( unsigned int ) 0x1 << 18 ) /* (EMAC) Specific address register 1 event enable */ +/* -------- EMAC_REV : (EMAC Offset: 0xfc) Revision Register -------- */ +#define AT91C_EMAC_REVREF ( ( unsigned int ) 0xFFFF << 0 ) /* (EMAC) */ +#define AT91C_EMAC_PARTREF ( ( unsigned int ) 0xFFFF << 16 ) /* (EMAC) */ + +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR Analog to Digital Convertor */ +/* ***************************************************************************** */ +typedef struct _AT91S_ADC +{ + AT91_REG ADC_CR; /* ADC Control Register */ + AT91_REG ADC_MR; /* ADC Mode Register */ + AT91_REG Reserved0[ 2 ]; /* */ + AT91_REG ADC_CHER; /* ADC Channel Enable Register */ + AT91_REG ADC_CHDR; /* ADC Channel Disable Register */ + AT91_REG ADC_CHSR; /* ADC Channel Status Register */ + AT91_REG ADC_SR; /* ADC Status Register */ + AT91_REG ADC_LCDR; /* ADC Last Converted Data Register */ + AT91_REG ADC_IER; /* ADC Interrupt Enable Register */ + AT91_REG ADC_IDR; /* ADC Interrupt Disable Register */ + AT91_REG ADC_IMR; /* ADC Interrupt Mask Register */ + AT91_REG ADC_CDR0; /* ADC Channel Data Register 0 */ + AT91_REG ADC_CDR1; /* ADC Channel Data Register 1 */ + AT91_REG ADC_CDR2; /* ADC Channel Data Register 2 */ + AT91_REG ADC_CDR3; /* ADC Channel Data Register 3 */ + AT91_REG ADC_CDR4; /* ADC Channel Data Register 4 */ + AT91_REG ADC_CDR5; /* ADC Channel Data Register 5 */ + AT91_REG ADC_CDR6; /* ADC Channel Data Register 6 */ + AT91_REG ADC_CDR7; /* ADC Channel Data Register 7 */ + AT91_REG Reserved1[ 44 ]; /* */ + AT91_REG ADC_RPR; /* Receive Pointer Register */ + AT91_REG ADC_RCR; /* Receive Counter Register */ + AT91_REG ADC_TPR; /* Transmit Pointer Register */ + AT91_REG ADC_TCR; /* Transmit Counter Register */ + AT91_REG ADC_RNPR; /* Receive Next Pointer Register */ + AT91_REG ADC_RNCR; /* Receive Next Counter Register */ + AT91_REG ADC_TNPR; /* Transmit Next Pointer Register */ + AT91_REG ADC_TNCR; /* Transmit Next Counter Register */ + AT91_REG ADC_PTCR; /* PDC Transfer Control Register */ + AT91_REG ADC_PTSR; /* PDC Transfer Status Register */ +} AT91S_ADC, * AT91PS_ADC; + +/* -------- ADC_CR : (ADC Offset: 0x0) ADC Control Register -------- */ +#define AT91C_ADC_SWRST ( ( unsigned int ) 0x1 << 0 ) /* (ADC) Software Reset */ +#define AT91C_ADC_START ( ( unsigned int ) 0x1 << 1 ) /* (ADC) Start Conversion */ +/* -------- ADC_MR : (ADC Offset: 0x4) ADC Mode Register -------- */ +#define AT91C_ADC_TRGEN ( ( unsigned int ) 0x1 << 0 ) /* (ADC) Trigger Enable */ +#define AT91C_ADC_TRGEN_DIS ( ( unsigned int ) 0x0 ) /* (ADC) Hardware triggers are disabled. Starting a conversion is only possible by software */ +#define AT91C_ADC_TRGEN_EN ( ( unsigned int ) 0x1 ) /* (ADC) Hardware trigger selected by TRGSEL field is enabled. */ +#define AT91C_ADC_TRGSEL ( ( unsigned int ) 0x7 << 1 ) /* (ADC) Trigger Selection */ +#define AT91C_ADC_TRGSEL_TIOA0 ( ( unsigned int ) 0x0 << 1 ) /* (ADC) Selected TRGSEL = TIAO0 */ +#define AT91C_ADC_TRGSEL_TIOA1 ( ( unsigned int ) 0x1 << 1 ) /* (ADC) Selected TRGSEL = TIAO1 */ +#define AT91C_ADC_TRGSEL_TIOA2 ( ( unsigned int ) 0x2 << 1 ) /* (ADC) Selected TRGSEL = TIAO2 */ +#define AT91C_ADC_TRGSEL_TIOA3 ( ( unsigned int ) 0x3 << 1 ) /* (ADC) Selected TRGSEL = TIAO3 */ +#define AT91C_ADC_TRGSEL_TIOA4 ( ( unsigned int ) 0x4 << 1 ) /* (ADC) Selected TRGSEL = TIAO4 */ +#define AT91C_ADC_TRGSEL_TIOA5 ( ( unsigned int ) 0x5 << 1 ) /* (ADC) Selected TRGSEL = TIAO5 */ +#define AT91C_ADC_TRGSEL_EXT ( ( unsigned int ) 0x6 << 1 ) /* (ADC) Selected TRGSEL = External Trigger */ +#define AT91C_ADC_LOWRES ( ( unsigned int ) 0x1 << 4 ) /* (ADC) Resolution. */ +#define AT91C_ADC_LOWRES_10_BIT ( ( unsigned int ) 0x0 << 4 ) /* (ADC) 10-bit resolution */ +#define AT91C_ADC_LOWRES_8_BIT ( ( unsigned int ) 0x1 << 4 ) /* (ADC) 8-bit resolution */ +#define AT91C_ADC_SLEEP ( ( unsigned int ) 0x1 << 5 ) /* (ADC) Sleep Mode */ +#define AT91C_ADC_SLEEP_NORMAL_MODE ( ( unsigned int ) 0x0 << 5 ) /* (ADC) Normal Mode */ +#define AT91C_ADC_SLEEP_MODE ( ( unsigned int ) 0x1 << 5 ) /* (ADC) Sleep Mode */ +#define AT91C_ADC_PRESCAL ( ( unsigned int ) 0x3F << 8 ) /* (ADC) Prescaler rate selection */ +#define AT91C_ADC_STARTUP ( ( unsigned int ) 0x1F << 16 ) /* (ADC) Startup Time */ +#define AT91C_ADC_SHTIM ( ( unsigned int ) 0xF << 24 ) /* (ADC) Sample & Hold Time */ +/* -------- ADC_CHER : (ADC Offset: 0x10) ADC Channel Enable Register -------- */ +#define AT91C_ADC_CH0 ( ( unsigned int ) 0x1 << 0 ) /* (ADC) Channel 0 */ +#define AT91C_ADC_CH1 ( ( unsigned int ) 0x1 << 1 ) /* (ADC) Channel 1 */ +#define AT91C_ADC_CH2 ( ( unsigned int ) 0x1 << 2 ) /* (ADC) Channel 2 */ +#define AT91C_ADC_CH3 ( ( unsigned int ) 0x1 << 3 ) /* (ADC) Channel 3 */ +#define AT91C_ADC_CH4 ( ( unsigned int ) 0x1 << 4 ) /* (ADC) Channel 4 */ +#define AT91C_ADC_CH5 ( ( unsigned int ) 0x1 << 5 ) /* (ADC) Channel 5 */ +#define AT91C_ADC_CH6 ( ( unsigned int ) 0x1 << 6 ) /* (ADC) Channel 6 */ +#define AT91C_ADC_CH7 ( ( unsigned int ) 0x1 << 7 ) /* (ADC) Channel 7 */ +/* -------- ADC_CHDR : (ADC Offset: 0x14) ADC Channel Disable Register -------- */ +/* -------- ADC_CHSR : (ADC Offset: 0x18) ADC Channel Status Register -------- */ +/* -------- ADC_SR : (ADC Offset: 0x1c) ADC Status Register -------- */ +#define AT91C_ADC_EOC0 ( ( unsigned int ) 0x1 << 0 ) /* (ADC) End of Conversion */ +#define AT91C_ADC_EOC1 ( ( unsigned int ) 0x1 << 1 ) /* (ADC) End of Conversion */ +#define AT91C_ADC_EOC2 ( ( unsigned int ) 0x1 << 2 ) /* (ADC) End of Conversion */ +#define AT91C_ADC_EOC3 ( ( unsigned int ) 0x1 << 3 ) /* (ADC) End of Conversion */ +#define AT91C_ADC_EOC4 ( ( unsigned int ) 0x1 << 4 ) /* (ADC) End of Conversion */ +#define AT91C_ADC_EOC5 ( ( unsigned int ) 0x1 << 5 ) /* (ADC) End of Conversion */ +#define AT91C_ADC_EOC6 ( ( unsigned int ) 0x1 << 6 ) /* (ADC) End of Conversion */ +#define AT91C_ADC_EOC7 ( ( unsigned int ) 0x1 << 7 ) /* (ADC) End of Conversion */ +#define AT91C_ADC_OVRE0 ( ( unsigned int ) 0x1 << 8 ) /* (ADC) Overrun Error */ +#define AT91C_ADC_OVRE1 ( ( unsigned int ) 0x1 << 9 ) /* (ADC) Overrun Error */ +#define AT91C_ADC_OVRE2 ( ( unsigned int ) 0x1 << 10 ) /* (ADC) Overrun Error */ +#define AT91C_ADC_OVRE3 ( ( unsigned int ) 0x1 << 11 ) /* (ADC) Overrun Error */ +#define AT91C_ADC_OVRE4 ( ( unsigned int ) 0x1 << 12 ) /* (ADC) Overrun Error */ +#define AT91C_ADC_OVRE5 ( ( unsigned int ) 0x1 << 13 ) /* (ADC) Overrun Error */ +#define AT91C_ADC_OVRE6 ( ( unsigned int ) 0x1 << 14 ) /* (ADC) Overrun Error */ +#define AT91C_ADC_OVRE7 ( ( unsigned int ) 0x1 << 15 ) /* (ADC) Overrun Error */ +#define AT91C_ADC_DRDY ( ( unsigned int ) 0x1 << 16 ) /* (ADC) Data Ready */ +#define AT91C_ADC_GOVRE ( ( unsigned int ) 0x1 << 17 ) /* (ADC) General Overrun */ +#define AT91C_ADC_ENDRX ( ( unsigned int ) 0x1 << 18 ) /* (ADC) End of Receiver Transfer */ +#define AT91C_ADC_RXBUFF ( ( unsigned int ) 0x1 << 19 ) /* (ADC) RXBUFF Interrupt */ +/* -------- ADC_LCDR : (ADC Offset: 0x20) ADC Last Converted Data Register -------- */ +#define AT91C_ADC_LDATA ( ( unsigned int ) 0x3FF << 0 ) /* (ADC) Last Data Converted */ +/* -------- ADC_IER : (ADC Offset: 0x24) ADC Interrupt Enable Register -------- */ +/* -------- ADC_IDR : (ADC Offset: 0x28) ADC Interrupt Disable Register -------- */ +/* -------- ADC_IMR : (ADC Offset: 0x2c) ADC Interrupt Mask Register -------- */ +/* -------- ADC_CDR0 : (ADC Offset: 0x30) ADC Channel Data Register 0 -------- */ +#define AT91C_ADC_DATA ( ( unsigned int ) 0x3FF << 0 ) /* (ADC) Converted Data */ +/* -------- ADC_CDR1 : (ADC Offset: 0x34) ADC Channel Data Register 1 -------- */ +/* -------- ADC_CDR2 : (ADC Offset: 0x38) ADC Channel Data Register 2 -------- */ +/* -------- ADC_CDR3 : (ADC Offset: 0x3c) ADC Channel Data Register 3 -------- */ +/* -------- ADC_CDR4 : (ADC Offset: 0x40) ADC Channel Data Register 4 -------- */ +/* -------- ADC_CDR5 : (ADC Offset: 0x44) ADC Channel Data Register 5 -------- */ +/* -------- ADC_CDR6 : (ADC Offset: 0x48) ADC Channel Data Register 6 -------- */ +/* -------- ADC_CDR7 : (ADC Offset: 0x4c) ADC Channel Data Register 7 -------- */ + +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR Advanced Encryption Standard */ +/* ***************************************************************************** */ +typedef struct _AT91S_AES +{ + AT91_REG AES_CR; /* Control Register */ + AT91_REG AES_MR; /* Mode Register */ + AT91_REG Reserved0[ 2 ]; /* */ + AT91_REG AES_IER; /* Interrupt Enable Register */ + AT91_REG AES_IDR; /* Interrupt Disable Register */ + AT91_REG AES_IMR; /* Interrupt Mask Register */ + AT91_REG AES_ISR; /* Interrupt Status Register */ + AT91_REG AES_KEYWxR[ 4 ]; /* Key Word x Register */ + AT91_REG Reserved1[ 4 ]; /* */ + AT91_REG AES_IDATAxR[ 4 ]; /* Input Data x Register */ + AT91_REG AES_ODATAxR[ 4 ]; /* Output Data x Register */ + AT91_REG AES_IVxR[ 4 ]; /* Initialization Vector x Register */ + AT91_REG Reserved2[ 35 ]; /* */ + AT91_REG AES_VR; /* AES Version Register */ + AT91_REG AES_RPR; /* Receive Pointer Register */ + AT91_REG AES_RCR; /* Receive Counter Register */ + AT91_REG AES_TPR; /* Transmit Pointer Register */ + AT91_REG AES_TCR; /* Transmit Counter Register */ + AT91_REG AES_RNPR; /* Receive Next Pointer Register */ + AT91_REG AES_RNCR; /* Receive Next Counter Register */ + AT91_REG AES_TNPR; /* Transmit Next Pointer Register */ + AT91_REG AES_TNCR; /* Transmit Next Counter Register */ + AT91_REG AES_PTCR; /* PDC Transfer Control Register */ + AT91_REG AES_PTSR; /* PDC Transfer Status Register */ +} AT91S_AES, * AT91PS_AES; + +/* -------- AES_CR : (AES Offset: 0x0) Control Register -------- */ +#define AT91C_AES_START ( ( unsigned int ) 0x1 << 0 ) /* (AES) Starts Processing */ +#define AT91C_AES_SWRST ( ( unsigned int ) 0x1 << 8 ) /* (AES) Software Reset */ +#define AT91C_AES_LOADSEED ( ( unsigned int ) 0x1 << 16 ) /* (AES) Random Number Generator Seed Loading */ +/* -------- AES_MR : (AES Offset: 0x4) Mode Register -------- */ +#define AT91C_AES_CIPHER ( ( unsigned int ) 0x1 << 0 ) /* (AES) Processing Mode */ +#define AT91C_AES_PROCDLY ( ( unsigned int ) 0xF << 4 ) /* (AES) Processing Delay */ +#define AT91C_AES_SMOD ( ( unsigned int ) 0x3 << 8 ) /* (AES) Start Mode */ +#define AT91C_AES_SMOD_MANUAL ( ( unsigned int ) 0x0 << 8 ) /* (AES) Manual Mode: The START bit in register AES_CR must be set to begin encryption or decryption. */ +#define AT91C_AES_SMOD_AUTO ( ( unsigned int ) 0x1 << 8 ) /* (AES) Auto Mode: no action in AES_CR is necessary (cf datasheet). */ +#define AT91C_AES_SMOD_PDC ( ( unsigned int ) 0x2 << 8 ) /* (AES) PDC Mode (cf datasheet). */ +#define AT91C_AES_OPMOD ( ( unsigned int ) 0x7 << 12 ) /* (AES) Operation Mode */ +#define AT91C_AES_OPMOD_ECB ( ( unsigned int ) 0x0 << 12 ) /* (AES) ECB Electronic CodeBook mode. */ +#define AT91C_AES_OPMOD_CBC ( ( unsigned int ) 0x1 << 12 ) /* (AES) CBC Cipher Block Chaining mode. */ +#define AT91C_AES_OPMOD_OFB ( ( unsigned int ) 0x2 << 12 ) /* (AES) OFB Output Feedback mode. */ +#define AT91C_AES_OPMOD_CFB ( ( unsigned int ) 0x3 << 12 ) /* (AES) CFB Cipher Feedback mode. */ +#define AT91C_AES_OPMOD_CTR ( ( unsigned int ) 0x4 << 12 ) /* (AES) CTR Counter mode. */ +#define AT91C_AES_LOD ( ( unsigned int ) 0x1 << 15 ) /* (AES) Last Output Data Mode */ +#define AT91C_AES_CFBS ( ( unsigned int ) 0x7 << 16 ) /* (AES) Cipher Feedback Data Size */ +#define AT91C_AES_CFBS_128_BIT ( ( unsigned int ) 0x0 << 16 ) /* (AES) 128-bit. */ +#define AT91C_AES_CFBS_64_BIT ( ( unsigned int ) 0x1 << 16 ) /* (AES) 64-bit. */ +#define AT91C_AES_CFBS_32_BIT ( ( unsigned int ) 0x2 << 16 ) /* (AES) 32-bit. */ +#define AT91C_AES_CFBS_16_BIT ( ( unsigned int ) 0x3 << 16 ) /* (AES) 16-bit. */ +#define AT91C_AES_CFBS_8_BIT ( ( unsigned int ) 0x4 << 16 ) /* (AES) 8-bit. */ +#define AT91C_AES_CKEY ( ( unsigned int ) 0xF << 20 ) /* (AES) Countermeasure Key */ +#define AT91C_AES_CTYPE ( ( unsigned int ) 0x1F << 24 ) /* (AES) Countermeasure Type */ +#define AT91C_AES_CTYPE_TYPE1_EN ( ( unsigned int ) 0x1 << 24 ) /* (AES) Countermeasure type 1 is enabled. */ +#define AT91C_AES_CTYPE_TYPE2_EN ( ( unsigned int ) 0x2 << 24 ) /* (AES) Countermeasure type 2 is enabled. */ +#define AT91C_AES_CTYPE_TYPE3_EN ( ( unsigned int ) 0x4 << 24 ) /* (AES) Countermeasure type 3 is enabled. */ +#define AT91C_AES_CTYPE_TYPE4_EN ( ( unsigned int ) 0x8 << 24 ) /* (AES) Countermeasure type 4 is enabled. */ +#define AT91C_AES_CTYPE_TYPE5_EN ( ( unsigned int ) 0x10 << 24 ) /* (AES) Countermeasure type 5 is enabled. */ +/* -------- AES_IER : (AES Offset: 0x10) Interrupt Enable Register -------- */ +#define AT91C_AES_DATRDY ( ( unsigned int ) 0x1 << 0 ) /* (AES) DATRDY */ +#define AT91C_AES_ENDRX ( ( unsigned int ) 0x1 << 1 ) /* (AES) PDC Read Buffer End */ +#define AT91C_AES_ENDTX ( ( unsigned int ) 0x1 << 2 ) /* (AES) PDC Write Buffer End */ +#define AT91C_AES_RXBUFF ( ( unsigned int ) 0x1 << 3 ) /* (AES) PDC Read Buffer Full */ +#define AT91C_AES_TXBUFE ( ( unsigned int ) 0x1 << 4 ) /* (AES) PDC Write Buffer Empty */ +#define AT91C_AES_URAD ( ( unsigned int ) 0x1 << 8 ) /* (AES) Unspecified Register Access Detection */ +/* -------- AES_IDR : (AES Offset: 0x14) Interrupt Disable Register -------- */ +/* -------- AES_IMR : (AES Offset: 0x18) Interrupt Mask Register -------- */ +/* -------- AES_ISR : (AES Offset: 0x1c) Interrupt Status Register -------- */ +#define AT91C_AES_URAT ( ( unsigned int ) 0x7 << 12 ) /* (AES) Unspecified Register Access Type Status */ +#define AT91C_AES_URAT_IN_DAT_WRITE_DATPROC ( ( unsigned int ) 0x0 << 12 ) /* (AES) Input data register written during the data processing in PDC mode. */ +#define AT91C_AES_URAT_OUT_DAT_READ_DATPROC ( ( unsigned int ) 0x1 << 12 ) /* (AES) Output data register read during the data processing. */ +#define AT91C_AES_URAT_MODEREG_WRITE_DATPROC ( ( unsigned int ) 0x2 << 12 ) /* (AES) Mode register written during the data processing. */ +#define AT91C_AES_URAT_OUT_DAT_READ_SUBKEY ( ( unsigned int ) 0x3 << 12 ) /* (AES) Output data register read during the sub-keys generation. */ +#define AT91C_AES_URAT_MODEREG_WRITE_SUBKEY ( ( unsigned int ) 0x4 << 12 ) /* (AES) Mode register written during the sub-keys generation. */ +#define AT91C_AES_URAT_WO_REG_READ ( ( unsigned int ) 0x5 << 12 ) /* (AES) Write-only register read access. */ + +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR Triple Data Encryption Standard */ +/* ***************************************************************************** */ +typedef struct _AT91S_TDES +{ + AT91_REG TDES_CR; /* Control Register */ + AT91_REG TDES_MR; /* Mode Register */ + AT91_REG Reserved0[ 2 ]; /* */ + AT91_REG TDES_IER; /* Interrupt Enable Register */ + AT91_REG TDES_IDR; /* Interrupt Disable Register */ + AT91_REG TDES_IMR; /* Interrupt Mask Register */ + AT91_REG TDES_ISR; /* Interrupt Status Register */ + AT91_REG TDES_KEY1WxR[ 2 ]; /* Key 1 Word x Register */ + AT91_REG TDES_KEY2WxR[ 2 ]; /* Key 2 Word x Register */ + AT91_REG TDES_KEY3WxR[ 2 ]; /* Key 3 Word x Register */ + AT91_REG Reserved1[ 2 ]; /* */ + AT91_REG TDES_IDATAxR[ 2 ]; /* Input Data x Register */ + AT91_REG Reserved2[ 2 ]; /* */ + AT91_REG TDES_ODATAxR[ 2 ]; /* Output Data x Register */ + AT91_REG Reserved3[ 2 ]; /* */ + AT91_REG TDES_IVxR[ 2 ]; /* Initialization Vector x Register */ + AT91_REG Reserved4[ 37 ]; /* */ + AT91_REG TDES_VR; /* TDES Version Register */ + AT91_REG TDES_RPR; /* Receive Pointer Register */ + AT91_REG TDES_RCR; /* Receive Counter Register */ + AT91_REG TDES_TPR; /* Transmit Pointer Register */ + AT91_REG TDES_TCR; /* Transmit Counter Register */ + AT91_REG TDES_RNPR; /* Receive Next Pointer Register */ + AT91_REG TDES_RNCR; /* Receive Next Counter Register */ + AT91_REG TDES_TNPR; /* Transmit Next Pointer Register */ + AT91_REG TDES_TNCR; /* Transmit Next Counter Register */ + AT91_REG TDES_PTCR; /* PDC Transfer Control Register */ + AT91_REG TDES_PTSR; /* PDC Transfer Status Register */ +} AT91S_TDES, * AT91PS_TDES; + +/* -------- TDES_CR : (TDES Offset: 0x0) Control Register -------- */ +#define AT91C_TDES_START ( ( unsigned int ) 0x1 << 0 ) /* (TDES) Starts Processing */ +#define AT91C_TDES_SWRST ( ( unsigned int ) 0x1 << 8 ) /* (TDES) Software Reset */ +/* -------- TDES_MR : (TDES Offset: 0x4) Mode Register -------- */ +#define AT91C_TDES_CIPHER ( ( unsigned int ) 0x1 << 0 ) /* (TDES) Processing Mode */ +#define AT91C_TDES_TDESMOD ( ( unsigned int ) 0x1 << 1 ) /* (TDES) Single or Triple DES Mode */ +#define AT91C_TDES_KEYMOD ( ( unsigned int ) 0x1 << 4 ) /* (TDES) Key Mode */ +#define AT91C_TDES_SMOD ( ( unsigned int ) 0x3 << 8 ) /* (TDES) Start Mode */ +#define AT91C_TDES_SMOD_MANUAL ( ( unsigned int ) 0x0 << 8 ) /* (TDES) Manual Mode: The START bit in register TDES_CR must be set to begin encryption or decryption. */ +#define AT91C_TDES_SMOD_AUTO ( ( unsigned int ) 0x1 << 8 ) /* (TDES) Auto Mode: no action in TDES_CR is necessary (cf datasheet). */ +#define AT91C_TDES_SMOD_PDC ( ( unsigned int ) 0x2 << 8 ) /* (TDES) PDC Mode (cf datasheet). */ +#define AT91C_TDES_OPMOD ( ( unsigned int ) 0x3 << 12 ) /* (TDES) Operation Mode */ +#define AT91C_TDES_OPMOD_ECB ( ( unsigned int ) 0x0 << 12 ) /* (TDES) ECB Electronic CodeBook mode. */ +#define AT91C_TDES_OPMOD_CBC ( ( unsigned int ) 0x1 << 12 ) /* (TDES) CBC Cipher Block Chaining mode. */ +#define AT91C_TDES_OPMOD_OFB ( ( unsigned int ) 0x2 << 12 ) /* (TDES) OFB Output Feedback mode. */ +#define AT91C_TDES_OPMOD_CFB ( ( unsigned int ) 0x3 << 12 ) /* (TDES) CFB Cipher Feedback mode. */ +#define AT91C_TDES_LOD ( ( unsigned int ) 0x1 << 15 ) /* (TDES) Last Output Data Mode */ +#define AT91C_TDES_CFBS ( ( unsigned int ) 0x3 << 16 ) /* (TDES) Cipher Feedback Data Size */ +#define AT91C_TDES_CFBS_64_BIT ( ( unsigned int ) 0x0 << 16 ) /* (TDES) 64-bit. */ +#define AT91C_TDES_CFBS_32_BIT ( ( unsigned int ) 0x1 << 16 ) /* (TDES) 32-bit. */ +#define AT91C_TDES_CFBS_16_BIT ( ( unsigned int ) 0x2 << 16 ) /* (TDES) 16-bit. */ +#define AT91C_TDES_CFBS_8_BIT ( ( unsigned int ) 0x3 << 16 ) /* (TDES) 8-bit. */ +/* -------- TDES_IER : (TDES Offset: 0x10) Interrupt Enable Register -------- */ +#define AT91C_TDES_DATRDY ( ( unsigned int ) 0x1 << 0 ) /* (TDES) DATRDY */ +#define AT91C_TDES_ENDRX ( ( unsigned int ) 0x1 << 1 ) /* (TDES) PDC Read Buffer End */ +#define AT91C_TDES_ENDTX ( ( unsigned int ) 0x1 << 2 ) /* (TDES) PDC Write Buffer End */ +#define AT91C_TDES_RXBUFF ( ( unsigned int ) 0x1 << 3 ) /* (TDES) PDC Read Buffer Full */ +#define AT91C_TDES_TXBUFE ( ( unsigned int ) 0x1 << 4 ) /* (TDES) PDC Write Buffer Empty */ +#define AT91C_TDES_URAD ( ( unsigned int ) 0x1 << 8 ) /* (TDES) Unspecified Register Access Detection */ +/* -------- TDES_IDR : (TDES Offset: 0x14) Interrupt Disable Register -------- */ +/* -------- TDES_IMR : (TDES Offset: 0x18) Interrupt Mask Register -------- */ +/* -------- TDES_ISR : (TDES Offset: 0x1c) Interrupt Status Register -------- */ +#define AT91C_TDES_URAT ( ( unsigned int ) 0x3 << 12 ) /* (TDES) Unspecified Register Access Type Status */ +#define AT91C_TDES_URAT_IN_DAT_WRITE_DATPROC ( ( unsigned int ) 0x0 << 12 ) /* (TDES) Input data register written during the data processing in PDC mode. */ +#define AT91C_TDES_URAT_OUT_DAT_READ_DATPROC ( ( unsigned int ) 0x1 << 12 ) /* (TDES) Output data register read during the data processing. */ +#define AT91C_TDES_URAT_MODEREG_WRITE_DATPROC ( ( unsigned int ) 0x2 << 12 ) /* (TDES) Mode register written during the data processing. */ +#define AT91C_TDES_URAT_WO_REG_READ ( ( unsigned int ) 0x3 << 12 ) /* (TDES) Write-only register read access. */ + +/* ***************************************************************************** */ +/* REGISTER ADDRESS DEFINITION FOR AT91SAM7X128 */ +/* ***************************************************************************** */ +/* ========== Register definition for SYS peripheral ========== */ +/* ========== Register definition for AIC peripheral ========== */ +#define AT91C_AIC_IVR ( ( AT91_REG * ) 0xFFFFF100 ) /* (AIC) IRQ Vector Register */ +#define AT91C_AIC_SMR ( ( AT91_REG * ) 0xFFFFF000 ) /* (AIC) Source Mode Register */ +#define AT91C_AIC_FVR ( ( AT91_REG * ) 0xFFFFF104 ) /* (AIC) FIQ Vector Register */ +#define AT91C_AIC_DCR ( ( AT91_REG * ) 0xFFFFF138 ) /* (AIC) Debug Control Register (Protect) */ +#define AT91C_AIC_EOICR ( ( AT91_REG * ) 0xFFFFF130 ) /* (AIC) End of Interrupt Command Register */ +#define AT91C_AIC_SVR ( ( AT91_REG * ) 0xFFFFF080 ) /* (AIC) Source Vector Register */ +#define AT91C_AIC_FFSR ( ( AT91_REG * ) 0xFFFFF148 ) /* (AIC) Fast Forcing Status Register */ +#define AT91C_AIC_ICCR ( ( AT91_REG * ) 0xFFFFF128 ) /* (AIC) Interrupt Clear Command Register */ +#define AT91C_AIC_ISR ( ( AT91_REG * ) 0xFFFFF108 ) /* (AIC) Interrupt Status Register */ +#define AT91C_AIC_IMR ( ( AT91_REG * ) 0xFFFFF110 ) /* (AIC) Interrupt Mask Register */ +#define AT91C_AIC_IPR ( ( AT91_REG * ) 0xFFFFF10C ) /* (AIC) Interrupt Pending Register */ +#define AT91C_AIC_FFER ( ( AT91_REG * ) 0xFFFFF140 ) /* (AIC) Fast Forcing Enable Register */ +#define AT91C_AIC_IECR ( ( AT91_REG * ) 0xFFFFF120 ) /* (AIC) Interrupt Enable Command Register */ +#define AT91C_AIC_ISCR ( ( AT91_REG * ) 0xFFFFF12C ) /* (AIC) Interrupt Set Command Register */ +#define AT91C_AIC_FFDR ( ( AT91_REG * ) 0xFFFFF144 ) /* (AIC) Fast Forcing Disable Register */ +#define AT91C_AIC_CISR ( ( AT91_REG * ) 0xFFFFF114 ) /* (AIC) Core Interrupt Status Register */ +#define AT91C_AIC_IDCR ( ( AT91_REG * ) 0xFFFFF124 ) /* (AIC) Interrupt Disable Command Register */ +#define AT91C_AIC_SPU ( ( AT91_REG * ) 0xFFFFF134 ) /* (AIC) Spurious Vector Register */ +/* ========== Register definition for PDC_DBGU peripheral ========== */ +#define AT91C_DBGU_TCR ( ( AT91_REG * ) 0xFFFFF30C ) /* (PDC_DBGU) Transmit Counter Register */ +#define AT91C_DBGU_RNPR ( ( AT91_REG * ) 0xFFFFF310 ) /* (PDC_DBGU) Receive Next Pointer Register */ +#define AT91C_DBGU_TNPR ( ( AT91_REG * ) 0xFFFFF318 ) /* (PDC_DBGU) Transmit Next Pointer Register */ +#define AT91C_DBGU_TPR ( ( AT91_REG * ) 0xFFFFF308 ) /* (PDC_DBGU) Transmit Pointer Register */ +#define AT91C_DBGU_RPR ( ( AT91_REG * ) 0xFFFFF300 ) /* (PDC_DBGU) Receive Pointer Register */ +#define AT91C_DBGU_RCR ( ( AT91_REG * ) 0xFFFFF304 ) /* (PDC_DBGU) Receive Counter Register */ +#define AT91C_DBGU_RNCR ( ( AT91_REG * ) 0xFFFFF314 ) /* (PDC_DBGU) Receive Next Counter Register */ +#define AT91C_DBGU_PTCR ( ( AT91_REG * ) 0xFFFFF320 ) /* (PDC_DBGU) PDC Transfer Control Register */ +#define AT91C_DBGU_PTSR ( ( AT91_REG * ) 0xFFFFF324 ) /* (PDC_DBGU) PDC Transfer Status Register */ +#define AT91C_DBGU_TNCR ( ( AT91_REG * ) 0xFFFFF31C ) /* (PDC_DBGU) Transmit Next Counter Register */ +/* ========== Register definition for DBGU peripheral ========== */ +#define AT91C_DBGU_EXID ( ( AT91_REG * ) 0xFFFFF244 ) /* (DBGU) Chip ID Extension Register */ +#define AT91C_DBGU_BRGR ( ( AT91_REG * ) 0xFFFFF220 ) /* (DBGU) Baud Rate Generator Register */ +#define AT91C_DBGU_IDR ( ( AT91_REG * ) 0xFFFFF20C ) /* (DBGU) Interrupt Disable Register */ +#define AT91C_DBGU_CSR ( ( AT91_REG * ) 0xFFFFF214 ) /* (DBGU) Channel Status Register */ +#define AT91C_DBGU_CIDR ( ( AT91_REG * ) 0xFFFFF240 ) /* (DBGU) Chip ID Register */ +#define AT91C_DBGU_MR ( ( AT91_REG * ) 0xFFFFF204 ) /* (DBGU) Mode Register */ +#define AT91C_DBGU_IMR ( ( AT91_REG * ) 0xFFFFF210 ) /* (DBGU) Interrupt Mask Register */ +#define AT91C_DBGU_CR ( ( AT91_REG * ) 0xFFFFF200 ) /* (DBGU) Control Register */ +#define AT91C_DBGU_FNTR ( ( AT91_REG * ) 0xFFFFF248 ) /* (DBGU) Force NTRST Register */ +#define AT91C_DBGU_THR ( ( AT91_REG * ) 0xFFFFF21C ) /* (DBGU) Transmitter Holding Register */ +#define AT91C_DBGU_RHR ( ( AT91_REG * ) 0xFFFFF218 ) /* (DBGU) Receiver Holding Register */ +#define AT91C_DBGU_IER ( ( AT91_REG * ) 0xFFFFF208 ) /* (DBGU) Interrupt Enable Register */ +/* ========== Register definition for PIOA peripheral ========== */ +#define AT91C_PIOA_ODR ( ( AT91_REG * ) 0xFFFFF414 ) /* (PIOA) Output Disable Registerr */ +#define AT91C_PIOA_SODR ( ( AT91_REG * ) 0xFFFFF430 ) /* (PIOA) Set Output Data Register */ +#define AT91C_PIOA_ISR ( ( AT91_REG * ) 0xFFFFF44C ) /* (PIOA) Interrupt Status Register */ +#define AT91C_PIOA_ABSR ( ( AT91_REG * ) 0xFFFFF478 ) /* (PIOA) AB Select Status Register */ +#define AT91C_PIOA_IER ( ( AT91_REG * ) 0xFFFFF440 ) /* (PIOA) Interrupt Enable Register */ +#define AT91C_PIOA_PPUDR ( ( AT91_REG * ) 0xFFFFF460 ) /* (PIOA) Pull-up Disable Register */ +#define AT91C_PIOA_IMR ( ( AT91_REG * ) 0xFFFFF448 ) /* (PIOA) Interrupt Mask Register */ +#define AT91C_PIOA_PER ( ( AT91_REG * ) 0xFFFFF400 ) /* (PIOA) PIO Enable Register */ +#define AT91C_PIOA_IFDR ( ( AT91_REG * ) 0xFFFFF424 ) /* (PIOA) Input Filter Disable Register */ +#define AT91C_PIOA_OWDR ( ( AT91_REG * ) 0xFFFFF4A4 ) /* (PIOA) Output Write Disable Register */ +#define AT91C_PIOA_MDSR ( ( AT91_REG * ) 0xFFFFF458 ) /* (PIOA) Multi-driver Status Register */ +#define AT91C_PIOA_IDR ( ( AT91_REG * ) 0xFFFFF444 ) /* (PIOA) Interrupt Disable Register */ +#define AT91C_PIOA_ODSR ( ( AT91_REG * ) 0xFFFFF438 ) /* (PIOA) Output Data Status Register */ +#define AT91C_PIOA_PPUSR ( ( AT91_REG * ) 0xFFFFF468 ) /* (PIOA) Pull-up Status Register */ +#define AT91C_PIOA_OWSR ( ( AT91_REG * ) 0xFFFFF4A8 ) /* (PIOA) Output Write Status Register */ +#define AT91C_PIOA_BSR ( ( AT91_REG * ) 0xFFFFF474 ) /* (PIOA) Select B Register */ +#define AT91C_PIOA_OWER ( ( AT91_REG * ) 0xFFFFF4A0 ) /* (PIOA) Output Write Enable Register */ +#define AT91C_PIOA_IFER ( ( AT91_REG * ) 0xFFFFF420 ) /* (PIOA) Input Filter Enable Register */ +#define AT91C_PIOA_PDSR ( ( AT91_REG * ) 0xFFFFF43C ) /* (PIOA) Pin Data Status Register */ +#define AT91C_PIOA_PPUER ( ( AT91_REG * ) 0xFFFFF464 ) /* (PIOA) Pull-up Enable Register */ +#define AT91C_PIOA_OSR ( ( AT91_REG * ) 0xFFFFF418 ) /* (PIOA) Output Status Register */ +#define AT91C_PIOA_ASR ( ( AT91_REG * ) 0xFFFFF470 ) /* (PIOA) Select A Register */ +#define AT91C_PIOA_MDDR ( ( AT91_REG * ) 0xFFFFF454 ) /* (PIOA) Multi-driver Disable Register */ +#define AT91C_PIOA_CODR ( ( AT91_REG * ) 0xFFFFF434 ) /* (PIOA) Clear Output Data Register */ +#define AT91C_PIOA_MDER ( ( AT91_REG * ) 0xFFFFF450 ) /* (PIOA) Multi-driver Enable Register */ +#define AT91C_PIOA_PDR ( ( AT91_REG * ) 0xFFFFF404 ) /* (PIOA) PIO Disable Register */ +#define AT91C_PIOA_IFSR ( ( AT91_REG * ) 0xFFFFF428 ) /* (PIOA) Input Filter Status Register */ +#define AT91C_PIOA_OER ( ( AT91_REG * ) 0xFFFFF410 ) /* (PIOA) Output Enable Register */ +#define AT91C_PIOA_PSR ( ( AT91_REG * ) 0xFFFFF408 ) /* (PIOA) PIO Status Register */ +/* ========== Register definition for PIOB peripheral ========== */ +#define AT91C_PIOB_OWDR ( ( AT91_REG * ) 0xFFFFF6A4 ) /* (PIOB) Output Write Disable Register */ +#define AT91C_PIOB_MDER ( ( AT91_REG * ) 0xFFFFF650 ) /* (PIOB) Multi-driver Enable Register */ +#define AT91C_PIOB_PPUSR ( ( AT91_REG * ) 0xFFFFF668 ) /* (PIOB) Pull-up Status Register */ +#define AT91C_PIOB_IMR ( ( AT91_REG * ) 0xFFFFF648 ) /* (PIOB) Interrupt Mask Register */ +#define AT91C_PIOB_ASR ( ( AT91_REG * ) 0xFFFFF670 ) /* (PIOB) Select A Register */ +#define AT91C_PIOB_PPUDR ( ( AT91_REG * ) 0xFFFFF660 ) /* (PIOB) Pull-up Disable Register */ +#define AT91C_PIOB_PSR ( ( AT91_REG * ) 0xFFFFF608 ) /* (PIOB) PIO Status Register */ +#define AT91C_PIOB_IER ( ( AT91_REG * ) 0xFFFFF640 ) /* (PIOB) Interrupt Enable Register */ +#define AT91C_PIOB_CODR ( ( AT91_REG * ) 0xFFFFF634 ) /* (PIOB) Clear Output Data Register */ +#define AT91C_PIOB_OWER ( ( AT91_REG * ) 0xFFFFF6A0 ) /* (PIOB) Output Write Enable Register */ +#define AT91C_PIOB_ABSR ( ( AT91_REG * ) 0xFFFFF678 ) /* (PIOB) AB Select Status Register */ +#define AT91C_PIOB_IFDR ( ( AT91_REG * ) 0xFFFFF624 ) /* (PIOB) Input Filter Disable Register */ +#define AT91C_PIOB_PDSR ( ( AT91_REG * ) 0xFFFFF63C ) /* (PIOB) Pin Data Status Register */ +#define AT91C_PIOB_IDR ( ( AT91_REG * ) 0xFFFFF644 ) /* (PIOB) Interrupt Disable Register */ +#define AT91C_PIOB_OWSR ( ( AT91_REG * ) 0xFFFFF6A8 ) /* (PIOB) Output Write Status Register */ +#define AT91C_PIOB_PDR ( ( AT91_REG * ) 0xFFFFF604 ) /* (PIOB) PIO Disable Register */ +#define AT91C_PIOB_ODR ( ( AT91_REG * ) 0xFFFFF614 ) /* (PIOB) Output Disable Registerr */ +#define AT91C_PIOB_IFSR ( ( AT91_REG * ) 0xFFFFF628 ) /* (PIOB) Input Filter Status Register */ +#define AT91C_PIOB_PPUER ( ( AT91_REG * ) 0xFFFFF664 ) /* (PIOB) Pull-up Enable Register */ +#define AT91C_PIOB_SODR ( ( AT91_REG * ) 0xFFFFF630 ) /* (PIOB) Set Output Data Register */ +#define AT91C_PIOB_ISR ( ( AT91_REG * ) 0xFFFFF64C ) /* (PIOB) Interrupt Status Register */ +#define AT91C_PIOB_ODSR ( ( AT91_REG * ) 0xFFFFF638 ) /* (PIOB) Output Data Status Register */ +#define AT91C_PIOB_OSR ( ( AT91_REG * ) 0xFFFFF618 ) /* (PIOB) Output Status Register */ +#define AT91C_PIOB_MDSR ( ( AT91_REG * ) 0xFFFFF658 ) /* (PIOB) Multi-driver Status Register */ +#define AT91C_PIOB_IFER ( ( AT91_REG * ) 0xFFFFF620 ) /* (PIOB) Input Filter Enable Register */ +#define AT91C_PIOB_BSR ( ( AT91_REG * ) 0xFFFFF674 ) /* (PIOB) Select B Register */ +#define AT91C_PIOB_MDDR ( ( AT91_REG * ) 0xFFFFF654 ) /* (PIOB) Multi-driver Disable Register */ +#define AT91C_PIOB_OER ( ( AT91_REG * ) 0xFFFFF610 ) /* (PIOB) Output Enable Register */ +#define AT91C_PIOB_PER ( ( AT91_REG * ) 0xFFFFF600 ) /* (PIOB) PIO Enable Register */ +/* ========== Register definition for CKGR peripheral ========== */ +#define AT91C_CKGR_MOR ( ( AT91_REG * ) 0xFFFFFC20 ) /* (CKGR) Main Oscillator Register */ +#define AT91C_CKGR_PLLR ( ( AT91_REG * ) 0xFFFFFC2C ) /* (CKGR) PLL Register */ +#define AT91C_CKGR_MCFR ( ( AT91_REG * ) 0xFFFFFC24 ) /* (CKGR) Main Clock Frequency Register */ +/* ========== Register definition for PMC peripheral ========== */ +#define AT91C_PMC_IDR ( ( AT91_REG * ) 0xFFFFFC64 ) /* (PMC) Interrupt Disable Register */ +#define AT91C_PMC_MOR ( ( AT91_REG * ) 0xFFFFFC20 ) /* (PMC) Main Oscillator Register */ +#define AT91C_PMC_PLLR ( ( AT91_REG * ) 0xFFFFFC2C ) /* (PMC) PLL Register */ +#define AT91C_PMC_PCER ( ( AT91_REG * ) 0xFFFFFC10 ) /* (PMC) Peripheral Clock Enable Register */ +#define AT91C_PMC_PCKR ( ( AT91_REG * ) 0xFFFFFC40 ) /* (PMC) Programmable Clock Register */ +#define AT91C_PMC_MCKR ( ( AT91_REG * ) 0xFFFFFC30 ) /* (PMC) Master Clock Register */ +#define AT91C_PMC_SCDR ( ( AT91_REG * ) 0xFFFFFC04 ) /* (PMC) System Clock Disable Register */ +#define AT91C_PMC_PCDR ( ( AT91_REG * ) 0xFFFFFC14 ) /* (PMC) Peripheral Clock Disable Register */ +#define AT91C_PMC_SCSR ( ( AT91_REG * ) 0xFFFFFC08 ) /* (PMC) System Clock Status Register */ +#define AT91C_PMC_PCSR ( ( AT91_REG * ) 0xFFFFFC18 ) /* (PMC) Peripheral Clock Status Register */ +#define AT91C_PMC_MCFR ( ( AT91_REG * ) 0xFFFFFC24 ) /* (PMC) Main Clock Frequency Register */ +#define AT91C_PMC_SCER ( ( AT91_REG * ) 0xFFFFFC00 ) /* (PMC) System Clock Enable Register */ +#define AT91C_PMC_IMR ( ( AT91_REG * ) 0xFFFFFC6C ) /* (PMC) Interrupt Mask Register */ +#define AT91C_PMC_IER ( ( AT91_REG * ) 0xFFFFFC60 ) /* (PMC) Interrupt Enable Register */ +#define AT91C_PMC_SR ( ( AT91_REG * ) 0xFFFFFC68 ) /* (PMC) Status Register */ +/* ========== Register definition for RSTC peripheral ========== */ +#define AT91C_RSTC_RCR ( ( AT91_REG * ) 0xFFFFFD00 ) /* (RSTC) Reset Control Register */ +#define AT91C_RSTC_RMR ( ( AT91_REG * ) 0xFFFFFD08 ) /* (RSTC) Reset Mode Register */ +#define AT91C_RSTC_RSR ( ( AT91_REG * ) 0xFFFFFD04 ) /* (RSTC) Reset Status Register */ +/* ========== Register definition for RTTC peripheral ========== */ +#define AT91C_RTTC_RTSR ( ( AT91_REG * ) 0xFFFFFD2C ) /* (RTTC) Real-time Status Register */ +#define AT91C_RTTC_RTMR ( ( AT91_REG * ) 0xFFFFFD20 ) /* (RTTC) Real-time Mode Register */ +#define AT91C_RTTC_RTVR ( ( AT91_REG * ) 0xFFFFFD28 ) /* (RTTC) Real-time Value Register */ +#define AT91C_RTTC_RTAR ( ( AT91_REG * ) 0xFFFFFD24 ) /* (RTTC) Real-time Alarm Register */ +/* ========== Register definition for PITC peripheral ========== */ +#define AT91C_PITC_PIVR ( ( AT91_REG * ) 0xFFFFFD38 ) /* (PITC) Period Interval Value Register */ +#define AT91C_PITC_PISR ( ( AT91_REG * ) 0xFFFFFD34 ) /* (PITC) Period Interval Status Register */ +#define AT91C_PITC_PIIR ( ( AT91_REG * ) 0xFFFFFD3C ) /* (PITC) Period Interval Image Register */ +#define AT91C_PITC_PIMR ( ( AT91_REG * ) 0xFFFFFD30 ) /* (PITC) Period Interval Mode Register */ +/* ========== Register definition for WDTC peripheral ========== */ +#define AT91C_WDTC_WDCR ( ( AT91_REG * ) 0xFFFFFD40 ) /* (WDTC) Watchdog Control Register */ +#define AT91C_WDTC_WDSR ( ( AT91_REG * ) 0xFFFFFD48 ) /* (WDTC) Watchdog Status Register */ +#define AT91C_WDTC_WDMR ( ( AT91_REG * ) 0xFFFFFD44 ) /* (WDTC) Watchdog Mode Register */ +/* ========== Register definition for VREG peripheral ========== */ +#define AT91C_VREG_MR ( ( AT91_REG * ) 0xFFFFFD60 ) /* (VREG) Voltage Regulator Mode Register */ +/* ========== Register definition for MC peripheral ========== */ +#define AT91C_MC_ASR ( ( AT91_REG * ) 0xFFFFFF04 ) /* (MC) MC Abort Status Register */ +#define AT91C_MC_RCR ( ( AT91_REG * ) 0xFFFFFF00 ) /* (MC) MC Remap Control Register */ +#define AT91C_MC_FCR ( ( AT91_REG * ) 0xFFFFFF64 ) /* (MC) MC Flash Command Register */ +#define AT91C_MC_AASR ( ( AT91_REG * ) 0xFFFFFF08 ) /* (MC) MC Abort Address Status Register */ +#define AT91C_MC_FSR ( ( AT91_REG * ) 0xFFFFFF68 ) /* (MC) MC Flash Status Register */ +#define AT91C_MC_FMR ( ( AT91_REG * ) 0xFFFFFF60 ) /* (MC) MC Flash Mode Register */ +/* ========== Register definition for PDC_SPI1 peripheral ========== */ +#define AT91C_SPI1_PTCR ( ( AT91_REG * ) 0xFFFE4120 ) /* (PDC_SPI1) PDC Transfer Control Register */ +#define AT91C_SPI1_RPR ( ( AT91_REG * ) 0xFFFE4100 ) /* (PDC_SPI1) Receive Pointer Register */ +#define AT91C_SPI1_TNCR ( ( AT91_REG * ) 0xFFFE411C ) /* (PDC_SPI1) Transmit Next Counter Register */ +#define AT91C_SPI1_TPR ( ( AT91_REG * ) 0xFFFE4108 ) /* (PDC_SPI1) Transmit Pointer Register */ +#define AT91C_SPI1_TNPR ( ( AT91_REG * ) 0xFFFE4118 ) /* (PDC_SPI1) Transmit Next Pointer Register */ +#define AT91C_SPI1_TCR ( ( AT91_REG * ) 0xFFFE410C ) /* (PDC_SPI1) Transmit Counter Register */ +#define AT91C_SPI1_RCR ( ( AT91_REG * ) 0xFFFE4104 ) /* (PDC_SPI1) Receive Counter Register */ +#define AT91C_SPI1_RNPR ( ( AT91_REG * ) 0xFFFE4110 ) /* (PDC_SPI1) Receive Next Pointer Register */ +#define AT91C_SPI1_RNCR ( ( AT91_REG * ) 0xFFFE4114 ) /* (PDC_SPI1) Receive Next Counter Register */ +#define AT91C_SPI1_PTSR ( ( AT91_REG * ) 0xFFFE4124 ) /* (PDC_SPI1) PDC Transfer Status Register */ +/* ========== Register definition for SPI1 peripheral ========== */ +#define AT91C_SPI1_IMR ( ( AT91_REG * ) 0xFFFE401C ) /* (SPI1) Interrupt Mask Register */ +#define AT91C_SPI1_IER ( ( AT91_REG * ) 0xFFFE4014 ) /* (SPI1) Interrupt Enable Register */ +#define AT91C_SPI1_MR ( ( AT91_REG * ) 0xFFFE4004 ) /* (SPI1) Mode Register */ +#define AT91C_SPI1_RDR ( ( AT91_REG * ) 0xFFFE4008 ) /* (SPI1) Receive Data Register */ +#define AT91C_SPI1_IDR ( ( AT91_REG * ) 0xFFFE4018 ) /* (SPI1) Interrupt Disable Register */ +#define AT91C_SPI1_SR ( ( AT91_REG * ) 0xFFFE4010 ) /* (SPI1) Status Register */ +#define AT91C_SPI1_TDR ( ( AT91_REG * ) 0xFFFE400C ) /* (SPI1) Transmit Data Register */ +#define AT91C_SPI1_CR ( ( AT91_REG * ) 0xFFFE4000 ) /* (SPI1) Control Register */ +#define AT91C_SPI1_CSR ( ( AT91_REG * ) 0xFFFE4030 ) /* (SPI1) Chip Select Register */ +/* ========== Register definition for PDC_SPI0 peripheral ========== */ +#define AT91C_SPI0_PTCR ( ( AT91_REG * ) 0xFFFE0120 ) /* (PDC_SPI0) PDC Transfer Control Register */ +#define AT91C_SPI0_TPR ( ( AT91_REG * ) 0xFFFE0108 ) /* (PDC_SPI0) Transmit Pointer Register */ +#define AT91C_SPI0_TCR ( ( AT91_REG * ) 0xFFFE010C ) /* (PDC_SPI0) Transmit Counter Register */ +#define AT91C_SPI0_RCR ( ( AT91_REG * ) 0xFFFE0104 ) /* (PDC_SPI0) Receive Counter Register */ +#define AT91C_SPI0_PTSR ( ( AT91_REG * ) 0xFFFE0124 ) /* (PDC_SPI0) PDC Transfer Status Register */ +#define AT91C_SPI0_RNPR ( ( AT91_REG * ) 0xFFFE0110 ) /* (PDC_SPI0) Receive Next Pointer Register */ +#define AT91C_SPI0_RPR ( ( AT91_REG * ) 0xFFFE0100 ) /* (PDC_SPI0) Receive Pointer Register */ +#define AT91C_SPI0_TNCR ( ( AT91_REG * ) 0xFFFE011C ) /* (PDC_SPI0) Transmit Next Counter Register */ +#define AT91C_SPI0_RNCR ( ( AT91_REG * ) 0xFFFE0114 ) /* (PDC_SPI0) Receive Next Counter Register */ +#define AT91C_SPI0_TNPR ( ( AT91_REG * ) 0xFFFE0118 ) /* (PDC_SPI0) Transmit Next Pointer Register */ +/* ========== Register definition for SPI0 peripheral ========== */ +#define AT91C_SPI0_IER ( ( AT91_REG * ) 0xFFFE0014 ) /* (SPI0) Interrupt Enable Register */ +#define AT91C_SPI0_SR ( ( AT91_REG * ) 0xFFFE0010 ) /* (SPI0) Status Register */ +#define AT91C_SPI0_IDR ( ( AT91_REG * ) 0xFFFE0018 ) /* (SPI0) Interrupt Disable Register */ +#define AT91C_SPI0_CR ( ( AT91_REG * ) 0xFFFE0000 ) /* (SPI0) Control Register */ +#define AT91C_SPI0_MR ( ( AT91_REG * ) 0xFFFE0004 ) /* (SPI0) Mode Register */ +#define AT91C_SPI0_IMR ( ( AT91_REG * ) 0xFFFE001C ) /* (SPI0) Interrupt Mask Register */ +#define AT91C_SPI0_TDR ( ( AT91_REG * ) 0xFFFE000C ) /* (SPI0) Transmit Data Register */ +#define AT91C_SPI0_RDR ( ( AT91_REG * ) 0xFFFE0008 ) /* (SPI0) Receive Data Register */ +#define AT91C_SPI0_CSR ( ( AT91_REG * ) 0xFFFE0030 ) /* (SPI0) Chip Select Register */ +/* ========== Register definition for PDC_US1 peripheral ========== */ +#define AT91C_US1_RNCR ( ( AT91_REG * ) 0xFFFC4114 ) /* (PDC_US1) Receive Next Counter Register */ +#define AT91C_US1_PTCR ( ( AT91_REG * ) 0xFFFC4120 ) /* (PDC_US1) PDC Transfer Control Register */ +#define AT91C_US1_TCR ( ( AT91_REG * ) 0xFFFC410C ) /* (PDC_US1) Transmit Counter Register */ +#define AT91C_US1_PTSR ( ( AT91_REG * ) 0xFFFC4124 ) /* (PDC_US1) PDC Transfer Status Register */ +#define AT91C_US1_TNPR ( ( AT91_REG * ) 0xFFFC4118 ) /* (PDC_US1) Transmit Next Pointer Register */ +#define AT91C_US1_RCR ( ( AT91_REG * ) 0xFFFC4104 ) /* (PDC_US1) Receive Counter Register */ +#define AT91C_US1_RNPR ( ( AT91_REG * ) 0xFFFC4110 ) /* (PDC_US1) Receive Next Pointer Register */ +#define AT91C_US1_RPR ( ( AT91_REG * ) 0xFFFC4100 ) /* (PDC_US1) Receive Pointer Register */ +#define AT91C_US1_TNCR ( ( AT91_REG * ) 0xFFFC411C ) /* (PDC_US1) Transmit Next Counter Register */ +#define AT91C_US1_TPR ( ( AT91_REG * ) 0xFFFC4108 ) /* (PDC_US1) Transmit Pointer Register */ +/* ========== Register definition for US1 peripheral ========== */ +#define AT91C_US1_IF ( ( AT91_REG * ) 0xFFFC404C ) /* (US1) IRDA_FILTER Register */ +#define AT91C_US1_NER ( ( AT91_REG * ) 0xFFFC4044 ) /* (US1) Nb Errors Register */ +#define AT91C_US1_RTOR ( ( AT91_REG * ) 0xFFFC4024 ) /* (US1) Receiver Time-out Register */ +#define AT91C_US1_CSR ( ( AT91_REG * ) 0xFFFC4014 ) /* (US1) Channel Status Register */ +#define AT91C_US1_IDR ( ( AT91_REG * ) 0xFFFC400C ) /* (US1) Interrupt Disable Register */ +#define AT91C_US1_IER ( ( AT91_REG * ) 0xFFFC4008 ) /* (US1) Interrupt Enable Register */ +#define AT91C_US1_THR ( ( AT91_REG * ) 0xFFFC401C ) /* (US1) Transmitter Holding Register */ +#define AT91C_US1_TTGR ( ( AT91_REG * ) 0xFFFC4028 ) /* (US1) Transmitter Time-guard Register */ +#define AT91C_US1_RHR ( ( AT91_REG * ) 0xFFFC4018 ) /* (US1) Receiver Holding Register */ +#define AT91C_US1_BRGR ( ( AT91_REG * ) 0xFFFC4020 ) /* (US1) Baud Rate Generator Register */ +#define AT91C_US1_IMR ( ( AT91_REG * ) 0xFFFC4010 ) /* (US1) Interrupt Mask Register */ +#define AT91C_US1_FIDI ( ( AT91_REG * ) 0xFFFC4040 ) /* (US1) FI_DI_Ratio Register */ +#define AT91C_US1_CR ( ( AT91_REG * ) 0xFFFC4000 ) /* (US1) Control Register */ +#define AT91C_US1_MR ( ( AT91_REG * ) 0xFFFC4004 ) /* (US1) Mode Register */ +/* ========== Register definition for PDC_US0 peripheral ========== */ +#define AT91C_US0_TNPR ( ( AT91_REG * ) 0xFFFC0118 ) /* (PDC_US0) Transmit Next Pointer Register */ +#define AT91C_US0_RNPR ( ( AT91_REG * ) 0xFFFC0110 ) /* (PDC_US0) Receive Next Pointer Register */ +#define AT91C_US0_TCR ( ( AT91_REG * ) 0xFFFC010C ) /* (PDC_US0) Transmit Counter Register */ +#define AT91C_US0_PTCR ( ( AT91_REG * ) 0xFFFC0120 ) /* (PDC_US0) PDC Transfer Control Register */ +#define AT91C_US0_PTSR ( ( AT91_REG * ) 0xFFFC0124 ) /* (PDC_US0) PDC Transfer Status Register */ +#define AT91C_US0_TNCR ( ( AT91_REG * ) 0xFFFC011C ) /* (PDC_US0) Transmit Next Counter Register */ +#define AT91C_US0_TPR ( ( AT91_REG * ) 0xFFFC0108 ) /* (PDC_US0) Transmit Pointer Register */ +#define AT91C_US0_RCR ( ( AT91_REG * ) 0xFFFC0104 ) /* (PDC_US0) Receive Counter Register */ +#define AT91C_US0_RPR ( ( AT91_REG * ) 0xFFFC0100 ) /* (PDC_US0) Receive Pointer Register */ +#define AT91C_US0_RNCR ( ( AT91_REG * ) 0xFFFC0114 ) /* (PDC_US0) Receive Next Counter Register */ +/* ========== Register definition for US0 peripheral ========== */ +#define AT91C_US0_BRGR ( ( AT91_REG * ) 0xFFFC0020 ) /* (US0) Baud Rate Generator Register */ +#define AT91C_US0_NER ( ( AT91_REG * ) 0xFFFC0044 ) /* (US0) Nb Errors Register */ +#define AT91C_US0_CR ( ( AT91_REG * ) 0xFFFC0000 ) /* (US0) Control Register */ +#define AT91C_US0_IMR ( ( AT91_REG * ) 0xFFFC0010 ) /* (US0) Interrupt Mask Register */ +#define AT91C_US0_FIDI ( ( AT91_REG * ) 0xFFFC0040 ) /* (US0) FI_DI_Ratio Register */ +#define AT91C_US0_TTGR ( ( AT91_REG * ) 0xFFFC0028 ) /* (US0) Transmitter Time-guard Register */ +#define AT91C_US0_MR ( ( AT91_REG * ) 0xFFFC0004 ) /* (US0) Mode Register */ +#define AT91C_US0_RTOR ( ( AT91_REG * ) 0xFFFC0024 ) /* (US0) Receiver Time-out Register */ +#define AT91C_US0_CSR ( ( AT91_REG * ) 0xFFFC0014 ) /* (US0) Channel Status Register */ +#define AT91C_US0_RHR ( ( AT91_REG * ) 0xFFFC0018 ) /* (US0) Receiver Holding Register */ +#define AT91C_US0_IDR ( ( AT91_REG * ) 0xFFFC000C ) /* (US0) Interrupt Disable Register */ +#define AT91C_US0_THR ( ( AT91_REG * ) 0xFFFC001C ) /* (US0) Transmitter Holding Register */ +#define AT91C_US0_IF ( ( AT91_REG * ) 0xFFFC004C ) /* (US0) IRDA_FILTER Register */ +#define AT91C_US0_IER ( ( AT91_REG * ) 0xFFFC0008 ) /* (US0) Interrupt Enable Register */ +/* ========== Register definition for PDC_SSC peripheral ========== */ +#define AT91C_SSC_TNCR ( ( AT91_REG * ) 0xFFFD411C ) /* (PDC_SSC) Transmit Next Counter Register */ +#define AT91C_SSC_RPR ( ( AT91_REG * ) 0xFFFD4100 ) /* (PDC_SSC) Receive Pointer Register */ +#define AT91C_SSC_RNCR ( ( AT91_REG * ) 0xFFFD4114 ) /* (PDC_SSC) Receive Next Counter Register */ +#define AT91C_SSC_TPR ( ( AT91_REG * ) 0xFFFD4108 ) /* (PDC_SSC) Transmit Pointer Register */ +#define AT91C_SSC_PTCR ( ( AT91_REG * ) 0xFFFD4120 ) /* (PDC_SSC) PDC Transfer Control Register */ +#define AT91C_SSC_TCR ( ( AT91_REG * ) 0xFFFD410C ) /* (PDC_SSC) Transmit Counter Register */ +#define AT91C_SSC_RCR ( ( AT91_REG * ) 0xFFFD4104 ) /* (PDC_SSC) Receive Counter Register */ +#define AT91C_SSC_RNPR ( ( AT91_REG * ) 0xFFFD4110 ) /* (PDC_SSC) Receive Next Pointer Register */ +#define AT91C_SSC_TNPR ( ( AT91_REG * ) 0xFFFD4118 ) /* (PDC_SSC) Transmit Next Pointer Register */ +#define AT91C_SSC_PTSR ( ( AT91_REG * ) 0xFFFD4124 ) /* (PDC_SSC) PDC Transfer Status Register */ +/* ========== Register definition for SSC peripheral ========== */ +#define AT91C_SSC_RHR ( ( AT91_REG * ) 0xFFFD4020 ) /* (SSC) Receive Holding Register */ +#define AT91C_SSC_RSHR ( ( AT91_REG * ) 0xFFFD4030 ) /* (SSC) Receive Sync Holding Register */ +#define AT91C_SSC_TFMR ( ( AT91_REG * ) 0xFFFD401C ) /* (SSC) Transmit Frame Mode Register */ +#define AT91C_SSC_IDR ( ( AT91_REG * ) 0xFFFD4048 ) /* (SSC) Interrupt Disable Register */ +#define AT91C_SSC_THR ( ( AT91_REG * ) 0xFFFD4024 ) /* (SSC) Transmit Holding Register */ +#define AT91C_SSC_RCMR ( ( AT91_REG * ) 0xFFFD4010 ) /* (SSC) Receive Clock ModeRegister */ +#define AT91C_SSC_IER ( ( AT91_REG * ) 0xFFFD4044 ) /* (SSC) Interrupt Enable Register */ +#define AT91C_SSC_TSHR ( ( AT91_REG * ) 0xFFFD4034 ) /* (SSC) Transmit Sync Holding Register */ +#define AT91C_SSC_SR ( ( AT91_REG * ) 0xFFFD4040 ) /* (SSC) Status Register */ +#define AT91C_SSC_CMR ( ( AT91_REG * ) 0xFFFD4004 ) /* (SSC) Clock Mode Register */ +#define AT91C_SSC_TCMR ( ( AT91_REG * ) 0xFFFD4018 ) /* (SSC) Transmit Clock Mode Register */ +#define AT91C_SSC_CR ( ( AT91_REG * ) 0xFFFD4000 ) /* (SSC) Control Register */ +#define AT91C_SSC_IMR ( ( AT91_REG * ) 0xFFFD404C ) /* (SSC) Interrupt Mask Register */ +#define AT91C_SSC_RFMR ( ( AT91_REG * ) 0xFFFD4014 ) /* (SSC) Receive Frame Mode Register */ +/* ========== Register definition for TWI peripheral ========== */ +#define AT91C_TWI_IER ( ( AT91_REG * ) 0xFFFB8024 ) /* (TWI) Interrupt Enable Register */ +#define AT91C_TWI_CR ( ( AT91_REG * ) 0xFFFB8000 ) /* (TWI) Control Register */ +#define AT91C_TWI_SR ( ( AT91_REG * ) 0xFFFB8020 ) /* (TWI) Status Register */ +#define AT91C_TWI_IMR ( ( AT91_REG * ) 0xFFFB802C ) /* (TWI) Interrupt Mask Register */ +#define AT91C_TWI_THR ( ( AT91_REG * ) 0xFFFB8034 ) /* (TWI) Transmit Holding Register */ +#define AT91C_TWI_IDR ( ( AT91_REG * ) 0xFFFB8028 ) /* (TWI) Interrupt Disable Register */ +#define AT91C_TWI_IADR ( ( AT91_REG * ) 0xFFFB800C ) /* (TWI) Internal Address Register */ +#define AT91C_TWI_MMR ( ( AT91_REG * ) 0xFFFB8004 ) /* (TWI) Master Mode Register */ +#define AT91C_TWI_CWGR ( ( AT91_REG * ) 0xFFFB8010 ) /* (TWI) Clock Waveform Generator Register */ +#define AT91C_TWI_RHR ( ( AT91_REG * ) 0xFFFB8030 ) /* (TWI) Receive Holding Register */ +/* ========== Register definition for PWMC_CH3 peripheral ========== */ +#define AT91C_PWMC_CH3_CUPDR ( ( AT91_REG * ) 0xFFFCC270 ) /* (PWMC_CH3) Channel Update Register */ +#define AT91C_PWMC_CH3_Reserved ( ( AT91_REG * ) 0xFFFCC274 ) /* (PWMC_CH3) Reserved */ +#define AT91C_PWMC_CH3_CPRDR ( ( AT91_REG * ) 0xFFFCC268 ) /* (PWMC_CH3) Channel Period Register */ +#define AT91C_PWMC_CH3_CDTYR ( ( AT91_REG * ) 0xFFFCC264 ) /* (PWMC_CH3) Channel Duty Cycle Register */ +#define AT91C_PWMC_CH3_CCNTR ( ( AT91_REG * ) 0xFFFCC26C ) /* (PWMC_CH3) Channel Counter Register */ +#define AT91C_PWMC_CH3_CMR ( ( AT91_REG * ) 0xFFFCC260 ) /* (PWMC_CH3) Channel Mode Register */ +/* ========== Register definition for PWMC_CH2 peripheral ========== */ +#define AT91C_PWMC_CH2_Reserved ( ( AT91_REG * ) 0xFFFCC254 ) /* (PWMC_CH2) Reserved */ +#define AT91C_PWMC_CH2_CMR ( ( AT91_REG * ) 0xFFFCC240 ) /* (PWMC_CH2) Channel Mode Register */ +#define AT91C_PWMC_CH2_CCNTR ( ( AT91_REG * ) 0xFFFCC24C ) /* (PWMC_CH2) Channel Counter Register */ +#define AT91C_PWMC_CH2_CPRDR ( ( AT91_REG * ) 0xFFFCC248 ) /* (PWMC_CH2) Channel Period Register */ +#define AT91C_PWMC_CH2_CUPDR ( ( AT91_REG * ) 0xFFFCC250 ) /* (PWMC_CH2) Channel Update Register */ +#define AT91C_PWMC_CH2_CDTYR ( ( AT91_REG * ) 0xFFFCC244 ) /* (PWMC_CH2) Channel Duty Cycle Register */ +/* ========== Register definition for PWMC_CH1 peripheral ========== */ +#define AT91C_PWMC_CH1_Reserved ( ( AT91_REG * ) 0xFFFCC234 ) /* (PWMC_CH1) Reserved */ +#define AT91C_PWMC_CH1_CUPDR ( ( AT91_REG * ) 0xFFFCC230 ) /* (PWMC_CH1) Channel Update Register */ +#define AT91C_PWMC_CH1_CPRDR ( ( AT91_REG * ) 0xFFFCC228 ) /* (PWMC_CH1) Channel Period Register */ +#define AT91C_PWMC_CH1_CCNTR ( ( AT91_REG * ) 0xFFFCC22C ) /* (PWMC_CH1) Channel Counter Register */ +#define AT91C_PWMC_CH1_CDTYR ( ( AT91_REG * ) 0xFFFCC224 ) /* (PWMC_CH1) Channel Duty Cycle Register */ +#define AT91C_PWMC_CH1_CMR ( ( AT91_REG * ) 0xFFFCC220 ) /* (PWMC_CH1) Channel Mode Register */ +/* ========== Register definition for PWMC_CH0 peripheral ========== */ +#define AT91C_PWMC_CH0_Reserved ( ( AT91_REG * ) 0xFFFCC214 ) /* (PWMC_CH0) Reserved */ +#define AT91C_PWMC_CH0_CPRDR ( ( AT91_REG * ) 0xFFFCC208 ) /* (PWMC_CH0) Channel Period Register */ +#define AT91C_PWMC_CH0_CDTYR ( ( AT91_REG * ) 0xFFFCC204 ) /* (PWMC_CH0) Channel Duty Cycle Register */ +#define AT91C_PWMC_CH0_CMR ( ( AT91_REG * ) 0xFFFCC200 ) /* (PWMC_CH0) Channel Mode Register */ +#define AT91C_PWMC_CH0_CUPDR ( ( AT91_REG * ) 0xFFFCC210 ) /* (PWMC_CH0) Channel Update Register */ +#define AT91C_PWMC_CH0_CCNTR ( ( AT91_REG * ) 0xFFFCC20C ) /* (PWMC_CH0) Channel Counter Register */ +/* ========== Register definition for PWMC peripheral ========== */ +#define AT91C_PWMC_IDR ( ( AT91_REG * ) 0xFFFCC014 ) /* (PWMC) PWMC Interrupt Disable Register */ +#define AT91C_PWMC_DIS ( ( AT91_REG * ) 0xFFFCC008 ) /* (PWMC) PWMC Disable Register */ +#define AT91C_PWMC_IER ( ( AT91_REG * ) 0xFFFCC010 ) /* (PWMC) PWMC Interrupt Enable Register */ +#define AT91C_PWMC_VR ( ( AT91_REG * ) 0xFFFCC0FC ) /* (PWMC) PWMC Version Register */ +#define AT91C_PWMC_ISR ( ( AT91_REG * ) 0xFFFCC01C ) /* (PWMC) PWMC Interrupt Status Register */ +#define AT91C_PWMC_SR ( ( AT91_REG * ) 0xFFFCC00C ) /* (PWMC) PWMC Status Register */ +#define AT91C_PWMC_IMR ( ( AT91_REG * ) 0xFFFCC018 ) /* (PWMC) PWMC Interrupt Mask Register */ +#define AT91C_PWMC_MR ( ( AT91_REG * ) 0xFFFCC000 ) /* (PWMC) PWMC Mode Register */ +#define AT91C_PWMC_ENA ( ( AT91_REG * ) 0xFFFCC004 ) /* (PWMC) PWMC Enable Register */ +/* ========== Register definition for UDP peripheral ========== */ +#define AT91C_UDP_IMR ( ( AT91_REG * ) 0xFFFB0018 ) /* (UDP) Interrupt Mask Register */ +#define AT91C_UDP_FADDR ( ( AT91_REG * ) 0xFFFB0008 ) /* (UDP) Function Address Register */ +#define AT91C_UDP_NUM ( ( AT91_REG * ) 0xFFFB0000 ) /* (UDP) Frame Number Register */ +#define AT91C_UDP_FDR ( ( AT91_REG * ) 0xFFFB0050 ) /* (UDP) Endpoint FIFO Data Register */ +#define AT91C_UDP_ISR ( ( AT91_REG * ) 0xFFFB001C ) /* (UDP) Interrupt Status Register */ +#define AT91C_UDP_CSR ( ( AT91_REG * ) 0xFFFB0030 ) /* (UDP) Endpoint Control and Status Register */ +#define AT91C_UDP_IDR ( ( AT91_REG * ) 0xFFFB0014 ) /* (UDP) Interrupt Disable Register */ +#define AT91C_UDP_ICR ( ( AT91_REG * ) 0xFFFB0020 ) /* (UDP) Interrupt Clear Register */ +#define AT91C_UDP_RSTEP ( ( AT91_REG * ) 0xFFFB0028 ) /* (UDP) Reset Endpoint Register */ +#define AT91C_UDP_TXVC ( ( AT91_REG * ) 0xFFFB0074 ) /* (UDP) Transceiver Control Register */ +#define AT91C_UDP_GLBSTATE ( ( AT91_REG * ) 0xFFFB0004 ) /* (UDP) Global State Register */ +#define AT91C_UDP_IER ( ( AT91_REG * ) 0xFFFB0010 ) /* (UDP) Interrupt Enable Register */ +/* ========== Register definition for TC0 peripheral ========== */ +#define AT91C_TC0_SR ( ( AT91_REG * ) 0xFFFA0020 ) /* (TC0) Status Register */ +#define AT91C_TC0_RC ( ( AT91_REG * ) 0xFFFA001C ) /* (TC0) Register C */ +#define AT91C_TC0_RB ( ( AT91_REG * ) 0xFFFA0018 ) /* (TC0) Register B */ +#define AT91C_TC0_CCR ( ( AT91_REG * ) 0xFFFA0000 ) /* (TC0) Channel Control Register */ +#define AT91C_TC0_CMR ( ( AT91_REG * ) 0xFFFA0004 ) /* (TC0) Channel Mode Register (Capture Mode / Waveform Mode) */ +#define AT91C_TC0_IER ( ( AT91_REG * ) 0xFFFA0024 ) /* (TC0) Interrupt Enable Register */ +#define AT91C_TC0_RA ( ( AT91_REG * ) 0xFFFA0014 ) /* (TC0) Register A */ +#define AT91C_TC0_IDR ( ( AT91_REG * ) 0xFFFA0028 ) /* (TC0) Interrupt Disable Register */ +#define AT91C_TC0_CV ( ( AT91_REG * ) 0xFFFA0010 ) /* (TC0) Counter Value */ +#define AT91C_TC0_IMR ( ( AT91_REG * ) 0xFFFA002C ) /* (TC0) Interrupt Mask Register */ +/* ========== Register definition for TC1 peripheral ========== */ +#define AT91C_TC1_RB ( ( AT91_REG * ) 0xFFFA0058 ) /* (TC1) Register B */ +#define AT91C_TC1_CCR ( ( AT91_REG * ) 0xFFFA0040 ) /* (TC1) Channel Control Register */ +#define AT91C_TC1_IER ( ( AT91_REG * ) 0xFFFA0064 ) /* (TC1) Interrupt Enable Register */ +#define AT91C_TC1_IDR ( ( AT91_REG * ) 0xFFFA0068 ) /* (TC1) Interrupt Disable Register */ +#define AT91C_TC1_SR ( ( AT91_REG * ) 0xFFFA0060 ) /* (TC1) Status Register */ +#define AT91C_TC1_CMR ( ( AT91_REG * ) 0xFFFA0044 ) /* (TC1) Channel Mode Register (Capture Mode / Waveform Mode) */ +#define AT91C_TC1_RA ( ( AT91_REG * ) 0xFFFA0054 ) /* (TC1) Register A */ +#define AT91C_TC1_RC ( ( AT91_REG * ) 0xFFFA005C ) /* (TC1) Register C */ +#define AT91C_TC1_IMR ( ( AT91_REG * ) 0xFFFA006C ) /* (TC1) Interrupt Mask Register */ +#define AT91C_TC1_CV ( ( AT91_REG * ) 0xFFFA0050 ) /* (TC1) Counter Value */ +/* ========== Register definition for TC2 peripheral ========== */ +#define AT91C_TC2_CMR ( ( AT91_REG * ) 0xFFFA0084 ) /* (TC2) Channel Mode Register (Capture Mode / Waveform Mode) */ +#define AT91C_TC2_CCR ( ( AT91_REG * ) 0xFFFA0080 ) /* (TC2) Channel Control Register */ +#define AT91C_TC2_CV ( ( AT91_REG * ) 0xFFFA0090 ) /* (TC2) Counter Value */ +#define AT91C_TC2_RA ( ( AT91_REG * ) 0xFFFA0094 ) /* (TC2) Register A */ +#define AT91C_TC2_RB ( ( AT91_REG * ) 0xFFFA0098 ) /* (TC2) Register B */ +#define AT91C_TC2_IDR ( ( AT91_REG * ) 0xFFFA00A8 ) /* (TC2) Interrupt Disable Register */ +#define AT91C_TC2_IMR ( ( AT91_REG * ) 0xFFFA00AC ) /* (TC2) Interrupt Mask Register */ +#define AT91C_TC2_RC ( ( AT91_REG * ) 0xFFFA009C ) /* (TC2) Register C */ +#define AT91C_TC2_IER ( ( AT91_REG * ) 0xFFFA00A4 ) /* (TC2) Interrupt Enable Register */ +#define AT91C_TC2_SR ( ( AT91_REG * ) 0xFFFA00A0 ) /* (TC2) Status Register */ +/* ========== Register definition for TCB peripheral ========== */ +#define AT91C_TCB_BMR ( ( AT91_REG * ) 0xFFFA00C4 ) /* (TCB) TC Block Mode Register */ +#define AT91C_TCB_BCR ( ( AT91_REG * ) 0xFFFA00C0 ) /* (TCB) TC Block Control Register */ +/* ========== Register definition for CAN_MB0 peripheral ========== */ +#define AT91C_CAN_MB0_MDL ( ( AT91_REG * ) 0xFFFD0214 ) /* (CAN_MB0) MailBox Data Low Register */ +#define AT91C_CAN_MB0_MAM ( ( AT91_REG * ) 0xFFFD0204 ) /* (CAN_MB0) MailBox Acceptance Mask Register */ +#define AT91C_CAN_MB0_MCR ( ( AT91_REG * ) 0xFFFD021C ) /* (CAN_MB0) MailBox Control Register */ +#define AT91C_CAN_MB0_MID ( ( AT91_REG * ) 0xFFFD0208 ) /* (CAN_MB0) MailBox ID Register */ +#define AT91C_CAN_MB0_MSR ( ( AT91_REG * ) 0xFFFD0210 ) /* (CAN_MB0) MailBox Status Register */ +#define AT91C_CAN_MB0_MFID ( ( AT91_REG * ) 0xFFFD020C ) /* (CAN_MB0) MailBox Family ID Register */ +#define AT91C_CAN_MB0_MDH ( ( AT91_REG * ) 0xFFFD0218 ) /* (CAN_MB0) MailBox Data High Register */ +#define AT91C_CAN_MB0_MMR ( ( AT91_REG * ) 0xFFFD0200 ) /* (CAN_MB0) MailBox Mode Register */ +/* ========== Register definition for CAN_MB1 peripheral ========== */ +#define AT91C_CAN_MB1_MDL ( ( AT91_REG * ) 0xFFFD0234 ) /* (CAN_MB1) MailBox Data Low Register */ +#define AT91C_CAN_MB1_MID ( ( AT91_REG * ) 0xFFFD0228 ) /* (CAN_MB1) MailBox ID Register */ +#define AT91C_CAN_MB1_MMR ( ( AT91_REG * ) 0xFFFD0220 ) /* (CAN_MB1) MailBox Mode Register */ +#define AT91C_CAN_MB1_MSR ( ( AT91_REG * ) 0xFFFD0230 ) /* (CAN_MB1) MailBox Status Register */ +#define AT91C_CAN_MB1_MAM ( ( AT91_REG * ) 0xFFFD0224 ) /* (CAN_MB1) MailBox Acceptance Mask Register */ +#define AT91C_CAN_MB1_MDH ( ( AT91_REG * ) 0xFFFD0238 ) /* (CAN_MB1) MailBox Data High Register */ +#define AT91C_CAN_MB1_MCR ( ( AT91_REG * ) 0xFFFD023C ) /* (CAN_MB1) MailBox Control Register */ +#define AT91C_CAN_MB1_MFID ( ( AT91_REG * ) 0xFFFD022C ) /* (CAN_MB1) MailBox Family ID Register */ +/* ========== Register definition for CAN_MB2 peripheral ========== */ +#define AT91C_CAN_MB2_MCR ( ( AT91_REG * ) 0xFFFD025C ) /* (CAN_MB2) MailBox Control Register */ +#define AT91C_CAN_MB2_MDH ( ( AT91_REG * ) 0xFFFD0258 ) /* (CAN_MB2) MailBox Data High Register */ +#define AT91C_CAN_MB2_MID ( ( AT91_REG * ) 0xFFFD0248 ) /* (CAN_MB2) MailBox ID Register */ +#define AT91C_CAN_MB2_MDL ( ( AT91_REG * ) 0xFFFD0254 ) /* (CAN_MB2) MailBox Data Low Register */ +#define AT91C_CAN_MB2_MMR ( ( AT91_REG * ) 0xFFFD0240 ) /* (CAN_MB2) MailBox Mode Register */ +#define AT91C_CAN_MB2_MAM ( ( AT91_REG * ) 0xFFFD0244 ) /* (CAN_MB2) MailBox Acceptance Mask Register */ +#define AT91C_CAN_MB2_MFID ( ( AT91_REG * ) 0xFFFD024C ) /* (CAN_MB2) MailBox Family ID Register */ +#define AT91C_CAN_MB2_MSR ( ( AT91_REG * ) 0xFFFD0250 ) /* (CAN_MB2) MailBox Status Register */ +/* ========== Register definition for CAN_MB3 peripheral ========== */ +#define AT91C_CAN_MB3_MFID ( ( AT91_REG * ) 0xFFFD026C ) /* (CAN_MB3) MailBox Family ID Register */ +#define AT91C_CAN_MB3_MAM ( ( AT91_REG * ) 0xFFFD0264 ) /* (CAN_MB3) MailBox Acceptance Mask Register */ +#define AT91C_CAN_MB3_MID ( ( AT91_REG * ) 0xFFFD0268 ) /* (CAN_MB3) MailBox ID Register */ +#define AT91C_CAN_MB3_MCR ( ( AT91_REG * ) 0xFFFD027C ) /* (CAN_MB3) MailBox Control Register */ +#define AT91C_CAN_MB3_MMR ( ( AT91_REG * ) 0xFFFD0260 ) /* (CAN_MB3) MailBox Mode Register */ +#define AT91C_CAN_MB3_MSR ( ( AT91_REG * ) 0xFFFD0270 ) /* (CAN_MB3) MailBox Status Register */ +#define AT91C_CAN_MB3_MDL ( ( AT91_REG * ) 0xFFFD0274 ) /* (CAN_MB3) MailBox Data Low Register */ +#define AT91C_CAN_MB3_MDH ( ( AT91_REG * ) 0xFFFD0278 ) /* (CAN_MB3) MailBox Data High Register */ +/* ========== Register definition for CAN_MB4 peripheral ========== */ +#define AT91C_CAN_MB4_MID ( ( AT91_REG * ) 0xFFFD0288 ) /* (CAN_MB4) MailBox ID Register */ +#define AT91C_CAN_MB4_MMR ( ( AT91_REG * ) 0xFFFD0280 ) /* (CAN_MB4) MailBox Mode Register */ +#define AT91C_CAN_MB4_MDH ( ( AT91_REG * ) 0xFFFD0298 ) /* (CAN_MB4) MailBox Data High Register */ +#define AT91C_CAN_MB4_MFID ( ( AT91_REG * ) 0xFFFD028C ) /* (CAN_MB4) MailBox Family ID Register */ +#define AT91C_CAN_MB4_MSR ( ( AT91_REG * ) 0xFFFD0290 ) /* (CAN_MB4) MailBox Status Register */ +#define AT91C_CAN_MB4_MCR ( ( AT91_REG * ) 0xFFFD029C ) /* (CAN_MB4) MailBox Control Register */ +#define AT91C_CAN_MB4_MDL ( ( AT91_REG * ) 0xFFFD0294 ) /* (CAN_MB4) MailBox Data Low Register */ +#define AT91C_CAN_MB4_MAM ( ( AT91_REG * ) 0xFFFD0284 ) /* (CAN_MB4) MailBox Acceptance Mask Register */ +/* ========== Register definition for CAN_MB5 peripheral ========== */ +#define AT91C_CAN_MB5_MSR ( ( AT91_REG * ) 0xFFFD02B0 ) /* (CAN_MB5) MailBox Status Register */ +#define AT91C_CAN_MB5_MCR ( ( AT91_REG * ) 0xFFFD02BC ) /* (CAN_MB5) MailBox Control Register */ +#define AT91C_CAN_MB5_MFID ( ( AT91_REG * ) 0xFFFD02AC ) /* (CAN_MB5) MailBox Family ID Register */ +#define AT91C_CAN_MB5_MDH ( ( AT91_REG * ) 0xFFFD02B8 ) /* (CAN_MB5) MailBox Data High Register */ +#define AT91C_CAN_MB5_MID ( ( AT91_REG * ) 0xFFFD02A8 ) /* (CAN_MB5) MailBox ID Register */ +#define AT91C_CAN_MB5_MMR ( ( AT91_REG * ) 0xFFFD02A0 ) /* (CAN_MB5) MailBox Mode Register */ +#define AT91C_CAN_MB5_MDL ( ( AT91_REG * ) 0xFFFD02B4 ) /* (CAN_MB5) MailBox Data Low Register */ +#define AT91C_CAN_MB5_MAM ( ( AT91_REG * ) 0xFFFD02A4 ) /* (CAN_MB5) MailBox Acceptance Mask Register */ +/* ========== Register definition for CAN_MB6 peripheral ========== */ +#define AT91C_CAN_MB6_MFID ( ( AT91_REG * ) 0xFFFD02CC ) /* (CAN_MB6) MailBox Family ID Register */ +#define AT91C_CAN_MB6_MID ( ( AT91_REG * ) 0xFFFD02C8 ) /* (CAN_MB6) MailBox ID Register */ +#define AT91C_CAN_MB6_MAM ( ( AT91_REG * ) 0xFFFD02C4 ) /* (CAN_MB6) MailBox Acceptance Mask Register */ +#define AT91C_CAN_MB6_MSR ( ( AT91_REG * ) 0xFFFD02D0 ) /* (CAN_MB6) MailBox Status Register */ +#define AT91C_CAN_MB6_MDL ( ( AT91_REG * ) 0xFFFD02D4 ) /* (CAN_MB6) MailBox Data Low Register */ +#define AT91C_CAN_MB6_MCR ( ( AT91_REG * ) 0xFFFD02DC ) /* (CAN_MB6) MailBox Control Register */ +#define AT91C_CAN_MB6_MDH ( ( AT91_REG * ) 0xFFFD02D8 ) /* (CAN_MB6) MailBox Data High Register */ +#define AT91C_CAN_MB6_MMR ( ( AT91_REG * ) 0xFFFD02C0 ) /* (CAN_MB6) MailBox Mode Register */ +/* ========== Register definition for CAN_MB7 peripheral ========== */ +#define AT91C_CAN_MB7_MCR ( ( AT91_REG * ) 0xFFFD02FC ) /* (CAN_MB7) MailBox Control Register */ +#define AT91C_CAN_MB7_MDH ( ( AT91_REG * ) 0xFFFD02F8 ) /* (CAN_MB7) MailBox Data High Register */ +#define AT91C_CAN_MB7_MFID ( ( AT91_REG * ) 0xFFFD02EC ) /* (CAN_MB7) MailBox Family ID Register */ +#define AT91C_CAN_MB7_MDL ( ( AT91_REG * ) 0xFFFD02F4 ) /* (CAN_MB7) MailBox Data Low Register */ +#define AT91C_CAN_MB7_MID ( ( AT91_REG * ) 0xFFFD02E8 ) /* (CAN_MB7) MailBox ID Register */ +#define AT91C_CAN_MB7_MMR ( ( AT91_REG * ) 0xFFFD02E0 ) /* (CAN_MB7) MailBox Mode Register */ +#define AT91C_CAN_MB7_MAM ( ( AT91_REG * ) 0xFFFD02E4 ) /* (CAN_MB7) MailBox Acceptance Mask Register */ +#define AT91C_CAN_MB7_MSR ( ( AT91_REG * ) 0xFFFD02F0 ) /* (CAN_MB7) MailBox Status Register */ +/* ========== Register definition for CAN peripheral ========== */ +#define AT91C_CAN_TCR ( ( AT91_REG * ) 0xFFFD0024 ) /* (CAN) Transfer Command Register */ +#define AT91C_CAN_IMR ( ( AT91_REG * ) 0xFFFD000C ) /* (CAN) Interrupt Mask Register */ +#define AT91C_CAN_IER ( ( AT91_REG * ) 0xFFFD0004 ) /* (CAN) Interrupt Enable Register */ +#define AT91C_CAN_ECR ( ( AT91_REG * ) 0xFFFD0020 ) /* (CAN) Error Counter Register */ +#define AT91C_CAN_TIMESTP ( ( AT91_REG * ) 0xFFFD001C ) /* (CAN) Time Stamp Register */ +#define AT91C_CAN_MR ( ( AT91_REG * ) 0xFFFD0000 ) /* (CAN) Mode Register */ +#define AT91C_CAN_IDR ( ( AT91_REG * ) 0xFFFD0008 ) /* (CAN) Interrupt Disable Register */ +#define AT91C_CAN_ACR ( ( AT91_REG * ) 0xFFFD0028 ) /* (CAN) Abort Command Register */ +#define AT91C_CAN_TIM ( ( AT91_REG * ) 0xFFFD0018 ) /* (CAN) Timer Register */ +#define AT91C_CAN_SR ( ( AT91_REG * ) 0xFFFD0010 ) /* (CAN) Status Register */ +#define AT91C_CAN_BR ( ( AT91_REG * ) 0xFFFD0014 ) /* (CAN) Baudrate Register */ +#define AT91C_CAN_VR ( ( AT91_REG * ) 0xFFFD00FC ) /* (CAN) Version Register */ +/* ========== Register definition for EMAC peripheral ========== */ +#define AT91C_EMAC_ISR ( ( AT91_REG * ) 0xFFFDC024 ) /* (EMAC) Interrupt Status Register */ +#define AT91C_EMAC_SA4H ( ( AT91_REG * ) 0xFFFDC0B4 ) /* (EMAC) Specific Address 4 Top, Last 2 bytes */ +#define AT91C_EMAC_SA1L ( ( AT91_REG * ) 0xFFFDC098 ) /* (EMAC) Specific Address 1 Bottom, First 4 bytes */ +#define AT91C_EMAC_ELE ( ( AT91_REG * ) 0xFFFDC078 ) /* (EMAC) Excessive Length Errors Register */ +#define AT91C_EMAC_LCOL ( ( AT91_REG * ) 0xFFFDC05C ) /* (EMAC) Late Collision Register */ +#define AT91C_EMAC_RLE ( ( AT91_REG * ) 0xFFFDC088 ) /* (EMAC) Receive Length Field Mismatch Register */ +#define AT91C_EMAC_WOL ( ( AT91_REG * ) 0xFFFDC0C4 ) /* (EMAC) Wake On LAN Register */ +#define AT91C_EMAC_DTF ( ( AT91_REG * ) 0xFFFDC058 ) /* (EMAC) Deferred Transmission Frame Register */ +#define AT91C_EMAC_TUND ( ( AT91_REG * ) 0xFFFDC064 ) /* (EMAC) Transmit Underrun Error Register */ +#define AT91C_EMAC_NCR ( ( AT91_REG * ) 0xFFFDC000 ) /* (EMAC) Network Control Register */ +#define AT91C_EMAC_SA4L ( ( AT91_REG * ) 0xFFFDC0B0 ) /* (EMAC) Specific Address 4 Bottom, First 4 bytes */ +#define AT91C_EMAC_RSR ( ( AT91_REG * ) 0xFFFDC020 ) /* (EMAC) Receive Status Register */ +#define AT91C_EMAC_SA3L ( ( AT91_REG * ) 0xFFFDC0A8 ) /* (EMAC) Specific Address 3 Bottom, First 4 bytes */ +#define AT91C_EMAC_TSR ( ( AT91_REG * ) 0xFFFDC014 ) /* (EMAC) Transmit Status Register */ +#define AT91C_EMAC_IDR ( ( AT91_REG * ) 0xFFFDC02C ) /* (EMAC) Interrupt Disable Register */ +#define AT91C_EMAC_RSE ( ( AT91_REG * ) 0xFFFDC074 ) /* (EMAC) Receive Symbol Errors Register */ +#define AT91C_EMAC_ECOL ( ( AT91_REG * ) 0xFFFDC060 ) /* (EMAC) Excessive Collision Register */ +#define AT91C_EMAC_TID ( ( AT91_REG * ) 0xFFFDC0B8 ) /* (EMAC) Type ID Checking Register */ +#define AT91C_EMAC_HRB ( ( AT91_REG * ) 0xFFFDC090 ) /* (EMAC) Hash Address Bottom[31:0] */ +#define AT91C_EMAC_TBQP ( ( AT91_REG * ) 0xFFFDC01C ) /* (EMAC) Transmit Buffer Queue Pointer */ +#define AT91C_EMAC_USRIO ( ( AT91_REG * ) 0xFFFDC0C0 ) /* (EMAC) USER Input/Output Register */ +#define AT91C_EMAC_PTR ( ( AT91_REG * ) 0xFFFDC038 ) /* (EMAC) Pause Time Register */ +#define AT91C_EMAC_SA2H ( ( AT91_REG * ) 0xFFFDC0A4 ) /* (EMAC) Specific Address 2 Top, Last 2 bytes */ +#define AT91C_EMAC_ROV ( ( AT91_REG * ) 0xFFFDC070 ) /* (EMAC) Receive Overrun Errors Register */ +#define AT91C_EMAC_ALE ( ( AT91_REG * ) 0xFFFDC054 ) /* (EMAC) Alignment Error Register */ +#define AT91C_EMAC_RJA ( ( AT91_REG * ) 0xFFFDC07C ) /* (EMAC) Receive Jabbers Register */ +#define AT91C_EMAC_RBQP ( ( AT91_REG * ) 0xFFFDC018 ) /* (EMAC) Receive Buffer Queue Pointer */ +#define AT91C_EMAC_TPF ( ( AT91_REG * ) 0xFFFDC08C ) /* (EMAC) Transmitted Pause Frames Register */ +#define AT91C_EMAC_NCFGR ( ( AT91_REG * ) 0xFFFDC004 ) /* (EMAC) Network Configuration Register */ +#define AT91C_EMAC_HRT ( ( AT91_REG * ) 0xFFFDC094 ) /* (EMAC) Hash Address Top[63:32] */ +#define AT91C_EMAC_USF ( ( AT91_REG * ) 0xFFFDC080 ) /* (EMAC) Undersize Frames Register */ +#define AT91C_EMAC_FCSE ( ( AT91_REG * ) 0xFFFDC050 ) /* (EMAC) Frame Check Sequence Error Register */ +#define AT91C_EMAC_TPQ ( ( AT91_REG * ) 0xFFFDC0BC ) /* (EMAC) Transmit Pause Quantum Register */ +#define AT91C_EMAC_MAN ( ( AT91_REG * ) 0xFFFDC034 ) /* (EMAC) PHY Maintenance Register */ +#define AT91C_EMAC_FTO ( ( AT91_REG * ) 0xFFFDC040 ) /* (EMAC) Frames Transmitted OK Register */ +#define AT91C_EMAC_REV ( ( AT91_REG * ) 0xFFFDC0FC ) /* (EMAC) Revision Register */ +#define AT91C_EMAC_IMR ( ( AT91_REG * ) 0xFFFDC030 ) /* (EMAC) Interrupt Mask Register */ +#define AT91C_EMAC_SCF ( ( AT91_REG * ) 0xFFFDC044 ) /* (EMAC) Single Collision Frame Register */ +#define AT91C_EMAC_PFR ( ( AT91_REG * ) 0xFFFDC03C ) /* (EMAC) Pause Frames received Register */ +#define AT91C_EMAC_MCF ( ( AT91_REG * ) 0xFFFDC048 ) /* (EMAC) Multiple Collision Frame Register */ +#define AT91C_EMAC_NSR ( ( AT91_REG * ) 0xFFFDC008 ) /* (EMAC) Network Status Register */ +#define AT91C_EMAC_SA2L ( ( AT91_REG * ) 0xFFFDC0A0 ) /* (EMAC) Specific Address 2 Bottom, First 4 bytes */ +#define AT91C_EMAC_FRO ( ( AT91_REG * ) 0xFFFDC04C ) /* (EMAC) Frames Received OK Register */ +#define AT91C_EMAC_IER ( ( AT91_REG * ) 0xFFFDC028 ) /* (EMAC) Interrupt Enable Register */ +#define AT91C_EMAC_SA1H ( ( AT91_REG * ) 0xFFFDC09C ) /* (EMAC) Specific Address 1 Top, Last 2 bytes */ +#define AT91C_EMAC_CSE ( ( AT91_REG * ) 0xFFFDC068 ) /* (EMAC) Carrier Sense Error Register */ +#define AT91C_EMAC_SA3H ( ( AT91_REG * ) 0xFFFDC0AC ) /* (EMAC) Specific Address 3 Top, Last 2 bytes */ +#define AT91C_EMAC_RRE ( ( AT91_REG * ) 0xFFFDC06C ) /* (EMAC) Receive Ressource Error Register */ +#define AT91C_EMAC_STE ( ( AT91_REG * ) 0xFFFDC084 ) /* (EMAC) SQE Test Error Register */ +/* ========== Register definition for PDC_ADC peripheral ========== */ +#define AT91C_ADC_PTSR ( ( AT91_REG * ) 0xFFFD8124 ) /* (PDC_ADC) PDC Transfer Status Register */ +#define AT91C_ADC_PTCR ( ( AT91_REG * ) 0xFFFD8120 ) /* (PDC_ADC) PDC Transfer Control Register */ +#define AT91C_ADC_TNPR ( ( AT91_REG * ) 0xFFFD8118 ) /* (PDC_ADC) Transmit Next Pointer Register */ +#define AT91C_ADC_TNCR ( ( AT91_REG * ) 0xFFFD811C ) /* (PDC_ADC) Transmit Next Counter Register */ +#define AT91C_ADC_RNPR ( ( AT91_REG * ) 0xFFFD8110 ) /* (PDC_ADC) Receive Next Pointer Register */ +#define AT91C_ADC_RNCR ( ( AT91_REG * ) 0xFFFD8114 ) /* (PDC_ADC) Receive Next Counter Register */ +#define AT91C_ADC_RPR ( ( AT91_REG * ) 0xFFFD8100 ) /* (PDC_ADC) Receive Pointer Register */ +#define AT91C_ADC_TCR ( ( AT91_REG * ) 0xFFFD810C ) /* (PDC_ADC) Transmit Counter Register */ +#define AT91C_ADC_TPR ( ( AT91_REG * ) 0xFFFD8108 ) /* (PDC_ADC) Transmit Pointer Register */ +#define AT91C_ADC_RCR ( ( AT91_REG * ) 0xFFFD8104 ) /* (PDC_ADC) Receive Counter Register */ +/* ========== Register definition for ADC peripheral ========== */ +#define AT91C_ADC_CDR2 ( ( AT91_REG * ) 0xFFFD8038 ) /* (ADC) ADC Channel Data Register 2 */ +#define AT91C_ADC_CDR3 ( ( AT91_REG * ) 0xFFFD803C ) /* (ADC) ADC Channel Data Register 3 */ +#define AT91C_ADC_CDR0 ( ( AT91_REG * ) 0xFFFD8030 ) /* (ADC) ADC Channel Data Register 0 */ +#define AT91C_ADC_CDR5 ( ( AT91_REG * ) 0xFFFD8044 ) /* (ADC) ADC Channel Data Register 5 */ +#define AT91C_ADC_CHDR ( ( AT91_REG * ) 0xFFFD8014 ) /* (ADC) ADC Channel Disable Register */ +#define AT91C_ADC_SR ( ( AT91_REG * ) 0xFFFD801C ) /* (ADC) ADC Status Register */ +#define AT91C_ADC_CDR4 ( ( AT91_REG * ) 0xFFFD8040 ) /* (ADC) ADC Channel Data Register 4 */ +#define AT91C_ADC_CDR1 ( ( AT91_REG * ) 0xFFFD8034 ) /* (ADC) ADC Channel Data Register 1 */ +#define AT91C_ADC_LCDR ( ( AT91_REG * ) 0xFFFD8020 ) /* (ADC) ADC Last Converted Data Register */ +#define AT91C_ADC_IDR ( ( AT91_REG * ) 0xFFFD8028 ) /* (ADC) ADC Interrupt Disable Register */ +#define AT91C_ADC_CR ( ( AT91_REG * ) 0xFFFD8000 ) /* (ADC) ADC Control Register */ +#define AT91C_ADC_CDR7 ( ( AT91_REG * ) 0xFFFD804C ) /* (ADC) ADC Channel Data Register 7 */ +#define AT91C_ADC_CDR6 ( ( AT91_REG * ) 0xFFFD8048 ) /* (ADC) ADC Channel Data Register 6 */ +#define AT91C_ADC_IER ( ( AT91_REG * ) 0xFFFD8024 ) /* (ADC) ADC Interrupt Enable Register */ +#define AT91C_ADC_CHER ( ( AT91_REG * ) 0xFFFD8010 ) /* (ADC) ADC Channel Enable Register */ +#define AT91C_ADC_CHSR ( ( AT91_REG * ) 0xFFFD8018 ) /* (ADC) ADC Channel Status Register */ +#define AT91C_ADC_MR ( ( AT91_REG * ) 0xFFFD8004 ) /* (ADC) ADC Mode Register */ +#define AT91C_ADC_IMR ( ( AT91_REG * ) 0xFFFD802C ) /* (ADC) ADC Interrupt Mask Register */ +/* ========== Register definition for PDC_AES peripheral ========== */ +#define AT91C_AES_TPR ( ( AT91_REG * ) 0xFFFA4108 ) /* (PDC_AES) Transmit Pointer Register */ +#define AT91C_AES_PTCR ( ( AT91_REG * ) 0xFFFA4120 ) /* (PDC_AES) PDC Transfer Control Register */ +#define AT91C_AES_RNPR ( ( AT91_REG * ) 0xFFFA4110 ) /* (PDC_AES) Receive Next Pointer Register */ +#define AT91C_AES_TNCR ( ( AT91_REG * ) 0xFFFA411C ) /* (PDC_AES) Transmit Next Counter Register */ +#define AT91C_AES_TCR ( ( AT91_REG * ) 0xFFFA410C ) /* (PDC_AES) Transmit Counter Register */ +#define AT91C_AES_RCR ( ( AT91_REG * ) 0xFFFA4104 ) /* (PDC_AES) Receive Counter Register */ +#define AT91C_AES_RNCR ( ( AT91_REG * ) 0xFFFA4114 ) /* (PDC_AES) Receive Next Counter Register */ +#define AT91C_AES_TNPR ( ( AT91_REG * ) 0xFFFA4118 ) /* (PDC_AES) Transmit Next Pointer Register */ +#define AT91C_AES_RPR ( ( AT91_REG * ) 0xFFFA4100 ) /* (PDC_AES) Receive Pointer Register */ +#define AT91C_AES_PTSR ( ( AT91_REG * ) 0xFFFA4124 ) /* (PDC_AES) PDC Transfer Status Register */ +/* ========== Register definition for AES peripheral ========== */ +#define AT91C_AES_IVxR ( ( AT91_REG * ) 0xFFFA4060 ) /* (AES) Initialization Vector x Register */ +#define AT91C_AES_MR ( ( AT91_REG * ) 0xFFFA4004 ) /* (AES) Mode Register */ +#define AT91C_AES_VR ( ( AT91_REG * ) 0xFFFA40FC ) /* (AES) AES Version Register */ +#define AT91C_AES_ODATAxR ( ( AT91_REG * ) 0xFFFA4050 ) /* (AES) Output Data x Register */ +#define AT91C_AES_IDATAxR ( ( AT91_REG * ) 0xFFFA4040 ) /* (AES) Input Data x Register */ +#define AT91C_AES_CR ( ( AT91_REG * ) 0xFFFA4000 ) /* (AES) Control Register */ +#define AT91C_AES_IDR ( ( AT91_REG * ) 0xFFFA4014 ) /* (AES) Interrupt Disable Register */ +#define AT91C_AES_IMR ( ( AT91_REG * ) 0xFFFA4018 ) /* (AES) Interrupt Mask Register */ +#define AT91C_AES_IER ( ( AT91_REG * ) 0xFFFA4010 ) /* (AES) Interrupt Enable Register */ +#define AT91C_AES_KEYWxR ( ( AT91_REG * ) 0xFFFA4020 ) /* (AES) Key Word x Register */ +#define AT91C_AES_ISR ( ( AT91_REG * ) 0xFFFA401C ) /* (AES) Interrupt Status Register */ +/* ========== Register definition for PDC_TDES peripheral ========== */ +#define AT91C_TDES_RNCR ( ( AT91_REG * ) 0xFFFA8114 ) /* (PDC_TDES) Receive Next Counter Register */ +#define AT91C_TDES_TCR ( ( AT91_REG * ) 0xFFFA810C ) /* (PDC_TDES) Transmit Counter Register */ +#define AT91C_TDES_RCR ( ( AT91_REG * ) 0xFFFA8104 ) /* (PDC_TDES) Receive Counter Register */ +#define AT91C_TDES_TNPR ( ( AT91_REG * ) 0xFFFA8118 ) /* (PDC_TDES) Transmit Next Pointer Register */ +#define AT91C_TDES_RNPR ( ( AT91_REG * ) 0xFFFA8110 ) /* (PDC_TDES) Receive Next Pointer Register */ +#define AT91C_TDES_RPR ( ( AT91_REG * ) 0xFFFA8100 ) /* (PDC_TDES) Receive Pointer Register */ +#define AT91C_TDES_TNCR ( ( AT91_REG * ) 0xFFFA811C ) /* (PDC_TDES) Transmit Next Counter Register */ +#define AT91C_TDES_TPR ( ( AT91_REG * ) 0xFFFA8108 ) /* (PDC_TDES) Transmit Pointer Register */ +#define AT91C_TDES_PTSR ( ( AT91_REG * ) 0xFFFA8124 ) /* (PDC_TDES) PDC Transfer Status Register */ +#define AT91C_TDES_PTCR ( ( AT91_REG * ) 0xFFFA8120 ) /* (PDC_TDES) PDC Transfer Control Register */ +/* ========== Register definition for TDES peripheral ========== */ +#define AT91C_TDES_KEY2WxR ( ( AT91_REG * ) 0xFFFA8028 ) /* (TDES) Key 2 Word x Register */ +#define AT91C_TDES_KEY3WxR ( ( AT91_REG * ) 0xFFFA8030 ) /* (TDES) Key 3 Word x Register */ +#define AT91C_TDES_IDR ( ( AT91_REG * ) 0xFFFA8014 ) /* (TDES) Interrupt Disable Register */ +#define AT91C_TDES_VR ( ( AT91_REG * ) 0xFFFA80FC ) /* (TDES) TDES Version Register */ +#define AT91C_TDES_IVxR ( ( AT91_REG * ) 0xFFFA8060 ) /* (TDES) Initialization Vector x Register */ +#define AT91C_TDES_ODATAxR ( ( AT91_REG * ) 0xFFFA8050 ) /* (TDES) Output Data x Register */ +#define AT91C_TDES_IMR ( ( AT91_REG * ) 0xFFFA8018 ) /* (TDES) Interrupt Mask Register */ +#define AT91C_TDES_MR ( ( AT91_REG * ) 0xFFFA8004 ) /* (TDES) Mode Register */ +#define AT91C_TDES_CR ( ( AT91_REG * ) 0xFFFA8000 ) /* (TDES) Control Register */ +#define AT91C_TDES_IER ( ( AT91_REG * ) 0xFFFA8010 ) /* (TDES) Interrupt Enable Register */ +#define AT91C_TDES_ISR ( ( AT91_REG * ) 0xFFFA801C ) /* (TDES) Interrupt Status Register */ +#define AT91C_TDES_IDATAxR ( ( AT91_REG * ) 0xFFFA8040 ) /* (TDES) Input Data x Register */ +#define AT91C_TDES_KEY1WxR ( ( AT91_REG * ) 0xFFFA8020 ) /* (TDES) Key 1 Word x Register */ + +/* ***************************************************************************** */ +/* PIO DEFINITIONS FOR AT91SAM7X128 */ +/* ***************************************************************************** */ +#define AT91C_PIO_PA0 ( ( unsigned int ) 1 << 0 ) /* Pin Controlled by PA0 */ +#define AT91C_PA0_RXD0 ( ( unsigned int ) AT91C_PIO_PA0 ) /* USART 0 Receive Data */ +#define AT91C_PIO_PA1 ( ( unsigned int ) 1 << 1 ) /* Pin Controlled by PA1 */ +#define AT91C_PA1_TXD0 ( ( unsigned int ) AT91C_PIO_PA1 ) /* USART 0 Transmit Data */ +#define AT91C_PIO_PA10 ( ( unsigned int ) 1 << 10 ) /* Pin Controlled by PA10 */ +#define AT91C_PA10_TWD ( ( unsigned int ) AT91C_PIO_PA10 ) /* TWI Two-wire Serial Data */ +#define AT91C_PIO_PA11 ( ( unsigned int ) 1 << 11 ) /* Pin Controlled by PA11 */ +#define AT91C_PA11_TWCK ( ( unsigned int ) AT91C_PIO_PA11 ) /* TWI Two-wire Serial Clock */ +#define AT91C_PIO_PA12 ( ( unsigned int ) 1 << 12 ) /* Pin Controlled by PA12 */ +#define AT91C_PA12_NPCS00 ( ( unsigned int ) AT91C_PIO_PA12 ) /* SPI 0 Peripheral Chip Select 0 */ +#define AT91C_PIO_PA13 ( ( unsigned int ) 1 << 13 ) /* Pin Controlled by PA13 */ +#define AT91C_PA13_NPCS01 ( ( unsigned int ) AT91C_PIO_PA13 ) /* SPI 0 Peripheral Chip Select 1 */ +#define AT91C_PA13_PCK1 ( ( unsigned int ) AT91C_PIO_PA13 ) /* PMC Programmable Clock Output 1 */ +#define AT91C_PIO_PA14 ( ( unsigned int ) 1 << 14 ) /* Pin Controlled by PA14 */ +#define AT91C_PA14_NPCS02 ( ( unsigned int ) AT91C_PIO_PA14 ) /* SPI 0 Peripheral Chip Select 2 */ +#define AT91C_PA14_IRQ1 ( ( unsigned int ) AT91C_PIO_PA14 ) /* External Interrupt 1 */ +#define AT91C_PIO_PA15 ( ( unsigned int ) 1 << 15 ) /* Pin Controlled by PA15 */ +#define AT91C_PA15_NPCS03 ( ( unsigned int ) AT91C_PIO_PA15 ) /* SPI 0 Peripheral Chip Select 3 */ +#define AT91C_PA15_TCLK2 ( ( unsigned int ) AT91C_PIO_PA15 ) /* Timer Counter 2 external clock input */ +#define AT91C_PIO_PA16 ( ( unsigned int ) 1 << 16 ) /* Pin Controlled by PA16 */ +#define AT91C_PA16_MISO0 ( ( unsigned int ) AT91C_PIO_PA16 ) /* SPI 0 Master In Slave */ +#define AT91C_PIO_PA17 ( ( unsigned int ) 1 << 17 ) /* Pin Controlled by PA17 */ +#define AT91C_PA17_MOSI0 ( ( unsigned int ) AT91C_PIO_PA17 ) /* SPI 0 Master Out Slave */ +#define AT91C_PIO_PA18 ( ( unsigned int ) 1 << 18 ) /* Pin Controlled by PA18 */ +#define AT91C_PA18_SPCK0 ( ( unsigned int ) AT91C_PIO_PA18 ) /* SPI 0 Serial Clock */ +#define AT91C_PIO_PA19 ( ( unsigned int ) 1 << 19 ) /* Pin Controlled by PA19 */ +#define AT91C_PA19_CANRX ( ( unsigned int ) AT91C_PIO_PA19 ) /* CAN Receive */ +#define AT91C_PIO_PA2 ( ( unsigned int ) 1 << 2 ) /* Pin Controlled by PA2 */ +#define AT91C_PA2_SCK0 ( ( unsigned int ) AT91C_PIO_PA2 ) /* USART 0 Serial Clock */ +#define AT91C_PA2_NPCS11 ( ( unsigned int ) AT91C_PIO_PA2 ) /* SPI 1 Peripheral Chip Select 1 */ +#define AT91C_PIO_PA20 ( ( unsigned int ) 1 << 20 ) /* Pin Controlled by PA20 */ +#define AT91C_PA20_CANTX ( ( unsigned int ) AT91C_PIO_PA20 ) /* CAN Transmit */ +#define AT91C_PIO_PA21 ( ( unsigned int ) 1 << 21 ) /* Pin Controlled by PA21 */ +#define AT91C_PA21_TF ( ( unsigned int ) AT91C_PIO_PA21 ) /* SSC Transmit Frame Sync */ +#define AT91C_PA21_NPCS10 ( ( unsigned int ) AT91C_PIO_PA21 ) /* SPI 1 Peripheral Chip Select 0 */ +#define AT91C_PIO_PA22 ( ( unsigned int ) 1 << 22 ) /* Pin Controlled by PA22 */ +#define AT91C_PA22_TK ( ( unsigned int ) AT91C_PIO_PA22 ) /* SSC Transmit Clock */ +#define AT91C_PA22_SPCK1 ( ( unsigned int ) AT91C_PIO_PA22 ) /* SPI 1 Serial Clock */ +#define AT91C_PIO_PA23 ( ( unsigned int ) 1 << 23 ) /* Pin Controlled by PA23 */ +#define AT91C_PA23_TD ( ( unsigned int ) AT91C_PIO_PA23 ) /* SSC Transmit data */ +#define AT91C_PA23_MOSI1 ( ( unsigned int ) AT91C_PIO_PA23 ) /* SPI 1 Master Out Slave */ +#define AT91C_PIO_PA24 ( ( unsigned int ) 1 << 24 ) /* Pin Controlled by PA24 */ +#define AT91C_PA24_RD ( ( unsigned int ) AT91C_PIO_PA24 ) /* SSC Receive Data */ +#define AT91C_PA24_MISO1 ( ( unsigned int ) AT91C_PIO_PA24 ) /* SPI 1 Master In Slave */ +#define AT91C_PIO_PA25 ( ( unsigned int ) 1 << 25 ) /* Pin Controlled by PA25 */ +#define AT91C_PA25_RK ( ( unsigned int ) AT91C_PIO_PA25 ) /* SSC Receive Clock */ +#define AT91C_PA25_NPCS11 ( ( unsigned int ) AT91C_PIO_PA25 ) /* SPI 1 Peripheral Chip Select 1 */ +#define AT91C_PIO_PA26 ( ( unsigned int ) 1 << 26 ) /* Pin Controlled by PA26 */ +#define AT91C_PA26_RF ( ( unsigned int ) AT91C_PIO_PA26 ) /* SSC Receive Frame Sync */ +#define AT91C_PA26_NPCS12 ( ( unsigned int ) AT91C_PIO_PA26 ) /* SPI 1 Peripheral Chip Select 2 */ +#define AT91C_PIO_PA27 ( ( unsigned int ) 1 << 27 ) /* Pin Controlled by PA27 */ +#define AT91C_PA27_DRXD ( ( unsigned int ) AT91C_PIO_PA27 ) /* DBGU Debug Receive Data */ +#define AT91C_PA27_PCK3 ( ( unsigned int ) AT91C_PIO_PA27 ) /* PMC Programmable Clock Output 3 */ +#define AT91C_PIO_PA28 ( ( unsigned int ) 1 << 28 ) /* Pin Controlled by PA28 */ +#define AT91C_PA28_DTXD ( ( unsigned int ) AT91C_PIO_PA28 ) /* DBGU Debug Transmit Data */ +#define AT91C_PIO_PA29 ( ( unsigned int ) 1 << 29 ) /* Pin Controlled by PA29 */ +#define AT91C_PA29_FIQ ( ( unsigned int ) AT91C_PIO_PA29 ) /* AIC Fast Interrupt Input */ +#define AT91C_PA29_NPCS13 ( ( unsigned int ) AT91C_PIO_PA29 ) /* SPI 1 Peripheral Chip Select 3 */ +#define AT91C_PIO_PA3 ( ( unsigned int ) 1 << 3 ) /* Pin Controlled by PA3 */ +#define AT91C_PA3_RTS0 ( ( unsigned int ) AT91C_PIO_PA3 ) /* USART 0 Ready To Send */ +#define AT91C_PA3_NPCS12 ( ( unsigned int ) AT91C_PIO_PA3 ) /* SPI 1 Peripheral Chip Select 2 */ +#define AT91C_PIO_PA30 ( ( unsigned int ) 1 << 30 ) /* Pin Controlled by PA30 */ +#define AT91C_PA30_IRQ0 ( ( unsigned int ) AT91C_PIO_PA30 ) /* External Interrupt 0 */ +#define AT91C_PA30_PCK2 ( ( unsigned int ) AT91C_PIO_PA30 ) /* PMC Programmable Clock Output 2 */ +#define AT91C_PIO_PA4 ( ( unsigned int ) 1 << 4 ) /* Pin Controlled by PA4 */ +#define AT91C_PA4_CTS0 ( ( unsigned int ) AT91C_PIO_PA4 ) /* USART 0 Clear To Send */ +#define AT91C_PA4_NPCS13 ( ( unsigned int ) AT91C_PIO_PA4 ) /* SPI 1 Peripheral Chip Select 3 */ +#define AT91C_PIO_PA5 ( ( unsigned int ) 1 << 5 ) /* Pin Controlled by PA5 */ +#define AT91C_PA5_RXD1 ( ( unsigned int ) AT91C_PIO_PA5 ) /* USART 1 Receive Data */ +#define AT91C_PIO_PA6 ( ( unsigned int ) 1 << 6 ) /* Pin Controlled by PA6 */ +#define AT91C_PA6_TXD1 ( ( unsigned int ) AT91C_PIO_PA6 ) /* USART 1 Transmit Data */ +#define AT91C_PIO_PA7 ( ( unsigned int ) 1 << 7 ) /* Pin Controlled by PA7 */ +#define AT91C_PA7_SCK1 ( ( unsigned int ) AT91C_PIO_PA7 ) /* USART 1 Serial Clock */ +#define AT91C_PA7_NPCS01 ( ( unsigned int ) AT91C_PIO_PA7 ) /* SPI 0 Peripheral Chip Select 1 */ +#define AT91C_PIO_PA8 ( ( unsigned int ) 1 << 8 ) /* Pin Controlled by PA8 */ +#define AT91C_PA8_RTS1 ( ( unsigned int ) AT91C_PIO_PA8 ) /* USART 1 Ready To Send */ +#define AT91C_PA8_NPCS02 ( ( unsigned int ) AT91C_PIO_PA8 ) /* SPI 0 Peripheral Chip Select 2 */ +#define AT91C_PIO_PA9 ( ( unsigned int ) 1 << 9 ) /* Pin Controlled by PA9 */ +#define AT91C_PA9_CTS1 ( ( unsigned int ) AT91C_PIO_PA9 ) /* USART 1 Clear To Send */ +#define AT91C_PA9_NPCS03 ( ( unsigned int ) AT91C_PIO_PA9 ) /* SPI 0 Peripheral Chip Select 3 */ +#define AT91C_PIO_PB0 ( ( unsigned int ) 1 << 0 ) /* Pin Controlled by PB0 */ +#define AT91C_PB0_ETXCK_EREFCK ( ( unsigned int ) AT91C_PIO_PB0 ) /* Ethernet MAC Transmit Clock/Reference Clock */ +#define AT91C_PB0_PCK0 ( ( unsigned int ) AT91C_PIO_PB0 ) /* PMC Programmable Clock Output 0 */ +#define AT91C_PIO_PB1 ( ( unsigned int ) 1 << 1 ) /* Pin Controlled by PB1 */ +#define AT91C_PB1_ETXEN ( ( unsigned int ) AT91C_PIO_PB1 ) /* Ethernet MAC Transmit Enable */ +#define AT91C_PIO_PB10 ( ( unsigned int ) 1 << 10 ) /* Pin Controlled by PB10 */ +#define AT91C_PB10_ETX2 ( ( unsigned int ) AT91C_PIO_PB10 ) /* Ethernet MAC Transmit Data 2 */ +#define AT91C_PB10_NPCS11 ( ( unsigned int ) AT91C_PIO_PB10 ) /* SPI 1 Peripheral Chip Select 1 */ +#define AT91C_PIO_PB11 ( ( unsigned int ) 1 << 11 ) /* Pin Controlled by PB11 */ +#define AT91C_PB11_ETX3 ( ( unsigned int ) AT91C_PIO_PB11 ) /* Ethernet MAC Transmit Data 3 */ +#define AT91C_PB11_NPCS12 ( ( unsigned int ) AT91C_PIO_PB11 ) /* SPI 1 Peripheral Chip Select 2 */ +#define AT91C_PIO_PB12 ( ( unsigned int ) 1 << 12 ) /* Pin Controlled by PB12 */ +#define AT91C_PB12_ETXER ( ( unsigned int ) AT91C_PIO_PB12 ) /* Ethernet MAC Transmit Coding Error */ +#define AT91C_PB12_TCLK0 ( ( unsigned int ) AT91C_PIO_PB12 ) /* Timer Counter 0 external clock input */ +#define AT91C_PIO_PB13 ( ( unsigned int ) 1 << 13 ) /* Pin Controlled by PB13 */ +#define AT91C_PB13_ERX2 ( ( unsigned int ) AT91C_PIO_PB13 ) /* Ethernet MAC Receive Data 2 */ +#define AT91C_PB13_NPCS01 ( ( unsigned int ) AT91C_PIO_PB13 ) /* SPI 0 Peripheral Chip Select 1 */ +#define AT91C_PIO_PB14 ( ( unsigned int ) 1 << 14 ) /* Pin Controlled by PB14 */ +#define AT91C_PB14_ERX3 ( ( unsigned int ) AT91C_PIO_PB14 ) /* Ethernet MAC Receive Data 3 */ +#define AT91C_PB14_NPCS02 ( ( unsigned int ) AT91C_PIO_PB14 ) /* SPI 0 Peripheral Chip Select 2 */ +#define AT91C_PIO_PB15 ( ( unsigned int ) 1 << 15 ) /* Pin Controlled by PB15 */ +#define AT91C_PB15_ERXDV ( ( unsigned int ) AT91C_PIO_PB15 ) /* Ethernet MAC Receive Data Valid */ +#define AT91C_PIO_PB16 ( ( unsigned int ) 1 << 16 ) /* Pin Controlled by PB16 */ +#define AT91C_PB16_ECOL ( ( unsigned int ) AT91C_PIO_PB16 ) /* Ethernet MAC Collision Detected */ +#define AT91C_PB16_NPCS13 ( ( unsigned int ) AT91C_PIO_PB16 ) /* SPI 1 Peripheral Chip Select 3 */ +#define AT91C_PIO_PB17 ( ( unsigned int ) 1 << 17 ) /* Pin Controlled by PB17 */ +#define AT91C_PB17_ERXCK ( ( unsigned int ) AT91C_PIO_PB17 ) /* Ethernet MAC Receive Clock */ +#define AT91C_PB17_NPCS03 ( ( unsigned int ) AT91C_PIO_PB17 ) /* SPI 0 Peripheral Chip Select 3 */ +#define AT91C_PIO_PB18 ( ( unsigned int ) 1 << 18 ) /* Pin Controlled by PB18 */ +#define AT91C_PB18_EF100 ( ( unsigned int ) AT91C_PIO_PB18 ) /* Ethernet MAC Force 100 Mbits/sec */ +#define AT91C_PB18_ADTRG ( ( unsigned int ) AT91C_PIO_PB18 ) /* ADC External Trigger */ +#define AT91C_PIO_PB19 ( ( unsigned int ) 1 << 19 ) /* Pin Controlled by PB19 */ +#define AT91C_PB19_PWM0 ( ( unsigned int ) AT91C_PIO_PB19 ) /* PWM Channel 0 */ +#define AT91C_PB19_TCLK1 ( ( unsigned int ) AT91C_PIO_PB19 ) /* Timer Counter 1 external clock input */ +#define AT91C_PIO_PB2 ( ( unsigned int ) 1 << 2 ) /* Pin Controlled by PB2 */ +#define AT91C_PB2_ETX0 ( ( unsigned int ) AT91C_PIO_PB2 ) /* Ethernet MAC Transmit Data 0 */ +#define AT91C_PIO_PB20 ( ( unsigned int ) 1 << 20 ) /* Pin Controlled by PB20 */ +#define AT91C_PB20_PWM1 ( ( unsigned int ) AT91C_PIO_PB20 ) /* PWM Channel 1 */ +#define AT91C_PB20_PCK0 ( ( unsigned int ) AT91C_PIO_PB20 ) /* PMC Programmable Clock Output 0 */ +#define AT91C_PIO_PB21 ( ( unsigned int ) 1 << 21 ) /* Pin Controlled by PB21 */ +#define AT91C_PB21_PWM2 ( ( unsigned int ) AT91C_PIO_PB21 ) /* PWM Channel 2 */ +#define AT91C_PB21_PCK1 ( ( unsigned int ) AT91C_PIO_PB21 ) /* PMC Programmable Clock Output 1 */ +#define AT91C_PIO_PB22 ( ( unsigned int ) 1 << 22 ) /* Pin Controlled by PB22 */ +#define AT91C_PB22_PWM3 ( ( unsigned int ) AT91C_PIO_PB22 ) /* PWM Channel 3 */ +#define AT91C_PB22_PCK2 ( ( unsigned int ) AT91C_PIO_PB22 ) /* PMC Programmable Clock Output 2 */ +#define AT91C_PIO_PB23 ( ( unsigned int ) 1 << 23 ) /* Pin Controlled by PB23 */ +#define AT91C_PB23_TIOA0 ( ( unsigned int ) AT91C_PIO_PB23 ) /* Timer Counter 0 Multipurpose Timer I/O Pin A */ +#define AT91C_PB23_DCD1 ( ( unsigned int ) AT91C_PIO_PB23 ) /* USART 1 Data Carrier Detect */ +#define AT91C_PIO_PB24 ( ( unsigned int ) 1 << 24 ) /* Pin Controlled by PB24 */ +#define AT91C_PB24_TIOB0 ( ( unsigned int ) AT91C_PIO_PB24 ) /* Timer Counter 0 Multipurpose Timer I/O Pin B */ +#define AT91C_PB24_DSR1 ( ( unsigned int ) AT91C_PIO_PB24 ) /* USART 1 Data Set ready */ +#define AT91C_PIO_PB25 ( ( unsigned int ) 1 << 25 ) /* Pin Controlled by PB25 */ +#define AT91C_PB25_TIOA1 ( ( unsigned int ) AT91C_PIO_PB25 ) /* Timer Counter 1 Multipurpose Timer I/O Pin A */ +#define AT91C_PB25_DTR1 ( ( unsigned int ) AT91C_PIO_PB25 ) /* USART 1 Data Terminal ready */ +#define AT91C_PIO_PB26 ( ( unsigned int ) 1 << 26 ) /* Pin Controlled by PB26 */ +#define AT91C_PB26_TIOB1 ( ( unsigned int ) AT91C_PIO_PB26 ) /* Timer Counter 1 Multipurpose Timer I/O Pin B */ +#define AT91C_PB26_RI1 ( ( unsigned int ) AT91C_PIO_PB26 ) /* USART 1 Ring Indicator */ +#define AT91C_PIO_PB27 ( ( unsigned int ) 1 << 27 ) /* Pin Controlled by PB27 */ +#define AT91C_PB27_TIOA2 ( ( unsigned int ) AT91C_PIO_PB27 ) /* Timer Counter 2 Multipurpose Timer I/O Pin A */ +#define AT91C_PB27_PWM0 ( ( unsigned int ) AT91C_PIO_PB27 ) /* PWM Channel 0 */ +#define AT91C_PIO_PB28 ( ( unsigned int ) 1 << 28 ) /* Pin Controlled by PB28 */ +#define AT91C_PB28_TIOB2 ( ( unsigned int ) AT91C_PIO_PB28 ) /* Timer Counter 2 Multipurpose Timer I/O Pin B */ +#define AT91C_PB28_PWM1 ( ( unsigned int ) AT91C_PIO_PB28 ) /* PWM Channel 1 */ +#define AT91C_PIO_PB29 ( ( unsigned int ) 1 << 29 ) /* Pin Controlled by PB29 */ +#define AT91C_PB29_PCK1 ( ( unsigned int ) AT91C_PIO_PB29 ) /* PMC Programmable Clock Output 1 */ +#define AT91C_PB29_PWM2 ( ( unsigned int ) AT91C_PIO_PB29 ) /* PWM Channel 2 */ +#define AT91C_PIO_PB3 ( ( unsigned int ) 1 << 3 ) /* Pin Controlled by PB3 */ +#define AT91C_PB3_ETX1 ( ( unsigned int ) AT91C_PIO_PB3 ) /* Ethernet MAC Transmit Data 1 */ +#define AT91C_PIO_PB30 ( ( unsigned int ) 1 << 30 ) /* Pin Controlled by PB30 */ +#define AT91C_PB30_PCK2 ( ( unsigned int ) AT91C_PIO_PB30 ) /* PMC Programmable Clock Output 2 */ +#define AT91C_PB30_PWM3 ( ( unsigned int ) AT91C_PIO_PB30 ) /* PWM Channel 3 */ +#define AT91C_PIO_PB4 ( ( unsigned int ) 1 << 4 ) /* Pin Controlled by PB4 */ +#define AT91C_PB4_ECRS_ECRSDV ( ( unsigned int ) AT91C_PIO_PB4 ) /* Ethernet MAC Carrier Sense/Carrier Sense and Data Valid */ +#define AT91C_PIO_PB5 ( ( unsigned int ) 1 << 5 ) /* Pin Controlled by PB5 */ +#define AT91C_PB5_ERX0 ( ( unsigned int ) AT91C_PIO_PB5 ) /* Ethernet MAC Receive Data 0 */ +#define AT91C_PIO_PB6 ( ( unsigned int ) 1 << 6 ) /* Pin Controlled by PB6 */ +#define AT91C_PB6_ERX1 ( ( unsigned int ) AT91C_PIO_PB6 ) /* Ethernet MAC Receive Data 1 */ +#define AT91C_PIO_PB7 ( ( unsigned int ) 1 << 7 ) /* Pin Controlled by PB7 */ +#define AT91C_PB7_ERXER ( ( unsigned int ) AT91C_PIO_PB7 ) /* Ethernet MAC Receive Error */ +#define AT91C_PIO_PB8 ( ( unsigned int ) 1 << 8 ) /* Pin Controlled by PB8 */ +#define AT91C_PB8_EMDC ( ( unsigned int ) AT91C_PIO_PB8 ) /* Ethernet MAC Management Data Clock */ +#define AT91C_PIO_PB9 ( ( unsigned int ) 1 << 9 ) /* Pin Controlled by PB9 */ +#define AT91C_PB9_EMDIO ( ( unsigned int ) AT91C_PIO_PB9 ) /* Ethernet MAC Management Data Input/Output */ + +/* ***************************************************************************** */ +/* PERIPHERAL ID DEFINITIONS FOR AT91SAM7X128 */ +/* ***************************************************************************** */ +#define AT91C_ID_FIQ ( ( unsigned int ) 0 ) /* Advanced Interrupt Controller (FIQ) */ +#define AT91C_ID_SYS ( ( unsigned int ) 1 ) /* System Peripheral */ +#define AT91C_ID_PIOA ( ( unsigned int ) 2 ) /* Parallel IO Controller A */ +#define AT91C_ID_PIOB ( ( unsigned int ) 3 ) /* Parallel IO Controller B */ +#define AT91C_ID_SPI0 ( ( unsigned int ) 4 ) /* Serial Peripheral Interface 0 */ +#define AT91C_ID_SPI1 ( ( unsigned int ) 5 ) /* Serial Peripheral Interface 1 */ +#define AT91C_ID_US0 ( ( unsigned int ) 6 ) /* USART 0 */ +#define AT91C_ID_US1 ( ( unsigned int ) 7 ) /* USART 1 */ +#define AT91C_ID_SSC ( ( unsigned int ) 8 ) /* Serial Synchronous Controller */ +#define AT91C_ID_TWI ( ( unsigned int ) 9 ) /* Two-Wire Interface */ +#define AT91C_ID_PWMC ( ( unsigned int ) 10 ) /* PWM Controller */ +#define AT91C_ID_UDP ( ( unsigned int ) 11 ) /* USB Device Port */ +#define AT91C_ID_TC0 ( ( unsigned int ) 12 ) /* Timer Counter 0 */ +#define AT91C_ID_TC1 ( ( unsigned int ) 13 ) /* Timer Counter 1 */ +#define AT91C_ID_TC2 ( ( unsigned int ) 14 ) /* Timer Counter 2 */ +#define AT91C_ID_CAN ( ( unsigned int ) 15 ) /* Control Area Network Controller */ +#define AT91C_ID_EMAC ( ( unsigned int ) 16 ) /* Ethernet MAC */ +#define AT91C_ID_ADC ( ( unsigned int ) 17 ) /* Analog-to-Digital Converter */ +#define AT91C_ID_AES ( ( unsigned int ) 18 ) /* Advanced Encryption Standard 128-bit */ +#define AT91C_ID_TDES ( ( unsigned int ) 19 ) /* Triple Data Encryption Standard */ +#define AT91C_ID_20_Reserved ( ( unsigned int ) 20 ) /* Reserved */ +#define AT91C_ID_21_Reserved ( ( unsigned int ) 21 ) /* Reserved */ +#define AT91C_ID_22_Reserved ( ( unsigned int ) 22 ) /* Reserved */ +#define AT91C_ID_23_Reserved ( ( unsigned int ) 23 ) /* Reserved */ +#define AT91C_ID_24_Reserved ( ( unsigned int ) 24 ) /* Reserved */ +#define AT91C_ID_25_Reserved ( ( unsigned int ) 25 ) /* Reserved */ +#define AT91C_ID_26_Reserved ( ( unsigned int ) 26 ) /* Reserved */ +#define AT91C_ID_27_Reserved ( ( unsigned int ) 27 ) /* Reserved */ +#define AT91C_ID_28_Reserved ( ( unsigned int ) 28 ) /* Reserved */ +#define AT91C_ID_29_Reserved ( ( unsigned int ) 29 ) /* Reserved */ +#define AT91C_ID_IRQ0 ( ( unsigned int ) 30 ) /* Advanced Interrupt Controller (IRQ0) */ +#define AT91C_ID_IRQ1 ( ( unsigned int ) 31 ) /* Advanced Interrupt Controller (IRQ1) */ + +/* ***************************************************************************** */ +/* BASE ADDRESS DEFINITIONS FOR AT91SAM7X128 */ +/* ***************************************************************************** */ +#define AT91C_BASE_SYS ( ( AT91PS_SYS ) 0xFFFFF000 ) /* (SYS) Base Address */ +#define AT91C_BASE_AIC ( ( AT91PS_AIC ) 0xFFFFF000 ) /* (AIC) Base Address */ +#define AT91C_BASE_PDC_DBGU ( ( AT91PS_PDC ) 0xFFFFF300 ) /* (PDC_DBGU) Base Address */ +#define AT91C_BASE_DBGU ( ( AT91PS_DBGU ) 0xFFFFF200 ) /* (DBGU) Base Address */ +#define AT91C_BASE_PIOA ( ( AT91PS_PIO ) 0xFFFFF400 ) /* (PIOA) Base Address */ +#define AT91C_BASE_PIOB ( ( AT91PS_PIO ) 0xFFFFF600 ) /* (PIOB) Base Address */ +#define AT91C_BASE_CKGR ( ( AT91PS_CKGR ) 0xFFFFFC20 ) /* (CKGR) Base Address */ +#define AT91C_BASE_PMC ( ( AT91PS_PMC ) 0xFFFFFC00 ) /* (PMC) Base Address */ +#define AT91C_BASE_RSTC ( ( AT91PS_RSTC ) 0xFFFFFD00 ) /* (RSTC) Base Address */ +#define AT91C_BASE_RTTC ( ( AT91PS_RTTC ) 0xFFFFFD20 ) /* (RTTC) Base Address */ +#define AT91C_BASE_PITC ( ( AT91PS_PITC ) 0xFFFFFD30 ) /* (PITC) Base Address */ +#define AT91C_BASE_WDTC ( ( AT91PS_WDTC ) 0xFFFFFD40 ) /* (WDTC) Base Address */ +#define AT91C_BASE_VREG ( ( AT91PS_VREG ) 0xFFFFFD60 ) /* (VREG) Base Address */ +#define AT91C_BASE_MC ( ( AT91PS_MC ) 0xFFFFFF00 ) /* (MC) Base Address */ +#define AT91C_BASE_PDC_SPI1 ( ( AT91PS_PDC ) 0xFFFE4100 ) /* (PDC_SPI1) Base Address */ +#define AT91C_BASE_SPI1 ( ( AT91PS_SPI ) 0xFFFE4000 ) /* (SPI1) Base Address */ +#define AT91C_BASE_PDC_SPI0 ( ( AT91PS_PDC ) 0xFFFE0100 ) /* (PDC_SPI0) Base Address */ +#define AT91C_BASE_SPI0 ( ( AT91PS_SPI ) 0xFFFE0000 ) /* (SPI0) Base Address */ +#define AT91C_BASE_PDC_US1 ( ( AT91PS_PDC ) 0xFFFC4100 ) /* (PDC_US1) Base Address */ +#define AT91C_BASE_US1 ( ( AT91PS_USART ) 0xFFFC4000 ) /* (US1) Base Address */ +#define AT91C_BASE_PDC_US0 ( ( AT91PS_PDC ) 0xFFFC0100 ) /* (PDC_US0) Base Address */ +#define AT91C_BASE_US0 ( ( AT91PS_USART ) 0xFFFC0000 ) /* (US0) Base Address */ +#define AT91C_BASE_PDC_SSC ( ( AT91PS_PDC ) 0xFFFD4100 ) /* (PDC_SSC) Base Address */ +#define AT91C_BASE_SSC ( ( AT91PS_SSC ) 0xFFFD4000 ) /* (SSC) Base Address */ +#define AT91C_BASE_TWI ( ( AT91PS_TWI ) 0xFFFB8000 ) /* (TWI) Base Address */ +#define AT91C_BASE_PWMC_CH3 ( ( AT91PS_PWMC_CH ) 0xFFFCC260 ) /* (PWMC_CH3) Base Address */ +#define AT91C_BASE_PWMC_CH2 ( ( AT91PS_PWMC_CH ) 0xFFFCC240 ) /* (PWMC_CH2) Base Address */ +#define AT91C_BASE_PWMC_CH1 ( ( AT91PS_PWMC_CH ) 0xFFFCC220 ) /* (PWMC_CH1) Base Address */ +#define AT91C_BASE_PWMC_CH0 ( ( AT91PS_PWMC_CH ) 0xFFFCC200 ) /* (PWMC_CH0) Base Address */ +#define AT91C_BASE_PWMC ( ( AT91PS_PWMC ) 0xFFFCC000 ) /* (PWMC) Base Address */ +#define AT91C_BASE_UDP ( ( AT91PS_UDP ) 0xFFFB0000 ) /* (UDP) Base Address */ +#define AT91C_BASE_TC0 ( ( AT91PS_TC ) 0xFFFA0000 ) /* (TC0) Base Address */ +#define AT91C_BASE_TC1 ( ( AT91PS_TC ) 0xFFFA0040 ) /* (TC1) Base Address */ +#define AT91C_BASE_TC2 ( ( AT91PS_TC ) 0xFFFA0080 ) /* (TC2) Base Address */ +#define AT91C_BASE_TCB ( ( AT91PS_TCB ) 0xFFFA0000 ) /* (TCB) Base Address */ +#define AT91C_BASE_CAN_MB0 ( ( AT91PS_CAN_MB ) 0xFFFD0200 ) /* (CAN_MB0) Base Address */ +#define AT91C_BASE_CAN_MB1 ( ( AT91PS_CAN_MB ) 0xFFFD0220 ) /* (CAN_MB1) Base Address */ +#define AT91C_BASE_CAN_MB2 ( ( AT91PS_CAN_MB ) 0xFFFD0240 ) /* (CAN_MB2) Base Address */ +#define AT91C_BASE_CAN_MB3 ( ( AT91PS_CAN_MB ) 0xFFFD0260 ) /* (CAN_MB3) Base Address */ +#define AT91C_BASE_CAN_MB4 ( ( AT91PS_CAN_MB ) 0xFFFD0280 ) /* (CAN_MB4) Base Address */ +#define AT91C_BASE_CAN_MB5 ( ( AT91PS_CAN_MB ) 0xFFFD02A0 ) /* (CAN_MB5) Base Address */ +#define AT91C_BASE_CAN_MB6 ( ( AT91PS_CAN_MB ) 0xFFFD02C0 ) /* (CAN_MB6) Base Address */ +#define AT91C_BASE_CAN_MB7 ( ( AT91PS_CAN_MB ) 0xFFFD02E0 ) /* (CAN_MB7) Base Address */ +#define AT91C_BASE_CAN ( ( AT91PS_CAN ) 0xFFFD0000 ) /* (CAN) Base Address */ +#define AT91C_BASE_EMAC ( ( AT91PS_EMAC ) 0xFFFDC000 ) /* (EMAC) Base Address */ +#define AT91C_BASE_PDC_ADC ( ( AT91PS_PDC ) 0xFFFD8100 ) /* (PDC_ADC) Base Address */ +#define AT91C_BASE_ADC ( ( AT91PS_ADC ) 0xFFFD8000 ) /* (ADC) Base Address */ +#define AT91C_BASE_PDC_AES ( ( AT91PS_PDC ) 0xFFFA4100 ) /* (PDC_AES) Base Address */ +#define AT91C_BASE_AES ( ( AT91PS_AES ) 0xFFFA4000 ) /* (AES) Base Address */ +#define AT91C_BASE_PDC_TDES ( ( AT91PS_PDC ) 0xFFFA8100 ) /* (PDC_TDES) Base Address */ +#define AT91C_BASE_TDES ( ( AT91PS_TDES ) 0xFFFA8000 ) /* (TDES) Base Address */ + +/* ***************************************************************************** */ +/* MEMORY MAPPING DEFINITIONS FOR AT91SAM7X128 */ +/* ***************************************************************************** */ +#define AT91C_ISRAM ( ( char * ) 0x00200000 ) /* Internal SRAM base address */ +#define AT91C_ISRAM_SIZE ( ( unsigned int ) 0x00008000 ) /* Internal SRAM size in byte (32 Kbyte) */ +#define AT91C_IFLASH ( ( char * ) 0x00100000 ) /* Internal ROM base address */ +#define AT91C_IFLASH_SIZE ( ( unsigned int ) 0x00020000 ) /* Internal ROM size in byte (128 Kbyte) */ + +#endif /* ifndef AT91SAM7X128_H */ diff --git a/Source/portable/IAR/AtmelSAM7S64/AT91SAM7X128_inc.h b/Source/portable/IAR/AtmelSAM7S64/AT91SAM7X128_inc.h index e76fdd774..fe701970e 100644 --- a/Source/portable/IAR/AtmelSAM7S64/AT91SAM7X128_inc.h +++ b/Source/portable/IAR/AtmelSAM7S64/AT91SAM7X128_inc.h @@ -1,2444 +1,2444 @@ -// ---------------------------------------------------------------------------- -// ATMEL Microcontroller Software Support - ROUSSET - -// ---------------------------------------------------------------------------- -// DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR -// IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF -// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE -// DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, -// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, -// OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF -// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING -// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, -// EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// ---------------------------------------------------------------------------- -// File Name : AT91SAM7X128.h -// Object : AT91SAM7X128 definitions -// Generated : AT91 SW Application Group 05/20/2005 (16:22:23) -// -// CVS Reference : /AT91SAM7X128.pl/1.14/Tue May 10 12:12:05 2005// -// CVS Reference : /SYS_SAM7X.pl/1.3/Tue Feb 1 17:01:43 2005// -// CVS Reference : /MC_SAM7X.pl/1.2/Fri May 20 14:13:04 2005// -// CVS Reference : /PMC_SAM7X.pl/1.4/Tue Feb 8 13:58:10 2005// -// CVS Reference : /RSTC_SAM7X.pl/1.1/Tue Feb 1 16:16:26 2005// -// CVS Reference : /UDP_SAM7X.pl/1.1/Tue May 10 11:35:35 2005// -// CVS Reference : /PWM_SAM7X.pl/1.1/Tue May 10 11:53:07 2005// -// CVS Reference : /AIC_6075B.pl/1.3/Fri May 20 14:01:30 2005// -// CVS Reference : /PIO_6057A.pl/1.2/Thu Feb 3 10:18:28 2005// -// CVS Reference : /RTTC_6081A.pl/1.2/Tue Nov 9 14:43:58 2004// -// CVS Reference : /PITC_6079A.pl/1.2/Tue Nov 9 14:43:56 2004// -// CVS Reference : /WDTC_6080A.pl/1.3/Tue Nov 9 14:44:00 2004// -// CVS Reference : /VREG_6085B.pl/1.1/Tue Feb 1 16:05:48 2005// -// CVS Reference : /PDC_6074C.pl/1.2/Thu Feb 3 08:48:54 2005// -// CVS Reference : /DBGU_6059D.pl/1.1/Mon Jan 31 13:15:32 2005// -// CVS Reference : /SPI_6088D.pl/1.3/Fri May 20 14:08:59 2005// -// CVS Reference : /US_6089C.pl/1.1/Mon Jul 12 18:23:26 2004// -// CVS Reference : /SSC_6078A.pl/1.1/Tue Jul 13 07:45:40 2004// -// CVS Reference : /TWI_6061A.pl/1.1/Tue Jul 13 07:38:06 2004// -// CVS Reference : /TC_6082A.pl/1.7/Fri Mar 11 12:52:17 2005// -// CVS Reference : /CAN_6019B.pl/1.1/Tue Mar 8 12:42:22 2005// -// CVS Reference : /EMACB_6119A.pl/1.5/Thu Feb 3 15:52:04 2005// -// CVS Reference : /ADC_6051C.pl/1.1/Fri Oct 17 09:12:38 2003// -// CVS Reference : /AES_6149A.pl/1.10/Mon Feb 7 09:44:25 2005// -// CVS Reference : /DES3_6150A.pl/1.1/Mon Jan 17 08:34:31 2005// -// ---------------------------------------------------------------------------- +/* ---------------------------------------------------------------------------- */ +/* ATMEL Microcontroller Software Support - ROUSSET - */ +/* ---------------------------------------------------------------------------- */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ +/* File Name : AT91SAM7X128.h */ +/* Object : AT91SAM7X128 definitions */ +/* Generated : AT91 SW Application Group 05/20/2005 (16:22:23) */ +/* */ +/* CVS Reference : /AT91SAM7X128.pl/1.14/Tue May 10 12:12:05 2005// */ +/* CVS Reference : /SYS_SAM7X.pl/1.3/Tue Feb 1 17:01:43 2005// */ +/* CVS Reference : /MC_SAM7X.pl/1.2/Fri May 20 14:13:04 2005// */ +/* CVS Reference : /PMC_SAM7X.pl/1.4/Tue Feb 8 13:58:10 2005// */ +/* CVS Reference : /RSTC_SAM7X.pl/1.1/Tue Feb 1 16:16:26 2005// */ +/* CVS Reference : /UDP_SAM7X.pl/1.1/Tue May 10 11:35:35 2005// */ +/* CVS Reference : /PWM_SAM7X.pl/1.1/Tue May 10 11:53:07 2005// */ +/* CVS Reference : /AIC_6075B.pl/1.3/Fri May 20 14:01:30 2005// */ +/* CVS Reference : /PIO_6057A.pl/1.2/Thu Feb 3 10:18:28 2005// */ +/* CVS Reference : /RTTC_6081A.pl/1.2/Tue Nov 9 14:43:58 2004// */ +/* CVS Reference : /PITC_6079A.pl/1.2/Tue Nov 9 14:43:56 2004// */ +/* CVS Reference : /WDTC_6080A.pl/1.3/Tue Nov 9 14:44:00 2004// */ +/* CVS Reference : /VREG_6085B.pl/1.1/Tue Feb 1 16:05:48 2005// */ +/* CVS Reference : /PDC_6074C.pl/1.2/Thu Feb 3 08:48:54 2005// */ +/* CVS Reference : /DBGU_6059D.pl/1.1/Mon Jan 31 13:15:32 2005// */ +/* CVS Reference : /SPI_6088D.pl/1.3/Fri May 20 14:08:59 2005// */ +/* CVS Reference : /US_6089C.pl/1.1/Mon Jul 12 18:23:26 2004// */ +/* CVS Reference : /SSC_6078A.pl/1.1/Tue Jul 13 07:45:40 2004// */ +/* CVS Reference : /TWI_6061A.pl/1.1/Tue Jul 13 07:38:06 2004// */ +/* CVS Reference : /TC_6082A.pl/1.7/Fri Mar 11 12:52:17 2005// */ +/* CVS Reference : /CAN_6019B.pl/1.1/Tue Mar 8 12:42:22 2005// */ +/* CVS Reference : /EMACB_6119A.pl/1.5/Thu Feb 3 15:52:04 2005// */ +/* CVS Reference : /ADC_6051C.pl/1.1/Fri Oct 17 09:12:38 2003// */ +/* CVS Reference : /AES_6149A.pl/1.10/Mon Feb 7 09:44:25 2005// */ +/* CVS Reference : /DES3_6150A.pl/1.1/Mon Jan 17 08:34:31 2005// */ +/* ---------------------------------------------------------------------------- */ -// Hardware register definition +/* Hardware register definition */ -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR System Peripherals -// ***************************************************************************** +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR System Peripherals */ +/* ***************************************************************************** */ -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Advanced Interrupt Controller -// ***************************************************************************** -// *** Register offset in AT91S_AIC structure *** -#define AIC_SMR ( 0) // Source Mode Register -#define AIC_SVR (128) // Source Vector Register -#define AIC_IVR (256) // IRQ Vector Register -#define AIC_FVR (260) // FIQ Vector Register -#define AIC_ISR (264) // Interrupt Status Register -#define AIC_IPR (268) // Interrupt Pending Register -#define AIC_IMR (272) // Interrupt Mask Register -#define AIC_CISR (276) // Core Interrupt Status Register -#define AIC_IECR (288) // Interrupt Enable Command Register -#define AIC_IDCR (292) // Interrupt Disable Command Register -#define AIC_ICCR (296) // Interrupt Clear Command Register -#define AIC_ISCR (300) // Interrupt Set Command Register -#define AIC_EOICR (304) // End of Interrupt Command Register -#define AIC_SPU (308) // Spurious Vector Register -#define AIC_DCR (312) // Debug Control Register (Protect) -#define AIC_FFER (320) // Fast Forcing Enable Register -#define AIC_FFDR (324) // Fast Forcing Disable Register -#define AIC_FFSR (328) // Fast Forcing Status Register -// -------- AIC_SMR : (AIC Offset: 0x0) Control Register -------- -#define AT91C_AIC_PRIOR (0x7 << 0) // (AIC) Priority Level -#define AT91C_AIC_PRIOR_LOWEST (0x0) // (AIC) Lowest priority level -#define AT91C_AIC_PRIOR_HIGHEST (0x7) // (AIC) Highest priority level -#define AT91C_AIC_SRCTYPE (0x3 << 5) // (AIC) Interrupt Source Type -#define AT91C_AIC_SRCTYPE_INT_HIGH_LEVEL (0x0 << 5) // (AIC) Internal Sources Code Label High-level Sensitive -#define AT91C_AIC_SRCTYPE_EXT_LOW_LEVEL (0x0 << 5) // (AIC) External Sources Code Label Low-level Sensitive -#define AT91C_AIC_SRCTYPE_INT_POSITIVE_EDGE (0x1 << 5) // (AIC) Internal Sources Code Label Positive Edge triggered -#define AT91C_AIC_SRCTYPE_EXT_NEGATIVE_EDGE (0x1 << 5) // (AIC) External Sources Code Label Negative Edge triggered -#define AT91C_AIC_SRCTYPE_HIGH_LEVEL (0x2 << 5) // (AIC) Internal Or External Sources Code Label High-level Sensitive -#define AT91C_AIC_SRCTYPE_POSITIVE_EDGE (0x3 << 5) // (AIC) Internal Or External Sources Code Label Positive Edge triggered -// -------- AIC_CISR : (AIC Offset: 0x114) AIC Core Interrupt Status Register -------- -#define AT91C_AIC_NFIQ (0x1 << 0) // (AIC) NFIQ Status -#define AT91C_AIC_NIRQ (0x1 << 1) // (AIC) NIRQ Status -// -------- AIC_DCR : (AIC Offset: 0x138) AIC Debug Control Register (Protect) -------- -#define AT91C_AIC_DCR_PROT (0x1 << 0) // (AIC) Protection Mode -#define AT91C_AIC_DCR_GMSK (0x1 << 1) // (AIC) General Mask +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR Advanced Interrupt Controller */ +/* ***************************************************************************** */ +/* *** Register offset in AT91S_AIC structure *** */ +#define AIC_SMR ( 0 ) /* Source Mode Register */ +#define AIC_SVR ( 128 ) /* Source Vector Register */ +#define AIC_IVR ( 256 ) /* IRQ Vector Register */ +#define AIC_FVR ( 260 ) /* FIQ Vector Register */ +#define AIC_ISR ( 264 ) /* Interrupt Status Register */ +#define AIC_IPR ( 268 ) /* Interrupt Pending Register */ +#define AIC_IMR ( 272 ) /* Interrupt Mask Register */ +#define AIC_CISR ( 276 ) /* Core Interrupt Status Register */ +#define AIC_IECR ( 288 ) /* Interrupt Enable Command Register */ +#define AIC_IDCR ( 292 ) /* Interrupt Disable Command Register */ +#define AIC_ICCR ( 296 ) /* Interrupt Clear Command Register */ +#define AIC_ISCR ( 300 ) /* Interrupt Set Command Register */ +#define AIC_EOICR ( 304 ) /* End of Interrupt Command Register */ +#define AIC_SPU ( 308 ) /* Spurious Vector Register */ +#define AIC_DCR ( 312 ) /* Debug Control Register (Protect) */ +#define AIC_FFER ( 320 ) /* Fast Forcing Enable Register */ +#define AIC_FFDR ( 324 ) /* Fast Forcing Disable Register */ +#define AIC_FFSR ( 328 ) /* Fast Forcing Status Register */ +/* -------- AIC_SMR : (AIC Offset: 0x0) Control Register -------- */ +#define AT91C_AIC_PRIOR ( 0x7 << 0 ) /* (AIC) Priority Level */ +#define AT91C_AIC_PRIOR_LOWEST ( 0x0 ) /* (AIC) Lowest priority level */ +#define AT91C_AIC_PRIOR_HIGHEST ( 0x7 ) /* (AIC) Highest priority level */ +#define AT91C_AIC_SRCTYPE ( 0x3 << 5 ) /* (AIC) Interrupt Source Type */ +#define AT91C_AIC_SRCTYPE_INT_HIGH_LEVEL ( 0x0 << 5 ) /* (AIC) Internal Sources Code Label High-level Sensitive */ +#define AT91C_AIC_SRCTYPE_EXT_LOW_LEVEL ( 0x0 << 5 ) /* (AIC) External Sources Code Label Low-level Sensitive */ +#define AT91C_AIC_SRCTYPE_INT_POSITIVE_EDGE ( 0x1 << 5 ) /* (AIC) Internal Sources Code Label Positive Edge triggered */ +#define AT91C_AIC_SRCTYPE_EXT_NEGATIVE_EDGE ( 0x1 << 5 ) /* (AIC) External Sources Code Label Negative Edge triggered */ +#define AT91C_AIC_SRCTYPE_HIGH_LEVEL ( 0x2 << 5 ) /* (AIC) Internal Or External Sources Code Label High-level Sensitive */ +#define AT91C_AIC_SRCTYPE_POSITIVE_EDGE ( 0x3 << 5 ) /* (AIC) Internal Or External Sources Code Label Positive Edge triggered */ +/* -------- AIC_CISR : (AIC Offset: 0x114) AIC Core Interrupt Status Register -------- */ +#define AT91C_AIC_NFIQ ( 0x1 << 0 ) /* (AIC) NFIQ Status */ +#define AT91C_AIC_NIRQ ( 0x1 << 1 ) /* (AIC) NIRQ Status */ +/* -------- AIC_DCR : (AIC Offset: 0x138) AIC Debug Control Register (Protect) -------- */ +#define AT91C_AIC_DCR_PROT ( 0x1 << 0 ) /* (AIC) Protection Mode */ +#define AT91C_AIC_DCR_GMSK ( 0x1 << 1 ) /* (AIC) General Mask */ -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Peripheral DMA Controller -// ***************************************************************************** -// *** Register offset in AT91S_PDC structure *** -#define PDC_RPR ( 0) // Receive Pointer Register -#define PDC_RCR ( 4) // Receive Counter Register -#define PDC_TPR ( 8) // Transmit Pointer Register -#define PDC_TCR (12) // Transmit Counter Register -#define PDC_RNPR (16) // Receive Next Pointer Register -#define PDC_RNCR (20) // Receive Next Counter Register -#define PDC_TNPR (24) // Transmit Next Pointer Register -#define PDC_TNCR (28) // Transmit Next Counter Register -#define PDC_PTCR (32) // PDC Transfer Control Register -#define PDC_PTSR (36) // PDC Transfer Status Register -// -------- PDC_PTCR : (PDC Offset: 0x20) PDC Transfer Control Register -------- -#define AT91C_PDC_RXTEN (0x1 << 0) // (PDC) Receiver Transfer Enable -#define AT91C_PDC_RXTDIS (0x1 << 1) // (PDC) Receiver Transfer Disable -#define AT91C_PDC_TXTEN (0x1 << 8) // (PDC) Transmitter Transfer Enable -#define AT91C_PDC_TXTDIS (0x1 << 9) // (PDC) Transmitter Transfer Disable -// -------- PDC_PTSR : (PDC Offset: 0x24) PDC Transfer Status Register -------- +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR Peripheral DMA Controller */ +/* ***************************************************************************** */ +/* *** Register offset in AT91S_PDC structure *** */ +#define PDC_RPR ( 0 ) /* Receive Pointer Register */ +#define PDC_RCR ( 4 ) /* Receive Counter Register */ +#define PDC_TPR ( 8 ) /* Transmit Pointer Register */ +#define PDC_TCR ( 12 ) /* Transmit Counter Register */ +#define PDC_RNPR ( 16 ) /* Receive Next Pointer Register */ +#define PDC_RNCR ( 20 ) /* Receive Next Counter Register */ +#define PDC_TNPR ( 24 ) /* Transmit Next Pointer Register */ +#define PDC_TNCR ( 28 ) /* Transmit Next Counter Register */ +#define PDC_PTCR ( 32 ) /* PDC Transfer Control Register */ +#define PDC_PTSR ( 36 ) /* PDC Transfer Status Register */ +/* -------- PDC_PTCR : (PDC Offset: 0x20) PDC Transfer Control Register -------- */ +#define AT91C_PDC_RXTEN ( 0x1 << 0 ) /* (PDC) Receiver Transfer Enable */ +#define AT91C_PDC_RXTDIS ( 0x1 << 1 ) /* (PDC) Receiver Transfer Disable */ +#define AT91C_PDC_TXTEN ( 0x1 << 8 ) /* (PDC) Transmitter Transfer Enable */ +#define AT91C_PDC_TXTDIS ( 0x1 << 9 ) /* (PDC) Transmitter Transfer Disable */ +/* -------- PDC_PTSR : (PDC Offset: 0x24) PDC Transfer Status Register -------- */ -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Debug Unit -// ***************************************************************************** -// *** Register offset in AT91S_DBGU structure *** -#define DBGU_CR ( 0) // Control Register -#define DBGU_MR ( 4) // Mode Register -#define DBGU_IER ( 8) // Interrupt Enable Register -#define DBGU_IDR (12) // Interrupt Disable Register -#define DBGU_IMR (16) // Interrupt Mask Register -#define DBGU_CSR (20) // Channel Status Register -#define DBGU_RHR (24) // Receiver Holding Register -#define DBGU_THR (28) // Transmitter Holding Register -#define DBGU_BRGR (32) // Baud Rate Generator Register -#define DBGU_CIDR (64) // Chip ID Register -#define DBGU_EXID (68) // Chip ID Extension Register -#define DBGU_FNTR (72) // Force NTRST Register -#define DBGU_RPR (256) // Receive Pointer Register -#define DBGU_RCR (260) // Receive Counter Register -#define DBGU_TPR (264) // Transmit Pointer Register -#define DBGU_TCR (268) // Transmit Counter Register -#define DBGU_RNPR (272) // Receive Next Pointer Register -#define DBGU_RNCR (276) // Receive Next Counter Register -#define DBGU_TNPR (280) // Transmit Next Pointer Register -#define DBGU_TNCR (284) // Transmit Next Counter Register -#define DBGU_PTCR (288) // PDC Transfer Control Register -#define DBGU_PTSR (292) // PDC Transfer Status Register -// -------- DBGU_CR : (DBGU Offset: 0x0) Debug Unit Control Register -------- -#define AT91C_US_RSTRX (0x1 << 2) // (DBGU) Reset Receiver -#define AT91C_US_RSTTX (0x1 << 3) // (DBGU) Reset Transmitter -#define AT91C_US_RXEN (0x1 << 4) // (DBGU) Receiver Enable -#define AT91C_US_RXDIS (0x1 << 5) // (DBGU) Receiver Disable -#define AT91C_US_TXEN (0x1 << 6) // (DBGU) Transmitter Enable -#define AT91C_US_TXDIS (0x1 << 7) // (DBGU) Transmitter Disable -#define AT91C_US_RSTSTA (0x1 << 8) // (DBGU) Reset Status Bits -// -------- DBGU_MR : (DBGU Offset: 0x4) Debug Unit Mode Register -------- -#define AT91C_US_PAR (0x7 << 9) // (DBGU) Parity type -#define AT91C_US_PAR_EVEN (0x0 << 9) // (DBGU) Even Parity -#define AT91C_US_PAR_ODD (0x1 << 9) // (DBGU) Odd Parity -#define AT91C_US_PAR_SPACE (0x2 << 9) // (DBGU) Parity forced to 0 (Space) -#define AT91C_US_PAR_MARK (0x3 << 9) // (DBGU) Parity forced to 1 (Mark) -#define AT91C_US_PAR_NONE (0x4 << 9) // (DBGU) No Parity -#define AT91C_US_PAR_MULTI_DROP (0x6 << 9) // (DBGU) Multi-drop mode -#define AT91C_US_CHMODE (0x3 << 14) // (DBGU) Channel Mode -#define AT91C_US_CHMODE_NORMAL (0x0 << 14) // (DBGU) Normal Mode: The USART channel operates as an RX/TX USART. -#define AT91C_US_CHMODE_AUTO (0x1 << 14) // (DBGU) Automatic Echo: Receiver Data Input is connected to the TXD pin. -#define AT91C_US_CHMODE_LOCAL (0x2 << 14) // (DBGU) Local Loopback: Transmitter Output Signal is connected to Receiver Input Signal. -#define AT91C_US_CHMODE_REMOTE (0x3 << 14) // (DBGU) Remote Loopback: RXD pin is internally connected to TXD pin. -// -------- DBGU_IER : (DBGU Offset: 0x8) Debug Unit Interrupt Enable Register -------- -#define AT91C_US_RXRDY (0x1 << 0) // (DBGU) RXRDY Interrupt -#define AT91C_US_TXRDY (0x1 << 1) // (DBGU) TXRDY Interrupt -#define AT91C_US_ENDRX (0x1 << 3) // (DBGU) End of Receive Transfer Interrupt -#define AT91C_US_ENDTX (0x1 << 4) // (DBGU) End of Transmit Interrupt -#define AT91C_US_OVRE (0x1 << 5) // (DBGU) Overrun Interrupt -#define AT91C_US_FRAME (0x1 << 6) // (DBGU) Framing Error Interrupt -#define AT91C_US_PARE (0x1 << 7) // (DBGU) Parity Error Interrupt -#define AT91C_US_TXEMPTY (0x1 << 9) // (DBGU) TXEMPTY Interrupt -#define AT91C_US_TXBUFE (0x1 << 11) // (DBGU) TXBUFE Interrupt -#define AT91C_US_RXBUFF (0x1 << 12) // (DBGU) RXBUFF Interrupt -#define AT91C_US_COMM_TX (0x1 << 30) // (DBGU) COMM_TX Interrupt -#define AT91C_US_COMM_RX (0x1 << 31) // (DBGU) COMM_RX Interrupt -// -------- DBGU_IDR : (DBGU Offset: 0xc) Debug Unit Interrupt Disable Register -------- -// -------- DBGU_IMR : (DBGU Offset: 0x10) Debug Unit Interrupt Mask Register -------- -// -------- DBGU_CSR : (DBGU Offset: 0x14) Debug Unit Channel Status Register -------- -// -------- DBGU_FNTR : (DBGU Offset: 0x48) Debug Unit FORCE_NTRST Register -------- -#define AT91C_US_FORCE_NTRST (0x1 << 0) // (DBGU) Force NTRST in JTAG +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR Debug Unit */ +/* ***************************************************************************** */ +/* *** Register offset in AT91S_DBGU structure *** */ +#define DBGU_CR ( 0 ) /* Control Register */ +#define DBGU_MR ( 4 ) /* Mode Register */ +#define DBGU_IER ( 8 ) /* Interrupt Enable Register */ +#define DBGU_IDR ( 12 ) /* Interrupt Disable Register */ +#define DBGU_IMR ( 16 ) /* Interrupt Mask Register */ +#define DBGU_CSR ( 20 ) /* Channel Status Register */ +#define DBGU_RHR ( 24 ) /* Receiver Holding Register */ +#define DBGU_THR ( 28 ) /* Transmitter Holding Register */ +#define DBGU_BRGR ( 32 ) /* Baud Rate Generator Register */ +#define DBGU_CIDR ( 64 ) /* Chip ID Register */ +#define DBGU_EXID ( 68 ) /* Chip ID Extension Register */ +#define DBGU_FNTR ( 72 ) /* Force NTRST Register */ +#define DBGU_RPR ( 256 ) /* Receive Pointer Register */ +#define DBGU_RCR ( 260 ) /* Receive Counter Register */ +#define DBGU_TPR ( 264 ) /* Transmit Pointer Register */ +#define DBGU_TCR ( 268 ) /* Transmit Counter Register */ +#define DBGU_RNPR ( 272 ) /* Receive Next Pointer Register */ +#define DBGU_RNCR ( 276 ) /* Receive Next Counter Register */ +#define DBGU_TNPR ( 280 ) /* Transmit Next Pointer Register */ +#define DBGU_TNCR ( 284 ) /* Transmit Next Counter Register */ +#define DBGU_PTCR ( 288 ) /* PDC Transfer Control Register */ +#define DBGU_PTSR ( 292 ) /* PDC Transfer Status Register */ +/* -------- DBGU_CR : (DBGU Offset: 0x0) Debug Unit Control Register -------- */ +#define AT91C_US_RSTRX ( 0x1 << 2 ) /* (DBGU) Reset Receiver */ +#define AT91C_US_RSTTX ( 0x1 << 3 ) /* (DBGU) Reset Transmitter */ +#define AT91C_US_RXEN ( 0x1 << 4 ) /* (DBGU) Receiver Enable */ +#define AT91C_US_RXDIS ( 0x1 << 5 ) /* (DBGU) Receiver Disable */ +#define AT91C_US_TXEN ( 0x1 << 6 ) /* (DBGU) Transmitter Enable */ +#define AT91C_US_TXDIS ( 0x1 << 7 ) /* (DBGU) Transmitter Disable */ +#define AT91C_US_RSTSTA ( 0x1 << 8 ) /* (DBGU) Reset Status Bits */ +/* -------- DBGU_MR : (DBGU Offset: 0x4) Debug Unit Mode Register -------- */ +#define AT91C_US_PAR ( 0x7 << 9 ) /* (DBGU) Parity type */ +#define AT91C_US_PAR_EVEN ( 0x0 << 9 ) /* (DBGU) Even Parity */ +#define AT91C_US_PAR_ODD ( 0x1 << 9 ) /* (DBGU) Odd Parity */ +#define AT91C_US_PAR_SPACE ( 0x2 << 9 ) /* (DBGU) Parity forced to 0 (Space) */ +#define AT91C_US_PAR_MARK ( 0x3 << 9 ) /* (DBGU) Parity forced to 1 (Mark) */ +#define AT91C_US_PAR_NONE ( 0x4 << 9 ) /* (DBGU) No Parity */ +#define AT91C_US_PAR_MULTI_DROP ( 0x6 << 9 ) /* (DBGU) Multi-drop mode */ +#define AT91C_US_CHMODE ( 0x3 << 14 ) /* (DBGU) Channel Mode */ +#define AT91C_US_CHMODE_NORMAL ( 0x0 << 14 ) /* (DBGU) Normal Mode: The USART channel operates as an RX/TX USART. */ +#define AT91C_US_CHMODE_AUTO ( 0x1 << 14 ) /* (DBGU) Automatic Echo: Receiver Data Input is connected to the TXD pin. */ +#define AT91C_US_CHMODE_LOCAL ( 0x2 << 14 ) /* (DBGU) Local Loopback: Transmitter Output Signal is connected to Receiver Input Signal. */ +#define AT91C_US_CHMODE_REMOTE ( 0x3 << 14 ) /* (DBGU) Remote Loopback: RXD pin is internally connected to TXD pin. */ +/* -------- DBGU_IER : (DBGU Offset: 0x8) Debug Unit Interrupt Enable Register -------- */ +#define AT91C_US_RXRDY ( 0x1 << 0 ) /* (DBGU) RXRDY Interrupt */ +#define AT91C_US_TXRDY ( 0x1 << 1 ) /* (DBGU) TXRDY Interrupt */ +#define AT91C_US_ENDRX ( 0x1 << 3 ) /* (DBGU) End of Receive Transfer Interrupt */ +#define AT91C_US_ENDTX ( 0x1 << 4 ) /* (DBGU) End of Transmit Interrupt */ +#define AT91C_US_OVRE ( 0x1 << 5 ) /* (DBGU) Overrun Interrupt */ +#define AT91C_US_FRAME ( 0x1 << 6 ) /* (DBGU) Framing Error Interrupt */ +#define AT91C_US_PARE ( 0x1 << 7 ) /* (DBGU) Parity Error Interrupt */ +#define AT91C_US_TXEMPTY ( 0x1 << 9 ) /* (DBGU) TXEMPTY Interrupt */ +#define AT91C_US_TXBUFE ( 0x1 << 11 ) /* (DBGU) TXBUFE Interrupt */ +#define AT91C_US_RXBUFF ( 0x1 << 12 ) /* (DBGU) RXBUFF Interrupt */ +#define AT91C_US_COMM_TX ( 0x1 << 30 ) /* (DBGU) COMM_TX Interrupt */ +#define AT91C_US_COMM_RX ( 0x1 << 31 ) /* (DBGU) COMM_RX Interrupt */ +/* -------- DBGU_IDR : (DBGU Offset: 0xc) Debug Unit Interrupt Disable Register -------- */ +/* -------- DBGU_IMR : (DBGU Offset: 0x10) Debug Unit Interrupt Mask Register -------- */ +/* -------- DBGU_CSR : (DBGU Offset: 0x14) Debug Unit Channel Status Register -------- */ +/* -------- DBGU_FNTR : (DBGU Offset: 0x48) Debug Unit FORCE_NTRST Register -------- */ +#define AT91C_US_FORCE_NTRST ( 0x1 << 0 ) /* (DBGU) Force NTRST in JTAG */ -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Parallel Input Output Controler -// ***************************************************************************** -// *** Register offset in AT91S_PIO structure *** -#define PIO_PER ( 0) // PIO Enable Register -#define PIO_PDR ( 4) // PIO Disable Register -#define PIO_PSR ( 8) // PIO Status Register -#define PIO_OER (16) // Output Enable Register -#define PIO_ODR (20) // Output Disable Registerr -#define PIO_OSR (24) // Output Status Register -#define PIO_IFER (32) // Input Filter Enable Register -#define PIO_IFDR (36) // Input Filter Disable Register -#define PIO_IFSR (40) // Input Filter Status Register -#define PIO_SODR (48) // Set Output Data Register -#define PIO_CODR (52) // Clear Output Data Register -#define PIO_ODSR (56) // Output Data Status Register -#define PIO_PDSR (60) // Pin Data Status Register -#define PIO_IER (64) // Interrupt Enable Register -#define PIO_IDR (68) // Interrupt Disable Register -#define PIO_IMR (72) // Interrupt Mask Register -#define PIO_ISR (76) // Interrupt Status Register -#define PIO_MDER (80) // Multi-driver Enable Register -#define PIO_MDDR (84) // Multi-driver Disable Register -#define PIO_MDSR (88) // Multi-driver Status Register -#define PIO_PPUDR (96) // Pull-up Disable Register -#define PIO_PPUER (100) // Pull-up Enable Register -#define PIO_PPUSR (104) // Pull-up Status Register -#define PIO_ASR (112) // Select A Register -#define PIO_BSR (116) // Select B Register -#define PIO_ABSR (120) // AB Select Status Register -#define PIO_OWER (160) // Output Write Enable Register -#define PIO_OWDR (164) // Output Write Disable Register -#define PIO_OWSR (168) // Output Write Status Register +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR Parallel Input Output Controller */ +/* ***************************************************************************** */ +/* *** Register offset in AT91S_PIO structure *** */ +#define PIO_PER ( 0 ) /* PIO Enable Register */ +#define PIO_PDR ( 4 ) /* PIO Disable Register */ +#define PIO_PSR ( 8 ) /* PIO Status Register */ +#define PIO_OER ( 16 ) /* Output Enable Register */ +#define PIO_ODR ( 20 ) /* Output Disable Registerr */ +#define PIO_OSR ( 24 ) /* Output Status Register */ +#define PIO_IFER ( 32 ) /* Input Filter Enable Register */ +#define PIO_IFDR ( 36 ) /* Input Filter Disable Register */ +#define PIO_IFSR ( 40 ) /* Input Filter Status Register */ +#define PIO_SODR ( 48 ) /* Set Output Data Register */ +#define PIO_CODR ( 52 ) /* Clear Output Data Register */ +#define PIO_ODSR ( 56 ) /* Output Data Status Register */ +#define PIO_PDSR ( 60 ) /* Pin Data Status Register */ +#define PIO_IER ( 64 ) /* Interrupt Enable Register */ +#define PIO_IDR ( 68 ) /* Interrupt Disable Register */ +#define PIO_IMR ( 72 ) /* Interrupt Mask Register */ +#define PIO_ISR ( 76 ) /* Interrupt Status Register */ +#define PIO_MDER ( 80 ) /* Multi-driver Enable Register */ +#define PIO_MDDR ( 84 ) /* Multi-driver Disable Register */ +#define PIO_MDSR ( 88 ) /* Multi-driver Status Register */ +#define PIO_PPUDR ( 96 ) /* Pull-up Disable Register */ +#define PIO_PPUER ( 100 ) /* Pull-up Enable Register */ +#define PIO_PPUSR ( 104 ) /* Pull-up Status Register */ +#define PIO_ASR ( 112 ) /* Select A Register */ +#define PIO_BSR ( 116 ) /* Select B Register */ +#define PIO_ABSR ( 120 ) /* AB Select Status Register */ +#define PIO_OWER ( 160 ) /* Output Write Enable Register */ +#define PIO_OWDR ( 164 ) /* Output Write Disable Register */ +#define PIO_OWSR ( 168 ) /* Output Write Status Register */ -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Clock Generator Controler -// ***************************************************************************** -// *** Register offset in AT91S_CKGR structure *** -#define CKGR_MOR ( 0) // Main Oscillator Register -#define CKGR_MCFR ( 4) // Main Clock Frequency Register -#define CKGR_PLLR (12) // PLL Register -// -------- CKGR_MOR : (CKGR Offset: 0x0) Main Oscillator Register -------- -#define AT91C_CKGR_MOSCEN (0x1 << 0) // (CKGR) Main Oscillator Enable -#define AT91C_CKGR_OSCBYPASS (0x1 << 1) // (CKGR) Main Oscillator Bypass -#define AT91C_CKGR_OSCOUNT (0xFF << 8) // (CKGR) Main Oscillator Start-up Time -// -------- CKGR_MCFR : (CKGR Offset: 0x4) Main Clock Frequency Register -------- -#define AT91C_CKGR_MAINF (0xFFFF << 0) // (CKGR) Main Clock Frequency -#define AT91C_CKGR_MAINRDY (0x1 << 16) // (CKGR) Main Clock Ready -// -------- CKGR_PLLR : (CKGR Offset: 0xc) PLL B Register -------- -#define AT91C_CKGR_DIV (0xFF << 0) // (CKGR) Divider Selected -#define AT91C_CKGR_DIV_0 (0x0) // (CKGR) Divider output is 0 -#define AT91C_CKGR_DIV_BYPASS (0x1) // (CKGR) Divider is bypassed -#define AT91C_CKGR_PLLCOUNT (0x3F << 8) // (CKGR) PLL Counter -#define AT91C_CKGR_OUT (0x3 << 14) // (CKGR) PLL Output Frequency Range -#define AT91C_CKGR_OUT_0 (0x0 << 14) // (CKGR) Please refer to the PLL datasheet -#define AT91C_CKGR_OUT_1 (0x1 << 14) // (CKGR) Please refer to the PLL datasheet -#define AT91C_CKGR_OUT_2 (0x2 << 14) // (CKGR) Please refer to the PLL datasheet -#define AT91C_CKGR_OUT_3 (0x3 << 14) // (CKGR) Please refer to the PLL datasheet -#define AT91C_CKGR_MUL (0x7FF << 16) // (CKGR) PLL Multiplier -#define AT91C_CKGR_USBDIV (0x3 << 28) // (CKGR) Divider for USB Clocks -#define AT91C_CKGR_USBDIV_0 (0x0 << 28) // (CKGR) Divider output is PLL clock output -#define AT91C_CKGR_USBDIV_1 (0x1 << 28) // (CKGR) Divider output is PLL clock output divided by 2 -#define AT91C_CKGR_USBDIV_2 (0x2 << 28) // (CKGR) Divider output is PLL clock output divided by 4 +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR Clock Generator Controller */ +/* ***************************************************************************** */ +/* *** Register offset in AT91S_CKGR structure *** */ +#define CKGR_MOR ( 0 ) /* Main Oscillator Register */ +#define CKGR_MCFR ( 4 ) /* Main Clock Frequency Register */ +#define CKGR_PLLR ( 12 ) /* PLL Register */ +/* -------- CKGR_MOR : (CKGR Offset: 0x0) Main Oscillator Register -------- */ +#define AT91C_CKGR_MOSCEN ( 0x1 << 0 ) /* (CKGR) Main Oscillator Enable */ +#define AT91C_CKGR_OSCBYPASS ( 0x1 << 1 ) /* (CKGR) Main Oscillator Bypass */ +#define AT91C_CKGR_OSCOUNT ( 0xFF << 8 ) /* (CKGR) Main Oscillator Start-up Time */ +/* -------- CKGR_MCFR : (CKGR Offset: 0x4) Main Clock Frequency Register -------- */ +#define AT91C_CKGR_MAINF ( 0xFFFF << 0 ) /* (CKGR) Main Clock Frequency */ +#define AT91C_CKGR_MAINRDY ( 0x1 << 16 ) /* (CKGR) Main Clock Ready */ +/* -------- CKGR_PLLR : (CKGR Offset: 0xc) PLL B Register -------- */ +#define AT91C_CKGR_DIV ( 0xFF << 0 ) /* (CKGR) Divider Selected */ +#define AT91C_CKGR_DIV_0 ( 0x0 ) /* (CKGR) Divider output is 0 */ +#define AT91C_CKGR_DIV_BYPASS ( 0x1 ) /* (CKGR) Divider is bypassed */ +#define AT91C_CKGR_PLLCOUNT ( 0x3F << 8 ) /* (CKGR) PLL Counter */ +#define AT91C_CKGR_OUT ( 0x3 << 14 ) /* (CKGR) PLL Output Frequency Range */ +#define AT91C_CKGR_OUT_0 ( 0x0 << 14 ) /* (CKGR) Please refer to the PLL datasheet */ +#define AT91C_CKGR_OUT_1 ( 0x1 << 14 ) /* (CKGR) Please refer to the PLL datasheet */ +#define AT91C_CKGR_OUT_2 ( 0x2 << 14 ) /* (CKGR) Please refer to the PLL datasheet */ +#define AT91C_CKGR_OUT_3 ( 0x3 << 14 ) /* (CKGR) Please refer to the PLL datasheet */ +#define AT91C_CKGR_MUL ( 0x7FF << 16 ) /* (CKGR) PLL Multiplier */ +#define AT91C_CKGR_USBDIV ( 0x3 << 28 ) /* (CKGR) Divider for USB Clocks */ +#define AT91C_CKGR_USBDIV_0 ( 0x0 << 28 ) /* (CKGR) Divider output is PLL clock output */ +#define AT91C_CKGR_USBDIV_1 ( 0x1 << 28 ) /* (CKGR) Divider output is PLL clock output divided by 2 */ +#define AT91C_CKGR_USBDIV_2 ( 0x2 << 28 ) /* (CKGR) Divider output is PLL clock output divided by 4 */ -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Power Management Controler -// ***************************************************************************** -// *** Register offset in AT91S_PMC structure *** -#define PMC_SCER ( 0) // System Clock Enable Register -#define PMC_SCDR ( 4) // System Clock Disable Register -#define PMC_SCSR ( 8) // System Clock Status Register -#define PMC_PCER (16) // Peripheral Clock Enable Register -#define PMC_PCDR (20) // Peripheral Clock Disable Register -#define PMC_PCSR (24) // Peripheral Clock Status Register -#define PMC_MOR (32) // Main Oscillator Register -#define PMC_MCFR (36) // Main Clock Frequency Register -#define PMC_PLLR (44) // PLL Register -#define PMC_MCKR (48) // Master Clock Register -#define PMC_PCKR (64) // Programmable Clock Register -#define PMC_IER (96) // Interrupt Enable Register -#define PMC_IDR (100) // Interrupt Disable Register -#define PMC_SR (104) // Status Register -#define PMC_IMR (108) // Interrupt Mask Register -// -------- PMC_SCER : (PMC Offset: 0x0) System Clock Enable Register -------- -#define AT91C_PMC_PCK (0x1 << 0) // (PMC) Processor Clock -#define AT91C_PMC_UDP (0x1 << 7) // (PMC) USB Device Port Clock -#define AT91C_PMC_PCK0 (0x1 << 8) // (PMC) Programmable Clock Output -#define AT91C_PMC_PCK1 (0x1 << 9) // (PMC) Programmable Clock Output -#define AT91C_PMC_PCK2 (0x1 << 10) // (PMC) Programmable Clock Output -#define AT91C_PMC_PCK3 (0x1 << 11) // (PMC) Programmable Clock Output -// -------- PMC_SCDR : (PMC Offset: 0x4) System Clock Disable Register -------- -// -------- PMC_SCSR : (PMC Offset: 0x8) System Clock Status Register -------- -// -------- CKGR_MOR : (PMC Offset: 0x20) Main Oscillator Register -------- -// -------- CKGR_MCFR : (PMC Offset: 0x24) Main Clock Frequency Register -------- -// -------- CKGR_PLLR : (PMC Offset: 0x2c) PLL B Register -------- -// -------- PMC_MCKR : (PMC Offset: 0x30) Master Clock Register -------- -#define AT91C_PMC_CSS (0x3 << 0) // (PMC) Programmable Clock Selection -#define AT91C_PMC_CSS_SLOW_CLK (0x0) // (PMC) Slow Clock is selected -#define AT91C_PMC_CSS_MAIN_CLK (0x1) // (PMC) Main Clock is selected -#define AT91C_PMC_CSS_PLL_CLK (0x3) // (PMC) Clock from PLL is selected -#define AT91C_PMC_PRES (0x7 << 2) // (PMC) Programmable Clock Prescaler -#define AT91C_PMC_PRES_CLK (0x0 << 2) // (PMC) Selected clock -#define AT91C_PMC_PRES_CLK_2 (0x1 << 2) // (PMC) Selected clock divided by 2 -#define AT91C_PMC_PRES_CLK_4 (0x2 << 2) // (PMC) Selected clock divided by 4 -#define AT91C_PMC_PRES_CLK_8 (0x3 << 2) // (PMC) Selected clock divided by 8 -#define AT91C_PMC_PRES_CLK_16 (0x4 << 2) // (PMC) Selected clock divided by 16 -#define AT91C_PMC_PRES_CLK_32 (0x5 << 2) // (PMC) Selected clock divided by 32 -#define AT91C_PMC_PRES_CLK_64 (0x6 << 2) // (PMC) Selected clock divided by 64 -// -------- PMC_PCKR : (PMC Offset: 0x40) Programmable Clock Register -------- -// -------- PMC_IER : (PMC Offset: 0x60) PMC Interrupt Enable Register -------- -#define AT91C_PMC_MOSCS (0x1 << 0) // (PMC) MOSC Status/Enable/Disable/Mask -#define AT91C_PMC_LOCK (0x1 << 2) // (PMC) PLL Status/Enable/Disable/Mask -#define AT91C_PMC_MCKRDY (0x1 << 3) // (PMC) MCK_RDY Status/Enable/Disable/Mask -#define AT91C_PMC_PCK0RDY (0x1 << 8) // (PMC) PCK0_RDY Status/Enable/Disable/Mask -#define AT91C_PMC_PCK1RDY (0x1 << 9) // (PMC) PCK1_RDY Status/Enable/Disable/Mask -#define AT91C_PMC_PCK2RDY (0x1 << 10) // (PMC) PCK2_RDY Status/Enable/Disable/Mask -#define AT91C_PMC_PCK3RDY (0x1 << 11) // (PMC) PCK3_RDY Status/Enable/Disable/Mask -// -------- PMC_IDR : (PMC Offset: 0x64) PMC Interrupt Disable Register -------- -// -------- PMC_SR : (PMC Offset: 0x68) PMC Status Register -------- -// -------- PMC_IMR : (PMC Offset: 0x6c) PMC Interrupt Mask Register -------- +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR Power Management Controller */ +/* ***************************************************************************** */ +/* *** Register offset in AT91S_PMC structure *** */ +#define PMC_SCER ( 0 ) /* System Clock Enable Register */ +#define PMC_SCDR ( 4 ) /* System Clock Disable Register */ +#define PMC_SCSR ( 8 ) /* System Clock Status Register */ +#define PMC_PCER ( 16 ) /* Peripheral Clock Enable Register */ +#define PMC_PCDR ( 20 ) /* Peripheral Clock Disable Register */ +#define PMC_PCSR ( 24 ) /* Peripheral Clock Status Register */ +#define PMC_MOR ( 32 ) /* Main Oscillator Register */ +#define PMC_MCFR ( 36 ) /* Main Clock Frequency Register */ +#define PMC_PLLR ( 44 ) /* PLL Register */ +#define PMC_MCKR ( 48 ) /* Master Clock Register */ +#define PMC_PCKR ( 64 ) /* Programmable Clock Register */ +#define PMC_IER ( 96 ) /* Interrupt Enable Register */ +#define PMC_IDR ( 100 ) /* Interrupt Disable Register */ +#define PMC_SR ( 104 ) /* Status Register */ +#define PMC_IMR ( 108 ) /* Interrupt Mask Register */ +/* -------- PMC_SCER : (PMC Offset: 0x0) System Clock Enable Register -------- */ +#define AT91C_PMC_PCK ( 0x1 << 0 ) /* (PMC) Processor Clock */ +#define AT91C_PMC_UDP ( 0x1 << 7 ) /* (PMC) USB Device Port Clock */ +#define AT91C_PMC_PCK0 ( 0x1 << 8 ) /* (PMC) Programmable Clock Output */ +#define AT91C_PMC_PCK1 ( 0x1 << 9 ) /* (PMC) Programmable Clock Output */ +#define AT91C_PMC_PCK2 ( 0x1 << 10 ) /* (PMC) Programmable Clock Output */ +#define AT91C_PMC_PCK3 ( 0x1 << 11 ) /* (PMC) Programmable Clock Output */ +/* -------- PMC_SCDR : (PMC Offset: 0x4) System Clock Disable Register -------- */ +/* -------- PMC_SCSR : (PMC Offset: 0x8) System Clock Status Register -------- */ +/* -------- CKGR_MOR : (PMC Offset: 0x20) Main Oscillator Register -------- */ +/* -------- CKGR_MCFR : (PMC Offset: 0x24) Main Clock Frequency Register -------- */ +/* -------- CKGR_PLLR : (PMC Offset: 0x2c) PLL B Register -------- */ +/* -------- PMC_MCKR : (PMC Offset: 0x30) Master Clock Register -------- */ +#define AT91C_PMC_CSS ( 0x3 << 0 ) /* (PMC) Programmable Clock Selection */ +#define AT91C_PMC_CSS_SLOW_CLK ( 0x0 ) /* (PMC) Slow Clock is selected */ +#define AT91C_PMC_CSS_MAIN_CLK ( 0x1 ) /* (PMC) Main Clock is selected */ +#define AT91C_PMC_CSS_PLL_CLK ( 0x3 ) /* (PMC) Clock from PLL is selected */ +#define AT91C_PMC_PRES ( 0x7 << 2 ) /* (PMC) Programmable Clock Prescaler */ +#define AT91C_PMC_PRES_CLK ( 0x0 << 2 ) /* (PMC) Selected clock */ +#define AT91C_PMC_PRES_CLK_2 ( 0x1 << 2 ) /* (PMC) Selected clock divided by 2 */ +#define AT91C_PMC_PRES_CLK_4 ( 0x2 << 2 ) /* (PMC) Selected clock divided by 4 */ +#define AT91C_PMC_PRES_CLK_8 ( 0x3 << 2 ) /* (PMC) Selected clock divided by 8 */ +#define AT91C_PMC_PRES_CLK_16 ( 0x4 << 2 ) /* (PMC) Selected clock divided by 16 */ +#define AT91C_PMC_PRES_CLK_32 ( 0x5 << 2 ) /* (PMC) Selected clock divided by 32 */ +#define AT91C_PMC_PRES_CLK_64 ( 0x6 << 2 ) /* (PMC) Selected clock divided by 64 */ +/* -------- PMC_PCKR : (PMC Offset: 0x40) Programmable Clock Register -------- */ +/* -------- PMC_IER : (PMC Offset: 0x60) PMC Interrupt Enable Register -------- */ +#define AT91C_PMC_MOSCS ( 0x1 << 0 ) /* (PMC) MOSC Status/Enable/Disable/Mask */ +#define AT91C_PMC_LOCK ( 0x1 << 2 ) /* (PMC) PLL Status/Enable/Disable/Mask */ +#define AT91C_PMC_MCKRDY ( 0x1 << 3 ) /* (PMC) MCK_RDY Status/Enable/Disable/Mask */ +#define AT91C_PMC_PCK0RDY ( 0x1 << 8 ) /* (PMC) PCK0_RDY Status/Enable/Disable/Mask */ +#define AT91C_PMC_PCK1RDY ( 0x1 << 9 ) /* (PMC) PCK1_RDY Status/Enable/Disable/Mask */ +#define AT91C_PMC_PCK2RDY ( 0x1 << 10 ) /* (PMC) PCK2_RDY Status/Enable/Disable/Mask */ +#define AT91C_PMC_PCK3RDY ( 0x1 << 11 ) /* (PMC) PCK3_RDY Status/Enable/Disable/Mask */ +/* -------- PMC_IDR : (PMC Offset: 0x64) PMC Interrupt Disable Register -------- */ +/* -------- PMC_SR : (PMC Offset: 0x68) PMC Status Register -------- */ +/* -------- PMC_IMR : (PMC Offset: 0x6c) PMC Interrupt Mask Register -------- */ -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Reset Controller Interface -// ***************************************************************************** -// *** Register offset in AT91S_RSTC structure *** -#define RSTC_RCR ( 0) // Reset Control Register -#define RSTC_RSR ( 4) // Reset Status Register -#define RSTC_RMR ( 8) // Reset Mode Register -// -------- RSTC_RCR : (RSTC Offset: 0x0) Reset Control Register -------- -#define AT91C_RSTC_PROCRST (0x1 << 0) // (RSTC) Processor Reset -#define AT91C_RSTC_PERRST (0x1 << 2) // (RSTC) Peripheral Reset -#define AT91C_RSTC_EXTRST (0x1 << 3) // (RSTC) External Reset -#define AT91C_RSTC_KEY (0xFF << 24) // (RSTC) Password -// -------- RSTC_RSR : (RSTC Offset: 0x4) Reset Status Register -------- -#define AT91C_RSTC_URSTS (0x1 << 0) // (RSTC) User Reset Status -#define AT91C_RSTC_BODSTS (0x1 << 1) // (RSTC) Brownout Detection Status -#define AT91C_RSTC_RSTTYP (0x7 << 8) // (RSTC) Reset Type -#define AT91C_RSTC_RSTTYP_POWERUP (0x0 << 8) // (RSTC) Power-up Reset. VDDCORE rising. -#define AT91C_RSTC_RSTTYP_WAKEUP (0x1 << 8) // (RSTC) WakeUp Reset. VDDCORE rising. -#define AT91C_RSTC_RSTTYP_WATCHDOG (0x2 << 8) // (RSTC) Watchdog Reset. Watchdog overflow occured. -#define AT91C_RSTC_RSTTYP_SOFTWARE (0x3 << 8) // (RSTC) Software Reset. Processor reset required by the software. -#define AT91C_RSTC_RSTTYP_USER (0x4 << 8) // (RSTC) User Reset. NRST pin detected low. -#define AT91C_RSTC_RSTTYP_BROWNOUT (0x5 << 8) // (RSTC) Brownout Reset occured. -#define AT91C_RSTC_NRSTL (0x1 << 16) // (RSTC) NRST pin level -#define AT91C_RSTC_SRCMP (0x1 << 17) // (RSTC) Software Reset Command in Progress. -// -------- RSTC_RMR : (RSTC Offset: 0x8) Reset Mode Register -------- -#define AT91C_RSTC_URSTEN (0x1 << 0) // (RSTC) User Reset Enable -#define AT91C_RSTC_URSTIEN (0x1 << 4) // (RSTC) User Reset Interrupt Enable -#define AT91C_RSTC_ERSTL (0xF << 8) // (RSTC) User Reset Enable -#define AT91C_RSTC_BODIEN (0x1 << 16) // (RSTC) Brownout Detection Interrupt Enable +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR Reset Controller Interface */ +/* ***************************************************************************** */ +/* *** Register offset in AT91S_RSTC structure *** */ +#define RSTC_RCR ( 0 ) /* Reset Control Register */ +#define RSTC_RSR ( 4 ) /* Reset Status Register */ +#define RSTC_RMR ( 8 ) /* Reset Mode Register */ +/* -------- RSTC_RCR : (RSTC Offset: 0x0) Reset Control Register -------- */ +#define AT91C_RSTC_PROCRST ( 0x1 << 0 ) /* (RSTC) Processor Reset */ +#define AT91C_RSTC_PERRST ( 0x1 << 2 ) /* (RSTC) Peripheral Reset */ +#define AT91C_RSTC_EXTRST ( 0x1 << 3 ) /* (RSTC) External Reset */ +#define AT91C_RSTC_KEY ( 0xFF << 24 ) /* (RSTC) Password */ +/* -------- RSTC_RSR : (RSTC Offset: 0x4) Reset Status Register -------- */ +#define AT91C_RSTC_URSTS ( 0x1 << 0 ) /* (RSTC) User Reset Status */ +#define AT91C_RSTC_BODSTS ( 0x1 << 1 ) /* (RSTC) Brownout Detection Status */ +#define AT91C_RSTC_RSTTYP ( 0x7 << 8 ) /* (RSTC) Reset Type */ +#define AT91C_RSTC_RSTTYP_POWERUP ( 0x0 << 8 ) /* (RSTC) Power-up Reset. VDDCORE rising. */ +#define AT91C_RSTC_RSTTYP_WAKEUP ( 0x1 << 8 ) /* (RSTC) WakeUp Reset. VDDCORE rising. */ +#define AT91C_RSTC_RSTTYP_WATCHDOG ( 0x2 << 8 ) /* (RSTC) Watchdog Reset. Watchdog overflow occurred. */ +#define AT91C_RSTC_RSTTYP_SOFTWARE ( 0x3 << 8 ) /* (RSTC) Software Reset. Processor reset required by the software. */ +#define AT91C_RSTC_RSTTYP_USER ( 0x4 << 8 ) /* (RSTC) User Reset. NRST pin detected low. */ +#define AT91C_RSTC_RSTTYP_BROWNOUT ( 0x5 << 8 ) /* (RSTC) Brownout Reset occurred. */ +#define AT91C_RSTC_NRSTL ( 0x1 << 16 ) /* (RSTC) NRST pin level */ +#define AT91C_RSTC_SRCMP ( 0x1 << 17 ) /* (RSTC) Software Reset Command in Progress. */ +/* -------- RSTC_RMR : (RSTC Offset: 0x8) Reset Mode Register -------- */ +#define AT91C_RSTC_URSTEN ( 0x1 << 0 ) /* (RSTC) User Reset Enable */ +#define AT91C_RSTC_URSTIEN ( 0x1 << 4 ) /* (RSTC) User Reset Interrupt Enable */ +#define AT91C_RSTC_ERSTL ( 0xF << 8 ) /* (RSTC) User Reset Enable */ +#define AT91C_RSTC_BODIEN ( 0x1 << 16 ) /* (RSTC) Brownout Detection Interrupt Enable */ -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Real Time Timer Controller Interface -// ***************************************************************************** -// *** Register offset in AT91S_RTTC structure *** -#define RTTC_RTMR ( 0) // Real-time Mode Register -#define RTTC_RTAR ( 4) // Real-time Alarm Register -#define RTTC_RTVR ( 8) // Real-time Value Register -#define RTTC_RTSR (12) // Real-time Status Register -// -------- RTTC_RTMR : (RTTC Offset: 0x0) Real-time Mode Register -------- -#define AT91C_RTTC_RTPRES (0xFFFF << 0) // (RTTC) Real-time Timer Prescaler Value -#define AT91C_RTTC_ALMIEN (0x1 << 16) // (RTTC) Alarm Interrupt Enable -#define AT91C_RTTC_RTTINCIEN (0x1 << 17) // (RTTC) Real Time Timer Increment Interrupt Enable -#define AT91C_RTTC_RTTRST (0x1 << 18) // (RTTC) Real Time Timer Restart -// -------- RTTC_RTAR : (RTTC Offset: 0x4) Real-time Alarm Register -------- -#define AT91C_RTTC_ALMV (0x0 << 0) // (RTTC) Alarm Value -// -------- RTTC_RTVR : (RTTC Offset: 0x8) Current Real-time Value Register -------- -#define AT91C_RTTC_CRTV (0x0 << 0) // (RTTC) Current Real-time Value -// -------- RTTC_RTSR : (RTTC Offset: 0xc) Real-time Status Register -------- -#define AT91C_RTTC_ALMS (0x1 << 0) // (RTTC) Real-time Alarm Status -#define AT91C_RTTC_RTTINC (0x1 << 1) // (RTTC) Real-time Timer Increment +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR Real Time Timer Controller Interface */ +/* ***************************************************************************** */ +/* *** Register offset in AT91S_RTTC structure *** */ +#define RTTC_RTMR ( 0 ) /* Real-time Mode Register */ +#define RTTC_RTAR ( 4 ) /* Real-time Alarm Register */ +#define RTTC_RTVR ( 8 ) /* Real-time Value Register */ +#define RTTC_RTSR ( 12 ) /* Real-time Status Register */ +/* -------- RTTC_RTMR : (RTTC Offset: 0x0) Real-time Mode Register -------- */ +#define AT91C_RTTC_RTPRES ( 0xFFFF << 0 ) /* (RTTC) Real-time Timer Prescaler Value */ +#define AT91C_RTTC_ALMIEN ( 0x1 << 16 ) /* (RTTC) Alarm Interrupt Enable */ +#define AT91C_RTTC_RTTINCIEN ( 0x1 << 17 ) /* (RTTC) Real Time Timer Increment Interrupt Enable */ +#define AT91C_RTTC_RTTRST ( 0x1 << 18 ) /* (RTTC) Real Time Timer Restart */ +/* -------- RTTC_RTAR : (RTTC Offset: 0x4) Real-time Alarm Register -------- */ +#define AT91C_RTTC_ALMV ( 0x0 << 0 ) /* (RTTC) Alarm Value */ +/* -------- RTTC_RTVR : (RTTC Offset: 0x8) Current Real-time Value Register -------- */ +#define AT91C_RTTC_CRTV ( 0x0 << 0 ) /* (RTTC) Current Real-time Value */ +/* -------- RTTC_RTSR : (RTTC Offset: 0xc) Real-time Status Register -------- */ +#define AT91C_RTTC_ALMS ( 0x1 << 0 ) /* (RTTC) Real-time Alarm Status */ +#define AT91C_RTTC_RTTINC ( 0x1 << 1 ) /* (RTTC) Real-time Timer Increment */ -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Periodic Interval Timer Controller Interface -// ***************************************************************************** -// *** Register offset in AT91S_PITC structure *** -#define PITC_PIMR ( 0) // Period Interval Mode Register -#define PITC_PISR ( 4) // Period Interval Status Register -#define PITC_PIVR ( 8) // Period Interval Value Register -#define PITC_PIIR (12) // Period Interval Image Register -// -------- PITC_PIMR : (PITC Offset: 0x0) Periodic Interval Mode Register -------- -#define AT91C_PITC_PIV (0xFFFFF << 0) // (PITC) Periodic Interval Value -#define AT91C_PITC_PITEN (0x1 << 24) // (PITC) Periodic Interval Timer Enabled -#define AT91C_PITC_PITIEN (0x1 << 25) // (PITC) Periodic Interval Timer Interrupt Enable -// -------- PITC_PISR : (PITC Offset: 0x4) Periodic Interval Status Register -------- -#define AT91C_PITC_PITS (0x1 << 0) // (PITC) Periodic Interval Timer Status -// -------- PITC_PIVR : (PITC Offset: 0x8) Periodic Interval Value Register -------- -#define AT91C_PITC_CPIV (0xFFFFF << 0) // (PITC) Current Periodic Interval Value -#define AT91C_PITC_PICNT (0xFFF << 20) // (PITC) Periodic Interval Counter -// -------- PITC_PIIR : (PITC Offset: 0xc) Periodic Interval Image Register -------- +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR Periodic Interval Timer Controller Interface */ +/* ***************************************************************************** */ +/* *** Register offset in AT91S_PITC structure *** */ +#define PITC_PIMR ( 0 ) /* Period Interval Mode Register */ +#define PITC_PISR ( 4 ) /* Period Interval Status Register */ +#define PITC_PIVR ( 8 ) /* Period Interval Value Register */ +#define PITC_PIIR ( 12 ) /* Period Interval Image Register */ +/* -------- PITC_PIMR : (PITC Offset: 0x0) Periodic Interval Mode Register -------- */ +#define AT91C_PITC_PIV ( 0xFFFFF << 0 ) /* (PITC) Periodic Interval Value */ +#define AT91C_PITC_PITEN ( 0x1 << 24 ) /* (PITC) Periodic Interval Timer Enabled */ +#define AT91C_PITC_PITIEN ( 0x1 << 25 ) /* (PITC) Periodic Interval Timer Interrupt Enable */ +/* -------- PITC_PISR : (PITC Offset: 0x4) Periodic Interval Status Register -------- */ +#define AT91C_PITC_PITS ( 0x1 << 0 ) /* (PITC) Periodic Interval Timer Status */ +/* -------- PITC_PIVR : (PITC Offset: 0x8) Periodic Interval Value Register -------- */ +#define AT91C_PITC_CPIV ( 0xFFFFF << 0 ) /* (PITC) Current Periodic Interval Value */ +#define AT91C_PITC_PICNT ( 0xFFF << 20 ) /* (PITC) Periodic Interval Counter */ +/* -------- PITC_PIIR : (PITC Offset: 0xc) Periodic Interval Image Register -------- */ -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Watchdog Timer Controller Interface -// ***************************************************************************** -// *** Register offset in AT91S_WDTC structure *** -#define WDTC_WDCR ( 0) // Watchdog Control Register -#define WDTC_WDMR ( 4) // Watchdog Mode Register -#define WDTC_WDSR ( 8) // Watchdog Status Register -// -------- WDTC_WDCR : (WDTC Offset: 0x0) Periodic Interval Image Register -------- -#define AT91C_WDTC_WDRSTT (0x1 << 0) // (WDTC) Watchdog Restart -#define AT91C_WDTC_KEY (0xFF << 24) // (WDTC) Watchdog KEY Password -// -------- WDTC_WDMR : (WDTC Offset: 0x4) Watchdog Mode Register -------- -#define AT91C_WDTC_WDV (0xFFF << 0) // (WDTC) Watchdog Timer Restart -#define AT91C_WDTC_WDFIEN (0x1 << 12) // (WDTC) Watchdog Fault Interrupt Enable -#define AT91C_WDTC_WDRSTEN (0x1 << 13) // (WDTC) Watchdog Reset Enable -#define AT91C_WDTC_WDRPROC (0x1 << 14) // (WDTC) Watchdog Timer Restart -#define AT91C_WDTC_WDDIS (0x1 << 15) // (WDTC) Watchdog Disable -#define AT91C_WDTC_WDD (0xFFF << 16) // (WDTC) Watchdog Delta Value -#define AT91C_WDTC_WDDBGHLT (0x1 << 28) // (WDTC) Watchdog Debug Halt -#define AT91C_WDTC_WDIDLEHLT (0x1 << 29) // (WDTC) Watchdog Idle Halt -// -------- WDTC_WDSR : (WDTC Offset: 0x8) Watchdog Status Register -------- -#define AT91C_WDTC_WDUNF (0x1 << 0) // (WDTC) Watchdog Underflow -#define AT91C_WDTC_WDERR (0x1 << 1) // (WDTC) Watchdog Error +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR Watchdog Timer Controller Interface */ +/* ***************************************************************************** */ +/* *** Register offset in AT91S_WDTC structure *** */ +#define WDTC_WDCR ( 0 ) /* Watchdog Control Register */ +#define WDTC_WDMR ( 4 ) /* Watchdog Mode Register */ +#define WDTC_WDSR ( 8 ) /* Watchdog Status Register */ +/* -------- WDTC_WDCR : (WDTC Offset: 0x0) Periodic Interval Image Register -------- */ +#define AT91C_WDTC_WDRSTT ( 0x1 << 0 ) /* (WDTC) Watchdog Restart */ +#define AT91C_WDTC_KEY ( 0xFF << 24 ) /* (WDTC) Watchdog KEY Password */ +/* -------- WDTC_WDMR : (WDTC Offset: 0x4) Watchdog Mode Register -------- */ +#define AT91C_WDTC_WDV ( 0xFFF << 0 ) /* (WDTC) Watchdog Timer Restart */ +#define AT91C_WDTC_WDFIEN ( 0x1 << 12 ) /* (WDTC) Watchdog Fault Interrupt Enable */ +#define AT91C_WDTC_WDRSTEN ( 0x1 << 13 ) /* (WDTC) Watchdog Reset Enable */ +#define AT91C_WDTC_WDRPROC ( 0x1 << 14 ) /* (WDTC) Watchdog Timer Restart */ +#define AT91C_WDTC_WDDIS ( 0x1 << 15 ) /* (WDTC) Watchdog Disable */ +#define AT91C_WDTC_WDD ( 0xFFF << 16 ) /* (WDTC) Watchdog Delta Value */ +#define AT91C_WDTC_WDDBGHLT ( 0x1 << 28 ) /* (WDTC) Watchdog Debug Halt */ +#define AT91C_WDTC_WDIDLEHLT ( 0x1 << 29 ) /* (WDTC) Watchdog Idle Halt */ +/* -------- WDTC_WDSR : (WDTC Offset: 0x8) Watchdog Status Register -------- */ +#define AT91C_WDTC_WDUNF ( 0x1 << 0 ) /* (WDTC) Watchdog Underflow */ +#define AT91C_WDTC_WDERR ( 0x1 << 1 ) /* (WDTC) Watchdog Error */ -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Voltage Regulator Mode Controller Interface -// ***************************************************************************** -// *** Register offset in AT91S_VREG structure *** -#define VREG_MR ( 0) // Voltage Regulator Mode Register -// -------- VREG_MR : (VREG Offset: 0x0) Voltage Regulator Mode Register -------- -#define AT91C_VREG_PSTDBY (0x1 << 0) // (VREG) Voltage Regulator Power Standby Mode +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR Voltage Regulator Mode Controller Interface */ +/* ***************************************************************************** */ +/* *** Register offset in AT91S_VREG structure *** */ +#define VREG_MR ( 0 ) /* Voltage Regulator Mode Register */ +/* -------- VREG_MR : (VREG Offset: 0x0) Voltage Regulator Mode Register -------- */ +#define AT91C_VREG_PSTDBY ( 0x1 << 0 ) /* (VREG) Voltage Regulator Power Standby Mode */ -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Memory Controller Interface -// ***************************************************************************** -// *** Register offset in AT91S_MC structure *** -#define MC_RCR ( 0) // MC Remap Control Register -#define MC_ASR ( 4) // MC Abort Status Register -#define MC_AASR ( 8) // MC Abort Address Status Register -#define MC_FMR (96) // MC Flash Mode Register -#define MC_FCR (100) // MC Flash Command Register -#define MC_FSR (104) // MC Flash Status Register -// -------- MC_RCR : (MC Offset: 0x0) MC Remap Control Register -------- -#define AT91C_MC_RCB (0x1 << 0) // (MC) Remap Command Bit -// -------- MC_ASR : (MC Offset: 0x4) MC Abort Status Register -------- -#define AT91C_MC_UNDADD (0x1 << 0) // (MC) Undefined Addess Abort Status -#define AT91C_MC_MISADD (0x1 << 1) // (MC) Misaligned Addess Abort Status -#define AT91C_MC_ABTSZ (0x3 << 8) // (MC) Abort Size Status -#define AT91C_MC_ABTSZ_BYTE (0x0 << 8) // (MC) Byte -#define AT91C_MC_ABTSZ_HWORD (0x1 << 8) // (MC) Half-word -#define AT91C_MC_ABTSZ_WORD (0x2 << 8) // (MC) Word -#define AT91C_MC_ABTTYP (0x3 << 10) // (MC) Abort Type Status -#define AT91C_MC_ABTTYP_DATAR (0x0 << 10) // (MC) Data Read -#define AT91C_MC_ABTTYP_DATAW (0x1 << 10) // (MC) Data Write -#define AT91C_MC_ABTTYP_FETCH (0x2 << 10) // (MC) Code Fetch -#define AT91C_MC_MST0 (0x1 << 16) // (MC) Master 0 Abort Source -#define AT91C_MC_MST1 (0x1 << 17) // (MC) Master 1 Abort Source -#define AT91C_MC_SVMST0 (0x1 << 24) // (MC) Saved Master 0 Abort Source -#define AT91C_MC_SVMST1 (0x1 << 25) // (MC) Saved Master 1 Abort Source -// -------- MC_FMR : (MC Offset: 0x60) MC Flash Mode Register -------- -#define AT91C_MC_FRDY (0x1 << 0) // (MC) Flash Ready -#define AT91C_MC_LOCKE (0x1 << 2) // (MC) Lock Error -#define AT91C_MC_PROGE (0x1 << 3) // (MC) Programming Error -#define AT91C_MC_NEBP (0x1 << 7) // (MC) No Erase Before Programming -#define AT91C_MC_FWS (0x3 << 8) // (MC) Flash Wait State -#define AT91C_MC_FWS_0FWS (0x0 << 8) // (MC) 1 cycle for Read, 2 for Write operations -#define AT91C_MC_FWS_1FWS (0x1 << 8) // (MC) 2 cycles for Read, 3 for Write operations -#define AT91C_MC_FWS_2FWS (0x2 << 8) // (MC) 3 cycles for Read, 4 for Write operations -#define AT91C_MC_FWS_3FWS (0x3 << 8) // (MC) 4 cycles for Read, 4 for Write operations -#define AT91C_MC_FMCN (0xFF << 16) // (MC) Flash Microsecond Cycle Number -// -------- MC_FCR : (MC Offset: 0x64) MC Flash Command Register -------- -#define AT91C_MC_FCMD (0xF << 0) // (MC) Flash Command -#define AT91C_MC_FCMD_START_PROG (0x1) // (MC) Starts the programming of th epage specified by PAGEN. -#define AT91C_MC_FCMD_LOCK (0x2) // (MC) Starts a lock sequence of the sector defined by the bits 4 to 7 of the field PAGEN. -#define AT91C_MC_FCMD_PROG_AND_LOCK (0x3) // (MC) The lock sequence automatically happens after the programming sequence is completed. -#define AT91C_MC_FCMD_UNLOCK (0x4) // (MC) Starts an unlock sequence of the sector defined by the bits 4 to 7 of the field PAGEN. -#define AT91C_MC_FCMD_ERASE_ALL (0x8) // (MC) Starts the erase of the entire flash.If at least a page is locked, the command is cancelled. -#define AT91C_MC_FCMD_SET_GP_NVM (0xB) // (MC) Set General Purpose NVM bits. -#define AT91C_MC_FCMD_CLR_GP_NVM (0xD) // (MC) Clear General Purpose NVM bits. -#define AT91C_MC_FCMD_SET_SECURITY (0xF) // (MC) Set Security Bit. -#define AT91C_MC_PAGEN (0x3FF << 8) // (MC) Page Number -#define AT91C_MC_KEY (0xFF << 24) // (MC) Writing Protect Key -// -------- MC_FSR : (MC Offset: 0x68) MC Flash Command Register -------- -#define AT91C_MC_SECURITY (0x1 << 4) // (MC) Security Bit Status -#define AT91C_MC_GPNVM0 (0x1 << 8) // (MC) Sector 0 Lock Status -#define AT91C_MC_GPNVM1 (0x1 << 9) // (MC) Sector 1 Lock Status -#define AT91C_MC_GPNVM2 (0x1 << 10) // (MC) Sector 2 Lock Status -#define AT91C_MC_GPNVM3 (0x1 << 11) // (MC) Sector 3 Lock Status -#define AT91C_MC_GPNVM4 (0x1 << 12) // (MC) Sector 4 Lock Status -#define AT91C_MC_GPNVM5 (0x1 << 13) // (MC) Sector 5 Lock Status -#define AT91C_MC_GPNVM6 (0x1 << 14) // (MC) Sector 6 Lock Status -#define AT91C_MC_GPNVM7 (0x1 << 15) // (MC) Sector 7 Lock Status -#define AT91C_MC_LOCKS0 (0x1 << 16) // (MC) Sector 0 Lock Status -#define AT91C_MC_LOCKS1 (0x1 << 17) // (MC) Sector 1 Lock Status -#define AT91C_MC_LOCKS2 (0x1 << 18) // (MC) Sector 2 Lock Status -#define AT91C_MC_LOCKS3 (0x1 << 19) // (MC) Sector 3 Lock Status -#define AT91C_MC_LOCKS4 (0x1 << 20) // (MC) Sector 4 Lock Status -#define AT91C_MC_LOCKS5 (0x1 << 21) // (MC) Sector 5 Lock Status -#define AT91C_MC_LOCKS6 (0x1 << 22) // (MC) Sector 6 Lock Status -#define AT91C_MC_LOCKS7 (0x1 << 23) // (MC) Sector 7 Lock Status -#define AT91C_MC_LOCKS8 (0x1 << 24) // (MC) Sector 8 Lock Status -#define AT91C_MC_LOCKS9 (0x1 << 25) // (MC) Sector 9 Lock Status -#define AT91C_MC_LOCKS10 (0x1 << 26) // (MC) Sector 10 Lock Status -#define AT91C_MC_LOCKS11 (0x1 << 27) // (MC) Sector 11 Lock Status -#define AT91C_MC_LOCKS12 (0x1 << 28) // (MC) Sector 12 Lock Status -#define AT91C_MC_LOCKS13 (0x1 << 29) // (MC) Sector 13 Lock Status -#define AT91C_MC_LOCKS14 (0x1 << 30) // (MC) Sector 14 Lock Status -#define AT91C_MC_LOCKS15 (0x1 << 31) // (MC) Sector 15 Lock Status +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR Memory Controller Interface */ +/* ***************************************************************************** */ +/* *** Register offset in AT91S_MC structure *** */ +#define MC_RCR ( 0 ) /* MC Remap Control Register */ +#define MC_ASR ( 4 ) /* MC Abort Status Register */ +#define MC_AASR ( 8 ) /* MC Abort Address Status Register */ +#define MC_FMR ( 96 ) /* MC Flash Mode Register */ +#define MC_FCR ( 100 ) /* MC Flash Command Register */ +#define MC_FSR ( 104 ) /* MC Flash Status Register */ +/* -------- MC_RCR : (MC Offset: 0x0) MC Remap Control Register -------- */ +#define AT91C_MC_RCB ( 0x1 << 0 ) /* (MC) Remap Command Bit */ +/* -------- MC_ASR : (MC Offset: 0x4) MC Abort Status Register -------- */ +#define AT91C_MC_UNDADD ( 0x1 << 0 ) /* (MC) Undefined Addess Abort Status */ +#define AT91C_MC_MISADD ( 0x1 << 1 ) /* (MC) Misaligned Addess Abort Status */ +#define AT91C_MC_ABTSZ ( 0x3 << 8 ) /* (MC) Abort Size Status */ +#define AT91C_MC_ABTSZ_BYTE ( 0x0 << 8 ) /* (MC) Byte */ +#define AT91C_MC_ABTSZ_HWORD ( 0x1 << 8 ) /* (MC) Half-word */ +#define AT91C_MC_ABTSZ_WORD ( 0x2 << 8 ) /* (MC) Word */ +#define AT91C_MC_ABTTYP ( 0x3 << 10 ) /* (MC) Abort Type Status */ +#define AT91C_MC_ABTTYP_DATAR ( 0x0 << 10 ) /* (MC) Data Read */ +#define AT91C_MC_ABTTYP_DATAW ( 0x1 << 10 ) /* (MC) Data Write */ +#define AT91C_MC_ABTTYP_FETCH ( 0x2 << 10 ) /* (MC) Code Fetch */ +#define AT91C_MC_MST0 ( 0x1 << 16 ) /* (MC) Master 0 Abort Source */ +#define AT91C_MC_MST1 ( 0x1 << 17 ) /* (MC) Master 1 Abort Source */ +#define AT91C_MC_SVMST0 ( 0x1 << 24 ) /* (MC) Saved Master 0 Abort Source */ +#define AT91C_MC_SVMST1 ( 0x1 << 25 ) /* (MC) Saved Master 1 Abort Source */ +/* -------- MC_FMR : (MC Offset: 0x60) MC Flash Mode Register -------- */ +#define AT91C_MC_FRDY ( 0x1 << 0 ) /* (MC) Flash Ready */ +#define AT91C_MC_LOCKE ( 0x1 << 2 ) /* (MC) Lock Error */ +#define AT91C_MC_PROGE ( 0x1 << 3 ) /* (MC) Programming Error */ +#define AT91C_MC_NEBP ( 0x1 << 7 ) /* (MC) No Erase Before Programming */ +#define AT91C_MC_FWS ( 0x3 << 8 ) /* (MC) Flash Wait State */ +#define AT91C_MC_FWS_0FWS ( 0x0 << 8 ) /* (MC) 1 cycle for Read, 2 for Write operations */ +#define AT91C_MC_FWS_1FWS ( 0x1 << 8 ) /* (MC) 2 cycles for Read, 3 for Write operations */ +#define AT91C_MC_FWS_2FWS ( 0x2 << 8 ) /* (MC) 3 cycles for Read, 4 for Write operations */ +#define AT91C_MC_FWS_3FWS ( 0x3 << 8 ) /* (MC) 4 cycles for Read, 4 for Write operations */ +#define AT91C_MC_FMCN ( 0xFF << 16 ) /* (MC) Flash Microsecond Cycle Number */ +/* -------- MC_FCR : (MC Offset: 0x64) MC Flash Command Register -------- */ +#define AT91C_MC_FCMD ( 0xF << 0 ) /* (MC) Flash Command */ +#define AT91C_MC_FCMD_START_PROG ( 0x1 ) /* (MC) Starts the programming of th epage specified by PAGEN. */ +#define AT91C_MC_FCMD_LOCK ( 0x2 ) /* (MC) Starts a lock sequence of the sector defined by the bits 4 to 7 of the field PAGEN. */ +#define AT91C_MC_FCMD_PROG_AND_LOCK ( 0x3 ) /* (MC) The lock sequence automatically happens after the programming sequence is completed. */ +#define AT91C_MC_FCMD_UNLOCK ( 0x4 ) /* (MC) Starts an unlock sequence of the sector defined by the bits 4 to 7 of the field PAGEN. */ +#define AT91C_MC_FCMD_ERASE_ALL ( 0x8 ) /* (MC) Starts the erase of the entire flash.If at least a page is locked, the command is cancelled. */ +#define AT91C_MC_FCMD_SET_GP_NVM ( 0xB ) /* (MC) Set General Purpose NVM bits. */ +#define AT91C_MC_FCMD_CLR_GP_NVM ( 0xD ) /* (MC) Clear General Purpose NVM bits. */ +#define AT91C_MC_FCMD_SET_SECURITY ( 0xF ) /* (MC) Set Security Bit. */ +#define AT91C_MC_PAGEN ( 0x3FF << 8 ) /* (MC) Page Number */ +#define AT91C_MC_KEY ( 0xFF << 24 ) /* (MC) Writing Protect Key */ +/* -------- MC_FSR : (MC Offset: 0x68) MC Flash Command Register -------- */ +#define AT91C_MC_SECURITY ( 0x1 << 4 ) /* (MC) Security Bit Status */ +#define AT91C_MC_GPNVM0 ( 0x1 << 8 ) /* (MC) Sector 0 Lock Status */ +#define AT91C_MC_GPNVM1 ( 0x1 << 9 ) /* (MC) Sector 1 Lock Status */ +#define AT91C_MC_GPNVM2 ( 0x1 << 10 ) /* (MC) Sector 2 Lock Status */ +#define AT91C_MC_GPNVM3 ( 0x1 << 11 ) /* (MC) Sector 3 Lock Status */ +#define AT91C_MC_GPNVM4 ( 0x1 << 12 ) /* (MC) Sector 4 Lock Status */ +#define AT91C_MC_GPNVM5 ( 0x1 << 13 ) /* (MC) Sector 5 Lock Status */ +#define AT91C_MC_GPNVM6 ( 0x1 << 14 ) /* (MC) Sector 6 Lock Status */ +#define AT91C_MC_GPNVM7 ( 0x1 << 15 ) /* (MC) Sector 7 Lock Status */ +#define AT91C_MC_LOCKS0 ( 0x1 << 16 ) /* (MC) Sector 0 Lock Status */ +#define AT91C_MC_LOCKS1 ( 0x1 << 17 ) /* (MC) Sector 1 Lock Status */ +#define AT91C_MC_LOCKS2 ( 0x1 << 18 ) /* (MC) Sector 2 Lock Status */ +#define AT91C_MC_LOCKS3 ( 0x1 << 19 ) /* (MC) Sector 3 Lock Status */ +#define AT91C_MC_LOCKS4 ( 0x1 << 20 ) /* (MC) Sector 4 Lock Status */ +#define AT91C_MC_LOCKS5 ( 0x1 << 21 ) /* (MC) Sector 5 Lock Status */ +#define AT91C_MC_LOCKS6 ( 0x1 << 22 ) /* (MC) Sector 6 Lock Status */ +#define AT91C_MC_LOCKS7 ( 0x1 << 23 ) /* (MC) Sector 7 Lock Status */ +#define AT91C_MC_LOCKS8 ( 0x1 << 24 ) /* (MC) Sector 8 Lock Status */ +#define AT91C_MC_LOCKS9 ( 0x1 << 25 ) /* (MC) Sector 9 Lock Status */ +#define AT91C_MC_LOCKS10 ( 0x1 << 26 ) /* (MC) Sector 10 Lock Status */ +#define AT91C_MC_LOCKS11 ( 0x1 << 27 ) /* (MC) Sector 11 Lock Status */ +#define AT91C_MC_LOCKS12 ( 0x1 << 28 ) /* (MC) Sector 12 Lock Status */ +#define AT91C_MC_LOCKS13 ( 0x1 << 29 ) /* (MC) Sector 13 Lock Status */ +#define AT91C_MC_LOCKS14 ( 0x1 << 30 ) /* (MC) Sector 14 Lock Status */ +#define AT91C_MC_LOCKS15 ( 0x1 << 31 ) /* (MC) Sector 15 Lock Status */ -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Serial Parallel Interface -// ***************************************************************************** -// *** Register offset in AT91S_SPI structure *** -#define SPI_CR ( 0) // Control Register -#define SPI_MR ( 4) // Mode Register -#define SPI_RDR ( 8) // Receive Data Register -#define SPI_TDR (12) // Transmit Data Register -#define SPI_SR (16) // Status Register -#define SPI_IER (20) // Interrupt Enable Register -#define SPI_IDR (24) // Interrupt Disable Register -#define SPI_IMR (28) // Interrupt Mask Register -#define SPI_CSR (48) // Chip Select Register -#define SPI_RPR (256) // Receive Pointer Register -#define SPI_RCR (260) // Receive Counter Register -#define SPI_TPR (264) // Transmit Pointer Register -#define SPI_TCR (268) // Transmit Counter Register -#define SPI_RNPR (272) // Receive Next Pointer Register -#define SPI_RNCR (276) // Receive Next Counter Register -#define SPI_TNPR (280) // Transmit Next Pointer Register -#define SPI_TNCR (284) // Transmit Next Counter Register -#define SPI_PTCR (288) // PDC Transfer Control Register -#define SPI_PTSR (292) // PDC Transfer Status Register -// -------- SPI_CR : (SPI Offset: 0x0) SPI Control Register -------- -#define AT91C_SPI_SPIEN (0x1 << 0) // (SPI) SPI Enable -#define AT91C_SPI_SPIDIS (0x1 << 1) // (SPI) SPI Disable -#define AT91C_SPI_SWRST (0x1 << 7) // (SPI) SPI Software reset -#define AT91C_SPI_LASTXFER (0x1 << 24) // (SPI) SPI Last Transfer -// -------- SPI_MR : (SPI Offset: 0x4) SPI Mode Register -------- -#define AT91C_SPI_MSTR (0x1 << 0) // (SPI) Master/Slave Mode -#define AT91C_SPI_PS (0x1 << 1) // (SPI) Peripheral Select -#define AT91C_SPI_PS_FIXED (0x0 << 1) // (SPI) Fixed Peripheral Select -#define AT91C_SPI_PS_VARIABLE (0x1 << 1) // (SPI) Variable Peripheral Select -#define AT91C_SPI_PCSDEC (0x1 << 2) // (SPI) Chip Select Decode -#define AT91C_SPI_FDIV (0x1 << 3) // (SPI) Clock Selection -#define AT91C_SPI_MODFDIS (0x1 << 4) // (SPI) Mode Fault Detection -#define AT91C_SPI_LLB (0x1 << 7) // (SPI) Clock Selection -#define AT91C_SPI_PCS (0xF << 16) // (SPI) Peripheral Chip Select -#define AT91C_SPI_DLYBCS (0xFF << 24) // (SPI) Delay Between Chip Selects -// -------- SPI_RDR : (SPI Offset: 0x8) Receive Data Register -------- -#define AT91C_SPI_RD (0xFFFF << 0) // (SPI) Receive Data -#define AT91C_SPI_RPCS (0xF << 16) // (SPI) Peripheral Chip Select Status -// -------- SPI_TDR : (SPI Offset: 0xc) Transmit Data Register -------- -#define AT91C_SPI_TD (0xFFFF << 0) // (SPI) Transmit Data -#define AT91C_SPI_TPCS (0xF << 16) // (SPI) Peripheral Chip Select Status -// -------- SPI_SR : (SPI Offset: 0x10) Status Register -------- -#define AT91C_SPI_RDRF (0x1 << 0) // (SPI) Receive Data Register Full -#define AT91C_SPI_TDRE (0x1 << 1) // (SPI) Transmit Data Register Empty -#define AT91C_SPI_MODF (0x1 << 2) // (SPI) Mode Fault Error -#define AT91C_SPI_OVRES (0x1 << 3) // (SPI) Overrun Error Status -#define AT91C_SPI_ENDRX (0x1 << 4) // (SPI) End of Receiver Transfer -#define AT91C_SPI_ENDTX (0x1 << 5) // (SPI) End of Receiver Transfer -#define AT91C_SPI_RXBUFF (0x1 << 6) // (SPI) RXBUFF Interrupt -#define AT91C_SPI_TXBUFE (0x1 << 7) // (SPI) TXBUFE Interrupt -#define AT91C_SPI_NSSR (0x1 << 8) // (SPI) NSSR Interrupt -#define AT91C_SPI_TXEMPTY (0x1 << 9) // (SPI) TXEMPTY Interrupt -#define AT91C_SPI_SPIENS (0x1 << 16) // (SPI) Enable Status -// -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register -------- -// -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register -------- -// -------- SPI_IMR : (SPI Offset: 0x1c) Interrupt Mask Register -------- -// -------- SPI_CSR : (SPI Offset: 0x30) Chip Select Register -------- -#define AT91C_SPI_CPOL (0x1 << 0) // (SPI) Clock Polarity -#define AT91C_SPI_NCPHA (0x1 << 1) // (SPI) Clock Phase -#define AT91C_SPI_CSAAT (0x1 << 3) // (SPI) Chip Select Active After Transfer -#define AT91C_SPI_BITS (0xF << 4) // (SPI) Bits Per Transfer -#define AT91C_SPI_BITS_8 (0x0 << 4) // (SPI) 8 Bits Per transfer -#define AT91C_SPI_BITS_9 (0x1 << 4) // (SPI) 9 Bits Per transfer -#define AT91C_SPI_BITS_10 (0x2 << 4) // (SPI) 10 Bits Per transfer -#define AT91C_SPI_BITS_11 (0x3 << 4) // (SPI) 11 Bits Per transfer -#define AT91C_SPI_BITS_12 (0x4 << 4) // (SPI) 12 Bits Per transfer -#define AT91C_SPI_BITS_13 (0x5 << 4) // (SPI) 13 Bits Per transfer -#define AT91C_SPI_BITS_14 (0x6 << 4) // (SPI) 14 Bits Per transfer -#define AT91C_SPI_BITS_15 (0x7 << 4) // (SPI) 15 Bits Per transfer -#define AT91C_SPI_BITS_16 (0x8 << 4) // (SPI) 16 Bits Per transfer -#define AT91C_SPI_SCBR (0xFF << 8) // (SPI) Serial Clock Baud Rate -#define AT91C_SPI_DLYBS (0xFF << 16) // (SPI) Delay Before SPCK -#define AT91C_SPI_DLYBCT (0xFF << 24) // (SPI) Delay Between Consecutive Transfers +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR Serial Parallel Interface */ +/* ***************************************************************************** */ +/* *** Register offset in AT91S_SPI structure *** */ +#define SPI_CR ( 0 ) /* Control Register */ +#define SPI_MR ( 4 ) /* Mode Register */ +#define SPI_RDR ( 8 ) /* Receive Data Register */ +#define SPI_TDR ( 12 ) /* Transmit Data Register */ +#define SPI_SR ( 16 ) /* Status Register */ +#define SPI_IER ( 20 ) /* Interrupt Enable Register */ +#define SPI_IDR ( 24 ) /* Interrupt Disable Register */ +#define SPI_IMR ( 28 ) /* Interrupt Mask Register */ +#define SPI_CSR ( 48 ) /* Chip Select Register */ +#define SPI_RPR ( 256 ) /* Receive Pointer Register */ +#define SPI_RCR ( 260 ) /* Receive Counter Register */ +#define SPI_TPR ( 264 ) /* Transmit Pointer Register */ +#define SPI_TCR ( 268 ) /* Transmit Counter Register */ +#define SPI_RNPR ( 272 ) /* Receive Next Pointer Register */ +#define SPI_RNCR ( 276 ) /* Receive Next Counter Register */ +#define SPI_TNPR ( 280 ) /* Transmit Next Pointer Register */ +#define SPI_TNCR ( 284 ) /* Transmit Next Counter Register */ +#define SPI_PTCR ( 288 ) /* PDC Transfer Control Register */ +#define SPI_PTSR ( 292 ) /* PDC Transfer Status Register */ +/* -------- SPI_CR : (SPI Offset: 0x0) SPI Control Register -------- */ +#define AT91C_SPI_SPIEN ( 0x1 << 0 ) /* (SPI) SPI Enable */ +#define AT91C_SPI_SPIDIS ( 0x1 << 1 ) /* (SPI) SPI Disable */ +#define AT91C_SPI_SWRST ( 0x1 << 7 ) /* (SPI) SPI Software reset */ +#define AT91C_SPI_LASTXFER ( 0x1 << 24 ) /* (SPI) SPI Last Transfer */ +/* -------- SPI_MR : (SPI Offset: 0x4) SPI Mode Register -------- */ +#define AT91C_SPI_MSTR ( 0x1 << 0 ) /* (SPI) Master/Slave Mode */ +#define AT91C_SPI_PS ( 0x1 << 1 ) /* (SPI) Peripheral Select */ +#define AT91C_SPI_PS_FIXED ( 0x0 << 1 ) /* (SPI) Fixed Peripheral Select */ +#define AT91C_SPI_PS_VARIABLE ( 0x1 << 1 ) /* (SPI) Variable Peripheral Select */ +#define AT91C_SPI_PCSDEC ( 0x1 << 2 ) /* (SPI) Chip Select Decode */ +#define AT91C_SPI_FDIV ( 0x1 << 3 ) /* (SPI) Clock Selection */ +#define AT91C_SPI_MODFDIS ( 0x1 << 4 ) /* (SPI) Mode Fault Detection */ +#define AT91C_SPI_LLB ( 0x1 << 7 ) /* (SPI) Clock Selection */ +#define AT91C_SPI_PCS ( 0xF << 16 ) /* (SPI) Peripheral Chip Select */ +#define AT91C_SPI_DLYBCS ( 0xFF << 24 ) /* (SPI) Delay Between Chip Selects */ +/* -------- SPI_RDR : (SPI Offset: 0x8) Receive Data Register -------- */ +#define AT91C_SPI_RD ( 0xFFFF << 0 ) /* (SPI) Receive Data */ +#define AT91C_SPI_RPCS ( 0xF << 16 ) /* (SPI) Peripheral Chip Select Status */ +/* -------- SPI_TDR : (SPI Offset: 0xc) Transmit Data Register -------- */ +#define AT91C_SPI_TD ( 0xFFFF << 0 ) /* (SPI) Transmit Data */ +#define AT91C_SPI_TPCS ( 0xF << 16 ) /* (SPI) Peripheral Chip Select Status */ +/* -------- SPI_SR : (SPI Offset: 0x10) Status Register -------- */ +#define AT91C_SPI_RDRF ( 0x1 << 0 ) /* (SPI) Receive Data Register Full */ +#define AT91C_SPI_TDRE ( 0x1 << 1 ) /* (SPI) Transmit Data Register Empty */ +#define AT91C_SPI_MODF ( 0x1 << 2 ) /* (SPI) Mode Fault Error */ +#define AT91C_SPI_OVRES ( 0x1 << 3 ) /* (SPI) Overrun Error Status */ +#define AT91C_SPI_ENDRX ( 0x1 << 4 ) /* (SPI) End of Receiver Transfer */ +#define AT91C_SPI_ENDTX ( 0x1 << 5 ) /* (SPI) End of Receiver Transfer */ +#define AT91C_SPI_RXBUFF ( 0x1 << 6 ) /* (SPI) RXBUFF Interrupt */ +#define AT91C_SPI_TXBUFE ( 0x1 << 7 ) /* (SPI) TXBUFE Interrupt */ +#define AT91C_SPI_NSSR ( 0x1 << 8 ) /* (SPI) NSSR Interrupt */ +#define AT91C_SPI_TXEMPTY ( 0x1 << 9 ) /* (SPI) TXEMPTY Interrupt */ +#define AT91C_SPI_SPIENS ( 0x1 << 16 ) /* (SPI) Enable Status */ +/* -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register -------- */ +/* -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register -------- */ +/* -------- SPI_IMR : (SPI Offset: 0x1c) Interrupt Mask Register -------- */ +/* -------- SPI_CSR : (SPI Offset: 0x30) Chip Select Register -------- */ +#define AT91C_SPI_CPOL ( 0x1 << 0 ) /* (SPI) Clock Polarity */ +#define AT91C_SPI_NCPHA ( 0x1 << 1 ) /* (SPI) Clock Phase */ +#define AT91C_SPI_CSAAT ( 0x1 << 3 ) /* (SPI) Chip Select Active After Transfer */ +#define AT91C_SPI_BITS ( 0xF << 4 ) /* (SPI) Bits Per Transfer */ +#define AT91C_SPI_BITS_8 ( 0x0 << 4 ) /* (SPI) 8 Bits Per transfer */ +#define AT91C_SPI_BITS_9 ( 0x1 << 4 ) /* (SPI) 9 Bits Per transfer */ +#define AT91C_SPI_BITS_10 ( 0x2 << 4 ) /* (SPI) 10 Bits Per transfer */ +#define AT91C_SPI_BITS_11 ( 0x3 << 4 ) /* (SPI) 11 Bits Per transfer */ +#define AT91C_SPI_BITS_12 ( 0x4 << 4 ) /* (SPI) 12 Bits Per transfer */ +#define AT91C_SPI_BITS_13 ( 0x5 << 4 ) /* (SPI) 13 Bits Per transfer */ +#define AT91C_SPI_BITS_14 ( 0x6 << 4 ) /* (SPI) 14 Bits Per transfer */ +#define AT91C_SPI_BITS_15 ( 0x7 << 4 ) /* (SPI) 15 Bits Per transfer */ +#define AT91C_SPI_BITS_16 ( 0x8 << 4 ) /* (SPI) 16 Bits Per transfer */ +#define AT91C_SPI_SCBR ( 0xFF << 8 ) /* (SPI) Serial Clock Baud Rate */ +#define AT91C_SPI_DLYBS ( 0xFF << 16 ) /* (SPI) Delay Before SPCK */ +#define AT91C_SPI_DLYBCT ( 0xFF << 24 ) /* (SPI) Delay Between Consecutive Transfers */ -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Usart -// ***************************************************************************** -// *** Register offset in AT91S_USART structure *** -#define US_CR ( 0) // Control Register -#define US_MR ( 4) // Mode Register -#define US_IER ( 8) // Interrupt Enable Register -#define US_IDR (12) // Interrupt Disable Register -#define US_IMR (16) // Interrupt Mask Register -#define US_CSR (20) // Channel Status Register -#define US_RHR (24) // Receiver Holding Register -#define US_THR (28) // Transmitter Holding Register -#define US_BRGR (32) // Baud Rate Generator Register -#define US_RTOR (36) // Receiver Time-out Register -#define US_TTGR (40) // Transmitter Time-guard Register -#define US_FIDI (64) // FI_DI_Ratio Register -#define US_NER (68) // Nb Errors Register -#define US_IF (76) // IRDA_FILTER Register -#define US_RPR (256) // Receive Pointer Register -#define US_RCR (260) // Receive Counter Register -#define US_TPR (264) // Transmit Pointer Register -#define US_TCR (268) // Transmit Counter Register -#define US_RNPR (272) // Receive Next Pointer Register -#define US_RNCR (276) // Receive Next Counter Register -#define US_TNPR (280) // Transmit Next Pointer Register -#define US_TNCR (284) // Transmit Next Counter Register -#define US_PTCR (288) // PDC Transfer Control Register -#define US_PTSR (292) // PDC Transfer Status Register -// -------- US_CR : (USART Offset: 0x0) Debug Unit Control Register -------- -#define AT91C_US_STTBRK (0x1 << 9) // (USART) Start Break -#define AT91C_US_STPBRK (0x1 << 10) // (USART) Stop Break -#define AT91C_US_STTTO (0x1 << 11) // (USART) Start Time-out -#define AT91C_US_SENDA (0x1 << 12) // (USART) Send Address -#define AT91C_US_RSTIT (0x1 << 13) // (USART) Reset Iterations -#define AT91C_US_RSTNACK (0x1 << 14) // (USART) Reset Non Acknowledge -#define AT91C_US_RETTO (0x1 << 15) // (USART) Rearm Time-out -#define AT91C_US_DTREN (0x1 << 16) // (USART) Data Terminal ready Enable -#define AT91C_US_DTRDIS (0x1 << 17) // (USART) Data Terminal ready Disable -#define AT91C_US_RTSEN (0x1 << 18) // (USART) Request to Send enable -#define AT91C_US_RTSDIS (0x1 << 19) // (USART) Request to Send Disable -// -------- US_MR : (USART Offset: 0x4) Debug Unit Mode Register -------- -#define AT91C_US_USMODE (0xF << 0) // (USART) Usart mode -#define AT91C_US_USMODE_NORMAL (0x0) // (USART) Normal -#define AT91C_US_USMODE_RS485 (0x1) // (USART) RS485 -#define AT91C_US_USMODE_HWHSH (0x2) // (USART) Hardware Handshaking -#define AT91C_US_USMODE_MODEM (0x3) // (USART) Modem -#define AT91C_US_USMODE_ISO7816_0 (0x4) // (USART) ISO7816 protocol: T = 0 -#define AT91C_US_USMODE_ISO7816_1 (0x6) // (USART) ISO7816 protocol: T = 1 -#define AT91C_US_USMODE_IRDA (0x8) // (USART) IrDA -#define AT91C_US_USMODE_SWHSH (0xC) // (USART) Software Handshaking -#define AT91C_US_CLKS (0x3 << 4) // (USART) Clock Selection (Baud Rate generator Input Clock -#define AT91C_US_CLKS_CLOCK (0x0 << 4) // (USART) Clock -#define AT91C_US_CLKS_FDIV1 (0x1 << 4) // (USART) fdiv1 -#define AT91C_US_CLKS_SLOW (0x2 << 4) // (USART) slow_clock (ARM) -#define AT91C_US_CLKS_EXT (0x3 << 4) // (USART) External (SCK) -#define AT91C_US_CHRL (0x3 << 6) // (USART) Clock Selection (Baud Rate generator Input Clock -#define AT91C_US_CHRL_5_BITS (0x0 << 6) // (USART) Character Length: 5 bits -#define AT91C_US_CHRL_6_BITS (0x1 << 6) // (USART) Character Length: 6 bits -#define AT91C_US_CHRL_7_BITS (0x2 << 6) // (USART) Character Length: 7 bits -#define AT91C_US_CHRL_8_BITS (0x3 << 6) // (USART) Character Length: 8 bits -#define AT91C_US_SYNC (0x1 << 8) // (USART) Synchronous Mode Select -#define AT91C_US_NBSTOP (0x3 << 12) // (USART) Number of Stop bits -#define AT91C_US_NBSTOP_1_BIT (0x0 << 12) // (USART) 1 stop bit -#define AT91C_US_NBSTOP_15_BIT (0x1 << 12) // (USART) Asynchronous (SYNC=0) 2 stop bits Synchronous (SYNC=1) 2 stop bits -#define AT91C_US_NBSTOP_2_BIT (0x2 << 12) // (USART) 2 stop bits -#define AT91C_US_MSBF (0x1 << 16) // (USART) Bit Order -#define AT91C_US_MODE9 (0x1 << 17) // (USART) 9-bit Character length -#define AT91C_US_CKLO (0x1 << 18) // (USART) Clock Output Select -#define AT91C_US_OVER (0x1 << 19) // (USART) Over Sampling Mode -#define AT91C_US_INACK (0x1 << 20) // (USART) Inhibit Non Acknowledge -#define AT91C_US_DSNACK (0x1 << 21) // (USART) Disable Successive NACK -#define AT91C_US_MAX_ITER (0x1 << 24) // (USART) Number of Repetitions -#define AT91C_US_FILTER (0x1 << 28) // (USART) Receive Line Filter -// -------- US_IER : (USART Offset: 0x8) Debug Unit Interrupt Enable Register -------- -#define AT91C_US_RXBRK (0x1 << 2) // (USART) Break Received/End of Break -#define AT91C_US_TIMEOUT (0x1 << 8) // (USART) Receiver Time-out -#define AT91C_US_ITERATION (0x1 << 10) // (USART) Max number of Repetitions Reached -#define AT91C_US_NACK (0x1 << 13) // (USART) Non Acknowledge -#define AT91C_US_RIIC (0x1 << 16) // (USART) Ring INdicator Input Change Flag -#define AT91C_US_DSRIC (0x1 << 17) // (USART) Data Set Ready Input Change Flag -#define AT91C_US_DCDIC (0x1 << 18) // (USART) Data Carrier Flag -#define AT91C_US_CTSIC (0x1 << 19) // (USART) Clear To Send Input Change Flag -// -------- US_IDR : (USART Offset: 0xc) Debug Unit Interrupt Disable Register -------- -// -------- US_IMR : (USART Offset: 0x10) Debug Unit Interrupt Mask Register -------- -// -------- US_CSR : (USART Offset: 0x14) Debug Unit Channel Status Register -------- -#define AT91C_US_RI (0x1 << 20) // (USART) Image of RI Input -#define AT91C_US_DSR (0x1 << 21) // (USART) Image of DSR Input -#define AT91C_US_DCD (0x1 << 22) // (USART) Image of DCD Input -#define AT91C_US_CTS (0x1 << 23) // (USART) Image of CTS Input +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR Usart */ +/* ***************************************************************************** */ +/* *** Register offset in AT91S_USART structure *** */ +#define US_CR ( 0 ) /* Control Register */ +#define US_MR ( 4 ) /* Mode Register */ +#define US_IER ( 8 ) /* Interrupt Enable Register */ +#define US_IDR ( 12 ) /* Interrupt Disable Register */ +#define US_IMR ( 16 ) /* Interrupt Mask Register */ +#define US_CSR ( 20 ) /* Channel Status Register */ +#define US_RHR ( 24 ) /* Receiver Holding Register */ +#define US_THR ( 28 ) /* Transmitter Holding Register */ +#define US_BRGR ( 32 ) /* Baud Rate Generator Register */ +#define US_RTOR ( 36 ) /* Receiver Time-out Register */ +#define US_TTGR ( 40 ) /* Transmitter Time-guard Register */ +#define US_FIDI ( 64 ) /* FI_DI_Ratio Register */ +#define US_NER ( 68 ) /* Nb Errors Register */ +#define US_IF ( 76 ) /* IRDA_FILTER Register */ +#define US_RPR ( 256 ) /* Receive Pointer Register */ +#define US_RCR ( 260 ) /* Receive Counter Register */ +#define US_TPR ( 264 ) /* Transmit Pointer Register */ +#define US_TCR ( 268 ) /* Transmit Counter Register */ +#define US_RNPR ( 272 ) /* Receive Next Pointer Register */ +#define US_RNCR ( 276 ) /* Receive Next Counter Register */ +#define US_TNPR ( 280 ) /* Transmit Next Pointer Register */ +#define US_TNCR ( 284 ) /* Transmit Next Counter Register */ +#define US_PTCR ( 288 ) /* PDC Transfer Control Register */ +#define US_PTSR ( 292 ) /* PDC Transfer Status Register */ +/* -------- US_CR : (USART Offset: 0x0) Debug Unit Control Register -------- */ +#define AT91C_US_STTBRK ( 0x1 << 9 ) /* (USART) Start Break */ +#define AT91C_US_STPBRK ( 0x1 << 10 ) /* (USART) Stop Break */ +#define AT91C_US_STTTO ( 0x1 << 11 ) /* (USART) Start Time-out */ +#define AT91C_US_SENDA ( 0x1 << 12 ) /* (USART) Send Address */ +#define AT91C_US_RSTIT ( 0x1 << 13 ) /* (USART) Reset Iterations */ +#define AT91C_US_RSTNACK ( 0x1 << 14 ) /* (USART) Reset Non Acknowledge */ +#define AT91C_US_RETTO ( 0x1 << 15 ) /* (USART) Rearm Time-out */ +#define AT91C_US_DTREN ( 0x1 << 16 ) /* (USART) Data Terminal ready Enable */ +#define AT91C_US_DTRDIS ( 0x1 << 17 ) /* (USART) Data Terminal ready Disable */ +#define AT91C_US_RTSEN ( 0x1 << 18 ) /* (USART) Request to Send enable */ +#define AT91C_US_RTSDIS ( 0x1 << 19 ) /* (USART) Request to Send Disable */ +/* -------- US_MR : (USART Offset: 0x4) Debug Unit Mode Register -------- */ +#define AT91C_US_USMODE ( 0xF << 0 ) /* (USART) Usart mode */ +#define AT91C_US_USMODE_NORMAL ( 0x0 ) /* (USART) Normal */ +#define AT91C_US_USMODE_RS485 ( 0x1 ) /* (USART) RS485 */ +#define AT91C_US_USMODE_HWHSH ( 0x2 ) /* (USART) Hardware Handshaking */ +#define AT91C_US_USMODE_MODEM ( 0x3 ) /* (USART) Modem */ +#define AT91C_US_USMODE_ISO7816_0 ( 0x4 ) /* (USART) ISO7816 protocol: T = 0 */ +#define AT91C_US_USMODE_ISO7816_1 ( 0x6 ) /* (USART) ISO7816 protocol: T = 1 */ +#define AT91C_US_USMODE_IRDA ( 0x8 ) /* (USART) IrDA */ +#define AT91C_US_USMODE_SWHSH ( 0xC ) /* (USART) Software Handshaking */ +#define AT91C_US_CLKS ( 0x3 << 4 ) /* (USART) Clock Selection (Baud Rate generator Input Clock */ +#define AT91C_US_CLKS_CLOCK ( 0x0 << 4 ) /* (USART) Clock */ +#define AT91C_US_CLKS_FDIV1 ( 0x1 << 4 ) /* (USART) fdiv1 */ +#define AT91C_US_CLKS_SLOW ( 0x2 << 4 ) /* (USART) slow_clock (ARM) */ +#define AT91C_US_CLKS_EXT ( 0x3 << 4 ) /* (USART) External (SCK) */ +#define AT91C_US_CHRL ( 0x3 << 6 ) /* (USART) Clock Selection (Baud Rate generator Input Clock */ +#define AT91C_US_CHRL_5_BITS ( 0x0 << 6 ) /* (USART) Character Length: 5 bits */ +#define AT91C_US_CHRL_6_BITS ( 0x1 << 6 ) /* (USART) Character Length: 6 bits */ +#define AT91C_US_CHRL_7_BITS ( 0x2 << 6 ) /* (USART) Character Length: 7 bits */ +#define AT91C_US_CHRL_8_BITS ( 0x3 << 6 ) /* (USART) Character Length: 8 bits */ +#define AT91C_US_SYNC ( 0x1 << 8 ) /* (USART) Synchronous Mode Select */ +#define AT91C_US_NBSTOP ( 0x3 << 12 ) /* (USART) Number of Stop bits */ +#define AT91C_US_NBSTOP_1_BIT ( 0x0 << 12 ) /* (USART) 1 stop bit */ +#define AT91C_US_NBSTOP_15_BIT ( 0x1 << 12 ) /* (USART) Asynchronous (SYNC=0) 2 stop bits Synchronous (SYNC=1) 2 stop bits */ +#define AT91C_US_NBSTOP_2_BIT ( 0x2 << 12 ) /* (USART) 2 stop bits */ +#define AT91C_US_MSBF ( 0x1 << 16 ) /* (USART) Bit Order */ +#define AT91C_US_MODE9 ( 0x1 << 17 ) /* (USART) 9-bit Character length */ +#define AT91C_US_CKLO ( 0x1 << 18 ) /* (USART) Clock Output Select */ +#define AT91C_US_OVER ( 0x1 << 19 ) /* (USART) Over Sampling Mode */ +#define AT91C_US_INACK ( 0x1 << 20 ) /* (USART) Inhibit Non Acknowledge */ +#define AT91C_US_DSNACK ( 0x1 << 21 ) /* (USART) Disable Successive NACK */ +#define AT91C_US_MAX_ITER ( 0x1 << 24 ) /* (USART) Number of Repetitions */ +#define AT91C_US_FILTER ( 0x1 << 28 ) /* (USART) Receive Line Filter */ +/* -------- US_IER : (USART Offset: 0x8) Debug Unit Interrupt Enable Register -------- */ +#define AT91C_US_RXBRK ( 0x1 << 2 ) /* (USART) Break Received/End of Break */ +#define AT91C_US_TIMEOUT ( 0x1 << 8 ) /* (USART) Receiver Time-out */ +#define AT91C_US_ITERATION ( 0x1 << 10 ) /* (USART) Max number of Repetitions Reached */ +#define AT91C_US_NACK ( 0x1 << 13 ) /* (USART) Non Acknowledge */ +#define AT91C_US_RIIC ( 0x1 << 16 ) /* (USART) Ring INdicator Input Change Flag */ +#define AT91C_US_DSRIC ( 0x1 << 17 ) /* (USART) Data Set Ready Input Change Flag */ +#define AT91C_US_DCDIC ( 0x1 << 18 ) /* (USART) Data Carrier Flag */ +#define AT91C_US_CTSIC ( 0x1 << 19 ) /* (USART) Clear To Send Input Change Flag */ +/* -------- US_IDR : (USART Offset: 0xc) Debug Unit Interrupt Disable Register -------- */ +/* -------- US_IMR : (USART Offset: 0x10) Debug Unit Interrupt Mask Register -------- */ +/* -------- US_CSR : (USART Offset: 0x14) Debug Unit Channel Status Register -------- */ +#define AT91C_US_RI ( 0x1 << 20 ) /* (USART) Image of RI Input */ +#define AT91C_US_DSR ( 0x1 << 21 ) /* (USART) Image of DSR Input */ +#define AT91C_US_DCD ( 0x1 << 22 ) /* (USART) Image of DCD Input */ +#define AT91C_US_CTS ( 0x1 << 23 ) /* (USART) Image of CTS Input */ -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Synchronous Serial Controller Interface -// ***************************************************************************** -// *** Register offset in AT91S_SSC structure *** -#define SSC_CR ( 0) // Control Register -#define SSC_CMR ( 4) // Clock Mode Register -#define SSC_RCMR (16) // Receive Clock ModeRegister -#define SSC_RFMR (20) // Receive Frame Mode Register -#define SSC_TCMR (24) // Transmit Clock Mode Register -#define SSC_TFMR (28) // Transmit Frame Mode Register -#define SSC_RHR (32) // Receive Holding Register -#define SSC_THR (36) // Transmit Holding Register -#define SSC_RSHR (48) // Receive Sync Holding Register -#define SSC_TSHR (52) // Transmit Sync Holding Register -#define SSC_SR (64) // Status Register -#define SSC_IER (68) // Interrupt Enable Register -#define SSC_IDR (72) // Interrupt Disable Register -#define SSC_IMR (76) // Interrupt Mask Register -#define SSC_RPR (256) // Receive Pointer Register -#define SSC_RCR (260) // Receive Counter Register -#define SSC_TPR (264) // Transmit Pointer Register -#define SSC_TCR (268) // Transmit Counter Register -#define SSC_RNPR (272) // Receive Next Pointer Register -#define SSC_RNCR (276) // Receive Next Counter Register -#define SSC_TNPR (280) // Transmit Next Pointer Register -#define SSC_TNCR (284) // Transmit Next Counter Register -#define SSC_PTCR (288) // PDC Transfer Control Register -#define SSC_PTSR (292) // PDC Transfer Status Register -// -------- SSC_CR : (SSC Offset: 0x0) SSC Control Register -------- -#define AT91C_SSC_RXEN (0x1 << 0) // (SSC) Receive Enable -#define AT91C_SSC_RXDIS (0x1 << 1) // (SSC) Receive Disable -#define AT91C_SSC_TXEN (0x1 << 8) // (SSC) Transmit Enable -#define AT91C_SSC_TXDIS (0x1 << 9) // (SSC) Transmit Disable -#define AT91C_SSC_SWRST (0x1 << 15) // (SSC) Software Reset -// -------- SSC_RCMR : (SSC Offset: 0x10) SSC Receive Clock Mode Register -------- -#define AT91C_SSC_CKS (0x3 << 0) // (SSC) Receive/Transmit Clock Selection -#define AT91C_SSC_CKS_DIV (0x0) // (SSC) Divided Clock -#define AT91C_SSC_CKS_TK (0x1) // (SSC) TK Clock signal -#define AT91C_SSC_CKS_RK (0x2) // (SSC) RK pin -#define AT91C_SSC_CKO (0x7 << 2) // (SSC) Receive/Transmit Clock Output Mode Selection -#define AT91C_SSC_CKO_NONE (0x0 << 2) // (SSC) Receive/Transmit Clock Output Mode: None RK pin: Input-only -#define AT91C_SSC_CKO_CONTINOUS (0x1 << 2) // (SSC) Continuous Receive/Transmit Clock RK pin: Output -#define AT91C_SSC_CKO_DATA_TX (0x2 << 2) // (SSC) Receive/Transmit Clock only during data transfers RK pin: Output -#define AT91C_SSC_CKI (0x1 << 5) // (SSC) Receive/Transmit Clock Inversion -#define AT91C_SSC_START (0xF << 8) // (SSC) Receive/Transmit Start Selection -#define AT91C_SSC_START_CONTINOUS (0x0 << 8) // (SSC) Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data. -#define AT91C_SSC_START_TX (0x1 << 8) // (SSC) Transmit/Receive start -#define AT91C_SSC_START_LOW_RF (0x2 << 8) // (SSC) Detection of a low level on RF input -#define AT91C_SSC_START_HIGH_RF (0x3 << 8) // (SSC) Detection of a high level on RF input -#define AT91C_SSC_START_FALL_RF (0x4 << 8) // (SSC) Detection of a falling edge on RF input -#define AT91C_SSC_START_RISE_RF (0x5 << 8) // (SSC) Detection of a rising edge on RF input -#define AT91C_SSC_START_LEVEL_RF (0x6 << 8) // (SSC) Detection of any level change on RF input -#define AT91C_SSC_START_EDGE_RF (0x7 << 8) // (SSC) Detection of any edge on RF input -#define AT91C_SSC_START_0 (0x8 << 8) // (SSC) Compare 0 -#define AT91C_SSC_STTDLY (0xFF << 16) // (SSC) Receive/Transmit Start Delay -#define AT91C_SSC_PERIOD (0xFF << 24) // (SSC) Receive/Transmit Period Divider Selection -// -------- SSC_RFMR : (SSC Offset: 0x14) SSC Receive Frame Mode Register -------- -#define AT91C_SSC_DATLEN (0x1F << 0) // (SSC) Data Length -#define AT91C_SSC_LOOP (0x1 << 5) // (SSC) Loop Mode -#define AT91C_SSC_MSBF (0x1 << 7) // (SSC) Most Significant Bit First -#define AT91C_SSC_DATNB (0xF << 8) // (SSC) Data Number per Frame -#define AT91C_SSC_FSLEN (0xF << 16) // (SSC) Receive/Transmit Frame Sync length -#define AT91C_SSC_FSOS (0x7 << 20) // (SSC) Receive/Transmit Frame Sync Output Selection -#define AT91C_SSC_FSOS_NONE (0x0 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: None RK pin Input-only -#define AT91C_SSC_FSOS_NEGATIVE (0x1 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Negative Pulse -#define AT91C_SSC_FSOS_POSITIVE (0x2 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Positive Pulse -#define AT91C_SSC_FSOS_LOW (0x3 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver Low during data transfer -#define AT91C_SSC_FSOS_HIGH (0x4 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver High during data transfer -#define AT91C_SSC_FSOS_TOGGLE (0x5 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Toggling at each start of data transfer -#define AT91C_SSC_FSEDGE (0x1 << 24) // (SSC) Frame Sync Edge Detection -// -------- SSC_TCMR : (SSC Offset: 0x18) SSC Transmit Clock Mode Register -------- -// -------- SSC_TFMR : (SSC Offset: 0x1c) SSC Transmit Frame Mode Register -------- -#define AT91C_SSC_DATDEF (0x1 << 5) // (SSC) Data Default Value -#define AT91C_SSC_FSDEN (0x1 << 23) // (SSC) Frame Sync Data Enable -// -------- SSC_SR : (SSC Offset: 0x40) SSC Status Register -------- -#define AT91C_SSC_TXRDY (0x1 << 0) // (SSC) Transmit Ready -#define AT91C_SSC_TXEMPTY (0x1 << 1) // (SSC) Transmit Empty -#define AT91C_SSC_ENDTX (0x1 << 2) // (SSC) End Of Transmission -#define AT91C_SSC_TXBUFE (0x1 << 3) // (SSC) Transmit Buffer Empty -#define AT91C_SSC_RXRDY (0x1 << 4) // (SSC) Receive Ready -#define AT91C_SSC_OVRUN (0x1 << 5) // (SSC) Receive Overrun -#define AT91C_SSC_ENDRX (0x1 << 6) // (SSC) End of Reception -#define AT91C_SSC_RXBUFF (0x1 << 7) // (SSC) Receive Buffer Full -#define AT91C_SSC_TXSYN (0x1 << 10) // (SSC) Transmit Sync -#define AT91C_SSC_RXSYN (0x1 << 11) // (SSC) Receive Sync -#define AT91C_SSC_TXENA (0x1 << 16) // (SSC) Transmit Enable -#define AT91C_SSC_RXENA (0x1 << 17) // (SSC) Receive Enable -// -------- SSC_IER : (SSC Offset: 0x44) SSC Interrupt Enable Register -------- -// -------- SSC_IDR : (SSC Offset: 0x48) SSC Interrupt Disable Register -------- -// -------- SSC_IMR : (SSC Offset: 0x4c) SSC Interrupt Mask Register -------- +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR Synchronous Serial Controller Interface */ +/* ***************************************************************************** */ +/* *** Register offset in AT91S_SSC structure *** */ +#define SSC_CR ( 0 ) /* Control Register */ +#define SSC_CMR ( 4 ) /* Clock Mode Register */ +#define SSC_RCMR ( 16 ) /* Receive Clock ModeRegister */ +#define SSC_RFMR ( 20 ) /* Receive Frame Mode Register */ +#define SSC_TCMR ( 24 ) /* Transmit Clock Mode Register */ +#define SSC_TFMR ( 28 ) /* Transmit Frame Mode Register */ +#define SSC_RHR ( 32 ) /* Receive Holding Register */ +#define SSC_THR ( 36 ) /* Transmit Holding Register */ +#define SSC_RSHR ( 48 ) /* Receive Sync Holding Register */ +#define SSC_TSHR ( 52 ) /* Transmit Sync Holding Register */ +#define SSC_SR ( 64 ) /* Status Register */ +#define SSC_IER ( 68 ) /* Interrupt Enable Register */ +#define SSC_IDR ( 72 ) /* Interrupt Disable Register */ +#define SSC_IMR ( 76 ) /* Interrupt Mask Register */ +#define SSC_RPR ( 256 ) /* Receive Pointer Register */ +#define SSC_RCR ( 260 ) /* Receive Counter Register */ +#define SSC_TPR ( 264 ) /* Transmit Pointer Register */ +#define SSC_TCR ( 268 ) /* Transmit Counter Register */ +#define SSC_RNPR ( 272 ) /* Receive Next Pointer Register */ +#define SSC_RNCR ( 276 ) /* Receive Next Counter Register */ +#define SSC_TNPR ( 280 ) /* Transmit Next Pointer Register */ +#define SSC_TNCR ( 284 ) /* Transmit Next Counter Register */ +#define SSC_PTCR ( 288 ) /* PDC Transfer Control Register */ +#define SSC_PTSR ( 292 ) /* PDC Transfer Status Register */ +/* -------- SSC_CR : (SSC Offset: 0x0) SSC Control Register -------- */ +#define AT91C_SSC_RXEN ( 0x1 << 0 ) /* (SSC) Receive Enable */ +#define AT91C_SSC_RXDIS ( 0x1 << 1 ) /* (SSC) Receive Disable */ +#define AT91C_SSC_TXEN ( 0x1 << 8 ) /* (SSC) Transmit Enable */ +#define AT91C_SSC_TXDIS ( 0x1 << 9 ) /* (SSC) Transmit Disable */ +#define AT91C_SSC_SWRST ( 0x1 << 15 ) /* (SSC) Software Reset */ +/* -------- SSC_RCMR : (SSC Offset: 0x10) SSC Receive Clock Mode Register -------- */ +#define AT91C_SSC_CKS ( 0x3 << 0 ) /* (SSC) Receive/Transmit Clock Selection */ +#define AT91C_SSC_CKS_DIV ( 0x0 ) /* (SSC) Divided Clock */ +#define AT91C_SSC_CKS_TK ( 0x1 ) /* (SSC) TK Clock signal */ +#define AT91C_SSC_CKS_RK ( 0x2 ) /* (SSC) RK pin */ +#define AT91C_SSC_CKO ( 0x7 << 2 ) /* (SSC) Receive/Transmit Clock Output Mode Selection */ +#define AT91C_SSC_CKO_NONE ( 0x0 << 2 ) /* (SSC) Receive/Transmit Clock Output Mode: None RK pin: Input-only */ +#define AT91C_SSC_CKO_CONTINUOUS ( 0x1 << 2 ) /* (SSC) Continuous Receive/Transmit Clock RK pin: Output */ +#define AT91C_SSC_CKO_DATA_TX ( 0x2 << 2 ) /* (SSC) Receive/Transmit Clock only during data transfers RK pin: Output */ +#define AT91C_SSC_CKI ( 0x1 << 5 ) /* (SSC) Receive/Transmit Clock Inversion */ +#define AT91C_SSC_START ( 0xF << 8 ) /* (SSC) Receive/Transmit Start Selection */ +#define AT91C_SSC_START_CONTINUOUS ( 0x0 << 8 ) /* (SSC) Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data. */ +#define AT91C_SSC_START_TX ( 0x1 << 8 ) /* (SSC) Transmit/Receive start */ +#define AT91C_SSC_START_LOW_RF ( 0x2 << 8 ) /* (SSC) Detection of a low level on RF input */ +#define AT91C_SSC_START_HIGH_RF ( 0x3 << 8 ) /* (SSC) Detection of a high level on RF input */ +#define AT91C_SSC_START_FALL_RF ( 0x4 << 8 ) /* (SSC) Detection of a falling edge on RF input */ +#define AT91C_SSC_START_RISE_RF ( 0x5 << 8 ) /* (SSC) Detection of a rising edge on RF input */ +#define AT91C_SSC_START_LEVEL_RF ( 0x6 << 8 ) /* (SSC) Detection of any level change on RF input */ +#define AT91C_SSC_START_EDGE_RF ( 0x7 << 8 ) /* (SSC) Detection of any edge on RF input */ +#define AT91C_SSC_START_0 ( 0x8 << 8 ) /* (SSC) Compare 0 */ +#define AT91C_SSC_STTDLY ( 0xFF << 16 ) /* (SSC) Receive/Transmit Start Delay */ +#define AT91C_SSC_PERIOD ( 0xFF << 24 ) /* (SSC) Receive/Transmit Period Divider Selection */ +/* -------- SSC_RFMR : (SSC Offset: 0x14) SSC Receive Frame Mode Register -------- */ +#define AT91C_SSC_DATLEN ( 0x1F << 0 ) /* (SSC) Data Length */ +#define AT91C_SSC_LOOP ( 0x1 << 5 ) /* (SSC) Loop Mode */ +#define AT91C_SSC_MSBF ( 0x1 << 7 ) /* (SSC) Most Significant Bit First */ +#define AT91C_SSC_DATNB ( 0xF << 8 ) /* (SSC) Data Number per Frame */ +#define AT91C_SSC_FSLEN ( 0xF << 16 ) /* (SSC) Receive/Transmit Frame Sync length */ +#define AT91C_SSC_FSOS ( 0x7 << 20 ) /* (SSC) Receive/Transmit Frame Sync Output Selection */ +#define AT91C_SSC_FSOS_NONE ( 0x0 << 20 ) /* (SSC) Selected Receive/Transmit Frame Sync Signal: None RK pin Input-only */ +#define AT91C_SSC_FSOS_NEGATIVE ( 0x1 << 20 ) /* (SSC) Selected Receive/Transmit Frame Sync Signal: Negative Pulse */ +#define AT91C_SSC_FSOS_POSITIVE ( 0x2 << 20 ) /* (SSC) Selected Receive/Transmit Frame Sync Signal: Positive Pulse */ +#define AT91C_SSC_FSOS_LOW ( 0x3 << 20 ) /* (SSC) Selected Receive/Transmit Frame Sync Signal: Driver Low during data transfer */ +#define AT91C_SSC_FSOS_HIGH ( 0x4 << 20 ) /* (SSC) Selected Receive/Transmit Frame Sync Signal: Driver High during data transfer */ +#define AT91C_SSC_FSOS_TOGGLE ( 0x5 << 20 ) /* (SSC) Selected Receive/Transmit Frame Sync Signal: Toggling at each start of data transfer */ +#define AT91C_SSC_FSEDGE ( 0x1 << 24 ) /* (SSC) Frame Sync Edge Detection */ +/* -------- SSC_TCMR : (SSC Offset: 0x18) SSC Transmit Clock Mode Register -------- */ +/* -------- SSC_TFMR : (SSC Offset: 0x1c) SSC Transmit Frame Mode Register -------- */ +#define AT91C_SSC_DATDEF ( 0x1 << 5 ) /* (SSC) Data Default Value */ +#define AT91C_SSC_FSDEN ( 0x1 << 23 ) /* (SSC) Frame Sync Data Enable */ +/* -------- SSC_SR : (SSC Offset: 0x40) SSC Status Register -------- */ +#define AT91C_SSC_TXRDY ( 0x1 << 0 ) /* (SSC) Transmit Ready */ +#define AT91C_SSC_TXEMPTY ( 0x1 << 1 ) /* (SSC) Transmit Empty */ +#define AT91C_SSC_ENDTX ( 0x1 << 2 ) /* (SSC) End Of Transmission */ +#define AT91C_SSC_TXBUFE ( 0x1 << 3 ) /* (SSC) Transmit Buffer Empty */ +#define AT91C_SSC_RXRDY ( 0x1 << 4 ) /* (SSC) Receive Ready */ +#define AT91C_SSC_OVRUN ( 0x1 << 5 ) /* (SSC) Receive Overrun */ +#define AT91C_SSC_ENDRX ( 0x1 << 6 ) /* (SSC) End of Reception */ +#define AT91C_SSC_RXBUFF ( 0x1 << 7 ) /* (SSC) Receive Buffer Full */ +#define AT91C_SSC_TXSYN ( 0x1 << 10 ) /* (SSC) Transmit Sync */ +#define AT91C_SSC_RXSYN ( 0x1 << 11 ) /* (SSC) Receive Sync */ +#define AT91C_SSC_TXENA ( 0x1 << 16 ) /* (SSC) Transmit Enable */ +#define AT91C_SSC_RXENA ( 0x1 << 17 ) /* (SSC) Receive Enable */ +/* -------- SSC_IER : (SSC Offset: 0x44) SSC Interrupt Enable Register -------- */ +/* -------- SSC_IDR : (SSC Offset: 0x48) SSC Interrupt Disable Register -------- */ +/* -------- SSC_IMR : (SSC Offset: 0x4c) SSC Interrupt Mask Register -------- */ -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Two-wire Interface -// ***************************************************************************** -// *** Register offset in AT91S_TWI structure *** -#define TWI_CR ( 0) // Control Register -#define TWI_MMR ( 4) // Master Mode Register -#define TWI_IADR (12) // Internal Address Register -#define TWI_CWGR (16) // Clock Waveform Generator Register -#define TWI_SR (32) // Status Register -#define TWI_IER (36) // Interrupt Enable Register -#define TWI_IDR (40) // Interrupt Disable Register -#define TWI_IMR (44) // Interrupt Mask Register -#define TWI_RHR (48) // Receive Holding Register -#define TWI_THR (52) // Transmit Holding Register -// -------- TWI_CR : (TWI Offset: 0x0) TWI Control Register -------- -#define AT91C_TWI_START (0x1 << 0) // (TWI) Send a START Condition -#define AT91C_TWI_STOP (0x1 << 1) // (TWI) Send a STOP Condition -#define AT91C_TWI_MSEN (0x1 << 2) // (TWI) TWI Master Transfer Enabled -#define AT91C_TWI_MSDIS (0x1 << 3) // (TWI) TWI Master Transfer Disabled -#define AT91C_TWI_SWRST (0x1 << 7) // (TWI) Software Reset -// -------- TWI_MMR : (TWI Offset: 0x4) TWI Master Mode Register -------- -#define AT91C_TWI_IADRSZ (0x3 << 8) // (TWI) Internal Device Address Size -#define AT91C_TWI_IADRSZ_NO (0x0 << 8) // (TWI) No internal device address -#define AT91C_TWI_IADRSZ_1_BYTE (0x1 << 8) // (TWI) One-byte internal device address -#define AT91C_TWI_IADRSZ_2_BYTE (0x2 << 8) // (TWI) Two-byte internal device address -#define AT91C_TWI_IADRSZ_3_BYTE (0x3 << 8) // (TWI) Three-byte internal device address -#define AT91C_TWI_MREAD (0x1 << 12) // (TWI) Master Read Direction -#define AT91C_TWI_DADR (0x7F << 16) // (TWI) Device Address -// -------- TWI_CWGR : (TWI Offset: 0x10) TWI Clock Waveform Generator Register -------- -#define AT91C_TWI_CLDIV (0xFF << 0) // (TWI) Clock Low Divider -#define AT91C_TWI_CHDIV (0xFF << 8) // (TWI) Clock High Divider -#define AT91C_TWI_CKDIV (0x7 << 16) // (TWI) Clock Divider -// -------- TWI_SR : (TWI Offset: 0x20) TWI Status Register -------- -#define AT91C_TWI_TXCOMP (0x1 << 0) // (TWI) Transmission Completed -#define AT91C_TWI_RXRDY (0x1 << 1) // (TWI) Receive holding register ReaDY -#define AT91C_TWI_TXRDY (0x1 << 2) // (TWI) Transmit holding register ReaDY -#define AT91C_TWI_OVRE (0x1 << 6) // (TWI) Overrun Error -#define AT91C_TWI_UNRE (0x1 << 7) // (TWI) Underrun Error -#define AT91C_TWI_NACK (0x1 << 8) // (TWI) Not Acknowledged -// -------- TWI_IER : (TWI Offset: 0x24) TWI Interrupt Enable Register -------- -// -------- TWI_IDR : (TWI Offset: 0x28) TWI Interrupt Disable Register -------- -// -------- TWI_IMR : (TWI Offset: 0x2c) TWI Interrupt Mask Register -------- +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR Two-wire Interface */ +/* ***************************************************************************** */ +/* *** Register offset in AT91S_TWI structure *** */ +#define TWI_CR ( 0 ) /* Control Register */ +#define TWI_MMR ( 4 ) /* Master Mode Register */ +#define TWI_IADR ( 12 ) /* Internal Address Register */ +#define TWI_CWGR ( 16 ) /* Clock Waveform Generator Register */ +#define TWI_SR ( 32 ) /* Status Register */ +#define TWI_IER ( 36 ) /* Interrupt Enable Register */ +#define TWI_IDR ( 40 ) /* Interrupt Disable Register */ +#define TWI_IMR ( 44 ) /* Interrupt Mask Register */ +#define TWI_RHR ( 48 ) /* Receive Holding Register */ +#define TWI_THR ( 52 ) /* Transmit Holding Register */ +/* -------- TWI_CR : (TWI Offset: 0x0) TWI Control Register -------- */ +#define AT91C_TWI_START ( 0x1 << 0 ) /* (TWI) Send a START Condition */ +#define AT91C_TWI_STOP ( 0x1 << 1 ) /* (TWI) Send a STOP Condition */ +#define AT91C_TWI_MSEN ( 0x1 << 2 ) /* (TWI) TWI Master Transfer Enabled */ +#define AT91C_TWI_MSDIS ( 0x1 << 3 ) /* (TWI) TWI Master Transfer Disabled */ +#define AT91C_TWI_SWRST ( 0x1 << 7 ) /* (TWI) Software Reset */ +/* -------- TWI_MMR : (TWI Offset: 0x4) TWI Master Mode Register -------- */ +#define AT91C_TWI_IADRSZ ( 0x3 << 8 ) /* (TWI) Internal Device Address Size */ +#define AT91C_TWI_IADRSZ_NO ( 0x0 << 8 ) /* (TWI) No internal device address */ +#define AT91C_TWI_IADRSZ_1_BYTE ( 0x1 << 8 ) /* (TWI) One-byte internal device address */ +#define AT91C_TWI_IADRSZ_2_BYTE ( 0x2 << 8 ) /* (TWI) Two-byte internal device address */ +#define AT91C_TWI_IADRSZ_3_BYTE ( 0x3 << 8 ) /* (TWI) Three-byte internal device address */ +#define AT91C_TWI_MREAD ( 0x1 << 12 ) /* (TWI) Master Read Direction */ +#define AT91C_TWI_DADR ( 0x7F << 16 ) /* (TWI) Device Address */ +/* -------- TWI_CWGR : (TWI Offset: 0x10) TWI Clock Waveform Generator Register -------- */ +#define AT91C_TWI_CLDIV ( 0xFF << 0 ) /* (TWI) Clock Low Divider */ +#define AT91C_TWI_CHDIV ( 0xFF << 8 ) /* (TWI) Clock High Divider */ +#define AT91C_TWI_CKDIV ( 0x7 << 16 ) /* (TWI) Clock Divider */ +/* -------- TWI_SR : (TWI Offset: 0x20) TWI Status Register -------- */ +#define AT91C_TWI_TXCOMP ( 0x1 << 0 ) /* (TWI) Transmission Completed */ +#define AT91C_TWI_RXRDY ( 0x1 << 1 ) /* (TWI) Receive holding register ReaDY */ +#define AT91C_TWI_TXRDY ( 0x1 << 2 ) /* (TWI) Transmit holding register ReaDY */ +#define AT91C_TWI_OVRE ( 0x1 << 6 ) /* (TWI) Overrun Error */ +#define AT91C_TWI_UNRE ( 0x1 << 7 ) /* (TWI) Underrun Error */ +#define AT91C_TWI_NACK ( 0x1 << 8 ) /* (TWI) Not Acknowledged */ +/* -------- TWI_IER : (TWI Offset: 0x24) TWI Interrupt Enable Register -------- */ +/* -------- TWI_IDR : (TWI Offset: 0x28) TWI Interrupt Disable Register -------- */ +/* -------- TWI_IMR : (TWI Offset: 0x2c) TWI Interrupt Mask Register -------- */ -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR PWMC Channel Interface -// ***************************************************************************** -// *** Register offset in AT91S_PWMC_CH structure *** -#define PWMC_CMR ( 0) // Channel Mode Register -#define PWMC_CDTYR ( 4) // Channel Duty Cycle Register -#define PWMC_CPRDR ( 8) // Channel Period Register -#define PWMC_CCNTR (12) // Channel Counter Register -#define PWMC_CUPDR (16) // Channel Update Register -#define PWMC_Reserved (20) // Reserved -// -------- PWMC_CMR : (PWMC_CH Offset: 0x0) PWMC Channel Mode Register -------- -#define AT91C_PWMC_CPRE (0xF << 0) // (PWMC_CH) Channel Pre-scaler : PWMC_CLKx -#define AT91C_PWMC_CPRE_MCK (0x0) // (PWMC_CH) -#define AT91C_PWMC_CPRE_MCKA (0xB) // (PWMC_CH) -#define AT91C_PWMC_CPRE_MCKB (0xC) // (PWMC_CH) -#define AT91C_PWMC_CALG (0x1 << 8) // (PWMC_CH) Channel Alignment -#define AT91C_PWMC_CPOL (0x1 << 9) // (PWMC_CH) Channel Polarity -#define AT91C_PWMC_CPD (0x1 << 10) // (PWMC_CH) Channel Update Period -// -------- PWMC_CDTYR : (PWMC_CH Offset: 0x4) PWMC Channel Duty Cycle Register -------- -#define AT91C_PWMC_CDTY (0x0 << 0) // (PWMC_CH) Channel Duty Cycle -// -------- PWMC_CPRDR : (PWMC_CH Offset: 0x8) PWMC Channel Period Register -------- -#define AT91C_PWMC_CPRD (0x0 << 0) // (PWMC_CH) Channel Period -// -------- PWMC_CCNTR : (PWMC_CH Offset: 0xc) PWMC Channel Counter Register -------- -#define AT91C_PWMC_CCNT (0x0 << 0) // (PWMC_CH) Channel Counter -// -------- PWMC_CUPDR : (PWMC_CH Offset: 0x10) PWMC Channel Update Register -------- -#define AT91C_PWMC_CUPD (0x0 << 0) // (PWMC_CH) Channel Update +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR PWMC Channel Interface */ +/* ***************************************************************************** */ +/* *** Register offset in AT91S_PWMC_CH structure *** */ +#define PWMC_CMR ( 0 ) /* Channel Mode Register */ +#define PWMC_CDTYR ( 4 ) /* Channel Duty Cycle Register */ +#define PWMC_CPRDR ( 8 ) /* Channel Period Register */ +#define PWMC_CCNTR ( 12 ) /* Channel Counter Register */ +#define PWMC_CUPDR ( 16 ) /* Channel Update Register */ +#define PWMC_Reserved ( 20 ) /* Reserved */ +/* -------- PWMC_CMR : (PWMC_CH Offset: 0x0) PWMC Channel Mode Register -------- */ +#define AT91C_PWMC_CPRE ( 0xF << 0 ) /* (PWMC_CH) Channel Pre-scaler : PWMC_CLKx */ +#define AT91C_PWMC_CPRE_MCK ( 0x0 ) /* (PWMC_CH) */ +#define AT91C_PWMC_CPRE_MCKA ( 0xB ) /* (PWMC_CH) */ +#define AT91C_PWMC_CPRE_MCKB ( 0xC ) /* (PWMC_CH) */ +#define AT91C_PWMC_CALG ( 0x1 << 8 ) /* (PWMC_CH) Channel Alignment */ +#define AT91C_PWMC_CPOL ( 0x1 << 9 ) /* (PWMC_CH) Channel Polarity */ +#define AT91C_PWMC_CPD ( 0x1 << 10 ) /* (PWMC_CH) Channel Update Period */ +/* -------- PWMC_CDTYR : (PWMC_CH Offset: 0x4) PWMC Channel Duty Cycle Register -------- */ +#define AT91C_PWMC_CDTY ( 0x0 << 0 ) /* (PWMC_CH) Channel Duty Cycle */ +/* -------- PWMC_CPRDR : (PWMC_CH Offset: 0x8) PWMC Channel Period Register -------- */ +#define AT91C_PWMC_CPRD ( 0x0 << 0 ) /* (PWMC_CH) Channel Period */ +/* -------- PWMC_CCNTR : (PWMC_CH Offset: 0xc) PWMC Channel Counter Register -------- */ +#define AT91C_PWMC_CCNT ( 0x0 << 0 ) /* (PWMC_CH) Channel Counter */ +/* -------- PWMC_CUPDR : (PWMC_CH Offset: 0x10) PWMC Channel Update Register -------- */ +#define AT91C_PWMC_CUPD ( 0x0 << 0 ) /* (PWMC_CH) Channel Update */ -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Pulse Width Modulation Controller Interface -// ***************************************************************************** -// *** Register offset in AT91S_PWMC structure *** -#define PWMC_MR ( 0) // PWMC Mode Register -#define PWMC_ENA ( 4) // PWMC Enable Register -#define PWMC_DIS ( 8) // PWMC Disable Register -#define PWMC_SR (12) // PWMC Status Register -#define PWMC_IER (16) // PWMC Interrupt Enable Register -#define PWMC_IDR (20) // PWMC Interrupt Disable Register -#define PWMC_IMR (24) // PWMC Interrupt Mask Register -#define PWMC_ISR (28) // PWMC Interrupt Status Register -#define PWMC_VR (252) // PWMC Version Register -#define PWMC_CH (512) // PWMC Channel -// -------- PWMC_MR : (PWMC Offset: 0x0) PWMC Mode Register -------- -#define AT91C_PWMC_DIVA (0xFF << 0) // (PWMC) CLKA divide factor. -#define AT91C_PWMC_PREA (0xF << 8) // (PWMC) Divider Input Clock Prescaler A -#define AT91C_PWMC_PREA_MCK (0x0 << 8) // (PWMC) -#define AT91C_PWMC_DIVB (0xFF << 16) // (PWMC) CLKB divide factor. -#define AT91C_PWMC_PREB (0xF << 24) // (PWMC) Divider Input Clock Prescaler B -#define AT91C_PWMC_PREB_MCK (0x0 << 24) // (PWMC) -// -------- PWMC_ENA : (PWMC Offset: 0x4) PWMC Enable Register -------- -#define AT91C_PWMC_CHID0 (0x1 << 0) // (PWMC) Channel ID 0 -#define AT91C_PWMC_CHID1 (0x1 << 1) // (PWMC) Channel ID 1 -#define AT91C_PWMC_CHID2 (0x1 << 2) // (PWMC) Channel ID 2 -#define AT91C_PWMC_CHID3 (0x1 << 3) // (PWMC) Channel ID 3 -// -------- PWMC_DIS : (PWMC Offset: 0x8) PWMC Disable Register -------- -// -------- PWMC_SR : (PWMC Offset: 0xc) PWMC Status Register -------- -// -------- PWMC_IER : (PWMC Offset: 0x10) PWMC Interrupt Enable Register -------- -// -------- PWMC_IDR : (PWMC Offset: 0x14) PWMC Interrupt Disable Register -------- -// -------- PWMC_IMR : (PWMC Offset: 0x18) PWMC Interrupt Mask Register -------- -// -------- PWMC_ISR : (PWMC Offset: 0x1c) PWMC Interrupt Status Register -------- +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR Pulse Width Modulation Controller Interface */ +/* ***************************************************************************** */ +/* *** Register offset in AT91S_PWMC structure *** */ +#define PWMC_MR ( 0 ) /* PWMC Mode Register */ +#define PWMC_ENA ( 4 ) /* PWMC Enable Register */ +#define PWMC_DIS ( 8 ) /* PWMC Disable Register */ +#define PWMC_SR ( 12 ) /* PWMC Status Register */ +#define PWMC_IER ( 16 ) /* PWMC Interrupt Enable Register */ +#define PWMC_IDR ( 20 ) /* PWMC Interrupt Disable Register */ +#define PWMC_IMR ( 24 ) /* PWMC Interrupt Mask Register */ +#define PWMC_ISR ( 28 ) /* PWMC Interrupt Status Register */ +#define PWMC_VR ( 252 ) /* PWMC Version Register */ +#define PWMC_CH ( 512 ) /* PWMC Channel */ +/* -------- PWMC_MR : (PWMC Offset: 0x0) PWMC Mode Register -------- */ +#define AT91C_PWMC_DIVA ( 0xFF << 0 ) /* (PWMC) CLKA divide factor. */ +#define AT91C_PWMC_PREA ( 0xF << 8 ) /* (PWMC) Divider Input Clock Prescaler A */ +#define AT91C_PWMC_PREA_MCK ( 0x0 << 8 ) /* (PWMC) */ +#define AT91C_PWMC_DIVB ( 0xFF << 16 ) /* (PWMC) CLKB divide factor. */ +#define AT91C_PWMC_PREB ( 0xF << 24 ) /* (PWMC) Divider Input Clock Prescaler B */ +#define AT91C_PWMC_PREB_MCK ( 0x0 << 24 ) /* (PWMC) */ +/* -------- PWMC_ENA : (PWMC Offset: 0x4) PWMC Enable Register -------- */ +#define AT91C_PWMC_CHID0 ( 0x1 << 0 ) /* (PWMC) Channel ID 0 */ +#define AT91C_PWMC_CHID1 ( 0x1 << 1 ) /* (PWMC) Channel ID 1 */ +#define AT91C_PWMC_CHID2 ( 0x1 << 2 ) /* (PWMC) Channel ID 2 */ +#define AT91C_PWMC_CHID3 ( 0x1 << 3 ) /* (PWMC) Channel ID 3 */ +/* -------- PWMC_DIS : (PWMC Offset: 0x8) PWMC Disable Register -------- */ +/* -------- PWMC_SR : (PWMC Offset: 0xc) PWMC Status Register -------- */ +/* -------- PWMC_IER : (PWMC Offset: 0x10) PWMC Interrupt Enable Register -------- */ +/* -------- PWMC_IDR : (PWMC Offset: 0x14) PWMC Interrupt Disable Register -------- */ +/* -------- PWMC_IMR : (PWMC Offset: 0x18) PWMC Interrupt Mask Register -------- */ +/* -------- PWMC_ISR : (PWMC Offset: 0x1c) PWMC Interrupt Status Register -------- */ -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR USB Device Interface -// ***************************************************************************** -// *** Register offset in AT91S_UDP structure *** -#define UDP_NUM ( 0) // Frame Number Register -#define UDP_GLBSTATE ( 4) // Global State Register -#define UDP_FADDR ( 8) // Function Address Register -#define UDP_IER (16) // Interrupt Enable Register -#define UDP_IDR (20) // Interrupt Disable Register -#define UDP_IMR (24) // Interrupt Mask Register -#define UDP_ISR (28) // Interrupt Status Register -#define UDP_ICR (32) // Interrupt Clear Register -#define UDP_RSTEP (40) // Reset Endpoint Register -#define UDP_CSR (48) // Endpoint Control and Status Register -#define UDP_FDR (80) // Endpoint FIFO Data Register -#define UDP_TXVC (116) // Transceiver Control Register -// -------- UDP_FRM_NUM : (UDP Offset: 0x0) USB Frame Number Register -------- -#define AT91C_UDP_FRM_NUM (0x7FF << 0) // (UDP) Frame Number as Defined in the Packet Field Formats -#define AT91C_UDP_FRM_ERR (0x1 << 16) // (UDP) Frame Error -#define AT91C_UDP_FRM_OK (0x1 << 17) // (UDP) Frame OK -// -------- UDP_GLB_STATE : (UDP Offset: 0x4) USB Global State Register -------- -#define AT91C_UDP_FADDEN (0x1 << 0) // (UDP) Function Address Enable -#define AT91C_UDP_CONFG (0x1 << 1) // (UDP) Configured -#define AT91C_UDP_ESR (0x1 << 2) // (UDP) Enable Send Resume -#define AT91C_UDP_RSMINPR (0x1 << 3) // (UDP) A Resume Has Been Sent to the Host -#define AT91C_UDP_RMWUPE (0x1 << 4) // (UDP) Remote Wake Up Enable -// -------- UDP_FADDR : (UDP Offset: 0x8) USB Function Address Register -------- -#define AT91C_UDP_FADD (0xFF << 0) // (UDP) Function Address Value -#define AT91C_UDP_FEN (0x1 << 8) // (UDP) Function Enable -// -------- UDP_IER : (UDP Offset: 0x10) USB Interrupt Enable Register -------- -#define AT91C_UDP_EPINT0 (0x1 << 0) // (UDP) Endpoint 0 Interrupt -#define AT91C_UDP_EPINT1 (0x1 << 1) // (UDP) Endpoint 0 Interrupt -#define AT91C_UDP_EPINT2 (0x1 << 2) // (UDP) Endpoint 2 Interrupt -#define AT91C_UDP_EPINT3 (0x1 << 3) // (UDP) Endpoint 3 Interrupt -#define AT91C_UDP_EPINT4 (0x1 << 4) // (UDP) Endpoint 4 Interrupt -#define AT91C_UDP_EPINT5 (0x1 << 5) // (UDP) Endpoint 5 Interrupt -#define AT91C_UDP_RXSUSP (0x1 << 8) // (UDP) USB Suspend Interrupt -#define AT91C_UDP_RXRSM (0x1 << 9) // (UDP) USB Resume Interrupt -#define AT91C_UDP_EXTRSM (0x1 << 10) // (UDP) USB External Resume Interrupt -#define AT91C_UDP_SOFINT (0x1 << 11) // (UDP) USB Start Of frame Interrupt -#define AT91C_UDP_WAKEUP (0x1 << 13) // (UDP) USB Resume Interrupt -// -------- UDP_IDR : (UDP Offset: 0x14) USB Interrupt Disable Register -------- -// -------- UDP_IMR : (UDP Offset: 0x18) USB Interrupt Mask Register -------- -// -------- UDP_ISR : (UDP Offset: 0x1c) USB Interrupt Status Register -------- -#define AT91C_UDP_ENDBUSRES (0x1 << 12) // (UDP) USB End Of Bus Reset Interrupt -// -------- UDP_ICR : (UDP Offset: 0x20) USB Interrupt Clear Register -------- -// -------- UDP_RST_EP : (UDP Offset: 0x28) USB Reset Endpoint Register -------- -#define AT91C_UDP_EP0 (0x1 << 0) // (UDP) Reset Endpoint 0 -#define AT91C_UDP_EP1 (0x1 << 1) // (UDP) Reset Endpoint 1 -#define AT91C_UDP_EP2 (0x1 << 2) // (UDP) Reset Endpoint 2 -#define AT91C_UDP_EP3 (0x1 << 3) // (UDP) Reset Endpoint 3 -#define AT91C_UDP_EP4 (0x1 << 4) // (UDP) Reset Endpoint 4 -#define AT91C_UDP_EP5 (0x1 << 5) // (UDP) Reset Endpoint 5 -// -------- UDP_CSR : (UDP Offset: 0x30) USB Endpoint Control and Status Register -------- -#define AT91C_UDP_TXCOMP (0x1 << 0) // (UDP) Generates an IN packet with data previously written in the DPR -#define AT91C_UDP_RX_DATA_BK0 (0x1 << 1) // (UDP) Receive Data Bank 0 -#define AT91C_UDP_RXSETUP (0x1 << 2) // (UDP) Sends STALL to the Host (Control endpoints) -#define AT91C_UDP_ISOERROR (0x1 << 3) // (UDP) Isochronous error (Isochronous endpoints) -#define AT91C_UDP_TXPKTRDY (0x1 << 4) // (UDP) Transmit Packet Ready -#define AT91C_UDP_FORCESTALL (0x1 << 5) // (UDP) Force Stall (used by Control, Bulk and Isochronous endpoints). -#define AT91C_UDP_RX_DATA_BK1 (0x1 << 6) // (UDP) Receive Data Bank 1 (only used by endpoints with ping-pong attributes). -#define AT91C_UDP_DIR (0x1 << 7) // (UDP) Transfer Direction -#define AT91C_UDP_EPTYPE (0x7 << 8) // (UDP) Endpoint type -#define AT91C_UDP_EPTYPE_CTRL (0x0 << 8) // (UDP) Control -#define AT91C_UDP_EPTYPE_ISO_OUT (0x1 << 8) // (UDP) Isochronous OUT -#define AT91C_UDP_EPTYPE_BULK_OUT (0x2 << 8) // (UDP) Bulk OUT -#define AT91C_UDP_EPTYPE_INT_OUT (0x3 << 8) // (UDP) Interrupt OUT -#define AT91C_UDP_EPTYPE_ISO_IN (0x5 << 8) // (UDP) Isochronous IN -#define AT91C_UDP_EPTYPE_BULK_IN (0x6 << 8) // (UDP) Bulk IN -#define AT91C_UDP_EPTYPE_INT_IN (0x7 << 8) // (UDP) Interrupt IN -#define AT91C_UDP_DTGLE (0x1 << 11) // (UDP) Data Toggle -#define AT91C_UDP_EPEDS (0x1 << 15) // (UDP) Endpoint Enable Disable -#define AT91C_UDP_RXBYTECNT (0x7FF << 16) // (UDP) Number Of Bytes Available in the FIFO -// -------- UDP_TXVC : (UDP Offset: 0x74) Transceiver Control Register -------- -#define AT91C_UDP_TXVDIS (0x1 << 8) // (UDP) -#define AT91C_UDP_PUON (0x1 << 9) // (UDP) Pull-up ON +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR USB Device Interface */ +/* ***************************************************************************** */ +/* *** Register offset in AT91S_UDP structure *** */ +#define UDP_NUM ( 0 ) /* Frame Number Register */ +#define UDP_GLBSTATE ( 4 ) /* Global State Register */ +#define UDP_FADDR ( 8 ) /* Function Address Register */ +#define UDP_IER ( 16 ) /* Interrupt Enable Register */ +#define UDP_IDR ( 20 ) /* Interrupt Disable Register */ +#define UDP_IMR ( 24 ) /* Interrupt Mask Register */ +#define UDP_ISR ( 28 ) /* Interrupt Status Register */ +#define UDP_ICR ( 32 ) /* Interrupt Clear Register */ +#define UDP_RSTEP ( 40 ) /* Reset Endpoint Register */ +#define UDP_CSR ( 48 ) /* Endpoint Control and Status Register */ +#define UDP_FDR ( 80 ) /* Endpoint FIFO Data Register */ +#define UDP_TXVC ( 116 ) /* Transceiver Control Register */ +/* -------- UDP_FRM_NUM : (UDP Offset: 0x0) USB Frame Number Register -------- */ +#define AT91C_UDP_FRM_NUM ( 0x7FF << 0 ) /* (UDP) Frame Number as Defined in the Packet Field Formats */ +#define AT91C_UDP_FRM_ERR ( 0x1 << 16 ) /* (UDP) Frame Error */ +#define AT91C_UDP_FRM_OK ( 0x1 << 17 ) /* (UDP) Frame OK */ +/* -------- UDP_GLB_STATE : (UDP Offset: 0x4) USB Global State Register -------- */ +#define AT91C_UDP_FADDEN ( 0x1 << 0 ) /* (UDP) Function Address Enable */ +#define AT91C_UDP_CONFG ( 0x1 << 1 ) /* (UDP) Configured */ +#define AT91C_UDP_ESR ( 0x1 << 2 ) /* (UDP) Enable Send Resume */ +#define AT91C_UDP_RSMINPR ( 0x1 << 3 ) /* (UDP) A Resume Has Been Sent to the Host */ +#define AT91C_UDP_RMWUPE ( 0x1 << 4 ) /* (UDP) Remote Wake Up Enable */ +/* -------- UDP_FADDR : (UDP Offset: 0x8) USB Function Address Register -------- */ +#define AT91C_UDP_FADD ( 0xFF << 0 ) /* (UDP) Function Address Value */ +#define AT91C_UDP_FEN ( 0x1 << 8 ) /* (UDP) Function Enable */ +/* -------- UDP_IER : (UDP Offset: 0x10) USB Interrupt Enable Register -------- */ +#define AT91C_UDP_EPINT0 ( 0x1 << 0 ) /* (UDP) Endpoint 0 Interrupt */ +#define AT91C_UDP_EPINT1 ( 0x1 << 1 ) /* (UDP) Endpoint 0 Interrupt */ +#define AT91C_UDP_EPINT2 ( 0x1 << 2 ) /* (UDP) Endpoint 2 Interrupt */ +#define AT91C_UDP_EPINT3 ( 0x1 << 3 ) /* (UDP) Endpoint 3 Interrupt */ +#define AT91C_UDP_EPINT4 ( 0x1 << 4 ) /* (UDP) Endpoint 4 Interrupt */ +#define AT91C_UDP_EPINT5 ( 0x1 << 5 ) /* (UDP) Endpoint 5 Interrupt */ +#define AT91C_UDP_RXSUSP ( 0x1 << 8 ) /* (UDP) USB Suspend Interrupt */ +#define AT91C_UDP_RXRSM ( 0x1 << 9 ) /* (UDP) USB Resume Interrupt */ +#define AT91C_UDP_EXTRSM ( 0x1 << 10 ) /* (UDP) USB External Resume Interrupt */ +#define AT91C_UDP_SOFINT ( 0x1 << 11 ) /* (UDP) USB Start Of frame Interrupt */ +#define AT91C_UDP_WAKEUP ( 0x1 << 13 ) /* (UDP) USB Resume Interrupt */ +/* -------- UDP_IDR : (UDP Offset: 0x14) USB Interrupt Disable Register -------- */ +/* -------- UDP_IMR : (UDP Offset: 0x18) USB Interrupt Mask Register -------- */ +/* -------- UDP_ISR : (UDP Offset: 0x1c) USB Interrupt Status Register -------- */ +#define AT91C_UDP_ENDBUSRES ( 0x1 << 12 ) /* (UDP) USB End Of Bus Reset Interrupt */ +/* -------- UDP_ICR : (UDP Offset: 0x20) USB Interrupt Clear Register -------- */ +/* -------- UDP_RST_EP : (UDP Offset: 0x28) USB Reset Endpoint Register -------- */ +#define AT91C_UDP_EP0 ( 0x1 << 0 ) /* (UDP) Reset Endpoint 0 */ +#define AT91C_UDP_EP1 ( 0x1 << 1 ) /* (UDP) Reset Endpoint 1 */ +#define AT91C_UDP_EP2 ( 0x1 << 2 ) /* (UDP) Reset Endpoint 2 */ +#define AT91C_UDP_EP3 ( 0x1 << 3 ) /* (UDP) Reset Endpoint 3 */ +#define AT91C_UDP_EP4 ( 0x1 << 4 ) /* (UDP) Reset Endpoint 4 */ +#define AT91C_UDP_EP5 ( 0x1 << 5 ) /* (UDP) Reset Endpoint 5 */ +/* -------- UDP_CSR : (UDP Offset: 0x30) USB Endpoint Control and Status Register -------- */ +#define AT91C_UDP_TXCOMP ( 0x1 << 0 ) /* (UDP) Generates an IN packet with data previously written in the DPR */ +#define AT91C_UDP_RX_DATA_BK0 ( 0x1 << 1 ) /* (UDP) Receive Data Bank 0 */ +#define AT91C_UDP_RXSETUP ( 0x1 << 2 ) /* (UDP) Sends STALL to the Host (Control endpoints) */ +#define AT91C_UDP_ISOERROR ( 0x1 << 3 ) /* (UDP) Isochronous error (Isochronous endpoints) */ +#define AT91C_UDP_TXPKTRDY ( 0x1 << 4 ) /* (UDP) Transmit Packet Ready */ +#define AT91C_UDP_FORCESTALL ( 0x1 << 5 ) /* (UDP) Force Stall (used by Control, Bulk and Isochronous endpoints). */ +#define AT91C_UDP_RX_DATA_BK1 ( 0x1 << 6 ) /* (UDP) Receive Data Bank 1 (only used by endpoints with ping-pong attributes). */ +#define AT91C_UDP_DIR ( 0x1 << 7 ) /* (UDP) Transfer Direction */ +#define AT91C_UDP_EPTYPE ( 0x7 << 8 ) /* (UDP) Endpoint type */ +#define AT91C_UDP_EPTYPE_CTRL ( 0x0 << 8 ) /* (UDP) Control */ +#define AT91C_UDP_EPTYPE_ISO_OUT ( 0x1 << 8 ) /* (UDP) Isochronous OUT */ +#define AT91C_UDP_EPTYPE_BULK_OUT ( 0x2 << 8 ) /* (UDP) Bulk OUT */ +#define AT91C_UDP_EPTYPE_INT_OUT ( 0x3 << 8 ) /* (UDP) Interrupt OUT */ +#define AT91C_UDP_EPTYPE_ISO_IN ( 0x5 << 8 ) /* (UDP) Isochronous IN */ +#define AT91C_UDP_EPTYPE_BULK_IN ( 0x6 << 8 ) /* (UDP) Bulk IN */ +#define AT91C_UDP_EPTYPE_INT_IN ( 0x7 << 8 ) /* (UDP) Interrupt IN */ +#define AT91C_UDP_DTGLE ( 0x1 << 11 ) /* (UDP) Data Toggle */ +#define AT91C_UDP_EPEDS ( 0x1 << 15 ) /* (UDP) Endpoint Enable Disable */ +#define AT91C_UDP_RXBYTECNT ( 0x7FF << 16 ) /* (UDP) Number Of Bytes Available in the FIFO */ +/* -------- UDP_TXVC : (UDP Offset: 0x74) Transceiver Control Register -------- */ +#define AT91C_UDP_TXVDIS ( 0x1 << 8 ) /* (UDP) */ +#define AT91C_UDP_PUON ( 0x1 << 9 ) /* (UDP) Pull-up ON */ -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Timer Counter Channel Interface -// ***************************************************************************** -// *** Register offset in AT91S_TC structure *** -#define TC_CCR ( 0) // Channel Control Register -#define TC_CMR ( 4) // Channel Mode Register (Capture Mode / Waveform Mode) -#define TC_CV (16) // Counter Value -#define TC_RA (20) // Register A -#define TC_RB (24) // Register B -#define TC_RC (28) // Register C -#define TC_SR (32) // Status Register -#define TC_IER (36) // Interrupt Enable Register -#define TC_IDR (40) // Interrupt Disable Register -#define TC_IMR (44) // Interrupt Mask Register -// -------- TC_CCR : (TC Offset: 0x0) TC Channel Control Register -------- -#define AT91C_TC_CLKEN (0x1 << 0) // (TC) Counter Clock Enable Command -#define AT91C_TC_CLKDIS (0x1 << 1) // (TC) Counter Clock Disable Command -#define AT91C_TC_SWTRG (0x1 << 2) // (TC) Software Trigger Command -// -------- TC_CMR : (TC Offset: 0x4) TC Channel Mode Register: Capture Mode / Waveform Mode -------- -#define AT91C_TC_CLKS (0x7 << 0) // (TC) Clock Selection -#define AT91C_TC_CLKS_TIMER_DIV1_CLOCK (0x0) // (TC) Clock selected: TIMER_DIV1_CLOCK -#define AT91C_TC_CLKS_TIMER_DIV2_CLOCK (0x1) // (TC) Clock selected: TIMER_DIV2_CLOCK -#define AT91C_TC_CLKS_TIMER_DIV3_CLOCK (0x2) // (TC) Clock selected: TIMER_DIV3_CLOCK -#define AT91C_TC_CLKS_TIMER_DIV4_CLOCK (0x3) // (TC) Clock selected: TIMER_DIV4_CLOCK -#define AT91C_TC_CLKS_TIMER_DIV5_CLOCK (0x4) // (TC) Clock selected: TIMER_DIV5_CLOCK -#define AT91C_TC_CLKS_XC0 (0x5) // (TC) Clock selected: XC0 -#define AT91C_TC_CLKS_XC1 (0x6) // (TC) Clock selected: XC1 -#define AT91C_TC_CLKS_XC2 (0x7) // (TC) Clock selected: XC2 -#define AT91C_TC_CLKI (0x1 << 3) // (TC) Clock Invert -#define AT91C_TC_BURST (0x3 << 4) // (TC) Burst Signal Selection -#define AT91C_TC_BURST_NONE (0x0 << 4) // (TC) The clock is not gated by an external signal -#define AT91C_TC_BURST_XC0 (0x1 << 4) // (TC) XC0 is ANDed with the selected clock -#define AT91C_TC_BURST_XC1 (0x2 << 4) // (TC) XC1 is ANDed with the selected clock -#define AT91C_TC_BURST_XC2 (0x3 << 4) // (TC) XC2 is ANDed with the selected clock -#define AT91C_TC_CPCSTOP (0x1 << 6) // (TC) Counter Clock Stopped with RC Compare -#define AT91C_TC_LDBSTOP (0x1 << 6) // (TC) Counter Clock Stopped with RB Loading -#define AT91C_TC_CPCDIS (0x1 << 7) // (TC) Counter Clock Disable with RC Compare -#define AT91C_TC_LDBDIS (0x1 << 7) // (TC) Counter Clock Disabled with RB Loading -#define AT91C_TC_ETRGEDG (0x3 << 8) // (TC) External Trigger Edge Selection -#define AT91C_TC_ETRGEDG_NONE (0x0 << 8) // (TC) Edge: None -#define AT91C_TC_ETRGEDG_RISING (0x1 << 8) // (TC) Edge: rising edge -#define AT91C_TC_ETRGEDG_FALLING (0x2 << 8) // (TC) Edge: falling edge -#define AT91C_TC_ETRGEDG_BOTH (0x3 << 8) // (TC) Edge: each edge -#define AT91C_TC_EEVTEDG (0x3 << 8) // (TC) External Event Edge Selection -#define AT91C_TC_EEVTEDG_NONE (0x0 << 8) // (TC) Edge: None -#define AT91C_TC_EEVTEDG_RISING (0x1 << 8) // (TC) Edge: rising edge -#define AT91C_TC_EEVTEDG_FALLING (0x2 << 8) // (TC) Edge: falling edge -#define AT91C_TC_EEVTEDG_BOTH (0x3 << 8) // (TC) Edge: each edge -#define AT91C_TC_EEVT (0x3 << 10) // (TC) External Event Selection -#define AT91C_TC_EEVT_TIOB (0x0 << 10) // (TC) Signal selected as external event: TIOB TIOB direction: input -#define AT91C_TC_EEVT_XC0 (0x1 << 10) // (TC) Signal selected as external event: XC0 TIOB direction: output -#define AT91C_TC_EEVT_XC1 (0x2 << 10) // (TC) Signal selected as external event: XC1 TIOB direction: output -#define AT91C_TC_EEVT_XC2 (0x3 << 10) // (TC) Signal selected as external event: XC2 TIOB direction: output -#define AT91C_TC_ABETRG (0x1 << 10) // (TC) TIOA or TIOB External Trigger Selection -#define AT91C_TC_ENETRG (0x1 << 12) // (TC) External Event Trigger enable -#define AT91C_TC_WAVESEL (0x3 << 13) // (TC) Waveform Selection -#define AT91C_TC_WAVESEL_UP (0x0 << 13) // (TC) UP mode without atomatic trigger on RC Compare -#define AT91C_TC_WAVESEL_UPDOWN (0x1 << 13) // (TC) UPDOWN mode without automatic trigger on RC Compare -#define AT91C_TC_WAVESEL_UP_AUTO (0x2 << 13) // (TC) UP mode with automatic trigger on RC Compare -#define AT91C_TC_WAVESEL_UPDOWN_AUTO (0x3 << 13) // (TC) UPDOWN mode with automatic trigger on RC Compare -#define AT91C_TC_CPCTRG (0x1 << 14) // (TC) RC Compare Trigger Enable -#define AT91C_TC_WAVE (0x1 << 15) // (TC) -#define AT91C_TC_ACPA (0x3 << 16) // (TC) RA Compare Effect on TIOA -#define AT91C_TC_ACPA_NONE (0x0 << 16) // (TC) Effect: none -#define AT91C_TC_ACPA_SET (0x1 << 16) // (TC) Effect: set -#define AT91C_TC_ACPA_CLEAR (0x2 << 16) // (TC) Effect: clear -#define AT91C_TC_ACPA_TOGGLE (0x3 << 16) // (TC) Effect: toggle -#define AT91C_TC_LDRA (0x3 << 16) // (TC) RA Loading Selection -#define AT91C_TC_LDRA_NONE (0x0 << 16) // (TC) Edge: None -#define AT91C_TC_LDRA_RISING (0x1 << 16) // (TC) Edge: rising edge of TIOA -#define AT91C_TC_LDRA_FALLING (0x2 << 16) // (TC) Edge: falling edge of TIOA -#define AT91C_TC_LDRA_BOTH (0x3 << 16) // (TC) Edge: each edge of TIOA -#define AT91C_TC_ACPC (0x3 << 18) // (TC) RC Compare Effect on TIOA -#define AT91C_TC_ACPC_NONE (0x0 << 18) // (TC) Effect: none -#define AT91C_TC_ACPC_SET (0x1 << 18) // (TC) Effect: set -#define AT91C_TC_ACPC_CLEAR (0x2 << 18) // (TC) Effect: clear -#define AT91C_TC_ACPC_TOGGLE (0x3 << 18) // (TC) Effect: toggle -#define AT91C_TC_LDRB (0x3 << 18) // (TC) RB Loading Selection -#define AT91C_TC_LDRB_NONE (0x0 << 18) // (TC) Edge: None -#define AT91C_TC_LDRB_RISING (0x1 << 18) // (TC) Edge: rising edge of TIOA -#define AT91C_TC_LDRB_FALLING (0x2 << 18) // (TC) Edge: falling edge of TIOA -#define AT91C_TC_LDRB_BOTH (0x3 << 18) // (TC) Edge: each edge of TIOA -#define AT91C_TC_AEEVT (0x3 << 20) // (TC) External Event Effect on TIOA -#define AT91C_TC_AEEVT_NONE (0x0 << 20) // (TC) Effect: none -#define AT91C_TC_AEEVT_SET (0x1 << 20) // (TC) Effect: set -#define AT91C_TC_AEEVT_CLEAR (0x2 << 20) // (TC) Effect: clear -#define AT91C_TC_AEEVT_TOGGLE (0x3 << 20) // (TC) Effect: toggle -#define AT91C_TC_ASWTRG (0x3 << 22) // (TC) Software Trigger Effect on TIOA -#define AT91C_TC_ASWTRG_NONE (0x0 << 22) // (TC) Effect: none -#define AT91C_TC_ASWTRG_SET (0x1 << 22) // (TC) Effect: set -#define AT91C_TC_ASWTRG_CLEAR (0x2 << 22) // (TC) Effect: clear -#define AT91C_TC_ASWTRG_TOGGLE (0x3 << 22) // (TC) Effect: toggle -#define AT91C_TC_BCPB (0x3 << 24) // (TC) RB Compare Effect on TIOB -#define AT91C_TC_BCPB_NONE (0x0 << 24) // (TC) Effect: none -#define AT91C_TC_BCPB_SET (0x1 << 24) // (TC) Effect: set -#define AT91C_TC_BCPB_CLEAR (0x2 << 24) // (TC) Effect: clear -#define AT91C_TC_BCPB_TOGGLE (0x3 << 24) // (TC) Effect: toggle -#define AT91C_TC_BCPC (0x3 << 26) // (TC) RC Compare Effect on TIOB -#define AT91C_TC_BCPC_NONE (0x0 << 26) // (TC) Effect: none -#define AT91C_TC_BCPC_SET (0x1 << 26) // (TC) Effect: set -#define AT91C_TC_BCPC_CLEAR (0x2 << 26) // (TC) Effect: clear -#define AT91C_TC_BCPC_TOGGLE (0x3 << 26) // (TC) Effect: toggle -#define AT91C_TC_BEEVT (0x3 << 28) // (TC) External Event Effect on TIOB -#define AT91C_TC_BEEVT_NONE (0x0 << 28) // (TC) Effect: none -#define AT91C_TC_BEEVT_SET (0x1 << 28) // (TC) Effect: set -#define AT91C_TC_BEEVT_CLEAR (0x2 << 28) // (TC) Effect: clear -#define AT91C_TC_BEEVT_TOGGLE (0x3 << 28) // (TC) Effect: toggle -#define AT91C_TC_BSWTRG (0x3 << 30) // (TC) Software Trigger Effect on TIOB -#define AT91C_TC_BSWTRG_NONE (0x0 << 30) // (TC) Effect: none -#define AT91C_TC_BSWTRG_SET (0x1 << 30) // (TC) Effect: set -#define AT91C_TC_BSWTRG_CLEAR (0x2 << 30) // (TC) Effect: clear -#define AT91C_TC_BSWTRG_TOGGLE (0x3 << 30) // (TC) Effect: toggle -// -------- TC_SR : (TC Offset: 0x20) TC Channel Status Register -------- -#define AT91C_TC_COVFS (0x1 << 0) // (TC) Counter Overflow -#define AT91C_TC_LOVRS (0x1 << 1) // (TC) Load Overrun -#define AT91C_TC_CPAS (0x1 << 2) // (TC) RA Compare -#define AT91C_TC_CPBS (0x1 << 3) // (TC) RB Compare -#define AT91C_TC_CPCS (0x1 << 4) // (TC) RC Compare -#define AT91C_TC_LDRAS (0x1 << 5) // (TC) RA Loading -#define AT91C_TC_LDRBS (0x1 << 6) // (TC) RB Loading -#define AT91C_TC_ETRGS (0x1 << 7) // (TC) External Trigger -#define AT91C_TC_CLKSTA (0x1 << 16) // (TC) Clock Enabling -#define AT91C_TC_MTIOA (0x1 << 17) // (TC) TIOA Mirror -#define AT91C_TC_MTIOB (0x1 << 18) // (TC) TIOA Mirror -// -------- TC_IER : (TC Offset: 0x24) TC Channel Interrupt Enable Register -------- -// -------- TC_IDR : (TC Offset: 0x28) TC Channel Interrupt Disable Register -------- -// -------- TC_IMR : (TC Offset: 0x2c) TC Channel Interrupt Mask Register -------- +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR Timer Counter Channel Interface */ +/* ***************************************************************************** */ +/* *** Register offset in AT91S_TC structure *** */ +#define TC_CCR ( 0 ) /* Channel Control Register */ +#define TC_CMR ( 4 ) /* Channel Mode Register (Capture Mode / Waveform Mode) */ +#define TC_CV ( 16 ) /* Counter Value */ +#define TC_RA ( 20 ) /* Register A */ +#define TC_RB ( 24 ) /* Register B */ +#define TC_RC ( 28 ) /* Register C */ +#define TC_SR ( 32 ) /* Status Register */ +#define TC_IER ( 36 ) /* Interrupt Enable Register */ +#define TC_IDR ( 40 ) /* Interrupt Disable Register */ +#define TC_IMR ( 44 ) /* Interrupt Mask Register */ +/* -------- TC_CCR : (TC Offset: 0x0) TC Channel Control Register -------- */ +#define AT91C_TC_CLKEN ( 0x1 << 0 ) /* (TC) Counter Clock Enable Command */ +#define AT91C_TC_CLKDIS ( 0x1 << 1 ) /* (TC) Counter Clock Disable Command */ +#define AT91C_TC_SWTRG ( 0x1 << 2 ) /* (TC) Software Trigger Command */ +/* -------- TC_CMR : (TC Offset: 0x4) TC Channel Mode Register: Capture Mode / Waveform Mode -------- */ +#define AT91C_TC_CLKS ( 0x7 << 0 ) /* (TC) Clock Selection */ +#define AT91C_TC_CLKS_TIMER_DIV1_CLOCK ( 0x0 ) /* (TC) Clock selected: TIMER_DIV1_CLOCK */ +#define AT91C_TC_CLKS_TIMER_DIV2_CLOCK ( 0x1 ) /* (TC) Clock selected: TIMER_DIV2_CLOCK */ +#define AT91C_TC_CLKS_TIMER_DIV3_CLOCK ( 0x2 ) /* (TC) Clock selected: TIMER_DIV3_CLOCK */ +#define AT91C_TC_CLKS_TIMER_DIV4_CLOCK ( 0x3 ) /* (TC) Clock selected: TIMER_DIV4_CLOCK */ +#define AT91C_TC_CLKS_TIMER_DIV5_CLOCK ( 0x4 ) /* (TC) Clock selected: TIMER_DIV5_CLOCK */ +#define AT91C_TC_CLKS_XC0 ( 0x5 ) /* (TC) Clock selected: XC0 */ +#define AT91C_TC_CLKS_XC1 ( 0x6 ) /* (TC) Clock selected: XC1 */ +#define AT91C_TC_CLKS_XC2 ( 0x7 ) /* (TC) Clock selected: XC2 */ +#define AT91C_TC_CLKI ( 0x1 << 3 ) /* (TC) Clock Invert */ +#define AT91C_TC_BURST ( 0x3 << 4 ) /* (TC) Burst Signal Selection */ +#define AT91C_TC_BURST_NONE ( 0x0 << 4 ) /* (TC) The clock is not gated by an external signal */ +#define AT91C_TC_BURST_XC0 ( 0x1 << 4 ) /* (TC) XC0 is ANDed with the selected clock */ +#define AT91C_TC_BURST_XC1 ( 0x2 << 4 ) /* (TC) XC1 is ANDed with the selected clock */ +#define AT91C_TC_BURST_XC2 ( 0x3 << 4 ) /* (TC) XC2 is ANDed with the selected clock */ +#define AT91C_TC_CPCSTOP ( 0x1 << 6 ) /* (TC) Counter Clock Stopped with RC Compare */ +#define AT91C_TC_LDBSTOP ( 0x1 << 6 ) /* (TC) Counter Clock Stopped with RB Loading */ +#define AT91C_TC_CPCDIS ( 0x1 << 7 ) /* (TC) Counter Clock Disable with RC Compare */ +#define AT91C_TC_LDBDIS ( 0x1 << 7 ) /* (TC) Counter Clock Disabled with RB Loading */ +#define AT91C_TC_ETRGEDG ( 0x3 << 8 ) /* (TC) External Trigger Edge Selection */ +#define AT91C_TC_ETRGEDG_NONE ( 0x0 << 8 ) /* (TC) Edge: None */ +#define AT91C_TC_ETRGEDG_RISING ( 0x1 << 8 ) /* (TC) Edge: rising edge */ +#define AT91C_TC_ETRGEDG_FALLING ( 0x2 << 8 ) /* (TC) Edge: falling edge */ +#define AT91C_TC_ETRGEDG_BOTH ( 0x3 << 8 ) /* (TC) Edge: each edge */ +#define AT91C_TC_EEVTEDG ( 0x3 << 8 ) /* (TC) External Event Edge Selection */ +#define AT91C_TC_EEVTEDG_NONE ( 0x0 << 8 ) /* (TC) Edge: None */ +#define AT91C_TC_EEVTEDG_RISING ( 0x1 << 8 ) /* (TC) Edge: rising edge */ +#define AT91C_TC_EEVTEDG_FALLING ( 0x2 << 8 ) /* (TC) Edge: falling edge */ +#define AT91C_TC_EEVTEDG_BOTH ( 0x3 << 8 ) /* (TC) Edge: each edge */ +#define AT91C_TC_EEVT ( 0x3 << 10 ) /* (TC) External Event Selection */ +#define AT91C_TC_EEVT_TIOB ( 0x0 << 10 ) /* (TC) Signal selected as external event: TIOB TIOB direction: input */ +#define AT91C_TC_EEVT_XC0 ( 0x1 << 10 ) /* (TC) Signal selected as external event: XC0 TIOB direction: output */ +#define AT91C_TC_EEVT_XC1 ( 0x2 << 10 ) /* (TC) Signal selected as external event: XC1 TIOB direction: output */ +#define AT91C_TC_EEVT_XC2 ( 0x3 << 10 ) /* (TC) Signal selected as external event: XC2 TIOB direction: output */ +#define AT91C_TC_ABETRG ( 0x1 << 10 ) /* (TC) TIOA or TIOB External Trigger Selection */ +#define AT91C_TC_ENETRG ( 0x1 << 12 ) /* (TC) External Event Trigger enable */ +#define AT91C_TC_WAVESEL ( 0x3 << 13 ) /* (TC) Waveform Selection */ +#define AT91C_TC_WAVESEL_UP ( 0x0 << 13 ) /* (TC) UP mode without atomatic trigger on RC Compare */ +#define AT91C_TC_WAVESEL_UPDOWN ( 0x1 << 13 ) /* (TC) UPDOWN mode without automatic trigger on RC Compare */ +#define AT91C_TC_WAVESEL_UP_AUTO ( 0x2 << 13 ) /* (TC) UP mode with automatic trigger on RC Compare */ +#define AT91C_TC_WAVESEL_UPDOWN_AUTO ( 0x3 << 13 ) /* (TC) UPDOWN mode with automatic trigger on RC Compare */ +#define AT91C_TC_CPCTRG ( 0x1 << 14 ) /* (TC) RC Compare Trigger Enable */ +#define AT91C_TC_WAVE ( 0x1 << 15 ) /* (TC) */ +#define AT91C_TC_ACPA ( 0x3 << 16 ) /* (TC) RA Compare Effect on TIOA */ +#define AT91C_TC_ACPA_NONE ( 0x0 << 16 ) /* (TC) Effect: none */ +#define AT91C_TC_ACPA_SET ( 0x1 << 16 ) /* (TC) Effect: set */ +#define AT91C_TC_ACPA_CLEAR ( 0x2 << 16 ) /* (TC) Effect: clear */ +#define AT91C_TC_ACPA_TOGGLE ( 0x3 << 16 ) /* (TC) Effect: toggle */ +#define AT91C_TC_LDRA ( 0x3 << 16 ) /* (TC) RA Loading Selection */ +#define AT91C_TC_LDRA_NONE ( 0x0 << 16 ) /* (TC) Edge: None */ +#define AT91C_TC_LDRA_RISING ( 0x1 << 16 ) /* (TC) Edge: rising edge of TIOA */ +#define AT91C_TC_LDRA_FALLING ( 0x2 << 16 ) /* (TC) Edge: falling edge of TIOA */ +#define AT91C_TC_LDRA_BOTH ( 0x3 << 16 ) /* (TC) Edge: each edge of TIOA */ +#define AT91C_TC_ACPC ( 0x3 << 18 ) /* (TC) RC Compare Effect on TIOA */ +#define AT91C_TC_ACPC_NONE ( 0x0 << 18 ) /* (TC) Effect: none */ +#define AT91C_TC_ACPC_SET ( 0x1 << 18 ) /* (TC) Effect: set */ +#define AT91C_TC_ACPC_CLEAR ( 0x2 << 18 ) /* (TC) Effect: clear */ +#define AT91C_TC_ACPC_TOGGLE ( 0x3 << 18 ) /* (TC) Effect: toggle */ +#define AT91C_TC_LDRB ( 0x3 << 18 ) /* (TC) RB Loading Selection */ +#define AT91C_TC_LDRB_NONE ( 0x0 << 18 ) /* (TC) Edge: None */ +#define AT91C_TC_LDRB_RISING ( 0x1 << 18 ) /* (TC) Edge: rising edge of TIOA */ +#define AT91C_TC_LDRB_FALLING ( 0x2 << 18 ) /* (TC) Edge: falling edge of TIOA */ +#define AT91C_TC_LDRB_BOTH ( 0x3 << 18 ) /* (TC) Edge: each edge of TIOA */ +#define AT91C_TC_AEEVT ( 0x3 << 20 ) /* (TC) External Event Effect on TIOA */ +#define AT91C_TC_AEEVT_NONE ( 0x0 << 20 ) /* (TC) Effect: none */ +#define AT91C_TC_AEEVT_SET ( 0x1 << 20 ) /* (TC) Effect: set */ +#define AT91C_TC_AEEVT_CLEAR ( 0x2 << 20 ) /* (TC) Effect: clear */ +#define AT91C_TC_AEEVT_TOGGLE ( 0x3 << 20 ) /* (TC) Effect: toggle */ +#define AT91C_TC_ASWTRG ( 0x3 << 22 ) /* (TC) Software Trigger Effect on TIOA */ +#define AT91C_TC_ASWTRG_NONE ( 0x0 << 22 ) /* (TC) Effect: none */ +#define AT91C_TC_ASWTRG_SET ( 0x1 << 22 ) /* (TC) Effect: set */ +#define AT91C_TC_ASWTRG_CLEAR ( 0x2 << 22 ) /* (TC) Effect: clear */ +#define AT91C_TC_ASWTRG_TOGGLE ( 0x3 << 22 ) /* (TC) Effect: toggle */ +#define AT91C_TC_BCPB ( 0x3 << 24 ) /* (TC) RB Compare Effect on TIOB */ +#define AT91C_TC_BCPB_NONE ( 0x0 << 24 ) /* (TC) Effect: none */ +#define AT91C_TC_BCPB_SET ( 0x1 << 24 ) /* (TC) Effect: set */ +#define AT91C_TC_BCPB_CLEAR ( 0x2 << 24 ) /* (TC) Effect: clear */ +#define AT91C_TC_BCPB_TOGGLE ( 0x3 << 24 ) /* (TC) Effect: toggle */ +#define AT91C_TC_BCPC ( 0x3 << 26 ) /* (TC) RC Compare Effect on TIOB */ +#define AT91C_TC_BCPC_NONE ( 0x0 << 26 ) /* (TC) Effect: none */ +#define AT91C_TC_BCPC_SET ( 0x1 << 26 ) /* (TC) Effect: set */ +#define AT91C_TC_BCPC_CLEAR ( 0x2 << 26 ) /* (TC) Effect: clear */ +#define AT91C_TC_BCPC_TOGGLE ( 0x3 << 26 ) /* (TC) Effect: toggle */ +#define AT91C_TC_BEEVT ( 0x3 << 28 ) /* (TC) External Event Effect on TIOB */ +#define AT91C_TC_BEEVT_NONE ( 0x0 << 28 ) /* (TC) Effect: none */ +#define AT91C_TC_BEEVT_SET ( 0x1 << 28 ) /* (TC) Effect: set */ +#define AT91C_TC_BEEVT_CLEAR ( 0x2 << 28 ) /* (TC) Effect: clear */ +#define AT91C_TC_BEEVT_TOGGLE ( 0x3 << 28 ) /* (TC) Effect: toggle */ +#define AT91C_TC_BSWTRG ( 0x3 << 30 ) /* (TC) Software Trigger Effect on TIOB */ +#define AT91C_TC_BSWTRG_NONE ( 0x0 << 30 ) /* (TC) Effect: none */ +#define AT91C_TC_BSWTRG_SET ( 0x1 << 30 ) /* (TC) Effect: set */ +#define AT91C_TC_BSWTRG_CLEAR ( 0x2 << 30 ) /* (TC) Effect: clear */ +#define AT91C_TC_BSWTRG_TOGGLE ( 0x3 << 30 ) /* (TC) Effect: toggle */ +/* -------- TC_SR : (TC Offset: 0x20) TC Channel Status Register -------- */ +#define AT91C_TC_COVFS ( 0x1 << 0 ) /* (TC) Counter Overflow */ +#define AT91C_TC_LOVRS ( 0x1 << 1 ) /* (TC) Load Overrun */ +#define AT91C_TC_CPAS ( 0x1 << 2 ) /* (TC) RA Compare */ +#define AT91C_TC_CPBS ( 0x1 << 3 ) /* (TC) RB Compare */ +#define AT91C_TC_CPCS ( 0x1 << 4 ) /* (TC) RC Compare */ +#define AT91C_TC_LDRAS ( 0x1 << 5 ) /* (TC) RA Loading */ +#define AT91C_TC_LDRBS ( 0x1 << 6 ) /* (TC) RB Loading */ +#define AT91C_TC_ETRGS ( 0x1 << 7 ) /* (TC) External Trigger */ +#define AT91C_TC_CLKSTA ( 0x1 << 16 ) /* (TC) Clock Enabling */ +#define AT91C_TC_MTIOA ( 0x1 << 17 ) /* (TC) TIOA Mirror */ +#define AT91C_TC_MTIOB ( 0x1 << 18 ) /* (TC) TIOA Mirror */ +/* -------- TC_IER : (TC Offset: 0x24) TC Channel Interrupt Enable Register -------- */ +/* -------- TC_IDR : (TC Offset: 0x28) TC Channel Interrupt Disable Register -------- */ +/* -------- TC_IMR : (TC Offset: 0x2c) TC Channel Interrupt Mask Register -------- */ -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Timer Counter Interface -// ***************************************************************************** -// *** Register offset in AT91S_TCB structure *** -#define TCB_TC0 ( 0) // TC Channel 0 -#define TCB_TC1 (64) // TC Channel 1 -#define TCB_TC2 (128) // TC Channel 2 -#define TCB_BCR (192) // TC Block Control Register -#define TCB_BMR (196) // TC Block Mode Register -// -------- TCB_BCR : (TCB Offset: 0xc0) TC Block Control Register -------- -#define AT91C_TCB_SYNC (0x1 << 0) // (TCB) Synchro Command -// -------- TCB_BMR : (TCB Offset: 0xc4) TC Block Mode Register -------- -#define AT91C_TCB_TC0XC0S (0x3 << 0) // (TCB) External Clock Signal 0 Selection -#define AT91C_TCB_TC0XC0S_TCLK0 (0x0) // (TCB) TCLK0 connected to XC0 -#define AT91C_TCB_TC0XC0S_NONE (0x1) // (TCB) None signal connected to XC0 -#define AT91C_TCB_TC0XC0S_TIOA1 (0x2) // (TCB) TIOA1 connected to XC0 -#define AT91C_TCB_TC0XC0S_TIOA2 (0x3) // (TCB) TIOA2 connected to XC0 -#define AT91C_TCB_TC1XC1S (0x3 << 2) // (TCB) External Clock Signal 1 Selection -#define AT91C_TCB_TC1XC1S_TCLK1 (0x0 << 2) // (TCB) TCLK1 connected to XC1 -#define AT91C_TCB_TC1XC1S_NONE (0x1 << 2) // (TCB) None signal connected to XC1 -#define AT91C_TCB_TC1XC1S_TIOA0 (0x2 << 2) // (TCB) TIOA0 connected to XC1 -#define AT91C_TCB_TC1XC1S_TIOA2 (0x3 << 2) // (TCB) TIOA2 connected to XC1 -#define AT91C_TCB_TC2XC2S (0x3 << 4) // (TCB) External Clock Signal 2 Selection -#define AT91C_TCB_TC2XC2S_TCLK2 (0x0 << 4) // (TCB) TCLK2 connected to XC2 -#define AT91C_TCB_TC2XC2S_NONE (0x1 << 4) // (TCB) None signal connected to XC2 -#define AT91C_TCB_TC2XC2S_TIOA0 (0x2 << 4) // (TCB) TIOA0 connected to XC2 -#define AT91C_TCB_TC2XC2S_TIOA1 (0x3 << 4) // (TCB) TIOA2 connected to XC2 +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR Timer Counter Interface */ +/* ***************************************************************************** */ +/* *** Register offset in AT91S_TCB structure *** */ +#define TCB_TC0 ( 0 ) /* TC Channel 0 */ +#define TCB_TC1 ( 64 ) /* TC Channel 1 */ +#define TCB_TC2 ( 128 ) /* TC Channel 2 */ +#define TCB_BCR ( 192 ) /* TC Block Control Register */ +#define TCB_BMR ( 196 ) /* TC Block Mode Register */ +/* -------- TCB_BCR : (TCB Offset: 0xc0) TC Block Control Register -------- */ +#define AT91C_TCB_SYNC ( 0x1 << 0 ) /* (TCB) Synchro Command */ +/* -------- TCB_BMR : (TCB Offset: 0xc4) TC Block Mode Register -------- */ +#define AT91C_TCB_TC0XC0S ( 0x3 << 0 ) /* (TCB) External Clock Signal 0 Selection */ +#define AT91C_TCB_TC0XC0S_TCLK0 ( 0x0 ) /* (TCB) TCLK0 connected to XC0 */ +#define AT91C_TCB_TC0XC0S_NONE ( 0x1 ) /* (TCB) None signal connected to XC0 */ +#define AT91C_TCB_TC0XC0S_TIOA1 ( 0x2 ) /* (TCB) TIOA1 connected to XC0 */ +#define AT91C_TCB_TC0XC0S_TIOA2 ( 0x3 ) /* (TCB) TIOA2 connected to XC0 */ +#define AT91C_TCB_TC1XC1S ( 0x3 << 2 ) /* (TCB) External Clock Signal 1 Selection */ +#define AT91C_TCB_TC1XC1S_TCLK1 ( 0x0 << 2 ) /* (TCB) TCLK1 connected to XC1 */ +#define AT91C_TCB_TC1XC1S_NONE ( 0x1 << 2 ) /* (TCB) None signal connected to XC1 */ +#define AT91C_TCB_TC1XC1S_TIOA0 ( 0x2 << 2 ) /* (TCB) TIOA0 connected to XC1 */ +#define AT91C_TCB_TC1XC1S_TIOA2 ( 0x3 << 2 ) /* (TCB) TIOA2 connected to XC1 */ +#define AT91C_TCB_TC2XC2S ( 0x3 << 4 ) /* (TCB) External Clock Signal 2 Selection */ +#define AT91C_TCB_TC2XC2S_TCLK2 ( 0x0 << 4 ) /* (TCB) TCLK2 connected to XC2 */ +#define AT91C_TCB_TC2XC2S_NONE ( 0x1 << 4 ) /* (TCB) None signal connected to XC2 */ +#define AT91C_TCB_TC2XC2S_TIOA0 ( 0x2 << 4 ) /* (TCB) TIOA0 connected to XC2 */ +#define AT91C_TCB_TC2XC2S_TIOA1 ( 0x3 << 4 ) /* (TCB) TIOA2 connected to XC2 */ -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Control Area Network MailBox Interface -// ***************************************************************************** -// *** Register offset in AT91S_CAN_MB structure *** -#define CAN_MB_MMR ( 0) // MailBox Mode Register -#define CAN_MB_MAM ( 4) // MailBox Acceptance Mask Register -#define CAN_MB_MID ( 8) // MailBox ID Register -#define CAN_MB_MFID (12) // MailBox Family ID Register -#define CAN_MB_MSR (16) // MailBox Status Register -#define CAN_MB_MDL (20) // MailBox Data Low Register -#define CAN_MB_MDH (24) // MailBox Data High Register -#define CAN_MB_MCR (28) // MailBox Control Register -// -------- CAN_MMR : (CAN_MB Offset: 0x0) CAN Message Mode Register -------- -#define AT91C_CAN_MTIMEMARK (0xFFFF << 0) // (CAN_MB) Mailbox Timemark -#define AT91C_CAN_PRIOR (0xF << 16) // (CAN_MB) Mailbox Priority -#define AT91C_CAN_MOT (0x7 << 24) // (CAN_MB) Mailbox Object Type -#define AT91C_CAN_MOT_DIS (0x0 << 24) // (CAN_MB) -#define AT91C_CAN_MOT_RX (0x1 << 24) // (CAN_MB) -#define AT91C_CAN_MOT_RXOVERWRITE (0x2 << 24) // (CAN_MB) -#define AT91C_CAN_MOT_TX (0x3 << 24) // (CAN_MB) -#define AT91C_CAN_MOT_CONSUMER (0x4 << 24) // (CAN_MB) -#define AT91C_CAN_MOT_PRODUCER (0x5 << 24) // (CAN_MB) -// -------- CAN_MAM : (CAN_MB Offset: 0x4) CAN Message Acceptance Mask Register -------- -#define AT91C_CAN_MIDvB (0x3FFFF << 0) // (CAN_MB) Complementary bits for identifier in extended mode -#define AT91C_CAN_MIDvA (0x7FF << 18) // (CAN_MB) Identifier for standard frame mode -#define AT91C_CAN_MIDE (0x1 << 29) // (CAN_MB) Identifier Version -// -------- CAN_MID : (CAN_MB Offset: 0x8) CAN Message ID Register -------- -// -------- CAN_MFID : (CAN_MB Offset: 0xc) CAN Message Family ID Register -------- -// -------- CAN_MSR : (CAN_MB Offset: 0x10) CAN Message Status Register -------- -#define AT91C_CAN_MTIMESTAMP (0xFFFF << 0) // (CAN_MB) Timer Value -#define AT91C_CAN_MDLC (0xF << 16) // (CAN_MB) Mailbox Data Length Code -#define AT91C_CAN_MRTR (0x1 << 20) // (CAN_MB) Mailbox Remote Transmission Request -#define AT91C_CAN_MABT (0x1 << 22) // (CAN_MB) Mailbox Message Abort -#define AT91C_CAN_MRDY (0x1 << 23) // (CAN_MB) Mailbox Ready -#define AT91C_CAN_MMI (0x1 << 24) // (CAN_MB) Mailbox Message Ignored -// -------- CAN_MDL : (CAN_MB Offset: 0x14) CAN Message Data Low Register -------- -// -------- CAN_MDH : (CAN_MB Offset: 0x18) CAN Message Data High Register -------- -// -------- CAN_MCR : (CAN_MB Offset: 0x1c) CAN Message Control Register -------- -#define AT91C_CAN_MACR (0x1 << 22) // (CAN_MB) Abort Request for Mailbox -#define AT91C_CAN_MTCR (0x1 << 23) // (CAN_MB) Mailbox Transfer Command +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR Control Area Network MailBox Interface */ +/* ***************************************************************************** */ +/* *** Register offset in AT91S_CAN_MB structure *** */ +#define CAN_MB_MMR ( 0 ) /* MailBox Mode Register */ +#define CAN_MB_MAM ( 4 ) /* MailBox Acceptance Mask Register */ +#define CAN_MB_MID ( 8 ) /* MailBox ID Register */ +#define CAN_MB_MFID ( 12 ) /* MailBox Family ID Register */ +#define CAN_MB_MSR ( 16 ) /* MailBox Status Register */ +#define CAN_MB_MDL ( 20 ) /* MailBox Data Low Register */ +#define CAN_MB_MDH ( 24 ) /* MailBox Data High Register */ +#define CAN_MB_MCR ( 28 ) /* MailBox Control Register */ +/* -------- CAN_MMR : (CAN_MB Offset: 0x0) CAN Message Mode Register -------- */ +#define AT91C_CAN_MTIMEMARK ( 0xFFFF << 0 ) /* (CAN_MB) Mailbox Timemark */ +#define AT91C_CAN_PRIOR ( 0xF << 16 ) /* (CAN_MB) Mailbox Priority */ +#define AT91C_CAN_MOT ( 0x7 << 24 ) /* (CAN_MB) Mailbox Object Type */ +#define AT91C_CAN_MOT_DIS ( 0x0 << 24 ) /* (CAN_MB) */ +#define AT91C_CAN_MOT_RX ( 0x1 << 24 ) /* (CAN_MB) */ +#define AT91C_CAN_MOT_RXOVERWRITE ( 0x2 << 24 ) /* (CAN_MB) */ +#define AT91C_CAN_MOT_TX ( 0x3 << 24 ) /* (CAN_MB) */ +#define AT91C_CAN_MOT_CONSUMER ( 0x4 << 24 ) /* (CAN_MB) */ +#define AT91C_CAN_MOT_PRODUCER ( 0x5 << 24 ) /* (CAN_MB) */ +/* -------- CAN_MAM : (CAN_MB Offset: 0x4) CAN Message Acceptance Mask Register -------- */ +#define AT91C_CAN_MIDvB ( 0x3FFFF << 0 ) /* (CAN_MB) Complementary bits for identifier in extended mode */ +#define AT91C_CAN_MIDvA ( 0x7FF << 18 ) /* (CAN_MB) Identifier for standard frame mode */ +#define AT91C_CAN_MIDE ( 0x1 << 29 ) /* (CAN_MB) Identifier Version */ +/* -------- CAN_MID : (CAN_MB Offset: 0x8) CAN Message ID Register -------- */ +/* -------- CAN_MFID : (CAN_MB Offset: 0xc) CAN Message Family ID Register -------- */ +/* -------- CAN_MSR : (CAN_MB Offset: 0x10) CAN Message Status Register -------- */ +#define AT91C_CAN_MTIMESTAMP ( 0xFFFF << 0 ) /* (CAN_MB) Timer Value */ +#define AT91C_CAN_MDLC ( 0xF << 16 ) /* (CAN_MB) Mailbox Data Length Code */ +#define AT91C_CAN_MRTR ( 0x1 << 20 ) /* (CAN_MB) Mailbox Remote Transmission Request */ +#define AT91C_CAN_MABT ( 0x1 << 22 ) /* (CAN_MB) Mailbox Message Abort */ +#define AT91C_CAN_MRDY ( 0x1 << 23 ) /* (CAN_MB) Mailbox Ready */ +#define AT91C_CAN_MMI ( 0x1 << 24 ) /* (CAN_MB) Mailbox Message Ignored */ +/* -------- CAN_MDL : (CAN_MB Offset: 0x14) CAN Message Data Low Register -------- */ +/* -------- CAN_MDH : (CAN_MB Offset: 0x18) CAN Message Data High Register -------- */ +/* -------- CAN_MCR : (CAN_MB Offset: 0x1c) CAN Message Control Register -------- */ +#define AT91C_CAN_MACR ( 0x1 << 22 ) /* (CAN_MB) Abort Request for Mailbox */ +#define AT91C_CAN_MTCR ( 0x1 << 23 ) /* (CAN_MB) Mailbox Transfer Command */ -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Control Area Network Interface -// ***************************************************************************** -// *** Register offset in AT91S_CAN structure *** -#define CAN_MR ( 0) // Mode Register -#define CAN_IER ( 4) // Interrupt Enable Register -#define CAN_IDR ( 8) // Interrupt Disable Register -#define CAN_IMR (12) // Interrupt Mask Register -#define CAN_SR (16) // Status Register -#define CAN_BR (20) // Baudrate Register -#define CAN_TIM (24) // Timer Register -#define CAN_TIMESTP (28) // Time Stamp Register -#define CAN_ECR (32) // Error Counter Register -#define CAN_TCR (36) // Transfer Command Register -#define CAN_ACR (40) // Abort Command Register -#define CAN_VR (252) // Version Register -#define CAN_MB0 (512) // CAN Mailbox 0 -#define CAN_MB1 (544) // CAN Mailbox 1 -#define CAN_MB2 (576) // CAN Mailbox 2 -#define CAN_MB3 (608) // CAN Mailbox 3 -#define CAN_MB4 (640) // CAN Mailbox 4 -#define CAN_MB5 (672) // CAN Mailbox 5 -#define CAN_MB6 (704) // CAN Mailbox 6 -#define CAN_MB7 (736) // CAN Mailbox 7 -#define CAN_MB8 (768) // CAN Mailbox 8 -#define CAN_MB9 (800) // CAN Mailbox 9 -#define CAN_MB10 (832) // CAN Mailbox 10 -#define CAN_MB11 (864) // CAN Mailbox 11 -#define CAN_MB12 (896) // CAN Mailbox 12 -#define CAN_MB13 (928) // CAN Mailbox 13 -#define CAN_MB14 (960) // CAN Mailbox 14 -#define CAN_MB15 (992) // CAN Mailbox 15 -// -------- CAN_MR : (CAN Offset: 0x0) CAN Mode Register -------- -#define AT91C_CAN_CANEN (0x1 << 0) // (CAN) CAN Controller Enable -#define AT91C_CAN_LPM (0x1 << 1) // (CAN) Disable/Enable Low Power Mode -#define AT91C_CAN_ABM (0x1 << 2) // (CAN) Disable/Enable Autobaud/Listen Mode -#define AT91C_CAN_OVL (0x1 << 3) // (CAN) Disable/Enable Overload Frame -#define AT91C_CAN_TEOF (0x1 << 4) // (CAN) Time Stamp messages at each end of Frame -#define AT91C_CAN_TTM (0x1 << 5) // (CAN) Disable/Enable Time Trigger Mode -#define AT91C_CAN_TIMFRZ (0x1 << 6) // (CAN) Enable Timer Freeze -#define AT91C_CAN_DRPT (0x1 << 7) // (CAN) Disable Repeat -// -------- CAN_IER : (CAN Offset: 0x4) CAN Interrupt Enable Register -------- -#define AT91C_CAN_MB0 (0x1 << 0) // (CAN) Mailbox 0 Flag -#define AT91C_CAN_MB1 (0x1 << 1) // (CAN) Mailbox 1 Flag -#define AT91C_CAN_MB2 (0x1 << 2) // (CAN) Mailbox 2 Flag -#define AT91C_CAN_MB3 (0x1 << 3) // (CAN) Mailbox 3 Flag -#define AT91C_CAN_MB4 (0x1 << 4) // (CAN) Mailbox 4 Flag -#define AT91C_CAN_MB5 (0x1 << 5) // (CAN) Mailbox 5 Flag -#define AT91C_CAN_MB6 (0x1 << 6) // (CAN) Mailbox 6 Flag -#define AT91C_CAN_MB7 (0x1 << 7) // (CAN) Mailbox 7 Flag -#define AT91C_CAN_MB8 (0x1 << 8) // (CAN) Mailbox 8 Flag -#define AT91C_CAN_MB9 (0x1 << 9) // (CAN) Mailbox 9 Flag -#define AT91C_CAN_MB10 (0x1 << 10) // (CAN) Mailbox 10 Flag -#define AT91C_CAN_MB11 (0x1 << 11) // (CAN) Mailbox 11 Flag -#define AT91C_CAN_MB12 (0x1 << 12) // (CAN) Mailbox 12 Flag -#define AT91C_CAN_MB13 (0x1 << 13) // (CAN) Mailbox 13 Flag -#define AT91C_CAN_MB14 (0x1 << 14) // (CAN) Mailbox 14 Flag -#define AT91C_CAN_MB15 (0x1 << 15) // (CAN) Mailbox 15 Flag -#define AT91C_CAN_ERRA (0x1 << 16) // (CAN) Error Active Mode Flag -#define AT91C_CAN_WARN (0x1 << 17) // (CAN) Warning Limit Flag -#define AT91C_CAN_ERRP (0x1 << 18) // (CAN) Error Passive Mode Flag -#define AT91C_CAN_BOFF (0x1 << 19) // (CAN) Bus Off Mode Flag -#define AT91C_CAN_SLEEP (0x1 << 20) // (CAN) Sleep Flag -#define AT91C_CAN_WAKEUP (0x1 << 21) // (CAN) Wakeup Flag -#define AT91C_CAN_TOVF (0x1 << 22) // (CAN) Timer Overflow Flag -#define AT91C_CAN_TSTP (0x1 << 23) // (CAN) Timestamp Flag -#define AT91C_CAN_CERR (0x1 << 24) // (CAN) CRC Error -#define AT91C_CAN_SERR (0x1 << 25) // (CAN) Stuffing Error -#define AT91C_CAN_AERR (0x1 << 26) // (CAN) Acknowledgment Error -#define AT91C_CAN_FERR (0x1 << 27) // (CAN) Form Error -#define AT91C_CAN_BERR (0x1 << 28) // (CAN) Bit Error -// -------- CAN_IDR : (CAN Offset: 0x8) CAN Interrupt Disable Register -------- -// -------- CAN_IMR : (CAN Offset: 0xc) CAN Interrupt Mask Register -------- -// -------- CAN_SR : (CAN Offset: 0x10) CAN Status Register -------- -#define AT91C_CAN_RBSY (0x1 << 29) // (CAN) Receiver Busy -#define AT91C_CAN_TBSY (0x1 << 30) // (CAN) Transmitter Busy -#define AT91C_CAN_OVLY (0x1 << 31) // (CAN) Overload Busy -// -------- CAN_BR : (CAN Offset: 0x14) CAN Baudrate Register -------- -#define AT91C_CAN_PHASE2 (0x7 << 0) // (CAN) Phase 2 segment -#define AT91C_CAN_PHASE1 (0x7 << 4) // (CAN) Phase 1 segment -#define AT91C_CAN_PROPAG (0x7 << 8) // (CAN) Programmation time segment -#define AT91C_CAN_SYNC (0x3 << 12) // (CAN) Re-synchronization jump width segment -#define AT91C_CAN_BRP (0x7F << 16) // (CAN) Baudrate Prescaler -#define AT91C_CAN_SMP (0x1 << 24) // (CAN) Sampling mode -// -------- CAN_TIM : (CAN Offset: 0x18) CAN Timer Register -------- -#define AT91C_CAN_TIMER (0xFFFF << 0) // (CAN) Timer field -// -------- CAN_TIMESTP : (CAN Offset: 0x1c) CAN Timestamp Register -------- -// -------- CAN_ECR : (CAN Offset: 0x20) CAN Error Counter Register -------- -#define AT91C_CAN_REC (0xFF << 0) // (CAN) Receive Error Counter -#define AT91C_CAN_TEC (0xFF << 16) // (CAN) Transmit Error Counter -// -------- CAN_TCR : (CAN Offset: 0x24) CAN Transfer Command Register -------- -#define AT91C_CAN_TIMRST (0x1 << 31) // (CAN) Timer Reset Field -// -------- CAN_ACR : (CAN Offset: 0x28) CAN Abort Command Register -------- +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR Control Area Network Interface */ +/* ***************************************************************************** */ +/* *** Register offset in AT91S_CAN structure *** */ +#define CAN_MR ( 0 ) /* Mode Register */ +#define CAN_IER ( 4 ) /* Interrupt Enable Register */ +#define CAN_IDR ( 8 ) /* Interrupt Disable Register */ +#define CAN_IMR ( 12 ) /* Interrupt Mask Register */ +#define CAN_SR ( 16 ) /* Status Register */ +#define CAN_BR ( 20 ) /* Baudrate Register */ +#define CAN_TIM ( 24 ) /* Timer Register */ +#define CAN_TIMESTP ( 28 ) /* Time Stamp Register */ +#define CAN_ECR ( 32 ) /* Error Counter Register */ +#define CAN_TCR ( 36 ) /* Transfer Command Register */ +#define CAN_ACR ( 40 ) /* Abort Command Register */ +#define CAN_VR ( 252 ) /* Version Register */ +#define CAN_MB0 ( 512 ) /* CAN Mailbox 0 */ +#define CAN_MB1 ( 544 ) /* CAN Mailbox 1 */ +#define CAN_MB2 ( 576 ) /* CAN Mailbox 2 */ +#define CAN_MB3 ( 608 ) /* CAN Mailbox 3 */ +#define CAN_MB4 ( 640 ) /* CAN Mailbox 4 */ +#define CAN_MB5 ( 672 ) /* CAN Mailbox 5 */ +#define CAN_MB6 ( 704 ) /* CAN Mailbox 6 */ +#define CAN_MB7 ( 736 ) /* CAN Mailbox 7 */ +#define CAN_MB8 ( 768 ) /* CAN Mailbox 8 */ +#define CAN_MB9 ( 800 ) /* CAN Mailbox 9 */ +#define CAN_MB10 ( 832 ) /* CAN Mailbox 10 */ +#define CAN_MB11 ( 864 ) /* CAN Mailbox 11 */ +#define CAN_MB12 ( 896 ) /* CAN Mailbox 12 */ +#define CAN_MB13 ( 928 ) /* CAN Mailbox 13 */ +#define CAN_MB14 ( 960 ) /* CAN Mailbox 14 */ +#define CAN_MB15 ( 992 ) /* CAN Mailbox 15 */ +/* -------- CAN_MR : (CAN Offset: 0x0) CAN Mode Register -------- */ +#define AT91C_CAN_CANEN ( 0x1 << 0 ) /* (CAN) CAN Controller Enable */ +#define AT91C_CAN_LPM ( 0x1 << 1 ) /* (CAN) Disable/Enable Low Power Mode */ +#define AT91C_CAN_ABM ( 0x1 << 2 ) /* (CAN) Disable/Enable Autobaud/Listen Mode */ +#define AT91C_CAN_OVL ( 0x1 << 3 ) /* (CAN) Disable/Enable Overload Frame */ +#define AT91C_CAN_TEOF ( 0x1 << 4 ) /* (CAN) Time Stamp messages at each end of Frame */ +#define AT91C_CAN_TTM ( 0x1 << 5 ) /* (CAN) Disable/Enable Time Trigger Mode */ +#define AT91C_CAN_TIMFRZ ( 0x1 << 6 ) /* (CAN) Enable Timer Freeze */ +#define AT91C_CAN_DRPT ( 0x1 << 7 ) /* (CAN) Disable Repeat */ +/* -------- CAN_IER : (CAN Offset: 0x4) CAN Interrupt Enable Register -------- */ +#define AT91C_CAN_MB0 ( 0x1 << 0 ) /* (CAN) Mailbox 0 Flag */ +#define AT91C_CAN_MB1 ( 0x1 << 1 ) /* (CAN) Mailbox 1 Flag */ +#define AT91C_CAN_MB2 ( 0x1 << 2 ) /* (CAN) Mailbox 2 Flag */ +#define AT91C_CAN_MB3 ( 0x1 << 3 ) /* (CAN) Mailbox 3 Flag */ +#define AT91C_CAN_MB4 ( 0x1 << 4 ) /* (CAN) Mailbox 4 Flag */ +#define AT91C_CAN_MB5 ( 0x1 << 5 ) /* (CAN) Mailbox 5 Flag */ +#define AT91C_CAN_MB6 ( 0x1 << 6 ) /* (CAN) Mailbox 6 Flag */ +#define AT91C_CAN_MB7 ( 0x1 << 7 ) /* (CAN) Mailbox 7 Flag */ +#define AT91C_CAN_MB8 ( 0x1 << 8 ) /* (CAN) Mailbox 8 Flag */ +#define AT91C_CAN_MB9 ( 0x1 << 9 ) /* (CAN) Mailbox 9 Flag */ +#define AT91C_CAN_MB10 ( 0x1 << 10 ) /* (CAN) Mailbox 10 Flag */ +#define AT91C_CAN_MB11 ( 0x1 << 11 ) /* (CAN) Mailbox 11 Flag */ +#define AT91C_CAN_MB12 ( 0x1 << 12 ) /* (CAN) Mailbox 12 Flag */ +#define AT91C_CAN_MB13 ( 0x1 << 13 ) /* (CAN) Mailbox 13 Flag */ +#define AT91C_CAN_MB14 ( 0x1 << 14 ) /* (CAN) Mailbox 14 Flag */ +#define AT91C_CAN_MB15 ( 0x1 << 15 ) /* (CAN) Mailbox 15 Flag */ +#define AT91C_CAN_ERRA ( 0x1 << 16 ) /* (CAN) Error Active Mode Flag */ +#define AT91C_CAN_WARN ( 0x1 << 17 ) /* (CAN) Warning Limit Flag */ +#define AT91C_CAN_ERRP ( 0x1 << 18 ) /* (CAN) Error Passive Mode Flag */ +#define AT91C_CAN_BOFF ( 0x1 << 19 ) /* (CAN) Bus Off Mode Flag */ +#define AT91C_CAN_SLEEP ( 0x1 << 20 ) /* (CAN) Sleep Flag */ +#define AT91C_CAN_WAKEUP ( 0x1 << 21 ) /* (CAN) Wakeup Flag */ +#define AT91C_CAN_TOVF ( 0x1 << 22 ) /* (CAN) Timer Overflow Flag */ +#define AT91C_CAN_TSTP ( 0x1 << 23 ) /* (CAN) Timestamp Flag */ +#define AT91C_CAN_CERR ( 0x1 << 24 ) /* (CAN) CRC Error */ +#define AT91C_CAN_SERR ( 0x1 << 25 ) /* (CAN) Stuffing Error */ +#define AT91C_CAN_AERR ( 0x1 << 26 ) /* (CAN) Acknowledgment Error */ +#define AT91C_CAN_FERR ( 0x1 << 27 ) /* (CAN) Form Error */ +#define AT91C_CAN_BERR ( 0x1 << 28 ) /* (CAN) Bit Error */ +/* -------- CAN_IDR : (CAN Offset: 0x8) CAN Interrupt Disable Register -------- */ +/* -------- CAN_IMR : (CAN Offset: 0xc) CAN Interrupt Mask Register -------- */ +/* -------- CAN_SR : (CAN Offset: 0x10) CAN Status Register -------- */ +#define AT91C_CAN_RBSY ( 0x1 << 29 ) /* (CAN) Receiver Busy */ +#define AT91C_CAN_TBSY ( 0x1 << 30 ) /* (CAN) Transmitter Busy */ +#define AT91C_CAN_OVLY ( 0x1 << 31 ) /* (CAN) Overload Busy */ +/* -------- CAN_BR : (CAN Offset: 0x14) CAN Baudrate Register -------- */ +#define AT91C_CAN_PHASE2 ( 0x7 << 0 ) /* (CAN) Phase 2 segment */ +#define AT91C_CAN_PHASE1 ( 0x7 << 4 ) /* (CAN) Phase 1 segment */ +#define AT91C_CAN_PROPAG ( 0x7 << 8 ) /* (CAN) Programmation time segment */ +#define AT91C_CAN_SYNC ( 0x3 << 12 ) /* (CAN) Re-synchronization jump width segment */ +#define AT91C_CAN_BRP ( 0x7F << 16 ) /* (CAN) Baudrate Prescaler */ +#define AT91C_CAN_SMP ( 0x1 << 24 ) /* (CAN) Sampling mode */ +/* -------- CAN_TIM : (CAN Offset: 0x18) CAN Timer Register -------- */ +#define AT91C_CAN_TIMER ( 0xFFFF << 0 ) /* (CAN) Timer field */ +/* -------- CAN_TIMESTP : (CAN Offset: 0x1c) CAN Timestamp Register -------- */ +/* -------- CAN_ECR : (CAN Offset: 0x20) CAN Error Counter Register -------- */ +#define AT91C_CAN_REC ( 0xFF << 0 ) /* (CAN) Receive Error Counter */ +#define AT91C_CAN_TEC ( 0xFF << 16 ) /* (CAN) Transmit Error Counter */ +/* -------- CAN_TCR : (CAN Offset: 0x24) CAN Transfer Command Register -------- */ +#define AT91C_CAN_TIMRST ( 0x1 << 31 ) /* (CAN) Timer Reset Field */ +/* -------- CAN_ACR : (CAN Offset: 0x28) CAN Abort Command Register -------- */ -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Ethernet MAC 10/100 -// ***************************************************************************** -// *** Register offset in AT91S_EMAC structure *** -#define EMAC_NCR ( 0) // Network Control Register -#define EMAC_NCFGR ( 4) // Network Configuration Register -#define EMAC_NSR ( 8) // Network Status Register -#define EMAC_TSR (20) // Transmit Status Register -#define EMAC_RBQP (24) // Receive Buffer Queue Pointer -#define EMAC_TBQP (28) // Transmit Buffer Queue Pointer -#define EMAC_RSR (32) // Receive Status Register -#define EMAC_ISR (36) // Interrupt Status Register -#define EMAC_IER (40) // Interrupt Enable Register -#define EMAC_IDR (44) // Interrupt Disable Register -#define EMAC_IMR (48) // Interrupt Mask Register -#define EMAC_MAN (52) // PHY Maintenance Register -#define EMAC_PTR (56) // Pause Time Register -#define EMAC_PFR (60) // Pause Frames received Register -#define EMAC_FTO (64) // Frames Transmitted OK Register -#define EMAC_SCF (68) // Single Collision Frame Register -#define EMAC_MCF (72) // Multiple Collision Frame Register -#define EMAC_FRO (76) // Frames Received OK Register -#define EMAC_FCSE (80) // Frame Check Sequence Error Register -#define EMAC_ALE (84) // Alignment Error Register -#define EMAC_DTF (88) // Deferred Transmission Frame Register -#define EMAC_LCOL (92) // Late Collision Register -#define EMAC_ECOL (96) // Excessive Collision Register -#define EMAC_TUND (100) // Transmit Underrun Error Register -#define EMAC_CSE (104) // Carrier Sense Error Register -#define EMAC_RRE (108) // Receive Ressource Error Register -#define EMAC_ROV (112) // Receive Overrun Errors Register -#define EMAC_RSE (116) // Receive Symbol Errors Register -#define EMAC_ELE (120) // Excessive Length Errors Register -#define EMAC_RJA (124) // Receive Jabbers Register -#define EMAC_USF (128) // Undersize Frames Register -#define EMAC_STE (132) // SQE Test Error Register -#define EMAC_RLE (136) // Receive Length Field Mismatch Register -#define EMAC_TPF (140) // Transmitted Pause Frames Register -#define EMAC_HRB (144) // Hash Address Bottom[31:0] -#define EMAC_HRT (148) // Hash Address Top[63:32] -#define EMAC_SA1L (152) // Specific Address 1 Bottom, First 4 bytes -#define EMAC_SA1H (156) // Specific Address 1 Top, Last 2 bytes -#define EMAC_SA2L (160) // Specific Address 2 Bottom, First 4 bytes -#define EMAC_SA2H (164) // Specific Address 2 Top, Last 2 bytes -#define EMAC_SA3L (168) // Specific Address 3 Bottom, First 4 bytes -#define EMAC_SA3H (172) // Specific Address 3 Top, Last 2 bytes -#define EMAC_SA4L (176) // Specific Address 4 Bottom, First 4 bytes -#define EMAC_SA4H (180) // Specific Address 4 Top, Last 2 bytes -#define EMAC_TID (184) // Type ID Checking Register -#define EMAC_TPQ (188) // Transmit Pause Quantum Register -#define EMAC_USRIO (192) // USER Input/Output Register -#define EMAC_WOL (196) // Wake On LAN Register -#define EMAC_REV (252) // Revision Register -// -------- EMAC_NCR : (EMAC Offset: 0x0) -------- -#define AT91C_EMAC_LB (0x1 << 0) // (EMAC) Loopback. Optional. When set, loopback signal is at high level. -#define AT91C_EMAC_LLB (0x1 << 1) // (EMAC) Loopback local. -#define AT91C_EMAC_RE (0x1 << 2) // (EMAC) Receive enable. -#define AT91C_EMAC_TE (0x1 << 3) // (EMAC) Transmit enable. -#define AT91C_EMAC_MPE (0x1 << 4) // (EMAC) Management port enable. -#define AT91C_EMAC_CLRSTAT (0x1 << 5) // (EMAC) Clear statistics registers. -#define AT91C_EMAC_INCSTAT (0x1 << 6) // (EMAC) Increment statistics registers. -#define AT91C_EMAC_WESTAT (0x1 << 7) // (EMAC) Write enable for statistics registers. -#define AT91C_EMAC_BP (0x1 << 8) // (EMAC) Back pressure. -#define AT91C_EMAC_TSTART (0x1 << 9) // (EMAC) Start Transmission. -#define AT91C_EMAC_THALT (0x1 << 10) // (EMAC) Transmission Halt. -#define AT91C_EMAC_TPFR (0x1 << 11) // (EMAC) Transmit pause frame -#define AT91C_EMAC_TZQ (0x1 << 12) // (EMAC) Transmit zero quantum pause frame -// -------- EMAC_NCFGR : (EMAC Offset: 0x4) Network Configuration Register -------- -#define AT91C_EMAC_SPD (0x1 << 0) // (EMAC) Speed. -#define AT91C_EMAC_FD (0x1 << 1) // (EMAC) Full duplex. -#define AT91C_EMAC_JFRAME (0x1 << 3) // (EMAC) Jumbo Frames. -#define AT91C_EMAC_CAF (0x1 << 4) // (EMAC) Copy all frames. -#define AT91C_EMAC_NBC (0x1 << 5) // (EMAC) No broadcast. -#define AT91C_EMAC_MTI (0x1 << 6) // (EMAC) Multicast hash event enable -#define AT91C_EMAC_UNI (0x1 << 7) // (EMAC) Unicast hash enable. -#define AT91C_EMAC_BIG (0x1 << 8) // (EMAC) Receive 1522 bytes. -#define AT91C_EMAC_EAE (0x1 << 9) // (EMAC) External address match enable. -#define AT91C_EMAC_CLK (0x3 << 10) // (EMAC) -#define AT91C_EMAC_CLK_HCLK_8 (0x0 << 10) // (EMAC) HCLK divided by 8 -#define AT91C_EMAC_CLK_HCLK_16 (0x1 << 10) // (EMAC) HCLK divided by 16 -#define AT91C_EMAC_CLK_HCLK_32 (0x2 << 10) // (EMAC) HCLK divided by 32 -#define AT91C_EMAC_CLK_HCLK_64 (0x3 << 10) // (EMAC) HCLK divided by 64 -#define AT91C_EMAC_RTY (0x1 << 12) // (EMAC) -#define AT91C_EMAC_PAE (0x1 << 13) // (EMAC) -#define AT91C_EMAC_RBOF (0x3 << 14) // (EMAC) -#define AT91C_EMAC_RBOF_OFFSET_0 (0x0 << 14) // (EMAC) no offset from start of receive buffer -#define AT91C_EMAC_RBOF_OFFSET_1 (0x1 << 14) // (EMAC) one byte offset from start of receive buffer -#define AT91C_EMAC_RBOF_OFFSET_2 (0x2 << 14) // (EMAC) two bytes offset from start of receive buffer -#define AT91C_EMAC_RBOF_OFFSET_3 (0x3 << 14) // (EMAC) three bytes offset from start of receive buffer -#define AT91C_EMAC_RLCE (0x1 << 16) // (EMAC) Receive Length field Checking Enable -#define AT91C_EMAC_DRFCS (0x1 << 17) // (EMAC) Discard Receive FCS -#define AT91C_EMAC_EFRHD (0x1 << 18) // (EMAC) -#define AT91C_EMAC_IRXFCS (0x1 << 19) // (EMAC) Ignore RX FCS -// -------- EMAC_NSR : (EMAC Offset: 0x8) Network Status Register -------- -#define AT91C_EMAC_LINKR (0x1 << 0) // (EMAC) -#define AT91C_EMAC_MDIO (0x1 << 1) // (EMAC) -#define AT91C_EMAC_IDLE (0x1 << 2) // (EMAC) -// -------- EMAC_TSR : (EMAC Offset: 0x14) Transmit Status Register -------- -#define AT91C_EMAC_UBR (0x1 << 0) // (EMAC) -#define AT91C_EMAC_COL (0x1 << 1) // (EMAC) -#define AT91C_EMAC_RLES (0x1 << 2) // (EMAC) -#define AT91C_EMAC_TGO (0x1 << 3) // (EMAC) Transmit Go -#define AT91C_EMAC_BEX (0x1 << 4) // (EMAC) Buffers exhausted mid frame -#define AT91C_EMAC_COMP (0x1 << 5) // (EMAC) -#define AT91C_EMAC_UND (0x1 << 6) // (EMAC) -// -------- EMAC_RSR : (EMAC Offset: 0x20) Receive Status Register -------- -#define AT91C_EMAC_BNA (0x1 << 0) // (EMAC) -#define AT91C_EMAC_REC (0x1 << 1) // (EMAC) -#define AT91C_EMAC_OVR (0x1 << 2) // (EMAC) -// -------- EMAC_ISR : (EMAC Offset: 0x24) Interrupt Status Register -------- -#define AT91C_EMAC_MFD (0x1 << 0) // (EMAC) -#define AT91C_EMAC_RCOMP (0x1 << 1) // (EMAC) -#define AT91C_EMAC_RXUBR (0x1 << 2) // (EMAC) -#define AT91C_EMAC_TXUBR (0x1 << 3) // (EMAC) -#define AT91C_EMAC_TUNDR (0x1 << 4) // (EMAC) -#define AT91C_EMAC_RLEX (0x1 << 5) // (EMAC) -#define AT91C_EMAC_TXERR (0x1 << 6) // (EMAC) -#define AT91C_EMAC_TCOMP (0x1 << 7) // (EMAC) -#define AT91C_EMAC_LINK (0x1 << 9) // (EMAC) -#define AT91C_EMAC_ROVR (0x1 << 10) // (EMAC) -#define AT91C_EMAC_HRESP (0x1 << 11) // (EMAC) -#define AT91C_EMAC_PFRE (0x1 << 12) // (EMAC) -#define AT91C_EMAC_PTZ (0x1 << 13) // (EMAC) -// -------- EMAC_IER : (EMAC Offset: 0x28) Interrupt Enable Register -------- -// -------- EMAC_IDR : (EMAC Offset: 0x2c) Interrupt Disable Register -------- -// -------- EMAC_IMR : (EMAC Offset: 0x30) Interrupt Mask Register -------- -// -------- EMAC_MAN : (EMAC Offset: 0x34) PHY Maintenance Register -------- -#define AT91C_EMAC_DATA (0xFFFF << 0) // (EMAC) -#define AT91C_EMAC_CODE (0x3 << 16) // (EMAC) -#define AT91C_EMAC_REGA (0x1F << 18) // (EMAC) -#define AT91C_EMAC_PHYA (0x1F << 23) // (EMAC) -#define AT91C_EMAC_RW (0x3 << 28) // (EMAC) -#define AT91C_EMAC_SOF (0x3 << 30) // (EMAC) -// -------- EMAC_USRIO : (EMAC Offset: 0xc0) USER Input Output Register -------- -#define AT91C_EMAC_RMII (0x1 << 0) // (EMAC) Reduce MII -// -------- EMAC_WOL : (EMAC Offset: 0xc4) Wake On LAN Register -------- -#define AT91C_EMAC_IP (0xFFFF << 0) // (EMAC) ARP request IP address -#define AT91C_EMAC_MAG (0x1 << 16) // (EMAC) Magic packet event enable -#define AT91C_EMAC_ARP (0x1 << 17) // (EMAC) ARP request event enable -#define AT91C_EMAC_SA1 (0x1 << 18) // (EMAC) Specific address register 1 event enable -// -------- EMAC_REV : (EMAC Offset: 0xfc) Revision Register -------- -#define AT91C_EMAC_REVREF (0xFFFF << 0) // (EMAC) -#define AT91C_EMAC_PARTREF (0xFFFF << 16) // (EMAC) +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR Ethernet MAC 10/100 */ +/* ***************************************************************************** */ +/* *** Register offset in AT91S_EMAC structure *** */ +#define EMAC_NCR ( 0 ) /* Network Control Register */ +#define EMAC_NCFGR ( 4 ) /* Network Configuration Register */ +#define EMAC_NSR ( 8 ) /* Network Status Register */ +#define EMAC_TSR ( 20 ) /* Transmit Status Register */ +#define EMAC_RBQP ( 24 ) /* Receive Buffer Queue Pointer */ +#define EMAC_TBQP ( 28 ) /* Transmit Buffer Queue Pointer */ +#define EMAC_RSR ( 32 ) /* Receive Status Register */ +#define EMAC_ISR ( 36 ) /* Interrupt Status Register */ +#define EMAC_IER ( 40 ) /* Interrupt Enable Register */ +#define EMAC_IDR ( 44 ) /* Interrupt Disable Register */ +#define EMAC_IMR ( 48 ) /* Interrupt Mask Register */ +#define EMAC_MAN ( 52 ) /* PHY Maintenance Register */ +#define EMAC_PTR ( 56 ) /* Pause Time Register */ +#define EMAC_PFR ( 60 ) /* Pause Frames received Register */ +#define EMAC_FTO ( 64 ) /* Frames Transmitted OK Register */ +#define EMAC_SCF ( 68 ) /* Single Collision Frame Register */ +#define EMAC_MCF ( 72 ) /* Multiple Collision Frame Register */ +#define EMAC_FRO ( 76 ) /* Frames Received OK Register */ +#define EMAC_FCSE ( 80 ) /* Frame Check Sequence Error Register */ +#define EMAC_ALE ( 84 ) /* Alignment Error Register */ +#define EMAC_DTF ( 88 ) /* Deferred Transmission Frame Register */ +#define EMAC_LCOL ( 92 ) /* Late Collision Register */ +#define EMAC_ECOL ( 96 ) /* Excessive Collision Register */ +#define EMAC_TUND ( 100 ) /* Transmit Underrun Error Register */ +#define EMAC_CSE ( 104 ) /* Carrier Sense Error Register */ +#define EMAC_RRE ( 108 ) /* Receive Ressource Error Register */ +#define EMAC_ROV ( 112 ) /* Receive Overrun Errors Register */ +#define EMAC_RSE ( 116 ) /* Receive Symbol Errors Register */ +#define EMAC_ELE ( 120 ) /* Excessive Length Errors Register */ +#define EMAC_RJA ( 124 ) /* Receive Jabbers Register */ +#define EMAC_USF ( 128 ) /* Undersize Frames Register */ +#define EMAC_STE ( 132 ) /* SQE Test Error Register */ +#define EMAC_RLE ( 136 ) /* Receive Length Field Mismatch Register */ +#define EMAC_TPF ( 140 ) /* Transmitted Pause Frames Register */ +#define EMAC_HRB ( 144 ) /* Hash Address Bottom[31:0] */ +#define EMAC_HRT ( 148 ) /* Hash Address Top[63:32] */ +#define EMAC_SA1L ( 152 ) /* Specific Address 1 Bottom, First 4 bytes */ +#define EMAC_SA1H ( 156 ) /* Specific Address 1 Top, Last 2 bytes */ +#define EMAC_SA2L ( 160 ) /* Specific Address 2 Bottom, First 4 bytes */ +#define EMAC_SA2H ( 164 ) /* Specific Address 2 Top, Last 2 bytes */ +#define EMAC_SA3L ( 168 ) /* Specific Address 3 Bottom, First 4 bytes */ +#define EMAC_SA3H ( 172 ) /* Specific Address 3 Top, Last 2 bytes */ +#define EMAC_SA4L ( 176 ) /* Specific Address 4 Bottom, First 4 bytes */ +#define EMAC_SA4H ( 180 ) /* Specific Address 4 Top, Last 2 bytes */ +#define EMAC_TID ( 184 ) /* Type ID Checking Register */ +#define EMAC_TPQ ( 188 ) /* Transmit Pause Quantum Register */ +#define EMAC_USRIO ( 192 ) /* USER Input/Output Register */ +#define EMAC_WOL ( 196 ) /* Wake On LAN Register */ +#define EMAC_REV ( 252 ) /* Revision Register */ +/* -------- EMAC_NCR : (EMAC Offset: 0x0) -------- */ +#define AT91C_EMAC_LB ( 0x1 << 0 ) /* (EMAC) Loopback. Optional. When set, loopback signal is at high level. */ +#define AT91C_EMAC_LLB ( 0x1 << 1 ) /* (EMAC) Loopback local. */ +#define AT91C_EMAC_RE ( 0x1 << 2 ) /* (EMAC) Receive enable. */ +#define AT91C_EMAC_TE ( 0x1 << 3 ) /* (EMAC) Transmit enable. */ +#define AT91C_EMAC_MPE ( 0x1 << 4 ) /* (EMAC) Management port enable. */ +#define AT91C_EMAC_CLRSTAT ( 0x1 << 5 ) /* (EMAC) Clear statistics registers. */ +#define AT91C_EMAC_INCSTAT ( 0x1 << 6 ) /* (EMAC) Increment statistics registers. */ +#define AT91C_EMAC_WESTAT ( 0x1 << 7 ) /* (EMAC) Write enable for statistics registers. */ +#define AT91C_EMAC_BP ( 0x1 << 8 ) /* (EMAC) Back pressure. */ +#define AT91C_EMAC_TSTART ( 0x1 << 9 ) /* (EMAC) Start Transmission. */ +#define AT91C_EMAC_THALT ( 0x1 << 10 ) /* (EMAC) Transmission Halt. */ +#define AT91C_EMAC_TPFR ( 0x1 << 11 ) /* (EMAC) Transmit pause frame */ +#define AT91C_EMAC_TZQ ( 0x1 << 12 ) /* (EMAC) Transmit zero quantum pause frame */ +/* -------- EMAC_NCFGR : (EMAC Offset: 0x4) Network Configuration Register -------- */ +#define AT91C_EMAC_SPD ( 0x1 << 0 ) /* (EMAC) Speed. */ +#define AT91C_EMAC_FD ( 0x1 << 1 ) /* (EMAC) Full duplex. */ +#define AT91C_EMAC_JFRAME ( 0x1 << 3 ) /* (EMAC) Jumbo Frames. */ +#define AT91C_EMAC_CAF ( 0x1 << 4 ) /* (EMAC) Copy all frames. */ +#define AT91C_EMAC_NBC ( 0x1 << 5 ) /* (EMAC) No broadcast. */ +#define AT91C_EMAC_MTI ( 0x1 << 6 ) /* (EMAC) Multicast hash event enable */ +#define AT91C_EMAC_UNI ( 0x1 << 7 ) /* (EMAC) Unicast hash enable. */ +#define AT91C_EMAC_BIG ( 0x1 << 8 ) /* (EMAC) Receive 1522 bytes. */ +#define AT91C_EMAC_EAE ( 0x1 << 9 ) /* (EMAC) External address match enable. */ +#define AT91C_EMAC_CLK ( 0x3 << 10 ) /* (EMAC) */ +#define AT91C_EMAC_CLK_HCLK_8 ( 0x0 << 10 ) /* (EMAC) HCLK divided by 8 */ +#define AT91C_EMAC_CLK_HCLK_16 ( 0x1 << 10 ) /* (EMAC) HCLK divided by 16 */ +#define AT91C_EMAC_CLK_HCLK_32 ( 0x2 << 10 ) /* (EMAC) HCLK divided by 32 */ +#define AT91C_EMAC_CLK_HCLK_64 ( 0x3 << 10 ) /* (EMAC) HCLK divided by 64 */ +#define AT91C_EMAC_RTY ( 0x1 << 12 ) /* (EMAC) */ +#define AT91C_EMAC_PAE ( 0x1 << 13 ) /* (EMAC) */ +#define AT91C_EMAC_RBOF ( 0x3 << 14 ) /* (EMAC) */ +#define AT91C_EMAC_RBOF_OFFSET_0 ( 0x0 << 14 ) /* (EMAC) no offset from start of receive buffer */ +#define AT91C_EMAC_RBOF_OFFSET_1 ( 0x1 << 14 ) /* (EMAC) one byte offset from start of receive buffer */ +#define AT91C_EMAC_RBOF_OFFSET_2 ( 0x2 << 14 ) /* (EMAC) two bytes offset from start of receive buffer */ +#define AT91C_EMAC_RBOF_OFFSET_3 ( 0x3 << 14 ) /* (EMAC) three bytes offset from start of receive buffer */ +#define AT91C_EMAC_RLCE ( 0x1 << 16 ) /* (EMAC) Receive Length field Checking Enable */ +#define AT91C_EMAC_DRFCS ( 0x1 << 17 ) /* (EMAC) Discard Receive FCS */ +#define AT91C_EMAC_EFRHD ( 0x1 << 18 ) /* (EMAC) */ +#define AT91C_EMAC_IRXFCS ( 0x1 << 19 ) /* (EMAC) Ignore RX FCS */ +/* -------- EMAC_NSR : (EMAC Offset: 0x8) Network Status Register -------- */ +#define AT91C_EMAC_LINKR ( 0x1 << 0 ) /* (EMAC) */ +#define AT91C_EMAC_MDIO ( 0x1 << 1 ) /* (EMAC) */ +#define AT91C_EMAC_IDLE ( 0x1 << 2 ) /* (EMAC) */ +/* -------- EMAC_TSR : (EMAC Offset: 0x14) Transmit Status Register -------- */ +#define AT91C_EMAC_UBR ( 0x1 << 0 ) /* (EMAC) */ +#define AT91C_EMAC_COL ( 0x1 << 1 ) /* (EMAC) */ +#define AT91C_EMAC_RLES ( 0x1 << 2 ) /* (EMAC) */ +#define AT91C_EMAC_TGO ( 0x1 << 3 ) /* (EMAC) Transmit Go */ +#define AT91C_EMAC_BEX ( 0x1 << 4 ) /* (EMAC) Buffers exhausted mid frame */ +#define AT91C_EMAC_COMP ( 0x1 << 5 ) /* (EMAC) */ +#define AT91C_EMAC_UND ( 0x1 << 6 ) /* (EMAC) */ +/* -------- EMAC_RSR : (EMAC Offset: 0x20) Receive Status Register -------- */ +#define AT91C_EMAC_BNA ( 0x1 << 0 ) /* (EMAC) */ +#define AT91C_EMAC_REC ( 0x1 << 1 ) /* (EMAC) */ +#define AT91C_EMAC_OVR ( 0x1 << 2 ) /* (EMAC) */ +/* -------- EMAC_ISR : (EMAC Offset: 0x24) Interrupt Status Register -------- */ +#define AT91C_EMAC_MFD ( 0x1 << 0 ) /* (EMAC) */ +#define AT91C_EMAC_RCOMP ( 0x1 << 1 ) /* (EMAC) */ +#define AT91C_EMAC_RXUBR ( 0x1 << 2 ) /* (EMAC) */ +#define AT91C_EMAC_TXUBR ( 0x1 << 3 ) /* (EMAC) */ +#define AT91C_EMAC_TUNDR ( 0x1 << 4 ) /* (EMAC) */ +#define AT91C_EMAC_RLEX ( 0x1 << 5 ) /* (EMAC) */ +#define AT91C_EMAC_TXERR ( 0x1 << 6 ) /* (EMAC) */ +#define AT91C_EMAC_TCOMP ( 0x1 << 7 ) /* (EMAC) */ +#define AT91C_EMAC_LINK ( 0x1 << 9 ) /* (EMAC) */ +#define AT91C_EMAC_ROVR ( 0x1 << 10 ) /* (EMAC) */ +#define AT91C_EMAC_HRESP ( 0x1 << 11 ) /* (EMAC) */ +#define AT91C_EMAC_PFRE ( 0x1 << 12 ) /* (EMAC) */ +#define AT91C_EMAC_PTZ ( 0x1 << 13 ) /* (EMAC) */ +/* -------- EMAC_IER : (EMAC Offset: 0x28) Interrupt Enable Register -------- */ +/* -------- EMAC_IDR : (EMAC Offset: 0x2c) Interrupt Disable Register -------- */ +/* -------- EMAC_IMR : (EMAC Offset: 0x30) Interrupt Mask Register -------- */ +/* -------- EMAC_MAN : (EMAC Offset: 0x34) PHY Maintenance Register -------- */ +#define AT91C_EMAC_DATA ( 0xFFFF << 0 ) /* (EMAC) */ +#define AT91C_EMAC_CODE ( 0x3 << 16 ) /* (EMAC) */ +#define AT91C_EMAC_REGA ( 0x1F << 18 ) /* (EMAC) */ +#define AT91C_EMAC_PHYA ( 0x1F << 23 ) /* (EMAC) */ +#define AT91C_EMAC_RW ( 0x3 << 28 ) /* (EMAC) */ +#define AT91C_EMAC_SOF ( 0x3 << 30 ) /* (EMAC) */ +/* -------- EMAC_USRIO : (EMAC Offset: 0xc0) USER Input Output Register -------- */ +#define AT91C_EMAC_RMII ( 0x1 << 0 ) /* (EMAC) Reduce MII */ +/* -------- EMAC_WOL : (EMAC Offset: 0xc4) Wake On LAN Register -------- */ +#define AT91C_EMAC_IP ( 0xFFFF << 0 ) /* (EMAC) ARP request IP address */ +#define AT91C_EMAC_MAG ( 0x1 << 16 ) /* (EMAC) Magic packet event enable */ +#define AT91C_EMAC_ARP ( 0x1 << 17 ) /* (EMAC) ARP request event enable */ +#define AT91C_EMAC_SA1 ( 0x1 << 18 ) /* (EMAC) Specific address register 1 event enable */ +/* -------- EMAC_REV : (EMAC Offset: 0xfc) Revision Register -------- */ +#define AT91C_EMAC_REVREF ( 0xFFFF << 0 ) /* (EMAC) */ +#define AT91C_EMAC_PARTREF ( 0xFFFF << 16 ) /* (EMAC) */ -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Analog to Digital Convertor -// ***************************************************************************** -// *** Register offset in AT91S_ADC structure *** -#define ADC_CR ( 0) // ADC Control Register -#define ADC_MR ( 4) // ADC Mode Register -#define ADC_CHER (16) // ADC Channel Enable Register -#define ADC_CHDR (20) // ADC Channel Disable Register -#define ADC_CHSR (24) // ADC Channel Status Register -#define ADC_SR (28) // ADC Status Register -#define ADC_LCDR (32) // ADC Last Converted Data Register -#define ADC_IER (36) // ADC Interrupt Enable Register -#define ADC_IDR (40) // ADC Interrupt Disable Register -#define ADC_IMR (44) // ADC Interrupt Mask Register -#define ADC_CDR0 (48) // ADC Channel Data Register 0 -#define ADC_CDR1 (52) // ADC Channel Data Register 1 -#define ADC_CDR2 (56) // ADC Channel Data Register 2 -#define ADC_CDR3 (60) // ADC Channel Data Register 3 -#define ADC_CDR4 (64) // ADC Channel Data Register 4 -#define ADC_CDR5 (68) // ADC Channel Data Register 5 -#define ADC_CDR6 (72) // ADC Channel Data Register 6 -#define ADC_CDR7 (76) // ADC Channel Data Register 7 -#define ADC_RPR (256) // Receive Pointer Register -#define ADC_RCR (260) // Receive Counter Register -#define ADC_TPR (264) // Transmit Pointer Register -#define ADC_TCR (268) // Transmit Counter Register -#define ADC_RNPR (272) // Receive Next Pointer Register -#define ADC_RNCR (276) // Receive Next Counter Register -#define ADC_TNPR (280) // Transmit Next Pointer Register -#define ADC_TNCR (284) // Transmit Next Counter Register -#define ADC_PTCR (288) // PDC Transfer Control Register -#define ADC_PTSR (292) // PDC Transfer Status Register -// -------- ADC_CR : (ADC Offset: 0x0) ADC Control Register -------- -#define AT91C_ADC_SWRST (0x1 << 0) // (ADC) Software Reset -#define AT91C_ADC_START (0x1 << 1) // (ADC) Start Conversion -// -------- ADC_MR : (ADC Offset: 0x4) ADC Mode Register -------- -#define AT91C_ADC_TRGEN (0x1 << 0) // (ADC) Trigger Enable -#define AT91C_ADC_TRGEN_DIS (0x0) // (ADC) Hradware triggers are disabled. Starting a conversion is only possible by software -#define AT91C_ADC_TRGEN_EN (0x1) // (ADC) Hardware trigger selected by TRGSEL field is enabled. -#define AT91C_ADC_TRGSEL (0x7 << 1) // (ADC) Trigger Selection -#define AT91C_ADC_TRGSEL_TIOA0 (0x0 << 1) // (ADC) Selected TRGSEL = TIAO0 -#define AT91C_ADC_TRGSEL_TIOA1 (0x1 << 1) // (ADC) Selected TRGSEL = TIAO1 -#define AT91C_ADC_TRGSEL_TIOA2 (0x2 << 1) // (ADC) Selected TRGSEL = TIAO2 -#define AT91C_ADC_TRGSEL_TIOA3 (0x3 << 1) // (ADC) Selected TRGSEL = TIAO3 -#define AT91C_ADC_TRGSEL_TIOA4 (0x4 << 1) // (ADC) Selected TRGSEL = TIAO4 -#define AT91C_ADC_TRGSEL_TIOA5 (0x5 << 1) // (ADC) Selected TRGSEL = TIAO5 -#define AT91C_ADC_TRGSEL_EXT (0x6 << 1) // (ADC) Selected TRGSEL = External Trigger -#define AT91C_ADC_LOWRES (0x1 << 4) // (ADC) Resolution. -#define AT91C_ADC_LOWRES_10_BIT (0x0 << 4) // (ADC) 10-bit resolution -#define AT91C_ADC_LOWRES_8_BIT (0x1 << 4) // (ADC) 8-bit resolution -#define AT91C_ADC_SLEEP (0x1 << 5) // (ADC) Sleep Mode -#define AT91C_ADC_SLEEP_NORMAL_MODE (0x0 << 5) // (ADC) Normal Mode -#define AT91C_ADC_SLEEP_MODE (0x1 << 5) // (ADC) Sleep Mode -#define AT91C_ADC_PRESCAL (0x3F << 8) // (ADC) Prescaler rate selection -#define AT91C_ADC_STARTUP (0x1F << 16) // (ADC) Startup Time -#define AT91C_ADC_SHTIM (0xF << 24) // (ADC) Sample & Hold Time -// -------- ADC_CHER : (ADC Offset: 0x10) ADC Channel Enable Register -------- -#define AT91C_ADC_CH0 (0x1 << 0) // (ADC) Channel 0 -#define AT91C_ADC_CH1 (0x1 << 1) // (ADC) Channel 1 -#define AT91C_ADC_CH2 (0x1 << 2) // (ADC) Channel 2 -#define AT91C_ADC_CH3 (0x1 << 3) // (ADC) Channel 3 -#define AT91C_ADC_CH4 (0x1 << 4) // (ADC) Channel 4 -#define AT91C_ADC_CH5 (0x1 << 5) // (ADC) Channel 5 -#define AT91C_ADC_CH6 (0x1 << 6) // (ADC) Channel 6 -#define AT91C_ADC_CH7 (0x1 << 7) // (ADC) Channel 7 -// -------- ADC_CHDR : (ADC Offset: 0x14) ADC Channel Disable Register -------- -// -------- ADC_CHSR : (ADC Offset: 0x18) ADC Channel Status Register -------- -// -------- ADC_SR : (ADC Offset: 0x1c) ADC Status Register -------- -#define AT91C_ADC_EOC0 (0x1 << 0) // (ADC) End of Conversion -#define AT91C_ADC_EOC1 (0x1 << 1) // (ADC) End of Conversion -#define AT91C_ADC_EOC2 (0x1 << 2) // (ADC) End of Conversion -#define AT91C_ADC_EOC3 (0x1 << 3) // (ADC) End of Conversion -#define AT91C_ADC_EOC4 (0x1 << 4) // (ADC) End of Conversion -#define AT91C_ADC_EOC5 (0x1 << 5) // (ADC) End of Conversion -#define AT91C_ADC_EOC6 (0x1 << 6) // (ADC) End of Conversion -#define AT91C_ADC_EOC7 (0x1 << 7) // (ADC) End of Conversion -#define AT91C_ADC_OVRE0 (0x1 << 8) // (ADC) Overrun Error -#define AT91C_ADC_OVRE1 (0x1 << 9) // (ADC) Overrun Error -#define AT91C_ADC_OVRE2 (0x1 << 10) // (ADC) Overrun Error -#define AT91C_ADC_OVRE3 (0x1 << 11) // (ADC) Overrun Error -#define AT91C_ADC_OVRE4 (0x1 << 12) // (ADC) Overrun Error -#define AT91C_ADC_OVRE5 (0x1 << 13) // (ADC) Overrun Error -#define AT91C_ADC_OVRE6 (0x1 << 14) // (ADC) Overrun Error -#define AT91C_ADC_OVRE7 (0x1 << 15) // (ADC) Overrun Error -#define AT91C_ADC_DRDY (0x1 << 16) // (ADC) Data Ready -#define AT91C_ADC_GOVRE (0x1 << 17) // (ADC) General Overrun -#define AT91C_ADC_ENDRX (0x1 << 18) // (ADC) End of Receiver Transfer -#define AT91C_ADC_RXBUFF (0x1 << 19) // (ADC) RXBUFF Interrupt -// -------- ADC_LCDR : (ADC Offset: 0x20) ADC Last Converted Data Register -------- -#define AT91C_ADC_LDATA (0x3FF << 0) // (ADC) Last Data Converted -// -------- ADC_IER : (ADC Offset: 0x24) ADC Interrupt Enable Register -------- -// -------- ADC_IDR : (ADC Offset: 0x28) ADC Interrupt Disable Register -------- -// -------- ADC_IMR : (ADC Offset: 0x2c) ADC Interrupt Mask Register -------- -// -------- ADC_CDR0 : (ADC Offset: 0x30) ADC Channel Data Register 0 -------- -#define AT91C_ADC_DATA (0x3FF << 0) // (ADC) Converted Data -// -------- ADC_CDR1 : (ADC Offset: 0x34) ADC Channel Data Register 1 -------- -// -------- ADC_CDR2 : (ADC Offset: 0x38) ADC Channel Data Register 2 -------- -// -------- ADC_CDR3 : (ADC Offset: 0x3c) ADC Channel Data Register 3 -------- -// -------- ADC_CDR4 : (ADC Offset: 0x40) ADC Channel Data Register 4 -------- -// -------- ADC_CDR5 : (ADC Offset: 0x44) ADC Channel Data Register 5 -------- -// -------- ADC_CDR6 : (ADC Offset: 0x48) ADC Channel Data Register 6 -------- -// -------- ADC_CDR7 : (ADC Offset: 0x4c) ADC Channel Data Register 7 -------- +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR Analog to Digital Convertor */ +/* ***************************************************************************** */ +/* *** Register offset in AT91S_ADC structure *** */ +#define ADC_CR ( 0 ) /* ADC Control Register */ +#define ADC_MR ( 4 ) /* ADC Mode Register */ +#define ADC_CHER ( 16 ) /* ADC Channel Enable Register */ +#define ADC_CHDR ( 20 ) /* ADC Channel Disable Register */ +#define ADC_CHSR ( 24 ) /* ADC Channel Status Register */ +#define ADC_SR ( 28 ) /* ADC Status Register */ +#define ADC_LCDR ( 32 ) /* ADC Last Converted Data Register */ +#define ADC_IER ( 36 ) /* ADC Interrupt Enable Register */ +#define ADC_IDR ( 40 ) /* ADC Interrupt Disable Register */ +#define ADC_IMR ( 44 ) /* ADC Interrupt Mask Register */ +#define ADC_CDR0 ( 48 ) /* ADC Channel Data Register 0 */ +#define ADC_CDR1 ( 52 ) /* ADC Channel Data Register 1 */ +#define ADC_CDR2 ( 56 ) /* ADC Channel Data Register 2 */ +#define ADC_CDR3 ( 60 ) /* ADC Channel Data Register 3 */ +#define ADC_CDR4 ( 64 ) /* ADC Channel Data Register 4 */ +#define ADC_CDR5 ( 68 ) /* ADC Channel Data Register 5 */ +#define ADC_CDR6 ( 72 ) /* ADC Channel Data Register 6 */ +#define ADC_CDR7 ( 76 ) /* ADC Channel Data Register 7 */ +#define ADC_RPR ( 256 ) /* Receive Pointer Register */ +#define ADC_RCR ( 260 ) /* Receive Counter Register */ +#define ADC_TPR ( 264 ) /* Transmit Pointer Register */ +#define ADC_TCR ( 268 ) /* Transmit Counter Register */ +#define ADC_RNPR ( 272 ) /* Receive Next Pointer Register */ +#define ADC_RNCR ( 276 ) /* Receive Next Counter Register */ +#define ADC_TNPR ( 280 ) /* Transmit Next Pointer Register */ +#define ADC_TNCR ( 284 ) /* Transmit Next Counter Register */ +#define ADC_PTCR ( 288 ) /* PDC Transfer Control Register */ +#define ADC_PTSR ( 292 ) /* PDC Transfer Status Register */ +/* -------- ADC_CR : (ADC Offset: 0x0) ADC Control Register -------- */ +#define AT91C_ADC_SWRST ( 0x1 << 0 ) /* (ADC) Software Reset */ +#define AT91C_ADC_START ( 0x1 << 1 ) /* (ADC) Start Conversion */ +/* -------- ADC_MR : (ADC Offset: 0x4) ADC Mode Register -------- */ +#define AT91C_ADC_TRGEN ( 0x1 << 0 ) /* (ADC) Trigger Enable */ +#define AT91C_ADC_TRGEN_DIS ( 0x0 ) /* (ADC) Hardware triggers are disabled. Starting a conversion is only possible by software */ +#define AT91C_ADC_TRGEN_EN ( 0x1 ) /* (ADC) Hardware trigger selected by TRGSEL field is enabled. */ +#define AT91C_ADC_TRGSEL ( 0x7 << 1 ) /* (ADC) Trigger Selection */ +#define AT91C_ADC_TRGSEL_TIOA0 ( 0x0 << 1 ) /* (ADC) Selected TRGSEL = TIAO0 */ +#define AT91C_ADC_TRGSEL_TIOA1 ( 0x1 << 1 ) /* (ADC) Selected TRGSEL = TIAO1 */ +#define AT91C_ADC_TRGSEL_TIOA2 ( 0x2 << 1 ) /* (ADC) Selected TRGSEL = TIAO2 */ +#define AT91C_ADC_TRGSEL_TIOA3 ( 0x3 << 1 ) /* (ADC) Selected TRGSEL = TIAO3 */ +#define AT91C_ADC_TRGSEL_TIOA4 ( 0x4 << 1 ) /* (ADC) Selected TRGSEL = TIAO4 */ +#define AT91C_ADC_TRGSEL_TIOA5 ( 0x5 << 1 ) /* (ADC) Selected TRGSEL = TIAO5 */ +#define AT91C_ADC_TRGSEL_EXT ( 0x6 << 1 ) /* (ADC) Selected TRGSEL = External Trigger */ +#define AT91C_ADC_LOWRES ( 0x1 << 4 ) /* (ADC) Resolution. */ +#define AT91C_ADC_LOWRES_10_BIT ( 0x0 << 4 ) /* (ADC) 10-bit resolution */ +#define AT91C_ADC_LOWRES_8_BIT ( 0x1 << 4 ) /* (ADC) 8-bit resolution */ +#define AT91C_ADC_SLEEP ( 0x1 << 5 ) /* (ADC) Sleep Mode */ +#define AT91C_ADC_SLEEP_NORMAL_MODE ( 0x0 << 5 ) /* (ADC) Normal Mode */ +#define AT91C_ADC_SLEEP_MODE ( 0x1 << 5 ) /* (ADC) Sleep Mode */ +#define AT91C_ADC_PRESCAL ( 0x3F << 8 ) /* (ADC) Prescaler rate selection */ +#define AT91C_ADC_STARTUP ( 0x1F << 16 ) /* (ADC) Startup Time */ +#define AT91C_ADC_SHTIM ( 0xF << 24 ) /* (ADC) Sample & Hold Time */ +/* -------- ADC_CHER : (ADC Offset: 0x10) ADC Channel Enable Register -------- */ +#define AT91C_ADC_CH0 ( 0x1 << 0 ) /* (ADC) Channel 0 */ +#define AT91C_ADC_CH1 ( 0x1 << 1 ) /* (ADC) Channel 1 */ +#define AT91C_ADC_CH2 ( 0x1 << 2 ) /* (ADC) Channel 2 */ +#define AT91C_ADC_CH3 ( 0x1 << 3 ) /* (ADC) Channel 3 */ +#define AT91C_ADC_CH4 ( 0x1 << 4 ) /* (ADC) Channel 4 */ +#define AT91C_ADC_CH5 ( 0x1 << 5 ) /* (ADC) Channel 5 */ +#define AT91C_ADC_CH6 ( 0x1 << 6 ) /* (ADC) Channel 6 */ +#define AT91C_ADC_CH7 ( 0x1 << 7 ) /* (ADC) Channel 7 */ +/* -------- ADC_CHDR : (ADC Offset: 0x14) ADC Channel Disable Register -------- */ +/* -------- ADC_CHSR : (ADC Offset: 0x18) ADC Channel Status Register -------- */ +/* -------- ADC_SR : (ADC Offset: 0x1c) ADC Status Register -------- */ +#define AT91C_ADC_EOC0 ( 0x1 << 0 ) /* (ADC) End of Conversion */ +#define AT91C_ADC_EOC1 ( 0x1 << 1 ) /* (ADC) End of Conversion */ +#define AT91C_ADC_EOC2 ( 0x1 << 2 ) /* (ADC) End of Conversion */ +#define AT91C_ADC_EOC3 ( 0x1 << 3 ) /* (ADC) End of Conversion */ +#define AT91C_ADC_EOC4 ( 0x1 << 4 ) /* (ADC) End of Conversion */ +#define AT91C_ADC_EOC5 ( 0x1 << 5 ) /* (ADC) End of Conversion */ +#define AT91C_ADC_EOC6 ( 0x1 << 6 ) /* (ADC) End of Conversion */ +#define AT91C_ADC_EOC7 ( 0x1 << 7 ) /* (ADC) End of Conversion */ +#define AT91C_ADC_OVRE0 ( 0x1 << 8 ) /* (ADC) Overrun Error */ +#define AT91C_ADC_OVRE1 ( 0x1 << 9 ) /* (ADC) Overrun Error */ +#define AT91C_ADC_OVRE2 ( 0x1 << 10 ) /* (ADC) Overrun Error */ +#define AT91C_ADC_OVRE3 ( 0x1 << 11 ) /* (ADC) Overrun Error */ +#define AT91C_ADC_OVRE4 ( 0x1 << 12 ) /* (ADC) Overrun Error */ +#define AT91C_ADC_OVRE5 ( 0x1 << 13 ) /* (ADC) Overrun Error */ +#define AT91C_ADC_OVRE6 ( 0x1 << 14 ) /* (ADC) Overrun Error */ +#define AT91C_ADC_OVRE7 ( 0x1 << 15 ) /* (ADC) Overrun Error */ +#define AT91C_ADC_DRDY ( 0x1 << 16 ) /* (ADC) Data Ready */ +#define AT91C_ADC_GOVRE ( 0x1 << 17 ) /* (ADC) General Overrun */ +#define AT91C_ADC_ENDRX ( 0x1 << 18 ) /* (ADC) End of Receiver Transfer */ +#define AT91C_ADC_RXBUFF ( 0x1 << 19 ) /* (ADC) RXBUFF Interrupt */ +/* -------- ADC_LCDR : (ADC Offset: 0x20) ADC Last Converted Data Register -------- */ +#define AT91C_ADC_LDATA ( 0x3FF << 0 ) /* (ADC) Last Data Converted */ +/* -------- ADC_IER : (ADC Offset: 0x24) ADC Interrupt Enable Register -------- */ +/* -------- ADC_IDR : (ADC Offset: 0x28) ADC Interrupt Disable Register -------- */ +/* -------- ADC_IMR : (ADC Offset: 0x2c) ADC Interrupt Mask Register -------- */ +/* -------- ADC_CDR0 : (ADC Offset: 0x30) ADC Channel Data Register 0 -------- */ +#define AT91C_ADC_DATA ( 0x3FF << 0 ) /* (ADC) Converted Data */ +/* -------- ADC_CDR1 : (ADC Offset: 0x34) ADC Channel Data Register 1 -------- */ +/* -------- ADC_CDR2 : (ADC Offset: 0x38) ADC Channel Data Register 2 -------- */ +/* -------- ADC_CDR3 : (ADC Offset: 0x3c) ADC Channel Data Register 3 -------- */ +/* -------- ADC_CDR4 : (ADC Offset: 0x40) ADC Channel Data Register 4 -------- */ +/* -------- ADC_CDR5 : (ADC Offset: 0x44) ADC Channel Data Register 5 -------- */ +/* -------- ADC_CDR6 : (ADC Offset: 0x48) ADC Channel Data Register 6 -------- */ +/* -------- ADC_CDR7 : (ADC Offset: 0x4c) ADC Channel Data Register 7 -------- */ -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Advanced Encryption Standard -// ***************************************************************************** -// *** Register offset in AT91S_AES structure *** -#define AES_CR ( 0) // Control Register -#define AES_MR ( 4) // Mode Register -#define AES_IER (16) // Interrupt Enable Register -#define AES_IDR (20) // Interrupt Disable Register -#define AES_IMR (24) // Interrupt Mask Register -#define AES_ISR (28) // Interrupt Status Register -#define AES_KEYWxR (32) // Key Word x Register -#define AES_IDATAxR (64) // Input Data x Register -#define AES_ODATAxR (80) // Output Data x Register -#define AES_IVxR (96) // Initialization Vector x Register -#define AES_VR (252) // AES Version Register -#define AES_RPR (256) // Receive Pointer Register -#define AES_RCR (260) // Receive Counter Register -#define AES_TPR (264) // Transmit Pointer Register -#define AES_TCR (268) // Transmit Counter Register -#define AES_RNPR (272) // Receive Next Pointer Register -#define AES_RNCR (276) // Receive Next Counter Register -#define AES_TNPR (280) // Transmit Next Pointer Register -#define AES_TNCR (284) // Transmit Next Counter Register -#define AES_PTCR (288) // PDC Transfer Control Register -#define AES_PTSR (292) // PDC Transfer Status Register -// -------- AES_CR : (AES Offset: 0x0) Control Register -------- -#define AT91C_AES_START (0x1 << 0) // (AES) Starts Processing -#define AT91C_AES_SWRST (0x1 << 8) // (AES) Software Reset -#define AT91C_AES_LOADSEED (0x1 << 16) // (AES) Random Number Generator Seed Loading -// -------- AES_MR : (AES Offset: 0x4) Mode Register -------- -#define AT91C_AES_CIPHER (0x1 << 0) // (AES) Processing Mode -#define AT91C_AES_PROCDLY (0xF << 4) // (AES) Processing Delay -#define AT91C_AES_SMOD (0x3 << 8) // (AES) Start Mode -#define AT91C_AES_SMOD_MANUAL (0x0 << 8) // (AES) Manual Mode: The START bit in register AES_CR must be set to begin encryption or decryption. -#define AT91C_AES_SMOD_AUTO (0x1 << 8) // (AES) Auto Mode: no action in AES_CR is necessary (cf datasheet). -#define AT91C_AES_SMOD_PDC (0x2 << 8) // (AES) PDC Mode (cf datasheet). -#define AT91C_AES_OPMOD (0x7 << 12) // (AES) Operation Mode -#define AT91C_AES_OPMOD_ECB (0x0 << 12) // (AES) ECB Electronic CodeBook mode. -#define AT91C_AES_OPMOD_CBC (0x1 << 12) // (AES) CBC Cipher Block Chaining mode. -#define AT91C_AES_OPMOD_OFB (0x2 << 12) // (AES) OFB Output Feedback mode. -#define AT91C_AES_OPMOD_CFB (0x3 << 12) // (AES) CFB Cipher Feedback mode. -#define AT91C_AES_OPMOD_CTR (0x4 << 12) // (AES) CTR Counter mode. -#define AT91C_AES_LOD (0x1 << 15) // (AES) Last Output Data Mode -#define AT91C_AES_CFBS (0x7 << 16) // (AES) Cipher Feedback Data Size -#define AT91C_AES_CFBS_128_BIT (0x0 << 16) // (AES) 128-bit. -#define AT91C_AES_CFBS_64_BIT (0x1 << 16) // (AES) 64-bit. -#define AT91C_AES_CFBS_32_BIT (0x2 << 16) // (AES) 32-bit. -#define AT91C_AES_CFBS_16_BIT (0x3 << 16) // (AES) 16-bit. -#define AT91C_AES_CFBS_8_BIT (0x4 << 16) // (AES) 8-bit. -#define AT91C_AES_CKEY (0xF << 20) // (AES) Countermeasure Key -#define AT91C_AES_CTYPE (0x1F << 24) // (AES) Countermeasure Type -#define AT91C_AES_CTYPE_TYPE1_EN (0x1 << 24) // (AES) Countermeasure type 1 is enabled. -#define AT91C_AES_CTYPE_TYPE2_EN (0x2 << 24) // (AES) Countermeasure type 2 is enabled. -#define AT91C_AES_CTYPE_TYPE3_EN (0x4 << 24) // (AES) Countermeasure type 3 is enabled. -#define AT91C_AES_CTYPE_TYPE4_EN (0x8 << 24) // (AES) Countermeasure type 4 is enabled. -#define AT91C_AES_CTYPE_TYPE5_EN (0x10 << 24) // (AES) Countermeasure type 5 is enabled. -// -------- AES_IER : (AES Offset: 0x10) Interrupt Enable Register -------- -#define AT91C_AES_DATRDY (0x1 << 0) // (AES) DATRDY -#define AT91C_AES_ENDRX (0x1 << 1) // (AES) PDC Read Buffer End -#define AT91C_AES_ENDTX (0x1 << 2) // (AES) PDC Write Buffer End -#define AT91C_AES_RXBUFF (0x1 << 3) // (AES) PDC Read Buffer Full -#define AT91C_AES_TXBUFE (0x1 << 4) // (AES) PDC Write Buffer Empty -#define AT91C_AES_URAD (0x1 << 8) // (AES) Unspecified Register Access Detection -// -------- AES_IDR : (AES Offset: 0x14) Interrupt Disable Register -------- -// -------- AES_IMR : (AES Offset: 0x18) Interrupt Mask Register -------- -// -------- AES_ISR : (AES Offset: 0x1c) Interrupt Status Register -------- -#define AT91C_AES_URAT (0x7 << 12) // (AES) Unspecified Register Access Type Status -#define AT91C_AES_URAT_IN_DAT_WRITE_DATPROC (0x0 << 12) // (AES) Input data register written during the data processing in PDC mode. -#define AT91C_AES_URAT_OUT_DAT_READ_DATPROC (0x1 << 12) // (AES) Output data register read during the data processing. -#define AT91C_AES_URAT_MODEREG_WRITE_DATPROC (0x2 << 12) // (AES) Mode register written during the data processing. -#define AT91C_AES_URAT_OUT_DAT_READ_SUBKEY (0x3 << 12) // (AES) Output data register read during the sub-keys generation. -#define AT91C_AES_URAT_MODEREG_WRITE_SUBKEY (0x4 << 12) // (AES) Mode register written during the sub-keys generation. -#define AT91C_AES_URAT_WO_REG_READ (0x5 << 12) // (AES) Write-only register read access. +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR Advanced Encryption Standard */ +/* ***************************************************************************** */ +/* *** Register offset in AT91S_AES structure *** */ +#define AES_CR ( 0 ) /* Control Register */ +#define AES_MR ( 4 ) /* Mode Register */ +#define AES_IER ( 16 ) /* Interrupt Enable Register */ +#define AES_IDR ( 20 ) /* Interrupt Disable Register */ +#define AES_IMR ( 24 ) /* Interrupt Mask Register */ +#define AES_ISR ( 28 ) /* Interrupt Status Register */ +#define AES_KEYWxR ( 32 ) /* Key Word x Register */ +#define AES_IDATAxR ( 64 ) /* Input Data x Register */ +#define AES_ODATAxR ( 80 ) /* Output Data x Register */ +#define AES_IVxR ( 96 ) /* Initialization Vector x Register */ +#define AES_VR ( 252 ) /* AES Version Register */ +#define AES_RPR ( 256 ) /* Receive Pointer Register */ +#define AES_RCR ( 260 ) /* Receive Counter Register */ +#define AES_TPR ( 264 ) /* Transmit Pointer Register */ +#define AES_TCR ( 268 ) /* Transmit Counter Register */ +#define AES_RNPR ( 272 ) /* Receive Next Pointer Register */ +#define AES_RNCR ( 276 ) /* Receive Next Counter Register */ +#define AES_TNPR ( 280 ) /* Transmit Next Pointer Register */ +#define AES_TNCR ( 284 ) /* Transmit Next Counter Register */ +#define AES_PTCR ( 288 ) /* PDC Transfer Control Register */ +#define AES_PTSR ( 292 ) /* PDC Transfer Status Register */ +/* -------- AES_CR : (AES Offset: 0x0) Control Register -------- */ +#define AT91C_AES_START ( 0x1 << 0 ) /* (AES) Starts Processing */ +#define AT91C_AES_SWRST ( 0x1 << 8 ) /* (AES) Software Reset */ +#define AT91C_AES_LOADSEED ( 0x1 << 16 ) /* (AES) Random Number Generator Seed Loading */ +/* -------- AES_MR : (AES Offset: 0x4) Mode Register -------- */ +#define AT91C_AES_CIPHER ( 0x1 << 0 ) /* (AES) Processing Mode */ +#define AT91C_AES_PROCDLY ( 0xF << 4 ) /* (AES) Processing Delay */ +#define AT91C_AES_SMOD ( 0x3 << 8 ) /* (AES) Start Mode */ +#define AT91C_AES_SMOD_MANUAL ( 0x0 << 8 ) /* (AES) Manual Mode: The START bit in register AES_CR must be set to begin encryption or decryption. */ +#define AT91C_AES_SMOD_AUTO ( 0x1 << 8 ) /* (AES) Auto Mode: no action in AES_CR is necessary (cf datasheet). */ +#define AT91C_AES_SMOD_PDC ( 0x2 << 8 ) /* (AES) PDC Mode (cf datasheet). */ +#define AT91C_AES_OPMOD ( 0x7 << 12 ) /* (AES) Operation Mode */ +#define AT91C_AES_OPMOD_ECB ( 0x0 << 12 ) /* (AES) ECB Electronic CodeBook mode. */ +#define AT91C_AES_OPMOD_CBC ( 0x1 << 12 ) /* (AES) CBC Cipher Block Chaining mode. */ +#define AT91C_AES_OPMOD_OFB ( 0x2 << 12 ) /* (AES) OFB Output Feedback mode. */ +#define AT91C_AES_OPMOD_CFB ( 0x3 << 12 ) /* (AES) CFB Cipher Feedback mode. */ +#define AT91C_AES_OPMOD_CTR ( 0x4 << 12 ) /* (AES) CTR Counter mode. */ +#define AT91C_AES_LOD ( 0x1 << 15 ) /* (AES) Last Output Data Mode */ +#define AT91C_AES_CFBS ( 0x7 << 16 ) /* (AES) Cipher Feedback Data Size */ +#define AT91C_AES_CFBS_128_BIT ( 0x0 << 16 ) /* (AES) 128-bit. */ +#define AT91C_AES_CFBS_64_BIT ( 0x1 << 16 ) /* (AES) 64-bit. */ +#define AT91C_AES_CFBS_32_BIT ( 0x2 << 16 ) /* (AES) 32-bit. */ +#define AT91C_AES_CFBS_16_BIT ( 0x3 << 16 ) /* (AES) 16-bit. */ +#define AT91C_AES_CFBS_8_BIT ( 0x4 << 16 ) /* (AES) 8-bit. */ +#define AT91C_AES_CKEY ( 0xF << 20 ) /* (AES) Countermeasure Key */ +#define AT91C_AES_CTYPE ( 0x1F << 24 ) /* (AES) Countermeasure Type */ +#define AT91C_AES_CTYPE_TYPE1_EN ( 0x1 << 24 ) /* (AES) Countermeasure type 1 is enabled. */ +#define AT91C_AES_CTYPE_TYPE2_EN ( 0x2 << 24 ) /* (AES) Countermeasure type 2 is enabled. */ +#define AT91C_AES_CTYPE_TYPE3_EN ( 0x4 << 24 ) /* (AES) Countermeasure type 3 is enabled. */ +#define AT91C_AES_CTYPE_TYPE4_EN ( 0x8 << 24 ) /* (AES) Countermeasure type 4 is enabled. */ +#define AT91C_AES_CTYPE_TYPE5_EN ( 0x10 << 24 ) /* (AES) Countermeasure type 5 is enabled. */ +/* -------- AES_IER : (AES Offset: 0x10) Interrupt Enable Register -------- */ +#define AT91C_AES_DATRDY ( 0x1 << 0 ) /* (AES) DATRDY */ +#define AT91C_AES_ENDRX ( 0x1 << 1 ) /* (AES) PDC Read Buffer End */ +#define AT91C_AES_ENDTX ( 0x1 << 2 ) /* (AES) PDC Write Buffer End */ +#define AT91C_AES_RXBUFF ( 0x1 << 3 ) /* (AES) PDC Read Buffer Full */ +#define AT91C_AES_TXBUFE ( 0x1 << 4 ) /* (AES) PDC Write Buffer Empty */ +#define AT91C_AES_URAD ( 0x1 << 8 ) /* (AES) Unspecified Register Access Detection */ +/* -------- AES_IDR : (AES Offset: 0x14) Interrupt Disable Register -------- */ +/* -------- AES_IMR : (AES Offset: 0x18) Interrupt Mask Register -------- */ +/* -------- AES_ISR : (AES Offset: 0x1c) Interrupt Status Register -------- */ +#define AT91C_AES_URAT ( 0x7 << 12 ) /* (AES) Unspecified Register Access Type Status */ +#define AT91C_AES_URAT_IN_DAT_WRITE_DATPROC ( 0x0 << 12 ) /* (AES) Input data register written during the data processing in PDC mode. */ +#define AT91C_AES_URAT_OUT_DAT_READ_DATPROC ( 0x1 << 12 ) /* (AES) Output data register read during the data processing. */ +#define AT91C_AES_URAT_MODEREG_WRITE_DATPROC ( 0x2 << 12 ) /* (AES) Mode register written during the data processing. */ +#define AT91C_AES_URAT_OUT_DAT_READ_SUBKEY ( 0x3 << 12 ) /* (AES) Output data register read during the sub-keys generation. */ +#define AT91C_AES_URAT_MODEREG_WRITE_SUBKEY ( 0x4 << 12 ) /* (AES) Mode register written during the sub-keys generation. */ +#define AT91C_AES_URAT_WO_REG_READ ( 0x5 << 12 ) /* (AES) Write-only register read access. */ -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Triple Data Encryption Standard -// ***************************************************************************** -// *** Register offset in AT91S_TDES structure *** -#define TDES_CR ( 0) // Control Register -#define TDES_MR ( 4) // Mode Register -#define TDES_IER (16) // Interrupt Enable Register -#define TDES_IDR (20) // Interrupt Disable Register -#define TDES_IMR (24) // Interrupt Mask Register -#define TDES_ISR (28) // Interrupt Status Register -#define TDES_KEY1WxR (32) // Key 1 Word x Register -#define TDES_KEY2WxR (40) // Key 2 Word x Register -#define TDES_KEY3WxR (48) // Key 3 Word x Register -#define TDES_IDATAxR (64) // Input Data x Register -#define TDES_ODATAxR (80) // Output Data x Register -#define TDES_IVxR (96) // Initialization Vector x Register -#define TDES_VR (252) // TDES Version Register -#define TDES_RPR (256) // Receive Pointer Register -#define TDES_RCR (260) // Receive Counter Register -#define TDES_TPR (264) // Transmit Pointer Register -#define TDES_TCR (268) // Transmit Counter Register -#define TDES_RNPR (272) // Receive Next Pointer Register -#define TDES_RNCR (276) // Receive Next Counter Register -#define TDES_TNPR (280) // Transmit Next Pointer Register -#define TDES_TNCR (284) // Transmit Next Counter Register -#define TDES_PTCR (288) // PDC Transfer Control Register -#define TDES_PTSR (292) // PDC Transfer Status Register -// -------- TDES_CR : (TDES Offset: 0x0) Control Register -------- -#define AT91C_TDES_START (0x1 << 0) // (TDES) Starts Processing -#define AT91C_TDES_SWRST (0x1 << 8) // (TDES) Software Reset -// -------- TDES_MR : (TDES Offset: 0x4) Mode Register -------- -#define AT91C_TDES_CIPHER (0x1 << 0) // (TDES) Processing Mode -#define AT91C_TDES_TDESMOD (0x1 << 1) // (TDES) Single or Triple DES Mode -#define AT91C_TDES_KEYMOD (0x1 << 4) // (TDES) Key Mode -#define AT91C_TDES_SMOD (0x3 << 8) // (TDES) Start Mode -#define AT91C_TDES_SMOD_MANUAL (0x0 << 8) // (TDES) Manual Mode: The START bit in register TDES_CR must be set to begin encryption or decryption. -#define AT91C_TDES_SMOD_AUTO (0x1 << 8) // (TDES) Auto Mode: no action in TDES_CR is necessary (cf datasheet). -#define AT91C_TDES_SMOD_PDC (0x2 << 8) // (TDES) PDC Mode (cf datasheet). -#define AT91C_TDES_OPMOD (0x3 << 12) // (TDES) Operation Mode -#define AT91C_TDES_OPMOD_ECB (0x0 << 12) // (TDES) ECB Electronic CodeBook mode. -#define AT91C_TDES_OPMOD_CBC (0x1 << 12) // (TDES) CBC Cipher Block Chaining mode. -#define AT91C_TDES_OPMOD_OFB (0x2 << 12) // (TDES) OFB Output Feedback mode. -#define AT91C_TDES_OPMOD_CFB (0x3 << 12) // (TDES) CFB Cipher Feedback mode. -#define AT91C_TDES_LOD (0x1 << 15) // (TDES) Last Output Data Mode -#define AT91C_TDES_CFBS (0x3 << 16) // (TDES) Cipher Feedback Data Size -#define AT91C_TDES_CFBS_64_BIT (0x0 << 16) // (TDES) 64-bit. -#define AT91C_TDES_CFBS_32_BIT (0x1 << 16) // (TDES) 32-bit. -#define AT91C_TDES_CFBS_16_BIT (0x2 << 16) // (TDES) 16-bit. -#define AT91C_TDES_CFBS_8_BIT (0x3 << 16) // (TDES) 8-bit. -// -------- TDES_IER : (TDES Offset: 0x10) Interrupt Enable Register -------- -#define AT91C_TDES_DATRDY (0x1 << 0) // (TDES) DATRDY -#define AT91C_TDES_ENDRX (0x1 << 1) // (TDES) PDC Read Buffer End -#define AT91C_TDES_ENDTX (0x1 << 2) // (TDES) PDC Write Buffer End -#define AT91C_TDES_RXBUFF (0x1 << 3) // (TDES) PDC Read Buffer Full -#define AT91C_TDES_TXBUFE (0x1 << 4) // (TDES) PDC Write Buffer Empty -#define AT91C_TDES_URAD (0x1 << 8) // (TDES) Unspecified Register Access Detection -// -------- TDES_IDR : (TDES Offset: 0x14) Interrupt Disable Register -------- -// -------- TDES_IMR : (TDES Offset: 0x18) Interrupt Mask Register -------- -// -------- TDES_ISR : (TDES Offset: 0x1c) Interrupt Status Register -------- -#define AT91C_TDES_URAT (0x3 << 12) // (TDES) Unspecified Register Access Type Status -#define AT91C_TDES_URAT_IN_DAT_WRITE_DATPROC (0x0 << 12) // (TDES) Input data register written during the data processing in PDC mode. -#define AT91C_TDES_URAT_OUT_DAT_READ_DATPROC (0x1 << 12) // (TDES) Output data register read during the data processing. -#define AT91C_TDES_URAT_MODEREG_WRITE_DATPROC (0x2 << 12) // (TDES) Mode register written during the data processing. -#define AT91C_TDES_URAT_WO_REG_READ (0x3 << 12) // (TDES) Write-only register read access. +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR Triple Data Encryption Standard */ +/* ***************************************************************************** */ +/* *** Register offset in AT91S_TDES structure *** */ +#define TDES_CR ( 0 ) /* Control Register */ +#define TDES_MR ( 4 ) /* Mode Register */ +#define TDES_IER ( 16 ) /* Interrupt Enable Register */ +#define TDES_IDR ( 20 ) /* Interrupt Disable Register */ +#define TDES_IMR ( 24 ) /* Interrupt Mask Register */ +#define TDES_ISR ( 28 ) /* Interrupt Status Register */ +#define TDES_KEY1WxR ( 32 ) /* Key 1 Word x Register */ +#define TDES_KEY2WxR ( 40 ) /* Key 2 Word x Register */ +#define TDES_KEY3WxR ( 48 ) /* Key 3 Word x Register */ +#define TDES_IDATAxR ( 64 ) /* Input Data x Register */ +#define TDES_ODATAxR ( 80 ) /* Output Data x Register */ +#define TDES_IVxR ( 96 ) /* Initialization Vector x Register */ +#define TDES_VR ( 252 ) /* TDES Version Register */ +#define TDES_RPR ( 256 ) /* Receive Pointer Register */ +#define TDES_RCR ( 260 ) /* Receive Counter Register */ +#define TDES_TPR ( 264 ) /* Transmit Pointer Register */ +#define TDES_TCR ( 268 ) /* Transmit Counter Register */ +#define TDES_RNPR ( 272 ) /* Receive Next Pointer Register */ +#define TDES_RNCR ( 276 ) /* Receive Next Counter Register */ +#define TDES_TNPR ( 280 ) /* Transmit Next Pointer Register */ +#define TDES_TNCR ( 284 ) /* Transmit Next Counter Register */ +#define TDES_PTCR ( 288 ) /* PDC Transfer Control Register */ +#define TDES_PTSR ( 292 ) /* PDC Transfer Status Register */ +/* -------- TDES_CR : (TDES Offset: 0x0) Control Register -------- */ +#define AT91C_TDES_START ( 0x1 << 0 ) /* (TDES) Starts Processing */ +#define AT91C_TDES_SWRST ( 0x1 << 8 ) /* (TDES) Software Reset */ +/* -------- TDES_MR : (TDES Offset: 0x4) Mode Register -------- */ +#define AT91C_TDES_CIPHER ( 0x1 << 0 ) /* (TDES) Processing Mode */ +#define AT91C_TDES_TDESMOD ( 0x1 << 1 ) /* (TDES) Single or Triple DES Mode */ +#define AT91C_TDES_KEYMOD ( 0x1 << 4 ) /* (TDES) Key Mode */ +#define AT91C_TDES_SMOD ( 0x3 << 8 ) /* (TDES) Start Mode */ +#define AT91C_TDES_SMOD_MANUAL ( 0x0 << 8 ) /* (TDES) Manual Mode: The START bit in register TDES_CR must be set to begin encryption or decryption. */ +#define AT91C_TDES_SMOD_AUTO ( 0x1 << 8 ) /* (TDES) Auto Mode: no action in TDES_CR is necessary (cf datasheet). */ +#define AT91C_TDES_SMOD_PDC ( 0x2 << 8 ) /* (TDES) PDC Mode (cf datasheet). */ +#define AT91C_TDES_OPMOD ( 0x3 << 12 ) /* (TDES) Operation Mode */ +#define AT91C_TDES_OPMOD_ECB ( 0x0 << 12 ) /* (TDES) ECB Electronic CodeBook mode. */ +#define AT91C_TDES_OPMOD_CBC ( 0x1 << 12 ) /* (TDES) CBC Cipher Block Chaining mode. */ +#define AT91C_TDES_OPMOD_OFB ( 0x2 << 12 ) /* (TDES) OFB Output Feedback mode. */ +#define AT91C_TDES_OPMOD_CFB ( 0x3 << 12 ) /* (TDES) CFB Cipher Feedback mode. */ +#define AT91C_TDES_LOD ( 0x1 << 15 ) /* (TDES) Last Output Data Mode */ +#define AT91C_TDES_CFBS ( 0x3 << 16 ) /* (TDES) Cipher Feedback Data Size */ +#define AT91C_TDES_CFBS_64_BIT ( 0x0 << 16 ) /* (TDES) 64-bit. */ +#define AT91C_TDES_CFBS_32_BIT ( 0x1 << 16 ) /* (TDES) 32-bit. */ +#define AT91C_TDES_CFBS_16_BIT ( 0x2 << 16 ) /* (TDES) 16-bit. */ +#define AT91C_TDES_CFBS_8_BIT ( 0x3 << 16 ) /* (TDES) 8-bit. */ +/* -------- TDES_IER : (TDES Offset: 0x10) Interrupt Enable Register -------- */ +#define AT91C_TDES_DATRDY ( 0x1 << 0 ) /* (TDES) DATRDY */ +#define AT91C_TDES_ENDRX ( 0x1 << 1 ) /* (TDES) PDC Read Buffer End */ +#define AT91C_TDES_ENDTX ( 0x1 << 2 ) /* (TDES) PDC Write Buffer End */ +#define AT91C_TDES_RXBUFF ( 0x1 << 3 ) /* (TDES) PDC Read Buffer Full */ +#define AT91C_TDES_TXBUFE ( 0x1 << 4 ) /* (TDES) PDC Write Buffer Empty */ +#define AT91C_TDES_URAD ( 0x1 << 8 ) /* (TDES) Unspecified Register Access Detection */ +/* -------- TDES_IDR : (TDES Offset: 0x14) Interrupt Disable Register -------- */ +/* -------- TDES_IMR : (TDES Offset: 0x18) Interrupt Mask Register -------- */ +/* -------- TDES_ISR : (TDES Offset: 0x1c) Interrupt Status Register -------- */ +#define AT91C_TDES_URAT ( 0x3 << 12 ) /* (TDES) Unspecified Register Access Type Status */ +#define AT91C_TDES_URAT_IN_DAT_WRITE_DATPROC ( 0x0 << 12 ) /* (TDES) Input data register written during the data processing in PDC mode. */ +#define AT91C_TDES_URAT_OUT_DAT_READ_DATPROC ( 0x1 << 12 ) /* (TDES) Output data register read during the data processing. */ +#define AT91C_TDES_URAT_MODEREG_WRITE_DATPROC ( 0x2 << 12 ) /* (TDES) Mode register written during the data processing. */ +#define AT91C_TDES_URAT_WO_REG_READ ( 0x3 << 12 ) /* (TDES) Write-only register read access. */ -// ***************************************************************************** -// REGISTER ADDRESS DEFINITION FOR AT91SAM7X128 -// ***************************************************************************** -// ========== Register definition for SYS peripheral ========== -// ========== Register definition for AIC peripheral ========== -#define AT91C_AIC_IVR (0xFFFFF100) // (AIC) IRQ Vector Register -#define AT91C_AIC_SMR (0xFFFFF000) // (AIC) Source Mode Register -#define AT91C_AIC_FVR (0xFFFFF104) // (AIC) FIQ Vector Register -#define AT91C_AIC_DCR (0xFFFFF138) // (AIC) Debug Control Register (Protect) -#define AT91C_AIC_EOICR (0xFFFFF130) // (AIC) End of Interrupt Command Register -#define AT91C_AIC_SVR (0xFFFFF080) // (AIC) Source Vector Register -#define AT91C_AIC_FFSR (0xFFFFF148) // (AIC) Fast Forcing Status Register -#define AT91C_AIC_ICCR (0xFFFFF128) // (AIC) Interrupt Clear Command Register -#define AT91C_AIC_ISR (0xFFFFF108) // (AIC) Interrupt Status Register -#define AT91C_AIC_IMR (0xFFFFF110) // (AIC) Interrupt Mask Register -#define AT91C_AIC_IPR (0xFFFFF10C) // (AIC) Interrupt Pending Register -#define AT91C_AIC_FFER (0xFFFFF140) // (AIC) Fast Forcing Enable Register -#define AT91C_AIC_IECR (0xFFFFF120) // (AIC) Interrupt Enable Command Register -#define AT91C_AIC_ISCR (0xFFFFF12C) // (AIC) Interrupt Set Command Register -#define AT91C_AIC_FFDR (0xFFFFF144) // (AIC) Fast Forcing Disable Register -#define AT91C_AIC_CISR (0xFFFFF114) // (AIC) Core Interrupt Status Register -#define AT91C_AIC_IDCR (0xFFFFF124) // (AIC) Interrupt Disable Command Register -#define AT91C_AIC_SPU (0xFFFFF134) // (AIC) Spurious Vector Register -// ========== Register definition for PDC_DBGU peripheral ========== -#define AT91C_DBGU_TCR (0xFFFFF30C) // (PDC_DBGU) Transmit Counter Register -#define AT91C_DBGU_RNPR (0xFFFFF310) // (PDC_DBGU) Receive Next Pointer Register -#define AT91C_DBGU_TNPR (0xFFFFF318) // (PDC_DBGU) Transmit Next Pointer Register -#define AT91C_DBGU_TPR (0xFFFFF308) // (PDC_DBGU) Transmit Pointer Register -#define AT91C_DBGU_RPR (0xFFFFF300) // (PDC_DBGU) Receive Pointer Register -#define AT91C_DBGU_RCR (0xFFFFF304) // (PDC_DBGU) Receive Counter Register -#define AT91C_DBGU_RNCR (0xFFFFF314) // (PDC_DBGU) Receive Next Counter Register -#define AT91C_DBGU_PTCR (0xFFFFF320) // (PDC_DBGU) PDC Transfer Control Register -#define AT91C_DBGU_PTSR (0xFFFFF324) // (PDC_DBGU) PDC Transfer Status Register -#define AT91C_DBGU_TNCR (0xFFFFF31C) // (PDC_DBGU) Transmit Next Counter Register -// ========== Register definition for DBGU peripheral ========== -#define AT91C_DBGU_EXID (0xFFFFF244) // (DBGU) Chip ID Extension Register -#define AT91C_DBGU_BRGR (0xFFFFF220) // (DBGU) Baud Rate Generator Register -#define AT91C_DBGU_IDR (0xFFFFF20C) // (DBGU) Interrupt Disable Register -#define AT91C_DBGU_CSR (0xFFFFF214) // (DBGU) Channel Status Register -#define AT91C_DBGU_CIDR (0xFFFFF240) // (DBGU) Chip ID Register -#define AT91C_DBGU_MR (0xFFFFF204) // (DBGU) Mode Register -#define AT91C_DBGU_IMR (0xFFFFF210) // (DBGU) Interrupt Mask Register -#define AT91C_DBGU_CR (0xFFFFF200) // (DBGU) Control Register -#define AT91C_DBGU_FNTR (0xFFFFF248) // (DBGU) Force NTRST Register -#define AT91C_DBGU_THR (0xFFFFF21C) // (DBGU) Transmitter Holding Register -#define AT91C_DBGU_RHR (0xFFFFF218) // (DBGU) Receiver Holding Register -#define AT91C_DBGU_IER (0xFFFFF208) // (DBGU) Interrupt Enable Register -// ========== Register definition for PIOA peripheral ========== -#define AT91C_PIOA_ODR (0xFFFFF414) // (PIOA) Output Disable Registerr -#define AT91C_PIOA_SODR (0xFFFFF430) // (PIOA) Set Output Data Register -#define AT91C_PIOA_ISR (0xFFFFF44C) // (PIOA) Interrupt Status Register -#define AT91C_PIOA_ABSR (0xFFFFF478) // (PIOA) AB Select Status Register -#define AT91C_PIOA_IER (0xFFFFF440) // (PIOA) Interrupt Enable Register -#define AT91C_PIOA_PPUDR (0xFFFFF460) // (PIOA) Pull-up Disable Register -#define AT91C_PIOA_IMR (0xFFFFF448) // (PIOA) Interrupt Mask Register -#define AT91C_PIOA_PER (0xFFFFF400) // (PIOA) PIO Enable Register -#define AT91C_PIOA_IFDR (0xFFFFF424) // (PIOA) Input Filter Disable Register -#define AT91C_PIOA_OWDR (0xFFFFF4A4) // (PIOA) Output Write Disable Register -#define AT91C_PIOA_MDSR (0xFFFFF458) // (PIOA) Multi-driver Status Register -#define AT91C_PIOA_IDR (0xFFFFF444) // (PIOA) Interrupt Disable Register -#define AT91C_PIOA_ODSR (0xFFFFF438) // (PIOA) Output Data Status Register -#define AT91C_PIOA_PPUSR (0xFFFFF468) // (PIOA) Pull-up Status Register -#define AT91C_PIOA_OWSR (0xFFFFF4A8) // (PIOA) Output Write Status Register -#define AT91C_PIOA_BSR (0xFFFFF474) // (PIOA) Select B Register -#define AT91C_PIOA_OWER (0xFFFFF4A0) // (PIOA) Output Write Enable Register -#define AT91C_PIOA_IFER (0xFFFFF420) // (PIOA) Input Filter Enable Register -#define AT91C_PIOA_PDSR (0xFFFFF43C) // (PIOA) Pin Data Status Register -#define AT91C_PIOA_PPUER (0xFFFFF464) // (PIOA) Pull-up Enable Register -#define AT91C_PIOA_OSR (0xFFFFF418) // (PIOA) Output Status Register -#define AT91C_PIOA_ASR (0xFFFFF470) // (PIOA) Select A Register -#define AT91C_PIOA_MDDR (0xFFFFF454) // (PIOA) Multi-driver Disable Register -#define AT91C_PIOA_CODR (0xFFFFF434) // (PIOA) Clear Output Data Register -#define AT91C_PIOA_MDER (0xFFFFF450) // (PIOA) Multi-driver Enable Register -#define AT91C_PIOA_PDR (0xFFFFF404) // (PIOA) PIO Disable Register -#define AT91C_PIOA_IFSR (0xFFFFF428) // (PIOA) Input Filter Status Register -#define AT91C_PIOA_OER (0xFFFFF410) // (PIOA) Output Enable Register -#define AT91C_PIOA_PSR (0xFFFFF408) // (PIOA) PIO Status Register -// ========== Register definition for PIOB peripheral ========== -#define AT91C_PIOB_OWDR (0xFFFFF6A4) // (PIOB) Output Write Disable Register -#define AT91C_PIOB_MDER (0xFFFFF650) // (PIOB) Multi-driver Enable Register -#define AT91C_PIOB_PPUSR (0xFFFFF668) // (PIOB) Pull-up Status Register -#define AT91C_PIOB_IMR (0xFFFFF648) // (PIOB) Interrupt Mask Register -#define AT91C_PIOB_ASR (0xFFFFF670) // (PIOB) Select A Register -#define AT91C_PIOB_PPUDR (0xFFFFF660) // (PIOB) Pull-up Disable Register -#define AT91C_PIOB_PSR (0xFFFFF608) // (PIOB) PIO Status Register -#define AT91C_PIOB_IER (0xFFFFF640) // (PIOB) Interrupt Enable Register -#define AT91C_PIOB_CODR (0xFFFFF634) // (PIOB) Clear Output Data Register -#define AT91C_PIOB_OWER (0xFFFFF6A0) // (PIOB) Output Write Enable Register -#define AT91C_PIOB_ABSR (0xFFFFF678) // (PIOB) AB Select Status Register -#define AT91C_PIOB_IFDR (0xFFFFF624) // (PIOB) Input Filter Disable Register -#define AT91C_PIOB_PDSR (0xFFFFF63C) // (PIOB) Pin Data Status Register -#define AT91C_PIOB_IDR (0xFFFFF644) // (PIOB) Interrupt Disable Register -#define AT91C_PIOB_OWSR (0xFFFFF6A8) // (PIOB) Output Write Status Register -#define AT91C_PIOB_PDR (0xFFFFF604) // (PIOB) PIO Disable Register -#define AT91C_PIOB_ODR (0xFFFFF614) // (PIOB) Output Disable Registerr -#define AT91C_PIOB_IFSR (0xFFFFF628) // (PIOB) Input Filter Status Register -#define AT91C_PIOB_PPUER (0xFFFFF664) // (PIOB) Pull-up Enable Register -#define AT91C_PIOB_SODR (0xFFFFF630) // (PIOB) Set Output Data Register -#define AT91C_PIOB_ISR (0xFFFFF64C) // (PIOB) Interrupt Status Register -#define AT91C_PIOB_ODSR (0xFFFFF638) // (PIOB) Output Data Status Register -#define AT91C_PIOB_OSR (0xFFFFF618) // (PIOB) Output Status Register -#define AT91C_PIOB_MDSR (0xFFFFF658) // (PIOB) Multi-driver Status Register -#define AT91C_PIOB_IFER (0xFFFFF620) // (PIOB) Input Filter Enable Register -#define AT91C_PIOB_BSR (0xFFFFF674) // (PIOB) Select B Register -#define AT91C_PIOB_MDDR (0xFFFFF654) // (PIOB) Multi-driver Disable Register -#define AT91C_PIOB_OER (0xFFFFF610) // (PIOB) Output Enable Register -#define AT91C_PIOB_PER (0xFFFFF600) // (PIOB) PIO Enable Register -// ========== Register definition for CKGR peripheral ========== -#define AT91C_CKGR_MOR (0xFFFFFC20) // (CKGR) Main Oscillator Register -#define AT91C_CKGR_PLLR (0xFFFFFC2C) // (CKGR) PLL Register -#define AT91C_CKGR_MCFR (0xFFFFFC24) // (CKGR) Main Clock Frequency Register -// ========== Register definition for PMC peripheral ========== -#define AT91C_PMC_IDR (0xFFFFFC64) // (PMC) Interrupt Disable Register -#define AT91C_PMC_MOR (0xFFFFFC20) // (PMC) Main Oscillator Register -#define AT91C_PMC_PLLR (0xFFFFFC2C) // (PMC) PLL Register -#define AT91C_PMC_PCER (0xFFFFFC10) // (PMC) Peripheral Clock Enable Register -#define AT91C_PMC_PCKR (0xFFFFFC40) // (PMC) Programmable Clock Register -#define AT91C_PMC_MCKR (0xFFFFFC30) // (PMC) Master Clock Register -#define AT91C_PMC_SCDR (0xFFFFFC04) // (PMC) System Clock Disable Register -#define AT91C_PMC_PCDR (0xFFFFFC14) // (PMC) Peripheral Clock Disable Register -#define AT91C_PMC_SCSR (0xFFFFFC08) // (PMC) System Clock Status Register -#define AT91C_PMC_PCSR (0xFFFFFC18) // (PMC) Peripheral Clock Status Register -#define AT91C_PMC_MCFR (0xFFFFFC24) // (PMC) Main Clock Frequency Register -#define AT91C_PMC_SCER (0xFFFFFC00) // (PMC) System Clock Enable Register -#define AT91C_PMC_IMR (0xFFFFFC6C) // (PMC) Interrupt Mask Register -#define AT91C_PMC_IER (0xFFFFFC60) // (PMC) Interrupt Enable Register -#define AT91C_PMC_SR (0xFFFFFC68) // (PMC) Status Register -// ========== Register definition for RSTC peripheral ========== -#define AT91C_RSTC_RCR (0xFFFFFD00) // (RSTC) Reset Control Register -#define AT91C_RSTC_RMR (0xFFFFFD08) // (RSTC) Reset Mode Register -#define AT91C_RSTC_RSR (0xFFFFFD04) // (RSTC) Reset Status Register -// ========== Register definition for RTTC peripheral ========== -#define AT91C_RTTC_RTSR (0xFFFFFD2C) // (RTTC) Real-time Status Register -#define AT91C_RTTC_RTMR (0xFFFFFD20) // (RTTC) Real-time Mode Register -#define AT91C_RTTC_RTVR (0xFFFFFD28) // (RTTC) Real-time Value Register -#define AT91C_RTTC_RTAR (0xFFFFFD24) // (RTTC) Real-time Alarm Register -// ========== Register definition for PITC peripheral ========== -#define AT91C_PITC_PIVR (0xFFFFFD38) // (PITC) Period Interval Value Register -#define AT91C_PITC_PISR (0xFFFFFD34) // (PITC) Period Interval Status Register -#define AT91C_PITC_PIIR (0xFFFFFD3C) // (PITC) Period Interval Image Register -#define AT91C_PITC_PIMR (0xFFFFFD30) // (PITC) Period Interval Mode Register -// ========== Register definition for WDTC peripheral ========== -#define AT91C_WDTC_WDCR (0xFFFFFD40) // (WDTC) Watchdog Control Register -#define AT91C_WDTC_WDSR (0xFFFFFD48) // (WDTC) Watchdog Status Register -#define AT91C_WDTC_WDMR (0xFFFFFD44) // (WDTC) Watchdog Mode Register -// ========== Register definition for VREG peripheral ========== -#define AT91C_VREG_MR (0xFFFFFD60) // (VREG) Voltage Regulator Mode Register -// ========== Register definition for MC peripheral ========== -#define AT91C_MC_ASR (0xFFFFFF04) // (MC) MC Abort Status Register -#define AT91C_MC_RCR (0xFFFFFF00) // (MC) MC Remap Control Register -#define AT91C_MC_FCR (0xFFFFFF64) // (MC) MC Flash Command Register -#define AT91C_MC_AASR (0xFFFFFF08) // (MC) MC Abort Address Status Register -#define AT91C_MC_FSR (0xFFFFFF68) // (MC) MC Flash Status Register -#define AT91C_MC_FMR (0xFFFFFF60) // (MC) MC Flash Mode Register -// ========== Register definition for PDC_SPI1 peripheral ========== -#define AT91C_SPI1_PTCR (0xFFFE4120) // (PDC_SPI1) PDC Transfer Control Register -#define AT91C_SPI1_RPR (0xFFFE4100) // (PDC_SPI1) Receive Pointer Register -#define AT91C_SPI1_TNCR (0xFFFE411C) // (PDC_SPI1) Transmit Next Counter Register -#define AT91C_SPI1_TPR (0xFFFE4108) // (PDC_SPI1) Transmit Pointer Register -#define AT91C_SPI1_TNPR (0xFFFE4118) // (PDC_SPI1) Transmit Next Pointer Register -#define AT91C_SPI1_TCR (0xFFFE410C) // (PDC_SPI1) Transmit Counter Register -#define AT91C_SPI1_RCR (0xFFFE4104) // (PDC_SPI1) Receive Counter Register -#define AT91C_SPI1_RNPR (0xFFFE4110) // (PDC_SPI1) Receive Next Pointer Register -#define AT91C_SPI1_RNCR (0xFFFE4114) // (PDC_SPI1) Receive Next Counter Register -#define AT91C_SPI1_PTSR (0xFFFE4124) // (PDC_SPI1) PDC Transfer Status Register -// ========== Register definition for SPI1 peripheral ========== -#define AT91C_SPI1_IMR (0xFFFE401C) // (SPI1) Interrupt Mask Register -#define AT91C_SPI1_IER (0xFFFE4014) // (SPI1) Interrupt Enable Register -#define AT91C_SPI1_MR (0xFFFE4004) // (SPI1) Mode Register -#define AT91C_SPI1_RDR (0xFFFE4008) // (SPI1) Receive Data Register -#define AT91C_SPI1_IDR (0xFFFE4018) // (SPI1) Interrupt Disable Register -#define AT91C_SPI1_SR (0xFFFE4010) // (SPI1) Status Register -#define AT91C_SPI1_TDR (0xFFFE400C) // (SPI1) Transmit Data Register -#define AT91C_SPI1_CR (0xFFFE4000) // (SPI1) Control Register -#define AT91C_SPI1_CSR (0xFFFE4030) // (SPI1) Chip Select Register -// ========== Register definition for PDC_SPI0 peripheral ========== -#define AT91C_SPI0_PTCR (0xFFFE0120) // (PDC_SPI0) PDC Transfer Control Register -#define AT91C_SPI0_TPR (0xFFFE0108) // (PDC_SPI0) Transmit Pointer Register -#define AT91C_SPI0_TCR (0xFFFE010C) // (PDC_SPI0) Transmit Counter Register -#define AT91C_SPI0_RCR (0xFFFE0104) // (PDC_SPI0) Receive Counter Register -#define AT91C_SPI0_PTSR (0xFFFE0124) // (PDC_SPI0) PDC Transfer Status Register -#define AT91C_SPI0_RNPR (0xFFFE0110) // (PDC_SPI0) Receive Next Pointer Register -#define AT91C_SPI0_RPR (0xFFFE0100) // (PDC_SPI0) Receive Pointer Register -#define AT91C_SPI0_TNCR (0xFFFE011C) // (PDC_SPI0) Transmit Next Counter Register -#define AT91C_SPI0_RNCR (0xFFFE0114) // (PDC_SPI0) Receive Next Counter Register -#define AT91C_SPI0_TNPR (0xFFFE0118) // (PDC_SPI0) Transmit Next Pointer Register -// ========== Register definition for SPI0 peripheral ========== -#define AT91C_SPI0_IER (0xFFFE0014) // (SPI0) Interrupt Enable Register -#define AT91C_SPI0_SR (0xFFFE0010) // (SPI0) Status Register -#define AT91C_SPI0_IDR (0xFFFE0018) // (SPI0) Interrupt Disable Register -#define AT91C_SPI0_CR (0xFFFE0000) // (SPI0) Control Register -#define AT91C_SPI0_MR (0xFFFE0004) // (SPI0) Mode Register -#define AT91C_SPI0_IMR (0xFFFE001C) // (SPI0) Interrupt Mask Register -#define AT91C_SPI0_TDR (0xFFFE000C) // (SPI0) Transmit Data Register -#define AT91C_SPI0_RDR (0xFFFE0008) // (SPI0) Receive Data Register -#define AT91C_SPI0_CSR (0xFFFE0030) // (SPI0) Chip Select Register -// ========== Register definition for PDC_US1 peripheral ========== -#define AT91C_US1_RNCR (0xFFFC4114) // (PDC_US1) Receive Next Counter Register -#define AT91C_US1_PTCR (0xFFFC4120) // (PDC_US1) PDC Transfer Control Register -#define AT91C_US1_TCR (0xFFFC410C) // (PDC_US1) Transmit Counter Register -#define AT91C_US1_PTSR (0xFFFC4124) // (PDC_US1) PDC Transfer Status Register -#define AT91C_US1_TNPR (0xFFFC4118) // (PDC_US1) Transmit Next Pointer Register -#define AT91C_US1_RCR (0xFFFC4104) // (PDC_US1) Receive Counter Register -#define AT91C_US1_RNPR (0xFFFC4110) // (PDC_US1) Receive Next Pointer Register -#define AT91C_US1_RPR (0xFFFC4100) // (PDC_US1) Receive Pointer Register -#define AT91C_US1_TNCR (0xFFFC411C) // (PDC_US1) Transmit Next Counter Register -#define AT91C_US1_TPR (0xFFFC4108) // (PDC_US1) Transmit Pointer Register -// ========== Register definition for US1 peripheral ========== -#define AT91C_US1_IF (0xFFFC404C) // (US1) IRDA_FILTER Register -#define AT91C_US1_NER (0xFFFC4044) // (US1) Nb Errors Register -#define AT91C_US1_RTOR (0xFFFC4024) // (US1) Receiver Time-out Register -#define AT91C_US1_CSR (0xFFFC4014) // (US1) Channel Status Register -#define AT91C_US1_IDR (0xFFFC400C) // (US1) Interrupt Disable Register -#define AT91C_US1_IER (0xFFFC4008) // (US1) Interrupt Enable Register -#define AT91C_US1_THR (0xFFFC401C) // (US1) Transmitter Holding Register -#define AT91C_US1_TTGR (0xFFFC4028) // (US1) Transmitter Time-guard Register -#define AT91C_US1_RHR (0xFFFC4018) // (US1) Receiver Holding Register -#define AT91C_US1_BRGR (0xFFFC4020) // (US1) Baud Rate Generator Register -#define AT91C_US1_IMR (0xFFFC4010) // (US1) Interrupt Mask Register -#define AT91C_US1_FIDI (0xFFFC4040) // (US1) FI_DI_Ratio Register -#define AT91C_US1_CR (0xFFFC4000) // (US1) Control Register -#define AT91C_US1_MR (0xFFFC4004) // (US1) Mode Register -// ========== Register definition for PDC_US0 peripheral ========== -#define AT91C_US0_TNPR (0xFFFC0118) // (PDC_US0) Transmit Next Pointer Register -#define AT91C_US0_RNPR (0xFFFC0110) // (PDC_US0) Receive Next Pointer Register -#define AT91C_US0_TCR (0xFFFC010C) // (PDC_US0) Transmit Counter Register -#define AT91C_US0_PTCR (0xFFFC0120) // (PDC_US0) PDC Transfer Control Register -#define AT91C_US0_PTSR (0xFFFC0124) // (PDC_US0) PDC Transfer Status Register -#define AT91C_US0_TNCR (0xFFFC011C) // (PDC_US0) Transmit Next Counter Register -#define AT91C_US0_TPR (0xFFFC0108) // (PDC_US0) Transmit Pointer Register -#define AT91C_US0_RCR (0xFFFC0104) // (PDC_US0) Receive Counter Register -#define AT91C_US0_RPR (0xFFFC0100) // (PDC_US0) Receive Pointer Register -#define AT91C_US0_RNCR (0xFFFC0114) // (PDC_US0) Receive Next Counter Register -// ========== Register definition for US0 peripheral ========== -#define AT91C_US0_BRGR (0xFFFC0020) // (US0) Baud Rate Generator Register -#define AT91C_US0_NER (0xFFFC0044) // (US0) Nb Errors Register -#define AT91C_US0_CR (0xFFFC0000) // (US0) Control Register -#define AT91C_US0_IMR (0xFFFC0010) // (US0) Interrupt Mask Register -#define AT91C_US0_FIDI (0xFFFC0040) // (US0) FI_DI_Ratio Register -#define AT91C_US0_TTGR (0xFFFC0028) // (US0) Transmitter Time-guard Register -#define AT91C_US0_MR (0xFFFC0004) // (US0) Mode Register -#define AT91C_US0_RTOR (0xFFFC0024) // (US0) Receiver Time-out Register -#define AT91C_US0_CSR (0xFFFC0014) // (US0) Channel Status Register -#define AT91C_US0_RHR (0xFFFC0018) // (US0) Receiver Holding Register -#define AT91C_US0_IDR (0xFFFC000C) // (US0) Interrupt Disable Register -#define AT91C_US0_THR (0xFFFC001C) // (US0) Transmitter Holding Register -#define AT91C_US0_IF (0xFFFC004C) // (US0) IRDA_FILTER Register -#define AT91C_US0_IER (0xFFFC0008) // (US0) Interrupt Enable Register -// ========== Register definition for PDC_SSC peripheral ========== -#define AT91C_SSC_TNCR (0xFFFD411C) // (PDC_SSC) Transmit Next Counter Register -#define AT91C_SSC_RPR (0xFFFD4100) // (PDC_SSC) Receive Pointer Register -#define AT91C_SSC_RNCR (0xFFFD4114) // (PDC_SSC) Receive Next Counter Register -#define AT91C_SSC_TPR (0xFFFD4108) // (PDC_SSC) Transmit Pointer Register -#define AT91C_SSC_PTCR (0xFFFD4120) // (PDC_SSC) PDC Transfer Control Register -#define AT91C_SSC_TCR (0xFFFD410C) // (PDC_SSC) Transmit Counter Register -#define AT91C_SSC_RCR (0xFFFD4104) // (PDC_SSC) Receive Counter Register -#define AT91C_SSC_RNPR (0xFFFD4110) // (PDC_SSC) Receive Next Pointer Register -#define AT91C_SSC_TNPR (0xFFFD4118) // (PDC_SSC) Transmit Next Pointer Register -#define AT91C_SSC_PTSR (0xFFFD4124) // (PDC_SSC) PDC Transfer Status Register -// ========== Register definition for SSC peripheral ========== -#define AT91C_SSC_RHR (0xFFFD4020) // (SSC) Receive Holding Register -#define AT91C_SSC_RSHR (0xFFFD4030) // (SSC) Receive Sync Holding Register -#define AT91C_SSC_TFMR (0xFFFD401C) // (SSC) Transmit Frame Mode Register -#define AT91C_SSC_IDR (0xFFFD4048) // (SSC) Interrupt Disable Register -#define AT91C_SSC_THR (0xFFFD4024) // (SSC) Transmit Holding Register -#define AT91C_SSC_RCMR (0xFFFD4010) // (SSC) Receive Clock ModeRegister -#define AT91C_SSC_IER (0xFFFD4044) // (SSC) Interrupt Enable Register -#define AT91C_SSC_TSHR (0xFFFD4034) // (SSC) Transmit Sync Holding Register -#define AT91C_SSC_SR (0xFFFD4040) // (SSC) Status Register -#define AT91C_SSC_CMR (0xFFFD4004) // (SSC) Clock Mode Register -#define AT91C_SSC_TCMR (0xFFFD4018) // (SSC) Transmit Clock Mode Register -#define AT91C_SSC_CR (0xFFFD4000) // (SSC) Control Register -#define AT91C_SSC_IMR (0xFFFD404C) // (SSC) Interrupt Mask Register -#define AT91C_SSC_RFMR (0xFFFD4014) // (SSC) Receive Frame Mode Register -// ========== Register definition for TWI peripheral ========== -#define AT91C_TWI_IER (0xFFFB8024) // (TWI) Interrupt Enable Register -#define AT91C_TWI_CR (0xFFFB8000) // (TWI) Control Register -#define AT91C_TWI_SR (0xFFFB8020) // (TWI) Status Register -#define AT91C_TWI_IMR (0xFFFB802C) // (TWI) Interrupt Mask Register -#define AT91C_TWI_THR (0xFFFB8034) // (TWI) Transmit Holding Register -#define AT91C_TWI_IDR (0xFFFB8028) // (TWI) Interrupt Disable Register -#define AT91C_TWI_IADR (0xFFFB800C) // (TWI) Internal Address Register -#define AT91C_TWI_MMR (0xFFFB8004) // (TWI) Master Mode Register -#define AT91C_TWI_CWGR (0xFFFB8010) // (TWI) Clock Waveform Generator Register -#define AT91C_TWI_RHR (0xFFFB8030) // (TWI) Receive Holding Register -// ========== Register definition for PWMC_CH3 peripheral ========== -#define AT91C_PWMC_CH3_CUPDR (0xFFFCC270) // (PWMC_CH3) Channel Update Register -#define AT91C_PWMC_CH3_Reserved (0xFFFCC274) // (PWMC_CH3) Reserved -#define AT91C_PWMC_CH3_CPRDR (0xFFFCC268) // (PWMC_CH3) Channel Period Register -#define AT91C_PWMC_CH3_CDTYR (0xFFFCC264) // (PWMC_CH3) Channel Duty Cycle Register -#define AT91C_PWMC_CH3_CCNTR (0xFFFCC26C) // (PWMC_CH3) Channel Counter Register -#define AT91C_PWMC_CH3_CMR (0xFFFCC260) // (PWMC_CH3) Channel Mode Register -// ========== Register definition for PWMC_CH2 peripheral ========== -#define AT91C_PWMC_CH2_Reserved (0xFFFCC254) // (PWMC_CH2) Reserved -#define AT91C_PWMC_CH2_CMR (0xFFFCC240) // (PWMC_CH2) Channel Mode Register -#define AT91C_PWMC_CH2_CCNTR (0xFFFCC24C) // (PWMC_CH2) Channel Counter Register -#define AT91C_PWMC_CH2_CPRDR (0xFFFCC248) // (PWMC_CH2) Channel Period Register -#define AT91C_PWMC_CH2_CUPDR (0xFFFCC250) // (PWMC_CH2) Channel Update Register -#define AT91C_PWMC_CH2_CDTYR (0xFFFCC244) // (PWMC_CH2) Channel Duty Cycle Register -// ========== Register definition for PWMC_CH1 peripheral ========== -#define AT91C_PWMC_CH1_Reserved (0xFFFCC234) // (PWMC_CH1) Reserved -#define AT91C_PWMC_CH1_CUPDR (0xFFFCC230) // (PWMC_CH1) Channel Update Register -#define AT91C_PWMC_CH1_CPRDR (0xFFFCC228) // (PWMC_CH1) Channel Period Register -#define AT91C_PWMC_CH1_CCNTR (0xFFFCC22C) // (PWMC_CH1) Channel Counter Register -#define AT91C_PWMC_CH1_CDTYR (0xFFFCC224) // (PWMC_CH1) Channel Duty Cycle Register -#define AT91C_PWMC_CH1_CMR (0xFFFCC220) // (PWMC_CH1) Channel Mode Register -// ========== Register definition for PWMC_CH0 peripheral ========== -#define AT91C_PWMC_CH0_Reserved (0xFFFCC214) // (PWMC_CH0) Reserved -#define AT91C_PWMC_CH0_CPRDR (0xFFFCC208) // (PWMC_CH0) Channel Period Register -#define AT91C_PWMC_CH0_CDTYR (0xFFFCC204) // (PWMC_CH0) Channel Duty Cycle Register -#define AT91C_PWMC_CH0_CMR (0xFFFCC200) // (PWMC_CH0) Channel Mode Register -#define AT91C_PWMC_CH0_CUPDR (0xFFFCC210) // (PWMC_CH0) Channel Update Register -#define AT91C_PWMC_CH0_CCNTR (0xFFFCC20C) // (PWMC_CH0) Channel Counter Register -// ========== Register definition for PWMC peripheral ========== -#define AT91C_PWMC_IDR (0xFFFCC014) // (PWMC) PWMC Interrupt Disable Register -#define AT91C_PWMC_DIS (0xFFFCC008) // (PWMC) PWMC Disable Register -#define AT91C_PWMC_IER (0xFFFCC010) // (PWMC) PWMC Interrupt Enable Register -#define AT91C_PWMC_VR (0xFFFCC0FC) // (PWMC) PWMC Version Register -#define AT91C_PWMC_ISR (0xFFFCC01C) // (PWMC) PWMC Interrupt Status Register -#define AT91C_PWMC_SR (0xFFFCC00C) // (PWMC) PWMC Status Register -#define AT91C_PWMC_IMR (0xFFFCC018) // (PWMC) PWMC Interrupt Mask Register -#define AT91C_PWMC_MR (0xFFFCC000) // (PWMC) PWMC Mode Register -#define AT91C_PWMC_ENA (0xFFFCC004) // (PWMC) PWMC Enable Register -// ========== Register definition for UDP peripheral ========== -#define AT91C_UDP_IMR (0xFFFB0018) // (UDP) Interrupt Mask Register -#define AT91C_UDP_FADDR (0xFFFB0008) // (UDP) Function Address Register -#define AT91C_UDP_NUM (0xFFFB0000) // (UDP) Frame Number Register -#define AT91C_UDP_FDR (0xFFFB0050) // (UDP) Endpoint FIFO Data Register -#define AT91C_UDP_ISR (0xFFFB001C) // (UDP) Interrupt Status Register -#define AT91C_UDP_CSR (0xFFFB0030) // (UDP) Endpoint Control and Status Register -#define AT91C_UDP_IDR (0xFFFB0014) // (UDP) Interrupt Disable Register -#define AT91C_UDP_ICR (0xFFFB0020) // (UDP) Interrupt Clear Register -#define AT91C_UDP_RSTEP (0xFFFB0028) // (UDP) Reset Endpoint Register -#define AT91C_UDP_TXVC (0xFFFB0074) // (UDP) Transceiver Control Register -#define AT91C_UDP_GLBSTATE (0xFFFB0004) // (UDP) Global State Register -#define AT91C_UDP_IER (0xFFFB0010) // (UDP) Interrupt Enable Register -// ========== Register definition for TC0 peripheral ========== -#define AT91C_TC0_SR (0xFFFA0020) // (TC0) Status Register -#define AT91C_TC0_RC (0xFFFA001C) // (TC0) Register C -#define AT91C_TC0_RB (0xFFFA0018) // (TC0) Register B -#define AT91C_TC0_CCR (0xFFFA0000) // (TC0) Channel Control Register -#define AT91C_TC0_CMR (0xFFFA0004) // (TC0) Channel Mode Register (Capture Mode / Waveform Mode) -#define AT91C_TC0_IER (0xFFFA0024) // (TC0) Interrupt Enable Register -#define AT91C_TC0_RA (0xFFFA0014) // (TC0) Register A -#define AT91C_TC0_IDR (0xFFFA0028) // (TC0) Interrupt Disable Register -#define AT91C_TC0_CV (0xFFFA0010) // (TC0) Counter Value -#define AT91C_TC0_IMR (0xFFFA002C) // (TC0) Interrupt Mask Register -// ========== Register definition for TC1 peripheral ========== -#define AT91C_TC1_RB (0xFFFA0058) // (TC1) Register B -#define AT91C_TC1_CCR (0xFFFA0040) // (TC1) Channel Control Register -#define AT91C_TC1_IER (0xFFFA0064) // (TC1) Interrupt Enable Register -#define AT91C_TC1_IDR (0xFFFA0068) // (TC1) Interrupt Disable Register -#define AT91C_TC1_SR (0xFFFA0060) // (TC1) Status Register -#define AT91C_TC1_CMR (0xFFFA0044) // (TC1) Channel Mode Register (Capture Mode / Waveform Mode) -#define AT91C_TC1_RA (0xFFFA0054) // (TC1) Register A -#define AT91C_TC1_RC (0xFFFA005C) // (TC1) Register C -#define AT91C_TC1_IMR (0xFFFA006C) // (TC1) Interrupt Mask Register -#define AT91C_TC1_CV (0xFFFA0050) // (TC1) Counter Value -// ========== Register definition for TC2 peripheral ========== -#define AT91C_TC2_CMR (0xFFFA0084) // (TC2) Channel Mode Register (Capture Mode / Waveform Mode) -#define AT91C_TC2_CCR (0xFFFA0080) // (TC2) Channel Control Register -#define AT91C_TC2_CV (0xFFFA0090) // (TC2) Counter Value -#define AT91C_TC2_RA (0xFFFA0094) // (TC2) Register A -#define AT91C_TC2_RB (0xFFFA0098) // (TC2) Register B -#define AT91C_TC2_IDR (0xFFFA00A8) // (TC2) Interrupt Disable Register -#define AT91C_TC2_IMR (0xFFFA00AC) // (TC2) Interrupt Mask Register -#define AT91C_TC2_RC (0xFFFA009C) // (TC2) Register C -#define AT91C_TC2_IER (0xFFFA00A4) // (TC2) Interrupt Enable Register -#define AT91C_TC2_SR (0xFFFA00A0) // (TC2) Status Register -// ========== Register definition for TCB peripheral ========== -#define AT91C_TCB_BMR (0xFFFA00C4) // (TCB) TC Block Mode Register -#define AT91C_TCB_BCR (0xFFFA00C0) // (TCB) TC Block Control Register -// ========== Register definition for CAN_MB0 peripheral ========== -#define AT91C_CAN_MB0_MDL (0xFFFD0214) // (CAN_MB0) MailBox Data Low Register -#define AT91C_CAN_MB0_MAM (0xFFFD0204) // (CAN_MB0) MailBox Acceptance Mask Register -#define AT91C_CAN_MB0_MCR (0xFFFD021C) // (CAN_MB0) MailBox Control Register -#define AT91C_CAN_MB0_MID (0xFFFD0208) // (CAN_MB0) MailBox ID Register -#define AT91C_CAN_MB0_MSR (0xFFFD0210) // (CAN_MB0) MailBox Status Register -#define AT91C_CAN_MB0_MFID (0xFFFD020C) // (CAN_MB0) MailBox Family ID Register -#define AT91C_CAN_MB0_MDH (0xFFFD0218) // (CAN_MB0) MailBox Data High Register -#define AT91C_CAN_MB0_MMR (0xFFFD0200) // (CAN_MB0) MailBox Mode Register -// ========== Register definition for CAN_MB1 peripheral ========== -#define AT91C_CAN_MB1_MDL (0xFFFD0234) // (CAN_MB1) MailBox Data Low Register -#define AT91C_CAN_MB1_MID (0xFFFD0228) // (CAN_MB1) MailBox ID Register -#define AT91C_CAN_MB1_MMR (0xFFFD0220) // (CAN_MB1) MailBox Mode Register -#define AT91C_CAN_MB1_MSR (0xFFFD0230) // (CAN_MB1) MailBox Status Register -#define AT91C_CAN_MB1_MAM (0xFFFD0224) // (CAN_MB1) MailBox Acceptance Mask Register -#define AT91C_CAN_MB1_MDH (0xFFFD0238) // (CAN_MB1) MailBox Data High Register -#define AT91C_CAN_MB1_MCR (0xFFFD023C) // (CAN_MB1) MailBox Control Register -#define AT91C_CAN_MB1_MFID (0xFFFD022C) // (CAN_MB1) MailBox Family ID Register -// ========== Register definition for CAN_MB2 peripheral ========== -#define AT91C_CAN_MB2_MCR (0xFFFD025C) // (CAN_MB2) MailBox Control Register -#define AT91C_CAN_MB2_MDH (0xFFFD0258) // (CAN_MB2) MailBox Data High Register -#define AT91C_CAN_MB2_MID (0xFFFD0248) // (CAN_MB2) MailBox ID Register -#define AT91C_CAN_MB2_MDL (0xFFFD0254) // (CAN_MB2) MailBox Data Low Register -#define AT91C_CAN_MB2_MMR (0xFFFD0240) // (CAN_MB2) MailBox Mode Register -#define AT91C_CAN_MB2_MAM (0xFFFD0244) // (CAN_MB2) MailBox Acceptance Mask Register -#define AT91C_CAN_MB2_MFID (0xFFFD024C) // (CAN_MB2) MailBox Family ID Register -#define AT91C_CAN_MB2_MSR (0xFFFD0250) // (CAN_MB2) MailBox Status Register -// ========== Register definition for CAN_MB3 peripheral ========== -#define AT91C_CAN_MB3_MFID (0xFFFD026C) // (CAN_MB3) MailBox Family ID Register -#define AT91C_CAN_MB3_MAM (0xFFFD0264) // (CAN_MB3) MailBox Acceptance Mask Register -#define AT91C_CAN_MB3_MID (0xFFFD0268) // (CAN_MB3) MailBox ID Register -#define AT91C_CAN_MB3_MCR (0xFFFD027C) // (CAN_MB3) MailBox Control Register -#define AT91C_CAN_MB3_MMR (0xFFFD0260) // (CAN_MB3) MailBox Mode Register -#define AT91C_CAN_MB3_MSR (0xFFFD0270) // (CAN_MB3) MailBox Status Register -#define AT91C_CAN_MB3_MDL (0xFFFD0274) // (CAN_MB3) MailBox Data Low Register -#define AT91C_CAN_MB3_MDH (0xFFFD0278) // (CAN_MB3) MailBox Data High Register -// ========== Register definition for CAN_MB4 peripheral ========== -#define AT91C_CAN_MB4_MID (0xFFFD0288) // (CAN_MB4) MailBox ID Register -#define AT91C_CAN_MB4_MMR (0xFFFD0280) // (CAN_MB4) MailBox Mode Register -#define AT91C_CAN_MB4_MDH (0xFFFD0298) // (CAN_MB4) MailBox Data High Register -#define AT91C_CAN_MB4_MFID (0xFFFD028C) // (CAN_MB4) MailBox Family ID Register -#define AT91C_CAN_MB4_MSR (0xFFFD0290) // (CAN_MB4) MailBox Status Register -#define AT91C_CAN_MB4_MCR (0xFFFD029C) // (CAN_MB4) MailBox Control Register -#define AT91C_CAN_MB4_MDL (0xFFFD0294) // (CAN_MB4) MailBox Data Low Register -#define AT91C_CAN_MB4_MAM (0xFFFD0284) // (CAN_MB4) MailBox Acceptance Mask Register -// ========== Register definition for CAN_MB5 peripheral ========== -#define AT91C_CAN_MB5_MSR (0xFFFD02B0) // (CAN_MB5) MailBox Status Register -#define AT91C_CAN_MB5_MCR (0xFFFD02BC) // (CAN_MB5) MailBox Control Register -#define AT91C_CAN_MB5_MFID (0xFFFD02AC) // (CAN_MB5) MailBox Family ID Register -#define AT91C_CAN_MB5_MDH (0xFFFD02B8) // (CAN_MB5) MailBox Data High Register -#define AT91C_CAN_MB5_MID (0xFFFD02A8) // (CAN_MB5) MailBox ID Register -#define AT91C_CAN_MB5_MMR (0xFFFD02A0) // (CAN_MB5) MailBox Mode Register -#define AT91C_CAN_MB5_MDL (0xFFFD02B4) // (CAN_MB5) MailBox Data Low Register -#define AT91C_CAN_MB5_MAM (0xFFFD02A4) // (CAN_MB5) MailBox Acceptance Mask Register -// ========== Register definition for CAN_MB6 peripheral ========== -#define AT91C_CAN_MB6_MFID (0xFFFD02CC) // (CAN_MB6) MailBox Family ID Register -#define AT91C_CAN_MB6_MID (0xFFFD02C8) // (CAN_MB6) MailBox ID Register -#define AT91C_CAN_MB6_MAM (0xFFFD02C4) // (CAN_MB6) MailBox Acceptance Mask Register -#define AT91C_CAN_MB6_MSR (0xFFFD02D0) // (CAN_MB6) MailBox Status Register -#define AT91C_CAN_MB6_MDL (0xFFFD02D4) // (CAN_MB6) MailBox Data Low Register -#define AT91C_CAN_MB6_MCR (0xFFFD02DC) // (CAN_MB6) MailBox Control Register -#define AT91C_CAN_MB6_MDH (0xFFFD02D8) // (CAN_MB6) MailBox Data High Register -#define AT91C_CAN_MB6_MMR (0xFFFD02C0) // (CAN_MB6) MailBox Mode Register -// ========== Register definition for CAN_MB7 peripheral ========== -#define AT91C_CAN_MB7_MCR (0xFFFD02FC) // (CAN_MB7) MailBox Control Register -#define AT91C_CAN_MB7_MDH (0xFFFD02F8) // (CAN_MB7) MailBox Data High Register -#define AT91C_CAN_MB7_MFID (0xFFFD02EC) // (CAN_MB7) MailBox Family ID Register -#define AT91C_CAN_MB7_MDL (0xFFFD02F4) // (CAN_MB7) MailBox Data Low Register -#define AT91C_CAN_MB7_MID (0xFFFD02E8) // (CAN_MB7) MailBox ID Register -#define AT91C_CAN_MB7_MMR (0xFFFD02E0) // (CAN_MB7) MailBox Mode Register -#define AT91C_CAN_MB7_MAM (0xFFFD02E4) // (CAN_MB7) MailBox Acceptance Mask Register -#define AT91C_CAN_MB7_MSR (0xFFFD02F0) // (CAN_MB7) MailBox Status Register -// ========== Register definition for CAN peripheral ========== -#define AT91C_CAN_TCR (0xFFFD0024) // (CAN) Transfer Command Register -#define AT91C_CAN_IMR (0xFFFD000C) // (CAN) Interrupt Mask Register -#define AT91C_CAN_IER (0xFFFD0004) // (CAN) Interrupt Enable Register -#define AT91C_CAN_ECR (0xFFFD0020) // (CAN) Error Counter Register -#define AT91C_CAN_TIMESTP (0xFFFD001C) // (CAN) Time Stamp Register -#define AT91C_CAN_MR (0xFFFD0000) // (CAN) Mode Register -#define AT91C_CAN_IDR (0xFFFD0008) // (CAN) Interrupt Disable Register -#define AT91C_CAN_ACR (0xFFFD0028) // (CAN) Abort Command Register -#define AT91C_CAN_TIM (0xFFFD0018) // (CAN) Timer Register -#define AT91C_CAN_SR (0xFFFD0010) // (CAN) Status Register -#define AT91C_CAN_BR (0xFFFD0014) // (CAN) Baudrate Register -#define AT91C_CAN_VR (0xFFFD00FC) // (CAN) Version Register -// ========== Register definition for EMAC peripheral ========== -#define AT91C_EMAC_ISR (0xFFFDC024) // (EMAC) Interrupt Status Register -#define AT91C_EMAC_SA4H (0xFFFDC0B4) // (EMAC) Specific Address 4 Top, Last 2 bytes -#define AT91C_EMAC_SA1L (0xFFFDC098) // (EMAC) Specific Address 1 Bottom, First 4 bytes -#define AT91C_EMAC_ELE (0xFFFDC078) // (EMAC) Excessive Length Errors Register -#define AT91C_EMAC_LCOL (0xFFFDC05C) // (EMAC) Late Collision Register -#define AT91C_EMAC_RLE (0xFFFDC088) // (EMAC) Receive Length Field Mismatch Register -#define AT91C_EMAC_WOL (0xFFFDC0C4) // (EMAC) Wake On LAN Register -#define AT91C_EMAC_DTF (0xFFFDC058) // (EMAC) Deferred Transmission Frame Register -#define AT91C_EMAC_TUND (0xFFFDC064) // (EMAC) Transmit Underrun Error Register -#define AT91C_EMAC_NCR (0xFFFDC000) // (EMAC) Network Control Register -#define AT91C_EMAC_SA4L (0xFFFDC0B0) // (EMAC) Specific Address 4 Bottom, First 4 bytes -#define AT91C_EMAC_RSR (0xFFFDC020) // (EMAC) Receive Status Register -#define AT91C_EMAC_SA3L (0xFFFDC0A8) // (EMAC) Specific Address 3 Bottom, First 4 bytes -#define AT91C_EMAC_TSR (0xFFFDC014) // (EMAC) Transmit Status Register -#define AT91C_EMAC_IDR (0xFFFDC02C) // (EMAC) Interrupt Disable Register -#define AT91C_EMAC_RSE (0xFFFDC074) // (EMAC) Receive Symbol Errors Register -#define AT91C_EMAC_ECOL (0xFFFDC060) // (EMAC) Excessive Collision Register -#define AT91C_EMAC_TID (0xFFFDC0B8) // (EMAC) Type ID Checking Register -#define AT91C_EMAC_HRB (0xFFFDC090) // (EMAC) Hash Address Bottom[31:0] -#define AT91C_EMAC_TBQP (0xFFFDC01C) // (EMAC) Transmit Buffer Queue Pointer -#define AT91C_EMAC_USRIO (0xFFFDC0C0) // (EMAC) USER Input/Output Register -#define AT91C_EMAC_PTR (0xFFFDC038) // (EMAC) Pause Time Register -#define AT91C_EMAC_SA2H (0xFFFDC0A4) // (EMAC) Specific Address 2 Top, Last 2 bytes -#define AT91C_EMAC_ROV (0xFFFDC070) // (EMAC) Receive Overrun Errors Register -#define AT91C_EMAC_ALE (0xFFFDC054) // (EMAC) Alignment Error Register -#define AT91C_EMAC_RJA (0xFFFDC07C) // (EMAC) Receive Jabbers Register -#define AT91C_EMAC_RBQP (0xFFFDC018) // (EMAC) Receive Buffer Queue Pointer -#define AT91C_EMAC_TPF (0xFFFDC08C) // (EMAC) Transmitted Pause Frames Register -#define AT91C_EMAC_NCFGR (0xFFFDC004) // (EMAC) Network Configuration Register -#define AT91C_EMAC_HRT (0xFFFDC094) // (EMAC) Hash Address Top[63:32] -#define AT91C_EMAC_USF (0xFFFDC080) // (EMAC) Undersize Frames Register -#define AT91C_EMAC_FCSE (0xFFFDC050) // (EMAC) Frame Check Sequence Error Register -#define AT91C_EMAC_TPQ (0xFFFDC0BC) // (EMAC) Transmit Pause Quantum Register -#define AT91C_EMAC_MAN (0xFFFDC034) // (EMAC) PHY Maintenance Register -#define AT91C_EMAC_FTO (0xFFFDC040) // (EMAC) Frames Transmitted OK Register -#define AT91C_EMAC_REV (0xFFFDC0FC) // (EMAC) Revision Register -#define AT91C_EMAC_IMR (0xFFFDC030) // (EMAC) Interrupt Mask Register -#define AT91C_EMAC_SCF (0xFFFDC044) // (EMAC) Single Collision Frame Register -#define AT91C_EMAC_PFR (0xFFFDC03C) // (EMAC) Pause Frames received Register -#define AT91C_EMAC_MCF (0xFFFDC048) // (EMAC) Multiple Collision Frame Register -#define AT91C_EMAC_NSR (0xFFFDC008) // (EMAC) Network Status Register -#define AT91C_EMAC_SA2L (0xFFFDC0A0) // (EMAC) Specific Address 2 Bottom, First 4 bytes -#define AT91C_EMAC_FRO (0xFFFDC04C) // (EMAC) Frames Received OK Register -#define AT91C_EMAC_IER (0xFFFDC028) // (EMAC) Interrupt Enable Register -#define AT91C_EMAC_SA1H (0xFFFDC09C) // (EMAC) Specific Address 1 Top, Last 2 bytes -#define AT91C_EMAC_CSE (0xFFFDC068) // (EMAC) Carrier Sense Error Register -#define AT91C_EMAC_SA3H (0xFFFDC0AC) // (EMAC) Specific Address 3 Top, Last 2 bytes -#define AT91C_EMAC_RRE (0xFFFDC06C) // (EMAC) Receive Ressource Error Register -#define AT91C_EMAC_STE (0xFFFDC084) // (EMAC) SQE Test Error Register -// ========== Register definition for PDC_ADC peripheral ========== -#define AT91C_ADC_PTSR (0xFFFD8124) // (PDC_ADC) PDC Transfer Status Register -#define AT91C_ADC_PTCR (0xFFFD8120) // (PDC_ADC) PDC Transfer Control Register -#define AT91C_ADC_TNPR (0xFFFD8118) // (PDC_ADC) Transmit Next Pointer Register -#define AT91C_ADC_TNCR (0xFFFD811C) // (PDC_ADC) Transmit Next Counter Register -#define AT91C_ADC_RNPR (0xFFFD8110) // (PDC_ADC) Receive Next Pointer Register -#define AT91C_ADC_RNCR (0xFFFD8114) // (PDC_ADC) Receive Next Counter Register -#define AT91C_ADC_RPR (0xFFFD8100) // (PDC_ADC) Receive Pointer Register -#define AT91C_ADC_TCR (0xFFFD810C) // (PDC_ADC) Transmit Counter Register -#define AT91C_ADC_TPR (0xFFFD8108) // (PDC_ADC) Transmit Pointer Register -#define AT91C_ADC_RCR (0xFFFD8104) // (PDC_ADC) Receive Counter Register -// ========== Register definition for ADC peripheral ========== -#define AT91C_ADC_CDR2 (0xFFFD8038) // (ADC) ADC Channel Data Register 2 -#define AT91C_ADC_CDR3 (0xFFFD803C) // (ADC) ADC Channel Data Register 3 -#define AT91C_ADC_CDR0 (0xFFFD8030) // (ADC) ADC Channel Data Register 0 -#define AT91C_ADC_CDR5 (0xFFFD8044) // (ADC) ADC Channel Data Register 5 -#define AT91C_ADC_CHDR (0xFFFD8014) // (ADC) ADC Channel Disable Register -#define AT91C_ADC_SR (0xFFFD801C) // (ADC) ADC Status Register -#define AT91C_ADC_CDR4 (0xFFFD8040) // (ADC) ADC Channel Data Register 4 -#define AT91C_ADC_CDR1 (0xFFFD8034) // (ADC) ADC Channel Data Register 1 -#define AT91C_ADC_LCDR (0xFFFD8020) // (ADC) ADC Last Converted Data Register -#define AT91C_ADC_IDR (0xFFFD8028) // (ADC) ADC Interrupt Disable Register -#define AT91C_ADC_CR (0xFFFD8000) // (ADC) ADC Control Register -#define AT91C_ADC_CDR7 (0xFFFD804C) // (ADC) ADC Channel Data Register 7 -#define AT91C_ADC_CDR6 (0xFFFD8048) // (ADC) ADC Channel Data Register 6 -#define AT91C_ADC_IER (0xFFFD8024) // (ADC) ADC Interrupt Enable Register -#define AT91C_ADC_CHER (0xFFFD8010) // (ADC) ADC Channel Enable Register -#define AT91C_ADC_CHSR (0xFFFD8018) // (ADC) ADC Channel Status Register -#define AT91C_ADC_MR (0xFFFD8004) // (ADC) ADC Mode Register -#define AT91C_ADC_IMR (0xFFFD802C) // (ADC) ADC Interrupt Mask Register -// ========== Register definition for PDC_AES peripheral ========== -#define AT91C_AES_TPR (0xFFFA4108) // (PDC_AES) Transmit Pointer Register -#define AT91C_AES_PTCR (0xFFFA4120) // (PDC_AES) PDC Transfer Control Register -#define AT91C_AES_RNPR (0xFFFA4110) // (PDC_AES) Receive Next Pointer Register -#define AT91C_AES_TNCR (0xFFFA411C) // (PDC_AES) Transmit Next Counter Register -#define AT91C_AES_TCR (0xFFFA410C) // (PDC_AES) Transmit Counter Register -#define AT91C_AES_RCR (0xFFFA4104) // (PDC_AES) Receive Counter Register -#define AT91C_AES_RNCR (0xFFFA4114) // (PDC_AES) Receive Next Counter Register -#define AT91C_AES_TNPR (0xFFFA4118) // (PDC_AES) Transmit Next Pointer Register -#define AT91C_AES_RPR (0xFFFA4100) // (PDC_AES) Receive Pointer Register -#define AT91C_AES_PTSR (0xFFFA4124) // (PDC_AES) PDC Transfer Status Register -// ========== Register definition for AES peripheral ========== -#define AT91C_AES_IVxR (0xFFFA4060) // (AES) Initialization Vector x Register -#define AT91C_AES_MR (0xFFFA4004) // (AES) Mode Register -#define AT91C_AES_VR (0xFFFA40FC) // (AES) AES Version Register -#define AT91C_AES_ODATAxR (0xFFFA4050) // (AES) Output Data x Register -#define AT91C_AES_IDATAxR (0xFFFA4040) // (AES) Input Data x Register -#define AT91C_AES_CR (0xFFFA4000) // (AES) Control Register -#define AT91C_AES_IDR (0xFFFA4014) // (AES) Interrupt Disable Register -#define AT91C_AES_IMR (0xFFFA4018) // (AES) Interrupt Mask Register -#define AT91C_AES_IER (0xFFFA4010) // (AES) Interrupt Enable Register -#define AT91C_AES_KEYWxR (0xFFFA4020) // (AES) Key Word x Register -#define AT91C_AES_ISR (0xFFFA401C) // (AES) Interrupt Status Register -// ========== Register definition for PDC_TDES peripheral ========== -#define AT91C_TDES_RNCR (0xFFFA8114) // (PDC_TDES) Receive Next Counter Register -#define AT91C_TDES_TCR (0xFFFA810C) // (PDC_TDES) Transmit Counter Register -#define AT91C_TDES_RCR (0xFFFA8104) // (PDC_TDES) Receive Counter Register -#define AT91C_TDES_TNPR (0xFFFA8118) // (PDC_TDES) Transmit Next Pointer Register -#define AT91C_TDES_RNPR (0xFFFA8110) // (PDC_TDES) Receive Next Pointer Register -#define AT91C_TDES_RPR (0xFFFA8100) // (PDC_TDES) Receive Pointer Register -#define AT91C_TDES_TNCR (0xFFFA811C) // (PDC_TDES) Transmit Next Counter Register -#define AT91C_TDES_TPR (0xFFFA8108) // (PDC_TDES) Transmit Pointer Register -#define AT91C_TDES_PTSR (0xFFFA8124) // (PDC_TDES) PDC Transfer Status Register -#define AT91C_TDES_PTCR (0xFFFA8120) // (PDC_TDES) PDC Transfer Control Register -// ========== Register definition for TDES peripheral ========== -#define AT91C_TDES_KEY2WxR (0xFFFA8028) // (TDES) Key 2 Word x Register -#define AT91C_TDES_KEY3WxR (0xFFFA8030) // (TDES) Key 3 Word x Register -#define AT91C_TDES_IDR (0xFFFA8014) // (TDES) Interrupt Disable Register -#define AT91C_TDES_VR (0xFFFA80FC) // (TDES) TDES Version Register -#define AT91C_TDES_IVxR (0xFFFA8060) // (TDES) Initialization Vector x Register -#define AT91C_TDES_ODATAxR (0xFFFA8050) // (TDES) Output Data x Register -#define AT91C_TDES_IMR (0xFFFA8018) // (TDES) Interrupt Mask Register -#define AT91C_TDES_MR (0xFFFA8004) // (TDES) Mode Register -#define AT91C_TDES_CR (0xFFFA8000) // (TDES) Control Register -#define AT91C_TDES_IER (0xFFFA8010) // (TDES) Interrupt Enable Register -#define AT91C_TDES_ISR (0xFFFA801C) // (TDES) Interrupt Status Register -#define AT91C_TDES_IDATAxR (0xFFFA8040) // (TDES) Input Data x Register -#define AT91C_TDES_KEY1WxR (0xFFFA8020) // (TDES) Key 1 Word x Register +/* ***************************************************************************** */ +/* REGISTER ADDRESS DEFINITION FOR AT91SAM7X128 */ +/* ***************************************************************************** */ +/* ========== Register definition for SYS peripheral ========== */ +/* ========== Register definition for AIC peripheral ========== */ +#define AT91C_AIC_IVR ( 0xFFFFF100 ) /* (AIC) IRQ Vector Register */ +#define AT91C_AIC_SMR ( 0xFFFFF000 ) /* (AIC) Source Mode Register */ +#define AT91C_AIC_FVR ( 0xFFFFF104 ) /* (AIC) FIQ Vector Register */ +#define AT91C_AIC_DCR ( 0xFFFFF138 ) /* (AIC) Debug Control Register (Protect) */ +#define AT91C_AIC_EOICR ( 0xFFFFF130 ) /* (AIC) End of Interrupt Command Register */ +#define AT91C_AIC_SVR ( 0xFFFFF080 ) /* (AIC) Source Vector Register */ +#define AT91C_AIC_FFSR ( 0xFFFFF148 ) /* (AIC) Fast Forcing Status Register */ +#define AT91C_AIC_ICCR ( 0xFFFFF128 ) /* (AIC) Interrupt Clear Command Register */ +#define AT91C_AIC_ISR ( 0xFFFFF108 ) /* (AIC) Interrupt Status Register */ +#define AT91C_AIC_IMR ( 0xFFFFF110 ) /* (AIC) Interrupt Mask Register */ +#define AT91C_AIC_IPR ( 0xFFFFF10C ) /* (AIC) Interrupt Pending Register */ +#define AT91C_AIC_FFER ( 0xFFFFF140 ) /* (AIC) Fast Forcing Enable Register */ +#define AT91C_AIC_IECR ( 0xFFFFF120 ) /* (AIC) Interrupt Enable Command Register */ +#define AT91C_AIC_ISCR ( 0xFFFFF12C ) /* (AIC) Interrupt Set Command Register */ +#define AT91C_AIC_FFDR ( 0xFFFFF144 ) /* (AIC) Fast Forcing Disable Register */ +#define AT91C_AIC_CISR ( 0xFFFFF114 ) /* (AIC) Core Interrupt Status Register */ +#define AT91C_AIC_IDCR ( 0xFFFFF124 ) /* (AIC) Interrupt Disable Command Register */ +#define AT91C_AIC_SPU ( 0xFFFFF134 ) /* (AIC) Spurious Vector Register */ +/* ========== Register definition for PDC_DBGU peripheral ========== */ +#define AT91C_DBGU_TCR ( 0xFFFFF30C ) /* (PDC_DBGU) Transmit Counter Register */ +#define AT91C_DBGU_RNPR ( 0xFFFFF310 ) /* (PDC_DBGU) Receive Next Pointer Register */ +#define AT91C_DBGU_TNPR ( 0xFFFFF318 ) /* (PDC_DBGU) Transmit Next Pointer Register */ +#define AT91C_DBGU_TPR ( 0xFFFFF308 ) /* (PDC_DBGU) Transmit Pointer Register */ +#define AT91C_DBGU_RPR ( 0xFFFFF300 ) /* (PDC_DBGU) Receive Pointer Register */ +#define AT91C_DBGU_RCR ( 0xFFFFF304 ) /* (PDC_DBGU) Receive Counter Register */ +#define AT91C_DBGU_RNCR ( 0xFFFFF314 ) /* (PDC_DBGU) Receive Next Counter Register */ +#define AT91C_DBGU_PTCR ( 0xFFFFF320 ) /* (PDC_DBGU) PDC Transfer Control Register */ +#define AT91C_DBGU_PTSR ( 0xFFFFF324 ) /* (PDC_DBGU) PDC Transfer Status Register */ +#define AT91C_DBGU_TNCR ( 0xFFFFF31C ) /* (PDC_DBGU) Transmit Next Counter Register */ +/* ========== Register definition for DBGU peripheral ========== */ +#define AT91C_DBGU_EXID ( 0xFFFFF244 ) /* (DBGU) Chip ID Extension Register */ +#define AT91C_DBGU_BRGR ( 0xFFFFF220 ) /* (DBGU) Baud Rate Generator Register */ +#define AT91C_DBGU_IDR ( 0xFFFFF20C ) /* (DBGU) Interrupt Disable Register */ +#define AT91C_DBGU_CSR ( 0xFFFFF214 ) /* (DBGU) Channel Status Register */ +#define AT91C_DBGU_CIDR ( 0xFFFFF240 ) /* (DBGU) Chip ID Register */ +#define AT91C_DBGU_MR ( 0xFFFFF204 ) /* (DBGU) Mode Register */ +#define AT91C_DBGU_IMR ( 0xFFFFF210 ) /* (DBGU) Interrupt Mask Register */ +#define AT91C_DBGU_CR ( 0xFFFFF200 ) /* (DBGU) Control Register */ +#define AT91C_DBGU_FNTR ( 0xFFFFF248 ) /* (DBGU) Force NTRST Register */ +#define AT91C_DBGU_THR ( 0xFFFFF21C ) /* (DBGU) Transmitter Holding Register */ +#define AT91C_DBGU_RHR ( 0xFFFFF218 ) /* (DBGU) Receiver Holding Register */ +#define AT91C_DBGU_IER ( 0xFFFFF208 ) /* (DBGU) Interrupt Enable Register */ +/* ========== Register definition for PIOA peripheral ========== */ +#define AT91C_PIOA_ODR ( 0xFFFFF414 ) /* (PIOA) Output Disable Registerr */ +#define AT91C_PIOA_SODR ( 0xFFFFF430 ) /* (PIOA) Set Output Data Register */ +#define AT91C_PIOA_ISR ( 0xFFFFF44C ) /* (PIOA) Interrupt Status Register */ +#define AT91C_PIOA_ABSR ( 0xFFFFF478 ) /* (PIOA) AB Select Status Register */ +#define AT91C_PIOA_IER ( 0xFFFFF440 ) /* (PIOA) Interrupt Enable Register */ +#define AT91C_PIOA_PPUDR ( 0xFFFFF460 ) /* (PIOA) Pull-up Disable Register */ +#define AT91C_PIOA_IMR ( 0xFFFFF448 ) /* (PIOA) Interrupt Mask Register */ +#define AT91C_PIOA_PER ( 0xFFFFF400 ) /* (PIOA) PIO Enable Register */ +#define AT91C_PIOA_IFDR ( 0xFFFFF424 ) /* (PIOA) Input Filter Disable Register */ +#define AT91C_PIOA_OWDR ( 0xFFFFF4A4 ) /* (PIOA) Output Write Disable Register */ +#define AT91C_PIOA_MDSR ( 0xFFFFF458 ) /* (PIOA) Multi-driver Status Register */ +#define AT91C_PIOA_IDR ( 0xFFFFF444 ) /* (PIOA) Interrupt Disable Register */ +#define AT91C_PIOA_ODSR ( 0xFFFFF438 ) /* (PIOA) Output Data Status Register */ +#define AT91C_PIOA_PPUSR ( 0xFFFFF468 ) /* (PIOA) Pull-up Status Register */ +#define AT91C_PIOA_OWSR ( 0xFFFFF4A8 ) /* (PIOA) Output Write Status Register */ +#define AT91C_PIOA_BSR ( 0xFFFFF474 ) /* (PIOA) Select B Register */ +#define AT91C_PIOA_OWER ( 0xFFFFF4A0 ) /* (PIOA) Output Write Enable Register */ +#define AT91C_PIOA_IFER ( 0xFFFFF420 ) /* (PIOA) Input Filter Enable Register */ +#define AT91C_PIOA_PDSR ( 0xFFFFF43C ) /* (PIOA) Pin Data Status Register */ +#define AT91C_PIOA_PPUER ( 0xFFFFF464 ) /* (PIOA) Pull-up Enable Register */ +#define AT91C_PIOA_OSR ( 0xFFFFF418 ) /* (PIOA) Output Status Register */ +#define AT91C_PIOA_ASR ( 0xFFFFF470 ) /* (PIOA) Select A Register */ +#define AT91C_PIOA_MDDR ( 0xFFFFF454 ) /* (PIOA) Multi-driver Disable Register */ +#define AT91C_PIOA_CODR ( 0xFFFFF434 ) /* (PIOA) Clear Output Data Register */ +#define AT91C_PIOA_MDER ( 0xFFFFF450 ) /* (PIOA) Multi-driver Enable Register */ +#define AT91C_PIOA_PDR ( 0xFFFFF404 ) /* (PIOA) PIO Disable Register */ +#define AT91C_PIOA_IFSR ( 0xFFFFF428 ) /* (PIOA) Input Filter Status Register */ +#define AT91C_PIOA_OER ( 0xFFFFF410 ) /* (PIOA) Output Enable Register */ +#define AT91C_PIOA_PSR ( 0xFFFFF408 ) /* (PIOA) PIO Status Register */ +/* ========== Register definition for PIOB peripheral ========== */ +#define AT91C_PIOB_OWDR ( 0xFFFFF6A4 ) /* (PIOB) Output Write Disable Register */ +#define AT91C_PIOB_MDER ( 0xFFFFF650 ) /* (PIOB) Multi-driver Enable Register */ +#define AT91C_PIOB_PPUSR ( 0xFFFFF668 ) /* (PIOB) Pull-up Status Register */ +#define AT91C_PIOB_IMR ( 0xFFFFF648 ) /* (PIOB) Interrupt Mask Register */ +#define AT91C_PIOB_ASR ( 0xFFFFF670 ) /* (PIOB) Select A Register */ +#define AT91C_PIOB_PPUDR ( 0xFFFFF660 ) /* (PIOB) Pull-up Disable Register */ +#define AT91C_PIOB_PSR ( 0xFFFFF608 ) /* (PIOB) PIO Status Register */ +#define AT91C_PIOB_IER ( 0xFFFFF640 ) /* (PIOB) Interrupt Enable Register */ +#define AT91C_PIOB_CODR ( 0xFFFFF634 ) /* (PIOB) Clear Output Data Register */ +#define AT91C_PIOB_OWER ( 0xFFFFF6A0 ) /* (PIOB) Output Write Enable Register */ +#define AT91C_PIOB_ABSR ( 0xFFFFF678 ) /* (PIOB) AB Select Status Register */ +#define AT91C_PIOB_IFDR ( 0xFFFFF624 ) /* (PIOB) Input Filter Disable Register */ +#define AT91C_PIOB_PDSR ( 0xFFFFF63C ) /* (PIOB) Pin Data Status Register */ +#define AT91C_PIOB_IDR ( 0xFFFFF644 ) /* (PIOB) Interrupt Disable Register */ +#define AT91C_PIOB_OWSR ( 0xFFFFF6A8 ) /* (PIOB) Output Write Status Register */ +#define AT91C_PIOB_PDR ( 0xFFFFF604 ) /* (PIOB) PIO Disable Register */ +#define AT91C_PIOB_ODR ( 0xFFFFF614 ) /* (PIOB) Output Disable Registerr */ +#define AT91C_PIOB_IFSR ( 0xFFFFF628 ) /* (PIOB) Input Filter Status Register */ +#define AT91C_PIOB_PPUER ( 0xFFFFF664 ) /* (PIOB) Pull-up Enable Register */ +#define AT91C_PIOB_SODR ( 0xFFFFF630 ) /* (PIOB) Set Output Data Register */ +#define AT91C_PIOB_ISR ( 0xFFFFF64C ) /* (PIOB) Interrupt Status Register */ +#define AT91C_PIOB_ODSR ( 0xFFFFF638 ) /* (PIOB) Output Data Status Register */ +#define AT91C_PIOB_OSR ( 0xFFFFF618 ) /* (PIOB) Output Status Register */ +#define AT91C_PIOB_MDSR ( 0xFFFFF658 ) /* (PIOB) Multi-driver Status Register */ +#define AT91C_PIOB_IFER ( 0xFFFFF620 ) /* (PIOB) Input Filter Enable Register */ +#define AT91C_PIOB_BSR ( 0xFFFFF674 ) /* (PIOB) Select B Register */ +#define AT91C_PIOB_MDDR ( 0xFFFFF654 ) /* (PIOB) Multi-driver Disable Register */ +#define AT91C_PIOB_OER ( 0xFFFFF610 ) /* (PIOB) Output Enable Register */ +#define AT91C_PIOB_PER ( 0xFFFFF600 ) /* (PIOB) PIO Enable Register */ +/* ========== Register definition for CKGR peripheral ========== */ +#define AT91C_CKGR_MOR ( 0xFFFFFC20 ) /* (CKGR) Main Oscillator Register */ +#define AT91C_CKGR_PLLR ( 0xFFFFFC2C ) /* (CKGR) PLL Register */ +#define AT91C_CKGR_MCFR ( 0xFFFFFC24 ) /* (CKGR) Main Clock Frequency Register */ +/* ========== Register definition for PMC peripheral ========== */ +#define AT91C_PMC_IDR ( 0xFFFFFC64 ) /* (PMC) Interrupt Disable Register */ +#define AT91C_PMC_MOR ( 0xFFFFFC20 ) /* (PMC) Main Oscillator Register */ +#define AT91C_PMC_PLLR ( 0xFFFFFC2C ) /* (PMC) PLL Register */ +#define AT91C_PMC_PCER ( 0xFFFFFC10 ) /* (PMC) Peripheral Clock Enable Register */ +#define AT91C_PMC_PCKR ( 0xFFFFFC40 ) /* (PMC) Programmable Clock Register */ +#define AT91C_PMC_MCKR ( 0xFFFFFC30 ) /* (PMC) Master Clock Register */ +#define AT91C_PMC_SCDR ( 0xFFFFFC04 ) /* (PMC) System Clock Disable Register */ +#define AT91C_PMC_PCDR ( 0xFFFFFC14 ) /* (PMC) Peripheral Clock Disable Register */ +#define AT91C_PMC_SCSR ( 0xFFFFFC08 ) /* (PMC) System Clock Status Register */ +#define AT91C_PMC_PCSR ( 0xFFFFFC18 ) /* (PMC) Peripheral Clock Status Register */ +#define AT91C_PMC_MCFR ( 0xFFFFFC24 ) /* (PMC) Main Clock Frequency Register */ +#define AT91C_PMC_SCER ( 0xFFFFFC00 ) /* (PMC) System Clock Enable Register */ +#define AT91C_PMC_IMR ( 0xFFFFFC6C ) /* (PMC) Interrupt Mask Register */ +#define AT91C_PMC_IER ( 0xFFFFFC60 ) /* (PMC) Interrupt Enable Register */ +#define AT91C_PMC_SR ( 0xFFFFFC68 ) /* (PMC) Status Register */ +/* ========== Register definition for RSTC peripheral ========== */ +#define AT91C_RSTC_RCR ( 0xFFFFFD00 ) /* (RSTC) Reset Control Register */ +#define AT91C_RSTC_RMR ( 0xFFFFFD08 ) /* (RSTC) Reset Mode Register */ +#define AT91C_RSTC_RSR ( 0xFFFFFD04 ) /* (RSTC) Reset Status Register */ +/* ========== Register definition for RTTC peripheral ========== */ +#define AT91C_RTTC_RTSR ( 0xFFFFFD2C ) /* (RTTC) Real-time Status Register */ +#define AT91C_RTTC_RTMR ( 0xFFFFFD20 ) /* (RTTC) Real-time Mode Register */ +#define AT91C_RTTC_RTVR ( 0xFFFFFD28 ) /* (RTTC) Real-time Value Register */ +#define AT91C_RTTC_RTAR ( 0xFFFFFD24 ) /* (RTTC) Real-time Alarm Register */ +/* ========== Register definition for PITC peripheral ========== */ +#define AT91C_PITC_PIVR ( 0xFFFFFD38 ) /* (PITC) Period Interval Value Register */ +#define AT91C_PITC_PISR ( 0xFFFFFD34 ) /* (PITC) Period Interval Status Register */ +#define AT91C_PITC_PIIR ( 0xFFFFFD3C ) /* (PITC) Period Interval Image Register */ +#define AT91C_PITC_PIMR ( 0xFFFFFD30 ) /* (PITC) Period Interval Mode Register */ +/* ========== Register definition for WDTC peripheral ========== */ +#define AT91C_WDTC_WDCR ( 0xFFFFFD40 ) /* (WDTC) Watchdog Control Register */ +#define AT91C_WDTC_WDSR ( 0xFFFFFD48 ) /* (WDTC) Watchdog Status Register */ +#define AT91C_WDTC_WDMR ( 0xFFFFFD44 ) /* (WDTC) Watchdog Mode Register */ +/* ========== Register definition for VREG peripheral ========== */ +#define AT91C_VREG_MR ( 0xFFFFFD60 ) /* (VREG) Voltage Regulator Mode Register */ +/* ========== Register definition for MC peripheral ========== */ +#define AT91C_MC_ASR ( 0xFFFFFF04 ) /* (MC) MC Abort Status Register */ +#define AT91C_MC_RCR ( 0xFFFFFF00 ) /* (MC) MC Remap Control Register */ +#define AT91C_MC_FCR ( 0xFFFFFF64 ) /* (MC) MC Flash Command Register */ +#define AT91C_MC_AASR ( 0xFFFFFF08 ) /* (MC) MC Abort Address Status Register */ +#define AT91C_MC_FSR ( 0xFFFFFF68 ) /* (MC) MC Flash Status Register */ +#define AT91C_MC_FMR ( 0xFFFFFF60 ) /* (MC) MC Flash Mode Register */ +/* ========== Register definition for PDC_SPI1 peripheral ========== */ +#define AT91C_SPI1_PTCR ( 0xFFFE4120 ) /* (PDC_SPI1) PDC Transfer Control Register */ +#define AT91C_SPI1_RPR ( 0xFFFE4100 ) /* (PDC_SPI1) Receive Pointer Register */ +#define AT91C_SPI1_TNCR ( 0xFFFE411C ) /* (PDC_SPI1) Transmit Next Counter Register */ +#define AT91C_SPI1_TPR ( 0xFFFE4108 ) /* (PDC_SPI1) Transmit Pointer Register */ +#define AT91C_SPI1_TNPR ( 0xFFFE4118 ) /* (PDC_SPI1) Transmit Next Pointer Register */ +#define AT91C_SPI1_TCR ( 0xFFFE410C ) /* (PDC_SPI1) Transmit Counter Register */ +#define AT91C_SPI1_RCR ( 0xFFFE4104 ) /* (PDC_SPI1) Receive Counter Register */ +#define AT91C_SPI1_RNPR ( 0xFFFE4110 ) /* (PDC_SPI1) Receive Next Pointer Register */ +#define AT91C_SPI1_RNCR ( 0xFFFE4114 ) /* (PDC_SPI1) Receive Next Counter Register */ +#define AT91C_SPI1_PTSR ( 0xFFFE4124 ) /* (PDC_SPI1) PDC Transfer Status Register */ +/* ========== Register definition for SPI1 peripheral ========== */ +#define AT91C_SPI1_IMR ( 0xFFFE401C ) /* (SPI1) Interrupt Mask Register */ +#define AT91C_SPI1_IER ( 0xFFFE4014 ) /* (SPI1) Interrupt Enable Register */ +#define AT91C_SPI1_MR ( 0xFFFE4004 ) /* (SPI1) Mode Register */ +#define AT91C_SPI1_RDR ( 0xFFFE4008 ) /* (SPI1) Receive Data Register */ +#define AT91C_SPI1_IDR ( 0xFFFE4018 ) /* (SPI1) Interrupt Disable Register */ +#define AT91C_SPI1_SR ( 0xFFFE4010 ) /* (SPI1) Status Register */ +#define AT91C_SPI1_TDR ( 0xFFFE400C ) /* (SPI1) Transmit Data Register */ +#define AT91C_SPI1_CR ( 0xFFFE4000 ) /* (SPI1) Control Register */ +#define AT91C_SPI1_CSR ( 0xFFFE4030 ) /* (SPI1) Chip Select Register */ +/* ========== Register definition for PDC_SPI0 peripheral ========== */ +#define AT91C_SPI0_PTCR ( 0xFFFE0120 ) /* (PDC_SPI0) PDC Transfer Control Register */ +#define AT91C_SPI0_TPR ( 0xFFFE0108 ) /* (PDC_SPI0) Transmit Pointer Register */ +#define AT91C_SPI0_TCR ( 0xFFFE010C ) /* (PDC_SPI0) Transmit Counter Register */ +#define AT91C_SPI0_RCR ( 0xFFFE0104 ) /* (PDC_SPI0) Receive Counter Register */ +#define AT91C_SPI0_PTSR ( 0xFFFE0124 ) /* (PDC_SPI0) PDC Transfer Status Register */ +#define AT91C_SPI0_RNPR ( 0xFFFE0110 ) /* (PDC_SPI0) Receive Next Pointer Register */ +#define AT91C_SPI0_RPR ( 0xFFFE0100 ) /* (PDC_SPI0) Receive Pointer Register */ +#define AT91C_SPI0_TNCR ( 0xFFFE011C ) /* (PDC_SPI0) Transmit Next Counter Register */ +#define AT91C_SPI0_RNCR ( 0xFFFE0114 ) /* (PDC_SPI0) Receive Next Counter Register */ +#define AT91C_SPI0_TNPR ( 0xFFFE0118 ) /* (PDC_SPI0) Transmit Next Pointer Register */ +/* ========== Register definition for SPI0 peripheral ========== */ +#define AT91C_SPI0_IER ( 0xFFFE0014 ) /* (SPI0) Interrupt Enable Register */ +#define AT91C_SPI0_SR ( 0xFFFE0010 ) /* (SPI0) Status Register */ +#define AT91C_SPI0_IDR ( 0xFFFE0018 ) /* (SPI0) Interrupt Disable Register */ +#define AT91C_SPI0_CR ( 0xFFFE0000 ) /* (SPI0) Control Register */ +#define AT91C_SPI0_MR ( 0xFFFE0004 ) /* (SPI0) Mode Register */ +#define AT91C_SPI0_IMR ( 0xFFFE001C ) /* (SPI0) Interrupt Mask Register */ +#define AT91C_SPI0_TDR ( 0xFFFE000C ) /* (SPI0) Transmit Data Register */ +#define AT91C_SPI0_RDR ( 0xFFFE0008 ) /* (SPI0) Receive Data Register */ +#define AT91C_SPI0_CSR ( 0xFFFE0030 ) /* (SPI0) Chip Select Register */ +/* ========== Register definition for PDC_US1 peripheral ========== */ +#define AT91C_US1_RNCR ( 0xFFFC4114 ) /* (PDC_US1) Receive Next Counter Register */ +#define AT91C_US1_PTCR ( 0xFFFC4120 ) /* (PDC_US1) PDC Transfer Control Register */ +#define AT91C_US1_TCR ( 0xFFFC410C ) /* (PDC_US1) Transmit Counter Register */ +#define AT91C_US1_PTSR ( 0xFFFC4124 ) /* (PDC_US1) PDC Transfer Status Register */ +#define AT91C_US1_TNPR ( 0xFFFC4118 ) /* (PDC_US1) Transmit Next Pointer Register */ +#define AT91C_US1_RCR ( 0xFFFC4104 ) /* (PDC_US1) Receive Counter Register */ +#define AT91C_US1_RNPR ( 0xFFFC4110 ) /* (PDC_US1) Receive Next Pointer Register */ +#define AT91C_US1_RPR ( 0xFFFC4100 ) /* (PDC_US1) Receive Pointer Register */ +#define AT91C_US1_TNCR ( 0xFFFC411C ) /* (PDC_US1) Transmit Next Counter Register */ +#define AT91C_US1_TPR ( 0xFFFC4108 ) /* (PDC_US1) Transmit Pointer Register */ +/* ========== Register definition for US1 peripheral ========== */ +#define AT91C_US1_IF ( 0xFFFC404C ) /* (US1) IRDA_FILTER Register */ +#define AT91C_US1_NER ( 0xFFFC4044 ) /* (US1) Nb Errors Register */ +#define AT91C_US1_RTOR ( 0xFFFC4024 ) /* (US1) Receiver Time-out Register */ +#define AT91C_US1_CSR ( 0xFFFC4014 ) /* (US1) Channel Status Register */ +#define AT91C_US1_IDR ( 0xFFFC400C ) /* (US1) Interrupt Disable Register */ +#define AT91C_US1_IER ( 0xFFFC4008 ) /* (US1) Interrupt Enable Register */ +#define AT91C_US1_THR ( 0xFFFC401C ) /* (US1) Transmitter Holding Register */ +#define AT91C_US1_TTGR ( 0xFFFC4028 ) /* (US1) Transmitter Time-guard Register */ +#define AT91C_US1_RHR ( 0xFFFC4018 ) /* (US1) Receiver Holding Register */ +#define AT91C_US1_BRGR ( 0xFFFC4020 ) /* (US1) Baud Rate Generator Register */ +#define AT91C_US1_IMR ( 0xFFFC4010 ) /* (US1) Interrupt Mask Register */ +#define AT91C_US1_FIDI ( 0xFFFC4040 ) /* (US1) FI_DI_Ratio Register */ +#define AT91C_US1_CR ( 0xFFFC4000 ) /* (US1) Control Register */ +#define AT91C_US1_MR ( 0xFFFC4004 ) /* (US1) Mode Register */ +/* ========== Register definition for PDC_US0 peripheral ========== */ +#define AT91C_US0_TNPR ( 0xFFFC0118 ) /* (PDC_US0) Transmit Next Pointer Register */ +#define AT91C_US0_RNPR ( 0xFFFC0110 ) /* (PDC_US0) Receive Next Pointer Register */ +#define AT91C_US0_TCR ( 0xFFFC010C ) /* (PDC_US0) Transmit Counter Register */ +#define AT91C_US0_PTCR ( 0xFFFC0120 ) /* (PDC_US0) PDC Transfer Control Register */ +#define AT91C_US0_PTSR ( 0xFFFC0124 ) /* (PDC_US0) PDC Transfer Status Register */ +#define AT91C_US0_TNCR ( 0xFFFC011C ) /* (PDC_US0) Transmit Next Counter Register */ +#define AT91C_US0_TPR ( 0xFFFC0108 ) /* (PDC_US0) Transmit Pointer Register */ +#define AT91C_US0_RCR ( 0xFFFC0104 ) /* (PDC_US0) Receive Counter Register */ +#define AT91C_US0_RPR ( 0xFFFC0100 ) /* (PDC_US0) Receive Pointer Register */ +#define AT91C_US0_RNCR ( 0xFFFC0114 ) /* (PDC_US0) Receive Next Counter Register */ +/* ========== Register definition for US0 peripheral ========== */ +#define AT91C_US0_BRGR ( 0xFFFC0020 ) /* (US0) Baud Rate Generator Register */ +#define AT91C_US0_NER ( 0xFFFC0044 ) /* (US0) Nb Errors Register */ +#define AT91C_US0_CR ( 0xFFFC0000 ) /* (US0) Control Register */ +#define AT91C_US0_IMR ( 0xFFFC0010 ) /* (US0) Interrupt Mask Register */ +#define AT91C_US0_FIDI ( 0xFFFC0040 ) /* (US0) FI_DI_Ratio Register */ +#define AT91C_US0_TTGR ( 0xFFFC0028 ) /* (US0) Transmitter Time-guard Register */ +#define AT91C_US0_MR ( 0xFFFC0004 ) /* (US0) Mode Register */ +#define AT91C_US0_RTOR ( 0xFFFC0024 ) /* (US0) Receiver Time-out Register */ +#define AT91C_US0_CSR ( 0xFFFC0014 ) /* (US0) Channel Status Register */ +#define AT91C_US0_RHR ( 0xFFFC0018 ) /* (US0) Receiver Holding Register */ +#define AT91C_US0_IDR ( 0xFFFC000C ) /* (US0) Interrupt Disable Register */ +#define AT91C_US0_THR ( 0xFFFC001C ) /* (US0) Transmitter Holding Register */ +#define AT91C_US0_IF ( 0xFFFC004C ) /* (US0) IRDA_FILTER Register */ +#define AT91C_US0_IER ( 0xFFFC0008 ) /* (US0) Interrupt Enable Register */ +/* ========== Register definition for PDC_SSC peripheral ========== */ +#define AT91C_SSC_TNCR ( 0xFFFD411C ) /* (PDC_SSC) Transmit Next Counter Register */ +#define AT91C_SSC_RPR ( 0xFFFD4100 ) /* (PDC_SSC) Receive Pointer Register */ +#define AT91C_SSC_RNCR ( 0xFFFD4114 ) /* (PDC_SSC) Receive Next Counter Register */ +#define AT91C_SSC_TPR ( 0xFFFD4108 ) /* (PDC_SSC) Transmit Pointer Register */ +#define AT91C_SSC_PTCR ( 0xFFFD4120 ) /* (PDC_SSC) PDC Transfer Control Register */ +#define AT91C_SSC_TCR ( 0xFFFD410C ) /* (PDC_SSC) Transmit Counter Register */ +#define AT91C_SSC_RCR ( 0xFFFD4104 ) /* (PDC_SSC) Receive Counter Register */ +#define AT91C_SSC_RNPR ( 0xFFFD4110 ) /* (PDC_SSC) Receive Next Pointer Register */ +#define AT91C_SSC_TNPR ( 0xFFFD4118 ) /* (PDC_SSC) Transmit Next Pointer Register */ +#define AT91C_SSC_PTSR ( 0xFFFD4124 ) /* (PDC_SSC) PDC Transfer Status Register */ +/* ========== Register definition for SSC peripheral ========== */ +#define AT91C_SSC_RHR ( 0xFFFD4020 ) /* (SSC) Receive Holding Register */ +#define AT91C_SSC_RSHR ( 0xFFFD4030 ) /* (SSC) Receive Sync Holding Register */ +#define AT91C_SSC_TFMR ( 0xFFFD401C ) /* (SSC) Transmit Frame Mode Register */ +#define AT91C_SSC_IDR ( 0xFFFD4048 ) /* (SSC) Interrupt Disable Register */ +#define AT91C_SSC_THR ( 0xFFFD4024 ) /* (SSC) Transmit Holding Register */ +#define AT91C_SSC_RCMR ( 0xFFFD4010 ) /* (SSC) Receive Clock ModeRegister */ +#define AT91C_SSC_IER ( 0xFFFD4044 ) /* (SSC) Interrupt Enable Register */ +#define AT91C_SSC_TSHR ( 0xFFFD4034 ) /* (SSC) Transmit Sync Holding Register */ +#define AT91C_SSC_SR ( 0xFFFD4040 ) /* (SSC) Status Register */ +#define AT91C_SSC_CMR ( 0xFFFD4004 ) /* (SSC) Clock Mode Register */ +#define AT91C_SSC_TCMR ( 0xFFFD4018 ) /* (SSC) Transmit Clock Mode Register */ +#define AT91C_SSC_CR ( 0xFFFD4000 ) /* (SSC) Control Register */ +#define AT91C_SSC_IMR ( 0xFFFD404C ) /* (SSC) Interrupt Mask Register */ +#define AT91C_SSC_RFMR ( 0xFFFD4014 ) /* (SSC) Receive Frame Mode Register */ +/* ========== Register definition for TWI peripheral ========== */ +#define AT91C_TWI_IER ( 0xFFFB8024 ) /* (TWI) Interrupt Enable Register */ +#define AT91C_TWI_CR ( 0xFFFB8000 ) /* (TWI) Control Register */ +#define AT91C_TWI_SR ( 0xFFFB8020 ) /* (TWI) Status Register */ +#define AT91C_TWI_IMR ( 0xFFFB802C ) /* (TWI) Interrupt Mask Register */ +#define AT91C_TWI_THR ( 0xFFFB8034 ) /* (TWI) Transmit Holding Register */ +#define AT91C_TWI_IDR ( 0xFFFB8028 ) /* (TWI) Interrupt Disable Register */ +#define AT91C_TWI_IADR ( 0xFFFB800C ) /* (TWI) Internal Address Register */ +#define AT91C_TWI_MMR ( 0xFFFB8004 ) /* (TWI) Master Mode Register */ +#define AT91C_TWI_CWGR ( 0xFFFB8010 ) /* (TWI) Clock Waveform Generator Register */ +#define AT91C_TWI_RHR ( 0xFFFB8030 ) /* (TWI) Receive Holding Register */ +/* ========== Register definition for PWMC_CH3 peripheral ========== */ +#define AT91C_PWMC_CH3_CUPDR ( 0xFFFCC270 ) /* (PWMC_CH3) Channel Update Register */ +#define AT91C_PWMC_CH3_Reserved ( 0xFFFCC274 ) /* (PWMC_CH3) Reserved */ +#define AT91C_PWMC_CH3_CPRDR ( 0xFFFCC268 ) /* (PWMC_CH3) Channel Period Register */ +#define AT91C_PWMC_CH3_CDTYR ( 0xFFFCC264 ) /* (PWMC_CH3) Channel Duty Cycle Register */ +#define AT91C_PWMC_CH3_CCNTR ( 0xFFFCC26C ) /* (PWMC_CH3) Channel Counter Register */ +#define AT91C_PWMC_CH3_CMR ( 0xFFFCC260 ) /* (PWMC_CH3) Channel Mode Register */ +/* ========== Register definition for PWMC_CH2 peripheral ========== */ +#define AT91C_PWMC_CH2_Reserved ( 0xFFFCC254 ) /* (PWMC_CH2) Reserved */ +#define AT91C_PWMC_CH2_CMR ( 0xFFFCC240 ) /* (PWMC_CH2) Channel Mode Register */ +#define AT91C_PWMC_CH2_CCNTR ( 0xFFFCC24C ) /* (PWMC_CH2) Channel Counter Register */ +#define AT91C_PWMC_CH2_CPRDR ( 0xFFFCC248 ) /* (PWMC_CH2) Channel Period Register */ +#define AT91C_PWMC_CH2_CUPDR ( 0xFFFCC250 ) /* (PWMC_CH2) Channel Update Register */ +#define AT91C_PWMC_CH2_CDTYR ( 0xFFFCC244 ) /* (PWMC_CH2) Channel Duty Cycle Register */ +/* ========== Register definition for PWMC_CH1 peripheral ========== */ +#define AT91C_PWMC_CH1_Reserved ( 0xFFFCC234 ) /* (PWMC_CH1) Reserved */ +#define AT91C_PWMC_CH1_CUPDR ( 0xFFFCC230 ) /* (PWMC_CH1) Channel Update Register */ +#define AT91C_PWMC_CH1_CPRDR ( 0xFFFCC228 ) /* (PWMC_CH1) Channel Period Register */ +#define AT91C_PWMC_CH1_CCNTR ( 0xFFFCC22C ) /* (PWMC_CH1) Channel Counter Register */ +#define AT91C_PWMC_CH1_CDTYR ( 0xFFFCC224 ) /* (PWMC_CH1) Channel Duty Cycle Register */ +#define AT91C_PWMC_CH1_CMR ( 0xFFFCC220 ) /* (PWMC_CH1) Channel Mode Register */ +/* ========== Register definition for PWMC_CH0 peripheral ========== */ +#define AT91C_PWMC_CH0_Reserved ( 0xFFFCC214 ) /* (PWMC_CH0) Reserved */ +#define AT91C_PWMC_CH0_CPRDR ( 0xFFFCC208 ) /* (PWMC_CH0) Channel Period Register */ +#define AT91C_PWMC_CH0_CDTYR ( 0xFFFCC204 ) /* (PWMC_CH0) Channel Duty Cycle Register */ +#define AT91C_PWMC_CH0_CMR ( 0xFFFCC200 ) /* (PWMC_CH0) Channel Mode Register */ +#define AT91C_PWMC_CH0_CUPDR ( 0xFFFCC210 ) /* (PWMC_CH0) Channel Update Register */ +#define AT91C_PWMC_CH0_CCNTR ( 0xFFFCC20C ) /* (PWMC_CH0) Channel Counter Register */ +/* ========== Register definition for PWMC peripheral ========== */ +#define AT91C_PWMC_IDR ( 0xFFFCC014 ) /* (PWMC) PWMC Interrupt Disable Register */ +#define AT91C_PWMC_DIS ( 0xFFFCC008 ) /* (PWMC) PWMC Disable Register */ +#define AT91C_PWMC_IER ( 0xFFFCC010 ) /* (PWMC) PWMC Interrupt Enable Register */ +#define AT91C_PWMC_VR ( 0xFFFCC0FC ) /* (PWMC) PWMC Version Register */ +#define AT91C_PWMC_ISR ( 0xFFFCC01C ) /* (PWMC) PWMC Interrupt Status Register */ +#define AT91C_PWMC_SR ( 0xFFFCC00C ) /* (PWMC) PWMC Status Register */ +#define AT91C_PWMC_IMR ( 0xFFFCC018 ) /* (PWMC) PWMC Interrupt Mask Register */ +#define AT91C_PWMC_MR ( 0xFFFCC000 ) /* (PWMC) PWMC Mode Register */ +#define AT91C_PWMC_ENA ( 0xFFFCC004 ) /* (PWMC) PWMC Enable Register */ +/* ========== Register definition for UDP peripheral ========== */ +#define AT91C_UDP_IMR ( 0xFFFB0018 ) /* (UDP) Interrupt Mask Register */ +#define AT91C_UDP_FADDR ( 0xFFFB0008 ) /* (UDP) Function Address Register */ +#define AT91C_UDP_NUM ( 0xFFFB0000 ) /* (UDP) Frame Number Register */ +#define AT91C_UDP_FDR ( 0xFFFB0050 ) /* (UDP) Endpoint FIFO Data Register */ +#define AT91C_UDP_ISR ( 0xFFFB001C ) /* (UDP) Interrupt Status Register */ +#define AT91C_UDP_CSR ( 0xFFFB0030 ) /* (UDP) Endpoint Control and Status Register */ +#define AT91C_UDP_IDR ( 0xFFFB0014 ) /* (UDP) Interrupt Disable Register */ +#define AT91C_UDP_ICR ( 0xFFFB0020 ) /* (UDP) Interrupt Clear Register */ +#define AT91C_UDP_RSTEP ( 0xFFFB0028 ) /* (UDP) Reset Endpoint Register */ +#define AT91C_UDP_TXVC ( 0xFFFB0074 ) /* (UDP) Transceiver Control Register */ +#define AT91C_UDP_GLBSTATE ( 0xFFFB0004 ) /* (UDP) Global State Register */ +#define AT91C_UDP_IER ( 0xFFFB0010 ) /* (UDP) Interrupt Enable Register */ +/* ========== Register definition for TC0 peripheral ========== */ +#define AT91C_TC0_SR ( 0xFFFA0020 ) /* (TC0) Status Register */ +#define AT91C_TC0_RC ( 0xFFFA001C ) /* (TC0) Register C */ +#define AT91C_TC0_RB ( 0xFFFA0018 ) /* (TC0) Register B */ +#define AT91C_TC0_CCR ( 0xFFFA0000 ) /* (TC0) Channel Control Register */ +#define AT91C_TC0_CMR ( 0xFFFA0004 ) /* (TC0) Channel Mode Register (Capture Mode / Waveform Mode) */ +#define AT91C_TC0_IER ( 0xFFFA0024 ) /* (TC0) Interrupt Enable Register */ +#define AT91C_TC0_RA ( 0xFFFA0014 ) /* (TC0) Register A */ +#define AT91C_TC0_IDR ( 0xFFFA0028 ) /* (TC0) Interrupt Disable Register */ +#define AT91C_TC0_CV ( 0xFFFA0010 ) /* (TC0) Counter Value */ +#define AT91C_TC0_IMR ( 0xFFFA002C ) /* (TC0) Interrupt Mask Register */ +/* ========== Register definition for TC1 peripheral ========== */ +#define AT91C_TC1_RB ( 0xFFFA0058 ) /* (TC1) Register B */ +#define AT91C_TC1_CCR ( 0xFFFA0040 ) /* (TC1) Channel Control Register */ +#define AT91C_TC1_IER ( 0xFFFA0064 ) /* (TC1) Interrupt Enable Register */ +#define AT91C_TC1_IDR ( 0xFFFA0068 ) /* (TC1) Interrupt Disable Register */ +#define AT91C_TC1_SR ( 0xFFFA0060 ) /* (TC1) Status Register */ +#define AT91C_TC1_CMR ( 0xFFFA0044 ) /* (TC1) Channel Mode Register (Capture Mode / Waveform Mode) */ +#define AT91C_TC1_RA ( 0xFFFA0054 ) /* (TC1) Register A */ +#define AT91C_TC1_RC ( 0xFFFA005C ) /* (TC1) Register C */ +#define AT91C_TC1_IMR ( 0xFFFA006C ) /* (TC1) Interrupt Mask Register */ +#define AT91C_TC1_CV ( 0xFFFA0050 ) /* (TC1) Counter Value */ +/* ========== Register definition for TC2 peripheral ========== */ +#define AT91C_TC2_CMR ( 0xFFFA0084 ) /* (TC2) Channel Mode Register (Capture Mode / Waveform Mode) */ +#define AT91C_TC2_CCR ( 0xFFFA0080 ) /* (TC2) Channel Control Register */ +#define AT91C_TC2_CV ( 0xFFFA0090 ) /* (TC2) Counter Value */ +#define AT91C_TC2_RA ( 0xFFFA0094 ) /* (TC2) Register A */ +#define AT91C_TC2_RB ( 0xFFFA0098 ) /* (TC2) Register B */ +#define AT91C_TC2_IDR ( 0xFFFA00A8 ) /* (TC2) Interrupt Disable Register */ +#define AT91C_TC2_IMR ( 0xFFFA00AC ) /* (TC2) Interrupt Mask Register */ +#define AT91C_TC2_RC ( 0xFFFA009C ) /* (TC2) Register C */ +#define AT91C_TC2_IER ( 0xFFFA00A4 ) /* (TC2) Interrupt Enable Register */ +#define AT91C_TC2_SR ( 0xFFFA00A0 ) /* (TC2) Status Register */ +/* ========== Register definition for TCB peripheral ========== */ +#define AT91C_TCB_BMR ( 0xFFFA00C4 ) /* (TCB) TC Block Mode Register */ +#define AT91C_TCB_BCR ( 0xFFFA00C0 ) /* (TCB) TC Block Control Register */ +/* ========== Register definition for CAN_MB0 peripheral ========== */ +#define AT91C_CAN_MB0_MDL ( 0xFFFD0214 ) /* (CAN_MB0) MailBox Data Low Register */ +#define AT91C_CAN_MB0_MAM ( 0xFFFD0204 ) /* (CAN_MB0) MailBox Acceptance Mask Register */ +#define AT91C_CAN_MB0_MCR ( 0xFFFD021C ) /* (CAN_MB0) MailBox Control Register */ +#define AT91C_CAN_MB0_MID ( 0xFFFD0208 ) /* (CAN_MB0) MailBox ID Register */ +#define AT91C_CAN_MB0_MSR ( 0xFFFD0210 ) /* (CAN_MB0) MailBox Status Register */ +#define AT91C_CAN_MB0_MFID ( 0xFFFD020C ) /* (CAN_MB0) MailBox Family ID Register */ +#define AT91C_CAN_MB0_MDH ( 0xFFFD0218 ) /* (CAN_MB0) MailBox Data High Register */ +#define AT91C_CAN_MB0_MMR ( 0xFFFD0200 ) /* (CAN_MB0) MailBox Mode Register */ +/* ========== Register definition for CAN_MB1 peripheral ========== */ +#define AT91C_CAN_MB1_MDL ( 0xFFFD0234 ) /* (CAN_MB1) MailBox Data Low Register */ +#define AT91C_CAN_MB1_MID ( 0xFFFD0228 ) /* (CAN_MB1) MailBox ID Register */ +#define AT91C_CAN_MB1_MMR ( 0xFFFD0220 ) /* (CAN_MB1) MailBox Mode Register */ +#define AT91C_CAN_MB1_MSR ( 0xFFFD0230 ) /* (CAN_MB1) MailBox Status Register */ +#define AT91C_CAN_MB1_MAM ( 0xFFFD0224 ) /* (CAN_MB1) MailBox Acceptance Mask Register */ +#define AT91C_CAN_MB1_MDH ( 0xFFFD0238 ) /* (CAN_MB1) MailBox Data High Register */ +#define AT91C_CAN_MB1_MCR ( 0xFFFD023C ) /* (CAN_MB1) MailBox Control Register */ +#define AT91C_CAN_MB1_MFID ( 0xFFFD022C ) /* (CAN_MB1) MailBox Family ID Register */ +/* ========== Register definition for CAN_MB2 peripheral ========== */ +#define AT91C_CAN_MB2_MCR ( 0xFFFD025C ) /* (CAN_MB2) MailBox Control Register */ +#define AT91C_CAN_MB2_MDH ( 0xFFFD0258 ) /* (CAN_MB2) MailBox Data High Register */ +#define AT91C_CAN_MB2_MID ( 0xFFFD0248 ) /* (CAN_MB2) MailBox ID Register */ +#define AT91C_CAN_MB2_MDL ( 0xFFFD0254 ) /* (CAN_MB2) MailBox Data Low Register */ +#define AT91C_CAN_MB2_MMR ( 0xFFFD0240 ) /* (CAN_MB2) MailBox Mode Register */ +#define AT91C_CAN_MB2_MAM ( 0xFFFD0244 ) /* (CAN_MB2) MailBox Acceptance Mask Register */ +#define AT91C_CAN_MB2_MFID ( 0xFFFD024C ) /* (CAN_MB2) MailBox Family ID Register */ +#define AT91C_CAN_MB2_MSR ( 0xFFFD0250 ) /* (CAN_MB2) MailBox Status Register */ +/* ========== Register definition for CAN_MB3 peripheral ========== */ +#define AT91C_CAN_MB3_MFID ( 0xFFFD026C ) /* (CAN_MB3) MailBox Family ID Register */ +#define AT91C_CAN_MB3_MAM ( 0xFFFD0264 ) /* (CAN_MB3) MailBox Acceptance Mask Register */ +#define AT91C_CAN_MB3_MID ( 0xFFFD0268 ) /* (CAN_MB3) MailBox ID Register */ +#define AT91C_CAN_MB3_MCR ( 0xFFFD027C ) /* (CAN_MB3) MailBox Control Register */ +#define AT91C_CAN_MB3_MMR ( 0xFFFD0260 ) /* (CAN_MB3) MailBox Mode Register */ +#define AT91C_CAN_MB3_MSR ( 0xFFFD0270 ) /* (CAN_MB3) MailBox Status Register */ +#define AT91C_CAN_MB3_MDL ( 0xFFFD0274 ) /* (CAN_MB3) MailBox Data Low Register */ +#define AT91C_CAN_MB3_MDH ( 0xFFFD0278 ) /* (CAN_MB3) MailBox Data High Register */ +/* ========== Register definition for CAN_MB4 peripheral ========== */ +#define AT91C_CAN_MB4_MID ( 0xFFFD0288 ) /* (CAN_MB4) MailBox ID Register */ +#define AT91C_CAN_MB4_MMR ( 0xFFFD0280 ) /* (CAN_MB4) MailBox Mode Register */ +#define AT91C_CAN_MB4_MDH ( 0xFFFD0298 ) /* (CAN_MB4) MailBox Data High Register */ +#define AT91C_CAN_MB4_MFID ( 0xFFFD028C ) /* (CAN_MB4) MailBox Family ID Register */ +#define AT91C_CAN_MB4_MSR ( 0xFFFD0290 ) /* (CAN_MB4) MailBox Status Register */ +#define AT91C_CAN_MB4_MCR ( 0xFFFD029C ) /* (CAN_MB4) MailBox Control Register */ +#define AT91C_CAN_MB4_MDL ( 0xFFFD0294 ) /* (CAN_MB4) MailBox Data Low Register */ +#define AT91C_CAN_MB4_MAM ( 0xFFFD0284 ) /* (CAN_MB4) MailBox Acceptance Mask Register */ +/* ========== Register definition for CAN_MB5 peripheral ========== */ +#define AT91C_CAN_MB5_MSR ( 0xFFFD02B0 ) /* (CAN_MB5) MailBox Status Register */ +#define AT91C_CAN_MB5_MCR ( 0xFFFD02BC ) /* (CAN_MB5) MailBox Control Register */ +#define AT91C_CAN_MB5_MFID ( 0xFFFD02AC ) /* (CAN_MB5) MailBox Family ID Register */ +#define AT91C_CAN_MB5_MDH ( 0xFFFD02B8 ) /* (CAN_MB5) MailBox Data High Register */ +#define AT91C_CAN_MB5_MID ( 0xFFFD02A8 ) /* (CAN_MB5) MailBox ID Register */ +#define AT91C_CAN_MB5_MMR ( 0xFFFD02A0 ) /* (CAN_MB5) MailBox Mode Register */ +#define AT91C_CAN_MB5_MDL ( 0xFFFD02B4 ) /* (CAN_MB5) MailBox Data Low Register */ +#define AT91C_CAN_MB5_MAM ( 0xFFFD02A4 ) /* (CAN_MB5) MailBox Acceptance Mask Register */ +/* ========== Register definition for CAN_MB6 peripheral ========== */ +#define AT91C_CAN_MB6_MFID ( 0xFFFD02CC ) /* (CAN_MB6) MailBox Family ID Register */ +#define AT91C_CAN_MB6_MID ( 0xFFFD02C8 ) /* (CAN_MB6) MailBox ID Register */ +#define AT91C_CAN_MB6_MAM ( 0xFFFD02C4 ) /* (CAN_MB6) MailBox Acceptance Mask Register */ +#define AT91C_CAN_MB6_MSR ( 0xFFFD02D0 ) /* (CAN_MB6) MailBox Status Register */ +#define AT91C_CAN_MB6_MDL ( 0xFFFD02D4 ) /* (CAN_MB6) MailBox Data Low Register */ +#define AT91C_CAN_MB6_MCR ( 0xFFFD02DC ) /* (CAN_MB6) MailBox Control Register */ +#define AT91C_CAN_MB6_MDH ( 0xFFFD02D8 ) /* (CAN_MB6) MailBox Data High Register */ +#define AT91C_CAN_MB6_MMR ( 0xFFFD02C0 ) /* (CAN_MB6) MailBox Mode Register */ +/* ========== Register definition for CAN_MB7 peripheral ========== */ +#define AT91C_CAN_MB7_MCR ( 0xFFFD02FC ) /* (CAN_MB7) MailBox Control Register */ +#define AT91C_CAN_MB7_MDH ( 0xFFFD02F8 ) /* (CAN_MB7) MailBox Data High Register */ +#define AT91C_CAN_MB7_MFID ( 0xFFFD02EC ) /* (CAN_MB7) MailBox Family ID Register */ +#define AT91C_CAN_MB7_MDL ( 0xFFFD02F4 ) /* (CAN_MB7) MailBox Data Low Register */ +#define AT91C_CAN_MB7_MID ( 0xFFFD02E8 ) /* (CAN_MB7) MailBox ID Register */ +#define AT91C_CAN_MB7_MMR ( 0xFFFD02E0 ) /* (CAN_MB7) MailBox Mode Register */ +#define AT91C_CAN_MB7_MAM ( 0xFFFD02E4 ) /* (CAN_MB7) MailBox Acceptance Mask Register */ +#define AT91C_CAN_MB7_MSR ( 0xFFFD02F0 ) /* (CAN_MB7) MailBox Status Register */ +/* ========== Register definition for CAN peripheral ========== */ +#define AT91C_CAN_TCR ( 0xFFFD0024 ) /* (CAN) Transfer Command Register */ +#define AT91C_CAN_IMR ( 0xFFFD000C ) /* (CAN) Interrupt Mask Register */ +#define AT91C_CAN_IER ( 0xFFFD0004 ) /* (CAN) Interrupt Enable Register */ +#define AT91C_CAN_ECR ( 0xFFFD0020 ) /* (CAN) Error Counter Register */ +#define AT91C_CAN_TIMESTP ( 0xFFFD001C ) /* (CAN) Time Stamp Register */ +#define AT91C_CAN_MR ( 0xFFFD0000 ) /* (CAN) Mode Register */ +#define AT91C_CAN_IDR ( 0xFFFD0008 ) /* (CAN) Interrupt Disable Register */ +#define AT91C_CAN_ACR ( 0xFFFD0028 ) /* (CAN) Abort Command Register */ +#define AT91C_CAN_TIM ( 0xFFFD0018 ) /* (CAN) Timer Register */ +#define AT91C_CAN_SR ( 0xFFFD0010 ) /* (CAN) Status Register */ +#define AT91C_CAN_BR ( 0xFFFD0014 ) /* (CAN) Baudrate Register */ +#define AT91C_CAN_VR ( 0xFFFD00FC ) /* (CAN) Version Register */ +/* ========== Register definition for EMAC peripheral ========== */ +#define AT91C_EMAC_ISR ( 0xFFFDC024 ) /* (EMAC) Interrupt Status Register */ +#define AT91C_EMAC_SA4H ( 0xFFFDC0B4 ) /* (EMAC) Specific Address 4 Top, Last 2 bytes */ +#define AT91C_EMAC_SA1L ( 0xFFFDC098 ) /* (EMAC) Specific Address 1 Bottom, First 4 bytes */ +#define AT91C_EMAC_ELE ( 0xFFFDC078 ) /* (EMAC) Excessive Length Errors Register */ +#define AT91C_EMAC_LCOL ( 0xFFFDC05C ) /* (EMAC) Late Collision Register */ +#define AT91C_EMAC_RLE ( 0xFFFDC088 ) /* (EMAC) Receive Length Field Mismatch Register */ +#define AT91C_EMAC_WOL ( 0xFFFDC0C4 ) /* (EMAC) Wake On LAN Register */ +#define AT91C_EMAC_DTF ( 0xFFFDC058 ) /* (EMAC) Deferred Transmission Frame Register */ +#define AT91C_EMAC_TUND ( 0xFFFDC064 ) /* (EMAC) Transmit Underrun Error Register */ +#define AT91C_EMAC_NCR ( 0xFFFDC000 ) /* (EMAC) Network Control Register */ +#define AT91C_EMAC_SA4L ( 0xFFFDC0B0 ) /* (EMAC) Specific Address 4 Bottom, First 4 bytes */ +#define AT91C_EMAC_RSR ( 0xFFFDC020 ) /* (EMAC) Receive Status Register */ +#define AT91C_EMAC_SA3L ( 0xFFFDC0A8 ) /* (EMAC) Specific Address 3 Bottom, First 4 bytes */ +#define AT91C_EMAC_TSR ( 0xFFFDC014 ) /* (EMAC) Transmit Status Register */ +#define AT91C_EMAC_IDR ( 0xFFFDC02C ) /* (EMAC) Interrupt Disable Register */ +#define AT91C_EMAC_RSE ( 0xFFFDC074 ) /* (EMAC) Receive Symbol Errors Register */ +#define AT91C_EMAC_ECOL ( 0xFFFDC060 ) /* (EMAC) Excessive Collision Register */ +#define AT91C_EMAC_TID ( 0xFFFDC0B8 ) /* (EMAC) Type ID Checking Register */ +#define AT91C_EMAC_HRB ( 0xFFFDC090 ) /* (EMAC) Hash Address Bottom[31:0] */ +#define AT91C_EMAC_TBQP ( 0xFFFDC01C ) /* (EMAC) Transmit Buffer Queue Pointer */ +#define AT91C_EMAC_USRIO ( 0xFFFDC0C0 ) /* (EMAC) USER Input/Output Register */ +#define AT91C_EMAC_PTR ( 0xFFFDC038 ) /* (EMAC) Pause Time Register */ +#define AT91C_EMAC_SA2H ( 0xFFFDC0A4 ) /* (EMAC) Specific Address 2 Top, Last 2 bytes */ +#define AT91C_EMAC_ROV ( 0xFFFDC070 ) /* (EMAC) Receive Overrun Errors Register */ +#define AT91C_EMAC_ALE ( 0xFFFDC054 ) /* (EMAC) Alignment Error Register */ +#define AT91C_EMAC_RJA ( 0xFFFDC07C ) /* (EMAC) Receive Jabbers Register */ +#define AT91C_EMAC_RBQP ( 0xFFFDC018 ) /* (EMAC) Receive Buffer Queue Pointer */ +#define AT91C_EMAC_TPF ( 0xFFFDC08C ) /* (EMAC) Transmitted Pause Frames Register */ +#define AT91C_EMAC_NCFGR ( 0xFFFDC004 ) /* (EMAC) Network Configuration Register */ +#define AT91C_EMAC_HRT ( 0xFFFDC094 ) /* (EMAC) Hash Address Top[63:32] */ +#define AT91C_EMAC_USF ( 0xFFFDC080 ) /* (EMAC) Undersize Frames Register */ +#define AT91C_EMAC_FCSE ( 0xFFFDC050 ) /* (EMAC) Frame Check Sequence Error Register */ +#define AT91C_EMAC_TPQ ( 0xFFFDC0BC ) /* (EMAC) Transmit Pause Quantum Register */ +#define AT91C_EMAC_MAN ( 0xFFFDC034 ) /* (EMAC) PHY Maintenance Register */ +#define AT91C_EMAC_FTO ( 0xFFFDC040 ) /* (EMAC) Frames Transmitted OK Register */ +#define AT91C_EMAC_REV ( 0xFFFDC0FC ) /* (EMAC) Revision Register */ +#define AT91C_EMAC_IMR ( 0xFFFDC030 ) /* (EMAC) Interrupt Mask Register */ +#define AT91C_EMAC_SCF ( 0xFFFDC044 ) /* (EMAC) Single Collision Frame Register */ +#define AT91C_EMAC_PFR ( 0xFFFDC03C ) /* (EMAC) Pause Frames received Register */ +#define AT91C_EMAC_MCF ( 0xFFFDC048 ) /* (EMAC) Multiple Collision Frame Register */ +#define AT91C_EMAC_NSR ( 0xFFFDC008 ) /* (EMAC) Network Status Register */ +#define AT91C_EMAC_SA2L ( 0xFFFDC0A0 ) /* (EMAC) Specific Address 2 Bottom, First 4 bytes */ +#define AT91C_EMAC_FRO ( 0xFFFDC04C ) /* (EMAC) Frames Received OK Register */ +#define AT91C_EMAC_IER ( 0xFFFDC028 ) /* (EMAC) Interrupt Enable Register */ +#define AT91C_EMAC_SA1H ( 0xFFFDC09C ) /* (EMAC) Specific Address 1 Top, Last 2 bytes */ +#define AT91C_EMAC_CSE ( 0xFFFDC068 ) /* (EMAC) Carrier Sense Error Register */ +#define AT91C_EMAC_SA3H ( 0xFFFDC0AC ) /* (EMAC) Specific Address 3 Top, Last 2 bytes */ +#define AT91C_EMAC_RRE ( 0xFFFDC06C ) /* (EMAC) Receive Ressource Error Register */ +#define AT91C_EMAC_STE ( 0xFFFDC084 ) /* (EMAC) SQE Test Error Register */ +/* ========== Register definition for PDC_ADC peripheral ========== */ +#define AT91C_ADC_PTSR ( 0xFFFD8124 ) /* (PDC_ADC) PDC Transfer Status Register */ +#define AT91C_ADC_PTCR ( 0xFFFD8120 ) /* (PDC_ADC) PDC Transfer Control Register */ +#define AT91C_ADC_TNPR ( 0xFFFD8118 ) /* (PDC_ADC) Transmit Next Pointer Register */ +#define AT91C_ADC_TNCR ( 0xFFFD811C ) /* (PDC_ADC) Transmit Next Counter Register */ +#define AT91C_ADC_RNPR ( 0xFFFD8110 ) /* (PDC_ADC) Receive Next Pointer Register */ +#define AT91C_ADC_RNCR ( 0xFFFD8114 ) /* (PDC_ADC) Receive Next Counter Register */ +#define AT91C_ADC_RPR ( 0xFFFD8100 ) /* (PDC_ADC) Receive Pointer Register */ +#define AT91C_ADC_TCR ( 0xFFFD810C ) /* (PDC_ADC) Transmit Counter Register */ +#define AT91C_ADC_TPR ( 0xFFFD8108 ) /* (PDC_ADC) Transmit Pointer Register */ +#define AT91C_ADC_RCR ( 0xFFFD8104 ) /* (PDC_ADC) Receive Counter Register */ +/* ========== Register definition for ADC peripheral ========== */ +#define AT91C_ADC_CDR2 ( 0xFFFD8038 ) /* (ADC) ADC Channel Data Register 2 */ +#define AT91C_ADC_CDR3 ( 0xFFFD803C ) /* (ADC) ADC Channel Data Register 3 */ +#define AT91C_ADC_CDR0 ( 0xFFFD8030 ) /* (ADC) ADC Channel Data Register 0 */ +#define AT91C_ADC_CDR5 ( 0xFFFD8044 ) /* (ADC) ADC Channel Data Register 5 */ +#define AT91C_ADC_CHDR ( 0xFFFD8014 ) /* (ADC) ADC Channel Disable Register */ +#define AT91C_ADC_SR ( 0xFFFD801C ) /* (ADC) ADC Status Register */ +#define AT91C_ADC_CDR4 ( 0xFFFD8040 ) /* (ADC) ADC Channel Data Register 4 */ +#define AT91C_ADC_CDR1 ( 0xFFFD8034 ) /* (ADC) ADC Channel Data Register 1 */ +#define AT91C_ADC_LCDR ( 0xFFFD8020 ) /* (ADC) ADC Last Converted Data Register */ +#define AT91C_ADC_IDR ( 0xFFFD8028 ) /* (ADC) ADC Interrupt Disable Register */ +#define AT91C_ADC_CR ( 0xFFFD8000 ) /* (ADC) ADC Control Register */ +#define AT91C_ADC_CDR7 ( 0xFFFD804C ) /* (ADC) ADC Channel Data Register 7 */ +#define AT91C_ADC_CDR6 ( 0xFFFD8048 ) /* (ADC) ADC Channel Data Register 6 */ +#define AT91C_ADC_IER ( 0xFFFD8024 ) /* (ADC) ADC Interrupt Enable Register */ +#define AT91C_ADC_CHER ( 0xFFFD8010 ) /* (ADC) ADC Channel Enable Register */ +#define AT91C_ADC_CHSR ( 0xFFFD8018 ) /* (ADC) ADC Channel Status Register */ +#define AT91C_ADC_MR ( 0xFFFD8004 ) /* (ADC) ADC Mode Register */ +#define AT91C_ADC_IMR ( 0xFFFD802C ) /* (ADC) ADC Interrupt Mask Register */ +/* ========== Register definition for PDC_AES peripheral ========== */ +#define AT91C_AES_TPR ( 0xFFFA4108 ) /* (PDC_AES) Transmit Pointer Register */ +#define AT91C_AES_PTCR ( 0xFFFA4120 ) /* (PDC_AES) PDC Transfer Control Register */ +#define AT91C_AES_RNPR ( 0xFFFA4110 ) /* (PDC_AES) Receive Next Pointer Register */ +#define AT91C_AES_TNCR ( 0xFFFA411C ) /* (PDC_AES) Transmit Next Counter Register */ +#define AT91C_AES_TCR ( 0xFFFA410C ) /* (PDC_AES) Transmit Counter Register */ +#define AT91C_AES_RCR ( 0xFFFA4104 ) /* (PDC_AES) Receive Counter Register */ +#define AT91C_AES_RNCR ( 0xFFFA4114 ) /* (PDC_AES) Receive Next Counter Register */ +#define AT91C_AES_TNPR ( 0xFFFA4118 ) /* (PDC_AES) Transmit Next Pointer Register */ +#define AT91C_AES_RPR ( 0xFFFA4100 ) /* (PDC_AES) Receive Pointer Register */ +#define AT91C_AES_PTSR ( 0xFFFA4124 ) /* (PDC_AES) PDC Transfer Status Register */ +/* ========== Register definition for AES peripheral ========== */ +#define AT91C_AES_IVxR ( 0xFFFA4060 ) /* (AES) Initialization Vector x Register */ +#define AT91C_AES_MR ( 0xFFFA4004 ) /* (AES) Mode Register */ +#define AT91C_AES_VR ( 0xFFFA40FC ) /* (AES) AES Version Register */ +#define AT91C_AES_ODATAxR ( 0xFFFA4050 ) /* (AES) Output Data x Register */ +#define AT91C_AES_IDATAxR ( 0xFFFA4040 ) /* (AES) Input Data x Register */ +#define AT91C_AES_CR ( 0xFFFA4000 ) /* (AES) Control Register */ +#define AT91C_AES_IDR ( 0xFFFA4014 ) /* (AES) Interrupt Disable Register */ +#define AT91C_AES_IMR ( 0xFFFA4018 ) /* (AES) Interrupt Mask Register */ +#define AT91C_AES_IER ( 0xFFFA4010 ) /* (AES) Interrupt Enable Register */ +#define AT91C_AES_KEYWxR ( 0xFFFA4020 ) /* (AES) Key Word x Register */ +#define AT91C_AES_ISR ( 0xFFFA401C ) /* (AES) Interrupt Status Register */ +/* ========== Register definition for PDC_TDES peripheral ========== */ +#define AT91C_TDES_RNCR ( 0xFFFA8114 ) /* (PDC_TDES) Receive Next Counter Register */ +#define AT91C_TDES_TCR ( 0xFFFA810C ) /* (PDC_TDES) Transmit Counter Register */ +#define AT91C_TDES_RCR ( 0xFFFA8104 ) /* (PDC_TDES) Receive Counter Register */ +#define AT91C_TDES_TNPR ( 0xFFFA8118 ) /* (PDC_TDES) Transmit Next Pointer Register */ +#define AT91C_TDES_RNPR ( 0xFFFA8110 ) /* (PDC_TDES) Receive Next Pointer Register */ +#define AT91C_TDES_RPR ( 0xFFFA8100 ) /* (PDC_TDES) Receive Pointer Register */ +#define AT91C_TDES_TNCR ( 0xFFFA811C ) /* (PDC_TDES) Transmit Next Counter Register */ +#define AT91C_TDES_TPR ( 0xFFFA8108 ) /* (PDC_TDES) Transmit Pointer Register */ +#define AT91C_TDES_PTSR ( 0xFFFA8124 ) /* (PDC_TDES) PDC Transfer Status Register */ +#define AT91C_TDES_PTCR ( 0xFFFA8120 ) /* (PDC_TDES) PDC Transfer Control Register */ +/* ========== Register definition for TDES peripheral ========== */ +#define AT91C_TDES_KEY2WxR ( 0xFFFA8028 ) /* (TDES) Key 2 Word x Register */ +#define AT91C_TDES_KEY3WxR ( 0xFFFA8030 ) /* (TDES) Key 3 Word x Register */ +#define AT91C_TDES_IDR ( 0xFFFA8014 ) /* (TDES) Interrupt Disable Register */ +#define AT91C_TDES_VR ( 0xFFFA80FC ) /* (TDES) TDES Version Register */ +#define AT91C_TDES_IVxR ( 0xFFFA8060 ) /* (TDES) Initialization Vector x Register */ +#define AT91C_TDES_ODATAxR ( 0xFFFA8050 ) /* (TDES) Output Data x Register */ +#define AT91C_TDES_IMR ( 0xFFFA8018 ) /* (TDES) Interrupt Mask Register */ +#define AT91C_TDES_MR ( 0xFFFA8004 ) /* (TDES) Mode Register */ +#define AT91C_TDES_CR ( 0xFFFA8000 ) /* (TDES) Control Register */ +#define AT91C_TDES_IER ( 0xFFFA8010 ) /* (TDES) Interrupt Enable Register */ +#define AT91C_TDES_ISR ( 0xFFFA801C ) /* (TDES) Interrupt Status Register */ +#define AT91C_TDES_IDATAxR ( 0xFFFA8040 ) /* (TDES) Input Data x Register */ +#define AT91C_TDES_KEY1WxR ( 0xFFFA8020 ) /* (TDES) Key 1 Word x Register */ -// ***************************************************************************** -// PIO DEFINITIONS FOR AT91SAM7X128 -// ***************************************************************************** -#define AT91C_PIO_PA0 (1 << 0) // Pin Controlled by PA0 -#define AT91C_PA0_RXD0 (AT91C_PIO_PA0) // USART 0 Receive Data -#define AT91C_PIO_PA1 (1 << 1) // Pin Controlled by PA1 -#define AT91C_PA1_TXD0 (AT91C_PIO_PA1) // USART 0 Transmit Data -#define AT91C_PIO_PA10 (1 << 10) // Pin Controlled by PA10 -#define AT91C_PA10_TWD (AT91C_PIO_PA10) // TWI Two-wire Serial Data -#define AT91C_PIO_PA11 (1 << 11) // Pin Controlled by PA11 -#define AT91C_PA11_TWCK (AT91C_PIO_PA11) // TWI Two-wire Serial Clock -#define AT91C_PIO_PA12 (1 << 12) // Pin Controlled by PA12 -#define AT91C_PA12_NPCS00 (AT91C_PIO_PA12) // SPI 0 Peripheral Chip Select 0 -#define AT91C_PIO_PA13 (1 << 13) // Pin Controlled by PA13 -#define AT91C_PA13_NPCS01 (AT91C_PIO_PA13) // SPI 0 Peripheral Chip Select 1 -#define AT91C_PA13_PCK1 (AT91C_PIO_PA13) // PMC Programmable Clock Output 1 -#define AT91C_PIO_PA14 (1 << 14) // Pin Controlled by PA14 -#define AT91C_PA14_NPCS02 (AT91C_PIO_PA14) // SPI 0 Peripheral Chip Select 2 -#define AT91C_PA14_IRQ1 (AT91C_PIO_PA14) // External Interrupt 1 -#define AT91C_PIO_PA15 (1 << 15) // Pin Controlled by PA15 -#define AT91C_PA15_NPCS03 (AT91C_PIO_PA15) // SPI 0 Peripheral Chip Select 3 -#define AT91C_PA15_TCLK2 (AT91C_PIO_PA15) // Timer Counter 2 external clock input -#define AT91C_PIO_PA16 (1 << 16) // Pin Controlled by PA16 -#define AT91C_PA16_MISO0 (AT91C_PIO_PA16) // SPI 0 Master In Slave -#define AT91C_PIO_PA17 (1 << 17) // Pin Controlled by PA17 -#define AT91C_PA17_MOSI0 (AT91C_PIO_PA17) // SPI 0 Master Out Slave -#define AT91C_PIO_PA18 (1 << 18) // Pin Controlled by PA18 -#define AT91C_PA18_SPCK0 (AT91C_PIO_PA18) // SPI 0 Serial Clock -#define AT91C_PIO_PA19 (1 << 19) // Pin Controlled by PA19 -#define AT91C_PA19_CANRX (AT91C_PIO_PA19) // CAN Receive -#define AT91C_PIO_PA2 (1 << 2) // Pin Controlled by PA2 -#define AT91C_PA2_SCK0 (AT91C_PIO_PA2) // USART 0 Serial Clock -#define AT91C_PA2_NPCS11 (AT91C_PIO_PA2) // SPI 1 Peripheral Chip Select 1 -#define AT91C_PIO_PA20 (1 << 20) // Pin Controlled by PA20 -#define AT91C_PA20_CANTX (AT91C_PIO_PA20) // CAN Transmit -#define AT91C_PIO_PA21 (1 << 21) // Pin Controlled by PA21 -#define AT91C_PA21_TF (AT91C_PIO_PA21) // SSC Transmit Frame Sync -#define AT91C_PA21_NPCS10 (AT91C_PIO_PA21) // SPI 1 Peripheral Chip Select 0 -#define AT91C_PIO_PA22 (1 << 22) // Pin Controlled by PA22 -#define AT91C_PA22_TK (AT91C_PIO_PA22) // SSC Transmit Clock -#define AT91C_PA22_SPCK1 (AT91C_PIO_PA22) // SPI 1 Serial Clock -#define AT91C_PIO_PA23 (1 << 23) // Pin Controlled by PA23 -#define AT91C_PA23_TD (AT91C_PIO_PA23) // SSC Transmit data -#define AT91C_PA23_MOSI1 (AT91C_PIO_PA23) // SPI 1 Master Out Slave -#define AT91C_PIO_PA24 (1 << 24) // Pin Controlled by PA24 -#define AT91C_PA24_RD (AT91C_PIO_PA24) // SSC Receive Data -#define AT91C_PA24_MISO1 (AT91C_PIO_PA24) // SPI 1 Master In Slave -#define AT91C_PIO_PA25 (1 << 25) // Pin Controlled by PA25 -#define AT91C_PA25_RK (AT91C_PIO_PA25) // SSC Receive Clock -#define AT91C_PA25_NPCS11 (AT91C_PIO_PA25) // SPI 1 Peripheral Chip Select 1 -#define AT91C_PIO_PA26 (1 << 26) // Pin Controlled by PA26 -#define AT91C_PA26_RF (AT91C_PIO_PA26) // SSC Receive Frame Sync -#define AT91C_PA26_NPCS12 (AT91C_PIO_PA26) // SPI 1 Peripheral Chip Select 2 -#define AT91C_PIO_PA27 (1 << 27) // Pin Controlled by PA27 -#define AT91C_PA27_DRXD (AT91C_PIO_PA27) // DBGU Debug Receive Data -#define AT91C_PA27_PCK3 (AT91C_PIO_PA27) // PMC Programmable Clock Output 3 -#define AT91C_PIO_PA28 (1 << 28) // Pin Controlled by PA28 -#define AT91C_PA28_DTXD (AT91C_PIO_PA28) // DBGU Debug Transmit Data -#define AT91C_PIO_PA29 (1 << 29) // Pin Controlled by PA29 -#define AT91C_PA29_FIQ (AT91C_PIO_PA29) // AIC Fast Interrupt Input -#define AT91C_PA29_NPCS13 (AT91C_PIO_PA29) // SPI 1 Peripheral Chip Select 3 -#define AT91C_PIO_PA3 (1 << 3) // Pin Controlled by PA3 -#define AT91C_PA3_RTS0 (AT91C_PIO_PA3) // USART 0 Ready To Send -#define AT91C_PA3_NPCS12 (AT91C_PIO_PA3) // SPI 1 Peripheral Chip Select 2 -#define AT91C_PIO_PA30 (1 << 30) // Pin Controlled by PA30 -#define AT91C_PA30_IRQ0 (AT91C_PIO_PA30) // External Interrupt 0 -#define AT91C_PA30_PCK2 (AT91C_PIO_PA30) // PMC Programmable Clock Output 2 -#define AT91C_PIO_PA4 (1 << 4) // Pin Controlled by PA4 -#define AT91C_PA4_CTS0 (AT91C_PIO_PA4) // USART 0 Clear To Send -#define AT91C_PA4_NPCS13 (AT91C_PIO_PA4) // SPI 1 Peripheral Chip Select 3 -#define AT91C_PIO_PA5 (1 << 5) // Pin Controlled by PA5 -#define AT91C_PA5_RXD1 (AT91C_PIO_PA5) // USART 1 Receive Data -#define AT91C_PIO_PA6 (1 << 6) // Pin Controlled by PA6 -#define AT91C_PA6_TXD1 (AT91C_PIO_PA6) // USART 1 Transmit Data -#define AT91C_PIO_PA7 (1 << 7) // Pin Controlled by PA7 -#define AT91C_PA7_SCK1 (AT91C_PIO_PA7) // USART 1 Serial Clock -#define AT91C_PA7_NPCS01 (AT91C_PIO_PA7) // SPI 0 Peripheral Chip Select 1 -#define AT91C_PIO_PA8 (1 << 8) // Pin Controlled by PA8 -#define AT91C_PA8_RTS1 (AT91C_PIO_PA8) // USART 1 Ready To Send -#define AT91C_PA8_NPCS02 (AT91C_PIO_PA8) // SPI 0 Peripheral Chip Select 2 -#define AT91C_PIO_PA9 (1 << 9) // Pin Controlled by PA9 -#define AT91C_PA9_CTS1 (AT91C_PIO_PA9) // USART 1 Clear To Send -#define AT91C_PA9_NPCS03 (AT91C_PIO_PA9) // SPI 0 Peripheral Chip Select 3 -#define AT91C_PIO_PB0 (1 << 0) // Pin Controlled by PB0 -#define AT91C_PB0_ETXCK_EREFCK (AT91C_PIO_PB0) // Ethernet MAC Transmit Clock/Reference Clock -#define AT91C_PB0_PCK0 (AT91C_PIO_PB0) // PMC Programmable Clock Output 0 -#define AT91C_PIO_PB1 (1 << 1) // Pin Controlled by PB1 -#define AT91C_PB1_ETXEN (AT91C_PIO_PB1) // Ethernet MAC Transmit Enable -#define AT91C_PIO_PB10 (1 << 10) // Pin Controlled by PB10 -#define AT91C_PB10_ETX2 (AT91C_PIO_PB10) // Ethernet MAC Transmit Data 2 -#define AT91C_PB10_NPCS11 (AT91C_PIO_PB10) // SPI 1 Peripheral Chip Select 1 -#define AT91C_PIO_PB11 (1 << 11) // Pin Controlled by PB11 -#define AT91C_PB11_ETX3 (AT91C_PIO_PB11) // Ethernet MAC Transmit Data 3 -#define AT91C_PB11_NPCS12 (AT91C_PIO_PB11) // SPI 1 Peripheral Chip Select 2 -#define AT91C_PIO_PB12 (1 << 12) // Pin Controlled by PB12 -#define AT91C_PB12_ETXER (AT91C_PIO_PB12) // Ethernet MAC Transmikt Coding Error -#define AT91C_PB12_TCLK0 (AT91C_PIO_PB12) // Timer Counter 0 external clock input -#define AT91C_PIO_PB13 (1 << 13) // Pin Controlled by PB13 -#define AT91C_PB13_ERX2 (AT91C_PIO_PB13) // Ethernet MAC Receive Data 2 -#define AT91C_PB13_NPCS01 (AT91C_PIO_PB13) // SPI 0 Peripheral Chip Select 1 -#define AT91C_PIO_PB14 (1 << 14) // Pin Controlled by PB14 -#define AT91C_PB14_ERX3 (AT91C_PIO_PB14) // Ethernet MAC Receive Data 3 -#define AT91C_PB14_NPCS02 (AT91C_PIO_PB14) // SPI 0 Peripheral Chip Select 2 -#define AT91C_PIO_PB15 (1 << 15) // Pin Controlled by PB15 -#define AT91C_PB15_ERXDV (AT91C_PIO_PB15) // Ethernet MAC Receive Data Valid -#define AT91C_PIO_PB16 (1 << 16) // Pin Controlled by PB16 -#define AT91C_PB16_ECOL (AT91C_PIO_PB16) // Ethernet MAC Collision Detected -#define AT91C_PB16_NPCS13 (AT91C_PIO_PB16) // SPI 1 Peripheral Chip Select 3 -#define AT91C_PIO_PB17 (1 << 17) // Pin Controlled by PB17 -#define AT91C_PB17_ERXCK (AT91C_PIO_PB17) // Ethernet MAC Receive Clock -#define AT91C_PB17_NPCS03 (AT91C_PIO_PB17) // SPI 0 Peripheral Chip Select 3 -#define AT91C_PIO_PB18 (1 << 18) // Pin Controlled by PB18 -#define AT91C_PB18_EF100 (AT91C_PIO_PB18) // Ethernet MAC Force 100 Mbits/sec -#define AT91C_PB18_ADTRG (AT91C_PIO_PB18) // ADC External Trigger -#define AT91C_PIO_PB19 (1 << 19) // Pin Controlled by PB19 -#define AT91C_PB19_PWM0 (AT91C_PIO_PB19) // PWM Channel 0 -#define AT91C_PB19_TCLK1 (AT91C_PIO_PB19) // Timer Counter 1 external clock input -#define AT91C_PIO_PB2 (1 << 2) // Pin Controlled by PB2 -#define AT91C_PB2_ETX0 (AT91C_PIO_PB2) // Ethernet MAC Transmit Data 0 -#define AT91C_PIO_PB20 (1 << 20) // Pin Controlled by PB20 -#define AT91C_PB20_PWM1 (AT91C_PIO_PB20) // PWM Channel 1 -#define AT91C_PB20_PCK0 (AT91C_PIO_PB20) // PMC Programmable Clock Output 0 -#define AT91C_PIO_PB21 (1 << 21) // Pin Controlled by PB21 -#define AT91C_PB21_PWM2 (AT91C_PIO_PB21) // PWM Channel 2 -#define AT91C_PB21_PCK1 (AT91C_PIO_PB21) // PMC Programmable Clock Output 1 -#define AT91C_PIO_PB22 (1 << 22) // Pin Controlled by PB22 -#define AT91C_PB22_PWM3 (AT91C_PIO_PB22) // PWM Channel 3 -#define AT91C_PB22_PCK2 (AT91C_PIO_PB22) // PMC Programmable Clock Output 2 -#define AT91C_PIO_PB23 (1 << 23) // Pin Controlled by PB23 -#define AT91C_PB23_TIOA0 (AT91C_PIO_PB23) // Timer Counter 0 Multipurpose Timer I/O Pin A -#define AT91C_PB23_DCD1 (AT91C_PIO_PB23) // USART 1 Data Carrier Detect -#define AT91C_PIO_PB24 (1 << 24) // Pin Controlled by PB24 -#define AT91C_PB24_TIOB0 (AT91C_PIO_PB24) // Timer Counter 0 Multipurpose Timer I/O Pin B -#define AT91C_PB24_DSR1 (AT91C_PIO_PB24) // USART 1 Data Set ready -#define AT91C_PIO_PB25 (1 << 25) // Pin Controlled by PB25 -#define AT91C_PB25_TIOA1 (AT91C_PIO_PB25) // Timer Counter 1 Multipurpose Timer I/O Pin A -#define AT91C_PB25_DTR1 (AT91C_PIO_PB25) // USART 1 Data Terminal ready -#define AT91C_PIO_PB26 (1 << 26) // Pin Controlled by PB26 -#define AT91C_PB26_TIOB1 (AT91C_PIO_PB26) // Timer Counter 1 Multipurpose Timer I/O Pin B -#define AT91C_PB26_RI1 (AT91C_PIO_PB26) // USART 1 Ring Indicator -#define AT91C_PIO_PB27 (1 << 27) // Pin Controlled by PB27 -#define AT91C_PB27_TIOA2 (AT91C_PIO_PB27) // Timer Counter 2 Multipurpose Timer I/O Pin A -#define AT91C_PB27_PWM0 (AT91C_PIO_PB27) // PWM Channel 0 -#define AT91C_PIO_PB28 (1 << 28) // Pin Controlled by PB28 -#define AT91C_PB28_TIOB2 (AT91C_PIO_PB28) // Timer Counter 2 Multipurpose Timer I/O Pin B -#define AT91C_PB28_PWM1 (AT91C_PIO_PB28) // PWM Channel 1 -#define AT91C_PIO_PB29 (1 << 29) // Pin Controlled by PB29 -#define AT91C_PB29_PCK1 (AT91C_PIO_PB29) // PMC Programmable Clock Output 1 -#define AT91C_PB29_PWM2 (AT91C_PIO_PB29) // PWM Channel 2 -#define AT91C_PIO_PB3 (1 << 3) // Pin Controlled by PB3 -#define AT91C_PB3_ETX1 (AT91C_PIO_PB3) // Ethernet MAC Transmit Data 1 -#define AT91C_PIO_PB30 (1 << 30) // Pin Controlled by PB30 -#define AT91C_PB30_PCK2 (AT91C_PIO_PB30) // PMC Programmable Clock Output 2 -#define AT91C_PB30_PWM3 (AT91C_PIO_PB30) // PWM Channel 3 -#define AT91C_PIO_PB4 (1 << 4) // Pin Controlled by PB4 -#define AT91C_PB4_ECRS_ECRSDV (AT91C_PIO_PB4) // Ethernet MAC Carrier Sense/Carrier Sense and Data Valid -#define AT91C_PIO_PB5 (1 << 5) // Pin Controlled by PB5 -#define AT91C_PB5_ERX0 (AT91C_PIO_PB5) // Ethernet MAC Receive Data 0 -#define AT91C_PIO_PB6 (1 << 6) // Pin Controlled by PB6 -#define AT91C_PB6_ERX1 (AT91C_PIO_PB6) // Ethernet MAC Receive Data 1 -#define AT91C_PIO_PB7 (1 << 7) // Pin Controlled by PB7 -#define AT91C_PB7_ERXER (AT91C_PIO_PB7) // Ethernet MAC Receive Error -#define AT91C_PIO_PB8 (1 << 8) // Pin Controlled by PB8 -#define AT91C_PB8_EMDC (AT91C_PIO_PB8) // Ethernet MAC Management Data Clock -#define AT91C_PIO_PB9 (1 << 9) // Pin Controlled by PB9 -#define AT91C_PB9_EMDIO (AT91C_PIO_PB9) // Ethernet MAC Management Data Input/Output +/* ***************************************************************************** */ +/* PIO DEFINITIONS FOR AT91SAM7X128 */ +/* ***************************************************************************** */ +#define AT91C_PIO_PA0 ( 1 << 0 ) /* Pin Controlled by PA0 */ +#define AT91C_PA0_RXD0 ( AT91C_PIO_PA0 ) /* USART 0 Receive Data */ +#define AT91C_PIO_PA1 ( 1 << 1 ) /* Pin Controlled by PA1 */ +#define AT91C_PA1_TXD0 ( AT91C_PIO_PA1 ) /* USART 0 Transmit Data */ +#define AT91C_PIO_PA10 ( 1 << 10 ) /* Pin Controlled by PA10 */ +#define AT91C_PA10_TWD ( AT91C_PIO_PA10 ) /* TWI Two-wire Serial Data */ +#define AT91C_PIO_PA11 ( 1 << 11 ) /* Pin Controlled by PA11 */ +#define AT91C_PA11_TWCK ( AT91C_PIO_PA11 ) /* TWI Two-wire Serial Clock */ +#define AT91C_PIO_PA12 ( 1 << 12 ) /* Pin Controlled by PA12 */ +#define AT91C_PA12_NPCS00 ( AT91C_PIO_PA12 ) /* SPI 0 Peripheral Chip Select 0 */ +#define AT91C_PIO_PA13 ( 1 << 13 ) /* Pin Controlled by PA13 */ +#define AT91C_PA13_NPCS01 ( AT91C_PIO_PA13 ) /* SPI 0 Peripheral Chip Select 1 */ +#define AT91C_PA13_PCK1 ( AT91C_PIO_PA13 ) /* PMC Programmable Clock Output 1 */ +#define AT91C_PIO_PA14 ( 1 << 14 ) /* Pin Controlled by PA14 */ +#define AT91C_PA14_NPCS02 ( AT91C_PIO_PA14 ) /* SPI 0 Peripheral Chip Select 2 */ +#define AT91C_PA14_IRQ1 ( AT91C_PIO_PA14 ) /* External Interrupt 1 */ +#define AT91C_PIO_PA15 ( 1 << 15 ) /* Pin Controlled by PA15 */ +#define AT91C_PA15_NPCS03 ( AT91C_PIO_PA15 ) /* SPI 0 Peripheral Chip Select 3 */ +#define AT91C_PA15_TCLK2 ( AT91C_PIO_PA15 ) /* Timer Counter 2 external clock input */ +#define AT91C_PIO_PA16 ( 1 << 16 ) /* Pin Controlled by PA16 */ +#define AT91C_PA16_MISO0 ( AT91C_PIO_PA16 ) /* SPI 0 Master In Slave */ +#define AT91C_PIO_PA17 ( 1 << 17 ) /* Pin Controlled by PA17 */ +#define AT91C_PA17_MOSI0 ( AT91C_PIO_PA17 ) /* SPI 0 Master Out Slave */ +#define AT91C_PIO_PA18 ( 1 << 18 ) /* Pin Controlled by PA18 */ +#define AT91C_PA18_SPCK0 ( AT91C_PIO_PA18 ) /* SPI 0 Serial Clock */ +#define AT91C_PIO_PA19 ( 1 << 19 ) /* Pin Controlled by PA19 */ +#define AT91C_PA19_CANRX ( AT91C_PIO_PA19 ) /* CAN Receive */ +#define AT91C_PIO_PA2 ( 1 << 2 ) /* Pin Controlled by PA2 */ +#define AT91C_PA2_SCK0 ( AT91C_PIO_PA2 ) /* USART 0 Serial Clock */ +#define AT91C_PA2_NPCS11 ( AT91C_PIO_PA2 ) /* SPI 1 Peripheral Chip Select 1 */ +#define AT91C_PIO_PA20 ( 1 << 20 ) /* Pin Controlled by PA20 */ +#define AT91C_PA20_CANTX ( AT91C_PIO_PA20 ) /* CAN Transmit */ +#define AT91C_PIO_PA21 ( 1 << 21 ) /* Pin Controlled by PA21 */ +#define AT91C_PA21_TF ( AT91C_PIO_PA21 ) /* SSC Transmit Frame Sync */ +#define AT91C_PA21_NPCS10 ( AT91C_PIO_PA21 ) /* SPI 1 Peripheral Chip Select 0 */ +#define AT91C_PIO_PA22 ( 1 << 22 ) /* Pin Controlled by PA22 */ +#define AT91C_PA22_TK ( AT91C_PIO_PA22 ) /* SSC Transmit Clock */ +#define AT91C_PA22_SPCK1 ( AT91C_PIO_PA22 ) /* SPI 1 Serial Clock */ +#define AT91C_PIO_PA23 ( 1 << 23 ) /* Pin Controlled by PA23 */ +#define AT91C_PA23_TD ( AT91C_PIO_PA23 ) /* SSC Transmit data */ +#define AT91C_PA23_MOSI1 ( AT91C_PIO_PA23 ) /* SPI 1 Master Out Slave */ +#define AT91C_PIO_PA24 ( 1 << 24 ) /* Pin Controlled by PA24 */ +#define AT91C_PA24_RD ( AT91C_PIO_PA24 ) /* SSC Receive Data */ +#define AT91C_PA24_MISO1 ( AT91C_PIO_PA24 ) /* SPI 1 Master In Slave */ +#define AT91C_PIO_PA25 ( 1 << 25 ) /* Pin Controlled by PA25 */ +#define AT91C_PA25_RK ( AT91C_PIO_PA25 ) /* SSC Receive Clock */ +#define AT91C_PA25_NPCS11 ( AT91C_PIO_PA25 ) /* SPI 1 Peripheral Chip Select 1 */ +#define AT91C_PIO_PA26 ( 1 << 26 ) /* Pin Controlled by PA26 */ +#define AT91C_PA26_RF ( AT91C_PIO_PA26 ) /* SSC Receive Frame Sync */ +#define AT91C_PA26_NPCS12 ( AT91C_PIO_PA26 ) /* SPI 1 Peripheral Chip Select 2 */ +#define AT91C_PIO_PA27 ( 1 << 27 ) /* Pin Controlled by PA27 */ +#define AT91C_PA27_DRXD ( AT91C_PIO_PA27 ) /* DBGU Debug Receive Data */ +#define AT91C_PA27_PCK3 ( AT91C_PIO_PA27 ) /* PMC Programmable Clock Output 3 */ +#define AT91C_PIO_PA28 ( 1 << 28 ) /* Pin Controlled by PA28 */ +#define AT91C_PA28_DTXD ( AT91C_PIO_PA28 ) /* DBGU Debug Transmit Data */ +#define AT91C_PIO_PA29 ( 1 << 29 ) /* Pin Controlled by PA29 */ +#define AT91C_PA29_FIQ ( AT91C_PIO_PA29 ) /* AIC Fast Interrupt Input */ +#define AT91C_PA29_NPCS13 ( AT91C_PIO_PA29 ) /* SPI 1 Peripheral Chip Select 3 */ +#define AT91C_PIO_PA3 ( 1 << 3 ) /* Pin Controlled by PA3 */ +#define AT91C_PA3_RTS0 ( AT91C_PIO_PA3 ) /* USART 0 Ready To Send */ +#define AT91C_PA3_NPCS12 ( AT91C_PIO_PA3 ) /* SPI 1 Peripheral Chip Select 2 */ +#define AT91C_PIO_PA30 ( 1 << 30 ) /* Pin Controlled by PA30 */ +#define AT91C_PA30_IRQ0 ( AT91C_PIO_PA30 ) /* External Interrupt 0 */ +#define AT91C_PA30_PCK2 ( AT91C_PIO_PA30 ) /* PMC Programmable Clock Output 2 */ +#define AT91C_PIO_PA4 ( 1 << 4 ) /* Pin Controlled by PA4 */ +#define AT91C_PA4_CTS0 ( AT91C_PIO_PA4 ) /* USART 0 Clear To Send */ +#define AT91C_PA4_NPCS13 ( AT91C_PIO_PA4 ) /* SPI 1 Peripheral Chip Select 3 */ +#define AT91C_PIO_PA5 ( 1 << 5 ) /* Pin Controlled by PA5 */ +#define AT91C_PA5_RXD1 ( AT91C_PIO_PA5 ) /* USART 1 Receive Data */ +#define AT91C_PIO_PA6 ( 1 << 6 ) /* Pin Controlled by PA6 */ +#define AT91C_PA6_TXD1 ( AT91C_PIO_PA6 ) /* USART 1 Transmit Data */ +#define AT91C_PIO_PA7 ( 1 << 7 ) /* Pin Controlled by PA7 */ +#define AT91C_PA7_SCK1 ( AT91C_PIO_PA7 ) /* USART 1 Serial Clock */ +#define AT91C_PA7_NPCS01 ( AT91C_PIO_PA7 ) /* SPI 0 Peripheral Chip Select 1 */ +#define AT91C_PIO_PA8 ( 1 << 8 ) /* Pin Controlled by PA8 */ +#define AT91C_PA8_RTS1 ( AT91C_PIO_PA8 ) /* USART 1 Ready To Send */ +#define AT91C_PA8_NPCS02 ( AT91C_PIO_PA8 ) /* SPI 0 Peripheral Chip Select 2 */ +#define AT91C_PIO_PA9 ( 1 << 9 ) /* Pin Controlled by PA9 */ +#define AT91C_PA9_CTS1 ( AT91C_PIO_PA9 ) /* USART 1 Clear To Send */ +#define AT91C_PA9_NPCS03 ( AT91C_PIO_PA9 ) /* SPI 0 Peripheral Chip Select 3 */ +#define AT91C_PIO_PB0 ( 1 << 0 ) /* Pin Controlled by PB0 */ +#define AT91C_PB0_ETXCK_EREFCK ( AT91C_PIO_PB0 ) /* Ethernet MAC Transmit Clock/Reference Clock */ +#define AT91C_PB0_PCK0 ( AT91C_PIO_PB0 ) /* PMC Programmable Clock Output 0 */ +#define AT91C_PIO_PB1 ( 1 << 1 ) /* Pin Controlled by PB1 */ +#define AT91C_PB1_ETXEN ( AT91C_PIO_PB1 ) /* Ethernet MAC Transmit Enable */ +#define AT91C_PIO_PB10 ( 1 << 10 ) /* Pin Controlled by PB10 */ +#define AT91C_PB10_ETX2 ( AT91C_PIO_PB10 ) /* Ethernet MAC Transmit Data 2 */ +#define AT91C_PB10_NPCS11 ( AT91C_PIO_PB10 ) /* SPI 1 Peripheral Chip Select 1 */ +#define AT91C_PIO_PB11 ( 1 << 11 ) /* Pin Controlled by PB11 */ +#define AT91C_PB11_ETX3 ( AT91C_PIO_PB11 ) /* Ethernet MAC Transmit Data 3 */ +#define AT91C_PB11_NPCS12 ( AT91C_PIO_PB11 ) /* SPI 1 Peripheral Chip Select 2 */ +#define AT91C_PIO_PB12 ( 1 << 12 ) /* Pin Controlled by PB12 */ +#define AT91C_PB12_ETXER ( AT91C_PIO_PB12 ) /* Ethernet MAC Transmit Coding Error */ +#define AT91C_PB12_TCLK0 ( AT91C_PIO_PB12 ) /* Timer Counter 0 external clock input */ +#define AT91C_PIO_PB13 ( 1 << 13 ) /* Pin Controlled by PB13 */ +#define AT91C_PB13_ERX2 ( AT91C_PIO_PB13 ) /* Ethernet MAC Receive Data 2 */ +#define AT91C_PB13_NPCS01 ( AT91C_PIO_PB13 ) /* SPI 0 Peripheral Chip Select 1 */ +#define AT91C_PIO_PB14 ( 1 << 14 ) /* Pin Controlled by PB14 */ +#define AT91C_PB14_ERX3 ( AT91C_PIO_PB14 ) /* Ethernet MAC Receive Data 3 */ +#define AT91C_PB14_NPCS02 ( AT91C_PIO_PB14 ) /* SPI 0 Peripheral Chip Select 2 */ +#define AT91C_PIO_PB15 ( 1 << 15 ) /* Pin Controlled by PB15 */ +#define AT91C_PB15_ERXDV ( AT91C_PIO_PB15 ) /* Ethernet MAC Receive Data Valid */ +#define AT91C_PIO_PB16 ( 1 << 16 ) /* Pin Controlled by PB16 */ +#define AT91C_PB16_ECOL ( AT91C_PIO_PB16 ) /* Ethernet MAC Collision Detected */ +#define AT91C_PB16_NPCS13 ( AT91C_PIO_PB16 ) /* SPI 1 Peripheral Chip Select 3 */ +#define AT91C_PIO_PB17 ( 1 << 17 ) /* Pin Controlled by PB17 */ +#define AT91C_PB17_ERXCK ( AT91C_PIO_PB17 ) /* Ethernet MAC Receive Clock */ +#define AT91C_PB17_NPCS03 ( AT91C_PIO_PB17 ) /* SPI 0 Peripheral Chip Select 3 */ +#define AT91C_PIO_PB18 ( 1 << 18 ) /* Pin Controlled by PB18 */ +#define AT91C_PB18_EF100 ( AT91C_PIO_PB18 ) /* Ethernet MAC Force 100 Mbits/sec */ +#define AT91C_PB18_ADTRG ( AT91C_PIO_PB18 ) /* ADC External Trigger */ +#define AT91C_PIO_PB19 ( 1 << 19 ) /* Pin Controlled by PB19 */ +#define AT91C_PB19_PWM0 ( AT91C_PIO_PB19 ) /* PWM Channel 0 */ +#define AT91C_PB19_TCLK1 ( AT91C_PIO_PB19 ) /* Timer Counter 1 external clock input */ +#define AT91C_PIO_PB2 ( 1 << 2 ) /* Pin Controlled by PB2 */ +#define AT91C_PB2_ETX0 ( AT91C_PIO_PB2 ) /* Ethernet MAC Transmit Data 0 */ +#define AT91C_PIO_PB20 ( 1 << 20 ) /* Pin Controlled by PB20 */ +#define AT91C_PB20_PWM1 ( AT91C_PIO_PB20 ) /* PWM Channel 1 */ +#define AT91C_PB20_PCK0 ( AT91C_PIO_PB20 ) /* PMC Programmable Clock Output 0 */ +#define AT91C_PIO_PB21 ( 1 << 21 ) /* Pin Controlled by PB21 */ +#define AT91C_PB21_PWM2 ( AT91C_PIO_PB21 ) /* PWM Channel 2 */ +#define AT91C_PB21_PCK1 ( AT91C_PIO_PB21 ) /* PMC Programmable Clock Output 1 */ +#define AT91C_PIO_PB22 ( 1 << 22 ) /* Pin Controlled by PB22 */ +#define AT91C_PB22_PWM3 ( AT91C_PIO_PB22 ) /* PWM Channel 3 */ +#define AT91C_PB22_PCK2 ( AT91C_PIO_PB22 ) /* PMC Programmable Clock Output 2 */ +#define AT91C_PIO_PB23 ( 1 << 23 ) /* Pin Controlled by PB23 */ +#define AT91C_PB23_TIOA0 ( AT91C_PIO_PB23 ) /* Timer Counter 0 Multipurpose Timer I/O Pin A */ +#define AT91C_PB23_DCD1 ( AT91C_PIO_PB23 ) /* USART 1 Data Carrier Detect */ +#define AT91C_PIO_PB24 ( 1 << 24 ) /* Pin Controlled by PB24 */ +#define AT91C_PB24_TIOB0 ( AT91C_PIO_PB24 ) /* Timer Counter 0 Multipurpose Timer I/O Pin B */ +#define AT91C_PB24_DSR1 ( AT91C_PIO_PB24 ) /* USART 1 Data Set ready */ +#define AT91C_PIO_PB25 ( 1 << 25 ) /* Pin Controlled by PB25 */ +#define AT91C_PB25_TIOA1 ( AT91C_PIO_PB25 ) /* Timer Counter 1 Multipurpose Timer I/O Pin A */ +#define AT91C_PB25_DTR1 ( AT91C_PIO_PB25 ) /* USART 1 Data Terminal ready */ +#define AT91C_PIO_PB26 ( 1 << 26 ) /* Pin Controlled by PB26 */ +#define AT91C_PB26_TIOB1 ( AT91C_PIO_PB26 ) /* Timer Counter 1 Multipurpose Timer I/O Pin B */ +#define AT91C_PB26_RI1 ( AT91C_PIO_PB26 ) /* USART 1 Ring Indicator */ +#define AT91C_PIO_PB27 ( 1 << 27 ) /* Pin Controlled by PB27 */ +#define AT91C_PB27_TIOA2 ( AT91C_PIO_PB27 ) /* Timer Counter 2 Multipurpose Timer I/O Pin A */ +#define AT91C_PB27_PWM0 ( AT91C_PIO_PB27 ) /* PWM Channel 0 */ +#define AT91C_PIO_PB28 ( 1 << 28 ) /* Pin Controlled by PB28 */ +#define AT91C_PB28_TIOB2 ( AT91C_PIO_PB28 ) /* Timer Counter 2 Multipurpose Timer I/O Pin B */ +#define AT91C_PB28_PWM1 ( AT91C_PIO_PB28 ) /* PWM Channel 1 */ +#define AT91C_PIO_PB29 ( 1 << 29 ) /* Pin Controlled by PB29 */ +#define AT91C_PB29_PCK1 ( AT91C_PIO_PB29 ) /* PMC Programmable Clock Output 1 */ +#define AT91C_PB29_PWM2 ( AT91C_PIO_PB29 ) /* PWM Channel 2 */ +#define AT91C_PIO_PB3 ( 1 << 3 ) /* Pin Controlled by PB3 */ +#define AT91C_PB3_ETX1 ( AT91C_PIO_PB3 ) /* Ethernet MAC Transmit Data 1 */ +#define AT91C_PIO_PB30 ( 1 << 30 ) /* Pin Controlled by PB30 */ +#define AT91C_PB30_PCK2 ( AT91C_PIO_PB30 ) /* PMC Programmable Clock Output 2 */ +#define AT91C_PB30_PWM3 ( AT91C_PIO_PB30 ) /* PWM Channel 3 */ +#define AT91C_PIO_PB4 ( 1 << 4 ) /* Pin Controlled by PB4 */ +#define AT91C_PB4_ECRS_ECRSDV ( AT91C_PIO_PB4 ) /* Ethernet MAC Carrier Sense/Carrier Sense and Data Valid */ +#define AT91C_PIO_PB5 ( 1 << 5 ) /* Pin Controlled by PB5 */ +#define AT91C_PB5_ERX0 ( AT91C_PIO_PB5 ) /* Ethernet MAC Receive Data 0 */ +#define AT91C_PIO_PB6 ( 1 << 6 ) /* Pin Controlled by PB6 */ +#define AT91C_PB6_ERX1 ( AT91C_PIO_PB6 ) /* Ethernet MAC Receive Data 1 */ +#define AT91C_PIO_PB7 ( 1 << 7 ) /* Pin Controlled by PB7 */ +#define AT91C_PB7_ERXER ( AT91C_PIO_PB7 ) /* Ethernet MAC Receive Error */ +#define AT91C_PIO_PB8 ( 1 << 8 ) /* Pin Controlled by PB8 */ +#define AT91C_PB8_EMDC ( AT91C_PIO_PB8 ) /* Ethernet MAC Management Data Clock */ +#define AT91C_PIO_PB9 ( 1 << 9 ) /* Pin Controlled by PB9 */ +#define AT91C_PB9_EMDIO ( AT91C_PIO_PB9 ) /* Ethernet MAC Management Data Input/Output */ -// ***************************************************************************** -// PERIPHERAL ID DEFINITIONS FOR AT91SAM7X128 -// ***************************************************************************** -#define AT91C_ID_FIQ ( 0) // Advanced Interrupt Controller (FIQ) -#define AT91C_ID_SYS ( 1) // System Peripheral -#define AT91C_ID_PIOA ( 2) // Parallel IO Controller A -#define AT91C_ID_PIOB ( 3) // Parallel IO Controller B -#define AT91C_ID_SPI0 ( 4) // Serial Peripheral Interface 0 -#define AT91C_ID_SPI1 ( 5) // Serial Peripheral Interface 1 -#define AT91C_ID_US0 ( 6) // USART 0 -#define AT91C_ID_US1 ( 7) // USART 1 -#define AT91C_ID_SSC ( 8) // Serial Synchronous Controller -#define AT91C_ID_TWI ( 9) // Two-Wire Interface -#define AT91C_ID_PWMC (10) // PWM Controller -#define AT91C_ID_UDP (11) // USB Device Port -#define AT91C_ID_TC0 (12) // Timer Counter 0 -#define AT91C_ID_TC1 (13) // Timer Counter 1 -#define AT91C_ID_TC2 (14) // Timer Counter 2 -#define AT91C_ID_CAN (15) // Control Area Network Controller -#define AT91C_ID_EMAC (16) // Ethernet MAC -#define AT91C_ID_ADC (17) // Analog-to-Digital Converter -#define AT91C_ID_AES (18) // Advanced Encryption Standard 128-bit -#define AT91C_ID_TDES (19) // Triple Data Encryption Standard -#define AT91C_ID_20_Reserved (20) // Reserved -#define AT91C_ID_21_Reserved (21) // Reserved -#define AT91C_ID_22_Reserved (22) // Reserved -#define AT91C_ID_23_Reserved (23) // Reserved -#define AT91C_ID_24_Reserved (24) // Reserved -#define AT91C_ID_25_Reserved (25) // Reserved -#define AT91C_ID_26_Reserved (26) // Reserved -#define AT91C_ID_27_Reserved (27) // Reserved -#define AT91C_ID_28_Reserved (28) // Reserved -#define AT91C_ID_29_Reserved (29) // Reserved -#define AT91C_ID_IRQ0 (30) // Advanced Interrupt Controller (IRQ0) -#define AT91C_ID_IRQ1 (31) // Advanced Interrupt Controller (IRQ1) +/* ***************************************************************************** */ +/* PERIPHERAL ID DEFINITIONS FOR AT91SAM7X128 */ +/* ***************************************************************************** */ +#define AT91C_ID_FIQ ( 0 ) /* Advanced Interrupt Controller (FIQ) */ +#define AT91C_ID_SYS ( 1 ) /* System Peripheral */ +#define AT91C_ID_PIOA ( 2 ) /* Parallel IO Controller A */ +#define AT91C_ID_PIOB ( 3 ) /* Parallel IO Controller B */ +#define AT91C_ID_SPI0 ( 4 ) /* Serial Peripheral Interface 0 */ +#define AT91C_ID_SPI1 ( 5 ) /* Serial Peripheral Interface 1 */ +#define AT91C_ID_US0 ( 6 ) /* USART 0 */ +#define AT91C_ID_US1 ( 7 ) /* USART 1 */ +#define AT91C_ID_SSC ( 8 ) /* Serial Synchronous Controller */ +#define AT91C_ID_TWI ( 9 ) /* Two-Wire Interface */ +#define AT91C_ID_PWMC ( 10 ) /* PWM Controller */ +#define AT91C_ID_UDP ( 11 ) /* USB Device Port */ +#define AT91C_ID_TC0 ( 12 ) /* Timer Counter 0 */ +#define AT91C_ID_TC1 ( 13 ) /* Timer Counter 1 */ +#define AT91C_ID_TC2 ( 14 ) /* Timer Counter 2 */ +#define AT91C_ID_CAN ( 15 ) /* Control Area Network Controller */ +#define AT91C_ID_EMAC ( 16 ) /* Ethernet MAC */ +#define AT91C_ID_ADC ( 17 ) /* Analog-to-Digital Converter */ +#define AT91C_ID_AES ( 18 ) /* Advanced Encryption Standard 128-bit */ +#define AT91C_ID_TDES ( 19 ) /* Triple Data Encryption Standard */ +#define AT91C_ID_20_Reserved ( 20 ) /* Reserved */ +#define AT91C_ID_21_Reserved ( 21 ) /* Reserved */ +#define AT91C_ID_22_Reserved ( 22 ) /* Reserved */ +#define AT91C_ID_23_Reserved ( 23 ) /* Reserved */ +#define AT91C_ID_24_Reserved ( 24 ) /* Reserved */ +#define AT91C_ID_25_Reserved ( 25 ) /* Reserved */ +#define AT91C_ID_26_Reserved ( 26 ) /* Reserved */ +#define AT91C_ID_27_Reserved ( 27 ) /* Reserved */ +#define AT91C_ID_28_Reserved ( 28 ) /* Reserved */ +#define AT91C_ID_29_Reserved ( 29 ) /* Reserved */ +#define AT91C_ID_IRQ0 ( 30 ) /* Advanced Interrupt Controller (IRQ0) */ +#define AT91C_ID_IRQ1 ( 31 ) /* Advanced Interrupt Controller (IRQ1) */ -// ***************************************************************************** -// BASE ADDRESS DEFINITIONS FOR AT91SAM7X128 -// ***************************************************************************** -#define AT91C_BASE_SYS (0xFFFFF000) // (SYS) Base Address -#define AT91C_BASE_AIC (0xFFFFF000) // (AIC) Base Address -#define AT91C_BASE_PDC_DBGU (0xFFFFF300) // (PDC_DBGU) Base Address -#define AT91C_BASE_DBGU (0xFFFFF200) // (DBGU) Base Address -#define AT91C_BASE_PIOA (0xFFFFF400) // (PIOA) Base Address -#define AT91C_BASE_PIOB (0xFFFFF600) // (PIOB) Base Address -#define AT91C_BASE_CKGR (0xFFFFFC20) // (CKGR) Base Address -#define AT91C_BASE_PMC (0xFFFFFC00) // (PMC) Base Address -#define AT91C_BASE_RSTC (0xFFFFFD00) // (RSTC) Base Address -#define AT91C_BASE_RTTC (0xFFFFFD20) // (RTTC) Base Address -#define AT91C_BASE_PITC (0xFFFFFD30) // (PITC) Base Address -#define AT91C_BASE_WDTC (0xFFFFFD40) // (WDTC) Base Address -#define AT91C_BASE_VREG (0xFFFFFD60) // (VREG) Base Address -#define AT91C_BASE_MC (0xFFFFFF00) // (MC) Base Address -#define AT91C_BASE_PDC_SPI1 (0xFFFE4100) // (PDC_SPI1) Base Address -#define AT91C_BASE_SPI1 (0xFFFE4000) // (SPI1) Base Address -#define AT91C_BASE_PDC_SPI0 (0xFFFE0100) // (PDC_SPI0) Base Address -#define AT91C_BASE_SPI0 (0xFFFE0000) // (SPI0) Base Address -#define AT91C_BASE_PDC_US1 (0xFFFC4100) // (PDC_US1) Base Address -#define AT91C_BASE_US1 (0xFFFC4000) // (US1) Base Address -#define AT91C_BASE_PDC_US0 (0xFFFC0100) // (PDC_US0) Base Address -#define AT91C_BASE_US0 (0xFFFC0000) // (US0) Base Address -#define AT91C_BASE_PDC_SSC (0xFFFD4100) // (PDC_SSC) Base Address -#define AT91C_BASE_SSC (0xFFFD4000) // (SSC) Base Address -#define AT91C_BASE_TWI (0xFFFB8000) // (TWI) Base Address -#define AT91C_BASE_PWMC_CH3 (0xFFFCC260) // (PWMC_CH3) Base Address -#define AT91C_BASE_PWMC_CH2 (0xFFFCC240) // (PWMC_CH2) Base Address -#define AT91C_BASE_PWMC_CH1 (0xFFFCC220) // (PWMC_CH1) Base Address -#define AT91C_BASE_PWMC_CH0 (0xFFFCC200) // (PWMC_CH0) Base Address -#define AT91C_BASE_PWMC (0xFFFCC000) // (PWMC) Base Address -#define AT91C_BASE_UDP (0xFFFB0000) // (UDP) Base Address -#define AT91C_BASE_TC0 (0xFFFA0000) // (TC0) Base Address -#define AT91C_BASE_TC1 (0xFFFA0040) // (TC1) Base Address -#define AT91C_BASE_TC2 (0xFFFA0080) // (TC2) Base Address -#define AT91C_BASE_TCB (0xFFFA0000) // (TCB) Base Address -#define AT91C_BASE_CAN_MB0 (0xFFFD0200) // (CAN_MB0) Base Address -#define AT91C_BASE_CAN_MB1 (0xFFFD0220) // (CAN_MB1) Base Address -#define AT91C_BASE_CAN_MB2 (0xFFFD0240) // (CAN_MB2) Base Address -#define AT91C_BASE_CAN_MB3 (0xFFFD0260) // (CAN_MB3) Base Address -#define AT91C_BASE_CAN_MB4 (0xFFFD0280) // (CAN_MB4) Base Address -#define AT91C_BASE_CAN_MB5 (0xFFFD02A0) // (CAN_MB5) Base Address -#define AT91C_BASE_CAN_MB6 (0xFFFD02C0) // (CAN_MB6) Base Address -#define AT91C_BASE_CAN_MB7 (0xFFFD02E0) // (CAN_MB7) Base Address -#define AT91C_BASE_CAN (0xFFFD0000) // (CAN) Base Address -#define AT91C_BASE_EMAC (0xFFFDC000) // (EMAC) Base Address -#define AT91C_BASE_PDC_ADC (0xFFFD8100) // (PDC_ADC) Base Address -#define AT91C_BASE_ADC (0xFFFD8000) // (ADC) Base Address -#define AT91C_BASE_PDC_AES (0xFFFA4100) // (PDC_AES) Base Address -#define AT91C_BASE_AES (0xFFFA4000) // (AES) Base Address -#define AT91C_BASE_PDC_TDES (0xFFFA8100) // (PDC_TDES) Base Address -#define AT91C_BASE_TDES (0xFFFA8000) // (TDES) Base Address +/* ***************************************************************************** */ +/* BASE ADDRESS DEFINITIONS FOR AT91SAM7X128 */ +/* ***************************************************************************** */ +#define AT91C_BASE_SYS ( 0xFFFFF000 ) /* (SYS) Base Address */ +#define AT91C_BASE_AIC ( 0xFFFFF000 ) /* (AIC) Base Address */ +#define AT91C_BASE_PDC_DBGU ( 0xFFFFF300 ) /* (PDC_DBGU) Base Address */ +#define AT91C_BASE_DBGU ( 0xFFFFF200 ) /* (DBGU) Base Address */ +#define AT91C_BASE_PIOA ( 0xFFFFF400 ) /* (PIOA) Base Address */ +#define AT91C_BASE_PIOB ( 0xFFFFF600 ) /* (PIOB) Base Address */ +#define AT91C_BASE_CKGR ( 0xFFFFFC20 ) /* (CKGR) Base Address */ +#define AT91C_BASE_PMC ( 0xFFFFFC00 ) /* (PMC) Base Address */ +#define AT91C_BASE_RSTC ( 0xFFFFFD00 ) /* (RSTC) Base Address */ +#define AT91C_BASE_RTTC ( 0xFFFFFD20 ) /* (RTTC) Base Address */ +#define AT91C_BASE_PITC ( 0xFFFFFD30 ) /* (PITC) Base Address */ +#define AT91C_BASE_WDTC ( 0xFFFFFD40 ) /* (WDTC) Base Address */ +#define AT91C_BASE_VREG ( 0xFFFFFD60 ) /* (VREG) Base Address */ +#define AT91C_BASE_MC ( 0xFFFFFF00 ) /* (MC) Base Address */ +#define AT91C_BASE_PDC_SPI1 ( 0xFFFE4100 ) /* (PDC_SPI1) Base Address */ +#define AT91C_BASE_SPI1 ( 0xFFFE4000 ) /* (SPI1) Base Address */ +#define AT91C_BASE_PDC_SPI0 ( 0xFFFE0100 ) /* (PDC_SPI0) Base Address */ +#define AT91C_BASE_SPI0 ( 0xFFFE0000 ) /* (SPI0) Base Address */ +#define AT91C_BASE_PDC_US1 ( 0xFFFC4100 ) /* (PDC_US1) Base Address */ +#define AT91C_BASE_US1 ( 0xFFFC4000 ) /* (US1) Base Address */ +#define AT91C_BASE_PDC_US0 ( 0xFFFC0100 ) /* (PDC_US0) Base Address */ +#define AT91C_BASE_US0 ( 0xFFFC0000 ) /* (US0) Base Address */ +#define AT91C_BASE_PDC_SSC ( 0xFFFD4100 ) /* (PDC_SSC) Base Address */ +#define AT91C_BASE_SSC ( 0xFFFD4000 ) /* (SSC) Base Address */ +#define AT91C_BASE_TWI ( 0xFFFB8000 ) /* (TWI) Base Address */ +#define AT91C_BASE_PWMC_CH3 ( 0xFFFCC260 ) /* (PWMC_CH3) Base Address */ +#define AT91C_BASE_PWMC_CH2 ( 0xFFFCC240 ) /* (PWMC_CH2) Base Address */ +#define AT91C_BASE_PWMC_CH1 ( 0xFFFCC220 ) /* (PWMC_CH1) Base Address */ +#define AT91C_BASE_PWMC_CH0 ( 0xFFFCC200 ) /* (PWMC_CH0) Base Address */ +#define AT91C_BASE_PWMC ( 0xFFFCC000 ) /* (PWMC) Base Address */ +#define AT91C_BASE_UDP ( 0xFFFB0000 ) /* (UDP) Base Address */ +#define AT91C_BASE_TC0 ( 0xFFFA0000 ) /* (TC0) Base Address */ +#define AT91C_BASE_TC1 ( 0xFFFA0040 ) /* (TC1) Base Address */ +#define AT91C_BASE_TC2 ( 0xFFFA0080 ) /* (TC2) Base Address */ +#define AT91C_BASE_TCB ( 0xFFFA0000 ) /* (TCB) Base Address */ +#define AT91C_BASE_CAN_MB0 ( 0xFFFD0200 ) /* (CAN_MB0) Base Address */ +#define AT91C_BASE_CAN_MB1 ( 0xFFFD0220 ) /* (CAN_MB1) Base Address */ +#define AT91C_BASE_CAN_MB2 ( 0xFFFD0240 ) /* (CAN_MB2) Base Address */ +#define AT91C_BASE_CAN_MB3 ( 0xFFFD0260 ) /* (CAN_MB3) Base Address */ +#define AT91C_BASE_CAN_MB4 ( 0xFFFD0280 ) /* (CAN_MB4) Base Address */ +#define AT91C_BASE_CAN_MB5 ( 0xFFFD02A0 ) /* (CAN_MB5) Base Address */ +#define AT91C_BASE_CAN_MB6 ( 0xFFFD02C0 ) /* (CAN_MB6) Base Address */ +#define AT91C_BASE_CAN_MB7 ( 0xFFFD02E0 ) /* (CAN_MB7) Base Address */ +#define AT91C_BASE_CAN ( 0xFFFD0000 ) /* (CAN) Base Address */ +#define AT91C_BASE_EMAC ( 0xFFFDC000 ) /* (EMAC) Base Address */ +#define AT91C_BASE_PDC_ADC ( 0xFFFD8100 ) /* (PDC_ADC) Base Address */ +#define AT91C_BASE_ADC ( 0xFFFD8000 ) /* (ADC) Base Address */ +#define AT91C_BASE_PDC_AES ( 0xFFFA4100 ) /* (PDC_AES) Base Address */ +#define AT91C_BASE_AES ( 0xFFFA4000 ) /* (AES) Base Address */ +#define AT91C_BASE_PDC_TDES ( 0xFFFA8100 ) /* (PDC_TDES) Base Address */ +#define AT91C_BASE_TDES ( 0xFFFA8000 ) /* (TDES) Base Address */ -// ***************************************************************************** -// MEMORY MAPPING DEFINITIONS FOR AT91SAM7X128 -// ***************************************************************************** -#define AT91C_ISRAM (0x00200000) // Internal SRAM base address -#define AT91C_ISRAM_SIZE (0x00008000) // Internal SRAM size in byte (32 Kbyte) -#define AT91C_IFLASH (0x00100000) // Internal ROM base address -#define AT91C_IFLASH_SIZE (0x00020000) // Internal ROM size in byte (128 Kbyte) +/* ***************************************************************************** */ +/* MEMORY MAPPING DEFINITIONS FOR AT91SAM7X128 */ +/* ***************************************************************************** */ +#define AT91C_ISRAM ( 0x00200000 ) /* Internal SRAM base address */ +#define AT91C_ISRAM_SIZE ( 0x00008000 ) /* Internal SRAM size in byte (32 Kbyte) */ +#define AT91C_IFLASH ( 0x00100000 ) /* Internal ROM base address */ +#define AT91C_IFLASH_SIZE ( 0x00020000 ) /* Internal ROM size in byte (128 Kbyte) */ diff --git a/Source/portable/IAR/AtmelSAM7S64/AT91SAM7X256.h b/Source/portable/IAR/AtmelSAM7S64/AT91SAM7X256.h index cf952e3c2..98e1babc2 100644 --- a/Source/portable/IAR/AtmelSAM7S64/AT91SAM7X256.h +++ b/Source/portable/IAR/AtmelSAM7S64/AT91SAM7X256.h @@ -1,2715 +1,2743 @@ -// ---------------------------------------------------------------------------- -// ATMEL Microcontroller Software Support - ROUSSET - -// ---------------------------------------------------------------------------- -// DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR -// IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF -// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE -// DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, -// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, -// OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF -// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING -// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, -// EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// ---------------------------------------------------------------------------- -// File Name : AT91SAM7X256.h -// Object : AT91SAM7X256 definitions -// Generated : AT91 SW Application Group 05/20/2005 (16:22:29) -// -// CVS Reference : /AT91SAM7X256.pl/1.11/Tue May 10 12:15:32 2005// -// CVS Reference : /SYS_SAM7X.pl/1.3/Tue Feb 1 17:01:43 2005// -// CVS Reference : /MC_SAM7X.pl/1.2/Fri May 20 14:13:04 2005// -// CVS Reference : /PMC_SAM7X.pl/1.4/Tue Feb 8 13:58:10 2005// -// CVS Reference : /RSTC_SAM7X.pl/1.1/Tue Feb 1 16:16:26 2005// -// CVS Reference : /UDP_SAM7X.pl/1.1/Tue May 10 11:35:35 2005// -// CVS Reference : /PWM_SAM7X.pl/1.1/Tue May 10 11:53:07 2005// -// CVS Reference : /AIC_6075B.pl/1.3/Fri May 20 14:01:30 2005// -// CVS Reference : /PIO_6057A.pl/1.2/Thu Feb 3 10:18:28 2005// -// CVS Reference : /RTTC_6081A.pl/1.2/Tue Nov 9 14:43:58 2004// -// CVS Reference : /PITC_6079A.pl/1.2/Tue Nov 9 14:43:56 2004// -// CVS Reference : /WDTC_6080A.pl/1.3/Tue Nov 9 14:44:00 2004// -// CVS Reference : /VREG_6085B.pl/1.1/Tue Feb 1 16:05:48 2005// -// CVS Reference : /PDC_6074C.pl/1.2/Thu Feb 3 08:48:54 2005// -// CVS Reference : /DBGU_6059D.pl/1.1/Mon Jan 31 13:15:32 2005// -// CVS Reference : /SPI_6088D.pl/1.3/Fri May 20 14:08:59 2005// -// CVS Reference : /US_6089C.pl/1.1/Mon Jul 12 18:23:26 2004// -// CVS Reference : /SSC_6078A.pl/1.1/Tue Jul 13 07:45:40 2004// -// CVS Reference : /TWI_6061A.pl/1.1/Tue Jul 13 07:38:06 2004// -// CVS Reference : /TC_6082A.pl/1.7/Fri Mar 11 12:52:17 2005// -// CVS Reference : /CAN_6019B.pl/1.1/Tue Mar 8 12:42:22 2005// -// CVS Reference : /EMACB_6119A.pl/1.5/Thu Feb 3 15:52:04 2005// -// CVS Reference : /ADC_6051C.pl/1.1/Fri Oct 17 09:12:38 2003// -// CVS Reference : /AES_6149A.pl/1.10/Mon Feb 7 09:44:25 2005// -// CVS Reference : /DES3_6150A.pl/1.1/Mon Jan 17 08:34:31 2005// -// ---------------------------------------------------------------------------- +/* ---------------------------------------------------------------------------- */ +/* ATMEL Microcontroller Software Support - ROUSSET - */ +/* ---------------------------------------------------------------------------- */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ +/* File Name : AT91SAM7X256.h */ +/* Object : AT91SAM7X256 definitions */ +/* Generated : AT91 SW Application Group 05/20/2005 (16:22:29) */ +/* */ +/* CVS Reference : /AT91SAM7X256.pl/1.11/Tue May 10 12:15:32 2005// */ +/* CVS Reference : /SYS_SAM7X.pl/1.3/Tue Feb 1 17:01:43 2005// */ +/* CVS Reference : /MC_SAM7X.pl/1.2/Fri May 20 14:13:04 2005// */ +/* CVS Reference : /PMC_SAM7X.pl/1.4/Tue Feb 8 13:58:10 2005// */ +/* CVS Reference : /RSTC_SAM7X.pl/1.1/Tue Feb 1 16:16:26 2005// */ +/* CVS Reference : /UDP_SAM7X.pl/1.1/Tue May 10 11:35:35 2005// */ +/* CVS Reference : /PWM_SAM7X.pl/1.1/Tue May 10 11:53:07 2005// */ +/* CVS Reference : /AIC_6075B.pl/1.3/Fri May 20 14:01:30 2005// */ +/* CVS Reference : /PIO_6057A.pl/1.2/Thu Feb 3 10:18:28 2005// */ +/* CVS Reference : /RTTC_6081A.pl/1.2/Tue Nov 9 14:43:58 2004// */ +/* CVS Reference : /PITC_6079A.pl/1.2/Tue Nov 9 14:43:56 2004// */ +/* CVS Reference : /WDTC_6080A.pl/1.3/Tue Nov 9 14:44:00 2004// */ +/* CVS Reference : /VREG_6085B.pl/1.1/Tue Feb 1 16:05:48 2005// */ +/* CVS Reference : /PDC_6074C.pl/1.2/Thu Feb 3 08:48:54 2005// */ +/* CVS Reference : /DBGU_6059D.pl/1.1/Mon Jan 31 13:15:32 2005// */ +/* CVS Reference : /SPI_6088D.pl/1.3/Fri May 20 14:08:59 2005// */ +/* CVS Reference : /US_6089C.pl/1.1/Mon Jul 12 18:23:26 2004// */ +/* CVS Reference : /SSC_6078A.pl/1.1/Tue Jul 13 07:45:40 2004// */ +/* CVS Reference : /TWI_6061A.pl/1.1/Tue Jul 13 07:38:06 2004// */ +/* CVS Reference : /TC_6082A.pl/1.7/Fri Mar 11 12:52:17 2005// */ +/* CVS Reference : /CAN_6019B.pl/1.1/Tue Mar 8 12:42:22 2005// */ +/* CVS Reference : /EMACB_6119A.pl/1.5/Thu Feb 3 15:52:04 2005// */ +/* CVS Reference : /ADC_6051C.pl/1.1/Fri Oct 17 09:12:38 2003// */ +/* CVS Reference : /AES_6149A.pl/1.10/Mon Feb 7 09:44:25 2005// */ +/* CVS Reference : /DES3_6150A.pl/1.1/Mon Jan 17 08:34:31 2005// */ +/* ---------------------------------------------------------------------------- */ #ifndef AT91SAM7X256_H #define AT91SAM7X256_H -typedef volatile unsigned int AT91_REG;// Hardware register definition - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR System Peripherals -// ***************************************************************************** -typedef struct _AT91S_SYS { - AT91_REG AIC_SMR[32]; // Source Mode Register - AT91_REG AIC_SVR[32]; // Source Vector Register - AT91_REG AIC_IVR; // IRQ Vector Register - AT91_REG AIC_FVR; // FIQ Vector Register - AT91_REG AIC_ISR; // Interrupt Status Register - AT91_REG AIC_IPR; // Interrupt Pending Register - AT91_REG AIC_IMR; // Interrupt Mask Register - AT91_REG AIC_CISR; // Core Interrupt Status Register - AT91_REG Reserved0[2]; // - AT91_REG AIC_IECR; // Interrupt Enable Command Register - AT91_REG AIC_IDCR; // Interrupt Disable Command Register - AT91_REG AIC_ICCR; // Interrupt Clear Command Register - AT91_REG AIC_ISCR; // Interrupt Set Command Register - AT91_REG AIC_EOICR; // End of Interrupt Command Register - AT91_REG AIC_SPU; // Spurious Vector Register - AT91_REG AIC_DCR; // Debug Control Register (Protect) - AT91_REG Reserved1[1]; // - AT91_REG AIC_FFER; // Fast Forcing Enable Register - AT91_REG AIC_FFDR; // Fast Forcing Disable Register - AT91_REG AIC_FFSR; // Fast Forcing Status Register - AT91_REG Reserved2[45]; // - AT91_REG DBGU_CR; // Control Register - AT91_REG DBGU_MR; // Mode Register - AT91_REG DBGU_IER; // Interrupt Enable Register - AT91_REG DBGU_IDR; // Interrupt Disable Register - AT91_REG DBGU_IMR; // Interrupt Mask Register - AT91_REG DBGU_CSR; // Channel Status Register - AT91_REG DBGU_RHR; // Receiver Holding Register - AT91_REG DBGU_THR; // Transmitter Holding Register - AT91_REG DBGU_BRGR; // Baud Rate Generator Register - AT91_REG Reserved3[7]; // - AT91_REG DBGU_CIDR; // Chip ID Register - AT91_REG DBGU_EXID; // Chip ID Extension Register - AT91_REG DBGU_FNTR; // Force NTRST Register - AT91_REG Reserved4[45]; // - AT91_REG DBGU_RPR; // Receive Pointer Register - AT91_REG DBGU_RCR; // Receive Counter Register - AT91_REG DBGU_TPR; // Transmit Pointer Register - AT91_REG DBGU_TCR; // Transmit Counter Register - AT91_REG DBGU_RNPR; // Receive Next Pointer Register - AT91_REG DBGU_RNCR; // Receive Next Counter Register - AT91_REG DBGU_TNPR; // Transmit Next Pointer Register - AT91_REG DBGU_TNCR; // Transmit Next Counter Register - AT91_REG DBGU_PTCR; // PDC Transfer Control Register - AT91_REG DBGU_PTSR; // PDC Transfer Status Register - AT91_REG Reserved5[54]; // - AT91_REG PIOA_PER; // PIO Enable Register - AT91_REG PIOA_PDR; // PIO Disable Register - AT91_REG PIOA_PSR; // PIO Status Register - AT91_REG Reserved6[1]; // - AT91_REG PIOA_OER; // Output Enable Register - AT91_REG PIOA_ODR; // Output Disable Registerr - AT91_REG PIOA_OSR; // Output Status Register - AT91_REG Reserved7[1]; // - AT91_REG PIOA_IFER; // Input Filter Enable Register - AT91_REG PIOA_IFDR; // Input Filter Disable Register - AT91_REG PIOA_IFSR; // Input Filter Status Register - AT91_REG Reserved8[1]; // - AT91_REG PIOA_SODR; // Set Output Data Register - AT91_REG PIOA_CODR; // Clear Output Data Register - AT91_REG PIOA_ODSR; // Output Data Status Register - AT91_REG PIOA_PDSR; // Pin Data Status Register - AT91_REG PIOA_IER; // Interrupt Enable Register - AT91_REG PIOA_IDR; // Interrupt Disable Register - AT91_REG PIOA_IMR; // Interrupt Mask Register - AT91_REG PIOA_ISR; // Interrupt Status Register - AT91_REG PIOA_MDER; // Multi-driver Enable Register - AT91_REG PIOA_MDDR; // Multi-driver Disable Register - AT91_REG PIOA_MDSR; // Multi-driver Status Register - AT91_REG Reserved9[1]; // - AT91_REG PIOA_PPUDR; // Pull-up Disable Register - AT91_REG PIOA_PPUER; // Pull-up Enable Register - AT91_REG PIOA_PPUSR; // Pull-up Status Register - AT91_REG Reserved10[1]; // - AT91_REG PIOA_ASR; // Select A Register - AT91_REG PIOA_BSR; // Select B Register - AT91_REG PIOA_ABSR; // AB Select Status Register - AT91_REG Reserved11[9]; // - AT91_REG PIOA_OWER; // Output Write Enable Register - AT91_REG PIOA_OWDR; // Output Write Disable Register - AT91_REG PIOA_OWSR; // Output Write Status Register - AT91_REG Reserved12[85]; // - AT91_REG PIOB_PER; // PIO Enable Register - AT91_REG PIOB_PDR; // PIO Disable Register - AT91_REG PIOB_PSR; // PIO Status Register - AT91_REG Reserved13[1]; // - AT91_REG PIOB_OER; // Output Enable Register - AT91_REG PIOB_ODR; // Output Disable Registerr - AT91_REG PIOB_OSR; // Output Status Register - AT91_REG Reserved14[1]; // - AT91_REG PIOB_IFER; // Input Filter Enable Register - AT91_REG PIOB_IFDR; // Input Filter Disable Register - AT91_REG PIOB_IFSR; // Input Filter Status Register - AT91_REG Reserved15[1]; // - AT91_REG PIOB_SODR; // Set Output Data Register - AT91_REG PIOB_CODR; // Clear Output Data Register - AT91_REG PIOB_ODSR; // Output Data Status Register - AT91_REG PIOB_PDSR; // Pin Data Status Register - AT91_REG PIOB_IER; // Interrupt Enable Register - AT91_REG PIOB_IDR; // Interrupt Disable Register - AT91_REG PIOB_IMR; // Interrupt Mask Register - AT91_REG PIOB_ISR; // Interrupt Status Register - AT91_REG PIOB_MDER; // Multi-driver Enable Register - AT91_REG PIOB_MDDR; // Multi-driver Disable Register - AT91_REG PIOB_MDSR; // Multi-driver Status Register - AT91_REG Reserved16[1]; // - AT91_REG PIOB_PPUDR; // Pull-up Disable Register - AT91_REG PIOB_PPUER; // Pull-up Enable Register - AT91_REG PIOB_PPUSR; // Pull-up Status Register - AT91_REG Reserved17[1]; // - AT91_REG PIOB_ASR; // Select A Register - AT91_REG PIOB_BSR; // Select B Register - AT91_REG PIOB_ABSR; // AB Select Status Register - AT91_REG Reserved18[9]; // - AT91_REG PIOB_OWER; // Output Write Enable Register - AT91_REG PIOB_OWDR; // Output Write Disable Register - AT91_REG PIOB_OWSR; // Output Write Status Register - AT91_REG Reserved19[341]; // - AT91_REG PMC_SCER; // System Clock Enable Register - AT91_REG PMC_SCDR; // System Clock Disable Register - AT91_REG PMC_SCSR; // System Clock Status Register - AT91_REG Reserved20[1]; // - AT91_REG PMC_PCER; // Peripheral Clock Enable Register - AT91_REG PMC_PCDR; // Peripheral Clock Disable Register - AT91_REG PMC_PCSR; // Peripheral Clock Status Register - AT91_REG Reserved21[1]; // - AT91_REG PMC_MOR; // Main Oscillator Register - AT91_REG PMC_MCFR; // Main Clock Frequency Register - AT91_REG Reserved22[1]; // - AT91_REG PMC_PLLR; // PLL Register - AT91_REG PMC_MCKR; // Master Clock Register - AT91_REG Reserved23[3]; // - AT91_REG PMC_PCKR[4]; // Programmable Clock Register - AT91_REG Reserved24[4]; // - AT91_REG PMC_IER; // Interrupt Enable Register - AT91_REG PMC_IDR; // Interrupt Disable Register - AT91_REG PMC_SR; // Status Register - AT91_REG PMC_IMR; // Interrupt Mask Register - AT91_REG Reserved25[36]; // - AT91_REG RSTC_RCR; // Reset Control Register - AT91_REG RSTC_RSR; // Reset Status Register - AT91_REG RSTC_RMR; // Reset Mode Register - AT91_REG Reserved26[5]; // - AT91_REG RTTC_RTMR; // Real-time Mode Register - AT91_REG RTTC_RTAR; // Real-time Alarm Register - AT91_REG RTTC_RTVR; // Real-time Value Register - AT91_REG RTTC_RTSR; // Real-time Status Register - AT91_REG PITC_PIMR; // Period Interval Mode Register - AT91_REG PITC_PISR; // Period Interval Status Register - AT91_REG PITC_PIVR; // Period Interval Value Register - AT91_REG PITC_PIIR; // Period Interval Image Register - AT91_REG WDTC_WDCR; // Watchdog Control Register - AT91_REG WDTC_WDMR; // Watchdog Mode Register - AT91_REG WDTC_WDSR; // Watchdog Status Register - AT91_REG Reserved27[5]; // - AT91_REG VREG_MR; // Voltage Regulator Mode Register -} AT91S_SYS, *AT91PS_SYS; - - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Advanced Interrupt Controller -// ***************************************************************************** -typedef struct _AT91S_AIC { - AT91_REG AIC_SMR[32]; // Source Mode Register - AT91_REG AIC_SVR[32]; // Source Vector Register - AT91_REG AIC_IVR; // IRQ Vector Register - AT91_REG AIC_FVR; // FIQ Vector Register - AT91_REG AIC_ISR; // Interrupt Status Register - AT91_REG AIC_IPR; // Interrupt Pending Register - AT91_REG AIC_IMR; // Interrupt Mask Register - AT91_REG AIC_CISR; // Core Interrupt Status Register - AT91_REG Reserved0[2]; // - AT91_REG AIC_IECR; // Interrupt Enable Command Register - AT91_REG AIC_IDCR; // Interrupt Disable Command Register - AT91_REG AIC_ICCR; // Interrupt Clear Command Register - AT91_REG AIC_ISCR; // Interrupt Set Command Register - AT91_REG AIC_EOICR; // End of Interrupt Command Register - AT91_REG AIC_SPU; // Spurious Vector Register - AT91_REG AIC_DCR; // Debug Control Register (Protect) - AT91_REG Reserved1[1]; // - AT91_REG AIC_FFER; // Fast Forcing Enable Register - AT91_REG AIC_FFDR; // Fast Forcing Disable Register - AT91_REG AIC_FFSR; // Fast Forcing Status Register -} AT91S_AIC, *AT91PS_AIC; - -// -------- AIC_SMR : (AIC Offset: 0x0) Control Register -------- -#define AT91C_AIC_PRIOR ((unsigned int) 0x7 << 0) // (AIC) Priority Level -#define AT91C_AIC_PRIOR_LOWEST ((unsigned int) 0x0) // (AIC) Lowest priority level -#define AT91C_AIC_PRIOR_HIGHEST ((unsigned int) 0x7) // (AIC) Highest priority level -#define AT91C_AIC_SRCTYPE ((unsigned int) 0x3 << 5) // (AIC) Interrupt Source Type -#define AT91C_AIC_SRCTYPE_INT_HIGH_LEVEL ((unsigned int) 0x0 << 5) // (AIC) Internal Sources Code Label High-level Sensitive -#define AT91C_AIC_SRCTYPE_EXT_LOW_LEVEL ((unsigned int) 0x0 << 5) // (AIC) External Sources Code Label Low-level Sensitive -#define AT91C_AIC_SRCTYPE_INT_POSITIVE_EDGE ((unsigned int) 0x1 << 5) // (AIC) Internal Sources Code Label Positive Edge triggered -#define AT91C_AIC_SRCTYPE_EXT_NEGATIVE_EDGE ((unsigned int) 0x1 << 5) // (AIC) External Sources Code Label Negative Edge triggered -#define AT91C_AIC_SRCTYPE_HIGH_LEVEL ((unsigned int) 0x2 << 5) // (AIC) Internal Or External Sources Code Label High-level Sensitive -#define AT91C_AIC_SRCTYPE_POSITIVE_EDGE ((unsigned int) 0x3 << 5) // (AIC) Internal Or External Sources Code Label Positive Edge triggered -// -------- AIC_CISR : (AIC Offset: 0x114) AIC Core Interrupt Status Register -------- -#define AT91C_AIC_NFIQ ((unsigned int) 0x1 << 0) // (AIC) NFIQ Status -#define AT91C_AIC_NIRQ ((unsigned int) 0x1 << 1) // (AIC) NIRQ Status -// -------- AIC_DCR : (AIC Offset: 0x138) AIC Debug Control Register (Protect) -------- -#define AT91C_AIC_DCR_PROT ((unsigned int) 0x1 << 0) // (AIC) Protection Mode -#define AT91C_AIC_DCR_GMSK ((unsigned int) 0x1 << 1) // (AIC) General Mask - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Peripheral DMA Controller -// ***************************************************************************** -typedef struct _AT91S_PDC { - AT91_REG PDC_RPR; // Receive Pointer Register - AT91_REG PDC_RCR; // Receive Counter Register - AT91_REG PDC_TPR; // Transmit Pointer Register - AT91_REG PDC_TCR; // Transmit Counter Register - AT91_REG PDC_RNPR; // Receive Next Pointer Register - AT91_REG PDC_RNCR; // Receive Next Counter Register - AT91_REG PDC_TNPR; // Transmit Next Pointer Register - AT91_REG PDC_TNCR; // Transmit Next Counter Register - AT91_REG PDC_PTCR; // PDC Transfer Control Register - AT91_REG PDC_PTSR; // PDC Transfer Status Register -} AT91S_PDC, *AT91PS_PDC; - -// -------- PDC_PTCR : (PDC Offset: 0x20) PDC Transfer Control Register -------- -#define AT91C_PDC_RXTEN ((unsigned int) 0x1 << 0) // (PDC) Receiver Transfer Enable -#define AT91C_PDC_RXTDIS ((unsigned int) 0x1 << 1) // (PDC) Receiver Transfer Disable -#define AT91C_PDC_TXTEN ((unsigned int) 0x1 << 8) // (PDC) Transmitter Transfer Enable -#define AT91C_PDC_TXTDIS ((unsigned int) 0x1 << 9) // (PDC) Transmitter Transfer Disable -// -------- PDC_PTSR : (PDC Offset: 0x24) PDC Transfer Status Register -------- - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Debug Unit -// ***************************************************************************** -typedef struct _AT91S_DBGU { - AT91_REG DBGU_CR; // Control Register - AT91_REG DBGU_MR; // Mode Register - AT91_REG DBGU_IER; // Interrupt Enable Register - AT91_REG DBGU_IDR; // Interrupt Disable Register - AT91_REG DBGU_IMR; // Interrupt Mask Register - AT91_REG DBGU_CSR; // Channel Status Register - AT91_REG DBGU_RHR; // Receiver Holding Register - AT91_REG DBGU_THR; // Transmitter Holding Register - AT91_REG DBGU_BRGR; // Baud Rate Generator Register - AT91_REG Reserved0[7]; // - AT91_REG DBGU_CIDR; // Chip ID Register - AT91_REG DBGU_EXID; // Chip ID Extension Register - AT91_REG DBGU_FNTR; // Force NTRST Register - AT91_REG Reserved1[45]; // - AT91_REG DBGU_RPR; // Receive Pointer Register - AT91_REG DBGU_RCR; // Receive Counter Register - AT91_REG DBGU_TPR; // Transmit Pointer Register - AT91_REG DBGU_TCR; // Transmit Counter Register - AT91_REG DBGU_RNPR; // Receive Next Pointer Register - AT91_REG DBGU_RNCR; // Receive Next Counter Register - AT91_REG DBGU_TNPR; // Transmit Next Pointer Register - AT91_REG DBGU_TNCR; // Transmit Next Counter Register - AT91_REG DBGU_PTCR; // PDC Transfer Control Register - AT91_REG DBGU_PTSR; // PDC Transfer Status Register -} AT91S_DBGU, *AT91PS_DBGU; - -// -------- DBGU_CR : (DBGU Offset: 0x0) Debug Unit Control Register -------- -#define AT91C_US_RSTRX ((unsigned int) 0x1 << 2) // (DBGU) Reset Receiver -#define AT91C_US_RSTTX ((unsigned int) 0x1 << 3) // (DBGU) Reset Transmitter -#define AT91C_US_RXEN ((unsigned int) 0x1 << 4) // (DBGU) Receiver Enable -#define AT91C_US_RXDIS ((unsigned int) 0x1 << 5) // (DBGU) Receiver Disable -#define AT91C_US_TXEN ((unsigned int) 0x1 << 6) // (DBGU) Transmitter Enable -#define AT91C_US_TXDIS ((unsigned int) 0x1 << 7) // (DBGU) Transmitter Disable -#define AT91C_US_RSTSTA ((unsigned int) 0x1 << 8) // (DBGU) Reset Status Bits -// -------- DBGU_MR : (DBGU Offset: 0x4) Debug Unit Mode Register -------- -#define AT91C_US_PAR ((unsigned int) 0x7 << 9) // (DBGU) Parity type -#define AT91C_US_PAR_EVEN ((unsigned int) 0x0 << 9) // (DBGU) Even Parity -#define AT91C_US_PAR_ODD ((unsigned int) 0x1 << 9) // (DBGU) Odd Parity -#define AT91C_US_PAR_SPACE ((unsigned int) 0x2 << 9) // (DBGU) Parity forced to 0 (Space) -#define AT91C_US_PAR_MARK ((unsigned int) 0x3 << 9) // (DBGU) Parity forced to 1 (Mark) -#define AT91C_US_PAR_NONE ((unsigned int) 0x4 << 9) // (DBGU) No Parity -#define AT91C_US_PAR_MULTI_DROP ((unsigned int) 0x6 << 9) // (DBGU) Multi-drop mode -#define AT91C_US_CHMODE ((unsigned int) 0x3 << 14) // (DBGU) Channel Mode -#define AT91C_US_CHMODE_NORMAL ((unsigned int) 0x0 << 14) // (DBGU) Normal Mode: The USART channel operates as an RX/TX USART. -#define AT91C_US_CHMODE_AUTO ((unsigned int) 0x1 << 14) // (DBGU) Automatic Echo: Receiver Data Input is connected to the TXD pin. -#define AT91C_US_CHMODE_LOCAL ((unsigned int) 0x2 << 14) // (DBGU) Local Loopback: Transmitter Output Signal is connected to Receiver Input Signal. -#define AT91C_US_CHMODE_REMOTE ((unsigned int) 0x3 << 14) // (DBGU) Remote Loopback: RXD pin is internally connected to TXD pin. -// -------- DBGU_IER : (DBGU Offset: 0x8) Debug Unit Interrupt Enable Register -------- -#define AT91C_US_RXRDY ((unsigned int) 0x1 << 0) // (DBGU) RXRDY Interrupt -#define AT91C_US_TXRDY ((unsigned int) 0x1 << 1) // (DBGU) TXRDY Interrupt -#define AT91C_US_ENDRX ((unsigned int) 0x1 << 3) // (DBGU) End of Receive Transfer Interrupt -#define AT91C_US_ENDTX ((unsigned int) 0x1 << 4) // (DBGU) End of Transmit Interrupt -#define AT91C_US_OVRE ((unsigned int) 0x1 << 5) // (DBGU) Overrun Interrupt -#define AT91C_US_FRAME ((unsigned int) 0x1 << 6) // (DBGU) Framing Error Interrupt -#define AT91C_US_PARE ((unsigned int) 0x1 << 7) // (DBGU) Parity Error Interrupt -#define AT91C_US_TXEMPTY ((unsigned int) 0x1 << 9) // (DBGU) TXEMPTY Interrupt -#define AT91C_US_TXBUFE ((unsigned int) 0x1 << 11) // (DBGU) TXBUFE Interrupt -#define AT91C_US_RXBUFF ((unsigned int) 0x1 << 12) // (DBGU) RXBUFF Interrupt -#define AT91C_US_COMM_TX ((unsigned int) 0x1 << 30) // (DBGU) COMM_TX Interrupt -#define AT91C_US_COMM_RX ((unsigned int) 0x1 << 31) // (DBGU) COMM_RX Interrupt -// -------- DBGU_IDR : (DBGU Offset: 0xc) Debug Unit Interrupt Disable Register -------- -// -------- DBGU_IMR : (DBGU Offset: 0x10) Debug Unit Interrupt Mask Register -------- -// -------- DBGU_CSR : (DBGU Offset: 0x14) Debug Unit Channel Status Register -------- -// -------- DBGU_FNTR : (DBGU Offset: 0x48) Debug Unit FORCE_NTRST Register -------- -#define AT91C_US_FORCE_NTRST ((unsigned int) 0x1 << 0) // (DBGU) Force NTRST in JTAG - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Parallel Input Output Controler -// ***************************************************************************** -typedef struct _AT91S_PIO { - AT91_REG PIO_PER; // PIO Enable Register - AT91_REG PIO_PDR; // PIO Disable Register - AT91_REG PIO_PSR; // PIO Status Register - AT91_REG Reserved0[1]; // - AT91_REG PIO_OER; // Output Enable Register - AT91_REG PIO_ODR; // Output Disable Registerr - AT91_REG PIO_OSR; // Output Status Register - AT91_REG Reserved1[1]; // - AT91_REG PIO_IFER; // Input Filter Enable Register - AT91_REG PIO_IFDR; // Input Filter Disable Register - AT91_REG PIO_IFSR; // Input Filter Status Register - AT91_REG Reserved2[1]; // - AT91_REG PIO_SODR; // Set Output Data Register - AT91_REG PIO_CODR; // Clear Output Data Register - AT91_REG PIO_ODSR; // Output Data Status Register - AT91_REG PIO_PDSR; // Pin Data Status Register - AT91_REG PIO_IER; // Interrupt Enable Register - AT91_REG PIO_IDR; // Interrupt Disable Register - AT91_REG PIO_IMR; // Interrupt Mask Register - AT91_REG PIO_ISR; // Interrupt Status Register - AT91_REG PIO_MDER; // Multi-driver Enable Register - AT91_REG PIO_MDDR; // Multi-driver Disable Register - AT91_REG PIO_MDSR; // Multi-driver Status Register - AT91_REG Reserved3[1]; // - AT91_REG PIO_PPUDR; // Pull-up Disable Register - AT91_REG PIO_PPUER; // Pull-up Enable Register - AT91_REG PIO_PPUSR; // Pull-up Status Register - AT91_REG Reserved4[1]; // - AT91_REG PIO_ASR; // Select A Register - AT91_REG PIO_BSR; // Select B Register - AT91_REG PIO_ABSR; // AB Select Status Register - AT91_REG Reserved5[9]; // - AT91_REG PIO_OWER; // Output Write Enable Register - AT91_REG PIO_OWDR; // Output Write Disable Register - AT91_REG PIO_OWSR; // Output Write Status Register -} AT91S_PIO, *AT91PS_PIO; - - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Clock Generator Controler -// ***************************************************************************** -typedef struct _AT91S_CKGR { - AT91_REG CKGR_MOR; // Main Oscillator Register - AT91_REG CKGR_MCFR; // Main Clock Frequency Register - AT91_REG Reserved0[1]; // - AT91_REG CKGR_PLLR; // PLL Register -} AT91S_CKGR, *AT91PS_CKGR; - -// -------- CKGR_MOR : (CKGR Offset: 0x0) Main Oscillator Register -------- -#define AT91C_CKGR_MOSCEN ((unsigned int) 0x1 << 0) // (CKGR) Main Oscillator Enable -#define AT91C_CKGR_OSCBYPASS ((unsigned int) 0x1 << 1) // (CKGR) Main Oscillator Bypass -#define AT91C_CKGR_OSCOUNT ((unsigned int) 0xFF << 8) // (CKGR) Main Oscillator Start-up Time -// -------- CKGR_MCFR : (CKGR Offset: 0x4) Main Clock Frequency Register -------- -#define AT91C_CKGR_MAINF ((unsigned int) 0xFFFF << 0) // (CKGR) Main Clock Frequency -#define AT91C_CKGR_MAINRDY ((unsigned int) 0x1 << 16) // (CKGR) Main Clock Ready -// -------- CKGR_PLLR : (CKGR Offset: 0xc) PLL B Register -------- -#define AT91C_CKGR_DIV ((unsigned int) 0xFF << 0) // (CKGR) Divider Selected -#define AT91C_CKGR_DIV_0 ((unsigned int) 0x0) // (CKGR) Divider output is 0 -#define AT91C_CKGR_DIV_BYPASS ((unsigned int) 0x1) // (CKGR) Divider is bypassed -#define AT91C_CKGR_PLLCOUNT ((unsigned int) 0x3F << 8) // (CKGR) PLL Counter -#define AT91C_CKGR_OUT ((unsigned int) 0x3 << 14) // (CKGR) PLL Output Frequency Range -#define AT91C_CKGR_OUT_0 ((unsigned int) 0x0 << 14) // (CKGR) Please refer to the PLL datasheet -#define AT91C_CKGR_OUT_1 ((unsigned int) 0x1 << 14) // (CKGR) Please refer to the PLL datasheet -#define AT91C_CKGR_OUT_2 ((unsigned int) 0x2 << 14) // (CKGR) Please refer to the PLL datasheet -#define AT91C_CKGR_OUT_3 ((unsigned int) 0x3 << 14) // (CKGR) Please refer to the PLL datasheet -#define AT91C_CKGR_MUL ((unsigned int) 0x7FF << 16) // (CKGR) PLL Multiplier -#define AT91C_CKGR_USBDIV ((unsigned int) 0x3 << 28) // (CKGR) Divider for USB Clocks -#define AT91C_CKGR_USBDIV_0 ((unsigned int) 0x0 << 28) // (CKGR) Divider output is PLL clock output -#define AT91C_CKGR_USBDIV_1 ((unsigned int) 0x1 << 28) // (CKGR) Divider output is PLL clock output divided by 2 -#define AT91C_CKGR_USBDIV_2 ((unsigned int) 0x2 << 28) // (CKGR) Divider output is PLL clock output divided by 4 - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Power Management Controler -// ***************************************************************************** -typedef struct _AT91S_PMC { - AT91_REG PMC_SCER; // System Clock Enable Register - AT91_REG PMC_SCDR; // System Clock Disable Register - AT91_REG PMC_SCSR; // System Clock Status Register - AT91_REG Reserved0[1]; // - AT91_REG PMC_PCER; // Peripheral Clock Enable Register - AT91_REG PMC_PCDR; // Peripheral Clock Disable Register - AT91_REG PMC_PCSR; // Peripheral Clock Status Register - AT91_REG Reserved1[1]; // - AT91_REG PMC_MOR; // Main Oscillator Register - AT91_REG PMC_MCFR; // Main Clock Frequency Register - AT91_REG Reserved2[1]; // - AT91_REG PMC_PLLR; // PLL Register - AT91_REG PMC_MCKR; // Master Clock Register - AT91_REG Reserved3[3]; // - AT91_REG PMC_PCKR[4]; // Programmable Clock Register - AT91_REG Reserved4[4]; // - AT91_REG PMC_IER; // Interrupt Enable Register - AT91_REG PMC_IDR; // Interrupt Disable Register - AT91_REG PMC_SR; // Status Register - AT91_REG PMC_IMR; // Interrupt Mask Register -} AT91S_PMC, *AT91PS_PMC; - -// -------- PMC_SCER : (PMC Offset: 0x0) System Clock Enable Register -------- -#define AT91C_PMC_PCK ((unsigned int) 0x1 << 0) // (PMC) Processor Clock -#define AT91C_PMC_UDP ((unsigned int) 0x1 << 7) // (PMC) USB Device Port Clock -#define AT91C_PMC_PCK0 ((unsigned int) 0x1 << 8) // (PMC) Programmable Clock Output -#define AT91C_PMC_PCK1 ((unsigned int) 0x1 << 9) // (PMC) Programmable Clock Output -#define AT91C_PMC_PCK2 ((unsigned int) 0x1 << 10) // (PMC) Programmable Clock Output -#define AT91C_PMC_PCK3 ((unsigned int) 0x1 << 11) // (PMC) Programmable Clock Output -// -------- PMC_SCDR : (PMC Offset: 0x4) System Clock Disable Register -------- -// -------- PMC_SCSR : (PMC Offset: 0x8) System Clock Status Register -------- -// -------- CKGR_MOR : (PMC Offset: 0x20) Main Oscillator Register -------- -// -------- CKGR_MCFR : (PMC Offset: 0x24) Main Clock Frequency Register -------- -// -------- CKGR_PLLR : (PMC Offset: 0x2c) PLL B Register -------- -// -------- PMC_MCKR : (PMC Offset: 0x30) Master Clock Register -------- -#define AT91C_PMC_CSS ((unsigned int) 0x3 << 0) // (PMC) Programmable Clock Selection -#define AT91C_PMC_CSS_SLOW_CLK ((unsigned int) 0x0) // (PMC) Slow Clock is selected -#define AT91C_PMC_CSS_MAIN_CLK ((unsigned int) 0x1) // (PMC) Main Clock is selected -#define AT91C_PMC_CSS_PLL_CLK ((unsigned int) 0x3) // (PMC) Clock from PLL is selected -#define AT91C_PMC_PRES ((unsigned int) 0x7 << 2) // (PMC) Programmable Clock Prescaler -#define AT91C_PMC_PRES_CLK ((unsigned int) 0x0 << 2) // (PMC) Selected clock -#define AT91C_PMC_PRES_CLK_2 ((unsigned int) 0x1 << 2) // (PMC) Selected clock divided by 2 -#define AT91C_PMC_PRES_CLK_4 ((unsigned int) 0x2 << 2) // (PMC) Selected clock divided by 4 -#define AT91C_PMC_PRES_CLK_8 ((unsigned int) 0x3 << 2) // (PMC) Selected clock divided by 8 -#define AT91C_PMC_PRES_CLK_16 ((unsigned int) 0x4 << 2) // (PMC) Selected clock divided by 16 -#define AT91C_PMC_PRES_CLK_32 ((unsigned int) 0x5 << 2) // (PMC) Selected clock divided by 32 -#define AT91C_PMC_PRES_CLK_64 ((unsigned int) 0x6 << 2) // (PMC) Selected clock divided by 64 -// -------- PMC_PCKR : (PMC Offset: 0x40) Programmable Clock Register -------- -// -------- PMC_IER : (PMC Offset: 0x60) PMC Interrupt Enable Register -------- -#define AT91C_PMC_MOSCS ((unsigned int) 0x1 << 0) // (PMC) MOSC Status/Enable/Disable/Mask -#define AT91C_PMC_LOCK ((unsigned int) 0x1 << 2) // (PMC) PLL Status/Enable/Disable/Mask -#define AT91C_PMC_MCKRDY ((unsigned int) 0x1 << 3) // (PMC) MCK_RDY Status/Enable/Disable/Mask -#define AT91C_PMC_PCK0RDY ((unsigned int) 0x1 << 8) // (PMC) PCK0_RDY Status/Enable/Disable/Mask -#define AT91C_PMC_PCK1RDY ((unsigned int) 0x1 << 9) // (PMC) PCK1_RDY Status/Enable/Disable/Mask -#define AT91C_PMC_PCK2RDY ((unsigned int) 0x1 << 10) // (PMC) PCK2_RDY Status/Enable/Disable/Mask -#define AT91C_PMC_PCK3RDY ((unsigned int) 0x1 << 11) // (PMC) PCK3_RDY Status/Enable/Disable/Mask -// -------- PMC_IDR : (PMC Offset: 0x64) PMC Interrupt Disable Register -------- -// -------- PMC_SR : (PMC Offset: 0x68) PMC Status Register -------- -// -------- PMC_IMR : (PMC Offset: 0x6c) PMC Interrupt Mask Register -------- - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Reset Controller Interface -// ***************************************************************************** -typedef struct _AT91S_RSTC { - AT91_REG RSTC_RCR; // Reset Control Register - AT91_REG RSTC_RSR; // Reset Status Register - AT91_REG RSTC_RMR; // Reset Mode Register -} AT91S_RSTC, *AT91PS_RSTC; - -// -------- RSTC_RCR : (RSTC Offset: 0x0) Reset Control Register -------- -#define AT91C_RSTC_PROCRST ((unsigned int) 0x1 << 0) // (RSTC) Processor Reset -#define AT91C_RSTC_PERRST ((unsigned int) 0x1 << 2) // (RSTC) Peripheral Reset -#define AT91C_RSTC_EXTRST ((unsigned int) 0x1 << 3) // (RSTC) External Reset -#define AT91C_RSTC_KEY ((unsigned int) 0xFF << 24) // (RSTC) Password -// -------- RSTC_RSR : (RSTC Offset: 0x4) Reset Status Register -------- -#define AT91C_RSTC_URSTS ((unsigned int) 0x1 << 0) // (RSTC) User Reset Status -#define AT91C_RSTC_BODSTS ((unsigned int) 0x1 << 1) // (RSTC) Brownout Detection Status -#define AT91C_RSTC_RSTTYP ((unsigned int) 0x7 << 8) // (RSTC) Reset Type -#define AT91C_RSTC_RSTTYP_POWERUP ((unsigned int) 0x0 << 8) // (RSTC) Power-up Reset. VDDCORE rising. -#define AT91C_RSTC_RSTTYP_WAKEUP ((unsigned int) 0x1 << 8) // (RSTC) WakeUp Reset. VDDCORE rising. -#define AT91C_RSTC_RSTTYP_WATCHDOG ((unsigned int) 0x2 << 8) // (RSTC) Watchdog Reset. Watchdog overflow occured. -#define AT91C_RSTC_RSTTYP_SOFTWARE ((unsigned int) 0x3 << 8) // (RSTC) Software Reset. Processor reset required by the software. -#define AT91C_RSTC_RSTTYP_USER ((unsigned int) 0x4 << 8) // (RSTC) User Reset. NRST pin detected low. -#define AT91C_RSTC_RSTTYP_BROWNOUT ((unsigned int) 0x5 << 8) // (RSTC) Brownout Reset occured. -#define AT91C_RSTC_NRSTL ((unsigned int) 0x1 << 16) // (RSTC) NRST pin level -#define AT91C_RSTC_SRCMP ((unsigned int) 0x1 << 17) // (RSTC) Software Reset Command in Progress. -// -------- RSTC_RMR : (RSTC Offset: 0x8) Reset Mode Register -------- -#define AT91C_RSTC_URSTEN ((unsigned int) 0x1 << 0) // (RSTC) User Reset Enable -#define AT91C_RSTC_URSTIEN ((unsigned int) 0x1 << 4) // (RSTC) User Reset Interrupt Enable -#define AT91C_RSTC_ERSTL ((unsigned int) 0xF << 8) // (RSTC) User Reset Enable -#define AT91C_RSTC_BODIEN ((unsigned int) 0x1 << 16) // (RSTC) Brownout Detection Interrupt Enable - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Real Time Timer Controller Interface -// ***************************************************************************** -typedef struct _AT91S_RTTC { - AT91_REG RTTC_RTMR; // Real-time Mode Register - AT91_REG RTTC_RTAR; // Real-time Alarm Register - AT91_REG RTTC_RTVR; // Real-time Value Register - AT91_REG RTTC_RTSR; // Real-time Status Register -} AT91S_RTTC, *AT91PS_RTTC; - -// -------- RTTC_RTMR : (RTTC Offset: 0x0) Real-time Mode Register -------- -#define AT91C_RTTC_RTPRES ((unsigned int) 0xFFFF << 0) // (RTTC) Real-time Timer Prescaler Value -#define AT91C_RTTC_ALMIEN ((unsigned int) 0x1 << 16) // (RTTC) Alarm Interrupt Enable -#define AT91C_RTTC_RTTINCIEN ((unsigned int) 0x1 << 17) // (RTTC) Real Time Timer Increment Interrupt Enable -#define AT91C_RTTC_RTTRST ((unsigned int) 0x1 << 18) // (RTTC) Real Time Timer Restart -// -------- RTTC_RTAR : (RTTC Offset: 0x4) Real-time Alarm Register -------- -#define AT91C_RTTC_ALMV ((unsigned int) 0x0 << 0) // (RTTC) Alarm Value -// -------- RTTC_RTVR : (RTTC Offset: 0x8) Current Real-time Value Register -------- -#define AT91C_RTTC_CRTV ((unsigned int) 0x0 << 0) // (RTTC) Current Real-time Value -// -------- RTTC_RTSR : (RTTC Offset: 0xc) Real-time Status Register -------- -#define AT91C_RTTC_ALMS ((unsigned int) 0x1 << 0) // (RTTC) Real-time Alarm Status -#define AT91C_RTTC_RTTINC ((unsigned int) 0x1 << 1) // (RTTC) Real-time Timer Increment - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Periodic Interval Timer Controller Interface -// ***************************************************************************** -typedef struct _AT91S_PITC { - AT91_REG PITC_PIMR; // Period Interval Mode Register - AT91_REG PITC_PISR; // Period Interval Status Register - AT91_REG PITC_PIVR; // Period Interval Value Register - AT91_REG PITC_PIIR; // Period Interval Image Register -} AT91S_PITC, *AT91PS_PITC; - -// -------- PITC_PIMR : (PITC Offset: 0x0) Periodic Interval Mode Register -------- -#define AT91C_PITC_PIV ((unsigned int) 0xFFFFF << 0) // (PITC) Periodic Interval Value -#define AT91C_PITC_PITEN ((unsigned int) 0x1 << 24) // (PITC) Periodic Interval Timer Enabled -#define AT91C_PITC_PITIEN ((unsigned int) 0x1 << 25) // (PITC) Periodic Interval Timer Interrupt Enable -// -------- PITC_PISR : (PITC Offset: 0x4) Periodic Interval Status Register -------- -#define AT91C_PITC_PITS ((unsigned int) 0x1 << 0) // (PITC) Periodic Interval Timer Status -// -------- PITC_PIVR : (PITC Offset: 0x8) Periodic Interval Value Register -------- -#define AT91C_PITC_CPIV ((unsigned int) 0xFFFFF << 0) // (PITC) Current Periodic Interval Value -#define AT91C_PITC_PICNT ((unsigned int) 0xFFF << 20) // (PITC) Periodic Interval Counter -// -------- PITC_PIIR : (PITC Offset: 0xc) Periodic Interval Image Register -------- - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Watchdog Timer Controller Interface -// ***************************************************************************** -typedef struct _AT91S_WDTC { - AT91_REG WDTC_WDCR; // Watchdog Control Register - AT91_REG WDTC_WDMR; // Watchdog Mode Register - AT91_REG WDTC_WDSR; // Watchdog Status Register -} AT91S_WDTC, *AT91PS_WDTC; - -// -------- WDTC_WDCR : (WDTC Offset: 0x0) Periodic Interval Image Register -------- -#define AT91C_WDTC_WDRSTT ((unsigned int) 0x1 << 0) // (WDTC) Watchdog Restart -#define AT91C_WDTC_KEY ((unsigned int) 0xFF << 24) // (WDTC) Watchdog KEY Password -// -------- WDTC_WDMR : (WDTC Offset: 0x4) Watchdog Mode Register -------- -#define AT91C_WDTC_WDV ((unsigned int) 0xFFF << 0) // (WDTC) Watchdog Timer Restart -#define AT91C_WDTC_WDFIEN ((unsigned int) 0x1 << 12) // (WDTC) Watchdog Fault Interrupt Enable -#define AT91C_WDTC_WDRSTEN ((unsigned int) 0x1 << 13) // (WDTC) Watchdog Reset Enable -#define AT91C_WDTC_WDRPROC ((unsigned int) 0x1 << 14) // (WDTC) Watchdog Timer Restart -#define AT91C_WDTC_WDDIS ((unsigned int) 0x1 << 15) // (WDTC) Watchdog Disable -#define AT91C_WDTC_WDD ((unsigned int) 0xFFF << 16) // (WDTC) Watchdog Delta Value -#define AT91C_WDTC_WDDBGHLT ((unsigned int) 0x1 << 28) // (WDTC) Watchdog Debug Halt -#define AT91C_WDTC_WDIDLEHLT ((unsigned int) 0x1 << 29) // (WDTC) Watchdog Idle Halt -// -------- WDTC_WDSR : (WDTC Offset: 0x8) Watchdog Status Register -------- -#define AT91C_WDTC_WDUNF ((unsigned int) 0x1 << 0) // (WDTC) Watchdog Underflow -#define AT91C_WDTC_WDERR ((unsigned int) 0x1 << 1) // (WDTC) Watchdog Error - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Voltage Regulator Mode Controller Interface -// ***************************************************************************** -typedef struct _AT91S_VREG { - AT91_REG VREG_MR; // Voltage Regulator Mode Register -} AT91S_VREG, *AT91PS_VREG; - -// -------- VREG_MR : (VREG Offset: 0x0) Voltage Regulator Mode Register -------- -#define AT91C_VREG_PSTDBY ((unsigned int) 0x1 << 0) // (VREG) Voltage Regulator Power Standby Mode - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Memory Controller Interface -// ***************************************************************************** -typedef struct _AT91S_MC { - AT91_REG MC_RCR; // MC Remap Control Register - AT91_REG MC_ASR; // MC Abort Status Register - AT91_REG MC_AASR; // MC Abort Address Status Register - AT91_REG Reserved0[21]; // - AT91_REG MC_FMR; // MC Flash Mode Register - AT91_REG MC_FCR; // MC Flash Command Register - AT91_REG MC_FSR; // MC Flash Status Register -} AT91S_MC, *AT91PS_MC; - -// -------- MC_RCR : (MC Offset: 0x0) MC Remap Control Register -------- -#define AT91C_MC_RCB ((unsigned int) 0x1 << 0) // (MC) Remap Command Bit -// -------- MC_ASR : (MC Offset: 0x4) MC Abort Status Register -------- -#define AT91C_MC_UNDADD ((unsigned int) 0x1 << 0) // (MC) Undefined Addess Abort Status -#define AT91C_MC_MISADD ((unsigned int) 0x1 << 1) // (MC) Misaligned Addess Abort Status -#define AT91C_MC_ABTSZ ((unsigned int) 0x3 << 8) // (MC) Abort Size Status -#define AT91C_MC_ABTSZ_BYTE ((unsigned int) 0x0 << 8) // (MC) Byte -#define AT91C_MC_ABTSZ_HWORD ((unsigned int) 0x1 << 8) // (MC) Half-word -#define AT91C_MC_ABTSZ_WORD ((unsigned int) 0x2 << 8) // (MC) Word -#define AT91C_MC_ABTTYP ((unsigned int) 0x3 << 10) // (MC) Abort Type Status -#define AT91C_MC_ABTTYP_DATAR ((unsigned int) 0x0 << 10) // (MC) Data Read -#define AT91C_MC_ABTTYP_DATAW ((unsigned int) 0x1 << 10) // (MC) Data Write -#define AT91C_MC_ABTTYP_FETCH ((unsigned int) 0x2 << 10) // (MC) Code Fetch -#define AT91C_MC_MST0 ((unsigned int) 0x1 << 16) // (MC) Master 0 Abort Source -#define AT91C_MC_MST1 ((unsigned int) 0x1 << 17) // (MC) Master 1 Abort Source -#define AT91C_MC_SVMST0 ((unsigned int) 0x1 << 24) // (MC) Saved Master 0 Abort Source -#define AT91C_MC_SVMST1 ((unsigned int) 0x1 << 25) // (MC) Saved Master 1 Abort Source -// -------- MC_FMR : (MC Offset: 0x60) MC Flash Mode Register -------- -#define AT91C_MC_FRDY ((unsigned int) 0x1 << 0) // (MC) Flash Ready -#define AT91C_MC_LOCKE ((unsigned int) 0x1 << 2) // (MC) Lock Error -#define AT91C_MC_PROGE ((unsigned int) 0x1 << 3) // (MC) Programming Error -#define AT91C_MC_NEBP ((unsigned int) 0x1 << 7) // (MC) No Erase Before Programming -#define AT91C_MC_FWS ((unsigned int) 0x3 << 8) // (MC) Flash Wait State -#define AT91C_MC_FWS_0FWS ((unsigned int) 0x0 << 8) // (MC) 1 cycle for Read, 2 for Write operations -#define AT91C_MC_FWS_1FWS ((unsigned int) 0x1 << 8) // (MC) 2 cycles for Read, 3 for Write operations -#define AT91C_MC_FWS_2FWS ((unsigned int) 0x2 << 8) // (MC) 3 cycles for Read, 4 for Write operations -#define AT91C_MC_FWS_3FWS ((unsigned int) 0x3 << 8) // (MC) 4 cycles for Read, 4 for Write operations -#define AT91C_MC_FMCN ((unsigned int) 0xFF << 16) // (MC) Flash Microsecond Cycle Number -// -------- MC_FCR : (MC Offset: 0x64) MC Flash Command Register -------- -#define AT91C_MC_FCMD ((unsigned int) 0xF << 0) // (MC) Flash Command -#define AT91C_MC_FCMD_START_PROG ((unsigned int) 0x1) // (MC) Starts the programming of th epage specified by PAGEN. -#define AT91C_MC_FCMD_LOCK ((unsigned int) 0x2) // (MC) Starts a lock sequence of the sector defined by the bits 4 to 7 of the field PAGEN. -#define AT91C_MC_FCMD_PROG_AND_LOCK ((unsigned int) 0x3) // (MC) The lock sequence automatically happens after the programming sequence is completed. -#define AT91C_MC_FCMD_UNLOCK ((unsigned int) 0x4) // (MC) Starts an unlock sequence of the sector defined by the bits 4 to 7 of the field PAGEN. -#define AT91C_MC_FCMD_ERASE_ALL ((unsigned int) 0x8) // (MC) Starts the erase of the entire flash.If at least a page is locked, the command is cancelled. -#define AT91C_MC_FCMD_SET_GP_NVM ((unsigned int) 0xB) // (MC) Set General Purpose NVM bits. -#define AT91C_MC_FCMD_CLR_GP_NVM ((unsigned int) 0xD) // (MC) Clear General Purpose NVM bits. -#define AT91C_MC_FCMD_SET_SECURITY ((unsigned int) 0xF) // (MC) Set Security Bit. -#define AT91C_MC_PAGEN ((unsigned int) 0x3FF << 8) // (MC) Page Number -#define AT91C_MC_KEY ((unsigned int) 0xFF << 24) // (MC) Writing Protect Key -// -------- MC_FSR : (MC Offset: 0x68) MC Flash Command Register -------- -#define AT91C_MC_SECURITY ((unsigned int) 0x1 << 4) // (MC) Security Bit Status -#define AT91C_MC_GPNVM0 ((unsigned int) 0x1 << 8) // (MC) Sector 0 Lock Status -#define AT91C_MC_GPNVM1 ((unsigned int) 0x1 << 9) // (MC) Sector 1 Lock Status -#define AT91C_MC_GPNVM2 ((unsigned int) 0x1 << 10) // (MC) Sector 2 Lock Status -#define AT91C_MC_GPNVM3 ((unsigned int) 0x1 << 11) // (MC) Sector 3 Lock Status -#define AT91C_MC_GPNVM4 ((unsigned int) 0x1 << 12) // (MC) Sector 4 Lock Status -#define AT91C_MC_GPNVM5 ((unsigned int) 0x1 << 13) // (MC) Sector 5 Lock Status -#define AT91C_MC_GPNVM6 ((unsigned int) 0x1 << 14) // (MC) Sector 6 Lock Status -#define AT91C_MC_GPNVM7 ((unsigned int) 0x1 << 15) // (MC) Sector 7 Lock Status -#define AT91C_MC_LOCKS0 ((unsigned int) 0x1 << 16) // (MC) Sector 0 Lock Status -#define AT91C_MC_LOCKS1 ((unsigned int) 0x1 << 17) // (MC) Sector 1 Lock Status -#define AT91C_MC_LOCKS2 ((unsigned int) 0x1 << 18) // (MC) Sector 2 Lock Status -#define AT91C_MC_LOCKS3 ((unsigned int) 0x1 << 19) // (MC) Sector 3 Lock Status -#define AT91C_MC_LOCKS4 ((unsigned int) 0x1 << 20) // (MC) Sector 4 Lock Status -#define AT91C_MC_LOCKS5 ((unsigned int) 0x1 << 21) // (MC) Sector 5 Lock Status -#define AT91C_MC_LOCKS6 ((unsigned int) 0x1 << 22) // (MC) Sector 6 Lock Status -#define AT91C_MC_LOCKS7 ((unsigned int) 0x1 << 23) // (MC) Sector 7 Lock Status -#define AT91C_MC_LOCKS8 ((unsigned int) 0x1 << 24) // (MC) Sector 8 Lock Status -#define AT91C_MC_LOCKS9 ((unsigned int) 0x1 << 25) // (MC) Sector 9 Lock Status -#define AT91C_MC_LOCKS10 ((unsigned int) 0x1 << 26) // (MC) Sector 10 Lock Status -#define AT91C_MC_LOCKS11 ((unsigned int) 0x1 << 27) // (MC) Sector 11 Lock Status -#define AT91C_MC_LOCKS12 ((unsigned int) 0x1 << 28) // (MC) Sector 12 Lock Status -#define AT91C_MC_LOCKS13 ((unsigned int) 0x1 << 29) // (MC) Sector 13 Lock Status -#define AT91C_MC_LOCKS14 ((unsigned int) 0x1 << 30) // (MC) Sector 14 Lock Status -#define AT91C_MC_LOCKS15 ((unsigned int) 0x1 << 31) // (MC) Sector 15 Lock Status - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Serial Parallel Interface -// ***************************************************************************** -typedef struct _AT91S_SPI { - AT91_REG SPI_CR; // Control Register - AT91_REG SPI_MR; // Mode Register - AT91_REG SPI_RDR; // Receive Data Register - AT91_REG SPI_TDR; // Transmit Data Register - AT91_REG SPI_SR; // Status Register - AT91_REG SPI_IER; // Interrupt Enable Register - AT91_REG SPI_IDR; // Interrupt Disable Register - AT91_REG SPI_IMR; // Interrupt Mask Register - AT91_REG Reserved0[4]; // - AT91_REG SPI_CSR[4]; // Chip Select Register - AT91_REG Reserved1[48]; // - AT91_REG SPI_RPR; // Receive Pointer Register - AT91_REG SPI_RCR; // Receive Counter Register - AT91_REG SPI_TPR; // Transmit Pointer Register - AT91_REG SPI_TCR; // Transmit Counter Register - AT91_REG SPI_RNPR; // Receive Next Pointer Register - AT91_REG SPI_RNCR; // Receive Next Counter Register - AT91_REG SPI_TNPR; // Transmit Next Pointer Register - AT91_REG SPI_TNCR; // Transmit Next Counter Register - AT91_REG SPI_PTCR; // PDC Transfer Control Register - AT91_REG SPI_PTSR; // PDC Transfer Status Register -} AT91S_SPI, *AT91PS_SPI; - -// -------- SPI_CR : (SPI Offset: 0x0) SPI Control Register -------- -#define AT91C_SPI_SPIEN ((unsigned int) 0x1 << 0) // (SPI) SPI Enable -#define AT91C_SPI_SPIDIS ((unsigned int) 0x1 << 1) // (SPI) SPI Disable -#define AT91C_SPI_SWRST ((unsigned int) 0x1 << 7) // (SPI) SPI Software reset -#define AT91C_SPI_LASTXFER ((unsigned int) 0x1 << 24) // (SPI) SPI Last Transfer -// -------- SPI_MR : (SPI Offset: 0x4) SPI Mode Register -------- -#define AT91C_SPI_MSTR ((unsigned int) 0x1 << 0) // (SPI) Master/Slave Mode -#define AT91C_SPI_PS ((unsigned int) 0x1 << 1) // (SPI) Peripheral Select -#define AT91C_SPI_PS_FIXED ((unsigned int) 0x0 << 1) // (SPI) Fixed Peripheral Select -#define AT91C_SPI_PS_VARIABLE ((unsigned int) 0x1 << 1) // (SPI) Variable Peripheral Select -#define AT91C_SPI_PCSDEC ((unsigned int) 0x1 << 2) // (SPI) Chip Select Decode -#define AT91C_SPI_FDIV ((unsigned int) 0x1 << 3) // (SPI) Clock Selection -#define AT91C_SPI_MODFDIS ((unsigned int) 0x1 << 4) // (SPI) Mode Fault Detection -#define AT91C_SPI_LLB ((unsigned int) 0x1 << 7) // (SPI) Clock Selection -#define AT91C_SPI_PCS ((unsigned int) 0xF << 16) // (SPI) Peripheral Chip Select -#define AT91C_SPI_DLYBCS ((unsigned int) 0xFF << 24) // (SPI) Delay Between Chip Selects -// -------- SPI_RDR : (SPI Offset: 0x8) Receive Data Register -------- -#define AT91C_SPI_RD ((unsigned int) 0xFFFF << 0) // (SPI) Receive Data -#define AT91C_SPI_RPCS ((unsigned int) 0xF << 16) // (SPI) Peripheral Chip Select Status -// -------- SPI_TDR : (SPI Offset: 0xc) Transmit Data Register -------- -#define AT91C_SPI_TD ((unsigned int) 0xFFFF << 0) // (SPI) Transmit Data -#define AT91C_SPI_TPCS ((unsigned int) 0xF << 16) // (SPI) Peripheral Chip Select Status -// -------- SPI_SR : (SPI Offset: 0x10) Status Register -------- -#define AT91C_SPI_RDRF ((unsigned int) 0x1 << 0) // (SPI) Receive Data Register Full -#define AT91C_SPI_TDRE ((unsigned int) 0x1 << 1) // (SPI) Transmit Data Register Empty -#define AT91C_SPI_MODF ((unsigned int) 0x1 << 2) // (SPI) Mode Fault Error -#define AT91C_SPI_OVRES ((unsigned int) 0x1 << 3) // (SPI) Overrun Error Status -#define AT91C_SPI_ENDRX ((unsigned int) 0x1 << 4) // (SPI) End of Receiver Transfer -#define AT91C_SPI_ENDTX ((unsigned int) 0x1 << 5) // (SPI) End of Receiver Transfer -#define AT91C_SPI_RXBUFF ((unsigned int) 0x1 << 6) // (SPI) RXBUFF Interrupt -#define AT91C_SPI_TXBUFE ((unsigned int) 0x1 << 7) // (SPI) TXBUFE Interrupt -#define AT91C_SPI_NSSR ((unsigned int) 0x1 << 8) // (SPI) NSSR Interrupt -#define AT91C_SPI_TXEMPTY ((unsigned int) 0x1 << 9) // (SPI) TXEMPTY Interrupt -#define AT91C_SPI_SPIENS ((unsigned int) 0x1 << 16) // (SPI) Enable Status -// -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register -------- -// -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register -------- -// -------- SPI_IMR : (SPI Offset: 0x1c) Interrupt Mask Register -------- -// -------- SPI_CSR : (SPI Offset: 0x30) Chip Select Register -------- -#define AT91C_SPI_CPOL ((unsigned int) 0x1 << 0) // (SPI) Clock Polarity -#define AT91C_SPI_NCPHA ((unsigned int) 0x1 << 1) // (SPI) Clock Phase -#define AT91C_SPI_CSAAT ((unsigned int) 0x1 << 3) // (SPI) Chip Select Active After Transfer -#define AT91C_SPI_BITS ((unsigned int) 0xF << 4) // (SPI) Bits Per Transfer -#define AT91C_SPI_BITS_8 ((unsigned int) 0x0 << 4) // (SPI) 8 Bits Per transfer -#define AT91C_SPI_BITS_9 ((unsigned int) 0x1 << 4) // (SPI) 9 Bits Per transfer -#define AT91C_SPI_BITS_10 ((unsigned int) 0x2 << 4) // (SPI) 10 Bits Per transfer -#define AT91C_SPI_BITS_11 ((unsigned int) 0x3 << 4) // (SPI) 11 Bits Per transfer -#define AT91C_SPI_BITS_12 ((unsigned int) 0x4 << 4) // (SPI) 12 Bits Per transfer -#define AT91C_SPI_BITS_13 ((unsigned int) 0x5 << 4) // (SPI) 13 Bits Per transfer -#define AT91C_SPI_BITS_14 ((unsigned int) 0x6 << 4) // (SPI) 14 Bits Per transfer -#define AT91C_SPI_BITS_15 ((unsigned int) 0x7 << 4) // (SPI) 15 Bits Per transfer -#define AT91C_SPI_BITS_16 ((unsigned int) 0x8 << 4) // (SPI) 16 Bits Per transfer -#define AT91C_SPI_SCBR ((unsigned int) 0xFF << 8) // (SPI) Serial Clock Baud Rate -#define AT91C_SPI_DLYBS ((unsigned int) 0xFF << 16) // (SPI) Delay Before SPCK -#define AT91C_SPI_DLYBCT ((unsigned int) 0xFF << 24) // (SPI) Delay Between Consecutive Transfers - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Usart -// ***************************************************************************** -typedef struct _AT91S_USART { - AT91_REG US_CR; // Control Register - AT91_REG US_MR; // Mode Register - AT91_REG US_IER; // Interrupt Enable Register - AT91_REG US_IDR; // Interrupt Disable Register - AT91_REG US_IMR; // Interrupt Mask Register - AT91_REG US_CSR; // Channel Status Register - AT91_REG US_RHR; // Receiver Holding Register - AT91_REG US_THR; // Transmitter Holding Register - AT91_REG US_BRGR; // Baud Rate Generator Register - AT91_REG US_RTOR; // Receiver Time-out Register - AT91_REG US_TTGR; // Transmitter Time-guard Register - AT91_REG Reserved0[5]; // - AT91_REG US_FIDI; // FI_DI_Ratio Register - AT91_REG US_NER; // Nb Errors Register - AT91_REG Reserved1[1]; // - AT91_REG US_IF; // IRDA_FILTER Register - AT91_REG Reserved2[44]; // - AT91_REG US_RPR; // Receive Pointer Register - AT91_REG US_RCR; // Receive Counter Register - AT91_REG US_TPR; // Transmit Pointer Register - AT91_REG US_TCR; // Transmit Counter Register - AT91_REG US_RNPR; // Receive Next Pointer Register - AT91_REG US_RNCR; // Receive Next Counter Register - AT91_REG US_TNPR; // Transmit Next Pointer Register - AT91_REG US_TNCR; // Transmit Next Counter Register - AT91_REG US_PTCR; // PDC Transfer Control Register - AT91_REG US_PTSR; // PDC Transfer Status Register -} AT91S_USART, *AT91PS_USART; - -// -------- US_CR : (USART Offset: 0x0) Debug Unit Control Register -------- -#define AT91C_US_STTBRK ((unsigned int) 0x1 << 9) // (USART) Start Break -#define AT91C_US_STPBRK ((unsigned int) 0x1 << 10) // (USART) Stop Break -#define AT91C_US_STTTO ((unsigned int) 0x1 << 11) // (USART) Start Time-out -#define AT91C_US_SENDA ((unsigned int) 0x1 << 12) // (USART) Send Address -#define AT91C_US_RSTIT ((unsigned int) 0x1 << 13) // (USART) Reset Iterations -#define AT91C_US_RSTNACK ((unsigned int) 0x1 << 14) // (USART) Reset Non Acknowledge -#define AT91C_US_RETTO ((unsigned int) 0x1 << 15) // (USART) Rearm Time-out -#define AT91C_US_DTREN ((unsigned int) 0x1 << 16) // (USART) Data Terminal ready Enable -#define AT91C_US_DTRDIS ((unsigned int) 0x1 << 17) // (USART) Data Terminal ready Disable -#define AT91C_US_RTSEN ((unsigned int) 0x1 << 18) // (USART) Request to Send enable -#define AT91C_US_RTSDIS ((unsigned int) 0x1 << 19) // (USART) Request to Send Disable -// -------- US_MR : (USART Offset: 0x4) Debug Unit Mode Register -------- -#define AT91C_US_USMODE ((unsigned int) 0xF << 0) // (USART) Usart mode -#define AT91C_US_USMODE_NORMAL ((unsigned int) 0x0) // (USART) Normal -#define AT91C_US_USMODE_RS485 ((unsigned int) 0x1) // (USART) RS485 -#define AT91C_US_USMODE_HWHSH ((unsigned int) 0x2) // (USART) Hardware Handshaking -#define AT91C_US_USMODE_MODEM ((unsigned int) 0x3) // (USART) Modem -#define AT91C_US_USMODE_ISO7816_0 ((unsigned int) 0x4) // (USART) ISO7816 protocol: T = 0 -#define AT91C_US_USMODE_ISO7816_1 ((unsigned int) 0x6) // (USART) ISO7816 protocol: T = 1 -#define AT91C_US_USMODE_IRDA ((unsigned int) 0x8) // (USART) IrDA -#define AT91C_US_USMODE_SWHSH ((unsigned int) 0xC) // (USART) Software Handshaking -#define AT91C_US_CLKS ((unsigned int) 0x3 << 4) // (USART) Clock Selection (Baud Rate generator Input Clock -#define AT91C_US_CLKS_CLOCK ((unsigned int) 0x0 << 4) // (USART) Clock -#define AT91C_US_CLKS_FDIV1 ((unsigned int) 0x1 << 4) // (USART) fdiv1 -#define AT91C_US_CLKS_SLOW ((unsigned int) 0x2 << 4) // (USART) slow_clock (ARM) -#define AT91C_US_CLKS_EXT ((unsigned int) 0x3 << 4) // (USART) External (SCK) -#define AT91C_US_CHRL ((unsigned int) 0x3 << 6) // (USART) Clock Selection (Baud Rate generator Input Clock -#define AT91C_US_CHRL_5_BITS ((unsigned int) 0x0 << 6) // (USART) Character Length: 5 bits -#define AT91C_US_CHRL_6_BITS ((unsigned int) 0x1 << 6) // (USART) Character Length: 6 bits -#define AT91C_US_CHRL_7_BITS ((unsigned int) 0x2 << 6) // (USART) Character Length: 7 bits -#define AT91C_US_CHRL_8_BITS ((unsigned int) 0x3 << 6) // (USART) Character Length: 8 bits -#define AT91C_US_SYNC ((unsigned int) 0x1 << 8) // (USART) Synchronous Mode Select -#define AT91C_US_NBSTOP ((unsigned int) 0x3 << 12) // (USART) Number of Stop bits -#define AT91C_US_NBSTOP_1_BIT ((unsigned int) 0x0 << 12) // (USART) 1 stop bit -#define AT91C_US_NBSTOP_15_BIT ((unsigned int) 0x1 << 12) // (USART) Asynchronous (SYNC=0) 2 stop bits Synchronous (SYNC=1) 2 stop bits -#define AT91C_US_NBSTOP_2_BIT ((unsigned int) 0x2 << 12) // (USART) 2 stop bits -#define AT91C_US_MSBF ((unsigned int) 0x1 << 16) // (USART) Bit Order -#define AT91C_US_MODE9 ((unsigned int) 0x1 << 17) // (USART) 9-bit Character length -#define AT91C_US_CKLO ((unsigned int) 0x1 << 18) // (USART) Clock Output Select -#define AT91C_US_OVER ((unsigned int) 0x1 << 19) // (USART) Over Sampling Mode -#define AT91C_US_INACK ((unsigned int) 0x1 << 20) // (USART) Inhibit Non Acknowledge -#define AT91C_US_DSNACK ((unsigned int) 0x1 << 21) // (USART) Disable Successive NACK -#define AT91C_US_MAX_ITER ((unsigned int) 0x1 << 24) // (USART) Number of Repetitions -#define AT91C_US_FILTER ((unsigned int) 0x1 << 28) // (USART) Receive Line Filter -// -------- US_IER : (USART Offset: 0x8) Debug Unit Interrupt Enable Register -------- -#define AT91C_US_RXBRK ((unsigned int) 0x1 << 2) // (USART) Break Received/End of Break -#define AT91C_US_TIMEOUT ((unsigned int) 0x1 << 8) // (USART) Receiver Time-out -#define AT91C_US_ITERATION ((unsigned int) 0x1 << 10) // (USART) Max number of Repetitions Reached -#define AT91C_US_NACK ((unsigned int) 0x1 << 13) // (USART) Non Acknowledge -#define AT91C_US_RIIC ((unsigned int) 0x1 << 16) // (USART) Ring INdicator Input Change Flag -#define AT91C_US_DSRIC ((unsigned int) 0x1 << 17) // (USART) Data Set Ready Input Change Flag -#define AT91C_US_DCDIC ((unsigned int) 0x1 << 18) // (USART) Data Carrier Flag -#define AT91C_US_CTSIC ((unsigned int) 0x1 << 19) // (USART) Clear To Send Input Change Flag -// -------- US_IDR : (USART Offset: 0xc) Debug Unit Interrupt Disable Register -------- -// -------- US_IMR : (USART Offset: 0x10) Debug Unit Interrupt Mask Register -------- -// -------- US_CSR : (USART Offset: 0x14) Debug Unit Channel Status Register -------- -#define AT91C_US_RI ((unsigned int) 0x1 << 20) // (USART) Image of RI Input -#define AT91C_US_DSR ((unsigned int) 0x1 << 21) // (USART) Image of DSR Input -#define AT91C_US_DCD ((unsigned int) 0x1 << 22) // (USART) Image of DCD Input -#define AT91C_US_CTS ((unsigned int) 0x1 << 23) // (USART) Image of CTS Input - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Synchronous Serial Controller Interface -// ***************************************************************************** -typedef struct _AT91S_SSC { - AT91_REG SSC_CR; // Control Register - AT91_REG SSC_CMR; // Clock Mode Register - AT91_REG Reserved0[2]; // - AT91_REG SSC_RCMR; // Receive Clock ModeRegister - AT91_REG SSC_RFMR; // Receive Frame Mode Register - AT91_REG SSC_TCMR; // Transmit Clock Mode Register - AT91_REG SSC_TFMR; // Transmit Frame Mode Register - AT91_REG SSC_RHR; // Receive Holding Register - AT91_REG SSC_THR; // Transmit Holding Register - AT91_REG Reserved1[2]; // - AT91_REG SSC_RSHR; // Receive Sync Holding Register - AT91_REG SSC_TSHR; // Transmit Sync Holding Register - AT91_REG Reserved2[2]; // - AT91_REG SSC_SR; // Status Register - AT91_REG SSC_IER; // Interrupt Enable Register - AT91_REG SSC_IDR; // Interrupt Disable Register - AT91_REG SSC_IMR; // Interrupt Mask Register - AT91_REG Reserved3[44]; // - AT91_REG SSC_RPR; // Receive Pointer Register - AT91_REG SSC_RCR; // Receive Counter Register - AT91_REG SSC_TPR; // Transmit Pointer Register - AT91_REG SSC_TCR; // Transmit Counter Register - AT91_REG SSC_RNPR; // Receive Next Pointer Register - AT91_REG SSC_RNCR; // Receive Next Counter Register - AT91_REG SSC_TNPR; // Transmit Next Pointer Register - AT91_REG SSC_TNCR; // Transmit Next Counter Register - AT91_REG SSC_PTCR; // PDC Transfer Control Register - AT91_REG SSC_PTSR; // PDC Transfer Status Register -} AT91S_SSC, *AT91PS_SSC; - -// -------- SSC_CR : (SSC Offset: 0x0) SSC Control Register -------- -#define AT91C_SSC_RXEN ((unsigned int) 0x1 << 0) // (SSC) Receive Enable -#define AT91C_SSC_RXDIS ((unsigned int) 0x1 << 1) // (SSC) Receive Disable -#define AT91C_SSC_TXEN ((unsigned int) 0x1 << 8) // (SSC) Transmit Enable -#define AT91C_SSC_TXDIS ((unsigned int) 0x1 << 9) // (SSC) Transmit Disable -#define AT91C_SSC_SWRST ((unsigned int) 0x1 << 15) // (SSC) Software Reset -// -------- SSC_RCMR : (SSC Offset: 0x10) SSC Receive Clock Mode Register -------- -#define AT91C_SSC_CKS ((unsigned int) 0x3 << 0) // (SSC) Receive/Transmit Clock Selection -#define AT91C_SSC_CKS_DIV ((unsigned int) 0x0) // (SSC) Divided Clock -#define AT91C_SSC_CKS_TK ((unsigned int) 0x1) // (SSC) TK Clock signal -#define AT91C_SSC_CKS_RK ((unsigned int) 0x2) // (SSC) RK pin -#define AT91C_SSC_CKO ((unsigned int) 0x7 << 2) // (SSC) Receive/Transmit Clock Output Mode Selection -#define AT91C_SSC_CKO_NONE ((unsigned int) 0x0 << 2) // (SSC) Receive/Transmit Clock Output Mode: None RK pin: Input-only -#define AT91C_SSC_CKO_CONTINOUS ((unsigned int) 0x1 << 2) // (SSC) Continuous Receive/Transmit Clock RK pin: Output -#define AT91C_SSC_CKO_DATA_TX ((unsigned int) 0x2 << 2) // (SSC) Receive/Transmit Clock only during data transfers RK pin: Output -#define AT91C_SSC_CKI ((unsigned int) 0x1 << 5) // (SSC) Receive/Transmit Clock Inversion -#define AT91C_SSC_START ((unsigned int) 0xF << 8) // (SSC) Receive/Transmit Start Selection -#define AT91C_SSC_START_CONTINOUS ((unsigned int) 0x0 << 8) // (SSC) Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data. -#define AT91C_SSC_START_TX ((unsigned int) 0x1 << 8) // (SSC) Transmit/Receive start -#define AT91C_SSC_START_LOW_RF ((unsigned int) 0x2 << 8) // (SSC) Detection of a low level on RF input -#define AT91C_SSC_START_HIGH_RF ((unsigned int) 0x3 << 8) // (SSC) Detection of a high level on RF input -#define AT91C_SSC_START_FALL_RF ((unsigned int) 0x4 << 8) // (SSC) Detection of a falling edge on RF input -#define AT91C_SSC_START_RISE_RF ((unsigned int) 0x5 << 8) // (SSC) Detection of a rising edge on RF input -#define AT91C_SSC_START_LEVEL_RF ((unsigned int) 0x6 << 8) // (SSC) Detection of any level change on RF input -#define AT91C_SSC_START_EDGE_RF ((unsigned int) 0x7 << 8) // (SSC) Detection of any edge on RF input -#define AT91C_SSC_START_0 ((unsigned int) 0x8 << 8) // (SSC) Compare 0 -#define AT91C_SSC_STTDLY ((unsigned int) 0xFF << 16) // (SSC) Receive/Transmit Start Delay -#define AT91C_SSC_PERIOD ((unsigned int) 0xFF << 24) // (SSC) Receive/Transmit Period Divider Selection -// -------- SSC_RFMR : (SSC Offset: 0x14) SSC Receive Frame Mode Register -------- -#define AT91C_SSC_DATLEN ((unsigned int) 0x1F << 0) // (SSC) Data Length -#define AT91C_SSC_LOOP ((unsigned int) 0x1 << 5) // (SSC) Loop Mode -#define AT91C_SSC_MSBF ((unsigned int) 0x1 << 7) // (SSC) Most Significant Bit First -#define AT91C_SSC_DATNB ((unsigned int) 0xF << 8) // (SSC) Data Number per Frame -#define AT91C_SSC_FSLEN ((unsigned int) 0xF << 16) // (SSC) Receive/Transmit Frame Sync length -#define AT91C_SSC_FSOS ((unsigned int) 0x7 << 20) // (SSC) Receive/Transmit Frame Sync Output Selection -#define AT91C_SSC_FSOS_NONE ((unsigned int) 0x0 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: None RK pin Input-only -#define AT91C_SSC_FSOS_NEGATIVE ((unsigned int) 0x1 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Negative Pulse -#define AT91C_SSC_FSOS_POSITIVE ((unsigned int) 0x2 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Positive Pulse -#define AT91C_SSC_FSOS_LOW ((unsigned int) 0x3 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver Low during data transfer -#define AT91C_SSC_FSOS_HIGH ((unsigned int) 0x4 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver High during data transfer -#define AT91C_SSC_FSOS_TOGGLE ((unsigned int) 0x5 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Toggling at each start of data transfer -#define AT91C_SSC_FSEDGE ((unsigned int) 0x1 << 24) // (SSC) Frame Sync Edge Detection -// -------- SSC_TCMR : (SSC Offset: 0x18) SSC Transmit Clock Mode Register -------- -// -------- SSC_TFMR : (SSC Offset: 0x1c) SSC Transmit Frame Mode Register -------- -#define AT91C_SSC_DATDEF ((unsigned int) 0x1 << 5) // (SSC) Data Default Value -#define AT91C_SSC_FSDEN ((unsigned int) 0x1 << 23) // (SSC) Frame Sync Data Enable -// -------- SSC_SR : (SSC Offset: 0x40) SSC Status Register -------- -#define AT91C_SSC_TXRDY ((unsigned int) 0x1 << 0) // (SSC) Transmit Ready -#define AT91C_SSC_TXEMPTY ((unsigned int) 0x1 << 1) // (SSC) Transmit Empty -#define AT91C_SSC_ENDTX ((unsigned int) 0x1 << 2) // (SSC) End Of Transmission -#define AT91C_SSC_TXBUFE ((unsigned int) 0x1 << 3) // (SSC) Transmit Buffer Empty -#define AT91C_SSC_RXRDY ((unsigned int) 0x1 << 4) // (SSC) Receive Ready -#define AT91C_SSC_OVRUN ((unsigned int) 0x1 << 5) // (SSC) Receive Overrun -#define AT91C_SSC_ENDRX ((unsigned int) 0x1 << 6) // (SSC) End of Reception -#define AT91C_SSC_RXBUFF ((unsigned int) 0x1 << 7) // (SSC) Receive Buffer Full -#define AT91C_SSC_TXSYN ((unsigned int) 0x1 << 10) // (SSC) Transmit Sync -#define AT91C_SSC_RXSYN ((unsigned int) 0x1 << 11) // (SSC) Receive Sync -#define AT91C_SSC_TXENA ((unsigned int) 0x1 << 16) // (SSC) Transmit Enable -#define AT91C_SSC_RXENA ((unsigned int) 0x1 << 17) // (SSC) Receive Enable -// -------- SSC_IER : (SSC Offset: 0x44) SSC Interrupt Enable Register -------- -// -------- SSC_IDR : (SSC Offset: 0x48) SSC Interrupt Disable Register -------- -// -------- SSC_IMR : (SSC Offset: 0x4c) SSC Interrupt Mask Register -------- - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Two-wire Interface -// ***************************************************************************** -typedef struct _AT91S_TWI { - AT91_REG TWI_CR; // Control Register - AT91_REG TWI_MMR; // Master Mode Register - AT91_REG Reserved0[1]; // - AT91_REG TWI_IADR; // Internal Address Register - AT91_REG TWI_CWGR; // Clock Waveform Generator Register - AT91_REG Reserved1[3]; // - AT91_REG TWI_SR; // Status Register - AT91_REG TWI_IER; // Interrupt Enable Register - AT91_REG TWI_IDR; // Interrupt Disable Register - AT91_REG TWI_IMR; // Interrupt Mask Register - AT91_REG TWI_RHR; // Receive Holding Register - AT91_REG TWI_THR; // Transmit Holding Register -} AT91S_TWI, *AT91PS_TWI; - -// -------- TWI_CR : (TWI Offset: 0x0) TWI Control Register -------- -#define AT91C_TWI_START ((unsigned int) 0x1 << 0) // (TWI) Send a START Condition -#define AT91C_TWI_STOP ((unsigned int) 0x1 << 1) // (TWI) Send a STOP Condition -#define AT91C_TWI_MSEN ((unsigned int) 0x1 << 2) // (TWI) TWI Master Transfer Enabled -#define AT91C_TWI_MSDIS ((unsigned int) 0x1 << 3) // (TWI) TWI Master Transfer Disabled -#define AT91C_TWI_SWRST ((unsigned int) 0x1 << 7) // (TWI) Software Reset -// -------- TWI_MMR : (TWI Offset: 0x4) TWI Master Mode Register -------- -#define AT91C_TWI_IADRSZ ((unsigned int) 0x3 << 8) // (TWI) Internal Device Address Size -#define AT91C_TWI_IADRSZ_NO ((unsigned int) 0x0 << 8) // (TWI) No internal device address -#define AT91C_TWI_IADRSZ_1_BYTE ((unsigned int) 0x1 << 8) // (TWI) One-byte internal device address -#define AT91C_TWI_IADRSZ_2_BYTE ((unsigned int) 0x2 << 8) // (TWI) Two-byte internal device address -#define AT91C_TWI_IADRSZ_3_BYTE ((unsigned int) 0x3 << 8) // (TWI) Three-byte internal device address -#define AT91C_TWI_MREAD ((unsigned int) 0x1 << 12) // (TWI) Master Read Direction -#define AT91C_TWI_DADR ((unsigned int) 0x7F << 16) // (TWI) Device Address -// -------- TWI_CWGR : (TWI Offset: 0x10) TWI Clock Waveform Generator Register -------- -#define AT91C_TWI_CLDIV ((unsigned int) 0xFF << 0) // (TWI) Clock Low Divider -#define AT91C_TWI_CHDIV ((unsigned int) 0xFF << 8) // (TWI) Clock High Divider -#define AT91C_TWI_CKDIV ((unsigned int) 0x7 << 16) // (TWI) Clock Divider -// -------- TWI_SR : (TWI Offset: 0x20) TWI Status Register -------- -#define AT91C_TWI_TXCOMP ((unsigned int) 0x1 << 0) // (TWI) Transmission Completed -#define AT91C_TWI_RXRDY ((unsigned int) 0x1 << 1) // (TWI) Receive holding register ReaDY -#define AT91C_TWI_TXRDY ((unsigned int) 0x1 << 2) // (TWI) Transmit holding register ReaDY -#define AT91C_TWI_OVRE ((unsigned int) 0x1 << 6) // (TWI) Overrun Error -#define AT91C_TWI_UNRE ((unsigned int) 0x1 << 7) // (TWI) Underrun Error -#define AT91C_TWI_NACK ((unsigned int) 0x1 << 8) // (TWI) Not Acknowledged -// -------- TWI_IER : (TWI Offset: 0x24) TWI Interrupt Enable Register -------- -// -------- TWI_IDR : (TWI Offset: 0x28) TWI Interrupt Disable Register -------- -// -------- TWI_IMR : (TWI Offset: 0x2c) TWI Interrupt Mask Register -------- - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR PWMC Channel Interface -// ***************************************************************************** -typedef struct _AT91S_PWMC_CH { - AT91_REG PWMC_CMR; // Channel Mode Register - AT91_REG PWMC_CDTYR; // Channel Duty Cycle Register - AT91_REG PWMC_CPRDR; // Channel Period Register - AT91_REG PWMC_CCNTR; // Channel Counter Register - AT91_REG PWMC_CUPDR; // Channel Update Register - AT91_REG PWMC_Reserved[3]; // Reserved -} AT91S_PWMC_CH, *AT91PS_PWMC_CH; - -// -------- PWMC_CMR : (PWMC_CH Offset: 0x0) PWMC Channel Mode Register -------- -#define AT91C_PWMC_CPRE ((unsigned int) 0xF << 0) // (PWMC_CH) Channel Pre-scaler : PWMC_CLKx -#define AT91C_PWMC_CPRE_MCK ((unsigned int) 0x0) // (PWMC_CH) -#define AT91C_PWMC_CPRE_MCKA ((unsigned int) 0xB) // (PWMC_CH) -#define AT91C_PWMC_CPRE_MCKB ((unsigned int) 0xC) // (PWMC_CH) -#define AT91C_PWMC_CALG ((unsigned int) 0x1 << 8) // (PWMC_CH) Channel Alignment -#define AT91C_PWMC_CPOL ((unsigned int) 0x1 << 9) // (PWMC_CH) Channel Polarity -#define AT91C_PWMC_CPD ((unsigned int) 0x1 << 10) // (PWMC_CH) Channel Update Period -// -------- PWMC_CDTYR : (PWMC_CH Offset: 0x4) PWMC Channel Duty Cycle Register -------- -#define AT91C_PWMC_CDTY ((unsigned int) 0x0 << 0) // (PWMC_CH) Channel Duty Cycle -// -------- PWMC_CPRDR : (PWMC_CH Offset: 0x8) PWMC Channel Period Register -------- -#define AT91C_PWMC_CPRD ((unsigned int) 0x0 << 0) // (PWMC_CH) Channel Period -// -------- PWMC_CCNTR : (PWMC_CH Offset: 0xc) PWMC Channel Counter Register -------- -#define AT91C_PWMC_CCNT ((unsigned int) 0x0 << 0) // (PWMC_CH) Channel Counter -// -------- PWMC_CUPDR : (PWMC_CH Offset: 0x10) PWMC Channel Update Register -------- -#define AT91C_PWMC_CUPD ((unsigned int) 0x0 << 0) // (PWMC_CH) Channel Update - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Pulse Width Modulation Controller Interface -// ***************************************************************************** -typedef struct _AT91S_PWMC { - AT91_REG PWMC_MR; // PWMC Mode Register - AT91_REG PWMC_ENA; // PWMC Enable Register - AT91_REG PWMC_DIS; // PWMC Disable Register - AT91_REG PWMC_SR; // PWMC Status Register - AT91_REG PWMC_IER; // PWMC Interrupt Enable Register - AT91_REG PWMC_IDR; // PWMC Interrupt Disable Register - AT91_REG PWMC_IMR; // PWMC Interrupt Mask Register - AT91_REG PWMC_ISR; // PWMC Interrupt Status Register - AT91_REG Reserved0[55]; // - AT91_REG PWMC_VR; // PWMC Version Register - AT91_REG Reserved1[64]; // - AT91S_PWMC_CH PWMC_CH[4]; // PWMC Channel -} AT91S_PWMC, *AT91PS_PWMC; - -// -------- PWMC_MR : (PWMC Offset: 0x0) PWMC Mode Register -------- -#define AT91C_PWMC_DIVA ((unsigned int) 0xFF << 0) // (PWMC) CLKA divide factor. -#define AT91C_PWMC_PREA ((unsigned int) 0xF << 8) // (PWMC) Divider Input Clock Prescaler A -#define AT91C_PWMC_PREA_MCK ((unsigned int) 0x0 << 8) // (PWMC) -#define AT91C_PWMC_DIVB ((unsigned int) 0xFF << 16) // (PWMC) CLKB divide factor. -#define AT91C_PWMC_PREB ((unsigned int) 0xF << 24) // (PWMC) Divider Input Clock Prescaler B -#define AT91C_PWMC_PREB_MCK ((unsigned int) 0x0 << 24) // (PWMC) -// -------- PWMC_ENA : (PWMC Offset: 0x4) PWMC Enable Register -------- -#define AT91C_PWMC_CHID0 ((unsigned int) 0x1 << 0) // (PWMC) Channel ID 0 -#define AT91C_PWMC_CHID1 ((unsigned int) 0x1 << 1) // (PWMC) Channel ID 1 -#define AT91C_PWMC_CHID2 ((unsigned int) 0x1 << 2) // (PWMC) Channel ID 2 -#define AT91C_PWMC_CHID3 ((unsigned int) 0x1 << 3) // (PWMC) Channel ID 3 -// -------- PWMC_DIS : (PWMC Offset: 0x8) PWMC Disable Register -------- -// -------- PWMC_SR : (PWMC Offset: 0xc) PWMC Status Register -------- -// -------- PWMC_IER : (PWMC Offset: 0x10) PWMC Interrupt Enable Register -------- -// -------- PWMC_IDR : (PWMC Offset: 0x14) PWMC Interrupt Disable Register -------- -// -------- PWMC_IMR : (PWMC Offset: 0x18) PWMC Interrupt Mask Register -------- -// -------- PWMC_ISR : (PWMC Offset: 0x1c) PWMC Interrupt Status Register -------- - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR USB Device Interface -// ***************************************************************************** -typedef struct _AT91S_UDP { - AT91_REG UDP_NUM; // Frame Number Register - AT91_REG UDP_GLBSTATE; // Global State Register - AT91_REG UDP_FADDR; // Function Address Register - AT91_REG Reserved0[1]; // - AT91_REG UDP_IER; // Interrupt Enable Register - AT91_REG UDP_IDR; // Interrupt Disable Register - AT91_REG UDP_IMR; // Interrupt Mask Register - AT91_REG UDP_ISR; // Interrupt Status Register - AT91_REG UDP_ICR; // Interrupt Clear Register - AT91_REG Reserved1[1]; // - AT91_REG UDP_RSTEP; // Reset Endpoint Register - AT91_REG Reserved2[1]; // - AT91_REG UDP_CSR[6]; // Endpoint Control and Status Register - AT91_REG Reserved3[2]; // - AT91_REG UDP_FDR[6]; // Endpoint FIFO Data Register - AT91_REG Reserved4[3]; // - AT91_REG UDP_TXVC; // Transceiver Control Register -} AT91S_UDP, *AT91PS_UDP; - -// -------- UDP_FRM_NUM : (UDP Offset: 0x0) USB Frame Number Register -------- -#define AT91C_UDP_FRM_NUM ((unsigned int) 0x7FF << 0) // (UDP) Frame Number as Defined in the Packet Field Formats -#define AT91C_UDP_FRM_ERR ((unsigned int) 0x1 << 16) // (UDP) Frame Error -#define AT91C_UDP_FRM_OK ((unsigned int) 0x1 << 17) // (UDP) Frame OK -// -------- UDP_GLB_STATE : (UDP Offset: 0x4) USB Global State Register -------- -#define AT91C_UDP_FADDEN ((unsigned int) 0x1 << 0) // (UDP) Function Address Enable -#define AT91C_UDP_CONFG ((unsigned int) 0x1 << 1) // (UDP) Configured -#define AT91C_UDP_ESR ((unsigned int) 0x1 << 2) // (UDP) Enable Send Resume -#define AT91C_UDP_RSMINPR ((unsigned int) 0x1 << 3) // (UDP) A Resume Has Been Sent to the Host -#define AT91C_UDP_RMWUPE ((unsigned int) 0x1 << 4) // (UDP) Remote Wake Up Enable -// -------- UDP_FADDR : (UDP Offset: 0x8) USB Function Address Register -------- -#define AT91C_UDP_FADD ((unsigned int) 0xFF << 0) // (UDP) Function Address Value -#define AT91C_UDP_FEN ((unsigned int) 0x1 << 8) // (UDP) Function Enable -// -------- UDP_IER : (UDP Offset: 0x10) USB Interrupt Enable Register -------- -#define AT91C_UDP_EPINT0 ((unsigned int) 0x1 << 0) // (UDP) Endpoint 0 Interrupt -#define AT91C_UDP_EPINT1 ((unsigned int) 0x1 << 1) // (UDP) Endpoint 0 Interrupt -#define AT91C_UDP_EPINT2 ((unsigned int) 0x1 << 2) // (UDP) Endpoint 2 Interrupt -#define AT91C_UDP_EPINT3 ((unsigned int) 0x1 << 3) // (UDP) Endpoint 3 Interrupt -#define AT91C_UDP_EPINT4 ((unsigned int) 0x1 << 4) // (UDP) Endpoint 4 Interrupt -#define AT91C_UDP_EPINT5 ((unsigned int) 0x1 << 5) // (UDP) Endpoint 5 Interrupt -#define AT91C_UDP_RXSUSP ((unsigned int) 0x1 << 8) // (UDP) USB Suspend Interrupt -#define AT91C_UDP_RXRSM ((unsigned int) 0x1 << 9) // (UDP) USB Resume Interrupt -#define AT91C_UDP_EXTRSM ((unsigned int) 0x1 << 10) // (UDP) USB External Resume Interrupt -#define AT91C_UDP_SOFINT ((unsigned int) 0x1 << 11) // (UDP) USB Start Of frame Interrupt -#define AT91C_UDP_WAKEUP ((unsigned int) 0x1 << 13) // (UDP) USB Resume Interrupt -// -------- UDP_IDR : (UDP Offset: 0x14) USB Interrupt Disable Register -------- -// -------- UDP_IMR : (UDP Offset: 0x18) USB Interrupt Mask Register -------- -// -------- UDP_ISR : (UDP Offset: 0x1c) USB Interrupt Status Register -------- -#define AT91C_UDP_ENDBUSRES ((unsigned int) 0x1 << 12) // (UDP) USB End Of Bus Reset Interrupt -// -------- UDP_ICR : (UDP Offset: 0x20) USB Interrupt Clear Register -------- -// -------- UDP_RST_EP : (UDP Offset: 0x28) USB Reset Endpoint Register -------- -#define AT91C_UDP_EP0 ((unsigned int) 0x1 << 0) // (UDP) Reset Endpoint 0 -#define AT91C_UDP_EP1 ((unsigned int) 0x1 << 1) // (UDP) Reset Endpoint 1 -#define AT91C_UDP_EP2 ((unsigned int) 0x1 << 2) // (UDP) Reset Endpoint 2 -#define AT91C_UDP_EP3 ((unsigned int) 0x1 << 3) // (UDP) Reset Endpoint 3 -#define AT91C_UDP_EP4 ((unsigned int) 0x1 << 4) // (UDP) Reset Endpoint 4 -#define AT91C_UDP_EP5 ((unsigned int) 0x1 << 5) // (UDP) Reset Endpoint 5 -// -------- UDP_CSR : (UDP Offset: 0x30) USB Endpoint Control and Status Register -------- -#define AT91C_UDP_TXCOMP ((unsigned int) 0x1 << 0) // (UDP) Generates an IN packet with data previously written in the DPR -#define AT91C_UDP_RX_DATA_BK0 ((unsigned int) 0x1 << 1) // (UDP) Receive Data Bank 0 -#define AT91C_UDP_RXSETUP ((unsigned int) 0x1 << 2) // (UDP) Sends STALL to the Host (Control endpoints) -#define AT91C_UDP_ISOERROR ((unsigned int) 0x1 << 3) // (UDP) Isochronous error (Isochronous endpoints) -#define AT91C_UDP_TXPKTRDY ((unsigned int) 0x1 << 4) // (UDP) Transmit Packet Ready -#define AT91C_UDP_FORCESTALL ((unsigned int) 0x1 << 5) // (UDP) Force Stall (used by Control, Bulk and Isochronous endpoints). -#define AT91C_UDP_RX_DATA_BK1 ((unsigned int) 0x1 << 6) // (UDP) Receive Data Bank 1 (only used by endpoints with ping-pong attributes). -#define AT91C_UDP_DIR ((unsigned int) 0x1 << 7) // (UDP) Transfer Direction -#define AT91C_UDP_EPTYPE ((unsigned int) 0x7 << 8) // (UDP) Endpoint type -#define AT91C_UDP_EPTYPE_CTRL ((unsigned int) 0x0 << 8) // (UDP) Control -#define AT91C_UDP_EPTYPE_ISO_OUT ((unsigned int) 0x1 << 8) // (UDP) Isochronous OUT -#define AT91C_UDP_EPTYPE_BULK_OUT ((unsigned int) 0x2 << 8) // (UDP) Bulk OUT -#define AT91C_UDP_EPTYPE_INT_OUT ((unsigned int) 0x3 << 8) // (UDP) Interrupt OUT -#define AT91C_UDP_EPTYPE_ISO_IN ((unsigned int) 0x5 << 8) // (UDP) Isochronous IN -#define AT91C_UDP_EPTYPE_BULK_IN ((unsigned int) 0x6 << 8) // (UDP) Bulk IN -#define AT91C_UDP_EPTYPE_INT_IN ((unsigned int) 0x7 << 8) // (UDP) Interrupt IN -#define AT91C_UDP_DTGLE ((unsigned int) 0x1 << 11) // (UDP) Data Toggle -#define AT91C_UDP_EPEDS ((unsigned int) 0x1 << 15) // (UDP) Endpoint Enable Disable -#define AT91C_UDP_RXBYTECNT ((unsigned int) 0x7FF << 16) // (UDP) Number Of Bytes Available in the FIFO -// -------- UDP_TXVC : (UDP Offset: 0x74) Transceiver Control Register -------- -#define AT91C_UDP_TXVDIS ((unsigned int) 0x1 << 8) // (UDP) -#define AT91C_UDP_PUON ((unsigned int) 0x1 << 9) // (UDP) Pull-up ON - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Timer Counter Channel Interface -// ***************************************************************************** -typedef struct _AT91S_TC { - AT91_REG TC_CCR; // Channel Control Register - AT91_REG TC_CMR; // Channel Mode Register (Capture Mode / Waveform Mode) - AT91_REG Reserved0[2]; // - AT91_REG TC_CV; // Counter Value - AT91_REG TC_RA; // Register A - AT91_REG TC_RB; // Register B - AT91_REG TC_RC; // Register C - AT91_REG TC_SR; // Status Register - AT91_REG TC_IER; // Interrupt Enable Register - AT91_REG TC_IDR; // Interrupt Disable Register - AT91_REG TC_IMR; // Interrupt Mask Register -} AT91S_TC, *AT91PS_TC; - -// -------- TC_CCR : (TC Offset: 0x0) TC Channel Control Register -------- -#define AT91C_TC_CLKEN ((unsigned int) 0x1 << 0) // (TC) Counter Clock Enable Command -#define AT91C_TC_CLKDIS ((unsigned int) 0x1 << 1) // (TC) Counter Clock Disable Command -#define AT91C_TC_SWTRG ((unsigned int) 0x1 << 2) // (TC) Software Trigger Command -// -------- TC_CMR : (TC Offset: 0x4) TC Channel Mode Register: Capture Mode / Waveform Mode -------- -#define AT91C_TC_CLKS ((unsigned int) 0x7 << 0) // (TC) Clock Selection -#define AT91C_TC_CLKS_TIMER_DIV1_CLOCK ((unsigned int) 0x0) // (TC) Clock selected: TIMER_DIV1_CLOCK -#define AT91C_TC_CLKS_TIMER_DIV2_CLOCK ((unsigned int) 0x1) // (TC) Clock selected: TIMER_DIV2_CLOCK -#define AT91C_TC_CLKS_TIMER_DIV3_CLOCK ((unsigned int) 0x2) // (TC) Clock selected: TIMER_DIV3_CLOCK -#define AT91C_TC_CLKS_TIMER_DIV4_CLOCK ((unsigned int) 0x3) // (TC) Clock selected: TIMER_DIV4_CLOCK -#define AT91C_TC_CLKS_TIMER_DIV5_CLOCK ((unsigned int) 0x4) // (TC) Clock selected: TIMER_DIV5_CLOCK -#define AT91C_TC_CLKS_XC0 ((unsigned int) 0x5) // (TC) Clock selected: XC0 -#define AT91C_TC_CLKS_XC1 ((unsigned int) 0x6) // (TC) Clock selected: XC1 -#define AT91C_TC_CLKS_XC2 ((unsigned int) 0x7) // (TC) Clock selected: XC2 -#define AT91C_TC_CLKI ((unsigned int) 0x1 << 3) // (TC) Clock Invert -#define AT91C_TC_BURST ((unsigned int) 0x3 << 4) // (TC) Burst Signal Selection -#define AT91C_TC_BURST_NONE ((unsigned int) 0x0 << 4) // (TC) The clock is not gated by an external signal -#define AT91C_TC_BURST_XC0 ((unsigned int) 0x1 << 4) // (TC) XC0 is ANDed with the selected clock -#define AT91C_TC_BURST_XC1 ((unsigned int) 0x2 << 4) // (TC) XC1 is ANDed with the selected clock -#define AT91C_TC_BURST_XC2 ((unsigned int) 0x3 << 4) // (TC) XC2 is ANDed with the selected clock -#define AT91C_TC_CPCSTOP ((unsigned int) 0x1 << 6) // (TC) Counter Clock Stopped with RC Compare -#define AT91C_TC_LDBSTOP ((unsigned int) 0x1 << 6) // (TC) Counter Clock Stopped with RB Loading -#define AT91C_TC_CPCDIS ((unsigned int) 0x1 << 7) // (TC) Counter Clock Disable with RC Compare -#define AT91C_TC_LDBDIS ((unsigned int) 0x1 << 7) // (TC) Counter Clock Disabled with RB Loading -#define AT91C_TC_ETRGEDG ((unsigned int) 0x3 << 8) // (TC) External Trigger Edge Selection -#define AT91C_TC_ETRGEDG_NONE ((unsigned int) 0x0 << 8) // (TC) Edge: None -#define AT91C_TC_ETRGEDG_RISING ((unsigned int) 0x1 << 8) // (TC) Edge: rising edge -#define AT91C_TC_ETRGEDG_FALLING ((unsigned int) 0x2 << 8) // (TC) Edge: falling edge -#define AT91C_TC_ETRGEDG_BOTH ((unsigned int) 0x3 << 8) // (TC) Edge: each edge -#define AT91C_TC_EEVTEDG ((unsigned int) 0x3 << 8) // (TC) External Event Edge Selection -#define AT91C_TC_EEVTEDG_NONE ((unsigned int) 0x0 << 8) // (TC) Edge: None -#define AT91C_TC_EEVTEDG_RISING ((unsigned int) 0x1 << 8) // (TC) Edge: rising edge -#define AT91C_TC_EEVTEDG_FALLING ((unsigned int) 0x2 << 8) // (TC) Edge: falling edge -#define AT91C_TC_EEVTEDG_BOTH ((unsigned int) 0x3 << 8) // (TC) Edge: each edge -#define AT91C_TC_EEVT ((unsigned int) 0x3 << 10) // (TC) External Event Selection -#define AT91C_TC_EEVT_TIOB ((unsigned int) 0x0 << 10) // (TC) Signal selected as external event: TIOB TIOB direction: input -#define AT91C_TC_EEVT_XC0 ((unsigned int) 0x1 << 10) // (TC) Signal selected as external event: XC0 TIOB direction: output -#define AT91C_TC_EEVT_XC1 ((unsigned int) 0x2 << 10) // (TC) Signal selected as external event: XC1 TIOB direction: output -#define AT91C_TC_EEVT_XC2 ((unsigned int) 0x3 << 10) // (TC) Signal selected as external event: XC2 TIOB direction: output -#define AT91C_TC_ABETRG ((unsigned int) 0x1 << 10) // (TC) TIOA or TIOB External Trigger Selection -#define AT91C_TC_ENETRG ((unsigned int) 0x1 << 12) // (TC) External Event Trigger enable -#define AT91C_TC_WAVESEL ((unsigned int) 0x3 << 13) // (TC) Waveform Selection -#define AT91C_TC_WAVESEL_UP ((unsigned int) 0x0 << 13) // (TC) UP mode without atomatic trigger on RC Compare -#define AT91C_TC_WAVESEL_UPDOWN ((unsigned int) 0x1 << 13) // (TC) UPDOWN mode without automatic trigger on RC Compare -#define AT91C_TC_WAVESEL_UP_AUTO ((unsigned int) 0x2 << 13) // (TC) UP mode with automatic trigger on RC Compare -#define AT91C_TC_WAVESEL_UPDOWN_AUTO ((unsigned int) 0x3 << 13) // (TC) UPDOWN mode with automatic trigger on RC Compare -#define AT91C_TC_CPCTRG ((unsigned int) 0x1 << 14) // (TC) RC Compare Trigger Enable -#define AT91C_TC_WAVE ((unsigned int) 0x1 << 15) // (TC) -#define AT91C_TC_ACPA ((unsigned int) 0x3 << 16) // (TC) RA Compare Effect on TIOA -#define AT91C_TC_ACPA_NONE ((unsigned int) 0x0 << 16) // (TC) Effect: none -#define AT91C_TC_ACPA_SET ((unsigned int) 0x1 << 16) // (TC) Effect: set -#define AT91C_TC_ACPA_CLEAR ((unsigned int) 0x2 << 16) // (TC) Effect: clear -#define AT91C_TC_ACPA_TOGGLE ((unsigned int) 0x3 << 16) // (TC) Effect: toggle -#define AT91C_TC_LDRA ((unsigned int) 0x3 << 16) // (TC) RA Loading Selection -#define AT91C_TC_LDRA_NONE ((unsigned int) 0x0 << 16) // (TC) Edge: None -#define AT91C_TC_LDRA_RISING ((unsigned int) 0x1 << 16) // (TC) Edge: rising edge of TIOA -#define AT91C_TC_LDRA_FALLING ((unsigned int) 0x2 << 16) // (TC) Edge: falling edge of TIOA -#define AT91C_TC_LDRA_BOTH ((unsigned int) 0x3 << 16) // (TC) Edge: each edge of TIOA -#define AT91C_TC_ACPC ((unsigned int) 0x3 << 18) // (TC) RC Compare Effect on TIOA -#define AT91C_TC_ACPC_NONE ((unsigned int) 0x0 << 18) // (TC) Effect: none -#define AT91C_TC_ACPC_SET ((unsigned int) 0x1 << 18) // (TC) Effect: set -#define AT91C_TC_ACPC_CLEAR ((unsigned int) 0x2 << 18) // (TC) Effect: clear -#define AT91C_TC_ACPC_TOGGLE ((unsigned int) 0x3 << 18) // (TC) Effect: toggle -#define AT91C_TC_LDRB ((unsigned int) 0x3 << 18) // (TC) RB Loading Selection -#define AT91C_TC_LDRB_NONE ((unsigned int) 0x0 << 18) // (TC) Edge: None -#define AT91C_TC_LDRB_RISING ((unsigned int) 0x1 << 18) // (TC) Edge: rising edge of TIOA -#define AT91C_TC_LDRB_FALLING ((unsigned int) 0x2 << 18) // (TC) Edge: falling edge of TIOA -#define AT91C_TC_LDRB_BOTH ((unsigned int) 0x3 << 18) // (TC) Edge: each edge of TIOA -#define AT91C_TC_AEEVT ((unsigned int) 0x3 << 20) // (TC) External Event Effect on TIOA -#define AT91C_TC_AEEVT_NONE ((unsigned int) 0x0 << 20) // (TC) Effect: none -#define AT91C_TC_AEEVT_SET ((unsigned int) 0x1 << 20) // (TC) Effect: set -#define AT91C_TC_AEEVT_CLEAR ((unsigned int) 0x2 << 20) // (TC) Effect: clear -#define AT91C_TC_AEEVT_TOGGLE ((unsigned int) 0x3 << 20) // (TC) Effect: toggle -#define AT91C_TC_ASWTRG ((unsigned int) 0x3 << 22) // (TC) Software Trigger Effect on TIOA -#define AT91C_TC_ASWTRG_NONE ((unsigned int) 0x0 << 22) // (TC) Effect: none -#define AT91C_TC_ASWTRG_SET ((unsigned int) 0x1 << 22) // (TC) Effect: set -#define AT91C_TC_ASWTRG_CLEAR ((unsigned int) 0x2 << 22) // (TC) Effect: clear -#define AT91C_TC_ASWTRG_TOGGLE ((unsigned int) 0x3 << 22) // (TC) Effect: toggle -#define AT91C_TC_BCPB ((unsigned int) 0x3 << 24) // (TC) RB Compare Effect on TIOB -#define AT91C_TC_BCPB_NONE ((unsigned int) 0x0 << 24) // (TC) Effect: none -#define AT91C_TC_BCPB_SET ((unsigned int) 0x1 << 24) // (TC) Effect: set -#define AT91C_TC_BCPB_CLEAR ((unsigned int) 0x2 << 24) // (TC) Effect: clear -#define AT91C_TC_BCPB_TOGGLE ((unsigned int) 0x3 << 24) // (TC) Effect: toggle -#define AT91C_TC_BCPC ((unsigned int) 0x3 << 26) // (TC) RC Compare Effect on TIOB -#define AT91C_TC_BCPC_NONE ((unsigned int) 0x0 << 26) // (TC) Effect: none -#define AT91C_TC_BCPC_SET ((unsigned int) 0x1 << 26) // (TC) Effect: set -#define AT91C_TC_BCPC_CLEAR ((unsigned int) 0x2 << 26) // (TC) Effect: clear -#define AT91C_TC_BCPC_TOGGLE ((unsigned int) 0x3 << 26) // (TC) Effect: toggle -#define AT91C_TC_BEEVT ((unsigned int) 0x3 << 28) // (TC) External Event Effect on TIOB -#define AT91C_TC_BEEVT_NONE ((unsigned int) 0x0 << 28) // (TC) Effect: none -#define AT91C_TC_BEEVT_SET ((unsigned int) 0x1 << 28) // (TC) Effect: set -#define AT91C_TC_BEEVT_CLEAR ((unsigned int) 0x2 << 28) // (TC) Effect: clear -#define AT91C_TC_BEEVT_TOGGLE ((unsigned int) 0x3 << 28) // (TC) Effect: toggle -#define AT91C_TC_BSWTRG ((unsigned int) 0x3 << 30) // (TC) Software Trigger Effect on TIOB -#define AT91C_TC_BSWTRG_NONE ((unsigned int) 0x0 << 30) // (TC) Effect: none -#define AT91C_TC_BSWTRG_SET ((unsigned int) 0x1 << 30) // (TC) Effect: set -#define AT91C_TC_BSWTRG_CLEAR ((unsigned int) 0x2 << 30) // (TC) Effect: clear -#define AT91C_TC_BSWTRG_TOGGLE ((unsigned int) 0x3 << 30) // (TC) Effect: toggle -// -------- TC_SR : (TC Offset: 0x20) TC Channel Status Register -------- -#define AT91C_TC_COVFS ((unsigned int) 0x1 << 0) // (TC) Counter Overflow -#define AT91C_TC_LOVRS ((unsigned int) 0x1 << 1) // (TC) Load Overrun -#define AT91C_TC_CPAS ((unsigned int) 0x1 << 2) // (TC) RA Compare -#define AT91C_TC_CPBS ((unsigned int) 0x1 << 3) // (TC) RB Compare -#define AT91C_TC_CPCS ((unsigned int) 0x1 << 4) // (TC) RC Compare -#define AT91C_TC_LDRAS ((unsigned int) 0x1 << 5) // (TC) RA Loading -#define AT91C_TC_LDRBS ((unsigned int) 0x1 << 6) // (TC) RB Loading -#define AT91C_TC_ETRGS ((unsigned int) 0x1 << 7) // (TC) External Trigger -#define AT91C_TC_CLKSTA ((unsigned int) 0x1 << 16) // (TC) Clock Enabling -#define AT91C_TC_MTIOA ((unsigned int) 0x1 << 17) // (TC) TIOA Mirror -#define AT91C_TC_MTIOB ((unsigned int) 0x1 << 18) // (TC) TIOA Mirror -// -------- TC_IER : (TC Offset: 0x24) TC Channel Interrupt Enable Register -------- -// -------- TC_IDR : (TC Offset: 0x28) TC Channel Interrupt Disable Register -------- -// -------- TC_IMR : (TC Offset: 0x2c) TC Channel Interrupt Mask Register -------- - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Timer Counter Interface -// ***************************************************************************** -typedef struct _AT91S_TCB { - AT91S_TC TCB_TC0; // TC Channel 0 - AT91_REG Reserved0[4]; // - AT91S_TC TCB_TC1; // TC Channel 1 - AT91_REG Reserved1[4]; // - AT91S_TC TCB_TC2; // TC Channel 2 - AT91_REG Reserved2[4]; // - AT91_REG TCB_BCR; // TC Block Control Register - AT91_REG TCB_BMR; // TC Block Mode Register -} AT91S_TCB, *AT91PS_TCB; - -// -------- TCB_BCR : (TCB Offset: 0xc0) TC Block Control Register -------- -#define AT91C_TCB_SYNC ((unsigned int) 0x1 << 0) // (TCB) Synchro Command -// -------- TCB_BMR : (TCB Offset: 0xc4) TC Block Mode Register -------- -#define AT91C_TCB_TC0XC0S ((unsigned int) 0x3 << 0) // (TCB) External Clock Signal 0 Selection -#define AT91C_TCB_TC0XC0S_TCLK0 ((unsigned int) 0x0) // (TCB) TCLK0 connected to XC0 -#define AT91C_TCB_TC0XC0S_NONE ((unsigned int) 0x1) // (TCB) None signal connected to XC0 -#define AT91C_TCB_TC0XC0S_TIOA1 ((unsigned int) 0x2) // (TCB) TIOA1 connected to XC0 -#define AT91C_TCB_TC0XC0S_TIOA2 ((unsigned int) 0x3) // (TCB) TIOA2 connected to XC0 -#define AT91C_TCB_TC1XC1S ((unsigned int) 0x3 << 2) // (TCB) External Clock Signal 1 Selection -#define AT91C_TCB_TC1XC1S_TCLK1 ((unsigned int) 0x0 << 2) // (TCB) TCLK1 connected to XC1 -#define AT91C_TCB_TC1XC1S_NONE ((unsigned int) 0x1 << 2) // (TCB) None signal connected to XC1 -#define AT91C_TCB_TC1XC1S_TIOA0 ((unsigned int) 0x2 << 2) // (TCB) TIOA0 connected to XC1 -#define AT91C_TCB_TC1XC1S_TIOA2 ((unsigned int) 0x3 << 2) // (TCB) TIOA2 connected to XC1 -#define AT91C_TCB_TC2XC2S ((unsigned int) 0x3 << 4) // (TCB) External Clock Signal 2 Selection -#define AT91C_TCB_TC2XC2S_TCLK2 ((unsigned int) 0x0 << 4) // (TCB) TCLK2 connected to XC2 -#define AT91C_TCB_TC2XC2S_NONE ((unsigned int) 0x1 << 4) // (TCB) None signal connected to XC2 -#define AT91C_TCB_TC2XC2S_TIOA0 ((unsigned int) 0x2 << 4) // (TCB) TIOA0 connected to XC2 -#define AT91C_TCB_TC2XC2S_TIOA1 ((unsigned int) 0x3 << 4) // (TCB) TIOA2 connected to XC2 - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Control Area Network MailBox Interface -// ***************************************************************************** -typedef struct _AT91S_CAN_MB { - AT91_REG CAN_MB_MMR; // MailBox Mode Register - AT91_REG CAN_MB_MAM; // MailBox Acceptance Mask Register - AT91_REG CAN_MB_MID; // MailBox ID Register - AT91_REG CAN_MB_MFID; // MailBox Family ID Register - AT91_REG CAN_MB_MSR; // MailBox Status Register - AT91_REG CAN_MB_MDL; // MailBox Data Low Register - AT91_REG CAN_MB_MDH; // MailBox Data High Register - AT91_REG CAN_MB_MCR; // MailBox Control Register -} AT91S_CAN_MB, *AT91PS_CAN_MB; - -// -------- CAN_MMR : (CAN_MB Offset: 0x0) CAN Message Mode Register -------- -#define AT91C_CAN_MTIMEMARK ((unsigned int) 0xFFFF << 0) // (CAN_MB) Mailbox Timemark -#define AT91C_CAN_PRIOR ((unsigned int) 0xF << 16) // (CAN_MB) Mailbox Priority -#define AT91C_CAN_MOT ((unsigned int) 0x7 << 24) // (CAN_MB) Mailbox Object Type -#define AT91C_CAN_MOT_DIS ((unsigned int) 0x0 << 24) // (CAN_MB) -#define AT91C_CAN_MOT_RX ((unsigned int) 0x1 << 24) // (CAN_MB) -#define AT91C_CAN_MOT_RXOVERWRITE ((unsigned int) 0x2 << 24) // (CAN_MB) -#define AT91C_CAN_MOT_TX ((unsigned int) 0x3 << 24) // (CAN_MB) -#define AT91C_CAN_MOT_CONSUMER ((unsigned int) 0x4 << 24) // (CAN_MB) -#define AT91C_CAN_MOT_PRODUCER ((unsigned int) 0x5 << 24) // (CAN_MB) -// -------- CAN_MAM : (CAN_MB Offset: 0x4) CAN Message Acceptance Mask Register -------- -#define AT91C_CAN_MIDvB ((unsigned int) 0x3FFFF << 0) // (CAN_MB) Complementary bits for identifier in extended mode -#define AT91C_CAN_MIDvA ((unsigned int) 0x7FF << 18) // (CAN_MB) Identifier for standard frame mode -#define AT91C_CAN_MIDE ((unsigned int) 0x1 << 29) // (CAN_MB) Identifier Version -// -------- CAN_MID : (CAN_MB Offset: 0x8) CAN Message ID Register -------- -// -------- CAN_MFID : (CAN_MB Offset: 0xc) CAN Message Family ID Register -------- -// -------- CAN_MSR : (CAN_MB Offset: 0x10) CAN Message Status Register -------- -#define AT91C_CAN_MTIMESTAMP ((unsigned int) 0xFFFF << 0) // (CAN_MB) Timer Value -#define AT91C_CAN_MDLC ((unsigned int) 0xF << 16) // (CAN_MB) Mailbox Data Length Code -#define AT91C_CAN_MRTR ((unsigned int) 0x1 << 20) // (CAN_MB) Mailbox Remote Transmission Request -#define AT91C_CAN_MABT ((unsigned int) 0x1 << 22) // (CAN_MB) Mailbox Message Abort -#define AT91C_CAN_MRDY ((unsigned int) 0x1 << 23) // (CAN_MB) Mailbox Ready -#define AT91C_CAN_MMI ((unsigned int) 0x1 << 24) // (CAN_MB) Mailbox Message Ignored -// -------- CAN_MDL : (CAN_MB Offset: 0x14) CAN Message Data Low Register -------- -// -------- CAN_MDH : (CAN_MB Offset: 0x18) CAN Message Data High Register -------- -// -------- CAN_MCR : (CAN_MB Offset: 0x1c) CAN Message Control Register -------- -#define AT91C_CAN_MACR ((unsigned int) 0x1 << 22) // (CAN_MB) Abort Request for Mailbox -#define AT91C_CAN_MTCR ((unsigned int) 0x1 << 23) // (CAN_MB) Mailbox Transfer Command - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Control Area Network Interface -// ***************************************************************************** -typedef struct _AT91S_CAN { - AT91_REG CAN_MR; // Mode Register - AT91_REG CAN_IER; // Interrupt Enable Register - AT91_REG CAN_IDR; // Interrupt Disable Register - AT91_REG CAN_IMR; // Interrupt Mask Register - AT91_REG CAN_SR; // Status Register - AT91_REG CAN_BR; // Baudrate Register - AT91_REG CAN_TIM; // Timer Register - AT91_REG CAN_TIMESTP; // Time Stamp Register - AT91_REG CAN_ECR; // Error Counter Register - AT91_REG CAN_TCR; // Transfer Command Register - AT91_REG CAN_ACR; // Abort Command Register - AT91_REG Reserved0[52]; // - AT91_REG CAN_VR; // Version Register - AT91_REG Reserved1[64]; // - AT91S_CAN_MB CAN_MB0; // CAN Mailbox 0 - AT91S_CAN_MB CAN_MB1; // CAN Mailbox 1 - AT91S_CAN_MB CAN_MB2; // CAN Mailbox 2 - AT91S_CAN_MB CAN_MB3; // CAN Mailbox 3 - AT91S_CAN_MB CAN_MB4; // CAN Mailbox 4 - AT91S_CAN_MB CAN_MB5; // CAN Mailbox 5 - AT91S_CAN_MB CAN_MB6; // CAN Mailbox 6 - AT91S_CAN_MB CAN_MB7; // CAN Mailbox 7 - AT91S_CAN_MB CAN_MB8; // CAN Mailbox 8 - AT91S_CAN_MB CAN_MB9; // CAN Mailbox 9 - AT91S_CAN_MB CAN_MB10; // CAN Mailbox 10 - AT91S_CAN_MB CAN_MB11; // CAN Mailbox 11 - AT91S_CAN_MB CAN_MB12; // CAN Mailbox 12 - AT91S_CAN_MB CAN_MB13; // CAN Mailbox 13 - AT91S_CAN_MB CAN_MB14; // CAN Mailbox 14 - AT91S_CAN_MB CAN_MB15; // CAN Mailbox 15 -} AT91S_CAN, *AT91PS_CAN; - -// -------- CAN_MR : (CAN Offset: 0x0) CAN Mode Register -------- -#define AT91C_CAN_CANEN ((unsigned int) 0x1 << 0) // (CAN) CAN Controller Enable -#define AT91C_CAN_LPM ((unsigned int) 0x1 << 1) // (CAN) Disable/Enable Low Power Mode -#define AT91C_CAN_ABM ((unsigned int) 0x1 << 2) // (CAN) Disable/Enable Autobaud/Listen Mode -#define AT91C_CAN_OVL ((unsigned int) 0x1 << 3) // (CAN) Disable/Enable Overload Frame -#define AT91C_CAN_TEOF ((unsigned int) 0x1 << 4) // (CAN) Time Stamp messages at each end of Frame -#define AT91C_CAN_TTM ((unsigned int) 0x1 << 5) // (CAN) Disable/Enable Time Trigger Mode -#define AT91C_CAN_TIMFRZ ((unsigned int) 0x1 << 6) // (CAN) Enable Timer Freeze -#define AT91C_CAN_DRPT ((unsigned int) 0x1 << 7) // (CAN) Disable Repeat -// -------- CAN_IER : (CAN Offset: 0x4) CAN Interrupt Enable Register -------- -#define AT91C_CAN_MB0 ((unsigned int) 0x1 << 0) // (CAN) Mailbox 0 Flag -#define AT91C_CAN_MB1 ((unsigned int) 0x1 << 1) // (CAN) Mailbox 1 Flag -#define AT91C_CAN_MB2 ((unsigned int) 0x1 << 2) // (CAN) Mailbox 2 Flag -#define AT91C_CAN_MB3 ((unsigned int) 0x1 << 3) // (CAN) Mailbox 3 Flag -#define AT91C_CAN_MB4 ((unsigned int) 0x1 << 4) // (CAN) Mailbox 4 Flag -#define AT91C_CAN_MB5 ((unsigned int) 0x1 << 5) // (CAN) Mailbox 5 Flag -#define AT91C_CAN_MB6 ((unsigned int) 0x1 << 6) // (CAN) Mailbox 6 Flag -#define AT91C_CAN_MB7 ((unsigned int) 0x1 << 7) // (CAN) Mailbox 7 Flag -#define AT91C_CAN_MB8 ((unsigned int) 0x1 << 8) // (CAN) Mailbox 8 Flag -#define AT91C_CAN_MB9 ((unsigned int) 0x1 << 9) // (CAN) Mailbox 9 Flag -#define AT91C_CAN_MB10 ((unsigned int) 0x1 << 10) // (CAN) Mailbox 10 Flag -#define AT91C_CAN_MB11 ((unsigned int) 0x1 << 11) // (CAN) Mailbox 11 Flag -#define AT91C_CAN_MB12 ((unsigned int) 0x1 << 12) // (CAN) Mailbox 12 Flag -#define AT91C_CAN_MB13 ((unsigned int) 0x1 << 13) // (CAN) Mailbox 13 Flag -#define AT91C_CAN_MB14 ((unsigned int) 0x1 << 14) // (CAN) Mailbox 14 Flag -#define AT91C_CAN_MB15 ((unsigned int) 0x1 << 15) // (CAN) Mailbox 15 Flag -#define AT91C_CAN_ERRA ((unsigned int) 0x1 << 16) // (CAN) Error Active Mode Flag -#define AT91C_CAN_WARN ((unsigned int) 0x1 << 17) // (CAN) Warning Limit Flag -#define AT91C_CAN_ERRP ((unsigned int) 0x1 << 18) // (CAN) Error Passive Mode Flag -#define AT91C_CAN_BOFF ((unsigned int) 0x1 << 19) // (CAN) Bus Off Mode Flag -#define AT91C_CAN_SLEEP ((unsigned int) 0x1 << 20) // (CAN) Sleep Flag -#define AT91C_CAN_WAKEUP ((unsigned int) 0x1 << 21) // (CAN) Wakeup Flag -#define AT91C_CAN_TOVF ((unsigned int) 0x1 << 22) // (CAN) Timer Overflow Flag -#define AT91C_CAN_TSTP ((unsigned int) 0x1 << 23) // (CAN) Timestamp Flag -#define AT91C_CAN_CERR ((unsigned int) 0x1 << 24) // (CAN) CRC Error -#define AT91C_CAN_SERR ((unsigned int) 0x1 << 25) // (CAN) Stuffing Error -#define AT91C_CAN_AERR ((unsigned int) 0x1 << 26) // (CAN) Acknowledgment Error -#define AT91C_CAN_FERR ((unsigned int) 0x1 << 27) // (CAN) Form Error -#define AT91C_CAN_BERR ((unsigned int) 0x1 << 28) // (CAN) Bit Error -// -------- CAN_IDR : (CAN Offset: 0x8) CAN Interrupt Disable Register -------- -// -------- CAN_IMR : (CAN Offset: 0xc) CAN Interrupt Mask Register -------- -// -------- CAN_SR : (CAN Offset: 0x10) CAN Status Register -------- -#define AT91C_CAN_RBSY ((unsigned int) 0x1 << 29) // (CAN) Receiver Busy -#define AT91C_CAN_TBSY ((unsigned int) 0x1 << 30) // (CAN) Transmitter Busy -#define AT91C_CAN_OVLY ((unsigned int) 0x1 << 31) // (CAN) Overload Busy -// -------- CAN_BR : (CAN Offset: 0x14) CAN Baudrate Register -------- -#define AT91C_CAN_PHASE2 ((unsigned int) 0x7 << 0) // (CAN) Phase 2 segment -#define AT91C_CAN_PHASE1 ((unsigned int) 0x7 << 4) // (CAN) Phase 1 segment -#define AT91C_CAN_PROPAG ((unsigned int) 0x7 << 8) // (CAN) Programmation time segment -#define AT91C_CAN_SYNC ((unsigned int) 0x3 << 12) // (CAN) Re-synchronization jump width segment -#define AT91C_CAN_BRP ((unsigned int) 0x7F << 16) // (CAN) Baudrate Prescaler -#define AT91C_CAN_SMP ((unsigned int) 0x1 << 24) // (CAN) Sampling mode -// -------- CAN_TIM : (CAN Offset: 0x18) CAN Timer Register -------- -#define AT91C_CAN_TIMER ((unsigned int) 0xFFFF << 0) // (CAN) Timer field -// -------- CAN_TIMESTP : (CAN Offset: 0x1c) CAN Timestamp Register -------- -// -------- CAN_ECR : (CAN Offset: 0x20) CAN Error Counter Register -------- -#define AT91C_CAN_REC ((unsigned int) 0xFF << 0) // (CAN) Receive Error Counter -#define AT91C_CAN_TEC ((unsigned int) 0xFF << 16) // (CAN) Transmit Error Counter -// -------- CAN_TCR : (CAN Offset: 0x24) CAN Transfer Command Register -------- -#define AT91C_CAN_TIMRST ((unsigned int) 0x1 << 31) // (CAN) Timer Reset Field -// -------- CAN_ACR : (CAN Offset: 0x28) CAN Abort Command Register -------- - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Ethernet MAC 10/100 -// ***************************************************************************** -typedef struct _AT91S_EMAC { - AT91_REG EMAC_NCR; // Network Control Register - AT91_REG EMAC_NCFGR; // Network Configuration Register - AT91_REG EMAC_NSR; // Network Status Register - AT91_REG Reserved0[2]; // - AT91_REG EMAC_TSR; // Transmit Status Register - AT91_REG EMAC_RBQP; // Receive Buffer Queue Pointer - AT91_REG EMAC_TBQP; // Transmit Buffer Queue Pointer - AT91_REG EMAC_RSR; // Receive Status Register - AT91_REG EMAC_ISR; // Interrupt Status Register - AT91_REG EMAC_IER; // Interrupt Enable Register - AT91_REG EMAC_IDR; // Interrupt Disable Register - AT91_REG EMAC_IMR; // Interrupt Mask Register - AT91_REG EMAC_MAN; // PHY Maintenance Register - AT91_REG EMAC_PTR; // Pause Time Register - AT91_REG EMAC_PFR; // Pause Frames received Register - AT91_REG EMAC_FTO; // Frames Transmitted OK Register - AT91_REG EMAC_SCF; // Single Collision Frame Register - AT91_REG EMAC_MCF; // Multiple Collision Frame Register - AT91_REG EMAC_FRO; // Frames Received OK Register - AT91_REG EMAC_FCSE; // Frame Check Sequence Error Register - AT91_REG EMAC_ALE; // Alignment Error Register - AT91_REG EMAC_DTF; // Deferred Transmission Frame Register - AT91_REG EMAC_LCOL; // Late Collision Register - AT91_REG EMAC_ECOL; // Excessive Collision Register - AT91_REG EMAC_TUND; // Transmit Underrun Error Register - AT91_REG EMAC_CSE; // Carrier Sense Error Register - AT91_REG EMAC_RRE; // Receive Ressource Error Register - AT91_REG EMAC_ROV; // Receive Overrun Errors Register - AT91_REG EMAC_RSE; // Receive Symbol Errors Register - AT91_REG EMAC_ELE; // Excessive Length Errors Register - AT91_REG EMAC_RJA; // Receive Jabbers Register - AT91_REG EMAC_USF; // Undersize Frames Register - AT91_REG EMAC_STE; // SQE Test Error Register - AT91_REG EMAC_RLE; // Receive Length Field Mismatch Register - AT91_REG EMAC_TPF; // Transmitted Pause Frames Register - AT91_REG EMAC_HRB; // Hash Address Bottom[31:0] - AT91_REG EMAC_HRT; // Hash Address Top[63:32] - AT91_REG EMAC_SA1L; // Specific Address 1 Bottom, First 4 bytes - AT91_REG EMAC_SA1H; // Specific Address 1 Top, Last 2 bytes - AT91_REG EMAC_SA2L; // Specific Address 2 Bottom, First 4 bytes - AT91_REG EMAC_SA2H; // Specific Address 2 Top, Last 2 bytes - AT91_REG EMAC_SA3L; // Specific Address 3 Bottom, First 4 bytes - AT91_REG EMAC_SA3H; // Specific Address 3 Top, Last 2 bytes - AT91_REG EMAC_SA4L; // Specific Address 4 Bottom, First 4 bytes - AT91_REG EMAC_SA4H; // Specific Address 4 Top, Last 2 bytes - AT91_REG EMAC_TID; // Type ID Checking Register - AT91_REG EMAC_TPQ; // Transmit Pause Quantum Register - AT91_REG EMAC_USRIO; // USER Input/Output Register - AT91_REG EMAC_WOL; // Wake On LAN Register - AT91_REG Reserved1[13]; // - AT91_REG EMAC_REV; // Revision Register -} AT91S_EMAC, *AT91PS_EMAC; - -// -------- EMAC_NCR : (EMAC Offset: 0x0) -------- -#define AT91C_EMAC_LB ((unsigned int) 0x1 << 0) // (EMAC) Loopback. Optional. When set, loopback signal is at high level. -#define AT91C_EMAC_LLB ((unsigned int) 0x1 << 1) // (EMAC) Loopback local. -#define AT91C_EMAC_RE ((unsigned int) 0x1 << 2) // (EMAC) Receive enable. -#define AT91C_EMAC_TE ((unsigned int) 0x1 << 3) // (EMAC) Transmit enable. -#define AT91C_EMAC_MPE ((unsigned int) 0x1 << 4) // (EMAC) Management port enable. -#define AT91C_EMAC_CLRSTAT ((unsigned int) 0x1 << 5) // (EMAC) Clear statistics registers. -#define AT91C_EMAC_INCSTAT ((unsigned int) 0x1 << 6) // (EMAC) Increment statistics registers. -#define AT91C_EMAC_WESTAT ((unsigned int) 0x1 << 7) // (EMAC) Write enable for statistics registers. -#define AT91C_EMAC_BP ((unsigned int) 0x1 << 8) // (EMAC) Back pressure. -#define AT91C_EMAC_TSTART ((unsigned int) 0x1 << 9) // (EMAC) Start Transmission. -#define AT91C_EMAC_THALT ((unsigned int) 0x1 << 10) // (EMAC) Transmission Halt. -#define AT91C_EMAC_TPFR ((unsigned int) 0x1 << 11) // (EMAC) Transmit pause frame -#define AT91C_EMAC_TZQ ((unsigned int) 0x1 << 12) // (EMAC) Transmit zero quantum pause frame -// -------- EMAC_NCFGR : (EMAC Offset: 0x4) Network Configuration Register -------- -#define AT91C_EMAC_SPD ((unsigned int) 0x1 << 0) // (EMAC) Speed. -#define AT91C_EMAC_FD ((unsigned int) 0x1 << 1) // (EMAC) Full duplex. -#define AT91C_EMAC_JFRAME ((unsigned int) 0x1 << 3) // (EMAC) Jumbo Frames. -#define AT91C_EMAC_CAF ((unsigned int) 0x1 << 4) // (EMAC) Copy all frames. -#define AT91C_EMAC_NBC ((unsigned int) 0x1 << 5) // (EMAC) No broadcast. -#define AT91C_EMAC_MTI ((unsigned int) 0x1 << 6) // (EMAC) Multicast hash event enable -#define AT91C_EMAC_UNI ((unsigned int) 0x1 << 7) // (EMAC) Unicast hash enable. -#define AT91C_EMAC_BIG ((unsigned int) 0x1 << 8) // (EMAC) Receive 1522 bytes. -#define AT91C_EMAC_EAE ((unsigned int) 0x1 << 9) // (EMAC) External address match enable. -#define AT91C_EMAC_CLK ((unsigned int) 0x3 << 10) // (EMAC) -#define AT91C_EMAC_CLK_HCLK_8 ((unsigned int) 0x0 << 10) // (EMAC) HCLK divided by 8 -#define AT91C_EMAC_CLK_HCLK_16 ((unsigned int) 0x1 << 10) // (EMAC) HCLK divided by 16 -#define AT91C_EMAC_CLK_HCLK_32 ((unsigned int) 0x2 << 10) // (EMAC) HCLK divided by 32 -#define AT91C_EMAC_CLK_HCLK_64 ((unsigned int) 0x3 << 10) // (EMAC) HCLK divided by 64 -#define AT91C_EMAC_RTY ((unsigned int) 0x1 << 12) // (EMAC) -#define AT91C_EMAC_PAE ((unsigned int) 0x1 << 13) // (EMAC) -#define AT91C_EMAC_RBOF ((unsigned int) 0x3 << 14) // (EMAC) -#define AT91C_EMAC_RBOF_OFFSET_0 ((unsigned int) 0x0 << 14) // (EMAC) no offset from start of receive buffer -#define AT91C_EMAC_RBOF_OFFSET_1 ((unsigned int) 0x1 << 14) // (EMAC) one byte offset from start of receive buffer -#define AT91C_EMAC_RBOF_OFFSET_2 ((unsigned int) 0x2 << 14) // (EMAC) two bytes offset from start of receive buffer -#define AT91C_EMAC_RBOF_OFFSET_3 ((unsigned int) 0x3 << 14) // (EMAC) three bytes offset from start of receive buffer -#define AT91C_EMAC_RLCE ((unsigned int) 0x1 << 16) // (EMAC) Receive Length field Checking Enable -#define AT91C_EMAC_DRFCS ((unsigned int) 0x1 << 17) // (EMAC) Discard Receive FCS -#define AT91C_EMAC_EFRHD ((unsigned int) 0x1 << 18) // (EMAC) -#define AT91C_EMAC_IRXFCS ((unsigned int) 0x1 << 19) // (EMAC) Ignore RX FCS -// -------- EMAC_NSR : (EMAC Offset: 0x8) Network Status Register -------- -#define AT91C_EMAC_LINKR ((unsigned int) 0x1 << 0) // (EMAC) -#define AT91C_EMAC_MDIO ((unsigned int) 0x1 << 1) // (EMAC) -#define AT91C_EMAC_IDLE ((unsigned int) 0x1 << 2) // (EMAC) -// -------- EMAC_TSR : (EMAC Offset: 0x14) Transmit Status Register -------- -#define AT91C_EMAC_UBR ((unsigned int) 0x1 << 0) // (EMAC) -#define AT91C_EMAC_COL ((unsigned int) 0x1 << 1) // (EMAC) -#define AT91C_EMAC_RLES ((unsigned int) 0x1 << 2) // (EMAC) -#define AT91C_EMAC_TGO ((unsigned int) 0x1 << 3) // (EMAC) Transmit Go -#define AT91C_EMAC_BEX ((unsigned int) 0x1 << 4) // (EMAC) Buffers exhausted mid frame -#define AT91C_EMAC_COMP ((unsigned int) 0x1 << 5) // (EMAC) -#define AT91C_EMAC_UND ((unsigned int) 0x1 << 6) // (EMAC) -// -------- EMAC_RSR : (EMAC Offset: 0x20) Receive Status Register -------- -#define AT91C_EMAC_BNA ((unsigned int) 0x1 << 0) // (EMAC) -#define AT91C_EMAC_REC ((unsigned int) 0x1 << 1) // (EMAC) -#define AT91C_EMAC_OVR ((unsigned int) 0x1 << 2) // (EMAC) -// -------- EMAC_ISR : (EMAC Offset: 0x24) Interrupt Status Register -------- -#define AT91C_EMAC_MFD ((unsigned int) 0x1 << 0) // (EMAC) -#define AT91C_EMAC_RCOMP ((unsigned int) 0x1 << 1) // (EMAC) -#define AT91C_EMAC_RXUBR ((unsigned int) 0x1 << 2) // (EMAC) -#define AT91C_EMAC_TXUBR ((unsigned int) 0x1 << 3) // (EMAC) -#define AT91C_EMAC_TUNDR ((unsigned int) 0x1 << 4) // (EMAC) -#define AT91C_EMAC_RLEX ((unsigned int) 0x1 << 5) // (EMAC) -#define AT91C_EMAC_TXERR ((unsigned int) 0x1 << 6) // (EMAC) -#define AT91C_EMAC_TCOMP ((unsigned int) 0x1 << 7) // (EMAC) -#define AT91C_EMAC_LINK ((unsigned int) 0x1 << 9) // (EMAC) -#define AT91C_EMAC_ROVR ((unsigned int) 0x1 << 10) // (EMAC) -#define AT91C_EMAC_HRESP ((unsigned int) 0x1 << 11) // (EMAC) -#define AT91C_EMAC_PFRE ((unsigned int) 0x1 << 12) // (EMAC) -#define AT91C_EMAC_PTZ ((unsigned int) 0x1 << 13) // (EMAC) -// -------- EMAC_IER : (EMAC Offset: 0x28) Interrupt Enable Register -------- -// -------- EMAC_IDR : (EMAC Offset: 0x2c) Interrupt Disable Register -------- -// -------- EMAC_IMR : (EMAC Offset: 0x30) Interrupt Mask Register -------- -// -------- EMAC_MAN : (EMAC Offset: 0x34) PHY Maintenance Register -------- -#define AT91C_EMAC_DATA ((unsigned int) 0xFFFF << 0) // (EMAC) -#define AT91C_EMAC_CODE ((unsigned int) 0x3 << 16) // (EMAC) -#define AT91C_EMAC_REGA ((unsigned int) 0x1F << 18) // (EMAC) -#define AT91C_EMAC_PHYA ((unsigned int) 0x1F << 23) // (EMAC) -#define AT91C_EMAC_RW ((unsigned int) 0x3 << 28) // (EMAC) -#define AT91C_EMAC_SOF ((unsigned int) 0x3 << 30) // (EMAC) -// -------- EMAC_USRIO : (EMAC Offset: 0xc0) USER Input Output Register -------- -#define AT91C_EMAC_RMII ((unsigned int) 0x1 << 0) // (EMAC) Reduce MII -// -------- EMAC_WOL : (EMAC Offset: 0xc4) Wake On LAN Register -------- -#define AT91C_EMAC_IP ((unsigned int) 0xFFFF << 0) // (EMAC) ARP request IP address -#define AT91C_EMAC_MAG ((unsigned int) 0x1 << 16) // (EMAC) Magic packet event enable -#define AT91C_EMAC_ARP ((unsigned int) 0x1 << 17) // (EMAC) ARP request event enable -#define AT91C_EMAC_SA1 ((unsigned int) 0x1 << 18) // (EMAC) Specific address register 1 event enable -// -------- EMAC_REV : (EMAC Offset: 0xfc) Revision Register -------- -#define AT91C_EMAC_REVREF ((unsigned int) 0xFFFF << 0) // (EMAC) -#define AT91C_EMAC_PARTREF ((unsigned int) 0xFFFF << 16) // (EMAC) - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Analog to Digital Convertor -// ***************************************************************************** -typedef struct _AT91S_ADC { - AT91_REG ADC_CR; // ADC Control Register - AT91_REG ADC_MR; // ADC Mode Register - AT91_REG Reserved0[2]; // - AT91_REG ADC_CHER; // ADC Channel Enable Register - AT91_REG ADC_CHDR; // ADC Channel Disable Register - AT91_REG ADC_CHSR; // ADC Channel Status Register - AT91_REG ADC_SR; // ADC Status Register - AT91_REG ADC_LCDR; // ADC Last Converted Data Register - AT91_REG ADC_IER; // ADC Interrupt Enable Register - AT91_REG ADC_IDR; // ADC Interrupt Disable Register - AT91_REG ADC_IMR; // ADC Interrupt Mask Register - AT91_REG ADC_CDR0; // ADC Channel Data Register 0 - AT91_REG ADC_CDR1; // ADC Channel Data Register 1 - AT91_REG ADC_CDR2; // ADC Channel Data Register 2 - AT91_REG ADC_CDR3; // ADC Channel Data Register 3 - AT91_REG ADC_CDR4; // ADC Channel Data Register 4 - AT91_REG ADC_CDR5; // ADC Channel Data Register 5 - AT91_REG ADC_CDR6; // ADC Channel Data Register 6 - AT91_REG ADC_CDR7; // ADC Channel Data Register 7 - AT91_REG Reserved1[44]; // - AT91_REG ADC_RPR; // Receive Pointer Register - AT91_REG ADC_RCR; // Receive Counter Register - AT91_REG ADC_TPR; // Transmit Pointer Register - AT91_REG ADC_TCR; // Transmit Counter Register - AT91_REG ADC_RNPR; // Receive Next Pointer Register - AT91_REG ADC_RNCR; // Receive Next Counter Register - AT91_REG ADC_TNPR; // Transmit Next Pointer Register - AT91_REG ADC_TNCR; // Transmit Next Counter Register - AT91_REG ADC_PTCR; // PDC Transfer Control Register - AT91_REG ADC_PTSR; // PDC Transfer Status Register -} AT91S_ADC, *AT91PS_ADC; - -// -------- ADC_CR : (ADC Offset: 0x0) ADC Control Register -------- -#define AT91C_ADC_SWRST ((unsigned int) 0x1 << 0) // (ADC) Software Reset -#define AT91C_ADC_START ((unsigned int) 0x1 << 1) // (ADC) Start Conversion -// -------- ADC_MR : (ADC Offset: 0x4) ADC Mode Register -------- -#define AT91C_ADC_TRGEN ((unsigned int) 0x1 << 0) // (ADC) Trigger Enable -#define AT91C_ADC_TRGEN_DIS ((unsigned int) 0x0) // (ADC) Hradware triggers are disabled. Starting a conversion is only possible by software -#define AT91C_ADC_TRGEN_EN ((unsigned int) 0x1) // (ADC) Hardware trigger selected by TRGSEL field is enabled. -#define AT91C_ADC_TRGSEL ((unsigned int) 0x7 << 1) // (ADC) Trigger Selection -#define AT91C_ADC_TRGSEL_TIOA0 ((unsigned int) 0x0 << 1) // (ADC) Selected TRGSEL = TIAO0 -#define AT91C_ADC_TRGSEL_TIOA1 ((unsigned int) 0x1 << 1) // (ADC) Selected TRGSEL = TIAO1 -#define AT91C_ADC_TRGSEL_TIOA2 ((unsigned int) 0x2 << 1) // (ADC) Selected TRGSEL = TIAO2 -#define AT91C_ADC_TRGSEL_TIOA3 ((unsigned int) 0x3 << 1) // (ADC) Selected TRGSEL = TIAO3 -#define AT91C_ADC_TRGSEL_TIOA4 ((unsigned int) 0x4 << 1) // (ADC) Selected TRGSEL = TIAO4 -#define AT91C_ADC_TRGSEL_TIOA5 ((unsigned int) 0x5 << 1) // (ADC) Selected TRGSEL = TIAO5 -#define AT91C_ADC_TRGSEL_EXT ((unsigned int) 0x6 << 1) // (ADC) Selected TRGSEL = External Trigger -#define AT91C_ADC_LOWRES ((unsigned int) 0x1 << 4) // (ADC) Resolution. -#define AT91C_ADC_LOWRES_10_BIT ((unsigned int) 0x0 << 4) // (ADC) 10-bit resolution -#define AT91C_ADC_LOWRES_8_BIT ((unsigned int) 0x1 << 4) // (ADC) 8-bit resolution -#define AT91C_ADC_SLEEP ((unsigned int) 0x1 << 5) // (ADC) Sleep Mode -#define AT91C_ADC_SLEEP_NORMAL_MODE ((unsigned int) 0x0 << 5) // (ADC) Normal Mode -#define AT91C_ADC_SLEEP_MODE ((unsigned int) 0x1 << 5) // (ADC) Sleep Mode -#define AT91C_ADC_PRESCAL ((unsigned int) 0x3F << 8) // (ADC) Prescaler rate selection -#define AT91C_ADC_STARTUP ((unsigned int) 0x1F << 16) // (ADC) Startup Time -#define AT91C_ADC_SHTIM ((unsigned int) 0xF << 24) // (ADC) Sample & Hold Time -// -------- ADC_CHER : (ADC Offset: 0x10) ADC Channel Enable Register -------- -#define AT91C_ADC_CH0 ((unsigned int) 0x1 << 0) // (ADC) Channel 0 -#define AT91C_ADC_CH1 ((unsigned int) 0x1 << 1) // (ADC) Channel 1 -#define AT91C_ADC_CH2 ((unsigned int) 0x1 << 2) // (ADC) Channel 2 -#define AT91C_ADC_CH3 ((unsigned int) 0x1 << 3) // (ADC) Channel 3 -#define AT91C_ADC_CH4 ((unsigned int) 0x1 << 4) // (ADC) Channel 4 -#define AT91C_ADC_CH5 ((unsigned int) 0x1 << 5) // (ADC) Channel 5 -#define AT91C_ADC_CH6 ((unsigned int) 0x1 << 6) // (ADC) Channel 6 -#define AT91C_ADC_CH7 ((unsigned int) 0x1 << 7) // (ADC) Channel 7 -// -------- ADC_CHDR : (ADC Offset: 0x14) ADC Channel Disable Register -------- -// -------- ADC_CHSR : (ADC Offset: 0x18) ADC Channel Status Register -------- -// -------- ADC_SR : (ADC Offset: 0x1c) ADC Status Register -------- -#define AT91C_ADC_EOC0 ((unsigned int) 0x1 << 0) // (ADC) End of Conversion -#define AT91C_ADC_EOC1 ((unsigned int) 0x1 << 1) // (ADC) End of Conversion -#define AT91C_ADC_EOC2 ((unsigned int) 0x1 << 2) // (ADC) End of Conversion -#define AT91C_ADC_EOC3 ((unsigned int) 0x1 << 3) // (ADC) End of Conversion -#define AT91C_ADC_EOC4 ((unsigned int) 0x1 << 4) // (ADC) End of Conversion -#define AT91C_ADC_EOC5 ((unsigned int) 0x1 << 5) // (ADC) End of Conversion -#define AT91C_ADC_EOC6 ((unsigned int) 0x1 << 6) // (ADC) End of Conversion -#define AT91C_ADC_EOC7 ((unsigned int) 0x1 << 7) // (ADC) End of Conversion -#define AT91C_ADC_OVRE0 ((unsigned int) 0x1 << 8) // (ADC) Overrun Error -#define AT91C_ADC_OVRE1 ((unsigned int) 0x1 << 9) // (ADC) Overrun Error -#define AT91C_ADC_OVRE2 ((unsigned int) 0x1 << 10) // (ADC) Overrun Error -#define AT91C_ADC_OVRE3 ((unsigned int) 0x1 << 11) // (ADC) Overrun Error -#define AT91C_ADC_OVRE4 ((unsigned int) 0x1 << 12) // (ADC) Overrun Error -#define AT91C_ADC_OVRE5 ((unsigned int) 0x1 << 13) // (ADC) Overrun Error -#define AT91C_ADC_OVRE6 ((unsigned int) 0x1 << 14) // (ADC) Overrun Error -#define AT91C_ADC_OVRE7 ((unsigned int) 0x1 << 15) // (ADC) Overrun Error -#define AT91C_ADC_DRDY ((unsigned int) 0x1 << 16) // (ADC) Data Ready -#define AT91C_ADC_GOVRE ((unsigned int) 0x1 << 17) // (ADC) General Overrun -#define AT91C_ADC_ENDRX ((unsigned int) 0x1 << 18) // (ADC) End of Receiver Transfer -#define AT91C_ADC_RXBUFF ((unsigned int) 0x1 << 19) // (ADC) RXBUFF Interrupt -// -------- ADC_LCDR : (ADC Offset: 0x20) ADC Last Converted Data Register -------- -#define AT91C_ADC_LDATA ((unsigned int) 0x3FF << 0) // (ADC) Last Data Converted -// -------- ADC_IER : (ADC Offset: 0x24) ADC Interrupt Enable Register -------- -// -------- ADC_IDR : (ADC Offset: 0x28) ADC Interrupt Disable Register -------- -// -------- ADC_IMR : (ADC Offset: 0x2c) ADC Interrupt Mask Register -------- -// -------- ADC_CDR0 : (ADC Offset: 0x30) ADC Channel Data Register 0 -------- -#define AT91C_ADC_DATA ((unsigned int) 0x3FF << 0) // (ADC) Converted Data -// -------- ADC_CDR1 : (ADC Offset: 0x34) ADC Channel Data Register 1 -------- -// -------- ADC_CDR2 : (ADC Offset: 0x38) ADC Channel Data Register 2 -------- -// -------- ADC_CDR3 : (ADC Offset: 0x3c) ADC Channel Data Register 3 -------- -// -------- ADC_CDR4 : (ADC Offset: 0x40) ADC Channel Data Register 4 -------- -// -------- ADC_CDR5 : (ADC Offset: 0x44) ADC Channel Data Register 5 -------- -// -------- ADC_CDR6 : (ADC Offset: 0x48) ADC Channel Data Register 6 -------- -// -------- ADC_CDR7 : (ADC Offset: 0x4c) ADC Channel Data Register 7 -------- - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Advanced Encryption Standard -// ***************************************************************************** -typedef struct _AT91S_AES { - AT91_REG AES_CR; // Control Register - AT91_REG AES_MR; // Mode Register - AT91_REG Reserved0[2]; // - AT91_REG AES_IER; // Interrupt Enable Register - AT91_REG AES_IDR; // Interrupt Disable Register - AT91_REG AES_IMR; // Interrupt Mask Register - AT91_REG AES_ISR; // Interrupt Status Register - AT91_REG AES_KEYWxR[4]; // Key Word x Register - AT91_REG Reserved1[4]; // - AT91_REG AES_IDATAxR[4]; // Input Data x Register - AT91_REG AES_ODATAxR[4]; // Output Data x Register - AT91_REG AES_IVxR[4]; // Initialization Vector x Register - AT91_REG Reserved2[35]; // - AT91_REG AES_VR; // AES Version Register - AT91_REG AES_RPR; // Receive Pointer Register - AT91_REG AES_RCR; // Receive Counter Register - AT91_REG AES_TPR; // Transmit Pointer Register - AT91_REG AES_TCR; // Transmit Counter Register - AT91_REG AES_RNPR; // Receive Next Pointer Register - AT91_REG AES_RNCR; // Receive Next Counter Register - AT91_REG AES_TNPR; // Transmit Next Pointer Register - AT91_REG AES_TNCR; // Transmit Next Counter Register - AT91_REG AES_PTCR; // PDC Transfer Control Register - AT91_REG AES_PTSR; // PDC Transfer Status Register -} AT91S_AES, *AT91PS_AES; - -// -------- AES_CR : (AES Offset: 0x0) Control Register -------- -#define AT91C_AES_START ((unsigned int) 0x1 << 0) // (AES) Starts Processing -#define AT91C_AES_SWRST ((unsigned int) 0x1 << 8) // (AES) Software Reset -#define AT91C_AES_LOADSEED ((unsigned int) 0x1 << 16) // (AES) Random Number Generator Seed Loading -// -------- AES_MR : (AES Offset: 0x4) Mode Register -------- -#define AT91C_AES_CIPHER ((unsigned int) 0x1 << 0) // (AES) Processing Mode -#define AT91C_AES_PROCDLY ((unsigned int) 0xF << 4) // (AES) Processing Delay -#define AT91C_AES_SMOD ((unsigned int) 0x3 << 8) // (AES) Start Mode -#define AT91C_AES_SMOD_MANUAL ((unsigned int) 0x0 << 8) // (AES) Manual Mode: The START bit in register AES_CR must be set to begin encryption or decryption. -#define AT91C_AES_SMOD_AUTO ((unsigned int) 0x1 << 8) // (AES) Auto Mode: no action in AES_CR is necessary (cf datasheet). -#define AT91C_AES_SMOD_PDC ((unsigned int) 0x2 << 8) // (AES) PDC Mode (cf datasheet). -#define AT91C_AES_OPMOD ((unsigned int) 0x7 << 12) // (AES) Operation Mode -#define AT91C_AES_OPMOD_ECB ((unsigned int) 0x0 << 12) // (AES) ECB Electronic CodeBook mode. -#define AT91C_AES_OPMOD_CBC ((unsigned int) 0x1 << 12) // (AES) CBC Cipher Block Chaining mode. -#define AT91C_AES_OPMOD_OFB ((unsigned int) 0x2 << 12) // (AES) OFB Output Feedback mode. -#define AT91C_AES_OPMOD_CFB ((unsigned int) 0x3 << 12) // (AES) CFB Cipher Feedback mode. -#define AT91C_AES_OPMOD_CTR ((unsigned int) 0x4 << 12) // (AES) CTR Counter mode. -#define AT91C_AES_LOD ((unsigned int) 0x1 << 15) // (AES) Last Output Data Mode -#define AT91C_AES_CFBS ((unsigned int) 0x7 << 16) // (AES) Cipher Feedback Data Size -#define AT91C_AES_CFBS_128_BIT ((unsigned int) 0x0 << 16) // (AES) 128-bit. -#define AT91C_AES_CFBS_64_BIT ((unsigned int) 0x1 << 16) // (AES) 64-bit. -#define AT91C_AES_CFBS_32_BIT ((unsigned int) 0x2 << 16) // (AES) 32-bit. -#define AT91C_AES_CFBS_16_BIT ((unsigned int) 0x3 << 16) // (AES) 16-bit. -#define AT91C_AES_CFBS_8_BIT ((unsigned int) 0x4 << 16) // (AES) 8-bit. -#define AT91C_AES_CKEY ((unsigned int) 0xF << 20) // (AES) Countermeasure Key -#define AT91C_AES_CTYPE ((unsigned int) 0x1F << 24) // (AES) Countermeasure Type -#define AT91C_AES_CTYPE_TYPE1_EN ((unsigned int) 0x1 << 24) // (AES) Countermeasure type 1 is enabled. -#define AT91C_AES_CTYPE_TYPE2_EN ((unsigned int) 0x2 << 24) // (AES) Countermeasure type 2 is enabled. -#define AT91C_AES_CTYPE_TYPE3_EN ((unsigned int) 0x4 << 24) // (AES) Countermeasure type 3 is enabled. -#define AT91C_AES_CTYPE_TYPE4_EN ((unsigned int) 0x8 << 24) // (AES) Countermeasure type 4 is enabled. -#define AT91C_AES_CTYPE_TYPE5_EN ((unsigned int) 0x10 << 24) // (AES) Countermeasure type 5 is enabled. -// -------- AES_IER : (AES Offset: 0x10) Interrupt Enable Register -------- -#define AT91C_AES_DATRDY ((unsigned int) 0x1 << 0) // (AES) DATRDY -#define AT91C_AES_ENDRX ((unsigned int) 0x1 << 1) // (AES) PDC Read Buffer End -#define AT91C_AES_ENDTX ((unsigned int) 0x1 << 2) // (AES) PDC Write Buffer End -#define AT91C_AES_RXBUFF ((unsigned int) 0x1 << 3) // (AES) PDC Read Buffer Full -#define AT91C_AES_TXBUFE ((unsigned int) 0x1 << 4) // (AES) PDC Write Buffer Empty -#define AT91C_AES_URAD ((unsigned int) 0x1 << 8) // (AES) Unspecified Register Access Detection -// -------- AES_IDR : (AES Offset: 0x14) Interrupt Disable Register -------- -// -------- AES_IMR : (AES Offset: 0x18) Interrupt Mask Register -------- -// -------- AES_ISR : (AES Offset: 0x1c) Interrupt Status Register -------- -#define AT91C_AES_URAT ((unsigned int) 0x7 << 12) // (AES) Unspecified Register Access Type Status -#define AT91C_AES_URAT_IN_DAT_WRITE_DATPROC ((unsigned int) 0x0 << 12) // (AES) Input data register written during the data processing in PDC mode. -#define AT91C_AES_URAT_OUT_DAT_READ_DATPROC ((unsigned int) 0x1 << 12) // (AES) Output data register read during the data processing. -#define AT91C_AES_URAT_MODEREG_WRITE_DATPROC ((unsigned int) 0x2 << 12) // (AES) Mode register written during the data processing. -#define AT91C_AES_URAT_OUT_DAT_READ_SUBKEY ((unsigned int) 0x3 << 12) // (AES) Output data register read during the sub-keys generation. -#define AT91C_AES_URAT_MODEREG_WRITE_SUBKEY ((unsigned int) 0x4 << 12) // (AES) Mode register written during the sub-keys generation. -#define AT91C_AES_URAT_WO_REG_READ ((unsigned int) 0x5 << 12) // (AES) Write-only register read access. - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Triple Data Encryption Standard -// ***************************************************************************** -typedef struct _AT91S_TDES { - AT91_REG TDES_CR; // Control Register - AT91_REG TDES_MR; // Mode Register - AT91_REG Reserved0[2]; // - AT91_REG TDES_IER; // Interrupt Enable Register - AT91_REG TDES_IDR; // Interrupt Disable Register - AT91_REG TDES_IMR; // Interrupt Mask Register - AT91_REG TDES_ISR; // Interrupt Status Register - AT91_REG TDES_KEY1WxR[2]; // Key 1 Word x Register - AT91_REG TDES_KEY2WxR[2]; // Key 2 Word x Register - AT91_REG TDES_KEY3WxR[2]; // Key 3 Word x Register - AT91_REG Reserved1[2]; // - AT91_REG TDES_IDATAxR[2]; // Input Data x Register - AT91_REG Reserved2[2]; // - AT91_REG TDES_ODATAxR[2]; // Output Data x Register - AT91_REG Reserved3[2]; // - AT91_REG TDES_IVxR[2]; // Initialization Vector x Register - AT91_REG Reserved4[37]; // - AT91_REG TDES_VR; // TDES Version Register - AT91_REG TDES_RPR; // Receive Pointer Register - AT91_REG TDES_RCR; // Receive Counter Register - AT91_REG TDES_TPR; // Transmit Pointer Register - AT91_REG TDES_TCR; // Transmit Counter Register - AT91_REG TDES_RNPR; // Receive Next Pointer Register - AT91_REG TDES_RNCR; // Receive Next Counter Register - AT91_REG TDES_TNPR; // Transmit Next Pointer Register - AT91_REG TDES_TNCR; // Transmit Next Counter Register - AT91_REG TDES_PTCR; // PDC Transfer Control Register - AT91_REG TDES_PTSR; // PDC Transfer Status Register -} AT91S_TDES, *AT91PS_TDES; - -// -------- TDES_CR : (TDES Offset: 0x0) Control Register -------- -#define AT91C_TDES_START ((unsigned int) 0x1 << 0) // (TDES) Starts Processing -#define AT91C_TDES_SWRST ((unsigned int) 0x1 << 8) // (TDES) Software Reset -// -------- TDES_MR : (TDES Offset: 0x4) Mode Register -------- -#define AT91C_TDES_CIPHER ((unsigned int) 0x1 << 0) // (TDES) Processing Mode -#define AT91C_TDES_TDESMOD ((unsigned int) 0x1 << 1) // (TDES) Single or Triple DES Mode -#define AT91C_TDES_KEYMOD ((unsigned int) 0x1 << 4) // (TDES) Key Mode -#define AT91C_TDES_SMOD ((unsigned int) 0x3 << 8) // (TDES) Start Mode -#define AT91C_TDES_SMOD_MANUAL ((unsigned int) 0x0 << 8) // (TDES) Manual Mode: The START bit in register TDES_CR must be set to begin encryption or decryption. -#define AT91C_TDES_SMOD_AUTO ((unsigned int) 0x1 << 8) // (TDES) Auto Mode: no action in TDES_CR is necessary (cf datasheet). -#define AT91C_TDES_SMOD_PDC ((unsigned int) 0x2 << 8) // (TDES) PDC Mode (cf datasheet). -#define AT91C_TDES_OPMOD ((unsigned int) 0x3 << 12) // (TDES) Operation Mode -#define AT91C_TDES_OPMOD_ECB ((unsigned int) 0x0 << 12) // (TDES) ECB Electronic CodeBook mode. -#define AT91C_TDES_OPMOD_CBC ((unsigned int) 0x1 << 12) // (TDES) CBC Cipher Block Chaining mode. -#define AT91C_TDES_OPMOD_OFB ((unsigned int) 0x2 << 12) // (TDES) OFB Output Feedback mode. -#define AT91C_TDES_OPMOD_CFB ((unsigned int) 0x3 << 12) // (TDES) CFB Cipher Feedback mode. -#define AT91C_TDES_LOD ((unsigned int) 0x1 << 15) // (TDES) Last Output Data Mode -#define AT91C_TDES_CFBS ((unsigned int) 0x3 << 16) // (TDES) Cipher Feedback Data Size -#define AT91C_TDES_CFBS_64_BIT ((unsigned int) 0x0 << 16) // (TDES) 64-bit. -#define AT91C_TDES_CFBS_32_BIT ((unsigned int) 0x1 << 16) // (TDES) 32-bit. -#define AT91C_TDES_CFBS_16_BIT ((unsigned int) 0x2 << 16) // (TDES) 16-bit. -#define AT91C_TDES_CFBS_8_BIT ((unsigned int) 0x3 << 16) // (TDES) 8-bit. -// -------- TDES_IER : (TDES Offset: 0x10) Interrupt Enable Register -------- -#define AT91C_TDES_DATRDY ((unsigned int) 0x1 << 0) // (TDES) DATRDY -#define AT91C_TDES_ENDRX ((unsigned int) 0x1 << 1) // (TDES) PDC Read Buffer End -#define AT91C_TDES_ENDTX ((unsigned int) 0x1 << 2) // (TDES) PDC Write Buffer End -#define AT91C_TDES_RXBUFF ((unsigned int) 0x1 << 3) // (TDES) PDC Read Buffer Full -#define AT91C_TDES_TXBUFE ((unsigned int) 0x1 << 4) // (TDES) PDC Write Buffer Empty -#define AT91C_TDES_URAD ((unsigned int) 0x1 << 8) // (TDES) Unspecified Register Access Detection -// -------- TDES_IDR : (TDES Offset: 0x14) Interrupt Disable Register -------- -// -------- TDES_IMR : (TDES Offset: 0x18) Interrupt Mask Register -------- -// -------- TDES_ISR : (TDES Offset: 0x1c) Interrupt Status Register -------- -#define AT91C_TDES_URAT ((unsigned int) 0x3 << 12) // (TDES) Unspecified Register Access Type Status -#define AT91C_TDES_URAT_IN_DAT_WRITE_DATPROC ((unsigned int) 0x0 << 12) // (TDES) Input data register written during the data processing in PDC mode. -#define AT91C_TDES_URAT_OUT_DAT_READ_DATPROC ((unsigned int) 0x1 << 12) // (TDES) Output data register read during the data processing. -#define AT91C_TDES_URAT_MODEREG_WRITE_DATPROC ((unsigned int) 0x2 << 12) // (TDES) Mode register written during the data processing. -#define AT91C_TDES_URAT_WO_REG_READ ((unsigned int) 0x3 << 12) // (TDES) Write-only register read access. - -// ***************************************************************************** -// REGISTER ADDRESS DEFINITION FOR AT91SAM7X256 -// ***************************************************************************** -// ========== Register definition for SYS peripheral ========== -// ========== Register definition for AIC peripheral ========== -#define AT91C_AIC_IVR ((AT91_REG *) 0xFFFFF100) // (AIC) IRQ Vector Register -#define AT91C_AIC_SMR ((AT91_REG *) 0xFFFFF000) // (AIC) Source Mode Register -#define AT91C_AIC_FVR ((AT91_REG *) 0xFFFFF104) // (AIC) FIQ Vector Register -#define AT91C_AIC_DCR ((AT91_REG *) 0xFFFFF138) // (AIC) Debug Control Register (Protect) -#define AT91C_AIC_EOICR ((AT91_REG *) 0xFFFFF130) // (AIC) End of Interrupt Command Register -#define AT91C_AIC_SVR ((AT91_REG *) 0xFFFFF080) // (AIC) Source Vector Register -#define AT91C_AIC_FFSR ((AT91_REG *) 0xFFFFF148) // (AIC) Fast Forcing Status Register -#define AT91C_AIC_ICCR ((AT91_REG *) 0xFFFFF128) // (AIC) Interrupt Clear Command Register -#define AT91C_AIC_ISR ((AT91_REG *) 0xFFFFF108) // (AIC) Interrupt Status Register -#define AT91C_AIC_IMR ((AT91_REG *) 0xFFFFF110) // (AIC) Interrupt Mask Register -#define AT91C_AIC_IPR ((AT91_REG *) 0xFFFFF10C) // (AIC) Interrupt Pending Register -#define AT91C_AIC_FFER ((AT91_REG *) 0xFFFFF140) // (AIC) Fast Forcing Enable Register -#define AT91C_AIC_IECR ((AT91_REG *) 0xFFFFF120) // (AIC) Interrupt Enable Command Register -#define AT91C_AIC_ISCR ((AT91_REG *) 0xFFFFF12C) // (AIC) Interrupt Set Command Register -#define AT91C_AIC_FFDR ((AT91_REG *) 0xFFFFF144) // (AIC) Fast Forcing Disable Register -#define AT91C_AIC_CISR ((AT91_REG *) 0xFFFFF114) // (AIC) Core Interrupt Status Register -#define AT91C_AIC_IDCR ((AT91_REG *) 0xFFFFF124) // (AIC) Interrupt Disable Command Register -#define AT91C_AIC_SPU ((AT91_REG *) 0xFFFFF134) // (AIC) Spurious Vector Register -// ========== Register definition for PDC_DBGU peripheral ========== -#define AT91C_DBGU_TCR ((AT91_REG *) 0xFFFFF30C) // (PDC_DBGU) Transmit Counter Register -#define AT91C_DBGU_RNPR ((AT91_REG *) 0xFFFFF310) // (PDC_DBGU) Receive Next Pointer Register -#define AT91C_DBGU_TNPR ((AT91_REG *) 0xFFFFF318) // (PDC_DBGU) Transmit Next Pointer Register -#define AT91C_DBGU_TPR ((AT91_REG *) 0xFFFFF308) // (PDC_DBGU) Transmit Pointer Register -#define AT91C_DBGU_RPR ((AT91_REG *) 0xFFFFF300) // (PDC_DBGU) Receive Pointer Register -#define AT91C_DBGU_RCR ((AT91_REG *) 0xFFFFF304) // (PDC_DBGU) Receive Counter Register -#define AT91C_DBGU_RNCR ((AT91_REG *) 0xFFFFF314) // (PDC_DBGU) Receive Next Counter Register -#define AT91C_DBGU_PTCR ((AT91_REG *) 0xFFFFF320) // (PDC_DBGU) PDC Transfer Control Register -#define AT91C_DBGU_PTSR ((AT91_REG *) 0xFFFFF324) // (PDC_DBGU) PDC Transfer Status Register -#define AT91C_DBGU_TNCR ((AT91_REG *) 0xFFFFF31C) // (PDC_DBGU) Transmit Next Counter Register -// ========== Register definition for DBGU peripheral ========== -#define AT91C_DBGU_EXID ((AT91_REG *) 0xFFFFF244) // (DBGU) Chip ID Extension Register -#define AT91C_DBGU_BRGR ((AT91_REG *) 0xFFFFF220) // (DBGU) Baud Rate Generator Register -#define AT91C_DBGU_IDR ((AT91_REG *) 0xFFFFF20C) // (DBGU) Interrupt Disable Register -#define AT91C_DBGU_CSR ((AT91_REG *) 0xFFFFF214) // (DBGU) Channel Status Register -#define AT91C_DBGU_CIDR ((AT91_REG *) 0xFFFFF240) // (DBGU) Chip ID Register -#define AT91C_DBGU_MR ((AT91_REG *) 0xFFFFF204) // (DBGU) Mode Register -#define AT91C_DBGU_IMR ((AT91_REG *) 0xFFFFF210) // (DBGU) Interrupt Mask Register -#define AT91C_DBGU_CR ((AT91_REG *) 0xFFFFF200) // (DBGU) Control Register -#define AT91C_DBGU_FNTR ((AT91_REG *) 0xFFFFF248) // (DBGU) Force NTRST Register -#define AT91C_DBGU_THR ((AT91_REG *) 0xFFFFF21C) // (DBGU) Transmitter Holding Register -#define AT91C_DBGU_RHR ((AT91_REG *) 0xFFFFF218) // (DBGU) Receiver Holding Register -#define AT91C_DBGU_IER ((AT91_REG *) 0xFFFFF208) // (DBGU) Interrupt Enable Register -// ========== Register definition for PIOA peripheral ========== -#define AT91C_PIOA_ODR ((AT91_REG *) 0xFFFFF414) // (PIOA) Output Disable Registerr -#define AT91C_PIOA_SODR ((AT91_REG *) 0xFFFFF430) // (PIOA) Set Output Data Register -#define AT91C_PIOA_ISR ((AT91_REG *) 0xFFFFF44C) // (PIOA) Interrupt Status Register -#define AT91C_PIOA_ABSR ((AT91_REG *) 0xFFFFF478) // (PIOA) AB Select Status Register -#define AT91C_PIOA_IER ((AT91_REG *) 0xFFFFF440) // (PIOA) Interrupt Enable Register -#define AT91C_PIOA_PPUDR ((AT91_REG *) 0xFFFFF460) // (PIOA) Pull-up Disable Register -#define AT91C_PIOA_IMR ((AT91_REG *) 0xFFFFF448) // (PIOA) Interrupt Mask Register -#define AT91C_PIOA_PER ((AT91_REG *) 0xFFFFF400) // (PIOA) PIO Enable Register -#define AT91C_PIOA_IFDR ((AT91_REG *) 0xFFFFF424) // (PIOA) Input Filter Disable Register -#define AT91C_PIOA_OWDR ((AT91_REG *) 0xFFFFF4A4) // (PIOA) Output Write Disable Register -#define AT91C_PIOA_MDSR ((AT91_REG *) 0xFFFFF458) // (PIOA) Multi-driver Status Register -#define AT91C_PIOA_IDR ((AT91_REG *) 0xFFFFF444) // (PIOA) Interrupt Disable Register -#define AT91C_PIOA_ODSR ((AT91_REG *) 0xFFFFF438) // (PIOA) Output Data Status Register -#define AT91C_PIOA_PPUSR ((AT91_REG *) 0xFFFFF468) // (PIOA) Pull-up Status Register -#define AT91C_PIOA_OWSR ((AT91_REG *) 0xFFFFF4A8) // (PIOA) Output Write Status Register -#define AT91C_PIOA_BSR ((AT91_REG *) 0xFFFFF474) // (PIOA) Select B Register -#define AT91C_PIOA_OWER ((AT91_REG *) 0xFFFFF4A0) // (PIOA) Output Write Enable Register -#define AT91C_PIOA_IFER ((AT91_REG *) 0xFFFFF420) // (PIOA) Input Filter Enable Register -#define AT91C_PIOA_PDSR ((AT91_REG *) 0xFFFFF43C) // (PIOA) Pin Data Status Register -#define AT91C_PIOA_PPUER ((AT91_REG *) 0xFFFFF464) // (PIOA) Pull-up Enable Register -#define AT91C_PIOA_OSR ((AT91_REG *) 0xFFFFF418) // (PIOA) Output Status Register -#define AT91C_PIOA_ASR ((AT91_REG *) 0xFFFFF470) // (PIOA) Select A Register -#define AT91C_PIOA_MDDR ((AT91_REG *) 0xFFFFF454) // (PIOA) Multi-driver Disable Register -#define AT91C_PIOA_CODR ((AT91_REG *) 0xFFFFF434) // (PIOA) Clear Output Data Register -#define AT91C_PIOA_MDER ((AT91_REG *) 0xFFFFF450) // (PIOA) Multi-driver Enable Register -#define AT91C_PIOA_PDR ((AT91_REG *) 0xFFFFF404) // (PIOA) PIO Disable Register -#define AT91C_PIOA_IFSR ((AT91_REG *) 0xFFFFF428) // (PIOA) Input Filter Status Register -#define AT91C_PIOA_OER ((AT91_REG *) 0xFFFFF410) // (PIOA) Output Enable Register -#define AT91C_PIOA_PSR ((AT91_REG *) 0xFFFFF408) // (PIOA) PIO Status Register -// ========== Register definition for PIOB peripheral ========== -#define AT91C_PIOB_OWDR ((AT91_REG *) 0xFFFFF6A4) // (PIOB) Output Write Disable Register -#define AT91C_PIOB_MDER ((AT91_REG *) 0xFFFFF650) // (PIOB) Multi-driver Enable Register -#define AT91C_PIOB_PPUSR ((AT91_REG *) 0xFFFFF668) // (PIOB) Pull-up Status Register -#define AT91C_PIOB_IMR ((AT91_REG *) 0xFFFFF648) // (PIOB) Interrupt Mask Register -#define AT91C_PIOB_ASR ((AT91_REG *) 0xFFFFF670) // (PIOB) Select A Register -#define AT91C_PIOB_PPUDR ((AT91_REG *) 0xFFFFF660) // (PIOB) Pull-up Disable Register -#define AT91C_PIOB_PSR ((AT91_REG *) 0xFFFFF608) // (PIOB) PIO Status Register -#define AT91C_PIOB_IER ((AT91_REG *) 0xFFFFF640) // (PIOB) Interrupt Enable Register -#define AT91C_PIOB_CODR ((AT91_REG *) 0xFFFFF634) // (PIOB) Clear Output Data Register -#define AT91C_PIOB_OWER ((AT91_REG *) 0xFFFFF6A0) // (PIOB) Output Write Enable Register -#define AT91C_PIOB_ABSR ((AT91_REG *) 0xFFFFF678) // (PIOB) AB Select Status Register -#define AT91C_PIOB_IFDR ((AT91_REG *) 0xFFFFF624) // (PIOB) Input Filter Disable Register -#define AT91C_PIOB_PDSR ((AT91_REG *) 0xFFFFF63C) // (PIOB) Pin Data Status Register -#define AT91C_PIOB_IDR ((AT91_REG *) 0xFFFFF644) // (PIOB) Interrupt Disable Register -#define AT91C_PIOB_OWSR ((AT91_REG *) 0xFFFFF6A8) // (PIOB) Output Write Status Register -#define AT91C_PIOB_PDR ((AT91_REG *) 0xFFFFF604) // (PIOB) PIO Disable Register -#define AT91C_PIOB_ODR ((AT91_REG *) 0xFFFFF614) // (PIOB) Output Disable Registerr -#define AT91C_PIOB_IFSR ((AT91_REG *) 0xFFFFF628) // (PIOB) Input Filter Status Register -#define AT91C_PIOB_PPUER ((AT91_REG *) 0xFFFFF664) // (PIOB) Pull-up Enable Register -#define AT91C_PIOB_SODR ((AT91_REG *) 0xFFFFF630) // (PIOB) Set Output Data Register -#define AT91C_PIOB_ISR ((AT91_REG *) 0xFFFFF64C) // (PIOB) Interrupt Status Register -#define AT91C_PIOB_ODSR ((AT91_REG *) 0xFFFFF638) // (PIOB) Output Data Status Register -#define AT91C_PIOB_OSR ((AT91_REG *) 0xFFFFF618) // (PIOB) Output Status Register -#define AT91C_PIOB_MDSR ((AT91_REG *) 0xFFFFF658) // (PIOB) Multi-driver Status Register -#define AT91C_PIOB_IFER ((AT91_REG *) 0xFFFFF620) // (PIOB) Input Filter Enable Register -#define AT91C_PIOB_BSR ((AT91_REG *) 0xFFFFF674) // (PIOB) Select B Register -#define AT91C_PIOB_MDDR ((AT91_REG *) 0xFFFFF654) // (PIOB) Multi-driver Disable Register -#define AT91C_PIOB_OER ((AT91_REG *) 0xFFFFF610) // (PIOB) Output Enable Register -#define AT91C_PIOB_PER ((AT91_REG *) 0xFFFFF600) // (PIOB) PIO Enable Register -// ========== Register definition for CKGR peripheral ========== -#define AT91C_CKGR_MOR ((AT91_REG *) 0xFFFFFC20) // (CKGR) Main Oscillator Register -#define AT91C_CKGR_PLLR ((AT91_REG *) 0xFFFFFC2C) // (CKGR) PLL Register -#define AT91C_CKGR_MCFR ((AT91_REG *) 0xFFFFFC24) // (CKGR) Main Clock Frequency Register -// ========== Register definition for PMC peripheral ========== -#define AT91C_PMC_IDR ((AT91_REG *) 0xFFFFFC64) // (PMC) Interrupt Disable Register -#define AT91C_PMC_MOR ((AT91_REG *) 0xFFFFFC20) // (PMC) Main Oscillator Register -#define AT91C_PMC_PLLR ((AT91_REG *) 0xFFFFFC2C) // (PMC) PLL Register -#define AT91C_PMC_PCER ((AT91_REG *) 0xFFFFFC10) // (PMC) Peripheral Clock Enable Register -#define AT91C_PMC_PCKR ((AT91_REG *) 0xFFFFFC40) // (PMC) Programmable Clock Register -#define AT91C_PMC_MCKR ((AT91_REG *) 0xFFFFFC30) // (PMC) Master Clock Register -#define AT91C_PMC_SCDR ((AT91_REG *) 0xFFFFFC04) // (PMC) System Clock Disable Register -#define AT91C_PMC_PCDR ((AT91_REG *) 0xFFFFFC14) // (PMC) Peripheral Clock Disable Register -#define AT91C_PMC_SCSR ((AT91_REG *) 0xFFFFFC08) // (PMC) System Clock Status Register -#define AT91C_PMC_PCSR ((AT91_REG *) 0xFFFFFC18) // (PMC) Peripheral Clock Status Register -#define AT91C_PMC_MCFR ((AT91_REG *) 0xFFFFFC24) // (PMC) Main Clock Frequency Register -#define AT91C_PMC_SCER ((AT91_REG *) 0xFFFFFC00) // (PMC) System Clock Enable Register -#define AT91C_PMC_IMR ((AT91_REG *) 0xFFFFFC6C) // (PMC) Interrupt Mask Register -#define AT91C_PMC_IER ((AT91_REG *) 0xFFFFFC60) // (PMC) Interrupt Enable Register -#define AT91C_PMC_SR ((AT91_REG *) 0xFFFFFC68) // (PMC) Status Register -// ========== Register definition for RSTC peripheral ========== -#define AT91C_RSTC_RCR ((AT91_REG *) 0xFFFFFD00) // (RSTC) Reset Control Register -#define AT91C_RSTC_RMR ((AT91_REG *) 0xFFFFFD08) // (RSTC) Reset Mode Register -#define AT91C_RSTC_RSR ((AT91_REG *) 0xFFFFFD04) // (RSTC) Reset Status Register -// ========== Register definition for RTTC peripheral ========== -#define AT91C_RTTC_RTSR ((AT91_REG *) 0xFFFFFD2C) // (RTTC) Real-time Status Register -#define AT91C_RTTC_RTMR ((AT91_REG *) 0xFFFFFD20) // (RTTC) Real-time Mode Register -#define AT91C_RTTC_RTVR ((AT91_REG *) 0xFFFFFD28) // (RTTC) Real-time Value Register -#define AT91C_RTTC_RTAR ((AT91_REG *) 0xFFFFFD24) // (RTTC) Real-time Alarm Register -// ========== Register definition for PITC peripheral ========== -#define AT91C_PITC_PIVR ((AT91_REG *) 0xFFFFFD38) // (PITC) Period Interval Value Register -#define AT91C_PITC_PISR ((AT91_REG *) 0xFFFFFD34) // (PITC) Period Interval Status Register -#define AT91C_PITC_PIIR ((AT91_REG *) 0xFFFFFD3C) // (PITC) Period Interval Image Register -#define AT91C_PITC_PIMR ((AT91_REG *) 0xFFFFFD30) // (PITC) Period Interval Mode Register -// ========== Register definition for WDTC peripheral ========== -#define AT91C_WDTC_WDCR ((AT91_REG *) 0xFFFFFD40) // (WDTC) Watchdog Control Register -#define AT91C_WDTC_WDSR ((AT91_REG *) 0xFFFFFD48) // (WDTC) Watchdog Status Register -#define AT91C_WDTC_WDMR ((AT91_REG *) 0xFFFFFD44) // (WDTC) Watchdog Mode Register -// ========== Register definition for VREG peripheral ========== -#define AT91C_VREG_MR ((AT91_REG *) 0xFFFFFD60) // (VREG) Voltage Regulator Mode Register -// ========== Register definition for MC peripheral ========== -#define AT91C_MC_ASR ((AT91_REG *) 0xFFFFFF04) // (MC) MC Abort Status Register -#define AT91C_MC_RCR ((AT91_REG *) 0xFFFFFF00) // (MC) MC Remap Control Register -#define AT91C_MC_FCR ((AT91_REG *) 0xFFFFFF64) // (MC) MC Flash Command Register -#define AT91C_MC_AASR ((AT91_REG *) 0xFFFFFF08) // (MC) MC Abort Address Status Register -#define AT91C_MC_FSR ((AT91_REG *) 0xFFFFFF68) // (MC) MC Flash Status Register -#define AT91C_MC_FMR ((AT91_REG *) 0xFFFFFF60) // (MC) MC Flash Mode Register -// ========== Register definition for PDC_SPI1 peripheral ========== -#define AT91C_SPI1_PTCR ((AT91_REG *) 0xFFFE4120) // (PDC_SPI1) PDC Transfer Control Register -#define AT91C_SPI1_RPR ((AT91_REG *) 0xFFFE4100) // (PDC_SPI1) Receive Pointer Register -#define AT91C_SPI1_TNCR ((AT91_REG *) 0xFFFE411C) // (PDC_SPI1) Transmit Next Counter Register -#define AT91C_SPI1_TPR ((AT91_REG *) 0xFFFE4108) // (PDC_SPI1) Transmit Pointer Register -#define AT91C_SPI1_TNPR ((AT91_REG *) 0xFFFE4118) // (PDC_SPI1) Transmit Next Pointer Register -#define AT91C_SPI1_TCR ((AT91_REG *) 0xFFFE410C) // (PDC_SPI1) Transmit Counter Register -#define AT91C_SPI1_RCR ((AT91_REG *) 0xFFFE4104) // (PDC_SPI1) Receive Counter Register -#define AT91C_SPI1_RNPR ((AT91_REG *) 0xFFFE4110) // (PDC_SPI1) Receive Next Pointer Register -#define AT91C_SPI1_RNCR ((AT91_REG *) 0xFFFE4114) // (PDC_SPI1) Receive Next Counter Register -#define AT91C_SPI1_PTSR ((AT91_REG *) 0xFFFE4124) // (PDC_SPI1) PDC Transfer Status Register -// ========== Register definition for SPI1 peripheral ========== -#define AT91C_SPI1_IMR ((AT91_REG *) 0xFFFE401C) // (SPI1) Interrupt Mask Register -#define AT91C_SPI1_IER ((AT91_REG *) 0xFFFE4014) // (SPI1) Interrupt Enable Register -#define AT91C_SPI1_MR ((AT91_REG *) 0xFFFE4004) // (SPI1) Mode Register -#define AT91C_SPI1_RDR ((AT91_REG *) 0xFFFE4008) // (SPI1) Receive Data Register -#define AT91C_SPI1_IDR ((AT91_REG *) 0xFFFE4018) // (SPI1) Interrupt Disable Register -#define AT91C_SPI1_SR ((AT91_REG *) 0xFFFE4010) // (SPI1) Status Register -#define AT91C_SPI1_TDR ((AT91_REG *) 0xFFFE400C) // (SPI1) Transmit Data Register -#define AT91C_SPI1_CR ((AT91_REG *) 0xFFFE4000) // (SPI1) Control Register -#define AT91C_SPI1_CSR ((AT91_REG *) 0xFFFE4030) // (SPI1) Chip Select Register -// ========== Register definition for PDC_SPI0 peripheral ========== -#define AT91C_SPI0_PTCR ((AT91_REG *) 0xFFFE0120) // (PDC_SPI0) PDC Transfer Control Register -#define AT91C_SPI0_TPR ((AT91_REG *) 0xFFFE0108) // (PDC_SPI0) Transmit Pointer Register -#define AT91C_SPI0_TCR ((AT91_REG *) 0xFFFE010C) // (PDC_SPI0) Transmit Counter Register -#define AT91C_SPI0_RCR ((AT91_REG *) 0xFFFE0104) // (PDC_SPI0) Receive Counter Register -#define AT91C_SPI0_PTSR ((AT91_REG *) 0xFFFE0124) // (PDC_SPI0) PDC Transfer Status Register -#define AT91C_SPI0_RNPR ((AT91_REG *) 0xFFFE0110) // (PDC_SPI0) Receive Next Pointer Register -#define AT91C_SPI0_RPR ((AT91_REG *) 0xFFFE0100) // (PDC_SPI0) Receive Pointer Register -#define AT91C_SPI0_TNCR ((AT91_REG *) 0xFFFE011C) // (PDC_SPI0) Transmit Next Counter Register -#define AT91C_SPI0_RNCR ((AT91_REG *) 0xFFFE0114) // (PDC_SPI0) Receive Next Counter Register -#define AT91C_SPI0_TNPR ((AT91_REG *) 0xFFFE0118) // (PDC_SPI0) Transmit Next Pointer Register -// ========== Register definition for SPI0 peripheral ========== -#define AT91C_SPI0_IER ((AT91_REG *) 0xFFFE0014) // (SPI0) Interrupt Enable Register -#define AT91C_SPI0_SR ((AT91_REG *) 0xFFFE0010) // (SPI0) Status Register -#define AT91C_SPI0_IDR ((AT91_REG *) 0xFFFE0018) // (SPI0) Interrupt Disable Register -#define AT91C_SPI0_CR ((AT91_REG *) 0xFFFE0000) // (SPI0) Control Register -#define AT91C_SPI0_MR ((AT91_REG *) 0xFFFE0004) // (SPI0) Mode Register -#define AT91C_SPI0_IMR ((AT91_REG *) 0xFFFE001C) // (SPI0) Interrupt Mask Register -#define AT91C_SPI0_TDR ((AT91_REG *) 0xFFFE000C) // (SPI0) Transmit Data Register -#define AT91C_SPI0_RDR ((AT91_REG *) 0xFFFE0008) // (SPI0) Receive Data Register -#define AT91C_SPI0_CSR ((AT91_REG *) 0xFFFE0030) // (SPI0) Chip Select Register -// ========== Register definition for PDC_US1 peripheral ========== -#define AT91C_US1_RNCR ((AT91_REG *) 0xFFFC4114) // (PDC_US1) Receive Next Counter Register -#define AT91C_US1_PTCR ((AT91_REG *) 0xFFFC4120) // (PDC_US1) PDC Transfer Control Register -#define AT91C_US1_TCR ((AT91_REG *) 0xFFFC410C) // (PDC_US1) Transmit Counter Register -#define AT91C_US1_PTSR ((AT91_REG *) 0xFFFC4124) // (PDC_US1) PDC Transfer Status Register -#define AT91C_US1_TNPR ((AT91_REG *) 0xFFFC4118) // (PDC_US1) Transmit Next Pointer Register -#define AT91C_US1_RCR ((AT91_REG *) 0xFFFC4104) // (PDC_US1) Receive Counter Register -#define AT91C_US1_RNPR ((AT91_REG *) 0xFFFC4110) // (PDC_US1) Receive Next Pointer Register -#define AT91C_US1_RPR ((AT91_REG *) 0xFFFC4100) // (PDC_US1) Receive Pointer Register -#define AT91C_US1_TNCR ((AT91_REG *) 0xFFFC411C) // (PDC_US1) Transmit Next Counter Register -#define AT91C_US1_TPR ((AT91_REG *) 0xFFFC4108) // (PDC_US1) Transmit Pointer Register -// ========== Register definition for US1 peripheral ========== -#define AT91C_US1_IF ((AT91_REG *) 0xFFFC404C) // (US1) IRDA_FILTER Register -#define AT91C_US1_NER ((AT91_REG *) 0xFFFC4044) // (US1) Nb Errors Register -#define AT91C_US1_RTOR ((AT91_REG *) 0xFFFC4024) // (US1) Receiver Time-out Register -#define AT91C_US1_CSR ((AT91_REG *) 0xFFFC4014) // (US1) Channel Status Register -#define AT91C_US1_IDR ((AT91_REG *) 0xFFFC400C) // (US1) Interrupt Disable Register -#define AT91C_US1_IER ((AT91_REG *) 0xFFFC4008) // (US1) Interrupt Enable Register -#define AT91C_US1_THR ((AT91_REG *) 0xFFFC401C) // (US1) Transmitter Holding Register -#define AT91C_US1_TTGR ((AT91_REG *) 0xFFFC4028) // (US1) Transmitter Time-guard Register -#define AT91C_US1_RHR ((AT91_REG *) 0xFFFC4018) // (US1) Receiver Holding Register -#define AT91C_US1_BRGR ((AT91_REG *) 0xFFFC4020) // (US1) Baud Rate Generator Register -#define AT91C_US1_IMR ((AT91_REG *) 0xFFFC4010) // (US1) Interrupt Mask Register -#define AT91C_US1_FIDI ((AT91_REG *) 0xFFFC4040) // (US1) FI_DI_Ratio Register -#define AT91C_US1_CR ((AT91_REG *) 0xFFFC4000) // (US1) Control Register -#define AT91C_US1_MR ((AT91_REG *) 0xFFFC4004) // (US1) Mode Register -// ========== Register definition for PDC_US0 peripheral ========== -#define AT91C_US0_TNPR ((AT91_REG *) 0xFFFC0118) // (PDC_US0) Transmit Next Pointer Register -#define AT91C_US0_RNPR ((AT91_REG *) 0xFFFC0110) // (PDC_US0) Receive Next Pointer Register -#define AT91C_US0_TCR ((AT91_REG *) 0xFFFC010C) // (PDC_US0) Transmit Counter Register -#define AT91C_US0_PTCR ((AT91_REG *) 0xFFFC0120) // (PDC_US0) PDC Transfer Control Register -#define AT91C_US0_PTSR ((AT91_REG *) 0xFFFC0124) // (PDC_US0) PDC Transfer Status Register -#define AT91C_US0_TNCR ((AT91_REG *) 0xFFFC011C) // (PDC_US0) Transmit Next Counter Register -#define AT91C_US0_TPR ((AT91_REG *) 0xFFFC0108) // (PDC_US0) Transmit Pointer Register -#define AT91C_US0_RCR ((AT91_REG *) 0xFFFC0104) // (PDC_US0) Receive Counter Register -#define AT91C_US0_RPR ((AT91_REG *) 0xFFFC0100) // (PDC_US0) Receive Pointer Register -#define AT91C_US0_RNCR ((AT91_REG *) 0xFFFC0114) // (PDC_US0) Receive Next Counter Register -// ========== Register definition for US0 peripheral ========== -#define AT91C_US0_BRGR ((AT91_REG *) 0xFFFC0020) // (US0) Baud Rate Generator Register -#define AT91C_US0_NER ((AT91_REG *) 0xFFFC0044) // (US0) Nb Errors Register -#define AT91C_US0_CR ((AT91_REG *) 0xFFFC0000) // (US0) Control Register -#define AT91C_US0_IMR ((AT91_REG *) 0xFFFC0010) // (US0) Interrupt Mask Register -#define AT91C_US0_FIDI ((AT91_REG *) 0xFFFC0040) // (US0) FI_DI_Ratio Register -#define AT91C_US0_TTGR ((AT91_REG *) 0xFFFC0028) // (US0) Transmitter Time-guard Register -#define AT91C_US0_MR ((AT91_REG *) 0xFFFC0004) // (US0) Mode Register -#define AT91C_US0_RTOR ((AT91_REG *) 0xFFFC0024) // (US0) Receiver Time-out Register -#define AT91C_US0_CSR ((AT91_REG *) 0xFFFC0014) // (US0) Channel Status Register -#define AT91C_US0_RHR ((AT91_REG *) 0xFFFC0018) // (US0) Receiver Holding Register -#define AT91C_US0_IDR ((AT91_REG *) 0xFFFC000C) // (US0) Interrupt Disable Register -#define AT91C_US0_THR ((AT91_REG *) 0xFFFC001C) // (US0) Transmitter Holding Register -#define AT91C_US0_IF ((AT91_REG *) 0xFFFC004C) // (US0) IRDA_FILTER Register -#define AT91C_US0_IER ((AT91_REG *) 0xFFFC0008) // (US0) Interrupt Enable Register -// ========== Register definition for PDC_SSC peripheral ========== -#define AT91C_SSC_TNCR ((AT91_REG *) 0xFFFD411C) // (PDC_SSC) Transmit Next Counter Register -#define AT91C_SSC_RPR ((AT91_REG *) 0xFFFD4100) // (PDC_SSC) Receive Pointer Register -#define AT91C_SSC_RNCR ((AT91_REG *) 0xFFFD4114) // (PDC_SSC) Receive Next Counter Register -#define AT91C_SSC_TPR ((AT91_REG *) 0xFFFD4108) // (PDC_SSC) Transmit Pointer Register -#define AT91C_SSC_PTCR ((AT91_REG *) 0xFFFD4120) // (PDC_SSC) PDC Transfer Control Register -#define AT91C_SSC_TCR ((AT91_REG *) 0xFFFD410C) // (PDC_SSC) Transmit Counter Register -#define AT91C_SSC_RCR ((AT91_REG *) 0xFFFD4104) // (PDC_SSC) Receive Counter Register -#define AT91C_SSC_RNPR ((AT91_REG *) 0xFFFD4110) // (PDC_SSC) Receive Next Pointer Register -#define AT91C_SSC_TNPR ((AT91_REG *) 0xFFFD4118) // (PDC_SSC) Transmit Next Pointer Register -#define AT91C_SSC_PTSR ((AT91_REG *) 0xFFFD4124) // (PDC_SSC) PDC Transfer Status Register -// ========== Register definition for SSC peripheral ========== -#define AT91C_SSC_RHR ((AT91_REG *) 0xFFFD4020) // (SSC) Receive Holding Register -#define AT91C_SSC_RSHR ((AT91_REG *) 0xFFFD4030) // (SSC) Receive Sync Holding Register -#define AT91C_SSC_TFMR ((AT91_REG *) 0xFFFD401C) // (SSC) Transmit Frame Mode Register -#define AT91C_SSC_IDR ((AT91_REG *) 0xFFFD4048) // (SSC) Interrupt Disable Register -#define AT91C_SSC_THR ((AT91_REG *) 0xFFFD4024) // (SSC) Transmit Holding Register -#define AT91C_SSC_RCMR ((AT91_REG *) 0xFFFD4010) // (SSC) Receive Clock ModeRegister -#define AT91C_SSC_IER ((AT91_REG *) 0xFFFD4044) // (SSC) Interrupt Enable Register -#define AT91C_SSC_TSHR ((AT91_REG *) 0xFFFD4034) // (SSC) Transmit Sync Holding Register -#define AT91C_SSC_SR ((AT91_REG *) 0xFFFD4040) // (SSC) Status Register -#define AT91C_SSC_CMR ((AT91_REG *) 0xFFFD4004) // (SSC) Clock Mode Register -#define AT91C_SSC_TCMR ((AT91_REG *) 0xFFFD4018) // (SSC) Transmit Clock Mode Register -#define AT91C_SSC_CR ((AT91_REG *) 0xFFFD4000) // (SSC) Control Register -#define AT91C_SSC_IMR ((AT91_REG *) 0xFFFD404C) // (SSC) Interrupt Mask Register -#define AT91C_SSC_RFMR ((AT91_REG *) 0xFFFD4014) // (SSC) Receive Frame Mode Register -// ========== Register definition for TWI peripheral ========== -#define AT91C_TWI_IER ((AT91_REG *) 0xFFFB8024) // (TWI) Interrupt Enable Register -#define AT91C_TWI_CR ((AT91_REG *) 0xFFFB8000) // (TWI) Control Register -#define AT91C_TWI_SR ((AT91_REG *) 0xFFFB8020) // (TWI) Status Register -#define AT91C_TWI_IMR ((AT91_REG *) 0xFFFB802C) // (TWI) Interrupt Mask Register -#define AT91C_TWI_THR ((AT91_REG *) 0xFFFB8034) // (TWI) Transmit Holding Register -#define AT91C_TWI_IDR ((AT91_REG *) 0xFFFB8028) // (TWI) Interrupt Disable Register -#define AT91C_TWI_IADR ((AT91_REG *) 0xFFFB800C) // (TWI) Internal Address Register -#define AT91C_TWI_MMR ((AT91_REG *) 0xFFFB8004) // (TWI) Master Mode Register -#define AT91C_TWI_CWGR ((AT91_REG *) 0xFFFB8010) // (TWI) Clock Waveform Generator Register -#define AT91C_TWI_RHR ((AT91_REG *) 0xFFFB8030) // (TWI) Receive Holding Register -// ========== Register definition for PWMC_CH3 peripheral ========== -#define AT91C_PWMC_CH3_CUPDR ((AT91_REG *) 0xFFFCC270) // (PWMC_CH3) Channel Update Register -#define AT91C_PWMC_CH3_Reserved ((AT91_REG *) 0xFFFCC274) // (PWMC_CH3) Reserved -#define AT91C_PWMC_CH3_CPRDR ((AT91_REG *) 0xFFFCC268) // (PWMC_CH3) Channel Period Register -#define AT91C_PWMC_CH3_CDTYR ((AT91_REG *) 0xFFFCC264) // (PWMC_CH3) Channel Duty Cycle Register -#define AT91C_PWMC_CH3_CCNTR ((AT91_REG *) 0xFFFCC26C) // (PWMC_CH3) Channel Counter Register -#define AT91C_PWMC_CH3_CMR ((AT91_REG *) 0xFFFCC260) // (PWMC_CH3) Channel Mode Register -// ========== Register definition for PWMC_CH2 peripheral ========== -#define AT91C_PWMC_CH2_Reserved ((AT91_REG *) 0xFFFCC254) // (PWMC_CH2) Reserved -#define AT91C_PWMC_CH2_CMR ((AT91_REG *) 0xFFFCC240) // (PWMC_CH2) Channel Mode Register -#define AT91C_PWMC_CH2_CCNTR ((AT91_REG *) 0xFFFCC24C) // (PWMC_CH2) Channel Counter Register -#define AT91C_PWMC_CH2_CPRDR ((AT91_REG *) 0xFFFCC248) // (PWMC_CH2) Channel Period Register -#define AT91C_PWMC_CH2_CUPDR ((AT91_REG *) 0xFFFCC250) // (PWMC_CH2) Channel Update Register -#define AT91C_PWMC_CH2_CDTYR ((AT91_REG *) 0xFFFCC244) // (PWMC_CH2) Channel Duty Cycle Register -// ========== Register definition for PWMC_CH1 peripheral ========== -#define AT91C_PWMC_CH1_Reserved ((AT91_REG *) 0xFFFCC234) // (PWMC_CH1) Reserved -#define AT91C_PWMC_CH1_CUPDR ((AT91_REG *) 0xFFFCC230) // (PWMC_CH1) Channel Update Register -#define AT91C_PWMC_CH1_CPRDR ((AT91_REG *) 0xFFFCC228) // (PWMC_CH1) Channel Period Register -#define AT91C_PWMC_CH1_CCNTR ((AT91_REG *) 0xFFFCC22C) // (PWMC_CH1) Channel Counter Register -#define AT91C_PWMC_CH1_CDTYR ((AT91_REG *) 0xFFFCC224) // (PWMC_CH1) Channel Duty Cycle Register -#define AT91C_PWMC_CH1_CMR ((AT91_REG *) 0xFFFCC220) // (PWMC_CH1) Channel Mode Register -// ========== Register definition for PWMC_CH0 peripheral ========== -#define AT91C_PWMC_CH0_Reserved ((AT91_REG *) 0xFFFCC214) // (PWMC_CH0) Reserved -#define AT91C_PWMC_CH0_CPRDR ((AT91_REG *) 0xFFFCC208) // (PWMC_CH0) Channel Period Register -#define AT91C_PWMC_CH0_CDTYR ((AT91_REG *) 0xFFFCC204) // (PWMC_CH0) Channel Duty Cycle Register -#define AT91C_PWMC_CH0_CMR ((AT91_REG *) 0xFFFCC200) // (PWMC_CH0) Channel Mode Register -#define AT91C_PWMC_CH0_CUPDR ((AT91_REG *) 0xFFFCC210) // (PWMC_CH0) Channel Update Register -#define AT91C_PWMC_CH0_CCNTR ((AT91_REG *) 0xFFFCC20C) // (PWMC_CH0) Channel Counter Register -// ========== Register definition for PWMC peripheral ========== -#define AT91C_PWMC_IDR ((AT91_REG *) 0xFFFCC014) // (PWMC) PWMC Interrupt Disable Register -#define AT91C_PWMC_DIS ((AT91_REG *) 0xFFFCC008) // (PWMC) PWMC Disable Register -#define AT91C_PWMC_IER ((AT91_REG *) 0xFFFCC010) // (PWMC) PWMC Interrupt Enable Register -#define AT91C_PWMC_VR ((AT91_REG *) 0xFFFCC0FC) // (PWMC) PWMC Version Register -#define AT91C_PWMC_ISR ((AT91_REG *) 0xFFFCC01C) // (PWMC) PWMC Interrupt Status Register -#define AT91C_PWMC_SR ((AT91_REG *) 0xFFFCC00C) // (PWMC) PWMC Status Register -#define AT91C_PWMC_IMR ((AT91_REG *) 0xFFFCC018) // (PWMC) PWMC Interrupt Mask Register -#define AT91C_PWMC_MR ((AT91_REG *) 0xFFFCC000) // (PWMC) PWMC Mode Register -#define AT91C_PWMC_ENA ((AT91_REG *) 0xFFFCC004) // (PWMC) PWMC Enable Register -// ========== Register definition for UDP peripheral ========== -#define AT91C_UDP_IMR ((AT91_REG *) 0xFFFB0018) // (UDP) Interrupt Mask Register -#define AT91C_UDP_FADDR ((AT91_REG *) 0xFFFB0008) // (UDP) Function Address Register -#define AT91C_UDP_NUM ((AT91_REG *) 0xFFFB0000) // (UDP) Frame Number Register -#define AT91C_UDP_FDR ((AT91_REG *) 0xFFFB0050) // (UDP) Endpoint FIFO Data Register -#define AT91C_UDP_ISR ((AT91_REG *) 0xFFFB001C) // (UDP) Interrupt Status Register -#define AT91C_UDP_CSR ((AT91_REG *) 0xFFFB0030) // (UDP) Endpoint Control and Status Register -#define AT91C_UDP_IDR ((AT91_REG *) 0xFFFB0014) // (UDP) Interrupt Disable Register -#define AT91C_UDP_ICR ((AT91_REG *) 0xFFFB0020) // (UDP) Interrupt Clear Register -#define AT91C_UDP_RSTEP ((AT91_REG *) 0xFFFB0028) // (UDP) Reset Endpoint Register -#define AT91C_UDP_TXVC ((AT91_REG *) 0xFFFB0074) // (UDP) Transceiver Control Register -#define AT91C_UDP_GLBSTATE ((AT91_REG *) 0xFFFB0004) // (UDP) Global State Register -#define AT91C_UDP_IER ((AT91_REG *) 0xFFFB0010) // (UDP) Interrupt Enable Register -// ========== Register definition for TC0 peripheral ========== -#define AT91C_TC0_SR ((AT91_REG *) 0xFFFA0020) // (TC0) Status Register -#define AT91C_TC0_RC ((AT91_REG *) 0xFFFA001C) // (TC0) Register C -#define AT91C_TC0_RB ((AT91_REG *) 0xFFFA0018) // (TC0) Register B -#define AT91C_TC0_CCR ((AT91_REG *) 0xFFFA0000) // (TC0) Channel Control Register -#define AT91C_TC0_CMR ((AT91_REG *) 0xFFFA0004) // (TC0) Channel Mode Register (Capture Mode / Waveform Mode) -#define AT91C_TC0_IER ((AT91_REG *) 0xFFFA0024) // (TC0) Interrupt Enable Register -#define AT91C_TC0_RA ((AT91_REG *) 0xFFFA0014) // (TC0) Register A -#define AT91C_TC0_IDR ((AT91_REG *) 0xFFFA0028) // (TC0) Interrupt Disable Register -#define AT91C_TC0_CV ((AT91_REG *) 0xFFFA0010) // (TC0) Counter Value -#define AT91C_TC0_IMR ((AT91_REG *) 0xFFFA002C) // (TC0) Interrupt Mask Register -// ========== Register definition for TC1 peripheral ========== -#define AT91C_TC1_RB ((AT91_REG *) 0xFFFA0058) // (TC1) Register B -#define AT91C_TC1_CCR ((AT91_REG *) 0xFFFA0040) // (TC1) Channel Control Register -#define AT91C_TC1_IER ((AT91_REG *) 0xFFFA0064) // (TC1) Interrupt Enable Register -#define AT91C_TC1_IDR ((AT91_REG *) 0xFFFA0068) // (TC1) Interrupt Disable Register -#define AT91C_TC1_SR ((AT91_REG *) 0xFFFA0060) // (TC1) Status Register -#define AT91C_TC1_CMR ((AT91_REG *) 0xFFFA0044) // (TC1) Channel Mode Register (Capture Mode / Waveform Mode) -#define AT91C_TC1_RA ((AT91_REG *) 0xFFFA0054) // (TC1) Register A -#define AT91C_TC1_RC ((AT91_REG *) 0xFFFA005C) // (TC1) Register C -#define AT91C_TC1_IMR ((AT91_REG *) 0xFFFA006C) // (TC1) Interrupt Mask Register -#define AT91C_TC1_CV ((AT91_REG *) 0xFFFA0050) // (TC1) Counter Value -// ========== Register definition for TC2 peripheral ========== -#define AT91C_TC2_CMR ((AT91_REG *) 0xFFFA0084) // (TC2) Channel Mode Register (Capture Mode / Waveform Mode) -#define AT91C_TC2_CCR ((AT91_REG *) 0xFFFA0080) // (TC2) Channel Control Register -#define AT91C_TC2_CV ((AT91_REG *) 0xFFFA0090) // (TC2) Counter Value -#define AT91C_TC2_RA ((AT91_REG *) 0xFFFA0094) // (TC2) Register A -#define AT91C_TC2_RB ((AT91_REG *) 0xFFFA0098) // (TC2) Register B -#define AT91C_TC2_IDR ((AT91_REG *) 0xFFFA00A8) // (TC2) Interrupt Disable Register -#define AT91C_TC2_IMR ((AT91_REG *) 0xFFFA00AC) // (TC2) Interrupt Mask Register -#define AT91C_TC2_RC ((AT91_REG *) 0xFFFA009C) // (TC2) Register C -#define AT91C_TC2_IER ((AT91_REG *) 0xFFFA00A4) // (TC2) Interrupt Enable Register -#define AT91C_TC2_SR ((AT91_REG *) 0xFFFA00A0) // (TC2) Status Register -// ========== Register definition for TCB peripheral ========== -#define AT91C_TCB_BMR ((AT91_REG *) 0xFFFA00C4) // (TCB) TC Block Mode Register -#define AT91C_TCB_BCR ((AT91_REG *) 0xFFFA00C0) // (TCB) TC Block Control Register -// ========== Register definition for CAN_MB0 peripheral ========== -#define AT91C_CAN_MB0_MDL ((AT91_REG *) 0xFFFD0214) // (CAN_MB0) MailBox Data Low Register -#define AT91C_CAN_MB0_MAM ((AT91_REG *) 0xFFFD0204) // (CAN_MB0) MailBox Acceptance Mask Register -#define AT91C_CAN_MB0_MCR ((AT91_REG *) 0xFFFD021C) // (CAN_MB0) MailBox Control Register -#define AT91C_CAN_MB0_MID ((AT91_REG *) 0xFFFD0208) // (CAN_MB0) MailBox ID Register -#define AT91C_CAN_MB0_MSR ((AT91_REG *) 0xFFFD0210) // (CAN_MB0) MailBox Status Register -#define AT91C_CAN_MB0_MFID ((AT91_REG *) 0xFFFD020C) // (CAN_MB0) MailBox Family ID Register -#define AT91C_CAN_MB0_MDH ((AT91_REG *) 0xFFFD0218) // (CAN_MB0) MailBox Data High Register -#define AT91C_CAN_MB0_MMR ((AT91_REG *) 0xFFFD0200) // (CAN_MB0) MailBox Mode Register -// ========== Register definition for CAN_MB1 peripheral ========== -#define AT91C_CAN_MB1_MDL ((AT91_REG *) 0xFFFD0234) // (CAN_MB1) MailBox Data Low Register -#define AT91C_CAN_MB1_MID ((AT91_REG *) 0xFFFD0228) // (CAN_MB1) MailBox ID Register -#define AT91C_CAN_MB1_MMR ((AT91_REG *) 0xFFFD0220) // (CAN_MB1) MailBox Mode Register -#define AT91C_CAN_MB1_MSR ((AT91_REG *) 0xFFFD0230) // (CAN_MB1) MailBox Status Register -#define AT91C_CAN_MB1_MAM ((AT91_REG *) 0xFFFD0224) // (CAN_MB1) MailBox Acceptance Mask Register -#define AT91C_CAN_MB1_MDH ((AT91_REG *) 0xFFFD0238) // (CAN_MB1) MailBox Data High Register -#define AT91C_CAN_MB1_MCR ((AT91_REG *) 0xFFFD023C) // (CAN_MB1) MailBox Control Register -#define AT91C_CAN_MB1_MFID ((AT91_REG *) 0xFFFD022C) // (CAN_MB1) MailBox Family ID Register -// ========== Register definition for CAN_MB2 peripheral ========== -#define AT91C_CAN_MB2_MCR ((AT91_REG *) 0xFFFD025C) // (CAN_MB2) MailBox Control Register -#define AT91C_CAN_MB2_MDH ((AT91_REG *) 0xFFFD0258) // (CAN_MB2) MailBox Data High Register -#define AT91C_CAN_MB2_MID ((AT91_REG *) 0xFFFD0248) // (CAN_MB2) MailBox ID Register -#define AT91C_CAN_MB2_MDL ((AT91_REG *) 0xFFFD0254) // (CAN_MB2) MailBox Data Low Register -#define AT91C_CAN_MB2_MMR ((AT91_REG *) 0xFFFD0240) // (CAN_MB2) MailBox Mode Register -#define AT91C_CAN_MB2_MAM ((AT91_REG *) 0xFFFD0244) // (CAN_MB2) MailBox Acceptance Mask Register -#define AT91C_CAN_MB2_MFID ((AT91_REG *) 0xFFFD024C) // (CAN_MB2) MailBox Family ID Register -#define AT91C_CAN_MB2_MSR ((AT91_REG *) 0xFFFD0250) // (CAN_MB2) MailBox Status Register -// ========== Register definition for CAN_MB3 peripheral ========== -#define AT91C_CAN_MB3_MFID ((AT91_REG *) 0xFFFD026C) // (CAN_MB3) MailBox Family ID Register -#define AT91C_CAN_MB3_MAM ((AT91_REG *) 0xFFFD0264) // (CAN_MB3) MailBox Acceptance Mask Register -#define AT91C_CAN_MB3_MID ((AT91_REG *) 0xFFFD0268) // (CAN_MB3) MailBox ID Register -#define AT91C_CAN_MB3_MCR ((AT91_REG *) 0xFFFD027C) // (CAN_MB3) MailBox Control Register -#define AT91C_CAN_MB3_MMR ((AT91_REG *) 0xFFFD0260) // (CAN_MB3) MailBox Mode Register -#define AT91C_CAN_MB3_MSR ((AT91_REG *) 0xFFFD0270) // (CAN_MB3) MailBox Status Register -#define AT91C_CAN_MB3_MDL ((AT91_REG *) 0xFFFD0274) // (CAN_MB3) MailBox Data Low Register -#define AT91C_CAN_MB3_MDH ((AT91_REG *) 0xFFFD0278) // (CAN_MB3) MailBox Data High Register -// ========== Register definition for CAN_MB4 peripheral ========== -#define AT91C_CAN_MB4_MID ((AT91_REG *) 0xFFFD0288) // (CAN_MB4) MailBox ID Register -#define AT91C_CAN_MB4_MMR ((AT91_REG *) 0xFFFD0280) // (CAN_MB4) MailBox Mode Register -#define AT91C_CAN_MB4_MDH ((AT91_REG *) 0xFFFD0298) // (CAN_MB4) MailBox Data High Register -#define AT91C_CAN_MB4_MFID ((AT91_REG *) 0xFFFD028C) // (CAN_MB4) MailBox Family ID Register -#define AT91C_CAN_MB4_MSR ((AT91_REG *) 0xFFFD0290) // (CAN_MB4) MailBox Status Register -#define AT91C_CAN_MB4_MCR ((AT91_REG *) 0xFFFD029C) // (CAN_MB4) MailBox Control Register -#define AT91C_CAN_MB4_MDL ((AT91_REG *) 0xFFFD0294) // (CAN_MB4) MailBox Data Low Register -#define AT91C_CAN_MB4_MAM ((AT91_REG *) 0xFFFD0284) // (CAN_MB4) MailBox Acceptance Mask Register -// ========== Register definition for CAN_MB5 peripheral ========== -#define AT91C_CAN_MB5_MSR ((AT91_REG *) 0xFFFD02B0) // (CAN_MB5) MailBox Status Register -#define AT91C_CAN_MB5_MCR ((AT91_REG *) 0xFFFD02BC) // (CAN_MB5) MailBox Control Register -#define AT91C_CAN_MB5_MFID ((AT91_REG *) 0xFFFD02AC) // (CAN_MB5) MailBox Family ID Register -#define AT91C_CAN_MB5_MDH ((AT91_REG *) 0xFFFD02B8) // (CAN_MB5) MailBox Data High Register -#define AT91C_CAN_MB5_MID ((AT91_REG *) 0xFFFD02A8) // (CAN_MB5) MailBox ID Register -#define AT91C_CAN_MB5_MMR ((AT91_REG *) 0xFFFD02A0) // (CAN_MB5) MailBox Mode Register -#define AT91C_CAN_MB5_MDL ((AT91_REG *) 0xFFFD02B4) // (CAN_MB5) MailBox Data Low Register -#define AT91C_CAN_MB5_MAM ((AT91_REG *) 0xFFFD02A4) // (CAN_MB5) MailBox Acceptance Mask Register -// ========== Register definition for CAN_MB6 peripheral ========== -#define AT91C_CAN_MB6_MFID ((AT91_REG *) 0xFFFD02CC) // (CAN_MB6) MailBox Family ID Register -#define AT91C_CAN_MB6_MID ((AT91_REG *) 0xFFFD02C8) // (CAN_MB6) MailBox ID Register -#define AT91C_CAN_MB6_MAM ((AT91_REG *) 0xFFFD02C4) // (CAN_MB6) MailBox Acceptance Mask Register -#define AT91C_CAN_MB6_MSR ((AT91_REG *) 0xFFFD02D0) // (CAN_MB6) MailBox Status Register -#define AT91C_CAN_MB6_MDL ((AT91_REG *) 0xFFFD02D4) // (CAN_MB6) MailBox Data Low Register -#define AT91C_CAN_MB6_MCR ((AT91_REG *) 0xFFFD02DC) // (CAN_MB6) MailBox Control Register -#define AT91C_CAN_MB6_MDH ((AT91_REG *) 0xFFFD02D8) // (CAN_MB6) MailBox Data High Register -#define AT91C_CAN_MB6_MMR ((AT91_REG *) 0xFFFD02C0) // (CAN_MB6) MailBox Mode Register -// ========== Register definition for CAN_MB7 peripheral ========== -#define AT91C_CAN_MB7_MCR ((AT91_REG *) 0xFFFD02FC) // (CAN_MB7) MailBox Control Register -#define AT91C_CAN_MB7_MDH ((AT91_REG *) 0xFFFD02F8) // (CAN_MB7) MailBox Data High Register -#define AT91C_CAN_MB7_MFID ((AT91_REG *) 0xFFFD02EC) // (CAN_MB7) MailBox Family ID Register -#define AT91C_CAN_MB7_MDL ((AT91_REG *) 0xFFFD02F4) // (CAN_MB7) MailBox Data Low Register -#define AT91C_CAN_MB7_MID ((AT91_REG *) 0xFFFD02E8) // (CAN_MB7) MailBox ID Register -#define AT91C_CAN_MB7_MMR ((AT91_REG *) 0xFFFD02E0) // (CAN_MB7) MailBox Mode Register -#define AT91C_CAN_MB7_MAM ((AT91_REG *) 0xFFFD02E4) // (CAN_MB7) MailBox Acceptance Mask Register -#define AT91C_CAN_MB7_MSR ((AT91_REG *) 0xFFFD02F0) // (CAN_MB7) MailBox Status Register -// ========== Register definition for CAN peripheral ========== -#define AT91C_CAN_TCR ((AT91_REG *) 0xFFFD0024) // (CAN) Transfer Command Register -#define AT91C_CAN_IMR ((AT91_REG *) 0xFFFD000C) // (CAN) Interrupt Mask Register -#define AT91C_CAN_IER ((AT91_REG *) 0xFFFD0004) // (CAN) Interrupt Enable Register -#define AT91C_CAN_ECR ((AT91_REG *) 0xFFFD0020) // (CAN) Error Counter Register -#define AT91C_CAN_TIMESTP ((AT91_REG *) 0xFFFD001C) // (CAN) Time Stamp Register -#define AT91C_CAN_MR ((AT91_REG *) 0xFFFD0000) // (CAN) Mode Register -#define AT91C_CAN_IDR ((AT91_REG *) 0xFFFD0008) // (CAN) Interrupt Disable Register -#define AT91C_CAN_ACR ((AT91_REG *) 0xFFFD0028) // (CAN) Abort Command Register -#define AT91C_CAN_TIM ((AT91_REG *) 0xFFFD0018) // (CAN) Timer Register -#define AT91C_CAN_SR ((AT91_REG *) 0xFFFD0010) // (CAN) Status Register -#define AT91C_CAN_BR ((AT91_REG *) 0xFFFD0014) // (CAN) Baudrate Register -#define AT91C_CAN_VR ((AT91_REG *) 0xFFFD00FC) // (CAN) Version Register -// ========== Register definition for EMAC peripheral ========== -#define AT91C_EMAC_ISR ((AT91_REG *) 0xFFFDC024) // (EMAC) Interrupt Status Register -#define AT91C_EMAC_SA4H ((AT91_REG *) 0xFFFDC0B4) // (EMAC) Specific Address 4 Top, Last 2 bytes -#define AT91C_EMAC_SA1L ((AT91_REG *) 0xFFFDC098) // (EMAC) Specific Address 1 Bottom, First 4 bytes -#define AT91C_EMAC_ELE ((AT91_REG *) 0xFFFDC078) // (EMAC) Excessive Length Errors Register -#define AT91C_EMAC_LCOL ((AT91_REG *) 0xFFFDC05C) // (EMAC) Late Collision Register -#define AT91C_EMAC_RLE ((AT91_REG *) 0xFFFDC088) // (EMAC) Receive Length Field Mismatch Register -#define AT91C_EMAC_WOL ((AT91_REG *) 0xFFFDC0C4) // (EMAC) Wake On LAN Register -#define AT91C_EMAC_DTF ((AT91_REG *) 0xFFFDC058) // (EMAC) Deferred Transmission Frame Register -#define AT91C_EMAC_TUND ((AT91_REG *) 0xFFFDC064) // (EMAC) Transmit Underrun Error Register -#define AT91C_EMAC_NCR ((AT91_REG *) 0xFFFDC000) // (EMAC) Network Control Register -#define AT91C_EMAC_SA4L ((AT91_REG *) 0xFFFDC0B0) // (EMAC) Specific Address 4 Bottom, First 4 bytes -#define AT91C_EMAC_RSR ((AT91_REG *) 0xFFFDC020) // (EMAC) Receive Status Register -#define AT91C_EMAC_SA3L ((AT91_REG *) 0xFFFDC0A8) // (EMAC) Specific Address 3 Bottom, First 4 bytes -#define AT91C_EMAC_TSR ((AT91_REG *) 0xFFFDC014) // (EMAC) Transmit Status Register -#define AT91C_EMAC_IDR ((AT91_REG *) 0xFFFDC02C) // (EMAC) Interrupt Disable Register -#define AT91C_EMAC_RSE ((AT91_REG *) 0xFFFDC074) // (EMAC) Receive Symbol Errors Register -#define AT91C_EMAC_ECOL ((AT91_REG *) 0xFFFDC060) // (EMAC) Excessive Collision Register -#define AT91C_EMAC_TID ((AT91_REG *) 0xFFFDC0B8) // (EMAC) Type ID Checking Register -#define AT91C_EMAC_HRB ((AT91_REG *) 0xFFFDC090) // (EMAC) Hash Address Bottom[31:0] -#define AT91C_EMAC_TBQP ((AT91_REG *) 0xFFFDC01C) // (EMAC) Transmit Buffer Queue Pointer -#define AT91C_EMAC_USRIO ((AT91_REG *) 0xFFFDC0C0) // (EMAC) USER Input/Output Register -#define AT91C_EMAC_PTR ((AT91_REG *) 0xFFFDC038) // (EMAC) Pause Time Register -#define AT91C_EMAC_SA2H ((AT91_REG *) 0xFFFDC0A4) // (EMAC) Specific Address 2 Top, Last 2 bytes -#define AT91C_EMAC_ROV ((AT91_REG *) 0xFFFDC070) // (EMAC) Receive Overrun Errors Register -#define AT91C_EMAC_ALE ((AT91_REG *) 0xFFFDC054) // (EMAC) Alignment Error Register -#define AT91C_EMAC_RJA ((AT91_REG *) 0xFFFDC07C) // (EMAC) Receive Jabbers Register -#define AT91C_EMAC_RBQP ((AT91_REG *) 0xFFFDC018) // (EMAC) Receive Buffer Queue Pointer -#define AT91C_EMAC_TPF ((AT91_REG *) 0xFFFDC08C) // (EMAC) Transmitted Pause Frames Register -#define AT91C_EMAC_NCFGR ((AT91_REG *) 0xFFFDC004) // (EMAC) Network Configuration Register -#define AT91C_EMAC_HRT ((AT91_REG *) 0xFFFDC094) // (EMAC) Hash Address Top[63:32] -#define AT91C_EMAC_USF ((AT91_REG *) 0xFFFDC080) // (EMAC) Undersize Frames Register -#define AT91C_EMAC_FCSE ((AT91_REG *) 0xFFFDC050) // (EMAC) Frame Check Sequence Error Register -#define AT91C_EMAC_TPQ ((AT91_REG *) 0xFFFDC0BC) // (EMAC) Transmit Pause Quantum Register -#define AT91C_EMAC_MAN ((AT91_REG *) 0xFFFDC034) // (EMAC) PHY Maintenance Register -#define AT91C_EMAC_FTO ((AT91_REG *) 0xFFFDC040) // (EMAC) Frames Transmitted OK Register -#define AT91C_EMAC_REV ((AT91_REG *) 0xFFFDC0FC) // (EMAC) Revision Register -#define AT91C_EMAC_IMR ((AT91_REG *) 0xFFFDC030) // (EMAC) Interrupt Mask Register -#define AT91C_EMAC_SCF ((AT91_REG *) 0xFFFDC044) // (EMAC) Single Collision Frame Register -#define AT91C_EMAC_PFR ((AT91_REG *) 0xFFFDC03C) // (EMAC) Pause Frames received Register -#define AT91C_EMAC_MCF ((AT91_REG *) 0xFFFDC048) // (EMAC) Multiple Collision Frame Register -#define AT91C_EMAC_NSR ((AT91_REG *) 0xFFFDC008) // (EMAC) Network Status Register -#define AT91C_EMAC_SA2L ((AT91_REG *) 0xFFFDC0A0) // (EMAC) Specific Address 2 Bottom, First 4 bytes -#define AT91C_EMAC_FRO ((AT91_REG *) 0xFFFDC04C) // (EMAC) Frames Received OK Register -#define AT91C_EMAC_IER ((AT91_REG *) 0xFFFDC028) // (EMAC) Interrupt Enable Register -#define AT91C_EMAC_SA1H ((AT91_REG *) 0xFFFDC09C) // (EMAC) Specific Address 1 Top, Last 2 bytes -#define AT91C_EMAC_CSE ((AT91_REG *) 0xFFFDC068) // (EMAC) Carrier Sense Error Register -#define AT91C_EMAC_SA3H ((AT91_REG *) 0xFFFDC0AC) // (EMAC) Specific Address 3 Top, Last 2 bytes -#define AT91C_EMAC_RRE ((AT91_REG *) 0xFFFDC06C) // (EMAC) Receive Ressource Error Register -#define AT91C_EMAC_STE ((AT91_REG *) 0xFFFDC084) // (EMAC) SQE Test Error Register -// ========== Register definition for PDC_ADC peripheral ========== -#define AT91C_ADC_PTSR ((AT91_REG *) 0xFFFD8124) // (PDC_ADC) PDC Transfer Status Register -#define AT91C_ADC_PTCR ((AT91_REG *) 0xFFFD8120) // (PDC_ADC) PDC Transfer Control Register -#define AT91C_ADC_TNPR ((AT91_REG *) 0xFFFD8118) // (PDC_ADC) Transmit Next Pointer Register -#define AT91C_ADC_TNCR ((AT91_REG *) 0xFFFD811C) // (PDC_ADC) Transmit Next Counter Register -#define AT91C_ADC_RNPR ((AT91_REG *) 0xFFFD8110) // (PDC_ADC) Receive Next Pointer Register -#define AT91C_ADC_RNCR ((AT91_REG *) 0xFFFD8114) // (PDC_ADC) Receive Next Counter Register -#define AT91C_ADC_RPR ((AT91_REG *) 0xFFFD8100) // (PDC_ADC) Receive Pointer Register -#define AT91C_ADC_TCR ((AT91_REG *) 0xFFFD810C) // (PDC_ADC) Transmit Counter Register -#define AT91C_ADC_TPR ((AT91_REG *) 0xFFFD8108) // (PDC_ADC) Transmit Pointer Register -#define AT91C_ADC_RCR ((AT91_REG *) 0xFFFD8104) // (PDC_ADC) Receive Counter Register -// ========== Register definition for ADC peripheral ========== -#define AT91C_ADC_CDR2 ((AT91_REG *) 0xFFFD8038) // (ADC) ADC Channel Data Register 2 -#define AT91C_ADC_CDR3 ((AT91_REG *) 0xFFFD803C) // (ADC) ADC Channel Data Register 3 -#define AT91C_ADC_CDR0 ((AT91_REG *) 0xFFFD8030) // (ADC) ADC Channel Data Register 0 -#define AT91C_ADC_CDR5 ((AT91_REG *) 0xFFFD8044) // (ADC) ADC Channel Data Register 5 -#define AT91C_ADC_CHDR ((AT91_REG *) 0xFFFD8014) // (ADC) ADC Channel Disable Register -#define AT91C_ADC_SR ((AT91_REG *) 0xFFFD801C) // (ADC) ADC Status Register -#define AT91C_ADC_CDR4 ((AT91_REG *) 0xFFFD8040) // (ADC) ADC Channel Data Register 4 -#define AT91C_ADC_CDR1 ((AT91_REG *) 0xFFFD8034) // (ADC) ADC Channel Data Register 1 -#define AT91C_ADC_LCDR ((AT91_REG *) 0xFFFD8020) // (ADC) ADC Last Converted Data Register -#define AT91C_ADC_IDR ((AT91_REG *) 0xFFFD8028) // (ADC) ADC Interrupt Disable Register -#define AT91C_ADC_CR ((AT91_REG *) 0xFFFD8000) // (ADC) ADC Control Register -#define AT91C_ADC_CDR7 ((AT91_REG *) 0xFFFD804C) // (ADC) ADC Channel Data Register 7 -#define AT91C_ADC_CDR6 ((AT91_REG *) 0xFFFD8048) // (ADC) ADC Channel Data Register 6 -#define AT91C_ADC_IER ((AT91_REG *) 0xFFFD8024) // (ADC) ADC Interrupt Enable Register -#define AT91C_ADC_CHER ((AT91_REG *) 0xFFFD8010) // (ADC) ADC Channel Enable Register -#define AT91C_ADC_CHSR ((AT91_REG *) 0xFFFD8018) // (ADC) ADC Channel Status Register -#define AT91C_ADC_MR ((AT91_REG *) 0xFFFD8004) // (ADC) ADC Mode Register -#define AT91C_ADC_IMR ((AT91_REG *) 0xFFFD802C) // (ADC) ADC Interrupt Mask Register -// ========== Register definition for PDC_AES peripheral ========== -#define AT91C_AES_TPR ((AT91_REG *) 0xFFFA4108) // (PDC_AES) Transmit Pointer Register -#define AT91C_AES_PTCR ((AT91_REG *) 0xFFFA4120) // (PDC_AES) PDC Transfer Control Register -#define AT91C_AES_RNPR ((AT91_REG *) 0xFFFA4110) // (PDC_AES) Receive Next Pointer Register -#define AT91C_AES_TNCR ((AT91_REG *) 0xFFFA411C) // (PDC_AES) Transmit Next Counter Register -#define AT91C_AES_TCR ((AT91_REG *) 0xFFFA410C) // (PDC_AES) Transmit Counter Register -#define AT91C_AES_RCR ((AT91_REG *) 0xFFFA4104) // (PDC_AES) Receive Counter Register -#define AT91C_AES_RNCR ((AT91_REG *) 0xFFFA4114) // (PDC_AES) Receive Next Counter Register -#define AT91C_AES_TNPR ((AT91_REG *) 0xFFFA4118) // (PDC_AES) Transmit Next Pointer Register -#define AT91C_AES_RPR ((AT91_REG *) 0xFFFA4100) // (PDC_AES) Receive Pointer Register -#define AT91C_AES_PTSR ((AT91_REG *) 0xFFFA4124) // (PDC_AES) PDC Transfer Status Register -// ========== Register definition for AES peripheral ========== -#define AT91C_AES_IVxR ((AT91_REG *) 0xFFFA4060) // (AES) Initialization Vector x Register -#define AT91C_AES_MR ((AT91_REG *) 0xFFFA4004) // (AES) Mode Register -#define AT91C_AES_VR ((AT91_REG *) 0xFFFA40FC) // (AES) AES Version Register -#define AT91C_AES_ODATAxR ((AT91_REG *) 0xFFFA4050) // (AES) Output Data x Register -#define AT91C_AES_IDATAxR ((AT91_REG *) 0xFFFA4040) // (AES) Input Data x Register -#define AT91C_AES_CR ((AT91_REG *) 0xFFFA4000) // (AES) Control Register -#define AT91C_AES_IDR ((AT91_REG *) 0xFFFA4014) // (AES) Interrupt Disable Register -#define AT91C_AES_IMR ((AT91_REG *) 0xFFFA4018) // (AES) Interrupt Mask Register -#define AT91C_AES_IER ((AT91_REG *) 0xFFFA4010) // (AES) Interrupt Enable Register -#define AT91C_AES_KEYWxR ((AT91_REG *) 0xFFFA4020) // (AES) Key Word x Register -#define AT91C_AES_ISR ((AT91_REG *) 0xFFFA401C) // (AES) Interrupt Status Register -// ========== Register definition for PDC_TDES peripheral ========== -#define AT91C_TDES_RNCR ((AT91_REG *) 0xFFFA8114) // (PDC_TDES) Receive Next Counter Register -#define AT91C_TDES_TCR ((AT91_REG *) 0xFFFA810C) // (PDC_TDES) Transmit Counter Register -#define AT91C_TDES_RCR ((AT91_REG *) 0xFFFA8104) // (PDC_TDES) Receive Counter Register -#define AT91C_TDES_TNPR ((AT91_REG *) 0xFFFA8118) // (PDC_TDES) Transmit Next Pointer Register -#define AT91C_TDES_RNPR ((AT91_REG *) 0xFFFA8110) // (PDC_TDES) Receive Next Pointer Register -#define AT91C_TDES_RPR ((AT91_REG *) 0xFFFA8100) // (PDC_TDES) Receive Pointer Register -#define AT91C_TDES_TNCR ((AT91_REG *) 0xFFFA811C) // (PDC_TDES) Transmit Next Counter Register -#define AT91C_TDES_TPR ((AT91_REG *) 0xFFFA8108) // (PDC_TDES) Transmit Pointer Register -#define AT91C_TDES_PTSR ((AT91_REG *) 0xFFFA8124) // (PDC_TDES) PDC Transfer Status Register -#define AT91C_TDES_PTCR ((AT91_REG *) 0xFFFA8120) // (PDC_TDES) PDC Transfer Control Register -// ========== Register definition for TDES peripheral ========== -#define AT91C_TDES_KEY2WxR ((AT91_REG *) 0xFFFA8028) // (TDES) Key 2 Word x Register -#define AT91C_TDES_KEY3WxR ((AT91_REG *) 0xFFFA8030) // (TDES) Key 3 Word x Register -#define AT91C_TDES_IDR ((AT91_REG *) 0xFFFA8014) // (TDES) Interrupt Disable Register -#define AT91C_TDES_VR ((AT91_REG *) 0xFFFA80FC) // (TDES) TDES Version Register -#define AT91C_TDES_IVxR ((AT91_REG *) 0xFFFA8060) // (TDES) Initialization Vector x Register -#define AT91C_TDES_ODATAxR ((AT91_REG *) 0xFFFA8050) // (TDES) Output Data x Register -#define AT91C_TDES_IMR ((AT91_REG *) 0xFFFA8018) // (TDES) Interrupt Mask Register -#define AT91C_TDES_MR ((AT91_REG *) 0xFFFA8004) // (TDES) Mode Register -#define AT91C_TDES_CR ((AT91_REG *) 0xFFFA8000) // (TDES) Control Register -#define AT91C_TDES_IER ((AT91_REG *) 0xFFFA8010) // (TDES) Interrupt Enable Register -#define AT91C_TDES_ISR ((AT91_REG *) 0xFFFA801C) // (TDES) Interrupt Status Register -#define AT91C_TDES_IDATAxR ((AT91_REG *) 0xFFFA8040) // (TDES) Input Data x Register -#define AT91C_TDES_KEY1WxR ((AT91_REG *) 0xFFFA8020) // (TDES) Key 1 Word x Register - -// ***************************************************************************** -// PIO DEFINITIONS FOR AT91SAM7X256 -// ***************************************************************************** -#define AT91C_PIO_PA0 ((unsigned int) 1 << 0) // Pin Controlled by PA0 -#define AT91C_PA0_RXD0 ((unsigned int) AT91C_PIO_PA0) // USART 0 Receive Data -#define AT91C_PIO_PA1 ((unsigned int) 1 << 1) // Pin Controlled by PA1 -#define AT91C_PA1_TXD0 ((unsigned int) AT91C_PIO_PA1) // USART 0 Transmit Data -#define AT91C_PIO_PA10 ((unsigned int) 1 << 10) // Pin Controlled by PA10 -#define AT91C_PA10_TWD ((unsigned int) AT91C_PIO_PA10) // TWI Two-wire Serial Data -#define AT91C_PIO_PA11 ((unsigned int) 1 << 11) // Pin Controlled by PA11 -#define AT91C_PA11_TWCK ((unsigned int) AT91C_PIO_PA11) // TWI Two-wire Serial Clock -#define AT91C_PIO_PA12 ((unsigned int) 1 << 12) // Pin Controlled by PA12 -#define AT91C_PA12_NPCS00 ((unsigned int) AT91C_PIO_PA12) // SPI 0 Peripheral Chip Select 0 -#define AT91C_PIO_PA13 ((unsigned int) 1 << 13) // Pin Controlled by PA13 -#define AT91C_PA13_NPCS01 ((unsigned int) AT91C_PIO_PA13) // SPI 0 Peripheral Chip Select 1 -#define AT91C_PA13_PCK1 ((unsigned int) AT91C_PIO_PA13) // PMC Programmable Clock Output 1 -#define AT91C_PIO_PA14 ((unsigned int) 1 << 14) // Pin Controlled by PA14 -#define AT91C_PA14_NPCS02 ((unsigned int) AT91C_PIO_PA14) // SPI 0 Peripheral Chip Select 2 -#define AT91C_PA14_IRQ1 ((unsigned int) AT91C_PIO_PA14) // External Interrupt 1 -#define AT91C_PIO_PA15 ((unsigned int) 1 << 15) // Pin Controlled by PA15 -#define AT91C_PA15_NPCS03 ((unsigned int) AT91C_PIO_PA15) // SPI 0 Peripheral Chip Select 3 -#define AT91C_PA15_TCLK2 ((unsigned int) AT91C_PIO_PA15) // Timer Counter 2 external clock input -#define AT91C_PIO_PA16 ((unsigned int) 1 << 16) // Pin Controlled by PA16 -#define AT91C_PA16_MISO0 ((unsigned int) AT91C_PIO_PA16) // SPI 0 Master In Slave -#define AT91C_PIO_PA17 ((unsigned int) 1 << 17) // Pin Controlled by PA17 -#define AT91C_PA17_MOSI0 ((unsigned int) AT91C_PIO_PA17) // SPI 0 Master Out Slave -#define AT91C_PIO_PA18 ((unsigned int) 1 << 18) // Pin Controlled by PA18 -#define AT91C_PA18_SPCK0 ((unsigned int) AT91C_PIO_PA18) // SPI 0 Serial Clock -#define AT91C_PIO_PA19 ((unsigned int) 1 << 19) // Pin Controlled by PA19 -#define AT91C_PA19_CANRX ((unsigned int) AT91C_PIO_PA19) // CAN Receive -#define AT91C_PIO_PA2 ((unsigned int) 1 << 2) // Pin Controlled by PA2 -#define AT91C_PA2_SCK0 ((unsigned int) AT91C_PIO_PA2) // USART 0 Serial Clock -#define AT91C_PA2_NPCS11 ((unsigned int) AT91C_PIO_PA2) // SPI 1 Peripheral Chip Select 1 -#define AT91C_PIO_PA20 ((unsigned int) 1 << 20) // Pin Controlled by PA20 -#define AT91C_PA20_CANTX ((unsigned int) AT91C_PIO_PA20) // CAN Transmit -#define AT91C_PIO_PA21 ((unsigned int) 1 << 21) // Pin Controlled by PA21 -#define AT91C_PA21_TF ((unsigned int) AT91C_PIO_PA21) // SSC Transmit Frame Sync -#define AT91C_PA21_NPCS10 ((unsigned int) AT91C_PIO_PA21) // SPI 1 Peripheral Chip Select 0 -#define AT91C_PIO_PA22 ((unsigned int) 1 << 22) // Pin Controlled by PA22 -#define AT91C_PA22_TK ((unsigned int) AT91C_PIO_PA22) // SSC Transmit Clock -#define AT91C_PA22_SPCK1 ((unsigned int) AT91C_PIO_PA22) // SPI 1 Serial Clock -#define AT91C_PIO_PA23 ((unsigned int) 1 << 23) // Pin Controlled by PA23 -#define AT91C_PA23_TD ((unsigned int) AT91C_PIO_PA23) // SSC Transmit data -#define AT91C_PA23_MOSI1 ((unsigned int) AT91C_PIO_PA23) // SPI 1 Master Out Slave -#define AT91C_PIO_PA24 ((unsigned int) 1 << 24) // Pin Controlled by PA24 -#define AT91C_PA24_RD ((unsigned int) AT91C_PIO_PA24) // SSC Receive Data -#define AT91C_PA24_MISO1 ((unsigned int) AT91C_PIO_PA24) // SPI 1 Master In Slave -#define AT91C_PIO_PA25 ((unsigned int) 1 << 25) // Pin Controlled by PA25 -#define AT91C_PA25_RK ((unsigned int) AT91C_PIO_PA25) // SSC Receive Clock -#define AT91C_PA25_NPCS11 ((unsigned int) AT91C_PIO_PA25) // SPI 1 Peripheral Chip Select 1 -#define AT91C_PIO_PA26 ((unsigned int) 1 << 26) // Pin Controlled by PA26 -#define AT91C_PA26_RF ((unsigned int) AT91C_PIO_PA26) // SSC Receive Frame Sync -#define AT91C_PA26_NPCS12 ((unsigned int) AT91C_PIO_PA26) // SPI 1 Peripheral Chip Select 2 -#define AT91C_PIO_PA27 ((unsigned int) 1 << 27) // Pin Controlled by PA27 -#define AT91C_PA27_DRXD ((unsigned int) AT91C_PIO_PA27) // DBGU Debug Receive Data -#define AT91C_PA27_PCK3 ((unsigned int) AT91C_PIO_PA27) // PMC Programmable Clock Output 3 -#define AT91C_PIO_PA28 ((unsigned int) 1 << 28) // Pin Controlled by PA28 -#define AT91C_PA28_DTXD ((unsigned int) AT91C_PIO_PA28) // DBGU Debug Transmit Data -#define AT91C_PIO_PA29 ((unsigned int) 1 << 29) // Pin Controlled by PA29 -#define AT91C_PA29_FIQ ((unsigned int) AT91C_PIO_PA29) // AIC Fast Interrupt Input -#define AT91C_PA29_NPCS13 ((unsigned int) AT91C_PIO_PA29) // SPI 1 Peripheral Chip Select 3 -#define AT91C_PIO_PA3 ((unsigned int) 1 << 3) // Pin Controlled by PA3 -#define AT91C_PA3_RTS0 ((unsigned int) AT91C_PIO_PA3) // USART 0 Ready To Send -#define AT91C_PA3_NPCS12 ((unsigned int) AT91C_PIO_PA3) // SPI 1 Peripheral Chip Select 2 -#define AT91C_PIO_PA30 ((unsigned int) 1 << 30) // Pin Controlled by PA30 -#define AT91C_PA30_IRQ0 ((unsigned int) AT91C_PIO_PA30) // External Interrupt 0 -#define AT91C_PA30_PCK2 ((unsigned int) AT91C_PIO_PA30) // PMC Programmable Clock Output 2 -#define AT91C_PIO_PA4 ((unsigned int) 1 << 4) // Pin Controlled by PA4 -#define AT91C_PA4_CTS0 ((unsigned int) AT91C_PIO_PA4) // USART 0 Clear To Send -#define AT91C_PA4_NPCS13 ((unsigned int) AT91C_PIO_PA4) // SPI 1 Peripheral Chip Select 3 -#define AT91C_PIO_PA5 ((unsigned int) 1 << 5) // Pin Controlled by PA5 -#define AT91C_PA5_RXD1 ((unsigned int) AT91C_PIO_PA5) // USART 1 Receive Data -#define AT91C_PIO_PA6 ((unsigned int) 1 << 6) // Pin Controlled by PA6 -#define AT91C_PA6_TXD1 ((unsigned int) AT91C_PIO_PA6) // USART 1 Transmit Data -#define AT91C_PIO_PA7 ((unsigned int) 1 << 7) // Pin Controlled by PA7 -#define AT91C_PA7_SCK1 ((unsigned int) AT91C_PIO_PA7) // USART 1 Serial Clock -#define AT91C_PA7_NPCS01 ((unsigned int) AT91C_PIO_PA7) // SPI 0 Peripheral Chip Select 1 -#define AT91C_PIO_PA8 ((unsigned int) 1 << 8) // Pin Controlled by PA8 -#define AT91C_PA8_RTS1 ((unsigned int) AT91C_PIO_PA8) // USART 1 Ready To Send -#define AT91C_PA8_NPCS02 ((unsigned int) AT91C_PIO_PA8) // SPI 0 Peripheral Chip Select 2 -#define AT91C_PIO_PA9 ((unsigned int) 1 << 9) // Pin Controlled by PA9 -#define AT91C_PA9_CTS1 ((unsigned int) AT91C_PIO_PA9) // USART 1 Clear To Send -#define AT91C_PA9_NPCS03 ((unsigned int) AT91C_PIO_PA9) // SPI 0 Peripheral Chip Select 3 -#define AT91C_PIO_PB0 ((unsigned int) 1 << 0) // Pin Controlled by PB0 -#define AT91C_PB0_ETXCK_EREFCK ((unsigned int) AT91C_PIO_PB0) // Ethernet MAC Transmit Clock/Reference Clock -#define AT91C_PB0_PCK0 ((unsigned int) AT91C_PIO_PB0) // PMC Programmable Clock Output 0 -#define AT91C_PIO_PB1 ((unsigned int) 1 << 1) // Pin Controlled by PB1 -#define AT91C_PB1_ETXEN ((unsigned int) AT91C_PIO_PB1) // Ethernet MAC Transmit Enable -#define AT91C_PIO_PB10 ((unsigned int) 1 << 10) // Pin Controlled by PB10 -#define AT91C_PB10_ETX2 ((unsigned int) AT91C_PIO_PB10) // Ethernet MAC Transmit Data 2 -#define AT91C_PB10_NPCS11 ((unsigned int) AT91C_PIO_PB10) // SPI 1 Peripheral Chip Select 1 -#define AT91C_PIO_PB11 ((unsigned int) 1 << 11) // Pin Controlled by PB11 -#define AT91C_PB11_ETX3 ((unsigned int) AT91C_PIO_PB11) // Ethernet MAC Transmit Data 3 -#define AT91C_PB11_NPCS12 ((unsigned int) AT91C_PIO_PB11) // SPI 1 Peripheral Chip Select 2 -#define AT91C_PIO_PB12 ((unsigned int) 1 << 12) // Pin Controlled by PB12 -#define AT91C_PB12_ETXER ((unsigned int) AT91C_PIO_PB12) // Ethernet MAC Transmikt Coding Error -#define AT91C_PB12_TCLK0 ((unsigned int) AT91C_PIO_PB12) // Timer Counter 0 external clock input -#define AT91C_PIO_PB13 ((unsigned int) 1 << 13) // Pin Controlled by PB13 -#define AT91C_PB13_ERX2 ((unsigned int) AT91C_PIO_PB13) // Ethernet MAC Receive Data 2 -#define AT91C_PB13_NPCS01 ((unsigned int) AT91C_PIO_PB13) // SPI 0 Peripheral Chip Select 1 -#define AT91C_PIO_PB14 ((unsigned int) 1 << 14) // Pin Controlled by PB14 -#define AT91C_PB14_ERX3 ((unsigned int) AT91C_PIO_PB14) // Ethernet MAC Receive Data 3 -#define AT91C_PB14_NPCS02 ((unsigned int) AT91C_PIO_PB14) // SPI 0 Peripheral Chip Select 2 -#define AT91C_PIO_PB15 ((unsigned int) 1 << 15) // Pin Controlled by PB15 -#define AT91C_PB15_ERXDV ((unsigned int) AT91C_PIO_PB15) // Ethernet MAC Receive Data Valid -#define AT91C_PIO_PB16 ((unsigned int) 1 << 16) // Pin Controlled by PB16 -#define AT91C_PB16_ECOL ((unsigned int) AT91C_PIO_PB16) // Ethernet MAC Collision Detected -#define AT91C_PB16_NPCS13 ((unsigned int) AT91C_PIO_PB16) // SPI 1 Peripheral Chip Select 3 -#define AT91C_PIO_PB17 ((unsigned int) 1 << 17) // Pin Controlled by PB17 -#define AT91C_PB17_ERXCK ((unsigned int) AT91C_PIO_PB17) // Ethernet MAC Receive Clock -#define AT91C_PB17_NPCS03 ((unsigned int) AT91C_PIO_PB17) // SPI 0 Peripheral Chip Select 3 -#define AT91C_PIO_PB18 ((unsigned int) 1 << 18) // Pin Controlled by PB18 -#define AT91C_PB18_EF100 ((unsigned int) AT91C_PIO_PB18) // Ethernet MAC Force 100 Mbits/sec -#define AT91C_PB18_ADTRG ((unsigned int) AT91C_PIO_PB18) // ADC External Trigger -#define AT91C_PIO_PB19 ((unsigned int) 1 << 19) // Pin Controlled by PB19 -#define AT91C_PB19_PWM0 ((unsigned int) AT91C_PIO_PB19) // PWM Channel 0 -#define AT91C_PB19_TCLK1 ((unsigned int) AT91C_PIO_PB19) // Timer Counter 1 external clock input -#define AT91C_PIO_PB2 ((unsigned int) 1 << 2) // Pin Controlled by PB2 -#define AT91C_PB2_ETX0 ((unsigned int) AT91C_PIO_PB2) // Ethernet MAC Transmit Data 0 -#define AT91C_PIO_PB20 ((unsigned int) 1 << 20) // Pin Controlled by PB20 -#define AT91C_PB20_PWM1 ((unsigned int) AT91C_PIO_PB20) // PWM Channel 1 -#define AT91C_PB20_PCK0 ((unsigned int) AT91C_PIO_PB20) // PMC Programmable Clock Output 0 -#define AT91C_PIO_PB21 ((unsigned int) 1 << 21) // Pin Controlled by PB21 -#define AT91C_PB21_PWM2 ((unsigned int) AT91C_PIO_PB21) // PWM Channel 2 -#define AT91C_PB21_PCK1 ((unsigned int) AT91C_PIO_PB21) // PMC Programmable Clock Output 1 -#define AT91C_PIO_PB22 ((unsigned int) 1 << 22) // Pin Controlled by PB22 -#define AT91C_PB22_PWM3 ((unsigned int) AT91C_PIO_PB22) // PWM Channel 3 -#define AT91C_PB22_PCK2 ((unsigned int) AT91C_PIO_PB22) // PMC Programmable Clock Output 2 -#define AT91C_PIO_PB23 ((unsigned int) 1 << 23) // Pin Controlled by PB23 -#define AT91C_PB23_TIOA0 ((unsigned int) AT91C_PIO_PB23) // Timer Counter 0 Multipurpose Timer I/O Pin A -#define AT91C_PB23_DCD1 ((unsigned int) AT91C_PIO_PB23) // USART 1 Data Carrier Detect -#define AT91C_PIO_PB24 ((unsigned int) 1 << 24) // Pin Controlled by PB24 -#define AT91C_PB24_TIOB0 ((unsigned int) AT91C_PIO_PB24) // Timer Counter 0 Multipurpose Timer I/O Pin B -#define AT91C_PB24_DSR1 ((unsigned int) AT91C_PIO_PB24) // USART 1 Data Set ready -#define AT91C_PIO_PB25 ((unsigned int) 1 << 25) // Pin Controlled by PB25 -#define AT91C_PB25_TIOA1 ((unsigned int) AT91C_PIO_PB25) // Timer Counter 1 Multipurpose Timer I/O Pin A -#define AT91C_PB25_DTR1 ((unsigned int) AT91C_PIO_PB25) // USART 1 Data Terminal ready -#define AT91C_PIO_PB26 ((unsigned int) 1 << 26) // Pin Controlled by PB26 -#define AT91C_PB26_TIOB1 ((unsigned int) AT91C_PIO_PB26) // Timer Counter 1 Multipurpose Timer I/O Pin B -#define AT91C_PB26_RI1 ((unsigned int) AT91C_PIO_PB26) // USART 1 Ring Indicator -#define AT91C_PIO_PB27 ((unsigned int) 1 << 27) // Pin Controlled by PB27 -#define AT91C_PB27_TIOA2 ((unsigned int) AT91C_PIO_PB27) // Timer Counter 2 Multipurpose Timer I/O Pin A -#define AT91C_PB27_PWM0 ((unsigned int) AT91C_PIO_PB27) // PWM Channel 0 -#define AT91C_PIO_PB28 ((unsigned int) 1 << 28) // Pin Controlled by PB28 -#define AT91C_PB28_TIOB2 ((unsigned int) AT91C_PIO_PB28) // Timer Counter 2 Multipurpose Timer I/O Pin B -#define AT91C_PB28_PWM1 ((unsigned int) AT91C_PIO_PB28) // PWM Channel 1 -#define AT91C_PIO_PB29 ((unsigned int) 1 << 29) // Pin Controlled by PB29 -#define AT91C_PB29_PCK1 ((unsigned int) AT91C_PIO_PB29) // PMC Programmable Clock Output 1 -#define AT91C_PB29_PWM2 ((unsigned int) AT91C_PIO_PB29) // PWM Channel 2 -#define AT91C_PIO_PB3 ((unsigned int) 1 << 3) // Pin Controlled by PB3 -#define AT91C_PB3_ETX1 ((unsigned int) AT91C_PIO_PB3) // Ethernet MAC Transmit Data 1 -#define AT91C_PIO_PB30 ((unsigned int) 1 << 30) // Pin Controlled by PB30 -#define AT91C_PB30_PCK2 ((unsigned int) AT91C_PIO_PB30) // PMC Programmable Clock Output 2 -#define AT91C_PB30_PWM3 ((unsigned int) AT91C_PIO_PB30) // PWM Channel 3 -#define AT91C_PIO_PB4 ((unsigned int) 1 << 4) // Pin Controlled by PB4 -#define AT91C_PB4_ECRS_ECRSDV ((unsigned int) AT91C_PIO_PB4) // Ethernet MAC Carrier Sense/Carrier Sense and Data Valid -#define AT91C_PIO_PB5 ((unsigned int) 1 << 5) // Pin Controlled by PB5 -#define AT91C_PB5_ERX0 ((unsigned int) AT91C_PIO_PB5) // Ethernet MAC Receive Data 0 -#define AT91C_PIO_PB6 ((unsigned int) 1 << 6) // Pin Controlled by PB6 -#define AT91C_PB6_ERX1 ((unsigned int) AT91C_PIO_PB6) // Ethernet MAC Receive Data 1 -#define AT91C_PIO_PB7 ((unsigned int) 1 << 7) // Pin Controlled by PB7 -#define AT91C_PB7_ERXER ((unsigned int) AT91C_PIO_PB7) // Ethernet MAC Receive Error -#define AT91C_PIO_PB8 ((unsigned int) 1 << 8) // Pin Controlled by PB8 -#define AT91C_PB8_EMDC ((unsigned int) AT91C_PIO_PB8) // Ethernet MAC Management Data Clock -#define AT91C_PIO_PB9 ((unsigned int) 1 << 9) // Pin Controlled by PB9 -#define AT91C_PB9_EMDIO ((unsigned int) AT91C_PIO_PB9) // Ethernet MAC Management Data Input/Output - -// ***************************************************************************** -// PERIPHERAL ID DEFINITIONS FOR AT91SAM7X256 -// ***************************************************************************** -#define AT91C_ID_FIQ ((unsigned int) 0) // Advanced Interrupt Controller (FIQ) -#define AT91C_ID_SYS ((unsigned int) 1) // System Peripheral -#define AT91C_ID_PIOA ((unsigned int) 2) // Parallel IO Controller A -#define AT91C_ID_PIOB ((unsigned int) 3) // Parallel IO Controller B -#define AT91C_ID_SPI0 ((unsigned int) 4) // Serial Peripheral Interface 0 -#define AT91C_ID_SPI1 ((unsigned int) 5) // Serial Peripheral Interface 1 -#define AT91C_ID_US0 ((unsigned int) 6) // USART 0 -#define AT91C_ID_US1 ((unsigned int) 7) // USART 1 -#define AT91C_ID_SSC ((unsigned int) 8) // Serial Synchronous Controller -#define AT91C_ID_TWI ((unsigned int) 9) // Two-Wire Interface -#define AT91C_ID_PWMC ((unsigned int) 10) // PWM Controller -#define AT91C_ID_UDP ((unsigned int) 11) // USB Device Port -#define AT91C_ID_TC0 ((unsigned int) 12) // Timer Counter 0 -#define AT91C_ID_TC1 ((unsigned int) 13) // Timer Counter 1 -#define AT91C_ID_TC2 ((unsigned int) 14) // Timer Counter 2 -#define AT91C_ID_CAN ((unsigned int) 15) // Control Area Network Controller -#define AT91C_ID_EMAC ((unsigned int) 16) // Ethernet MAC -#define AT91C_ID_ADC ((unsigned int) 17) // Analog-to-Digital Converter -#define AT91C_ID_AES ((unsigned int) 18) // Advanced Encryption Standard 128-bit -#define AT91C_ID_TDES ((unsigned int) 19) // Triple Data Encryption Standard -#define AT91C_ID_20_Reserved ((unsigned int) 20) // Reserved -#define AT91C_ID_21_Reserved ((unsigned int) 21) // Reserved -#define AT91C_ID_22_Reserved ((unsigned int) 22) // Reserved -#define AT91C_ID_23_Reserved ((unsigned int) 23) // Reserved -#define AT91C_ID_24_Reserved ((unsigned int) 24) // Reserved -#define AT91C_ID_25_Reserved ((unsigned int) 25) // Reserved -#define AT91C_ID_26_Reserved ((unsigned int) 26) // Reserved -#define AT91C_ID_27_Reserved ((unsigned int) 27) // Reserved -#define AT91C_ID_28_Reserved ((unsigned int) 28) // Reserved -#define AT91C_ID_29_Reserved ((unsigned int) 29) // Reserved -#define AT91C_ID_IRQ0 ((unsigned int) 30) // Advanced Interrupt Controller (IRQ0) -#define AT91C_ID_IRQ1 ((unsigned int) 31) // Advanced Interrupt Controller (IRQ1) - -// ***************************************************************************** -// BASE ADDRESS DEFINITIONS FOR AT91SAM7X256 -// ***************************************************************************** -#define AT91C_BASE_SYS ((AT91PS_SYS) 0xFFFFF000) // (SYS) Base Address -#define AT91C_BASE_AIC ((AT91PS_AIC) 0xFFFFF000) // (AIC) Base Address -#define AT91C_BASE_PDC_DBGU ((AT91PS_PDC) 0xFFFFF300) // (PDC_DBGU) Base Address -#define AT91C_BASE_DBGU ((AT91PS_DBGU) 0xFFFFF200) // (DBGU) Base Address -#define AT91C_BASE_PIOA ((AT91PS_PIO) 0xFFFFF400) // (PIOA) Base Address -#define AT91C_BASE_PIOB ((AT91PS_PIO) 0xFFFFF600) // (PIOB) Base Address -#define AT91C_BASE_CKGR ((AT91PS_CKGR) 0xFFFFFC20) // (CKGR) Base Address -#define AT91C_BASE_PMC ((AT91PS_PMC) 0xFFFFFC00) // (PMC) Base Address -#define AT91C_BASE_RSTC ((AT91PS_RSTC) 0xFFFFFD00) // (RSTC) Base Address -#define AT91C_BASE_RTTC ((AT91PS_RTTC) 0xFFFFFD20) // (RTTC) Base Address -#define AT91C_BASE_PITC ((AT91PS_PITC) 0xFFFFFD30) // (PITC) Base Address -#define AT91C_BASE_WDTC ((AT91PS_WDTC) 0xFFFFFD40) // (WDTC) Base Address -#define AT91C_BASE_VREG ((AT91PS_VREG) 0xFFFFFD60) // (VREG) Base Address -#define AT91C_BASE_MC ((AT91PS_MC) 0xFFFFFF00) // (MC) Base Address -#define AT91C_BASE_PDC_SPI1 ((AT91PS_PDC) 0xFFFE4100) // (PDC_SPI1) Base Address -#define AT91C_BASE_SPI1 ((AT91PS_SPI) 0xFFFE4000) // (SPI1) Base Address -#define AT91C_BASE_PDC_SPI0 ((AT91PS_PDC) 0xFFFE0100) // (PDC_SPI0) Base Address -#define AT91C_BASE_SPI0 ((AT91PS_SPI) 0xFFFE0000) // (SPI0) Base Address -#define AT91C_BASE_PDC_US1 ((AT91PS_PDC) 0xFFFC4100) // (PDC_US1) Base Address -#define AT91C_BASE_US1 ((AT91PS_USART) 0xFFFC4000) // (US1) Base Address -#define AT91C_BASE_PDC_US0 ((AT91PS_PDC) 0xFFFC0100) // (PDC_US0) Base Address -#define AT91C_BASE_US0 ((AT91PS_USART) 0xFFFC0000) // (US0) Base Address -#define AT91C_BASE_PDC_SSC ((AT91PS_PDC) 0xFFFD4100) // (PDC_SSC) Base Address -#define AT91C_BASE_SSC ((AT91PS_SSC) 0xFFFD4000) // (SSC) Base Address -#define AT91C_BASE_TWI ((AT91PS_TWI) 0xFFFB8000) // (TWI) Base Address -#define AT91C_BASE_PWMC_CH3 ((AT91PS_PWMC_CH) 0xFFFCC260) // (PWMC_CH3) Base Address -#define AT91C_BASE_PWMC_CH2 ((AT91PS_PWMC_CH) 0xFFFCC240) // (PWMC_CH2) Base Address -#define AT91C_BASE_PWMC_CH1 ((AT91PS_PWMC_CH) 0xFFFCC220) // (PWMC_CH1) Base Address -#define AT91C_BASE_PWMC_CH0 ((AT91PS_PWMC_CH) 0xFFFCC200) // (PWMC_CH0) Base Address -#define AT91C_BASE_PWMC ((AT91PS_PWMC) 0xFFFCC000) // (PWMC) Base Address -#define AT91C_BASE_UDP ((AT91PS_UDP) 0xFFFB0000) // (UDP) Base Address -#define AT91C_BASE_TC0 ((AT91PS_TC) 0xFFFA0000) // (TC0) Base Address -#define AT91C_BASE_TC1 ((AT91PS_TC) 0xFFFA0040) // (TC1) Base Address -#define AT91C_BASE_TC2 ((AT91PS_TC) 0xFFFA0080) // (TC2) Base Address -#define AT91C_BASE_TCB ((AT91PS_TCB) 0xFFFA0000) // (TCB) Base Address -#define AT91C_BASE_CAN_MB0 ((AT91PS_CAN_MB) 0xFFFD0200) // (CAN_MB0) Base Address -#define AT91C_BASE_CAN_MB1 ((AT91PS_CAN_MB) 0xFFFD0220) // (CAN_MB1) Base Address -#define AT91C_BASE_CAN_MB2 ((AT91PS_CAN_MB) 0xFFFD0240) // (CAN_MB2) Base Address -#define AT91C_BASE_CAN_MB3 ((AT91PS_CAN_MB) 0xFFFD0260) // (CAN_MB3) Base Address -#define AT91C_BASE_CAN_MB4 ((AT91PS_CAN_MB) 0xFFFD0280) // (CAN_MB4) Base Address -#define AT91C_BASE_CAN_MB5 ((AT91PS_CAN_MB) 0xFFFD02A0) // (CAN_MB5) Base Address -#define AT91C_BASE_CAN_MB6 ((AT91PS_CAN_MB) 0xFFFD02C0) // (CAN_MB6) Base Address -#define AT91C_BASE_CAN_MB7 ((AT91PS_CAN_MB) 0xFFFD02E0) // (CAN_MB7) Base Address -#define AT91C_BASE_CAN ((AT91PS_CAN) 0xFFFD0000) // (CAN) Base Address -#define AT91C_BASE_EMAC ((AT91PS_EMAC) 0xFFFDC000) // (EMAC) Base Address -#define AT91C_BASE_PDC_ADC ((AT91PS_PDC) 0xFFFD8100) // (PDC_ADC) Base Address -#define AT91C_BASE_ADC ((AT91PS_ADC) 0xFFFD8000) // (ADC) Base Address -#define AT91C_BASE_PDC_AES ((AT91PS_PDC) 0xFFFA4100) // (PDC_AES) Base Address -#define AT91C_BASE_AES ((AT91PS_AES) 0xFFFA4000) // (AES) Base Address -#define AT91C_BASE_PDC_TDES ((AT91PS_PDC) 0xFFFA8100) // (PDC_TDES) Base Address -#define AT91C_BASE_TDES ((AT91PS_TDES) 0xFFFA8000) // (TDES) Base Address - -// ***************************************************************************** -// MEMORY MAPPING DEFINITIONS FOR AT91SAM7X256 -// ***************************************************************************** -#define AT91C_ISRAM ((char *) 0x00200000) // Internal SRAM base address -#define AT91C_ISRAM_SIZE ((unsigned int) 0x00010000) // Internal SRAM size in byte (64 Kbyte) -#define AT91C_IFLASH ((char *) 0x00100000) // Internal ROM base address -#define AT91C_IFLASH_SIZE ((unsigned int) 0x00040000) // Internal ROM size in byte (256 Kbyte) - -#endif +typedef volatile unsigned int AT91_REG; /* Hardware register definition */ + +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR System Peripherals */ +/* ***************************************************************************** */ +typedef struct _AT91S_SYS +{ + AT91_REG AIC_SMR[ 32 ]; /* Source Mode Register */ + AT91_REG AIC_SVR[ 32 ]; /* Source Vector Register */ + AT91_REG AIC_IVR; /* IRQ Vector Register */ + AT91_REG AIC_FVR; /* FIQ Vector Register */ + AT91_REG AIC_ISR; /* Interrupt Status Register */ + AT91_REG AIC_IPR; /* Interrupt Pending Register */ + AT91_REG AIC_IMR; /* Interrupt Mask Register */ + AT91_REG AIC_CISR; /* Core Interrupt Status Register */ + AT91_REG Reserved0[ 2 ]; /* */ + AT91_REG AIC_IECR; /* Interrupt Enable Command Register */ + AT91_REG AIC_IDCR; /* Interrupt Disable Command Register */ + AT91_REG AIC_ICCR; /* Interrupt Clear Command Register */ + AT91_REG AIC_ISCR; /* Interrupt Set Command Register */ + AT91_REG AIC_EOICR; /* End of Interrupt Command Register */ + AT91_REG AIC_SPU; /* Spurious Vector Register */ + AT91_REG AIC_DCR; /* Debug Control Register (Protect) */ + AT91_REG Reserved1[ 1 ]; /* */ + AT91_REG AIC_FFER; /* Fast Forcing Enable Register */ + AT91_REG AIC_FFDR; /* Fast Forcing Disable Register */ + AT91_REG AIC_FFSR; /* Fast Forcing Status Register */ + AT91_REG Reserved2[ 45 ]; /* */ + AT91_REG DBGU_CR; /* Control Register */ + AT91_REG DBGU_MR; /* Mode Register */ + AT91_REG DBGU_IER; /* Interrupt Enable Register */ + AT91_REG DBGU_IDR; /* Interrupt Disable Register */ + AT91_REG DBGU_IMR; /* Interrupt Mask Register */ + AT91_REG DBGU_CSR; /* Channel Status Register */ + AT91_REG DBGU_RHR; /* Receiver Holding Register */ + AT91_REG DBGU_THR; /* Transmitter Holding Register */ + AT91_REG DBGU_BRGR; /* Baud Rate Generator Register */ + AT91_REG Reserved3[ 7 ]; /* */ + AT91_REG DBGU_CIDR; /* Chip ID Register */ + AT91_REG DBGU_EXID; /* Chip ID Extension Register */ + AT91_REG DBGU_FNTR; /* Force NTRST Register */ + AT91_REG Reserved4[ 45 ]; /* */ + AT91_REG DBGU_RPR; /* Receive Pointer Register */ + AT91_REG DBGU_RCR; /* Receive Counter Register */ + AT91_REG DBGU_TPR; /* Transmit Pointer Register */ + AT91_REG DBGU_TCR; /* Transmit Counter Register */ + AT91_REG DBGU_RNPR; /* Receive Next Pointer Register */ + AT91_REG DBGU_RNCR; /* Receive Next Counter Register */ + AT91_REG DBGU_TNPR; /* Transmit Next Pointer Register */ + AT91_REG DBGU_TNCR; /* Transmit Next Counter Register */ + AT91_REG DBGU_PTCR; /* PDC Transfer Control Register */ + AT91_REG DBGU_PTSR; /* PDC Transfer Status Register */ + AT91_REG Reserved5[ 54 ]; /* */ + AT91_REG PIOA_PER; /* PIO Enable Register */ + AT91_REG PIOA_PDR; /* PIO Disable Register */ + AT91_REG PIOA_PSR; /* PIO Status Register */ + AT91_REG Reserved6[ 1 ]; /* */ + AT91_REG PIOA_OER; /* Output Enable Register */ + AT91_REG PIOA_ODR; /* Output Disable Registerr */ + AT91_REG PIOA_OSR; /* Output Status Register */ + AT91_REG Reserved7[ 1 ]; /* */ + AT91_REG PIOA_IFER; /* Input Filter Enable Register */ + AT91_REG PIOA_IFDR; /* Input Filter Disable Register */ + AT91_REG PIOA_IFSR; /* Input Filter Status Register */ + AT91_REG Reserved8[ 1 ]; /* */ + AT91_REG PIOA_SODR; /* Set Output Data Register */ + AT91_REG PIOA_CODR; /* Clear Output Data Register */ + AT91_REG PIOA_ODSR; /* Output Data Status Register */ + AT91_REG PIOA_PDSR; /* Pin Data Status Register */ + AT91_REG PIOA_IER; /* Interrupt Enable Register */ + AT91_REG PIOA_IDR; /* Interrupt Disable Register */ + AT91_REG PIOA_IMR; /* Interrupt Mask Register */ + AT91_REG PIOA_ISR; /* Interrupt Status Register */ + AT91_REG PIOA_MDER; /* Multi-driver Enable Register */ + AT91_REG PIOA_MDDR; /* Multi-driver Disable Register */ + AT91_REG PIOA_MDSR; /* Multi-driver Status Register */ + AT91_REG Reserved9[ 1 ]; /* */ + AT91_REG PIOA_PPUDR; /* Pull-up Disable Register */ + AT91_REG PIOA_PPUER; /* Pull-up Enable Register */ + AT91_REG PIOA_PPUSR; /* Pull-up Status Register */ + AT91_REG Reserved10[ 1 ]; /* */ + AT91_REG PIOA_ASR; /* Select A Register */ + AT91_REG PIOA_BSR; /* Select B Register */ + AT91_REG PIOA_ABSR; /* AB Select Status Register */ + AT91_REG Reserved11[ 9 ]; /* */ + AT91_REG PIOA_OWER; /* Output Write Enable Register */ + AT91_REG PIOA_OWDR; /* Output Write Disable Register */ + AT91_REG PIOA_OWSR; /* Output Write Status Register */ + AT91_REG Reserved12[ 85 ]; /* */ + AT91_REG PIOB_PER; /* PIO Enable Register */ + AT91_REG PIOB_PDR; /* PIO Disable Register */ + AT91_REG PIOB_PSR; /* PIO Status Register */ + AT91_REG Reserved13[ 1 ]; /* */ + AT91_REG PIOB_OER; /* Output Enable Register */ + AT91_REG PIOB_ODR; /* Output Disable Registerr */ + AT91_REG PIOB_OSR; /* Output Status Register */ + AT91_REG Reserved14[ 1 ]; /* */ + AT91_REG PIOB_IFER; /* Input Filter Enable Register */ + AT91_REG PIOB_IFDR; /* Input Filter Disable Register */ + AT91_REG PIOB_IFSR; /* Input Filter Status Register */ + AT91_REG Reserved15[ 1 ]; /* */ + AT91_REG PIOB_SODR; /* Set Output Data Register */ + AT91_REG PIOB_CODR; /* Clear Output Data Register */ + AT91_REG PIOB_ODSR; /* Output Data Status Register */ + AT91_REG PIOB_PDSR; /* Pin Data Status Register */ + AT91_REG PIOB_IER; /* Interrupt Enable Register */ + AT91_REG PIOB_IDR; /* Interrupt Disable Register */ + AT91_REG PIOB_IMR; /* Interrupt Mask Register */ + AT91_REG PIOB_ISR; /* Interrupt Status Register */ + AT91_REG PIOB_MDER; /* Multi-driver Enable Register */ + AT91_REG PIOB_MDDR; /* Multi-driver Disable Register */ + AT91_REG PIOB_MDSR; /* Multi-driver Status Register */ + AT91_REG Reserved16[ 1 ]; /* */ + AT91_REG PIOB_PPUDR; /* Pull-up Disable Register */ + AT91_REG PIOB_PPUER; /* Pull-up Enable Register */ + AT91_REG PIOB_PPUSR; /* Pull-up Status Register */ + AT91_REG Reserved17[ 1 ]; /* */ + AT91_REG PIOB_ASR; /* Select A Register */ + AT91_REG PIOB_BSR; /* Select B Register */ + AT91_REG PIOB_ABSR; /* AB Select Status Register */ + AT91_REG Reserved18[ 9 ]; /* */ + AT91_REG PIOB_OWER; /* Output Write Enable Register */ + AT91_REG PIOB_OWDR; /* Output Write Disable Register */ + AT91_REG PIOB_OWSR; /* Output Write Status Register */ + AT91_REG Reserved19[ 341 ]; /* */ + AT91_REG PMC_SCER; /* System Clock Enable Register */ + AT91_REG PMC_SCDR; /* System Clock Disable Register */ + AT91_REG PMC_SCSR; /* System Clock Status Register */ + AT91_REG Reserved20[ 1 ]; /* */ + AT91_REG PMC_PCER; /* Peripheral Clock Enable Register */ + AT91_REG PMC_PCDR; /* Peripheral Clock Disable Register */ + AT91_REG PMC_PCSR; /* Peripheral Clock Status Register */ + AT91_REG Reserved21[ 1 ]; /* */ + AT91_REG PMC_MOR; /* Main Oscillator Register */ + AT91_REG PMC_MCFR; /* Main Clock Frequency Register */ + AT91_REG Reserved22[ 1 ]; /* */ + AT91_REG PMC_PLLR; /* PLL Register */ + AT91_REG PMC_MCKR; /* Master Clock Register */ + AT91_REG Reserved23[ 3 ]; /* */ + AT91_REG PMC_PCKR[ 4 ]; /* Programmable Clock Register */ + AT91_REG Reserved24[ 4 ]; /* */ + AT91_REG PMC_IER; /* Interrupt Enable Register */ + AT91_REG PMC_IDR; /* Interrupt Disable Register */ + AT91_REG PMC_SR; /* Status Register */ + AT91_REG PMC_IMR; /* Interrupt Mask Register */ + AT91_REG Reserved25[ 36 ]; /* */ + AT91_REG RSTC_RCR; /* Reset Control Register */ + AT91_REG RSTC_RSR; /* Reset Status Register */ + AT91_REG RSTC_RMR; /* Reset Mode Register */ + AT91_REG Reserved26[ 5 ]; /* */ + AT91_REG RTTC_RTMR; /* Real-time Mode Register */ + AT91_REG RTTC_RTAR; /* Real-time Alarm Register */ + AT91_REG RTTC_RTVR; /* Real-time Value Register */ + AT91_REG RTTC_RTSR; /* Real-time Status Register */ + AT91_REG PITC_PIMR; /* Period Interval Mode Register */ + AT91_REG PITC_PISR; /* Period Interval Status Register */ + AT91_REG PITC_PIVR; /* Period Interval Value Register */ + AT91_REG PITC_PIIR; /* Period Interval Image Register */ + AT91_REG WDTC_WDCR; /* Watchdog Control Register */ + AT91_REG WDTC_WDMR; /* Watchdog Mode Register */ + AT91_REG WDTC_WDSR; /* Watchdog Status Register */ + AT91_REG Reserved27[ 5 ]; /* */ + AT91_REG VREG_MR; /* Voltage Regulator Mode Register */ +} AT91S_SYS, * AT91PS_SYS; + + +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR Advanced Interrupt Controller */ +/* ***************************************************************************** */ +typedef struct _AT91S_AIC +{ + AT91_REG AIC_SMR[ 32 ]; /* Source Mode Register */ + AT91_REG AIC_SVR[ 32 ]; /* Source Vector Register */ + AT91_REG AIC_IVR; /* IRQ Vector Register */ + AT91_REG AIC_FVR; /* FIQ Vector Register */ + AT91_REG AIC_ISR; /* Interrupt Status Register */ + AT91_REG AIC_IPR; /* Interrupt Pending Register */ + AT91_REG AIC_IMR; /* Interrupt Mask Register */ + AT91_REG AIC_CISR; /* Core Interrupt Status Register */ + AT91_REG Reserved0[ 2 ]; /* */ + AT91_REG AIC_IECR; /* Interrupt Enable Command Register */ + AT91_REG AIC_IDCR; /* Interrupt Disable Command Register */ + AT91_REG AIC_ICCR; /* Interrupt Clear Command Register */ + AT91_REG AIC_ISCR; /* Interrupt Set Command Register */ + AT91_REG AIC_EOICR; /* End of Interrupt Command Register */ + AT91_REG AIC_SPU; /* Spurious Vector Register */ + AT91_REG AIC_DCR; /* Debug Control Register (Protect) */ + AT91_REG Reserved1[ 1 ]; /* */ + AT91_REG AIC_FFER; /* Fast Forcing Enable Register */ + AT91_REG AIC_FFDR; /* Fast Forcing Disable Register */ + AT91_REG AIC_FFSR; /* Fast Forcing Status Register */ +} AT91S_AIC, * AT91PS_AIC; + +/* -------- AIC_SMR : (AIC Offset: 0x0) Control Register -------- */ +#define AT91C_AIC_PRIOR ( ( unsigned int ) 0x7 << 0 ) /* (AIC) Priority Level */ +#define AT91C_AIC_PRIOR_LOWEST ( ( unsigned int ) 0x0 ) /* (AIC) Lowest priority level */ +#define AT91C_AIC_PRIOR_HIGHEST ( ( unsigned int ) 0x7 ) /* (AIC) Highest priority level */ +#define AT91C_AIC_SRCTYPE ( ( unsigned int ) 0x3 << 5 ) /* (AIC) Interrupt Source Type */ +#define AT91C_AIC_SRCTYPE_INT_HIGH_LEVEL ( ( unsigned int ) 0x0 << 5 ) /* (AIC) Internal Sources Code Label High-level Sensitive */ +#define AT91C_AIC_SRCTYPE_EXT_LOW_LEVEL ( ( unsigned int ) 0x0 << 5 ) /* (AIC) External Sources Code Label Low-level Sensitive */ +#define AT91C_AIC_SRCTYPE_INT_POSITIVE_EDGE ( ( unsigned int ) 0x1 << 5 ) /* (AIC) Internal Sources Code Label Positive Edge triggered */ +#define AT91C_AIC_SRCTYPE_EXT_NEGATIVE_EDGE ( ( unsigned int ) 0x1 << 5 ) /* (AIC) External Sources Code Label Negative Edge triggered */ +#define AT91C_AIC_SRCTYPE_HIGH_LEVEL ( ( unsigned int ) 0x2 << 5 ) /* (AIC) Internal Or External Sources Code Label High-level Sensitive */ +#define AT91C_AIC_SRCTYPE_POSITIVE_EDGE ( ( unsigned int ) 0x3 << 5 ) /* (AIC) Internal Or External Sources Code Label Positive Edge triggered */ +/* -------- AIC_CISR : (AIC Offset: 0x114) AIC Core Interrupt Status Register -------- */ +#define AT91C_AIC_NFIQ ( ( unsigned int ) 0x1 << 0 ) /* (AIC) NFIQ Status */ +#define AT91C_AIC_NIRQ ( ( unsigned int ) 0x1 << 1 ) /* (AIC) NIRQ Status */ +/* -------- AIC_DCR : (AIC Offset: 0x138) AIC Debug Control Register (Protect) -------- */ +#define AT91C_AIC_DCR_PROT ( ( unsigned int ) 0x1 << 0 ) /* (AIC) Protection Mode */ +#define AT91C_AIC_DCR_GMSK ( ( unsigned int ) 0x1 << 1 ) /* (AIC) General Mask */ + +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR Peripheral DMA Controller */ +/* ***************************************************************************** */ +typedef struct _AT91S_PDC +{ + AT91_REG PDC_RPR; /* Receive Pointer Register */ + AT91_REG PDC_RCR; /* Receive Counter Register */ + AT91_REG PDC_TPR; /* Transmit Pointer Register */ + AT91_REG PDC_TCR; /* Transmit Counter Register */ + AT91_REG PDC_RNPR; /* Receive Next Pointer Register */ + AT91_REG PDC_RNCR; /* Receive Next Counter Register */ + AT91_REG PDC_TNPR; /* Transmit Next Pointer Register */ + AT91_REG PDC_TNCR; /* Transmit Next Counter Register */ + AT91_REG PDC_PTCR; /* PDC Transfer Control Register */ + AT91_REG PDC_PTSR; /* PDC Transfer Status Register */ +} AT91S_PDC, * AT91PS_PDC; + +/* -------- PDC_PTCR : (PDC Offset: 0x20) PDC Transfer Control Register -------- */ +#define AT91C_PDC_RXTEN ( ( unsigned int ) 0x1 << 0 ) /* (PDC) Receiver Transfer Enable */ +#define AT91C_PDC_RXTDIS ( ( unsigned int ) 0x1 << 1 ) /* (PDC) Receiver Transfer Disable */ +#define AT91C_PDC_TXTEN ( ( unsigned int ) 0x1 << 8 ) /* (PDC) Transmitter Transfer Enable */ +#define AT91C_PDC_TXTDIS ( ( unsigned int ) 0x1 << 9 ) /* (PDC) Transmitter Transfer Disable */ +/* -------- PDC_PTSR : (PDC Offset: 0x24) PDC Transfer Status Register -------- */ + +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR Debug Unit */ +/* ***************************************************************************** */ +typedef struct _AT91S_DBGU +{ + AT91_REG DBGU_CR; /* Control Register */ + AT91_REG DBGU_MR; /* Mode Register */ + AT91_REG DBGU_IER; /* Interrupt Enable Register */ + AT91_REG DBGU_IDR; /* Interrupt Disable Register */ + AT91_REG DBGU_IMR; /* Interrupt Mask Register */ + AT91_REG DBGU_CSR; /* Channel Status Register */ + AT91_REG DBGU_RHR; /* Receiver Holding Register */ + AT91_REG DBGU_THR; /* Transmitter Holding Register */ + AT91_REG DBGU_BRGR; /* Baud Rate Generator Register */ + AT91_REG Reserved0[ 7 ]; /* */ + AT91_REG DBGU_CIDR; /* Chip ID Register */ + AT91_REG DBGU_EXID; /* Chip ID Extension Register */ + AT91_REG DBGU_FNTR; /* Force NTRST Register */ + AT91_REG Reserved1[ 45 ]; /* */ + AT91_REG DBGU_RPR; /* Receive Pointer Register */ + AT91_REG DBGU_RCR; /* Receive Counter Register */ + AT91_REG DBGU_TPR; /* Transmit Pointer Register */ + AT91_REG DBGU_TCR; /* Transmit Counter Register */ + AT91_REG DBGU_RNPR; /* Receive Next Pointer Register */ + AT91_REG DBGU_RNCR; /* Receive Next Counter Register */ + AT91_REG DBGU_TNPR; /* Transmit Next Pointer Register */ + AT91_REG DBGU_TNCR; /* Transmit Next Counter Register */ + AT91_REG DBGU_PTCR; /* PDC Transfer Control Register */ + AT91_REG DBGU_PTSR; /* PDC Transfer Status Register */ +} AT91S_DBGU, * AT91PS_DBGU; + +/* -------- DBGU_CR : (DBGU Offset: 0x0) Debug Unit Control Register -------- */ +#define AT91C_US_RSTRX ( ( unsigned int ) 0x1 << 2 ) /* (DBGU) Reset Receiver */ +#define AT91C_US_RSTTX ( ( unsigned int ) 0x1 << 3 ) /* (DBGU) Reset Transmitter */ +#define AT91C_US_RXEN ( ( unsigned int ) 0x1 << 4 ) /* (DBGU) Receiver Enable */ +#define AT91C_US_RXDIS ( ( unsigned int ) 0x1 << 5 ) /* (DBGU) Receiver Disable */ +#define AT91C_US_TXEN ( ( unsigned int ) 0x1 << 6 ) /* (DBGU) Transmitter Enable */ +#define AT91C_US_TXDIS ( ( unsigned int ) 0x1 << 7 ) /* (DBGU) Transmitter Disable */ +#define AT91C_US_RSTSTA ( ( unsigned int ) 0x1 << 8 ) /* (DBGU) Reset Status Bits */ +/* -------- DBGU_MR : (DBGU Offset: 0x4) Debug Unit Mode Register -------- */ +#define AT91C_US_PAR ( ( unsigned int ) 0x7 << 9 ) /* (DBGU) Parity type */ +#define AT91C_US_PAR_EVEN ( ( unsigned int ) 0x0 << 9 ) /* (DBGU) Even Parity */ +#define AT91C_US_PAR_ODD ( ( unsigned int ) 0x1 << 9 ) /* (DBGU) Odd Parity */ +#define AT91C_US_PAR_SPACE ( ( unsigned int ) 0x2 << 9 ) /* (DBGU) Parity forced to 0 (Space) */ +#define AT91C_US_PAR_MARK ( ( unsigned int ) 0x3 << 9 ) /* (DBGU) Parity forced to 1 (Mark) */ +#define AT91C_US_PAR_NONE ( ( unsigned int ) 0x4 << 9 ) /* (DBGU) No Parity */ +#define AT91C_US_PAR_MULTI_DROP ( ( unsigned int ) 0x6 << 9 ) /* (DBGU) Multi-drop mode */ +#define AT91C_US_CHMODE ( ( unsigned int ) 0x3 << 14 ) /* (DBGU) Channel Mode */ +#define AT91C_US_CHMODE_NORMAL ( ( unsigned int ) 0x0 << 14 ) /* (DBGU) Normal Mode: The USART channel operates as an RX/TX USART. */ +#define AT91C_US_CHMODE_AUTO ( ( unsigned int ) 0x1 << 14 ) /* (DBGU) Automatic Echo: Receiver Data Input is connected to the TXD pin. */ +#define AT91C_US_CHMODE_LOCAL ( ( unsigned int ) 0x2 << 14 ) /* (DBGU) Local Loopback: Transmitter Output Signal is connected to Receiver Input Signal. */ +#define AT91C_US_CHMODE_REMOTE ( ( unsigned int ) 0x3 << 14 ) /* (DBGU) Remote Loopback: RXD pin is internally connected to TXD pin. */ +/* -------- DBGU_IER : (DBGU Offset: 0x8) Debug Unit Interrupt Enable Register -------- */ +#define AT91C_US_RXRDY ( ( unsigned int ) 0x1 << 0 ) /* (DBGU) RXRDY Interrupt */ +#define AT91C_US_TXRDY ( ( unsigned int ) 0x1 << 1 ) /* (DBGU) TXRDY Interrupt */ +#define AT91C_US_ENDRX ( ( unsigned int ) 0x1 << 3 ) /* (DBGU) End of Receive Transfer Interrupt */ +#define AT91C_US_ENDTX ( ( unsigned int ) 0x1 << 4 ) /* (DBGU) End of Transmit Interrupt */ +#define AT91C_US_OVRE ( ( unsigned int ) 0x1 << 5 ) /* (DBGU) Overrun Interrupt */ +#define AT91C_US_FRAME ( ( unsigned int ) 0x1 << 6 ) /* (DBGU) Framing Error Interrupt */ +#define AT91C_US_PARE ( ( unsigned int ) 0x1 << 7 ) /* (DBGU) Parity Error Interrupt */ +#define AT91C_US_TXEMPTY ( ( unsigned int ) 0x1 << 9 ) /* (DBGU) TXEMPTY Interrupt */ +#define AT91C_US_TXBUFE ( ( unsigned int ) 0x1 << 11 ) /* (DBGU) TXBUFE Interrupt */ +#define AT91C_US_RXBUFF ( ( unsigned int ) 0x1 << 12 ) /* (DBGU) RXBUFF Interrupt */ +#define AT91C_US_COMM_TX ( ( unsigned int ) 0x1 << 30 ) /* (DBGU) COMM_TX Interrupt */ +#define AT91C_US_COMM_RX ( ( unsigned int ) 0x1 << 31 ) /* (DBGU) COMM_RX Interrupt */ +/* -------- DBGU_IDR : (DBGU Offset: 0xc) Debug Unit Interrupt Disable Register -------- */ +/* -------- DBGU_IMR : (DBGU Offset: 0x10) Debug Unit Interrupt Mask Register -------- */ +/* -------- DBGU_CSR : (DBGU Offset: 0x14) Debug Unit Channel Status Register -------- */ +/* -------- DBGU_FNTR : (DBGU Offset: 0x48) Debug Unit FORCE_NTRST Register -------- */ +#define AT91C_US_FORCE_NTRST ( ( unsigned int ) 0x1 << 0 ) /* (DBGU) Force NTRST in JTAG */ + +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR Parallel Input Output Controller */ +/* ***************************************************************************** */ +typedef struct _AT91S_PIO +{ + AT91_REG PIO_PER; /* PIO Enable Register */ + AT91_REG PIO_PDR; /* PIO Disable Register */ + AT91_REG PIO_PSR; /* PIO Status Register */ + AT91_REG Reserved0[ 1 ]; /* */ + AT91_REG PIO_OER; /* Output Enable Register */ + AT91_REG PIO_ODR; /* Output Disable Registerr */ + AT91_REG PIO_OSR; /* Output Status Register */ + AT91_REG Reserved1[ 1 ]; /* */ + AT91_REG PIO_IFER; /* Input Filter Enable Register */ + AT91_REG PIO_IFDR; /* Input Filter Disable Register */ + AT91_REG PIO_IFSR; /* Input Filter Status Register */ + AT91_REG Reserved2[ 1 ]; /* */ + AT91_REG PIO_SODR; /* Set Output Data Register */ + AT91_REG PIO_CODR; /* Clear Output Data Register */ + AT91_REG PIO_ODSR; /* Output Data Status Register */ + AT91_REG PIO_PDSR; /* Pin Data Status Register */ + AT91_REG PIO_IER; /* Interrupt Enable Register */ + AT91_REG PIO_IDR; /* Interrupt Disable Register */ + AT91_REG PIO_IMR; /* Interrupt Mask Register */ + AT91_REG PIO_ISR; /* Interrupt Status Register */ + AT91_REG PIO_MDER; /* Multi-driver Enable Register */ + AT91_REG PIO_MDDR; /* Multi-driver Disable Register */ + AT91_REG PIO_MDSR; /* Multi-driver Status Register */ + AT91_REG Reserved3[ 1 ]; /* */ + AT91_REG PIO_PPUDR; /* Pull-up Disable Register */ + AT91_REG PIO_PPUER; /* Pull-up Enable Register */ + AT91_REG PIO_PPUSR; /* Pull-up Status Register */ + AT91_REG Reserved4[ 1 ]; /* */ + AT91_REG PIO_ASR; /* Select A Register */ + AT91_REG PIO_BSR; /* Select B Register */ + AT91_REG PIO_ABSR; /* AB Select Status Register */ + AT91_REG Reserved5[ 9 ]; /* */ + AT91_REG PIO_OWER; /* Output Write Enable Register */ + AT91_REG PIO_OWDR; /* Output Write Disable Register */ + AT91_REG PIO_OWSR; /* Output Write Status Register */ +} AT91S_PIO, * AT91PS_PIO; + + +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR Clock Generator Controller */ +/* ***************************************************************************** */ +typedef struct _AT91S_CKGR +{ + AT91_REG CKGR_MOR; /* Main Oscillator Register */ + AT91_REG CKGR_MCFR; /* Main Clock Frequency Register */ + AT91_REG Reserved0[ 1 ]; /* */ + AT91_REG CKGR_PLLR; /* PLL Register */ +} AT91S_CKGR, * AT91PS_CKGR; + +/* -------- CKGR_MOR : (CKGR Offset: 0x0) Main Oscillator Register -------- */ +#define AT91C_CKGR_MOSCEN ( ( unsigned int ) 0x1 << 0 ) /* (CKGR) Main Oscillator Enable */ +#define AT91C_CKGR_OSCBYPASS ( ( unsigned int ) 0x1 << 1 ) /* (CKGR) Main Oscillator Bypass */ +#define AT91C_CKGR_OSCOUNT ( ( unsigned int ) 0xFF << 8 ) /* (CKGR) Main Oscillator Start-up Time */ +/* -------- CKGR_MCFR : (CKGR Offset: 0x4) Main Clock Frequency Register -------- */ +#define AT91C_CKGR_MAINF ( ( unsigned int ) 0xFFFF << 0 ) /* (CKGR) Main Clock Frequency */ +#define AT91C_CKGR_MAINRDY ( ( unsigned int ) 0x1 << 16 ) /* (CKGR) Main Clock Ready */ +/* -------- CKGR_PLLR : (CKGR Offset: 0xc) PLL B Register -------- */ +#define AT91C_CKGR_DIV ( ( unsigned int ) 0xFF << 0 ) /* (CKGR) Divider Selected */ +#define AT91C_CKGR_DIV_0 ( ( unsigned int ) 0x0 ) /* (CKGR) Divider output is 0 */ +#define AT91C_CKGR_DIV_BYPASS ( ( unsigned int ) 0x1 ) /* (CKGR) Divider is bypassed */ +#define AT91C_CKGR_PLLCOUNT ( ( unsigned int ) 0x3F << 8 ) /* (CKGR) PLL Counter */ +#define AT91C_CKGR_OUT ( ( unsigned int ) 0x3 << 14 ) /* (CKGR) PLL Output Frequency Range */ +#define AT91C_CKGR_OUT_0 ( ( unsigned int ) 0x0 << 14 ) /* (CKGR) Please refer to the PLL datasheet */ +#define AT91C_CKGR_OUT_1 ( ( unsigned int ) 0x1 << 14 ) /* (CKGR) Please refer to the PLL datasheet */ +#define AT91C_CKGR_OUT_2 ( ( unsigned int ) 0x2 << 14 ) /* (CKGR) Please refer to the PLL datasheet */ +#define AT91C_CKGR_OUT_3 ( ( unsigned int ) 0x3 << 14 ) /* (CKGR) Please refer to the PLL datasheet */ +#define AT91C_CKGR_MUL ( ( unsigned int ) 0x7FF << 16 ) /* (CKGR) PLL Multiplier */ +#define AT91C_CKGR_USBDIV ( ( unsigned int ) 0x3 << 28 ) /* (CKGR) Divider for USB Clocks */ +#define AT91C_CKGR_USBDIV_0 ( ( unsigned int ) 0x0 << 28 ) /* (CKGR) Divider output is PLL clock output */ +#define AT91C_CKGR_USBDIV_1 ( ( unsigned int ) 0x1 << 28 ) /* (CKGR) Divider output is PLL clock output divided by 2 */ +#define AT91C_CKGR_USBDIV_2 ( ( unsigned int ) 0x2 << 28 ) /* (CKGR) Divider output is PLL clock output divided by 4 */ + +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR Power Management Controller */ +/* ***************************************************************************** */ +typedef struct _AT91S_PMC +{ + AT91_REG PMC_SCER; /* System Clock Enable Register */ + AT91_REG PMC_SCDR; /* System Clock Disable Register */ + AT91_REG PMC_SCSR; /* System Clock Status Register */ + AT91_REG Reserved0[ 1 ]; /* */ + AT91_REG PMC_PCER; /* Peripheral Clock Enable Register */ + AT91_REG PMC_PCDR; /* Peripheral Clock Disable Register */ + AT91_REG PMC_PCSR; /* Peripheral Clock Status Register */ + AT91_REG Reserved1[ 1 ]; /* */ + AT91_REG PMC_MOR; /* Main Oscillator Register */ + AT91_REG PMC_MCFR; /* Main Clock Frequency Register */ + AT91_REG Reserved2[ 1 ]; /* */ + AT91_REG PMC_PLLR; /* PLL Register */ + AT91_REG PMC_MCKR; /* Master Clock Register */ + AT91_REG Reserved3[ 3 ]; /* */ + AT91_REG PMC_PCKR[ 4 ]; /* Programmable Clock Register */ + AT91_REG Reserved4[ 4 ]; /* */ + AT91_REG PMC_IER; /* Interrupt Enable Register */ + AT91_REG PMC_IDR; /* Interrupt Disable Register */ + AT91_REG PMC_SR; /* Status Register */ + AT91_REG PMC_IMR; /* Interrupt Mask Register */ +} AT91S_PMC, * AT91PS_PMC; + +/* -------- PMC_SCER : (PMC Offset: 0x0) System Clock Enable Register -------- */ +#define AT91C_PMC_PCK ( ( unsigned int ) 0x1 << 0 ) /* (PMC) Processor Clock */ +#define AT91C_PMC_UDP ( ( unsigned int ) 0x1 << 7 ) /* (PMC) USB Device Port Clock */ +#define AT91C_PMC_PCK0 ( ( unsigned int ) 0x1 << 8 ) /* (PMC) Programmable Clock Output */ +#define AT91C_PMC_PCK1 ( ( unsigned int ) 0x1 << 9 ) /* (PMC) Programmable Clock Output */ +#define AT91C_PMC_PCK2 ( ( unsigned int ) 0x1 << 10 ) /* (PMC) Programmable Clock Output */ +#define AT91C_PMC_PCK3 ( ( unsigned int ) 0x1 << 11 ) /* (PMC) Programmable Clock Output */ +/* -------- PMC_SCDR : (PMC Offset: 0x4) System Clock Disable Register -------- */ +/* -------- PMC_SCSR : (PMC Offset: 0x8) System Clock Status Register -------- */ +/* -------- CKGR_MOR : (PMC Offset: 0x20) Main Oscillator Register -------- */ +/* -------- CKGR_MCFR : (PMC Offset: 0x24) Main Clock Frequency Register -------- */ +/* -------- CKGR_PLLR : (PMC Offset: 0x2c) PLL B Register -------- */ +/* -------- PMC_MCKR : (PMC Offset: 0x30) Master Clock Register -------- */ +#define AT91C_PMC_CSS ( ( unsigned int ) 0x3 << 0 ) /* (PMC) Programmable Clock Selection */ +#define AT91C_PMC_CSS_SLOW_CLK ( ( unsigned int ) 0x0 ) /* (PMC) Slow Clock is selected */ +#define AT91C_PMC_CSS_MAIN_CLK ( ( unsigned int ) 0x1 ) /* (PMC) Main Clock is selected */ +#define AT91C_PMC_CSS_PLL_CLK ( ( unsigned int ) 0x3 ) /* (PMC) Clock from PLL is selected */ +#define AT91C_PMC_PRES ( ( unsigned int ) 0x7 << 2 ) /* (PMC) Programmable Clock Prescaler */ +#define AT91C_PMC_PRES_CLK ( ( unsigned int ) 0x0 << 2 ) /* (PMC) Selected clock */ +#define AT91C_PMC_PRES_CLK_2 ( ( unsigned int ) 0x1 << 2 ) /* (PMC) Selected clock divided by 2 */ +#define AT91C_PMC_PRES_CLK_4 ( ( unsigned int ) 0x2 << 2 ) /* (PMC) Selected clock divided by 4 */ +#define AT91C_PMC_PRES_CLK_8 ( ( unsigned int ) 0x3 << 2 ) /* (PMC) Selected clock divided by 8 */ +#define AT91C_PMC_PRES_CLK_16 ( ( unsigned int ) 0x4 << 2 ) /* (PMC) Selected clock divided by 16 */ +#define AT91C_PMC_PRES_CLK_32 ( ( unsigned int ) 0x5 << 2 ) /* (PMC) Selected clock divided by 32 */ +#define AT91C_PMC_PRES_CLK_64 ( ( unsigned int ) 0x6 << 2 ) /* (PMC) Selected clock divided by 64 */ +/* -------- PMC_PCKR : (PMC Offset: 0x40) Programmable Clock Register -------- */ +/* -------- PMC_IER : (PMC Offset: 0x60) PMC Interrupt Enable Register -------- */ +#define AT91C_PMC_MOSCS ( ( unsigned int ) 0x1 << 0 ) /* (PMC) MOSC Status/Enable/Disable/Mask */ +#define AT91C_PMC_LOCK ( ( unsigned int ) 0x1 << 2 ) /* (PMC) PLL Status/Enable/Disable/Mask */ +#define AT91C_PMC_MCKRDY ( ( unsigned int ) 0x1 << 3 ) /* (PMC) MCK_RDY Status/Enable/Disable/Mask */ +#define AT91C_PMC_PCK0RDY ( ( unsigned int ) 0x1 << 8 ) /* (PMC) PCK0_RDY Status/Enable/Disable/Mask */ +#define AT91C_PMC_PCK1RDY ( ( unsigned int ) 0x1 << 9 ) /* (PMC) PCK1_RDY Status/Enable/Disable/Mask */ +#define AT91C_PMC_PCK2RDY ( ( unsigned int ) 0x1 << 10 ) /* (PMC) PCK2_RDY Status/Enable/Disable/Mask */ +#define AT91C_PMC_PCK3RDY ( ( unsigned int ) 0x1 << 11 ) /* (PMC) PCK3_RDY Status/Enable/Disable/Mask */ +/* -------- PMC_IDR : (PMC Offset: 0x64) PMC Interrupt Disable Register -------- */ +/* -------- PMC_SR : (PMC Offset: 0x68) PMC Status Register -------- */ +/* -------- PMC_IMR : (PMC Offset: 0x6c) PMC Interrupt Mask Register -------- */ + +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR Reset Controller Interface */ +/* ***************************************************************************** */ +typedef struct _AT91S_RSTC +{ + AT91_REG RSTC_RCR; /* Reset Control Register */ + AT91_REG RSTC_RSR; /* Reset Status Register */ + AT91_REG RSTC_RMR; /* Reset Mode Register */ +} AT91S_RSTC, * AT91PS_RSTC; + +/* -------- RSTC_RCR : (RSTC Offset: 0x0) Reset Control Register -------- */ +#define AT91C_RSTC_PROCRST ( ( unsigned int ) 0x1 << 0 ) /* (RSTC) Processor Reset */ +#define AT91C_RSTC_PERRST ( ( unsigned int ) 0x1 << 2 ) /* (RSTC) Peripheral Reset */ +#define AT91C_RSTC_EXTRST ( ( unsigned int ) 0x1 << 3 ) /* (RSTC) External Reset */ +#define AT91C_RSTC_KEY ( ( unsigned int ) 0xFF << 24 ) /* (RSTC) Password */ +/* -------- RSTC_RSR : (RSTC Offset: 0x4) Reset Status Register -------- */ +#define AT91C_RSTC_URSTS ( ( unsigned int ) 0x1 << 0 ) /* (RSTC) User Reset Status */ +#define AT91C_RSTC_BODSTS ( ( unsigned int ) 0x1 << 1 ) /* (RSTC) Brownout Detection Status */ +#define AT91C_RSTC_RSTTYP ( ( unsigned int ) 0x7 << 8 ) /* (RSTC) Reset Type */ +#define AT91C_RSTC_RSTTYP_POWERUP ( ( unsigned int ) 0x0 << 8 ) /* (RSTC) Power-up Reset. VDDCORE rising. */ +#define AT91C_RSTC_RSTTYP_WAKEUP ( ( unsigned int ) 0x1 << 8 ) /* (RSTC) WakeUp Reset. VDDCORE rising. */ +#define AT91C_RSTC_RSTTYP_WATCHDOG ( ( unsigned int ) 0x2 << 8 ) /* (RSTC) Watchdog Reset. Watchdog overflow occurred. */ +#define AT91C_RSTC_RSTTYP_SOFTWARE ( ( unsigned int ) 0x3 << 8 ) /* (RSTC) Software Reset. Processor reset required by the software. */ +#define AT91C_RSTC_RSTTYP_USER ( ( unsigned int ) 0x4 << 8 ) /* (RSTC) User Reset. NRST pin detected low. */ +#define AT91C_RSTC_RSTTYP_BROWNOUT ( ( unsigned int ) 0x5 << 8 ) /* (RSTC) Brownout Reset occurred. */ +#define AT91C_RSTC_NRSTL ( ( unsigned int ) 0x1 << 16 ) /* (RSTC) NRST pin level */ +#define AT91C_RSTC_SRCMP ( ( unsigned int ) 0x1 << 17 ) /* (RSTC) Software Reset Command in Progress. */ +/* -------- RSTC_RMR : (RSTC Offset: 0x8) Reset Mode Register -------- */ +#define AT91C_RSTC_URSTEN ( ( unsigned int ) 0x1 << 0 ) /* (RSTC) User Reset Enable */ +#define AT91C_RSTC_URSTIEN ( ( unsigned int ) 0x1 << 4 ) /* (RSTC) User Reset Interrupt Enable */ +#define AT91C_RSTC_ERSTL ( ( unsigned int ) 0xF << 8 ) /* (RSTC) User Reset Enable */ +#define AT91C_RSTC_BODIEN ( ( unsigned int ) 0x1 << 16 ) /* (RSTC) Brownout Detection Interrupt Enable */ + +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR Real Time Timer Controller Interface */ +/* ***************************************************************************** */ +typedef struct _AT91S_RTTC +{ + AT91_REG RTTC_RTMR; /* Real-time Mode Register */ + AT91_REG RTTC_RTAR; /* Real-time Alarm Register */ + AT91_REG RTTC_RTVR; /* Real-time Value Register */ + AT91_REG RTTC_RTSR; /* Real-time Status Register */ +} AT91S_RTTC, * AT91PS_RTTC; + +/* -------- RTTC_RTMR : (RTTC Offset: 0x0) Real-time Mode Register -------- */ +#define AT91C_RTTC_RTPRES ( ( unsigned int ) 0xFFFF << 0 ) /* (RTTC) Real-time Timer Prescaler Value */ +#define AT91C_RTTC_ALMIEN ( ( unsigned int ) 0x1 << 16 ) /* (RTTC) Alarm Interrupt Enable */ +#define AT91C_RTTC_RTTINCIEN ( ( unsigned int ) 0x1 << 17 ) /* (RTTC) Real Time Timer Increment Interrupt Enable */ +#define AT91C_RTTC_RTTRST ( ( unsigned int ) 0x1 << 18 ) /* (RTTC) Real Time Timer Restart */ +/* -------- RTTC_RTAR : (RTTC Offset: 0x4) Real-time Alarm Register -------- */ +#define AT91C_RTTC_ALMV ( ( unsigned int ) 0x0 << 0 ) /* (RTTC) Alarm Value */ +/* -------- RTTC_RTVR : (RTTC Offset: 0x8) Current Real-time Value Register -------- */ +#define AT91C_RTTC_CRTV ( ( unsigned int ) 0x0 << 0 ) /* (RTTC) Current Real-time Value */ +/* -------- RTTC_RTSR : (RTTC Offset: 0xc) Real-time Status Register -------- */ +#define AT91C_RTTC_ALMS ( ( unsigned int ) 0x1 << 0 ) /* (RTTC) Real-time Alarm Status */ +#define AT91C_RTTC_RTTINC ( ( unsigned int ) 0x1 << 1 ) /* (RTTC) Real-time Timer Increment */ + +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR Periodic Interval Timer Controller Interface */ +/* ***************************************************************************** */ +typedef struct _AT91S_PITC +{ + AT91_REG PITC_PIMR; /* Period Interval Mode Register */ + AT91_REG PITC_PISR; /* Period Interval Status Register */ + AT91_REG PITC_PIVR; /* Period Interval Value Register */ + AT91_REG PITC_PIIR; /* Period Interval Image Register */ +} AT91S_PITC, * AT91PS_PITC; + +/* -------- PITC_PIMR : (PITC Offset: 0x0) Periodic Interval Mode Register -------- */ +#define AT91C_PITC_PIV ( ( unsigned int ) 0xFFFFF << 0 ) /* (PITC) Periodic Interval Value */ +#define AT91C_PITC_PITEN ( ( unsigned int ) 0x1 << 24 ) /* (PITC) Periodic Interval Timer Enabled */ +#define AT91C_PITC_PITIEN ( ( unsigned int ) 0x1 << 25 ) /* (PITC) Periodic Interval Timer Interrupt Enable */ +/* -------- PITC_PISR : (PITC Offset: 0x4) Periodic Interval Status Register -------- */ +#define AT91C_PITC_PITS ( ( unsigned int ) 0x1 << 0 ) /* (PITC) Periodic Interval Timer Status */ +/* -------- PITC_PIVR : (PITC Offset: 0x8) Periodic Interval Value Register -------- */ +#define AT91C_PITC_CPIV ( ( unsigned int ) 0xFFFFF << 0 ) /* (PITC) Current Periodic Interval Value */ +#define AT91C_PITC_PICNT ( ( unsigned int ) 0xFFF << 20 ) /* (PITC) Periodic Interval Counter */ +/* -------- PITC_PIIR : (PITC Offset: 0xc) Periodic Interval Image Register -------- */ + +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR Watchdog Timer Controller Interface */ +/* ***************************************************************************** */ +typedef struct _AT91S_WDTC +{ + AT91_REG WDTC_WDCR; /* Watchdog Control Register */ + AT91_REG WDTC_WDMR; /* Watchdog Mode Register */ + AT91_REG WDTC_WDSR; /* Watchdog Status Register */ +} AT91S_WDTC, * AT91PS_WDTC; + +/* -------- WDTC_WDCR : (WDTC Offset: 0x0) Periodic Interval Image Register -------- */ +#define AT91C_WDTC_WDRSTT ( ( unsigned int ) 0x1 << 0 ) /* (WDTC) Watchdog Restart */ +#define AT91C_WDTC_KEY ( ( unsigned int ) 0xFF << 24 ) /* (WDTC) Watchdog KEY Password */ +/* -------- WDTC_WDMR : (WDTC Offset: 0x4) Watchdog Mode Register -------- */ +#define AT91C_WDTC_WDV ( ( unsigned int ) 0xFFF << 0 ) /* (WDTC) Watchdog Timer Restart */ +#define AT91C_WDTC_WDFIEN ( ( unsigned int ) 0x1 << 12 ) /* (WDTC) Watchdog Fault Interrupt Enable */ +#define AT91C_WDTC_WDRSTEN ( ( unsigned int ) 0x1 << 13 ) /* (WDTC) Watchdog Reset Enable */ +#define AT91C_WDTC_WDRPROC ( ( unsigned int ) 0x1 << 14 ) /* (WDTC) Watchdog Timer Restart */ +#define AT91C_WDTC_WDDIS ( ( unsigned int ) 0x1 << 15 ) /* (WDTC) Watchdog Disable */ +#define AT91C_WDTC_WDD ( ( unsigned int ) 0xFFF << 16 ) /* (WDTC) Watchdog Delta Value */ +#define AT91C_WDTC_WDDBGHLT ( ( unsigned int ) 0x1 << 28 ) /* (WDTC) Watchdog Debug Halt */ +#define AT91C_WDTC_WDIDLEHLT ( ( unsigned int ) 0x1 << 29 ) /* (WDTC) Watchdog Idle Halt */ +/* -------- WDTC_WDSR : (WDTC Offset: 0x8) Watchdog Status Register -------- */ +#define AT91C_WDTC_WDUNF ( ( unsigned int ) 0x1 << 0 ) /* (WDTC) Watchdog Underflow */ +#define AT91C_WDTC_WDERR ( ( unsigned int ) 0x1 << 1 ) /* (WDTC) Watchdog Error */ + +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR Voltage Regulator Mode Controller Interface */ +/* ***************************************************************************** */ +typedef struct _AT91S_VREG +{ + AT91_REG VREG_MR; /* Voltage Regulator Mode Register */ +} AT91S_VREG, * AT91PS_VREG; + +/* -------- VREG_MR : (VREG Offset: 0x0) Voltage Regulator Mode Register -------- */ +#define AT91C_VREG_PSTDBY ( ( unsigned int ) 0x1 << 0 ) /* (VREG) Voltage Regulator Power Standby Mode */ + +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR Memory Controller Interface */ +/* ***************************************************************************** */ +typedef struct _AT91S_MC +{ + AT91_REG MC_RCR; /* MC Remap Control Register */ + AT91_REG MC_ASR; /* MC Abort Status Register */ + AT91_REG MC_AASR; /* MC Abort Address Status Register */ + AT91_REG Reserved0[ 21 ]; /* */ + AT91_REG MC_FMR; /* MC Flash Mode Register */ + AT91_REG MC_FCR; /* MC Flash Command Register */ + AT91_REG MC_FSR; /* MC Flash Status Register */ +} AT91S_MC, * AT91PS_MC; + +/* -------- MC_RCR : (MC Offset: 0x0) MC Remap Control Register -------- */ +#define AT91C_MC_RCB ( ( unsigned int ) 0x1 << 0 ) /* (MC) Remap Command Bit */ +/* -------- MC_ASR : (MC Offset: 0x4) MC Abort Status Register -------- */ +#define AT91C_MC_UNDADD ( ( unsigned int ) 0x1 << 0 ) /* (MC) Undefined Addess Abort Status */ +#define AT91C_MC_MISADD ( ( unsigned int ) 0x1 << 1 ) /* (MC) Misaligned Addess Abort Status */ +#define AT91C_MC_ABTSZ ( ( unsigned int ) 0x3 << 8 ) /* (MC) Abort Size Status */ +#define AT91C_MC_ABTSZ_BYTE ( ( unsigned int ) 0x0 << 8 ) /* (MC) Byte */ +#define AT91C_MC_ABTSZ_HWORD ( ( unsigned int ) 0x1 << 8 ) /* (MC) Half-word */ +#define AT91C_MC_ABTSZ_WORD ( ( unsigned int ) 0x2 << 8 ) /* (MC) Word */ +#define AT91C_MC_ABTTYP ( ( unsigned int ) 0x3 << 10 ) /* (MC) Abort Type Status */ +#define AT91C_MC_ABTTYP_DATAR ( ( unsigned int ) 0x0 << 10 ) /* (MC) Data Read */ +#define AT91C_MC_ABTTYP_DATAW ( ( unsigned int ) 0x1 << 10 ) /* (MC) Data Write */ +#define AT91C_MC_ABTTYP_FETCH ( ( unsigned int ) 0x2 << 10 ) /* (MC) Code Fetch */ +#define AT91C_MC_MST0 ( ( unsigned int ) 0x1 << 16 ) /* (MC) Master 0 Abort Source */ +#define AT91C_MC_MST1 ( ( unsigned int ) 0x1 << 17 ) /* (MC) Master 1 Abort Source */ +#define AT91C_MC_SVMST0 ( ( unsigned int ) 0x1 << 24 ) /* (MC) Saved Master 0 Abort Source */ +#define AT91C_MC_SVMST1 ( ( unsigned int ) 0x1 << 25 ) /* (MC) Saved Master 1 Abort Source */ +/* -------- MC_FMR : (MC Offset: 0x60) MC Flash Mode Register -------- */ +#define AT91C_MC_FRDY ( ( unsigned int ) 0x1 << 0 ) /* (MC) Flash Ready */ +#define AT91C_MC_LOCKE ( ( unsigned int ) 0x1 << 2 ) /* (MC) Lock Error */ +#define AT91C_MC_PROGE ( ( unsigned int ) 0x1 << 3 ) /* (MC) Programming Error */ +#define AT91C_MC_NEBP ( ( unsigned int ) 0x1 << 7 ) /* (MC) No Erase Before Programming */ +#define AT91C_MC_FWS ( ( unsigned int ) 0x3 << 8 ) /* (MC) Flash Wait State */ +#define AT91C_MC_FWS_0FWS ( ( unsigned int ) 0x0 << 8 ) /* (MC) 1 cycle for Read, 2 for Write operations */ +#define AT91C_MC_FWS_1FWS ( ( unsigned int ) 0x1 << 8 ) /* (MC) 2 cycles for Read, 3 for Write operations */ +#define AT91C_MC_FWS_2FWS ( ( unsigned int ) 0x2 << 8 ) /* (MC) 3 cycles for Read, 4 for Write operations */ +#define AT91C_MC_FWS_3FWS ( ( unsigned int ) 0x3 << 8 ) /* (MC) 4 cycles for Read, 4 for Write operations */ +#define AT91C_MC_FMCN ( ( unsigned int ) 0xFF << 16 ) /* (MC) Flash Microsecond Cycle Number */ +/* -------- MC_FCR : (MC Offset: 0x64) MC Flash Command Register -------- */ +#define AT91C_MC_FCMD ( ( unsigned int ) 0xF << 0 ) /* (MC) Flash Command */ +#define AT91C_MC_FCMD_START_PROG ( ( unsigned int ) 0x1 ) /* (MC) Starts the programming of th epage specified by PAGEN. */ +#define AT91C_MC_FCMD_LOCK ( ( unsigned int ) 0x2 ) /* (MC) Starts a lock sequence of the sector defined by the bits 4 to 7 of the field PAGEN. */ +#define AT91C_MC_FCMD_PROG_AND_LOCK ( ( unsigned int ) 0x3 ) /* (MC) The lock sequence automatically happens after the programming sequence is completed. */ +#define AT91C_MC_FCMD_UNLOCK ( ( unsigned int ) 0x4 ) /* (MC) Starts an unlock sequence of the sector defined by the bits 4 to 7 of the field PAGEN. */ +#define AT91C_MC_FCMD_ERASE_ALL ( ( unsigned int ) 0x8 ) /* (MC) Starts the erase of the entire flash.If at least a page is locked, the command is cancelled. */ +#define AT91C_MC_FCMD_SET_GP_NVM ( ( unsigned int ) 0xB ) /* (MC) Set General Purpose NVM bits. */ +#define AT91C_MC_FCMD_CLR_GP_NVM ( ( unsigned int ) 0xD ) /* (MC) Clear General Purpose NVM bits. */ +#define AT91C_MC_FCMD_SET_SECURITY ( ( unsigned int ) 0xF ) /* (MC) Set Security Bit. */ +#define AT91C_MC_PAGEN ( ( unsigned int ) 0x3FF << 8 ) /* (MC) Page Number */ +#define AT91C_MC_KEY ( ( unsigned int ) 0xFF << 24 ) /* (MC) Writing Protect Key */ +/* -------- MC_FSR : (MC Offset: 0x68) MC Flash Command Register -------- */ +#define AT91C_MC_SECURITY ( ( unsigned int ) 0x1 << 4 ) /* (MC) Security Bit Status */ +#define AT91C_MC_GPNVM0 ( ( unsigned int ) 0x1 << 8 ) /* (MC) Sector 0 Lock Status */ +#define AT91C_MC_GPNVM1 ( ( unsigned int ) 0x1 << 9 ) /* (MC) Sector 1 Lock Status */ +#define AT91C_MC_GPNVM2 ( ( unsigned int ) 0x1 << 10 ) /* (MC) Sector 2 Lock Status */ +#define AT91C_MC_GPNVM3 ( ( unsigned int ) 0x1 << 11 ) /* (MC) Sector 3 Lock Status */ +#define AT91C_MC_GPNVM4 ( ( unsigned int ) 0x1 << 12 ) /* (MC) Sector 4 Lock Status */ +#define AT91C_MC_GPNVM5 ( ( unsigned int ) 0x1 << 13 ) /* (MC) Sector 5 Lock Status */ +#define AT91C_MC_GPNVM6 ( ( unsigned int ) 0x1 << 14 ) /* (MC) Sector 6 Lock Status */ +#define AT91C_MC_GPNVM7 ( ( unsigned int ) 0x1 << 15 ) /* (MC) Sector 7 Lock Status */ +#define AT91C_MC_LOCKS0 ( ( unsigned int ) 0x1 << 16 ) /* (MC) Sector 0 Lock Status */ +#define AT91C_MC_LOCKS1 ( ( unsigned int ) 0x1 << 17 ) /* (MC) Sector 1 Lock Status */ +#define AT91C_MC_LOCKS2 ( ( unsigned int ) 0x1 << 18 ) /* (MC) Sector 2 Lock Status */ +#define AT91C_MC_LOCKS3 ( ( unsigned int ) 0x1 << 19 ) /* (MC) Sector 3 Lock Status */ +#define AT91C_MC_LOCKS4 ( ( unsigned int ) 0x1 << 20 ) /* (MC) Sector 4 Lock Status */ +#define AT91C_MC_LOCKS5 ( ( unsigned int ) 0x1 << 21 ) /* (MC) Sector 5 Lock Status */ +#define AT91C_MC_LOCKS6 ( ( unsigned int ) 0x1 << 22 ) /* (MC) Sector 6 Lock Status */ +#define AT91C_MC_LOCKS7 ( ( unsigned int ) 0x1 << 23 ) /* (MC) Sector 7 Lock Status */ +#define AT91C_MC_LOCKS8 ( ( unsigned int ) 0x1 << 24 ) /* (MC) Sector 8 Lock Status */ +#define AT91C_MC_LOCKS9 ( ( unsigned int ) 0x1 << 25 ) /* (MC) Sector 9 Lock Status */ +#define AT91C_MC_LOCKS10 ( ( unsigned int ) 0x1 << 26 ) /* (MC) Sector 10 Lock Status */ +#define AT91C_MC_LOCKS11 ( ( unsigned int ) 0x1 << 27 ) /* (MC) Sector 11 Lock Status */ +#define AT91C_MC_LOCKS12 ( ( unsigned int ) 0x1 << 28 ) /* (MC) Sector 12 Lock Status */ +#define AT91C_MC_LOCKS13 ( ( unsigned int ) 0x1 << 29 ) /* (MC) Sector 13 Lock Status */ +#define AT91C_MC_LOCKS14 ( ( unsigned int ) 0x1 << 30 ) /* (MC) Sector 14 Lock Status */ +#define AT91C_MC_LOCKS15 ( ( unsigned int ) 0x1 << 31 ) /* (MC) Sector 15 Lock Status */ + +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR Serial Parallel Interface */ +/* ***************************************************************************** */ +typedef struct _AT91S_SPI +{ + AT91_REG SPI_CR; /* Control Register */ + AT91_REG SPI_MR; /* Mode Register */ + AT91_REG SPI_RDR; /* Receive Data Register */ + AT91_REG SPI_TDR; /* Transmit Data Register */ + AT91_REG SPI_SR; /* Status Register */ + AT91_REG SPI_IER; /* Interrupt Enable Register */ + AT91_REG SPI_IDR; /* Interrupt Disable Register */ + AT91_REG SPI_IMR; /* Interrupt Mask Register */ + AT91_REG Reserved0[ 4 ]; /* */ + AT91_REG SPI_CSR[ 4 ]; /* Chip Select Register */ + AT91_REG Reserved1[ 48 ]; /* */ + AT91_REG SPI_RPR; /* Receive Pointer Register */ + AT91_REG SPI_RCR; /* Receive Counter Register */ + AT91_REG SPI_TPR; /* Transmit Pointer Register */ + AT91_REG SPI_TCR; /* Transmit Counter Register */ + AT91_REG SPI_RNPR; /* Receive Next Pointer Register */ + AT91_REG SPI_RNCR; /* Receive Next Counter Register */ + AT91_REG SPI_TNPR; /* Transmit Next Pointer Register */ + AT91_REG SPI_TNCR; /* Transmit Next Counter Register */ + AT91_REG SPI_PTCR; /* PDC Transfer Control Register */ + AT91_REG SPI_PTSR; /* PDC Transfer Status Register */ +} AT91S_SPI, * AT91PS_SPI; + +/* -------- SPI_CR : (SPI Offset: 0x0) SPI Control Register -------- */ +#define AT91C_SPI_SPIEN ( ( unsigned int ) 0x1 << 0 ) /* (SPI) SPI Enable */ +#define AT91C_SPI_SPIDIS ( ( unsigned int ) 0x1 << 1 ) /* (SPI) SPI Disable */ +#define AT91C_SPI_SWRST ( ( unsigned int ) 0x1 << 7 ) /* (SPI) SPI Software reset */ +#define AT91C_SPI_LASTXFER ( ( unsigned int ) 0x1 << 24 ) /* (SPI) SPI Last Transfer */ +/* -------- SPI_MR : (SPI Offset: 0x4) SPI Mode Register -------- */ +#define AT91C_SPI_MSTR ( ( unsigned int ) 0x1 << 0 ) /* (SPI) Master/Slave Mode */ +#define AT91C_SPI_PS ( ( unsigned int ) 0x1 << 1 ) /* (SPI) Peripheral Select */ +#define AT91C_SPI_PS_FIXED ( ( unsigned int ) 0x0 << 1 ) /* (SPI) Fixed Peripheral Select */ +#define AT91C_SPI_PS_VARIABLE ( ( unsigned int ) 0x1 << 1 ) /* (SPI) Variable Peripheral Select */ +#define AT91C_SPI_PCSDEC ( ( unsigned int ) 0x1 << 2 ) /* (SPI) Chip Select Decode */ +#define AT91C_SPI_FDIV ( ( unsigned int ) 0x1 << 3 ) /* (SPI) Clock Selection */ +#define AT91C_SPI_MODFDIS ( ( unsigned int ) 0x1 << 4 ) /* (SPI) Mode Fault Detection */ +#define AT91C_SPI_LLB ( ( unsigned int ) 0x1 << 7 ) /* (SPI) Clock Selection */ +#define AT91C_SPI_PCS ( ( unsigned int ) 0xF << 16 ) /* (SPI) Peripheral Chip Select */ +#define AT91C_SPI_DLYBCS ( ( unsigned int ) 0xFF << 24 ) /* (SPI) Delay Between Chip Selects */ +/* -------- SPI_RDR : (SPI Offset: 0x8) Receive Data Register -------- */ +#define AT91C_SPI_RD ( ( unsigned int ) 0xFFFF << 0 ) /* (SPI) Receive Data */ +#define AT91C_SPI_RPCS ( ( unsigned int ) 0xF << 16 ) /* (SPI) Peripheral Chip Select Status */ +/* -------- SPI_TDR : (SPI Offset: 0xc) Transmit Data Register -------- */ +#define AT91C_SPI_TD ( ( unsigned int ) 0xFFFF << 0 ) /* (SPI) Transmit Data */ +#define AT91C_SPI_TPCS ( ( unsigned int ) 0xF << 16 ) /* (SPI) Peripheral Chip Select Status */ +/* -------- SPI_SR : (SPI Offset: 0x10) Status Register -------- */ +#define AT91C_SPI_RDRF ( ( unsigned int ) 0x1 << 0 ) /* (SPI) Receive Data Register Full */ +#define AT91C_SPI_TDRE ( ( unsigned int ) 0x1 << 1 ) /* (SPI) Transmit Data Register Empty */ +#define AT91C_SPI_MODF ( ( unsigned int ) 0x1 << 2 ) /* (SPI) Mode Fault Error */ +#define AT91C_SPI_OVRES ( ( unsigned int ) 0x1 << 3 ) /* (SPI) Overrun Error Status */ +#define AT91C_SPI_ENDRX ( ( unsigned int ) 0x1 << 4 ) /* (SPI) End of Receiver Transfer */ +#define AT91C_SPI_ENDTX ( ( unsigned int ) 0x1 << 5 ) /* (SPI) End of Receiver Transfer */ +#define AT91C_SPI_RXBUFF ( ( unsigned int ) 0x1 << 6 ) /* (SPI) RXBUFF Interrupt */ +#define AT91C_SPI_TXBUFE ( ( unsigned int ) 0x1 << 7 ) /* (SPI) TXBUFE Interrupt */ +#define AT91C_SPI_NSSR ( ( unsigned int ) 0x1 << 8 ) /* (SPI) NSSR Interrupt */ +#define AT91C_SPI_TXEMPTY ( ( unsigned int ) 0x1 << 9 ) /* (SPI) TXEMPTY Interrupt */ +#define AT91C_SPI_SPIENS ( ( unsigned int ) 0x1 << 16 ) /* (SPI) Enable Status */ +/* -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register -------- */ +/* -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register -------- */ +/* -------- SPI_IMR : (SPI Offset: 0x1c) Interrupt Mask Register -------- */ +/* -------- SPI_CSR : (SPI Offset: 0x30) Chip Select Register -------- */ +#define AT91C_SPI_CPOL ( ( unsigned int ) 0x1 << 0 ) /* (SPI) Clock Polarity */ +#define AT91C_SPI_NCPHA ( ( unsigned int ) 0x1 << 1 ) /* (SPI) Clock Phase */ +#define AT91C_SPI_CSAAT ( ( unsigned int ) 0x1 << 3 ) /* (SPI) Chip Select Active After Transfer */ +#define AT91C_SPI_BITS ( ( unsigned int ) 0xF << 4 ) /* (SPI) Bits Per Transfer */ +#define AT91C_SPI_BITS_8 ( ( unsigned int ) 0x0 << 4 ) /* (SPI) 8 Bits Per transfer */ +#define AT91C_SPI_BITS_9 ( ( unsigned int ) 0x1 << 4 ) /* (SPI) 9 Bits Per transfer */ +#define AT91C_SPI_BITS_10 ( ( unsigned int ) 0x2 << 4 ) /* (SPI) 10 Bits Per transfer */ +#define AT91C_SPI_BITS_11 ( ( unsigned int ) 0x3 << 4 ) /* (SPI) 11 Bits Per transfer */ +#define AT91C_SPI_BITS_12 ( ( unsigned int ) 0x4 << 4 ) /* (SPI) 12 Bits Per transfer */ +#define AT91C_SPI_BITS_13 ( ( unsigned int ) 0x5 << 4 ) /* (SPI) 13 Bits Per transfer */ +#define AT91C_SPI_BITS_14 ( ( unsigned int ) 0x6 << 4 ) /* (SPI) 14 Bits Per transfer */ +#define AT91C_SPI_BITS_15 ( ( unsigned int ) 0x7 << 4 ) /* (SPI) 15 Bits Per transfer */ +#define AT91C_SPI_BITS_16 ( ( unsigned int ) 0x8 << 4 ) /* (SPI) 16 Bits Per transfer */ +#define AT91C_SPI_SCBR ( ( unsigned int ) 0xFF << 8 ) /* (SPI) Serial Clock Baud Rate */ +#define AT91C_SPI_DLYBS ( ( unsigned int ) 0xFF << 16 ) /* (SPI) Delay Before SPCK */ +#define AT91C_SPI_DLYBCT ( ( unsigned int ) 0xFF << 24 ) /* (SPI) Delay Between Consecutive Transfers */ + +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR Usart */ +/* ***************************************************************************** */ +typedef struct _AT91S_USART +{ + AT91_REG US_CR; /* Control Register */ + AT91_REG US_MR; /* Mode Register */ + AT91_REG US_IER; /* Interrupt Enable Register */ + AT91_REG US_IDR; /* Interrupt Disable Register */ + AT91_REG US_IMR; /* Interrupt Mask Register */ + AT91_REG US_CSR; /* Channel Status Register */ + AT91_REG US_RHR; /* Receiver Holding Register */ + AT91_REG US_THR; /* Transmitter Holding Register */ + AT91_REG US_BRGR; /* Baud Rate Generator Register */ + AT91_REG US_RTOR; /* Receiver Time-out Register */ + AT91_REG US_TTGR; /* Transmitter Time-guard Register */ + AT91_REG Reserved0[ 5 ]; /* */ + AT91_REG US_FIDI; /* FI_DI_Ratio Register */ + AT91_REG US_NER; /* Nb Errors Register */ + AT91_REG Reserved1[ 1 ]; /* */ + AT91_REG US_IF; /* IRDA_FILTER Register */ + AT91_REG Reserved2[ 44 ]; /* */ + AT91_REG US_RPR; /* Receive Pointer Register */ + AT91_REG US_RCR; /* Receive Counter Register */ + AT91_REG US_TPR; /* Transmit Pointer Register */ + AT91_REG US_TCR; /* Transmit Counter Register */ + AT91_REG US_RNPR; /* Receive Next Pointer Register */ + AT91_REG US_RNCR; /* Receive Next Counter Register */ + AT91_REG US_TNPR; /* Transmit Next Pointer Register */ + AT91_REG US_TNCR; /* Transmit Next Counter Register */ + AT91_REG US_PTCR; /* PDC Transfer Control Register */ + AT91_REG US_PTSR; /* PDC Transfer Status Register */ +} AT91S_USART, * AT91PS_USART; + +/* -------- US_CR : (USART Offset: 0x0) Debug Unit Control Register -------- */ +#define AT91C_US_STTBRK ( ( unsigned int ) 0x1 << 9 ) /* (USART) Start Break */ +#define AT91C_US_STPBRK ( ( unsigned int ) 0x1 << 10 ) /* (USART) Stop Break */ +#define AT91C_US_STTTO ( ( unsigned int ) 0x1 << 11 ) /* (USART) Start Time-out */ +#define AT91C_US_SENDA ( ( unsigned int ) 0x1 << 12 ) /* (USART) Send Address */ +#define AT91C_US_RSTIT ( ( unsigned int ) 0x1 << 13 ) /* (USART) Reset Iterations */ +#define AT91C_US_RSTNACK ( ( unsigned int ) 0x1 << 14 ) /* (USART) Reset Non Acknowledge */ +#define AT91C_US_RETTO ( ( unsigned int ) 0x1 << 15 ) /* (USART) Rearm Time-out */ +#define AT91C_US_DTREN ( ( unsigned int ) 0x1 << 16 ) /* (USART) Data Terminal ready Enable */ +#define AT91C_US_DTRDIS ( ( unsigned int ) 0x1 << 17 ) /* (USART) Data Terminal ready Disable */ +#define AT91C_US_RTSEN ( ( unsigned int ) 0x1 << 18 ) /* (USART) Request to Send enable */ +#define AT91C_US_RTSDIS ( ( unsigned int ) 0x1 << 19 ) /* (USART) Request to Send Disable */ +/* -------- US_MR : (USART Offset: 0x4) Debug Unit Mode Register -------- */ +#define AT91C_US_USMODE ( ( unsigned int ) 0xF << 0 ) /* (USART) Usart mode */ +#define AT91C_US_USMODE_NORMAL ( ( unsigned int ) 0x0 ) /* (USART) Normal */ +#define AT91C_US_USMODE_RS485 ( ( unsigned int ) 0x1 ) /* (USART) RS485 */ +#define AT91C_US_USMODE_HWHSH ( ( unsigned int ) 0x2 ) /* (USART) Hardware Handshaking */ +#define AT91C_US_USMODE_MODEM ( ( unsigned int ) 0x3 ) /* (USART) Modem */ +#define AT91C_US_USMODE_ISO7816_0 ( ( unsigned int ) 0x4 ) /* (USART) ISO7816 protocol: T = 0 */ +#define AT91C_US_USMODE_ISO7816_1 ( ( unsigned int ) 0x6 ) /* (USART) ISO7816 protocol: T = 1 */ +#define AT91C_US_USMODE_IRDA ( ( unsigned int ) 0x8 ) /* (USART) IrDA */ +#define AT91C_US_USMODE_SWHSH ( ( unsigned int ) 0xC ) /* (USART) Software Handshaking */ +#define AT91C_US_CLKS ( ( unsigned int ) 0x3 << 4 ) /* (USART) Clock Selection (Baud Rate generator Input Clock */ +#define AT91C_US_CLKS_CLOCK ( ( unsigned int ) 0x0 << 4 ) /* (USART) Clock */ +#define AT91C_US_CLKS_FDIV1 ( ( unsigned int ) 0x1 << 4 ) /* (USART) fdiv1 */ +#define AT91C_US_CLKS_SLOW ( ( unsigned int ) 0x2 << 4 ) /* (USART) slow_clock (ARM) */ +#define AT91C_US_CLKS_EXT ( ( unsigned int ) 0x3 << 4 ) /* (USART) External (SCK) */ +#define AT91C_US_CHRL ( ( unsigned int ) 0x3 << 6 ) /* (USART) Clock Selection (Baud Rate generator Input Clock */ +#define AT91C_US_CHRL_5_BITS ( ( unsigned int ) 0x0 << 6 ) /* (USART) Character Length: 5 bits */ +#define AT91C_US_CHRL_6_BITS ( ( unsigned int ) 0x1 << 6 ) /* (USART) Character Length: 6 bits */ +#define AT91C_US_CHRL_7_BITS ( ( unsigned int ) 0x2 << 6 ) /* (USART) Character Length: 7 bits */ +#define AT91C_US_CHRL_8_BITS ( ( unsigned int ) 0x3 << 6 ) /* (USART) Character Length: 8 bits */ +#define AT91C_US_SYNC ( ( unsigned int ) 0x1 << 8 ) /* (USART) Synchronous Mode Select */ +#define AT91C_US_NBSTOP ( ( unsigned int ) 0x3 << 12 ) /* (USART) Number of Stop bits */ +#define AT91C_US_NBSTOP_1_BIT ( ( unsigned int ) 0x0 << 12 ) /* (USART) 1 stop bit */ +#define AT91C_US_NBSTOP_15_BIT ( ( unsigned int ) 0x1 << 12 ) /* (USART) Asynchronous (SYNC=0) 2 stop bits Synchronous (SYNC=1) 2 stop bits */ +#define AT91C_US_NBSTOP_2_BIT ( ( unsigned int ) 0x2 << 12 ) /* (USART) 2 stop bits */ +#define AT91C_US_MSBF ( ( unsigned int ) 0x1 << 16 ) /* (USART) Bit Order */ +#define AT91C_US_MODE9 ( ( unsigned int ) 0x1 << 17 ) /* (USART) 9-bit Character length */ +#define AT91C_US_CKLO ( ( unsigned int ) 0x1 << 18 ) /* (USART) Clock Output Select */ +#define AT91C_US_OVER ( ( unsigned int ) 0x1 << 19 ) /* (USART) Over Sampling Mode */ +#define AT91C_US_INACK ( ( unsigned int ) 0x1 << 20 ) /* (USART) Inhibit Non Acknowledge */ +#define AT91C_US_DSNACK ( ( unsigned int ) 0x1 << 21 ) /* (USART) Disable Successive NACK */ +#define AT91C_US_MAX_ITER ( ( unsigned int ) 0x1 << 24 ) /* (USART) Number of Repetitions */ +#define AT91C_US_FILTER ( ( unsigned int ) 0x1 << 28 ) /* (USART) Receive Line Filter */ +/* -------- US_IER : (USART Offset: 0x8) Debug Unit Interrupt Enable Register -------- */ +#define AT91C_US_RXBRK ( ( unsigned int ) 0x1 << 2 ) /* (USART) Break Received/End of Break */ +#define AT91C_US_TIMEOUT ( ( unsigned int ) 0x1 << 8 ) /* (USART) Receiver Time-out */ +#define AT91C_US_ITERATION ( ( unsigned int ) 0x1 << 10 ) /* (USART) Max number of Repetitions Reached */ +#define AT91C_US_NACK ( ( unsigned int ) 0x1 << 13 ) /* (USART) Non Acknowledge */ +#define AT91C_US_RIIC ( ( unsigned int ) 0x1 << 16 ) /* (USART) Ring INdicator Input Change Flag */ +#define AT91C_US_DSRIC ( ( unsigned int ) 0x1 << 17 ) /* (USART) Data Set Ready Input Change Flag */ +#define AT91C_US_DCDIC ( ( unsigned int ) 0x1 << 18 ) /* (USART) Data Carrier Flag */ +#define AT91C_US_CTSIC ( ( unsigned int ) 0x1 << 19 ) /* (USART) Clear To Send Input Change Flag */ +/* -------- US_IDR : (USART Offset: 0xc) Debug Unit Interrupt Disable Register -------- */ +/* -------- US_IMR : (USART Offset: 0x10) Debug Unit Interrupt Mask Register -------- */ +/* -------- US_CSR : (USART Offset: 0x14) Debug Unit Channel Status Register -------- */ +#define AT91C_US_RI ( ( unsigned int ) 0x1 << 20 ) /* (USART) Image of RI Input */ +#define AT91C_US_DSR ( ( unsigned int ) 0x1 << 21 ) /* (USART) Image of DSR Input */ +#define AT91C_US_DCD ( ( unsigned int ) 0x1 << 22 ) /* (USART) Image of DCD Input */ +#define AT91C_US_CTS ( ( unsigned int ) 0x1 << 23 ) /* (USART) Image of CTS Input */ + +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR Synchronous Serial Controller Interface */ +/* ***************************************************************************** */ +typedef struct _AT91S_SSC +{ + AT91_REG SSC_CR; /* Control Register */ + AT91_REG SSC_CMR; /* Clock Mode Register */ + AT91_REG Reserved0[ 2 ]; /* */ + AT91_REG SSC_RCMR; /* Receive Clock ModeRegister */ + AT91_REG SSC_RFMR; /* Receive Frame Mode Register */ + AT91_REG SSC_TCMR; /* Transmit Clock Mode Register */ + AT91_REG SSC_TFMR; /* Transmit Frame Mode Register */ + AT91_REG SSC_RHR; /* Receive Holding Register */ + AT91_REG SSC_THR; /* Transmit Holding Register */ + AT91_REG Reserved1[ 2 ]; /* */ + AT91_REG SSC_RSHR; /* Receive Sync Holding Register */ + AT91_REG SSC_TSHR; /* Transmit Sync Holding Register */ + AT91_REG Reserved2[ 2 ]; /* */ + AT91_REG SSC_SR; /* Status Register */ + AT91_REG SSC_IER; /* Interrupt Enable Register */ + AT91_REG SSC_IDR; /* Interrupt Disable Register */ + AT91_REG SSC_IMR; /* Interrupt Mask Register */ + AT91_REG Reserved3[ 44 ]; /* */ + AT91_REG SSC_RPR; /* Receive Pointer Register */ + AT91_REG SSC_RCR; /* Receive Counter Register */ + AT91_REG SSC_TPR; /* Transmit Pointer Register */ + AT91_REG SSC_TCR; /* Transmit Counter Register */ + AT91_REG SSC_RNPR; /* Receive Next Pointer Register */ + AT91_REG SSC_RNCR; /* Receive Next Counter Register */ + AT91_REG SSC_TNPR; /* Transmit Next Pointer Register */ + AT91_REG SSC_TNCR; /* Transmit Next Counter Register */ + AT91_REG SSC_PTCR; /* PDC Transfer Control Register */ + AT91_REG SSC_PTSR; /* PDC Transfer Status Register */ +} AT91S_SSC, * AT91PS_SSC; + +/* -------- SSC_CR : (SSC Offset: 0x0) SSC Control Register -------- */ +#define AT91C_SSC_RXEN ( ( unsigned int ) 0x1 << 0 ) /* (SSC) Receive Enable */ +#define AT91C_SSC_RXDIS ( ( unsigned int ) 0x1 << 1 ) /* (SSC) Receive Disable */ +#define AT91C_SSC_TXEN ( ( unsigned int ) 0x1 << 8 ) /* (SSC) Transmit Enable */ +#define AT91C_SSC_TXDIS ( ( unsigned int ) 0x1 << 9 ) /* (SSC) Transmit Disable */ +#define AT91C_SSC_SWRST ( ( unsigned int ) 0x1 << 15 ) /* (SSC) Software Reset */ +/* -------- SSC_RCMR : (SSC Offset: 0x10) SSC Receive Clock Mode Register -------- */ +#define AT91C_SSC_CKS ( ( unsigned int ) 0x3 << 0 ) /* (SSC) Receive/Transmit Clock Selection */ +#define AT91C_SSC_CKS_DIV ( ( unsigned int ) 0x0 ) /* (SSC) Divided Clock */ +#define AT91C_SSC_CKS_TK ( ( unsigned int ) 0x1 ) /* (SSC) TK Clock signal */ +#define AT91C_SSC_CKS_RK ( ( unsigned int ) 0x2 ) /* (SSC) RK pin */ +#define AT91C_SSC_CKO ( ( unsigned int ) 0x7 << 2 ) /* (SSC) Receive/Transmit Clock Output Mode Selection */ +#define AT91C_SSC_CKO_NONE ( ( unsigned int ) 0x0 << 2 ) /* (SSC) Receive/Transmit Clock Output Mode: None RK pin: Input-only */ +#define AT91C_SSC_CKO_CONTINUOUS ( ( unsigned int ) 0x1 << 2 ) /* (SSC) Continuous Receive/Transmit Clock RK pin: Output */ +#define AT91C_SSC_CKO_DATA_TX ( ( unsigned int ) 0x2 << 2 ) /* (SSC) Receive/Transmit Clock only during data transfers RK pin: Output */ +#define AT91C_SSC_CKI ( ( unsigned int ) 0x1 << 5 ) /* (SSC) Receive/Transmit Clock Inversion */ +#define AT91C_SSC_START ( ( unsigned int ) 0xF << 8 ) /* (SSC) Receive/Transmit Start Selection */ +#define AT91C_SSC_START_CONTINUOUS ( ( unsigned int ) 0x0 << 8 ) /* (SSC) Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data. */ +#define AT91C_SSC_START_TX ( ( unsigned int ) 0x1 << 8 ) /* (SSC) Transmit/Receive start */ +#define AT91C_SSC_START_LOW_RF ( ( unsigned int ) 0x2 << 8 ) /* (SSC) Detection of a low level on RF input */ +#define AT91C_SSC_START_HIGH_RF ( ( unsigned int ) 0x3 << 8 ) /* (SSC) Detection of a high level on RF input */ +#define AT91C_SSC_START_FALL_RF ( ( unsigned int ) 0x4 << 8 ) /* (SSC) Detection of a falling edge on RF input */ +#define AT91C_SSC_START_RISE_RF ( ( unsigned int ) 0x5 << 8 ) /* (SSC) Detection of a rising edge on RF input */ +#define AT91C_SSC_START_LEVEL_RF ( ( unsigned int ) 0x6 << 8 ) /* (SSC) Detection of any level change on RF input */ +#define AT91C_SSC_START_EDGE_RF ( ( unsigned int ) 0x7 << 8 ) /* (SSC) Detection of any edge on RF input */ +#define AT91C_SSC_START_0 ( ( unsigned int ) 0x8 << 8 ) /* (SSC) Compare 0 */ +#define AT91C_SSC_STTDLY ( ( unsigned int ) 0xFF << 16 ) /* (SSC) Receive/Transmit Start Delay */ +#define AT91C_SSC_PERIOD ( ( unsigned int ) 0xFF << 24 ) /* (SSC) Receive/Transmit Period Divider Selection */ +/* -------- SSC_RFMR : (SSC Offset: 0x14) SSC Receive Frame Mode Register -------- */ +#define AT91C_SSC_DATLEN ( ( unsigned int ) 0x1F << 0 ) /* (SSC) Data Length */ +#define AT91C_SSC_LOOP ( ( unsigned int ) 0x1 << 5 ) /* (SSC) Loop Mode */ +#define AT91C_SSC_MSBF ( ( unsigned int ) 0x1 << 7 ) /* (SSC) Most Significant Bit First */ +#define AT91C_SSC_DATNB ( ( unsigned int ) 0xF << 8 ) /* (SSC) Data Number per Frame */ +#define AT91C_SSC_FSLEN ( ( unsigned int ) 0xF << 16 ) /* (SSC) Receive/Transmit Frame Sync length */ +#define AT91C_SSC_FSOS ( ( unsigned int ) 0x7 << 20 ) /* (SSC) Receive/Transmit Frame Sync Output Selection */ +#define AT91C_SSC_FSOS_NONE ( ( unsigned int ) 0x0 << 20 ) /* (SSC) Selected Receive/Transmit Frame Sync Signal: None RK pin Input-only */ +#define AT91C_SSC_FSOS_NEGATIVE ( ( unsigned int ) 0x1 << 20 ) /* (SSC) Selected Receive/Transmit Frame Sync Signal: Negative Pulse */ +#define AT91C_SSC_FSOS_POSITIVE ( ( unsigned int ) 0x2 << 20 ) /* (SSC) Selected Receive/Transmit Frame Sync Signal: Positive Pulse */ +#define AT91C_SSC_FSOS_LOW ( ( unsigned int ) 0x3 << 20 ) /* (SSC) Selected Receive/Transmit Frame Sync Signal: Driver Low during data transfer */ +#define AT91C_SSC_FSOS_HIGH ( ( unsigned int ) 0x4 << 20 ) /* (SSC) Selected Receive/Transmit Frame Sync Signal: Driver High during data transfer */ +#define AT91C_SSC_FSOS_TOGGLE ( ( unsigned int ) 0x5 << 20 ) /* (SSC) Selected Receive/Transmit Frame Sync Signal: Toggling at each start of data transfer */ +#define AT91C_SSC_FSEDGE ( ( unsigned int ) 0x1 << 24 ) /* (SSC) Frame Sync Edge Detection */ +/* -------- SSC_TCMR : (SSC Offset: 0x18) SSC Transmit Clock Mode Register -------- */ +/* -------- SSC_TFMR : (SSC Offset: 0x1c) SSC Transmit Frame Mode Register -------- */ +#define AT91C_SSC_DATDEF ( ( unsigned int ) 0x1 << 5 ) /* (SSC) Data Default Value */ +#define AT91C_SSC_FSDEN ( ( unsigned int ) 0x1 << 23 ) /* (SSC) Frame Sync Data Enable */ +/* -------- SSC_SR : (SSC Offset: 0x40) SSC Status Register -------- */ +#define AT91C_SSC_TXRDY ( ( unsigned int ) 0x1 << 0 ) /* (SSC) Transmit Ready */ +#define AT91C_SSC_TXEMPTY ( ( unsigned int ) 0x1 << 1 ) /* (SSC) Transmit Empty */ +#define AT91C_SSC_ENDTX ( ( unsigned int ) 0x1 << 2 ) /* (SSC) End Of Transmission */ +#define AT91C_SSC_TXBUFE ( ( unsigned int ) 0x1 << 3 ) /* (SSC) Transmit Buffer Empty */ +#define AT91C_SSC_RXRDY ( ( unsigned int ) 0x1 << 4 ) /* (SSC) Receive Ready */ +#define AT91C_SSC_OVRUN ( ( unsigned int ) 0x1 << 5 ) /* (SSC) Receive Overrun */ +#define AT91C_SSC_ENDRX ( ( unsigned int ) 0x1 << 6 ) /* (SSC) End of Reception */ +#define AT91C_SSC_RXBUFF ( ( unsigned int ) 0x1 << 7 ) /* (SSC) Receive Buffer Full */ +#define AT91C_SSC_TXSYN ( ( unsigned int ) 0x1 << 10 ) /* (SSC) Transmit Sync */ +#define AT91C_SSC_RXSYN ( ( unsigned int ) 0x1 << 11 ) /* (SSC) Receive Sync */ +#define AT91C_SSC_TXENA ( ( unsigned int ) 0x1 << 16 ) /* (SSC) Transmit Enable */ +#define AT91C_SSC_RXENA ( ( unsigned int ) 0x1 << 17 ) /* (SSC) Receive Enable */ +/* -------- SSC_IER : (SSC Offset: 0x44) SSC Interrupt Enable Register -------- */ +/* -------- SSC_IDR : (SSC Offset: 0x48) SSC Interrupt Disable Register -------- */ +/* -------- SSC_IMR : (SSC Offset: 0x4c) SSC Interrupt Mask Register -------- */ + +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR Two-wire Interface */ +/* ***************************************************************************** */ +typedef struct _AT91S_TWI +{ + AT91_REG TWI_CR; /* Control Register */ + AT91_REG TWI_MMR; /* Master Mode Register */ + AT91_REG Reserved0[ 1 ]; /* */ + AT91_REG TWI_IADR; /* Internal Address Register */ + AT91_REG TWI_CWGR; /* Clock Waveform Generator Register */ + AT91_REG Reserved1[ 3 ]; /* */ + AT91_REG TWI_SR; /* Status Register */ + AT91_REG TWI_IER; /* Interrupt Enable Register */ + AT91_REG TWI_IDR; /* Interrupt Disable Register */ + AT91_REG TWI_IMR; /* Interrupt Mask Register */ + AT91_REG TWI_RHR; /* Receive Holding Register */ + AT91_REG TWI_THR; /* Transmit Holding Register */ +} AT91S_TWI, * AT91PS_TWI; + +/* -------- TWI_CR : (TWI Offset: 0x0) TWI Control Register -------- */ +#define AT91C_TWI_START ( ( unsigned int ) 0x1 << 0 ) /* (TWI) Send a START Condition */ +#define AT91C_TWI_STOP ( ( unsigned int ) 0x1 << 1 ) /* (TWI) Send a STOP Condition */ +#define AT91C_TWI_MSEN ( ( unsigned int ) 0x1 << 2 ) /* (TWI) TWI Master Transfer Enabled */ +#define AT91C_TWI_MSDIS ( ( unsigned int ) 0x1 << 3 ) /* (TWI) TWI Master Transfer Disabled */ +#define AT91C_TWI_SWRST ( ( unsigned int ) 0x1 << 7 ) /* (TWI) Software Reset */ +/* -------- TWI_MMR : (TWI Offset: 0x4) TWI Master Mode Register -------- */ +#define AT91C_TWI_IADRSZ ( ( unsigned int ) 0x3 << 8 ) /* (TWI) Internal Device Address Size */ +#define AT91C_TWI_IADRSZ_NO ( ( unsigned int ) 0x0 << 8 ) /* (TWI) No internal device address */ +#define AT91C_TWI_IADRSZ_1_BYTE ( ( unsigned int ) 0x1 << 8 ) /* (TWI) One-byte internal device address */ +#define AT91C_TWI_IADRSZ_2_BYTE ( ( unsigned int ) 0x2 << 8 ) /* (TWI) Two-byte internal device address */ +#define AT91C_TWI_IADRSZ_3_BYTE ( ( unsigned int ) 0x3 << 8 ) /* (TWI) Three-byte internal device address */ +#define AT91C_TWI_MREAD ( ( unsigned int ) 0x1 << 12 ) /* (TWI) Master Read Direction */ +#define AT91C_TWI_DADR ( ( unsigned int ) 0x7F << 16 ) /* (TWI) Device Address */ +/* -------- TWI_CWGR : (TWI Offset: 0x10) TWI Clock Waveform Generator Register -------- */ +#define AT91C_TWI_CLDIV ( ( unsigned int ) 0xFF << 0 ) /* (TWI) Clock Low Divider */ +#define AT91C_TWI_CHDIV ( ( unsigned int ) 0xFF << 8 ) /* (TWI) Clock High Divider */ +#define AT91C_TWI_CKDIV ( ( unsigned int ) 0x7 << 16 ) /* (TWI) Clock Divider */ +/* -------- TWI_SR : (TWI Offset: 0x20) TWI Status Register -------- */ +#define AT91C_TWI_TXCOMP ( ( unsigned int ) 0x1 << 0 ) /* (TWI) Transmission Completed */ +#define AT91C_TWI_RXRDY ( ( unsigned int ) 0x1 << 1 ) /* (TWI) Receive holding register ReaDY */ +#define AT91C_TWI_TXRDY ( ( unsigned int ) 0x1 << 2 ) /* (TWI) Transmit holding register ReaDY */ +#define AT91C_TWI_OVRE ( ( unsigned int ) 0x1 << 6 ) /* (TWI) Overrun Error */ +#define AT91C_TWI_UNRE ( ( unsigned int ) 0x1 << 7 ) /* (TWI) Underrun Error */ +#define AT91C_TWI_NACK ( ( unsigned int ) 0x1 << 8 ) /* (TWI) Not Acknowledged */ +/* -------- TWI_IER : (TWI Offset: 0x24) TWI Interrupt Enable Register -------- */ +/* -------- TWI_IDR : (TWI Offset: 0x28) TWI Interrupt Disable Register -------- */ +/* -------- TWI_IMR : (TWI Offset: 0x2c) TWI Interrupt Mask Register -------- */ + +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR PWMC Channel Interface */ +/* ***************************************************************************** */ +typedef struct _AT91S_PWMC_CH +{ + AT91_REG PWMC_CMR; /* Channel Mode Register */ + AT91_REG PWMC_CDTYR; /* Channel Duty Cycle Register */ + AT91_REG PWMC_CPRDR; /* Channel Period Register */ + AT91_REG PWMC_CCNTR; /* Channel Counter Register */ + AT91_REG PWMC_CUPDR; /* Channel Update Register */ + AT91_REG PWMC_Reserved[ 3 ]; /* Reserved */ +} AT91S_PWMC_CH, * AT91PS_PWMC_CH; + +/* -------- PWMC_CMR : (PWMC_CH Offset: 0x0) PWMC Channel Mode Register -------- */ +#define AT91C_PWMC_CPRE ( ( unsigned int ) 0xF << 0 ) /* (PWMC_CH) Channel Pre-scaler : PWMC_CLKx */ +#define AT91C_PWMC_CPRE_MCK ( ( unsigned int ) 0x0 ) /* (PWMC_CH) */ +#define AT91C_PWMC_CPRE_MCKA ( ( unsigned int ) 0xB ) /* (PWMC_CH) */ +#define AT91C_PWMC_CPRE_MCKB ( ( unsigned int ) 0xC ) /* (PWMC_CH) */ +#define AT91C_PWMC_CALG ( ( unsigned int ) 0x1 << 8 ) /* (PWMC_CH) Channel Alignment */ +#define AT91C_PWMC_CPOL ( ( unsigned int ) 0x1 << 9 ) /* (PWMC_CH) Channel Polarity */ +#define AT91C_PWMC_CPD ( ( unsigned int ) 0x1 << 10 ) /* (PWMC_CH) Channel Update Period */ +/* -------- PWMC_CDTYR : (PWMC_CH Offset: 0x4) PWMC Channel Duty Cycle Register -------- */ +#define AT91C_PWMC_CDTY ( ( unsigned int ) 0x0 << 0 ) /* (PWMC_CH) Channel Duty Cycle */ +/* -------- PWMC_CPRDR : (PWMC_CH Offset: 0x8) PWMC Channel Period Register -------- */ +#define AT91C_PWMC_CPRD ( ( unsigned int ) 0x0 << 0 ) /* (PWMC_CH) Channel Period */ +/* -------- PWMC_CCNTR : (PWMC_CH Offset: 0xc) PWMC Channel Counter Register -------- */ +#define AT91C_PWMC_CCNT ( ( unsigned int ) 0x0 << 0 ) /* (PWMC_CH) Channel Counter */ +/* -------- PWMC_CUPDR : (PWMC_CH Offset: 0x10) PWMC Channel Update Register -------- */ +#define AT91C_PWMC_CUPD ( ( unsigned int ) 0x0 << 0 ) /* (PWMC_CH) Channel Update */ + +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR Pulse Width Modulation Controller Interface */ +/* ***************************************************************************** */ +typedef struct _AT91S_PWMC +{ + AT91_REG PWMC_MR; /* PWMC Mode Register */ + AT91_REG PWMC_ENA; /* PWMC Enable Register */ + AT91_REG PWMC_DIS; /* PWMC Disable Register */ + AT91_REG PWMC_SR; /* PWMC Status Register */ + AT91_REG PWMC_IER; /* PWMC Interrupt Enable Register */ + AT91_REG PWMC_IDR; /* PWMC Interrupt Disable Register */ + AT91_REG PWMC_IMR; /* PWMC Interrupt Mask Register */ + AT91_REG PWMC_ISR; /* PWMC Interrupt Status Register */ + AT91_REG Reserved0[ 55 ]; /* */ + AT91_REG PWMC_VR; /* PWMC Version Register */ + AT91_REG Reserved1[ 64 ]; /* */ + AT91S_PWMC_CH PWMC_CH[ 4 ]; /* PWMC Channel */ +} AT91S_PWMC, * AT91PS_PWMC; + +/* -------- PWMC_MR : (PWMC Offset: 0x0) PWMC Mode Register -------- */ +#define AT91C_PWMC_DIVA ( ( unsigned int ) 0xFF << 0 ) /* (PWMC) CLKA divide factor. */ +#define AT91C_PWMC_PREA ( ( unsigned int ) 0xF << 8 ) /* (PWMC) Divider Input Clock Prescaler A */ +#define AT91C_PWMC_PREA_MCK ( ( unsigned int ) 0x0 << 8 ) /* (PWMC) */ +#define AT91C_PWMC_DIVB ( ( unsigned int ) 0xFF << 16 ) /* (PWMC) CLKB divide factor. */ +#define AT91C_PWMC_PREB ( ( unsigned int ) 0xF << 24 ) /* (PWMC) Divider Input Clock Prescaler B */ +#define AT91C_PWMC_PREB_MCK ( ( unsigned int ) 0x0 << 24 ) /* (PWMC) */ +/* -------- PWMC_ENA : (PWMC Offset: 0x4) PWMC Enable Register -------- */ +#define AT91C_PWMC_CHID0 ( ( unsigned int ) 0x1 << 0 ) /* (PWMC) Channel ID 0 */ +#define AT91C_PWMC_CHID1 ( ( unsigned int ) 0x1 << 1 ) /* (PWMC) Channel ID 1 */ +#define AT91C_PWMC_CHID2 ( ( unsigned int ) 0x1 << 2 ) /* (PWMC) Channel ID 2 */ +#define AT91C_PWMC_CHID3 ( ( unsigned int ) 0x1 << 3 ) /* (PWMC) Channel ID 3 */ +/* -------- PWMC_DIS : (PWMC Offset: 0x8) PWMC Disable Register -------- */ +/* -------- PWMC_SR : (PWMC Offset: 0xc) PWMC Status Register -------- */ +/* -------- PWMC_IER : (PWMC Offset: 0x10) PWMC Interrupt Enable Register -------- */ +/* -------- PWMC_IDR : (PWMC Offset: 0x14) PWMC Interrupt Disable Register -------- */ +/* -------- PWMC_IMR : (PWMC Offset: 0x18) PWMC Interrupt Mask Register -------- */ +/* -------- PWMC_ISR : (PWMC Offset: 0x1c) PWMC Interrupt Status Register -------- */ + +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR USB Device Interface */ +/* ***************************************************************************** */ +typedef struct _AT91S_UDP +{ + AT91_REG UDP_NUM; /* Frame Number Register */ + AT91_REG UDP_GLBSTATE; /* Global State Register */ + AT91_REG UDP_FADDR; /* Function Address Register */ + AT91_REG Reserved0[ 1 ]; /* */ + AT91_REG UDP_IER; /* Interrupt Enable Register */ + AT91_REG UDP_IDR; /* Interrupt Disable Register */ + AT91_REG UDP_IMR; /* Interrupt Mask Register */ + AT91_REG UDP_ISR; /* Interrupt Status Register */ + AT91_REG UDP_ICR; /* Interrupt Clear Register */ + AT91_REG Reserved1[ 1 ]; /* */ + AT91_REG UDP_RSTEP; /* Reset Endpoint Register */ + AT91_REG Reserved2[ 1 ]; /* */ + AT91_REG UDP_CSR[ 6 ]; /* Endpoint Control and Status Register */ + AT91_REG Reserved3[ 2 ]; /* */ + AT91_REG UDP_FDR[ 6 ]; /* Endpoint FIFO Data Register */ + AT91_REG Reserved4[ 3 ]; /* */ + AT91_REG UDP_TXVC; /* Transceiver Control Register */ +} AT91S_UDP, * AT91PS_UDP; + +/* -------- UDP_FRM_NUM : (UDP Offset: 0x0) USB Frame Number Register -------- */ +#define AT91C_UDP_FRM_NUM ( ( unsigned int ) 0x7FF << 0 ) /* (UDP) Frame Number as Defined in the Packet Field Formats */ +#define AT91C_UDP_FRM_ERR ( ( unsigned int ) 0x1 << 16 ) /* (UDP) Frame Error */ +#define AT91C_UDP_FRM_OK ( ( unsigned int ) 0x1 << 17 ) /* (UDP) Frame OK */ +/* -------- UDP_GLB_STATE : (UDP Offset: 0x4) USB Global State Register -------- */ +#define AT91C_UDP_FADDEN ( ( unsigned int ) 0x1 << 0 ) /* (UDP) Function Address Enable */ +#define AT91C_UDP_CONFG ( ( unsigned int ) 0x1 << 1 ) /* (UDP) Configured */ +#define AT91C_UDP_ESR ( ( unsigned int ) 0x1 << 2 ) /* (UDP) Enable Send Resume */ +#define AT91C_UDP_RSMINPR ( ( unsigned int ) 0x1 << 3 ) /* (UDP) A Resume Has Been Sent to the Host */ +#define AT91C_UDP_RMWUPE ( ( unsigned int ) 0x1 << 4 ) /* (UDP) Remote Wake Up Enable */ +/* -------- UDP_FADDR : (UDP Offset: 0x8) USB Function Address Register -------- */ +#define AT91C_UDP_FADD ( ( unsigned int ) 0xFF << 0 ) /* (UDP) Function Address Value */ +#define AT91C_UDP_FEN ( ( unsigned int ) 0x1 << 8 ) /* (UDP) Function Enable */ +/* -------- UDP_IER : (UDP Offset: 0x10) USB Interrupt Enable Register -------- */ +#define AT91C_UDP_EPINT0 ( ( unsigned int ) 0x1 << 0 ) /* (UDP) Endpoint 0 Interrupt */ +#define AT91C_UDP_EPINT1 ( ( unsigned int ) 0x1 << 1 ) /* (UDP) Endpoint 0 Interrupt */ +#define AT91C_UDP_EPINT2 ( ( unsigned int ) 0x1 << 2 ) /* (UDP) Endpoint 2 Interrupt */ +#define AT91C_UDP_EPINT3 ( ( unsigned int ) 0x1 << 3 ) /* (UDP) Endpoint 3 Interrupt */ +#define AT91C_UDP_EPINT4 ( ( unsigned int ) 0x1 << 4 ) /* (UDP) Endpoint 4 Interrupt */ +#define AT91C_UDP_EPINT5 ( ( unsigned int ) 0x1 << 5 ) /* (UDP) Endpoint 5 Interrupt */ +#define AT91C_UDP_RXSUSP ( ( unsigned int ) 0x1 << 8 ) /* (UDP) USB Suspend Interrupt */ +#define AT91C_UDP_RXRSM ( ( unsigned int ) 0x1 << 9 ) /* (UDP) USB Resume Interrupt */ +#define AT91C_UDP_EXTRSM ( ( unsigned int ) 0x1 << 10 ) /* (UDP) USB External Resume Interrupt */ +#define AT91C_UDP_SOFINT ( ( unsigned int ) 0x1 << 11 ) /* (UDP) USB Start Of frame Interrupt */ +#define AT91C_UDP_WAKEUP ( ( unsigned int ) 0x1 << 13 ) /* (UDP) USB Resume Interrupt */ +/* -------- UDP_IDR : (UDP Offset: 0x14) USB Interrupt Disable Register -------- */ +/* -------- UDP_IMR : (UDP Offset: 0x18) USB Interrupt Mask Register -------- */ +/* -------- UDP_ISR : (UDP Offset: 0x1c) USB Interrupt Status Register -------- */ +#define AT91C_UDP_ENDBUSRES ( ( unsigned int ) 0x1 << 12 ) /* (UDP) USB End Of Bus Reset Interrupt */ +/* -------- UDP_ICR : (UDP Offset: 0x20) USB Interrupt Clear Register -------- */ +/* -------- UDP_RST_EP : (UDP Offset: 0x28) USB Reset Endpoint Register -------- */ +#define AT91C_UDP_EP0 ( ( unsigned int ) 0x1 << 0 ) /* (UDP) Reset Endpoint 0 */ +#define AT91C_UDP_EP1 ( ( unsigned int ) 0x1 << 1 ) /* (UDP) Reset Endpoint 1 */ +#define AT91C_UDP_EP2 ( ( unsigned int ) 0x1 << 2 ) /* (UDP) Reset Endpoint 2 */ +#define AT91C_UDP_EP3 ( ( unsigned int ) 0x1 << 3 ) /* (UDP) Reset Endpoint 3 */ +#define AT91C_UDP_EP4 ( ( unsigned int ) 0x1 << 4 ) /* (UDP) Reset Endpoint 4 */ +#define AT91C_UDP_EP5 ( ( unsigned int ) 0x1 << 5 ) /* (UDP) Reset Endpoint 5 */ +/* -------- UDP_CSR : (UDP Offset: 0x30) USB Endpoint Control and Status Register -------- */ +#define AT91C_UDP_TXCOMP ( ( unsigned int ) 0x1 << 0 ) /* (UDP) Generates an IN packet with data previously written in the DPR */ +#define AT91C_UDP_RX_DATA_BK0 ( ( unsigned int ) 0x1 << 1 ) /* (UDP) Receive Data Bank 0 */ +#define AT91C_UDP_RXSETUP ( ( unsigned int ) 0x1 << 2 ) /* (UDP) Sends STALL to the Host (Control endpoints) */ +#define AT91C_UDP_ISOERROR ( ( unsigned int ) 0x1 << 3 ) /* (UDP) Isochronous error (Isochronous endpoints) */ +#define AT91C_UDP_TXPKTRDY ( ( unsigned int ) 0x1 << 4 ) /* (UDP) Transmit Packet Ready */ +#define AT91C_UDP_FORCESTALL ( ( unsigned int ) 0x1 << 5 ) /* (UDP) Force Stall (used by Control, Bulk and Isochronous endpoints). */ +#define AT91C_UDP_RX_DATA_BK1 ( ( unsigned int ) 0x1 << 6 ) /* (UDP) Receive Data Bank 1 (only used by endpoints with ping-pong attributes). */ +#define AT91C_UDP_DIR ( ( unsigned int ) 0x1 << 7 ) /* (UDP) Transfer Direction */ +#define AT91C_UDP_EPTYPE ( ( unsigned int ) 0x7 << 8 ) /* (UDP) Endpoint type */ +#define AT91C_UDP_EPTYPE_CTRL ( ( unsigned int ) 0x0 << 8 ) /* (UDP) Control */ +#define AT91C_UDP_EPTYPE_ISO_OUT ( ( unsigned int ) 0x1 << 8 ) /* (UDP) Isochronous OUT */ +#define AT91C_UDP_EPTYPE_BULK_OUT ( ( unsigned int ) 0x2 << 8 ) /* (UDP) Bulk OUT */ +#define AT91C_UDP_EPTYPE_INT_OUT ( ( unsigned int ) 0x3 << 8 ) /* (UDP) Interrupt OUT */ +#define AT91C_UDP_EPTYPE_ISO_IN ( ( unsigned int ) 0x5 << 8 ) /* (UDP) Isochronous IN */ +#define AT91C_UDP_EPTYPE_BULK_IN ( ( unsigned int ) 0x6 << 8 ) /* (UDP) Bulk IN */ +#define AT91C_UDP_EPTYPE_INT_IN ( ( unsigned int ) 0x7 << 8 ) /* (UDP) Interrupt IN */ +#define AT91C_UDP_DTGLE ( ( unsigned int ) 0x1 << 11 ) /* (UDP) Data Toggle */ +#define AT91C_UDP_EPEDS ( ( unsigned int ) 0x1 << 15 ) /* (UDP) Endpoint Enable Disable */ +#define AT91C_UDP_RXBYTECNT ( ( unsigned int ) 0x7FF << 16 ) /* (UDP) Number Of Bytes Available in the FIFO */ +/* -------- UDP_TXVC : (UDP Offset: 0x74) Transceiver Control Register -------- */ +#define AT91C_UDP_TXVDIS ( ( unsigned int ) 0x1 << 8 ) /* (UDP) */ +#define AT91C_UDP_PUON ( ( unsigned int ) 0x1 << 9 ) /* (UDP) Pull-up ON */ + +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR Timer Counter Channel Interface */ +/* ***************************************************************************** */ +typedef struct _AT91S_TC +{ + AT91_REG TC_CCR; /* Channel Control Register */ + AT91_REG TC_CMR; /* Channel Mode Register (Capture Mode / Waveform Mode) */ + AT91_REG Reserved0[ 2 ]; /* */ + AT91_REG TC_CV; /* Counter Value */ + AT91_REG TC_RA; /* Register A */ + AT91_REG TC_RB; /* Register B */ + AT91_REG TC_RC; /* Register C */ + AT91_REG TC_SR; /* Status Register */ + AT91_REG TC_IER; /* Interrupt Enable Register */ + AT91_REG TC_IDR; /* Interrupt Disable Register */ + AT91_REG TC_IMR; /* Interrupt Mask Register */ +} AT91S_TC, * AT91PS_TC; + +/* -------- TC_CCR : (TC Offset: 0x0) TC Channel Control Register -------- */ +#define AT91C_TC_CLKEN ( ( unsigned int ) 0x1 << 0 ) /* (TC) Counter Clock Enable Command */ +#define AT91C_TC_CLKDIS ( ( unsigned int ) 0x1 << 1 ) /* (TC) Counter Clock Disable Command */ +#define AT91C_TC_SWTRG ( ( unsigned int ) 0x1 << 2 ) /* (TC) Software Trigger Command */ +/* -------- TC_CMR : (TC Offset: 0x4) TC Channel Mode Register: Capture Mode / Waveform Mode -------- */ +#define AT91C_TC_CLKS ( ( unsigned int ) 0x7 << 0 ) /* (TC) Clock Selection */ +#define AT91C_TC_CLKS_TIMER_DIV1_CLOCK ( ( unsigned int ) 0x0 ) /* (TC) Clock selected: TIMER_DIV1_CLOCK */ +#define AT91C_TC_CLKS_TIMER_DIV2_CLOCK ( ( unsigned int ) 0x1 ) /* (TC) Clock selected: TIMER_DIV2_CLOCK */ +#define AT91C_TC_CLKS_TIMER_DIV3_CLOCK ( ( unsigned int ) 0x2 ) /* (TC) Clock selected: TIMER_DIV3_CLOCK */ +#define AT91C_TC_CLKS_TIMER_DIV4_CLOCK ( ( unsigned int ) 0x3 ) /* (TC) Clock selected: TIMER_DIV4_CLOCK */ +#define AT91C_TC_CLKS_TIMER_DIV5_CLOCK ( ( unsigned int ) 0x4 ) /* (TC) Clock selected: TIMER_DIV5_CLOCK */ +#define AT91C_TC_CLKS_XC0 ( ( unsigned int ) 0x5 ) /* (TC) Clock selected: XC0 */ +#define AT91C_TC_CLKS_XC1 ( ( unsigned int ) 0x6 ) /* (TC) Clock selected: XC1 */ +#define AT91C_TC_CLKS_XC2 ( ( unsigned int ) 0x7 ) /* (TC) Clock selected: XC2 */ +#define AT91C_TC_CLKI ( ( unsigned int ) 0x1 << 3 ) /* (TC) Clock Invert */ +#define AT91C_TC_BURST ( ( unsigned int ) 0x3 << 4 ) /* (TC) Burst Signal Selection */ +#define AT91C_TC_BURST_NONE ( ( unsigned int ) 0x0 << 4 ) /* (TC) The clock is not gated by an external signal */ +#define AT91C_TC_BURST_XC0 ( ( unsigned int ) 0x1 << 4 ) /* (TC) XC0 is ANDed with the selected clock */ +#define AT91C_TC_BURST_XC1 ( ( unsigned int ) 0x2 << 4 ) /* (TC) XC1 is ANDed with the selected clock */ +#define AT91C_TC_BURST_XC2 ( ( unsigned int ) 0x3 << 4 ) /* (TC) XC2 is ANDed with the selected clock */ +#define AT91C_TC_CPCSTOP ( ( unsigned int ) 0x1 << 6 ) /* (TC) Counter Clock Stopped with RC Compare */ +#define AT91C_TC_LDBSTOP ( ( unsigned int ) 0x1 << 6 ) /* (TC) Counter Clock Stopped with RB Loading */ +#define AT91C_TC_CPCDIS ( ( unsigned int ) 0x1 << 7 ) /* (TC) Counter Clock Disable with RC Compare */ +#define AT91C_TC_LDBDIS ( ( unsigned int ) 0x1 << 7 ) /* (TC) Counter Clock Disabled with RB Loading */ +#define AT91C_TC_ETRGEDG ( ( unsigned int ) 0x3 << 8 ) /* (TC) External Trigger Edge Selection */ +#define AT91C_TC_ETRGEDG_NONE ( ( unsigned int ) 0x0 << 8 ) /* (TC) Edge: None */ +#define AT91C_TC_ETRGEDG_RISING ( ( unsigned int ) 0x1 << 8 ) /* (TC) Edge: rising edge */ +#define AT91C_TC_ETRGEDG_FALLING ( ( unsigned int ) 0x2 << 8 ) /* (TC) Edge: falling edge */ +#define AT91C_TC_ETRGEDG_BOTH ( ( unsigned int ) 0x3 << 8 ) /* (TC) Edge: each edge */ +#define AT91C_TC_EEVTEDG ( ( unsigned int ) 0x3 << 8 ) /* (TC) External Event Edge Selection */ +#define AT91C_TC_EEVTEDG_NONE ( ( unsigned int ) 0x0 << 8 ) /* (TC) Edge: None */ +#define AT91C_TC_EEVTEDG_RISING ( ( unsigned int ) 0x1 << 8 ) /* (TC) Edge: rising edge */ +#define AT91C_TC_EEVTEDG_FALLING ( ( unsigned int ) 0x2 << 8 ) /* (TC) Edge: falling edge */ +#define AT91C_TC_EEVTEDG_BOTH ( ( unsigned int ) 0x3 << 8 ) /* (TC) Edge: each edge */ +#define AT91C_TC_EEVT ( ( unsigned int ) 0x3 << 10 ) /* (TC) External Event Selection */ +#define AT91C_TC_EEVT_TIOB ( ( unsigned int ) 0x0 << 10 ) /* (TC) Signal selected as external event: TIOB TIOB direction: input */ +#define AT91C_TC_EEVT_XC0 ( ( unsigned int ) 0x1 << 10 ) /* (TC) Signal selected as external event: XC0 TIOB direction: output */ +#define AT91C_TC_EEVT_XC1 ( ( unsigned int ) 0x2 << 10 ) /* (TC) Signal selected as external event: XC1 TIOB direction: output */ +#define AT91C_TC_EEVT_XC2 ( ( unsigned int ) 0x3 << 10 ) /* (TC) Signal selected as external event: XC2 TIOB direction: output */ +#define AT91C_TC_ABETRG ( ( unsigned int ) 0x1 << 10 ) /* (TC) TIOA or TIOB External Trigger Selection */ +#define AT91C_TC_ENETRG ( ( unsigned int ) 0x1 << 12 ) /* (TC) External Event Trigger enable */ +#define AT91C_TC_WAVESEL ( ( unsigned int ) 0x3 << 13 ) /* (TC) Waveform Selection */ +#define AT91C_TC_WAVESEL_UP ( ( unsigned int ) 0x0 << 13 ) /* (TC) UP mode without atomatic trigger on RC Compare */ +#define AT91C_TC_WAVESEL_UPDOWN ( ( unsigned int ) 0x1 << 13 ) /* (TC) UPDOWN mode without automatic trigger on RC Compare */ +#define AT91C_TC_WAVESEL_UP_AUTO ( ( unsigned int ) 0x2 << 13 ) /* (TC) UP mode with automatic trigger on RC Compare */ +#define AT91C_TC_WAVESEL_UPDOWN_AUTO ( ( unsigned int ) 0x3 << 13 ) /* (TC) UPDOWN mode with automatic trigger on RC Compare */ +#define AT91C_TC_CPCTRG ( ( unsigned int ) 0x1 << 14 ) /* (TC) RC Compare Trigger Enable */ +#define AT91C_TC_WAVE ( ( unsigned int ) 0x1 << 15 ) /* (TC) */ +#define AT91C_TC_ACPA ( ( unsigned int ) 0x3 << 16 ) /* (TC) RA Compare Effect on TIOA */ +#define AT91C_TC_ACPA_NONE ( ( unsigned int ) 0x0 << 16 ) /* (TC) Effect: none */ +#define AT91C_TC_ACPA_SET ( ( unsigned int ) 0x1 << 16 ) /* (TC) Effect: set */ +#define AT91C_TC_ACPA_CLEAR ( ( unsigned int ) 0x2 << 16 ) /* (TC) Effect: clear */ +#define AT91C_TC_ACPA_TOGGLE ( ( unsigned int ) 0x3 << 16 ) /* (TC) Effect: toggle */ +#define AT91C_TC_LDRA ( ( unsigned int ) 0x3 << 16 ) /* (TC) RA Loading Selection */ +#define AT91C_TC_LDRA_NONE ( ( unsigned int ) 0x0 << 16 ) /* (TC) Edge: None */ +#define AT91C_TC_LDRA_RISING ( ( unsigned int ) 0x1 << 16 ) /* (TC) Edge: rising edge of TIOA */ +#define AT91C_TC_LDRA_FALLING ( ( unsigned int ) 0x2 << 16 ) /* (TC) Edge: falling edge of TIOA */ +#define AT91C_TC_LDRA_BOTH ( ( unsigned int ) 0x3 << 16 ) /* (TC) Edge: each edge of TIOA */ +#define AT91C_TC_ACPC ( ( unsigned int ) 0x3 << 18 ) /* (TC) RC Compare Effect on TIOA */ +#define AT91C_TC_ACPC_NONE ( ( unsigned int ) 0x0 << 18 ) /* (TC) Effect: none */ +#define AT91C_TC_ACPC_SET ( ( unsigned int ) 0x1 << 18 ) /* (TC) Effect: set */ +#define AT91C_TC_ACPC_CLEAR ( ( unsigned int ) 0x2 << 18 ) /* (TC) Effect: clear */ +#define AT91C_TC_ACPC_TOGGLE ( ( unsigned int ) 0x3 << 18 ) /* (TC) Effect: toggle */ +#define AT91C_TC_LDRB ( ( unsigned int ) 0x3 << 18 ) /* (TC) RB Loading Selection */ +#define AT91C_TC_LDRB_NONE ( ( unsigned int ) 0x0 << 18 ) /* (TC) Edge: None */ +#define AT91C_TC_LDRB_RISING ( ( unsigned int ) 0x1 << 18 ) /* (TC) Edge: rising edge of TIOA */ +#define AT91C_TC_LDRB_FALLING ( ( unsigned int ) 0x2 << 18 ) /* (TC) Edge: falling edge of TIOA */ +#define AT91C_TC_LDRB_BOTH ( ( unsigned int ) 0x3 << 18 ) /* (TC) Edge: each edge of TIOA */ +#define AT91C_TC_AEEVT ( ( unsigned int ) 0x3 << 20 ) /* (TC) External Event Effect on TIOA */ +#define AT91C_TC_AEEVT_NONE ( ( unsigned int ) 0x0 << 20 ) /* (TC) Effect: none */ +#define AT91C_TC_AEEVT_SET ( ( unsigned int ) 0x1 << 20 ) /* (TC) Effect: set */ +#define AT91C_TC_AEEVT_CLEAR ( ( unsigned int ) 0x2 << 20 ) /* (TC) Effect: clear */ +#define AT91C_TC_AEEVT_TOGGLE ( ( unsigned int ) 0x3 << 20 ) /* (TC) Effect: toggle */ +#define AT91C_TC_ASWTRG ( ( unsigned int ) 0x3 << 22 ) /* (TC) Software Trigger Effect on TIOA */ +#define AT91C_TC_ASWTRG_NONE ( ( unsigned int ) 0x0 << 22 ) /* (TC) Effect: none */ +#define AT91C_TC_ASWTRG_SET ( ( unsigned int ) 0x1 << 22 ) /* (TC) Effect: set */ +#define AT91C_TC_ASWTRG_CLEAR ( ( unsigned int ) 0x2 << 22 ) /* (TC) Effect: clear */ +#define AT91C_TC_ASWTRG_TOGGLE ( ( unsigned int ) 0x3 << 22 ) /* (TC) Effect: toggle */ +#define AT91C_TC_BCPB ( ( unsigned int ) 0x3 << 24 ) /* (TC) RB Compare Effect on TIOB */ +#define AT91C_TC_BCPB_NONE ( ( unsigned int ) 0x0 << 24 ) /* (TC) Effect: none */ +#define AT91C_TC_BCPB_SET ( ( unsigned int ) 0x1 << 24 ) /* (TC) Effect: set */ +#define AT91C_TC_BCPB_CLEAR ( ( unsigned int ) 0x2 << 24 ) /* (TC) Effect: clear */ +#define AT91C_TC_BCPB_TOGGLE ( ( unsigned int ) 0x3 << 24 ) /* (TC) Effect: toggle */ +#define AT91C_TC_BCPC ( ( unsigned int ) 0x3 << 26 ) /* (TC) RC Compare Effect on TIOB */ +#define AT91C_TC_BCPC_NONE ( ( unsigned int ) 0x0 << 26 ) /* (TC) Effect: none */ +#define AT91C_TC_BCPC_SET ( ( unsigned int ) 0x1 << 26 ) /* (TC) Effect: set */ +#define AT91C_TC_BCPC_CLEAR ( ( unsigned int ) 0x2 << 26 ) /* (TC) Effect: clear */ +#define AT91C_TC_BCPC_TOGGLE ( ( unsigned int ) 0x3 << 26 ) /* (TC) Effect: toggle */ +#define AT91C_TC_BEEVT ( ( unsigned int ) 0x3 << 28 ) /* (TC) External Event Effect on TIOB */ +#define AT91C_TC_BEEVT_NONE ( ( unsigned int ) 0x0 << 28 ) /* (TC) Effect: none */ +#define AT91C_TC_BEEVT_SET ( ( unsigned int ) 0x1 << 28 ) /* (TC) Effect: set */ +#define AT91C_TC_BEEVT_CLEAR ( ( unsigned int ) 0x2 << 28 ) /* (TC) Effect: clear */ +#define AT91C_TC_BEEVT_TOGGLE ( ( unsigned int ) 0x3 << 28 ) /* (TC) Effect: toggle */ +#define AT91C_TC_BSWTRG ( ( unsigned int ) 0x3 << 30 ) /* (TC) Software Trigger Effect on TIOB */ +#define AT91C_TC_BSWTRG_NONE ( ( unsigned int ) 0x0 << 30 ) /* (TC) Effect: none */ +#define AT91C_TC_BSWTRG_SET ( ( unsigned int ) 0x1 << 30 ) /* (TC) Effect: set */ +#define AT91C_TC_BSWTRG_CLEAR ( ( unsigned int ) 0x2 << 30 ) /* (TC) Effect: clear */ +#define AT91C_TC_BSWTRG_TOGGLE ( ( unsigned int ) 0x3 << 30 ) /* (TC) Effect: toggle */ +/* -------- TC_SR : (TC Offset: 0x20) TC Channel Status Register -------- */ +#define AT91C_TC_COVFS ( ( unsigned int ) 0x1 << 0 ) /* (TC) Counter Overflow */ +#define AT91C_TC_LOVRS ( ( unsigned int ) 0x1 << 1 ) /* (TC) Load Overrun */ +#define AT91C_TC_CPAS ( ( unsigned int ) 0x1 << 2 ) /* (TC) RA Compare */ +#define AT91C_TC_CPBS ( ( unsigned int ) 0x1 << 3 ) /* (TC) RB Compare */ +#define AT91C_TC_CPCS ( ( unsigned int ) 0x1 << 4 ) /* (TC) RC Compare */ +#define AT91C_TC_LDRAS ( ( unsigned int ) 0x1 << 5 ) /* (TC) RA Loading */ +#define AT91C_TC_LDRBS ( ( unsigned int ) 0x1 << 6 ) /* (TC) RB Loading */ +#define AT91C_TC_ETRGS ( ( unsigned int ) 0x1 << 7 ) /* (TC) External Trigger */ +#define AT91C_TC_CLKSTA ( ( unsigned int ) 0x1 << 16 ) /* (TC) Clock Enabling */ +#define AT91C_TC_MTIOA ( ( unsigned int ) 0x1 << 17 ) /* (TC) TIOA Mirror */ +#define AT91C_TC_MTIOB ( ( unsigned int ) 0x1 << 18 ) /* (TC) TIOA Mirror */ +/* -------- TC_IER : (TC Offset: 0x24) TC Channel Interrupt Enable Register -------- */ +/* -------- TC_IDR : (TC Offset: 0x28) TC Channel Interrupt Disable Register -------- */ +/* -------- TC_IMR : (TC Offset: 0x2c) TC Channel Interrupt Mask Register -------- */ + +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR Timer Counter Interface */ +/* ***************************************************************************** */ +typedef struct _AT91S_TCB +{ + AT91S_TC TCB_TC0; /* TC Channel 0 */ + AT91_REG Reserved0[ 4 ]; /* */ + AT91S_TC TCB_TC1; /* TC Channel 1 */ + AT91_REG Reserved1[ 4 ]; /* */ + AT91S_TC TCB_TC2; /* TC Channel 2 */ + AT91_REG Reserved2[ 4 ]; /* */ + AT91_REG TCB_BCR; /* TC Block Control Register */ + AT91_REG TCB_BMR; /* TC Block Mode Register */ +} AT91S_TCB, * AT91PS_TCB; + +/* -------- TCB_BCR : (TCB Offset: 0xc0) TC Block Control Register -------- */ +#define AT91C_TCB_SYNC ( ( unsigned int ) 0x1 << 0 ) /* (TCB) Synchro Command */ +/* -------- TCB_BMR : (TCB Offset: 0xc4) TC Block Mode Register -------- */ +#define AT91C_TCB_TC0XC0S ( ( unsigned int ) 0x3 << 0 ) /* (TCB) External Clock Signal 0 Selection */ +#define AT91C_TCB_TC0XC0S_TCLK0 ( ( unsigned int ) 0x0 ) /* (TCB) TCLK0 connected to XC0 */ +#define AT91C_TCB_TC0XC0S_NONE ( ( unsigned int ) 0x1 ) /* (TCB) None signal connected to XC0 */ +#define AT91C_TCB_TC0XC0S_TIOA1 ( ( unsigned int ) 0x2 ) /* (TCB) TIOA1 connected to XC0 */ +#define AT91C_TCB_TC0XC0S_TIOA2 ( ( unsigned int ) 0x3 ) /* (TCB) TIOA2 connected to XC0 */ +#define AT91C_TCB_TC1XC1S ( ( unsigned int ) 0x3 << 2 ) /* (TCB) External Clock Signal 1 Selection */ +#define AT91C_TCB_TC1XC1S_TCLK1 ( ( unsigned int ) 0x0 << 2 ) /* (TCB) TCLK1 connected to XC1 */ +#define AT91C_TCB_TC1XC1S_NONE ( ( unsigned int ) 0x1 << 2 ) /* (TCB) None signal connected to XC1 */ +#define AT91C_TCB_TC1XC1S_TIOA0 ( ( unsigned int ) 0x2 << 2 ) /* (TCB) TIOA0 connected to XC1 */ +#define AT91C_TCB_TC1XC1S_TIOA2 ( ( unsigned int ) 0x3 << 2 ) /* (TCB) TIOA2 connected to XC1 */ +#define AT91C_TCB_TC2XC2S ( ( unsigned int ) 0x3 << 4 ) /* (TCB) External Clock Signal 2 Selection */ +#define AT91C_TCB_TC2XC2S_TCLK2 ( ( unsigned int ) 0x0 << 4 ) /* (TCB) TCLK2 connected to XC2 */ +#define AT91C_TCB_TC2XC2S_NONE ( ( unsigned int ) 0x1 << 4 ) /* (TCB) None signal connected to XC2 */ +#define AT91C_TCB_TC2XC2S_TIOA0 ( ( unsigned int ) 0x2 << 4 ) /* (TCB) TIOA0 connected to XC2 */ +#define AT91C_TCB_TC2XC2S_TIOA1 ( ( unsigned int ) 0x3 << 4 ) /* (TCB) TIOA2 connected to XC2 */ + +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR Control Area Network MailBox Interface */ +/* ***************************************************************************** */ +typedef struct _AT91S_CAN_MB +{ + AT91_REG CAN_MB_MMR; /* MailBox Mode Register */ + AT91_REG CAN_MB_MAM; /* MailBox Acceptance Mask Register */ + AT91_REG CAN_MB_MID; /* MailBox ID Register */ + AT91_REG CAN_MB_MFID; /* MailBox Family ID Register */ + AT91_REG CAN_MB_MSR; /* MailBox Status Register */ + AT91_REG CAN_MB_MDL; /* MailBox Data Low Register */ + AT91_REG CAN_MB_MDH; /* MailBox Data High Register */ + AT91_REG CAN_MB_MCR; /* MailBox Control Register */ +} AT91S_CAN_MB, * AT91PS_CAN_MB; + +/* -------- CAN_MMR : (CAN_MB Offset: 0x0) CAN Message Mode Register -------- */ +#define AT91C_CAN_MTIMEMARK ( ( unsigned int ) 0xFFFF << 0 ) /* (CAN_MB) Mailbox Timemark */ +#define AT91C_CAN_PRIOR ( ( unsigned int ) 0xF << 16 ) /* (CAN_MB) Mailbox Priority */ +#define AT91C_CAN_MOT ( ( unsigned int ) 0x7 << 24 ) /* (CAN_MB) Mailbox Object Type */ +#define AT91C_CAN_MOT_DIS ( ( unsigned int ) 0x0 << 24 ) /* (CAN_MB) */ +#define AT91C_CAN_MOT_RX ( ( unsigned int ) 0x1 << 24 ) /* (CAN_MB) */ +#define AT91C_CAN_MOT_RXOVERWRITE ( ( unsigned int ) 0x2 << 24 ) /* (CAN_MB) */ +#define AT91C_CAN_MOT_TX ( ( unsigned int ) 0x3 << 24 ) /* (CAN_MB) */ +#define AT91C_CAN_MOT_CONSUMER ( ( unsigned int ) 0x4 << 24 ) /* (CAN_MB) */ +#define AT91C_CAN_MOT_PRODUCER ( ( unsigned int ) 0x5 << 24 ) /* (CAN_MB) */ +/* -------- CAN_MAM : (CAN_MB Offset: 0x4) CAN Message Acceptance Mask Register -------- */ +#define AT91C_CAN_MIDvB ( ( unsigned int ) 0x3FFFF << 0 ) /* (CAN_MB) Complementary bits for identifier in extended mode */ +#define AT91C_CAN_MIDvA ( ( unsigned int ) 0x7FF << 18 ) /* (CAN_MB) Identifier for standard frame mode */ +#define AT91C_CAN_MIDE ( ( unsigned int ) 0x1 << 29 ) /* (CAN_MB) Identifier Version */ +/* -------- CAN_MID : (CAN_MB Offset: 0x8) CAN Message ID Register -------- */ +/* -------- CAN_MFID : (CAN_MB Offset: 0xc) CAN Message Family ID Register -------- */ +/* -------- CAN_MSR : (CAN_MB Offset: 0x10) CAN Message Status Register -------- */ +#define AT91C_CAN_MTIMESTAMP ( ( unsigned int ) 0xFFFF << 0 ) /* (CAN_MB) Timer Value */ +#define AT91C_CAN_MDLC ( ( unsigned int ) 0xF << 16 ) /* (CAN_MB) Mailbox Data Length Code */ +#define AT91C_CAN_MRTR ( ( unsigned int ) 0x1 << 20 ) /* (CAN_MB) Mailbox Remote Transmission Request */ +#define AT91C_CAN_MABT ( ( unsigned int ) 0x1 << 22 ) /* (CAN_MB) Mailbox Message Abort */ +#define AT91C_CAN_MRDY ( ( unsigned int ) 0x1 << 23 ) /* (CAN_MB) Mailbox Ready */ +#define AT91C_CAN_MMI ( ( unsigned int ) 0x1 << 24 ) /* (CAN_MB) Mailbox Message Ignored */ +/* -------- CAN_MDL : (CAN_MB Offset: 0x14) CAN Message Data Low Register -------- */ +/* -------- CAN_MDH : (CAN_MB Offset: 0x18) CAN Message Data High Register -------- */ +/* -------- CAN_MCR : (CAN_MB Offset: 0x1c) CAN Message Control Register -------- */ +#define AT91C_CAN_MACR ( ( unsigned int ) 0x1 << 22 ) /* (CAN_MB) Abort Request for Mailbox */ +#define AT91C_CAN_MTCR ( ( unsigned int ) 0x1 << 23 ) /* (CAN_MB) Mailbox Transfer Command */ + +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR Control Area Network Interface */ +/* ***************************************************************************** */ +typedef struct _AT91S_CAN +{ + AT91_REG CAN_MR; /* Mode Register */ + AT91_REG CAN_IER; /* Interrupt Enable Register */ + AT91_REG CAN_IDR; /* Interrupt Disable Register */ + AT91_REG CAN_IMR; /* Interrupt Mask Register */ + AT91_REG CAN_SR; /* Status Register */ + AT91_REG CAN_BR; /* Baudrate Register */ + AT91_REG CAN_TIM; /* Timer Register */ + AT91_REG CAN_TIMESTP; /* Time Stamp Register */ + AT91_REG CAN_ECR; /* Error Counter Register */ + AT91_REG CAN_TCR; /* Transfer Command Register */ + AT91_REG CAN_ACR; /* Abort Command Register */ + AT91_REG Reserved0[ 52 ]; /* */ + AT91_REG CAN_VR; /* Version Register */ + AT91_REG Reserved1[ 64 ]; /* */ + AT91S_CAN_MB CAN_MB0; /* CAN Mailbox 0 */ + AT91S_CAN_MB CAN_MB1; /* CAN Mailbox 1 */ + AT91S_CAN_MB CAN_MB2; /* CAN Mailbox 2 */ + AT91S_CAN_MB CAN_MB3; /* CAN Mailbox 3 */ + AT91S_CAN_MB CAN_MB4; /* CAN Mailbox 4 */ + AT91S_CAN_MB CAN_MB5; /* CAN Mailbox 5 */ + AT91S_CAN_MB CAN_MB6; /* CAN Mailbox 6 */ + AT91S_CAN_MB CAN_MB7; /* CAN Mailbox 7 */ + AT91S_CAN_MB CAN_MB8; /* CAN Mailbox 8 */ + AT91S_CAN_MB CAN_MB9; /* CAN Mailbox 9 */ + AT91S_CAN_MB CAN_MB10; /* CAN Mailbox 10 */ + AT91S_CAN_MB CAN_MB11; /* CAN Mailbox 11 */ + AT91S_CAN_MB CAN_MB12; /* CAN Mailbox 12 */ + AT91S_CAN_MB CAN_MB13; /* CAN Mailbox 13 */ + AT91S_CAN_MB CAN_MB14; /* CAN Mailbox 14 */ + AT91S_CAN_MB CAN_MB15; /* CAN Mailbox 15 */ +} AT91S_CAN, * AT91PS_CAN; + +/* -------- CAN_MR : (CAN Offset: 0x0) CAN Mode Register -------- */ +#define AT91C_CAN_CANEN ( ( unsigned int ) 0x1 << 0 ) /* (CAN) CAN Controller Enable */ +#define AT91C_CAN_LPM ( ( unsigned int ) 0x1 << 1 ) /* (CAN) Disable/Enable Low Power Mode */ +#define AT91C_CAN_ABM ( ( unsigned int ) 0x1 << 2 ) /* (CAN) Disable/Enable Autobaud/Listen Mode */ +#define AT91C_CAN_OVL ( ( unsigned int ) 0x1 << 3 ) /* (CAN) Disable/Enable Overload Frame */ +#define AT91C_CAN_TEOF ( ( unsigned int ) 0x1 << 4 ) /* (CAN) Time Stamp messages at each end of Frame */ +#define AT91C_CAN_TTM ( ( unsigned int ) 0x1 << 5 ) /* (CAN) Disable/Enable Time Trigger Mode */ +#define AT91C_CAN_TIMFRZ ( ( unsigned int ) 0x1 << 6 ) /* (CAN) Enable Timer Freeze */ +#define AT91C_CAN_DRPT ( ( unsigned int ) 0x1 << 7 ) /* (CAN) Disable Repeat */ +/* -------- CAN_IER : (CAN Offset: 0x4) CAN Interrupt Enable Register -------- */ +#define AT91C_CAN_MB0 ( ( unsigned int ) 0x1 << 0 ) /* (CAN) Mailbox 0 Flag */ +#define AT91C_CAN_MB1 ( ( unsigned int ) 0x1 << 1 ) /* (CAN) Mailbox 1 Flag */ +#define AT91C_CAN_MB2 ( ( unsigned int ) 0x1 << 2 ) /* (CAN) Mailbox 2 Flag */ +#define AT91C_CAN_MB3 ( ( unsigned int ) 0x1 << 3 ) /* (CAN) Mailbox 3 Flag */ +#define AT91C_CAN_MB4 ( ( unsigned int ) 0x1 << 4 ) /* (CAN) Mailbox 4 Flag */ +#define AT91C_CAN_MB5 ( ( unsigned int ) 0x1 << 5 ) /* (CAN) Mailbox 5 Flag */ +#define AT91C_CAN_MB6 ( ( unsigned int ) 0x1 << 6 ) /* (CAN) Mailbox 6 Flag */ +#define AT91C_CAN_MB7 ( ( unsigned int ) 0x1 << 7 ) /* (CAN) Mailbox 7 Flag */ +#define AT91C_CAN_MB8 ( ( unsigned int ) 0x1 << 8 ) /* (CAN) Mailbox 8 Flag */ +#define AT91C_CAN_MB9 ( ( unsigned int ) 0x1 << 9 ) /* (CAN) Mailbox 9 Flag */ +#define AT91C_CAN_MB10 ( ( unsigned int ) 0x1 << 10 ) /* (CAN) Mailbox 10 Flag */ +#define AT91C_CAN_MB11 ( ( unsigned int ) 0x1 << 11 ) /* (CAN) Mailbox 11 Flag */ +#define AT91C_CAN_MB12 ( ( unsigned int ) 0x1 << 12 ) /* (CAN) Mailbox 12 Flag */ +#define AT91C_CAN_MB13 ( ( unsigned int ) 0x1 << 13 ) /* (CAN) Mailbox 13 Flag */ +#define AT91C_CAN_MB14 ( ( unsigned int ) 0x1 << 14 ) /* (CAN) Mailbox 14 Flag */ +#define AT91C_CAN_MB15 ( ( unsigned int ) 0x1 << 15 ) /* (CAN) Mailbox 15 Flag */ +#define AT91C_CAN_ERRA ( ( unsigned int ) 0x1 << 16 ) /* (CAN) Error Active Mode Flag */ +#define AT91C_CAN_WARN ( ( unsigned int ) 0x1 << 17 ) /* (CAN) Warning Limit Flag */ +#define AT91C_CAN_ERRP ( ( unsigned int ) 0x1 << 18 ) /* (CAN) Error Passive Mode Flag */ +#define AT91C_CAN_BOFF ( ( unsigned int ) 0x1 << 19 ) /* (CAN) Bus Off Mode Flag */ +#define AT91C_CAN_SLEEP ( ( unsigned int ) 0x1 << 20 ) /* (CAN) Sleep Flag */ +#define AT91C_CAN_WAKEUP ( ( unsigned int ) 0x1 << 21 ) /* (CAN) Wakeup Flag */ +#define AT91C_CAN_TOVF ( ( unsigned int ) 0x1 << 22 ) /* (CAN) Timer Overflow Flag */ +#define AT91C_CAN_TSTP ( ( unsigned int ) 0x1 << 23 ) /* (CAN) Timestamp Flag */ +#define AT91C_CAN_CERR ( ( unsigned int ) 0x1 << 24 ) /* (CAN) CRC Error */ +#define AT91C_CAN_SERR ( ( unsigned int ) 0x1 << 25 ) /* (CAN) Stuffing Error */ +#define AT91C_CAN_AERR ( ( unsigned int ) 0x1 << 26 ) /* (CAN) Acknowledgment Error */ +#define AT91C_CAN_FERR ( ( unsigned int ) 0x1 << 27 ) /* (CAN) Form Error */ +#define AT91C_CAN_BERR ( ( unsigned int ) 0x1 << 28 ) /* (CAN) Bit Error */ +/* -------- CAN_IDR : (CAN Offset: 0x8) CAN Interrupt Disable Register -------- */ +/* -------- CAN_IMR : (CAN Offset: 0xc) CAN Interrupt Mask Register -------- */ +/* -------- CAN_SR : (CAN Offset: 0x10) CAN Status Register -------- */ +#define AT91C_CAN_RBSY ( ( unsigned int ) 0x1 << 29 ) /* (CAN) Receiver Busy */ +#define AT91C_CAN_TBSY ( ( unsigned int ) 0x1 << 30 ) /* (CAN) Transmitter Busy */ +#define AT91C_CAN_OVLY ( ( unsigned int ) 0x1 << 31 ) /* (CAN) Overload Busy */ +/* -------- CAN_BR : (CAN Offset: 0x14) CAN Baudrate Register -------- */ +#define AT91C_CAN_PHASE2 ( ( unsigned int ) 0x7 << 0 ) /* (CAN) Phase 2 segment */ +#define AT91C_CAN_PHASE1 ( ( unsigned int ) 0x7 << 4 ) /* (CAN) Phase 1 segment */ +#define AT91C_CAN_PROPAG ( ( unsigned int ) 0x7 << 8 ) /* (CAN) Programmation time segment */ +#define AT91C_CAN_SYNC ( ( unsigned int ) 0x3 << 12 ) /* (CAN) Re-synchronization jump width segment */ +#define AT91C_CAN_BRP ( ( unsigned int ) 0x7F << 16 ) /* (CAN) Baudrate Prescaler */ +#define AT91C_CAN_SMP ( ( unsigned int ) 0x1 << 24 ) /* (CAN) Sampling mode */ +/* -------- CAN_TIM : (CAN Offset: 0x18) CAN Timer Register -------- */ +#define AT91C_CAN_TIMER ( ( unsigned int ) 0xFFFF << 0 ) /* (CAN) Timer field */ +/* -------- CAN_TIMESTP : (CAN Offset: 0x1c) CAN Timestamp Register -------- */ +/* -------- CAN_ECR : (CAN Offset: 0x20) CAN Error Counter Register -------- */ +#define AT91C_CAN_REC ( ( unsigned int ) 0xFF << 0 ) /* (CAN) Receive Error Counter */ +#define AT91C_CAN_TEC ( ( unsigned int ) 0xFF << 16 ) /* (CAN) Transmit Error Counter */ +/* -------- CAN_TCR : (CAN Offset: 0x24) CAN Transfer Command Register -------- */ +#define AT91C_CAN_TIMRST ( ( unsigned int ) 0x1 << 31 ) /* (CAN) Timer Reset Field */ +/* -------- CAN_ACR : (CAN Offset: 0x28) CAN Abort Command Register -------- */ + +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR Ethernet MAC 10/100 */ +/* ***************************************************************************** */ +typedef struct _AT91S_EMAC +{ + AT91_REG EMAC_NCR; /* Network Control Register */ + AT91_REG EMAC_NCFGR; /* Network Configuration Register */ + AT91_REG EMAC_NSR; /* Network Status Register */ + AT91_REG Reserved0[ 2 ]; /* */ + AT91_REG EMAC_TSR; /* Transmit Status Register */ + AT91_REG EMAC_RBQP; /* Receive Buffer Queue Pointer */ + AT91_REG EMAC_TBQP; /* Transmit Buffer Queue Pointer */ + AT91_REG EMAC_RSR; /* Receive Status Register */ + AT91_REG EMAC_ISR; /* Interrupt Status Register */ + AT91_REG EMAC_IER; /* Interrupt Enable Register */ + AT91_REG EMAC_IDR; /* Interrupt Disable Register */ + AT91_REG EMAC_IMR; /* Interrupt Mask Register */ + AT91_REG EMAC_MAN; /* PHY Maintenance Register */ + AT91_REG EMAC_PTR; /* Pause Time Register */ + AT91_REG EMAC_PFR; /* Pause Frames received Register */ + AT91_REG EMAC_FTO; /* Frames Transmitted OK Register */ + AT91_REG EMAC_SCF; /* Single Collision Frame Register */ + AT91_REG EMAC_MCF; /* Multiple Collision Frame Register */ + AT91_REG EMAC_FRO; /* Frames Received OK Register */ + AT91_REG EMAC_FCSE; /* Frame Check Sequence Error Register */ + AT91_REG EMAC_ALE; /* Alignment Error Register */ + AT91_REG EMAC_DTF; /* Deferred Transmission Frame Register */ + AT91_REG EMAC_LCOL; /* Late Collision Register */ + AT91_REG EMAC_ECOL; /* Excessive Collision Register */ + AT91_REG EMAC_TUND; /* Transmit Underrun Error Register */ + AT91_REG EMAC_CSE; /* Carrier Sense Error Register */ + AT91_REG EMAC_RRE; /* Receive Ressource Error Register */ + AT91_REG EMAC_ROV; /* Receive Overrun Errors Register */ + AT91_REG EMAC_RSE; /* Receive Symbol Errors Register */ + AT91_REG EMAC_ELE; /* Excessive Length Errors Register */ + AT91_REG EMAC_RJA; /* Receive Jabbers Register */ + AT91_REG EMAC_USF; /* Undersize Frames Register */ + AT91_REG EMAC_STE; /* SQE Test Error Register */ + AT91_REG EMAC_RLE; /* Receive Length Field Mismatch Register */ + AT91_REG EMAC_TPF; /* Transmitted Pause Frames Register */ + AT91_REG EMAC_HRB; /* Hash Address Bottom[31:0] */ + AT91_REG EMAC_HRT; /* Hash Address Top[63:32] */ + AT91_REG EMAC_SA1L; /* Specific Address 1 Bottom, First 4 bytes */ + AT91_REG EMAC_SA1H; /* Specific Address 1 Top, Last 2 bytes */ + AT91_REG EMAC_SA2L; /* Specific Address 2 Bottom, First 4 bytes */ + AT91_REG EMAC_SA2H; /* Specific Address 2 Top, Last 2 bytes */ + AT91_REG EMAC_SA3L; /* Specific Address 3 Bottom, First 4 bytes */ + AT91_REG EMAC_SA3H; /* Specific Address 3 Top, Last 2 bytes */ + AT91_REG EMAC_SA4L; /* Specific Address 4 Bottom, First 4 bytes */ + AT91_REG EMAC_SA4H; /* Specific Address 4 Top, Last 2 bytes */ + AT91_REG EMAC_TID; /* Type ID Checking Register */ + AT91_REG EMAC_TPQ; /* Transmit Pause Quantum Register */ + AT91_REG EMAC_USRIO; /* USER Input/Output Register */ + AT91_REG EMAC_WOL; /* Wake On LAN Register */ + AT91_REG Reserved1[ 13 ]; /* */ + AT91_REG EMAC_REV; /* Revision Register */ +} AT91S_EMAC, * AT91PS_EMAC; + +/* -------- EMAC_NCR : (EMAC Offset: 0x0) -------- */ +#define AT91C_EMAC_LB ( ( unsigned int ) 0x1 << 0 ) /* (EMAC) Loopback. Optional. When set, loopback signal is at high level. */ +#define AT91C_EMAC_LLB ( ( unsigned int ) 0x1 << 1 ) /* (EMAC) Loopback local. */ +#define AT91C_EMAC_RE ( ( unsigned int ) 0x1 << 2 ) /* (EMAC) Receive enable. */ +#define AT91C_EMAC_TE ( ( unsigned int ) 0x1 << 3 ) /* (EMAC) Transmit enable. */ +#define AT91C_EMAC_MPE ( ( unsigned int ) 0x1 << 4 ) /* (EMAC) Management port enable. */ +#define AT91C_EMAC_CLRSTAT ( ( unsigned int ) 0x1 << 5 ) /* (EMAC) Clear statistics registers. */ +#define AT91C_EMAC_INCSTAT ( ( unsigned int ) 0x1 << 6 ) /* (EMAC) Increment statistics registers. */ +#define AT91C_EMAC_WESTAT ( ( unsigned int ) 0x1 << 7 ) /* (EMAC) Write enable for statistics registers. */ +#define AT91C_EMAC_BP ( ( unsigned int ) 0x1 << 8 ) /* (EMAC) Back pressure. */ +#define AT91C_EMAC_TSTART ( ( unsigned int ) 0x1 << 9 ) /* (EMAC) Start Transmission. */ +#define AT91C_EMAC_THALT ( ( unsigned int ) 0x1 << 10 ) /* (EMAC) Transmission Halt. */ +#define AT91C_EMAC_TPFR ( ( unsigned int ) 0x1 << 11 ) /* (EMAC) Transmit pause frame */ +#define AT91C_EMAC_TZQ ( ( unsigned int ) 0x1 << 12 ) /* (EMAC) Transmit zero quantum pause frame */ +/* -------- EMAC_NCFGR : (EMAC Offset: 0x4) Network Configuration Register -------- */ +#define AT91C_EMAC_SPD ( ( unsigned int ) 0x1 << 0 ) /* (EMAC) Speed. */ +#define AT91C_EMAC_FD ( ( unsigned int ) 0x1 << 1 ) /* (EMAC) Full duplex. */ +#define AT91C_EMAC_JFRAME ( ( unsigned int ) 0x1 << 3 ) /* (EMAC) Jumbo Frames. */ +#define AT91C_EMAC_CAF ( ( unsigned int ) 0x1 << 4 ) /* (EMAC) Copy all frames. */ +#define AT91C_EMAC_NBC ( ( unsigned int ) 0x1 << 5 ) /* (EMAC) No broadcast. */ +#define AT91C_EMAC_MTI ( ( unsigned int ) 0x1 << 6 ) /* (EMAC) Multicast hash event enable */ +#define AT91C_EMAC_UNI ( ( unsigned int ) 0x1 << 7 ) /* (EMAC) Unicast hash enable. */ +#define AT91C_EMAC_BIG ( ( unsigned int ) 0x1 << 8 ) /* (EMAC) Receive 1522 bytes. */ +#define AT91C_EMAC_EAE ( ( unsigned int ) 0x1 << 9 ) /* (EMAC) External address match enable. */ +#define AT91C_EMAC_CLK ( ( unsigned int ) 0x3 << 10 ) /* (EMAC) */ +#define AT91C_EMAC_CLK_HCLK_8 ( ( unsigned int ) 0x0 << 10 ) /* (EMAC) HCLK divided by 8 */ +#define AT91C_EMAC_CLK_HCLK_16 ( ( unsigned int ) 0x1 << 10 ) /* (EMAC) HCLK divided by 16 */ +#define AT91C_EMAC_CLK_HCLK_32 ( ( unsigned int ) 0x2 << 10 ) /* (EMAC) HCLK divided by 32 */ +#define AT91C_EMAC_CLK_HCLK_64 ( ( unsigned int ) 0x3 << 10 ) /* (EMAC) HCLK divided by 64 */ +#define AT91C_EMAC_RTY ( ( unsigned int ) 0x1 << 12 ) /* (EMAC) */ +#define AT91C_EMAC_PAE ( ( unsigned int ) 0x1 << 13 ) /* (EMAC) */ +#define AT91C_EMAC_RBOF ( ( unsigned int ) 0x3 << 14 ) /* (EMAC) */ +#define AT91C_EMAC_RBOF_OFFSET_0 ( ( unsigned int ) 0x0 << 14 ) /* (EMAC) no offset from start of receive buffer */ +#define AT91C_EMAC_RBOF_OFFSET_1 ( ( unsigned int ) 0x1 << 14 ) /* (EMAC) one byte offset from start of receive buffer */ +#define AT91C_EMAC_RBOF_OFFSET_2 ( ( unsigned int ) 0x2 << 14 ) /* (EMAC) two bytes offset from start of receive buffer */ +#define AT91C_EMAC_RBOF_OFFSET_3 ( ( unsigned int ) 0x3 << 14 ) /* (EMAC) three bytes offset from start of receive buffer */ +#define AT91C_EMAC_RLCE ( ( unsigned int ) 0x1 << 16 ) /* (EMAC) Receive Length field Checking Enable */ +#define AT91C_EMAC_DRFCS ( ( unsigned int ) 0x1 << 17 ) /* (EMAC) Discard Receive FCS */ +#define AT91C_EMAC_EFRHD ( ( unsigned int ) 0x1 << 18 ) /* (EMAC) */ +#define AT91C_EMAC_IRXFCS ( ( unsigned int ) 0x1 << 19 ) /* (EMAC) Ignore RX FCS */ +/* -------- EMAC_NSR : (EMAC Offset: 0x8) Network Status Register -------- */ +#define AT91C_EMAC_LINKR ( ( unsigned int ) 0x1 << 0 ) /* (EMAC) */ +#define AT91C_EMAC_MDIO ( ( unsigned int ) 0x1 << 1 ) /* (EMAC) */ +#define AT91C_EMAC_IDLE ( ( unsigned int ) 0x1 << 2 ) /* (EMAC) */ +/* -------- EMAC_TSR : (EMAC Offset: 0x14) Transmit Status Register -------- */ +#define AT91C_EMAC_UBR ( ( unsigned int ) 0x1 << 0 ) /* (EMAC) */ +#define AT91C_EMAC_COL ( ( unsigned int ) 0x1 << 1 ) /* (EMAC) */ +#define AT91C_EMAC_RLES ( ( unsigned int ) 0x1 << 2 ) /* (EMAC) */ +#define AT91C_EMAC_TGO ( ( unsigned int ) 0x1 << 3 ) /* (EMAC) Transmit Go */ +#define AT91C_EMAC_BEX ( ( unsigned int ) 0x1 << 4 ) /* (EMAC) Buffers exhausted mid frame */ +#define AT91C_EMAC_COMP ( ( unsigned int ) 0x1 << 5 ) /* (EMAC) */ +#define AT91C_EMAC_UND ( ( unsigned int ) 0x1 << 6 ) /* (EMAC) */ +/* -------- EMAC_RSR : (EMAC Offset: 0x20) Receive Status Register -------- */ +#define AT91C_EMAC_BNA ( ( unsigned int ) 0x1 << 0 ) /* (EMAC) */ +#define AT91C_EMAC_REC ( ( unsigned int ) 0x1 << 1 ) /* (EMAC) */ +#define AT91C_EMAC_OVR ( ( unsigned int ) 0x1 << 2 ) /* (EMAC) */ +/* -------- EMAC_ISR : (EMAC Offset: 0x24) Interrupt Status Register -------- */ +#define AT91C_EMAC_MFD ( ( unsigned int ) 0x1 << 0 ) /* (EMAC) */ +#define AT91C_EMAC_RCOMP ( ( unsigned int ) 0x1 << 1 ) /* (EMAC) */ +#define AT91C_EMAC_RXUBR ( ( unsigned int ) 0x1 << 2 ) /* (EMAC) */ +#define AT91C_EMAC_TXUBR ( ( unsigned int ) 0x1 << 3 ) /* (EMAC) */ +#define AT91C_EMAC_TUNDR ( ( unsigned int ) 0x1 << 4 ) /* (EMAC) */ +#define AT91C_EMAC_RLEX ( ( unsigned int ) 0x1 << 5 ) /* (EMAC) */ +#define AT91C_EMAC_TXERR ( ( unsigned int ) 0x1 << 6 ) /* (EMAC) */ +#define AT91C_EMAC_TCOMP ( ( unsigned int ) 0x1 << 7 ) /* (EMAC) */ +#define AT91C_EMAC_LINK ( ( unsigned int ) 0x1 << 9 ) /* (EMAC) */ +#define AT91C_EMAC_ROVR ( ( unsigned int ) 0x1 << 10 ) /* (EMAC) */ +#define AT91C_EMAC_HRESP ( ( unsigned int ) 0x1 << 11 ) /* (EMAC) */ +#define AT91C_EMAC_PFRE ( ( unsigned int ) 0x1 << 12 ) /* (EMAC) */ +#define AT91C_EMAC_PTZ ( ( unsigned int ) 0x1 << 13 ) /* (EMAC) */ +/* -------- EMAC_IER : (EMAC Offset: 0x28) Interrupt Enable Register -------- */ +/* -------- EMAC_IDR : (EMAC Offset: 0x2c) Interrupt Disable Register -------- */ +/* -------- EMAC_IMR : (EMAC Offset: 0x30) Interrupt Mask Register -------- */ +/* -------- EMAC_MAN : (EMAC Offset: 0x34) PHY Maintenance Register -------- */ +#define AT91C_EMAC_DATA ( ( unsigned int ) 0xFFFF << 0 ) /* (EMAC) */ +#define AT91C_EMAC_CODE ( ( unsigned int ) 0x3 << 16 ) /* (EMAC) */ +#define AT91C_EMAC_REGA ( ( unsigned int ) 0x1F << 18 ) /* (EMAC) */ +#define AT91C_EMAC_PHYA ( ( unsigned int ) 0x1F << 23 ) /* (EMAC) */ +#define AT91C_EMAC_RW ( ( unsigned int ) 0x3 << 28 ) /* (EMAC) */ +#define AT91C_EMAC_SOF ( ( unsigned int ) 0x3 << 30 ) /* (EMAC) */ +/* -------- EMAC_USRIO : (EMAC Offset: 0xc0) USER Input Output Register -------- */ +#define AT91C_EMAC_RMII ( ( unsigned int ) 0x1 << 0 ) /* (EMAC) Reduce MII */ +/* -------- EMAC_WOL : (EMAC Offset: 0xc4) Wake On LAN Register -------- */ +#define AT91C_EMAC_IP ( ( unsigned int ) 0xFFFF << 0 ) /* (EMAC) ARP request IP address */ +#define AT91C_EMAC_MAG ( ( unsigned int ) 0x1 << 16 ) /* (EMAC) Magic packet event enable */ +#define AT91C_EMAC_ARP ( ( unsigned int ) 0x1 << 17 ) /* (EMAC) ARP request event enable */ +#define AT91C_EMAC_SA1 ( ( unsigned int ) 0x1 << 18 ) /* (EMAC) Specific address register 1 event enable */ +/* -------- EMAC_REV : (EMAC Offset: 0xfc) Revision Register -------- */ +#define AT91C_EMAC_REVREF ( ( unsigned int ) 0xFFFF << 0 ) /* (EMAC) */ +#define AT91C_EMAC_PARTREF ( ( unsigned int ) 0xFFFF << 16 ) /* (EMAC) */ + +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR Analog to Digital Convertor */ +/* ***************************************************************************** */ +typedef struct _AT91S_ADC +{ + AT91_REG ADC_CR; /* ADC Control Register */ + AT91_REG ADC_MR; /* ADC Mode Register */ + AT91_REG Reserved0[ 2 ]; /* */ + AT91_REG ADC_CHER; /* ADC Channel Enable Register */ + AT91_REG ADC_CHDR; /* ADC Channel Disable Register */ + AT91_REG ADC_CHSR; /* ADC Channel Status Register */ + AT91_REG ADC_SR; /* ADC Status Register */ + AT91_REG ADC_LCDR; /* ADC Last Converted Data Register */ + AT91_REG ADC_IER; /* ADC Interrupt Enable Register */ + AT91_REG ADC_IDR; /* ADC Interrupt Disable Register */ + AT91_REG ADC_IMR; /* ADC Interrupt Mask Register */ + AT91_REG ADC_CDR0; /* ADC Channel Data Register 0 */ + AT91_REG ADC_CDR1; /* ADC Channel Data Register 1 */ + AT91_REG ADC_CDR2; /* ADC Channel Data Register 2 */ + AT91_REG ADC_CDR3; /* ADC Channel Data Register 3 */ + AT91_REG ADC_CDR4; /* ADC Channel Data Register 4 */ + AT91_REG ADC_CDR5; /* ADC Channel Data Register 5 */ + AT91_REG ADC_CDR6; /* ADC Channel Data Register 6 */ + AT91_REG ADC_CDR7; /* ADC Channel Data Register 7 */ + AT91_REG Reserved1[ 44 ]; /* */ + AT91_REG ADC_RPR; /* Receive Pointer Register */ + AT91_REG ADC_RCR; /* Receive Counter Register */ + AT91_REG ADC_TPR; /* Transmit Pointer Register */ + AT91_REG ADC_TCR; /* Transmit Counter Register */ + AT91_REG ADC_RNPR; /* Receive Next Pointer Register */ + AT91_REG ADC_RNCR; /* Receive Next Counter Register */ + AT91_REG ADC_TNPR; /* Transmit Next Pointer Register */ + AT91_REG ADC_TNCR; /* Transmit Next Counter Register */ + AT91_REG ADC_PTCR; /* PDC Transfer Control Register */ + AT91_REG ADC_PTSR; /* PDC Transfer Status Register */ +} AT91S_ADC, * AT91PS_ADC; + +/* -------- ADC_CR : (ADC Offset: 0x0) ADC Control Register -------- */ +#define AT91C_ADC_SWRST ( ( unsigned int ) 0x1 << 0 ) /* (ADC) Software Reset */ +#define AT91C_ADC_START ( ( unsigned int ) 0x1 << 1 ) /* (ADC) Start Conversion */ +/* -------- ADC_MR : (ADC Offset: 0x4) ADC Mode Register -------- */ +#define AT91C_ADC_TRGEN ( ( unsigned int ) 0x1 << 0 ) /* (ADC) Trigger Enable */ +#define AT91C_ADC_TRGEN_DIS ( ( unsigned int ) 0x0 ) /* (ADC) Hardware triggers are disabled. Starting a conversion is only possible by software */ +#define AT91C_ADC_TRGEN_EN ( ( unsigned int ) 0x1 ) /* (ADC) Hardware trigger selected by TRGSEL field is enabled. */ +#define AT91C_ADC_TRGSEL ( ( unsigned int ) 0x7 << 1 ) /* (ADC) Trigger Selection */ +#define AT91C_ADC_TRGSEL_TIOA0 ( ( unsigned int ) 0x0 << 1 ) /* (ADC) Selected TRGSEL = TIAO0 */ +#define AT91C_ADC_TRGSEL_TIOA1 ( ( unsigned int ) 0x1 << 1 ) /* (ADC) Selected TRGSEL = TIAO1 */ +#define AT91C_ADC_TRGSEL_TIOA2 ( ( unsigned int ) 0x2 << 1 ) /* (ADC) Selected TRGSEL = TIAO2 */ +#define AT91C_ADC_TRGSEL_TIOA3 ( ( unsigned int ) 0x3 << 1 ) /* (ADC) Selected TRGSEL = TIAO3 */ +#define AT91C_ADC_TRGSEL_TIOA4 ( ( unsigned int ) 0x4 << 1 ) /* (ADC) Selected TRGSEL = TIAO4 */ +#define AT91C_ADC_TRGSEL_TIOA5 ( ( unsigned int ) 0x5 << 1 ) /* (ADC) Selected TRGSEL = TIAO5 */ +#define AT91C_ADC_TRGSEL_EXT ( ( unsigned int ) 0x6 << 1 ) /* (ADC) Selected TRGSEL = External Trigger */ +#define AT91C_ADC_LOWRES ( ( unsigned int ) 0x1 << 4 ) /* (ADC) Resolution. */ +#define AT91C_ADC_LOWRES_10_BIT ( ( unsigned int ) 0x0 << 4 ) /* (ADC) 10-bit resolution */ +#define AT91C_ADC_LOWRES_8_BIT ( ( unsigned int ) 0x1 << 4 ) /* (ADC) 8-bit resolution */ +#define AT91C_ADC_SLEEP ( ( unsigned int ) 0x1 << 5 ) /* (ADC) Sleep Mode */ +#define AT91C_ADC_SLEEP_NORMAL_MODE ( ( unsigned int ) 0x0 << 5 ) /* (ADC) Normal Mode */ +#define AT91C_ADC_SLEEP_MODE ( ( unsigned int ) 0x1 << 5 ) /* (ADC) Sleep Mode */ +#define AT91C_ADC_PRESCAL ( ( unsigned int ) 0x3F << 8 ) /* (ADC) Prescaler rate selection */ +#define AT91C_ADC_STARTUP ( ( unsigned int ) 0x1F << 16 ) /* (ADC) Startup Time */ +#define AT91C_ADC_SHTIM ( ( unsigned int ) 0xF << 24 ) /* (ADC) Sample & Hold Time */ +/* -------- ADC_CHER : (ADC Offset: 0x10) ADC Channel Enable Register -------- */ +#define AT91C_ADC_CH0 ( ( unsigned int ) 0x1 << 0 ) /* (ADC) Channel 0 */ +#define AT91C_ADC_CH1 ( ( unsigned int ) 0x1 << 1 ) /* (ADC) Channel 1 */ +#define AT91C_ADC_CH2 ( ( unsigned int ) 0x1 << 2 ) /* (ADC) Channel 2 */ +#define AT91C_ADC_CH3 ( ( unsigned int ) 0x1 << 3 ) /* (ADC) Channel 3 */ +#define AT91C_ADC_CH4 ( ( unsigned int ) 0x1 << 4 ) /* (ADC) Channel 4 */ +#define AT91C_ADC_CH5 ( ( unsigned int ) 0x1 << 5 ) /* (ADC) Channel 5 */ +#define AT91C_ADC_CH6 ( ( unsigned int ) 0x1 << 6 ) /* (ADC) Channel 6 */ +#define AT91C_ADC_CH7 ( ( unsigned int ) 0x1 << 7 ) /* (ADC) Channel 7 */ +/* -------- ADC_CHDR : (ADC Offset: 0x14) ADC Channel Disable Register -------- */ +/* -------- ADC_CHSR : (ADC Offset: 0x18) ADC Channel Status Register -------- */ +/* -------- ADC_SR : (ADC Offset: 0x1c) ADC Status Register -------- */ +#define AT91C_ADC_EOC0 ( ( unsigned int ) 0x1 << 0 ) /* (ADC) End of Conversion */ +#define AT91C_ADC_EOC1 ( ( unsigned int ) 0x1 << 1 ) /* (ADC) End of Conversion */ +#define AT91C_ADC_EOC2 ( ( unsigned int ) 0x1 << 2 ) /* (ADC) End of Conversion */ +#define AT91C_ADC_EOC3 ( ( unsigned int ) 0x1 << 3 ) /* (ADC) End of Conversion */ +#define AT91C_ADC_EOC4 ( ( unsigned int ) 0x1 << 4 ) /* (ADC) End of Conversion */ +#define AT91C_ADC_EOC5 ( ( unsigned int ) 0x1 << 5 ) /* (ADC) End of Conversion */ +#define AT91C_ADC_EOC6 ( ( unsigned int ) 0x1 << 6 ) /* (ADC) End of Conversion */ +#define AT91C_ADC_EOC7 ( ( unsigned int ) 0x1 << 7 ) /* (ADC) End of Conversion */ +#define AT91C_ADC_OVRE0 ( ( unsigned int ) 0x1 << 8 ) /* (ADC) Overrun Error */ +#define AT91C_ADC_OVRE1 ( ( unsigned int ) 0x1 << 9 ) /* (ADC) Overrun Error */ +#define AT91C_ADC_OVRE2 ( ( unsigned int ) 0x1 << 10 ) /* (ADC) Overrun Error */ +#define AT91C_ADC_OVRE3 ( ( unsigned int ) 0x1 << 11 ) /* (ADC) Overrun Error */ +#define AT91C_ADC_OVRE4 ( ( unsigned int ) 0x1 << 12 ) /* (ADC) Overrun Error */ +#define AT91C_ADC_OVRE5 ( ( unsigned int ) 0x1 << 13 ) /* (ADC) Overrun Error */ +#define AT91C_ADC_OVRE6 ( ( unsigned int ) 0x1 << 14 ) /* (ADC) Overrun Error */ +#define AT91C_ADC_OVRE7 ( ( unsigned int ) 0x1 << 15 ) /* (ADC) Overrun Error */ +#define AT91C_ADC_DRDY ( ( unsigned int ) 0x1 << 16 ) /* (ADC) Data Ready */ +#define AT91C_ADC_GOVRE ( ( unsigned int ) 0x1 << 17 ) /* (ADC) General Overrun */ +#define AT91C_ADC_ENDRX ( ( unsigned int ) 0x1 << 18 ) /* (ADC) End of Receiver Transfer */ +#define AT91C_ADC_RXBUFF ( ( unsigned int ) 0x1 << 19 ) /* (ADC) RXBUFF Interrupt */ +/* -------- ADC_LCDR : (ADC Offset: 0x20) ADC Last Converted Data Register -------- */ +#define AT91C_ADC_LDATA ( ( unsigned int ) 0x3FF << 0 ) /* (ADC) Last Data Converted */ +/* -------- ADC_IER : (ADC Offset: 0x24) ADC Interrupt Enable Register -------- */ +/* -------- ADC_IDR : (ADC Offset: 0x28) ADC Interrupt Disable Register -------- */ +/* -------- ADC_IMR : (ADC Offset: 0x2c) ADC Interrupt Mask Register -------- */ +/* -------- ADC_CDR0 : (ADC Offset: 0x30) ADC Channel Data Register 0 -------- */ +#define AT91C_ADC_DATA ( ( unsigned int ) 0x3FF << 0 ) /* (ADC) Converted Data */ +/* -------- ADC_CDR1 : (ADC Offset: 0x34) ADC Channel Data Register 1 -------- */ +/* -------- ADC_CDR2 : (ADC Offset: 0x38) ADC Channel Data Register 2 -------- */ +/* -------- ADC_CDR3 : (ADC Offset: 0x3c) ADC Channel Data Register 3 -------- */ +/* -------- ADC_CDR4 : (ADC Offset: 0x40) ADC Channel Data Register 4 -------- */ +/* -------- ADC_CDR5 : (ADC Offset: 0x44) ADC Channel Data Register 5 -------- */ +/* -------- ADC_CDR6 : (ADC Offset: 0x48) ADC Channel Data Register 6 -------- */ +/* -------- ADC_CDR7 : (ADC Offset: 0x4c) ADC Channel Data Register 7 -------- */ + +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR Advanced Encryption Standard */ +/* ***************************************************************************** */ +typedef struct _AT91S_AES +{ + AT91_REG AES_CR; /* Control Register */ + AT91_REG AES_MR; /* Mode Register */ + AT91_REG Reserved0[ 2 ]; /* */ + AT91_REG AES_IER; /* Interrupt Enable Register */ + AT91_REG AES_IDR; /* Interrupt Disable Register */ + AT91_REG AES_IMR; /* Interrupt Mask Register */ + AT91_REG AES_ISR; /* Interrupt Status Register */ + AT91_REG AES_KEYWxR[ 4 ]; /* Key Word x Register */ + AT91_REG Reserved1[ 4 ]; /* */ + AT91_REG AES_IDATAxR[ 4 ]; /* Input Data x Register */ + AT91_REG AES_ODATAxR[ 4 ]; /* Output Data x Register */ + AT91_REG AES_IVxR[ 4 ]; /* Initialization Vector x Register */ + AT91_REG Reserved2[ 35 ]; /* */ + AT91_REG AES_VR; /* AES Version Register */ + AT91_REG AES_RPR; /* Receive Pointer Register */ + AT91_REG AES_RCR; /* Receive Counter Register */ + AT91_REG AES_TPR; /* Transmit Pointer Register */ + AT91_REG AES_TCR; /* Transmit Counter Register */ + AT91_REG AES_RNPR; /* Receive Next Pointer Register */ + AT91_REG AES_RNCR; /* Receive Next Counter Register */ + AT91_REG AES_TNPR; /* Transmit Next Pointer Register */ + AT91_REG AES_TNCR; /* Transmit Next Counter Register */ + AT91_REG AES_PTCR; /* PDC Transfer Control Register */ + AT91_REG AES_PTSR; /* PDC Transfer Status Register */ +} AT91S_AES, * AT91PS_AES; + +/* -------- AES_CR : (AES Offset: 0x0) Control Register -------- */ +#define AT91C_AES_START ( ( unsigned int ) 0x1 << 0 ) /* (AES) Starts Processing */ +#define AT91C_AES_SWRST ( ( unsigned int ) 0x1 << 8 ) /* (AES) Software Reset */ +#define AT91C_AES_LOADSEED ( ( unsigned int ) 0x1 << 16 ) /* (AES) Random Number Generator Seed Loading */ +/* -------- AES_MR : (AES Offset: 0x4) Mode Register -------- */ +#define AT91C_AES_CIPHER ( ( unsigned int ) 0x1 << 0 ) /* (AES) Processing Mode */ +#define AT91C_AES_PROCDLY ( ( unsigned int ) 0xF << 4 ) /* (AES) Processing Delay */ +#define AT91C_AES_SMOD ( ( unsigned int ) 0x3 << 8 ) /* (AES) Start Mode */ +#define AT91C_AES_SMOD_MANUAL ( ( unsigned int ) 0x0 << 8 ) /* (AES) Manual Mode: The START bit in register AES_CR must be set to begin encryption or decryption. */ +#define AT91C_AES_SMOD_AUTO ( ( unsigned int ) 0x1 << 8 ) /* (AES) Auto Mode: no action in AES_CR is necessary (cf datasheet). */ +#define AT91C_AES_SMOD_PDC ( ( unsigned int ) 0x2 << 8 ) /* (AES) PDC Mode (cf datasheet). */ +#define AT91C_AES_OPMOD ( ( unsigned int ) 0x7 << 12 ) /* (AES) Operation Mode */ +#define AT91C_AES_OPMOD_ECB ( ( unsigned int ) 0x0 << 12 ) /* (AES) ECB Electronic CodeBook mode. */ +#define AT91C_AES_OPMOD_CBC ( ( unsigned int ) 0x1 << 12 ) /* (AES) CBC Cipher Block Chaining mode. */ +#define AT91C_AES_OPMOD_OFB ( ( unsigned int ) 0x2 << 12 ) /* (AES) OFB Output Feedback mode. */ +#define AT91C_AES_OPMOD_CFB ( ( unsigned int ) 0x3 << 12 ) /* (AES) CFB Cipher Feedback mode. */ +#define AT91C_AES_OPMOD_CTR ( ( unsigned int ) 0x4 << 12 ) /* (AES) CTR Counter mode. */ +#define AT91C_AES_LOD ( ( unsigned int ) 0x1 << 15 ) /* (AES) Last Output Data Mode */ +#define AT91C_AES_CFBS ( ( unsigned int ) 0x7 << 16 ) /* (AES) Cipher Feedback Data Size */ +#define AT91C_AES_CFBS_128_BIT ( ( unsigned int ) 0x0 << 16 ) /* (AES) 128-bit. */ +#define AT91C_AES_CFBS_64_BIT ( ( unsigned int ) 0x1 << 16 ) /* (AES) 64-bit. */ +#define AT91C_AES_CFBS_32_BIT ( ( unsigned int ) 0x2 << 16 ) /* (AES) 32-bit. */ +#define AT91C_AES_CFBS_16_BIT ( ( unsigned int ) 0x3 << 16 ) /* (AES) 16-bit. */ +#define AT91C_AES_CFBS_8_BIT ( ( unsigned int ) 0x4 << 16 ) /* (AES) 8-bit. */ +#define AT91C_AES_CKEY ( ( unsigned int ) 0xF << 20 ) /* (AES) Countermeasure Key */ +#define AT91C_AES_CTYPE ( ( unsigned int ) 0x1F << 24 ) /* (AES) Countermeasure Type */ +#define AT91C_AES_CTYPE_TYPE1_EN ( ( unsigned int ) 0x1 << 24 ) /* (AES) Countermeasure type 1 is enabled. */ +#define AT91C_AES_CTYPE_TYPE2_EN ( ( unsigned int ) 0x2 << 24 ) /* (AES) Countermeasure type 2 is enabled. */ +#define AT91C_AES_CTYPE_TYPE3_EN ( ( unsigned int ) 0x4 << 24 ) /* (AES) Countermeasure type 3 is enabled. */ +#define AT91C_AES_CTYPE_TYPE4_EN ( ( unsigned int ) 0x8 << 24 ) /* (AES) Countermeasure type 4 is enabled. */ +#define AT91C_AES_CTYPE_TYPE5_EN ( ( unsigned int ) 0x10 << 24 ) /* (AES) Countermeasure type 5 is enabled. */ +/* -------- AES_IER : (AES Offset: 0x10) Interrupt Enable Register -------- */ +#define AT91C_AES_DATRDY ( ( unsigned int ) 0x1 << 0 ) /* (AES) DATRDY */ +#define AT91C_AES_ENDRX ( ( unsigned int ) 0x1 << 1 ) /* (AES) PDC Read Buffer End */ +#define AT91C_AES_ENDTX ( ( unsigned int ) 0x1 << 2 ) /* (AES) PDC Write Buffer End */ +#define AT91C_AES_RXBUFF ( ( unsigned int ) 0x1 << 3 ) /* (AES) PDC Read Buffer Full */ +#define AT91C_AES_TXBUFE ( ( unsigned int ) 0x1 << 4 ) /* (AES) PDC Write Buffer Empty */ +#define AT91C_AES_URAD ( ( unsigned int ) 0x1 << 8 ) /* (AES) Unspecified Register Access Detection */ +/* -------- AES_IDR : (AES Offset: 0x14) Interrupt Disable Register -------- */ +/* -------- AES_IMR : (AES Offset: 0x18) Interrupt Mask Register -------- */ +/* -------- AES_ISR : (AES Offset: 0x1c) Interrupt Status Register -------- */ +#define AT91C_AES_URAT ( ( unsigned int ) 0x7 << 12 ) /* (AES) Unspecified Register Access Type Status */ +#define AT91C_AES_URAT_IN_DAT_WRITE_DATPROC ( ( unsigned int ) 0x0 << 12 ) /* (AES) Input data register written during the data processing in PDC mode. */ +#define AT91C_AES_URAT_OUT_DAT_READ_DATPROC ( ( unsigned int ) 0x1 << 12 ) /* (AES) Output data register read during the data processing. */ +#define AT91C_AES_URAT_MODEREG_WRITE_DATPROC ( ( unsigned int ) 0x2 << 12 ) /* (AES) Mode register written during the data processing. */ +#define AT91C_AES_URAT_OUT_DAT_READ_SUBKEY ( ( unsigned int ) 0x3 << 12 ) /* (AES) Output data register read during the sub-keys generation. */ +#define AT91C_AES_URAT_MODEREG_WRITE_SUBKEY ( ( unsigned int ) 0x4 << 12 ) /* (AES) Mode register written during the sub-keys generation. */ +#define AT91C_AES_URAT_WO_REG_READ ( ( unsigned int ) 0x5 << 12 ) /* (AES) Write-only register read access. */ + +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR Triple Data Encryption Standard */ +/* ***************************************************************************** */ +typedef struct _AT91S_TDES +{ + AT91_REG TDES_CR; /* Control Register */ + AT91_REG TDES_MR; /* Mode Register */ + AT91_REG Reserved0[ 2 ]; /* */ + AT91_REG TDES_IER; /* Interrupt Enable Register */ + AT91_REG TDES_IDR; /* Interrupt Disable Register */ + AT91_REG TDES_IMR; /* Interrupt Mask Register */ + AT91_REG TDES_ISR; /* Interrupt Status Register */ + AT91_REG TDES_KEY1WxR[ 2 ]; /* Key 1 Word x Register */ + AT91_REG TDES_KEY2WxR[ 2 ]; /* Key 2 Word x Register */ + AT91_REG TDES_KEY3WxR[ 2 ]; /* Key 3 Word x Register */ + AT91_REG Reserved1[ 2 ]; /* */ + AT91_REG TDES_IDATAxR[ 2 ]; /* Input Data x Register */ + AT91_REG Reserved2[ 2 ]; /* */ + AT91_REG TDES_ODATAxR[ 2 ]; /* Output Data x Register */ + AT91_REG Reserved3[ 2 ]; /* */ + AT91_REG TDES_IVxR[ 2 ]; /* Initialization Vector x Register */ + AT91_REG Reserved4[ 37 ]; /* */ + AT91_REG TDES_VR; /* TDES Version Register */ + AT91_REG TDES_RPR; /* Receive Pointer Register */ + AT91_REG TDES_RCR; /* Receive Counter Register */ + AT91_REG TDES_TPR; /* Transmit Pointer Register */ + AT91_REG TDES_TCR; /* Transmit Counter Register */ + AT91_REG TDES_RNPR; /* Receive Next Pointer Register */ + AT91_REG TDES_RNCR; /* Receive Next Counter Register */ + AT91_REG TDES_TNPR; /* Transmit Next Pointer Register */ + AT91_REG TDES_TNCR; /* Transmit Next Counter Register */ + AT91_REG TDES_PTCR; /* PDC Transfer Control Register */ + AT91_REG TDES_PTSR; /* PDC Transfer Status Register */ +} AT91S_TDES, * AT91PS_TDES; + +/* -------- TDES_CR : (TDES Offset: 0x0) Control Register -------- */ +#define AT91C_TDES_START ( ( unsigned int ) 0x1 << 0 ) /* (TDES) Starts Processing */ +#define AT91C_TDES_SWRST ( ( unsigned int ) 0x1 << 8 ) /* (TDES) Software Reset */ +/* -------- TDES_MR : (TDES Offset: 0x4) Mode Register -------- */ +#define AT91C_TDES_CIPHER ( ( unsigned int ) 0x1 << 0 ) /* (TDES) Processing Mode */ +#define AT91C_TDES_TDESMOD ( ( unsigned int ) 0x1 << 1 ) /* (TDES) Single or Triple DES Mode */ +#define AT91C_TDES_KEYMOD ( ( unsigned int ) 0x1 << 4 ) /* (TDES) Key Mode */ +#define AT91C_TDES_SMOD ( ( unsigned int ) 0x3 << 8 ) /* (TDES) Start Mode */ +#define AT91C_TDES_SMOD_MANUAL ( ( unsigned int ) 0x0 << 8 ) /* (TDES) Manual Mode: The START bit in register TDES_CR must be set to begin encryption or decryption. */ +#define AT91C_TDES_SMOD_AUTO ( ( unsigned int ) 0x1 << 8 ) /* (TDES) Auto Mode: no action in TDES_CR is necessary (cf datasheet). */ +#define AT91C_TDES_SMOD_PDC ( ( unsigned int ) 0x2 << 8 ) /* (TDES) PDC Mode (cf datasheet). */ +#define AT91C_TDES_OPMOD ( ( unsigned int ) 0x3 << 12 ) /* (TDES) Operation Mode */ +#define AT91C_TDES_OPMOD_ECB ( ( unsigned int ) 0x0 << 12 ) /* (TDES) ECB Electronic CodeBook mode. */ +#define AT91C_TDES_OPMOD_CBC ( ( unsigned int ) 0x1 << 12 ) /* (TDES) CBC Cipher Block Chaining mode. */ +#define AT91C_TDES_OPMOD_OFB ( ( unsigned int ) 0x2 << 12 ) /* (TDES) OFB Output Feedback mode. */ +#define AT91C_TDES_OPMOD_CFB ( ( unsigned int ) 0x3 << 12 ) /* (TDES) CFB Cipher Feedback mode. */ +#define AT91C_TDES_LOD ( ( unsigned int ) 0x1 << 15 ) /* (TDES) Last Output Data Mode */ +#define AT91C_TDES_CFBS ( ( unsigned int ) 0x3 << 16 ) /* (TDES) Cipher Feedback Data Size */ +#define AT91C_TDES_CFBS_64_BIT ( ( unsigned int ) 0x0 << 16 ) /* (TDES) 64-bit. */ +#define AT91C_TDES_CFBS_32_BIT ( ( unsigned int ) 0x1 << 16 ) /* (TDES) 32-bit. */ +#define AT91C_TDES_CFBS_16_BIT ( ( unsigned int ) 0x2 << 16 ) /* (TDES) 16-bit. */ +#define AT91C_TDES_CFBS_8_BIT ( ( unsigned int ) 0x3 << 16 ) /* (TDES) 8-bit. */ +/* -------- TDES_IER : (TDES Offset: 0x10) Interrupt Enable Register -------- */ +#define AT91C_TDES_DATRDY ( ( unsigned int ) 0x1 << 0 ) /* (TDES) DATRDY */ +#define AT91C_TDES_ENDRX ( ( unsigned int ) 0x1 << 1 ) /* (TDES) PDC Read Buffer End */ +#define AT91C_TDES_ENDTX ( ( unsigned int ) 0x1 << 2 ) /* (TDES) PDC Write Buffer End */ +#define AT91C_TDES_RXBUFF ( ( unsigned int ) 0x1 << 3 ) /* (TDES) PDC Read Buffer Full */ +#define AT91C_TDES_TXBUFE ( ( unsigned int ) 0x1 << 4 ) /* (TDES) PDC Write Buffer Empty */ +#define AT91C_TDES_URAD ( ( unsigned int ) 0x1 << 8 ) /* (TDES) Unspecified Register Access Detection */ +/* -------- TDES_IDR : (TDES Offset: 0x14) Interrupt Disable Register -------- */ +/* -------- TDES_IMR : (TDES Offset: 0x18) Interrupt Mask Register -------- */ +/* -------- TDES_ISR : (TDES Offset: 0x1c) Interrupt Status Register -------- */ +#define AT91C_TDES_URAT ( ( unsigned int ) 0x3 << 12 ) /* (TDES) Unspecified Register Access Type Status */ +#define AT91C_TDES_URAT_IN_DAT_WRITE_DATPROC ( ( unsigned int ) 0x0 << 12 ) /* (TDES) Input data register written during the data processing in PDC mode. */ +#define AT91C_TDES_URAT_OUT_DAT_READ_DATPROC ( ( unsigned int ) 0x1 << 12 ) /* (TDES) Output data register read during the data processing. */ +#define AT91C_TDES_URAT_MODEREG_WRITE_DATPROC ( ( unsigned int ) 0x2 << 12 ) /* (TDES) Mode register written during the data processing. */ +#define AT91C_TDES_URAT_WO_REG_READ ( ( unsigned int ) 0x3 << 12 ) /* (TDES) Write-only register read access. */ + +/* ***************************************************************************** */ +/* REGISTER ADDRESS DEFINITION FOR AT91SAM7X256 */ +/* ***************************************************************************** */ +/* ========== Register definition for SYS peripheral ========== */ +/* ========== Register definition for AIC peripheral ========== */ +#define AT91C_AIC_IVR ( ( AT91_REG * ) 0xFFFFF100 ) /* (AIC) IRQ Vector Register */ +#define AT91C_AIC_SMR ( ( AT91_REG * ) 0xFFFFF000 ) /* (AIC) Source Mode Register */ +#define AT91C_AIC_FVR ( ( AT91_REG * ) 0xFFFFF104 ) /* (AIC) FIQ Vector Register */ +#define AT91C_AIC_DCR ( ( AT91_REG * ) 0xFFFFF138 ) /* (AIC) Debug Control Register (Protect) */ +#define AT91C_AIC_EOICR ( ( AT91_REG * ) 0xFFFFF130 ) /* (AIC) End of Interrupt Command Register */ +#define AT91C_AIC_SVR ( ( AT91_REG * ) 0xFFFFF080 ) /* (AIC) Source Vector Register */ +#define AT91C_AIC_FFSR ( ( AT91_REG * ) 0xFFFFF148 ) /* (AIC) Fast Forcing Status Register */ +#define AT91C_AIC_ICCR ( ( AT91_REG * ) 0xFFFFF128 ) /* (AIC) Interrupt Clear Command Register */ +#define AT91C_AIC_ISR ( ( AT91_REG * ) 0xFFFFF108 ) /* (AIC) Interrupt Status Register */ +#define AT91C_AIC_IMR ( ( AT91_REG * ) 0xFFFFF110 ) /* (AIC) Interrupt Mask Register */ +#define AT91C_AIC_IPR ( ( AT91_REG * ) 0xFFFFF10C ) /* (AIC) Interrupt Pending Register */ +#define AT91C_AIC_FFER ( ( AT91_REG * ) 0xFFFFF140 ) /* (AIC) Fast Forcing Enable Register */ +#define AT91C_AIC_IECR ( ( AT91_REG * ) 0xFFFFF120 ) /* (AIC) Interrupt Enable Command Register */ +#define AT91C_AIC_ISCR ( ( AT91_REG * ) 0xFFFFF12C ) /* (AIC) Interrupt Set Command Register */ +#define AT91C_AIC_FFDR ( ( AT91_REG * ) 0xFFFFF144 ) /* (AIC) Fast Forcing Disable Register */ +#define AT91C_AIC_CISR ( ( AT91_REG * ) 0xFFFFF114 ) /* (AIC) Core Interrupt Status Register */ +#define AT91C_AIC_IDCR ( ( AT91_REG * ) 0xFFFFF124 ) /* (AIC) Interrupt Disable Command Register */ +#define AT91C_AIC_SPU ( ( AT91_REG * ) 0xFFFFF134 ) /* (AIC) Spurious Vector Register */ +/* ========== Register definition for PDC_DBGU peripheral ========== */ +#define AT91C_DBGU_TCR ( ( AT91_REG * ) 0xFFFFF30C ) /* (PDC_DBGU) Transmit Counter Register */ +#define AT91C_DBGU_RNPR ( ( AT91_REG * ) 0xFFFFF310 ) /* (PDC_DBGU) Receive Next Pointer Register */ +#define AT91C_DBGU_TNPR ( ( AT91_REG * ) 0xFFFFF318 ) /* (PDC_DBGU) Transmit Next Pointer Register */ +#define AT91C_DBGU_TPR ( ( AT91_REG * ) 0xFFFFF308 ) /* (PDC_DBGU) Transmit Pointer Register */ +#define AT91C_DBGU_RPR ( ( AT91_REG * ) 0xFFFFF300 ) /* (PDC_DBGU) Receive Pointer Register */ +#define AT91C_DBGU_RCR ( ( AT91_REG * ) 0xFFFFF304 ) /* (PDC_DBGU) Receive Counter Register */ +#define AT91C_DBGU_RNCR ( ( AT91_REG * ) 0xFFFFF314 ) /* (PDC_DBGU) Receive Next Counter Register */ +#define AT91C_DBGU_PTCR ( ( AT91_REG * ) 0xFFFFF320 ) /* (PDC_DBGU) PDC Transfer Control Register */ +#define AT91C_DBGU_PTSR ( ( AT91_REG * ) 0xFFFFF324 ) /* (PDC_DBGU) PDC Transfer Status Register */ +#define AT91C_DBGU_TNCR ( ( AT91_REG * ) 0xFFFFF31C ) /* (PDC_DBGU) Transmit Next Counter Register */ +/* ========== Register definition for DBGU peripheral ========== */ +#define AT91C_DBGU_EXID ( ( AT91_REG * ) 0xFFFFF244 ) /* (DBGU) Chip ID Extension Register */ +#define AT91C_DBGU_BRGR ( ( AT91_REG * ) 0xFFFFF220 ) /* (DBGU) Baud Rate Generator Register */ +#define AT91C_DBGU_IDR ( ( AT91_REG * ) 0xFFFFF20C ) /* (DBGU) Interrupt Disable Register */ +#define AT91C_DBGU_CSR ( ( AT91_REG * ) 0xFFFFF214 ) /* (DBGU) Channel Status Register */ +#define AT91C_DBGU_CIDR ( ( AT91_REG * ) 0xFFFFF240 ) /* (DBGU) Chip ID Register */ +#define AT91C_DBGU_MR ( ( AT91_REG * ) 0xFFFFF204 ) /* (DBGU) Mode Register */ +#define AT91C_DBGU_IMR ( ( AT91_REG * ) 0xFFFFF210 ) /* (DBGU) Interrupt Mask Register */ +#define AT91C_DBGU_CR ( ( AT91_REG * ) 0xFFFFF200 ) /* (DBGU) Control Register */ +#define AT91C_DBGU_FNTR ( ( AT91_REG * ) 0xFFFFF248 ) /* (DBGU) Force NTRST Register */ +#define AT91C_DBGU_THR ( ( AT91_REG * ) 0xFFFFF21C ) /* (DBGU) Transmitter Holding Register */ +#define AT91C_DBGU_RHR ( ( AT91_REG * ) 0xFFFFF218 ) /* (DBGU) Receiver Holding Register */ +#define AT91C_DBGU_IER ( ( AT91_REG * ) 0xFFFFF208 ) /* (DBGU) Interrupt Enable Register */ +/* ========== Register definition for PIOA peripheral ========== */ +#define AT91C_PIOA_ODR ( ( AT91_REG * ) 0xFFFFF414 ) /* (PIOA) Output Disable Registerr */ +#define AT91C_PIOA_SODR ( ( AT91_REG * ) 0xFFFFF430 ) /* (PIOA) Set Output Data Register */ +#define AT91C_PIOA_ISR ( ( AT91_REG * ) 0xFFFFF44C ) /* (PIOA) Interrupt Status Register */ +#define AT91C_PIOA_ABSR ( ( AT91_REG * ) 0xFFFFF478 ) /* (PIOA) AB Select Status Register */ +#define AT91C_PIOA_IER ( ( AT91_REG * ) 0xFFFFF440 ) /* (PIOA) Interrupt Enable Register */ +#define AT91C_PIOA_PPUDR ( ( AT91_REG * ) 0xFFFFF460 ) /* (PIOA) Pull-up Disable Register */ +#define AT91C_PIOA_IMR ( ( AT91_REG * ) 0xFFFFF448 ) /* (PIOA) Interrupt Mask Register */ +#define AT91C_PIOA_PER ( ( AT91_REG * ) 0xFFFFF400 ) /* (PIOA) PIO Enable Register */ +#define AT91C_PIOA_IFDR ( ( AT91_REG * ) 0xFFFFF424 ) /* (PIOA) Input Filter Disable Register */ +#define AT91C_PIOA_OWDR ( ( AT91_REG * ) 0xFFFFF4A4 ) /* (PIOA) Output Write Disable Register */ +#define AT91C_PIOA_MDSR ( ( AT91_REG * ) 0xFFFFF458 ) /* (PIOA) Multi-driver Status Register */ +#define AT91C_PIOA_IDR ( ( AT91_REG * ) 0xFFFFF444 ) /* (PIOA) Interrupt Disable Register */ +#define AT91C_PIOA_ODSR ( ( AT91_REG * ) 0xFFFFF438 ) /* (PIOA) Output Data Status Register */ +#define AT91C_PIOA_PPUSR ( ( AT91_REG * ) 0xFFFFF468 ) /* (PIOA) Pull-up Status Register */ +#define AT91C_PIOA_OWSR ( ( AT91_REG * ) 0xFFFFF4A8 ) /* (PIOA) Output Write Status Register */ +#define AT91C_PIOA_BSR ( ( AT91_REG * ) 0xFFFFF474 ) /* (PIOA) Select B Register */ +#define AT91C_PIOA_OWER ( ( AT91_REG * ) 0xFFFFF4A0 ) /* (PIOA) Output Write Enable Register */ +#define AT91C_PIOA_IFER ( ( AT91_REG * ) 0xFFFFF420 ) /* (PIOA) Input Filter Enable Register */ +#define AT91C_PIOA_PDSR ( ( AT91_REG * ) 0xFFFFF43C ) /* (PIOA) Pin Data Status Register */ +#define AT91C_PIOA_PPUER ( ( AT91_REG * ) 0xFFFFF464 ) /* (PIOA) Pull-up Enable Register */ +#define AT91C_PIOA_OSR ( ( AT91_REG * ) 0xFFFFF418 ) /* (PIOA) Output Status Register */ +#define AT91C_PIOA_ASR ( ( AT91_REG * ) 0xFFFFF470 ) /* (PIOA) Select A Register */ +#define AT91C_PIOA_MDDR ( ( AT91_REG * ) 0xFFFFF454 ) /* (PIOA) Multi-driver Disable Register */ +#define AT91C_PIOA_CODR ( ( AT91_REG * ) 0xFFFFF434 ) /* (PIOA) Clear Output Data Register */ +#define AT91C_PIOA_MDER ( ( AT91_REG * ) 0xFFFFF450 ) /* (PIOA) Multi-driver Enable Register */ +#define AT91C_PIOA_PDR ( ( AT91_REG * ) 0xFFFFF404 ) /* (PIOA) PIO Disable Register */ +#define AT91C_PIOA_IFSR ( ( AT91_REG * ) 0xFFFFF428 ) /* (PIOA) Input Filter Status Register */ +#define AT91C_PIOA_OER ( ( AT91_REG * ) 0xFFFFF410 ) /* (PIOA) Output Enable Register */ +#define AT91C_PIOA_PSR ( ( AT91_REG * ) 0xFFFFF408 ) /* (PIOA) PIO Status Register */ +/* ========== Register definition for PIOB peripheral ========== */ +#define AT91C_PIOB_OWDR ( ( AT91_REG * ) 0xFFFFF6A4 ) /* (PIOB) Output Write Disable Register */ +#define AT91C_PIOB_MDER ( ( AT91_REG * ) 0xFFFFF650 ) /* (PIOB) Multi-driver Enable Register */ +#define AT91C_PIOB_PPUSR ( ( AT91_REG * ) 0xFFFFF668 ) /* (PIOB) Pull-up Status Register */ +#define AT91C_PIOB_IMR ( ( AT91_REG * ) 0xFFFFF648 ) /* (PIOB) Interrupt Mask Register */ +#define AT91C_PIOB_ASR ( ( AT91_REG * ) 0xFFFFF670 ) /* (PIOB) Select A Register */ +#define AT91C_PIOB_PPUDR ( ( AT91_REG * ) 0xFFFFF660 ) /* (PIOB) Pull-up Disable Register */ +#define AT91C_PIOB_PSR ( ( AT91_REG * ) 0xFFFFF608 ) /* (PIOB) PIO Status Register */ +#define AT91C_PIOB_IER ( ( AT91_REG * ) 0xFFFFF640 ) /* (PIOB) Interrupt Enable Register */ +#define AT91C_PIOB_CODR ( ( AT91_REG * ) 0xFFFFF634 ) /* (PIOB) Clear Output Data Register */ +#define AT91C_PIOB_OWER ( ( AT91_REG * ) 0xFFFFF6A0 ) /* (PIOB) Output Write Enable Register */ +#define AT91C_PIOB_ABSR ( ( AT91_REG * ) 0xFFFFF678 ) /* (PIOB) AB Select Status Register */ +#define AT91C_PIOB_IFDR ( ( AT91_REG * ) 0xFFFFF624 ) /* (PIOB) Input Filter Disable Register */ +#define AT91C_PIOB_PDSR ( ( AT91_REG * ) 0xFFFFF63C ) /* (PIOB) Pin Data Status Register */ +#define AT91C_PIOB_IDR ( ( AT91_REG * ) 0xFFFFF644 ) /* (PIOB) Interrupt Disable Register */ +#define AT91C_PIOB_OWSR ( ( AT91_REG * ) 0xFFFFF6A8 ) /* (PIOB) Output Write Status Register */ +#define AT91C_PIOB_PDR ( ( AT91_REG * ) 0xFFFFF604 ) /* (PIOB) PIO Disable Register */ +#define AT91C_PIOB_ODR ( ( AT91_REG * ) 0xFFFFF614 ) /* (PIOB) Output Disable Registerr */ +#define AT91C_PIOB_IFSR ( ( AT91_REG * ) 0xFFFFF628 ) /* (PIOB) Input Filter Status Register */ +#define AT91C_PIOB_PPUER ( ( AT91_REG * ) 0xFFFFF664 ) /* (PIOB) Pull-up Enable Register */ +#define AT91C_PIOB_SODR ( ( AT91_REG * ) 0xFFFFF630 ) /* (PIOB) Set Output Data Register */ +#define AT91C_PIOB_ISR ( ( AT91_REG * ) 0xFFFFF64C ) /* (PIOB) Interrupt Status Register */ +#define AT91C_PIOB_ODSR ( ( AT91_REG * ) 0xFFFFF638 ) /* (PIOB) Output Data Status Register */ +#define AT91C_PIOB_OSR ( ( AT91_REG * ) 0xFFFFF618 ) /* (PIOB) Output Status Register */ +#define AT91C_PIOB_MDSR ( ( AT91_REG * ) 0xFFFFF658 ) /* (PIOB) Multi-driver Status Register */ +#define AT91C_PIOB_IFER ( ( AT91_REG * ) 0xFFFFF620 ) /* (PIOB) Input Filter Enable Register */ +#define AT91C_PIOB_BSR ( ( AT91_REG * ) 0xFFFFF674 ) /* (PIOB) Select B Register */ +#define AT91C_PIOB_MDDR ( ( AT91_REG * ) 0xFFFFF654 ) /* (PIOB) Multi-driver Disable Register */ +#define AT91C_PIOB_OER ( ( AT91_REG * ) 0xFFFFF610 ) /* (PIOB) Output Enable Register */ +#define AT91C_PIOB_PER ( ( AT91_REG * ) 0xFFFFF600 ) /* (PIOB) PIO Enable Register */ +/* ========== Register definition for CKGR peripheral ========== */ +#define AT91C_CKGR_MOR ( ( AT91_REG * ) 0xFFFFFC20 ) /* (CKGR) Main Oscillator Register */ +#define AT91C_CKGR_PLLR ( ( AT91_REG * ) 0xFFFFFC2C ) /* (CKGR) PLL Register */ +#define AT91C_CKGR_MCFR ( ( AT91_REG * ) 0xFFFFFC24 ) /* (CKGR) Main Clock Frequency Register */ +/* ========== Register definition for PMC peripheral ========== */ +#define AT91C_PMC_IDR ( ( AT91_REG * ) 0xFFFFFC64 ) /* (PMC) Interrupt Disable Register */ +#define AT91C_PMC_MOR ( ( AT91_REG * ) 0xFFFFFC20 ) /* (PMC) Main Oscillator Register */ +#define AT91C_PMC_PLLR ( ( AT91_REG * ) 0xFFFFFC2C ) /* (PMC) PLL Register */ +#define AT91C_PMC_PCER ( ( AT91_REG * ) 0xFFFFFC10 ) /* (PMC) Peripheral Clock Enable Register */ +#define AT91C_PMC_PCKR ( ( AT91_REG * ) 0xFFFFFC40 ) /* (PMC) Programmable Clock Register */ +#define AT91C_PMC_MCKR ( ( AT91_REG * ) 0xFFFFFC30 ) /* (PMC) Master Clock Register */ +#define AT91C_PMC_SCDR ( ( AT91_REG * ) 0xFFFFFC04 ) /* (PMC) System Clock Disable Register */ +#define AT91C_PMC_PCDR ( ( AT91_REG * ) 0xFFFFFC14 ) /* (PMC) Peripheral Clock Disable Register */ +#define AT91C_PMC_SCSR ( ( AT91_REG * ) 0xFFFFFC08 ) /* (PMC) System Clock Status Register */ +#define AT91C_PMC_PCSR ( ( AT91_REG * ) 0xFFFFFC18 ) /* (PMC) Peripheral Clock Status Register */ +#define AT91C_PMC_MCFR ( ( AT91_REG * ) 0xFFFFFC24 ) /* (PMC) Main Clock Frequency Register */ +#define AT91C_PMC_SCER ( ( AT91_REG * ) 0xFFFFFC00 ) /* (PMC) System Clock Enable Register */ +#define AT91C_PMC_IMR ( ( AT91_REG * ) 0xFFFFFC6C ) /* (PMC) Interrupt Mask Register */ +#define AT91C_PMC_IER ( ( AT91_REG * ) 0xFFFFFC60 ) /* (PMC) Interrupt Enable Register */ +#define AT91C_PMC_SR ( ( AT91_REG * ) 0xFFFFFC68 ) /* (PMC) Status Register */ +/* ========== Register definition for RSTC peripheral ========== */ +#define AT91C_RSTC_RCR ( ( AT91_REG * ) 0xFFFFFD00 ) /* (RSTC) Reset Control Register */ +#define AT91C_RSTC_RMR ( ( AT91_REG * ) 0xFFFFFD08 ) /* (RSTC) Reset Mode Register */ +#define AT91C_RSTC_RSR ( ( AT91_REG * ) 0xFFFFFD04 ) /* (RSTC) Reset Status Register */ +/* ========== Register definition for RTTC peripheral ========== */ +#define AT91C_RTTC_RTSR ( ( AT91_REG * ) 0xFFFFFD2C ) /* (RTTC) Real-time Status Register */ +#define AT91C_RTTC_RTMR ( ( AT91_REG * ) 0xFFFFFD20 ) /* (RTTC) Real-time Mode Register */ +#define AT91C_RTTC_RTVR ( ( AT91_REG * ) 0xFFFFFD28 ) /* (RTTC) Real-time Value Register */ +#define AT91C_RTTC_RTAR ( ( AT91_REG * ) 0xFFFFFD24 ) /* (RTTC) Real-time Alarm Register */ +/* ========== Register definition for PITC peripheral ========== */ +#define AT91C_PITC_PIVR ( ( AT91_REG * ) 0xFFFFFD38 ) /* (PITC) Period Interval Value Register */ +#define AT91C_PITC_PISR ( ( AT91_REG * ) 0xFFFFFD34 ) /* (PITC) Period Interval Status Register */ +#define AT91C_PITC_PIIR ( ( AT91_REG * ) 0xFFFFFD3C ) /* (PITC) Period Interval Image Register */ +#define AT91C_PITC_PIMR ( ( AT91_REG * ) 0xFFFFFD30 ) /* (PITC) Period Interval Mode Register */ +/* ========== Register definition for WDTC peripheral ========== */ +#define AT91C_WDTC_WDCR ( ( AT91_REG * ) 0xFFFFFD40 ) /* (WDTC) Watchdog Control Register */ +#define AT91C_WDTC_WDSR ( ( AT91_REG * ) 0xFFFFFD48 ) /* (WDTC) Watchdog Status Register */ +#define AT91C_WDTC_WDMR ( ( AT91_REG * ) 0xFFFFFD44 ) /* (WDTC) Watchdog Mode Register */ +/* ========== Register definition for VREG peripheral ========== */ +#define AT91C_VREG_MR ( ( AT91_REG * ) 0xFFFFFD60 ) /* (VREG) Voltage Regulator Mode Register */ +/* ========== Register definition for MC peripheral ========== */ +#define AT91C_MC_ASR ( ( AT91_REG * ) 0xFFFFFF04 ) /* (MC) MC Abort Status Register */ +#define AT91C_MC_RCR ( ( AT91_REG * ) 0xFFFFFF00 ) /* (MC) MC Remap Control Register */ +#define AT91C_MC_FCR ( ( AT91_REG * ) 0xFFFFFF64 ) /* (MC) MC Flash Command Register */ +#define AT91C_MC_AASR ( ( AT91_REG * ) 0xFFFFFF08 ) /* (MC) MC Abort Address Status Register */ +#define AT91C_MC_FSR ( ( AT91_REG * ) 0xFFFFFF68 ) /* (MC) MC Flash Status Register */ +#define AT91C_MC_FMR ( ( AT91_REG * ) 0xFFFFFF60 ) /* (MC) MC Flash Mode Register */ +/* ========== Register definition for PDC_SPI1 peripheral ========== */ +#define AT91C_SPI1_PTCR ( ( AT91_REG * ) 0xFFFE4120 ) /* (PDC_SPI1) PDC Transfer Control Register */ +#define AT91C_SPI1_RPR ( ( AT91_REG * ) 0xFFFE4100 ) /* (PDC_SPI1) Receive Pointer Register */ +#define AT91C_SPI1_TNCR ( ( AT91_REG * ) 0xFFFE411C ) /* (PDC_SPI1) Transmit Next Counter Register */ +#define AT91C_SPI1_TPR ( ( AT91_REG * ) 0xFFFE4108 ) /* (PDC_SPI1) Transmit Pointer Register */ +#define AT91C_SPI1_TNPR ( ( AT91_REG * ) 0xFFFE4118 ) /* (PDC_SPI1) Transmit Next Pointer Register */ +#define AT91C_SPI1_TCR ( ( AT91_REG * ) 0xFFFE410C ) /* (PDC_SPI1) Transmit Counter Register */ +#define AT91C_SPI1_RCR ( ( AT91_REG * ) 0xFFFE4104 ) /* (PDC_SPI1) Receive Counter Register */ +#define AT91C_SPI1_RNPR ( ( AT91_REG * ) 0xFFFE4110 ) /* (PDC_SPI1) Receive Next Pointer Register */ +#define AT91C_SPI1_RNCR ( ( AT91_REG * ) 0xFFFE4114 ) /* (PDC_SPI1) Receive Next Counter Register */ +#define AT91C_SPI1_PTSR ( ( AT91_REG * ) 0xFFFE4124 ) /* (PDC_SPI1) PDC Transfer Status Register */ +/* ========== Register definition for SPI1 peripheral ========== */ +#define AT91C_SPI1_IMR ( ( AT91_REG * ) 0xFFFE401C ) /* (SPI1) Interrupt Mask Register */ +#define AT91C_SPI1_IER ( ( AT91_REG * ) 0xFFFE4014 ) /* (SPI1) Interrupt Enable Register */ +#define AT91C_SPI1_MR ( ( AT91_REG * ) 0xFFFE4004 ) /* (SPI1) Mode Register */ +#define AT91C_SPI1_RDR ( ( AT91_REG * ) 0xFFFE4008 ) /* (SPI1) Receive Data Register */ +#define AT91C_SPI1_IDR ( ( AT91_REG * ) 0xFFFE4018 ) /* (SPI1) Interrupt Disable Register */ +#define AT91C_SPI1_SR ( ( AT91_REG * ) 0xFFFE4010 ) /* (SPI1) Status Register */ +#define AT91C_SPI1_TDR ( ( AT91_REG * ) 0xFFFE400C ) /* (SPI1) Transmit Data Register */ +#define AT91C_SPI1_CR ( ( AT91_REG * ) 0xFFFE4000 ) /* (SPI1) Control Register */ +#define AT91C_SPI1_CSR ( ( AT91_REG * ) 0xFFFE4030 ) /* (SPI1) Chip Select Register */ +/* ========== Register definition for PDC_SPI0 peripheral ========== */ +#define AT91C_SPI0_PTCR ( ( AT91_REG * ) 0xFFFE0120 ) /* (PDC_SPI0) PDC Transfer Control Register */ +#define AT91C_SPI0_TPR ( ( AT91_REG * ) 0xFFFE0108 ) /* (PDC_SPI0) Transmit Pointer Register */ +#define AT91C_SPI0_TCR ( ( AT91_REG * ) 0xFFFE010C ) /* (PDC_SPI0) Transmit Counter Register */ +#define AT91C_SPI0_RCR ( ( AT91_REG * ) 0xFFFE0104 ) /* (PDC_SPI0) Receive Counter Register */ +#define AT91C_SPI0_PTSR ( ( AT91_REG * ) 0xFFFE0124 ) /* (PDC_SPI0) PDC Transfer Status Register */ +#define AT91C_SPI0_RNPR ( ( AT91_REG * ) 0xFFFE0110 ) /* (PDC_SPI0) Receive Next Pointer Register */ +#define AT91C_SPI0_RPR ( ( AT91_REG * ) 0xFFFE0100 ) /* (PDC_SPI0) Receive Pointer Register */ +#define AT91C_SPI0_TNCR ( ( AT91_REG * ) 0xFFFE011C ) /* (PDC_SPI0) Transmit Next Counter Register */ +#define AT91C_SPI0_RNCR ( ( AT91_REG * ) 0xFFFE0114 ) /* (PDC_SPI0) Receive Next Counter Register */ +#define AT91C_SPI0_TNPR ( ( AT91_REG * ) 0xFFFE0118 ) /* (PDC_SPI0) Transmit Next Pointer Register */ +/* ========== Register definition for SPI0 peripheral ========== */ +#define AT91C_SPI0_IER ( ( AT91_REG * ) 0xFFFE0014 ) /* (SPI0) Interrupt Enable Register */ +#define AT91C_SPI0_SR ( ( AT91_REG * ) 0xFFFE0010 ) /* (SPI0) Status Register */ +#define AT91C_SPI0_IDR ( ( AT91_REG * ) 0xFFFE0018 ) /* (SPI0) Interrupt Disable Register */ +#define AT91C_SPI0_CR ( ( AT91_REG * ) 0xFFFE0000 ) /* (SPI0) Control Register */ +#define AT91C_SPI0_MR ( ( AT91_REG * ) 0xFFFE0004 ) /* (SPI0) Mode Register */ +#define AT91C_SPI0_IMR ( ( AT91_REG * ) 0xFFFE001C ) /* (SPI0) Interrupt Mask Register */ +#define AT91C_SPI0_TDR ( ( AT91_REG * ) 0xFFFE000C ) /* (SPI0) Transmit Data Register */ +#define AT91C_SPI0_RDR ( ( AT91_REG * ) 0xFFFE0008 ) /* (SPI0) Receive Data Register */ +#define AT91C_SPI0_CSR ( ( AT91_REG * ) 0xFFFE0030 ) /* (SPI0) Chip Select Register */ +/* ========== Register definition for PDC_US1 peripheral ========== */ +#define AT91C_US1_RNCR ( ( AT91_REG * ) 0xFFFC4114 ) /* (PDC_US1) Receive Next Counter Register */ +#define AT91C_US1_PTCR ( ( AT91_REG * ) 0xFFFC4120 ) /* (PDC_US1) PDC Transfer Control Register */ +#define AT91C_US1_TCR ( ( AT91_REG * ) 0xFFFC410C ) /* (PDC_US1) Transmit Counter Register */ +#define AT91C_US1_PTSR ( ( AT91_REG * ) 0xFFFC4124 ) /* (PDC_US1) PDC Transfer Status Register */ +#define AT91C_US1_TNPR ( ( AT91_REG * ) 0xFFFC4118 ) /* (PDC_US1) Transmit Next Pointer Register */ +#define AT91C_US1_RCR ( ( AT91_REG * ) 0xFFFC4104 ) /* (PDC_US1) Receive Counter Register */ +#define AT91C_US1_RNPR ( ( AT91_REG * ) 0xFFFC4110 ) /* (PDC_US1) Receive Next Pointer Register */ +#define AT91C_US1_RPR ( ( AT91_REG * ) 0xFFFC4100 ) /* (PDC_US1) Receive Pointer Register */ +#define AT91C_US1_TNCR ( ( AT91_REG * ) 0xFFFC411C ) /* (PDC_US1) Transmit Next Counter Register */ +#define AT91C_US1_TPR ( ( AT91_REG * ) 0xFFFC4108 ) /* (PDC_US1) Transmit Pointer Register */ +/* ========== Register definition for US1 peripheral ========== */ +#define AT91C_US1_IF ( ( AT91_REG * ) 0xFFFC404C ) /* (US1) IRDA_FILTER Register */ +#define AT91C_US1_NER ( ( AT91_REG * ) 0xFFFC4044 ) /* (US1) Nb Errors Register */ +#define AT91C_US1_RTOR ( ( AT91_REG * ) 0xFFFC4024 ) /* (US1) Receiver Time-out Register */ +#define AT91C_US1_CSR ( ( AT91_REG * ) 0xFFFC4014 ) /* (US1) Channel Status Register */ +#define AT91C_US1_IDR ( ( AT91_REG * ) 0xFFFC400C ) /* (US1) Interrupt Disable Register */ +#define AT91C_US1_IER ( ( AT91_REG * ) 0xFFFC4008 ) /* (US1) Interrupt Enable Register */ +#define AT91C_US1_THR ( ( AT91_REG * ) 0xFFFC401C ) /* (US1) Transmitter Holding Register */ +#define AT91C_US1_TTGR ( ( AT91_REG * ) 0xFFFC4028 ) /* (US1) Transmitter Time-guard Register */ +#define AT91C_US1_RHR ( ( AT91_REG * ) 0xFFFC4018 ) /* (US1) Receiver Holding Register */ +#define AT91C_US1_BRGR ( ( AT91_REG * ) 0xFFFC4020 ) /* (US1) Baud Rate Generator Register */ +#define AT91C_US1_IMR ( ( AT91_REG * ) 0xFFFC4010 ) /* (US1) Interrupt Mask Register */ +#define AT91C_US1_FIDI ( ( AT91_REG * ) 0xFFFC4040 ) /* (US1) FI_DI_Ratio Register */ +#define AT91C_US1_CR ( ( AT91_REG * ) 0xFFFC4000 ) /* (US1) Control Register */ +#define AT91C_US1_MR ( ( AT91_REG * ) 0xFFFC4004 ) /* (US1) Mode Register */ +/* ========== Register definition for PDC_US0 peripheral ========== */ +#define AT91C_US0_TNPR ( ( AT91_REG * ) 0xFFFC0118 ) /* (PDC_US0) Transmit Next Pointer Register */ +#define AT91C_US0_RNPR ( ( AT91_REG * ) 0xFFFC0110 ) /* (PDC_US0) Receive Next Pointer Register */ +#define AT91C_US0_TCR ( ( AT91_REG * ) 0xFFFC010C ) /* (PDC_US0) Transmit Counter Register */ +#define AT91C_US0_PTCR ( ( AT91_REG * ) 0xFFFC0120 ) /* (PDC_US0) PDC Transfer Control Register */ +#define AT91C_US0_PTSR ( ( AT91_REG * ) 0xFFFC0124 ) /* (PDC_US0) PDC Transfer Status Register */ +#define AT91C_US0_TNCR ( ( AT91_REG * ) 0xFFFC011C ) /* (PDC_US0) Transmit Next Counter Register */ +#define AT91C_US0_TPR ( ( AT91_REG * ) 0xFFFC0108 ) /* (PDC_US0) Transmit Pointer Register */ +#define AT91C_US0_RCR ( ( AT91_REG * ) 0xFFFC0104 ) /* (PDC_US0) Receive Counter Register */ +#define AT91C_US0_RPR ( ( AT91_REG * ) 0xFFFC0100 ) /* (PDC_US0) Receive Pointer Register */ +#define AT91C_US0_RNCR ( ( AT91_REG * ) 0xFFFC0114 ) /* (PDC_US0) Receive Next Counter Register */ +/* ========== Register definition for US0 peripheral ========== */ +#define AT91C_US0_BRGR ( ( AT91_REG * ) 0xFFFC0020 ) /* (US0) Baud Rate Generator Register */ +#define AT91C_US0_NER ( ( AT91_REG * ) 0xFFFC0044 ) /* (US0) Nb Errors Register */ +#define AT91C_US0_CR ( ( AT91_REG * ) 0xFFFC0000 ) /* (US0) Control Register */ +#define AT91C_US0_IMR ( ( AT91_REG * ) 0xFFFC0010 ) /* (US0) Interrupt Mask Register */ +#define AT91C_US0_FIDI ( ( AT91_REG * ) 0xFFFC0040 ) /* (US0) FI_DI_Ratio Register */ +#define AT91C_US0_TTGR ( ( AT91_REG * ) 0xFFFC0028 ) /* (US0) Transmitter Time-guard Register */ +#define AT91C_US0_MR ( ( AT91_REG * ) 0xFFFC0004 ) /* (US0) Mode Register */ +#define AT91C_US0_RTOR ( ( AT91_REG * ) 0xFFFC0024 ) /* (US0) Receiver Time-out Register */ +#define AT91C_US0_CSR ( ( AT91_REG * ) 0xFFFC0014 ) /* (US0) Channel Status Register */ +#define AT91C_US0_RHR ( ( AT91_REG * ) 0xFFFC0018 ) /* (US0) Receiver Holding Register */ +#define AT91C_US0_IDR ( ( AT91_REG * ) 0xFFFC000C ) /* (US0) Interrupt Disable Register */ +#define AT91C_US0_THR ( ( AT91_REG * ) 0xFFFC001C ) /* (US0) Transmitter Holding Register */ +#define AT91C_US0_IF ( ( AT91_REG * ) 0xFFFC004C ) /* (US0) IRDA_FILTER Register */ +#define AT91C_US0_IER ( ( AT91_REG * ) 0xFFFC0008 ) /* (US0) Interrupt Enable Register */ +/* ========== Register definition for PDC_SSC peripheral ========== */ +#define AT91C_SSC_TNCR ( ( AT91_REG * ) 0xFFFD411C ) /* (PDC_SSC) Transmit Next Counter Register */ +#define AT91C_SSC_RPR ( ( AT91_REG * ) 0xFFFD4100 ) /* (PDC_SSC) Receive Pointer Register */ +#define AT91C_SSC_RNCR ( ( AT91_REG * ) 0xFFFD4114 ) /* (PDC_SSC) Receive Next Counter Register */ +#define AT91C_SSC_TPR ( ( AT91_REG * ) 0xFFFD4108 ) /* (PDC_SSC) Transmit Pointer Register */ +#define AT91C_SSC_PTCR ( ( AT91_REG * ) 0xFFFD4120 ) /* (PDC_SSC) PDC Transfer Control Register */ +#define AT91C_SSC_TCR ( ( AT91_REG * ) 0xFFFD410C ) /* (PDC_SSC) Transmit Counter Register */ +#define AT91C_SSC_RCR ( ( AT91_REG * ) 0xFFFD4104 ) /* (PDC_SSC) Receive Counter Register */ +#define AT91C_SSC_RNPR ( ( AT91_REG * ) 0xFFFD4110 ) /* (PDC_SSC) Receive Next Pointer Register */ +#define AT91C_SSC_TNPR ( ( AT91_REG * ) 0xFFFD4118 ) /* (PDC_SSC) Transmit Next Pointer Register */ +#define AT91C_SSC_PTSR ( ( AT91_REG * ) 0xFFFD4124 ) /* (PDC_SSC) PDC Transfer Status Register */ +/* ========== Register definition for SSC peripheral ========== */ +#define AT91C_SSC_RHR ( ( AT91_REG * ) 0xFFFD4020 ) /* (SSC) Receive Holding Register */ +#define AT91C_SSC_RSHR ( ( AT91_REG * ) 0xFFFD4030 ) /* (SSC) Receive Sync Holding Register */ +#define AT91C_SSC_TFMR ( ( AT91_REG * ) 0xFFFD401C ) /* (SSC) Transmit Frame Mode Register */ +#define AT91C_SSC_IDR ( ( AT91_REG * ) 0xFFFD4048 ) /* (SSC) Interrupt Disable Register */ +#define AT91C_SSC_THR ( ( AT91_REG * ) 0xFFFD4024 ) /* (SSC) Transmit Holding Register */ +#define AT91C_SSC_RCMR ( ( AT91_REG * ) 0xFFFD4010 ) /* (SSC) Receive Clock ModeRegister */ +#define AT91C_SSC_IER ( ( AT91_REG * ) 0xFFFD4044 ) /* (SSC) Interrupt Enable Register */ +#define AT91C_SSC_TSHR ( ( AT91_REG * ) 0xFFFD4034 ) /* (SSC) Transmit Sync Holding Register */ +#define AT91C_SSC_SR ( ( AT91_REG * ) 0xFFFD4040 ) /* (SSC) Status Register */ +#define AT91C_SSC_CMR ( ( AT91_REG * ) 0xFFFD4004 ) /* (SSC) Clock Mode Register */ +#define AT91C_SSC_TCMR ( ( AT91_REG * ) 0xFFFD4018 ) /* (SSC) Transmit Clock Mode Register */ +#define AT91C_SSC_CR ( ( AT91_REG * ) 0xFFFD4000 ) /* (SSC) Control Register */ +#define AT91C_SSC_IMR ( ( AT91_REG * ) 0xFFFD404C ) /* (SSC) Interrupt Mask Register */ +#define AT91C_SSC_RFMR ( ( AT91_REG * ) 0xFFFD4014 ) /* (SSC) Receive Frame Mode Register */ +/* ========== Register definition for TWI peripheral ========== */ +#define AT91C_TWI_IER ( ( AT91_REG * ) 0xFFFB8024 ) /* (TWI) Interrupt Enable Register */ +#define AT91C_TWI_CR ( ( AT91_REG * ) 0xFFFB8000 ) /* (TWI) Control Register */ +#define AT91C_TWI_SR ( ( AT91_REG * ) 0xFFFB8020 ) /* (TWI) Status Register */ +#define AT91C_TWI_IMR ( ( AT91_REG * ) 0xFFFB802C ) /* (TWI) Interrupt Mask Register */ +#define AT91C_TWI_THR ( ( AT91_REG * ) 0xFFFB8034 ) /* (TWI) Transmit Holding Register */ +#define AT91C_TWI_IDR ( ( AT91_REG * ) 0xFFFB8028 ) /* (TWI) Interrupt Disable Register */ +#define AT91C_TWI_IADR ( ( AT91_REG * ) 0xFFFB800C ) /* (TWI) Internal Address Register */ +#define AT91C_TWI_MMR ( ( AT91_REG * ) 0xFFFB8004 ) /* (TWI) Master Mode Register */ +#define AT91C_TWI_CWGR ( ( AT91_REG * ) 0xFFFB8010 ) /* (TWI) Clock Waveform Generator Register */ +#define AT91C_TWI_RHR ( ( AT91_REG * ) 0xFFFB8030 ) /* (TWI) Receive Holding Register */ +/* ========== Register definition for PWMC_CH3 peripheral ========== */ +#define AT91C_PWMC_CH3_CUPDR ( ( AT91_REG * ) 0xFFFCC270 ) /* (PWMC_CH3) Channel Update Register */ +#define AT91C_PWMC_CH3_Reserved ( ( AT91_REG * ) 0xFFFCC274 ) /* (PWMC_CH3) Reserved */ +#define AT91C_PWMC_CH3_CPRDR ( ( AT91_REG * ) 0xFFFCC268 ) /* (PWMC_CH3) Channel Period Register */ +#define AT91C_PWMC_CH3_CDTYR ( ( AT91_REG * ) 0xFFFCC264 ) /* (PWMC_CH3) Channel Duty Cycle Register */ +#define AT91C_PWMC_CH3_CCNTR ( ( AT91_REG * ) 0xFFFCC26C ) /* (PWMC_CH3) Channel Counter Register */ +#define AT91C_PWMC_CH3_CMR ( ( AT91_REG * ) 0xFFFCC260 ) /* (PWMC_CH3) Channel Mode Register */ +/* ========== Register definition for PWMC_CH2 peripheral ========== */ +#define AT91C_PWMC_CH2_Reserved ( ( AT91_REG * ) 0xFFFCC254 ) /* (PWMC_CH2) Reserved */ +#define AT91C_PWMC_CH2_CMR ( ( AT91_REG * ) 0xFFFCC240 ) /* (PWMC_CH2) Channel Mode Register */ +#define AT91C_PWMC_CH2_CCNTR ( ( AT91_REG * ) 0xFFFCC24C ) /* (PWMC_CH2) Channel Counter Register */ +#define AT91C_PWMC_CH2_CPRDR ( ( AT91_REG * ) 0xFFFCC248 ) /* (PWMC_CH2) Channel Period Register */ +#define AT91C_PWMC_CH2_CUPDR ( ( AT91_REG * ) 0xFFFCC250 ) /* (PWMC_CH2) Channel Update Register */ +#define AT91C_PWMC_CH2_CDTYR ( ( AT91_REG * ) 0xFFFCC244 ) /* (PWMC_CH2) Channel Duty Cycle Register */ +/* ========== Register definition for PWMC_CH1 peripheral ========== */ +#define AT91C_PWMC_CH1_Reserved ( ( AT91_REG * ) 0xFFFCC234 ) /* (PWMC_CH1) Reserved */ +#define AT91C_PWMC_CH1_CUPDR ( ( AT91_REG * ) 0xFFFCC230 ) /* (PWMC_CH1) Channel Update Register */ +#define AT91C_PWMC_CH1_CPRDR ( ( AT91_REG * ) 0xFFFCC228 ) /* (PWMC_CH1) Channel Period Register */ +#define AT91C_PWMC_CH1_CCNTR ( ( AT91_REG * ) 0xFFFCC22C ) /* (PWMC_CH1) Channel Counter Register */ +#define AT91C_PWMC_CH1_CDTYR ( ( AT91_REG * ) 0xFFFCC224 ) /* (PWMC_CH1) Channel Duty Cycle Register */ +#define AT91C_PWMC_CH1_CMR ( ( AT91_REG * ) 0xFFFCC220 ) /* (PWMC_CH1) Channel Mode Register */ +/* ========== Register definition for PWMC_CH0 peripheral ========== */ +#define AT91C_PWMC_CH0_Reserved ( ( AT91_REG * ) 0xFFFCC214 ) /* (PWMC_CH0) Reserved */ +#define AT91C_PWMC_CH0_CPRDR ( ( AT91_REG * ) 0xFFFCC208 ) /* (PWMC_CH0) Channel Period Register */ +#define AT91C_PWMC_CH0_CDTYR ( ( AT91_REG * ) 0xFFFCC204 ) /* (PWMC_CH0) Channel Duty Cycle Register */ +#define AT91C_PWMC_CH0_CMR ( ( AT91_REG * ) 0xFFFCC200 ) /* (PWMC_CH0) Channel Mode Register */ +#define AT91C_PWMC_CH0_CUPDR ( ( AT91_REG * ) 0xFFFCC210 ) /* (PWMC_CH0) Channel Update Register */ +#define AT91C_PWMC_CH0_CCNTR ( ( AT91_REG * ) 0xFFFCC20C ) /* (PWMC_CH0) Channel Counter Register */ +/* ========== Register definition for PWMC peripheral ========== */ +#define AT91C_PWMC_IDR ( ( AT91_REG * ) 0xFFFCC014 ) /* (PWMC) PWMC Interrupt Disable Register */ +#define AT91C_PWMC_DIS ( ( AT91_REG * ) 0xFFFCC008 ) /* (PWMC) PWMC Disable Register */ +#define AT91C_PWMC_IER ( ( AT91_REG * ) 0xFFFCC010 ) /* (PWMC) PWMC Interrupt Enable Register */ +#define AT91C_PWMC_VR ( ( AT91_REG * ) 0xFFFCC0FC ) /* (PWMC) PWMC Version Register */ +#define AT91C_PWMC_ISR ( ( AT91_REG * ) 0xFFFCC01C ) /* (PWMC) PWMC Interrupt Status Register */ +#define AT91C_PWMC_SR ( ( AT91_REG * ) 0xFFFCC00C ) /* (PWMC) PWMC Status Register */ +#define AT91C_PWMC_IMR ( ( AT91_REG * ) 0xFFFCC018 ) /* (PWMC) PWMC Interrupt Mask Register */ +#define AT91C_PWMC_MR ( ( AT91_REG * ) 0xFFFCC000 ) /* (PWMC) PWMC Mode Register */ +#define AT91C_PWMC_ENA ( ( AT91_REG * ) 0xFFFCC004 ) /* (PWMC) PWMC Enable Register */ +/* ========== Register definition for UDP peripheral ========== */ +#define AT91C_UDP_IMR ( ( AT91_REG * ) 0xFFFB0018 ) /* (UDP) Interrupt Mask Register */ +#define AT91C_UDP_FADDR ( ( AT91_REG * ) 0xFFFB0008 ) /* (UDP) Function Address Register */ +#define AT91C_UDP_NUM ( ( AT91_REG * ) 0xFFFB0000 ) /* (UDP) Frame Number Register */ +#define AT91C_UDP_FDR ( ( AT91_REG * ) 0xFFFB0050 ) /* (UDP) Endpoint FIFO Data Register */ +#define AT91C_UDP_ISR ( ( AT91_REG * ) 0xFFFB001C ) /* (UDP) Interrupt Status Register */ +#define AT91C_UDP_CSR ( ( AT91_REG * ) 0xFFFB0030 ) /* (UDP) Endpoint Control and Status Register */ +#define AT91C_UDP_IDR ( ( AT91_REG * ) 0xFFFB0014 ) /* (UDP) Interrupt Disable Register */ +#define AT91C_UDP_ICR ( ( AT91_REG * ) 0xFFFB0020 ) /* (UDP) Interrupt Clear Register */ +#define AT91C_UDP_RSTEP ( ( AT91_REG * ) 0xFFFB0028 ) /* (UDP) Reset Endpoint Register */ +#define AT91C_UDP_TXVC ( ( AT91_REG * ) 0xFFFB0074 ) /* (UDP) Transceiver Control Register */ +#define AT91C_UDP_GLBSTATE ( ( AT91_REG * ) 0xFFFB0004 ) /* (UDP) Global State Register */ +#define AT91C_UDP_IER ( ( AT91_REG * ) 0xFFFB0010 ) /* (UDP) Interrupt Enable Register */ +/* ========== Register definition for TC0 peripheral ========== */ +#define AT91C_TC0_SR ( ( AT91_REG * ) 0xFFFA0020 ) /* (TC0) Status Register */ +#define AT91C_TC0_RC ( ( AT91_REG * ) 0xFFFA001C ) /* (TC0) Register C */ +#define AT91C_TC0_RB ( ( AT91_REG * ) 0xFFFA0018 ) /* (TC0) Register B */ +#define AT91C_TC0_CCR ( ( AT91_REG * ) 0xFFFA0000 ) /* (TC0) Channel Control Register */ +#define AT91C_TC0_CMR ( ( AT91_REG * ) 0xFFFA0004 ) /* (TC0) Channel Mode Register (Capture Mode / Waveform Mode) */ +#define AT91C_TC0_IER ( ( AT91_REG * ) 0xFFFA0024 ) /* (TC0) Interrupt Enable Register */ +#define AT91C_TC0_RA ( ( AT91_REG * ) 0xFFFA0014 ) /* (TC0) Register A */ +#define AT91C_TC0_IDR ( ( AT91_REG * ) 0xFFFA0028 ) /* (TC0) Interrupt Disable Register */ +#define AT91C_TC0_CV ( ( AT91_REG * ) 0xFFFA0010 ) /* (TC0) Counter Value */ +#define AT91C_TC0_IMR ( ( AT91_REG * ) 0xFFFA002C ) /* (TC0) Interrupt Mask Register */ +/* ========== Register definition for TC1 peripheral ========== */ +#define AT91C_TC1_RB ( ( AT91_REG * ) 0xFFFA0058 ) /* (TC1) Register B */ +#define AT91C_TC1_CCR ( ( AT91_REG * ) 0xFFFA0040 ) /* (TC1) Channel Control Register */ +#define AT91C_TC1_IER ( ( AT91_REG * ) 0xFFFA0064 ) /* (TC1) Interrupt Enable Register */ +#define AT91C_TC1_IDR ( ( AT91_REG * ) 0xFFFA0068 ) /* (TC1) Interrupt Disable Register */ +#define AT91C_TC1_SR ( ( AT91_REG * ) 0xFFFA0060 ) /* (TC1) Status Register */ +#define AT91C_TC1_CMR ( ( AT91_REG * ) 0xFFFA0044 ) /* (TC1) Channel Mode Register (Capture Mode / Waveform Mode) */ +#define AT91C_TC1_RA ( ( AT91_REG * ) 0xFFFA0054 ) /* (TC1) Register A */ +#define AT91C_TC1_RC ( ( AT91_REG * ) 0xFFFA005C ) /* (TC1) Register C */ +#define AT91C_TC1_IMR ( ( AT91_REG * ) 0xFFFA006C ) /* (TC1) Interrupt Mask Register */ +#define AT91C_TC1_CV ( ( AT91_REG * ) 0xFFFA0050 ) /* (TC1) Counter Value */ +/* ========== Register definition for TC2 peripheral ========== */ +#define AT91C_TC2_CMR ( ( AT91_REG * ) 0xFFFA0084 ) /* (TC2) Channel Mode Register (Capture Mode / Waveform Mode) */ +#define AT91C_TC2_CCR ( ( AT91_REG * ) 0xFFFA0080 ) /* (TC2) Channel Control Register */ +#define AT91C_TC2_CV ( ( AT91_REG * ) 0xFFFA0090 ) /* (TC2) Counter Value */ +#define AT91C_TC2_RA ( ( AT91_REG * ) 0xFFFA0094 ) /* (TC2) Register A */ +#define AT91C_TC2_RB ( ( AT91_REG * ) 0xFFFA0098 ) /* (TC2) Register B */ +#define AT91C_TC2_IDR ( ( AT91_REG * ) 0xFFFA00A8 ) /* (TC2) Interrupt Disable Register */ +#define AT91C_TC2_IMR ( ( AT91_REG * ) 0xFFFA00AC ) /* (TC2) Interrupt Mask Register */ +#define AT91C_TC2_RC ( ( AT91_REG * ) 0xFFFA009C ) /* (TC2) Register C */ +#define AT91C_TC2_IER ( ( AT91_REG * ) 0xFFFA00A4 ) /* (TC2) Interrupt Enable Register */ +#define AT91C_TC2_SR ( ( AT91_REG * ) 0xFFFA00A0 ) /* (TC2) Status Register */ +/* ========== Register definition for TCB peripheral ========== */ +#define AT91C_TCB_BMR ( ( AT91_REG * ) 0xFFFA00C4 ) /* (TCB) TC Block Mode Register */ +#define AT91C_TCB_BCR ( ( AT91_REG * ) 0xFFFA00C0 ) /* (TCB) TC Block Control Register */ +/* ========== Register definition for CAN_MB0 peripheral ========== */ +#define AT91C_CAN_MB0_MDL ( ( AT91_REG * ) 0xFFFD0214 ) /* (CAN_MB0) MailBox Data Low Register */ +#define AT91C_CAN_MB0_MAM ( ( AT91_REG * ) 0xFFFD0204 ) /* (CAN_MB0) MailBox Acceptance Mask Register */ +#define AT91C_CAN_MB0_MCR ( ( AT91_REG * ) 0xFFFD021C ) /* (CAN_MB0) MailBox Control Register */ +#define AT91C_CAN_MB0_MID ( ( AT91_REG * ) 0xFFFD0208 ) /* (CAN_MB0) MailBox ID Register */ +#define AT91C_CAN_MB0_MSR ( ( AT91_REG * ) 0xFFFD0210 ) /* (CAN_MB0) MailBox Status Register */ +#define AT91C_CAN_MB0_MFID ( ( AT91_REG * ) 0xFFFD020C ) /* (CAN_MB0) MailBox Family ID Register */ +#define AT91C_CAN_MB0_MDH ( ( AT91_REG * ) 0xFFFD0218 ) /* (CAN_MB0) MailBox Data High Register */ +#define AT91C_CAN_MB0_MMR ( ( AT91_REG * ) 0xFFFD0200 ) /* (CAN_MB0) MailBox Mode Register */ +/* ========== Register definition for CAN_MB1 peripheral ========== */ +#define AT91C_CAN_MB1_MDL ( ( AT91_REG * ) 0xFFFD0234 ) /* (CAN_MB1) MailBox Data Low Register */ +#define AT91C_CAN_MB1_MID ( ( AT91_REG * ) 0xFFFD0228 ) /* (CAN_MB1) MailBox ID Register */ +#define AT91C_CAN_MB1_MMR ( ( AT91_REG * ) 0xFFFD0220 ) /* (CAN_MB1) MailBox Mode Register */ +#define AT91C_CAN_MB1_MSR ( ( AT91_REG * ) 0xFFFD0230 ) /* (CAN_MB1) MailBox Status Register */ +#define AT91C_CAN_MB1_MAM ( ( AT91_REG * ) 0xFFFD0224 ) /* (CAN_MB1) MailBox Acceptance Mask Register */ +#define AT91C_CAN_MB1_MDH ( ( AT91_REG * ) 0xFFFD0238 ) /* (CAN_MB1) MailBox Data High Register */ +#define AT91C_CAN_MB1_MCR ( ( AT91_REG * ) 0xFFFD023C ) /* (CAN_MB1) MailBox Control Register */ +#define AT91C_CAN_MB1_MFID ( ( AT91_REG * ) 0xFFFD022C ) /* (CAN_MB1) MailBox Family ID Register */ +/* ========== Register definition for CAN_MB2 peripheral ========== */ +#define AT91C_CAN_MB2_MCR ( ( AT91_REG * ) 0xFFFD025C ) /* (CAN_MB2) MailBox Control Register */ +#define AT91C_CAN_MB2_MDH ( ( AT91_REG * ) 0xFFFD0258 ) /* (CAN_MB2) MailBox Data High Register */ +#define AT91C_CAN_MB2_MID ( ( AT91_REG * ) 0xFFFD0248 ) /* (CAN_MB2) MailBox ID Register */ +#define AT91C_CAN_MB2_MDL ( ( AT91_REG * ) 0xFFFD0254 ) /* (CAN_MB2) MailBox Data Low Register */ +#define AT91C_CAN_MB2_MMR ( ( AT91_REG * ) 0xFFFD0240 ) /* (CAN_MB2) MailBox Mode Register */ +#define AT91C_CAN_MB2_MAM ( ( AT91_REG * ) 0xFFFD0244 ) /* (CAN_MB2) MailBox Acceptance Mask Register */ +#define AT91C_CAN_MB2_MFID ( ( AT91_REG * ) 0xFFFD024C ) /* (CAN_MB2) MailBox Family ID Register */ +#define AT91C_CAN_MB2_MSR ( ( AT91_REG * ) 0xFFFD0250 ) /* (CAN_MB2) MailBox Status Register */ +/* ========== Register definition for CAN_MB3 peripheral ========== */ +#define AT91C_CAN_MB3_MFID ( ( AT91_REG * ) 0xFFFD026C ) /* (CAN_MB3) MailBox Family ID Register */ +#define AT91C_CAN_MB3_MAM ( ( AT91_REG * ) 0xFFFD0264 ) /* (CAN_MB3) MailBox Acceptance Mask Register */ +#define AT91C_CAN_MB3_MID ( ( AT91_REG * ) 0xFFFD0268 ) /* (CAN_MB3) MailBox ID Register */ +#define AT91C_CAN_MB3_MCR ( ( AT91_REG * ) 0xFFFD027C ) /* (CAN_MB3) MailBox Control Register */ +#define AT91C_CAN_MB3_MMR ( ( AT91_REG * ) 0xFFFD0260 ) /* (CAN_MB3) MailBox Mode Register */ +#define AT91C_CAN_MB3_MSR ( ( AT91_REG * ) 0xFFFD0270 ) /* (CAN_MB3) MailBox Status Register */ +#define AT91C_CAN_MB3_MDL ( ( AT91_REG * ) 0xFFFD0274 ) /* (CAN_MB3) MailBox Data Low Register */ +#define AT91C_CAN_MB3_MDH ( ( AT91_REG * ) 0xFFFD0278 ) /* (CAN_MB3) MailBox Data High Register */ +/* ========== Register definition for CAN_MB4 peripheral ========== */ +#define AT91C_CAN_MB4_MID ( ( AT91_REG * ) 0xFFFD0288 ) /* (CAN_MB4) MailBox ID Register */ +#define AT91C_CAN_MB4_MMR ( ( AT91_REG * ) 0xFFFD0280 ) /* (CAN_MB4) MailBox Mode Register */ +#define AT91C_CAN_MB4_MDH ( ( AT91_REG * ) 0xFFFD0298 ) /* (CAN_MB4) MailBox Data High Register */ +#define AT91C_CAN_MB4_MFID ( ( AT91_REG * ) 0xFFFD028C ) /* (CAN_MB4) MailBox Family ID Register */ +#define AT91C_CAN_MB4_MSR ( ( AT91_REG * ) 0xFFFD0290 ) /* (CAN_MB4) MailBox Status Register */ +#define AT91C_CAN_MB4_MCR ( ( AT91_REG * ) 0xFFFD029C ) /* (CAN_MB4) MailBox Control Register */ +#define AT91C_CAN_MB4_MDL ( ( AT91_REG * ) 0xFFFD0294 ) /* (CAN_MB4) MailBox Data Low Register */ +#define AT91C_CAN_MB4_MAM ( ( AT91_REG * ) 0xFFFD0284 ) /* (CAN_MB4) MailBox Acceptance Mask Register */ +/* ========== Register definition for CAN_MB5 peripheral ========== */ +#define AT91C_CAN_MB5_MSR ( ( AT91_REG * ) 0xFFFD02B0 ) /* (CAN_MB5) MailBox Status Register */ +#define AT91C_CAN_MB5_MCR ( ( AT91_REG * ) 0xFFFD02BC ) /* (CAN_MB5) MailBox Control Register */ +#define AT91C_CAN_MB5_MFID ( ( AT91_REG * ) 0xFFFD02AC ) /* (CAN_MB5) MailBox Family ID Register */ +#define AT91C_CAN_MB5_MDH ( ( AT91_REG * ) 0xFFFD02B8 ) /* (CAN_MB5) MailBox Data High Register */ +#define AT91C_CAN_MB5_MID ( ( AT91_REG * ) 0xFFFD02A8 ) /* (CAN_MB5) MailBox ID Register */ +#define AT91C_CAN_MB5_MMR ( ( AT91_REG * ) 0xFFFD02A0 ) /* (CAN_MB5) MailBox Mode Register */ +#define AT91C_CAN_MB5_MDL ( ( AT91_REG * ) 0xFFFD02B4 ) /* (CAN_MB5) MailBox Data Low Register */ +#define AT91C_CAN_MB5_MAM ( ( AT91_REG * ) 0xFFFD02A4 ) /* (CAN_MB5) MailBox Acceptance Mask Register */ +/* ========== Register definition for CAN_MB6 peripheral ========== */ +#define AT91C_CAN_MB6_MFID ( ( AT91_REG * ) 0xFFFD02CC ) /* (CAN_MB6) MailBox Family ID Register */ +#define AT91C_CAN_MB6_MID ( ( AT91_REG * ) 0xFFFD02C8 ) /* (CAN_MB6) MailBox ID Register */ +#define AT91C_CAN_MB6_MAM ( ( AT91_REG * ) 0xFFFD02C4 ) /* (CAN_MB6) MailBox Acceptance Mask Register */ +#define AT91C_CAN_MB6_MSR ( ( AT91_REG * ) 0xFFFD02D0 ) /* (CAN_MB6) MailBox Status Register */ +#define AT91C_CAN_MB6_MDL ( ( AT91_REG * ) 0xFFFD02D4 ) /* (CAN_MB6) MailBox Data Low Register */ +#define AT91C_CAN_MB6_MCR ( ( AT91_REG * ) 0xFFFD02DC ) /* (CAN_MB6) MailBox Control Register */ +#define AT91C_CAN_MB6_MDH ( ( AT91_REG * ) 0xFFFD02D8 ) /* (CAN_MB6) MailBox Data High Register */ +#define AT91C_CAN_MB6_MMR ( ( AT91_REG * ) 0xFFFD02C0 ) /* (CAN_MB6) MailBox Mode Register */ +/* ========== Register definition for CAN_MB7 peripheral ========== */ +#define AT91C_CAN_MB7_MCR ( ( AT91_REG * ) 0xFFFD02FC ) /* (CAN_MB7) MailBox Control Register */ +#define AT91C_CAN_MB7_MDH ( ( AT91_REG * ) 0xFFFD02F8 ) /* (CAN_MB7) MailBox Data High Register */ +#define AT91C_CAN_MB7_MFID ( ( AT91_REG * ) 0xFFFD02EC ) /* (CAN_MB7) MailBox Family ID Register */ +#define AT91C_CAN_MB7_MDL ( ( AT91_REG * ) 0xFFFD02F4 ) /* (CAN_MB7) MailBox Data Low Register */ +#define AT91C_CAN_MB7_MID ( ( AT91_REG * ) 0xFFFD02E8 ) /* (CAN_MB7) MailBox ID Register */ +#define AT91C_CAN_MB7_MMR ( ( AT91_REG * ) 0xFFFD02E0 ) /* (CAN_MB7) MailBox Mode Register */ +#define AT91C_CAN_MB7_MAM ( ( AT91_REG * ) 0xFFFD02E4 ) /* (CAN_MB7) MailBox Acceptance Mask Register */ +#define AT91C_CAN_MB7_MSR ( ( AT91_REG * ) 0xFFFD02F0 ) /* (CAN_MB7) MailBox Status Register */ +/* ========== Register definition for CAN peripheral ========== */ +#define AT91C_CAN_TCR ( ( AT91_REG * ) 0xFFFD0024 ) /* (CAN) Transfer Command Register */ +#define AT91C_CAN_IMR ( ( AT91_REG * ) 0xFFFD000C ) /* (CAN) Interrupt Mask Register */ +#define AT91C_CAN_IER ( ( AT91_REG * ) 0xFFFD0004 ) /* (CAN) Interrupt Enable Register */ +#define AT91C_CAN_ECR ( ( AT91_REG * ) 0xFFFD0020 ) /* (CAN) Error Counter Register */ +#define AT91C_CAN_TIMESTP ( ( AT91_REG * ) 0xFFFD001C ) /* (CAN) Time Stamp Register */ +#define AT91C_CAN_MR ( ( AT91_REG * ) 0xFFFD0000 ) /* (CAN) Mode Register */ +#define AT91C_CAN_IDR ( ( AT91_REG * ) 0xFFFD0008 ) /* (CAN) Interrupt Disable Register */ +#define AT91C_CAN_ACR ( ( AT91_REG * ) 0xFFFD0028 ) /* (CAN) Abort Command Register */ +#define AT91C_CAN_TIM ( ( AT91_REG * ) 0xFFFD0018 ) /* (CAN) Timer Register */ +#define AT91C_CAN_SR ( ( AT91_REG * ) 0xFFFD0010 ) /* (CAN) Status Register */ +#define AT91C_CAN_BR ( ( AT91_REG * ) 0xFFFD0014 ) /* (CAN) Baudrate Register */ +#define AT91C_CAN_VR ( ( AT91_REG * ) 0xFFFD00FC ) /* (CAN) Version Register */ +/* ========== Register definition for EMAC peripheral ========== */ +#define AT91C_EMAC_ISR ( ( AT91_REG * ) 0xFFFDC024 ) /* (EMAC) Interrupt Status Register */ +#define AT91C_EMAC_SA4H ( ( AT91_REG * ) 0xFFFDC0B4 ) /* (EMAC) Specific Address 4 Top, Last 2 bytes */ +#define AT91C_EMAC_SA1L ( ( AT91_REG * ) 0xFFFDC098 ) /* (EMAC) Specific Address 1 Bottom, First 4 bytes */ +#define AT91C_EMAC_ELE ( ( AT91_REG * ) 0xFFFDC078 ) /* (EMAC) Excessive Length Errors Register */ +#define AT91C_EMAC_LCOL ( ( AT91_REG * ) 0xFFFDC05C ) /* (EMAC) Late Collision Register */ +#define AT91C_EMAC_RLE ( ( AT91_REG * ) 0xFFFDC088 ) /* (EMAC) Receive Length Field Mismatch Register */ +#define AT91C_EMAC_WOL ( ( AT91_REG * ) 0xFFFDC0C4 ) /* (EMAC) Wake On LAN Register */ +#define AT91C_EMAC_DTF ( ( AT91_REG * ) 0xFFFDC058 ) /* (EMAC) Deferred Transmission Frame Register */ +#define AT91C_EMAC_TUND ( ( AT91_REG * ) 0xFFFDC064 ) /* (EMAC) Transmit Underrun Error Register */ +#define AT91C_EMAC_NCR ( ( AT91_REG * ) 0xFFFDC000 ) /* (EMAC) Network Control Register */ +#define AT91C_EMAC_SA4L ( ( AT91_REG * ) 0xFFFDC0B0 ) /* (EMAC) Specific Address 4 Bottom, First 4 bytes */ +#define AT91C_EMAC_RSR ( ( AT91_REG * ) 0xFFFDC020 ) /* (EMAC) Receive Status Register */ +#define AT91C_EMAC_SA3L ( ( AT91_REG * ) 0xFFFDC0A8 ) /* (EMAC) Specific Address 3 Bottom, First 4 bytes */ +#define AT91C_EMAC_TSR ( ( AT91_REG * ) 0xFFFDC014 ) /* (EMAC) Transmit Status Register */ +#define AT91C_EMAC_IDR ( ( AT91_REG * ) 0xFFFDC02C ) /* (EMAC) Interrupt Disable Register */ +#define AT91C_EMAC_RSE ( ( AT91_REG * ) 0xFFFDC074 ) /* (EMAC) Receive Symbol Errors Register */ +#define AT91C_EMAC_ECOL ( ( AT91_REG * ) 0xFFFDC060 ) /* (EMAC) Excessive Collision Register */ +#define AT91C_EMAC_TID ( ( AT91_REG * ) 0xFFFDC0B8 ) /* (EMAC) Type ID Checking Register */ +#define AT91C_EMAC_HRB ( ( AT91_REG * ) 0xFFFDC090 ) /* (EMAC) Hash Address Bottom[31:0] */ +#define AT91C_EMAC_TBQP ( ( AT91_REG * ) 0xFFFDC01C ) /* (EMAC) Transmit Buffer Queue Pointer */ +#define AT91C_EMAC_USRIO ( ( AT91_REG * ) 0xFFFDC0C0 ) /* (EMAC) USER Input/Output Register */ +#define AT91C_EMAC_PTR ( ( AT91_REG * ) 0xFFFDC038 ) /* (EMAC) Pause Time Register */ +#define AT91C_EMAC_SA2H ( ( AT91_REG * ) 0xFFFDC0A4 ) /* (EMAC) Specific Address 2 Top, Last 2 bytes */ +#define AT91C_EMAC_ROV ( ( AT91_REG * ) 0xFFFDC070 ) /* (EMAC) Receive Overrun Errors Register */ +#define AT91C_EMAC_ALE ( ( AT91_REG * ) 0xFFFDC054 ) /* (EMAC) Alignment Error Register */ +#define AT91C_EMAC_RJA ( ( AT91_REG * ) 0xFFFDC07C ) /* (EMAC) Receive Jabbers Register */ +#define AT91C_EMAC_RBQP ( ( AT91_REG * ) 0xFFFDC018 ) /* (EMAC) Receive Buffer Queue Pointer */ +#define AT91C_EMAC_TPF ( ( AT91_REG * ) 0xFFFDC08C ) /* (EMAC) Transmitted Pause Frames Register */ +#define AT91C_EMAC_NCFGR ( ( AT91_REG * ) 0xFFFDC004 ) /* (EMAC) Network Configuration Register */ +#define AT91C_EMAC_HRT ( ( AT91_REG * ) 0xFFFDC094 ) /* (EMAC) Hash Address Top[63:32] */ +#define AT91C_EMAC_USF ( ( AT91_REG * ) 0xFFFDC080 ) /* (EMAC) Undersize Frames Register */ +#define AT91C_EMAC_FCSE ( ( AT91_REG * ) 0xFFFDC050 ) /* (EMAC) Frame Check Sequence Error Register */ +#define AT91C_EMAC_TPQ ( ( AT91_REG * ) 0xFFFDC0BC ) /* (EMAC) Transmit Pause Quantum Register */ +#define AT91C_EMAC_MAN ( ( AT91_REG * ) 0xFFFDC034 ) /* (EMAC) PHY Maintenance Register */ +#define AT91C_EMAC_FTO ( ( AT91_REG * ) 0xFFFDC040 ) /* (EMAC) Frames Transmitted OK Register */ +#define AT91C_EMAC_REV ( ( AT91_REG * ) 0xFFFDC0FC ) /* (EMAC) Revision Register */ +#define AT91C_EMAC_IMR ( ( AT91_REG * ) 0xFFFDC030 ) /* (EMAC) Interrupt Mask Register */ +#define AT91C_EMAC_SCF ( ( AT91_REG * ) 0xFFFDC044 ) /* (EMAC) Single Collision Frame Register */ +#define AT91C_EMAC_PFR ( ( AT91_REG * ) 0xFFFDC03C ) /* (EMAC) Pause Frames received Register */ +#define AT91C_EMAC_MCF ( ( AT91_REG * ) 0xFFFDC048 ) /* (EMAC) Multiple Collision Frame Register */ +#define AT91C_EMAC_NSR ( ( AT91_REG * ) 0xFFFDC008 ) /* (EMAC) Network Status Register */ +#define AT91C_EMAC_SA2L ( ( AT91_REG * ) 0xFFFDC0A0 ) /* (EMAC) Specific Address 2 Bottom, First 4 bytes */ +#define AT91C_EMAC_FRO ( ( AT91_REG * ) 0xFFFDC04C ) /* (EMAC) Frames Received OK Register */ +#define AT91C_EMAC_IER ( ( AT91_REG * ) 0xFFFDC028 ) /* (EMAC) Interrupt Enable Register */ +#define AT91C_EMAC_SA1H ( ( AT91_REG * ) 0xFFFDC09C ) /* (EMAC) Specific Address 1 Top, Last 2 bytes */ +#define AT91C_EMAC_CSE ( ( AT91_REG * ) 0xFFFDC068 ) /* (EMAC) Carrier Sense Error Register */ +#define AT91C_EMAC_SA3H ( ( AT91_REG * ) 0xFFFDC0AC ) /* (EMAC) Specific Address 3 Top, Last 2 bytes */ +#define AT91C_EMAC_RRE ( ( AT91_REG * ) 0xFFFDC06C ) /* (EMAC) Receive Ressource Error Register */ +#define AT91C_EMAC_STE ( ( AT91_REG * ) 0xFFFDC084 ) /* (EMAC) SQE Test Error Register */ +/* ========== Register definition for PDC_ADC peripheral ========== */ +#define AT91C_ADC_PTSR ( ( AT91_REG * ) 0xFFFD8124 ) /* (PDC_ADC) PDC Transfer Status Register */ +#define AT91C_ADC_PTCR ( ( AT91_REG * ) 0xFFFD8120 ) /* (PDC_ADC) PDC Transfer Control Register */ +#define AT91C_ADC_TNPR ( ( AT91_REG * ) 0xFFFD8118 ) /* (PDC_ADC) Transmit Next Pointer Register */ +#define AT91C_ADC_TNCR ( ( AT91_REG * ) 0xFFFD811C ) /* (PDC_ADC) Transmit Next Counter Register */ +#define AT91C_ADC_RNPR ( ( AT91_REG * ) 0xFFFD8110 ) /* (PDC_ADC) Receive Next Pointer Register */ +#define AT91C_ADC_RNCR ( ( AT91_REG * ) 0xFFFD8114 ) /* (PDC_ADC) Receive Next Counter Register */ +#define AT91C_ADC_RPR ( ( AT91_REG * ) 0xFFFD8100 ) /* (PDC_ADC) Receive Pointer Register */ +#define AT91C_ADC_TCR ( ( AT91_REG * ) 0xFFFD810C ) /* (PDC_ADC) Transmit Counter Register */ +#define AT91C_ADC_TPR ( ( AT91_REG * ) 0xFFFD8108 ) /* (PDC_ADC) Transmit Pointer Register */ +#define AT91C_ADC_RCR ( ( AT91_REG * ) 0xFFFD8104 ) /* (PDC_ADC) Receive Counter Register */ +/* ========== Register definition for ADC peripheral ========== */ +#define AT91C_ADC_CDR2 ( ( AT91_REG * ) 0xFFFD8038 ) /* (ADC) ADC Channel Data Register 2 */ +#define AT91C_ADC_CDR3 ( ( AT91_REG * ) 0xFFFD803C ) /* (ADC) ADC Channel Data Register 3 */ +#define AT91C_ADC_CDR0 ( ( AT91_REG * ) 0xFFFD8030 ) /* (ADC) ADC Channel Data Register 0 */ +#define AT91C_ADC_CDR5 ( ( AT91_REG * ) 0xFFFD8044 ) /* (ADC) ADC Channel Data Register 5 */ +#define AT91C_ADC_CHDR ( ( AT91_REG * ) 0xFFFD8014 ) /* (ADC) ADC Channel Disable Register */ +#define AT91C_ADC_SR ( ( AT91_REG * ) 0xFFFD801C ) /* (ADC) ADC Status Register */ +#define AT91C_ADC_CDR4 ( ( AT91_REG * ) 0xFFFD8040 ) /* (ADC) ADC Channel Data Register 4 */ +#define AT91C_ADC_CDR1 ( ( AT91_REG * ) 0xFFFD8034 ) /* (ADC) ADC Channel Data Register 1 */ +#define AT91C_ADC_LCDR ( ( AT91_REG * ) 0xFFFD8020 ) /* (ADC) ADC Last Converted Data Register */ +#define AT91C_ADC_IDR ( ( AT91_REG * ) 0xFFFD8028 ) /* (ADC) ADC Interrupt Disable Register */ +#define AT91C_ADC_CR ( ( AT91_REG * ) 0xFFFD8000 ) /* (ADC) ADC Control Register */ +#define AT91C_ADC_CDR7 ( ( AT91_REG * ) 0xFFFD804C ) /* (ADC) ADC Channel Data Register 7 */ +#define AT91C_ADC_CDR6 ( ( AT91_REG * ) 0xFFFD8048 ) /* (ADC) ADC Channel Data Register 6 */ +#define AT91C_ADC_IER ( ( AT91_REG * ) 0xFFFD8024 ) /* (ADC) ADC Interrupt Enable Register */ +#define AT91C_ADC_CHER ( ( AT91_REG * ) 0xFFFD8010 ) /* (ADC) ADC Channel Enable Register */ +#define AT91C_ADC_CHSR ( ( AT91_REG * ) 0xFFFD8018 ) /* (ADC) ADC Channel Status Register */ +#define AT91C_ADC_MR ( ( AT91_REG * ) 0xFFFD8004 ) /* (ADC) ADC Mode Register */ +#define AT91C_ADC_IMR ( ( AT91_REG * ) 0xFFFD802C ) /* (ADC) ADC Interrupt Mask Register */ +/* ========== Register definition for PDC_AES peripheral ========== */ +#define AT91C_AES_TPR ( ( AT91_REG * ) 0xFFFA4108 ) /* (PDC_AES) Transmit Pointer Register */ +#define AT91C_AES_PTCR ( ( AT91_REG * ) 0xFFFA4120 ) /* (PDC_AES) PDC Transfer Control Register */ +#define AT91C_AES_RNPR ( ( AT91_REG * ) 0xFFFA4110 ) /* (PDC_AES) Receive Next Pointer Register */ +#define AT91C_AES_TNCR ( ( AT91_REG * ) 0xFFFA411C ) /* (PDC_AES) Transmit Next Counter Register */ +#define AT91C_AES_TCR ( ( AT91_REG * ) 0xFFFA410C ) /* (PDC_AES) Transmit Counter Register */ +#define AT91C_AES_RCR ( ( AT91_REG * ) 0xFFFA4104 ) /* (PDC_AES) Receive Counter Register */ +#define AT91C_AES_RNCR ( ( AT91_REG * ) 0xFFFA4114 ) /* (PDC_AES) Receive Next Counter Register */ +#define AT91C_AES_TNPR ( ( AT91_REG * ) 0xFFFA4118 ) /* (PDC_AES) Transmit Next Pointer Register */ +#define AT91C_AES_RPR ( ( AT91_REG * ) 0xFFFA4100 ) /* (PDC_AES) Receive Pointer Register */ +#define AT91C_AES_PTSR ( ( AT91_REG * ) 0xFFFA4124 ) /* (PDC_AES) PDC Transfer Status Register */ +/* ========== Register definition for AES peripheral ========== */ +#define AT91C_AES_IVxR ( ( AT91_REG * ) 0xFFFA4060 ) /* (AES) Initialization Vector x Register */ +#define AT91C_AES_MR ( ( AT91_REG * ) 0xFFFA4004 ) /* (AES) Mode Register */ +#define AT91C_AES_VR ( ( AT91_REG * ) 0xFFFA40FC ) /* (AES) AES Version Register */ +#define AT91C_AES_ODATAxR ( ( AT91_REG * ) 0xFFFA4050 ) /* (AES) Output Data x Register */ +#define AT91C_AES_IDATAxR ( ( AT91_REG * ) 0xFFFA4040 ) /* (AES) Input Data x Register */ +#define AT91C_AES_CR ( ( AT91_REG * ) 0xFFFA4000 ) /* (AES) Control Register */ +#define AT91C_AES_IDR ( ( AT91_REG * ) 0xFFFA4014 ) /* (AES) Interrupt Disable Register */ +#define AT91C_AES_IMR ( ( AT91_REG * ) 0xFFFA4018 ) /* (AES) Interrupt Mask Register */ +#define AT91C_AES_IER ( ( AT91_REG * ) 0xFFFA4010 ) /* (AES) Interrupt Enable Register */ +#define AT91C_AES_KEYWxR ( ( AT91_REG * ) 0xFFFA4020 ) /* (AES) Key Word x Register */ +#define AT91C_AES_ISR ( ( AT91_REG * ) 0xFFFA401C ) /* (AES) Interrupt Status Register */ +/* ========== Register definition for PDC_TDES peripheral ========== */ +#define AT91C_TDES_RNCR ( ( AT91_REG * ) 0xFFFA8114 ) /* (PDC_TDES) Receive Next Counter Register */ +#define AT91C_TDES_TCR ( ( AT91_REG * ) 0xFFFA810C ) /* (PDC_TDES) Transmit Counter Register */ +#define AT91C_TDES_RCR ( ( AT91_REG * ) 0xFFFA8104 ) /* (PDC_TDES) Receive Counter Register */ +#define AT91C_TDES_TNPR ( ( AT91_REG * ) 0xFFFA8118 ) /* (PDC_TDES) Transmit Next Pointer Register */ +#define AT91C_TDES_RNPR ( ( AT91_REG * ) 0xFFFA8110 ) /* (PDC_TDES) Receive Next Pointer Register */ +#define AT91C_TDES_RPR ( ( AT91_REG * ) 0xFFFA8100 ) /* (PDC_TDES) Receive Pointer Register */ +#define AT91C_TDES_TNCR ( ( AT91_REG * ) 0xFFFA811C ) /* (PDC_TDES) Transmit Next Counter Register */ +#define AT91C_TDES_TPR ( ( AT91_REG * ) 0xFFFA8108 ) /* (PDC_TDES) Transmit Pointer Register */ +#define AT91C_TDES_PTSR ( ( AT91_REG * ) 0xFFFA8124 ) /* (PDC_TDES) PDC Transfer Status Register */ +#define AT91C_TDES_PTCR ( ( AT91_REG * ) 0xFFFA8120 ) /* (PDC_TDES) PDC Transfer Control Register */ +/* ========== Register definition for TDES peripheral ========== */ +#define AT91C_TDES_KEY2WxR ( ( AT91_REG * ) 0xFFFA8028 ) /* (TDES) Key 2 Word x Register */ +#define AT91C_TDES_KEY3WxR ( ( AT91_REG * ) 0xFFFA8030 ) /* (TDES) Key 3 Word x Register */ +#define AT91C_TDES_IDR ( ( AT91_REG * ) 0xFFFA8014 ) /* (TDES) Interrupt Disable Register */ +#define AT91C_TDES_VR ( ( AT91_REG * ) 0xFFFA80FC ) /* (TDES) TDES Version Register */ +#define AT91C_TDES_IVxR ( ( AT91_REG * ) 0xFFFA8060 ) /* (TDES) Initialization Vector x Register */ +#define AT91C_TDES_ODATAxR ( ( AT91_REG * ) 0xFFFA8050 ) /* (TDES) Output Data x Register */ +#define AT91C_TDES_IMR ( ( AT91_REG * ) 0xFFFA8018 ) /* (TDES) Interrupt Mask Register */ +#define AT91C_TDES_MR ( ( AT91_REG * ) 0xFFFA8004 ) /* (TDES) Mode Register */ +#define AT91C_TDES_CR ( ( AT91_REG * ) 0xFFFA8000 ) /* (TDES) Control Register */ +#define AT91C_TDES_IER ( ( AT91_REG * ) 0xFFFA8010 ) /* (TDES) Interrupt Enable Register */ +#define AT91C_TDES_ISR ( ( AT91_REG * ) 0xFFFA801C ) /* (TDES) Interrupt Status Register */ +#define AT91C_TDES_IDATAxR ( ( AT91_REG * ) 0xFFFA8040 ) /* (TDES) Input Data x Register */ +#define AT91C_TDES_KEY1WxR ( ( AT91_REG * ) 0xFFFA8020 ) /* (TDES) Key 1 Word x Register */ + +/* ***************************************************************************** */ +/* PIO DEFINITIONS FOR AT91SAM7X256 */ +/* ***************************************************************************** */ +#define AT91C_PIO_PA0 ( ( unsigned int ) 1 << 0 ) /* Pin Controlled by PA0 */ +#define AT91C_PA0_RXD0 ( ( unsigned int ) AT91C_PIO_PA0 ) /* USART 0 Receive Data */ +#define AT91C_PIO_PA1 ( ( unsigned int ) 1 << 1 ) /* Pin Controlled by PA1 */ +#define AT91C_PA1_TXD0 ( ( unsigned int ) AT91C_PIO_PA1 ) /* USART 0 Transmit Data */ +#define AT91C_PIO_PA10 ( ( unsigned int ) 1 << 10 ) /* Pin Controlled by PA10 */ +#define AT91C_PA10_TWD ( ( unsigned int ) AT91C_PIO_PA10 ) /* TWI Two-wire Serial Data */ +#define AT91C_PIO_PA11 ( ( unsigned int ) 1 << 11 ) /* Pin Controlled by PA11 */ +#define AT91C_PA11_TWCK ( ( unsigned int ) AT91C_PIO_PA11 ) /* TWI Two-wire Serial Clock */ +#define AT91C_PIO_PA12 ( ( unsigned int ) 1 << 12 ) /* Pin Controlled by PA12 */ +#define AT91C_PA12_NPCS00 ( ( unsigned int ) AT91C_PIO_PA12 ) /* SPI 0 Peripheral Chip Select 0 */ +#define AT91C_PIO_PA13 ( ( unsigned int ) 1 << 13 ) /* Pin Controlled by PA13 */ +#define AT91C_PA13_NPCS01 ( ( unsigned int ) AT91C_PIO_PA13 ) /* SPI 0 Peripheral Chip Select 1 */ +#define AT91C_PA13_PCK1 ( ( unsigned int ) AT91C_PIO_PA13 ) /* PMC Programmable Clock Output 1 */ +#define AT91C_PIO_PA14 ( ( unsigned int ) 1 << 14 ) /* Pin Controlled by PA14 */ +#define AT91C_PA14_NPCS02 ( ( unsigned int ) AT91C_PIO_PA14 ) /* SPI 0 Peripheral Chip Select 2 */ +#define AT91C_PA14_IRQ1 ( ( unsigned int ) AT91C_PIO_PA14 ) /* External Interrupt 1 */ +#define AT91C_PIO_PA15 ( ( unsigned int ) 1 << 15 ) /* Pin Controlled by PA15 */ +#define AT91C_PA15_NPCS03 ( ( unsigned int ) AT91C_PIO_PA15 ) /* SPI 0 Peripheral Chip Select 3 */ +#define AT91C_PA15_TCLK2 ( ( unsigned int ) AT91C_PIO_PA15 ) /* Timer Counter 2 external clock input */ +#define AT91C_PIO_PA16 ( ( unsigned int ) 1 << 16 ) /* Pin Controlled by PA16 */ +#define AT91C_PA16_MISO0 ( ( unsigned int ) AT91C_PIO_PA16 ) /* SPI 0 Master In Slave */ +#define AT91C_PIO_PA17 ( ( unsigned int ) 1 << 17 ) /* Pin Controlled by PA17 */ +#define AT91C_PA17_MOSI0 ( ( unsigned int ) AT91C_PIO_PA17 ) /* SPI 0 Master Out Slave */ +#define AT91C_PIO_PA18 ( ( unsigned int ) 1 << 18 ) /* Pin Controlled by PA18 */ +#define AT91C_PA18_SPCK0 ( ( unsigned int ) AT91C_PIO_PA18 ) /* SPI 0 Serial Clock */ +#define AT91C_PIO_PA19 ( ( unsigned int ) 1 << 19 ) /* Pin Controlled by PA19 */ +#define AT91C_PA19_CANRX ( ( unsigned int ) AT91C_PIO_PA19 ) /* CAN Receive */ +#define AT91C_PIO_PA2 ( ( unsigned int ) 1 << 2 ) /* Pin Controlled by PA2 */ +#define AT91C_PA2_SCK0 ( ( unsigned int ) AT91C_PIO_PA2 ) /* USART 0 Serial Clock */ +#define AT91C_PA2_NPCS11 ( ( unsigned int ) AT91C_PIO_PA2 ) /* SPI 1 Peripheral Chip Select 1 */ +#define AT91C_PIO_PA20 ( ( unsigned int ) 1 << 20 ) /* Pin Controlled by PA20 */ +#define AT91C_PA20_CANTX ( ( unsigned int ) AT91C_PIO_PA20 ) /* CAN Transmit */ +#define AT91C_PIO_PA21 ( ( unsigned int ) 1 << 21 ) /* Pin Controlled by PA21 */ +#define AT91C_PA21_TF ( ( unsigned int ) AT91C_PIO_PA21 ) /* SSC Transmit Frame Sync */ +#define AT91C_PA21_NPCS10 ( ( unsigned int ) AT91C_PIO_PA21 ) /* SPI 1 Peripheral Chip Select 0 */ +#define AT91C_PIO_PA22 ( ( unsigned int ) 1 << 22 ) /* Pin Controlled by PA22 */ +#define AT91C_PA22_TK ( ( unsigned int ) AT91C_PIO_PA22 ) /* SSC Transmit Clock */ +#define AT91C_PA22_SPCK1 ( ( unsigned int ) AT91C_PIO_PA22 ) /* SPI 1 Serial Clock */ +#define AT91C_PIO_PA23 ( ( unsigned int ) 1 << 23 ) /* Pin Controlled by PA23 */ +#define AT91C_PA23_TD ( ( unsigned int ) AT91C_PIO_PA23 ) /* SSC Transmit data */ +#define AT91C_PA23_MOSI1 ( ( unsigned int ) AT91C_PIO_PA23 ) /* SPI 1 Master Out Slave */ +#define AT91C_PIO_PA24 ( ( unsigned int ) 1 << 24 ) /* Pin Controlled by PA24 */ +#define AT91C_PA24_RD ( ( unsigned int ) AT91C_PIO_PA24 ) /* SSC Receive Data */ +#define AT91C_PA24_MISO1 ( ( unsigned int ) AT91C_PIO_PA24 ) /* SPI 1 Master In Slave */ +#define AT91C_PIO_PA25 ( ( unsigned int ) 1 << 25 ) /* Pin Controlled by PA25 */ +#define AT91C_PA25_RK ( ( unsigned int ) AT91C_PIO_PA25 ) /* SSC Receive Clock */ +#define AT91C_PA25_NPCS11 ( ( unsigned int ) AT91C_PIO_PA25 ) /* SPI 1 Peripheral Chip Select 1 */ +#define AT91C_PIO_PA26 ( ( unsigned int ) 1 << 26 ) /* Pin Controlled by PA26 */ +#define AT91C_PA26_RF ( ( unsigned int ) AT91C_PIO_PA26 ) /* SSC Receive Frame Sync */ +#define AT91C_PA26_NPCS12 ( ( unsigned int ) AT91C_PIO_PA26 ) /* SPI 1 Peripheral Chip Select 2 */ +#define AT91C_PIO_PA27 ( ( unsigned int ) 1 << 27 ) /* Pin Controlled by PA27 */ +#define AT91C_PA27_DRXD ( ( unsigned int ) AT91C_PIO_PA27 ) /* DBGU Debug Receive Data */ +#define AT91C_PA27_PCK3 ( ( unsigned int ) AT91C_PIO_PA27 ) /* PMC Programmable Clock Output 3 */ +#define AT91C_PIO_PA28 ( ( unsigned int ) 1 << 28 ) /* Pin Controlled by PA28 */ +#define AT91C_PA28_DTXD ( ( unsigned int ) AT91C_PIO_PA28 ) /* DBGU Debug Transmit Data */ +#define AT91C_PIO_PA29 ( ( unsigned int ) 1 << 29 ) /* Pin Controlled by PA29 */ +#define AT91C_PA29_FIQ ( ( unsigned int ) AT91C_PIO_PA29 ) /* AIC Fast Interrupt Input */ +#define AT91C_PA29_NPCS13 ( ( unsigned int ) AT91C_PIO_PA29 ) /* SPI 1 Peripheral Chip Select 3 */ +#define AT91C_PIO_PA3 ( ( unsigned int ) 1 << 3 ) /* Pin Controlled by PA3 */ +#define AT91C_PA3_RTS0 ( ( unsigned int ) AT91C_PIO_PA3 ) /* USART 0 Ready To Send */ +#define AT91C_PA3_NPCS12 ( ( unsigned int ) AT91C_PIO_PA3 ) /* SPI 1 Peripheral Chip Select 2 */ +#define AT91C_PIO_PA30 ( ( unsigned int ) 1 << 30 ) /* Pin Controlled by PA30 */ +#define AT91C_PA30_IRQ0 ( ( unsigned int ) AT91C_PIO_PA30 ) /* External Interrupt 0 */ +#define AT91C_PA30_PCK2 ( ( unsigned int ) AT91C_PIO_PA30 ) /* PMC Programmable Clock Output 2 */ +#define AT91C_PIO_PA4 ( ( unsigned int ) 1 << 4 ) /* Pin Controlled by PA4 */ +#define AT91C_PA4_CTS0 ( ( unsigned int ) AT91C_PIO_PA4 ) /* USART 0 Clear To Send */ +#define AT91C_PA4_NPCS13 ( ( unsigned int ) AT91C_PIO_PA4 ) /* SPI 1 Peripheral Chip Select 3 */ +#define AT91C_PIO_PA5 ( ( unsigned int ) 1 << 5 ) /* Pin Controlled by PA5 */ +#define AT91C_PA5_RXD1 ( ( unsigned int ) AT91C_PIO_PA5 ) /* USART 1 Receive Data */ +#define AT91C_PIO_PA6 ( ( unsigned int ) 1 << 6 ) /* Pin Controlled by PA6 */ +#define AT91C_PA6_TXD1 ( ( unsigned int ) AT91C_PIO_PA6 ) /* USART 1 Transmit Data */ +#define AT91C_PIO_PA7 ( ( unsigned int ) 1 << 7 ) /* Pin Controlled by PA7 */ +#define AT91C_PA7_SCK1 ( ( unsigned int ) AT91C_PIO_PA7 ) /* USART 1 Serial Clock */ +#define AT91C_PA7_NPCS01 ( ( unsigned int ) AT91C_PIO_PA7 ) /* SPI 0 Peripheral Chip Select 1 */ +#define AT91C_PIO_PA8 ( ( unsigned int ) 1 << 8 ) /* Pin Controlled by PA8 */ +#define AT91C_PA8_RTS1 ( ( unsigned int ) AT91C_PIO_PA8 ) /* USART 1 Ready To Send */ +#define AT91C_PA8_NPCS02 ( ( unsigned int ) AT91C_PIO_PA8 ) /* SPI 0 Peripheral Chip Select 2 */ +#define AT91C_PIO_PA9 ( ( unsigned int ) 1 << 9 ) /* Pin Controlled by PA9 */ +#define AT91C_PA9_CTS1 ( ( unsigned int ) AT91C_PIO_PA9 ) /* USART 1 Clear To Send */ +#define AT91C_PA9_NPCS03 ( ( unsigned int ) AT91C_PIO_PA9 ) /* SPI 0 Peripheral Chip Select 3 */ +#define AT91C_PIO_PB0 ( ( unsigned int ) 1 << 0 ) /* Pin Controlled by PB0 */ +#define AT91C_PB0_ETXCK_EREFCK ( ( unsigned int ) AT91C_PIO_PB0 ) /* Ethernet MAC Transmit Clock/Reference Clock */ +#define AT91C_PB0_PCK0 ( ( unsigned int ) AT91C_PIO_PB0 ) /* PMC Programmable Clock Output 0 */ +#define AT91C_PIO_PB1 ( ( unsigned int ) 1 << 1 ) /* Pin Controlled by PB1 */ +#define AT91C_PB1_ETXEN ( ( unsigned int ) AT91C_PIO_PB1 ) /* Ethernet MAC Transmit Enable */ +#define AT91C_PIO_PB10 ( ( unsigned int ) 1 << 10 ) /* Pin Controlled by PB10 */ +#define AT91C_PB10_ETX2 ( ( unsigned int ) AT91C_PIO_PB10 ) /* Ethernet MAC Transmit Data 2 */ +#define AT91C_PB10_NPCS11 ( ( unsigned int ) AT91C_PIO_PB10 ) /* SPI 1 Peripheral Chip Select 1 */ +#define AT91C_PIO_PB11 ( ( unsigned int ) 1 << 11 ) /* Pin Controlled by PB11 */ +#define AT91C_PB11_ETX3 ( ( unsigned int ) AT91C_PIO_PB11 ) /* Ethernet MAC Transmit Data 3 */ +#define AT91C_PB11_NPCS12 ( ( unsigned int ) AT91C_PIO_PB11 ) /* SPI 1 Peripheral Chip Select 2 */ +#define AT91C_PIO_PB12 ( ( unsigned int ) 1 << 12 ) /* Pin Controlled by PB12 */ +#define AT91C_PB12_ETXER ( ( unsigned int ) AT91C_PIO_PB12 ) /* Ethernet MAC Transmit Coding Error */ +#define AT91C_PB12_TCLK0 ( ( unsigned int ) AT91C_PIO_PB12 ) /* Timer Counter 0 external clock input */ +#define AT91C_PIO_PB13 ( ( unsigned int ) 1 << 13 ) /* Pin Controlled by PB13 */ +#define AT91C_PB13_ERX2 ( ( unsigned int ) AT91C_PIO_PB13 ) /* Ethernet MAC Receive Data 2 */ +#define AT91C_PB13_NPCS01 ( ( unsigned int ) AT91C_PIO_PB13 ) /* SPI 0 Peripheral Chip Select 1 */ +#define AT91C_PIO_PB14 ( ( unsigned int ) 1 << 14 ) /* Pin Controlled by PB14 */ +#define AT91C_PB14_ERX3 ( ( unsigned int ) AT91C_PIO_PB14 ) /* Ethernet MAC Receive Data 3 */ +#define AT91C_PB14_NPCS02 ( ( unsigned int ) AT91C_PIO_PB14 ) /* SPI 0 Peripheral Chip Select 2 */ +#define AT91C_PIO_PB15 ( ( unsigned int ) 1 << 15 ) /* Pin Controlled by PB15 */ +#define AT91C_PB15_ERXDV ( ( unsigned int ) AT91C_PIO_PB15 ) /* Ethernet MAC Receive Data Valid */ +#define AT91C_PIO_PB16 ( ( unsigned int ) 1 << 16 ) /* Pin Controlled by PB16 */ +#define AT91C_PB16_ECOL ( ( unsigned int ) AT91C_PIO_PB16 ) /* Ethernet MAC Collision Detected */ +#define AT91C_PB16_NPCS13 ( ( unsigned int ) AT91C_PIO_PB16 ) /* SPI 1 Peripheral Chip Select 3 */ +#define AT91C_PIO_PB17 ( ( unsigned int ) 1 << 17 ) /* Pin Controlled by PB17 */ +#define AT91C_PB17_ERXCK ( ( unsigned int ) AT91C_PIO_PB17 ) /* Ethernet MAC Receive Clock */ +#define AT91C_PB17_NPCS03 ( ( unsigned int ) AT91C_PIO_PB17 ) /* SPI 0 Peripheral Chip Select 3 */ +#define AT91C_PIO_PB18 ( ( unsigned int ) 1 << 18 ) /* Pin Controlled by PB18 */ +#define AT91C_PB18_EF100 ( ( unsigned int ) AT91C_PIO_PB18 ) /* Ethernet MAC Force 100 Mbits/sec */ +#define AT91C_PB18_ADTRG ( ( unsigned int ) AT91C_PIO_PB18 ) /* ADC External Trigger */ +#define AT91C_PIO_PB19 ( ( unsigned int ) 1 << 19 ) /* Pin Controlled by PB19 */ +#define AT91C_PB19_PWM0 ( ( unsigned int ) AT91C_PIO_PB19 ) /* PWM Channel 0 */ +#define AT91C_PB19_TCLK1 ( ( unsigned int ) AT91C_PIO_PB19 ) /* Timer Counter 1 external clock input */ +#define AT91C_PIO_PB2 ( ( unsigned int ) 1 << 2 ) /* Pin Controlled by PB2 */ +#define AT91C_PB2_ETX0 ( ( unsigned int ) AT91C_PIO_PB2 ) /* Ethernet MAC Transmit Data 0 */ +#define AT91C_PIO_PB20 ( ( unsigned int ) 1 << 20 ) /* Pin Controlled by PB20 */ +#define AT91C_PB20_PWM1 ( ( unsigned int ) AT91C_PIO_PB20 ) /* PWM Channel 1 */ +#define AT91C_PB20_PCK0 ( ( unsigned int ) AT91C_PIO_PB20 ) /* PMC Programmable Clock Output 0 */ +#define AT91C_PIO_PB21 ( ( unsigned int ) 1 << 21 ) /* Pin Controlled by PB21 */ +#define AT91C_PB21_PWM2 ( ( unsigned int ) AT91C_PIO_PB21 ) /* PWM Channel 2 */ +#define AT91C_PB21_PCK1 ( ( unsigned int ) AT91C_PIO_PB21 ) /* PMC Programmable Clock Output 1 */ +#define AT91C_PIO_PB22 ( ( unsigned int ) 1 << 22 ) /* Pin Controlled by PB22 */ +#define AT91C_PB22_PWM3 ( ( unsigned int ) AT91C_PIO_PB22 ) /* PWM Channel 3 */ +#define AT91C_PB22_PCK2 ( ( unsigned int ) AT91C_PIO_PB22 ) /* PMC Programmable Clock Output 2 */ +#define AT91C_PIO_PB23 ( ( unsigned int ) 1 << 23 ) /* Pin Controlled by PB23 */ +#define AT91C_PB23_TIOA0 ( ( unsigned int ) AT91C_PIO_PB23 ) /* Timer Counter 0 Multipurpose Timer I/O Pin A */ +#define AT91C_PB23_DCD1 ( ( unsigned int ) AT91C_PIO_PB23 ) /* USART 1 Data Carrier Detect */ +#define AT91C_PIO_PB24 ( ( unsigned int ) 1 << 24 ) /* Pin Controlled by PB24 */ +#define AT91C_PB24_TIOB0 ( ( unsigned int ) AT91C_PIO_PB24 ) /* Timer Counter 0 Multipurpose Timer I/O Pin B */ +#define AT91C_PB24_DSR1 ( ( unsigned int ) AT91C_PIO_PB24 ) /* USART 1 Data Set ready */ +#define AT91C_PIO_PB25 ( ( unsigned int ) 1 << 25 ) /* Pin Controlled by PB25 */ +#define AT91C_PB25_TIOA1 ( ( unsigned int ) AT91C_PIO_PB25 ) /* Timer Counter 1 Multipurpose Timer I/O Pin A */ +#define AT91C_PB25_DTR1 ( ( unsigned int ) AT91C_PIO_PB25 ) /* USART 1 Data Terminal ready */ +#define AT91C_PIO_PB26 ( ( unsigned int ) 1 << 26 ) /* Pin Controlled by PB26 */ +#define AT91C_PB26_TIOB1 ( ( unsigned int ) AT91C_PIO_PB26 ) /* Timer Counter 1 Multipurpose Timer I/O Pin B */ +#define AT91C_PB26_RI1 ( ( unsigned int ) AT91C_PIO_PB26 ) /* USART 1 Ring Indicator */ +#define AT91C_PIO_PB27 ( ( unsigned int ) 1 << 27 ) /* Pin Controlled by PB27 */ +#define AT91C_PB27_TIOA2 ( ( unsigned int ) AT91C_PIO_PB27 ) /* Timer Counter 2 Multipurpose Timer I/O Pin A */ +#define AT91C_PB27_PWM0 ( ( unsigned int ) AT91C_PIO_PB27 ) /* PWM Channel 0 */ +#define AT91C_PIO_PB28 ( ( unsigned int ) 1 << 28 ) /* Pin Controlled by PB28 */ +#define AT91C_PB28_TIOB2 ( ( unsigned int ) AT91C_PIO_PB28 ) /* Timer Counter 2 Multipurpose Timer I/O Pin B */ +#define AT91C_PB28_PWM1 ( ( unsigned int ) AT91C_PIO_PB28 ) /* PWM Channel 1 */ +#define AT91C_PIO_PB29 ( ( unsigned int ) 1 << 29 ) /* Pin Controlled by PB29 */ +#define AT91C_PB29_PCK1 ( ( unsigned int ) AT91C_PIO_PB29 ) /* PMC Programmable Clock Output 1 */ +#define AT91C_PB29_PWM2 ( ( unsigned int ) AT91C_PIO_PB29 ) /* PWM Channel 2 */ +#define AT91C_PIO_PB3 ( ( unsigned int ) 1 << 3 ) /* Pin Controlled by PB3 */ +#define AT91C_PB3_ETX1 ( ( unsigned int ) AT91C_PIO_PB3 ) /* Ethernet MAC Transmit Data 1 */ +#define AT91C_PIO_PB30 ( ( unsigned int ) 1 << 30 ) /* Pin Controlled by PB30 */ +#define AT91C_PB30_PCK2 ( ( unsigned int ) AT91C_PIO_PB30 ) /* PMC Programmable Clock Output 2 */ +#define AT91C_PB30_PWM3 ( ( unsigned int ) AT91C_PIO_PB30 ) /* PWM Channel 3 */ +#define AT91C_PIO_PB4 ( ( unsigned int ) 1 << 4 ) /* Pin Controlled by PB4 */ +#define AT91C_PB4_ECRS_ECRSDV ( ( unsigned int ) AT91C_PIO_PB4 ) /* Ethernet MAC Carrier Sense/Carrier Sense and Data Valid */ +#define AT91C_PIO_PB5 ( ( unsigned int ) 1 << 5 ) /* Pin Controlled by PB5 */ +#define AT91C_PB5_ERX0 ( ( unsigned int ) AT91C_PIO_PB5 ) /* Ethernet MAC Receive Data 0 */ +#define AT91C_PIO_PB6 ( ( unsigned int ) 1 << 6 ) /* Pin Controlled by PB6 */ +#define AT91C_PB6_ERX1 ( ( unsigned int ) AT91C_PIO_PB6 ) /* Ethernet MAC Receive Data 1 */ +#define AT91C_PIO_PB7 ( ( unsigned int ) 1 << 7 ) /* Pin Controlled by PB7 */ +#define AT91C_PB7_ERXER ( ( unsigned int ) AT91C_PIO_PB7 ) /* Ethernet MAC Receive Error */ +#define AT91C_PIO_PB8 ( ( unsigned int ) 1 << 8 ) /* Pin Controlled by PB8 */ +#define AT91C_PB8_EMDC ( ( unsigned int ) AT91C_PIO_PB8 ) /* Ethernet MAC Management Data Clock */ +#define AT91C_PIO_PB9 ( ( unsigned int ) 1 << 9 ) /* Pin Controlled by PB9 */ +#define AT91C_PB9_EMDIO ( ( unsigned int ) AT91C_PIO_PB9 ) /* Ethernet MAC Management Data Input/Output */ + +/* ***************************************************************************** */ +/* PERIPHERAL ID DEFINITIONS FOR AT91SAM7X256 */ +/* ***************************************************************************** */ +#define AT91C_ID_FIQ ( ( unsigned int ) 0 ) /* Advanced Interrupt Controller (FIQ) */ +#define AT91C_ID_SYS ( ( unsigned int ) 1 ) /* System Peripheral */ +#define AT91C_ID_PIOA ( ( unsigned int ) 2 ) /* Parallel IO Controller A */ +#define AT91C_ID_PIOB ( ( unsigned int ) 3 ) /* Parallel IO Controller B */ +#define AT91C_ID_SPI0 ( ( unsigned int ) 4 ) /* Serial Peripheral Interface 0 */ +#define AT91C_ID_SPI1 ( ( unsigned int ) 5 ) /* Serial Peripheral Interface 1 */ +#define AT91C_ID_US0 ( ( unsigned int ) 6 ) /* USART 0 */ +#define AT91C_ID_US1 ( ( unsigned int ) 7 ) /* USART 1 */ +#define AT91C_ID_SSC ( ( unsigned int ) 8 ) /* Serial Synchronous Controller */ +#define AT91C_ID_TWI ( ( unsigned int ) 9 ) /* Two-Wire Interface */ +#define AT91C_ID_PWMC ( ( unsigned int ) 10 ) /* PWM Controller */ +#define AT91C_ID_UDP ( ( unsigned int ) 11 ) /* USB Device Port */ +#define AT91C_ID_TC0 ( ( unsigned int ) 12 ) /* Timer Counter 0 */ +#define AT91C_ID_TC1 ( ( unsigned int ) 13 ) /* Timer Counter 1 */ +#define AT91C_ID_TC2 ( ( unsigned int ) 14 ) /* Timer Counter 2 */ +#define AT91C_ID_CAN ( ( unsigned int ) 15 ) /* Control Area Network Controller */ +#define AT91C_ID_EMAC ( ( unsigned int ) 16 ) /* Ethernet MAC */ +#define AT91C_ID_ADC ( ( unsigned int ) 17 ) /* Analog-to-Digital Converter */ +#define AT91C_ID_AES ( ( unsigned int ) 18 ) /* Advanced Encryption Standard 128-bit */ +#define AT91C_ID_TDES ( ( unsigned int ) 19 ) /* Triple Data Encryption Standard */ +#define AT91C_ID_20_Reserved ( ( unsigned int ) 20 ) /* Reserved */ +#define AT91C_ID_21_Reserved ( ( unsigned int ) 21 ) /* Reserved */ +#define AT91C_ID_22_Reserved ( ( unsigned int ) 22 ) /* Reserved */ +#define AT91C_ID_23_Reserved ( ( unsigned int ) 23 ) /* Reserved */ +#define AT91C_ID_24_Reserved ( ( unsigned int ) 24 ) /* Reserved */ +#define AT91C_ID_25_Reserved ( ( unsigned int ) 25 ) /* Reserved */ +#define AT91C_ID_26_Reserved ( ( unsigned int ) 26 ) /* Reserved */ +#define AT91C_ID_27_Reserved ( ( unsigned int ) 27 ) /* Reserved */ +#define AT91C_ID_28_Reserved ( ( unsigned int ) 28 ) /* Reserved */ +#define AT91C_ID_29_Reserved ( ( unsigned int ) 29 ) /* Reserved */ +#define AT91C_ID_IRQ0 ( ( unsigned int ) 30 ) /* Advanced Interrupt Controller (IRQ0) */ +#define AT91C_ID_IRQ1 ( ( unsigned int ) 31 ) /* Advanced Interrupt Controller (IRQ1) */ + +/* ***************************************************************************** */ +/* BASE ADDRESS DEFINITIONS FOR AT91SAM7X256 */ +/* ***************************************************************************** */ +#define AT91C_BASE_SYS ( ( AT91PS_SYS ) 0xFFFFF000 ) /* (SYS) Base Address */ +#define AT91C_BASE_AIC ( ( AT91PS_AIC ) 0xFFFFF000 ) /* (AIC) Base Address */ +#define AT91C_BASE_PDC_DBGU ( ( AT91PS_PDC ) 0xFFFFF300 ) /* (PDC_DBGU) Base Address */ +#define AT91C_BASE_DBGU ( ( AT91PS_DBGU ) 0xFFFFF200 ) /* (DBGU) Base Address */ +#define AT91C_BASE_PIOA ( ( AT91PS_PIO ) 0xFFFFF400 ) /* (PIOA) Base Address */ +#define AT91C_BASE_PIOB ( ( AT91PS_PIO ) 0xFFFFF600 ) /* (PIOB) Base Address */ +#define AT91C_BASE_CKGR ( ( AT91PS_CKGR ) 0xFFFFFC20 ) /* (CKGR) Base Address */ +#define AT91C_BASE_PMC ( ( AT91PS_PMC ) 0xFFFFFC00 ) /* (PMC) Base Address */ +#define AT91C_BASE_RSTC ( ( AT91PS_RSTC ) 0xFFFFFD00 ) /* (RSTC) Base Address */ +#define AT91C_BASE_RTTC ( ( AT91PS_RTTC ) 0xFFFFFD20 ) /* (RTTC) Base Address */ +#define AT91C_BASE_PITC ( ( AT91PS_PITC ) 0xFFFFFD30 ) /* (PITC) Base Address */ +#define AT91C_BASE_WDTC ( ( AT91PS_WDTC ) 0xFFFFFD40 ) /* (WDTC) Base Address */ +#define AT91C_BASE_VREG ( ( AT91PS_VREG ) 0xFFFFFD60 ) /* (VREG) Base Address */ +#define AT91C_BASE_MC ( ( AT91PS_MC ) 0xFFFFFF00 ) /* (MC) Base Address */ +#define AT91C_BASE_PDC_SPI1 ( ( AT91PS_PDC ) 0xFFFE4100 ) /* (PDC_SPI1) Base Address */ +#define AT91C_BASE_SPI1 ( ( AT91PS_SPI ) 0xFFFE4000 ) /* (SPI1) Base Address */ +#define AT91C_BASE_PDC_SPI0 ( ( AT91PS_PDC ) 0xFFFE0100 ) /* (PDC_SPI0) Base Address */ +#define AT91C_BASE_SPI0 ( ( AT91PS_SPI ) 0xFFFE0000 ) /* (SPI0) Base Address */ +#define AT91C_BASE_PDC_US1 ( ( AT91PS_PDC ) 0xFFFC4100 ) /* (PDC_US1) Base Address */ +#define AT91C_BASE_US1 ( ( AT91PS_USART ) 0xFFFC4000 ) /* (US1) Base Address */ +#define AT91C_BASE_PDC_US0 ( ( AT91PS_PDC ) 0xFFFC0100 ) /* (PDC_US0) Base Address */ +#define AT91C_BASE_US0 ( ( AT91PS_USART ) 0xFFFC0000 ) /* (US0) Base Address */ +#define AT91C_BASE_PDC_SSC ( ( AT91PS_PDC ) 0xFFFD4100 ) /* (PDC_SSC) Base Address */ +#define AT91C_BASE_SSC ( ( AT91PS_SSC ) 0xFFFD4000 ) /* (SSC) Base Address */ +#define AT91C_BASE_TWI ( ( AT91PS_TWI ) 0xFFFB8000 ) /* (TWI) Base Address */ +#define AT91C_BASE_PWMC_CH3 ( ( AT91PS_PWMC_CH ) 0xFFFCC260 ) /* (PWMC_CH3) Base Address */ +#define AT91C_BASE_PWMC_CH2 ( ( AT91PS_PWMC_CH ) 0xFFFCC240 ) /* (PWMC_CH2) Base Address */ +#define AT91C_BASE_PWMC_CH1 ( ( AT91PS_PWMC_CH ) 0xFFFCC220 ) /* (PWMC_CH1) Base Address */ +#define AT91C_BASE_PWMC_CH0 ( ( AT91PS_PWMC_CH ) 0xFFFCC200 ) /* (PWMC_CH0) Base Address */ +#define AT91C_BASE_PWMC ( ( AT91PS_PWMC ) 0xFFFCC000 ) /* (PWMC) Base Address */ +#define AT91C_BASE_UDP ( ( AT91PS_UDP ) 0xFFFB0000 ) /* (UDP) Base Address */ +#define AT91C_BASE_TC0 ( ( AT91PS_TC ) 0xFFFA0000 ) /* (TC0) Base Address */ +#define AT91C_BASE_TC1 ( ( AT91PS_TC ) 0xFFFA0040 ) /* (TC1) Base Address */ +#define AT91C_BASE_TC2 ( ( AT91PS_TC ) 0xFFFA0080 ) /* (TC2) Base Address */ +#define AT91C_BASE_TCB ( ( AT91PS_TCB ) 0xFFFA0000 ) /* (TCB) Base Address */ +#define AT91C_BASE_CAN_MB0 ( ( AT91PS_CAN_MB ) 0xFFFD0200 ) /* (CAN_MB0) Base Address */ +#define AT91C_BASE_CAN_MB1 ( ( AT91PS_CAN_MB ) 0xFFFD0220 ) /* (CAN_MB1) Base Address */ +#define AT91C_BASE_CAN_MB2 ( ( AT91PS_CAN_MB ) 0xFFFD0240 ) /* (CAN_MB2) Base Address */ +#define AT91C_BASE_CAN_MB3 ( ( AT91PS_CAN_MB ) 0xFFFD0260 ) /* (CAN_MB3) Base Address */ +#define AT91C_BASE_CAN_MB4 ( ( AT91PS_CAN_MB ) 0xFFFD0280 ) /* (CAN_MB4) Base Address */ +#define AT91C_BASE_CAN_MB5 ( ( AT91PS_CAN_MB ) 0xFFFD02A0 ) /* (CAN_MB5) Base Address */ +#define AT91C_BASE_CAN_MB6 ( ( AT91PS_CAN_MB ) 0xFFFD02C0 ) /* (CAN_MB6) Base Address */ +#define AT91C_BASE_CAN_MB7 ( ( AT91PS_CAN_MB ) 0xFFFD02E0 ) /* (CAN_MB7) Base Address */ +#define AT91C_BASE_CAN ( ( AT91PS_CAN ) 0xFFFD0000 ) /* (CAN) Base Address */ +#define AT91C_BASE_EMAC ( ( AT91PS_EMAC ) 0xFFFDC000 ) /* (EMAC) Base Address */ +#define AT91C_BASE_PDC_ADC ( ( AT91PS_PDC ) 0xFFFD8100 ) /* (PDC_ADC) Base Address */ +#define AT91C_BASE_ADC ( ( AT91PS_ADC ) 0xFFFD8000 ) /* (ADC) Base Address */ +#define AT91C_BASE_PDC_AES ( ( AT91PS_PDC ) 0xFFFA4100 ) /* (PDC_AES) Base Address */ +#define AT91C_BASE_AES ( ( AT91PS_AES ) 0xFFFA4000 ) /* (AES) Base Address */ +#define AT91C_BASE_PDC_TDES ( ( AT91PS_PDC ) 0xFFFA8100 ) /* (PDC_TDES) Base Address */ +#define AT91C_BASE_TDES ( ( AT91PS_TDES ) 0xFFFA8000 ) /* (TDES) Base Address */ + +/* ***************************************************************************** */ +/* MEMORY MAPPING DEFINITIONS FOR AT91SAM7X256 */ +/* ***************************************************************************** */ +#define AT91C_ISRAM ( ( char * ) 0x00200000 ) /* Internal SRAM base address */ +#define AT91C_ISRAM_SIZE ( ( unsigned int ) 0x00010000 ) /* Internal SRAM size in byte (64 Kbyte) */ +#define AT91C_IFLASH ( ( char * ) 0x00100000 ) /* Internal ROM base address */ +#define AT91C_IFLASH_SIZE ( ( unsigned int ) 0x00040000 ) /* Internal ROM size in byte (256 Kbyte) */ + +#endif /* ifndef AT91SAM7X256_H */ diff --git a/Source/portable/IAR/AtmelSAM7S64/AT91SAM7X256_inc.h b/Source/portable/IAR/AtmelSAM7S64/AT91SAM7X256_inc.h index c85684df6..5c0be5efc 100644 --- a/Source/portable/IAR/AtmelSAM7S64/AT91SAM7X256_inc.h +++ b/Source/portable/IAR/AtmelSAM7S64/AT91SAM7X256_inc.h @@ -1,2444 +1,2444 @@ -// ---------------------------------------------------------------------------- -// ATMEL Microcontroller Software Support - ROUSSET - -// ---------------------------------------------------------------------------- -// DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR -// IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF -// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE -// DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, -// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, -// OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF -// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING -// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, -// EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// ---------------------------------------------------------------------------- -// File Name : AT91SAM7X256.h -// Object : AT91SAM7X256 definitions -// Generated : AT91 SW Application Group 05/20/2005 (16:22:29) -// -// CVS Reference : /AT91SAM7X256.pl/1.11/Tue May 10 12:15:32 2005// -// CVS Reference : /SYS_SAM7X.pl/1.3/Tue Feb 1 17:01:43 2005// -// CVS Reference : /MC_SAM7X.pl/1.2/Fri May 20 14:13:04 2005// -// CVS Reference : /PMC_SAM7X.pl/1.4/Tue Feb 8 13:58:10 2005// -// CVS Reference : /RSTC_SAM7X.pl/1.1/Tue Feb 1 16:16:26 2005// -// CVS Reference : /UDP_SAM7X.pl/1.1/Tue May 10 11:35:35 2005// -// CVS Reference : /PWM_SAM7X.pl/1.1/Tue May 10 11:53:07 2005// -// CVS Reference : /AIC_6075B.pl/1.3/Fri May 20 14:01:30 2005// -// CVS Reference : /PIO_6057A.pl/1.2/Thu Feb 3 10:18:28 2005// -// CVS Reference : /RTTC_6081A.pl/1.2/Tue Nov 9 14:43:58 2004// -// CVS Reference : /PITC_6079A.pl/1.2/Tue Nov 9 14:43:56 2004// -// CVS Reference : /WDTC_6080A.pl/1.3/Tue Nov 9 14:44:00 2004// -// CVS Reference : /VREG_6085B.pl/1.1/Tue Feb 1 16:05:48 2005// -// CVS Reference : /PDC_6074C.pl/1.2/Thu Feb 3 08:48:54 2005// -// CVS Reference : /DBGU_6059D.pl/1.1/Mon Jan 31 13:15:32 2005// -// CVS Reference : /SPI_6088D.pl/1.3/Fri May 20 14:08:59 2005// -// CVS Reference : /US_6089C.pl/1.1/Mon Jul 12 18:23:26 2004// -// CVS Reference : /SSC_6078A.pl/1.1/Tue Jul 13 07:45:40 2004// -// CVS Reference : /TWI_6061A.pl/1.1/Tue Jul 13 07:38:06 2004// -// CVS Reference : /TC_6082A.pl/1.7/Fri Mar 11 12:52:17 2005// -// CVS Reference : /CAN_6019B.pl/1.1/Tue Mar 8 12:42:22 2005// -// CVS Reference : /EMACB_6119A.pl/1.5/Thu Feb 3 15:52:04 2005// -// CVS Reference : /ADC_6051C.pl/1.1/Fri Oct 17 09:12:38 2003// -// CVS Reference : /AES_6149A.pl/1.10/Mon Feb 7 09:44:25 2005// -// CVS Reference : /DES3_6150A.pl/1.1/Mon Jan 17 08:34:31 2005// -// ---------------------------------------------------------------------------- +/* ---------------------------------------------------------------------------- */ +/* ATMEL Microcontroller Software Support - ROUSSET - */ +/* ---------------------------------------------------------------------------- */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ +/* File Name : AT91SAM7X256.h */ +/* Object : AT91SAM7X256 definitions */ +/* Generated : AT91 SW Application Group 05/20/2005 (16:22:29) */ +/* */ +/* CVS Reference : /AT91SAM7X256.pl/1.11/Tue May 10 12:15:32 2005// */ +/* CVS Reference : /SYS_SAM7X.pl/1.3/Tue Feb 1 17:01:43 2005// */ +/* CVS Reference : /MC_SAM7X.pl/1.2/Fri May 20 14:13:04 2005// */ +/* CVS Reference : /PMC_SAM7X.pl/1.4/Tue Feb 8 13:58:10 2005// */ +/* CVS Reference : /RSTC_SAM7X.pl/1.1/Tue Feb 1 16:16:26 2005// */ +/* CVS Reference : /UDP_SAM7X.pl/1.1/Tue May 10 11:35:35 2005// */ +/* CVS Reference : /PWM_SAM7X.pl/1.1/Tue May 10 11:53:07 2005// */ +/* CVS Reference : /AIC_6075B.pl/1.3/Fri May 20 14:01:30 2005// */ +/* CVS Reference : /PIO_6057A.pl/1.2/Thu Feb 3 10:18:28 2005// */ +/* CVS Reference : /RTTC_6081A.pl/1.2/Tue Nov 9 14:43:58 2004// */ +/* CVS Reference : /PITC_6079A.pl/1.2/Tue Nov 9 14:43:56 2004// */ +/* CVS Reference : /WDTC_6080A.pl/1.3/Tue Nov 9 14:44:00 2004// */ +/* CVS Reference : /VREG_6085B.pl/1.1/Tue Feb 1 16:05:48 2005// */ +/* CVS Reference : /PDC_6074C.pl/1.2/Thu Feb 3 08:48:54 2005// */ +/* CVS Reference : /DBGU_6059D.pl/1.1/Mon Jan 31 13:15:32 2005// */ +/* CVS Reference : /SPI_6088D.pl/1.3/Fri May 20 14:08:59 2005// */ +/* CVS Reference : /US_6089C.pl/1.1/Mon Jul 12 18:23:26 2004// */ +/* CVS Reference : /SSC_6078A.pl/1.1/Tue Jul 13 07:45:40 2004// */ +/* CVS Reference : /TWI_6061A.pl/1.1/Tue Jul 13 07:38:06 2004// */ +/* CVS Reference : /TC_6082A.pl/1.7/Fri Mar 11 12:52:17 2005// */ +/* CVS Reference : /CAN_6019B.pl/1.1/Tue Mar 8 12:42:22 2005// */ +/* CVS Reference : /EMACB_6119A.pl/1.5/Thu Feb 3 15:52:04 2005// */ +/* CVS Reference : /ADC_6051C.pl/1.1/Fri Oct 17 09:12:38 2003// */ +/* CVS Reference : /AES_6149A.pl/1.10/Mon Feb 7 09:44:25 2005// */ +/* CVS Reference : /DES3_6150A.pl/1.1/Mon Jan 17 08:34:31 2005// */ +/* ---------------------------------------------------------------------------- */ -// Hardware register definition +/* Hardware register definition */ -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR System Peripherals -// ***************************************************************************** +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR System Peripherals */ +/* ***************************************************************************** */ -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Advanced Interrupt Controller -// ***************************************************************************** -// *** Register offset in AT91S_AIC structure *** -#define AIC_SMR ( 0) // Source Mode Register -#define AIC_SVR (128) // Source Vector Register -#define AIC_IVR (256) // IRQ Vector Register -#define AIC_FVR (260) // FIQ Vector Register -#define AIC_ISR (264) // Interrupt Status Register -#define AIC_IPR (268) // Interrupt Pending Register -#define AIC_IMR (272) // Interrupt Mask Register -#define AIC_CISR (276) // Core Interrupt Status Register -#define AIC_IECR (288) // Interrupt Enable Command Register -#define AIC_IDCR (292) // Interrupt Disable Command Register -#define AIC_ICCR (296) // Interrupt Clear Command Register -#define AIC_ISCR (300) // Interrupt Set Command Register -#define AIC_EOICR (304) // End of Interrupt Command Register -#define AIC_SPU (308) // Spurious Vector Register -#define AIC_DCR (312) // Debug Control Register (Protect) -#define AIC_FFER (320) // Fast Forcing Enable Register -#define AIC_FFDR (324) // Fast Forcing Disable Register -#define AIC_FFSR (328) // Fast Forcing Status Register -// -------- AIC_SMR : (AIC Offset: 0x0) Control Register -------- -#define AT91C_AIC_PRIOR (0x7 << 0) // (AIC) Priority Level -#define AT91C_AIC_PRIOR_LOWEST (0x0) // (AIC) Lowest priority level -#define AT91C_AIC_PRIOR_HIGHEST (0x7) // (AIC) Highest priority level -#define AT91C_AIC_SRCTYPE (0x3 << 5) // (AIC) Interrupt Source Type -#define AT91C_AIC_SRCTYPE_INT_HIGH_LEVEL (0x0 << 5) // (AIC) Internal Sources Code Label High-level Sensitive -#define AT91C_AIC_SRCTYPE_EXT_LOW_LEVEL (0x0 << 5) // (AIC) External Sources Code Label Low-level Sensitive -#define AT91C_AIC_SRCTYPE_INT_POSITIVE_EDGE (0x1 << 5) // (AIC) Internal Sources Code Label Positive Edge triggered -#define AT91C_AIC_SRCTYPE_EXT_NEGATIVE_EDGE (0x1 << 5) // (AIC) External Sources Code Label Negative Edge triggered -#define AT91C_AIC_SRCTYPE_HIGH_LEVEL (0x2 << 5) // (AIC) Internal Or External Sources Code Label High-level Sensitive -#define AT91C_AIC_SRCTYPE_POSITIVE_EDGE (0x3 << 5) // (AIC) Internal Or External Sources Code Label Positive Edge triggered -// -------- AIC_CISR : (AIC Offset: 0x114) AIC Core Interrupt Status Register -------- -#define AT91C_AIC_NFIQ (0x1 << 0) // (AIC) NFIQ Status -#define AT91C_AIC_NIRQ (0x1 << 1) // (AIC) NIRQ Status -// -------- AIC_DCR : (AIC Offset: 0x138) AIC Debug Control Register (Protect) -------- -#define AT91C_AIC_DCR_PROT (0x1 << 0) // (AIC) Protection Mode -#define AT91C_AIC_DCR_GMSK (0x1 << 1) // (AIC) General Mask +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR Advanced Interrupt Controller */ +/* ***************************************************************************** */ +/* *** Register offset in AT91S_AIC structure *** */ +#define AIC_SMR ( 0 ) /* Source Mode Register */ +#define AIC_SVR ( 128 ) /* Source Vector Register */ +#define AIC_IVR ( 256 ) /* IRQ Vector Register */ +#define AIC_FVR ( 260 ) /* FIQ Vector Register */ +#define AIC_ISR ( 264 ) /* Interrupt Status Register */ +#define AIC_IPR ( 268 ) /* Interrupt Pending Register */ +#define AIC_IMR ( 272 ) /* Interrupt Mask Register */ +#define AIC_CISR ( 276 ) /* Core Interrupt Status Register */ +#define AIC_IECR ( 288 ) /* Interrupt Enable Command Register */ +#define AIC_IDCR ( 292 ) /* Interrupt Disable Command Register */ +#define AIC_ICCR ( 296 ) /* Interrupt Clear Command Register */ +#define AIC_ISCR ( 300 ) /* Interrupt Set Command Register */ +#define AIC_EOICR ( 304 ) /* End of Interrupt Command Register */ +#define AIC_SPU ( 308 ) /* Spurious Vector Register */ +#define AIC_DCR ( 312 ) /* Debug Control Register (Protect) */ +#define AIC_FFER ( 320 ) /* Fast Forcing Enable Register */ +#define AIC_FFDR ( 324 ) /* Fast Forcing Disable Register */ +#define AIC_FFSR ( 328 ) /* Fast Forcing Status Register */ +/* -------- AIC_SMR : (AIC Offset: 0x0) Control Register -------- */ +#define AT91C_AIC_PRIOR ( 0x7 << 0 ) /* (AIC) Priority Level */ +#define AT91C_AIC_PRIOR_LOWEST ( 0x0 ) /* (AIC) Lowest priority level */ +#define AT91C_AIC_PRIOR_HIGHEST ( 0x7 ) /* (AIC) Highest priority level */ +#define AT91C_AIC_SRCTYPE ( 0x3 << 5 ) /* (AIC) Interrupt Source Type */ +#define AT91C_AIC_SRCTYPE_INT_HIGH_LEVEL ( 0x0 << 5 ) /* (AIC) Internal Sources Code Label High-level Sensitive */ +#define AT91C_AIC_SRCTYPE_EXT_LOW_LEVEL ( 0x0 << 5 ) /* (AIC) External Sources Code Label Low-level Sensitive */ +#define AT91C_AIC_SRCTYPE_INT_POSITIVE_EDGE ( 0x1 << 5 ) /* (AIC) Internal Sources Code Label Positive Edge triggered */ +#define AT91C_AIC_SRCTYPE_EXT_NEGATIVE_EDGE ( 0x1 << 5 ) /* (AIC) External Sources Code Label Negative Edge triggered */ +#define AT91C_AIC_SRCTYPE_HIGH_LEVEL ( 0x2 << 5 ) /* (AIC) Internal Or External Sources Code Label High-level Sensitive */ +#define AT91C_AIC_SRCTYPE_POSITIVE_EDGE ( 0x3 << 5 ) /* (AIC) Internal Or External Sources Code Label Positive Edge triggered */ +/* -------- AIC_CISR : (AIC Offset: 0x114) AIC Core Interrupt Status Register -------- */ +#define AT91C_AIC_NFIQ ( 0x1 << 0 ) /* (AIC) NFIQ Status */ +#define AT91C_AIC_NIRQ ( 0x1 << 1 ) /* (AIC) NIRQ Status */ +/* -------- AIC_DCR : (AIC Offset: 0x138) AIC Debug Control Register (Protect) -------- */ +#define AT91C_AIC_DCR_PROT ( 0x1 << 0 ) /* (AIC) Protection Mode */ +#define AT91C_AIC_DCR_GMSK ( 0x1 << 1 ) /* (AIC) General Mask */ -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Peripheral DMA Controller -// ***************************************************************************** -// *** Register offset in AT91S_PDC structure *** -#define PDC_RPR ( 0) // Receive Pointer Register -#define PDC_RCR ( 4) // Receive Counter Register -#define PDC_TPR ( 8) // Transmit Pointer Register -#define PDC_TCR (12) // Transmit Counter Register -#define PDC_RNPR (16) // Receive Next Pointer Register -#define PDC_RNCR (20) // Receive Next Counter Register -#define PDC_TNPR (24) // Transmit Next Pointer Register -#define PDC_TNCR (28) // Transmit Next Counter Register -#define PDC_PTCR (32) // PDC Transfer Control Register -#define PDC_PTSR (36) // PDC Transfer Status Register -// -------- PDC_PTCR : (PDC Offset: 0x20) PDC Transfer Control Register -------- -#define AT91C_PDC_RXTEN (0x1 << 0) // (PDC) Receiver Transfer Enable -#define AT91C_PDC_RXTDIS (0x1 << 1) // (PDC) Receiver Transfer Disable -#define AT91C_PDC_TXTEN (0x1 << 8) // (PDC) Transmitter Transfer Enable -#define AT91C_PDC_TXTDIS (0x1 << 9) // (PDC) Transmitter Transfer Disable -// -------- PDC_PTSR : (PDC Offset: 0x24) PDC Transfer Status Register -------- +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR Peripheral DMA Controller */ +/* ***************************************************************************** */ +/* *** Register offset in AT91S_PDC structure *** */ +#define PDC_RPR ( 0 ) /* Receive Pointer Register */ +#define PDC_RCR ( 4 ) /* Receive Counter Register */ +#define PDC_TPR ( 8 ) /* Transmit Pointer Register */ +#define PDC_TCR ( 12 ) /* Transmit Counter Register */ +#define PDC_RNPR ( 16 ) /* Receive Next Pointer Register */ +#define PDC_RNCR ( 20 ) /* Receive Next Counter Register */ +#define PDC_TNPR ( 24 ) /* Transmit Next Pointer Register */ +#define PDC_TNCR ( 28 ) /* Transmit Next Counter Register */ +#define PDC_PTCR ( 32 ) /* PDC Transfer Control Register */ +#define PDC_PTSR ( 36 ) /* PDC Transfer Status Register */ +/* -------- PDC_PTCR : (PDC Offset: 0x20) PDC Transfer Control Register -------- */ +#define AT91C_PDC_RXTEN ( 0x1 << 0 ) /* (PDC) Receiver Transfer Enable */ +#define AT91C_PDC_RXTDIS ( 0x1 << 1 ) /* (PDC) Receiver Transfer Disable */ +#define AT91C_PDC_TXTEN ( 0x1 << 8 ) /* (PDC) Transmitter Transfer Enable */ +#define AT91C_PDC_TXTDIS ( 0x1 << 9 ) /* (PDC) Transmitter Transfer Disable */ +/* -------- PDC_PTSR : (PDC Offset: 0x24) PDC Transfer Status Register -------- */ -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Debug Unit -// ***************************************************************************** -// *** Register offset in AT91S_DBGU structure *** -#define DBGU_CR ( 0) // Control Register -#define DBGU_MR ( 4) // Mode Register -#define DBGU_IER ( 8) // Interrupt Enable Register -#define DBGU_IDR (12) // Interrupt Disable Register -#define DBGU_IMR (16) // Interrupt Mask Register -#define DBGU_CSR (20) // Channel Status Register -#define DBGU_RHR (24) // Receiver Holding Register -#define DBGU_THR (28) // Transmitter Holding Register -#define DBGU_BRGR (32) // Baud Rate Generator Register -#define DBGU_CIDR (64) // Chip ID Register -#define DBGU_EXID (68) // Chip ID Extension Register -#define DBGU_FNTR (72) // Force NTRST Register -#define DBGU_RPR (256) // Receive Pointer Register -#define DBGU_RCR (260) // Receive Counter Register -#define DBGU_TPR (264) // Transmit Pointer Register -#define DBGU_TCR (268) // Transmit Counter Register -#define DBGU_RNPR (272) // Receive Next Pointer Register -#define DBGU_RNCR (276) // Receive Next Counter Register -#define DBGU_TNPR (280) // Transmit Next Pointer Register -#define DBGU_TNCR (284) // Transmit Next Counter Register -#define DBGU_PTCR (288) // PDC Transfer Control Register -#define DBGU_PTSR (292) // PDC Transfer Status Register -// -------- DBGU_CR : (DBGU Offset: 0x0) Debug Unit Control Register -------- -#define AT91C_US_RSTRX (0x1 << 2) // (DBGU) Reset Receiver -#define AT91C_US_RSTTX (0x1 << 3) // (DBGU) Reset Transmitter -#define AT91C_US_RXEN (0x1 << 4) // (DBGU) Receiver Enable -#define AT91C_US_RXDIS (0x1 << 5) // (DBGU) Receiver Disable -#define AT91C_US_TXEN (0x1 << 6) // (DBGU) Transmitter Enable -#define AT91C_US_TXDIS (0x1 << 7) // (DBGU) Transmitter Disable -#define AT91C_US_RSTSTA (0x1 << 8) // (DBGU) Reset Status Bits -// -------- DBGU_MR : (DBGU Offset: 0x4) Debug Unit Mode Register -------- -#define AT91C_US_PAR (0x7 << 9) // (DBGU) Parity type -#define AT91C_US_PAR_EVEN (0x0 << 9) // (DBGU) Even Parity -#define AT91C_US_PAR_ODD (0x1 << 9) // (DBGU) Odd Parity -#define AT91C_US_PAR_SPACE (0x2 << 9) // (DBGU) Parity forced to 0 (Space) -#define AT91C_US_PAR_MARK (0x3 << 9) // (DBGU) Parity forced to 1 (Mark) -#define AT91C_US_PAR_NONE (0x4 << 9) // (DBGU) No Parity -#define AT91C_US_PAR_MULTI_DROP (0x6 << 9) // (DBGU) Multi-drop mode -#define AT91C_US_CHMODE (0x3 << 14) // (DBGU) Channel Mode -#define AT91C_US_CHMODE_NORMAL (0x0 << 14) // (DBGU) Normal Mode: The USART channel operates as an RX/TX USART. -#define AT91C_US_CHMODE_AUTO (0x1 << 14) // (DBGU) Automatic Echo: Receiver Data Input is connected to the TXD pin. -#define AT91C_US_CHMODE_LOCAL (0x2 << 14) // (DBGU) Local Loopback: Transmitter Output Signal is connected to Receiver Input Signal. -#define AT91C_US_CHMODE_REMOTE (0x3 << 14) // (DBGU) Remote Loopback: RXD pin is internally connected to TXD pin. -// -------- DBGU_IER : (DBGU Offset: 0x8) Debug Unit Interrupt Enable Register -------- -#define AT91C_US_RXRDY (0x1 << 0) // (DBGU) RXRDY Interrupt -#define AT91C_US_TXRDY (0x1 << 1) // (DBGU) TXRDY Interrupt -#define AT91C_US_ENDRX (0x1 << 3) // (DBGU) End of Receive Transfer Interrupt -#define AT91C_US_ENDTX (0x1 << 4) // (DBGU) End of Transmit Interrupt -#define AT91C_US_OVRE (0x1 << 5) // (DBGU) Overrun Interrupt -#define AT91C_US_FRAME (0x1 << 6) // (DBGU) Framing Error Interrupt -#define AT91C_US_PARE (0x1 << 7) // (DBGU) Parity Error Interrupt -#define AT91C_US_TXEMPTY (0x1 << 9) // (DBGU) TXEMPTY Interrupt -#define AT91C_US_TXBUFE (0x1 << 11) // (DBGU) TXBUFE Interrupt -#define AT91C_US_RXBUFF (0x1 << 12) // (DBGU) RXBUFF Interrupt -#define AT91C_US_COMM_TX (0x1 << 30) // (DBGU) COMM_TX Interrupt -#define AT91C_US_COMM_RX (0x1 << 31) // (DBGU) COMM_RX Interrupt -// -------- DBGU_IDR : (DBGU Offset: 0xc) Debug Unit Interrupt Disable Register -------- -// -------- DBGU_IMR : (DBGU Offset: 0x10) Debug Unit Interrupt Mask Register -------- -// -------- DBGU_CSR : (DBGU Offset: 0x14) Debug Unit Channel Status Register -------- -// -------- DBGU_FNTR : (DBGU Offset: 0x48) Debug Unit FORCE_NTRST Register -------- -#define AT91C_US_FORCE_NTRST (0x1 << 0) // (DBGU) Force NTRST in JTAG +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR Debug Unit */ +/* ***************************************************************************** */ +/* *** Register offset in AT91S_DBGU structure *** */ +#define DBGU_CR ( 0 ) /* Control Register */ +#define DBGU_MR ( 4 ) /* Mode Register */ +#define DBGU_IER ( 8 ) /* Interrupt Enable Register */ +#define DBGU_IDR ( 12 ) /* Interrupt Disable Register */ +#define DBGU_IMR ( 16 ) /* Interrupt Mask Register */ +#define DBGU_CSR ( 20 ) /* Channel Status Register */ +#define DBGU_RHR ( 24 ) /* Receiver Holding Register */ +#define DBGU_THR ( 28 ) /* Transmitter Holding Register */ +#define DBGU_BRGR ( 32 ) /* Baud Rate Generator Register */ +#define DBGU_CIDR ( 64 ) /* Chip ID Register */ +#define DBGU_EXID ( 68 ) /* Chip ID Extension Register */ +#define DBGU_FNTR ( 72 ) /* Force NTRST Register */ +#define DBGU_RPR ( 256 ) /* Receive Pointer Register */ +#define DBGU_RCR ( 260 ) /* Receive Counter Register */ +#define DBGU_TPR ( 264 ) /* Transmit Pointer Register */ +#define DBGU_TCR ( 268 ) /* Transmit Counter Register */ +#define DBGU_RNPR ( 272 ) /* Receive Next Pointer Register */ +#define DBGU_RNCR ( 276 ) /* Receive Next Counter Register */ +#define DBGU_TNPR ( 280 ) /* Transmit Next Pointer Register */ +#define DBGU_TNCR ( 284 ) /* Transmit Next Counter Register */ +#define DBGU_PTCR ( 288 ) /* PDC Transfer Control Register */ +#define DBGU_PTSR ( 292 ) /* PDC Transfer Status Register */ +/* -------- DBGU_CR : (DBGU Offset: 0x0) Debug Unit Control Register -------- */ +#define AT91C_US_RSTRX ( 0x1 << 2 ) /* (DBGU) Reset Receiver */ +#define AT91C_US_RSTTX ( 0x1 << 3 ) /* (DBGU) Reset Transmitter */ +#define AT91C_US_RXEN ( 0x1 << 4 ) /* (DBGU) Receiver Enable */ +#define AT91C_US_RXDIS ( 0x1 << 5 ) /* (DBGU) Receiver Disable */ +#define AT91C_US_TXEN ( 0x1 << 6 ) /* (DBGU) Transmitter Enable */ +#define AT91C_US_TXDIS ( 0x1 << 7 ) /* (DBGU) Transmitter Disable */ +#define AT91C_US_RSTSTA ( 0x1 << 8 ) /* (DBGU) Reset Status Bits */ +/* -------- DBGU_MR : (DBGU Offset: 0x4) Debug Unit Mode Register -------- */ +#define AT91C_US_PAR ( 0x7 << 9 ) /* (DBGU) Parity type */ +#define AT91C_US_PAR_EVEN ( 0x0 << 9 ) /* (DBGU) Even Parity */ +#define AT91C_US_PAR_ODD ( 0x1 << 9 ) /* (DBGU) Odd Parity */ +#define AT91C_US_PAR_SPACE ( 0x2 << 9 ) /* (DBGU) Parity forced to 0 (Space) */ +#define AT91C_US_PAR_MARK ( 0x3 << 9 ) /* (DBGU) Parity forced to 1 (Mark) */ +#define AT91C_US_PAR_NONE ( 0x4 << 9 ) /* (DBGU) No Parity */ +#define AT91C_US_PAR_MULTI_DROP ( 0x6 << 9 ) /* (DBGU) Multi-drop mode */ +#define AT91C_US_CHMODE ( 0x3 << 14 ) /* (DBGU) Channel Mode */ +#define AT91C_US_CHMODE_NORMAL ( 0x0 << 14 ) /* (DBGU) Normal Mode: The USART channel operates as an RX/TX USART. */ +#define AT91C_US_CHMODE_AUTO ( 0x1 << 14 ) /* (DBGU) Automatic Echo: Receiver Data Input is connected to the TXD pin. */ +#define AT91C_US_CHMODE_LOCAL ( 0x2 << 14 ) /* (DBGU) Local Loopback: Transmitter Output Signal is connected to Receiver Input Signal. */ +#define AT91C_US_CHMODE_REMOTE ( 0x3 << 14 ) /* (DBGU) Remote Loopback: RXD pin is internally connected to TXD pin. */ +/* -------- DBGU_IER : (DBGU Offset: 0x8) Debug Unit Interrupt Enable Register -------- */ +#define AT91C_US_RXRDY ( 0x1 << 0 ) /* (DBGU) RXRDY Interrupt */ +#define AT91C_US_TXRDY ( 0x1 << 1 ) /* (DBGU) TXRDY Interrupt */ +#define AT91C_US_ENDRX ( 0x1 << 3 ) /* (DBGU) End of Receive Transfer Interrupt */ +#define AT91C_US_ENDTX ( 0x1 << 4 ) /* (DBGU) End of Transmit Interrupt */ +#define AT91C_US_OVRE ( 0x1 << 5 ) /* (DBGU) Overrun Interrupt */ +#define AT91C_US_FRAME ( 0x1 << 6 ) /* (DBGU) Framing Error Interrupt */ +#define AT91C_US_PARE ( 0x1 << 7 ) /* (DBGU) Parity Error Interrupt */ +#define AT91C_US_TXEMPTY ( 0x1 << 9 ) /* (DBGU) TXEMPTY Interrupt */ +#define AT91C_US_TXBUFE ( 0x1 << 11 ) /* (DBGU) TXBUFE Interrupt */ +#define AT91C_US_RXBUFF ( 0x1 << 12 ) /* (DBGU) RXBUFF Interrupt */ +#define AT91C_US_COMM_TX ( 0x1 << 30 ) /* (DBGU) COMM_TX Interrupt */ +#define AT91C_US_COMM_RX ( 0x1 << 31 ) /* (DBGU) COMM_RX Interrupt */ +/* -------- DBGU_IDR : (DBGU Offset: 0xc) Debug Unit Interrupt Disable Register -------- */ +/* -------- DBGU_IMR : (DBGU Offset: 0x10) Debug Unit Interrupt Mask Register -------- */ +/* -------- DBGU_CSR : (DBGU Offset: 0x14) Debug Unit Channel Status Register -------- */ +/* -------- DBGU_FNTR : (DBGU Offset: 0x48) Debug Unit FORCE_NTRST Register -------- */ +#define AT91C_US_FORCE_NTRST ( 0x1 << 0 ) /* (DBGU) Force NTRST in JTAG */ -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Parallel Input Output Controler -// ***************************************************************************** -// *** Register offset in AT91S_PIO structure *** -#define PIO_PER ( 0) // PIO Enable Register -#define PIO_PDR ( 4) // PIO Disable Register -#define PIO_PSR ( 8) // PIO Status Register -#define PIO_OER (16) // Output Enable Register -#define PIO_ODR (20) // Output Disable Registerr -#define PIO_OSR (24) // Output Status Register -#define PIO_IFER (32) // Input Filter Enable Register -#define PIO_IFDR (36) // Input Filter Disable Register -#define PIO_IFSR (40) // Input Filter Status Register -#define PIO_SODR (48) // Set Output Data Register -#define PIO_CODR (52) // Clear Output Data Register -#define PIO_ODSR (56) // Output Data Status Register -#define PIO_PDSR (60) // Pin Data Status Register -#define PIO_IER (64) // Interrupt Enable Register -#define PIO_IDR (68) // Interrupt Disable Register -#define PIO_IMR (72) // Interrupt Mask Register -#define PIO_ISR (76) // Interrupt Status Register -#define PIO_MDER (80) // Multi-driver Enable Register -#define PIO_MDDR (84) // Multi-driver Disable Register -#define PIO_MDSR (88) // Multi-driver Status Register -#define PIO_PPUDR (96) // Pull-up Disable Register -#define PIO_PPUER (100) // Pull-up Enable Register -#define PIO_PPUSR (104) // Pull-up Status Register -#define PIO_ASR (112) // Select A Register -#define PIO_BSR (116) // Select B Register -#define PIO_ABSR (120) // AB Select Status Register -#define PIO_OWER (160) // Output Write Enable Register -#define PIO_OWDR (164) // Output Write Disable Register -#define PIO_OWSR (168) // Output Write Status Register +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR Parallel Input Output Controller */ +/* ***************************************************************************** */ +/* *** Register offset in AT91S_PIO structure *** */ +#define PIO_PER ( 0 ) /* PIO Enable Register */ +#define PIO_PDR ( 4 ) /* PIO Disable Register */ +#define PIO_PSR ( 8 ) /* PIO Status Register */ +#define PIO_OER ( 16 ) /* Output Enable Register */ +#define PIO_ODR ( 20 ) /* Output Disable Registerr */ +#define PIO_OSR ( 24 ) /* Output Status Register */ +#define PIO_IFER ( 32 ) /* Input Filter Enable Register */ +#define PIO_IFDR ( 36 ) /* Input Filter Disable Register */ +#define PIO_IFSR ( 40 ) /* Input Filter Status Register */ +#define PIO_SODR ( 48 ) /* Set Output Data Register */ +#define PIO_CODR ( 52 ) /* Clear Output Data Register */ +#define PIO_ODSR ( 56 ) /* Output Data Status Register */ +#define PIO_PDSR ( 60 ) /* Pin Data Status Register */ +#define PIO_IER ( 64 ) /* Interrupt Enable Register */ +#define PIO_IDR ( 68 ) /* Interrupt Disable Register */ +#define PIO_IMR ( 72 ) /* Interrupt Mask Register */ +#define PIO_ISR ( 76 ) /* Interrupt Status Register */ +#define PIO_MDER ( 80 ) /* Multi-driver Enable Register */ +#define PIO_MDDR ( 84 ) /* Multi-driver Disable Register */ +#define PIO_MDSR ( 88 ) /* Multi-driver Status Register */ +#define PIO_PPUDR ( 96 ) /* Pull-up Disable Register */ +#define PIO_PPUER ( 100 ) /* Pull-up Enable Register */ +#define PIO_PPUSR ( 104 ) /* Pull-up Status Register */ +#define PIO_ASR ( 112 ) /* Select A Register */ +#define PIO_BSR ( 116 ) /* Select B Register */ +#define PIO_ABSR ( 120 ) /* AB Select Status Register */ +#define PIO_OWER ( 160 ) /* Output Write Enable Register */ +#define PIO_OWDR ( 164 ) /* Output Write Disable Register */ +#define PIO_OWSR ( 168 ) /* Output Write Status Register */ -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Clock Generator Controler -// ***************************************************************************** -// *** Register offset in AT91S_CKGR structure *** -#define CKGR_MOR ( 0) // Main Oscillator Register -#define CKGR_MCFR ( 4) // Main Clock Frequency Register -#define CKGR_PLLR (12) // PLL Register -// -------- CKGR_MOR : (CKGR Offset: 0x0) Main Oscillator Register -------- -#define AT91C_CKGR_MOSCEN (0x1 << 0) // (CKGR) Main Oscillator Enable -#define AT91C_CKGR_OSCBYPASS (0x1 << 1) // (CKGR) Main Oscillator Bypass -#define AT91C_CKGR_OSCOUNT (0xFF << 8) // (CKGR) Main Oscillator Start-up Time -// -------- CKGR_MCFR : (CKGR Offset: 0x4) Main Clock Frequency Register -------- -#define AT91C_CKGR_MAINF (0xFFFF << 0) // (CKGR) Main Clock Frequency -#define AT91C_CKGR_MAINRDY (0x1 << 16) // (CKGR) Main Clock Ready -// -------- CKGR_PLLR : (CKGR Offset: 0xc) PLL B Register -------- -#define AT91C_CKGR_DIV (0xFF << 0) // (CKGR) Divider Selected -#define AT91C_CKGR_DIV_0 (0x0) // (CKGR) Divider output is 0 -#define AT91C_CKGR_DIV_BYPASS (0x1) // (CKGR) Divider is bypassed -#define AT91C_CKGR_PLLCOUNT (0x3F << 8) // (CKGR) PLL Counter -#define AT91C_CKGR_OUT (0x3 << 14) // (CKGR) PLL Output Frequency Range -#define AT91C_CKGR_OUT_0 (0x0 << 14) // (CKGR) Please refer to the PLL datasheet -#define AT91C_CKGR_OUT_1 (0x1 << 14) // (CKGR) Please refer to the PLL datasheet -#define AT91C_CKGR_OUT_2 (0x2 << 14) // (CKGR) Please refer to the PLL datasheet -#define AT91C_CKGR_OUT_3 (0x3 << 14) // (CKGR) Please refer to the PLL datasheet -#define AT91C_CKGR_MUL (0x7FF << 16) // (CKGR) PLL Multiplier -#define AT91C_CKGR_USBDIV (0x3 << 28) // (CKGR) Divider for USB Clocks -#define AT91C_CKGR_USBDIV_0 (0x0 << 28) // (CKGR) Divider output is PLL clock output -#define AT91C_CKGR_USBDIV_1 (0x1 << 28) // (CKGR) Divider output is PLL clock output divided by 2 -#define AT91C_CKGR_USBDIV_2 (0x2 << 28) // (CKGR) Divider output is PLL clock output divided by 4 +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR Clock Generator Controller */ +/* ***************************************************************************** */ +/* *** Register offset in AT91S_CKGR structure *** */ +#define CKGR_MOR ( 0 ) /* Main Oscillator Register */ +#define CKGR_MCFR ( 4 ) /* Main Clock Frequency Register */ +#define CKGR_PLLR ( 12 ) /* PLL Register */ +/* -------- CKGR_MOR : (CKGR Offset: 0x0) Main Oscillator Register -------- */ +#define AT91C_CKGR_MOSCEN ( 0x1 << 0 ) /* (CKGR) Main Oscillator Enable */ +#define AT91C_CKGR_OSCBYPASS ( 0x1 << 1 ) /* (CKGR) Main Oscillator Bypass */ +#define AT91C_CKGR_OSCOUNT ( 0xFF << 8 ) /* (CKGR) Main Oscillator Start-up Time */ +/* -------- CKGR_MCFR : (CKGR Offset: 0x4) Main Clock Frequency Register -------- */ +#define AT91C_CKGR_MAINF ( 0xFFFF << 0 ) /* (CKGR) Main Clock Frequency */ +#define AT91C_CKGR_MAINRDY ( 0x1 << 16 ) /* (CKGR) Main Clock Ready */ +/* -------- CKGR_PLLR : (CKGR Offset: 0xc) PLL B Register -------- */ +#define AT91C_CKGR_DIV ( 0xFF << 0 ) /* (CKGR) Divider Selected */ +#define AT91C_CKGR_DIV_0 ( 0x0 ) /* (CKGR) Divider output is 0 */ +#define AT91C_CKGR_DIV_BYPASS ( 0x1 ) /* (CKGR) Divider is bypassed */ +#define AT91C_CKGR_PLLCOUNT ( 0x3F << 8 ) /* (CKGR) PLL Counter */ +#define AT91C_CKGR_OUT ( 0x3 << 14 ) /* (CKGR) PLL Output Frequency Range */ +#define AT91C_CKGR_OUT_0 ( 0x0 << 14 ) /* (CKGR) Please refer to the PLL datasheet */ +#define AT91C_CKGR_OUT_1 ( 0x1 << 14 ) /* (CKGR) Please refer to the PLL datasheet */ +#define AT91C_CKGR_OUT_2 ( 0x2 << 14 ) /* (CKGR) Please refer to the PLL datasheet */ +#define AT91C_CKGR_OUT_3 ( 0x3 << 14 ) /* (CKGR) Please refer to the PLL datasheet */ +#define AT91C_CKGR_MUL ( 0x7FF << 16 ) /* (CKGR) PLL Multiplier */ +#define AT91C_CKGR_USBDIV ( 0x3 << 28 ) /* (CKGR) Divider for USB Clocks */ +#define AT91C_CKGR_USBDIV_0 ( 0x0 << 28 ) /* (CKGR) Divider output is PLL clock output */ +#define AT91C_CKGR_USBDIV_1 ( 0x1 << 28 ) /* (CKGR) Divider output is PLL clock output divided by 2 */ +#define AT91C_CKGR_USBDIV_2 ( 0x2 << 28 ) /* (CKGR) Divider output is PLL clock output divided by 4 */ -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Power Management Controler -// ***************************************************************************** -// *** Register offset in AT91S_PMC structure *** -#define PMC_SCER ( 0) // System Clock Enable Register -#define PMC_SCDR ( 4) // System Clock Disable Register -#define PMC_SCSR ( 8) // System Clock Status Register -#define PMC_PCER (16) // Peripheral Clock Enable Register -#define PMC_PCDR (20) // Peripheral Clock Disable Register -#define PMC_PCSR (24) // Peripheral Clock Status Register -#define PMC_MOR (32) // Main Oscillator Register -#define PMC_MCFR (36) // Main Clock Frequency Register -#define PMC_PLLR (44) // PLL Register -#define PMC_MCKR (48) // Master Clock Register -#define PMC_PCKR (64) // Programmable Clock Register -#define PMC_IER (96) // Interrupt Enable Register -#define PMC_IDR (100) // Interrupt Disable Register -#define PMC_SR (104) // Status Register -#define PMC_IMR (108) // Interrupt Mask Register -// -------- PMC_SCER : (PMC Offset: 0x0) System Clock Enable Register -------- -#define AT91C_PMC_PCK (0x1 << 0) // (PMC) Processor Clock -#define AT91C_PMC_UDP (0x1 << 7) // (PMC) USB Device Port Clock -#define AT91C_PMC_PCK0 (0x1 << 8) // (PMC) Programmable Clock Output -#define AT91C_PMC_PCK1 (0x1 << 9) // (PMC) Programmable Clock Output -#define AT91C_PMC_PCK2 (0x1 << 10) // (PMC) Programmable Clock Output -#define AT91C_PMC_PCK3 (0x1 << 11) // (PMC) Programmable Clock Output -// -------- PMC_SCDR : (PMC Offset: 0x4) System Clock Disable Register -------- -// -------- PMC_SCSR : (PMC Offset: 0x8) System Clock Status Register -------- -// -------- CKGR_MOR : (PMC Offset: 0x20) Main Oscillator Register -------- -// -------- CKGR_MCFR : (PMC Offset: 0x24) Main Clock Frequency Register -------- -// -------- CKGR_PLLR : (PMC Offset: 0x2c) PLL B Register -------- -// -------- PMC_MCKR : (PMC Offset: 0x30) Master Clock Register -------- -#define AT91C_PMC_CSS (0x3 << 0) // (PMC) Programmable Clock Selection -#define AT91C_PMC_CSS_SLOW_CLK (0x0) // (PMC) Slow Clock is selected -#define AT91C_PMC_CSS_MAIN_CLK (0x1) // (PMC) Main Clock is selected -#define AT91C_PMC_CSS_PLL_CLK (0x3) // (PMC) Clock from PLL is selected -#define AT91C_PMC_PRES (0x7 << 2) // (PMC) Programmable Clock Prescaler -#define AT91C_PMC_PRES_CLK (0x0 << 2) // (PMC) Selected clock -#define AT91C_PMC_PRES_CLK_2 (0x1 << 2) // (PMC) Selected clock divided by 2 -#define AT91C_PMC_PRES_CLK_4 (0x2 << 2) // (PMC) Selected clock divided by 4 -#define AT91C_PMC_PRES_CLK_8 (0x3 << 2) // (PMC) Selected clock divided by 8 -#define AT91C_PMC_PRES_CLK_16 (0x4 << 2) // (PMC) Selected clock divided by 16 -#define AT91C_PMC_PRES_CLK_32 (0x5 << 2) // (PMC) Selected clock divided by 32 -#define AT91C_PMC_PRES_CLK_64 (0x6 << 2) // (PMC) Selected clock divided by 64 -// -------- PMC_PCKR : (PMC Offset: 0x40) Programmable Clock Register -------- -// -------- PMC_IER : (PMC Offset: 0x60) PMC Interrupt Enable Register -------- -#define AT91C_PMC_MOSCS (0x1 << 0) // (PMC) MOSC Status/Enable/Disable/Mask -#define AT91C_PMC_LOCK (0x1 << 2) // (PMC) PLL Status/Enable/Disable/Mask -#define AT91C_PMC_MCKRDY (0x1 << 3) // (PMC) MCK_RDY Status/Enable/Disable/Mask -#define AT91C_PMC_PCK0RDY (0x1 << 8) // (PMC) PCK0_RDY Status/Enable/Disable/Mask -#define AT91C_PMC_PCK1RDY (0x1 << 9) // (PMC) PCK1_RDY Status/Enable/Disable/Mask -#define AT91C_PMC_PCK2RDY (0x1 << 10) // (PMC) PCK2_RDY Status/Enable/Disable/Mask -#define AT91C_PMC_PCK3RDY (0x1 << 11) // (PMC) PCK3_RDY Status/Enable/Disable/Mask -// -------- PMC_IDR : (PMC Offset: 0x64) PMC Interrupt Disable Register -------- -// -------- PMC_SR : (PMC Offset: 0x68) PMC Status Register -------- -// -------- PMC_IMR : (PMC Offset: 0x6c) PMC Interrupt Mask Register -------- +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR Power Management Controller */ +/* ***************************************************************************** */ +/* *** Register offset in AT91S_PMC structure *** */ +#define PMC_SCER ( 0 ) /* System Clock Enable Register */ +#define PMC_SCDR ( 4 ) /* System Clock Disable Register */ +#define PMC_SCSR ( 8 ) /* System Clock Status Register */ +#define PMC_PCER ( 16 ) /* Peripheral Clock Enable Register */ +#define PMC_PCDR ( 20 ) /* Peripheral Clock Disable Register */ +#define PMC_PCSR ( 24 ) /* Peripheral Clock Status Register */ +#define PMC_MOR ( 32 ) /* Main Oscillator Register */ +#define PMC_MCFR ( 36 ) /* Main Clock Frequency Register */ +#define PMC_PLLR ( 44 ) /* PLL Register */ +#define PMC_MCKR ( 48 ) /* Master Clock Register */ +#define PMC_PCKR ( 64 ) /* Programmable Clock Register */ +#define PMC_IER ( 96 ) /* Interrupt Enable Register */ +#define PMC_IDR ( 100 ) /* Interrupt Disable Register */ +#define PMC_SR ( 104 ) /* Status Register */ +#define PMC_IMR ( 108 ) /* Interrupt Mask Register */ +/* -------- PMC_SCER : (PMC Offset: 0x0) System Clock Enable Register -------- */ +#define AT91C_PMC_PCK ( 0x1 << 0 ) /* (PMC) Processor Clock */ +#define AT91C_PMC_UDP ( 0x1 << 7 ) /* (PMC) USB Device Port Clock */ +#define AT91C_PMC_PCK0 ( 0x1 << 8 ) /* (PMC) Programmable Clock Output */ +#define AT91C_PMC_PCK1 ( 0x1 << 9 ) /* (PMC) Programmable Clock Output */ +#define AT91C_PMC_PCK2 ( 0x1 << 10 ) /* (PMC) Programmable Clock Output */ +#define AT91C_PMC_PCK3 ( 0x1 << 11 ) /* (PMC) Programmable Clock Output */ +/* -------- PMC_SCDR : (PMC Offset: 0x4) System Clock Disable Register -------- */ +/* -------- PMC_SCSR : (PMC Offset: 0x8) System Clock Status Register -------- */ +/* -------- CKGR_MOR : (PMC Offset: 0x20) Main Oscillator Register -------- */ +/* -------- CKGR_MCFR : (PMC Offset: 0x24) Main Clock Frequency Register -------- */ +/* -------- CKGR_PLLR : (PMC Offset: 0x2c) PLL B Register -------- */ +/* -------- PMC_MCKR : (PMC Offset: 0x30) Master Clock Register -------- */ +#define AT91C_PMC_CSS ( 0x3 << 0 ) /* (PMC) Programmable Clock Selection */ +#define AT91C_PMC_CSS_SLOW_CLK ( 0x0 ) /* (PMC) Slow Clock is selected */ +#define AT91C_PMC_CSS_MAIN_CLK ( 0x1 ) /* (PMC) Main Clock is selected */ +#define AT91C_PMC_CSS_PLL_CLK ( 0x3 ) /* (PMC) Clock from PLL is selected */ +#define AT91C_PMC_PRES ( 0x7 << 2 ) /* (PMC) Programmable Clock Prescaler */ +#define AT91C_PMC_PRES_CLK ( 0x0 << 2 ) /* (PMC) Selected clock */ +#define AT91C_PMC_PRES_CLK_2 ( 0x1 << 2 ) /* (PMC) Selected clock divided by 2 */ +#define AT91C_PMC_PRES_CLK_4 ( 0x2 << 2 ) /* (PMC) Selected clock divided by 4 */ +#define AT91C_PMC_PRES_CLK_8 ( 0x3 << 2 ) /* (PMC) Selected clock divided by 8 */ +#define AT91C_PMC_PRES_CLK_16 ( 0x4 << 2 ) /* (PMC) Selected clock divided by 16 */ +#define AT91C_PMC_PRES_CLK_32 ( 0x5 << 2 ) /* (PMC) Selected clock divided by 32 */ +#define AT91C_PMC_PRES_CLK_64 ( 0x6 << 2 ) /* (PMC) Selected clock divided by 64 */ +/* -------- PMC_PCKR : (PMC Offset: 0x40) Programmable Clock Register -------- */ +/* -------- PMC_IER : (PMC Offset: 0x60) PMC Interrupt Enable Register -------- */ +#define AT91C_PMC_MOSCS ( 0x1 << 0 ) /* (PMC) MOSC Status/Enable/Disable/Mask */ +#define AT91C_PMC_LOCK ( 0x1 << 2 ) /* (PMC) PLL Status/Enable/Disable/Mask */ +#define AT91C_PMC_MCKRDY ( 0x1 << 3 ) /* (PMC) MCK_RDY Status/Enable/Disable/Mask */ +#define AT91C_PMC_PCK0RDY ( 0x1 << 8 ) /* (PMC) PCK0_RDY Status/Enable/Disable/Mask */ +#define AT91C_PMC_PCK1RDY ( 0x1 << 9 ) /* (PMC) PCK1_RDY Status/Enable/Disable/Mask */ +#define AT91C_PMC_PCK2RDY ( 0x1 << 10 ) /* (PMC) PCK2_RDY Status/Enable/Disable/Mask */ +#define AT91C_PMC_PCK3RDY ( 0x1 << 11 ) /* (PMC) PCK3_RDY Status/Enable/Disable/Mask */ +/* -------- PMC_IDR : (PMC Offset: 0x64) PMC Interrupt Disable Register -------- */ +/* -------- PMC_SR : (PMC Offset: 0x68) PMC Status Register -------- */ +/* -------- PMC_IMR : (PMC Offset: 0x6c) PMC Interrupt Mask Register -------- */ -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Reset Controller Interface -// ***************************************************************************** -// *** Register offset in AT91S_RSTC structure *** -#define RSTC_RCR ( 0) // Reset Control Register -#define RSTC_RSR ( 4) // Reset Status Register -#define RSTC_RMR ( 8) // Reset Mode Register -// -------- RSTC_RCR : (RSTC Offset: 0x0) Reset Control Register -------- -#define AT91C_RSTC_PROCRST (0x1 << 0) // (RSTC) Processor Reset -#define AT91C_RSTC_PERRST (0x1 << 2) // (RSTC) Peripheral Reset -#define AT91C_RSTC_EXTRST (0x1 << 3) // (RSTC) External Reset -#define AT91C_RSTC_KEY (0xFF << 24) // (RSTC) Password -// -------- RSTC_RSR : (RSTC Offset: 0x4) Reset Status Register -------- -#define AT91C_RSTC_URSTS (0x1 << 0) // (RSTC) User Reset Status -#define AT91C_RSTC_BODSTS (0x1 << 1) // (RSTC) Brownout Detection Status -#define AT91C_RSTC_RSTTYP (0x7 << 8) // (RSTC) Reset Type -#define AT91C_RSTC_RSTTYP_POWERUP (0x0 << 8) // (RSTC) Power-up Reset. VDDCORE rising. -#define AT91C_RSTC_RSTTYP_WAKEUP (0x1 << 8) // (RSTC) WakeUp Reset. VDDCORE rising. -#define AT91C_RSTC_RSTTYP_WATCHDOG (0x2 << 8) // (RSTC) Watchdog Reset. Watchdog overflow occured. -#define AT91C_RSTC_RSTTYP_SOFTWARE (0x3 << 8) // (RSTC) Software Reset. Processor reset required by the software. -#define AT91C_RSTC_RSTTYP_USER (0x4 << 8) // (RSTC) User Reset. NRST pin detected low. -#define AT91C_RSTC_RSTTYP_BROWNOUT (0x5 << 8) // (RSTC) Brownout Reset occured. -#define AT91C_RSTC_NRSTL (0x1 << 16) // (RSTC) NRST pin level -#define AT91C_RSTC_SRCMP (0x1 << 17) // (RSTC) Software Reset Command in Progress. -// -------- RSTC_RMR : (RSTC Offset: 0x8) Reset Mode Register -------- -#define AT91C_RSTC_URSTEN (0x1 << 0) // (RSTC) User Reset Enable -#define AT91C_RSTC_URSTIEN (0x1 << 4) // (RSTC) User Reset Interrupt Enable -#define AT91C_RSTC_ERSTL (0xF << 8) // (RSTC) User Reset Enable -#define AT91C_RSTC_BODIEN (0x1 << 16) // (RSTC) Brownout Detection Interrupt Enable +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR Reset Controller Interface */ +/* ***************************************************************************** */ +/* *** Register offset in AT91S_RSTC structure *** */ +#define RSTC_RCR ( 0 ) /* Reset Control Register */ +#define RSTC_RSR ( 4 ) /* Reset Status Register */ +#define RSTC_RMR ( 8 ) /* Reset Mode Register */ +/* -------- RSTC_RCR : (RSTC Offset: 0x0) Reset Control Register -------- */ +#define AT91C_RSTC_PROCRST ( 0x1 << 0 ) /* (RSTC) Processor Reset */ +#define AT91C_RSTC_PERRST ( 0x1 << 2 ) /* (RSTC) Peripheral Reset */ +#define AT91C_RSTC_EXTRST ( 0x1 << 3 ) /* (RSTC) External Reset */ +#define AT91C_RSTC_KEY ( 0xFF << 24 ) /* (RSTC) Password */ +/* -------- RSTC_RSR : (RSTC Offset: 0x4) Reset Status Register -------- */ +#define AT91C_RSTC_URSTS ( 0x1 << 0 ) /* (RSTC) User Reset Status */ +#define AT91C_RSTC_BODSTS ( 0x1 << 1 ) /* (RSTC) Brownout Detection Status */ +#define AT91C_RSTC_RSTTYP ( 0x7 << 8 ) /* (RSTC) Reset Type */ +#define AT91C_RSTC_RSTTYP_POWERUP ( 0x0 << 8 ) /* (RSTC) Power-up Reset. VDDCORE rising. */ +#define AT91C_RSTC_RSTTYP_WAKEUP ( 0x1 << 8 ) /* (RSTC) WakeUp Reset. VDDCORE rising. */ +#define AT91C_RSTC_RSTTYP_WATCHDOG ( 0x2 << 8 ) /* (RSTC) Watchdog Reset. Watchdog overflow occurred. */ +#define AT91C_RSTC_RSTTYP_SOFTWARE ( 0x3 << 8 ) /* (RSTC) Software Reset. Processor reset required by the software. */ +#define AT91C_RSTC_RSTTYP_USER ( 0x4 << 8 ) /* (RSTC) User Reset. NRST pin detected low. */ +#define AT91C_RSTC_RSTTYP_BROWNOUT ( 0x5 << 8 ) /* (RSTC) Brownout Reset occurred. */ +#define AT91C_RSTC_NRSTL ( 0x1 << 16 ) /* (RSTC) NRST pin level */ +#define AT91C_RSTC_SRCMP ( 0x1 << 17 ) /* (RSTC) Software Reset Command in Progress. */ +/* -------- RSTC_RMR : (RSTC Offset: 0x8) Reset Mode Register -------- */ +#define AT91C_RSTC_URSTEN ( 0x1 << 0 ) /* (RSTC) User Reset Enable */ +#define AT91C_RSTC_URSTIEN ( 0x1 << 4 ) /* (RSTC) User Reset Interrupt Enable */ +#define AT91C_RSTC_ERSTL ( 0xF << 8 ) /* (RSTC) User Reset Enable */ +#define AT91C_RSTC_BODIEN ( 0x1 << 16 ) /* (RSTC) Brownout Detection Interrupt Enable */ -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Real Time Timer Controller Interface -// ***************************************************************************** -// *** Register offset in AT91S_RTTC structure *** -#define RTTC_RTMR ( 0) // Real-time Mode Register -#define RTTC_RTAR ( 4) // Real-time Alarm Register -#define RTTC_RTVR ( 8) // Real-time Value Register -#define RTTC_RTSR (12) // Real-time Status Register -// -------- RTTC_RTMR : (RTTC Offset: 0x0) Real-time Mode Register -------- -#define AT91C_RTTC_RTPRES (0xFFFF << 0) // (RTTC) Real-time Timer Prescaler Value -#define AT91C_RTTC_ALMIEN (0x1 << 16) // (RTTC) Alarm Interrupt Enable -#define AT91C_RTTC_RTTINCIEN (0x1 << 17) // (RTTC) Real Time Timer Increment Interrupt Enable -#define AT91C_RTTC_RTTRST (0x1 << 18) // (RTTC) Real Time Timer Restart -// -------- RTTC_RTAR : (RTTC Offset: 0x4) Real-time Alarm Register -------- -#define AT91C_RTTC_ALMV (0x0 << 0) // (RTTC) Alarm Value -// -------- RTTC_RTVR : (RTTC Offset: 0x8) Current Real-time Value Register -------- -#define AT91C_RTTC_CRTV (0x0 << 0) // (RTTC) Current Real-time Value -// -------- RTTC_RTSR : (RTTC Offset: 0xc) Real-time Status Register -------- -#define AT91C_RTTC_ALMS (0x1 << 0) // (RTTC) Real-time Alarm Status -#define AT91C_RTTC_RTTINC (0x1 << 1) // (RTTC) Real-time Timer Increment +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR Real Time Timer Controller Interface */ +/* ***************************************************************************** */ +/* *** Register offset in AT91S_RTTC structure *** */ +#define RTTC_RTMR ( 0 ) /* Real-time Mode Register */ +#define RTTC_RTAR ( 4 ) /* Real-time Alarm Register */ +#define RTTC_RTVR ( 8 ) /* Real-time Value Register */ +#define RTTC_RTSR ( 12 ) /* Real-time Status Register */ +/* -------- RTTC_RTMR : (RTTC Offset: 0x0) Real-time Mode Register -------- */ +#define AT91C_RTTC_RTPRES ( 0xFFFF << 0 ) /* (RTTC) Real-time Timer Prescaler Value */ +#define AT91C_RTTC_ALMIEN ( 0x1 << 16 ) /* (RTTC) Alarm Interrupt Enable */ +#define AT91C_RTTC_RTTINCIEN ( 0x1 << 17 ) /* (RTTC) Real Time Timer Increment Interrupt Enable */ +#define AT91C_RTTC_RTTRST ( 0x1 << 18 ) /* (RTTC) Real Time Timer Restart */ +/* -------- RTTC_RTAR : (RTTC Offset: 0x4) Real-time Alarm Register -------- */ +#define AT91C_RTTC_ALMV ( 0x0 << 0 ) /* (RTTC) Alarm Value */ +/* -------- RTTC_RTVR : (RTTC Offset: 0x8) Current Real-time Value Register -------- */ +#define AT91C_RTTC_CRTV ( 0x0 << 0 ) /* (RTTC) Current Real-time Value */ +/* -------- RTTC_RTSR : (RTTC Offset: 0xc) Real-time Status Register -------- */ +#define AT91C_RTTC_ALMS ( 0x1 << 0 ) /* (RTTC) Real-time Alarm Status */ +#define AT91C_RTTC_RTTINC ( 0x1 << 1 ) /* (RTTC) Real-time Timer Increment */ -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Periodic Interval Timer Controller Interface -// ***************************************************************************** -// *** Register offset in AT91S_PITC structure *** -#define PITC_PIMR ( 0) // Period Interval Mode Register -#define PITC_PISR ( 4) // Period Interval Status Register -#define PITC_PIVR ( 8) // Period Interval Value Register -#define PITC_PIIR (12) // Period Interval Image Register -// -------- PITC_PIMR : (PITC Offset: 0x0) Periodic Interval Mode Register -------- -#define AT91C_PITC_PIV (0xFFFFF << 0) // (PITC) Periodic Interval Value -#define AT91C_PITC_PITEN (0x1 << 24) // (PITC) Periodic Interval Timer Enabled -#define AT91C_PITC_PITIEN (0x1 << 25) // (PITC) Periodic Interval Timer Interrupt Enable -// -------- PITC_PISR : (PITC Offset: 0x4) Periodic Interval Status Register -------- -#define AT91C_PITC_PITS (0x1 << 0) // (PITC) Periodic Interval Timer Status -// -------- PITC_PIVR : (PITC Offset: 0x8) Periodic Interval Value Register -------- -#define AT91C_PITC_CPIV (0xFFFFF << 0) // (PITC) Current Periodic Interval Value -#define AT91C_PITC_PICNT (0xFFF << 20) // (PITC) Periodic Interval Counter -// -------- PITC_PIIR : (PITC Offset: 0xc) Periodic Interval Image Register -------- +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR Periodic Interval Timer Controller Interface */ +/* ***************************************************************************** */ +/* *** Register offset in AT91S_PITC structure *** */ +#define PITC_PIMR ( 0 ) /* Period Interval Mode Register */ +#define PITC_PISR ( 4 ) /* Period Interval Status Register */ +#define PITC_PIVR ( 8 ) /* Period Interval Value Register */ +#define PITC_PIIR ( 12 ) /* Period Interval Image Register */ +/* -------- PITC_PIMR : (PITC Offset: 0x0) Periodic Interval Mode Register -------- */ +#define AT91C_PITC_PIV ( 0xFFFFF << 0 ) /* (PITC) Periodic Interval Value */ +#define AT91C_PITC_PITEN ( 0x1 << 24 ) /* (PITC) Periodic Interval Timer Enabled */ +#define AT91C_PITC_PITIEN ( 0x1 << 25 ) /* (PITC) Periodic Interval Timer Interrupt Enable */ +/* -------- PITC_PISR : (PITC Offset: 0x4) Periodic Interval Status Register -------- */ +#define AT91C_PITC_PITS ( 0x1 << 0 ) /* (PITC) Periodic Interval Timer Status */ +/* -------- PITC_PIVR : (PITC Offset: 0x8) Periodic Interval Value Register -------- */ +#define AT91C_PITC_CPIV ( 0xFFFFF << 0 ) /* (PITC) Current Periodic Interval Value */ +#define AT91C_PITC_PICNT ( 0xFFF << 20 ) /* (PITC) Periodic Interval Counter */ +/* -------- PITC_PIIR : (PITC Offset: 0xc) Periodic Interval Image Register -------- */ -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Watchdog Timer Controller Interface -// ***************************************************************************** -// *** Register offset in AT91S_WDTC structure *** -#define WDTC_WDCR ( 0) // Watchdog Control Register -#define WDTC_WDMR ( 4) // Watchdog Mode Register -#define WDTC_WDSR ( 8) // Watchdog Status Register -// -------- WDTC_WDCR : (WDTC Offset: 0x0) Periodic Interval Image Register -------- -#define AT91C_WDTC_WDRSTT (0x1 << 0) // (WDTC) Watchdog Restart -#define AT91C_WDTC_KEY (0xFF << 24) // (WDTC) Watchdog KEY Password -// -------- WDTC_WDMR : (WDTC Offset: 0x4) Watchdog Mode Register -------- -#define AT91C_WDTC_WDV (0xFFF << 0) // (WDTC) Watchdog Timer Restart -#define AT91C_WDTC_WDFIEN (0x1 << 12) // (WDTC) Watchdog Fault Interrupt Enable -#define AT91C_WDTC_WDRSTEN (0x1 << 13) // (WDTC) Watchdog Reset Enable -#define AT91C_WDTC_WDRPROC (0x1 << 14) // (WDTC) Watchdog Timer Restart -#define AT91C_WDTC_WDDIS (0x1 << 15) // (WDTC) Watchdog Disable -#define AT91C_WDTC_WDD (0xFFF << 16) // (WDTC) Watchdog Delta Value -#define AT91C_WDTC_WDDBGHLT (0x1 << 28) // (WDTC) Watchdog Debug Halt -#define AT91C_WDTC_WDIDLEHLT (0x1 << 29) // (WDTC) Watchdog Idle Halt -// -------- WDTC_WDSR : (WDTC Offset: 0x8) Watchdog Status Register -------- -#define AT91C_WDTC_WDUNF (0x1 << 0) // (WDTC) Watchdog Underflow -#define AT91C_WDTC_WDERR (0x1 << 1) // (WDTC) Watchdog Error +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR Watchdog Timer Controller Interface */ +/* ***************************************************************************** */ +/* *** Register offset in AT91S_WDTC structure *** */ +#define WDTC_WDCR ( 0 ) /* Watchdog Control Register */ +#define WDTC_WDMR ( 4 ) /* Watchdog Mode Register */ +#define WDTC_WDSR ( 8 ) /* Watchdog Status Register */ +/* -------- WDTC_WDCR : (WDTC Offset: 0x0) Periodic Interval Image Register -------- */ +#define AT91C_WDTC_WDRSTT ( 0x1 << 0 ) /* (WDTC) Watchdog Restart */ +#define AT91C_WDTC_KEY ( 0xFF << 24 ) /* (WDTC) Watchdog KEY Password */ +/* -------- WDTC_WDMR : (WDTC Offset: 0x4) Watchdog Mode Register -------- */ +#define AT91C_WDTC_WDV ( 0xFFF << 0 ) /* (WDTC) Watchdog Timer Restart */ +#define AT91C_WDTC_WDFIEN ( 0x1 << 12 ) /* (WDTC) Watchdog Fault Interrupt Enable */ +#define AT91C_WDTC_WDRSTEN ( 0x1 << 13 ) /* (WDTC) Watchdog Reset Enable */ +#define AT91C_WDTC_WDRPROC ( 0x1 << 14 ) /* (WDTC) Watchdog Timer Restart */ +#define AT91C_WDTC_WDDIS ( 0x1 << 15 ) /* (WDTC) Watchdog Disable */ +#define AT91C_WDTC_WDD ( 0xFFF << 16 ) /* (WDTC) Watchdog Delta Value */ +#define AT91C_WDTC_WDDBGHLT ( 0x1 << 28 ) /* (WDTC) Watchdog Debug Halt */ +#define AT91C_WDTC_WDIDLEHLT ( 0x1 << 29 ) /* (WDTC) Watchdog Idle Halt */ +/* -------- WDTC_WDSR : (WDTC Offset: 0x8) Watchdog Status Register -------- */ +#define AT91C_WDTC_WDUNF ( 0x1 << 0 ) /* (WDTC) Watchdog Underflow */ +#define AT91C_WDTC_WDERR ( 0x1 << 1 ) /* (WDTC) Watchdog Error */ -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Voltage Regulator Mode Controller Interface -// ***************************************************************************** -// *** Register offset in AT91S_VREG structure *** -#define VREG_MR ( 0) // Voltage Regulator Mode Register -// -------- VREG_MR : (VREG Offset: 0x0) Voltage Regulator Mode Register -------- -#define AT91C_VREG_PSTDBY (0x1 << 0) // (VREG) Voltage Regulator Power Standby Mode +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR Voltage Regulator Mode Controller Interface */ +/* ***************************************************************************** */ +/* *** Register offset in AT91S_VREG structure *** */ +#define VREG_MR ( 0 ) /* Voltage Regulator Mode Register */ +/* -------- VREG_MR : (VREG Offset: 0x0) Voltage Regulator Mode Register -------- */ +#define AT91C_VREG_PSTDBY ( 0x1 << 0 ) /* (VREG) Voltage Regulator Power Standby Mode */ -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Memory Controller Interface -// ***************************************************************************** -// *** Register offset in AT91S_MC structure *** -#define MC_RCR ( 0) // MC Remap Control Register -#define MC_ASR ( 4) // MC Abort Status Register -#define MC_AASR ( 8) // MC Abort Address Status Register -#define MC_FMR (96) // MC Flash Mode Register -#define MC_FCR (100) // MC Flash Command Register -#define MC_FSR (104) // MC Flash Status Register -// -------- MC_RCR : (MC Offset: 0x0) MC Remap Control Register -------- -#define AT91C_MC_RCB (0x1 << 0) // (MC) Remap Command Bit -// -------- MC_ASR : (MC Offset: 0x4) MC Abort Status Register -------- -#define AT91C_MC_UNDADD (0x1 << 0) // (MC) Undefined Addess Abort Status -#define AT91C_MC_MISADD (0x1 << 1) // (MC) Misaligned Addess Abort Status -#define AT91C_MC_ABTSZ (0x3 << 8) // (MC) Abort Size Status -#define AT91C_MC_ABTSZ_BYTE (0x0 << 8) // (MC) Byte -#define AT91C_MC_ABTSZ_HWORD (0x1 << 8) // (MC) Half-word -#define AT91C_MC_ABTSZ_WORD (0x2 << 8) // (MC) Word -#define AT91C_MC_ABTTYP (0x3 << 10) // (MC) Abort Type Status -#define AT91C_MC_ABTTYP_DATAR (0x0 << 10) // (MC) Data Read -#define AT91C_MC_ABTTYP_DATAW (0x1 << 10) // (MC) Data Write -#define AT91C_MC_ABTTYP_FETCH (0x2 << 10) // (MC) Code Fetch -#define AT91C_MC_MST0 (0x1 << 16) // (MC) Master 0 Abort Source -#define AT91C_MC_MST1 (0x1 << 17) // (MC) Master 1 Abort Source -#define AT91C_MC_SVMST0 (0x1 << 24) // (MC) Saved Master 0 Abort Source -#define AT91C_MC_SVMST1 (0x1 << 25) // (MC) Saved Master 1 Abort Source -// -------- MC_FMR : (MC Offset: 0x60) MC Flash Mode Register -------- -#define AT91C_MC_FRDY (0x1 << 0) // (MC) Flash Ready -#define AT91C_MC_LOCKE (0x1 << 2) // (MC) Lock Error -#define AT91C_MC_PROGE (0x1 << 3) // (MC) Programming Error -#define AT91C_MC_NEBP (0x1 << 7) // (MC) No Erase Before Programming -#define AT91C_MC_FWS (0x3 << 8) // (MC) Flash Wait State -#define AT91C_MC_FWS_0FWS (0x0 << 8) // (MC) 1 cycle for Read, 2 for Write operations -#define AT91C_MC_FWS_1FWS (0x1 << 8) // (MC) 2 cycles for Read, 3 for Write operations -#define AT91C_MC_FWS_2FWS (0x2 << 8) // (MC) 3 cycles for Read, 4 for Write operations -#define AT91C_MC_FWS_3FWS (0x3 << 8) // (MC) 4 cycles for Read, 4 for Write operations -#define AT91C_MC_FMCN (0xFF << 16) // (MC) Flash Microsecond Cycle Number -// -------- MC_FCR : (MC Offset: 0x64) MC Flash Command Register -------- -#define AT91C_MC_FCMD (0xF << 0) // (MC) Flash Command -#define AT91C_MC_FCMD_START_PROG (0x1) // (MC) Starts the programming of th epage specified by PAGEN. -#define AT91C_MC_FCMD_LOCK (0x2) // (MC) Starts a lock sequence of the sector defined by the bits 4 to 7 of the field PAGEN. -#define AT91C_MC_FCMD_PROG_AND_LOCK (0x3) // (MC) The lock sequence automatically happens after the programming sequence is completed. -#define AT91C_MC_FCMD_UNLOCK (0x4) // (MC) Starts an unlock sequence of the sector defined by the bits 4 to 7 of the field PAGEN. -#define AT91C_MC_FCMD_ERASE_ALL (0x8) // (MC) Starts the erase of the entire flash.If at least a page is locked, the command is cancelled. -#define AT91C_MC_FCMD_SET_GP_NVM (0xB) // (MC) Set General Purpose NVM bits. -#define AT91C_MC_FCMD_CLR_GP_NVM (0xD) // (MC) Clear General Purpose NVM bits. -#define AT91C_MC_FCMD_SET_SECURITY (0xF) // (MC) Set Security Bit. -#define AT91C_MC_PAGEN (0x3FF << 8) // (MC) Page Number -#define AT91C_MC_KEY (0xFF << 24) // (MC) Writing Protect Key -// -------- MC_FSR : (MC Offset: 0x68) MC Flash Command Register -------- -#define AT91C_MC_SECURITY (0x1 << 4) // (MC) Security Bit Status -#define AT91C_MC_GPNVM0 (0x1 << 8) // (MC) Sector 0 Lock Status -#define AT91C_MC_GPNVM1 (0x1 << 9) // (MC) Sector 1 Lock Status -#define AT91C_MC_GPNVM2 (0x1 << 10) // (MC) Sector 2 Lock Status -#define AT91C_MC_GPNVM3 (0x1 << 11) // (MC) Sector 3 Lock Status -#define AT91C_MC_GPNVM4 (0x1 << 12) // (MC) Sector 4 Lock Status -#define AT91C_MC_GPNVM5 (0x1 << 13) // (MC) Sector 5 Lock Status -#define AT91C_MC_GPNVM6 (0x1 << 14) // (MC) Sector 6 Lock Status -#define AT91C_MC_GPNVM7 (0x1 << 15) // (MC) Sector 7 Lock Status -#define AT91C_MC_LOCKS0 (0x1 << 16) // (MC) Sector 0 Lock Status -#define AT91C_MC_LOCKS1 (0x1 << 17) // (MC) Sector 1 Lock Status -#define AT91C_MC_LOCKS2 (0x1 << 18) // (MC) Sector 2 Lock Status -#define AT91C_MC_LOCKS3 (0x1 << 19) // (MC) Sector 3 Lock Status -#define AT91C_MC_LOCKS4 (0x1 << 20) // (MC) Sector 4 Lock Status -#define AT91C_MC_LOCKS5 (0x1 << 21) // (MC) Sector 5 Lock Status -#define AT91C_MC_LOCKS6 (0x1 << 22) // (MC) Sector 6 Lock Status -#define AT91C_MC_LOCKS7 (0x1 << 23) // (MC) Sector 7 Lock Status -#define AT91C_MC_LOCKS8 (0x1 << 24) // (MC) Sector 8 Lock Status -#define AT91C_MC_LOCKS9 (0x1 << 25) // (MC) Sector 9 Lock Status -#define AT91C_MC_LOCKS10 (0x1 << 26) // (MC) Sector 10 Lock Status -#define AT91C_MC_LOCKS11 (0x1 << 27) // (MC) Sector 11 Lock Status -#define AT91C_MC_LOCKS12 (0x1 << 28) // (MC) Sector 12 Lock Status -#define AT91C_MC_LOCKS13 (0x1 << 29) // (MC) Sector 13 Lock Status -#define AT91C_MC_LOCKS14 (0x1 << 30) // (MC) Sector 14 Lock Status -#define AT91C_MC_LOCKS15 (0x1 << 31) // (MC) Sector 15 Lock Status +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR Memory Controller Interface */ +/* ***************************************************************************** */ +/* *** Register offset in AT91S_MC structure *** */ +#define MC_RCR ( 0 ) /* MC Remap Control Register */ +#define MC_ASR ( 4 ) /* MC Abort Status Register */ +#define MC_AASR ( 8 ) /* MC Abort Address Status Register */ +#define MC_FMR ( 96 ) /* MC Flash Mode Register */ +#define MC_FCR ( 100 ) /* MC Flash Command Register */ +#define MC_FSR ( 104 ) /* MC Flash Status Register */ +/* -------- MC_RCR : (MC Offset: 0x0) MC Remap Control Register -------- */ +#define AT91C_MC_RCB ( 0x1 << 0 ) /* (MC) Remap Command Bit */ +/* -------- MC_ASR : (MC Offset: 0x4) MC Abort Status Register -------- */ +#define AT91C_MC_UNDADD ( 0x1 << 0 ) /* (MC) Undefined Addess Abort Status */ +#define AT91C_MC_MISADD ( 0x1 << 1 ) /* (MC) Misaligned Addess Abort Status */ +#define AT91C_MC_ABTSZ ( 0x3 << 8 ) /* (MC) Abort Size Status */ +#define AT91C_MC_ABTSZ_BYTE ( 0x0 << 8 ) /* (MC) Byte */ +#define AT91C_MC_ABTSZ_HWORD ( 0x1 << 8 ) /* (MC) Half-word */ +#define AT91C_MC_ABTSZ_WORD ( 0x2 << 8 ) /* (MC) Word */ +#define AT91C_MC_ABTTYP ( 0x3 << 10 ) /* (MC) Abort Type Status */ +#define AT91C_MC_ABTTYP_DATAR ( 0x0 << 10 ) /* (MC) Data Read */ +#define AT91C_MC_ABTTYP_DATAW ( 0x1 << 10 ) /* (MC) Data Write */ +#define AT91C_MC_ABTTYP_FETCH ( 0x2 << 10 ) /* (MC) Code Fetch */ +#define AT91C_MC_MST0 ( 0x1 << 16 ) /* (MC) Master 0 Abort Source */ +#define AT91C_MC_MST1 ( 0x1 << 17 ) /* (MC) Master 1 Abort Source */ +#define AT91C_MC_SVMST0 ( 0x1 << 24 ) /* (MC) Saved Master 0 Abort Source */ +#define AT91C_MC_SVMST1 ( 0x1 << 25 ) /* (MC) Saved Master 1 Abort Source */ +/* -------- MC_FMR : (MC Offset: 0x60) MC Flash Mode Register -------- */ +#define AT91C_MC_FRDY ( 0x1 << 0 ) /* (MC) Flash Ready */ +#define AT91C_MC_LOCKE ( 0x1 << 2 ) /* (MC) Lock Error */ +#define AT91C_MC_PROGE ( 0x1 << 3 ) /* (MC) Programming Error */ +#define AT91C_MC_NEBP ( 0x1 << 7 ) /* (MC) No Erase Before Programming */ +#define AT91C_MC_FWS ( 0x3 << 8 ) /* (MC) Flash Wait State */ +#define AT91C_MC_FWS_0FWS ( 0x0 << 8 ) /* (MC) 1 cycle for Read, 2 for Write operations */ +#define AT91C_MC_FWS_1FWS ( 0x1 << 8 ) /* (MC) 2 cycles for Read, 3 for Write operations */ +#define AT91C_MC_FWS_2FWS ( 0x2 << 8 ) /* (MC) 3 cycles for Read, 4 for Write operations */ +#define AT91C_MC_FWS_3FWS ( 0x3 << 8 ) /* (MC) 4 cycles for Read, 4 for Write operations */ +#define AT91C_MC_FMCN ( 0xFF << 16 ) /* (MC) Flash Microsecond Cycle Number */ +/* -------- MC_FCR : (MC Offset: 0x64) MC Flash Command Register -------- */ +#define AT91C_MC_FCMD ( 0xF << 0 ) /* (MC) Flash Command */ +#define AT91C_MC_FCMD_START_PROG ( 0x1 ) /* (MC) Starts the programming of th epage specified by PAGEN. */ +#define AT91C_MC_FCMD_LOCK ( 0x2 ) /* (MC) Starts a lock sequence of the sector defined by the bits 4 to 7 of the field PAGEN. */ +#define AT91C_MC_FCMD_PROG_AND_LOCK ( 0x3 ) /* (MC) The lock sequence automatically happens after the programming sequence is completed. */ +#define AT91C_MC_FCMD_UNLOCK ( 0x4 ) /* (MC) Starts an unlock sequence of the sector defined by the bits 4 to 7 of the field PAGEN. */ +#define AT91C_MC_FCMD_ERASE_ALL ( 0x8 ) /* (MC) Starts the erase of the entire flash.If at least a page is locked, the command is cancelled. */ +#define AT91C_MC_FCMD_SET_GP_NVM ( 0xB ) /* (MC) Set General Purpose NVM bits. */ +#define AT91C_MC_FCMD_CLR_GP_NVM ( 0xD ) /* (MC) Clear General Purpose NVM bits. */ +#define AT91C_MC_FCMD_SET_SECURITY ( 0xF ) /* (MC) Set Security Bit. */ +#define AT91C_MC_PAGEN ( 0x3FF << 8 ) /* (MC) Page Number */ +#define AT91C_MC_KEY ( 0xFF << 24 ) /* (MC) Writing Protect Key */ +/* -------- MC_FSR : (MC Offset: 0x68) MC Flash Command Register -------- */ +#define AT91C_MC_SECURITY ( 0x1 << 4 ) /* (MC) Security Bit Status */ +#define AT91C_MC_GPNVM0 ( 0x1 << 8 ) /* (MC) Sector 0 Lock Status */ +#define AT91C_MC_GPNVM1 ( 0x1 << 9 ) /* (MC) Sector 1 Lock Status */ +#define AT91C_MC_GPNVM2 ( 0x1 << 10 ) /* (MC) Sector 2 Lock Status */ +#define AT91C_MC_GPNVM3 ( 0x1 << 11 ) /* (MC) Sector 3 Lock Status */ +#define AT91C_MC_GPNVM4 ( 0x1 << 12 ) /* (MC) Sector 4 Lock Status */ +#define AT91C_MC_GPNVM5 ( 0x1 << 13 ) /* (MC) Sector 5 Lock Status */ +#define AT91C_MC_GPNVM6 ( 0x1 << 14 ) /* (MC) Sector 6 Lock Status */ +#define AT91C_MC_GPNVM7 ( 0x1 << 15 ) /* (MC) Sector 7 Lock Status */ +#define AT91C_MC_LOCKS0 ( 0x1 << 16 ) /* (MC) Sector 0 Lock Status */ +#define AT91C_MC_LOCKS1 ( 0x1 << 17 ) /* (MC) Sector 1 Lock Status */ +#define AT91C_MC_LOCKS2 ( 0x1 << 18 ) /* (MC) Sector 2 Lock Status */ +#define AT91C_MC_LOCKS3 ( 0x1 << 19 ) /* (MC) Sector 3 Lock Status */ +#define AT91C_MC_LOCKS4 ( 0x1 << 20 ) /* (MC) Sector 4 Lock Status */ +#define AT91C_MC_LOCKS5 ( 0x1 << 21 ) /* (MC) Sector 5 Lock Status */ +#define AT91C_MC_LOCKS6 ( 0x1 << 22 ) /* (MC) Sector 6 Lock Status */ +#define AT91C_MC_LOCKS7 ( 0x1 << 23 ) /* (MC) Sector 7 Lock Status */ +#define AT91C_MC_LOCKS8 ( 0x1 << 24 ) /* (MC) Sector 8 Lock Status */ +#define AT91C_MC_LOCKS9 ( 0x1 << 25 ) /* (MC) Sector 9 Lock Status */ +#define AT91C_MC_LOCKS10 ( 0x1 << 26 ) /* (MC) Sector 10 Lock Status */ +#define AT91C_MC_LOCKS11 ( 0x1 << 27 ) /* (MC) Sector 11 Lock Status */ +#define AT91C_MC_LOCKS12 ( 0x1 << 28 ) /* (MC) Sector 12 Lock Status */ +#define AT91C_MC_LOCKS13 ( 0x1 << 29 ) /* (MC) Sector 13 Lock Status */ +#define AT91C_MC_LOCKS14 ( 0x1 << 30 ) /* (MC) Sector 14 Lock Status */ +#define AT91C_MC_LOCKS15 ( 0x1 << 31 ) /* (MC) Sector 15 Lock Status */ -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Serial Parallel Interface -// ***************************************************************************** -// *** Register offset in AT91S_SPI structure *** -#define SPI_CR ( 0) // Control Register -#define SPI_MR ( 4) // Mode Register -#define SPI_RDR ( 8) // Receive Data Register -#define SPI_TDR (12) // Transmit Data Register -#define SPI_SR (16) // Status Register -#define SPI_IER (20) // Interrupt Enable Register -#define SPI_IDR (24) // Interrupt Disable Register -#define SPI_IMR (28) // Interrupt Mask Register -#define SPI_CSR (48) // Chip Select Register -#define SPI_RPR (256) // Receive Pointer Register -#define SPI_RCR (260) // Receive Counter Register -#define SPI_TPR (264) // Transmit Pointer Register -#define SPI_TCR (268) // Transmit Counter Register -#define SPI_RNPR (272) // Receive Next Pointer Register -#define SPI_RNCR (276) // Receive Next Counter Register -#define SPI_TNPR (280) // Transmit Next Pointer Register -#define SPI_TNCR (284) // Transmit Next Counter Register -#define SPI_PTCR (288) // PDC Transfer Control Register -#define SPI_PTSR (292) // PDC Transfer Status Register -// -------- SPI_CR : (SPI Offset: 0x0) SPI Control Register -------- -#define AT91C_SPI_SPIEN (0x1 << 0) // (SPI) SPI Enable -#define AT91C_SPI_SPIDIS (0x1 << 1) // (SPI) SPI Disable -#define AT91C_SPI_SWRST (0x1 << 7) // (SPI) SPI Software reset -#define AT91C_SPI_LASTXFER (0x1 << 24) // (SPI) SPI Last Transfer -// -------- SPI_MR : (SPI Offset: 0x4) SPI Mode Register -------- -#define AT91C_SPI_MSTR (0x1 << 0) // (SPI) Master/Slave Mode -#define AT91C_SPI_PS (0x1 << 1) // (SPI) Peripheral Select -#define AT91C_SPI_PS_FIXED (0x0 << 1) // (SPI) Fixed Peripheral Select -#define AT91C_SPI_PS_VARIABLE (0x1 << 1) // (SPI) Variable Peripheral Select -#define AT91C_SPI_PCSDEC (0x1 << 2) // (SPI) Chip Select Decode -#define AT91C_SPI_FDIV (0x1 << 3) // (SPI) Clock Selection -#define AT91C_SPI_MODFDIS (0x1 << 4) // (SPI) Mode Fault Detection -#define AT91C_SPI_LLB (0x1 << 7) // (SPI) Clock Selection -#define AT91C_SPI_PCS (0xF << 16) // (SPI) Peripheral Chip Select -#define AT91C_SPI_DLYBCS (0xFF << 24) // (SPI) Delay Between Chip Selects -// -------- SPI_RDR : (SPI Offset: 0x8) Receive Data Register -------- -#define AT91C_SPI_RD (0xFFFF << 0) // (SPI) Receive Data -#define AT91C_SPI_RPCS (0xF << 16) // (SPI) Peripheral Chip Select Status -// -------- SPI_TDR : (SPI Offset: 0xc) Transmit Data Register -------- -#define AT91C_SPI_TD (0xFFFF << 0) // (SPI) Transmit Data -#define AT91C_SPI_TPCS (0xF << 16) // (SPI) Peripheral Chip Select Status -// -------- SPI_SR : (SPI Offset: 0x10) Status Register -------- -#define AT91C_SPI_RDRF (0x1 << 0) // (SPI) Receive Data Register Full -#define AT91C_SPI_TDRE (0x1 << 1) // (SPI) Transmit Data Register Empty -#define AT91C_SPI_MODF (0x1 << 2) // (SPI) Mode Fault Error -#define AT91C_SPI_OVRES (0x1 << 3) // (SPI) Overrun Error Status -#define AT91C_SPI_ENDRX (0x1 << 4) // (SPI) End of Receiver Transfer -#define AT91C_SPI_ENDTX (0x1 << 5) // (SPI) End of Receiver Transfer -#define AT91C_SPI_RXBUFF (0x1 << 6) // (SPI) RXBUFF Interrupt -#define AT91C_SPI_TXBUFE (0x1 << 7) // (SPI) TXBUFE Interrupt -#define AT91C_SPI_NSSR (0x1 << 8) // (SPI) NSSR Interrupt -#define AT91C_SPI_TXEMPTY (0x1 << 9) // (SPI) TXEMPTY Interrupt -#define AT91C_SPI_SPIENS (0x1 << 16) // (SPI) Enable Status -// -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register -------- -// -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register -------- -// -------- SPI_IMR : (SPI Offset: 0x1c) Interrupt Mask Register -------- -// -------- SPI_CSR : (SPI Offset: 0x30) Chip Select Register -------- -#define AT91C_SPI_CPOL (0x1 << 0) // (SPI) Clock Polarity -#define AT91C_SPI_NCPHA (0x1 << 1) // (SPI) Clock Phase -#define AT91C_SPI_CSAAT (0x1 << 3) // (SPI) Chip Select Active After Transfer -#define AT91C_SPI_BITS (0xF << 4) // (SPI) Bits Per Transfer -#define AT91C_SPI_BITS_8 (0x0 << 4) // (SPI) 8 Bits Per transfer -#define AT91C_SPI_BITS_9 (0x1 << 4) // (SPI) 9 Bits Per transfer -#define AT91C_SPI_BITS_10 (0x2 << 4) // (SPI) 10 Bits Per transfer -#define AT91C_SPI_BITS_11 (0x3 << 4) // (SPI) 11 Bits Per transfer -#define AT91C_SPI_BITS_12 (0x4 << 4) // (SPI) 12 Bits Per transfer -#define AT91C_SPI_BITS_13 (0x5 << 4) // (SPI) 13 Bits Per transfer -#define AT91C_SPI_BITS_14 (0x6 << 4) // (SPI) 14 Bits Per transfer -#define AT91C_SPI_BITS_15 (0x7 << 4) // (SPI) 15 Bits Per transfer -#define AT91C_SPI_BITS_16 (0x8 << 4) // (SPI) 16 Bits Per transfer -#define AT91C_SPI_SCBR (0xFF << 8) // (SPI) Serial Clock Baud Rate -#define AT91C_SPI_DLYBS (0xFF << 16) // (SPI) Delay Before SPCK -#define AT91C_SPI_DLYBCT (0xFF << 24) // (SPI) Delay Between Consecutive Transfers +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR Serial Parallel Interface */ +/* ***************************************************************************** */ +/* *** Register offset in AT91S_SPI structure *** */ +#define SPI_CR ( 0 ) /* Control Register */ +#define SPI_MR ( 4 ) /* Mode Register */ +#define SPI_RDR ( 8 ) /* Receive Data Register */ +#define SPI_TDR ( 12 ) /* Transmit Data Register */ +#define SPI_SR ( 16 ) /* Status Register */ +#define SPI_IER ( 20 ) /* Interrupt Enable Register */ +#define SPI_IDR ( 24 ) /* Interrupt Disable Register */ +#define SPI_IMR ( 28 ) /* Interrupt Mask Register */ +#define SPI_CSR ( 48 ) /* Chip Select Register */ +#define SPI_RPR ( 256 ) /* Receive Pointer Register */ +#define SPI_RCR ( 260 ) /* Receive Counter Register */ +#define SPI_TPR ( 264 ) /* Transmit Pointer Register */ +#define SPI_TCR ( 268 ) /* Transmit Counter Register */ +#define SPI_RNPR ( 272 ) /* Receive Next Pointer Register */ +#define SPI_RNCR ( 276 ) /* Receive Next Counter Register */ +#define SPI_TNPR ( 280 ) /* Transmit Next Pointer Register */ +#define SPI_TNCR ( 284 ) /* Transmit Next Counter Register */ +#define SPI_PTCR ( 288 ) /* PDC Transfer Control Register */ +#define SPI_PTSR ( 292 ) /* PDC Transfer Status Register */ +/* -------- SPI_CR : (SPI Offset: 0x0) SPI Control Register -------- */ +#define AT91C_SPI_SPIEN ( 0x1 << 0 ) /* (SPI) SPI Enable */ +#define AT91C_SPI_SPIDIS ( 0x1 << 1 ) /* (SPI) SPI Disable */ +#define AT91C_SPI_SWRST ( 0x1 << 7 ) /* (SPI) SPI Software reset */ +#define AT91C_SPI_LASTXFER ( 0x1 << 24 ) /* (SPI) SPI Last Transfer */ +/* -------- SPI_MR : (SPI Offset: 0x4) SPI Mode Register -------- */ +#define AT91C_SPI_MSTR ( 0x1 << 0 ) /* (SPI) Master/Slave Mode */ +#define AT91C_SPI_PS ( 0x1 << 1 ) /* (SPI) Peripheral Select */ +#define AT91C_SPI_PS_FIXED ( 0x0 << 1 ) /* (SPI) Fixed Peripheral Select */ +#define AT91C_SPI_PS_VARIABLE ( 0x1 << 1 ) /* (SPI) Variable Peripheral Select */ +#define AT91C_SPI_PCSDEC ( 0x1 << 2 ) /* (SPI) Chip Select Decode */ +#define AT91C_SPI_FDIV ( 0x1 << 3 ) /* (SPI) Clock Selection */ +#define AT91C_SPI_MODFDIS ( 0x1 << 4 ) /* (SPI) Mode Fault Detection */ +#define AT91C_SPI_LLB ( 0x1 << 7 ) /* (SPI) Clock Selection */ +#define AT91C_SPI_PCS ( 0xF << 16 ) /* (SPI) Peripheral Chip Select */ +#define AT91C_SPI_DLYBCS ( 0xFF << 24 ) /* (SPI) Delay Between Chip Selects */ +/* -------- SPI_RDR : (SPI Offset: 0x8) Receive Data Register -------- */ +#define AT91C_SPI_RD ( 0xFFFF << 0 ) /* (SPI) Receive Data */ +#define AT91C_SPI_RPCS ( 0xF << 16 ) /* (SPI) Peripheral Chip Select Status */ +/* -------- SPI_TDR : (SPI Offset: 0xc) Transmit Data Register -------- */ +#define AT91C_SPI_TD ( 0xFFFF << 0 ) /* (SPI) Transmit Data */ +#define AT91C_SPI_TPCS ( 0xF << 16 ) /* (SPI) Peripheral Chip Select Status */ +/* -------- SPI_SR : (SPI Offset: 0x10) Status Register -------- */ +#define AT91C_SPI_RDRF ( 0x1 << 0 ) /* (SPI) Receive Data Register Full */ +#define AT91C_SPI_TDRE ( 0x1 << 1 ) /* (SPI) Transmit Data Register Empty */ +#define AT91C_SPI_MODF ( 0x1 << 2 ) /* (SPI) Mode Fault Error */ +#define AT91C_SPI_OVRES ( 0x1 << 3 ) /* (SPI) Overrun Error Status */ +#define AT91C_SPI_ENDRX ( 0x1 << 4 ) /* (SPI) End of Receiver Transfer */ +#define AT91C_SPI_ENDTX ( 0x1 << 5 ) /* (SPI) End of Receiver Transfer */ +#define AT91C_SPI_RXBUFF ( 0x1 << 6 ) /* (SPI) RXBUFF Interrupt */ +#define AT91C_SPI_TXBUFE ( 0x1 << 7 ) /* (SPI) TXBUFE Interrupt */ +#define AT91C_SPI_NSSR ( 0x1 << 8 ) /* (SPI) NSSR Interrupt */ +#define AT91C_SPI_TXEMPTY ( 0x1 << 9 ) /* (SPI) TXEMPTY Interrupt */ +#define AT91C_SPI_SPIENS ( 0x1 << 16 ) /* (SPI) Enable Status */ +/* -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register -------- */ +/* -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register -------- */ +/* -------- SPI_IMR : (SPI Offset: 0x1c) Interrupt Mask Register -------- */ +/* -------- SPI_CSR : (SPI Offset: 0x30) Chip Select Register -------- */ +#define AT91C_SPI_CPOL ( 0x1 << 0 ) /* (SPI) Clock Polarity */ +#define AT91C_SPI_NCPHA ( 0x1 << 1 ) /* (SPI) Clock Phase */ +#define AT91C_SPI_CSAAT ( 0x1 << 3 ) /* (SPI) Chip Select Active After Transfer */ +#define AT91C_SPI_BITS ( 0xF << 4 ) /* (SPI) Bits Per Transfer */ +#define AT91C_SPI_BITS_8 ( 0x0 << 4 ) /* (SPI) 8 Bits Per transfer */ +#define AT91C_SPI_BITS_9 ( 0x1 << 4 ) /* (SPI) 9 Bits Per transfer */ +#define AT91C_SPI_BITS_10 ( 0x2 << 4 ) /* (SPI) 10 Bits Per transfer */ +#define AT91C_SPI_BITS_11 ( 0x3 << 4 ) /* (SPI) 11 Bits Per transfer */ +#define AT91C_SPI_BITS_12 ( 0x4 << 4 ) /* (SPI) 12 Bits Per transfer */ +#define AT91C_SPI_BITS_13 ( 0x5 << 4 ) /* (SPI) 13 Bits Per transfer */ +#define AT91C_SPI_BITS_14 ( 0x6 << 4 ) /* (SPI) 14 Bits Per transfer */ +#define AT91C_SPI_BITS_15 ( 0x7 << 4 ) /* (SPI) 15 Bits Per transfer */ +#define AT91C_SPI_BITS_16 ( 0x8 << 4 ) /* (SPI) 16 Bits Per transfer */ +#define AT91C_SPI_SCBR ( 0xFF << 8 ) /* (SPI) Serial Clock Baud Rate */ +#define AT91C_SPI_DLYBS ( 0xFF << 16 ) /* (SPI) Delay Before SPCK */ +#define AT91C_SPI_DLYBCT ( 0xFF << 24 ) /* (SPI) Delay Between Consecutive Transfers */ -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Usart -// ***************************************************************************** -// *** Register offset in AT91S_USART structure *** -#define US_CR ( 0) // Control Register -#define US_MR ( 4) // Mode Register -#define US_IER ( 8) // Interrupt Enable Register -#define US_IDR (12) // Interrupt Disable Register -#define US_IMR (16) // Interrupt Mask Register -#define US_CSR (20) // Channel Status Register -#define US_RHR (24) // Receiver Holding Register -#define US_THR (28) // Transmitter Holding Register -#define US_BRGR (32) // Baud Rate Generator Register -#define US_RTOR (36) // Receiver Time-out Register -#define US_TTGR (40) // Transmitter Time-guard Register -#define US_FIDI (64) // FI_DI_Ratio Register -#define US_NER (68) // Nb Errors Register -#define US_IF (76) // IRDA_FILTER Register -#define US_RPR (256) // Receive Pointer Register -#define US_RCR (260) // Receive Counter Register -#define US_TPR (264) // Transmit Pointer Register -#define US_TCR (268) // Transmit Counter Register -#define US_RNPR (272) // Receive Next Pointer Register -#define US_RNCR (276) // Receive Next Counter Register -#define US_TNPR (280) // Transmit Next Pointer Register -#define US_TNCR (284) // Transmit Next Counter Register -#define US_PTCR (288) // PDC Transfer Control Register -#define US_PTSR (292) // PDC Transfer Status Register -// -------- US_CR : (USART Offset: 0x0) Debug Unit Control Register -------- -#define AT91C_US_STTBRK (0x1 << 9) // (USART) Start Break -#define AT91C_US_STPBRK (0x1 << 10) // (USART) Stop Break -#define AT91C_US_STTTO (0x1 << 11) // (USART) Start Time-out -#define AT91C_US_SENDA (0x1 << 12) // (USART) Send Address -#define AT91C_US_RSTIT (0x1 << 13) // (USART) Reset Iterations -#define AT91C_US_RSTNACK (0x1 << 14) // (USART) Reset Non Acknowledge -#define AT91C_US_RETTO (0x1 << 15) // (USART) Rearm Time-out -#define AT91C_US_DTREN (0x1 << 16) // (USART) Data Terminal ready Enable -#define AT91C_US_DTRDIS (0x1 << 17) // (USART) Data Terminal ready Disable -#define AT91C_US_RTSEN (0x1 << 18) // (USART) Request to Send enable -#define AT91C_US_RTSDIS (0x1 << 19) // (USART) Request to Send Disable -// -------- US_MR : (USART Offset: 0x4) Debug Unit Mode Register -------- -#define AT91C_US_USMODE (0xF << 0) // (USART) Usart mode -#define AT91C_US_USMODE_NORMAL (0x0) // (USART) Normal -#define AT91C_US_USMODE_RS485 (0x1) // (USART) RS485 -#define AT91C_US_USMODE_HWHSH (0x2) // (USART) Hardware Handshaking -#define AT91C_US_USMODE_MODEM (0x3) // (USART) Modem -#define AT91C_US_USMODE_ISO7816_0 (0x4) // (USART) ISO7816 protocol: T = 0 -#define AT91C_US_USMODE_ISO7816_1 (0x6) // (USART) ISO7816 protocol: T = 1 -#define AT91C_US_USMODE_IRDA (0x8) // (USART) IrDA -#define AT91C_US_USMODE_SWHSH (0xC) // (USART) Software Handshaking -#define AT91C_US_CLKS (0x3 << 4) // (USART) Clock Selection (Baud Rate generator Input Clock -#define AT91C_US_CLKS_CLOCK (0x0 << 4) // (USART) Clock -#define AT91C_US_CLKS_FDIV1 (0x1 << 4) // (USART) fdiv1 -#define AT91C_US_CLKS_SLOW (0x2 << 4) // (USART) slow_clock (ARM) -#define AT91C_US_CLKS_EXT (0x3 << 4) // (USART) External (SCK) -#define AT91C_US_CHRL (0x3 << 6) // (USART) Clock Selection (Baud Rate generator Input Clock -#define AT91C_US_CHRL_5_BITS (0x0 << 6) // (USART) Character Length: 5 bits -#define AT91C_US_CHRL_6_BITS (0x1 << 6) // (USART) Character Length: 6 bits -#define AT91C_US_CHRL_7_BITS (0x2 << 6) // (USART) Character Length: 7 bits -#define AT91C_US_CHRL_8_BITS (0x3 << 6) // (USART) Character Length: 8 bits -#define AT91C_US_SYNC (0x1 << 8) // (USART) Synchronous Mode Select -#define AT91C_US_NBSTOP (0x3 << 12) // (USART) Number of Stop bits -#define AT91C_US_NBSTOP_1_BIT (0x0 << 12) // (USART) 1 stop bit -#define AT91C_US_NBSTOP_15_BIT (0x1 << 12) // (USART) Asynchronous (SYNC=0) 2 stop bits Synchronous (SYNC=1) 2 stop bits -#define AT91C_US_NBSTOP_2_BIT (0x2 << 12) // (USART) 2 stop bits -#define AT91C_US_MSBF (0x1 << 16) // (USART) Bit Order -#define AT91C_US_MODE9 (0x1 << 17) // (USART) 9-bit Character length -#define AT91C_US_CKLO (0x1 << 18) // (USART) Clock Output Select -#define AT91C_US_OVER (0x1 << 19) // (USART) Over Sampling Mode -#define AT91C_US_INACK (0x1 << 20) // (USART) Inhibit Non Acknowledge -#define AT91C_US_DSNACK (0x1 << 21) // (USART) Disable Successive NACK -#define AT91C_US_MAX_ITER (0x1 << 24) // (USART) Number of Repetitions -#define AT91C_US_FILTER (0x1 << 28) // (USART) Receive Line Filter -// -------- US_IER : (USART Offset: 0x8) Debug Unit Interrupt Enable Register -------- -#define AT91C_US_RXBRK (0x1 << 2) // (USART) Break Received/End of Break -#define AT91C_US_TIMEOUT (0x1 << 8) // (USART) Receiver Time-out -#define AT91C_US_ITERATION (0x1 << 10) // (USART) Max number of Repetitions Reached -#define AT91C_US_NACK (0x1 << 13) // (USART) Non Acknowledge -#define AT91C_US_RIIC (0x1 << 16) // (USART) Ring INdicator Input Change Flag -#define AT91C_US_DSRIC (0x1 << 17) // (USART) Data Set Ready Input Change Flag -#define AT91C_US_DCDIC (0x1 << 18) // (USART) Data Carrier Flag -#define AT91C_US_CTSIC (0x1 << 19) // (USART) Clear To Send Input Change Flag -// -------- US_IDR : (USART Offset: 0xc) Debug Unit Interrupt Disable Register -------- -// -------- US_IMR : (USART Offset: 0x10) Debug Unit Interrupt Mask Register -------- -// -------- US_CSR : (USART Offset: 0x14) Debug Unit Channel Status Register -------- -#define AT91C_US_RI (0x1 << 20) // (USART) Image of RI Input -#define AT91C_US_DSR (0x1 << 21) // (USART) Image of DSR Input -#define AT91C_US_DCD (0x1 << 22) // (USART) Image of DCD Input -#define AT91C_US_CTS (0x1 << 23) // (USART) Image of CTS Input +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR Usart */ +/* ***************************************************************************** */ +/* *** Register offset in AT91S_USART structure *** */ +#define US_CR ( 0 ) /* Control Register */ +#define US_MR ( 4 ) /* Mode Register */ +#define US_IER ( 8 ) /* Interrupt Enable Register */ +#define US_IDR ( 12 ) /* Interrupt Disable Register */ +#define US_IMR ( 16 ) /* Interrupt Mask Register */ +#define US_CSR ( 20 ) /* Channel Status Register */ +#define US_RHR ( 24 ) /* Receiver Holding Register */ +#define US_THR ( 28 ) /* Transmitter Holding Register */ +#define US_BRGR ( 32 ) /* Baud Rate Generator Register */ +#define US_RTOR ( 36 ) /* Receiver Time-out Register */ +#define US_TTGR ( 40 ) /* Transmitter Time-guard Register */ +#define US_FIDI ( 64 ) /* FI_DI_Ratio Register */ +#define US_NER ( 68 ) /* Nb Errors Register */ +#define US_IF ( 76 ) /* IRDA_FILTER Register */ +#define US_RPR ( 256 ) /* Receive Pointer Register */ +#define US_RCR ( 260 ) /* Receive Counter Register */ +#define US_TPR ( 264 ) /* Transmit Pointer Register */ +#define US_TCR ( 268 ) /* Transmit Counter Register */ +#define US_RNPR ( 272 ) /* Receive Next Pointer Register */ +#define US_RNCR ( 276 ) /* Receive Next Counter Register */ +#define US_TNPR ( 280 ) /* Transmit Next Pointer Register */ +#define US_TNCR ( 284 ) /* Transmit Next Counter Register */ +#define US_PTCR ( 288 ) /* PDC Transfer Control Register */ +#define US_PTSR ( 292 ) /* PDC Transfer Status Register */ +/* -------- US_CR : (USART Offset: 0x0) Debug Unit Control Register -------- */ +#define AT91C_US_STTBRK ( 0x1 << 9 ) /* (USART) Start Break */ +#define AT91C_US_STPBRK ( 0x1 << 10 ) /* (USART) Stop Break */ +#define AT91C_US_STTTO ( 0x1 << 11 ) /* (USART) Start Time-out */ +#define AT91C_US_SENDA ( 0x1 << 12 ) /* (USART) Send Address */ +#define AT91C_US_RSTIT ( 0x1 << 13 ) /* (USART) Reset Iterations */ +#define AT91C_US_RSTNACK ( 0x1 << 14 ) /* (USART) Reset Non Acknowledge */ +#define AT91C_US_RETTO ( 0x1 << 15 ) /* (USART) Rearm Time-out */ +#define AT91C_US_DTREN ( 0x1 << 16 ) /* (USART) Data Terminal ready Enable */ +#define AT91C_US_DTRDIS ( 0x1 << 17 ) /* (USART) Data Terminal ready Disable */ +#define AT91C_US_RTSEN ( 0x1 << 18 ) /* (USART) Request to Send enable */ +#define AT91C_US_RTSDIS ( 0x1 << 19 ) /* (USART) Request to Send Disable */ +/* -------- US_MR : (USART Offset: 0x4) Debug Unit Mode Register -------- */ +#define AT91C_US_USMODE ( 0xF << 0 ) /* (USART) Usart mode */ +#define AT91C_US_USMODE_NORMAL ( 0x0 ) /* (USART) Normal */ +#define AT91C_US_USMODE_RS485 ( 0x1 ) /* (USART) RS485 */ +#define AT91C_US_USMODE_HWHSH ( 0x2 ) /* (USART) Hardware Handshaking */ +#define AT91C_US_USMODE_MODEM ( 0x3 ) /* (USART) Modem */ +#define AT91C_US_USMODE_ISO7816_0 ( 0x4 ) /* (USART) ISO7816 protocol: T = 0 */ +#define AT91C_US_USMODE_ISO7816_1 ( 0x6 ) /* (USART) ISO7816 protocol: T = 1 */ +#define AT91C_US_USMODE_IRDA ( 0x8 ) /* (USART) IrDA */ +#define AT91C_US_USMODE_SWHSH ( 0xC ) /* (USART) Software Handshaking */ +#define AT91C_US_CLKS ( 0x3 << 4 ) /* (USART) Clock Selection (Baud Rate generator Input Clock */ +#define AT91C_US_CLKS_CLOCK ( 0x0 << 4 ) /* (USART) Clock */ +#define AT91C_US_CLKS_FDIV1 ( 0x1 << 4 ) /* (USART) fdiv1 */ +#define AT91C_US_CLKS_SLOW ( 0x2 << 4 ) /* (USART) slow_clock (ARM) */ +#define AT91C_US_CLKS_EXT ( 0x3 << 4 ) /* (USART) External (SCK) */ +#define AT91C_US_CHRL ( 0x3 << 6 ) /* (USART) Clock Selection (Baud Rate generator Input Clock */ +#define AT91C_US_CHRL_5_BITS ( 0x0 << 6 ) /* (USART) Character Length: 5 bits */ +#define AT91C_US_CHRL_6_BITS ( 0x1 << 6 ) /* (USART) Character Length: 6 bits */ +#define AT91C_US_CHRL_7_BITS ( 0x2 << 6 ) /* (USART) Character Length: 7 bits */ +#define AT91C_US_CHRL_8_BITS ( 0x3 << 6 ) /* (USART) Character Length: 8 bits */ +#define AT91C_US_SYNC ( 0x1 << 8 ) /* (USART) Synchronous Mode Select */ +#define AT91C_US_NBSTOP ( 0x3 << 12 ) /* (USART) Number of Stop bits */ +#define AT91C_US_NBSTOP_1_BIT ( 0x0 << 12 ) /* (USART) 1 stop bit */ +#define AT91C_US_NBSTOP_15_BIT ( 0x1 << 12 ) /* (USART) Asynchronous (SYNC=0) 2 stop bits Synchronous (SYNC=1) 2 stop bits */ +#define AT91C_US_NBSTOP_2_BIT ( 0x2 << 12 ) /* (USART) 2 stop bits */ +#define AT91C_US_MSBF ( 0x1 << 16 ) /* (USART) Bit Order */ +#define AT91C_US_MODE9 ( 0x1 << 17 ) /* (USART) 9-bit Character length */ +#define AT91C_US_CKLO ( 0x1 << 18 ) /* (USART) Clock Output Select */ +#define AT91C_US_OVER ( 0x1 << 19 ) /* (USART) Over Sampling Mode */ +#define AT91C_US_INACK ( 0x1 << 20 ) /* (USART) Inhibit Non Acknowledge */ +#define AT91C_US_DSNACK ( 0x1 << 21 ) /* (USART) Disable Successive NACK */ +#define AT91C_US_MAX_ITER ( 0x1 << 24 ) /* (USART) Number of Repetitions */ +#define AT91C_US_FILTER ( 0x1 << 28 ) /* (USART) Receive Line Filter */ +/* -------- US_IER : (USART Offset: 0x8) Debug Unit Interrupt Enable Register -------- */ +#define AT91C_US_RXBRK ( 0x1 << 2 ) /* (USART) Break Received/End of Break */ +#define AT91C_US_TIMEOUT ( 0x1 << 8 ) /* (USART) Receiver Time-out */ +#define AT91C_US_ITERATION ( 0x1 << 10 ) /* (USART) Max number of Repetitions Reached */ +#define AT91C_US_NACK ( 0x1 << 13 ) /* (USART) Non Acknowledge */ +#define AT91C_US_RIIC ( 0x1 << 16 ) /* (USART) Ring INdicator Input Change Flag */ +#define AT91C_US_DSRIC ( 0x1 << 17 ) /* (USART) Data Set Ready Input Change Flag */ +#define AT91C_US_DCDIC ( 0x1 << 18 ) /* (USART) Data Carrier Flag */ +#define AT91C_US_CTSIC ( 0x1 << 19 ) /* (USART) Clear To Send Input Change Flag */ +/* -------- US_IDR : (USART Offset: 0xc) Debug Unit Interrupt Disable Register -------- */ +/* -------- US_IMR : (USART Offset: 0x10) Debug Unit Interrupt Mask Register -------- */ +/* -------- US_CSR : (USART Offset: 0x14) Debug Unit Channel Status Register -------- */ +#define AT91C_US_RI ( 0x1 << 20 ) /* (USART) Image of RI Input */ +#define AT91C_US_DSR ( 0x1 << 21 ) /* (USART) Image of DSR Input */ +#define AT91C_US_DCD ( 0x1 << 22 ) /* (USART) Image of DCD Input */ +#define AT91C_US_CTS ( 0x1 << 23 ) /* (USART) Image of CTS Input */ -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Synchronous Serial Controller Interface -// ***************************************************************************** -// *** Register offset in AT91S_SSC structure *** -#define SSC_CR ( 0) // Control Register -#define SSC_CMR ( 4) // Clock Mode Register -#define SSC_RCMR (16) // Receive Clock ModeRegister -#define SSC_RFMR (20) // Receive Frame Mode Register -#define SSC_TCMR (24) // Transmit Clock Mode Register -#define SSC_TFMR (28) // Transmit Frame Mode Register -#define SSC_RHR (32) // Receive Holding Register -#define SSC_THR (36) // Transmit Holding Register -#define SSC_RSHR (48) // Receive Sync Holding Register -#define SSC_TSHR (52) // Transmit Sync Holding Register -#define SSC_SR (64) // Status Register -#define SSC_IER (68) // Interrupt Enable Register -#define SSC_IDR (72) // Interrupt Disable Register -#define SSC_IMR (76) // Interrupt Mask Register -#define SSC_RPR (256) // Receive Pointer Register -#define SSC_RCR (260) // Receive Counter Register -#define SSC_TPR (264) // Transmit Pointer Register -#define SSC_TCR (268) // Transmit Counter Register -#define SSC_RNPR (272) // Receive Next Pointer Register -#define SSC_RNCR (276) // Receive Next Counter Register -#define SSC_TNPR (280) // Transmit Next Pointer Register -#define SSC_TNCR (284) // Transmit Next Counter Register -#define SSC_PTCR (288) // PDC Transfer Control Register -#define SSC_PTSR (292) // PDC Transfer Status Register -// -------- SSC_CR : (SSC Offset: 0x0) SSC Control Register -------- -#define AT91C_SSC_RXEN (0x1 << 0) // (SSC) Receive Enable -#define AT91C_SSC_RXDIS (0x1 << 1) // (SSC) Receive Disable -#define AT91C_SSC_TXEN (0x1 << 8) // (SSC) Transmit Enable -#define AT91C_SSC_TXDIS (0x1 << 9) // (SSC) Transmit Disable -#define AT91C_SSC_SWRST (0x1 << 15) // (SSC) Software Reset -// -------- SSC_RCMR : (SSC Offset: 0x10) SSC Receive Clock Mode Register -------- -#define AT91C_SSC_CKS (0x3 << 0) // (SSC) Receive/Transmit Clock Selection -#define AT91C_SSC_CKS_DIV (0x0) // (SSC) Divided Clock -#define AT91C_SSC_CKS_TK (0x1) // (SSC) TK Clock signal -#define AT91C_SSC_CKS_RK (0x2) // (SSC) RK pin -#define AT91C_SSC_CKO (0x7 << 2) // (SSC) Receive/Transmit Clock Output Mode Selection -#define AT91C_SSC_CKO_NONE (0x0 << 2) // (SSC) Receive/Transmit Clock Output Mode: None RK pin: Input-only -#define AT91C_SSC_CKO_CONTINOUS (0x1 << 2) // (SSC) Continuous Receive/Transmit Clock RK pin: Output -#define AT91C_SSC_CKO_DATA_TX (0x2 << 2) // (SSC) Receive/Transmit Clock only during data transfers RK pin: Output -#define AT91C_SSC_CKI (0x1 << 5) // (SSC) Receive/Transmit Clock Inversion -#define AT91C_SSC_START (0xF << 8) // (SSC) Receive/Transmit Start Selection -#define AT91C_SSC_START_CONTINOUS (0x0 << 8) // (SSC) Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data. -#define AT91C_SSC_START_TX (0x1 << 8) // (SSC) Transmit/Receive start -#define AT91C_SSC_START_LOW_RF (0x2 << 8) // (SSC) Detection of a low level on RF input -#define AT91C_SSC_START_HIGH_RF (0x3 << 8) // (SSC) Detection of a high level on RF input -#define AT91C_SSC_START_FALL_RF (0x4 << 8) // (SSC) Detection of a falling edge on RF input -#define AT91C_SSC_START_RISE_RF (0x5 << 8) // (SSC) Detection of a rising edge on RF input -#define AT91C_SSC_START_LEVEL_RF (0x6 << 8) // (SSC) Detection of any level change on RF input -#define AT91C_SSC_START_EDGE_RF (0x7 << 8) // (SSC) Detection of any edge on RF input -#define AT91C_SSC_START_0 (0x8 << 8) // (SSC) Compare 0 -#define AT91C_SSC_STTDLY (0xFF << 16) // (SSC) Receive/Transmit Start Delay -#define AT91C_SSC_PERIOD (0xFF << 24) // (SSC) Receive/Transmit Period Divider Selection -// -------- SSC_RFMR : (SSC Offset: 0x14) SSC Receive Frame Mode Register -------- -#define AT91C_SSC_DATLEN (0x1F << 0) // (SSC) Data Length -#define AT91C_SSC_LOOP (0x1 << 5) // (SSC) Loop Mode -#define AT91C_SSC_MSBF (0x1 << 7) // (SSC) Most Significant Bit First -#define AT91C_SSC_DATNB (0xF << 8) // (SSC) Data Number per Frame -#define AT91C_SSC_FSLEN (0xF << 16) // (SSC) Receive/Transmit Frame Sync length -#define AT91C_SSC_FSOS (0x7 << 20) // (SSC) Receive/Transmit Frame Sync Output Selection -#define AT91C_SSC_FSOS_NONE (0x0 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: None RK pin Input-only -#define AT91C_SSC_FSOS_NEGATIVE (0x1 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Negative Pulse -#define AT91C_SSC_FSOS_POSITIVE (0x2 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Positive Pulse -#define AT91C_SSC_FSOS_LOW (0x3 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver Low during data transfer -#define AT91C_SSC_FSOS_HIGH (0x4 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver High during data transfer -#define AT91C_SSC_FSOS_TOGGLE (0x5 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Toggling at each start of data transfer -#define AT91C_SSC_FSEDGE (0x1 << 24) // (SSC) Frame Sync Edge Detection -// -------- SSC_TCMR : (SSC Offset: 0x18) SSC Transmit Clock Mode Register -------- -// -------- SSC_TFMR : (SSC Offset: 0x1c) SSC Transmit Frame Mode Register -------- -#define AT91C_SSC_DATDEF (0x1 << 5) // (SSC) Data Default Value -#define AT91C_SSC_FSDEN (0x1 << 23) // (SSC) Frame Sync Data Enable -// -------- SSC_SR : (SSC Offset: 0x40) SSC Status Register -------- -#define AT91C_SSC_TXRDY (0x1 << 0) // (SSC) Transmit Ready -#define AT91C_SSC_TXEMPTY (0x1 << 1) // (SSC) Transmit Empty -#define AT91C_SSC_ENDTX (0x1 << 2) // (SSC) End Of Transmission -#define AT91C_SSC_TXBUFE (0x1 << 3) // (SSC) Transmit Buffer Empty -#define AT91C_SSC_RXRDY (0x1 << 4) // (SSC) Receive Ready -#define AT91C_SSC_OVRUN (0x1 << 5) // (SSC) Receive Overrun -#define AT91C_SSC_ENDRX (0x1 << 6) // (SSC) End of Reception -#define AT91C_SSC_RXBUFF (0x1 << 7) // (SSC) Receive Buffer Full -#define AT91C_SSC_TXSYN (0x1 << 10) // (SSC) Transmit Sync -#define AT91C_SSC_RXSYN (0x1 << 11) // (SSC) Receive Sync -#define AT91C_SSC_TXENA (0x1 << 16) // (SSC) Transmit Enable -#define AT91C_SSC_RXENA (0x1 << 17) // (SSC) Receive Enable -// -------- SSC_IER : (SSC Offset: 0x44) SSC Interrupt Enable Register -------- -// -------- SSC_IDR : (SSC Offset: 0x48) SSC Interrupt Disable Register -------- -// -------- SSC_IMR : (SSC Offset: 0x4c) SSC Interrupt Mask Register -------- +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR Synchronous Serial Controller Interface */ +/* ***************************************************************************** */ +/* *** Register offset in AT91S_SSC structure *** */ +#define SSC_CR ( 0 ) /* Control Register */ +#define SSC_CMR ( 4 ) /* Clock Mode Register */ +#define SSC_RCMR ( 16 ) /* Receive Clock ModeRegister */ +#define SSC_RFMR ( 20 ) /* Receive Frame Mode Register */ +#define SSC_TCMR ( 24 ) /* Transmit Clock Mode Register */ +#define SSC_TFMR ( 28 ) /* Transmit Frame Mode Register */ +#define SSC_RHR ( 32 ) /* Receive Holding Register */ +#define SSC_THR ( 36 ) /* Transmit Holding Register */ +#define SSC_RSHR ( 48 ) /* Receive Sync Holding Register */ +#define SSC_TSHR ( 52 ) /* Transmit Sync Holding Register */ +#define SSC_SR ( 64 ) /* Status Register */ +#define SSC_IER ( 68 ) /* Interrupt Enable Register */ +#define SSC_IDR ( 72 ) /* Interrupt Disable Register */ +#define SSC_IMR ( 76 ) /* Interrupt Mask Register */ +#define SSC_RPR ( 256 ) /* Receive Pointer Register */ +#define SSC_RCR ( 260 ) /* Receive Counter Register */ +#define SSC_TPR ( 264 ) /* Transmit Pointer Register */ +#define SSC_TCR ( 268 ) /* Transmit Counter Register */ +#define SSC_RNPR ( 272 ) /* Receive Next Pointer Register */ +#define SSC_RNCR ( 276 ) /* Receive Next Counter Register */ +#define SSC_TNPR ( 280 ) /* Transmit Next Pointer Register */ +#define SSC_TNCR ( 284 ) /* Transmit Next Counter Register */ +#define SSC_PTCR ( 288 ) /* PDC Transfer Control Register */ +#define SSC_PTSR ( 292 ) /* PDC Transfer Status Register */ +/* -------- SSC_CR : (SSC Offset: 0x0) SSC Control Register -------- */ +#define AT91C_SSC_RXEN ( 0x1 << 0 ) /* (SSC) Receive Enable */ +#define AT91C_SSC_RXDIS ( 0x1 << 1 ) /* (SSC) Receive Disable */ +#define AT91C_SSC_TXEN ( 0x1 << 8 ) /* (SSC) Transmit Enable */ +#define AT91C_SSC_TXDIS ( 0x1 << 9 ) /* (SSC) Transmit Disable */ +#define AT91C_SSC_SWRST ( 0x1 << 15 ) /* (SSC) Software Reset */ +/* -------- SSC_RCMR : (SSC Offset: 0x10) SSC Receive Clock Mode Register -------- */ +#define AT91C_SSC_CKS ( 0x3 << 0 ) /* (SSC) Receive/Transmit Clock Selection */ +#define AT91C_SSC_CKS_DIV ( 0x0 ) /* (SSC) Divided Clock */ +#define AT91C_SSC_CKS_TK ( 0x1 ) /* (SSC) TK Clock signal */ +#define AT91C_SSC_CKS_RK ( 0x2 ) /* (SSC) RK pin */ +#define AT91C_SSC_CKO ( 0x7 << 2 ) /* (SSC) Receive/Transmit Clock Output Mode Selection */ +#define AT91C_SSC_CKO_NONE ( 0x0 << 2 ) /* (SSC) Receive/Transmit Clock Output Mode: None RK pin: Input-only */ +#define AT91C_SSC_CKO_CONTINUOUS ( 0x1 << 2 ) /* (SSC) Continuous Receive/Transmit Clock RK pin: Output */ +#define AT91C_SSC_CKO_DATA_TX ( 0x2 << 2 ) /* (SSC) Receive/Transmit Clock only during data transfers RK pin: Output */ +#define AT91C_SSC_CKI ( 0x1 << 5 ) /* (SSC) Receive/Transmit Clock Inversion */ +#define AT91C_SSC_START ( 0xF << 8 ) /* (SSC) Receive/Transmit Start Selection */ +#define AT91C_SSC_START_CONTINUOUS ( 0x0 << 8 ) /* (SSC) Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data. */ +#define AT91C_SSC_START_TX ( 0x1 << 8 ) /* (SSC) Transmit/Receive start */ +#define AT91C_SSC_START_LOW_RF ( 0x2 << 8 ) /* (SSC) Detection of a low level on RF input */ +#define AT91C_SSC_START_HIGH_RF ( 0x3 << 8 ) /* (SSC) Detection of a high level on RF input */ +#define AT91C_SSC_START_FALL_RF ( 0x4 << 8 ) /* (SSC) Detection of a falling edge on RF input */ +#define AT91C_SSC_START_RISE_RF ( 0x5 << 8 ) /* (SSC) Detection of a rising edge on RF input */ +#define AT91C_SSC_START_LEVEL_RF ( 0x6 << 8 ) /* (SSC) Detection of any level change on RF input */ +#define AT91C_SSC_START_EDGE_RF ( 0x7 << 8 ) /* (SSC) Detection of any edge on RF input */ +#define AT91C_SSC_START_0 ( 0x8 << 8 ) /* (SSC) Compare 0 */ +#define AT91C_SSC_STTDLY ( 0xFF << 16 ) /* (SSC) Receive/Transmit Start Delay */ +#define AT91C_SSC_PERIOD ( 0xFF << 24 ) /* (SSC) Receive/Transmit Period Divider Selection */ +/* -------- SSC_RFMR : (SSC Offset: 0x14) SSC Receive Frame Mode Register -------- */ +#define AT91C_SSC_DATLEN ( 0x1F << 0 ) /* (SSC) Data Length */ +#define AT91C_SSC_LOOP ( 0x1 << 5 ) /* (SSC) Loop Mode */ +#define AT91C_SSC_MSBF ( 0x1 << 7 ) /* (SSC) Most Significant Bit First */ +#define AT91C_SSC_DATNB ( 0xF << 8 ) /* (SSC) Data Number per Frame */ +#define AT91C_SSC_FSLEN ( 0xF << 16 ) /* (SSC) Receive/Transmit Frame Sync length */ +#define AT91C_SSC_FSOS ( 0x7 << 20 ) /* (SSC) Receive/Transmit Frame Sync Output Selection */ +#define AT91C_SSC_FSOS_NONE ( 0x0 << 20 ) /* (SSC) Selected Receive/Transmit Frame Sync Signal: None RK pin Input-only */ +#define AT91C_SSC_FSOS_NEGATIVE ( 0x1 << 20 ) /* (SSC) Selected Receive/Transmit Frame Sync Signal: Negative Pulse */ +#define AT91C_SSC_FSOS_POSITIVE ( 0x2 << 20 ) /* (SSC) Selected Receive/Transmit Frame Sync Signal: Positive Pulse */ +#define AT91C_SSC_FSOS_LOW ( 0x3 << 20 ) /* (SSC) Selected Receive/Transmit Frame Sync Signal: Driver Low during data transfer */ +#define AT91C_SSC_FSOS_HIGH ( 0x4 << 20 ) /* (SSC) Selected Receive/Transmit Frame Sync Signal: Driver High during data transfer */ +#define AT91C_SSC_FSOS_TOGGLE ( 0x5 << 20 ) /* (SSC) Selected Receive/Transmit Frame Sync Signal: Toggling at each start of data transfer */ +#define AT91C_SSC_FSEDGE ( 0x1 << 24 ) /* (SSC) Frame Sync Edge Detection */ +/* -------- SSC_TCMR : (SSC Offset: 0x18) SSC Transmit Clock Mode Register -------- */ +/* -------- SSC_TFMR : (SSC Offset: 0x1c) SSC Transmit Frame Mode Register -------- */ +#define AT91C_SSC_DATDEF ( 0x1 << 5 ) /* (SSC) Data Default Value */ +#define AT91C_SSC_FSDEN ( 0x1 << 23 ) /* (SSC) Frame Sync Data Enable */ +/* -------- SSC_SR : (SSC Offset: 0x40) SSC Status Register -------- */ +#define AT91C_SSC_TXRDY ( 0x1 << 0 ) /* (SSC) Transmit Ready */ +#define AT91C_SSC_TXEMPTY ( 0x1 << 1 ) /* (SSC) Transmit Empty */ +#define AT91C_SSC_ENDTX ( 0x1 << 2 ) /* (SSC) End Of Transmission */ +#define AT91C_SSC_TXBUFE ( 0x1 << 3 ) /* (SSC) Transmit Buffer Empty */ +#define AT91C_SSC_RXRDY ( 0x1 << 4 ) /* (SSC) Receive Ready */ +#define AT91C_SSC_OVRUN ( 0x1 << 5 ) /* (SSC) Receive Overrun */ +#define AT91C_SSC_ENDRX ( 0x1 << 6 ) /* (SSC) End of Reception */ +#define AT91C_SSC_RXBUFF ( 0x1 << 7 ) /* (SSC) Receive Buffer Full */ +#define AT91C_SSC_TXSYN ( 0x1 << 10 ) /* (SSC) Transmit Sync */ +#define AT91C_SSC_RXSYN ( 0x1 << 11 ) /* (SSC) Receive Sync */ +#define AT91C_SSC_TXENA ( 0x1 << 16 ) /* (SSC) Transmit Enable */ +#define AT91C_SSC_RXENA ( 0x1 << 17 ) /* (SSC) Receive Enable */ +/* -------- SSC_IER : (SSC Offset: 0x44) SSC Interrupt Enable Register -------- */ +/* -------- SSC_IDR : (SSC Offset: 0x48) SSC Interrupt Disable Register -------- */ +/* -------- SSC_IMR : (SSC Offset: 0x4c) SSC Interrupt Mask Register -------- */ -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Two-wire Interface -// ***************************************************************************** -// *** Register offset in AT91S_TWI structure *** -#define TWI_CR ( 0) // Control Register -#define TWI_MMR ( 4) // Master Mode Register -#define TWI_IADR (12) // Internal Address Register -#define TWI_CWGR (16) // Clock Waveform Generator Register -#define TWI_SR (32) // Status Register -#define TWI_IER (36) // Interrupt Enable Register -#define TWI_IDR (40) // Interrupt Disable Register -#define TWI_IMR (44) // Interrupt Mask Register -#define TWI_RHR (48) // Receive Holding Register -#define TWI_THR (52) // Transmit Holding Register -// -------- TWI_CR : (TWI Offset: 0x0) TWI Control Register -------- -#define AT91C_TWI_START (0x1 << 0) // (TWI) Send a START Condition -#define AT91C_TWI_STOP (0x1 << 1) // (TWI) Send a STOP Condition -#define AT91C_TWI_MSEN (0x1 << 2) // (TWI) TWI Master Transfer Enabled -#define AT91C_TWI_MSDIS (0x1 << 3) // (TWI) TWI Master Transfer Disabled -#define AT91C_TWI_SWRST (0x1 << 7) // (TWI) Software Reset -// -------- TWI_MMR : (TWI Offset: 0x4) TWI Master Mode Register -------- -#define AT91C_TWI_IADRSZ (0x3 << 8) // (TWI) Internal Device Address Size -#define AT91C_TWI_IADRSZ_NO (0x0 << 8) // (TWI) No internal device address -#define AT91C_TWI_IADRSZ_1_BYTE (0x1 << 8) // (TWI) One-byte internal device address -#define AT91C_TWI_IADRSZ_2_BYTE (0x2 << 8) // (TWI) Two-byte internal device address -#define AT91C_TWI_IADRSZ_3_BYTE (0x3 << 8) // (TWI) Three-byte internal device address -#define AT91C_TWI_MREAD (0x1 << 12) // (TWI) Master Read Direction -#define AT91C_TWI_DADR (0x7F << 16) // (TWI) Device Address -// -------- TWI_CWGR : (TWI Offset: 0x10) TWI Clock Waveform Generator Register -------- -#define AT91C_TWI_CLDIV (0xFF << 0) // (TWI) Clock Low Divider -#define AT91C_TWI_CHDIV (0xFF << 8) // (TWI) Clock High Divider -#define AT91C_TWI_CKDIV (0x7 << 16) // (TWI) Clock Divider -// -------- TWI_SR : (TWI Offset: 0x20) TWI Status Register -------- -#define AT91C_TWI_TXCOMP (0x1 << 0) // (TWI) Transmission Completed -#define AT91C_TWI_RXRDY (0x1 << 1) // (TWI) Receive holding register ReaDY -#define AT91C_TWI_TXRDY (0x1 << 2) // (TWI) Transmit holding register ReaDY -#define AT91C_TWI_OVRE (0x1 << 6) // (TWI) Overrun Error -#define AT91C_TWI_UNRE (0x1 << 7) // (TWI) Underrun Error -#define AT91C_TWI_NACK (0x1 << 8) // (TWI) Not Acknowledged -// -------- TWI_IER : (TWI Offset: 0x24) TWI Interrupt Enable Register -------- -// -------- TWI_IDR : (TWI Offset: 0x28) TWI Interrupt Disable Register -------- -// -------- TWI_IMR : (TWI Offset: 0x2c) TWI Interrupt Mask Register -------- +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR Two-wire Interface */ +/* ***************************************************************************** */ +/* *** Register offset in AT91S_TWI structure *** */ +#define TWI_CR ( 0 ) /* Control Register */ +#define TWI_MMR ( 4 ) /* Master Mode Register */ +#define TWI_IADR ( 12 ) /* Internal Address Register */ +#define TWI_CWGR ( 16 ) /* Clock Waveform Generator Register */ +#define TWI_SR ( 32 ) /* Status Register */ +#define TWI_IER ( 36 ) /* Interrupt Enable Register */ +#define TWI_IDR ( 40 ) /* Interrupt Disable Register */ +#define TWI_IMR ( 44 ) /* Interrupt Mask Register */ +#define TWI_RHR ( 48 ) /* Receive Holding Register */ +#define TWI_THR ( 52 ) /* Transmit Holding Register */ +/* -------- TWI_CR : (TWI Offset: 0x0) TWI Control Register -------- */ +#define AT91C_TWI_START ( 0x1 << 0 ) /* (TWI) Send a START Condition */ +#define AT91C_TWI_STOP ( 0x1 << 1 ) /* (TWI) Send a STOP Condition */ +#define AT91C_TWI_MSEN ( 0x1 << 2 ) /* (TWI) TWI Master Transfer Enabled */ +#define AT91C_TWI_MSDIS ( 0x1 << 3 ) /* (TWI) TWI Master Transfer Disabled */ +#define AT91C_TWI_SWRST ( 0x1 << 7 ) /* (TWI) Software Reset */ +/* -------- TWI_MMR : (TWI Offset: 0x4) TWI Master Mode Register -------- */ +#define AT91C_TWI_IADRSZ ( 0x3 << 8 ) /* (TWI) Internal Device Address Size */ +#define AT91C_TWI_IADRSZ_NO ( 0x0 << 8 ) /* (TWI) No internal device address */ +#define AT91C_TWI_IADRSZ_1_BYTE ( 0x1 << 8 ) /* (TWI) One-byte internal device address */ +#define AT91C_TWI_IADRSZ_2_BYTE ( 0x2 << 8 ) /* (TWI) Two-byte internal device address */ +#define AT91C_TWI_IADRSZ_3_BYTE ( 0x3 << 8 ) /* (TWI) Three-byte internal device address */ +#define AT91C_TWI_MREAD ( 0x1 << 12 ) /* (TWI) Master Read Direction */ +#define AT91C_TWI_DADR ( 0x7F << 16 ) /* (TWI) Device Address */ +/* -------- TWI_CWGR : (TWI Offset: 0x10) TWI Clock Waveform Generator Register -------- */ +#define AT91C_TWI_CLDIV ( 0xFF << 0 ) /* (TWI) Clock Low Divider */ +#define AT91C_TWI_CHDIV ( 0xFF << 8 ) /* (TWI) Clock High Divider */ +#define AT91C_TWI_CKDIV ( 0x7 << 16 ) /* (TWI) Clock Divider */ +/* -------- TWI_SR : (TWI Offset: 0x20) TWI Status Register -------- */ +#define AT91C_TWI_TXCOMP ( 0x1 << 0 ) /* (TWI) Transmission Completed */ +#define AT91C_TWI_RXRDY ( 0x1 << 1 ) /* (TWI) Receive holding register ReaDY */ +#define AT91C_TWI_TXRDY ( 0x1 << 2 ) /* (TWI) Transmit holding register ReaDY */ +#define AT91C_TWI_OVRE ( 0x1 << 6 ) /* (TWI) Overrun Error */ +#define AT91C_TWI_UNRE ( 0x1 << 7 ) /* (TWI) Underrun Error */ +#define AT91C_TWI_NACK ( 0x1 << 8 ) /* (TWI) Not Acknowledged */ +/* -------- TWI_IER : (TWI Offset: 0x24) TWI Interrupt Enable Register -------- */ +/* -------- TWI_IDR : (TWI Offset: 0x28) TWI Interrupt Disable Register -------- */ +/* -------- TWI_IMR : (TWI Offset: 0x2c) TWI Interrupt Mask Register -------- */ -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR PWMC Channel Interface -// ***************************************************************************** -// *** Register offset in AT91S_PWMC_CH structure *** -#define PWMC_CMR ( 0) // Channel Mode Register -#define PWMC_CDTYR ( 4) // Channel Duty Cycle Register -#define PWMC_CPRDR ( 8) // Channel Period Register -#define PWMC_CCNTR (12) // Channel Counter Register -#define PWMC_CUPDR (16) // Channel Update Register -#define PWMC_Reserved (20) // Reserved -// -------- PWMC_CMR : (PWMC_CH Offset: 0x0) PWMC Channel Mode Register -------- -#define AT91C_PWMC_CPRE (0xF << 0) // (PWMC_CH) Channel Pre-scaler : PWMC_CLKx -#define AT91C_PWMC_CPRE_MCK (0x0) // (PWMC_CH) -#define AT91C_PWMC_CPRE_MCKA (0xB) // (PWMC_CH) -#define AT91C_PWMC_CPRE_MCKB (0xC) // (PWMC_CH) -#define AT91C_PWMC_CALG (0x1 << 8) // (PWMC_CH) Channel Alignment -#define AT91C_PWMC_CPOL (0x1 << 9) // (PWMC_CH) Channel Polarity -#define AT91C_PWMC_CPD (0x1 << 10) // (PWMC_CH) Channel Update Period -// -------- PWMC_CDTYR : (PWMC_CH Offset: 0x4) PWMC Channel Duty Cycle Register -------- -#define AT91C_PWMC_CDTY (0x0 << 0) // (PWMC_CH) Channel Duty Cycle -// -------- PWMC_CPRDR : (PWMC_CH Offset: 0x8) PWMC Channel Period Register -------- -#define AT91C_PWMC_CPRD (0x0 << 0) // (PWMC_CH) Channel Period -// -------- PWMC_CCNTR : (PWMC_CH Offset: 0xc) PWMC Channel Counter Register -------- -#define AT91C_PWMC_CCNT (0x0 << 0) // (PWMC_CH) Channel Counter -// -------- PWMC_CUPDR : (PWMC_CH Offset: 0x10) PWMC Channel Update Register -------- -#define AT91C_PWMC_CUPD (0x0 << 0) // (PWMC_CH) Channel Update +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR PWMC Channel Interface */ +/* ***************************************************************************** */ +/* *** Register offset in AT91S_PWMC_CH structure *** */ +#define PWMC_CMR ( 0 ) /* Channel Mode Register */ +#define PWMC_CDTYR ( 4 ) /* Channel Duty Cycle Register */ +#define PWMC_CPRDR ( 8 ) /* Channel Period Register */ +#define PWMC_CCNTR ( 12 ) /* Channel Counter Register */ +#define PWMC_CUPDR ( 16 ) /* Channel Update Register */ +#define PWMC_Reserved ( 20 ) /* Reserved */ +/* -------- PWMC_CMR : (PWMC_CH Offset: 0x0) PWMC Channel Mode Register -------- */ +#define AT91C_PWMC_CPRE ( 0xF << 0 ) /* (PWMC_CH) Channel Pre-scaler : PWMC_CLKx */ +#define AT91C_PWMC_CPRE_MCK ( 0x0 ) /* (PWMC_CH) */ +#define AT91C_PWMC_CPRE_MCKA ( 0xB ) /* (PWMC_CH) */ +#define AT91C_PWMC_CPRE_MCKB ( 0xC ) /* (PWMC_CH) */ +#define AT91C_PWMC_CALG ( 0x1 << 8 ) /* (PWMC_CH) Channel Alignment */ +#define AT91C_PWMC_CPOL ( 0x1 << 9 ) /* (PWMC_CH) Channel Polarity */ +#define AT91C_PWMC_CPD ( 0x1 << 10 ) /* (PWMC_CH) Channel Update Period */ +/* -------- PWMC_CDTYR : (PWMC_CH Offset: 0x4) PWMC Channel Duty Cycle Register -------- */ +#define AT91C_PWMC_CDTY ( 0x0 << 0 ) /* (PWMC_CH) Channel Duty Cycle */ +/* -------- PWMC_CPRDR : (PWMC_CH Offset: 0x8) PWMC Channel Period Register -------- */ +#define AT91C_PWMC_CPRD ( 0x0 << 0 ) /* (PWMC_CH) Channel Period */ +/* -------- PWMC_CCNTR : (PWMC_CH Offset: 0xc) PWMC Channel Counter Register -------- */ +#define AT91C_PWMC_CCNT ( 0x0 << 0 ) /* (PWMC_CH) Channel Counter */ +/* -------- PWMC_CUPDR : (PWMC_CH Offset: 0x10) PWMC Channel Update Register -------- */ +#define AT91C_PWMC_CUPD ( 0x0 << 0 ) /* (PWMC_CH) Channel Update */ -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Pulse Width Modulation Controller Interface -// ***************************************************************************** -// *** Register offset in AT91S_PWMC structure *** -#define PWMC_MR ( 0) // PWMC Mode Register -#define PWMC_ENA ( 4) // PWMC Enable Register -#define PWMC_DIS ( 8) // PWMC Disable Register -#define PWMC_SR (12) // PWMC Status Register -#define PWMC_IER (16) // PWMC Interrupt Enable Register -#define PWMC_IDR (20) // PWMC Interrupt Disable Register -#define PWMC_IMR (24) // PWMC Interrupt Mask Register -#define PWMC_ISR (28) // PWMC Interrupt Status Register -#define PWMC_VR (252) // PWMC Version Register -#define PWMC_CH (512) // PWMC Channel -// -------- PWMC_MR : (PWMC Offset: 0x0) PWMC Mode Register -------- -#define AT91C_PWMC_DIVA (0xFF << 0) // (PWMC) CLKA divide factor. -#define AT91C_PWMC_PREA (0xF << 8) // (PWMC) Divider Input Clock Prescaler A -#define AT91C_PWMC_PREA_MCK (0x0 << 8) // (PWMC) -#define AT91C_PWMC_DIVB (0xFF << 16) // (PWMC) CLKB divide factor. -#define AT91C_PWMC_PREB (0xF << 24) // (PWMC) Divider Input Clock Prescaler B -#define AT91C_PWMC_PREB_MCK (0x0 << 24) // (PWMC) -// -------- PWMC_ENA : (PWMC Offset: 0x4) PWMC Enable Register -------- -#define AT91C_PWMC_CHID0 (0x1 << 0) // (PWMC) Channel ID 0 -#define AT91C_PWMC_CHID1 (0x1 << 1) // (PWMC) Channel ID 1 -#define AT91C_PWMC_CHID2 (0x1 << 2) // (PWMC) Channel ID 2 -#define AT91C_PWMC_CHID3 (0x1 << 3) // (PWMC) Channel ID 3 -// -------- PWMC_DIS : (PWMC Offset: 0x8) PWMC Disable Register -------- -// -------- PWMC_SR : (PWMC Offset: 0xc) PWMC Status Register -------- -// -------- PWMC_IER : (PWMC Offset: 0x10) PWMC Interrupt Enable Register -------- -// -------- PWMC_IDR : (PWMC Offset: 0x14) PWMC Interrupt Disable Register -------- -// -------- PWMC_IMR : (PWMC Offset: 0x18) PWMC Interrupt Mask Register -------- -// -------- PWMC_ISR : (PWMC Offset: 0x1c) PWMC Interrupt Status Register -------- +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR Pulse Width Modulation Controller Interface */ +/* ***************************************************************************** */ +/* *** Register offset in AT91S_PWMC structure *** */ +#define PWMC_MR ( 0 ) /* PWMC Mode Register */ +#define PWMC_ENA ( 4 ) /* PWMC Enable Register */ +#define PWMC_DIS ( 8 ) /* PWMC Disable Register */ +#define PWMC_SR ( 12 ) /* PWMC Status Register */ +#define PWMC_IER ( 16 ) /* PWMC Interrupt Enable Register */ +#define PWMC_IDR ( 20 ) /* PWMC Interrupt Disable Register */ +#define PWMC_IMR ( 24 ) /* PWMC Interrupt Mask Register */ +#define PWMC_ISR ( 28 ) /* PWMC Interrupt Status Register */ +#define PWMC_VR ( 252 ) /* PWMC Version Register */ +#define PWMC_CH ( 512 ) /* PWMC Channel */ +/* -------- PWMC_MR : (PWMC Offset: 0x0) PWMC Mode Register -------- */ +#define AT91C_PWMC_DIVA ( 0xFF << 0 ) /* (PWMC) CLKA divide factor. */ +#define AT91C_PWMC_PREA ( 0xF << 8 ) /* (PWMC) Divider Input Clock Prescaler A */ +#define AT91C_PWMC_PREA_MCK ( 0x0 << 8 ) /* (PWMC) */ +#define AT91C_PWMC_DIVB ( 0xFF << 16 ) /* (PWMC) CLKB divide factor. */ +#define AT91C_PWMC_PREB ( 0xF << 24 ) /* (PWMC) Divider Input Clock Prescaler B */ +#define AT91C_PWMC_PREB_MCK ( 0x0 << 24 ) /* (PWMC) */ +/* -------- PWMC_ENA : (PWMC Offset: 0x4) PWMC Enable Register -------- */ +#define AT91C_PWMC_CHID0 ( 0x1 << 0 ) /* (PWMC) Channel ID 0 */ +#define AT91C_PWMC_CHID1 ( 0x1 << 1 ) /* (PWMC) Channel ID 1 */ +#define AT91C_PWMC_CHID2 ( 0x1 << 2 ) /* (PWMC) Channel ID 2 */ +#define AT91C_PWMC_CHID3 ( 0x1 << 3 ) /* (PWMC) Channel ID 3 */ +/* -------- PWMC_DIS : (PWMC Offset: 0x8) PWMC Disable Register -------- */ +/* -------- PWMC_SR : (PWMC Offset: 0xc) PWMC Status Register -------- */ +/* -------- PWMC_IER : (PWMC Offset: 0x10) PWMC Interrupt Enable Register -------- */ +/* -------- PWMC_IDR : (PWMC Offset: 0x14) PWMC Interrupt Disable Register -------- */ +/* -------- PWMC_IMR : (PWMC Offset: 0x18) PWMC Interrupt Mask Register -------- */ +/* -------- PWMC_ISR : (PWMC Offset: 0x1c) PWMC Interrupt Status Register -------- */ -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR USB Device Interface -// ***************************************************************************** -// *** Register offset in AT91S_UDP structure *** -#define UDP_NUM ( 0) // Frame Number Register -#define UDP_GLBSTATE ( 4) // Global State Register -#define UDP_FADDR ( 8) // Function Address Register -#define UDP_IER (16) // Interrupt Enable Register -#define UDP_IDR (20) // Interrupt Disable Register -#define UDP_IMR (24) // Interrupt Mask Register -#define UDP_ISR (28) // Interrupt Status Register -#define UDP_ICR (32) // Interrupt Clear Register -#define UDP_RSTEP (40) // Reset Endpoint Register -#define UDP_CSR (48) // Endpoint Control and Status Register -#define UDP_FDR (80) // Endpoint FIFO Data Register -#define UDP_TXVC (116) // Transceiver Control Register -// -------- UDP_FRM_NUM : (UDP Offset: 0x0) USB Frame Number Register -------- -#define AT91C_UDP_FRM_NUM (0x7FF << 0) // (UDP) Frame Number as Defined in the Packet Field Formats -#define AT91C_UDP_FRM_ERR (0x1 << 16) // (UDP) Frame Error -#define AT91C_UDP_FRM_OK (0x1 << 17) // (UDP) Frame OK -// -------- UDP_GLB_STATE : (UDP Offset: 0x4) USB Global State Register -------- -#define AT91C_UDP_FADDEN (0x1 << 0) // (UDP) Function Address Enable -#define AT91C_UDP_CONFG (0x1 << 1) // (UDP) Configured -#define AT91C_UDP_ESR (0x1 << 2) // (UDP) Enable Send Resume -#define AT91C_UDP_RSMINPR (0x1 << 3) // (UDP) A Resume Has Been Sent to the Host -#define AT91C_UDP_RMWUPE (0x1 << 4) // (UDP) Remote Wake Up Enable -// -------- UDP_FADDR : (UDP Offset: 0x8) USB Function Address Register -------- -#define AT91C_UDP_FADD (0xFF << 0) // (UDP) Function Address Value -#define AT91C_UDP_FEN (0x1 << 8) // (UDP) Function Enable -// -------- UDP_IER : (UDP Offset: 0x10) USB Interrupt Enable Register -------- -#define AT91C_UDP_EPINT0 (0x1 << 0) // (UDP) Endpoint 0 Interrupt -#define AT91C_UDP_EPINT1 (0x1 << 1) // (UDP) Endpoint 0 Interrupt -#define AT91C_UDP_EPINT2 (0x1 << 2) // (UDP) Endpoint 2 Interrupt -#define AT91C_UDP_EPINT3 (0x1 << 3) // (UDP) Endpoint 3 Interrupt -#define AT91C_UDP_EPINT4 (0x1 << 4) // (UDP) Endpoint 4 Interrupt -#define AT91C_UDP_EPINT5 (0x1 << 5) // (UDP) Endpoint 5 Interrupt -#define AT91C_UDP_RXSUSP (0x1 << 8) // (UDP) USB Suspend Interrupt -#define AT91C_UDP_RXRSM (0x1 << 9) // (UDP) USB Resume Interrupt -#define AT91C_UDP_EXTRSM (0x1 << 10) // (UDP) USB External Resume Interrupt -#define AT91C_UDP_SOFINT (0x1 << 11) // (UDP) USB Start Of frame Interrupt -#define AT91C_UDP_WAKEUP (0x1 << 13) // (UDP) USB Resume Interrupt -// -------- UDP_IDR : (UDP Offset: 0x14) USB Interrupt Disable Register -------- -// -------- UDP_IMR : (UDP Offset: 0x18) USB Interrupt Mask Register -------- -// -------- UDP_ISR : (UDP Offset: 0x1c) USB Interrupt Status Register -------- -#define AT91C_UDP_ENDBUSRES (0x1 << 12) // (UDP) USB End Of Bus Reset Interrupt -// -------- UDP_ICR : (UDP Offset: 0x20) USB Interrupt Clear Register -------- -// -------- UDP_RST_EP : (UDP Offset: 0x28) USB Reset Endpoint Register -------- -#define AT91C_UDP_EP0 (0x1 << 0) // (UDP) Reset Endpoint 0 -#define AT91C_UDP_EP1 (0x1 << 1) // (UDP) Reset Endpoint 1 -#define AT91C_UDP_EP2 (0x1 << 2) // (UDP) Reset Endpoint 2 -#define AT91C_UDP_EP3 (0x1 << 3) // (UDP) Reset Endpoint 3 -#define AT91C_UDP_EP4 (0x1 << 4) // (UDP) Reset Endpoint 4 -#define AT91C_UDP_EP5 (0x1 << 5) // (UDP) Reset Endpoint 5 -// -------- UDP_CSR : (UDP Offset: 0x30) USB Endpoint Control and Status Register -------- -#define AT91C_UDP_TXCOMP (0x1 << 0) // (UDP) Generates an IN packet with data previously written in the DPR -#define AT91C_UDP_RX_DATA_BK0 (0x1 << 1) // (UDP) Receive Data Bank 0 -#define AT91C_UDP_RXSETUP (0x1 << 2) // (UDP) Sends STALL to the Host (Control endpoints) -#define AT91C_UDP_ISOERROR (0x1 << 3) // (UDP) Isochronous error (Isochronous endpoints) -#define AT91C_UDP_TXPKTRDY (0x1 << 4) // (UDP) Transmit Packet Ready -#define AT91C_UDP_FORCESTALL (0x1 << 5) // (UDP) Force Stall (used by Control, Bulk and Isochronous endpoints). -#define AT91C_UDP_RX_DATA_BK1 (0x1 << 6) // (UDP) Receive Data Bank 1 (only used by endpoints with ping-pong attributes). -#define AT91C_UDP_DIR (0x1 << 7) // (UDP) Transfer Direction -#define AT91C_UDP_EPTYPE (0x7 << 8) // (UDP) Endpoint type -#define AT91C_UDP_EPTYPE_CTRL (0x0 << 8) // (UDP) Control -#define AT91C_UDP_EPTYPE_ISO_OUT (0x1 << 8) // (UDP) Isochronous OUT -#define AT91C_UDP_EPTYPE_BULK_OUT (0x2 << 8) // (UDP) Bulk OUT -#define AT91C_UDP_EPTYPE_INT_OUT (0x3 << 8) // (UDP) Interrupt OUT -#define AT91C_UDP_EPTYPE_ISO_IN (0x5 << 8) // (UDP) Isochronous IN -#define AT91C_UDP_EPTYPE_BULK_IN (0x6 << 8) // (UDP) Bulk IN -#define AT91C_UDP_EPTYPE_INT_IN (0x7 << 8) // (UDP) Interrupt IN -#define AT91C_UDP_DTGLE (0x1 << 11) // (UDP) Data Toggle -#define AT91C_UDP_EPEDS (0x1 << 15) // (UDP) Endpoint Enable Disable -#define AT91C_UDP_RXBYTECNT (0x7FF << 16) // (UDP) Number Of Bytes Available in the FIFO -// -------- UDP_TXVC : (UDP Offset: 0x74) Transceiver Control Register -------- -#define AT91C_UDP_TXVDIS (0x1 << 8) // (UDP) -#define AT91C_UDP_PUON (0x1 << 9) // (UDP) Pull-up ON +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR USB Device Interface */ +/* ***************************************************************************** */ +/* *** Register offset in AT91S_UDP structure *** */ +#define UDP_NUM ( 0 ) /* Frame Number Register */ +#define UDP_GLBSTATE ( 4 ) /* Global State Register */ +#define UDP_FADDR ( 8 ) /* Function Address Register */ +#define UDP_IER ( 16 ) /* Interrupt Enable Register */ +#define UDP_IDR ( 20 ) /* Interrupt Disable Register */ +#define UDP_IMR ( 24 ) /* Interrupt Mask Register */ +#define UDP_ISR ( 28 ) /* Interrupt Status Register */ +#define UDP_ICR ( 32 ) /* Interrupt Clear Register */ +#define UDP_RSTEP ( 40 ) /* Reset Endpoint Register */ +#define UDP_CSR ( 48 ) /* Endpoint Control and Status Register */ +#define UDP_FDR ( 80 ) /* Endpoint FIFO Data Register */ +#define UDP_TXVC ( 116 ) /* Transceiver Control Register */ +/* -------- UDP_FRM_NUM : (UDP Offset: 0x0) USB Frame Number Register -------- */ +#define AT91C_UDP_FRM_NUM ( 0x7FF << 0 ) /* (UDP) Frame Number as Defined in the Packet Field Formats */ +#define AT91C_UDP_FRM_ERR ( 0x1 << 16 ) /* (UDP) Frame Error */ +#define AT91C_UDP_FRM_OK ( 0x1 << 17 ) /* (UDP) Frame OK */ +/* -------- UDP_GLB_STATE : (UDP Offset: 0x4) USB Global State Register -------- */ +#define AT91C_UDP_FADDEN ( 0x1 << 0 ) /* (UDP) Function Address Enable */ +#define AT91C_UDP_CONFG ( 0x1 << 1 ) /* (UDP) Configured */ +#define AT91C_UDP_ESR ( 0x1 << 2 ) /* (UDP) Enable Send Resume */ +#define AT91C_UDP_RSMINPR ( 0x1 << 3 ) /* (UDP) A Resume Has Been Sent to the Host */ +#define AT91C_UDP_RMWUPE ( 0x1 << 4 ) /* (UDP) Remote Wake Up Enable */ +/* -------- UDP_FADDR : (UDP Offset: 0x8) USB Function Address Register -------- */ +#define AT91C_UDP_FADD ( 0xFF << 0 ) /* (UDP) Function Address Value */ +#define AT91C_UDP_FEN ( 0x1 << 8 ) /* (UDP) Function Enable */ +/* -------- UDP_IER : (UDP Offset: 0x10) USB Interrupt Enable Register -------- */ +#define AT91C_UDP_EPINT0 ( 0x1 << 0 ) /* (UDP) Endpoint 0 Interrupt */ +#define AT91C_UDP_EPINT1 ( 0x1 << 1 ) /* (UDP) Endpoint 0 Interrupt */ +#define AT91C_UDP_EPINT2 ( 0x1 << 2 ) /* (UDP) Endpoint 2 Interrupt */ +#define AT91C_UDP_EPINT3 ( 0x1 << 3 ) /* (UDP) Endpoint 3 Interrupt */ +#define AT91C_UDP_EPINT4 ( 0x1 << 4 ) /* (UDP) Endpoint 4 Interrupt */ +#define AT91C_UDP_EPINT5 ( 0x1 << 5 ) /* (UDP) Endpoint 5 Interrupt */ +#define AT91C_UDP_RXSUSP ( 0x1 << 8 ) /* (UDP) USB Suspend Interrupt */ +#define AT91C_UDP_RXRSM ( 0x1 << 9 ) /* (UDP) USB Resume Interrupt */ +#define AT91C_UDP_EXTRSM ( 0x1 << 10 ) /* (UDP) USB External Resume Interrupt */ +#define AT91C_UDP_SOFINT ( 0x1 << 11 ) /* (UDP) USB Start Of frame Interrupt */ +#define AT91C_UDP_WAKEUP ( 0x1 << 13 ) /* (UDP) USB Resume Interrupt */ +/* -------- UDP_IDR : (UDP Offset: 0x14) USB Interrupt Disable Register -------- */ +/* -------- UDP_IMR : (UDP Offset: 0x18) USB Interrupt Mask Register -------- */ +/* -------- UDP_ISR : (UDP Offset: 0x1c) USB Interrupt Status Register -------- */ +#define AT91C_UDP_ENDBUSRES ( 0x1 << 12 ) /* (UDP) USB End Of Bus Reset Interrupt */ +/* -------- UDP_ICR : (UDP Offset: 0x20) USB Interrupt Clear Register -------- */ +/* -------- UDP_RST_EP : (UDP Offset: 0x28) USB Reset Endpoint Register -------- */ +#define AT91C_UDP_EP0 ( 0x1 << 0 ) /* (UDP) Reset Endpoint 0 */ +#define AT91C_UDP_EP1 ( 0x1 << 1 ) /* (UDP) Reset Endpoint 1 */ +#define AT91C_UDP_EP2 ( 0x1 << 2 ) /* (UDP) Reset Endpoint 2 */ +#define AT91C_UDP_EP3 ( 0x1 << 3 ) /* (UDP) Reset Endpoint 3 */ +#define AT91C_UDP_EP4 ( 0x1 << 4 ) /* (UDP) Reset Endpoint 4 */ +#define AT91C_UDP_EP5 ( 0x1 << 5 ) /* (UDP) Reset Endpoint 5 */ +/* -------- UDP_CSR : (UDP Offset: 0x30) USB Endpoint Control and Status Register -------- */ +#define AT91C_UDP_TXCOMP ( 0x1 << 0 ) /* (UDP) Generates an IN packet with data previously written in the DPR */ +#define AT91C_UDP_RX_DATA_BK0 ( 0x1 << 1 ) /* (UDP) Receive Data Bank 0 */ +#define AT91C_UDP_RXSETUP ( 0x1 << 2 ) /* (UDP) Sends STALL to the Host (Control endpoints) */ +#define AT91C_UDP_ISOERROR ( 0x1 << 3 ) /* (UDP) Isochronous error (Isochronous endpoints) */ +#define AT91C_UDP_TXPKTRDY ( 0x1 << 4 ) /* (UDP) Transmit Packet Ready */ +#define AT91C_UDP_FORCESTALL ( 0x1 << 5 ) /* (UDP) Force Stall (used by Control, Bulk and Isochronous endpoints). */ +#define AT91C_UDP_RX_DATA_BK1 ( 0x1 << 6 ) /* (UDP) Receive Data Bank 1 (only used by endpoints with ping-pong attributes). */ +#define AT91C_UDP_DIR ( 0x1 << 7 ) /* (UDP) Transfer Direction */ +#define AT91C_UDP_EPTYPE ( 0x7 << 8 ) /* (UDP) Endpoint type */ +#define AT91C_UDP_EPTYPE_CTRL ( 0x0 << 8 ) /* (UDP) Control */ +#define AT91C_UDP_EPTYPE_ISO_OUT ( 0x1 << 8 ) /* (UDP) Isochronous OUT */ +#define AT91C_UDP_EPTYPE_BULK_OUT ( 0x2 << 8 ) /* (UDP) Bulk OUT */ +#define AT91C_UDP_EPTYPE_INT_OUT ( 0x3 << 8 ) /* (UDP) Interrupt OUT */ +#define AT91C_UDP_EPTYPE_ISO_IN ( 0x5 << 8 ) /* (UDP) Isochronous IN */ +#define AT91C_UDP_EPTYPE_BULK_IN ( 0x6 << 8 ) /* (UDP) Bulk IN */ +#define AT91C_UDP_EPTYPE_INT_IN ( 0x7 << 8 ) /* (UDP) Interrupt IN */ +#define AT91C_UDP_DTGLE ( 0x1 << 11 ) /* (UDP) Data Toggle */ +#define AT91C_UDP_EPEDS ( 0x1 << 15 ) /* (UDP) Endpoint Enable Disable */ +#define AT91C_UDP_RXBYTECNT ( 0x7FF << 16 ) /* (UDP) Number Of Bytes Available in the FIFO */ +/* -------- UDP_TXVC : (UDP Offset: 0x74) Transceiver Control Register -------- */ +#define AT91C_UDP_TXVDIS ( 0x1 << 8 ) /* (UDP) */ +#define AT91C_UDP_PUON ( 0x1 << 9 ) /* (UDP) Pull-up ON */ -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Timer Counter Channel Interface -// ***************************************************************************** -// *** Register offset in AT91S_TC structure *** -#define TC_CCR ( 0) // Channel Control Register -#define TC_CMR ( 4) // Channel Mode Register (Capture Mode / Waveform Mode) -#define TC_CV (16) // Counter Value -#define TC_RA (20) // Register A -#define TC_RB (24) // Register B -#define TC_RC (28) // Register C -#define TC_SR (32) // Status Register -#define TC_IER (36) // Interrupt Enable Register -#define TC_IDR (40) // Interrupt Disable Register -#define TC_IMR (44) // Interrupt Mask Register -// -------- TC_CCR : (TC Offset: 0x0) TC Channel Control Register -------- -#define AT91C_TC_CLKEN (0x1 << 0) // (TC) Counter Clock Enable Command -#define AT91C_TC_CLKDIS (0x1 << 1) // (TC) Counter Clock Disable Command -#define AT91C_TC_SWTRG (0x1 << 2) // (TC) Software Trigger Command -// -------- TC_CMR : (TC Offset: 0x4) TC Channel Mode Register: Capture Mode / Waveform Mode -------- -#define AT91C_TC_CLKS (0x7 << 0) // (TC) Clock Selection -#define AT91C_TC_CLKS_TIMER_DIV1_CLOCK (0x0) // (TC) Clock selected: TIMER_DIV1_CLOCK -#define AT91C_TC_CLKS_TIMER_DIV2_CLOCK (0x1) // (TC) Clock selected: TIMER_DIV2_CLOCK -#define AT91C_TC_CLKS_TIMER_DIV3_CLOCK (0x2) // (TC) Clock selected: TIMER_DIV3_CLOCK -#define AT91C_TC_CLKS_TIMER_DIV4_CLOCK (0x3) // (TC) Clock selected: TIMER_DIV4_CLOCK -#define AT91C_TC_CLKS_TIMER_DIV5_CLOCK (0x4) // (TC) Clock selected: TIMER_DIV5_CLOCK -#define AT91C_TC_CLKS_XC0 (0x5) // (TC) Clock selected: XC0 -#define AT91C_TC_CLKS_XC1 (0x6) // (TC) Clock selected: XC1 -#define AT91C_TC_CLKS_XC2 (0x7) // (TC) Clock selected: XC2 -#define AT91C_TC_CLKI (0x1 << 3) // (TC) Clock Invert -#define AT91C_TC_BURST (0x3 << 4) // (TC) Burst Signal Selection -#define AT91C_TC_BURST_NONE (0x0 << 4) // (TC) The clock is not gated by an external signal -#define AT91C_TC_BURST_XC0 (0x1 << 4) // (TC) XC0 is ANDed with the selected clock -#define AT91C_TC_BURST_XC1 (0x2 << 4) // (TC) XC1 is ANDed with the selected clock -#define AT91C_TC_BURST_XC2 (0x3 << 4) // (TC) XC2 is ANDed with the selected clock -#define AT91C_TC_CPCSTOP (0x1 << 6) // (TC) Counter Clock Stopped with RC Compare -#define AT91C_TC_LDBSTOP (0x1 << 6) // (TC) Counter Clock Stopped with RB Loading -#define AT91C_TC_CPCDIS (0x1 << 7) // (TC) Counter Clock Disable with RC Compare -#define AT91C_TC_LDBDIS (0x1 << 7) // (TC) Counter Clock Disabled with RB Loading -#define AT91C_TC_ETRGEDG (0x3 << 8) // (TC) External Trigger Edge Selection -#define AT91C_TC_ETRGEDG_NONE (0x0 << 8) // (TC) Edge: None -#define AT91C_TC_ETRGEDG_RISING (0x1 << 8) // (TC) Edge: rising edge -#define AT91C_TC_ETRGEDG_FALLING (0x2 << 8) // (TC) Edge: falling edge -#define AT91C_TC_ETRGEDG_BOTH (0x3 << 8) // (TC) Edge: each edge -#define AT91C_TC_EEVTEDG (0x3 << 8) // (TC) External Event Edge Selection -#define AT91C_TC_EEVTEDG_NONE (0x0 << 8) // (TC) Edge: None -#define AT91C_TC_EEVTEDG_RISING (0x1 << 8) // (TC) Edge: rising edge -#define AT91C_TC_EEVTEDG_FALLING (0x2 << 8) // (TC) Edge: falling edge -#define AT91C_TC_EEVTEDG_BOTH (0x3 << 8) // (TC) Edge: each edge -#define AT91C_TC_EEVT (0x3 << 10) // (TC) External Event Selection -#define AT91C_TC_EEVT_TIOB (0x0 << 10) // (TC) Signal selected as external event: TIOB TIOB direction: input -#define AT91C_TC_EEVT_XC0 (0x1 << 10) // (TC) Signal selected as external event: XC0 TIOB direction: output -#define AT91C_TC_EEVT_XC1 (0x2 << 10) // (TC) Signal selected as external event: XC1 TIOB direction: output -#define AT91C_TC_EEVT_XC2 (0x3 << 10) // (TC) Signal selected as external event: XC2 TIOB direction: output -#define AT91C_TC_ABETRG (0x1 << 10) // (TC) TIOA or TIOB External Trigger Selection -#define AT91C_TC_ENETRG (0x1 << 12) // (TC) External Event Trigger enable -#define AT91C_TC_WAVESEL (0x3 << 13) // (TC) Waveform Selection -#define AT91C_TC_WAVESEL_UP (0x0 << 13) // (TC) UP mode without atomatic trigger on RC Compare -#define AT91C_TC_WAVESEL_UPDOWN (0x1 << 13) // (TC) UPDOWN mode without automatic trigger on RC Compare -#define AT91C_TC_WAVESEL_UP_AUTO (0x2 << 13) // (TC) UP mode with automatic trigger on RC Compare -#define AT91C_TC_WAVESEL_UPDOWN_AUTO (0x3 << 13) // (TC) UPDOWN mode with automatic trigger on RC Compare -#define AT91C_TC_CPCTRG (0x1 << 14) // (TC) RC Compare Trigger Enable -#define AT91C_TC_WAVE (0x1 << 15) // (TC) -#define AT91C_TC_ACPA (0x3 << 16) // (TC) RA Compare Effect on TIOA -#define AT91C_TC_ACPA_NONE (0x0 << 16) // (TC) Effect: none -#define AT91C_TC_ACPA_SET (0x1 << 16) // (TC) Effect: set -#define AT91C_TC_ACPA_CLEAR (0x2 << 16) // (TC) Effect: clear -#define AT91C_TC_ACPA_TOGGLE (0x3 << 16) // (TC) Effect: toggle -#define AT91C_TC_LDRA (0x3 << 16) // (TC) RA Loading Selection -#define AT91C_TC_LDRA_NONE (0x0 << 16) // (TC) Edge: None -#define AT91C_TC_LDRA_RISING (0x1 << 16) // (TC) Edge: rising edge of TIOA -#define AT91C_TC_LDRA_FALLING (0x2 << 16) // (TC) Edge: falling edge of TIOA -#define AT91C_TC_LDRA_BOTH (0x3 << 16) // (TC) Edge: each edge of TIOA -#define AT91C_TC_ACPC (0x3 << 18) // (TC) RC Compare Effect on TIOA -#define AT91C_TC_ACPC_NONE (0x0 << 18) // (TC) Effect: none -#define AT91C_TC_ACPC_SET (0x1 << 18) // (TC) Effect: set -#define AT91C_TC_ACPC_CLEAR (0x2 << 18) // (TC) Effect: clear -#define AT91C_TC_ACPC_TOGGLE (0x3 << 18) // (TC) Effect: toggle -#define AT91C_TC_LDRB (0x3 << 18) // (TC) RB Loading Selection -#define AT91C_TC_LDRB_NONE (0x0 << 18) // (TC) Edge: None -#define AT91C_TC_LDRB_RISING (0x1 << 18) // (TC) Edge: rising edge of TIOA -#define AT91C_TC_LDRB_FALLING (0x2 << 18) // (TC) Edge: falling edge of TIOA -#define AT91C_TC_LDRB_BOTH (0x3 << 18) // (TC) Edge: each edge of TIOA -#define AT91C_TC_AEEVT (0x3 << 20) // (TC) External Event Effect on TIOA -#define AT91C_TC_AEEVT_NONE (0x0 << 20) // (TC) Effect: none -#define AT91C_TC_AEEVT_SET (0x1 << 20) // (TC) Effect: set -#define AT91C_TC_AEEVT_CLEAR (0x2 << 20) // (TC) Effect: clear -#define AT91C_TC_AEEVT_TOGGLE (0x3 << 20) // (TC) Effect: toggle -#define AT91C_TC_ASWTRG (0x3 << 22) // (TC) Software Trigger Effect on TIOA -#define AT91C_TC_ASWTRG_NONE (0x0 << 22) // (TC) Effect: none -#define AT91C_TC_ASWTRG_SET (0x1 << 22) // (TC) Effect: set -#define AT91C_TC_ASWTRG_CLEAR (0x2 << 22) // (TC) Effect: clear -#define AT91C_TC_ASWTRG_TOGGLE (0x3 << 22) // (TC) Effect: toggle -#define AT91C_TC_BCPB (0x3 << 24) // (TC) RB Compare Effect on TIOB -#define AT91C_TC_BCPB_NONE (0x0 << 24) // (TC) Effect: none -#define AT91C_TC_BCPB_SET (0x1 << 24) // (TC) Effect: set -#define AT91C_TC_BCPB_CLEAR (0x2 << 24) // (TC) Effect: clear -#define AT91C_TC_BCPB_TOGGLE (0x3 << 24) // (TC) Effect: toggle -#define AT91C_TC_BCPC (0x3 << 26) // (TC) RC Compare Effect on TIOB -#define AT91C_TC_BCPC_NONE (0x0 << 26) // (TC) Effect: none -#define AT91C_TC_BCPC_SET (0x1 << 26) // (TC) Effect: set -#define AT91C_TC_BCPC_CLEAR (0x2 << 26) // (TC) Effect: clear -#define AT91C_TC_BCPC_TOGGLE (0x3 << 26) // (TC) Effect: toggle -#define AT91C_TC_BEEVT (0x3 << 28) // (TC) External Event Effect on TIOB -#define AT91C_TC_BEEVT_NONE (0x0 << 28) // (TC) Effect: none -#define AT91C_TC_BEEVT_SET (0x1 << 28) // (TC) Effect: set -#define AT91C_TC_BEEVT_CLEAR (0x2 << 28) // (TC) Effect: clear -#define AT91C_TC_BEEVT_TOGGLE (0x3 << 28) // (TC) Effect: toggle -#define AT91C_TC_BSWTRG (0x3 << 30) // (TC) Software Trigger Effect on TIOB -#define AT91C_TC_BSWTRG_NONE (0x0 << 30) // (TC) Effect: none -#define AT91C_TC_BSWTRG_SET (0x1 << 30) // (TC) Effect: set -#define AT91C_TC_BSWTRG_CLEAR (0x2 << 30) // (TC) Effect: clear -#define AT91C_TC_BSWTRG_TOGGLE (0x3 << 30) // (TC) Effect: toggle -// -------- TC_SR : (TC Offset: 0x20) TC Channel Status Register -------- -#define AT91C_TC_COVFS (0x1 << 0) // (TC) Counter Overflow -#define AT91C_TC_LOVRS (0x1 << 1) // (TC) Load Overrun -#define AT91C_TC_CPAS (0x1 << 2) // (TC) RA Compare -#define AT91C_TC_CPBS (0x1 << 3) // (TC) RB Compare -#define AT91C_TC_CPCS (0x1 << 4) // (TC) RC Compare -#define AT91C_TC_LDRAS (0x1 << 5) // (TC) RA Loading -#define AT91C_TC_LDRBS (0x1 << 6) // (TC) RB Loading -#define AT91C_TC_ETRGS (0x1 << 7) // (TC) External Trigger -#define AT91C_TC_CLKSTA (0x1 << 16) // (TC) Clock Enabling -#define AT91C_TC_MTIOA (0x1 << 17) // (TC) TIOA Mirror -#define AT91C_TC_MTIOB (0x1 << 18) // (TC) TIOA Mirror -// -------- TC_IER : (TC Offset: 0x24) TC Channel Interrupt Enable Register -------- -// -------- TC_IDR : (TC Offset: 0x28) TC Channel Interrupt Disable Register -------- -// -------- TC_IMR : (TC Offset: 0x2c) TC Channel Interrupt Mask Register -------- +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR Timer Counter Channel Interface */ +/* ***************************************************************************** */ +/* *** Register offset in AT91S_TC structure *** */ +#define TC_CCR ( 0 ) /* Channel Control Register */ +#define TC_CMR ( 4 ) /* Channel Mode Register (Capture Mode / Waveform Mode) */ +#define TC_CV ( 16 ) /* Counter Value */ +#define TC_RA ( 20 ) /* Register A */ +#define TC_RB ( 24 ) /* Register B */ +#define TC_RC ( 28 ) /* Register C */ +#define TC_SR ( 32 ) /* Status Register */ +#define TC_IER ( 36 ) /* Interrupt Enable Register */ +#define TC_IDR ( 40 ) /* Interrupt Disable Register */ +#define TC_IMR ( 44 ) /* Interrupt Mask Register */ +/* -------- TC_CCR : (TC Offset: 0x0) TC Channel Control Register -------- */ +#define AT91C_TC_CLKEN ( 0x1 << 0 ) /* (TC) Counter Clock Enable Command */ +#define AT91C_TC_CLKDIS ( 0x1 << 1 ) /* (TC) Counter Clock Disable Command */ +#define AT91C_TC_SWTRG ( 0x1 << 2 ) /* (TC) Software Trigger Command */ +/* -------- TC_CMR : (TC Offset: 0x4) TC Channel Mode Register: Capture Mode / Waveform Mode -------- */ +#define AT91C_TC_CLKS ( 0x7 << 0 ) /* (TC) Clock Selection */ +#define AT91C_TC_CLKS_TIMER_DIV1_CLOCK ( 0x0 ) /* (TC) Clock selected: TIMER_DIV1_CLOCK */ +#define AT91C_TC_CLKS_TIMER_DIV2_CLOCK ( 0x1 ) /* (TC) Clock selected: TIMER_DIV2_CLOCK */ +#define AT91C_TC_CLKS_TIMER_DIV3_CLOCK ( 0x2 ) /* (TC) Clock selected: TIMER_DIV3_CLOCK */ +#define AT91C_TC_CLKS_TIMER_DIV4_CLOCK ( 0x3 ) /* (TC) Clock selected: TIMER_DIV4_CLOCK */ +#define AT91C_TC_CLKS_TIMER_DIV5_CLOCK ( 0x4 ) /* (TC) Clock selected: TIMER_DIV5_CLOCK */ +#define AT91C_TC_CLKS_XC0 ( 0x5 ) /* (TC) Clock selected: XC0 */ +#define AT91C_TC_CLKS_XC1 ( 0x6 ) /* (TC) Clock selected: XC1 */ +#define AT91C_TC_CLKS_XC2 ( 0x7 ) /* (TC) Clock selected: XC2 */ +#define AT91C_TC_CLKI ( 0x1 << 3 ) /* (TC) Clock Invert */ +#define AT91C_TC_BURST ( 0x3 << 4 ) /* (TC) Burst Signal Selection */ +#define AT91C_TC_BURST_NONE ( 0x0 << 4 ) /* (TC) The clock is not gated by an external signal */ +#define AT91C_TC_BURST_XC0 ( 0x1 << 4 ) /* (TC) XC0 is ANDed with the selected clock */ +#define AT91C_TC_BURST_XC1 ( 0x2 << 4 ) /* (TC) XC1 is ANDed with the selected clock */ +#define AT91C_TC_BURST_XC2 ( 0x3 << 4 ) /* (TC) XC2 is ANDed with the selected clock */ +#define AT91C_TC_CPCSTOP ( 0x1 << 6 ) /* (TC) Counter Clock Stopped with RC Compare */ +#define AT91C_TC_LDBSTOP ( 0x1 << 6 ) /* (TC) Counter Clock Stopped with RB Loading */ +#define AT91C_TC_CPCDIS ( 0x1 << 7 ) /* (TC) Counter Clock Disable with RC Compare */ +#define AT91C_TC_LDBDIS ( 0x1 << 7 ) /* (TC) Counter Clock Disabled with RB Loading */ +#define AT91C_TC_ETRGEDG ( 0x3 << 8 ) /* (TC) External Trigger Edge Selection */ +#define AT91C_TC_ETRGEDG_NONE ( 0x0 << 8 ) /* (TC) Edge: None */ +#define AT91C_TC_ETRGEDG_RISING ( 0x1 << 8 ) /* (TC) Edge: rising edge */ +#define AT91C_TC_ETRGEDG_FALLING ( 0x2 << 8 ) /* (TC) Edge: falling edge */ +#define AT91C_TC_ETRGEDG_BOTH ( 0x3 << 8 ) /* (TC) Edge: each edge */ +#define AT91C_TC_EEVTEDG ( 0x3 << 8 ) /* (TC) External Event Edge Selection */ +#define AT91C_TC_EEVTEDG_NONE ( 0x0 << 8 ) /* (TC) Edge: None */ +#define AT91C_TC_EEVTEDG_RISING ( 0x1 << 8 ) /* (TC) Edge: rising edge */ +#define AT91C_TC_EEVTEDG_FALLING ( 0x2 << 8 ) /* (TC) Edge: falling edge */ +#define AT91C_TC_EEVTEDG_BOTH ( 0x3 << 8 ) /* (TC) Edge: each edge */ +#define AT91C_TC_EEVT ( 0x3 << 10 ) /* (TC) External Event Selection */ +#define AT91C_TC_EEVT_TIOB ( 0x0 << 10 ) /* (TC) Signal selected as external event: TIOB TIOB direction: input */ +#define AT91C_TC_EEVT_XC0 ( 0x1 << 10 ) /* (TC) Signal selected as external event: XC0 TIOB direction: output */ +#define AT91C_TC_EEVT_XC1 ( 0x2 << 10 ) /* (TC) Signal selected as external event: XC1 TIOB direction: output */ +#define AT91C_TC_EEVT_XC2 ( 0x3 << 10 ) /* (TC) Signal selected as external event: XC2 TIOB direction: output */ +#define AT91C_TC_ABETRG ( 0x1 << 10 ) /* (TC) TIOA or TIOB External Trigger Selection */ +#define AT91C_TC_ENETRG ( 0x1 << 12 ) /* (TC) External Event Trigger enable */ +#define AT91C_TC_WAVESEL ( 0x3 << 13 ) /* (TC) Waveform Selection */ +#define AT91C_TC_WAVESEL_UP ( 0x0 << 13 ) /* (TC) UP mode without atomatic trigger on RC Compare */ +#define AT91C_TC_WAVESEL_UPDOWN ( 0x1 << 13 ) /* (TC) UPDOWN mode without automatic trigger on RC Compare */ +#define AT91C_TC_WAVESEL_UP_AUTO ( 0x2 << 13 ) /* (TC) UP mode with automatic trigger on RC Compare */ +#define AT91C_TC_WAVESEL_UPDOWN_AUTO ( 0x3 << 13 ) /* (TC) UPDOWN mode with automatic trigger on RC Compare */ +#define AT91C_TC_CPCTRG ( 0x1 << 14 ) /* (TC) RC Compare Trigger Enable */ +#define AT91C_TC_WAVE ( 0x1 << 15 ) /* (TC) */ +#define AT91C_TC_ACPA ( 0x3 << 16 ) /* (TC) RA Compare Effect on TIOA */ +#define AT91C_TC_ACPA_NONE ( 0x0 << 16 ) /* (TC) Effect: none */ +#define AT91C_TC_ACPA_SET ( 0x1 << 16 ) /* (TC) Effect: set */ +#define AT91C_TC_ACPA_CLEAR ( 0x2 << 16 ) /* (TC) Effect: clear */ +#define AT91C_TC_ACPA_TOGGLE ( 0x3 << 16 ) /* (TC) Effect: toggle */ +#define AT91C_TC_LDRA ( 0x3 << 16 ) /* (TC) RA Loading Selection */ +#define AT91C_TC_LDRA_NONE ( 0x0 << 16 ) /* (TC) Edge: None */ +#define AT91C_TC_LDRA_RISING ( 0x1 << 16 ) /* (TC) Edge: rising edge of TIOA */ +#define AT91C_TC_LDRA_FALLING ( 0x2 << 16 ) /* (TC) Edge: falling edge of TIOA */ +#define AT91C_TC_LDRA_BOTH ( 0x3 << 16 ) /* (TC) Edge: each edge of TIOA */ +#define AT91C_TC_ACPC ( 0x3 << 18 ) /* (TC) RC Compare Effect on TIOA */ +#define AT91C_TC_ACPC_NONE ( 0x0 << 18 ) /* (TC) Effect: none */ +#define AT91C_TC_ACPC_SET ( 0x1 << 18 ) /* (TC) Effect: set */ +#define AT91C_TC_ACPC_CLEAR ( 0x2 << 18 ) /* (TC) Effect: clear */ +#define AT91C_TC_ACPC_TOGGLE ( 0x3 << 18 ) /* (TC) Effect: toggle */ +#define AT91C_TC_LDRB ( 0x3 << 18 ) /* (TC) RB Loading Selection */ +#define AT91C_TC_LDRB_NONE ( 0x0 << 18 ) /* (TC) Edge: None */ +#define AT91C_TC_LDRB_RISING ( 0x1 << 18 ) /* (TC) Edge: rising edge of TIOA */ +#define AT91C_TC_LDRB_FALLING ( 0x2 << 18 ) /* (TC) Edge: falling edge of TIOA */ +#define AT91C_TC_LDRB_BOTH ( 0x3 << 18 ) /* (TC) Edge: each edge of TIOA */ +#define AT91C_TC_AEEVT ( 0x3 << 20 ) /* (TC) External Event Effect on TIOA */ +#define AT91C_TC_AEEVT_NONE ( 0x0 << 20 ) /* (TC) Effect: none */ +#define AT91C_TC_AEEVT_SET ( 0x1 << 20 ) /* (TC) Effect: set */ +#define AT91C_TC_AEEVT_CLEAR ( 0x2 << 20 ) /* (TC) Effect: clear */ +#define AT91C_TC_AEEVT_TOGGLE ( 0x3 << 20 ) /* (TC) Effect: toggle */ +#define AT91C_TC_ASWTRG ( 0x3 << 22 ) /* (TC) Software Trigger Effect on TIOA */ +#define AT91C_TC_ASWTRG_NONE ( 0x0 << 22 ) /* (TC) Effect: none */ +#define AT91C_TC_ASWTRG_SET ( 0x1 << 22 ) /* (TC) Effect: set */ +#define AT91C_TC_ASWTRG_CLEAR ( 0x2 << 22 ) /* (TC) Effect: clear */ +#define AT91C_TC_ASWTRG_TOGGLE ( 0x3 << 22 ) /* (TC) Effect: toggle */ +#define AT91C_TC_BCPB ( 0x3 << 24 ) /* (TC) RB Compare Effect on TIOB */ +#define AT91C_TC_BCPB_NONE ( 0x0 << 24 ) /* (TC) Effect: none */ +#define AT91C_TC_BCPB_SET ( 0x1 << 24 ) /* (TC) Effect: set */ +#define AT91C_TC_BCPB_CLEAR ( 0x2 << 24 ) /* (TC) Effect: clear */ +#define AT91C_TC_BCPB_TOGGLE ( 0x3 << 24 ) /* (TC) Effect: toggle */ +#define AT91C_TC_BCPC ( 0x3 << 26 ) /* (TC) RC Compare Effect on TIOB */ +#define AT91C_TC_BCPC_NONE ( 0x0 << 26 ) /* (TC) Effect: none */ +#define AT91C_TC_BCPC_SET ( 0x1 << 26 ) /* (TC) Effect: set */ +#define AT91C_TC_BCPC_CLEAR ( 0x2 << 26 ) /* (TC) Effect: clear */ +#define AT91C_TC_BCPC_TOGGLE ( 0x3 << 26 ) /* (TC) Effect: toggle */ +#define AT91C_TC_BEEVT ( 0x3 << 28 ) /* (TC) External Event Effect on TIOB */ +#define AT91C_TC_BEEVT_NONE ( 0x0 << 28 ) /* (TC) Effect: none */ +#define AT91C_TC_BEEVT_SET ( 0x1 << 28 ) /* (TC) Effect: set */ +#define AT91C_TC_BEEVT_CLEAR ( 0x2 << 28 ) /* (TC) Effect: clear */ +#define AT91C_TC_BEEVT_TOGGLE ( 0x3 << 28 ) /* (TC) Effect: toggle */ +#define AT91C_TC_BSWTRG ( 0x3 << 30 ) /* (TC) Software Trigger Effect on TIOB */ +#define AT91C_TC_BSWTRG_NONE ( 0x0 << 30 ) /* (TC) Effect: none */ +#define AT91C_TC_BSWTRG_SET ( 0x1 << 30 ) /* (TC) Effect: set */ +#define AT91C_TC_BSWTRG_CLEAR ( 0x2 << 30 ) /* (TC) Effect: clear */ +#define AT91C_TC_BSWTRG_TOGGLE ( 0x3 << 30 ) /* (TC) Effect: toggle */ +/* -------- TC_SR : (TC Offset: 0x20) TC Channel Status Register -------- */ +#define AT91C_TC_COVFS ( 0x1 << 0 ) /* (TC) Counter Overflow */ +#define AT91C_TC_LOVRS ( 0x1 << 1 ) /* (TC) Load Overrun */ +#define AT91C_TC_CPAS ( 0x1 << 2 ) /* (TC) RA Compare */ +#define AT91C_TC_CPBS ( 0x1 << 3 ) /* (TC) RB Compare */ +#define AT91C_TC_CPCS ( 0x1 << 4 ) /* (TC) RC Compare */ +#define AT91C_TC_LDRAS ( 0x1 << 5 ) /* (TC) RA Loading */ +#define AT91C_TC_LDRBS ( 0x1 << 6 ) /* (TC) RB Loading */ +#define AT91C_TC_ETRGS ( 0x1 << 7 ) /* (TC) External Trigger */ +#define AT91C_TC_CLKSTA ( 0x1 << 16 ) /* (TC) Clock Enabling */ +#define AT91C_TC_MTIOA ( 0x1 << 17 ) /* (TC) TIOA Mirror */ +#define AT91C_TC_MTIOB ( 0x1 << 18 ) /* (TC) TIOA Mirror */ +/* -------- TC_IER : (TC Offset: 0x24) TC Channel Interrupt Enable Register -------- */ +/* -------- TC_IDR : (TC Offset: 0x28) TC Channel Interrupt Disable Register -------- */ +/* -------- TC_IMR : (TC Offset: 0x2c) TC Channel Interrupt Mask Register -------- */ -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Timer Counter Interface -// ***************************************************************************** -// *** Register offset in AT91S_TCB structure *** -#define TCB_TC0 ( 0) // TC Channel 0 -#define TCB_TC1 (64) // TC Channel 1 -#define TCB_TC2 (128) // TC Channel 2 -#define TCB_BCR (192) // TC Block Control Register -#define TCB_BMR (196) // TC Block Mode Register -// -------- TCB_BCR : (TCB Offset: 0xc0) TC Block Control Register -------- -#define AT91C_TCB_SYNC (0x1 << 0) // (TCB) Synchro Command -// -------- TCB_BMR : (TCB Offset: 0xc4) TC Block Mode Register -------- -#define AT91C_TCB_TC0XC0S (0x3 << 0) // (TCB) External Clock Signal 0 Selection -#define AT91C_TCB_TC0XC0S_TCLK0 (0x0) // (TCB) TCLK0 connected to XC0 -#define AT91C_TCB_TC0XC0S_NONE (0x1) // (TCB) None signal connected to XC0 -#define AT91C_TCB_TC0XC0S_TIOA1 (0x2) // (TCB) TIOA1 connected to XC0 -#define AT91C_TCB_TC0XC0S_TIOA2 (0x3) // (TCB) TIOA2 connected to XC0 -#define AT91C_TCB_TC1XC1S (0x3 << 2) // (TCB) External Clock Signal 1 Selection -#define AT91C_TCB_TC1XC1S_TCLK1 (0x0 << 2) // (TCB) TCLK1 connected to XC1 -#define AT91C_TCB_TC1XC1S_NONE (0x1 << 2) // (TCB) None signal connected to XC1 -#define AT91C_TCB_TC1XC1S_TIOA0 (0x2 << 2) // (TCB) TIOA0 connected to XC1 -#define AT91C_TCB_TC1XC1S_TIOA2 (0x3 << 2) // (TCB) TIOA2 connected to XC1 -#define AT91C_TCB_TC2XC2S (0x3 << 4) // (TCB) External Clock Signal 2 Selection -#define AT91C_TCB_TC2XC2S_TCLK2 (0x0 << 4) // (TCB) TCLK2 connected to XC2 -#define AT91C_TCB_TC2XC2S_NONE (0x1 << 4) // (TCB) None signal connected to XC2 -#define AT91C_TCB_TC2XC2S_TIOA0 (0x2 << 4) // (TCB) TIOA0 connected to XC2 -#define AT91C_TCB_TC2XC2S_TIOA1 (0x3 << 4) // (TCB) TIOA2 connected to XC2 +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR Timer Counter Interface */ +/* ***************************************************************************** */ +/* *** Register offset in AT91S_TCB structure *** */ +#define TCB_TC0 ( 0 ) /* TC Channel 0 */ +#define TCB_TC1 ( 64 ) /* TC Channel 1 */ +#define TCB_TC2 ( 128 ) /* TC Channel 2 */ +#define TCB_BCR ( 192 ) /* TC Block Control Register */ +#define TCB_BMR ( 196 ) /* TC Block Mode Register */ +/* -------- TCB_BCR : (TCB Offset: 0xc0) TC Block Control Register -------- */ +#define AT91C_TCB_SYNC ( 0x1 << 0 ) /* (TCB) Synchro Command */ +/* -------- TCB_BMR : (TCB Offset: 0xc4) TC Block Mode Register -------- */ +#define AT91C_TCB_TC0XC0S ( 0x3 << 0 ) /* (TCB) External Clock Signal 0 Selection */ +#define AT91C_TCB_TC0XC0S_TCLK0 ( 0x0 ) /* (TCB) TCLK0 connected to XC0 */ +#define AT91C_TCB_TC0XC0S_NONE ( 0x1 ) /* (TCB) None signal connected to XC0 */ +#define AT91C_TCB_TC0XC0S_TIOA1 ( 0x2 ) /* (TCB) TIOA1 connected to XC0 */ +#define AT91C_TCB_TC0XC0S_TIOA2 ( 0x3 ) /* (TCB) TIOA2 connected to XC0 */ +#define AT91C_TCB_TC1XC1S ( 0x3 << 2 ) /* (TCB) External Clock Signal 1 Selection */ +#define AT91C_TCB_TC1XC1S_TCLK1 ( 0x0 << 2 ) /* (TCB) TCLK1 connected to XC1 */ +#define AT91C_TCB_TC1XC1S_NONE ( 0x1 << 2 ) /* (TCB) None signal connected to XC1 */ +#define AT91C_TCB_TC1XC1S_TIOA0 ( 0x2 << 2 ) /* (TCB) TIOA0 connected to XC1 */ +#define AT91C_TCB_TC1XC1S_TIOA2 ( 0x3 << 2 ) /* (TCB) TIOA2 connected to XC1 */ +#define AT91C_TCB_TC2XC2S ( 0x3 << 4 ) /* (TCB) External Clock Signal 2 Selection */ +#define AT91C_TCB_TC2XC2S_TCLK2 ( 0x0 << 4 ) /* (TCB) TCLK2 connected to XC2 */ +#define AT91C_TCB_TC2XC2S_NONE ( 0x1 << 4 ) /* (TCB) None signal connected to XC2 */ +#define AT91C_TCB_TC2XC2S_TIOA0 ( 0x2 << 4 ) /* (TCB) TIOA0 connected to XC2 */ +#define AT91C_TCB_TC2XC2S_TIOA1 ( 0x3 << 4 ) /* (TCB) TIOA2 connected to XC2 */ -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Control Area Network MailBox Interface -// ***************************************************************************** -// *** Register offset in AT91S_CAN_MB structure *** -#define CAN_MB_MMR ( 0) // MailBox Mode Register -#define CAN_MB_MAM ( 4) // MailBox Acceptance Mask Register -#define CAN_MB_MID ( 8) // MailBox ID Register -#define CAN_MB_MFID (12) // MailBox Family ID Register -#define CAN_MB_MSR (16) // MailBox Status Register -#define CAN_MB_MDL (20) // MailBox Data Low Register -#define CAN_MB_MDH (24) // MailBox Data High Register -#define CAN_MB_MCR (28) // MailBox Control Register -// -------- CAN_MMR : (CAN_MB Offset: 0x0) CAN Message Mode Register -------- -#define AT91C_CAN_MTIMEMARK (0xFFFF << 0) // (CAN_MB) Mailbox Timemark -#define AT91C_CAN_PRIOR (0xF << 16) // (CAN_MB) Mailbox Priority -#define AT91C_CAN_MOT (0x7 << 24) // (CAN_MB) Mailbox Object Type -#define AT91C_CAN_MOT_DIS (0x0 << 24) // (CAN_MB) -#define AT91C_CAN_MOT_RX (0x1 << 24) // (CAN_MB) -#define AT91C_CAN_MOT_RXOVERWRITE (0x2 << 24) // (CAN_MB) -#define AT91C_CAN_MOT_TX (0x3 << 24) // (CAN_MB) -#define AT91C_CAN_MOT_CONSUMER (0x4 << 24) // (CAN_MB) -#define AT91C_CAN_MOT_PRODUCER (0x5 << 24) // (CAN_MB) -// -------- CAN_MAM : (CAN_MB Offset: 0x4) CAN Message Acceptance Mask Register -------- -#define AT91C_CAN_MIDvB (0x3FFFF << 0) // (CAN_MB) Complementary bits for identifier in extended mode -#define AT91C_CAN_MIDvA (0x7FF << 18) // (CAN_MB) Identifier for standard frame mode -#define AT91C_CAN_MIDE (0x1 << 29) // (CAN_MB) Identifier Version -// -------- CAN_MID : (CAN_MB Offset: 0x8) CAN Message ID Register -------- -// -------- CAN_MFID : (CAN_MB Offset: 0xc) CAN Message Family ID Register -------- -// -------- CAN_MSR : (CAN_MB Offset: 0x10) CAN Message Status Register -------- -#define AT91C_CAN_MTIMESTAMP (0xFFFF << 0) // (CAN_MB) Timer Value -#define AT91C_CAN_MDLC (0xF << 16) // (CAN_MB) Mailbox Data Length Code -#define AT91C_CAN_MRTR (0x1 << 20) // (CAN_MB) Mailbox Remote Transmission Request -#define AT91C_CAN_MABT (0x1 << 22) // (CAN_MB) Mailbox Message Abort -#define AT91C_CAN_MRDY (0x1 << 23) // (CAN_MB) Mailbox Ready -#define AT91C_CAN_MMI (0x1 << 24) // (CAN_MB) Mailbox Message Ignored -// -------- CAN_MDL : (CAN_MB Offset: 0x14) CAN Message Data Low Register -------- -// -------- CAN_MDH : (CAN_MB Offset: 0x18) CAN Message Data High Register -------- -// -------- CAN_MCR : (CAN_MB Offset: 0x1c) CAN Message Control Register -------- -#define AT91C_CAN_MACR (0x1 << 22) // (CAN_MB) Abort Request for Mailbox -#define AT91C_CAN_MTCR (0x1 << 23) // (CAN_MB) Mailbox Transfer Command +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR Control Area Network MailBox Interface */ +/* ***************************************************************************** */ +/* *** Register offset in AT91S_CAN_MB structure *** */ +#define CAN_MB_MMR ( 0 ) /* MailBox Mode Register */ +#define CAN_MB_MAM ( 4 ) /* MailBox Acceptance Mask Register */ +#define CAN_MB_MID ( 8 ) /* MailBox ID Register */ +#define CAN_MB_MFID ( 12 ) /* MailBox Family ID Register */ +#define CAN_MB_MSR ( 16 ) /* MailBox Status Register */ +#define CAN_MB_MDL ( 20 ) /* MailBox Data Low Register */ +#define CAN_MB_MDH ( 24 ) /* MailBox Data High Register */ +#define CAN_MB_MCR ( 28 ) /* MailBox Control Register */ +/* -------- CAN_MMR : (CAN_MB Offset: 0x0) CAN Message Mode Register -------- */ +#define AT91C_CAN_MTIMEMARK ( 0xFFFF << 0 ) /* (CAN_MB) Mailbox Timemark */ +#define AT91C_CAN_PRIOR ( 0xF << 16 ) /* (CAN_MB) Mailbox Priority */ +#define AT91C_CAN_MOT ( 0x7 << 24 ) /* (CAN_MB) Mailbox Object Type */ +#define AT91C_CAN_MOT_DIS ( 0x0 << 24 ) /* (CAN_MB) */ +#define AT91C_CAN_MOT_RX ( 0x1 << 24 ) /* (CAN_MB) */ +#define AT91C_CAN_MOT_RXOVERWRITE ( 0x2 << 24 ) /* (CAN_MB) */ +#define AT91C_CAN_MOT_TX ( 0x3 << 24 ) /* (CAN_MB) */ +#define AT91C_CAN_MOT_CONSUMER ( 0x4 << 24 ) /* (CAN_MB) */ +#define AT91C_CAN_MOT_PRODUCER ( 0x5 << 24 ) /* (CAN_MB) */ +/* -------- CAN_MAM : (CAN_MB Offset: 0x4) CAN Message Acceptance Mask Register -------- */ +#define AT91C_CAN_MIDvB ( 0x3FFFF << 0 ) /* (CAN_MB) Complementary bits for identifier in extended mode */ +#define AT91C_CAN_MIDvA ( 0x7FF << 18 ) /* (CAN_MB) Identifier for standard frame mode */ +#define AT91C_CAN_MIDE ( 0x1 << 29 ) /* (CAN_MB) Identifier Version */ +/* -------- CAN_MID : (CAN_MB Offset: 0x8) CAN Message ID Register -------- */ +/* -------- CAN_MFID : (CAN_MB Offset: 0xc) CAN Message Family ID Register -------- */ +/* -------- CAN_MSR : (CAN_MB Offset: 0x10) CAN Message Status Register -------- */ +#define AT91C_CAN_MTIMESTAMP ( 0xFFFF << 0 ) /* (CAN_MB) Timer Value */ +#define AT91C_CAN_MDLC ( 0xF << 16 ) /* (CAN_MB) Mailbox Data Length Code */ +#define AT91C_CAN_MRTR ( 0x1 << 20 ) /* (CAN_MB) Mailbox Remote Transmission Request */ +#define AT91C_CAN_MABT ( 0x1 << 22 ) /* (CAN_MB) Mailbox Message Abort */ +#define AT91C_CAN_MRDY ( 0x1 << 23 ) /* (CAN_MB) Mailbox Ready */ +#define AT91C_CAN_MMI ( 0x1 << 24 ) /* (CAN_MB) Mailbox Message Ignored */ +/* -------- CAN_MDL : (CAN_MB Offset: 0x14) CAN Message Data Low Register -------- */ +/* -------- CAN_MDH : (CAN_MB Offset: 0x18) CAN Message Data High Register -------- */ +/* -------- CAN_MCR : (CAN_MB Offset: 0x1c) CAN Message Control Register -------- */ +#define AT91C_CAN_MACR ( 0x1 << 22 ) /* (CAN_MB) Abort Request for Mailbox */ +#define AT91C_CAN_MTCR ( 0x1 << 23 ) /* (CAN_MB) Mailbox Transfer Command */ -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Control Area Network Interface -// ***************************************************************************** -// *** Register offset in AT91S_CAN structure *** -#define CAN_MR ( 0) // Mode Register -#define CAN_IER ( 4) // Interrupt Enable Register -#define CAN_IDR ( 8) // Interrupt Disable Register -#define CAN_IMR (12) // Interrupt Mask Register -#define CAN_SR (16) // Status Register -#define CAN_BR (20) // Baudrate Register -#define CAN_TIM (24) // Timer Register -#define CAN_TIMESTP (28) // Time Stamp Register -#define CAN_ECR (32) // Error Counter Register -#define CAN_TCR (36) // Transfer Command Register -#define CAN_ACR (40) // Abort Command Register -#define CAN_VR (252) // Version Register -#define CAN_MB0 (512) // CAN Mailbox 0 -#define CAN_MB1 (544) // CAN Mailbox 1 -#define CAN_MB2 (576) // CAN Mailbox 2 -#define CAN_MB3 (608) // CAN Mailbox 3 -#define CAN_MB4 (640) // CAN Mailbox 4 -#define CAN_MB5 (672) // CAN Mailbox 5 -#define CAN_MB6 (704) // CAN Mailbox 6 -#define CAN_MB7 (736) // CAN Mailbox 7 -#define CAN_MB8 (768) // CAN Mailbox 8 -#define CAN_MB9 (800) // CAN Mailbox 9 -#define CAN_MB10 (832) // CAN Mailbox 10 -#define CAN_MB11 (864) // CAN Mailbox 11 -#define CAN_MB12 (896) // CAN Mailbox 12 -#define CAN_MB13 (928) // CAN Mailbox 13 -#define CAN_MB14 (960) // CAN Mailbox 14 -#define CAN_MB15 (992) // CAN Mailbox 15 -// -------- CAN_MR : (CAN Offset: 0x0) CAN Mode Register -------- -#define AT91C_CAN_CANEN (0x1 << 0) // (CAN) CAN Controller Enable -#define AT91C_CAN_LPM (0x1 << 1) // (CAN) Disable/Enable Low Power Mode -#define AT91C_CAN_ABM (0x1 << 2) // (CAN) Disable/Enable Autobaud/Listen Mode -#define AT91C_CAN_OVL (0x1 << 3) // (CAN) Disable/Enable Overload Frame -#define AT91C_CAN_TEOF (0x1 << 4) // (CAN) Time Stamp messages at each end of Frame -#define AT91C_CAN_TTM (0x1 << 5) // (CAN) Disable/Enable Time Trigger Mode -#define AT91C_CAN_TIMFRZ (0x1 << 6) // (CAN) Enable Timer Freeze -#define AT91C_CAN_DRPT (0x1 << 7) // (CAN) Disable Repeat -// -------- CAN_IER : (CAN Offset: 0x4) CAN Interrupt Enable Register -------- -#define AT91C_CAN_MB0 (0x1 << 0) // (CAN) Mailbox 0 Flag -#define AT91C_CAN_MB1 (0x1 << 1) // (CAN) Mailbox 1 Flag -#define AT91C_CAN_MB2 (0x1 << 2) // (CAN) Mailbox 2 Flag -#define AT91C_CAN_MB3 (0x1 << 3) // (CAN) Mailbox 3 Flag -#define AT91C_CAN_MB4 (0x1 << 4) // (CAN) Mailbox 4 Flag -#define AT91C_CAN_MB5 (0x1 << 5) // (CAN) Mailbox 5 Flag -#define AT91C_CAN_MB6 (0x1 << 6) // (CAN) Mailbox 6 Flag -#define AT91C_CAN_MB7 (0x1 << 7) // (CAN) Mailbox 7 Flag -#define AT91C_CAN_MB8 (0x1 << 8) // (CAN) Mailbox 8 Flag -#define AT91C_CAN_MB9 (0x1 << 9) // (CAN) Mailbox 9 Flag -#define AT91C_CAN_MB10 (0x1 << 10) // (CAN) Mailbox 10 Flag -#define AT91C_CAN_MB11 (0x1 << 11) // (CAN) Mailbox 11 Flag -#define AT91C_CAN_MB12 (0x1 << 12) // (CAN) Mailbox 12 Flag -#define AT91C_CAN_MB13 (0x1 << 13) // (CAN) Mailbox 13 Flag -#define AT91C_CAN_MB14 (0x1 << 14) // (CAN) Mailbox 14 Flag -#define AT91C_CAN_MB15 (0x1 << 15) // (CAN) Mailbox 15 Flag -#define AT91C_CAN_ERRA (0x1 << 16) // (CAN) Error Active Mode Flag -#define AT91C_CAN_WARN (0x1 << 17) // (CAN) Warning Limit Flag -#define AT91C_CAN_ERRP (0x1 << 18) // (CAN) Error Passive Mode Flag -#define AT91C_CAN_BOFF (0x1 << 19) // (CAN) Bus Off Mode Flag -#define AT91C_CAN_SLEEP (0x1 << 20) // (CAN) Sleep Flag -#define AT91C_CAN_WAKEUP (0x1 << 21) // (CAN) Wakeup Flag -#define AT91C_CAN_TOVF (0x1 << 22) // (CAN) Timer Overflow Flag -#define AT91C_CAN_TSTP (0x1 << 23) // (CAN) Timestamp Flag -#define AT91C_CAN_CERR (0x1 << 24) // (CAN) CRC Error -#define AT91C_CAN_SERR (0x1 << 25) // (CAN) Stuffing Error -#define AT91C_CAN_AERR (0x1 << 26) // (CAN) Acknowledgment Error -#define AT91C_CAN_FERR (0x1 << 27) // (CAN) Form Error -#define AT91C_CAN_BERR (0x1 << 28) // (CAN) Bit Error -// -------- CAN_IDR : (CAN Offset: 0x8) CAN Interrupt Disable Register -------- -// -------- CAN_IMR : (CAN Offset: 0xc) CAN Interrupt Mask Register -------- -// -------- CAN_SR : (CAN Offset: 0x10) CAN Status Register -------- -#define AT91C_CAN_RBSY (0x1 << 29) // (CAN) Receiver Busy -#define AT91C_CAN_TBSY (0x1 << 30) // (CAN) Transmitter Busy -#define AT91C_CAN_OVLY (0x1 << 31) // (CAN) Overload Busy -// -------- CAN_BR : (CAN Offset: 0x14) CAN Baudrate Register -------- -#define AT91C_CAN_PHASE2 (0x7 << 0) // (CAN) Phase 2 segment -#define AT91C_CAN_PHASE1 (0x7 << 4) // (CAN) Phase 1 segment -#define AT91C_CAN_PROPAG (0x7 << 8) // (CAN) Programmation time segment -#define AT91C_CAN_SYNC (0x3 << 12) // (CAN) Re-synchronization jump width segment -#define AT91C_CAN_BRP (0x7F << 16) // (CAN) Baudrate Prescaler -#define AT91C_CAN_SMP (0x1 << 24) // (CAN) Sampling mode -// -------- CAN_TIM : (CAN Offset: 0x18) CAN Timer Register -------- -#define AT91C_CAN_TIMER (0xFFFF << 0) // (CAN) Timer field -// -------- CAN_TIMESTP : (CAN Offset: 0x1c) CAN Timestamp Register -------- -// -------- CAN_ECR : (CAN Offset: 0x20) CAN Error Counter Register -------- -#define AT91C_CAN_REC (0xFF << 0) // (CAN) Receive Error Counter -#define AT91C_CAN_TEC (0xFF << 16) // (CAN) Transmit Error Counter -// -------- CAN_TCR : (CAN Offset: 0x24) CAN Transfer Command Register -------- -#define AT91C_CAN_TIMRST (0x1 << 31) // (CAN) Timer Reset Field -// -------- CAN_ACR : (CAN Offset: 0x28) CAN Abort Command Register -------- +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR Control Area Network Interface */ +/* ***************************************************************************** */ +/* *** Register offset in AT91S_CAN structure *** */ +#define CAN_MR ( 0 ) /* Mode Register */ +#define CAN_IER ( 4 ) /* Interrupt Enable Register */ +#define CAN_IDR ( 8 ) /* Interrupt Disable Register */ +#define CAN_IMR ( 12 ) /* Interrupt Mask Register */ +#define CAN_SR ( 16 ) /* Status Register */ +#define CAN_BR ( 20 ) /* Baudrate Register */ +#define CAN_TIM ( 24 ) /* Timer Register */ +#define CAN_TIMESTP ( 28 ) /* Time Stamp Register */ +#define CAN_ECR ( 32 ) /* Error Counter Register */ +#define CAN_TCR ( 36 ) /* Transfer Command Register */ +#define CAN_ACR ( 40 ) /* Abort Command Register */ +#define CAN_VR ( 252 ) /* Version Register */ +#define CAN_MB0 ( 512 ) /* CAN Mailbox 0 */ +#define CAN_MB1 ( 544 ) /* CAN Mailbox 1 */ +#define CAN_MB2 ( 576 ) /* CAN Mailbox 2 */ +#define CAN_MB3 ( 608 ) /* CAN Mailbox 3 */ +#define CAN_MB4 ( 640 ) /* CAN Mailbox 4 */ +#define CAN_MB5 ( 672 ) /* CAN Mailbox 5 */ +#define CAN_MB6 ( 704 ) /* CAN Mailbox 6 */ +#define CAN_MB7 ( 736 ) /* CAN Mailbox 7 */ +#define CAN_MB8 ( 768 ) /* CAN Mailbox 8 */ +#define CAN_MB9 ( 800 ) /* CAN Mailbox 9 */ +#define CAN_MB10 ( 832 ) /* CAN Mailbox 10 */ +#define CAN_MB11 ( 864 ) /* CAN Mailbox 11 */ +#define CAN_MB12 ( 896 ) /* CAN Mailbox 12 */ +#define CAN_MB13 ( 928 ) /* CAN Mailbox 13 */ +#define CAN_MB14 ( 960 ) /* CAN Mailbox 14 */ +#define CAN_MB15 ( 992 ) /* CAN Mailbox 15 */ +/* -------- CAN_MR : (CAN Offset: 0x0) CAN Mode Register -------- */ +#define AT91C_CAN_CANEN ( 0x1 << 0 ) /* (CAN) CAN Controller Enable */ +#define AT91C_CAN_LPM ( 0x1 << 1 ) /* (CAN) Disable/Enable Low Power Mode */ +#define AT91C_CAN_ABM ( 0x1 << 2 ) /* (CAN) Disable/Enable Autobaud/Listen Mode */ +#define AT91C_CAN_OVL ( 0x1 << 3 ) /* (CAN) Disable/Enable Overload Frame */ +#define AT91C_CAN_TEOF ( 0x1 << 4 ) /* (CAN) Time Stamp messages at each end of Frame */ +#define AT91C_CAN_TTM ( 0x1 << 5 ) /* (CAN) Disable/Enable Time Trigger Mode */ +#define AT91C_CAN_TIMFRZ ( 0x1 << 6 ) /* (CAN) Enable Timer Freeze */ +#define AT91C_CAN_DRPT ( 0x1 << 7 ) /* (CAN) Disable Repeat */ +/* -------- CAN_IER : (CAN Offset: 0x4) CAN Interrupt Enable Register -------- */ +#define AT91C_CAN_MB0 ( 0x1 << 0 ) /* (CAN) Mailbox 0 Flag */ +#define AT91C_CAN_MB1 ( 0x1 << 1 ) /* (CAN) Mailbox 1 Flag */ +#define AT91C_CAN_MB2 ( 0x1 << 2 ) /* (CAN) Mailbox 2 Flag */ +#define AT91C_CAN_MB3 ( 0x1 << 3 ) /* (CAN) Mailbox 3 Flag */ +#define AT91C_CAN_MB4 ( 0x1 << 4 ) /* (CAN) Mailbox 4 Flag */ +#define AT91C_CAN_MB5 ( 0x1 << 5 ) /* (CAN) Mailbox 5 Flag */ +#define AT91C_CAN_MB6 ( 0x1 << 6 ) /* (CAN) Mailbox 6 Flag */ +#define AT91C_CAN_MB7 ( 0x1 << 7 ) /* (CAN) Mailbox 7 Flag */ +#define AT91C_CAN_MB8 ( 0x1 << 8 ) /* (CAN) Mailbox 8 Flag */ +#define AT91C_CAN_MB9 ( 0x1 << 9 ) /* (CAN) Mailbox 9 Flag */ +#define AT91C_CAN_MB10 ( 0x1 << 10 ) /* (CAN) Mailbox 10 Flag */ +#define AT91C_CAN_MB11 ( 0x1 << 11 ) /* (CAN) Mailbox 11 Flag */ +#define AT91C_CAN_MB12 ( 0x1 << 12 ) /* (CAN) Mailbox 12 Flag */ +#define AT91C_CAN_MB13 ( 0x1 << 13 ) /* (CAN) Mailbox 13 Flag */ +#define AT91C_CAN_MB14 ( 0x1 << 14 ) /* (CAN) Mailbox 14 Flag */ +#define AT91C_CAN_MB15 ( 0x1 << 15 ) /* (CAN) Mailbox 15 Flag */ +#define AT91C_CAN_ERRA ( 0x1 << 16 ) /* (CAN) Error Active Mode Flag */ +#define AT91C_CAN_WARN ( 0x1 << 17 ) /* (CAN) Warning Limit Flag */ +#define AT91C_CAN_ERRP ( 0x1 << 18 ) /* (CAN) Error Passive Mode Flag */ +#define AT91C_CAN_BOFF ( 0x1 << 19 ) /* (CAN) Bus Off Mode Flag */ +#define AT91C_CAN_SLEEP ( 0x1 << 20 ) /* (CAN) Sleep Flag */ +#define AT91C_CAN_WAKEUP ( 0x1 << 21 ) /* (CAN) Wakeup Flag */ +#define AT91C_CAN_TOVF ( 0x1 << 22 ) /* (CAN) Timer Overflow Flag */ +#define AT91C_CAN_TSTP ( 0x1 << 23 ) /* (CAN) Timestamp Flag */ +#define AT91C_CAN_CERR ( 0x1 << 24 ) /* (CAN) CRC Error */ +#define AT91C_CAN_SERR ( 0x1 << 25 ) /* (CAN) Stuffing Error */ +#define AT91C_CAN_AERR ( 0x1 << 26 ) /* (CAN) Acknowledgment Error */ +#define AT91C_CAN_FERR ( 0x1 << 27 ) /* (CAN) Form Error */ +#define AT91C_CAN_BERR ( 0x1 << 28 ) /* (CAN) Bit Error */ +/* -------- CAN_IDR : (CAN Offset: 0x8) CAN Interrupt Disable Register -------- */ +/* -------- CAN_IMR : (CAN Offset: 0xc) CAN Interrupt Mask Register -------- */ +/* -------- CAN_SR : (CAN Offset: 0x10) CAN Status Register -------- */ +#define AT91C_CAN_RBSY ( 0x1 << 29 ) /* (CAN) Receiver Busy */ +#define AT91C_CAN_TBSY ( 0x1 << 30 ) /* (CAN) Transmitter Busy */ +#define AT91C_CAN_OVLY ( 0x1 << 31 ) /* (CAN) Overload Busy */ +/* -------- CAN_BR : (CAN Offset: 0x14) CAN Baudrate Register -------- */ +#define AT91C_CAN_PHASE2 ( 0x7 << 0 ) /* (CAN) Phase 2 segment */ +#define AT91C_CAN_PHASE1 ( 0x7 << 4 ) /* (CAN) Phase 1 segment */ +#define AT91C_CAN_PROPAG ( 0x7 << 8 ) /* (CAN) Programmation time segment */ +#define AT91C_CAN_SYNC ( 0x3 << 12 ) /* (CAN) Re-synchronization jump width segment */ +#define AT91C_CAN_BRP ( 0x7F << 16 ) /* (CAN) Baudrate Prescaler */ +#define AT91C_CAN_SMP ( 0x1 << 24 ) /* (CAN) Sampling mode */ +/* -------- CAN_TIM : (CAN Offset: 0x18) CAN Timer Register -------- */ +#define AT91C_CAN_TIMER ( 0xFFFF << 0 ) /* (CAN) Timer field */ +/* -------- CAN_TIMESTP : (CAN Offset: 0x1c) CAN Timestamp Register -------- */ +/* -------- CAN_ECR : (CAN Offset: 0x20) CAN Error Counter Register -------- */ +#define AT91C_CAN_REC ( 0xFF << 0 ) /* (CAN) Receive Error Counter */ +#define AT91C_CAN_TEC ( 0xFF << 16 ) /* (CAN) Transmit Error Counter */ +/* -------- CAN_TCR : (CAN Offset: 0x24) CAN Transfer Command Register -------- */ +#define AT91C_CAN_TIMRST ( 0x1 << 31 ) /* (CAN) Timer Reset Field */ +/* -------- CAN_ACR : (CAN Offset: 0x28) CAN Abort Command Register -------- */ -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Ethernet MAC 10/100 -// ***************************************************************************** -// *** Register offset in AT91S_EMAC structure *** -#define EMAC_NCR ( 0) // Network Control Register -#define EMAC_NCFGR ( 4) // Network Configuration Register -#define EMAC_NSR ( 8) // Network Status Register -#define EMAC_TSR (20) // Transmit Status Register -#define EMAC_RBQP (24) // Receive Buffer Queue Pointer -#define EMAC_TBQP (28) // Transmit Buffer Queue Pointer -#define EMAC_RSR (32) // Receive Status Register -#define EMAC_ISR (36) // Interrupt Status Register -#define EMAC_IER (40) // Interrupt Enable Register -#define EMAC_IDR (44) // Interrupt Disable Register -#define EMAC_IMR (48) // Interrupt Mask Register -#define EMAC_MAN (52) // PHY Maintenance Register -#define EMAC_PTR (56) // Pause Time Register -#define EMAC_PFR (60) // Pause Frames received Register -#define EMAC_FTO (64) // Frames Transmitted OK Register -#define EMAC_SCF (68) // Single Collision Frame Register -#define EMAC_MCF (72) // Multiple Collision Frame Register -#define EMAC_FRO (76) // Frames Received OK Register -#define EMAC_FCSE (80) // Frame Check Sequence Error Register -#define EMAC_ALE (84) // Alignment Error Register -#define EMAC_DTF (88) // Deferred Transmission Frame Register -#define EMAC_LCOL (92) // Late Collision Register -#define EMAC_ECOL (96) // Excessive Collision Register -#define EMAC_TUND (100) // Transmit Underrun Error Register -#define EMAC_CSE (104) // Carrier Sense Error Register -#define EMAC_RRE (108) // Receive Ressource Error Register -#define EMAC_ROV (112) // Receive Overrun Errors Register -#define EMAC_RSE (116) // Receive Symbol Errors Register -#define EMAC_ELE (120) // Excessive Length Errors Register -#define EMAC_RJA (124) // Receive Jabbers Register -#define EMAC_USF (128) // Undersize Frames Register -#define EMAC_STE (132) // SQE Test Error Register -#define EMAC_RLE (136) // Receive Length Field Mismatch Register -#define EMAC_TPF (140) // Transmitted Pause Frames Register -#define EMAC_HRB (144) // Hash Address Bottom[31:0] -#define EMAC_HRT (148) // Hash Address Top[63:32] -#define EMAC_SA1L (152) // Specific Address 1 Bottom, First 4 bytes -#define EMAC_SA1H (156) // Specific Address 1 Top, Last 2 bytes -#define EMAC_SA2L (160) // Specific Address 2 Bottom, First 4 bytes -#define EMAC_SA2H (164) // Specific Address 2 Top, Last 2 bytes -#define EMAC_SA3L (168) // Specific Address 3 Bottom, First 4 bytes -#define EMAC_SA3H (172) // Specific Address 3 Top, Last 2 bytes -#define EMAC_SA4L (176) // Specific Address 4 Bottom, First 4 bytes -#define EMAC_SA4H (180) // Specific Address 4 Top, Last 2 bytes -#define EMAC_TID (184) // Type ID Checking Register -#define EMAC_TPQ (188) // Transmit Pause Quantum Register -#define EMAC_USRIO (192) // USER Input/Output Register -#define EMAC_WOL (196) // Wake On LAN Register -#define EMAC_REV (252) // Revision Register -// -------- EMAC_NCR : (EMAC Offset: 0x0) -------- -#define AT91C_EMAC_LB (0x1 << 0) // (EMAC) Loopback. Optional. When set, loopback signal is at high level. -#define AT91C_EMAC_LLB (0x1 << 1) // (EMAC) Loopback local. -#define AT91C_EMAC_RE (0x1 << 2) // (EMAC) Receive enable. -#define AT91C_EMAC_TE (0x1 << 3) // (EMAC) Transmit enable. -#define AT91C_EMAC_MPE (0x1 << 4) // (EMAC) Management port enable. -#define AT91C_EMAC_CLRSTAT (0x1 << 5) // (EMAC) Clear statistics registers. -#define AT91C_EMAC_INCSTAT (0x1 << 6) // (EMAC) Increment statistics registers. -#define AT91C_EMAC_WESTAT (0x1 << 7) // (EMAC) Write enable for statistics registers. -#define AT91C_EMAC_BP (0x1 << 8) // (EMAC) Back pressure. -#define AT91C_EMAC_TSTART (0x1 << 9) // (EMAC) Start Transmission. -#define AT91C_EMAC_THALT (0x1 << 10) // (EMAC) Transmission Halt. -#define AT91C_EMAC_TPFR (0x1 << 11) // (EMAC) Transmit pause frame -#define AT91C_EMAC_TZQ (0x1 << 12) // (EMAC) Transmit zero quantum pause frame -// -------- EMAC_NCFGR : (EMAC Offset: 0x4) Network Configuration Register -------- -#define AT91C_EMAC_SPD (0x1 << 0) // (EMAC) Speed. -#define AT91C_EMAC_FD (0x1 << 1) // (EMAC) Full duplex. -#define AT91C_EMAC_JFRAME (0x1 << 3) // (EMAC) Jumbo Frames. -#define AT91C_EMAC_CAF (0x1 << 4) // (EMAC) Copy all frames. -#define AT91C_EMAC_NBC (0x1 << 5) // (EMAC) No broadcast. -#define AT91C_EMAC_MTI (0x1 << 6) // (EMAC) Multicast hash event enable -#define AT91C_EMAC_UNI (0x1 << 7) // (EMAC) Unicast hash enable. -#define AT91C_EMAC_BIG (0x1 << 8) // (EMAC) Receive 1522 bytes. -#define AT91C_EMAC_EAE (0x1 << 9) // (EMAC) External address match enable. -#define AT91C_EMAC_CLK (0x3 << 10) // (EMAC) -#define AT91C_EMAC_CLK_HCLK_8 (0x0 << 10) // (EMAC) HCLK divided by 8 -#define AT91C_EMAC_CLK_HCLK_16 (0x1 << 10) // (EMAC) HCLK divided by 16 -#define AT91C_EMAC_CLK_HCLK_32 (0x2 << 10) // (EMAC) HCLK divided by 32 -#define AT91C_EMAC_CLK_HCLK_64 (0x3 << 10) // (EMAC) HCLK divided by 64 -#define AT91C_EMAC_RTY (0x1 << 12) // (EMAC) -#define AT91C_EMAC_PAE (0x1 << 13) // (EMAC) -#define AT91C_EMAC_RBOF (0x3 << 14) // (EMAC) -#define AT91C_EMAC_RBOF_OFFSET_0 (0x0 << 14) // (EMAC) no offset from start of receive buffer -#define AT91C_EMAC_RBOF_OFFSET_1 (0x1 << 14) // (EMAC) one byte offset from start of receive buffer -#define AT91C_EMAC_RBOF_OFFSET_2 (0x2 << 14) // (EMAC) two bytes offset from start of receive buffer -#define AT91C_EMAC_RBOF_OFFSET_3 (0x3 << 14) // (EMAC) three bytes offset from start of receive buffer -#define AT91C_EMAC_RLCE (0x1 << 16) // (EMAC) Receive Length field Checking Enable -#define AT91C_EMAC_DRFCS (0x1 << 17) // (EMAC) Discard Receive FCS -#define AT91C_EMAC_EFRHD (0x1 << 18) // (EMAC) -#define AT91C_EMAC_IRXFCS (0x1 << 19) // (EMAC) Ignore RX FCS -// -------- EMAC_NSR : (EMAC Offset: 0x8) Network Status Register -------- -#define AT91C_EMAC_LINKR (0x1 << 0) // (EMAC) -#define AT91C_EMAC_MDIO (0x1 << 1) // (EMAC) -#define AT91C_EMAC_IDLE (0x1 << 2) // (EMAC) -// -------- EMAC_TSR : (EMAC Offset: 0x14) Transmit Status Register -------- -#define AT91C_EMAC_UBR (0x1 << 0) // (EMAC) -#define AT91C_EMAC_COL (0x1 << 1) // (EMAC) -#define AT91C_EMAC_RLES (0x1 << 2) // (EMAC) -#define AT91C_EMAC_TGO (0x1 << 3) // (EMAC) Transmit Go -#define AT91C_EMAC_BEX (0x1 << 4) // (EMAC) Buffers exhausted mid frame -#define AT91C_EMAC_COMP (0x1 << 5) // (EMAC) -#define AT91C_EMAC_UND (0x1 << 6) // (EMAC) -// -------- EMAC_RSR : (EMAC Offset: 0x20) Receive Status Register -------- -#define AT91C_EMAC_BNA (0x1 << 0) // (EMAC) -#define AT91C_EMAC_REC (0x1 << 1) // (EMAC) -#define AT91C_EMAC_OVR (0x1 << 2) // (EMAC) -// -------- EMAC_ISR : (EMAC Offset: 0x24) Interrupt Status Register -------- -#define AT91C_EMAC_MFD (0x1 << 0) // (EMAC) -#define AT91C_EMAC_RCOMP (0x1 << 1) // (EMAC) -#define AT91C_EMAC_RXUBR (0x1 << 2) // (EMAC) -#define AT91C_EMAC_TXUBR (0x1 << 3) // (EMAC) -#define AT91C_EMAC_TUNDR (0x1 << 4) // (EMAC) -#define AT91C_EMAC_RLEX (0x1 << 5) // (EMAC) -#define AT91C_EMAC_TXERR (0x1 << 6) // (EMAC) -#define AT91C_EMAC_TCOMP (0x1 << 7) // (EMAC) -#define AT91C_EMAC_LINK (0x1 << 9) // (EMAC) -#define AT91C_EMAC_ROVR (0x1 << 10) // (EMAC) -#define AT91C_EMAC_HRESP (0x1 << 11) // (EMAC) -#define AT91C_EMAC_PFRE (0x1 << 12) // (EMAC) -#define AT91C_EMAC_PTZ (0x1 << 13) // (EMAC) -// -------- EMAC_IER : (EMAC Offset: 0x28) Interrupt Enable Register -------- -// -------- EMAC_IDR : (EMAC Offset: 0x2c) Interrupt Disable Register -------- -// -------- EMAC_IMR : (EMAC Offset: 0x30) Interrupt Mask Register -------- -// -------- EMAC_MAN : (EMAC Offset: 0x34) PHY Maintenance Register -------- -#define AT91C_EMAC_DATA (0xFFFF << 0) // (EMAC) -#define AT91C_EMAC_CODE (0x3 << 16) // (EMAC) -#define AT91C_EMAC_REGA (0x1F << 18) // (EMAC) -#define AT91C_EMAC_PHYA (0x1F << 23) // (EMAC) -#define AT91C_EMAC_RW (0x3 << 28) // (EMAC) -#define AT91C_EMAC_SOF (0x3 << 30) // (EMAC) -// -------- EMAC_USRIO : (EMAC Offset: 0xc0) USER Input Output Register -------- -#define AT91C_EMAC_RMII (0x1 << 0) // (EMAC) Reduce MII -// -------- EMAC_WOL : (EMAC Offset: 0xc4) Wake On LAN Register -------- -#define AT91C_EMAC_IP (0xFFFF << 0) // (EMAC) ARP request IP address -#define AT91C_EMAC_MAG (0x1 << 16) // (EMAC) Magic packet event enable -#define AT91C_EMAC_ARP (0x1 << 17) // (EMAC) ARP request event enable -#define AT91C_EMAC_SA1 (0x1 << 18) // (EMAC) Specific address register 1 event enable -// -------- EMAC_REV : (EMAC Offset: 0xfc) Revision Register -------- -#define AT91C_EMAC_REVREF (0xFFFF << 0) // (EMAC) -#define AT91C_EMAC_PARTREF (0xFFFF << 16) // (EMAC) +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR Ethernet MAC 10/100 */ +/* ***************************************************************************** */ +/* *** Register offset in AT91S_EMAC structure *** */ +#define EMAC_NCR ( 0 ) /* Network Control Register */ +#define EMAC_NCFGR ( 4 ) /* Network Configuration Register */ +#define EMAC_NSR ( 8 ) /* Network Status Register */ +#define EMAC_TSR ( 20 ) /* Transmit Status Register */ +#define EMAC_RBQP ( 24 ) /* Receive Buffer Queue Pointer */ +#define EMAC_TBQP ( 28 ) /* Transmit Buffer Queue Pointer */ +#define EMAC_RSR ( 32 ) /* Receive Status Register */ +#define EMAC_ISR ( 36 ) /* Interrupt Status Register */ +#define EMAC_IER ( 40 ) /* Interrupt Enable Register */ +#define EMAC_IDR ( 44 ) /* Interrupt Disable Register */ +#define EMAC_IMR ( 48 ) /* Interrupt Mask Register */ +#define EMAC_MAN ( 52 ) /* PHY Maintenance Register */ +#define EMAC_PTR ( 56 ) /* Pause Time Register */ +#define EMAC_PFR ( 60 ) /* Pause Frames received Register */ +#define EMAC_FTO ( 64 ) /* Frames Transmitted OK Register */ +#define EMAC_SCF ( 68 ) /* Single Collision Frame Register */ +#define EMAC_MCF ( 72 ) /* Multiple Collision Frame Register */ +#define EMAC_FRO ( 76 ) /* Frames Received OK Register */ +#define EMAC_FCSE ( 80 ) /* Frame Check Sequence Error Register */ +#define EMAC_ALE ( 84 ) /* Alignment Error Register */ +#define EMAC_DTF ( 88 ) /* Deferred Transmission Frame Register */ +#define EMAC_LCOL ( 92 ) /* Late Collision Register */ +#define EMAC_ECOL ( 96 ) /* Excessive Collision Register */ +#define EMAC_TUND ( 100 ) /* Transmit Underrun Error Register */ +#define EMAC_CSE ( 104 ) /* Carrier Sense Error Register */ +#define EMAC_RRE ( 108 ) /* Receive Ressource Error Register */ +#define EMAC_ROV ( 112 ) /* Receive Overrun Errors Register */ +#define EMAC_RSE ( 116 ) /* Receive Symbol Errors Register */ +#define EMAC_ELE ( 120 ) /* Excessive Length Errors Register */ +#define EMAC_RJA ( 124 ) /* Receive Jabbers Register */ +#define EMAC_USF ( 128 ) /* Undersize Frames Register */ +#define EMAC_STE ( 132 ) /* SQE Test Error Register */ +#define EMAC_RLE ( 136 ) /* Receive Length Field Mismatch Register */ +#define EMAC_TPF ( 140 ) /* Transmitted Pause Frames Register */ +#define EMAC_HRB ( 144 ) /* Hash Address Bottom[31:0] */ +#define EMAC_HRT ( 148 ) /* Hash Address Top[63:32] */ +#define EMAC_SA1L ( 152 ) /* Specific Address 1 Bottom, First 4 bytes */ +#define EMAC_SA1H ( 156 ) /* Specific Address 1 Top, Last 2 bytes */ +#define EMAC_SA2L ( 160 ) /* Specific Address 2 Bottom, First 4 bytes */ +#define EMAC_SA2H ( 164 ) /* Specific Address 2 Top, Last 2 bytes */ +#define EMAC_SA3L ( 168 ) /* Specific Address 3 Bottom, First 4 bytes */ +#define EMAC_SA3H ( 172 ) /* Specific Address 3 Top, Last 2 bytes */ +#define EMAC_SA4L ( 176 ) /* Specific Address 4 Bottom, First 4 bytes */ +#define EMAC_SA4H ( 180 ) /* Specific Address 4 Top, Last 2 bytes */ +#define EMAC_TID ( 184 ) /* Type ID Checking Register */ +#define EMAC_TPQ ( 188 ) /* Transmit Pause Quantum Register */ +#define EMAC_USRIO ( 192 ) /* USER Input/Output Register */ +#define EMAC_WOL ( 196 ) /* Wake On LAN Register */ +#define EMAC_REV ( 252 ) /* Revision Register */ +/* -------- EMAC_NCR : (EMAC Offset: 0x0) -------- */ +#define AT91C_EMAC_LB ( 0x1 << 0 ) /* (EMAC) Loopback. Optional. When set, loopback signal is at high level. */ +#define AT91C_EMAC_LLB ( 0x1 << 1 ) /* (EMAC) Loopback local. */ +#define AT91C_EMAC_RE ( 0x1 << 2 ) /* (EMAC) Receive enable. */ +#define AT91C_EMAC_TE ( 0x1 << 3 ) /* (EMAC) Transmit enable. */ +#define AT91C_EMAC_MPE ( 0x1 << 4 ) /* (EMAC) Management port enable. */ +#define AT91C_EMAC_CLRSTAT ( 0x1 << 5 ) /* (EMAC) Clear statistics registers. */ +#define AT91C_EMAC_INCSTAT ( 0x1 << 6 ) /* (EMAC) Increment statistics registers. */ +#define AT91C_EMAC_WESTAT ( 0x1 << 7 ) /* (EMAC) Write enable for statistics registers. */ +#define AT91C_EMAC_BP ( 0x1 << 8 ) /* (EMAC) Back pressure. */ +#define AT91C_EMAC_TSTART ( 0x1 << 9 ) /* (EMAC) Start Transmission. */ +#define AT91C_EMAC_THALT ( 0x1 << 10 ) /* (EMAC) Transmission Halt. */ +#define AT91C_EMAC_TPFR ( 0x1 << 11 ) /* (EMAC) Transmit pause frame */ +#define AT91C_EMAC_TZQ ( 0x1 << 12 ) /* (EMAC) Transmit zero quantum pause frame */ +/* -------- EMAC_NCFGR : (EMAC Offset: 0x4) Network Configuration Register -------- */ +#define AT91C_EMAC_SPD ( 0x1 << 0 ) /* (EMAC) Speed. */ +#define AT91C_EMAC_FD ( 0x1 << 1 ) /* (EMAC) Full duplex. */ +#define AT91C_EMAC_JFRAME ( 0x1 << 3 ) /* (EMAC) Jumbo Frames. */ +#define AT91C_EMAC_CAF ( 0x1 << 4 ) /* (EMAC) Copy all frames. */ +#define AT91C_EMAC_NBC ( 0x1 << 5 ) /* (EMAC) No broadcast. */ +#define AT91C_EMAC_MTI ( 0x1 << 6 ) /* (EMAC) Multicast hash event enable */ +#define AT91C_EMAC_UNI ( 0x1 << 7 ) /* (EMAC) Unicast hash enable. */ +#define AT91C_EMAC_BIG ( 0x1 << 8 ) /* (EMAC) Receive 1522 bytes. */ +#define AT91C_EMAC_EAE ( 0x1 << 9 ) /* (EMAC) External address match enable. */ +#define AT91C_EMAC_CLK ( 0x3 << 10 ) /* (EMAC) */ +#define AT91C_EMAC_CLK_HCLK_8 ( 0x0 << 10 ) /* (EMAC) HCLK divided by 8 */ +#define AT91C_EMAC_CLK_HCLK_16 ( 0x1 << 10 ) /* (EMAC) HCLK divided by 16 */ +#define AT91C_EMAC_CLK_HCLK_32 ( 0x2 << 10 ) /* (EMAC) HCLK divided by 32 */ +#define AT91C_EMAC_CLK_HCLK_64 ( 0x3 << 10 ) /* (EMAC) HCLK divided by 64 */ +#define AT91C_EMAC_RTY ( 0x1 << 12 ) /* (EMAC) */ +#define AT91C_EMAC_PAE ( 0x1 << 13 ) /* (EMAC) */ +#define AT91C_EMAC_RBOF ( 0x3 << 14 ) /* (EMAC) */ +#define AT91C_EMAC_RBOF_OFFSET_0 ( 0x0 << 14 ) /* (EMAC) no offset from start of receive buffer */ +#define AT91C_EMAC_RBOF_OFFSET_1 ( 0x1 << 14 ) /* (EMAC) one byte offset from start of receive buffer */ +#define AT91C_EMAC_RBOF_OFFSET_2 ( 0x2 << 14 ) /* (EMAC) two bytes offset from start of receive buffer */ +#define AT91C_EMAC_RBOF_OFFSET_3 ( 0x3 << 14 ) /* (EMAC) three bytes offset from start of receive buffer */ +#define AT91C_EMAC_RLCE ( 0x1 << 16 ) /* (EMAC) Receive Length field Checking Enable */ +#define AT91C_EMAC_DRFCS ( 0x1 << 17 ) /* (EMAC) Discard Receive FCS */ +#define AT91C_EMAC_EFRHD ( 0x1 << 18 ) /* (EMAC) */ +#define AT91C_EMAC_IRXFCS ( 0x1 << 19 ) /* (EMAC) Ignore RX FCS */ +/* -------- EMAC_NSR : (EMAC Offset: 0x8) Network Status Register -------- */ +#define AT91C_EMAC_LINKR ( 0x1 << 0 ) /* (EMAC) */ +#define AT91C_EMAC_MDIO ( 0x1 << 1 ) /* (EMAC) */ +#define AT91C_EMAC_IDLE ( 0x1 << 2 ) /* (EMAC) */ +/* -------- EMAC_TSR : (EMAC Offset: 0x14) Transmit Status Register -------- */ +#define AT91C_EMAC_UBR ( 0x1 << 0 ) /* (EMAC) */ +#define AT91C_EMAC_COL ( 0x1 << 1 ) /* (EMAC) */ +#define AT91C_EMAC_RLES ( 0x1 << 2 ) /* (EMAC) */ +#define AT91C_EMAC_TGO ( 0x1 << 3 ) /* (EMAC) Transmit Go */ +#define AT91C_EMAC_BEX ( 0x1 << 4 ) /* (EMAC) Buffers exhausted mid frame */ +#define AT91C_EMAC_COMP ( 0x1 << 5 ) /* (EMAC) */ +#define AT91C_EMAC_UND ( 0x1 << 6 ) /* (EMAC) */ +/* -------- EMAC_RSR : (EMAC Offset: 0x20) Receive Status Register -------- */ +#define AT91C_EMAC_BNA ( 0x1 << 0 ) /* (EMAC) */ +#define AT91C_EMAC_REC ( 0x1 << 1 ) /* (EMAC) */ +#define AT91C_EMAC_OVR ( 0x1 << 2 ) /* (EMAC) */ +/* -------- EMAC_ISR : (EMAC Offset: 0x24) Interrupt Status Register -------- */ +#define AT91C_EMAC_MFD ( 0x1 << 0 ) /* (EMAC) */ +#define AT91C_EMAC_RCOMP ( 0x1 << 1 ) /* (EMAC) */ +#define AT91C_EMAC_RXUBR ( 0x1 << 2 ) /* (EMAC) */ +#define AT91C_EMAC_TXUBR ( 0x1 << 3 ) /* (EMAC) */ +#define AT91C_EMAC_TUNDR ( 0x1 << 4 ) /* (EMAC) */ +#define AT91C_EMAC_RLEX ( 0x1 << 5 ) /* (EMAC) */ +#define AT91C_EMAC_TXERR ( 0x1 << 6 ) /* (EMAC) */ +#define AT91C_EMAC_TCOMP ( 0x1 << 7 ) /* (EMAC) */ +#define AT91C_EMAC_LINK ( 0x1 << 9 ) /* (EMAC) */ +#define AT91C_EMAC_ROVR ( 0x1 << 10 ) /* (EMAC) */ +#define AT91C_EMAC_HRESP ( 0x1 << 11 ) /* (EMAC) */ +#define AT91C_EMAC_PFRE ( 0x1 << 12 ) /* (EMAC) */ +#define AT91C_EMAC_PTZ ( 0x1 << 13 ) /* (EMAC) */ +/* -------- EMAC_IER : (EMAC Offset: 0x28) Interrupt Enable Register -------- */ +/* -------- EMAC_IDR : (EMAC Offset: 0x2c) Interrupt Disable Register -------- */ +/* -------- EMAC_IMR : (EMAC Offset: 0x30) Interrupt Mask Register -------- */ +/* -------- EMAC_MAN : (EMAC Offset: 0x34) PHY Maintenance Register -------- */ +#define AT91C_EMAC_DATA ( 0xFFFF << 0 ) /* (EMAC) */ +#define AT91C_EMAC_CODE ( 0x3 << 16 ) /* (EMAC) */ +#define AT91C_EMAC_REGA ( 0x1F << 18 ) /* (EMAC) */ +#define AT91C_EMAC_PHYA ( 0x1F << 23 ) /* (EMAC) */ +#define AT91C_EMAC_RW ( 0x3 << 28 ) /* (EMAC) */ +#define AT91C_EMAC_SOF ( 0x3 << 30 ) /* (EMAC) */ +/* -------- EMAC_USRIO : (EMAC Offset: 0xc0) USER Input Output Register -------- */ +#define AT91C_EMAC_RMII ( 0x1 << 0 ) /* (EMAC) Reduce MII */ +/* -------- EMAC_WOL : (EMAC Offset: 0xc4) Wake On LAN Register -------- */ +#define AT91C_EMAC_IP ( 0xFFFF << 0 ) /* (EMAC) ARP request IP address */ +#define AT91C_EMAC_MAG ( 0x1 << 16 ) /* (EMAC) Magic packet event enable */ +#define AT91C_EMAC_ARP ( 0x1 << 17 ) /* (EMAC) ARP request event enable */ +#define AT91C_EMAC_SA1 ( 0x1 << 18 ) /* (EMAC) Specific address register 1 event enable */ +/* -------- EMAC_REV : (EMAC Offset: 0xfc) Revision Register -------- */ +#define AT91C_EMAC_REVREF ( 0xFFFF << 0 ) /* (EMAC) */ +#define AT91C_EMAC_PARTREF ( 0xFFFF << 16 ) /* (EMAC) */ -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Analog to Digital Convertor -// ***************************************************************************** -// *** Register offset in AT91S_ADC structure *** -#define ADC_CR ( 0) // ADC Control Register -#define ADC_MR ( 4) // ADC Mode Register -#define ADC_CHER (16) // ADC Channel Enable Register -#define ADC_CHDR (20) // ADC Channel Disable Register -#define ADC_CHSR (24) // ADC Channel Status Register -#define ADC_SR (28) // ADC Status Register -#define ADC_LCDR (32) // ADC Last Converted Data Register -#define ADC_IER (36) // ADC Interrupt Enable Register -#define ADC_IDR (40) // ADC Interrupt Disable Register -#define ADC_IMR (44) // ADC Interrupt Mask Register -#define ADC_CDR0 (48) // ADC Channel Data Register 0 -#define ADC_CDR1 (52) // ADC Channel Data Register 1 -#define ADC_CDR2 (56) // ADC Channel Data Register 2 -#define ADC_CDR3 (60) // ADC Channel Data Register 3 -#define ADC_CDR4 (64) // ADC Channel Data Register 4 -#define ADC_CDR5 (68) // ADC Channel Data Register 5 -#define ADC_CDR6 (72) // ADC Channel Data Register 6 -#define ADC_CDR7 (76) // ADC Channel Data Register 7 -#define ADC_RPR (256) // Receive Pointer Register -#define ADC_RCR (260) // Receive Counter Register -#define ADC_TPR (264) // Transmit Pointer Register -#define ADC_TCR (268) // Transmit Counter Register -#define ADC_RNPR (272) // Receive Next Pointer Register -#define ADC_RNCR (276) // Receive Next Counter Register -#define ADC_TNPR (280) // Transmit Next Pointer Register -#define ADC_TNCR (284) // Transmit Next Counter Register -#define ADC_PTCR (288) // PDC Transfer Control Register -#define ADC_PTSR (292) // PDC Transfer Status Register -// -------- ADC_CR : (ADC Offset: 0x0) ADC Control Register -------- -#define AT91C_ADC_SWRST (0x1 << 0) // (ADC) Software Reset -#define AT91C_ADC_START (0x1 << 1) // (ADC) Start Conversion -// -------- ADC_MR : (ADC Offset: 0x4) ADC Mode Register -------- -#define AT91C_ADC_TRGEN (0x1 << 0) // (ADC) Trigger Enable -#define AT91C_ADC_TRGEN_DIS (0x0) // (ADC) Hradware triggers are disabled. Starting a conversion is only possible by software -#define AT91C_ADC_TRGEN_EN (0x1) // (ADC) Hardware trigger selected by TRGSEL field is enabled. -#define AT91C_ADC_TRGSEL (0x7 << 1) // (ADC) Trigger Selection -#define AT91C_ADC_TRGSEL_TIOA0 (0x0 << 1) // (ADC) Selected TRGSEL = TIAO0 -#define AT91C_ADC_TRGSEL_TIOA1 (0x1 << 1) // (ADC) Selected TRGSEL = TIAO1 -#define AT91C_ADC_TRGSEL_TIOA2 (0x2 << 1) // (ADC) Selected TRGSEL = TIAO2 -#define AT91C_ADC_TRGSEL_TIOA3 (0x3 << 1) // (ADC) Selected TRGSEL = TIAO3 -#define AT91C_ADC_TRGSEL_TIOA4 (0x4 << 1) // (ADC) Selected TRGSEL = TIAO4 -#define AT91C_ADC_TRGSEL_TIOA5 (0x5 << 1) // (ADC) Selected TRGSEL = TIAO5 -#define AT91C_ADC_TRGSEL_EXT (0x6 << 1) // (ADC) Selected TRGSEL = External Trigger -#define AT91C_ADC_LOWRES (0x1 << 4) // (ADC) Resolution. -#define AT91C_ADC_LOWRES_10_BIT (0x0 << 4) // (ADC) 10-bit resolution -#define AT91C_ADC_LOWRES_8_BIT (0x1 << 4) // (ADC) 8-bit resolution -#define AT91C_ADC_SLEEP (0x1 << 5) // (ADC) Sleep Mode -#define AT91C_ADC_SLEEP_NORMAL_MODE (0x0 << 5) // (ADC) Normal Mode -#define AT91C_ADC_SLEEP_MODE (0x1 << 5) // (ADC) Sleep Mode -#define AT91C_ADC_PRESCAL (0x3F << 8) // (ADC) Prescaler rate selection -#define AT91C_ADC_STARTUP (0x1F << 16) // (ADC) Startup Time -#define AT91C_ADC_SHTIM (0xF << 24) // (ADC) Sample & Hold Time -// -------- ADC_CHER : (ADC Offset: 0x10) ADC Channel Enable Register -------- -#define AT91C_ADC_CH0 (0x1 << 0) // (ADC) Channel 0 -#define AT91C_ADC_CH1 (0x1 << 1) // (ADC) Channel 1 -#define AT91C_ADC_CH2 (0x1 << 2) // (ADC) Channel 2 -#define AT91C_ADC_CH3 (0x1 << 3) // (ADC) Channel 3 -#define AT91C_ADC_CH4 (0x1 << 4) // (ADC) Channel 4 -#define AT91C_ADC_CH5 (0x1 << 5) // (ADC) Channel 5 -#define AT91C_ADC_CH6 (0x1 << 6) // (ADC) Channel 6 -#define AT91C_ADC_CH7 (0x1 << 7) // (ADC) Channel 7 -// -------- ADC_CHDR : (ADC Offset: 0x14) ADC Channel Disable Register -------- -// -------- ADC_CHSR : (ADC Offset: 0x18) ADC Channel Status Register -------- -// -------- ADC_SR : (ADC Offset: 0x1c) ADC Status Register -------- -#define AT91C_ADC_EOC0 (0x1 << 0) // (ADC) End of Conversion -#define AT91C_ADC_EOC1 (0x1 << 1) // (ADC) End of Conversion -#define AT91C_ADC_EOC2 (0x1 << 2) // (ADC) End of Conversion -#define AT91C_ADC_EOC3 (0x1 << 3) // (ADC) End of Conversion -#define AT91C_ADC_EOC4 (0x1 << 4) // (ADC) End of Conversion -#define AT91C_ADC_EOC5 (0x1 << 5) // (ADC) End of Conversion -#define AT91C_ADC_EOC6 (0x1 << 6) // (ADC) End of Conversion -#define AT91C_ADC_EOC7 (0x1 << 7) // (ADC) End of Conversion -#define AT91C_ADC_OVRE0 (0x1 << 8) // (ADC) Overrun Error -#define AT91C_ADC_OVRE1 (0x1 << 9) // (ADC) Overrun Error -#define AT91C_ADC_OVRE2 (0x1 << 10) // (ADC) Overrun Error -#define AT91C_ADC_OVRE3 (0x1 << 11) // (ADC) Overrun Error -#define AT91C_ADC_OVRE4 (0x1 << 12) // (ADC) Overrun Error -#define AT91C_ADC_OVRE5 (0x1 << 13) // (ADC) Overrun Error -#define AT91C_ADC_OVRE6 (0x1 << 14) // (ADC) Overrun Error -#define AT91C_ADC_OVRE7 (0x1 << 15) // (ADC) Overrun Error -#define AT91C_ADC_DRDY (0x1 << 16) // (ADC) Data Ready -#define AT91C_ADC_GOVRE (0x1 << 17) // (ADC) General Overrun -#define AT91C_ADC_ENDRX (0x1 << 18) // (ADC) End of Receiver Transfer -#define AT91C_ADC_RXBUFF (0x1 << 19) // (ADC) RXBUFF Interrupt -// -------- ADC_LCDR : (ADC Offset: 0x20) ADC Last Converted Data Register -------- -#define AT91C_ADC_LDATA (0x3FF << 0) // (ADC) Last Data Converted -// -------- ADC_IER : (ADC Offset: 0x24) ADC Interrupt Enable Register -------- -// -------- ADC_IDR : (ADC Offset: 0x28) ADC Interrupt Disable Register -------- -// -------- ADC_IMR : (ADC Offset: 0x2c) ADC Interrupt Mask Register -------- -// -------- ADC_CDR0 : (ADC Offset: 0x30) ADC Channel Data Register 0 -------- -#define AT91C_ADC_DATA (0x3FF << 0) // (ADC) Converted Data -// -------- ADC_CDR1 : (ADC Offset: 0x34) ADC Channel Data Register 1 -------- -// -------- ADC_CDR2 : (ADC Offset: 0x38) ADC Channel Data Register 2 -------- -// -------- ADC_CDR3 : (ADC Offset: 0x3c) ADC Channel Data Register 3 -------- -// -------- ADC_CDR4 : (ADC Offset: 0x40) ADC Channel Data Register 4 -------- -// -------- ADC_CDR5 : (ADC Offset: 0x44) ADC Channel Data Register 5 -------- -// -------- ADC_CDR6 : (ADC Offset: 0x48) ADC Channel Data Register 6 -------- -// -------- ADC_CDR7 : (ADC Offset: 0x4c) ADC Channel Data Register 7 -------- +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR Analog to Digital Convertor */ +/* ***************************************************************************** */ +/* *** Register offset in AT91S_ADC structure *** */ +#define ADC_CR ( 0 ) /* ADC Control Register */ +#define ADC_MR ( 4 ) /* ADC Mode Register */ +#define ADC_CHER ( 16 ) /* ADC Channel Enable Register */ +#define ADC_CHDR ( 20 ) /* ADC Channel Disable Register */ +#define ADC_CHSR ( 24 ) /* ADC Channel Status Register */ +#define ADC_SR ( 28 ) /* ADC Status Register */ +#define ADC_LCDR ( 32 ) /* ADC Last Converted Data Register */ +#define ADC_IER ( 36 ) /* ADC Interrupt Enable Register */ +#define ADC_IDR ( 40 ) /* ADC Interrupt Disable Register */ +#define ADC_IMR ( 44 ) /* ADC Interrupt Mask Register */ +#define ADC_CDR0 ( 48 ) /* ADC Channel Data Register 0 */ +#define ADC_CDR1 ( 52 ) /* ADC Channel Data Register 1 */ +#define ADC_CDR2 ( 56 ) /* ADC Channel Data Register 2 */ +#define ADC_CDR3 ( 60 ) /* ADC Channel Data Register 3 */ +#define ADC_CDR4 ( 64 ) /* ADC Channel Data Register 4 */ +#define ADC_CDR5 ( 68 ) /* ADC Channel Data Register 5 */ +#define ADC_CDR6 ( 72 ) /* ADC Channel Data Register 6 */ +#define ADC_CDR7 ( 76 ) /* ADC Channel Data Register 7 */ +#define ADC_RPR ( 256 ) /* Receive Pointer Register */ +#define ADC_RCR ( 260 ) /* Receive Counter Register */ +#define ADC_TPR ( 264 ) /* Transmit Pointer Register */ +#define ADC_TCR ( 268 ) /* Transmit Counter Register */ +#define ADC_RNPR ( 272 ) /* Receive Next Pointer Register */ +#define ADC_RNCR ( 276 ) /* Receive Next Counter Register */ +#define ADC_TNPR ( 280 ) /* Transmit Next Pointer Register */ +#define ADC_TNCR ( 284 ) /* Transmit Next Counter Register */ +#define ADC_PTCR ( 288 ) /* PDC Transfer Control Register */ +#define ADC_PTSR ( 292 ) /* PDC Transfer Status Register */ +/* -------- ADC_CR : (ADC Offset: 0x0) ADC Control Register -------- */ +#define AT91C_ADC_SWRST ( 0x1 << 0 ) /* (ADC) Software Reset */ +#define AT91C_ADC_START ( 0x1 << 1 ) /* (ADC) Start Conversion */ +/* -------- ADC_MR : (ADC Offset: 0x4) ADC Mode Register -------- */ +#define AT91C_ADC_TRGEN ( 0x1 << 0 ) /* (ADC) Trigger Enable */ +#define AT91C_ADC_TRGEN_DIS ( 0x0 ) /* (ADC) Hardware triggers are disabled. Starting a conversion is only possible by software */ +#define AT91C_ADC_TRGEN_EN ( 0x1 ) /* (ADC) Hardware trigger selected by TRGSEL field is enabled. */ +#define AT91C_ADC_TRGSEL ( 0x7 << 1 ) /* (ADC) Trigger Selection */ +#define AT91C_ADC_TRGSEL_TIOA0 ( 0x0 << 1 ) /* (ADC) Selected TRGSEL = TIAO0 */ +#define AT91C_ADC_TRGSEL_TIOA1 ( 0x1 << 1 ) /* (ADC) Selected TRGSEL = TIAO1 */ +#define AT91C_ADC_TRGSEL_TIOA2 ( 0x2 << 1 ) /* (ADC) Selected TRGSEL = TIAO2 */ +#define AT91C_ADC_TRGSEL_TIOA3 ( 0x3 << 1 ) /* (ADC) Selected TRGSEL = TIAO3 */ +#define AT91C_ADC_TRGSEL_TIOA4 ( 0x4 << 1 ) /* (ADC) Selected TRGSEL = TIAO4 */ +#define AT91C_ADC_TRGSEL_TIOA5 ( 0x5 << 1 ) /* (ADC) Selected TRGSEL = TIAO5 */ +#define AT91C_ADC_TRGSEL_EXT ( 0x6 << 1 ) /* (ADC) Selected TRGSEL = External Trigger */ +#define AT91C_ADC_LOWRES ( 0x1 << 4 ) /* (ADC) Resolution. */ +#define AT91C_ADC_LOWRES_10_BIT ( 0x0 << 4 ) /* (ADC) 10-bit resolution */ +#define AT91C_ADC_LOWRES_8_BIT ( 0x1 << 4 ) /* (ADC) 8-bit resolution */ +#define AT91C_ADC_SLEEP ( 0x1 << 5 ) /* (ADC) Sleep Mode */ +#define AT91C_ADC_SLEEP_NORMAL_MODE ( 0x0 << 5 ) /* (ADC) Normal Mode */ +#define AT91C_ADC_SLEEP_MODE ( 0x1 << 5 ) /* (ADC) Sleep Mode */ +#define AT91C_ADC_PRESCAL ( 0x3F << 8 ) /* (ADC) Prescaler rate selection */ +#define AT91C_ADC_STARTUP ( 0x1F << 16 ) /* (ADC) Startup Time */ +#define AT91C_ADC_SHTIM ( 0xF << 24 ) /* (ADC) Sample & Hold Time */ +/* -------- ADC_CHER : (ADC Offset: 0x10) ADC Channel Enable Register -------- */ +#define AT91C_ADC_CH0 ( 0x1 << 0 ) /* (ADC) Channel 0 */ +#define AT91C_ADC_CH1 ( 0x1 << 1 ) /* (ADC) Channel 1 */ +#define AT91C_ADC_CH2 ( 0x1 << 2 ) /* (ADC) Channel 2 */ +#define AT91C_ADC_CH3 ( 0x1 << 3 ) /* (ADC) Channel 3 */ +#define AT91C_ADC_CH4 ( 0x1 << 4 ) /* (ADC) Channel 4 */ +#define AT91C_ADC_CH5 ( 0x1 << 5 ) /* (ADC) Channel 5 */ +#define AT91C_ADC_CH6 ( 0x1 << 6 ) /* (ADC) Channel 6 */ +#define AT91C_ADC_CH7 ( 0x1 << 7 ) /* (ADC) Channel 7 */ +/* -------- ADC_CHDR : (ADC Offset: 0x14) ADC Channel Disable Register -------- */ +/* -------- ADC_CHSR : (ADC Offset: 0x18) ADC Channel Status Register -------- */ +/* -------- ADC_SR : (ADC Offset: 0x1c) ADC Status Register -------- */ +#define AT91C_ADC_EOC0 ( 0x1 << 0 ) /* (ADC) End of Conversion */ +#define AT91C_ADC_EOC1 ( 0x1 << 1 ) /* (ADC) End of Conversion */ +#define AT91C_ADC_EOC2 ( 0x1 << 2 ) /* (ADC) End of Conversion */ +#define AT91C_ADC_EOC3 ( 0x1 << 3 ) /* (ADC) End of Conversion */ +#define AT91C_ADC_EOC4 ( 0x1 << 4 ) /* (ADC) End of Conversion */ +#define AT91C_ADC_EOC5 ( 0x1 << 5 ) /* (ADC) End of Conversion */ +#define AT91C_ADC_EOC6 ( 0x1 << 6 ) /* (ADC) End of Conversion */ +#define AT91C_ADC_EOC7 ( 0x1 << 7 ) /* (ADC) End of Conversion */ +#define AT91C_ADC_OVRE0 ( 0x1 << 8 ) /* (ADC) Overrun Error */ +#define AT91C_ADC_OVRE1 ( 0x1 << 9 ) /* (ADC) Overrun Error */ +#define AT91C_ADC_OVRE2 ( 0x1 << 10 ) /* (ADC) Overrun Error */ +#define AT91C_ADC_OVRE3 ( 0x1 << 11 ) /* (ADC) Overrun Error */ +#define AT91C_ADC_OVRE4 ( 0x1 << 12 ) /* (ADC) Overrun Error */ +#define AT91C_ADC_OVRE5 ( 0x1 << 13 ) /* (ADC) Overrun Error */ +#define AT91C_ADC_OVRE6 ( 0x1 << 14 ) /* (ADC) Overrun Error */ +#define AT91C_ADC_OVRE7 ( 0x1 << 15 ) /* (ADC) Overrun Error */ +#define AT91C_ADC_DRDY ( 0x1 << 16 ) /* (ADC) Data Ready */ +#define AT91C_ADC_GOVRE ( 0x1 << 17 ) /* (ADC) General Overrun */ +#define AT91C_ADC_ENDRX ( 0x1 << 18 ) /* (ADC) End of Receiver Transfer */ +#define AT91C_ADC_RXBUFF ( 0x1 << 19 ) /* (ADC) RXBUFF Interrupt */ +/* -------- ADC_LCDR : (ADC Offset: 0x20) ADC Last Converted Data Register -------- */ +#define AT91C_ADC_LDATA ( 0x3FF << 0 ) /* (ADC) Last Data Converted */ +/* -------- ADC_IER : (ADC Offset: 0x24) ADC Interrupt Enable Register -------- */ +/* -------- ADC_IDR : (ADC Offset: 0x28) ADC Interrupt Disable Register -------- */ +/* -------- ADC_IMR : (ADC Offset: 0x2c) ADC Interrupt Mask Register -------- */ +/* -------- ADC_CDR0 : (ADC Offset: 0x30) ADC Channel Data Register 0 -------- */ +#define AT91C_ADC_DATA ( 0x3FF << 0 ) /* (ADC) Converted Data */ +/* -------- ADC_CDR1 : (ADC Offset: 0x34) ADC Channel Data Register 1 -------- */ +/* -------- ADC_CDR2 : (ADC Offset: 0x38) ADC Channel Data Register 2 -------- */ +/* -------- ADC_CDR3 : (ADC Offset: 0x3c) ADC Channel Data Register 3 -------- */ +/* -------- ADC_CDR4 : (ADC Offset: 0x40) ADC Channel Data Register 4 -------- */ +/* -------- ADC_CDR5 : (ADC Offset: 0x44) ADC Channel Data Register 5 -------- */ +/* -------- ADC_CDR6 : (ADC Offset: 0x48) ADC Channel Data Register 6 -------- */ +/* -------- ADC_CDR7 : (ADC Offset: 0x4c) ADC Channel Data Register 7 -------- */ -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Advanced Encryption Standard -// ***************************************************************************** -// *** Register offset in AT91S_AES structure *** -#define AES_CR ( 0) // Control Register -#define AES_MR ( 4) // Mode Register -#define AES_IER (16) // Interrupt Enable Register -#define AES_IDR (20) // Interrupt Disable Register -#define AES_IMR (24) // Interrupt Mask Register -#define AES_ISR (28) // Interrupt Status Register -#define AES_KEYWxR (32) // Key Word x Register -#define AES_IDATAxR (64) // Input Data x Register -#define AES_ODATAxR (80) // Output Data x Register -#define AES_IVxR (96) // Initialization Vector x Register -#define AES_VR (252) // AES Version Register -#define AES_RPR (256) // Receive Pointer Register -#define AES_RCR (260) // Receive Counter Register -#define AES_TPR (264) // Transmit Pointer Register -#define AES_TCR (268) // Transmit Counter Register -#define AES_RNPR (272) // Receive Next Pointer Register -#define AES_RNCR (276) // Receive Next Counter Register -#define AES_TNPR (280) // Transmit Next Pointer Register -#define AES_TNCR (284) // Transmit Next Counter Register -#define AES_PTCR (288) // PDC Transfer Control Register -#define AES_PTSR (292) // PDC Transfer Status Register -// -------- AES_CR : (AES Offset: 0x0) Control Register -------- -#define AT91C_AES_START (0x1 << 0) // (AES) Starts Processing -#define AT91C_AES_SWRST (0x1 << 8) // (AES) Software Reset -#define AT91C_AES_LOADSEED (0x1 << 16) // (AES) Random Number Generator Seed Loading -// -------- AES_MR : (AES Offset: 0x4) Mode Register -------- -#define AT91C_AES_CIPHER (0x1 << 0) // (AES) Processing Mode -#define AT91C_AES_PROCDLY (0xF << 4) // (AES) Processing Delay -#define AT91C_AES_SMOD (0x3 << 8) // (AES) Start Mode -#define AT91C_AES_SMOD_MANUAL (0x0 << 8) // (AES) Manual Mode: The START bit in register AES_CR must be set to begin encryption or decryption. -#define AT91C_AES_SMOD_AUTO (0x1 << 8) // (AES) Auto Mode: no action in AES_CR is necessary (cf datasheet). -#define AT91C_AES_SMOD_PDC (0x2 << 8) // (AES) PDC Mode (cf datasheet). -#define AT91C_AES_OPMOD (0x7 << 12) // (AES) Operation Mode -#define AT91C_AES_OPMOD_ECB (0x0 << 12) // (AES) ECB Electronic CodeBook mode. -#define AT91C_AES_OPMOD_CBC (0x1 << 12) // (AES) CBC Cipher Block Chaining mode. -#define AT91C_AES_OPMOD_OFB (0x2 << 12) // (AES) OFB Output Feedback mode. -#define AT91C_AES_OPMOD_CFB (0x3 << 12) // (AES) CFB Cipher Feedback mode. -#define AT91C_AES_OPMOD_CTR (0x4 << 12) // (AES) CTR Counter mode. -#define AT91C_AES_LOD (0x1 << 15) // (AES) Last Output Data Mode -#define AT91C_AES_CFBS (0x7 << 16) // (AES) Cipher Feedback Data Size -#define AT91C_AES_CFBS_128_BIT (0x0 << 16) // (AES) 128-bit. -#define AT91C_AES_CFBS_64_BIT (0x1 << 16) // (AES) 64-bit. -#define AT91C_AES_CFBS_32_BIT (0x2 << 16) // (AES) 32-bit. -#define AT91C_AES_CFBS_16_BIT (0x3 << 16) // (AES) 16-bit. -#define AT91C_AES_CFBS_8_BIT (0x4 << 16) // (AES) 8-bit. -#define AT91C_AES_CKEY (0xF << 20) // (AES) Countermeasure Key -#define AT91C_AES_CTYPE (0x1F << 24) // (AES) Countermeasure Type -#define AT91C_AES_CTYPE_TYPE1_EN (0x1 << 24) // (AES) Countermeasure type 1 is enabled. -#define AT91C_AES_CTYPE_TYPE2_EN (0x2 << 24) // (AES) Countermeasure type 2 is enabled. -#define AT91C_AES_CTYPE_TYPE3_EN (0x4 << 24) // (AES) Countermeasure type 3 is enabled. -#define AT91C_AES_CTYPE_TYPE4_EN (0x8 << 24) // (AES) Countermeasure type 4 is enabled. -#define AT91C_AES_CTYPE_TYPE5_EN (0x10 << 24) // (AES) Countermeasure type 5 is enabled. -// -------- AES_IER : (AES Offset: 0x10) Interrupt Enable Register -------- -#define AT91C_AES_DATRDY (0x1 << 0) // (AES) DATRDY -#define AT91C_AES_ENDRX (0x1 << 1) // (AES) PDC Read Buffer End -#define AT91C_AES_ENDTX (0x1 << 2) // (AES) PDC Write Buffer End -#define AT91C_AES_RXBUFF (0x1 << 3) // (AES) PDC Read Buffer Full -#define AT91C_AES_TXBUFE (0x1 << 4) // (AES) PDC Write Buffer Empty -#define AT91C_AES_URAD (0x1 << 8) // (AES) Unspecified Register Access Detection -// -------- AES_IDR : (AES Offset: 0x14) Interrupt Disable Register -------- -// -------- AES_IMR : (AES Offset: 0x18) Interrupt Mask Register -------- -// -------- AES_ISR : (AES Offset: 0x1c) Interrupt Status Register -------- -#define AT91C_AES_URAT (0x7 << 12) // (AES) Unspecified Register Access Type Status -#define AT91C_AES_URAT_IN_DAT_WRITE_DATPROC (0x0 << 12) // (AES) Input data register written during the data processing in PDC mode. -#define AT91C_AES_URAT_OUT_DAT_READ_DATPROC (0x1 << 12) // (AES) Output data register read during the data processing. -#define AT91C_AES_URAT_MODEREG_WRITE_DATPROC (0x2 << 12) // (AES) Mode register written during the data processing. -#define AT91C_AES_URAT_OUT_DAT_READ_SUBKEY (0x3 << 12) // (AES) Output data register read during the sub-keys generation. -#define AT91C_AES_URAT_MODEREG_WRITE_SUBKEY (0x4 << 12) // (AES) Mode register written during the sub-keys generation. -#define AT91C_AES_URAT_WO_REG_READ (0x5 << 12) // (AES) Write-only register read access. +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR Advanced Encryption Standard */ +/* ***************************************************************************** */ +/* *** Register offset in AT91S_AES structure *** */ +#define AES_CR ( 0 ) /* Control Register */ +#define AES_MR ( 4 ) /* Mode Register */ +#define AES_IER ( 16 ) /* Interrupt Enable Register */ +#define AES_IDR ( 20 ) /* Interrupt Disable Register */ +#define AES_IMR ( 24 ) /* Interrupt Mask Register */ +#define AES_ISR ( 28 ) /* Interrupt Status Register */ +#define AES_KEYWxR ( 32 ) /* Key Word x Register */ +#define AES_IDATAxR ( 64 ) /* Input Data x Register */ +#define AES_ODATAxR ( 80 ) /* Output Data x Register */ +#define AES_IVxR ( 96 ) /* Initialization Vector x Register */ +#define AES_VR ( 252 ) /* AES Version Register */ +#define AES_RPR ( 256 ) /* Receive Pointer Register */ +#define AES_RCR ( 260 ) /* Receive Counter Register */ +#define AES_TPR ( 264 ) /* Transmit Pointer Register */ +#define AES_TCR ( 268 ) /* Transmit Counter Register */ +#define AES_RNPR ( 272 ) /* Receive Next Pointer Register */ +#define AES_RNCR ( 276 ) /* Receive Next Counter Register */ +#define AES_TNPR ( 280 ) /* Transmit Next Pointer Register */ +#define AES_TNCR ( 284 ) /* Transmit Next Counter Register */ +#define AES_PTCR ( 288 ) /* PDC Transfer Control Register */ +#define AES_PTSR ( 292 ) /* PDC Transfer Status Register */ +/* -------- AES_CR : (AES Offset: 0x0) Control Register -------- */ +#define AT91C_AES_START ( 0x1 << 0 ) /* (AES) Starts Processing */ +#define AT91C_AES_SWRST ( 0x1 << 8 ) /* (AES) Software Reset */ +#define AT91C_AES_LOADSEED ( 0x1 << 16 ) /* (AES) Random Number Generator Seed Loading */ +/* -------- AES_MR : (AES Offset: 0x4) Mode Register -------- */ +#define AT91C_AES_CIPHER ( 0x1 << 0 ) /* (AES) Processing Mode */ +#define AT91C_AES_PROCDLY ( 0xF << 4 ) /* (AES) Processing Delay */ +#define AT91C_AES_SMOD ( 0x3 << 8 ) /* (AES) Start Mode */ +#define AT91C_AES_SMOD_MANUAL ( 0x0 << 8 ) /* (AES) Manual Mode: The START bit in register AES_CR must be set to begin encryption or decryption. */ +#define AT91C_AES_SMOD_AUTO ( 0x1 << 8 ) /* (AES) Auto Mode: no action in AES_CR is necessary (cf datasheet). */ +#define AT91C_AES_SMOD_PDC ( 0x2 << 8 ) /* (AES) PDC Mode (cf datasheet). */ +#define AT91C_AES_OPMOD ( 0x7 << 12 ) /* (AES) Operation Mode */ +#define AT91C_AES_OPMOD_ECB ( 0x0 << 12 ) /* (AES) ECB Electronic CodeBook mode. */ +#define AT91C_AES_OPMOD_CBC ( 0x1 << 12 ) /* (AES) CBC Cipher Block Chaining mode. */ +#define AT91C_AES_OPMOD_OFB ( 0x2 << 12 ) /* (AES) OFB Output Feedback mode. */ +#define AT91C_AES_OPMOD_CFB ( 0x3 << 12 ) /* (AES) CFB Cipher Feedback mode. */ +#define AT91C_AES_OPMOD_CTR ( 0x4 << 12 ) /* (AES) CTR Counter mode. */ +#define AT91C_AES_LOD ( 0x1 << 15 ) /* (AES) Last Output Data Mode */ +#define AT91C_AES_CFBS ( 0x7 << 16 ) /* (AES) Cipher Feedback Data Size */ +#define AT91C_AES_CFBS_128_BIT ( 0x0 << 16 ) /* (AES) 128-bit. */ +#define AT91C_AES_CFBS_64_BIT ( 0x1 << 16 ) /* (AES) 64-bit. */ +#define AT91C_AES_CFBS_32_BIT ( 0x2 << 16 ) /* (AES) 32-bit. */ +#define AT91C_AES_CFBS_16_BIT ( 0x3 << 16 ) /* (AES) 16-bit. */ +#define AT91C_AES_CFBS_8_BIT ( 0x4 << 16 ) /* (AES) 8-bit. */ +#define AT91C_AES_CKEY ( 0xF << 20 ) /* (AES) Countermeasure Key */ +#define AT91C_AES_CTYPE ( 0x1F << 24 ) /* (AES) Countermeasure Type */ +#define AT91C_AES_CTYPE_TYPE1_EN ( 0x1 << 24 ) /* (AES) Countermeasure type 1 is enabled. */ +#define AT91C_AES_CTYPE_TYPE2_EN ( 0x2 << 24 ) /* (AES) Countermeasure type 2 is enabled. */ +#define AT91C_AES_CTYPE_TYPE3_EN ( 0x4 << 24 ) /* (AES) Countermeasure type 3 is enabled. */ +#define AT91C_AES_CTYPE_TYPE4_EN ( 0x8 << 24 ) /* (AES) Countermeasure type 4 is enabled. */ +#define AT91C_AES_CTYPE_TYPE5_EN ( 0x10 << 24 ) /* (AES) Countermeasure type 5 is enabled. */ +/* -------- AES_IER : (AES Offset: 0x10) Interrupt Enable Register -------- */ +#define AT91C_AES_DATRDY ( 0x1 << 0 ) /* (AES) DATRDY */ +#define AT91C_AES_ENDRX ( 0x1 << 1 ) /* (AES) PDC Read Buffer End */ +#define AT91C_AES_ENDTX ( 0x1 << 2 ) /* (AES) PDC Write Buffer End */ +#define AT91C_AES_RXBUFF ( 0x1 << 3 ) /* (AES) PDC Read Buffer Full */ +#define AT91C_AES_TXBUFE ( 0x1 << 4 ) /* (AES) PDC Write Buffer Empty */ +#define AT91C_AES_URAD ( 0x1 << 8 ) /* (AES) Unspecified Register Access Detection */ +/* -------- AES_IDR : (AES Offset: 0x14) Interrupt Disable Register -------- */ +/* -------- AES_IMR : (AES Offset: 0x18) Interrupt Mask Register -------- */ +/* -------- AES_ISR : (AES Offset: 0x1c) Interrupt Status Register -------- */ +#define AT91C_AES_URAT ( 0x7 << 12 ) /* (AES) Unspecified Register Access Type Status */ +#define AT91C_AES_URAT_IN_DAT_WRITE_DATPROC ( 0x0 << 12 ) /* (AES) Input data register written during the data processing in PDC mode. */ +#define AT91C_AES_URAT_OUT_DAT_READ_DATPROC ( 0x1 << 12 ) /* (AES) Output data register read during the data processing. */ +#define AT91C_AES_URAT_MODEREG_WRITE_DATPROC ( 0x2 << 12 ) /* (AES) Mode register written during the data processing. */ +#define AT91C_AES_URAT_OUT_DAT_READ_SUBKEY ( 0x3 << 12 ) /* (AES) Output data register read during the sub-keys generation. */ +#define AT91C_AES_URAT_MODEREG_WRITE_SUBKEY ( 0x4 << 12 ) /* (AES) Mode register written during the sub-keys generation. */ +#define AT91C_AES_URAT_WO_REG_READ ( 0x5 << 12 ) /* (AES) Write-only register read access. */ -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Triple Data Encryption Standard -// ***************************************************************************** -// *** Register offset in AT91S_TDES structure *** -#define TDES_CR ( 0) // Control Register -#define TDES_MR ( 4) // Mode Register -#define TDES_IER (16) // Interrupt Enable Register -#define TDES_IDR (20) // Interrupt Disable Register -#define TDES_IMR (24) // Interrupt Mask Register -#define TDES_ISR (28) // Interrupt Status Register -#define TDES_KEY1WxR (32) // Key 1 Word x Register -#define TDES_KEY2WxR (40) // Key 2 Word x Register -#define TDES_KEY3WxR (48) // Key 3 Word x Register -#define TDES_IDATAxR (64) // Input Data x Register -#define TDES_ODATAxR (80) // Output Data x Register -#define TDES_IVxR (96) // Initialization Vector x Register -#define TDES_VR (252) // TDES Version Register -#define TDES_RPR (256) // Receive Pointer Register -#define TDES_RCR (260) // Receive Counter Register -#define TDES_TPR (264) // Transmit Pointer Register -#define TDES_TCR (268) // Transmit Counter Register -#define TDES_RNPR (272) // Receive Next Pointer Register -#define TDES_RNCR (276) // Receive Next Counter Register -#define TDES_TNPR (280) // Transmit Next Pointer Register -#define TDES_TNCR (284) // Transmit Next Counter Register -#define TDES_PTCR (288) // PDC Transfer Control Register -#define TDES_PTSR (292) // PDC Transfer Status Register -// -------- TDES_CR : (TDES Offset: 0x0) Control Register -------- -#define AT91C_TDES_START (0x1 << 0) // (TDES) Starts Processing -#define AT91C_TDES_SWRST (0x1 << 8) // (TDES) Software Reset -// -------- TDES_MR : (TDES Offset: 0x4) Mode Register -------- -#define AT91C_TDES_CIPHER (0x1 << 0) // (TDES) Processing Mode -#define AT91C_TDES_TDESMOD (0x1 << 1) // (TDES) Single or Triple DES Mode -#define AT91C_TDES_KEYMOD (0x1 << 4) // (TDES) Key Mode -#define AT91C_TDES_SMOD (0x3 << 8) // (TDES) Start Mode -#define AT91C_TDES_SMOD_MANUAL (0x0 << 8) // (TDES) Manual Mode: The START bit in register TDES_CR must be set to begin encryption or decryption. -#define AT91C_TDES_SMOD_AUTO (0x1 << 8) // (TDES) Auto Mode: no action in TDES_CR is necessary (cf datasheet). -#define AT91C_TDES_SMOD_PDC (0x2 << 8) // (TDES) PDC Mode (cf datasheet). -#define AT91C_TDES_OPMOD (0x3 << 12) // (TDES) Operation Mode -#define AT91C_TDES_OPMOD_ECB (0x0 << 12) // (TDES) ECB Electronic CodeBook mode. -#define AT91C_TDES_OPMOD_CBC (0x1 << 12) // (TDES) CBC Cipher Block Chaining mode. -#define AT91C_TDES_OPMOD_OFB (0x2 << 12) // (TDES) OFB Output Feedback mode. -#define AT91C_TDES_OPMOD_CFB (0x3 << 12) // (TDES) CFB Cipher Feedback mode. -#define AT91C_TDES_LOD (0x1 << 15) // (TDES) Last Output Data Mode -#define AT91C_TDES_CFBS (0x3 << 16) // (TDES) Cipher Feedback Data Size -#define AT91C_TDES_CFBS_64_BIT (0x0 << 16) // (TDES) 64-bit. -#define AT91C_TDES_CFBS_32_BIT (0x1 << 16) // (TDES) 32-bit. -#define AT91C_TDES_CFBS_16_BIT (0x2 << 16) // (TDES) 16-bit. -#define AT91C_TDES_CFBS_8_BIT (0x3 << 16) // (TDES) 8-bit. -// -------- TDES_IER : (TDES Offset: 0x10) Interrupt Enable Register -------- -#define AT91C_TDES_DATRDY (0x1 << 0) // (TDES) DATRDY -#define AT91C_TDES_ENDRX (0x1 << 1) // (TDES) PDC Read Buffer End -#define AT91C_TDES_ENDTX (0x1 << 2) // (TDES) PDC Write Buffer End -#define AT91C_TDES_RXBUFF (0x1 << 3) // (TDES) PDC Read Buffer Full -#define AT91C_TDES_TXBUFE (0x1 << 4) // (TDES) PDC Write Buffer Empty -#define AT91C_TDES_URAD (0x1 << 8) // (TDES) Unspecified Register Access Detection -// -------- TDES_IDR : (TDES Offset: 0x14) Interrupt Disable Register -------- -// -------- TDES_IMR : (TDES Offset: 0x18) Interrupt Mask Register -------- -// -------- TDES_ISR : (TDES Offset: 0x1c) Interrupt Status Register -------- -#define AT91C_TDES_URAT (0x3 << 12) // (TDES) Unspecified Register Access Type Status -#define AT91C_TDES_URAT_IN_DAT_WRITE_DATPROC (0x0 << 12) // (TDES) Input data register written during the data processing in PDC mode. -#define AT91C_TDES_URAT_OUT_DAT_READ_DATPROC (0x1 << 12) // (TDES) Output data register read during the data processing. -#define AT91C_TDES_URAT_MODEREG_WRITE_DATPROC (0x2 << 12) // (TDES) Mode register written during the data processing. -#define AT91C_TDES_URAT_WO_REG_READ (0x3 << 12) // (TDES) Write-only register read access. +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR Triple Data Encryption Standard */ +/* ***************************************************************************** */ +/* *** Register offset in AT91S_TDES structure *** */ +#define TDES_CR ( 0 ) /* Control Register */ +#define TDES_MR ( 4 ) /* Mode Register */ +#define TDES_IER ( 16 ) /* Interrupt Enable Register */ +#define TDES_IDR ( 20 ) /* Interrupt Disable Register */ +#define TDES_IMR ( 24 ) /* Interrupt Mask Register */ +#define TDES_ISR ( 28 ) /* Interrupt Status Register */ +#define TDES_KEY1WxR ( 32 ) /* Key 1 Word x Register */ +#define TDES_KEY2WxR ( 40 ) /* Key 2 Word x Register */ +#define TDES_KEY3WxR ( 48 ) /* Key 3 Word x Register */ +#define TDES_IDATAxR ( 64 ) /* Input Data x Register */ +#define TDES_ODATAxR ( 80 ) /* Output Data x Register */ +#define TDES_IVxR ( 96 ) /* Initialization Vector x Register */ +#define TDES_VR ( 252 ) /* TDES Version Register */ +#define TDES_RPR ( 256 ) /* Receive Pointer Register */ +#define TDES_RCR ( 260 ) /* Receive Counter Register */ +#define TDES_TPR ( 264 ) /* Transmit Pointer Register */ +#define TDES_TCR ( 268 ) /* Transmit Counter Register */ +#define TDES_RNPR ( 272 ) /* Receive Next Pointer Register */ +#define TDES_RNCR ( 276 ) /* Receive Next Counter Register */ +#define TDES_TNPR ( 280 ) /* Transmit Next Pointer Register */ +#define TDES_TNCR ( 284 ) /* Transmit Next Counter Register */ +#define TDES_PTCR ( 288 ) /* PDC Transfer Control Register */ +#define TDES_PTSR ( 292 ) /* PDC Transfer Status Register */ +/* -------- TDES_CR : (TDES Offset: 0x0) Control Register -------- */ +#define AT91C_TDES_START ( 0x1 << 0 ) /* (TDES) Starts Processing */ +#define AT91C_TDES_SWRST ( 0x1 << 8 ) /* (TDES) Software Reset */ +/* -------- TDES_MR : (TDES Offset: 0x4) Mode Register -------- */ +#define AT91C_TDES_CIPHER ( 0x1 << 0 ) /* (TDES) Processing Mode */ +#define AT91C_TDES_TDESMOD ( 0x1 << 1 ) /* (TDES) Single or Triple DES Mode */ +#define AT91C_TDES_KEYMOD ( 0x1 << 4 ) /* (TDES) Key Mode */ +#define AT91C_TDES_SMOD ( 0x3 << 8 ) /* (TDES) Start Mode */ +#define AT91C_TDES_SMOD_MANUAL ( 0x0 << 8 ) /* (TDES) Manual Mode: The START bit in register TDES_CR must be set to begin encryption or decryption. */ +#define AT91C_TDES_SMOD_AUTO ( 0x1 << 8 ) /* (TDES) Auto Mode: no action in TDES_CR is necessary (cf datasheet). */ +#define AT91C_TDES_SMOD_PDC ( 0x2 << 8 ) /* (TDES) PDC Mode (cf datasheet). */ +#define AT91C_TDES_OPMOD ( 0x3 << 12 ) /* (TDES) Operation Mode */ +#define AT91C_TDES_OPMOD_ECB ( 0x0 << 12 ) /* (TDES) ECB Electronic CodeBook mode. */ +#define AT91C_TDES_OPMOD_CBC ( 0x1 << 12 ) /* (TDES) CBC Cipher Block Chaining mode. */ +#define AT91C_TDES_OPMOD_OFB ( 0x2 << 12 ) /* (TDES) OFB Output Feedback mode. */ +#define AT91C_TDES_OPMOD_CFB ( 0x3 << 12 ) /* (TDES) CFB Cipher Feedback mode. */ +#define AT91C_TDES_LOD ( 0x1 << 15 ) /* (TDES) Last Output Data Mode */ +#define AT91C_TDES_CFBS ( 0x3 << 16 ) /* (TDES) Cipher Feedback Data Size */ +#define AT91C_TDES_CFBS_64_BIT ( 0x0 << 16 ) /* (TDES) 64-bit. */ +#define AT91C_TDES_CFBS_32_BIT ( 0x1 << 16 ) /* (TDES) 32-bit. */ +#define AT91C_TDES_CFBS_16_BIT ( 0x2 << 16 ) /* (TDES) 16-bit. */ +#define AT91C_TDES_CFBS_8_BIT ( 0x3 << 16 ) /* (TDES) 8-bit. */ +/* -------- TDES_IER : (TDES Offset: 0x10) Interrupt Enable Register -------- */ +#define AT91C_TDES_DATRDY ( 0x1 << 0 ) /* (TDES) DATRDY */ +#define AT91C_TDES_ENDRX ( 0x1 << 1 ) /* (TDES) PDC Read Buffer End */ +#define AT91C_TDES_ENDTX ( 0x1 << 2 ) /* (TDES) PDC Write Buffer End */ +#define AT91C_TDES_RXBUFF ( 0x1 << 3 ) /* (TDES) PDC Read Buffer Full */ +#define AT91C_TDES_TXBUFE ( 0x1 << 4 ) /* (TDES) PDC Write Buffer Empty */ +#define AT91C_TDES_URAD ( 0x1 << 8 ) /* (TDES) Unspecified Register Access Detection */ +/* -------- TDES_IDR : (TDES Offset: 0x14) Interrupt Disable Register -------- */ +/* -------- TDES_IMR : (TDES Offset: 0x18) Interrupt Mask Register -------- */ +/* -------- TDES_ISR : (TDES Offset: 0x1c) Interrupt Status Register -------- */ +#define AT91C_TDES_URAT ( 0x3 << 12 ) /* (TDES) Unspecified Register Access Type Status */ +#define AT91C_TDES_URAT_IN_DAT_WRITE_DATPROC ( 0x0 << 12 ) /* (TDES) Input data register written during the data processing in PDC mode. */ +#define AT91C_TDES_URAT_OUT_DAT_READ_DATPROC ( 0x1 << 12 ) /* (TDES) Output data register read during the data processing. */ +#define AT91C_TDES_URAT_MODEREG_WRITE_DATPROC ( 0x2 << 12 ) /* (TDES) Mode register written during the data processing. */ +#define AT91C_TDES_URAT_WO_REG_READ ( 0x3 << 12 ) /* (TDES) Write-only register read access. */ -// ***************************************************************************** -// REGISTER ADDRESS DEFINITION FOR AT91SAM7X256 -// ***************************************************************************** -// ========== Register definition for SYS peripheral ========== -// ========== Register definition for AIC peripheral ========== -#define AT91C_AIC_IVR (0xFFFFF100) // (AIC) IRQ Vector Register -#define AT91C_AIC_SMR (0xFFFFF000) // (AIC) Source Mode Register -#define AT91C_AIC_FVR (0xFFFFF104) // (AIC) FIQ Vector Register -#define AT91C_AIC_DCR (0xFFFFF138) // (AIC) Debug Control Register (Protect) -#define AT91C_AIC_EOICR (0xFFFFF130) // (AIC) End of Interrupt Command Register -#define AT91C_AIC_SVR (0xFFFFF080) // (AIC) Source Vector Register -#define AT91C_AIC_FFSR (0xFFFFF148) // (AIC) Fast Forcing Status Register -#define AT91C_AIC_ICCR (0xFFFFF128) // (AIC) Interrupt Clear Command Register -#define AT91C_AIC_ISR (0xFFFFF108) // (AIC) Interrupt Status Register -#define AT91C_AIC_IMR (0xFFFFF110) // (AIC) Interrupt Mask Register -#define AT91C_AIC_IPR (0xFFFFF10C) // (AIC) Interrupt Pending Register -#define AT91C_AIC_FFER (0xFFFFF140) // (AIC) Fast Forcing Enable Register -#define AT91C_AIC_IECR (0xFFFFF120) // (AIC) Interrupt Enable Command Register -#define AT91C_AIC_ISCR (0xFFFFF12C) // (AIC) Interrupt Set Command Register -#define AT91C_AIC_FFDR (0xFFFFF144) // (AIC) Fast Forcing Disable Register -#define AT91C_AIC_CISR (0xFFFFF114) // (AIC) Core Interrupt Status Register -#define AT91C_AIC_IDCR (0xFFFFF124) // (AIC) Interrupt Disable Command Register -#define AT91C_AIC_SPU (0xFFFFF134) // (AIC) Spurious Vector Register -// ========== Register definition for PDC_DBGU peripheral ========== -#define AT91C_DBGU_TCR (0xFFFFF30C) // (PDC_DBGU) Transmit Counter Register -#define AT91C_DBGU_RNPR (0xFFFFF310) // (PDC_DBGU) Receive Next Pointer Register -#define AT91C_DBGU_TNPR (0xFFFFF318) // (PDC_DBGU) Transmit Next Pointer Register -#define AT91C_DBGU_TPR (0xFFFFF308) // (PDC_DBGU) Transmit Pointer Register -#define AT91C_DBGU_RPR (0xFFFFF300) // (PDC_DBGU) Receive Pointer Register -#define AT91C_DBGU_RCR (0xFFFFF304) // (PDC_DBGU) Receive Counter Register -#define AT91C_DBGU_RNCR (0xFFFFF314) // (PDC_DBGU) Receive Next Counter Register -#define AT91C_DBGU_PTCR (0xFFFFF320) // (PDC_DBGU) PDC Transfer Control Register -#define AT91C_DBGU_PTSR (0xFFFFF324) // (PDC_DBGU) PDC Transfer Status Register -#define AT91C_DBGU_TNCR (0xFFFFF31C) // (PDC_DBGU) Transmit Next Counter Register -// ========== Register definition for DBGU peripheral ========== -#define AT91C_DBGU_EXID (0xFFFFF244) // (DBGU) Chip ID Extension Register -#define AT91C_DBGU_BRGR (0xFFFFF220) // (DBGU) Baud Rate Generator Register -#define AT91C_DBGU_IDR (0xFFFFF20C) // (DBGU) Interrupt Disable Register -#define AT91C_DBGU_CSR (0xFFFFF214) // (DBGU) Channel Status Register -#define AT91C_DBGU_CIDR (0xFFFFF240) // (DBGU) Chip ID Register -#define AT91C_DBGU_MR (0xFFFFF204) // (DBGU) Mode Register -#define AT91C_DBGU_IMR (0xFFFFF210) // (DBGU) Interrupt Mask Register -#define AT91C_DBGU_CR (0xFFFFF200) // (DBGU) Control Register -#define AT91C_DBGU_FNTR (0xFFFFF248) // (DBGU) Force NTRST Register -#define AT91C_DBGU_THR (0xFFFFF21C) // (DBGU) Transmitter Holding Register -#define AT91C_DBGU_RHR (0xFFFFF218) // (DBGU) Receiver Holding Register -#define AT91C_DBGU_IER (0xFFFFF208) // (DBGU) Interrupt Enable Register -// ========== Register definition for PIOA peripheral ========== -#define AT91C_PIOA_ODR (0xFFFFF414) // (PIOA) Output Disable Registerr -#define AT91C_PIOA_SODR (0xFFFFF430) // (PIOA) Set Output Data Register -#define AT91C_PIOA_ISR (0xFFFFF44C) // (PIOA) Interrupt Status Register -#define AT91C_PIOA_ABSR (0xFFFFF478) // (PIOA) AB Select Status Register -#define AT91C_PIOA_IER (0xFFFFF440) // (PIOA) Interrupt Enable Register -#define AT91C_PIOA_PPUDR (0xFFFFF460) // (PIOA) Pull-up Disable Register -#define AT91C_PIOA_IMR (0xFFFFF448) // (PIOA) Interrupt Mask Register -#define AT91C_PIOA_PER (0xFFFFF400) // (PIOA) PIO Enable Register -#define AT91C_PIOA_IFDR (0xFFFFF424) // (PIOA) Input Filter Disable Register -#define AT91C_PIOA_OWDR (0xFFFFF4A4) // (PIOA) Output Write Disable Register -#define AT91C_PIOA_MDSR (0xFFFFF458) // (PIOA) Multi-driver Status Register -#define AT91C_PIOA_IDR (0xFFFFF444) // (PIOA) Interrupt Disable Register -#define AT91C_PIOA_ODSR (0xFFFFF438) // (PIOA) Output Data Status Register -#define AT91C_PIOA_PPUSR (0xFFFFF468) // (PIOA) Pull-up Status Register -#define AT91C_PIOA_OWSR (0xFFFFF4A8) // (PIOA) Output Write Status Register -#define AT91C_PIOA_BSR (0xFFFFF474) // (PIOA) Select B Register -#define AT91C_PIOA_OWER (0xFFFFF4A0) // (PIOA) Output Write Enable Register -#define AT91C_PIOA_IFER (0xFFFFF420) // (PIOA) Input Filter Enable Register -#define AT91C_PIOA_PDSR (0xFFFFF43C) // (PIOA) Pin Data Status Register -#define AT91C_PIOA_PPUER (0xFFFFF464) // (PIOA) Pull-up Enable Register -#define AT91C_PIOA_OSR (0xFFFFF418) // (PIOA) Output Status Register -#define AT91C_PIOA_ASR (0xFFFFF470) // (PIOA) Select A Register -#define AT91C_PIOA_MDDR (0xFFFFF454) // (PIOA) Multi-driver Disable Register -#define AT91C_PIOA_CODR (0xFFFFF434) // (PIOA) Clear Output Data Register -#define AT91C_PIOA_MDER (0xFFFFF450) // (PIOA) Multi-driver Enable Register -#define AT91C_PIOA_PDR (0xFFFFF404) // (PIOA) PIO Disable Register -#define AT91C_PIOA_IFSR (0xFFFFF428) // (PIOA) Input Filter Status Register -#define AT91C_PIOA_OER (0xFFFFF410) // (PIOA) Output Enable Register -#define AT91C_PIOA_PSR (0xFFFFF408) // (PIOA) PIO Status Register -// ========== Register definition for PIOB peripheral ========== -#define AT91C_PIOB_OWDR (0xFFFFF6A4) // (PIOB) Output Write Disable Register -#define AT91C_PIOB_MDER (0xFFFFF650) // (PIOB) Multi-driver Enable Register -#define AT91C_PIOB_PPUSR (0xFFFFF668) // (PIOB) Pull-up Status Register -#define AT91C_PIOB_IMR (0xFFFFF648) // (PIOB) Interrupt Mask Register -#define AT91C_PIOB_ASR (0xFFFFF670) // (PIOB) Select A Register -#define AT91C_PIOB_PPUDR (0xFFFFF660) // (PIOB) Pull-up Disable Register -#define AT91C_PIOB_PSR (0xFFFFF608) // (PIOB) PIO Status Register -#define AT91C_PIOB_IER (0xFFFFF640) // (PIOB) Interrupt Enable Register -#define AT91C_PIOB_CODR (0xFFFFF634) // (PIOB) Clear Output Data Register -#define AT91C_PIOB_OWER (0xFFFFF6A0) // (PIOB) Output Write Enable Register -#define AT91C_PIOB_ABSR (0xFFFFF678) // (PIOB) AB Select Status Register -#define AT91C_PIOB_IFDR (0xFFFFF624) // (PIOB) Input Filter Disable Register -#define AT91C_PIOB_PDSR (0xFFFFF63C) // (PIOB) Pin Data Status Register -#define AT91C_PIOB_IDR (0xFFFFF644) // (PIOB) Interrupt Disable Register -#define AT91C_PIOB_OWSR (0xFFFFF6A8) // (PIOB) Output Write Status Register -#define AT91C_PIOB_PDR (0xFFFFF604) // (PIOB) PIO Disable Register -#define AT91C_PIOB_ODR (0xFFFFF614) // (PIOB) Output Disable Registerr -#define AT91C_PIOB_IFSR (0xFFFFF628) // (PIOB) Input Filter Status Register -#define AT91C_PIOB_PPUER (0xFFFFF664) // (PIOB) Pull-up Enable Register -#define AT91C_PIOB_SODR (0xFFFFF630) // (PIOB) Set Output Data Register -#define AT91C_PIOB_ISR (0xFFFFF64C) // (PIOB) Interrupt Status Register -#define AT91C_PIOB_ODSR (0xFFFFF638) // (PIOB) Output Data Status Register -#define AT91C_PIOB_OSR (0xFFFFF618) // (PIOB) Output Status Register -#define AT91C_PIOB_MDSR (0xFFFFF658) // (PIOB) Multi-driver Status Register -#define AT91C_PIOB_IFER (0xFFFFF620) // (PIOB) Input Filter Enable Register -#define AT91C_PIOB_BSR (0xFFFFF674) // (PIOB) Select B Register -#define AT91C_PIOB_MDDR (0xFFFFF654) // (PIOB) Multi-driver Disable Register -#define AT91C_PIOB_OER (0xFFFFF610) // (PIOB) Output Enable Register -#define AT91C_PIOB_PER (0xFFFFF600) // (PIOB) PIO Enable Register -// ========== Register definition for CKGR peripheral ========== -#define AT91C_CKGR_MOR (0xFFFFFC20) // (CKGR) Main Oscillator Register -#define AT91C_CKGR_PLLR (0xFFFFFC2C) // (CKGR) PLL Register -#define AT91C_CKGR_MCFR (0xFFFFFC24) // (CKGR) Main Clock Frequency Register -// ========== Register definition for PMC peripheral ========== -#define AT91C_PMC_IDR (0xFFFFFC64) // (PMC) Interrupt Disable Register -#define AT91C_PMC_MOR (0xFFFFFC20) // (PMC) Main Oscillator Register -#define AT91C_PMC_PLLR (0xFFFFFC2C) // (PMC) PLL Register -#define AT91C_PMC_PCER (0xFFFFFC10) // (PMC) Peripheral Clock Enable Register -#define AT91C_PMC_PCKR (0xFFFFFC40) // (PMC) Programmable Clock Register -#define AT91C_PMC_MCKR (0xFFFFFC30) // (PMC) Master Clock Register -#define AT91C_PMC_SCDR (0xFFFFFC04) // (PMC) System Clock Disable Register -#define AT91C_PMC_PCDR (0xFFFFFC14) // (PMC) Peripheral Clock Disable Register -#define AT91C_PMC_SCSR (0xFFFFFC08) // (PMC) System Clock Status Register -#define AT91C_PMC_PCSR (0xFFFFFC18) // (PMC) Peripheral Clock Status Register -#define AT91C_PMC_MCFR (0xFFFFFC24) // (PMC) Main Clock Frequency Register -#define AT91C_PMC_SCER (0xFFFFFC00) // (PMC) System Clock Enable Register -#define AT91C_PMC_IMR (0xFFFFFC6C) // (PMC) Interrupt Mask Register -#define AT91C_PMC_IER (0xFFFFFC60) // (PMC) Interrupt Enable Register -#define AT91C_PMC_SR (0xFFFFFC68) // (PMC) Status Register -// ========== Register definition for RSTC peripheral ========== -#define AT91C_RSTC_RCR (0xFFFFFD00) // (RSTC) Reset Control Register -#define AT91C_RSTC_RMR (0xFFFFFD08) // (RSTC) Reset Mode Register -#define AT91C_RSTC_RSR (0xFFFFFD04) // (RSTC) Reset Status Register -// ========== Register definition for RTTC peripheral ========== -#define AT91C_RTTC_RTSR (0xFFFFFD2C) // (RTTC) Real-time Status Register -#define AT91C_RTTC_RTMR (0xFFFFFD20) // (RTTC) Real-time Mode Register -#define AT91C_RTTC_RTVR (0xFFFFFD28) // (RTTC) Real-time Value Register -#define AT91C_RTTC_RTAR (0xFFFFFD24) // (RTTC) Real-time Alarm Register -// ========== Register definition for PITC peripheral ========== -#define AT91C_PITC_PIVR (0xFFFFFD38) // (PITC) Period Interval Value Register -#define AT91C_PITC_PISR (0xFFFFFD34) // (PITC) Period Interval Status Register -#define AT91C_PITC_PIIR (0xFFFFFD3C) // (PITC) Period Interval Image Register -#define AT91C_PITC_PIMR (0xFFFFFD30) // (PITC) Period Interval Mode Register -// ========== Register definition for WDTC peripheral ========== -#define AT91C_WDTC_WDCR (0xFFFFFD40) // (WDTC) Watchdog Control Register -#define AT91C_WDTC_WDSR (0xFFFFFD48) // (WDTC) Watchdog Status Register -#define AT91C_WDTC_WDMR (0xFFFFFD44) // (WDTC) Watchdog Mode Register -// ========== Register definition for VREG peripheral ========== -#define AT91C_VREG_MR (0xFFFFFD60) // (VREG) Voltage Regulator Mode Register -// ========== Register definition for MC peripheral ========== -#define AT91C_MC_ASR (0xFFFFFF04) // (MC) MC Abort Status Register -#define AT91C_MC_RCR (0xFFFFFF00) // (MC) MC Remap Control Register -#define AT91C_MC_FCR (0xFFFFFF64) // (MC) MC Flash Command Register -#define AT91C_MC_AASR (0xFFFFFF08) // (MC) MC Abort Address Status Register -#define AT91C_MC_FSR (0xFFFFFF68) // (MC) MC Flash Status Register -#define AT91C_MC_FMR (0xFFFFFF60) // (MC) MC Flash Mode Register -// ========== Register definition for PDC_SPI1 peripheral ========== -#define AT91C_SPI1_PTCR (0xFFFE4120) // (PDC_SPI1) PDC Transfer Control Register -#define AT91C_SPI1_RPR (0xFFFE4100) // (PDC_SPI1) Receive Pointer Register -#define AT91C_SPI1_TNCR (0xFFFE411C) // (PDC_SPI1) Transmit Next Counter Register -#define AT91C_SPI1_TPR (0xFFFE4108) // (PDC_SPI1) Transmit Pointer Register -#define AT91C_SPI1_TNPR (0xFFFE4118) // (PDC_SPI1) Transmit Next Pointer Register -#define AT91C_SPI1_TCR (0xFFFE410C) // (PDC_SPI1) Transmit Counter Register -#define AT91C_SPI1_RCR (0xFFFE4104) // (PDC_SPI1) Receive Counter Register -#define AT91C_SPI1_RNPR (0xFFFE4110) // (PDC_SPI1) Receive Next Pointer Register -#define AT91C_SPI1_RNCR (0xFFFE4114) // (PDC_SPI1) Receive Next Counter Register -#define AT91C_SPI1_PTSR (0xFFFE4124) // (PDC_SPI1) PDC Transfer Status Register -// ========== Register definition for SPI1 peripheral ========== -#define AT91C_SPI1_IMR (0xFFFE401C) // (SPI1) Interrupt Mask Register -#define AT91C_SPI1_IER (0xFFFE4014) // (SPI1) Interrupt Enable Register -#define AT91C_SPI1_MR (0xFFFE4004) // (SPI1) Mode Register -#define AT91C_SPI1_RDR (0xFFFE4008) // (SPI1) Receive Data Register -#define AT91C_SPI1_IDR (0xFFFE4018) // (SPI1) Interrupt Disable Register -#define AT91C_SPI1_SR (0xFFFE4010) // (SPI1) Status Register -#define AT91C_SPI1_TDR (0xFFFE400C) // (SPI1) Transmit Data Register -#define AT91C_SPI1_CR (0xFFFE4000) // (SPI1) Control Register -#define AT91C_SPI1_CSR (0xFFFE4030) // (SPI1) Chip Select Register -// ========== Register definition for PDC_SPI0 peripheral ========== -#define AT91C_SPI0_PTCR (0xFFFE0120) // (PDC_SPI0) PDC Transfer Control Register -#define AT91C_SPI0_TPR (0xFFFE0108) // (PDC_SPI0) Transmit Pointer Register -#define AT91C_SPI0_TCR (0xFFFE010C) // (PDC_SPI0) Transmit Counter Register -#define AT91C_SPI0_RCR (0xFFFE0104) // (PDC_SPI0) Receive Counter Register -#define AT91C_SPI0_PTSR (0xFFFE0124) // (PDC_SPI0) PDC Transfer Status Register -#define AT91C_SPI0_RNPR (0xFFFE0110) // (PDC_SPI0) Receive Next Pointer Register -#define AT91C_SPI0_RPR (0xFFFE0100) // (PDC_SPI0) Receive Pointer Register -#define AT91C_SPI0_TNCR (0xFFFE011C) // (PDC_SPI0) Transmit Next Counter Register -#define AT91C_SPI0_RNCR (0xFFFE0114) // (PDC_SPI0) Receive Next Counter Register -#define AT91C_SPI0_TNPR (0xFFFE0118) // (PDC_SPI0) Transmit Next Pointer Register -// ========== Register definition for SPI0 peripheral ========== -#define AT91C_SPI0_IER (0xFFFE0014) // (SPI0) Interrupt Enable Register -#define AT91C_SPI0_SR (0xFFFE0010) // (SPI0) Status Register -#define AT91C_SPI0_IDR (0xFFFE0018) // (SPI0) Interrupt Disable Register -#define AT91C_SPI0_CR (0xFFFE0000) // (SPI0) Control Register -#define AT91C_SPI0_MR (0xFFFE0004) // (SPI0) Mode Register -#define AT91C_SPI0_IMR (0xFFFE001C) // (SPI0) Interrupt Mask Register -#define AT91C_SPI0_TDR (0xFFFE000C) // (SPI0) Transmit Data Register -#define AT91C_SPI0_RDR (0xFFFE0008) // (SPI0) Receive Data Register -#define AT91C_SPI0_CSR (0xFFFE0030) // (SPI0) Chip Select Register -// ========== Register definition for PDC_US1 peripheral ========== -#define AT91C_US1_RNCR (0xFFFC4114) // (PDC_US1) Receive Next Counter Register -#define AT91C_US1_PTCR (0xFFFC4120) // (PDC_US1) PDC Transfer Control Register -#define AT91C_US1_TCR (0xFFFC410C) // (PDC_US1) Transmit Counter Register -#define AT91C_US1_PTSR (0xFFFC4124) // (PDC_US1) PDC Transfer Status Register -#define AT91C_US1_TNPR (0xFFFC4118) // (PDC_US1) Transmit Next Pointer Register -#define AT91C_US1_RCR (0xFFFC4104) // (PDC_US1) Receive Counter Register -#define AT91C_US1_RNPR (0xFFFC4110) // (PDC_US1) Receive Next Pointer Register -#define AT91C_US1_RPR (0xFFFC4100) // (PDC_US1) Receive Pointer Register -#define AT91C_US1_TNCR (0xFFFC411C) // (PDC_US1) Transmit Next Counter Register -#define AT91C_US1_TPR (0xFFFC4108) // (PDC_US1) Transmit Pointer Register -// ========== Register definition for US1 peripheral ========== -#define AT91C_US1_IF (0xFFFC404C) // (US1) IRDA_FILTER Register -#define AT91C_US1_NER (0xFFFC4044) // (US1) Nb Errors Register -#define AT91C_US1_RTOR (0xFFFC4024) // (US1) Receiver Time-out Register -#define AT91C_US1_CSR (0xFFFC4014) // (US1) Channel Status Register -#define AT91C_US1_IDR (0xFFFC400C) // (US1) Interrupt Disable Register -#define AT91C_US1_IER (0xFFFC4008) // (US1) Interrupt Enable Register -#define AT91C_US1_THR (0xFFFC401C) // (US1) Transmitter Holding Register -#define AT91C_US1_TTGR (0xFFFC4028) // (US1) Transmitter Time-guard Register -#define AT91C_US1_RHR (0xFFFC4018) // (US1) Receiver Holding Register -#define AT91C_US1_BRGR (0xFFFC4020) // (US1) Baud Rate Generator Register -#define AT91C_US1_IMR (0xFFFC4010) // (US1) Interrupt Mask Register -#define AT91C_US1_FIDI (0xFFFC4040) // (US1) FI_DI_Ratio Register -#define AT91C_US1_CR (0xFFFC4000) // (US1) Control Register -#define AT91C_US1_MR (0xFFFC4004) // (US1) Mode Register -// ========== Register definition for PDC_US0 peripheral ========== -#define AT91C_US0_TNPR (0xFFFC0118) // (PDC_US0) Transmit Next Pointer Register -#define AT91C_US0_RNPR (0xFFFC0110) // (PDC_US0) Receive Next Pointer Register -#define AT91C_US0_TCR (0xFFFC010C) // (PDC_US0) Transmit Counter Register -#define AT91C_US0_PTCR (0xFFFC0120) // (PDC_US0) PDC Transfer Control Register -#define AT91C_US0_PTSR (0xFFFC0124) // (PDC_US0) PDC Transfer Status Register -#define AT91C_US0_TNCR (0xFFFC011C) // (PDC_US0) Transmit Next Counter Register -#define AT91C_US0_TPR (0xFFFC0108) // (PDC_US0) Transmit Pointer Register -#define AT91C_US0_RCR (0xFFFC0104) // (PDC_US0) Receive Counter Register -#define AT91C_US0_RPR (0xFFFC0100) // (PDC_US0) Receive Pointer Register -#define AT91C_US0_RNCR (0xFFFC0114) // (PDC_US0) Receive Next Counter Register -// ========== Register definition for US0 peripheral ========== -#define AT91C_US0_BRGR (0xFFFC0020) // (US0) Baud Rate Generator Register -#define AT91C_US0_NER (0xFFFC0044) // (US0) Nb Errors Register -#define AT91C_US0_CR (0xFFFC0000) // (US0) Control Register -#define AT91C_US0_IMR (0xFFFC0010) // (US0) Interrupt Mask Register -#define AT91C_US0_FIDI (0xFFFC0040) // (US0) FI_DI_Ratio Register -#define AT91C_US0_TTGR (0xFFFC0028) // (US0) Transmitter Time-guard Register -#define AT91C_US0_MR (0xFFFC0004) // (US0) Mode Register -#define AT91C_US0_RTOR (0xFFFC0024) // (US0) Receiver Time-out Register -#define AT91C_US0_CSR (0xFFFC0014) // (US0) Channel Status Register -#define AT91C_US0_RHR (0xFFFC0018) // (US0) Receiver Holding Register -#define AT91C_US0_IDR (0xFFFC000C) // (US0) Interrupt Disable Register -#define AT91C_US0_THR (0xFFFC001C) // (US0) Transmitter Holding Register -#define AT91C_US0_IF (0xFFFC004C) // (US0) IRDA_FILTER Register -#define AT91C_US0_IER (0xFFFC0008) // (US0) Interrupt Enable Register -// ========== Register definition for PDC_SSC peripheral ========== -#define AT91C_SSC_TNCR (0xFFFD411C) // (PDC_SSC) Transmit Next Counter Register -#define AT91C_SSC_RPR (0xFFFD4100) // (PDC_SSC) Receive Pointer Register -#define AT91C_SSC_RNCR (0xFFFD4114) // (PDC_SSC) Receive Next Counter Register -#define AT91C_SSC_TPR (0xFFFD4108) // (PDC_SSC) Transmit Pointer Register -#define AT91C_SSC_PTCR (0xFFFD4120) // (PDC_SSC) PDC Transfer Control Register -#define AT91C_SSC_TCR (0xFFFD410C) // (PDC_SSC) Transmit Counter Register -#define AT91C_SSC_RCR (0xFFFD4104) // (PDC_SSC) Receive Counter Register -#define AT91C_SSC_RNPR (0xFFFD4110) // (PDC_SSC) Receive Next Pointer Register -#define AT91C_SSC_TNPR (0xFFFD4118) // (PDC_SSC) Transmit Next Pointer Register -#define AT91C_SSC_PTSR (0xFFFD4124) // (PDC_SSC) PDC Transfer Status Register -// ========== Register definition for SSC peripheral ========== -#define AT91C_SSC_RHR (0xFFFD4020) // (SSC) Receive Holding Register -#define AT91C_SSC_RSHR (0xFFFD4030) // (SSC) Receive Sync Holding Register -#define AT91C_SSC_TFMR (0xFFFD401C) // (SSC) Transmit Frame Mode Register -#define AT91C_SSC_IDR (0xFFFD4048) // (SSC) Interrupt Disable Register -#define AT91C_SSC_THR (0xFFFD4024) // (SSC) Transmit Holding Register -#define AT91C_SSC_RCMR (0xFFFD4010) // (SSC) Receive Clock ModeRegister -#define AT91C_SSC_IER (0xFFFD4044) // (SSC) Interrupt Enable Register -#define AT91C_SSC_TSHR (0xFFFD4034) // (SSC) Transmit Sync Holding Register -#define AT91C_SSC_SR (0xFFFD4040) // (SSC) Status Register -#define AT91C_SSC_CMR (0xFFFD4004) // (SSC) Clock Mode Register -#define AT91C_SSC_TCMR (0xFFFD4018) // (SSC) Transmit Clock Mode Register -#define AT91C_SSC_CR (0xFFFD4000) // (SSC) Control Register -#define AT91C_SSC_IMR (0xFFFD404C) // (SSC) Interrupt Mask Register -#define AT91C_SSC_RFMR (0xFFFD4014) // (SSC) Receive Frame Mode Register -// ========== Register definition for TWI peripheral ========== -#define AT91C_TWI_IER (0xFFFB8024) // (TWI) Interrupt Enable Register -#define AT91C_TWI_CR (0xFFFB8000) // (TWI) Control Register -#define AT91C_TWI_SR (0xFFFB8020) // (TWI) Status Register -#define AT91C_TWI_IMR (0xFFFB802C) // (TWI) Interrupt Mask Register -#define AT91C_TWI_THR (0xFFFB8034) // (TWI) Transmit Holding Register -#define AT91C_TWI_IDR (0xFFFB8028) // (TWI) Interrupt Disable Register -#define AT91C_TWI_IADR (0xFFFB800C) // (TWI) Internal Address Register -#define AT91C_TWI_MMR (0xFFFB8004) // (TWI) Master Mode Register -#define AT91C_TWI_CWGR (0xFFFB8010) // (TWI) Clock Waveform Generator Register -#define AT91C_TWI_RHR (0xFFFB8030) // (TWI) Receive Holding Register -// ========== Register definition for PWMC_CH3 peripheral ========== -#define AT91C_PWMC_CH3_CUPDR (0xFFFCC270) // (PWMC_CH3) Channel Update Register -#define AT91C_PWMC_CH3_Reserved (0xFFFCC274) // (PWMC_CH3) Reserved -#define AT91C_PWMC_CH3_CPRDR (0xFFFCC268) // (PWMC_CH3) Channel Period Register -#define AT91C_PWMC_CH3_CDTYR (0xFFFCC264) // (PWMC_CH3) Channel Duty Cycle Register -#define AT91C_PWMC_CH3_CCNTR (0xFFFCC26C) // (PWMC_CH3) Channel Counter Register -#define AT91C_PWMC_CH3_CMR (0xFFFCC260) // (PWMC_CH3) Channel Mode Register -// ========== Register definition for PWMC_CH2 peripheral ========== -#define AT91C_PWMC_CH2_Reserved (0xFFFCC254) // (PWMC_CH2) Reserved -#define AT91C_PWMC_CH2_CMR (0xFFFCC240) // (PWMC_CH2) Channel Mode Register -#define AT91C_PWMC_CH2_CCNTR (0xFFFCC24C) // (PWMC_CH2) Channel Counter Register -#define AT91C_PWMC_CH2_CPRDR (0xFFFCC248) // (PWMC_CH2) Channel Period Register -#define AT91C_PWMC_CH2_CUPDR (0xFFFCC250) // (PWMC_CH2) Channel Update Register -#define AT91C_PWMC_CH2_CDTYR (0xFFFCC244) // (PWMC_CH2) Channel Duty Cycle Register -// ========== Register definition for PWMC_CH1 peripheral ========== -#define AT91C_PWMC_CH1_Reserved (0xFFFCC234) // (PWMC_CH1) Reserved -#define AT91C_PWMC_CH1_CUPDR (0xFFFCC230) // (PWMC_CH1) Channel Update Register -#define AT91C_PWMC_CH1_CPRDR (0xFFFCC228) // (PWMC_CH1) Channel Period Register -#define AT91C_PWMC_CH1_CCNTR (0xFFFCC22C) // (PWMC_CH1) Channel Counter Register -#define AT91C_PWMC_CH1_CDTYR (0xFFFCC224) // (PWMC_CH1) Channel Duty Cycle Register -#define AT91C_PWMC_CH1_CMR (0xFFFCC220) // (PWMC_CH1) Channel Mode Register -// ========== Register definition for PWMC_CH0 peripheral ========== -#define AT91C_PWMC_CH0_Reserved (0xFFFCC214) // (PWMC_CH0) Reserved -#define AT91C_PWMC_CH0_CPRDR (0xFFFCC208) // (PWMC_CH0) Channel Period Register -#define AT91C_PWMC_CH0_CDTYR (0xFFFCC204) // (PWMC_CH0) Channel Duty Cycle Register -#define AT91C_PWMC_CH0_CMR (0xFFFCC200) // (PWMC_CH0) Channel Mode Register -#define AT91C_PWMC_CH0_CUPDR (0xFFFCC210) // (PWMC_CH0) Channel Update Register -#define AT91C_PWMC_CH0_CCNTR (0xFFFCC20C) // (PWMC_CH0) Channel Counter Register -// ========== Register definition for PWMC peripheral ========== -#define AT91C_PWMC_IDR (0xFFFCC014) // (PWMC) PWMC Interrupt Disable Register -#define AT91C_PWMC_DIS (0xFFFCC008) // (PWMC) PWMC Disable Register -#define AT91C_PWMC_IER (0xFFFCC010) // (PWMC) PWMC Interrupt Enable Register -#define AT91C_PWMC_VR (0xFFFCC0FC) // (PWMC) PWMC Version Register -#define AT91C_PWMC_ISR (0xFFFCC01C) // (PWMC) PWMC Interrupt Status Register -#define AT91C_PWMC_SR (0xFFFCC00C) // (PWMC) PWMC Status Register -#define AT91C_PWMC_IMR (0xFFFCC018) // (PWMC) PWMC Interrupt Mask Register -#define AT91C_PWMC_MR (0xFFFCC000) // (PWMC) PWMC Mode Register -#define AT91C_PWMC_ENA (0xFFFCC004) // (PWMC) PWMC Enable Register -// ========== Register definition for UDP peripheral ========== -#define AT91C_UDP_IMR (0xFFFB0018) // (UDP) Interrupt Mask Register -#define AT91C_UDP_FADDR (0xFFFB0008) // (UDP) Function Address Register -#define AT91C_UDP_NUM (0xFFFB0000) // (UDP) Frame Number Register -#define AT91C_UDP_FDR (0xFFFB0050) // (UDP) Endpoint FIFO Data Register -#define AT91C_UDP_ISR (0xFFFB001C) // (UDP) Interrupt Status Register -#define AT91C_UDP_CSR (0xFFFB0030) // (UDP) Endpoint Control and Status Register -#define AT91C_UDP_IDR (0xFFFB0014) // (UDP) Interrupt Disable Register -#define AT91C_UDP_ICR (0xFFFB0020) // (UDP) Interrupt Clear Register -#define AT91C_UDP_RSTEP (0xFFFB0028) // (UDP) Reset Endpoint Register -#define AT91C_UDP_TXVC (0xFFFB0074) // (UDP) Transceiver Control Register -#define AT91C_UDP_GLBSTATE (0xFFFB0004) // (UDP) Global State Register -#define AT91C_UDP_IER (0xFFFB0010) // (UDP) Interrupt Enable Register -// ========== Register definition for TC0 peripheral ========== -#define AT91C_TC0_SR (0xFFFA0020) // (TC0) Status Register -#define AT91C_TC0_RC (0xFFFA001C) // (TC0) Register C -#define AT91C_TC0_RB (0xFFFA0018) // (TC0) Register B -#define AT91C_TC0_CCR (0xFFFA0000) // (TC0) Channel Control Register -#define AT91C_TC0_CMR (0xFFFA0004) // (TC0) Channel Mode Register (Capture Mode / Waveform Mode) -#define AT91C_TC0_IER (0xFFFA0024) // (TC0) Interrupt Enable Register -#define AT91C_TC0_RA (0xFFFA0014) // (TC0) Register A -#define AT91C_TC0_IDR (0xFFFA0028) // (TC0) Interrupt Disable Register -#define AT91C_TC0_CV (0xFFFA0010) // (TC0) Counter Value -#define AT91C_TC0_IMR (0xFFFA002C) // (TC0) Interrupt Mask Register -// ========== Register definition for TC1 peripheral ========== -#define AT91C_TC1_RB (0xFFFA0058) // (TC1) Register B -#define AT91C_TC1_CCR (0xFFFA0040) // (TC1) Channel Control Register -#define AT91C_TC1_IER (0xFFFA0064) // (TC1) Interrupt Enable Register -#define AT91C_TC1_IDR (0xFFFA0068) // (TC1) Interrupt Disable Register -#define AT91C_TC1_SR (0xFFFA0060) // (TC1) Status Register -#define AT91C_TC1_CMR (0xFFFA0044) // (TC1) Channel Mode Register (Capture Mode / Waveform Mode) -#define AT91C_TC1_RA (0xFFFA0054) // (TC1) Register A -#define AT91C_TC1_RC (0xFFFA005C) // (TC1) Register C -#define AT91C_TC1_IMR (0xFFFA006C) // (TC1) Interrupt Mask Register -#define AT91C_TC1_CV (0xFFFA0050) // (TC1) Counter Value -// ========== Register definition for TC2 peripheral ========== -#define AT91C_TC2_CMR (0xFFFA0084) // (TC2) Channel Mode Register (Capture Mode / Waveform Mode) -#define AT91C_TC2_CCR (0xFFFA0080) // (TC2) Channel Control Register -#define AT91C_TC2_CV (0xFFFA0090) // (TC2) Counter Value -#define AT91C_TC2_RA (0xFFFA0094) // (TC2) Register A -#define AT91C_TC2_RB (0xFFFA0098) // (TC2) Register B -#define AT91C_TC2_IDR (0xFFFA00A8) // (TC2) Interrupt Disable Register -#define AT91C_TC2_IMR (0xFFFA00AC) // (TC2) Interrupt Mask Register -#define AT91C_TC2_RC (0xFFFA009C) // (TC2) Register C -#define AT91C_TC2_IER (0xFFFA00A4) // (TC2) Interrupt Enable Register -#define AT91C_TC2_SR (0xFFFA00A0) // (TC2) Status Register -// ========== Register definition for TCB peripheral ========== -#define AT91C_TCB_BMR (0xFFFA00C4) // (TCB) TC Block Mode Register -#define AT91C_TCB_BCR (0xFFFA00C0) // (TCB) TC Block Control Register -// ========== Register definition for CAN_MB0 peripheral ========== -#define AT91C_CAN_MB0_MDL (0xFFFD0214) // (CAN_MB0) MailBox Data Low Register -#define AT91C_CAN_MB0_MAM (0xFFFD0204) // (CAN_MB0) MailBox Acceptance Mask Register -#define AT91C_CAN_MB0_MCR (0xFFFD021C) // (CAN_MB0) MailBox Control Register -#define AT91C_CAN_MB0_MID (0xFFFD0208) // (CAN_MB0) MailBox ID Register -#define AT91C_CAN_MB0_MSR (0xFFFD0210) // (CAN_MB0) MailBox Status Register -#define AT91C_CAN_MB0_MFID (0xFFFD020C) // (CAN_MB0) MailBox Family ID Register -#define AT91C_CAN_MB0_MDH (0xFFFD0218) // (CAN_MB0) MailBox Data High Register -#define AT91C_CAN_MB0_MMR (0xFFFD0200) // (CAN_MB0) MailBox Mode Register -// ========== Register definition for CAN_MB1 peripheral ========== -#define AT91C_CAN_MB1_MDL (0xFFFD0234) // (CAN_MB1) MailBox Data Low Register -#define AT91C_CAN_MB1_MID (0xFFFD0228) // (CAN_MB1) MailBox ID Register -#define AT91C_CAN_MB1_MMR (0xFFFD0220) // (CAN_MB1) MailBox Mode Register -#define AT91C_CAN_MB1_MSR (0xFFFD0230) // (CAN_MB1) MailBox Status Register -#define AT91C_CAN_MB1_MAM (0xFFFD0224) // (CAN_MB1) MailBox Acceptance Mask Register -#define AT91C_CAN_MB1_MDH (0xFFFD0238) // (CAN_MB1) MailBox Data High Register -#define AT91C_CAN_MB1_MCR (0xFFFD023C) // (CAN_MB1) MailBox Control Register -#define AT91C_CAN_MB1_MFID (0xFFFD022C) // (CAN_MB1) MailBox Family ID Register -// ========== Register definition for CAN_MB2 peripheral ========== -#define AT91C_CAN_MB2_MCR (0xFFFD025C) // (CAN_MB2) MailBox Control Register -#define AT91C_CAN_MB2_MDH (0xFFFD0258) // (CAN_MB2) MailBox Data High Register -#define AT91C_CAN_MB2_MID (0xFFFD0248) // (CAN_MB2) MailBox ID Register -#define AT91C_CAN_MB2_MDL (0xFFFD0254) // (CAN_MB2) MailBox Data Low Register -#define AT91C_CAN_MB2_MMR (0xFFFD0240) // (CAN_MB2) MailBox Mode Register -#define AT91C_CAN_MB2_MAM (0xFFFD0244) // (CAN_MB2) MailBox Acceptance Mask Register -#define AT91C_CAN_MB2_MFID (0xFFFD024C) // (CAN_MB2) MailBox Family ID Register -#define AT91C_CAN_MB2_MSR (0xFFFD0250) // (CAN_MB2) MailBox Status Register -// ========== Register definition for CAN_MB3 peripheral ========== -#define AT91C_CAN_MB3_MFID (0xFFFD026C) // (CAN_MB3) MailBox Family ID Register -#define AT91C_CAN_MB3_MAM (0xFFFD0264) // (CAN_MB3) MailBox Acceptance Mask Register -#define AT91C_CAN_MB3_MID (0xFFFD0268) // (CAN_MB3) MailBox ID Register -#define AT91C_CAN_MB3_MCR (0xFFFD027C) // (CAN_MB3) MailBox Control Register -#define AT91C_CAN_MB3_MMR (0xFFFD0260) // (CAN_MB3) MailBox Mode Register -#define AT91C_CAN_MB3_MSR (0xFFFD0270) // (CAN_MB3) MailBox Status Register -#define AT91C_CAN_MB3_MDL (0xFFFD0274) // (CAN_MB3) MailBox Data Low Register -#define AT91C_CAN_MB3_MDH (0xFFFD0278) // (CAN_MB3) MailBox Data High Register -// ========== Register definition for CAN_MB4 peripheral ========== -#define AT91C_CAN_MB4_MID (0xFFFD0288) // (CAN_MB4) MailBox ID Register -#define AT91C_CAN_MB4_MMR (0xFFFD0280) // (CAN_MB4) MailBox Mode Register -#define AT91C_CAN_MB4_MDH (0xFFFD0298) // (CAN_MB4) MailBox Data High Register -#define AT91C_CAN_MB4_MFID (0xFFFD028C) // (CAN_MB4) MailBox Family ID Register -#define AT91C_CAN_MB4_MSR (0xFFFD0290) // (CAN_MB4) MailBox Status Register -#define AT91C_CAN_MB4_MCR (0xFFFD029C) // (CAN_MB4) MailBox Control Register -#define AT91C_CAN_MB4_MDL (0xFFFD0294) // (CAN_MB4) MailBox Data Low Register -#define AT91C_CAN_MB4_MAM (0xFFFD0284) // (CAN_MB4) MailBox Acceptance Mask Register -// ========== Register definition for CAN_MB5 peripheral ========== -#define AT91C_CAN_MB5_MSR (0xFFFD02B0) // (CAN_MB5) MailBox Status Register -#define AT91C_CAN_MB5_MCR (0xFFFD02BC) // (CAN_MB5) MailBox Control Register -#define AT91C_CAN_MB5_MFID (0xFFFD02AC) // (CAN_MB5) MailBox Family ID Register -#define AT91C_CAN_MB5_MDH (0xFFFD02B8) // (CAN_MB5) MailBox Data High Register -#define AT91C_CAN_MB5_MID (0xFFFD02A8) // (CAN_MB5) MailBox ID Register -#define AT91C_CAN_MB5_MMR (0xFFFD02A0) // (CAN_MB5) MailBox Mode Register -#define AT91C_CAN_MB5_MDL (0xFFFD02B4) // (CAN_MB5) MailBox Data Low Register -#define AT91C_CAN_MB5_MAM (0xFFFD02A4) // (CAN_MB5) MailBox Acceptance Mask Register -// ========== Register definition for CAN_MB6 peripheral ========== -#define AT91C_CAN_MB6_MFID (0xFFFD02CC) // (CAN_MB6) MailBox Family ID Register -#define AT91C_CAN_MB6_MID (0xFFFD02C8) // (CAN_MB6) MailBox ID Register -#define AT91C_CAN_MB6_MAM (0xFFFD02C4) // (CAN_MB6) MailBox Acceptance Mask Register -#define AT91C_CAN_MB6_MSR (0xFFFD02D0) // (CAN_MB6) MailBox Status Register -#define AT91C_CAN_MB6_MDL (0xFFFD02D4) // (CAN_MB6) MailBox Data Low Register -#define AT91C_CAN_MB6_MCR (0xFFFD02DC) // (CAN_MB6) MailBox Control Register -#define AT91C_CAN_MB6_MDH (0xFFFD02D8) // (CAN_MB6) MailBox Data High Register -#define AT91C_CAN_MB6_MMR (0xFFFD02C0) // (CAN_MB6) MailBox Mode Register -// ========== Register definition for CAN_MB7 peripheral ========== -#define AT91C_CAN_MB7_MCR (0xFFFD02FC) // (CAN_MB7) MailBox Control Register -#define AT91C_CAN_MB7_MDH (0xFFFD02F8) // (CAN_MB7) MailBox Data High Register -#define AT91C_CAN_MB7_MFID (0xFFFD02EC) // (CAN_MB7) MailBox Family ID Register -#define AT91C_CAN_MB7_MDL (0xFFFD02F4) // (CAN_MB7) MailBox Data Low Register -#define AT91C_CAN_MB7_MID (0xFFFD02E8) // (CAN_MB7) MailBox ID Register -#define AT91C_CAN_MB7_MMR (0xFFFD02E0) // (CAN_MB7) MailBox Mode Register -#define AT91C_CAN_MB7_MAM (0xFFFD02E4) // (CAN_MB7) MailBox Acceptance Mask Register -#define AT91C_CAN_MB7_MSR (0xFFFD02F0) // (CAN_MB7) MailBox Status Register -// ========== Register definition for CAN peripheral ========== -#define AT91C_CAN_TCR (0xFFFD0024) // (CAN) Transfer Command Register -#define AT91C_CAN_IMR (0xFFFD000C) // (CAN) Interrupt Mask Register -#define AT91C_CAN_IER (0xFFFD0004) // (CAN) Interrupt Enable Register -#define AT91C_CAN_ECR (0xFFFD0020) // (CAN) Error Counter Register -#define AT91C_CAN_TIMESTP (0xFFFD001C) // (CAN) Time Stamp Register -#define AT91C_CAN_MR (0xFFFD0000) // (CAN) Mode Register -#define AT91C_CAN_IDR (0xFFFD0008) // (CAN) Interrupt Disable Register -#define AT91C_CAN_ACR (0xFFFD0028) // (CAN) Abort Command Register -#define AT91C_CAN_TIM (0xFFFD0018) // (CAN) Timer Register -#define AT91C_CAN_SR (0xFFFD0010) // (CAN) Status Register -#define AT91C_CAN_BR (0xFFFD0014) // (CAN) Baudrate Register -#define AT91C_CAN_VR (0xFFFD00FC) // (CAN) Version Register -// ========== Register definition for EMAC peripheral ========== -#define AT91C_EMAC_ISR (0xFFFDC024) // (EMAC) Interrupt Status Register -#define AT91C_EMAC_SA4H (0xFFFDC0B4) // (EMAC) Specific Address 4 Top, Last 2 bytes -#define AT91C_EMAC_SA1L (0xFFFDC098) // (EMAC) Specific Address 1 Bottom, First 4 bytes -#define AT91C_EMAC_ELE (0xFFFDC078) // (EMAC) Excessive Length Errors Register -#define AT91C_EMAC_LCOL (0xFFFDC05C) // (EMAC) Late Collision Register -#define AT91C_EMAC_RLE (0xFFFDC088) // (EMAC) Receive Length Field Mismatch Register -#define AT91C_EMAC_WOL (0xFFFDC0C4) // (EMAC) Wake On LAN Register -#define AT91C_EMAC_DTF (0xFFFDC058) // (EMAC) Deferred Transmission Frame Register -#define AT91C_EMAC_TUND (0xFFFDC064) // (EMAC) Transmit Underrun Error Register -#define AT91C_EMAC_NCR (0xFFFDC000) // (EMAC) Network Control Register -#define AT91C_EMAC_SA4L (0xFFFDC0B0) // (EMAC) Specific Address 4 Bottom, First 4 bytes -#define AT91C_EMAC_RSR (0xFFFDC020) // (EMAC) Receive Status Register -#define AT91C_EMAC_SA3L (0xFFFDC0A8) // (EMAC) Specific Address 3 Bottom, First 4 bytes -#define AT91C_EMAC_TSR (0xFFFDC014) // (EMAC) Transmit Status Register -#define AT91C_EMAC_IDR (0xFFFDC02C) // (EMAC) Interrupt Disable Register -#define AT91C_EMAC_RSE (0xFFFDC074) // (EMAC) Receive Symbol Errors Register -#define AT91C_EMAC_ECOL (0xFFFDC060) // (EMAC) Excessive Collision Register -#define AT91C_EMAC_TID (0xFFFDC0B8) // (EMAC) Type ID Checking Register -#define AT91C_EMAC_HRB (0xFFFDC090) // (EMAC) Hash Address Bottom[31:0] -#define AT91C_EMAC_TBQP (0xFFFDC01C) // (EMAC) Transmit Buffer Queue Pointer -#define AT91C_EMAC_USRIO (0xFFFDC0C0) // (EMAC) USER Input/Output Register -#define AT91C_EMAC_PTR (0xFFFDC038) // (EMAC) Pause Time Register -#define AT91C_EMAC_SA2H (0xFFFDC0A4) // (EMAC) Specific Address 2 Top, Last 2 bytes -#define AT91C_EMAC_ROV (0xFFFDC070) // (EMAC) Receive Overrun Errors Register -#define AT91C_EMAC_ALE (0xFFFDC054) // (EMAC) Alignment Error Register -#define AT91C_EMAC_RJA (0xFFFDC07C) // (EMAC) Receive Jabbers Register -#define AT91C_EMAC_RBQP (0xFFFDC018) // (EMAC) Receive Buffer Queue Pointer -#define AT91C_EMAC_TPF (0xFFFDC08C) // (EMAC) Transmitted Pause Frames Register -#define AT91C_EMAC_NCFGR (0xFFFDC004) // (EMAC) Network Configuration Register -#define AT91C_EMAC_HRT (0xFFFDC094) // (EMAC) Hash Address Top[63:32] -#define AT91C_EMAC_USF (0xFFFDC080) // (EMAC) Undersize Frames Register -#define AT91C_EMAC_FCSE (0xFFFDC050) // (EMAC) Frame Check Sequence Error Register -#define AT91C_EMAC_TPQ (0xFFFDC0BC) // (EMAC) Transmit Pause Quantum Register -#define AT91C_EMAC_MAN (0xFFFDC034) // (EMAC) PHY Maintenance Register -#define AT91C_EMAC_FTO (0xFFFDC040) // (EMAC) Frames Transmitted OK Register -#define AT91C_EMAC_REV (0xFFFDC0FC) // (EMAC) Revision Register -#define AT91C_EMAC_IMR (0xFFFDC030) // (EMAC) Interrupt Mask Register -#define AT91C_EMAC_SCF (0xFFFDC044) // (EMAC) Single Collision Frame Register -#define AT91C_EMAC_PFR (0xFFFDC03C) // (EMAC) Pause Frames received Register -#define AT91C_EMAC_MCF (0xFFFDC048) // (EMAC) Multiple Collision Frame Register -#define AT91C_EMAC_NSR (0xFFFDC008) // (EMAC) Network Status Register -#define AT91C_EMAC_SA2L (0xFFFDC0A0) // (EMAC) Specific Address 2 Bottom, First 4 bytes -#define AT91C_EMAC_FRO (0xFFFDC04C) // (EMAC) Frames Received OK Register -#define AT91C_EMAC_IER (0xFFFDC028) // (EMAC) Interrupt Enable Register -#define AT91C_EMAC_SA1H (0xFFFDC09C) // (EMAC) Specific Address 1 Top, Last 2 bytes -#define AT91C_EMAC_CSE (0xFFFDC068) // (EMAC) Carrier Sense Error Register -#define AT91C_EMAC_SA3H (0xFFFDC0AC) // (EMAC) Specific Address 3 Top, Last 2 bytes -#define AT91C_EMAC_RRE (0xFFFDC06C) // (EMAC) Receive Ressource Error Register -#define AT91C_EMAC_STE (0xFFFDC084) // (EMAC) SQE Test Error Register -// ========== Register definition for PDC_ADC peripheral ========== -#define AT91C_ADC_PTSR (0xFFFD8124) // (PDC_ADC) PDC Transfer Status Register -#define AT91C_ADC_PTCR (0xFFFD8120) // (PDC_ADC) PDC Transfer Control Register -#define AT91C_ADC_TNPR (0xFFFD8118) // (PDC_ADC) Transmit Next Pointer Register -#define AT91C_ADC_TNCR (0xFFFD811C) // (PDC_ADC) Transmit Next Counter Register -#define AT91C_ADC_RNPR (0xFFFD8110) // (PDC_ADC) Receive Next Pointer Register -#define AT91C_ADC_RNCR (0xFFFD8114) // (PDC_ADC) Receive Next Counter Register -#define AT91C_ADC_RPR (0xFFFD8100) // (PDC_ADC) Receive Pointer Register -#define AT91C_ADC_TCR (0xFFFD810C) // (PDC_ADC) Transmit Counter Register -#define AT91C_ADC_TPR (0xFFFD8108) // (PDC_ADC) Transmit Pointer Register -#define AT91C_ADC_RCR (0xFFFD8104) // (PDC_ADC) Receive Counter Register -// ========== Register definition for ADC peripheral ========== -#define AT91C_ADC_CDR2 (0xFFFD8038) // (ADC) ADC Channel Data Register 2 -#define AT91C_ADC_CDR3 (0xFFFD803C) // (ADC) ADC Channel Data Register 3 -#define AT91C_ADC_CDR0 (0xFFFD8030) // (ADC) ADC Channel Data Register 0 -#define AT91C_ADC_CDR5 (0xFFFD8044) // (ADC) ADC Channel Data Register 5 -#define AT91C_ADC_CHDR (0xFFFD8014) // (ADC) ADC Channel Disable Register -#define AT91C_ADC_SR (0xFFFD801C) // (ADC) ADC Status Register -#define AT91C_ADC_CDR4 (0xFFFD8040) // (ADC) ADC Channel Data Register 4 -#define AT91C_ADC_CDR1 (0xFFFD8034) // (ADC) ADC Channel Data Register 1 -#define AT91C_ADC_LCDR (0xFFFD8020) // (ADC) ADC Last Converted Data Register -#define AT91C_ADC_IDR (0xFFFD8028) // (ADC) ADC Interrupt Disable Register -#define AT91C_ADC_CR (0xFFFD8000) // (ADC) ADC Control Register -#define AT91C_ADC_CDR7 (0xFFFD804C) // (ADC) ADC Channel Data Register 7 -#define AT91C_ADC_CDR6 (0xFFFD8048) // (ADC) ADC Channel Data Register 6 -#define AT91C_ADC_IER (0xFFFD8024) // (ADC) ADC Interrupt Enable Register -#define AT91C_ADC_CHER (0xFFFD8010) // (ADC) ADC Channel Enable Register -#define AT91C_ADC_CHSR (0xFFFD8018) // (ADC) ADC Channel Status Register -#define AT91C_ADC_MR (0xFFFD8004) // (ADC) ADC Mode Register -#define AT91C_ADC_IMR (0xFFFD802C) // (ADC) ADC Interrupt Mask Register -// ========== Register definition for PDC_AES peripheral ========== -#define AT91C_AES_TPR (0xFFFA4108) // (PDC_AES) Transmit Pointer Register -#define AT91C_AES_PTCR (0xFFFA4120) // (PDC_AES) PDC Transfer Control Register -#define AT91C_AES_RNPR (0xFFFA4110) // (PDC_AES) Receive Next Pointer Register -#define AT91C_AES_TNCR (0xFFFA411C) // (PDC_AES) Transmit Next Counter Register -#define AT91C_AES_TCR (0xFFFA410C) // (PDC_AES) Transmit Counter Register -#define AT91C_AES_RCR (0xFFFA4104) // (PDC_AES) Receive Counter Register -#define AT91C_AES_RNCR (0xFFFA4114) // (PDC_AES) Receive Next Counter Register -#define AT91C_AES_TNPR (0xFFFA4118) // (PDC_AES) Transmit Next Pointer Register -#define AT91C_AES_RPR (0xFFFA4100) // (PDC_AES) Receive Pointer Register -#define AT91C_AES_PTSR (0xFFFA4124) // (PDC_AES) PDC Transfer Status Register -// ========== Register definition for AES peripheral ========== -#define AT91C_AES_IVxR (0xFFFA4060) // (AES) Initialization Vector x Register -#define AT91C_AES_MR (0xFFFA4004) // (AES) Mode Register -#define AT91C_AES_VR (0xFFFA40FC) // (AES) AES Version Register -#define AT91C_AES_ODATAxR (0xFFFA4050) // (AES) Output Data x Register -#define AT91C_AES_IDATAxR (0xFFFA4040) // (AES) Input Data x Register -#define AT91C_AES_CR (0xFFFA4000) // (AES) Control Register -#define AT91C_AES_IDR (0xFFFA4014) // (AES) Interrupt Disable Register -#define AT91C_AES_IMR (0xFFFA4018) // (AES) Interrupt Mask Register -#define AT91C_AES_IER (0xFFFA4010) // (AES) Interrupt Enable Register -#define AT91C_AES_KEYWxR (0xFFFA4020) // (AES) Key Word x Register -#define AT91C_AES_ISR (0xFFFA401C) // (AES) Interrupt Status Register -// ========== Register definition for PDC_TDES peripheral ========== -#define AT91C_TDES_RNCR (0xFFFA8114) // (PDC_TDES) Receive Next Counter Register -#define AT91C_TDES_TCR (0xFFFA810C) // (PDC_TDES) Transmit Counter Register -#define AT91C_TDES_RCR (0xFFFA8104) // (PDC_TDES) Receive Counter Register -#define AT91C_TDES_TNPR (0xFFFA8118) // (PDC_TDES) Transmit Next Pointer Register -#define AT91C_TDES_RNPR (0xFFFA8110) // (PDC_TDES) Receive Next Pointer Register -#define AT91C_TDES_RPR (0xFFFA8100) // (PDC_TDES) Receive Pointer Register -#define AT91C_TDES_TNCR (0xFFFA811C) // (PDC_TDES) Transmit Next Counter Register -#define AT91C_TDES_TPR (0xFFFA8108) // (PDC_TDES) Transmit Pointer Register -#define AT91C_TDES_PTSR (0xFFFA8124) // (PDC_TDES) PDC Transfer Status Register -#define AT91C_TDES_PTCR (0xFFFA8120) // (PDC_TDES) PDC Transfer Control Register -// ========== Register definition for TDES peripheral ========== -#define AT91C_TDES_KEY2WxR (0xFFFA8028) // (TDES) Key 2 Word x Register -#define AT91C_TDES_KEY3WxR (0xFFFA8030) // (TDES) Key 3 Word x Register -#define AT91C_TDES_IDR (0xFFFA8014) // (TDES) Interrupt Disable Register -#define AT91C_TDES_VR (0xFFFA80FC) // (TDES) TDES Version Register -#define AT91C_TDES_IVxR (0xFFFA8060) // (TDES) Initialization Vector x Register -#define AT91C_TDES_ODATAxR (0xFFFA8050) // (TDES) Output Data x Register -#define AT91C_TDES_IMR (0xFFFA8018) // (TDES) Interrupt Mask Register -#define AT91C_TDES_MR (0xFFFA8004) // (TDES) Mode Register -#define AT91C_TDES_CR (0xFFFA8000) // (TDES) Control Register -#define AT91C_TDES_IER (0xFFFA8010) // (TDES) Interrupt Enable Register -#define AT91C_TDES_ISR (0xFFFA801C) // (TDES) Interrupt Status Register -#define AT91C_TDES_IDATAxR (0xFFFA8040) // (TDES) Input Data x Register -#define AT91C_TDES_KEY1WxR (0xFFFA8020) // (TDES) Key 1 Word x Register +/* ***************************************************************************** */ +/* REGISTER ADDRESS DEFINITION FOR AT91SAM7X256 */ +/* ***************************************************************************** */ +/* ========== Register definition for SYS peripheral ========== */ +/* ========== Register definition for AIC peripheral ========== */ +#define AT91C_AIC_IVR ( 0xFFFFF100 ) /* (AIC) IRQ Vector Register */ +#define AT91C_AIC_SMR ( 0xFFFFF000 ) /* (AIC) Source Mode Register */ +#define AT91C_AIC_FVR ( 0xFFFFF104 ) /* (AIC) FIQ Vector Register */ +#define AT91C_AIC_DCR ( 0xFFFFF138 ) /* (AIC) Debug Control Register (Protect) */ +#define AT91C_AIC_EOICR ( 0xFFFFF130 ) /* (AIC) End of Interrupt Command Register */ +#define AT91C_AIC_SVR ( 0xFFFFF080 ) /* (AIC) Source Vector Register */ +#define AT91C_AIC_FFSR ( 0xFFFFF148 ) /* (AIC) Fast Forcing Status Register */ +#define AT91C_AIC_ICCR ( 0xFFFFF128 ) /* (AIC) Interrupt Clear Command Register */ +#define AT91C_AIC_ISR ( 0xFFFFF108 ) /* (AIC) Interrupt Status Register */ +#define AT91C_AIC_IMR ( 0xFFFFF110 ) /* (AIC) Interrupt Mask Register */ +#define AT91C_AIC_IPR ( 0xFFFFF10C ) /* (AIC) Interrupt Pending Register */ +#define AT91C_AIC_FFER ( 0xFFFFF140 ) /* (AIC) Fast Forcing Enable Register */ +#define AT91C_AIC_IECR ( 0xFFFFF120 ) /* (AIC) Interrupt Enable Command Register */ +#define AT91C_AIC_ISCR ( 0xFFFFF12C ) /* (AIC) Interrupt Set Command Register */ +#define AT91C_AIC_FFDR ( 0xFFFFF144 ) /* (AIC) Fast Forcing Disable Register */ +#define AT91C_AIC_CISR ( 0xFFFFF114 ) /* (AIC) Core Interrupt Status Register */ +#define AT91C_AIC_IDCR ( 0xFFFFF124 ) /* (AIC) Interrupt Disable Command Register */ +#define AT91C_AIC_SPU ( 0xFFFFF134 ) /* (AIC) Spurious Vector Register */ +/* ========== Register definition for PDC_DBGU peripheral ========== */ +#define AT91C_DBGU_TCR ( 0xFFFFF30C ) /* (PDC_DBGU) Transmit Counter Register */ +#define AT91C_DBGU_RNPR ( 0xFFFFF310 ) /* (PDC_DBGU) Receive Next Pointer Register */ +#define AT91C_DBGU_TNPR ( 0xFFFFF318 ) /* (PDC_DBGU) Transmit Next Pointer Register */ +#define AT91C_DBGU_TPR ( 0xFFFFF308 ) /* (PDC_DBGU) Transmit Pointer Register */ +#define AT91C_DBGU_RPR ( 0xFFFFF300 ) /* (PDC_DBGU) Receive Pointer Register */ +#define AT91C_DBGU_RCR ( 0xFFFFF304 ) /* (PDC_DBGU) Receive Counter Register */ +#define AT91C_DBGU_RNCR ( 0xFFFFF314 ) /* (PDC_DBGU) Receive Next Counter Register */ +#define AT91C_DBGU_PTCR ( 0xFFFFF320 ) /* (PDC_DBGU) PDC Transfer Control Register */ +#define AT91C_DBGU_PTSR ( 0xFFFFF324 ) /* (PDC_DBGU) PDC Transfer Status Register */ +#define AT91C_DBGU_TNCR ( 0xFFFFF31C ) /* (PDC_DBGU) Transmit Next Counter Register */ +/* ========== Register definition for DBGU peripheral ========== */ +#define AT91C_DBGU_EXID ( 0xFFFFF244 ) /* (DBGU) Chip ID Extension Register */ +#define AT91C_DBGU_BRGR ( 0xFFFFF220 ) /* (DBGU) Baud Rate Generator Register */ +#define AT91C_DBGU_IDR ( 0xFFFFF20C ) /* (DBGU) Interrupt Disable Register */ +#define AT91C_DBGU_CSR ( 0xFFFFF214 ) /* (DBGU) Channel Status Register */ +#define AT91C_DBGU_CIDR ( 0xFFFFF240 ) /* (DBGU) Chip ID Register */ +#define AT91C_DBGU_MR ( 0xFFFFF204 ) /* (DBGU) Mode Register */ +#define AT91C_DBGU_IMR ( 0xFFFFF210 ) /* (DBGU) Interrupt Mask Register */ +#define AT91C_DBGU_CR ( 0xFFFFF200 ) /* (DBGU) Control Register */ +#define AT91C_DBGU_FNTR ( 0xFFFFF248 ) /* (DBGU) Force NTRST Register */ +#define AT91C_DBGU_THR ( 0xFFFFF21C ) /* (DBGU) Transmitter Holding Register */ +#define AT91C_DBGU_RHR ( 0xFFFFF218 ) /* (DBGU) Receiver Holding Register */ +#define AT91C_DBGU_IER ( 0xFFFFF208 ) /* (DBGU) Interrupt Enable Register */ +/* ========== Register definition for PIOA peripheral ========== */ +#define AT91C_PIOA_ODR ( 0xFFFFF414 ) /* (PIOA) Output Disable Registerr */ +#define AT91C_PIOA_SODR ( 0xFFFFF430 ) /* (PIOA) Set Output Data Register */ +#define AT91C_PIOA_ISR ( 0xFFFFF44C ) /* (PIOA) Interrupt Status Register */ +#define AT91C_PIOA_ABSR ( 0xFFFFF478 ) /* (PIOA) AB Select Status Register */ +#define AT91C_PIOA_IER ( 0xFFFFF440 ) /* (PIOA) Interrupt Enable Register */ +#define AT91C_PIOA_PPUDR ( 0xFFFFF460 ) /* (PIOA) Pull-up Disable Register */ +#define AT91C_PIOA_IMR ( 0xFFFFF448 ) /* (PIOA) Interrupt Mask Register */ +#define AT91C_PIOA_PER ( 0xFFFFF400 ) /* (PIOA) PIO Enable Register */ +#define AT91C_PIOA_IFDR ( 0xFFFFF424 ) /* (PIOA) Input Filter Disable Register */ +#define AT91C_PIOA_OWDR ( 0xFFFFF4A4 ) /* (PIOA) Output Write Disable Register */ +#define AT91C_PIOA_MDSR ( 0xFFFFF458 ) /* (PIOA) Multi-driver Status Register */ +#define AT91C_PIOA_IDR ( 0xFFFFF444 ) /* (PIOA) Interrupt Disable Register */ +#define AT91C_PIOA_ODSR ( 0xFFFFF438 ) /* (PIOA) Output Data Status Register */ +#define AT91C_PIOA_PPUSR ( 0xFFFFF468 ) /* (PIOA) Pull-up Status Register */ +#define AT91C_PIOA_OWSR ( 0xFFFFF4A8 ) /* (PIOA) Output Write Status Register */ +#define AT91C_PIOA_BSR ( 0xFFFFF474 ) /* (PIOA) Select B Register */ +#define AT91C_PIOA_OWER ( 0xFFFFF4A0 ) /* (PIOA) Output Write Enable Register */ +#define AT91C_PIOA_IFER ( 0xFFFFF420 ) /* (PIOA) Input Filter Enable Register */ +#define AT91C_PIOA_PDSR ( 0xFFFFF43C ) /* (PIOA) Pin Data Status Register */ +#define AT91C_PIOA_PPUER ( 0xFFFFF464 ) /* (PIOA) Pull-up Enable Register */ +#define AT91C_PIOA_OSR ( 0xFFFFF418 ) /* (PIOA) Output Status Register */ +#define AT91C_PIOA_ASR ( 0xFFFFF470 ) /* (PIOA) Select A Register */ +#define AT91C_PIOA_MDDR ( 0xFFFFF454 ) /* (PIOA) Multi-driver Disable Register */ +#define AT91C_PIOA_CODR ( 0xFFFFF434 ) /* (PIOA) Clear Output Data Register */ +#define AT91C_PIOA_MDER ( 0xFFFFF450 ) /* (PIOA) Multi-driver Enable Register */ +#define AT91C_PIOA_PDR ( 0xFFFFF404 ) /* (PIOA) PIO Disable Register */ +#define AT91C_PIOA_IFSR ( 0xFFFFF428 ) /* (PIOA) Input Filter Status Register */ +#define AT91C_PIOA_OER ( 0xFFFFF410 ) /* (PIOA) Output Enable Register */ +#define AT91C_PIOA_PSR ( 0xFFFFF408 ) /* (PIOA) PIO Status Register */ +/* ========== Register definition for PIOB peripheral ========== */ +#define AT91C_PIOB_OWDR ( 0xFFFFF6A4 ) /* (PIOB) Output Write Disable Register */ +#define AT91C_PIOB_MDER ( 0xFFFFF650 ) /* (PIOB) Multi-driver Enable Register */ +#define AT91C_PIOB_PPUSR ( 0xFFFFF668 ) /* (PIOB) Pull-up Status Register */ +#define AT91C_PIOB_IMR ( 0xFFFFF648 ) /* (PIOB) Interrupt Mask Register */ +#define AT91C_PIOB_ASR ( 0xFFFFF670 ) /* (PIOB) Select A Register */ +#define AT91C_PIOB_PPUDR ( 0xFFFFF660 ) /* (PIOB) Pull-up Disable Register */ +#define AT91C_PIOB_PSR ( 0xFFFFF608 ) /* (PIOB) PIO Status Register */ +#define AT91C_PIOB_IER ( 0xFFFFF640 ) /* (PIOB) Interrupt Enable Register */ +#define AT91C_PIOB_CODR ( 0xFFFFF634 ) /* (PIOB) Clear Output Data Register */ +#define AT91C_PIOB_OWER ( 0xFFFFF6A0 ) /* (PIOB) Output Write Enable Register */ +#define AT91C_PIOB_ABSR ( 0xFFFFF678 ) /* (PIOB) AB Select Status Register */ +#define AT91C_PIOB_IFDR ( 0xFFFFF624 ) /* (PIOB) Input Filter Disable Register */ +#define AT91C_PIOB_PDSR ( 0xFFFFF63C ) /* (PIOB) Pin Data Status Register */ +#define AT91C_PIOB_IDR ( 0xFFFFF644 ) /* (PIOB) Interrupt Disable Register */ +#define AT91C_PIOB_OWSR ( 0xFFFFF6A8 ) /* (PIOB) Output Write Status Register */ +#define AT91C_PIOB_PDR ( 0xFFFFF604 ) /* (PIOB) PIO Disable Register */ +#define AT91C_PIOB_ODR ( 0xFFFFF614 ) /* (PIOB) Output Disable Registerr */ +#define AT91C_PIOB_IFSR ( 0xFFFFF628 ) /* (PIOB) Input Filter Status Register */ +#define AT91C_PIOB_PPUER ( 0xFFFFF664 ) /* (PIOB) Pull-up Enable Register */ +#define AT91C_PIOB_SODR ( 0xFFFFF630 ) /* (PIOB) Set Output Data Register */ +#define AT91C_PIOB_ISR ( 0xFFFFF64C ) /* (PIOB) Interrupt Status Register */ +#define AT91C_PIOB_ODSR ( 0xFFFFF638 ) /* (PIOB) Output Data Status Register */ +#define AT91C_PIOB_OSR ( 0xFFFFF618 ) /* (PIOB) Output Status Register */ +#define AT91C_PIOB_MDSR ( 0xFFFFF658 ) /* (PIOB) Multi-driver Status Register */ +#define AT91C_PIOB_IFER ( 0xFFFFF620 ) /* (PIOB) Input Filter Enable Register */ +#define AT91C_PIOB_BSR ( 0xFFFFF674 ) /* (PIOB) Select B Register */ +#define AT91C_PIOB_MDDR ( 0xFFFFF654 ) /* (PIOB) Multi-driver Disable Register */ +#define AT91C_PIOB_OER ( 0xFFFFF610 ) /* (PIOB) Output Enable Register */ +#define AT91C_PIOB_PER ( 0xFFFFF600 ) /* (PIOB) PIO Enable Register */ +/* ========== Register definition for CKGR peripheral ========== */ +#define AT91C_CKGR_MOR ( 0xFFFFFC20 ) /* (CKGR) Main Oscillator Register */ +#define AT91C_CKGR_PLLR ( 0xFFFFFC2C ) /* (CKGR) PLL Register */ +#define AT91C_CKGR_MCFR ( 0xFFFFFC24 ) /* (CKGR) Main Clock Frequency Register */ +/* ========== Register definition for PMC peripheral ========== */ +#define AT91C_PMC_IDR ( 0xFFFFFC64 ) /* (PMC) Interrupt Disable Register */ +#define AT91C_PMC_MOR ( 0xFFFFFC20 ) /* (PMC) Main Oscillator Register */ +#define AT91C_PMC_PLLR ( 0xFFFFFC2C ) /* (PMC) PLL Register */ +#define AT91C_PMC_PCER ( 0xFFFFFC10 ) /* (PMC) Peripheral Clock Enable Register */ +#define AT91C_PMC_PCKR ( 0xFFFFFC40 ) /* (PMC) Programmable Clock Register */ +#define AT91C_PMC_MCKR ( 0xFFFFFC30 ) /* (PMC) Master Clock Register */ +#define AT91C_PMC_SCDR ( 0xFFFFFC04 ) /* (PMC) System Clock Disable Register */ +#define AT91C_PMC_PCDR ( 0xFFFFFC14 ) /* (PMC) Peripheral Clock Disable Register */ +#define AT91C_PMC_SCSR ( 0xFFFFFC08 ) /* (PMC) System Clock Status Register */ +#define AT91C_PMC_PCSR ( 0xFFFFFC18 ) /* (PMC) Peripheral Clock Status Register */ +#define AT91C_PMC_MCFR ( 0xFFFFFC24 ) /* (PMC) Main Clock Frequency Register */ +#define AT91C_PMC_SCER ( 0xFFFFFC00 ) /* (PMC) System Clock Enable Register */ +#define AT91C_PMC_IMR ( 0xFFFFFC6C ) /* (PMC) Interrupt Mask Register */ +#define AT91C_PMC_IER ( 0xFFFFFC60 ) /* (PMC) Interrupt Enable Register */ +#define AT91C_PMC_SR ( 0xFFFFFC68 ) /* (PMC) Status Register */ +/* ========== Register definition for RSTC peripheral ========== */ +#define AT91C_RSTC_RCR ( 0xFFFFFD00 ) /* (RSTC) Reset Control Register */ +#define AT91C_RSTC_RMR ( 0xFFFFFD08 ) /* (RSTC) Reset Mode Register */ +#define AT91C_RSTC_RSR ( 0xFFFFFD04 ) /* (RSTC) Reset Status Register */ +/* ========== Register definition for RTTC peripheral ========== */ +#define AT91C_RTTC_RTSR ( 0xFFFFFD2C ) /* (RTTC) Real-time Status Register */ +#define AT91C_RTTC_RTMR ( 0xFFFFFD20 ) /* (RTTC) Real-time Mode Register */ +#define AT91C_RTTC_RTVR ( 0xFFFFFD28 ) /* (RTTC) Real-time Value Register */ +#define AT91C_RTTC_RTAR ( 0xFFFFFD24 ) /* (RTTC) Real-time Alarm Register */ +/* ========== Register definition for PITC peripheral ========== */ +#define AT91C_PITC_PIVR ( 0xFFFFFD38 ) /* (PITC) Period Interval Value Register */ +#define AT91C_PITC_PISR ( 0xFFFFFD34 ) /* (PITC) Period Interval Status Register */ +#define AT91C_PITC_PIIR ( 0xFFFFFD3C ) /* (PITC) Period Interval Image Register */ +#define AT91C_PITC_PIMR ( 0xFFFFFD30 ) /* (PITC) Period Interval Mode Register */ +/* ========== Register definition for WDTC peripheral ========== */ +#define AT91C_WDTC_WDCR ( 0xFFFFFD40 ) /* (WDTC) Watchdog Control Register */ +#define AT91C_WDTC_WDSR ( 0xFFFFFD48 ) /* (WDTC) Watchdog Status Register */ +#define AT91C_WDTC_WDMR ( 0xFFFFFD44 ) /* (WDTC) Watchdog Mode Register */ +/* ========== Register definition for VREG peripheral ========== */ +#define AT91C_VREG_MR ( 0xFFFFFD60 ) /* (VREG) Voltage Regulator Mode Register */ +/* ========== Register definition for MC peripheral ========== */ +#define AT91C_MC_ASR ( 0xFFFFFF04 ) /* (MC) MC Abort Status Register */ +#define AT91C_MC_RCR ( 0xFFFFFF00 ) /* (MC) MC Remap Control Register */ +#define AT91C_MC_FCR ( 0xFFFFFF64 ) /* (MC) MC Flash Command Register */ +#define AT91C_MC_AASR ( 0xFFFFFF08 ) /* (MC) MC Abort Address Status Register */ +#define AT91C_MC_FSR ( 0xFFFFFF68 ) /* (MC) MC Flash Status Register */ +#define AT91C_MC_FMR ( 0xFFFFFF60 ) /* (MC) MC Flash Mode Register */ +/* ========== Register definition for PDC_SPI1 peripheral ========== */ +#define AT91C_SPI1_PTCR ( 0xFFFE4120 ) /* (PDC_SPI1) PDC Transfer Control Register */ +#define AT91C_SPI1_RPR ( 0xFFFE4100 ) /* (PDC_SPI1) Receive Pointer Register */ +#define AT91C_SPI1_TNCR ( 0xFFFE411C ) /* (PDC_SPI1) Transmit Next Counter Register */ +#define AT91C_SPI1_TPR ( 0xFFFE4108 ) /* (PDC_SPI1) Transmit Pointer Register */ +#define AT91C_SPI1_TNPR ( 0xFFFE4118 ) /* (PDC_SPI1) Transmit Next Pointer Register */ +#define AT91C_SPI1_TCR ( 0xFFFE410C ) /* (PDC_SPI1) Transmit Counter Register */ +#define AT91C_SPI1_RCR ( 0xFFFE4104 ) /* (PDC_SPI1) Receive Counter Register */ +#define AT91C_SPI1_RNPR ( 0xFFFE4110 ) /* (PDC_SPI1) Receive Next Pointer Register */ +#define AT91C_SPI1_RNCR ( 0xFFFE4114 ) /* (PDC_SPI1) Receive Next Counter Register */ +#define AT91C_SPI1_PTSR ( 0xFFFE4124 ) /* (PDC_SPI1) PDC Transfer Status Register */ +/* ========== Register definition for SPI1 peripheral ========== */ +#define AT91C_SPI1_IMR ( 0xFFFE401C ) /* (SPI1) Interrupt Mask Register */ +#define AT91C_SPI1_IER ( 0xFFFE4014 ) /* (SPI1) Interrupt Enable Register */ +#define AT91C_SPI1_MR ( 0xFFFE4004 ) /* (SPI1) Mode Register */ +#define AT91C_SPI1_RDR ( 0xFFFE4008 ) /* (SPI1) Receive Data Register */ +#define AT91C_SPI1_IDR ( 0xFFFE4018 ) /* (SPI1) Interrupt Disable Register */ +#define AT91C_SPI1_SR ( 0xFFFE4010 ) /* (SPI1) Status Register */ +#define AT91C_SPI1_TDR ( 0xFFFE400C ) /* (SPI1) Transmit Data Register */ +#define AT91C_SPI1_CR ( 0xFFFE4000 ) /* (SPI1) Control Register */ +#define AT91C_SPI1_CSR ( 0xFFFE4030 ) /* (SPI1) Chip Select Register */ +/* ========== Register definition for PDC_SPI0 peripheral ========== */ +#define AT91C_SPI0_PTCR ( 0xFFFE0120 ) /* (PDC_SPI0) PDC Transfer Control Register */ +#define AT91C_SPI0_TPR ( 0xFFFE0108 ) /* (PDC_SPI0) Transmit Pointer Register */ +#define AT91C_SPI0_TCR ( 0xFFFE010C ) /* (PDC_SPI0) Transmit Counter Register */ +#define AT91C_SPI0_RCR ( 0xFFFE0104 ) /* (PDC_SPI0) Receive Counter Register */ +#define AT91C_SPI0_PTSR ( 0xFFFE0124 ) /* (PDC_SPI0) PDC Transfer Status Register */ +#define AT91C_SPI0_RNPR ( 0xFFFE0110 ) /* (PDC_SPI0) Receive Next Pointer Register */ +#define AT91C_SPI0_RPR ( 0xFFFE0100 ) /* (PDC_SPI0) Receive Pointer Register */ +#define AT91C_SPI0_TNCR ( 0xFFFE011C ) /* (PDC_SPI0) Transmit Next Counter Register */ +#define AT91C_SPI0_RNCR ( 0xFFFE0114 ) /* (PDC_SPI0) Receive Next Counter Register */ +#define AT91C_SPI0_TNPR ( 0xFFFE0118 ) /* (PDC_SPI0) Transmit Next Pointer Register */ +/* ========== Register definition for SPI0 peripheral ========== */ +#define AT91C_SPI0_IER ( 0xFFFE0014 ) /* (SPI0) Interrupt Enable Register */ +#define AT91C_SPI0_SR ( 0xFFFE0010 ) /* (SPI0) Status Register */ +#define AT91C_SPI0_IDR ( 0xFFFE0018 ) /* (SPI0) Interrupt Disable Register */ +#define AT91C_SPI0_CR ( 0xFFFE0000 ) /* (SPI0) Control Register */ +#define AT91C_SPI0_MR ( 0xFFFE0004 ) /* (SPI0) Mode Register */ +#define AT91C_SPI0_IMR ( 0xFFFE001C ) /* (SPI0) Interrupt Mask Register */ +#define AT91C_SPI0_TDR ( 0xFFFE000C ) /* (SPI0) Transmit Data Register */ +#define AT91C_SPI0_RDR ( 0xFFFE0008 ) /* (SPI0) Receive Data Register */ +#define AT91C_SPI0_CSR ( 0xFFFE0030 ) /* (SPI0) Chip Select Register */ +/* ========== Register definition for PDC_US1 peripheral ========== */ +#define AT91C_US1_RNCR ( 0xFFFC4114 ) /* (PDC_US1) Receive Next Counter Register */ +#define AT91C_US1_PTCR ( 0xFFFC4120 ) /* (PDC_US1) PDC Transfer Control Register */ +#define AT91C_US1_TCR ( 0xFFFC410C ) /* (PDC_US1) Transmit Counter Register */ +#define AT91C_US1_PTSR ( 0xFFFC4124 ) /* (PDC_US1) PDC Transfer Status Register */ +#define AT91C_US1_TNPR ( 0xFFFC4118 ) /* (PDC_US1) Transmit Next Pointer Register */ +#define AT91C_US1_RCR ( 0xFFFC4104 ) /* (PDC_US1) Receive Counter Register */ +#define AT91C_US1_RNPR ( 0xFFFC4110 ) /* (PDC_US1) Receive Next Pointer Register */ +#define AT91C_US1_RPR ( 0xFFFC4100 ) /* (PDC_US1) Receive Pointer Register */ +#define AT91C_US1_TNCR ( 0xFFFC411C ) /* (PDC_US1) Transmit Next Counter Register */ +#define AT91C_US1_TPR ( 0xFFFC4108 ) /* (PDC_US1) Transmit Pointer Register */ +/* ========== Register definition for US1 peripheral ========== */ +#define AT91C_US1_IF ( 0xFFFC404C ) /* (US1) IRDA_FILTER Register */ +#define AT91C_US1_NER ( 0xFFFC4044 ) /* (US1) Nb Errors Register */ +#define AT91C_US1_RTOR ( 0xFFFC4024 ) /* (US1) Receiver Time-out Register */ +#define AT91C_US1_CSR ( 0xFFFC4014 ) /* (US1) Channel Status Register */ +#define AT91C_US1_IDR ( 0xFFFC400C ) /* (US1) Interrupt Disable Register */ +#define AT91C_US1_IER ( 0xFFFC4008 ) /* (US1) Interrupt Enable Register */ +#define AT91C_US1_THR ( 0xFFFC401C ) /* (US1) Transmitter Holding Register */ +#define AT91C_US1_TTGR ( 0xFFFC4028 ) /* (US1) Transmitter Time-guard Register */ +#define AT91C_US1_RHR ( 0xFFFC4018 ) /* (US1) Receiver Holding Register */ +#define AT91C_US1_BRGR ( 0xFFFC4020 ) /* (US1) Baud Rate Generator Register */ +#define AT91C_US1_IMR ( 0xFFFC4010 ) /* (US1) Interrupt Mask Register */ +#define AT91C_US1_FIDI ( 0xFFFC4040 ) /* (US1) FI_DI_Ratio Register */ +#define AT91C_US1_CR ( 0xFFFC4000 ) /* (US1) Control Register */ +#define AT91C_US1_MR ( 0xFFFC4004 ) /* (US1) Mode Register */ +/* ========== Register definition for PDC_US0 peripheral ========== */ +#define AT91C_US0_TNPR ( 0xFFFC0118 ) /* (PDC_US0) Transmit Next Pointer Register */ +#define AT91C_US0_RNPR ( 0xFFFC0110 ) /* (PDC_US0) Receive Next Pointer Register */ +#define AT91C_US0_TCR ( 0xFFFC010C ) /* (PDC_US0) Transmit Counter Register */ +#define AT91C_US0_PTCR ( 0xFFFC0120 ) /* (PDC_US0) PDC Transfer Control Register */ +#define AT91C_US0_PTSR ( 0xFFFC0124 ) /* (PDC_US0) PDC Transfer Status Register */ +#define AT91C_US0_TNCR ( 0xFFFC011C ) /* (PDC_US0) Transmit Next Counter Register */ +#define AT91C_US0_TPR ( 0xFFFC0108 ) /* (PDC_US0) Transmit Pointer Register */ +#define AT91C_US0_RCR ( 0xFFFC0104 ) /* (PDC_US0) Receive Counter Register */ +#define AT91C_US0_RPR ( 0xFFFC0100 ) /* (PDC_US0) Receive Pointer Register */ +#define AT91C_US0_RNCR ( 0xFFFC0114 ) /* (PDC_US0) Receive Next Counter Register */ +/* ========== Register definition for US0 peripheral ========== */ +#define AT91C_US0_BRGR ( 0xFFFC0020 ) /* (US0) Baud Rate Generator Register */ +#define AT91C_US0_NER ( 0xFFFC0044 ) /* (US0) Nb Errors Register */ +#define AT91C_US0_CR ( 0xFFFC0000 ) /* (US0) Control Register */ +#define AT91C_US0_IMR ( 0xFFFC0010 ) /* (US0) Interrupt Mask Register */ +#define AT91C_US0_FIDI ( 0xFFFC0040 ) /* (US0) FI_DI_Ratio Register */ +#define AT91C_US0_TTGR ( 0xFFFC0028 ) /* (US0) Transmitter Time-guard Register */ +#define AT91C_US0_MR ( 0xFFFC0004 ) /* (US0) Mode Register */ +#define AT91C_US0_RTOR ( 0xFFFC0024 ) /* (US0) Receiver Time-out Register */ +#define AT91C_US0_CSR ( 0xFFFC0014 ) /* (US0) Channel Status Register */ +#define AT91C_US0_RHR ( 0xFFFC0018 ) /* (US0) Receiver Holding Register */ +#define AT91C_US0_IDR ( 0xFFFC000C ) /* (US0) Interrupt Disable Register */ +#define AT91C_US0_THR ( 0xFFFC001C ) /* (US0) Transmitter Holding Register */ +#define AT91C_US0_IF ( 0xFFFC004C ) /* (US0) IRDA_FILTER Register */ +#define AT91C_US0_IER ( 0xFFFC0008 ) /* (US0) Interrupt Enable Register */ +/* ========== Register definition for PDC_SSC peripheral ========== */ +#define AT91C_SSC_TNCR ( 0xFFFD411C ) /* (PDC_SSC) Transmit Next Counter Register */ +#define AT91C_SSC_RPR ( 0xFFFD4100 ) /* (PDC_SSC) Receive Pointer Register */ +#define AT91C_SSC_RNCR ( 0xFFFD4114 ) /* (PDC_SSC) Receive Next Counter Register */ +#define AT91C_SSC_TPR ( 0xFFFD4108 ) /* (PDC_SSC) Transmit Pointer Register */ +#define AT91C_SSC_PTCR ( 0xFFFD4120 ) /* (PDC_SSC) PDC Transfer Control Register */ +#define AT91C_SSC_TCR ( 0xFFFD410C ) /* (PDC_SSC) Transmit Counter Register */ +#define AT91C_SSC_RCR ( 0xFFFD4104 ) /* (PDC_SSC) Receive Counter Register */ +#define AT91C_SSC_RNPR ( 0xFFFD4110 ) /* (PDC_SSC) Receive Next Pointer Register */ +#define AT91C_SSC_TNPR ( 0xFFFD4118 ) /* (PDC_SSC) Transmit Next Pointer Register */ +#define AT91C_SSC_PTSR ( 0xFFFD4124 ) /* (PDC_SSC) PDC Transfer Status Register */ +/* ========== Register definition for SSC peripheral ========== */ +#define AT91C_SSC_RHR ( 0xFFFD4020 ) /* (SSC) Receive Holding Register */ +#define AT91C_SSC_RSHR ( 0xFFFD4030 ) /* (SSC) Receive Sync Holding Register */ +#define AT91C_SSC_TFMR ( 0xFFFD401C ) /* (SSC) Transmit Frame Mode Register */ +#define AT91C_SSC_IDR ( 0xFFFD4048 ) /* (SSC) Interrupt Disable Register */ +#define AT91C_SSC_THR ( 0xFFFD4024 ) /* (SSC) Transmit Holding Register */ +#define AT91C_SSC_RCMR ( 0xFFFD4010 ) /* (SSC) Receive Clock ModeRegister */ +#define AT91C_SSC_IER ( 0xFFFD4044 ) /* (SSC) Interrupt Enable Register */ +#define AT91C_SSC_TSHR ( 0xFFFD4034 ) /* (SSC) Transmit Sync Holding Register */ +#define AT91C_SSC_SR ( 0xFFFD4040 ) /* (SSC) Status Register */ +#define AT91C_SSC_CMR ( 0xFFFD4004 ) /* (SSC) Clock Mode Register */ +#define AT91C_SSC_TCMR ( 0xFFFD4018 ) /* (SSC) Transmit Clock Mode Register */ +#define AT91C_SSC_CR ( 0xFFFD4000 ) /* (SSC) Control Register */ +#define AT91C_SSC_IMR ( 0xFFFD404C ) /* (SSC) Interrupt Mask Register */ +#define AT91C_SSC_RFMR ( 0xFFFD4014 ) /* (SSC) Receive Frame Mode Register */ +/* ========== Register definition for TWI peripheral ========== */ +#define AT91C_TWI_IER ( 0xFFFB8024 ) /* (TWI) Interrupt Enable Register */ +#define AT91C_TWI_CR ( 0xFFFB8000 ) /* (TWI) Control Register */ +#define AT91C_TWI_SR ( 0xFFFB8020 ) /* (TWI) Status Register */ +#define AT91C_TWI_IMR ( 0xFFFB802C ) /* (TWI) Interrupt Mask Register */ +#define AT91C_TWI_THR ( 0xFFFB8034 ) /* (TWI) Transmit Holding Register */ +#define AT91C_TWI_IDR ( 0xFFFB8028 ) /* (TWI) Interrupt Disable Register */ +#define AT91C_TWI_IADR ( 0xFFFB800C ) /* (TWI) Internal Address Register */ +#define AT91C_TWI_MMR ( 0xFFFB8004 ) /* (TWI) Master Mode Register */ +#define AT91C_TWI_CWGR ( 0xFFFB8010 ) /* (TWI) Clock Waveform Generator Register */ +#define AT91C_TWI_RHR ( 0xFFFB8030 ) /* (TWI) Receive Holding Register */ +/* ========== Register definition for PWMC_CH3 peripheral ========== */ +#define AT91C_PWMC_CH3_CUPDR ( 0xFFFCC270 ) /* (PWMC_CH3) Channel Update Register */ +#define AT91C_PWMC_CH3_Reserved ( 0xFFFCC274 ) /* (PWMC_CH3) Reserved */ +#define AT91C_PWMC_CH3_CPRDR ( 0xFFFCC268 ) /* (PWMC_CH3) Channel Period Register */ +#define AT91C_PWMC_CH3_CDTYR ( 0xFFFCC264 ) /* (PWMC_CH3) Channel Duty Cycle Register */ +#define AT91C_PWMC_CH3_CCNTR ( 0xFFFCC26C ) /* (PWMC_CH3) Channel Counter Register */ +#define AT91C_PWMC_CH3_CMR ( 0xFFFCC260 ) /* (PWMC_CH3) Channel Mode Register */ +/* ========== Register definition for PWMC_CH2 peripheral ========== */ +#define AT91C_PWMC_CH2_Reserved ( 0xFFFCC254 ) /* (PWMC_CH2) Reserved */ +#define AT91C_PWMC_CH2_CMR ( 0xFFFCC240 ) /* (PWMC_CH2) Channel Mode Register */ +#define AT91C_PWMC_CH2_CCNTR ( 0xFFFCC24C ) /* (PWMC_CH2) Channel Counter Register */ +#define AT91C_PWMC_CH2_CPRDR ( 0xFFFCC248 ) /* (PWMC_CH2) Channel Period Register */ +#define AT91C_PWMC_CH2_CUPDR ( 0xFFFCC250 ) /* (PWMC_CH2) Channel Update Register */ +#define AT91C_PWMC_CH2_CDTYR ( 0xFFFCC244 ) /* (PWMC_CH2) Channel Duty Cycle Register */ +/* ========== Register definition for PWMC_CH1 peripheral ========== */ +#define AT91C_PWMC_CH1_Reserved ( 0xFFFCC234 ) /* (PWMC_CH1) Reserved */ +#define AT91C_PWMC_CH1_CUPDR ( 0xFFFCC230 ) /* (PWMC_CH1) Channel Update Register */ +#define AT91C_PWMC_CH1_CPRDR ( 0xFFFCC228 ) /* (PWMC_CH1) Channel Period Register */ +#define AT91C_PWMC_CH1_CCNTR ( 0xFFFCC22C ) /* (PWMC_CH1) Channel Counter Register */ +#define AT91C_PWMC_CH1_CDTYR ( 0xFFFCC224 ) /* (PWMC_CH1) Channel Duty Cycle Register */ +#define AT91C_PWMC_CH1_CMR ( 0xFFFCC220 ) /* (PWMC_CH1) Channel Mode Register */ +/* ========== Register definition for PWMC_CH0 peripheral ========== */ +#define AT91C_PWMC_CH0_Reserved ( 0xFFFCC214 ) /* (PWMC_CH0) Reserved */ +#define AT91C_PWMC_CH0_CPRDR ( 0xFFFCC208 ) /* (PWMC_CH0) Channel Period Register */ +#define AT91C_PWMC_CH0_CDTYR ( 0xFFFCC204 ) /* (PWMC_CH0) Channel Duty Cycle Register */ +#define AT91C_PWMC_CH0_CMR ( 0xFFFCC200 ) /* (PWMC_CH0) Channel Mode Register */ +#define AT91C_PWMC_CH0_CUPDR ( 0xFFFCC210 ) /* (PWMC_CH0) Channel Update Register */ +#define AT91C_PWMC_CH0_CCNTR ( 0xFFFCC20C ) /* (PWMC_CH0) Channel Counter Register */ +/* ========== Register definition for PWMC peripheral ========== */ +#define AT91C_PWMC_IDR ( 0xFFFCC014 ) /* (PWMC) PWMC Interrupt Disable Register */ +#define AT91C_PWMC_DIS ( 0xFFFCC008 ) /* (PWMC) PWMC Disable Register */ +#define AT91C_PWMC_IER ( 0xFFFCC010 ) /* (PWMC) PWMC Interrupt Enable Register */ +#define AT91C_PWMC_VR ( 0xFFFCC0FC ) /* (PWMC) PWMC Version Register */ +#define AT91C_PWMC_ISR ( 0xFFFCC01C ) /* (PWMC) PWMC Interrupt Status Register */ +#define AT91C_PWMC_SR ( 0xFFFCC00C ) /* (PWMC) PWMC Status Register */ +#define AT91C_PWMC_IMR ( 0xFFFCC018 ) /* (PWMC) PWMC Interrupt Mask Register */ +#define AT91C_PWMC_MR ( 0xFFFCC000 ) /* (PWMC) PWMC Mode Register */ +#define AT91C_PWMC_ENA ( 0xFFFCC004 ) /* (PWMC) PWMC Enable Register */ +/* ========== Register definition for UDP peripheral ========== */ +#define AT91C_UDP_IMR ( 0xFFFB0018 ) /* (UDP) Interrupt Mask Register */ +#define AT91C_UDP_FADDR ( 0xFFFB0008 ) /* (UDP) Function Address Register */ +#define AT91C_UDP_NUM ( 0xFFFB0000 ) /* (UDP) Frame Number Register */ +#define AT91C_UDP_FDR ( 0xFFFB0050 ) /* (UDP) Endpoint FIFO Data Register */ +#define AT91C_UDP_ISR ( 0xFFFB001C ) /* (UDP) Interrupt Status Register */ +#define AT91C_UDP_CSR ( 0xFFFB0030 ) /* (UDP) Endpoint Control and Status Register */ +#define AT91C_UDP_IDR ( 0xFFFB0014 ) /* (UDP) Interrupt Disable Register */ +#define AT91C_UDP_ICR ( 0xFFFB0020 ) /* (UDP) Interrupt Clear Register */ +#define AT91C_UDP_RSTEP ( 0xFFFB0028 ) /* (UDP) Reset Endpoint Register */ +#define AT91C_UDP_TXVC ( 0xFFFB0074 ) /* (UDP) Transceiver Control Register */ +#define AT91C_UDP_GLBSTATE ( 0xFFFB0004 ) /* (UDP) Global State Register */ +#define AT91C_UDP_IER ( 0xFFFB0010 ) /* (UDP) Interrupt Enable Register */ +/* ========== Register definition for TC0 peripheral ========== */ +#define AT91C_TC0_SR ( 0xFFFA0020 ) /* (TC0) Status Register */ +#define AT91C_TC0_RC ( 0xFFFA001C ) /* (TC0) Register C */ +#define AT91C_TC0_RB ( 0xFFFA0018 ) /* (TC0) Register B */ +#define AT91C_TC0_CCR ( 0xFFFA0000 ) /* (TC0) Channel Control Register */ +#define AT91C_TC0_CMR ( 0xFFFA0004 ) /* (TC0) Channel Mode Register (Capture Mode / Waveform Mode) */ +#define AT91C_TC0_IER ( 0xFFFA0024 ) /* (TC0) Interrupt Enable Register */ +#define AT91C_TC0_RA ( 0xFFFA0014 ) /* (TC0) Register A */ +#define AT91C_TC0_IDR ( 0xFFFA0028 ) /* (TC0) Interrupt Disable Register */ +#define AT91C_TC0_CV ( 0xFFFA0010 ) /* (TC0) Counter Value */ +#define AT91C_TC0_IMR ( 0xFFFA002C ) /* (TC0) Interrupt Mask Register */ +/* ========== Register definition for TC1 peripheral ========== */ +#define AT91C_TC1_RB ( 0xFFFA0058 ) /* (TC1) Register B */ +#define AT91C_TC1_CCR ( 0xFFFA0040 ) /* (TC1) Channel Control Register */ +#define AT91C_TC1_IER ( 0xFFFA0064 ) /* (TC1) Interrupt Enable Register */ +#define AT91C_TC1_IDR ( 0xFFFA0068 ) /* (TC1) Interrupt Disable Register */ +#define AT91C_TC1_SR ( 0xFFFA0060 ) /* (TC1) Status Register */ +#define AT91C_TC1_CMR ( 0xFFFA0044 ) /* (TC1) Channel Mode Register (Capture Mode / Waveform Mode) */ +#define AT91C_TC1_RA ( 0xFFFA0054 ) /* (TC1) Register A */ +#define AT91C_TC1_RC ( 0xFFFA005C ) /* (TC1) Register C */ +#define AT91C_TC1_IMR ( 0xFFFA006C ) /* (TC1) Interrupt Mask Register */ +#define AT91C_TC1_CV ( 0xFFFA0050 ) /* (TC1) Counter Value */ +/* ========== Register definition for TC2 peripheral ========== */ +#define AT91C_TC2_CMR ( 0xFFFA0084 ) /* (TC2) Channel Mode Register (Capture Mode / Waveform Mode) */ +#define AT91C_TC2_CCR ( 0xFFFA0080 ) /* (TC2) Channel Control Register */ +#define AT91C_TC2_CV ( 0xFFFA0090 ) /* (TC2) Counter Value */ +#define AT91C_TC2_RA ( 0xFFFA0094 ) /* (TC2) Register A */ +#define AT91C_TC2_RB ( 0xFFFA0098 ) /* (TC2) Register B */ +#define AT91C_TC2_IDR ( 0xFFFA00A8 ) /* (TC2) Interrupt Disable Register */ +#define AT91C_TC2_IMR ( 0xFFFA00AC ) /* (TC2) Interrupt Mask Register */ +#define AT91C_TC2_RC ( 0xFFFA009C ) /* (TC2) Register C */ +#define AT91C_TC2_IER ( 0xFFFA00A4 ) /* (TC2) Interrupt Enable Register */ +#define AT91C_TC2_SR ( 0xFFFA00A0 ) /* (TC2) Status Register */ +/* ========== Register definition for TCB peripheral ========== */ +#define AT91C_TCB_BMR ( 0xFFFA00C4 ) /* (TCB) TC Block Mode Register */ +#define AT91C_TCB_BCR ( 0xFFFA00C0 ) /* (TCB) TC Block Control Register */ +/* ========== Register definition for CAN_MB0 peripheral ========== */ +#define AT91C_CAN_MB0_MDL ( 0xFFFD0214 ) /* (CAN_MB0) MailBox Data Low Register */ +#define AT91C_CAN_MB0_MAM ( 0xFFFD0204 ) /* (CAN_MB0) MailBox Acceptance Mask Register */ +#define AT91C_CAN_MB0_MCR ( 0xFFFD021C ) /* (CAN_MB0) MailBox Control Register */ +#define AT91C_CAN_MB0_MID ( 0xFFFD0208 ) /* (CAN_MB0) MailBox ID Register */ +#define AT91C_CAN_MB0_MSR ( 0xFFFD0210 ) /* (CAN_MB0) MailBox Status Register */ +#define AT91C_CAN_MB0_MFID ( 0xFFFD020C ) /* (CAN_MB0) MailBox Family ID Register */ +#define AT91C_CAN_MB0_MDH ( 0xFFFD0218 ) /* (CAN_MB0) MailBox Data High Register */ +#define AT91C_CAN_MB0_MMR ( 0xFFFD0200 ) /* (CAN_MB0) MailBox Mode Register */ +/* ========== Register definition for CAN_MB1 peripheral ========== */ +#define AT91C_CAN_MB1_MDL ( 0xFFFD0234 ) /* (CAN_MB1) MailBox Data Low Register */ +#define AT91C_CAN_MB1_MID ( 0xFFFD0228 ) /* (CAN_MB1) MailBox ID Register */ +#define AT91C_CAN_MB1_MMR ( 0xFFFD0220 ) /* (CAN_MB1) MailBox Mode Register */ +#define AT91C_CAN_MB1_MSR ( 0xFFFD0230 ) /* (CAN_MB1) MailBox Status Register */ +#define AT91C_CAN_MB1_MAM ( 0xFFFD0224 ) /* (CAN_MB1) MailBox Acceptance Mask Register */ +#define AT91C_CAN_MB1_MDH ( 0xFFFD0238 ) /* (CAN_MB1) MailBox Data High Register */ +#define AT91C_CAN_MB1_MCR ( 0xFFFD023C ) /* (CAN_MB1) MailBox Control Register */ +#define AT91C_CAN_MB1_MFID ( 0xFFFD022C ) /* (CAN_MB1) MailBox Family ID Register */ +/* ========== Register definition for CAN_MB2 peripheral ========== */ +#define AT91C_CAN_MB2_MCR ( 0xFFFD025C ) /* (CAN_MB2) MailBox Control Register */ +#define AT91C_CAN_MB2_MDH ( 0xFFFD0258 ) /* (CAN_MB2) MailBox Data High Register */ +#define AT91C_CAN_MB2_MID ( 0xFFFD0248 ) /* (CAN_MB2) MailBox ID Register */ +#define AT91C_CAN_MB2_MDL ( 0xFFFD0254 ) /* (CAN_MB2) MailBox Data Low Register */ +#define AT91C_CAN_MB2_MMR ( 0xFFFD0240 ) /* (CAN_MB2) MailBox Mode Register */ +#define AT91C_CAN_MB2_MAM ( 0xFFFD0244 ) /* (CAN_MB2) MailBox Acceptance Mask Register */ +#define AT91C_CAN_MB2_MFID ( 0xFFFD024C ) /* (CAN_MB2) MailBox Family ID Register */ +#define AT91C_CAN_MB2_MSR ( 0xFFFD0250 ) /* (CAN_MB2) MailBox Status Register */ +/* ========== Register definition for CAN_MB3 peripheral ========== */ +#define AT91C_CAN_MB3_MFID ( 0xFFFD026C ) /* (CAN_MB3) MailBox Family ID Register */ +#define AT91C_CAN_MB3_MAM ( 0xFFFD0264 ) /* (CAN_MB3) MailBox Acceptance Mask Register */ +#define AT91C_CAN_MB3_MID ( 0xFFFD0268 ) /* (CAN_MB3) MailBox ID Register */ +#define AT91C_CAN_MB3_MCR ( 0xFFFD027C ) /* (CAN_MB3) MailBox Control Register */ +#define AT91C_CAN_MB3_MMR ( 0xFFFD0260 ) /* (CAN_MB3) MailBox Mode Register */ +#define AT91C_CAN_MB3_MSR ( 0xFFFD0270 ) /* (CAN_MB3) MailBox Status Register */ +#define AT91C_CAN_MB3_MDL ( 0xFFFD0274 ) /* (CAN_MB3) MailBox Data Low Register */ +#define AT91C_CAN_MB3_MDH ( 0xFFFD0278 ) /* (CAN_MB3) MailBox Data High Register */ +/* ========== Register definition for CAN_MB4 peripheral ========== */ +#define AT91C_CAN_MB4_MID ( 0xFFFD0288 ) /* (CAN_MB4) MailBox ID Register */ +#define AT91C_CAN_MB4_MMR ( 0xFFFD0280 ) /* (CAN_MB4) MailBox Mode Register */ +#define AT91C_CAN_MB4_MDH ( 0xFFFD0298 ) /* (CAN_MB4) MailBox Data High Register */ +#define AT91C_CAN_MB4_MFID ( 0xFFFD028C ) /* (CAN_MB4) MailBox Family ID Register */ +#define AT91C_CAN_MB4_MSR ( 0xFFFD0290 ) /* (CAN_MB4) MailBox Status Register */ +#define AT91C_CAN_MB4_MCR ( 0xFFFD029C ) /* (CAN_MB4) MailBox Control Register */ +#define AT91C_CAN_MB4_MDL ( 0xFFFD0294 ) /* (CAN_MB4) MailBox Data Low Register */ +#define AT91C_CAN_MB4_MAM ( 0xFFFD0284 ) /* (CAN_MB4) MailBox Acceptance Mask Register */ +/* ========== Register definition for CAN_MB5 peripheral ========== */ +#define AT91C_CAN_MB5_MSR ( 0xFFFD02B0 ) /* (CAN_MB5) MailBox Status Register */ +#define AT91C_CAN_MB5_MCR ( 0xFFFD02BC ) /* (CAN_MB5) MailBox Control Register */ +#define AT91C_CAN_MB5_MFID ( 0xFFFD02AC ) /* (CAN_MB5) MailBox Family ID Register */ +#define AT91C_CAN_MB5_MDH ( 0xFFFD02B8 ) /* (CAN_MB5) MailBox Data High Register */ +#define AT91C_CAN_MB5_MID ( 0xFFFD02A8 ) /* (CAN_MB5) MailBox ID Register */ +#define AT91C_CAN_MB5_MMR ( 0xFFFD02A0 ) /* (CAN_MB5) MailBox Mode Register */ +#define AT91C_CAN_MB5_MDL ( 0xFFFD02B4 ) /* (CAN_MB5) MailBox Data Low Register */ +#define AT91C_CAN_MB5_MAM ( 0xFFFD02A4 ) /* (CAN_MB5) MailBox Acceptance Mask Register */ +/* ========== Register definition for CAN_MB6 peripheral ========== */ +#define AT91C_CAN_MB6_MFID ( 0xFFFD02CC ) /* (CAN_MB6) MailBox Family ID Register */ +#define AT91C_CAN_MB6_MID ( 0xFFFD02C8 ) /* (CAN_MB6) MailBox ID Register */ +#define AT91C_CAN_MB6_MAM ( 0xFFFD02C4 ) /* (CAN_MB6) MailBox Acceptance Mask Register */ +#define AT91C_CAN_MB6_MSR ( 0xFFFD02D0 ) /* (CAN_MB6) MailBox Status Register */ +#define AT91C_CAN_MB6_MDL ( 0xFFFD02D4 ) /* (CAN_MB6) MailBox Data Low Register */ +#define AT91C_CAN_MB6_MCR ( 0xFFFD02DC ) /* (CAN_MB6) MailBox Control Register */ +#define AT91C_CAN_MB6_MDH ( 0xFFFD02D8 ) /* (CAN_MB6) MailBox Data High Register */ +#define AT91C_CAN_MB6_MMR ( 0xFFFD02C0 ) /* (CAN_MB6) MailBox Mode Register */ +/* ========== Register definition for CAN_MB7 peripheral ========== */ +#define AT91C_CAN_MB7_MCR ( 0xFFFD02FC ) /* (CAN_MB7) MailBox Control Register */ +#define AT91C_CAN_MB7_MDH ( 0xFFFD02F8 ) /* (CAN_MB7) MailBox Data High Register */ +#define AT91C_CAN_MB7_MFID ( 0xFFFD02EC ) /* (CAN_MB7) MailBox Family ID Register */ +#define AT91C_CAN_MB7_MDL ( 0xFFFD02F4 ) /* (CAN_MB7) MailBox Data Low Register */ +#define AT91C_CAN_MB7_MID ( 0xFFFD02E8 ) /* (CAN_MB7) MailBox ID Register */ +#define AT91C_CAN_MB7_MMR ( 0xFFFD02E0 ) /* (CAN_MB7) MailBox Mode Register */ +#define AT91C_CAN_MB7_MAM ( 0xFFFD02E4 ) /* (CAN_MB7) MailBox Acceptance Mask Register */ +#define AT91C_CAN_MB7_MSR ( 0xFFFD02F0 ) /* (CAN_MB7) MailBox Status Register */ +/* ========== Register definition for CAN peripheral ========== */ +#define AT91C_CAN_TCR ( 0xFFFD0024 ) /* (CAN) Transfer Command Register */ +#define AT91C_CAN_IMR ( 0xFFFD000C ) /* (CAN) Interrupt Mask Register */ +#define AT91C_CAN_IER ( 0xFFFD0004 ) /* (CAN) Interrupt Enable Register */ +#define AT91C_CAN_ECR ( 0xFFFD0020 ) /* (CAN) Error Counter Register */ +#define AT91C_CAN_TIMESTP ( 0xFFFD001C ) /* (CAN) Time Stamp Register */ +#define AT91C_CAN_MR ( 0xFFFD0000 ) /* (CAN) Mode Register */ +#define AT91C_CAN_IDR ( 0xFFFD0008 ) /* (CAN) Interrupt Disable Register */ +#define AT91C_CAN_ACR ( 0xFFFD0028 ) /* (CAN) Abort Command Register */ +#define AT91C_CAN_TIM ( 0xFFFD0018 ) /* (CAN) Timer Register */ +#define AT91C_CAN_SR ( 0xFFFD0010 ) /* (CAN) Status Register */ +#define AT91C_CAN_BR ( 0xFFFD0014 ) /* (CAN) Baudrate Register */ +#define AT91C_CAN_VR ( 0xFFFD00FC ) /* (CAN) Version Register */ +/* ========== Register definition for EMAC peripheral ========== */ +#define AT91C_EMAC_ISR ( 0xFFFDC024 ) /* (EMAC) Interrupt Status Register */ +#define AT91C_EMAC_SA4H ( 0xFFFDC0B4 ) /* (EMAC) Specific Address 4 Top, Last 2 bytes */ +#define AT91C_EMAC_SA1L ( 0xFFFDC098 ) /* (EMAC) Specific Address 1 Bottom, First 4 bytes */ +#define AT91C_EMAC_ELE ( 0xFFFDC078 ) /* (EMAC) Excessive Length Errors Register */ +#define AT91C_EMAC_LCOL ( 0xFFFDC05C ) /* (EMAC) Late Collision Register */ +#define AT91C_EMAC_RLE ( 0xFFFDC088 ) /* (EMAC) Receive Length Field Mismatch Register */ +#define AT91C_EMAC_WOL ( 0xFFFDC0C4 ) /* (EMAC) Wake On LAN Register */ +#define AT91C_EMAC_DTF ( 0xFFFDC058 ) /* (EMAC) Deferred Transmission Frame Register */ +#define AT91C_EMAC_TUND ( 0xFFFDC064 ) /* (EMAC) Transmit Underrun Error Register */ +#define AT91C_EMAC_NCR ( 0xFFFDC000 ) /* (EMAC) Network Control Register */ +#define AT91C_EMAC_SA4L ( 0xFFFDC0B0 ) /* (EMAC) Specific Address 4 Bottom, First 4 bytes */ +#define AT91C_EMAC_RSR ( 0xFFFDC020 ) /* (EMAC) Receive Status Register */ +#define AT91C_EMAC_SA3L ( 0xFFFDC0A8 ) /* (EMAC) Specific Address 3 Bottom, First 4 bytes */ +#define AT91C_EMAC_TSR ( 0xFFFDC014 ) /* (EMAC) Transmit Status Register */ +#define AT91C_EMAC_IDR ( 0xFFFDC02C ) /* (EMAC) Interrupt Disable Register */ +#define AT91C_EMAC_RSE ( 0xFFFDC074 ) /* (EMAC) Receive Symbol Errors Register */ +#define AT91C_EMAC_ECOL ( 0xFFFDC060 ) /* (EMAC) Excessive Collision Register */ +#define AT91C_EMAC_TID ( 0xFFFDC0B8 ) /* (EMAC) Type ID Checking Register */ +#define AT91C_EMAC_HRB ( 0xFFFDC090 ) /* (EMAC) Hash Address Bottom[31:0] */ +#define AT91C_EMAC_TBQP ( 0xFFFDC01C ) /* (EMAC) Transmit Buffer Queue Pointer */ +#define AT91C_EMAC_USRIO ( 0xFFFDC0C0 ) /* (EMAC) USER Input/Output Register */ +#define AT91C_EMAC_PTR ( 0xFFFDC038 ) /* (EMAC) Pause Time Register */ +#define AT91C_EMAC_SA2H ( 0xFFFDC0A4 ) /* (EMAC) Specific Address 2 Top, Last 2 bytes */ +#define AT91C_EMAC_ROV ( 0xFFFDC070 ) /* (EMAC) Receive Overrun Errors Register */ +#define AT91C_EMAC_ALE ( 0xFFFDC054 ) /* (EMAC) Alignment Error Register */ +#define AT91C_EMAC_RJA ( 0xFFFDC07C ) /* (EMAC) Receive Jabbers Register */ +#define AT91C_EMAC_RBQP ( 0xFFFDC018 ) /* (EMAC) Receive Buffer Queue Pointer */ +#define AT91C_EMAC_TPF ( 0xFFFDC08C ) /* (EMAC) Transmitted Pause Frames Register */ +#define AT91C_EMAC_NCFGR ( 0xFFFDC004 ) /* (EMAC) Network Configuration Register */ +#define AT91C_EMAC_HRT ( 0xFFFDC094 ) /* (EMAC) Hash Address Top[63:32] */ +#define AT91C_EMAC_USF ( 0xFFFDC080 ) /* (EMAC) Undersize Frames Register */ +#define AT91C_EMAC_FCSE ( 0xFFFDC050 ) /* (EMAC) Frame Check Sequence Error Register */ +#define AT91C_EMAC_TPQ ( 0xFFFDC0BC ) /* (EMAC) Transmit Pause Quantum Register */ +#define AT91C_EMAC_MAN ( 0xFFFDC034 ) /* (EMAC) PHY Maintenance Register */ +#define AT91C_EMAC_FTO ( 0xFFFDC040 ) /* (EMAC) Frames Transmitted OK Register */ +#define AT91C_EMAC_REV ( 0xFFFDC0FC ) /* (EMAC) Revision Register */ +#define AT91C_EMAC_IMR ( 0xFFFDC030 ) /* (EMAC) Interrupt Mask Register */ +#define AT91C_EMAC_SCF ( 0xFFFDC044 ) /* (EMAC) Single Collision Frame Register */ +#define AT91C_EMAC_PFR ( 0xFFFDC03C ) /* (EMAC) Pause Frames received Register */ +#define AT91C_EMAC_MCF ( 0xFFFDC048 ) /* (EMAC) Multiple Collision Frame Register */ +#define AT91C_EMAC_NSR ( 0xFFFDC008 ) /* (EMAC) Network Status Register */ +#define AT91C_EMAC_SA2L ( 0xFFFDC0A0 ) /* (EMAC) Specific Address 2 Bottom, First 4 bytes */ +#define AT91C_EMAC_FRO ( 0xFFFDC04C ) /* (EMAC) Frames Received OK Register */ +#define AT91C_EMAC_IER ( 0xFFFDC028 ) /* (EMAC) Interrupt Enable Register */ +#define AT91C_EMAC_SA1H ( 0xFFFDC09C ) /* (EMAC) Specific Address 1 Top, Last 2 bytes */ +#define AT91C_EMAC_CSE ( 0xFFFDC068 ) /* (EMAC) Carrier Sense Error Register */ +#define AT91C_EMAC_SA3H ( 0xFFFDC0AC ) /* (EMAC) Specific Address 3 Top, Last 2 bytes */ +#define AT91C_EMAC_RRE ( 0xFFFDC06C ) /* (EMAC) Receive Ressource Error Register */ +#define AT91C_EMAC_STE ( 0xFFFDC084 ) /* (EMAC) SQE Test Error Register */ +/* ========== Register definition for PDC_ADC peripheral ========== */ +#define AT91C_ADC_PTSR ( 0xFFFD8124 ) /* (PDC_ADC) PDC Transfer Status Register */ +#define AT91C_ADC_PTCR ( 0xFFFD8120 ) /* (PDC_ADC) PDC Transfer Control Register */ +#define AT91C_ADC_TNPR ( 0xFFFD8118 ) /* (PDC_ADC) Transmit Next Pointer Register */ +#define AT91C_ADC_TNCR ( 0xFFFD811C ) /* (PDC_ADC) Transmit Next Counter Register */ +#define AT91C_ADC_RNPR ( 0xFFFD8110 ) /* (PDC_ADC) Receive Next Pointer Register */ +#define AT91C_ADC_RNCR ( 0xFFFD8114 ) /* (PDC_ADC) Receive Next Counter Register */ +#define AT91C_ADC_RPR ( 0xFFFD8100 ) /* (PDC_ADC) Receive Pointer Register */ +#define AT91C_ADC_TCR ( 0xFFFD810C ) /* (PDC_ADC) Transmit Counter Register */ +#define AT91C_ADC_TPR ( 0xFFFD8108 ) /* (PDC_ADC) Transmit Pointer Register */ +#define AT91C_ADC_RCR ( 0xFFFD8104 ) /* (PDC_ADC) Receive Counter Register */ +/* ========== Register definition for ADC peripheral ========== */ +#define AT91C_ADC_CDR2 ( 0xFFFD8038 ) /* (ADC) ADC Channel Data Register 2 */ +#define AT91C_ADC_CDR3 ( 0xFFFD803C ) /* (ADC) ADC Channel Data Register 3 */ +#define AT91C_ADC_CDR0 ( 0xFFFD8030 ) /* (ADC) ADC Channel Data Register 0 */ +#define AT91C_ADC_CDR5 ( 0xFFFD8044 ) /* (ADC) ADC Channel Data Register 5 */ +#define AT91C_ADC_CHDR ( 0xFFFD8014 ) /* (ADC) ADC Channel Disable Register */ +#define AT91C_ADC_SR ( 0xFFFD801C ) /* (ADC) ADC Status Register */ +#define AT91C_ADC_CDR4 ( 0xFFFD8040 ) /* (ADC) ADC Channel Data Register 4 */ +#define AT91C_ADC_CDR1 ( 0xFFFD8034 ) /* (ADC) ADC Channel Data Register 1 */ +#define AT91C_ADC_LCDR ( 0xFFFD8020 ) /* (ADC) ADC Last Converted Data Register */ +#define AT91C_ADC_IDR ( 0xFFFD8028 ) /* (ADC) ADC Interrupt Disable Register */ +#define AT91C_ADC_CR ( 0xFFFD8000 ) /* (ADC) ADC Control Register */ +#define AT91C_ADC_CDR7 ( 0xFFFD804C ) /* (ADC) ADC Channel Data Register 7 */ +#define AT91C_ADC_CDR6 ( 0xFFFD8048 ) /* (ADC) ADC Channel Data Register 6 */ +#define AT91C_ADC_IER ( 0xFFFD8024 ) /* (ADC) ADC Interrupt Enable Register */ +#define AT91C_ADC_CHER ( 0xFFFD8010 ) /* (ADC) ADC Channel Enable Register */ +#define AT91C_ADC_CHSR ( 0xFFFD8018 ) /* (ADC) ADC Channel Status Register */ +#define AT91C_ADC_MR ( 0xFFFD8004 ) /* (ADC) ADC Mode Register */ +#define AT91C_ADC_IMR ( 0xFFFD802C ) /* (ADC) ADC Interrupt Mask Register */ +/* ========== Register definition for PDC_AES peripheral ========== */ +#define AT91C_AES_TPR ( 0xFFFA4108 ) /* (PDC_AES) Transmit Pointer Register */ +#define AT91C_AES_PTCR ( 0xFFFA4120 ) /* (PDC_AES) PDC Transfer Control Register */ +#define AT91C_AES_RNPR ( 0xFFFA4110 ) /* (PDC_AES) Receive Next Pointer Register */ +#define AT91C_AES_TNCR ( 0xFFFA411C ) /* (PDC_AES) Transmit Next Counter Register */ +#define AT91C_AES_TCR ( 0xFFFA410C ) /* (PDC_AES) Transmit Counter Register */ +#define AT91C_AES_RCR ( 0xFFFA4104 ) /* (PDC_AES) Receive Counter Register */ +#define AT91C_AES_RNCR ( 0xFFFA4114 ) /* (PDC_AES) Receive Next Counter Register */ +#define AT91C_AES_TNPR ( 0xFFFA4118 ) /* (PDC_AES) Transmit Next Pointer Register */ +#define AT91C_AES_RPR ( 0xFFFA4100 ) /* (PDC_AES) Receive Pointer Register */ +#define AT91C_AES_PTSR ( 0xFFFA4124 ) /* (PDC_AES) PDC Transfer Status Register */ +/* ========== Register definition for AES peripheral ========== */ +#define AT91C_AES_IVxR ( 0xFFFA4060 ) /* (AES) Initialization Vector x Register */ +#define AT91C_AES_MR ( 0xFFFA4004 ) /* (AES) Mode Register */ +#define AT91C_AES_VR ( 0xFFFA40FC ) /* (AES) AES Version Register */ +#define AT91C_AES_ODATAxR ( 0xFFFA4050 ) /* (AES) Output Data x Register */ +#define AT91C_AES_IDATAxR ( 0xFFFA4040 ) /* (AES) Input Data x Register */ +#define AT91C_AES_CR ( 0xFFFA4000 ) /* (AES) Control Register */ +#define AT91C_AES_IDR ( 0xFFFA4014 ) /* (AES) Interrupt Disable Register */ +#define AT91C_AES_IMR ( 0xFFFA4018 ) /* (AES) Interrupt Mask Register */ +#define AT91C_AES_IER ( 0xFFFA4010 ) /* (AES) Interrupt Enable Register */ +#define AT91C_AES_KEYWxR ( 0xFFFA4020 ) /* (AES) Key Word x Register */ +#define AT91C_AES_ISR ( 0xFFFA401C ) /* (AES) Interrupt Status Register */ +/* ========== Register definition for PDC_TDES peripheral ========== */ +#define AT91C_TDES_RNCR ( 0xFFFA8114 ) /* (PDC_TDES) Receive Next Counter Register */ +#define AT91C_TDES_TCR ( 0xFFFA810C ) /* (PDC_TDES) Transmit Counter Register */ +#define AT91C_TDES_RCR ( 0xFFFA8104 ) /* (PDC_TDES) Receive Counter Register */ +#define AT91C_TDES_TNPR ( 0xFFFA8118 ) /* (PDC_TDES) Transmit Next Pointer Register */ +#define AT91C_TDES_RNPR ( 0xFFFA8110 ) /* (PDC_TDES) Receive Next Pointer Register */ +#define AT91C_TDES_RPR ( 0xFFFA8100 ) /* (PDC_TDES) Receive Pointer Register */ +#define AT91C_TDES_TNCR ( 0xFFFA811C ) /* (PDC_TDES) Transmit Next Counter Register */ +#define AT91C_TDES_TPR ( 0xFFFA8108 ) /* (PDC_TDES) Transmit Pointer Register */ +#define AT91C_TDES_PTSR ( 0xFFFA8124 ) /* (PDC_TDES) PDC Transfer Status Register */ +#define AT91C_TDES_PTCR ( 0xFFFA8120 ) /* (PDC_TDES) PDC Transfer Control Register */ +/* ========== Register definition for TDES peripheral ========== */ +#define AT91C_TDES_KEY2WxR ( 0xFFFA8028 ) /* (TDES) Key 2 Word x Register */ +#define AT91C_TDES_KEY3WxR ( 0xFFFA8030 ) /* (TDES) Key 3 Word x Register */ +#define AT91C_TDES_IDR ( 0xFFFA8014 ) /* (TDES) Interrupt Disable Register */ +#define AT91C_TDES_VR ( 0xFFFA80FC ) /* (TDES) TDES Version Register */ +#define AT91C_TDES_IVxR ( 0xFFFA8060 ) /* (TDES) Initialization Vector x Register */ +#define AT91C_TDES_ODATAxR ( 0xFFFA8050 ) /* (TDES) Output Data x Register */ +#define AT91C_TDES_IMR ( 0xFFFA8018 ) /* (TDES) Interrupt Mask Register */ +#define AT91C_TDES_MR ( 0xFFFA8004 ) /* (TDES) Mode Register */ +#define AT91C_TDES_CR ( 0xFFFA8000 ) /* (TDES) Control Register */ +#define AT91C_TDES_IER ( 0xFFFA8010 ) /* (TDES) Interrupt Enable Register */ +#define AT91C_TDES_ISR ( 0xFFFA801C ) /* (TDES) Interrupt Status Register */ +#define AT91C_TDES_IDATAxR ( 0xFFFA8040 ) /* (TDES) Input Data x Register */ +#define AT91C_TDES_KEY1WxR ( 0xFFFA8020 ) /* (TDES) Key 1 Word x Register */ -// ***************************************************************************** -// PIO DEFINITIONS FOR AT91SAM7X256 -// ***************************************************************************** -#define AT91C_PIO_PA0 (1 << 0) // Pin Controlled by PA0 -#define AT91C_PA0_RXD0 (AT91C_PIO_PA0) // USART 0 Receive Data -#define AT91C_PIO_PA1 (1 << 1) // Pin Controlled by PA1 -#define AT91C_PA1_TXD0 (AT91C_PIO_PA1) // USART 0 Transmit Data -#define AT91C_PIO_PA10 (1 << 10) // Pin Controlled by PA10 -#define AT91C_PA10_TWD (AT91C_PIO_PA10) // TWI Two-wire Serial Data -#define AT91C_PIO_PA11 (1 << 11) // Pin Controlled by PA11 -#define AT91C_PA11_TWCK (AT91C_PIO_PA11) // TWI Two-wire Serial Clock -#define AT91C_PIO_PA12 (1 << 12) // Pin Controlled by PA12 -#define AT91C_PA12_NPCS00 (AT91C_PIO_PA12) // SPI 0 Peripheral Chip Select 0 -#define AT91C_PIO_PA13 (1 << 13) // Pin Controlled by PA13 -#define AT91C_PA13_NPCS01 (AT91C_PIO_PA13) // SPI 0 Peripheral Chip Select 1 -#define AT91C_PA13_PCK1 (AT91C_PIO_PA13) // PMC Programmable Clock Output 1 -#define AT91C_PIO_PA14 (1 << 14) // Pin Controlled by PA14 -#define AT91C_PA14_NPCS02 (AT91C_PIO_PA14) // SPI 0 Peripheral Chip Select 2 -#define AT91C_PA14_IRQ1 (AT91C_PIO_PA14) // External Interrupt 1 -#define AT91C_PIO_PA15 (1 << 15) // Pin Controlled by PA15 -#define AT91C_PA15_NPCS03 (AT91C_PIO_PA15) // SPI 0 Peripheral Chip Select 3 -#define AT91C_PA15_TCLK2 (AT91C_PIO_PA15) // Timer Counter 2 external clock input -#define AT91C_PIO_PA16 (1 << 16) // Pin Controlled by PA16 -#define AT91C_PA16_MISO0 (AT91C_PIO_PA16) // SPI 0 Master In Slave -#define AT91C_PIO_PA17 (1 << 17) // Pin Controlled by PA17 -#define AT91C_PA17_MOSI0 (AT91C_PIO_PA17) // SPI 0 Master Out Slave -#define AT91C_PIO_PA18 (1 << 18) // Pin Controlled by PA18 -#define AT91C_PA18_SPCK0 (AT91C_PIO_PA18) // SPI 0 Serial Clock -#define AT91C_PIO_PA19 (1 << 19) // Pin Controlled by PA19 -#define AT91C_PA19_CANRX (AT91C_PIO_PA19) // CAN Receive -#define AT91C_PIO_PA2 (1 << 2) // Pin Controlled by PA2 -#define AT91C_PA2_SCK0 (AT91C_PIO_PA2) // USART 0 Serial Clock -#define AT91C_PA2_NPCS11 (AT91C_PIO_PA2) // SPI 1 Peripheral Chip Select 1 -#define AT91C_PIO_PA20 (1 << 20) // Pin Controlled by PA20 -#define AT91C_PA20_CANTX (AT91C_PIO_PA20) // CAN Transmit -#define AT91C_PIO_PA21 (1 << 21) // Pin Controlled by PA21 -#define AT91C_PA21_TF (AT91C_PIO_PA21) // SSC Transmit Frame Sync -#define AT91C_PA21_NPCS10 (AT91C_PIO_PA21) // SPI 1 Peripheral Chip Select 0 -#define AT91C_PIO_PA22 (1 << 22) // Pin Controlled by PA22 -#define AT91C_PA22_TK (AT91C_PIO_PA22) // SSC Transmit Clock -#define AT91C_PA22_SPCK1 (AT91C_PIO_PA22) // SPI 1 Serial Clock -#define AT91C_PIO_PA23 (1 << 23) // Pin Controlled by PA23 -#define AT91C_PA23_TD (AT91C_PIO_PA23) // SSC Transmit data -#define AT91C_PA23_MOSI1 (AT91C_PIO_PA23) // SPI 1 Master Out Slave -#define AT91C_PIO_PA24 (1 << 24) // Pin Controlled by PA24 -#define AT91C_PA24_RD (AT91C_PIO_PA24) // SSC Receive Data -#define AT91C_PA24_MISO1 (AT91C_PIO_PA24) // SPI 1 Master In Slave -#define AT91C_PIO_PA25 (1 << 25) // Pin Controlled by PA25 -#define AT91C_PA25_RK (AT91C_PIO_PA25) // SSC Receive Clock -#define AT91C_PA25_NPCS11 (AT91C_PIO_PA25) // SPI 1 Peripheral Chip Select 1 -#define AT91C_PIO_PA26 (1 << 26) // Pin Controlled by PA26 -#define AT91C_PA26_RF (AT91C_PIO_PA26) // SSC Receive Frame Sync -#define AT91C_PA26_NPCS12 (AT91C_PIO_PA26) // SPI 1 Peripheral Chip Select 2 -#define AT91C_PIO_PA27 (1 << 27) // Pin Controlled by PA27 -#define AT91C_PA27_DRXD (AT91C_PIO_PA27) // DBGU Debug Receive Data -#define AT91C_PA27_PCK3 (AT91C_PIO_PA27) // PMC Programmable Clock Output 3 -#define AT91C_PIO_PA28 (1 << 28) // Pin Controlled by PA28 -#define AT91C_PA28_DTXD (AT91C_PIO_PA28) // DBGU Debug Transmit Data -#define AT91C_PIO_PA29 (1 << 29) // Pin Controlled by PA29 -#define AT91C_PA29_FIQ (AT91C_PIO_PA29) // AIC Fast Interrupt Input -#define AT91C_PA29_NPCS13 (AT91C_PIO_PA29) // SPI 1 Peripheral Chip Select 3 -#define AT91C_PIO_PA3 (1 << 3) // Pin Controlled by PA3 -#define AT91C_PA3_RTS0 (AT91C_PIO_PA3) // USART 0 Ready To Send -#define AT91C_PA3_NPCS12 (AT91C_PIO_PA3) // SPI 1 Peripheral Chip Select 2 -#define AT91C_PIO_PA30 (1 << 30) // Pin Controlled by PA30 -#define AT91C_PA30_IRQ0 (AT91C_PIO_PA30) // External Interrupt 0 -#define AT91C_PA30_PCK2 (AT91C_PIO_PA30) // PMC Programmable Clock Output 2 -#define AT91C_PIO_PA4 (1 << 4) // Pin Controlled by PA4 -#define AT91C_PA4_CTS0 (AT91C_PIO_PA4) // USART 0 Clear To Send -#define AT91C_PA4_NPCS13 (AT91C_PIO_PA4) // SPI 1 Peripheral Chip Select 3 -#define AT91C_PIO_PA5 (1 << 5) // Pin Controlled by PA5 -#define AT91C_PA5_RXD1 (AT91C_PIO_PA5) // USART 1 Receive Data -#define AT91C_PIO_PA6 (1 << 6) // Pin Controlled by PA6 -#define AT91C_PA6_TXD1 (AT91C_PIO_PA6) // USART 1 Transmit Data -#define AT91C_PIO_PA7 (1 << 7) // Pin Controlled by PA7 -#define AT91C_PA7_SCK1 (AT91C_PIO_PA7) // USART 1 Serial Clock -#define AT91C_PA7_NPCS01 (AT91C_PIO_PA7) // SPI 0 Peripheral Chip Select 1 -#define AT91C_PIO_PA8 (1 << 8) // Pin Controlled by PA8 -#define AT91C_PA8_RTS1 (AT91C_PIO_PA8) // USART 1 Ready To Send -#define AT91C_PA8_NPCS02 (AT91C_PIO_PA8) // SPI 0 Peripheral Chip Select 2 -#define AT91C_PIO_PA9 (1 << 9) // Pin Controlled by PA9 -#define AT91C_PA9_CTS1 (AT91C_PIO_PA9) // USART 1 Clear To Send -#define AT91C_PA9_NPCS03 (AT91C_PIO_PA9) // SPI 0 Peripheral Chip Select 3 -#define AT91C_PIO_PB0 (1 << 0) // Pin Controlled by PB0 -#define AT91C_PB0_ETXCK_EREFCK (AT91C_PIO_PB0) // Ethernet MAC Transmit Clock/Reference Clock -#define AT91C_PB0_PCK0 (AT91C_PIO_PB0) // PMC Programmable Clock Output 0 -#define AT91C_PIO_PB1 (1 << 1) // Pin Controlled by PB1 -#define AT91C_PB1_ETXEN (AT91C_PIO_PB1) // Ethernet MAC Transmit Enable -#define AT91C_PIO_PB10 (1 << 10) // Pin Controlled by PB10 -#define AT91C_PB10_ETX2 (AT91C_PIO_PB10) // Ethernet MAC Transmit Data 2 -#define AT91C_PB10_NPCS11 (AT91C_PIO_PB10) // SPI 1 Peripheral Chip Select 1 -#define AT91C_PIO_PB11 (1 << 11) // Pin Controlled by PB11 -#define AT91C_PB11_ETX3 (AT91C_PIO_PB11) // Ethernet MAC Transmit Data 3 -#define AT91C_PB11_NPCS12 (AT91C_PIO_PB11) // SPI 1 Peripheral Chip Select 2 -#define AT91C_PIO_PB12 (1 << 12) // Pin Controlled by PB12 -#define AT91C_PB12_ETXER (AT91C_PIO_PB12) // Ethernet MAC Transmikt Coding Error -#define AT91C_PB12_TCLK0 (AT91C_PIO_PB12) // Timer Counter 0 external clock input -#define AT91C_PIO_PB13 (1 << 13) // Pin Controlled by PB13 -#define AT91C_PB13_ERX2 (AT91C_PIO_PB13) // Ethernet MAC Receive Data 2 -#define AT91C_PB13_NPCS01 (AT91C_PIO_PB13) // SPI 0 Peripheral Chip Select 1 -#define AT91C_PIO_PB14 (1 << 14) // Pin Controlled by PB14 -#define AT91C_PB14_ERX3 (AT91C_PIO_PB14) // Ethernet MAC Receive Data 3 -#define AT91C_PB14_NPCS02 (AT91C_PIO_PB14) // SPI 0 Peripheral Chip Select 2 -#define AT91C_PIO_PB15 (1 << 15) // Pin Controlled by PB15 -#define AT91C_PB15_ERXDV (AT91C_PIO_PB15) // Ethernet MAC Receive Data Valid -#define AT91C_PIO_PB16 (1 << 16) // Pin Controlled by PB16 -#define AT91C_PB16_ECOL (AT91C_PIO_PB16) // Ethernet MAC Collision Detected -#define AT91C_PB16_NPCS13 (AT91C_PIO_PB16) // SPI 1 Peripheral Chip Select 3 -#define AT91C_PIO_PB17 (1 << 17) // Pin Controlled by PB17 -#define AT91C_PB17_ERXCK (AT91C_PIO_PB17) // Ethernet MAC Receive Clock -#define AT91C_PB17_NPCS03 (AT91C_PIO_PB17) // SPI 0 Peripheral Chip Select 3 -#define AT91C_PIO_PB18 (1 << 18) // Pin Controlled by PB18 -#define AT91C_PB18_EF100 (AT91C_PIO_PB18) // Ethernet MAC Force 100 Mbits/sec -#define AT91C_PB18_ADTRG (AT91C_PIO_PB18) // ADC External Trigger -#define AT91C_PIO_PB19 (1 << 19) // Pin Controlled by PB19 -#define AT91C_PB19_PWM0 (AT91C_PIO_PB19) // PWM Channel 0 -#define AT91C_PB19_TCLK1 (AT91C_PIO_PB19) // Timer Counter 1 external clock input -#define AT91C_PIO_PB2 (1 << 2) // Pin Controlled by PB2 -#define AT91C_PB2_ETX0 (AT91C_PIO_PB2) // Ethernet MAC Transmit Data 0 -#define AT91C_PIO_PB20 (1 << 20) // Pin Controlled by PB20 -#define AT91C_PB20_PWM1 (AT91C_PIO_PB20) // PWM Channel 1 -#define AT91C_PB20_PCK0 (AT91C_PIO_PB20) // PMC Programmable Clock Output 0 -#define AT91C_PIO_PB21 (1 << 21) // Pin Controlled by PB21 -#define AT91C_PB21_PWM2 (AT91C_PIO_PB21) // PWM Channel 2 -#define AT91C_PB21_PCK1 (AT91C_PIO_PB21) // PMC Programmable Clock Output 1 -#define AT91C_PIO_PB22 (1 << 22) // Pin Controlled by PB22 -#define AT91C_PB22_PWM3 (AT91C_PIO_PB22) // PWM Channel 3 -#define AT91C_PB22_PCK2 (AT91C_PIO_PB22) // PMC Programmable Clock Output 2 -#define AT91C_PIO_PB23 (1 << 23) // Pin Controlled by PB23 -#define AT91C_PB23_TIOA0 (AT91C_PIO_PB23) // Timer Counter 0 Multipurpose Timer I/O Pin A -#define AT91C_PB23_DCD1 (AT91C_PIO_PB23) // USART 1 Data Carrier Detect -#define AT91C_PIO_PB24 (1 << 24) // Pin Controlled by PB24 -#define AT91C_PB24_TIOB0 (AT91C_PIO_PB24) // Timer Counter 0 Multipurpose Timer I/O Pin B -#define AT91C_PB24_DSR1 (AT91C_PIO_PB24) // USART 1 Data Set ready -#define AT91C_PIO_PB25 (1 << 25) // Pin Controlled by PB25 -#define AT91C_PB25_TIOA1 (AT91C_PIO_PB25) // Timer Counter 1 Multipurpose Timer I/O Pin A -#define AT91C_PB25_DTR1 (AT91C_PIO_PB25) // USART 1 Data Terminal ready -#define AT91C_PIO_PB26 (1 << 26) // Pin Controlled by PB26 -#define AT91C_PB26_TIOB1 (AT91C_PIO_PB26) // Timer Counter 1 Multipurpose Timer I/O Pin B -#define AT91C_PB26_RI1 (AT91C_PIO_PB26) // USART 1 Ring Indicator -#define AT91C_PIO_PB27 (1 << 27) // Pin Controlled by PB27 -#define AT91C_PB27_TIOA2 (AT91C_PIO_PB27) // Timer Counter 2 Multipurpose Timer I/O Pin A -#define AT91C_PB27_PWM0 (AT91C_PIO_PB27) // PWM Channel 0 -#define AT91C_PIO_PB28 (1 << 28) // Pin Controlled by PB28 -#define AT91C_PB28_TIOB2 (AT91C_PIO_PB28) // Timer Counter 2 Multipurpose Timer I/O Pin B -#define AT91C_PB28_PWM1 (AT91C_PIO_PB28) // PWM Channel 1 -#define AT91C_PIO_PB29 (1 << 29) // Pin Controlled by PB29 -#define AT91C_PB29_PCK1 (AT91C_PIO_PB29) // PMC Programmable Clock Output 1 -#define AT91C_PB29_PWM2 (AT91C_PIO_PB29) // PWM Channel 2 -#define AT91C_PIO_PB3 (1 << 3) // Pin Controlled by PB3 -#define AT91C_PB3_ETX1 (AT91C_PIO_PB3) // Ethernet MAC Transmit Data 1 -#define AT91C_PIO_PB30 (1 << 30) // Pin Controlled by PB30 -#define AT91C_PB30_PCK2 (AT91C_PIO_PB30) // PMC Programmable Clock Output 2 -#define AT91C_PB30_PWM3 (AT91C_PIO_PB30) // PWM Channel 3 -#define AT91C_PIO_PB4 (1 << 4) // Pin Controlled by PB4 -#define AT91C_PB4_ECRS_ECRSDV (AT91C_PIO_PB4) // Ethernet MAC Carrier Sense/Carrier Sense and Data Valid -#define AT91C_PIO_PB5 (1 << 5) // Pin Controlled by PB5 -#define AT91C_PB5_ERX0 (AT91C_PIO_PB5) // Ethernet MAC Receive Data 0 -#define AT91C_PIO_PB6 (1 << 6) // Pin Controlled by PB6 -#define AT91C_PB6_ERX1 (AT91C_PIO_PB6) // Ethernet MAC Receive Data 1 -#define AT91C_PIO_PB7 (1 << 7) // Pin Controlled by PB7 -#define AT91C_PB7_ERXER (AT91C_PIO_PB7) // Ethernet MAC Receive Error -#define AT91C_PIO_PB8 (1 << 8) // Pin Controlled by PB8 -#define AT91C_PB8_EMDC (AT91C_PIO_PB8) // Ethernet MAC Management Data Clock -#define AT91C_PIO_PB9 (1 << 9) // Pin Controlled by PB9 -#define AT91C_PB9_EMDIO (AT91C_PIO_PB9) // Ethernet MAC Management Data Input/Output +/* ***************************************************************************** */ +/* PIO DEFINITIONS FOR AT91SAM7X256 */ +/* ***************************************************************************** */ +#define AT91C_PIO_PA0 ( 1 << 0 ) /* Pin Controlled by PA0 */ +#define AT91C_PA0_RXD0 ( AT91C_PIO_PA0 ) /* USART 0 Receive Data */ +#define AT91C_PIO_PA1 ( 1 << 1 ) /* Pin Controlled by PA1 */ +#define AT91C_PA1_TXD0 ( AT91C_PIO_PA1 ) /* USART 0 Transmit Data */ +#define AT91C_PIO_PA10 ( 1 << 10 ) /* Pin Controlled by PA10 */ +#define AT91C_PA10_TWD ( AT91C_PIO_PA10 ) /* TWI Two-wire Serial Data */ +#define AT91C_PIO_PA11 ( 1 << 11 ) /* Pin Controlled by PA11 */ +#define AT91C_PA11_TWCK ( AT91C_PIO_PA11 ) /* TWI Two-wire Serial Clock */ +#define AT91C_PIO_PA12 ( 1 << 12 ) /* Pin Controlled by PA12 */ +#define AT91C_PA12_NPCS00 ( AT91C_PIO_PA12 ) /* SPI 0 Peripheral Chip Select 0 */ +#define AT91C_PIO_PA13 ( 1 << 13 ) /* Pin Controlled by PA13 */ +#define AT91C_PA13_NPCS01 ( AT91C_PIO_PA13 ) /* SPI 0 Peripheral Chip Select 1 */ +#define AT91C_PA13_PCK1 ( AT91C_PIO_PA13 ) /* PMC Programmable Clock Output 1 */ +#define AT91C_PIO_PA14 ( 1 << 14 ) /* Pin Controlled by PA14 */ +#define AT91C_PA14_NPCS02 ( AT91C_PIO_PA14 ) /* SPI 0 Peripheral Chip Select 2 */ +#define AT91C_PA14_IRQ1 ( AT91C_PIO_PA14 ) /* External Interrupt 1 */ +#define AT91C_PIO_PA15 ( 1 << 15 ) /* Pin Controlled by PA15 */ +#define AT91C_PA15_NPCS03 ( AT91C_PIO_PA15 ) /* SPI 0 Peripheral Chip Select 3 */ +#define AT91C_PA15_TCLK2 ( AT91C_PIO_PA15 ) /* Timer Counter 2 external clock input */ +#define AT91C_PIO_PA16 ( 1 << 16 ) /* Pin Controlled by PA16 */ +#define AT91C_PA16_MISO0 ( AT91C_PIO_PA16 ) /* SPI 0 Master In Slave */ +#define AT91C_PIO_PA17 ( 1 << 17 ) /* Pin Controlled by PA17 */ +#define AT91C_PA17_MOSI0 ( AT91C_PIO_PA17 ) /* SPI 0 Master Out Slave */ +#define AT91C_PIO_PA18 ( 1 << 18 ) /* Pin Controlled by PA18 */ +#define AT91C_PA18_SPCK0 ( AT91C_PIO_PA18 ) /* SPI 0 Serial Clock */ +#define AT91C_PIO_PA19 ( 1 << 19 ) /* Pin Controlled by PA19 */ +#define AT91C_PA19_CANRX ( AT91C_PIO_PA19 ) /* CAN Receive */ +#define AT91C_PIO_PA2 ( 1 << 2 ) /* Pin Controlled by PA2 */ +#define AT91C_PA2_SCK0 ( AT91C_PIO_PA2 ) /* USART 0 Serial Clock */ +#define AT91C_PA2_NPCS11 ( AT91C_PIO_PA2 ) /* SPI 1 Peripheral Chip Select 1 */ +#define AT91C_PIO_PA20 ( 1 << 20 ) /* Pin Controlled by PA20 */ +#define AT91C_PA20_CANTX ( AT91C_PIO_PA20 ) /* CAN Transmit */ +#define AT91C_PIO_PA21 ( 1 << 21 ) /* Pin Controlled by PA21 */ +#define AT91C_PA21_TF ( AT91C_PIO_PA21 ) /* SSC Transmit Frame Sync */ +#define AT91C_PA21_NPCS10 ( AT91C_PIO_PA21 ) /* SPI 1 Peripheral Chip Select 0 */ +#define AT91C_PIO_PA22 ( 1 << 22 ) /* Pin Controlled by PA22 */ +#define AT91C_PA22_TK ( AT91C_PIO_PA22 ) /* SSC Transmit Clock */ +#define AT91C_PA22_SPCK1 ( AT91C_PIO_PA22 ) /* SPI 1 Serial Clock */ +#define AT91C_PIO_PA23 ( 1 << 23 ) /* Pin Controlled by PA23 */ +#define AT91C_PA23_TD ( AT91C_PIO_PA23 ) /* SSC Transmit data */ +#define AT91C_PA23_MOSI1 ( AT91C_PIO_PA23 ) /* SPI 1 Master Out Slave */ +#define AT91C_PIO_PA24 ( 1 << 24 ) /* Pin Controlled by PA24 */ +#define AT91C_PA24_RD ( AT91C_PIO_PA24 ) /* SSC Receive Data */ +#define AT91C_PA24_MISO1 ( AT91C_PIO_PA24 ) /* SPI 1 Master In Slave */ +#define AT91C_PIO_PA25 ( 1 << 25 ) /* Pin Controlled by PA25 */ +#define AT91C_PA25_RK ( AT91C_PIO_PA25 ) /* SSC Receive Clock */ +#define AT91C_PA25_NPCS11 ( AT91C_PIO_PA25 ) /* SPI 1 Peripheral Chip Select 1 */ +#define AT91C_PIO_PA26 ( 1 << 26 ) /* Pin Controlled by PA26 */ +#define AT91C_PA26_RF ( AT91C_PIO_PA26 ) /* SSC Receive Frame Sync */ +#define AT91C_PA26_NPCS12 ( AT91C_PIO_PA26 ) /* SPI 1 Peripheral Chip Select 2 */ +#define AT91C_PIO_PA27 ( 1 << 27 ) /* Pin Controlled by PA27 */ +#define AT91C_PA27_DRXD ( AT91C_PIO_PA27 ) /* DBGU Debug Receive Data */ +#define AT91C_PA27_PCK3 ( AT91C_PIO_PA27 ) /* PMC Programmable Clock Output 3 */ +#define AT91C_PIO_PA28 ( 1 << 28 ) /* Pin Controlled by PA28 */ +#define AT91C_PA28_DTXD ( AT91C_PIO_PA28 ) /* DBGU Debug Transmit Data */ +#define AT91C_PIO_PA29 ( 1 << 29 ) /* Pin Controlled by PA29 */ +#define AT91C_PA29_FIQ ( AT91C_PIO_PA29 ) /* AIC Fast Interrupt Input */ +#define AT91C_PA29_NPCS13 ( AT91C_PIO_PA29 ) /* SPI 1 Peripheral Chip Select 3 */ +#define AT91C_PIO_PA3 ( 1 << 3 ) /* Pin Controlled by PA3 */ +#define AT91C_PA3_RTS0 ( AT91C_PIO_PA3 ) /* USART 0 Ready To Send */ +#define AT91C_PA3_NPCS12 ( AT91C_PIO_PA3 ) /* SPI 1 Peripheral Chip Select 2 */ +#define AT91C_PIO_PA30 ( 1 << 30 ) /* Pin Controlled by PA30 */ +#define AT91C_PA30_IRQ0 ( AT91C_PIO_PA30 ) /* External Interrupt 0 */ +#define AT91C_PA30_PCK2 ( AT91C_PIO_PA30 ) /* PMC Programmable Clock Output 2 */ +#define AT91C_PIO_PA4 ( 1 << 4 ) /* Pin Controlled by PA4 */ +#define AT91C_PA4_CTS0 ( AT91C_PIO_PA4 ) /* USART 0 Clear To Send */ +#define AT91C_PA4_NPCS13 ( AT91C_PIO_PA4 ) /* SPI 1 Peripheral Chip Select 3 */ +#define AT91C_PIO_PA5 ( 1 << 5 ) /* Pin Controlled by PA5 */ +#define AT91C_PA5_RXD1 ( AT91C_PIO_PA5 ) /* USART 1 Receive Data */ +#define AT91C_PIO_PA6 ( 1 << 6 ) /* Pin Controlled by PA6 */ +#define AT91C_PA6_TXD1 ( AT91C_PIO_PA6 ) /* USART 1 Transmit Data */ +#define AT91C_PIO_PA7 ( 1 << 7 ) /* Pin Controlled by PA7 */ +#define AT91C_PA7_SCK1 ( AT91C_PIO_PA7 ) /* USART 1 Serial Clock */ +#define AT91C_PA7_NPCS01 ( AT91C_PIO_PA7 ) /* SPI 0 Peripheral Chip Select 1 */ +#define AT91C_PIO_PA8 ( 1 << 8 ) /* Pin Controlled by PA8 */ +#define AT91C_PA8_RTS1 ( AT91C_PIO_PA8 ) /* USART 1 Ready To Send */ +#define AT91C_PA8_NPCS02 ( AT91C_PIO_PA8 ) /* SPI 0 Peripheral Chip Select 2 */ +#define AT91C_PIO_PA9 ( 1 << 9 ) /* Pin Controlled by PA9 */ +#define AT91C_PA9_CTS1 ( AT91C_PIO_PA9 ) /* USART 1 Clear To Send */ +#define AT91C_PA9_NPCS03 ( AT91C_PIO_PA9 ) /* SPI 0 Peripheral Chip Select 3 */ +#define AT91C_PIO_PB0 ( 1 << 0 ) /* Pin Controlled by PB0 */ +#define AT91C_PB0_ETXCK_EREFCK ( AT91C_PIO_PB0 ) /* Ethernet MAC Transmit Clock/Reference Clock */ +#define AT91C_PB0_PCK0 ( AT91C_PIO_PB0 ) /* PMC Programmable Clock Output 0 */ +#define AT91C_PIO_PB1 ( 1 << 1 ) /* Pin Controlled by PB1 */ +#define AT91C_PB1_ETXEN ( AT91C_PIO_PB1 ) /* Ethernet MAC Transmit Enable */ +#define AT91C_PIO_PB10 ( 1 << 10 ) /* Pin Controlled by PB10 */ +#define AT91C_PB10_ETX2 ( AT91C_PIO_PB10 ) /* Ethernet MAC Transmit Data 2 */ +#define AT91C_PB10_NPCS11 ( AT91C_PIO_PB10 ) /* SPI 1 Peripheral Chip Select 1 */ +#define AT91C_PIO_PB11 ( 1 << 11 ) /* Pin Controlled by PB11 */ +#define AT91C_PB11_ETX3 ( AT91C_PIO_PB11 ) /* Ethernet MAC Transmit Data 3 */ +#define AT91C_PB11_NPCS12 ( AT91C_PIO_PB11 ) /* SPI 1 Peripheral Chip Select 2 */ +#define AT91C_PIO_PB12 ( 1 << 12 ) /* Pin Controlled by PB12 */ +#define AT91C_PB12_ETXER ( AT91C_PIO_PB12 ) /* Ethernet MAC Transmit Coding Error */ +#define AT91C_PB12_TCLK0 ( AT91C_PIO_PB12 ) /* Timer Counter 0 external clock input */ +#define AT91C_PIO_PB13 ( 1 << 13 ) /* Pin Controlled by PB13 */ +#define AT91C_PB13_ERX2 ( AT91C_PIO_PB13 ) /* Ethernet MAC Receive Data 2 */ +#define AT91C_PB13_NPCS01 ( AT91C_PIO_PB13 ) /* SPI 0 Peripheral Chip Select 1 */ +#define AT91C_PIO_PB14 ( 1 << 14 ) /* Pin Controlled by PB14 */ +#define AT91C_PB14_ERX3 ( AT91C_PIO_PB14 ) /* Ethernet MAC Receive Data 3 */ +#define AT91C_PB14_NPCS02 ( AT91C_PIO_PB14 ) /* SPI 0 Peripheral Chip Select 2 */ +#define AT91C_PIO_PB15 ( 1 << 15 ) /* Pin Controlled by PB15 */ +#define AT91C_PB15_ERXDV ( AT91C_PIO_PB15 ) /* Ethernet MAC Receive Data Valid */ +#define AT91C_PIO_PB16 ( 1 << 16 ) /* Pin Controlled by PB16 */ +#define AT91C_PB16_ECOL ( AT91C_PIO_PB16 ) /* Ethernet MAC Collision Detected */ +#define AT91C_PB16_NPCS13 ( AT91C_PIO_PB16 ) /* SPI 1 Peripheral Chip Select 3 */ +#define AT91C_PIO_PB17 ( 1 << 17 ) /* Pin Controlled by PB17 */ +#define AT91C_PB17_ERXCK ( AT91C_PIO_PB17 ) /* Ethernet MAC Receive Clock */ +#define AT91C_PB17_NPCS03 ( AT91C_PIO_PB17 ) /* SPI 0 Peripheral Chip Select 3 */ +#define AT91C_PIO_PB18 ( 1 << 18 ) /* Pin Controlled by PB18 */ +#define AT91C_PB18_EF100 ( AT91C_PIO_PB18 ) /* Ethernet MAC Force 100 Mbits/sec */ +#define AT91C_PB18_ADTRG ( AT91C_PIO_PB18 ) /* ADC External Trigger */ +#define AT91C_PIO_PB19 ( 1 << 19 ) /* Pin Controlled by PB19 */ +#define AT91C_PB19_PWM0 ( AT91C_PIO_PB19 ) /* PWM Channel 0 */ +#define AT91C_PB19_TCLK1 ( AT91C_PIO_PB19 ) /* Timer Counter 1 external clock input */ +#define AT91C_PIO_PB2 ( 1 << 2 ) /* Pin Controlled by PB2 */ +#define AT91C_PB2_ETX0 ( AT91C_PIO_PB2 ) /* Ethernet MAC Transmit Data 0 */ +#define AT91C_PIO_PB20 ( 1 << 20 ) /* Pin Controlled by PB20 */ +#define AT91C_PB20_PWM1 ( AT91C_PIO_PB20 ) /* PWM Channel 1 */ +#define AT91C_PB20_PCK0 ( AT91C_PIO_PB20 ) /* PMC Programmable Clock Output 0 */ +#define AT91C_PIO_PB21 ( 1 << 21 ) /* Pin Controlled by PB21 */ +#define AT91C_PB21_PWM2 ( AT91C_PIO_PB21 ) /* PWM Channel 2 */ +#define AT91C_PB21_PCK1 ( AT91C_PIO_PB21 ) /* PMC Programmable Clock Output 1 */ +#define AT91C_PIO_PB22 ( 1 << 22 ) /* Pin Controlled by PB22 */ +#define AT91C_PB22_PWM3 ( AT91C_PIO_PB22 ) /* PWM Channel 3 */ +#define AT91C_PB22_PCK2 ( AT91C_PIO_PB22 ) /* PMC Programmable Clock Output 2 */ +#define AT91C_PIO_PB23 ( 1 << 23 ) /* Pin Controlled by PB23 */ +#define AT91C_PB23_TIOA0 ( AT91C_PIO_PB23 ) /* Timer Counter 0 Multipurpose Timer I/O Pin A */ +#define AT91C_PB23_DCD1 ( AT91C_PIO_PB23 ) /* USART 1 Data Carrier Detect */ +#define AT91C_PIO_PB24 ( 1 << 24 ) /* Pin Controlled by PB24 */ +#define AT91C_PB24_TIOB0 ( AT91C_PIO_PB24 ) /* Timer Counter 0 Multipurpose Timer I/O Pin B */ +#define AT91C_PB24_DSR1 ( AT91C_PIO_PB24 ) /* USART 1 Data Set ready */ +#define AT91C_PIO_PB25 ( 1 << 25 ) /* Pin Controlled by PB25 */ +#define AT91C_PB25_TIOA1 ( AT91C_PIO_PB25 ) /* Timer Counter 1 Multipurpose Timer I/O Pin A */ +#define AT91C_PB25_DTR1 ( AT91C_PIO_PB25 ) /* USART 1 Data Terminal ready */ +#define AT91C_PIO_PB26 ( 1 << 26 ) /* Pin Controlled by PB26 */ +#define AT91C_PB26_TIOB1 ( AT91C_PIO_PB26 ) /* Timer Counter 1 Multipurpose Timer I/O Pin B */ +#define AT91C_PB26_RI1 ( AT91C_PIO_PB26 ) /* USART 1 Ring Indicator */ +#define AT91C_PIO_PB27 ( 1 << 27 ) /* Pin Controlled by PB27 */ +#define AT91C_PB27_TIOA2 ( AT91C_PIO_PB27 ) /* Timer Counter 2 Multipurpose Timer I/O Pin A */ +#define AT91C_PB27_PWM0 ( AT91C_PIO_PB27 ) /* PWM Channel 0 */ +#define AT91C_PIO_PB28 ( 1 << 28 ) /* Pin Controlled by PB28 */ +#define AT91C_PB28_TIOB2 ( AT91C_PIO_PB28 ) /* Timer Counter 2 Multipurpose Timer I/O Pin B */ +#define AT91C_PB28_PWM1 ( AT91C_PIO_PB28 ) /* PWM Channel 1 */ +#define AT91C_PIO_PB29 ( 1 << 29 ) /* Pin Controlled by PB29 */ +#define AT91C_PB29_PCK1 ( AT91C_PIO_PB29 ) /* PMC Programmable Clock Output 1 */ +#define AT91C_PB29_PWM2 ( AT91C_PIO_PB29 ) /* PWM Channel 2 */ +#define AT91C_PIO_PB3 ( 1 << 3 ) /* Pin Controlled by PB3 */ +#define AT91C_PB3_ETX1 ( AT91C_PIO_PB3 ) /* Ethernet MAC Transmit Data 1 */ +#define AT91C_PIO_PB30 ( 1 << 30 ) /* Pin Controlled by PB30 */ +#define AT91C_PB30_PCK2 ( AT91C_PIO_PB30 ) /* PMC Programmable Clock Output 2 */ +#define AT91C_PB30_PWM3 ( AT91C_PIO_PB30 ) /* PWM Channel 3 */ +#define AT91C_PIO_PB4 ( 1 << 4 ) /* Pin Controlled by PB4 */ +#define AT91C_PB4_ECRS_ECRSDV ( AT91C_PIO_PB4 ) /* Ethernet MAC Carrier Sense/Carrier Sense and Data Valid */ +#define AT91C_PIO_PB5 ( 1 << 5 ) /* Pin Controlled by PB5 */ +#define AT91C_PB5_ERX0 ( AT91C_PIO_PB5 ) /* Ethernet MAC Receive Data 0 */ +#define AT91C_PIO_PB6 ( 1 << 6 ) /* Pin Controlled by PB6 */ +#define AT91C_PB6_ERX1 ( AT91C_PIO_PB6 ) /* Ethernet MAC Receive Data 1 */ +#define AT91C_PIO_PB7 ( 1 << 7 ) /* Pin Controlled by PB7 */ +#define AT91C_PB7_ERXER ( AT91C_PIO_PB7 ) /* Ethernet MAC Receive Error */ +#define AT91C_PIO_PB8 ( 1 << 8 ) /* Pin Controlled by PB8 */ +#define AT91C_PB8_EMDC ( AT91C_PIO_PB8 ) /* Ethernet MAC Management Data Clock */ +#define AT91C_PIO_PB9 ( 1 << 9 ) /* Pin Controlled by PB9 */ +#define AT91C_PB9_EMDIO ( AT91C_PIO_PB9 ) /* Ethernet MAC Management Data Input/Output */ -// ***************************************************************************** -// PERIPHERAL ID DEFINITIONS FOR AT91SAM7X256 -// ***************************************************************************** -#define AT91C_ID_FIQ ( 0) // Advanced Interrupt Controller (FIQ) -#define AT91C_ID_SYS ( 1) // System Peripheral -#define AT91C_ID_PIOA ( 2) // Parallel IO Controller A -#define AT91C_ID_PIOB ( 3) // Parallel IO Controller B -#define AT91C_ID_SPI0 ( 4) // Serial Peripheral Interface 0 -#define AT91C_ID_SPI1 ( 5) // Serial Peripheral Interface 1 -#define AT91C_ID_US0 ( 6) // USART 0 -#define AT91C_ID_US1 ( 7) // USART 1 -#define AT91C_ID_SSC ( 8) // Serial Synchronous Controller -#define AT91C_ID_TWI ( 9) // Two-Wire Interface -#define AT91C_ID_PWMC (10) // PWM Controller -#define AT91C_ID_UDP (11) // USB Device Port -#define AT91C_ID_TC0 (12) // Timer Counter 0 -#define AT91C_ID_TC1 (13) // Timer Counter 1 -#define AT91C_ID_TC2 (14) // Timer Counter 2 -#define AT91C_ID_CAN (15) // Control Area Network Controller -#define AT91C_ID_EMAC (16) // Ethernet MAC -#define AT91C_ID_ADC (17) // Analog-to-Digital Converter -#define AT91C_ID_AES (18) // Advanced Encryption Standard 128-bit -#define AT91C_ID_TDES (19) // Triple Data Encryption Standard -#define AT91C_ID_20_Reserved (20) // Reserved -#define AT91C_ID_21_Reserved (21) // Reserved -#define AT91C_ID_22_Reserved (22) // Reserved -#define AT91C_ID_23_Reserved (23) // Reserved -#define AT91C_ID_24_Reserved (24) // Reserved -#define AT91C_ID_25_Reserved (25) // Reserved -#define AT91C_ID_26_Reserved (26) // Reserved -#define AT91C_ID_27_Reserved (27) // Reserved -#define AT91C_ID_28_Reserved (28) // Reserved -#define AT91C_ID_29_Reserved (29) // Reserved -#define AT91C_ID_IRQ0 (30) // Advanced Interrupt Controller (IRQ0) -#define AT91C_ID_IRQ1 (31) // Advanced Interrupt Controller (IRQ1) +/* ***************************************************************************** */ +/* PERIPHERAL ID DEFINITIONS FOR AT91SAM7X256 */ +/* ***************************************************************************** */ +#define AT91C_ID_FIQ ( 0 ) /* Advanced Interrupt Controller (FIQ) */ +#define AT91C_ID_SYS ( 1 ) /* System Peripheral */ +#define AT91C_ID_PIOA ( 2 ) /* Parallel IO Controller A */ +#define AT91C_ID_PIOB ( 3 ) /* Parallel IO Controller B */ +#define AT91C_ID_SPI0 ( 4 ) /* Serial Peripheral Interface 0 */ +#define AT91C_ID_SPI1 ( 5 ) /* Serial Peripheral Interface 1 */ +#define AT91C_ID_US0 ( 6 ) /* USART 0 */ +#define AT91C_ID_US1 ( 7 ) /* USART 1 */ +#define AT91C_ID_SSC ( 8 ) /* Serial Synchronous Controller */ +#define AT91C_ID_TWI ( 9 ) /* Two-Wire Interface */ +#define AT91C_ID_PWMC ( 10 ) /* PWM Controller */ +#define AT91C_ID_UDP ( 11 ) /* USB Device Port */ +#define AT91C_ID_TC0 ( 12 ) /* Timer Counter 0 */ +#define AT91C_ID_TC1 ( 13 ) /* Timer Counter 1 */ +#define AT91C_ID_TC2 ( 14 ) /* Timer Counter 2 */ +#define AT91C_ID_CAN ( 15 ) /* Control Area Network Controller */ +#define AT91C_ID_EMAC ( 16 ) /* Ethernet MAC */ +#define AT91C_ID_ADC ( 17 ) /* Analog-to-Digital Converter */ +#define AT91C_ID_AES ( 18 ) /* Advanced Encryption Standard 128-bit */ +#define AT91C_ID_TDES ( 19 ) /* Triple Data Encryption Standard */ +#define AT91C_ID_20_Reserved ( 20 ) /* Reserved */ +#define AT91C_ID_21_Reserved ( 21 ) /* Reserved */ +#define AT91C_ID_22_Reserved ( 22 ) /* Reserved */ +#define AT91C_ID_23_Reserved ( 23 ) /* Reserved */ +#define AT91C_ID_24_Reserved ( 24 ) /* Reserved */ +#define AT91C_ID_25_Reserved ( 25 ) /* Reserved */ +#define AT91C_ID_26_Reserved ( 26 ) /* Reserved */ +#define AT91C_ID_27_Reserved ( 27 ) /* Reserved */ +#define AT91C_ID_28_Reserved ( 28 ) /* Reserved */ +#define AT91C_ID_29_Reserved ( 29 ) /* Reserved */ +#define AT91C_ID_IRQ0 ( 30 ) /* Advanced Interrupt Controller (IRQ0) */ +#define AT91C_ID_IRQ1 ( 31 ) /* Advanced Interrupt Controller (IRQ1) */ -// ***************************************************************************** -// BASE ADDRESS DEFINITIONS FOR AT91SAM7X256 -// ***************************************************************************** -#define AT91C_BASE_SYS (0xFFFFF000) // (SYS) Base Address -#define AT91C_BASE_AIC (0xFFFFF000) // (AIC) Base Address -#define AT91C_BASE_PDC_DBGU (0xFFFFF300) // (PDC_DBGU) Base Address -#define AT91C_BASE_DBGU (0xFFFFF200) // (DBGU) Base Address -#define AT91C_BASE_PIOA (0xFFFFF400) // (PIOA) Base Address -#define AT91C_BASE_PIOB (0xFFFFF600) // (PIOB) Base Address -#define AT91C_BASE_CKGR (0xFFFFFC20) // (CKGR) Base Address -#define AT91C_BASE_PMC (0xFFFFFC00) // (PMC) Base Address -#define AT91C_BASE_RSTC (0xFFFFFD00) // (RSTC) Base Address -#define AT91C_BASE_RTTC (0xFFFFFD20) // (RTTC) Base Address -#define AT91C_BASE_PITC (0xFFFFFD30) // (PITC) Base Address -#define AT91C_BASE_WDTC (0xFFFFFD40) // (WDTC) Base Address -#define AT91C_BASE_VREG (0xFFFFFD60) // (VREG) Base Address -#define AT91C_BASE_MC (0xFFFFFF00) // (MC) Base Address -#define AT91C_BASE_PDC_SPI1 (0xFFFE4100) // (PDC_SPI1) Base Address -#define AT91C_BASE_SPI1 (0xFFFE4000) // (SPI1) Base Address -#define AT91C_BASE_PDC_SPI0 (0xFFFE0100) // (PDC_SPI0) Base Address -#define AT91C_BASE_SPI0 (0xFFFE0000) // (SPI0) Base Address -#define AT91C_BASE_PDC_US1 (0xFFFC4100) // (PDC_US1) Base Address -#define AT91C_BASE_US1 (0xFFFC4000) // (US1) Base Address -#define AT91C_BASE_PDC_US0 (0xFFFC0100) // (PDC_US0) Base Address -#define AT91C_BASE_US0 (0xFFFC0000) // (US0) Base Address -#define AT91C_BASE_PDC_SSC (0xFFFD4100) // (PDC_SSC) Base Address -#define AT91C_BASE_SSC (0xFFFD4000) // (SSC) Base Address -#define AT91C_BASE_TWI (0xFFFB8000) // (TWI) Base Address -#define AT91C_BASE_PWMC_CH3 (0xFFFCC260) // (PWMC_CH3) Base Address -#define AT91C_BASE_PWMC_CH2 (0xFFFCC240) // (PWMC_CH2) Base Address -#define AT91C_BASE_PWMC_CH1 (0xFFFCC220) // (PWMC_CH1) Base Address -#define AT91C_BASE_PWMC_CH0 (0xFFFCC200) // (PWMC_CH0) Base Address -#define AT91C_BASE_PWMC (0xFFFCC000) // (PWMC) Base Address -#define AT91C_BASE_UDP (0xFFFB0000) // (UDP) Base Address -#define AT91C_BASE_TC0 (0xFFFA0000) // (TC0) Base Address -#define AT91C_BASE_TC1 (0xFFFA0040) // (TC1) Base Address -#define AT91C_BASE_TC2 (0xFFFA0080) // (TC2) Base Address -#define AT91C_BASE_TCB (0xFFFA0000) // (TCB) Base Address -#define AT91C_BASE_CAN_MB0 (0xFFFD0200) // (CAN_MB0) Base Address -#define AT91C_BASE_CAN_MB1 (0xFFFD0220) // (CAN_MB1) Base Address -#define AT91C_BASE_CAN_MB2 (0xFFFD0240) // (CAN_MB2) Base Address -#define AT91C_BASE_CAN_MB3 (0xFFFD0260) // (CAN_MB3) Base Address -#define AT91C_BASE_CAN_MB4 (0xFFFD0280) // (CAN_MB4) Base Address -#define AT91C_BASE_CAN_MB5 (0xFFFD02A0) // (CAN_MB5) Base Address -#define AT91C_BASE_CAN_MB6 (0xFFFD02C0) // (CAN_MB6) Base Address -#define AT91C_BASE_CAN_MB7 (0xFFFD02E0) // (CAN_MB7) Base Address -#define AT91C_BASE_CAN (0xFFFD0000) // (CAN) Base Address -#define AT91C_BASE_EMAC (0xFFFDC000) // (EMAC) Base Address -#define AT91C_BASE_PDC_ADC (0xFFFD8100) // (PDC_ADC) Base Address -#define AT91C_BASE_ADC (0xFFFD8000) // (ADC) Base Address -#define AT91C_BASE_PDC_AES (0xFFFA4100) // (PDC_AES) Base Address -#define AT91C_BASE_AES (0xFFFA4000) // (AES) Base Address -#define AT91C_BASE_PDC_TDES (0xFFFA8100) // (PDC_TDES) Base Address -#define AT91C_BASE_TDES (0xFFFA8000) // (TDES) Base Address +/* ***************************************************************************** */ +/* BASE ADDRESS DEFINITIONS FOR AT91SAM7X256 */ +/* ***************************************************************************** */ +#define AT91C_BASE_SYS ( 0xFFFFF000 ) /* (SYS) Base Address */ +#define AT91C_BASE_AIC ( 0xFFFFF000 ) /* (AIC) Base Address */ +#define AT91C_BASE_PDC_DBGU ( 0xFFFFF300 ) /* (PDC_DBGU) Base Address */ +#define AT91C_BASE_DBGU ( 0xFFFFF200 ) /* (DBGU) Base Address */ +#define AT91C_BASE_PIOA ( 0xFFFFF400 ) /* (PIOA) Base Address */ +#define AT91C_BASE_PIOB ( 0xFFFFF600 ) /* (PIOB) Base Address */ +#define AT91C_BASE_CKGR ( 0xFFFFFC20 ) /* (CKGR) Base Address */ +#define AT91C_BASE_PMC ( 0xFFFFFC00 ) /* (PMC) Base Address */ +#define AT91C_BASE_RSTC ( 0xFFFFFD00 ) /* (RSTC) Base Address */ +#define AT91C_BASE_RTTC ( 0xFFFFFD20 ) /* (RTTC) Base Address */ +#define AT91C_BASE_PITC ( 0xFFFFFD30 ) /* (PITC) Base Address */ +#define AT91C_BASE_WDTC ( 0xFFFFFD40 ) /* (WDTC) Base Address */ +#define AT91C_BASE_VREG ( 0xFFFFFD60 ) /* (VREG) Base Address */ +#define AT91C_BASE_MC ( 0xFFFFFF00 ) /* (MC) Base Address */ +#define AT91C_BASE_PDC_SPI1 ( 0xFFFE4100 ) /* (PDC_SPI1) Base Address */ +#define AT91C_BASE_SPI1 ( 0xFFFE4000 ) /* (SPI1) Base Address */ +#define AT91C_BASE_PDC_SPI0 ( 0xFFFE0100 ) /* (PDC_SPI0) Base Address */ +#define AT91C_BASE_SPI0 ( 0xFFFE0000 ) /* (SPI0) Base Address */ +#define AT91C_BASE_PDC_US1 ( 0xFFFC4100 ) /* (PDC_US1) Base Address */ +#define AT91C_BASE_US1 ( 0xFFFC4000 ) /* (US1) Base Address */ +#define AT91C_BASE_PDC_US0 ( 0xFFFC0100 ) /* (PDC_US0) Base Address */ +#define AT91C_BASE_US0 ( 0xFFFC0000 ) /* (US0) Base Address */ +#define AT91C_BASE_PDC_SSC ( 0xFFFD4100 ) /* (PDC_SSC) Base Address */ +#define AT91C_BASE_SSC ( 0xFFFD4000 ) /* (SSC) Base Address */ +#define AT91C_BASE_TWI ( 0xFFFB8000 ) /* (TWI) Base Address */ +#define AT91C_BASE_PWMC_CH3 ( 0xFFFCC260 ) /* (PWMC_CH3) Base Address */ +#define AT91C_BASE_PWMC_CH2 ( 0xFFFCC240 ) /* (PWMC_CH2) Base Address */ +#define AT91C_BASE_PWMC_CH1 ( 0xFFFCC220 ) /* (PWMC_CH1) Base Address */ +#define AT91C_BASE_PWMC_CH0 ( 0xFFFCC200 ) /* (PWMC_CH0) Base Address */ +#define AT91C_BASE_PWMC ( 0xFFFCC000 ) /* (PWMC) Base Address */ +#define AT91C_BASE_UDP ( 0xFFFB0000 ) /* (UDP) Base Address */ +#define AT91C_BASE_TC0 ( 0xFFFA0000 ) /* (TC0) Base Address */ +#define AT91C_BASE_TC1 ( 0xFFFA0040 ) /* (TC1) Base Address */ +#define AT91C_BASE_TC2 ( 0xFFFA0080 ) /* (TC2) Base Address */ +#define AT91C_BASE_TCB ( 0xFFFA0000 ) /* (TCB) Base Address */ +#define AT91C_BASE_CAN_MB0 ( 0xFFFD0200 ) /* (CAN_MB0) Base Address */ +#define AT91C_BASE_CAN_MB1 ( 0xFFFD0220 ) /* (CAN_MB1) Base Address */ +#define AT91C_BASE_CAN_MB2 ( 0xFFFD0240 ) /* (CAN_MB2) Base Address */ +#define AT91C_BASE_CAN_MB3 ( 0xFFFD0260 ) /* (CAN_MB3) Base Address */ +#define AT91C_BASE_CAN_MB4 ( 0xFFFD0280 ) /* (CAN_MB4) Base Address */ +#define AT91C_BASE_CAN_MB5 ( 0xFFFD02A0 ) /* (CAN_MB5) Base Address */ +#define AT91C_BASE_CAN_MB6 ( 0xFFFD02C0 ) /* (CAN_MB6) Base Address */ +#define AT91C_BASE_CAN_MB7 ( 0xFFFD02E0 ) /* (CAN_MB7) Base Address */ +#define AT91C_BASE_CAN ( 0xFFFD0000 ) /* (CAN) Base Address */ +#define AT91C_BASE_EMAC ( 0xFFFDC000 ) /* (EMAC) Base Address */ +#define AT91C_BASE_PDC_ADC ( 0xFFFD8100 ) /* (PDC_ADC) Base Address */ +#define AT91C_BASE_ADC ( 0xFFFD8000 ) /* (ADC) Base Address */ +#define AT91C_BASE_PDC_AES ( 0xFFFA4100 ) /* (PDC_AES) Base Address */ +#define AT91C_BASE_AES ( 0xFFFA4000 ) /* (AES) Base Address */ +#define AT91C_BASE_PDC_TDES ( 0xFFFA8100 ) /* (PDC_TDES) Base Address */ +#define AT91C_BASE_TDES ( 0xFFFA8000 ) /* (TDES) Base Address */ -// ***************************************************************************** -// MEMORY MAPPING DEFINITIONS FOR AT91SAM7X256 -// ***************************************************************************** -#define AT91C_ISRAM (0x00200000) // Internal SRAM base address -#define AT91C_ISRAM_SIZE (0x00010000) // Internal SRAM size in byte (64 Kbyte) -#define AT91C_IFLASH (0x00100000) // Internal ROM base address -#define AT91C_IFLASH_SIZE (0x00040000) // Internal ROM size in byte (256 Kbyte) +/* ***************************************************************************** */ +/* MEMORY MAPPING DEFINITIONS FOR AT91SAM7X256 */ +/* ***************************************************************************** */ +#define AT91C_ISRAM ( 0x00200000 ) /* Internal SRAM base address */ +#define AT91C_ISRAM_SIZE ( 0x00010000 ) /* Internal SRAM size in byte (64 Kbyte) */ +#define AT91C_IFLASH ( 0x00100000 ) /* Internal ROM base address */ +#define AT91C_IFLASH_SIZE ( 0x00040000 ) /* Internal ROM size in byte (256 Kbyte) */ diff --git a/Source/portable/IAR/AtmelSAM7S64/ISR_Support.h b/Source/portable/IAR/AtmelSAM7S64/ISR_Support.h index f6b701a11..3aa820266 100644 --- a/Source/portable/IAR/AtmelSAM7S64/ISR_Support.h +++ b/Source/portable/IAR/AtmelSAM7S64/ISR_Support.h @@ -1,105 +1,151 @@ -;/* -; * FreeRTOS Kernel V10.6.2 -; * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. -; * -; * SPDX-License-Identifier: MIT -; * -; * Permission is hereby granted, free of charge, to any person obtaining a copy of -; * this software and associated documentation files (the "Software"), to deal in -; * the Software without restriction, including without limitation the rights to -; * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of -; * the Software, and to permit persons to whom the Software is furnished to do so, -; * subject to the following conditions: -; * -; * The above copyright notice and this permission notice shall be included in all -; * copies or substantial portions of the Software. -; * -; * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -; * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS -; * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR -; * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER -; * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN -; * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. -; * -; * https://www.FreeRTOS.org -; * https://github.com/FreeRTOS -; * -; */ - - EXTERN pxCurrentTCB - EXTERN ulCriticalNesting - -;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -; Context save and restore macro definitions -;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +; /* + * ; * FreeRTOS Kernel V11.0.1 + * ; * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * ; * + * ; * SPDX-License-Identifier: MIT + * ; * + * ; * Permission is hereby granted, free of charge, to any person obtaining a copy of + * ; * this software and associated documentation files (the "Software"), to deal in + * ; * the Software without restriction, including without limitation the rights to + * ; * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * ; * the Software, and to permit persons to whom the Software is furnished to do so, + * ; * subject to the following conditions: + * ; * + * ; * The above copyright notice and this permission notice shall be included in all + * ; * copies or substantial portions of the Software. + * ; * + * ; * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * ; * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * ; * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * ; * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * ; * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * ; * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * ; * + * ; * https://www.FreeRTOS.org + * ; * https://github.com/FreeRTOS + * ; * + * ; */ + +EXTERN pxCurrentTCB +EXTERN ulCriticalNesting + +; +Context save and restore macro definitions +; portSAVE_CONTEXT MACRO - ; Push R0 as we are going to use the register. - STMDB SP!, {R0} +; +Push R0 as we are going to use the register. + STMDB SP !, { + R0 +} + +Set R0 to point to the task stack pointer. + STMDB SP, { + SP +} +^ +NOP +SUB SP, SP, # 4 +LDMIA SP !, { + R0 +} + +; +Push the return address onto the stack. + STMDB R0 !, { + LR + } + + Now we have saved LR we can use it instead of R0. + MOV LR, R0 + +; + +Pop R0 so we can save it onto the system mode stack. + LDMIA SP !, { + R0 +} + +Push all the system mode registers onto the task stack. + STMDB LR, { + R0 - LR +} +^ +NOP +SUB LR, LR, # 60 + +; +Push the SPSR onto the task stack. + MRS R0, SPSR +STMDB LR !, { + R0 +} + +LDR R0, = ulCriticalNesting + LDR R0, [ R0 ] +STMDB LR !, { + R0 +} + +Store the new top of stack + +for the task. + LDR R1, = pxCurrentTCB + LDR R0, [ R1 ] +STR LR, [ R0 ] + +ENDM - ; Set R0 to point to the task stack pointer. - STMDB SP, {SP}^ - NOP - SUB SP, SP, #4 - LDMIA SP!, {R0} - ; Push the return address onto the stack. - STMDB R0!, {LR} - - ; Now we have saved LR we can use it instead of R0. - MOV LR, R0 - - ; Pop R0 so we can save it onto the system mode stack. - LDMIA SP!, {R0} - - ; Push all the system mode registers onto the task stack. - STMDB LR, {R0-LR}^ - NOP - SUB LR, LR, #60 - - ; Push the SPSR onto the task stack. - MRS R0, SPSR - STMDB LR!, {R0} +portRESTORE_CONTEXT MACRO - LDR R0, =ulCriticalNesting - LDR R0, [R0] - STMDB LR!, {R0} +; +Set the LR to the task stack. + LDR R1, = pxCurrentTCB + LDR R0, [ R1 ] +LDR LR, [ R0 ] - ; Store the new top of stack for the task. - LDR R1, =pxCurrentTCB - LDR R0, [R1] - STR LR, [R0] +; +The critical nesting depth is the first item on the stack. + ; +Load it into the ulCriticalNesting variable. + LDR R0, = ulCriticalNesting + LDMFD LR !, { + R1 +} - ENDM +STR R1, [ R0 ] +; +Get the SPSR from the stack. + LDMFD LR !, { + R0 +} +MSR SPSR_cxsf, R0 -portRESTORE_CONTEXT MACRO +; +Restore all system mode registers - ; Set the LR to the task stack. - LDR R1, =pxCurrentTCB - LDR R0, [R1] - LDR LR, [R0] +for the task. + LDMFD LR, { + R0 - R14 +} - ; The critical nesting depth is the first item on the stack. - ; Load it into the ulCriticalNesting variable. - LDR R0, =ulCriticalNesting - LDMFD LR!, {R1} - STR R1, [R0] +^ +NOP - ; Get the SPSR from the stack. - LDMFD LR!, {R0} - MSR SPSR_cxsf, R0 +; +Restore the return address. + LDR LR, [ LR, # + 60 ] - ; Restore all system mode registers for the task. - LDMFD LR, {R0-R14}^ - NOP +; - ; Restore the return address. - LDR LR, [LR, #+60] +And return -correcting the offset in the LR to obtain the +; - ; And return - correcting the offset in the LR to obtain the - ; correct address. - SUBS PC, LR, #4 +correct address. + SUBS PC, LR, # 4 - ENDM +ENDM diff --git a/Source/portable/IAR/AtmelSAM7S64/lib_AT91SAM7S64.h b/Source/portable/IAR/AtmelSAM7S64/lib_AT91SAM7S64.h index 144dc73c2..a392be1a7 100644 --- a/Source/portable/IAR/AtmelSAM7S64/lib_AT91SAM7S64.h +++ b/Source/portable/IAR/AtmelSAM7S64/lib_AT91SAM7S64.h @@ -1,3265 +1,3113 @@ -//*---------------------------------------------------------------------------- -//* ATMEL Microcontroller Software Support - ROUSSET - -//*---------------------------------------------------------------------------- -//* The software is delivered "AS IS" without warranty or condition of any -//* kind, either express, implied or statutory. This includes without -//* limitation any warranty or condition with respect to merchantability or -//* fitness for any particular purpose, or against the infringements of -//* intellectual property rights of others. -//*---------------------------------------------------------------------------- -//* File Name : lib_AT91SAM7S64.h -//* Object : AT91SAM7S64 inlined functions -//* Generated : AT91 SW Application Group 07/16/2004 (07:43:09) -//* -//* CVS Reference : /lib_MC_SAM.h/1.3/Thu Mar 25 15:19:14 2004// -//* CVS Reference : /lib_pdc_1363d.h/1.2/Wed Feb 19 09:25:22 2003// -//* CVS Reference : /lib_dbgu.h/1.1/Fri Jan 31 12:18:40 2003// -//* CVS Reference : /lib_ssc.h/1.4/Fri Jan 31 12:19:20 2003// -//* CVS Reference : /lib_spi2.h/1.1/Mon Aug 25 13:23:52 2003// -//* CVS Reference : /lib_PWM_SAM.h/1.3/Thu Jan 22 10:10:50 2004// -//* CVS Reference : /lib_tc_1753b.h/1.1/Fri Jan 31 12:20:02 2003// -//* CVS Reference : /lib_pmc_SAM.h/1.6/Tue Apr 27 13:53:52 2004// -//* CVS Reference : /lib_adc.h/1.6/Fri Oct 17 08:12:38 2003// -//* CVS Reference : /lib_pio.h/1.3/Fri Jan 31 12:18:56 2003// -//* CVS Reference : /lib_twi.h/1.2/Fri Jan 31 12:19:38 2003// -//* CVS Reference : /lib_usart.h/1.5/Thu Nov 21 16:01:54 2002// -//* CVS Reference : /lib_udp.h/1.3/Fri Jan 31 12:19:48 2003// -//* CVS Reference : /lib_aic.h/1.3/Fri Jul 12 07:46:12 2002// -//*---------------------------------------------------------------------------- +/**---------------------------------------------------------------------------- */ +/** ATMEL Microcontroller Software Support - ROUSSET - */ +/**---------------------------------------------------------------------------- */ +/** The software is delivered "AS IS" without warranty or condition of any */ +/** kind, either express, implied or statutory. This includes without */ +/** limitation any warranty or condition with respect to merchantability or */ +/** fitness for any particular purpose, or against the infringements of */ +/** intellectual property rights of others. */ +/**---------------------------------------------------------------------------- */ +/** File Name : lib_AT91SAM7S64.h */ +/** Object : AT91SAM7S64 inlined functions */ +/** Generated : AT91 SW Application Group 07/16/2004 (07:43:09) */ +/** */ +/** CVS Reference : /lib_MC_SAM.h/1.3/Thu Mar 25 15:19:14 2004// */ +/** CVS Reference : /lib_pdc_1363d.h/1.2/Wed Feb 19 09:25:22 2003// */ +/** CVS Reference : /lib_dbgu.h/1.1/Fri Jan 31 12:18:40 2003// */ +/** CVS Reference : /lib_ssc.h/1.4/Fri Jan 31 12:19:20 2003// */ +/** CVS Reference : /lib_spi2.h/1.1/Mon Aug 25 13:23:52 2003// */ +/** CVS Reference : /lib_PWM_SAM.h/1.3/Thu Jan 22 10:10:50 2004// */ +/** CVS Reference : /lib_tc_1753b.h/1.1/Fri Jan 31 12:20:02 2003// */ +/** CVS Reference : /lib_pmc_SAM.h/1.6/Tue Apr 27 13:53:52 2004// */ +/** CVS Reference : /lib_adc.h/1.6/Fri Oct 17 08:12:38 2003// */ +/** CVS Reference : /lib_pio.h/1.3/Fri Jan 31 12:18:56 2003// */ +/** CVS Reference : /lib_twi.h/1.2/Fri Jan 31 12:19:38 2003// */ +/** CVS Reference : /lib_usart.h/1.5/Thu Nov 21 16:01:54 2002// */ +/** CVS Reference : /lib_udp.h/1.3/Fri Jan 31 12:19:48 2003// */ +/** CVS Reference : /lib_aic.h/1.3/Fri Jul 12 07:46:12 2002// */ +/**---------------------------------------------------------------------------- */ #ifndef lib_AT91SAM7S64_H #define lib_AT91SAM7S64_H /* ***************************************************************************** - SOFTWARE API FOR MC - ***************************************************************************** */ +* SOFTWARE API FOR MC +***************************************************************************** */ -#define AT91C_MC_CORRECT_KEY ((unsigned int) 0x5A << 24) // (MC) Correct Protect Key +#define AT91C_MC_CORRECT_KEY ( ( unsigned int ) 0x5A << 24 ) /* (MC) Correct Protect Key */ -//*---------------------------------------------------------------------------- -//* \fn AT91F_MC_Remap -//* \brief Make Remap -//*---------------------------------------------------------------------------- -__inline void AT91F_MC_Remap (void) // +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_MC_Remap */ +/** \brief Make Remap */ +/**---------------------------------------------------------------------------- */ +__inline void AT91F_MC_Remap( void ) /* */ { - AT91PS_MC pMC = (AT91PS_MC) AT91C_BASE_MC; + AT91PS_MC pMC = ( AT91PS_MC ) AT91C_BASE_MC; pMC->MC_RCR = AT91C_MC_RCB; } -//*---------------------------------------------------------------------------- -//* \fn AT91F_MC_EFC_CfgModeReg -//* \brief Configure the EFC Mode Register of the MC controller -//*---------------------------------------------------------------------------- -__inline void AT91F_MC_EFC_CfgModeReg ( - AT91PS_MC pMC, // pointer to a MC controller - unsigned int mode) // mode register +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_MC_EFC_CfgModeReg */ +/** \brief Configure the EFC Mode Register of the MC controller */ +/**---------------------------------------------------------------------------- */ +__inline void AT91F_MC_EFC_CfgModeReg( AT91PS_MC pMC, /* pointer to a MC controller */ + unsigned int mode ) /* mode register */ { - // Write to the FMR register + /* Write to the FMR register */ pMC->MC_FMR = mode; } -//*---------------------------------------------------------------------------- -//* \fn AT91F_MC_EFC_GetModeReg -//* \brief Return MC EFC Mode Regsiter -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_MC_EFC_GetModeReg( - AT91PS_MC pMC) // pointer to a MC controller +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_MC_EFC_GetModeReg */ +/** \brief Return MC EFC Mode Regsiter */ +/**---------------------------------------------------------------------------- */ +__inline unsigned int AT91F_MC_EFC_GetModeReg( AT91PS_MC pMC ) /* pointer to a MC controller */ { return pMC->MC_FMR; } -//*---------------------------------------------------------------------------- -//* \fn AT91F_MC_EFC_ComputeFMCN -//* \brief Return MC EFC Mode Regsiter -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_MC_EFC_ComputeFMCN( - int master_clock) // master clock in Hz +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_MC_EFC_ComputeFMCN */ +/** \brief Return MC EFC Mode Regsiter */ +/**---------------------------------------------------------------------------- */ +__inline unsigned int AT91F_MC_EFC_ComputeFMCN( int master_clock ) /* master clock in Hz */ { - return (master_clock/1000000 +2); + return( master_clock / 1000000 + 2 ); } -//*---------------------------------------------------------------------------- -//* \fn AT91F_MC_EFC_PerformCmd -//* \brief Perform EFC Command -//*---------------------------------------------------------------------------- -__inline void AT91F_MC_EFC_PerformCmd ( - AT91PS_MC pMC, // pointer to a MC controller - unsigned int transfer_cmd) +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_MC_EFC_PerformCmd */ +/** \brief Perform EFC Command */ +/**---------------------------------------------------------------------------- */ +__inline void AT91F_MC_EFC_PerformCmd( AT91PS_MC pMC, /* pointer to a MC controller */ + unsigned int transfer_cmd ) { pMC->MC_FCR = transfer_cmd; } -//*---------------------------------------------------------------------------- -//* \fn AT91F_MC_EFC_GetStatus -//* \brief Return MC EFC Status -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_MC_EFC_GetStatus( - AT91PS_MC pMC) // pointer to a MC controller +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_MC_EFC_GetStatus */ +/** \brief Return MC EFC Status */ +/**---------------------------------------------------------------------------- */ +__inline unsigned int AT91F_MC_EFC_GetStatus( AT91PS_MC pMC ) /* pointer to a MC controller */ { return pMC->MC_FSR; } -//*---------------------------------------------------------------------------- -//* \fn AT91F_MC_EFC_IsInterruptMasked -//* \brief Test if EFC MC Interrupt is Masked -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_MC_EFC_IsInterruptMasked( - AT91PS_MC pMC, // \arg pointer to a MC controller - unsigned int flag) // \arg flag to be tested +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_MC_EFC_IsInterruptMasked */ +/** \brief Test if EFC MC Interrupt is Masked */ +/**---------------------------------------------------------------------------- */ +__inline unsigned int AT91F_MC_EFC_IsInterruptMasked( AT91PS_MC pMC, /* \arg pointer to a MC controller */ + unsigned int flag ) /* \arg flag to be tested */ { - return (AT91F_MC_EFC_GetModeReg(pMC) & flag); + return( AT91F_MC_EFC_GetModeReg( pMC ) & flag ); } -//*---------------------------------------------------------------------------- -//* \fn AT91F_MC_EFC_IsInterruptSet -//* \brief Test if EFC MC Interrupt is Set -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_MC_EFC_IsInterruptSet( - AT91PS_MC pMC, // \arg pointer to a MC controller - unsigned int flag) // \arg flag to be tested +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_MC_EFC_IsInterruptSet */ +/** \brief Test if EFC MC Interrupt is Set */ +/**---------------------------------------------------------------------------- */ +__inline unsigned int AT91F_MC_EFC_IsInterruptSet( AT91PS_MC pMC, /* \arg pointer to a MC controller */ + unsigned int flag ) /* \arg flag to be tested */ { - return (AT91F_MC_EFC_GetStatus(pMC) & flag); + return( AT91F_MC_EFC_GetStatus( pMC ) & flag ); } /* ***************************************************************************** - SOFTWARE API FOR PDC - ***************************************************************************** */ -//*---------------------------------------------------------------------------- -//* \fn AT91F_PDC_SetNextRx -//* \brief Set the next receive transfer descriptor -//*---------------------------------------------------------------------------- -__inline void AT91F_PDC_SetNextRx ( - AT91PS_PDC pPDC, // \arg pointer to a PDC controller - char *address, // \arg address to the next bloc to be received - unsigned int bytes) // \arg number of bytes to be received -{ - pPDC->PDC_RNPR = (unsigned int) address; +* SOFTWARE API FOR PDC +***************************************************************************** */ +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PDC_SetNextRx */ +/** \brief Set the next receive transfer descriptor */ +/**---------------------------------------------------------------------------- */ +__inline void AT91F_PDC_SetNextRx( AT91PS_PDC pPDC, /* \arg pointer to a PDC controller */ + char * address, /* \arg address to the next bloc to be received */ + unsigned int bytes ) /* \arg number of bytes to be received */ +{ + pPDC->PDC_RNPR = ( unsigned int ) address; pPDC->PDC_RNCR = bytes; } -//*---------------------------------------------------------------------------- -//* \fn AT91F_PDC_SetNextTx -//* \brief Set the next transmit transfer descriptor -//*---------------------------------------------------------------------------- -__inline void AT91F_PDC_SetNextTx ( - AT91PS_PDC pPDC, // \arg pointer to a PDC controller - char *address, // \arg address to the next bloc to be transmitted - unsigned int bytes) // \arg number of bytes to be transmitted +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PDC_SetNextTx */ +/** \brief Set the next transmit transfer descriptor */ +/**---------------------------------------------------------------------------- */ +__inline void AT91F_PDC_SetNextTx( AT91PS_PDC pPDC, /* \arg pointer to a PDC controller */ + char * address, /* \arg address to the next bloc to be transmitted */ + unsigned int bytes ) /* \arg number of bytes to be transmitted */ { - pPDC->PDC_TNPR = (unsigned int) address; + pPDC->PDC_TNPR = ( unsigned int ) address; pPDC->PDC_TNCR = bytes; } -//*---------------------------------------------------------------------------- -//* \fn AT91F_PDC_SetRx -//* \brief Set the receive transfer descriptor -//*---------------------------------------------------------------------------- -__inline void AT91F_PDC_SetRx ( - AT91PS_PDC pPDC, // \arg pointer to a PDC controller - char *address, // \arg address to the next bloc to be received - unsigned int bytes) // \arg number of bytes to be received +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PDC_SetRx */ +/** \brief Set the receive transfer descriptor */ +/**---------------------------------------------------------------------------- */ +__inline void AT91F_PDC_SetRx( AT91PS_PDC pPDC, /* \arg pointer to a PDC controller */ + char * address, /* \arg address to the next bloc to be received */ + unsigned int bytes ) /* \arg number of bytes to be received */ { - pPDC->PDC_RPR = (unsigned int) address; + pPDC->PDC_RPR = ( unsigned int ) address; pPDC->PDC_RCR = bytes; } -//*---------------------------------------------------------------------------- -//* \fn AT91F_PDC_SetTx -//* \brief Set the transmit transfer descriptor -//*---------------------------------------------------------------------------- -__inline void AT91F_PDC_SetTx ( - AT91PS_PDC pPDC, // \arg pointer to a PDC controller - char *address, // \arg address to the next bloc to be transmitted - unsigned int bytes) // \arg number of bytes to be transmitted +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PDC_SetTx */ +/** \brief Set the transmit transfer descriptor */ +/**---------------------------------------------------------------------------- */ +__inline void AT91F_PDC_SetTx( AT91PS_PDC pPDC, /* \arg pointer to a PDC controller */ + char * address, /* \arg address to the next bloc to be transmitted */ + unsigned int bytes ) /* \arg number of bytes to be transmitted */ { - pPDC->PDC_TPR = (unsigned int) address; + pPDC->PDC_TPR = ( unsigned int ) address; pPDC->PDC_TCR = bytes; } -//*---------------------------------------------------------------------------- -//* \fn AT91F_PDC_EnableTx -//* \brief Enable transmit -//*---------------------------------------------------------------------------- -__inline void AT91F_PDC_EnableTx ( - AT91PS_PDC pPDC ) // \arg pointer to a PDC controller +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PDC_EnableTx */ +/** \brief Enable transmit */ +/**---------------------------------------------------------------------------- */ +__inline void AT91F_PDC_EnableTx( AT91PS_PDC pPDC ) /* \arg pointer to a PDC controller */ { pPDC->PDC_PTCR = AT91C_PDC_TXTEN; } -//*---------------------------------------------------------------------------- -//* \fn AT91F_PDC_EnableRx -//* \brief Enable receive -//*---------------------------------------------------------------------------- -__inline void AT91F_PDC_EnableRx ( - AT91PS_PDC pPDC ) // \arg pointer to a PDC controller +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PDC_EnableRx */ +/** \brief Enable receive */ +/**---------------------------------------------------------------------------- */ +__inline void AT91F_PDC_EnableRx( AT91PS_PDC pPDC ) /* \arg pointer to a PDC controller */ { pPDC->PDC_PTCR = AT91C_PDC_RXTEN; } -//*---------------------------------------------------------------------------- -//* \fn AT91F_PDC_DisableTx -//* \brief Disable transmit -//*---------------------------------------------------------------------------- -__inline void AT91F_PDC_DisableTx ( - AT91PS_PDC pPDC ) // \arg pointer to a PDC controller +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PDC_DisableTx */ +/** \brief Disable transmit */ +/**---------------------------------------------------------------------------- */ +__inline void AT91F_PDC_DisableTx( AT91PS_PDC pPDC ) /* \arg pointer to a PDC controller */ { pPDC->PDC_PTCR = AT91C_PDC_TXTDIS; } -//*---------------------------------------------------------------------------- -//* \fn AT91F_PDC_DisableRx -//* \brief Disable receive -//*---------------------------------------------------------------------------- -__inline void AT91F_PDC_DisableRx ( - AT91PS_PDC pPDC ) // \arg pointer to a PDC controller +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PDC_DisableRx */ +/** \brief Disable receive */ +/**---------------------------------------------------------------------------- */ +__inline void AT91F_PDC_DisableRx( AT91PS_PDC pPDC ) /* \arg pointer to a PDC controller */ { pPDC->PDC_PTCR = AT91C_PDC_RXTDIS; } -//*---------------------------------------------------------------------------- -//* \fn AT91F_PDC_IsTxEmpty -//* \brief Test if the current transfer descriptor has been sent -//*---------------------------------------------------------------------------- -__inline int AT91F_PDC_IsTxEmpty ( // \return return 1 if transfer is complete - AT91PS_PDC pPDC ) // \arg pointer to a PDC controller +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PDC_IsTxEmpty */ +/** \brief Test if the current transfer descriptor has been sent */ +/**---------------------------------------------------------------------------- */ +__inline int AT91F_PDC_IsTxEmpty( /* \return return 1 if transfer is complete */ + AT91PS_PDC pPDC ) /* \arg pointer to a PDC controller */ { - return !(pPDC->PDC_TCR); + return !( pPDC->PDC_TCR ); } -//*---------------------------------------------------------------------------- -//* \fn AT91F_PDC_IsNextTxEmpty -//* \brief Test if the next transfer descriptor has been moved to the current td -//*---------------------------------------------------------------------------- -__inline int AT91F_PDC_IsNextTxEmpty ( // \return return 1 if transfer is complete - AT91PS_PDC pPDC ) // \arg pointer to a PDC controller +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PDC_IsNextTxEmpty */ +/** \brief Test if the next transfer descriptor has been moved to the current td */ +/**---------------------------------------------------------------------------- */ +__inline int AT91F_PDC_IsNextTxEmpty( /* \return return 1 if transfer is complete */ + AT91PS_PDC pPDC ) /* \arg pointer to a PDC controller */ { - return !(pPDC->PDC_TNCR); + return !( pPDC->PDC_TNCR ); } -//*---------------------------------------------------------------------------- -//* \fn AT91F_PDC_IsRxEmpty -//* \brief Test if the current transfer descriptor has been filled -//*---------------------------------------------------------------------------- -__inline int AT91F_PDC_IsRxEmpty ( // \return return 1 if transfer is complete - AT91PS_PDC pPDC ) // \arg pointer to a PDC controller +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PDC_IsRxEmpty */ +/** \brief Test if the current transfer descriptor has been filled */ +/**---------------------------------------------------------------------------- */ +__inline int AT91F_PDC_IsRxEmpty( /* \return return 1 if transfer is complete */ + AT91PS_PDC pPDC ) /* \arg pointer to a PDC controller */ { - return !(pPDC->PDC_RCR); + return !( pPDC->PDC_RCR ); } -//*---------------------------------------------------------------------------- -//* \fn AT91F_PDC_IsNextRxEmpty -//* \brief Test if the next transfer descriptor has been moved to the current td -//*---------------------------------------------------------------------------- -__inline int AT91F_PDC_IsNextRxEmpty ( // \return return 1 if transfer is complete - AT91PS_PDC pPDC ) // \arg pointer to a PDC controller +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PDC_IsNextRxEmpty */ +/** \brief Test if the next transfer descriptor has been moved to the current td */ +/**---------------------------------------------------------------------------- */ +__inline int AT91F_PDC_IsNextRxEmpty( /* \return return 1 if transfer is complete */ + AT91PS_PDC pPDC ) /* \arg pointer to a PDC controller */ { - return !(pPDC->PDC_RNCR); + return !( pPDC->PDC_RNCR ); } -//*---------------------------------------------------------------------------- -//* \fn AT91F_PDC_Open -//* \brief Open PDC: disable TX and RX reset transfer descriptors, re-enable RX and TX -//*---------------------------------------------------------------------------- -__inline void AT91F_PDC_Open ( - AT91PS_PDC pPDC) // \arg pointer to a PDC controller +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PDC_Open */ +/** \brief Open PDC: disable TX and RX reset transfer descriptors, re-enable RX and TX */ +/**---------------------------------------------------------------------------- */ +__inline void AT91F_PDC_Open( AT91PS_PDC pPDC ) /* \arg pointer to a PDC controller */ { - //* Disable the RX and TX PDC transfer requests - AT91F_PDC_DisableRx(pPDC); - AT91F_PDC_DisableTx(pPDC); + /** Disable the RX and TX PDC transfer requests */ + AT91F_PDC_DisableRx( pPDC ); + AT91F_PDC_DisableTx( pPDC ); - //* Reset all Counter register Next buffer first - AT91F_PDC_SetNextTx(pPDC, (char *) 0, 0); - AT91F_PDC_SetNextRx(pPDC, (char *) 0, 0); - AT91F_PDC_SetTx(pPDC, (char *) 0, 0); - AT91F_PDC_SetRx(pPDC, (char *) 0, 0); + /** Reset all Counter register Next buffer first */ + AT91F_PDC_SetNextTx( pPDC, ( char * ) 0, 0 ); + AT91F_PDC_SetNextRx( pPDC, ( char * ) 0, 0 ); + AT91F_PDC_SetTx( pPDC, ( char * ) 0, 0 ); + AT91F_PDC_SetRx( pPDC, ( char * ) 0, 0 ); - //* Enable the RX and TX PDC transfer requests - AT91F_PDC_EnableRx(pPDC); - AT91F_PDC_EnableTx(pPDC); + /** Enable the RX and TX PDC transfer requests */ + AT91F_PDC_EnableRx( pPDC ); + AT91F_PDC_EnableTx( pPDC ); } -//*---------------------------------------------------------------------------- -//* \fn AT91F_PDC_Close -//* \brief Close PDC: disable TX and RX reset transfer descriptors -//*---------------------------------------------------------------------------- -__inline void AT91F_PDC_Close ( - AT91PS_PDC pPDC) // \arg pointer to a PDC controller +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PDC_Close */ +/** \brief Close PDC: disable TX and RX reset transfer descriptors */ +/**---------------------------------------------------------------------------- */ +__inline void AT91F_PDC_Close( AT91PS_PDC pPDC ) /* \arg pointer to a PDC controller */ { - //* Disable the RX and TX PDC transfer requests - AT91F_PDC_DisableRx(pPDC); - AT91F_PDC_DisableTx(pPDC); - - //* Reset all Counter register Next buffer first - AT91F_PDC_SetNextTx(pPDC, (char *) 0, 0); - AT91F_PDC_SetNextRx(pPDC, (char *) 0, 0); - AT91F_PDC_SetTx(pPDC, (char *) 0, 0); - AT91F_PDC_SetRx(pPDC, (char *) 0, 0); + /** Disable the RX and TX PDC transfer requests */ + AT91F_PDC_DisableRx( pPDC ); + AT91F_PDC_DisableTx( pPDC ); + /** Reset all Counter register Next buffer first */ + AT91F_PDC_SetNextTx( pPDC, ( char * ) 0, 0 ); + AT91F_PDC_SetNextRx( pPDC, ( char * ) 0, 0 ); + AT91F_PDC_SetTx( pPDC, ( char * ) 0, 0 ); + AT91F_PDC_SetRx( pPDC, ( char * ) 0, 0 ); } -//*---------------------------------------------------------------------------- -//* \fn AT91F_PDC_SendFrame -//* \brief Close PDC: disable TX and RX reset transfer descriptors -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_PDC_SendFrame( - AT91PS_PDC pPDC, - char *pBuffer, - unsigned int szBuffer, - char *pNextBuffer, - unsigned int szNextBuffer ) +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PDC_SendFrame */ +/** \brief Close PDC: disable TX and RX reset transfer descriptors */ +/**---------------------------------------------------------------------------- */ +__inline unsigned int AT91F_PDC_SendFrame( AT91PS_PDC pPDC, + char * pBuffer, + unsigned int szBuffer, + char * pNextBuffer, + unsigned int szNextBuffer ) { - if (AT91F_PDC_IsTxEmpty(pPDC)) { - //* Buffer and next buffer can be initialized - AT91F_PDC_SetTx(pPDC, pBuffer, szBuffer); - AT91F_PDC_SetNextTx(pPDC, pNextBuffer, szNextBuffer); + if( AT91F_PDC_IsTxEmpty( pPDC ) ) + { + /** Buffer and next buffer can be initialized */ + AT91F_PDC_SetTx( pPDC, pBuffer, szBuffer ); + AT91F_PDC_SetNextTx( pPDC, pNextBuffer, szNextBuffer ); return 2; } - else if (AT91F_PDC_IsNextTxEmpty(pPDC)) { - //* Only one buffer can be initialized - AT91F_PDC_SetNextTx(pPDC, pBuffer, szBuffer); + else if( AT91F_PDC_IsNextTxEmpty( pPDC ) ) + { + /** Only one buffer can be initialized */ + AT91F_PDC_SetNextTx( pPDC, pBuffer, szBuffer ); return 1; } - else { - //* All buffer are in use... + else + { + /** All buffer are in use... */ return 0; } } -//*---------------------------------------------------------------------------- -//* \fn AT91F_PDC_ReceiveFrame -//* \brief Close PDC: disable TX and RX reset transfer descriptors -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_PDC_ReceiveFrame ( - AT91PS_PDC pPDC, - char *pBuffer, - unsigned int szBuffer, - char *pNextBuffer, - unsigned int szNextBuffer ) -{ - if (AT91F_PDC_IsRxEmpty(pPDC)) { - //* Buffer and next buffer can be initialized - AT91F_PDC_SetRx(pPDC, pBuffer, szBuffer); - AT91F_PDC_SetNextRx(pPDC, pNextBuffer, szNextBuffer); +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PDC_ReceiveFrame */ +/** \brief Close PDC: disable TX and RX reset transfer descriptors */ +/**---------------------------------------------------------------------------- */ +__inline unsigned int AT91F_PDC_ReceiveFrame( AT91PS_PDC pPDC, + char * pBuffer, + unsigned int szBuffer, + char * pNextBuffer, + unsigned int szNextBuffer ) +{ + if( AT91F_PDC_IsRxEmpty( pPDC ) ) + { + /** Buffer and next buffer can be initialized */ + AT91F_PDC_SetRx( pPDC, pBuffer, szBuffer ); + AT91F_PDC_SetNextRx( pPDC, pNextBuffer, szNextBuffer ); return 2; } - else if (AT91F_PDC_IsNextRxEmpty(pPDC)) { - //* Only one buffer can be initialized - AT91F_PDC_SetNextRx(pPDC, pBuffer, szBuffer); + else if( AT91F_PDC_IsNextRxEmpty( pPDC ) ) + { + /** Only one buffer can be initialized */ + AT91F_PDC_SetNextRx( pPDC, pBuffer, szBuffer ); return 1; } - else { - //* All buffer are in use... + else + { + /** All buffer are in use... */ return 0; } } + /* ***************************************************************************** - SOFTWARE API FOR DBGU - ***************************************************************************** */ -//*---------------------------------------------------------------------------- -//* \fn AT91F_DBGU_InterruptEnable -//* \brief Enable DBGU Interrupt -//*---------------------------------------------------------------------------- -__inline void AT91F_DBGU_InterruptEnable( - AT91PS_DBGU pDbgu, // \arg pointer to a DBGU controller - unsigned int flag) // \arg dbgu interrupt to be enabled +* SOFTWARE API FOR DBGU +***************************************************************************** */ +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_DBGU_InterruptEnable */ +/** \brief Enable DBGU Interrupt */ +/**---------------------------------------------------------------------------- */ +__inline void AT91F_DBGU_InterruptEnable( AT91PS_DBGU pDbgu, /* \arg pointer to a DBGU controller */ + unsigned int flag ) /* \arg dbgu interrupt to be enabled */ { - pDbgu->DBGU_IER = flag; + pDbgu->DBGU_IER = flag; } -//*---------------------------------------------------------------------------- -//* \fn AT91F_DBGU_InterruptDisable -//* \brief Disable DBGU Interrupt -//*---------------------------------------------------------------------------- -__inline void AT91F_DBGU_InterruptDisable( - AT91PS_DBGU pDbgu, // \arg pointer to a DBGU controller - unsigned int flag) // \arg dbgu interrupt to be disabled +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_DBGU_InterruptDisable */ +/** \brief Disable DBGU Interrupt */ +/**---------------------------------------------------------------------------- */ +__inline void AT91F_DBGU_InterruptDisable( AT91PS_DBGU pDbgu, /* \arg pointer to a DBGU controller */ + unsigned int flag ) /* \arg dbgu interrupt to be disabled */ { - pDbgu->DBGU_IDR = flag; + pDbgu->DBGU_IDR = flag; } -//*---------------------------------------------------------------------------- -//* \fn AT91F_DBGU_GetInterruptMaskStatus -//* \brief Return DBGU Interrupt Mask Status -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_DBGU_GetInterruptMaskStatus( // \return DBGU Interrupt Mask Status - AT91PS_DBGU pDbgu) // \arg pointer to a DBGU controller +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_DBGU_GetInterruptMaskStatus */ +/** \brief Return DBGU Interrupt Mask Status */ +/**---------------------------------------------------------------------------- */ +__inline unsigned int AT91F_DBGU_GetInterruptMaskStatus( /* \return DBGU Interrupt Mask Status */ + AT91PS_DBGU pDbgu ) /* \arg pointer to a DBGU controller */ { - return pDbgu->DBGU_IMR; + return pDbgu->DBGU_IMR; } -//*---------------------------------------------------------------------------- -//* \fn AT91F_DBGU_IsInterruptMasked -//* \brief Test if DBGU Interrupt is Masked -//*---------------------------------------------------------------------------- -__inline int AT91F_DBGU_IsInterruptMasked( - AT91PS_DBGU pDbgu, // \arg pointer to a DBGU controller - unsigned int flag) // \arg flag to be tested +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_DBGU_IsInterruptMasked */ +/** \brief Test if DBGU Interrupt is Masked */ +/**---------------------------------------------------------------------------- */ +__inline int AT91F_DBGU_IsInterruptMasked( AT91PS_DBGU pDbgu, /* \arg pointer to a DBGU controller */ + unsigned int flag ) /* \arg flag to be tested */ { - return (AT91F_DBGU_GetInterruptMaskStatus(pDbgu) & flag); + return( AT91F_DBGU_GetInterruptMaskStatus( pDbgu ) & flag ); } /* ***************************************************************************** - SOFTWARE API FOR SSC - ***************************************************************************** */ -//* Define the standard I2S mode configuration - -//* Configuration to set in the SSC Transmit Clock Mode Register -//* Parameters : nb_bit_by_slot : 8, 16 or 32 bits -//* nb_slot_by_frame : number of channels -#define AT91C_I2S_ASY_MASTER_TX_SETTING(nb_bit_by_slot, nb_slot_by_frame)( +\ - AT91C_SSC_CKS_DIV +\ - AT91C_SSC_CKO_CONTINOUS +\ - AT91C_SSC_CKG_NONE +\ - AT91C_SSC_START_FALL_RF +\ - AT91C_SSC_STTOUT +\ - ((1<<16) & AT91C_SSC_STTDLY) +\ - ((((nb_bit_by_slot*nb_slot_by_frame)/2)-1) <<24)) - - -//* Configuration to set in the SSC Transmit Frame Mode Register -//* Parameters : nb_bit_by_slot : 8, 16 or 32 bits -//* nb_slot_by_frame : number of channels -#define AT91C_I2S_ASY_TX_FRAME_SETTING(nb_bit_by_slot, nb_slot_by_frame)( +\ - (nb_bit_by_slot-1) +\ - AT91C_SSC_MSBF +\ - (((nb_slot_by_frame-1)<<8) & AT91C_SSC_DATNB) +\ - (((nb_bit_by_slot-1)<<16) & AT91C_SSC_FSLEN) +\ - AT91C_SSC_FSOS_NEGATIVE) - - -//*---------------------------------------------------------------------------- -//* \fn AT91F_SSC_SetBaudrate -//* \brief Set the baudrate according to the CPU clock -//*---------------------------------------------------------------------------- -__inline void AT91F_SSC_SetBaudrate ( - AT91PS_SSC pSSC, // \arg pointer to a SSC controller - unsigned int mainClock, // \arg peripheral clock - unsigned int speed) // \arg SSC baudrate -{ - unsigned int baud_value; - //* Define the baud rate divisor register - if (speed == 0) - baud_value = 0; +* SOFTWARE API FOR SSC +***************************************************************************** */ +/** Define the standard I2S mode configuration */ + +/** Configuration to set in the SSC Transmit Clock Mode Register */ +/** Parameters : nb_bit_by_slot : 8, 16 or 32 bits */ +/** nb_slot_by_frame : number of channels */ +#define AT91C_I2S_ASY_MASTER_TX_SETTING( nb_bit_by_slot, nb_slot_by_frame ) \ + ( + \ + AT91C_SSC_CKS_DIV + \ + AT91C_SSC_CKO_CONTINUOUS + \ + AT91C_SSC_CKG_NONE + \ + AT91C_SSC_START_FALL_RF + \ + AT91C_SSC_STTOUT + \ + ( ( 1 << 16 ) & AT91C_SSC_STTDLY ) + \ + ( ( ( ( nb_bit_by_slot * nb_slot_by_frame ) / 2 ) - 1 ) << 24 ) ) + + +/** Configuration to set in the SSC Transmit Frame Mode Register */ +/** Parameters : nb_bit_by_slot : 8, 16 or 32 bits */ +/** nb_slot_by_frame : number of channels */ +#define AT91C_I2S_ASY_TX_FRAME_SETTING( nb_bit_by_slot, nb_slot_by_frame ) \ + ( + \ + ( nb_bit_by_slot - 1 ) + \ + AT91C_SSC_MSBF + \ + ( ( ( nb_slot_by_frame - 1 ) << 8 ) & AT91C_SSC_DATNB ) + \ + ( ( ( nb_bit_by_slot - 1 ) << 16 ) & AT91C_SSC_FSLEN ) + \ + AT91C_SSC_FSOS_NEGATIVE ) + + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_SSC_SetBaudrate */ +/** \brief Set the baudrate according to the CPU clock */ +/**---------------------------------------------------------------------------- */ +__inline void AT91F_SSC_SetBaudrate( AT91PS_SSC pSSC, /* \arg pointer to a SSC controller */ + unsigned int mainClock, /* \arg peripheral clock */ + unsigned int speed ) /* \arg SSC baudrate */ +{ + unsigned int baud_value; + + /** Define the baud rate divisor register */ + if( speed == 0 ) + { + baud_value = 0; + } + else + { + baud_value = ( unsigned int ) ( mainClock * 10 ) / ( 2 * speed ); + + if( ( baud_value % 10 ) >= 5 ) + { + baud_value = ( baud_value / 10 ) + 1; + } else { - baud_value = (unsigned int) (mainClock * 10)/(2*speed); - if ((baud_value % 10) >= 5) - baud_value = (baud_value / 10) + 1; - else - baud_value /= 10; + baud_value /= 10; } + } - pSSC->SSC_CMR = baud_value; + pSSC->SSC_CMR = baud_value; } -//*---------------------------------------------------------------------------- -//* \fn AT91F_SSC_Configure -//* \brief Configure SSC -//*---------------------------------------------------------------------------- -__inline void AT91F_SSC_Configure ( - AT91PS_SSC pSSC, // \arg pointer to a SSC controller - unsigned int syst_clock, // \arg System Clock Frequency - unsigned int baud_rate, // \arg Expected Baud Rate Frequency - unsigned int clock_rx, // \arg Receiver Clock Parameters - unsigned int mode_rx, // \arg mode Register to be programmed - unsigned int clock_tx, // \arg Transmitter Clock Parameters - unsigned int mode_tx) // \arg mode Register to be programmed +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_SSC_Configure */ +/** \brief Configure SSC */ +/**---------------------------------------------------------------------------- */ +__inline void AT91F_SSC_Configure( AT91PS_SSC pSSC, /* \arg pointer to a SSC controller */ + unsigned int syst_clock, /* \arg System Clock Frequency */ + unsigned int baud_rate, /* \arg Expected Baud Rate Frequency */ + unsigned int clock_rx, /* \arg Receiver Clock Parameters */ + unsigned int mode_rx, /* \arg mode Register to be programmed */ + unsigned int clock_tx, /* \arg Transmitter Clock Parameters */ + unsigned int mode_tx ) /* \arg mode Register to be programmed */ { - //* Disable interrupts - pSSC->SSC_IDR = (unsigned int) -1; - - //* Reset receiver and transmitter - pSSC->SSC_CR = AT91C_SSC_SWRST | AT91C_SSC_RXDIS | AT91C_SSC_TXDIS ; - - //* Define the Clock Mode Register - AT91F_SSC_SetBaudrate(pSSC, syst_clock, baud_rate); + /** Disable interrupts */ + pSSC->SSC_IDR = ( unsigned int ) -1; - //* Write the Receive Clock Mode Register - pSSC->SSC_RCMR = clock_rx; + /** Reset receiver and transmitter */ + pSSC->SSC_CR = AT91C_SSC_SWRST | AT91C_SSC_RXDIS | AT91C_SSC_TXDIS; - //* Write the Transmit Clock Mode Register - pSSC->SSC_TCMR = clock_tx; + /** Define the Clock Mode Register */ + AT91F_SSC_SetBaudrate( pSSC, syst_clock, baud_rate ); - //* Write the Receive Frame Mode Register - pSSC->SSC_RFMR = mode_rx; + /** Write the Receive Clock Mode Register */ + pSSC->SSC_RCMR = clock_rx; - //* Write the Transmit Frame Mode Register - pSSC->SSC_TFMR = mode_tx; + /** Write the Transmit Clock Mode Register */ + pSSC->SSC_TCMR = clock_tx; - //* Clear Transmit and Receive Counters - AT91F_PDC_Open((AT91PS_PDC) &(pSSC->SSC_RPR)); + /** Write the Receive Frame Mode Register */ + pSSC->SSC_RFMR = mode_rx; + /** Write the Transmit Frame Mode Register */ + pSSC->SSC_TFMR = mode_tx; + /** Clear Transmit and Receive Counters */ + AT91F_PDC_Open( ( AT91PS_PDC ) &( pSSC->SSC_RPR ) ); } -//*---------------------------------------------------------------------------- -//* \fn AT91F_SSC_EnableRx -//* \brief Enable receiving datas -//*---------------------------------------------------------------------------- -__inline void AT91F_SSC_EnableRx ( - AT91PS_SSC pSSC) // \arg pointer to a SSC controller +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_SSC_EnableRx */ +/** \brief Enable receiving data */ +/**---------------------------------------------------------------------------- */ +__inline void AT91F_SSC_EnableRx( AT91PS_SSC pSSC ) /* \arg pointer to a SSC controller */ { - //* Enable receiver + /** Enable receiver */ pSSC->SSC_CR = AT91C_SSC_RXEN; } -//*---------------------------------------------------------------------------- -//* \fn AT91F_SSC_DisableRx -//* \brief Disable receiving datas -//*---------------------------------------------------------------------------- -__inline void AT91F_SSC_DisableRx ( - AT91PS_SSC pSSC) // \arg pointer to a SSC controller +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_SSC_DisableRx */ +/** \brief Disable receiving data */ +/**---------------------------------------------------------------------------- */ +__inline void AT91F_SSC_DisableRx( AT91PS_SSC pSSC ) /* \arg pointer to a SSC controller */ { - //* Disable receiver + /** Disable receiver */ pSSC->SSC_CR = AT91C_SSC_RXDIS; } -//*---------------------------------------------------------------------------- -//* \fn AT91F_SSC_EnableTx -//* \brief Enable sending datas -//*---------------------------------------------------------------------------- -__inline void AT91F_SSC_EnableTx ( - AT91PS_SSC pSSC) // \arg pointer to a SSC controller +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_SSC_EnableTx */ +/** \brief Enable sending data */ +/**---------------------------------------------------------------------------- */ +__inline void AT91F_SSC_EnableTx( AT91PS_SSC pSSC ) /* \arg pointer to a SSC controller */ { - //* Enable transmitter + /** Enable transmitter */ pSSC->SSC_CR = AT91C_SSC_TXEN; } -//*---------------------------------------------------------------------------- -//* \fn AT91F_SSC_DisableTx -//* \brief Disable sending datas -//*---------------------------------------------------------------------------- -__inline void AT91F_SSC_DisableTx ( - AT91PS_SSC pSSC) // \arg pointer to a SSC controller +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_SSC_DisableTx */ +/** \brief Disable sending data */ +/**---------------------------------------------------------------------------- */ +__inline void AT91F_SSC_DisableTx( AT91PS_SSC pSSC ) /* \arg pointer to a SSC controller */ { - //* Disable transmitter + /** Disable transmitter */ pSSC->SSC_CR = AT91C_SSC_TXDIS; } -//*---------------------------------------------------------------------------- -//* \fn AT91F_SSC_EnableIt -//* \brief Enable SSC IT -//*---------------------------------------------------------------------------- -__inline void AT91F_SSC_EnableIt ( - AT91PS_SSC pSSC, // \arg pointer to a SSC controller - unsigned int flag) // \arg IT to be enabled +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_SSC_EnableIt */ +/** \brief Enable SSC IT */ +/**---------------------------------------------------------------------------- */ +__inline void AT91F_SSC_EnableIt( AT91PS_SSC pSSC, /* \arg pointer to a SSC controller */ + unsigned int flag ) /* \arg IT to be enabled */ { - //* Write to the IER register + /** Write to the IER register */ pSSC->SSC_IER = flag; } -//*---------------------------------------------------------------------------- -//* \fn AT91F_SSC_DisableIt -//* \brief Disable SSC IT -//*---------------------------------------------------------------------------- -__inline void AT91F_SSC_DisableIt ( - AT91PS_SSC pSSC, // \arg pointer to a SSC controller - unsigned int flag) // \arg IT to be disabled +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_SSC_DisableIt */ +/** \brief Disable SSC IT */ +/**---------------------------------------------------------------------------- */ +__inline void AT91F_SSC_DisableIt( AT91PS_SSC pSSC, /* \arg pointer to a SSC controller */ + unsigned int flag ) /* \arg IT to be disabled */ { - //* Write to the IDR register + /** Write to the IDR register */ pSSC->SSC_IDR = flag; } -//*---------------------------------------------------------------------------- -//* \fn AT91F_SSC_ReceiveFrame -//* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initialized with Next Buffer, 0 if PDC is busy -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_SSC_ReceiveFrame ( - AT91PS_SSC pSSC, - char *pBuffer, - unsigned int szBuffer, - char *pNextBuffer, - unsigned int szNextBuffer ) +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_SSC_ReceiveFrame */ +/** \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initialized with Next Buffer, 0 if PDC is busy */ +/**---------------------------------------------------------------------------- */ +__inline unsigned int AT91F_SSC_ReceiveFrame( AT91PS_SSC pSSC, + char * pBuffer, + unsigned int szBuffer, + char * pNextBuffer, + unsigned int szNextBuffer ) { return AT91F_PDC_ReceiveFrame( - (AT91PS_PDC) &(pSSC->SSC_RPR), + ( AT91PS_PDC ) &( pSSC->SSC_RPR ), pBuffer, szBuffer, pNextBuffer, - szNextBuffer); + szNextBuffer ); } -//*---------------------------------------------------------------------------- -//* \fn AT91F_SSC_SendFrame -//* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initialized with Next Buffer, 0 if PDC is busy -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_SSC_SendFrame( - AT91PS_SSC pSSC, - char *pBuffer, - unsigned int szBuffer, - char *pNextBuffer, - unsigned int szNextBuffer ) +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_SSC_SendFrame */ +/** \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initialized with Next Buffer, 0 if PDC is busy */ +/**---------------------------------------------------------------------------- */ +__inline unsigned int AT91F_SSC_SendFrame( AT91PS_SSC pSSC, + char * pBuffer, + unsigned int szBuffer, + char * pNextBuffer, + unsigned int szNextBuffer ) { return AT91F_PDC_SendFrame( - (AT91PS_PDC) &(pSSC->SSC_RPR), + ( AT91PS_PDC ) &( pSSC->SSC_RPR ), pBuffer, szBuffer, pNextBuffer, - szNextBuffer); + szNextBuffer ); } -//*---------------------------------------------------------------------------- -//* \fn AT91F_SSC_GetInterruptMaskStatus -//* \brief Return SSC Interrupt Mask Status -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_SSC_GetInterruptMaskStatus( // \return SSC Interrupt Mask Status - AT91PS_SSC pSsc) // \arg pointer to a SSC controller +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_SSC_GetInterruptMaskStatus */ +/** \brief Return SSC Interrupt Mask Status */ +/**---------------------------------------------------------------------------- */ +__inline unsigned int AT91F_SSC_GetInterruptMaskStatus( /* \return SSC Interrupt Mask Status */ + AT91PS_SSC pSsc ) /* \arg pointer to a SSC controller */ { - return pSsc->SSC_IMR; + return pSsc->SSC_IMR; } -//*---------------------------------------------------------------------------- -//* \fn AT91F_SSC_IsInterruptMasked -//* \brief Test if SSC Interrupt is Masked -//*---------------------------------------------------------------------------- -__inline int AT91F_SSC_IsInterruptMasked( - AT91PS_SSC pSsc, // \arg pointer to a SSC controller - unsigned int flag) // \arg flag to be tested +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_SSC_IsInterruptMasked */ +/** \brief Test if SSC Interrupt is Masked */ +/**---------------------------------------------------------------------------- */ +__inline int AT91F_SSC_IsInterruptMasked( AT91PS_SSC pSsc, /* \arg pointer to a SSC controller */ + unsigned int flag ) /* \arg flag to be tested */ { - return (AT91F_SSC_GetInterruptMaskStatus(pSsc) & flag); + return( AT91F_SSC_GetInterruptMaskStatus( pSsc ) & flag ); } /* ***************************************************************************** - SOFTWARE API FOR SPI - ***************************************************************************** */ -//*---------------------------------------------------------------------------- -//* \fn AT91F_SPI_Open -//* \brief Open a SPI Port -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_SPI_Open ( - const unsigned int null) // \arg -{ - /* NOT DEFINED AT THIS MOMENT */ - return ( 0 ); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_SPI_CfgCs -//* \brief Configure SPI chip select register -//*---------------------------------------------------------------------------- -__inline void AT91F_SPI_CfgCs ( - AT91PS_SPI pSPI, // pointer to a SPI controller - int cs, // SPI cs number (0 to 3) - int val) // chip select register -{ - //* Write to the CSR register - *(pSPI->SPI_CSR + cs) = val; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_SPI_EnableIt -//* \brief Enable SPI interrupt -//*---------------------------------------------------------------------------- -__inline void AT91F_SPI_EnableIt ( - AT91PS_SPI pSPI, // pointer to a SPI controller - unsigned int flag) // IT to be enabled -{ - //* Write to the IER register +* SOFTWARE API FOR SPI +***************************************************************************** */ +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_SPI_Open */ +/** \brief Open a SPI Port */ +/**---------------------------------------------------------------------------- */ +__inline unsigned int AT91F_SPI_Open( const unsigned int null ) /* \arg */ +{ + /* NOT DEFINED AT THIS MOMENT */ + return( 0 ); +} + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_SPI_CfgCs */ +/** \brief Configure SPI chip select register */ +/**---------------------------------------------------------------------------- */ +__inline void AT91F_SPI_CfgCs( AT91PS_SPI pSPI, /* pointer to a SPI controller */ + int cs, /* SPI cs number (0 to 3) */ + int val ) /* chip select register */ +{ + /** Write to the CSR register */ + *( pSPI->SPI_CSR + cs ) = val; +} + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_SPI_EnableIt */ +/** \brief Enable SPI interrupt */ +/**---------------------------------------------------------------------------- */ +__inline void AT91F_SPI_EnableIt( AT91PS_SPI pSPI, /* pointer to a SPI controller */ + unsigned int flag ) /* IT to be enabled */ +{ + /** Write to the IER register */ pSPI->SPI_IER = flag; } -//*---------------------------------------------------------------------------- -//* \fn AT91F_SPI_DisableIt -//* \brief Disable SPI interrupt -//*---------------------------------------------------------------------------- -__inline void AT91F_SPI_DisableIt ( - AT91PS_SPI pSPI, // pointer to a SPI controller - unsigned int flag) // IT to be disabled +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_SPI_DisableIt */ +/** \brief Disable SPI interrupt */ +/**---------------------------------------------------------------------------- */ +__inline void AT91F_SPI_DisableIt( AT91PS_SPI pSPI, /* pointer to a SPI controller */ + unsigned int flag ) /* IT to be disabled */ { - //* Write to the IDR register + /** Write to the IDR register */ pSPI->SPI_IDR = flag; } -//*---------------------------------------------------------------------------- -//* \fn AT91F_SPI_Reset -//* \brief Reset the SPI controller -//*---------------------------------------------------------------------------- -__inline void AT91F_SPI_Reset ( - AT91PS_SPI pSPI // pointer to a SPI controller - ) +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_SPI_Reset */ +/** \brief Reset the SPI controller */ +/**---------------------------------------------------------------------------- */ +__inline void AT91F_SPI_Reset( AT91PS_SPI pSPI /* pointer to a SPI controller */ + ) { - //* Write to the CR register + /** Write to the CR register */ pSPI->SPI_CR = AT91C_SPI_SWRST; } -//*---------------------------------------------------------------------------- -//* \fn AT91F_SPI_Enable -//* \brief Enable the SPI controller -//*---------------------------------------------------------------------------- -__inline void AT91F_SPI_Enable ( - AT91PS_SPI pSPI // pointer to a SPI controller - ) +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_SPI_Enable */ +/** \brief Enable the SPI controller */ +/**---------------------------------------------------------------------------- */ +__inline void AT91F_SPI_Enable( AT91PS_SPI pSPI /* pointer to a SPI controller */ + ) { - //* Write to the CR register + /** Write to the CR register */ pSPI->SPI_CR = AT91C_SPI_SPIEN; } -//*---------------------------------------------------------------------------- -//* \fn AT91F_SPI_Disable -//* \brief Disable the SPI controller -//*---------------------------------------------------------------------------- -__inline void AT91F_SPI_Disable ( - AT91PS_SPI pSPI // pointer to a SPI controller - ) +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_SPI_Disable */ +/** \brief Disable the SPI controller */ +/**---------------------------------------------------------------------------- */ +__inline void AT91F_SPI_Disable( AT91PS_SPI pSPI /* pointer to a SPI controller */ + ) { - //* Write to the CR register + /** Write to the CR register */ pSPI->SPI_CR = AT91C_SPI_SPIDIS; } -//*---------------------------------------------------------------------------- -//* \fn AT91F_SPI_CfgMode -//* \brief Enable the SPI controller -//*---------------------------------------------------------------------------- -__inline void AT91F_SPI_CfgMode ( - AT91PS_SPI pSPI, // pointer to a SPI controller - int mode) // mode register +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_SPI_CfgMode */ +/** \brief Enable the SPI controller */ +/**---------------------------------------------------------------------------- */ +__inline void AT91F_SPI_CfgMode( AT91PS_SPI pSPI, /* pointer to a SPI controller */ + int mode ) /* mode register */ { - //* Write to the MR register + /** Write to the MR register */ pSPI->SPI_MR = mode; } -//*---------------------------------------------------------------------------- -//* \fn AT91F_SPI_CfgPCS -//* \brief Switch to the correct PCS of SPI Mode Register : Fixed Peripheral Selected -//*---------------------------------------------------------------------------- -__inline void AT91F_SPI_CfgPCS ( - AT91PS_SPI pSPI, // pointer to a SPI controller - char PCS_Device) // PCS of the Device +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_SPI_CfgPCS */ +/** \brief Switch to the correct PCS of SPI Mode Register : Fixed Peripheral Selected */ +/**---------------------------------------------------------------------------- */ +__inline void AT91F_SPI_CfgPCS( AT91PS_SPI pSPI, /* pointer to a SPI controller */ + char PCS_Device ) /* PCS of the Device */ { - //* Write to the MR register + /** Write to the MR register */ pSPI->SPI_MR &= 0xFFF0FFFF; - pSPI->SPI_MR |= ( (PCS_Device<<16) & AT91C_SPI_PCS ); + pSPI->SPI_MR |= ( ( PCS_Device << 16 ) & AT91C_SPI_PCS ); } -//*---------------------------------------------------------------------------- -//* \fn AT91F_SPI_ReceiveFrame -//* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initializaed with Next Buffer, 0 if PDC is busy -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_SPI_ReceiveFrame ( - AT91PS_SPI pSPI, - char *pBuffer, - unsigned int szBuffer, - char *pNextBuffer, - unsigned int szNextBuffer ) +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_SPI_ReceiveFrame */ +/** \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initialized with Next Buffer, 0 if PDC is busy */ +/**---------------------------------------------------------------------------- */ +__inline unsigned int AT91F_SPI_ReceiveFrame( AT91PS_SPI pSPI, + char * pBuffer, + unsigned int szBuffer, + char * pNextBuffer, + unsigned int szNextBuffer ) { return AT91F_PDC_ReceiveFrame( - (AT91PS_PDC) &(pSPI->SPI_RPR), + ( AT91PS_PDC ) &( pSPI->SPI_RPR ), pBuffer, szBuffer, pNextBuffer, - szNextBuffer); + szNextBuffer ); } -//*---------------------------------------------------------------------------- -//* \fn AT91F_SPI_SendFrame -//* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initializaed with Next Buffer, 0 if PDC is bSPIy -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_SPI_SendFrame( - AT91PS_SPI pSPI, - char *pBuffer, - unsigned int szBuffer, - char *pNextBuffer, - unsigned int szNextBuffer ) +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_SPI_SendFrame */ +/** \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initialized with Next Buffer, 0 if PDC is bSPIy */ +/**---------------------------------------------------------------------------- */ +__inline unsigned int AT91F_SPI_SendFrame( AT91PS_SPI pSPI, + char * pBuffer, + unsigned int szBuffer, + char * pNextBuffer, + unsigned int szNextBuffer ) { return AT91F_PDC_SendFrame( - (AT91PS_PDC) &(pSPI->SPI_RPR), + ( AT91PS_PDC ) &( pSPI->SPI_RPR ), pBuffer, szBuffer, pNextBuffer, - szNextBuffer); + szNextBuffer ); } -//*---------------------------------------------------------------------------- -//* \fn AT91F_SPI_Close -//* \brief Close SPI: disable IT disable transfert, close PDC -//*---------------------------------------------------------------------------- -__inline void AT91F_SPI_Close ( - AT91PS_SPI pSPI) // \arg pointer to a SPI controller +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_SPI_Close */ +/** \brief Close SPI: disable IT disable transfert, close PDC */ +/**---------------------------------------------------------------------------- */ +__inline void AT91F_SPI_Close( AT91PS_SPI pSPI ) /* \arg pointer to a SPI controller */ { - //* Reset all the Chip Select register - pSPI->SPI_CSR[0] = 0 ; - pSPI->SPI_CSR[1] = 0 ; - pSPI->SPI_CSR[2] = 0 ; - pSPI->SPI_CSR[3] = 0 ; + /** Reset all the Chip Select register */ + pSPI->SPI_CSR[ 0 ] = 0; + pSPI->SPI_CSR[ 1 ] = 0; + pSPI->SPI_CSR[ 2 ] = 0; + pSPI->SPI_CSR[ 3 ] = 0; - //* Reset the SPI mode - pSPI->SPI_MR = 0 ; + /** Reset the SPI mode */ + pSPI->SPI_MR = 0; - //* Disable all interrupts - pSPI->SPI_IDR = 0xFFFFFFFF ; + /** Disable all interrupts */ + pSPI->SPI_IDR = 0xFFFFFFFF; - //* Abort the Peripheral Data Transfers - AT91F_PDC_Close((AT91PS_PDC) &(pSPI->SPI_RPR)); + /** Abort the Peripheral Data Transfers */ + AT91F_PDC_Close( ( AT91PS_PDC ) &( pSPI->SPI_RPR ) ); - //* Disable receiver and transmitter and stop any activity immediately + /** Disable receiver and transmitter and stop any activity immediately */ pSPI->SPI_CR = AT91C_SPI_SPIDIS; } -//*---------------------------------------------------------------------------- -//* \fn AT91F_SPI_PutChar -//* \brief Send a character,does not check if ready to send -//*---------------------------------------------------------------------------- -__inline void AT91F_SPI_PutChar ( - AT91PS_SPI pSPI, - unsigned int character, - unsigned int cs_number ) +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_SPI_PutChar */ +/** \brief Send a character,does not check if ready to send */ +/**---------------------------------------------------------------------------- */ +__inline void AT91F_SPI_PutChar( AT91PS_SPI pSPI, + unsigned int character, + unsigned int cs_number ) { unsigned int value_for_cs; - value_for_cs = (~(1 << cs_number)) & 0xF; //Place a zero among a 4 ONEs number - pSPI->SPI_TDR = (character & 0xFFFF) | (value_for_cs << 16); + + value_for_cs = ( ~( 1 << cs_number ) ) & 0xF; /*Place a zero among a 4 ONEs number */ + pSPI->SPI_TDR = ( character & 0xFFFF ) | ( value_for_cs << 16 ); } -//*---------------------------------------------------------------------------- -//* \fn AT91F_SPI_GetChar -//* \brief Receive a character,does not check if a character is available -//*---------------------------------------------------------------------------- -__inline int AT91F_SPI_GetChar ( - const AT91PS_SPI pSPI) +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_SPI_GetChar */ +/** \brief Receive a character,does not check if a character is available */ +/**---------------------------------------------------------------------------- */ +__inline int AT91F_SPI_GetChar( const AT91PS_SPI pSPI ) { - return((pSPI->SPI_RDR) & 0xFFFF); + return( ( pSPI->SPI_RDR ) & 0xFFFF ); } -//*---------------------------------------------------------------------------- -//* \fn AT91F_SPI_GetInterruptMaskStatus -//* \brief Return SPI Interrupt Mask Status -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_SPI_GetInterruptMaskStatus( // \return SPI Interrupt Mask Status - AT91PS_SPI pSpi) // \arg pointer to a SPI controller +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_SPI_GetInterruptMaskStatus */ +/** \brief Return SPI Interrupt Mask Status */ +/**---------------------------------------------------------------------------- */ +__inline unsigned int AT91F_SPI_GetInterruptMaskStatus( /* \return SPI Interrupt Mask Status */ + AT91PS_SPI pSpi ) /* \arg pointer to a SPI controller */ { - return pSpi->SPI_IMR; + return pSpi->SPI_IMR; } -//*---------------------------------------------------------------------------- -//* \fn AT91F_SPI_IsInterruptMasked -//* \brief Test if SPI Interrupt is Masked -//*---------------------------------------------------------------------------- -__inline int AT91F_SPI_IsInterruptMasked( - AT91PS_SPI pSpi, // \arg pointer to a SPI controller - unsigned int flag) // \arg flag to be tested +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_SPI_IsInterruptMasked */ +/** \brief Test if SPI Interrupt is Masked */ +/**---------------------------------------------------------------------------- */ +__inline int AT91F_SPI_IsInterruptMasked( AT91PS_SPI pSpi, /* \arg pointer to a SPI controller */ + unsigned int flag ) /* \arg flag to be tested */ { - return (AT91F_SPI_GetInterruptMaskStatus(pSpi) & flag); + return( AT91F_SPI_GetInterruptMaskStatus( pSpi ) & flag ); } /* ***************************************************************************** - SOFTWARE API FOR PWMC - ***************************************************************************** */ -//*---------------------------------------------------------------------------- -//* \fn AT91F_PWM_GetStatus -//* \brief Return PWM Interrupt Status -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_PWMC_GetStatus( // \return PWM Interrupt Status - AT91PS_PWMC pPWM) // pointer to a PWM controller +* SOFTWARE API FOR PWMC +***************************************************************************** */ +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PWM_GetStatus */ +/** \brief Return PWM Interrupt Status */ +/**---------------------------------------------------------------------------- */ +__inline unsigned int AT91F_PWMC_GetStatus( /* \return PWM Interrupt Status */ + AT91PS_PWMC pPWM ) /* pointer to a PWM controller */ { return pPWM->PWMC_SR; } -//*---------------------------------------------------------------------------- -//* \fn AT91F_PWM_InterruptEnable -//* \brief Enable PWM Interrupt -//*---------------------------------------------------------------------------- -__inline void AT91F_PWMC_InterruptEnable( - AT91PS_PWMC pPwm, // \arg pointer to a PWM controller - unsigned int flag) // \arg PWM interrupt to be enabled +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PWM_InterruptEnable */ +/** \brief Enable PWM Interrupt */ +/**---------------------------------------------------------------------------- */ +__inline void AT91F_PWMC_InterruptEnable( AT91PS_PWMC pPwm, /* \arg pointer to a PWM controller */ + unsigned int flag ) /* \arg PWM interrupt to be enabled */ { - pPwm->PWMC_IER = flag; + pPwm->PWMC_IER = flag; } -//*---------------------------------------------------------------------------- -//* \fn AT91F_PWM_InterruptDisable -//* \brief Disable PWM Interrupt -//*---------------------------------------------------------------------------- -__inline void AT91F_PWMC_InterruptDisable( - AT91PS_PWMC pPwm, // \arg pointer to a PWM controller - unsigned int flag) // \arg PWM interrupt to be disabled +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PWM_InterruptDisable */ +/** \brief Disable PWM Interrupt */ +/**---------------------------------------------------------------------------- */ +__inline void AT91F_PWMC_InterruptDisable( AT91PS_PWMC pPwm, /* \arg pointer to a PWM controller */ + unsigned int flag ) /* \arg PWM interrupt to be disabled */ { - pPwm->PWMC_IDR = flag; + pPwm->PWMC_IDR = flag; } -//*---------------------------------------------------------------------------- -//* \fn AT91F_PWM_GetInterruptMaskStatus -//* \brief Return PWM Interrupt Mask Status -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_PWMC_GetInterruptMaskStatus( // \return PWM Interrupt Mask Status - AT91PS_PWMC pPwm) // \arg pointer to a PWM controller +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PWM_GetInterruptMaskStatus */ +/** \brief Return PWM Interrupt Mask Status */ +/**---------------------------------------------------------------------------- */ +__inline unsigned int AT91F_PWMC_GetInterruptMaskStatus( /* \return PWM Interrupt Mask Status */ + AT91PS_PWMC pPwm ) /* \arg pointer to a PWM controller */ { - return pPwm->PWMC_IMR; + return pPwm->PWMC_IMR; } -//*---------------------------------------------------------------------------- -//* \fn AT91F_PWM_IsInterruptMasked -//* \brief Test if PWM Interrupt is Masked -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_PWMC_IsInterruptMasked( - AT91PS_PWMC pPWM, // \arg pointer to a PWM controller - unsigned int flag) // \arg flag to be tested +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PWM_IsInterruptMasked */ +/** \brief Test if PWM Interrupt is Masked */ +/**---------------------------------------------------------------------------- */ +__inline unsigned int AT91F_PWMC_IsInterruptMasked( AT91PS_PWMC pPWM, /* \arg pointer to a PWM controller */ + unsigned int flag ) /* \arg flag to be tested */ { - return (AT91F_PWMC_GetInterruptMaskStatus(pPWM) & flag); + return( AT91F_PWMC_GetInterruptMaskStatus( pPWM ) & flag ); } -//*---------------------------------------------------------------------------- -//* \fn AT91F_PWM_IsStatusSet -//* \brief Test if PWM Interrupt is Set -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_PWMC_IsStatusSet( - AT91PS_PWMC pPWM, // \arg pointer to a PWM controller - unsigned int flag) // \arg flag to be tested +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PWM_IsStatusSet */ +/** \brief Test if PWM Interrupt is Set */ +/**---------------------------------------------------------------------------- */ +__inline unsigned int AT91F_PWMC_IsStatusSet( AT91PS_PWMC pPWM, /* \arg pointer to a PWM controller */ + unsigned int flag ) /* \arg flag to be tested */ { - return (AT91F_PWMC_GetStatus(pPWM) & flag); + return( AT91F_PWMC_GetStatus( pPWM ) & flag ); } -//*---------------------------------------------------------------------------- -//* \fn AT91F_PWM_CfgChannel -//* \brief Test if PWM Interrupt is Set -//*---------------------------------------------------------------------------- -__inline void AT91F_PWMC_CfgChannel( - AT91PS_PWMC pPWM, // \arg pointer to a PWM controller - unsigned int channelId, // \arg PWM channel ID - unsigned int mode, // \arg PWM mode - unsigned int period, // \arg PWM period - unsigned int duty) // \arg PWM duty cycle +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PWM_CfgChannel */ +/** \brief Test if PWM Interrupt is Set */ +/**---------------------------------------------------------------------------- */ +__inline void AT91F_PWMC_CfgChannel( AT91PS_PWMC pPWM, /* \arg pointer to a PWM controller */ + unsigned int channelId, /* \arg PWM channel ID */ + unsigned int mode, /* \arg PWM mode */ + unsigned int period, /* \arg PWM period */ + unsigned int duty ) /* \arg PWM duty cycle */ { - pPWM->PWMC_CH[channelId].PWMC_CMR = mode; - pPWM->PWMC_CH[channelId].PWMC_CDTYR = duty; - pPWM->PWMC_CH[channelId].PWMC_CPRDR = period; + pPWM->PWMC_CH[ channelId ].PWMC_CMR = mode; + pPWM->PWMC_CH[ channelId ].PWMC_CDTYR = duty; + pPWM->PWMC_CH[ channelId ].PWMC_CPRDR = period; } -//*---------------------------------------------------------------------------- -//* \fn AT91F_PWM_StartChannel -//* \brief Enable channel -//*---------------------------------------------------------------------------- -__inline void AT91F_PWMC_StartChannel( - AT91PS_PWMC pPWM, // \arg pointer to a PWM controller - unsigned int flag) // \arg Channels IDs to be enabled +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PWM_StartChannel */ +/** \brief Enable channel */ +/**---------------------------------------------------------------------------- */ +__inline void AT91F_PWMC_StartChannel( AT91PS_PWMC pPWM, /* \arg pointer to a PWM controller */ + unsigned int flag ) /* \arg Channels IDs to be enabled */ { pPWM->PWMC_ENA = flag; } -//*---------------------------------------------------------------------------- -//* \fn AT91F_PWM_StopChannel -//* \brief Disable channel -//*---------------------------------------------------------------------------- -__inline void AT91F_PWMC_StopChannel( - AT91PS_PWMC pPWM, // \arg pointer to a PWM controller - unsigned int flag) // \arg Channels IDs to be enabled +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PWM_StopChannel */ +/** \brief Disable channel */ +/**---------------------------------------------------------------------------- */ +__inline void AT91F_PWMC_StopChannel( AT91PS_PWMC pPWM, /* \arg pointer to a PWM controller */ + unsigned int flag ) /* \arg Channels IDs to be enabled */ { pPWM->PWMC_DIS = flag; } -//*---------------------------------------------------------------------------- -//* \fn AT91F_PWM_UpdateChannel -//* \brief Update Period or Duty Cycle -//*---------------------------------------------------------------------------- -__inline void AT91F_PWMC_UpdateChannel( - AT91PS_PWMC pPWM, // \arg pointer to a PWM controller - unsigned int channelId, // \arg PWM channel ID - unsigned int update) // \arg Channels IDs to be enabled +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PWM_UpdateChannel */ +/** \brief Update Period or Duty Cycle */ +/**---------------------------------------------------------------------------- */ +__inline void AT91F_PWMC_UpdateChannel( AT91PS_PWMC pPWM, /* \arg pointer to a PWM controller */ + unsigned int channelId, /* \arg PWM channel ID */ + unsigned int update ) /* \arg Channels IDs to be enabled */ { - pPWM->PWMC_CH[channelId].PWMC_CUPDR = update; + pPWM->PWMC_CH[ channelId ].PWMC_CUPDR = update; } /* ***************************************************************************** - SOFTWARE API FOR TC - ***************************************************************************** */ -//*---------------------------------------------------------------------------- -//* \fn AT91F_TC_InterruptEnable -//* \brief Enable TC Interrupt -//*---------------------------------------------------------------------------- -__inline void AT91F_TC_InterruptEnable( - AT91PS_TC pTc, // \arg pointer to a TC controller - unsigned int flag) // \arg TC interrupt to be enabled +* SOFTWARE API FOR TC +***************************************************************************** */ +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_TC_InterruptEnable */ +/** \brief Enable TC Interrupt */ +/**---------------------------------------------------------------------------- */ +__inline void AT91F_TC_InterruptEnable( AT91PS_TC pTc, /* \arg pointer to a TC controller */ + unsigned int flag ) /* \arg TC interrupt to be enabled */ { - pTc->TC_IER = flag; + pTc->TC_IER = flag; } -//*---------------------------------------------------------------------------- -//* \fn AT91F_TC_InterruptDisable -//* \brief Disable TC Interrupt -//*---------------------------------------------------------------------------- -__inline void AT91F_TC_InterruptDisable( - AT91PS_TC pTc, // \arg pointer to a TC controller - unsigned int flag) // \arg TC interrupt to be disabled +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_TC_InterruptDisable */ +/** \brief Disable TC Interrupt */ +/**---------------------------------------------------------------------------- */ +__inline void AT91F_TC_InterruptDisable( AT91PS_TC pTc, /* \arg pointer to a TC controller */ + unsigned int flag ) /* \arg TC interrupt to be disabled */ { - pTc->TC_IDR = flag; + pTc->TC_IDR = flag; } -//*---------------------------------------------------------------------------- -//* \fn AT91F_TC_GetInterruptMaskStatus -//* \brief Return TC Interrupt Mask Status -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_TC_GetInterruptMaskStatus( // \return TC Interrupt Mask Status - AT91PS_TC pTc) // \arg pointer to a TC controller +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_TC_GetInterruptMaskStatus */ +/** \brief Return TC Interrupt Mask Status */ +/**---------------------------------------------------------------------------- */ +__inline unsigned int AT91F_TC_GetInterruptMaskStatus( /* \return TC Interrupt Mask Status */ + AT91PS_TC pTc ) /* \arg pointer to a TC controller */ { - return pTc->TC_IMR; + return pTc->TC_IMR; } -//*---------------------------------------------------------------------------- -//* \fn AT91F_TC_IsInterruptMasked -//* \brief Test if TC Interrupt is Masked -//*---------------------------------------------------------------------------- -__inline int AT91F_TC_IsInterruptMasked( - AT91PS_TC pTc, // \arg pointer to a TC controller - unsigned int flag) // \arg flag to be tested +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_TC_IsInterruptMasked */ +/** \brief Test if TC Interrupt is Masked */ +/**---------------------------------------------------------------------------- */ +__inline int AT91F_TC_IsInterruptMasked( AT91PS_TC pTc, /* \arg pointer to a TC controller */ + unsigned int flag ) /* \arg flag to be tested */ { - return (AT91F_TC_GetInterruptMaskStatus(pTc) & flag); + return( AT91F_TC_GetInterruptMaskStatus( pTc ) & flag ); } /* ***************************************************************************** - SOFTWARE API FOR PMC - ***************************************************************************** */ -//*---------------------------------------------------------------------------- -//* \fn AT91F_PMC_CfgSysClkEnableReg -//* \brief Configure the System Clock Enable Register of the PMC controller -//*---------------------------------------------------------------------------- -__inline void AT91F_PMC_CfgSysClkEnableReg ( - AT91PS_PMC pPMC, // \arg pointer to PMC controller - unsigned int mode) -{ - //* Write to the SCER register +* SOFTWARE API FOR PMC +***************************************************************************** */ +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PMC_CfgSysClkEnableReg */ +/** \brief Configure the System Clock Enable Register of the PMC controller */ +/**---------------------------------------------------------------------------- */ +__inline void AT91F_PMC_CfgSysClkEnableReg( AT91PS_PMC pPMC, /* \arg pointer to PMC controller */ + unsigned int mode ) +{ + /** Write to the SCER register */ pPMC->PMC_SCER = mode; } -//*---------------------------------------------------------------------------- -//* \fn AT91F_PMC_CfgSysClkDisableReg -//* \brief Configure the System Clock Disable Register of the PMC controller -//*---------------------------------------------------------------------------- -__inline void AT91F_PMC_CfgSysClkDisableReg ( - AT91PS_PMC pPMC, // \arg pointer to PMC controller - unsigned int mode) +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PMC_CfgSysClkDisableReg */ +/** \brief Configure the System Clock Disable Register of the PMC controller */ +/**---------------------------------------------------------------------------- */ +__inline void AT91F_PMC_CfgSysClkDisableReg( AT91PS_PMC pPMC, /* \arg pointer to PMC controller */ + unsigned int mode ) { - //* Write to the SCDR register + /** Write to the SCDR register */ pPMC->PMC_SCDR = mode; } -//*---------------------------------------------------------------------------- -//* \fn AT91F_PMC_GetSysClkStatusReg -//* \brief Return the System Clock Status Register of the PMC controller -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_PMC_GetSysClkStatusReg ( - AT91PS_PMC pPMC // pointer to a CAN controller - ) +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PMC_GetSysClkStatusReg */ +/** \brief Return the System Clock Status Register of the PMC controller */ +/**---------------------------------------------------------------------------- */ +__inline unsigned int AT91F_PMC_GetSysClkStatusReg( AT91PS_PMC pPMC /* pointer to a CAN controller */ + ) { return pPMC->PMC_SCSR; } -//*---------------------------------------------------------------------------- -//* \fn AT91F_PMC_EnablePeriphClock -//* \brief Enable peripheral clock -//*---------------------------------------------------------------------------- -__inline void AT91F_PMC_EnablePeriphClock ( - AT91PS_PMC pPMC, // \arg pointer to PMC controller - unsigned int periphIds) // \arg IDs of peripherals to enable +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PMC_EnablePeriphClock */ +/** \brief Enable peripheral clock */ +/**---------------------------------------------------------------------------- */ +__inline void AT91F_PMC_EnablePeriphClock( AT91PS_PMC pPMC, /* \arg pointer to PMC controller */ + unsigned int periphIds ) /* \arg IDs of peripherals to enable */ { pPMC->PMC_PCER = periphIds; } -//*---------------------------------------------------------------------------- -//* \fn AT91F_PMC_DisablePeriphClock -//* \brief Disable peripheral clock -//*---------------------------------------------------------------------------- -__inline void AT91F_PMC_DisablePeriphClock ( - AT91PS_PMC pPMC, // \arg pointer to PMC controller - unsigned int periphIds) // \arg IDs of peripherals to enable +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PMC_DisablePeriphClock */ +/** \brief Disable peripheral clock */ +/**---------------------------------------------------------------------------- */ +__inline void AT91F_PMC_DisablePeriphClock( AT91PS_PMC pPMC, /* \arg pointer to PMC controller */ + unsigned int periphIds ) /* \arg IDs of peripherals to enable */ { pPMC->PMC_PCDR = periphIds; } -//*---------------------------------------------------------------------------- -//* \fn AT91F_PMC_GetPeriphClock -//* \brief Get peripheral clock status -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_PMC_GetPeriphClock ( - AT91PS_PMC pPMC) // \arg pointer to PMC controller +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PMC_GetPeriphClock */ +/** \brief Get peripheral clock status */ +/**---------------------------------------------------------------------------- */ +__inline unsigned int AT91F_PMC_GetPeriphClock( AT91PS_PMC pPMC ) /* \arg pointer to PMC controller */ { return pPMC->PMC_PCSR; } -//*---------------------------------------------------------------------------- -//* \fn AT91F_CKGR_CfgMainOscillatorReg -//* \brief Cfg the main oscillator -//*---------------------------------------------------------------------------- -__inline void AT91F_CKGR_CfgMainOscillatorReg ( - AT91PS_CKGR pCKGR, // \arg pointer to CKGR controller - unsigned int mode) +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_CKGR_CfgMainOscillatorReg */ +/** \brief Cfg the main oscillator */ +/**---------------------------------------------------------------------------- */ +__inline void AT91F_CKGR_CfgMainOscillatorReg( AT91PS_CKGR pCKGR, /* \arg pointer to CKGR controller */ + unsigned int mode ) { pCKGR->CKGR_MOR = mode; } -//*---------------------------------------------------------------------------- -//* \fn AT91F_CKGR_GetMainOscillatorReg -//* \brief Cfg the main oscillator -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_CKGR_GetMainOscillatorReg ( - AT91PS_CKGR pCKGR) // \arg pointer to CKGR controller +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_CKGR_GetMainOscillatorReg */ +/** \brief Cfg the main oscillator */ +/**---------------------------------------------------------------------------- */ +__inline unsigned int AT91F_CKGR_GetMainOscillatorReg( AT91PS_CKGR pCKGR ) /* \arg pointer to CKGR controller */ { return pCKGR->CKGR_MOR; } -//*---------------------------------------------------------------------------- -//* \fn AT91F_CKGR_EnableMainOscillator -//* \brief Enable the main oscillator -//*---------------------------------------------------------------------------- -__inline void AT91F_CKGR_EnableMainOscillator( - AT91PS_CKGR pCKGR) // \arg pointer to CKGR controller +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_CKGR_EnableMainOscillator */ +/** \brief Enable the main oscillator */ +/**---------------------------------------------------------------------------- */ +__inline void AT91F_CKGR_EnableMainOscillator( AT91PS_CKGR pCKGR ) /* \arg pointer to CKGR controller */ { pCKGR->CKGR_MOR |= AT91C_CKGR_MOSCEN; } -//*---------------------------------------------------------------------------- -//* \fn AT91F_CKGR_DisableMainOscillator -//* \brief Disable the main oscillator -//*---------------------------------------------------------------------------- -__inline void AT91F_CKGR_DisableMainOscillator ( - AT91PS_CKGR pCKGR) // \arg pointer to CKGR controller +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_CKGR_DisableMainOscillator */ +/** \brief Disable the main oscillator */ +/**---------------------------------------------------------------------------- */ +__inline void AT91F_CKGR_DisableMainOscillator( AT91PS_CKGR pCKGR ) /* \arg pointer to CKGR controller */ { pCKGR->CKGR_MOR &= ~AT91C_CKGR_MOSCEN; } -//*---------------------------------------------------------------------------- -//* \fn AT91F_CKGR_CfgMainOscStartUpTime -//* \brief Cfg MOR Register according to the main osc startup time -//*---------------------------------------------------------------------------- -__inline void AT91F_CKGR_CfgMainOscStartUpTime ( - AT91PS_CKGR pCKGR, // \arg pointer to CKGR controller - unsigned int startup_time, // \arg main osc startup time in microsecond (us) - unsigned int slowClock) // \arg slowClock in Hz +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_CKGR_CfgMainOscStartUpTime */ +/** \brief Cfg MOR Register according to the main osc startup time */ +/**---------------------------------------------------------------------------- */ +__inline void AT91F_CKGR_CfgMainOscStartUpTime( AT91PS_CKGR pCKGR, /* \arg pointer to CKGR controller */ + unsigned int startup_time, /* \arg main osc startup time in microsecond (us) */ + unsigned int slowClock ) /* \arg slowClock in Hz */ { pCKGR->CKGR_MOR &= ~AT91C_CKGR_OSCOUNT; - pCKGR->CKGR_MOR |= ((slowClock * startup_time)/(8*1000000)) << 8; + pCKGR->CKGR_MOR |= ( ( slowClock * startup_time ) / ( 8 * 1000000 ) ) << 8; } -//*---------------------------------------------------------------------------- -//* \fn AT91F_CKGR_GetMainClockFreqReg -//* \brief Cfg the main oscillator -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_CKGR_GetMainClockFreqReg ( - AT91PS_CKGR pCKGR) // \arg pointer to CKGR controller +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_CKGR_GetMainClockFreqReg */ +/** \brief Cfg the main oscillator */ +/**---------------------------------------------------------------------------- */ +__inline unsigned int AT91F_CKGR_GetMainClockFreqReg( AT91PS_CKGR pCKGR ) /* \arg pointer to CKGR controller */ { return pCKGR->CKGR_MCFR; } -//*---------------------------------------------------------------------------- -//* \fn AT91F_CKGR_GetMainClock -//* \brief Return Main clock in Hz -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_CKGR_GetMainClock ( - AT91PS_CKGR pCKGR, // \arg pointer to CKGR controller - unsigned int slowClock) // \arg slowClock in Hz +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_CKGR_GetMainClock */ +/** \brief Return Main clock in Hz */ +/**---------------------------------------------------------------------------- */ +__inline unsigned int AT91F_CKGR_GetMainClock( AT91PS_CKGR pCKGR, /* \arg pointer to CKGR controller */ + unsigned int slowClock ) /* \arg slowClock in Hz */ { - return ((pCKGR->CKGR_MCFR & AT91C_CKGR_MAINF) * slowClock) >> 4; + return ( ( pCKGR->CKGR_MCFR & AT91C_CKGR_MAINF ) * slowClock ) >> 4; } -//*---------------------------------------------------------------------------- -//* \fn AT91F_PMC_CfgMCKReg -//* \brief Cfg Master Clock Register -//*---------------------------------------------------------------------------- -__inline void AT91F_PMC_CfgMCKReg ( - AT91PS_PMC pPMC, // \arg pointer to PMC controller - unsigned int mode) +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PMC_CfgMCKReg */ +/** \brief Cfg Master Clock Register */ +/**---------------------------------------------------------------------------- */ +__inline void AT91F_PMC_CfgMCKReg( AT91PS_PMC pPMC, /* \arg pointer to PMC controller */ + unsigned int mode ) { pPMC->PMC_MCKR = mode; } -//*---------------------------------------------------------------------------- -//* \fn AT91F_PMC_GetMCKReg -//* \brief Return Master Clock Register -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_PMC_GetMCKReg( - AT91PS_PMC pPMC) // \arg pointer to PMC controller +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PMC_GetMCKReg */ +/** \brief Return Master Clock Register */ +/**---------------------------------------------------------------------------- */ +__inline unsigned int AT91F_PMC_GetMCKReg( AT91PS_PMC pPMC ) /* \arg pointer to PMC controller */ { return pPMC->PMC_MCKR; } -//*------------------------------------------------------------------------------ -//* \fn AT91F_PMC_GetMasterClock -//* \brief Return master clock in Hz which correponds to processor clock for ARM7 -//*------------------------------------------------------------------------------ -__inline unsigned int AT91F_PMC_GetMasterClock ( - AT91PS_PMC pPMC, // \arg pointer to PMC controller - AT91PS_CKGR pCKGR, // \arg pointer to CKGR controller - unsigned int slowClock) // \arg slowClock in Hz +/**------------------------------------------------------------------------------ */ +/** \fn AT91F_PMC_GetMasterClock */ +/** \brief Return master clock in Hz which corresponds to processor clock for ARM7 */ +/**------------------------------------------------------------------------------ */ +__inline unsigned int AT91F_PMC_GetMasterClock( AT91PS_PMC pPMC, /* \arg pointer to PMC controller */ + AT91PS_CKGR pCKGR, /* \arg pointer to CKGR controller */ + unsigned int slowClock ) /* \arg slowClock in Hz */ { unsigned int reg = pPMC->PMC_MCKR; - unsigned int prescaler = (1 << ((reg & AT91C_PMC_PRES) >> 2)); + unsigned int prescaler = ( 1 << ( ( reg & AT91C_PMC_PRES ) >> 2 ) ); unsigned int pllDivider, pllMultiplier; - switch (reg & AT91C_PMC_CSS) { - case AT91C_PMC_CSS_SLOW_CLK: // Slow clock selected + switch( reg & AT91C_PMC_CSS ) + { + case AT91C_PMC_CSS_SLOW_CLK: /* Slow clock selected */ return slowClock / prescaler; - case AT91C_PMC_CSS_MAIN_CLK: // Main clock is selected - return AT91F_CKGR_GetMainClock(pCKGR, slowClock) / prescaler; - case AT91C_PMC_CSS_PLL_CLK: // PLLB clock is selected + + case AT91C_PMC_CSS_MAIN_CLK: /* Main clock is selected */ + return AT91F_CKGR_GetMainClock( pCKGR, slowClock ) / prescaler; + + case AT91C_PMC_CSS_PLL_CLK: /* PLLB clock is selected */ reg = pCKGR->CKGR_PLLR; - pllDivider = (reg & AT91C_CKGR_DIV); - pllMultiplier = ((reg & AT91C_CKGR_MUL) >> 16) + 1; - return AT91F_CKGR_GetMainClock(pCKGR, slowClock) / pllDivider * pllMultiplier / prescaler; + pllDivider = ( reg & AT91C_CKGR_DIV ); + pllMultiplier = ( ( reg & AT91C_CKGR_MUL ) >> 16 ) + 1; + return AT91F_CKGR_GetMainClock( pCKGR, slowClock ) / pllDivider * pllMultiplier / prescaler; } + return 0; } -//*---------------------------------------------------------------------------- -//* \fn AT91F_PMC_EnablePCK -//* \brief Enable peripheral clock -//*---------------------------------------------------------------------------- -__inline void AT91F_PMC_EnablePCK ( - AT91PS_PMC pPMC, // \arg pointer to PMC controller - unsigned int pck, // \arg Peripheral clock identifier 0 .. 7 - unsigned int mode) +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PMC_EnablePCK */ +/** \brief Enable peripheral clock */ +/**---------------------------------------------------------------------------- */ +__inline void AT91F_PMC_EnablePCK( AT91PS_PMC pPMC, /* \arg pointer to PMC controller */ + unsigned int pck, /* \arg Peripheral clock identifier 0 .. 7 */ + unsigned int mode ) { - pPMC->PMC_PCKR[pck] = mode; - pPMC->PMC_SCER = (1 << pck) << 8; + pPMC->PMC_PCKR[ pck ] = mode; + pPMC->PMC_SCER = ( 1 << pck ) << 8; } -//*---------------------------------------------------------------------------- -//* \fn AT91F_PMC_DisablePCK -//* \brief Enable peripheral clock -//*---------------------------------------------------------------------------- -__inline void AT91F_PMC_DisablePCK ( - AT91PS_PMC pPMC, // \arg pointer to PMC controller - unsigned int pck) // \arg Peripheral clock identifier 0 .. 7 +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PMC_DisablePCK */ +/** \brief Enable peripheral clock */ +/**---------------------------------------------------------------------------- */ +__inline void AT91F_PMC_DisablePCK( AT91PS_PMC pPMC, /* \arg pointer to PMC controller */ + unsigned int pck ) /* \arg Peripheral clock identifier 0 .. 7 */ { - pPMC->PMC_SCDR = (1 << pck) << 8; + pPMC->PMC_SCDR = ( 1 << pck ) << 8; } -//*---------------------------------------------------------------------------- -//* \fn AT91F_PMC_EnableIt -//* \brief Enable PMC interrupt -//*---------------------------------------------------------------------------- -__inline void AT91F_PMC_EnableIt ( - AT91PS_PMC pPMC, // pointer to a PMC controller - unsigned int flag) // IT to be enabled +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PMC_EnableIt */ +/** \brief Enable PMC interrupt */ +/**---------------------------------------------------------------------------- */ +__inline void AT91F_PMC_EnableIt( AT91PS_PMC pPMC, /* pointer to a PMC controller */ + unsigned int flag ) /* IT to be enabled */ { - //* Write to the IER register + /** Write to the IER register */ pPMC->PMC_IER = flag; } -//*---------------------------------------------------------------------------- -//* \fn AT91F_PMC_DisableIt -//* \brief Disable PMC interrupt -//*---------------------------------------------------------------------------- -__inline void AT91F_PMC_DisableIt ( - AT91PS_PMC pPMC, // pointer to a PMC controller - unsigned int flag) // IT to be disabled +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PMC_DisableIt */ +/** \brief Disable PMC interrupt */ +/**---------------------------------------------------------------------------- */ +__inline void AT91F_PMC_DisableIt( AT91PS_PMC pPMC, /* pointer to a PMC controller */ + unsigned int flag ) /* IT to be disabled */ { - //* Write to the IDR register + /** Write to the IDR register */ pPMC->PMC_IDR = flag; } -//*---------------------------------------------------------------------------- -//* \fn AT91F_PMC_GetStatus -//* \brief Return PMC Interrupt Status -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_PMC_GetStatus( // \return PMC Interrupt Status - AT91PS_PMC pPMC) // pointer to a PMC controller +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PMC_GetStatus */ +/** \brief Return PMC Interrupt Status */ +/**---------------------------------------------------------------------------- */ +__inline unsigned int AT91F_PMC_GetStatus( /* \return PMC Interrupt Status */ + AT91PS_PMC pPMC ) /* pointer to a PMC controller */ { return pPMC->PMC_SR; } -//*---------------------------------------------------------------------------- -//* \fn AT91F_PMC_GetInterruptMaskStatus -//* \brief Return PMC Interrupt Mask Status -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_PMC_GetInterruptMaskStatus( // \return PMC Interrupt Mask Status - AT91PS_PMC pPMC) // pointer to a PMC controller +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PMC_GetInterruptMaskStatus */ +/** \brief Return PMC Interrupt Mask Status */ +/**---------------------------------------------------------------------------- */ +__inline unsigned int AT91F_PMC_GetInterruptMaskStatus( /* \return PMC Interrupt Mask Status */ + AT91PS_PMC pPMC ) /* pointer to a PMC controller */ { return pPMC->PMC_IMR; } -//*---------------------------------------------------------------------------- -//* \fn AT91F_PMC_IsInterruptMasked -//* \brief Test if PMC Interrupt is Masked -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_PMC_IsInterruptMasked( - AT91PS_PMC pPMC, // \arg pointer to a PMC controller - unsigned int flag) // \arg flag to be tested -{ - return (AT91F_PMC_GetInterruptMaskStatus(pPMC) & flag); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PMC_IsStatusSet -//* \brief Test if PMC Status is Set -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_PMC_IsStatusSet( - AT91PS_PMC pPMC, // \arg pointer to a PMC controller - unsigned int flag) // \arg flag to be tested -{ - return (AT91F_PMC_GetStatus(pPMC) & flag); -}/* ***************************************************************************** - SOFTWARE API FOR ADC - ***************************************************************************** */ -//*---------------------------------------------------------------------------- -//* \fn AT91F_ADC_EnableIt -//* \brief Enable ADC interrupt -//*---------------------------------------------------------------------------- -__inline void AT91F_ADC_EnableIt ( - AT91PS_ADC pADC, // pointer to a ADC controller - unsigned int flag) // IT to be enabled -{ - //* Write to the IER register +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PMC_IsInterruptMasked */ +/** \brief Test if PMC Interrupt is Masked */ +/**---------------------------------------------------------------------------- */ +__inline unsigned int AT91F_PMC_IsInterruptMasked( AT91PS_PMC pPMC, /* \arg pointer to a PMC controller */ + unsigned int flag ) /* \arg flag to be tested */ +{ + return( AT91F_PMC_GetInterruptMaskStatus( pPMC ) & flag ); +} + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PMC_IsStatusSet */ +/** \brief Test if PMC Status is Set */ +/**---------------------------------------------------------------------------- */ +__inline unsigned int AT91F_PMC_IsStatusSet( AT91PS_PMC pPMC, /* \arg pointer to a PMC controller */ + unsigned int flag ) /* \arg flag to be tested */ +{ + return( AT91F_PMC_GetStatus( pPMC ) & flag ); +} /* ***************************************************************************** + * SOFTWARE API FOR ADC + ***************************************************************************** */ +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_ADC_EnableIt */ +/** \brief Enable ADC interrupt */ +/**---------------------------------------------------------------------------- */ +__inline void AT91F_ADC_EnableIt( AT91PS_ADC pADC, /* pointer to a ADC controller */ + unsigned int flag ) /* IT to be enabled */ +{ + /** Write to the IER register */ pADC->ADC_IER = flag; } -//*---------------------------------------------------------------------------- -//* \fn AT91F_ADC_DisableIt -//* \brief Disable ADC interrupt -//*---------------------------------------------------------------------------- -__inline void AT91F_ADC_DisableIt ( - AT91PS_ADC pADC, // pointer to a ADC controller - unsigned int flag) // IT to be disabled +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_ADC_DisableIt */ +/** \brief Disable ADC interrupt */ +/**---------------------------------------------------------------------------- */ +__inline void AT91F_ADC_DisableIt( AT91PS_ADC pADC, /* pointer to a ADC controller */ + unsigned int flag ) /* IT to be disabled */ { - //* Write to the IDR register + /** Write to the IDR register */ pADC->ADC_IDR = flag; } -//*---------------------------------------------------------------------------- -//* \fn AT91F_ADC_GetStatus -//* \brief Return ADC Interrupt Status -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_ADC_GetStatus( // \return ADC Interrupt Status - AT91PS_ADC pADC) // pointer to a ADC controller +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_ADC_GetStatus */ +/** \brief Return ADC Interrupt Status */ +/**---------------------------------------------------------------------------- */ +__inline unsigned int AT91F_ADC_GetStatus( /* \return ADC Interrupt Status */ + AT91PS_ADC pADC ) /* pointer to a ADC controller */ { return pADC->ADC_SR; } -//*---------------------------------------------------------------------------- -//* \fn AT91F_ADC_GetInterruptMaskStatus -//* \brief Return ADC Interrupt Mask Status -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_ADC_GetInterruptMaskStatus( // \return ADC Interrupt Mask Status - AT91PS_ADC pADC) // pointer to a ADC controller +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_ADC_GetInterruptMaskStatus */ +/** \brief Return ADC Interrupt Mask Status */ +/**---------------------------------------------------------------------------- */ +__inline unsigned int AT91F_ADC_GetInterruptMaskStatus( /* \return ADC Interrupt Mask Status */ + AT91PS_ADC pADC ) /* pointer to a ADC controller */ { return pADC->ADC_IMR; } -//*---------------------------------------------------------------------------- -//* \fn AT91F_ADC_IsInterruptMasked -//* \brief Test if ADC Interrupt is Masked -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_ADC_IsInterruptMasked( - AT91PS_ADC pADC, // \arg pointer to a ADC controller - unsigned int flag) // \arg flag to be tested +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_ADC_IsInterruptMasked */ +/** \brief Test if ADC Interrupt is Masked */ +/**---------------------------------------------------------------------------- */ +__inline unsigned int AT91F_ADC_IsInterruptMasked( AT91PS_ADC pADC, /* \arg pointer to a ADC controller */ + unsigned int flag ) /* \arg flag to be tested */ { - return (AT91F_ADC_GetInterruptMaskStatus(pADC) & flag); + return( AT91F_ADC_GetInterruptMaskStatus( pADC ) & flag ); } -//*---------------------------------------------------------------------------- -//* \fn AT91F_ADC_IsStatusSet -//* \brief Test if ADC Status is Set -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_ADC_IsStatusSet( - AT91PS_ADC pADC, // \arg pointer to a ADC controller - unsigned int flag) // \arg flag to be tested +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_ADC_IsStatusSet */ +/** \brief Test if ADC Status is Set */ +/**---------------------------------------------------------------------------- */ +__inline unsigned int AT91F_ADC_IsStatusSet( AT91PS_ADC pADC, /* \arg pointer to a ADC controller */ + unsigned int flag ) /* \arg flag to be tested */ { - return (AT91F_ADC_GetStatus(pADC) & flag); + return( AT91F_ADC_GetStatus( pADC ) & flag ); } -//*---------------------------------------------------------------------------- -//* \fn AT91F_ADC_CfgModeReg -//* \brief Configure the Mode Register of the ADC controller -//*---------------------------------------------------------------------------- -__inline void AT91F_ADC_CfgModeReg ( - AT91PS_ADC pADC, // pointer to a ADC controller - unsigned int mode) // mode register +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_ADC_CfgModeReg */ +/** \brief Configure the Mode Register of the ADC controller */ +/**---------------------------------------------------------------------------- */ +__inline void AT91F_ADC_CfgModeReg( AT91PS_ADC pADC, /* pointer to a ADC controller */ + unsigned int mode ) /* mode register */ { - //* Write to the MR register + /** Write to the MR register */ pADC->ADC_MR = mode; } -//*---------------------------------------------------------------------------- -//* \fn AT91F_ADC_GetModeReg -//* \brief Return the Mode Register of the ADC controller value -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_ADC_GetModeReg ( - AT91PS_ADC pADC // pointer to a ADC controller - ) +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_ADC_GetModeReg */ +/** \brief Return the Mode Register of the ADC controller value */ +/**---------------------------------------------------------------------------- */ +__inline unsigned int AT91F_ADC_GetModeReg( AT91PS_ADC pADC /* pointer to a ADC controller */ + ) { return pADC->ADC_MR; } -//*---------------------------------------------------------------------------- -//* \fn AT91F_ADC_CfgTimings -//* \brief Configure the different necessary timings of the ADC controller -//*---------------------------------------------------------------------------- -__inline void AT91F_ADC_CfgTimings ( - AT91PS_ADC pADC, // pointer to a ADC controller - unsigned int mck_clock, // in MHz - unsigned int adc_clock, // in MHz - unsigned int startup_time, // in us - unsigned int sample_and_hold_time) // in ns +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_ADC_CfgTimings */ +/** \brief Configure the different necessary timings of the ADC controller */ +/**---------------------------------------------------------------------------- */ +__inline void AT91F_ADC_CfgTimings( AT91PS_ADC pADC, /* pointer to a ADC controller */ + unsigned int mck_clock, /* in MHz */ + unsigned int adc_clock, /* in MHz */ + unsigned int startup_time, /* in us */ + unsigned int sample_and_hold_time ) /* in ns */ { - unsigned int prescal,startup,shtim; + unsigned int prescal, startup, shtim; - prescal = mck_clock/(2*adc_clock) - 1; - startup = adc_clock*startup_time/8 - 1; - shtim = adc_clock*sample_and_hold_time/1000 - 1; + prescal = mck_clock / ( 2 * adc_clock ) - 1; + startup = adc_clock * startup_time / 8 - 1; + shtim = adc_clock * sample_and_hold_time / 1000 - 1; - //* Write to the MR register - pADC->ADC_MR = ( (prescal<<8) & AT91C_ADC_PRESCAL) | ( (startup<<16) & AT91C_ADC_STARTUP) | ( (shtim<<24) & AT91C_ADC_SHTIM); + /** Write to the MR register */ + pADC->ADC_MR = ( ( prescal << 8 ) & AT91C_ADC_PRESCAL ) | ( ( startup << 16 ) & AT91C_ADC_STARTUP ) | ( ( shtim << 24 ) & AT91C_ADC_SHTIM ); } -//*---------------------------------------------------------------------------- -//* \fn AT91F_ADC_EnableChannel -//* \brief Return ADC Timer Register Value -//*---------------------------------------------------------------------------- -__inline void AT91F_ADC_EnableChannel ( - AT91PS_ADC pADC, // pointer to a ADC controller - unsigned int channel) // mode register +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_ADC_EnableChannel */ +/** \brief Return ADC Timer Register Value */ +/**---------------------------------------------------------------------------- */ +__inline void AT91F_ADC_EnableChannel( AT91PS_ADC pADC, /* pointer to a ADC controller */ + unsigned int channel ) /* mode register */ { - //* Write to the CHER register + /** Write to the CHER register */ pADC->ADC_CHER = channel; } -//*---------------------------------------------------------------------------- -//* \fn AT91F_ADC_DisableChannel -//* \brief Return ADC Timer Register Value -//*---------------------------------------------------------------------------- -__inline void AT91F_ADC_DisableChannel ( - AT91PS_ADC pADC, // pointer to a ADC controller - unsigned int channel) // mode register +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_ADC_DisableChannel */ +/** \brief Return ADC Timer Register Value */ +/**---------------------------------------------------------------------------- */ +__inline void AT91F_ADC_DisableChannel( AT91PS_ADC pADC, /* pointer to a ADC controller */ + unsigned int channel ) /* mode register */ { - //* Write to the CHDR register + /** Write to the CHDR register */ pADC->ADC_CHDR = channel; } -//*---------------------------------------------------------------------------- -//* \fn AT91F_ADC_GetChannelStatus -//* \brief Return ADC Timer Register Value -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_ADC_GetChannelStatus ( - AT91PS_ADC pADC // pointer to a ADC controller - ) +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_ADC_GetChannelStatus */ +/** \brief Return ADC Timer Register Value */ +/**---------------------------------------------------------------------------- */ +__inline unsigned int AT91F_ADC_GetChannelStatus( AT91PS_ADC pADC /* pointer to a ADC controller */ + ) { return pADC->ADC_CHSR; } -//*---------------------------------------------------------------------------- -//* \fn AT91F_ADC_StartConversion -//* \brief Software request for a analog to digital conversion -//*---------------------------------------------------------------------------- -__inline void AT91F_ADC_StartConversion ( - AT91PS_ADC pADC // pointer to a ADC controller - ) +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_ADC_StartConversion */ +/** \brief Software request for a analog to digital conversion */ +/**---------------------------------------------------------------------------- */ +__inline void AT91F_ADC_StartConversion( AT91PS_ADC pADC /* pointer to a ADC controller */ + ) { pADC->ADC_CR = AT91C_ADC_START; } -//*---------------------------------------------------------------------------- -//* \fn AT91F_ADC_SoftReset -//* \brief Software reset -//*---------------------------------------------------------------------------- -__inline void AT91F_ADC_SoftReset ( - AT91PS_ADC pADC // pointer to a ADC controller - ) +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_ADC_SoftReset */ +/** \brief Software reset */ +/**---------------------------------------------------------------------------- */ +__inline void AT91F_ADC_SoftReset( AT91PS_ADC pADC /* pointer to a ADC controller */ + ) { pADC->ADC_CR = AT91C_ADC_SWRST; } -//*---------------------------------------------------------------------------- -//* \fn AT91F_ADC_GetLastConvertedData -//* \brief Return the Last Converted Data -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_ADC_GetLastConvertedData ( - AT91PS_ADC pADC // pointer to a ADC controller - ) +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_ADC_GetLastConvertedData */ +/** \brief Return the Last Converted Data */ +/**---------------------------------------------------------------------------- */ +__inline unsigned int AT91F_ADC_GetLastConvertedData( AT91PS_ADC pADC /* pointer to a ADC controller */ + ) { return pADC->ADC_LCDR; } -//*---------------------------------------------------------------------------- -//* \fn AT91F_ADC_GetConvertedDataCH0 -//* \brief Return the Channel 0 Converted Data -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_ADC_GetConvertedDataCH0 ( - AT91PS_ADC pADC // pointer to a ADC controller - ) +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_ADC_GetConvertedDataCH0 */ +/** \brief Return the Channel 0 Converted Data */ +/**---------------------------------------------------------------------------- */ +__inline unsigned int AT91F_ADC_GetConvertedDataCH0( AT91PS_ADC pADC /* pointer to a ADC controller */ + ) { return pADC->ADC_CDR0; } -//*---------------------------------------------------------------------------- -//* \fn AT91F_ADC_GetConvertedDataCH1 -//* \brief Return the Channel 1 Converted Data -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_ADC_GetConvertedDataCH1 ( - AT91PS_ADC pADC // pointer to a ADC controller - ) +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_ADC_GetConvertedDataCH1 */ +/** \brief Return the Channel 1 Converted Data */ +/**---------------------------------------------------------------------------- */ +__inline unsigned int AT91F_ADC_GetConvertedDataCH1( AT91PS_ADC pADC /* pointer to a ADC controller */ + ) { return pADC->ADC_CDR1; } -//*---------------------------------------------------------------------------- -//* \fn AT91F_ADC_GetConvertedDataCH2 -//* \brief Return the Channel 2 Converted Data -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_ADC_GetConvertedDataCH2 ( - AT91PS_ADC pADC // pointer to a ADC controller - ) +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_ADC_GetConvertedDataCH2 */ +/** \brief Return the Channel 2 Converted Data */ +/**---------------------------------------------------------------------------- */ +__inline unsigned int AT91F_ADC_GetConvertedDataCH2( AT91PS_ADC pADC /* pointer to a ADC controller */ + ) { return pADC->ADC_CDR2; } -//*---------------------------------------------------------------------------- -//* \fn AT91F_ADC_GetConvertedDataCH3 -//* \brief Return the Channel 3 Converted Data -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_ADC_GetConvertedDataCH3 ( - AT91PS_ADC pADC // pointer to a ADC controller - ) +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_ADC_GetConvertedDataCH3 */ +/** \brief Return the Channel 3 Converted Data */ +/**---------------------------------------------------------------------------- */ +__inline unsigned int AT91F_ADC_GetConvertedDataCH3( AT91PS_ADC pADC /* pointer to a ADC controller */ + ) { return pADC->ADC_CDR3; } -//*---------------------------------------------------------------------------- -//* \fn AT91F_ADC_GetConvertedDataCH4 -//* \brief Return the Channel 4 Converted Data -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_ADC_GetConvertedDataCH4 ( - AT91PS_ADC pADC // pointer to a ADC controller - ) +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_ADC_GetConvertedDataCH4 */ +/** \brief Return the Channel 4 Converted Data */ +/**---------------------------------------------------------------------------- */ +__inline unsigned int AT91F_ADC_GetConvertedDataCH4( AT91PS_ADC pADC /* pointer to a ADC controller */ + ) { return pADC->ADC_CDR4; } -//*---------------------------------------------------------------------------- -//* \fn AT91F_ADC_GetConvertedDataCH5 -//* \brief Return the Channel 5 Converted Data -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_ADC_GetConvertedDataCH5 ( - AT91PS_ADC pADC // pointer to a ADC controller - ) +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_ADC_GetConvertedDataCH5 */ +/** \brief Return the Channel 5 Converted Data */ +/**---------------------------------------------------------------------------- */ +__inline unsigned int AT91F_ADC_GetConvertedDataCH5( AT91PS_ADC pADC /* pointer to a ADC controller */ + ) { return pADC->ADC_CDR5; } -//*---------------------------------------------------------------------------- -//* \fn AT91F_ADC_GetConvertedDataCH6 -//* \brief Return the Channel 6 Converted Data -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_ADC_GetConvertedDataCH6 ( - AT91PS_ADC pADC // pointer to a ADC controller - ) +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_ADC_GetConvertedDataCH6 */ +/** \brief Return the Channel 6 Converted Data */ +/**---------------------------------------------------------------------------- */ +__inline unsigned int AT91F_ADC_GetConvertedDataCH6( AT91PS_ADC pADC /* pointer to a ADC controller */ + ) { return pADC->ADC_CDR6; } -//*---------------------------------------------------------------------------- -//* \fn AT91F_ADC_GetConvertedDataCH7 -//* \brief Return the Channel 7 Converted Data -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_ADC_GetConvertedDataCH7 ( - AT91PS_ADC pADC // pointer to a ADC controller - ) +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_ADC_GetConvertedDataCH7 */ +/** \brief Return the Channel 7 Converted Data */ +/**---------------------------------------------------------------------------- */ +__inline unsigned int AT91F_ADC_GetConvertedDataCH7( AT91PS_ADC pADC /* pointer to a ADC controller */ + ) { return pADC->ADC_CDR7; } /* ***************************************************************************** - SOFTWARE API FOR PIO - ***************************************************************************** */ -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_CfgPeriph -//* \brief Enable pins to be drived by peripheral -//*---------------------------------------------------------------------------- -__inline void AT91F_PIO_CfgPeriph( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int periphAEnable, // \arg PERIPH A to enable - unsigned int periphBEnable) // \arg PERIPH B to enable +* SOFTWARE API FOR PIO +***************************************************************************** */ +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PIO_CfgPeriph */ +/** \brief Enable pins to be derived by peripheral */ +/**---------------------------------------------------------------------------- */ +__inline void AT91F_PIO_CfgPeriph( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */ + unsigned int periphAEnable, /* \arg PERIPH A to enable */ + unsigned int periphBEnable ) /* \arg PERIPH B to enable */ { pPio->PIO_ASR = periphAEnable; pPio->PIO_BSR = periphBEnable; - pPio->PIO_PDR = (periphAEnable | periphBEnable); // Set in Periph mode + pPio->PIO_PDR = ( periphAEnable | periphBEnable ); /* Set in Periph mode */ } -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_CfgOutput -//* \brief Enable PIO in output mode -//*---------------------------------------------------------------------------- -__inline void AT91F_PIO_CfgOutput( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int pioEnable) // \arg PIO to be enabled +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PIO_CfgOutput */ +/** \brief Enable PIO in output mode */ +/**---------------------------------------------------------------------------- */ +__inline void AT91F_PIO_CfgOutput( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */ + unsigned int pioEnable ) /* \arg PIO to be enabled */ { - pPio->PIO_PER = pioEnable; // Set in PIO mode - pPio->PIO_OER = pioEnable; // Configure in Output + pPio->PIO_PER = pioEnable; /* Set in PIO mode */ + pPio->PIO_OER = pioEnable; /* Configure in Output */ } -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_CfgInput -//* \brief Enable PIO in input mode -//*---------------------------------------------------------------------------- -__inline void AT91F_PIO_CfgInput( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int inputEnable) // \arg PIO to be enabled +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PIO_CfgInput */ +/** \brief Enable PIO in input mode */ +/**---------------------------------------------------------------------------- */ +__inline void AT91F_PIO_CfgInput( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */ + unsigned int inputEnable ) /* \arg PIO to be enabled */ { - // Disable output - pPio->PIO_ODR = inputEnable; - pPio->PIO_PER = inputEnable; + /* Disable output */ + pPio->PIO_ODR = inputEnable; + pPio->PIO_PER = inputEnable; } -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_CfgOpendrain -//* \brief Configure PIO in open drain -//*---------------------------------------------------------------------------- -__inline void AT91F_PIO_CfgOpendrain( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int multiDrvEnable) // \arg pio to be configured in open drain +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PIO_CfgOpendrain */ +/** \brief Configure PIO in open drain */ +/**---------------------------------------------------------------------------- */ +__inline void AT91F_PIO_CfgOpendrain( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */ + unsigned int multiDrvEnable ) /* \arg pio to be configured in open drain */ { - // Configure the multi-drive option + /* Configure the multi-drive option */ pPio->PIO_MDDR = ~multiDrvEnable; pPio->PIO_MDER = multiDrvEnable; } -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_CfgPullup -//* \brief Enable pullup on PIO -//*---------------------------------------------------------------------------- -__inline void AT91F_PIO_CfgPullup( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int pullupEnable) // \arg enable pullup on PIO +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PIO_CfgPullup */ +/** \brief Enable pullup on PIO */ +/**---------------------------------------------------------------------------- */ +__inline void AT91F_PIO_CfgPullup( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */ + unsigned int pullupEnable ) /* \arg enable pullup on PIO */ { - // Connect or not Pullup + /* Connect or not Pullup */ pPio->PIO_PPUDR = ~pullupEnable; pPio->PIO_PPUER = pullupEnable; } -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_CfgDirectDrive -//* \brief Enable direct drive on PIO -//*---------------------------------------------------------------------------- -__inline void AT91F_PIO_CfgDirectDrive( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int directDrive) // \arg PIO to be configured with direct drive +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PIO_CfgDirectDrive */ +/** \brief Enable direct drive on PIO */ +/**---------------------------------------------------------------------------- */ +__inline void AT91F_PIO_CfgDirectDrive( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */ + unsigned int directDrive ) /* \arg PIO to be configured with direct drive */ { - // Configure the Direct Drive - pPio->PIO_OWDR = ~directDrive; - pPio->PIO_OWER = directDrive; + /* Configure the Direct Drive */ + pPio->PIO_OWDR = ~directDrive; + pPio->PIO_OWER = directDrive; } -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_CfgInputFilter -//* \brief Enable input filter on input PIO -//*---------------------------------------------------------------------------- -__inline void AT91F_PIO_CfgInputFilter( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int inputFilter) // \arg PIO to be configured with input filter +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PIO_CfgInputFilter */ +/** \brief Enable input filter on input PIO */ +/**---------------------------------------------------------------------------- */ +__inline void AT91F_PIO_CfgInputFilter( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */ + unsigned int inputFilter ) /* \arg PIO to be configured with input filter */ { - // Configure the Direct Drive - pPio->PIO_IFDR = ~inputFilter; - pPio->PIO_IFER = inputFilter; + /* Configure the Direct Drive */ + pPio->PIO_IFDR = ~inputFilter; + pPio->PIO_IFER = inputFilter; } -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_GetInput -//* \brief Return PIO input value -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_PIO_GetInput( // \return PIO input - AT91PS_PIO pPio) // \arg pointer to a PIO controller +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PIO_GetInput */ +/** \brief Return PIO input value */ +/**---------------------------------------------------------------------------- */ +__inline unsigned int AT91F_PIO_GetInput( /* \return PIO input */ + AT91PS_PIO pPio ) /* \arg pointer to a PIO controller */ { return pPio->PIO_PDSR; } -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_IsInputSet -//* \brief Test if PIO is input flag is active -//*---------------------------------------------------------------------------- -__inline int AT91F_PIO_IsInputSet( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag) // \arg flag to be tested +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PIO_IsInputSet */ +/** \brief Test if PIO is input flag is active */ +/**---------------------------------------------------------------------------- */ +__inline int AT91F_PIO_IsInputSet( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */ + unsigned int flag ) /* \arg flag to be tested */ { - return (AT91F_PIO_GetInput(pPio) & flag); + return( AT91F_PIO_GetInput( pPio ) & flag ); } -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_SetOutput -//* \brief Set to 1 output PIO -//*---------------------------------------------------------------------------- -__inline void AT91F_PIO_SetOutput( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag) // \arg output to be set +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PIO_SetOutput */ +/** \brief Set to 1 output PIO */ +/**---------------------------------------------------------------------------- */ +__inline void AT91F_PIO_SetOutput( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */ + unsigned int flag ) /* \arg output to be set */ { pPio->PIO_SODR = flag; } -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_ClearOutput -//* \brief Set to 0 output PIO -//*---------------------------------------------------------------------------- -__inline void AT91F_PIO_ClearOutput( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag) // \arg output to be cleared +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PIO_ClearOutput */ +/** \brief Set to 0 output PIO */ +/**---------------------------------------------------------------------------- */ +__inline void AT91F_PIO_ClearOutput( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */ + unsigned int flag ) /* \arg output to be cleared */ { pPio->PIO_CODR = flag; } -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_ForceOutput -//* \brief Force output when Direct drive option is enabled -//*---------------------------------------------------------------------------- -__inline void AT91F_PIO_ForceOutput( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag) // \arg output to be forced +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PIO_ForceOutput */ +/** \brief Force output when Direct drive option is enabled */ +/**---------------------------------------------------------------------------- */ +__inline void AT91F_PIO_ForceOutput( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */ + unsigned int flag ) /* \arg output to be forced */ { pPio->PIO_ODSR = flag; } -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_Enable -//* \brief Enable PIO -//*---------------------------------------------------------------------------- -__inline void AT91F_PIO_Enable( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag) // \arg pio to be enabled +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PIO_Enable */ +/** \brief Enable PIO */ +/**---------------------------------------------------------------------------- */ +__inline void AT91F_PIO_Enable( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */ + unsigned int flag ) /* \arg pio to be enabled */ { - pPio->PIO_PER = flag; + pPio->PIO_PER = flag; } -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_Disable -//* \brief Disable PIO -//*---------------------------------------------------------------------------- -__inline void AT91F_PIO_Disable( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag) // \arg pio to be disabled +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PIO_Disable */ +/** \brief Disable PIO */ +/**---------------------------------------------------------------------------- */ +__inline void AT91F_PIO_Disable( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */ + unsigned int flag ) /* \arg pio to be disabled */ { - pPio->PIO_PDR = flag; + pPio->PIO_PDR = flag; } -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_GetStatus -//* \brief Return PIO Status -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_PIO_GetStatus( // \return PIO Status - AT91PS_PIO pPio) // \arg pointer to a PIO controller +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PIO_GetStatus */ +/** \brief Return PIO Status */ +/**---------------------------------------------------------------------------- */ +__inline unsigned int AT91F_PIO_GetStatus( /* \return PIO Status */ + AT91PS_PIO pPio ) /* \arg pointer to a PIO controller */ { - return pPio->PIO_PSR; + return pPio->PIO_PSR; } -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_IsSet -//* \brief Test if PIO is Set -//*---------------------------------------------------------------------------- -__inline int AT91F_PIO_IsSet( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag) // \arg flag to be tested +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PIO_IsSet */ +/** \brief Test if PIO is Set */ +/**---------------------------------------------------------------------------- */ +__inline int AT91F_PIO_IsSet( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */ + unsigned int flag ) /* \arg flag to be tested */ { - return (AT91F_PIO_GetStatus(pPio) & flag); + return( AT91F_PIO_GetStatus( pPio ) & flag ); } -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_OutputEnable -//* \brief Output Enable PIO -//*---------------------------------------------------------------------------- -__inline void AT91F_PIO_OutputEnable( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag) // \arg pio output to be enabled +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PIO_OutputEnable */ +/** \brief Output Enable PIO */ +/**---------------------------------------------------------------------------- */ +__inline void AT91F_PIO_OutputEnable( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */ + unsigned int flag ) /* \arg pio output to be enabled */ { - pPio->PIO_OER = flag; + pPio->PIO_OER = flag; } -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_OutputDisable -//* \brief Output Enable PIO -//*---------------------------------------------------------------------------- -__inline void AT91F_PIO_OutputDisable( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag) // \arg pio output to be disabled +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PIO_OutputDisable */ +/** \brief Output Enable PIO */ +/**---------------------------------------------------------------------------- */ +__inline void AT91F_PIO_OutputDisable( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */ + unsigned int flag ) /* \arg pio output to be disabled */ { - pPio->PIO_ODR = flag; + pPio->PIO_ODR = flag; } -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_GetOutputStatus -//* \brief Return PIO Output Status -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_PIO_GetOutputStatus( // \return PIO Output Status - AT91PS_PIO pPio) // \arg pointer to a PIO controller +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PIO_GetOutputStatus */ +/** \brief Return PIO Output Status */ +/**---------------------------------------------------------------------------- */ +__inline unsigned int AT91F_PIO_GetOutputStatus( /* \return PIO Output Status */ + AT91PS_PIO pPio ) /* \arg pointer to a PIO controller */ { - return pPio->PIO_OSR; + return pPio->PIO_OSR; } -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_IsOuputSet -//* \brief Test if PIO Output is Set -//*---------------------------------------------------------------------------- -__inline int AT91F_PIO_IsOutputSet( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag) // \arg flag to be tested +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PIO_IsOuputSet */ +/** \brief Test if PIO Output is Set */ +/**---------------------------------------------------------------------------- */ +__inline int AT91F_PIO_IsOutputSet( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */ + unsigned int flag ) /* \arg flag to be tested */ { - return (AT91F_PIO_GetOutputStatus(pPio) & flag); + return( AT91F_PIO_GetOutputStatus( pPio ) & flag ); } -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_InputFilterEnable -//* \brief Input Filter Enable PIO -//*---------------------------------------------------------------------------- -__inline void AT91F_PIO_InputFilterEnable( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag) // \arg pio input filter to be enabled +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PIO_InputFilterEnable */ +/** \brief Input Filter Enable PIO */ +/**---------------------------------------------------------------------------- */ +__inline void AT91F_PIO_InputFilterEnable( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */ + unsigned int flag ) /* \arg pio input filter to be enabled */ { - pPio->PIO_IFER = flag; + pPio->PIO_IFER = flag; } -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_InputFilterDisable -//* \brief Input Filter Disable PIO -//*---------------------------------------------------------------------------- -__inline void AT91F_PIO_InputFilterDisable( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag) // \arg pio input filter to be disabled +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PIO_InputFilterDisable */ +/** \brief Input Filter Disable PIO */ +/**---------------------------------------------------------------------------- */ +__inline void AT91F_PIO_InputFilterDisable( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */ + unsigned int flag ) /* \arg pio input filter to be disabled */ { - pPio->PIO_IFDR = flag; + pPio->PIO_IFDR = flag; } -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_GetInputFilterStatus -//* \brief Return PIO Input Filter Status -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_PIO_GetInputFilterStatus( // \return PIO Input Filter Status - AT91PS_PIO pPio) // \arg pointer to a PIO controller +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PIO_GetInputFilterStatus */ +/** \brief Return PIO Input Filter Status */ +/**---------------------------------------------------------------------------- */ +__inline unsigned int AT91F_PIO_GetInputFilterStatus( /* \return PIO Input Filter Status */ + AT91PS_PIO pPio ) /* \arg pointer to a PIO controller */ { - return pPio->PIO_IFSR; + return pPio->PIO_IFSR; } -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_IsInputFilterSet -//* \brief Test if PIO Input filter is Set -//*---------------------------------------------------------------------------- -__inline int AT91F_PIO_IsInputFilterSet( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag) // \arg flag to be tested +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PIO_IsInputFilterSet */ +/** \brief Test if PIO Input filter is Set */ +/**---------------------------------------------------------------------------- */ +__inline int AT91F_PIO_IsInputFilterSet( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */ + unsigned int flag ) /* \arg flag to be tested */ { - return (AT91F_PIO_GetInputFilterStatus(pPio) & flag); + return( AT91F_PIO_GetInputFilterStatus( pPio ) & flag ); } -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_GetOutputDataStatus -//* \brief Return PIO Output Data Status -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_PIO_GetOutputDataStatus( // \return PIO Output Data Status - AT91PS_PIO pPio) // \arg pointer to a PIO controller +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PIO_GetOutputDataStatus */ +/** \brief Return PIO Output Data Status */ +/**---------------------------------------------------------------------------- */ +__inline unsigned int AT91F_PIO_GetOutputDataStatus( /* \return PIO Output Data Status */ + AT91PS_PIO pPio ) /* \arg pointer to a PIO controller */ { - return pPio->PIO_ODSR; + return pPio->PIO_ODSR; } -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_InterruptEnable -//* \brief Enable PIO Interrupt -//*---------------------------------------------------------------------------- -__inline void AT91F_PIO_InterruptEnable( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag) // \arg pio interrupt to be enabled +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PIO_InterruptEnable */ +/** \brief Enable PIO Interrupt */ +/**---------------------------------------------------------------------------- */ +__inline void AT91F_PIO_InterruptEnable( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */ + unsigned int flag ) /* \arg pio interrupt to be enabled */ { - pPio->PIO_IER = flag; + pPio->PIO_IER = flag; } -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_InterruptDisable -//* \brief Disable PIO Interrupt -//*---------------------------------------------------------------------------- -__inline void AT91F_PIO_InterruptDisable( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag) // \arg pio interrupt to be disabled +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PIO_InterruptDisable */ +/** \brief Disable PIO Interrupt */ +/**---------------------------------------------------------------------------- */ +__inline void AT91F_PIO_InterruptDisable( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */ + unsigned int flag ) /* \arg pio interrupt to be disabled */ { - pPio->PIO_IDR = flag; + pPio->PIO_IDR = flag; } -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_GetInterruptMaskStatus -//* \brief Return PIO Interrupt Mask Status -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_PIO_GetInterruptMaskStatus( // \return PIO Interrupt Mask Status - AT91PS_PIO pPio) // \arg pointer to a PIO controller +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PIO_GetInterruptMaskStatus */ +/** \brief Return PIO Interrupt Mask Status */ +/**---------------------------------------------------------------------------- */ +__inline unsigned int AT91F_PIO_GetInterruptMaskStatus( /* \return PIO Interrupt Mask Status */ + AT91PS_PIO pPio ) /* \arg pointer to a PIO controller */ { - return pPio->PIO_IMR; + return pPio->PIO_IMR; } -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_GetInterruptStatus -//* \brief Return PIO Interrupt Status -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_PIO_GetInterruptStatus( // \return PIO Interrupt Status - AT91PS_PIO pPio) // \arg pointer to a PIO controller +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PIO_GetInterruptStatus */ +/** \brief Return PIO Interrupt Status */ +/**---------------------------------------------------------------------------- */ +__inline unsigned int AT91F_PIO_GetInterruptStatus( /* \return PIO Interrupt Status */ + AT91PS_PIO pPio ) /* \arg pointer to a PIO controller */ { - return pPio->PIO_ISR; + return pPio->PIO_ISR; } -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_IsInterruptMasked -//* \brief Test if PIO Interrupt is Masked -//*---------------------------------------------------------------------------- -__inline int AT91F_PIO_IsInterruptMasked( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag) // \arg flag to be tested +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PIO_IsInterruptMasked */ +/** \brief Test if PIO Interrupt is Masked */ +/**---------------------------------------------------------------------------- */ +__inline int AT91F_PIO_IsInterruptMasked( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */ + unsigned int flag ) /* \arg flag to be tested */ { - return (AT91F_PIO_GetInterruptMaskStatus(pPio) & flag); + return( AT91F_PIO_GetInterruptMaskStatus( pPio ) & flag ); } -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_IsInterruptSet -//* \brief Test if PIO Interrupt is Set -//*---------------------------------------------------------------------------- -__inline int AT91F_PIO_IsInterruptSet( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag) // \arg flag to be tested +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PIO_IsInterruptSet */ +/** \brief Test if PIO Interrupt is Set */ +/**---------------------------------------------------------------------------- */ +__inline int AT91F_PIO_IsInterruptSet( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */ + unsigned int flag ) /* \arg flag to be tested */ { - return (AT91F_PIO_GetInterruptStatus(pPio) & flag); + return( AT91F_PIO_GetInterruptStatus( pPio ) & flag ); } -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_MultiDriverEnable -//* \brief Multi Driver Enable PIO -//*---------------------------------------------------------------------------- -__inline void AT91F_PIO_MultiDriverEnable( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag) // \arg pio to be enabled +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PIO_MultiDriverEnable */ +/** \brief Multi Driver Enable PIO */ +/**---------------------------------------------------------------------------- */ +__inline void AT91F_PIO_MultiDriverEnable( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */ + unsigned int flag ) /* \arg pio to be enabled */ { - pPio->PIO_MDER = flag; + pPio->PIO_MDER = flag; } -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_MultiDriverDisable -//* \brief Multi Driver Disable PIO -//*---------------------------------------------------------------------------- -__inline void AT91F_PIO_MultiDriverDisable( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag) // \arg pio to be disabled +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PIO_MultiDriverDisable */ +/** \brief Multi Driver Disable PIO */ +/**---------------------------------------------------------------------------- */ +__inline void AT91F_PIO_MultiDriverDisable( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */ + unsigned int flag ) /* \arg pio to be disabled */ { - pPio->PIO_MDDR = flag; + pPio->PIO_MDDR = flag; } -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_GetMultiDriverStatus -//* \brief Return PIO Multi Driver Status -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_PIO_GetMultiDriverStatus( // \return PIO Multi Driver Status - AT91PS_PIO pPio) // \arg pointer to a PIO controller +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PIO_GetMultiDriverStatus */ +/** \brief Return PIO Multi Driver Status */ +/**---------------------------------------------------------------------------- */ +__inline unsigned int AT91F_PIO_GetMultiDriverStatus( /* \return PIO Multi Driver Status */ + AT91PS_PIO pPio ) /* \arg pointer to a PIO controller */ { - return pPio->PIO_MDSR; + return pPio->PIO_MDSR; } -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_IsMultiDriverSet -//* \brief Test if PIO MultiDriver is Set -//*---------------------------------------------------------------------------- -__inline int AT91F_PIO_IsMultiDriverSet( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag) // \arg flag to be tested +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PIO_IsMultiDriverSet */ +/** \brief Test if PIO MultiDriver is Set */ +/**---------------------------------------------------------------------------- */ +__inline int AT91F_PIO_IsMultiDriverSet( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */ + unsigned int flag ) /* \arg flag to be tested */ { - return (AT91F_PIO_GetMultiDriverStatus(pPio) & flag); + return( AT91F_PIO_GetMultiDriverStatus( pPio ) & flag ); } -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_A_RegisterSelection -//* \brief PIO A Register Selection -//*---------------------------------------------------------------------------- -__inline void AT91F_PIO_A_RegisterSelection( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag) // \arg pio A register selection +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PIO_A_RegisterSelection */ +/** \brief PIO A Register Selection */ +/**---------------------------------------------------------------------------- */ +__inline void AT91F_PIO_A_RegisterSelection( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */ + unsigned int flag ) /* \arg pio A register selection */ { - pPio->PIO_ASR = flag; + pPio->PIO_ASR = flag; } -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_B_RegisterSelection -//* \brief PIO B Register Selection -//*---------------------------------------------------------------------------- -__inline void AT91F_PIO_B_RegisterSelection( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag) // \arg pio B register selection +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PIO_B_RegisterSelection */ +/** \brief PIO B Register Selection */ +/**---------------------------------------------------------------------------- */ +__inline void AT91F_PIO_B_RegisterSelection( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */ + unsigned int flag ) /* \arg pio B register selection */ { - pPio->PIO_BSR = flag; + pPio->PIO_BSR = flag; } -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_Get_AB_RegisterStatus -//* \brief Return PIO Interrupt Status -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_PIO_Get_AB_RegisterStatus( // \return PIO AB Register Status - AT91PS_PIO pPio) // \arg pointer to a PIO controller +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PIO_Get_AB_RegisterStatus */ +/** \brief Return PIO Interrupt Status */ +/**---------------------------------------------------------------------------- */ +__inline unsigned int AT91F_PIO_Get_AB_RegisterStatus( /* \return PIO AB Register Status */ + AT91PS_PIO pPio ) /* \arg pointer to a PIO controller */ { - return pPio->PIO_ABSR; + return pPio->PIO_ABSR; } -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_IsAB_RegisterSet -//* \brief Test if PIO AB Register is Set -//*---------------------------------------------------------------------------- -__inline int AT91F_PIO_IsAB_RegisterSet( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag) // \arg flag to be tested +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PIO_IsAB_RegisterSet */ +/** \brief Test if PIO AB Register is Set */ +/**---------------------------------------------------------------------------- */ +__inline int AT91F_PIO_IsAB_RegisterSet( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */ + unsigned int flag ) /* \arg flag to be tested */ { - return (AT91F_PIO_Get_AB_RegisterStatus(pPio) & flag); + return( AT91F_PIO_Get_AB_RegisterStatus( pPio ) & flag ); } -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_OutputWriteEnable -//* \brief Output Write Enable PIO -//*---------------------------------------------------------------------------- -__inline void AT91F_PIO_OutputWriteEnable( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag) // \arg pio output write to be enabled +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PIO_OutputWriteEnable */ +/** \brief Output Write Enable PIO */ +/**---------------------------------------------------------------------------- */ +__inline void AT91F_PIO_OutputWriteEnable( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */ + unsigned int flag ) /* \arg pio output write to be enabled */ { - pPio->PIO_OWER = flag; + pPio->PIO_OWER = flag; } -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_OutputWriteDisable -//* \brief Output Write Disable PIO -//*---------------------------------------------------------------------------- -__inline void AT91F_PIO_OutputWriteDisable( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag) // \arg pio output write to be disabled +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PIO_OutputWriteDisable */ +/** \brief Output Write Disable PIO */ +/**---------------------------------------------------------------------------- */ +__inline void AT91F_PIO_OutputWriteDisable( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */ + unsigned int flag ) /* \arg pio output write to be disabled */ { - pPio->PIO_OWDR = flag; + pPio->PIO_OWDR = flag; } -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_GetOutputWriteStatus -//* \brief Return PIO Output Write Status -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_PIO_GetOutputWriteStatus( // \return PIO Output Write Status - AT91PS_PIO pPio) // \arg pointer to a PIO controller +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PIO_GetOutputWriteStatus */ +/** \brief Return PIO Output Write Status */ +/**---------------------------------------------------------------------------- */ +__inline unsigned int AT91F_PIO_GetOutputWriteStatus( /* \return PIO Output Write Status */ + AT91PS_PIO pPio ) /* \arg pointer to a PIO controller */ { - return pPio->PIO_OWSR; + return pPio->PIO_OWSR; } -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_IsOutputWriteSet -//* \brief Test if PIO OutputWrite is Set -//*---------------------------------------------------------------------------- -__inline int AT91F_PIO_IsOutputWriteSet( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag) // \arg flag to be tested +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PIO_IsOutputWriteSet */ +/** \brief Test if PIO OutputWrite is Set */ +/**---------------------------------------------------------------------------- */ +__inline int AT91F_PIO_IsOutputWriteSet( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */ + unsigned int flag ) /* \arg flag to be tested */ { - return (AT91F_PIO_GetOutputWriteStatus(pPio) & flag); + return( AT91F_PIO_GetOutputWriteStatus( pPio ) & flag ); } -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_GetCfgPullup -//* \brief Return PIO Configuration Pullup -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_PIO_GetCfgPullup( // \return PIO Configuration Pullup - AT91PS_PIO pPio) // \arg pointer to a PIO controller +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PIO_GetCfgPullup */ +/** \brief Return PIO Configuration Pullup */ +/**---------------------------------------------------------------------------- */ +__inline unsigned int AT91F_PIO_GetCfgPullup( /* \return PIO Configuration Pullup */ + AT91PS_PIO pPio ) /* \arg pointer to a PIO controller */ { - return pPio->PIO_PPUSR; + return pPio->PIO_PPUSR; } -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_IsOutputDataStatusSet -//* \brief Test if PIO Output Data Status is Set -//*---------------------------------------------------------------------------- -__inline int AT91F_PIO_IsOutputDataStatusSet( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag) // \arg flag to be tested +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PIO_IsOutputDataStatusSet */ +/** \brief Test if PIO Output Data Status is Set */ +/**---------------------------------------------------------------------------- */ +__inline int AT91F_PIO_IsOutputDataStatusSet( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */ + unsigned int flag ) /* \arg flag to be tested */ { - return (AT91F_PIO_GetOutputDataStatus(pPio) & flag); + return( AT91F_PIO_GetOutputDataStatus( pPio ) & flag ); } -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_IsCfgPullupStatusSet -//* \brief Test if PIO Configuration Pullup Status is Set -//*---------------------------------------------------------------------------- -__inline int AT91F_PIO_IsCfgPullupStatusSet( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag) // \arg flag to be tested +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PIO_IsCfgPullupStatusSet */ +/** \brief Test if PIO Configuration Pullup Status is Set */ +/**---------------------------------------------------------------------------- */ +__inline int AT91F_PIO_IsCfgPullupStatusSet( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */ + unsigned int flag ) /* \arg flag to be tested */ { - return (~AT91F_PIO_GetCfgPullup(pPio) & flag); + return( ~AT91F_PIO_GetCfgPullup( pPio ) & flag ); } /* ***************************************************************************** - SOFTWARE API FOR TWI - ***************************************************************************** */ -//*---------------------------------------------------------------------------- -//* \fn AT91F_TWI_EnableIt -//* \brief Enable TWI IT -//*---------------------------------------------------------------------------- -__inline void AT91F_TWI_EnableIt ( - AT91PS_TWI pTWI, // \arg pointer to a TWI controller - unsigned int flag) // \arg IT to be enabled -{ - //* Write to the IER register +* SOFTWARE API FOR TWI +***************************************************************************** */ +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_TWI_EnableIt */ +/** \brief Enable TWI IT */ +/**---------------------------------------------------------------------------- */ +__inline void AT91F_TWI_EnableIt( AT91PS_TWI pTWI, /* \arg pointer to a TWI controller */ + unsigned int flag ) /* \arg IT to be enabled */ +{ + /** Write to the IER register */ pTWI->TWI_IER = flag; } -//*---------------------------------------------------------------------------- -//* \fn AT91F_TWI_DisableIt -//* \brief Disable TWI IT -//*---------------------------------------------------------------------------- -__inline void AT91F_TWI_DisableIt ( - AT91PS_TWI pTWI, // \arg pointer to a TWI controller - unsigned int flag) // \arg IT to be disabled +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_TWI_DisableIt */ +/** \brief Disable TWI IT */ +/**---------------------------------------------------------------------------- */ +__inline void AT91F_TWI_DisableIt( AT91PS_TWI pTWI, /* \arg pointer to a TWI controller */ + unsigned int flag ) /* \arg IT to be disabled */ { - //* Write to the IDR register + /** Write to the IDR register */ pTWI->TWI_IDR = flag; } -//*---------------------------------------------------------------------------- -//* \fn AT91F_TWI_Configure -//* \brief Configure TWI in master mode -//*---------------------------------------------------------------------------- -__inline void AT91F_TWI_Configure ( AT91PS_TWI pTWI ) // \arg pointer to a TWI controller +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_TWI_Configure */ +/** \brief Configure TWI in master mode */ +/**---------------------------------------------------------------------------- */ +__inline void AT91F_TWI_Configure( AT91PS_TWI pTWI ) /* \arg pointer to a TWI controller */ { - //* Disable interrupts - pTWI->TWI_IDR = (unsigned int) -1; + /** Disable interrupts */ + pTWI->TWI_IDR = ( unsigned int ) -1; - //* Reset peripheral + /** Reset peripheral */ pTWI->TWI_CR = AT91C_TWI_SWRST; - //* Set Master mode + /** Set Master mode */ pTWI->TWI_CR = AT91C_TWI_MSEN | AT91C_TWI_SVDIS; - } -//*---------------------------------------------------------------------------- -//* \fn AT91F_TWI_GetInterruptMaskStatus -//* \brief Return TWI Interrupt Mask Status -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_TWI_GetInterruptMaskStatus( // \return TWI Interrupt Mask Status - AT91PS_TWI pTwi) // \arg pointer to a TWI controller +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_TWI_GetInterruptMaskStatus */ +/** \brief Return TWI Interrupt Mask Status */ +/**---------------------------------------------------------------------------- */ +__inline unsigned int AT91F_TWI_GetInterruptMaskStatus( /* \return TWI Interrupt Mask Status */ + AT91PS_TWI pTwi ) /* \arg pointer to a TWI controller */ { - return pTwi->TWI_IMR; + return pTwi->TWI_IMR; } -//*---------------------------------------------------------------------------- -//* \fn AT91F_TWI_IsInterruptMasked -//* \brief Test if TWI Interrupt is Masked -//*---------------------------------------------------------------------------- -__inline int AT91F_TWI_IsInterruptMasked( - AT91PS_TWI pTwi, // \arg pointer to a TWI controller - unsigned int flag) // \arg flag to be tested +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_TWI_IsInterruptMasked */ +/** \brief Test if TWI Interrupt is Masked */ +/**---------------------------------------------------------------------------- */ +__inline int AT91F_TWI_IsInterruptMasked( AT91PS_TWI pTwi, /* \arg pointer to a TWI controller */ + unsigned int flag ) /* \arg flag to be tested */ { - return (AT91F_TWI_GetInterruptMaskStatus(pTwi) & flag); + return( AT91F_TWI_GetInterruptMaskStatus( pTwi ) & flag ); } /* ***************************************************************************** - SOFTWARE API FOR USART - ***************************************************************************** */ -//*---------------------------------------------------------------------------- -//* \fn AT91F_US_Baudrate -//* \brief Calculate the baudrate -//* Standard Asynchronous Mode : 8 bits , 1 stop , no parity -#define AT91C_US_ASYNC_MODE ( AT91C_US_USMODE_NORMAL + \ - AT91C_US_NBSTOP_1_BIT + \ - AT91C_US_PAR_NONE + \ - AT91C_US_CHRL_8_BITS + \ - AT91C_US_CLKS_CLOCK ) - -//* Standard External Asynchronous Mode : 8 bits , 1 stop , no parity -#define AT91C_US_ASYNC_SCK_MODE ( AT91C_US_USMODE_NORMAL + \ - AT91C_US_NBSTOP_1_BIT + \ - AT91C_US_PAR_NONE + \ - AT91C_US_CHRL_8_BITS + \ - AT91C_US_CLKS_EXT ) - -//* Standard Synchronous Mode : 8 bits , 1 stop , no parity -#define AT91C_US_SYNC_MODE ( AT91C_US_SYNC + \ - AT91C_US_USMODE_NORMAL + \ - AT91C_US_NBSTOP_1_BIT + \ - AT91C_US_PAR_NONE + \ - AT91C_US_CHRL_8_BITS + \ - AT91C_US_CLKS_CLOCK ) - -//* SCK used Label -#define AT91C_US_SCK_USED (AT91C_US_CKLO | AT91C_US_CLKS_EXT) - -//* Standard ISO T=0 Mode : 8 bits , 1 stop , parity -#define AT91C_US_ISO_READER_MODE ( AT91C_US_USMODE_ISO7816_0 + \ - AT91C_US_CLKS_CLOCK +\ - AT91C_US_NBSTOP_1_BIT + \ - AT91C_US_PAR_EVEN + \ - AT91C_US_CHRL_8_BITS + \ - AT91C_US_CKLO +\ - AT91C_US_OVER) - -//* Standard IRDA mode -#define AT91C_US_ASYNC_IRDA_MODE ( AT91C_US_USMODE_IRDA + \ - AT91C_US_NBSTOP_1_BIT + \ - AT91C_US_PAR_NONE + \ - AT91C_US_CHRL_8_BITS + \ - AT91C_US_CLKS_CLOCK ) - -//*---------------------------------------------------------------------------- -//* \fn AT91F_US_Baudrate -//* \brief Caluculate baud_value according to the main clock and the baud rate -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_US_Baudrate ( - const unsigned int main_clock, // \arg peripheral clock - const unsigned int baud_rate) // \arg UART baudrate -{ - unsigned int baud_value = ((main_clock*10)/(baud_rate * 16)); - if ((baud_value % 10) >= 5) - baud_value = (baud_value / 10) + 1; +* SOFTWARE API FOR USART +***************************************************************************** */ +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_US_Baudrate */ +/** \brief Calculate the baudrate */ +/** Standard Asynchronous Mode : 8 bits , 1 stop , no parity */ +#define AT91C_US_ASYNC_MODE \ + ( AT91C_US_USMODE_NORMAL + \ + AT91C_US_NBSTOP_1_BIT + \ + AT91C_US_PAR_NONE + \ + AT91C_US_CHRL_8_BITS + \ + AT91C_US_CLKS_CLOCK ) + +/** Standard External Asynchronous Mode : 8 bits , 1 stop , no parity */ +#define AT91C_US_ASYNC_SCK_MODE \ + ( AT91C_US_USMODE_NORMAL + \ + AT91C_US_NBSTOP_1_BIT + \ + AT91C_US_PAR_NONE + \ + AT91C_US_CHRL_8_BITS + \ + AT91C_US_CLKS_EXT ) + +/** Standard Synchronous Mode : 8 bits , 1 stop , no parity */ +#define AT91C_US_SYNC_MODE \ + ( AT91C_US_SYNC + \ + AT91C_US_USMODE_NORMAL + \ + AT91C_US_NBSTOP_1_BIT + \ + AT91C_US_PAR_NONE + \ + AT91C_US_CHRL_8_BITS + \ + AT91C_US_CLKS_CLOCK ) + +/** SCK used Label */ +#define AT91C_US_SCK_USED ( AT91C_US_CKLO | AT91C_US_CLKS_EXT ) + +/** Standard ISO T=0 Mode : 8 bits , 1 stop , parity */ +#define AT91C_US_ISO_READER_MODE \ + ( AT91C_US_USMODE_ISO7816_0 + \ + AT91C_US_CLKS_CLOCK + \ + AT91C_US_NBSTOP_1_BIT + \ + AT91C_US_PAR_EVEN + \ + AT91C_US_CHRL_8_BITS + \ + AT91C_US_CKLO + \ + AT91C_US_OVER ) + +/** Standard IRDA mode */ +#define AT91C_US_ASYNC_IRDA_MODE \ + ( AT91C_US_USMODE_IRDA + \ + AT91C_US_NBSTOP_1_BIT + \ + AT91C_US_PAR_NONE + \ + AT91C_US_CHRL_8_BITS + \ + AT91C_US_CLKS_CLOCK ) + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_US_Baudrate */ +/** \brief Calculate baud_value according to the main clock and the baud rate */ +/**---------------------------------------------------------------------------- */ +__inline unsigned int AT91F_US_Baudrate( const unsigned int main_clock, /* \arg peripheral clock */ + const unsigned int baud_rate ) /* \arg UART baudrate */ +{ + unsigned int baud_value = ( ( main_clock * 10 ) / ( baud_rate * 16 ) ); + + if( ( baud_value % 10 ) >= 5 ) + { + baud_value = ( baud_value / 10 ) + 1; + } else + { baud_value /= 10; + } + return baud_value; } -//*---------------------------------------------------------------------------- -//* \fn AT91F_US_SetBaudrate -//* \brief Set the baudrate according to the CPU clock -//*---------------------------------------------------------------------------- -__inline void AT91F_US_SetBaudrate ( - AT91PS_USART pUSART, // \arg pointer to a USART controller - unsigned int mainClock, // \arg peripheral clock - unsigned int speed) // \arg UART baudrate +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_US_SetBaudrate */ +/** \brief Set the baudrate according to the CPU clock */ +/**---------------------------------------------------------------------------- */ +__inline void AT91F_US_SetBaudrate( AT91PS_USART pUSART, /* \arg pointer to a USART controller */ + unsigned int mainClock, /* \arg peripheral clock */ + unsigned int speed ) /* \arg UART baudrate */ { - //* Define the baud rate divisor register - pUSART->US_BRGR = AT91F_US_Baudrate(mainClock, speed); + /** Define the baud rate divisor register */ + pUSART->US_BRGR = AT91F_US_Baudrate( mainClock, speed ); } -//*---------------------------------------------------------------------------- -//* \fn AT91F_US_SetTimeguard -//* \brief Set USART timeguard -//*---------------------------------------------------------------------------- -__inline void AT91F_US_SetTimeguard ( - AT91PS_USART pUSART, // \arg pointer to a USART controller - unsigned int timeguard) // \arg timeguard value +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_US_SetTimeguard */ +/** \brief Set USART timeguard */ +/**---------------------------------------------------------------------------- */ +__inline void AT91F_US_SetTimeguard( AT91PS_USART pUSART, /* \arg pointer to a USART controller */ + unsigned int timeguard ) /* \arg timeguard value */ { - //* Write the Timeguard Register - pUSART->US_TTGR = timeguard ; + /** Write the Timeguard Register */ + pUSART->US_TTGR = timeguard; } -//*---------------------------------------------------------------------------- -//* \fn AT91F_US_EnableIt -//* \brief Enable USART IT -//*---------------------------------------------------------------------------- -__inline void AT91F_US_EnableIt ( - AT91PS_USART pUSART, // \arg pointer to a USART controller - unsigned int flag) // \arg IT to be enabled +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_US_EnableIt */ +/** \brief Enable USART IT */ +/**---------------------------------------------------------------------------- */ +__inline void AT91F_US_EnableIt( AT91PS_USART pUSART, /* \arg pointer to a USART controller */ + unsigned int flag ) /* \arg IT to be enabled */ { - //* Write to the IER register + /** Write to the IER register */ pUSART->US_IER = flag; } -//*---------------------------------------------------------------------------- -//* \fn AT91F_US_DisableIt -//* \brief Disable USART IT -//*---------------------------------------------------------------------------- -__inline void AT91F_US_DisableIt ( - AT91PS_USART pUSART, // \arg pointer to a USART controller - unsigned int flag) // \arg IT to be disabled +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_US_DisableIt */ +/** \brief Disable USART IT */ +/**---------------------------------------------------------------------------- */ +__inline void AT91F_US_DisableIt( AT91PS_USART pUSART, /* \arg pointer to a USART controller */ + unsigned int flag ) /* \arg IT to be disabled */ { - //* Write to the IER register + /** Write to the IER register */ pUSART->US_IDR = flag; } -//*---------------------------------------------------------------------------- -//* \fn AT91F_US_Configure -//* \brief Configure USART -//*---------------------------------------------------------------------------- -__inline void AT91F_US_Configure ( - AT91PS_USART pUSART, // \arg pointer to a USART controller - unsigned int mainClock, // \arg peripheral clock - unsigned int mode , // \arg mode Register to be programmed - unsigned int baudRate , // \arg baudrate to be programmed - unsigned int timeguard ) // \arg timeguard to be programmed +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_US_Configure */ +/** \brief Configure USART */ +/**---------------------------------------------------------------------------- */ +__inline void AT91F_US_Configure( AT91PS_USART pUSART, /* \arg pointer to a USART controller */ + unsigned int mainClock, /* \arg peripheral clock */ + unsigned int mode, /* \arg mode Register to be programmed */ + unsigned int baudRate, /* \arg baudrate to be programmed */ + unsigned int timeguard ) /* \arg timeguard to be programmed */ { - //* Disable interrupts - pUSART->US_IDR = (unsigned int) -1; - - //* Reset receiver and transmitter - pUSART->US_CR = AT91C_US_RSTRX | AT91C_US_RSTTX | AT91C_US_RXDIS | AT91C_US_TXDIS ; + /** Disable interrupts */ + pUSART->US_IDR = ( unsigned int ) -1; - //* Define the baud rate divisor register - AT91F_US_SetBaudrate(pUSART, mainClock, baudRate); + /** Reset receiver and transmitter */ + pUSART->US_CR = AT91C_US_RSTRX | AT91C_US_RSTTX | AT91C_US_RXDIS | AT91C_US_TXDIS; - //* Write the Timeguard Register - AT91F_US_SetTimeguard(pUSART, timeguard); + /** Define the baud rate divisor register */ + AT91F_US_SetBaudrate( pUSART, mainClock, baudRate ); - //* Clear Transmit and Receive Counters - AT91F_PDC_Open((AT91PS_PDC) &(pUSART->US_RPR)); + /** Write the Timeguard Register */ + AT91F_US_SetTimeguard( pUSART, timeguard ); - //* Define the USART mode - pUSART->US_MR = mode ; + /** Clear Transmit and Receive Counters */ + AT91F_PDC_Open( ( AT91PS_PDC ) &( pUSART->US_RPR ) ); + /** Define the USART mode */ + pUSART->US_MR = mode; } -//*---------------------------------------------------------------------------- -//* \fn AT91F_US_EnableRx -//* \brief Enable receiving characters -//*---------------------------------------------------------------------------- -__inline void AT91F_US_EnableRx ( - AT91PS_USART pUSART) // \arg pointer to a USART controller +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_US_EnableRx */ +/** \brief Enable receiving characters */ +/**---------------------------------------------------------------------------- */ +__inline void AT91F_US_EnableRx( AT91PS_USART pUSART ) /* \arg pointer to a USART controller */ { - //* Enable receiver + /** Enable receiver */ pUSART->US_CR = AT91C_US_RXEN; } -//*---------------------------------------------------------------------------- -//* \fn AT91F_US_EnableTx -//* \brief Enable sending characters -//*---------------------------------------------------------------------------- -__inline void AT91F_US_EnableTx ( - AT91PS_USART pUSART) // \arg pointer to a USART controller +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_US_EnableTx */ +/** \brief Enable sending characters */ +/**---------------------------------------------------------------------------- */ +__inline void AT91F_US_EnableTx( AT91PS_USART pUSART ) /* \arg pointer to a USART controller */ { - //* Enable transmitter + /** Enable transmitter */ pUSART->US_CR = AT91C_US_TXEN; } -//*---------------------------------------------------------------------------- -//* \fn AT91F_US_ResetRx -//* \brief Reset Receiver and re-enable it -//*---------------------------------------------------------------------------- -__inline void AT91F_US_ResetRx ( - AT91PS_USART pUSART) // \arg pointer to a USART controller +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_US_ResetRx */ +/** \brief Reset Receiver and re-enable it */ +/**---------------------------------------------------------------------------- */ +__inline void AT91F_US_ResetRx( AT91PS_USART pUSART ) /* \arg pointer to a USART controller */ { - //* Reset receiver + /** Reset receiver */ pUSART->US_CR = AT91C_US_RSTRX; - //* Re-Enable receiver + /** Re-Enable receiver */ pUSART->US_CR = AT91C_US_RXEN; } -//*---------------------------------------------------------------------------- -//* \fn AT91F_US_ResetTx -//* \brief Reset Transmitter and re-enable it -//*---------------------------------------------------------------------------- -__inline void AT91F_US_ResetTx ( - AT91PS_USART pUSART) // \arg pointer to a USART controller +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_US_ResetTx */ +/** \brief Reset Transmitter and re-enable it */ +/**---------------------------------------------------------------------------- */ +__inline void AT91F_US_ResetTx( AT91PS_USART pUSART ) /* \arg pointer to a USART controller */ { - //* Reset transmitter + /** Reset transmitter */ pUSART->US_CR = AT91C_US_RSTTX; - //* Enable transmitter + /** Enable transmitter */ pUSART->US_CR = AT91C_US_TXEN; } -//*---------------------------------------------------------------------------- -//* \fn AT91F_US_DisableRx -//* \brief Disable Receiver -//*---------------------------------------------------------------------------- -__inline void AT91F_US_DisableRx ( - AT91PS_USART pUSART) // \arg pointer to a USART controller +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_US_DisableRx */ +/** \brief Disable Receiver */ +/**---------------------------------------------------------------------------- */ +__inline void AT91F_US_DisableRx( AT91PS_USART pUSART ) /* \arg pointer to a USART controller */ { - //* Disable receiver + /** Disable receiver */ pUSART->US_CR = AT91C_US_RXDIS; } -//*---------------------------------------------------------------------------- -//* \fn AT91F_US_DisableTx -//* \brief Disable Transmitter -//*---------------------------------------------------------------------------- -__inline void AT91F_US_DisableTx ( - AT91PS_USART pUSART) // \arg pointer to a USART controller +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_US_DisableTx */ +/** \brief Disable Transmitter */ +/**---------------------------------------------------------------------------- */ +__inline void AT91F_US_DisableTx( AT91PS_USART pUSART ) /* \arg pointer to a USART controller */ { - //* Disable transmitter + /** Disable transmitter */ pUSART->US_CR = AT91C_US_TXDIS; } -//*---------------------------------------------------------------------------- -//* \fn AT91F_US_Close -//* \brief Close USART: disable IT disable receiver and transmitter, close PDC -//*---------------------------------------------------------------------------- -__inline void AT91F_US_Close ( - AT91PS_USART pUSART) // \arg pointer to a USART controller +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_US_Close */ +/** \brief Close USART: disable IT disable receiver and transmitter, close PDC */ +/**---------------------------------------------------------------------------- */ +__inline void AT91F_US_Close( AT91PS_USART pUSART ) /* \arg pointer to a USART controller */ { - //* Reset the baud rate divisor register - pUSART->US_BRGR = 0 ; + /** Reset the baud rate divisor register */ + pUSART->US_BRGR = 0; - //* Reset the USART mode - pUSART->US_MR = 0 ; + /** Reset the USART mode */ + pUSART->US_MR = 0; - //* Reset the Timeguard Register + /** Reset the Timeguard Register */ pUSART->US_TTGR = 0; - //* Disable all interrupts - pUSART->US_IDR = 0xFFFFFFFF ; + /** Disable all interrupts */ + pUSART->US_IDR = 0xFFFFFFFF; - //* Abort the Peripheral Data Transfers - AT91F_PDC_Close((AT91PS_PDC) &(pUSART->US_RPR)); + /** Abort the Peripheral Data Transfers */ + AT91F_PDC_Close( ( AT91PS_PDC ) &( pUSART->US_RPR ) ); - //* Disable receiver and transmitter and stop any activity immediately - pUSART->US_CR = AT91C_US_TXDIS | AT91C_US_RXDIS | AT91C_US_RSTTX | AT91C_US_RSTRX ; + /** Disable receiver and transmitter and stop any activity immediately */ + pUSART->US_CR = AT91C_US_TXDIS | AT91C_US_RXDIS | AT91C_US_RSTTX | AT91C_US_RSTRX; } -//*---------------------------------------------------------------------------- -//* \fn AT91F_US_TxReady -//* \brief Return 1 if a character can be written in US_THR -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_US_TxReady ( - AT91PS_USART pUSART ) // \arg pointer to a USART controller +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_US_TxReady */ +/** \brief Return 1 if a character can be written in US_THR */ +/**---------------------------------------------------------------------------- */ +__inline unsigned int AT91F_US_TxReady( AT91PS_USART pUSART ) /* \arg pointer to a USART controller */ { - return (pUSART->US_CSR & AT91C_US_TXRDY); + return( pUSART->US_CSR & AT91C_US_TXRDY ); } -//*---------------------------------------------------------------------------- -//* \fn AT91F_US_RxReady -//* \brief Return 1 if a character can be read in US_RHR -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_US_RxReady ( - AT91PS_USART pUSART ) // \arg pointer to a USART controller +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_US_RxReady */ +/** \brief Return 1 if a character can be read in US_RHR */ +/**---------------------------------------------------------------------------- */ +__inline unsigned int AT91F_US_RxReady( AT91PS_USART pUSART ) /* \arg pointer to a USART controller */ { - return (pUSART->US_CSR & AT91C_US_RXRDY); + return( pUSART->US_CSR & AT91C_US_RXRDY ); } -//*---------------------------------------------------------------------------- -//* \fn AT91F_US_Error -//* \brief Return the error flag -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_US_Error ( - AT91PS_USART pUSART ) // \arg pointer to a USART controller +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_US_Error */ +/** \brief Return the error flag */ +/**---------------------------------------------------------------------------- */ +__inline unsigned int AT91F_US_Error( AT91PS_USART pUSART ) /* \arg pointer to a USART controller */ { - return (pUSART->US_CSR & - (AT91C_US_OVRE | // Overrun error - AT91C_US_FRAME | // Framing error - AT91C_US_PARE)); // Parity error + return( pUSART->US_CSR & + ( AT91C_US_OVRE | /* Overrun error */ + AT91C_US_FRAME | /* Framing error */ + AT91C_US_PARE ) ); /* Parity error */ } -//*---------------------------------------------------------------------------- -//* \fn AT91F_US_PutChar -//* \brief Send a character,does not check if ready to send -//*---------------------------------------------------------------------------- -__inline void AT91F_US_PutChar ( - AT91PS_USART pUSART, - int character ) +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_US_PutChar */ +/** \brief Send a character,does not check if ready to send */ +/**---------------------------------------------------------------------------- */ +__inline void AT91F_US_PutChar( AT91PS_USART pUSART, + int character ) { - pUSART->US_THR = (character & 0x1FF); + pUSART->US_THR = ( character & 0x1FF ); } -//*---------------------------------------------------------------------------- -//* \fn AT91F_US_GetChar -//* \brief Receive a character,does not check if a character is available -//*---------------------------------------------------------------------------- -__inline int AT91F_US_GetChar ( - const AT91PS_USART pUSART) +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_US_GetChar */ +/** \brief Receive a character,does not check if a character is available */ +/**---------------------------------------------------------------------------- */ +__inline int AT91F_US_GetChar( const AT91PS_USART pUSART ) { - return((pUSART->US_RHR) & 0x1FF); + return( ( pUSART->US_RHR ) & 0x1FF ); } -//*---------------------------------------------------------------------------- -//* \fn AT91F_US_SendFrame -//* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initializaed with Next Buffer, 0 if PDC is busy -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_US_SendFrame( - AT91PS_USART pUSART, - char *pBuffer, - unsigned int szBuffer, - char *pNextBuffer, - unsigned int szNextBuffer ) +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_US_SendFrame */ +/** \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initialized with Next Buffer, 0 if PDC is busy */ +/**---------------------------------------------------------------------------- */ +__inline unsigned int AT91F_US_SendFrame( AT91PS_USART pUSART, + char * pBuffer, + unsigned int szBuffer, + char * pNextBuffer, + unsigned int szNextBuffer ) { return AT91F_PDC_SendFrame( - (AT91PS_PDC) &(pUSART->US_RPR), + ( AT91PS_PDC ) &( pUSART->US_RPR ), pBuffer, szBuffer, pNextBuffer, - szNextBuffer); + szNextBuffer ); } -//*---------------------------------------------------------------------------- -//* \fn AT91F_US_ReceiveFrame -//* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initializaed with Next Buffer, 0 if PDC is busy -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_US_ReceiveFrame ( - AT91PS_USART pUSART, - char *pBuffer, - unsigned int szBuffer, - char *pNextBuffer, - unsigned int szNextBuffer ) +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_US_ReceiveFrame */ +/** \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initialized with Next Buffer, 0 if PDC is busy */ +/**---------------------------------------------------------------------------- */ +__inline unsigned int AT91F_US_ReceiveFrame( AT91PS_USART pUSART, + char * pBuffer, + unsigned int szBuffer, + char * pNextBuffer, + unsigned int szNextBuffer ) { return AT91F_PDC_ReceiveFrame( - (AT91PS_PDC) &(pUSART->US_RPR), + ( AT91PS_PDC ) &( pUSART->US_RPR ), pBuffer, szBuffer, pNextBuffer, - szNextBuffer); + szNextBuffer ); } -//*---------------------------------------------------------------------------- -//* \fn AT91F_US_SetIrdaFilter -//* \brief Set the value of IrDa filter tregister -//*---------------------------------------------------------------------------- -__inline void AT91F_US_SetIrdaFilter ( - AT91PS_USART pUSART, - unsigned char value -) +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_US_SetIrdaFilter */ +/** \brief Set the value of IrDa filter register */ +/**---------------------------------------------------------------------------- */ +__inline void AT91F_US_SetIrdaFilter( AT91PS_USART pUSART, + unsigned char value ) { pUSART->US_IF = value; } /* ***************************************************************************** - SOFTWARE API FOR UDP - ***************************************************************************** */ -//*---------------------------------------------------------------------------- -//* \fn AT91F_UDP_EnableIt -//* \brief Enable UDP IT -//*---------------------------------------------------------------------------- -__inline void AT91F_UDP_EnableIt ( - AT91PS_UDP pUDP, // \arg pointer to a UDP controller - unsigned int flag) // \arg IT to be enabled -{ - //* Write to the IER register +* SOFTWARE API FOR UDP +***************************************************************************** */ +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_UDP_EnableIt */ +/** \brief Enable UDP IT */ +/**---------------------------------------------------------------------------- */ +__inline void AT91F_UDP_EnableIt( AT91PS_UDP pUDP, /* \arg pointer to a UDP controller */ + unsigned int flag ) /* \arg IT to be enabled */ +{ + /** Write to the IER register */ pUDP->UDP_IER = flag; } -//*---------------------------------------------------------------------------- -//* \fn AT91F_UDP_DisableIt -//* \brief Disable UDP IT -//*---------------------------------------------------------------------------- -__inline void AT91F_UDP_DisableIt ( - AT91PS_UDP pUDP, // \arg pointer to a UDP controller - unsigned int flag) // \arg IT to be disabled +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_UDP_DisableIt */ +/** \brief Disable UDP IT */ +/**---------------------------------------------------------------------------- */ +__inline void AT91F_UDP_DisableIt( AT91PS_UDP pUDP, /* \arg pointer to a UDP controller */ + unsigned int flag ) /* \arg IT to be disabled */ { - //* Write to the IDR register + /** Write to the IDR register */ pUDP->UDP_IDR = flag; } -//*---------------------------------------------------------------------------- -//* \fn AT91F_UDP_SetAddress -//* \brief Set UDP functional address -//*---------------------------------------------------------------------------- -__inline void AT91F_UDP_SetAddress ( - AT91PS_UDP pUDP, // \arg pointer to a UDP controller - unsigned char address) // \arg new UDP address +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_UDP_SetAddress */ +/** \brief Set UDP functional address */ +/**---------------------------------------------------------------------------- */ +__inline void AT91F_UDP_SetAddress( AT91PS_UDP pUDP, /* \arg pointer to a UDP controller */ + unsigned char address ) /* \arg new UDP address */ { - pUDP->UDP_FADDR = (AT91C_UDP_FEN | address); + pUDP->UDP_FADDR = ( AT91C_UDP_FEN | address ); } -//*---------------------------------------------------------------------------- -//* \fn AT91F_UDP_EnableEp -//* \brief Enable Endpoint -//*---------------------------------------------------------------------------- -__inline void AT91F_UDP_EnableEp ( - AT91PS_UDP pUDP, // \arg pointer to a UDP controller - unsigned int flag) // \arg endpoints to be enabled +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_UDP_EnableEp */ +/** \brief Enable Endpoint */ +/**---------------------------------------------------------------------------- */ +__inline void AT91F_UDP_EnableEp( AT91PS_UDP pUDP, /* \arg pointer to a UDP controller */ + unsigned int flag ) /* \arg endpoints to be enabled */ { - pUDP->UDP_GLBSTATE |= flag; + pUDP->UDP_GLBSTATE |= flag; } -//*---------------------------------------------------------------------------- -//* \fn AT91F_UDP_DisableEp -//* \brief Enable Endpoint -//*---------------------------------------------------------------------------- -__inline void AT91F_UDP_DisableEp ( - AT91PS_UDP pUDP, // \arg pointer to a UDP controller - unsigned int flag) // \arg endpoints to be enabled +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_UDP_DisableEp */ +/** \brief Enable Endpoint */ +/**---------------------------------------------------------------------------- */ +__inline void AT91F_UDP_DisableEp( AT91PS_UDP pUDP, /* \arg pointer to a UDP controller */ + unsigned int flag ) /* \arg endpoints to be enabled */ { - pUDP->UDP_GLBSTATE &= ~(flag); + pUDP->UDP_GLBSTATE &= ~( flag ); } -//*---------------------------------------------------------------------------- -//* \fn AT91F_UDP_SetState -//* \brief Set UDP Device state -//*---------------------------------------------------------------------------- -__inline void AT91F_UDP_SetState ( - AT91PS_UDP pUDP, // \arg pointer to a UDP controller - unsigned int flag) // \arg new UDP address +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_UDP_SetState */ +/** \brief Set UDP Device state */ +/**---------------------------------------------------------------------------- */ +__inline void AT91F_UDP_SetState( AT91PS_UDP pUDP, /* \arg pointer to a UDP controller */ + unsigned int flag ) /* \arg new UDP address */ { - pUDP->UDP_GLBSTATE &= ~(AT91C_UDP_FADDEN | AT91C_UDP_CONFG); - pUDP->UDP_GLBSTATE |= flag; + pUDP->UDP_GLBSTATE &= ~( AT91C_UDP_FADDEN | AT91C_UDP_CONFG ); + pUDP->UDP_GLBSTATE |= flag; } -//*---------------------------------------------------------------------------- -//* \fn AT91F_UDP_GetState -//* \brief return UDP Device state -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_UDP_GetState ( // \return the UDP device state - AT91PS_UDP pUDP) // \arg pointer to a UDP controller +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_UDP_GetState */ +/** \brief return UDP Device state */ +/**---------------------------------------------------------------------------- */ +__inline unsigned int AT91F_UDP_GetState( /* \return the UDP device state */ + AT91PS_UDP pUDP ) /* \arg pointer to a UDP controller */ { - return (pUDP->UDP_GLBSTATE & (AT91C_UDP_FADDEN | AT91C_UDP_CONFG)); + return( pUDP->UDP_GLBSTATE & ( AT91C_UDP_FADDEN | AT91C_UDP_CONFG ) ); } -//*---------------------------------------------------------------------------- -//* \fn AT91F_UDP_ResetEp -//* \brief Reset UDP endpoint -//*---------------------------------------------------------------------------- -__inline void AT91F_UDP_ResetEp ( // \return the UDP device state - AT91PS_UDP pUDP, // \arg pointer to a UDP controller - unsigned int flag) // \arg Endpoints to be reset +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_UDP_ResetEp */ +/** \brief Reset UDP endpoint */ +/**---------------------------------------------------------------------------- */ +__inline void AT91F_UDP_ResetEp( /* \return the UDP device state */ + AT91PS_UDP pUDP, /* \arg pointer to a UDP controller */ + unsigned int flag ) /* \arg Endpoints to be reset */ { pUDP->UDP_RSTEP = flag; } -//*---------------------------------------------------------------------------- -//* \fn AT91F_UDP_EpStall -//* \brief Endpoint will STALL requests -//*---------------------------------------------------------------------------- -__inline void AT91F_UDP_EpStall( - AT91PS_UDP pUDP, // \arg pointer to a UDP controller - unsigned char endpoint) // \arg endpoint number +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_UDP_EpStall */ +/** \brief Endpoint will STALL requests */ +/**---------------------------------------------------------------------------- */ +__inline void AT91F_UDP_EpStall( AT91PS_UDP pUDP, /* \arg pointer to a UDP controller */ + unsigned char endpoint ) /* \arg endpoint number */ { - pUDP->UDP_CSR[endpoint] |= AT91C_UDP_FORCESTALL; + pUDP->UDP_CSR[ endpoint ] |= AT91C_UDP_FORCESTALL; } -//*---------------------------------------------------------------------------- -//* \fn AT91F_UDP_EpWrite -//* \brief Write value in the DPR -//*---------------------------------------------------------------------------- -__inline void AT91F_UDP_EpWrite( - AT91PS_UDP pUDP, // \arg pointer to a UDP controller - unsigned char endpoint, // \arg endpoint number - unsigned char value) // \arg value to be written in the DPR +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_UDP_EpWrite */ +/** \brief Write value in the DPR */ +/**---------------------------------------------------------------------------- */ +__inline void AT91F_UDP_EpWrite( AT91PS_UDP pUDP, /* \arg pointer to a UDP controller */ + unsigned char endpoint, /* \arg endpoint number */ + unsigned char value ) /* \arg value to be written in the DPR */ { - pUDP->UDP_FDR[endpoint] = value; + pUDP->UDP_FDR[ endpoint ] = value; } -//*---------------------------------------------------------------------------- -//* \fn AT91F_UDP_EpRead -//* \brief Return value from the DPR -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_UDP_EpRead( - AT91PS_UDP pUDP, // \arg pointer to a UDP controller - unsigned char endpoint) // \arg endpoint number +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_UDP_EpRead */ +/** \brief Return value from the DPR */ +/**---------------------------------------------------------------------------- */ +__inline unsigned int AT91F_UDP_EpRead( AT91PS_UDP pUDP, /* \arg pointer to a UDP controller */ + unsigned char endpoint ) /* \arg endpoint number */ { - return pUDP->UDP_FDR[endpoint]; + return pUDP->UDP_FDR[ endpoint ]; } -//*---------------------------------------------------------------------------- -//* \fn AT91F_UDP_EpEndOfWr -//* \brief Notify the UDP that values in DPR are ready to be sent -//*---------------------------------------------------------------------------- -__inline void AT91F_UDP_EpEndOfWr( - AT91PS_UDP pUDP, // \arg pointer to a UDP controller - unsigned char endpoint) // \arg endpoint number +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_UDP_EpEndOfWr */ +/** \brief Notify the UDP that values in DPR are ready to be sent */ +/**---------------------------------------------------------------------------- */ +__inline void AT91F_UDP_EpEndOfWr( AT91PS_UDP pUDP, /* \arg pointer to a UDP controller */ + unsigned char endpoint ) /* \arg endpoint number */ { - pUDP->UDP_CSR[endpoint] |= AT91C_UDP_TXPKTRDY; + pUDP->UDP_CSR[ endpoint ] |= AT91C_UDP_TXPKTRDY; } -//*---------------------------------------------------------------------------- -//* \fn AT91F_UDP_EpClear -//* \brief Clear flag in the endpoint CSR register -//*---------------------------------------------------------------------------- -__inline void AT91F_UDP_EpClear( - AT91PS_UDP pUDP, // \arg pointer to a UDP controller - unsigned char endpoint, // \arg endpoint number - unsigned int flag) // \arg flag to be cleared +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_UDP_EpClear */ +/** \brief Clear flag in the endpoint CSR register */ +/**---------------------------------------------------------------------------- */ +__inline void AT91F_UDP_EpClear( AT91PS_UDP pUDP, /* \arg pointer to a UDP controller */ + unsigned char endpoint, /* \arg endpoint number */ + unsigned int flag ) /* \arg flag to be cleared */ { - pUDP->UDP_CSR[endpoint] &= ~(flag); + pUDP->UDP_CSR[ endpoint ] &= ~( flag ); } -//*---------------------------------------------------------------------------- -//* \fn AT91F_UDP_EpSet -//* \brief Set flag in the endpoint CSR register -//*---------------------------------------------------------------------------- -__inline void AT91F_UDP_EpSet( - AT91PS_UDP pUDP, // \arg pointer to a UDP controller - unsigned char endpoint, // \arg endpoint number - unsigned int flag) // \arg flag to be cleared +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_UDP_EpSet */ +/** \brief Set flag in the endpoint CSR register */ +/**---------------------------------------------------------------------------- */ +__inline void AT91F_UDP_EpSet( AT91PS_UDP pUDP, /* \arg pointer to a UDP controller */ + unsigned char endpoint, /* \arg endpoint number */ + unsigned int flag ) /* \arg flag to be cleared */ { - pUDP->UDP_CSR[endpoint] |= flag; + pUDP->UDP_CSR[ endpoint ] |= flag; } -//*---------------------------------------------------------------------------- -//* \fn AT91F_UDP_EpStatus -//* \brief Return the endpoint CSR register -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_UDP_EpStatus( - AT91PS_UDP pUDP, // \arg pointer to a UDP controller - unsigned char endpoint) // \arg endpoint number +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_UDP_EpStatus */ +/** \brief Return the endpoint CSR register */ +/**---------------------------------------------------------------------------- */ +__inline unsigned int AT91F_UDP_EpStatus( AT91PS_UDP pUDP, /* \arg pointer to a UDP controller */ + unsigned char endpoint ) /* \arg endpoint number */ { - return pUDP->UDP_CSR[endpoint]; + return pUDP->UDP_CSR[ endpoint ]; } -//*---------------------------------------------------------------------------- -//* \fn AT91F_UDP_GetInterruptMaskStatus -//* \brief Return UDP Interrupt Mask Status -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_UDP_GetInterruptMaskStatus( // \return UDP Interrupt Mask Status - AT91PS_UDP pUdp) // \arg pointer to a UDP controller +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_UDP_GetInterruptMaskStatus */ +/** \brief Return UDP Interrupt Mask Status */ +/**---------------------------------------------------------------------------- */ +__inline unsigned int AT91F_UDP_GetInterruptMaskStatus( /* \return UDP Interrupt Mask Status */ + AT91PS_UDP pUdp ) /* \arg pointer to a UDP controller */ { - return pUdp->UDP_IMR; + return pUdp->UDP_IMR; } -//*---------------------------------------------------------------------------- -//* \fn AT91F_UDP_IsInterruptMasked -//* \brief Test if UDP Interrupt is Masked -//*---------------------------------------------------------------------------- -__inline int AT91F_UDP_IsInterruptMasked( - AT91PS_UDP pUdp, // \arg pointer to a UDP controller - unsigned int flag) // \arg flag to be tested +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_UDP_IsInterruptMasked */ +/** \brief Test if UDP Interrupt is Masked */ +/**---------------------------------------------------------------------------- */ +__inline int AT91F_UDP_IsInterruptMasked( AT91PS_UDP pUdp, /* \arg pointer to a UDP controller */ + unsigned int flag ) /* \arg flag to be tested */ { - return (AT91F_UDP_GetInterruptMaskStatus(pUdp) & flag); + return( AT91F_UDP_GetInterruptMaskStatus( pUdp ) & flag ); } /* ***************************************************************************** - SOFTWARE API FOR AIC - ***************************************************************************** */ -#define AT91C_AIC_BRANCH_OPCODE ((void (*) ()) 0xE51FFF20) // ldr, pc, [pc, #-&F20] - -//*---------------------------------------------------------------------------- -//* \fn AT91F_AIC_ConfigureIt -//* \brief Interrupt Handler Initialization -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_AIC_ConfigureIt ( - AT91PS_AIC pAic, // \arg pointer to the AIC registers - unsigned int irq_id, // \arg interrupt number to initialize - unsigned int priority, // \arg priority to give to the interrupt - unsigned int src_type, // \arg activation and sense of activation - void (*newHandler) (void) ) // \arg address of the interrupt handler +* SOFTWARE API FOR AIC +***************************************************************************** */ +#define AT91C_AIC_BRANCH_OPCODE ( ( void ( * )() ) 0xE51FFF20 ) /* ldr, pc, [pc, #-&F20] */ + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_AIC_ConfigureIt */ +/** \brief Interrupt Handler Initialization */ +/**---------------------------------------------------------------------------- */ +__inline unsigned int AT91F_AIC_ConfigureIt( AT91PS_AIC pAic, /* \arg pointer to the AIC registers */ + unsigned int irq_id, /* \arg interrupt number to initialize */ + unsigned int priority, /* \arg priority to give to the interrupt */ + unsigned int src_type, /* \arg activation and sense of activation */ + void ( * newHandler )( void ) ) /* \arg address of the interrupt handler */ { unsigned int oldHandler; - unsigned int mask ; + unsigned int mask; - oldHandler = pAic->AIC_SVR[irq_id]; + oldHandler = pAic->AIC_SVR[ irq_id ]; - mask = 0x1 << irq_id ; - //* Disable the interrupt on the interrupt controller - pAic->AIC_IDCR = mask ; - //* Save the interrupt handler routine pointer and the interrupt priority - pAic->AIC_SVR[irq_id] = (unsigned int) newHandler ; - //* Store the Source Mode Register - pAic->AIC_SMR[irq_id] = src_type | priority ; - //* Clear the interrupt on the interrupt controller - pAic->AIC_ICCR = mask ; + mask = 0x1 << irq_id; + /** Disable the interrupt on the interrupt controller */ + pAic->AIC_IDCR = mask; + /** Save the interrupt handler routine pointer and the interrupt priority */ + pAic->AIC_SVR[ irq_id ] = ( unsigned int ) newHandler; + /** Store the Source Mode Register */ + pAic->AIC_SMR[ irq_id ] = src_type | priority; + /** Clear the interrupt on the interrupt controller */ + pAic->AIC_ICCR = mask; return oldHandler; } -//*---------------------------------------------------------------------------- -//* \fn AT91F_AIC_EnableIt -//* \brief Enable corresponding IT number -//*---------------------------------------------------------------------------- -__inline void AT91F_AIC_EnableIt ( - AT91PS_AIC pAic, // \arg pointer to the AIC registers - unsigned int irq_id ) // \arg interrupt number to initialize +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_AIC_EnableIt */ +/** \brief Enable corresponding IT number */ +/**---------------------------------------------------------------------------- */ +__inline void AT91F_AIC_EnableIt( AT91PS_AIC pAic, /* \arg pointer to the AIC registers */ + unsigned int irq_id ) /* \arg interrupt number to initialize */ { - //* Enable the interrupt on the interrupt controller - pAic->AIC_IECR = 0x1 << irq_id ; + /** Enable the interrupt on the interrupt controller */ + pAic->AIC_IECR = 0x1 << irq_id; } -//*---------------------------------------------------------------------------- -//* \fn AT91F_AIC_DisableIt -//* \brief Disable corresponding IT number -//*---------------------------------------------------------------------------- -__inline void AT91F_AIC_DisableIt ( - AT91PS_AIC pAic, // \arg pointer to the AIC registers - unsigned int irq_id ) // \arg interrupt number to initialize +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_AIC_DisableIt */ +/** \brief Disable corresponding IT number */ +/**---------------------------------------------------------------------------- */ +__inline void AT91F_AIC_DisableIt( AT91PS_AIC pAic, /* \arg pointer to the AIC registers */ + unsigned int irq_id ) /* \arg interrupt number to initialize */ { unsigned int mask = 0x1 << irq_id; - //* Disable the interrupt on the interrupt controller - pAic->AIC_IDCR = mask ; - //* Clear the interrupt on the Interrupt Controller ( if one is pending ) - pAic->AIC_ICCR = mask ; + + /** Disable the interrupt on the interrupt controller */ + pAic->AIC_IDCR = mask; + /** Clear the interrupt on the Interrupt Controller ( if one is pending ) */ + pAic->AIC_ICCR = mask; } -//*---------------------------------------------------------------------------- -//* \fn AT91F_AIC_ClearIt -//* \brief Clear corresponding IT number -//*---------------------------------------------------------------------------- -__inline void AT91F_AIC_ClearIt ( - AT91PS_AIC pAic, // \arg pointer to the AIC registers - unsigned int irq_id) // \arg interrupt number to initialize +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_AIC_ClearIt */ +/** \brief Clear corresponding IT number */ +/**---------------------------------------------------------------------------- */ +__inline void AT91F_AIC_ClearIt( AT91PS_AIC pAic, /* \arg pointer to the AIC registers */ + unsigned int irq_id ) /* \arg interrupt number to initialize */ { - //* Clear the interrupt on the Interrupt Controller ( if one is pending ) - pAic->AIC_ICCR = (0x1 << irq_id); + /** Clear the interrupt on the Interrupt Controller ( if one is pending ) */ + pAic->AIC_ICCR = ( 0x1 << irq_id ); } -//*---------------------------------------------------------------------------- -//* \fn AT91F_AIC_AcknowledgeIt -//* \brief Acknowledge corresponding IT number -//*---------------------------------------------------------------------------- -__inline void AT91F_AIC_AcknowledgeIt ( - AT91PS_AIC pAic) // \arg pointer to the AIC registers +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_AIC_AcknowledgeIt */ +/** \brief Acknowledge corresponding IT number */ +/**---------------------------------------------------------------------------- */ +__inline void AT91F_AIC_AcknowledgeIt( AT91PS_AIC pAic ) /* \arg pointer to the AIC registers */ { pAic->AIC_EOICR = pAic->AIC_EOICR; } -//*---------------------------------------------------------------------------- -//* \fn AT91F_AIC_SetExceptionVector -//* \brief Configure vector handler -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_AIC_SetExceptionVector ( - unsigned int *pVector, // \arg pointer to the AIC registers - void (*Handler) () ) // \arg Interrupt Handler +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_AIC_SetExceptionVector */ +/** \brief Configure vector handler */ +/**---------------------------------------------------------------------------- */ +__inline unsigned int AT91F_AIC_SetExceptionVector( unsigned int * pVector, /* \arg pointer to the AIC registers */ + void ( * Handler )() ) /* \arg Interrupt Handler */ { unsigned int oldVector = *pVector; - if ((unsigned int) Handler == (unsigned int) AT91C_AIC_BRANCH_OPCODE) - *pVector = (unsigned int) AT91C_AIC_BRANCH_OPCODE; + if( ( unsigned int ) Handler == ( unsigned int ) AT91C_AIC_BRANCH_OPCODE ) + { + *pVector = ( unsigned int ) AT91C_AIC_BRANCH_OPCODE; + } else - *pVector = (((((unsigned int) Handler) - ((unsigned int) pVector) - 0x8) >> 2) & 0x00FFFFFF) | 0xEA000000; + { + *pVector = ( ( ( ( ( unsigned int ) Handler ) - ( ( unsigned int ) pVector ) - 0x8 ) >> 2 ) & 0x00FFFFFF ) | 0xEA000000; + } return oldVector; } -//*---------------------------------------------------------------------------- -//* \fn AT91F_AIC_Trig -//* \brief Trig an IT -//*---------------------------------------------------------------------------- -__inline void AT91F_AIC_Trig ( - AT91PS_AIC pAic, // \arg pointer to the AIC registers - unsigned int irq_id) // \arg interrupt number +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_AIC_Trig */ +/** \brief Trig an IT */ +/**---------------------------------------------------------------------------- */ +__inline void AT91F_AIC_Trig( AT91PS_AIC pAic, /* \arg pointer to the AIC registers */ + unsigned int irq_id ) /* \arg interrupt number */ { - pAic->AIC_ISCR = (0x1 << irq_id) ; + pAic->AIC_ISCR = ( 0x1 << irq_id ); } -//*---------------------------------------------------------------------------- -//* \fn AT91F_AIC_IsActive -//* \brief Test if an IT is active -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_AIC_IsActive ( - AT91PS_AIC pAic, // \arg pointer to the AIC registers - unsigned int irq_id) // \arg Interrupt Number +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_AIC_IsActive */ +/** \brief Test if an IT is active */ +/**---------------------------------------------------------------------------- */ +__inline unsigned int AT91F_AIC_IsActive( AT91PS_AIC pAic, /* \arg pointer to the AIC registers */ + unsigned int irq_id ) /* \arg Interrupt Number */ { - return (pAic->AIC_ISR & (0x1 << irq_id)); + return( pAic->AIC_ISR & ( 0x1 << irq_id ) ); } -//*---------------------------------------------------------------------------- -//* \fn AT91F_AIC_IsPending -//* \brief Test if an IT is pending -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_AIC_IsPending ( - AT91PS_AIC pAic, // \arg pointer to the AIC registers - unsigned int irq_id) // \arg Interrupt Number +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_AIC_IsPending */ +/** \brief Test if an IT is pending */ +/**---------------------------------------------------------------------------- */ +__inline unsigned int AT91F_AIC_IsPending( AT91PS_AIC pAic, /* \arg pointer to the AIC registers */ + unsigned int irq_id ) /* \arg Interrupt Number */ { - return (pAic->AIC_IPR & (0x1 << irq_id)); + return( pAic->AIC_IPR & ( 0x1 << irq_id ) ); } -//*---------------------------------------------------------------------------- -//* \fn AT91F_AIC_Open -//* \brief Set exception vectors and AIC registers to default values -//*---------------------------------------------------------------------------- -__inline void AT91F_AIC_Open( - AT91PS_AIC pAic, // \arg pointer to the AIC registers - void (*IrqHandler) (), // \arg Default IRQ vector exception - void (*FiqHandler) (), // \arg Default FIQ vector exception - void (*DefaultHandler) (), // \arg Default Handler set in ISR - void (*SpuriousHandler) (), // \arg Default Spurious Handler - unsigned int protectMode) // \arg Debug Control Register +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_AIC_Open */ +/** \brief Set exception vectors and AIC registers to default values */ +/**---------------------------------------------------------------------------- */ +__inline void AT91F_AIC_Open( AT91PS_AIC pAic, /* \arg pointer to the AIC registers */ + void ( * IrqHandler )(), /* \arg Default IRQ vector exception */ + void ( * FiqHandler )(), /* \arg Default FIQ vector exception */ + void ( * DefaultHandler )(), /* \arg Default Handler set in ISR */ + void ( * SpuriousHandler )(), /* \arg Default Spurious Handler */ + unsigned int protectMode ) /* \arg Debug Control Register */ { int i; - // Disable all interrupts and set IVR to the default handler - for (i = 0; i < 32; ++i) { - AT91F_AIC_DisableIt(pAic, i); - AT91F_AIC_ConfigureIt(pAic, i, AT91C_AIC_PRIOR_LOWEST, AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE, DefaultHandler); + /* Disable all interrupts and set IVR to the default handler */ + for( i = 0; i < 32; ++i ) + { + AT91F_AIC_DisableIt( pAic, i ); + AT91F_AIC_ConfigureIt( pAic, i, AT91C_AIC_PRIOR_LOWEST, AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE, DefaultHandler ); } - // Set the IRQ exception vector - AT91F_AIC_SetExceptionVector((unsigned int *) 0x18, IrqHandler); - // Set the Fast Interrupt exception vector - AT91F_AIC_SetExceptionVector((unsigned int *) 0x1C, FiqHandler); + /* Set the IRQ exception vector */ + AT91F_AIC_SetExceptionVector( ( unsigned int * ) 0x18, IrqHandler ); + /* Set the Fast Interrupt exception vector */ + AT91F_AIC_SetExceptionVector( ( unsigned int * ) 0x1C, FiqHandler ); - pAic->AIC_SPU = (unsigned int) SpuriousHandler; + pAic->AIC_SPU = ( unsigned int ) SpuriousHandler; pAic->AIC_DCR = protectMode; } -//*---------------------------------------------------------------------------- -//* \fn AT91F_MC_CfgPMC -//* \brief Enable Peripheral clock in PMC for MC -//*---------------------------------------------------------------------------- -__inline void AT91F_MC_CfgPMC (void) +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_MC_CfgPMC */ +/** \brief Enable Peripheral clock in PMC for MC */ +/**---------------------------------------------------------------------------- */ +__inline void AT91F_MC_CfgPMC( void ) { AT91F_PMC_EnablePeriphClock( - AT91C_BASE_PMC, // PIO controller base address - ((unsigned int) 1 << AT91C_ID_SYS)); + AT91C_BASE_PMC, /* PIO controller base address */ + ( ( unsigned int ) 1 << AT91C_ID_SYS ) ); } -//*---------------------------------------------------------------------------- -//* \fn AT91F_DBGU_CfgPMC -//* \brief Enable Peripheral clock in PMC for DBGU -//*---------------------------------------------------------------------------- -__inline void AT91F_DBGU_CfgPMC (void) +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_DBGU_CfgPMC */ +/** \brief Enable Peripheral clock in PMC for DBGU */ +/**---------------------------------------------------------------------------- */ +__inline void AT91F_DBGU_CfgPMC( void ) { AT91F_PMC_EnablePeriphClock( - AT91C_BASE_PMC, // PIO controller base address - ((unsigned int) 1 << AT91C_ID_SYS)); + AT91C_BASE_PMC, /* PIO controller base address */ + ( ( unsigned int ) 1 << AT91C_ID_SYS ) ); } -//*---------------------------------------------------------------------------- -//* \fn AT91F_DBGU_CfgPIO -//* \brief Configure PIO controllers to drive DBGU signals -//*---------------------------------------------------------------------------- -__inline void AT91F_DBGU_CfgPIO (void) +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_DBGU_CfgPIO */ +/** \brief Configure PIO controllers to drive DBGU signals */ +/**---------------------------------------------------------------------------- */ +__inline void AT91F_DBGU_CfgPIO( void ) { - // Configure PIO controllers to periph mode + /* Configure PIO controllers to periph mode */ AT91F_PIO_CfgPeriph( - AT91C_BASE_PIOA, // PIO controller base address - ((unsigned int) AT91C_PA10_DTXD ) | - ((unsigned int) AT91C_PA9_DRXD ), // Peripheral A - 0); // Peripheral B + AT91C_BASE_PIOA, /* PIO controller base address */ + ( ( unsigned int ) AT91C_PA10_DTXD ) | + ( ( unsigned int ) AT91C_PA9_DRXD ), /* Peripheral A */ + 0 ); /* Peripheral B */ } -//*---------------------------------------------------------------------------- -//* \fn AT91F_PWMC_CH3_CfgPIO -//* \brief Configure PIO controllers to drive PWMC_CH3 signals -//*---------------------------------------------------------------------------- -__inline void AT91F_PWMC_CH3_CfgPIO (void) +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PWMC_CH3_CfgPIO */ +/** \brief Configure PIO controllers to drive PWMC_CH3 signals */ +/**---------------------------------------------------------------------------- */ +__inline void AT91F_PWMC_CH3_CfgPIO( void ) { - // Configure PIO controllers to periph mode + /* Configure PIO controllers to periph mode */ AT91F_PIO_CfgPeriph( - AT91C_BASE_PIOA, // PIO controller base address - 0, // Peripheral A - ((unsigned int) AT91C_PA14_PWM3 ) | - ((unsigned int) AT91C_PA7_PWM3 )); // Peripheral B + AT91C_BASE_PIOA, /* PIO controller base address */ + 0, /* Peripheral A */ + ( ( unsigned int ) AT91C_PA14_PWM3 ) | + ( ( unsigned int ) AT91C_PA7_PWM3 ) ); /* Peripheral B */ } -//*---------------------------------------------------------------------------- -//* \fn AT91F_PWMC_CH2_CfgPIO -//* \brief Configure PIO controllers to drive PWMC_CH2 signals -//*---------------------------------------------------------------------------- -__inline void AT91F_PWMC_CH2_CfgPIO (void) +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PWMC_CH2_CfgPIO */ +/** \brief Configure PIO controllers to drive PWMC_CH2 signals */ +/**---------------------------------------------------------------------------- */ +__inline void AT91F_PWMC_CH2_CfgPIO( void ) { - // Configure PIO controllers to periph mode + /* Configure PIO controllers to periph mode */ AT91F_PIO_CfgPeriph( - AT91C_BASE_PIOA, // PIO controller base address - ((unsigned int) AT91C_PA2_PWM2 ), // Peripheral A - ((unsigned int) AT91C_PA25_PWM2 ) | - ((unsigned int) AT91C_PA13_PWM2 )); // Peripheral B + AT91C_BASE_PIOA, /* PIO controller base address */ + ( ( unsigned int ) AT91C_PA2_PWM2 ), /* Peripheral A */ + ( ( unsigned int ) AT91C_PA25_PWM2 ) | + ( ( unsigned int ) AT91C_PA13_PWM2 ) ); /* Peripheral B */ } -//*---------------------------------------------------------------------------- -//* \fn AT91F_PWMC_CH1_CfgPIO -//* \brief Configure PIO controllers to drive PWMC_CH1 signals -//*---------------------------------------------------------------------------- -__inline void AT91F_PWMC_CH1_CfgPIO (void) +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PWMC_CH1_CfgPIO */ +/** \brief Configure PIO controllers to drive PWMC_CH1 signals */ +/**---------------------------------------------------------------------------- */ +__inline void AT91F_PWMC_CH1_CfgPIO( void ) { - // Configure PIO controllers to periph mode + /* Configure PIO controllers to periph mode */ AT91F_PIO_CfgPeriph( - AT91C_BASE_PIOA, // PIO controller base address - ((unsigned int) AT91C_PA1_PWM1 ), // Peripheral A - ((unsigned int) AT91C_PA24_PWM1 ) | - ((unsigned int) AT91C_PA12_PWM1 )); // Peripheral B + AT91C_BASE_PIOA, /* PIO controller base address */ + ( ( unsigned int ) AT91C_PA1_PWM1 ), /* Peripheral A */ + ( ( unsigned int ) AT91C_PA24_PWM1 ) | + ( ( unsigned int ) AT91C_PA12_PWM1 ) ); /* Peripheral B */ } -//*---------------------------------------------------------------------------- -//* \fn AT91F_PWMC_CH0_CfgPIO -//* \brief Configure PIO controllers to drive PWMC_CH0 signals -//*---------------------------------------------------------------------------- -__inline void AT91F_PWMC_CH0_CfgPIO (void) +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PWMC_CH0_CfgPIO */ +/** \brief Configure PIO controllers to drive PWMC_CH0 signals */ +/**---------------------------------------------------------------------------- */ +__inline void AT91F_PWMC_CH0_CfgPIO( void ) { - // Configure PIO controllers to periph mode + /* Configure PIO controllers to periph mode */ AT91F_PIO_CfgPeriph( - AT91C_BASE_PIOA, // PIO controller base address - ((unsigned int) AT91C_PA0_PWM0 ), // Peripheral A - ((unsigned int) AT91C_PA23_PWM0 ) | - ((unsigned int) AT91C_PA11_PWM0 )); // Peripheral B + AT91C_BASE_PIOA, /* PIO controller base address */ + ( ( unsigned int ) AT91C_PA0_PWM0 ), /* Peripheral A */ + ( ( unsigned int ) AT91C_PA23_PWM0 ) | + ( ( unsigned int ) AT91C_PA11_PWM0 ) ); /* Peripheral B */ } -//*---------------------------------------------------------------------------- -//* \fn AT91F_SSC_CfgPMC -//* \brief Enable Peripheral clock in PMC for SSC -//*---------------------------------------------------------------------------- -__inline void AT91F_SSC_CfgPMC (void) +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_SSC_CfgPMC */ +/** \brief Enable Peripheral clock in PMC for SSC */ +/**---------------------------------------------------------------------------- */ +__inline void AT91F_SSC_CfgPMC( void ) { AT91F_PMC_EnablePeriphClock( - AT91C_BASE_PMC, // PIO controller base address - ((unsigned int) 1 << AT91C_ID_SSC)); + AT91C_BASE_PMC, /* PIO controller base address */ + ( ( unsigned int ) 1 << AT91C_ID_SSC ) ); } -//*---------------------------------------------------------------------------- -//* \fn AT91F_SSC_CfgPIO -//* \brief Configure PIO controllers to drive SSC signals -//*---------------------------------------------------------------------------- -__inline void AT91F_SSC_CfgPIO (void) +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_SSC_CfgPIO */ +/** \brief Configure PIO controllers to drive SSC signals */ +/**---------------------------------------------------------------------------- */ +__inline void AT91F_SSC_CfgPIO( void ) { - // Configure PIO controllers to periph mode + /* Configure PIO controllers to periph mode */ AT91F_PIO_CfgPeriph( - AT91C_BASE_PIOA, // PIO controller base address - ((unsigned int) AT91C_PA17_TD ) | - ((unsigned int) AT91C_PA15_TF ) | - ((unsigned int) AT91C_PA19_RK ) | - ((unsigned int) AT91C_PA18_RD ) | - ((unsigned int) AT91C_PA20_RF ) | - ((unsigned int) AT91C_PA16_TK ), // Peripheral A - 0); // Peripheral B -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_SPI_CfgPMC -//* \brief Enable Peripheral clock in PMC for SPI -//*---------------------------------------------------------------------------- -__inline void AT91F_SPI_CfgPMC (void) + AT91C_BASE_PIOA, /* PIO controller base address */ + ( ( unsigned int ) AT91C_PA17_TD ) | + ( ( unsigned int ) AT91C_PA15_TF ) | + ( ( unsigned int ) AT91C_PA19_RK ) | + ( ( unsigned int ) AT91C_PA18_RD ) | + ( ( unsigned int ) AT91C_PA20_RF ) | + ( ( unsigned int ) AT91C_PA16_TK ), /* Peripheral A */ + 0 ); /* Peripheral B */ +} + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_SPI_CfgPMC */ +/** \brief Enable Peripheral clock in PMC for SPI */ +/**---------------------------------------------------------------------------- */ +__inline void AT91F_SPI_CfgPMC( void ) { AT91F_PMC_EnablePeriphClock( - AT91C_BASE_PMC, // PIO controller base address - ((unsigned int) 1 << AT91C_ID_SPI)); + AT91C_BASE_PMC, /* PIO controller base address */ + ( ( unsigned int ) 1 << AT91C_ID_SPI ) ); } -//*---------------------------------------------------------------------------- -//* \fn AT91F_SPI_CfgPIO -//* \brief Configure PIO controllers to drive SPI signals -//*---------------------------------------------------------------------------- -__inline void AT91F_SPI_CfgPIO (void) +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_SPI_CfgPIO */ +/** \brief Configure PIO controllers to drive SPI signals */ +/**---------------------------------------------------------------------------- */ +__inline void AT91F_SPI_CfgPIO( void ) { - // Configure PIO controllers to periph mode + /* Configure PIO controllers to periph mode */ AT91F_PIO_CfgPeriph( - AT91C_BASE_PIOA, // PIO controller base address - ((unsigned int) AT91C_PA11_NPCS0 ) | - ((unsigned int) AT91C_PA13_MOSI ) | - ((unsigned int) AT91C_PA31_NPCS1 ) | - ((unsigned int) AT91C_PA12_MISO ) | - ((unsigned int) AT91C_PA14_SPCK ), // Peripheral A - ((unsigned int) AT91C_PA9_NPCS1 ) | - ((unsigned int) AT91C_PA30_NPCS2 ) | - ((unsigned int) AT91C_PA10_NPCS2 ) | - ((unsigned int) AT91C_PA22_NPCS3 ) | - ((unsigned int) AT91C_PA3_NPCS3 ) | - ((unsigned int) AT91C_PA5_NPCS3 )); // Peripheral B -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PWMC_CfgPMC -//* \brief Enable Peripheral clock in PMC for PWMC -//*---------------------------------------------------------------------------- -__inline void AT91F_PWMC_CfgPMC (void) + AT91C_BASE_PIOA, /* PIO controller base address */ + ( ( unsigned int ) AT91C_PA11_NPCS0 ) | + ( ( unsigned int ) AT91C_PA13_MOSI ) | + ( ( unsigned int ) AT91C_PA31_NPCS1 ) | + ( ( unsigned int ) AT91C_PA12_MISO ) | + ( ( unsigned int ) AT91C_PA14_SPCK ), /* Peripheral A */ + ( ( unsigned int ) AT91C_PA9_NPCS1 ) | + ( ( unsigned int ) AT91C_PA30_NPCS2 ) | + ( ( unsigned int ) AT91C_PA10_NPCS2 ) | + ( ( unsigned int ) AT91C_PA22_NPCS3 ) | + ( ( unsigned int ) AT91C_PA3_NPCS3 ) | + ( ( unsigned int ) AT91C_PA5_NPCS3 ) ); /* Peripheral B */ +} + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PWMC_CfgPMC */ +/** \brief Enable Peripheral clock in PMC for PWMC */ +/**---------------------------------------------------------------------------- */ +__inline void AT91F_PWMC_CfgPMC( void ) { AT91F_PMC_EnablePeriphClock( - AT91C_BASE_PMC, // PIO controller base address - ((unsigned int) 1 << AT91C_ID_PWMC)); + AT91C_BASE_PMC, /* PIO controller base address */ + ( ( unsigned int ) 1 << AT91C_ID_PWMC ) ); } -//*---------------------------------------------------------------------------- -//* \fn AT91F_TC2_CfgPMC -//* \brief Enable Peripheral clock in PMC for TC2 -//*---------------------------------------------------------------------------- -__inline void AT91F_TC2_CfgPMC (void) +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_TC2_CfgPMC */ +/** \brief Enable Peripheral clock in PMC for TC2 */ +/**---------------------------------------------------------------------------- */ +__inline void AT91F_TC2_CfgPMC( void ) { AT91F_PMC_EnablePeriphClock( - AT91C_BASE_PMC, // PIO controller base address - ((unsigned int) 1 << AT91C_ID_TC2)); + AT91C_BASE_PMC, /* PIO controller base address */ + ( ( unsigned int ) 1 << AT91C_ID_TC2 ) ); } -//*---------------------------------------------------------------------------- -//* \fn AT91F_TC2_CfgPIO -//* \brief Configure PIO controllers to drive TC2 signals -//*---------------------------------------------------------------------------- -__inline void AT91F_TC2_CfgPIO (void) +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_TC2_CfgPIO */ +/** \brief Configure PIO controllers to drive TC2 signals */ +/**---------------------------------------------------------------------------- */ +__inline void AT91F_TC2_CfgPIO( void ) { - // Configure PIO controllers to periph mode + /* Configure PIO controllers to periph mode */ AT91F_PIO_CfgPeriph( - AT91C_BASE_PIOA, // PIO controller base address - 0, // Peripheral A - ((unsigned int) AT91C_PA26_TIOA2 ) | - ((unsigned int) AT91C_PA27_TIOB2 ) | - ((unsigned int) AT91C_PA29_TCLK2 )); // Peripheral B + AT91C_BASE_PIOA, /* PIO controller base address */ + 0, /* Peripheral A */ + ( ( unsigned int ) AT91C_PA26_TIOA2 ) | + ( ( unsigned int ) AT91C_PA27_TIOB2 ) | + ( ( unsigned int ) AT91C_PA29_TCLK2 ) ); /* Peripheral B */ } -//*---------------------------------------------------------------------------- -//* \fn AT91F_TC1_CfgPMC -//* \brief Enable Peripheral clock in PMC for TC1 -//*---------------------------------------------------------------------------- -__inline void AT91F_TC1_CfgPMC (void) +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_TC1_CfgPMC */ +/** \brief Enable Peripheral clock in PMC for TC1 */ +/**---------------------------------------------------------------------------- */ +__inline void AT91F_TC1_CfgPMC( void ) { AT91F_PMC_EnablePeriphClock( - AT91C_BASE_PMC, // PIO controller base address - ((unsigned int) 1 << AT91C_ID_TC1)); + AT91C_BASE_PMC, /* PIO controller base address */ + ( ( unsigned int ) 1 << AT91C_ID_TC1 ) ); } -//*---------------------------------------------------------------------------- -//* \fn AT91F_TC1_CfgPIO -//* \brief Configure PIO controllers to drive TC1 signals -//*---------------------------------------------------------------------------- -__inline void AT91F_TC1_CfgPIO (void) +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_TC1_CfgPIO */ +/** \brief Configure PIO controllers to drive TC1 signals */ +/**---------------------------------------------------------------------------- */ +__inline void AT91F_TC1_CfgPIO( void ) { - // Configure PIO controllers to periph mode + /* Configure PIO controllers to periph mode */ AT91F_PIO_CfgPeriph( - AT91C_BASE_PIOA, // PIO controller base address - 0, // Peripheral A - ((unsigned int) AT91C_PA15_TIOA1 ) | - ((unsigned int) AT91C_PA16_TIOB1 ) | - ((unsigned int) AT91C_PA28_TCLK1 )); // Peripheral B + AT91C_BASE_PIOA, /* PIO controller base address */ + 0, /* Peripheral A */ + ( ( unsigned int ) AT91C_PA15_TIOA1 ) | + ( ( unsigned int ) AT91C_PA16_TIOB1 ) | + ( ( unsigned int ) AT91C_PA28_TCLK1 ) ); /* Peripheral B */ } -//*---------------------------------------------------------------------------- -//* \fn AT91F_TC0_CfgPMC -//* \brief Enable Peripheral clock in PMC for TC0 -//*---------------------------------------------------------------------------- -__inline void AT91F_TC0_CfgPMC (void) +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_TC0_CfgPMC */ +/** \brief Enable Peripheral clock in PMC for TC0 */ +/**---------------------------------------------------------------------------- */ +__inline void AT91F_TC0_CfgPMC( void ) { AT91F_PMC_EnablePeriphClock( - AT91C_BASE_PMC, // PIO controller base address - ((unsigned int) 1 << AT91C_ID_TC0)); + AT91C_BASE_PMC, /* PIO controller base address */ + ( ( unsigned int ) 1 << AT91C_ID_TC0 ) ); } -//*---------------------------------------------------------------------------- -//* \fn AT91F_TC0_CfgPIO -//* \brief Configure PIO controllers to drive TC0 signals -//*---------------------------------------------------------------------------- -__inline void AT91F_TC0_CfgPIO (void) +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_TC0_CfgPIO */ +/** \brief Configure PIO controllers to drive TC0 signals */ +/**---------------------------------------------------------------------------- */ +__inline void AT91F_TC0_CfgPIO( void ) { - // Configure PIO controllers to periph mode + /* Configure PIO controllers to periph mode */ AT91F_PIO_CfgPeriph( - AT91C_BASE_PIOA, // PIO controller base address - 0, // Peripheral A - ((unsigned int) AT91C_PA0_TIOA0 ) | - ((unsigned int) AT91C_PA1_TIOB0 ) | - ((unsigned int) AT91C_PA4_TCLK0 )); // Peripheral B + AT91C_BASE_PIOA, /* PIO controller base address */ + 0, /* Peripheral A */ + ( ( unsigned int ) AT91C_PA0_TIOA0 ) | + ( ( unsigned int ) AT91C_PA1_TIOB0 ) | + ( ( unsigned int ) AT91C_PA4_TCLK0 ) ); /* Peripheral B */ } -//*---------------------------------------------------------------------------- -//* \fn AT91F_PMC_CfgPMC -//* \brief Enable Peripheral clock in PMC for PMC -//*---------------------------------------------------------------------------- -__inline void AT91F_PMC_CfgPMC (void) +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PMC_CfgPMC */ +/** \brief Enable Peripheral clock in PMC for PMC */ +/**---------------------------------------------------------------------------- */ +__inline void AT91F_PMC_CfgPMC( void ) { AT91F_PMC_EnablePeriphClock( - AT91C_BASE_PMC, // PIO controller base address - ((unsigned int) 1 << AT91C_ID_SYS)); + AT91C_BASE_PMC, /* PIO controller base address */ + ( ( unsigned int ) 1 << AT91C_ID_SYS ) ); } -//*---------------------------------------------------------------------------- -//* \fn AT91F_PMC_CfgPIO -//* \brief Configure PIO controllers to drive PMC signals -//*---------------------------------------------------------------------------- -__inline void AT91F_PMC_CfgPIO (void) +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PMC_CfgPIO */ +/** \brief Configure PIO controllers to drive PMC signals */ +/**---------------------------------------------------------------------------- */ +__inline void AT91F_PMC_CfgPIO( void ) { - // Configure PIO controllers to periph mode + /* Configure PIO controllers to periph mode */ AT91F_PIO_CfgPeriph( - AT91C_BASE_PIOA, // PIO controller base address - 0, // Peripheral A - ((unsigned int) AT91C_PA17_PCK1 ) | - ((unsigned int) AT91C_PA21_PCK1 ) | - ((unsigned int) AT91C_PA31_PCK2 ) | - ((unsigned int) AT91C_PA18_PCK2 ) | - ((unsigned int) AT91C_PA6_PCK0 )); // Peripheral B + AT91C_BASE_PIOA, /* PIO controller base address */ + 0, /* Peripheral A */ + ( ( unsigned int ) AT91C_PA17_PCK1 ) | + ( ( unsigned int ) AT91C_PA21_PCK1 ) | + ( ( unsigned int ) AT91C_PA31_PCK2 ) | + ( ( unsigned int ) AT91C_PA18_PCK2 ) | + ( ( unsigned int ) AT91C_PA6_PCK0 ) ); /* Peripheral B */ } -//*---------------------------------------------------------------------------- -//* \fn AT91F_ADC_CfgPMC -//* \brief Enable Peripheral clock in PMC for ADC -//*---------------------------------------------------------------------------- -__inline void AT91F_ADC_CfgPMC (void) +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_ADC_CfgPMC */ +/** \brief Enable Peripheral clock in PMC for ADC */ +/**---------------------------------------------------------------------------- */ +__inline void AT91F_ADC_CfgPMC( void ) { AT91F_PMC_EnablePeriphClock( - AT91C_BASE_PMC, // PIO controller base address - ((unsigned int) 1 << AT91C_ID_ADC)); + AT91C_BASE_PMC, /* PIO controller base address */ + ( ( unsigned int ) 1 << AT91C_ID_ADC ) ); } -//*---------------------------------------------------------------------------- -//* \fn AT91F_ADC_CfgPIO -//* \brief Configure PIO controllers to drive ADC signals -//*---------------------------------------------------------------------------- -__inline void AT91F_ADC_CfgPIO (void) +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_ADC_CfgPIO */ +/** \brief Configure PIO controllers to drive ADC signals */ +/**---------------------------------------------------------------------------- */ +__inline void AT91F_ADC_CfgPIO( void ) { - // Configure PIO controllers to periph mode + /* Configure PIO controllers to periph mode */ AT91F_PIO_CfgPeriph( - AT91C_BASE_PIOA, // PIO controller base address - 0, // Peripheral A - ((unsigned int) AT91C_PA8_ADTRG )); // Peripheral B + AT91C_BASE_PIOA, /* PIO controller base address */ + 0, /* Peripheral A */ + ( ( unsigned int ) AT91C_PA8_ADTRG ) ); /* Peripheral B */ } -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIOA_CfgPMC -//* \brief Enable Peripheral clock in PMC for PIOA -//*---------------------------------------------------------------------------- -__inline void AT91F_PIOA_CfgPMC (void) +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PIOA_CfgPMC */ +/** \brief Enable Peripheral clock in PMC for PIOA */ +/**---------------------------------------------------------------------------- */ +__inline void AT91F_PIOA_CfgPMC( void ) { AT91F_PMC_EnablePeriphClock( - AT91C_BASE_PMC, // PIO controller base address - ((unsigned int) 1 << AT91C_ID_PIOA)); + AT91C_BASE_PMC, /* PIO controller base address */ + ( ( unsigned int ) 1 << AT91C_ID_PIOA ) ); } -//*---------------------------------------------------------------------------- -//* \fn AT91F_TWI_CfgPMC -//* \brief Enable Peripheral clock in PMC for TWI -//*---------------------------------------------------------------------------- -__inline void AT91F_TWI_CfgPMC (void) +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_TWI_CfgPMC */ +/** \brief Enable Peripheral clock in PMC for TWI */ +/**---------------------------------------------------------------------------- */ +__inline void AT91F_TWI_CfgPMC( void ) { AT91F_PMC_EnablePeriphClock( - AT91C_BASE_PMC, // PIO controller base address - ((unsigned int) 1 << AT91C_ID_TWI)); + AT91C_BASE_PMC, /* PIO controller base address */ + ( ( unsigned int ) 1 << AT91C_ID_TWI ) ); } -//*---------------------------------------------------------------------------- -//* \fn AT91F_TWI_CfgPIO -//* \brief Configure PIO controllers to drive TWI signals -//*---------------------------------------------------------------------------- -__inline void AT91F_TWI_CfgPIO (void) +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_TWI_CfgPIO */ +/** \brief Configure PIO controllers to drive TWI signals */ +/**---------------------------------------------------------------------------- */ +__inline void AT91F_TWI_CfgPIO( void ) { - // Configure PIO controllers to periph mode + /* Configure PIO controllers to periph mode */ AT91F_PIO_CfgPeriph( - AT91C_BASE_PIOA, // PIO controller base address - ((unsigned int) AT91C_PA3_TWD ) | - ((unsigned int) AT91C_PA4_TWCK ), // Peripheral A - 0); // Peripheral B + AT91C_BASE_PIOA, /* PIO controller base address */ + ( ( unsigned int ) AT91C_PA3_TWD ) | + ( ( unsigned int ) AT91C_PA4_TWCK ), /* Peripheral A */ + 0 ); /* Peripheral B */ } -//*---------------------------------------------------------------------------- -//* \fn AT91F_US1_CfgPMC -//* \brief Enable Peripheral clock in PMC for US1 -//*---------------------------------------------------------------------------- -__inline void AT91F_US1_CfgPMC (void) +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_US1_CfgPMC */ +/** \brief Enable Peripheral clock in PMC for US1 */ +/**---------------------------------------------------------------------------- */ +__inline void AT91F_US1_CfgPMC( void ) { AT91F_PMC_EnablePeriphClock( - AT91C_BASE_PMC, // PIO controller base address - ((unsigned int) 1 << AT91C_ID_US1)); + AT91C_BASE_PMC, /* PIO controller base address */ + ( ( unsigned int ) 1 << AT91C_ID_US1 ) ); } -//*---------------------------------------------------------------------------- -//* \fn AT91F_US1_CfgPIO -//* \brief Configure PIO controllers to drive US1 signals -//*---------------------------------------------------------------------------- -__inline void AT91F_US1_CfgPIO (void) +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_US1_CfgPIO */ +/** \brief Configure PIO controllers to drive US1 signals */ +/**---------------------------------------------------------------------------- */ +__inline void AT91F_US1_CfgPIO( void ) { - // Configure PIO controllers to periph mode + /* Configure PIO controllers to periph mode */ AT91F_PIO_CfgPeriph( - AT91C_BASE_PIOA, // PIO controller base address - ((unsigned int) AT91C_PA21_RXD1 ) | - ((unsigned int) AT91C_PA27_DTR1 ) | - ((unsigned int) AT91C_PA26_DCD1 ) | - ((unsigned int) AT91C_PA22_TXD1 ) | - ((unsigned int) AT91C_PA24_RTS1 ) | - ((unsigned int) AT91C_PA23_SCK1 ) | - ((unsigned int) AT91C_PA28_DSR1 ) | - ((unsigned int) AT91C_PA29_RI1 ) | - ((unsigned int) AT91C_PA25_CTS1 ), // Peripheral A - 0); // Peripheral B -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_US0_CfgPMC -//* \brief Enable Peripheral clock in PMC for US0 -//*---------------------------------------------------------------------------- -__inline void AT91F_US0_CfgPMC (void) + AT91C_BASE_PIOA, /* PIO controller base address */ + ( ( unsigned int ) AT91C_PA21_RXD1 ) | + ( ( unsigned int ) AT91C_PA27_DTR1 ) | + ( ( unsigned int ) AT91C_PA26_DCD1 ) | + ( ( unsigned int ) AT91C_PA22_TXD1 ) | + ( ( unsigned int ) AT91C_PA24_RTS1 ) | + ( ( unsigned int ) AT91C_PA23_SCK1 ) | + ( ( unsigned int ) AT91C_PA28_DSR1 ) | + ( ( unsigned int ) AT91C_PA29_RI1 ) | + ( ( unsigned int ) AT91C_PA25_CTS1 ), /* Peripheral A */ + 0 ); /* Peripheral B */ +} + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_US0_CfgPMC */ +/** \brief Enable Peripheral clock in PMC for US0 */ +/**---------------------------------------------------------------------------- */ +__inline void AT91F_US0_CfgPMC( void ) { AT91F_PMC_EnablePeriphClock( - AT91C_BASE_PMC, // PIO controller base address - ((unsigned int) 1 << AT91C_ID_US0)); + AT91C_BASE_PMC, /* PIO controller base address */ + ( ( unsigned int ) 1 << AT91C_ID_US0 ) ); } -//*---------------------------------------------------------------------------- -//* \fn AT91F_US0_CfgPIO -//* \brief Configure PIO controllers to drive US0 signals -//*---------------------------------------------------------------------------- -__inline void AT91F_US0_CfgPIO (void) +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_US0_CfgPIO */ +/** \brief Configure PIO controllers to drive US0 signals */ +/**---------------------------------------------------------------------------- */ +__inline void AT91F_US0_CfgPIO( void ) { - // Configure PIO controllers to periph mode + /* Configure PIO controllers to periph mode */ AT91F_PIO_CfgPeriph( - AT91C_BASE_PIOA, // PIO controller base address - ((unsigned int) AT91C_PA5_RXD0 ) | - ((unsigned int) AT91C_PA6_TXD0 ) | - ((unsigned int) AT91C_PA7_RTS0 ) | - ((unsigned int) AT91C_PA8_CTS0 ), // Peripheral A - ((unsigned int) AT91C_PA2_SCK0 )); // Peripheral B + AT91C_BASE_PIOA, /* PIO controller base address */ + ( ( unsigned int ) AT91C_PA5_RXD0 ) | + ( ( unsigned int ) AT91C_PA6_TXD0 ) | + ( ( unsigned int ) AT91C_PA7_RTS0 ) | + ( ( unsigned int ) AT91C_PA8_CTS0 ), /* Peripheral A */ + ( ( unsigned int ) AT91C_PA2_SCK0 ) ); /* Peripheral B */ } -//*---------------------------------------------------------------------------- -//* \fn AT91F_UDP_CfgPMC -//* \brief Enable Peripheral clock in PMC for UDP -//*---------------------------------------------------------------------------- -__inline void AT91F_UDP_CfgPMC (void) +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_UDP_CfgPMC */ +/** \brief Enable Peripheral clock in PMC for UDP */ +/**---------------------------------------------------------------------------- */ +__inline void AT91F_UDP_CfgPMC( void ) { AT91F_PMC_EnablePeriphClock( - AT91C_BASE_PMC, // PIO controller base address - ((unsigned int) 1 << AT91C_ID_UDP)); + AT91C_BASE_PMC, /* PIO controller base address */ + ( ( unsigned int ) 1 << AT91C_ID_UDP ) ); } -//*---------------------------------------------------------------------------- -//* \fn AT91F_AIC_CfgPMC -//* \brief Enable Peripheral clock in PMC for AIC -//*---------------------------------------------------------------------------- -__inline void AT91F_AIC_CfgPMC (void) +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_AIC_CfgPMC */ +/** \brief Enable Peripheral clock in PMC for AIC */ +/**---------------------------------------------------------------------------- */ +__inline void AT91F_AIC_CfgPMC( void ) { AT91F_PMC_EnablePeriphClock( - AT91C_BASE_PMC, // PIO controller base address - ((unsigned int) 1 << AT91C_ID_IRQ0) | - ((unsigned int) 1 << AT91C_ID_FIQ) | - ((unsigned int) 1 << AT91C_ID_IRQ1)); + AT91C_BASE_PMC, /* PIO controller base address */ + ( ( unsigned int ) 1 << AT91C_ID_IRQ0 ) | + ( ( unsigned int ) 1 << AT91C_ID_FIQ ) | + ( ( unsigned int ) 1 << AT91C_ID_IRQ1 ) ); } -//*---------------------------------------------------------------------------- -//* \fn AT91F_AIC_CfgPIO -//* \brief Configure PIO controllers to drive AIC signals -//*---------------------------------------------------------------------------- -__inline void AT91F_AIC_CfgPIO (void) +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_AIC_CfgPIO */ +/** \brief Configure PIO controllers to drive AIC signals */ +/**---------------------------------------------------------------------------- */ +__inline void AT91F_AIC_CfgPIO( void ) { - // Configure PIO controllers to periph mode + /* Configure PIO controllers to periph mode */ AT91F_PIO_CfgPeriph( - AT91C_BASE_PIOA, // PIO controller base address - ((unsigned int) AT91C_PA30_IRQ1 ), // Peripheral A - ((unsigned int) AT91C_PA20_IRQ0 ) | - ((unsigned int) AT91C_PA19_FIQ )); // Peripheral B + AT91C_BASE_PIOA, /* PIO controller base address */ + ( ( unsigned int ) AT91C_PA30_IRQ1 ), /* Peripheral A */ + ( ( unsigned int ) AT91C_PA20_IRQ0 ) | + ( ( unsigned int ) AT91C_PA19_FIQ ) ); /* Peripheral B */ } #endif // lib_AT91SAM7S64_H diff --git a/Source/portable/IAR/AtmelSAM7S64/lib_AT91SAM7X128.h b/Source/portable/IAR/AtmelSAM7S64/lib_AT91SAM7X128.h index 26afc9411..61fbb1f79 100644 --- a/Source/portable/IAR/AtmelSAM7S64/lib_AT91SAM7X128.h +++ b/Source/portable/IAR/AtmelSAM7S64/lib_AT91SAM7X128.h @@ -1,1469 +1,1396 @@ -//* ---------------------------------------------------------------------------- -//* ATMEL Microcontroller Software Support - ROUSSET - -//* ---------------------------------------------------------------------------- -//* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR -//* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF -//* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE -//* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, -//* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -//* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, -//* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF -//* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING -//* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, -//* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -//* ---------------------------------------------------------------------------- -//* File Name : lib_AT91SAM7X128.h -//* Object : AT91SAM7X128 inlined functions -//* Generated : AT91 SW Application Group 05/20/2005 (16:22:23) -//* -//* CVS Reference : /lib_dbgu.h/1.1/Fri Jan 31 12:18:40 2003// -//* CVS Reference : /lib_pmc_SAM7X.h/1.1/Tue Feb 1 08:32:10 2005// -//* CVS Reference : /lib_VREG_6085B.h/1.1/Tue Feb 1 16:20:47 2005// -//* CVS Reference : /lib_rstc_6098A.h/1.1/Wed Oct 6 10:39:20 2004// -//* CVS Reference : /lib_ssc.h/1.4/Fri Jan 31 12:19:20 2003// -//* CVS Reference : /lib_wdtc_6080A.h/1.1/Wed Oct 6 10:38:30 2004// -//* CVS Reference : /lib_usart.h/1.5/Thu Nov 21 16:01:54 2002// -//* CVS Reference : /lib_spi2.h/1.1/Mon Aug 25 14:23:52 2003// -//* CVS Reference : /lib_pitc_6079A.h/1.2/Tue Nov 9 14:43:56 2004// -//* CVS Reference : /lib_aic_6075b.h/1.1/Fri May 20 14:01:19 2005// -//* CVS Reference : /lib_aes_6149a.h/1.1/Mon Jan 17 07:43:09 2005// -//* CVS Reference : /lib_twi.h/1.3/Mon Jul 19 14:27:58 2004// -//* CVS Reference : /lib_adc.h/1.6/Fri Oct 17 09:12:38 2003// -//* CVS Reference : /lib_rttc_6081A.h/1.1/Wed Oct 6 10:39:38 2004// -//* CVS Reference : /lib_udp.h/1.4/Wed Feb 16 08:39:34 2005// -//* CVS Reference : /lib_des3_6150a.h/1.1/Mon Jan 17 09:19:19 2005// -//* CVS Reference : /lib_tc_1753b.h/1.1/Fri Jan 31 12:20:02 2003// -//* CVS Reference : /lib_MC_SAM7X.h/1.1/Thu Mar 25 15:19:14 2004// -//* CVS Reference : /lib_pio.h/1.3/Fri Jan 31 12:18:56 2003// -//* CVS Reference : /lib_can_AT91.h/1.4/Fri Oct 17 09:12:50 2003// -//* CVS Reference : /lib_PWM_SAM.h/1.3/Thu Jan 22 10:10:50 2004// -//* CVS Reference : /lib_pdc.h/1.2/Tue Jul 2 13:29:40 2002// -//* ---------------------------------------------------------------------------- +/** ---------------------------------------------------------------------------- */ +/** ATMEL Microcontroller Software Support - ROUSSET - */ +/** ---------------------------------------------------------------------------- */ +/** DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/** IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/** MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/** DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/** INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/** LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/** OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/** LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/** NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/** EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/** ---------------------------------------------------------------------------- */ +/** File Name : lib_AT91SAM7X128.h */ +/** Object : AT91SAM7X128 inlined functions */ +/** Generated : AT91 SW Application Group 05/20/2005 (16:22:23) */ +/** */ +/** CVS Reference : /lib_dbgu.h/1.1/Fri Jan 31 12:18:40 2003// */ +/** CVS Reference : /lib_pmc_SAM7X.h/1.1/Tue Feb 1 08:32:10 2005// */ +/** CVS Reference : /lib_VREG_6085B.h/1.1/Tue Feb 1 16:20:47 2005// */ +/** CVS Reference : /lib_rstc_6098A.h/1.1/Wed Oct 6 10:39:20 2004// */ +/** CVS Reference : /lib_ssc.h/1.4/Fri Jan 31 12:19:20 2003// */ +/** CVS Reference : /lib_wdtc_6080A.h/1.1/Wed Oct 6 10:38:30 2004// */ +/** CVS Reference : /lib_usart.h/1.5/Thu Nov 21 16:01:54 2002// */ +/** CVS Reference : /lib_spi2.h/1.1/Mon Aug 25 14:23:52 2003// */ +/** CVS Reference : /lib_pitc_6079A.h/1.2/Tue Nov 9 14:43:56 2004// */ +/** CVS Reference : /lib_aic_6075b.h/1.1/Fri May 20 14:01:19 2005// */ +/** CVS Reference : /lib_aes_6149a.h/1.1/Mon Jan 17 07:43:09 2005// */ +/** CVS Reference : /lib_twi.h/1.3/Mon Jul 19 14:27:58 2004// */ +/** CVS Reference : /lib_adc.h/1.6/Fri Oct 17 09:12:38 2003// */ +/** CVS Reference : /lib_rttc_6081A.h/1.1/Wed Oct 6 10:39:38 2004// */ +/** CVS Reference : /lib_udp.h/1.4/Wed Feb 16 08:39:34 2005// */ +/** CVS Reference : /lib_des3_6150a.h/1.1/Mon Jan 17 09:19:19 2005// */ +/** CVS Reference : /lib_tc_1753b.h/1.1/Fri Jan 31 12:20:02 2003// */ +/** CVS Reference : /lib_MC_SAM7X.h/1.1/Thu Mar 25 15:19:14 2004// */ +/** CVS Reference : /lib_pio.h/1.3/Fri Jan 31 12:18:56 2003// */ +/** CVS Reference : /lib_can_AT91.h/1.4/Fri Oct 17 09:12:50 2003// */ +/** CVS Reference : /lib_PWM_SAM.h/1.3/Thu Jan 22 10:10:50 2004// */ +/** CVS Reference : /lib_pdc.h/1.2/Tue Jul 2 13:29:40 2002// */ +/** ---------------------------------------------------------------------------- */ #ifndef lib_AT91SAM7X128_H -#define lib_AT91SAM7X128_H + #define lib_AT91SAM7X128_H /* ***************************************************************************** - SOFTWARE API FOR AIC - ***************************************************************************** */ -#define AT91C_AIC_BRANCH_OPCODE ((void (*) ()) 0xE51FFF20) // ldr, pc, [pc, #-&F20] - -//*---------------------------------------------------------------------------- -//* \fn AT91F_AIC_ConfigureIt -//* \brief Interrupt Handler Initialization -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_AIC_ConfigureIt ( - AT91PS_AIC pAic, // \arg pointer to the AIC registers - unsigned int irq_id, // \arg interrupt number to initialize - unsigned int priority, // \arg priority to give to the interrupt - unsigned int src_type, // \arg activation and sense of activation - void (*newHandler) (void) ) // \arg address of the interrupt handler -{ - unsigned int oldHandler; - unsigned int mask ; - - oldHandler = pAic->AIC_SVR[irq_id]; - - mask = 0x1 << irq_id ; - //* Disable the interrupt on the interrupt controller - pAic->AIC_IDCR = mask ; - //* Save the interrupt handler routine pointer and the interrupt priority - pAic->AIC_SVR[irq_id] = (unsigned int) newHandler ; - //* Store the Source Mode Register - pAic->AIC_SMR[irq_id] = src_type | priority ; - //* Clear the interrupt on the interrupt controller - pAic->AIC_ICCR = mask ; - - return oldHandler; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_AIC_EnableIt -//* \brief Enable corresponding IT number -//*---------------------------------------------------------------------------- -__inline void AT91F_AIC_EnableIt ( - AT91PS_AIC pAic, // \arg pointer to the AIC registers - unsigned int irq_id ) // \arg interrupt number to initialize -{ - //* Enable the interrupt on the interrupt controller - pAic->AIC_IECR = 0x1 << irq_id ; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_AIC_DisableIt -//* \brief Disable corresponding IT number -//*---------------------------------------------------------------------------- -__inline void AT91F_AIC_DisableIt ( - AT91PS_AIC pAic, // \arg pointer to the AIC registers - unsigned int irq_id ) // \arg interrupt number to initialize -{ - unsigned int mask = 0x1 << irq_id; - //* Disable the interrupt on the interrupt controller - pAic->AIC_IDCR = mask ; - //* Clear the interrupt on the Interrupt Controller ( if one is pending ) - pAic->AIC_ICCR = mask ; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_AIC_ClearIt -//* \brief Clear corresponding IT number -//*---------------------------------------------------------------------------- -__inline void AT91F_AIC_ClearIt ( - AT91PS_AIC pAic, // \arg pointer to the AIC registers - unsigned int irq_id) // \arg interrupt number to initialize -{ - //* Clear the interrupt on the Interrupt Controller ( if one is pending ) - pAic->AIC_ICCR = (0x1 << irq_id); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_AIC_AcknowledgeIt -//* \brief Acknowledge corresponding IT number -//*---------------------------------------------------------------------------- -__inline void AT91F_AIC_AcknowledgeIt ( - AT91PS_AIC pAic) // \arg pointer to the AIC registers -{ - pAic->AIC_EOICR = pAic->AIC_EOICR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_AIC_SetExceptionVector -//* \brief Configure vector handler -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_AIC_SetExceptionVector ( - unsigned int *pVector, // \arg pointer to the AIC registers - void (*Handler) () ) // \arg Interrupt Handler -{ - unsigned int oldVector = *pVector; - - if ((unsigned int) Handler == (unsigned int) AT91C_AIC_BRANCH_OPCODE) - *pVector = (unsigned int) AT91C_AIC_BRANCH_OPCODE; - else - *pVector = (((((unsigned int) Handler) - ((unsigned int) pVector) - 0x8) >> 2) & 0x00FFFFFF) | 0xEA000000; - - return oldVector; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_AIC_Trig -//* \brief Trig an IT -//*---------------------------------------------------------------------------- -__inline void AT91F_AIC_Trig ( - AT91PS_AIC pAic, // \arg pointer to the AIC registers - unsigned int irq_id) // \arg interrupt number -{ - pAic->AIC_ISCR = (0x1 << irq_id) ; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_AIC_IsActive -//* \brief Test if an IT is active -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_AIC_IsActive ( - AT91PS_AIC pAic, // \arg pointer to the AIC registers - unsigned int irq_id) // \arg Interrupt Number -{ - return (pAic->AIC_ISR & (0x1 << irq_id)); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_AIC_IsPending -//* \brief Test if an IT is pending -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_AIC_IsPending ( - AT91PS_AIC pAic, // \arg pointer to the AIC registers - unsigned int irq_id) // \arg Interrupt Number -{ - return (pAic->AIC_IPR & (0x1 << irq_id)); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_AIC_Open -//* \brief Set exception vectors and AIC registers to default values -//*---------------------------------------------------------------------------- -__inline void AT91F_AIC_Open( - AT91PS_AIC pAic, // \arg pointer to the AIC registers - void (*IrqHandler) (), // \arg Default IRQ vector exception - void (*FiqHandler) (), // \arg Default FIQ vector exception - void (*DefaultHandler) (), // \arg Default Handler set in ISR - void (*SpuriousHandler) (), // \arg Default Spurious Handler - unsigned int protectMode) // \arg Debug Control Register -{ - int i; - - // Disable all interrupts and set IVR to the default handler - for (i = 0; i < 32; ++i) { - AT91F_AIC_DisableIt(pAic, i); - AT91F_AIC_ConfigureIt(pAic, i, AT91C_AIC_PRIOR_LOWEST, AT91C_AIC_SRCTYPE_HIGH_LEVEL, DefaultHandler); - } - - // Set the IRQ exception vector - AT91F_AIC_SetExceptionVector((unsigned int *) 0x18, IrqHandler); - // Set the Fast Interrupt exception vector - AT91F_AIC_SetExceptionVector((unsigned int *) 0x1C, FiqHandler); - - pAic->AIC_SPU = (unsigned int) SpuriousHandler; - pAic->AIC_DCR = protectMode; -} +* SOFTWARE API FOR AIC +***************************************************************************** */ + #define AT91C_AIC_BRANCH_OPCODE ( ( void ( * )() ) 0xE51FFF20 ) /* ldr, pc, [pc, #-&F20] */ + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_AIC_ConfigureIt */ +/** \brief Interrupt Handler Initialization */ +/**---------------------------------------------------------------------------- */ + __inline unsigned int AT91F_AIC_ConfigureIt( AT91PS_AIC pAic, /* \arg pointer to the AIC registers */ + unsigned int irq_id, /* \arg interrupt number to initialize */ + unsigned int priority, /* \arg priority to give to the interrupt */ + unsigned int src_type, /* \arg activation and sense of activation */ + void ( * newHandler )( void ) ) /* \arg address of the interrupt handler */ + { + unsigned int oldHandler; + unsigned int mask; + + oldHandler = pAic->AIC_SVR[ irq_id ]; + + mask = 0x1 << irq_id; + /** Disable the interrupt on the interrupt controller */ + pAic->AIC_IDCR = mask; + /** Save the interrupt handler routine pointer and the interrupt priority */ + pAic->AIC_SVR[ irq_id ] = ( unsigned int ) newHandler; + /** Store the Source Mode Register */ + pAic->AIC_SMR[ irq_id ] = src_type | priority; + /** Clear the interrupt on the interrupt controller */ + pAic->AIC_ICCR = mask; + + return oldHandler; + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_AIC_EnableIt */ +/** \brief Enable corresponding IT number */ +/**---------------------------------------------------------------------------- */ + __inline void AT91F_AIC_EnableIt( AT91PS_AIC pAic, /* \arg pointer to the AIC registers */ + unsigned int irq_id ) /* \arg interrupt number to initialize */ + { + /** Enable the interrupt on the interrupt controller */ + pAic->AIC_IECR = 0x1 << irq_id; + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_AIC_DisableIt */ +/** \brief Disable corresponding IT number */ +/**---------------------------------------------------------------------------- */ + __inline void AT91F_AIC_DisableIt( AT91PS_AIC pAic, /* \arg pointer to the AIC registers */ + unsigned int irq_id ) /* \arg interrupt number to initialize */ + { + unsigned int mask = 0x1 << irq_id; + + /** Disable the interrupt on the interrupt controller */ + pAic->AIC_IDCR = mask; + /** Clear the interrupt on the Interrupt Controller ( if one is pending ) */ + pAic->AIC_ICCR = mask; + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_AIC_ClearIt */ +/** \brief Clear corresponding IT number */ +/**---------------------------------------------------------------------------- */ + __inline void AT91F_AIC_ClearIt( AT91PS_AIC pAic, /* \arg pointer to the AIC registers */ + unsigned int irq_id ) /* \arg interrupt number to initialize */ + { + /** Clear the interrupt on the Interrupt Controller ( if one is pending ) */ + pAic->AIC_ICCR = ( 0x1 << irq_id ); + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_AIC_AcknowledgeIt */ +/** \brief Acknowledge corresponding IT number */ +/**---------------------------------------------------------------------------- */ + __inline void AT91F_AIC_AcknowledgeIt( AT91PS_AIC pAic ) /* \arg pointer to the AIC registers */ + { + pAic->AIC_EOICR = pAic->AIC_EOICR; + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_AIC_SetExceptionVector */ +/** \brief Configure vector handler */ +/**---------------------------------------------------------------------------- */ + __inline unsigned int AT91F_AIC_SetExceptionVector( unsigned int * pVector, /* \arg pointer to the AIC registers */ + void ( * Handler )() ) /* \arg Interrupt Handler */ + { + unsigned int oldVector = *pVector; + + if( ( unsigned int ) Handler == ( unsigned int ) AT91C_AIC_BRANCH_OPCODE ) + { + *pVector = ( unsigned int ) AT91C_AIC_BRANCH_OPCODE; + } + else + { + *pVector = ( ( ( ( ( unsigned int ) Handler ) - ( ( unsigned int ) pVector ) - 0x8 ) >> 2 ) & 0x00FFFFFF ) | 0xEA000000; + } + + return oldVector; + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_AIC_Trig */ +/** \brief Trig an IT */ +/**---------------------------------------------------------------------------- */ + __inline void AT91F_AIC_Trig( AT91PS_AIC pAic, /* \arg pointer to the AIC registers */ + unsigned int irq_id ) /* \arg interrupt number */ + { + pAic->AIC_ISCR = ( 0x1 << irq_id ); + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_AIC_IsActive */ +/** \brief Test if an IT is active */ +/**---------------------------------------------------------------------------- */ + __inline unsigned int AT91F_AIC_IsActive( AT91PS_AIC pAic, /* \arg pointer to the AIC registers */ + unsigned int irq_id ) /* \arg Interrupt Number */ + { + return( pAic->AIC_ISR & ( 0x1 << irq_id ) ); + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_AIC_IsPending */ +/** \brief Test if an IT is pending */ +/**---------------------------------------------------------------------------- */ + __inline unsigned int AT91F_AIC_IsPending( AT91PS_AIC pAic, /* \arg pointer to the AIC registers */ + unsigned int irq_id ) /* \arg Interrupt Number */ + { + return( pAic->AIC_IPR & ( 0x1 << irq_id ) ); + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_AIC_Open */ +/** \brief Set exception vectors and AIC registers to default values */ +/**---------------------------------------------------------------------------- */ + __inline void AT91F_AIC_Open( AT91PS_AIC pAic, /* \arg pointer to the AIC registers */ + void ( * IrqHandler )(), /* \arg Default IRQ vector exception */ + void ( * FiqHandler )(), /* \arg Default FIQ vector exception */ + void ( * DefaultHandler )(), /* \arg Default Handler set in ISR */ + void ( * SpuriousHandler )(), /* \arg Default Spurious Handler */ + unsigned int protectMode ) /* \arg Debug Control Register */ + { + int i; + + /* Disable all interrupts and set IVR to the default handler */ + for( i = 0; i < 32; ++i ) + { + AT91F_AIC_DisableIt( pAic, i ); + AT91F_AIC_ConfigureIt( pAic, i, AT91C_AIC_PRIOR_LOWEST, AT91C_AIC_SRCTYPE_HIGH_LEVEL, DefaultHandler ); + } + + /* Set the IRQ exception vector */ + AT91F_AIC_SetExceptionVector( ( unsigned int * ) 0x18, IrqHandler ); + /* Set the Fast Interrupt exception vector */ + AT91F_AIC_SetExceptionVector( ( unsigned int * ) 0x1C, FiqHandler ); + + pAic->AIC_SPU = ( unsigned int ) SpuriousHandler; + pAic->AIC_DCR = protectMode; + } + /* ***************************************************************************** - SOFTWARE API FOR PDC - ***************************************************************************** */ -//*---------------------------------------------------------------------------- -//* \fn AT91F_PDC_SetNextRx -//* \brief Set the next receive transfer descriptor -//*---------------------------------------------------------------------------- -__inline void AT91F_PDC_SetNextRx ( - AT91PS_PDC pPDC, // \arg pointer to a PDC controller - char *address, // \arg address to the next bloc to be received - unsigned int bytes) // \arg number of bytes to be received -{ - pPDC->PDC_RNPR = (unsigned int) address; - pPDC->PDC_RNCR = bytes; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PDC_SetNextTx -//* \brief Set the next transmit transfer descriptor -//*---------------------------------------------------------------------------- -__inline void AT91F_PDC_SetNextTx ( - AT91PS_PDC pPDC, // \arg pointer to a PDC controller - char *address, // \arg address to the next bloc to be transmitted - unsigned int bytes) // \arg number of bytes to be transmitted -{ - pPDC->PDC_TNPR = (unsigned int) address; - pPDC->PDC_TNCR = bytes; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PDC_SetRx -//* \brief Set the receive transfer descriptor -//*---------------------------------------------------------------------------- -__inline void AT91F_PDC_SetRx ( - AT91PS_PDC pPDC, // \arg pointer to a PDC controller - char *address, // \arg address to the next bloc to be received - unsigned int bytes) // \arg number of bytes to be received -{ - pPDC->PDC_RPR = (unsigned int) address; - pPDC->PDC_RCR = bytes; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PDC_SetTx -//* \brief Set the transmit transfer descriptor -//*---------------------------------------------------------------------------- -__inline void AT91F_PDC_SetTx ( - AT91PS_PDC pPDC, // \arg pointer to a PDC controller - char *address, // \arg address to the next bloc to be transmitted - unsigned int bytes) // \arg number of bytes to be transmitted -{ - pPDC->PDC_TPR = (unsigned int) address; - pPDC->PDC_TCR = bytes; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PDC_EnableTx -//* \brief Enable transmit -//*---------------------------------------------------------------------------- -__inline void AT91F_PDC_EnableTx ( - AT91PS_PDC pPDC ) // \arg pointer to a PDC controller -{ - pPDC->PDC_PTCR = AT91C_PDC_TXTEN; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PDC_EnableRx -//* \brief Enable receive -//*---------------------------------------------------------------------------- -__inline void AT91F_PDC_EnableRx ( - AT91PS_PDC pPDC ) // \arg pointer to a PDC controller -{ - pPDC->PDC_PTCR = AT91C_PDC_RXTEN; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PDC_DisableTx -//* \brief Disable transmit -//*---------------------------------------------------------------------------- -__inline void AT91F_PDC_DisableTx ( - AT91PS_PDC pPDC ) // \arg pointer to a PDC controller -{ - pPDC->PDC_PTCR = AT91C_PDC_TXTDIS; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PDC_DisableRx -//* \brief Disable receive -//*---------------------------------------------------------------------------- -__inline void AT91F_PDC_DisableRx ( - AT91PS_PDC pPDC ) // \arg pointer to a PDC controller -{ - pPDC->PDC_PTCR = AT91C_PDC_RXTDIS; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PDC_IsTxEmpty -//* \brief Test if the current transfer descriptor has been sent -//*---------------------------------------------------------------------------- -__inline int AT91F_PDC_IsTxEmpty ( // \return return 1 if transfer is complete - AT91PS_PDC pPDC ) // \arg pointer to a PDC controller -{ - return !(pPDC->PDC_TCR); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PDC_IsNextTxEmpty -//* \brief Test if the next transfer descriptor has been moved to the current td -//*---------------------------------------------------------------------------- -__inline int AT91F_PDC_IsNextTxEmpty ( // \return return 1 if transfer is complete - AT91PS_PDC pPDC ) // \arg pointer to a PDC controller -{ - return !(pPDC->PDC_TNCR); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PDC_IsRxEmpty -//* \brief Test if the current transfer descriptor has been filled -//*---------------------------------------------------------------------------- -__inline int AT91F_PDC_IsRxEmpty ( // \return return 1 if transfer is complete - AT91PS_PDC pPDC ) // \arg pointer to a PDC controller -{ - return !(pPDC->PDC_RCR); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PDC_IsNextRxEmpty -//* \brief Test if the next transfer descriptor has been moved to the current td -//*---------------------------------------------------------------------------- -__inline int AT91F_PDC_IsNextRxEmpty ( // \return return 1 if transfer is complete - AT91PS_PDC pPDC ) // \arg pointer to a PDC controller -{ - return !(pPDC->PDC_RNCR); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PDC_Open -//* \brief Open PDC: disable TX and RX reset transfer descriptors, re-enable RX and TX -//*---------------------------------------------------------------------------- -__inline void AT91F_PDC_Open ( - AT91PS_PDC pPDC) // \arg pointer to a PDC controller -{ - //* Disable the RX and TX PDC transfer requests - AT91F_PDC_DisableRx(pPDC); - AT91F_PDC_DisableTx(pPDC); - - //* Reset all Counter register Next buffer first - AT91F_PDC_SetNextTx(pPDC, (char *) 0, 0); - AT91F_PDC_SetNextRx(pPDC, (char *) 0, 0); - AT91F_PDC_SetTx(pPDC, (char *) 0, 0); - AT91F_PDC_SetRx(pPDC, (char *) 0, 0); - - //* Enable the RX and TX PDC transfer requests - AT91F_PDC_EnableRx(pPDC); - AT91F_PDC_EnableTx(pPDC); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PDC_Close -//* \brief Close PDC: disable TX and RX reset transfer descriptors -//*---------------------------------------------------------------------------- -__inline void AT91F_PDC_Close ( - AT91PS_PDC pPDC) // \arg pointer to a PDC controller -{ - //* Disable the RX and TX PDC transfer requests - AT91F_PDC_DisableRx(pPDC); - AT91F_PDC_DisableTx(pPDC); - - //* Reset all Counter register Next buffer first - AT91F_PDC_SetNextTx(pPDC, (char *) 0, 0); - AT91F_PDC_SetNextRx(pPDC, (char *) 0, 0); - AT91F_PDC_SetTx(pPDC, (char *) 0, 0); - AT91F_PDC_SetRx(pPDC, (char *) 0, 0); - -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PDC_SendFrame -//* \brief Close PDC: disable TX and RX reset transfer descriptors -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_PDC_SendFrame( - AT91PS_PDC pPDC, - char *pBuffer, - unsigned int szBuffer, - char *pNextBuffer, - unsigned int szNextBuffer ) -{ - if (AT91F_PDC_IsTxEmpty(pPDC)) { - //* Buffer and next buffer can be initialized - AT91F_PDC_SetTx(pPDC, pBuffer, szBuffer); - AT91F_PDC_SetNextTx(pPDC, pNextBuffer, szNextBuffer); - return 2; - } - else if (AT91F_PDC_IsNextTxEmpty(pPDC)) { - //* Only one buffer can be initialized - AT91F_PDC_SetNextTx(pPDC, pBuffer, szBuffer); - return 1; - } - else { - //* All buffer are in use... - return 0; +* SOFTWARE API FOR PDC +***************************************************************************** */ +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PDC_SetNextRx */ +/** \brief Set the next receive transfer descriptor */ +/**---------------------------------------------------------------------------- */ + __inline void AT91F_PDC_SetNextRx( AT91PS_PDC pPDC, /* \arg pointer to a PDC controller */ + char * address, /* \arg address to the next bloc to be received */ + unsigned int bytes ) /* \arg number of bytes to be received */ + { + pPDC->PDC_RNPR = ( unsigned int ) address; + pPDC->PDC_RNCR = bytes; } -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PDC_ReceiveFrame -//* \brief Close PDC: disable TX and RX reset transfer descriptors -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_PDC_ReceiveFrame ( - AT91PS_PDC pPDC, - char *pBuffer, - unsigned int szBuffer, - char *pNextBuffer, - unsigned int szNextBuffer ) -{ - if (AT91F_PDC_IsRxEmpty(pPDC)) { - //* Buffer and next buffer can be initialized - AT91F_PDC_SetRx(pPDC, pBuffer, szBuffer); - AT91F_PDC_SetNextRx(pPDC, pNextBuffer, szNextBuffer); - return 2; - } - else if (AT91F_PDC_IsNextRxEmpty(pPDC)) { - //* Only one buffer can be initialized - AT91F_PDC_SetNextRx(pPDC, pBuffer, szBuffer); - return 1; - } - else { - //* All buffer are in use... - return 0; + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PDC_SetNextTx */ +/** \brief Set the next transmit transfer descriptor */ +/**---------------------------------------------------------------------------- */ + __inline void AT91F_PDC_SetNextTx( AT91PS_PDC pPDC, /* \arg pointer to a PDC controller */ + char * address, /* \arg address to the next bloc to be transmitted */ + unsigned int bytes ) /* \arg number of bytes to be transmitted */ + { + pPDC->PDC_TNPR = ( unsigned int ) address; + pPDC->PDC_TNCR = bytes; + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PDC_SetRx */ +/** \brief Set the receive transfer descriptor */ +/**---------------------------------------------------------------------------- */ + __inline void AT91F_PDC_SetRx( AT91PS_PDC pPDC, /* \arg pointer to a PDC controller */ + char * address, /* \arg address to the next bloc to be received */ + unsigned int bytes ) /* \arg number of bytes to be received */ + { + pPDC->PDC_RPR = ( unsigned int ) address; + pPDC->PDC_RCR = bytes; + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PDC_SetTx */ +/** \brief Set the transmit transfer descriptor */ +/**---------------------------------------------------------------------------- */ + __inline void AT91F_PDC_SetTx( AT91PS_PDC pPDC, /* \arg pointer to a PDC controller */ + char * address, /* \arg address to the next bloc to be transmitted */ + unsigned int bytes ) /* \arg number of bytes to be transmitted */ + { + pPDC->PDC_TPR = ( unsigned int ) address; + pPDC->PDC_TCR = bytes; + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PDC_EnableTx */ +/** \brief Enable transmit */ +/**---------------------------------------------------------------------------- */ + __inline void AT91F_PDC_EnableTx( AT91PS_PDC pPDC ) /* \arg pointer to a PDC controller */ + { + pPDC->PDC_PTCR = AT91C_PDC_TXTEN; } -} + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PDC_EnableRx */ +/** \brief Enable receive */ +/**---------------------------------------------------------------------------- */ + __inline void AT91F_PDC_EnableRx( AT91PS_PDC pPDC ) /* \arg pointer to a PDC controller */ + { + pPDC->PDC_PTCR = AT91C_PDC_RXTEN; + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PDC_DisableTx */ +/** \brief Disable transmit */ +/**---------------------------------------------------------------------------- */ + __inline void AT91F_PDC_DisableTx( AT91PS_PDC pPDC ) /* \arg pointer to a PDC controller */ + { + pPDC->PDC_PTCR = AT91C_PDC_TXTDIS; + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PDC_DisableRx */ +/** \brief Disable receive */ +/**---------------------------------------------------------------------------- */ + __inline void AT91F_PDC_DisableRx( AT91PS_PDC pPDC ) /* \arg pointer to a PDC controller */ + { + pPDC->PDC_PTCR = AT91C_PDC_RXTDIS; + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PDC_IsTxEmpty */ +/** \brief Test if the current transfer descriptor has been sent */ +/**---------------------------------------------------------------------------- */ + __inline int AT91F_PDC_IsTxEmpty( /* \return return 1 if transfer is complete */ + AT91PS_PDC pPDC ) /* \arg pointer to a PDC controller */ + { + return !( pPDC->PDC_TCR ); + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PDC_IsNextTxEmpty */ +/** \brief Test if the next transfer descriptor has been moved to the current td */ +/**---------------------------------------------------------------------------- */ + __inline int AT91F_PDC_IsNextTxEmpty( /* \return return 1 if transfer is complete */ + AT91PS_PDC pPDC ) /* \arg pointer to a PDC controller */ + { + return !( pPDC->PDC_TNCR ); + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PDC_IsRxEmpty */ +/** \brief Test if the current transfer descriptor has been filled */ +/**---------------------------------------------------------------------------- */ + __inline int AT91F_PDC_IsRxEmpty( /* \return return 1 if transfer is complete */ + AT91PS_PDC pPDC ) /* \arg pointer to a PDC controller */ + { + return !( pPDC->PDC_RCR ); + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PDC_IsNextRxEmpty */ +/** \brief Test if the next transfer descriptor has been moved to the current td */ +/**---------------------------------------------------------------------------- */ + __inline int AT91F_PDC_IsNextRxEmpty( /* \return return 1 if transfer is complete */ + AT91PS_PDC pPDC ) /* \arg pointer to a PDC controller */ + { + return !( pPDC->PDC_RNCR ); + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PDC_Open */ +/** \brief Open PDC: disable TX and RX reset transfer descriptors, re-enable RX and TX */ +/**---------------------------------------------------------------------------- */ + __inline void AT91F_PDC_Open( AT91PS_PDC pPDC ) /* \arg pointer to a PDC controller */ + { + /** Disable the RX and TX PDC transfer requests */ + AT91F_PDC_DisableRx( pPDC ); + AT91F_PDC_DisableTx( pPDC ); + + /** Reset all Counter register Next buffer first */ + AT91F_PDC_SetNextTx( pPDC, ( char * ) 0, 0 ); + AT91F_PDC_SetNextRx( pPDC, ( char * ) 0, 0 ); + AT91F_PDC_SetTx( pPDC, ( char * ) 0, 0 ); + AT91F_PDC_SetRx( pPDC, ( char * ) 0, 0 ); + + /** Enable the RX and TX PDC transfer requests */ + AT91F_PDC_EnableRx( pPDC ); + AT91F_PDC_EnableTx( pPDC ); + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PDC_Close */ +/** \brief Close PDC: disable TX and RX reset transfer descriptors */ +/**---------------------------------------------------------------------------- */ + __inline void AT91F_PDC_Close( AT91PS_PDC pPDC ) /* \arg pointer to a PDC controller */ + { + /** Disable the RX and TX PDC transfer requests */ + AT91F_PDC_DisableRx( pPDC ); + AT91F_PDC_DisableTx( pPDC ); + + /** Reset all Counter register Next buffer first */ + AT91F_PDC_SetNextTx( pPDC, ( char * ) 0, 0 ); + AT91F_PDC_SetNextRx( pPDC, ( char * ) 0, 0 ); + AT91F_PDC_SetTx( pPDC, ( char * ) 0, 0 ); + AT91F_PDC_SetRx( pPDC, ( char * ) 0, 0 ); + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PDC_SendFrame */ +/** \brief Close PDC: disable TX and RX reset transfer descriptors */ +/**---------------------------------------------------------------------------- */ + __inline unsigned int AT91F_PDC_SendFrame( AT91PS_PDC pPDC, + char * pBuffer, + unsigned int szBuffer, + char * pNextBuffer, + unsigned int szNextBuffer ) + { + if( AT91F_PDC_IsTxEmpty( pPDC ) ) + { + /** Buffer and next buffer can be initialized */ + AT91F_PDC_SetTx( pPDC, pBuffer, szBuffer ); + AT91F_PDC_SetNextTx( pPDC, pNextBuffer, szNextBuffer ); + return 2; + } + else if( AT91F_PDC_IsNextTxEmpty( pPDC ) ) + { + /** Only one buffer can be initialized */ + AT91F_PDC_SetNextTx( pPDC, pBuffer, szBuffer ); + return 1; + } + else + { + /** All buffer are in use... */ + return 0; + } + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PDC_ReceiveFrame */ +/** \brief Close PDC: disable TX and RX reset transfer descriptors */ +/**---------------------------------------------------------------------------- */ + __inline unsigned int AT91F_PDC_ReceiveFrame( AT91PS_PDC pPDC, + char * pBuffer, + unsigned int szBuffer, + char * pNextBuffer, + unsigned int szNextBuffer ) + { + if( AT91F_PDC_IsRxEmpty( pPDC ) ) + { + /** Buffer and next buffer can be initialized */ + AT91F_PDC_SetRx( pPDC, pBuffer, szBuffer ); + AT91F_PDC_SetNextRx( pPDC, pNextBuffer, szNextBuffer ); + return 2; + } + else if( AT91F_PDC_IsNextRxEmpty( pPDC ) ) + { + /** Only one buffer can be initialized */ + AT91F_PDC_SetNextRx( pPDC, pBuffer, szBuffer ); + return 1; + } + else + { + /** All buffer are in use... */ + return 0; + } + } + /* ***************************************************************************** - SOFTWARE API FOR DBGU - ***************************************************************************** */ -//*---------------------------------------------------------------------------- -//* \fn AT91F_DBGU_InterruptEnable -//* \brief Enable DBGU Interrupt -//*---------------------------------------------------------------------------- -__inline void AT91F_DBGU_InterruptEnable( - AT91PS_DBGU pDbgu, // \arg pointer to a DBGU controller - unsigned int flag) // \arg dbgu interrupt to be enabled -{ +* SOFTWARE API FOR DBGU +***************************************************************************** */ +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_DBGU_InterruptEnable */ +/** \brief Enable DBGU Interrupt */ +/**---------------------------------------------------------------------------- */ + __inline void AT91F_DBGU_InterruptEnable( AT91PS_DBGU pDbgu, /* \arg pointer to a DBGU controller */ + unsigned int flag ) /* \arg dbgu interrupt to be enabled */ + { pDbgu->DBGU_IER = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_DBGU_InterruptDisable -//* \brief Disable DBGU Interrupt -//*---------------------------------------------------------------------------- -__inline void AT91F_DBGU_InterruptDisable( - AT91PS_DBGU pDbgu, // \arg pointer to a DBGU controller - unsigned int flag) // \arg dbgu interrupt to be disabled -{ + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_DBGU_InterruptDisable */ +/** \brief Disable DBGU Interrupt */ +/**---------------------------------------------------------------------------- */ + __inline void AT91F_DBGU_InterruptDisable( AT91PS_DBGU pDbgu, /* \arg pointer to a DBGU controller */ + unsigned int flag ) /* \arg dbgu interrupt to be disabled */ + { pDbgu->DBGU_IDR = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_DBGU_GetInterruptMaskStatus -//* \brief Return DBGU Interrupt Mask Status -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_DBGU_GetInterruptMaskStatus( // \return DBGU Interrupt Mask Status - AT91PS_DBGU pDbgu) // \arg pointer to a DBGU controller -{ + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_DBGU_GetInterruptMaskStatus */ +/** \brief Return DBGU Interrupt Mask Status */ +/**---------------------------------------------------------------------------- */ + __inline unsigned int AT91F_DBGU_GetInterruptMaskStatus( /* \return DBGU Interrupt Mask Status */ + AT91PS_DBGU pDbgu ) /* \arg pointer to a DBGU controller */ + { return pDbgu->DBGU_IMR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_DBGU_IsInterruptMasked -//* \brief Test if DBGU Interrupt is Masked -//*---------------------------------------------------------------------------- -__inline int AT91F_DBGU_IsInterruptMasked( - AT91PS_DBGU pDbgu, // \arg pointer to a DBGU controller - unsigned int flag) // \arg flag to be tested -{ - return (AT91F_DBGU_GetInterruptMaskStatus(pDbgu) & flag); -} + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_DBGU_IsInterruptMasked */ +/** \brief Test if DBGU Interrupt is Masked */ +/**---------------------------------------------------------------------------- */ + __inline int AT91F_DBGU_IsInterruptMasked( AT91PS_DBGU pDbgu, /* \arg pointer to a DBGU controller */ + unsigned int flag ) /* \arg flag to be tested */ + { + return( AT91F_DBGU_GetInterruptMaskStatus( pDbgu ) & flag ); + } /* ***************************************************************************** - SOFTWARE API FOR PIO - ***************************************************************************** */ -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_CfgPeriph -//* \brief Enable pins to be drived by peripheral -//*---------------------------------------------------------------------------- -__inline void AT91F_PIO_CfgPeriph( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int periphAEnable, // \arg PERIPH A to enable - unsigned int periphBEnable) // \arg PERIPH B to enable - -{ - pPio->PIO_ASR = periphAEnable; - pPio->PIO_BSR = periphBEnable; - pPio->PIO_PDR = (periphAEnable | periphBEnable); // Set in Periph mode -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_CfgOutput -//* \brief Enable PIO in output mode -//*---------------------------------------------------------------------------- -__inline void AT91F_PIO_CfgOutput( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int pioEnable) // \arg PIO to be enabled -{ - pPio->PIO_PER = pioEnable; // Set in PIO mode - pPio->PIO_OER = pioEnable; // Configure in Output -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_CfgInput -//* \brief Enable PIO in input mode -//*---------------------------------------------------------------------------- -__inline void AT91F_PIO_CfgInput( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int inputEnable) // \arg PIO to be enabled -{ - // Disable output - pPio->PIO_ODR = inputEnable; - pPio->PIO_PER = inputEnable; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_CfgOpendrain -//* \brief Configure PIO in open drain -//*---------------------------------------------------------------------------- -__inline void AT91F_PIO_CfgOpendrain( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int multiDrvEnable) // \arg pio to be configured in open drain -{ - // Configure the multi-drive option - pPio->PIO_MDDR = ~multiDrvEnable; - pPio->PIO_MDER = multiDrvEnable; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_CfgPullup -//* \brief Enable pullup on PIO -//*---------------------------------------------------------------------------- -__inline void AT91F_PIO_CfgPullup( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int pullupEnable) // \arg enable pullup on PIO -{ - // Connect or not Pullup - pPio->PIO_PPUDR = ~pullupEnable; - pPio->PIO_PPUER = pullupEnable; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_CfgDirectDrive -//* \brief Enable direct drive on PIO -//*---------------------------------------------------------------------------- -__inline void AT91F_PIO_CfgDirectDrive( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int directDrive) // \arg PIO to be configured with direct drive - -{ - // Configure the Direct Drive - pPio->PIO_OWDR = ~directDrive; - pPio->PIO_OWER = directDrive; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_CfgInputFilter -//* \brief Enable input filter on input PIO -//*---------------------------------------------------------------------------- -__inline void AT91F_PIO_CfgInputFilter( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int inputFilter) // \arg PIO to be configured with input filter - -{ - // Configure the Direct Drive - pPio->PIO_IFDR = ~inputFilter; - pPio->PIO_IFER = inputFilter; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_GetInput -//* \brief Return PIO input value -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_PIO_GetInput( // \return PIO input - AT91PS_PIO pPio) // \arg pointer to a PIO controller -{ - return pPio->PIO_PDSR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_IsInputSet -//* \brief Test if PIO is input flag is active -//*---------------------------------------------------------------------------- -__inline int AT91F_PIO_IsInputSet( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag) // \arg flag to be tested -{ - return (AT91F_PIO_GetInput(pPio) & flag); -} - - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_SetOutput -//* \brief Set to 1 output PIO -//*---------------------------------------------------------------------------- -__inline void AT91F_PIO_SetOutput( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag) // \arg output to be set -{ - pPio->PIO_SODR = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_ClearOutput -//* \brief Set to 0 output PIO -//*---------------------------------------------------------------------------- -__inline void AT91F_PIO_ClearOutput( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag) // \arg output to be cleared -{ - pPio->PIO_CODR = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_ForceOutput -//* \brief Force output when Direct drive option is enabled -//*---------------------------------------------------------------------------- -__inline void AT91F_PIO_ForceOutput( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag) // \arg output to be forced -{ - pPio->PIO_ODSR = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_Enable -//* \brief Enable PIO -//*---------------------------------------------------------------------------- -__inline void AT91F_PIO_Enable( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag) // \arg pio to be enabled -{ +* SOFTWARE API FOR PIO +***************************************************************************** */ +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PIO_CfgPeriph */ +/** \brief Enable pins to be derived by peripheral */ +/**---------------------------------------------------------------------------- */ + __inline void AT91F_PIO_CfgPeriph( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */ + unsigned int periphAEnable, /* \arg PERIPH A to enable */ + unsigned int periphBEnable ) /* \arg PERIPH B to enable */ + + { + pPio->PIO_ASR = periphAEnable; + pPio->PIO_BSR = periphBEnable; + pPio->PIO_PDR = ( periphAEnable | periphBEnable ); /* Set in Periph mode */ + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PIO_CfgOutput */ +/** \brief Enable PIO in output mode */ +/**---------------------------------------------------------------------------- */ + __inline void AT91F_PIO_CfgOutput( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */ + unsigned int pioEnable ) /* \arg PIO to be enabled */ + { + pPio->PIO_PER = pioEnable; /* Set in PIO mode */ + pPio->PIO_OER = pioEnable; /* Configure in Output */ + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PIO_CfgInput */ +/** \brief Enable PIO in input mode */ +/**---------------------------------------------------------------------------- */ + __inline void AT91F_PIO_CfgInput( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */ + unsigned int inputEnable ) /* \arg PIO to be enabled */ + { + /* Disable output */ + pPio->PIO_ODR = inputEnable; + pPio->PIO_PER = inputEnable; + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PIO_CfgOpendrain */ +/** \brief Configure PIO in open drain */ +/**---------------------------------------------------------------------------- */ + __inline void AT91F_PIO_CfgOpendrain( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */ + unsigned int multiDrvEnable ) /* \arg pio to be configured in open drain */ + { + /* Configure the multi-drive option */ + pPio->PIO_MDDR = ~multiDrvEnable; + pPio->PIO_MDER = multiDrvEnable; + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PIO_CfgPullup */ +/** \brief Enable pullup on PIO */ +/**---------------------------------------------------------------------------- */ + __inline void AT91F_PIO_CfgPullup( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */ + unsigned int pullupEnable ) /* \arg enable pullup on PIO */ + { + /* Connect or not Pullup */ + pPio->PIO_PPUDR = ~pullupEnable; + pPio->PIO_PPUER = pullupEnable; + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PIO_CfgDirectDrive */ +/** \brief Enable direct drive on PIO */ +/**---------------------------------------------------------------------------- */ + __inline void AT91F_PIO_CfgDirectDrive( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */ + unsigned int directDrive ) /* \arg PIO to be configured with direct drive */ + + { + /* Configure the Direct Drive */ + pPio->PIO_OWDR = ~directDrive; + pPio->PIO_OWER = directDrive; + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PIO_CfgInputFilter */ +/** \brief Enable input filter on input PIO */ +/**---------------------------------------------------------------------------- */ + __inline void AT91F_PIO_CfgInputFilter( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */ + unsigned int inputFilter ) /* \arg PIO to be configured with input filter */ + + { + /* Configure the Direct Drive */ + pPio->PIO_IFDR = ~inputFilter; + pPio->PIO_IFER = inputFilter; + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PIO_GetInput */ +/** \brief Return PIO input value */ +/**---------------------------------------------------------------------------- */ + __inline unsigned int AT91F_PIO_GetInput( /* \return PIO input */ + AT91PS_PIO pPio ) /* \arg pointer to a PIO controller */ + { + return pPio->PIO_PDSR; + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PIO_IsInputSet */ +/** \brief Test if PIO is input flag is active */ +/**---------------------------------------------------------------------------- */ + __inline int AT91F_PIO_IsInputSet( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */ + unsigned int flag ) /* \arg flag to be tested */ + { + return( AT91F_PIO_GetInput( pPio ) & flag ); + } + + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PIO_SetOutput */ +/** \brief Set to 1 output PIO */ +/**---------------------------------------------------------------------------- */ + __inline void AT91F_PIO_SetOutput( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */ + unsigned int flag ) /* \arg output to be set */ + { + pPio->PIO_SODR = flag; + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PIO_ClearOutput */ +/** \brief Set to 0 output PIO */ +/**---------------------------------------------------------------------------- */ + __inline void AT91F_PIO_ClearOutput( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */ + unsigned int flag ) /* \arg output to be cleared */ + { + pPio->PIO_CODR = flag; + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PIO_ForceOutput */ +/** \brief Force output when Direct drive option is enabled */ +/**---------------------------------------------------------------------------- */ + __inline void AT91F_PIO_ForceOutput( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */ + unsigned int flag ) /* \arg output to be forced */ + { + pPio->PIO_ODSR = flag; + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PIO_Enable */ +/** \brief Enable PIO */ +/**---------------------------------------------------------------------------- */ + __inline void AT91F_PIO_Enable( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */ + unsigned int flag ) /* \arg pio to be enabled */ + { pPio->PIO_PER = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_Disable -//* \brief Disable PIO -//*---------------------------------------------------------------------------- -__inline void AT91F_PIO_Disable( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag) // \arg pio to be disabled -{ + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PIO_Disable */ +/** \brief Disable PIO */ +/**---------------------------------------------------------------------------- */ + __inline void AT91F_PIO_Disable( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */ + unsigned int flag ) /* \arg pio to be disabled */ + { pPio->PIO_PDR = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_GetStatus -//* \brief Return PIO Status -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_PIO_GetStatus( // \return PIO Status - AT91PS_PIO pPio) // \arg pointer to a PIO controller -{ + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PIO_GetStatus */ +/** \brief Return PIO Status */ +/**---------------------------------------------------------------------------- */ + __inline unsigned int AT91F_PIO_GetStatus( /* \return PIO Status */ + AT91PS_PIO pPio ) /* \arg pointer to a PIO controller */ + { return pPio->PIO_PSR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_IsSet -//* \brief Test if PIO is Set -//*---------------------------------------------------------------------------- -__inline int AT91F_PIO_IsSet( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag) // \arg flag to be tested -{ - return (AT91F_PIO_GetStatus(pPio) & flag); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_OutputEnable -//* \brief Output Enable PIO -//*---------------------------------------------------------------------------- -__inline void AT91F_PIO_OutputEnable( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag) // \arg pio output to be enabled -{ + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PIO_IsSet */ +/** \brief Test if PIO is Set */ +/**---------------------------------------------------------------------------- */ + __inline int AT91F_PIO_IsSet( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */ + unsigned int flag ) /* \arg flag to be tested */ + { + return( AT91F_PIO_GetStatus( pPio ) & flag ); + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PIO_OutputEnable */ +/** \brief Output Enable PIO */ +/**---------------------------------------------------------------------------- */ + __inline void AT91F_PIO_OutputEnable( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */ + unsigned int flag ) /* \arg pio output to be enabled */ + { pPio->PIO_OER = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_OutputDisable -//* \brief Output Enable PIO -//*---------------------------------------------------------------------------- -__inline void AT91F_PIO_OutputDisable( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag) // \arg pio output to be disabled -{ + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PIO_OutputDisable */ +/** \brief Output Enable PIO */ +/**---------------------------------------------------------------------------- */ + __inline void AT91F_PIO_OutputDisable( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */ + unsigned int flag ) /* \arg pio output to be disabled */ + { pPio->PIO_ODR = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_GetOutputStatus -//* \brief Return PIO Output Status -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_PIO_GetOutputStatus( // \return PIO Output Status - AT91PS_PIO pPio) // \arg pointer to a PIO controller -{ + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PIO_GetOutputStatus */ +/** \brief Return PIO Output Status */ +/**---------------------------------------------------------------------------- */ + __inline unsigned int AT91F_PIO_GetOutputStatus( /* \return PIO Output Status */ + AT91PS_PIO pPio ) /* \arg pointer to a PIO controller */ + { return pPio->PIO_OSR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_IsOuputSet -//* \brief Test if PIO Output is Set -//*---------------------------------------------------------------------------- -__inline int AT91F_PIO_IsOutputSet( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag) // \arg flag to be tested -{ - return (AT91F_PIO_GetOutputStatus(pPio) & flag); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_InputFilterEnable -//* \brief Input Filter Enable PIO -//*---------------------------------------------------------------------------- -__inline void AT91F_PIO_InputFilterEnable( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag) // \arg pio input filter to be enabled -{ + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PIO_IsOuputSet */ +/** \brief Test if PIO Output is Set */ +/**---------------------------------------------------------------------------- */ + __inline int AT91F_PIO_IsOutputSet( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */ + unsigned int flag ) /* \arg flag to be tested */ + { + return( AT91F_PIO_GetOutputStatus( pPio ) & flag ); + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PIO_InputFilterEnable */ +/** \brief Input Filter Enable PIO */ +/**---------------------------------------------------------------------------- */ + __inline void AT91F_PIO_InputFilterEnable( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */ + unsigned int flag ) /* \arg pio input filter to be enabled */ + { pPio->PIO_IFER = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_InputFilterDisable -//* \brief Input Filter Disable PIO -//*---------------------------------------------------------------------------- -__inline void AT91F_PIO_InputFilterDisable( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag) // \arg pio input filter to be disabled -{ + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PIO_InputFilterDisable */ +/** \brief Input Filter Disable PIO */ +/**---------------------------------------------------------------------------- */ + __inline void AT91F_PIO_InputFilterDisable( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */ + unsigned int flag ) /* \arg pio input filter to be disabled */ + { pPio->PIO_IFDR = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_GetInputFilterStatus -//* \brief Return PIO Input Filter Status -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_PIO_GetInputFilterStatus( // \return PIO Input Filter Status - AT91PS_PIO pPio) // \arg pointer to a PIO controller -{ + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PIO_GetInputFilterStatus */ +/** \brief Return PIO Input Filter Status */ +/**---------------------------------------------------------------------------- */ + __inline unsigned int AT91F_PIO_GetInputFilterStatus( /* \return PIO Input Filter Status */ + AT91PS_PIO pPio ) /* \arg pointer to a PIO controller */ + { return pPio->PIO_IFSR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_IsInputFilterSet -//* \brief Test if PIO Input filter is Set -//*---------------------------------------------------------------------------- -__inline int AT91F_PIO_IsInputFilterSet( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag) // \arg flag to be tested -{ - return (AT91F_PIO_GetInputFilterStatus(pPio) & flag); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_GetOutputDataStatus -//* \brief Return PIO Output Data Status -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_PIO_GetOutputDataStatus( // \return PIO Output Data Status - AT91PS_PIO pPio) // \arg pointer to a PIO controller -{ + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PIO_IsInputFilterSet */ +/** \brief Test if PIO Input filter is Set */ +/**---------------------------------------------------------------------------- */ + __inline int AT91F_PIO_IsInputFilterSet( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */ + unsigned int flag ) /* \arg flag to be tested */ + { + return( AT91F_PIO_GetInputFilterStatus( pPio ) & flag ); + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PIO_GetOutputDataStatus */ +/** \brief Return PIO Output Data Status */ +/**---------------------------------------------------------------------------- */ + __inline unsigned int AT91F_PIO_GetOutputDataStatus( /* \return PIO Output Data Status */ + AT91PS_PIO pPio ) /* \arg pointer to a PIO controller */ + { return pPio->PIO_ODSR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_InterruptEnable -//* \brief Enable PIO Interrupt -//*---------------------------------------------------------------------------- -__inline void AT91F_PIO_InterruptEnable( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag) // \arg pio interrupt to be enabled -{ + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PIO_InterruptEnable */ +/** \brief Enable PIO Interrupt */ +/**---------------------------------------------------------------------------- */ + __inline void AT91F_PIO_InterruptEnable( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */ + unsigned int flag ) /* \arg pio interrupt to be enabled */ + { pPio->PIO_IER = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_InterruptDisable -//* \brief Disable PIO Interrupt -//*---------------------------------------------------------------------------- -__inline void AT91F_PIO_InterruptDisable( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag) // \arg pio interrupt to be disabled -{ + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PIO_InterruptDisable */ +/** \brief Disable PIO Interrupt */ +/**---------------------------------------------------------------------------- */ + __inline void AT91F_PIO_InterruptDisable( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */ + unsigned int flag ) /* \arg pio interrupt to be disabled */ + { pPio->PIO_IDR = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_GetInterruptMaskStatus -//* \brief Return PIO Interrupt Mask Status -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_PIO_GetInterruptMaskStatus( // \return PIO Interrupt Mask Status - AT91PS_PIO pPio) // \arg pointer to a PIO controller -{ + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PIO_GetInterruptMaskStatus */ +/** \brief Return PIO Interrupt Mask Status */ +/**---------------------------------------------------------------------------- */ + __inline unsigned int AT91F_PIO_GetInterruptMaskStatus( /* \return PIO Interrupt Mask Status */ + AT91PS_PIO pPio ) /* \arg pointer to a PIO controller */ + { return pPio->PIO_IMR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_GetInterruptStatus -//* \brief Return PIO Interrupt Status -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_PIO_GetInterruptStatus( // \return PIO Interrupt Status - AT91PS_PIO pPio) // \arg pointer to a PIO controller -{ + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PIO_GetInterruptStatus */ +/** \brief Return PIO Interrupt Status */ +/**---------------------------------------------------------------------------- */ + __inline unsigned int AT91F_PIO_GetInterruptStatus( /* \return PIO Interrupt Status */ + AT91PS_PIO pPio ) /* \arg pointer to a PIO controller */ + { return pPio->PIO_ISR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_IsInterruptMasked -//* \brief Test if PIO Interrupt is Masked -//*---------------------------------------------------------------------------- -__inline int AT91F_PIO_IsInterruptMasked( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag) // \arg flag to be tested -{ - return (AT91F_PIO_GetInterruptMaskStatus(pPio) & flag); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_IsInterruptSet -//* \brief Test if PIO Interrupt is Set -//*---------------------------------------------------------------------------- -__inline int AT91F_PIO_IsInterruptSet( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag) // \arg flag to be tested -{ - return (AT91F_PIO_GetInterruptStatus(pPio) & flag); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_MultiDriverEnable -//* \brief Multi Driver Enable PIO -//*---------------------------------------------------------------------------- -__inline void AT91F_PIO_MultiDriverEnable( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag) // \arg pio to be enabled -{ + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PIO_IsInterruptMasked */ +/** \brief Test if PIO Interrupt is Masked */ +/**---------------------------------------------------------------------------- */ + __inline int AT91F_PIO_IsInterruptMasked( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */ + unsigned int flag ) /* \arg flag to be tested */ + { + return( AT91F_PIO_GetInterruptMaskStatus( pPio ) & flag ); + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PIO_IsInterruptSet */ +/** \brief Test if PIO Interrupt is Set */ +/**---------------------------------------------------------------------------- */ + __inline int AT91F_PIO_IsInterruptSet( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */ + unsigned int flag ) /* \arg flag to be tested */ + { + return( AT91F_PIO_GetInterruptStatus( pPio ) & flag ); + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PIO_MultiDriverEnable */ +/** \brief Multi Driver Enable PIO */ +/**---------------------------------------------------------------------------- */ + __inline void AT91F_PIO_MultiDriverEnable( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */ + unsigned int flag ) /* \arg pio to be enabled */ + { pPio->PIO_MDER = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_MultiDriverDisable -//* \brief Multi Driver Disable PIO -//*---------------------------------------------------------------------------- -__inline void AT91F_PIO_MultiDriverDisable( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag) // \arg pio to be disabled -{ + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PIO_MultiDriverDisable */ +/** \brief Multi Driver Disable PIO */ +/**---------------------------------------------------------------------------- */ + __inline void AT91F_PIO_MultiDriverDisable( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */ + unsigned int flag ) /* \arg pio to be disabled */ + { pPio->PIO_MDDR = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_GetMultiDriverStatus -//* \brief Return PIO Multi Driver Status -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_PIO_GetMultiDriverStatus( // \return PIO Multi Driver Status - AT91PS_PIO pPio) // \arg pointer to a PIO controller -{ + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PIO_GetMultiDriverStatus */ +/** \brief Return PIO Multi Driver Status */ +/**---------------------------------------------------------------------------- */ + __inline unsigned int AT91F_PIO_GetMultiDriverStatus( /* \return PIO Multi Driver Status */ + AT91PS_PIO pPio ) /* \arg pointer to a PIO controller */ + { return pPio->PIO_MDSR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_IsMultiDriverSet -//* \brief Test if PIO MultiDriver is Set -//*---------------------------------------------------------------------------- -__inline int AT91F_PIO_IsMultiDriverSet( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag) // \arg flag to be tested -{ - return (AT91F_PIO_GetMultiDriverStatus(pPio) & flag); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_A_RegisterSelection -//* \brief PIO A Register Selection -//*---------------------------------------------------------------------------- -__inline void AT91F_PIO_A_RegisterSelection( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag) // \arg pio A register selection -{ + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PIO_IsMultiDriverSet */ +/** \brief Test if PIO MultiDriver is Set */ +/**---------------------------------------------------------------------------- */ + __inline int AT91F_PIO_IsMultiDriverSet( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */ + unsigned int flag ) /* \arg flag to be tested */ + { + return( AT91F_PIO_GetMultiDriverStatus( pPio ) & flag ); + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PIO_A_RegisterSelection */ +/** \brief PIO A Register Selection */ +/**---------------------------------------------------------------------------- */ + __inline void AT91F_PIO_A_RegisterSelection( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */ + unsigned int flag ) /* \arg pio A register selection */ + { pPio->PIO_ASR = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_B_RegisterSelection -//* \brief PIO B Register Selection -//*---------------------------------------------------------------------------- -__inline void AT91F_PIO_B_RegisterSelection( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag) // \arg pio B register selection -{ + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PIO_B_RegisterSelection */ +/** \brief PIO B Register Selection */ +/**---------------------------------------------------------------------------- */ + __inline void AT91F_PIO_B_RegisterSelection( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */ + unsigned int flag ) /* \arg pio B register selection */ + { pPio->PIO_BSR = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_Get_AB_RegisterStatus -//* \brief Return PIO Interrupt Status -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_PIO_Get_AB_RegisterStatus( // \return PIO AB Register Status - AT91PS_PIO pPio) // \arg pointer to a PIO controller -{ + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PIO_Get_AB_RegisterStatus */ +/** \brief Return PIO Interrupt Status */ +/**---------------------------------------------------------------------------- */ + __inline unsigned int AT91F_PIO_Get_AB_RegisterStatus( /* \return PIO AB Register Status */ + AT91PS_PIO pPio ) /* \arg pointer to a PIO controller */ + { return pPio->PIO_ABSR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_IsAB_RegisterSet -//* \brief Test if PIO AB Register is Set -//*---------------------------------------------------------------------------- -__inline int AT91F_PIO_IsAB_RegisterSet( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag) // \arg flag to be tested -{ - return (AT91F_PIO_Get_AB_RegisterStatus(pPio) & flag); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_OutputWriteEnable -//* \brief Output Write Enable PIO -//*---------------------------------------------------------------------------- -__inline void AT91F_PIO_OutputWriteEnable( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag) // \arg pio output write to be enabled -{ + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PIO_IsAB_RegisterSet */ +/** \brief Test if PIO AB Register is Set */ +/**---------------------------------------------------------------------------- */ + __inline int AT91F_PIO_IsAB_RegisterSet( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */ + unsigned int flag ) /* \arg flag to be tested */ + { + return( AT91F_PIO_Get_AB_RegisterStatus( pPio ) & flag ); + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PIO_OutputWriteEnable */ +/** \brief Output Write Enable PIO */ +/**---------------------------------------------------------------------------- */ + __inline void AT91F_PIO_OutputWriteEnable( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */ + unsigned int flag ) /* \arg pio output write to be enabled */ + { pPio->PIO_OWER = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_OutputWriteDisable -//* \brief Output Write Disable PIO -//*---------------------------------------------------------------------------- -__inline void AT91F_PIO_OutputWriteDisable( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag) // \arg pio output write to be disabled -{ + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PIO_OutputWriteDisable */ +/** \brief Output Write Disable PIO */ +/**---------------------------------------------------------------------------- */ + __inline void AT91F_PIO_OutputWriteDisable( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */ + unsigned int flag ) /* \arg pio output write to be disabled */ + { pPio->PIO_OWDR = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_GetOutputWriteStatus -//* \brief Return PIO Output Write Status -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_PIO_GetOutputWriteStatus( // \return PIO Output Write Status - AT91PS_PIO pPio) // \arg pointer to a PIO controller -{ + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PIO_GetOutputWriteStatus */ +/** \brief Return PIO Output Write Status */ +/**---------------------------------------------------------------------------- */ + __inline unsigned int AT91F_PIO_GetOutputWriteStatus( /* \return PIO Output Write Status */ + AT91PS_PIO pPio ) /* \arg pointer to a PIO controller */ + { return pPio->PIO_OWSR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_IsOutputWriteSet -//* \brief Test if PIO OutputWrite is Set -//*---------------------------------------------------------------------------- -__inline int AT91F_PIO_IsOutputWriteSet( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag) // \arg flag to be tested -{ - return (AT91F_PIO_GetOutputWriteStatus(pPio) & flag); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_GetCfgPullup -//* \brief Return PIO Configuration Pullup -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_PIO_GetCfgPullup( // \return PIO Configuration Pullup - AT91PS_PIO pPio) // \arg pointer to a PIO controller -{ + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PIO_IsOutputWriteSet */ +/** \brief Test if PIO OutputWrite is Set */ +/**---------------------------------------------------------------------------- */ + __inline int AT91F_PIO_IsOutputWriteSet( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */ + unsigned int flag ) /* \arg flag to be tested */ + { + return( AT91F_PIO_GetOutputWriteStatus( pPio ) & flag ); + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PIO_GetCfgPullup */ +/** \brief Return PIO Configuration Pullup */ +/**---------------------------------------------------------------------------- */ + __inline unsigned int AT91F_PIO_GetCfgPullup( /* \return PIO Configuration Pullup */ + AT91PS_PIO pPio ) /* \arg pointer to a PIO controller */ + { return pPio->PIO_PPUSR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_IsOutputDataStatusSet -//* \brief Test if PIO Output Data Status is Set -//*---------------------------------------------------------------------------- -__inline int AT91F_PIO_IsOutputDataStatusSet( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag) // \arg flag to be tested -{ - return (AT91F_PIO_GetOutputDataStatus(pPio) & flag); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_IsCfgPullupStatusSet -//* \brief Test if PIO Configuration Pullup Status is Set -//*---------------------------------------------------------------------------- -__inline int AT91F_PIO_IsCfgPullupStatusSet( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag) // \arg flag to be tested -{ - return (~AT91F_PIO_GetCfgPullup(pPio) & flag); -} + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PIO_IsOutputDataStatusSet */ +/** \brief Test if PIO Output Data Status is Set */ +/**---------------------------------------------------------------------------- */ + __inline int AT91F_PIO_IsOutputDataStatusSet( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */ + unsigned int flag ) /* \arg flag to be tested */ + { + return( AT91F_PIO_GetOutputDataStatus( pPio ) & flag ); + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PIO_IsCfgPullupStatusSet */ +/** \brief Test if PIO Configuration Pullup Status is Set */ +/**---------------------------------------------------------------------------- */ + __inline int AT91F_PIO_IsCfgPullupStatusSet( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */ + unsigned int flag ) /* \arg flag to be tested */ + { + return( ~AT91F_PIO_GetCfgPullup( pPio ) & flag ); + } /* ***************************************************************************** - SOFTWARE API FOR PMC - ***************************************************************************** */ -//*---------------------------------------------------------------------------- -//* \fn AT91F_PMC_CfgSysClkEnableReg -//* \brief Configure the System Clock Enable Register of the PMC controller -//*---------------------------------------------------------------------------- -__inline void AT91F_PMC_CfgSysClkEnableReg ( - AT91PS_PMC pPMC, // \arg pointer to PMC controller - unsigned int mode) -{ - //* Write to the SCER register - pPMC->PMC_SCER = mode; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PMC_CfgSysClkDisableReg -//* \brief Configure the System Clock Disable Register of the PMC controller -//*---------------------------------------------------------------------------- -__inline void AT91F_PMC_CfgSysClkDisableReg ( - AT91PS_PMC pPMC, // \arg pointer to PMC controller - unsigned int mode) -{ - //* Write to the SCDR register - pPMC->PMC_SCDR = mode; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PMC_GetSysClkStatusReg -//* \brief Return the System Clock Status Register of the PMC controller -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_PMC_GetSysClkStatusReg ( - AT91PS_PMC pPMC // pointer to a CAN controller - ) -{ - return pPMC->PMC_SCSR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PMC_EnablePeriphClock -//* \brief Enable peripheral clock -//*---------------------------------------------------------------------------- -__inline void AT91F_PMC_EnablePeriphClock ( - AT91PS_PMC pPMC, // \arg pointer to PMC controller - unsigned int periphIds) // \arg IDs of peripherals to enable -{ - pPMC->PMC_PCER = periphIds; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PMC_DisablePeriphClock -//* \brief Disable peripheral clock -//*---------------------------------------------------------------------------- -__inline void AT91F_PMC_DisablePeriphClock ( - AT91PS_PMC pPMC, // \arg pointer to PMC controller - unsigned int periphIds) // \arg IDs of peripherals to enable -{ - pPMC->PMC_PCDR = periphIds; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PMC_GetPeriphClock -//* \brief Get peripheral clock status -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_PMC_GetPeriphClock ( - AT91PS_PMC pPMC) // \arg pointer to PMC controller -{ - return pPMC->PMC_PCSR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_CKGR_CfgMainOscillatorReg -//* \brief Cfg the main oscillator -//*---------------------------------------------------------------------------- -__inline void AT91F_CKGR_CfgMainOscillatorReg ( - AT91PS_CKGR pCKGR, // \arg pointer to CKGR controller - unsigned int mode) -{ - pCKGR->CKGR_MOR = mode; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_CKGR_GetMainOscillatorReg -//* \brief Cfg the main oscillator -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_CKGR_GetMainOscillatorReg ( - AT91PS_CKGR pCKGR) // \arg pointer to CKGR controller -{ - return pCKGR->CKGR_MOR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_CKGR_EnableMainOscillator -//* \brief Enable the main oscillator -//*---------------------------------------------------------------------------- -__inline void AT91F_CKGR_EnableMainOscillator( - AT91PS_CKGR pCKGR) // \arg pointer to CKGR controller -{ - pCKGR->CKGR_MOR |= AT91C_CKGR_MOSCEN; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_CKGR_DisableMainOscillator -//* \brief Disable the main oscillator -//*---------------------------------------------------------------------------- -__inline void AT91F_CKGR_DisableMainOscillator ( - AT91PS_CKGR pCKGR) // \arg pointer to CKGR controller -{ - pCKGR->CKGR_MOR &= ~AT91C_CKGR_MOSCEN; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_CKGR_CfgMainOscStartUpTime -//* \brief Cfg MOR Register according to the main osc startup time -//*---------------------------------------------------------------------------- -__inline void AT91F_CKGR_CfgMainOscStartUpTime ( - AT91PS_CKGR pCKGR, // \arg pointer to CKGR controller - unsigned int startup_time, // \arg main osc startup time in microsecond (us) - unsigned int slowClock) // \arg slowClock in Hz -{ - pCKGR->CKGR_MOR &= ~AT91C_CKGR_OSCOUNT; - pCKGR->CKGR_MOR |= ((slowClock * startup_time)/(8*1000000)) << 8; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_CKGR_GetMainClockFreqReg -//* \brief Cfg the main oscillator -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_CKGR_GetMainClockFreqReg ( - AT91PS_CKGR pCKGR) // \arg pointer to CKGR controller -{ - return pCKGR->CKGR_MCFR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_CKGR_GetMainClock -//* \brief Return Main clock in Hz -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_CKGR_GetMainClock ( - AT91PS_CKGR pCKGR, // \arg pointer to CKGR controller - unsigned int slowClock) // \arg slowClock in Hz -{ - return ((pCKGR->CKGR_MCFR & AT91C_CKGR_MAINF) * slowClock) >> 4; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PMC_CfgMCKReg -//* \brief Cfg Master Clock Register -//*---------------------------------------------------------------------------- -__inline void AT91F_PMC_CfgMCKReg ( - AT91PS_PMC pPMC, // \arg pointer to PMC controller - unsigned int mode) -{ - pPMC->PMC_MCKR = mode; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PMC_GetMCKReg -//* \brief Return Master Clock Register -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_PMC_GetMCKReg( - AT91PS_PMC pPMC) // \arg pointer to PMC controller -{ - return pPMC->PMC_MCKR; -} - -//*------------------------------------------------------------------------------ -//* \fn AT91F_PMC_GetMasterClock -//* \brief Return master clock in Hz which correponds to processor clock for ARM7 -//*------------------------------------------------------------------------------ -__inline unsigned int AT91F_PMC_GetMasterClock ( - AT91PS_PMC pPMC, // \arg pointer to PMC controller - AT91PS_CKGR pCKGR, // \arg pointer to CKGR controller - unsigned int slowClock) // \arg slowClock in Hz -{ - unsigned int reg = pPMC->PMC_MCKR; - unsigned int prescaler = (1 << ((reg & AT91C_PMC_PRES) >> 2)); - unsigned int pllDivider, pllMultiplier; - - switch (reg & AT91C_PMC_CSS) { - case AT91C_PMC_CSS_SLOW_CLK: // Slow clock selected - return slowClock / prescaler; - case AT91C_PMC_CSS_MAIN_CLK: // Main clock is selected - return AT91F_CKGR_GetMainClock(pCKGR, slowClock) / prescaler; - case AT91C_PMC_CSS_PLL_CLK: // PLLB clock is selected - reg = pCKGR->CKGR_PLLR; - pllDivider = (reg & AT91C_CKGR_DIV); - pllMultiplier = ((reg & AT91C_CKGR_MUL) >> 16) + 1; - return AT91F_CKGR_GetMainClock(pCKGR, slowClock) / pllDivider * pllMultiplier / prescaler; - } - return 0; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PMC_EnablePCK -//* \brief Enable peripheral clock -//*---------------------------------------------------------------------------- -__inline void AT91F_PMC_EnablePCK ( - AT91PS_PMC pPMC, // \arg pointer to PMC controller - unsigned int pck, // \arg Peripheral clock identifier 0 .. 7 - unsigned int mode) -{ - pPMC->PMC_PCKR[pck] = mode; - pPMC->PMC_SCER = (1 << pck) << 8; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PMC_DisablePCK -//* \brief Enable peripheral clock -//*---------------------------------------------------------------------------- -__inline void AT91F_PMC_DisablePCK ( - AT91PS_PMC pPMC, // \arg pointer to PMC controller - unsigned int pck) // \arg Peripheral clock identifier 0 .. 7 -{ - pPMC->PMC_SCDR = (1 << pck) << 8; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PMC_EnableIt -//* \brief Enable PMC interrupt -//*---------------------------------------------------------------------------- -__inline void AT91F_PMC_EnableIt ( - AT91PS_PMC pPMC, // pointer to a PMC controller - unsigned int flag) // IT to be enabled -{ - //* Write to the IER register - pPMC->PMC_IER = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PMC_DisableIt -//* \brief Disable PMC interrupt -//*---------------------------------------------------------------------------- -__inline void AT91F_PMC_DisableIt ( - AT91PS_PMC pPMC, // pointer to a PMC controller - unsigned int flag) // IT to be disabled -{ - //* Write to the IDR register - pPMC->PMC_IDR = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PMC_GetStatus -//* \brief Return PMC Interrupt Status -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_PMC_GetStatus( // \return PMC Interrupt Status - AT91PS_PMC pPMC) // pointer to a PMC controller -{ - return pPMC->PMC_SR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PMC_GetInterruptMaskStatus -//* \brief Return PMC Interrupt Mask Status -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_PMC_GetInterruptMaskStatus( // \return PMC Interrupt Mask Status - AT91PS_PMC pPMC) // pointer to a PMC controller -{ - return pPMC->PMC_IMR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PMC_IsInterruptMasked -//* \brief Test if PMC Interrupt is Masked -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_PMC_IsInterruptMasked( - AT91PS_PMC pPMC, // \arg pointer to a PMC controller - unsigned int flag) // \arg flag to be tested -{ - return (AT91F_PMC_GetInterruptMaskStatus(pPMC) & flag); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PMC_IsStatusSet -//* \brief Test if PMC Status is Set -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_PMC_IsStatusSet( - AT91PS_PMC pPMC, // \arg pointer to a PMC controller - unsigned int flag) // \arg flag to be tested -{ - return (AT91F_PMC_GetStatus(pPMC) & flag); -}/* ***************************************************************************** - SOFTWARE API FOR RSTC - ***************************************************************************** */ -//*---------------------------------------------------------------------------- -//* \fn AT91F_RSTSoftReset -//* \brief Start Software Reset -//*---------------------------------------------------------------------------- -__inline void AT91F_RSTSoftReset( - AT91PS_RSTC pRSTC, - unsigned int reset) -{ - pRSTC->RSTC_RCR = (0xA5000000 | reset); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_RSTSetMode -//* \brief Set Reset Mode -//*---------------------------------------------------------------------------- -__inline void AT91F_RSTSetMode( - AT91PS_RSTC pRSTC, - unsigned int mode) -{ - pRSTC->RSTC_RMR = (0xA5000000 | mode); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_RSTGetMode -//* \brief Get Reset Mode -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_RSTGetMode( - AT91PS_RSTC pRSTC) -{ - return (pRSTC->RSTC_RMR); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_RSTGetStatus -//* \brief Get Reset Status -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_RSTGetStatus( - AT91PS_RSTC pRSTC) -{ - return (pRSTC->RSTC_RSR); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_RSTIsSoftRstActive -//* \brief Return !=0 if software reset is still not completed -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_RSTIsSoftRstActive( - AT91PS_RSTC pRSTC) -{ - return ((pRSTC->RSTC_RSR) & AT91C_RSTC_SRCMP); -} +* SOFTWARE API FOR PMC +***************************************************************************** */ +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PMC_CfgSysClkEnableReg */ +/** \brief Configure the System Clock Enable Register of the PMC controller */ +/**---------------------------------------------------------------------------- */ + __inline void AT91F_PMC_CfgSysClkEnableReg( AT91PS_PMC pPMC, /* \arg pointer to PMC controller */ + unsigned int mode ) + { + /** Write to the SCER register */ + pPMC->PMC_SCER = mode; + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PMC_CfgSysClkDisableReg */ +/** \brief Configure the System Clock Disable Register of the PMC controller */ +/**---------------------------------------------------------------------------- */ + __inline void AT91F_PMC_CfgSysClkDisableReg( AT91PS_PMC pPMC, /* \arg pointer to PMC controller */ + unsigned int mode ) + { + /** Write to the SCDR register */ + pPMC->PMC_SCDR = mode; + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PMC_GetSysClkStatusReg */ +/** \brief Return the System Clock Status Register of the PMC controller */ +/**---------------------------------------------------------------------------- */ + __inline unsigned int AT91F_PMC_GetSysClkStatusReg( AT91PS_PMC pPMC /* pointer to a CAN controller */ + ) + { + return pPMC->PMC_SCSR; + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PMC_EnablePeriphClock */ +/** \brief Enable peripheral clock */ +/**---------------------------------------------------------------------------- */ + __inline void AT91F_PMC_EnablePeriphClock( AT91PS_PMC pPMC, /* \arg pointer to PMC controller */ + unsigned int periphIds ) /* \arg IDs of peripherals to enable */ + { + pPMC->PMC_PCER = periphIds; + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PMC_DisablePeriphClock */ +/** \brief Disable peripheral clock */ +/**---------------------------------------------------------------------------- */ + __inline void AT91F_PMC_DisablePeriphClock( AT91PS_PMC pPMC, /* \arg pointer to PMC controller */ + unsigned int periphIds ) /* \arg IDs of peripherals to enable */ + { + pPMC->PMC_PCDR = periphIds; + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PMC_GetPeriphClock */ +/** \brief Get peripheral clock status */ +/**---------------------------------------------------------------------------- */ + __inline unsigned int AT91F_PMC_GetPeriphClock( AT91PS_PMC pPMC ) /* \arg pointer to PMC controller */ + { + return pPMC->PMC_PCSR; + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_CKGR_CfgMainOscillatorReg */ +/** \brief Cfg the main oscillator */ +/**---------------------------------------------------------------------------- */ + __inline void AT91F_CKGR_CfgMainOscillatorReg( AT91PS_CKGR pCKGR, /* \arg pointer to CKGR controller */ + unsigned int mode ) + { + pCKGR->CKGR_MOR = mode; + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_CKGR_GetMainOscillatorReg */ +/** \brief Cfg the main oscillator */ +/**---------------------------------------------------------------------------- */ + __inline unsigned int AT91F_CKGR_GetMainOscillatorReg( AT91PS_CKGR pCKGR ) /* \arg pointer to CKGR controller */ + { + return pCKGR->CKGR_MOR; + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_CKGR_EnableMainOscillator */ +/** \brief Enable the main oscillator */ +/**---------------------------------------------------------------------------- */ + __inline void AT91F_CKGR_EnableMainOscillator( AT91PS_CKGR pCKGR ) /* \arg pointer to CKGR controller */ + { + pCKGR->CKGR_MOR |= AT91C_CKGR_MOSCEN; + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_CKGR_DisableMainOscillator */ +/** \brief Disable the main oscillator */ +/**---------------------------------------------------------------------------- */ + __inline void AT91F_CKGR_DisableMainOscillator( AT91PS_CKGR pCKGR ) /* \arg pointer to CKGR controller */ + { + pCKGR->CKGR_MOR &= ~AT91C_CKGR_MOSCEN; + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_CKGR_CfgMainOscStartUpTime */ +/** \brief Cfg MOR Register according to the main osc startup time */ +/**---------------------------------------------------------------------------- */ + __inline void AT91F_CKGR_CfgMainOscStartUpTime( AT91PS_CKGR pCKGR, /* \arg pointer to CKGR controller */ + unsigned int startup_time, /* \arg main osc startup time in microsecond (us) */ + unsigned int slowClock ) /* \arg slowClock in Hz */ + { + pCKGR->CKGR_MOR &= ~AT91C_CKGR_OSCOUNT; + pCKGR->CKGR_MOR |= ( ( slowClock * startup_time ) / ( 8 * 1000000 ) ) << 8; + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_CKGR_GetMainClockFreqReg */ +/** \brief Cfg the main oscillator */ +/**---------------------------------------------------------------------------- */ + __inline unsigned int AT91F_CKGR_GetMainClockFreqReg( AT91PS_CKGR pCKGR ) /* \arg pointer to CKGR controller */ + { + return pCKGR->CKGR_MCFR; + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_CKGR_GetMainClock */ +/** \brief Return Main clock in Hz */ +/**---------------------------------------------------------------------------- */ + __inline unsigned int AT91F_CKGR_GetMainClock( AT91PS_CKGR pCKGR, /* \arg pointer to CKGR controller */ + unsigned int slowClock ) /* \arg slowClock in Hz */ + { + return ( ( pCKGR->CKGR_MCFR & AT91C_CKGR_MAINF ) * slowClock ) >> 4; + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PMC_CfgMCKReg */ +/** \brief Cfg Master Clock Register */ +/**---------------------------------------------------------------------------- */ + __inline void AT91F_PMC_CfgMCKReg( AT91PS_PMC pPMC, /* \arg pointer to PMC controller */ + unsigned int mode ) + { + pPMC->PMC_MCKR = mode; + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PMC_GetMCKReg */ +/** \brief Return Master Clock Register */ +/**---------------------------------------------------------------------------- */ + __inline unsigned int AT91F_PMC_GetMCKReg( AT91PS_PMC pPMC ) /* \arg pointer to PMC controller */ + { + return pPMC->PMC_MCKR; + } + +/**------------------------------------------------------------------------------ */ +/** \fn AT91F_PMC_GetMasterClock */ +/** \brief Return master clock in Hz which corresponds to processor clock for ARM7 */ +/**------------------------------------------------------------------------------ */ + __inline unsigned int AT91F_PMC_GetMasterClock( AT91PS_PMC pPMC, /* \arg pointer to PMC controller */ + AT91PS_CKGR pCKGR, /* \arg pointer to CKGR controller */ + unsigned int slowClock ) /* \arg slowClock in Hz */ + { + unsigned int reg = pPMC->PMC_MCKR; + unsigned int prescaler = ( 1 << ( ( reg & AT91C_PMC_PRES ) >> 2 ) ); + unsigned int pllDivider, pllMultiplier; + + switch( reg & AT91C_PMC_CSS ) + { + case AT91C_PMC_CSS_SLOW_CLK: /* Slow clock selected */ + return slowClock / prescaler; + + case AT91C_PMC_CSS_MAIN_CLK: /* Main clock is selected */ + return AT91F_CKGR_GetMainClock( pCKGR, slowClock ) / prescaler; + + case AT91C_PMC_CSS_PLL_CLK: /* PLLB clock is selected */ + reg = pCKGR->CKGR_PLLR; + pllDivider = ( reg & AT91C_CKGR_DIV ); + pllMultiplier = ( ( reg & AT91C_CKGR_MUL ) >> 16 ) + 1; + return AT91F_CKGR_GetMainClock( pCKGR, slowClock ) / pllDivider * pllMultiplier / prescaler; + } + + return 0; + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PMC_EnablePCK */ +/** \brief Enable peripheral clock */ +/**---------------------------------------------------------------------------- */ + __inline void AT91F_PMC_EnablePCK( AT91PS_PMC pPMC, /* \arg pointer to PMC controller */ + unsigned int pck, /* \arg Peripheral clock identifier 0 .. 7 */ + unsigned int mode ) + { + pPMC->PMC_PCKR[ pck ] = mode; + pPMC->PMC_SCER = ( 1 << pck ) << 8; + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PMC_DisablePCK */ +/** \brief Enable peripheral clock */ +/**---------------------------------------------------------------------------- */ + __inline void AT91F_PMC_DisablePCK( AT91PS_PMC pPMC, /* \arg pointer to PMC controller */ + unsigned int pck ) /* \arg Peripheral clock identifier 0 .. 7 */ + { + pPMC->PMC_SCDR = ( 1 << pck ) << 8; + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PMC_EnableIt */ +/** \brief Enable PMC interrupt */ +/**---------------------------------------------------------------------------- */ + __inline void AT91F_PMC_EnableIt( AT91PS_PMC pPMC, /* pointer to a PMC controller */ + unsigned int flag ) /* IT to be enabled */ + { + /** Write to the IER register */ + pPMC->PMC_IER = flag; + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PMC_DisableIt */ +/** \brief Disable PMC interrupt */ +/**---------------------------------------------------------------------------- */ + __inline void AT91F_PMC_DisableIt( AT91PS_PMC pPMC, /* pointer to a PMC controller */ + unsigned int flag ) /* IT to be disabled */ + { + /** Write to the IDR register */ + pPMC->PMC_IDR = flag; + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PMC_GetStatus */ +/** \brief Return PMC Interrupt Status */ +/**---------------------------------------------------------------------------- */ + __inline unsigned int AT91F_PMC_GetStatus( /* \return PMC Interrupt Status */ + AT91PS_PMC pPMC ) /* pointer to a PMC controller */ + { + return pPMC->PMC_SR; + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PMC_GetInterruptMaskStatus */ +/** \brief Return PMC Interrupt Mask Status */ +/**---------------------------------------------------------------------------- */ + __inline unsigned int AT91F_PMC_GetInterruptMaskStatus( /* \return PMC Interrupt Mask Status */ + AT91PS_PMC pPMC ) /* pointer to a PMC controller */ + { + return pPMC->PMC_IMR; + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PMC_IsInterruptMasked */ +/** \brief Test if PMC Interrupt is Masked */ +/**---------------------------------------------------------------------------- */ + __inline unsigned int AT91F_PMC_IsInterruptMasked( AT91PS_PMC pPMC, /* \arg pointer to a PMC controller */ + unsigned int flag ) /* \arg flag to be tested */ + { + return( AT91F_PMC_GetInterruptMaskStatus( pPMC ) & flag ); + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PMC_IsStatusSet */ +/** \brief Test if PMC Status is Set */ +/**---------------------------------------------------------------------------- */ + __inline unsigned int AT91F_PMC_IsStatusSet( AT91PS_PMC pPMC, /* \arg pointer to a PMC controller */ + unsigned int flag ) /* \arg flag to be tested */ + { + return( AT91F_PMC_GetStatus( pPMC ) & flag ); + } /* ***************************************************************************** + * SOFTWARE API FOR RSTC + ***************************************************************************** */ +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_RSTSoftReset */ +/** \brief Start Software Reset */ +/**---------------------------------------------------------------------------- */ + __inline void AT91F_RSTSoftReset( AT91PS_RSTC pRSTC, + unsigned int reset ) + { + pRSTC->RSTC_RCR = ( 0xA5000000 | reset ); + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_RSTSetMode */ +/** \brief Set Reset Mode */ +/**---------------------------------------------------------------------------- */ + __inline void AT91F_RSTSetMode( AT91PS_RSTC pRSTC, + unsigned int mode ) + { + pRSTC->RSTC_RMR = ( 0xA5000000 | mode ); + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_RSTGetMode */ +/** \brief Get Reset Mode */ +/**---------------------------------------------------------------------------- */ + __inline unsigned int AT91F_RSTGetMode( AT91PS_RSTC pRSTC ) + { + return( pRSTC->RSTC_RMR ); + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_RSTGetStatus */ +/** \brief Get Reset Status */ +/**---------------------------------------------------------------------------- */ + __inline unsigned int AT91F_RSTGetStatus( AT91PS_RSTC pRSTC ) + { + return( pRSTC->RSTC_RSR ); + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_RSTIsSoftRstActive */ +/** \brief Return !=0 if software reset is still not completed */ +/**---------------------------------------------------------------------------- */ + __inline unsigned int AT91F_RSTIsSoftRstActive( AT91PS_RSTC pRSTC ) + { + return( ( pRSTC->RSTC_RSR ) & AT91C_RSTC_SRCMP ); + } + /* ***************************************************************************** - SOFTWARE API FOR RTTC - ***************************************************************************** */ -//*-------------------------------------------------------------------------------------- -//* \fn AT91F_SetRTT_TimeBase() -//* \brief Set the RTT prescaler according to the TimeBase in ms -//*-------------------------------------------------------------------------------------- -__inline unsigned int AT91F_RTTSetTimeBase( - AT91PS_RTTC pRTTC, - unsigned int ms) -{ - if (ms > 2000) - return 1; // AT91C_TIME_OUT_OF_RANGE - pRTTC->RTTC_RTMR &= ~0xFFFF; - pRTTC->RTTC_RTMR |= (((ms << 15) /1000) & 0xFFFF); - return 0; -} - -//*-------------------------------------------------------------------------------------- -//* \fn AT91F_RTTSetPrescaler() -//* \brief Set the new prescaler value -//*-------------------------------------------------------------------------------------- -__inline unsigned int AT91F_RTTSetPrescaler( - AT91PS_RTTC pRTTC, - unsigned int rtpres) -{ - pRTTC->RTTC_RTMR &= ~0xFFFF; - pRTTC->RTTC_RTMR |= (rtpres & 0xFFFF); - return (pRTTC->RTTC_RTMR); -} - -//*-------------------------------------------------------------------------------------- -//* \fn AT91F_RTTRestart() -//* \brief Restart the RTT prescaler -//*-------------------------------------------------------------------------------------- -__inline void AT91F_RTTRestart( - AT91PS_RTTC pRTTC) -{ - pRTTC->RTTC_RTMR |= AT91C_RTTC_RTTRST; -} - - -//*-------------------------------------------------------------------------------------- -//* \fn AT91F_RTT_SetAlarmINT() -//* \brief Enable RTT Alarm Interrupt -//*-------------------------------------------------------------------------------------- -__inline void AT91F_RTTSetAlarmINT( - AT91PS_RTTC pRTTC) -{ - pRTTC->RTTC_RTMR |= AT91C_RTTC_ALMIEN; -} - -//*-------------------------------------------------------------------------------------- -//* \fn AT91F_RTT_ClearAlarmINT() -//* \brief Disable RTT Alarm Interrupt -//*-------------------------------------------------------------------------------------- -__inline void AT91F_RTTClearAlarmINT( - AT91PS_RTTC pRTTC) -{ - pRTTC->RTTC_RTMR &= ~AT91C_RTTC_ALMIEN; -} - -//*-------------------------------------------------------------------------------------- -//* \fn AT91F_RTT_SetRttIncINT() -//* \brief Enable RTT INC Interrupt -//*-------------------------------------------------------------------------------------- -__inline void AT91F_RTTSetRttIncINT( - AT91PS_RTTC pRTTC) -{ - pRTTC->RTTC_RTMR |= AT91C_RTTC_RTTINCIEN; -} - -//*-------------------------------------------------------------------------------------- -//* \fn AT91F_RTT_ClearRttIncINT() -//* \brief Disable RTT INC Interrupt -//*-------------------------------------------------------------------------------------- -__inline void AT91F_RTTClearRttIncINT( - AT91PS_RTTC pRTTC) -{ - pRTTC->RTTC_RTMR &= ~AT91C_RTTC_RTTINCIEN; -} - -//*-------------------------------------------------------------------------------------- -//* \fn AT91F_RTT_SetAlarmValue() -//* \brief Set RTT Alarm Value -//*-------------------------------------------------------------------------------------- -__inline void AT91F_RTTSetAlarmValue( - AT91PS_RTTC pRTTC, unsigned int alarm) -{ - pRTTC->RTTC_RTAR = alarm; -} - -//*-------------------------------------------------------------------------------------- -//* \fn AT91F_RTT_GetAlarmValue() -//* \brief Get RTT Alarm Value -//*-------------------------------------------------------------------------------------- -__inline unsigned int AT91F_RTTGetAlarmValue( - AT91PS_RTTC pRTTC) -{ - return(pRTTC->RTTC_RTAR); -} - -//*-------------------------------------------------------------------------------------- -//* \fn AT91F_RTTGetStatus() -//* \brief Read the RTT status -//*-------------------------------------------------------------------------------------- -__inline unsigned int AT91F_RTTGetStatus( - AT91PS_RTTC pRTTC) -{ - return(pRTTC->RTTC_RTSR); -} - -//*-------------------------------------------------------------------------------------- -//* \fn AT91F_RTT_ReadValue() -//* \brief Read the RTT value -//*-------------------------------------------------------------------------------------- -__inline unsigned int AT91F_RTTReadValue( - AT91PS_RTTC pRTTC) -{ - register volatile unsigned int val1,val2; - do - { - val1 = pRTTC->RTTC_RTVR; - val2 = pRTTC->RTTC_RTVR; - } - while(val1 != val2); - return(val1); -} +* SOFTWARE API FOR RTTC +***************************************************************************** */ +/**-------------------------------------------------------------------------------------- */ +/** \fn AT91F_SetRTT_TimeBase() */ +/** \brief Set the RTT prescaler according to the TimeBase in ms */ +/**-------------------------------------------------------------------------------------- */ + __inline unsigned int AT91F_RTTSetTimeBase( AT91PS_RTTC pRTTC, + unsigned int ms ) + { + if( ms > 2000 ) + { + return 1; /* AT91C_TIME_OUT_OF_RANGE */ + } + + pRTTC->RTTC_RTMR &= ~0xFFFF; + pRTTC->RTTC_RTMR |= ( ( ( ms << 15 ) / 1000 ) & 0xFFFF ); + return 0; + } + +/**-------------------------------------------------------------------------------------- */ +/** \fn AT91F_RTTSetPrescaler() */ +/** \brief Set the new prescaler value */ +/**-------------------------------------------------------------------------------------- */ + __inline unsigned int AT91F_RTTSetPrescaler( AT91PS_RTTC pRTTC, + unsigned int rtpres ) + { + pRTTC->RTTC_RTMR &= ~0xFFFF; + pRTTC->RTTC_RTMR |= ( rtpres & 0xFFFF ); + return( pRTTC->RTTC_RTMR ); + } + +/**-------------------------------------------------------------------------------------- */ +/** \fn AT91F_RTTRestart() */ +/** \brief Restart the RTT prescaler */ +/**-------------------------------------------------------------------------------------- */ + __inline void AT91F_RTTRestart( AT91PS_RTTC pRTTC ) + { + pRTTC->RTTC_RTMR |= AT91C_RTTC_RTTRST; + } + + +/**-------------------------------------------------------------------------------------- */ +/** \fn AT91F_RTT_SetAlarmINT() */ +/** \brief Enable RTT Alarm Interrupt */ +/**-------------------------------------------------------------------------------------- */ + __inline void AT91F_RTTSetAlarmINT( AT91PS_RTTC pRTTC ) + { + pRTTC->RTTC_RTMR |= AT91C_RTTC_ALMIEN; + } + +/**-------------------------------------------------------------------------------------- */ +/** \fn AT91F_RTT_ClearAlarmINT() */ +/** \brief Disable RTT Alarm Interrupt */ +/**-------------------------------------------------------------------------------------- */ + __inline void AT91F_RTTClearAlarmINT( AT91PS_RTTC pRTTC ) + { + pRTTC->RTTC_RTMR &= ~AT91C_RTTC_ALMIEN; + } + +/**-------------------------------------------------------------------------------------- */ +/** \fn AT91F_RTT_SetRttIncINT() */ +/** \brief Enable RTT INC Interrupt */ +/**-------------------------------------------------------------------------------------- */ + __inline void AT91F_RTTSetRttIncINT( AT91PS_RTTC pRTTC ) + { + pRTTC->RTTC_RTMR |= AT91C_RTTC_RTTINCIEN; + } + +/**-------------------------------------------------------------------------------------- */ +/** \fn AT91F_RTT_ClearRttIncINT() */ +/** \brief Disable RTT INC Interrupt */ +/**-------------------------------------------------------------------------------------- */ + __inline void AT91F_RTTClearRttIncINT( AT91PS_RTTC pRTTC ) + { + pRTTC->RTTC_RTMR &= ~AT91C_RTTC_RTTINCIEN; + } + +/**-------------------------------------------------------------------------------------- */ +/** \fn AT91F_RTT_SetAlarmValue() */ +/** \brief Set RTT Alarm Value */ +/**-------------------------------------------------------------------------------------- */ + __inline void AT91F_RTTSetAlarmValue( AT91PS_RTTC pRTTC, + unsigned int alarm ) + { + pRTTC->RTTC_RTAR = alarm; + } + +/**-------------------------------------------------------------------------------------- */ +/** \fn AT91F_RTT_GetAlarmValue() */ +/** \brief Get RTT Alarm Value */ +/**-------------------------------------------------------------------------------------- */ + __inline unsigned int AT91F_RTTGetAlarmValue( AT91PS_RTTC pRTTC ) + { + return( pRTTC->RTTC_RTAR ); + } + +/**-------------------------------------------------------------------------------------- */ +/** \fn AT91F_RTTGetStatus() */ +/** \brief Read the RTT status */ +/**-------------------------------------------------------------------------------------- */ + __inline unsigned int AT91F_RTTGetStatus( AT91PS_RTTC pRTTC ) + { + return( pRTTC->RTTC_RTSR ); + } + +/**-------------------------------------------------------------------------------------- */ +/** \fn AT91F_RTT_ReadValue() */ +/** \brief Read the RTT value */ +/**-------------------------------------------------------------------------------------- */ + __inline unsigned int AT91F_RTTReadValue( AT91PS_RTTC pRTTC ) + { + register volatile unsigned int val1, val2; + + do + { + val1 = pRTTC->RTTC_RTVR; + val2 = pRTTC->RTTC_RTVR; + } + while( val1 != val2 ); + + return( val1 ); + } + /* ***************************************************************************** - SOFTWARE API FOR PITC - ***************************************************************************** */ -//*---------------------------------------------------------------------------- -//* \fn AT91F_PITInit -//* \brief System timer init : period in \ No newline at end of file +* SOFTWARE API FOR PITC +***************************************************************************** */ +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PITInit */ +/** \brief System timer init : period in */ diff --git a/Source/portable/IAR/AtmelSAM7S64/lib_AT91SAM7X256.h b/Source/portable/IAR/AtmelSAM7S64/lib_AT91SAM7X256.h index 556e0ca16..0d9a70884 100644 --- a/Source/portable/IAR/AtmelSAM7S64/lib_AT91SAM7X256.h +++ b/Source/portable/IAR/AtmelSAM7S64/lib_AT91SAM7X256.h @@ -1,1469 +1,1396 @@ -//* ---------------------------------------------------------------------------- -//* ATMEL Microcontroller Software Support - ROUSSET - -//* ---------------------------------------------------------------------------- -//* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR -//* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF -//* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE -//* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, -//* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -//* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, -//* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF -//* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING -//* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, -//* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -//* ---------------------------------------------------------------------------- -//* File Name : lib_AT91SAM7X256.h -//* Object : AT91SAM7X256 inlined functions -//* Generated : AT91 SW Application Group 05/20/2005 (16:22:29) -//* -//* CVS Reference : /lib_dbgu.h/1.1/Fri Jan 31 12:18:40 2003// -//* CVS Reference : /lib_pmc_SAM7X.h/1.1/Tue Feb 1 08:32:10 2005// -//* CVS Reference : /lib_VREG_6085B.h/1.1/Tue Feb 1 16:20:47 2005// -//* CVS Reference : /lib_rstc_6098A.h/1.1/Wed Oct 6 10:39:20 2004// -//* CVS Reference : /lib_ssc.h/1.4/Fri Jan 31 12:19:20 2003// -//* CVS Reference : /lib_wdtc_6080A.h/1.1/Wed Oct 6 10:38:30 2004// -//* CVS Reference : /lib_usart.h/1.5/Thu Nov 21 16:01:54 2002// -//* CVS Reference : /lib_spi2.h/1.1/Mon Aug 25 14:23:52 2003// -//* CVS Reference : /lib_pitc_6079A.h/1.2/Tue Nov 9 14:43:56 2004// -//* CVS Reference : /lib_aic_6075b.h/1.1/Fri May 20 14:01:19 2005// -//* CVS Reference : /lib_aes_6149a.h/1.1/Mon Jan 17 07:43:09 2005// -//* CVS Reference : /lib_twi.h/1.3/Mon Jul 19 14:27:58 2004// -//* CVS Reference : /lib_adc.h/1.6/Fri Oct 17 09:12:38 2003// -//* CVS Reference : /lib_rttc_6081A.h/1.1/Wed Oct 6 10:39:38 2004// -//* CVS Reference : /lib_udp.h/1.4/Wed Feb 16 08:39:34 2005// -//* CVS Reference : /lib_des3_6150a.h/1.1/Mon Jan 17 09:19:19 2005// -//* CVS Reference : /lib_tc_1753b.h/1.1/Fri Jan 31 12:20:02 2003// -//* CVS Reference : /lib_MC_SAM7X.h/1.1/Thu Mar 25 15:19:14 2004// -//* CVS Reference : /lib_pio.h/1.3/Fri Jan 31 12:18:56 2003// -//* CVS Reference : /lib_can_AT91.h/1.4/Fri Oct 17 09:12:50 2003// -//* CVS Reference : /lib_PWM_SAM.h/1.3/Thu Jan 22 10:10:50 2004// -//* CVS Reference : /lib_pdc.h/1.2/Tue Jul 2 13:29:40 2002// -//* ---------------------------------------------------------------------------- +/** ---------------------------------------------------------------------------- */ +/** ATMEL Microcontroller Software Support - ROUSSET - */ +/** ---------------------------------------------------------------------------- */ +/** DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/** IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/** MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/** DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/** INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/** LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/** OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/** LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/** NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/** EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/** ---------------------------------------------------------------------------- */ +/** File Name : lib_AT91SAM7X256.h */ +/** Object : AT91SAM7X256 inlined functions */ +/** Generated : AT91 SW Application Group 05/20/2005 (16:22:29) */ +/** */ +/** CVS Reference : /lib_dbgu.h/1.1/Fri Jan 31 12:18:40 2003// */ +/** CVS Reference : /lib_pmc_SAM7X.h/1.1/Tue Feb 1 08:32:10 2005// */ +/** CVS Reference : /lib_VREG_6085B.h/1.1/Tue Feb 1 16:20:47 2005// */ +/** CVS Reference : /lib_rstc_6098A.h/1.1/Wed Oct 6 10:39:20 2004// */ +/** CVS Reference : /lib_ssc.h/1.4/Fri Jan 31 12:19:20 2003// */ +/** CVS Reference : /lib_wdtc_6080A.h/1.1/Wed Oct 6 10:38:30 2004// */ +/** CVS Reference : /lib_usart.h/1.5/Thu Nov 21 16:01:54 2002// */ +/** CVS Reference : /lib_spi2.h/1.1/Mon Aug 25 14:23:52 2003// */ +/** CVS Reference : /lib_pitc_6079A.h/1.2/Tue Nov 9 14:43:56 2004// */ +/** CVS Reference : /lib_aic_6075b.h/1.1/Fri May 20 14:01:19 2005// */ +/** CVS Reference : /lib_aes_6149a.h/1.1/Mon Jan 17 07:43:09 2005// */ +/** CVS Reference : /lib_twi.h/1.3/Mon Jul 19 14:27:58 2004// */ +/** CVS Reference : /lib_adc.h/1.6/Fri Oct 17 09:12:38 2003// */ +/** CVS Reference : /lib_rttc_6081A.h/1.1/Wed Oct 6 10:39:38 2004// */ +/** CVS Reference : /lib_udp.h/1.4/Wed Feb 16 08:39:34 2005// */ +/** CVS Reference : /lib_des3_6150a.h/1.1/Mon Jan 17 09:19:19 2005// */ +/** CVS Reference : /lib_tc_1753b.h/1.1/Fri Jan 31 12:20:02 2003// */ +/** CVS Reference : /lib_MC_SAM7X.h/1.1/Thu Mar 25 15:19:14 2004// */ +/** CVS Reference : /lib_pio.h/1.3/Fri Jan 31 12:18:56 2003// */ +/** CVS Reference : /lib_can_AT91.h/1.4/Fri Oct 17 09:12:50 2003// */ +/** CVS Reference : /lib_PWM_SAM.h/1.3/Thu Jan 22 10:10:50 2004// */ +/** CVS Reference : /lib_pdc.h/1.2/Tue Jul 2 13:29:40 2002// */ +/** ---------------------------------------------------------------------------- */ #ifndef lib_AT91SAM7X256_H -#define lib_AT91SAM7X256_H + #define lib_AT91SAM7X256_H /* ***************************************************************************** - SOFTWARE API FOR AIC - ***************************************************************************** */ -#define AT91C_AIC_BRANCH_OPCODE ((void (*) ()) 0xE51FFF20) // ldr, pc, [pc, #-&F20] - -//*---------------------------------------------------------------------------- -//* \fn AT91F_AIC_ConfigureIt -//* \brief Interrupt Handler Initialization -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_AIC_ConfigureIt ( - AT91PS_AIC pAic, // \arg pointer to the AIC registers - unsigned int irq_id, // \arg interrupt number to initialize - unsigned int priority, // \arg priority to give to the interrupt - unsigned int src_type, // \arg activation and sense of activation - void (*newHandler) (void) ) // \arg address of the interrupt handler -{ - unsigned int oldHandler; - unsigned int mask ; - - oldHandler = pAic->AIC_SVR[irq_id]; - - mask = 0x1 << irq_id ; - //* Disable the interrupt on the interrupt controller - pAic->AIC_IDCR = mask ; - //* Save the interrupt handler routine pointer and the interrupt priority - pAic->AIC_SVR[irq_id] = (unsigned int) newHandler ; - //* Store the Source Mode Register - pAic->AIC_SMR[irq_id] = src_type | priority ; - //* Clear the interrupt on the interrupt controller - pAic->AIC_ICCR = mask ; - - return oldHandler; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_AIC_EnableIt -//* \brief Enable corresponding IT number -//*---------------------------------------------------------------------------- -__inline void AT91F_AIC_EnableIt ( - AT91PS_AIC pAic, // \arg pointer to the AIC registers - unsigned int irq_id ) // \arg interrupt number to initialize -{ - //* Enable the interrupt on the interrupt controller - pAic->AIC_IECR = 0x1 << irq_id ; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_AIC_DisableIt -//* \brief Disable corresponding IT number -//*---------------------------------------------------------------------------- -__inline void AT91F_AIC_DisableIt ( - AT91PS_AIC pAic, // \arg pointer to the AIC registers - unsigned int irq_id ) // \arg interrupt number to initialize -{ - unsigned int mask = 0x1 << irq_id; - //* Disable the interrupt on the interrupt controller - pAic->AIC_IDCR = mask ; - //* Clear the interrupt on the Interrupt Controller ( if one is pending ) - pAic->AIC_ICCR = mask ; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_AIC_ClearIt -//* \brief Clear corresponding IT number -//*---------------------------------------------------------------------------- -__inline void AT91F_AIC_ClearIt ( - AT91PS_AIC pAic, // \arg pointer to the AIC registers - unsigned int irq_id) // \arg interrupt number to initialize -{ - //* Clear the interrupt on the Interrupt Controller ( if one is pending ) - pAic->AIC_ICCR = (0x1 << irq_id); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_AIC_AcknowledgeIt -//* \brief Acknowledge corresponding IT number -//*---------------------------------------------------------------------------- -__inline void AT91F_AIC_AcknowledgeIt ( - AT91PS_AIC pAic) // \arg pointer to the AIC registers -{ - pAic->AIC_EOICR = pAic->AIC_EOICR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_AIC_SetExceptionVector -//* \brief Configure vector handler -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_AIC_SetExceptionVector ( - unsigned int *pVector, // \arg pointer to the AIC registers - void (*Handler) () ) // \arg Interrupt Handler -{ - unsigned int oldVector = *pVector; - - if ((unsigned int) Handler == (unsigned int) AT91C_AIC_BRANCH_OPCODE) - *pVector = (unsigned int) AT91C_AIC_BRANCH_OPCODE; - else - *pVector = (((((unsigned int) Handler) - ((unsigned int) pVector) - 0x8) >> 2) & 0x00FFFFFF) | 0xEA000000; - - return oldVector; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_AIC_Trig -//* \brief Trig an IT -//*---------------------------------------------------------------------------- -__inline void AT91F_AIC_Trig ( - AT91PS_AIC pAic, // \arg pointer to the AIC registers - unsigned int irq_id) // \arg interrupt number -{ - pAic->AIC_ISCR = (0x1 << irq_id) ; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_AIC_IsActive -//* \brief Test if an IT is active -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_AIC_IsActive ( - AT91PS_AIC pAic, // \arg pointer to the AIC registers - unsigned int irq_id) // \arg Interrupt Number -{ - return (pAic->AIC_ISR & (0x1 << irq_id)); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_AIC_IsPending -//* \brief Test if an IT is pending -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_AIC_IsPending ( - AT91PS_AIC pAic, // \arg pointer to the AIC registers - unsigned int irq_id) // \arg Interrupt Number -{ - return (pAic->AIC_IPR & (0x1 << irq_id)); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_AIC_Open -//* \brief Set exception vectors and AIC registers to default values -//*---------------------------------------------------------------------------- -__inline void AT91F_AIC_Open( - AT91PS_AIC pAic, // \arg pointer to the AIC registers - void (*IrqHandler) (), // \arg Default IRQ vector exception - void (*FiqHandler) (), // \arg Default FIQ vector exception - void (*DefaultHandler) (), // \arg Default Handler set in ISR - void (*SpuriousHandler) (), // \arg Default Spurious Handler - unsigned int protectMode) // \arg Debug Control Register -{ - int i; - - // Disable all interrupts and set IVR to the default handler - for (i = 0; i < 32; ++i) { - AT91F_AIC_DisableIt(pAic, i); - AT91F_AIC_ConfigureIt(pAic, i, AT91C_AIC_PRIOR_LOWEST, AT91C_AIC_SRCTYPE_HIGH_LEVEL, DefaultHandler); - } - - // Set the IRQ exception vector - AT91F_AIC_SetExceptionVector((unsigned int *) 0x18, IrqHandler); - // Set the Fast Interrupt exception vector - AT91F_AIC_SetExceptionVector((unsigned int *) 0x1C, FiqHandler); - - pAic->AIC_SPU = (unsigned int) SpuriousHandler; - pAic->AIC_DCR = protectMode; -} +* SOFTWARE API FOR AIC +***************************************************************************** */ + #define AT91C_AIC_BRANCH_OPCODE ( ( void ( * )() ) 0xE51FFF20 ) /* ldr, pc, [pc, #-&F20] */ + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_AIC_ConfigureIt */ +/** \brief Interrupt Handler Initialization */ +/**---------------------------------------------------------------------------- */ + __inline unsigned int AT91F_AIC_ConfigureIt( AT91PS_AIC pAic, /* \arg pointer to the AIC registers */ + unsigned int irq_id, /* \arg interrupt number to initialize */ + unsigned int priority, /* \arg priority to give to the interrupt */ + unsigned int src_type, /* \arg activation and sense of activation */ + void ( * newHandler )( void ) ) /* \arg address of the interrupt handler */ + { + unsigned int oldHandler; + unsigned int mask; + + oldHandler = pAic->AIC_SVR[ irq_id ]; + + mask = 0x1 << irq_id; + /** Disable the interrupt on the interrupt controller */ + pAic->AIC_IDCR = mask; + /** Save the interrupt handler routine pointer and the interrupt priority */ + pAic->AIC_SVR[ irq_id ] = ( unsigned int ) newHandler; + /** Store the Source Mode Register */ + pAic->AIC_SMR[ irq_id ] = src_type | priority; + /** Clear the interrupt on the interrupt controller */ + pAic->AIC_ICCR = mask; + + return oldHandler; + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_AIC_EnableIt */ +/** \brief Enable corresponding IT number */ +/**---------------------------------------------------------------------------- */ + __inline void AT91F_AIC_EnableIt( AT91PS_AIC pAic, /* \arg pointer to the AIC registers */ + unsigned int irq_id ) /* \arg interrupt number to initialize */ + { + /** Enable the interrupt on the interrupt controller */ + pAic->AIC_IECR = 0x1 << irq_id; + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_AIC_DisableIt */ +/** \brief Disable corresponding IT number */ +/**---------------------------------------------------------------------------- */ + __inline void AT91F_AIC_DisableIt( AT91PS_AIC pAic, /* \arg pointer to the AIC registers */ + unsigned int irq_id ) /* \arg interrupt number to initialize */ + { + unsigned int mask = 0x1 << irq_id; + + /** Disable the interrupt on the interrupt controller */ + pAic->AIC_IDCR = mask; + /** Clear the interrupt on the Interrupt Controller ( if one is pending ) */ + pAic->AIC_ICCR = mask; + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_AIC_ClearIt */ +/** \brief Clear corresponding IT number */ +/**---------------------------------------------------------------------------- */ + __inline void AT91F_AIC_ClearIt( AT91PS_AIC pAic, /* \arg pointer to the AIC registers */ + unsigned int irq_id ) /* \arg interrupt number to initialize */ + { + /** Clear the interrupt on the Interrupt Controller ( if one is pending ) */ + pAic->AIC_ICCR = ( 0x1 << irq_id ); + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_AIC_AcknowledgeIt */ +/** \brief Acknowledge corresponding IT number */ +/**---------------------------------------------------------------------------- */ + __inline void AT91F_AIC_AcknowledgeIt( AT91PS_AIC pAic ) /* \arg pointer to the AIC registers */ + { + pAic->AIC_EOICR = pAic->AIC_EOICR; + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_AIC_SetExceptionVector */ +/** \brief Configure vector handler */ +/**---------------------------------------------------------------------------- */ + __inline unsigned int AT91F_AIC_SetExceptionVector( unsigned int * pVector, /* \arg pointer to the AIC registers */ + void ( * Handler )() ) /* \arg Interrupt Handler */ + { + unsigned int oldVector = *pVector; + + if( ( unsigned int ) Handler == ( unsigned int ) AT91C_AIC_BRANCH_OPCODE ) + { + *pVector = ( unsigned int ) AT91C_AIC_BRANCH_OPCODE; + } + else + { + *pVector = ( ( ( ( ( unsigned int ) Handler ) - ( ( unsigned int ) pVector ) - 0x8 ) >> 2 ) & 0x00FFFFFF ) | 0xEA000000; + } + + return oldVector; + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_AIC_Trig */ +/** \brief Trig an IT */ +/**---------------------------------------------------------------------------- */ + __inline void AT91F_AIC_Trig( AT91PS_AIC pAic, /* \arg pointer to the AIC registers */ + unsigned int irq_id ) /* \arg interrupt number */ + { + pAic->AIC_ISCR = ( 0x1 << irq_id ); + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_AIC_IsActive */ +/** \brief Test if an IT is active */ +/**---------------------------------------------------------------------------- */ + __inline unsigned int AT91F_AIC_IsActive( AT91PS_AIC pAic, /* \arg pointer to the AIC registers */ + unsigned int irq_id ) /* \arg Interrupt Number */ + { + return( pAic->AIC_ISR & ( 0x1 << irq_id ) ); + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_AIC_IsPending */ +/** \brief Test if an IT is pending */ +/**---------------------------------------------------------------------------- */ + __inline unsigned int AT91F_AIC_IsPending( AT91PS_AIC pAic, /* \arg pointer to the AIC registers */ + unsigned int irq_id ) /* \arg Interrupt Number */ + { + return( pAic->AIC_IPR & ( 0x1 << irq_id ) ); + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_AIC_Open */ +/** \brief Set exception vectors and AIC registers to default values */ +/**---------------------------------------------------------------------------- */ + __inline void AT91F_AIC_Open( AT91PS_AIC pAic, /* \arg pointer to the AIC registers */ + void ( * IrqHandler )(), /* \arg Default IRQ vector exception */ + void ( * FiqHandler )(), /* \arg Default FIQ vector exception */ + void ( * DefaultHandler )(), /* \arg Default Handler set in ISR */ + void ( * SpuriousHandler )(), /* \arg Default Spurious Handler */ + unsigned int protectMode ) /* \arg Debug Control Register */ + { + int i; + + /* Disable all interrupts and set IVR to the default handler */ + for( i = 0; i < 32; ++i ) + { + AT91F_AIC_DisableIt( pAic, i ); + AT91F_AIC_ConfigureIt( pAic, i, AT91C_AIC_PRIOR_LOWEST, AT91C_AIC_SRCTYPE_HIGH_LEVEL, DefaultHandler ); + } + + /* Set the IRQ exception vector */ + AT91F_AIC_SetExceptionVector( ( unsigned int * ) 0x18, IrqHandler ); + /* Set the Fast Interrupt exception vector */ + AT91F_AIC_SetExceptionVector( ( unsigned int * ) 0x1C, FiqHandler ); + + pAic->AIC_SPU = ( unsigned int ) SpuriousHandler; + pAic->AIC_DCR = protectMode; + } + /* ***************************************************************************** - SOFTWARE API FOR PDC - ***************************************************************************** */ -//*---------------------------------------------------------------------------- -//* \fn AT91F_PDC_SetNextRx -//* \brief Set the next receive transfer descriptor -//*---------------------------------------------------------------------------- -__inline void AT91F_PDC_SetNextRx ( - AT91PS_PDC pPDC, // \arg pointer to a PDC controller - char *address, // \arg address to the next bloc to be received - unsigned int bytes) // \arg number of bytes to be received -{ - pPDC->PDC_RNPR = (unsigned int) address; - pPDC->PDC_RNCR = bytes; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PDC_SetNextTx -//* \brief Set the next transmit transfer descriptor -//*---------------------------------------------------------------------------- -__inline void AT91F_PDC_SetNextTx ( - AT91PS_PDC pPDC, // \arg pointer to a PDC controller - char *address, // \arg address to the next bloc to be transmitted - unsigned int bytes) // \arg number of bytes to be transmitted -{ - pPDC->PDC_TNPR = (unsigned int) address; - pPDC->PDC_TNCR = bytes; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PDC_SetRx -//* \brief Set the receive transfer descriptor -//*---------------------------------------------------------------------------- -__inline void AT91F_PDC_SetRx ( - AT91PS_PDC pPDC, // \arg pointer to a PDC controller - char *address, // \arg address to the next bloc to be received - unsigned int bytes) // \arg number of bytes to be received -{ - pPDC->PDC_RPR = (unsigned int) address; - pPDC->PDC_RCR = bytes; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PDC_SetTx -//* \brief Set the transmit transfer descriptor -//*---------------------------------------------------------------------------- -__inline void AT91F_PDC_SetTx ( - AT91PS_PDC pPDC, // \arg pointer to a PDC controller - char *address, // \arg address to the next bloc to be transmitted - unsigned int bytes) // \arg number of bytes to be transmitted -{ - pPDC->PDC_TPR = (unsigned int) address; - pPDC->PDC_TCR = bytes; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PDC_EnableTx -//* \brief Enable transmit -//*---------------------------------------------------------------------------- -__inline void AT91F_PDC_EnableTx ( - AT91PS_PDC pPDC ) // \arg pointer to a PDC controller -{ - pPDC->PDC_PTCR = AT91C_PDC_TXTEN; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PDC_EnableRx -//* \brief Enable receive -//*---------------------------------------------------------------------------- -__inline void AT91F_PDC_EnableRx ( - AT91PS_PDC pPDC ) // \arg pointer to a PDC controller -{ - pPDC->PDC_PTCR = AT91C_PDC_RXTEN; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PDC_DisableTx -//* \brief Disable transmit -//*---------------------------------------------------------------------------- -__inline void AT91F_PDC_DisableTx ( - AT91PS_PDC pPDC ) // \arg pointer to a PDC controller -{ - pPDC->PDC_PTCR = AT91C_PDC_TXTDIS; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PDC_DisableRx -//* \brief Disable receive -//*---------------------------------------------------------------------------- -__inline void AT91F_PDC_DisableRx ( - AT91PS_PDC pPDC ) // \arg pointer to a PDC controller -{ - pPDC->PDC_PTCR = AT91C_PDC_RXTDIS; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PDC_IsTxEmpty -//* \brief Test if the current transfer descriptor has been sent -//*---------------------------------------------------------------------------- -__inline int AT91F_PDC_IsTxEmpty ( // \return return 1 if transfer is complete - AT91PS_PDC pPDC ) // \arg pointer to a PDC controller -{ - return !(pPDC->PDC_TCR); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PDC_IsNextTxEmpty -//* \brief Test if the next transfer descriptor has been moved to the current td -//*---------------------------------------------------------------------------- -__inline int AT91F_PDC_IsNextTxEmpty ( // \return return 1 if transfer is complete - AT91PS_PDC pPDC ) // \arg pointer to a PDC controller -{ - return !(pPDC->PDC_TNCR); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PDC_IsRxEmpty -//* \brief Test if the current transfer descriptor has been filled -//*---------------------------------------------------------------------------- -__inline int AT91F_PDC_IsRxEmpty ( // \return return 1 if transfer is complete - AT91PS_PDC pPDC ) // \arg pointer to a PDC controller -{ - return !(pPDC->PDC_RCR); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PDC_IsNextRxEmpty -//* \brief Test if the next transfer descriptor has been moved to the current td -//*---------------------------------------------------------------------------- -__inline int AT91F_PDC_IsNextRxEmpty ( // \return return 1 if transfer is complete - AT91PS_PDC pPDC ) // \arg pointer to a PDC controller -{ - return !(pPDC->PDC_RNCR); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PDC_Open -//* \brief Open PDC: disable TX and RX reset transfer descriptors, re-enable RX and TX -//*---------------------------------------------------------------------------- -__inline void AT91F_PDC_Open ( - AT91PS_PDC pPDC) // \arg pointer to a PDC controller -{ - //* Disable the RX and TX PDC transfer requests - AT91F_PDC_DisableRx(pPDC); - AT91F_PDC_DisableTx(pPDC); - - //* Reset all Counter register Next buffer first - AT91F_PDC_SetNextTx(pPDC, (char *) 0, 0); - AT91F_PDC_SetNextRx(pPDC, (char *) 0, 0); - AT91F_PDC_SetTx(pPDC, (char *) 0, 0); - AT91F_PDC_SetRx(pPDC, (char *) 0, 0); - - //* Enable the RX and TX PDC transfer requests - AT91F_PDC_EnableRx(pPDC); - AT91F_PDC_EnableTx(pPDC); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PDC_Close -//* \brief Close PDC: disable TX and RX reset transfer descriptors -//*---------------------------------------------------------------------------- -__inline void AT91F_PDC_Close ( - AT91PS_PDC pPDC) // \arg pointer to a PDC controller -{ - //* Disable the RX and TX PDC transfer requests - AT91F_PDC_DisableRx(pPDC); - AT91F_PDC_DisableTx(pPDC); - - //* Reset all Counter register Next buffer first - AT91F_PDC_SetNextTx(pPDC, (char *) 0, 0); - AT91F_PDC_SetNextRx(pPDC, (char *) 0, 0); - AT91F_PDC_SetTx(pPDC, (char *) 0, 0); - AT91F_PDC_SetRx(pPDC, (char *) 0, 0); - -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PDC_SendFrame -//* \brief Close PDC: disable TX and RX reset transfer descriptors -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_PDC_SendFrame( - AT91PS_PDC pPDC, - char *pBuffer, - unsigned int szBuffer, - char *pNextBuffer, - unsigned int szNextBuffer ) -{ - if (AT91F_PDC_IsTxEmpty(pPDC)) { - //* Buffer and next buffer can be initialized - AT91F_PDC_SetTx(pPDC, pBuffer, szBuffer); - AT91F_PDC_SetNextTx(pPDC, pNextBuffer, szNextBuffer); - return 2; - } - else if (AT91F_PDC_IsNextTxEmpty(pPDC)) { - //* Only one buffer can be initialized - AT91F_PDC_SetNextTx(pPDC, pBuffer, szBuffer); - return 1; - } - else { - //* All buffer are in use... - return 0; +* SOFTWARE API FOR PDC +***************************************************************************** */ +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PDC_SetNextRx */ +/** \brief Set the next receive transfer descriptor */ +/**---------------------------------------------------------------------------- */ + __inline void AT91F_PDC_SetNextRx( AT91PS_PDC pPDC, /* \arg pointer to a PDC controller */ + char * address, /* \arg address to the next bloc to be received */ + unsigned int bytes ) /* \arg number of bytes to be received */ + { + pPDC->PDC_RNPR = ( unsigned int ) address; + pPDC->PDC_RNCR = bytes; } -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PDC_ReceiveFrame -//* \brief Close PDC: disable TX and RX reset transfer descriptors -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_PDC_ReceiveFrame ( - AT91PS_PDC pPDC, - char *pBuffer, - unsigned int szBuffer, - char *pNextBuffer, - unsigned int szNextBuffer ) -{ - if (AT91F_PDC_IsRxEmpty(pPDC)) { - //* Buffer and next buffer can be initialized - AT91F_PDC_SetRx(pPDC, pBuffer, szBuffer); - AT91F_PDC_SetNextRx(pPDC, pNextBuffer, szNextBuffer); - return 2; - } - else if (AT91F_PDC_IsNextRxEmpty(pPDC)) { - //* Only one buffer can be initialized - AT91F_PDC_SetNextRx(pPDC, pBuffer, szBuffer); - return 1; - } - else { - //* All buffer are in use... - return 0; + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PDC_SetNextTx */ +/** \brief Set the next transmit transfer descriptor */ +/**---------------------------------------------------------------------------- */ + __inline void AT91F_PDC_SetNextTx( AT91PS_PDC pPDC, /* \arg pointer to a PDC controller */ + char * address, /* \arg address to the next bloc to be transmitted */ + unsigned int bytes ) /* \arg number of bytes to be transmitted */ + { + pPDC->PDC_TNPR = ( unsigned int ) address; + pPDC->PDC_TNCR = bytes; + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PDC_SetRx */ +/** \brief Set the receive transfer descriptor */ +/**---------------------------------------------------------------------------- */ + __inline void AT91F_PDC_SetRx( AT91PS_PDC pPDC, /* \arg pointer to a PDC controller */ + char * address, /* \arg address to the next bloc to be received */ + unsigned int bytes ) /* \arg number of bytes to be received */ + { + pPDC->PDC_RPR = ( unsigned int ) address; + pPDC->PDC_RCR = bytes; + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PDC_SetTx */ +/** \brief Set the transmit transfer descriptor */ +/**---------------------------------------------------------------------------- */ + __inline void AT91F_PDC_SetTx( AT91PS_PDC pPDC, /* \arg pointer to a PDC controller */ + char * address, /* \arg address to the next bloc to be transmitted */ + unsigned int bytes ) /* \arg number of bytes to be transmitted */ + { + pPDC->PDC_TPR = ( unsigned int ) address; + pPDC->PDC_TCR = bytes; + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PDC_EnableTx */ +/** \brief Enable transmit */ +/**---------------------------------------------------------------------------- */ + __inline void AT91F_PDC_EnableTx( AT91PS_PDC pPDC ) /* \arg pointer to a PDC controller */ + { + pPDC->PDC_PTCR = AT91C_PDC_TXTEN; } -} + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PDC_EnableRx */ +/** \brief Enable receive */ +/**---------------------------------------------------------------------------- */ + __inline void AT91F_PDC_EnableRx( AT91PS_PDC pPDC ) /* \arg pointer to a PDC controller */ + { + pPDC->PDC_PTCR = AT91C_PDC_RXTEN; + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PDC_DisableTx */ +/** \brief Disable transmit */ +/**---------------------------------------------------------------------------- */ + __inline void AT91F_PDC_DisableTx( AT91PS_PDC pPDC ) /* \arg pointer to a PDC controller */ + { + pPDC->PDC_PTCR = AT91C_PDC_TXTDIS; + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PDC_DisableRx */ +/** \brief Disable receive */ +/**---------------------------------------------------------------------------- */ + __inline void AT91F_PDC_DisableRx( AT91PS_PDC pPDC ) /* \arg pointer to a PDC controller */ + { + pPDC->PDC_PTCR = AT91C_PDC_RXTDIS; + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PDC_IsTxEmpty */ +/** \brief Test if the current transfer descriptor has been sent */ +/**---------------------------------------------------------------------------- */ + __inline int AT91F_PDC_IsTxEmpty( /* \return return 1 if transfer is complete */ + AT91PS_PDC pPDC ) /* \arg pointer to a PDC controller */ + { + return !( pPDC->PDC_TCR ); + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PDC_IsNextTxEmpty */ +/** \brief Test if the next transfer descriptor has been moved to the current td */ +/**---------------------------------------------------------------------------- */ + __inline int AT91F_PDC_IsNextTxEmpty( /* \return return 1 if transfer is complete */ + AT91PS_PDC pPDC ) /* \arg pointer to a PDC controller */ + { + return !( pPDC->PDC_TNCR ); + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PDC_IsRxEmpty */ +/** \brief Test if the current transfer descriptor has been filled */ +/**---------------------------------------------------------------------------- */ + __inline int AT91F_PDC_IsRxEmpty( /* \return return 1 if transfer is complete */ + AT91PS_PDC pPDC ) /* \arg pointer to a PDC controller */ + { + return !( pPDC->PDC_RCR ); + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PDC_IsNextRxEmpty */ +/** \brief Test if the next transfer descriptor has been moved to the current td */ +/**---------------------------------------------------------------------------- */ + __inline int AT91F_PDC_IsNextRxEmpty( /* \return return 1 if transfer is complete */ + AT91PS_PDC pPDC ) /* \arg pointer to a PDC controller */ + { + return !( pPDC->PDC_RNCR ); + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PDC_Open */ +/** \brief Open PDC: disable TX and RX reset transfer descriptors, re-enable RX and TX */ +/**---------------------------------------------------------------------------- */ + __inline void AT91F_PDC_Open( AT91PS_PDC pPDC ) /* \arg pointer to a PDC controller */ + { + /** Disable the RX and TX PDC transfer requests */ + AT91F_PDC_DisableRx( pPDC ); + AT91F_PDC_DisableTx( pPDC ); + + /** Reset all Counter register Next buffer first */ + AT91F_PDC_SetNextTx( pPDC, ( char * ) 0, 0 ); + AT91F_PDC_SetNextRx( pPDC, ( char * ) 0, 0 ); + AT91F_PDC_SetTx( pPDC, ( char * ) 0, 0 ); + AT91F_PDC_SetRx( pPDC, ( char * ) 0, 0 ); + + /** Enable the RX and TX PDC transfer requests */ + AT91F_PDC_EnableRx( pPDC ); + AT91F_PDC_EnableTx( pPDC ); + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PDC_Close */ +/** \brief Close PDC: disable TX and RX reset transfer descriptors */ +/**---------------------------------------------------------------------------- */ + __inline void AT91F_PDC_Close( AT91PS_PDC pPDC ) /* \arg pointer to a PDC controller */ + { + /** Disable the RX and TX PDC transfer requests */ + AT91F_PDC_DisableRx( pPDC ); + AT91F_PDC_DisableTx( pPDC ); + + /** Reset all Counter register Next buffer first */ + AT91F_PDC_SetNextTx( pPDC, ( char * ) 0, 0 ); + AT91F_PDC_SetNextRx( pPDC, ( char * ) 0, 0 ); + AT91F_PDC_SetTx( pPDC, ( char * ) 0, 0 ); + AT91F_PDC_SetRx( pPDC, ( char * ) 0, 0 ); + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PDC_SendFrame */ +/** \brief Close PDC: disable TX and RX reset transfer descriptors */ +/**---------------------------------------------------------------------------- */ + __inline unsigned int AT91F_PDC_SendFrame( AT91PS_PDC pPDC, + char * pBuffer, + unsigned int szBuffer, + char * pNextBuffer, + unsigned int szNextBuffer ) + { + if( AT91F_PDC_IsTxEmpty( pPDC ) ) + { + /** Buffer and next buffer can be initialized */ + AT91F_PDC_SetTx( pPDC, pBuffer, szBuffer ); + AT91F_PDC_SetNextTx( pPDC, pNextBuffer, szNextBuffer ); + return 2; + } + else if( AT91F_PDC_IsNextTxEmpty( pPDC ) ) + { + /** Only one buffer can be initialized */ + AT91F_PDC_SetNextTx( pPDC, pBuffer, szBuffer ); + return 1; + } + else + { + /** All buffer are in use... */ + return 0; + } + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PDC_ReceiveFrame */ +/** \brief Close PDC: disable TX and RX reset transfer descriptors */ +/**---------------------------------------------------------------------------- */ + __inline unsigned int AT91F_PDC_ReceiveFrame( AT91PS_PDC pPDC, + char * pBuffer, + unsigned int szBuffer, + char * pNextBuffer, + unsigned int szNextBuffer ) + { + if( AT91F_PDC_IsRxEmpty( pPDC ) ) + { + /** Buffer and next buffer can be initialized */ + AT91F_PDC_SetRx( pPDC, pBuffer, szBuffer ); + AT91F_PDC_SetNextRx( pPDC, pNextBuffer, szNextBuffer ); + return 2; + } + else if( AT91F_PDC_IsNextRxEmpty( pPDC ) ) + { + /** Only one buffer can be initialized */ + AT91F_PDC_SetNextRx( pPDC, pBuffer, szBuffer ); + return 1; + } + else + { + /** All buffer are in use... */ + return 0; + } + } + /* ***************************************************************************** - SOFTWARE API FOR DBGU - ***************************************************************************** */ -//*---------------------------------------------------------------------------- -//* \fn AT91F_DBGU_InterruptEnable -//* \brief Enable DBGU Interrupt -//*---------------------------------------------------------------------------- -__inline void AT91F_DBGU_InterruptEnable( - AT91PS_DBGU pDbgu, // \arg pointer to a DBGU controller - unsigned int flag) // \arg dbgu interrupt to be enabled -{ +* SOFTWARE API FOR DBGU +***************************************************************************** */ +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_DBGU_InterruptEnable */ +/** \brief Enable DBGU Interrupt */ +/**---------------------------------------------------------------------------- */ + __inline void AT91F_DBGU_InterruptEnable( AT91PS_DBGU pDbgu, /* \arg pointer to a DBGU controller */ + unsigned int flag ) /* \arg dbgu interrupt to be enabled */ + { pDbgu->DBGU_IER = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_DBGU_InterruptDisable -//* \brief Disable DBGU Interrupt -//*---------------------------------------------------------------------------- -__inline void AT91F_DBGU_InterruptDisable( - AT91PS_DBGU pDbgu, // \arg pointer to a DBGU controller - unsigned int flag) // \arg dbgu interrupt to be disabled -{ + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_DBGU_InterruptDisable */ +/** \brief Disable DBGU Interrupt */ +/**---------------------------------------------------------------------------- */ + __inline void AT91F_DBGU_InterruptDisable( AT91PS_DBGU pDbgu, /* \arg pointer to a DBGU controller */ + unsigned int flag ) /* \arg dbgu interrupt to be disabled */ + { pDbgu->DBGU_IDR = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_DBGU_GetInterruptMaskStatus -//* \brief Return DBGU Interrupt Mask Status -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_DBGU_GetInterruptMaskStatus( // \return DBGU Interrupt Mask Status - AT91PS_DBGU pDbgu) // \arg pointer to a DBGU controller -{ + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_DBGU_GetInterruptMaskStatus */ +/** \brief Return DBGU Interrupt Mask Status */ +/**---------------------------------------------------------------------------- */ + __inline unsigned int AT91F_DBGU_GetInterruptMaskStatus( /* \return DBGU Interrupt Mask Status */ + AT91PS_DBGU pDbgu ) /* \arg pointer to a DBGU controller */ + { return pDbgu->DBGU_IMR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_DBGU_IsInterruptMasked -//* \brief Test if DBGU Interrupt is Masked -//*---------------------------------------------------------------------------- -__inline int AT91F_DBGU_IsInterruptMasked( - AT91PS_DBGU pDbgu, // \arg pointer to a DBGU controller - unsigned int flag) // \arg flag to be tested -{ - return (AT91F_DBGU_GetInterruptMaskStatus(pDbgu) & flag); -} + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_DBGU_IsInterruptMasked */ +/** \brief Test if DBGU Interrupt is Masked */ +/**---------------------------------------------------------------------------- */ + __inline int AT91F_DBGU_IsInterruptMasked( AT91PS_DBGU pDbgu, /* \arg pointer to a DBGU controller */ + unsigned int flag ) /* \arg flag to be tested */ + { + return( AT91F_DBGU_GetInterruptMaskStatus( pDbgu ) & flag ); + } /* ***************************************************************************** - SOFTWARE API FOR PIO - ***************************************************************************** */ -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_CfgPeriph -//* \brief Enable pins to be drived by peripheral -//*---------------------------------------------------------------------------- -__inline void AT91F_PIO_CfgPeriph( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int periphAEnable, // \arg PERIPH A to enable - unsigned int periphBEnable) // \arg PERIPH B to enable - -{ - pPio->PIO_ASR = periphAEnable; - pPio->PIO_BSR = periphBEnable; - pPio->PIO_PDR = (periphAEnable | periphBEnable); // Set in Periph mode -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_CfgOutput -//* \brief Enable PIO in output mode -//*---------------------------------------------------------------------------- -__inline void AT91F_PIO_CfgOutput( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int pioEnable) // \arg PIO to be enabled -{ - pPio->PIO_PER = pioEnable; // Set in PIO mode - pPio->PIO_OER = pioEnable; // Configure in Output -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_CfgInput -//* \brief Enable PIO in input mode -//*---------------------------------------------------------------------------- -__inline void AT91F_PIO_CfgInput( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int inputEnable) // \arg PIO to be enabled -{ - // Disable output - pPio->PIO_ODR = inputEnable; - pPio->PIO_PER = inputEnable; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_CfgOpendrain -//* \brief Configure PIO in open drain -//*---------------------------------------------------------------------------- -__inline void AT91F_PIO_CfgOpendrain( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int multiDrvEnable) // \arg pio to be configured in open drain -{ - // Configure the multi-drive option - pPio->PIO_MDDR = ~multiDrvEnable; - pPio->PIO_MDER = multiDrvEnable; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_CfgPullup -//* \brief Enable pullup on PIO -//*---------------------------------------------------------------------------- -__inline void AT91F_PIO_CfgPullup( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int pullupEnable) // \arg enable pullup on PIO -{ - // Connect or not Pullup - pPio->PIO_PPUDR = ~pullupEnable; - pPio->PIO_PPUER = pullupEnable; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_CfgDirectDrive -//* \brief Enable direct drive on PIO -//*---------------------------------------------------------------------------- -__inline void AT91F_PIO_CfgDirectDrive( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int directDrive) // \arg PIO to be configured with direct drive - -{ - // Configure the Direct Drive - pPio->PIO_OWDR = ~directDrive; - pPio->PIO_OWER = directDrive; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_CfgInputFilter -//* \brief Enable input filter on input PIO -//*---------------------------------------------------------------------------- -__inline void AT91F_PIO_CfgInputFilter( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int inputFilter) // \arg PIO to be configured with input filter - -{ - // Configure the Direct Drive - pPio->PIO_IFDR = ~inputFilter; - pPio->PIO_IFER = inputFilter; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_GetInput -//* \brief Return PIO input value -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_PIO_GetInput( // \return PIO input - AT91PS_PIO pPio) // \arg pointer to a PIO controller -{ - return pPio->PIO_PDSR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_IsInputSet -//* \brief Test if PIO is input flag is active -//*---------------------------------------------------------------------------- -__inline int AT91F_PIO_IsInputSet( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag) // \arg flag to be tested -{ - return (AT91F_PIO_GetInput(pPio) & flag); -} - - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_SetOutput -//* \brief Set to 1 output PIO -//*---------------------------------------------------------------------------- -__inline void AT91F_PIO_SetOutput( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag) // \arg output to be set -{ - pPio->PIO_SODR = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_ClearOutput -//* \brief Set to 0 output PIO -//*---------------------------------------------------------------------------- -__inline void AT91F_PIO_ClearOutput( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag) // \arg output to be cleared -{ - pPio->PIO_CODR = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_ForceOutput -//* \brief Force output when Direct drive option is enabled -//*---------------------------------------------------------------------------- -__inline void AT91F_PIO_ForceOutput( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag) // \arg output to be forced -{ - pPio->PIO_ODSR = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_Enable -//* \brief Enable PIO -//*---------------------------------------------------------------------------- -__inline void AT91F_PIO_Enable( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag) // \arg pio to be enabled -{ +* SOFTWARE API FOR PIO +***************************************************************************** */ +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PIO_CfgPeriph */ +/** \brief Enable pins to be derived by peripheral */ +/**---------------------------------------------------------------------------- */ + __inline void AT91F_PIO_CfgPeriph( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */ + unsigned int periphAEnable, /* \arg PERIPH A to enable */ + unsigned int periphBEnable ) /* \arg PERIPH B to enable */ + + { + pPio->PIO_ASR = periphAEnable; + pPio->PIO_BSR = periphBEnable; + pPio->PIO_PDR = ( periphAEnable | periphBEnable ); /* Set in Periph mode */ + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PIO_CfgOutput */ +/** \brief Enable PIO in output mode */ +/**---------------------------------------------------------------------------- */ + __inline void AT91F_PIO_CfgOutput( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */ + unsigned int pioEnable ) /* \arg PIO to be enabled */ + { + pPio->PIO_PER = pioEnable; /* Set in PIO mode */ + pPio->PIO_OER = pioEnable; /* Configure in Output */ + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PIO_CfgInput */ +/** \brief Enable PIO in input mode */ +/**---------------------------------------------------------------------------- */ + __inline void AT91F_PIO_CfgInput( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */ + unsigned int inputEnable ) /* \arg PIO to be enabled */ + { + /* Disable output */ + pPio->PIO_ODR = inputEnable; + pPio->PIO_PER = inputEnable; + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PIO_CfgOpendrain */ +/** \brief Configure PIO in open drain */ +/**---------------------------------------------------------------------------- */ + __inline void AT91F_PIO_CfgOpendrain( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */ + unsigned int multiDrvEnable ) /* \arg pio to be configured in open drain */ + { + /* Configure the multi-drive option */ + pPio->PIO_MDDR = ~multiDrvEnable; + pPio->PIO_MDER = multiDrvEnable; + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PIO_CfgPullup */ +/** \brief Enable pullup on PIO */ +/**---------------------------------------------------------------------------- */ + __inline void AT91F_PIO_CfgPullup( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */ + unsigned int pullupEnable ) /* \arg enable pullup on PIO */ + { + /* Connect or not Pullup */ + pPio->PIO_PPUDR = ~pullupEnable; + pPio->PIO_PPUER = pullupEnable; + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PIO_CfgDirectDrive */ +/** \brief Enable direct drive on PIO */ +/**---------------------------------------------------------------------------- */ + __inline void AT91F_PIO_CfgDirectDrive( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */ + unsigned int directDrive ) /* \arg PIO to be configured with direct drive */ + + { + /* Configure the Direct Drive */ + pPio->PIO_OWDR = ~directDrive; + pPio->PIO_OWER = directDrive; + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PIO_CfgInputFilter */ +/** \brief Enable input filter on input PIO */ +/**---------------------------------------------------------------------------- */ + __inline void AT91F_PIO_CfgInputFilter( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */ + unsigned int inputFilter ) /* \arg PIO to be configured with input filter */ + + { + /* Configure the Direct Drive */ + pPio->PIO_IFDR = ~inputFilter; + pPio->PIO_IFER = inputFilter; + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PIO_GetInput */ +/** \brief Return PIO input value */ +/**---------------------------------------------------------------------------- */ + __inline unsigned int AT91F_PIO_GetInput( /* \return PIO input */ + AT91PS_PIO pPio ) /* \arg pointer to a PIO controller */ + { + return pPio->PIO_PDSR; + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PIO_IsInputSet */ +/** \brief Test if PIO is input flag is active */ +/**---------------------------------------------------------------------------- */ + __inline int AT91F_PIO_IsInputSet( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */ + unsigned int flag ) /* \arg flag to be tested */ + { + return( AT91F_PIO_GetInput( pPio ) & flag ); + } + + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PIO_SetOutput */ +/** \brief Set to 1 output PIO */ +/**---------------------------------------------------------------------------- */ + __inline void AT91F_PIO_SetOutput( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */ + unsigned int flag ) /* \arg output to be set */ + { + pPio->PIO_SODR = flag; + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PIO_ClearOutput */ +/** \brief Set to 0 output PIO */ +/**---------------------------------------------------------------------------- */ + __inline void AT91F_PIO_ClearOutput( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */ + unsigned int flag ) /* \arg output to be cleared */ + { + pPio->PIO_CODR = flag; + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PIO_ForceOutput */ +/** \brief Force output when Direct drive option is enabled */ +/**---------------------------------------------------------------------------- */ + __inline void AT91F_PIO_ForceOutput( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */ + unsigned int flag ) /* \arg output to be forced */ + { + pPio->PIO_ODSR = flag; + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PIO_Enable */ +/** \brief Enable PIO */ +/**---------------------------------------------------------------------------- */ + __inline void AT91F_PIO_Enable( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */ + unsigned int flag ) /* \arg pio to be enabled */ + { pPio->PIO_PER = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_Disable -//* \brief Disable PIO -//*---------------------------------------------------------------------------- -__inline void AT91F_PIO_Disable( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag) // \arg pio to be disabled -{ + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PIO_Disable */ +/** \brief Disable PIO */ +/**---------------------------------------------------------------------------- */ + __inline void AT91F_PIO_Disable( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */ + unsigned int flag ) /* \arg pio to be disabled */ + { pPio->PIO_PDR = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_GetStatus -//* \brief Return PIO Status -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_PIO_GetStatus( // \return PIO Status - AT91PS_PIO pPio) // \arg pointer to a PIO controller -{ + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PIO_GetStatus */ +/** \brief Return PIO Status */ +/**---------------------------------------------------------------------------- */ + __inline unsigned int AT91F_PIO_GetStatus( /* \return PIO Status */ + AT91PS_PIO pPio ) /* \arg pointer to a PIO controller */ + { return pPio->PIO_PSR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_IsSet -//* \brief Test if PIO is Set -//*---------------------------------------------------------------------------- -__inline int AT91F_PIO_IsSet( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag) // \arg flag to be tested -{ - return (AT91F_PIO_GetStatus(pPio) & flag); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_OutputEnable -//* \brief Output Enable PIO -//*---------------------------------------------------------------------------- -__inline void AT91F_PIO_OutputEnable( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag) // \arg pio output to be enabled -{ + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PIO_IsSet */ +/** \brief Test if PIO is Set */ +/**---------------------------------------------------------------------------- */ + __inline int AT91F_PIO_IsSet( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */ + unsigned int flag ) /* \arg flag to be tested */ + { + return( AT91F_PIO_GetStatus( pPio ) & flag ); + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PIO_OutputEnable */ +/** \brief Output Enable PIO */ +/**---------------------------------------------------------------------------- */ + __inline void AT91F_PIO_OutputEnable( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */ + unsigned int flag ) /* \arg pio output to be enabled */ + { pPio->PIO_OER = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_OutputDisable -//* \brief Output Enable PIO -//*---------------------------------------------------------------------------- -__inline void AT91F_PIO_OutputDisable( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag) // \arg pio output to be disabled -{ + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PIO_OutputDisable */ +/** \brief Output Enable PIO */ +/**---------------------------------------------------------------------------- */ + __inline void AT91F_PIO_OutputDisable( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */ + unsigned int flag ) /* \arg pio output to be disabled */ + { pPio->PIO_ODR = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_GetOutputStatus -//* \brief Return PIO Output Status -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_PIO_GetOutputStatus( // \return PIO Output Status - AT91PS_PIO pPio) // \arg pointer to a PIO controller -{ + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PIO_GetOutputStatus */ +/** \brief Return PIO Output Status */ +/**---------------------------------------------------------------------------- */ + __inline unsigned int AT91F_PIO_GetOutputStatus( /* \return PIO Output Status */ + AT91PS_PIO pPio ) /* \arg pointer to a PIO controller */ + { return pPio->PIO_OSR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_IsOuputSet -//* \brief Test if PIO Output is Set -//*---------------------------------------------------------------------------- -__inline int AT91F_PIO_IsOutputSet( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag) // \arg flag to be tested -{ - return (AT91F_PIO_GetOutputStatus(pPio) & flag); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_InputFilterEnable -//* \brief Input Filter Enable PIO -//*---------------------------------------------------------------------------- -__inline void AT91F_PIO_InputFilterEnable( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag) // \arg pio input filter to be enabled -{ + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PIO_IsOuputSet */ +/** \brief Test if PIO Output is Set */ +/**---------------------------------------------------------------------------- */ + __inline int AT91F_PIO_IsOutputSet( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */ + unsigned int flag ) /* \arg flag to be tested */ + { + return( AT91F_PIO_GetOutputStatus( pPio ) & flag ); + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PIO_InputFilterEnable */ +/** \brief Input Filter Enable PIO */ +/**---------------------------------------------------------------------------- */ + __inline void AT91F_PIO_InputFilterEnable( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */ + unsigned int flag ) /* \arg pio input filter to be enabled */ + { pPio->PIO_IFER = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_InputFilterDisable -//* \brief Input Filter Disable PIO -//*---------------------------------------------------------------------------- -__inline void AT91F_PIO_InputFilterDisable( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag) // \arg pio input filter to be disabled -{ + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PIO_InputFilterDisable */ +/** \brief Input Filter Disable PIO */ +/**---------------------------------------------------------------------------- */ + __inline void AT91F_PIO_InputFilterDisable( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */ + unsigned int flag ) /* \arg pio input filter to be disabled */ + { pPio->PIO_IFDR = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_GetInputFilterStatus -//* \brief Return PIO Input Filter Status -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_PIO_GetInputFilterStatus( // \return PIO Input Filter Status - AT91PS_PIO pPio) // \arg pointer to a PIO controller -{ + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PIO_GetInputFilterStatus */ +/** \brief Return PIO Input Filter Status */ +/**---------------------------------------------------------------------------- */ + __inline unsigned int AT91F_PIO_GetInputFilterStatus( /* \return PIO Input Filter Status */ + AT91PS_PIO pPio ) /* \arg pointer to a PIO controller */ + { return pPio->PIO_IFSR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_IsInputFilterSet -//* \brief Test if PIO Input filter is Set -//*---------------------------------------------------------------------------- -__inline int AT91F_PIO_IsInputFilterSet( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag) // \arg flag to be tested -{ - return (AT91F_PIO_GetInputFilterStatus(pPio) & flag); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_GetOutputDataStatus -//* \brief Return PIO Output Data Status -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_PIO_GetOutputDataStatus( // \return PIO Output Data Status - AT91PS_PIO pPio) // \arg pointer to a PIO controller -{ + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PIO_IsInputFilterSet */ +/** \brief Test if PIO Input filter is Set */ +/**---------------------------------------------------------------------------- */ + __inline int AT91F_PIO_IsInputFilterSet( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */ + unsigned int flag ) /* \arg flag to be tested */ + { + return( AT91F_PIO_GetInputFilterStatus( pPio ) & flag ); + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PIO_GetOutputDataStatus */ +/** \brief Return PIO Output Data Status */ +/**---------------------------------------------------------------------------- */ + __inline unsigned int AT91F_PIO_GetOutputDataStatus( /* \return PIO Output Data Status */ + AT91PS_PIO pPio ) /* \arg pointer to a PIO controller */ + { return pPio->PIO_ODSR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_InterruptEnable -//* \brief Enable PIO Interrupt -//*---------------------------------------------------------------------------- -__inline void AT91F_PIO_InterruptEnable( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag) // \arg pio interrupt to be enabled -{ + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PIO_InterruptEnable */ +/** \brief Enable PIO Interrupt */ +/**---------------------------------------------------------------------------- */ + __inline void AT91F_PIO_InterruptEnable( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */ + unsigned int flag ) /* \arg pio interrupt to be enabled */ + { pPio->PIO_IER = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_InterruptDisable -//* \brief Disable PIO Interrupt -//*---------------------------------------------------------------------------- -__inline void AT91F_PIO_InterruptDisable( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag) // \arg pio interrupt to be disabled -{ + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PIO_InterruptDisable */ +/** \brief Disable PIO Interrupt */ +/**---------------------------------------------------------------------------- */ + __inline void AT91F_PIO_InterruptDisable( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */ + unsigned int flag ) /* \arg pio interrupt to be disabled */ + { pPio->PIO_IDR = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_GetInterruptMaskStatus -//* \brief Return PIO Interrupt Mask Status -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_PIO_GetInterruptMaskStatus( // \return PIO Interrupt Mask Status - AT91PS_PIO pPio) // \arg pointer to a PIO controller -{ + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PIO_GetInterruptMaskStatus */ +/** \brief Return PIO Interrupt Mask Status */ +/**---------------------------------------------------------------------------- */ + __inline unsigned int AT91F_PIO_GetInterruptMaskStatus( /* \return PIO Interrupt Mask Status */ + AT91PS_PIO pPio ) /* \arg pointer to a PIO controller */ + { return pPio->PIO_IMR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_GetInterruptStatus -//* \brief Return PIO Interrupt Status -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_PIO_GetInterruptStatus( // \return PIO Interrupt Status - AT91PS_PIO pPio) // \arg pointer to a PIO controller -{ + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PIO_GetInterruptStatus */ +/** \brief Return PIO Interrupt Status */ +/**---------------------------------------------------------------------------- */ + __inline unsigned int AT91F_PIO_GetInterruptStatus( /* \return PIO Interrupt Status */ + AT91PS_PIO pPio ) /* \arg pointer to a PIO controller */ + { return pPio->PIO_ISR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_IsInterruptMasked -//* \brief Test if PIO Interrupt is Masked -//*---------------------------------------------------------------------------- -__inline int AT91F_PIO_IsInterruptMasked( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag) // \arg flag to be tested -{ - return (AT91F_PIO_GetInterruptMaskStatus(pPio) & flag); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_IsInterruptSet -//* \brief Test if PIO Interrupt is Set -//*---------------------------------------------------------------------------- -__inline int AT91F_PIO_IsInterruptSet( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag) // \arg flag to be tested -{ - return (AT91F_PIO_GetInterruptStatus(pPio) & flag); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_MultiDriverEnable -//* \brief Multi Driver Enable PIO -//*---------------------------------------------------------------------------- -__inline void AT91F_PIO_MultiDriverEnable( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag) // \arg pio to be enabled -{ + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PIO_IsInterruptMasked */ +/** \brief Test if PIO Interrupt is Masked */ +/**---------------------------------------------------------------------------- */ + __inline int AT91F_PIO_IsInterruptMasked( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */ + unsigned int flag ) /* \arg flag to be tested */ + { + return( AT91F_PIO_GetInterruptMaskStatus( pPio ) & flag ); + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PIO_IsInterruptSet */ +/** \brief Test if PIO Interrupt is Set */ +/**---------------------------------------------------------------------------- */ + __inline int AT91F_PIO_IsInterruptSet( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */ + unsigned int flag ) /* \arg flag to be tested */ + { + return( AT91F_PIO_GetInterruptStatus( pPio ) & flag ); + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PIO_MultiDriverEnable */ +/** \brief Multi Driver Enable PIO */ +/**---------------------------------------------------------------------------- */ + __inline void AT91F_PIO_MultiDriverEnable( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */ + unsigned int flag ) /* \arg pio to be enabled */ + { pPio->PIO_MDER = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_MultiDriverDisable -//* \brief Multi Driver Disable PIO -//*---------------------------------------------------------------------------- -__inline void AT91F_PIO_MultiDriverDisable( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag) // \arg pio to be disabled -{ + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PIO_MultiDriverDisable */ +/** \brief Multi Driver Disable PIO */ +/**---------------------------------------------------------------------------- */ + __inline void AT91F_PIO_MultiDriverDisable( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */ + unsigned int flag ) /* \arg pio to be disabled */ + { pPio->PIO_MDDR = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_GetMultiDriverStatus -//* \brief Return PIO Multi Driver Status -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_PIO_GetMultiDriverStatus( // \return PIO Multi Driver Status - AT91PS_PIO pPio) // \arg pointer to a PIO controller -{ + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PIO_GetMultiDriverStatus */ +/** \brief Return PIO Multi Driver Status */ +/**---------------------------------------------------------------------------- */ + __inline unsigned int AT91F_PIO_GetMultiDriverStatus( /* \return PIO Multi Driver Status */ + AT91PS_PIO pPio ) /* \arg pointer to a PIO controller */ + { return pPio->PIO_MDSR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_IsMultiDriverSet -//* \brief Test if PIO MultiDriver is Set -//*---------------------------------------------------------------------------- -__inline int AT91F_PIO_IsMultiDriverSet( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag) // \arg flag to be tested -{ - return (AT91F_PIO_GetMultiDriverStatus(pPio) & flag); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_A_RegisterSelection -//* \brief PIO A Register Selection -//*---------------------------------------------------------------------------- -__inline void AT91F_PIO_A_RegisterSelection( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag) // \arg pio A register selection -{ + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PIO_IsMultiDriverSet */ +/** \brief Test if PIO MultiDriver is Set */ +/**---------------------------------------------------------------------------- */ + __inline int AT91F_PIO_IsMultiDriverSet( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */ + unsigned int flag ) /* \arg flag to be tested */ + { + return( AT91F_PIO_GetMultiDriverStatus( pPio ) & flag ); + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PIO_A_RegisterSelection */ +/** \brief PIO A Register Selection */ +/**---------------------------------------------------------------------------- */ + __inline void AT91F_PIO_A_RegisterSelection( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */ + unsigned int flag ) /* \arg pio A register selection */ + { pPio->PIO_ASR = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_B_RegisterSelection -//* \brief PIO B Register Selection -//*---------------------------------------------------------------------------- -__inline void AT91F_PIO_B_RegisterSelection( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag) // \arg pio B register selection -{ + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PIO_B_RegisterSelection */ +/** \brief PIO B Register Selection */ +/**---------------------------------------------------------------------------- */ + __inline void AT91F_PIO_B_RegisterSelection( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */ + unsigned int flag ) /* \arg pio B register selection */ + { pPio->PIO_BSR = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_Get_AB_RegisterStatus -//* \brief Return PIO Interrupt Status -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_PIO_Get_AB_RegisterStatus( // \return PIO AB Register Status - AT91PS_PIO pPio) // \arg pointer to a PIO controller -{ + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PIO_Get_AB_RegisterStatus */ +/** \brief Return PIO Interrupt Status */ +/**---------------------------------------------------------------------------- */ + __inline unsigned int AT91F_PIO_Get_AB_RegisterStatus( /* \return PIO AB Register Status */ + AT91PS_PIO pPio ) /* \arg pointer to a PIO controller */ + { return pPio->PIO_ABSR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_IsAB_RegisterSet -//* \brief Test if PIO AB Register is Set -//*---------------------------------------------------------------------------- -__inline int AT91F_PIO_IsAB_RegisterSet( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag) // \arg flag to be tested -{ - return (AT91F_PIO_Get_AB_RegisterStatus(pPio) & flag); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_OutputWriteEnable -//* \brief Output Write Enable PIO -//*---------------------------------------------------------------------------- -__inline void AT91F_PIO_OutputWriteEnable( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag) // \arg pio output write to be enabled -{ + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PIO_IsAB_RegisterSet */ +/** \brief Test if PIO AB Register is Set */ +/**---------------------------------------------------------------------------- */ + __inline int AT91F_PIO_IsAB_RegisterSet( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */ + unsigned int flag ) /* \arg flag to be tested */ + { + return( AT91F_PIO_Get_AB_RegisterStatus( pPio ) & flag ); + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PIO_OutputWriteEnable */ +/** \brief Output Write Enable PIO */ +/**---------------------------------------------------------------------------- */ + __inline void AT91F_PIO_OutputWriteEnable( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */ + unsigned int flag ) /* \arg pio output write to be enabled */ + { pPio->PIO_OWER = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_OutputWriteDisable -//* \brief Output Write Disable PIO -//*---------------------------------------------------------------------------- -__inline void AT91F_PIO_OutputWriteDisable( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag) // \arg pio output write to be disabled -{ + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PIO_OutputWriteDisable */ +/** \brief Output Write Disable PIO */ +/**---------------------------------------------------------------------------- */ + __inline void AT91F_PIO_OutputWriteDisable( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */ + unsigned int flag ) /* \arg pio output write to be disabled */ + { pPio->PIO_OWDR = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_GetOutputWriteStatus -//* \brief Return PIO Output Write Status -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_PIO_GetOutputWriteStatus( // \return PIO Output Write Status - AT91PS_PIO pPio) // \arg pointer to a PIO controller -{ + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PIO_GetOutputWriteStatus */ +/** \brief Return PIO Output Write Status */ +/**---------------------------------------------------------------------------- */ + __inline unsigned int AT91F_PIO_GetOutputWriteStatus( /* \return PIO Output Write Status */ + AT91PS_PIO pPio ) /* \arg pointer to a PIO controller */ + { return pPio->PIO_OWSR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_IsOutputWriteSet -//* \brief Test if PIO OutputWrite is Set -//*---------------------------------------------------------------------------- -__inline int AT91F_PIO_IsOutputWriteSet( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag) // \arg flag to be tested -{ - return (AT91F_PIO_GetOutputWriteStatus(pPio) & flag); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_GetCfgPullup -//* \brief Return PIO Configuration Pullup -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_PIO_GetCfgPullup( // \return PIO Configuration Pullup - AT91PS_PIO pPio) // \arg pointer to a PIO controller -{ + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PIO_IsOutputWriteSet */ +/** \brief Test if PIO OutputWrite is Set */ +/**---------------------------------------------------------------------------- */ + __inline int AT91F_PIO_IsOutputWriteSet( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */ + unsigned int flag ) /* \arg flag to be tested */ + { + return( AT91F_PIO_GetOutputWriteStatus( pPio ) & flag ); + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PIO_GetCfgPullup */ +/** \brief Return PIO Configuration Pullup */ +/**---------------------------------------------------------------------------- */ + __inline unsigned int AT91F_PIO_GetCfgPullup( /* \return PIO Configuration Pullup */ + AT91PS_PIO pPio ) /* \arg pointer to a PIO controller */ + { return pPio->PIO_PPUSR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_IsOutputDataStatusSet -//* \brief Test if PIO Output Data Status is Set -//*---------------------------------------------------------------------------- -__inline int AT91F_PIO_IsOutputDataStatusSet( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag) // \arg flag to be tested -{ - return (AT91F_PIO_GetOutputDataStatus(pPio) & flag); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_IsCfgPullupStatusSet -//* \brief Test if PIO Configuration Pullup Status is Set -//*---------------------------------------------------------------------------- -__inline int AT91F_PIO_IsCfgPullupStatusSet( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag) // \arg flag to be tested -{ - return (~AT91F_PIO_GetCfgPullup(pPio) & flag); -} + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PIO_IsOutputDataStatusSet */ +/** \brief Test if PIO Output Data Status is Set */ +/**---------------------------------------------------------------------------- */ + __inline int AT91F_PIO_IsOutputDataStatusSet( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */ + unsigned int flag ) /* \arg flag to be tested */ + { + return( AT91F_PIO_GetOutputDataStatus( pPio ) & flag ); + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PIO_IsCfgPullupStatusSet */ +/** \brief Test if PIO Configuration Pullup Status is Set */ +/**---------------------------------------------------------------------------- */ + __inline int AT91F_PIO_IsCfgPullupStatusSet( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */ + unsigned int flag ) /* \arg flag to be tested */ + { + return( ~AT91F_PIO_GetCfgPullup( pPio ) & flag ); + } /* ***************************************************************************** - SOFTWARE API FOR PMC - ***************************************************************************** */ -//*---------------------------------------------------------------------------- -//* \fn AT91F_PMC_CfgSysClkEnableReg -//* \brief Configure the System Clock Enable Register of the PMC controller -//*---------------------------------------------------------------------------- -__inline void AT91F_PMC_CfgSysClkEnableReg ( - AT91PS_PMC pPMC, // \arg pointer to PMC controller - unsigned int mode) -{ - //* Write to the SCER register - pPMC->PMC_SCER = mode; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PMC_CfgSysClkDisableReg -//* \brief Configure the System Clock Disable Register of the PMC controller -//*---------------------------------------------------------------------------- -__inline void AT91F_PMC_CfgSysClkDisableReg ( - AT91PS_PMC pPMC, // \arg pointer to PMC controller - unsigned int mode) -{ - //* Write to the SCDR register - pPMC->PMC_SCDR = mode; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PMC_GetSysClkStatusReg -//* \brief Return the System Clock Status Register of the PMC controller -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_PMC_GetSysClkStatusReg ( - AT91PS_PMC pPMC // pointer to a CAN controller - ) -{ - return pPMC->PMC_SCSR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PMC_EnablePeriphClock -//* \brief Enable peripheral clock -//*---------------------------------------------------------------------------- -__inline void AT91F_PMC_EnablePeriphClock ( - AT91PS_PMC pPMC, // \arg pointer to PMC controller - unsigned int periphIds) // \arg IDs of peripherals to enable -{ - pPMC->PMC_PCER = periphIds; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PMC_DisablePeriphClock -//* \brief Disable peripheral clock -//*---------------------------------------------------------------------------- -__inline void AT91F_PMC_DisablePeriphClock ( - AT91PS_PMC pPMC, // \arg pointer to PMC controller - unsigned int periphIds) // \arg IDs of peripherals to enable -{ - pPMC->PMC_PCDR = periphIds; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PMC_GetPeriphClock -//* \brief Get peripheral clock status -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_PMC_GetPeriphClock ( - AT91PS_PMC pPMC) // \arg pointer to PMC controller -{ - return pPMC->PMC_PCSR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_CKGR_CfgMainOscillatorReg -//* \brief Cfg the main oscillator -//*---------------------------------------------------------------------------- -__inline void AT91F_CKGR_CfgMainOscillatorReg ( - AT91PS_CKGR pCKGR, // \arg pointer to CKGR controller - unsigned int mode) -{ - pCKGR->CKGR_MOR = mode; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_CKGR_GetMainOscillatorReg -//* \brief Cfg the main oscillator -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_CKGR_GetMainOscillatorReg ( - AT91PS_CKGR pCKGR) // \arg pointer to CKGR controller -{ - return pCKGR->CKGR_MOR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_CKGR_EnableMainOscillator -//* \brief Enable the main oscillator -//*---------------------------------------------------------------------------- -__inline void AT91F_CKGR_EnableMainOscillator( - AT91PS_CKGR pCKGR) // \arg pointer to CKGR controller -{ - pCKGR->CKGR_MOR |= AT91C_CKGR_MOSCEN; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_CKGR_DisableMainOscillator -//* \brief Disable the main oscillator -//*---------------------------------------------------------------------------- -__inline void AT91F_CKGR_DisableMainOscillator ( - AT91PS_CKGR pCKGR) // \arg pointer to CKGR controller -{ - pCKGR->CKGR_MOR &= ~AT91C_CKGR_MOSCEN; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_CKGR_CfgMainOscStartUpTime -//* \brief Cfg MOR Register according to the main osc startup time -//*---------------------------------------------------------------------------- -__inline void AT91F_CKGR_CfgMainOscStartUpTime ( - AT91PS_CKGR pCKGR, // \arg pointer to CKGR controller - unsigned int startup_time, // \arg main osc startup time in microsecond (us) - unsigned int slowClock) // \arg slowClock in Hz -{ - pCKGR->CKGR_MOR &= ~AT91C_CKGR_OSCOUNT; - pCKGR->CKGR_MOR |= ((slowClock * startup_time)/(8*1000000)) << 8; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_CKGR_GetMainClockFreqReg -//* \brief Cfg the main oscillator -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_CKGR_GetMainClockFreqReg ( - AT91PS_CKGR pCKGR) // \arg pointer to CKGR controller -{ - return pCKGR->CKGR_MCFR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_CKGR_GetMainClock -//* \brief Return Main clock in Hz -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_CKGR_GetMainClock ( - AT91PS_CKGR pCKGR, // \arg pointer to CKGR controller - unsigned int slowClock) // \arg slowClock in Hz -{ - return ((pCKGR->CKGR_MCFR & AT91C_CKGR_MAINF) * slowClock) >> 4; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PMC_CfgMCKReg -//* \brief Cfg Master Clock Register -//*---------------------------------------------------------------------------- -__inline void AT91F_PMC_CfgMCKReg ( - AT91PS_PMC pPMC, // \arg pointer to PMC controller - unsigned int mode) -{ - pPMC->PMC_MCKR = mode; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PMC_GetMCKReg -//* \brief Return Master Clock Register -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_PMC_GetMCKReg( - AT91PS_PMC pPMC) // \arg pointer to PMC controller -{ - return pPMC->PMC_MCKR; -} - -//*------------------------------------------------------------------------------ -//* \fn AT91F_PMC_GetMasterClock -//* \brief Return master clock in Hz which correponds to processor clock for ARM7 -//*------------------------------------------------------------------------------ -__inline unsigned int AT91F_PMC_GetMasterClock ( - AT91PS_PMC pPMC, // \arg pointer to PMC controller - AT91PS_CKGR pCKGR, // \arg pointer to CKGR controller - unsigned int slowClock) // \arg slowClock in Hz -{ - unsigned int reg = pPMC->PMC_MCKR; - unsigned int prescaler = (1 << ((reg & AT91C_PMC_PRES) >> 2)); - unsigned int pllDivider, pllMultiplier; - - switch (reg & AT91C_PMC_CSS) { - case AT91C_PMC_CSS_SLOW_CLK: // Slow clock selected - return slowClock / prescaler; - case AT91C_PMC_CSS_MAIN_CLK: // Main clock is selected - return AT91F_CKGR_GetMainClock(pCKGR, slowClock) / prescaler; - case AT91C_PMC_CSS_PLL_CLK: // PLLB clock is selected - reg = pCKGR->CKGR_PLLR; - pllDivider = (reg & AT91C_CKGR_DIV); - pllMultiplier = ((reg & AT91C_CKGR_MUL) >> 16) + 1; - return AT91F_CKGR_GetMainClock(pCKGR, slowClock) / pllDivider * pllMultiplier / prescaler; - } - return 0; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PMC_EnablePCK -//* \brief Enable peripheral clock -//*---------------------------------------------------------------------------- -__inline void AT91F_PMC_EnablePCK ( - AT91PS_PMC pPMC, // \arg pointer to PMC controller - unsigned int pck, // \arg Peripheral clock identifier 0 .. 7 - unsigned int mode) -{ - pPMC->PMC_PCKR[pck] = mode; - pPMC->PMC_SCER = (1 << pck) << 8; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PMC_DisablePCK -//* \brief Enable peripheral clock -//*---------------------------------------------------------------------------- -__inline void AT91F_PMC_DisablePCK ( - AT91PS_PMC pPMC, // \arg pointer to PMC controller - unsigned int pck) // \arg Peripheral clock identifier 0 .. 7 -{ - pPMC->PMC_SCDR = (1 << pck) << 8; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PMC_EnableIt -//* \brief Enable PMC interrupt -//*---------------------------------------------------------------------------- -__inline void AT91F_PMC_EnableIt ( - AT91PS_PMC pPMC, // pointer to a PMC controller - unsigned int flag) // IT to be enabled -{ - //* Write to the IER register - pPMC->PMC_IER = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PMC_DisableIt -//* \brief Disable PMC interrupt -//*---------------------------------------------------------------------------- -__inline void AT91F_PMC_DisableIt ( - AT91PS_PMC pPMC, // pointer to a PMC controller - unsigned int flag) // IT to be disabled -{ - //* Write to the IDR register - pPMC->PMC_IDR = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PMC_GetStatus -//* \brief Return PMC Interrupt Status -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_PMC_GetStatus( // \return PMC Interrupt Status - AT91PS_PMC pPMC) // pointer to a PMC controller -{ - return pPMC->PMC_SR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PMC_GetInterruptMaskStatus -//* \brief Return PMC Interrupt Mask Status -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_PMC_GetInterruptMaskStatus( // \return PMC Interrupt Mask Status - AT91PS_PMC pPMC) // pointer to a PMC controller -{ - return pPMC->PMC_IMR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PMC_IsInterruptMasked -//* \brief Test if PMC Interrupt is Masked -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_PMC_IsInterruptMasked( - AT91PS_PMC pPMC, // \arg pointer to a PMC controller - unsigned int flag) // \arg flag to be tested -{ - return (AT91F_PMC_GetInterruptMaskStatus(pPMC) & flag); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PMC_IsStatusSet -//* \brief Test if PMC Status is Set -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_PMC_IsStatusSet( - AT91PS_PMC pPMC, // \arg pointer to a PMC controller - unsigned int flag) // \arg flag to be tested -{ - return (AT91F_PMC_GetStatus(pPMC) & flag); -}/* ***************************************************************************** - SOFTWARE API FOR RSTC - ***************************************************************************** */ -//*---------------------------------------------------------------------------- -//* \fn AT91F_RSTSoftReset -//* \brief Start Software Reset -//*---------------------------------------------------------------------------- -__inline void AT91F_RSTSoftReset( - AT91PS_RSTC pRSTC, - unsigned int reset) -{ - pRSTC->RSTC_RCR = (0xA5000000 | reset); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_RSTSetMode -//* \brief Set Reset Mode -//*---------------------------------------------------------------------------- -__inline void AT91F_RSTSetMode( - AT91PS_RSTC pRSTC, - unsigned int mode) -{ - pRSTC->RSTC_RMR = (0xA5000000 | mode); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_RSTGetMode -//* \brief Get Reset Mode -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_RSTGetMode( - AT91PS_RSTC pRSTC) -{ - return (pRSTC->RSTC_RMR); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_RSTGetStatus -//* \brief Get Reset Status -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_RSTGetStatus( - AT91PS_RSTC pRSTC) -{ - return (pRSTC->RSTC_RSR); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_RSTIsSoftRstActive -//* \brief Return !=0 if software reset is still not completed -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_RSTIsSoftRstActive( - AT91PS_RSTC pRSTC) -{ - return ((pRSTC->RSTC_RSR) & AT91C_RSTC_SRCMP); -} +* SOFTWARE API FOR PMC +***************************************************************************** */ +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PMC_CfgSysClkEnableReg */ +/** \brief Configure the System Clock Enable Register of the PMC controller */ +/**---------------------------------------------------------------------------- */ + __inline void AT91F_PMC_CfgSysClkEnableReg( AT91PS_PMC pPMC, /* \arg pointer to PMC controller */ + unsigned int mode ) + { + /** Write to the SCER register */ + pPMC->PMC_SCER = mode; + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PMC_CfgSysClkDisableReg */ +/** \brief Configure the System Clock Disable Register of the PMC controller */ +/**---------------------------------------------------------------------------- */ + __inline void AT91F_PMC_CfgSysClkDisableReg( AT91PS_PMC pPMC, /* \arg pointer to PMC controller */ + unsigned int mode ) + { + /** Write to the SCDR register */ + pPMC->PMC_SCDR = mode; + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PMC_GetSysClkStatusReg */ +/** \brief Return the System Clock Status Register of the PMC controller */ +/**---------------------------------------------------------------------------- */ + __inline unsigned int AT91F_PMC_GetSysClkStatusReg( AT91PS_PMC pPMC /* pointer to a CAN controller */ + ) + { + return pPMC->PMC_SCSR; + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PMC_EnablePeriphClock */ +/** \brief Enable peripheral clock */ +/**---------------------------------------------------------------------------- */ + __inline void AT91F_PMC_EnablePeriphClock( AT91PS_PMC pPMC, /* \arg pointer to PMC controller */ + unsigned int periphIds ) /* \arg IDs of peripherals to enable */ + { + pPMC->PMC_PCER = periphIds; + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PMC_DisablePeriphClock */ +/** \brief Disable peripheral clock */ +/**---------------------------------------------------------------------------- */ + __inline void AT91F_PMC_DisablePeriphClock( AT91PS_PMC pPMC, /* \arg pointer to PMC controller */ + unsigned int periphIds ) /* \arg IDs of peripherals to enable */ + { + pPMC->PMC_PCDR = periphIds; + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PMC_GetPeriphClock */ +/** \brief Get peripheral clock status */ +/**---------------------------------------------------------------------------- */ + __inline unsigned int AT91F_PMC_GetPeriphClock( AT91PS_PMC pPMC ) /* \arg pointer to PMC controller */ + { + return pPMC->PMC_PCSR; + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_CKGR_CfgMainOscillatorReg */ +/** \brief Cfg the main oscillator */ +/**---------------------------------------------------------------------------- */ + __inline void AT91F_CKGR_CfgMainOscillatorReg( AT91PS_CKGR pCKGR, /* \arg pointer to CKGR controller */ + unsigned int mode ) + { + pCKGR->CKGR_MOR = mode; + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_CKGR_GetMainOscillatorReg */ +/** \brief Cfg the main oscillator */ +/**---------------------------------------------------------------------------- */ + __inline unsigned int AT91F_CKGR_GetMainOscillatorReg( AT91PS_CKGR pCKGR ) /* \arg pointer to CKGR controller */ + { + return pCKGR->CKGR_MOR; + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_CKGR_EnableMainOscillator */ +/** \brief Enable the main oscillator */ +/**---------------------------------------------------------------------------- */ + __inline void AT91F_CKGR_EnableMainOscillator( AT91PS_CKGR pCKGR ) /* \arg pointer to CKGR controller */ + { + pCKGR->CKGR_MOR |= AT91C_CKGR_MOSCEN; + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_CKGR_DisableMainOscillator */ +/** \brief Disable the main oscillator */ +/**---------------------------------------------------------------------------- */ + __inline void AT91F_CKGR_DisableMainOscillator( AT91PS_CKGR pCKGR ) /* \arg pointer to CKGR controller */ + { + pCKGR->CKGR_MOR &= ~AT91C_CKGR_MOSCEN; + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_CKGR_CfgMainOscStartUpTime */ +/** \brief Cfg MOR Register according to the main osc startup time */ +/**---------------------------------------------------------------------------- */ + __inline void AT91F_CKGR_CfgMainOscStartUpTime( AT91PS_CKGR pCKGR, /* \arg pointer to CKGR controller */ + unsigned int startup_time, /* \arg main osc startup time in microsecond (us) */ + unsigned int slowClock ) /* \arg slowClock in Hz */ + { + pCKGR->CKGR_MOR &= ~AT91C_CKGR_OSCOUNT; + pCKGR->CKGR_MOR |= ( ( slowClock * startup_time ) / ( 8 * 1000000 ) ) << 8; + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_CKGR_GetMainClockFreqReg */ +/** \brief Cfg the main oscillator */ +/**---------------------------------------------------------------------------- */ + __inline unsigned int AT91F_CKGR_GetMainClockFreqReg( AT91PS_CKGR pCKGR ) /* \arg pointer to CKGR controller */ + { + return pCKGR->CKGR_MCFR; + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_CKGR_GetMainClock */ +/** \brief Return Main clock in Hz */ +/**---------------------------------------------------------------------------- */ + __inline unsigned int AT91F_CKGR_GetMainClock( AT91PS_CKGR pCKGR, /* \arg pointer to CKGR controller */ + unsigned int slowClock ) /* \arg slowClock in Hz */ + { + return ( ( pCKGR->CKGR_MCFR & AT91C_CKGR_MAINF ) * slowClock ) >> 4; + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PMC_CfgMCKReg */ +/** \brief Cfg Master Clock Register */ +/**---------------------------------------------------------------------------- */ + __inline void AT91F_PMC_CfgMCKReg( AT91PS_PMC pPMC, /* \arg pointer to PMC controller */ + unsigned int mode ) + { + pPMC->PMC_MCKR = mode; + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PMC_GetMCKReg */ +/** \brief Return Master Clock Register */ +/**---------------------------------------------------------------------------- */ + __inline unsigned int AT91F_PMC_GetMCKReg( AT91PS_PMC pPMC ) /* \arg pointer to PMC controller */ + { + return pPMC->PMC_MCKR; + } + +/**------------------------------------------------------------------------------ */ +/** \fn AT91F_PMC_GetMasterClock */ +/** \brief Return master clock in Hz which corresponds to processor clock for ARM7 */ +/**------------------------------------------------------------------------------ */ + __inline unsigned int AT91F_PMC_GetMasterClock( AT91PS_PMC pPMC, /* \arg pointer to PMC controller */ + AT91PS_CKGR pCKGR, /* \arg pointer to CKGR controller */ + unsigned int slowClock ) /* \arg slowClock in Hz */ + { + unsigned int reg = pPMC->PMC_MCKR; + unsigned int prescaler = ( 1 << ( ( reg & AT91C_PMC_PRES ) >> 2 ) ); + unsigned int pllDivider, pllMultiplier; + + switch( reg & AT91C_PMC_CSS ) + { + case AT91C_PMC_CSS_SLOW_CLK: /* Slow clock selected */ + return slowClock / prescaler; + + case AT91C_PMC_CSS_MAIN_CLK: /* Main clock is selected */ + return AT91F_CKGR_GetMainClock( pCKGR, slowClock ) / prescaler; + + case AT91C_PMC_CSS_PLL_CLK: /* PLLB clock is selected */ + reg = pCKGR->CKGR_PLLR; + pllDivider = ( reg & AT91C_CKGR_DIV ); + pllMultiplier = ( ( reg & AT91C_CKGR_MUL ) >> 16 ) + 1; + return AT91F_CKGR_GetMainClock( pCKGR, slowClock ) / pllDivider * pllMultiplier / prescaler; + } + + return 0; + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PMC_EnablePCK */ +/** \brief Enable peripheral clock */ +/**---------------------------------------------------------------------------- */ + __inline void AT91F_PMC_EnablePCK( AT91PS_PMC pPMC, /* \arg pointer to PMC controller */ + unsigned int pck, /* \arg Peripheral clock identifier 0 .. 7 */ + unsigned int mode ) + { + pPMC->PMC_PCKR[ pck ] = mode; + pPMC->PMC_SCER = ( 1 << pck ) << 8; + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PMC_DisablePCK */ +/** \brief Enable peripheral clock */ +/**---------------------------------------------------------------------------- */ + __inline void AT91F_PMC_DisablePCK( AT91PS_PMC pPMC, /* \arg pointer to PMC controller */ + unsigned int pck ) /* \arg Peripheral clock identifier 0 .. 7 */ + { + pPMC->PMC_SCDR = ( 1 << pck ) << 8; + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PMC_EnableIt */ +/** \brief Enable PMC interrupt */ +/**---------------------------------------------------------------------------- */ + __inline void AT91F_PMC_EnableIt( AT91PS_PMC pPMC, /* pointer to a PMC controller */ + unsigned int flag ) /* IT to be enabled */ + { + /** Write to the IER register */ + pPMC->PMC_IER = flag; + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PMC_DisableIt */ +/** \brief Disable PMC interrupt */ +/**---------------------------------------------------------------------------- */ + __inline void AT91F_PMC_DisableIt( AT91PS_PMC pPMC, /* pointer to a PMC controller */ + unsigned int flag ) /* IT to be disabled */ + { + /** Write to the IDR register */ + pPMC->PMC_IDR = flag; + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PMC_GetStatus */ +/** \brief Return PMC Interrupt Status */ +/**---------------------------------------------------------------------------- */ + __inline unsigned int AT91F_PMC_GetStatus( /* \return PMC Interrupt Status */ + AT91PS_PMC pPMC ) /* pointer to a PMC controller */ + { + return pPMC->PMC_SR; + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PMC_GetInterruptMaskStatus */ +/** \brief Return PMC Interrupt Mask Status */ +/**---------------------------------------------------------------------------- */ + __inline unsigned int AT91F_PMC_GetInterruptMaskStatus( /* \return PMC Interrupt Mask Status */ + AT91PS_PMC pPMC ) /* pointer to a PMC controller */ + { + return pPMC->PMC_IMR; + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PMC_IsInterruptMasked */ +/** \brief Test if PMC Interrupt is Masked */ +/**---------------------------------------------------------------------------- */ + __inline unsigned int AT91F_PMC_IsInterruptMasked( AT91PS_PMC pPMC, /* \arg pointer to a PMC controller */ + unsigned int flag ) /* \arg flag to be tested */ + { + return( AT91F_PMC_GetInterruptMaskStatus( pPMC ) & flag ); + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PMC_IsStatusSet */ +/** \brief Test if PMC Status is Set */ +/**---------------------------------------------------------------------------- */ + __inline unsigned int AT91F_PMC_IsStatusSet( AT91PS_PMC pPMC, /* \arg pointer to a PMC controller */ + unsigned int flag ) /* \arg flag to be tested */ + { + return( AT91F_PMC_GetStatus( pPMC ) & flag ); + } /* ***************************************************************************** + * SOFTWARE API FOR RSTC + ***************************************************************************** */ +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_RSTSoftReset */ +/** \brief Start Software Reset */ +/**---------------------------------------------------------------------------- */ + __inline void AT91F_RSTSoftReset( AT91PS_RSTC pRSTC, + unsigned int reset ) + { + pRSTC->RSTC_RCR = ( 0xA5000000 | reset ); + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_RSTSetMode */ +/** \brief Set Reset Mode */ +/**---------------------------------------------------------------------------- */ + __inline void AT91F_RSTSetMode( AT91PS_RSTC pRSTC, + unsigned int mode ) + { + pRSTC->RSTC_RMR = ( 0xA5000000 | mode ); + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_RSTGetMode */ +/** \brief Get Reset Mode */ +/**---------------------------------------------------------------------------- */ + __inline unsigned int AT91F_RSTGetMode( AT91PS_RSTC pRSTC ) + { + return( pRSTC->RSTC_RMR ); + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_RSTGetStatus */ +/** \brief Get Reset Status */ +/**---------------------------------------------------------------------------- */ + __inline unsigned int AT91F_RSTGetStatus( AT91PS_RSTC pRSTC ) + { + return( pRSTC->RSTC_RSR ); + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_RSTIsSoftRstActive */ +/** \brief Return !=0 if software reset is still not completed */ +/**---------------------------------------------------------------------------- */ + __inline unsigned int AT91F_RSTIsSoftRstActive( AT91PS_RSTC pRSTC ) + { + return( ( pRSTC->RSTC_RSR ) & AT91C_RSTC_SRCMP ); + } + /* ***************************************************************************** - SOFTWARE API FOR RTTC - ***************************************************************************** */ -//*-------------------------------------------------------------------------------------- -//* \fn AT91F_SetRTT_TimeBase() -//* \brief Set the RTT prescaler according to the TimeBase in ms -//*-------------------------------------------------------------------------------------- -__inline unsigned int AT91F_RTTSetTimeBase( - AT91PS_RTTC pRTTC, - unsigned int ms) -{ - if (ms > 2000) - return 1; // AT91C_TIME_OUT_OF_RANGE - pRTTC->RTTC_RTMR &= ~0xFFFF; - pRTTC->RTTC_RTMR |= (((ms << 15) /1000) & 0xFFFF); - return 0; -} - -//*-------------------------------------------------------------------------------------- -//* \fn AT91F_RTTSetPrescaler() -//* \brief Set the new prescaler value -//*-------------------------------------------------------------------------------------- -__inline unsigned int AT91F_RTTSetPrescaler( - AT91PS_RTTC pRTTC, - unsigned int rtpres) -{ - pRTTC->RTTC_RTMR &= ~0xFFFF; - pRTTC->RTTC_RTMR |= (rtpres & 0xFFFF); - return (pRTTC->RTTC_RTMR); -} - -//*-------------------------------------------------------------------------------------- -//* \fn AT91F_RTTRestart() -//* \brief Restart the RTT prescaler -//*-------------------------------------------------------------------------------------- -__inline void AT91F_RTTRestart( - AT91PS_RTTC pRTTC) -{ - pRTTC->RTTC_RTMR |= AT91C_RTTC_RTTRST; -} - - -//*-------------------------------------------------------------------------------------- -//* \fn AT91F_RTT_SetAlarmINT() -//* \brief Enable RTT Alarm Interrupt -//*-------------------------------------------------------------------------------------- -__inline void AT91F_RTTSetAlarmINT( - AT91PS_RTTC pRTTC) -{ - pRTTC->RTTC_RTMR |= AT91C_RTTC_ALMIEN; -} - -//*-------------------------------------------------------------------------------------- -//* \fn AT91F_RTT_ClearAlarmINT() -//* \brief Disable RTT Alarm Interrupt -//*-------------------------------------------------------------------------------------- -__inline void AT91F_RTTClearAlarmINT( - AT91PS_RTTC pRTTC) -{ - pRTTC->RTTC_RTMR &= ~AT91C_RTTC_ALMIEN; -} - -//*-------------------------------------------------------------------------------------- -//* \fn AT91F_RTT_SetRttIncINT() -//* \brief Enable RTT INC Interrupt -//*-------------------------------------------------------------------------------------- -__inline void AT91F_RTTSetRttIncINT( - AT91PS_RTTC pRTTC) -{ - pRTTC->RTTC_RTMR |= AT91C_RTTC_RTTINCIEN; -} - -//*-------------------------------------------------------------------------------------- -//* \fn AT91F_RTT_ClearRttIncINT() -//* \brief Disable RTT INC Interrupt -//*-------------------------------------------------------------------------------------- -__inline void AT91F_RTTClearRttIncINT( - AT91PS_RTTC pRTTC) -{ - pRTTC->RTTC_RTMR &= ~AT91C_RTTC_RTTINCIEN; -} - -//*-------------------------------------------------------------------------------------- -//* \fn AT91F_RTT_SetAlarmValue() -//* \brief Set RTT Alarm Value -//*-------------------------------------------------------------------------------------- -__inline void AT91F_RTTSetAlarmValue( - AT91PS_RTTC pRTTC, unsigned int alarm) -{ - pRTTC->RTTC_RTAR = alarm; -} - -//*-------------------------------------------------------------------------------------- -//* \fn AT91F_RTT_GetAlarmValue() -//* \brief Get RTT Alarm Value -//*-------------------------------------------------------------------------------------- -__inline unsigned int AT91F_RTTGetAlarmValue( - AT91PS_RTTC pRTTC) -{ - return(pRTTC->RTTC_RTAR); -} - -//*-------------------------------------------------------------------------------------- -//* \fn AT91F_RTTGetStatus() -//* \brief Read the RTT status -//*-------------------------------------------------------------------------------------- -__inline unsigned int AT91F_RTTGetStatus( - AT91PS_RTTC pRTTC) -{ - return(pRTTC->RTTC_RTSR); -} - -//*-------------------------------------------------------------------------------------- -//* \fn AT91F_RTT_ReadValue() -//* \brief Read the RTT value -//*-------------------------------------------------------------------------------------- -__inline unsigned int AT91F_RTTReadValue( - AT91PS_RTTC pRTTC) -{ - register volatile unsigned int val1,val2; - do - { - val1 = pRTTC->RTTC_RTVR; - val2 = pRTTC->RTTC_RTVR; - } - while(val1 != val2); - return(val1); -} +* SOFTWARE API FOR RTTC +***************************************************************************** */ +/**-------------------------------------------------------------------------------------- */ +/** \fn AT91F_SetRTT_TimeBase() */ +/** \brief Set the RTT prescaler according to the TimeBase in ms */ +/**-------------------------------------------------------------------------------------- */ + __inline unsigned int AT91F_RTTSetTimeBase( AT91PS_RTTC pRTTC, + unsigned int ms ) + { + if( ms > 2000 ) + { + return 1; /* AT91C_TIME_OUT_OF_RANGE */ + } + + pRTTC->RTTC_RTMR &= ~0xFFFF; + pRTTC->RTTC_RTMR |= ( ( ( ms << 15 ) / 1000 ) & 0xFFFF ); + return 0; + } + +/**-------------------------------------------------------------------------------------- */ +/** \fn AT91F_RTTSetPrescaler() */ +/** \brief Set the new prescaler value */ +/**-------------------------------------------------------------------------------------- */ + __inline unsigned int AT91F_RTTSetPrescaler( AT91PS_RTTC pRTTC, + unsigned int rtpres ) + { + pRTTC->RTTC_RTMR &= ~0xFFFF; + pRTTC->RTTC_RTMR |= ( rtpres & 0xFFFF ); + return( pRTTC->RTTC_RTMR ); + } + +/**-------------------------------------------------------------------------------------- */ +/** \fn AT91F_RTTRestart() */ +/** \brief Restart the RTT prescaler */ +/**-------------------------------------------------------------------------------------- */ + __inline void AT91F_RTTRestart( AT91PS_RTTC pRTTC ) + { + pRTTC->RTTC_RTMR |= AT91C_RTTC_RTTRST; + } + + +/**-------------------------------------------------------------------------------------- */ +/** \fn AT91F_RTT_SetAlarmINT() */ +/** \brief Enable RTT Alarm Interrupt */ +/**-------------------------------------------------------------------------------------- */ + __inline void AT91F_RTTSetAlarmINT( AT91PS_RTTC pRTTC ) + { + pRTTC->RTTC_RTMR |= AT91C_RTTC_ALMIEN; + } + +/**-------------------------------------------------------------------------------------- */ +/** \fn AT91F_RTT_ClearAlarmINT() */ +/** \brief Disable RTT Alarm Interrupt */ +/**-------------------------------------------------------------------------------------- */ + __inline void AT91F_RTTClearAlarmINT( AT91PS_RTTC pRTTC ) + { + pRTTC->RTTC_RTMR &= ~AT91C_RTTC_ALMIEN; + } + +/**-------------------------------------------------------------------------------------- */ +/** \fn AT91F_RTT_SetRttIncINT() */ +/** \brief Enable RTT INC Interrupt */ +/**-------------------------------------------------------------------------------------- */ + __inline void AT91F_RTTSetRttIncINT( AT91PS_RTTC pRTTC ) + { + pRTTC->RTTC_RTMR |= AT91C_RTTC_RTTINCIEN; + } + +/**-------------------------------------------------------------------------------------- */ +/** \fn AT91F_RTT_ClearRttIncINT() */ +/** \brief Disable RTT INC Interrupt */ +/**-------------------------------------------------------------------------------------- */ + __inline void AT91F_RTTClearRttIncINT( AT91PS_RTTC pRTTC ) + { + pRTTC->RTTC_RTMR &= ~AT91C_RTTC_RTTINCIEN; + } + +/**-------------------------------------------------------------------------------------- */ +/** \fn AT91F_RTT_SetAlarmValue() */ +/** \brief Set RTT Alarm Value */ +/**-------------------------------------------------------------------------------------- */ + __inline void AT91F_RTTSetAlarmValue( AT91PS_RTTC pRTTC, + unsigned int alarm ) + { + pRTTC->RTTC_RTAR = alarm; + } + +/**-------------------------------------------------------------------------------------- */ +/** \fn AT91F_RTT_GetAlarmValue() */ +/** \brief Get RTT Alarm Value */ +/**-------------------------------------------------------------------------------------- */ + __inline unsigned int AT91F_RTTGetAlarmValue( AT91PS_RTTC pRTTC ) + { + return( pRTTC->RTTC_RTAR ); + } + +/**-------------------------------------------------------------------------------------- */ +/** \fn AT91F_RTTGetStatus() */ +/** \brief Read the RTT status */ +/**-------------------------------------------------------------------------------------- */ + __inline unsigned int AT91F_RTTGetStatus( AT91PS_RTTC pRTTC ) + { + return( pRTTC->RTTC_RTSR ); + } + +/**-------------------------------------------------------------------------------------- */ +/** \fn AT91F_RTT_ReadValue() */ +/** \brief Read the RTT value */ +/**-------------------------------------------------------------------------------------- */ + __inline unsigned int AT91F_RTTReadValue( AT91PS_RTTC pRTTC ) + { + register volatile unsigned int val1, val2; + + do + { + val1 = pRTTC->RTTC_RTVR; + val2 = pRTTC->RTTC_RTVR; + } + while( val1 != val2 ); + + return( val1 ); + } + /* ***************************************************************************** - SOFTWARE API FOR PITC - ***************************************************************************** */ -//*---------------------------------------------------------------------------- -//* \fn AT91F_PITInit -//* \brief System timer init : period in \ No newline at end of file +* SOFTWARE API FOR PITC +***************************************************************************** */ +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PITInit */ +/** \brief System timer init : period in */ diff --git a/Source/portable/IAR/AtmelSAM7S64/port.c b/Source/portable/IAR/AtmelSAM7S64/port.c index 8dc479cf5..b34bb2a9b 100644 --- a/Source/portable/IAR/AtmelSAM7S64/port.c +++ b/Source/portable/IAR/AtmelSAM7S64/port.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -27,8 +27,8 @@ */ /*----------------------------------------------------------- - * Implementation of functions defined in portable.h for the Atmel ARM7 port. - *----------------------------------------------------------*/ +* Implementation of functions defined in portable.h for the Atmel ARM7 port. +*----------------------------------------------------------*/ /* Standard includes. */ @@ -39,29 +39,29 @@ #include "task.h" /* Constants required to setup the initial stack. */ -#define portINITIAL_SPSR ( ( StackType_t ) 0x1f ) /* System mode, ARM mode, interrupts enabled. */ -#define portTHUMB_MODE_BIT ( ( StackType_t ) 0x20 ) -#define portINSTRUCTION_SIZE ( ( StackType_t ) 4 ) +#define portINITIAL_SPSR ( ( StackType_t ) 0x1f ) /* System mode, ARM mode, interrupts enabled. */ +#define portTHUMB_MODE_BIT ( ( StackType_t ) 0x20 ) +#define portINSTRUCTION_SIZE ( ( StackType_t ) 4 ) /* Constants required to setup the PIT. */ -#define portPIT_CLOCK_DIVISOR ( ( uint32_t ) 16 ) -#define portPIT_COUNTER_VALUE ( ( ( configCPU_CLOCK_HZ / portPIT_CLOCK_DIVISOR ) / 1000UL ) * portTICK_PERIOD_MS ) +#define portPIT_CLOCK_DIVISOR ( ( uint32_t ) 16 ) +#define portPIT_COUNTER_VALUE ( ( ( configCPU_CLOCK_HZ / portPIT_CLOCK_DIVISOR ) / 1000UL ) * portTICK_PERIOD_MS ) /* Constants required to handle critical sections. */ -#define portNO_CRITICAL_NESTING ( ( uint32_t ) 0 ) +#define portNO_CRITICAL_NESTING ( ( uint32_t ) 0 ) -#define portINT_LEVEL_SENSITIVE 0 -#define portPIT_ENABLE ( ( uint16_t ) 0x1 << 24 ) -#define portPIT_INT_ENABLE ( ( uint16_t ) 0x1 << 25 ) +#define portINT_LEVEL_SENSITIVE 0 +#define portPIT_ENABLE ( ( uint16_t ) 0x1 << 24 ) +#define portPIT_INT_ENABLE ( ( uint16_t ) 0x1 << 25 ) /*-----------------------------------------------------------*/ /* Setup the PIT to generate the tick interrupts. */ static void prvSetupTimerInterrupt( void ); /* ulCriticalNesting will get set to zero when the first task starts. It -cannot be initialised to 0 as this will cause interrupts to be enabled -during the kernel initialisation process. */ + * cannot be initialised to 0 as this will cause interrupts to be enabled + * during the kernel initialisation process. */ uint32_t ulCriticalNesting = ( uint32_t ) 9999; /*-----------------------------------------------------------*/ @@ -72,56 +72,58 @@ uint32_t ulCriticalNesting = ( uint32_t ) 9999; * * See header file for description. */ -StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters ) +StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, + TaskFunction_t pxCode, + void * pvParameters ) { -StackType_t *pxOriginalTOS; + StackType_t * pxOriginalTOS; pxOriginalTOS = pxTopOfStack; /* To ensure asserts in tasks.c don't fail, although in this case the assert - is not really required. */ + * is not really required. */ pxTopOfStack--; /* Setup the initial stack of the task. The stack is set exactly as - expected by the portRESTORE_CONTEXT() macro. */ + * expected by the portRESTORE_CONTEXT() macro. */ /* First on the stack is the return address - which in this case is the - start of the task. The offset is added to make the return address appear - as it would within an IRQ ISR. */ + * start of the task. The offset is added to make the return address appear + * as it would within an IRQ ISR. */ *pxTopOfStack = ( StackType_t ) pxCode + portINSTRUCTION_SIZE; pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0xaaaaaaaa; /* R14 */ + *pxTopOfStack = ( StackType_t ) 0xaaaaaaaa; /* R14 */ pxTopOfStack--; *pxTopOfStack = ( StackType_t ) pxOriginalTOS; /* Stack used when task starts goes in R13. */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x12121212; /* R12 */ + *pxTopOfStack = ( StackType_t ) 0x12121212; /* R12 */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x11111111; /* R11 */ + *pxTopOfStack = ( StackType_t ) 0x11111111; /* R11 */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x10101010; /* R10 */ + *pxTopOfStack = ( StackType_t ) 0x10101010; /* R10 */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x09090909; /* R9 */ + *pxTopOfStack = ( StackType_t ) 0x09090909; /* R9 */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x08080808; /* R8 */ + *pxTopOfStack = ( StackType_t ) 0x08080808; /* R8 */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x07070707; /* R7 */ + *pxTopOfStack = ( StackType_t ) 0x07070707; /* R7 */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x06060606; /* R6 */ + *pxTopOfStack = ( StackType_t ) 0x06060606; /* R6 */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x05050505; /* R5 */ + *pxTopOfStack = ( StackType_t ) 0x05050505; /* R5 */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x04040404; /* R4 */ + *pxTopOfStack = ( StackType_t ) 0x04040404; /* R4 */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x03030303; /* R3 */ + *pxTopOfStack = ( StackType_t ) 0x03030303; /* R3 */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x02020202; /* R2 */ + *pxTopOfStack = ( StackType_t ) 0x02020202; /* R2 */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x01010101; /* R1 */ + *pxTopOfStack = ( StackType_t ) 0x01010101; /* R1 */ pxTopOfStack--; /* When the task starts is will expect to find the function parameter in - R0. */ + * R0. */ *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */ pxTopOfStack--; @@ -137,8 +139,8 @@ StackType_t *pxOriginalTOS; pxTopOfStack--; /* Interrupt flags cannot always be stored on the stack and will - instead be stored in a variable, which is then saved as part of the - tasks context. */ + * instead be stored in a variable, which is then saved as part of the + * tasks context. */ *pxTopOfStack = portNO_CRITICAL_NESTING; return pxTopOfStack; @@ -147,10 +149,10 @@ StackType_t *pxOriginalTOS; BaseType_t xPortStartScheduler( void ) { -extern void vPortStartFirstTask( void ); + extern void vPortStartFirstTask( void ); /* Start the timer that generates the tick ISR. Interrupts are disabled - here already. */ + * here already. */ prvSetupTimerInterrupt(); /* Start the first task. */ @@ -164,22 +166,22 @@ extern void vPortStartFirstTask( void ); void vPortEndScheduler( void ) { /* It is unlikely that the ARM port will require this function as there - is nothing to return to. */ + * is nothing to return to. */ } /*-----------------------------------------------------------*/ #if configUSE_PREEMPTION == 0 - /* The cooperative scheduler requires a normal IRQ service routine to - simply increment the system tick. */ +/* The cooperative scheduler requires a normal IRQ service routine to + * simply increment the system tick. */ static __arm __irq void vPortNonPreemptiveTick( void ); static __arm __irq void vPortNonPreemptiveTick( void ) { uint32_t ulDummy; /* Increment the tick count - which may wake some tasks but as the - preemptive scheduler is not being used any woken task is not given - processor time no matter what its priority. */ + * preemptive scheduler is not being used any woken task is not given + * processor time no matter what its priority. */ xTaskIncrementTick(); /* Clear the PIT interrupt. */ @@ -189,37 +191,33 @@ void vPortEndScheduler( void ) AT91C_BASE_AIC->AIC_EOICR = ulDummy; } -#else +#else /* if configUSE_PREEMPTION == 0 */ - /* Currently the IAR port requires the preemptive tick function to be - defined in an asm file. */ +/* Currently the IAR port requires the preemptive tick function to be + * defined in an asm file. */ -#endif +#endif /* if configUSE_PREEMPTION == 0 */ /*-----------------------------------------------------------*/ static void prvSetupTimerInterrupt( void ) { -AT91PS_PITC pxPIT = AT91C_BASE_PITC; + AT91PS_PITC pxPIT = AT91C_BASE_PITC; /* Setup the AIC for PIT interrupts. The interrupt routine chosen depends - on whether the preemptive or cooperative scheduler is being used. */ + * on whether the preemptive or cooperative scheduler is being used. */ #if configUSE_PREEMPTION == 0 - - AT91F_AIC_ConfigureIt( AT91C_BASE_AIC, AT91C_ID_SYS, AT91C_AIC_PRIOR_HIGHEST, portINT_LEVEL_SENSITIVE, ( void (*)(void) ) vPortNonPreemptiveTick ); - + AT91F_AIC_ConfigureIt( AT91C_BASE_AIC, AT91C_ID_SYS, AT91C_AIC_PRIOR_HIGHEST, portINT_LEVEL_SENSITIVE, ( void ( * )( void ) )vPortNonPreemptiveTick ); #else - - extern void ( vPortPreemptiveTick )( void ); - AT91F_AIC_ConfigureIt( AT91C_BASE_AIC, AT91C_ID_SYS, AT91C_AIC_PRIOR_HIGHEST, portINT_LEVEL_SENSITIVE, ( void (*)(void) ) vPortPreemptiveTick ); - + extern void( vPortPreemptiveTick )( void ); + AT91F_AIC_ConfigureIt( AT91C_BASE_AIC, AT91C_ID_SYS, AT91C_AIC_PRIOR_HIGHEST, portINT_LEVEL_SENSITIVE, ( void ( * )( void ) )vPortPreemptiveTick ); #endif /* Configure the PIT period. */ pxPIT->PITC_PIMR = portPIT_ENABLE | portPIT_INT_ENABLE | portPIT_COUNTER_VALUE; /* Enable the interrupt. Global interrupts are disabled at this point so - this is safe. */ + * this is safe. */ AT91F_AIC_EnableIt( AT91C_BASE_AIC, AT91C_ID_SYS ); } /*-----------------------------------------------------------*/ @@ -229,9 +227,9 @@ void vPortEnterCritical( void ) /* Disable interrupts first! */ __disable_interrupt(); - /* Now interrupts are disabled ulCriticalNesting can be accessed - directly. Increment ulCriticalNesting to keep a count of how many times - portENTER_CRITICAL() has been called. */ + /* Now that interrupts are disabled, ulCriticalNesting can be accessed + * directly. Increment ulCriticalNesting to keep a count of how many times + * portENTER_CRITICAL() has been called. */ ulCriticalNesting++; } /*-----------------------------------------------------------*/ @@ -244,7 +242,7 @@ void vPortExitCritical( void ) ulCriticalNesting--; /* If the nesting level has reached zero then interrupts should be - re-enabled. */ + * re-enabled. */ if( ulCriticalNesting == portNO_CRITICAL_NESTING ) { __enable_interrupt(); diff --git a/Source/portable/IAR/AtmelSAM7S64/portasm.s79 b/Source/portable/IAR/AtmelSAM7S64/portasm.s79 index b1733d959..d7033a062 100644 --- a/Source/portable/IAR/AtmelSAM7S64/portasm.s79 +++ b/Source/portable/IAR/AtmelSAM7S64/portasm.s79 @@ -1,5 +1,5 @@ ;/* -; * FreeRTOS Kernel V10.6.2 +; * FreeRTOS Kernel V11.0.1 ; * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. ; * ; * SPDX-License-Identifier: MIT diff --git a/Source/portable/IAR/AtmelSAM7S64/portmacro.h b/Source/portable/IAR/AtmelSAM7S64/portmacro.h index 131d77009..a3e24b74d 100644 --- a/Source/portable/IAR/AtmelSAM7S64/portmacro.h +++ b/Source/portable/IAR/AtmelSAM7S64/portmacro.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -47,35 +47,35 @@ */ /* Type definitions. */ -#define portCHAR char -#define portFLOAT float -#define portDOUBLE double -#define portLONG long -#define portSHORT short -#define portSTACK_TYPE uint32_t -#define portBASE_TYPE long +#define portCHAR char +#define portFLOAT float +#define portDOUBLE double +#define portLONG long +#define portSHORT short +#define portSTACK_TYPE uint32_t +#define portBASE_TYPE long -typedef portSTACK_TYPE StackType_t; -typedef long BaseType_t; -typedef unsigned long UBaseType_t; +typedef portSTACK_TYPE StackType_t; +typedef long BaseType_t; +typedef unsigned long UBaseType_t; -#if( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS ) - typedef uint16_t TickType_t; - #define portMAX_DELAY ( TickType_t ) 0xffff +#if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS ) + typedef uint16_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffff #elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS ) - typedef uint32_t TickType_t; - #define portMAX_DELAY ( TickType_t ) ( 0xFFFFFFFFUL ) + typedef uint32_t TickType_t; + #define portMAX_DELAY ( TickType_t ) ( 0xFFFFFFFFUL ) #else #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width. #endif /*-----------------------------------------------------------*/ /* Hardware specifics. */ -#define portSTACK_GROWTH ( -1 ) -#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) -#define portBYTE_ALIGNMENT 8 -#define portYIELD() asm ( "SWI 0" ) -#define portNOP() asm ( "NOP" ) +#define portSTACK_GROWTH ( -1 ) +#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) +#define portBYTE_ALIGNMENT 8 +#define portYIELD() asm ( "SWI 0" ) +#define portNOP() asm ( "NOP" ) /*-----------------------------------------------------------*/ /* Critical section handling. */ @@ -91,21 +91,26 @@ __arm __interwork void vPortExitCritical( void ); /*-----------------------------------------------------------*/ /* Task utilities. */ -#define portEND_SWITCHING_ISR( xSwitchRequired ) \ -{ \ -extern void vTaskSwitchContext( void ); \ - \ - if( xSwitchRequired ) \ - { \ - vTaskSwitchContext(); \ - } \ -} +#define portEND_SWITCHING_ISR( xSwitchRequired ) \ + { \ + extern void vTaskSwitchContext( void ); \ + \ + if( xSwitchRequired ) \ + { \ + traceISR_EXIT_TO_SCHEDULER(); \ + vTaskSwitchContext(); \ + } \ + else \ + { \ + traceISR_EXIT(); \ + } \ + } /*-----------------------------------------------------------*/ /* Task function macros as described on the FreeRTOS.org WEB site. */ -#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters ) -#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters ) +#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters ) +#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters ) /* *INDENT-OFF* */ #ifdef __cplusplus diff --git a/Source/portable/IAR/AtmelSAM9XE/ISR_Support.h b/Source/portable/IAR/AtmelSAM9XE/ISR_Support.h index f28ce85b1..152087982 100644 --- a/Source/portable/IAR/AtmelSAM9XE/ISR_Support.h +++ b/Source/portable/IAR/AtmelSAM9XE/ISR_Support.h @@ -1,104 +1,150 @@ -;/* -; * FreeRTOS Kernel V10.6.2 -; * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. -; * -; * SPDX-License-Identifier: MIT -; * -; * Permission is hereby granted, free of charge, to any person obtaining a copy of -; * this software and associated documentation files (the "Software"), to deal in -; * the Software without restriction, including without limitation the rights to -; * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of -; * the Software, and to permit persons to whom the Software is furnished to do so, -; * subject to the following conditions: -; * -; * The above copyright notice and this permission notice shall be included in all -; * copies or substantial portions of the Software. -; * -; * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -; * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS -; * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR -; * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER -; * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN -; * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. -; * -; * https://www.FreeRTOS.org -; * https://github.com/FreeRTOS -; * -; */ - EXTERN pxCurrentTCB - EXTERN ulCriticalNesting - -;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -; Context save and restore macro definitions -;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +; /* + * ; * FreeRTOS Kernel V11.0.1 + * ; * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * ; * + * ; * SPDX-License-Identifier: MIT + * ; * + * ; * Permission is hereby granted, free of charge, to any person obtaining a copy of + * ; * this software and associated documentation files (the "Software"), to deal in + * ; * the Software without restriction, including without limitation the rights to + * ; * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * ; * the Software, and to permit persons to whom the Software is furnished to do so, + * ; * subject to the following conditions: + * ; * + * ; * The above copyright notice and this permission notice shall be included in all + * ; * copies or substantial portions of the Software. + * ; * + * ; * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * ; * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * ; * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * ; * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * ; * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * ; * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * ; * + * ; * https://www.FreeRTOS.org + * ; * https://github.com/FreeRTOS + * ; * + * ; */ +EXTERN pxCurrentTCB +EXTERN ulCriticalNesting + +; +Context save and restore macro definitions +; portSAVE_CONTEXT MACRO - ; Push R0 as we are going to use the register. - STMDB SP!, {R0} +; +Push R0 as we are going to use the register. + STMDB SP !, { + R0 +} + +Set R0 to point to the task stack pointer. + STMDB SP, { + SP +} +^ +NOP +SUB SP, SP, # 4 +LDMIA SP !, { + R0 +} + +; +Push the return address onto the stack. + STMDB R0 !, { + LR + } + + Now we have saved LR we can use it instead of R0. + MOV LR, R0 + +; + +Pop R0 so we can save it onto the system mode stack. + LDMIA SP !, { + R0 +} + +Push all the system mode registers onto the task stack. + STMDB LR, { + R0 - LR +} +^ +NOP +SUB LR, LR, # 60 + +; +Push the SPSR onto the task stack. + MRS R0, SPSR +STMDB LR !, { + R0 +} + +LDR R0, = ulCriticalNesting + LDR R0, [ R0 ] +STMDB LR !, { + R0 +} + +Store the new top of stack + +for the task. + LDR R1, = pxCurrentTCB + LDR R0, [ R1 ] +STR LR, [ R0 ] + +ENDM - ; Set R0 to point to the task stack pointer. - STMDB SP, {SP}^ - NOP - SUB SP, SP, #4 - LDMIA SP!, {R0} - ; Push the return address onto the stack. - STMDB R0!, {LR} - - ; Now we have saved LR we can use it instead of R0. - MOV LR, R0 - - ; Pop R0 so we can save it onto the system mode stack. - LDMIA SP!, {R0} - - ; Push all the system mode registers onto the task stack. - STMDB LR, {R0-LR}^ - NOP - SUB LR, LR, #60 - - ; Push the SPSR onto the task stack. - MRS R0, SPSR - STMDB LR!, {R0} +portRESTORE_CONTEXT MACRO - LDR R0, =ulCriticalNesting - LDR R0, [R0] - STMDB LR!, {R0} +; +Set the LR to the task stack. + LDR R1, = pxCurrentTCB + LDR R0, [ R1 ] +LDR LR, [ R0 ] - ; Store the new top of stack for the task. - LDR R1, =pxCurrentTCB - LDR R0, [R1] - STR LR, [R0] +; +The critical nesting depth is the first item on the stack. + ; +Load it into the ulCriticalNesting variable. + LDR R0, = ulCriticalNesting + LDMFD LR !, { + R1 +} - ENDM +STR R1, [ R0 ] +; +Get the SPSR from the stack. + LDMFD LR !, { + R0 +} +MSR SPSR_cxsf, R0 -portRESTORE_CONTEXT MACRO +; +Restore all system mode registers - ; Set the LR to the task stack. - LDR R1, =pxCurrentTCB - LDR R0, [R1] - LDR LR, [R0] +for the task. + LDMFD LR, { + R0 - R14 +} - ; The critical nesting depth is the first item on the stack. - ; Load it into the ulCriticalNesting variable. - LDR R0, =ulCriticalNesting - LDMFD LR!, {R1} - STR R1, [R0] +^ +NOP - ; Get the SPSR from the stack. - LDMFD LR!, {R0} - MSR SPSR_cxsf, R0 +; +Restore the return address. + LDR LR, [ LR, # + 60 ] - ; Restore all system mode registers for the task. - LDMFD LR, {R0-R14}^ - NOP +; - ; Restore the return address. - LDR LR, [LR, #+60] +And return -correcting the offset in the LR to obtain the +; - ; And return - correcting the offset in the LR to obtain the - ; correct address. - SUBS PC, LR, #4 +correct address. + SUBS PC, LR, # 4 - ENDM +ENDM diff --git a/Source/portable/IAR/AtmelSAM9XE/port.c b/Source/portable/IAR/AtmelSAM9XE/port.c index 483dceda2..a0d56c486 100644 --- a/Source/portable/IAR/AtmelSAM9XE/port.c +++ b/Source/portable/IAR/AtmelSAM9XE/port.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -27,8 +27,8 @@ */ /*----------------------------------------------------------- - * Implementation of functions defined in portable.h for the Atmel ARM7 port. - *----------------------------------------------------------*/ +* Implementation of functions defined in portable.h for the Atmel ARM7 port. +*----------------------------------------------------------*/ /* Standard includes. */ @@ -51,21 +51,21 @@ /*-----------------------------------------------------------*/ /* Constants required to setup the initial stack. */ -#define portINITIAL_SPSR ( ( StackType_t ) 0x1f ) /* System mode, ARM mode, interrupts enabled. */ -#define portTHUMB_MODE_BIT ( ( StackType_t ) 0x20 ) -#define portINSTRUCTION_SIZE ( ( StackType_t ) 4 ) +#define portINITIAL_SPSR ( ( StackType_t ) 0x1f ) /* System mode, ARM mode, interrupts enabled. */ +#define portTHUMB_MODE_BIT ( ( StackType_t ) 0x20 ) +#define portINSTRUCTION_SIZE ( ( StackType_t ) 4 ) /* Constants required to setup the PIT. */ -#define port1MHz_IN_Hz ( 1000000ul ) -#define port1SECOND_IN_uS ( 1000000.0 ) +#define port1MHz_IN_Hz ( 1000000ul ) +#define port1SECOND_IN_uS ( 1000000.0 ) /* Constants required to handle critical sections. */ -#define portNO_CRITICAL_NESTING ( ( uint32_t ) 0 ) +#define portNO_CRITICAL_NESTING ( ( uint32_t ) 0 ) -#define portINT_LEVEL_SENSITIVE 0 -#define portPIT_ENABLE ( ( uint16_t ) 0x1 << 24 ) -#define portPIT_INT_ENABLE ( ( uint16_t ) 0x1 << 25 ) +#define portINT_LEVEL_SENSITIVE 0 +#define portPIT_ENABLE ( ( uint16_t ) 0x1 << 24 ) +#define portPIT_INT_ENABLE ( ( uint16_t ) 0x1 << 25 ) /*-----------------------------------------------------------*/ /* Setup the PIT to generate the tick interrupts. */ @@ -75,8 +75,8 @@ static void prvSetupTimerInterrupt( void ); static void vPortTickISR( void ); /* ulCriticalNesting will get set to zero when the first task starts. It -cannot be initialised to 0 as this will cause interrupts to be enabled -during the kernel initialisation process. */ + * cannot be initialised to 0 as this will cause interrupts to be enabled + * during the kernel initialisation process. */ uint32_t ulCriticalNesting = ( uint32_t ) 9999; /*-----------------------------------------------------------*/ @@ -87,56 +87,58 @@ uint32_t ulCriticalNesting = ( uint32_t ) 9999; * * See header file for description. */ -StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters ) +StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, + TaskFunction_t pxCode, + void * pvParameters ) { -StackType_t *pxOriginalTOS; + StackType_t * pxOriginalTOS; pxOriginalTOS = pxTopOfStack; /* To ensure asserts in tasks.c don't fail, although in this case the assert - is not really required. */ + * is not really required. */ pxTopOfStack--; /* Setup the initial stack of the task. The stack is set exactly as - expected by the portRESTORE_CONTEXT() macro. */ + * expected by the portRESTORE_CONTEXT() macro. */ /* First on the stack is the return address - which in this case is the - start of the task. The offset is added to make the return address appear - as it would within an IRQ ISR. */ + * start of the task. The offset is added to make the return address appear + * as it would within an IRQ ISR. */ *pxTopOfStack = ( StackType_t ) pxCode + portINSTRUCTION_SIZE; pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0xaaaaaaaa; /* R14 */ + *pxTopOfStack = ( StackType_t ) 0xaaaaaaaa; /* R14 */ pxTopOfStack--; *pxTopOfStack = ( StackType_t ) pxOriginalTOS; /* Stack used when task starts goes in R13. */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x12121212; /* R12 */ + *pxTopOfStack = ( StackType_t ) 0x12121212; /* R12 */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x11111111; /* R11 */ + *pxTopOfStack = ( StackType_t ) 0x11111111; /* R11 */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x10101010; /* R10 */ + *pxTopOfStack = ( StackType_t ) 0x10101010; /* R10 */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x09090909; /* R9 */ + *pxTopOfStack = ( StackType_t ) 0x09090909; /* R9 */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x08080808; /* R8 */ + *pxTopOfStack = ( StackType_t ) 0x08080808; /* R8 */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x07070707; /* R7 */ + *pxTopOfStack = ( StackType_t ) 0x07070707; /* R7 */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x06060606; /* R6 */ + *pxTopOfStack = ( StackType_t ) 0x06060606; /* R6 */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x05050505; /* R5 */ + *pxTopOfStack = ( StackType_t ) 0x05050505; /* R5 */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x04040404; /* R4 */ + *pxTopOfStack = ( StackType_t ) 0x04040404; /* R4 */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x03030303; /* R3 */ + *pxTopOfStack = ( StackType_t ) 0x03030303; /* R3 */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x02020202; /* R2 */ + *pxTopOfStack = ( StackType_t ) 0x02020202; /* R2 */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x01010101; /* R1 */ + *pxTopOfStack = ( StackType_t ) 0x01010101; /* R1 */ pxTopOfStack--; /* When the task starts is will expect to find the function parameter in - R0. */ + * R0. */ *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */ pxTopOfStack--; @@ -153,8 +155,8 @@ StackType_t *pxOriginalTOS; pxTopOfStack--; /* Interrupt flags cannot always be stored on the stack and will - instead be stored in a variable, which is then saved as part of the - tasks context. */ + * instead be stored in a variable, which is then saved as part of the + * tasks context. */ *pxTopOfStack = portNO_CRITICAL_NESTING; return pxTopOfStack; @@ -163,10 +165,10 @@ StackType_t *pxOriginalTOS; BaseType_t xPortStartScheduler( void ) { -extern void vPortStartFirstTask( void ); + extern void vPortStartFirstTask( void ); /* Start the timer that generates the tick ISR. Interrupts are disabled - here already. */ + * here already. */ prvSetupTimerInterrupt(); /* Start the first task. */ @@ -180,17 +182,17 @@ extern void vPortStartFirstTask( void ); void vPortEndScheduler( void ) { /* It is unlikely that the ARM port will require this function as there - is nothing to return to. */ + * is nothing to return to. */ } /*-----------------------------------------------------------*/ static __arm void vPortTickISR( void ) { -volatile uint32_t ulDummy; + volatile uint32_t ulDummy; /* Increment the tick count - which may wake some tasks but as the - preemptive scheduler is not being used any woken task is not given - processor time no matter what its priority. */ + * preemptive scheduler is not being used any woken task is not given + * processor time no matter what its priority. */ if( xTaskIncrementTick() != pdFALSE ) { vTaskSwitchContext(); @@ -208,7 +210,7 @@ volatile uint32_t ulDummy; static void prvSetupTimerInterrupt( void ) { -const uint32_t ulPeriodIn_uS = ( 1.0 / ( double ) configTICK_RATE_HZ ) * port1SECOND_IN_uS; + const uint32_t ulPeriodIn_uS = ( 1.0 / ( double ) configTICK_RATE_HZ ) * port1SECOND_IN_uS; /* Setup the PIT for the required frequency. */ PIT_Init( ulPeriodIn_uS, BOARD_MCK / port1MHz_IN_Hz ); @@ -226,9 +228,9 @@ void vPortEnterCritical( void ) /* Disable interrupts first! */ __disable_irq(); - /* Now interrupts are disabled ulCriticalNesting can be accessed - directly. Increment ulCriticalNesting to keep a count of how many times - portENTER_CRITICAL() has been called. */ + /* Now that interrupts are disabled, ulCriticalNesting can be accessed + * directly. Increment ulCriticalNesting to keep a count of how many times + * portENTER_CRITICAL() has been called. */ ulCriticalNesting++; } /*-----------------------------------------------------------*/ @@ -241,7 +243,7 @@ void vPortExitCritical( void ) ulCriticalNesting--; /* If the nesting level has reached zero then interrupts should be - re-enabled. */ + * re-enabled. */ if( ulCriticalNesting == portNO_CRITICAL_NESTING ) { __enable_irq(); diff --git a/Source/portable/IAR/AtmelSAM9XE/portasm.s79 b/Source/portable/IAR/AtmelSAM9XE/portasm.s79 index ed0bbf450..4dce9d7af 100644 --- a/Source/portable/IAR/AtmelSAM9XE/portasm.s79 +++ b/Source/portable/IAR/AtmelSAM9XE/portasm.s79 @@ -1,5 +1,5 @@ ;/* -; * FreeRTOS Kernel V10.6.2 +; * FreeRTOS Kernel V11.0.1 ; * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. ; * ; * SPDX-License-Identifier: MIT diff --git a/Source/portable/IAR/AtmelSAM9XE/portmacro.h b/Source/portable/IAR/AtmelSAM9XE/portmacro.h index 3878f973b..3a7f0f64e 100644 --- a/Source/portable/IAR/AtmelSAM9XE/portmacro.h +++ b/Source/portable/IAR/AtmelSAM9XE/portmacro.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -49,36 +49,36 @@ */ /* Type definitions. */ -#define portCHAR char -#define portFLOAT float -#define portDOUBLE double -#define portLONG long -#define portSHORT short -#define portSTACK_TYPE uint32_t -#define portBASE_TYPE long - -typedef portSTACK_TYPE StackType_t; -typedef long BaseType_t; -typedef unsigned long UBaseType_t; - - -#if( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS ) - typedef uint16_t TickType_t; - #define portMAX_DELAY ( TickType_t ) 0xffff +#define portCHAR char +#define portFLOAT float +#define portDOUBLE double +#define portLONG long +#define portSHORT short +#define portSTACK_TYPE uint32_t +#define portBASE_TYPE long + +typedef portSTACK_TYPE StackType_t; +typedef long BaseType_t; +typedef unsigned long UBaseType_t; + + +#if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS ) + typedef uint16_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffff #elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS ) - typedef uint32_t TickType_t; - #define portMAX_DELAY ( TickType_t ) ( 0xFFFFFFFFUL ) + typedef uint32_t TickType_t; + #define portMAX_DELAY ( TickType_t ) ( 0xFFFFFFFFUL ) #else #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width. #endif /*-----------------------------------------------------------*/ /* Hardware specifics. */ -#define portSTACK_GROWTH ( -1 ) -#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) -#define portBYTE_ALIGNMENT 8 -#define portYIELD() asm ( "SWI 0" ) -#define portNOP() asm ( "NOP" ) +#define portSTACK_GROWTH ( -1 ) +#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) +#define portBYTE_ALIGNMENT 8 +#define portYIELD() asm ( "SWI 0" ) +#define portNOP() asm ( "NOP" ) /*-----------------------------------------------------------*/ /* Critical section handling. */ @@ -94,21 +94,26 @@ __arm __interwork void vPortExitCritical( void ); /*-----------------------------------------------------------*/ /* Task utilities. */ -#define portEND_SWITCHING_ISR( xSwitchRequired ) \ -{ \ -extern void vTaskSwitchContext( void ); \ - \ - if( xSwitchRequired ) \ - { \ - vTaskSwitchContext(); \ - } \ -} +#define portEND_SWITCHING_ISR( xSwitchRequired ) \ + { \ + extern void vTaskSwitchContext( void ); \ + \ + if( xSwitchRequired ) \ + { \ + traceISR_EXIT_TO_SCHEDULER(); \ + vTaskSwitchContext(); \ + } \ + else \ + { \ + traceISR_EXIT(); \ + } \ + } /*-----------------------------------------------------------*/ /* Task function macros as described on the FreeRTOS.org WEB site. */ -#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters ) -#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters ) +#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters ) +#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters ) /* *INDENT-OFF* */ #ifdef __cplusplus diff --git a/Source/portable/IAR/LPC2000/ISR_Support.h b/Source/portable/IAR/LPC2000/ISR_Support.h index f6b701a11..3aa820266 100644 --- a/Source/portable/IAR/LPC2000/ISR_Support.h +++ b/Source/portable/IAR/LPC2000/ISR_Support.h @@ -1,105 +1,151 @@ -;/* -; * FreeRTOS Kernel V10.6.2 -; * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. -; * -; * SPDX-License-Identifier: MIT -; * -; * Permission is hereby granted, free of charge, to any person obtaining a copy of -; * this software and associated documentation files (the "Software"), to deal in -; * the Software without restriction, including without limitation the rights to -; * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of -; * the Software, and to permit persons to whom the Software is furnished to do so, -; * subject to the following conditions: -; * -; * The above copyright notice and this permission notice shall be included in all -; * copies or substantial portions of the Software. -; * -; * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -; * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS -; * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR -; * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER -; * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN -; * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. -; * -; * https://www.FreeRTOS.org -; * https://github.com/FreeRTOS -; * -; */ - - EXTERN pxCurrentTCB - EXTERN ulCriticalNesting - -;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -; Context save and restore macro definitions -;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +; /* + * ; * FreeRTOS Kernel V11.0.1 + * ; * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * ; * + * ; * SPDX-License-Identifier: MIT + * ; * + * ; * Permission is hereby granted, free of charge, to any person obtaining a copy of + * ; * this software and associated documentation files (the "Software"), to deal in + * ; * the Software without restriction, including without limitation the rights to + * ; * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * ; * the Software, and to permit persons to whom the Software is furnished to do so, + * ; * subject to the following conditions: + * ; * + * ; * The above copyright notice and this permission notice shall be included in all + * ; * copies or substantial portions of the Software. + * ; * + * ; * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * ; * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * ; * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * ; * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * ; * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * ; * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * ; * + * ; * https://www.FreeRTOS.org + * ; * https://github.com/FreeRTOS + * ; * + * ; */ + +EXTERN pxCurrentTCB +EXTERN ulCriticalNesting + +; +Context save and restore macro definitions +; portSAVE_CONTEXT MACRO - ; Push R0 as we are going to use the register. - STMDB SP!, {R0} +; +Push R0 as we are going to use the register. + STMDB SP !, { + R0 +} + +Set R0 to point to the task stack pointer. + STMDB SP, { + SP +} +^ +NOP +SUB SP, SP, # 4 +LDMIA SP !, { + R0 +} + +; +Push the return address onto the stack. + STMDB R0 !, { + LR + } + + Now we have saved LR we can use it instead of R0. + MOV LR, R0 + +; + +Pop R0 so we can save it onto the system mode stack. + LDMIA SP !, { + R0 +} + +Push all the system mode registers onto the task stack. + STMDB LR, { + R0 - LR +} +^ +NOP +SUB LR, LR, # 60 + +; +Push the SPSR onto the task stack. + MRS R0, SPSR +STMDB LR !, { + R0 +} + +LDR R0, = ulCriticalNesting + LDR R0, [ R0 ] +STMDB LR !, { + R0 +} + +Store the new top of stack + +for the task. + LDR R1, = pxCurrentTCB + LDR R0, [ R1 ] +STR LR, [ R0 ] + +ENDM - ; Set R0 to point to the task stack pointer. - STMDB SP, {SP}^ - NOP - SUB SP, SP, #4 - LDMIA SP!, {R0} - ; Push the return address onto the stack. - STMDB R0!, {LR} - - ; Now we have saved LR we can use it instead of R0. - MOV LR, R0 - - ; Pop R0 so we can save it onto the system mode stack. - LDMIA SP!, {R0} - - ; Push all the system mode registers onto the task stack. - STMDB LR, {R0-LR}^ - NOP - SUB LR, LR, #60 - - ; Push the SPSR onto the task stack. - MRS R0, SPSR - STMDB LR!, {R0} +portRESTORE_CONTEXT MACRO - LDR R0, =ulCriticalNesting - LDR R0, [R0] - STMDB LR!, {R0} +; +Set the LR to the task stack. + LDR R1, = pxCurrentTCB + LDR R0, [ R1 ] +LDR LR, [ R0 ] - ; Store the new top of stack for the task. - LDR R1, =pxCurrentTCB - LDR R0, [R1] - STR LR, [R0] +; +The critical nesting depth is the first item on the stack. + ; +Load it into the ulCriticalNesting variable. + LDR R0, = ulCriticalNesting + LDMFD LR !, { + R1 +} - ENDM +STR R1, [ R0 ] +; +Get the SPSR from the stack. + LDMFD LR !, { + R0 +} +MSR SPSR_cxsf, R0 -portRESTORE_CONTEXT MACRO +; +Restore all system mode registers - ; Set the LR to the task stack. - LDR R1, =pxCurrentTCB - LDR R0, [R1] - LDR LR, [R0] +for the task. + LDMFD LR, { + R0 - R14 +} - ; The critical nesting depth is the first item on the stack. - ; Load it into the ulCriticalNesting variable. - LDR R0, =ulCriticalNesting - LDMFD LR!, {R1} - STR R1, [R0] +^ +NOP - ; Get the SPSR from the stack. - LDMFD LR!, {R0} - MSR SPSR_cxsf, R0 +; +Restore the return address. + LDR LR, [ LR, # + 60 ] - ; Restore all system mode registers for the task. - LDMFD LR, {R0-R14}^ - NOP +; - ; Restore the return address. - LDR LR, [LR, #+60] +And return -correcting the offset in the LR to obtain the +; - ; And return - correcting the offset in the LR to obtain the - ; correct address. - SUBS PC, LR, #4 +correct address. + SUBS PC, LR, # 4 - ENDM +ENDM diff --git a/Source/portable/IAR/LPC2000/port.c b/Source/portable/IAR/LPC2000/port.c index 55ef3e3d2..75259b70f 100644 --- a/Source/portable/IAR/LPC2000/port.c +++ b/Source/portable/IAR/LPC2000/port.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -27,16 +27,16 @@ */ /*----------------------------------------------------------- - * Implementation of functions defined in portable.h for the Philips ARM7 port. - *----------------------------------------------------------*/ +* Implementation of functions defined in portable.h for the Philips ARM7 port. +*----------------------------------------------------------*/ /* - Changes from V3.2.2 - - + Bug fix - The prescale value for the timer setup is now written to T0PR - instead of T0PC. This bug would have had no effect unless a prescale - value was actually used. -*/ + * Changes from V3.2.2 + * + + Bug fix - The prescale value for the timer setup is now written to T0PR + + instead of T0PC. This bug would have had no effect unless a prescale + + value was actually used. + */ /* Standard includes. */ #include @@ -47,36 +47,36 @@ #include "task.h" /* Constants required to setup the tick ISR. */ -#define portENABLE_TIMER ( ( uint8_t ) 0x01 ) -#define portPRESCALE_VALUE 0x00 -#define portINTERRUPT_ON_MATCH ( ( uint32_t ) 0x01 ) -#define portRESET_COUNT_ON_MATCH ( ( uint32_t ) 0x02 ) +#define portENABLE_TIMER ( ( uint8_t ) 0x01 ) +#define portPRESCALE_VALUE 0x00 +#define portINTERRUPT_ON_MATCH ( ( uint32_t ) 0x01 ) +#define portRESET_COUNT_ON_MATCH ( ( uint32_t ) 0x02 ) /* Constants required to setup the initial stack. */ -#define portINITIAL_SPSR ( ( StackType_t ) 0x1f ) /* System mode, ARM mode, interrupts enabled. */ -#define portTHUMB_MODE_BIT ( ( StackType_t ) 0x20 ) -#define portINSTRUCTION_SIZE ( ( StackType_t ) 4 ) +#define portINITIAL_SPSR ( ( StackType_t ) 0x1f ) /* System mode, ARM mode, interrupts enabled. */ +#define portTHUMB_MODE_BIT ( ( StackType_t ) 0x20 ) +#define portINSTRUCTION_SIZE ( ( StackType_t ) 4 ) /* Constants required to setup the PIT. */ -#define portPIT_CLOCK_DIVISOR ( ( uint32_t ) 16 ) -#define portPIT_COUNTER_VALUE ( ( ( configCPU_CLOCK_HZ / portPIT_CLOCK_DIVISOR ) / 1000UL ) * portTICK_PERIOD_MS ) +#define portPIT_CLOCK_DIVISOR ( ( uint32_t ) 16 ) +#define portPIT_COUNTER_VALUE ( ( ( configCPU_CLOCK_HZ / portPIT_CLOCK_DIVISOR ) / 1000UL ) * portTICK_PERIOD_MS ) /* Constants required to handle interrupts. */ -#define portTIMER_MATCH_ISR_BIT ( ( uint8_t ) 0x01 ) -#define portCLEAR_VIC_INTERRUPT ( ( uint32_t ) 0 ) +#define portTIMER_MATCH_ISR_BIT ( ( uint8_t ) 0x01 ) +#define portCLEAR_VIC_INTERRUPT ( ( uint32_t ) 0 ) /* Constants required to handle critical sections. */ -#define portNO_CRITICAL_NESTING ( ( uint32_t ) 0 ) +#define portNO_CRITICAL_NESTING ( ( uint32_t ) 0 ) -#define portINT_LEVEL_SENSITIVE 0 -#define portPIT_ENABLE ( ( uint16_t ) 0x1 << 24 ) -#define portPIT_INT_ENABLE ( ( uint16_t ) 0x1 << 25 ) +#define portINT_LEVEL_SENSITIVE 0 +#define portPIT_ENABLE ( ( uint16_t ) 0x1 << 24 ) +#define portPIT_INT_ENABLE ( ( uint16_t ) 0x1 << 25 ) /* Constants required to setup the VIC for the tick ISR. */ -#define portTIMER_VIC_CHANNEL ( ( uint32_t ) 0x0004 ) -#define portTIMER_VIC_CHANNEL_BIT ( ( uint32_t ) 0x0010 ) -#define portTIMER_VIC_ENABLE ( ( uint32_t ) 0x0020 ) +#define portTIMER_VIC_CHANNEL ( ( uint32_t ) 0x0004 ) +#define portTIMER_VIC_CHANNEL_BIT ( ( uint32_t ) 0x0010 ) +#define portTIMER_VIC_ENABLE ( ( uint32_t ) 0x0020 ) /*-----------------------------------------------------------*/ @@ -84,8 +84,8 @@ static void prvSetupTimerInterrupt( void ); /* ulCriticalNesting will get set to zero when the first task starts. It -cannot be initialised to 0 as this will cause interrupts to be enabled -during the kernel initialisation process. */ + * cannot be initialised to 0 as this will cause interrupts to be enabled + * during the kernel initialisation process. */ uint32_t ulCriticalNesting = ( uint32_t ) 9999; /*-----------------------------------------------------------*/ @@ -96,52 +96,54 @@ uint32_t ulCriticalNesting = ( uint32_t ) 9999; * * See header file for description. */ -StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters ) +StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, + TaskFunction_t pxCode, + void * pvParameters ) { -StackType_t *pxOriginalTOS; + StackType_t * pxOriginalTOS; pxOriginalTOS = pxTopOfStack; /* Setup the initial stack of the task. The stack is set exactly as - expected by the portRESTORE_CONTEXT() macro. */ + * expected by the portRESTORE_CONTEXT() macro. */ /* First on the stack is the return address - which in this case is the - start of the task. The offset is added to make the return address appear - as it would within an IRQ ISR. */ + * start of the task. The offset is added to make the return address appear + * as it would within an IRQ ISR. */ *pxTopOfStack = ( StackType_t ) pxCode + portINSTRUCTION_SIZE; pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0xaaaaaaaa; /* R14 */ + *pxTopOfStack = ( StackType_t ) 0xaaaaaaaa; /* R14 */ pxTopOfStack--; *pxTopOfStack = ( StackType_t ) pxOriginalTOS; /* Stack used when task starts goes in R13. */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x12121212; /* R12 */ + *pxTopOfStack = ( StackType_t ) 0x12121212; /* R12 */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x11111111; /* R11 */ + *pxTopOfStack = ( StackType_t ) 0x11111111; /* R11 */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x10101010; /* R10 */ + *pxTopOfStack = ( StackType_t ) 0x10101010; /* R10 */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x09090909; /* R9 */ + *pxTopOfStack = ( StackType_t ) 0x09090909; /* R9 */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x08080808; /* R8 */ + *pxTopOfStack = ( StackType_t ) 0x08080808; /* R8 */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x07070707; /* R7 */ + *pxTopOfStack = ( StackType_t ) 0x07070707; /* R7 */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x06060606; /* R6 */ + *pxTopOfStack = ( StackType_t ) 0x06060606; /* R6 */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x05050505; /* R5 */ + *pxTopOfStack = ( StackType_t ) 0x05050505; /* R5 */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x04040404; /* R4 */ + *pxTopOfStack = ( StackType_t ) 0x04040404; /* R4 */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x03030303; /* R3 */ + *pxTopOfStack = ( StackType_t ) 0x03030303; /* R3 */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x02020202; /* R2 */ + *pxTopOfStack = ( StackType_t ) 0x02020202; /* R2 */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x01010101; /* R1 */ + *pxTopOfStack = ( StackType_t ) 0x01010101; /* R1 */ pxTopOfStack--; /* When the task starts is will expect to find the function parameter in - R0. */ + * R0. */ *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */ pxTopOfStack--; @@ -157,8 +159,8 @@ StackType_t *pxOriginalTOS; pxTopOfStack--; /* Interrupt flags cannot always be stored on the stack and will - instead be stored in a variable, which is then saved as part of the - tasks context. */ + * instead be stored in a variable, which is then saved as part of the + * tasks context. */ *pxTopOfStack = portNO_CRITICAL_NESTING; return pxTopOfStack; @@ -167,10 +169,10 @@ StackType_t *pxOriginalTOS; BaseType_t xPortStartScheduler( void ) { -extern void vPortStartFirstTask( void ); + extern void vPortStartFirstTask( void ); /* Start the timer that generates the tick ISR. Interrupts are disabled - here already. */ + * here already. */ prvSetupTimerInterrupt(); /* Start the first task. */ @@ -184,20 +186,20 @@ extern void vPortStartFirstTask( void ); void vPortEndScheduler( void ) { /* It is unlikely that the ARM port will require this function as there - is nothing to return to. */ + * is nothing to return to. */ } /*-----------------------------------------------------------*/ #if configUSE_PREEMPTION == 0 - /* The cooperative scheduler requires a normal IRQ service routine to - simply increment the system tick. */ +/* The cooperative scheduler requires a normal IRQ service routine to + * simply increment the system tick. */ static __arm __irq void vPortNonPreemptiveTick( void ); static __arm __irq void vPortNonPreemptiveTick( void ) { /* Increment the tick count - which may wake some tasks but as the - preemptive scheduler is not being used any woken task is not given - processor time no matter what its priority. */ + * preemptive scheduler is not being used any woken task is not given + * processor time no matter what its priority. */ xTaskIncrementTick(); /* Ready for the next interrupt. */ @@ -205,10 +207,10 @@ void vPortEndScheduler( void ) VICVectAddr = portCLEAR_VIC_INTERRUPT; } -#else +#else /* if configUSE_PREEMPTION == 0 */ - /* This function is called from an asm wrapper, so does not require the __irq - keyword. */ +/* This function is called from an asm wrapper, so does not require the __irq + * keyword. */ void vPortPreemptiveTick( void ); void vPortPreemptiveTick( void ) { @@ -216,8 +218,8 @@ void vPortEndScheduler( void ) if( xTaskIncrementTick() != pdFALSE ) { /* The new tick value might unblock a task. Ensure the highest task that - is ready to execute is the task that will execute when the tick ISR - exits. */ + * is ready to execute is the task that will execute when the tick ISR + * exits. */ vTaskSwitchContext(); } @@ -226,23 +228,23 @@ void vPortEndScheduler( void ) VICVectAddr = portCLEAR_VIC_INTERRUPT; } -#endif +#endif /* if configUSE_PREEMPTION == 0 */ /*-----------------------------------------------------------*/ static void prvSetupTimerInterrupt( void ) { -uint32_t ulCompareMatch; + uint32_t ulCompareMatch; /* A 1ms tick does not require the use of the timer prescale. This is - defaulted to zero but can be used if necessary. */ + * defaulted to zero but can be used if necessary. */ T0PR = portPRESCALE_VALUE; /* Calculate the match value required for our wanted tick rate. */ ulCompareMatch = configCPU_CLOCK_HZ / configTICK_RATE_HZ; /* Protect against divide by zero. Using an if() statement still results - in a warning - hence the #if. */ + * in a warning - hence the #if. */ #if portPRESCALE_VALUE != 0 { ulCompareMatch /= ( portPRESCALE_VALUE + 1 ); @@ -259,25 +261,25 @@ uint32_t ulCompareMatch; VICIntEnable |= portTIMER_VIC_CHANNEL_BIT; /* The ISR installed depends on whether the preemptive or cooperative - scheduler is being used. */ + * scheduler is being used. */ #if configUSE_PREEMPTION == 1 { - extern void ( vPortPreemptiveTickEntry )( void ); + extern void( vPortPreemptiveTickEntry )( void ); VICVectAddr0 = ( uint32_t ) vPortPreemptiveTickEntry; } #else { - extern void ( vNonPreemptiveTick )( void ); + extern void( vNonPreemptiveTick )( void ); VICVectAddr0 = ( int32_t ) vPortNonPreemptiveTick; } - #endif + #endif /* if configUSE_PREEMPTION == 1 */ VICVectCntl0 = portTIMER_VIC_CHANNEL | portTIMER_VIC_ENABLE; /* Start the timer - interrupts are disabled when this function is called - so it is okay to do this here. */ + * so it is okay to do this here. */ T0TCR = portENABLE_TIMER; } /*-----------------------------------------------------------*/ @@ -287,9 +289,9 @@ void vPortEnterCritical( void ) /* Disable interrupts first! */ __disable_interrupt(); - /* Now interrupts are disabled ulCriticalNesting can be accessed - directly. Increment ulCriticalNesting to keep a count of how many times - portENTER_CRITICAL() has been called. */ + /* Now that interrupts are disabled, ulCriticalNesting can be accessed + * directly. Increment ulCriticalNesting to keep a count of how many times + * portENTER_CRITICAL() has been called. */ ulCriticalNesting++; } /*-----------------------------------------------------------*/ @@ -302,7 +304,7 @@ void vPortExitCritical( void ) ulCriticalNesting--; /* If the nesting level has reached zero then interrupts should be - re-enabled. */ + * re-enabled. */ if( ulCriticalNesting == portNO_CRITICAL_NESTING ) { __enable_interrupt(); diff --git a/Source/portable/IAR/LPC2000/portasm.s79 b/Source/portable/IAR/LPC2000/portasm.s79 index e6a1b7cfa..04c3425f8 100644 --- a/Source/portable/IAR/LPC2000/portasm.s79 +++ b/Source/portable/IAR/LPC2000/portasm.s79 @@ -1,5 +1,5 @@ ;/* -; * FreeRTOS Kernel V10.6.2 +; * FreeRTOS Kernel V11.0.1 ; * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. ; * ; * SPDX-License-Identifier: MIT diff --git a/Source/portable/IAR/LPC2000/portmacro.h b/Source/portable/IAR/LPC2000/portmacro.h index 2ef544913..69192d0a9 100644 --- a/Source/portable/IAR/LPC2000/portmacro.h +++ b/Source/portable/IAR/LPC2000/portmacro.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -49,36 +49,36 @@ */ /* Type definitions. */ -#define portCHAR char -#define portFLOAT float -#define portDOUBLE double -#define portLONG long -#define portSHORT short -#define portSTACK_TYPE uint32_t -#define portBASE_TYPE long - -typedef portSTACK_TYPE StackType_t; -typedef long BaseType_t; -typedef unsigned long UBaseType_t; - - -#if( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS ) - typedef uint16_t TickType_t; - #define portMAX_DELAY ( TickType_t ) 0xffff +#define portCHAR char +#define portFLOAT float +#define portDOUBLE double +#define portLONG long +#define portSHORT short +#define portSTACK_TYPE uint32_t +#define portBASE_TYPE long + +typedef portSTACK_TYPE StackType_t; +typedef long BaseType_t; +typedef unsigned long UBaseType_t; + + +#if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS ) + typedef uint16_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffff #elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS ) - typedef uint32_t TickType_t; - #define portMAX_DELAY ( TickType_t ) ( 0xFFFFFFFFUL ) + typedef uint32_t TickType_t; + #define portMAX_DELAY ( TickType_t ) ( 0xFFFFFFFFUL ) #else #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width. #endif /*-----------------------------------------------------------*/ /* Hardware specifics. */ -#define portSTACK_GROWTH ( -1 ) -#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) -#define portBYTE_ALIGNMENT 8 -#define portYIELD() asm ( "SWI 0" ) -#define portNOP() asm ( "NOP" ) +#define portSTACK_GROWTH ( -1 ) +#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) +#define portBYTE_ALIGNMENT 8 +#define portYIELD() asm ( "SWI 0" ) +#define portNOP() asm ( "NOP" ) /*-----------------------------------------------------------*/ /* Critical section handling. */ @@ -94,20 +94,25 @@ __arm __interwork void vPortExitCritical( void ); /*-----------------------------------------------------------*/ /* Task utilities. */ -#define portEND_SWITCHING_ISR( xSwitchRequired ) \ -{ \ -extern void vTaskSwitchContext( void ); \ - \ - if( xSwitchRequired ) \ - { \ - vTaskSwitchContext(); \ - } \ -} +#define portEND_SWITCHING_ISR( xSwitchRequired ) \ + { \ + extern void vTaskSwitchContext( void ); \ + \ + if( xSwitchRequired ) \ + { \ + traceISR_EXIT_TO_SCHEDULER(); \ + vTaskSwitchContext(); \ + } \ + else \ + { \ + traceISR_EXIT(); \ + } \ + } /*-----------------------------------------------------------*/ /* Task function macros as described on the FreeRTOS.org WEB site. */ -#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters ) -#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters ) +#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters ) +#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters ) /* *INDENT-OFF* */ #ifdef __cplusplus diff --git a/Source/portable/IAR/MSP430/port.c b/Source/portable/IAR/MSP430/port.c index ff78ad4c3..413777343 100644 --- a/Source/portable/IAR/MSP430/port.c +++ b/Source/portable/IAR/MSP430/port.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -31,28 +31,28 @@ #include "task.h" /*----------------------------------------------------------- - * Implementation of functions defined in portable.h for the MSP430 port. - *----------------------------------------------------------*/ +* Implementation of functions defined in portable.h for the MSP430 port. +*----------------------------------------------------------*/ /* Constants required for hardware setup. The tick ISR runs off the ACLK, -not the MCLK. */ + * not the MCLK. */ #define portACLK_FREQUENCY_HZ ( ( TickType_t ) 32768 ) #define portINITIAL_CRITICAL_NESTING ( ( uint16_t ) 10 ) #define portFLAGS_INT_ENABLED ( ( StackType_t ) 0x08 ) /* We require the address of the pxCurrentTCB variable, but don't want to know -any details of its type. */ + * any details of its type. */ typedef void TCB_t; extern volatile TCB_t * volatile pxCurrentTCB; /* Each task maintains a count of the critical section nesting depth. Each -time a critical section is entered the count is incremented. Each time a -critical section is exited the count is decremented - with interrupts only -being re-enabled if the count is zero. - -usCriticalNesting will get set to zero when the scheduler starts, but must -not be initialised to zero as this will cause problems during the startup -sequence. */ + * time a critical section is entered the count is incremented. Each time a + * critical section is exited the count is decremented - with interrupts only + * being re-enabled if the count is zero. + * + * usCriticalNesting will get set to zero when the scheduler starts, but must + * not be initialised to zero as this will cause problems during the startup + * sequence. */ volatile uint16_t usCriticalNesting = portINITIAL_CRITICAL_NESTING; /*-----------------------------------------------------------*/ @@ -70,24 +70,26 @@ void vPortSetupTimerInterrupt( void ); * * See the header file portable.h. */ -StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters ) +StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, + TaskFunction_t pxCode, + void * pvParameters ) { /* - Place a few bytes of known values on the bottom of the stack. - This is just useful for debugging and can be included if required. - - *pxTopOfStack = ( StackType_t ) 0x1111; - pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x2222; - pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x3333; - pxTopOfStack--; - */ + * Place a few bytes of known values on the bottom of the stack. + * This is just useful for debugging and can be included if required. + * + * pxTopOfStack = ( StackType_t ) 0x1111; + * pxTopOfStack--; + * pxTopOfStack = ( StackType_t ) 0x2222; + * pxTopOfStack--; + * pxTopOfStack = ( StackType_t ) 0x3333; + * pxTopOfStack--; + */ /* The msp430 automatically pushes the PC then SR onto the stack before - executing an ISR. We want the stack to look just as if this has happened - so place a pointer to the start of the task on the stack first - followed - by the flags we want the task to use when it starts up. */ + * executing an ISR. We want the stack to look just as if this has happened + * so place a pointer to the start of the task on the stack first - followed + * by the flags we want the task to use when it starts up. */ *pxTopOfStack = ( StackType_t ) pxCode; pxTopOfStack--; *pxTopOfStack = portFLAGS_INT_ENABLED; @@ -112,7 +114,7 @@ StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t px pxTopOfStack--; /* When the task starts is will expect to find the function parameter in - R15. */ + * R15. */ *pxTopOfStack = ( StackType_t ) pvParameters; pxTopOfStack--; @@ -124,12 +126,12 @@ StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t px pxTopOfStack--; /* A variable is used to keep track of the critical section nesting. - This variable has to be stored as part of the task context and is - initially set to zero. */ + * This variable has to be stored as part of the task context and is + * initially set to zero. */ *pxTopOfStack = ( StackType_t ) portNO_CRITICAL_SECTION_NESTING; /* Return a pointer to the top of the stack we have generated so this can - be stored in the task control block for the task. */ + * be stored in the task control block for the task. */ return pxTopOfStack; } /*-----------------------------------------------------------*/ @@ -137,7 +139,7 @@ StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t px void vPortEndScheduler( void ) { /* It is unlikely that the MSP430 port will get stopped. If required simply - disable the tick interrupt here. */ + * disable the tick interrupt here. */ } /*-----------------------------------------------------------*/ @@ -169,6 +171,3 @@ void vPortSetupTimerInterrupt( void ) TACTL |= MC_1; } /*-----------------------------------------------------------*/ - - - diff --git a/Source/portable/IAR/MSP430/portasm.h b/Source/portable/IAR/MSP430/portasm.h index 34b91e6d5..2868ed97c 100644 --- a/Source/portable/IAR/MSP430/portasm.h +++ b/Source/portable/IAR/MSP430/portasm.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -31,54 +31,54 @@ portSAVE_CONTEXT macro - IMPORT pxCurrentTCB - IMPORT usCriticalNesting +IMPORT pxCurrentTCB +IMPORT usCriticalNesting - /* Save the remaining registers. */ - push r4 - push r5 - push r6 - push r7 - push r8 - push r9 - push r10 - push r11 - push r12 - push r13 - push r14 - push r15 - mov.w &usCriticalNesting, r14 - push r14 - mov.w &pxCurrentTCB, r12 - mov.w r1, 0(r12) - endm +/* Save the remaining registers. */ +push r4 +push r5 +push r6 +push r7 +push r8 +push r9 +push r10 +push r11 +push r12 +push r13 +push r14 +push r15 +mov.w &usCriticalNesting, r14 +push r14 + mov.w &pxCurrentTCB, r12 + mov.w r1, 0 ( r12 ) +endm /*-----------------------------------------------------------*/ portRESTORE_CONTEXT macro - mov.w &pxCurrentTCB, r12 - mov.w @r12, r1 - pop r15 - mov.w r15, &usCriticalNesting - pop r15 - pop r14 - pop r13 - pop r12 - pop r11 - pop r10 - pop r9 - pop r8 - pop r7 - pop r6 - pop r5 - pop r4 +mov.w & pxCurrentTCB, r12 +mov.w @r12, r1 +pop r15 +mov.w r15, &usCriticalNesting +pop r15 +pop r14 +pop r13 +pop r12 +pop r11 +pop r10 +pop r9 +pop r8 +pop r7 +pop r6 +pop r5 +pop r4 - /* The last thing on the stack will be the status register. - Ensure the power down bits are clear ready for the next - time this power down register is popped from the stack. */ - bic.w #0xf0,0(SP) +/* The last thing on the stack will be the status register. + * Ensure the power down bits are clear ready for the next + * time this power down register is popped from the stack. */ +bic.w # 0xf0, 0 ( SP ) - reti - endm +reti +endm /*-----------------------------------------------------------*/ -#endif +#endif /* ifndef PORTASM_H */ diff --git a/Source/portable/IAR/MSP430/portext.s43 b/Source/portable/IAR/MSP430/portext.s43 index 43e634cc2..d73d03234 100644 --- a/Source/portable/IAR/MSP430/portext.s43 +++ b/Source/portable/IAR/MSP430/portext.s43 @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/Source/portable/IAR/MSP430/portmacro.h b/Source/portable/IAR/MSP430/portmacro.h index f93c4c451..24b097c81 100644 --- a/Source/portable/IAR/MSP430/portmacro.h +++ b/Source/portable/IAR/MSP430/portmacro.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -40,25 +40,25 @@ */ /* Type definitions. */ -#define portCHAR char -#define portFLOAT float -#define portDOUBLE double -#define portLONG long -#define portSHORT int -#define portSTACK_TYPE uint16_t -#define portBASE_TYPE short - -typedef portSTACK_TYPE StackType_t; -typedef short BaseType_t; -typedef unsigned short UBaseType_t; - - -#if( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS ) - typedef uint16_t TickType_t; - #define portMAX_DELAY ( TickType_t ) 0xffff +#define portCHAR char +#define portFLOAT float +#define portDOUBLE double +#define portLONG long +#define portSHORT int +#define portSTACK_TYPE uint16_t +#define portBASE_TYPE short + +typedef portSTACK_TYPE StackType_t; +typedef short BaseType_t; +typedef unsigned short UBaseType_t; + + +#if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS ) + typedef uint16_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffff #elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS ) - typedef uint32_t TickType_t; - #define portMAX_DELAY ( TickType_t ) ( 0xFFFFFFFFUL ) + typedef uint32_t TickType_t; + #define portMAX_DELAY ( TickType_t ) ( 0xFFFFFFFFUL ) #else #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width. #endif @@ -71,37 +71,37 @@ typedef unsigned short UBaseType_t; /*-----------------------------------------------------------*/ /* Critical section control macros. */ -#define portNO_CRITICAL_SECTION_NESTING ( ( uint16_t ) 0 ) - -#define portENTER_CRITICAL() \ -{ \ -extern volatile uint16_t usCriticalNesting; \ - \ - portDISABLE_INTERRUPTS(); \ - \ - /* Now interrupts are disabled usCriticalNesting can be accessed */ \ - /* directly. Increment ulCriticalNesting to keep a count of how many */ \ - /* times portENTER_CRITICAL() has been called. */ \ - usCriticalNesting++; \ -} - -#define portEXIT_CRITICAL() \ -{ \ -extern volatile uint16_t usCriticalNesting; \ - \ - if( usCriticalNesting > portNO_CRITICAL_SECTION_NESTING ) \ - { \ - /* Decrement the nesting count as we are leaving a critical section. */ \ - usCriticalNesting--; \ - \ - /* If the nesting level has reached zero then interrupts should be */ \ - /* re-enabled. */ \ - if( usCriticalNesting == portNO_CRITICAL_SECTION_NESTING ) \ - { \ - portENABLE_INTERRUPTS(); \ - } \ - } \ -} +#define portNO_CRITICAL_SECTION_NESTING ( ( uint16_t ) 0 ) + +#define portENTER_CRITICAL() \ + { \ + extern volatile uint16_t usCriticalNesting; \ + \ + portDISABLE_INTERRUPTS(); \ + \ + /* Now interrupts are disabled usCriticalNesting can be accessed */ \ + /* directly. Increment ulCriticalNesting to keep a count of how many */ \ + /* times portENTER_CRITICAL() has been called. */ \ + usCriticalNesting++; \ + } + +#define portEXIT_CRITICAL() \ + { \ + extern volatile uint16_t usCriticalNesting; \ + \ + if( usCriticalNesting > portNO_CRITICAL_SECTION_NESTING ) \ + { \ + /* Decrement the nesting count as we are leaving a critical section. */ \ + usCriticalNesting--; \ + \ + /* If the nesting level has reached zero then interrupts should be */ \ + /* re-enabled. */ \ + if( usCriticalNesting == portNO_CRITICAL_SECTION_NESTING ) \ + { \ + portENABLE_INTERRUPTS(); \ + } \ + } \ + } /*-----------------------------------------------------------*/ /* Task utilities. */ @@ -110,25 +110,25 @@ extern volatile uint16_t usCriticalNesting; \ * Manual context switch called by portYIELD or taskYIELD. */ extern void vPortYield( void ); -#define portYIELD() vPortYield() +#define portYIELD() vPortYield() /*-----------------------------------------------------------*/ /* Hardware specifics. */ -#define portBYTE_ALIGNMENT 2 -#define portSTACK_GROWTH ( -1 ) -#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) +#define portBYTE_ALIGNMENT 2 +#define portSTACK_GROWTH ( -1 ) +#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) #define portNOP() -#define portPOINTER_SIZE_TYPE uint16_t +#define portPOINTER_SIZE_TYPE uint16_t /*-----------------------------------------------------------*/ /* Task function macros as described on the FreeRTOS.org WEB site. */ -#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters ) -#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters ) +#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters ) +#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters ) #if configINTERRUPT_EXAMPLE_METHOD == 2 -extern void vTaskSwitchContext( void ); -#define portYIELD_FROM_ISR( x ) do { if( x ) vTaskSwitchContext(); } while( 0 ) + extern void vTaskSwitchContext( void ); + #define portYIELD_FROM_ISR( x ) do { if( x ) vTaskSwitchContext( ); } while( 0 ) #endif diff --git a/Source/portable/IAR/MSP430X/data_model.h b/Source/portable/IAR/MSP430X/data_model.h index b2b39bc3f..0dd902d62 100644 --- a/Source/portable/IAR/MSP430X/data_model.h +++ b/Source/portable/IAR/MSP430X/data_model.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -30,30 +30,30 @@ #define DATA_MODEL_H #if __DATA_MODEL__ == __DATA_MODEL_SMALL__ - #define pushm_x pushm.w - #define popm_x popm.w - #define push_x push.w - #define pop_x pop.w - #define mov_x mov.w - #define cmp_x cmp.w + #define pushm_x pushm.w + #define popm_x popm.w + #define push_x push.w + #define pop_x pop.w + #define mov_x mov.w + #define cmp_x cmp.w #endif #if __DATA_MODEL__ == __DATA_MODEL_MEDIUM__ - #define pushm_x pushm.a - #define popm_x popm.a - #define push_x pushx.a - #define pop_x popx.a - #define mov_x mov.w - #define cmp_x cmp.w + #define pushm_x pushm.a + #define popm_x popm.a + #define push_x pushx.a + #define pop_x popx.a + #define mov_x mov.w + #define cmp_x cmp.w #endif #if __DATA_MODEL__ == __DATA_MODEL_LARGE__ - #define pushm_x pushm.a - #define popm_x popm.a - #define push_x pushx.a - #define pop_x popx.a - #define mov_x movx.a - #define cmp_x cmpx.a + #define pushm_x pushm.a + #define popm_x popm.a + #define push_x pushx.a + #define pop_x popx.a + #define mov_x movx.a + #define cmp_x cmpx.a #endif #ifndef pushm_x diff --git a/Source/portable/IAR/MSP430X/port.c b/Source/portable/IAR/MSP430X/port.c index 90bb8af64..126ee7fd3 100644 --- a/Source/portable/IAR/MSP430X/port.c +++ b/Source/portable/IAR/MSP430X/port.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -31,28 +31,28 @@ #include "task.h" /*----------------------------------------------------------- - * Implementation of functions defined in portable.h for the MSP430X port. - *----------------------------------------------------------*/ +* Implementation of functions defined in portable.h for the MSP430X port. +*----------------------------------------------------------*/ /* Constants required for hardware setup. The tick ISR runs off the ACLK, -not the MCLK. */ + * not the MCLK. */ #define portACLK_FREQUENCY_HZ ( ( TickType_t ) 32768 ) #define portINITIAL_CRITICAL_NESTING ( ( uint16_t ) 10 ) #define portFLAGS_INT_ENABLED ( ( StackType_t ) 0x08 ) /* We require the address of the pxCurrentTCB variable, but don't want to know -any details of its type. */ + * any details of its type. */ typedef void TCB_t; extern volatile TCB_t * volatile pxCurrentTCB; /* Each task maintains a count of the critical section nesting depth. Each -time a critical section is entered the count is incremented. Each time a -critical section is exited the count is decremented - with interrupts only -being re-enabled if the count is zero. - -usCriticalNesting will get set to zero when the scheduler starts, but must -not be initialised to zero as this will cause problems during the startup -sequence. */ + * time a critical section is entered the count is incremented. Each time a + * critical section is exited the count is decremented - with interrupts only + * being re-enabled if the count is zero. + * + * usCriticalNesting will get set to zero when the scheduler starts, but must + * not be initialised to zero as this will cause problems during the startup + * sequence. */ volatile uint16_t usCriticalNesting = portINITIAL_CRITICAL_NESTING; /*-----------------------------------------------------------*/ @@ -70,26 +70,28 @@ void vPortSetupTimerInterrupt( void ); * * See the header file portable.h. */ -StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters ) +StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, + TaskFunction_t pxCode, + void * pvParameters ) { -uint16_t *pusTopOfStack; -uint32_t *pulTopOfStack; + uint16_t * pusTopOfStack; + uint32_t * pulTopOfStack; /* - Place a few bytes of known values on the bottom of the stack. - This is just useful for debugging and can be included if required. - - *pxTopOfStack = ( StackType_t ) 0x1111; - pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x2222; - pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x3333; - */ + * Place a few bytes of known values on the bottom of the stack. + * This is just useful for debugging and can be included if required. + * + * pxTopOfStack = ( StackType_t ) 0x1111; + * pxTopOfStack--; + * pxTopOfStack = ( StackType_t ) 0x2222; + * pxTopOfStack--; + * pxTopOfStack = ( StackType_t ) 0x3333; + */ /* StackType_t is either 16 bits or 32 bits depending on the data model. - Some stacked items do not change size depending on the data model so have - to be explicitly cast to the correct size so this function will work - whichever data model is being used. */ + * Some stacked items do not change size depending on the data model so have + * to be explicitly cast to the correct size so this function will work + * whichever data model is being used. */ if( sizeof( StackType_t ) == sizeof( uint16_t ) ) { /* Make room for a 20 bit value stored as a 32 bit value. */ @@ -101,6 +103,7 @@ uint32_t *pulTopOfStack; { pulTopOfStack = ( uint32_t * ) pxTopOfStack; } + *pulTopOfStack = ( uint32_t ) pxCode; pusTopOfStack = ( uint16_t * ) pulTopOfStack; @@ -137,20 +140,20 @@ uint32_t *pulTopOfStack; pxTopOfStack--; *pxTopOfStack = ( StackType_t ) 0x4444; pxTopOfStack--; - #else + #else /* ifdef PRELOAD_REGISTER_VALUES */ pxTopOfStack -= 3; *pxTopOfStack = ( StackType_t ) pvParameters; pxTopOfStack -= 9; - #endif + #endif /* ifdef PRELOAD_REGISTER_VALUES */ /* A variable is used to keep track of the critical section nesting. - This variable has to be stored as part of the task context and is - initially set to zero. */ + * This variable has to be stored as part of the task context and is + * initially set to zero. */ *pxTopOfStack = ( StackType_t ) portNO_CRITICAL_SECTION_NESTING; /* Return a pointer to the top of the stack we have generated so this can - be stored in the task control block for the task. */ + * be stored in the task control block for the task. */ return pxTopOfStack; } /*-----------------------------------------------------------*/ @@ -158,7 +161,7 @@ uint32_t *pulTopOfStack; void vPortEndScheduler( void ) { /* It is unlikely that the MSP430 port will get stopped. If required simply - disable the tick interrupt here. */ + * disable the tick interrupt here. */ } /*-----------------------------------------------------------*/ @@ -174,10 +177,8 @@ void vPortSetupTimerInterrupt( void ) #pragma vector=configTICK_VECTOR __interrupt __raw void vTickISREntry( void ) { -extern void vPortTickISR( void ); + extern void vPortTickISR( void ); __bic_SR_register_on_exit( SCG1 + SCG0 + OSCOFF + CPUOFF ); vPortTickISR(); } - - diff --git a/Source/portable/IAR/MSP430X/portext.s43 b/Source/portable/IAR/MSP430X/portext.s43 index 25560c7df..37697d1bd 100644 --- a/Source/portable/IAR/MSP430X/portext.s43 +++ b/Source/portable/IAR/MSP430X/portext.s43 @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/Source/portable/IAR/MSP430X/portmacro.h b/Source/portable/IAR/MSP430X/portmacro.h index d0fce750e..72a22b651 100644 --- a/Source/portable/IAR/MSP430X/portmacro.h +++ b/Source/portable/IAR/MSP430X/portmacro.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -43,31 +43,31 @@ #include "msp430.h" /* Type definitions. */ -#define portCHAR char -#define portFLOAT float -#define portDOUBLE double -#define portLONG long -#define portSHORT int -#define portBASE_TYPE short +#define portCHAR char +#define portFLOAT float +#define portDOUBLE double +#define portLONG long +#define portSHORT int +#define portBASE_TYPE short /* The stack type changes depending on the data model. */ -#if( __DATA_MODEL__ == __DATA_MODEL_SMALL__ ) - #define portSTACK_TYPE uint16_t - #define portPOINTER_SIZE_TYPE uint16_t +#if ( __DATA_MODEL__ == __DATA_MODEL_SMALL__ ) + #define portSTACK_TYPE uint16_t + #define portPOINTER_SIZE_TYPE uint16_t #else - #define portSTACK_TYPE uint32_t + #define portSTACK_TYPE uint32_t #endif -typedef portSTACK_TYPE StackType_t; -typedef short BaseType_t; -typedef unsigned short UBaseType_t; +typedef portSTACK_TYPE StackType_t; +typedef short BaseType_t; +typedef unsigned short UBaseType_t; -#if( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS ) - typedef uint16_t TickType_t; - #define portMAX_DELAY ( TickType_t ) 0xffff +#if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS ) + typedef uint16_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffff #elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS ) - typedef uint32_t TickType_t; - #define portMAX_DELAY ( TickType_t ) ( 0xFFFFFFFFUL ) + typedef uint32_t TickType_t; + #define portMAX_DELAY ( TickType_t ) ( 0xFFFFFFFFUL ) #else #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width. #endif @@ -80,37 +80,37 @@ typedef unsigned short UBaseType_t; /*-----------------------------------------------------------*/ /* Critical section control macros. */ -#define portNO_CRITICAL_SECTION_NESTING ( ( uint16_t ) 0 ) - -#define portENTER_CRITICAL() \ -{ \ -extern volatile uint16_t usCriticalNesting; \ - \ - portDISABLE_INTERRUPTS(); \ - \ - /* Now interrupts are disabled usCriticalNesting can be accessed */ \ - /* directly. Increment ulCriticalNesting to keep a count of how many */ \ - /* times portENTER_CRITICAL() has been called. */ \ - usCriticalNesting++; \ -} - -#define portEXIT_CRITICAL() \ -{ \ -extern volatile uint16_t usCriticalNesting; \ - \ - if( usCriticalNesting > portNO_CRITICAL_SECTION_NESTING ) \ - { \ - /* Decrement the nesting count as we are leaving a critical section. */ \ - usCriticalNesting--; \ - \ - /* If the nesting level has reached zero then interrupts should be */ \ - /* re-enabled. */ \ - if( usCriticalNesting == portNO_CRITICAL_SECTION_NESTING ) \ - { \ - portENABLE_INTERRUPTS(); \ - } \ - } \ -} +#define portNO_CRITICAL_SECTION_NESTING ( ( uint16_t ) 0 ) + +#define portENTER_CRITICAL() \ + { \ + extern volatile uint16_t usCriticalNesting; \ + \ + portDISABLE_INTERRUPTS(); \ + \ + /* Now interrupts are disabled usCriticalNesting can be accessed */ \ + /* directly. Increment ulCriticalNesting to keep a count of how many */ \ + /* times portENTER_CRITICAL() has been called. */ \ + usCriticalNesting++; \ + } + +#define portEXIT_CRITICAL() \ + { \ + extern volatile uint16_t usCriticalNesting; \ + \ + if( usCriticalNesting > portNO_CRITICAL_SECTION_NESTING ) \ + { \ + /* Decrement the nesting count as we are leaving a critical section. */ \ + usCriticalNesting--; \ + \ + /* If the nesting level has reached zero then interrupts should be */ \ + /* re-enabled. */ \ + if( usCriticalNesting == portNO_CRITICAL_SECTION_NESTING ) \ + { \ + portENABLE_INTERRUPTS(); \ + } \ + } \ + } /*-----------------------------------------------------------*/ /* Task utilities. */ @@ -119,26 +119,26 @@ extern volatile uint16_t usCriticalNesting; * Manual context switch called by portYIELD or taskYIELD. */ extern void vPortYield( void ); -#define portYIELD() vPortYield() +#define portYIELD() vPortYield() /*-----------------------------------------------------------*/ /* Hardware specifics. */ -#define portBYTE_ALIGNMENT 2 -#define portSTACK_GROWTH ( -1 ) -#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) -#define portNOP() __no_operation() +#define portBYTE_ALIGNMENT 2 +#define portSTACK_GROWTH ( -1 ) +#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) +#define portNOP() __no_operation() /*-----------------------------------------------------------*/ /* Task function macros as described on the FreeRTOS.org WEB site. */ -#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters ) -#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters ) +#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters ) +#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters ) -#define portYIELD_FROM_ISR( x ) do { if( x ) vPortYield(); } while( 0 ) +#define portYIELD_FROM_ISR( x ) do { if( x ) vPortYield( ); } while( 0 ) void vApplicationSetupTimerInterrupt( void ); /* sizeof( int ) != sizeof( long ) so a full printf() library is required if -run time stats information is to be displayed. */ + * run time stats information is to be displayed. */ #define portLU_PRINTF_SPECIFIER_REQUIRED #endif /* PORTMACRO_H */ diff --git a/Source/portable/IAR/RISC-V/chip_extensions.cmake b/Source/portable/IAR/RISC-V/chip_extensions.cmake new file mode 100644 index 000000000..110ec4a2e --- /dev/null +++ b/Source/portable/IAR/RISC-V/chip_extensions.cmake @@ -0,0 +1,16 @@ +if( FREERTOS_PORT STREQUAL "IAR_RISC_V_GENERIC" ) + set( VALID_CHIP_EXTENSIONS + "RV32I_CLINT_no_extensions" ) + + if( ( NOT FREERTOS_RISCV_EXTENSION ) OR ( NOT ( ${FREERTOS_RISCV_EXTENSION} IN_LIST VALID_CHIP_EXTENSIONS ) ) ) + message(FATAL_ERROR + "FREERTOS_RISCV_EXTENSION \"${FREERTOS_RISCV_EXTENSION}\" is not set or unsupported.\n" + "Please specify it from top-level CMake file (example):\n" + " set(FREERTOS_RISCV_EXTENSION RISCV_MTIME_CLINT_no_extensions CACHE STRING \"\")\n" + " or from CMake command line option:\n" + " -DFREERTOS_RISCV_EXTENSION=RISCV_MTIME_CLINT_no_extensions\n" + "\n" + " Available extension options:\n" + " ${VALID_CHIP_EXTENSIONS} \n") + endif() +endif() diff --git a/Source/portable/IAR/RISC-V/chip_specific_extensions/RV32I_CLINT_no_extensions/freertos_risc_v_chip_specific_extensions.h b/Source/portable/IAR/RISC-V/chip_specific_extensions/RV32I_CLINT_no_extensions/freertos_risc_v_chip_specific_extensions.h index 33446058f..73da14b9d 100644 --- a/Source/portable/IAR/RISC-V/chip_specific_extensions/RV32I_CLINT_no_extensions/freertos_risc_v_chip_specific_extensions.h +++ b/Source/portable/IAR/RISC-V/chip_specific_extensions/RV32I_CLINT_no_extensions/freertos_risc_v_chip_specific_extensions.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -54,16 +54,16 @@ #ifndef __FREERTOS_RISC_V_EXTENSIONS_H__ #define __FREERTOS_RISC_V_EXTENSIONS_H__ -#define portasmHAS_SIFIVE_CLINT 1 -#define portasmHAS_MTIME 1 -#define portasmADDITIONAL_CONTEXT_SIZE 0 /* Must be even number on 32-bit cores. */ +#define portasmHAS_SIFIVE_CLINT 1 +#define portasmHAS_MTIME 1 +#define portasmADDITIONAL_CONTEXT_SIZE 0 /* Must be even number on 32-bit cores. */ portasmSAVE_ADDITIONAL_REGISTERS MACRO - /* No additional registers to save, so this macro does nothing. */ - ENDM +/* No additional registers to save, so this macro does nothing. */ +ENDM portasmRESTORE_ADDITIONAL_REGISTERS MACRO - /* No additional registers to restore, so this macro does nothing. */ +/* No additional registers to restore, so this macro does nothing. */ ENDM #endif /* __FREERTOS_RISC_V_EXTENSIONS_H__ */ diff --git a/Source/portable/IAR/RISC-V/port.c b/Source/portable/IAR/RISC-V/port.c index 79c32213e..4d4430866 100644 --- a/Source/portable/IAR/RISC-V/port.c +++ b/Source/portable/IAR/RISC-V/port.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -39,15 +39,15 @@ #include "string.h" #ifdef configCLINT_BASE_ADDRESS - #warning The configCLINT_BASE_ADDRESS constant has been deprecated. configMTIME_BASE_ADDRESS and configMTIMECMP_BASE_ADDRESS are currently being derived from the (possibly 0) configCLINT_BASE_ADDRESS setting. Please update to define configMTIME_BASE_ADDRESS and configMTIMECMP_BASE_ADDRESS dirctly in place of configCLINT_BASE_ADDRESS. See https: /*www.FreeRTOS.org/Using-FreeRTOS-on-RISC-V.html */ + #warning "The configCLINT_BASE_ADDRESS constant has been deprecated. configMTIME_BASE_ADDRESS and configMTIMECMP_BASE_ADDRESS are currently being derived from the (possibly 0) configCLINT_BASE_ADDRESS setting. Please update to define configMTIME_BASE_ADDRESS and configMTIMECMP_BASE_ADDRESS directly in place of configCLINT_BASE_ADDRESS. See www.FreeRTOS.org/Using-FreeRTOS-on-RISC-V.html" #endif #ifndef configMTIME_BASE_ADDRESS - #warning configMTIME_BASE_ADDRESS must be defined in FreeRTOSConfig.h. If the target chip includes a memory-mapped mtime register then set configMTIME_BASE_ADDRESS to the mapped address. Otherwise set configMTIME_BASE_ADDRESS to 0. See https: /*www.FreeRTOS.org/Using-FreeRTOS-on-RISC-V.html */ + #warning "configMTIME_BASE_ADDRESS must be defined in FreeRTOSConfig.h. If the target chip includes a memory-mapped mtime register then set configMTIME_BASE_ADDRESS to the mapped address. Otherwise set configMTIME_BASE_ADDRESS to 0. See www.FreeRTOS.org/Using-FreeRTOS-on-RISC-V.html" #endif #ifndef configMTIMECMP_BASE_ADDRESS - #warning configMTIMECMP_BASE_ADDRESS must be defined in FreeRTOSConfig.h. If the target chip includes a memory-mapped mtimecmp register then set configMTIMECMP_BASE_ADDRESS to the mapped address. Otherwise set configMTIMECMP_BASE_ADDRESS to 0. See https: /*www.FreeRTOS.org/Using-FreeRTOS-on-RISC-V.html */ + #warning "configMTIMECMP_BASE_ADDRESS must be defined in FreeRTOSConfig.h. If the target chip includes a memory-mapped mtimecmp register then set configMTIMECMP_BASE_ADDRESS to the mapped address. Otherwise set configMTIMECMP_BASE_ADDRESS to 0. See www.FreeRTOS.org/Using-FreeRTOS-on-RISC-V.html" #endif /* Let the user override the pre-loading of the initial LR with the address of @@ -70,7 +70,7 @@ static __attribute__( ( aligned( 16 ) ) ) StackType_t xISRStack[ configISR_STACK_SIZE_WORDS ] = { 0 }; const StackType_t xISRStackTop = ( StackType_t ) &( xISRStack[ configISR_STACK_SIZE_WORDS & ~portBYTE_ALIGNMENT_MASK ] ); -/* Don't use 0xa5 as the stack fill bytes as that is used by the kernerl for +/* Don't use 0xa5 as the stack fill bytes as that is used by the kernel for * the task stacks, and so will legitimately appear in many positions within * the ISR stack. */ #define portISR_STACK_FILL_BYTE 0xee @@ -114,7 +114,7 @@ size_t xTaskReturnAddress = ( size_t ) portTASK_RETURN_ADDRESS; * the stack overflow hook function (because the stack overflow hook is specific * to a task stack, not the ISR stack). */ #if defined( configISR_STACK_SIZE_WORDS ) && ( configCHECK_FOR_STACK_OVERFLOW > 2 ) - #warning This path not tested, or even compiled yet. + #warning "This path not tested, or even compiled yet." static const uint8_t ucExpectedStackBytes[] = { @@ -126,7 +126,7 @@ size_t xTaskReturnAddress = ( size_t ) portTASK_RETURN_ADDRESS; }; \ #define portCHECK_ISR_STACK() configASSERT( ( memcmp( ( void * ) xISRStack, ( void * ) ucExpectedStackBytes, sizeof( ucExpectedStackBytes ) ) == 0 ) ) -#else /* if defined( configISR_STACK_SIZE_WORDS ) && ( configCHECK_FOR_STACK_OVERFLOW > 2 ) */ +#else /* if defined( configISR_STACK_SIZE_WORDS ) && ( configCHECK_FOR_STACK_OVERFLOW > 2 ) */ /* Define the function away. */ #define portCHECK_ISR_STACK() #endif /* configCHECK_FOR_STACK_OVERFLOW > 2 */ @@ -167,7 +167,7 @@ static void prvTaskExitError( void ) volatile uint32_t * const pulTimeLow = ( uint32_t * ) ( configMTIME_BASE_ADDRESS ); volatile uint32_t ulHartId; - __asm volatile ( "csrr %0, 0xf14" : "=r" ( ulHartId ) ); /* 0xf14 is hartid. */ + __asm volatile ( "csrr %0, 0xf14" : "=r" ( ulHartId ) ); /* 0xf14 is HART ID. */ pullMachineTimerCompareRegister = ( volatile uint64_t * ) ( ullMachineTimerCompareRegisterBase + ( ulHartId * sizeof( uint64_t ) ) ); diff --git a/Source/portable/IAR/RISC-V/portASM.s b/Source/portable/IAR/RISC-V/portASM.s index 1ca9e2d4c..e919a50d7 100644 --- a/Source/portable/IAR/RISC-V/portASM.s +++ b/Source/portable/IAR/RISC-V/portASM.s @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/Source/portable/IAR/RISC-V/portContext.h b/Source/portable/IAR/RISC-V/portContext.h index da6af471b..01698a8cb 100644 --- a/Source/portable/IAR/RISC-V/portContext.h +++ b/Source/portable/IAR/RISC-V/portContext.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -30,13 +30,13 @@ #define PORTCONTEXT_H #if __riscv_xlen == 64 - #define portWORD_SIZE 8 - #define store_x sd - #define load_x ld + #define portWORD_SIZE 8 + #define store_x sd + #define load_x ld #elif __riscv_xlen == 32 - #define store_x sw - #define load_x lw - #define portWORD_SIZE 4 + #define store_x sw + #define load_x lw + #define portWORD_SIZE 4 #else #error Assembler did not define __riscv_xlen #endif @@ -49,36 +49,36 @@ * specific version of freertos_risc_v_chip_specific_extensions.h. See the * notes at the top of portASM.S file. */ #ifdef __riscv_32e - #define portCONTEXT_SIZE ( 15 * portWORD_SIZE ) - #define portCRITICAL_NESTING_OFFSET 13 - #define portMSTATUS_OFFSET 14 + #define portCONTEXT_SIZE ( 15 * portWORD_SIZE ) + #define portCRITICAL_NESTING_OFFSET 13 + #define portMSTATUS_OFFSET 14 #else - #define portCONTEXT_SIZE ( 31 * portWORD_SIZE ) - #define portCRITICAL_NESTING_OFFSET 29 - #define portMSTATUS_OFFSET 30 + #define portCONTEXT_SIZE ( 31 * portWORD_SIZE ) + #define portCRITICAL_NESTING_OFFSET 29 + #define portMSTATUS_OFFSET 30 #endif - EXTERN pxCurrentTCB - EXTERN xISRStackTop - EXTERN xCriticalNesting - EXTERN pxCriticalNesting +EXTERN pxCurrentTCB +EXTERN xISRStackTop +EXTERN xCriticalNesting +EXTERN pxCriticalNesting /*-----------------------------------------------------------*/ portcontextSAVE_CONTEXT_INTERNAL MACRO - addi sp, sp, -portCONTEXT_SIZE - store_x x1, 1 * portWORD_SIZE( sp ) - store_x x5, 2 * portWORD_SIZE( sp ) - store_x x6, 3 * portWORD_SIZE( sp ) - store_x x7, 4 * portWORD_SIZE( sp ) - store_x x8, 5 * portWORD_SIZE( sp ) - store_x x9, 6 * portWORD_SIZE( sp ) - store_x x10, 7 * portWORD_SIZE( sp ) - store_x x11, 8 * portWORD_SIZE( sp ) - store_x x12, 9 * portWORD_SIZE( sp ) - store_x x13, 10 * portWORD_SIZE( sp ) - store_x x14, 11 * portWORD_SIZE( sp ) - store_x x15, 12 * portWORD_SIZE( sp ) +addi sp, sp, -portCONTEXT_SIZE +store_x x1, 1 * portWORD_SIZE( sp ) +store_x x5, 2 * portWORD_SIZE( sp ) +store_x x6, 3 * portWORD_SIZE( sp ) +store_x x7, 4 * portWORD_SIZE( sp ) +store_x x8, 5 * portWORD_SIZE( sp ) +store_x x9, 6 * portWORD_SIZE( sp ) +store_x x10, 7 * portWORD_SIZE( sp ) +store_x x11, 8 * portWORD_SIZE( sp ) +store_x x12, 9 * portWORD_SIZE( sp ) +store_x x13, 10 * portWORD_SIZE( sp ) +store_x x14, 11 * portWORD_SIZE( sp ) +store_x x15, 12 * portWORD_SIZE( sp ) #ifndef __riscv_32e store_x x16, 13 * portWORD_SIZE( sp ) store_x x17, 14 * portWORD_SIZE( sp ) @@ -96,94 +96,94 @@ portcontextSAVE_CONTEXT_INTERNAL MACRO store_x x29, 26 * portWORD_SIZE( sp ) store_x x30, 27 * portWORD_SIZE( sp ) store_x x31, 28 * portWORD_SIZE( sp ) -#endif +#endif /* ifndef __riscv_32e */ - load_x t0, xCriticalNesting /* Load the value of xCriticalNesting into t0. */ - store_x t0, portCRITICAL_NESTING_OFFSET * portWORD_SIZE( sp ) /* Store the critical nesting value to the stack. */ +load_x t0, xCriticalNesting /* Load the value of xCriticalNesting into t0. */ +store_x t0, portCRITICAL_NESTING_OFFSET * portWORD_SIZE( sp ) /* Store the critical nesting value to the stack. */ - csrr t0, mstatus /* Required for MPIE bit. */ - store_x t0, portMSTATUS_OFFSET * portWORD_SIZE( sp ) +csrr t0, mstatus /* Required for MPIE bit. */ +store_x t0, portMSTATUS_OFFSET * portWORD_SIZE( sp ) - portasmSAVE_ADDITIONAL_REGISTERS /* Defined in freertos_risc_v_chip_specific_extensions.h to save any registers unique to the RISC-V implementation. */ +portasmSAVE_ADDITIONAL_REGISTERS /* Defined in freertos_risc_v_chip_specific_extensions.h to save any registers unique to the RISC-V implementation. */ - load_x t0, pxCurrentTCB /* Load pxCurrentTCB. */ - store_x sp, 0( t0 ) /* Write sp to first TCB member. */ +load_x t0, pxCurrentTCB /* Load pxCurrentTCB. */ +store_x sp, 0 ( t0 ) /* Write sp to first TCB member. */ - ENDM +ENDM /*-----------------------------------------------------------*/ portcontextSAVE_EXCEPTION_CONTEXT MACRO - portcontextSAVE_CONTEXT_INTERNAL - csrr a0, mcause - csrr a1, mepc - addi a1, a1, 4 /* Synchronous so update exception return address to the instruction after the instruction that generated the exception. */ - store_x a1, 0( sp ) /* Save updated exception return address. */ - load_x sp, xISRStackTop /* Switch to ISR stack. */ - ENDM +portcontextSAVE_CONTEXT_INTERNAL +csrr a0, mcause +csrr a1, mepc +addi a1, a1, 4 /* Synchronous so update exception return address to the instruction after the instruction that generated the exception. */ +store_x a1, 0 ( sp ) /* Save updated exception return address. */ +load_x sp, xISRStackTop /* Switch to ISR stack. */ +ENDM /*-----------------------------------------------------------*/ portcontextSAVE_INTERRUPT_CONTEXT MACRO - portcontextSAVE_CONTEXT_INTERNAL - csrr a0, mcause - csrr a1, mepc - store_x a1, 0( sp ) /* Asynchronous interrupt so save unmodified exception return address. */ - load_x sp, xISRStackTop /* Switch to ISR stack. */ - ENDM +portcontextSAVE_CONTEXT_INTERNAL +csrr a0, mcause +csrr a1, mepc +store_x a1, 0 ( sp ) /* Asynchronous interrupt so save unmodified exception return address. */ +load_x sp, xISRStackTop /* Switch to ISR stack. */ +ENDM /*-----------------------------------------------------------*/ portcontextRESTORE_CONTEXT MACRO - load_x t1, pxCurrentTCB /* Load pxCurrentTCB. */ - load_x sp, 0( t1 ) /* Read sp from first TCB member. */ - - /* Load mepc with the address of the instruction in the task to run next. */ - load_x t0, 0( sp ) - csrw mepc, t0 - - /* Defined in freertos_risc_v_chip_specific_extensions.h to restore any registers unique to the RISC-V implementation. */ - portasmRESTORE_ADDITIONAL_REGISTERS - - /* Load mstatus with the interrupt enable bits used by the task. */ - load_x t0, portMSTATUS_OFFSET * portWORD_SIZE( sp ) - csrw mstatus, t0 /* Required for MPIE bit. */ - - load_x t0, portCRITICAL_NESTING_OFFSET * portWORD_SIZE( sp ) /* Obtain xCriticalNesting value for this task from task's stack. */ - load_x t1, pxCriticalNesting /* Load the address of xCriticalNesting into t1. */ - store_x t0, 0( t1 ) /* Restore the critical nesting value for this task. */ - - load_x x1, 1 * portWORD_SIZE( sp ) - load_x x5, 2 * portWORD_SIZE( sp ) - load_x x6, 3 * portWORD_SIZE( sp ) - load_x x7, 4 * portWORD_SIZE( sp ) - load_x x8, 5 * portWORD_SIZE( sp ) - load_x x9, 6 * portWORD_SIZE( sp ) - load_x x10, 7 * portWORD_SIZE( sp ) - load_x x11, 8 * portWORD_SIZE( sp ) - load_x x12, 9 * portWORD_SIZE( sp ) - load_x x13, 10 * portWORD_SIZE( sp ) - load_x x14, 11 * portWORD_SIZE( sp ) - load_x x15, 12 * portWORD_SIZE( sp ) +load_x t1, pxCurrentTCB /* Load pxCurrentTCB. */ +load_x sp, 0 ( t1 ) /* Read sp from first TCB member. */ + +/* Load mepc with the address of the instruction in the task to run next. */ +load_x t0, 0 ( sp ) +csrw mepc, t0 + +/* Defined in freertos_risc_v_chip_specific_extensions.h to restore any registers unique to the RISC-V implementation. */ +portasmRESTORE_ADDITIONAL_REGISTERS + +/* Load mstatus with the interrupt enable bits used by the task. */ +load_x t0, portMSTATUS_OFFSET * portWORD_SIZE( sp ) +csrw mstatus, t0 /* Required for MPIE bit. */ + +load_x t0, portCRITICAL_NESTING_OFFSET * portWORD_SIZE( sp ) /* Obtain xCriticalNesting value for this task from task's stack. */ +load_x t1, pxCriticalNesting /* Load the address of xCriticalNesting into t1. */ +store_x t0, 0 ( t1 ) /* Restore the critical nesting value for this task. */ + +load_x x1, 1 * portWORD_SIZE( sp ) +load_x x5, 2 * portWORD_SIZE( sp ) +load_x x6, 3 * portWORD_SIZE( sp ) +load_x x7, 4 * portWORD_SIZE( sp ) +load_x x8, 5 * portWORD_SIZE( sp ) +load_x x9, 6 * portWORD_SIZE( sp ) +load_x x10, 7 * portWORD_SIZE( sp ) +load_x x11, 8 * portWORD_SIZE( sp ) +load_x x12, 9 * portWORD_SIZE( sp ) +load_x x13, 10 * portWORD_SIZE( sp ) +load_x x14, 11 * portWORD_SIZE( sp ) +load_x x15, 12 * portWORD_SIZE( sp ) #ifndef __riscv_32e - load_x x16, 13 * portWORD_SIZE( sp ) - load_x x17, 14 * portWORD_SIZE( sp ) - load_x x18, 15 * portWORD_SIZE( sp ) - load_x x19, 16 * portWORD_SIZE( sp ) - load_x x20, 17 * portWORD_SIZE( sp ) - load_x x21, 18 * portWORD_SIZE( sp ) - load_x x22, 19 * portWORD_SIZE( sp ) - load_x x23, 20 * portWORD_SIZE( sp ) - load_x x24, 21 * portWORD_SIZE( sp ) - load_x x25, 22 * portWORD_SIZE( sp ) - load_x x26, 23 * portWORD_SIZE( sp ) - load_x x27, 24 * portWORD_SIZE( sp ) - load_x x28, 25 * portWORD_SIZE( sp ) - load_x x29, 26 * portWORD_SIZE( sp ) - load_x x30, 27 * portWORD_SIZE( sp ) - load_x x31, 28 * portWORD_SIZE( sp ) -#endif - addi sp, sp, portCONTEXT_SIZE - - mret - ENDM + load_x x16, 13 * portWORD_SIZE( sp ) + load_x x17, 14 * portWORD_SIZE( sp ) + load_x x18, 15 * portWORD_SIZE( sp ) + load_x x19, 16 * portWORD_SIZE( sp ) + load_x x20, 17 * portWORD_SIZE( sp ) + load_x x21, 18 * portWORD_SIZE( sp ) + load_x x22, 19 * portWORD_SIZE( sp ) + load_x x23, 20 * portWORD_SIZE( sp ) + load_x x24, 21 * portWORD_SIZE( sp ) + load_x x25, 22 * portWORD_SIZE( sp ) + load_x x26, 23 * portWORD_SIZE( sp ) + load_x x27, 24 * portWORD_SIZE( sp ) + load_x x28, 25 * portWORD_SIZE( sp ) + load_x x29, 26 * portWORD_SIZE( sp ) + load_x x30, 27 * portWORD_SIZE( sp ) + load_x x31, 28 * portWORD_SIZE( sp ) +#endif /* ifndef __riscv_32e */ +addi sp, sp, portCONTEXT_SIZE + +mret +ENDM /*-----------------------------------------------------------*/ #endif /* PORTCONTEXT_H */ diff --git a/Source/portable/IAR/RISC-V/portmacro.h b/Source/portable/IAR/RISC-V/portmacro.h index 1e0cbc2ee..b9f91e619 100644 --- a/Source/portable/IAR/RISC-V/portmacro.h +++ b/Source/portable/IAR/RISC-V/portmacro.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -50,85 +50,97 @@ /* Type definitions. */ #if __riscv_xlen == 64 - #define portSTACK_TYPE uint64_t - #define portBASE_TYPE int64_t - #define portUBASE_TYPE uint64_t - #define portMAX_DELAY ( TickType_t ) 0xffffffffffffffffUL - #define portPOINTER_SIZE_TYPE uint64_t + #define portSTACK_TYPE uint64_t + #define portBASE_TYPE int64_t + #define portUBASE_TYPE uint64_t + #define portMAX_DELAY ( TickType_t ) 0xffffffffffffffffUL + #define portPOINTER_SIZE_TYPE uint64_t #elif __riscv_xlen == 32 - #define portSTACK_TYPE uint32_t - #define portBASE_TYPE int32_t - #define portUBASE_TYPE uint32_t - #define portMAX_DELAY ( TickType_t ) 0xffffffffUL -#else - #error Assembler did not define __riscv_xlen -#endif - -typedef portSTACK_TYPE StackType_t; -typedef portBASE_TYPE BaseType_t; -typedef portUBASE_TYPE UBaseType_t; -typedef portUBASE_TYPE TickType_t; + #define portSTACK_TYPE uint32_t + #define portBASE_TYPE int32_t + #define portUBASE_TYPE uint32_t + #define portMAX_DELAY ( TickType_t ) 0xffffffffUL +#else /* if __riscv_xlen == 64 */ + #error "Assembler did not define __riscv_xlen" +#endif /* if __riscv_xlen == 64 */ + +typedef portSTACK_TYPE StackType_t; +typedef portBASE_TYPE BaseType_t; +typedef portUBASE_TYPE UBaseType_t; +typedef portUBASE_TYPE TickType_t; /* Legacy type definitions. */ -#define portCHAR char -#define portFLOAT float -#define portDOUBLE double -#define portLONG long -#define portSHORT short +#define portCHAR char +#define portFLOAT float +#define portDOUBLE double +#define portLONG long +#define portSHORT short /* 32-bit tick type on a 32-bit architecture, so reads of the tick count do * not need to be guarded with a critical section. */ -#define portTICK_TYPE_IS_ATOMIC 1 +#define portTICK_TYPE_IS_ATOMIC 1 /*-----------------------------------------------------------*/ /* Architecture specifics. */ -#define portSTACK_GROWTH ( -1 ) -#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) +#define portSTACK_GROWTH ( -1 ) +#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) #ifdef __riscv_32e - #define portBYTE_ALIGNMENT 8 /* RV32E uses RISC-V EABI with reduced stack alignment requirements. */ + #define portBYTE_ALIGNMENT 8 /* RV32E uses RISC-V EABI with reduced stack alignment requirements. */ #else - #define portBYTE_ALIGNMENT 16 + #define portBYTE_ALIGNMENT 16 #endif /*-----------------------------------------------------------*/ /* Scheduler utilities. */ extern void vTaskSwitchContext( void ); -#define portYIELD() __asm volatile( "ecall" ); -#define portEND_SWITCHING_ISR( xSwitchRequired ) do { if( xSwitchRequired ) vTaskSwitchContext(); } while( 0 ) -#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x ) +#define portYIELD() __asm volatile ( "ecall" ); +#define portEND_SWITCHING_ISR( xSwitchRequired ) \ + do \ + { \ + if( xSwitchRequired != pdFALSE ) \ + { \ + traceISR_EXIT_TO_SCHEDULER(); \ + vTaskSwitchContext(); \ + } \ + else \ + { \ + traceISR_EXIT(); \ + } \ + } while( 0 ) +#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x ) /*-----------------------------------------------------------*/ /* Critical section management. */ -#define portCRITICAL_NESTING_IN_TCB 0 +#define portCRITICAL_NESTING_IN_TCB 0 -#define portSET_INTERRUPT_MASK_FROM_ISR() 0 -#define portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedStatusValue ) ( void ) uxSavedStatusValue +#define portSET_INTERRUPT_MASK_FROM_ISR() 0 +#define portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedStatusValue ) ( void ) uxSavedStatusValue -#define portDISABLE_INTERRUPTS() __disable_interrupt() -#define portENABLE_INTERRUPTS() __enable_interrupt() +#define portDISABLE_INTERRUPTS() __disable_interrupt() +#define portENABLE_INTERRUPTS() __enable_interrupt() extern size_t xCriticalNesting; -#define portENTER_CRITICAL() \ -{ \ - portDISABLE_INTERRUPTS(); \ - xCriticalNesting++; \ -} - -#define portEXIT_CRITICAL() \ -{ \ - xCriticalNesting--; \ - if( xCriticalNesting == 0 ) \ - { \ - portENABLE_INTERRUPTS(); \ - } \ -} +#define portENTER_CRITICAL() \ + { \ + portDISABLE_INTERRUPTS(); \ + xCriticalNesting++; \ + } + +#define portEXIT_CRITICAL() \ + { \ + xCriticalNesting--; \ + if( xCriticalNesting == 0 ) \ + { \ + portENABLE_INTERRUPTS(); \ + } \ + } /*-----------------------------------------------------------*/ /* Architecture specific optimisations. */ -#if( configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 ) +#if ( configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 ) - #error configUSE_PORT_OPTIMISED_TASK_SELECTION cannot yet be used in the IAR RISC-V port, the CLZ instruction needs to be emulated. + #error "configUSE_PORT_OPTIMISED_TASK_SELECTION cannot yet be used in the IAR RISC-V port, the CLZ instruction needs to be emulated." #endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */ @@ -138,19 +150,19 @@ extern size_t xCriticalNesting; /* Task function macros as described on the FreeRTOS.org WEB site. These are * not necessary for to use this port. They are defined so the common demo * files (which build with all the ports) will build. */ -#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters ) -#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters ) +#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters ) +#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters ) /*-----------------------------------------------------------*/ -#define portNOP() __asm volatile( " nop " ) -#define portINLINE __inline +#define portNOP() __asm volatile ( " nop " ) +#define portINLINE __inline #ifndef portFORCE_INLINE - #define portFORCE_INLINE inline __attribute__(( always_inline)) + #define portFORCE_INLINE inline __attribute__( ( always_inline ) ) #endif -#define portMEMORY_BARRIER() __asm volatile( "" ::: "memory" ) +#define portMEMORY_BARRIER() __asm volatile ( "" ::: "memory" ) /*-----------------------------------------------------------*/ /* Suppress warnings that are generated by the IAR tools, but cannot be fixed in @@ -163,20 +175,22 @@ extern size_t xCriticalNesting; * backward compatibility derive the newer definitions from the old if the old * definition is found. */ #if defined( configCLINT_BASE_ADDRESS ) && !defined( configMTIME_BASE_ADDRESS ) && ( configCLINT_BASE_ADDRESS == 0 ) - /* Legacy case where configCLINT_BASE_ADDRESS was defined as 0 to indicate - * there was no CLINT. Equivalent now is to set the MTIME and MTIMECMP - * addresses to 0. */ - #define configMTIME_BASE_ADDRESS ( 0 ) - #define configMTIMECMP_BASE_ADDRESS ( 0 ) + +/* Legacy case where configCLINT_BASE_ADDRESS was defined as 0 to indicate + * there was no CLINT. Equivalent now is to set the MTIME and MTIMECMP + * addresses to 0. */ + #define configMTIME_BASE_ADDRESS ( 0 ) + #define configMTIMECMP_BASE_ADDRESS ( 0 ) #elif defined( configCLINT_BASE_ADDRESS ) && !defined( configMTIME_BASE_ADDRESS ) - /* Legacy case where configCLINT_BASE_ADDRESS was set to the base address of - * the CLINT. Equivalent now is to derive the MTIME and MTIMECMP addresses - * from the CLINT address. */ - #define configMTIME_BASE_ADDRESS ( ( configCLINT_BASE_ADDRESS ) + 0xBFF8UL ) - #define configMTIMECMP_BASE_ADDRESS ( ( configCLINT_BASE_ADDRESS ) + 0x4000UL ) + +/* Legacy case where configCLINT_BASE_ADDRESS was set to the base address of + * the CLINT. Equivalent now is to derive the MTIME and MTIMECMP addresses + * from the CLINT address. */ + #define configMTIME_BASE_ADDRESS ( ( configCLINT_BASE_ADDRESS ) + 0xBFF8UL ) + #define configMTIMECMP_BASE_ADDRESS ( ( configCLINT_BASE_ADDRESS ) + 0x4000UL ) #elif !defined( configMTIME_BASE_ADDRESS ) || !defined( configMTIMECMP_BASE_ADDRESS ) - #error configMTIME_BASE_ADDRESS and configMTIMECMP_BASE_ADDRESS must be defined in FreeRTOSConfig.h. Set them to zero if there is no MTIME (machine time) clock. See https://www.FreeRTOS.org/Using-FreeRTOS-on-RISC-V.html -#endif + #error "configMTIME_BASE_ADDRESS and configMTIMECMP_BASE_ADDRESS must be defined in FreeRTOSConfig.h. Set them to zero if there is no MTIME (machine time) clock. See www.FreeRTOS.org/Using-FreeRTOS-on-RISC-V.html" +#endif /* if defined( configCLINT_BASE_ADDRESS ) && !defined( configMTIME_BASE_ADDRESS ) && ( configCLINT_BASE_ADDRESS == 0 ) */ /* *INDENT-OFF* */ #ifdef __cplusplus diff --git a/Source/portable/IAR/RL78/port.c b/Source/portable/IAR/RL78/port.c index 8f221bd69..219a739f9 100644 --- a/Source/portable/IAR/RL78/port.c +++ b/Source/portable/IAR/RL78/port.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -31,8 +31,8 @@ #include "task.h" /* The critical nesting value is initialised to a non zero value to ensure -interrupts don't accidentally become enabled before the scheduler is started. */ -#define portINITIAL_CRITICAL_NESTING ( ( uint16_t ) 10 ) + * interrupts don't accidentally become enabled before the scheduler is started. */ +#define portINITIAL_CRITICAL_NESTING ( ( uint16_t ) 10 ) /* Initial PSW value allocated to a newly created task. * 1100011000000000 @@ -45,21 +45,21 @@ interrupts don't accidentally become enabled before the scheduler is started. */ * |--------------------- Zero Flag set * ---------------------- Global Interrupt Flag set (enabled) */ -#define portPSW ( 0xc6UL ) +#define portPSW ( 0xc6UL ) /* The address of the pxCurrentTCB variable, but don't know or need to know its -type. */ + * type. */ typedef void TCB_t; extern volatile TCB_t * volatile pxCurrentTCB; /* Each task maintains a count of the critical section nesting depth. Each time -a critical section is entered the count is incremented. Each time a critical -section is exited the count is decremented - with interrupts only being -re-enabled if the count is zero. - -usCriticalNesting will get set to zero when the scheduler starts, but must -not be initialised to zero as that could cause problems during the startup -sequence. */ + * a critical section is entered the count is incremented. Each time a critical + * section is exited the count is decremented - with interrupts only being + * re-enabled if the count is zero. + * + * usCriticalNesting will get set to zero when the scheduler starts, but must + * not be initialised to zero as that could cause problems during the startup + * sequence. */ volatile uint16_t usCriticalNesting = portINITIAL_CRITICAL_NESTING; /*-----------------------------------------------------------*/ @@ -88,35 +88,37 @@ static void prvTaskExitError( void ); * * See the header file portable.h. */ -StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters ) +StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, + TaskFunction_t pxCode, + void * pvParameters ) { -uint32_t *pulLocal; + uint32_t * pulLocal; /* With large code and large data sizeof( StackType_t ) == 2, and - sizeof( StackType_t * ) == 4. With small code and small data - sizeof( StackType_t ) == 2 and sizeof( StackType_t * ) == 2. */ + * sizeof( StackType_t * ) == 4. With small code and small data + * sizeof( StackType_t ) == 2 and sizeof( StackType_t * ) == 2. */ #if __DATA_MODEL__ == __DATA_MODEL_FAR__ { /* Far pointer parameters are passed using the A:DE registers (24-bit). - Although they are stored in memory as a 32-bit value. Hence decrement - the stack pointer, so 2 bytes are left for the contents of A, before - storing the pvParameters value. */ + * Although they are stored in memory as a 32-bit value. Hence decrement + * the stack pointer, so 2 bytes are left for the contents of A, before + * storing the pvParameters value. */ pxTopOfStack--; - pulLocal = ( uint32_t * ) pxTopOfStack; + pulLocal = ( uint32_t * ) pxTopOfStack; *pulLocal = ( uint32_t ) pvParameters; pxTopOfStack--; /* The return address is a 32-bit value. So decrement the stack pointer - in order to make extra room needed to store the correct value. See the - comments above the prvTaskExitError() prototype at the top of this file. */ + * in order to make extra room needed to store the correct value. See the + * comments above the prvTaskExitError() prototype at the top of this file. */ pxTopOfStack--; pulLocal = ( uint32_t * ) pxTopOfStack; *pulLocal = ( uint32_t ) prvTaskExitError; pxTopOfStack--; /* The task function start address combined with the PSW is also stored - as a 32-bit value. So leave a space for the second two bytes. */ + * as a 32-bit value. So leave a space for the second two bytes. */ pxTopOfStack--; pulLocal = ( uint32_t * ) pxTopOfStack; *pulLocal = ( ( ( uint32_t ) pxCode ) | ( portPSW << 24UL ) ); @@ -126,18 +128,18 @@ uint32_t *pulLocal; *pxTopOfStack = ( StackType_t ) 0x1111; pxTopOfStack--; } - #else + #else /* if __DATA_MODEL__ == __DATA_MODEL_FAR__ */ { /* The return address, leaving space for the first two bytes of the - 32-bit value. See the comments above the prvTaskExitError() prototype - at the top of this file. */ + * 32-bit value. See the comments above the prvTaskExitError() prototype + * at the top of this file. */ pxTopOfStack--; pulLocal = ( uint32_t * ) pxTopOfStack; *pulLocal = ( uint32_t ) prvTaskExitError; pxTopOfStack--; /* Task function. Again as it is written as a 32-bit value a space is - left on the stack for the second two bytes. */ + * left on the stack for the second two bytes. */ pxTopOfStack--; /* Task function start address combined with the PSW. */ @@ -149,7 +151,7 @@ uint32_t *pulLocal; *pxTopOfStack = ( StackType_t ) pvParameters; pxTopOfStack--; } - #endif + #endif /* if __DATA_MODEL__ == __DATA_MODEL_FAR__ */ /* An initial value for the HL register. */ *pxTopOfStack = ( StackType_t ) 0x2222; @@ -166,11 +168,11 @@ uint32_t *pulLocal; pxTopOfStack--; /* Finally the critical section nesting count is set to zero when the task - first starts. */ + * first starts. */ *pxTopOfStack = ( StackType_t ) portNO_CRITICAL_SECTION_NESTING; /* Return a pointer to the top of the stack that has been generated so - it can be stored in the task control block for the task. */ + * it can be stored in the task control block for the task. */ return pxTopOfStack; } /*-----------------------------------------------------------*/ @@ -178,21 +180,24 @@ uint32_t *pulLocal; static void prvTaskExitError( void ) { /* A function that implements a task must not exit or attempt to return to - its caller as there is nothing to return to. If a task wants to exit it - should instead call vTaskDelete( NULL ). - - Artificially force an assert() to be triggered if configASSERT() is - defined, then stop here so application writers can catch the error. */ + * its caller as there is nothing to return to. If a task wants to exit it + * should instead call vTaskDelete( NULL ). + * + * Artificially force an assert() to be triggered if configASSERT() is + * defined, then stop here so application writers can catch the error. */ configASSERT( usCriticalNesting == ~0U ); portDISABLE_INTERRUPTS(); - for( ;; ); + + for( ; ; ) + { + } } /*-----------------------------------------------------------*/ BaseType_t xPortStartScheduler( void ) { /* Setup the hardware to generate the tick. Interrupts are disabled when - this function is called. */ + * this function is called. */ vApplicationSetupTimerInterrupt(); /* Restore the context of the first task that is going to run. */ diff --git a/Source/portable/IAR/RL78/portasm.s b/Source/portable/IAR/RL78/portasm.s index 184c78cda..16ab4b327 100644 --- a/Source/portable/IAR/RL78/portasm.s +++ b/Source/portable/IAR/RL78/portasm.s @@ -1,5 +1,5 @@ ;/* -; * FreeRTOS Kernel V10.6.2 +; * FreeRTOS Kernel V11.0.1 ; * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. ; * ; * SPDX-License-Identifier: MIT diff --git a/Source/portable/IAR/RL78/portmacro.h b/Source/portable/IAR/RL78/portmacro.h index a9da5a118..4b0d036e8 100644 --- a/Source/portable/IAR/RL78/portmacro.h +++ b/Source/portable/IAR/RL78/portmacro.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -47,101 +47,101 @@ *----------------------------------------------------------- */ -#if __DATA_MODEL__ == __DATA_MODEL_FAR__ && __CODE_MODEL__ == __CODE_MODEL_NEAR__ - #warning This port has not been tested with your selected memory model combination. If a far data model is required it is recommended to also use a far code model. -#endif + #if __DATA_MODEL__ == __DATA_MODEL_FAR__ && __CODE_MODEL__ == __CODE_MODEL_NEAR__ + #warning This port has not been tested with your selected memory model combination. If a far data model is required it is recommended to also use a far code model. + #endif -#if __DATA_MODEL__ == __DATA_MODEL_NEAR__ && __CODE_MODEL__ == __CODE_MODEL_FAR__ - #warning This port has not been tested with your selected memory model combination. If a far code model is required it is recommended to also use a far data model. -#endif + #if __DATA_MODEL__ == __DATA_MODEL_NEAR__ && __CODE_MODEL__ == __CODE_MODEL_FAR__ + #warning This port has not been tested with your selected memory model combination. If a far code model is required it is recommended to also use a far data model. + #endif /* Type definitions. */ -#define portCHAR char -#define portFLOAT float -#define portDOUBLE double -#define portLONG long -#define portSHORT short -#define portSTACK_TYPE uint16_t -#define portBASE_TYPE short - -typedef portSTACK_TYPE StackType_t; -typedef short BaseType_t; -typedef unsigned short UBaseType_t; - - -#if __DATA_MODEL__ == __DATA_MODEL_FAR__ - #define portPOINTER_SIZE_TYPE uint32_t -#else - #define portPOINTER_SIZE_TYPE uint16_t -#endif - - -#if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS ) - typedef unsigned int TickType_t; - #define portMAX_DELAY ( TickType_t ) 0xffff -#elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS ) - typedef uint32_t TickType_t; - #define portMAX_DELAY ( TickType_t ) ( 0xFFFFFFFFUL ) -#else - #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width. -#endif + #define portCHAR char + #define portFLOAT float + #define portDOUBLE double + #define portLONG long + #define portSHORT short + #define portSTACK_TYPE uint16_t + #define portBASE_TYPE short + + typedef portSTACK_TYPE StackType_t; + typedef short BaseType_t; + typedef unsigned short UBaseType_t; + + + #if __DATA_MODEL__ == __DATA_MODEL_FAR__ + #define portPOINTER_SIZE_TYPE uint32_t + #else + #define portPOINTER_SIZE_TYPE uint16_t + #endif + + + #if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS ) + typedef unsigned int TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffff + #elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS ) + typedef uint32_t TickType_t; + #define portMAX_DELAY ( TickType_t ) ( 0xFFFFFFFFUL ) + #else + #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width. + #endif /*-----------------------------------------------------------*/ /* Interrupt control macros. */ -#define portDISABLE_INTERRUPTS() __asm ( "DI" ) -#define portENABLE_INTERRUPTS() __asm ( "EI" ) + #define portDISABLE_INTERRUPTS() __asm( "DI" ) + #define portENABLE_INTERRUPTS() __asm( "EI" ) /*-----------------------------------------------------------*/ /* Critical section control macros. */ -#define portNO_CRITICAL_SECTION_NESTING ( ( uint16_t ) 0 ) - -#define portENTER_CRITICAL() \ -{ \ -extern volatile uint16_t usCriticalNesting; \ - \ - portDISABLE_INTERRUPTS(); \ - \ - /* Now interrupts are disabled ulCriticalNesting can be accessed */ \ - /* directly. Increment ulCriticalNesting to keep a count of how many */ \ - /* times portENTER_CRITICAL() has been called. */ \ - usCriticalNesting++; \ -} - -#define portEXIT_CRITICAL() \ -{ \ -extern volatile uint16_t usCriticalNesting; \ - \ - if( usCriticalNesting > portNO_CRITICAL_SECTION_NESTING ) \ - { \ - /* Decrement the nesting count when leaving a critical section. */ \ - usCriticalNesting--; \ - \ - /* If the nesting level has reached zero then interrupts should be */ \ - /* re-enabled. */ \ - if( usCriticalNesting == portNO_CRITICAL_SECTION_NESTING ) \ - { \ - portENABLE_INTERRUPTS(); \ - } \ - } \ -} + #define portNO_CRITICAL_SECTION_NESTING ( ( uint16_t ) 0 ) + + #define portENTER_CRITICAL() \ + { \ + extern volatile uint16_t usCriticalNesting; \ + \ + portDISABLE_INTERRUPTS(); \ + \ + /* Now that interrupts are disabled, ulCriticalNesting can be accessed */ \ + /* directly. Increment ulCriticalNesting to keep a count of how many */ \ + /* times portENTER_CRITICAL() has been called. */ \ + usCriticalNesting++; \ + } + + #define portEXIT_CRITICAL() \ + { \ + extern volatile uint16_t usCriticalNesting; \ + \ + if( usCriticalNesting > portNO_CRITICAL_SECTION_NESTING ) \ + { \ + /* Decrement the nesting count when leaving a critical section. */ \ + usCriticalNesting--; \ + \ + /* If the nesting level has reached zero then interrupts should be */ \ + /* re-enabled. */ \ + if( usCriticalNesting == portNO_CRITICAL_SECTION_NESTING ) \ + { \ + portENABLE_INTERRUPTS(); \ + } \ + } \ + } /*-----------------------------------------------------------*/ /* Task utilities. */ -#define portNOP() __asm( "NOP" ) -#define portYIELD() __asm( "BRK" ) -#define portYIELD_FROM_ISR( xHigherPriorityTaskWoken ) do { if( xHigherPriorityTaskWoken ) vTaskSwitchContext(); } while( 0 ) + #define portNOP() __asm( "NOP" ) + #define portYIELD() __asm( "BRK" ) + #define portYIELD_FROM_ISR( xHigherPriorityTaskWoken ) do { if( xHigherPriorityTaskWoken ) vTaskSwitchContext( ); } while( 0 ) /*-----------------------------------------------------------*/ -/* Hardwware specifics. */ -#define portBYTE_ALIGNMENT 2 -#define portSTACK_GROWTH ( -1 ) -#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) +/* Hardware specifics. */ + #define portBYTE_ALIGNMENT 2 + #define portSTACK_GROWTH ( -1 ) + #define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) /*-----------------------------------------------------------*/ /* Task function macros as described on the FreeRTOS.org WEB site. */ -#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters ) -#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters ) + #define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters ) + #define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters ) /* *INDENT-OFF* */ #ifdef __cplusplus @@ -151,83 +151,83 @@ extern volatile uint16_t usCriticalNesting; \ #endif /* __IAR_SYSTEMS_ICC__ */ -;//----------------------------------------------------------------------------- -;// The macros below are processed for asm sources which include portmacro.h. -;//----------------------------------------------------------------------------- +; /*----------------------------------------------------------------------------- */ + /* The macros below are processed for asm sources which include portmacro.h. */ + /*----------------------------------------------------------------------------- */ #ifdef __IAR_SYSTEMS_ASM__ -;/* Functions and variables used by this file. */ -;//----------------------------------------------------------------------------- + ; /* Functions and variables used by this file. */ + /*----------------------------------------------------------------------------- */ EXTERN _pxCurrentTCB EXTERN _usCriticalNesting -;/* Macro used to declutter calls, depends on the selected code model. */ -;//----------------------------------------------------------------------------- -#if __CODE_MODEL__ == __CODE_MODEL_FAR__ - #define RCALL(X) CALL F:X -#else - #define RCALL(X) CALL X -#endif - - -;/*----------------------------------------------------------------------------- -; * portSAVE_CONTEXT MACRO -; * Saves the context of the general purpose registers, CS and ES (only in __far -; * memory mode) registers the _usCriticalNesting value and the Stack Pointer -; * of the active Task onto the task stack. -; *---------------------------------------------------------------------------*/ -portSAVE_CONTEXT MACRO - PUSH AX ; // Save AX Register to stack. - PUSH HL -#if __CODE_MODEL__ == __CODE_MODEL_FAR__ - MOV A, CS ; // Save CS register. - XCH A, X - MOV A, ES ; // Save ES register. - PUSH AX -#else - MOV A, CS ; // Save CS register. - PUSH AX -#endif - PUSH DE ; // Save the remaining general purpose registers. - PUSH BC - MOVW AX, _usCriticalNesting ; // Save the _usCriticalNesting value. - PUSH AX - MOVW AX, _pxCurrentTCB ; // Save the Task stack pointer. - MOVW HL, AX - MOVW AX, SP - MOVW [HL], AX - ENDM -;//----------------------------------------------------------------------------- - - -;/*----------------------------------------------------------------------------- -; * portRESTORE_CONTEXT MACRO -; * Restores the task Stack Pointer then use this to restore _usCriticalNesting, -; * general purpose registers and the CS and ES (only in __far memory mode) -; * of the selected task from the task stack. -; *---------------------------------------------------------------------------*/ -portRESTORE_CONTEXT MACRO - MOVW AX, _pxCurrentTCB ; // Restore the Task stack pointer. - MOVW HL, AX - MOVW AX, [HL] - MOVW SP, AX - POP AX ; // Restore _usCriticalNesting value. - MOVW _usCriticalNesting, AX - POP BC ; // Restore the necessary general purpose registers. - POP DE -#if __CODE_MODEL__ == __CODE_MODEL_FAR__ - POP AX ; // Restore the ES register. - MOV ES, A - XCH A, X ; // Restore the CS register. - MOV CS, A -#else - POP AX - MOV CS, A ; // Restore CS register. -#endif - POP HL ; // Restore general purpose register HL. - POP AX ; // Restore AX. + ; /* Macro used to declutter calls, depends on the selected code model. */ + /*----------------------------------------------------------------------------- */ + #if __CODE_MODEL__ == __CODE_MODEL_FAR__ + #define RCALL( X ) CALL F: X + #else + #define RCALL( X ) CALL X + #endif + + + ; /*----------------------------------------------------------------------------- + * ; * portSAVE_CONTEXT MACRO + * ; * Saves the context of the general purpose registers, CS and ES (only in __far + * ; * memory mode) registers the _usCriticalNesting value and the Stack Pointer + * ; * of the active Task onto the task stack. + * ; *---------------------------------------------------------------------------*/ + portSAVE_CONTEXT MACRO + PUSH AX; /* Save AX Register to stack. */ + PUSH HL + #if __CODE_MODEL__ == __CODE_MODEL_FAR__ + MOV A, CS; /* Save CS register. */ + XCH A, X + MOV A, ES; /* Save ES register. */ + PUSH AX + #else + MOV A, CS; /* Save CS register. */ + PUSH AX + #endif + PUSH DE; /* Save the remaining general purpose registers. */ + PUSH BC + MOVW AX, _usCriticalNesting; /* Save the _usCriticalNesting value. */ + PUSH AX + MOVW AX, _pxCurrentTCB; /* Save the Task stack pointer. */ + MOVW HL, AX + MOVW AX, SP + MOVW[ HL ], AX + ENDM + ; /*----------------------------------------------------------------------------- */ + + +/*----------------------------------------------------------------------------- + * ; * portRESTORE_CONTEXT MACRO + * ; * Restores the task Stack Pointer then use this to restore _usCriticalNesting, + * ; * general purpose registers and the CS and ES (only in __far memory mode) + * ; * of the selected task from the task stack. + * ; *---------------------------------------------------------------------------*/ + portRESTORE_CONTEXT MACRO + MOVW AX, _pxCurrentTCB; /* Restore the Task stack pointer. */ + MOVW HL, AX + MOVW AX, [ HL ] + MOVW SP, AX + POP AX; /* Restore _usCriticalNesting value. */ + MOVW _usCriticalNesting, AX + POP BC; /* Restore the necessary general purpose registers. */ + POP DE + #if __CODE_MODEL__ == __CODE_MODEL_FAR__ + POP AX; /* Restore the ES register. */ + MOV ES, A + XCH A, X; /* Restore the CS register. */ + MOV CS, A + #else + POP AX + MOV CS, A; /* Restore CS register. */ + #endif + POP HL; /* Restore general purpose register HL. */ + POP AX; /* Restore AX. */ ENDM -;//----------------------------------------------------------------------------- + ; /*----------------------------------------------------------------------------- */ #endif /* __IAR_SYSTEMS_ASM__ */ diff --git a/Source/portable/IAR/RX100/port.c b/Source/portable/IAR/RX100/port.c index 6af4d859f..c3c1631fa 100644 --- a/Source/portable/IAR/RX100/port.c +++ b/Source/portable/IAR/RX100/port.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -27,8 +27,8 @@ */ /*----------------------------------------------------------- - * Implementation of functions defined in portable.h for the SH2A port. - *----------------------------------------------------------*/ +* Implementation of functions defined in portable.h for the SH2A port. +*----------------------------------------------------------*/ /* Standard C includes. */ #include "limits.h" @@ -46,29 +46,29 @@ /*-----------------------------------------------------------*/ /* Tasks should start with interrupts enabled and in Supervisor mode, therefore -PSW is set with U and I set, and PM and IPL clear. */ -#define portINITIAL_PSW ( ( StackType_t ) 0x00030000 ) + * PSW is set with U and I set, and PM and IPL clear. */ +#define portINITIAL_PSW ( ( StackType_t ) 0x00030000 ) /* The peripheral clock is divided by this value before being supplying the -CMT. */ + * CMT. */ #if ( configUSE_TICKLESS_IDLE == 0 ) /* If tickless idle is not used then the divisor can be fixed. */ - #define portCLOCK_DIVISOR 8UL + #define portCLOCK_DIVISOR 8UL #elif ( configPERIPHERAL_CLOCK_HZ >= 12000000 ) - #define portCLOCK_DIVISOR 512UL + #define portCLOCK_DIVISOR 512UL #elif ( configPERIPHERAL_CLOCK_HZ >= 6000000 ) - #define portCLOCK_DIVISOR 128UL + #define portCLOCK_DIVISOR 128UL #elif ( configPERIPHERAL_CLOCK_HZ >= 1000000 ) - #define portCLOCK_DIVISOR 32UL + #define portCLOCK_DIVISOR 32UL #else - #define portCLOCK_DIVISOR 8UL + #define portCLOCK_DIVISOR 8UL #endif /* Keys required to lock and unlock access to certain system registers -respectively. */ -#define portUNLOCK_KEY 0xA50B -#define portLOCK_KEY 0xA500 + * respectively. */ +#define portUNLOCK_KEY 0xA50B +#define portLOCK_KEY 0xA500 /*-----------------------------------------------------------*/ @@ -92,9 +92,10 @@ __interrupt static void prvTickISR( void ); */ static void prvSetupTimerInterrupt( void ); #ifndef configSETUP_TICK_INTERRUPT - /* The user has not provided their own tick interrupt configuration so use - the definition in this file (which uses the interval timer). */ - #define configSETUP_TICK_INTERRUPT() prvSetupTimerInterrupt() + +/* The user has not provided their own tick interrupt configuration so use + * the definition in this file (which uses the interval timer). */ + #define configSETUP_TICK_INTERRUPT() prvSetupTimerInterrupt() #endif /* configSETUP_TICK_INTERRUPT */ /* @@ -108,7 +109,7 @@ static void prvSetupTimerInterrupt( void ); /*-----------------------------------------------------------*/ -extern void *pxCurrentTCB; +extern void * pxCurrentTCB; /*-----------------------------------------------------------*/ @@ -117,33 +118,35 @@ static const uint32_t ulMatchValueForOneTick = ( ( configPERIPHERAL_CLOCK_HZ / p #if configUSE_TICKLESS_IDLE == 1 - /* Holds the maximum number of ticks that can be suppressed - which is - basically how far into the future an interrupt can be generated. Set - during initialisation. This is the maximum possible value that the - compare match register can hold divided by ulMatchValueForOneTick. */ +/* Holds the maximum number of ticks that can be suppressed - which is + * basically how far into the future an interrupt can be generated. Set + * during initialisation. This is the maximum possible value that the + * compare match register can hold divided by ulMatchValueForOneTick. */ static const TickType_t xMaximumPossibleSuppressedTicks = USHRT_MAX / ( ( configPERIPHERAL_CLOCK_HZ / portCLOCK_DIVISOR ) / configTICK_RATE_HZ ); - /* Flag set from the tick interrupt to allow the sleep processing to know if - sleep mode was exited because of a tick interrupt, or an interrupt - generated by something else. */ +/* Flag set from the tick interrupt to allow the sleep processing to know if + * sleep mode was exited because of a tick interrupt, or an interrupt + * generated by something else. */ static volatile uint32_t ulTickFlag = pdFALSE; - /* The CMT counter is stopped temporarily each time it is re-programmed. - The following constant offsets the CMT counter match value by the number of - CMT counts that would typically be missed while the counter was stopped to - compensate for the lost time. The large difference between the divided CMT - clock and the CPU clock means it is likely ulStoppedTimerCompensation will - equal zero - and be optimised away. */ +/* The CMT counter is stopped temporarily each time it is re-programmed. + * The following constant offsets the CMT counter match value by the number of + * CMT counts that would typically be missed while the counter was stopped to + * compensate for the lost time. The large difference between the divided CMT + * clock and the CPU clock means it is likely ulStoppedTimerCompensation will + * equal zero - and be optimised away. */ static const uint32_t ulStoppedTimerCompensation = 100UL / ( configCPU_CLOCK_HZ / ( configPERIPHERAL_CLOCK_HZ / portCLOCK_DIVISOR ) ); -#endif +#endif /* if configUSE_TICKLESS_IDLE == 1 */ /*-----------------------------------------------------------*/ /* * See header file for description. */ -StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters ) +StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, + TaskFunction_t pxCode, + void * pvParameters ) { /* Offset to end up on 8 byte boundary. */ pxTopOfStack--; @@ -158,8 +161,8 @@ StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t px *pxTopOfStack = ( StackType_t ) pxCode; /* When debugging it can be useful if every register is set to a known - value. Otherwise code space can be saved by just setting the registers - that need to be set. */ + * value. Otherwise code space can be saved by just setting the registers + * that need to be set. */ #ifdef USE_FULL_REGISTER_INITIALISATION { pxTopOfStack--; @@ -192,19 +195,19 @@ StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t px *pxTopOfStack = 0x22222222; pxTopOfStack--; } - #else + #else /* ifdef USE_FULL_REGISTER_INITIALISATION */ { /* Leave space for the registers that will get popped from the stack - when the task first starts executing. */ + * when the task first starts executing. */ pxTopOfStack -= 15; } - #endif + #endif /* ifdef USE_FULL_REGISTER_INITIALISATION */ *pxTopOfStack = ( StackType_t ) pvParameters; /* R1 */ pxTopOfStack--; - *pxTopOfStack = 0x12345678; /* Accumulator. */ + *pxTopOfStack = 0x12345678; /* Accumulator. */ pxTopOfStack--; - *pxTopOfStack = 0x87654321; /* Accumulator. */ + *pxTopOfStack = 0x87654321; /* Accumulator. */ return pxTopOfStack; } @@ -216,10 +219,10 @@ BaseType_t xPortStartScheduler( void ) if( pxCurrentTCB != NULL ) { /* Call an application function to set up the timer that will generate - the tick interrupt. This way the application can decide which - peripheral to use. If tickless mode is used then the default - implementation defined in this file (which uses CMT0) should not be - overridden. */ + * the tick interrupt. This way the application can decide which + * peripheral to use. If tickless mode is used then the default + * implementation defined in this file (which uses CMT0) should not be + * overridden. */ configSETUP_TICK_INTERRUPT(); /* Enable the software interrupt. */ @@ -236,11 +239,11 @@ BaseType_t xPortStartScheduler( void ) } /* Execution should not reach here as the tasks are now running! - prvSetupTimerInterrupt() is called here to prevent the compiler outputting - a warning about a statically declared function not being referenced in the - case that the application writer has provided their own tick interrupt - configuration routine (and defined configSETUP_TICK_INTERRUPT() such that - their own routine will be called in place of prvSetupTimerInterrupt()). */ + * prvSetupTimerInterrupt() is called here to prevent the compiler outputting + * a warning about a statically declared function not being referenced in the + * case that the application writer has provided their own tick interrupt + * configuration routine (and defined configSETUP_TICK_INTERRUPT() such that + * their own routine will be called in place of prvSetupTimerInterrupt()). */ prvSetupTimerInterrupt(); /* Should not get here. */ @@ -255,7 +258,7 @@ __interrupt static void prvTickISR( void ) __enable_interrupt(); /* Increment the tick, and perform any processing the new tick value - necessitates. */ + * necessitates. */ __set_interrupt_level( configMAX_SYSCALL_INTERRUPT_PRIORITY ); { if( xTaskIncrementTick() != pdFALSE ) @@ -271,7 +274,7 @@ __interrupt static void prvTickISR( void ) ulTickFlag = pdTRUE; /* If this is the first tick since exiting tickless mode then the CMT - compare match value needs resetting. */ + * compare match value needs resetting. */ CMT0.CMCOR = ( uint16_t ) ulMatchValueForOneTick; } #endif @@ -281,7 +284,7 @@ __interrupt static void prvTickISR( void ) void vPortEndScheduler( void ) { /* Not implemented in ports where there is nothing to return to. - Artificially force an assert. */ + * Artificially force an assert. */ configASSERT( pxCurrentTCB == NULL ); } /*-----------------------------------------------------------*/ @@ -320,11 +323,11 @@ static void prvSetupTimerInterrupt( void ) { CMT0.CMCR.BIT.CKS = 0; } - #else + #else /* if portCLOCK_DIVISOR == 512 */ { #error Invalid portCLOCK_DIVISOR setting } - #endif + #endif /* if portCLOCK_DIVISOR == 512 */ /* Enable the interrupt... */ @@ -346,8 +349,8 @@ static void prvSetupTimerInterrupt( void ) configPRE_SLEEP_PROCESSING( xExpectedIdleTime ); /* xExpectedIdleTime being set to 0 by configPRE_SLEEP_PROCESSING() - means the application defined code has already executed the WAIT - instruction. */ + * means the application defined code has already executed the WAIT + * instruction. */ if( xExpectedIdleTime > 0 ) { __wait_for_interrupt(); @@ -364,8 +367,8 @@ static void prvSetupTimerInterrupt( void ) void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime ) { - uint32_t ulMatchValue, ulCompleteTickPeriods, ulCurrentCount; - eSleepModeStatus eSleepAction; + uint32_t ulMatchValue, ulCompleteTickPeriods, ulCurrentCount; + eSleepModeStatus eSleepAction; /* THIS FUNCTION IS CALLED WITH THE SCHEDULER SUSPENDED. */ @@ -376,38 +379,41 @@ static void prvSetupTimerInterrupt( void ) } /* Calculate the reload value required to wait xExpectedIdleTime tick - periods. */ + * periods. */ ulMatchValue = ulMatchValueForOneTick * xExpectedIdleTime; + if( ulMatchValue > ulStoppedTimerCompensation ) { /* Compensate for the fact that the CMT is going to be stopped - momentarily. */ + * momentarily. */ ulMatchValue -= ulStoppedTimerCompensation; } /* Stop the CMT momentarily. The time the CMT is stopped for is - accounted for as best it can be, but using the tickless mode will - inevitably result in some tiny drift of the time maintained by the - kernel with respect to calendar time. */ + * accounted for as best it can be, but using the tickless mode will + * inevitably result in some tiny drift of the time maintained by the + * kernel with respect to calendar time. */ CMT.CMSTR0.BIT.STR0 = 0; + while( CMT.CMSTR0.BIT.STR0 == 1 ) { /* Nothing to do here. */ } /* Critical section using the global interrupt bit as the i bit is - automatically reset by the WAIT instruction. */ + * automatically reset by the WAIT instruction. */ __disable_interrupt(); /* The tick flag is set to false before sleeping. If it is true when - sleep mode is exited then sleep mode was probably exited because the - tick was suppressed for the entire xExpectedIdleTime period. */ + * sleep mode is exited then sleep mode was probably exited because the + * tick was suppressed for the entire xExpectedIdleTime period. */ ulTickFlag = pdFALSE; /* If a context switch is pending then abandon the low power entry as - the context switch might have been pended by an external interrupt that - requires processing. */ + * the context switch might have been pended by an external interrupt that + * requires processing. */ eSleepAction = eTaskConfirmSleepModeStatus(); + if( eSleepAction == eAbortSleep ) { /* Restart tick. */ @@ -426,7 +432,7 @@ static void prvSetupTimerInterrupt( void ) SYSTEM.PRCR.WORD = portLOCK_KEY; /* Sleep until something happens. Calling prvSleep() will - automatically reset the i bit in the PSW. */ + * automatically reset the i bit in the PSW. */ prvSleep( xExpectedIdleTime ); /* Restart the CMT. */ @@ -446,7 +452,7 @@ static void prvSetupTimerInterrupt( void ) SYSTEM.PRCR.WORD = portLOCK_KEY; /* Adjust the match value to take into account that the current - time slice is already partially complete. */ + * time slice is already partially complete. */ ulMatchValue -= ( uint32_t ) CMT0.CMCNT; CMT0.CMCOR = ( uint16_t ) ulMatchValue; @@ -455,14 +461,15 @@ static void prvSetupTimerInterrupt( void ) CMT.CMSTR0.BIT.STR0 = 1; /* Sleep until something happens. Calling prvSleep() will - automatically reset the i bit in the PSW. */ + * automatically reset the i bit in the PSW. */ prvSleep( xExpectedIdleTime ); /* Stop CMT. Again, the time the SysTick is stopped for is - accounted for as best it can be, but using the tickless mode will - inevitably result in some tiny drift of the time maintained by the - kernel with respect to calendar time. */ + * accounted for as best it can be, but using the tickless mode will + * inevitably result in some tiny drift of the time maintained by the + * kernel with respect to calendar time. */ CMT.CMSTR0.BIT.STR0 = 0; + while( CMT.CMSTR0.BIT.STR0 == 1 ) { /* Nothing to do here. */ @@ -473,42 +480,42 @@ static void prvSetupTimerInterrupt( void ) if( ulTickFlag != pdFALSE ) { /* The tick interrupt has already executed, although because - this function is called with the scheduler suspended the actual - tick processing will not occur until after this function has - exited. Reset the match value with whatever remains of this - tick period. */ + * this function is called with the scheduler suspended the actual + * tick processing will not occur until after this function has + * exited. Reset the match value with whatever remains of this + * tick period. */ ulMatchValue = ulMatchValueForOneTick - ulCurrentCount; CMT0.CMCOR = ( uint16_t ) ulMatchValue; /* The tick interrupt handler will already have pended the tick - processing in the kernel. As the pending tick will be - processed as soon as this function exits, the tick value - maintained by the tick is stepped forward by one less than the - time spent sleeping. The actual stepping of the tick appears - later in this function. */ + * processing in the kernel. As the pending tick will be + * processed as soon as this function exits, the tick value + * maintained by the tick is stepped forward by one less than the + * time spent sleeping. The actual stepping of the tick appears + * later in this function. */ ulCompleteTickPeriods = xExpectedIdleTime - 1UL; } else { /* Something other than the tick interrupt ended the sleep. - How many complete tick periods passed while the processor was - sleeping? */ + * How many complete tick periods passed while the processor was + * sleeping? */ ulCompleteTickPeriods = ulCurrentCount / ulMatchValueForOneTick; /* The match value is set to whatever fraction of a single tick - period remains. */ + * period remains. */ ulMatchValue = ulCurrentCount - ( ulCompleteTickPeriods * ulMatchValueForOneTick ); CMT0.CMCOR = ( uint16_t ) ulMatchValue; } /* Restart the CMT so it runs up to the match value. The match value - will get set to the value required to generate exactly one tick period - the next time the CMT interrupt executes. */ + * will get set to the value required to generate exactly one tick period + * the next time the CMT interrupt executes. */ CMT0.CMCNT = 0; CMT.CMSTR0.BIT.STR0 = 1; /* Wind the tick forward by the number of tick periods that the CPU - remained in a low power state. */ + * remained in a low power state. */ vTaskStepTick( ulCompleteTickPeriods ); } } diff --git a/Source/portable/IAR/RX100/port_asm.s b/Source/portable/IAR/RX100/port_asm.s index 0389b702c..2b79292a3 100644 --- a/Source/portable/IAR/RX100/port_asm.s +++ b/Source/portable/IAR/RX100/port_asm.s @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/Source/portable/IAR/RX100/portmacro.h b/Source/portable/IAR/RX100/portmacro.h index 513d0f0f7..7e75e07b4 100644 --- a/Source/portable/IAR/RX100/portmacro.h +++ b/Source/portable/IAR/RX100/portmacro.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -52,40 +52,40 @@ */ /* Type definitions - these are a bit legacy and not really used now, other than -portSTACK_TYPE and portBASE_TYPE. */ -#define portCHAR char -#define portFLOAT float -#define portDOUBLE double -#define portLONG long -#define portSHORT short -#define portSTACK_TYPE uint32_t -#define portBASE_TYPE long - -typedef portSTACK_TYPE StackType_t; -typedef long BaseType_t; -typedef unsigned long UBaseType_t; - - -#if( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS ) - typedef uint16_t TickType_t; - #define portMAX_DELAY ( TickType_t ) 0xffff + * portSTACK_TYPE and portBASE_TYPE. */ +#define portCHAR char +#define portFLOAT float +#define portDOUBLE double +#define portLONG long +#define portSHORT short +#define portSTACK_TYPE uint32_t +#define portBASE_TYPE long + +typedef portSTACK_TYPE StackType_t; +typedef long BaseType_t; +typedef unsigned long UBaseType_t; + + +#if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS ) + typedef uint16_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffff #elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS ) - typedef uint32_t TickType_t; - #define portMAX_DELAY ( TickType_t ) 0xffffffffUL + typedef uint32_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffffffffUL - /* 32-bit tick type on a 32-bit architecture, so reads of the tick count do - not need to be guarded with a critical section. */ - #define portTICK_TYPE_IS_ATOMIC 1 +/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do + * not need to be guarded with a critical section. */ + #define portTICK_TYPE_IS_ATOMIC 1 #else #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width. #endif /*-----------------------------------------------------------*/ /* Hardware specifics. */ -#define portBYTE_ALIGNMENT 8 /* Could make four, according to manual. */ -#define portSTACK_GROWTH -1 -#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) -#define portNOP() __no_operation() +#define portBYTE_ALIGNMENT 8 /* Could make four, according to manual. */ +#define portSTACK_GROWTH -1 +#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) +#define portNOP() __no_operation() #define portYIELD() \ __asm volatile \ @@ -96,55 +96,55 @@ typedef unsigned long UBaseType_t; ::: "R15" \ ) -#define portYIELD_FROM_ISR( x ) do { if( ( x ) != pdFALSE ) { portYIELD(); } } while( 0 ) +#define portYIELD_FROM_ISR( x ) do { if( ( x ) != pdFALSE ) { portYIELD(); } } while( 0 ) /* These macros should not be called directly, but through the -taskENTER_CRITICAL() and taskEXIT_CRITICAL() macros. An extra check is -performed if configASSERT() is defined to ensure an assertion handler does not -inadvertently attempt to lower the IPL when the call to assert was triggered -because the IPL value was found to be above configMAX_SYSCALL_INTERRUPT_PRIORITY -when an ISR safe FreeRTOS API function was executed. ISR safe FreeRTOS API -functions are those that end in FromISR. FreeRTOS maintains a separate -interrupt API to ensure API function and interrupt entry is as fast and as -simple as possible. */ -#define portENABLE_INTERRUPTS() __set_interrupt_level( ( uint8_t ) 0 ) + * taskENTER_CRITICAL() and taskEXIT_CRITICAL() macros. An extra check is + * performed if configASSERT() is defined to ensure an assertion handler does not + * inadvertently attempt to lower the IPL when the call to assert was triggered + * because the IPL value was found to be above configMAX_SYSCALL_INTERRUPT_PRIORITY + * when an ISR safe FreeRTOS API function was executed. ISR safe FreeRTOS API + * functions are those that end in FromISR. FreeRTOS maintains a separate + * interrupt API to ensure API function and interrupt entry is as fast and as + * simple as possible. */ +#define portENABLE_INTERRUPTS() __set_interrupt_level( ( uint8_t ) 0 ) #ifdef configASSERT - #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() configASSERT( ( __get_interrupt_level() <= configMAX_SYSCALL_INTERRUPT_PRIORITY ) ) - #define portDISABLE_INTERRUPTS() if( __get_interrupt_level() < configMAX_SYSCALL_INTERRUPT_PRIORITY ) __set_interrupt_level( ( uint8_t ) configMAX_SYSCALL_INTERRUPT_PRIORITY ) + #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() configASSERT( ( __get_interrupt_level() <= configMAX_SYSCALL_INTERRUPT_PRIORITY ) ) + #define portDISABLE_INTERRUPTS() if( __get_interrupt_level() < configMAX_SYSCALL_INTERRUPT_PRIORITY ) __set_interrupt_level( ( uint8_t ) configMAX_SYSCALL_INTERRUPT_PRIORITY ) #else - #define portDISABLE_INTERRUPTS() __set_interrupt_level( ( uint8_t ) configMAX_SYSCALL_INTERRUPT_PRIORITY ) + #define portDISABLE_INTERRUPTS() __set_interrupt_level( ( uint8_t ) configMAX_SYSCALL_INTERRUPT_PRIORITY ) #endif /* Critical nesting counts are stored in the TCB. */ -#define portCRITICAL_NESTING_IN_TCB ( 1 ) +#define portCRITICAL_NESTING_IN_TCB ( 1 ) /* The critical nesting functions defined within tasks.c. */ extern void vTaskEnterCritical( void ); extern void vTaskExitCritical( void ); -#define portENTER_CRITICAL() vTaskEnterCritical() -#define portEXIT_CRITICAL() vTaskExitCritical() +#define portENTER_CRITICAL() vTaskEnterCritical() +#define portEXIT_CRITICAL() vTaskExitCritical() /* As this port allows interrupt nesting... */ -#define portSET_INTERRUPT_MASK_FROM_ISR() __get_interrupt_level(); portDISABLE_INTERRUPTS() -#define portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus ) __set_interrupt_level( ( uint8_t ) ( uxSavedInterruptStatus ) ) +#define portSET_INTERRUPT_MASK_FROM_ISR() __get_interrupt_level(); portDISABLE_INTERRUPTS() +#define portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus ) __set_interrupt_level( ( uint8_t ) ( uxSavedInterruptStatus ) ) /* Tickless idle/low power functionality. */ #if configUSE_TICKLESS_IDLE == 1 #ifndef portSUPPRESS_TICKS_AND_SLEEP extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime ); - #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime ) vPortSuppressTicksAndSleep( xExpectedIdleTime ) + #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime ) vPortSuppressTicksAndSleep( xExpectedIdleTime ) #endif #endif /*-----------------------------------------------------------*/ /* Task function macros as described on the FreeRTOS.org WEB site. */ -#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters ) -#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters ) +#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters ) +#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters ) /* Prevent warnings of undefined behaviour: the order of volatile accesses is -undefined - all warnings have been manually checked and are not an issue, and -the warnings cannot be prevent by code changes without undesirable effects. */ + * undefined - all warnings have been manually checked and are not an issue, and + * the warnings cannot be prevent by code changes without undesirable effects. */ #pragma diag_suppress=Pa082 /* *INDENT-OFF* */ diff --git a/Source/portable/IAR/RX600/port.c b/Source/portable/IAR/RX600/port.c index b7aa568d4..f7101ec00 100644 --- a/Source/portable/IAR/RX600/port.c +++ b/Source/portable/IAR/RX600/port.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -27,8 +27,8 @@ */ /*----------------------------------------------------------- - * Implementation of functions defined in portable.h for the SH2A port. - *----------------------------------------------------------*/ +* Implementation of functions defined in portable.h for the SH2A port. +*----------------------------------------------------------*/ /* Scheduler includes. */ #include "FreeRTOS.h" @@ -43,8 +43,8 @@ /*-----------------------------------------------------------*/ /* Tasks should start with interrupts enabled and in Supervisor mode, therefore -PSW is set with U and I set, and PM and IPL clear. */ -#define portINITIAL_PSW ( ( StackType_t ) 0x00030000 ) + * PSW is set with U and I set, and PM and IPL clear. */ +#define portINITIAL_PSW ( ( StackType_t ) 0x00030000 ) #define portINITIAL_FPSW ( ( StackType_t ) 0x00000100 ) /*-----------------------------------------------------------*/ @@ -63,14 +63,16 @@ __interrupt void vTickISR( void ); /*-----------------------------------------------------------*/ -extern void *pxCurrentTCB; +extern void * pxCurrentTCB; /*-----------------------------------------------------------*/ /* * See header file for description. */ -StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters ) +StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, + TaskFunction_t pxCode, + void * pvParameters ) { /* R0 is not included as it is the stack pointer. */ @@ -81,8 +83,8 @@ StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t px *pxTopOfStack = ( StackType_t ) pxCode; /* When debugging it can be useful if every register is set to a known - value. Otherwise code space can be saved by just setting the registers - that need to be set. */ + * value. Otherwise code space can be saved by just setting the registers + * that need to be set. */ #ifdef USE_FULL_REGISTER_INITIALISATION { pxTopOfStack--; @@ -115,11 +117,11 @@ StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t px *pxTopOfStack = 0x22222222; pxTopOfStack--; } - #else + #else /* ifdef USE_FULL_REGISTER_INITIALISATION */ { pxTopOfStack -= 15; } - #endif + #endif /* ifdef USE_FULL_REGISTER_INITIALISATION */ *pxTopOfStack = ( StackType_t ) pvParameters; /* R1 */ pxTopOfStack--; @@ -135,14 +137,14 @@ StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t px BaseType_t xPortStartScheduler( void ) { -extern void vApplicationSetupTimerInterrupt( void ); + extern void vApplicationSetupTimerInterrupt( void ); /* Use pxCurrentTCB just so it does not get optimised away. */ if( pxCurrentTCB != NULL ) { /* Call an application function to set up the timer that will generate the - tick interrupt. This way the application can decide which peripheral to - use. A demo application is provided to show a suitable example. */ + * tick interrupt. This way the application can decide which peripheral to + * use. A demo application is provided to show a suitable example. */ vApplicationSetupTimerInterrupt(); /* Enable the software interrupt. */ @@ -170,7 +172,7 @@ __interrupt void vTickISR( void ) __enable_interrupt(); /* Increment the tick, and perform any processing the new tick value - necessitates. */ + * necessitates. */ __set_interrupt_level( configMAX_SYSCALL_INTERRUPT_PRIORITY ); { if( xTaskIncrementTick() != pdFALSE ) @@ -185,7 +187,7 @@ __interrupt void vTickISR( void ) void vPortEndScheduler( void ) { /* Not implemented in ports where there is nothing to return to. - Artificially force an assert. */ + * Artificially force an assert. */ configASSERT( pxCurrentTCB == NULL ); } /*-----------------------------------------------------------*/ diff --git a/Source/portable/IAR/RX600/port_asm.s b/Source/portable/IAR/RX600/port_asm.s index 066620ad9..85494222c 100644 --- a/Source/portable/IAR/RX600/port_asm.s +++ b/Source/portable/IAR/RX600/port_asm.s @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/Source/portable/IAR/RX600/portmacro.h b/Source/portable/IAR/RX600/portmacro.h index bb2b8344b..7500b30aa 100644 --- a/Source/portable/IAR/RX600/portmacro.h +++ b/Source/portable/IAR/RX600/portmacro.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -49,92 +49,92 @@ */ /* Type definitions - these are a bit legacy and not really used now, other than -portSTACK_TYPE and portBASE_TYPE. */ -#define portCHAR char -#define portFLOAT float -#define portDOUBLE double -#define portLONG long -#define portSHORT short -#define portSTACK_TYPE uint32_t -#define portBASE_TYPE long - -typedef portSTACK_TYPE StackType_t; -typedef long BaseType_t; -typedef unsigned long UBaseType_t; - - -#if( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS ) - typedef uint16_t TickType_t; - #define portMAX_DELAY ( TickType_t ) 0xffff + * portSTACK_TYPE and portBASE_TYPE. */ +#define portCHAR char +#define portFLOAT float +#define portDOUBLE double +#define portLONG long +#define portSHORT short +#define portSTACK_TYPE uint32_t +#define portBASE_TYPE long + +typedef portSTACK_TYPE StackType_t; +typedef long BaseType_t; +typedef unsigned long UBaseType_t; + + +#if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS ) + typedef uint16_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffff #elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS ) - typedef uint32_t TickType_t; - #define portMAX_DELAY ( TickType_t ) 0xffffffffUL + typedef uint32_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffffffffUL - /* 32-bit tick type on a 32-bit architecture, so reads of the tick count do - not need to be guarded with a critical section. */ - #define portTICK_TYPE_IS_ATOMIC 1 +/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do + * not need to be guarded with a critical section. */ + #define portTICK_TYPE_IS_ATOMIC 1 #else #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width. #endif /*-----------------------------------------------------------*/ /* Hardware specifics. */ -#define portBYTE_ALIGNMENT 8 /* Could make four, according to manual. */ -#define portSTACK_GROWTH -1 -#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) -#define portNOP() __no_operation() +#define portBYTE_ALIGNMENT 8 /* Could make four, according to manual. */ +#define portSTACK_GROWTH -1 +#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) +#define portNOP() __no_operation() /* Yield equivalent to "*portITU_SWINTR = 0x01; ( void ) *portITU_SWINTR;" -where portITU_SWINTR is the location of the software interrupt register -(0x000872E0). Don't rely on the assembler to select a register, so instead -save and restore clobbered registers manually. */ -#define portYIELD() \ - __asm volatile \ - ( \ - "PUSH.L R10 \n" \ - "MOV.L #0x872E0, R10 \n" \ - "MOV.B #0x1, [R10] \n" \ - "MOV.L [R10], R10 \n" \ - "POP R10 \n" \ + * where portITU_SWINTR is the location of the software interrupt register + * (0x000872E0). Don't rely on the assembler to select a register, so instead + * save and restore clobbered registers manually. */ +#define portYIELD() \ + __asm volatile \ + ( \ + "PUSH.L R10 \n" \ + "MOV.L #0x872E0, R10 \n" \ + "MOV.B #0x1, [R10] \n" \ + "MOV.L [R10], R10 \n" \ + "POP R10 \n" \ ) -#define portYIELD_FROM_ISR( x ) do { if( ( x ) != pdFALSE ) portYIELD(); } while( 0 ) +#define portYIELD_FROM_ISR( x ) do { if( ( x ) != pdFALSE ) portYIELD( ); } while( 0 ) /* These macros should not be called directly, but through the -taskENTER_CRITICAL() and taskEXIT_CRITICAL() macros. An extra check is -performed if configASSERT() is defined to ensure an assertion handler does not -inadvertently attempt to lower the IPL when the call to assert was triggered -because the IPL value was found to be above configMAX_SYSCALL_INTERRUPT_PRIORITY -when an ISR safe FreeRTOS API function was executed. ISR safe FreeRTOS API -functions are those that end in FromISR. FreeRTOS maintains a separate -interrupt API to ensure API function and interrupt entry is as fast and as -simple as possible. */ -#define portENABLE_INTERRUPTS() __set_interrupt_level( ( uint8_t ) 0 ) + * taskENTER_CRITICAL() and taskEXIT_CRITICAL() macros. An extra check is + * performed if configASSERT() is defined to ensure an assertion handler does not + * inadvertently attempt to lower the IPL when the call to assert was triggered + * because the IPL value was found to be above configMAX_SYSCALL_INTERRUPT_PRIORITY + * when an ISR safe FreeRTOS API function was executed. ISR safe FreeRTOS API + * functions are those that end in FromISR. FreeRTOS maintains a separate + * interrupt API to ensure API function and interrupt entry is as fast and as + * simple as possible. */ +#define portENABLE_INTERRUPTS() __set_interrupt_level( ( uint8_t ) 0 ) #ifdef configASSERT - #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() configASSERT( ( __get_interrupt_level() <= configMAX_SYSCALL_INTERRUPT_PRIORITY ) ) - #define portDISABLE_INTERRUPTS() if( __get_interrupt_level() < configMAX_SYSCALL_INTERRUPT_PRIORITY ) __set_interrupt_level( ( uint8_t ) configMAX_SYSCALL_INTERRUPT_PRIORITY ) + #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() configASSERT( ( __get_interrupt_level() <= configMAX_SYSCALL_INTERRUPT_PRIORITY ) ) + #define portDISABLE_INTERRUPTS() if( __get_interrupt_level() < configMAX_SYSCALL_INTERRUPT_PRIORITY ) __set_interrupt_level( ( uint8_t ) configMAX_SYSCALL_INTERRUPT_PRIORITY ) #else - #define portDISABLE_INTERRUPTS() __set_interrupt_level( ( uint8_t ) configMAX_SYSCALL_INTERRUPT_PRIORITY ) + #define portDISABLE_INTERRUPTS() __set_interrupt_level( ( uint8_t ) configMAX_SYSCALL_INTERRUPT_PRIORITY ) #endif /* Critical nesting counts are stored in the TCB. */ -#define portCRITICAL_NESTING_IN_TCB ( 1 ) +#define portCRITICAL_NESTING_IN_TCB ( 1 ) /* The critical nesting functions defined within tasks.c. */ extern void vTaskEnterCritical( void ); extern void vTaskExitCritical( void ); -#define portENTER_CRITICAL() vTaskEnterCritical() -#define portEXIT_CRITICAL() vTaskExitCritical() +#define portENTER_CRITICAL() vTaskEnterCritical() +#define portEXIT_CRITICAL() vTaskExitCritical() /* As this port allows interrupt nesting... */ -#define portSET_INTERRUPT_MASK_FROM_ISR() __get_interrupt_level(); portDISABLE_INTERRUPTS() -#define portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus ) __set_interrupt_level( ( uint8_t ) ( uxSavedInterruptStatus ) ) +#define portSET_INTERRUPT_MASK_FROM_ISR() __get_interrupt_level(); portDISABLE_INTERRUPTS() +#define portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus ) __set_interrupt_level( ( uint8_t ) ( uxSavedInterruptStatus ) ) /*-----------------------------------------------------------*/ /* Task function macros as described on the FreeRTOS.org WEB site. */ -#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters ) -#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters ) +#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters ) +#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters ) /* *INDENT-OFF* */ #ifdef __cplusplus diff --git a/Source/portable/IAR/RX700v3_DPFPU/port.c b/Source/portable/IAR/RX700v3_DPFPU/port.c index e383ab565..6f0f95fef 100644 --- a/Source/portable/IAR/RX700v3_DPFPU/port.c +++ b/Source/portable/IAR/RX700v3_DPFPU/port.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -54,22 +54,22 @@ /* Tasks should start with interrupts enabled and in Supervisor mode, therefore * PSW is set with U and I set, and PM and IPL clear. */ -#define portINITIAL_PSW ( ( StackType_t ) 0x00030000 ) -#define portINITIAL_FPSW ( ( StackType_t ) 0x00000100 ) -#define portINITIAL_DPSW ( ( StackType_t ) 0x00000100 ) -#define portINITIAL_DCMR ( ( StackType_t ) 0x00000000 ) -#define portINITIAL_DECNT ( ( StackType_t ) 0x00000001 ) +#define portINITIAL_PSW ( ( StackType_t ) 0x00030000 ) +#define portINITIAL_FPSW ( ( StackType_t ) 0x00000100 ) +#define portINITIAL_DPSW ( ( StackType_t ) 0x00000100 ) +#define portINITIAL_DCMR ( ( StackType_t ) 0x00000000 ) +#define portINITIAL_DECNT ( ( StackType_t ) 0x00000001 ) /* Tasks are not created with a DPFPU context, but can be given a DPFPU context * after they have been created. A variable is stored as part of the tasks context * that holds portNO_DPFPU_CONTEXT if the task does not have a DPFPU context, or * any other value if the task does have a DPFPU context. */ -#define portNO_DPFPU_CONTEXT ( ( StackType_t ) 0 ) -#define portHAS_DPFPU_CONTEXT ( ( StackType_t ) 1 ) +#define portNO_DPFPU_CONTEXT ( ( StackType_t ) 0 ) +#define portHAS_DPFPU_CONTEXT ( ( StackType_t ) 1 ) /* The space on the stack required to hold the DPFPU data registers. This is 16 * 64-bit registers. */ -#define portDPFPU_DATA_REGISTER_WORDS ( 16 * 2 ) +#define portDPFPU_DATA_REGISTER_WORDS ( 16 * 2 ) /*-----------------------------------------------------------*/ @@ -128,41 +128,41 @@ StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, * value. Otherwise code space can be saved by just setting the registers * that need to be set. */ #ifdef USE_FULL_REGISTER_INITIALISATION - { - pxTopOfStack--; - *pxTopOfStack = 0xffffffff; /* r15. */ - pxTopOfStack--; - *pxTopOfStack = 0xeeeeeeee; - pxTopOfStack--; - *pxTopOfStack = 0xdddddddd; - pxTopOfStack--; - *pxTopOfStack = 0xcccccccc; - pxTopOfStack--; - *pxTopOfStack = 0xbbbbbbbb; - pxTopOfStack--; - *pxTopOfStack = 0xaaaaaaaa; - pxTopOfStack--; - *pxTopOfStack = 0x99999999; - pxTopOfStack--; - *pxTopOfStack = 0x88888888; - pxTopOfStack--; - *pxTopOfStack = 0x77777777; - pxTopOfStack--; - *pxTopOfStack = 0x66666666; - pxTopOfStack--; - *pxTopOfStack = 0x55555555; - pxTopOfStack--; - *pxTopOfStack = 0x44444444; - pxTopOfStack--; - *pxTopOfStack = 0x33333333; - pxTopOfStack--; - *pxTopOfStack = 0x22222222; - pxTopOfStack--; - } + { + pxTopOfStack--; + *pxTopOfStack = 0xffffffff; /* r15. */ + pxTopOfStack--; + *pxTopOfStack = 0xeeeeeeee; + pxTopOfStack--; + *pxTopOfStack = 0xdddddddd; + pxTopOfStack--; + *pxTopOfStack = 0xcccccccc; + pxTopOfStack--; + *pxTopOfStack = 0xbbbbbbbb; + pxTopOfStack--; + *pxTopOfStack = 0xaaaaaaaa; + pxTopOfStack--; + *pxTopOfStack = 0x99999999; + pxTopOfStack--; + *pxTopOfStack = 0x88888888; + pxTopOfStack--; + *pxTopOfStack = 0x77777777; + pxTopOfStack--; + *pxTopOfStack = 0x66666666; + pxTopOfStack--; + *pxTopOfStack = 0x55555555; + pxTopOfStack--; + *pxTopOfStack = 0x44444444; + pxTopOfStack--; + *pxTopOfStack = 0x33333333; + pxTopOfStack--; + *pxTopOfStack = 0x22222222; + pxTopOfStack--; + } #else /* ifdef USE_FULL_REGISTER_INITIALISATION */ - { - pxTopOfStack -= 15; - } + { + pxTopOfStack -= 15; + } #endif /* ifdef USE_FULL_REGISTER_INITIALISATION */ *pxTopOfStack = ( StackType_t ) pvParameters; /* R1 */ @@ -182,73 +182,73 @@ StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, *pxTopOfStack = 0x66666666; /* Accumulator 0. */ #if ( configUSE_TASK_DPFPU_SUPPORT == 1 ) - { - /* The task will start without a DPFPU context. A task that - * uses the DPFPU hardware must call vPortTaskUsesDPFPU() before - * executing any floating point instructions. */ - pxTopOfStack--; - *pxTopOfStack = portNO_DPFPU_CONTEXT; - } + { + /* The task will start without a DPFPU context. A task that + * uses the DPFPU hardware must call vPortTaskUsesDPFPU() before + * executing any floating point instructions. */ + pxTopOfStack--; + *pxTopOfStack = portNO_DPFPU_CONTEXT; + } #elif ( configUSE_TASK_DPFPU_SUPPORT == 2 ) + { + /* The task will start with a DPFPU context. Leave enough + * space for the registers - and ensure they are initialised if desired. */ + #ifdef USE_FULL_REGISTER_INITIALISATION { - /* The task will start with a DPFPU context. Leave enough - * space for the registers - and ensure they are initialised if desired. */ - #ifdef USE_FULL_REGISTER_INITIALISATION - { - pxTopOfStack -= 2; - *(double *)pxTopOfStack = 1515.1515; /* DR15. */ - pxTopOfStack -= 2; - *(double *)pxTopOfStack = 1414.1414; /* DR14. */ - pxTopOfStack -= 2; - *(double *)pxTopOfStack = 1313.1313; /* DR13. */ - pxTopOfStack -= 2; - *(double *)pxTopOfStack = 1212.1212; /* DR12. */ - pxTopOfStack -= 2; - *(double *)pxTopOfStack = 1111.1111; /* DR11. */ - pxTopOfStack -= 2; - *(double *)pxTopOfStack = 1010.1010; /* DR10. */ - pxTopOfStack -= 2; - *(double *)pxTopOfStack = 909.0909; /* DR9. */ - pxTopOfStack -= 2; - *(double *)pxTopOfStack = 808.0808; /* DR8. */ - pxTopOfStack -= 2; - *(double *)pxTopOfStack = 707.0707; /* DR7. */ - pxTopOfStack -= 2; - *(double *)pxTopOfStack = 606.0606; /* DR6. */ - pxTopOfStack -= 2; - *(double *)pxTopOfStack = 505.0505; /* DR5. */ - pxTopOfStack -= 2; - *(double *)pxTopOfStack = 404.0404; /* DR4. */ - pxTopOfStack -= 2; - *(double *)pxTopOfStack = 303.0303; /* DR3. */ - pxTopOfStack -= 2; - *(double *)pxTopOfStack = 202.0202; /* DR2. */ - pxTopOfStack -= 2; - *(double *)pxTopOfStack = 101.0101; /* DR1. */ - pxTopOfStack -= 2; - *(double *)pxTopOfStack = 9876.54321;/* DR0. */ - } - #else /* ifdef USE_FULL_REGISTER_INITIALISATION */ - { - pxTopOfStack -= portDPFPU_DATA_REGISTER_WORDS; - memset( pxTopOfStack, 0x00, portDPFPU_DATA_REGISTER_WORDS * sizeof( StackType_t ) ); - } - #endif /* ifdef USE_FULL_REGISTER_INITIALISATION */ - pxTopOfStack--; - *pxTopOfStack = portINITIAL_DECNT; /* DECNT. */ - pxTopOfStack--; - *pxTopOfStack = portINITIAL_DCMR; /* DCMR. */ - pxTopOfStack--; - *pxTopOfStack = portINITIAL_DPSW; /* DPSW. */ + pxTopOfStack -= 2; + *( double * ) pxTopOfStack = 1515.1515; /* DR15. */ + pxTopOfStack -= 2; + *( double * ) pxTopOfStack = 1414.1414; /* DR14. */ + pxTopOfStack -= 2; + *( double * ) pxTopOfStack = 1313.1313; /* DR13. */ + pxTopOfStack -= 2; + *( double * ) pxTopOfStack = 1212.1212; /* DR12. */ + pxTopOfStack -= 2; + *( double * ) pxTopOfStack = 1111.1111; /* DR11. */ + pxTopOfStack -= 2; + *( double * ) pxTopOfStack = 1010.1010; /* DR10. */ + pxTopOfStack -= 2; + *( double * ) pxTopOfStack = 909.0909; /* DR9. */ + pxTopOfStack -= 2; + *( double * ) pxTopOfStack = 808.0808; /* DR8. */ + pxTopOfStack -= 2; + *( double * ) pxTopOfStack = 707.0707; /* DR7. */ + pxTopOfStack -= 2; + *( double * ) pxTopOfStack = 606.0606; /* DR6. */ + pxTopOfStack -= 2; + *( double * ) pxTopOfStack = 505.0505; /* DR5. */ + pxTopOfStack -= 2; + *( double * ) pxTopOfStack = 404.0404; /* DR4. */ + pxTopOfStack -= 2; + *( double * ) pxTopOfStack = 303.0303; /* DR3. */ + pxTopOfStack -= 2; + *( double * ) pxTopOfStack = 202.0202; /* DR2. */ + pxTopOfStack -= 2; + *( double * ) pxTopOfStack = 101.0101; /* DR1. */ + pxTopOfStack -= 2; + *( double * ) pxTopOfStack = 9876.54321; /* DR0. */ } - #elif ( configUSE_TASK_DPFPU_SUPPORT == 0 ) + #else /* ifdef USE_FULL_REGISTER_INITIALISATION */ { - /* Omit DPFPU support. */ + pxTopOfStack -= portDPFPU_DATA_REGISTER_WORDS; + memset( pxTopOfStack, 0x00, portDPFPU_DATA_REGISTER_WORDS * sizeof( StackType_t ) ); } + #endif /* ifdef USE_FULL_REGISTER_INITIALISATION */ + pxTopOfStack--; + *pxTopOfStack = portINITIAL_DECNT; /* DECNT. */ + pxTopOfStack--; + *pxTopOfStack = portINITIAL_DCMR; /* DCMR. */ + pxTopOfStack--; + *pxTopOfStack = portINITIAL_DPSW; /* DPSW. */ + } + #elif ( configUSE_TASK_DPFPU_SUPPORT == 0 ) + { + /* Omit DPFPU support. */ + } #else /* if ( configUSE_TASK_DPFPU_SUPPORT == 1 ) */ - { - #error Invalid configUSE_TASK_DPFPU_SUPPORT setting - configUSE_TASK_DPFPU_SUPPORT must be set to 0, 1, 2, or left undefined. - } + { + #error Invalid configUSE_TASK_DPFPU_SUPPORT setting - configUSE_TASK_DPFPU_SUPPORT must be set to 0, 1, 2, or left undefined. + } #endif /* if ( configUSE_TASK_DPFPU_SUPPORT == 1 ) */ return pxTopOfStack; @@ -316,14 +316,14 @@ static void prvStartFirstTask( void ) /* When starting the scheduler there is nothing that needs moving to the * interrupt stack because the function is not called from an interrupt. * Just ensure the current stack is the user stack. */ - "SETPSW U \n"\ + "SETPSW U \n" \ /* Obtain the location of the stack associated with which ever task * pxCurrentTCB is currently pointing to. */ - "MOV.L #_pxCurrentTCB, R15 \n"\ - "MOV.L [R15], R15 \n"\ - "MOV.L [R15], R0 \n"\ + "MOV.L #_pxCurrentTCB, R15 \n" \ + "MOV.L [R15], R15 \n" \ + "MOV.L [R15], R0 \n" \ /* Restore the registers from the stack of the task pointed to by @@ -333,53 +333,52 @@ static void prvStartFirstTask( void ) /* The restored ulPortTaskHasDPFPUContext is to be zero here. * So, it is never necessary to restore the DPFPU context here. */ - "POP R15 \n"\ - "MOV.L #_ulPortTaskHasDPFPUContext, R14 \n"\ - "MOV.L R15, [R14] \n"\ + "POP R15 \n" \ + "MOV.L #_ulPortTaskHasDPFPUContext, R14 \n" \ + "MOV.L R15, [R14] \n" \ #elif ( configUSE_TASK_DPFPU_SUPPORT == 2 ) - /* Restore the DPFPU context. */ - "DPOPM.L DPSW-DECNT \n"\ - "DPOPM.D DR0-DR15 \n"\ + "DPOPM.L DPSW-DECNT \n" \ + "DPOPM.D DR0-DR15 \n" \ #endif /* if ( configUSE_TASK_DPFPU_SUPPORT == 1 ) */ - "POP R15 \n"\ + "POP R15 \n" \ /* Accumulator low 32 bits. */ - "MVTACLO R15, A0 \n"\ - "POP R15 \n"\ + "MVTACLO R15, A0 \n" \ + "POP R15 \n" \ /* Accumulator high 32 bits. */ - "MVTACHI R15, A0 \n"\ - "POP R15 \n"\ + "MVTACHI R15, A0 \n" \ + "POP R15 \n" \ /* Accumulator guard. */ - "MVTACGU R15, A0 \n"\ - "POP R15 \n"\ + "MVTACGU R15, A0 \n" \ + "POP R15 \n" \ /* Accumulator low 32 bits. */ - "MVTACLO R15, A1 \n"\ - "POP R15 \n"\ + "MVTACLO R15, A1 \n" \ + "POP R15 \n" \ /* Accumulator high 32 bits. */ - "MVTACHI R15, A1 \n"\ - "POP R15 \n"\ + "MVTACHI R15, A1 \n" \ + "POP R15 \n" \ /* Accumulator guard. */ - "MVTACGU R15, A1 \n"\ - "POP R15 \n"\ + "MVTACGU R15, A1 \n" \ + "POP R15 \n" \ /* Floating point status word. */ - "MVTC R15, FPSW \n"\ + "MVTC R15, FPSW \n" \ /* R1 to R15 - R0 is not included as it is the SP. */ - "POPM R1-R15 \n"\ + "POPM R1-R15 \n" \ /* This pops the remaining registers. */ - "RTE \n"\ - "NOP \n"\ + "RTE \n" \ + "NOP \n" \ "NOP \n" ); } @@ -391,100 +390,99 @@ __interrupt void vSoftwareInterruptISR( void ) __asm volatile ( /* Re-enable interrupts. */ - "SETPSW I \n"\ + "SETPSW I \n" \ /* Move the data that was automatically pushed onto the interrupt stack when * the interrupt occurred from the interrupt stack to the user stack. * * R15 is saved before it is clobbered. */ - "PUSH.L R15 \n"\ + "PUSH.L R15 \n" \ /* Read the user stack pointer. */ - "MVFC USP, R15 \n"\ + "MVFC USP, R15 \n" \ /* Move the address down to the data being moved. */ - "SUB #12, R15 \n"\ - "MVTC R15, USP \n"\ + "SUB #12, R15 \n" \ + "MVTC R15, USP \n" \ /* Copy the data across, R15, then PC, then PSW. */ - "MOV.L [ R0 ], [ R15 ] \n"\ - "MOV.L 4[ R0 ], 4[ R15 ] \n"\ - "MOV.L 8[ R0 ], 8[ R15 ] \n"\ + "MOV.L [ R0 ], [ R15 ] \n" \ + "MOV.L 4[ R0 ], 4[ R15 ] \n" \ + "MOV.L 8[ R0 ], 8[ R15 ] \n" \ /* Move the interrupt stack pointer to its new correct position. */ - "ADD #12, R0 \n"\ + "ADD #12, R0 \n" \ /* All the rest of the registers are saved directly to the user stack. */ - "SETPSW U \n"\ + "SETPSW U \n" \ /* Save the rest of the general registers (R15 has been saved already). */ - "PUSHM R1-R14 \n"\ + "PUSHM R1-R14 \n" \ /* Save the FPSW and accumulators. */ - "MVFC FPSW, R15 \n"\ - "PUSH.L R15 \n"\ - "MVFACGU #0, A1, R15 \n"\ - "PUSH.L R15 \n"\ - "MVFACHI #0, A1, R15 \n"\ - "PUSH.L R15 \n"\ + "MVFC FPSW, R15 \n" \ + "PUSH.L R15 \n" \ + "MVFACGU #0, A1, R15 \n" \ + "PUSH.L R15 \n" \ + "MVFACHI #0, A1, R15 \n" \ + "PUSH.L R15 \n" \ "MVFACLO #0, A1, R15 \n" /* Low order word. */ \ - "PUSH.L R15 \n"\ - "MVFACGU #0, A0, R15 \n"\ - "PUSH.L R15 \n"\ - "MVFACHI #0, A0, R15 \n"\ - "PUSH.L R15 \n"\ + "PUSH.L R15 \n" \ + "MVFACGU #0, A0, R15 \n" \ + "PUSH.L R15 \n" \ + "MVFACHI #0, A0, R15 \n" \ + "PUSH.L R15 \n" \ "MVFACLO #0, A0, R15 \n" /* Low order word. */ \ - "PUSH.L R15 \n"\ + "PUSH.L R15 \n" \ #if ( configUSE_TASK_DPFPU_SUPPORT == 1 ) /* Does the task have a DPFPU context that needs saving? If * ulPortTaskHasDPFPUContext is 0 then no. */ - "MOV.L #_ulPortTaskHasDPFPUContext, R15 \n"\ - "MOV.L [R15], R15 \n"\ - "CMP #0, R15 \n"\ + "MOV.L #_ulPortTaskHasDPFPUContext, R15 \n" \ + "MOV.L [R15], R15 \n" \ + "CMP #0, R15 \n" \ /* Save the DPFPU context, if any. */ - "BEQ.B __lab1 \n"\ - "DPUSHM.D DR0-DR15 \n"\ - "DPUSHM.L DPSW-DECNT \n"\ - "__lab1: \n"\ + "BEQ.B __lab1 \n" \ + "DPUSHM.D DR0-DR15 \n" \ + "DPUSHM.L DPSW-DECNT \n" \ + "__lab1: \n" \ /* Save ulPortTaskHasDPFPUContext itself. */ - "PUSH.L R15 \n"\ + "PUSH.L R15 \n" \ #elif ( configUSE_TASK_DPFPU_SUPPORT == 2 ) - /* Save the DPFPU context, always. */ - "DPUSHM.D DR0-DR15 \n"\ - "DPUSHM.L DPSW-DECNT \n"\ + "DPUSHM.D DR0-DR15 \n" \ + "DPUSHM.L DPSW-DECNT \n" \ #endif /* if ( configUSE_TASK_DPFPU_SUPPORT == 1 ) */ /* Save the stack pointer to the TCB. */ - "MOV.L #_pxCurrentTCB, R15 \n"\ - "MOV.L [ R15 ], R15 \n"\ - "MOV.L R0, [ R15 ] \n"\ + "MOV.L #_pxCurrentTCB, R15 \n" \ + "MOV.L [ R15 ], R15 \n" \ + "MOV.L R0, [ R15 ] \n" \ /* Ensure the interrupt mask is set to the syscall priority while the kernel * structures are being accessed. */ - "MVTIPL %0 \n"\ + "MVTIPL %0 \n" \ /* Select the next task to run. */ - "BSR.A _vTaskSwitchContext \n"\ + "BSR.A _vTaskSwitchContext \n" \ /* Reset the interrupt mask as no more data structure access is required. */ - "MVTIPL %1 \n"\ + "MVTIPL %1 \n" \ /* Load the stack pointer of the task that is now selected as the Running * state task from its TCB. */ - "MOV.L #_pxCurrentTCB,R15 \n"\ - "MOV.L [ R15 ], R15 \n"\ - "MOV.L [ R15 ], R0 \n"\ + "MOV.L #_pxCurrentTCB,R15 \n" \ + "MOV.L [ R15 ], R15 \n" \ + "MOV.L [ R15 ], R0 \n" \ /* Restore the context of the new task. The PSW (Program Status Word) and @@ -494,56 +492,55 @@ __interrupt void vSoftwareInterruptISR( void ) /* Is there a DPFPU context to restore? If the restored * ulPortTaskHasDPFPUContext is zero then no. */ - "POP R15 \n"\ - "MOV.L #_ulPortTaskHasDPFPUContext, R14 \n"\ - "MOV.L R15, [R14] \n"\ - "CMP #0, R15 \n"\ + "POP R15 \n" \ + "MOV.L #_ulPortTaskHasDPFPUContext, R14 \n" \ + "MOV.L R15, [R14] \n" \ + "CMP #0, R15 \n" \ /* Restore the DPFPU context, if any. */ - "BEQ.B __lab2 \n"\ - "DPOPM.L DPSW-DECNT \n"\ - "DPOPM.D DR0-DR15 \n"\ - "__lab2: \n"\ + "BEQ.B __lab2 \n" \ + "DPOPM.L DPSW-DECNT \n" \ + "DPOPM.D DR0-DR15 \n" \ + "__lab2: \n" \ #elif ( configUSE_TASK_DPFPU_SUPPORT == 2 ) - /* Restore the DPFPU context, always. */ - "DPOPM.L DPSW-DECNT \n"\ - "DPOPM.D DR0-DR15 \n"\ + "DPOPM.L DPSW-DECNT \n" \ + "DPOPM.D DR0-DR15 \n" \ #endif /* if( configUSE_TASK_DPFPU_SUPPORT == 1 ) */ - "POP R15 \n"\ + "POP R15 \n" \ /* Accumulator low 32 bits. */ - "MVTACLO R15, A0 \n"\ - "POP R15 \n"\ + "MVTACLO R15, A0 \n" \ + "POP R15 \n" \ /* Accumulator high 32 bits. */ - "MVTACHI R15, A0 \n"\ - "POP R15 \n"\ + "MVTACHI R15, A0 \n" \ + "POP R15 \n" \ /* Accumulator guard. */ - "MVTACGU R15, A0 \n"\ - "POP R15 \n"\ + "MVTACGU R15, A0 \n" \ + "POP R15 \n" \ /* Accumulator low 32 bits. */ - "MVTACLO R15, A1 \n"\ - "POP R15 \n"\ + "MVTACLO R15, A1 \n" \ + "POP R15 \n" \ /* Accumulator high 32 bits. */ - "MVTACHI R15, A1 \n"\ - "POP R15 \n"\ + "MVTACHI R15, A1 \n" \ + "POP R15 \n" \ /* Accumulator guard. */ - "MVTACGU R15, A1 \n"\ - "POP R15 \n"\ - "MVTC R15, FPSW \n"\ - "POPM R1-R15 \n"\ - "RTE \n"\ - "NOP \n"\ + "MVTACGU R15, A1 \n" \ + "POP R15 \n" \ + "MVTC R15, FPSW \n" \ + "POPM R1-R15 \n" \ + "RTE \n" \ + "NOP \n" \ "NOP " - portCDT_NO_PARSE( :: ) "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ), "i" ( configKERNEL_INTERRUPT_PRIORITY ) + portCDT_NO_PARSE( ::) "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ), "i" ( configKERNEL_INTERRUPT_PRIORITY ) ); } /*-----------------------------------------------------------*/ diff --git a/Source/portable/IAR/RX700v3_DPFPU/portmacro.h b/Source/portable/IAR/RX700v3_DPFPU/portmacro.h index 5cb3de128..1af637636 100644 --- a/Source/portable/IAR/RX700v3_DPFPU/portmacro.h +++ b/Source/portable/IAR/RX700v3_DPFPU/portmacro.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -28,10 +28,10 @@ #ifndef PORTMACRO_H - #define PORTMACRO_H +#define PORTMACRO_H /* Hardware specifics. */ - #include +#include /* *INDENT-OFF* */ #ifdef __cplusplus @@ -51,9 +51,9 @@ /* When the FIT configurator or the Smart Configurator is used, platform.h has to be * used. */ - #ifndef configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H - #define configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H 0 - #endif +#ifndef configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H + #define configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H 0 +#endif /* If configUSE_TASK_DPFPU_SUPPORT is set to 1 (or undefined) then each task will * be created without a DPFPU context, and a task must call vTaskUsesDPFPU() before @@ -61,77 +61,77 @@ * tasks are created with a DPFPU context by default, and calling vTaskUsesDPFPU() has * no effect. If configUSE_TASK_DPFPU_SUPPORT is set to 0 then tasks never take care * of any DPFPU context (even if DPFPU registers are used). */ - #ifndef configUSE_TASK_DPFPU_SUPPORT - #define configUSE_TASK_DPFPU_SUPPORT 1 - #endif +#ifndef configUSE_TASK_DPFPU_SUPPORT + #define configUSE_TASK_DPFPU_SUPPORT 1 +#endif /*-----------------------------------------------------------*/ /* Type definitions - these are a bit legacy and not really used now, other than * portSTACK_TYPE and portBASE_TYPE. */ - #define portCHAR char - #define portFLOAT float - #define portDOUBLE double - #define portLONG long - #define portSHORT short - #define portSTACK_TYPE uint32_t - #define portBASE_TYPE long - - typedef portSTACK_TYPE StackType_t; - typedef long BaseType_t; - typedef unsigned long UBaseType_t; - - #if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS ) - typedef uint16_t TickType_t; - #define portMAX_DELAY ( TickType_t ) 0xffff - #elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS ) - typedef uint32_t TickType_t; - #define portMAX_DELAY ( TickType_t ) 0xffffffffUL +#define portCHAR char +#define portFLOAT float +#define portDOUBLE double +#define portLONG long +#define portSHORT short +#define portSTACK_TYPE uint32_t +#define portBASE_TYPE long + +typedef portSTACK_TYPE StackType_t; +typedef long BaseType_t; +typedef unsigned long UBaseType_t; + +#if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS ) + typedef uint16_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffff +#elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS ) + typedef uint32_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffffffffUL /* 32-bit tick type on a 32-bit architecture, so reads of the tick count do * not need to be guarded with a critical section. */ - #define portTICK_TYPE_IS_ATOMIC 1 - #else - #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width. - #endif + #define portTICK_TYPE_IS_ATOMIC 1 +#else + #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width. +#endif /*-----------------------------------------------------------*/ /* Hardware specifics. */ - #define portBYTE_ALIGNMENT 8 /* Could make four, according to manual. */ - #define portSTACK_GROWTH -1 - #define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) - #define portNOP() __no_operation() +#define portBYTE_ALIGNMENT 8 /* Could make four, according to manual. */ +#define portSTACK_GROWTH -1 +#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) +#define portNOP() __no_operation() /* Yield equivalent to "*portITU_SWINTR = 0x01; ( void ) *portITU_SWINTR;" * where portITU_SWINTR is the location of the software interrupt register * (0x000872E0). Don't rely on the assembler to select a register, so instead * save and restore clobbered registers manually. */ - #define portYIELD() \ - __asm volatile \ - ( \ - "PUSH.L R10 \n"\ - "MOV.L #0x872E0, R10 \n"\ - "MOV.B #0x1, [R10] \n"\ - "CMP [R10].UB, R10 \n"\ - "POP R10 \n"\ - portCDT_NO_PARSE( ::: ) "cc"\ +#define portYIELD() \ + __asm volatile \ + ( \ + "PUSH.L R10 \n" \ + "MOV.L #0x872E0, R10 \n" \ + "MOV.B #0x1, [R10] \n" \ + "CMP [R10].UB, R10 \n" \ + "POP R10 \n" \ + portCDT_NO_PARSE( ::: ) "cc" \ ) - #define portYIELD_FROM_ISR( x ) do { if( ( x ) != pdFALSE ) portYIELD(); } while( 0 ) +#define portYIELD_FROM_ISR( x ) do { if( ( x ) != pdFALSE ) portYIELD( ); } while( 0 ) /* Workaround to reduce errors/warnings caused by e2 studio CDT's INDEXER and CODAN. */ - #ifdef __CDT_PARSER__ +#ifdef __CDT_PARSER__ #ifndef __asm - #define __asm asm + #define __asm asm #endif #ifndef __attribute__ - #define __attribute__( ... ) + #define __attribute__( ... ) #endif #define portCDT_NO_PARSE( token ) - #else - #define portCDT_NO_PARSE( token ) token - #endif +#else + #define portCDT_NO_PARSE( token ) token +#endif /* These macros should not be called directly, but through the * taskENTER_CRITICAL() and taskEXIT_CRITICAL() macros. An extra check is @@ -142,32 +142,32 @@ * functions are those that end in FromISR. FreeRTOS maintains a separate * interrupt API to ensure API function and interrupt entry is as fast and as * simple as possible. */ - #define portENABLE_INTERRUPTS() __set_interrupt_level( ( uint8_t ) 0 ) - #ifdef configASSERT - #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() configASSERT( ( __get_interrupt_level() <= configMAX_SYSCALL_INTERRUPT_PRIORITY ) ) - #define portDISABLE_INTERRUPTS() if( __get_interrupt_level() < configMAX_SYSCALL_INTERRUPT_PRIORITY ) __set_interrupt_level( ( uint8_t ) configMAX_SYSCALL_INTERRUPT_PRIORITY ) - #else - #define portDISABLE_INTERRUPTS() __set_interrupt_level( ( uint8_t ) configMAX_SYSCALL_INTERRUPT_PRIORITY ) - #endif +#define portENABLE_INTERRUPTS() __set_interrupt_level( ( uint8_t ) 0 ) +#ifdef configASSERT + #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() configASSERT( ( __get_interrupt_level() <= configMAX_SYSCALL_INTERRUPT_PRIORITY ) ) + #define portDISABLE_INTERRUPTS() if( __get_interrupt_level() < configMAX_SYSCALL_INTERRUPT_PRIORITY ) __set_interrupt_level( ( uint8_t ) configMAX_SYSCALL_INTERRUPT_PRIORITY ) +#else + #define portDISABLE_INTERRUPTS() __set_interrupt_level( ( uint8_t ) configMAX_SYSCALL_INTERRUPT_PRIORITY ) +#endif /* Critical nesting counts are stored in the TCB. */ - #define portCRITICAL_NESTING_IN_TCB ( 1 ) +#define portCRITICAL_NESTING_IN_TCB ( 1 ) /* The critical nesting functions defined within tasks.c. */ - extern void vTaskEnterCritical( void ); - extern void vTaskExitCritical( void ); - #define portENTER_CRITICAL() vTaskEnterCritical() - #define portEXIT_CRITICAL() vTaskExitCritical() +extern void vTaskEnterCritical( void ); +extern void vTaskExitCritical( void ); +#define portENTER_CRITICAL() vTaskEnterCritical() +#define portEXIT_CRITICAL() vTaskExitCritical() /* As this port allows interrupt nesting... */ - #define portSET_INTERRUPT_MASK_FROM_ISR() __get_interrupt_level(); portDISABLE_INTERRUPTS() - #define portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus ) __set_interrupt_level( ( uint8_t ) ( uxSavedInterruptStatus ) ) +#define portSET_INTERRUPT_MASK_FROM_ISR() __get_interrupt_level(); portDISABLE_INTERRUPTS() +#define portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus ) __set_interrupt_level( ( uint8_t ) ( uxSavedInterruptStatus ) ) /*-----------------------------------------------------------*/ /* Task function macros as described on the FreeRTOS.org WEB site. */ - #define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters ) - #define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters ) +#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters ) +#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters ) /*-----------------------------------------------------------*/ @@ -176,22 +176,23 @@ * themselves a DPFPU context before using any DPFPU instructions. If * configUSE_TASK_DPFPU_SUPPORT is set to 2 then all tasks will have a DPFPU context * by default. */ - #if( configUSE_TASK_DPFPU_SUPPORT == 1 ) - void vPortTaskUsesDPFPU( void ); - #else +#if ( configUSE_TASK_DPFPU_SUPPORT == 1 ) + void vPortTaskUsesDPFPU( void ); +#else + /* Each task has a DPFPU context already, so define this function away to * nothing to prevent it being called accidentally. */ - #define vPortTaskUsesDPFPU() - #endif - #define portTASK_USES_DPFPU() vPortTaskUsesDPFPU() + #define vPortTaskUsesDPFPU() +#endif +#define portTASK_USES_DPFPU() vPortTaskUsesDPFPU() /* Definition to allow compatibility with existing FreeRTOS Demo using flop.c. */ - #define portTASK_USES_FLOATING_POINT() vPortTaskUsesDPFPU() +#define portTASK_USES_FLOATING_POINT() vPortTaskUsesDPFPU() /* Prevent warnings of undefined behaviour: the order of volatile accesses is * undefined - all warnings have been manually checked and are not an issue, and * the warnings cannot be prevent by code changes without undesirable effects. */ - #pragma diag_suppress=Pa082 +#pragma diag_suppress=Pa082 /* *INDENT-OFF* */ #ifdef __cplusplus diff --git a/Source/portable/IAR/RXv2/port.c b/Source/portable/IAR/RXv2/port.c index 1599c8bef..5c0575135 100644 --- a/Source/portable/IAR/RXv2/port.c +++ b/Source/portable/IAR/RXv2/port.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -27,8 +27,8 @@ */ /*----------------------------------------------------------- - * Implementation of functions defined in portable.h for the SH2A port. - *----------------------------------------------------------*/ +* Implementation of functions defined in portable.h for the SH2A port. +*----------------------------------------------------------*/ /* Scheduler includes. */ #include "FreeRTOS.h" @@ -43,8 +43,8 @@ /*-----------------------------------------------------------*/ /* Tasks should start with interrupts enabled and in Supervisor mode, therefore -PSW is set with U and I set, and PM and IPL clear. */ -#define portINITIAL_PSW ( ( StackType_t ) 0x00030000 ) + * PSW is set with U and I set, and PM and IPL clear. */ +#define portINITIAL_PSW ( ( StackType_t ) 0x00030000 ) #define portINITIAL_FPSW ( ( StackType_t ) 0x00000100 ) /*-----------------------------------------------------------*/ @@ -63,14 +63,16 @@ __interrupt void vTickISR( void ); /*-----------------------------------------------------------*/ -extern void *pxCurrentTCB; +extern void * pxCurrentTCB; /*-----------------------------------------------------------*/ /* * See header file for description. */ -StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters ) +StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, + TaskFunction_t pxCode, + void * pvParameters ) { /* R0 is not included as it is the stack pointer. */ @@ -81,8 +83,8 @@ StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t px *pxTopOfStack = ( StackType_t ) pxCode; /* When debugging it can be useful if every register is set to a known - value. Otherwise code space can be saved by just setting the registers - that need to be set. */ + * value. Otherwise code space can be saved by just setting the registers + * that need to be set. */ #ifdef USE_FULL_REGISTER_INITIALISATION { pxTopOfStack--; @@ -115,11 +117,11 @@ StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t px *pxTopOfStack = 0x22222222; pxTopOfStack--; } - #else + #else /* ifdef USE_FULL_REGISTER_INITIALISATION */ { pxTopOfStack -= 15; } - #endif + #endif /* ifdef USE_FULL_REGISTER_INITIALISATION */ *pxTopOfStack = ( StackType_t ) pvParameters; /* R1 */ pxTopOfStack--; @@ -143,14 +145,14 @@ StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t px BaseType_t xPortStartScheduler( void ) { -extern void vApplicationSetupTimerInterrupt( void ); + extern void vApplicationSetupTimerInterrupt( void ); /* Use pxCurrentTCB just so it does not get optimised away. */ if( pxCurrentTCB != NULL ) { /* Call an application function to set up the timer that will generate the - tick interrupt. This way the application can decide which peripheral to - use. A demo application is provided to show a suitable example. */ + * tick interrupt. This way the application can decide which peripheral to + * use. A demo application is provided to show a suitable example. */ vApplicationSetupTimerInterrupt(); /* Enable the software interrupt. */ @@ -178,7 +180,7 @@ __interrupt void vTickISR( void ) __enable_interrupt(); /* Increment the tick, and perform any processing the new tick value - necessitates. */ + * necessitates. */ __set_interrupt_level( configMAX_SYSCALL_INTERRUPT_PRIORITY ); { if( xTaskIncrementTick() != pdFALSE ) @@ -193,7 +195,7 @@ __interrupt void vTickISR( void ) void vPortEndScheduler( void ) { /* Not implemented in ports where there is nothing to return to. - Artificially force an assert. */ + * Artificially force an assert. */ configASSERT( pxCurrentTCB == NULL ); } /*-----------------------------------------------------------*/ diff --git a/Source/portable/IAR/RXv2/port_asm.s b/Source/portable/IAR/RXv2/port_asm.s index 6c7b6e16e..9bba5c92c 100644 --- a/Source/portable/IAR/RXv2/port_asm.s +++ b/Source/portable/IAR/RXv2/port_asm.s @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/Source/portable/IAR/RXv2/portmacro.h b/Source/portable/IAR/RXv2/portmacro.h index d9d02233a..c5b3933b3 100644 --- a/Source/portable/IAR/RXv2/portmacro.h +++ b/Source/portable/IAR/RXv2/portmacro.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -49,96 +49,96 @@ */ /* Type definitions - these are a bit legacy and not really used now, other than -portSTACK_TYPE and portBASE_TYPE. */ -#define portCHAR char -#define portFLOAT float -#define portDOUBLE double -#define portLONG long -#define portSHORT short -#define portSTACK_TYPE uint32_t -#define portBASE_TYPE long - -typedef portSTACK_TYPE StackType_t; -typedef long BaseType_t; -typedef unsigned long UBaseType_t; - - -#if( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS ) - typedef uint16_t TickType_t; - #define portMAX_DELAY ( TickType_t ) 0xffff + * portSTACK_TYPE and portBASE_TYPE. */ +#define portCHAR char +#define portFLOAT float +#define portDOUBLE double +#define portLONG long +#define portSHORT short +#define portSTACK_TYPE uint32_t +#define portBASE_TYPE long + +typedef portSTACK_TYPE StackType_t; +typedef long BaseType_t; +typedef unsigned long UBaseType_t; + + +#if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS ) + typedef uint16_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffff #elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS ) - typedef uint32_t TickType_t; - #define portMAX_DELAY ( TickType_t ) 0xffffffffUL + typedef uint32_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffffffffUL - /* 32-bit tick type on a 32-bit architecture, so reads of the tick count do - not need to be guarded with a critical section. */ - #define portTICK_TYPE_IS_ATOMIC 1 +/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do + * not need to be guarded with a critical section. */ + #define portTICK_TYPE_IS_ATOMIC 1 #else #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width. #endif /*-----------------------------------------------------------*/ /* Hardware specifics. */ -#define portBYTE_ALIGNMENT 8 /* Could make four, according to manual. */ -#define portSTACK_GROWTH -1 -#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) -#define portNOP() __no_operation() +#define portBYTE_ALIGNMENT 8 /* Could make four, according to manual. */ +#define portSTACK_GROWTH -1 +#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) +#define portNOP() __no_operation() /* Yield equivalent to "*portITU_SWINTR = 0x01; ( void ) *portITU_SWINTR;" -where portITU_SWINTR is the location of the software interrupt register -(0x000872E0). Don't rely on the assembler to select a register, so instead -save and restore clobbered registers manually. */ -#define portYIELD() \ - __asm volatile \ - ( \ - "PUSH.L R10 \n" \ - "MOV.L #0x872E0, R10 \n" \ - "MOV.B #0x1, [R10] \n" \ - "MOV.L [R10], R10 \n" \ - "POP R10 \n" \ + * where portITU_SWINTR is the location of the software interrupt register + * (0x000872E0). Don't rely on the assembler to select a register, so instead + * save and restore clobbered registers manually. */ +#define portYIELD() \ + __asm volatile \ + ( \ + "PUSH.L R10 \n" \ + "MOV.L #0x872E0, R10 \n" \ + "MOV.B #0x1, [R10] \n" \ + "MOV.L [R10], R10 \n" \ + "POP R10 \n" \ ) -#define portYIELD_FROM_ISR( x ) do { if( ( x ) != pdFALSE ) portYIELD(); } while( 0 ) +#define portYIELD_FROM_ISR( x ) do { if( ( x ) != pdFALSE ) portYIELD( ); } while( 0 ) /* These macros should not be called directly, but through the -taskENTER_CRITICAL() and taskEXIT_CRITICAL() macros. An extra check is -performed if configASSERT() is defined to ensure an assertion handler does not -inadvertently attempt to lower the IPL when the call to assert was triggered -because the IPL value was found to be above configMAX_SYSCALL_INTERRUPT_PRIORITY -when an ISR safe FreeRTOS API function was executed. ISR safe FreeRTOS API -functions are those that end in FromISR. FreeRTOS maintains a separate -interrupt API to ensure API function and interrupt entry is as fast and as -simple as possible. */ -#define portENABLE_INTERRUPTS() __set_interrupt_level( ( uint8_t ) 0 ) + * taskENTER_CRITICAL() and taskEXIT_CRITICAL() macros. An extra check is + * performed if configASSERT() is defined to ensure an assertion handler does not + * inadvertently attempt to lower the IPL when the call to assert was triggered + * because the IPL value was found to be above configMAX_SYSCALL_INTERRUPT_PRIORITY + * when an ISR safe FreeRTOS API function was executed. ISR safe FreeRTOS API + * functions are those that end in FromISR. FreeRTOS maintains a separate + * interrupt API to ensure API function and interrupt entry is as fast and as + * simple as possible. */ +#define portENABLE_INTERRUPTS() __set_interrupt_level( ( uint8_t ) 0 ) #ifdef configASSERT - #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() configASSERT( ( __get_interrupt_level() <= configMAX_SYSCALL_INTERRUPT_PRIORITY ) ) - #define portDISABLE_INTERRUPTS() if( __get_interrupt_level() < configMAX_SYSCALL_INTERRUPT_PRIORITY ) __set_interrupt_level( ( uint8_t ) configMAX_SYSCALL_INTERRUPT_PRIORITY ) + #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() configASSERT( ( __get_interrupt_level() <= configMAX_SYSCALL_INTERRUPT_PRIORITY ) ) + #define portDISABLE_INTERRUPTS() if( __get_interrupt_level() < configMAX_SYSCALL_INTERRUPT_PRIORITY ) __set_interrupt_level( ( uint8_t ) configMAX_SYSCALL_INTERRUPT_PRIORITY ) #else - #define portDISABLE_INTERRUPTS() __set_interrupt_level( ( uint8_t ) configMAX_SYSCALL_INTERRUPT_PRIORITY ) + #define portDISABLE_INTERRUPTS() __set_interrupt_level( ( uint8_t ) configMAX_SYSCALL_INTERRUPT_PRIORITY ) #endif /* Critical nesting counts are stored in the TCB. */ -#define portCRITICAL_NESTING_IN_TCB ( 1 ) +#define portCRITICAL_NESTING_IN_TCB ( 1 ) /* The critical nesting functions defined within tasks.c. */ extern void vTaskEnterCritical( void ); extern void vTaskExitCritical( void ); -#define portENTER_CRITICAL() vTaskEnterCritical() -#define portEXIT_CRITICAL() vTaskExitCritical() +#define portENTER_CRITICAL() vTaskEnterCritical() +#define portEXIT_CRITICAL() vTaskExitCritical() /* As this port allows interrupt nesting... */ -#define portSET_INTERRUPT_MASK_FROM_ISR() __get_interrupt_level(); portDISABLE_INTERRUPTS() -#define portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus ) __set_interrupt_level( ( uint8_t ) ( uxSavedInterruptStatus ) ) +#define portSET_INTERRUPT_MASK_FROM_ISR() __get_interrupt_level(); portDISABLE_INTERRUPTS() +#define portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus ) __set_interrupt_level( ( uint8_t ) ( uxSavedInterruptStatus ) ) /*-----------------------------------------------------------*/ /* Task function macros as described on the FreeRTOS.org WEB site. */ -#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters ) -#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters ) +#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters ) +#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters ) /* Prevent warnings of undefined behaviour: the order of volatile accesses is -undefined - all warnings have been manually checked and are not an issue, and -the warnings cannot be prevent by code changes without undesirable effects. */ + * undefined - all warnings have been manually checked and are not an issue, and + * the warnings cannot be prevent by code changes without undesirable effects. */ #pragma diag_suppress=Pa082 /* *INDENT-OFF* */ diff --git a/Source/portable/IAR/STR71x/ISR_Support.h b/Source/portable/IAR/STR71x/ISR_Support.h index f6b701a11..3aa820266 100644 --- a/Source/portable/IAR/STR71x/ISR_Support.h +++ b/Source/portable/IAR/STR71x/ISR_Support.h @@ -1,105 +1,151 @@ -;/* -; * FreeRTOS Kernel V10.6.2 -; * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. -; * -; * SPDX-License-Identifier: MIT -; * -; * Permission is hereby granted, free of charge, to any person obtaining a copy of -; * this software and associated documentation files (the "Software"), to deal in -; * the Software without restriction, including without limitation the rights to -; * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of -; * the Software, and to permit persons to whom the Software is furnished to do so, -; * subject to the following conditions: -; * -; * The above copyright notice and this permission notice shall be included in all -; * copies or substantial portions of the Software. -; * -; * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -; * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS -; * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR -; * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER -; * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN -; * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. -; * -; * https://www.FreeRTOS.org -; * https://github.com/FreeRTOS -; * -; */ - - EXTERN pxCurrentTCB - EXTERN ulCriticalNesting - -;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -; Context save and restore macro definitions -;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +; /* + * ; * FreeRTOS Kernel V11.0.1 + * ; * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * ; * + * ; * SPDX-License-Identifier: MIT + * ; * + * ; * Permission is hereby granted, free of charge, to any person obtaining a copy of + * ; * this software and associated documentation files (the "Software"), to deal in + * ; * the Software without restriction, including without limitation the rights to + * ; * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * ; * the Software, and to permit persons to whom the Software is furnished to do so, + * ; * subject to the following conditions: + * ; * + * ; * The above copyright notice and this permission notice shall be included in all + * ; * copies or substantial portions of the Software. + * ; * + * ; * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * ; * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * ; * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * ; * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * ; * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * ; * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * ; * + * ; * https://www.FreeRTOS.org + * ; * https://github.com/FreeRTOS + * ; * + * ; */ + +EXTERN pxCurrentTCB +EXTERN ulCriticalNesting + +; +Context save and restore macro definitions +; portSAVE_CONTEXT MACRO - ; Push R0 as we are going to use the register. - STMDB SP!, {R0} +; +Push R0 as we are going to use the register. + STMDB SP !, { + R0 +} + +Set R0 to point to the task stack pointer. + STMDB SP, { + SP +} +^ +NOP +SUB SP, SP, # 4 +LDMIA SP !, { + R0 +} + +; +Push the return address onto the stack. + STMDB R0 !, { + LR + } + + Now we have saved LR we can use it instead of R0. + MOV LR, R0 + +; + +Pop R0 so we can save it onto the system mode stack. + LDMIA SP !, { + R0 +} + +Push all the system mode registers onto the task stack. + STMDB LR, { + R0 - LR +} +^ +NOP +SUB LR, LR, # 60 + +; +Push the SPSR onto the task stack. + MRS R0, SPSR +STMDB LR !, { + R0 +} + +LDR R0, = ulCriticalNesting + LDR R0, [ R0 ] +STMDB LR !, { + R0 +} + +Store the new top of stack + +for the task. + LDR R1, = pxCurrentTCB + LDR R0, [ R1 ] +STR LR, [ R0 ] + +ENDM - ; Set R0 to point to the task stack pointer. - STMDB SP, {SP}^ - NOP - SUB SP, SP, #4 - LDMIA SP!, {R0} - ; Push the return address onto the stack. - STMDB R0!, {LR} - - ; Now we have saved LR we can use it instead of R0. - MOV LR, R0 - - ; Pop R0 so we can save it onto the system mode stack. - LDMIA SP!, {R0} - - ; Push all the system mode registers onto the task stack. - STMDB LR, {R0-LR}^ - NOP - SUB LR, LR, #60 - - ; Push the SPSR onto the task stack. - MRS R0, SPSR - STMDB LR!, {R0} +portRESTORE_CONTEXT MACRO - LDR R0, =ulCriticalNesting - LDR R0, [R0] - STMDB LR!, {R0} +; +Set the LR to the task stack. + LDR R1, = pxCurrentTCB + LDR R0, [ R1 ] +LDR LR, [ R0 ] - ; Store the new top of stack for the task. - LDR R1, =pxCurrentTCB - LDR R0, [R1] - STR LR, [R0] +; +The critical nesting depth is the first item on the stack. + ; +Load it into the ulCriticalNesting variable. + LDR R0, = ulCriticalNesting + LDMFD LR !, { + R1 +} - ENDM +STR R1, [ R0 ] +; +Get the SPSR from the stack. + LDMFD LR !, { + R0 +} +MSR SPSR_cxsf, R0 -portRESTORE_CONTEXT MACRO +; +Restore all system mode registers - ; Set the LR to the task stack. - LDR R1, =pxCurrentTCB - LDR R0, [R1] - LDR LR, [R0] +for the task. + LDMFD LR, { + R0 - R14 +} - ; The critical nesting depth is the first item on the stack. - ; Load it into the ulCriticalNesting variable. - LDR R0, =ulCriticalNesting - LDMFD LR!, {R1} - STR R1, [R0] +^ +NOP - ; Get the SPSR from the stack. - LDMFD LR!, {R0} - MSR SPSR_cxsf, R0 +; +Restore the return address. + LDR LR, [ LR, # + 60 ] - ; Restore all system mode registers for the task. - LDMFD LR, {R0-R14}^ - NOP +; - ; Restore the return address. - LDR LR, [LR, #+60] +And return -correcting the offset in the LR to obtain the +; - ; And return - correcting the offset in the LR to obtain the - ; correct address. - SUBS PC, LR, #4 +correct address. + SUBS PC, LR, # 4 - ENDM +ENDM diff --git a/Source/portable/IAR/STR71x/port.c b/Source/portable/IAR/STR71x/port.c index 4496b7dfd..c99f293bd 100644 --- a/Source/portable/IAR/STR71x/port.c +++ b/Source/portable/IAR/STR71x/port.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -27,9 +27,9 @@ */ /*----------------------------------------------------------- - * Implementation of functions defined in portable.h for the ST STR71x ARM7 - * port. - *----------------------------------------------------------*/ +* Implementation of functions defined in portable.h for the ST STR71x ARM7 +* port. +*----------------------------------------------------------*/ /* Library includes. */ #include "wdg.h" @@ -43,14 +43,14 @@ #include "task.h" /* Constants required to setup the initial stack. */ -#define portINITIAL_SPSR ( ( StackType_t ) 0x1f ) /* System mode, ARM mode, interrupts enabled. */ -#define portTHUMB_MODE_BIT ( ( StackType_t ) 0x20 ) -#define portINSTRUCTION_SIZE ( ( StackType_t ) 4 ) +#define portINITIAL_SPSR ( ( StackType_t ) 0x1f ) /* System mode, ARM mode, interrupts enabled. */ +#define portTHUMB_MODE_BIT ( ( StackType_t ) 0x20 ) +#define portINSTRUCTION_SIZE ( ( StackType_t ) 4 ) /* Constants required to handle critical sections. */ -#define portNO_CRITICAL_NESTING ( ( uint32_t ) 0 ) +#define portNO_CRITICAL_NESTING ( ( uint32_t ) 0 ) -#define portMICROS_PER_SECOND 1000000 +#define portMICROS_PER_SECOND 1000000 /*-----------------------------------------------------------*/ @@ -58,13 +58,13 @@ static void prvSetupTimerInterrupt( void ); /* ulCriticalNesting will get set to zero when the first task starts. It -cannot be initialised to 0 as this will cause interrupts to be enabled -during the kernel initialisation process. */ + * cannot be initialised to 0 as this will cause interrupts to be enabled + * during the kernel initialisation process. */ uint32_t ulCriticalNesting = ( uint32_t ) 9999; /* Tick interrupt routines for cooperative and preemptive operation -respectively. The preemptive version is not defined as __irq as it is called -from an asm wrapper function. */ + * respectively. The preemptive version is not defined as __irq as it is called + * from an asm wrapper function. */ __arm __irq void vPortNonPreemptiveTick( void ); void vPortPreemptiveTick( void ); @@ -76,56 +76,58 @@ void vPortPreemptiveTick( void ); * * See header file for description. */ -StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters ) +StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, + TaskFunction_t pxCode, + void * pvParameters ) { -StackType_t *pxOriginalTOS; + StackType_t * pxOriginalTOS; pxOriginalTOS = pxTopOfStack; /* To ensure asserts in tasks.c don't fail, although in this case the assert - is not really required. */ + * is not really required. */ pxTopOfStack--; /* Setup the initial stack of the task. The stack is set exactly as - expected by the portRESTORE_CONTEXT() macro. */ + * expected by the portRESTORE_CONTEXT() macro. */ /* First on the stack is the return address - which in this case is the - start of the task. The offset is added to make the return address appear - as it would within an IRQ ISR. */ + * start of the task. The offset is added to make the return address appear + * as it would within an IRQ ISR. */ *pxTopOfStack = ( StackType_t ) pxCode + portINSTRUCTION_SIZE; pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0xaaaaaaaa; /* R14 */ + *pxTopOfStack = ( StackType_t ) 0xaaaaaaaa; /* R14 */ pxTopOfStack--; *pxTopOfStack = ( StackType_t ) pxOriginalTOS; /* Stack used when task starts goes in R13. */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x12121212; /* R12 */ + *pxTopOfStack = ( StackType_t ) 0x12121212; /* R12 */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x11111111; /* R11 */ + *pxTopOfStack = ( StackType_t ) 0x11111111; /* R11 */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x10101010; /* R10 */ + *pxTopOfStack = ( StackType_t ) 0x10101010; /* R10 */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x09090909; /* R9 */ + *pxTopOfStack = ( StackType_t ) 0x09090909; /* R9 */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x08080808; /* R8 */ + *pxTopOfStack = ( StackType_t ) 0x08080808; /* R8 */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x07070707; /* R7 */ + *pxTopOfStack = ( StackType_t ) 0x07070707; /* R7 */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x06060606; /* R6 */ + *pxTopOfStack = ( StackType_t ) 0x06060606; /* R6 */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x05050505; /* R5 */ + *pxTopOfStack = ( StackType_t ) 0x05050505; /* R5 */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x04040404; /* R4 */ + *pxTopOfStack = ( StackType_t ) 0x04040404; /* R4 */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x03030303; /* R3 */ + *pxTopOfStack = ( StackType_t ) 0x03030303; /* R3 */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x02020202; /* R2 */ + *pxTopOfStack = ( StackType_t ) 0x02020202; /* R2 */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x01010101; /* R1 */ + *pxTopOfStack = ( StackType_t ) 0x01010101; /* R1 */ pxTopOfStack--; /* When the task starts is will expect to find the function parameter in - R0. */ + * R0. */ *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */ pxTopOfStack--; @@ -141,8 +143,8 @@ StackType_t *pxOriginalTOS; pxTopOfStack--; /* Interrupt flags cannot always be stored on the stack and will - instead be stored in a variable, which is then saved as part of the - tasks context. */ + * instead be stored in a variable, which is then saved as part of the + * tasks context. */ *pxTopOfStack = portNO_CRITICAL_NESTING; return pxTopOfStack; @@ -151,10 +153,10 @@ StackType_t *pxOriginalTOS; BaseType_t xPortStartScheduler( void ) { -extern void vPortStartFirstTask( void ); + extern void vPortStartFirstTask( void ); /* Start the timer that generates the tick ISR. Interrupts are disabled - here already. */ + * here already. */ prvSetupTimerInterrupt(); /* Start the first task. */ @@ -168,17 +170,17 @@ extern void vPortStartFirstTask( void ); void vPortEndScheduler( void ) { /* It is unlikely that the ARM port will require this function as there - is nothing to return to. */ + * is nothing to return to. */ } /*-----------------------------------------------------------*/ /* The cooperative scheduler requires a normal IRQ service routine to -simply increment the system tick. */ + * simply increment the system tick. */ __arm __irq void vPortNonPreemptiveTick( void ) { /* Increment the tick count - which may wake some tasks but as the - preemptive scheduler is not being used any woken task is not given - processor time no matter what its priority. */ + * preemptive scheduler is not being used any woken task is not given + * processor time no matter what its priority. */ xTaskIncrementTick(); /* Clear the interrupt in the watchdog and EIC. */ @@ -188,7 +190,7 @@ __arm __irq void vPortNonPreemptiveTick( void ) /*-----------------------------------------------------------*/ /* This function is called from an asm wrapper, so does not require the __irq -keyword. */ + * keyword. */ void vPortPreemptiveTick( void ) { /* Increment the tick counter. */ @@ -218,7 +220,7 @@ static void prvSetupTimerInterrupt( void ) WDG_ECITConfig( ENABLE ); /* Start the timer - interrupts are actually disabled at this point so - it is safe to do this here. */ + * it is safe to do this here. */ WDG_CntOnOffConfig( ENABLE ); } /*-----------------------------------------------------------*/ @@ -228,9 +230,9 @@ __arm __interwork void vPortEnterCritical( void ) /* Disable interrupts first! */ __disable_interrupt(); - /* Now interrupts are disabled ulCriticalNesting can be accessed - directly. Increment ulCriticalNesting to keep a count of how many times - portENTER_CRITICAL() has been called. */ + /* Now that interrupts are disabled, ulCriticalNesting can be accessed + * directly. Increment ulCriticalNesting to keep a count of how many times + * portENTER_CRITICAL() has been called. */ ulCriticalNesting++; } /*-----------------------------------------------------------*/ @@ -243,7 +245,7 @@ __arm __interwork void vPortExitCritical( void ) ulCriticalNesting--; /* If the nesting level has reached zero then interrupts should be - re-enabled. */ + * re-enabled. */ if( ulCriticalNesting == portNO_CRITICAL_NESTING ) { __enable_interrupt(); diff --git a/Source/portable/IAR/STR71x/portasm.s79 b/Source/portable/IAR/STR71x/portasm.s79 index 9939edab3..f49df6109 100644 --- a/Source/portable/IAR/STR71x/portasm.s79 +++ b/Source/portable/IAR/STR71x/portasm.s79 @@ -1,5 +1,5 @@ ;/* -; * FreeRTOS Kernel V10.6.2 +; * FreeRTOS Kernel V11.0.1 ; * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. ; * ; * SPDX-License-Identifier: MIT diff --git a/Source/portable/IAR/STR71x/portmacro.h b/Source/portable/IAR/STR71x/portmacro.h index 379bfe51c..cfb610ac2 100644 --- a/Source/portable/IAR/STR71x/portmacro.h +++ b/Source/portable/IAR/STR71x/portmacro.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -50,24 +50,24 @@ /* Type definitions. */ -#define portCHAR char -#define portFLOAT float -#define portDOUBLE double -#define portLONG long -#define portSHORT short -#define portSTACK_TYPE uint32_t -#define portBASE_TYPE long - -typedef portSTACK_TYPE StackType_t; -typedef long BaseType_t; -typedef unsigned long UBaseType_t; - - -#if( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS ) - typedef uint16_t TickType_t; - #define portMAX_DELAY ( TickType_t ) 0xffff -#elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS ) - typedef uint32_t TickType_t; +#define portCHAR char +#define portFLOAT float +#define portDOUBLE double +#define portLONG long +#define portSHORT short +#define portSTACK_TYPE uint32_t +#define portBASE_TYPE long + +typedef portSTACK_TYPE StackType_t; +typedef long BaseType_t; +typedef unsigned long UBaseType_t; + + +#if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS ) + typedef uint16_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffff +#elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS ) + typedef uint32_t TickType_t; #define portMAX_DELAY ( TickType_t ) 0xffffffffUL #else #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width. @@ -75,11 +75,11 @@ typedef unsigned long UBaseType_t; /*-----------------------------------------------------------*/ /* Hardware specifics. */ -#define portSTACK_GROWTH ( -1 ) -#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) -#define portBYTE_ALIGNMENT 8 -#define portYIELD() asm ( "SWI 0" ) -#define portNOP() asm ( "NOP" ) +#define portSTACK_GROWTH ( -1 ) +#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) +#define portBYTE_ALIGNMENT 8 +#define portYIELD() asm ( "SWI 0" ) +#define portNOP() asm ( "NOP" ) /*-----------------------------------------------------------*/ /* Critical section handling. */ @@ -95,27 +95,32 @@ __arm __interwork void vPortExitCritical( void ); /*-----------------------------------------------------------*/ /* Task utilities. */ -#define portEND_SWITCHING_ISR( xSwitchRequired ) \ -{ \ -extern void vTaskSwitchContext( void ); \ - \ - if( xSwitchRequired ) \ - { \ - vTaskSwitchContext(); \ - } \ -} +#define portEND_SWITCHING_ISR( xSwitchRequired ) \ + { \ + extern void vTaskSwitchContext( void ); \ + \ + if( xSwitchRequired ) \ + { \ + traceISR_EXIT_TO_SCHEDULER(); \ + vTaskSwitchContext(); \ + } \ + else \ + { \ + traceISR_EXIT(); \ + } \ + } /*-----------------------------------------------------------*/ /* EIC utilities. */ -#define portEIC_CICR_ADDR *( ( uint32_t * ) 0xFFFFF804 ) -#define portEIC_IPR_ADDR *( ( uint32_t * ) 0xFFFFF840 ) -#define portCLEAR_EIC() portEIC_IPR_ADDR = 0x01 << portEIC_CICR_ADDR +#define portEIC_CICR_ADDR *( ( uint32_t * ) 0xFFFFF804 ) +#define portEIC_IPR_ADDR *( ( uint32_t * ) 0xFFFFF840 ) +#define portCLEAR_EIC() portEIC_IPR_ADDR = 0x01 << portEIC_CICR_ADDR /*-----------------------------------------------------------*/ /* Task function macros as described on the FreeRTOS.org WEB site. */ -#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters ) -#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters ) +#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters ) +#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters ) /* *INDENT-OFF* */ #ifdef __cplusplus diff --git a/Source/portable/IAR/STR75x/ISR_Support.h b/Source/portable/IAR/STR75x/ISR_Support.h index f6b701a11..3aa820266 100644 --- a/Source/portable/IAR/STR75x/ISR_Support.h +++ b/Source/portable/IAR/STR75x/ISR_Support.h @@ -1,105 +1,151 @@ -;/* -; * FreeRTOS Kernel V10.6.2 -; * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. -; * -; * SPDX-License-Identifier: MIT -; * -; * Permission is hereby granted, free of charge, to any person obtaining a copy of -; * this software and associated documentation files (the "Software"), to deal in -; * the Software without restriction, including without limitation the rights to -; * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of -; * the Software, and to permit persons to whom the Software is furnished to do so, -; * subject to the following conditions: -; * -; * The above copyright notice and this permission notice shall be included in all -; * copies or substantial portions of the Software. -; * -; * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -; * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS -; * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR -; * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER -; * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN -; * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. -; * -; * https://www.FreeRTOS.org -; * https://github.com/FreeRTOS -; * -; */ - - EXTERN pxCurrentTCB - EXTERN ulCriticalNesting - -;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -; Context save and restore macro definitions -;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +; /* + * ; * FreeRTOS Kernel V11.0.1 + * ; * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * ; * + * ; * SPDX-License-Identifier: MIT + * ; * + * ; * Permission is hereby granted, free of charge, to any person obtaining a copy of + * ; * this software and associated documentation files (the "Software"), to deal in + * ; * the Software without restriction, including without limitation the rights to + * ; * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * ; * the Software, and to permit persons to whom the Software is furnished to do so, + * ; * subject to the following conditions: + * ; * + * ; * The above copyright notice and this permission notice shall be included in all + * ; * copies or substantial portions of the Software. + * ; * + * ; * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * ; * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * ; * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * ; * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * ; * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * ; * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * ; * + * ; * https://www.FreeRTOS.org + * ; * https://github.com/FreeRTOS + * ; * + * ; */ + +EXTERN pxCurrentTCB +EXTERN ulCriticalNesting + +; +Context save and restore macro definitions +; portSAVE_CONTEXT MACRO - ; Push R0 as we are going to use the register. - STMDB SP!, {R0} +; +Push R0 as we are going to use the register. + STMDB SP !, { + R0 +} + +Set R0 to point to the task stack pointer. + STMDB SP, { + SP +} +^ +NOP +SUB SP, SP, # 4 +LDMIA SP !, { + R0 +} + +; +Push the return address onto the stack. + STMDB R0 !, { + LR + } + + Now we have saved LR we can use it instead of R0. + MOV LR, R0 + +; + +Pop R0 so we can save it onto the system mode stack. + LDMIA SP !, { + R0 +} + +Push all the system mode registers onto the task stack. + STMDB LR, { + R0 - LR +} +^ +NOP +SUB LR, LR, # 60 + +; +Push the SPSR onto the task stack. + MRS R0, SPSR +STMDB LR !, { + R0 +} + +LDR R0, = ulCriticalNesting + LDR R0, [ R0 ] +STMDB LR !, { + R0 +} + +Store the new top of stack + +for the task. + LDR R1, = pxCurrentTCB + LDR R0, [ R1 ] +STR LR, [ R0 ] + +ENDM - ; Set R0 to point to the task stack pointer. - STMDB SP, {SP}^ - NOP - SUB SP, SP, #4 - LDMIA SP!, {R0} - ; Push the return address onto the stack. - STMDB R0!, {LR} - - ; Now we have saved LR we can use it instead of R0. - MOV LR, R0 - - ; Pop R0 so we can save it onto the system mode stack. - LDMIA SP!, {R0} - - ; Push all the system mode registers onto the task stack. - STMDB LR, {R0-LR}^ - NOP - SUB LR, LR, #60 - - ; Push the SPSR onto the task stack. - MRS R0, SPSR - STMDB LR!, {R0} +portRESTORE_CONTEXT MACRO - LDR R0, =ulCriticalNesting - LDR R0, [R0] - STMDB LR!, {R0} +; +Set the LR to the task stack. + LDR R1, = pxCurrentTCB + LDR R0, [ R1 ] +LDR LR, [ R0 ] - ; Store the new top of stack for the task. - LDR R1, =pxCurrentTCB - LDR R0, [R1] - STR LR, [R0] +; +The critical nesting depth is the first item on the stack. + ; +Load it into the ulCriticalNesting variable. + LDR R0, = ulCriticalNesting + LDMFD LR !, { + R1 +} - ENDM +STR R1, [ R0 ] +; +Get the SPSR from the stack. + LDMFD LR !, { + R0 +} +MSR SPSR_cxsf, R0 -portRESTORE_CONTEXT MACRO +; +Restore all system mode registers - ; Set the LR to the task stack. - LDR R1, =pxCurrentTCB - LDR R0, [R1] - LDR LR, [R0] +for the task. + LDMFD LR, { + R0 - R14 +} - ; The critical nesting depth is the first item on the stack. - ; Load it into the ulCriticalNesting variable. - LDR R0, =ulCriticalNesting - LDMFD LR!, {R1} - STR R1, [R0] +^ +NOP - ; Get the SPSR from the stack. - LDMFD LR!, {R0} - MSR SPSR_cxsf, R0 +; +Restore the return address. + LDR LR, [ LR, # + 60 ] - ; Restore all system mode registers for the task. - LDMFD LR, {R0-R14}^ - NOP +; - ; Restore the return address. - LDR LR, [LR, #+60] +And return -correcting the offset in the LR to obtain the +; - ; And return - correcting the offset in the LR to obtain the - ; correct address. - SUBS PC, LR, #4 +correct address. + SUBS PC, LR, # 4 - ENDM +ENDM diff --git a/Source/portable/IAR/STR75x/port.c b/Source/portable/IAR/STR75x/port.c index 2b2a78f2c..da7263714 100644 --- a/Source/portable/IAR/STR75x/port.c +++ b/Source/portable/IAR/STR75x/port.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -27,9 +27,9 @@ */ /*----------------------------------------------------------- - * Implementation of functions defined in portable.h for the ST STR75x ARM7 - * port. - *----------------------------------------------------------*/ +* Implementation of functions defined in portable.h for the ST STR75x ARM7 +* port. +*----------------------------------------------------------*/ /* Library includes. */ #include "75x_tb.h" @@ -40,14 +40,14 @@ #include "task.h" /* Constants required to setup the initial stack. */ -#define portINITIAL_SPSR ( ( StackType_t ) 0x3f ) /* System mode, THUMB mode, interrupts enabled. */ -#define portINSTRUCTION_SIZE ( ( StackType_t ) 4 ) +#define portINITIAL_SPSR ( ( StackType_t ) 0x3f ) /* System mode, THUMB mode, interrupts enabled. */ +#define portINSTRUCTION_SIZE ( ( StackType_t ) 4 ) /* Constants required to handle critical sections. */ -#define portNO_CRITICAL_NESTING ( ( uint32_t ) 0 ) +#define portNO_CRITICAL_NESTING ( ( uint32_t ) 0 ) /* Prescale used on the timer clock when calculating the tick period. */ -#define portPRESCALE 20 +#define portPRESCALE 20 /*-----------------------------------------------------------*/ @@ -56,8 +56,8 @@ static void prvSetupTimerInterrupt( void ); /* ulCriticalNesting will get set to zero when the first task starts. It -cannot be initialised to 0 as this will cause interrupts to be enabled -during the kernel initialisation process. */ + * cannot be initialised to 0 as this will cause interrupts to be enabled + * during the kernel initialisation process. */ uint32_t ulCriticalNesting = ( uint32_t ) 9999; /* Tick interrupt routines for preemptive operation. */ @@ -71,56 +71,58 @@ __arm void vPortPreemptiveTick( void ); * * See header file for description. */ -StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters ) +StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, + TaskFunction_t pxCode, + void * pvParameters ) { -StackType_t *pxOriginalTOS; + StackType_t * pxOriginalTOS; pxOriginalTOS = pxTopOfStack; /* To ensure asserts in tasks.c don't fail, although in this case the assert - is not really required. */ + * is not really required. */ pxTopOfStack--; /* Setup the initial stack of the task. The stack is set exactly as - expected by the portRESTORE_CONTEXT() macro. */ + * expected by the portRESTORE_CONTEXT() macro. */ /* First on the stack is the return address - which in this case is the - start of the task. The offset is added to make the return address appear - as it would within an IRQ ISR. */ + * start of the task. The offset is added to make the return address appear + * as it would within an IRQ ISR. */ *pxTopOfStack = ( StackType_t ) pxCode + portINSTRUCTION_SIZE; pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0xaaaaaaaa; /* R14 */ + *pxTopOfStack = ( StackType_t ) 0xaaaaaaaa; /* R14 */ pxTopOfStack--; *pxTopOfStack = ( StackType_t ) pxOriginalTOS; /* Stack used when task starts goes in R13. */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x12121212; /* R12 */ + *pxTopOfStack = ( StackType_t ) 0x12121212; /* R12 */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x11111111; /* R11 */ + *pxTopOfStack = ( StackType_t ) 0x11111111; /* R11 */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x10101010; /* R10 */ + *pxTopOfStack = ( StackType_t ) 0x10101010; /* R10 */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x09090909; /* R9 */ + *pxTopOfStack = ( StackType_t ) 0x09090909; /* R9 */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x08080808; /* R8 */ + *pxTopOfStack = ( StackType_t ) 0x08080808; /* R8 */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x07070707; /* R7 */ + *pxTopOfStack = ( StackType_t ) 0x07070707; /* R7 */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x06060606; /* R6 */ + *pxTopOfStack = ( StackType_t ) 0x06060606; /* R6 */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x05050505; /* R5 */ + *pxTopOfStack = ( StackType_t ) 0x05050505; /* R5 */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x04040404; /* R4 */ + *pxTopOfStack = ( StackType_t ) 0x04040404; /* R4 */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x03030303; /* R3 */ + *pxTopOfStack = ( StackType_t ) 0x03030303; /* R3 */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x02020202; /* R2 */ + *pxTopOfStack = ( StackType_t ) 0x02020202; /* R2 */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x01010101; /* R1 */ + *pxTopOfStack = ( StackType_t ) 0x01010101; /* R1 */ pxTopOfStack--; /* When the task starts is will expect to find the function parameter in - R0. */ + * R0. */ *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */ pxTopOfStack--; @@ -129,8 +131,8 @@ StackType_t *pxOriginalTOS; pxTopOfStack--; /* Interrupt flags cannot always be stored on the stack and will - instead be stored in a variable, which is then saved as part of the - tasks context. */ + * instead be stored in a variable, which is then saved as part of the + * tasks context. */ *pxTopOfStack = portNO_CRITICAL_NESTING; return pxTopOfStack; @@ -139,10 +141,10 @@ StackType_t *pxOriginalTOS; BaseType_t xPortStartScheduler( void ) { -extern void vPortStartFirstTask( void ); + extern void vPortStartFirstTask( void ); /* Start the timer that generates the tick ISR. Interrupts are disabled - here already. */ + * here already. */ prvSetupTimerInterrupt(); /* Start the first task. */ @@ -156,7 +158,7 @@ extern void vPortStartFirstTask( void ); void vPortEndScheduler( void ) { /* It is unlikely that the ARM port will require this function as there - is nothing to return to. */ + * is nothing to return to. */ } /*-----------------------------------------------------------*/ @@ -175,30 +177,30 @@ __arm void vPortPreemptiveTick( void ) static void prvSetupTimerInterrupt( void ) { -EIC_IRQInitTypeDef EIC_IRQInitStructure; -TB_InitTypeDef TB_InitStructure; + EIC_IRQInitTypeDef EIC_IRQInitStructure; + TB_InitTypeDef TB_InitStructure; /* Setup the EIC for the TB. */ EIC_IRQInitStructure.EIC_IRQChannelCmd = ENABLE; EIC_IRQInitStructure.EIC_IRQChannel = TB_IRQChannel; EIC_IRQInitStructure.EIC_IRQChannelPriority = 1; - EIC_IRQInit(&EIC_IRQInitStructure); + EIC_IRQInit( &EIC_IRQInitStructure ); /* Setup the TB for the generation of the tick interrupt. */ TB_InitStructure.TB_Mode = TB_Mode_Timing; TB_InitStructure.TB_CounterMode = TB_CounterMode_Down; TB_InitStructure.TB_Prescaler = portPRESCALE - 1; TB_InitStructure.TB_AutoReload = ( ( configCPU_CLOCK_HZ / portPRESCALE ) / configTICK_RATE_HZ ); - TB_Init(&TB_InitStructure); + TB_Init( &TB_InitStructure ); /* Enable TB Update interrupt */ - TB_ITConfig(TB_IT_Update, ENABLE); + TB_ITConfig( TB_IT_Update, ENABLE ); /* Clear TB Update interrupt pending bit */ - TB_ClearITPendingBit(TB_IT_Update); + TB_ClearITPendingBit( TB_IT_Update ); /* Enable TB */ - TB_Cmd(ENABLE); + TB_Cmd( ENABLE ); } /*-----------------------------------------------------------*/ @@ -207,9 +209,9 @@ __arm __interwork void vPortEnterCritical( void ) /* Disable interrupts first! */ __disable_interrupt(); - /* Now interrupts are disabled ulCriticalNesting can be accessed - directly. Increment ulCriticalNesting to keep a count of how many times - portENTER_CRITICAL() has been called. */ + /* Now that interrupts are disabled, ulCriticalNesting can be accessed + * directly. Increment ulCriticalNesting to keep a count of how many times + * portENTER_CRITICAL() has been called. */ ulCriticalNesting++; } /*-----------------------------------------------------------*/ @@ -222,7 +224,7 @@ __arm __interwork void vPortExitCritical( void ) ulCriticalNesting--; /* If the nesting level has reached zero then interrupts should be - re-enabled. */ + * re-enabled. */ if( ulCriticalNesting == portNO_CRITICAL_NESTING ) { __enable_interrupt(); diff --git a/Source/portable/IAR/STR75x/portasm.s79 b/Source/portable/IAR/STR75x/portasm.s79 index 45a1f4280..d02e3dcee 100644 --- a/Source/portable/IAR/STR75x/portasm.s79 +++ b/Source/portable/IAR/STR75x/portasm.s79 @@ -1,5 +1,5 @@ ;/* -; * FreeRTOS Kernel V10.6.2 +; * FreeRTOS Kernel V11.0.1 ; * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. ; * ; * SPDX-License-Identifier: MIT diff --git a/Source/portable/IAR/STR75x/portmacro.h b/Source/portable/IAR/STR75x/portmacro.h index 297fee6f5..db4531c4e 100644 --- a/Source/portable/IAR/STR75x/portmacro.h +++ b/Source/portable/IAR/STR75x/portmacro.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -49,24 +49,24 @@ /* *INDENT-ON* */ /* Type definitions. */ -#define portCHAR char -#define portFLOAT float -#define portDOUBLE double -#define portLONG long -#define portSHORT short -#define portSTACK_TYPE uint32_t -#define portBASE_TYPE long - -typedef portSTACK_TYPE StackType_t; -typedef long BaseType_t; -typedef unsigned long UBaseType_t; - - -#if( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS ) - typedef uint16_t TickType_t; - #define portMAX_DELAY ( TickType_t ) 0xffff -#elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS ) - typedef uint32_t TickType_t; +#define portCHAR char +#define portFLOAT float +#define portDOUBLE double +#define portLONG long +#define portSHORT short +#define portSTACK_TYPE uint32_t +#define portBASE_TYPE long + +typedef portSTACK_TYPE StackType_t; +typedef long BaseType_t; +typedef unsigned long UBaseType_t; + + +#if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS ) + typedef uint16_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffff +#elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS ) + typedef uint32_t TickType_t; #define portMAX_DELAY ( TickType_t ) 0xffffffffUL #else #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width. @@ -74,11 +74,11 @@ typedef unsigned long UBaseType_t; /*-----------------------------------------------------------*/ /* Hardware specifics. */ -#define portSTACK_GROWTH ( -1 ) -#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) -#define portBYTE_ALIGNMENT 8 -#define portYIELD() asm ( "SWI 0" ) -#define portNOP() asm ( "NOP" ) +#define portSTACK_GROWTH ( -1 ) +#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) +#define portBYTE_ALIGNMENT 8 +#define portYIELD() asm ( "SWI 0" ) +#define portNOP() asm ( "NOP" ) /*-----------------------------------------------------------*/ /* Critical section handling. */ @@ -92,21 +92,26 @@ __arm __interwork void vPortExitCritical( void ); /*-----------------------------------------------------------*/ /* Task utilities. */ -#define portEND_SWITCHING_ISR( xSwitchRequired ) \ -{ \ -extern void vTaskSwitchContext( void ); \ - \ - if( xSwitchRequired ) \ - { \ - vTaskSwitchContext(); \ - } \ -} +#define portEND_SWITCHING_ISR( xSwitchRequired ) \ + { \ + extern void vTaskSwitchContext( void ); \ + \ + if( xSwitchRequired ) \ + { \ + traceISR_EXIT_TO_SCHEDULER(); \ + vTaskSwitchContext(); \ + } \ + else \ + { \ + traceISR_EXIT(); \ + } \ + } /*-----------------------------------------------------------*/ /* Task function macros as described on the FreeRTOS.org WEB site. */ -#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters ) -#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters ) +#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters ) +#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters ) /* *INDENT-OFF* */ #ifdef __cplusplus diff --git a/Source/portable/IAR/STR91x/ISR_Support.h b/Source/portable/IAR/STR91x/ISR_Support.h index e27236ce0..947559b37 100644 --- a/Source/portable/IAR/STR91x/ISR_Support.h +++ b/Source/portable/IAR/STR91x/ISR_Support.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -26,80 +26,126 @@ * */ - EXTERN pxCurrentTCB - EXTERN ulCriticalNesting +EXTERN pxCurrentTCB +EXTERN ulCriticalNesting -;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -; Context save and restore macro definitions -;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +; +Context save and restore macro definitions +; portSAVE_CONTEXT MACRO - ; Push R0 as we are going to use the register. - STMDB SP!, {R0} +; +Push R0 as we are going to use the register. + STMDB SP !, { + R0 +} + +Set R0 to point to the task stack pointer. + STMDB SP, { + SP +} +^ +NOP +SUB SP, SP, # 4 +LDMIA SP !, { + R0 +} + +; +Push the return address onto the stack. + STMDB R0 !, { + LR + } + + Now we have saved LR we can use it instead of R0. + MOV LR, R0 + +; + +Pop R0 so we can save it onto the system mode stack. + LDMIA SP !, { + R0 +} + +Push all the system mode registers onto the task stack. + STMDB LR, { + R0 - LR +} +^ +NOP +SUB LR, LR, # 60 + +; +Push the SPSR onto the task stack. + MRS R0, SPSR +STMDB LR !, { + R0 +} + +LDR R0, = ulCriticalNesting + LDR R0, [ R0 ] +STMDB LR !, { + R0 +} + +Store the new top of stack + +for the task. + LDR R1, = pxCurrentTCB + LDR R0, [ R1 ] +STR LR, [ R0 ] + +ENDM - ; Set R0 to point to the task stack pointer. - STMDB SP, {SP}^ - NOP - SUB SP, SP, #4 - LDMIA SP!, {R0} - ; Push the return address onto the stack. - STMDB R0!, {LR} - - ; Now we have saved LR we can use it instead of R0. - MOV LR, R0 - - ; Pop R0 so we can save it onto the system mode stack. - LDMIA SP!, {R0} - - ; Push all the system mode registers onto the task stack. - STMDB LR, {R0-LR}^ - NOP - SUB LR, LR, #60 - - ; Push the SPSR onto the task stack. - MRS R0, SPSR - STMDB LR!, {R0} +portRESTORE_CONTEXT MACRO - LDR R0, =ulCriticalNesting - LDR R0, [R0] - STMDB LR!, {R0} +; +Set the LR to the task stack. + LDR R1, = pxCurrentTCB + LDR R0, [ R1 ] +LDR LR, [ R0 ] - ; Store the new top of stack for the task. - LDR R1, =pxCurrentTCB - LDR R0, [R1] - STR LR, [R0] +; +The critical nesting depth is the first item on the stack. + ; +Load it into the ulCriticalNesting variable. + LDR R0, = ulCriticalNesting + LDMFD LR !, { + R1 +} - ENDM +STR R1, [ R0 ] +; +Get the SPSR from the stack. + LDMFD LR !, { + R0 +} +MSR SPSR_cxsf, R0 -portRESTORE_CONTEXT MACRO +; +Restore all system mode registers - ; Set the LR to the task stack. - LDR R1, =pxCurrentTCB - LDR R0, [R1] - LDR LR, [R0] +for the task. + LDMFD LR, { + R0 - R14 +} - ; The critical nesting depth is the first item on the stack. - ; Load it into the ulCriticalNesting variable. - LDR R0, =ulCriticalNesting - LDMFD LR!, {R1} - STR R1, [R0] +^ +NOP - ; Get the SPSR from the stack. - LDMFD LR!, {R0} - MSR SPSR_cxsf, R0 +; +Restore the return address. + LDR LR, [ LR, # + 60 ] - ; Restore all system mode registers for the task. - LDMFD LR, {R0-R14}^ - NOP +; - ; Restore the return address. - LDR LR, [LR, #+60] +And return -correcting the offset in the LR to obtain the +; - ; And return - correcting the offset in the LR to obtain the - ; correct address. - SUBS PC, LR, #4 +correct address. + SUBS PC, LR, # 4 - ENDM +ENDM diff --git a/Source/portable/IAR/STR91x/port.c b/Source/portable/IAR/STR91x/port.c index 0127ca042..5eda5d0c0 100644 --- a/Source/portable/IAR/STR91x/port.c +++ b/Source/portable/IAR/STR91x/port.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -27,9 +27,9 @@ */ /*----------------------------------------------------------- - * Implementation of functions defined in portable.h for the ST STR91x ARM9 - * port. - *----------------------------------------------------------*/ +* Implementation of functions defined in portable.h for the ST STR91x ARM9 +* port. +*----------------------------------------------------------*/ /* Library includes. */ #include "91x_lib.h" @@ -48,18 +48,18 @@ /* Constants required to setup the initial stack. */ #ifndef _RUN_TASK_IN_ARM_MODE_ - #define portINITIAL_SPSR ( ( StackType_t ) 0x3f ) /* System mode, THUMB mode, interrupts enabled. */ + #define portINITIAL_SPSR ( ( StackType_t ) 0x3f ) /* System mode, THUMB mode, interrupts enabled. */ #else - #define portINITIAL_SPSR ( ( StackType_t ) 0x1f ) /* System mode, ARM mode, interrupts enabled. */ + #define portINITIAL_SPSR ( ( StackType_t ) 0x1f ) /* System mode, ARM mode, interrupts enabled. */ #endif -#define portINSTRUCTION_SIZE ( ( StackType_t ) 4 ) +#define portINSTRUCTION_SIZE ( ( StackType_t ) 4 ) /* Constants required to handle critical sections. */ -#define portNO_CRITICAL_NESTING ( ( uint32_t ) 0 ) +#define portNO_CRITICAL_NESTING ( ( uint32_t ) 0 ) #ifndef abs - #define abs(x) ((x)>0 ? (x) : -(x)) + #define abs( x ) ( ( x ) > 0 ? ( x ) : -( x ) ) #endif /** @@ -74,14 +74,14 @@ * } * */ -#define TOGGLE_LED(port,pin) \ - if ( ((((port)->DR[(pin)<<2])) & (pin)) != Bit_RESET ) \ - { \ - (port)->DR[(pin) <<2] = 0x00; \ - } \ - else \ - { \ - (port)->DR[(pin) <<2] = (pin); \ +#define TOGGLE_LED( port, pin ) \ + if( ( ( ( ( port )->DR[ ( pin ) << 2 ] ) ) & ( pin ) ) != Bit_RESET ) \ + { \ + ( port )->DR[ ( pin ) << 2 ] = 0x00; \ + } \ + else \ + { \ + ( port )->DR[ ( pin ) << 2 ] = ( pin ); \ } @@ -91,13 +91,13 @@ static void prvSetupTimerInterrupt( void ); /* ulCriticalNesting will get set to zero when the first task starts. It -cannot be initialised to 0 as this will cause interrupts to be enabled -during the kernel initialisation process. */ + * cannot be initialised to 0 as this will cause interrupts to be enabled + * during the kernel initialisation process. */ uint32_t ulCriticalNesting = ( uint32_t ) 9999; /* Tick interrupt routines for cooperative and preemptive operation -respectively. The preemptive version is not defined as __irq as it is called -from an asm wrapper function. */ + * respectively. The preemptive version is not defined as __irq as it is called + * from an asm wrapper function. */ void WDG_IRQHandler( void ); /* VIC interrupt default handler. */ @@ -116,56 +116,58 @@ static void prvDefaultHandler( void ); * * See header file for description. */ -StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters ) +StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, + TaskFunction_t pxCode, + void * pvParameters ) { - StackType_t *pxOriginalTOS; + StackType_t * pxOriginalTOS; pxOriginalTOS = pxTopOfStack; /* To ensure asserts in tasks.c don't fail, although in this case the assert - is not really required. */ + * is not really required. */ pxTopOfStack--; /* Setup the initial stack of the task. The stack is set exactly as - expected by the portRESTORE_CONTEXT() macro. */ + * expected by the portRESTORE_CONTEXT() macro. */ /* First on the stack is the return address - which in this case is the - start of the task. The offset is added to make the return address appear - as it would within an IRQ ISR. */ + * start of the task. The offset is added to make the return address appear + * as it would within an IRQ ISR. */ *pxTopOfStack = ( StackType_t ) pxCode + portINSTRUCTION_SIZE; pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0xaaaaaaaa; /* R14 */ + *pxTopOfStack = ( StackType_t ) 0xaaaaaaaa; /* R14 */ pxTopOfStack--; *pxTopOfStack = ( StackType_t ) pxOriginalTOS; /* Stack used when task starts goes in R13. */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x12121212; /* R12 */ + *pxTopOfStack = ( StackType_t ) 0x12121212; /* R12 */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x11111111; /* R11 */ + *pxTopOfStack = ( StackType_t ) 0x11111111; /* R11 */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x10101010; /* R10 */ + *pxTopOfStack = ( StackType_t ) 0x10101010; /* R10 */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x09090909; /* R9 */ + *pxTopOfStack = ( StackType_t ) 0x09090909; /* R9 */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x08080808; /* R8 */ + *pxTopOfStack = ( StackType_t ) 0x08080808; /* R8 */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x07070707; /* R7 */ + *pxTopOfStack = ( StackType_t ) 0x07070707; /* R7 */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x06060606; /* R6 */ + *pxTopOfStack = ( StackType_t ) 0x06060606; /* R6 */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x05050505; /* R5 */ + *pxTopOfStack = ( StackType_t ) 0x05050505; /* R5 */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x04040404; /* R4 */ + *pxTopOfStack = ( StackType_t ) 0x04040404; /* R4 */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x03030303; /* R3 */ + *pxTopOfStack = ( StackType_t ) 0x03030303; /* R3 */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x02020202; /* R2 */ + *pxTopOfStack = ( StackType_t ) 0x02020202; /* R2 */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x01010101; /* R1 */ + *pxTopOfStack = ( StackType_t ) 0x01010101; /* R1 */ pxTopOfStack--; /* When the task starts is will expect to find the function parameter in - R0. */ + * R0. */ *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */ pxTopOfStack--; @@ -174,8 +176,8 @@ StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t px pxTopOfStack--; /* Interrupt flags cannot always be stored on the stack and will - instead be stored in a variable, which is then saved as part of the - tasks context. */ + * instead be stored in a variable, which is then saved as part of the + * tasks context. */ *pxTopOfStack = portNO_CRITICAL_NESTING; return pxTopOfStack; @@ -184,10 +186,10 @@ StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t px BaseType_t xPortStartScheduler( void ) { -extern void vPortStartFirstTask( void ); + extern void vPortStartFirstTask( void ); /* Start the timer that generates the tick ISR. Interrupts are disabled - here already. */ + * here already. */ prvSetupTimerInterrupt(); /* Start the first task. */ @@ -201,41 +203,49 @@ extern void vPortStartFirstTask( void ); void vPortEndScheduler( void ) { /* It is unlikely that the ARM port will require this function as there - is nothing to return to. */ + * is nothing to return to. */ } /*-----------------------------------------------------------*/ /* This function is called from an asm wrapper, so does not require the __irq -keyword. */ + * keyword. */ #if configUSE_WATCHDOG_TICK == 1 - static void prvFindFactors(u32 n, u16 *a, u32 *b) + static void prvFindFactors( u32 n, + u16 * a, + u32 * b ) { /* This function is copied from the ST STR7 library and is - copyright STMicroelectronics. Reproduced with permission. */ + * copyright STMicroelectronics. Reproduced with permission. */ u32 b0; u16 a0; - int32_t err, err_min=n; + int32_t err, err_min = n; - *a = a0 = ((n-1)/65536ul) + 1; + *a = a0 = ( ( n - 1 ) / 65536ul ) + 1; *b = b0 = n / *a; - for (; *a <= 256; (*a)++) + for( ; *a <= 256; ( *a )++ ) { *b = n / *a; - err = (int32_t)*a * (int32_t)*b - (int32_t)n; - if (abs(err) > (*a / 2)) + err = ( int32_t ) *a * ( int32_t ) *b - ( int32_t ) n; + + if( abs( err ) > ( *a / 2 ) ) { - (*b)++; - err = (int32_t)*a * (int32_t)*b - (int32_t)n; + ( *b )++; + err = ( int32_t ) *a * ( int32_t ) *b - ( int32_t ) n; } - if (abs(err) < abs(err_min)) + + if( abs( err ) < abs( err_min ) ) { err_min = err; a0 = *a; b0 = *b; - if (err == 0) break; + + if( err == 0 ) + { + break; + } } } @@ -246,21 +256,21 @@ keyword. */ static void prvSetupTimerInterrupt( void ) { - WDG_InitTypeDef xWdg; - uint16_t a; - uint32_t n = configCPU_PERIPH_HZ / configTICK_RATE_HZ, b; + WDG_InitTypeDef xWdg; + uint16_t a; + uint32_t n = configCPU_PERIPH_HZ / configTICK_RATE_HZ, b; /* Configure the watchdog as a free running timer that generates a - periodic interrupt. */ + * periodic interrupt. */ SCU_APBPeriphClockConfig( __WDG, ENABLE ); WDG_DeInit(); - WDG_StructInit(&xWdg); + WDG_StructInit( &xWdg ); prvFindFactors( n, &a, &b ); xWdg.WDG_Prescaler = a - 1; xWdg.WDG_Preload = b - 1; WDG_Init( &xWdg ); - WDG_ITConfig(ENABLE); + WDG_ITConfig( ENABLE ); /* Configure the VIC for the WDG interrupt. */ VIC_Config( WDG_ITLine, VIC_IRQ, 10 ); @@ -270,7 +280,7 @@ keyword. */ VIC0->DVAR = ( uint32_t ) prvDefaultHandler; VIC1->DVAR = ( uint32_t ) prvDefaultHandler; - WDG_Cmd(ENABLE); + WDG_Cmd( ENABLE ); } /*-----------------------------------------------------------*/ @@ -289,36 +299,44 @@ keyword. */ } } -#else +#else /* if configUSE_WATCHDOG_TICK == 1 */ - static void prvFindFactors(u32 n, u8 *a, u16 *b) + static void prvFindFactors( u32 n, + u8 * a, + u16 * b ) { /* This function is copied from the ST STR7 library and is - copyright STMicroelectronics. Reproduced with permission. */ + * copyright STMicroelectronics. Reproduced with permission. */ u16 b0; u8 a0; - int32_t err, err_min=n; + int32_t err, err_min = n; - *a = a0 = ((n-1)/256) + 1; + *a = a0 = ( ( n - 1 ) / 256 ) + 1; *b = b0 = n / *a; - for (; *a <= 256; (*a)++) + for( ; *a <= 256; ( *a )++ ) { *b = n / *a; - err = (int32_t)*a * (int32_t)*b - (int32_t)n; - if (abs(err) > (*a / 2)) + err = ( int32_t ) *a * ( int32_t ) *b - ( int32_t ) n; + + if( abs( err ) > ( *a / 2 ) ) { - (*b)++; - err = (int32_t)*a * (int32_t)*b - (int32_t)n; + ( *b )++; + err = ( int32_t ) *a * ( int32_t ) *b - ( int32_t ) n; } - if (abs(err) < abs(err_min)) + + if( abs( err ) < abs( err_min ) ) { err_min = err; a0 = *a; b0 = *b; - if (err == 0) break; + + if( err == 0 ) + { + break; + } } } @@ -336,20 +354,20 @@ keyword. */ TIM_InitTypeDef timer; SCU_APBPeriphClockConfig( __TIM23, ENABLE ); - TIM_DeInit(TIM2); - TIM_StructInit(&timer); + TIM_DeInit( TIM2 ); + TIM_StructInit( &timer ); prvFindFactors( n, &a, &b ); - timer.TIM_Mode = TIM_OCM_CHANNEL_1; - timer.TIM_OC1_Modes = TIM_TIMING; - timer.TIM_Clock_Source = TIM_CLK_APB; - timer.TIM_Clock_Edge = TIM_CLK_EDGE_RISING; - timer.TIM_Prescaler = a-1; - timer.TIM_Pulse_Level_1 = TIM_HIGH; - timer.TIM_Pulse_Length_1 = s_nPulseLength = b-1; + timer.TIM_Mode = TIM_OCM_CHANNEL_1; + timer.TIM_OC1_Modes = TIM_TIMING; + timer.TIM_Clock_Source = TIM_CLK_APB; + timer.TIM_Clock_Edge = TIM_CLK_EDGE_RISING; + timer.TIM_Prescaler = a - 1; + timer.TIM_Pulse_Level_1 = TIM_HIGH; + timer.TIM_Pulse_Length_1 = s_nPulseLength = b - 1; - TIM_Init (TIM2, &timer); - TIM_ITConfig(TIM2, TIM_IT_OC1, ENABLE); + TIM_Init( TIM2, &timer ); + TIM_ITConfig( TIM2, TIM_IT_OC1, ENABLE ); /* Configure the VIC for the WDG interrupt. */ VIC_Config( TIM2_ITLine, VIC_IRQ, 10 ); VIC_ITCmd( TIM2_ITLine, ENABLE ); @@ -358,14 +376,14 @@ keyword. */ VIC0->DVAR = ( uint32_t ) prvDefaultHandler; VIC1->DVAR = ( uint32_t ) prvDefaultHandler; - TIM_CounterCmd(TIM2, TIM_CLEAR); - TIM_CounterCmd(TIM2, TIM_START); + TIM_CounterCmd( TIM2, TIM_CLEAR ); + TIM_CounterCmd( TIM2, TIM_START ); } /*-----------------------------------------------------------*/ void TIM2_IRQHandler( void ) { - /* Reset the timer counter to avioid overflow. */ + /* Reset the timer counter to avoid overflow. */ TIM2->OC1R += s_nPulseLength; /* Increment the tick counter. */ @@ -388,9 +406,9 @@ __arm __interwork void vPortEnterCritical( void ) /* Disable interrupts first! */ portDISABLE_INTERRUPTS(); - /* Now interrupts are disabled ulCriticalNesting can be accessed - directly. Increment ulCriticalNesting to keep a count of how many times - portENTER_CRITICAL() has been called. */ + /* Now that interrupts are disabled, ulCriticalNesting can be accessed + * directly. Increment ulCriticalNesting to keep a count of how many times + * portENTER_CRITICAL() has been called. */ ulCriticalNesting++; } /*-----------------------------------------------------------*/ @@ -403,7 +421,7 @@ __arm __interwork void vPortExitCritical( void ) ulCriticalNesting--; /* If the nesting level has reached zero then interrupts should be - re-enabled. */ + * re-enabled. */ if( ulCriticalNesting == portNO_CRITICAL_NESTING ) { portENABLE_INTERRUPTS(); diff --git a/Source/portable/IAR/STR91x/portasm.s79 b/Source/portable/IAR/STR91x/portasm.s79 index bb9d45082..32b17c44b 100644 --- a/Source/portable/IAR/STR91x/portasm.s79 +++ b/Source/portable/IAR/STR91x/portasm.s79 @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/Source/portable/IAR/STR91x/portmacro.h b/Source/portable/IAR/STR91x/portmacro.h index 852baec99..e5359cdcd 100644 --- a/Source/portable/IAR/STR91x/portmacro.h +++ b/Source/portable/IAR/STR91x/portmacro.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -49,24 +49,24 @@ /* *INDENT-ON* */ /* Type definitions. */ -#define portCHAR char -#define portFLOAT float -#define portDOUBLE double -#define portLONG long -#define portSHORT short -#define portSTACK_TYPE uint32_t -#define portBASE_TYPE long - -typedef portSTACK_TYPE StackType_t; -typedef long BaseType_t; -typedef unsigned long UBaseType_t; - - -#if( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS ) - typedef uint16_t TickType_t; - #define portMAX_DELAY ( TickType_t ) 0xffff -#elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS ) - typedef uint32_t TickType_t; +#define portCHAR char +#define portFLOAT float +#define portDOUBLE double +#define portLONG long +#define portSHORT short +#define portSTACK_TYPE uint32_t +#define portBASE_TYPE long + +typedef portSTACK_TYPE StackType_t; +typedef long BaseType_t; +typedef unsigned long UBaseType_t; + + +#if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS ) + typedef uint16_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffff +#elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS ) + typedef uint32_t TickType_t; #define portMAX_DELAY ( TickType_t ) 0xffffffffUL #else #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width. @@ -74,11 +74,11 @@ typedef unsigned long UBaseType_t; /*-----------------------------------------------------------*/ /* Hardware specifics. */ -#define portSTACK_GROWTH ( -1 ) -#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) -#define portBYTE_ALIGNMENT 8 -#define portYIELD() asm ( "SWI 0" ) -#define portNOP() asm ( "NOP" ) +#define portSTACK_GROWTH ( -1 ) +#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) +#define portBYTE_ALIGNMENT 8 +#define portYIELD() asm ( "SWI 0" ) +#define portNOP() asm ( "NOP" ) /*-----------------------------------------------------------*/ /* Critical section handling. */ @@ -94,21 +94,26 @@ __arm __interwork void vPortExitCritical( void ); /*-----------------------------------------------------------*/ /* Task utilities. */ -#define portEND_SWITCHING_ISR( xSwitchRequired ) \ -{ \ -extern void vTaskSwitchContext( void ); \ - \ - if( xSwitchRequired ) \ - { \ - vTaskSwitchContext(); \ - } \ -} +#define portEND_SWITCHING_ISR( xSwitchRequired ) \ + { \ + extern void vTaskSwitchContext( void ); \ + \ + if( xSwitchRequired ) \ + { \ + traceISR_EXIT_TO_SCHEDULER(); \ + vTaskSwitchContext(); \ + } \ + else \ + { \ + traceISR_EXIT(); \ + } \ + } /*-----------------------------------------------------------*/ /* Task function macros as described on the FreeRTOS.org WEB site. */ -#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters ) -#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters ) +#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters ) +#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters ) /* *INDENT-OFF* */ #ifdef __cplusplus diff --git a/Source/portable/IAR/V850ES/ISR_Support.h b/Source/portable/IAR/V850ES/ISR_Support.h index aa66708c9..d18e4efd8 100644 --- a/Source/portable/IAR/V850ES/ISR_Support.h +++ b/Source/portable/IAR/V850ES/ISR_Support.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -26,125 +26,150 @@ * */ - EXTERN pxCurrentTCB - EXTERN usCriticalNesting +EXTERN pxCurrentTCB +EXTERN usCriticalNesting #include "FreeRTOSConfig.h" -;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -; Context save and restore macro definitions -;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +; +Context save and restore macro definitions +; portSAVE_CONTEXT MACRO - add -0x0C,sp ; prepare stack to save necessary values - st.w lp,8[sp] ; store LP to stack - stsr 0,r31 - st.w lp,4[sp] ; store EIPC to stack - stsr 1,lp - st.w lp,0[sp] ; store EIPSW to stack -#if configDATA_MODE == 1 ; Using the Tiny data model - prepare {r20,r21,r22,r23,r24,r25,r26,r27,r28,r29,r30},76,sp ; save general purpose registers - sst.w r19,72[ep] - sst.w r18,68[ep] - sst.w r17,64[ep] - sst.w r16,60[ep] - sst.w r15,56[ep] - sst.w r14,52[ep] - sst.w r13,48[ep] - sst.w r12,44[ep] - sst.w r11,40[ep] - sst.w r10,36[ep] - sst.w r9,32[ep] - sst.w r8,28[ep] - sst.w r7,24[ep] - sst.w r6,20[ep] - sst.w r5,16[ep] - sst.w r4,12[ep] -#else ; Using the Small/Large data model - prepare {r20,r21,r22,r23,r24,r26,r27,r28,r29,r30},72,sp ; save general purpose registers - sst.w r19,68[ep] - sst.w r18,64[ep] - sst.w r17,60[ep] - sst.w r16,56[ep] - sst.w r15,52[ep] - sst.w r14,48[ep] - sst.w r13,44[ep] - sst.w r12,40[ep] - sst.w r11,36[ep] - sst.w r10,32[ep] - sst.w r9,28[ep] - sst.w r8,24[ep] - sst.w r7,20[ep] - sst.w r6,16[ep] - sst.w r5,12[ep] + add - 0x0C, sp; +prepare stack to save necessary values +st.w lp, 8[ sp ]; +store LP to stack + stsr 0, r31 + st.w lp, 4[ sp ]; +store EIPC to stack + stsr 1, lp + st.w lp, 0[ sp ]; +store EIPSW to stack +#if configDATA_MODE == 1; Using the Tiny data model +prepare { + r20, r21, r22, r23, r24, r25, r26, r27, r28, r29, r30 +}, 76, sp; +save general purpose registers +sst.w r19, 72[ ep ] +sst.w r18, 68[ ep ] +sst.w r17, 64[ ep ] +sst.w r16, 60[ ep ] +sst.w r15, 56[ ep ] +sst.w r14, 52[ ep ] +sst.w r13, 48[ ep ] +sst.w r12, 44[ ep ] +sst.w r11, 40[ ep ] +sst.w r10, 36[ ep ] +sst.w r9, 32[ ep ] +sst.w r8, 28[ ep ] +sst.w r7, 24[ ep ] +sst.w r6, 20[ ep ] +sst.w r5, 16[ ep ] +sst.w r4, 12[ ep ] +#else; Using the Small / Large data model +prepare { + r20, r21, r22, r23, r24, r26, r27, r28, r29, r30 +}, 72, sp; +save general purpose registers +sst.w r19, 68[ ep ] +sst.w r18, 64[ ep ] +sst.w r17, 60[ ep ] +sst.w r16, 56[ ep ] +sst.w r15, 52[ ep ] +sst.w r14, 48[ ep ] +sst.w r13, 44[ ep ] +sst.w r12, 40[ ep ] +sst.w r11, 36[ ep ] +sst.w r10, 32[ ep ] +sst.w r9, 28[ ep ] +sst.w r8, 24[ ep ] +sst.w r7, 20[ ep ] +sst.w r6, 16[ ep ] +sst.w r5, 12[ ep ] #endif /* configDATA_MODE */ - sst.w r2,8[ep] - sst.w r1,4[ep] - MOVHI hi1(usCriticalNesting),r0,r1 ; save usCriticalNesting value to stack - ld.w lw1(usCriticalNesting)[r1],r2 - sst.w r2,0[ep] - MOVHI hi1(pxCurrentTCB),r0,r1 ; save SP to top of current TCB - ld.w lw1(pxCurrentTCB)[r1],r2 - st.w sp,0[r2] - ENDM +sst.w r2, 8[ ep ] +sst.w r1, 4[ ep ] +MOVHI hi1( usCriticalNesting ), r0, r1; +save usCriticalNesting value to stack +ld.w lw1( usCriticalNesting )[ r1 ], r2 +sst.w r2, 0[ ep ] +MOVHI hi1( pxCurrentTCB ), r0, r1; +save SP to top of current TCB +ld.w lw1( pxCurrentTCB )[ r1 ], r2 +st.w sp, 0[ r2 ] +ENDM portRESTORE_CONTEXT MACRO - MOVHI hi1(pxCurrentTCB),r0,r1 ; get Stackpointer address - ld.w lw1(pxCurrentTCB)[r1],sp - MOV sp,r1 - ld.w 0[r1],sp ; load stackpointer - MOV sp,ep ; set stack pointer to element pointer - sld.w 0[ep],r1 ; load usCriticalNesting value from stack - MOVHI hi1(usCriticalNesting),r0,r2 - st.w r1,lw1(usCriticalNesting)[r2] - sld.w 4[ep],r1 ; restore general purpose registers - sld.w 8[ep],r2 -#if configDATA_MODE == 1 ; Using Tiny data model - sld.w 12[ep],r4 - sld.w 16[ep],r5 - sld.w 20[ep],r6 - sld.w 24[ep],r7 - sld.w 28[ep],r8 - sld.w 32[ep],r9 - sld.w 36[ep],r10 - sld.w 40[ep],r11 - sld.w 44[ep],r12 - sld.w 48[ep],r13 - sld.w 52[ep],r14 - sld.w 56[ep],r15 - sld.w 60[ep],r16 - sld.w 64[ep],r17 - sld.w 68[ep],r18 - sld.w 72[ep],r19 - dispose 76,{r20,r21,r22,r23,r24,r25,r26,r27,r28,r29,r30} -#else ; Using Small/Large data model - sld.w 12[ep],r5 - sld.w 16[ep],r6 - sld.w 20[ep],r7 - sld.w 24[ep],r8 - sld.w 28[ep],r9 - sld.w 32[ep],r10 - sld.w 36[ep],r11 - sld.w 40[ep],r12 - sld.w 44[ep],r13 - sld.w 48[ep],r14 - sld.w 52[ep],r15 - sld.w 56[ep],r16 - sld.w 60[ep],r17 - sld.w 64[ep],r18 - sld.w 68[ep],r19 - dispose 72,{r20,r21,r22,r23,r24,r26,r27,r28,r29,r30} +MOVHI hi1( pxCurrentTCB ), r0, r1; +get Stackpointer address +ld.w lw1( pxCurrentTCB )[ r1 ], sp +MOV sp, r1 +ld.w 0[ r1 ], sp; +load stackpointer +MOV sp, ep; +set stack pointer to element pointer +sld.w 0[ ep ], r1; +load usCriticalNesting value from stack +MOVHI hi1( usCriticalNesting ), r0, r2 +st.w r1, lw1( usCriticalNesting )[ r2 ] +sld.w 4[ ep ], r1; +restore general purpose registers +sld.w 8[ ep ], r2 +#if configDATA_MODE == 1; Using Tiny data model + sld.w 12[ ep ], r4 + sld.w 16[ ep ], r5 + sld.w 20[ ep ], r6 + sld.w 24[ ep ], r7 + sld.w 28[ ep ], r8 + sld.w 32[ ep ], r9 + sld.w 36[ ep ], r10 + sld.w 40[ ep ], r11 + sld.w 44[ ep ], r12 + sld.w 48[ ep ], r13 + sld.w 52[ ep ], r14 + sld.w 56[ ep ], r15 + sld.w 60[ ep ], r16 + sld.w 64[ ep ], r17 + sld.w 68[ ep ], r18 + sld.w 72[ ep ], r19 + dispose 76, { + r20, r21, r22, r23, r24, r25, r26, r27, r28, r29, r30 + } +#else; Using Small / Large data model + sld.w 12[ ep ], r5 + sld.w 16[ ep ], r6 + sld.w 20[ ep ], r7 + sld.w 24[ ep ], r8 + sld.w 28[ ep ], r9 + sld.w 32[ ep ], r10 + sld.w 36[ ep ], r11 + sld.w 40[ ep ], r12 + sld.w 44[ ep ], r13 + sld.w 48[ ep ], r14 + sld.w 52[ ep ], r15 + sld.w 56[ ep ], r16 + sld.w 60[ ep ], r17 + sld.w 64[ ep ], r18 + sld.w 68[ ep ], r19 + dispose 72, { + r20, r21, r22, r23, r24, r26, r27, r28, r29, r30 + } #endif /* configDATA_MODE */ - ld.w 0[sp],lp ; restore EIPSW from stack - ldsr lp,1 - ld.w 4[sp],lp ; restore EIPC from stack - ldsr lp,0 - ld.w 8[sp],lp ; restore LP from stack - add 0x0C,sp ; set SP to right position +ld.w 0[ sp ], lp; +restore EIPSW from stack +ldsr lp, 1 +ld.w 4[ sp ], lp; +restore EIPC from stack +ldsr lp, 0 +ld.w 8[ sp ], lp; +restore LP from stack + add 0x0C, sp; +set SP to right position - RETI +RETI - ENDM +ENDM diff --git a/Source/portable/IAR/V850ES/port.c b/Source/portable/IAR/V850ES/port.c index ed0601c11..801609076 100644 --- a/Source/portable/IAR/V850ES/port.c +++ b/Source/portable/IAR/V850ES/port.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -34,14 +34,14 @@ #include "task.h" /* Critical nesting should be initialised to a non zero value so interrupts don't -accidentally get enabled before the scheduler is started. */ -#define portINITIAL_CRITICAL_NESTING (( StackType_t ) 10) + * accidentally get enabled before the scheduler is started. */ +#define portINITIAL_CRITICAL_NESTING ( ( StackType_t ) 10 ) /* The PSW value assigned to tasks when they start to run for the first time. */ -#define portPSW (( StackType_t ) 0x00000000) +#define portPSW ( ( StackType_t ) 0x00000000 ) /* We require the address of the pxCurrentTCB variable, but don't want to know -any details of its type. */ + * any details of its type. */ typedef void TCB_t; extern volatile TCB_t * volatile pxCurrentTCB; @@ -53,75 +53,77 @@ volatile StackType_t usCriticalNesting = portINITIAL_CRITICAL_NESTING; static void prvSetupTimerInterrupt( void ); /*-----------------------------------------------------------*/ -StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters ) +StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, + TaskFunction_t pxCode, + void * pvParameters ) { - *pxTopOfStack = ( StackType_t ) pxCode; /* Task function start address */ + *pxTopOfStack = ( StackType_t ) pxCode; /* Task function start address */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) pxCode; /* Task function start address */ + *pxTopOfStack = ( StackType_t ) pxCode; /* Task function start address */ pxTopOfStack--; - *pxTopOfStack = portPSW; /* Initial PSW value */ + *pxTopOfStack = portPSW; /* Initial PSW value */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x20202020; /* Initial Value of R20 */ + *pxTopOfStack = ( StackType_t ) 0x20202020; /* Initial Value of R20 */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x21212121; /* Initial Value of R21 */ + *pxTopOfStack = ( StackType_t ) 0x21212121; /* Initial Value of R21 */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x22222222; /* Initial Value of R22 */ + *pxTopOfStack = ( StackType_t ) 0x22222222; /* Initial Value of R22 */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x23232323; /* Initial Value of R23 */ + *pxTopOfStack = ( StackType_t ) 0x23232323; /* Initial Value of R23 */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x24242424; /* Initial Value of R24 */ + *pxTopOfStack = ( StackType_t ) 0x24242424; /* Initial Value of R24 */ pxTopOfStack--; -#if (__DATA_MODEL__ == 0) || (__DATA_MODEL__ == 1) - *pxTopOfStack = ( StackType_t ) 0x25252525; /* Initial Value of R25 */ + #if ( __DATA_MODEL__ == 0 ) || ( __DATA_MODEL__ == 1 ) + *pxTopOfStack = ( StackType_t ) 0x25252525; /* Initial Value of R25 */ + pxTopOfStack--; + #endif /* configDATA_MODE */ + *pxTopOfStack = ( StackType_t ) 0x26262626; /* Initial Value of R26 */ pxTopOfStack--; -#endif /* configDATA_MODE */ - *pxTopOfStack = ( StackType_t ) 0x26262626; /* Initial Value of R26 */ + *pxTopOfStack = ( StackType_t ) 0x27272727; /* Initial Value of R27 */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x27272727; /* Initial Value of R27 */ + *pxTopOfStack = ( StackType_t ) 0x28282828; /* Initial Value of R28 */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x28282828; /* Initial Value of R28 */ + *pxTopOfStack = ( StackType_t ) 0x29292929; /* Initial Value of R29 */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x29292929; /* Initial Value of R29 */ + *pxTopOfStack = ( StackType_t ) 0x30303030; /* Initial Value of R30 */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x30303030; /* Initial Value of R30 */ + *pxTopOfStack = ( StackType_t ) 0x19191919; /* Initial Value of R19 */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x19191919; /* Initial Value of R19 */ + *pxTopOfStack = ( StackType_t ) 0x18181818; /* Initial Value of R18 */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x18181818; /* Initial Value of R18 */ + *pxTopOfStack = ( StackType_t ) 0x17171717; /* Initial Value of R17 */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x17171717; /* Initial Value of R17 */ + *pxTopOfStack = ( StackType_t ) 0x16161616; /* Initial Value of R16 */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x16161616; /* Initial Value of R16 */ + *pxTopOfStack = ( StackType_t ) 0x15151515; /* Initial Value of R15 */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x15151515; /* Initial Value of R15 */ + *pxTopOfStack = ( StackType_t ) 0x14141414; /* Initial Value of R14 */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x14141414; /* Initial Value of R14 */ + *pxTopOfStack = ( StackType_t ) 0x13131313; /* Initial Value of R13 */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x13131313; /* Initial Value of R13 */ + *pxTopOfStack = ( StackType_t ) 0x12121212; /* Initial Value of R12 */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x12121212; /* Initial Value of R12 */ + *pxTopOfStack = ( StackType_t ) 0x11111111; /* Initial Value of R11 */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x11111111; /* Initial Value of R11 */ + *pxTopOfStack = ( StackType_t ) 0x10101010; /* Initial Value of R10 */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x10101010; /* Initial Value of R10 */ + *pxTopOfStack = ( StackType_t ) 0x99999999; /* Initial Value of R09 */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x99999999; /* Initial Value of R09 */ + *pxTopOfStack = ( StackType_t ) 0x88888888; /* Initial Value of R08 */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x88888888; /* Initial Value of R08 */ + *pxTopOfStack = ( StackType_t ) 0x77777777; /* Initial Value of R07 */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x77777777; /* Initial Value of R07 */ + *pxTopOfStack = ( StackType_t ) 0x66666666; /* Initial Value of R06 */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x66666666; /* Initial Value of R06 */ + *pxTopOfStack = ( StackType_t ) 0x55555555; /* Initial Value of R05 */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x55555555; /* Initial Value of R05 */ + #if __DATA_MODEL__ == 0 || __DATA_MODEL__ == 1 + *pxTopOfStack = ( StackType_t ) 0x44444444; /* Initial Value of R04 */ + pxTopOfStack--; + #endif /* configDATA_MODE */ + *pxTopOfStack = ( StackType_t ) 0x22222222; /* Initial Value of R02 */ pxTopOfStack--; -#if __DATA_MODEL__ == 0 || __DATA_MODEL__ == 1 - *pxTopOfStack = ( StackType_t ) 0x44444444; /* Initial Value of R04 */ - pxTopOfStack--; -#endif /* configDATA_MODE */ - *pxTopOfStack = ( StackType_t ) 0x22222222; /* Initial Value of R02 */ - pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) pvParameters; /* R1 is expected to hold the function parameter*/ + *pxTopOfStack = ( StackType_t ) pvParameters; /* R1 is expected to hold the function parameter*/ pxTopOfStack--; *pxTopOfStack = ( StackType_t ) portNO_CRITICAL_SECTION_NESTING; @@ -136,7 +138,7 @@ StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t px BaseType_t xPortStartScheduler( void ) { /* Setup the hardware to generate the tick. Interrupts are disabled when - this function is called. */ + * this function is called. */ prvSetupTimerInterrupt(); /* Restore the context of the first task that is going to run. */ @@ -150,7 +152,7 @@ BaseType_t xPortStartScheduler( void ) void vPortEndScheduler( void ) { /* It is unlikely that the V850ES/Fx3 port will get stopped. If required simply - disable the tick interrupt here. */ + * disable the tick interrupt here. */ } /*-----------------------------------------------------------*/ @@ -159,24 +161,24 @@ void vPortEndScheduler( void ) */ static void prvSetupTimerInterrupt( void ) { - TM0CE = 0; /* TMM0 operation disable */ - TM0EQMK0 = 1; /* INTTM0EQ0 interrupt disable */ - TM0EQIF0 = 0; /* clear INTTM0EQ0 interrupt flag */ + TM0CE = 0; /* TMM0 operation disable */ + TM0EQMK0 = 1; /* INTTM0EQ0 interrupt disable */ + TM0EQIF0 = 0; /* clear INTTM0EQ0 interrupt flag */ #ifdef __IAR_V850ES_Fx3__ { - TM0CMP0 = (((configCPU_CLOCK_HZ / configTICK_RATE_HZ) / 2)-1); /* divided by 2 because peripherals only run at CPU_CLOCK/2 */ + TM0CMP0 = ( ( ( configCPU_CLOCK_HZ / configTICK_RATE_HZ ) / 2 ) - 1 ); /* divided by 2 because peripherals only run at CPU_CLOCK/2 */ } #else { - TM0CMP0 = (configCPU_CLOCK_HZ / configTICK_RATE_HZ); + TM0CMP0 = ( configCPU_CLOCK_HZ / configTICK_RATE_HZ ); } #endif TM0EQIC0 &= 0xF8; - TM0CTL0 = 0x00; - TM0EQIF0 = 0; /* clear INTTM0EQ0 interrupt flag */ - TM0EQMK0 = 0; /* INTTM0EQ0 interrupt enable */ - TM0CE = 1; /* TMM0 operation enable */ + TM0CTL0 = 0x00; + TM0EQIF0 = 0; /* clear INTTM0EQ0 interrupt flag */ + TM0EQMK0 = 0; /* INTTM0EQ0 interrupt enable */ + TM0CE = 1; /* TMM0 operation enable */ } /*-----------------------------------------------------------*/ diff --git a/Source/portable/IAR/V850ES/portasm.s85 b/Source/portable/IAR/V850ES/portasm.s85 index 9627e1f4f..c81904d3b 100644 --- a/Source/portable/IAR/V850ES/portasm.s85 +++ b/Source/portable/IAR/V850ES/portasm.s85 @@ -1,5 +1,5 @@ ;/* -; * FreeRTOS Kernel V10.6.2 +; * FreeRTOS Kernel V11.0.1 ; * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. ; * ; * SPDX-License-Identifier: MIT diff --git a/Source/portable/IAR/V850ES/portasm_Fx3.s85 b/Source/portable/IAR/V850ES/portasm_Fx3.s85 index e20477ed6..51717c37d 100644 --- a/Source/portable/IAR/V850ES/portasm_Fx3.s85 +++ b/Source/portable/IAR/V850ES/portasm_Fx3.s85 @@ -1,5 +1,5 @@ ;/* -; * FreeRTOS Kernel V10.6.2 +; * FreeRTOS Kernel V11.0.1 ; * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. ; * ; * SPDX-License-Identifier: MIT diff --git a/Source/portable/IAR/V850ES/portasm_Hx2.s85 b/Source/portable/IAR/V850ES/portasm_Hx2.s85 index 9e0275c3d..11abf9407 100644 --- a/Source/portable/IAR/V850ES/portasm_Hx2.s85 +++ b/Source/portable/IAR/V850ES/portasm_Hx2.s85 @@ -1,5 +1,5 @@ ;/* -; * FreeRTOS Kernel V10.6.2 +; * FreeRTOS Kernel V11.0.1 ; * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. ; * ; * SPDX-License-Identifier: MIT diff --git a/Source/portable/IAR/V850ES/portmacro.h b/Source/portable/IAR/V850ES/portmacro.h index 3b9fe731c..35d2531c6 100644 --- a/Source/portable/IAR/V850ES/portmacro.h +++ b/Source/portable/IAR/V850ES/portmacro.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -46,24 +46,24 @@ */ /* Type definitions. */ -#define portCHAR char -#define portFLOAT float -#define portDOUBLE double -#define portLONG long -#define portSHORT short -#define portSTACK_TYPE unsigned int -#define portBASE_TYPE int +#define portCHAR char +#define portFLOAT float +#define portDOUBLE double +#define portLONG long +#define portSHORT short +#define portSTACK_TYPE unsigned int +#define portBASE_TYPE int -typedef portSTACK_TYPE StackType_t; -typedef long BaseType_t; -typedef unsigned long UBaseType_t; +typedef portSTACK_TYPE StackType_t; +typedef long BaseType_t; +typedef unsigned long UBaseType_t; #if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS ) - typedef uint16_t TickType_t; - #define portMAX_DELAY ( TickType_t ) 0xffff -#elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS ) - typedef uint32_t TickType_t; + typedef uint16_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffff +#elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS ) + typedef uint32_t TickType_t; #define portMAX_DELAY ( TickType_t ) 0xffffffffUL #else #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width. @@ -71,42 +71,42 @@ typedef unsigned long UBaseType_t; /*-----------------------------------------------------------*/ /* Interrupt control macros. */ -#define portDISABLE_INTERRUPTS() __asm ( "DI" ) -#define portENABLE_INTERRUPTS() __asm ( "EI" ) +#define portDISABLE_INTERRUPTS() __asm( "DI" ) +#define portENABLE_INTERRUPTS() __asm( "EI" ) /*-----------------------------------------------------------*/ /* Critical section control macros. */ -#define portNO_CRITICAL_SECTION_NESTING ( ( UBaseType_t ) 0 ) - -#define portENTER_CRITICAL() \ -{ \ -extern volatile /*uint16_t*/ portSTACK_TYPE usCriticalNesting; \ - \ - portDISABLE_INTERRUPTS(); \ - \ - /* Now interrupts are disabled ulCriticalNesting can be accessed */ \ - /* directly. Increment ulCriticalNesting to keep a count of how many */ \ - /* times portENTER_CRITICAL() has been called. */ \ - usCriticalNesting++; \ -} +#define portNO_CRITICAL_SECTION_NESTING ( ( UBaseType_t ) 0 ) + +#define portENTER_CRITICAL() \ + { \ + extern volatile /*uint16_t*/ portSTACK_TYPE usCriticalNesting; \ + \ + portDISABLE_INTERRUPTS(); \ + \ + /* Now that interrupts are disabled, ulCriticalNesting can be accessed */ \ + /* directly. Increment ulCriticalNesting to keep a count of how many */ \ + /* times portENTER_CRITICAL() has been called. */ \ + usCriticalNesting++; \ + } #define portEXIT_CRITICAL() \ -{ \ -extern volatile /*uint16_t*/ portSTACK_TYPE usCriticalNesting; \ - \ - if( usCriticalNesting > portNO_CRITICAL_SECTION_NESTING ) \ { \ - /* Decrement the nesting count as we are leaving a critical section. */ \ - usCriticalNesting--; \ + extern volatile /*uint16_t*/ portSTACK_TYPE usCriticalNesting; \ \ - /* If the nesting level has reached zero then interrupts should be */ \ - /* re-enabled. */ \ - if( usCriticalNesting == portNO_CRITICAL_SECTION_NESTING ) \ + if( usCriticalNesting > portNO_CRITICAL_SECTION_NESTING ) \ { \ - portENABLE_INTERRUPTS(); \ + /* Decrement the nesting count as we are leaving a critical section. */ \ + usCriticalNesting--; \ + \ + /* If the nesting level has reached zero then interrupts should be */ \ + /* re-enabled. */ \ + if( usCriticalNesting == portNO_CRITICAL_SECTION_NESTING ) \ + { \ + portENABLE_INTERRUPTS(); \ + } \ } \ - } \ -} + } /*-----------------------------------------------------------*/ /* Task utilities. */ @@ -114,22 +114,22 @@ extern void vPortYield( void ); extern void vPortStart( void ); extern void portSAVE_CONTEXT( void ); extern void portRESTORE_CONTEXT( void ); -#define portYIELD() __asm ( "trap 0" ) -#define portNOP() __asm ( "NOP" ) +#define portYIELD() __asm( "trap 0" ) +#define portNOP() __asm( "NOP" ) extern void vTaskSwitchContext( void ); -#define portYIELD_FROM_ISR( xHigherPriorityTaskWoken ) do { if( xHigherPriorityTaskWoken ) vTaskSwitchContext(); } while( 0 ) +#define portYIELD_FROM_ISR( xHigherPriorityTaskWoken ) do { if( xHigherPriorityTaskWoken ) vTaskSwitchContext( ); } while( 0 ) /*-----------------------------------------------------------*/ -/* Hardwware specifics. */ -#define portBYTE_ALIGNMENT 4 -#define portSTACK_GROWTH ( -1 ) -#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) +/* Hardware specifics. */ +#define portBYTE_ALIGNMENT 4 +#define portSTACK_GROWTH ( -1 ) +#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) /*-----------------------------------------------------------*/ /* Task function macros as described on the FreeRTOS.org WEB site. */ -#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters ) -#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters ) +#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters ) +#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters ) /* *INDENT-OFF* */ diff --git a/Source/portable/MPLAB/PIC18F/port.c b/Source/portable/MPLAB/PIC18F/port.c index d6949d4f4..088818e68 100644 --- a/Source/portable/MPLAB/PIC18F/port.c +++ b/Source/portable/MPLAB/PIC18F/port.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -136,7 +136,7 @@ static void prvLowInterrupt( void ); * * The compiler uses some locations at the bottom of the memory for temporary * storage during math and other computations. This is especially true if - * 32bit data types are utilised (as they are by the scheduler). The .tmpdata + * 32bit data types are utilized (as they are by the scheduler). The .tmpdata * and MATH_DATA sections have to be stored in there entirety as part of a task * context. This macro stores from data address 0x00 to * portCOMPILER_MANAGED_MEMORY_SIZE. This is sufficient for the demo diff --git a/Source/portable/MPLAB/PIC18F/portmacro.h b/Source/portable/MPLAB/PIC18F/portmacro.h index 517d3dc0b..f44016e81 100644 --- a/Source/portable/MPLAB/PIC18F/portmacro.h +++ b/Source/portable/MPLAB/PIC18F/portmacro.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -80,7 +80,7 @@ typedef unsigned char UBaseType_t; /* Retrieve the INTCON register from the stack, and enable interrupts if they were saved as being enabled. Don't modify any other bits -within the INTCON register as these may have lagitimately have been +within the INTCON register as these may have legitimately have been modified within the critical region. */ #define portEXIT_CRITICAL() _asm \ MOVF POSTDEC1, 1, 0 \ diff --git a/Source/portable/MPLAB/PIC24_dsPIC/port.c b/Source/portable/MPLAB/PIC24_dsPIC/port.c index 3ba3d2bce..7ff134db3 100644 --- a/Source/portable/MPLAB/PIC24_dsPIC/port.c +++ b/Source/portable/MPLAB/PIC24_dsPIC/port.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/Source/portable/MPLAB/PIC24_dsPIC/portasm_PIC24.S b/Source/portable/MPLAB/PIC24_dsPIC/portasm_PIC24.S index e9b9476dc..074e15ebe 100644 --- a/Source/portable/MPLAB/PIC24_dsPIC/portasm_PIC24.S +++ b/Source/portable/MPLAB/PIC24_dsPIC/portasm_PIC24.S @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/Source/portable/MPLAB/PIC24_dsPIC/portasm_dsPIC.S b/Source/portable/MPLAB/PIC24_dsPIC/portasm_dsPIC.S index f1fbcb0bd..f6cb18823 100644 --- a/Source/portable/MPLAB/PIC24_dsPIC/portasm_dsPIC.S +++ b/Source/portable/MPLAB/PIC24_dsPIC/portasm_dsPIC.S @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/Source/portable/MPLAB/PIC24_dsPIC/portmacro.h b/Source/portable/MPLAB/PIC24_dsPIC/portmacro.h index bc7a1d758..4f0ae100e 100644 --- a/Source/portable/MPLAB/PIC24_dsPIC/portmacro.h +++ b/Source/portable/MPLAB/PIC24_dsPIC/portmacro.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -84,7 +84,7 @@ typedef unsigned short UBaseType_t; #define portDISABLE_INTERRUPTS() SET_CPU_IPL( configKERNEL_INTERRUPT_PRIORITY ); __asm volatile ( "NOP" ) #define portENABLE_INTERRUPTS() SET_CPU_IPL( 0 ) -/* Note that exiting a critical sectino will set the IPL bits to 0, nomatter +/* Note that exiting a critical sectino will set the IPL bits to 0, no matter what their value was prior to entering the critical section. */ extern void vPortEnterCritical( void ); extern void vPortExitCritical( void ); diff --git a/Source/portable/MPLAB/PIC32MEC14xx/ISR_Support.h b/Source/portable/MPLAB/PIC32MEC14xx/ISR_Support.h index d3d368056..5b01d2ab1 100644 --- a/Source/portable/MPLAB/PIC32MEC14xx/ISR_Support.h +++ b/Source/portable/MPLAB/PIC32MEC14xx/ISR_Support.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/Source/portable/MPLAB/PIC32MEC14xx/port.c b/Source/portable/MPLAB/PIC32MEC14xx/port.c index 161016b4b..7f3aee4ed 100644 --- a/Source/portable/MPLAB/PIC32MEC14xx/port.c +++ b/Source/portable/MPLAB/PIC32MEC14xx/port.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/Source/portable/MPLAB/PIC32MEC14xx/port_asm.S b/Source/portable/MPLAB/PIC32MEC14xx/port_asm.S index 7da7b78bd..bb34bcdae 100644 --- a/Source/portable/MPLAB/PIC32MEC14xx/port_asm.S +++ b/Source/portable/MPLAB/PIC32MEC14xx/port_asm.S @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/Source/portable/MPLAB/PIC32MEC14xx/portmacro.h b/Source/portable/MPLAB/PIC32MEC14xx/portmacro.h index 3ce89b8ab..2017d3c6e 100644 --- a/Source/portable/MPLAB/PIC32MEC14xx/portmacro.h +++ b/Source/portable/MPLAB/PIC32MEC14xx/portmacro.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -239,7 +239,19 @@ extern volatile UBaseType_t uxInterruptNesting; #define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters ) /*-----------------------------------------------------------*/ -#define portEND_SWITCHING_ISR( xSwitchRequired ) do { if( xSwitchRequired ) { portYIELD(); } } while( 0 ) +#define portEND_SWITCHING_ISR( xSwitchRequired ) \ + do \ + { \ + if( xSwitchRequired != pdFALSE ) \ + { \ + traceISR_EXIT_TO_SCHEDULER(); \ + portYIELD(); \ + } \ + else \ + { \ + traceISR_EXIT(); \ + } \ + } while( 0 ) /* Required by the kernel aware debugger. */ #ifdef __DEBUG diff --git a/Source/portable/MPLAB/PIC32MX/ISR_Support.h b/Source/portable/MPLAB/PIC32MX/ISR_Support.h index 7d0cc2fc2..fa1d6a23f 100644 --- a/Source/portable/MPLAB/PIC32MX/ISR_Support.h +++ b/Source/portable/MPLAB/PIC32MX/ISR_Support.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/Source/portable/MPLAB/PIC32MX/port.c b/Source/portable/MPLAB/PIC32MX/port.c index 716348867..8a4f2f811 100644 --- a/Source/portable/MPLAB/PIC32MX/port.c +++ b/Source/portable/MPLAB/PIC32MX/port.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -95,7 +95,7 @@ stack overflow hook function (because the stack overflow hook is specific to a task stack, not the ISR stack). */ #if( configCHECK_FOR_STACK_OVERFLOW > 2 ) - /* Don't use 0xa5 as the stack fill bytes as that is used by the kernerl for + /* Don't use 0xa5 as the stack fill bytes as that is used by the kernel for the task stacks, and so will legitimately appear in many positions within the ISR stack. */ #define portISR_STACK_FILL_BYTE 0xee diff --git a/Source/portable/MPLAB/PIC32MX/port_asm.S b/Source/portable/MPLAB/PIC32MX/port_asm.S index d0b8878e9..c3fffcd60 100644 --- a/Source/portable/MPLAB/PIC32MX/port_asm.S +++ b/Source/portable/MPLAB/PIC32MX/port_asm.S @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/Source/portable/MPLAB/PIC32MX/portmacro.h b/Source/portable/MPLAB/PIC32MX/portmacro.h index 1cd24e0ba..d99e61375 100644 --- a/Source/portable/MPLAB/PIC32MX/portmacro.h +++ b/Source/portable/MPLAB/PIC32MX/portmacro.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -191,7 +191,19 @@ extern volatile UBaseType_t uxInterruptNesting; #define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters ) /*-----------------------------------------------------------*/ -#define portEND_SWITCHING_ISR( xSwitchRequired ) do { if( xSwitchRequired ) { portYIELD(); } } while( 0 ) +#define portEND_SWITCHING_ISR( xSwitchRequired ) \ + do \ + { \ + if( xSwitchRequired != pdFALSE ) \ + { \ + traceISR_EXIT_TO_SCHEDULER(); \ + portYIELD(); \ + } \ + else \ + { \ + traceISR_EXIT(); \ + } \ + } while( 0 ) /* Required by the kernel aware debugger. */ #ifdef __DEBUG diff --git a/Source/portable/MPLAB/PIC32MZ/ISR_Support.h b/Source/portable/MPLAB/PIC32MZ/ISR_Support.h index fd5d71ae5..56e9746c4 100644 --- a/Source/portable/MPLAB/PIC32MZ/ISR_Support.h +++ b/Source/portable/MPLAB/PIC32MZ/ISR_Support.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/Source/portable/MPLAB/PIC32MZ/port.c b/Source/portable/MPLAB/PIC32MZ/port.c index a56e8dda3..076eb9b50 100644 --- a/Source/portable/MPLAB/PIC32MZ/port.c +++ b/Source/portable/MPLAB/PIC32MZ/port.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -117,7 +117,7 @@ stack overflow hook function (because the stack overflow hook is specific to a task stack, not the ISR stack). */ #if( configCHECK_FOR_STACK_OVERFLOW > 2 ) - /* Don't use 0xa5 as the stack fill bytes as that is used by the kernerl for + /* Don't use 0xa5 as the stack fill bytes as that is used by the kernel for the task stacks, and so will legitimately appear in many positions within the ISR stack. */ #define portISR_STACK_FILL_BYTE 0xee diff --git a/Source/portable/MPLAB/PIC32MZ/port_asm.S b/Source/portable/MPLAB/PIC32MZ/port_asm.S index c4bfce31d..c6aa5ef25 100644 --- a/Source/portable/MPLAB/PIC32MZ/port_asm.S +++ b/Source/portable/MPLAB/PIC32MZ/port_asm.S @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/Source/portable/MPLAB/PIC32MZ/portmacro.h b/Source/portable/MPLAB/PIC32MZ/portmacro.h index 7e2a14d26..7d25c587b 100644 --- a/Source/portable/MPLAB/PIC32MZ/portmacro.h +++ b/Source/portable/MPLAB/PIC32MZ/portmacro.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -202,7 +202,19 @@ extern volatile UBaseType_t uxInterruptNesting; #define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters ) /*-----------------------------------------------------------*/ -#define portEND_SWITCHING_ISR( xSwitchRequired ) do { if( xSwitchRequired ) { portYIELD(); } } while( 0 ) +#define portEND_SWITCHING_ISR( xSwitchRequired ) \ + do \ + { \ + if( xSwitchRequired != pdFALSE ) \ + { \ + traceISR_EXIT_TO_SCHEDULER(); \ + portYIELD(); \ + } \ + else \ + { \ + traceISR_EXIT(); \ + } \ + } while( 0 ) /* Required by the kernel aware debugger. */ #ifdef __DEBUG diff --git a/Source/portable/MSVC-MingW/port.c b/Source/portable/MSVC-MingW/port.c index 55618fe09..a87837488 100644 --- a/Source/portable/MSVC-MingW/port.c +++ b/Source/portable/MSVC-MingW/port.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -39,14 +39,14 @@ #pragma comment(lib, "winmm.lib") #endif -#define portMAX_INTERRUPTS ( ( uint32_t ) sizeof( uint32_t ) * 8UL ) /* The number of bits in an uint32_t. */ -#define portNO_CRITICAL_NESTING ( ( uint32_t ) 0 ) +#define portMAX_INTERRUPTS ( ( uint32_t ) sizeof( uint32_t ) * 8UL ) /* The number of bits in an uint32_t. */ +#define portNO_CRITICAL_NESTING ( ( uint32_t ) 0 ) /* The priorities at which the various components of the simulation execute. */ -#define portDELETE_SELF_THREAD_PRIORITY THREAD_PRIORITY_TIME_CRITICAL /* Must be highest. */ -#define portSIMULATED_INTERRUPTS_THREAD_PRIORITY THREAD_PRIORITY_TIME_CRITICAL -#define portSIMULATED_TIMER_THREAD_PRIORITY THREAD_PRIORITY_HIGHEST -#define portTASK_THREAD_PRIORITY THREAD_PRIORITY_ABOVE_NORMAL +#define portDELETE_SELF_THREAD_PRIORITY THREAD_PRIORITY_TIME_CRITICAL /* Must be highest. */ +#define portSIMULATED_INTERRUPTS_THREAD_PRIORITY THREAD_PRIORITY_TIME_CRITICAL +#define portSIMULATED_TIMER_THREAD_PRIORITY THREAD_PRIORITY_HIGHEST +#define portTASK_THREAD_PRIORITY THREAD_PRIORITY_ABOVE_NORMAL /* * Created as a high priority thread, this function uses a timer to simulate @@ -87,47 +87,47 @@ static BOOL WINAPI prvEndProcess( DWORD dwCtrlType ); /*-----------------------------------------------------------*/ /* The WIN32 simulator runs each task in a thread. The context switching is -managed by the threads, so the task stack does not have to be managed directly, -although the task stack is still used to hold an xThreadState structure this is -the only thing it will ever hold. The structure indirectly maps the task handle -to a thread handle. */ + * managed by the threads, so the task stack does not have to be managed directly, + * although the task stack is still used to hold an xThreadState structure this is + * the only thing it will ever hold. The structure indirectly maps the task handle + * to a thread handle. */ typedef struct { /* Handle of the thread that executes the task. */ - void *pvThread; + void * pvThread; /* Event used to make sure the thread does not execute past a yield point - between the call to SuspendThread() to suspend the thread and the - asynchronous SuspendThread() operation actually being performed. */ - void *pvYieldEvent; + * between the call to SuspendThread() to suspend the thread and the + * asynchronous SuspendThread() operation actually being performed. */ + void * pvYieldEvent; } ThreadState_t; /* Simulated interrupts waiting to be processed. This is a bit mask where each -bit represents one interrupt, so a maximum of 32 interrupts can be simulated. */ + * bit represents one interrupt, so a maximum of 32 interrupts can be simulated. */ static volatile uint32_t ulPendingInterrupts = 0UL; /* An event used to inform the simulated interrupt processing thread (a high -priority thread that simulated interrupt processing) that an interrupt is -pending. */ -static void *pvInterruptEvent = NULL; + * priority thread that simulated interrupt processing) that an interrupt is + * pending. */ +static void * pvInterruptEvent = NULL; /* Mutex used to protect all the simulated interrupt variables that are accessed -by multiple threads. */ -static void *pvInterruptEventMutex = NULL; + * by multiple threads. */ +static void * pvInterruptEventMutex = NULL; /* The critical nesting count for the currently executing task. This is -initialised to a non-zero value so interrupts do not become enabled during -the initialisation phase. As each task has its own critical nesting value -ulCriticalNesting will get set to zero when the first task runs. This -initialisation is probably not critical in this simulated environment as the -simulated interrupt handlers do not get created until the FreeRTOS scheduler is -started anyway. */ + * initialised to a non-zero value so interrupts do not become enabled during + * the initialisation phase. As each task has its own critical nesting value + * ulCriticalNesting will get set to zero when the first task runs. This + * initialisation is probably not critical in this simulated environment as the + * simulated interrupt handlers do not get created until the FreeRTOS scheduler is + * started anyway. */ static volatile uint32_t ulCriticalNesting = 9999UL; /* Handlers for all the simulated software interrupts. The first two positions -are used for the Yield and Tick interrupts so are handled slightly differently, -all the other interrupts can be user defined. */ -static uint32_t (*ulIsrHandler[ portMAX_INTERRUPTS ])( void ) = { 0 }; + * are used for the Yield and Tick interrupts so are handled slightly differently, + * all the other interrupts can be user defined. */ +static uint32_t (* ulIsrHandler[ portMAX_INTERRUPTS ])( void ) = { 0 }; /* Pointer to the TCB of the currently executing task. */ extern void * volatile pxCurrentTCB; @@ -139,8 +139,8 @@ static BaseType_t xPortRunning = pdFALSE; static DWORD WINAPI prvSimulatedPeripheralTimer( LPVOID lpParameter ) { -TickType_t xMinimumWindowsBlockTime; -TIMECAPS xTimeCaps; + TickType_t xMinimumWindowsBlockTime; + TIMECAPS xTimeCaps; /* Set the timer resolution to the maximum possible. */ if( timeGetDevCaps( &xTimeCaps, sizeof( xTimeCaps ) ) == MMSYSERR_NOERROR ) @@ -149,7 +149,7 @@ TIMECAPS xTimeCaps; timeBeginPeriod( xTimeCaps.wPeriodMin ); /* Register an exit handler so the timeBeginPeriod() function can be - matched with a timeEndPeriod() when the application exits. */ + * matched with a timeEndPeriod() when the application exits. */ SetConsoleCtrlHandler( prvEndProcess, TRUE ); } else @@ -163,11 +163,11 @@ TIMECAPS xTimeCaps; while( xPortRunning == pdTRUE ) { /* Wait until the timer expires and we can access the simulated interrupt - variables. *NOTE* this is not a 'real time' way of generating tick - events as the next wake time should be relative to the previous wake - time, not the time that Sleep() is called. It is done this way to - prevent overruns in this very non real time simulated/emulated - environment. */ + * variables. *NOTE* this is not a 'real time' way of generating tick + * events as the next wake time should be relative to the previous wake + * time, not the time that Sleep() is called. It is done this way to + * prevent overruns in this very non real time simulated/emulated + * environment. */ if( portTICK_PERIOD_MS < xMinimumWindowsBlockTime ) { Sleep( xMinimumWindowsBlockTime ); @@ -182,40 +182,39 @@ TIMECAPS xTimeCaps; configASSERT( xPortRunning ); /* Can't proceed if in a critical section as pvInterruptEventMutex won't - be available. */ + * be available. */ WaitForSingleObject( pvInterruptEventMutex, INFINITE ); /* The timer has expired, generate the simulated tick event. */ ulPendingInterrupts |= ( 1 << portINTERRUPT_TICK ); /* The interrupt is now pending - notify the simulated interrupt - handler thread. Must be outside of a critical section to get here so - the handler thread can execute immediately pvInterruptEventMutex is - released. */ + * handler thread. Must be outside of a critical section to get here so + * the handler thread can execute immediately pvInterruptEventMutex is + * released. */ configASSERT( ulCriticalNesting == 0UL ); SetEvent( pvInterruptEvent ); /* Give back the mutex so the simulated interrupt handler unblocks - and can access the interrupt handler variables. */ + * and can access the interrupt handler variables. */ ReleaseMutex( pvInterruptEventMutex ); } } - return 0; } /*-----------------------------------------------------------*/ static BOOL WINAPI prvEndProcess( DWORD dwCtrlType ) { -TIMECAPS xTimeCaps; + TIMECAPS xTimeCaps; ( void ) dwCtrlType; if( timeGetDevCaps( &xTimeCaps, sizeof( xTimeCaps ) ) == MMSYSERR_NOERROR ) { /* Match the call to timeBeginPeriod( xTimeCaps.wPeriodMin ) made when - the process started with a timeEndPeriod() as the process exits. */ + * the process started with a timeEndPeriod() as the process exits. */ timeEndPeriod( xTimeCaps.wPeriodMin ); } @@ -223,27 +222,29 @@ TIMECAPS xTimeCaps; } /*-----------------------------------------------------------*/ -StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters ) +StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, + TaskFunction_t pxCode, + void * pvParameters ) { -ThreadState_t *pxThreadState = NULL; -int8_t *pcTopOfStack = ( int8_t * ) pxTopOfStack; -const SIZE_T xStackSize = 1024; /* Set the size to a small number which will get rounded up to the minimum possible. */ + ThreadState_t * pxThreadState = NULL; + int8_t * pcTopOfStack = ( int8_t * ) pxTopOfStack; + const SIZE_T xStackSize = 1024; /* Set the size to a small number which will get rounded up to the minimum possible. */ /* In this simulated case a stack is not initialised, but instead a thread - is created that will execute the task being created. The thread handles - the context switching itself. The ThreadState_t object is placed onto - the stack that was created for the task - so the stack buffer is still - used, just not in the conventional way. It will not be used for anything - other than holding this structure. */ + * is created that will execute the task being created. The thread handles + * the context switching itself. The ThreadState_t object is placed onto + * the stack that was created for the task - so the stack buffer is still + * used, just not in the conventional way. It will not be used for anything + * other than holding this structure. */ pxThreadState = ( ThreadState_t * ) ( pcTopOfStack - sizeof( ThreadState_t ) ); /* Create the event used to prevent the thread from executing past its yield - point if the SuspendThread() call that suspends the thread does not take - effect immediately (it is an asynchronous call). */ - pxThreadState->pvYieldEvent = CreateEvent( NULL, /* Default security attributes. */ - FALSE, /* Auto reset. */ - FALSE, /* Start not signalled. */ - NULL );/* No name. */ + * point if the SuspendThread() call that suspends the thread does not take + * effect immediately (it is an asynchronous call). */ + pxThreadState->pvYieldEvent = CreateEvent( NULL, /* Default security attributes. */ + FALSE, /* Auto reset. */ + FALSE, /* Start not signalled. */ + NULL ); /* No name. */ /* Create the thread itself. */ pxThreadState->pvThread = CreateThread( NULL, xStackSize, ( LPTHREAD_START_ROUTINE ) pxCode, pvParameters, CREATE_SUSPENDED | STACK_SIZE_PARAM_IS_A_RESERVATION, NULL ); @@ -258,15 +259,16 @@ const SIZE_T xStackSize = 1024; /* Set the size to a small number which will get BaseType_t xPortStartScheduler( void ) { -void *pvHandle = NULL; -int32_t lSuccess; -ThreadState_t *pxThreadState = NULL; -SYSTEM_INFO xSystemInfo; + void * pvHandle = NULL; + int32_t lSuccess; + ThreadState_t * pxThreadState = NULL; + SYSTEM_INFO xSystemInfo; /* This port runs windows threads with extremely high priority. All the - threads execute on the same core - to prevent locking up the host only start - if the host has multiple cores. */ + * threads execute on the same core - to prevent locking up the host only start + * if the host has multiple cores. */ GetSystemInfo( &xSystemInfo ); + if( xSystemInfo.dwNumberOfProcessors <= 1 ) { printf( "This version of the FreeRTOS Windows port can only be used on multi-core hosts.\r\n" ); @@ -277,7 +279,7 @@ SYSTEM_INFO xSystemInfo; lSuccess = pdPASS; /* The highest priority class is used to [try to] prevent other Windows - activity interfering with FreeRTOS timing too much. */ + * activity interfering with FreeRTOS timing too much. */ if( SetPriorityClass( GetCurrentProcess(), REALTIME_PRIORITY_CLASS ) == 0 ) { printf( "SetPriorityClass() failed\r\n" ); @@ -288,7 +290,7 @@ SYSTEM_INFO xSystemInfo; vPortSetInterruptHandler( portINTERRUPT_TICK, prvProcessTickInterrupt ); /* Create the events and mutexes that are used to synchronise all the - threads. */ + * threads. */ pvInterruptEventMutex = CreateMutex( NULL, FALSE, NULL ); pvInterruptEvent = CreateEvent( NULL, FALSE, FALSE, NULL ); @@ -298,9 +300,10 @@ SYSTEM_INFO xSystemInfo; } /* Set the priority of this thread such that it is above the priority of - the threads that run tasks. This higher priority is required to ensure - simulated interrupts take priority over tasks. */ + * the threads that run tasks. This higher priority is required to ensure + * simulated interrupts take priority over tasks. */ pvHandle = GetCurrentThread(); + if( pvHandle == NULL ) { lSuccess = pdFAIL; @@ -313,6 +316,7 @@ SYSTEM_INFO xSystemInfo; { lSuccess = pdFAIL; } + SetThreadPriorityBoost( pvHandle, TRUE ); SetThreadAffinityMask( pvHandle, 0x01 ); } @@ -320,10 +324,11 @@ SYSTEM_INFO xSystemInfo; if( lSuccess == pdPASS ) { /* Start the thread that simulates the timer peripheral to generate - tick interrupts. The priority is set below that of the simulated - interrupt handler so the interrupt event mutex is used for the - handshake / overrun protection. */ + * tick interrupts. The priority is set below that of the simulated + * interrupt handler so the interrupt event mutex is used for the + * handshake / overrun protection. */ pvHandle = CreateThread( NULL, 0, prvSimulatedPeripheralTimer, NULL, CREATE_SUSPENDED, NULL ); + if( pvHandle != NULL ) { SetThreadPriority( pvHandle, portSIMULATED_TIMER_THREAD_PRIORITY ); @@ -333,20 +338,23 @@ SYSTEM_INFO xSystemInfo; } /* Start the highest priority task by obtaining its associated thread - state structure, in which is stored the thread handle. */ + * state structure, in which is stored the thread handle. */ pxThreadState = ( ThreadState_t * ) *( ( size_t * ) pxCurrentTCB ); ulCriticalNesting = portNO_CRITICAL_NESTING; /* Start the first task. */ ResumeThread( pxThreadState->pvThread ); + /* The scheduler is now running. */ + xPortRunning = pdTRUE; + /* Handle all simulated interrupts - including yield requests and - simulated ticks. */ + * simulated ticks. */ prvProcessSimulatedInterrupts(); } /* Would not expect to return from prvProcessSimulatedInterrupts(), so should - not get here. */ + * not get here. */ return 0; } /*-----------------------------------------------------------*/ @@ -360,7 +368,7 @@ static uint32_t prvProcessYieldInterrupt( void ) static uint32_t prvProcessTickInterrupt( void ) { -uint32_t ulSwitchRequired; + uint32_t ulSwitchRequired; /* Process the tick itself. */ configASSERT( xPortRunning ); @@ -372,148 +380,154 @@ uint32_t ulSwitchRequired; static void prvProcessSimulatedInterrupts( void ) { -uint32_t ulSwitchRequired, i; -ThreadState_t *pxThreadState; -void *pvObjectList[ 2 ]; -CONTEXT xContext; + uint32_t ulSwitchRequired, i; + ThreadState_t * pxThreadState; + void * pvObjectList[ 2 ]; + CONTEXT xContext; + DWORD xWinApiResult; + const DWORD xTimeoutMilliseconds = 1000; /* Going to block on the mutex that ensured exclusive access to the simulated - interrupt objects, and the event that signals that a simulated interrupt - should be processed. */ + * interrupt objects, and the event that signals that a simulated interrupt + * should be processed. */ pvObjectList[ 0 ] = pvInterruptEventMutex; pvObjectList[ 1 ] = pvInterruptEvent; /* Create a pending tick to ensure the first task is started as soon as - this thread pends. */ + * this thread pends. */ ulPendingInterrupts |= ( 1 << portINTERRUPT_TICK ); SetEvent( pvInterruptEvent ); - xPortRunning = pdTRUE; - - for(;;) + while( xPortRunning == pdTRUE ) { xInsideInterrupt = pdFALSE; - WaitForMultipleObjects( sizeof( pvObjectList ) / sizeof( void * ), pvObjectList, TRUE, INFINITE ); - - /* Cannot be in a critical section to get here. Tasks that exit a - critical section will block on a yield mutex to wait for an interrupt to - process if an interrupt was set pending while the task was inside the - critical section. xInsideInterrupt prevents interrupts that contain - critical sections from doing the same. */ - xInsideInterrupt = pdTRUE; - - /* Used to indicate whether the simulated interrupt processing has - necessitated a context switch to another task/thread. */ - ulSwitchRequired = pdFALSE; - - /* For each interrupt we are interested in processing, each of which is - represented by a bit in the 32bit ulPendingInterrupts variable. */ - for( i = 0; i < portMAX_INTERRUPTS; i++ ) + + /* Wait with timeout so that we can exit from this loop when + * the scheduler is stopped by calling vPortEndScheduler. */ + xWinApiResult = WaitForMultipleObjects( sizeof( pvObjectList ) / sizeof( void * ), pvObjectList, TRUE, xTimeoutMilliseconds ); + + if( xWinApiResult != WAIT_TIMEOUT ) { - /* Is the simulated interrupt pending? */ - if( ( ulPendingInterrupts & ( 1UL << i ) ) != 0 ) + /* Cannot be in a critical section to get here. Tasks that exit a + * critical section will block on a yield mutex to wait for an interrupt to + * process if an interrupt was set pending while the task was inside the + * critical section. xInsideInterrupt prevents interrupts that contain + * critical sections from doing the same. */ + xInsideInterrupt = pdTRUE; + + /* Used to indicate whether the simulated interrupt processing has + * necessitated a context switch to another task/thread. */ + ulSwitchRequired = pdFALSE; + + /* For each interrupt we are interested in processing, each of which is + * represented by a bit in the 32bit ulPendingInterrupts variable. */ + for( i = 0; i < portMAX_INTERRUPTS; i++ ) { - /* Is a handler installed? */ - if( ulIsrHandler[ i ] != NULL ) + /* Is the simulated interrupt pending? */ + if( ( ulPendingInterrupts & ( 1UL << i ) ) != 0 ) { - /* Run the actual handler. Handlers return pdTRUE if they - necessitate a context switch. */ - if( ulIsrHandler[ i ]() != pdFALSE ) + /* Is a handler installed? */ + if( ulIsrHandler[ i ] != NULL ) { - /* A bit mask is used purely to help debugging. */ - ulSwitchRequired |= ( 1 << i ); + /* Run the actual handler. Handlers return pdTRUE if they + * necessitate a context switch. */ + if( ulIsrHandler[ i ]() != pdFALSE ) + { + /* A bit mask is used purely to help debugging. */ + ulSwitchRequired |= ( 1 << i ); + } } - } - /* Clear the interrupt pending bit. */ - ulPendingInterrupts &= ~( 1UL << i ); + /* Clear the interrupt pending bit. */ + ulPendingInterrupts &= ~( 1UL << i ); + } } - } - if( ulSwitchRequired != pdFALSE ) - { - void *pvOldCurrentTCB; + if( ulSwitchRequired != pdFALSE ) + { + void * pvOldCurrentTCB; - pvOldCurrentTCB = pxCurrentTCB; + pvOldCurrentTCB = pxCurrentTCB; - /* Select the next task to run. */ - vTaskSwitchContext(); + /* Select the next task to run. */ + vTaskSwitchContext(); - /* If the task selected to enter the running state is not the task - that is already in the running state. */ - if( pvOldCurrentTCB != pxCurrentTCB ) - { - /* Suspend the old thread. In the cases where the (simulated) - interrupt is asynchronous (tick event swapping a task out rather - than a task blocking or yielding) it doesn't matter if the - 'suspend' operation doesn't take effect immediately - if it - doesn't it would just be like the interrupt occurring slightly - later. In cases where the yield was caused by a task blocking - or yielding then the task will block on a yield event after the - yield operation in case the 'suspend' operation doesn't take - effect immediately. */ - pxThreadState = ( ThreadState_t *) *( ( size_t * ) pvOldCurrentTCB ); - SuspendThread( pxThreadState->pvThread ); - - /* Ensure the thread is actually suspended by performing a - synchronous operation that can only complete when the thread is - actually suspended. The below code asks for dummy register - data. Experimentation shows that these two lines don't appear - to do anything now, but according to - https://devblogs.microsoft.com/oldnewthing/20150205-00/?p=44743 - they do - so as they do not harm (slight run-time hit). */ - xContext.ContextFlags = CONTEXT_INTEGER; - ( void ) GetThreadContext( pxThreadState->pvThread, &xContext ); - - /* Obtain the state of the task now selected to enter the - Running state. */ - pxThreadState = ( ThreadState_t * ) ( *( size_t *) pxCurrentTCB ); - - /* pxThreadState->pvThread can be NULL if the task deleted - itself - but a deleted task should never be resumed here. */ - configASSERT( pxThreadState->pvThread != NULL ); - ResumeThread( pxThreadState->pvThread ); + /* If the task selected to enter the running state is not the task + * that is already in the running state. */ + if( pvOldCurrentTCB != pxCurrentTCB ) + { + /* Suspend the old thread. In the cases where the (simulated) + * interrupt is asynchronous (tick event swapping a task out rather + * than a task blocking or yielding) it doesn't matter if the + * 'suspend' operation doesn't take effect immediately - if it + * doesn't it would just be like the interrupt occurring slightly + * later. In cases where the yield was caused by a task blocking + * or yielding then the task will block on a yield event after the + * yield operation in case the 'suspend' operation doesn't take + * effect immediately. */ + pxThreadState = ( ThreadState_t * ) *( ( size_t * ) pvOldCurrentTCB ); + SuspendThread( pxThreadState->pvThread ); + + /* Ensure the thread is actually suspended by performing a + * synchronous operation that can only complete when the thread is + * actually suspended. The below code asks for dummy register + * data. Experimentation shows that these two lines don't appear + * to do anything now, but according to + * https://devblogs.microsoft.com/oldnewthing/20150205-00/?p=44743 + * they do - so as they do not harm (slight run-time hit). */ + xContext.ContextFlags = CONTEXT_INTEGER; + ( void ) GetThreadContext( pxThreadState->pvThread, &xContext ); + + /* Obtain the state of the task now selected to enter the + * Running state. */ + pxThreadState = ( ThreadState_t * ) ( *( size_t * ) pxCurrentTCB ); + + /* pxThreadState->pvThread can be NULL if the task deleted + * itself - but a deleted task should never be resumed here. */ + configASSERT( pxThreadState->pvThread != NULL ); + ResumeThread( pxThreadState->pvThread ); + } } - } - /* If the thread that is about to be resumed stopped running - because it yielded then it will wait on an event when it resumed - (to ensure it does not continue running after the call to - SuspendThread() above as SuspendThread() is asynchronous). - Signal the event to ensure the thread can proceed now it is - valid for it to do so. Signaling the event is benign in the case that - the task was switched out asynchronously by an interrupt as the event - is reset before the task blocks on it. */ - pxThreadState = ( ThreadState_t * ) ( *( size_t *) pxCurrentTCB ); - SetEvent( pxThreadState->pvYieldEvent ); - ReleaseMutex( pvInterruptEventMutex ); + /* If the thread that is about to be resumed stopped running + * because it yielded then it will wait on an event when it resumed + * (to ensure it does not continue running after the call to + * SuspendThread() above as SuspendThread() is asynchronous). + * Signal the event to ensure the thread can proceed now it is + * valid for it to do so. Signaling the event is benign in the case that + * the task was switched out asynchronously by an interrupt as the event + * is reset before the task blocks on it. */ + pxThreadState = ( ThreadState_t * ) ( *( size_t * ) pxCurrentTCB ); + SetEvent( pxThreadState->pvYieldEvent ); + ReleaseMutex( pvInterruptEventMutex ); + } } } /*-----------------------------------------------------------*/ -void vPortDeleteThread( void *pvTaskToDelete ) +void vPortDeleteThread( void * pvTaskToDelete ) { -ThreadState_t *pxThreadState; -uint32_t ulErrorCode; + ThreadState_t * pxThreadState; + uint32_t ulErrorCode; /* Remove compiler warnings if configASSERT() is not defined. */ ( void ) ulErrorCode; /* Find the handle of the thread being deleted. */ - pxThreadState = ( ThreadState_t * ) ( *( size_t *) pvTaskToDelete ); + pxThreadState = ( ThreadState_t * ) ( *( size_t * ) pvTaskToDelete ); /* Check that the thread is still valid, it might have been closed by - vPortCloseRunningThread() - which will be the case if the task associated - with the thread originally deleted itself rather than being deleted by a - different task. */ + * vPortCloseRunningThread() - which will be the case if the task associated + * with the thread originally deleted itself rather than being deleted by a + * different task. */ if( pxThreadState->pvThread != NULL ) { WaitForSingleObject( pvInterruptEventMutex, INFINITE ); /* !!! This is not a nice way to terminate a thread, and will eventually - result in resources being depleted if tasks frequently delete other - tasks (rather than deleting themselves) as the task stacks will not be - freed. */ + * result in resources being depleted if tasks frequently delete other + * tasks (rather than deleting themselves) as the task stacks will not be + * freed. */ ulErrorCode = TerminateThread( pxThreadState->pvThread, 0 ); configASSERT( ulErrorCode ); @@ -525,31 +539,32 @@ uint32_t ulErrorCode; } /*-----------------------------------------------------------*/ -void vPortCloseRunningThread( void *pvTaskToDelete, volatile BaseType_t *pxPendYield ) +void vPortCloseRunningThread( void * pvTaskToDelete, + volatile BaseType_t * pxPendYield ) { -ThreadState_t *pxThreadState; -void *pvThread; -uint32_t ulErrorCode; + ThreadState_t * pxThreadState; + void * pvThread; + uint32_t ulErrorCode; /* Remove compiler warnings if configASSERT() is not defined. */ ( void ) ulErrorCode; /* Find the handle of the thread being deleted. */ - pxThreadState = ( ThreadState_t * ) ( *( size_t *) pvTaskToDelete ); + pxThreadState = ( ThreadState_t * ) ( *( size_t * ) pvTaskToDelete ); pvThread = pxThreadState->pvThread; /* Raise the Windows priority of the thread to ensure the FreeRTOS scheduler - does not run and swap it out before it is closed. If that were to happen - the thread would never run again and effectively be a thread handle and - memory leak. */ + * does not run and swap it out before it is closed. If that were to happen + * the thread would never run again and effectively be a thread handle and + * memory leak. */ SetThreadPriority( pvThread, portDELETE_SELF_THREAD_PRIORITY ); /* This function will not return, therefore a yield is set as pending to - ensure a context switch occurs away from this thread on the next tick. */ + * ensure a context switch occurs away from this thread on the next tick. */ *pxPendYield = pdTRUE; /* Mark the thread associated with this task as invalid so - vPortDeleteThread() does not try to terminate it. */ + * vPortDeleteThread() does not try to terminate it. */ pxThreadState->pvThread = NULL; /* Close the thread. */ @@ -557,7 +572,7 @@ uint32_t ulErrorCode; configASSERT( ulErrorCode ); /* This is called from a critical section, which must be exited before the - thread stops. */ + * thread stops. */ taskEXIT_CRITICAL(); CloseHandle( pxThreadState->pvYieldEvent ); ExitThread( 0 ); @@ -572,7 +587,7 @@ void vPortEndScheduler( void ) void vPortGenerateSimulatedInterrupt( uint32_t ulInterruptNumber ) { -ThreadState_t *pxThreadState = ( ThreadState_t *) *( ( size_t * ) pxCurrentTCB ); + ThreadState_t * pxThreadState = ( ThreadState_t * ) *( ( size_t * ) pxCurrentTCB ); configASSERT( xPortRunning ); @@ -582,34 +597,36 @@ ThreadState_t *pxThreadState = ( ThreadState_t *) *( ( size_t * ) pxCurrentTCB ) ulPendingInterrupts |= ( 1 << ulInterruptNumber ); /* The simulated interrupt is now held pending, but don't actually - process it yet if this call is within a critical section. It is - possible for this to be in a critical section as calls to wait for - mutexes are accumulative. If in a critical section then the event - will get set when the critical section nesting count is wound back - down to zero. */ + * process it yet if this call is within a critical section. It is + * possible for this to be in a critical section as calls to wait for + * mutexes are accumulative. If in a critical section then the event + * will get set when the critical section nesting count is wound back + * down to zero. */ if( ulCriticalNesting == portNO_CRITICAL_NESTING ) { SetEvent( pvInterruptEvent ); /* Going to wait for an event - make sure the event is not already - signaled. */ + * signaled. */ ResetEvent( pxThreadState->pvYieldEvent ); } ReleaseMutex( pvInterruptEventMutex ); + if( ulCriticalNesting == portNO_CRITICAL_NESTING ) { /* An interrupt was pended so ensure to block to allow it to - execute. In most cases the (simulated) interrupt will have - executed before the next line is reached - so this is just to make - sure. */ + * execute. In most cases the (simulated) interrupt will have + * executed before the next line is reached - so this is just to make + * sure. */ WaitForSingleObject( pxThreadState->pvYieldEvent, INFINITE ); } } } /*-----------------------------------------------------------*/ -void vPortSetInterruptHandler( uint32_t ulInterruptNumber, uint32_t (*pvHandler)( void ) ) +void vPortSetInterruptHandler( uint32_t ulInterruptNumber, + uint32_t ( * pvHandler )( void ) ) { if( ulInterruptNumber < portMAX_INTERRUPTS ) { @@ -632,7 +649,7 @@ void vPortEnterCritical( void ) if( xPortRunning == pdTRUE ) { /* The interrupt event mutex is held for the entire critical section, - effectively disabling (simulated) interrupts. */ + * effectively disabling (simulated) interrupts. */ WaitForSingleObject( pvInterruptEventMutex, INFINITE ); } @@ -642,10 +659,10 @@ void vPortEnterCritical( void ) void vPortExitCritical( void ) { -int32_t lMutexNeedsReleasing; + int32_t lMutexNeedsReleasing; /* The interrupt event mutex should already be held by this thread as it was - obtained on entry to the critical section. */ + * obtained on entry to the critical section. */ lMutexNeedsReleasing = pdTRUE; if( ulCriticalNesting > portNO_CRITICAL_NESTING ) @@ -653,33 +670,34 @@ int32_t lMutexNeedsReleasing; ulCriticalNesting--; /* Don't need to wait for any pending interrupts to execute if the - critical section was exited from inside an interrupt. */ + * critical section was exited from inside an interrupt. */ if( ( ulCriticalNesting == portNO_CRITICAL_NESTING ) && ( xInsideInterrupt == pdFALSE ) ) { /* Were any interrupts set to pending while interrupts were - (simulated) disabled? */ + * (simulated) disabled? */ if( ulPendingInterrupts != 0UL ) { - ThreadState_t *pxThreadState = ( ThreadState_t *) *( ( size_t * ) pxCurrentTCB ); + ThreadState_t * pxThreadState = ( ThreadState_t * ) *( ( size_t * ) pxCurrentTCB ); configASSERT( xPortRunning ); /* The interrupt won't actually executed until - pvInterruptEventMutex is released as it waits on both - pvInterruptEventMutex and pvInterruptEvent. - pvInterruptEvent is only set when the simulated - interrupt is pended if the interrupt is pended - from outside a critical section - hence it is set - here. */ + * pvInterruptEventMutex is released as it waits on both + * pvInterruptEventMutex and pvInterruptEvent. + * pvInterruptEvent is only set when the simulated + * interrupt is pended if the interrupt is pended + * from outside a critical section - hence it is set + * here. */ SetEvent( pvInterruptEvent ); + /* The calling task is going to wait for an event to ensure the - interrupt that is pending executes immediately after the - critical section is exited - so make sure the event is not - already signaled. */ + * interrupt that is pending executes immediately after the + * critical section is exited - so make sure the event is not + * already signaled. */ ResetEvent( pxThreadState->pvYieldEvent ); /* Mutex will be released now so the (simulated) interrupt can - execute, so does not require releasing on function exit. */ + * execute, so does not require releasing on function exit. */ lMutexNeedsReleasing = pdFALSE; ReleaseMutex( pvInterruptEventMutex ); WaitForSingleObject( pxThreadState->pvYieldEvent, INFINITE ); diff --git a/Source/portable/MSVC-MingW/portmacro.h b/Source/portable/MSVC-MingW/portmacro.h index c79e57bfe..601c70d91 100644 --- a/Source/portable/MSVC-MingW/portmacro.h +++ b/Source/portable/MSVC-MingW/portmacro.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -29,104 +29,121 @@ #ifndef PORTMACRO_H #define PORTMACRO_H +#ifdef WIN32_LEAN_AND_MEAN + #include +#else + #include +#endif + #include +#include +#include #include /****************************************************************************** - Defines +* Defines ******************************************************************************/ /* Type definitions. */ -#define portCHAR char -#define portFLOAT float -#define portDOUBLE double -#define portLONG long -#define portSHORT short -#define portSTACK_TYPE size_t -#define portBASE_TYPE long -#define portPOINTER_SIZE_TYPE size_t - -typedef portSTACK_TYPE StackType_t; -typedef long BaseType_t; -typedef unsigned long UBaseType_t; - - -#if( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS ) - typedef uint16_t TickType_t; - #define portMAX_DELAY ( TickType_t ) 0xffff +#define portCHAR char +#define portFLOAT float +#define portDOUBLE double +#define portLONG long +#define portSHORT short +#define portSTACK_TYPE size_t +#define portPOINTER_SIZE_TYPE size_t + +typedef portSTACK_TYPE StackType_t; + +#if defined( __x86_64__ ) || defined( _M_X64 ) + #define portBASE_TYPE long long + typedef long long BaseType_t; + typedef unsigned long long UBaseType_t; +#else + #define portBASE_TYPE long + typedef long BaseType_t; + typedef unsigned long UBaseType_t; +#endif + + +#if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS ) + typedef uint16_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffff #elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS ) - typedef uint32_t TickType_t; - #define portMAX_DELAY ( TickType_t ) 0xffffffffUL + typedef uint32_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffffffffUL - /* 32/64-bit tick type on a 32/64-bit architecture, so reads of the tick - count do not need to be guarded with a critical section. */ - #define portTICK_TYPE_IS_ATOMIC 1 +/* 32/64-bit tick type on a 32/64-bit architecture, so reads of the tick + * count do not need to be guarded with a critical section. */ + #define portTICK_TYPE_IS_ATOMIC 1 #else #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width. #endif /* Hardware specifics. */ -#define portSTACK_GROWTH ( -1 ) -#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) -#define portINLINE __inline +#define portSTACK_GROWTH ( -1 ) +#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) +#define portINLINE __inline -#if defined( __x86_64__) || defined( _M_X64 ) - #define portBYTE_ALIGNMENT 8 +#if defined( __x86_64__ ) || defined( _M_X64 ) + #define portBYTE_ALIGNMENT 8 #else - #define portBYTE_ALIGNMENT 4 + #define portBYTE_ALIGNMENT 4 #endif -#define portYIELD() vPortGenerateSimulatedInterrupt( portINTERRUPT_YIELD ) +#define portYIELD() vPortGenerateSimulatedInterrupt( portINTERRUPT_YIELD ) extern volatile BaseType_t xInsideInterrupt; -#define portSOFTWARE_BARRIER() while( xInsideInterrupt != pdFALSE ) +#define portSOFTWARE_BARRIER() while( xInsideInterrupt != pdFALSE ) /* Simulated interrupts return pdFALSE if no context switch should be performed, -or a non-zero number if a context switch should be performed. */ -#define portYIELD_FROM_ISR( x ) ( void ) x -#define portEND_SWITCHING_ISR( x ) portYIELD_FROM_ISR( ( x ) ) - -void vPortCloseRunningThread( void *pvTaskToDelete, volatile BaseType_t *pxPendYield ); -void vPortDeleteThread( void *pvThreadToDelete ); -#define portCLEAN_UP_TCB( pxTCB ) vPortDeleteThread( pxTCB ) -#define portPRE_TASK_DELETE_HOOK( pvTaskToDelete, pxPendYield ) vPortCloseRunningThread( ( pvTaskToDelete ), ( pxPendYield ) ) -#define portDISABLE_INTERRUPTS() vPortEnterCritical() -#define portENABLE_INTERRUPTS() vPortExitCritical() + * or a non-zero number if a context switch should be performed. */ +#define portYIELD_FROM_ISR( x ) ( void ) x +#define portEND_SWITCHING_ISR( x ) portYIELD_FROM_ISR( ( x ) ) + +void vPortCloseRunningThread( void * pvTaskToDelete, + volatile BaseType_t * pxPendYield ); +void vPortDeleteThread( void * pvThreadToDelete ); +#define portCLEAN_UP_TCB( pxTCB ) vPortDeleteThread( pxTCB ) +#define portPRE_TASK_DELETE_HOOK( pvTaskToDelete, pxPendYield ) vPortCloseRunningThread( ( pvTaskToDelete ), ( pxPendYield ) ) +#define portDISABLE_INTERRUPTS() vPortEnterCritical() +#define portENABLE_INTERRUPTS() vPortExitCritical() /* Critical section handling. */ void vPortEnterCritical( void ); void vPortExitCritical( void ); -#define portENTER_CRITICAL() vPortEnterCritical() -#define portEXIT_CRITICAL() vPortExitCritical() +#define portENTER_CRITICAL() vPortEnterCritical() +#define portEXIT_CRITICAL() vPortExitCritical() #ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION - #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1 + #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1 #endif #if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 - /* Check the configuration. */ - #if( configMAX_PRIORITIES > 32 ) +/* Check the configuration. */ + #if ( configMAX_PRIORITIES > 32 ) #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice. #endif - /* Store/clear the ready priorities in a bit map. */ - #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) ) - #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) ) +/* Store/clear the ready priorities in a bit map. */ + #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) ) + #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) ) - /*-----------------------------------------------------------*/ +/*-----------------------------------------------------------*/ #ifdef __GNUC__ - #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) \ - __asm volatile( "bsr %1, %0\n\t" \ - :"=r"(uxTopPriority) : "rm"(uxReadyPriorities) : "cc" ) + #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) \ + __asm volatile ( "bsr %1, %0\n\t" \ + : "=r" ( uxTopPriority ) : "rm" ( uxReadyPriorities ) : "cc" ) #else - /* BitScanReverse returns the bit position of the most significant '1' - in the word. */ - #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) _BitScanReverse( ( DWORD * ) &( uxTopPriority ), ( uxReadyPriorities ) ) + +/* BitScanReverse returns the bit position of the most significant '1' + * in the word. */ + #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) _BitScanReverse( ( DWORD * ) &( uxTopPriority ), ( uxReadyPriorities ) ) #endif /* __GNUC__ */ #endif /* taskRECORD_READY_PRIORITY */ @@ -137,17 +154,17 @@ void vPortExitCritical( void ); /* Task function macros as described on the FreeRTOS.org WEB site. */ -#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters ) -#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters ) +#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters ) +#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters ) -#define portINTERRUPT_YIELD ( 0UL ) -#define portINTERRUPT_TICK ( 1UL ) +#define portINTERRUPT_YIELD ( 0UL ) +#define portINTERRUPT_TICK ( 1UL ) /* * Raise a simulated interrupt represented by the bit mask in ulInterruptMask. * Each bit can be used to represent an individual interrupt - with the first * two bits being used for the Yield and Tick interrupts respectively. -*/ + */ void vPortGenerateSimulatedInterrupt( uint32_t ulInterruptNumber ); /* @@ -159,6 +176,7 @@ void vPortGenerateSimulatedInterrupt( uint32_t ulInterruptNumber ); * Interrupt handler functions must return a non-zero value if executing the * handler resulted in a task switch being required. */ -void vPortSetInterruptHandler( uint32_t ulInterruptNumber, uint32_t (*pvHandler)( void ) ); +void vPortSetInterruptHandler( uint32_t ulInterruptNumber, + uint32_t ( * pvHandler )( void ) ); -#endif +#endif /* ifndef PORTMACRO_H */ diff --git a/Source/portable/MemMang/heap_1.c b/Source/portable/MemMang/heap_1.c index da11bfcc5..4da8de50f 100644 --- a/Source/portable/MemMang/heap_1.c +++ b/Source/portable/MemMang/heap_1.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/Source/portable/MemMang/heap_2.c b/Source/portable/MemMang/heap_2.c index 9f363f151..2f37e5c59 100644 --- a/Source/portable/MemMang/heap_2.c +++ b/Source/portable/MemMang/heap_2.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -103,8 +103,8 @@ typedef struct A_BLOCK_LINK } BlockLink_t; -static const uint16_t heapSTRUCT_SIZE = ( ( sizeof( BlockLink_t ) + ( portBYTE_ALIGNMENT - 1 ) ) & ~( ( size_t ) portBYTE_ALIGNMENT_MASK ) ); -#define heapMINIMUM_BLOCK_SIZE ( ( size_t ) ( heapSTRUCT_SIZE * 2 ) ) +static const size_t xHeapStructSize = ( ( sizeof( BlockLink_t ) + ( size_t ) ( portBYTE_ALIGNMENT - 1 ) ) & ~( ( size_t ) portBYTE_ALIGNMENT_MASK ) ); +#define heapMINIMUM_BLOCK_SIZE ( ( size_t ) ( xHeapStructSize * 2 ) ) /* Create a couple of list links to mark the start and end of the list. */ PRIVILEGED_DATA static BlockLink_t xStart, xEnd; @@ -159,32 +159,54 @@ void * pvPortMalloc( size_t xWantedSize ) void * pvReturn = NULL; size_t xAdditionalRequiredSize; - vTaskSuspendAll(); + if( xWantedSize > 0 ) { - /* If this is the first call to malloc then the heap will require - * initialisation to setup the list of free blocks. */ - if( xHeapHasBeenInitialised == pdFALSE ) + /* The wanted size must be increased so it can contain a BlockLink_t + * structure in addition to the requested amount of bytes. */ + if( heapADD_WILL_OVERFLOW( xWantedSize, xHeapStructSize ) == 0 ) { - prvHeapInit(); - xHeapHasBeenInitialised = pdTRUE; - } + xWantedSize += xHeapStructSize; - if( xWantedSize > 0 ) - { - /* The wanted size must be increased so it can contain a BlockLink_t - * structure in addition to the requested amount of bytes. Some - * additional increment may also be needed for alignment. */ - xAdditionalRequiredSize = heapSTRUCT_SIZE + portBYTE_ALIGNMENT - ( xWantedSize & portBYTE_ALIGNMENT_MASK ); - - if( heapADD_WILL_OVERFLOW( xWantedSize, xAdditionalRequiredSize ) == 0 ) + /* Ensure that blocks are always aligned to the required number + * of bytes. */ + if( ( xWantedSize & portBYTE_ALIGNMENT_MASK ) != 0x00 ) { - xWantedSize += xAdditionalRequiredSize; + /* Byte alignment required. */ + xAdditionalRequiredSize = portBYTE_ALIGNMENT - ( xWantedSize & portBYTE_ALIGNMENT_MASK ); + + if( heapADD_WILL_OVERFLOW( xWantedSize, xAdditionalRequiredSize ) == 0 ) + { + xWantedSize += xAdditionalRequiredSize; + } + else + { + xWantedSize = 0; + } } else { - xWantedSize = 0; + mtCOVERAGE_TEST_MARKER(); } } + else + { + xWantedSize = 0; + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + vTaskSuspendAll(); + { + /* If this is the first call to malloc then the heap will require + * initialisation to setup the list of free blocks. */ + if( xHeapHasBeenInitialised == pdFALSE ) + { + prvHeapInit(); + xHeapHasBeenInitialised = pdTRUE; + } /* Check the block size we are trying to allocate is not so large that the * top bit is set. The top bit of the block size member of the BlockLink_t @@ -210,7 +232,7 @@ void * pvPortMalloc( size_t xWantedSize ) { /* Return the memory space - jumping over the BlockLink_t structure * at its start. */ - pvReturn = ( void * ) ( ( ( uint8_t * ) pxPreviousBlock->pxNextFreeBlock ) + heapSTRUCT_SIZE ); + pvReturn = ( void * ) ( ( ( uint8_t * ) pxPreviousBlock->pxNextFreeBlock ) + xHeapStructSize ); /* This block is being returned for use so must be taken out of the * list of free blocks. */ @@ -229,7 +251,9 @@ void * pvPortMalloc( size_t xWantedSize ) pxNewBlockLink->xBlockSize = pxBlock->xBlockSize - xWantedSize; pxBlock->xBlockSize = xWantedSize; - /* Insert the new block into the list of free blocks. */ + /* Insert the new block into the list of free blocks. + * The list of free blocks is sorted by their size, we have to + * iterate to find the right place to insert new block. */ prvInsertBlockIntoFreeList( ( pxNewBlockLink ) ); } @@ -269,7 +293,7 @@ void vPortFree( void * pv ) { /* The memory being freed will have an BlockLink_t structure immediately * before it. */ - puc -= heapSTRUCT_SIZE; + puc -= xHeapStructSize; /* This unexpected casting is to keep some compilers from issuing * byte alignment warnings. */ @@ -287,7 +311,7 @@ void vPortFree( void * pv ) heapFREE_BLOCK( pxLink ); #if ( configHEAP_CLEAR_MEMORY_ON_FREE == 1 ) { - ( void ) memset( puc + heapSTRUCT_SIZE, 0, pxLink->xBlockSize - heapSTRUCT_SIZE ); + ( void ) memset( puc + xHeapStructSize, 0, pxLink->xBlockSize - xHeapStructSize ); } #endif diff --git a/Source/portable/MemMang/heap_3.c b/Source/portable/MemMang/heap_3.c index f0ecc9600..0b43ede6c 100644 --- a/Source/portable/MemMang/heap_3.c +++ b/Source/portable/MemMang/heap_3.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/Source/portable/MemMang/heap_4.c b/Source/portable/MemMang/heap_4.c index 013364f30..d2914bb79 100644 --- a/Source/portable/MemMang/heap_4.c +++ b/Source/portable/MemMang/heap_4.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -65,10 +65,13 @@ #define heapSIZE_MAX ( ~( ( size_t ) 0 ) ) /* Check if multiplying a and b will result in overflow. */ -#define heapMULTIPLY_WILL_OVERFLOW( a, b ) ( ( ( a ) > 0 ) && ( ( b ) > ( heapSIZE_MAX / ( a ) ) ) ) +#define heapMULTIPLY_WILL_OVERFLOW( a, b ) ( ( ( a ) > 0 ) && ( ( b ) > ( heapSIZE_MAX / ( a ) ) ) ) /* Check if adding a and b will result in overflow. */ -#define heapADD_WILL_OVERFLOW( a, b ) ( ( a ) > ( heapSIZE_MAX - ( b ) ) ) +#define heapADD_WILL_OVERFLOW( a, b ) ( ( a ) > ( heapSIZE_MAX - ( b ) ) ) + +/* Check if the subtraction operation ( a - b ) will result in underflow. */ +#define heapSUBTRACT_WILL_UNDERFLOW( a, b ) ( ( a ) < ( b ) ) /* MSB of the xBlockSize member of an BlockLink_t structure is used to track * the allocation status of a block. When MSB of the xBlockSize member of @@ -100,6 +103,38 @@ typedef struct A_BLOCK_LINK size_t xBlockSize; /**< The size of the free block. */ } BlockLink_t; +/* Setting configENABLE_HEAP_PROTECTOR to 1 enables heap block pointers + * protection using an application supplied canary value to catch heap + * corruption should a heap buffer overflow occur. + */ +#if ( configENABLE_HEAP_PROTECTOR == 1 ) + +/** + * @brief Application provided function to get a random value to be used as canary. + * + * @param pxHeapCanary [out] Output parameter to return the canary value. + */ + extern void vApplicationGetRandomHeapCanary( portPOINTER_SIZE_TYPE * pxHeapCanary ); + +/* Canary value for protecting internal heap pointers. */ + PRIVILEGED_DATA static portPOINTER_SIZE_TYPE xHeapCanary; + +/* Macro to load/store BlockLink_t pointers to memory. By XORing the + * pointers with a random canary value, heap overflows will result + * in randomly unpredictable pointer values which will be caught by + * heapVALIDATE_BLOCK_POINTER assert. */ + #define heapPROTECT_BLOCK_POINTER( pxBlock ) ( ( BlockLink_t * ) ( ( ( portPOINTER_SIZE_TYPE ) ( pxBlock ) ) ^ xHeapCanary ) ) +#else + + #define heapPROTECT_BLOCK_POINTER( pxBlock ) ( pxBlock ) + +#endif /* configENABLE_HEAP_PROTECTOR */ + +/* Assert that a heap block pointer is within the heap bounds. */ +#define heapVALIDATE_BLOCK_POINTER( pxBlock ) \ + configASSERT( ( ( uint8_t * ) ( pxBlock ) >= &( ucHeap[ 0 ] ) ) && \ + ( ( uint8_t * ) ( pxBlock ) <= &( ucHeap[ configTOTAL_HEAP_SIZE - 1 ] ) ) ) + /*-----------------------------------------------------------*/ /* @@ -143,54 +178,54 @@ void * pvPortMalloc( size_t xWantedSize ) void * pvReturn = NULL; size_t xAdditionalRequiredSize; - vTaskSuspendAll(); + if( xWantedSize > 0 ) { - /* If this is the first call to malloc then the heap will require - * initialisation to setup the list of free blocks. */ - if( pxEnd == NULL ) + /* The wanted size must be increased so it can contain a BlockLink_t + * structure in addition to the requested amount of bytes. */ + if( heapADD_WILL_OVERFLOW( xWantedSize, xHeapStructSize ) == 0 ) { - prvHeapInit(); - } - else - { - mtCOVERAGE_TEST_MARKER(); - } + xWantedSize += xHeapStructSize; - if( xWantedSize > 0 ) - { - /* The wanted size must be increased so it can contain a BlockLink_t - * structure in addition to the requested amount of bytes. */ - if( heapADD_WILL_OVERFLOW( xWantedSize, xHeapStructSize ) == 0 ) + /* Ensure that blocks are always aligned to the required number + * of bytes. */ + if( ( xWantedSize & portBYTE_ALIGNMENT_MASK ) != 0x00 ) { - xWantedSize += xHeapStructSize; + /* Byte alignment required. */ + xAdditionalRequiredSize = portBYTE_ALIGNMENT - ( xWantedSize & portBYTE_ALIGNMENT_MASK ); - /* Ensure that blocks are always aligned to the required number - * of bytes. */ - if( ( xWantedSize & portBYTE_ALIGNMENT_MASK ) != 0x00 ) + if( heapADD_WILL_OVERFLOW( xWantedSize, xAdditionalRequiredSize ) == 0 ) { - /* Byte alignment required. */ - xAdditionalRequiredSize = portBYTE_ALIGNMENT - ( xWantedSize & portBYTE_ALIGNMENT_MASK ); - - if( heapADD_WILL_OVERFLOW( xWantedSize, xAdditionalRequiredSize ) == 0 ) - { - xWantedSize += xAdditionalRequiredSize; - } - else - { - xWantedSize = 0; - } + xWantedSize += xAdditionalRequiredSize; } else { - mtCOVERAGE_TEST_MARKER(); + xWantedSize = 0; } } else { - xWantedSize = 0; + mtCOVERAGE_TEST_MARKER(); } } else + { + xWantedSize = 0; + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + vTaskSuspendAll(); + { + /* If this is the first call to malloc then the heap will require + * initialisation to setup the list of free blocks. */ + if( pxEnd == NULL ) + { + prvHeapInit(); + } + else { mtCOVERAGE_TEST_MARKER(); } @@ -206,12 +241,14 @@ void * pvPortMalloc( size_t xWantedSize ) /* Traverse the list from the start (lowest address) block until * one of adequate size is found. */ pxPreviousBlock = &xStart; - pxBlock = xStart.pxNextFreeBlock; + pxBlock = heapPROTECT_BLOCK_POINTER( xStart.pxNextFreeBlock ); + heapVALIDATE_BLOCK_POINTER( pxBlock ); - while( ( pxBlock->xBlockSize < xWantedSize ) && ( pxBlock->pxNextFreeBlock != NULL ) ) + while( ( pxBlock->xBlockSize < xWantedSize ) && ( pxBlock->pxNextFreeBlock != heapPROTECT_BLOCK_POINTER( NULL ) ) ) { pxPreviousBlock = pxBlock; - pxBlock = pxBlock->pxNextFreeBlock; + pxBlock = heapPROTECT_BLOCK_POINTER( pxBlock->pxNextFreeBlock ); + heapVALIDATE_BLOCK_POINTER( pxBlock ); } /* If the end marker was reached then a block of adequate size @@ -220,7 +257,8 @@ void * pvPortMalloc( size_t xWantedSize ) { /* Return the memory space pointed to - jumping over the * BlockLink_t structure at its start. */ - pvReturn = ( void * ) ( ( ( uint8_t * ) pxPreviousBlock->pxNextFreeBlock ) + xHeapStructSize ); + pvReturn = ( void * ) ( ( ( uint8_t * ) heapPROTECT_BLOCK_POINTER( pxPreviousBlock->pxNextFreeBlock ) ) + xHeapStructSize ); + heapVALIDATE_BLOCK_POINTER( pvReturn ); /* This block is being returned for use so must be taken out * of the list of free blocks. */ @@ -228,6 +266,8 @@ void * pvPortMalloc( size_t xWantedSize ) /* If the block is larger than required it can be split into * two. */ + configASSERT( heapSUBTRACT_WILL_UNDERFLOW( pxBlock->xBlockSize, xWantedSize ) == 0 ); + if( ( pxBlock->xBlockSize - xWantedSize ) > heapMINIMUM_BLOCK_SIZE ) { /* This block is to be split into two. Create a new @@ -243,7 +283,8 @@ void * pvPortMalloc( size_t xWantedSize ) pxBlock->xBlockSize = xWantedSize; /* Insert the new block into the list of free blocks. */ - prvInsertBlockIntoFreeList( pxNewBlockLink ); + pxNewBlockLink->pxNextFreeBlock = pxPreviousBlock->pxNextFreeBlock; + pxPreviousBlock->pxNextFreeBlock = heapPROTECT_BLOCK_POINTER( pxNewBlockLink ); } else { @@ -318,6 +359,7 @@ void vPortFree( void * pv ) /* This casting is to keep the compiler from issuing warnings. */ pxLink = ( void * ) puc; + heapVALIDATE_BLOCK_POINTER( pxLink ); configASSERT( heapBLOCK_IS_ALLOCATED( pxLink ) != 0 ); configASSERT( pxLink->pxNextFreeBlock == NULL ); @@ -330,7 +372,12 @@ void vPortFree( void * pv ) heapFREE_BLOCK( pxLink ); #if ( configHEAP_CLEAR_MEMORY_ON_FREE == 1 ) { - ( void ) memset( puc + xHeapStructSize, 0, pxLink->xBlockSize - xHeapStructSize ); + /* Check for underflow as this can occur if xBlockSize is + * overwritten in a heap block. */ + if( heapSUBTRACT_WILL_UNDERFLOW( pxLink->xBlockSize, xHeapStructSize ) == 0 ) + { + ( void ) memset( puc + xHeapStructSize, 0, pxLink->xBlockSize - xHeapStructSize ); + } } #endif @@ -397,41 +444,44 @@ void * pvPortCalloc( size_t xNum, static void prvHeapInit( void ) /* PRIVILEGED_FUNCTION */ { BlockLink_t * pxFirstFreeBlock; - uint8_t * pucAlignedHeap; - portPOINTER_SIZE_TYPE uxAddress; + portPOINTER_SIZE_TYPE uxStartAddress, uxEndAddress; size_t xTotalHeapSize = configTOTAL_HEAP_SIZE; /* Ensure the heap starts on a correctly aligned boundary. */ - uxAddress = ( portPOINTER_SIZE_TYPE ) ucHeap; + uxStartAddress = ( portPOINTER_SIZE_TYPE ) ucHeap; - if( ( uxAddress & portBYTE_ALIGNMENT_MASK ) != 0 ) + if( ( uxStartAddress & portBYTE_ALIGNMENT_MASK ) != 0 ) { - uxAddress += ( portBYTE_ALIGNMENT - 1 ); - uxAddress &= ~( ( portPOINTER_SIZE_TYPE ) portBYTE_ALIGNMENT_MASK ); - xTotalHeapSize -= ( size_t ) ( uxAddress - ( portPOINTER_SIZE_TYPE ) ucHeap ); + uxStartAddress += ( portBYTE_ALIGNMENT - 1 ); + uxStartAddress &= ~( ( portPOINTER_SIZE_TYPE ) portBYTE_ALIGNMENT_MASK ); + xTotalHeapSize -= ( size_t ) ( uxStartAddress - ( portPOINTER_SIZE_TYPE ) ucHeap ); } - pucAlignedHeap = ( uint8_t * ) uxAddress; + #if ( configENABLE_HEAP_PROTECTOR == 1 ) + { + vApplicationGetRandomHeapCanary( &( xHeapCanary ) ); + } + #endif /* xStart is used to hold a pointer to the first item in the list of free * blocks. The void cast is used to prevent compiler warnings. */ - xStart.pxNextFreeBlock = ( void * ) pucAlignedHeap; + xStart.pxNextFreeBlock = ( void * ) heapPROTECT_BLOCK_POINTER( uxStartAddress ); xStart.xBlockSize = ( size_t ) 0; /* pxEnd is used to mark the end of the list of free blocks and is inserted * at the end of the heap space. */ - uxAddress = ( portPOINTER_SIZE_TYPE ) ( pucAlignedHeap + xTotalHeapSize ); - uxAddress -= xHeapStructSize; - uxAddress &= ~( ( portPOINTER_SIZE_TYPE ) portBYTE_ALIGNMENT_MASK ); - pxEnd = ( BlockLink_t * ) uxAddress; + uxEndAddress = uxStartAddress + ( portPOINTER_SIZE_TYPE ) xTotalHeapSize; + uxEndAddress -= ( portPOINTER_SIZE_TYPE ) xHeapStructSize; + uxEndAddress &= ~( ( portPOINTER_SIZE_TYPE ) portBYTE_ALIGNMENT_MASK ); + pxEnd = ( BlockLink_t * ) uxEndAddress; pxEnd->xBlockSize = 0; - pxEnd->pxNextFreeBlock = NULL; + pxEnd->pxNextFreeBlock = heapPROTECT_BLOCK_POINTER( NULL ); /* To start with there is a single free block that is sized to take up the * entire heap space, minus the space taken by pxEnd. */ - pxFirstFreeBlock = ( BlockLink_t * ) pucAlignedHeap; - pxFirstFreeBlock->xBlockSize = ( size_t ) ( uxAddress - ( portPOINTER_SIZE_TYPE ) pxFirstFreeBlock ); - pxFirstFreeBlock->pxNextFreeBlock = pxEnd; + pxFirstFreeBlock = ( BlockLink_t * ) uxStartAddress; + pxFirstFreeBlock->xBlockSize = ( size_t ) ( uxEndAddress - ( portPOINTER_SIZE_TYPE ) pxFirstFreeBlock ); + pxFirstFreeBlock->pxNextFreeBlock = heapPROTECT_BLOCK_POINTER( pxEnd ); /* Only one block exists - and it covers the entire usable heap space. */ xMinimumEverFreeBytesRemaining = pxFirstFreeBlock->xBlockSize; @@ -446,11 +496,16 @@ static void prvInsertBlockIntoFreeList( BlockLink_t * pxBlockToInsert ) /* PRIVI /* Iterate through the list until a block is found that has a higher address * than the block being inserted. */ - for( pxIterator = &xStart; pxIterator->pxNextFreeBlock < pxBlockToInsert; pxIterator = pxIterator->pxNextFreeBlock ) + for( pxIterator = &xStart; heapPROTECT_BLOCK_POINTER( pxIterator->pxNextFreeBlock ) < pxBlockToInsert; pxIterator = heapPROTECT_BLOCK_POINTER( pxIterator->pxNextFreeBlock ) ) { /* Nothing to do here, just iterate to the right position. */ } + if( pxIterator != &xStart ) + { + heapVALIDATE_BLOCK_POINTER( pxIterator ); + } + /* Do the block being inserted, and the block it is being inserted after * make a contiguous block of memory? */ puc = ( uint8_t * ) pxIterator; @@ -469,17 +524,17 @@ static void prvInsertBlockIntoFreeList( BlockLink_t * pxBlockToInsert ) /* PRIVI * make a contiguous block of memory? */ puc = ( uint8_t * ) pxBlockToInsert; - if( ( puc + pxBlockToInsert->xBlockSize ) == ( uint8_t * ) pxIterator->pxNextFreeBlock ) + if( ( puc + pxBlockToInsert->xBlockSize ) == ( uint8_t * ) heapPROTECT_BLOCK_POINTER( pxIterator->pxNextFreeBlock ) ) { - if( pxIterator->pxNextFreeBlock != pxEnd ) + if( heapPROTECT_BLOCK_POINTER( pxIterator->pxNextFreeBlock ) != pxEnd ) { /* Form one big block from the two blocks. */ - pxBlockToInsert->xBlockSize += pxIterator->pxNextFreeBlock->xBlockSize; - pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock->pxNextFreeBlock; + pxBlockToInsert->xBlockSize += heapPROTECT_BLOCK_POINTER( pxIterator->pxNextFreeBlock )->xBlockSize; + pxBlockToInsert->pxNextFreeBlock = heapPROTECT_BLOCK_POINTER( pxIterator->pxNextFreeBlock )->pxNextFreeBlock; } else { - pxBlockToInsert->pxNextFreeBlock = pxEnd; + pxBlockToInsert->pxNextFreeBlock = heapPROTECT_BLOCK_POINTER( pxEnd ); } } else @@ -493,7 +548,7 @@ static void prvInsertBlockIntoFreeList( BlockLink_t * pxBlockToInsert ) /* PRIVI * to itself. */ if( pxIterator != pxBlockToInsert ) { - pxIterator->pxNextFreeBlock = pxBlockToInsert; + pxIterator->pxNextFreeBlock = heapPROTECT_BLOCK_POINTER( pxBlockToInsert ); } else { @@ -509,7 +564,7 @@ void vPortGetHeapStats( HeapStats_t * pxHeapStats ) vTaskSuspendAll(); { - pxBlock = xStart.pxNextFreeBlock; + pxBlock = heapPROTECT_BLOCK_POINTER( xStart.pxNextFreeBlock ); /* pxBlock will be NULL if the heap has not been initialised. The heap * is initialised automatically when the first allocation is made. */ @@ -533,7 +588,7 @@ void vPortGetHeapStats( HeapStats_t * pxHeapStats ) /* Move to the next block in the chain until the last block is * reached. */ - pxBlock = pxBlock->pxNextFreeBlock; + pxBlock = heapPROTECT_BLOCK_POINTER( pxBlock->pxNextFreeBlock ); } } } diff --git a/Source/portable/MemMang/heap_5.c b/Source/portable/MemMang/heap_5.c index 79b3a8a5b..49053c45b 100644 --- a/Source/portable/MemMang/heap_5.c +++ b/Source/portable/MemMang/heap_5.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -28,7 +28,7 @@ /* * A sample implementation of pvPortMalloc() that allows the heap to be defined - * across multiple non-contigous blocks and combines (coalescences) adjacent + * across multiple non-contiguous blocks and combines (coalescences) adjacent * memory blocks as they are freed. * * See heap_1.c, heap_2.c, heap_3.c and heap_4.c for alternative @@ -99,10 +99,13 @@ #define heapSIZE_MAX ( ~( ( size_t ) 0 ) ) /* Check if multiplying a and b will result in overflow. */ -#define heapMULTIPLY_WILL_OVERFLOW( a, b ) ( ( ( a ) > 0 ) && ( ( b ) > ( heapSIZE_MAX / ( a ) ) ) ) +#define heapMULTIPLY_WILL_OVERFLOW( a, b ) ( ( ( a ) > 0 ) && ( ( b ) > ( heapSIZE_MAX / ( a ) ) ) ) /* Check if adding a and b will result in overflow. */ -#define heapADD_WILL_OVERFLOW( a, b ) ( ( a ) > ( heapSIZE_MAX - ( b ) ) ) +#define heapADD_WILL_OVERFLOW( a, b ) ( ( a ) > ( heapSIZE_MAX - ( b ) ) ) + +/* Check if the subtraction operation ( a - b ) will result in underflow. */ +#define heapSUBTRACT_WILL_UNDERFLOW( a, b ) ( ( a ) < ( b ) ) /* MSB of the xBlockSize member of an BlockLink_t structure is used to track * the allocation status of a block. When MSB of the xBlockSize member of @@ -114,14 +117,41 @@ #define heapALLOCATE_BLOCK( pxBlock ) ( ( pxBlock->xBlockSize ) |= heapBLOCK_ALLOCATED_BITMASK ) #define heapFREE_BLOCK( pxBlock ) ( ( pxBlock->xBlockSize ) &= ~heapBLOCK_ALLOCATED_BITMASK ) +/* Setting configENABLE_HEAP_PROTECTOR to 1 enables heap block pointers + * protection using an application supplied canary value to catch heap + * corruption should a heap buffer overflow occur. + */ +#if ( configENABLE_HEAP_PROTECTOR == 1 ) + +/* Macro to load/store BlockLink_t pointers to memory. By XORing the + * pointers with a random canary value, heap overflows will result + * in randomly unpredictable pointer values which will be caught by + * heapVALIDATE_BLOCK_POINTER assert. */ + #define heapPROTECT_BLOCK_POINTER( pxBlock ) ( ( BlockLink_t * ) ( ( ( portPOINTER_SIZE_TYPE ) ( pxBlock ) ) ^ xHeapCanary ) ) + +/* Assert that a heap block pointer is within the heap bounds. */ + #define heapVALIDATE_BLOCK_POINTER( pxBlock ) \ + configASSERT( ( pucHeapHighAddress != NULL ) && \ + ( pucHeapLowAddress != NULL ) && \ + ( ( uint8_t * ) ( pxBlock ) >= pucHeapLowAddress ) && \ + ( ( uint8_t * ) ( pxBlock ) < pucHeapHighAddress ) ) + +#else /* if ( configENABLE_HEAP_PROTECTOR == 1 ) */ + + #define heapPROTECT_BLOCK_POINTER( pxBlock ) ( pxBlock ) + + #define heapVALIDATE_BLOCK_POINTER( pxBlock ) + +#endif /* configENABLE_HEAP_PROTECTOR */ + /*-----------------------------------------------------------*/ /* Define the linked list structure. This is used to link free blocks in order * of their memory address. */ typedef struct A_BLOCK_LINK { - struct A_BLOCK_LINK * pxNextFreeBlock; /*<< The next free block in the list. */ - size_t xBlockSize; /*<< The size of the free block. */ + struct A_BLOCK_LINK * pxNextFreeBlock; /**< The next free block in the list. */ + size_t xBlockSize; /**< The size of the free block. */ } BlockLink_t; /*-----------------------------------------------------------*/ @@ -132,7 +162,18 @@ typedef struct A_BLOCK_LINK * the block in front it and/or the block behind it if the memory blocks are * adjacent to each other. */ -static void prvInsertBlockIntoFreeList( BlockLink_t * pxBlockToInsert ); +static void prvInsertBlockIntoFreeList( BlockLink_t * pxBlockToInsert ) PRIVILEGED_FUNCTION; +void vPortDefineHeapRegions( const HeapRegion_t * const pxHeapRegions ) PRIVILEGED_FUNCTION; + +#if ( configENABLE_HEAP_PROTECTOR == 1 ) + +/** + * @brief Application provided function to get a random value to be used as canary. + * + * @param pxHeapCanary [out] Output parameter to return the canary value. + */ + extern void vApplicationGetRandomHeapCanary( portPOINTER_SIZE_TYPE * pxHeapCanary ); +#endif /* configENABLE_HEAP_PROTECTOR */ /*-----------------------------------------------------------*/ @@ -141,15 +182,26 @@ static void prvInsertBlockIntoFreeList( BlockLink_t * pxBlockToInsert ); static const size_t xHeapStructSize = ( sizeof( BlockLink_t ) + ( ( size_t ) ( portBYTE_ALIGNMENT - 1 ) ) ) & ~( ( size_t ) portBYTE_ALIGNMENT_MASK ); /* Create a couple of list links to mark the start and end of the list. */ -static BlockLink_t xStart; -static BlockLink_t * pxEnd = NULL; +PRIVILEGED_DATA static BlockLink_t xStart; +PRIVILEGED_DATA static BlockLink_t * pxEnd = NULL; /* Keeps track of the number of calls to allocate and free memory as well as the * number of free bytes remaining, but says nothing about fragmentation. */ -static size_t xFreeBytesRemaining = 0U; -static size_t xMinimumEverFreeBytesRemaining = 0U; -static size_t xNumberOfSuccessfulAllocations = 0; -static size_t xNumberOfSuccessfulFrees = 0; +PRIVILEGED_DATA static size_t xFreeBytesRemaining = 0U; +PRIVILEGED_DATA static size_t xMinimumEverFreeBytesRemaining = 0U; +PRIVILEGED_DATA static size_t xNumberOfSuccessfulAllocations = 0; +PRIVILEGED_DATA static size_t xNumberOfSuccessfulFrees = 0; + +#if ( configENABLE_HEAP_PROTECTOR == 1 ) + +/* Canary value for protecting internal heap pointers. */ + PRIVILEGED_DATA static portPOINTER_SIZE_TYPE xHeapCanary; + +/* Highest and lowest heap addresses used for heap block bounds checking. */ + PRIVILEGED_DATA static uint8_t * pucHeapHighAddress = NULL; + PRIVILEGED_DATA static uint8_t * pucHeapLowAddress = NULL; + +#endif /* configENABLE_HEAP_PROTECTOR */ /*-----------------------------------------------------------*/ @@ -162,50 +214,50 @@ void * pvPortMalloc( size_t xWantedSize ) size_t xAdditionalRequiredSize; /* The heap must be initialised before the first call to - * prvPortMalloc(). */ + * pvPortMalloc(). */ configASSERT( pxEnd ); - vTaskSuspendAll(); + if( xWantedSize > 0 ) { - if( xWantedSize > 0 ) + /* The wanted size must be increased so it can contain a BlockLink_t + * structure in addition to the requested amount of bytes. */ + if( heapADD_WILL_OVERFLOW( xWantedSize, xHeapStructSize ) == 0 ) { - /* The wanted size must be increased so it can contain a BlockLink_t - * structure in addition to the requested amount of bytes. */ - if( heapADD_WILL_OVERFLOW( xWantedSize, xHeapStructSize ) == 0 ) + xWantedSize += xHeapStructSize; + + /* Ensure that blocks are always aligned to the required number + * of bytes. */ + if( ( xWantedSize & portBYTE_ALIGNMENT_MASK ) != 0x00 ) { - xWantedSize += xHeapStructSize; + /* Byte alignment required. */ + xAdditionalRequiredSize = portBYTE_ALIGNMENT - ( xWantedSize & portBYTE_ALIGNMENT_MASK ); - /* Ensure that blocks are always aligned to the required number - * of bytes. */ - if( ( xWantedSize & portBYTE_ALIGNMENT_MASK ) != 0x00 ) + if( heapADD_WILL_OVERFLOW( xWantedSize, xAdditionalRequiredSize ) == 0 ) { - /* Byte alignment required. */ - xAdditionalRequiredSize = portBYTE_ALIGNMENT - ( xWantedSize & portBYTE_ALIGNMENT_MASK ); - - if( heapADD_WILL_OVERFLOW( xWantedSize, xAdditionalRequiredSize ) == 0 ) - { - xWantedSize += xAdditionalRequiredSize; - } - else - { - xWantedSize = 0; - } + xWantedSize += xAdditionalRequiredSize; } else { - mtCOVERAGE_TEST_MARKER(); + xWantedSize = 0; } } else { - xWantedSize = 0; + mtCOVERAGE_TEST_MARKER(); } } else { - mtCOVERAGE_TEST_MARKER(); + xWantedSize = 0; } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + vTaskSuspendAll(); + { /* Check the block size we are trying to allocate is not so large that the * top bit is set. The top bit of the block size member of the BlockLink_t * structure is used to determine who owns the block - the application or @@ -217,12 +269,14 @@ void * pvPortMalloc( size_t xWantedSize ) /* Traverse the list from the start (lowest address) block until * one of adequate size is found. */ pxPreviousBlock = &xStart; - pxBlock = xStart.pxNextFreeBlock; + pxBlock = heapPROTECT_BLOCK_POINTER( xStart.pxNextFreeBlock ); + heapVALIDATE_BLOCK_POINTER( pxBlock ); - while( ( pxBlock->xBlockSize < xWantedSize ) && ( pxBlock->pxNextFreeBlock != NULL ) ) + while( ( pxBlock->xBlockSize < xWantedSize ) && ( pxBlock->pxNextFreeBlock != heapPROTECT_BLOCK_POINTER( NULL ) ) ) { pxPreviousBlock = pxBlock; - pxBlock = pxBlock->pxNextFreeBlock; + pxBlock = heapPROTECT_BLOCK_POINTER( pxBlock->pxNextFreeBlock ); + heapVALIDATE_BLOCK_POINTER( pxBlock ); } /* If the end marker was reached then a block of adequate size @@ -231,7 +285,8 @@ void * pvPortMalloc( size_t xWantedSize ) { /* Return the memory space pointed to - jumping over the * BlockLink_t structure at its start. */ - pvReturn = ( void * ) ( ( ( uint8_t * ) pxPreviousBlock->pxNextFreeBlock ) + xHeapStructSize ); + pvReturn = ( void * ) ( ( ( uint8_t * ) heapPROTECT_BLOCK_POINTER( pxPreviousBlock->pxNextFreeBlock ) ) + xHeapStructSize ); + heapVALIDATE_BLOCK_POINTER( pvReturn ); /* This block is being returned for use so must be taken out * of the list of free blocks. */ @@ -239,6 +294,8 @@ void * pvPortMalloc( size_t xWantedSize ) /* If the block is larger than required it can be split into * two. */ + configASSERT( heapSUBTRACT_WILL_UNDERFLOW( pxBlock->xBlockSize, xWantedSize ) == 0 ); + if( ( pxBlock->xBlockSize - xWantedSize ) > heapMINIMUM_BLOCK_SIZE ) { /* This block is to be split into two. Create a new @@ -246,6 +303,7 @@ void * pvPortMalloc( size_t xWantedSize ) * cast is used to prevent byte alignment warnings from the * compiler. */ pxNewBlockLink = ( void * ) ( ( ( uint8_t * ) pxBlock ) + xWantedSize ); + configASSERT( ( ( ( size_t ) pxNewBlockLink ) & portBYTE_ALIGNMENT_MASK ) == 0 ); /* Calculate the sizes of two blocks split from the * single block. */ @@ -253,7 +311,8 @@ void * pvPortMalloc( size_t xWantedSize ) pxBlock->xBlockSize = xWantedSize; /* Insert the new block into the list of free blocks. */ - prvInsertBlockIntoFreeList( ( pxNewBlockLink ) ); + pxNewBlockLink->pxNextFreeBlock = pxPreviousBlock->pxNextFreeBlock; + pxPreviousBlock->pxNextFreeBlock = heapPROTECT_BLOCK_POINTER( pxNewBlockLink ); } else { @@ -309,6 +368,7 @@ void * pvPortMalloc( size_t xWantedSize ) } #endif /* if ( configUSE_MALLOC_FAILED_HOOK == 1 ) */ + configASSERT( ( ( ( size_t ) pvReturn ) & ( size_t ) portBYTE_ALIGNMENT_MASK ) == 0 ); return pvReturn; } /*-----------------------------------------------------------*/ @@ -327,6 +387,7 @@ void vPortFree( void * pv ) /* This casting is to keep the compiler from issuing warnings. */ pxLink = ( void * ) puc; + heapVALIDATE_BLOCK_POINTER( pxLink ); configASSERT( heapBLOCK_IS_ALLOCATED( pxLink ) != 0 ); configASSERT( pxLink->pxNextFreeBlock == NULL ); @@ -339,7 +400,12 @@ void vPortFree( void * pv ) heapFREE_BLOCK( pxLink ); #if ( configHEAP_CLEAR_MEMORY_ON_FREE == 1 ) { - ( void ) memset( puc + xHeapStructSize, 0, pxLink->xBlockSize - xHeapStructSize ); + /* Check for underflow as this can occur if xBlockSize is + * overwritten in a heap block. */ + if( heapSUBTRACT_WILL_UNDERFLOW( pxLink->xBlockSize, xHeapStructSize ) == 0 ) + { + ( void ) memset( puc + xHeapStructSize, 0, pxLink->xBlockSize - xHeapStructSize ); + } } #endif @@ -397,18 +463,23 @@ void * pvPortCalloc( size_t xNum, } /*-----------------------------------------------------------*/ -static void prvInsertBlockIntoFreeList( BlockLink_t * pxBlockToInsert ) +static void prvInsertBlockIntoFreeList( BlockLink_t * pxBlockToInsert ) /* PRIVILEGED_FUNCTION */ { BlockLink_t * pxIterator; uint8_t * puc; /* Iterate through the list until a block is found that has a higher address * than the block being inserted. */ - for( pxIterator = &xStart; pxIterator->pxNextFreeBlock < pxBlockToInsert; pxIterator = pxIterator->pxNextFreeBlock ) + for( pxIterator = &xStart; heapPROTECT_BLOCK_POINTER( pxIterator->pxNextFreeBlock ) < pxBlockToInsert; pxIterator = heapPROTECT_BLOCK_POINTER( pxIterator->pxNextFreeBlock ) ) { /* Nothing to do here, just iterate to the right position. */ } + if( pxIterator != &xStart ) + { + heapVALIDATE_BLOCK_POINTER( pxIterator ); + } + /* Do the block being inserted, and the block it is being inserted after * make a contiguous block of memory? */ puc = ( uint8_t * ) pxIterator; @@ -427,17 +498,17 @@ static void prvInsertBlockIntoFreeList( BlockLink_t * pxBlockToInsert ) * make a contiguous block of memory? */ puc = ( uint8_t * ) pxBlockToInsert; - if( ( puc + pxBlockToInsert->xBlockSize ) == ( uint8_t * ) pxIterator->pxNextFreeBlock ) + if( ( puc + pxBlockToInsert->xBlockSize ) == ( uint8_t * ) heapPROTECT_BLOCK_POINTER( pxIterator->pxNextFreeBlock ) ) { - if( pxIterator->pxNextFreeBlock != pxEnd ) + if( heapPROTECT_BLOCK_POINTER( pxIterator->pxNextFreeBlock ) != pxEnd ) { /* Form one big block from the two blocks. */ - pxBlockToInsert->xBlockSize += pxIterator->pxNextFreeBlock->xBlockSize; - pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock->pxNextFreeBlock; + pxBlockToInsert->xBlockSize += heapPROTECT_BLOCK_POINTER( pxIterator->pxNextFreeBlock )->xBlockSize; + pxBlockToInsert->pxNextFreeBlock = heapPROTECT_BLOCK_POINTER( pxIterator->pxNextFreeBlock )->pxNextFreeBlock; } else { - pxBlockToInsert->pxNextFreeBlock = pxEnd; + pxBlockToInsert->pxNextFreeBlock = heapPROTECT_BLOCK_POINTER( pxEnd ); } } else @@ -445,13 +516,13 @@ static void prvInsertBlockIntoFreeList( BlockLink_t * pxBlockToInsert ) pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock; } - /* If the block being inserted plugged a gab, so was merged with the block + /* If the block being inserted plugged a gap, so was merged with the block * before and the block after, then it's pxNextFreeBlock pointer will have * already been set, and should not be set here as that would make it point * to itself. */ if( pxIterator != pxBlockToInsert ) { - pxIterator->pxNextFreeBlock = pxBlockToInsert; + pxIterator->pxNextFreeBlock = heapPROTECT_BLOCK_POINTER( pxBlockToInsert ); } else { @@ -460,7 +531,7 @@ static void prvInsertBlockIntoFreeList( BlockLink_t * pxBlockToInsert ) } /*-----------------------------------------------------------*/ -void vPortDefineHeapRegions( const HeapRegion_t * const pxHeapRegions ) +void vPortDefineHeapRegions( const HeapRegion_t * const pxHeapRegions ) /* PRIVILEGED_FUNCTION */ { BlockLink_t * pxFirstFreeBlockInRegion = NULL; BlockLink_t * pxPreviousFreeBlock; @@ -473,6 +544,12 @@ void vPortDefineHeapRegions( const HeapRegion_t * const pxHeapRegions ) /* Can only call once! */ configASSERT( pxEnd == NULL ); + #if ( configENABLE_HEAP_PROTECTOR == 1 ) + { + vApplicationGetRandomHeapCanary( &( xHeapCanary ) ); + } + #endif + pxHeapRegion = &( pxHeapRegions[ xDefinedRegions ] ); while( pxHeapRegion->xSizeInBytes > 0 ) @@ -485,7 +562,7 @@ void vPortDefineHeapRegions( const HeapRegion_t * const pxHeapRegions ) if( ( xAddress & portBYTE_ALIGNMENT_MASK ) != 0 ) { xAddress += ( portBYTE_ALIGNMENT - 1 ); - xAddress &= ~portBYTE_ALIGNMENT_MASK; + xAddress &= ~( portPOINTER_SIZE_TYPE ) portBYTE_ALIGNMENT_MASK; /* Adjust the size for the bytes lost to alignment. */ xTotalRegionSize -= ( size_t ) ( xAddress - ( portPOINTER_SIZE_TYPE ) pxHeapRegion->pucStartAddress ); @@ -498,48 +575,68 @@ void vPortDefineHeapRegions( const HeapRegion_t * const pxHeapRegions ) { /* xStart is used to hold a pointer to the first item in the list of * free blocks. The void cast is used to prevent compiler warnings. */ - xStart.pxNextFreeBlock = ( BlockLink_t * ) xAlignedHeap; + xStart.pxNextFreeBlock = ( BlockLink_t * ) heapPROTECT_BLOCK_POINTER( xAlignedHeap ); xStart.xBlockSize = ( size_t ) 0; } else { /* Should only get here if one region has already been added to the * heap. */ - configASSERT( pxEnd != NULL ); + configASSERT( pxEnd != heapPROTECT_BLOCK_POINTER( NULL ) ); /* Check blocks are passed in with increasing start addresses. */ - configASSERT( xAddress > ( size_t ) pxEnd ); + configASSERT( ( size_t ) xAddress > ( size_t ) pxEnd ); } + #if ( configENABLE_HEAP_PROTECTOR == 1 ) + { + if( ( pucHeapLowAddress == NULL ) || + ( ( uint8_t * ) xAlignedHeap < pucHeapLowAddress ) ) + { + pucHeapLowAddress = ( uint8_t * ) xAlignedHeap; + } + } + #endif /* configENABLE_HEAP_PROTECTOR */ + /* Remember the location of the end marker in the previous region, if * any. */ pxPreviousFreeBlock = pxEnd; /* pxEnd is used to mark the end of the list of free blocks and is * inserted at the end of the region space. */ - xAddress = xAlignedHeap + xTotalRegionSize; - xAddress -= xHeapStructSize; - xAddress &= ~( ( size_t ) portBYTE_ALIGNMENT_MASK ); + xAddress = xAlignedHeap + ( portPOINTER_SIZE_TYPE ) xTotalRegionSize; + xAddress -= ( portPOINTER_SIZE_TYPE ) xHeapStructSize; + xAddress &= ~( ( portPOINTER_SIZE_TYPE ) portBYTE_ALIGNMENT_MASK ); pxEnd = ( BlockLink_t * ) xAddress; pxEnd->xBlockSize = 0; - pxEnd->pxNextFreeBlock = NULL; + pxEnd->pxNextFreeBlock = heapPROTECT_BLOCK_POINTER( NULL ); /* To start with there is a single free block in this region that is * sized to take up the entire heap region minus the space taken by the * free block structure. */ pxFirstFreeBlockInRegion = ( BlockLink_t * ) xAlignedHeap; pxFirstFreeBlockInRegion->xBlockSize = ( size_t ) ( xAddress - ( portPOINTER_SIZE_TYPE ) pxFirstFreeBlockInRegion ); - pxFirstFreeBlockInRegion->pxNextFreeBlock = pxEnd; + pxFirstFreeBlockInRegion->pxNextFreeBlock = heapPROTECT_BLOCK_POINTER( pxEnd ); /* If this is not the first region that makes up the entire heap space * then link the previous region to this region. */ if( pxPreviousFreeBlock != NULL ) { - pxPreviousFreeBlock->pxNextFreeBlock = pxFirstFreeBlockInRegion; + pxPreviousFreeBlock->pxNextFreeBlock = heapPROTECT_BLOCK_POINTER( pxFirstFreeBlockInRegion ); } xTotalHeapSize += pxFirstFreeBlockInRegion->xBlockSize; + #if ( configENABLE_HEAP_PROTECTOR == 1 ) + { + if( ( pucHeapHighAddress == NULL ) || + ( ( ( ( uint8_t * ) pxFirstFreeBlockInRegion ) + pxFirstFreeBlockInRegion->xBlockSize ) > pucHeapHighAddress ) ) + { + pucHeapHighAddress = ( ( uint8_t * ) pxFirstFreeBlockInRegion ) + pxFirstFreeBlockInRegion->xBlockSize; + } + } + #endif + /* Move onto the next HeapRegion_t structure. */ xDefinedRegions++; pxHeapRegion = &( pxHeapRegions[ xDefinedRegions ] ); @@ -560,7 +657,7 @@ void vPortGetHeapStats( HeapStats_t * pxHeapStats ) vTaskSuspendAll(); { - pxBlock = xStart.pxNextFreeBlock; + pxBlock = heapPROTECT_BLOCK_POINTER( xStart.pxNextFreeBlock ); /* pxBlock will be NULL if the heap has not been initialised. The heap * is initialised automatically when the first allocation is made. */ @@ -590,7 +687,7 @@ void vPortGetHeapStats( HeapStats_t * pxHeapStats ) /* Move to the next block in the chain until the last block is * reached. */ - pxBlock = pxBlock->pxNextFreeBlock; + pxBlock = heapPROTECT_BLOCK_POINTER( pxBlock->pxNextFreeBlock ); } } } diff --git a/Source/portable/MikroC/ARM_CM4F/port.c b/Source/portable/MikroC/ARM_CM4F/port.c index d488c1307..c11e0aa3c 100644 --- a/Source/portable/MikroC/ARM_CM4F/port.c +++ b/Source/portable/MikroC/ARM_CM4F/port.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -509,14 +509,21 @@ void xPortSysTickHandler( void ) iv IVT_INT_SysTick ics ICS_AUTO * known - therefore the slightly faster portDISABLE_INTERRUPTS() function is * used in place of portSET_INTERRUPT_MASK_FROM_ISR(). */ portDISABLE_INTERRUPTS(); + traceISR_ENTER(); { /* Increment the RTOS tick. */ if( xTaskIncrementTick() != pdFALSE ) { + traceISR_EXIT_TO_SCHEDULER(); + /* A context switch is required. Context switching is performed in * the PendSV interrupt. Pend the PendSV interrupt. */ portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; } + else + { + traceISR_EXIT(); + } } portENABLE_INTERRUPTS(); } diff --git a/Source/portable/MikroC/ARM_CM4F/portmacro.h b/Source/portable/MikroC/ARM_CM4F/portmacro.h index 545af2b32..b603f79cb 100644 --- a/Source/portable/MikroC/ARM_CM4F/portmacro.h +++ b/Source/portable/MikroC/ARM_CM4F/portmacro.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -97,10 +97,22 @@ __asm{ isb }; \ } - #define portNVIC_INT_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed04 ) ) - #define portNVIC_PENDSVSET_BIT ( 1UL << 28UL ) - #define portEND_SWITCHING_ISR( xSwitchRequired ) do { if( xSwitchRequired != pdFALSE ) portYIELD(); } while( 0 ) - #define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x ) +#define portNVIC_INT_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed04 ) ) +#define portNVIC_PENDSVSET_BIT ( 1UL << 28UL ) +#define portEND_SWITCHING_ISR( xSwitchRequired ) \ + do \ + { \ + if( xSwitchRequired != pdFALSE ) \ + { \ + traceISR_EXIT_TO_SCHEDULER(); \ + portYIELD(); \ + } \ + else \ + { \ + traceISR_EXIT(); \ + } \ + } while( 0 ) +#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x ) /*-----------------------------------------------------------*/ /* Critical section management. */ diff --git a/Source/portable/Paradigm/Tern_EE/large_untested/port.c b/Source/portable/Paradigm/Tern_EE/large_untested/port.c index db7c790f7..b57943c39 100644 --- a/Source/portable/Paradigm/Tern_EE/large_untested/port.c +++ b/Source/portable/Paradigm/Tern_EE/large_untested/port.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/Source/portable/Paradigm/Tern_EE/large_untested/portasm.h b/Source/portable/Paradigm/Tern_EE/large_untested/portasm.h index 6e88f768a..e276fa38a 100644 --- a/Source/portable/Paradigm/Tern_EE/large_untested/portasm.h +++ b/Source/portable/Paradigm/Tern_EE/large_untested/portasm.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/Source/portable/Paradigm/Tern_EE/large_untested/portmacro.h b/Source/portable/Paradigm/Tern_EE/large_untested/portmacro.h index 40712f2e8..f1f68a46b 100644 --- a/Source/portable/Paradigm/Tern_EE/large_untested/portmacro.h +++ b/Source/portable/Paradigm/Tern_EE/large_untested/portmacro.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/Source/portable/Paradigm/Tern_EE/small/port.c b/Source/portable/Paradigm/Tern_EE/small/port.c index ddd96d549..379e06a7a 100644 --- a/Source/portable/Paradigm/Tern_EE/small/port.c +++ b/Source/portable/Paradigm/Tern_EE/small/port.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/Source/portable/Paradigm/Tern_EE/small/portasm.h b/Source/portable/Paradigm/Tern_EE/small/portasm.h index b72a90f37..33e095071 100644 --- a/Source/portable/Paradigm/Tern_EE/small/portasm.h +++ b/Source/portable/Paradigm/Tern_EE/small/portasm.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/Source/portable/Paradigm/Tern_EE/small/portmacro.h b/Source/portable/Paradigm/Tern_EE/small/portmacro.h index 771df324e..b6fbfa398 100644 --- a/Source/portable/Paradigm/Tern_EE/small/portmacro.h +++ b/Source/portable/Paradigm/Tern_EE/small/portmacro.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/Source/portable/RVDS/ARM7_LPC21xx/port.c b/Source/portable/RVDS/ARM7_LPC21xx/port.c index 5a5f51783..11c9ff12d 100644 --- a/Source/portable/RVDS/ARM7_LPC21xx/port.c +++ b/Source/portable/RVDS/ARM7_LPC21xx/port.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -35,35 +35,35 @@ #include "task.h" /* Constants required to setup the initial task context. */ -#define portINITIAL_SPSR ( ( StackType_t ) 0x1f ) /* System mode, ARM mode, interrupts enabled. */ -#define portTHUMB_MODE_BIT ( ( StackType_t ) 0x20 ) -#define portINSTRUCTION_SIZE ( ( StackType_t ) 4 ) -#define portNO_CRITICAL_SECTION_NESTING ( ( StackType_t ) 0 ) +#define portINITIAL_SPSR ( ( StackType_t ) 0x1f ) /* System mode, ARM mode, interrupts enabled. */ +#define portTHUMB_MODE_BIT ( ( StackType_t ) 0x20 ) +#define portINSTRUCTION_SIZE ( ( StackType_t ) 4 ) +#define portNO_CRITICAL_SECTION_NESTING ( ( StackType_t ) 0 ) /* Constants required to setup the tick ISR. */ -#define portENABLE_TIMER ( ( uint8_t ) 0x01 ) -#define portPRESCALE_VALUE 0x00 -#define portINTERRUPT_ON_MATCH ( ( uint32_t ) 0x01 ) -#define portRESET_COUNT_ON_MATCH ( ( uint32_t ) 0x02 ) +#define portENABLE_TIMER ( ( uint8_t ) 0x01 ) +#define portPRESCALE_VALUE 0x00 +#define portINTERRUPT_ON_MATCH ( ( uint32_t ) 0x01 ) +#define portRESET_COUNT_ON_MATCH ( ( uint32_t ) 0x02 ) /* Constants required to setup the VIC for the tick ISR. */ -#define portTIMER_VIC_CHANNEL ( ( uint32_t ) 0x0004 ) -#define portTIMER_VIC_CHANNEL_BIT ( ( uint32_t ) 0x0010 ) -#define portTIMER_VIC_ENABLE ( ( uint32_t ) 0x0020 ) +#define portTIMER_VIC_CHANNEL ( ( uint32_t ) 0x0004 ) +#define portTIMER_VIC_CHANNEL_BIT ( ( uint32_t ) 0x0010 ) +#define portTIMER_VIC_ENABLE ( ( uint32_t ) 0x0020 ) /* Constants required to handle interrupts. */ -#define portTIMER_MATCH_ISR_BIT ( ( uint8_t ) 0x01 ) -#define portCLEAR_VIC_INTERRUPT ( ( uint32_t ) 0 ) +#define portTIMER_MATCH_ISR_BIT ( ( uint8_t ) 0x01 ) +#define portCLEAR_VIC_INTERRUPT ( ( uint32_t ) 0 ) /*-----------------------------------------------------------*/ /* The code generated by the Keil compiler does not maintain separate -stack and frame pointers. The portENTER_CRITICAL macro cannot therefore -use the stack as per other ports. Instead a variable is used to keep -track of the critical section nesting. This variable has to be stored -as part of the task context and must be initialised to a non zero value. */ + * stack and frame pointers. The portENTER_CRITICAL macro cannot therefore + * use the stack as per other ports. Instead a variable is used to keep + * track of the critical section nesting. This variable has to be stored + * as part of the task context and must be initialised to a non zero value. */ -#define portNO_CRITICAL_NESTING ( ( uint32_t ) 0 ) +#define portNO_CRITICAL_NESTING ( ( uint32_t ) 0 ) volatile uint32_t ulCriticalNesting = 9999UL; /*-----------------------------------------------------------*/ @@ -82,60 +82,62 @@ extern __asm void vPortStartFirstTask( void ); /* * See header file for description. */ -StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters ) +StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, + TaskFunction_t pxCode, + void * pvParameters ) { -StackType_t *pxOriginalTOS; + StackType_t * pxOriginalTOS; /* Setup the initial stack of the task. The stack is set exactly as - expected by the portRESTORE_CONTEXT() macro. - - Remember where the top of the (simulated) stack is before we place - anything on it. */ + * expected by the portRESTORE_CONTEXT() macro. + * + * Remember where the top of the (simulated) stack is before we place + * anything on it. */ pxOriginalTOS = pxTopOfStack; /* To ensure asserts in tasks.c don't fail, although in this case the assert - is not really required. */ + * is not really required. */ pxTopOfStack--; /* First on the stack is the return address - which in this case is the - start of the task. The offset is added to make the return address appear - as it would within an IRQ ISR. */ + * start of the task. The offset is added to make the return address appear + * as it would within an IRQ ISR. */ *pxTopOfStack = ( StackType_t ) pxCode + portINSTRUCTION_SIZE; pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0xaaaaaaaa; /* R14 */ + *pxTopOfStack = ( StackType_t ) 0xaaaaaaaa; /* R14 */ pxTopOfStack--; *pxTopOfStack = ( StackType_t ) pxOriginalTOS; /* Stack used when task starts goes in R13. */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x12121212; /* R12 */ + *pxTopOfStack = ( StackType_t ) 0x12121212; /* R12 */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x11111111; /* R11 */ + *pxTopOfStack = ( StackType_t ) 0x11111111; /* R11 */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x10101010; /* R10 */ + *pxTopOfStack = ( StackType_t ) 0x10101010; /* R10 */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x09090909; /* R9 */ + *pxTopOfStack = ( StackType_t ) 0x09090909; /* R9 */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x08080808; /* R8 */ + *pxTopOfStack = ( StackType_t ) 0x08080808; /* R8 */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x07070707; /* R7 */ + *pxTopOfStack = ( StackType_t ) 0x07070707; /* R7 */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x06060606; /* R6 */ + *pxTopOfStack = ( StackType_t ) 0x06060606; /* R6 */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x05050505; /* R5 */ + *pxTopOfStack = ( StackType_t ) 0x05050505; /* R5 */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x04040404; /* R4 */ + *pxTopOfStack = ( StackType_t ) 0x04040404; /* R4 */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x03030303; /* R3 */ + *pxTopOfStack = ( StackType_t ) 0x03030303; /* R3 */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x02020202; /* R2 */ + *pxTopOfStack = ( StackType_t ) 0x02020202; /* R2 */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x01010101; /* R1 */ + *pxTopOfStack = ( StackType_t ) 0x01010101; /* R1 */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */ + *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */ pxTopOfStack--; /* The last thing onto the stack is the status register, which is set for - system mode, with interrupts enabled. */ + * system mode, with interrupts enabled. */ *pxTopOfStack = ( StackType_t ) portINITIAL_SPSR; if( ( ( uint32_t ) pxCode & 0x01UL ) != 0x00UL ) @@ -147,10 +149,10 @@ StackType_t *pxOriginalTOS; pxTopOfStack--; /* The code generated by the Keil compiler does not maintain separate - stack and frame pointers. The portENTER_CRITICAL macro cannot therefore - use the stack as per other ports. Instead a variable is used to keep - track of the critical section nesting. This variable has to be stored - as part of the task context and is initially set to zero. */ + * stack and frame pointers. The portENTER_CRITICAL macro cannot therefore + * use the stack as per other ports. Instead a variable is used to keep + * track of the critical section nesting. This variable has to be stored + * as part of the task context and is initially set to zero. */ *pxTopOfStack = portNO_CRITICAL_SECTION_NESTING; return pxTopOfStack; @@ -163,7 +165,7 @@ BaseType_t xPortStartScheduler( void ) prvSetupTimerInterrupt(); /* Start the first task. This is done from portISR.c as ARM mode must be - used. */ + * used. */ vPortStartFirstTask(); /* Should not get here! */ @@ -174,56 +176,56 @@ BaseType_t xPortStartScheduler( void ) void vPortEndScheduler( void ) { /* It is unlikely that the ARM port will require this function as there - is nothing to return to. If this is required - stop the tick ISR then - return back to main. */ + * is nothing to return to. If this is required - stop the tick ISR then + * return back to main. */ } /*-----------------------------------------------------------*/ #if configUSE_PREEMPTION == 0 - /* - * The cooperative scheduler requires a normal IRQ service routine to - * simply increment the system tick. - */ +/* + * The cooperative scheduler requires a normal IRQ service routine to + * simply increment the system tick. + */ void vNonPreemptiveTick( void ) __irq; void vNonPreemptiveTick( void ) __irq { /* Increment the tick count - this may make a delaying task ready - to run - but a context switch is not performed. */ + * to run - but a context switch is not performed. */ xTaskIncrementTick(); - T0IR = portTIMER_MATCH_ISR_BIT; /* Clear the timer event */ - VICVectAddr = portCLEAR_VIC_INTERRUPT; /* Acknowledge the Interrupt */ + T0IR = portTIMER_MATCH_ISR_BIT; /* Clear the timer event */ + VICVectAddr = portCLEAR_VIC_INTERRUPT; /* Acknowledge the Interrupt */ } - #else +#else /* if configUSE_PREEMPTION == 0 */ - /* - ************************************************************************** - * The preemptive scheduler ISR is written in assembler and can be found - * in the portASM.s file. This will only get used if portUSE_PREEMPTION - * is set to 1 in portmacro.h - ************************************************************************** - */ +/* + ************************************************************************** + * The preemptive scheduler ISR is written in assembler and can be found + * in the portASM.s file. This will only get used if portUSE_PREEMPTION + * is set to 1 in portmacro.h + ************************************************************************** + */ - void vPreemptiveTick( void ); + void vPreemptiveTick( void ); -#endif +#endif /* if configUSE_PREEMPTION == 0 */ /*-----------------------------------------------------------*/ static void prvSetupTimerInterrupt( void ) { -uint32_t ulCompareMatch; + uint32_t ulCompareMatch; /* A 1ms tick does not require the use of the timer prescale. This is - defaulted to zero but can be used if necessary. */ + * defaulted to zero but can be used if necessary. */ T0PR = portPRESCALE_VALUE; /* Calculate the match value required for our wanted tick rate. */ ulCompareMatch = configCPU_CLOCK_HZ / configTICK_RATE_HZ; /* Protect against divide by zero. Using an if() statement still results - in a warning - hence the #if. */ + * in a warning - hence the #if. */ #if portPRESCALE_VALUE != 0 { ulCompareMatch /= ( portPRESCALE_VALUE + 1 ); @@ -240,7 +242,7 @@ uint32_t ulCompareMatch; VICIntEnable |= portTIMER_VIC_CHANNEL_BIT; /* The ISR installed depends on whether the preemptive or cooperative - scheduler is being used. */ + * scheduler is being used. */ #if configUSE_PREEMPTION == 1 { VICVectAddr0 = ( uint32_t ) vPreemptiveTick; @@ -254,7 +256,7 @@ uint32_t ulCompareMatch; VICVectCntl0 = portTIMER_VIC_CHANNEL | portTIMER_VIC_ENABLE; /* Start the timer - interrupts are disabled when this function is called - so it is okay to do this here. */ + * so it is okay to do this here. */ T0TCR = portENABLE_TIMER; } /*-----------------------------------------------------------*/ @@ -264,9 +266,9 @@ void vPortEnterCritical( void ) /* Disable interrupts as per portDISABLE_INTERRUPTS(); */ __disable_irq(); - /* Now interrupts are disabled ulCriticalNesting can be accessed - directly. Increment ulCriticalNesting to keep a count of how many times - portENTER_CRITICAL() has been called. */ + /* Now that interrupts are disabled, ulCriticalNesting can be accessed + * directly. Increment ulCriticalNesting to keep a count of how many times + * portENTER_CRITICAL() has been called. */ ulCriticalNesting++; } /*-----------------------------------------------------------*/ @@ -279,7 +281,7 @@ void vPortExitCritical( void ) ulCriticalNesting--; /* If the nesting level has reached zero then interrupts should be - re-enabled. */ + * re-enabled. */ if( ulCriticalNesting == portNO_CRITICAL_NESTING ) { /* Enable interrupts as per portEXIT_CRITICAL(). */ diff --git a/Source/portable/RVDS/ARM7_LPC21xx/portASM.s b/Source/portable/RVDS/ARM7_LPC21xx/portASM.s index 3d291ebac..8f98d4871 100644 --- a/Source/portable/RVDS/ARM7_LPC21xx/portASM.s +++ b/Source/portable/RVDS/ARM7_LPC21xx/portASM.s @@ -1,5 +1,5 @@ ;/* -; * FreeRTOS Kernel V10.6.2 +; * FreeRTOS Kernel V11.0.1 ; * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. ; * ; * SPDX-License-Identifier: MIT diff --git a/Source/portable/RVDS/ARM7_LPC21xx/portmacro.h b/Source/portable/RVDS/ARM7_LPC21xx/portmacro.h index 95ba4dc05..24455c399 100644 --- a/Source/portable/RVDS/ARM7_LPC21xx/portmacro.h +++ b/Source/portable/RVDS/ARM7_LPC21xx/portmacro.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -47,24 +47,24 @@ */ /* Type definitions. */ -#define portCHAR char -#define portFLOAT float -#define portDOUBLE double -#define portLONG long -#define portSHORT short -#define portSTACK_TYPE uint32_t -#define portBASE_TYPE long - -typedef portSTACK_TYPE StackType_t; -typedef long BaseType_t; -typedef unsigned long UBaseType_t; - - -#if( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS ) - typedef uint16_t TickType_t; - #define portMAX_DELAY ( TickType_t ) 0xffff -#elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS ) - typedef uint32_t TickType_t; +#define portCHAR char +#define portFLOAT float +#define portDOUBLE double +#define portLONG long +#define portSHORT short +#define portSTACK_TYPE uint32_t +#define portBASE_TYPE long + +typedef portSTACK_TYPE StackType_t; +typedef long BaseType_t; +typedef unsigned long UBaseType_t; + + +#if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS ) + typedef uint16_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffff +#elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS ) + typedef uint32_t TickType_t; #define portMAX_DELAY ( TickType_t ) 0xffffffffUL #else #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width. @@ -72,34 +72,34 @@ typedef unsigned long UBaseType_t; /*-----------------------------------------------------------*/ /* Hardware specifics. */ -#define portSTACK_GROWTH ( -1 ) -#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) -#define portBYTE_ALIGNMENT 8 +#define portSTACK_GROWTH ( -1 ) +#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) +#define portBYTE_ALIGNMENT 8 /*-----------------------------------------------------------*/ /* Task utilities. */ /*----------------------------------------------------------- - * ISR entry and exit macros. These are only required if a task switch - * is required from an ISR. - *----------------------------------------------------------*/ +* ISR entry and exit macros. These are only required if a task switch +* is required from an ISR. +*----------------------------------------------------------*/ /* If a switch is required then we just need to call */ /* vTaskSwitchContext() as the context has already been */ /* saved. */ -#define portEXIT_SWITCHING_ISR(SwitchRequired) \ -{ \ -extern void vTaskSwitchContext(void); \ - \ - if(SwitchRequired) \ - { \ - vTaskSwitchContext(); \ - } \ -} \ +#define portEXIT_SWITCHING_ISR( SwitchRequired ) \ + { \ + extern void vTaskSwitchContext( void ); \ + \ + if( SwitchRequired ) \ + { \ + vTaskSwitchContext(); \ + } \ + } \ extern void vPortYield( void ); -#define portYIELD() vPortYield() +#define portYIELD() vPortYield() /* Critical section management. */ @@ -117,31 +117,31 @@ extern void vPortYield( void ); /*----------------------------------------------------------- - * Critical section control - * - * The code generated by the Keil compiler does not maintain separate - * stack and frame pointers. The portENTER_CRITICAL macro cannot therefore - * use the stack as per other ports. Instead a variable is used to keep - * track of the critical section nesting. This necessitates the use of a - * function in place of the macro. - *----------------------------------------------------------*/ +* Critical section control +* +* The code generated by the Keil compiler does not maintain separate +* stack and frame pointers. The portENTER_CRITICAL macro cannot therefore +* use the stack as per other ports. Instead a variable is used to keep +* track of the critical section nesting. This necessitates the use of a +* function in place of the macro. +*----------------------------------------------------------*/ extern void vPortEnterCritical( void ); extern void vPortExitCritical( void ); -#define portENTER_CRITICAL() vPortEnterCritical(); -#define portEXIT_CRITICAL() vPortExitCritical(); +#define portENTER_CRITICAL() vPortEnterCritical(); +#define portEXIT_CRITICAL() vPortExitCritical(); /*-----------------------------------------------------------*/ /* Compiler specifics. */ #define inline #define register -#define portNOP() __asm{ NOP } +#define portNOP() __asm { NOP } /*-----------------------------------------------------------*/ /* Task function macros as described on the FreeRTOS.org WEB site. */ -#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters ) -#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters ) +#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters ) +#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters ) /* *INDENT-OFF* */ #ifdef __cplusplus diff --git a/Source/portable/RVDS/ARM7_LPC21xx/portmacro.inc b/Source/portable/RVDS/ARM7_LPC21xx/portmacro.inc index 0be2c18bc..7f857960c 100644 --- a/Source/portable/RVDS/ARM7_LPC21xx/portmacro.inc +++ b/Source/portable/RVDS/ARM7_LPC21xx/portmacro.inc @@ -1,5 +1,5 @@ ;/* -; * FreeRTOS Kernel V10.6.2 +; * FreeRTOS Kernel V11.0.1 ; * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. ; * ; * SPDX-License-Identifier: MIT diff --git a/Source/portable/RVDS/ARM_CA9/port.c b/Source/portable/RVDS/ARM_CA9/port.c index d41813121..c66e92f0a 100644 --- a/Source/portable/RVDS/ARM_CA9/port.c +++ b/Source/portable/RVDS/ARM_CA9/port.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -34,43 +34,43 @@ #include "task.h" #ifndef configINTERRUPT_CONTROLLER_BASE_ADDRESS - #error configINTERRUPT_CONTROLLER_BASE_ADDRESS must be defined. See https://www.FreeRTOS.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html + #error "configINTERRUPT_CONTROLLER_BASE_ADDRESS must be defined. See www.FreeRTOS.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html" #endif #ifndef configINTERRUPT_CONTROLLER_CPU_INTERFACE_OFFSET - #error configINTERRUPT_CONTROLLER_CPU_INTERFACE_OFFSET must be defined. See https://www.FreeRTOS.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html + #error "configINTERRUPT_CONTROLLER_CPU_INTERFACE_OFFSET must be defined. See www.FreeRTOS.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html" #endif #ifndef configUNIQUE_INTERRUPT_PRIORITIES - #error configUNIQUE_INTERRUPT_PRIORITIES must be defined. See https://www.FreeRTOS.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html + #error "configUNIQUE_INTERRUPT_PRIORITIES must be defined. See www.FreeRTOS.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html" #endif #ifndef configSETUP_TICK_INTERRUPT - #error configSETUP_TICK_INTERRUPT() must be defined. See https://www.FreeRTOS.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html + #error "configSETUP_TICK_INTERRUPT() must be defined. See www.FreeRTOS.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html" #endif /* configSETUP_TICK_INTERRUPT */ #ifndef configMAX_API_CALL_INTERRUPT_PRIORITY - #error configMAX_API_CALL_INTERRUPT_PRIORITY must be defined. See https://www.FreeRTOS.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html + #error "configMAX_API_CALL_INTERRUPT_PRIORITY must be defined. See www.FreeRTOS.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html" #endif #if configMAX_API_CALL_INTERRUPT_PRIORITY == 0 - #error configMAX_API_CALL_INTERRUPT_PRIORITY must not be set to 0 + #error "configMAX_API_CALL_INTERRUPT_PRIORITY must not be set to 0" #endif #if configMAX_API_CALL_INTERRUPT_PRIORITY > configUNIQUE_INTERRUPT_PRIORITIES - #error configMAX_API_CALL_INTERRUPT_PRIORITY must be less than or equal to configUNIQUE_INTERRUPT_PRIORITIES as the lower the numeric priority value the higher the logical interrupt priority + #error "configMAX_API_CALL_INTERRUPT_PRIORITY must be less than or equal to configUNIQUE_INTERRUPT_PRIORITIES as the lower the numeric priority value the higher the logical interrupt priority" #endif #if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 /* Check the configuration. */ - #if( configMAX_PRIORITIES > 32 ) - #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice. + #if ( configMAX_PRIORITIES > 32 ) + #error "configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice." #endif #endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */ /* In case security extensions are implemented. */ #if configMAX_API_CALL_INTERRUPT_PRIORITY <= ( configUNIQUE_INTERRUPT_PRIORITIES / 2 ) - #error configMAX_API_CALL_INTERRUPT_PRIORITY must be greater than ( configUNIQUE_INTERRUPT_PRIORITIES / 2 ) + #error "configMAX_API_CALL_INTERRUPT_PRIORITY must be greater than ( configUNIQUE_INTERRUPT_PRIORITIES / 2 )" #endif #ifndef configCLEAR_TICK_INTERRUPT @@ -78,80 +78,80 @@ #endif /* The number of bits to shift for an interrupt priority is dependent on the -number of bits implemented by the interrupt controller. */ + * number of bits implemented by the interrupt controller. */ #if configUNIQUE_INTERRUPT_PRIORITIES == 16 - #define portPRIORITY_SHIFT 4 - #define portMAX_BINARY_POINT_VALUE 3 + #define portPRIORITY_SHIFT 4 + #define portMAX_BINARY_POINT_VALUE 3 #elif configUNIQUE_INTERRUPT_PRIORITIES == 32 - #define portPRIORITY_SHIFT 3 - #define portMAX_BINARY_POINT_VALUE 2 + #define portPRIORITY_SHIFT 3 + #define portMAX_BINARY_POINT_VALUE 2 #elif configUNIQUE_INTERRUPT_PRIORITIES == 64 - #define portPRIORITY_SHIFT 2 - #define portMAX_BINARY_POINT_VALUE 1 + #define portPRIORITY_SHIFT 2 + #define portMAX_BINARY_POINT_VALUE 1 #elif configUNIQUE_INTERRUPT_PRIORITIES == 128 - #define portPRIORITY_SHIFT 1 - #define portMAX_BINARY_POINT_VALUE 0 + #define portPRIORITY_SHIFT 1 + #define portMAX_BINARY_POINT_VALUE 0 #elif configUNIQUE_INTERRUPT_PRIORITIES == 256 - #define portPRIORITY_SHIFT 0 - #define portMAX_BINARY_POINT_VALUE 0 -#else - #error Invalid configUNIQUE_INTERRUPT_PRIORITIES setting. configUNIQUE_INTERRUPT_PRIORITIES must be set to the number of unique priorities implemented by the target hardware -#endif + #define portPRIORITY_SHIFT 0 + #define portMAX_BINARY_POINT_VALUE 0 +#else /* if configUNIQUE_INTERRUPT_PRIORITIES == 16 */ + #error "Invalid configUNIQUE_INTERRUPT_PRIORITIES setting. configUNIQUE_INTERRUPT_PRIORITIES must be set to the number of unique priorities implemented by the target hardware" +#endif /* if configUNIQUE_INTERRUPT_PRIORITIES == 16 */ /* A critical section is exited when the critical section nesting count reaches -this value. */ -#define portNO_CRITICAL_NESTING ( ( uint32_t ) 0 ) + * this value. */ +#define portNO_CRITICAL_NESTING ( ( uint32_t ) 0 ) /* In all GICs 255 can be written to the priority mask register to unmask all -(but the lowest) interrupt priority. */ -#define portUNMASK_VALUE ( 0xFFUL ) + * (but the lowest) interrupt priority. */ +#define portUNMASK_VALUE ( 0xFFUL ) /* Tasks are not created with a floating point context, but can be given a -floating point context after they have been created. A variable is stored as -part of the tasks context that holds portNO_FLOATING_POINT_CONTEXT if the task -does not have an FPU context, or any other value if the task does have an FPU -context. */ -#define portNO_FLOATING_POINT_CONTEXT ( ( StackType_t ) 0 ) + * floating point context after they have been created. A variable is stored as + * part of the tasks context that holds portNO_FLOATING_POINT_CONTEXT if the task + * does not have an FPU context, or any other value if the task does have an FPU + * context. */ +#define portNO_FLOATING_POINT_CONTEXT ( ( StackType_t ) 0 ) /* Interrupt controller access addresses. */ -#define portICCPMR_PRIORITY_MASK_OFFSET ( 0x04 ) -#define portICCIAR_INTERRUPT_ACKNOWLEDGE_OFFSET ( 0x0C ) -#define portICCEOIR_END_OF_INTERRUPT_OFFSET ( 0x10 ) -#define portICCBPR_BINARY_POINT_OFFSET ( 0x08 ) -#define portICCRPR_RUNNING_PRIORITY_OFFSET ( 0x14 ) -#define portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS ( configINTERRUPT_CONTROLLER_BASE_ADDRESS + configINTERRUPT_CONTROLLER_CPU_INTERFACE_OFFSET ) -#define portICCPMR_PRIORITY_MASK_REGISTER ( *( ( volatile uint32_t * ) ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCPMR_PRIORITY_MASK_OFFSET ) ) ) -#define portICCIAR_INTERRUPT_ACKNOWLEDGE_REGISTER_ADDRESS ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCIAR_INTERRUPT_ACKNOWLEDGE_OFFSET ) -#define portICCEOIR_END_OF_INTERRUPT_REGISTER_ADDRESS ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCEOIR_END_OF_INTERRUPT_OFFSET ) -#define portICCPMR_PRIORITY_MASK_REGISTER_ADDRESS ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCPMR_PRIORITY_MASK_OFFSET ) -#define portICCBPR_BINARY_POINT_REGISTER ( *( ( const volatile uint32_t * ) ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCBPR_BINARY_POINT_OFFSET ) ) ) -#define portICCRPR_RUNNING_PRIORITY_REGISTER ( *( ( const volatile uint32_t * ) ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCRPR_RUNNING_PRIORITY_OFFSET ) ) ) +#define portICCPMR_PRIORITY_MASK_OFFSET ( 0x04 ) +#define portICCIAR_INTERRUPT_ACKNOWLEDGE_OFFSET ( 0x0C ) +#define portICCEOIR_END_OF_INTERRUPT_OFFSET ( 0x10 ) +#define portICCBPR_BINARY_POINT_OFFSET ( 0x08 ) +#define portICCRPR_RUNNING_PRIORITY_OFFSET ( 0x14 ) +#define portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS ( configINTERRUPT_CONTROLLER_BASE_ADDRESS + configINTERRUPT_CONTROLLER_CPU_INTERFACE_OFFSET ) +#define portICCPMR_PRIORITY_MASK_REGISTER ( *( ( volatile uint32_t * ) ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCPMR_PRIORITY_MASK_OFFSET ) ) ) +#define portICCIAR_INTERRUPT_ACKNOWLEDGE_REGISTER_ADDRESS ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCIAR_INTERRUPT_ACKNOWLEDGE_OFFSET ) +#define portICCEOIR_END_OF_INTERRUPT_REGISTER_ADDRESS ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCEOIR_END_OF_INTERRUPT_OFFSET ) +#define portICCPMR_PRIORITY_MASK_REGISTER_ADDRESS ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCPMR_PRIORITY_MASK_OFFSET ) +#define portICCBPR_BINARY_POINT_REGISTER ( *( ( const volatile uint32_t * ) ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCBPR_BINARY_POINT_OFFSET ) ) ) +#define portICCRPR_RUNNING_PRIORITY_REGISTER ( *( ( const volatile uint32_t * ) ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCRPR_RUNNING_PRIORITY_OFFSET ) ) ) /* Used by portASSERT_IF_INTERRUPT_PRIORITY_INVALID() when ensuring the binary -point is zero. */ -#define portBINARY_POINT_BITS ( ( uint8_t ) 0x03 ) + * point is zero. */ +#define portBINARY_POINT_BITS ( ( uint8_t ) 0x03 ) /* Constants required to setup the initial task context. */ -#define portINITIAL_SPSR ( ( StackType_t ) 0x1f ) /* System mode, ARM mode, interrupts enabled. */ -#define portTHUMB_MODE_BIT ( ( StackType_t ) 0x20 ) -#define portTHUMB_MODE_ADDRESS ( 0x01UL ) +#define portINITIAL_SPSR ( ( StackType_t ) 0x1f ) /* System mode, ARM mode, interrupts enabled. */ +#define portTHUMB_MODE_BIT ( ( StackType_t ) 0x20 ) +#define portTHUMB_MODE_ADDRESS ( 0x01UL ) /* Masks all bits in the APSR other than the mode bits. */ -#define portAPSR_MODE_BITS_MASK ( 0x1F ) +#define portAPSR_MODE_BITS_MASK ( 0x1F ) /* The value of the mode bits in the APSR when the CPU is executing in user -mode. */ -#define portAPSR_USER_MODE ( 0x10 ) + * mode. */ +#define portAPSR_USER_MODE ( 0x10 ) /* Macro to unmask all interrupt priorities. */ -#define portCLEAR_INTERRUPT_MASK() \ -{ \ - __disable_irq(); \ - portICCPMR_PRIORITY_MASK_REGISTER = portUNMASK_VALUE; \ - __asm( "DSB \n" \ - "ISB \n" ); \ - __enable_irq(); \ -} +#define portCLEAR_INTERRUPT_MASK() \ + { \ + __disable_irq(); \ + portICCPMR_PRIORITY_MASK_REGISTER = portUNMASK_VALUE; \ + __asm( "DSB \n" \ + "ISB \n" ); \ + __enable_irq(); \ + } /*-----------------------------------------------------------*/ @@ -169,29 +169,29 @@ static void prvTaskExitError( void ); /*-----------------------------------------------------------*/ /* A variable is used to keep track of the critical section nesting. This -variable has to be stored as part of the task context and must be initialised to -a non zero value to ensure interrupts don't inadvertently become unmasked before -the scheduler starts. As it is stored as part of the task context it will -automatically be set to 0 when the first task is started. */ + * variable has to be stored as part of the task context and must be initialised to + * a non zero value to ensure interrupts don't inadvertently become unmasked before + * the scheduler starts. As it is stored as part of the task context it will + * automatically be set to 0 when the first task is started. */ volatile uint32_t ulCriticalNesting = 9999UL; /* Used to pass constants into the ASM code. The address at which variables are -placed is the constant value so indirect loads in the asm code are not -required. */ + * placed is the constant value so indirect loads in the asm code are not + * required. */ uint32_t ulICCIAR __attribute__( ( at( portICCIAR_INTERRUPT_ACKNOWLEDGE_REGISTER_ADDRESS ) ) ); uint32_t ulICCEOIR __attribute__( ( at( portICCEOIR_END_OF_INTERRUPT_REGISTER_ADDRESS ) ) ); uint32_t ulICCPMR __attribute__( ( at( portICCPMR_PRIORITY_MASK_REGISTER_ADDRESS ) ) ); uint32_t ulAsmAPIPriorityMask __attribute__( ( at( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT ) ) ); /* Saved as part of the task context. If ulPortTaskHasFPUContext is non-zero then -a floating point context must be saved and restored for the task. */ + * a floating point context must be saved and restored for the task. */ uint32_t ulPortTaskHasFPUContext = pdFALSE; /* Set to 1 to pend a context switch from an ISR. */ uint32_t ulPortYieldRequired = pdFALSE; /* Counts the interrupt nesting depth. A context switch is only performed if -if the nesting depth is 0. */ + * if the nesting depth is 0. */ uint32_t ulPortInterruptNesting = 0UL; /*-----------------------------------------------------------*/ @@ -199,14 +199,16 @@ uint32_t ulPortInterruptNesting = 0UL; /* * See header file for description. */ -StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters ) +StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, + TaskFunction_t pxCode, + void * pvParameters ) { /* Setup the initial stack of the task. The stack is set exactly as - expected by the portRESTORE_CONTEXT() macro. - - The fist real value on the stack is the status register, which is set for - system mode, with interrupts enabled. A few NULLs are added first to ensure - GDB does not try decoding a non-existent return address. */ + * expected by the portRESTORE_CONTEXT() macro. + * + * The fist real value on the stack is the status register, which is set for + * system mode, with interrupts enabled. A few NULLs are added first to ensure + * GDB does not try decoding a non-existent return address. */ *pxTopOfStack = NULL; pxTopOfStack--; *pxTopOfStack = NULL; @@ -228,43 +230,43 @@ StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t px pxTopOfStack--; /* Next all the registers other than the stack pointer. */ - *pxTopOfStack = ( StackType_t ) prvTaskExitError; /* R14 */ + *pxTopOfStack = ( StackType_t ) prvTaskExitError; /* R14 */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x12121212; /* R12 */ + *pxTopOfStack = ( StackType_t ) 0x12121212; /* R12 */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x11111111; /* R11 */ + *pxTopOfStack = ( StackType_t ) 0x11111111; /* R11 */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x10101010; /* R10 */ + *pxTopOfStack = ( StackType_t ) 0x10101010; /* R10 */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x09090909; /* R9 */ + *pxTopOfStack = ( StackType_t ) 0x09090909; /* R9 */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x08080808; /* R8 */ + *pxTopOfStack = ( StackType_t ) 0x08080808; /* R8 */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x07070707; /* R7 */ + *pxTopOfStack = ( StackType_t ) 0x07070707; /* R7 */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x06060606; /* R6 */ + *pxTopOfStack = ( StackType_t ) 0x06060606; /* R6 */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x05050505; /* R5 */ + *pxTopOfStack = ( StackType_t ) 0x05050505; /* R5 */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x04040404; /* R4 */ + *pxTopOfStack = ( StackType_t ) 0x04040404; /* R4 */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x03030303; /* R3 */ + *pxTopOfStack = ( StackType_t ) 0x03030303; /* R3 */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x02020202; /* R2 */ + *pxTopOfStack = ( StackType_t ) 0x02020202; /* R2 */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x01010101; /* R1 */ + *pxTopOfStack = ( StackType_t ) 0x01010101; /* R1 */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */ + *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */ pxTopOfStack--; /* The task will start with a critical nesting count of 0 as interrupts are - enabled. */ + * enabled. */ *pxTopOfStack = portNO_CRITICAL_NESTING; pxTopOfStack--; /* The task will start without a floating point context. A task that uses - the floating point hardware must call vPortTaskUsesFPU() before executing - any floating point instructions. */ + * the floating point hardware must call vPortTaskUsesFPU() before executing + * any floating point instructions. */ *pxTopOfStack = portNO_FLOATING_POINT_CONTEXT; return pxTopOfStack; @@ -274,23 +276,26 @@ StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t px static void prvTaskExitError( void ) { /* A function that implements a task must not exit or attempt to return to - its caller as there is nothing to return to. If a task wants to exit it - should instead call vTaskDelete( NULL ). - - Artificially force an assert() to be triggered if configASSERT() is - defined, then stop here so application writers can catch the error. */ + * its caller as there is nothing to return to. If a task wants to exit it + * should instead call vTaskDelete( NULL ). + * + * Artificially force an assert() to be triggered if configASSERT() is + * defined, then stop here so application writers can catch the error. */ configASSERT( ulPortInterruptNesting == ~0UL ); portDISABLE_INTERRUPTS(); - for( ;; ); + + for( ; ; ) + { + } } /*-----------------------------------------------------------*/ BaseType_t xPortStartScheduler( void ) { -uint32_t ulAPSR; + uint32_t ulAPSR; /* Only continue if the CPU is not in User mode. The CPU must be in a - Privileged mode for the scheduler to start. */ + * Privileged mode for the scheduler to start. */ __asm( "MRS ulAPSR, APSR" ); ulAPSR &= portAPSR_MODE_BITS_MASK; configASSERT( ulAPSR != portAPSR_USER_MODE ); @@ -298,8 +303,8 @@ uint32_t ulAPSR; if( ulAPSR != portAPSR_USER_MODE ) { /* Only continue if the binary point value is set to its lowest possible - setting. See the comments in vPortValidateInterruptPriority() below for - more information. */ + * setting. See the comments in vPortValidateInterruptPriority() below for + * more information. */ configASSERT( ( portICCBPR_BINARY_POINT_REGISTER & portBINARY_POINT_BITS ) <= portMAX_BINARY_POINT_VALUE ); if( ( portICCBPR_BINARY_POINT_REGISTER & portBINARY_POINT_BITS ) <= portMAX_BINARY_POINT_VALUE ) @@ -313,8 +318,8 @@ uint32_t ulAPSR; } /* Will only get here if vTaskStartScheduler() was called with the CPU in - a non-privileged mode or the binary point register was not set to its lowest - possible value. */ + * a non-privileged mode or the binary point register was not set to its lowest + * possible value. */ return 0; } /*-----------------------------------------------------------*/ @@ -322,7 +327,7 @@ uint32_t ulAPSR; void vPortEndScheduler( void ) { /* Not implemented in ports where there is nothing to return to. - Artificially force an assert. */ + * Artificially force an assert. */ configASSERT( ulCriticalNesting == 1000UL ); } /*-----------------------------------------------------------*/ @@ -332,16 +337,16 @@ void vPortEnterCritical( void ) /* Disable interrupts as per portDISABLE_INTERRUPTS(); */ ulPortSetInterruptMask(); - /* Now interrupts are disabled ulCriticalNesting can be accessed - directly. Increment ulCriticalNesting to keep a count of how many times - portENTER_CRITICAL() has been called. */ + /* Now that interrupts are disabled, ulCriticalNesting can be accessed + * directly. Increment ulCriticalNesting to keep a count of how many times + * portENTER_CRITICAL() has been called. */ ulCriticalNesting++; /* This is not the interrupt safe version of the enter critical function so - assert() if it is being called from an interrupt context. Only API - functions that end in "FromISR" can be used in an interrupt. Only assert if - the critical nesting count is 1 to protect against recursive calls if the - assert function also uses a critical section. */ + * assert() if it is being called from an interrupt context. Only API + * functions that end in "FromISR" can be used in an interrupt. Only assert if + * the critical nesting count is 1 to protect against recursive calls if the + * assert function also uses a critical section. */ if( ulCriticalNesting == 1 ) { configASSERT( ulPortInterruptNesting == 0 ); @@ -354,15 +359,15 @@ void vPortExitCritical( void ) if( ulCriticalNesting > portNO_CRITICAL_NESTING ) { /* Decrement the nesting count as the critical section is being - exited. */ + * exited. */ ulCriticalNesting--; /* If the nesting level has reached zero then all interrupt - priorities must be re-enabled. */ + * priorities must be re-enabled. */ if( ulCriticalNesting == portNO_CRITICAL_NESTING ) { /* Critical nesting has reached zero so all interrupt priorities - should be unmasked. */ + * should be unmasked. */ portCLEAR_INTERRUPT_MASK(); } } @@ -372,12 +377,12 @@ void vPortExitCritical( void ) void FreeRTOS_Tick_Handler( void ) { /* Set interrupt mask before altering scheduler structures. The tick - handler runs at the lowest priority, so interrupts cannot already be masked, - so there is no need to save and restore the current mask value. */ + * handler runs at the lowest priority, so interrupts cannot already be masked, + * so there is no need to save and restore the current mask value. */ __disable_irq(); portICCPMR_PRIORITY_MASK_REGISTER = ( uint32_t ) ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT ); - __asm( "DSB \n" - "ISB \n" ); + __asm( "DSB \n" + "ISB \n" ); __enable_irq(); /* Increment the RTOS tick. */ @@ -394,10 +399,10 @@ void FreeRTOS_Tick_Handler( void ) void vPortTaskUsesFPU( void ) { -uint32_t ulInitialFPSCR = 0; + uint32_t ulInitialFPSCR = 0; /* A task is registering the fact that it needs an FPU context. Set the - FPU flag (which is saved as part of the task context). */ + * FPU flag (which is saved as part of the task context). */ ulPortTaskHasFPUContext = pdTRUE; /* Initialise the floating point status register. */ @@ -416,9 +421,10 @@ void vPortClearInterruptMask( uint32_t ulNewMaskValue ) uint32_t ulPortSetInterruptMask( void ) { -uint32_t ulReturn; + uint32_t ulReturn; __disable_irq(); + if( portICCPMR_PRIORITY_MASK_REGISTER == ( uint32_t ) ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT ) ) { /* Interrupts were already masked. */ @@ -428,49 +434,50 @@ uint32_t ulReturn; { ulReturn = pdFALSE; portICCPMR_PRIORITY_MASK_REGISTER = ( uint32_t ) ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT ); - __asm( "DSB \n" - "ISB \n" ); + __asm( "DSB \n" + "ISB \n" ); } + __enable_irq(); return ulReturn; } /*-----------------------------------------------------------*/ -#if( configASSERT_DEFINED == 1 ) +#if ( configASSERT_DEFINED == 1 ) void vPortValidateInterruptPriority( void ) { /* The following assertion will fail if a service routine (ISR) for - an interrupt that has been assigned a priority above - configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API - function. ISR safe FreeRTOS API functions must *only* be called - from interrupts that have been assigned a priority at or below - configMAX_SYSCALL_INTERRUPT_PRIORITY. - - Numerically low interrupt priority numbers represent logically high - interrupt priorities, therefore the priority of the interrupt must - be set to a value equal to or numerically *higher* than - configMAX_SYSCALL_INTERRUPT_PRIORITY. - - FreeRTOS maintains separate thread and ISR API functions to ensure - interrupt entry is as fast and simple as possible. - - The following links provide detailed information: - https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html - https://www.FreeRTOS.org/FAQHelp.html */ + * an interrupt that has been assigned a priority above + * configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API + * function. ISR safe FreeRTOS API functions must *only* be called + * from interrupts that have been assigned a priority at or below + * configMAX_SYSCALL_INTERRUPT_PRIORITY. + * + * Numerically low interrupt priority numbers represent logically high + * interrupt priorities, therefore the priority of the interrupt must + * be set to a value equal to or numerically *higher* than + * configMAX_SYSCALL_INTERRUPT_PRIORITY. + * + * FreeRTOS maintains separate thread and ISR API functions to ensure + * interrupt entry is as fast and simple as possible. + * + * The following links provide detailed information: + * https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html + * https://www.FreeRTOS.org/FAQHelp.html */ configASSERT( portICCRPR_RUNNING_PRIORITY_REGISTER >= ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT ) ); /* Priority grouping: The interrupt controller (GIC) allows the bits - that define each interrupt's priority to be split between bits that - define the interrupt's pre-emption priority bits and bits that define - the interrupt's sub-priority. For simplicity all bits must be defined - to be pre-emption priority bits. The following assertion will fail if - this is not the case (if some bits represent a sub-priority). - - The priority grouping is configured by the GIC's binary point register - (ICCBPR). Writting 0 to ICCBPR will ensure it is set to its lowest - possible value (which may be above 0). */ + * that define each interrupt's priority to be split between bits that + * define the interrupt's pre-emption priority bits and bits that define + * the interrupt's sub-priority. For simplicity all bits must be defined + * to be pre-emption priority bits. The following assertion will fail if + * this is not the case (if some bits represent a sub-priority). + * + * The priority grouping is configured by the GIC's binary point register + * (ICCBPR). Writting 0 to ICCBPR will ensure it is set to its lowest + * possible value (which may be above 0). */ configASSERT( portICCBPR_BINARY_POINT_REGISTER <= portMAX_BINARY_POINT_VALUE ); } diff --git a/Source/portable/RVDS/ARM_CA9/portASM.s b/Source/portable/RVDS/ARM_CA9/portASM.s index bd36f2ebe..1b4a8fbe2 100644 --- a/Source/portable/RVDS/ARM_CA9/portASM.s +++ b/Source/portable/RVDS/ARM_CA9/portASM.s @@ -1,5 +1,5 @@ ;/* -; * FreeRTOS Kernel V10.6.2 +; * FreeRTOS Kernel V11.0.1 ; * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. ; * ; * SPDX-License-Identifier: MIT diff --git a/Source/portable/RVDS/ARM_CA9/portmacro.h b/Source/portable/RVDS/ARM_CA9/portmacro.h index 35e48871e..cb5e167fc 100644 --- a/Source/portable/RVDS/ARM_CA9/portmacro.h +++ b/Source/portable/RVDS/ARM_CA9/portmacro.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -46,61 +46,61 @@ */ /* Type definitions. */ -#define portCHAR char -#define portFLOAT float -#define portDOUBLE double -#define portLONG long -#define portSHORT short -#define portSTACK_TYPE uint32_t -#define portBASE_TYPE long - -typedef portSTACK_TYPE StackType_t; -typedef long BaseType_t; -typedef unsigned long UBaseType_t; - - -#if( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS ) - typedef uint16_t TickType_t; - #define portMAX_DELAY ( TickType_t ) 0xffff +#define portCHAR char +#define portFLOAT float +#define portDOUBLE double +#define portLONG long +#define portSHORT short +#define portSTACK_TYPE uint32_t +#define portBASE_TYPE long + +typedef portSTACK_TYPE StackType_t; +typedef long BaseType_t; +typedef unsigned long UBaseType_t; + + +#if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS ) + typedef uint16_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffff #elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS ) - typedef uint32_t TickType_t; - #define portMAX_DELAY ( TickType_t ) 0xffffffffUL + typedef uint32_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffffffffUL - /* 32-bit tick type on a 32-bit architecture, so reads of the tick count do - not need to be guarded with a critical section. */ - #define portTICK_TYPE_IS_ATOMIC 1 +/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do + * not need to be guarded with a critical section. */ + #define portTICK_TYPE_IS_ATOMIC 1 #else #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width. #endif /*-----------------------------------------------------------*/ /* Hardware specifics. */ -#define portSTACK_GROWTH ( -1 ) -#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) -#define portBYTE_ALIGNMENT 8 +#define portSTACK_GROWTH ( -1 ) +#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) +#define portBYTE_ALIGNMENT 8 /*-----------------------------------------------------------*/ /* Task utilities. */ /* Called at the end of an ISR that can cause a context switch. */ -#define portEND_SWITCHING_ISR( xSwitchRequired )\ -{ \ -extern uint32_t ulPortYieldRequired; \ - \ - if( xSwitchRequired != pdFALSE ) \ - { \ - ulPortYieldRequired = pdTRUE; \ - } \ -} +#define portEND_SWITCHING_ISR( xSwitchRequired ) \ + { \ + extern uint32_t ulPortYieldRequired; \ + \ + if( xSwitchRequired != pdFALSE ) \ + { \ + ulPortYieldRequired = pdTRUE; \ + } \ + } -#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x ) -#define portYIELD() __asm( "SWI 0" ); +#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x ) +#define portYIELD() __asm( "SWI 0" ); /*----------------------------------------------------------- - * Critical section control - *----------------------------------------------------------*/ +* Critical section control +*----------------------------------------------------------*/ extern void vPortEnterCritical( void ); extern void vPortExitCritical( void ); @@ -108,57 +108,57 @@ extern uint32_t ulPortSetInterruptMask( void ); extern void vPortClearInterruptMask( uint32_t ulNewMaskValue ); /* These macros do not globally disable/enable interrupts. They do mask off -interrupts that have a priority below configMAX_API_CALL_INTERRUPT_PRIORITY. */ -#define portENTER_CRITICAL() vPortEnterCritical(); -#define portEXIT_CRITICAL() vPortExitCritical(); -#define portDISABLE_INTERRUPTS() ulPortSetInterruptMask() -#define portENABLE_INTERRUPTS() vPortClearInterruptMask( 0 ) -#define portSET_INTERRUPT_MASK_FROM_ISR() ulPortSetInterruptMask() -#define portCLEAR_INTERRUPT_MASK_FROM_ISR(x) vPortClearInterruptMask(x) + * interrupts that have a priority below configMAX_API_CALL_INTERRUPT_PRIORITY. */ +#define portENTER_CRITICAL() vPortEnterCritical(); +#define portEXIT_CRITICAL() vPortExitCritical(); +#define portDISABLE_INTERRUPTS() ulPortSetInterruptMask() +#define portENABLE_INTERRUPTS() vPortClearInterruptMask( 0 ) +#define portSET_INTERRUPT_MASK_FROM_ISR() ulPortSetInterruptMask() +#define portCLEAR_INTERRUPT_MASK_FROM_ISR( x ) vPortClearInterruptMask( x ) /*-----------------------------------------------------------*/ /* Task function macros as described on the FreeRTOS.org WEB site. These are -not required for this port but included in case common demo code that uses these -macros is used. */ -#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters ) -#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters ) + * not required for this port but included in case common demo code that uses these + * macros is used. */ +#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters ) +#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters ) /* Prototype of the FreeRTOS tick handler. This must be installed as the -handler for whichever peripheral is used to generate the RTOS tick. */ + * handler for whichever peripheral is used to generate the RTOS tick. */ void FreeRTOS_Tick_Handler( void ); /* Any task that uses the floating point unit MUST call vPortTaskUsesFPU() -before any floating point instructions are executed. */ + * before any floating point instructions are executed. */ void vPortTaskUsesFPU( void ); -#define portTASK_USES_FLOATING_POINT() vPortTaskUsesFPU() +#define portTASK_USES_FLOATING_POINT() vPortTaskUsesFPU() -#define portLOWEST_INTERRUPT_PRIORITY ( ( ( uint32_t ) configUNIQUE_INTERRUPT_PRIORITIES ) - 1UL ) -#define portLOWEST_USABLE_INTERRUPT_PRIORITY ( portLOWEST_INTERRUPT_PRIORITY - 1UL ) +#define portLOWEST_INTERRUPT_PRIORITY ( ( ( uint32_t ) configUNIQUE_INTERRUPT_PRIORITIES ) - 1UL ) +#define portLOWEST_USABLE_INTERRUPT_PRIORITY ( portLOWEST_INTERRUPT_PRIORITY - 1UL ) /* Architecture specific optimisations. */ #ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION - #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1 + #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1 #endif #if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 - /* Store/clear the ready priorities in a bit map. */ - #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) ) - #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) ) +/* Store/clear the ready priorities in a bit map. */ + #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) ) + #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) ) - /*-----------------------------------------------------------*/ +/*-----------------------------------------------------------*/ - #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31 - __clz( uxReadyPriorities ) ) + #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31 - __clz( uxReadyPriorities ) ) #endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */ #ifdef configASSERT void vPortValidateInterruptPriority( void ); - #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() vPortValidateInterruptPriority() + #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() vPortValidateInterruptPriority() #endif -#define portNOP() __nop() +#define portNOP() __nop() /* *INDENT-OFF* */ #ifdef __cplusplus diff --git a/Source/portable/RVDS/ARM_CA9/portmacro.inc b/Source/portable/RVDS/ARM_CA9/portmacro.inc index cfcdc581f..26bb4acf9 100644 --- a/Source/portable/RVDS/ARM_CA9/portmacro.inc +++ b/Source/portable/RVDS/ARM_CA9/portmacro.inc @@ -1,5 +1,5 @@ ;/* -; * FreeRTOS Kernel V10.6.2 +; * FreeRTOS Kernel V11.0.1 ; * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. ; * ; * SPDX-License-Identifier: MIT diff --git a/Source/portable/RVDS/ARM_CM0/port.c b/Source/portable/RVDS/ARM_CM0/port.c index 169e262ff..e919a52c0 100644 --- a/Source/portable/RVDS/ARM_CM0/port.c +++ b/Source/portable/RVDS/ARM_CM0/port.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -352,13 +352,19 @@ void xPortSysTickHandler( void ) uint32_t ulPreviousMask; ulPreviousMask = portSET_INTERRUPT_MASK_FROM_ISR(); + traceISR_ENTER(); { /* Increment the RTOS tick. */ if( xTaskIncrementTick() != pdFALSE ) { + traceISR_EXIT_TO_SCHEDULER(); /* Pend a context switch. */ portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; } + else + { + traceISR_EXIT(); + } } portCLEAR_INTERRUPT_MASK_FROM_ISR( ulPreviousMask ); } diff --git a/Source/portable/RVDS/ARM_CM0/portmacro.h b/Source/portable/RVDS/ARM_CM0/portmacro.h index e75c8efa7..6e0a60ef1 100644 --- a/Source/portable/RVDS/ARM_CM0/portmacro.h +++ b/Source/portable/RVDS/ARM_CM0/portmacro.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -86,9 +86,19 @@ extern void vPortYield( void ); #define portNVIC_INT_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed04 ) ) #define portNVIC_PENDSVSET_BIT ( 1UL << 28UL ) #define portYIELD() vPortYield() -#define portEND_SWITCHING_ISR( xSwitchRequired ) \ - do { if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; } \ - while( 0 ) +#define portEND_SWITCHING_ISR( xSwitchRequired ) \ + do \ + { \ + if( xSwitchRequired ) \ + { \ + traceISR_EXIT_TO_SCHEDULER(); \ + portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; \ + } \ + else \ + { \ + traceISR_EXIT(); \ + } \ + } while( 0 ) #define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x ) /*-----------------------------------------------------------*/ diff --git a/Source/portable/RVDS/ARM_CM3/port.c b/Source/portable/RVDS/ARM_CM3/port.c index d39491dd2..95a4d0ecc 100644 --- a/Source/portable/RVDS/ARM_CM3/port.c +++ b/Source/portable/RVDS/ARM_CM3/port.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -310,22 +310,22 @@ BaseType_t xPortStartScheduler( void ) if( ulImplementedPrioBits == 8 ) { /* When the hardware implements 8 priority bits, there is no way for - * the software to configure PRIGROUP to not have sub-priorities. As - * a result, the least significant bit is always used for sub-priority - * and there are 128 preemption priorities and 2 sub-priorities. - * - * This may cause some confusion in some cases - for example, if - * configMAX_SYSCALL_INTERRUPT_PRIORITY is set to 5, both 5 and 4 - * priority interrupts will be masked in Critical Sections as those - * are at the same preemption priority. This may appear confusing as - * 4 is higher (numerically lower) priority than - * configMAX_SYSCALL_INTERRUPT_PRIORITY and therefore, should not - * have been masked. Instead, if we set configMAX_SYSCALL_INTERRUPT_PRIORITY - * to 4, this confusion does not happen and the behaviour remains the same. - * - * The following assert ensures that the sub-priority bit in the - * configMAX_SYSCALL_INTERRUPT_PRIORITY is clear to avoid the above mentioned - * confusion. */ + * the software to configure PRIGROUP to not have sub-priorities. As + * a result, the least significant bit is always used for sub-priority + * and there are 128 preemption priorities and 2 sub-priorities. + * + * This may cause some confusion in some cases - for example, if + * configMAX_SYSCALL_INTERRUPT_PRIORITY is set to 5, both 5 and 4 + * priority interrupts will be masked in Critical Sections as those + * are at the same preemption priority. This may appear confusing as + * 4 is higher (numerically lower) priority than + * configMAX_SYSCALL_INTERRUPT_PRIORITY and therefore, should not + * have been masked. Instead, if we set configMAX_SYSCALL_INTERRUPT_PRIORITY + * to 4, this confusion does not happen and the behaviour remains the same. + * + * The following assert ensures that the sub-priority bit in the + * configMAX_SYSCALL_INTERRUPT_PRIORITY is clear to avoid the above mentioned + * confusion. */ configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & 0x1U ) == 0U ); ulMaxPRIGROUPValue = 0; } @@ -449,14 +449,21 @@ void xPortSysTickHandler( void ) * known - therefore the slightly faster vPortRaiseBASEPRI() function is used * in place of portSET_INTERRUPT_MASK_FROM_ISR(). */ vPortRaiseBASEPRI(); + traceISR_ENTER(); { /* Increment the RTOS tick. */ if( xTaskIncrementTick() != pdFALSE ) { + traceISR_EXIT_TO_SCHEDULER(); + /* A context switch is required. Context switching is performed in * the PendSV interrupt. Pend the PendSV interrupt. */ portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; } + else + { + traceISR_EXIT(); + } } vPortClearBASEPRIFromISR(); diff --git a/Source/portable/RVDS/ARM_CM3/portmacro.h b/Source/portable/RVDS/ARM_CM3/portmacro.h index 245522068..70a9e5ea2 100644 --- a/Source/portable/RVDS/ARM_CM3/portmacro.h +++ b/Source/portable/RVDS/ARM_CM3/portmacro.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -47,45 +47,45 @@ */ /* Type definitions. */ - #define portCHAR char - #define portFLOAT float - #define portDOUBLE double - #define portLONG long - #define portSHORT short - #define portSTACK_TYPE uint32_t - #define portBASE_TYPE long - - typedef portSTACK_TYPE StackType_t; - typedef long BaseType_t; - typedef unsigned long UBaseType_t; - - #if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS ) - typedef uint16_t TickType_t; - #define portMAX_DELAY ( TickType_t ) 0xffff - #elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS ) - typedef uint32_t TickType_t; - #define portMAX_DELAY ( TickType_t ) 0xffffffffUL +#define portCHAR char +#define portFLOAT float +#define portDOUBLE double +#define portLONG long +#define portSHORT short +#define portSTACK_TYPE uint32_t +#define portBASE_TYPE long + +typedef portSTACK_TYPE StackType_t; +typedef long BaseType_t; +typedef unsigned long UBaseType_t; + +#if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS ) + typedef uint16_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffff +#elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS ) + typedef uint32_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffffffffUL /* 32-bit tick type on a 32-bit architecture, so reads of the tick count do * not need to be guarded with a critical section. */ - #define portTICK_TYPE_IS_ATOMIC 1 - #else - #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width. - #endif + #define portTICK_TYPE_IS_ATOMIC 1 +#else + #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width. +#endif /*-----------------------------------------------------------*/ /* Architecture specifics. */ - #define portSTACK_GROWTH ( -1 ) - #define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) - #define portBYTE_ALIGNMENT 8 +#define portSTACK_GROWTH ( -1 ) +#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) +#define portBYTE_ALIGNMENT 8 /* Constants used with memory barrier intrinsics. */ - #define portSY_FULL_READ_WRITE ( 15 ) +#define portSY_FULL_READ_WRITE ( 15 ) /*-----------------------------------------------------------*/ /* Scheduler utilities. */ - #define portYIELD() \ +#define portYIELD() \ { \ /* Set a PendSV to request a context switch. */ \ portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; \ @@ -97,167 +97,179 @@ } /*-----------------------------------------------------------*/ - #define portNVIC_INT_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed04 ) ) - #define portNVIC_PENDSVSET_BIT ( 1UL << 28UL ) - #define portEND_SWITCHING_ISR( xSwitchRequired ) do { if( xSwitchRequired != pdFALSE ) portYIELD(); } while( 0 ) - #define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x ) +#define portNVIC_INT_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed04 ) ) +#define portNVIC_PENDSVSET_BIT ( 1UL << 28UL ) +#define portEND_SWITCHING_ISR( xSwitchRequired ) \ + do \ + { \ + if( xSwitchRequired != pdFALSE ) \ + { \ + traceISR_EXIT_TO_SCHEDULER(); \ + portYIELD(); \ + } \ + else \ + { \ + traceISR_EXIT(); \ + } \ + } while( 0 ) +#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x ) /*-----------------------------------------------------------*/ /* Critical section management. */ - extern void vPortEnterCritical( void ); - extern void vPortExitCritical( void ); +extern void vPortEnterCritical( void ); +extern void vPortExitCritical( void ); - #define portDISABLE_INTERRUPTS() vPortRaiseBASEPRI() - #define portENABLE_INTERRUPTS() vPortSetBASEPRI( 0 ) - #define portENTER_CRITICAL() vPortEnterCritical() - #define portEXIT_CRITICAL() vPortExitCritical() - #define portSET_INTERRUPT_MASK_FROM_ISR() ulPortRaiseBASEPRI() - #define portCLEAR_INTERRUPT_MASK_FROM_ISR( x ) vPortSetBASEPRI( x ) +#define portDISABLE_INTERRUPTS() vPortRaiseBASEPRI() +#define portENABLE_INTERRUPTS() vPortSetBASEPRI( 0 ) +#define portENTER_CRITICAL() vPortEnterCritical() +#define portEXIT_CRITICAL() vPortExitCritical() +#define portSET_INTERRUPT_MASK_FROM_ISR() ulPortRaiseBASEPRI() +#define portCLEAR_INTERRUPT_MASK_FROM_ISR( x ) vPortSetBASEPRI( x ) /*-----------------------------------------------------------*/ /* Tickless idle/low power functionality. */ - #ifndef portSUPPRESS_TICKS_AND_SLEEP - extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime ); - #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime ) vPortSuppressTicksAndSleep( xExpectedIdleTime ) - #endif +#ifndef portSUPPRESS_TICKS_AND_SLEEP + extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime ); + #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime ) vPortSuppressTicksAndSleep( xExpectedIdleTime ) +#endif /*-----------------------------------------------------------*/ /* Port specific optimisations. */ - #ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION - #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1 - #endif +#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION + #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1 +#endif - #if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 +#if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 /* Check the configuration. */ - #if ( configMAX_PRIORITIES > 32 ) - #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice. - #endif + #if ( configMAX_PRIORITIES > 32 ) + #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice. + #endif /* Store/clear the ready priorities in a bit map. */ - #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) ) - #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) ) + #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) ) + #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) ) /*-----------------------------------------------------------*/ - #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - ( uint32_t ) __clz( ( uxReadyPriorities ) ) ) + #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - ( uint32_t ) __clz( ( uxReadyPriorities ) ) ) - #endif /* taskRECORD_READY_PRIORITY */ +#endif /* taskRECORD_READY_PRIORITY */ /*-----------------------------------------------------------*/ /* Task function macros as described on the FreeRTOS.org WEB site. These are * not necessary for to use this port. They are defined so the common demo files * (which build with all the ports) will build. */ - #define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters ) - #define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters ) +#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters ) +#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters ) /*-----------------------------------------------------------*/ - #ifdef configASSERT - void vPortValidateInterruptPriority( void ); - #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() vPortValidateInterruptPriority() - #endif +#ifdef configASSERT + void vPortValidateInterruptPriority( void ); + #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() vPortValidateInterruptPriority() +#endif /* portNOP() is not required by this port. */ - #define portNOP() +#define portNOP() - #define portINLINE __inline +#define portINLINE __inline - #ifndef portFORCE_INLINE - #define portFORCE_INLINE __forceinline - #endif +#ifndef portFORCE_INLINE + #define portFORCE_INLINE __forceinline +#endif /*-----------------------------------------------------------*/ - static portFORCE_INLINE void vPortSetBASEPRI( uint32_t ulBASEPRI ) +static portFORCE_INLINE void vPortSetBASEPRI( uint32_t ulBASEPRI ) +{ + __asm { - __asm - { - /* Barrier instructions are not used as this function is only used to - * lower the BASEPRI value. */ + /* Barrier instructions are not used as this function is only used to + * lower the BASEPRI value. */ /* *INDENT-OFF* */ msr basepri, ulBASEPRI /* *INDENT-ON* */ - } } +} /*-----------------------------------------------------------*/ - static portFORCE_INLINE void vPortRaiseBASEPRI( void ) - { - uint32_t ulNewBASEPRI = configMAX_SYSCALL_INTERRUPT_PRIORITY; +static portFORCE_INLINE void vPortRaiseBASEPRI( void ) +{ + uint32_t ulNewBASEPRI = configMAX_SYSCALL_INTERRUPT_PRIORITY; - __asm - { - /* Set BASEPRI to the max syscall priority to effect a critical - * section. */ + __asm + { + /* Set BASEPRI to the max syscall priority to effect a critical + * section. */ /* *INDENT-OFF* */ msr basepri, ulNewBASEPRI dsb isb /* *INDENT-ON* */ - } } +} /*-----------------------------------------------------------*/ - static portFORCE_INLINE void vPortClearBASEPRIFromISR( void ) +static portFORCE_INLINE void vPortClearBASEPRIFromISR( void ) +{ + __asm { - __asm - { - /* Set BASEPRI to 0 so no interrupts are masked. This function is only - * used to lower the mask in an interrupt, so memory barriers are not - * used. */ + /* Set BASEPRI to 0 so no interrupts are masked. This function is only + * used to lower the mask in an interrupt, so memory barriers are not + * used. */ /* *INDENT-OFF* */ msr basepri, # 0 /* *INDENT-ON* */ - } } +} /*-----------------------------------------------------------*/ - static portFORCE_INLINE uint32_t ulPortRaiseBASEPRI( void ) - { - uint32_t ulReturn, ulNewBASEPRI = configMAX_SYSCALL_INTERRUPT_PRIORITY; +static portFORCE_INLINE uint32_t ulPortRaiseBASEPRI( void ) +{ + uint32_t ulReturn, ulNewBASEPRI = configMAX_SYSCALL_INTERRUPT_PRIORITY; - __asm - { - /* Set BASEPRI to the max syscall priority to effect a critical - * section. */ + __asm + { + /* Set BASEPRI to the max syscall priority to effect a critical + * section. */ /* *INDENT-OFF* */ mrs ulReturn, basepri msr basepri, ulNewBASEPRI dsb isb /* *INDENT-ON* */ - } - - return ulReturn; } + + return ulReturn; +} /*-----------------------------------------------------------*/ - static portFORCE_INLINE BaseType_t xPortIsInsideInterrupt( void ) - { - uint32_t ulCurrentInterrupt; - BaseType_t xReturn; +static portFORCE_INLINE BaseType_t xPortIsInsideInterrupt( void ) +{ + uint32_t ulCurrentInterrupt; + BaseType_t xReturn; - /* Obtain the number of the currently executing interrupt. */ - __asm - { + /* Obtain the number of the currently executing interrupt. */ + __asm + { /* *INDENT-OFF* */ mrs ulCurrentInterrupt, ipsr /* *INDENT-ON* */ - } - - if( ulCurrentInterrupt == 0 ) - { - xReturn = pdFALSE; - } - else - { - xReturn = pdTRUE; - } - - return xReturn; } + if( ulCurrentInterrupt == 0 ) + { + xReturn = pdFALSE; + } + else + { + xReturn = pdTRUE; + } + + return xReturn; +} + /* *INDENT-OFF* */ #ifdef __cplusplus diff --git a/Source/portable/RVDS/ARM_CM4F/port.c b/Source/portable/RVDS/ARM_CM4F/port.c index 05ef20ca9..040bede1a 100644 --- a/Source/portable/RVDS/ARM_CM4F/port.c +++ b/Source/portable/RVDS/ARM_CM4F/port.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -376,22 +376,22 @@ BaseType_t xPortStartScheduler( void ) if( ulImplementedPrioBits == 8 ) { /* When the hardware implements 8 priority bits, there is no way for - * the software to configure PRIGROUP to not have sub-priorities. As - * a result, the least significant bit is always used for sub-priority - * and there are 128 preemption priorities and 2 sub-priorities. - * - * This may cause some confusion in some cases - for example, if - * configMAX_SYSCALL_INTERRUPT_PRIORITY is set to 5, both 5 and 4 - * priority interrupts will be masked in Critical Sections as those - * are at the same preemption priority. This may appear confusing as - * 4 is higher (numerically lower) priority than - * configMAX_SYSCALL_INTERRUPT_PRIORITY and therefore, should not - * have been masked. Instead, if we set configMAX_SYSCALL_INTERRUPT_PRIORITY - * to 4, this confusion does not happen and the behaviour remains the same. - * - * The following assert ensures that the sub-priority bit in the - * configMAX_SYSCALL_INTERRUPT_PRIORITY is clear to avoid the above mentioned - * confusion. */ + * the software to configure PRIGROUP to not have sub-priorities. As + * a result, the least significant bit is always used for sub-priority + * and there are 128 preemption priorities and 2 sub-priorities. + * + * This may cause some confusion in some cases - for example, if + * configMAX_SYSCALL_INTERRUPT_PRIORITY is set to 5, both 5 and 4 + * priority interrupts will be masked in Critical Sections as those + * are at the same preemption priority. This may appear confusing as + * 4 is higher (numerically lower) priority than + * configMAX_SYSCALL_INTERRUPT_PRIORITY and therefore, should not + * have been masked. Instead, if we set configMAX_SYSCALL_INTERRUPT_PRIORITY + * to 4, this confusion does not happen and the behaviour remains the same. + * + * The following assert ensures that the sub-priority bit in the + * configMAX_SYSCALL_INTERRUPT_PRIORITY is clear to avoid the above mentioned + * confusion. */ configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & 0x1U ) == 0U ); ulMaxPRIGROUPValue = 0; } @@ -545,14 +545,21 @@ void xPortSysTickHandler( void ) * known - therefore the slightly faster vPortRaiseBASEPRI() function is used * in place of portSET_INTERRUPT_MASK_FROM_ISR(). */ vPortRaiseBASEPRI(); + traceISR_ENTER(); { /* Increment the RTOS tick. */ if( xTaskIncrementTick() != pdFALSE ) { + traceISR_EXIT_TO_SCHEDULER(); + /* A context switch is required. Context switching is performed in * the PendSV interrupt. Pend the PendSV interrupt. */ portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; } + else + { + traceISR_EXIT(); + } } vPortClearBASEPRIFromISR(); diff --git a/Source/portable/RVDS/ARM_CM4F/portmacro.h b/Source/portable/RVDS/ARM_CM4F/portmacro.h index d79c9b425..07659db86 100644 --- a/Source/portable/RVDS/ARM_CM4F/portmacro.h +++ b/Source/portable/RVDS/ARM_CM4F/portmacro.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -47,45 +47,45 @@ */ /* Type definitions. */ - #define portCHAR char - #define portFLOAT float - #define portDOUBLE double - #define portLONG long - #define portSHORT short - #define portSTACK_TYPE uint32_t - #define portBASE_TYPE long - - typedef portSTACK_TYPE StackType_t; - typedef long BaseType_t; - typedef unsigned long UBaseType_t; - - #if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS ) - typedef uint16_t TickType_t; - #define portMAX_DELAY ( TickType_t ) 0xffff - #elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS ) - typedef uint32_t TickType_t; - #define portMAX_DELAY ( TickType_t ) 0xffffffffUL +#define portCHAR char +#define portFLOAT float +#define portDOUBLE double +#define portLONG long +#define portSHORT short +#define portSTACK_TYPE uint32_t +#define portBASE_TYPE long + +typedef portSTACK_TYPE StackType_t; +typedef long BaseType_t; +typedef unsigned long UBaseType_t; + +#if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS ) + typedef uint16_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffff +#elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS ) + typedef uint32_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffffffffUL /* 32-bit tick type on a 32-bit architecture, so reads of the tick count do * not need to be guarded with a critical section. */ - #define portTICK_TYPE_IS_ATOMIC 1 - #else - #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width. - #endif + #define portTICK_TYPE_IS_ATOMIC 1 +#else + #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width. +#endif /*-----------------------------------------------------------*/ /* Architecture specifics. */ - #define portSTACK_GROWTH ( -1 ) - #define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) - #define portBYTE_ALIGNMENT 8 +#define portSTACK_GROWTH ( -1 ) +#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) +#define portBYTE_ALIGNMENT 8 /* Constants used with memory barrier intrinsics. */ - #define portSY_FULL_READ_WRITE ( 15 ) +#define portSY_FULL_READ_WRITE ( 15 ) /*-----------------------------------------------------------*/ /* Scheduler utilities. */ - #define portYIELD() \ +#define portYIELD() \ { \ /* Set a PendSV to request a context switch. */ \ portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; \ @@ -97,167 +97,179 @@ } /*-----------------------------------------------------------*/ - #define portNVIC_INT_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed04 ) ) - #define portNVIC_PENDSVSET_BIT ( 1UL << 28UL ) - #define portEND_SWITCHING_ISR( xSwitchRequired ) do { if( xSwitchRequired != pdFALSE ) portYIELD(); } while( 0 ) - #define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x ) +#define portNVIC_INT_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed04 ) ) +#define portNVIC_PENDSVSET_BIT ( 1UL << 28UL ) +#define portEND_SWITCHING_ISR( xSwitchRequired ) \ + do \ + { \ + if( xSwitchRequired != pdFALSE ) \ + { \ + traceISR_EXIT_TO_SCHEDULER(); \ + portYIELD(); \ + } \ + else \ + { \ + traceISR_EXIT(); \ + } \ + } while( 0 ) +#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x ) /*-----------------------------------------------------------*/ /* Critical section management. */ - extern void vPortEnterCritical( void ); - extern void vPortExitCritical( void ); +extern void vPortEnterCritical( void ); +extern void vPortExitCritical( void ); - #define portDISABLE_INTERRUPTS() vPortRaiseBASEPRI() - #define portENABLE_INTERRUPTS() vPortSetBASEPRI( 0 ) - #define portENTER_CRITICAL() vPortEnterCritical() - #define portEXIT_CRITICAL() vPortExitCritical() - #define portSET_INTERRUPT_MASK_FROM_ISR() ulPortRaiseBASEPRI() - #define portCLEAR_INTERRUPT_MASK_FROM_ISR( x ) vPortSetBASEPRI( x ) +#define portDISABLE_INTERRUPTS() vPortRaiseBASEPRI() +#define portENABLE_INTERRUPTS() vPortSetBASEPRI( 0 ) +#define portENTER_CRITICAL() vPortEnterCritical() +#define portEXIT_CRITICAL() vPortExitCritical() +#define portSET_INTERRUPT_MASK_FROM_ISR() ulPortRaiseBASEPRI() +#define portCLEAR_INTERRUPT_MASK_FROM_ISR( x ) vPortSetBASEPRI( x ) /*-----------------------------------------------------------*/ /* Tickless idle/low power functionality. */ - #ifndef portSUPPRESS_TICKS_AND_SLEEP - extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime ); - #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime ) vPortSuppressTicksAndSleep( xExpectedIdleTime ) - #endif +#ifndef portSUPPRESS_TICKS_AND_SLEEP + extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime ); + #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime ) vPortSuppressTicksAndSleep( xExpectedIdleTime ) +#endif /*-----------------------------------------------------------*/ /* Port specific optimisations. */ - #ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION - #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1 - #endif +#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION + #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1 +#endif - #if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 +#if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 /* Check the configuration. */ - #if ( configMAX_PRIORITIES > 32 ) - #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice. - #endif + #if ( configMAX_PRIORITIES > 32 ) + #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice. + #endif /* Store/clear the ready priorities in a bit map. */ - #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) ) - #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) ) + #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) ) + #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) ) /*-----------------------------------------------------------*/ - #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - ( uint32_t ) __clz( ( uxReadyPriorities ) ) ) + #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - ( uint32_t ) __clz( ( uxReadyPriorities ) ) ) - #endif /* taskRECORD_READY_PRIORITY */ +#endif /* taskRECORD_READY_PRIORITY */ /*-----------------------------------------------------------*/ /* Task function macros as described on the FreeRTOS.org WEB site. These are * not necessary for to use this port. They are defined so the common demo files * (which build with all the ports) will build. */ - #define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters ) - #define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters ) +#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters ) +#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters ) /*-----------------------------------------------------------*/ - #ifdef configASSERT - void vPortValidateInterruptPriority( void ); - #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() vPortValidateInterruptPriority() - #endif +#ifdef configASSERT + void vPortValidateInterruptPriority( void ); + #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() vPortValidateInterruptPriority() +#endif /* portNOP() is not required by this port. */ - #define portNOP() +#define portNOP() - #define portINLINE __inline +#define portINLINE __inline - #ifndef portFORCE_INLINE - #define portFORCE_INLINE __forceinline - #endif +#ifndef portFORCE_INLINE + #define portFORCE_INLINE __forceinline +#endif /*-----------------------------------------------------------*/ - static portFORCE_INLINE void vPortSetBASEPRI( uint32_t ulBASEPRI ) +static portFORCE_INLINE void vPortSetBASEPRI( uint32_t ulBASEPRI ) +{ + __asm { - __asm - { - /* Barrier instructions are not used as this function is only used to - * lower the BASEPRI value. */ + /* Barrier instructions are not used as this function is only used to + * lower the BASEPRI value. */ /* *INDENT-OFF* */ msr basepri, ulBASEPRI /* *INDENT-ON* */ - } } +} /*-----------------------------------------------------------*/ - static portFORCE_INLINE void vPortRaiseBASEPRI( void ) - { - uint32_t ulNewBASEPRI = configMAX_SYSCALL_INTERRUPT_PRIORITY; +static portFORCE_INLINE void vPortRaiseBASEPRI( void ) +{ + uint32_t ulNewBASEPRI = configMAX_SYSCALL_INTERRUPT_PRIORITY; - __asm - { - /* Set BASEPRI to the max syscall priority to effect a critical - * section. */ + __asm + { + /* Set BASEPRI to the max syscall priority to effect a critical + * section. */ /* *INDENT-OFF* */ msr basepri, ulNewBASEPRI dsb isb /* *INDENT-ON* */ - } } +} /*-----------------------------------------------------------*/ - static portFORCE_INLINE void vPortClearBASEPRIFromISR( void ) +static portFORCE_INLINE void vPortClearBASEPRIFromISR( void ) +{ + __asm { - __asm - { - /* Set BASEPRI to 0 so no interrupts are masked. This function is only - * used to lower the mask in an interrupt, so memory barriers are not - * used. */ + /* Set BASEPRI to 0 so no interrupts are masked. This function is only + * used to lower the mask in an interrupt, so memory barriers are not + * used. */ /* *INDENT-OFF* */ msr basepri, # 0 /* *INDENT-ON* */ - } } +} /*-----------------------------------------------------------*/ - static portFORCE_INLINE uint32_t ulPortRaiseBASEPRI( void ) - { - uint32_t ulReturn, ulNewBASEPRI = configMAX_SYSCALL_INTERRUPT_PRIORITY; +static portFORCE_INLINE uint32_t ulPortRaiseBASEPRI( void ) +{ + uint32_t ulReturn, ulNewBASEPRI = configMAX_SYSCALL_INTERRUPT_PRIORITY; - __asm - { - /* Set BASEPRI to the max syscall priority to effect a critical - * section. */ + __asm + { + /* Set BASEPRI to the max syscall priority to effect a critical + * section. */ /* *INDENT-OFF* */ mrs ulReturn, basepri msr basepri, ulNewBASEPRI dsb isb /* *INDENT-ON* */ - } - - return ulReturn; } + + return ulReturn; +} /*-----------------------------------------------------------*/ - static portFORCE_INLINE BaseType_t xPortIsInsideInterrupt( void ) - { - uint32_t ulCurrentInterrupt; - BaseType_t xReturn; +static portFORCE_INLINE BaseType_t xPortIsInsideInterrupt( void ) +{ + uint32_t ulCurrentInterrupt; + BaseType_t xReturn; - /* Obtain the number of the currently executing interrupt. */ - __asm - { + /* Obtain the number of the currently executing interrupt. */ + __asm + { /* *INDENT-OFF* */ mrs ulCurrentInterrupt, ipsr /* *INDENT-ON* */ - } - - if( ulCurrentInterrupt == 0 ) - { - xReturn = pdFALSE; - } - else - { - xReturn = pdTRUE; - } - - return xReturn; } + if( ulCurrentInterrupt == 0 ) + { + xReturn = pdFALSE; + } + else + { + xReturn = pdTRUE; + } + + return xReturn; +} + /* *INDENT-OFF* */ #ifdef __cplusplus } diff --git a/Source/portable/RVDS/ARM_CM4_MPU/mpu_wrappers_v2_asm.c b/Source/portable/RVDS/ARM_CM4_MPU/mpu_wrappers_v2_asm.c index 80f0ee1bb..139159e0b 100644 --- a/Source/portable/RVDS/ARM_CM4_MPU/mpu_wrappers_v2_asm.c +++ b/Source/portable/RVDS/ARM_CM4_MPU/mpu_wrappers_v2_asm.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -310,26 +310,6 @@ MPU_uxTaskGetNumberOfTasks_Unpriv } /*-----------------------------------------------------------*/ -char * MPU_pcTaskGetName( TaskHandle_t xTaskToQuery ) FREERTOS_SYSTEM_CALL; - -__asm char * MPU_pcTaskGetName( TaskHandle_t xTaskToQuery ) /* FREERTOS_SYSTEM_CALL */ -{ - PRESERVE8 - extern MPU_pcTaskGetNameImpl - - push {r0} - mrs r0, control - tst r0, #1 - bne MPU_pcTaskGetName_Unpriv -MPU_pcTaskGetName_Priv - pop {r0} - b MPU_pcTaskGetNameImpl -MPU_pcTaskGetName_Unpriv - pop {r0} - svc #SYSTEM_CALL_pcTaskGetName -} -/*-----------------------------------------------------------*/ - #if ( configGENERATE_RUN_TIME_STATS == 1 ) configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetRunTimeCounter( const TaskHandle_t xTask ) FREERTOS_SYSTEM_CALL; @@ -1262,26 +1242,23 @@ MPU_xTimerGetTimerDaemonTaskHandle_Unpriv #if ( configUSE_TIMERS == 1 ) -BaseType_t MPU_xTimerGenericCommandEntry( const xTimerGenericCommandParams_t * pxParams ) FREERTOS_SYSTEM_CALL; +BaseType_t MPU_xTimerGenericCommandFromTaskEntry( const xTimerGenericCommandFromTaskParams_t * pxParams ) FREERTOS_SYSTEM_CALL; -__asm BaseType_t MPU_xTimerGenericCommandEntry( const xTimerGenericCommandParams_t * pxParams ) /* FREERTOS_SYSTEM_CALL */ +__asm BaseType_t MPU_xTimerGenericCommandFromTaskEntry( const xTimerGenericCommandFromTaskParams_t * pxParams ) /* FREERTOS_SYSTEM_CALL */ { PRESERVE8 - extern MPU_xTimerGenericCommandPrivImpl + extern MPU_xTimerGenericCommandFromTaskImpl push {r0} - mrs r0, ipsr - cmp r0, #0 - bne MPU_xTimerGenericCommand_Priv mrs r0, control tst r0, #1 - beq MPU_xTimerGenericCommand_Priv -MPU_xTimerGenericCommand_Unpriv + bne MPU_xTimerGenericCommandFromTask_Unpriv +MPU_xTimerGenericCommandFromTask_Priv pop {r0} - svc #SYSTEM_CALL_xTimerGenericCommand -MPU_xTimerGenericCommand_Priv + b MPU_xTimerGenericCommandFromTaskImpl +MPU_xTimerGenericCommandFromTask_Unpriv pop {r0} - b MPU_xTimerGenericCommandPrivImpl + svc #SYSTEM_CALL_xTimerGenericCommandFromTask } #endif /* if ( configUSE_TIMERS == 1 ) */ diff --git a/Source/portable/RVDS/ARM_CM4_MPU/port.c b/Source/portable/RVDS/ARM_CM4_MPU/port.c index b5c4cb916..ae7f39f86 100644 --- a/Source/portable/RVDS/ARM_CM4_MPU/port.c +++ b/Source/portable/RVDS/ARM_CM4_MPU/port.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -51,6 +51,9 @@ #define configALLOW_UNPRIVILEGED_CRITICAL_SECTIONS 1 #endif +/* Prototype of all Interrupt Service Routines (ISRs). */ +typedef void ( * portISR_t )( void ); + /* Constants required to access and manipulate the NVIC. */ #define portNVIC_SYSTICK_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000e010 ) ) #define portNVIC_SYSTICK_LOAD_REG ( *( ( volatile uint32_t * ) 0xe000e014 ) ) @@ -87,7 +90,6 @@ #define portMIN_INTERRUPT_PRIORITY ( 255UL ) #define portNVIC_PENDSV_PRI ( ( ( uint32_t ) portMIN_INTERRUPT_PRIORITY ) << 16UL ) #define portNVIC_SYSTICK_PRI ( ( ( uint32_t ) portMIN_INTERRUPT_PRIORITY ) << 24UL ) -#define portNVIC_SVC_PRI ( ( ( uint32_t ) configMAX_SYSCALL_INTERRUPT_PRIORITY - 1UL ) << 24UL ) /* Constants required to manipulate the VFP. */ #define portFPCCR ( ( volatile uint32_t * ) 0xe000ef34UL ) /* Floating point context control register. */ @@ -99,6 +101,11 @@ #define portINITIAL_CONTROL_IF_UNPRIVILEGED ( 0x03 ) #define portINITIAL_CONTROL_IF_PRIVILEGED ( 0x02 ) +/* Constants used to check the installation of the FreeRTOS interrupt handlers. */ +#define portSCB_VTOR_REG ( *( ( portISR_t ** ) 0xE000ED08 ) ) +#define portVECTOR_INDEX_SVC ( 11 ) +#define portVECTOR_INDEX_PENDSV ( 14 ) + /* Constants required to check the validity of an interrupt priority. */ #define portFIRST_USER_INTERRUPT_NUMBER ( 16 ) #define portNVIC_IP_REGISTERS_OFFSET_16 ( 0xE000E3F0 ) @@ -229,6 +236,11 @@ BaseType_t xIsPrivileged( void ); */ void vResetPrivilege( void ); +/** + * @brief Make a task unprivileged. + */ +void vPortSwitchToUserMode( void ); + /** * @brief Enter critical section. */ @@ -283,13 +295,13 @@ void vResetPrivilege( void ); #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) - /** - * @brief Sets up the task stack so that upon returning from - * SVC, the task stack is used again. - * - * @param pulSystemCallStack The current SP when the SVC was raised. - * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler. - */ +/** + * @brief Sets up the task stack so that upon returning from + * SVC, the task stack is used again. + * + * @param pulSystemCallStack The current SP when the SVC was raised. + * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler. + */ void vSystemCallExit( uint32_t * pulSystemCallStack, uint32_t ulLR ) PRIVILEGED_FUNCTION; @@ -319,28 +331,29 @@ StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, } else { - xMPUSettings->ulTaskFlags &= ( ~portTASK_IS_PRIVILEGED_FLAG ); + xMPUSettings->ulTaskFlags &= ( ~( portTASK_IS_PRIVILEGED_FLAG ) ); xMPUSettings->ulContext[ 0 ] = portINITIAL_CONTROL_IF_UNPRIVILEGED; } - xMPUSettings->ulContext[ 1 ] = 0x04040404; /* r4. */ - xMPUSettings->ulContext[ 2 ] = 0x05050505; /* r5. */ - xMPUSettings->ulContext[ 3 ] = 0x06060606; /* r6. */ - xMPUSettings->ulContext[ 4 ] = 0x07070707; /* r7. */ - xMPUSettings->ulContext[ 5 ] = 0x08080808; /* r8. */ - xMPUSettings->ulContext[ 6 ] = 0x09090909; /* r9. */ - xMPUSettings->ulContext[ 7 ] = 0x10101010; /* r10. */ - xMPUSettings->ulContext[ 8 ] = 0x11111111; /* r11. */ - xMPUSettings->ulContext[ 9 ] = portINITIAL_EXC_RETURN; /* EXC_RETURN. */ - - xMPUSettings->ulContext[ 10 ] = ( uint32_t ) ( pxTopOfStack - 8 ); /* PSP with the hardware saved stack. */ - xMPUSettings->ulContext[ 11 ] = ( uint32_t ) pvParameters; /* r0. */ - xMPUSettings->ulContext[ 12 ] = 0x01010101; /* r1. */ - xMPUSettings->ulContext[ 13 ] = 0x02020202; /* r2. */ - xMPUSettings->ulContext[ 14 ] = 0x03030303; /* r3. */ - xMPUSettings->ulContext[ 15 ] = 0x12121212; /* r12. */ - xMPUSettings->ulContext[ 16 ] = 0; /* LR. */ + + xMPUSettings->ulContext[ 1 ] = 0x04040404; /* r4. */ + xMPUSettings->ulContext[ 2 ] = 0x05050505; /* r5. */ + xMPUSettings->ulContext[ 3 ] = 0x06060606; /* r6. */ + xMPUSettings->ulContext[ 4 ] = 0x07070707; /* r7. */ + xMPUSettings->ulContext[ 5 ] = 0x08080808; /* r8. */ + xMPUSettings->ulContext[ 6 ] = 0x09090909; /* r9. */ + xMPUSettings->ulContext[ 7 ] = 0x10101010; /* r10. */ + xMPUSettings->ulContext[ 8 ] = 0x11111111; /* r11. */ + xMPUSettings->ulContext[ 9 ] = portINITIAL_EXC_RETURN; /* EXC_RETURN. */ + + xMPUSettings->ulContext[ 10 ] = ( uint32_t ) ( pxTopOfStack - 8 ); /* PSP with the hardware saved stack. */ + xMPUSettings->ulContext[ 11 ] = ( uint32_t ) pvParameters; /* r0. */ + xMPUSettings->ulContext[ 12 ] = 0x01010101; /* r1. */ + xMPUSettings->ulContext[ 13 ] = 0x02020202; /* r2. */ + xMPUSettings->ulContext[ 14 ] = 0x03030303; /* r3. */ + xMPUSettings->ulContext[ 15 ] = 0x12121212; /* r12. */ + xMPUSettings->ulContext[ 16 ] = 0; /* LR. */ xMPUSettings->ulContext[ 17 ] = ( ( uint32_t ) pxCode ) & portSTART_ADDRESS_MASK; /* PC. */ - xMPUSettings->ulContext[ 18 ] = portINITIAL_XPSR; /* xPSR. */ + xMPUSettings->ulContext[ 18 ] = portINITIAL_XPSR; /* xPSR. */ #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) { @@ -380,7 +393,6 @@ void vSVCHandler_C( uint32_t * pulParam ) switch( ucSVCNumber ) { case portSVC_START_SCHEDULER: - portNVIC_SHPR2_REG |= portNVIC_SVC_PRI; prvRestoreContextOfFirstTask(); break; @@ -519,7 +531,7 @@ void vSVCHandler_C( uint32_t * pulParam ) __asm { mrs r1, control /* Obtain current control value. */ - bic r1, #1 /* Clear nPRIV bit. */ + bic r1, # 1 /* Clear nPRIV bit. */ msr control, r1 /* Write back new control value. */ }; @@ -535,7 +547,6 @@ void vSVCHandler_C( uint32_t * pulParam ) /* Start executing the system call upon returning from this handler. */ pulSystemCallStack[ portOFFSET_TO_PC ] = uxSystemCallImplementations[ ucSystemCallNumber ]; - /* Raise a request to exit from the system call upon finishing the * system call. */ pulSystemCallStack[ portOFFSET_TO_LR ] = ( uint32_t ) vRequestSystemCallExit; @@ -634,7 +645,7 @@ void vSVCHandler_C( uint32_t * pulParam ) __asm { mrs r1, control /* Obtain current control value. */ - orr r1, #1 /* Set nPRIV bit. */ + orr r1, # 1 /* Set nPRIV bit. */ msr control, r1 /* Write back new control value. */ }; @@ -680,13 +691,13 @@ BaseType_t xPortIsTaskPrivileged( void ) /* PRIVILEGED_FUNCTION */ #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) -/* *INDENT-OFF* */ -__asm void vPortSVCHandler( void ) -{ - extern vSVCHandler_C - extern vSystemCallEnter - extern vSystemCallExit + __asm void vPortSVCHandler( void ) + { + extern vSVCHandler_C + extern vSystemCallEnter + extern vSystemCallExit +/* *INDENT-OFF* */ PRESERVE8 tst lr, #4 @@ -709,15 +720,17 @@ syscall_enter syscall_exit mov r1, lr b vSystemCallExit -} +/* *INDENT-ON* */ + } #else /* #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ -__asm void vPortSVCHandler( void ) -{ - extern vSVCHandler_C + __asm void vPortSVCHandler( void ) + { + extern vSVCHandler_C - PRESERVE8 +/* *INDENT-OFF* */ + PRESERVE8 /* Assumes psp was in use. */ #ifndef USE_PROCESS_STACK /* Code should not be required if a main() is using the process stack. */ @@ -730,8 +743,8 @@ __asm void vPortSVCHandler( void ) #endif b vSVCHandler_C -} /* *INDENT-ON* */ + } #endif /* #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ /*-----------------------------------------------------------*/ @@ -758,14 +771,14 @@ __asm void prvRestoreContextOfFirstTask( void ) str r3, [r0] /* Disable MPU. */ ldr r0, =0xe000ed9c /* Region Base Address register. */ - ldmia r2!, {r4-r11} /* Read 4 sets of MPU registers [MPU Region # 4 - 7]. */ - stmia r0, {r4-r11} /* Write 4 sets of MPU registers [MPU Region # 4 - 7]. */ + ldmia r2!, {r4-r11} /* Read 4 sets of MPU registers [MPU Region # 0 - 3]. */ + stmia r0, {r4-r11} /* Write 4 sets of MPU registers [MPU Region # 0 - 3]. */ #if ( configTOTAL_MPU_REGIONS == 16 ) + ldmia r2!, {r4-r11} /* Read 4 sets of MPU registers [MPU Region # 4 - 7]. */ + stmia r0, {r4-r11} /* Write 4 sets of MPU registers. [MPU Region # 4 - 7]. */ ldmia r2!, {r4-r11} /* Read 4 sets of MPU registers [MPU Region # 8 - 11]. */ stmia r0, {r4-r11} /* Write 4 sets of MPU registers. [MPU Region # 8 - 11]. */ - ldmia r2!, {r4-r11} /* Read 4 sets of MPU registers [MPU Region # 12 - 15]. */ - stmia r0, {r4-r11} /* Write 4 sets of MPU registers. [MPU Region # 12 - 15]. */ #endif /* configTOTAL_MPU_REGIONS == 16. */ ldr r0, =0xe000ed94 /* MPU_CTRL register. */ @@ -807,6 +820,7 @@ BaseType_t xPortStartScheduler( void ) #if ( configENABLE_ERRATA_837070_WORKAROUND == 1 ) configASSERT( ( portCPUID == portCORTEX_M7_r0p1_ID ) || ( portCPUID == portCORTEX_M7_r0p0_ID ) ); #else + /* When using this port on a Cortex-M7 r0p0 or r0p1 core, define * configENABLE_ERRATA_837070_WORKAROUND to 1 in your * FreeRTOSConfig.h. */ @@ -814,6 +828,40 @@ BaseType_t xPortStartScheduler( void ) configASSERT( portCPUID != portCORTEX_M7_r0p0_ID ); #endif + /* An application can install FreeRTOS interrupt handlers in one of the + * folllowing ways: + * 1. Direct Routing - Install the functions vPortSVCHandler and + * xPortPendSVHandler for SVCall and PendSV interrupts respectively. + * 2. Indirect Routing - Install separate handlers for SVCall and PendSV + * interrupts and route program control from those handlers to + * vPortSVCHandler and xPortPendSVHandler functions. + * + * Applications that use Indirect Routing must set + * configCHECK_HANDLER_INSTALLATION to 0 in their FreeRTOSConfig.h. Direct + * routing, which is validated here when configCHECK_HANDLER_INSTALLATION + * is 1, should be preferred when possible. */ + #if ( configCHECK_HANDLER_INSTALLATION == 1 ) + { + const portISR_t * const pxVectorTable = portSCB_VTOR_REG; + + /* Validate that the application has correctly installed the FreeRTOS + * handlers for SVCall and PendSV interrupts. We do not check the + * installation of the SysTick handler because the application may + * choose to drive the RTOS tick using a timer other than the SysTick + * timer by overriding the weak function vPortSetupTimerInterrupt(). + * + * Assertion failures here indicate incorrect installation of the + * FreeRTOS handlers. For help installing the FreeRTOS handlers, see + * https://www.FreeRTOS.org/FAQHelp.html. + * + * Systems with a configurable address for the interrupt vector table + * can also encounter assertion failures or even system faults here if + * VTOR is not set correctly to point to the application's vector table. */ + configASSERT( pxVectorTable[ portVECTOR_INDEX_SVC ] == vPortSVCHandler ); + configASSERT( pxVectorTable[ portVECTOR_INDEX_PENDSV ] == xPortPendSVHandler ); + } + #endif /* configCHECK_HANDLER_INSTALLATION */ + #if ( configASSERT_DEFINED == 1 ) { volatile uint8_t ucOriginalPriority; @@ -899,10 +947,11 @@ BaseType_t xPortStartScheduler( void ) #endif /* configASSERT_DEFINED */ /* Make PendSV and SysTick the same priority as the kernel, and the SVC - * handler higher priority so it can be used to exit a critical section (where - * lower priorities are masked). */ + * handler highest priority so it can be used to exit a critical section + * (where lower priorities are masked). */ portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI; portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI; + portNVIC_SHPR2_REG = 0; /* Configure the regions in the MPU that are common to all tasks. */ prvSetupMPU(); @@ -1099,14 +1148,14 @@ __asm void xPortPendSVHandler( void ) str r3, [r0] /* Disable MPU. */ ldr r0, =0xe000ed9c /* Region Base Address register. */ - ldmia r2!, {r4-r11} /* Read 4 sets of MPU registers [MPU Region # 4 - 7]. */ - stmia r0, {r4-r11} /* Write 4 sets of MPU registers [MPU Region # 4 - 7]. */ + ldmia r2!, {r4-r11} /* Read 4 sets of MPU registers [MPU Region # 0 - 3]. */ + stmia r0, {r4-r11} /* Write 4 sets of MPU registers [MPU Region # 0 - 3]. */ #if ( configTOTAL_MPU_REGIONS == 16 ) + ldmia r2!, {r4-r11} /* Read 4 sets of MPU registers [MPU Region # 4 - 7]. */ + stmia r0, {r4-r11} /* Write 4 sets of MPU registers. [MPU Region # 4 - 7]. */ ldmia r2!, {r4-r11} /* Read 4 sets of MPU registers [MPU Region # 8 - 11]. */ stmia r0, {r4-r11} /* Write 4 sets of MPU registers. [MPU Region # 8 - 11]. */ - ldmia r2!, {r4-r11} /* Read 4 sets of MPU registers [MPU Region # 12 - 15]. */ - stmia r0, {r4-r11} /* Write 4 sets of MPU registers. [MPU Region # 12 - 15]. */ #endif /* configTOTAL_MPU_REGIONS == 16. */ ldr r0, =0xe000ed94 /* MPU_CTRL register. */ @@ -1143,13 +1192,19 @@ void xPortSysTickHandler( void ) uint32_t ulDummy; ulDummy = portSET_INTERRUPT_MASK_FROM_ISR(); + traceISR_ENTER(); { /* Increment the RTOS tick. */ if( xTaskIncrementTick() != pdFALSE ) { + traceISR_EXIT_TO_SCHEDULER(); /* Pend a context switch. */ portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; } + else + { + traceISR_EXIT(); + } } portCLEAR_INTERRUPT_MASK_FROM_ISR( ulDummy ); } @@ -1171,19 +1226,6 @@ __weak void vSetupTimerInterrupt( void ) } /*-----------------------------------------------------------*/ -__asm void vPortSwitchToUserMode( void ) -{ -/* *INDENT-OFF* */ - PRESERVE8 - - mrs r0, control - orr r0, #1 - msr control, r0 - bx r14 -/* *INDENT-ON* */ -} -/*-----------------------------------------------------------*/ - __asm void vPortEnableVFP( void ) { /* *INDENT-OFF* */ @@ -1195,6 +1237,7 @@ __asm void vPortEnableVFP( void ) orr r1, r1, #( 0xf << 20 ) /* Enable CP10 and CP11 coprocessors, then save back. */ str r1, [ r0 ] bx r14 + nop /* *INDENT-ON* */ } /*-----------------------------------------------------------*/ @@ -1299,10 +1342,10 @@ __asm BaseType_t xIsPrivileged( void ) PRESERVE8 mrs r0, control /* r0 = CONTROL. */ - tst r0, #1 /* Perform r0 & 1 (bitwise AND) and update the conditions flag. */ + tst r0, #1 /* Perform r0 & 1 (bitwise AND) and update the conditions flag. */ ite ne - movne r0, #0 /* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */ - moveq r0, #1 /* CONTROL[0]==0. Return true to indicate that the processor is privileged. */ + movne r0, #0 /* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */ + moveq r0, #1 /* CONTROL[0]==0. Return true to indicate that the processor is privileged. */ bx lr /* Return. */ /* *INDENT-ON* */ } @@ -1313,14 +1356,27 @@ __asm void vResetPrivilege( void ) /* *INDENT-OFF* */ PRESERVE8 - mrs r0, control /* r0 = CONTROL. */ - orrs r0, #1 /* r0 = r0 | 1. */ - msr control, r0 /* CONTROL = r0. */ - bx lr /* Return. */ + mrs r0, control /* r0 = CONTROL. */ + orrs r0, #1 /* r0 = r0 | 1. */ + msr control, r0 /* CONTROL = r0. */ + bx lr /* Return. */ /* *INDENT-ON* */ } /*-----------------------------------------------------------*/ +void vPortSwitchToUserMode( void ) +{ + /* Load the current task's MPU settings from its TCB. */ + xMPU_SETTINGS * xTaskMpuSettings = xTaskGetMPUSettings( NULL ); + + /* Mark the task as unprivileged. */ + xTaskMpuSettings->ulTaskFlags &= ( ~( portTASK_IS_PRIVILEGED_FLAG ) ); + + /* Lower the processor's privilege level. */ + vResetPrivilege(); +} +/*-----------------------------------------------------------*/ + void vPortStoreTaskMPUSettings( xMPU_SETTINGS * xMPUSettings, const struct xMEMORY_REGION * const xRegions, StackType_t * pxBottomOfStack, diff --git a/Source/portable/RVDS/ARM_CM4_MPU/portmacro.h b/Source/portable/RVDS/ARM_CM4_MPU/portmacro.h index 0f300434d..3f7fb8aaf 100644 --- a/Source/portable/RVDS/ARM_CM4_MPU/portmacro.h +++ b/Source/portable/RVDS/ARM_CM4_MPU/portmacro.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -62,7 +62,7 @@ typedef unsigned long UBaseType_t; #if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS ) typedef uint16_t TickType_t; #define portMAX_DELAY ( TickType_t ) 0xffff -#elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS ) +#elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS ) typedef uint32_t TickType_t; #define portMAX_DELAY ( TickType_t ) 0xffffffffUL @@ -70,9 +70,14 @@ typedef unsigned long UBaseType_t; * not need to be guarded with a critical section. */ #define portTICK_TYPE_IS_ATOMIC 1 #else - #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width. + #error "configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width." #endif +/* Errata 837070 workaround must be enabled on Cortex-M7 r0p0 + * and r0p1 cores. */ +#ifndef configENABLE_ERRATA_837070_WORKAROUND + #define configENABLE_ERRATA_837070_WORKAROUND 0 +#endif /*-----------------------------------------------------------*/ /* MPU specific constants. */ @@ -174,8 +179,8 @@ typedef unsigned long UBaseType_t; #define configTEX_S_C_B_SRAM ( 0x07UL ) #endif -#define portGENERAL_PERIPHERALS_REGION ( configTOTAL_MPU_REGIONS - 5UL ) -#define portSTACK_REGION ( configTOTAL_MPU_REGIONS - 4UL ) +#define portSTACK_REGION ( configTOTAL_MPU_REGIONS - 5UL ) +#define portGENERAL_PERIPHERALS_REGION ( configTOTAL_MPU_REGIONS - 4UL ) #define portUNPRIVILEGED_FLASH_REGION ( configTOTAL_MPU_REGIONS - 3UL ) #define portPRIVILEGED_FLASH_REGION ( configTOTAL_MPU_REGIONS - 2UL ) #define portPRIVILEGED_RAM_REGION ( configTOTAL_MPU_REGIONS - 1UL ) @@ -184,9 +189,6 @@ typedef unsigned long UBaseType_t; #define portNUM_CONFIGURABLE_REGIONS ( configTOTAL_MPU_REGIONS - 5UL ) #define portTOTAL_NUM_REGIONS_IN_TCB ( portNUM_CONFIGURABLE_REGIONS + 1 ) /* Plus 1 to create space for the stack region. */ -void vPortSwitchToUserMode( void ); -#define portSWITCH_TO_USER_MODE() vPortSwitchToUserMode() - typedef struct MPU_REGION_REGISTERS { uint32_t ulRegionBaseAddress; @@ -203,7 +205,7 @@ typedef struct MPU_REGION_SETTINGS #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) #ifndef configSYSTEM_CALL_STACK_SIZE - #error configSYSTEM_CALL_STACK_SIZE must be defined to the desired size of the system call stack in words for using MPU wrappers v2. + #error "configSYSTEM_CALL_STACK_SIZE must be defined to the desired size of the system call stack in words for using MPU wrappers v2." #endif typedef struct SYSTEM_CALL_STACK_INFO @@ -222,8 +224,8 @@ typedef struct MPU_REGION_SETTINGS #define portACL_ENTRY_SIZE_BITS ( 32U ) /* Flags used for xMPU_SETTINGS.ulTaskFlags member. */ -#define portSTACK_FRAME_HAS_PADDING_FLAG ( 1UL << 0UL ) -#define portTASK_IS_PRIVILEGED_FLAG ( 1UL << 1UL ) +#define portSTACK_FRAME_HAS_PADDING_FLAG ( 1UL << 0UL ) +#define portTASK_IS_PRIVILEGED_FLAG ( 1UL << 1UL ) typedef struct MPU_SETTINGS { @@ -258,7 +260,7 @@ typedef struct MPU_SETTINGS /* Scheduler utilities. */ -#define portYIELD() __asm{ SVC portSVC_YIELD } +#define portYIELD() __asm { SVC portSVC_YIELD } #define portYIELD_WITHIN_API() \ { \ /* Set a PendSV to request a context switch. */ \ @@ -273,8 +275,20 @@ typedef struct MPU_SETTINGS #define portNVIC_INT_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed04 ) ) #define portNVIC_PENDSVSET_BIT ( 1UL << 28UL ) -#define portEND_SWITCHING_ISR( xSwitchRequired ) do { if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; } while( 0 ) -#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x ) +#define portEND_SWITCHING_ISR( xSwitchRequired ) \ + do \ + { \ + if( xSwitchRequired ) \ + { \ + traceISR_EXIT_TO_SCHEDULER(); \ + portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; \ + } \ + else \ + { \ + traceISR_EXIT(); \ + } \ + } while( 0 ) +#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x ) /*-----------------------------------------------------------*/ /* Critical section management. */ @@ -299,7 +313,7 @@ extern void vPortExitCritical( void ); /* Check the configuration. */ #if ( configMAX_PRIORITIES > 32 ) - #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice. + #error "configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice." #endif /* Store/clear the ready priorities in a bit map. */ @@ -337,24 +351,33 @@ extern void vPortExitCritical( void ); extern BaseType_t xIsPrivileged( void ); extern void vResetPrivilege( void ); +extern void vPortSwitchToUserMode( void ); /** * @brief Checks whether or not the processor is privileged. * * @return 1 if the processor is already privileged, 0 otherwise. */ -#define portIS_PRIVILEGED() xIsPrivileged() +#define portIS_PRIVILEGED() xIsPrivileged() /** * @brief Raise an SVC request to raise privilege. */ -#define portRAISE_PRIVILEGE() __asm { svc portSVC_RAISE_PRIVILEGE } +#define portRAISE_PRIVILEGE() __asm { svc portSVC_RAISE_PRIVILEGE } /** * @brief Lowers the privilege level by setting the bit 0 of the CONTROL * register. */ -#define portRESET_PRIVILEGE() vResetPrivilege() +#define portRESET_PRIVILEGE() vResetPrivilege() + +/** + * @brief Make a task unprivileged. + * + * It must be called from privileged tasks only. Calling it from unprivileged + * task will result in a memory protection fault. + */ +#define portSWITCH_TO_USER_MODE() vPortSwitchToUserMode() /*-----------------------------------------------------------*/ extern BaseType_t xPortIsTaskPrivileged( void ); @@ -364,7 +387,7 @@ extern BaseType_t xPortIsTaskPrivileged( void ); * * @return pdTRUE if the calling task is privileged, pdFALSE otherwise. */ -#define portIS_TASK_PRIVILEGED() xPortIsTaskPrivileged() +#define portIS_TASK_PRIVILEGED() xPortIsTaskPrivileged() /*-----------------------------------------------------------*/ static portFORCE_INLINE void vPortSetBASEPRI( uint32_t ulBASEPRI ) @@ -468,7 +491,7 @@ static portFORCE_INLINE BaseType_t xPortIsInsideInterrupt( void ) /*-----------------------------------------------------------*/ #ifndef configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY - #warning "configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY is not defined. We recommend defining it to 1 in FreeRTOSConfig.h for better security. https://www.FreeRTOS.org/FreeRTOS-V10.3.x.html" + #warning "configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY is not defined. We recommend defining it to 1 in FreeRTOSConfig.h for better security. www.FreeRTOS.org/FreeRTOS-V10.3.x.html" #define configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY 0 #endif /*-----------------------------------------------------------*/ diff --git a/Source/portable/RVDS/ARM_CM7/r0p1/port.c b/Source/portable/RVDS/ARM_CM7/r0p1/port.c index 2e1bdfc5b..14ffd36c0 100644 --- a/Source/portable/RVDS/ARM_CM7/r0p1/port.c +++ b/Source/portable/RVDS/ARM_CM7/r0p1/port.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -360,22 +360,22 @@ BaseType_t xPortStartScheduler( void ) if( ulImplementedPrioBits == 8 ) { /* When the hardware implements 8 priority bits, there is no way for - * the software to configure PRIGROUP to not have sub-priorities. As - * a result, the least significant bit is always used for sub-priority - * and there are 128 preemption priorities and 2 sub-priorities. - * - * This may cause some confusion in some cases - for example, if - * configMAX_SYSCALL_INTERRUPT_PRIORITY is set to 5, both 5 and 4 - * priority interrupts will be masked in Critical Sections as those - * are at the same preemption priority. This may appear confusing as - * 4 is higher (numerically lower) priority than - * configMAX_SYSCALL_INTERRUPT_PRIORITY and therefore, should not - * have been masked. Instead, if we set configMAX_SYSCALL_INTERRUPT_PRIORITY - * to 4, this confusion does not happen and the behaviour remains the same. - * - * The following assert ensures that the sub-priority bit in the - * configMAX_SYSCALL_INTERRUPT_PRIORITY is clear to avoid the above mentioned - * confusion. */ + * the software to configure PRIGROUP to not have sub-priorities. As + * a result, the least significant bit is always used for sub-priority + * and there are 128 preemption priorities and 2 sub-priorities. + * + * This may cause some confusion in some cases - for example, if + * configMAX_SYSCALL_INTERRUPT_PRIORITY is set to 5, both 5 and 4 + * priority interrupts will be masked in Critical Sections as those + * are at the same preemption priority. This may appear confusing as + * 4 is higher (numerically lower) priority than + * configMAX_SYSCALL_INTERRUPT_PRIORITY and therefore, should not + * have been masked. Instead, if we set configMAX_SYSCALL_INTERRUPT_PRIORITY + * to 4, this confusion does not happen and the behaviour remains the same. + * + * The following assert ensures that the sub-priority bit in the + * configMAX_SYSCALL_INTERRUPT_PRIORITY is clear to avoid the above mentioned + * confusion. */ configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & 0x1U ) == 0U ); ulMaxPRIGROUPValue = 0; } @@ -531,14 +531,21 @@ void xPortSysTickHandler( void ) * known - therefore the slightly faster vPortRaiseBASEPRI() function is used * in place of portSET_INTERRUPT_MASK_FROM_ISR(). */ vPortRaiseBASEPRI(); + traceISR_ENTER(); { /* Increment the RTOS tick. */ if( xTaskIncrementTick() != pdFALSE ) { + traceISR_EXIT_TO_SCHEDULER(); + /* A context switch is required. Context switching is performed in * the PendSV interrupt. Pend the PendSV interrupt. */ portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; } + else + { + traceISR_EXIT(); + } } vPortClearBASEPRIFromISR(); diff --git a/Source/portable/RVDS/ARM_CM7/r0p1/portmacro.h b/Source/portable/RVDS/ARM_CM7/r0p1/portmacro.h index 19301dd9f..2d6460f8e 100644 --- a/Source/portable/RVDS/ARM_CM7/r0p1/portmacro.h +++ b/Source/portable/RVDS/ARM_CM7/r0p1/portmacro.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -47,45 +47,45 @@ */ /* Type definitions. */ - #define portCHAR char - #define portFLOAT float - #define portDOUBLE double - #define portLONG long - #define portSHORT short - #define portSTACK_TYPE uint32_t - #define portBASE_TYPE long - - typedef portSTACK_TYPE StackType_t; - typedef long BaseType_t; - typedef unsigned long UBaseType_t; - - #if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS ) - typedef uint16_t TickType_t; - #define portMAX_DELAY ( TickType_t ) 0xffff - #elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS ) - typedef uint32_t TickType_t; - #define portMAX_DELAY ( TickType_t ) 0xffffffffUL +#define portCHAR char +#define portFLOAT float +#define portDOUBLE double +#define portLONG long +#define portSHORT short +#define portSTACK_TYPE uint32_t +#define portBASE_TYPE long + +typedef portSTACK_TYPE StackType_t; +typedef long BaseType_t; +typedef unsigned long UBaseType_t; + +#if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS ) + typedef uint16_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffff +#elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS ) + typedef uint32_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffffffffUL /* 32-bit tick type on a 32-bit architecture, so reads of the tick count do * not need to be guarded with a critical section. */ - #define portTICK_TYPE_IS_ATOMIC 1 - #else - #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width. - #endif + #define portTICK_TYPE_IS_ATOMIC 1 +#else + #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width. +#endif /*-----------------------------------------------------------*/ /* Architecture specifics. */ - #define portSTACK_GROWTH ( -1 ) - #define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) - #define portBYTE_ALIGNMENT 8 +#define portSTACK_GROWTH ( -1 ) +#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) +#define portBYTE_ALIGNMENT 8 /* Constants used with memory barrier intrinsics. */ - #define portSY_FULL_READ_WRITE ( 15 ) +#define portSY_FULL_READ_WRITE ( 15 ) /*-----------------------------------------------------------*/ /* Scheduler utilities. */ - #define portYIELD() \ +#define portYIELD() \ { \ /* Set a PendSV to request a context switch. */ \ portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; \ @@ -97,99 +97,111 @@ } /*-----------------------------------------------------------*/ - #define portNVIC_INT_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed04 ) ) - #define portNVIC_PENDSVSET_BIT ( 1UL << 28UL ) - #define portEND_SWITCHING_ISR( xSwitchRequired ) do { if( xSwitchRequired != pdFALSE ) portYIELD(); } while( 0 ) - #define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x ) +#define portNVIC_INT_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed04 ) ) +#define portNVIC_PENDSVSET_BIT ( 1UL << 28UL ) +#define portEND_SWITCHING_ISR( xSwitchRequired ) \ + do \ + { \ + if( xSwitchRequired != pdFALSE ) \ + { \ + traceISR_EXIT_TO_SCHEDULER(); \ + portYIELD(); \ + } \ + else \ + { \ + traceISR_EXIT(); \ + } \ + } while( 0 ) +#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x ) /*-----------------------------------------------------------*/ /* Critical section management. */ - extern void vPortEnterCritical( void ); - extern void vPortExitCritical( void ); +extern void vPortEnterCritical( void ); +extern void vPortExitCritical( void ); - #define portDISABLE_INTERRUPTS() vPortRaiseBASEPRI() - #define portENABLE_INTERRUPTS() vPortSetBASEPRI( 0 ) - #define portENTER_CRITICAL() vPortEnterCritical() - #define portEXIT_CRITICAL() vPortExitCritical() - #define portSET_INTERRUPT_MASK_FROM_ISR() ulPortRaiseBASEPRI() - #define portCLEAR_INTERRUPT_MASK_FROM_ISR( x ) vPortSetBASEPRI( x ) +#define portDISABLE_INTERRUPTS() vPortRaiseBASEPRI() +#define portENABLE_INTERRUPTS() vPortSetBASEPRI( 0 ) +#define portENTER_CRITICAL() vPortEnterCritical() +#define portEXIT_CRITICAL() vPortExitCritical() +#define portSET_INTERRUPT_MASK_FROM_ISR() ulPortRaiseBASEPRI() +#define portCLEAR_INTERRUPT_MASK_FROM_ISR( x ) vPortSetBASEPRI( x ) /*-----------------------------------------------------------*/ /* Tickless idle/low power functionality. */ - #ifndef portSUPPRESS_TICKS_AND_SLEEP - extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime ); - #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime ) vPortSuppressTicksAndSleep( xExpectedIdleTime ) - #endif +#ifndef portSUPPRESS_TICKS_AND_SLEEP + extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime ); + #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime ) vPortSuppressTicksAndSleep( xExpectedIdleTime ) +#endif /*-----------------------------------------------------------*/ /* Port specific optimisations. */ - #ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION - #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1 - #endif +#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION + #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1 +#endif - #if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 +#if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 /* Check the configuration. */ - #if ( configMAX_PRIORITIES > 32 ) - #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice. - #endif + #if ( configMAX_PRIORITIES > 32 ) + #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice. + #endif /* Store/clear the ready priorities in a bit map. */ - #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) ) - #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) ) + #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) ) + #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) ) /*-----------------------------------------------------------*/ - #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - ( uint32_t ) __clz( ( uxReadyPriorities ) ) ) + #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - ( uint32_t ) __clz( ( uxReadyPriorities ) ) ) - #endif /* taskRECORD_READY_PRIORITY */ +#endif /* taskRECORD_READY_PRIORITY */ /*-----------------------------------------------------------*/ /* Task function macros as described on the FreeRTOS.org WEB site. These are * not necessary for to use this port. They are defined so the common demo files * (which build with all the ports) will build. */ - #define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters ) - #define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters ) +#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters ) +#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters ) /*-----------------------------------------------------------*/ - #ifdef configASSERT - void vPortValidateInterruptPriority( void ); - #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() vPortValidateInterruptPriority() - #endif +#ifdef configASSERT + void vPortValidateInterruptPriority( void ); + #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() vPortValidateInterruptPriority() +#endif /* portNOP() is not required by this port. */ - #define portNOP() +#define portNOP() - #define portINLINE __inline +#define portINLINE __inline - #ifndef portFORCE_INLINE - #define portFORCE_INLINE __forceinline - #endif +#ifndef portFORCE_INLINE + #define portFORCE_INLINE __forceinline +#endif /*-----------------------------------------------------------*/ - static portFORCE_INLINE void vPortSetBASEPRI( uint32_t ulBASEPRI ) +static portFORCE_INLINE void vPortSetBASEPRI( uint32_t ulBASEPRI ) +{ + __asm { - __asm - { - /* Barrier instructions are not used as this function is only used to - * lower the BASEPRI value. */ + /* Barrier instructions are not used as this function is only used to + * lower the BASEPRI value. */ /* *INDENT-OFF* */ msr basepri, ulBASEPRI /* *INDENT-ON* */ - } } +} /*-----------------------------------------------------------*/ - static portFORCE_INLINE void vPortRaiseBASEPRI( void ) - { - uint32_t ulNewBASEPRI = configMAX_SYSCALL_INTERRUPT_PRIORITY; +static portFORCE_INLINE void vPortRaiseBASEPRI( void ) +{ + uint32_t ulNewBASEPRI = configMAX_SYSCALL_INTERRUPT_PRIORITY; - __asm - { - /* Set BASEPRI to the max syscall priority to effect a critical - * section. */ + __asm + { + /* Set BASEPRI to the max syscall priority to effect a critical + * section. */ /* *INDENT-OFF* */ cpsid i msr basepri, ulNewBASEPRI @@ -197,32 +209,32 @@ isb cpsie i /* *INDENT-ON* */ - } } +} /*-----------------------------------------------------------*/ - static portFORCE_INLINE void vPortClearBASEPRIFromISR( void ) +static portFORCE_INLINE void vPortClearBASEPRIFromISR( void ) +{ + __asm { - __asm - { - /* Set BASEPRI to 0 so no interrupts are masked. This function is only - * used to lower the mask in an interrupt, so memory barriers are not - * used. */ + /* Set BASEPRI to 0 so no interrupts are masked. This function is only + * used to lower the mask in an interrupt, so memory barriers are not + * used. */ /* *INDENT-OFF* */ msr basepri, # 0 /* *INDENT-ON* */ - } } +} /*-----------------------------------------------------------*/ - static portFORCE_INLINE uint32_t ulPortRaiseBASEPRI( void ) - { - uint32_t ulReturn, ulNewBASEPRI = configMAX_SYSCALL_INTERRUPT_PRIORITY; +static portFORCE_INLINE uint32_t ulPortRaiseBASEPRI( void ) +{ + uint32_t ulReturn, ulNewBASEPRI = configMAX_SYSCALL_INTERRUPT_PRIORITY; - __asm - { - /* Set BASEPRI to the max syscall priority to effect a critical - * section. */ + __asm + { + /* Set BASEPRI to the max syscall priority to effect a critical + * section. */ /* *INDENT-OFF* */ mrs ulReturn, basepri cpsid i @@ -231,37 +243,37 @@ isb cpsie i /* *INDENT-ON* */ - } - - return ulReturn; } + + return ulReturn; +} /*-----------------------------------------------------------*/ - static portFORCE_INLINE BaseType_t xPortIsInsideInterrupt( void ) - { - uint32_t ulCurrentInterrupt; - BaseType_t xReturn; +static portFORCE_INLINE BaseType_t xPortIsInsideInterrupt( void ) +{ + uint32_t ulCurrentInterrupt; + BaseType_t xReturn; - /* Obtain the number of the currently executing interrupt. */ - __asm - { + /* Obtain the number of the currently executing interrupt. */ + __asm + { /* *INDENT-OFF* */ mrs ulCurrentInterrupt, ipsr /* *INDENT-ON* */ - } - - if( ulCurrentInterrupt == 0 ) - { - xReturn = pdFALSE; - } - else - { - xReturn = pdTRUE; - } - - return xReturn; } + if( ulCurrentInterrupt == 0 ) + { + xReturn = pdFALSE; + } + else + { + xReturn = pdTRUE; + } + + return xReturn; +} + /* *INDENT-OFF* */ #ifdef __cplusplus } diff --git a/Source/portable/Renesas/RX100/port.c b/Source/portable/Renesas/RX100/port.c index 38718d7de..4b7841930 100644 --- a/Source/portable/Renesas/RX100/port.c +++ b/Source/portable/Renesas/RX100/port.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/Source/portable/Renesas/RX100/port_asm.src b/Source/portable/Renesas/RX100/port_asm.src index e0a9e9376..1105763b8 100644 --- a/Source/portable/Renesas/RX100/port_asm.src +++ b/Source/portable/Renesas/RX100/port_asm.src @@ -1,5 +1,5 @@ ;/* -; * FreeRTOS Kernel V10.6.2 +; * FreeRTOS Kernel V11.0.1 ; * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. ; * ; * SPDX-License-Identifier: MIT diff --git a/Source/portable/Renesas/RX100/portmacro.h b/Source/portable/Renesas/RX100/portmacro.h index d8ab9474b..c48abfc54 100644 --- a/Source/portable/Renesas/RX100/portmacro.h +++ b/Source/portable/Renesas/RX100/portmacro.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -148,6 +148,13 @@ extern void vTaskExitCritical( void ); #define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters ) #define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters ) +#pragma inline_asm vPortMemoryBarrier +static void vPortMemoryBarrier( void ) +{ +} + +#define portMEMORY_BARRIER() vPortMemoryBarrier() + /* *INDENT-OFF* */ #ifdef __cplusplus } diff --git a/Source/portable/Renesas/RX200/port.c b/Source/portable/Renesas/RX200/port.c index 4264889d1..c90f77855 100644 --- a/Source/portable/Renesas/RX200/port.c +++ b/Source/portable/Renesas/RX200/port.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/Source/portable/Renesas/RX200/port_asm.src b/Source/portable/Renesas/RX200/port_asm.src index e0a9e9376..1105763b8 100644 --- a/Source/portable/Renesas/RX200/port_asm.src +++ b/Source/portable/Renesas/RX200/port_asm.src @@ -1,5 +1,5 @@ ;/* -; * FreeRTOS Kernel V10.6.2 +; * FreeRTOS Kernel V11.0.1 ; * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. ; * ; * SPDX-License-Identifier: MIT diff --git a/Source/portable/Renesas/RX200/portmacro.h b/Source/portable/Renesas/RX200/portmacro.h index 84dab7145..160947921 100644 --- a/Source/portable/Renesas/RX200/portmacro.h +++ b/Source/portable/Renesas/RX200/portmacro.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -138,6 +138,12 @@ extern void vTaskExitCritical( void ); #define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters ) #define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters ) +#pragma inline_asm vPortMemoryBarrier +static void vPortMemoryBarrier( void ) +{ +} + +#define portMEMORY_BARRIER() vPortMemoryBarrier() /* *INDENT-OFF* */ #ifdef __cplusplus } diff --git a/Source/portable/Renesas/RX600/port.c b/Source/portable/Renesas/RX600/port.c index 415ea318a..375b578ca 100644 --- a/Source/portable/Renesas/RX600/port.c +++ b/Source/portable/Renesas/RX600/port.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/Source/portable/Renesas/RX600/port_asm.src b/Source/portable/Renesas/RX600/port_asm.src index e0a9e9376..1105763b8 100644 --- a/Source/portable/Renesas/RX600/port_asm.src +++ b/Source/portable/Renesas/RX600/port_asm.src @@ -1,5 +1,5 @@ ;/* -; * FreeRTOS Kernel V10.6.2 +; * FreeRTOS Kernel V11.0.1 ; * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. ; * ; * SPDX-License-Identifier: MIT diff --git a/Source/portable/Renesas/RX600/portmacro.h b/Source/portable/Renesas/RX600/portmacro.h index afad13592..841caef5f 100644 --- a/Source/portable/Renesas/RX600/portmacro.h +++ b/Source/portable/Renesas/RX600/portmacro.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -139,6 +139,13 @@ extern void vTaskExitCritical( void ); #define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters ) #define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters ) +#pragma inline_asm vPortMemoryBarrier +static void vPortMemoryBarrier( void ) +{ +} + +#define portMEMORY_BARRIER() vPortMemoryBarrier() + /* *INDENT-OFF* */ #ifdef __cplusplus } diff --git a/Source/portable/Renesas/RX600v2/port.c b/Source/portable/Renesas/RX600v2/port.c index df1b8f2c2..a2932e3bc 100644 --- a/Source/portable/Renesas/RX600v2/port.c +++ b/Source/portable/Renesas/RX600v2/port.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/Source/portable/Renesas/RX600v2/port_asm.src b/Source/portable/Renesas/RX600v2/port_asm.src index 18066a63e..6c30b6190 100644 --- a/Source/portable/Renesas/RX600v2/port_asm.src +++ b/Source/portable/Renesas/RX600v2/port_asm.src @@ -1,5 +1,5 @@ ;/* -; * FreeRTOS Kernel V10.6.2 +; * FreeRTOS Kernel V11.0.1 ; * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. ; * ; * SPDX-License-Identifier: MIT diff --git a/Source/portable/Renesas/RX600v2/portmacro.h b/Source/portable/Renesas/RX600v2/portmacro.h index 71da3da4d..181f3df2c 100644 --- a/Source/portable/Renesas/RX600v2/portmacro.h +++ b/Source/portable/Renesas/RX600v2/portmacro.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -139,6 +139,13 @@ extern void vTaskExitCritical( void ); #define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters ) #define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters ) +#pragma inline_asm vPortMemoryBarrier +static void vPortMemoryBarrier( void ) +{ +} + +#define portMEMORY_BARRIER() vPortMemoryBarrier() + /* *INDENT-OFF* */ #ifdef __cplusplus } diff --git a/Source/portable/Renesas/RX700v3_DPFPU/port.c b/Source/portable/Renesas/RX700v3_DPFPU/port.c index 7ec44c05e..3fe9634c9 100644 --- a/Source/portable/Renesas/RX700v3_DPFPU/port.c +++ b/Source/portable/Renesas/RX700v3_DPFPU/port.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/Source/portable/Renesas/RX700v3_DPFPU/port_asm.src b/Source/portable/Renesas/RX700v3_DPFPU/port_asm.src index 18066a63e..6c30b6190 100644 --- a/Source/portable/Renesas/RX700v3_DPFPU/port_asm.src +++ b/Source/portable/Renesas/RX700v3_DPFPU/port_asm.src @@ -1,5 +1,5 @@ ;/* -; * FreeRTOS Kernel V10.6.2 +; * FreeRTOS Kernel V11.0.1 ; * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. ; * ; * SPDX-License-Identifier: MIT diff --git a/Source/portable/Renesas/RX700v3_DPFPU/portmacro.h b/Source/portable/Renesas/RX700v3_DPFPU/portmacro.h index 4aae682cd..f3d0b353e 100644 --- a/Source/portable/Renesas/RX700v3_DPFPU/portmacro.h +++ b/Source/portable/Renesas/RX700v3_DPFPU/portmacro.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -183,6 +183,13 @@ /* Definition to allow compatibility with existing FreeRTOS Demo using flop.c. */ #define portTASK_USES_FLOATING_POINT() vPortTaskUsesDPFPU() +#pragma inline_asm vPortMemoryBarrier +static void vPortMemoryBarrier( void ) +{ +} + +#define portMEMORY_BARRIER() vPortMemoryBarrier() + /* *INDENT-OFF* */ #ifdef __cplusplus } diff --git a/Source/portable/Renesas/SH2A_FPU/ISR_Support.inc b/Source/portable/Renesas/SH2A_FPU/ISR_Support.inc index 811ffee87..4e9b7133b 100644 --- a/Source/portable/Renesas/SH2A_FPU/ISR_Support.inc +++ b/Source/portable/Renesas/SH2A_FPU/ISR_Support.inc @@ -1,5 +1,5 @@ ;/* -; * FreeRTOS Kernel V10.6.2 +; * FreeRTOS Kernel V11.0.1 ; * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. ; * ; * SPDX-License-Identifier: MIT diff --git a/Source/portable/Renesas/SH2A_FPU/port.c b/Source/portable/Renesas/SH2A_FPU/port.c index 105f243e6..293ea5515 100644 --- a/Source/portable/Renesas/SH2A_FPU/port.c +++ b/Source/portable/Renesas/SH2A_FPU/port.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -27,8 +27,8 @@ */ /*----------------------------------------------------------- - * Implementation of functions defined in portable.h for the SH2A port. - *----------------------------------------------------------*/ +* Implementation of functions defined in portable.h for the SH2A port. +*----------------------------------------------------------*/ /* Scheduler includes. */ #include "FreeRTOS.h" @@ -40,17 +40,17 @@ /*-----------------------------------------------------------*/ /* The SR assigned to a newly created task. The only important thing in this -value is for all interrupts to be enabled. */ -#define portINITIAL_SR ( 0UL ) + * value is for all interrupts to be enabled. */ +#define portINITIAL_SR ( 0UL ) /* Dimensions the array into which the floating point context is saved. -Allocate enough space for FPR0 to FPR15, FPUL and FPSCR, each of which is 4 -bytes big. If this number is changed then the 72 in portasm.src also needs -changing. */ -#define portFLOP_REGISTERS_TO_STORE ( 18 ) -#define portFLOP_STORAGE_SIZE ( portFLOP_REGISTERS_TO_STORE * 4 ) + * Allocate enough space for FPR0 to FPR15, FPUL and FPSCR, each of which is 4 + * bytes big. If this number is changed then the 72 in portasm.src also needs + * changing. */ +#define portFLOP_REGISTERS_TO_STORE ( 18 ) +#define portFLOP_STORAGE_SIZE ( portFLOP_REGISTERS_TO_STORE * 4 ) -#if( configSUPPORT_DYNAMIC_ALLOCATION == 0 ) +#if ( configSUPPORT_DYNAMIC_ALLOCATION == 0 ) #error configSUPPORT_DYNAMIC_ALLOCATION must be 1 to use this port. #endif @@ -76,7 +76,9 @@ extern uint32_t ulPortGetGBR( void ); /* * See header file for description. */ -StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters ) +StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, + TaskFunction_t pxCode, + void * pvParameters ) { /* Mark the end of the stack - used for debugging only and can be removed. */ *pxTopOfStack = 0x11111111UL; @@ -170,9 +172,9 @@ StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t px *pxTopOfStack = ulPortGetGBR(); /* GBR = global base register. - VBR = vector base register. - TBR = jump table base register. - R15 is the stack pointer. */ + * VBR = vector base register. + * TBR = jump table base register. + * R15 is the stack pointer. */ return pxTopOfStack; } @@ -180,18 +182,18 @@ StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t px BaseType_t xPortStartScheduler( void ) { -extern void vApplicationSetupTimerInterrupt( void ); + extern void vApplicationSetupTimerInterrupt( void ); /* Call an application function to set up the timer that will generate the - tick interrupt. This way the application can decide which peripheral to - use. A demo application is provided to show a suitable example. */ + * tick interrupt. This way the application can decide which peripheral to + * use. A demo application is provided to show a suitable example. */ vApplicationSetupTimerInterrupt(); /* Start the first task. This will only restore the standard registers and - not the flop registers. This does not really matter though because the only - flop register that is initialised to a particular value is fpscr, and it is - only initialised to the current value, which will still be the current value - when the first task starts executing. */ + * not the flop registers. This does not really matter though because the only + * flop register that is initialised to a particular value is fpscr, and it is + * only initialised to the current value, which will still be the current value + * when the first task starts executing. */ trapa( portSTART_SCHEDULER_TRAP_NO ); /* Should not get here. */ @@ -207,37 +209,37 @@ void vPortEndScheduler( void ) void vPortYield( void ) { -int32_t lInterruptMask; + int32_t lInterruptMask; /* Ensure the yield trap runs at the same priority as the other interrupts - that can cause a context switch. */ + * that can cause a context switch. */ lInterruptMask = get_imask(); /* taskYIELD() can only be called from a task, not an interrupt, so the - current interrupt mask can only be 0 or portKERNEL_INTERRUPT_PRIORITY and - the mask can be set without risk of accidentally lowering the mask value. */ + * current interrupt mask can only be 0 or portKERNEL_INTERRUPT_PRIORITY and + * the mask can be set without risk of accidentally lowering the mask value. */ set_imask( portKERNEL_INTERRUPT_PRIORITY ); trapa( portYIELD_TRAP_NO ); /* Restore the interrupt mask to whatever it was previously (when the - function was entered). */ + * function was entered). */ set_imask( ( int ) lInterruptMask ); } /*-----------------------------------------------------------*/ BaseType_t xPortUsesFloatingPoint( TaskHandle_t xTask ) { -uint32_t *pulFlopBuffer; -BaseType_t xReturn; -extern void * volatile pxCurrentTCB; + uint32_t * pulFlopBuffer; + BaseType_t xReturn; + extern void * volatile pxCurrentTCB; /* This function tells the kernel that the task referenced by xTask is - going to use the floating point registers and therefore requires the - floating point registers saved as part of its context. */ + * going to use the floating point registers and therefore requires the + * floating point registers saved as part of its context. */ /* Passing NULL as xTask is used to indicate that the calling task is the - subject task - so pxCurrentTCB is the task handle. */ + * subject task - so pxCurrentTCB is the task handle. */ if( xTask == NULL ) { xTask = ( TaskHandle_t ) pxCurrentTCB; @@ -252,11 +254,11 @@ extern void * volatile pxCurrentTCB; memset( ( void * ) pulFlopBuffer, 0x00, portFLOP_STORAGE_SIZE ); /* The first thing to get saved in the buffer is the FPSCR value - - initialise this to the current FPSCR value. */ + * initialise this to the current FPSCR value. */ *pulFlopBuffer = get_fpscr(); /* Use the task tag to point to the flop buffer. Pass pointer to just - above the buffer because the flop save routine uses a pre-decrement. */ + * above the buffer because the flop save routine uses a pre-decrement. */ vTaskSetApplicationTaskTag( xTask, ( void * ) ( pulFlopBuffer + portFLOP_REGISTERS_TO_STORE ) ); xReturn = pdPASS; } diff --git a/Source/portable/Renesas/SH2A_FPU/portasm.src b/Source/portable/Renesas/SH2A_FPU/portasm.src index c0af9ba7d..eee46e669 100644 --- a/Source/portable/Renesas/SH2A_FPU/portasm.src +++ b/Source/portable/Renesas/SH2A_FPU/portasm.src @@ -1,5 +1,5 @@ ;/* -; * FreeRTOS Kernel V10.6.2 +; * FreeRTOS Kernel V11.0.1 ; * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. ; * ; * SPDX-License-Identifier: MIT diff --git a/Source/portable/Renesas/SH2A_FPU/portmacro.h b/Source/portable/Renesas/SH2A_FPU/portmacro.h index 8cce0588a..9901d1fe8 100644 --- a/Source/portable/Renesas/SH2A_FPU/portmacro.h +++ b/Source/portable/Renesas/SH2A_FPU/portmacro.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -49,68 +49,68 @@ */ /* Type definitions - these are a bit legacy and not really used now, other than -portSTACK_TYPE and portBASE_TYPE. */ -#define portCHAR char -#define portFLOAT float -#define portDOUBLE double -#define portLONG long -#define portSHORT short -#define portSTACK_TYPE uint32_t -#define portBASE_TYPE long - -typedef portSTACK_TYPE StackType_t; -typedef long BaseType_t; -typedef unsigned long UBaseType_t; - -#if( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS ) - typedef uint16_t TickType_t; - #define portMAX_DELAY ( TickType_t ) 0xffff + * portSTACK_TYPE and portBASE_TYPE. */ +#define portCHAR char +#define portFLOAT float +#define portDOUBLE double +#define portLONG long +#define portSHORT short +#define portSTACK_TYPE uint32_t +#define portBASE_TYPE long + +typedef portSTACK_TYPE StackType_t; +typedef long BaseType_t; +typedef unsigned long UBaseType_t; + +#if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS ) + typedef uint16_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffff #elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS ) - typedef uint32_t TickType_t; - #define portMAX_DELAY ( TickType_t ) 0xffffffffUL + typedef uint32_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffffffffUL - /* 32-bit tick type on a 32-bit architecture, so reads of the tick count do - not need to be guarded with a critical section. */ - #define portTICK_TYPE_IS_ATOMIC 1 +/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do + * not need to be guarded with a critical section. */ + #define portTICK_TYPE_IS_ATOMIC 1 #endif /*-----------------------------------------------------------*/ /* Hardware specifics. */ -#define portBYTE_ALIGNMENT 8 -#define portSTACK_GROWTH -1 -#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) -#define portNOP() nop() -#define portSTART_SCHEDULER_TRAP_NO ( 32 ) -#define portYIELD_TRAP_NO ( 33 ) -#define portKERNEL_INTERRUPT_PRIORITY ( 1 ) +#define portBYTE_ALIGNMENT 8 +#define portSTACK_GROWTH -1 +#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) +#define portNOP() nop() +#define portSTART_SCHEDULER_TRAP_NO ( 32 ) +#define portYIELD_TRAP_NO ( 33 ) +#define portKERNEL_INTERRUPT_PRIORITY ( 1 ) void vPortYield( void ); -#define portYIELD() vPortYield() +#define portYIELD() vPortYield() extern void vTaskSwitchContext( void ); -#define portYIELD_FROM_ISR( x ) do { if( x != pdFALSE ) vTaskSwitchContext(); } while( 0 ) +#define portYIELD_FROM_ISR( x ) do { if( x != pdFALSE ) vTaskSwitchContext( ); } while( 0 ) /* * This function tells the kernel that the task referenced by xTask is going to * use the floating point registers and therefore requires the floating point * registers saved as part of its context. */ -BaseType_t xPortUsesFloatingPoint( void* xTask ); +BaseType_t xPortUsesFloatingPoint( void * xTask ); /* * The flop save and restore functions are defined in portasm.src and called by * the trace "task switched in" and "trace task switched out" macros. */ -void vPortSaveFlopRegisters( void *pulBuffer ); -void vPortRestoreFlopRegisters( void *pulBuffer ); +void vPortSaveFlopRegisters( void * pulBuffer ); +void vPortRestoreFlopRegisters( void * pulBuffer ); /* * pxTaskTag is used to point to the buffer into which the floating point * context should be saved. If pxTaskTag is NULL then the task does not use * a floating point context. */ -#define traceTASK_SWITCHED_OUT() do { if( pxCurrentTCB->pxTaskTag != NULL ) vPortSaveFlopRegisters( pxCurrentTCB->pxTaskTag ); } while( 0 ) -#define traceTASK_SWITCHED_IN() do { if( pxCurrentTCB->pxTaskTag != NULL ) vPortRestoreFlopRegisters( pxCurrentTCB->pxTaskTag ); } while( 0 ) +#define traceTASK_SWITCHED_OUT() do { if( pxCurrentTCB->pxTaskTag != NULL ) vPortSaveFlopRegisters( pxCurrentTCB->pxTaskTag ); } while( 0 ) +#define traceTASK_SWITCHED_IN() do { if( pxCurrentTCB->pxTaskTag != NULL ) vPortRestoreFlopRegisters( pxCurrentTCB->pxTaskTag ); } while( 0 ) /* * These macros should be called directly, but through the taskENTER_CRITICAL() @@ -120,7 +120,7 @@ void vPortRestoreFlopRegisters( void *pulBuffer ); #define portDISABLE_INTERRUPTS() set_imask( portKERNEL_INTERRUPT_PRIORITY ) /* Critical nesting counts are stored in the TCB. */ -#define portCRITICAL_NESTING_IN_TCB ( 1 ) +#define portCRITICAL_NESTING_IN_TCB ( 1 ) /* The critical nesting functions defined within tasks.c. */ extern void vTaskEnterCritical( void ); @@ -131,8 +131,8 @@ extern void vTaskExitCritical( void ); /*-----------------------------------------------------------*/ /* Task function macros as described on the FreeRTOS.org WEB site. */ -#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters ) -#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters ) +#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters ) +#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters ) /* *INDENT-OFF* */ #ifdef __cplusplus diff --git a/Source/portable/Rowley/MSP430F449/port.c b/Source/portable/Rowley/MSP430F449/port.c index 77cf0ca30..1a0cf932c 100644 --- a/Source/portable/Rowley/MSP430F449/port.c +++ b/Source/portable/Rowley/MSP430F449/port.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/Source/portable/Rowley/MSP430F449/portasm.h b/Source/portable/Rowley/MSP430F449/portasm.h index 12ff46bbe..fa38248cd 100644 --- a/Source/portable/Rowley/MSP430F449/portasm.h +++ b/Source/portable/Rowley/MSP430F449/portasm.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/Source/portable/Rowley/MSP430F449/portext.asm b/Source/portable/Rowley/MSP430F449/portext.asm index eef7afe62..42919dd1b 100644 --- a/Source/portable/Rowley/MSP430F449/portext.asm +++ b/Source/portable/Rowley/MSP430F449/portext.asm @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/Source/portable/Rowley/MSP430F449/portmacro.h b/Source/portable/Rowley/MSP430F449/portmacro.h index 8c8d290e4..4c6d823e2 100644 --- a/Source/portable/Rowley/MSP430F449/portmacro.h +++ b/Source/portable/Rowley/MSP430F449/portmacro.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/Source/portable/SDCC/Cygnal/port.c b/Source/portable/SDCC/Cygnal/port.c index b2d4b466d..b8c061c9e 100644 --- a/Source/portable/SDCC/Cygnal/port.c +++ b/Source/portable/SDCC/Cygnal/port.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/Source/portable/SDCC/Cygnal/portmacro.h b/Source/portable/SDCC/Cygnal/portmacro.h index 03fa6c3c1..3d14305a1 100644 --- a/Source/portable/SDCC/Cygnal/portmacro.h +++ b/Source/portable/SDCC/Cygnal/portmacro.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/Source/portable/Softune/MB91460/__STD_LIB_sbrk.c b/Source/portable/Softune/MB91460/__STD_LIB_sbrk.c index a1678d819..1be0b8208 100644 --- a/Source/portable/Softune/MB91460/__STD_LIB_sbrk.c +++ b/Source/portable/Softune/MB91460/__STD_LIB_sbrk.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -32,7 +32,7 @@ /* (C) Fujitsu Microelectronics Europe GmbH */ /*--------------------------------------------------------------------------- __STD_LIB_sbrk.C - - Used by heap_3.c for memory accocation and deletion. + - Used by heap_3.c for memory allocation and deletion. /*---------------------------------------------------------------------------*/ diff --git a/Source/portable/Softune/MB91460/port.c b/Source/portable/Softune/MB91460/port.c index 77c23a6f4..32a34e9c9 100644 --- a/Source/portable/Softune/MB91460/port.c +++ b/Source/portable/Softune/MB91460/port.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/Source/portable/Softune/MB91460/portmacro.h b/Source/portable/Softune/MB91460/portmacro.h index 274195278..4380256dd 100644 --- a/Source/portable/Softune/MB91460/portmacro.h +++ b/Source/portable/Softune/MB91460/portmacro.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/Source/portable/Softune/MB96340/__STD_LIB_sbrk.c b/Source/portable/Softune/MB96340/__STD_LIB_sbrk.c index a1678d819..1be0b8208 100644 --- a/Source/portable/Softune/MB96340/__STD_LIB_sbrk.c +++ b/Source/portable/Softune/MB96340/__STD_LIB_sbrk.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -32,7 +32,7 @@ /* (C) Fujitsu Microelectronics Europe GmbH */ /*--------------------------------------------------------------------------- __STD_LIB_sbrk.C - - Used by heap_3.c for memory accocation and deletion. + - Used by heap_3.c for memory allocation and deletion. /*---------------------------------------------------------------------------*/ diff --git a/Source/portable/Softune/MB96340/port.c b/Source/portable/Softune/MB96340/port.c index a748a3ea5..4aedbeaab 100644 --- a/Source/portable/Softune/MB96340/port.c +++ b/Source/portable/Softune/MB96340/port.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -105,13 +105,13 @@ extern volatile TCB_t * volatile pxCurrentTCB; } /* - * Macro to restore a task context from the task stack. This is effecti- - * vely the reverse of SAVE_CONTEXT(). First the stack pointer value - * (USP for SMALL and MEDIUM memory model amd USB:USP for COMPACT and - * LARGE memory model ) is loaded from the task control block. Next the - * value of all the general purpose registers RW0-RW7 is retrieved. Fina- - * lly it copies of the context ( AH:AL, DPR:ADB, DTB:PCB, PC and PS) of - * the task to be executed upon RETI from user stack to system stack. + * Macro to restore a task context from the task stack. This is + * effectively the reverse of SAVE_CONTEXT(). First the stack pointer + * value (USP for SMALL and MEDIUM memory model amd USB:USP for COMPACT + * and LARGE memory model ) is loaded from the task control block. Next + * the value of all the general purpose registers RW0-RW7 is retrieved. + * Finally it copies of the context ( AH:AL, DPR:ADB, DTB:PCB, PC and PS) + * of the task to be executed upon RETI from user stack to system stack. */ #define portRESTORE_CONTEXT() \ diff --git a/Source/portable/Softune/MB96340/portmacro.h b/Source/portable/Softune/MB96340/portmacro.h index 2ccbb90bb..e035e7d7e 100644 --- a/Source/portable/Softune/MB96340/portmacro.h +++ b/Source/portable/Softune/MB96340/portmacro.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/Source/portable/Tasking/ARM_CM4F/port.c b/Source/portable/Tasking/ARM_CM4F/port.c index b5967d352..b308280bf 100644 --- a/Source/portable/Tasking/ARM_CM4F/port.c +++ b/Source/portable/Tasking/ARM_CM4F/port.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -246,12 +246,18 @@ void SysTick_Handler( void ) uint32_t ulDummy; ulDummy = portSET_INTERRUPT_MASK_FROM_ISR(); + traceISR_ENTER(); { if( xTaskIncrementTick() != pdFALSE ) { + traceISR_EXIT_TO_SCHEDULER(); /* Pend a context switch. */ *( portNVIC_INT_CTRL ) = portNVIC_PENDSVSET; } + else + { + traceISR_EXIT(); + } } portCLEAR_INTERRUPT_MASK_FROM_ISR( ulDummy ); } diff --git a/Source/portable/Tasking/ARM_CM4F/port_asm.asm b/Source/portable/Tasking/ARM_CM4F/port_asm.asm index f47139e5d..fc9483daf 100644 --- a/Source/portable/Tasking/ARM_CM4F/port_asm.asm +++ b/Source/portable/Tasking/ARM_CM4F/port_asm.asm @@ -1,5 +1,5 @@ ;/* -; * FreeRTOS Kernel V10.6.2 +; * FreeRTOS Kernel V11.0.1 ; * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. ; * ; * SPDX-License-Identifier: MIT diff --git a/Source/portable/Tasking/ARM_CM4F/portmacro.h b/Source/portable/Tasking/ARM_CM4F/portmacro.h index 152709198..c406ef08f 100644 --- a/Source/portable/Tasking/ARM_CM4F/portmacro.h +++ b/Source/portable/Tasking/ARM_CM4F/portmacro.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -83,13 +83,25 @@ /* Scheduler utilities. */ - extern void vPortYield( void ); - #define portNVIC_INT_CTRL ( ( volatile uint32_t * ) 0xe000ed04 ) - #define portNVIC_PENDSVSET 0x10000000 - #define portYIELD() vPortYield() - - #define portEND_SWITCHING_ISR( xSwitchRequired ) if( xSwitchRequired ) *( portNVIC_INT_CTRL ) = portNVIC_PENDSVSET - #define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x ) +extern void vPortYield( void ); +#define portNVIC_INT_CTRL ( ( volatile uint32_t * ) 0xe000ed04 ) +#define portNVIC_PENDSVSET 0x10000000 +#define portYIELD() vPortYield() + +#define portEND_SWITCHING_ISR( xSwitchRequired ) \ + do \ + { \ + if( xSwitchRequired != pdFALSE ) \ + { \ + traceISR_EXIT_TO_SCHEDULER(); \ + *( portNVIC_INT_CTRL ) = portNVIC_PENDSVSET; \ + } \ + else \ + { \ + traceISR_EXIT(); \ + } \ + } while( 0 ) +#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x ) /*-----------------------------------------------------------*/ diff --git a/Source/portable/ThirdParty/CDK/T-HEAD_CK802/port.c b/Source/portable/ThirdParty/CDK/T-HEAD_CK802/port.c index 964ddd96c..6e953a0cb 100644 --- a/Source/portable/ThirdParty/CDK/T-HEAD_CK802/port.c +++ b/Source/portable/ThirdParty/CDK/T-HEAD_CK802/port.c @@ -26,39 +26,41 @@ #include "FreeRTOS.h" #include "task.h" -extern void vPortStartTask(void); +extern void vPortStartTask( void ); /* Used to keep track of the number of nested calls to taskENTER_CRITICAL(). This -will be set to 0 prior to the first task being started. */ + * will be set to 0 prior to the first task being started. */ portLONG ulCriticalNesting = 0x9999UL; /* Used to record one tack want to swtich task after enter critical area, we need know it * and implement task switch after exit critical area */ portLONG pendsvflag = 0; -StackType_t *pxPortInitialiseStack( StackType_t * pxTopOfStack, TaskFunction_t pxCode, void *pvParameters ) +StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, + TaskFunction_t pxCode, + void * pvParameters ) { - StackType_t *stk = NULL; + StackType_t * stk = NULL; stk = pxTopOfStack; - *(--stk) = (uint32_t)pxCode; /* Entry Point */ - *(--stk) = (uint32_t)0xE0000140L; /* PSR */ - *(--stk) = (uint32_t)0xFFFFFFFEL; /* R15 (LR) (init value will cause fault if ever used) */ - *(--stk) = (uint32_t)0x13131313L; /* R13 */ - *(--stk) = (uint32_t)0x12121212L; /* R12 */ - *(--stk) = (uint32_t)0x11111111L; /* R11 */ - *(--stk) = (uint32_t)0x10101010L; /* R10 */ - *(--stk) = (uint32_t)0x09090909L; /* R9 */ - *(--stk) = (uint32_t)0x08080808L; /* R8 */ - *(--stk) = (uint32_t)0x07070707L; /* R7 */ - *(--stk) = (uint32_t)0x06060606L; /* R6 */ - *(--stk) = (uint32_t)0x05050505L; /* R5 */ - *(--stk) = (uint32_t)0x04040404L; /* R4 */ - *(--stk) = (uint32_t)0x03030303L; /* R3 */ - *(--stk) = (uint32_t)0x02020202L; /* R2 */ - *(--stk) = (uint32_t)0x01010101L; /* R1 */ - *(--stk) = (uint32_t)pvParameters; /* R0 : argument */ + *( --stk ) = ( uint32_t ) pxCode; /* Entry Point */ + *( --stk ) = ( uint32_t ) 0xE0000140L; /* PSR */ + *( --stk ) = ( uint32_t ) 0xFFFFFFFEL; /* R15 (LR) (init value will cause fault if ever used) */ + *( --stk ) = ( uint32_t ) 0x13131313L; /* R13 */ + *( --stk ) = ( uint32_t ) 0x12121212L; /* R12 */ + *( --stk ) = ( uint32_t ) 0x11111111L; /* R11 */ + *( --stk ) = ( uint32_t ) 0x10101010L; /* R10 */ + *( --stk ) = ( uint32_t ) 0x09090909L; /* R9 */ + *( --stk ) = ( uint32_t ) 0x08080808L; /* R8 */ + *( --stk ) = ( uint32_t ) 0x07070707L; /* R7 */ + *( --stk ) = ( uint32_t ) 0x06060606L; /* R6 */ + *( --stk ) = ( uint32_t ) 0x05050505L; /* R5 */ + *( --stk ) = ( uint32_t ) 0x04040404L; /* R4 */ + *( --stk ) = ( uint32_t ) 0x03030303L; /* R3 */ + *( --stk ) = ( uint32_t ) 0x02020202L; /* R2 */ + *( --stk ) = ( uint32_t ) 0x01010101L; /* R1 */ + *( --stk ) = ( uint32_t ) pvParameters; /* R0 : argument */ return stk; } @@ -81,21 +83,25 @@ void vPortEndScheduler( void ) void vPortEnterCritical( void ) { portDISABLE_INTERRUPTS(); - ulCriticalNesting ++; + ulCriticalNesting++; } void vPortExitCritical( void ) { - if (ulCriticalNesting == 0) { - while(1); + if( ulCriticalNesting == 0 ) + { + while( 1 ) + { + } } - ulCriticalNesting --; - if (ulCriticalNesting == 0) + ulCriticalNesting--; + + if( ulCriticalNesting == 0 ) { portENABLE_INTERRUPTS(); - if (pendsvflag) + if( pendsvflag ) { pendsvflag = 0; portYIELD(); @@ -104,30 +110,36 @@ void vPortExitCritical( void ) } #if configUSE_PREEMPTION == 0 -void xPortSysTickHandler( void ) -{ - portLONG ulDummy; + void xPortSysTickHandler( void ) + { + portLONG ulDummy; - ulDummy = portSET_INTERRUPT_MASK_FROM_ISR(); - xTaskIncrementTick(); - portCLEAR_INTERRUPT_MASK_FROM_ISR( ulDummy ); -} + ulDummy = portSET_INTERRUPT_MASK_FROM_ISR(); + xTaskIncrementTick(); + portCLEAR_INTERRUPT_MASK_FROM_ISR( ulDummy ); + } #else -void xPortSysTickHandler( void ) -{ - portLONG ulDummy; - - ulDummy = portSET_INTERRUPT_MASK_FROM_ISR(); + void xPortSysTickHandler( void ) { - if (xTaskIncrementTick() != pdFALSE) + portLONG ulDummy; + + ulDummy = portSET_INTERRUPT_MASK_FROM_ISR(); + traceISR_ENTER(); { - portYIELD_FROM_ISR(pdTRUE); + if( xTaskIncrementTick() != pdFALSE ) + { + traceISR_EXIT_TO_SCHEDULER(); + portYIELD_FROM_ISR( pdTRUE ); + } + else + { + traceISR_EXIT(); + } } + portCLEAR_INTERRUPT_MASK_FROM_ISR( ulDummy ); } - portCLEAR_INTERRUPT_MASK_FROM_ISR( ulDummy ); -} -#endif +#endif /* if configUSE_PREEMPTION == 0 */ void vPortYieldHandler( void ) { @@ -140,12 +152,17 @@ void vPortYieldHandler( void ) portCLEAR_INTERRUPT_MASK_FROM_ISR( ulSavedInterruptMask ); } -__attribute__((weak)) void vApplicationStackOverflowHook( xTaskHandle *pxTask, signed portCHAR *pcTaskName ) +__attribute__( ( weak ) ) void vApplicationStackOverflowHook( xTaskHandle * pxTask, + signed portCHAR * pcTaskName ) { - for(;;); + for( ; ; ) + { + } } -__attribute__((weak)) void vApplicationMallocFailedHook( void ) +__attribute__( ( weak ) ) void vApplicationMallocFailedHook( void ) { - for(;;); + for( ; ; ) + { + } } diff --git a/Source/portable/ThirdParty/CDK/T-HEAD_CK802/portmacro.h b/Source/portable/ThirdParty/CDK/T-HEAD_CK802/portmacro.h index 2c6979faf..76c72f488 100644 --- a/Source/portable/ThirdParty/CDK/T-HEAD_CK802/portmacro.h +++ b/Source/portable/ThirdParty/CDK/T-HEAD_CK802/portmacro.h @@ -29,7 +29,7 @@ #include #include -extern void vPortYield(void); +extern void vPortYield( void ); /* *INDENT-OFF* */ #ifdef __cplusplus @@ -50,24 +50,24 @@ extern void vPortYield(void); */ /* Type definitions. */ -#define portCHAR char -#define portFLOAT float -#define portDOUBLE double -#define portLONG long -#define portSHORT short -#define portSTACK_TYPE uint32_t -#define portBASE_TYPE long - -typedef portSTACK_TYPE StackType_t; -typedef long BaseType_t; -typedef unsigned long UBaseType_t; -typedef void (*portvectorfunc)(void); - -#if( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS ) - typedef uint16_t TickType_t; - #define portMAX_DELAY ( TickType_t ) 0xffff -#elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS ) - typedef uint32_t TickType_t; +#define portCHAR char +#define portFLOAT float +#define portDOUBLE double +#define portLONG long +#define portSHORT short +#define portSTACK_TYPE uint32_t +#define portBASE_TYPE long + +typedef portSTACK_TYPE StackType_t; +typedef long BaseType_t; +typedef unsigned long UBaseType_t; +typedef void (* portvectorfunc)( void ); + +#if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS ) + typedef uint16_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffff +#elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS ) + typedef uint32_t TickType_t; #define portMAX_DELAY ( TickType_t ) 0xffffffffUL #else #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width. @@ -75,10 +75,10 @@ typedef void (*portvectorfunc)(void); /* Hardware specifics. */ -#define portBYTE_ALIGNMENT 8 -#define portSTACK_GROWTH -1 -#define portMS_PERIOD_TICK 10 -#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) +#define portBYTE_ALIGNMENT 8 +#define portSTACK_GROWTH -1 +#define portMS_PERIOD_TICK 10 +#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) static inline void vPortEnableInterrupt( void ) @@ -91,69 +91,77 @@ static inline void vPortDisableInterrupt( void ) __disable_irq(); } -static inline portLONG GetCurrentPSR (void) +static inline portLONG GetCurrentPSR( void ) { return __get_PSR(); } -static inline portLONG SaveLocalPSR (void) +static inline portLONG SaveLocalPSR( void ) { portLONG flags = __get_PSR(); + __disable_irq(); return flags; } -static inline void RestoreLocalPSR (portLONG newMask) +static inline void RestoreLocalPSR( portLONG newMask ) { - __asm__ __volatile__( - "mtcr %0, psr \n" - : - :"r" (newMask) - :"memory" - ); + __asm__ __volatile__ ( + "mtcr %0, psr \n" + : + : "r" ( newMask ) + : "memory" + ); } extern void vPortEnterCritical( void ); extern void vPortExitCritical( void ); -extern __attribute__((naked)) void cpu_yeild(void); +extern __attribute__( ( naked ) ) void cpu_yeild( void ); -#define portDISABLE_INTERRUPTS() vPortDisableInterrupt() -#define portENABLE_INTERRUPTS() vPortEnableInterrupt() -#define portENTER_CRITICAL() vPortEnterCritical() -#define portEXIT_CRITICAL() vPortExitCritical() -#define portSET_INTERRUPT_MASK_FROM_ISR() SaveLocalPSR() -#define portCLEAR_INTERRUPT_MASK_FROM_ISR(a) RestoreLocalPSR(a) +#define portDISABLE_INTERRUPTS() vPortDisableInterrupt() +#define portENABLE_INTERRUPTS() vPortEnableInterrupt() +#define portENTER_CRITICAL() vPortEnterCritical() +#define portEXIT_CRITICAL() vPortExitCritical() +#define portSET_INTERRUPT_MASK_FROM_ISR() SaveLocalPSR() +#define portCLEAR_INTERRUPT_MASK_FROM_ISR( a ) RestoreLocalPSR( a ) -#define portNOP() asm("nop") +#define portNOP() asm ( "nop" ) extern portLONG ulCriticalNesting; extern portLONG pendsvflag; -#define portYIELD() if (ulCriticalNesting == 0) \ - { \ - vPortYield(); \ - } \ - else \ - { \ - pendsvflag = 1; \ - } \ - portNOP();portNOP() +#define portYIELD() \ + if( ulCriticalNesting == 0 ) \ + { \ + vPortYield(); \ + } \ + else \ + { \ + pendsvflag = 1; \ + } \ + portNOP(); portNOP() /*-----------------------------------------------------------*/ /* Task function macros as described on the FreeRTOS.org WEB site. */ -#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters ) __attribute__((noreturn)) -#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters ) +#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters ) __attribute__( ( noreturn ) ) +#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters ) /*-----------------------------------------------------------*/ -#define portEND_SWITCHING_ISR( xSwitchRequired ) do { \ - if( xSwitchRequired != pdFALSE ) \ - { \ - portYIELD(); \ - } \ - }while(0) - -#define portYIELD_FROM_ISR( a ) vTaskSwitchContext() +#define portEND_SWITCHING_ISR( xSwitchRequired ) \ + do { \ + if( xSwitchRequired != pdFALSE ) \ + { \ + traceISR_EXIT_TO_SCHEDULER(); \ + portYIELD(); \ + } \ + else \ + { \ + traceISR_EXIT(); \ + } \ + } while( 0 ) + +#define portYIELD_FROM_ISR( a ) vTaskSwitchContext() diff --git a/Source/portable/ThirdParty/Community-Supported-Ports/CCS/C2000_C28x/README.md b/Source/portable/ThirdParty/Community-Supported-Ports/CCS/C2000_C28x/README.md index 78256a0e2..b630d1388 100644 --- a/Source/portable/ThirdParty/Community-Supported-Ports/CCS/C2000_C28x/README.md +++ b/Source/portable/ThirdParty/Community-Supported-Ports/CCS/C2000_C28x/README.md @@ -8,9 +8,6 @@ FreeRTOS-Community-Supported-Demos\C2000_F2838x_C28x_CCS\freertos_ex1_c28x_port_ This port is distributed under MIT open source license. -KNOWN ISSUES: -Support for "fpu64" is not added yet to the port. The examples should specify "fpu32" as option for floating point. - TOOL CHAIN SUPPORT: Code Composer Studio™ IDE (CCS) v11.1.0 or newer C2000 Compiler v20.2.1.LTS or newer diff --git a/Source/portable/ThirdParty/Community-Supported-Ports/CCS/C2000_C28x/port.c b/Source/portable/ThirdParty/Community-Supported-Ports/CCS/C2000_C28x/port.c index 575513283..f869683aa 100644 --- a/Source/portable/ThirdParty/Community-Supported-Ports/CCS/C2000_C28x/port.c +++ b/Source/portable/ThirdParty/Community-Supported-Ports/CCS/C2000_C28x/port.c @@ -33,7 +33,11 @@ // Constants required for hardware setup. #define portINITIAL_CRITICAL_NESTING ( ( uint16_t ) 10 ) #define portFLAGS_INT_ENABLED ( ( StackType_t ) 0x08 ) -#if defined(__TMS320C28XX_FPU32__) +#if defined(__TMS320C28XX_FPU64__) +# define AUX_REGISTERS_TO_SAVE 27 // XAR + FPU registers +# define XAR4_REGISTER_POSITION 6 // XAR4 position in AUX registers array +# define STF_REGISTER_POSITION 10 // STF position in AUX registers array +#elif defined(__TMS320C28XX_FPU32__) # define AUX_REGISTERS_TO_SAVE 19 // XAR + FPU registers # define XAR4_REGISTER_POSITION 6 // XAR4 position in AUX registers array # define STF_REGISTER_POSITION 10 // STF position in AUX registers array diff --git a/Source/portable/ThirdParty/Community-Supported-Ports/CCS/C2000_C28x/portasm.asm b/Source/portable/ThirdParty/Community-Supported-Ports/CCS/C2000_C28x/portasm.asm index 35c13ae0d..ff2795a5f 100644 --- a/Source/portable/ThirdParty/Community-Supported-Ports/CCS/C2000_C28x/portasm.asm +++ b/Source/portable/ThirdParty/Community-Supported-Ports/CCS/C2000_C28x/portasm.asm @@ -61,7 +61,11 @@ _portRESTORE_FIRST_CONTEXT: ; Restore XAR4 and RPC from saved task stack. ; and return to main task function. ; SP should be set to stack start plus 2 before LRETR. + .if .TMS320C2800_FPU64 = 1 + SUBB SP, #44 + .else SUBB SP, #28 + .endif POP XAR4 SUBB SP, #14 POP RPC @@ -82,14 +86,35 @@ _portTICK_ISR: MOVL *SP++, XAR6 MOVL *SP++, XAR7 MOV32 *SP++, STF + + .if .TMS320C2800_FPU64 = 1 + MOV32 *SP++, R0L MOV32 *SP++, R0H + MOV32 *SP++, R1L MOV32 *SP++, R1H + MOV32 *SP++, R2L MOV32 *SP++, R2H + MOV32 *SP++, R3L MOV32 *SP++, R3H + MOV32 *SP++, R4L MOV32 *SP++, R4H + MOV32 *SP++, R5L MOV32 *SP++, R5H + MOV32 *SP++, R6L MOV32 *SP++, R6H + MOV32 *SP++, R7L MOV32 *SP++, R7H + .else + MOV32 *SP++, R0H + MOV32 *SP++, R1H + MOV32 *SP++, R2H + MOV32 *SP++, R3H + MOV32 *SP++, R4H + MOV32 *SP++, R5H + MOV32 *SP++, R6H + MOV32 *SP++, R7H + .endif + PUSH DP:ST1 ; Save critical section nesting counter @@ -110,10 +135,22 @@ _portTICK_ISR: POP AL TBIT AL, #4 SB SPA_BIT_SET, TC + .if .TMS320C2800_FPU64 = 1 + MOVZ AR7, @SP ;load lower half of XAR7 with contents of SP, clear upper half of XAR7 + SUBB XAR7, #62 + MOVZ AR7, *XAR7 + .else MOV AR7, *-SP[46] + .endif SB SAVE_IER, UNC SPA_BIT_SET: + .if .TMS320C2800_FPU64 = 1 + MOVZ AR7, @SP ;load lower half of XAR7 with contents of SP, clear upper half of XAR7 + SUBB XAR7, #64 + MOV AR7, *XAR7 + .else MOV AR7, *-SP[48] + .endif SAVE_IER: MOVL *SP++, XAR7 @@ -164,12 +201,42 @@ SKIP_CONTEXT_SWITCH: POP AL TBIT AL, #4 SB SPA_BIT_SET_RESTORE, TC + .if .TMS320C2800_FPU64 = 1 + MOVZ AR6, @SP ;load lower half of XAR6 with contents of SP, clear upper half of XAR6 + SUBB XAR6, #58 + MOV *XAR6, AR7 + .else MOV *-SP[42], AR7 + .endif SB RESTORE_CONTEXT, UNC SPA_BIT_SET_RESTORE: + .if .TMS320C2800_FPU64 = 1 + MOVZ AR6, @SP ;load lower half of XAR6 with contents of SP, clear upper half of XAR6 + SUBB XAR6, #60 + MOV *XAR6, AR7 + .else MOV *-SP[44], AR7 + .endif RESTORE_CONTEXT: + .if .TMS320C2800_FPU64 = 1 + MOV32 R7H, *--SP + MOV32 R7L, *--SP + MOV32 R6H, *--SP + MOV32 R6L, *--SP + MOV32 R5H, *--SP + MOV32 R5L, *--SP + MOV32 R4H, *--SP + MOV32 R4L, *--SP + MOV32 R3H, *--SP + MOV32 R3L, *--SP + MOV32 R2H, *--SP + MOV32 R2L, *--SP + MOV32 R1H, *--SP + MOV32 R1L, *--SP + MOV32 R0H, *--SP + MOV32 R0L, *--SP + .else MOV32 R7H, *--SP MOV32 R6H, *--SP MOV32 R5H, *--SP @@ -178,6 +245,7 @@ RESTORE_CONTEXT: MOV32 R2H, *--SP MOV32 R1H, *--SP MOV32 R0H, *--SP + .endif MOV32 STF, *--SP MOVL XAR7, *--SP MOVL XAR6, *--SP @@ -314,3 +382,4 @@ RESTORE_CONTEXT: IRET .endif + diff --git a/Source/portable/ThirdParty/Community-Supported-Ports/GCC/TriCore_38xa/portmacro.h b/Source/portable/ThirdParty/Community-Supported-Ports/GCC/TriCore_38xa/portmacro.h index b2c4ebcd0..72b30e9eb 100644 --- a/Source/portable/ThirdParty/Community-Supported-Ports/GCC/TriCore_38xa/portmacro.h +++ b/Source/portable/ThirdParty/Community-Supported-Ports/GCC/TriCore_38xa/portmacro.h @@ -28,9 +28,11 @@ #ifndef _PORTABLE_GCC_TRICORE_PORTMACRO_H_ #define _PORTABLE_GCC_TRICORE_PORTMACRO_H_ +/* *INDENT-OFF* */ #ifdef __cplusplus -extern "C" { + extern "C" { #endif +/* *INDENT-ON* */ #include "port.h" @@ -168,8 +170,10 @@ extern uint32_t uxPortSetInterruptMaskFromISR( void ); void vPortReclaimCSA( uint32_t *pxTCB ); #define portCLEAN_UP_TCB( pxTCB ) vPortReclaimCSA( ( uint32_t * ) ( pxTCB ) ) +/* *INDENT-OFF* */ #ifdef __cplusplus -} + } #endif +/* *INDENT-ON* */ #endif /* _PORTABLE_GCC_TRICORE_PORTMACRO_H_ */ diff --git a/Source/portable/ThirdParty/Community-Supported-Ports/README.md b/Source/portable/ThirdParty/Community-Supported-Ports/README.md index 209ffc3bd..b0126d70f 100644 --- a/Source/portable/ThirdParty/Community-Supported-Ports/README.md +++ b/Source/portable/ThirdParty/Community-Supported-Ports/README.md @@ -1,7 +1,14 @@ ## FreeRTOS Community Supported Ports This repository contains FreeRTOS ports supported by FreeRTOS community members. -Follow the steps below to contribute a FreeRTOS port to this repository: +For a community supported FreeRTOS port: + +* The code has not been reviewed by the FreeRTOS team. +* Tests may or may not exist for the FreeRTOS port. +* Customer queries as well as bugs are addressed by the community. + +A new FreeRTOS port can be directly contributed by anyone. Follow the steps +below to contribute a FreeRTOS port to this repository: 1. Write FreeRTOS port for your Compiler and Architecture. 2. *[Optional]* Create a project in the [FreeRTOS Community Supported Demos Repository](https://github.com/FreeRTOS/FreeRTOS-Community-Supported-Demos/tree/main) diff --git a/Source/portable/ThirdParty/Community-Supported-Ports/Z88DK/Z180/port.c b/Source/portable/ThirdParty/Community-Supported-Ports/Z88DK/Z180/port.c index 59a815f32..d3ddb58c8 100644 --- a/Source/portable/ThirdParty/Community-Supported-Ports/Z88DK/Z180/port.c +++ b/Source/portable/ThirdParty/Community-Supported-Ports/Z88DK/Z180/port.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.4.3 + * FreeRTOS Kernel V10.5.1+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of @@ -42,29 +42,21 @@ any details of its type. */ typedef void TCB_t; extern volatile TCB_t * volatile pxCurrentTCB; + /*-----------------------------------------------------------*/ /* - * Macro to save all the general purpose registers, the save the stack pointer - * into the TCB. - * - * The first thing we do is save the flags then disable interrupts. This is to - * guard our stack against having a context switch interrupt after we have already - * pushed the registers onto the stack. - * - * The interrupts will have been disabled during the call to portSAVE_CONTEXT() - * so we need not worry about reading/writing to the stack pointer. + * Macros to set up, restart (reload), and stop the PRT1 Timer used for + * the System Tick. */ #define configTICK_RATE_HZ (256) /* Timer configured */ #define configISR_ORG ASMPC /* ISR relocation */ #define configISR_IVT 0xFFE6 /* PRT1 address */ -#ifdef __SCCZ80 - #define configSETUP_TIMER_INTERRUPT() \ do{ \ - asm( \ + __asm__( \ "EXTERN __CPU_CLOCK \n" \ "EXTERN RLDR1L, RLDR1H \n" \ "EXTERN TCR, TCR_TIE1, TCR_TDE1 \n" \ @@ -85,7 +77,7 @@ extern volatile TCB_t * volatile pxCurrentTCB; #define configRESET_TIMER_INTERRUPT() \ do{ \ - asm( \ + __asm__( \ "EXTERN TCR, TMDR1L \n" \ "in0 a,(TCR) \n" \ "in0 a,(TMDR1L) \n" \ @@ -94,7 +86,7 @@ extern volatile TCB_t * volatile pxCurrentTCB; #define configSTOP_TIMER_INTERRUPT() \ do{ \ - asm( \ + __asm__( \ "EXTERN TCR, TCR_TIE1, TCR_TDE1 \n" \ "; disable down counting and interrupts for PRT1\n" \ "in0 a,(TCR) \n" \ @@ -103,55 +95,6 @@ extern volatile TCB_t * volatile pxCurrentTCB; ); \ }while(0) -#endif - -#ifdef __SDCC - -#define configSETUP_TIMER_INTERRUPT() \ - do{ \ - __asm \ - EXTERN __CPU_CLOCK \ - EXTERN RLDR1L, RLDR1H \ - EXTERN TCR, TCR_TIE1, TCR_TDE1 \ - ; address of ISR \ - ld de,_timer_isr \ - ld hl,configISR_IVT ; PRT1 address \ - ld (hl),e \ - inc hl \ - ld (hl),d \ - ; we do configTICK_RATE_HZ ticks per second \ - ld hl,__CPU_CLOCK/configTICK_RATE_HZ/20-1 \ - out0(RLDR1L),l \ - out0(RLDR1H),h \ - ; enable down counting and interrupts for PRT1 \ - in0 a,(TCR) \ - or TCR_TIE1|TCR_TDE1 \ - out0 (TCR),a \ - __endasm; \ - }while(0) - -#define configRESET_TIMER_INTERRUPT() \ - do{ \ - __asm \ - EXTERN TCR, TMDR1L \ - ; reset interrupt for PRT1 \ - in0 a,(TCR) \ - in0 a,(TMDR1L) \ - __endasm; \ - }while(0) - -#define configSTOP_TIMER_INTERRUPT() \ - do{ \ - __asm \ - EXTERN TCR, TCR_TIE1, TCR_TDE1 \ - ; disable down counting and interrupts for PRT1 \ - in0 a,(TCR) \ - xor TCR_TIE1|TCR_TDE1 \ - out0 (TCR),a \ - __endasm; \ - }while(0) - -#endif /*-----------------------------------------------------------*/ @@ -159,6 +102,7 @@ extern volatile TCB_t * volatile pxCurrentTCB; * Perform hardware setup to enable ticks from Timer. */ static void prvSetupTimerInterrupt( void ) __preserves_regs(iyh,iyl); + /*-----------------------------------------------------------*/ /* diff --git a/Source/portable/ThirdParty/Community-Supported-Ports/Z88DK/Z180/portmacro.h b/Source/portable/ThirdParty/Community-Supported-Ports/Z88DK/Z180/portmacro.h index f8f2f02eb..254f053ba 100644 --- a/Source/portable/ThirdParty/Community-Supported-Ports/Z88DK/Z180/portmacro.h +++ b/Source/portable/ThirdParty/Community-Supported-Ports/Z88DK/Z180/portmacro.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.4.3 + * FreeRTOS Kernel V10.5.1+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of @@ -24,12 +24,15 @@ * */ + #ifndef PORTMACRO_H #define PORTMACRO_H +/* *INDENT-OFF* */ #ifdef __cplusplus -extern "C" { + extern "C" { #endif +/* *INDENT-ON* */ /*----------------------------------------------------------- * Port specific definitions. @@ -48,32 +51,42 @@ extern "C" { #define portLONG long #define portSHORT int -typedef uint16_t StackType_t; -typedef int8_t BaseType_t; -typedef uint8_t UBaseType_t; +typedef uint16_t StackType_t; +typedef int8_t BaseType_t; +typedef uint8_t UBaseType_t; -#if configUSE_16_BIT_TICKS == 1 - typedef uint16_t TickType_t; - #define portMAX_DELAY ( TickType_t ) 0xffff +#if configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS + typedef uint16_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffff +#elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS ) + typedef uint32_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffffffffUL #else - typedef uint32_t TickType_t; - #define portMAX_DELAY ( TickType_t ) 0xffffffffUL + #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width. #endif + /*-----------------------------------------------------------*/ /* General purpose stringify macros. */ #define string(a) __string(a) #define __string(a) #a + /*-----------------------------------------------------------*/ -/* Critical section management using sccz80 compiler. */ +/* Architecture specifics. */ -#ifdef __SCCZ80 +#define portSTACK_GROWTH ( -1 ) +#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) +#define portBYTE_ALIGNMENT 1 + +/*-----------------------------------------------------------*/ + +/* Critical section management. */ #define portENTER_CRITICAL() \ do{ \ - asm( \ + __asm__( \ "ld a,i \n" \ "di \n" \ "push af \n" \ @@ -82,7 +95,7 @@ typedef uint8_t UBaseType_t; #define portEXIT_CRITICAL() \ do{ \ - asm( \ + __asm__( \ "pop af \n" \ "; di ; unneeded \n" \ "jp PO,ASMPC+4 \n" \ @@ -92,32 +105,39 @@ typedef uint8_t UBaseType_t; #define portDISABLE_INTERRUPTS() \ do{ \ - asm( \ + __asm__( \ "di \n" \ ); \ }while(0) #define portENABLE_INTERRUPTS() \ do{ \ - asm( \ + __asm__( \ "ei \n" \ ); \ }while(0) #define portNOP() \ do{ \ - asm( \ + __asm__( \ "nop \n" \ ); \ }while(0) /* * Macros to save all the registers, and save the stack pointer into the TCB. + * + * The first thing we do is save the flags then disable interrupts. This is to + * guard our stack against having a context switch interrupt after we have already + * pushed the registers onto the stack. + * + * The interrupts will have been disabled during the call to portSAVE_CONTEXT() + * so we need not worry about reading/writing to the stack pointer. */ #define portSAVE_CONTEXT() \ do{ \ - asm( \ + __asm__( \ "push af \n" \ "ld a,i \n" \ "di \n" \ @@ -145,7 +165,7 @@ typedef uint8_t UBaseType_t; #define portRESTORE_CONTEXT() \ do{ \ - asm( \ + __asm__( \ "ld hl,(_pxCurrentTCB) \n" \ "ld e,(hl) \n" \ "inc hl \n" \ @@ -174,7 +194,7 @@ typedef uint8_t UBaseType_t; #define portSAVE_CONTEXT_IN_ISR() \ do{ \ - asm( \ + __asm__( \ "PHASE "string(configISR_ORG)" \n" \ "._timer_isr_start \n" \ "push af \n" \ @@ -204,7 +224,7 @@ typedef uint8_t UBaseType_t; #define portRESTORE_CONTEXT_IN_ISR()\ do{ \ - asm( \ + __asm__( \ "ld hl,(_pxCurrentTCB) \n" \ "ld e,(hl) \n" \ "inc hl \n" \ @@ -233,183 +253,6 @@ typedef uint8_t UBaseType_t; ); \ }while(0) -#endif -/*-----------------------------------------------------------*/ - -/* Critical section management using sdcc compiler. */ - -#ifdef __SDCC - -#define portENTER_CRITICAL() \ - do{ \ - __asm \ - ld a,i \ - di \ - push af \ - __endasm; \ - }while(0) - -#define portEXIT_CRITICAL() \ - do{ \ - __asm \ - pop af \ - ; di ; unneeded \ - jp PO,ASMPC+4 \ - ei \ - __endasm; \ - }while(0) - -#define portDISABLE_INTERRUPTS() \ - do{ \ - __asm \ - di \ - __endasm; \ - }while(0) - -#define portENABLE_INTERRUPTS() \ - do{ \ - __asm \ - ei \ - __endasm; \ - }while(0) - -#define portNOP() \ - do{ \ - __asm \ - nop \ - __endasm; \ - }while(0) - -/* - * Macros to save all the registers, and save the stack pointer into the TCB. - */ - -#define portSAVE_CONTEXT() \ - do{ \ - __asm \ - push af \ - ld a,i \ - di \ - push af ; iff1:iff2 \ - push bc \ - push de \ - push hl \ - exx \ - ex af,af \ - push af \ - push bc \ - push de \ - push hl \ - push ix \ - push iy \ - ld hl,0 \ - add hl,sp \ - ld de,(_pxCurrentTCB) \ - ex de,hl \ - ld (hl),e \ - inc hl \ - ld (hl),d \ - __endasm; \ - }while(0) - -#define portRESTORE_CONTEXT() \ - do{ \ - __asm \ - ld hl,(_pxCurrentTCB) \ - ld e,(hl) \ - inc hl \ - ld d,(hl) \ - ex de,hl \ - ld sp,hl \ - pop iy \ - pop ix \ - pop hl \ - pop de \ - pop bc \ - pop af \ - ex af,af \ - exx \ - pop hl \ - pop de \ - pop bc \ - pop af ; iff1:iff2 \ - ; di ; unneeded \ - jp PO,ASMPC+4 \ - ei \ - pop af \ - ret \ - __endasm; \ - }while(0) - -#define portSAVE_CONTEXT_IN_ISR() \ - do{ \ - __asm \ - PHASE configISR_ORG \ - _timer_isr_start: \ - push af \ - ld a,0x7F \ - inc a ; set PE \ - push af ; iff1:iff2 \ - push bc \ - push de \ - push hl \ - exx \ - ex af,af \ - push af \ - push bc \ - push de \ - push hl \ - push ix \ - push iy \ - ld hl,0 \ - add hl,sp \ - ld de,(_pxCurrentTCB) \ - ex de,hl \ - ld (hl),e \ - inc hl \ - ld (hl),d \ - __endasm; \ - }while(0) - -#define portRESTORE_CONTEXT_IN_ISR()\ - do{ \ - __asm \ - ld hl,(_pxCurrentTCB) \ - ld e,(hl) \ - inc hl \ - ld d,(hl) \ - ex de,hl \ - ld sp,hl \ - pop iy \ - pop ix \ - pop hl \ - pop de \ - pop bc \ - pop af \ - ex af,af \ - exx \ - pop hl \ - pop de \ - pop bc \ - pop af ; iff1:iff2 \ - ; di ; unneeded \ - jp PO,ASMPC+4 \ - ei \ - pop af \ - reti \ - _timer_isr_end: \ - DEPHASE \ - __endasm; \ - }while(0) - -#endif -/*-----------------------------------------------------------*/ - -/* Architecture specifics. */ - -#define portSTACK_GROWTH ( -1 ) -#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) -#define portBYTE_ALIGNMENT 1 /*-----------------------------------------------------------*/ /* Kernel utilities. */ @@ -424,8 +267,10 @@ extern void vPortYieldFromISR( void ); #define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters ) #define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters ) +/* *INDENT-OFF* */ #ifdef __cplusplus -} + } #endif +/* *INDENT-ON* */ #endif /* PORTMACRO_H */ diff --git a/Source/portable/ThirdParty/Community-Supported-Ports/Z88DK/Z180/readme.md b/Source/portable/ThirdParty/Community-Supported-Ports/Z88DK/Z180/readme.md index 89af17a7d..b13054d7c 100644 --- a/Source/portable/ThirdParty/Community-Supported-Ports/Z88DK/Z180/readme.md +++ b/Source/portable/ThirdParty/Community-Supported-Ports/Z88DK/Z180/readme.md @@ -1,12 +1,12 @@ -

z180 support

+

Z180 support

Description ----------- -This PR establishes support for a Zilog z180 port, using the Programmable Reload Timer 1, configured at 256 Hz. +This PR establishes support for a Zilog Z180 port, using the Programmable Reload Timer 1, configured at 256 Hz. -Because of the generality of the z180, the address of the Interrupt Vector for PRT1 is configurable, and must be configured by the `crt0.asm` outside of this port. A configuration assumption has been made. +Because of the generality of the Z180, the address of the Interrupt Vector for the programmable timer PRT1 is configurable, and must be configured by the `crt0.asm` outside of this port. A configuration assumption has been made, which should be checked against the actual system environment. -The two compilers ([used by the z88dk](https://github.com/z88dk/z88dk)) are supported. The sccz80 compiler and the sdcc compiler. The PR is located under Z88dk. +The two compilers ([used by the z88dk](https://github.com/z88dk/z88dk)) are supported. The sccz80 compiler and the sdcc compiler. The in-line assembly language notation used can be read by both compilers. Background ----------- diff --git a/Source/portable/ThirdParty/GCC/ARC_EM_HS/arc_freertos_exceptions.c b/Source/portable/ThirdParty/GCC/ARC_EM_HS/arc_freertos_exceptions.c index 69807a10f..09d2c639c 100644 --- a/Source/portable/ThirdParty/GCC/ARC_EM_HS/arc_freertos_exceptions.c +++ b/Source/portable/ThirdParty/GCC/ARC_EM_HS/arc_freertos_exceptions.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2020 Synopsys, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/Source/portable/ThirdParty/GCC/ARC_EM_HS/arc_freertos_exceptions.h b/Source/portable/ThirdParty/GCC/ARC_EM_HS/arc_freertos_exceptions.h index 8fe536328..d5bc6426e 100644 --- a/Source/portable/ThirdParty/GCC/ARC_EM_HS/arc_freertos_exceptions.h +++ b/Source/portable/ThirdParty/GCC/ARC_EM_HS/arc_freertos_exceptions.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2020 Synopsys, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/Source/portable/ThirdParty/GCC/ARC_EM_HS/arc_support.s b/Source/portable/ThirdParty/GCC/ARC_EM_HS/arc_support.s index b12ccde46..0dd643e49 100644 --- a/Source/portable/ThirdParty/GCC/ARC_EM_HS/arc_support.s +++ b/Source/portable/ThirdParty/GCC/ARC_EM_HS/arc_support.s @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2020 Synopsys, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/Source/portable/ThirdParty/GCC/ARC_EM_HS/freertos_tls.c b/Source/portable/ThirdParty/GCC/ARC_EM_HS/freertos_tls.c index cce374cc0..ba865e6ec 100644 --- a/Source/portable/ThirdParty/GCC/ARC_EM_HS/freertos_tls.c +++ b/Source/portable/ThirdParty/GCC/ARC_EM_HS/freertos_tls.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2020 Synopsys, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/Source/portable/ThirdParty/GCC/ARC_EM_HS/port.c b/Source/portable/ThirdParty/GCC/ARC_EM_HS/port.c index 8ef46685e..261fcdbac 100644 --- a/Source/portable/ThirdParty/GCC/ARC_EM_HS/port.c +++ b/Source/portable/ThirdParty/GCC/ARC_EM_HS/port.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2020 Synopsys, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/Source/portable/ThirdParty/GCC/ARC_EM_HS/portmacro.h b/Source/portable/ThirdParty/GCC/ARC_EM_HS/portmacro.h index 9c58240a6..49de957e8 100644 --- a/Source/portable/ThirdParty/GCC/ARC_EM_HS/portmacro.h +++ b/Source/portable/ThirdParty/GCC/ARC_EM_HS/portmacro.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2020 Synopsys, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -78,15 +78,15 @@ #define false 0 /* false */ #endif /* false */ -typedef portSTACK_TYPE StackType_t; -typedef long BaseType_t; -typedef unsigned long UBaseType_t; +typedef portSTACK_TYPE StackType_t; +typedef long BaseType_t; +typedef unsigned long UBaseType_t; #if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS ) - typedef uint16_t TickType_t; - #define portMAX_DELAY ( TickType_t ) 0xffff -#elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS ) - typedef uint32_t TickType_t; + typedef uint16_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffff +#elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS ) + typedef uint32_t TickType_t; #define portMAX_DELAY ( TickType_t ) 0xffffffffUL #else #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width. diff --git a/Source/portable/ThirdParty/GCC/ARC_v1/arc_freertos_exceptions.c b/Source/portable/ThirdParty/GCC/ARC_v1/arc_freertos_exceptions.c index 69807a10f..09d2c639c 100644 --- a/Source/portable/ThirdParty/GCC/ARC_v1/arc_freertos_exceptions.c +++ b/Source/portable/ThirdParty/GCC/ARC_v1/arc_freertos_exceptions.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2020 Synopsys, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/Source/portable/ThirdParty/GCC/ARC_v1/arc_freertos_exceptions.h b/Source/portable/ThirdParty/GCC/ARC_v1/arc_freertos_exceptions.h index 8fe536328..d5bc6426e 100644 --- a/Source/portable/ThirdParty/GCC/ARC_v1/arc_freertos_exceptions.h +++ b/Source/portable/ThirdParty/GCC/ARC_v1/arc_freertos_exceptions.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2020 Synopsys, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/Source/portable/ThirdParty/GCC/ARC_v1/arc_support.s b/Source/portable/ThirdParty/GCC/ARC_v1/arc_support.s index 4215cb622..f250f188c 100644 --- a/Source/portable/ThirdParty/GCC/ARC_v1/arc_support.s +++ b/Source/portable/ThirdParty/GCC/ARC_v1/arc_support.s @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2020 Synopsys, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/Source/portable/ThirdParty/GCC/ARC_v1/port.c b/Source/portable/ThirdParty/GCC/ARC_v1/port.c index 5fce18719..8ec36c573 100644 --- a/Source/portable/ThirdParty/GCC/ARC_v1/port.c +++ b/Source/portable/ThirdParty/GCC/ARC_v1/port.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2020 Synopsys, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -212,7 +212,7 @@ void vPortEndTask( void ) volatile StackType_t * pxTopOfStack; /*< Points to the location of the last item placed on the tasks stack. THIS MUST BE THE FIRST MEMBER OF THE TCB STRUCT. */ #if ( portUSING_MPU_WRAPPERS == 1 ) - xMPU_SETTINGS xMPUSettings; /*< The MPU settings are defined as part of the port layer. THIS MUST BE THE SECOND MEMBER OF THE TCB STRUCT. */ + xMPU_SETTINGS xMPUSettings; /*< The MPU settings are defined as part of the port layer. THIS MUST BE THE SECOND MEMBER OF THE TCB STRUCT. */ #endif ListItem_t xStateListItem; /*< The list that the state list item of a task is reference from denotes the state of that task (Ready, Blocked, Suspended ). */ @@ -222,20 +222,20 @@ void vPortEndTask( void ) char pcTaskName[ configMAX_TASK_NAME_LEN ]; /*< Descriptive name given to the task when created. Facilitates debugging only. */ /*lint !e971 Unqualified char types are allowed for strings and single characters only. */ #if ( ( portSTACK_GROWTH > 0 ) || ( configRECORD_STACK_HIGH_ADDRESS == 1 ) ) - StackType_t * pxEndOfStack; /*< Points to the highest valid address for the stack. */ + StackType_t * pxEndOfStack; /*< Points to the highest valid address for the stack. */ #endif #if ( portCRITICAL_NESTING_IN_TCB == 1 ) - UBaseType_t uxCriticalNesting; /*< Holds the critical section nesting depth for ports that do not maintain their own count in the port layer. */ + UBaseType_t uxCriticalNesting; /*< Holds the critical section nesting depth for ports that do not maintain their own count in the port layer. */ #endif #if ( configUSE_TRACE_FACILITY == 1 ) - UBaseType_t uxTCBNumber; /*< Stores a number that increments each time a TCB is created. It allows debuggers to determine when a task has been deleted and then recreated. */ - UBaseType_t uxTaskNumber; /*< Stores a number specifically for use by third party trace code. */ + UBaseType_t uxTCBNumber; /*< Stores a number that increments each time a TCB is created. It allows debuggers to determine when a task has been deleted and then recreated. */ + UBaseType_t uxTaskNumber; /*< Stores a number specifically for use by third party trace code. */ #endif #if ( configUSE_MUTEXES == 1 ) - UBaseType_t uxBasePriority; /*< The priority last assigned to the task - used by the priority inheritance mechanism. */ + UBaseType_t uxBasePriority; /*< The priority last assigned to the task - used by the priority inheritance mechanism. */ UBaseType_t uxMutexesHeld; #endif @@ -248,7 +248,7 @@ void vPortEndTask( void ) #endif #if ( configGENERATE_RUN_TIME_STATS == 1 ) - uint32_t ulRunTimeCounter; /*< Stores the amount of time the task has spent in the Running state. */ + uint32_t ulRunTimeCounter; /*< Stores the amount of time the task has spent in the Running state. */ #endif #if ( configUSE_C_RUNTIME_TLS_SUPPORT == 1 ) diff --git a/Source/portable/ThirdParty/GCC/ARC_v1/portmacro.h b/Source/portable/ThirdParty/GCC/ARC_v1/portmacro.h index 6036735b3..f1b87b9f4 100644 --- a/Source/portable/ThirdParty/GCC/ARC_v1/portmacro.h +++ b/Source/portable/ThirdParty/GCC/ARC_v1/portmacro.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2020 Synopsys, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -27,8 +27,8 @@ */ #ifndef PORTMACRO_H - #define PORTMACRO_H - #include "embARC.h" +#define PORTMACRO_H +#include "embARC.h" /* *INDENT-OFF* */ #ifdef __cplusplus @@ -37,9 +37,9 @@ /* *INDENT-ON* */ /* record stack high address for stack check */ - #ifndef configRECORD_STACK_HIGH_ADDRESS - #define configRECORD_STACK_HIGH_ADDRESS 1 - #endif +#ifndef configRECORD_STACK_HIGH_ADDRESS + #define configRECORD_STACK_HIGH_ADDRESS 1 +#endif /*----------------------------------------------------------- * Port specific definitions. @@ -52,78 +52,78 @@ */ /* Type definitions. */ - #define portCHAR char - #define portFLOAT float - #define portDOUBLE double - #define portLONG long - #define portSHORT short - #define portSTACK_TYPE unsigned int - #define portBASE_TYPE portLONG - - #ifndef Asm - #define Asm __asm__ volatile - #endif +#define portCHAR char +#define portFLOAT float +#define portDOUBLE double +#define portLONG long +#define portSHORT short +#define portSTACK_TYPE unsigned int +#define portBASE_TYPE portLONG + +#ifndef Asm + #define Asm __asm__ volatile +#endif /* * normal constants */ - #ifndef NULL - #define NULL 0 /* invalid pointer */ - #endif /* NULL */ - - #ifndef true - #define true 1 /* true */ - #endif /* true */ - - #ifndef false - #define false 0 /* false */ - #endif /* false */ - - typedef portSTACK_TYPE StackType_t; - typedef long BaseType_t; - typedef unsigned long UBaseType_t; - - #if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS ) - typedef uint16_t TickType_t; - #define portMAX_DELAY ( TickType_t ) 0xffff - #elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS ) - typedef uint32_t TickType_t; - #define portMAX_DELAY ( TickType_t ) 0xffffffffUL - #else - #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width. - #endif - - #define portNO_CRITICAL_NESTING ( ( uint32_t ) 0 ) - #define portSTACK_GROWTH ( -1 ) - #define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) - #define portBYTE_ALIGNMENT 8 - #define portNOP() Asm( "nop_s" ); - #define IPM_ENABLE_ALL 1 - - #define portYIELD_FROM_ISR() vPortYieldFromIsr() - #define portYIELD() vPortYield() +#ifndef NULL + #define NULL 0 /* invalid pointer */ +#endif /* NULL */ + +#ifndef true + #define true 1 /* true */ +#endif /* true */ + +#ifndef false + #define false 0 /* false */ +#endif /* false */ + +typedef portSTACK_TYPE StackType_t; +typedef long BaseType_t; +typedef unsigned long UBaseType_t; + +#if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS ) + typedef uint16_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffff +#elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS ) + typedef uint32_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffffffffUL +#else + #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width. +#endif + +#define portNO_CRITICAL_NESTING ( ( uint32_t ) 0 ) +#define portSTACK_GROWTH ( -1 ) +#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) +#define portBYTE_ALIGNMENT 8 +#define portNOP() Asm( "nop_s" ); +#define IPM_ENABLE_ALL 1 + +#define portYIELD_FROM_ISR() vPortYieldFromIsr() +#define portYIELD() vPortYield() /* Critical section management. */ - #define portDISABLE_INTERRUPTS() \ - { \ - arc_lock(); \ - } \ +#define portDISABLE_INTERRUPTS() \ + { \ + arc_lock(); \ + } \ - #define portENABLE_INTERRUPTS() \ - { \ - arc_unlock(); \ - } \ +#define portENABLE_INTERRUPTS() \ + { \ + arc_unlock(); \ + } \ - extern volatile unsigned int ulCriticalNesting; +extern volatile unsigned int ulCriticalNesting; - #define portENTER_CRITICAL() \ +#define portENTER_CRITICAL() \ { \ portDISABLE_INTERRUPTS() \ ulCriticalNesting++; \ } - #define portEXIT_CRITICAL() \ +#define portEXIT_CRITICAL() \ { \ if( ulCriticalNesting > portNO_CRITICAL_NESTING ) \ { \ @@ -136,14 +136,14 @@ } - #define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters ) - #define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters ) +#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters ) +#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters ) - #define portCONFIGURE_TIMER_FOR_RUN_TIME_STATS() do {} while( 0 ) /* we use the timer */ - #define portALT_GET_RUN_TIME_COUNTER_VALUE( dest ) ( dest = xTickCount ) +#define portCONFIGURE_TIMER_FOR_RUN_TIME_STATS() do {} while( 0 ) /* we use the timer */ +#define portALT_GET_RUN_TIME_COUNTER_VALUE( dest ) ( dest = xTickCount ) - void vPortYield( void ); - void vPortYieldFromIsr( void ); +void vPortYield( void ); +void vPortYieldFromIsr( void ); /* *INDENT-OFF* */ #ifdef __cplusplus diff --git a/Source/portable/ThirdParty/GCC/ARM_TFM/README.md b/Source/portable/ThirdParty/GCC/ARM_TFM/README.md index 310d21b9c..b1d49fd71 100644 --- a/Source/portable/ThirdParty/GCC/ARM_TFM/README.md +++ b/Source/portable/ThirdParty/GCC/ARM_TFM/README.md @@ -32,7 +32,7 @@ See the [link](https://git.trustedfirmware.org/TF-M/trusted-firmware-m.git/) to ### Build TF-M -Please refer to this [link](https://tf-m-user-guide.trustedfirmware.org/docs/technical_references/instructions/tfm_build_instruction.html) to build the secure side. +Please refer to this [link](https://developer.nordicsemi.com/nRF_Connect_SDK/doc/latest/tfm/building/tfm_build_instruction.html) to build the secure side. _**Note:** ```TFM_NS_MANAGE_NSID``` must be configured as "OFF" when building TF-M_. ## Build the Non-Secure Side diff --git a/Source/portable/ThirdParty/GCC/ARM_TFM/os_wrapper_freertos.c b/Source/portable/ThirdParty/GCC/ARM_TFM/os_wrapper_freertos.c index 4c634ddfa..8eb453930 100644 --- a/Source/portable/ThirdParty/GCC/ARM_TFM/os_wrapper_freertos.c +++ b/Source/portable/ThirdParty/GCC/ARM_TFM/os_wrapper_freertos.c @@ -34,58 +34,72 @@ #include "semphr.h" #include "mpu_wrappers.h" -#if( configSUPPORT_STATIC_ALLOCATION == 1 ) - /* - * In the static allocation, the RAM is required to hold the semaphore's - * state. - */ +#if ( configSUPPORT_STATIC_ALLOCATION == 1 ) + +/* + * In the static allocation, the RAM is required to hold the semaphore's + * state. + */ StaticSemaphore_t xSecureMutexBuffer; #endif void * os_wrapper_mutex_create( void ) { -SemaphoreHandle_t xMutexHandle = NULL; + SemaphoreHandle_t xMutexHandle = NULL; -#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) - xMutexHandle = xSemaphoreCreateMutex(); -#elif( configSUPPORT_STATIC_ALLOCATION == 1 ) - xMutexHandle = xSemaphoreCreateMutexStatic( &xSecureMutexBuffer ); -#endif + #if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) + xMutexHandle = xSemaphoreCreateMutex(); + #elif ( configSUPPORT_STATIC_ALLOCATION == 1 ) + xMutexHandle = xSemaphoreCreateMutexStatic( &xSecureMutexBuffer ); + #endif return ( void * ) xMutexHandle; } /*-----------------------------------------------------------*/ -uint32_t os_wrapper_mutex_acquire( void * handle, uint32_t timeout ) +uint32_t os_wrapper_mutex_acquire( void * handle, + uint32_t timeout ) { -BaseType_t xRet; + BaseType_t xRet; - if( ! handle ) + if( !handle ) + { return OS_WRAPPER_ERROR; + } xRet = xSemaphoreTake( ( SemaphoreHandle_t ) handle, ( timeout == OS_WRAPPER_WAIT_FOREVER ) ? portMAX_DELAY : ( TickType_t ) timeout ); if( xRet != pdPASS ) + { return OS_WRAPPER_ERROR; + } else + { return OS_WRAPPER_SUCCESS; + } } /*-----------------------------------------------------------*/ uint32_t os_wrapper_mutex_release( void * handle ) { -BaseType_t xRet; + BaseType_t xRet; if( !handle ) + { return OS_WRAPPER_ERROR; + } xRet = xSemaphoreGive( ( SemaphoreHandle_t ) handle ); if( xRet != pdPASS ) + { return OS_WRAPPER_ERROR; + } else + { return OS_WRAPPER_SUCCESS; + } } /*-----------------------------------------------------------*/ diff --git a/Source/portable/ThirdParty/GCC/ATmega/port.c b/Source/portable/ThirdParty/GCC/ATmega/port.c index 308ebc73d..f39f8a678 100644 --- a/Source/portable/ThirdParty/GCC/ATmega/port.c +++ b/Source/portable/ThirdParty/GCC/ATmega/port.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -37,167 +37,168 @@ #include "task.h" /*----------------------------------------------------------- - * Implementation of functions defined in portable.h for the AVR port. - *----------------------------------------------------------*/ +* Implementation of functions defined in portable.h for the AVR port. +*----------------------------------------------------------*/ /* Start tasks with interrupts enabled. */ -#define portFLAGS_INT_ENABLED ( (StackType_t) 0x80 ) +#define portFLAGS_INT_ENABLED ( ( StackType_t ) 0x80 ) -#if defined( portUSE_WDTO) +#if defined( portUSE_WDTO ) #warning "Watchdog Timer used for scheduler." - #define portSCHEDULER_ISR WDT_vect + #define portSCHEDULER_ISR WDT_vect #elif defined( portUSE_TIMER0 ) /* Hardware constants for Timer0. */ #warning "Timer0 used for scheduler." - #define portSCHEDULER_ISR TIMER0_COMPA_vect - #define portCLEAR_COUNTER_ON_MATCH ( (uint8_t) _BV(WGM01) ) - #define portPRESCALE_1024 ( (uint8_t) (_BV(CS02)|_BV(CS00)) ) - #define portCLOCK_PRESCALER ( (uint32_t) 1024 ) - #define portCOMPARE_MATCH_A_INTERRUPT_ENABLE ( (uint8_t) _BV(OCIE0A) ) - #define portOCRL OCR0A - #define portTCCRa TCCR0A - #define portTCCRb TCCR0B - #define portTIMSK TIMSK0 - #define portTIFR TIFR0 - -#else + #define portSCHEDULER_ISR TIMER0_COMPA_vect + #define portCLEAR_COUNTER_ON_MATCH ( ( uint8_t ) _BV( WGM01 ) ) + #define portPRESCALE_1024 ( ( uint8_t ) ( _BV( CS02 ) | _BV( CS00 ) ) ) + #define portCLOCK_PRESCALER ( ( uint32_t ) 1024 ) + #define portCOMPARE_MATCH_A_INTERRUPT_ENABLE ( ( uint8_t ) _BV( OCIE0A ) ) + #define portOCRL OCR0A + #define portTCCRa TCCR0A + #define portTCCRb TCCR0B + #define portTIMSK TIMSK0 + #define portTIFR TIFR0 + +#else /* if defined( portUSE_WDTO ) */ #error "No Timer defined for scheduler" -#endif +#endif /* if defined( portUSE_WDTO ) */ /*-----------------------------------------------------------*/ /* We require the address of the pxCurrentTCB variable, but don't want to know -any details of its type. */ + * any details of its type. */ typedef void TCB_t; extern volatile TCB_t * volatile pxCurrentTCB; /*-----------------------------------------------------------*/ /** - Enable the watchdog timer, configuring it for expire after - (value) timeout (which is a combination of the WDP0 - through WDP3 bits). - - This function is derived from but enables only - the interrupt bit (WDIE), rather than the reset bit (WDE). - - Can't find it documented but the WDT, once enabled, - rolls over and fires a new interrupt each time. - - See also the symbolic constants WDTO_15MS et al. - - Updated to match avr-libc 2.0.0 -*/ + * Enable the watchdog timer, configuring it for expire after + * (value) timeout (which is a combination of the WDP0 + * through WDP3 bits). + * + * This function is derived from but enables only + * the interrupt bit (WDIE), rather than the reset bit (WDE). + * + * Can't find it documented but the WDT, once enabled, + * rolls over and fires a new interrupt each time. + * + * See also the symbolic constants WDTO_15MS et al. + * + * Updated to match avr-libc 2.0.0 + */ -#if defined( portUSE_WDTO) +#if defined( portUSE_WDTO ) -static __inline__ -__attribute__ ((__always_inline__)) -void wdt_interrupt_enable (const uint8_t value) -{ - if (_SFR_IO_REG_P (_WD_CONTROL_REG)) + static __inline__ + __attribute__( ( __always_inline__ ) ) + void wdt_interrupt_enable( const uint8_t value ) { - __asm__ __volatile__ ( + if( _SFR_IO_REG_P( _WD_CONTROL_REG ) ) + { + __asm__ __volatile__ ( "in __tmp_reg__,__SREG__" "\n\t" - "cli" "\n\t" - "wdr" "\n\t" - "out %0, %1" "\n\t" - "out __SREG__,__tmp_reg__" "\n\t" - "out %0, %2" "\n\t" + "cli" "\n\t" + "wdr" "\n\t" + "out %0, %1" "\n\t" + "out __SREG__,__tmp_reg__" "\n\t" + "out %0, %2" "\n\t" : /* no outputs */ - : "I" (_SFR_IO_ADDR(_WD_CONTROL_REG)), - "r" ((uint8_t)(_BV(_WD_CHANGE_BIT) | _BV(WDE))), - "r" ((uint8_t) ((value & 0x08 ? _WD_PS3_MASK : 0x00) | - _BV(WDIF) | _BV(WDIE) | (value & 0x07)) ) + : "I" ( _SFR_IO_ADDR( _WD_CONTROL_REG ) ), + "r" ( ( uint8_t ) ( _BV( _WD_CHANGE_BIT ) | _BV( WDE ) ) ), + "r" ( ( uint8_t ) ( ( value & 0x08 ? _WD_PS3_MASK : 0x00 ) | + _BV( WDIF ) | _BV( WDIE ) | ( value & 0x07 ) ) ) : "r0" - ); - } - else - { - __asm__ __volatile__ ( + ); + } + else + { + __asm__ __volatile__ ( "in __tmp_reg__,__SREG__" "\n\t" - "cli" "\n\t" - "wdr" "\n\t" - "sts %0, %1" "\n\t" - "out __SREG__,__tmp_reg__" "\n\t" - "sts %0, %2" "\n\t" + "cli" "\n\t" + "wdr" "\n\t" + "sts %0, %1" "\n\t" + "out __SREG__,__tmp_reg__" "\n\t" + "sts %0, %2" "\n\t" : /* no outputs */ - : "n" (_SFR_MEM_ADDR(_WD_CONTROL_REG)), - "r" ((uint8_t)(_BV(_WD_CHANGE_BIT) | _BV(WDE))), - "r" ((uint8_t) ((value & 0x08 ? _WD_PS3_MASK : 0x00) | - _BV(WDIF) | _BV(WDIE) | (value & 0x07)) ) + : "n" ( _SFR_MEM_ADDR( _WD_CONTROL_REG ) ), + "r" ( ( uint8_t ) ( _BV( _WD_CHANGE_BIT ) | _BV( WDE ) ) ), + "r" ( ( uint8_t ) ( ( value & 0x08 ? _WD_PS3_MASK : 0x00 ) | + _BV( WDIF ) | _BV( WDIE ) | ( value & 0x07 ) ) ) : "r0" - ); + ); + } } -} -#endif +#endif /* if defined( portUSE_WDTO ) */ /*-----------------------------------------------------------*/ -/** - Enable the watchdog timer, configuring it for expire after - (value) timeout (which is a combination of the WDP0 - through WDP3 bits). - - This function is derived from but enables both - the reset bit (WDE), and the interrupt bit (WDIE). - This will ensure that if the interrupt is not serviced - before the second timeout, the AVR will reset. - - Servicing the interrupt automatically clears it, - and ensures the AVR does not reset. - - Can't find it documented but the WDT, once enabled, - rolls over and fires a new interrupt each time. - - See also the symbolic constants WDTO_15MS et al. - - Updated to match avr-libc 2.0.0 -*/ +/** + * Enable the watchdog timer, configuring it for expire after + * (value) timeout (which is a combination of the WDP0 + * through WDP3 bits). + * + * This function is derived from but enables both + * the reset bit (WDE), and the interrupt bit (WDIE). + * + * This will ensure that if the interrupt is not serviced + * before the second timeout, the AVR will reset. + * + * Servicing the interrupt automatically clears it, + * and ensures the AVR does not reset. + * + * Can't find it documented but the WDT, once enabled, + * rolls over and fires a new interrupt each time. + * + * See also the symbolic constants WDTO_15MS et al. + * + * Updated to match avr-libc 2.0.0 + */ -#if defined( portUSE_WDTO) +#if defined( portUSE_WDTO ) -static __inline__ -__attribute__ ((__always_inline__)) -void wdt_interrupt_reset_enable (const uint8_t value) -{ - if (_SFR_IO_REG_P (_WD_CONTROL_REG)) + static __inline__ + __attribute__( ( __always_inline__ ) ) + void wdt_interrupt_reset_enable( const uint8_t value ) { - __asm__ __volatile__ ( + if( _SFR_IO_REG_P( _WD_CONTROL_REG ) ) + { + __asm__ __volatile__ ( "in __tmp_reg__,__SREG__" "\n\t" - "cli" "\n\t" - "wdr" "\n\t" - "out %0, %1" "\n\t" - "out __SREG__,__tmp_reg__" "\n\t" - "out %0, %2" "\n\t" + "cli" "\n\t" + "wdr" "\n\t" + "out %0, %1" "\n\t" + "out __SREG__,__tmp_reg__" "\n\t" + "out %0, %2" "\n\t" : /* no outputs */ - : "I" (_SFR_IO_ADDR(_WD_CONTROL_REG)), - "r" ((uint8_t)(_BV(_WD_CHANGE_BIT) | _BV(WDE))), - "r" ((uint8_t) ((value & 0x08 ? _WD_PS3_MASK : 0x00) | - _BV(WDIF) | _BV(WDIE) | _BV(WDE) | (value & 0x07)) ) + : "I" ( _SFR_IO_ADDR( _WD_CONTROL_REG ) ), + "r" ( ( uint8_t ) ( _BV( _WD_CHANGE_BIT ) | _BV( WDE ) ) ), + "r" ( ( uint8_t ) ( ( value & 0x08 ? _WD_PS3_MASK : 0x00 ) | + _BV( WDIF ) | _BV( WDIE ) | _BV( WDE ) | ( value & 0x07 ) ) ) : "r0" - ); - } - else - { - __asm__ __volatile__ ( + ); + } + else + { + __asm__ __volatile__ ( "in __tmp_reg__,__SREG__" "\n\t" - "cli" "\n\t" - "wdr" "\n\t" - "sts %0, %1" "\n\t" - "out __SREG__,__tmp_reg__" "\n\t" - "sts %0, %2" "\n\t" + "cli" "\n\t" + "wdr" "\n\t" + "sts %0, %1" "\n\t" + "out __SREG__,__tmp_reg__" "\n\t" + "sts %0, %2" "\n\t" : /* no outputs */ - : "n" (_SFR_MEM_ADDR(_WD_CONTROL_REG)), - "r" ((uint8_t)(_BV(_WD_CHANGE_BIT) | _BV(WDE))), - "r" ((uint8_t) ((value & 0x08 ? _WD_PS3_MASK : 0x00) | - _BV(WDIF) | _BV(WDIE) | _BV(WDE) | (value & 0x07)) ) + : "n" ( _SFR_MEM_ADDR( _WD_CONTROL_REG ) ), + "r" ( ( uint8_t ) ( _BV( _WD_CHANGE_BIT ) | _BV( WDE ) ) ), + "r" ( ( uint8_t ) ( ( value & 0x08 ? _WD_PS3_MASK : 0x00 ) | + _BV( WDIF ) | _BV( WDIE ) | _BV( WDE ) | ( value & 0x07 ) ) ) : "r0" - ); + ); + } } -} -#endif +#endif /* if defined( portUSE_WDTO ) */ /*-----------------------------------------------------------*/ @@ -226,295 +227,295 @@ void wdt_interrupt_reset_enable (const uint8_t value) * The interrupts will have been disabled during the call to portSAVE_CONTEXT() * so we need not worry about reading/writing to the stack pointer. */ -#if defined(__AVR_3_BYTE_PC__) && defined(__AVR_HAVE_RAMPZ__) +#if defined( __AVR_3_BYTE_PC__ ) && defined( __AVR_HAVE_RAMPZ__ ) /* 3-Byte PC Save with RAMPZ */ -#define portSAVE_CONTEXT() \ - __asm__ __volatile__ ( "push __tmp_reg__ \n\t" \ - "in __tmp_reg__, __SREG__ \n\t" \ - "cli \n\t" \ - "push __tmp_reg__ \n\t" \ - "in __tmp_reg__, 0x3B \n\t" \ - "push __tmp_reg__ \n\t" \ - "in __tmp_reg__, 0x3C \n\t" \ - "push __tmp_reg__ \n\t" \ - "push __zero_reg__ \n\t" \ - "clr __zero_reg__ \n\t" \ - "push r2 \n\t" \ - "push r3 \n\t" \ - "push r4 \n\t" \ - "push r5 \n\t" \ - "push r6 \n\t" \ - "push r7 \n\t" \ - "push r8 \n\t" \ - "push r9 \n\t" \ - "push r10 \n\t" \ - "push r11 \n\t" \ - "push r12 \n\t" \ - "push r13 \n\t" \ - "push r14 \n\t" \ - "push r15 \n\t" \ - "push r16 \n\t" \ - "push r17 \n\t" \ - "push r18 \n\t" \ - "push r19 \n\t" \ - "push r20 \n\t" \ - "push r21 \n\t" \ - "push r22 \n\t" \ - "push r23 \n\t" \ - "push r24 \n\t" \ - "push r25 \n\t" \ - "push r26 \n\t" \ - "push r27 \n\t" \ - "push r28 \n\t" \ - "push r29 \n\t" \ - "push r30 \n\t" \ - "push r31 \n\t" \ - "lds r26, pxCurrentTCB \n\t" \ - "lds r27, pxCurrentTCB + 1 \n\t" \ - "in __tmp_reg__, __SP_L__ \n\t" \ - "st x+, __tmp_reg__ \n\t" \ - "in __tmp_reg__, __SP_H__ \n\t" \ - "st x+, __tmp_reg__ \n\t" \ - ); -#elif defined(__AVR_HAVE_RAMPZ__) + #define portSAVE_CONTEXT() \ + __asm__ __volatile__ ( "push __tmp_reg__ \n\t" \ + "in __tmp_reg__, __SREG__ \n\t" \ + "cli \n\t" \ + "push __tmp_reg__ \n\t" \ + "in __tmp_reg__, 0x3B \n\t" \ + "push __tmp_reg__ \n\t" \ + "in __tmp_reg__, 0x3C \n\t" \ + "push __tmp_reg__ \n\t" \ + "push __zero_reg__ \n\t" \ + "clr __zero_reg__ \n\t" \ + "push r2 \n\t" \ + "push r3 \n\t" \ + "push r4 \n\t" \ + "push r5 \n\t" \ + "push r6 \n\t" \ + "push r7 \n\t" \ + "push r8 \n\t" \ + "push r9 \n\t" \ + "push r10 \n\t" \ + "push r11 \n\t" \ + "push r12 \n\t" \ + "push r13 \n\t" \ + "push r14 \n\t" \ + "push r15 \n\t" \ + "push r16 \n\t" \ + "push r17 \n\t" \ + "push r18 \n\t" \ + "push r19 \n\t" \ + "push r20 \n\t" \ + "push r21 \n\t" \ + "push r22 \n\t" \ + "push r23 \n\t" \ + "push r24 \n\t" \ + "push r25 \n\t" \ + "push r26 \n\t" \ + "push r27 \n\t" \ + "push r28 \n\t" \ + "push r29 \n\t" \ + "push r30 \n\t" \ + "push r31 \n\t" \ + "lds r26, pxCurrentTCB \n\t" \ + "lds r27, pxCurrentTCB + 1 \n\t" \ + "in __tmp_reg__, __SP_L__ \n\t" \ + "st x+, __tmp_reg__ \n\t" \ + "in __tmp_reg__, __SP_H__ \n\t" \ + "st x+, __tmp_reg__ \n\t" \ + ); +#elif defined( __AVR_HAVE_RAMPZ__ ) /* 2-Byte PC Save with RAMPZ */ -#define portSAVE_CONTEXT() \ - __asm__ __volatile__ ( "push __tmp_reg__ \n\t" \ - "in __tmp_reg__, __SREG__ \n\t" \ - "cli \n\t" \ - "push __tmp_reg__ \n\t" \ - "in __tmp_reg__, 0x3B \n\t" \ - "push __tmp_reg__ \n\t" \ - "push __zero_reg__ \n\t" \ - "clr __zero_reg__ \n\t" \ - "push r2 \n\t" \ - "push r3 \n\t" \ - "push r4 \n\t" \ - "push r5 \n\t" \ - "push r6 \n\t" \ - "push r7 \n\t" \ - "push r8 \n\t" \ - "push r9 \n\t" \ - "push r10 \n\t" \ - "push r11 \n\t" \ - "push r12 \n\t" \ - "push r13 \n\t" \ - "push r14 \n\t" \ - "push r15 \n\t" \ - "push r16 \n\t" \ - "push r17 \n\t" \ - "push r18 \n\t" \ - "push r19 \n\t" \ - "push r20 \n\t" \ - "push r21 \n\t" \ - "push r22 \n\t" \ - "push r23 \n\t" \ - "push r24 \n\t" \ - "push r25 \n\t" \ - "push r26 \n\t" \ - "push r27 \n\t" \ - "push r28 \n\t" \ - "push r29 \n\t" \ - "push r30 \n\t" \ - "push r31 \n\t" \ - "lds r26, pxCurrentTCB \n\t" \ - "lds r27, pxCurrentTCB + 1 \n\t" \ - "in __tmp_reg__, __SP_L__ \n\t" \ - "st x+, __tmp_reg__ \n\t" \ - "in __tmp_reg__, __SP_H__ \n\t" \ - "st x+, __tmp_reg__ \n\t" \ - ); -#else + #define portSAVE_CONTEXT() \ + __asm__ __volatile__ ( "push __tmp_reg__ \n\t" \ + "in __tmp_reg__, __SREG__ \n\t" \ + "cli \n\t" \ + "push __tmp_reg__ \n\t" \ + "in __tmp_reg__, 0x3B \n\t" \ + "push __tmp_reg__ \n\t" \ + "push __zero_reg__ \n\t" \ + "clr __zero_reg__ \n\t" \ + "push r2 \n\t" \ + "push r3 \n\t" \ + "push r4 \n\t" \ + "push r5 \n\t" \ + "push r6 \n\t" \ + "push r7 \n\t" \ + "push r8 \n\t" \ + "push r9 \n\t" \ + "push r10 \n\t" \ + "push r11 \n\t" \ + "push r12 \n\t" \ + "push r13 \n\t" \ + "push r14 \n\t" \ + "push r15 \n\t" \ + "push r16 \n\t" \ + "push r17 \n\t" \ + "push r18 \n\t" \ + "push r19 \n\t" \ + "push r20 \n\t" \ + "push r21 \n\t" \ + "push r22 \n\t" \ + "push r23 \n\t" \ + "push r24 \n\t" \ + "push r25 \n\t" \ + "push r26 \n\t" \ + "push r27 \n\t" \ + "push r28 \n\t" \ + "push r29 \n\t" \ + "push r30 \n\t" \ + "push r31 \n\t" \ + "lds r26, pxCurrentTCB \n\t" \ + "lds r27, pxCurrentTCB + 1 \n\t" \ + "in __tmp_reg__, __SP_L__ \n\t" \ + "st x+, __tmp_reg__ \n\t" \ + "in __tmp_reg__, __SP_H__ \n\t" \ + "st x+, __tmp_reg__ \n\t" \ + ); +#else /* if defined( __AVR_3_BYTE_PC__ ) && defined( __AVR_HAVE_RAMPZ__ ) */ /* 2-Byte PC Save */ -#define portSAVE_CONTEXT() \ - __asm__ __volatile__ ( "push __tmp_reg__ \n\t" \ - "in __tmp_reg__, __SREG__ \n\t" \ - "cli \n\t" \ - "push __tmp_reg__ \n\t" \ - "push __zero_reg__ \n\t" \ - "clr __zero_reg__ \n\t" \ - "push r2 \n\t" \ - "push r3 \n\t" \ - "push r4 \n\t" \ - "push r5 \n\t" \ - "push r6 \n\t" \ - "push r7 \n\t" \ - "push r8 \n\t" \ - "push r9 \n\t" \ - "push r10 \n\t" \ - "push r11 \n\t" \ - "push r12 \n\t" \ - "push r13 \n\t" \ - "push r14 \n\t" \ - "push r15 \n\t" \ - "push r16 \n\t" \ - "push r17 \n\t" \ - "push r18 \n\t" \ - "push r19 \n\t" \ - "push r20 \n\t" \ - "push r21 \n\t" \ - "push r22 \n\t" \ - "push r23 \n\t" \ - "push r24 \n\t" \ - "push r25 \n\t" \ - "push r26 \n\t" \ - "push r27 \n\t" \ - "push r28 \n\t" \ - "push r29 \n\t" \ - "push r30 \n\t" \ - "push r31 \n\t" \ - "lds r26, pxCurrentTCB \n\t" \ - "lds r27, pxCurrentTCB + 1 \n\t" \ - "in __tmp_reg__, __SP_L__ \n\t" \ - "st x+, __tmp_reg__ \n\t" \ - "in __tmp_reg__, __SP_H__ \n\t" \ - "st x+, __tmp_reg__ \n\t" \ - ); -#endif + #define portSAVE_CONTEXT() \ + __asm__ __volatile__ ( "push __tmp_reg__ \n\t" \ + "in __tmp_reg__, __SREG__ \n\t" \ + "cli \n\t" \ + "push __tmp_reg__ \n\t" \ + "push __zero_reg__ \n\t" \ + "clr __zero_reg__ \n\t" \ + "push r2 \n\t" \ + "push r3 \n\t" \ + "push r4 \n\t" \ + "push r5 \n\t" \ + "push r6 \n\t" \ + "push r7 \n\t" \ + "push r8 \n\t" \ + "push r9 \n\t" \ + "push r10 \n\t" \ + "push r11 \n\t" \ + "push r12 \n\t" \ + "push r13 \n\t" \ + "push r14 \n\t" \ + "push r15 \n\t" \ + "push r16 \n\t" \ + "push r17 \n\t" \ + "push r18 \n\t" \ + "push r19 \n\t" \ + "push r20 \n\t" \ + "push r21 \n\t" \ + "push r22 \n\t" \ + "push r23 \n\t" \ + "push r24 \n\t" \ + "push r25 \n\t" \ + "push r26 \n\t" \ + "push r27 \n\t" \ + "push r28 \n\t" \ + "push r29 \n\t" \ + "push r30 \n\t" \ + "push r31 \n\t" \ + "lds r26, pxCurrentTCB \n\t" \ + "lds r27, pxCurrentTCB + 1 \n\t" \ + "in __tmp_reg__, __SP_L__ \n\t" \ + "st x+, __tmp_reg__ \n\t" \ + "in __tmp_reg__, __SP_H__ \n\t" \ + "st x+, __tmp_reg__ \n\t" \ + ); +#endif /* if defined( __AVR_3_BYTE_PC__ ) && defined( __AVR_HAVE_RAMPZ__ ) */ /* * Opposite to portSAVE_CONTEXT(). Interrupts will have been disabled during * the context save so we can write to the stack pointer. */ -#if defined(__AVR_3_BYTE_PC__) && defined(__AVR_HAVE_RAMPZ__) +#if defined( __AVR_3_BYTE_PC__ ) && defined( __AVR_HAVE_RAMPZ__ ) /* 3-Byte PC Restore with RAMPZ */ -#define portRESTORE_CONTEXT() \ - __asm__ __volatile__ ( "lds r26, pxCurrentTCB \n\t" \ - "lds r27, pxCurrentTCB + 1 \n\t" \ - "ld r28, x+ \n\t" \ - "out __SP_L__, r28 \n\t" \ - "ld r29, x+ \n\t" \ - "out __SP_H__, r29 \n\t" \ - "pop r31 \n\t" \ - "pop r30 \n\t" \ - "pop r29 \n\t" \ - "pop r28 \n\t" \ - "pop r27 \n\t" \ - "pop r26 \n\t" \ - "pop r25 \n\t" \ - "pop r24 \n\t" \ - "pop r23 \n\t" \ - "pop r22 \n\t" \ - "pop r21 \n\t" \ - "pop r20 \n\t" \ - "pop r19 \n\t" \ - "pop r18 \n\t" \ - "pop r17 \n\t" \ - "pop r16 \n\t" \ - "pop r15 \n\t" \ - "pop r14 \n\t" \ - "pop r13 \n\t" \ - "pop r12 \n\t" \ - "pop r11 \n\t" \ - "pop r10 \n\t" \ - "pop r9 \n\t" \ - "pop r8 \n\t" \ - "pop r7 \n\t" \ - "pop r6 \n\t" \ - "pop r5 \n\t" \ - "pop r4 \n\t" \ - "pop r3 \n\t" \ - "pop r2 \n\t" \ - "pop __zero_reg__ \n\t" \ - "pop __tmp_reg__ \n\t" \ - "out 0x3C, __tmp_reg__ \n\t" \ - "pop __tmp_reg__ \n\t" \ - "out 0x3B, __tmp_reg__ \n\t" \ - "pop __tmp_reg__ \n\t" \ - "out __SREG__, __tmp_reg__ \n\t" \ - "pop __tmp_reg__ \n\t" \ - ); -#elif defined(__AVR_HAVE_RAMPZ__) + #define portRESTORE_CONTEXT() \ + __asm__ __volatile__ ( "lds r26, pxCurrentTCB \n\t" \ + "lds r27, pxCurrentTCB + 1 \n\t" \ + "ld r28, x+ \n\t" \ + "out __SP_L__, r28 \n\t" \ + "ld r29, x+ \n\t" \ + "out __SP_H__, r29 \n\t" \ + "pop r31 \n\t" \ + "pop r30 \n\t" \ + "pop r29 \n\t" \ + "pop r28 \n\t" \ + "pop r27 \n\t" \ + "pop r26 \n\t" \ + "pop r25 \n\t" \ + "pop r24 \n\t" \ + "pop r23 \n\t" \ + "pop r22 \n\t" \ + "pop r21 \n\t" \ + "pop r20 \n\t" \ + "pop r19 \n\t" \ + "pop r18 \n\t" \ + "pop r17 \n\t" \ + "pop r16 \n\t" \ + "pop r15 \n\t" \ + "pop r14 \n\t" \ + "pop r13 \n\t" \ + "pop r12 \n\t" \ + "pop r11 \n\t" \ + "pop r10 \n\t" \ + "pop r9 \n\t" \ + "pop r8 \n\t" \ + "pop r7 \n\t" \ + "pop r6 \n\t" \ + "pop r5 \n\t" \ + "pop r4 \n\t" \ + "pop r3 \n\t" \ + "pop r2 \n\t" \ + "pop __zero_reg__ \n\t" \ + "pop __tmp_reg__ \n\t" \ + "out 0x3C, __tmp_reg__ \n\t" \ + "pop __tmp_reg__ \n\t" \ + "out 0x3B, __tmp_reg__ \n\t" \ + "pop __tmp_reg__ \n\t" \ + "out __SREG__, __tmp_reg__ \n\t" \ + "pop __tmp_reg__ \n\t" \ + ); +#elif defined( __AVR_HAVE_RAMPZ__ ) /* 2-Byte PC Restore with RAMPZ */ -#define portRESTORE_CONTEXT() \ - __asm__ __volatile__ ( "lds r26, pxCurrentTCB \n\t" \ - "lds r27, pxCurrentTCB + 1 \n\t" \ - "ld r28, x+ \n\t" \ - "out __SP_L__, r28 \n\t" \ - "ld r29, x+ \n\t" \ - "out __SP_H__, r29 \n\t" \ - "pop r31 \n\t" \ - "pop r30 \n\t" \ - "pop r29 \n\t" \ - "pop r28 \n\t" \ - "pop r27 \n\t" \ - "pop r26 \n\t" \ - "pop r25 \n\t" \ - "pop r24 \n\t" \ - "pop r23 \n\t" \ - "pop r22 \n\t" \ - "pop r21 \n\t" \ - "pop r20 \n\t" \ - "pop r19 \n\t" \ - "pop r18 \n\t" \ - "pop r17 \n\t" \ - "pop r16 \n\t" \ - "pop r15 \n\t" \ - "pop r14 \n\t" \ - "pop r13 \n\t" \ - "pop r12 \n\t" \ - "pop r11 \n\t" \ - "pop r10 \n\t" \ - "pop r9 \n\t" \ - "pop r8 \n\t" \ - "pop r7 \n\t" \ - "pop r6 \n\t" \ - "pop r5 \n\t" \ - "pop r4 \n\t" \ - "pop r3 \n\t" \ - "pop r2 \n\t" \ - "pop __zero_reg__ \n\t" \ - "pop __tmp_reg__ \n\t" \ - "out 0x3B, __tmp_reg__ \n\t" \ - "pop __tmp_reg__ \n\t" \ - "out __SREG__, __tmp_reg__ \n\t" \ - "pop __tmp_reg__ \n\t" \ - ); -#else + #define portRESTORE_CONTEXT() \ + __asm__ __volatile__ ( "lds r26, pxCurrentTCB \n\t" \ + "lds r27, pxCurrentTCB + 1 \n\t" \ + "ld r28, x+ \n\t" \ + "out __SP_L__, r28 \n\t" \ + "ld r29, x+ \n\t" \ + "out __SP_H__, r29 \n\t" \ + "pop r31 \n\t" \ + "pop r30 \n\t" \ + "pop r29 \n\t" \ + "pop r28 \n\t" \ + "pop r27 \n\t" \ + "pop r26 \n\t" \ + "pop r25 \n\t" \ + "pop r24 \n\t" \ + "pop r23 \n\t" \ + "pop r22 \n\t" \ + "pop r21 \n\t" \ + "pop r20 \n\t" \ + "pop r19 \n\t" \ + "pop r18 \n\t" \ + "pop r17 \n\t" \ + "pop r16 \n\t" \ + "pop r15 \n\t" \ + "pop r14 \n\t" \ + "pop r13 \n\t" \ + "pop r12 \n\t" \ + "pop r11 \n\t" \ + "pop r10 \n\t" \ + "pop r9 \n\t" \ + "pop r8 \n\t" \ + "pop r7 \n\t" \ + "pop r6 \n\t" \ + "pop r5 \n\t" \ + "pop r4 \n\t" \ + "pop r3 \n\t" \ + "pop r2 \n\t" \ + "pop __zero_reg__ \n\t" \ + "pop __tmp_reg__ \n\t" \ + "out 0x3B, __tmp_reg__ \n\t" \ + "pop __tmp_reg__ \n\t" \ + "out __SREG__, __tmp_reg__ \n\t" \ + "pop __tmp_reg__ \n\t" \ + ); +#else /* if defined( __AVR_3_BYTE_PC__ ) && defined( __AVR_HAVE_RAMPZ__ ) */ /* 2-Byte PC Restore */ -#define portRESTORE_CONTEXT() \ - __asm__ __volatile__ ( "lds r26, pxCurrentTCB \n\t" \ - "lds r27, pxCurrentTCB + 1 \n\t" \ - "ld r28, x+ \n\t" \ - "out __SP_L__, r28 \n\t" \ - "ld r29, x+ \n\t" \ - "out __SP_H__, r29 \n\t" \ - "pop r31 \n\t" \ - "pop r30 \n\t" \ - "pop r29 \n\t" \ - "pop r28 \n\t" \ - "pop r27 \n\t" \ - "pop r26 \n\t" \ - "pop r25 \n\t" \ - "pop r24 \n\t" \ - "pop r23 \n\t" \ - "pop r22 \n\t" \ - "pop r21 \n\t" \ - "pop r20 \n\t" \ - "pop r19 \n\t" \ - "pop r18 \n\t" \ - "pop r17 \n\t" \ - "pop r16 \n\t" \ - "pop r15 \n\t" \ - "pop r14 \n\t" \ - "pop r13 \n\t" \ - "pop r12 \n\t" \ - "pop r11 \n\t" \ - "pop r10 \n\t" \ - "pop r9 \n\t" \ - "pop r8 \n\t" \ - "pop r7 \n\t" \ - "pop r6 \n\t" \ - "pop r5 \n\t" \ - "pop r4 \n\t" \ - "pop r3 \n\t" \ - "pop r2 \n\t" \ - "pop __zero_reg__ \n\t" \ - "pop __tmp_reg__ \n\t" \ - "out __SREG__, __tmp_reg__ \n\t" \ - "pop __tmp_reg__ \n\t" \ - ); -#endif + #define portRESTORE_CONTEXT() \ + __asm__ __volatile__ ( "lds r26, pxCurrentTCB \n\t" \ + "lds r27, pxCurrentTCB + 1 \n\t" \ + "ld r28, x+ \n\t" \ + "out __SP_L__, r28 \n\t" \ + "ld r29, x+ \n\t" \ + "out __SP_H__, r29 \n\t" \ + "pop r31 \n\t" \ + "pop r30 \n\t" \ + "pop r29 \n\t" \ + "pop r28 \n\t" \ + "pop r27 \n\t" \ + "pop r26 \n\t" \ + "pop r25 \n\t" \ + "pop r24 \n\t" \ + "pop r23 \n\t" \ + "pop r22 \n\t" \ + "pop r21 \n\t" \ + "pop r20 \n\t" \ + "pop r19 \n\t" \ + "pop r18 \n\t" \ + "pop r17 \n\t" \ + "pop r16 \n\t" \ + "pop r15 \n\t" \ + "pop r14 \n\t" \ + "pop r13 \n\t" \ + "pop r12 \n\t" \ + "pop r11 \n\t" \ + "pop r10 \n\t" \ + "pop r9 \n\t" \ + "pop r8 \n\t" \ + "pop r7 \n\t" \ + "pop r6 \n\t" \ + "pop r5 \n\t" \ + "pop r4 \n\t" \ + "pop r3 \n\t" \ + "pop r2 \n\t" \ + "pop __zero_reg__ \n\t" \ + "pop __tmp_reg__ \n\t" \ + "out __SREG__, __tmp_reg__ \n\t" \ + "pop __tmp_reg__ \n\t" \ + ); +#endif /* if defined( __AVR_3_BYTE_PC__ ) && defined( __AVR_HAVE_RAMPZ__ ) */ /*-----------------------------------------------------------*/ /* @@ -526,14 +527,17 @@ static void prvSetupTimerInterrupt( void ); /* * See header file for description. */ -StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters ) +StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, + TaskFunction_t pxCode, + void * pvParameters ) { -uint16_t usAddress; + uint16_t usAddress; + /* Simulate how the stack would look after a call to vPortYield() generated by - the compiler. */ + * the compiler. */ /* The start of the task code will be popped off the stack last, so place - it on first. */ + * it on first. */ usAddress = ( uint16_t ) pxCode; *pxTopOfStack = ( StackType_t ) ( usAddress & ( uint16_t ) 0x00ff ); pxTopOfStack--; @@ -542,48 +546,51 @@ uint16_t usAddress; *pxTopOfStack = ( StackType_t ) ( usAddress & ( uint16_t ) 0x00ff ); pxTopOfStack--; -#if defined(__AVR_3_BYTE_PC__) - /* The AVR ATmega2560/ATmega2561 have 256KBytes of program memory and a 17-bit - * program counter. When a code address is stored on the stack, it takes 3 bytes - * instead of 2 for the other ATmega* chips. - * - * Store 0 as the top byte since we force all task routines to the bottom 128K - * of flash. We do this by using the .lowtext label in the linker script. - * - * In order to do this properly, we would need to get a full 3-byte pointer to - * pxCode. That requires a change to GCC. Not likely to happen any time soon. - */ - *pxTopOfStack = 0; - pxTopOfStack--; -#endif + #if defined( __AVR_3_BYTE_PC__ ) + + /* The AVR ATmega2560/ATmega2561 have 256KBytes of program memory and a 17-bit + * program counter. When a code address is stored on the stack, it takes 3 bytes + * instead of 2 for the other ATmega* chips. + * + * Store 0 as the top byte since we force all task routines to the bottom 128K + * of flash. We do this by using the .lowtext label in the linker script. + * + * In order to do this properly, we would need to get a full 3-byte pointer to + * pxCode. That requires a change to GCC. Not likely to happen any time soon. + */ + *pxTopOfStack = 0; + pxTopOfStack--; + #endif /* Next simulate the stack as if after a call to portSAVE_CONTEXT(). - portSAVE_CONTEXT places the flags on the stack immediately after r0 - to ensure the interrupts get disabled as soon as possible, and so ensuring - the stack use is minimal should a context switch interrupt occur. */ - *pxTopOfStack = ( StackType_t ) 0x00; /* R0 */ + * portSAVE_CONTEXT places the flags on the stack immediately after r0 + * to ensure the interrupts get disabled as soon as possible, and so ensuring + * the stack use is minimal should a context switch interrupt occur. */ + *pxTopOfStack = ( StackType_t ) 0x00; /* R0 */ pxTopOfStack--; *pxTopOfStack = portFLAGS_INT_ENABLED; pxTopOfStack--; -#if defined(__AVR_3_BYTE_PC__) - /* If we have an ATmega256x, we are also saving the EIND register. - * We should default to 0. - */ - *pxTopOfStack = ( StackType_t ) 0x00; /* EIND */ - pxTopOfStack--; -#endif + #if defined( __AVR_3_BYTE_PC__ ) -#if defined(__AVR_HAVE_RAMPZ__) - /* We are saving the RAMPZ register. - * We should default to 0. - */ - *pxTopOfStack = ( StackType_t ) 0x00; /* RAMPZ */ - pxTopOfStack--; -#endif + /* If we have an ATmega256x, we are also saving the EIND register. + * We should default to 0. + */ + *pxTopOfStack = ( StackType_t ) 0x00; /* EIND */ + pxTopOfStack--; + #endif + + #if defined( __AVR_HAVE_RAMPZ__ ) + + /* We are saving the RAMPZ register. + * We should default to 0. + */ + *pxTopOfStack = ( StackType_t ) 0x00; /* RAMPZ */ + pxTopOfStack--; + #endif /* Now the remaining registers. The compiler expects R1 to be 0. */ - *pxTopOfStack = ( StackType_t ) 0x00; /* R1 */ + *pxTopOfStack = ( StackType_t ) 0x00; /* R1 */ /* Leave R2 - R23 untouched */ pxTopOfStack -= 23; @@ -612,7 +619,7 @@ BaseType_t xPortStartScheduler( void ) portRESTORE_CONTEXT(); /* Simulate a function call end as generated by the compiler. We will now - jump to the start of the task the context of which we have just restored. */ + * jump to the start of the task the context of which we have just restored. */ __asm__ __volatile__ ( "ret" ); /* Should not get here. */ @@ -630,7 +637,7 @@ void vPortEndScheduler( void ) * Manual context switch. The first thing we do is save the registers so we * can use a naked attribute. */ -void vPortYield( void ) __attribute__ ( ( hot, flatten, naked ) ); +void vPortYield( void ) __attribute__( ( hot, flatten, naked ) ); void vPortYield( void ) { portSAVE_CONTEXT(); @@ -645,8 +652,8 @@ void vPortYield( void ) * Manual context switch callable from ISRs. The first thing we do is save * the registers so we can use a naked attribute. */ -void vPortYieldFromISR(void) __attribute__ ( ( hot, flatten, naked ) ); -void vPortYieldFromISR(void) +void vPortYieldFromISR( void ) __attribute__( ( hot, flatten, naked ) ); +void vPortYieldFromISR( void ) { portSAVE_CONTEXT(); vTaskSwitchContext(); @@ -662,105 +669,111 @@ void vPortYieldFromISR(void) * difference from vPortYield() is the tick count is incremented as the * call comes from the tick ISR. */ -void vPortYieldFromTick( void ) __attribute__ ( ( hot, flatten, naked ) ); +void vPortYieldFromTick( void ) __attribute__( ( hot, flatten, naked ) ); void vPortYieldFromTick( void ) { portSAVE_CONTEXT(); + if( xTaskIncrementTick() != pdFALSE ) { vTaskSwitchContext(); } + portRESTORE_CONTEXT(); __asm__ __volatile__ ( "ret" ); } /*-----------------------------------------------------------*/ -#if defined(portUSE_WDTO) +#if defined( portUSE_WDTO ) + /* * Setup WDT to generate a tick interrupt. */ -void prvSetupTimerInterrupt( void ) -{ - /* reset watchdog */ - wdt_reset(); + void prvSetupTimerInterrupt( void ) + { + /* reset watchdog */ + wdt_reset(); - /* set up WDT Interrupt (rather than the WDT Reset). */ - wdt_interrupt_enable( portUSE_WDTO ); -} + /* set up WDT Interrupt (rather than the WDT Reset). */ + wdt_interrupt_enable( portUSE_WDTO ); + } + +#elif defined( portUSE_TIMER0 ) -#elif defined (portUSE_TIMER0) /* * Setup Timer0 compare match A to generate a tick interrupt. */ -static void prvSetupTimerInterrupt( void ) -{ -uint32_t ulCompareMatch; -uint8_t ucLowByte; + static void prvSetupTimerInterrupt( void ) + { + uint32_t ulCompareMatch; + uint8_t ucLowByte; - /* Using 8bit Timer0 to generate the tick. Correct fuses must be - selected for the configCPU_CLOCK_HZ clock.*/ + /* Using 8bit Timer0 to generate the tick. Correct fuses must be + * selected for the configCPU_CLOCK_HZ clock.*/ - ulCompareMatch = configCPU_CLOCK_HZ / configTICK_RATE_HZ; + ulCompareMatch = configCPU_CLOCK_HZ / configTICK_RATE_HZ; - /* We only have 8 bits so have to scale 1024 to get our required tick rate. */ - ulCompareMatch /= portCLOCK_PRESCALER; + /* We only have 8 bits so have to scale 1024 to get our required tick rate. */ + ulCompareMatch /= portCLOCK_PRESCALER; - /* Adjust for correct value. */ - ulCompareMatch -= ( uint32_t ) 1; + /* Adjust for correct value. */ + ulCompareMatch -= ( uint32_t ) 1; - /* Setup compare match value for compare match A. Interrupts are disabled - before this is called so we need not worry here. */ - ucLowByte = ( uint8_t ) ( ulCompareMatch & ( uint32_t ) 0xff ); - portOCRL = ucLowByte; + /* Setup compare match value for compare match A. Interrupts are disabled + * before this is called so we need not worry here. */ + ucLowByte = ( uint8_t ) ( ulCompareMatch & ( uint32_t ) 0xff ); + portOCRL = ucLowByte; - /* Setup clock source and compare match behaviour. */ - portTCCRa = portCLEAR_COUNTER_ON_MATCH; - portTCCRb = portPRESCALE_1024; + /* Setup clock source and compare match behaviour. */ + portTCCRa = portCLEAR_COUNTER_ON_MATCH; + portTCCRb = portPRESCALE_1024; - /* Enable the interrupt - this is okay as interrupt are currently globally disabled. */ - ucLowByte = portTIMSK; - ucLowByte |= portCOMPARE_MATCH_A_INTERRUPT_ENABLE; - portTIMSK = ucLowByte; -} + /* Enable the interrupt - this is okay as interrupt are currently globally disabled. */ + ucLowByte = portTIMSK; + ucLowByte |= portCOMPARE_MATCH_A_INTERRUPT_ENABLE; + portTIMSK = ucLowByte; + } -#endif +#endif /* if defined( portUSE_WDTO ) */ /*-----------------------------------------------------------*/ #if configUSE_PREEMPTION == 1 - /* - * Tick ISR for preemptive scheduler. We can use a naked attribute as - * the context is saved at the start of vPortYieldFromTick(). The tick - * count is incremented after the context is saved. - * - * use ISR_NOBLOCK where there is an important timer running, that should preempt the scheduler. - * - */ - ISR(portSCHEDULER_ISR, ISR_NAKED) __attribute__ ((hot, flatten)); +/* + * Tick ISR for preemptive scheduler. We can use a naked attribute as + * the context is saved at the start of vPortYieldFromTick(). The tick + * count is incremented after the context is saved. + * + * use ISR_NOBLOCK where there is an important timer running, that should preempt the scheduler. + * + */ + ISR( portSCHEDULER_ISR, ISR_NAKED ) __attribute__( ( hot, flatten ) ); + /* ISR(portSCHEDULER_ISR, ISR_NAKED ISR_NOBLOCK) __attribute__ ((hot, flatten)); */ - ISR(portSCHEDULER_ISR) + ISR( portSCHEDULER_ISR ) { vPortYieldFromTick(); __asm__ __volatile__ ( "reti" ); } -#else - - /* - * Tick ISR for the cooperative scheduler. All this does is increment the - * tick count. We don't need to switch context, this can only be done by - * manual calls to taskYIELD(); - * - * use ISR_NOBLOCK where there is an important timer running, that should preempt the scheduler. - */ - ISR(portSCHEDULER_ISR) __attribute__ ((hot, flatten)); +#else /* if configUSE_PREEMPTION == 1 */ + +/* + * Tick ISR for the cooperative scheduler. All this does is increment the + * tick count. We don't need to switch context, this can only be done by + * manual calls to taskYIELD(); + * + * use ISR_NOBLOCK where there is an important timer running, that should preempt the scheduler. + */ + ISR( portSCHEDULER_ISR ) __attribute__( ( hot, flatten ) ); + /* ISR(portSCHEDULER_ISR, ISR_NOBLOCK) __attribute__ ((hot, flatten)); */ - ISR(portSCHEDULER_ISR) + ISR( portSCHEDULER_ISR ) { xTaskIncrementTick(); } -#endif +#endif /* if configUSE_PREEMPTION == 1 */ diff --git a/Source/portable/ThirdParty/GCC/ATmega/portmacro.h b/Source/portable/ThirdParty/GCC/ATmega/portmacro.h index 6e7e795cd..d6d22c6b0 100644 --- a/Source/portable/ThirdParty/GCC/ATmega/portmacro.h +++ b/Source/portable/ThirdParty/GCC/ATmega/portmacro.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -24,7 +24,7 @@ * https://www.FreeRTOS.org * https://github.com/FreeRTOS * -*/ + */ #ifndef PORTMACRO_H #define PORTMACRO_H @@ -48,23 +48,23 @@ #include /* Type definitions. */ -#define portCHAR char -#define portFLOAT float -#define portDOUBLE double -#define portLONG long -#define portSHORT int +#define portCHAR char +#define portFLOAT float +#define portDOUBLE double +#define portLONG long +#define portSHORT int #define portPOINTER_SIZE_TYPE uint16_t -typedef uint8_t StackType_t; -typedef int8_t BaseType_t; -typedef uint8_t UBaseType_t; +typedef uint8_t StackType_t; +typedef int8_t BaseType_t; +typedef uint8_t UBaseType_t; #if configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS - typedef uint16_t TickType_t; - #define portMAX_DELAY ( TickType_t ) 0xffff -#elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS ) - typedef uint32_t TickType_t; + typedef uint16_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffff +#elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS ) + typedef uint32_t TickType_t; #define portMAX_DELAY ( TickType_t ) 0xffffffffUL #else #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width. @@ -73,23 +73,25 @@ typedef uint8_t UBaseType_t; /* Critical section management. */ -#define portENTER_CRITICAL() __asm__ __volatile__ ( \ - "in __tmp_reg__, __SREG__" "\n\t" \ - "cli" "\n\t" \ - "push __tmp_reg__" "\n\t" \ - ::: "memory" \ - ) +#define portENTER_CRITICAL() \ + __asm__ __volatile__ ( \ + "in __tmp_reg__, __SREG__" "\n\t" \ + "cli" "\n\t" \ + "push __tmp_reg__" "\n\t" \ + ::: "memory" \ + ) -#define portEXIT_CRITICAL() __asm__ __volatile__ ( \ - "pop __tmp_reg__" "\n\t" \ - "out __SREG__, __tmp_reg__" "\n\t" \ - ::: "memory" \ - ) +#define portEXIT_CRITICAL() \ + __asm__ __volatile__ ( \ + "pop __tmp_reg__" "\n\t" \ + "out __SREG__, __tmp_reg__" "\n\t" \ + ::: "memory" \ + ) -#define portDISABLE_INTERRUPTS() __asm__ __volatile__ ( "cli" ::: "memory") -#define portENABLE_INTERRUPTS() __asm__ __volatile__ ( "sei" ::: "memory") +#define portDISABLE_INTERRUPTS() __asm__ __volatile__ ( "cli" ::: "memory" ) +#define portENABLE_INTERRUPTS() __asm__ __volatile__ ( "sei" ::: "memory" ) /*-----------------------------------------------------------*/ /* Architecture specifics. */ @@ -98,27 +100,27 @@ typedef uint8_t UBaseType_t; * Prefer to use the enhanced Watchdog Timer, but also Timer0 is ok. */ -#if defined(WDIE) && defined(WDIF) /* If Enhanced WDT with interrupt capability is available */ +#if defined( WDIE ) && defined( WDIF ) /* If Enhanced WDT with interrupt capability is available */ -#define portUSE_WDTO WDTO_15MS /* use the Watchdog Timer for xTaskIncrementTick */ + #define portUSE_WDTO WDTO_15MS /* use the Watchdog Timer for xTaskIncrementTick */ /* Watchdog period options: WDTO_15MS - WDTO_30MS - WDTO_60MS - WDTO_120MS - WDTO_250MS - WDTO_500MS - WDTO_1S - WDTO_2S -*/ + * WDTO_30MS + * WDTO_60MS + * WDTO_120MS + * WDTO_250MS + * WDTO_500MS + * WDTO_1S + * WDTO_2S + */ #else -#define portUSE_TIMER0 /* use the 8-bit Timer0 for xTaskIncrementTick */ + #define portUSE_TIMER0 /* use the 8-bit Timer0 for xTaskIncrementTick */ #endif -#define portSTACK_GROWTH ( -1 ) +#define portSTACK_GROWTH ( -1 ) /* Timing for the scheduler. * Watchdog Timer is 128kHz nominal, @@ -126,35 +128,35 @@ typedef uint8_t UBaseType_t; * from data sheet. */ #if defined( portUSE_WDTO ) -#define portTICK_PERIOD_MS ( (TickType_t) _BV( portUSE_WDTO + 4 ) ) + #define portTICK_PERIOD_MS ( ( TickType_t ) _BV( portUSE_WDTO + 4 ) ) #else -#define portTICK_PERIOD_MS ( (TickType_t) 1000 / configTICK_RATE_HZ ) + #define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) #endif -#define portBYTE_ALIGNMENT 1 -#define portNOP() __asm__ __volatile__ ( "nop" ); +#define portBYTE_ALIGNMENT 1 +#define portNOP() __asm__ __volatile__ ( "nop" ); /*-----------------------------------------------------------*/ /* Kernel utilities. */ -extern void vPortYield( void ) __attribute__ ( ( naked ) ); -#define portYIELD() vPortYield() +extern void vPortYield( void ) __attribute__( ( naked ) ); +#define portYIELD() vPortYield() -extern void vPortYieldFromISR( void ) __attribute__ ( ( naked ) ); -#define portYIELD_FROM_ISR() vPortYieldFromISR() +extern void vPortYieldFromISR( void ) __attribute__( ( naked ) ); +#define portYIELD_FROM_ISR() vPortYieldFromISR() /*-----------------------------------------------------------*/ -#if defined(__AVR_3_BYTE_PC__) +#if defined( __AVR_3_BYTE_PC__ ) /* Task function macros as described on the FreeRTOS.org WEB site. */ /* Add .lowtext tag from the avr linker script avr6.x for ATmega2560 and ATmega2561 * to make sure functions are loaded in low memory. */ -#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters ) __attribute__ ((section (".lowtext"))) + #define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters ) __attribute__( ( section( ".lowtext" ) ) ) #else -#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters ) + #define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters ) #endif -#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters ) +#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters ) /* *INDENT-OFF* */ #ifdef __cplusplus diff --git a/Source/portable/ThirdParty/GCC/Posix/port.c b/Source/portable/ThirdParty/GCC/Posix/port.c index d3b3fecf8..9ec0e2df9 100644 --- a/Source/portable/ThirdParty/GCC/Posix/port.c +++ b/Source/portable/ThirdParty/GCC/Posix/port.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2020 Cambridge Consultants Ltd. * * SPDX-License-Identifier: MIT @@ -100,10 +100,10 @@ static pthread_once_t hSigSetupThread = PTHREAD_ONCE_INIT; static sigset_t xAllSignals; static sigset_t xSchedulerOriginalSignalMask; static pthread_t hMainThread = ( pthread_t ) NULL; -static volatile portBASE_TYPE uxCriticalNesting; +static volatile BaseType_t uxCriticalNesting; /*-----------------------------------------------------------*/ -static portBASE_TYPE xSchedulerEnd = pdFALSE; +static BaseType_t xSchedulerEnd = pdFALSE; /*-----------------------------------------------------------*/ static void prvSetupSignalsAndSchedulerPolicy( void ); @@ -119,10 +119,10 @@ static void prvPortYieldFromISR( void ); /*-----------------------------------------------------------*/ static void prvFatalError( const char * pcCall, - int iErrno ) __attribute__ ((__noreturn__)); + int iErrno ) __attribute__( ( __noreturn__ ) ); void prvFatalError( const char * pcCall, - int iErrno ) + int iErrno ) { fprintf( stderr, "%s: %s\n", pcCall, strerror( iErrno ) ); abort(); @@ -131,10 +131,10 @@ void prvFatalError( const char * pcCall, /* * See header file for description. */ -portSTACK_TYPE * pxPortInitialiseStack( StackType_t * pxTopOfStack, - StackType_t * pxEndOfStack, - TaskFunction_t pxCode, - void * pvParameters ) +StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, + StackType_t * pxEndOfStack, + TaskFunction_t pxCode, + void * pvParameters ) { Thread_t * thread; pthread_attr_t xThreadAttributes; @@ -147,12 +147,16 @@ portSTACK_TYPE * pxPortInitialiseStack( StackType_t * pxTopOfStack, * Store the additional thread data at the start of the stack. */ thread = ( Thread_t * ) ( pxTopOfStack + 1 ) - 1; - pxTopOfStack = ( portSTACK_TYPE * ) thread - 1; - ulStackSize = ( size_t )( pxTopOfStack + 1 - pxEndOfStack ) * sizeof( *pxTopOfStack ); + pxTopOfStack = ( StackType_t * ) thread - 1; #ifdef __APPLE__ - pxEndOfStack = mach_vm_round_page ( pxEndOfStack ); - ulStackSize = mach_vm_trunc_page ( ulStackSize ); + pxEndOfStack = ( StackType_t * ) mach_vm_round_page( pxEndOfStack ); + #endif + + ulStackSize = ( size_t ) ( pxTopOfStack + 1 - pxEndOfStack ) * sizeof( *pxTopOfStack ); + + #ifdef __APPLE__ + ulStackSize = mach_vm_trunc_page( ulStackSize ); #endif thread->pxCode = pxCode; @@ -161,6 +165,7 @@ portSTACK_TYPE * pxPortInitialiseStack( StackType_t * pxTopOfStack, pthread_attr_init( &xThreadAttributes ); iRet = pthread_attr_setstack( &xThreadAttributes, pxEndOfStack, ulStackSize ); + if( iRet != 0 ) { fprintf( stderr, "[WARN] pthread_attr_setstack failed with return value: %d. Default stack will be used.\n", iRet ); @@ -197,7 +202,7 @@ void vPortStartFirstTask( void ) /* * See header file for description. */ -portBASE_TYPE xPortStartScheduler( void ) +BaseType_t xPortStartScheduler( void ) { int iSignal; sigset_t xSignals; @@ -336,7 +341,7 @@ UBaseType_t xPortSetInterruptMask( void ) { /* Interrupts are always disabled inside ISRs (signals * handlers). */ - return ( UBaseType_t )0; + return ( UBaseType_t ) 0; } /*-----------------------------------------------------------*/ @@ -352,7 +357,7 @@ static uint64_t prvGetTimeNs( void ) clock_gettime( CLOCK_MONOTONIC, &t ); - return ( uint64_t )t.tv_sec * ( uint64_t )1000000000UL + ( uint64_t )t.tv_nsec; + return ( uint64_t ) t.tv_sec * ( uint64_t ) 1000000000UL + ( uint64_t ) t.tv_nsec; } static uint64_t prvStartTimeNs; @@ -584,12 +589,12 @@ static void prvSetupSignalsAndSchedulerPolicy( void ) } /*-----------------------------------------------------------*/ -unsigned long ulPortGetRunTime( void ) +uint32_t ulPortGetRunTime( void ) { struct tms xTimes; times( &xTimes ); - return ( unsigned long ) xTimes.tms_utime; + return ( uint32_t ) xTimes.tms_utime; } /*-----------------------------------------------------------*/ diff --git a/Source/portable/ThirdParty/GCC/Posix/portmacro.h b/Source/portable/ThirdParty/GCC/Posix/portmacro.h index 27ba82de2..cc9453bf7 100644 --- a/Source/portable/ThirdParty/GCC/Posix/portmacro.h +++ b/Source/portable/ThirdParty/GCC/Posix/portmacro.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright 2020 Cambridge Consultants Ltd. * * SPDX-License-Identifier: MIT @@ -37,6 +37,7 @@ /* *INDENT-ON* */ #include +#include /*----------------------------------------------------------- * Port specific definitions. @@ -49,71 +50,84 @@ */ /* Type definitions. */ -#define portCHAR char -#define portFLOAT float -#define portDOUBLE double -#define portLONG long -#define portSHORT short -#define portSTACK_TYPE unsigned long -#define portBASE_TYPE long -#define portPOINTER_SIZE_TYPE intptr_t +#define portCHAR char +#define portFLOAT float +#define portDOUBLE double +#define portLONG long +#define portSHORT short +#define portSTACK_TYPE unsigned long +#define portBASE_TYPE long +#define portPOINTER_SIZE_TYPE intptr_t -typedef portSTACK_TYPE StackType_t; -typedef long BaseType_t; -typedef unsigned long UBaseType_t; +typedef portSTACK_TYPE StackType_t; +typedef long BaseType_t; +typedef unsigned long UBaseType_t; -typedef unsigned long TickType_t; -#define portMAX_DELAY ( TickType_t ) ULONG_MAX +typedef unsigned long TickType_t; +#define portMAX_DELAY ( TickType_t ) ULONG_MAX -#define portTICK_TYPE_IS_ATOMIC 1 +#define portTICK_TYPE_IS_ATOMIC 1 /*-----------------------------------------------------------*/ /* Architecture specifics. */ -#define portSTACK_GROWTH ( -1 ) -#define portHAS_STACK_OVERFLOW_CHECKING ( 1 ) -#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) -#define portTICK_RATE_MICROSECONDS ( ( TickType_t ) 1000000 / configTICK_RATE_HZ ) -#define portBYTE_ALIGNMENT 8 +#define portSTACK_GROWTH ( -1 ) +#define portHAS_STACK_OVERFLOW_CHECKING ( 1 ) +#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) +#define portTICK_RATE_MICROSECONDS ( ( TickType_t ) 1000000 / configTICK_RATE_HZ ) +#define portBYTE_ALIGNMENT 8 /*-----------------------------------------------------------*/ /* Scheduler utilities. */ extern void vPortYield( void ); -#define portYIELD() vPortYield() - -#define portEND_SWITCHING_ISR( xSwitchRequired ) if( xSwitchRequired != pdFALSE ) vPortYield() -#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x ) +#define portYIELD() vPortYield() + +#define portEND_SWITCHING_ISR( xSwitchRequired ) \ + do \ + { \ + if( xSwitchRequired != pdFALSE ) \ + { \ + traceISR_EXIT_TO_SCHEDULER(); \ + vPortYield(); \ + } \ + else \ + { \ + traceISR_EXIT(); \ + } \ + } while( 0 ) +#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x ) /*-----------------------------------------------------------*/ /* Critical section management. */ extern void vPortDisableInterrupts( void ); extern void vPortEnableInterrupts( void ); -#define portSET_INTERRUPT_MASK() ( vPortDisableInterrupts() ) -#define portCLEAR_INTERRUPT_MASK() ( vPortEnableInterrupts() ) +#define portSET_INTERRUPT_MASK() ( vPortDisableInterrupts() ) +#define portCLEAR_INTERRUPT_MASK() ( vPortEnableInterrupts() ) extern UBaseType_t xPortSetInterruptMask( void ); extern void vPortClearInterruptMask( UBaseType_t xMask ); extern void vPortEnterCritical( void ); extern void vPortExitCritical( void ); -#define portSET_INTERRUPT_MASK_FROM_ISR() xPortSetInterruptMask() -#define portCLEAR_INTERRUPT_MASK_FROM_ISR(x) vPortClearInterruptMask(x) -#define portDISABLE_INTERRUPTS() portSET_INTERRUPT_MASK() -#define portENABLE_INTERRUPTS() portCLEAR_INTERRUPT_MASK() -#define portENTER_CRITICAL() vPortEnterCritical() -#define portEXIT_CRITICAL() vPortExitCritical() +#define portSET_INTERRUPT_MASK_FROM_ISR() xPortSetInterruptMask() +#define portCLEAR_INTERRUPT_MASK_FROM_ISR( x ) vPortClearInterruptMask( x ) +#define portDISABLE_INTERRUPTS() portSET_INTERRUPT_MASK() +#define portENABLE_INTERRUPTS() portCLEAR_INTERRUPT_MASK() +#define portENTER_CRITICAL() vPortEnterCritical() +#define portEXIT_CRITICAL() vPortExitCritical() /*-----------------------------------------------------------*/ -extern void vPortThreadDying( void *pxTaskToDelete, volatile BaseType_t *pxPendYield ); -extern void vPortCancelThread( void *pxTaskToDelete ); -#define portPRE_TASK_DELETE_HOOK( pvTaskToDelete, pxPendYield ) vPortThreadDying( ( pvTaskToDelete ), ( pxPendYield ) ) -#define portCLEAN_UP_TCB( pxTCB ) vPortCancelThread( pxTCB ) +extern void vPortThreadDying( void * pxTaskToDelete, + volatile BaseType_t * pxPendYield ); +extern void vPortCancelThread( void * pxTaskToDelete ); +#define portPRE_TASK_DELETE_HOOK( pvTaskToDelete, pxPendYield ) vPortThreadDying( ( pvTaskToDelete ), ( pxPendYield ) ) +#define portCLEAN_UP_TCB( pxTCB ) vPortCancelThread( pxTCB ) /*-----------------------------------------------------------*/ -#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters ) __attribute__( ( noreturn ) ) -#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters ) +#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters ) __attribute__( ( noreturn ) ) +#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters ) /*-----------------------------------------------------------*/ /* @@ -124,11 +138,11 @@ extern void vPortCancelThread( void *pxTaskToDelete ); * Thus, only a compilier barrier is needed to prevent the compiler * reordering. */ -#define portMEMORY_BARRIER() __asm volatile( "" ::: "memory" ) +#define portMEMORY_BARRIER() __asm volatile ( "" ::: "memory" ) -extern unsigned long ulPortGetRunTime( void ); -#define portCONFIGURE_TIMER_FOR_RUN_TIME_STATS() /* no-op */ -#define portGET_RUN_TIME_COUNTER_VALUE() ulPortGetRunTime() +extern uint32_t ulPortGetRunTime( void ); +#define portCONFIGURE_TIMER_FOR_RUN_TIME_STATS() /* no-op */ +#define portGET_RUN_TIME_COUNTER_VALUE() ulPortGetRunTime() /* *INDENT-OFF* */ #ifdef __cplusplus diff --git a/Source/portable/ThirdParty/GCC/Posix/utils/wait_for_event.c b/Source/portable/ThirdParty/GCC/Posix/utils/wait_for_event.c index a0d71ab70..5b31cf8da 100644 --- a/Source/portable/ThirdParty/GCC/Posix/utils/wait_for_event.c +++ b/Source/portable/ThirdParty/GCC/Posix/utils/wait_for_event.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -77,10 +77,10 @@ bool event_wait_timed( struct event * ev, clock_gettime( CLOCK_REALTIME, &ts ); ts.tv_sec += ms / 1000; - ts.tv_nsec += ((ms % 1000) * 1000000); + ts.tv_nsec += ( ( ms % 1000 ) * 1000000 ); pthread_mutex_lock( &ev->mutex ); - while( (ev->event_triggered == false) && (ret == 0) ) + while( ( ev->event_triggered == false ) && ( ret == 0 ) ) { ret = pthread_cond_timedwait( &ev->cond, &ev->mutex, &ts ); diff --git a/Source/portable/ThirdParty/GCC/Posix/utils/wait_for_event.h b/Source/portable/ThirdParty/GCC/Posix/utils/wait_for_event.h index 6584d765c..5e5bbde6d 100644 --- a/Source/portable/ThirdParty/GCC/Posix/utils/wait_for_event.h +++ b/Source/portable/ThirdParty/GCC/Posix/utils/wait_for_event.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -26,8 +26,8 @@ * */ -#ifndef _WAIT_FOR_EVENT_H_ -#define _WAIT_FOR_EVENT_H_ +#ifndef WAIT_FOR_EVENT_H_ +#define WAIT_FOR_EVENT_H_ #include #include @@ -43,4 +43,4 @@ void event_signal( struct event * ev ); -#endif /* ifndef _WAIT_FOR_EVENT_H_ */ +#endif /* ifndef WAIT_FOR_EVENT_H_ */ diff --git a/Source/portable/ThirdParty/GCC/RP2040/README.md b/Source/portable/ThirdParty/GCC/RP2040/README.md index c50cb4e38..bd521d53f 100644 --- a/Source/portable/ThirdParty/GCC/RP2040/README.md +++ b/Source/portable/ThirdParty/GCC/RP2040/README.md @@ -1,32 +1,33 @@ ## Overview -This directory provides a FreeRTOS-Kernel port that can be used with the Raspberry Pi Pico SDK. It supports: +This directory provides an SMP FreeRTOS-Kernel port that can be used with the Raspberry Pi Pico SDK. It supports: * Simple CMake INTERFACE libraries, to provide the FreeRTOS-Kernel and also the individual allocator types, without copying code into the user's project. - * Running the FreeRTOS-Kernel and tasks on either core 0 or core 1 - * Use of SDK synchronization primitives (such as mutexes, semaphores, queues from pico_sync) between FreeRTOS tasks and code executing on the other core, or in IRQ handlers. + * Running the FreeRTOS-Kernel and tasks on either core 0 or core 1, or both. + * Use of SDK synchronization primitives (such as mutexes, semaphores, queues from pico_sync) between FreeRTOS tasks and code executing on a non FreeRTOS core, or in IRQ handlers. -Note that a FreeRTOS SMP version of this port is also available in the FreeRTOS-Kernel smp branch, which additionally supports utilizing both RP2040 CPU cores for FreeRTOS tasks simultaneously. +Note that whilst this SMP version can be run on just a single (either) core, it is probably +more efficient to use the non SMP version in the main FreeRTOS-Kernel branch in that case. ## Using this port -You can copy [FreeRTOS-Kernel-import.cmake](FreeRTOS-Kernel-import.cmake) into your project, and +You can copy [FreeRTOS_Kernel_import.cmake](FreeRTOS_Kernel_import.cmake) into your project, and add the following in your `CMakeLists.txt`: ```cmake include(FreeRTOS_Kernel_import.cmake) ``` -This will locate the FreeRTOS kernel if it is a direct sub-module of your project, or if you provide the +This will locate the FreeRTOS kernel if it is a direct sub-module of your project, or if you provide the `FREERTOS_KERNEL_PATH` variable in your environment or via `-DFREERTOS_KERNEL_PATH=/path/to/FreeRTOS-Kernel` on the CMake command line. -**NOTE:** If you are using version 1.3.1 or older of the Raspberry Pi Pico SDK then this line must appear before the -`pico_sdk_init()` and will cause FreeRTOS to be included/required in all RP2040 targets in your project. After this SDK -version, you can include the FreeRTOS-Kernel support later in your CMake build (possibly in a subdirectory) and the +**NOTE:** If you are using version 1.3.1 or older of the Raspberry Pi Pico SDK then this line must appear before the +`pico_sdk_init()` and will cause FreeRTOS to be included/required in all RP2040 targets in your project. After this SDK +version, you can include the FreeRTOS-Kernel support later in your CMake build (possibly in a subdirectory) and the FreeRTOS-Kernel support will only apply to those targets which explicitly include FreeRTOS support. -As an alternative to the `import` statement above, you can just add this directory directly via thw following (with -the same placement restrictions related to the Raspberry Pi Pico SDK version above): +As an alternative to the `import` statement above, you can just add this directory directly via thw following (with +the same placement restrictions related to the Raspberry Pi Pico SDK version above): ```cmake add_subdirectory(path/to/this/directory FreeRTOS-Kernel) diff --git a/Source/portable/ThirdParty/GCC/RP2040/idle_task_static_memory.c b/Source/portable/ThirdParty/GCC/RP2040/idle_task_static_memory.c index fe384aa5a..2cc0d0b74 100644 --- a/Source/portable/ThirdParty/GCC/RP2040/idle_task_static_memory.c +++ b/Source/portable/ThirdParty/GCC/RP2040/idle_task_static_memory.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * Copyright (c) 2021 Raspberry Pi (Trading) Ltd. * @@ -28,25 +28,25 @@ #include "FreeRTOS.h" -void vApplicationGetIdleTaskMemory( StaticTask_t **ppxIdleTaskTCBBuffer, - StackType_t **ppxIdleTaskStackBuffer, - uint32_t *pulIdleTaskStackSize ) +void vApplicationGetIdleTaskMemory( StaticTask_t ** ppxIdleTaskTCBBuffer, + StackType_t ** ppxIdleTaskStackBuffer, + uint32_t * pulIdleTaskStackSize ) { /* If the buffers to be provided to the Idle task are declared inside this - function then they must be declared static - otherwise they will be allocated on - the stack and so not exists after this function exits. */ + * function then they must be declared static - otherwise they will be allocated on + * the stack and so not exists after this function exits. */ static StaticTask_t xIdleTaskTCB; static StackType_t uxIdleTaskStack[ configMINIMAL_STACK_SIZE ]; /* Pass out a pointer to the StaticTask_t structure in which the Idle task's - state will be stored. */ + * state will be stored. */ *ppxIdleTaskTCBBuffer = &xIdleTaskTCB; /* Pass out the array that will be used as the Idle task's stack. */ *ppxIdleTaskStackBuffer = uxIdleTaskStack; /* Pass out the size of the array pointed to by *ppxIdleTaskStackBuffer. - Note that, as the array is necessarily of type StackType_t, - configMINIMAL_STACK_SIZE is specified in words, not bytes. */ + * Note that, as the array is necessarily of type StackType_t, + * configMINIMAL_STACK_SIZE is specified in words, not bytes. */ *pulIdleTaskStackSize = configMINIMAL_STACK_SIZE; } diff --git a/Source/portable/ThirdParty/GCC/RP2040/include/freertos_sdk_config.h b/Source/portable/ThirdParty/GCC/RP2040/include/freertos_sdk_config.h index ca0022562..9c182f09e 100644 --- a/Source/portable/ThirdParty/GCC/RP2040/include/freertos_sdk_config.h +++ b/Source/portable/ThirdParty/GCC/RP2040/include/freertos_sdk_config.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * Copyright (c) 2021 Raspberry Pi (Trading) Ltd. * @@ -33,41 +33,45 @@ #include "FreeRTOSConfig.h" #include "rp2040_config.h" #ifndef PICO_USE_MALLOC_MUTEX - // malloc needs to be made thread safe - #define PICO_USE_MALLOC_MUTEX 1 + /* malloc needs to be made thread safe */ + #define PICO_USE_MALLOC_MUTEX 1 #endif /* PICO_USE_MALLOC_MUTEX */ #if ( configSUPPORT_PICO_SYNC_INTEROP == 1 ) - // increase the amount of time it may reasonably take to wake us up + /* increase the amount of time it may reasonably take to wake us up */ #ifndef PICO_TIME_SLEEP_OVERHEAD_ADJUST_US - #define PICO_TIME_SLEEP_OVERHEAD_ADJUST_US 150 + #define PICO_TIME_SLEEP_OVERHEAD_ADJUST_US 150 #endif - #define lock_owner_id_t uint32_t - extern uint32_t ulPortLockGetCurrentOwnerId(void); - #define lock_get_caller_owner_id() ulPortLockGetCurrentOwnerId() - #define LOCK_INVALID_OWNER_ID ((uint32_t)-1) + #define lock_owner_id_t uint32_t + extern uint32_t ulPortLockGetCurrentOwnerId( void ); + #define lock_get_caller_owner_id() ulPortLockGetCurrentOwnerId() + #define LOCK_INVALID_OWNER_ID ( ( uint32_t ) -1 ) struct lock_core; #ifndef lock_internal_spin_unlock_with_wait - extern void vPortLockInternalSpinUnlockWithWait( struct lock_core *pxLock, uint32_t ulSave); - #define lock_internal_spin_unlock_with_wait(lock, save) vPortLockInternalSpinUnlockWithWait(lock, save) + extern void vPortLockInternalSpinUnlockWithWait( struct lock_core * pxLock, + uint32_t ulSave ); + #define lock_internal_spin_unlock_with_wait( lock, save ) vPortLockInternalSpinUnlockWithWait( lock, save ) #endif #ifndef lock_internal_spin_unlock_with_notify - extern void vPortLockInternalSpinUnlockWithNotify( struct lock_core *pxLock, uint32_t save); - #define lock_internal_spin_unlock_with_notify(lock, save) vPortLockInternalSpinUnlockWithNotify(lock, save); + extern void vPortLockInternalSpinUnlockWithNotify( struct lock_core * pxLock, + uint32_t save ); + #define lock_internal_spin_unlock_with_notify( lock, save ) vPortLockInternalSpinUnlockWithNotify( lock, save ); #endif #ifndef lock_internal_spin_unlock_with_best_effort_wait_or_timeout - extern bool xPortLockInternalSpinUnlockWithBestEffortWaitOrTimeout( struct lock_core *pxLock, uint32_t ulSave, absolute_time_t uxUntil); - #define lock_internal_spin_unlock_with_best_effort_wait_or_timeout(lock, save, until) \ - xPortLockInternalSpinUnlockWithBestEffortWaitOrTimeout(lock, save, until) + extern bool xPortLockInternalSpinUnlockWithBestEffortWaitOrTimeout( struct lock_core * pxLock, + uint32_t ulSave, + absolute_time_t uxUntil ); + #define lock_internal_spin_unlock_with_best_effort_wait_or_timeout( lock, save, until ) \ + xPortLockInternalSpinUnlockWithBestEffortWaitOrTimeout( lock, save, until ) #endif #endif /* configSUPPORT_PICO_SYNC_INTEROP */ #if ( configSUPPORT_PICO_TIME_INTEROP == 1 ) - extern void xPortSyncInternalYieldUntilBefore(absolute_time_t t); - #define sync_internal_yield_until_before(t) xPortSyncInternalYieldUntilBefore(t) + extern void xPortSyncInternalYieldUntilBefore( absolute_time_t t ); + #define sync_internal_yield_until_before( t ) xPortSyncInternalYieldUntilBefore( t ) #endif /* configSUPPORT_PICO_TIME_INTEROP */ #endif /* __ASSEMBLER__ */ -#endif +#endif /* ifndef FREERTOS_SDK_CONFIG_H */ diff --git a/Source/portable/ThirdParty/GCC/RP2040/include/portmacro.h b/Source/portable/ThirdParty/GCC/RP2040/include/portmacro.h index 5fc9c3bdb..1a2d7e6b7 100644 --- a/Source/portable/ThirdParty/GCC/RP2040/include/portmacro.h +++ b/Source/portable/ThirdParty/GCC/RP2040/include/portmacro.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * Copyright (c) 2021 Raspberry Pi (Trading) Ltd. * @@ -28,7 +28,7 @@ */ #ifndef PORTMACRO_H - #define PORTMACRO_H +#define PORTMACRO_H /* *INDENT-OFF* */ #ifdef __cplusplus @@ -36,7 +36,9 @@ #endif /* *INDENT-ON* */ - #include "pico.h" +#include "pico.h" +#include "hardware/sync.h" + /*----------------------------------------------------------- * Port specific definitions. * @@ -48,105 +50,237 @@ */ /* Type definitions. */ - #define portCHAR char - #define portFLOAT float - #define portDOUBLE double - #define portLONG long - #define portSHORT short - #define portSTACK_TYPE uint32_t - #define portBASE_TYPE long - - typedef portSTACK_TYPE StackType_t; - typedef int32_t BaseType_t; - typedef uint32_t UBaseType_t; - - #if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS ) - typedef uint16_t TickType_t; - #define portMAX_DELAY ( TickType_t ) 0xffff - #elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS ) - typedef uint32_t TickType_t; - #define portMAX_DELAY ( TickType_t ) 0xffffffffUL +#define portCHAR char +#define portFLOAT float +#define portDOUBLE double +#define portLONG long +#define portSHORT short +#define portSTACK_TYPE uint32_t +#define portBASE_TYPE long + +typedef portSTACK_TYPE StackType_t; +typedef int32_t BaseType_t; +typedef uint32_t UBaseType_t; + +#if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS ) + typedef uint16_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffff +#elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS ) + typedef uint32_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffffffffUL /* 32-bit tick type on a 32-bit architecture, so reads of the tick count do * not need to be guarded with a critical section. */ - #define portTICK_TYPE_IS_ATOMIC 1 - #else - #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width. - #endif + #define portTICK_TYPE_IS_ATOMIC 1 +#else + #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width. +#endif /*-----------------------------------------------------------*/ /* Architecture specifics. */ - #define portSTACK_GROWTH ( -1 ) - #define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) - #define portBYTE_ALIGNMENT 8 - #define portDONT_DISCARD __attribute__( ( used ) ) - /* We have to use PICO_DIVIDER_DISABLE_INTERRUPTS as the source of truth rathern than our config, - * as our FreeRTOSConfig.h header cannot be included by ASM code - which is what this affects in the SDK */ - #define portUSE_DIVIDER_SAVE_RESTORE !PICO_DIVIDER_DISABLE_INTERRUPTS - #if portUSE_DIVIDER_SAVE_RESTORE - #define portSTACK_LIMIT_PADDING 4 - #endif +#define portSTACK_GROWTH ( -1 ) +#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) +#define portBYTE_ALIGNMENT 8 +#define portDONT_DISCARD __attribute__( ( used ) ) + +/* We have to use PICO_DIVIDER_DISABLE_INTERRUPTS as the source of truth rathern than our config, + * as our FreeRTOSConfig.h header cannot be included by ASM code - which is what this affects in the SDK */ +#define portUSE_DIVIDER_SAVE_RESTORE !PICO_DIVIDER_DISABLE_INTERRUPTS +#if portUSE_DIVIDER_SAVE_RESTORE + #define portSTACK_LIMIT_PADDING 4 +#endif /*-----------------------------------------------------------*/ /* Scheduler utilities. */ - extern void vPortYield( void ); - #define portNVIC_INT_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed04 ) ) - #define portNVIC_PENDSVSET_BIT ( 1UL << 28UL ) - #define portYIELD() vPortYield() - #define portEND_SWITCHING_ISR( xSwitchRequired ) if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT - #define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x ) +extern void vPortYield( void ); +#define portNVIC_INT_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed04 ) ) +#define portNVIC_PENDSVSET_BIT ( 1UL << 28UL ) +#define portYIELD() vPortYield() +#define portEND_SWITCHING_ISR( xSwitchRequired ) \ + do \ + { \ + if( xSwitchRequired ) \ + { \ + traceISR_EXIT_TO_SCHEDULER(); \ + portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; \ + } \ + else \ + { \ + traceISR_EXIT(); \ + } \ + } while( 0 ) +#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x ) /*-----------------------------------------------------------*/ /* Exception handlers */ - #if (configUSE_DYNAMIC_EXCEPTION_HANDLERS == 0) - /* We only need to override the SDK's weak functions if we want to replace them at compile time */ - #define vPortSVCHandler isr_svcall - #define xPortPendSVHandler isr_pendsv - #define xPortSysTickHandler isr_systick - #endif - - #define portCHECK_IF_IN_ISR() ({ \ - uint32_t ulIPSR; \ - __asm volatile ("mrs %0, IPSR" : "=r" (ulIPSR)::); \ - ((uint8_t)ulIPSR)>0;}) +#if ( configUSE_DYNAMIC_EXCEPTION_HANDLERS == 0 ) + /* We only need to override the SDK's weak functions if we want to replace them at compile time */ + #define vPortSVCHandler isr_svcall + #define xPortPendSVHandler isr_pendsv + #define xPortSysTickHandler isr_systick +#endif + +/*-----------------------------------------------------------*/ + +/* Multi-core */ +#define portMAX_CORE_COUNT 2 + +/* Check validity of number of cores specified in config */ +#if ( configNUMBER_OF_CORES < 1 || portMAX_CORE_COUNT < configNUMBER_OF_CORES ) + #error "Invalid number of cores specified in config!" +#endif + +#if ( configTICK_CORE < 0 || configTICK_CORE > configNUMBER_OF_CORES ) + #error "Invalid tick core specified in config!" +#endif +/* FreeRTOS core id is always zero based, so always 0 if we're running on only one core */ +#if configNUMBER_OF_CORES == portMAX_CORE_COUNT + #define portGET_CORE_ID() get_core_num() +#else + #define portGET_CORE_ID() 0 +#endif + +#define portCHECK_IF_IN_ISR() \ + ( { \ + uint32_t ulIPSR; \ + __asm volatile ( "mrs %0, IPSR" : "=r" ( ulIPSR )::); \ + ( ( uint8_t ) ulIPSR ) > 0; } ) + +void vYieldCore( int xCoreID ); +#define portYIELD_CORE( a ) vYieldCore( a ) +#define portRESTORE_INTERRUPTS( ulState ) __asm volatile ( "msr PRIMASK,%0" ::"r" ( ulState ) : ) + +/*-----------------------------------------------------------*/ + +/* Critical nesting count management. */ +extern UBaseType_t uxCriticalNestings[ configNUMBER_OF_CORES ]; +#define portGET_CRITICAL_NESTING_COUNT() ( uxCriticalNestings[ portGET_CORE_ID() ] ) +#define portSET_CRITICAL_NESTING_COUNT( x ) ( uxCriticalNestings[ portGET_CORE_ID() ] = ( x ) ) +#define portINCREMENT_CRITICAL_NESTING_COUNT() ( uxCriticalNestings[ portGET_CORE_ID() ]++ ) +#define portDECREMENT_CRITICAL_NESTING_COUNT() ( uxCriticalNestings[ portGET_CORE_ID() ]-- ) /*-----------------------------------------------------------*/ /* Critical section management. */ - extern uint32_t ulSetInterruptMaskFromISR( void ) __attribute__( ( naked ) ); - extern void vClearInterruptMaskFromISR( uint32_t ulMask ) __attribute__( ( naked ) ); - #define portSET_INTERRUPT_MASK_FROM_ISR() ulSetInterruptMaskFromISR() - #define portCLEAR_INTERRUPT_MASK_FROM_ISR( x ) vClearInterruptMaskFromISR( x ) - #define portDISABLE_INTERRUPTS() __asm volatile ( " cpsid i " ::: "memory" ) +#define portSET_INTERRUPT_MASK() \ + ( { \ + uint32_t ulState; \ + __asm volatile ( "mrs %0, PRIMASK" : "=r" ( ulState )::); \ + __asm volatile ( " cpsid i " ::: "memory" ); \ + ulState; } ) + +#define portCLEAR_INTERRUPT_MASK( ulState ) __asm volatile ( "msr PRIMASK,%0" ::"r" ( ulState ) : ) + +extern uint32_t ulSetInterruptMaskFromISR( void ) __attribute__( ( naked ) ); +extern void vClearInterruptMaskFromISR( uint32_t ulMask ) __attribute__( ( naked ) ); +#define portSET_INTERRUPT_MASK_FROM_ISR() ulSetInterruptMaskFromISR() +#define portCLEAR_INTERRUPT_MASK_FROM_ISR( x ) vClearInterruptMaskFromISR( x ) + +#define portDISABLE_INTERRUPTS() __asm volatile ( " cpsid i " ::: "memory" ) - extern void vPortEnableInterrupts(); - #define portENABLE_INTERRUPTS() vPortEnableInterrupts() +extern void vPortEnableInterrupts(); +#define portENABLE_INTERRUPTS() vPortEnableInterrupts() +#if ( configNUMBER_OF_CORES == 1 ) extern void vPortEnterCritical( void ); extern void vPortExitCritical( void ); - #define portENTER_CRITICAL() vPortEnterCritical() - #define portEXIT_CRITICAL() vPortExitCritical() + #define portENTER_CRITICAL() vPortEnterCritical() + #define portEXIT_CRITICAL() vPortExitCritical() +#else + extern void vTaskEnterCritical( void ); + extern void vTaskExitCritical( void ); + extern UBaseType_t vTaskEnterCriticalFromISR( void ); + extern void vTaskExitCriticalFromISR( UBaseType_t uxSavedInterruptStatus ); + #define portENTER_CRITICAL() vTaskEnterCritical() + #define portEXIT_CRITICAL() vTaskExitCritical() + #define portENTER_CRITICAL_FROM_ISR() vTaskEnterCriticalFromISR() + #define portEXIT_CRITICAL_FROM_ISR( x ) vTaskExitCriticalFromISR( x ) +#endif /* if ( configNUMBER_OF_CORES == 1 ) */ + +#define portRTOS_SPINLOCK_COUNT 2 + +/* Note this is a single method with uxAcquire parameter since we have + * static vars, the method is always called with a compile time constant for + * uxAcquire, and the compiler should dothe right thing! */ +static inline void vPortRecursiveLock( uint32_t ulLockNum, + spin_lock_t * pxSpinLock, + BaseType_t uxAcquire ) +{ + static uint8_t ucOwnedByCore[ portMAX_CORE_COUNT ]; + static uint8_t ucRecursionCountByLock[ portRTOS_SPINLOCK_COUNT ]; + + configASSERT( ulLockNum < portRTOS_SPINLOCK_COUNT ); + uint32_t ulCoreNum = get_core_num(); + uint32_t ulLockBit = 1u << ulLockNum; + configASSERT( ulLockBit < 256u ); + + if( uxAcquire ) + { + if( __builtin_expect( !*pxSpinLock, 0 ) ) + { + if( ucOwnedByCore[ ulCoreNum ] & ulLockBit ) + { + configASSERT( ucRecursionCountByLock[ ulLockNum ] != 255u ); + ucRecursionCountByLock[ ulLockNum ]++; + return; + } + + while( __builtin_expect( !*pxSpinLock, 0 ) ) + { + } + } + + __mem_fence_acquire(); + configASSERT( ucRecursionCountByLock[ ulLockNum ] == 0 ); + ucRecursionCountByLock[ ulLockNum ] = 1; + ucOwnedByCore[ ulCoreNum ] |= ulLockBit; + } + else + { + configASSERT( ( ucOwnedByCore[ ulCoreNum ] & ulLockBit ) != 0 ); + configASSERT( ucRecursionCountByLock[ ulLockNum ] != 0 ); + + if( !--ucRecursionCountByLock[ ulLockNum ] ) + { + ucOwnedByCore[ ulCoreNum ] &= ~ulLockBit; + __mem_fence_release(); + *pxSpinLock = 1; + } + } +} + +#if ( configNUMBER_OF_CORES == 1 ) + #define portGET_ISR_LOCK() + #define portRELEASE_ISR_LOCK() + #define portGET_TASK_LOCK() + #define portRELEASE_TASK_LOCK() +#else + #define portGET_ISR_LOCK() vPortRecursiveLock( 0, spin_lock_instance( configSMP_SPINLOCK_0 ), pdTRUE ) + #define portRELEASE_ISR_LOCK() vPortRecursiveLock( 0, spin_lock_instance( configSMP_SPINLOCK_0 ), pdFALSE ) + #define portGET_TASK_LOCK() vPortRecursiveLock( 1, spin_lock_instance( configSMP_SPINLOCK_1 ), pdTRUE ) + #define portRELEASE_TASK_LOCK() vPortRecursiveLock( 1, spin_lock_instance( configSMP_SPINLOCK_1 ), pdFALSE ) +#endif /*-----------------------------------------------------------*/ /* Tickless idle/low power functionality. */ - #ifndef portSUPPRESS_TICKS_AND_SLEEP - extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime ); - #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime ) vPortSuppressTicksAndSleep( xExpectedIdleTime ) - #endif +#ifndef portSUPPRESS_TICKS_AND_SLEEP + extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime ); + #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime ) vPortSuppressTicksAndSleep( xExpectedIdleTime ) +#endif /*-----------------------------------------------------------*/ /* Task function macros as described on the FreeRTOS.org WEB site. */ - #define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters ) - #define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters ) +#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters ) +#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters ) - #define portNOP() +#define portNOP() - #define portMEMORY_BARRIER() __asm volatile ( "" ::: "memory" ) +#define portMEMORY_BARRIER() __asm volatile ( "" ::: "memory" ) /* *INDENT-OFF* */ #ifdef __cplusplus diff --git a/Source/portable/ThirdParty/GCC/RP2040/include/rp2040_config.h b/Source/portable/ThirdParty/GCC/RP2040/include/rp2040_config.h index 0e97f98fc..f5cf799d2 100644 --- a/Source/portable/ThirdParty/GCC/RP2040/include/rp2040_config.h +++ b/Source/portable/ThirdParty/GCC/RP2040/include/rp2040_config.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * Copyright (c) 2021 Raspberry Pi (Trading) Ltd. * @@ -40,9 +40,9 @@ */ #ifndef configUSE_DYNAMIC_EXCEPTION_HANDLERS #if defined( PICO_NO_RAM_VECTOR_TABLE ) && ( PICO_NO_RAM_VECTOR_TABLE == 1 ) - #define configUSE_DYNAMIC_EXCEPTION_HANDLERS 0 + #define configUSE_DYNAMIC_EXCEPTION_HANDLERS 0 #else - #define configUSE_DYNAMIC_EXCEPTION_HANDLERS 1 + #define configUSE_DYNAMIC_EXCEPTION_HANDLERS 1 #endif #endif @@ -51,7 +51,7 @@ */ #ifndef configSUPPORT_PICO_SYNC_INTEROP #if LIB_PICO_SYNC - #define configSUPPORT_PICO_SYNC_INTEROP 1 + #define configSUPPORT_PICO_SYNC_INTEROP 1 #endif #endif @@ -61,14 +61,34 @@ */ #ifndef configSUPPORT_PICO_TIME_INTEROP #if LIB_PICO_TIME - #define configSUPPORT_PICO_TIME_INTEROP 1 + #define configSUPPORT_PICO_TIME_INTEROP 1 #endif #endif +#if ( configNUMBER_OF_CORES > 1 ) + +/* configTICK_CORE indicates which core should handle the SysTick + * interrupts */ + #ifndef configTICK_CORE + #define configTICK_CORE 0 + #endif +#endif + +/* This SMP port requires two spin locks, which are claimed from the SDK. + * the spin lock numbers to be used are defined statically and defaulted here + * to the values nominally set aside for RTOS by the SDK */ +#ifndef configSMP_SPINLOCK_0 + #define configSMP_SPINLOCK_0 PICO_SPINLOCK_ID_OS1 +#endif + +#ifndef configSMP_SPINLOCK_1 + #define configSMP_SPINLOCK_1 PICO_SPINLOCK_ID_OS2 +#endif + /* *INDENT-OFF* */ #ifdef __cplusplus } #endif /* *INDENT-ON* */ -#endif +#endif /* ifndef RP2040_CONFIG_H */ diff --git a/Source/portable/ThirdParty/GCC/RP2040/library.cmake b/Source/portable/ThirdParty/GCC/RP2040/library.cmake index 902a21766..1db96517a 100644 --- a/Source/portable/ThirdParty/GCC/RP2040/library.cmake +++ b/Source/portable/ThirdParty/GCC/RP2040/library.cmake @@ -33,11 +33,14 @@ target_include_directories(FreeRTOS-Kernel INTERFACE target_link_libraries(FreeRTOS-Kernel INTERFACE FreeRTOS-Kernel-Core pico_base_headers - hardware_exception) + hardware_clocks + hardware_exception + pico_multicore +) target_compile_definitions(FreeRTOS-Kernel INTERFACE LIB_FREERTOS_KERNEL=1 - FREERTOS_KERNEL_SMP=0 + FREE_RTOS_KERNEL_SMP=1 ) add_library(FreeRTOS-Kernel-Static INTERFACE) diff --git a/Source/portable/ThirdParty/GCC/RP2040/port.c b/Source/portable/ThirdParty/GCC/RP2040/port.c index ada8d8421..ab471d264 100644 --- a/Source/portable/ThirdParty/GCC/RP2040/port.c +++ b/Source/portable/ThirdParty/GCC/RP2040/port.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * Copyright (c) 2021 Raspberry Pi (Trading) Ltd. * @@ -28,8 +28,8 @@ */ /*---------------------------------------------------------------------- -* Implementation of functions defined in portable.h for the RP2040 port. -*----------------------------------------------------------------------*/ + * Implementation of functions defined in portable.h for the RP2040 port. + *----------------------------------------------------------------------*/ #include "FreeRTOS.h" #include "task.h" @@ -42,10 +42,13 @@ * the non SMP FreeRTOS_Kernel is not linked with pico_multicore itself). We * use this flag to determine if we need multi-core functionality. */ -#if ( LIB_PICO_MULTICORE == 1) +#if ( LIB_PICO_MULTICORE == 1 ) #include "pico/multicore.h" #endif /* LIB_PICO_MULTICORE */ +/* TODO : consider to remove this macro. */ +#define portRUNNING_ON_BOTH_CORES ( configNUMBER_OF_CORES == portMAX_CORE_COUNT ) + /* Constants required to manipulate the NVIC. */ #define portNVIC_SYSTICK_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000e010 ) ) #define portNVIC_SYSTICK_LOAD_REG ( *( ( volatile uint32_t * ) 0xe000e014 ) ) @@ -112,7 +115,11 @@ static void prvTaskExitError( void ); /* Each task maintains its own interrupt status in the critical nesting * variable. This is initialized to 0 to allow vPortEnter/ExitCritical * to be called before the scheduler is started */ -static UBaseType_t uxCriticalNesting; +#if ( configNUMBER_OF_CORES == 1 ) + static UBaseType_t uxCriticalNesting; +#else /* #if ( configNUMBER_OF_CORES == 1 ) */ +UBaseType_t uxCriticalNestings[ configNUMBER_OF_CORES ] = { 0 }; +#endif /* #if ( configNUMBER_OF_CORES == 1 ) */ /*-----------------------------------------------------------*/ @@ -122,16 +129,16 @@ static UBaseType_t uxCriticalNesting; #include "event_groups.h" #if configSUPPORT_STATIC_ALLOCATION static StaticEventGroup_t xStaticEventGroup; - #define pEventGroup (&xStaticEventGroup) + #define pEventGroup ( &xStaticEventGroup ) #endif /* configSUPPORT_STATIC_ALLOCATION */ static EventGroupHandle_t xEventGroup; - #if ( LIB_PICO_MULTICORE == 1 ) + #if ( portRUNNING_ON_BOTH_CORES == 0 ) static EventBits_t uxCrossCoreEventBits; static spin_lock_t * pxCrossCoreSpinLock; - #endif /* LIB_PICO_MULTICORE */ + #endif - static spin_lock_t * pxYieldSpinLock; - static uint32_t ulYieldSpinLockSaveValue; + static spin_lock_t * pxYieldSpinLock[ configNUMBER_OF_CORES ]; + static uint32_t ulYieldSpinLockSaveValue[ configNUMBER_OF_CORES ]; #endif /* configSUPPORT_PICO_SYNC_INTEROP */ /* @@ -159,9 +166,16 @@ static UBaseType_t uxCriticalNesting; /*-----------------------------------------------------------*/ -#define INVALID_LAUNCH_CORE_NUM 0xffu -static uint8_t ucLaunchCoreNum = INVALID_LAUNCH_CORE_NUM; -#define portIS_FREE_RTOS_CORE() ( ucLaunchCoreNum == get_core_num() ) +#define INVALID_PRIMARY_CORE_NUM 0xffu +/* The primary core number (the own which has the SysTick handler) */ +static uint8_t ucPrimaryCoreNum = INVALID_PRIMARY_CORE_NUM; + +/* Note: portIS_FREE_RTOS_CORE() also returns false until the scheduler is started */ +#if ( portRUNNING_ON_BOTH_CORES == 1 ) + #define portIS_FREE_RTOS_CORE() ( ucPrimaryCoreNum != INVALID_PRIMARY_CORE_NUM ) +#else + #define portIS_FREE_RTOS_CORE() ( ucPrimaryCoreNum == get_core_num() ) +#endif /* * See header file for description. @@ -204,94 +218,229 @@ void vPortSVCHandler( void ) void vPortStartFirstTask( void ) { - __asm volatile ( - " .syntax unified \n" - " ldr r2, pxCurrentTCBConst1 \n"/* Obtain location of pxCurrentTCB. */ - " ldr r3, [r2] \n" - " ldr r0, [r3] \n"/* The first item in pxCurrentTCB is the task top of stack. */ - " adds r0, #32 \n"/* Discard everything up to r0. */ - " msr psp, r0 \n"/* This is now the new top of stack to use in the task. */ - " movs r0, #2 \n"/* Switch to the psp stack. */ - " msr CONTROL, r0 \n" - " isb \n" - " pop {r0-r5} \n"/* Pop the registers that are saved automatically. */ - " mov lr, r5 \n"/* lr is now in r5. */ - " pop {r3} \n"/* Return address is now in r3. */ - " pop {r2} \n"/* Pop and discard XPSR. */ - " cpsie i \n"/* The first task has its context and interrupts can be enabled. */ - " bx r3 \n"/* Finally, jump to the user defined task code. */ - " .align 4 \n" - "pxCurrentTCBConst1: .word pxCurrentTCB\n" - ); + #if ( configNUMBER_OF_CORES == 1 ) + __asm volatile ( + " .syntax unified \n" + " ldr r2, pxCurrentTCBConst1 \n" /* Obtain location of pxCurrentTCB. */ + " ldr r3, [r2] \n" + " ldr r0, [r3] \n" /* The first item in pxCurrentTCB is the task top of stack. */ + " adds r0, #32 \n" /* Discard everything up to r0. */ + " msr psp, r0 \n" /* This is now the new top of stack to use in the task. */ + " movs r0, #2 \n" /* Switch to the psp stack. */ + " msr CONTROL, r0 \n" + " isb \n" + " pop {r0-r5} \n" /* Pop the registers that are saved automatically. */ + " mov lr, r5 \n" /* lr is now in r5. */ + " pop {r3} \n" /* Return address is now in r3. */ + " pop {r2} \n" /* Pop and discard XPSR. */ + " cpsie i \n" /* The first task has its context and interrupts can be enabled. */ + " bx r3 \n" /* Finally, jump to the user defined task code. */ + " .align 4 \n" + "pxCurrentTCBConst1: .word pxCurrentTCB\n" + ); + #else /* if ( configNUMBER_OF_CORES == 1 ) */ + __asm volatile ( + " .syntax unified \n" + #if configRESET_STACK_POINTER + " ldr r0, =0xE000ED08 \n" /* Use the NVIC offset register to locate the stack. */ + " ldr r0, [r0] \n" + " ldr r0, [r0] \n" + " msr msp, r0 \n" /* Set the msp back to the start of the stack. */ + #endif /* configRESET_STACK_POINTER */ + #if portRUNNING_ON_BOTH_CORES + " adr r1, ulAsmLocals \n" /* Get the location of the current TCB for the current core. */ + " ldmia r1!, {r2, r3} \n" + " ldr r2, [r2] \n" /* r2 = Core number */ + " lsls r2, #2 \n" + " ldr r3, [r3, r2] \n" /* r3 = pxCurrentTCBs[get_core_num()] */ + #else + " ldr r3, =pxCurrentTCBs \n" + " ldr r3, [r3] \n" /* r3 = pxCurrentTCBs[0] */ + #endif /* portRUNNING_ON_BOTH_CORES */ + " ldr r0, [r3] \n" /* The first item in pxCurrentTCB is the task top of stack. */ + " adds r0, #32 \n" /* Discard everything up to r0. */ + " msr psp, r0 \n" /* This is now the new top of stack to use in the task. */ + " movs r0, #2 \n" /* Switch to the psp stack. */ + " msr CONTROL, r0 \n" + " isb \n" + " pop {r0-r5} \n" /* Pop the registers that are saved automatically. */ + " mov lr, r5 \n" /* lr is now in r5. */ + " pop {r3} \n" /* Return address is now in r3. */ + " pop {r2} \n" /* Pop and discard XPSR. */ + " cpsie i \n" /* The first task has its context and interrupts can be enabled. */ + " bx r3 \n" /* Finally, jump to the user defined task code. */ + #if portRUNNING_ON_BOTH_CORES + " \n" + " .align 4 \n" + "ulAsmLocals: \n" + " .word 0xD0000000 \n" /* SIO */ + " .word pxCurrentTCBs \n" + #endif /* portRUNNING_ON_BOTH_CORES */ + ); + #endif /* if ( configNUMBER_OF_CORES == 1 ) */ } /*-----------------------------------------------------------*/ -#if ( LIB_PICO_MULTICORE == 1 ) && ( configSUPPORT_PICO_SYNC_INTEROP == 1) +#if ( LIB_PICO_MULTICORE == 1 ) && ( configSUPPORT_PICO_SYNC_INTEROP == 1 ) static void prvFIFOInterruptHandler() { /* We must remove the contents (which we don't care about) * to clear the IRQ */ multicore_fifo_drain(); + + /* And explicitly clear any other IRQ flags. */ multicore_fifo_clear_irq(); - BaseType_t xHigherPriorityTaskWoken = pdFALSE; - uint32_t ulSave = spin_lock_blocking( pxCrossCoreSpinLock ); - EventBits_t ulBits = uxCrossCoreEventBits; - uxCrossCoreEventBits &= ~ulBits; - spin_unlock( pxCrossCoreSpinLock, ulSave ); - xEventGroupSetBitsFromISR( xEventGroup, ulBits, &xHigherPriorityTaskWoken ); - portYIELD_FROM_ISR( xHigherPriorityTaskWoken ); + + #if ( portRUNNING_ON_BOTH_CORES == 1 ) + portYIELD_FROM_ISR( pdTRUE ); + #elif ( configSUPPORT_PICO_SYNC_INTEROP == 1 ) + BaseType_t xHigherPriorityTaskWoken = pdFALSE; + uint32_t ulSave = spin_lock_blocking( pxCrossCoreSpinLock ); + EventBits_t ulBits = uxCrossCoreEventBits; + uxCrossCoreEventBits &= ~ulBits; + spin_unlock( pxCrossCoreSpinLock, ulSave ); + xEventGroupSetBitsFromISR( xEventGroup, ulBits, &xHigherPriorityTaskWoken ); + portYIELD_FROM_ISR( xHigherPriorityTaskWoken ); + #endif /* portRUNNING_ON_BOTH_CORES */ } -#endif +#endif /* if ( LIB_PICO_MULTICORE == 1 ) && ( configSUPPORT_PICO_SYNC_INTEROP == 1 ) */ + +#if ( configNUMBER_OF_CORES > 1 ) /* * See header file for description. */ -BaseType_t xPortStartScheduler( void ) -{ - /* Make PendSV, CallSV and SysTick the same priority as the kernel. */ - portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI; - portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI; - - #if (configUSE_DYNAMIC_EXCEPTION_HANDLERS == 1) - exception_set_exclusive_handler( PENDSV_EXCEPTION, xPortPendSVHandler ); - exception_set_exclusive_handler( SYSTICK_EXCEPTION, xPortSysTickHandler ); - exception_set_exclusive_handler( SVCALL_EXCEPTION, vPortSVCHandler ); - #endif + static BaseType_t xPortStartSchedulerOnCore() + { + if( ucPrimaryCoreNum == get_core_num() ) + { + /* Start the timer that generates the tick ISR. Interrupts are disabled + * here already. */ + vPortSetupTimerInterrupt(); + + /* Make PendSV, CallSV and SysTick the same priority as the kernel. */ + portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI; + #if ( configUSE_DYNAMIC_EXCEPTION_HANDLERS == 1 ) + exception_set_exclusive_handler( SYSTICK_EXCEPTION, xPortSysTickHandler ); + #endif + } - /* Start the timer that generates the tick ISR. Interrupts are disabled - * here already. */ - vPortSetupTimerInterrupt(); - - /* Initialise the critical nesting count ready for the first task. */ - uxCriticalNesting = 0; - - ucLaunchCoreNum = get_core_num(); - #if (LIB_PICO_MULTICORE == 1) - #if ( configSUPPORT_PICO_SYNC_INTEROP == 1) - multicore_fifo_clear_irq(); - multicore_fifo_drain(); - uint32_t irq_num = 15 + get_core_num(); - irq_set_priority( irq_num, portMIN_INTERRUPT_PRIORITY ); - irq_set_exclusive_handler( irq_num, prvFIFOInterruptHandler ); - irq_set_enabled( irq_num, 1 ); + portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI; + + #if ( configUSE_DYNAMIC_EXCEPTION_HANDLERS == 1 ) + exception_set_exclusive_handler( PENDSV_EXCEPTION, xPortPendSVHandler ); + exception_set_exclusive_handler( SVCALL_EXCEPTION, vPortSVCHandler ); #endif + + /* Install FIFO handler to receive interrupt from other core */ + multicore_fifo_clear_irq(); + multicore_fifo_drain(); + uint32_t ulIRQNum = SIO_IRQ_PROC0 + get_core_num(); + irq_set_priority( ulIRQNum, portMIN_INTERRUPT_PRIORITY ); + irq_set_exclusive_handler( ulIRQNum, prvFIFOInterruptHandler ); + irq_set_enabled( ulIRQNum, 1 ); + + /* Start the first task. */ + vPortStartFirstTask(); + + /* Should never get here as the tasks will now be executing! Call the task + * exit error function to prevent compiler warnings about a static function + * not being called in the case that the application writer overrides this + * functionality by defining configTASK_RETURN_ADDRESS. Call + * vTaskSwitchContext() so link time optimisation does not remove the + * symbol. */ + vTaskSwitchContext( portGET_CORE_ID() ); + prvTaskExitError(); + + /* Should not get here! */ + return 0; + } + + #if portRUNNING_ON_BOTH_CORES + static void prvDisableInterruptsAndPortStartSchedulerOnCore( void ) + { + portDISABLE_INTERRUPTS(); + xPortStartSchedulerOnCore(); + } #endif - /* Start the first task. */ - vPortStartFirstTask(); +/* + * See header file for description. + */ + BaseType_t xPortStartScheduler( void ) + { + configASSERT( ucPrimaryCoreNum == INVALID_PRIMARY_CORE_NUM ); + + /* No one else should use these! */ + spin_lock_claim( configSMP_SPINLOCK_0 ); + spin_lock_claim( configSMP_SPINLOCK_1 ); - /* Should never get here as the tasks will now be executing! Call the task - * exit error function to prevent compiler warnings about a static function - * not being called in the case that the application writer overrides this - * functionality by defining configTASK_RETURN_ADDRESS. Call - * vTaskSwitchContext() so link time optimisation does not remove the - * symbol. */ - vTaskSwitchContext(); - prvTaskExitError(); + #if portRUNNING_ON_BOTH_CORES + ucPrimaryCoreNum = configTICK_CORE; + configASSERT( get_core_num() == 0 ); /* we must be started on core 0 */ + multicore_launch_core1( prvDisableInterruptsAndPortStartSchedulerOnCore ); + #else + ucPrimaryCoreNum = get_core_num(); + #endif + xPortStartSchedulerOnCore(); + + /* Should not get here! */ + return 0; + } + +#else /* if ( configNUMBER_OF_CORES > 1 ) */ + +/* + * See header file for description. + */ + BaseType_t xPortStartScheduler( void ) + { + /* Make PendSV, CallSV and SysTick the same priority as the kernel. */ + portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI; + portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI; + + #if ( configUSE_DYNAMIC_EXCEPTION_HANDLERS == 1 ) + exception_set_exclusive_handler( PENDSV_EXCEPTION, xPortPendSVHandler ); + exception_set_exclusive_handler( SYSTICK_EXCEPTION, xPortSysTickHandler ); + exception_set_exclusive_handler( SVCALL_EXCEPTION, vPortSVCHandler ); + #endif + + /* Start the timer that generates the tick ISR. Interrupts are disabled + * here already. */ + vPortSetupTimerInterrupt(); + + /* Initialise the critical nesting count ready for the first task. */ + uxCriticalNesting = 0; + + ucPrimaryCoreNum = get_core_num(); + #if ( LIB_PICO_MULTICORE == 1 ) + #if ( configSUPPORT_PICO_SYNC_INTEROP == 1 ) + multicore_fifo_clear_irq(); + multicore_fifo_drain(); + uint32_t irq_num = 15 + get_core_num(); + irq_set_priority( irq_num, portMIN_INTERRUPT_PRIORITY ); + irq_set_exclusive_handler( irq_num, prvFIFOInterruptHandler ); + irq_set_enabled( irq_num, 1 ); + #endif + #endif + + /* Start the first task. */ + vPortStartFirstTask(); + + /* Should never get here as the tasks will now be executing! Call the task + * exit error function to prevent compiler warnings about a static function + * not being called in the case that the application writer overrides this + * functionality by defining configTASK_RETURN_ADDRESS. Call + * vTaskSwitchContext() so link time optimisation does not remove the + * symbol. */ + vTaskSwitchContext(); + prvTaskExitError(); + + /* Should not get here! */ + return 0; + } +#endif /* if ( configNUMBER_OF_CORES > 1 ) */ - /* Should not get here! */ - return 0; -} /*-----------------------------------------------------------*/ void vPortEndScheduler( void ) @@ -304,9 +453,10 @@ void vPortEndScheduler( void ) void vPortYield( void ) { #if ( configSUPPORT_PICO_SYNC_INTEROP == 1 ) + /* We are not in an ISR, and pxYieldSpinLock is always dealt with and - * cleared interrupts are re-enabled, so should be NULL */ - configASSERT( pxYieldSpinLock == NULL ); + * cleared when interrupts are re-enabled, so should be NULL */ + configASSERT( pxYieldSpinLock[ portGET_CORE_ID() ] == NULL ); #endif /* configSUPPORT_PICO_SYNC_INTEROP */ /* Set a PendSV to request a context switch. */ @@ -320,31 +470,40 @@ void vPortYield( void ) /*-----------------------------------------------------------*/ -void vPortEnterCritical( void ) -{ - portDISABLE_INTERRUPTS(); - uxCriticalNesting++; - __asm volatile ( "dsb" ::: "memory" ); - __asm volatile ( "isb" ); -} +#if ( configNUMBER_OF_CORES == 1 ) + void vPortEnterCritical( void ) + { + portDISABLE_INTERRUPTS(); + uxCriticalNesting++; + __asm volatile ( "dsb" ::: "memory" ); + __asm volatile ( "isb" ); + } +#endif /* #if ( configNUMBER_OF_CORES == 1 ) */ /*-----------------------------------------------------------*/ -void vPortExitCritical( void ) -{ - configASSERT( uxCriticalNesting ); - uxCriticalNesting--; - if( uxCriticalNesting == 0 ) +#if ( configNUMBER_OF_CORES == 1 ) + void vPortExitCritical( void ) { - portENABLE_INTERRUPTS(); + configASSERT( uxCriticalNesting ); + uxCriticalNesting--; + + if( uxCriticalNesting == 0 ) + { + portENABLE_INTERRUPTS(); + } } -} +#endif /* #if ( configNUMBER_OF_CORES == 1 ) */ -void vPortEnableInterrupts() { +void vPortEnableInterrupts( void ) +{ #if ( configSUPPORT_PICO_SYNC_INTEROP == 1 ) - if( pxYieldSpinLock ) + int xCoreID = ( int ) portGET_CORE_ID(); + + if( pxYieldSpinLock[ xCoreID ] ) { - spin_unlock(pxYieldSpinLock, ulYieldSpinLockSaveValue); - pxYieldSpinLock = NULL; + spin_lock_t * const pxTmpLock = pxYieldSpinLock[ xCoreID ]; + pxYieldSpinLock[ xCoreID ] = NULL; + spin_unlock( pxTmpLock, ulYieldSpinLockSaveValue[ xCoreID ] ); } #endif __asm volatile ( " cpsie i " ::: "memory" ); @@ -371,90 +530,209 @@ void vClearInterruptMaskFromISR( __attribute__( ( unused ) ) uint32_t ulMask ) ::: "memory" ); } + +/*-----------------------------------------------------------*/ + +void vYieldCore( int xCoreID ) +{ + /* Remove warning if configASSERT is not defined. + * xCoreID is not used in this function due to this is a dual-core system. The yielding core must be different from the current core. */ + ( void ) xCoreID; + + configASSERT( xCoreID != ( int ) portGET_CORE_ID() ); + + #if portRUNNING_ON_BOTH_CORES + + /* Non blocking, will cause interrupt on other core if the queue isn't already full, + * in which case an IRQ must be pending */ + sio_hw->fifo_wr = 0; + #endif +} + /*-----------------------------------------------------------*/ void xPortPendSVHandler( void ) { /* This is a naked function. */ - - __asm volatile - ( - " .syntax unified \n" - " mrs r0, psp \n" - " \n" - " ldr r3, pxCurrentTCBConst2 \n"/* Get the location of the current TCB. */ - " ldr r2, [r3] \n" - " \n" - " subs r0, r0, #32 \n"/* Make space for the remaining low registers. */ - " str r0, [r2] \n"/* Save the new top of stack. */ - " stmia r0!, {r4-r7} \n"/* Store the low registers that are not saved automatically. */ - " mov r4, r8 \n"/* Store the high registers. */ - " mov r5, r9 \n" - " mov r6, r10 \n" - " mov r7, r11 \n" - " stmia r0!, {r4-r7} \n" - #if portUSE_DIVIDER_SAVE_RESTORE - " movs r2, #0xd \n"/* Store the divider state. */ - " lsls r2, #28 \n" - /* We expect that the divider is ready at this point (which is - * necessary to safely save/restore), because: - * a) if we have not been interrupted since we entered this method, - * then >8 cycles have clearly passed, so the divider is done - * b) if we were interrupted in the interim, then any "safe" - i.e. - * does the right thing in an IRQ - use of the divider should - * have waited for any in-process divide to complete, saved and - * then fully restored the result, thus the result is ready in - * that case too. */ - " ldr r4, [r2, #0x60] \n"/* SIO_DIV_UDIVIDEND_OFFSET */ - " ldr r5, [r2, #0x64] \n"/* SIO_DIV_UDIVISOR_OFFSET */ - " ldr r6, [r2, #0x74] \n"/* SIO_DIV_REMAINDER_OFFSET */ - " ldr r7, [r2, #0x70] \n"/* SIO_DIV_QUOTIENT_OFFSET */ - /* We actually save the divider state in the 4 words below - * our recorded stack pointer, so as not to disrupt the stack - * frame expected by debuggers - this is addressed by - * portEXTRA_STACK_SIZE */ - " subs r0, r0, #48 \n" - " stmia r0!, {r4-r7} \n" - #endif /* portUSE_DIVIDER_SAVE_RESTORE */ - " push {r3, r14} \n" - " cpsid i \n" - " bl vTaskSwitchContext \n" - " cpsie i \n" - " pop {r2, r3} \n"/* lr goes in r3. r2 now holds tcb pointer. */ - " \n" - " ldr r1, [r2] \n" - " ldr r0, [r1] \n"/* The first item in pxCurrentTCB is the task top of stack. */ - " adds r0, r0, #16 \n"/* Move to the high registers. */ - " ldmia r0!, {r4-r7} \n"/* Pop the high registers. */ - " mov r8, r4 \n" - " mov r9, r5 \n" - " mov r10, r6 \n" - " mov r11, r7 \n" - " \n" - " msr psp, r0 \n"/* Remember the new top of stack for the task. */ - " \n" - #if portUSE_DIVIDER_SAVE_RESTORE - " movs r2, #0xd \n"/* Pop the divider state. */ - " lsls r2, #28 \n" - " subs r0, r0, #48 \n"/* Go back for the divider state */ - " ldmia r0!, {r4-r7} \n"/* Pop the divider state. */ - /* Note always restore via SIO_DIV_UDIVI*, because we will overwrite the - * results stopping the calculation anyway, however the sign of results - * is adjusted by the h/w at read time based on whether the last started - * division was signed and the inputs' signs differed */ - " str r4, [r2, #0x60] \n"/* SIO_DIV_UDIVIDEND_OFFSET */ - " str r5, [r2, #0x64] \n"/* SIO_DIV_UDIVISOR_OFFSET */ - " str r6, [r2, #0x74] \n"/* SIO_DIV_REMAINDER_OFFSET */ - " str r7, [r2, #0x70] \n"/* SIO_DIV_QUOTIENT_OFFSET */ - #else - " subs r0, r0, #32 \n"/* Go back for the low registers that are not automatically restored. */ - #endif /* portUSE_DIVIDER_SAVE_RESTORE */ - " ldmia r0!, {r4-r7} \n"/* Pop low registers. */ - " \n" - " bx r3 \n" - " .align 4 \n" - "pxCurrentTCBConst2: .word pxCurrentTCB \n" - ); + #if ( configNUMBER_OF_CORES == 1 ) + __asm volatile + ( + " .syntax unified \n" + " mrs r0, psp \n" + " \n" + " ldr r3, pxCurrentTCBConst2 \n" /* Get the location of the current TCB. */ + " ldr r2, [r3] \n" + " \n" + " subs r0, r0, #32 \n" /* Make space for the remaining low registers. */ + " str r0, [r2] \n" /* Save the new top of stack. */ + " stmia r0!, {r4-r7} \n" /* Store the low registers that are not saved automatically. */ + " mov r4, r8 \n" /* Store the high registers. */ + " mov r5, r9 \n" + " mov r6, r10 \n" + " mov r7, r11 \n" + " stmia r0!, {r4-r7} \n" + #if portUSE_DIVIDER_SAVE_RESTORE + " movs r2, #0xd \n" /* Store the divider state. */ + " lsls r2, #28 \n" + + /* We expect that the divider is ready at this point (which is + * necessary to safely save/restore), because: + * a) if we have not been interrupted since we entered this method, + * then >8 cycles have clearly passed, so the divider is done + * b) if we were interrupted in the interim, then any "safe" - i.e. + * does the right thing in an IRQ - use of the divider should + * have waited for any in-process divide to complete, saved and + * then fully restored the result, thus the result is ready in + * that case too. */ + " ldr r4, [r2, #0x60] \n" /* SIO_DIV_UDIVIDEND_OFFSET */ + " ldr r5, [r2, #0x64] \n" /* SIO_DIV_UDIVISOR_OFFSET */ + " ldr r6, [r2, #0x74] \n" /* SIO_DIV_REMAINDER_OFFSET */ + " ldr r7, [r2, #0x70] \n" /* SIO_DIV_QUOTIENT_OFFSET */ + + /* We actually save the divider state in the 4 words below + * our recorded stack pointer, so as not to disrupt the stack + * frame expected by debuggers - this is addressed by + * portEXTRA_STACK_SIZE */ + " subs r0, r0, #48 \n" + " stmia r0!, {r4-r7} \n" + #endif /* portUSE_DIVIDER_SAVE_RESTORE */ + " push {r3, r14} \n" + " cpsid i \n" + " bl vTaskSwitchContext \n" + " cpsie i \n" + " pop {r2, r3} \n" /* lr goes in r3. r2 now holds tcb pointer. */ + " \n" + " ldr r1, [r2] \n" + " ldr r0, [r1] \n" /* The first item in pxCurrentTCB is the task top of stack. */ + " adds r0, r0, #16 \n" /* Move to the high registers. */ + " ldmia r0!, {r4-r7} \n" /* Pop the high registers. */ + " mov r8, r4 \n" + " mov r9, r5 \n" + " mov r10, r6 \n" + " mov r11, r7 \n" + " \n" + " msr psp, r0 \n" /* Remember the new top of stack for the task. */ + " \n" + #if portUSE_DIVIDER_SAVE_RESTORE + " movs r2, #0xd \n" /* Pop the divider state. */ + " lsls r2, #28 \n" + " subs r0, r0, #48 \n" /* Go back for the divider state */ + " ldmia r0!, {r4-r7} \n" /* Pop the divider state. */ + + /* Note always restore via SIO_DIV_UDIVI*, because we will overwrite the + * results stopping the calculation anyway, however the sign of results + * is adjusted by the h/w at read time based on whether the last started + * division was signed and the inputs' signs differed */ + " str r4, [r2, #0x60] \n" /* SIO_DIV_UDIVIDEND_OFFSET */ + " str r5, [r2, #0x64] \n" /* SIO_DIV_UDIVISOR_OFFSET */ + " str r6, [r2, #0x74] \n" /* SIO_DIV_REMAINDER_OFFSET */ + " str r7, [r2, #0x70] \n" /* SIO_DIV_QUOTIENT_OFFSET */ + #else /* if portUSE_DIVIDER_SAVE_RESTORE */ + " subs r0, r0, #32 \n" /* Go back for the low registers that are not automatically restored. */ + #endif /* portUSE_DIVIDER_SAVE_RESTORE */ + " ldmia r0!, {r4-r7} \n" /* Pop low registers. */ + " \n" + " bx r3 \n" + " .align 4 \n" + "pxCurrentTCBConst2: .word pxCurrentTCB \n" + ); + #else /* if ( configNUMBER_OF_CORES == 1 ) */ + __asm volatile + ( + " .syntax unified \n" + " mrs r1, psp \n" + " \n" + " adr r0, ulAsmLocals2 \n" /* Get the location of the current TCB for the current core. */ + " ldmia r0!, {r2, r3} \n" + #if portRUNNING_ON_BOTH_CORES + " ldr r0, [r2] \n" /* r0 = Core number */ + " lsls r0, r0, #2 \n" + " adds r3, r0 \n" /* r3 = &pxCurrentTCBs[get_core_num()] */ + #else + " \n" /* r3 = &pxCurrentTCBs[0] */ + #endif /* portRUNNING_ON_BOTH_CORES */ + " ldr r0, [r3] \n" /* r0 = pxCurrentTCB */ + " \n" + " subs r1, r1, #32 \n" /* Make space for the remaining low registers. */ + " str r1, [r0] \n" /* Save the new top of stack. */ + " stmia r1!, {r4-r7} \n" /* Store the low registers that are not saved automatically. */ + " mov r4, r8 \n" /* Store the high registers. */ + " mov r5, r9 \n" + " mov r6, r10 \n" + " mov r7, r11 \n" + " stmia r1!, {r4-r7} \n" + #if portUSE_DIVIDER_SAVE_RESTORE + + /* We expect that the divider is ready at this point (which is + * necessary to safely save/restore), because: + * a) if we have not been interrupted since we entered this method, + * then >8 cycles have clearly passed, so the divider is done + * b) if we were interrupted in the interim, then any "safe" - i.e. + * does the right thing in an IRQ - use of the divider should + * have waited for any in-process divide to complete, saved and + * then fully restored the result, thus the result is ready in + * that case too. */ + " ldr r4, [r2, #0x60] \n" /* SIO_DIV_UDIVIDEND_OFFSET */ + " ldr r5, [r2, #0x64] \n" /* SIO_DIV_UDIVISOR_OFFSET */ + " ldr r6, [r2, #0x74] \n" /* SIO_DIV_REMAINDER_OFFSET */ + " ldr r7, [r2, #0x70] \n" /* SIO_DIV_QUOTIENT_OFFSET */ + + /* We actually save the divider state in the 4 words below + * our recorded stack pointer, so as not to disrupt the stack + * frame expected by debuggers - this is addressed by + * portEXTRA_STACK_SIZE */ + " subs r1, r1, #48 \n" + " stmia r1!, {r4-r7} \n" + #endif /* portUSE_DIVIDER_SAVE_RESTORE */ + #if portRUNNING_ON_BOTH_CORES + " ldr r0, [r2] \n" /* r0 = Core number */ + #else + " movs r0, #0 \n" + #endif /* portRUNNING_ON_BOTH_CORES */ + " push {r3, r14} \n" + " cpsid i \n" + " bl vTaskSwitchContext \n" + " cpsie i \n" + " pop {r2, r3} \n" /* lr goes in r3. r2 now holds tcb pointer. */ + " \n" + " ldr r1, [r2] \n" + " ldr r0, [r1] \n" /* The first item in pxCurrentTCB is the task top of stack. */ + " adds r0, r0, #16 \n" /* Move to the high registers. */ + " ldmia r0!, {r4-r7} \n" /* Pop the high registers. */ + " mov r8, r4 \n" + " mov r9, r5 \n" + " mov r10, r6 \n" + " mov r11, r7 \n" + " \n" + " msr psp, r0 \n" /* Remember the new top of stack for the task. */ + " \n" + #if portUSE_DIVIDER_SAVE_RESTORE + " movs r2, #0xd \n" /* Pop the divider state. */ + " lsls r2, #28 \n" + " subs r0, r0, #48 \n" /* Go back for the divider state */ + " ldmia r0!, {r4-r7} \n" /* Pop the divider state. */ + + /* Note always restore via SIO_DIV_UDIVI*, because we will overwrite the + * results stopping the calculation anyway, however the sign of results + * is adjusted by the h/w at read time based on whether the last started + * division was signed and the inputs' signs differed */ + " str r4, [r2, #0x60] \n" /* SIO_DIV_UDIVIDEND_OFFSET */ + " str r5, [r2, #0x64] \n" /* SIO_DIV_UDIVISOR_OFFSET */ + " str r6, [r2, #0x74] \n" /* SIO_DIV_REMAINDER_OFFSET */ + " str r7, [r2, #0x70] \n" /* SIO_DIV_QUOTIENT_OFFSET */ + #else /* if portUSE_DIVIDER_SAVE_RESTORE */ + " subs r0, r0, #32 \n" /* Go back for the low registers that are not automatically restored. */ + #endif /* portUSE_DIVIDER_SAVE_RESTORE */ + " ldmia r0!, {r4-r7} \n" /* Pop low registers. */ + " \n" + " bx r3 \n" + " \n" + " .align 4 \n" + "ulAsmLocals2: \n" + " .word 0xD0000000 \n" /* SIO */ + " .word pxCurrentTCBs \n" + ); + #endif /* if ( configNUMBER_OF_CORES == 1 ) */ } /*-----------------------------------------------------------*/ @@ -462,16 +740,22 @@ void xPortSysTickHandler( void ) { uint32_t ulPreviousMask; - ulPreviousMask = portSET_INTERRUPT_MASK_FROM_ISR(); + ulPreviousMask = taskENTER_CRITICAL_FROM_ISR(); + traceISR_ENTER(); { /* Increment the RTOS tick. */ if( xTaskIncrementTick() != pdFALSE ) { + traceISR_EXIT_TO_SCHEDULER(); /* Pend a context switch. */ portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; } + else + { + traceISR_EXIT(); + } } - portCLEAR_INTERRUPT_MASK_FROM_ISR( ulPreviousMask ); + taskEXIT_CRITICAL_FROM_ISR( ulPreviousMask ); } /*-----------------------------------------------------------*/ @@ -483,11 +767,11 @@ __attribute__( ( weak ) ) void vPortSetupTimerInterrupt( void ) { /* Calculate the constants required to configure the tick interrupt. */ #if ( configUSE_TICKLESS_IDLE == 1 ) - { - ulTimerCountsForOneTick = ( clock_get_hz(clk_sys) / configTICK_RATE_HZ ); - xMaximumPossibleSuppressedTicks = portMAX_24_BIT_NUMBER / ulTimerCountsForOneTick; - ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR; - } + { + ulTimerCountsForOneTick = ( clock_get_hz( clk_sys ) / configTICK_RATE_HZ ); + xMaximumPossibleSuppressedTicks = portMAX_24_BIT_NUMBER / ulTimerCountsForOneTick; + ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR; + } #endif /* configUSE_TICKLESS_IDLE */ /* Stop and reset the SysTick. */ @@ -672,32 +956,38 @@ __attribute__( ( weak ) ) void vPortSetupTimerInterrupt( void ) #if ( configSUPPORT_PICO_SYNC_INTEROP == 1 ) || ( configSUPPORT_PICO_TIME_INTEROP == 1 ) static TickType_t prvGetTicksToWaitBefore( absolute_time_t t ) { - int64_t xDelay = absolute_time_diff_us(get_absolute_time(), t); + int64_t xDelay = absolute_time_diff_us( get_absolute_time(), t ); const uint32_t ulTickPeriod = 1000000 / configTICK_RATE_HZ; + xDelay -= ulTickPeriod; + if( xDelay >= ulTickPeriod ) { return xDelay / ulTickPeriod; } + return 0; } -#endif +#endif /* if ( configSUPPORT_PICO_SYNC_INTEROP == 1 ) || ( configSUPPORT_PICO_TIME_INTEROP == 1 ) */ #if ( configSUPPORT_PICO_SYNC_INTEROP == 1 ) uint32_t ulPortLockGetCurrentOwnerId() { - if( portIS_FREE_RTOS_CORE()) + if( portIS_FREE_RTOS_CORE() ) { uint32_t exception = __get_current_exception(); + if( !exception ) { return ( uintptr_t ) xTaskGetCurrentTaskHandle(); } + /* Note: since ROM as at 0x00000000, these can't be confused with * valid task handles (pointers) in RAM */ /* We make all exception handler/core combinations distinct owners */ return get_core_num() + exception * 2; } + /* Note: since ROM as at 0x00000000, this can't be confused with * valid task handles (pointers) in RAM */ return get_core_num(); @@ -706,10 +996,11 @@ __attribute__( ( weak ) ) void vPortSetupTimerInterrupt( void ) static inline EventBits_t prvGetEventGroupBit( spin_lock_t * spinLock ) { uint32_t ulBit; + #if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS ) - ulBit = 1u << (spin_lock_get_num(spinLock) & 0x7u); + ulBit = 1u << ( spin_lock_get_num( spinLock ) & 0x7u ); #elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS ) - ulBit = 1u << spin_lock_get_num(spinLock); + ulBit = 1u << spin_lock_get_num( spinLock ); /* reduce to range 0-24 */ ulBit |= ulBit << 8u; ulBit >>= 8u; @@ -720,43 +1011,52 @@ __attribute__( ( weak ) ) void vPortSetupTimerInterrupt( void ) static inline EventBits_t prvGetAllEventGroupBits() { #if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS ) - return (EventBits_t) 0xffu; + return ( EventBits_t ) 0xffu; #elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS ) return ( EventBits_t ) 0xffffffu; #endif /* configTICK_TYPE_WIDTH_IN_BITS */ } - void vPortLockInternalSpinUnlockWithWait( struct lock_core * pxLock, uint32_t ulSave ) + void vPortLockInternalSpinUnlockWithWait( struct lock_core * pxLock, + uint32_t ulSave ) { configASSERT( !portCHECK_IF_IN_ISR() ); + + /* note no need to check LIB_PICO_MULTICORE, as this is always returns true if that is not defined */ if( !portIS_FREE_RTOS_CORE() ) { - spin_unlock(pxLock->spin_lock, ulSave ); + spin_unlock( pxLock->spin_lock, ulSave ); __wfe(); } else { - configASSERT( pxYieldSpinLock == NULL ); - - // we want to hold the lock until the event bits have been set; since interrupts are currently disabled - // by the spinlock, we can defer until portENABLE_INTERRUPTS is called which is always called when - // the scheduler is unlocked during this call - configASSERT(pxLock->spin_lock); - pxYieldSpinLock = pxLock->spin_lock; - ulYieldSpinLockSaveValue = ulSave; - xEventGroupWaitBits( xEventGroup, prvGetEventGroupBit(pxLock->spin_lock), - pdTRUE, pdFALSE, portMAX_DELAY); + configASSERT( pxYieldSpinLock[ portGET_CORE_ID() ] == NULL ); + + /* we want to hold the lock until the event bits have been set; since interrupts are currently disabled */ + /* by the spinlock, we can defer until portENABLE_INTERRUPTS is called which is always called when */ + /* the scheduler is unlocked during this call */ + configASSERT( pxLock->spin_lock ); + int xCoreID = ( int ) portGET_CORE_ID(); + pxYieldSpinLock[ xCoreID ] = pxLock->spin_lock; + ulYieldSpinLockSaveValue[ xCoreID ] = ulSave; + xEventGroupWaitBits( xEventGroup, prvGetEventGroupBit( pxLock->spin_lock ), + pdTRUE, pdFALSE, portMAX_DELAY ); } } - void vPortLockInternalSpinUnlockWithNotify( struct lock_core *pxLock, uint32_t ulSave ) { - EventBits_t uxBits = prvGetEventGroupBit(pxLock->spin_lock ); - if (portIS_FREE_RTOS_CORE()) { + void vPortLockInternalSpinUnlockWithNotify( struct lock_core * pxLock, + uint32_t ulSave ) + { + EventBits_t uxBits = prvGetEventGroupBit( pxLock->spin_lock ); + + if( portIS_FREE_RTOS_CORE() ) + { #if LIB_PICO_MULTICORE /* signal an event in case a regular core is waiting */ __sev(); #endif - spin_unlock(pxLock->spin_lock, ulSave ); + spin_unlock( pxLock->spin_lock, ulSave ); + if( !portCHECK_IF_IN_ISR() ) { xEventGroupSetBits( xEventGroup, uxBits ); @@ -771,61 +1071,67 @@ __attribute__( ( weak ) ) void vPortSetupTimerInterrupt( void ) else { __sev(); - #if ( LIB_PICO_MULTICORE == 1) + #if ( portRUNNING_ON_BOTH_CORES == 0 ) + /* We could sent the bits across the FIFO which would have required us to block here if the FIFO was full, * or we could have just set all bits on the other side, however it seems reasonable instead to take * the hit of another spin lock to protect an accurate bit set. */ if( pxCrossCoreSpinLock != pxLock->spin_lock ) { - spin_lock_unsafe_blocking(pxCrossCoreSpinLock); + spin_lock_unsafe_blocking( pxCrossCoreSpinLock ); uxCrossCoreEventBits |= uxBits; - spin_unlock_unsafe(pxCrossCoreSpinLock); + spin_unlock_unsafe( pxCrossCoreSpinLock ); } else { uxCrossCoreEventBits |= uxBits; } + /* This causes fifo irq on the other (FreeRTOS) core which will do the set the event bits */ sio_hw->fifo_wr = 0; - #endif /* LIB_PICO_MULTICORE */ - spin_unlock(pxLock->spin_lock, ulSave); + #endif /* portRUNNING_ON_BOTH_CORES == 0 */ + spin_unlock( pxLock->spin_lock, ulSave ); } } - bool xPortLockInternalSpinUnlockWithBestEffortWaitOrTimeout( struct lock_core * pxLock, uint32_t ulSave, absolute_time_t uxUntil ) + bool xPortLockInternalSpinUnlockWithBestEffortWaitOrTimeout( struct lock_core * pxLock, + uint32_t ulSave, + absolute_time_t uxUntil ) { configASSERT( !portCHECK_IF_IN_ISR() ); - // note no need to check LIB_PICO_MULTICORE, as this is always returns true if that is not defined + + /* note no need to check LIB_PICO_MULTICORE, as this is always returns true if that is not defined */ if( !portIS_FREE_RTOS_CORE() ) { - spin_unlock(pxLock->spin_lock, ulSave); - return best_effort_wfe_or_timeout(uxUntil); + spin_unlock( pxLock->spin_lock, ulSave ); + return best_effort_wfe_or_timeout( uxUntil ); } else { - configASSERT( pxYieldSpinLock == NULL ); + configASSERT( portIS_FREE_RTOS_CORE() ); + configASSERT( pxYieldSpinLock[ portGET_CORE_ID() ] == NULL ); TickType_t uxTicksToWait = prvGetTicksToWaitBefore( uxUntil ); + if( uxTicksToWait ) { /* We want to hold the lock until the event bits have been set; since interrupts are currently disabled * by the spinlock, we can defer until portENABLE_INTERRUPTS is called which is always called when * the scheduler is unlocked during this call */ - configASSERT(pxLock->spin_lock); - pxYieldSpinLock = pxLock->spin_lock; - ulYieldSpinLockSaveValue = ulSave; + configASSERT( pxLock->spin_lock ); + int xCoreID = ( int ) portGET_CORE_ID(); + pxYieldSpinLock[ xCoreID ] = pxLock->spin_lock; + ulYieldSpinLockSaveValue[ xCoreID ] = ulSave; xEventGroupWaitBits( xEventGroup, - prvGetEventGroupBit(pxLock->spin_lock), pdTRUE, + prvGetEventGroupBit( pxLock->spin_lock ), pdTRUE, pdFALSE, uxTicksToWait ); - /* sanity check that interrupts were disabled, then re-enabled during the call, which will have - * taken care of the yield */ - configASSERT( pxYieldSpinLock == NULL ); } else { spin_unlock( pxLock->spin_lock, ulSave ); } - if ( time_reached( uxUntil ) ) + + if( time_reached( uxUntil ) ) { return true; } @@ -839,21 +1145,22 @@ __attribute__( ( weak ) ) void vPortSetupTimerInterrupt( void ) } } - #if ( configSUPPORT_PICO_SYNC_INTEROP == 1) + #if ( configSUPPORT_PICO_SYNC_INTEROP == 1 ) /* runs before main */ - static void __attribute__((constructor)) prvRuntimeInitializer( void ) + static void __attribute__( ( constructor ) ) prvRuntimeInitializer( void ) { /* This must be done even before the scheduler is started, as the spin lock * is used by the overrides of the SDK wait/notify primitives */ - #if ( LIB_PICO_MULTICORE == 1 ) + #if ( portRUNNING_ON_BOTH_CORES == 0 ) pxCrossCoreSpinLock = spin_lock_instance( next_striped_spin_lock_num() ); #endif /* portRUNNING_ON_BOTH_CORES */ /* The event group is not used prior to scheduler init, but is initialized * here to since it logically belongs with the spin lock */ #if ( configSUPPORT_STATIC_ALLOCATION == 1 ) - xEventGroup = xEventGroupCreateStatic(&xStaticEventGroup); + xEventGroup = xEventGroupCreateStatic( &xStaticEventGroup ); #else + /* Note that it is slightly dubious calling this here before the scheduler is initialized, * however the only thing it touches is the allocator which then calls vPortEnterCritical * and vPortExitCritical, and allocating here saves us checking the one time initialized variable in @@ -861,16 +1168,17 @@ __attribute__( ( weak ) ) void vPortSetupTimerInterrupt( void ) xEventGroup = xEventGroupCreate(); #endif /* configSUPPORT_STATIC_ALLOCATION */ } - #endif + #endif /* if ( configSUPPORT_PICO_SYNC_INTEROP == 1 ) */ #endif /* configSUPPORT_PICO_SYNC_INTEROP */ #if ( configSUPPORT_PICO_TIME_INTEROP == 1 ) void xPortSyncInternalYieldUntilBefore( absolute_time_t t ) { - TickType_t uxTicksToWait = prvGetTicksToWaitBefore(t); + TickType_t uxTicksToWait = prvGetTicksToWaitBefore( t ); + if( uxTicksToWait ) { - vTaskDelay(uxTicksToWait); + vTaskDelay( uxTicksToWait ); } } #endif /* configSUPPORT_PICO_TIME_INTEROP */ diff --git a/Source/portable/ThirdParty/GCC/Xtensa_ESP32/include/FreeRTOSConfig_arch.h b/Source/portable/ThirdParty/GCC/Xtensa_ESP32/include/FreeRTOSConfig_arch.h index 822edb895..7a4e2f62f 100644 --- a/Source/portable/ThirdParty/GCC/Xtensa_ESP32/include/FreeRTOSConfig_arch.h +++ b/Source/portable/ThirdParty/GCC/Xtensa_ESP32/include/FreeRTOSConfig_arch.h @@ -5,8 +5,9 @@ * * SPDX-FileContributor: 2016-2022 Espressif Systems (Shanghai) CO LTD */ + /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of @@ -39,29 +40,30 @@ #include "sdkconfig.h" /* enable use of optimized task selection by the scheduler */ -#if defined (CONFIG_FREERTOS_OPTIMIZED_SCHEDULER) && !defined(configUSE_PORT_OPTIMISED_TASK_SELECTION) -#define configUSE_PORT_OPTIMISED_TASK_SELECTION 1 +#if defined( CONFIG_FREERTOS_OPTIMIZED_SCHEDULER ) && !defined( configUSE_PORT_OPTIMISED_TASK_SELECTION ) + #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1 #endif -#define XT_USE_THREAD_SAFE_CLIB 0 +#define XT_USE_THREAD_SAFE_CLIB 0 #undef XT_USE_SWPRI #if CONFIG_FREERTOS_CORETIMER_0 -#define XT_TIMER_INDEX 0 + #define XT_TIMER_INDEX 0 #elif CONFIG_FREERTOS_CORETIMER_1 -#define XT_TIMER_INDEX 1 + #define XT_TIMER_INDEX 1 #endif #ifndef __ASSEMBLER__ + /** * This function is defined to provide a deprecation warning whenever * XT_CLOCK_FREQ macro is used. * Update the code to use esp_clk_cpu_freq function instead. * @return current CPU clock frequency, in Hz */ -int xt_clock_freq(void) __attribute__((deprecated)); + int xt_clock_freq( void ) __attribute__( ( deprecated ) ); -#define XT_CLOCK_FREQ (xt_clock_freq()) + #define XT_CLOCK_FREQ ( xt_clock_freq() ) #endif // __ASSEMBLER__ @@ -70,47 +72,50 @@ int xt_clock_freq(void) __attribute__((deprecated)); /* configASSERT behaviour */ #ifndef __ASSEMBLER__ -#include -#include "esp_rom_sys.h" -#if CONFIG_IDF_TARGET_ESP32 -#include "esp32/rom/ets_sys.h" // will be removed in idf v5.0 -#elif CONFIG_IDF_TARGET_ESP32S2 -#include "esp32s2/rom/ets_sys.h" -#elif CONFIG_IDF_TARGET_ESP32S3 -#include "esp32s3/rom/ets_sys.h" -#endif + #include + #include "esp_rom_sys.h" + #if CONFIG_IDF_TARGET_ESP32 + #include "esp32/rom/ets_sys.h" /* will be removed in idf v5.0 */ + #elif CONFIG_IDF_TARGET_ESP32S2 + #include "esp32s2/rom/ets_sys.h" + #elif CONFIG_IDF_TARGET_ESP32S3 + #include "esp32s3/rom/ets_sys.h" + #endif #endif // __ASSEMBLER__ -// If CONFIG_FREERTOS_ASSERT_DISABLE is set then configASSERT is defined empty later in FreeRTOS.h and the macro -// configASSERT_DEFINED remains unset (meaning some warnings are avoided) +/* If CONFIG_FREERTOS_ASSERT_DISABLE is set then configASSERT is defined empty later in FreeRTOS.h and the macro */ +/* configASSERT_DEFINED remains unset (meaning some warnings are avoided) */ #ifdef configASSERT -#undef configASSERT -#if defined(CONFIG_FREERTOS_ASSERT_FAIL_PRINT_CONTINUE) -#define configASSERT(a) if (unlikely(!(a))) { \ - esp_rom_printf("%s:%d (%s)- assert failed!\n", __FILE__, __LINE__, \ - __FUNCTION__); \ + #undef configASSERT + #if defined( CONFIG_FREERTOS_ASSERT_FAIL_PRINT_CONTINUE ) + #define configASSERT( a ) \ + if( unlikely( !( a ) ) ) { \ + esp_rom_printf( "%s:%d (%s)- assert failed!\n", __FILE__, __LINE__, \ + __FUNCTION__ ); \ } -#elif defined(CONFIG_FREERTOS_ASSERT_FAIL_ABORT) -#define configASSERT(a) assert(a) -#endif -#endif + #elif defined( CONFIG_FREERTOS_ASSERT_FAIL_ABORT ) + #define configASSERT( a ) assert( a ) + #endif +#endif /* ifdef configASSERT */ #if CONFIG_FREERTOS_ASSERT_ON_UNTESTED_FUNCTION -#define UNTESTED_FUNCTION() { esp_rom_printf("Untested FreeRTOS function %s\r\n", __FUNCTION__); configASSERT(false); } while(0) + #define UNTESTED_FUNCTION() \ + { esp_rom_printf( "Untested FreeRTOS function %s\r\n", __FUNCTION__ ); configASSERT( false ); } \ + while( 0 ) #else -#define UNTESTED_FUNCTION() + #define UNTESTED_FUNCTION() #endif -#define configXT_BOARD 1 /* Board mode */ -#define configXT_SIMULATOR 0 +#define configXT_BOARD 1 /* Board mode */ +#define configXT_SIMULATOR 0 /* The maximum interrupt priority from which FreeRTOS.org API functions can - be called. Only API functions that end in ...FromISR() can be used within - interrupts. */ + * be called. Only API functions that end in ...FromISR() can be used within + * interrupts. */ #define configMAX_SYSCALL_INTERRUPT_PRIORITY XCHAL_EXCM_LEVEL /* Stack alignment, architecture specifc. Must be a power of two. */ -#define configSTACK_ALIGNMENT 16 +#define configSTACK_ALIGNMENT 16 /* The Xtensa port uses a separate interrupt stack. Adjust the stack size @@ -119,16 +124,16 @@ int xt_clock_freq(void) __attribute__((deprecated)); * the stack for the 2nd CPU will be calculated using configISR_STACK_SIZE. */ #ifndef configISR_STACK_SIZE -#define configISR_STACK_SIZE ((CONFIG_FREERTOS_ISR_STACKSIZE + configSTACK_ALIGNMENT - 1) & (~(configSTACK_ALIGNMENT - 1))) + #define configISR_STACK_SIZE ( ( CONFIG_FREERTOS_ISR_STACKSIZE + configSTACK_ALIGNMENT - 1 ) & ( ~( configSTACK_ALIGNMENT - 1 ) ) ) #endif #ifndef __ASSEMBLER__ -#if CONFIG_APPTRACE_SV_ENABLE -extern uint32_t port_switch_flag[]; -#define os_task_switch_is_pended(_cpu_) (port_switch_flag[_cpu_]) -#else -#define os_task_switch_is_pended(_cpu_) (false) -#endif + #if CONFIG_APPTRACE_SV_ENABLE + extern uint32_t port_switch_flag[]; + #define os_task_switch_is_pended( _cpu_ ) ( port_switch_flag[ _cpu_ ] ) + #else + #define os_task_switch_is_pended( _cpu_ ) ( false ) + #endif #endif #endif // FREERTOS_CONFIG_XTENSA_H diff --git a/Source/portable/ThirdParty/GCC/Xtensa_ESP32/include/port_systick.h b/Source/portable/ThirdParty/GCC/Xtensa_ESP32/include/port_systick.h index 738b5a180..22f18ba52 100644 --- a/Source/portable/ThirdParty/GCC/Xtensa_ESP32/include/port_systick.h +++ b/Source/portable/ThirdParty/GCC/Xtensa_ESP32/include/port_systick.h @@ -15,7 +15,7 @@ /** * @brief Set up the SysTick interrupt */ -void vPortSetupTimer(void); +void vPortSetupTimer( void ); /* *INDENT-OFF* */ #ifdef __cplusplus diff --git a/Source/portable/ThirdParty/GCC/Xtensa_ESP32/include/portbenchmark.h b/Source/portable/ThirdParty/GCC/Xtensa_ESP32/include/portbenchmark.h index 4f14dc478..ad5c881d1 100644 --- a/Source/portable/ThirdParty/GCC/Xtensa_ESP32/include/portbenchmark.h +++ b/Source/portable/ThirdParty/GCC/Xtensa_ESP32/include/portbenchmark.h @@ -5,6 +5,7 @@ * * SPDX-FileContributor: 2016-2022 Espressif Systems (Shanghai) CO LTD */ + /* * Copyright (c) 2015-2019 Cadence Design Systems, Inc. * diff --git a/Source/portable/ThirdParty/GCC/Xtensa_ESP32/include/portmacro.h b/Source/portable/ThirdParty/GCC/Xtensa_ESP32/include/portmacro.h index 179b0f538..c9ea95f13 100644 --- a/Source/portable/ThirdParty/GCC/Xtensa_ESP32/include/portmacro.h +++ b/Source/portable/ThirdParty/GCC/Xtensa_ESP32/include/portmacro.h @@ -6,8 +6,9 @@ * * SPDX-FileContributor: 2016-2022 Espressif Systems (Shanghai) CO LTD */ + /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of @@ -75,23 +76,23 @@ #include /* required for XSHAL_CLIB */ #include #include "soc/spinlock.h" - #include "esp_timer.h" /* required for FreeRTOS run time stats */ + #include "esp_timer.h" /* required for FreeRTOS run time stats */ #include "esp_system.h" #include "esp_idf_version.h" #include "esp_heap_caps.h" - /* TODO: Resolve build warnings generated due to this header inclusion */ +/* TODO: Resolve build warnings generated due to this header inclusion */ #include "hal/cpu_hal.h" - /* TODO: These includes are not directly used in this file. They are kept into to prevent a breaking change. Remove these. */ +/* TODO: These includes are not directly used in this file. They are kept into to prevent a breaking change. Remove these. */ #include #include #include "soc/cpu.h" #include "soc/soc_memory_layout.h" -#if (ESP_IDF_VERSION >= ESP_IDF_VERSION_VAL(4, 2, 0)) - #include "soc/compare_set.h" -#endif /* ESP_IDF_VERSION >= ESP_IDF_VERSION_VAL(4, 2, 0) */ + #if ( ESP_IDF_VERSION >= ESP_IDF_VERSION_VAL( 4, 2, 0 ) ) + #include "soc/compare_set.h" + #endif /* ESP_IDF_VERSION >= ESP_IDF_VERSION_VAL(4, 2, 0) */ /*#include "xtensa_context.h" */ @@ -122,7 +123,7 @@ #if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS ) typedef uint16_t TickType_t; #define portMAX_DELAY ( TickType_t ) 0xffff - #elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS ) + #elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS ) typedef uint32_t TickType_t; #define portMAX_DELAY ( TickType_t ) 0xffffffffUL #else @@ -137,14 +138,14 @@ #include "esp_attr.h" /* "mux" data structure (spinlock) */ - typedef spinlock_t portMUX_TYPE; /**< Spinlock type used by FreeRTOS critical sections */ - #define portMUX_INITIALIZER_UNLOCKED SPINLOCK_INITIALIZER /**< Spinlock initializer */ - #define portMUX_FREE_VAL SPINLOCK_FREE /**< Spinlock is free. [refactor-todo] check if this is still required */ - #define portMUX_NO_TIMEOUT SPINLOCK_WAIT_FOREVER /**< When passed for 'timeout_cycles', spin forever if necessary. [refactor-todo] check if this is still required */ - #define portMUX_TRY_LOCK SPINLOCK_NO_WAIT /**< Try to acquire the spinlock a single time only. [refactor-todo] check if this is still required */ - #define portMUX_INITIALIZE(mux) spinlock_initialize(mux) /*< Initialize a spinlock to its unlocked state */ + typedef spinlock_t portMUX_TYPE; /**< Spinlock type used by FreeRTOS critical sections */ + #define portMUX_INITIALIZER_UNLOCKED SPINLOCK_INITIALIZER /**< Spinlock initializer */ + #define portMUX_FREE_VAL SPINLOCK_FREE /**< Spinlock is free. [refactor-todo] check if this is still required */ + #define portMUX_NO_TIMEOUT SPINLOCK_WAIT_FOREVER /**< When passed for 'timeout_cycles', spin forever if necessary. [refactor-todo] check if this is still required */ + #define portMUX_TRY_LOCK SPINLOCK_NO_WAIT /**< Try to acquire the spinlock a single time only. [refactor-todo] check if this is still required */ + #define portMUX_INITIALIZE( mux ) spinlock_initialize( mux ) /*< Initialize a spinlock to its unlocked state */ - #define portCRITICAL_NESTING_IN_TCB 1 + #define portCRITICAL_NESTING_IN_TCB 1 /* * Modifications to portENTER_CRITICAL. @@ -223,8 +224,8 @@ } \ } while( 0 ) - #define portASSERT_IF_IN_ISR() vPortAssertIfInISR() - void vPortAssertIfInISR(void); + #define portASSERT_IF_IN_ISR() vPortAssertIfInISR() + void vPortAssertIfInISR( void ); /* Critical section management. NW-TODO: replace XTOS_SET_INTLEVEL with more efficient version, if any? */ /* These cannot be nested. They should be used with a lot of care and cannot be called from interrupt level. */ @@ -239,6 +240,7 @@ static inline UBaseType_t __attribute__( ( always_inline ) ) xPortSetInterruptMaskFromISR( void ) { UBaseType_t prev_int_level = XTOS_SET_INTLEVEL( XCHAL_EXCM_LEVEL ); + portbenchmarkINTERRUPT_DISABLE(); return prev_int_level; } @@ -255,11 +257,11 @@ /*Because the ROM routines don't necessarily handle a stack in external RAM correctly, we force */ /*the stack memory to always be internal. */ - #define portTcbMemoryCaps (MALLOC_CAP_INTERNAL|MALLOC_CAP_8BIT) - #define portStackMemoryCaps (MALLOC_CAP_INTERNAL|MALLOC_CAP_8BIT) + #define portTcbMemoryCaps ( MALLOC_CAP_INTERNAL | MALLOC_CAP_8BIT ) + #define portStackMemoryCaps ( MALLOC_CAP_INTERNAL | MALLOC_CAP_8BIT ) - #define pvPortMallocTcbMem(size) heap_caps_malloc(size, portTcbMemoryCaps) - #define pvPortMallocStackMem(size) heap_caps_malloc(size, portStackMemoryCaps) + #define pvPortMallocTcbMem( size ) heap_caps_malloc( size, portTcbMemoryCaps ) + #define pvPortMallocStackMem( size ) heap_caps_malloc( size, portStackMemoryCaps ) /*xTaskCreateStatic uses these functions to check incoming memory. */ #define portVALID_TCB_MEM( ptr ) ( esp_ptr_internal( ptr ) && esp_ptr_byte_accessible( ptr ) ) @@ -278,18 +280,18 @@ * *bitwise inverse* of the old mem if the mem wasn't written. This doesn't seem to happen on the * ESP32 (portMUX assertions would fail). */ - static inline void uxPortCompareSet( volatile uint32_t * addr, - uint32_t compare, - uint32_t * set ) - { - #if (ESP_IDF_VERSION < ESP_IDF_VERSION_VAL(4, 2, 0)) + static inline void uxPortCompareSet( volatile uint32_t * addr, + uint32_t compare, + uint32_t * set ) + { + #if ( ESP_IDF_VERSION < ESP_IDF_VERSION_VAL( 4, 2, 0 ) ) __asm__ __volatile__ ( "WSR %2,SCOMPARE1 \n" "S32C1I %0, %1, 0 \n" : "=r" ( *set ) : "r" ( addr ), "r" ( compare ), "0" ( *set ) ); - #else + #else #if ( XCHAL_HAVE_S32C1I > 0 ) __asm__ __volatile__ ( "WSR %2,SCOMPARE1 \n" @@ -316,21 +318,23 @@ *set = old_value; #endif /* if ( XCHAL_HAVE_S32C1I > 0 ) */ - #endif /* #if (ESP_IDF_VERSION >= ESP_IDF_VERSION_VAL(4, 2, 0)) */ - } + #endif /* #if (ESP_IDF_VERSION >= ESP_IDF_VERSION_VAL(4, 2, 0)) */ + } - #if (ESP_IDF_VERSION < ESP_IDF_VERSION_VAL(4, 2, 0)) + #if ( ESP_IDF_VERSION < ESP_IDF_VERSION_VAL( 4, 2, 0 ) ) void uxPortCompareSetExtram( volatile uint32_t * addr, uint32_t compare, uint32_t * set ); - #else - static inline void uxPortCompareSetExtram(volatile uint32_t *addr, uint32_t compare, uint32_t *set) + #else + static inline void uxPortCompareSetExtram( volatile uint32_t * addr, + uint32_t compare, + uint32_t * set ) { - #if defined(CONFIG_SPIRAM) - compare_and_set_extram(addr, compare, set); - #endif + #if defined( CONFIG_SPIRAM ) + compare_and_set_extram( addr, compare, set ); + #endif } - #endif + #endif /* if ( ESP_IDF_VERSION < ESP_IDF_VERSION_VAL( 4, 2, 0 ) ) */ /*-----------------------------------------------------------*/ @@ -348,15 +352,17 @@ #ifdef CONFIG_FREERTOS_RUN_TIME_STATS_USING_ESP_TIMER /* Coarse resolution time (us) */ - #define portALT_GET_RUN_TIME_COUNTER_VALUE( x ) do { x = ( uint32_t )esp_timer_get_time(); } while( 0 ) + #define portALT_GET_RUN_TIME_COUNTER_VALUE( x ) do { x = ( uint32_t ) esp_timer_get_time(); } while( 0 ) #endif /* Kernel utilities. */ void vPortYield( void ); - void vPortEvaluateYieldFromISR( int argc, ... ); + void vPortEvaluateYieldFromISR( int argc, + ... ); void _frxt_setup_switch( void ); + /* Macro to count number of arguments of a __VA_ARGS__ used to support portYIELD_FROM_ISR with, * or without arguments. The macro counts only 0 or 1 arguments. * @@ -366,26 +372,26 @@ * This allows users to compile their code with standard C++20 enabled instead of the GNU extension. * Below C++20, we haven't found any good alternative to using ##__VA_ARGS__. */ - #if defined( __cplusplus ) && ( __cplusplus > 201703L ) - #define portGET_ARGUMENT_COUNT(...) portGET_ARGUMENT_COUNT_INNER( 0 __VA_OPT__(,) __VA_ARGS__, 1 , 0 ) + #if defined( __cplusplus ) && ( __cplusplus > 201703L ) + #define portGET_ARGUMENT_COUNT( ... ) portGET_ARGUMENT_COUNT_INNER( 0 __VA_OPT__(, ) __VA_ARGS__, 1, 0 ) #else - #define portGET_ARGUMENT_COUNT(...) portGET_ARGUMENT_COUNT_INNER( 0, ##__VA_ARGS__, 1, 0 ) + #define portGET_ARGUMENT_COUNT( ... ) portGET_ARGUMENT_COUNT_INNER( 0, ## __VA_ARGS__, 1, 0 ) #endif - #define portGET_ARGUMENT_COUNT_INNER( zero, one, count, ... ) count + #define portGET_ARGUMENT_COUNT_INNER( zero, one, count, ... ) count _Static_assert( portGET_ARGUMENT_COUNT() == 0, "portGET_ARGUMENT_COUNT() result does not match for 0 arguments" ); _Static_assert( portGET_ARGUMENT_COUNT( 1 ) == 1, "portGET_ARGUMENT_COUNT() result does not match for 1 argument" ); - #define portYIELD() vPortYield() + #define portYIELD() vPortYield() /* The macro below could be used when passing a single argument, or without any argument, * it was developed to support both usages of portYIELD inside of an ISR. Any other usage form * might result in undesired behaviour */ - #if defined( __cplusplus ) && ( __cplusplus > 201703L ) - #define portYIELD_FROM_ISR(...) vPortEvaluateYieldFromISR( portGET_ARGUMENT_COUNT( __VA_ARGS__ ) __VA_OPT__( , ) __VA_ARGS__ ) + #if defined( __cplusplus ) && ( __cplusplus > 201703L ) + #define portYIELD_FROM_ISR( ... ) vPortEvaluateYieldFromISR( portGET_ARGUMENT_COUNT( __VA_ARGS__ ) __VA_OPT__(, ) __VA_ARGS__ ) #else - #define portYIELD_FROM_ISR(...) vPortEvaluateYieldFromISR( portGET_ARGUMENT_COUNT( __VA_ARGS__ ), ##__VA_ARGS__ ) + #define portYIELD_FROM_ISR( ... ) vPortEvaluateYieldFromISR( portGET_ARGUMENT_COUNT( __VA_ARGS__ ), ## __VA_ARGS__ ) #endif static inline BaseType_t xPortGetCoreID(); @@ -436,31 +442,31 @@ void _xt_coproc_release( volatile void * coproc_sa_base ); - /*-----------------------------------------------------------*/ +/*-----------------------------------------------------------*/ - #if (ESP_IDF_VERSION >= ESP_IDF_VERSION_VAL(4, 2, 0)) - /* Architecture specific optimisations. */ + #if ( ESP_IDF_VERSION >= ESP_IDF_VERSION_VAL( 4, 2, 0 ) ) + /* Architecture specific optimisations. */ - #if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 + #if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 - /* Check the configuration. */ - #if( configMAX_PRIORITIES > 32 ) - #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 different priorities as tasks that share a priority will time slice. - #endif +/* Check the configuration. */ + #if ( configMAX_PRIORITIES > 32 ) + #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 different priorities as tasks that share a priority will time slice. + #endif - /* Store/clear the ready priorities in a bit map. */ - #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) ) - #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) ) +/* Store/clear the ready priorities in a bit map. */ + #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) ) + #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) ) - /*-----------------------------------------------------------*/ +/*-----------------------------------------------------------*/ - #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31 - __builtin_clz( ( uxReadyPriorities ) ) ) + #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31 - __builtin_clz( ( uxReadyPriorities ) ) ) - #endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */ + #endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */ #endif /* ESP_IDF_VERSION >= ESP_IDF_VERSION_VAL(4, 2, 0) */ - /*-----------------------------------------------------------*/ +/*-----------------------------------------------------------*/ /* * Map to the memory management routines required for the port. @@ -474,7 +480,8 @@ #define xPortGetFreeHeapSize esp_get_free_heap_size #define xPortGetMinimumEverFreeHeapSize esp_get_minimum_free_heap_size -#if (ESP_IDF_VERSION < ESP_IDF_VERSION_VAL(4, 2, 0)) + #if ( ESP_IDF_VERSION < ESP_IDF_VERSION_VAL( 4, 2, 0 ) ) + /* * Send an interrupt to another core in order to make the task running * on it yield for a higher-priority task. @@ -482,7 +489,7 @@ void vPortYieldOtherCore( BaseType_t coreid ) PRIVILEGED_FUNCTION; -#endif /* ESP_IDF_VERSION < ESP_IDF_VERSION_VAL(4, 2, 0) */ + #endif /* ESP_IDF_VERSION < ESP_IDF_VERSION_VAL(4, 2, 0) */ /* * Callback to set a watchpoint on the end of the stack. Called every context switch to change the stack @@ -522,27 +529,27 @@ /* Multi-core: get current core ID */ static inline BaseType_t IRAM_ATTR xPortGetCoreID() { - return ( uint32_t )cpu_hal_get_core_id(); + return ( uint32_t ) cpu_hal_get_core_id(); } /* Get tick rate per second */ uint32_t xPortGetTickRateHz( void ); - static inline bool IRAM_ATTR xPortCanYield(void) + static inline bool IRAM_ATTR xPortCanYield( void ) { uint32_t ps_reg = 0; - //Get the current value of PS (processor status) register - RSR(PS, ps_reg); + /*Get the current value of PS (processor status) register */ + RSR( PS, ps_reg ); /* - * intlevel = (ps_reg & 0xf); - * excm = (ps_reg >> 4) & 0x1; - * CINTLEVEL is max(excm * EXCMLEVEL, INTLEVEL), where EXCMLEVEL is 3. - * However, just return true, only intlevel is zero. - */ + * intlevel = (ps_reg & 0xf); + * excm = (ps_reg >> 4) & 0x1; + * CINTLEVEL is max(excm * EXCMLEVEL, INTLEVEL), where EXCMLEVEL is 3. + * However, just return true, only intlevel is zero. + */ - return ((ps_reg & PS_INTLEVEL_MASK) == 0); + return( ( ps_reg & PS_INTLEVEL_MASK ) == 0 ); } /* porttrace */ diff --git a/Source/portable/ThirdParty/GCC/Xtensa_ESP32/include/xt_asm_utils.h b/Source/portable/ThirdParty/GCC/Xtensa_ESP32/include/xt_asm_utils.h index ba31b9c26..9660e49a9 100644 --- a/Source/portable/ThirdParty/GCC/Xtensa_ESP32/include/xt_asm_utils.h +++ b/Source/portable/ThirdParty/GCC/Xtensa_ESP32/include/xt_asm_utils.h @@ -8,7 +8,7 @@ /* File adapted to use on IDF FreeRTOS component, extracted * originally from zephyr RTOS code base: - * https://github.com/zephyrproject-rtos/zephyr/blob/dafd348/arch/xtensa/include/xtensa-asm2-s.h + * https://github.com/zephyrproject-rtos/zephyr/blob/dafd3485bf67880e667b6e9a758b0b64fb688d63/arch/xtensa/include/xtensa-asm2-s.h */ #ifndef __XT_ASM_UTILS_H @@ -67,9 +67,9 @@ rotw 3 and a4, a4, a4 rotw 2 -#else -#error Unrecognized XCHAL_NUM_AREGS -#endif -.endm +#else /* if XCHAL_NUM_AREGS == 64 */ + #error Unrecognized XCHAL_NUM_AREGS +#endif /* if XCHAL_NUM_AREGS == 64 */ + .endm -#endif +#endif /* ifndef __XT_ASM_UTILS_H */ diff --git a/Source/portable/ThirdParty/GCC/Xtensa_ESP32/include/xtensa_api.h b/Source/portable/ThirdParty/GCC/Xtensa_ESP32/include/xtensa_api.h index 511a9da3d..a9069d798 100644 --- a/Source/portable/ThirdParty/GCC/Xtensa_ESP32/include/xtensa_api.h +++ b/Source/portable/ThirdParty/GCC/Xtensa_ESP32/include/xtensa_api.h @@ -5,6 +5,7 @@ * * SPDX-FileContributor: 2016-2022 Espressif Systems (Shanghai) CO LTD */ + /* * Copyright (c) 2015-2019 Cadence Design Systems, Inc. * diff --git a/Source/portable/ThirdParty/GCC/Xtensa_ESP32/include/xtensa_config.h b/Source/portable/ThirdParty/GCC/Xtensa_ESP32/include/xtensa_config.h index 78ef67da8..635e8647a 100644 --- a/Source/portable/ThirdParty/GCC/Xtensa_ESP32/include/xtensa_config.h +++ b/Source/portable/ThirdParty/GCC/Xtensa_ESP32/include/xtensa_config.h @@ -5,6 +5,7 @@ * * SPDX-FileContributor: 2016-2022 Espressif Systems (Shanghai) CO LTD */ + /* * Copyright (c) 2015-2019 Cadence Design Systems, Inc. * @@ -40,7 +41,7 @@ *******************************************************************************/ #ifndef XTENSA_CONFIG_H - #define XTENSA_CONFIG_H +#define XTENSA_CONFIG_H /* *INDENT-OFF* */ #ifdef __cplusplus @@ -48,11 +49,11 @@ #endif /* *INDENT-ON* */ - #include - #include - #include /* required for XSHAL_CLIB */ +#include +#include +#include /* required for XSHAL_CLIB */ - #include "xtensa_context.h" +#include "xtensa_context.h" /*----------------------------------------------------------------------------- @@ -105,27 +106,27 @@ * -----------------------------------------------------------------------------*/ /* Extra space required for interrupt/exception hooks. */ - #ifdef XT_INTEXC_HOOKS - #ifdef __XTENSA_CALL0_ABI__ - #define STK_INTEXC_EXTRA 0x200 - #else - #define STK_INTEXC_EXTRA 0x180 - #endif +#ifdef XT_INTEXC_HOOKS + #ifdef __XTENSA_CALL0_ABI__ + #define STK_INTEXC_EXTRA 0x200 #else - #define STK_INTEXC_EXTRA 0 + #define STK_INTEXC_EXTRA 0x180 #endif +#else + #define STK_INTEXC_EXTRA 0 +#endif - #define XT_CLIB_CONTEXT_AREA_SIZE 0 +#define XT_CLIB_CONTEXT_AREA_SIZE 0 /*------------------------------------------------------------------------------ * Extra size -- interrupt frame plus coprocessor save area plus hook space. * NOTE: Make sure XT_INTEXC_HOOKS is undefined unless you really need the hooks. * ------------------------------------------------------------------------------*/ - #ifdef __XTENSA_CALL0_ABI__ - #define XT_XTRA_SIZE ( XT_STK_FRMSZ + STK_INTEXC_EXTRA + 0x10 + XT_CP_SIZE ) - #else - #define XT_XTRA_SIZE ( XT_STK_FRMSZ + STK_INTEXC_EXTRA + 0x20 + XT_CP_SIZE ) - #endif +#ifdef __XTENSA_CALL0_ABI__ + #define XT_XTRA_SIZE ( XT_STK_FRMSZ + STK_INTEXC_EXTRA + 0x10 + XT_CP_SIZE ) +#else + #define XT_XTRA_SIZE ( XT_STK_FRMSZ + STK_INTEXC_EXTRA + 0x20 + XT_CP_SIZE ) +#endif /*------------------------------------------------------------------------------ * Space allocated for user code -- function calls and local variables. @@ -135,18 +136,18 @@ * NOTE: The windowed ABI requires more stack, since space has to be reserved * for spilling register windows. * ------------------------------------------------------------------------------*/ - #ifdef __XTENSA_CALL0_ABI__ - #define XT_USER_SIZE 0x200 - #else - #define XT_USER_SIZE 0x400 - #endif +#ifdef __XTENSA_CALL0_ABI__ + #define XT_USER_SIZE 0x200 +#else + #define XT_USER_SIZE 0x400 +#endif /* Minimum recommended stack size. */ - #define XT_STACK_MIN_SIZE ( ( XT_XTRA_SIZE + XT_USER_SIZE ) / sizeof( unsigned char ) ) +#define XT_STACK_MIN_SIZE ( ( XT_XTRA_SIZE + XT_USER_SIZE ) / sizeof( unsigned char ) ) /* OS overhead with and without C library thread context. */ - #define XT_STACK_EXTRA ( XT_XTRA_SIZE ) - #define XT_STACK_EXTRA_CLIB ( XT_XTRA_SIZE + XT_CLIB_CONTEXT_AREA_SIZE ) +#define XT_STACK_EXTRA ( XT_XTRA_SIZE ) +#define XT_STACK_EXTRA_CLIB ( XT_XTRA_SIZE + XT_CLIB_CONTEXT_AREA_SIZE ) /* *INDENT-OFF* */ #ifdef __cplusplus diff --git a/Source/portable/ThirdParty/GCC/Xtensa_ESP32/include/xtensa_context.h b/Source/portable/ThirdParty/GCC/Xtensa_ESP32/include/xtensa_context.h index fc24748c4..56e6bf5c7 100644 --- a/Source/portable/ThirdParty/GCC/Xtensa_ESP32/include/xtensa_context.h +++ b/Source/portable/ThirdParty/GCC/Xtensa_ESP32/include/xtensa_context.h @@ -5,6 +5,7 @@ * * SPDX-FileContributor: 2016-2022 Espressif Systems (Shanghai) CO LTD */ + /* * Copyright (c) 2015-2019 Cadence Design Systems, Inc. * diff --git a/Source/portable/ThirdParty/GCC/Xtensa_ESP32/include/xtensa_rtos.h b/Source/portable/ThirdParty/GCC/Xtensa_ESP32/include/xtensa_rtos.h index 1f0c063b1..767e95052 100644 --- a/Source/portable/ThirdParty/GCC/Xtensa_ESP32/include/xtensa_rtos.h +++ b/Source/portable/ThirdParty/GCC/Xtensa_ESP32/include/xtensa_rtos.h @@ -5,6 +5,7 @@ * * SPDX-FileContributor: 2016-2022 Espressif Systems (Shanghai) CO LTD */ + /* * Copyright (c) 2015-2019 Cadence Design Systems, Inc. * @@ -60,6 +61,7 @@ #include #include #include "sdkconfig.h" + /* * Include any RTOS specific definitions that are needed by this header. */ @@ -155,9 +157,9 @@ */ /* void XT_RTOS_TIMER_INT(void) */ #ifdef CONFIG_FREERTOS_SYSTICK_USES_CCOUNT -#define XT_RTOS_TIMER_INT _frxt_timer_int + #define XT_RTOS_TIMER_INT _frxt_timer_int #endif -#define XT_TICK_PER_SEC configTICK_RATE_HZ +#define XT_TICK_PER_SEC configTICK_RATE_HZ /* * Return in a15 the base address of the co-processor state save area for the diff --git a/Source/portable/ThirdParty/GCC/Xtensa_ESP32/include/xtensa_timer.h b/Source/portable/ThirdParty/GCC/Xtensa_ESP32/include/xtensa_timer.h index 635ce1ffd..d046feac5 100644 --- a/Source/portable/ThirdParty/GCC/Xtensa_ESP32/include/xtensa_timer.h +++ b/Source/portable/ThirdParty/GCC/Xtensa_ESP32/include/xtensa_timer.h @@ -5,6 +5,7 @@ * * SPDX-FileContributor: 2016-2022 Espressif Systems (Shanghai) CO LTD */ + /* * Copyright (c) 2015-2019 Cadence Design Systems, Inc. * diff --git a/Source/portable/ThirdParty/GCC/Xtensa_ESP32/port.c b/Source/portable/ThirdParty/GCC/Xtensa_ESP32/port.c index 83ae40720..fc469966e 100644 --- a/Source/portable/ThirdParty/GCC/Xtensa_ESP32/port.c +++ b/Source/portable/ThirdParty/GCC/Xtensa_ESP32/port.c @@ -6,8 +6,9 @@ * * SPDX-FileContributor: 2016-2022 Espressif Systems (Shanghai) CO LTD */ + /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of @@ -33,6 +34,7 @@ * * 1 tab == 4 spaces! */ + /* * Copyright (c) 2015-2019 Cadence Design Systems, Inc. * @@ -63,22 +65,22 @@ #include "xtensa_rtos.h" #include "esp_idf_version.h" -#if (ESP_IDF_VERSION < ESP_IDF_VERSION_VAL(4, 2, 0)) -#include "rom/ets_sys.h" -#include "esp_panic.h" -#include "esp_crosscore_int.h" +#if ( ESP_IDF_VERSION < ESP_IDF_VERSION_VAL( 4, 2, 0 ) ) + #include "rom/ets_sys.h" + #include "esp_panic.h" + #include "esp_crosscore_int.h" #else -#if CONFIG_IDF_TARGET_ESP32S3 - #include "esp32s3/rom/ets_sys.h" -#elif CONFIG_IDF_TARGET_ESP32S2 - #include "esp32s2/rom/ets_sys.h" -#elif CONFIG_IDF_TARGET_ESP32 - #include "esp32/rom/ets_sys.h" -#endif -#include "esp_private/panic_reason.h" -#include "esp_debug_helpers.h" -#include "esp_private/crosscore_int.h" -#include "esp_log.h" + #if CONFIG_IDF_TARGET_ESP32S3 + #include "esp32s3/rom/ets_sys.h" + #elif CONFIG_IDF_TARGET_ESP32S2 + #include "esp32s2/rom/ets_sys.h" + #elif CONFIG_IDF_TARGET_ESP32 + #include "esp32/rom/ets_sys.h" + #endif + #include "esp_private/panic_reason.h" + #include "esp_debug_helpers.h" + #include "esp_private/crosscore_int.h" + #include "esp_log.h" #endif /* ESP_IDF_VERSION < ESP_IDF_VERSION_VAL(4, 2, 0) */ #include "soc/cpu.h" @@ -94,12 +96,12 @@ /* Defined in xtensa_context.S */ extern void _xt_coproc_init( void ); -_Static_assert(tskNO_AFFINITY == CONFIG_FREERTOS_NO_AFFINITY, "incorrect tskNO_AFFINITY value"); +_Static_assert( tskNO_AFFINITY == CONFIG_FREERTOS_NO_AFFINITY, "incorrect tskNO_AFFINITY value" ); /*-----------------------------------------------------------*/ -extern volatile int port_xSchedulerRunning[portNUM_PROCESSORS]; -unsigned port_interruptNesting[ portNUM_PROCESSORS ] = { 0 }; /* Interrupt nesting level. Increased/decreased in portasm.c, _frxt_int_enter/_frxt_int_exit */ +extern volatile int port_xSchedulerRunning[ portNUM_PROCESSORS ]; +unsigned port_interruptNesting[ portNUM_PROCESSORS ] = { 0 }; /* Interrupt nesting level. Increased/decreased in portasm.c, _frxt_int_enter/_frxt_int_exit */ /*-----------------------------------------------------------*/ @@ -153,15 +155,15 @@ void _xt_user_exit( void ); thread_local_sz = ALIGNUP( 0x10, thread_local_sz ); /* Initialize task's stack so that we have the following structure at the top: - - ----LOW ADDRESSES ----------------------------------------HIGH ADDRESSES---------- - task stack | interrupt stack frame | thread local vars | co-processor save area | - ---------------------------------------------------------------------------------- - | | - SP pxTopOfStack - - All parts are aligned to 16 byte boundary. - */ + * + * ----LOW ADDRESSES ----------------------------------------HIGH ADDRESSES---------- + * task stack | interrupt stack frame | thread local vars | co-processor save area | + * ---------------------------------------------------------------------------------- + | | + | SP pxTopOfStack + | + | All parts are aligned to 16 byte boundary. + */ /* Create interrupt stack frame aligned to 16 byte boundary */ sp = ( StackType_t * ) ( ( ( UBaseType_t ) pxTopOfStack - XT_CP_SIZE - thread_local_sz - XT_STK_FRMSZ ) & ~0xf ); @@ -309,7 +311,7 @@ void vPortYieldOtherCore( BaseType_t coreid ) uint32_t usStackDepth ) { #if XCHAL_CP_NUM > 0 - xMPUSettings->coproc_area = ( StackType_t * ) ( ( uint32_t ) ( pxBottomOfStack + usStackDepth - 1 )); + xMPUSettings->coproc_area = ( StackType_t * ) ( ( uint32_t ) ( pxBottomOfStack + usStackDepth - 1 ) ); xMPUSettings->coproc_area = ( StackType_t * ) ( ( ( portPOINTER_SIZE_TYPE ) xMPUSettings->coproc_area ) & ( ~( ( portPOINTER_SIZE_TYPE ) portBYTE_ALIGNMENT_MASK ) ) ); xMPUSettings->coproc_area = ( StackType_t * ) ( ( ( uint32_t ) xMPUSettings->coproc_area - XT_CP_SIZE ) & ~0xf ); @@ -351,27 +353,29 @@ BaseType_t IRAM_ATTR xPortInterruptedFromISRContext() return( port_interruptNesting[ xPortGetCoreID() ] != 0 ); } -void IRAM_ATTR vPortEvaluateYieldFromISR( int argc, ... ) +void IRAM_ATTR vPortEvaluateYieldFromISR( int argc, + ... ) { BaseType_t xYield; va_list ap; + va_start( ap, argc ); if( argc ) { - xYield = ( BaseType_t )va_arg( ap, int ); + xYield = ( BaseType_t ) va_arg( ap, int ); va_end( ap ); } else { - //it is a empty parameter vPortYieldFromISR macro call: + /*it is a empty parameter vPortYieldFromISR macro call: */ va_end( ap ); traceISR_EXIT_TO_SCHEDULER(); _frxt_setup_switch(); return; } - //Yield exists, so need evaluate it first then switch: + /*Yield exists, so need evaluate it first then switch: */ if( xYield == pdTRUE ) { traceISR_EXIT_TO_SCHEDULER(); @@ -477,8 +481,8 @@ void vPortCPUInitializeMutex( portMUX_TYPE * mux ) } #endif /* ifdef CONFIG_FREERTOS_PORTMUX_DEBUG */ -#define STACK_WATCH_AREA_SIZE ( 32 ) -#define STACK_WATCH_POINT_NUMBER ( SOC_CPU_WATCHPOINTS_NUM - 1 ) +#define STACK_WATCH_AREA_SIZE ( 32 ) +#define STACK_WATCH_POINT_NUMBER ( SOC_CPU_WATCHPOINTS_NUM - 1 ) void vPortSetStackWatchpoint( void * pxStackStart ) { @@ -491,48 +495,48 @@ void vPortSetStackWatchpoint( void * pxStackStart ) int addr = ( int ) pxStackStart; addr = ( addr + 31 ) & ( ~31 ); - esp_cpu_set_watchpoint( STACK_WATCH_POINT_NUMBER, (char*)addr, 32, ESP_WATCHPOINT_STORE ); + esp_cpu_set_watchpoint( STACK_WATCH_POINT_NUMBER, ( char * ) addr, 32, ESP_WATCHPOINT_STORE ); } -#if (ESP_IDF_VERSION < ESP_IDF_VERSION_VAL(4, 2, 0)) +#if ( ESP_IDF_VERSION < ESP_IDF_VERSION_VAL( 4, 2, 0 ) ) -#if defined( CONFIG_SPIRAM_SUPPORT ) + #if defined( CONFIG_SPIRAM_SUPPORT ) /* * Compare & set (S32C1) does not work in external RAM. Instead, this routine uses a mux (in internal memory) to fake it. */ - static portMUX_TYPE extram_mux = portMUX_INITIALIZER_UNLOCKED; - - void uxPortCompareSetExtram( volatile uint32_t * addr, - uint32_t compare, - uint32_t * set ) - { - uint32_t prev; - - uint32_t oldlevel = portSET_INTERRUPT_MASK_FROM_ISR(); + static portMUX_TYPE extram_mux = portMUX_INITIALIZER_UNLOCKED; - #ifdef CONFIG_FREERTOS_PORTMUX_DEBUG - vPortCPUAcquireMutexIntsDisabled( &extram_mux, portMUX_NO_TIMEOUT, __FUNCTION__, __LINE__ ); - #else - vPortCPUAcquireMutexIntsDisabled( &extram_mux, portMUX_NO_TIMEOUT ); - #endif - prev = *addr; - - if( prev == compare ) + void uxPortCompareSetExtram( volatile uint32_t * addr, + uint32_t compare, + uint32_t * set ) { - *addr = *set; + uint32_t prev; + + uint32_t oldlevel = portSET_INTERRUPT_MASK_FROM_ISR(); + + #ifdef CONFIG_FREERTOS_PORTMUX_DEBUG + vPortCPUAcquireMutexIntsDisabled( &extram_mux, portMUX_NO_TIMEOUT, __FUNCTION__, __LINE__ ); + #else + vPortCPUAcquireMutexIntsDisabled( &extram_mux, portMUX_NO_TIMEOUT ); + #endif + prev = *addr; + + if( prev == compare ) + { + *addr = *set; + } + + *set = prev; + #ifdef CONFIG_FREERTOS_PORTMUX_DEBUG + vPortCPUReleaseMutexIntsDisabled( &extram_mux, __FUNCTION__, __LINE__ ); + #else + vPortCPUReleaseMutexIntsDisabled( &extram_mux ); + #endif + + portCLEAR_INTERRUPT_MASK_FROM_ISR( oldlevel ); } - - *set = prev; - #ifdef CONFIG_FREERTOS_PORTMUX_DEBUG - vPortCPUReleaseMutexIntsDisabled( &extram_mux, __FUNCTION__, __LINE__ ); - #else - vPortCPUReleaseMutexIntsDisabled( &extram_mux ); - #endif - - portCLEAR_INTERRUPT_MASK_FROM_ISR(oldlevel); - } -#endif //defined(CONFIG_SPIRAM_SUPPORT) + #endif //defined(CONFIG_SPIRAM_SUPPORT) #endif /* ESP_IDF_VERSION < ESP_IDF_VERSION_VAL(4, 2, 0) */ @@ -542,27 +546,27 @@ uint32_t xPortGetTickRateHz( void ) return ( uint32_t ) configTICK_RATE_HZ; } -// For now, running FreeRTOS on one core and a bare metal on the other (or other OSes) -// is not supported. For now CONFIG_FREERTOS_UNICORE and CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE -// should mirror each other's values. -// -// And since this should be true, we can just check for CONFIG_FREERTOS_UNICORE. +/* For now, running FreeRTOS on one core and a bare metal on the other (or other OSes) */ +/* is not supported. For now CONFIG_FREERTOS_UNICORE and CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE */ +/* should mirror each other's values. */ +/* */ +/* And since this should be true, we can just check for CONFIG_FREERTOS_UNICORE. */ #if CONFIG_FREERTOS_UNICORE != CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE #error "FreeRTOS and system configuration mismatch regarding the use of multiple cores." #endif -extern void esp_startup_start_app_common(void); +extern void esp_startup_start_app_common( void ); -void esp_startup_start_app(void) +void esp_startup_start_app( void ) { -#if !CONFIG_ESP_INT_WDT -#if CONFIG_ESP32_ECO3_CACHE_LOCK_FIX - assert(!soc_has_cache_lock_bug() && "ESP32 Rev 3 + Dual Core + PSRAM requires INT WDT enabled in project config!"); -#endif -#endif + #if !CONFIG_ESP_INT_WDT + #if CONFIG_ESP32_ECO3_CACHE_LOCK_FIX + assert( !soc_has_cache_lock_bug() && "ESP32 Rev 3 + Dual Core + PSRAM requires INT WDT enabled in project config!" ); + #endif + #endif esp_startup_start_app_common(); - ESP_LOGI("cpu_start", "Starting scheduler on PRO CPU."); + ESP_LOGI( "cpu_start", "Starting scheduler on PRO CPU." ); vTaskStartScheduler(); } diff --git a/Source/portable/ThirdParty/GCC/Xtensa_ESP32/port_common.c b/Source/portable/ThirdParty/GCC/Xtensa_ESP32/port_common.c index 11f119bcd..cd8193a89 100644 --- a/Source/portable/ThirdParty/GCC/Xtensa_ESP32/port_common.c +++ b/Source/portable/ThirdParty/GCC/Xtensa_ESP32/port_common.c @@ -14,7 +14,7 @@ #include "esp_task_wdt.h" #include "esp_task.h" #include "esp_private/crosscore_int.h" -#include "esp_private/startup_internal.h" /* Required by g_spiram_ok. [refactor-todo] for g_spiram_ok */ +#include "esp_private/startup_internal.h" /* Required by g_spiram_ok. [refactor-todo] for g_spiram_ok */ #include "esp_log.h" #include "soc/soc_memory_types.h" #include "soc/dport_access.h" @@ -22,17 +22,17 @@ #include "esp_freertos_hooks.h" #if CONFIG_IDF_TARGET_ESP32 -#include "esp32/spiram.h" + #include "esp32/spiram.h" #elif CONFIG_IDF_TARGET_ESP32S2 -#include "esp32s2/spiram.h" + #include "esp32s2/spiram.h" #elif CONFIG_IDF_TARGET_ESP32S3 -#include "esp32s3/spiram.h" + #include "esp32s3/spiram.h" #elif CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32H2 -// SPIRAM is not supported on ESP32-C3 +/* SPIRAM is not supported on ESP32-C3 */ #endif #if CONFIG_SPIRAM_MALLOC_RESERVE_INTERNAL -static const char* TAG = "cpu_start"; + static const char * TAG = "cpu_start"; #endif /* Architecture-agnostic parts of the FreeRTOS ESP-IDF port layer can go here. @@ -41,119 +41,127 @@ static const char* TAG = "cpu_start"; * which will then call esp_startup_start_app_common() */ -// Duplicate of inaccessible xSchedulerRunning; needed at startup to avoid counting nesting -volatile unsigned port_xSchedulerRunning[portNUM_PROCESSORS] = {0}; +/* Duplicate of inaccessible xSchedulerRunning; needed at startup to avoid counting nesting */ +volatile unsigned port_xSchedulerRunning[ portNUM_PROCESSORS ] = { 0 }; -// For now, running FreeRTOS on one core and a bare metal on the other (or other OSes) -// is not supported. For now CONFIG_FREERTOS_UNICORE and CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE -// should mirror each other's values. -// -// And since this should be true, we can just check for CONFIG_FREERTOS_UNICORE. +/* For now, running FreeRTOS on one core and a bare metal on the other (or other OSes) */ +/* is not supported. For now CONFIG_FREERTOS_UNICORE and CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE */ +/* should mirror each other's values. */ +/* */ +/* And since this should be true, we can just check for CONFIG_FREERTOS_UNICORE. */ #if CONFIG_FREERTOS_UNICORE != CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE #error "FreeRTOS and system configuration mismatch regarding the use of multiple cores." #endif -static void main_task(void* args); +static void main_task( void * args ); #ifdef CONFIG_ESP_SYSTEM_GDBSTUB_RUNTIME -void esp_gdbstub_init(void); + void esp_gdbstub_init( void ); #endif // CONFIG_ESP_SYSTEM_GDBSTUB_RUNTIME -extern void app_main(void); +extern void app_main( void ); -void esp_startup_start_app_common(void) +void esp_startup_start_app_common( void ) { -#if CONFIG_ESP_INT_WDT - esp_int_wdt_init(); - //Initialize the interrupt watch dog for CPU0. - esp_int_wdt_cpu_init(); -#endif + #if CONFIG_ESP_INT_WDT + esp_int_wdt_init(); + /*Initialize the interrupt watch dog for CPU0. */ + esp_int_wdt_cpu_init(); + #endif esp_crosscore_int_init(); -#ifdef CONFIG_ESP_SYSTEM_GDBSTUB_RUNTIME - esp_gdbstub_init(); -#endif // CONFIG_ESP_SYSTEM_GDBSTUB_RUNTIME - - portBASE_TYPE res = xTaskCreatePinnedToCore(&main_task, "main", - ESP_TASK_MAIN_STACK, NULL, - ESP_TASK_MAIN_PRIO, NULL, ESP_TASK_MAIN_CORE); - assert(res == pdTRUE); - (void)res; -} + #ifdef CONFIG_ESP_SYSTEM_GDBSTUB_RUNTIME + esp_gdbstub_init(); + #endif // CONFIG_ESP_SYSTEM_GDBSTUB_RUNTIME -#if !CONFIG_FREERTOS_UNICORE -static volatile bool s_other_cpu_startup_done = false; -static bool other_cpu_startup_idle_hook_cb(void) -{ - s_other_cpu_startup_done = true; - return true; + portBASE_TYPE res = xTaskCreatePinnedToCore( &main_task, "main", + ESP_TASK_MAIN_STACK, NULL, + ESP_TASK_MAIN_PRIO, NULL, ESP_TASK_MAIN_CORE ); + assert( res == pdTRUE ); + ( void ) res; } -#endif -static void main_task(void* args) -{ #if !CONFIG_FREERTOS_UNICORE - // Wait for FreeRTOS initialization to finish on other core, before replacing its startup stack - esp_register_freertos_idle_hook_for_cpu(other_cpu_startup_idle_hook_cb, !xPortGetCoreID()); - while (!s_other_cpu_startup_done) { - ; + static volatile bool s_other_cpu_startup_done = false; + static bool other_cpu_startup_idle_hook_cb( void ) + { + s_other_cpu_startup_done = true; + return true; } - esp_deregister_freertos_idle_hook_for_cpu(other_cpu_startup_idle_hook_cb, !xPortGetCoreID()); #endif - // [refactor-todo] check if there is a way to move the following block to esp_system startup - heap_caps_enable_nonos_stack_heaps(); +static void main_task( void * args ) +{ + #if !CONFIG_FREERTOS_UNICORE + /* Wait for FreeRTOS initialization to finish on other core, before replacing its startup stack */ + esp_register_freertos_idle_hook_for_cpu( other_cpu_startup_idle_hook_cb, !xPortGetCoreID() ); - // Now we have startup stack RAM available for heap, enable any DMA pool memory -#if CONFIG_SPIRAM_MALLOC_RESERVE_INTERNAL - if (g_spiram_ok) { - esp_err_t r = esp_spiram_reserve_dma_pool(CONFIG_SPIRAM_MALLOC_RESERVE_INTERNAL); - if (r != ESP_OK) { - ESP_EARLY_LOGE(TAG, "Could not reserve internal/DMA pool (error 0x%x)", r); - abort(); + while( !s_other_cpu_startup_done ) + { } - } -#endif + esp_deregister_freertos_idle_hook_for_cpu( other_cpu_startup_idle_hook_cb, !xPortGetCoreID() ); + #endif - //Initialize task wdt if configured to do so -#ifdef CONFIG_ESP_TASK_WDT_PANIC - ESP_ERROR_CHECK(esp_task_wdt_init(CONFIG_ESP_TASK_WDT_TIMEOUT_S, true)); -#elif CONFIG_ESP_TASK_WDT - ESP_ERROR_CHECK(esp_task_wdt_init(CONFIG_ESP_TASK_WDT_TIMEOUT_S, false)); -#endif + /* [refactor-todo] check if there is a way to move the following block to esp_system startup */ + heap_caps_enable_nonos_stack_heaps(); - //Add IDLE 0 to task wdt -#ifdef CONFIG_ESP_TASK_WDT_CHECK_IDLE_TASK_CPU0 - TaskHandle_t idle_0 = xTaskGetIdleTaskHandleForCPU(0); - if(idle_0 != NULL){ - ESP_ERROR_CHECK(esp_task_wdt_add(idle_0)); - } -#endif - //Add IDLE 1 to task wdt -#ifdef CONFIG_ESP_TASK_WDT_CHECK_IDLE_TASK_CPU1 - TaskHandle_t idle_1 = xTaskGetIdleTaskHandleForCPU(1); - if(idle_1 != NULL){ - ESP_ERROR_CHECK(esp_task_wdt_add(idle_1)); - } -#endif + /* Now we have startup stack RAM available for heap, enable any DMA pool memory */ + #if CONFIG_SPIRAM_MALLOC_RESERVE_INTERNAL + if( g_spiram_ok ) + { + esp_err_t r = esp_spiram_reserve_dma_pool( CONFIG_SPIRAM_MALLOC_RESERVE_INTERNAL ); + + if( r != ESP_OK ) + { + ESP_EARLY_LOGE( TAG, "Could not reserve internal/DMA pool (error 0x%x)", r ); + abort(); + } + } + #endif /* if CONFIG_SPIRAM_MALLOC_RESERVE_INTERNAL */ + + /*Initialize task wdt if configured to do so */ + #ifdef CONFIG_ESP_TASK_WDT_PANIC + ESP_ERROR_CHECK( esp_task_wdt_init( CONFIG_ESP_TASK_WDT_TIMEOUT_S, true ) ); + #elif CONFIG_ESP_TASK_WDT + ESP_ERROR_CHECK( esp_task_wdt_init( CONFIG_ESP_TASK_WDT_TIMEOUT_S, false ) ); + #endif + + /*Add IDLE 0 to task wdt */ + #ifdef CONFIG_ESP_TASK_WDT_CHECK_IDLE_TASK_CPU0 + TaskHandle_t idle_0 = xTaskGetIdleTaskHandleForCPU( 0 ); + + if( idle_0 != NULL ) + { + ESP_ERROR_CHECK( esp_task_wdt_add( idle_0 ) ); + } + #endif + /*Add IDLE 1 to task wdt */ + #ifdef CONFIG_ESP_TASK_WDT_CHECK_IDLE_TASK_CPU1 + TaskHandle_t idle_1 = xTaskGetIdleTaskHandleForCPU( 1 ); + + if( idle_1 != NULL ) + { + ESP_ERROR_CHECK( esp_task_wdt_add( idle_1 ) ); + } + #endif app_main(); - vTaskDelete(NULL); + vTaskDelete( NULL ); } -// -------------------- Heap Related ----------------------- +/* -------------------- Heap Related ----------------------- */ -bool xPortCheckValidTCBMem(const void *ptr) +bool xPortCheckValidTCBMem( const void * ptr ) { - return esp_ptr_internal(ptr) && esp_ptr_byte_accessible(ptr); + return esp_ptr_internal( ptr ) && esp_ptr_byte_accessible( ptr ); } -bool xPortcheckValidStackMem(const void *ptr) +bool xPortcheckValidStackMem( const void * ptr ) { -#ifdef CONFIG_SPIRAM_ALLOW_STACK_EXTERNAL_MEMORY - return esp_ptr_byte_accessible(ptr); -#else - return esp_ptr_internal(ptr) && esp_ptr_byte_accessible(ptr); -#endif + #ifdef CONFIG_SPIRAM_ALLOW_STACK_EXTERNAL_MEMORY + return esp_ptr_byte_accessible( ptr ); + #else + return esp_ptr_internal( ptr ) && esp_ptr_byte_accessible( ptr ); + #endif } diff --git a/Source/portable/ThirdParty/GCC/Xtensa_ESP32/port_systick.c b/Source/portable/ThirdParty/GCC/Xtensa_ESP32/port_systick.c index a9f437c61..b7a49170b 100644 --- a/Source/portable/ThirdParty/GCC/Xtensa_ESP32/port_systick.c +++ b/Source/portable/ThirdParty/GCC/Xtensa_ESP32/port_systick.c @@ -14,51 +14,51 @@ #include "esp_log.h" #include "sdkconfig.h" #ifdef CONFIG_FREERTOS_SYSTICK_USES_SYSTIMER -#include "soc/periph_defs.h" -#include "soc/system_reg.h" -#include "hal/systimer_hal.h" -#include "hal/systimer_ll.h" + #include "soc/periph_defs.h" + #include "soc/system_reg.h" + #include "hal/systimer_hal.h" + #include "hal/systimer_ll.h" #endif #ifdef CONFIG_PM_TRACE -#include "esp_private/pm_trace.h" + #include "esp_private/pm_trace.h" #endif //CONFIG_PM_TRACE -BaseType_t xPortSysTickHandler(void); +BaseType_t xPortSysTickHandler( void ); #ifdef CONFIG_FREERTOS_SYSTICK_USES_CCOUNT -extern void _frxt_tick_timer_init(void); -extern void _xt_tick_divisor_init(void); + extern void _frxt_tick_timer_init( void ); + extern void _xt_tick_divisor_init( void ); -#ifdef CONFIG_FREERTOS_CORETIMER_0 - #define SYSTICK_INTR_ID (ETS_INTERNAL_TIMER0_INTR_SOURCE+ETS_INTERNAL_INTR_SOURCE_OFF) -#endif -#ifdef CONFIG_FREERTOS_CORETIMER_1 - #define SYSTICK_INTR_ID (ETS_INTERNAL_TIMER1_INTR_SOURCE+ETS_INTERNAL_INTR_SOURCE_OFF) -#endif + #ifdef CONFIG_FREERTOS_CORETIMER_0 + #define SYSTICK_INTR_ID ( ETS_INTERNAL_TIMER0_INTR_SOURCE + ETS_INTERNAL_INTR_SOURCE_OFF ) + #endif + #ifdef CONFIG_FREERTOS_CORETIMER_1 + #define SYSTICK_INTR_ID ( ETS_INTERNAL_TIMER1_INTR_SOURCE + ETS_INTERNAL_INTR_SOURCE_OFF ) + #endif /** * @brief Initialize CCONT timer to generate the tick interrupt * */ -void vPortSetupTimer(void) -{ - /* Init the tick divisor value */ - _xt_tick_divisor_init(); + void vPortSetupTimer( void ) + { + /* Init the tick divisor value */ + _xt_tick_divisor_init(); - _frxt_tick_timer_init(); -} + _frxt_tick_timer_init(); + } #elif CONFIG_FREERTOS_SYSTICK_USES_SYSTIMER -_Static_assert(SOC_CPU_CORES_NUM <= SOC_SYSTIMER_ALARM_NUM - 1, "the number of cores must match the number of core alarms in SYSTIMER"); + _Static_assert( SOC_CPU_CORES_NUM <= SOC_SYSTIMER_ALARM_NUM - 1, "the number of cores must match the number of core alarms in SYSTIMER" ); -void SysTickIsrHandler(void *arg); + void SysTickIsrHandler( void * arg ); -static uint32_t s_handled_systicks[portNUM_PROCESSORS] = { 0 }; + static uint32_t s_handled_systicks[ portNUM_PROCESSORS ] = { 0 }; -#define SYSTICK_INTR_ID (ETS_SYSTIMER_TARGET0_EDGE_INTR_SOURCE) + #define SYSTICK_INTR_ID ( ETS_SYSTIMER_TARGET0_EDGE_INTR_SOURCE ) /** * @brief Set up the systimer peripheral to generate the tick interrupt @@ -67,50 +67,58 @@ static uint32_t s_handled_systicks[portNUM_PROCESSORS] = { 0 }; * It is done at the same time so SysTicks for both CPUs occur at the same time or very close. * Shifts a time of triggering interrupts for core 0 and core 1. */ -void vPortSetupTimer(void) -{ - unsigned cpuid = xPortGetCoreID(); -#ifdef CONFIG_FREERTOS_CORETIMER_SYSTIMER_LVL3 - const unsigned level = ESP_INTR_FLAG_LEVEL3; -#else - const unsigned level = ESP_INTR_FLAG_LEVEL1; -#endif - /* Systimer HAL layer object */ - static systimer_hal_context_t systimer_hal; - /* set system timer interrupt vector */ - ESP_ERROR_CHECK(esp_intr_alloc(ETS_SYSTIMER_TARGET0_EDGE_INTR_SOURCE + cpuid, ESP_INTR_FLAG_IRAM | level, SysTickIsrHandler, &systimer_hal, NULL)); - - if (cpuid == 0) { - systimer_hal_init(&systimer_hal); - systimer_ll_set_counter_value(systimer_hal.dev, SYSTIMER_LL_COUNTER_OS_TICK, 0); - systimer_ll_apply_counter_value(systimer_hal.dev, SYSTIMER_LL_COUNTER_OS_TICK); - - for (cpuid = 0; cpuid < SOC_CPU_CORES_NUM; cpuid++) { - systimer_hal_counter_can_stall_by_cpu(&systimer_hal, SYSTIMER_LL_COUNTER_OS_TICK, cpuid, false); - } - - for (cpuid = 0; cpuid < portNUM_PROCESSORS; ++cpuid) { - uint32_t alarm_id = SYSTIMER_LL_ALARM_OS_TICK_CORE0 + cpuid; + void vPortSetupTimer( void ) + { + unsigned cpuid = xPortGetCoreID(); + + #ifdef CONFIG_FREERTOS_CORETIMER_SYSTIMER_LVL3 + const unsigned level = ESP_INTR_FLAG_LEVEL3; + #else + const unsigned level = ESP_INTR_FLAG_LEVEL1; + #endif + /* Systimer HAL layer object */ + static systimer_hal_context_t systimer_hal; + /* set system timer interrupt vector */ + ESP_ERROR_CHECK( esp_intr_alloc( ETS_SYSTIMER_TARGET0_EDGE_INTR_SOURCE + cpuid, ESP_INTR_FLAG_IRAM | level, SysTickIsrHandler, &systimer_hal, NULL ) ); + + if( cpuid == 0 ) + { + systimer_hal_init( &systimer_hal ); + systimer_ll_set_counter_value( systimer_hal.dev, SYSTIMER_LL_COUNTER_OS_TICK, 0 ); + systimer_ll_apply_counter_value( systimer_hal.dev, SYSTIMER_LL_COUNTER_OS_TICK ); + + for( cpuid = 0; cpuid < SOC_CPU_CORES_NUM; cpuid++ ) + { + systimer_hal_counter_can_stall_by_cpu( &systimer_hal, SYSTIMER_LL_COUNTER_OS_TICK, cpuid, false ); + } - /* configure the timer */ - systimer_hal_connect_alarm_counter(&systimer_hal, alarm_id, SYSTIMER_LL_COUNTER_OS_TICK); - systimer_hal_set_alarm_period(&systimer_hal, alarm_id, 1000000UL / CONFIG_FREERTOS_HZ); - systimer_hal_select_alarm_mode(&systimer_hal, alarm_id, SYSTIMER_ALARM_MODE_PERIOD); - systimer_hal_counter_can_stall_by_cpu(&systimer_hal, SYSTIMER_LL_COUNTER_OS_TICK, cpuid, true); - if (cpuid == 0) { - systimer_hal_enable_alarm_int(&systimer_hal, alarm_id); - systimer_hal_enable_counter(&systimer_hal, SYSTIMER_LL_COUNTER_OS_TICK); -#ifndef CONFIG_FREERTOS_UNICORE - // SysTick of core 0 and core 1 are shifted by half of period - systimer_hal_counter_value_advance(&systimer_hal, SYSTIMER_LL_COUNTER_OS_TICK, 1000000UL / CONFIG_FREERTOS_HZ / 2); -#endif + for( cpuid = 0; cpuid < portNUM_PROCESSORS; ++cpuid ) + { + uint32_t alarm_id = SYSTIMER_LL_ALARM_OS_TICK_CORE0 + cpuid; + + /* configure the timer */ + systimer_hal_connect_alarm_counter( &systimer_hal, alarm_id, SYSTIMER_LL_COUNTER_OS_TICK ); + systimer_hal_set_alarm_period( &systimer_hal, alarm_id, 1000000UL / CONFIG_FREERTOS_HZ ); + systimer_hal_select_alarm_mode( &systimer_hal, alarm_id, SYSTIMER_ALARM_MODE_PERIOD ); + systimer_hal_counter_can_stall_by_cpu( &systimer_hal, SYSTIMER_LL_COUNTER_OS_TICK, cpuid, true ); + + if( cpuid == 0 ) + { + systimer_hal_enable_alarm_int( &systimer_hal, alarm_id ); + systimer_hal_enable_counter( &systimer_hal, SYSTIMER_LL_COUNTER_OS_TICK ); + #ifndef CONFIG_FREERTOS_UNICORE + /* SysTick of core 0 and core 1 are shifted by half of period */ + systimer_hal_counter_value_advance( &systimer_hal, SYSTIMER_LL_COUNTER_OS_TICK, 1000000UL / CONFIG_FREERTOS_HZ / 2 ); + #endif + } } } - } else { - uint32_t alarm_id = SYSTIMER_LL_ALARM_OS_TICK_CORE0 + cpuid; - systimer_hal_enable_alarm_int(&systimer_hal, alarm_id); + else + { + uint32_t alarm_id = SYSTIMER_LL_ALARM_OS_TICK_CORE0 + cpuid; + systimer_hal_enable_alarm_int( &systimer_hal, alarm_id ); + } } -} /** * @brief Systimer interrupt handler. @@ -118,37 +126,46 @@ void vPortSetupTimer(void) * The Systimer interrupt for SysTick works in periodic mode no need to calc the next alarm. * If a timer interrupt is ever serviced more than one tick late, it is necessary to process multiple ticks. */ -IRAM_ATTR void SysTickIsrHandler(void *arg) -{ - uint32_t cpuid = xPortGetCoreID(); - systimer_hal_context_t *systimer_hal = (systimer_hal_context_t *)arg; -#ifdef CONFIG_PM_TRACE - ESP_PM_TRACE_ENTER(TICK, cpuid); -#endif + IRAM_ATTR void SysTickIsrHandler( void * arg ) + { + uint32_t cpuid = xPortGetCoreID(); + systimer_hal_context_t * systimer_hal = ( systimer_hal_context_t * ) arg; - uint32_t alarm_id = SYSTIMER_LL_ALARM_OS_TICK_CORE0 + cpuid; - do { - systimer_ll_clear_alarm_int(systimer_hal->dev, alarm_id); - - uint32_t diff = systimer_hal_get_counter_value(systimer_hal, SYSTIMER_LL_COUNTER_OS_TICK) / systimer_ll_get_alarm_period(systimer_hal->dev, alarm_id) - s_handled_systicks[cpuid]; - if (diff > 0) { - if (s_handled_systicks[cpuid] == 0) { - s_handled_systicks[cpuid] = diff; - diff = 1; - } else { - s_handled_systicks[cpuid] += diff; - } + #ifdef CONFIG_PM_TRACE + ESP_PM_TRACE_ENTER( TICK, cpuid ); + #endif - do { - xPortSysTickHandler(); - } while (--diff); - } - } while (systimer_ll_is_alarm_int_fired(systimer_hal->dev, alarm_id)); + uint32_t alarm_id = SYSTIMER_LL_ALARM_OS_TICK_CORE0 + cpuid; -#ifdef CONFIG_PM_TRACE - ESP_PM_TRACE_EXIT(TICK, cpuid); -#endif -} + do + { + systimer_ll_clear_alarm_int( systimer_hal->dev, alarm_id ); + + uint32_t diff = systimer_hal_get_counter_value( systimer_hal, SYSTIMER_LL_COUNTER_OS_TICK ) / systimer_ll_get_alarm_period( systimer_hal->dev, alarm_id ) - s_handled_systicks[ cpuid ]; + + if( diff > 0 ) + { + if( s_handled_systicks[ cpuid ] == 0 ) + { + s_handled_systicks[ cpuid ] = diff; + diff = 1; + } + else + { + s_handled_systicks[ cpuid ] += diff; + } + + do + { + xPortSysTickHandler(); + } while( --diff ); + } + } while( systimer_ll_is_alarm_int_fired( systimer_hal->dev, alarm_id ) ); + + #ifdef CONFIG_PM_TRACE + ESP_PM_TRACE_EXIT( TICK, cpuid ); + #endif + } #endif // CONFIG_FREERTOS_SYSTICK_USES_CCOUNT @@ -160,15 +177,21 @@ IRAM_ATTR void SysTickIsrHandler(void *arg) * - SysTickIsrHandler for xtensa with CONFIG_FREERTOS_SYSTICK_USES_SYSTIMER * - SysTickIsrHandler for riscv */ -BaseType_t xPortSysTickHandler(void) +BaseType_t xPortSysTickHandler( void ) { portbenchmarkIntLatency(); - traceISR_ENTER(SYSTICK_INTR_ID); + traceISR_ENTER( SYSTICK_INTR_ID ); BaseType_t ret = xTaskIncrementTick(); - if(ret != pdFALSE) { + + if( ret != pdFALSE ) + { + traceISR_EXIT_TO_SCHEDULER(); portYIELD_FROM_ISR(); - } else { + } + else + { traceISR_EXIT(); } + return ret; } diff --git a/Source/portable/ThirdParty/GCC/Xtensa_ESP32/portmux_impl.h b/Source/portable/ThirdParty/GCC/Xtensa_ESP32/portmux_impl.h index 98d924f40..b9a4fa508 100644 --- a/Source/portable/ThirdParty/GCC/Xtensa_ESP32/portmux_impl.h +++ b/Source/portable/ThirdParty/GCC/Xtensa_ESP32/portmux_impl.h @@ -31,10 +31,10 @@ #include "portable.h" /* XOR one core ID with this value to get the other core ID */ -#if (ESP_IDF_VERSION < ESP_IDF_VERSION_VAL(4, 2, 0)) -#define CORE_ID_XOR_SWAP ( CORE_ID_PRO ^ CORE_ID_APP ) +#if ( ESP_IDF_VERSION < ESP_IDF_VERSION_VAL( 4, 2, 0 ) ) + #define CORE_ID_XOR_SWAP ( CORE_ID_PRO ^ CORE_ID_APP ) #else -#define CORE_ID_REGVAL_XOR_SWAP (CORE_ID_REGVAL_PRO ^ CORE_ID_REGVAL_APP) + #define CORE_ID_REGVAL_XOR_SWAP ( CORE_ID_REGVAL_PRO ^ CORE_ID_REGVAL_APP ) #endif diff --git a/Source/portable/ThirdParty/GCC/Xtensa_ESP32/portmux_impl.inc.h b/Source/portable/ThirdParty/GCC/Xtensa_ESP32/portmux_impl.inc.h index 9d7c826ec..37ca2fd0b 100644 --- a/Source/portable/ThirdParty/GCC/Xtensa_ESP32/portmux_impl.inc.h +++ b/Source/portable/ThirdParty/GCC/Xtensa_ESP32/portmux_impl.inc.h @@ -53,16 +53,16 @@ static inline bool __attribute__( ( always_inline ) ) #ifdef CONFIG_FREERTOS_PORTMUX_DEBUG uint32_t owner = mux->owner; - #if (ESP_IDF_VERSION < ESP_IDF_VERSION_VAL(4, 2, 0)) - if( ( owner != portMUX_FREE_VAL ) && ( owner != CORE_ID_PRO ) && ( owner != CORE_ID_APP ) ) + #if ( ESP_IDF_VERSION < ESP_IDF_VERSION_VAL( 4, 2, 0 ) ) + if( ( owner != portMUX_FREE_VAL ) && ( owner != CORE_ID_PRO ) && ( owner != CORE_ID_APP ) ) #else - if (owner != portMUX_FREE_VAL && owner != CORE_ID_REGVAL_PRO && owner != CORE_ID_REGVAL_APP) + if( ( owner != portMUX_FREE_VAL ) && ( owner != CORE_ID_REGVAL_PRO ) && ( owner != CORE_ID_REGVAL_APP ) ) #endif { ets_printf( "ERROR: vPortCPUAcquireMutex: mux %p is uninitialized (0x%X)! Called from %s line %d.\n", mux, owner, fnName, line ); mux->owner = portMUX_FREE_VAL; } - #endif + #endif /* ifdef CONFIG_FREERTOS_PORTMUX_DEBUG */ /* Spin until we own the core */ @@ -71,10 +71,10 @@ static inline bool __attribute__( ( always_inline ) ) /* Note: coreID is the full 32 bit core ID (CORE_ID_PRO/CORE_ID_APP), * not the 0/1 value returned by xPortGetCoreID() */ - #if (ESP_IDF_VERSION < ESP_IDF_VERSION_VAL(4, 2, 0)) - otherCoreID = CORE_ID_XOR_SWAP ^ coreID; + #if ( ESP_IDF_VERSION < ESP_IDF_VERSION_VAL( 4, 2, 0 ) ) + otherCoreID = CORE_ID_XOR_SWAP ^ coreID; #else - otherCoreID = CORE_ID_REGVAL_XOR_SWAP ^ coreID; + otherCoreID = CORE_ID_REGVAL_XOR_SWAP ^ coreID; #endif do @@ -154,10 +154,10 @@ static inline bool __attribute__( ( always_inline ) ) mux->lastLockedLine = line; uint32_t owner = mux->owner; - #if (ESP_IDF_VERSION < ESP_IDF_VERSION_VAL(4, 2, 0)) - if( ( owner != portMUX_FREE_VAL ) && ( owner != CORE_ID_PRO ) && ( owner != CORE_ID_APP ) ) + #if ( ESP_IDF_VERSION < ESP_IDF_VERSION_VAL( 4, 2, 0 ) ) + if( ( owner != portMUX_FREE_VAL ) && ( owner != CORE_ID_PRO ) && ( owner != CORE_ID_APP ) ) #else - if (owner != portMUX_FREE_VAL && owner != CORE_ID_REGVAL_PRO && owner != CORE_ID_REGVAL_APP) + if( ( owner != portMUX_FREE_VAL ) && ( owner != CORE_ID_REGVAL_PRO ) && ( owner != CORE_ID_REGVAL_APP ) ) #endif { ets_printf( "ERROR: vPortCPUReleaseMutex: mux %p is invalid (0x%x)!\n", mux, mux->owner ); diff --git a/Source/portable/ThirdParty/GCC/Xtensa_ESP32/xtensa_init.c b/Source/portable/ThirdParty/GCC/Xtensa_ESP32/xtensa_init.c index e7275c623..fbdd95fc5 100644 --- a/Source/portable/ThirdParty/GCC/Xtensa_ESP32/xtensa_init.c +++ b/Source/portable/ThirdParty/GCC/Xtensa_ESP32/xtensa_init.c @@ -5,6 +5,7 @@ * * SPDX-FileContributor: 2016-2022 Espressif Systems (Shanghai) CO LTD */ + /* * Copyright (c) 2015-2019 Cadence Design Systems, Inc. * @@ -39,37 +40,37 @@ #ifdef XT_BOARD -#include "xtensa/xtbsp.h" + #include "xtensa/xtbsp.h" #endif #include "xtensa_rtos.h" #include "sdkconfig.h" #include "esp_idf_version.h" -#if (ESP_IDF_VERSION < ESP_IDF_VERSION_VAL(4, 2, 0)) -#include "esp_clk.h" +#if ( ESP_IDF_VERSION < ESP_IDF_VERSION_VAL( 4, 2, 0 ) ) + #include "esp_clk.h" #else -#if CONFIG_IDF_TARGET_ESP32 -#include "esp32/clk.h" -#elif CONFIG_IDF_TARGET_ESP32S2 -#include "esp32s2/clk.h" -#elif CONFIG_IDF_TARGET_ESP32S3 -#include "esp32s3/clk.h" -#endif + #if CONFIG_IDF_TARGET_ESP32 + #include "esp32/clk.h" + #elif CONFIG_IDF_TARGET_ESP32S2 + #include "esp32s2/clk.h" + #elif CONFIG_IDF_TARGET_ESP32S3 + #include "esp32s3/clk.h" + #endif #endif /* ESP_IDF_VERSION < ESP_IDF_VERSION_VAL(4, 2, 0) */ #ifdef XT_RTOS_TIMER_INT -unsigned _xt_tick_divisor = 0; /* cached number of cycles per tick */ + unsigned _xt_tick_divisor = 0; /* cached number of cycles per tick */ -void _xt_tick_divisor_init(void) -{ - _xt_tick_divisor = esp_clk_cpu_freq() / XT_TICK_PER_SEC; -} + void _xt_tick_divisor_init( void ) + { + _xt_tick_divisor = esp_clk_cpu_freq() / XT_TICK_PER_SEC; + } /* Deprecated, to be removed */ -int xt_clock_freq(void) -{ - return esp_clk_cpu_freq(); -} + int xt_clock_freq( void ) + { + return esp_clk_cpu_freq(); + } #endif /* XT_RTOS_TIMER_INT */ diff --git a/Source/portable/ThirdParty/GCC/Xtensa_ESP32/xtensa_overlay_os_hook.c b/Source/portable/ThirdParty/GCC/Xtensa_ESP32/xtensa_overlay_os_hook.c index 618083dc9..4146f5d64 100644 --- a/Source/portable/ThirdParty/GCC/Xtensa_ESP32/xtensa_overlay_os_hook.c +++ b/Source/portable/ThirdParty/GCC/Xtensa_ESP32/xtensa_overlay_os_hook.c @@ -5,6 +5,7 @@ * * SPDX-FileContributor: 2016-2022 Espressif Systems (Shanghai) CO LTD */ + /* * Copyright (c) 2015-2019 Cadence Design Systems, Inc. * diff --git a/Source/portable/ThirdParty/Partner-Supported-Ports/GCC/AVR_AVRDx/porthardware.h b/Source/portable/ThirdParty/Partner-Supported-Ports/GCC/AVR_AVRDx/porthardware.h index 52e3f1293..74a16bc89 100644 --- a/Source/portable/ThirdParty/Partner-Supported-Ports/GCC/AVR_AVRDx/porthardware.h +++ b/Source/portable/ThirdParty/Partner-Supported-Ports/GCC/AVR_AVRDx/porthardware.h @@ -174,21 +174,21 @@ RTC.PER = RTC_PERIOD_HZ( configTICK_RATE_HZ ); \ RTC.INTCTRL |= 1 << RTC_OVF_bp; \ } - #undef TICK_TMR_STOP() - #undef TICK_TMR_START() - #undef TICK_TMR_READ() - #undef TICK_INT_READY() + #undef TICK_TMR_STOP + #undef TICK_TMR_START + #undef TICK_TMR_READ + #undef TICK_INT_READY #endif #else /* if ( configUSE_TIMER_INSTANCE == 0 ) */ #undef TICK_INT_vect #undef INT_FLAGS #undef INT_MASK - #undef TICK_init() - #undef TICK_TMR_STOP() - #undef TICK_TMR_START() - #undef TICK_TMR_READ() - #undef TICK_INT_READY() + #undef TICK_init + #undef TICK_TMR_STOP + #undef TICK_TMR_START + #undef TICK_TMR_READ + #undef TICK_INT_READY #error Invalid timer setting. #endif /* if ( configUSE_TIMER_INSTANCE == 0 ) */ diff --git a/Source/portable/ThirdParty/Partner-Supported-Ports/GCC/AVR_Mega0/porthardware.h b/Source/portable/ThirdParty/Partner-Supported-Ports/GCC/AVR_Mega0/porthardware.h index 05a04aee9..4cdb88566 100644 --- a/Source/portable/ThirdParty/Partner-Supported-Ports/GCC/AVR_Mega0/porthardware.h +++ b/Source/portable/ThirdParty/Partner-Supported-Ports/GCC/AVR_Mega0/porthardware.h @@ -151,7 +151,7 @@ #undef TICK_INT_vect #undef INT_FLAGS #undef INT_MASK - #undef TICK_init() + #undef TICK_init #error Invalid timer setting. #endif /* if ( configUSE_TIMER_INSTANCE == 0 ) */ diff --git a/Source/portable/ThirdParty/Partner-Supported-Ports/README.md b/Source/portable/ThirdParty/Partner-Supported-Ports/README.md index b614914c9..3fab01fbc 100644 --- a/Source/portable/ThirdParty/Partner-Supported-Ports/README.md +++ b/Source/portable/ThirdParty/Partner-Supported-Ports/README.md @@ -1,7 +1,15 @@ ## FreeRTOS Partner Supported Ports -This repository contains FreeRTOS ports supported by FreeRTOS partners. Follow -the steps below to contribute a FreeRTOS port to this repository: +This repository contains FreeRTOS ports supported by FreeRTOS partners. For a +partner supported FreeRTOS port: + +* The code has not been reviewed by the FreeRTOS team. +* FreeRTOS team has not verified the tests results but tests exist and are + reported to be successful by the partner. +* Customer queries as well as bugs are addressed by the partner. + +A new FreeRTOS port can be directly contributed by a partner. Follow the steps +below to contribute a FreeRTOS port to this repository: 1. Write the FreeRTOS port for your Compiler and Architecture. 2. Create a project in the [FreeRTOS Partner Supported Demos Repository](https://github.com/FreeRTOS/FreeRTOS-Partner-Supported-Demos/tree/main) diff --git a/Source/portable/ThirdParty/Partner-Supported-Ports/TI/CORTEX_A53_64-BIT_TI_AM64_SMP/port.c b/Source/portable/ThirdParty/Partner-Supported-Ports/TI/CORTEX_A53_64-BIT_TI_AM64_SMP/port.c new file mode 100644 index 000000000..29e06e97a --- /dev/null +++ b/Source/portable/ThirdParty/Partner-Supported-Ports/TI/CORTEX_A53_64-BIT_TI_AM64_SMP/port.c @@ -0,0 +1,418 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ +/* + * Copyright (C) 2018-2022 Texas Instruments Incorporated + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/* Standard includes. */ +#include + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" + +#include +#include + +#if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 + /* Check the configuration. */ + #if( configMAX_PRIORITIES > 32 ) + #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice. + #endif +#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */ + +/* A critical section is exited when the critical section nesting count reaches +this value. */ +#define portNO_CRITICAL_NESTING ( ( size_t ) 0 ) + +/* Tasks are not created with a floating point context, but can be given a +floating point context after they have been created. A variable is stored as +part of the tasks context that holds portNO_FLOATING_POINT_CONTEXT if the task +does not have an FPU context, or any other value if the task does have an FPU +context. */ +#define portNO_FLOATING_POINT_CONTEXT ( ( StackType_t ) 0 ) + +/* Constants required to setup the initial task context. */ +#define portSP_EL0 ( ( StackType_t ) 0x00 ) +#define portEL1 ( ( StackType_t ) 0x04 ) +#define portINITIAL_PSTATE ( portEL1 | portSP_EL0 ) + +/* Masks all bits in the APSR other than the mode bits. */ +#define portAPSR_MODE_BITS_MASK ( 0x0C ) + +/* + * Starts the first task executing. This function is necessarily written in + * assembly code so is implemented in portASM.s. + */ +extern void vPortRestoreTaskContext( void ); + +/* Saved as part of the task context. If ullPortTaskHasFPUContext is non-zero +then floating point context must be saved and restored for the task. */ +volatile uint64_t ullPortTaskHasFPUContext[configNUM_CORES] = {pdFALSE}; + +/* Set to 1 to pend a context switch from an ISR. */ +uint64_t ullPortYieldRequired[configNUM_CORES] = { pdFALSE }; + +/* Counts the interrupt nesting depth. A context switch is only performed if +if the nesting depth is 0. */ +uint64_t ullPortInterruptNesting[configNUM_CORES] = { 0 }; + +/* flag to control tick ISR handling, this is made true just before schedular start */ +volatile uint64_t ullPortSchedularRunning = pdFALSE; + +#define portPRIORITY_SHIFT 4 +__attribute__(( used )) const uint64_t ullMaxAPIPriorityMask = ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT ); + +/* + * See header file for description. + */ +StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters ) +{ + /* Setup the initial stack of the task. The stack is set exactly as + expected by the portRESTORE_CONTEXT() macro. */ + + /* First all the general purpose registers. */ + pxTopOfStack--; + *pxTopOfStack = 0x0101010101010101ULL; /* R1 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */ + pxTopOfStack--; + *pxTopOfStack = 0x0303030303030303ULL; /* R3 */ + pxTopOfStack--; + *pxTopOfStack = 0x0202020202020202ULL; /* R2 */ + pxTopOfStack--; + *pxTopOfStack = 0x0505050505050505ULL; /* R5 */ + pxTopOfStack--; + *pxTopOfStack = 0x0404040404040404ULL; /* R4 */ + pxTopOfStack--; + *pxTopOfStack = 0x0707070707070707ULL; /* R7 */ + pxTopOfStack--; + *pxTopOfStack = 0x0606060606060606ULL; /* R6 */ + pxTopOfStack--; + *pxTopOfStack = 0x0909090909090909ULL; /* R9 */ + pxTopOfStack--; + *pxTopOfStack = 0x0808080808080808ULL; /* R8 */ + pxTopOfStack--; + *pxTopOfStack = 0x1111111111111111ULL; /* R11 */ + pxTopOfStack--; + *pxTopOfStack = 0x1010101010101010ULL; /* R10 */ + pxTopOfStack--; + *pxTopOfStack = 0x1313131313131313ULL; /* R13 */ + pxTopOfStack--; + *pxTopOfStack = 0x1212121212121212ULL; /* R12 */ + pxTopOfStack--; + *pxTopOfStack = 0x1515151515151515ULL; /* R15 */ + pxTopOfStack--; + *pxTopOfStack = 0x1414141414141414ULL; /* R14 */ + pxTopOfStack--; + *pxTopOfStack = 0x1717171717171717ULL; /* R17 */ + pxTopOfStack--; + *pxTopOfStack = 0x1616161616161616ULL; /* R16 */ + pxTopOfStack--; + *pxTopOfStack = 0x1919191919191919ULL; /* R19 */ + pxTopOfStack--; + *pxTopOfStack = 0x1818181818181818ULL; /* R18 */ + pxTopOfStack--; + *pxTopOfStack = 0x2121212121212121ULL; /* R21 */ + pxTopOfStack--; + *pxTopOfStack = 0x2020202020202020ULL; /* R20 */ + pxTopOfStack--; + *pxTopOfStack = 0x2323232323232323ULL; /* R23 */ + pxTopOfStack--; + *pxTopOfStack = 0x2222222222222222ULL; /* R22 */ + pxTopOfStack--; + *pxTopOfStack = 0x2525252525252525ULL; /* R25 */ + pxTopOfStack--; + *pxTopOfStack = 0x2424242424242424ULL; /* R24 */ + pxTopOfStack--; + *pxTopOfStack = 0x2727272727272727ULL; /* R27 */ + pxTopOfStack--; + *pxTopOfStack = 0x2626262626262626ULL; /* R26 */ + pxTopOfStack--; + *pxTopOfStack = 0x2929292929292929ULL; /* R29 */ + pxTopOfStack--; + *pxTopOfStack = 0x2828282828282828ULL; /* R28 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x00; /* XZR - has no effect, used so there are an even number of registers. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x00; /* R30 - procedure call link register. */ + pxTopOfStack--; + + *pxTopOfStack = portINITIAL_PSTATE; + pxTopOfStack--; + + *pxTopOfStack = ( StackType_t ) pxCode; /* Exception return address. */ + pxTopOfStack--; + + /* The task will start with a critical nesting count of 0 as interrupts are + enabled. */ + *pxTopOfStack = portNO_CRITICAL_NESTING; + pxTopOfStack--; + + /* The task will start without a floating point context. A task that uses + the floating point hardware must call vPortTaskUsesFPU() before executing + any floating point instructions. */ + *pxTopOfStack = portNO_FLOATING_POINT_CONTEXT; + + return pxTopOfStack; +} + +BaseType_t xPortStartScheduler( void ) +{ + uint32_t ulAPSR; + + __asm volatile ( "MRS %0, CurrentEL" : "=r" ( ulAPSR ) ); + ulAPSR &= portAPSR_MODE_BITS_MASK; + + configASSERT( ulAPSR == portEL1 ); + if( ulAPSR == portEL1 ) + { + /* Interrupts are turned off in the CPU itself to ensure a tick does + not execute while the scheduler is being started. Interrupts are + automatically turned back on in the CPU when the first task starts + executing. */ + portDISABLE_INTERRUPTS(); + + if (0 == portGET_CORE_ID()) + { + ullPortSchedularRunning = pdTRUE; + } + + /* Start the first task executing. */ + vPortRestoreTaskContext(); + } + + return 0; +} + +void vPortEndScheduler( void ) +{ + /* Not implemented in ports where there is nothing to return to. + Artificially force an assert. */ + configASSERT( 0 ); +} + +void vPortTimerTickHandler() +{ + if( ullPortSchedularRunning == pdTRUE ) + { + /* Increment the RTOS tick. */ + if( xTaskIncrementTick() != pdFALSE ) + { + ullPortYieldRequired[portGET_CORE_ID()] = pdTRUE; + } + } +} + +void vPortTaskUsesFPU( void ) +{ + /* A task is registering the fact that it needs an FPU context. Set the + FPU flag (which is saved as part of the task context). */ + ullPortTaskHasFPUContext[portGET_CORE_ID()] = pdTRUE; + + /* Consider initialising the FPSR here - but probably not necessary in + AArch64. */ +} + +/* configCHECK_FOR_STACK_OVERFLOW is set to 1, so the application must provide an + * implementation of vApplicationStackOverflowHook() + */ +void vApplicationStackOverflowHook( TaskHandle_t xTask, + char * pcTaskName ) +{ + DebugP_logError("[FreeRTOS] Stack overflow detected for task [%s]", pcTaskName); + DebugP_assertNoLog(0); +} + +#if ( configSUPPORT_STATIC_ALLOCATION == 1 ) && ( configKERNEL_PROVIDED_STATIC_MEMORY == 0 ) + static StaticTask_t xIdleTaskTCB; + static StackType_t uxIdleTaskStack[ configMINIMAL_STACK_SIZE ]; + /* configSUPPORT_STATIC_ALLOCATION is set to 1, so the application must provide an + * implementation of vApplicationGetIdleTaskMemory() to provide the memory that is + * used by the Idle task. + */ + void vApplicationGetIdleTaskMemory( StaticTask_t **ppxIdleTaskTCBBuffer, + StackType_t **ppxIdleTaskStackBuffer, + uint32_t *pulIdleTaskStackSize ) + { + /* Pass out a pointer to the StaticTask_t structure in which the Idle task’s + * state will be stored. + */ + *ppxIdleTaskTCBBuffer = &xIdleTaskTCB; + + /* Pass out the array that will be used as the Idle task’s stack. */ + *ppxIdleTaskStackBuffer = uxIdleTaskStack; + + /* Pass out the size of the array pointed to by *ppxIdleTaskStackBuffer. + * Note that, as the array is necessarily of type StackType_t, + * configMINIMAL_STACK_SIZE is specified in words, not bytes. + */ + *pulIdleTaskStackSize = configMINIMAL_STACK_SIZE; + } + + #if ( configNUMBER_OF_CORES > 1 ) + static StaticTask_t xPassiveIdleTaskTCBs[ configNUMBER_OF_CORES - 1 ]; + static StackType_t uxPassiveIdleTaskStacks[ configNUMBER_OF_CORES - 1 ][ configMINIMAL_STACK_SIZE ]; + void vApplicationGetPassiveIdleTaskMemory( StaticTask_t ** ppxIdleTaskTCBBuffer, + StackType_t ** ppxIdleTaskStackBuffer, + uint32_t * pulIdleTaskStackSize, + BaseType_t xPassiveIdleTaskIndex ) + { + *ppxIdleTaskTCBBuffer = &( xPassiveIdleTaskTCBs[ xPassiveIdleTaskIndex ] ); + *ppxIdleTaskStackBuffer = &( uxPassiveIdleTaskStacks[ xPassiveIdleTaskIndex ][ 0 ] ); + *pulIdleTaskStackSize = configMINIMAL_STACK_SIZE; + } + + #endif /* #if ( configNUMBER_OF_CORES > 1 ) */ + + static StaticTask_t xTimerTaskTCB; + static StackType_t uxTimerTaskStack[ configTIMER_TASK_STACK_DEPTH ]; + /* configSUPPORT_STATIC_ALLOCATION and configUSE_TIMERS are both set to 1, so the + * application must provide an implementation of vApplicationGetTimerTaskMemory() + * to provide the memory that is used by the Timer service task. + */ + void vApplicationGetTimerTaskMemory( StaticTask_t **ppxTimerTaskTCBBuffer, + StackType_t **ppxTimerTaskStackBuffer, + uint32_t *pulTimerTaskStackSize ) + { + /* Pass out a pointer to the StaticTask_t structure in which the Timer + * task’s state will be stored. + */ + *ppxTimerTaskTCBBuffer = &xTimerTaskTCB; + + /* Pass out the array that will be used as the Timer task’s stack. */ + *ppxTimerTaskStackBuffer = uxTimerTaskStack; + + /* Pass out the size of the array pointed to by *ppxTimerTaskStackBuffer. + * Note that, as the array is necessarily of type StackType_t, + * configTIMER_TASK_STACK_DEPTH is specified in words, not bytes. + */ + *pulTimerTaskStackSize = configTIMER_TASK_STACK_DEPTH; + } +#endif + +/* This function is called when configUSE_IDLE_HOOK is 1 in FreeRTOSConfig.h */ +void vApplicationIdleHook( void ) +{ + void vApplicationLoadHook(); + + vApplicationLoadHook(); + + __asm__ volatile ("wfi"); +} + +/* This function is called when configUSE_MINIMAL_IDLE_HOOK is 1 in FreeRTOSConfig.h */ +void vApplicationMinimalIdleHook( void ) +{ + void vApplicationLoadHook(); + + vApplicationLoadHook(); + + __asm__ volatile ("wfi"); +} + +/* initialize high resolution timer for CPU and task load calculation */ +void vPortConfigTimerForRunTimeStats() +{ + /* we assume clock is initialized before the schedular is started */ +} + +/* return current counter value of high speed counter in units of usecs */ +uint32_t uiPortGetRunTimeCounterValue() +{ + uint64_t timeInUsecs = ClockP_getTimeUsec(); + + /* note, there is no overflow protection for this 32b value in FreeRTOS + * + * This value will overflow in + * ((0xFFFFFFFF)/(1000000*60)) minutes ~ 71 minutes + * + * We call vApplicationLoadHook() in idle loop to accumlate the task load into a 64b value. + * The implementation of vApplicationLoadHook() is in source\kernel\freertos\dpl\common\TaskP_freertos.c + */ + return (uint32_t)(timeInUsecs); +} + +int32_t Signal_coreIntr( CSL_gic500_gicrRegs *pGic500GicrRegs, uint32_t coreId, uint32_t intrNum ) +{ + if ( coreId < configNUM_CORES ) + { + if ( intrNum < HWIP_GICD_SGI_PPI_INTR_ID_MAX ) + { + uint32_t mask = 1 << intrNum; + pGic500GicrRegs->CORE[coreId].SGI_PPI.ISPENDR0 = mask; + } + } + + __asm("dsb sy"); + + return SystemP_SUCCESS; +} + +/* Read 64b value shared between cores */ +uint64_t Get_64(volatile uint64_t* x) +{ + __asm("dsb sy"); + return *x; +} + +/* Write 64b value shared between cores */ +void Set_64(volatile uint64_t* x, uint64_t value) +{ + *x = value; + __asm("dsb sy"); +} + diff --git a/Source/portable/ThirdParty/Partner-Supported-Ports/TI/CORTEX_A53_64-BIT_TI_AM64_SMP/portASM.S b/Source/portable/ThirdParty/Partner-Supported-Ports/TI/CORTEX_A53_64-BIT_TI_AM64_SMP/portASM.S new file mode 100644 index 000000000..266fd9765 --- /dev/null +++ b/Source/portable/ThirdParty/Partner-Supported-Ports/TI/CORTEX_A53_64-BIT_TI_AM64_SMP/portASM.S @@ -0,0 +1,602 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ +/* + * Copyright (C) 2018-2022 Texas Instruments Incorporated + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + + .text + + /* Variables and functions. */ + .extern vTaskSwitchContext + .extern HwiP_intrHandler + .extern ullPortInterruptNesting + .extern ullPortTaskHasFPUContext + .extern ullPortYieldRequired + + .global HwiP_IRQ_Handler + .global HwiP_SVC_Handler + .global vPortRestoreTaskContext + .global HwiP_defaultExcHandler + .global HwiP_abortHandler + +.macro PUSH_ALL_CPU_REGS stackPtr + stp x0, x1, [\stackPtr, #-16]! + stp x2, x3, [\stackPtr, #-16]! + stp x4, x5, [\stackPtr, #-16]! + stp x6, x7, [\stackPtr, #-16]! + stp x8, x9, [\stackPtr, #-16]! + stp x10, x11, [\stackPtr, #-16]! + stp x12, x13, [\stackPtr, #-16]! + stp x14, x15, [\stackPtr, #-16]! + stp x16, x17, [\stackPtr, #-16]! + stp x18, x19, [\stackPtr, #-16]! + stp x20, x21, [\stackPtr, #-16]! + stp x22, x23, [\stackPtr, #-16]! + stp x24, x25, [\stackPtr, #-16]! + stp x26, x27, [\stackPtr, #-16]! + stp x28, x29, [\stackPtr, #-16]! + stp x30, xzr, [\stackPtr, #-16]! +.endm + +.macro POP_ALL_CPU_REGS stackPtr + LDP X30, XZR, [\stackPtr], #0x10 + LDP X28, X29, [\stackPtr], #0x10 + LDP X26, X27, [\stackPtr], #0x10 + LDP X24, X25, [\stackPtr], #0x10 + LDP X22, X23, [\stackPtr], #0x10 + LDP X20, X21, [\stackPtr], #0x10 + LDP X18, X19, [\stackPtr], #0x10 + LDP X16, X17, [\stackPtr], #0x10 + LDP X14, X15, [\stackPtr], #0x10 + LDP X12, X13, [\stackPtr], #0x10 + LDP X10, X11, [\stackPtr], #0x10 + LDP X8, X9, [\stackPtr], #0x10 + LDP X6, X7, [\stackPtr], #0x10 + LDP X4, X5, [\stackPtr], #0x10 + LDP X2, X3, [\stackPtr], #0x10 + LDP X0, X1, [\stackPtr], #0x10 +.endm + +.macro PUSH_CALLER_SAVE_CPU_REGS stackPtr + stp x0, x1, [\stackPtr, #-16]! + stp x2, x3, [\stackPtr, #-16]! + stp x4, x5, [\stackPtr, #-16]! + stp x6, x7, [\stackPtr, #-16]! + stp x8, x9, [\stackPtr, #-16]! + stp x10, x11, [\stackPtr, #-16]! + stp x12, x13, [\stackPtr, #-16]! + stp x14, x15, [\stackPtr, #-16]! + stp x16, x17, [\stackPtr, #-16]! + stp x18, x19, [\stackPtr, #-16]! + stp x29, x30, [\stackPtr, #-16]! +.endm + +.macro POP_CALLER_SAVE_CPU_REGS stackPtr + ldp x29, x30, [\stackPtr], #16 + ldp x18, x19, [\stackPtr], #16 + ldp x16, x17, [\stackPtr], #16 + ldp x14, x15, [\stackPtr], #16 + ldp x12, x13, [\stackPtr], #16 + ldp x10, x11, [\stackPtr], #16 + ldp x8, x9, [\stackPtr], #16 + ldp x6, x7, [\stackPtr], #16 + ldp x4, x5, [\stackPtr], #16 + ldp x2, x3, [\stackPtr], #16 + ldp x0, x1, [\stackPtr], #16 +.endm + +.macro PUSH_CALLER_SAVE_FPU_REGS stackPtr + stp q0, q1, [\stackPtr, #-32]! + stp q2, q3, [\stackPtr, #-32]! + stp q4, q5, [\stackPtr, #-32]! + stp q6, q7, [\stackPtr, #-32]! + stp q8, q9, [\stackPtr, #-32]! + stp q10, q11, [\stackPtr, #-32]! + stp q12, q13, [\stackPtr, #-32]! + stp q14, q15, [\stackPtr, #-32]! + stp q16, q17, [\stackPtr, #-32]! + stp q18, q19, [\stackPtr, #-32]! + stp q20, q21, [\stackPtr, #-32]! + stp q22, q23, [\stackPtr, #-32]! + stp q24, q25, [\stackPtr, #-32]! + stp q26, q27, [\stackPtr, #-32]! + stp q28, q29, [\stackPtr, #-32]! + stp q30, q31, [\stackPtr, #-32]! +.endm + +.macro POP_CALLER_SAVE_FPU_REGS stackPtr + ldp q30, q31, [\stackPtr], #32 + ldp q28, q29, [\stackPtr], #32 + ldp q26, q27, [\stackPtr], #32 + ldp q24, q25, [\stackPtr], #32 + ldp q22, q23, [\stackPtr], #32 + ldp q20, q21, [\stackPtr], #32 + ldp q18, q19, [\stackPtr], #32 + ldp q16, q17, [\stackPtr], #32 + ldp q14, q15, [\stackPtr], #32 + ldp q12, q13, [\stackPtr], #32 + ldp q10, q11, [\stackPtr], #32 + ldp q8, q9, [\stackPtr], #32 + ldp q6, q7, [\stackPtr], #32 + ldp q4, q5, [\stackPtr], #32 + ldp q2, q3, [\stackPtr], #32 + ldp q0, q1, [\stackPtr], #32 +.endm + + +.macro portSAVE_CONTEXT + + /* Switch to use the EL0 stack pointer. */ + MSR SPSEL, #0 + + /* Save the entire context. */ + PUSH_ALL_CPU_REGS SP + + /* Save the SPSR. */ + MRS X3, SPSR_EL1 + MRS X2, ELR_EL1 + + STP X2, X3, [SP, #-0x10]! + + /* Get coreId to X1 */ + MRS X1, MPIDR_EL1 + AND X1, X1, #0xff + LDR X0, ullPortTaskHasFPUContextConst + CMP X1, #0 + BEQ 3f + ADD X0, X0, #8 +3: + + /* Save the FPU context indicator. */ + LDR X2, [X0] + + /* Save the FPU context, if any (32 128-bit registers). */ + CMP X2, #0 + B.EQ 1f + PUSH_CALLER_SAVE_FPU_REGS SP + +1: + /* Store the FPU context indicator. */ + STR x2, [SP, #-0x10]! + + LDR X0, pxCurrentTCBConst + + /* Get coreId and choose the corresponding index for core in pxCurrentTCB */ + MRS X1, MPIDR_EL1 + AND X1, X1, #0xff + CMP X1, #0 + B.EQ 2f + ADD X0, X0, #8 + +2: + LDR X1, [X0] + MOV X0, SP /* Move SP into X0 for saving. */ + STR X0, [X1] + + /* Switch to use the ELx stack pointer. */ + MSR SPSEL, #1 + +.endm + +; /**********************************************************************/ + +.macro portRESTORE_CONTEXT + + /* Switch to use the EL0 stack pointer. */ + MSR SPSEL, #0 + + /* Set the SP to point to the stack of the task being restored. */ + LDR X0, pxCurrentTCBConst + + /* Get coreId and choose the corresponding index for core in pxCurrentTCB */ + MRS X1, MPIDR_EL1 + AND X1, X1, #0xff + CMP X1, #0 + B.EQ 2f + ADD X0, X0, #8 + +2: + LDR X1, [X0] + LDR X0, [X1] + MOV SP, X0 + + LDR X2, [SP], #0x10 /* FPU context. */ + + /* Set the PMR register to be correct for the current critical nesting + depth. */ + MOV X1, #255 /* X1 holds the unmask value. */ + + MSR s3_0_c4_c6_0, X1 /* Write the mask value to ICCPMR. s3_0_c4_c6_0 is ICC_PMR_EL1. */ + DSB SY /* _RB_Barriers probably not required here. */ + ISB SY + + /* Get coreId */ + MRS X1, MPIDR_EL1 + AND X1, X1, #0xff + LDR X0, ullPortTaskHasFPUContextConst + BEQ 3f + ADD X0, X0, #8 +3: + + /* Restore the FPU context indicator. */ + STR X2, [X0] + + /* Restore the FPU context, if any. */ + CMP X2, #0 + B.EQ 1f + POP_CALLER_SAVE_FPU_REGS SP +1: + LDP X2, X3, [SP], #0x10 /* SPSR and ELR. */ + + /* Restore the SPSR. */ + MSR SPSR_EL1, X3 + /* Restore the ELR. */ + MSR ELR_EL1, X2 + + POP_ALL_CPU_REGS SP + + /* Switch to use the ELx stack pointer. _RB_ Might not be required. */ + MSR SPSEL, #1 + + ERET + +.endm + +.macro VECTOR_ENTRY name + .align 7 +\name: +.endm + + .global HwiP_gicv3Vectors + .section .vecs, "ax" + .align 11 +HwiP_gicv3Vectors: + +/* + ************************************************************************* + * Exception from currentEL, using SP0 + ************************************************************************* + */ +VECTOR_ENTRY el1SyncSP0 + B HwiP_SVC_Handler + +VECTOR_ENTRY el1IrqSP0 + B HwiP_IRQ_Handler + +VECTOR_ENTRY el1FiqSP0 + b el1FiqSP0 + +VECTOR_ENTRY el1SErrorSP0 + PUSH_ALL_CPU_REGS sp /* save all CPU regs */ + mrs x0, sp_el0 + mrs x1, elr_el1 + mrs x2, spsr_el1 + mrs x3, esr_el1 + stp x0, x1, [sp, #-16]! /* save sp & elr */ + stp x2, x3, [sp, #-16]! /* save spsr and esr */ + mov x0, sp + mov x1, #1 + ldr x2, =HwiP_defaultExcHandler + br x2 + +/* + ************************************************************************* + * Exception from currentEL, using SPx + ************************************************************************* + */ +VECTOR_ENTRY el1SyncSPx + B HwiP_SVC_Handler + +VECTOR_ENTRY el1IrqSPx + B HwiP_IRQ_Handler + +VECTOR_ENTRY el1FiqSPx + b el1FiqSPx + +VECTOR_ENTRY el1SErrorSPx + PUSH_ALL_CPU_REGS sp /* save all CPU regs */ + add x0, sp, #256 /* compute original SP */ + mrs x1, elr_el1 + mrs x2, spsr_el1 + mrs x3, esr_el1 + stp x0, x1, [sp, #-16]! /* save sp & elr */ + stp x2, x3, [sp, #-16]! /* save spsr and esr */ + mov x0, sp + mov x1, #1 + ldr x2, =HwiP_defaultExcHandler + br x2 + +/* + ************************************************************************* + * Exception from lowerEL, all lowerEL using Aarch64 + ************************************************************************* + */ +VECTOR_ENTRY el0SyncAarch64 + b el0SyncAarch64 + +VECTOR_ENTRY el0IrqAarch64 + b el0IrqAarch64 + +VECTOR_ENTRY el0FiqAarch64 + b el0FiqAarch64 + +VECTOR_ENTRY el0SErrorAarch64 + b el0SErrorAarch64 + +/* + ************************************************************************* + * Exception from lowerEL, all lowerEL using Aarch32 + ************************************************************************* + */ +VECTOR_ENTRY el0SyncAarch32 + b el0SyncAarch32 + +VECTOR_ENTRY el0IrqAarch32 + b el0IrqAarch32 + +VECTOR_ENTRY el0FiqAarch32 + b el0FiqAarch32 + +VECTOR_ENTRY el0SErrorAarch32 + b el0SErrorAarch32 + + +/****************************************************************************** + * vPortRestoreTaskContext is used to start the scheduler. + *****************************************************************************/ +.align 8 +.type vPortRestoreTaskContext, %function +vPortRestoreTaskContext: + DSB SY + ISB SY + /* Start the first task. */ + portRESTORE_CONTEXT + +/****************************************************************************** + * handles SVC entry and exit. + *****************************************************************************/ +.align 8 +.type HwiP_SVC_Handler, %function +HwiP_SVC_Handler: + /* Save the context of the current task and select a new task to run. */ + portSAVE_CONTEXT + MRS X0, ESR_EL1 + MRS X2, ELR_EL1 + LSR X1, X0, #26 + CMP X1, #0x15 /* 0x15 = SVC instruction. */ + B.NE HwiP_SVC_Abort + MRS x0, mpidr_el1 /* Get CoreID */ + and x0, x0, #0xff + BL vTaskSwitchContext + portRESTORE_CONTEXT +HwiP_SVC_Abort: + /* Full ESR is in X0, exception class code is in X1. */ + B . + +/****************************************************************************** + * handles IRQ entry and exit. + *****************************************************************************/ +.align 8 +.type HwiP_IRQ_Handler, %function +HwiP_IRQ_Handler: + /* save cpu scratch regs */ + PUSH_CALLER_SAVE_CPU_REGS SP + + /* Save the SPSR and ELR. */ + MRS X3, SPSR_EL1 + MRS X2, ELR_EL1 + STP X2, X3, [SP, #-0x10]! + + /* Increment the interrupt nesting counter. */ + LDR X5, ullPortInterruptNestingConst + + /* Get coreId and choose the corresponding index for core in ullPortInterruptNesting */ + MRS X1, MPIDR_EL1 + AND X1, X1, #0xff + CMP X1, #0 + B.EQ 2f + ADD X5, X5, #8 +2: + LDR X1, [X5] /* Old nesting count in X1. */ + ADD X6, X1, #1 + STR X6, [X5] /* Address of nesting count variable in X5. */ + + /* Maintain the interrupt nesting information across the function call. */ + STP X1, X5, [SP, #-0x10]! + + /* Call the C handler. */ + BL HwiP_intrHandler + + /* Disable interrupts. */ + MSR DAIFSET, #2 + DSB SY + ISB SY + + /* Restore the critical nesting count. */ + LDP X1, X5, [SP], #0x10 + STR X1, [X5] + + /* Has interrupt nesting unwound? */ + CMP X1, #0 + B.NE Exit_IRQ_No_Context_Switch + + /* Is a context switch required? */ + LDR X0, ullPortYieldRequiredConst + + /* Get coreId and choose the corresponding index for core in ullPortYieldRequired */ + MRS X1, MPIDR_EL1 + AND X1, X1, #0xff + CMP X1, #0 + B.EQ 2f + ADD X0, X0, #8 +2: + LDR X1, [X0] + CMP X1, #0 + B.EQ Exit_IRQ_No_Context_Switch + + /* Reset ullPortYieldRequired to 0. */ + MOV X2, #0 + STR X2, [X0] + + /* Restore volatile registers. */ + LDP X4, X5, [SP], #0x10 /* SPSR and ELR. */ + MSR SPSR_EL1, X5 + MSR ELR_EL1, X4 + DSB SY + ISB SY + + POP_CALLER_SAVE_CPU_REGS SP + + /* Save the context of the current task and select a new task to run. */ + portSAVE_CONTEXT + MRS x0, mpidr_el1 /* Get CoreID */ + and x0, x0, #0xff + BL vTaskSwitchContext + portRESTORE_CONTEXT + +Exit_IRQ_No_Context_Switch: + /* Restore volatile registers. */ + LDP X4, X5, [SP], #0x10 /* SPSR and ELR. */ + MSR SPSR_EL1, X5 + MSR ELR_EL1, X4 + DSB SY + ISB SY + + POP_CALLER_SAVE_CPU_REGS SP + + ERET + +/* + * Void HwiP_defaultExcHandler(uint32_t usingEL0Stack); + */ + .section .text.HwiP_defaultExcHandler, "ax" + .func HwiP_defaultExcHandler +HwiP_defaultExcHandler: + + mov x19, x0 /* copy 'usingEL0Stack' argument */ + mrs x0, spsr_el1 + mrs x1, elr_el1 + stp x0, x1, [sp, #-16]! /* save spsr_el1 and elr_el1 */ +#if defined(__ARM_FP) + mrs x0, fpcr + mrs x1, fpsr + stp x0, x1, [sp, #-16]! /* save fpcr and fpsr */ +#endif + + /* call dispatch default handler */ + mrs x0, elr_el1 /* pass IRP to dispatchIRQC() */ + ldr x1, =HwiP_defaultHandler + blr x1 + + /* returns with interrupts disabled */ +#if defined(__ARM_FP) + ldp x0, x1, [sp], #16 + msr fpcr, x0 + msr fpsr, x1 +#endif + ldp x0, x1, [sp], #16 + msr spsr_el1, x0 + msr elr_el1, x1 +#if defined(__ARM_FP) + POP_CALLER_SAVE_FPU_REGS sp /* restore vfp scratch regs */ +#endif + POP_CALLER_SAVE_CPU_REGS sp /* restore cpu scratch regs */ + eret + +.align 8 + +/* + * int32_t GateSmp_tryLock(uintptr_t gateWord); + */ + .global GateSmp_tryLock + .type GateSmp_tryLock , %function +GateSmp_tryLock: + ldxr w1, [x0] + cmp w1, #1 /* is locked already? */ + beq 1f /* if so, leave with fail */ + + mov w2, #1 /* locked = 1 */ + stxr w1, w2, [x0] /* if so attempt to grab it */ + cmp w1, #0 /* did we get it? zero is yes */ + /* if not, loop while in contention */ + bne GateSmp_tryLock +1: + mov w0, w1 + dmb sy + ret + +/* + * void GateSmp_unlock(uintptr_t gateWord); + */ + .global GateSmp_unlock + .type GateSmp_unlock , %function + +GateSmp_unlock: + dmb sy + + mov w1, #0 + str w1, [x0] + + dsb sy + sev /* let everyone know */ + ret + +pxCurrentTCBConst: .dword pxCurrentTCBs +ullPortTaskHasFPUContextConst: .dword ullPortTaskHasFPUContext +ullPortInterruptNestingConst: .dword ullPortInterruptNesting +ullPortYieldRequiredConst: .dword ullPortYieldRequired + +.end diff --git a/Source/portable/ThirdParty/Partner-Supported-Ports/TI/CORTEX_A53_64-BIT_TI_AM64_SMP/portmacro.h b/Source/portable/ThirdParty/Partner-Supported-Ports/TI/CORTEX_A53_64-BIT_TI_AM64_SMP/portmacro.h new file mode 100644 index 000000000..126b9ff3c --- /dev/null +++ b/Source/portable/ThirdParty/Partner-Supported-Ports/TI/CORTEX_A53_64-BIT_TI_AM64_SMP/portmacro.h @@ -0,0 +1,294 @@ +/* + * FreeRTOS Kernel V10.4.3 + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + * 1 tab == 4 spaces! + */ +/* + * Copyright (C) 2018-2022 Texas Instruments Incorporated + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef PORTMACRO_H +#define PORTMACRO_H + +#ifdef __cplusplus + extern "C" { +#endif + +#include +#include +#include + +/*----------------------------------------------------------- + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the given hardware + * and compiler. + * + * These settings should not be altered. + *----------------------------------------------------------- + */ + +/* Type definitions. */ +#define portCHAR char +#define portFLOAT float +#define portDOUBLE double +#define portLONG long +#define portSHORT short +#define portSTACK_TYPE size_t +#define portBASE_TYPE long + +typedef portSTACK_TYPE StackType_t; +typedef portBASE_TYPE BaseType_t; +typedef uint64_t UBaseType_t; + +typedef uint32_t TickType_t; +#define portMAX_DELAY ( ( TickType_t ) 0xffffffff ) + +/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do +not need to be guarded with a critical section. */ +#define portTICK_TYPE_IS_ATOMIC 1 + +/* Hardware specifics. */ +#define portSTACK_GROWTH ( -1 ) +#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) +#define portBYTE_ALIGNMENT 16 +#define portPOINTER_SIZE_TYPE uint64_t +#define portCRITICAL_NESTING_IN_TCB 1 + +/* Task utilities. */ + +extern uint64_t ullPortYieldRequired[]; +/* Called at the end of an ISR that can cause a context switch. */ +#define portEND_SWITCHING_ISR( xSwitchRequired ) \ +{ \ + \ + if( xSwitchRequired != pdFALSE ) \ + { \ + ullPortYieldRequired[portGET_CORE_ID()] = pdTRUE; \ + } \ +} + +#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x ) +#define portYIELD() __asm volatile ( "SVC 0" ::: "memory" ) + +/*----------------------------------------------------------- + * Critical section control + *----------------------------------------------------------*/ + +extern void vTaskEnterCritical( void ); +extern void vTaskExitCritical( void ); + +#define portDISABLE_INTERRUPTS() HwiP_disable() +#define portENABLE_INTERRUPTS() HwiP_enable() +#define portENTER_CRITICAL() vTaskEnterCritical(); +#define portEXIT_CRITICAL() vTaskExitCritical(); +#define portSET_INTERRUPT_MASK_FROM_ISR() ({ \ + uint64_t x = HwiP_disable(); \ + vTaskEnterCritical(); \ + x; \ + }) + +#define portCLEAR_INTERRUPT_MASK_FROM_ISR(x) ({ \ + vTaskExitCritical(); \ + HwiP_restore(x); \ + }) + +/* Task function macros as described on the FreeRTOS.org WEB site. These are +not required for this port but included in case common demo code that uses these +macros is used. */ +#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters ) +#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters ) + +/* Any task that uses the floating point unit MUST call vPortTaskUsesFPU() +before any floating point instructions are executed. */ +void vPortTaskUsesFPU( void ); +#define portTASK_USES_FLOATING_POINT() vPortTaskUsesFPU() + +/* Architecture specific optimisations. */ +#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION + #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1 +#endif + +#if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 + + /* Store/clear the ready priorities in a bit map. */ + #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) ) + #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) ) + + #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31 - __builtin_clz( uxReadyPriorities ) ) + +#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */ + +#define portNOP() __asm volatile( "NOP" ) +#define portINLINE __inline +#define portMEMORY_BARRIER() __asm volatile( "" ::: "memory" ) + +/* port for SMP */ +#define portGET_CORE_ID() Armv8_getCoreId() +#define portRESTORE_INTERRUPTS( ulState ) HwiP_restore ( ulState ) +#define portCHECK_IF_IN_ISR() HwiP_inISR() + +/*----------------------------------------------------------- + * Critical section locks + *----------------------------------------------------------*/ + +#define ISR_LOCK (0u) +#define TASK_LOCK (1u) + +#define portRTOS_LOCK_COUNT 2 +#define portMAX_CORE_COUNT 2 + +#define portRELEASE_ISR_LOCK() vPortRecursiveLock(ISR_LOCK, pdFALSE) +#define portGET_ISR_LOCK() vPortRecursiveLock(ISR_LOCK, pdTRUE) + +#define portRELEASE_TASK_LOCK() vPortRecursiveLock(TASK_LOCK, pdFALSE) +#define portGET_TASK_LOCK() vPortRecursiveLock(TASK_LOCK, pdTRUE) + +/* Interrupt number to interrupt a core for task yield */ +#define YIELD_CORE_INTERRUPT_NO (0U) + +extern int32_t Signal_coreIntr( CSL_gic500_gicrRegs *pGic500GicrRegs, uint32_t coreId, uint32_t intrNum ); + +#define portYIELD_CORE( xCoreID ) do { \ + Signal_coreIntr((CSL_gic500_gicrRegs *) ( HWIP_GIC_BASE_ADDR + \ + CSL_GIC500_GICR_CORE_CONTROL_CTLR(0U)), xCoreID, YIELD_CORE_INTERRUPT_NO); \ + }while(0); + + +uint64_t Get_64(volatile uint64_t* x); +void Set_64(volatile uint64_t* x, uint64_t value); + +/* Which core owns the lock */ +volatile uint64_t ucOwnedByCore[ portMAX_CORE_COUNT ]; +/* Lock count a core owns */ +volatile uint64_t ucRecursionCountByLock[ portRTOS_LOCK_COUNT ]; + +/* Index 0 is used for ISR lock and Index 1 is used for task lock */ +uint32_t GateWord[ portRTOS_LOCK_COUNT ]; + +int32_t GateSmp_tryLock(uint32_t* gateWord); +void GateSmp_unlock(uint32_t* gateWord); + +static inline void vPortRecursiveLock(uint32_t ulLockNum, BaseType_t uxAcquire) +{ + uint32_t ulCoreNum = portGET_CORE_ID(); + uint32_t ulLockBit = 1u << ulLockNum; + + /* Lock acquire */ + if (uxAcquire) + { + + /* Check if spinlock is available */ + /* If spinlock is not available check if the core owns the lock */ + /* If the core owns the lock wait increment the lock count by the core */ + /* If core does not own the lock wait for the spinlock */ + if( GateSmp_tryLock( &GateWord[ulLockNum] ) != 0) + { + /* Check if the core owns the spinlock */ + if( Get_64(&ucOwnedByCore[ulCoreNum]) & ulLockBit ) + { + configASSERT( Get_64(&ucRecursionCountByLock[ulLockNum]) != 255u); + Set_64(&ucRecursionCountByLock[ulLockNum], (Get_64(&ucRecursionCountByLock[ulLockNum])+1)); + return; + } + + /* Preload the gate word into the cache */ + uint32_t dummy = GateWord[ulLockNum]; + dummy++; + + /* Wait for spinlock */ + while( GateSmp_tryLock(&GateWord[ulLockNum]) != 0); + } + + /* Add barrier to ensure lock is taken before we proceed */ + __asm__ __volatile__ ( + "dmb sy" + ::: "memory" + ); + + /* Assert the lock count is 0 when the spinlock is free and is acquired */ + configASSERT(Get_64(&ucRecursionCountByLock[ulLockNum]) == 0); + + /* Set lock count as 1 */ + Set_64(&ucRecursionCountByLock[ulLockNum], 1); + /* Set ucOwnedByCore */ + Set_64(&ucOwnedByCore[ulCoreNum], (Get_64(&ucOwnedByCore[ulCoreNum]) | ulLockBit)); + } + /* Lock release */ + else + { + /* Assert the lock is not free already */ + configASSERT( (Get_64(&ucOwnedByCore[ulCoreNum]) & ulLockBit) != 0 ); + configASSERT( Get_64(&ucRecursionCountByLock[ulLockNum]) != 0 ); + + /* Reduce ucRecursionCountByLock by 1 */ + Set_64(&ucRecursionCountByLock[ulLockNum], (Get_64(&ucRecursionCountByLock[ulLockNum]) - 1) ); + + if( !Get_64(&ucRecursionCountByLock[ulLockNum]) ) + { + Set_64(&ucOwnedByCore[ulCoreNum], (Get_64(&ucOwnedByCore[ulCoreNum]) & ~ulLockBit)); + GateSmp_unlock(&GateWord[ulLockNum]); + /* Add barrier to ensure lock is taken before we proceed */ + __asm__ __volatile__ ( + "dmb sy" + ::: "memory" + ); + } + } +} + +#ifdef __cplusplus + } /* extern C */ +#endif + +#endif /* PORTMACRO_H */ + diff --git a/Source/portable/ThirdParty/XCC/Xtensa/port.c b/Source/portable/ThirdParty/XCC/Xtensa/port.c index e64456280..f5aa4b950 100644 --- a/Source/portable/ThirdParty/XCC/Xtensa/port.c +++ b/Source/portable/ThirdParty/XCC/Xtensa/port.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2015-2019 Cadence Design Systems, Inc. * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * @@ -37,34 +37,39 @@ /* Defined in portasm.h */ -extern void _frxt_tick_timer_init(void); +extern void _frxt_tick_timer_init( void ); /* Defined in xtensa_context.S */ -extern void _xt_coproc_init(void); +extern void _xt_coproc_init( void ); /*-----------------------------------------------------------*/ /* We require the address of the pxCurrentTCB variable, but don't want to know -any details of its type. */ + * any details of its type. */ typedef void TCB_t; extern volatile TCB_t * volatile pxCurrentTCB; -unsigned port_xSchedulerRunning = 0; // Duplicate of inaccessible xSchedulerRunning; needed at startup to avoid counting nesting -unsigned port_interruptNesting = 0; // Interrupt nesting level +unsigned port_xSchedulerRunning = 0; /* Duplicate of inaccessible xSchedulerRunning; needed at startup to avoid counting nesting */ +unsigned port_interruptNesting = 0; /* Interrupt nesting level */ /*-----------------------------------------------------------*/ -// User exception dispatcher when exiting -void _xt_user_exit(void); +/* User exception dispatcher when exiting */ +void _xt_user_exit( void ); /* * Stack initialization */ #if portUSING_MPU_WRAPPERS -StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters, BaseType_t xRunPrivileged ) + StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, + TaskFunction_t pxCode, + void * pvParameters, + BaseType_t xRunPrivileged ) #else -StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters ) + StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, + TaskFunction_t pxCode, + void * pvParameters ) #endif { StackType_t * sp; @@ -129,18 +134,18 @@ StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t px void vPortEndScheduler( void ) { /* It is unlikely that the Xtensa port will get stopped. If required simply - disable the tick interrupt here. */ + * disable the tick interrupt here. */ } /*-----------------------------------------------------------*/ BaseType_t xPortStartScheduler( void ) { - // Interrupts are disabled at this point and stack contains PS with enabled interrupts when task context is restored + /* Interrupts are disabled at this point and stack contains PS with enabled interrupts when task context is restored */ #if XCHAL_CP_NUM > 0 - /* Initialize co-processor management for tasks. Leave CPENABLE alone. */ - _xt_coproc_init(); + /* Initialize co-processor management for tasks. Leave CPENABLE alone. */ + _xt_coproc_init(); #endif /* Init the tick divisor value */ @@ -150,14 +155,14 @@ BaseType_t xPortStartScheduler( void ) _frxt_tick_timer_init(); #if XT_USE_THREAD_SAFE_CLIB - // Init C library - vPortClibInit(); + /* Init C library */ + vPortClibInit(); #endif port_xSchedulerRunning = 1; - // Cannot be directly called from C; never returns - __asm__ volatile ("call0 _frxt_dispatch\n"); + /* Cannot be directly called from C; never returns */ + __asm__ volatile ( "call0 _frxt_dispatch\n" ); /* Should not get here. */ return pdTRUE; @@ -190,19 +195,19 @@ BaseType_t xPortSysTickHandler( void ) * Used to set coprocessor area in stack. Current hack is to reuse MPU pointer for coprocessor area. */ #if portUSING_MPU_WRAPPERS -void vPortStoreTaskMPUSettings( xMPU_SETTINGS * xMPUSettings, - const struct xMEMORY_REGION * const xRegions, - StackType_t * pxBottomOfStack, - uint32_t ulStackDepth ) -{ - #if XCHAL_CP_NUM > 0 - xMPUSettings->coproc_area = ( StackType_t * ) ( ( uint32_t ) ( pxBottomOfStack + ulStackDepth - 1 )); - xMPUSettings->coproc_area = ( StackType_t * ) ( ( ( portPOINTER_SIZE_TYPE ) xMPUSettings->coproc_area ) & ( ~( ( portPOINTER_SIZE_TYPE ) portBYTE_ALIGNMENT_MASK ) ) ); - xMPUSettings->coproc_area = ( StackType_t * ) ( ( ( uint32_t ) xMPUSettings->coproc_area - XT_CP_SIZE ) & ~0xf ); - - /* NOTE: we cannot initialize the coprocessor save area here because FreeRTOS is going to - * clear the stack area after we return. This is done in pxPortInitialiseStack(). - */ - #endif -} + void vPortStoreTaskMPUSettings( xMPU_SETTINGS * xMPUSettings, + const struct xMEMORY_REGION * const xRegions, + StackType_t * pxBottomOfStack, + uint32_t ulStackDepth ) + { + #if XCHAL_CP_NUM > 0 + xMPUSettings->coproc_area = ( StackType_t * ) ( ( uint32_t ) ( pxBottomOfStack + ulStackDepth - 1 ) ); + xMPUSettings->coproc_area = ( StackType_t * ) ( ( ( portPOINTER_SIZE_TYPE ) xMPUSettings->coproc_area ) & ( ~( ( portPOINTER_SIZE_TYPE ) portBYTE_ALIGNMENT_MASK ) ) ); + xMPUSettings->coproc_area = ( StackType_t * ) ( ( ( uint32_t ) xMPUSettings->coproc_area - XT_CP_SIZE ) & ~0xf ); + + /* NOTE: we cannot initialize the coprocessor save area here because FreeRTOS is going to + * clear the stack area after we return. This is done in pxPortInitialiseStack(). + */ + #endif + } #endif /* if portUSING_MPU_WRAPPERS */ diff --git a/Source/portable/ThirdParty/XCC/Xtensa/portasm.S b/Source/portable/ThirdParty/XCC/Xtensa/portasm.S index fb4e29428..3aa68bfac 100644 --- a/Source/portable/ThirdParty/XCC/Xtensa/portasm.S +++ b/Source/portable/ThirdParty/XCC/Xtensa/portasm.S @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2015-2019 Cadence Design Systems, Inc. * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * diff --git a/Source/portable/ThirdParty/XCC/Xtensa/portbenchmark.h b/Source/portable/ThirdParty/XCC/Xtensa/portbenchmark.h index 6202165f8..057013a6d 100644 --- a/Source/portable/ThirdParty/XCC/Xtensa/portbenchmark.h +++ b/Source/portable/ThirdParty/XCC/Xtensa/portbenchmark.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2015-2019 Cadence Design Systems, Inc. * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * @@ -42,7 +42,7 @@ #endif #define portbenchmarkINTERRUPT_DISABLE() -#define portbenchmarkINTERRUPT_RESTORE(newstate) +#define portbenchmarkINTERRUPT_RESTORE( newstate ) #define portbenchmarkIntLatency() #define portbenchmarkIntWait() #define portbenchmarkReset() diff --git a/Source/portable/ThirdParty/XCC/Xtensa/portclib.c b/Source/portable/ThirdParty/XCC/Xtensa/portclib.c index 671fd0a4f..c62cc46c5 100644 --- a/Source/portable/ThirdParty/XCC/Xtensa/portclib.c +++ b/Source/portable/ThirdParty/XCC/Xtensa/portclib.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2015-2019 Cadence Design Systems, Inc. * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * @@ -31,200 +31,204 @@ #if XT_USE_THREAD_SAFE_CLIB -#if XSHAL_CLIB == XTHAL_CLIB_XCLIB - -#include -#include - -#include "semphr.h" - -typedef SemaphoreHandle_t _Rmtx; - -//----------------------------------------------------------------------------- -// Override this and set to nonzero to enable locking. -//----------------------------------------------------------------------------- -int32_t _xclib_use_mt = 1; - - -//----------------------------------------------------------------------------- -// Init lock. -//----------------------------------------------------------------------------- -void -_Mtxinit(_Rmtx * mtx) -{ - *mtx = xSemaphoreCreateRecursiveMutex(); -} - -//----------------------------------------------------------------------------- -// Destroy lock. -//----------------------------------------------------------------------------- -void -_Mtxdst(_Rmtx * mtx) -{ - if ((mtx != NULL) && (*mtx != NULL)) { - vSemaphoreDelete(*mtx); - } -} - -//----------------------------------------------------------------------------- -// Lock. -//----------------------------------------------------------------------------- -void -_Mtxlock(_Rmtx * mtx) -{ - if ((mtx != NULL) && (*mtx != NULL)) { - xSemaphoreTakeRecursive(*mtx, portMAX_DELAY); - } -} - -//----------------------------------------------------------------------------- -// Unlock. -//----------------------------------------------------------------------------- -void -_Mtxunlock(_Rmtx * mtx) -{ - if ((mtx != NULL) && (*mtx != NULL)) { - xSemaphoreGiveRecursive(*mtx); - } -} - -//----------------------------------------------------------------------------- -// Called by malloc() to allocate blocks of memory from the heap. -//----------------------------------------------------------------------------- -void * -_sbrk_r (struct _reent * reent, int32_t incr) -{ - extern char _end; - extern char _heap_sentry; - static char * _heap_sentry_ptr = &_heap_sentry; - static char * heap_ptr; - char * base; - - if (!heap_ptr) - heap_ptr = (char *) &_end; - - base = heap_ptr; - if (heap_ptr + incr >= _heap_sentry_ptr) { - reent->_errno = ENOMEM; - return (char *) -1; - } - - heap_ptr += incr; - return base; -} - -//----------------------------------------------------------------------------- -// Global initialization for C library. -//----------------------------------------------------------------------------- -void -vPortClibInit(void) -{ -} - -//----------------------------------------------------------------------------- -// Per-thread cleanup stub provided for linking, does nothing. -//----------------------------------------------------------------------------- -void -_reclaim_reent(void * ptr) -{ -} - -#endif /* XSHAL_CLIB == XTHAL_CLIB_XCLIB */ - -#if XSHAL_CLIB == XTHAL_CLIB_NEWLIB - -#include -#include -#include -#include -#include - -#include "semphr.h" - -static SemaphoreHandle_t xClibMutex; -static uint32_t ulClibInitDone = 0; - -//----------------------------------------------------------------------------- -// Get C library lock. -//----------------------------------------------------------------------------- -void -__malloc_lock(struct _reent * ptr) -{ - if (!ulClibInitDone) - return; - - xSemaphoreTakeRecursive(xClibMutex, portMAX_DELAY); -} - -//----------------------------------------------------------------------------- -// Release C library lock. -//----------------------------------------------------------------------------- -void -__malloc_unlock(struct _reent * ptr) -{ - if (!ulClibInitDone) - return; - - xSemaphoreGiveRecursive(xClibMutex); -} - -//----------------------------------------------------------------------------- -// Lock for environment. Since we have only one global lock we can just call -// the malloc() lock function. -//----------------------------------------------------------------------------- -void -__env_lock(struct _reent * ptr) -{ - __malloc_lock(ptr); -} - - -//----------------------------------------------------------------------------- -// Unlock environment. -//----------------------------------------------------------------------------- -void -__env_unlock(struct _reent * ptr) -{ - __malloc_unlock(ptr); -} - -//----------------------------------------------------------------------------- -// Called by malloc() to allocate blocks of memory from the heap. -//----------------------------------------------------------------------------- -void * -_sbrk_r (struct _reent * reent, int32_t incr) -{ - extern char _end; - extern char _heap_sentry; - static char * _heap_sentry_ptr = &_heap_sentry; - static char * heap_ptr; - char * base; - - if (!heap_ptr) - heap_ptr = (char *) &_end; - - base = heap_ptr; - if (heap_ptr + incr >= _heap_sentry_ptr) { - reent->_errno = ENOMEM; - return (char *) -1; - } - - heap_ptr += incr; - return base; -} - -//----------------------------------------------------------------------------- -// Global initialization for C library. -//----------------------------------------------------------------------------- -void -vPortClibInit(void) -{ - configASSERT(!ulClibInitDone); - - xClibMutex = xSemaphoreCreateRecursiveMutex(); - ulClibInitDone = 1; -} - -#endif /* XSHAL_CLIB == XTHAL_CLIB_NEWLIB */ + #if XSHAL_CLIB == XTHAL_CLIB_XCLIB + + #include + #include + + #include "semphr.h" + + typedef SemaphoreHandle_t _Rmtx; + +/*----------------------------------------------------------------------------- */ +/* Override this and set to nonzero to enable locking. */ +/*----------------------------------------------------------------------------- */ + int32_t _xclib_use_mt = 1; + + +/*----------------------------------------------------------------------------- */ +/* Init lock. */ +/*----------------------------------------------------------------------------- */ + void _Mtxinit( _Rmtx * mtx ) + { + *mtx = xSemaphoreCreateRecursiveMutex(); + } + +/*----------------------------------------------------------------------------- */ +/* Destroy lock. */ +/*----------------------------------------------------------------------------- */ + void _Mtxdst( _Rmtx * mtx ) + { + if( ( mtx != NULL ) && ( *mtx != NULL ) ) + { + vSemaphoreDelete( *mtx ); + } + } + +/*----------------------------------------------------------------------------- */ +/* Lock. */ +/*----------------------------------------------------------------------------- */ + void _Mtxlock( _Rmtx * mtx ) + { + if( ( mtx != NULL ) && ( *mtx != NULL ) ) + { + xSemaphoreTakeRecursive( *mtx, portMAX_DELAY ); + } + } + +/*----------------------------------------------------------------------------- */ +/* Unlock. */ +/*----------------------------------------------------------------------------- */ + void _Mtxunlock( _Rmtx * mtx ) + { + if( ( mtx != NULL ) && ( *mtx != NULL ) ) + { + xSemaphoreGiveRecursive( *mtx ); + } + } + +/*----------------------------------------------------------------------------- */ +/* Called by malloc() to allocate blocks of memory from the heap. */ +/*----------------------------------------------------------------------------- */ + void * _sbrk_r( struct _reent * reent, + int32_t incr ) + { + extern char _end; + extern char _heap_sentry; + static char * _heap_sentry_ptr = &_heap_sentry; + static char * heap_ptr; + char * base; + + if( !heap_ptr ) + { + heap_ptr = ( char * ) &_end; + } + + base = heap_ptr; + + if( heap_ptr + incr >= _heap_sentry_ptr ) + { + reent->_errno = ENOMEM; + return ( char * ) -1; + } + + heap_ptr += incr; + return base; + } + +/*----------------------------------------------------------------------------- */ +/* Global initialization for C library. */ +/*----------------------------------------------------------------------------- */ + void vPortClibInit( void ) + { + } + +/*----------------------------------------------------------------------------- */ +/* Per-thread cleanup stub provided for linking, does nothing. */ +/*----------------------------------------------------------------------------- */ + void _reclaim_reent( void * ptr ) + { + } + + #endif /* XSHAL_CLIB == XTHAL_CLIB_XCLIB */ + + #if XSHAL_CLIB == XTHAL_CLIB_NEWLIB + + #include + #include + #include + #include + #include + + #include "semphr.h" + + static SemaphoreHandle_t xClibMutex; + static uint32_t ulClibInitDone = 0; + +/*----------------------------------------------------------------------------- */ +/* Get C library lock. */ +/*----------------------------------------------------------------------------- */ + void __malloc_lock( struct _reent * ptr ) + { + if( !ulClibInitDone ) + { + return; + } + + xSemaphoreTakeRecursive( xClibMutex, portMAX_DELAY ); + } + +/*----------------------------------------------------------------------------- */ +/* Release C library lock. */ +/*----------------------------------------------------------------------------- */ + void __malloc_unlock( struct _reent * ptr ) + { + if( !ulClibInitDone ) + { + return; + } + + xSemaphoreGiveRecursive( xClibMutex ); + } + +/*----------------------------------------------------------------------------- */ +/* Lock for environment. Since we have only one global lock we can just call */ +/* the malloc() lock function. */ +/*----------------------------------------------------------------------------- */ + void __env_lock( struct _reent * ptr ) + { + __malloc_lock( ptr ); + } + + +/*----------------------------------------------------------------------------- */ +/* Unlock environment. */ +/*----------------------------------------------------------------------------- */ + void __env_unlock( struct _reent * ptr ) + { + __malloc_unlock( ptr ); + } + +/*----------------------------------------------------------------------------- */ +/* Called by malloc() to allocate blocks of memory from the heap. */ +/*----------------------------------------------------------------------------- */ + void * _sbrk_r( struct _reent * reent, + int32_t incr ) + { + extern char _end; + extern char _heap_sentry; + static char * _heap_sentry_ptr = &_heap_sentry; + static char * heap_ptr; + char * base; + + if( !heap_ptr ) + { + heap_ptr = ( char * ) &_end; + } + + base = heap_ptr; + + if( heap_ptr + incr >= _heap_sentry_ptr ) + { + reent->_errno = ENOMEM; + return ( char * ) -1; + } + + heap_ptr += incr; + return base; + } + +/*----------------------------------------------------------------------------- */ +/* Global initialization for C library. */ +/*----------------------------------------------------------------------------- */ + void vPortClibInit( void ) + { + configASSERT( !ulClibInitDone ); + + xClibMutex = xSemaphoreCreateRecursiveMutex(); + ulClibInitDone = 1; + } + + #endif /* XSHAL_CLIB == XTHAL_CLIB_NEWLIB */ #endif /* XT_USE_THREAD_SAFE_CLIB */ diff --git a/Source/portable/ThirdParty/XCC/Xtensa/portmacro.h b/Source/portable/ThirdParty/XCC/Xtensa/portmacro.h index eda36f246..1e5b477fa 100644 --- a/Source/portable/ThirdParty/XCC/Xtensa/portmacro.h +++ b/Source/portable/ThirdParty/XCC/Xtensa/portmacro.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2015-2019 Cadence Design Systems, Inc. * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * @@ -38,15 +38,15 @@ #ifndef __ASSEMBLER__ -#include + #include -#include -#include -#include -#include /* required for XSHAL_CLIB */ -#include + #include + #include + #include + #include /* required for XSHAL_CLIB */ + #include -//#include "xtensa_context.h" +/*#include "xtensa_context.h" */ /*----------------------------------------------------------- * Port specific definitions. @@ -60,149 +60,159 @@ /* Type definitions. */ -#define portCHAR int8_t -#define portFLOAT float -#define portDOUBLE double -#define portLONG int32_t -#define portSHORT int16_t -#define portSTACK_TYPE uint32_t -#define portBASE_TYPE int - -typedef portSTACK_TYPE StackType_t; -typedef portBASE_TYPE BaseType_t; -typedef unsigned portBASE_TYPE UBaseType_t; - -#if( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS ) - typedef uint16_t TickType_t; - #define portMAX_DELAY ( TickType_t ) 0xffff -#elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS ) - typedef uint32_t TickType_t; - #define portMAX_DELAY ( TickType_t ) 0xffffffffUL -#else - #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width. -#endif + #define portCHAR int8_t + #define portFLOAT float + #define portDOUBLE double + #define portLONG int32_t + #define portSHORT int16_t + #define portSTACK_TYPE uint32_t + #define portBASE_TYPE int + + typedef portSTACK_TYPE StackType_t; + typedef portBASE_TYPE BaseType_t; + typedef unsigned portBASE_TYPE UBaseType_t; + + #if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS ) + typedef uint16_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffff + #elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS ) + typedef uint32_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffffffffUL + #else + #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width. + #endif /*-----------------------------------------------------------*/ -// portbenchmark -#include "portbenchmark.h" +/* portbenchmark */ + #include "portbenchmark.h" /* Critical section management. NW-TODO: replace XTOS_SET_INTLEVEL with more efficient version, if any? */ -// These cannot be nested. They should be used with a lot of care and cannot be called from interrupt level. -#define portDISABLE_INTERRUPTS() do { XTOS_SET_INTLEVEL(XCHAL_EXCM_LEVEL); portbenchmarkINTERRUPT_DISABLE(); } while (0) -#define portENABLE_INTERRUPTS() do { portbenchmarkINTERRUPT_RESTORE(0); XTOS_SET_INTLEVEL(0); } while (0) - -// These can be nested -#define portCRITICAL_NESTING_IN_TCB 1 // For now, let FreeRTOS' (tasks.c) manage critical nesting -void vTaskEnterCritical(void); -void vTaskExitCritical(void); -#define portENTER_CRITICAL() vTaskEnterCritical() -#define portEXIT_CRITICAL() vTaskExitCritical() - -// Cleaner and preferred solution allows nested interrupts disabling and restoring via local registers or stack. -// They can be called from interrupts too. -static inline unsigned portENTER_CRITICAL_NESTED() { unsigned state = XTOS_SET_INTLEVEL(XCHAL_EXCM_LEVEL); portbenchmarkINTERRUPT_DISABLE(); return state; } -#define portEXIT_CRITICAL_NESTED(state) do { portbenchmarkINTERRUPT_RESTORE(state); XTOS_RESTORE_JUST_INTLEVEL(state); } while (0) - -// These FreeRTOS versions are similar to the nested versions above -#define portSET_INTERRUPT_MASK_FROM_ISR() portENTER_CRITICAL_NESTED() -#define portCLEAR_INTERRUPT_MASK_FROM_ISR(state) portEXIT_CRITICAL_NESTED(state) +/* These cannot be nested. They should be used with a lot of care and cannot be called from interrupt level. */ + #define portDISABLE_INTERRUPTS() do { XTOS_SET_INTLEVEL( XCHAL_EXCM_LEVEL ); portbenchmarkINTERRUPT_DISABLE(); } while( 0 ) + #define portENABLE_INTERRUPTS() do { portbenchmarkINTERRUPT_RESTORE( 0 ); XTOS_SET_INTLEVEL( 0 ); } while( 0 ) + +/* These can be nested */ + #define portCRITICAL_NESTING_IN_TCB 1 /* For now, let FreeRTOS' (tasks.c) manage critical nesting */ + void vTaskEnterCritical( void ); + void vTaskExitCritical( void ); + #define portENTER_CRITICAL() vTaskEnterCritical() + #define portEXIT_CRITICAL() vTaskExitCritical() + +/* Cleaner and preferred solution allows nested interrupts disabling and restoring via local registers or stack. */ +/* They can be called from interrupts too. */ + static inline unsigned portENTER_CRITICAL_NESTED() + { + unsigned state = XTOS_SET_INTLEVEL( XCHAL_EXCM_LEVEL ); + + portbenchmarkINTERRUPT_DISABLE(); + return state; + } + #define portEXIT_CRITICAL_NESTED( state ) do { portbenchmarkINTERRUPT_RESTORE( state ); XTOS_RESTORE_JUST_INTLEVEL( state ); } while( 0 ) + +/* These FreeRTOS versions are similar to the nested versions above */ + #define portSET_INTERRUPT_MASK_FROM_ISR() portENTER_CRITICAL_NESTED() + #define portCLEAR_INTERRUPT_MASK_FROM_ISR( state ) portEXIT_CRITICAL_NESTED( state ) /*-----------------------------------------------------------*/ /* Architecture specifics. */ -#define portSTACK_GROWTH ( -1 ) -#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) -#define portBYTE_ALIGNMENT 4 -#define portNOP() XT_NOP() + #define portSTACK_GROWTH ( -1 ) + #define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) + #define portBYTE_ALIGNMENT 4 + #define portNOP() XT_NOP() /*-----------------------------------------------------------*/ /* Fine resolution time */ -#define portGET_RUN_TIME_COUNTER_VALUE() xthal_get_ccount() + #define portGET_RUN_TIME_COUNTER_VALUE() xthal_get_ccount() /* Kernel utilities. */ -void vPortYield( void ); -void _frxt_setup_switch( void ); -#define portYIELD() vPortYield() -#define portYIELD_FROM_ISR( xHigherPriorityTaskWoken ) \ - if ( ( xHigherPriorityTaskWoken ) != 0 ) { \ - _frxt_setup_switch(); \ + void vPortYield( void ); + void _frxt_setup_switch( void ); + #define portYIELD() vPortYield() + #define portYIELD_FROM_ISR( xHigherPriorityTaskWoken ) \ + if( ( xHigherPriorityTaskWoken ) != 0 ) { \ + _frxt_setup_switch(); \ } /*-----------------------------------------------------------*/ /* Task function macros as described on the FreeRTOS.org WEB site. */ -#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters ) -#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters ) - -// When coprocessors are defined, we to maintain a pointer to coprocessors area. -// We currently use a hack: redefine field xMPU_SETTINGS in TCB block as a structure that can hold: -// MPU wrappers, coprocessor area pointer, trace code structure, and more if needed. -// The field is normally used for memory protection. FreeRTOS should create another general purpose field. -typedef struct { - #if XCHAL_CP_NUM > 0 - volatile StackType_t* coproc_area; // Pointer to coprocessor save area; MUST BE FIRST - #endif - - #if portUSING_MPU_WRAPPERS - // Define here mpu_settings, which is port dependent - int mpu_setting; // Just a dummy example here; MPU not ported to Xtensa yet + #define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters ) + #define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters ) + +/* When coprocessors are defined, we to maintain a pointer to coprocessors area. */ +/* We currently use a hack: redefine field xMPU_SETTINGS in TCB block as a structure that can hold: */ +/* MPU wrappers, coprocessor area pointer, trace code structure, and more if needed. */ +/* The field is normally used for memory protection. FreeRTOS should create another general purpose field. */ + typedef struct + { + #if XCHAL_CP_NUM > 0 + volatile StackType_t * coproc_area; /* Pointer to coprocessor save area; MUST BE FIRST */ + #endif + + #if portUSING_MPU_WRAPPERS + /* Define here mpu_settings, which is port dependent */ + int mpu_setting; /* Just a dummy example here; MPU not ported to Xtensa yet */ + #endif + + #if configUSE_TRACE_FACILITY_2 + struct + { + /* Cf. porttraceStamp() */ + int taskstamp; /* Stamp from inside task to see where we are */ + int taskstampcount; /* A counter usually incremented when we restart the task's loop */ + } porttrace; + #endif + } xMPU_SETTINGS; + +/* Main hack to use MPU_wrappers even when no MPU is defined (warning: mpu_setting should not be accessed; otherwise move this above xMPU_SETTINGS) */ + #if ( XCHAL_CP_NUM > 0 || configUSE_TRACE_FACILITY_2 ) && !portUSING_MPU_WRAPPERS /* If MPU wrappers not used, we still need to allocate coproc area */ + #undef portUSING_MPU_WRAPPERS + #define portUSING_MPU_WRAPPERS 1 /* Enable it to allocate coproc area */ + #define MPU_WRAPPERS_H /* Override mpu_wrapper.h to disable unwanted code */ + #define PRIVILEGED_FUNCTION + #define PRIVILEGED_DATA #endif +/* porttrace */ #if configUSE_TRACE_FACILITY_2 - struct { - // Cf. porttraceStamp() - int taskstamp; /* Stamp from inside task to see where we are */ - int taskstampcount; /* A counter usually incremented when we restart the task's loop */ - } porttrace; + #include "porttrace.h" #endif -} xMPU_SETTINGS; - -// Main hack to use MPU_wrappers even when no MPU is defined (warning: mpu_setting should not be accessed; otherwise move this above xMPU_SETTINGS) -#if (XCHAL_CP_NUM > 0 || configUSE_TRACE_FACILITY_2) && !portUSING_MPU_WRAPPERS // If MPU wrappers not used, we still need to allocate coproc area - #undef portUSING_MPU_WRAPPERS - #define portUSING_MPU_WRAPPERS 1 // Enable it to allocate coproc area - #define MPU_WRAPPERS_H // Override mpu_wrapper.h to disable unwanted code - #define PRIVILEGED_FUNCTION - #define PRIVILEGED_DATA -#endif - -// porttrace -#if configUSE_TRACE_FACILITY_2 -#include "porttrace.h" -#endif -// configASSERT_2 if requested -#if configASSERT_2 -#include -void exit(int); -#define configASSERT( x ) if (!(x)) { porttracePrint(-1); printf("\nAssertion failed in %s:%d\n", __FILE__, __LINE__); exit(-1); } -#endif +/* configASSERT_2 if requested */ + #if configASSERT_2 + #include + void exit( int ); + #define configASSERT( x ) if( !( x ) ) { porttracePrint( -1 ); printf( "\nAssertion failed in %s:%d\n", __FILE__, __LINE__ ); exit( -1 ); } + #endif /* C library support -- only XCLIB and NEWLIB are supported. */ /* To enable thread-safe C library support, XT_USE_THREAD_SAFE_CLIB must be - defined to be > 0 somewhere above or on the command line. */ - -#if (XT_USE_THREAD_SAFE_CLIB > 0u) && (XSHAL_CLIB == XTHAL_CLIB_XCLIB) -extern void vPortClibInit(void); -#endif // XCLIB support - -#if (XT_USE_THREAD_SAFE_CLIB > 0u) && (XSHAL_CLIB == XTHAL_CLIB_NEWLIB) -extern void vPortClibInit(void); - -// This C library cleanup is not currently done by FreeRTOS when deleting a task -#include -#define portCLEAN_UP_TCB(pxTCB) vPortCleanUpTcbClib(&((pxTCB)->xNewLib_reent)) -static inline void vPortCleanUpTcbClib(struct _reent *ptr) -{ - FILE * fp = &(ptr->__sf[0]); - int i; - for (i = 0; i < 3; ++i, ++fp) { - fp->_close = NULL; - } -} -#endif // NEWLIB support + * defined to be > 0 somewhere above or on the command line. */ + + #if ( XT_USE_THREAD_SAFE_CLIB > 0u ) && ( XSHAL_CLIB == XTHAL_CLIB_XCLIB ) + extern void vPortClibInit( void ); + #endif // XCLIB support + + #if ( XT_USE_THREAD_SAFE_CLIB > 0u ) && ( XSHAL_CLIB == XTHAL_CLIB_NEWLIB ) + extern void vPortClibInit( void ); + +/* This C library cleanup is not currently done by FreeRTOS when deleting a task */ + #include + #define portCLEAN_UP_TCB( pxTCB ) vPortCleanUpTcbClib( &( ( pxTCB )->xNewLib_reent ) ) + static inline void vPortCleanUpTcbClib( struct _reent * ptr ) + { + FILE * fp = &( ptr->__sf[ 0 ] ); + int i; + + for( i = 0; i < 3; ++i, ++fp ) + { + fp->_close = NULL; + } + } + #endif // NEWLIB support #endif // __ASSEMBLER__ diff --git a/Source/portable/ThirdParty/XCC/Xtensa/porttrace.h b/Source/portable/ThirdParty/XCC/Xtensa/porttrace.h index 0be91af6e..b58222a9b 100644 --- a/Source/portable/ThirdParty/XCC/Xtensa/porttrace.h +++ b/Source/portable/ThirdParty/XCC/Xtensa/porttrace.h @@ -1,5 +1,5 @@ - /* - * FreeRTOS Kernel V10.6.2 +/* + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2015-2019 Cadence Design Systems, Inc. * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * @@ -43,7 +43,7 @@ #error "You need to download the FreeRTOS_trace patch that overwrites this file" #endif -#define porttracePrint(nelements) -#define porttraceStamp(stamp, count_incr) +#define porttracePrint( nelements ) +#define porttraceStamp( stamp, count_incr ) #endif /* PORTTRACE_H */ diff --git a/Source/portable/ThirdParty/XCC/Xtensa/xtensa_api.h b/Source/portable/ThirdParty/XCC/Xtensa/xtensa_api.h index 16c51f807..5f862be68 100644 --- a/Source/portable/ThirdParty/XCC/Xtensa/xtensa_api.h +++ b/Source/portable/ThirdParty/XCC/Xtensa/xtensa_api.h @@ -1,5 +1,5 @@ - /* - * FreeRTOS Kernel V10.6.2 +/* + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2015-2019 Cadence Design Systems, Inc. * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * @@ -40,87 +40,90 @@ /* Typedef for C-callable interrupt handler function */ -typedef void (*xt_handler)(void *); +typedef void (* xt_handler)( void * ); /* Typedef for C-callable exception handler function */ -typedef void (*xt_exc_handler)(XtExcFrame *); +typedef void (* xt_exc_handler)( XtExcFrame * ); /* -------------------------------------------------------------------------------- - Call this function to set a handler for the specified exception. - - n - Exception number (type) - f - Handler function address, NULL to uninstall handler. - - The handler will be passed a pointer to the exception frame, which is created - on the stack of the thread that caused the exception. - - If the handler returns, the thread context will be restored and the faulting - instruction will be retried. Any values in the exception frame that are - modified by the handler will be restored as part of the context. For details - of the exception frame structure see xtensa_context.h. -------------------------------------------------------------------------------- -*/ -extern xt_exc_handler xt_set_exception_handler(int n, xt_exc_handler f); + * ------------------------------------------------------------------------------- + * Call this function to set a handler for the specified exception. + * + * n - Exception number (type) + * f - Handler function address, NULL to uninstall handler. + * + * The handler will be passed a pointer to the exception frame, which is created + * on the stack of the thread that caused the exception. + * + * If the handler returns, the thread context will be restored and the faulting + * instruction will be retried. Any values in the exception frame that are + * modified by the handler will be restored as part of the context. For details + * of the exception frame structure see xtensa_context.h. + * ------------------------------------------------------------------------------- + */ +extern xt_exc_handler xt_set_exception_handler( int n, + xt_exc_handler f ); /* -------------------------------------------------------------------------------- - Call this function to set a handler for the specified interrupt. - - n - Interrupt number. - f - Handler function address, NULL to uninstall handler. - arg - Argument to be passed to handler. -------------------------------------------------------------------------------- -*/ -extern xt_handler xt_set_interrupt_handler(int n, xt_handler f, void * arg); + * ------------------------------------------------------------------------------- + * Call this function to set a handler for the specified interrupt. + * + * n - Interrupt number. + * f - Handler function address, NULL to uninstall handler. + * arg - Argument to be passed to handler. + * ------------------------------------------------------------------------------- + */ +extern xt_handler xt_set_interrupt_handler( int n, + xt_handler f, + void * arg ); /* -------------------------------------------------------------------------------- - Call this function to enable the specified interrupts. - - mask - Bit mask of interrupts to be enabled. - - Returns the previous state of the interrupt enables. -------------------------------------------------------------------------------- -*/ -extern unsigned int xt_ints_on(unsigned int mask); + * ------------------------------------------------------------------------------- + * Call this function to enable the specified interrupts. + * + * mask - Bit mask of interrupts to be enabled. + * + * Returns the previous state of the interrupt enables. + * ------------------------------------------------------------------------------- + */ +extern unsigned int xt_ints_on( unsigned int mask ); /* -------------------------------------------------------------------------------- - Call this function to disable the specified interrupts. - - mask - Bit mask of interrupts to be disabled. - - Returns the previous state of the interrupt enables. -------------------------------------------------------------------------------- -*/ -extern unsigned int xt_ints_off(unsigned int mask); + * ------------------------------------------------------------------------------- + * Call this function to disable the specified interrupts. + * + * mask - Bit mask of interrupts to be disabled. + * + * Returns the previous state of the interrupt enables. + * ------------------------------------------------------------------------------- + */ +extern unsigned int xt_ints_off( unsigned int mask ); /* -------------------------------------------------------------------------------- - Call this function to set the specified (s/w) interrupt. -------------------------------------------------------------------------------- -*/ -static inline void xt_set_intset(unsigned int arg) + * ------------------------------------------------------------------------------- + * Call this function to set the specified (s/w) interrupt. + * ------------------------------------------------------------------------------- + */ +static inline void xt_set_intset( unsigned int arg ) { - xthal_set_intset(arg); + xthal_set_intset( arg ); } /* -------------------------------------------------------------------------------- - Call this function to clear the specified (s/w or edge-triggered) - interrupt. -------------------------------------------------------------------------------- -*/ -static inline void xt_set_intclear(unsigned int arg) + * ------------------------------------------------------------------------------- + * Call this function to clear the specified (s/w or edge-triggered) + * interrupt. + * ------------------------------------------------------------------------------- + */ +static inline void xt_set_intclear( unsigned int arg ) { - xthal_set_intclear(arg); + xthal_set_intclear( arg ); } diff --git a/Source/portable/ThirdParty/XCC/Xtensa/xtensa_config.h b/Source/portable/ThirdParty/XCC/Xtensa/xtensa_config.h index 041378f5c..6586e7b9a 100644 --- a/Source/portable/ThirdParty/XCC/Xtensa/xtensa_config.h +++ b/Source/portable/ThirdParty/XCC/Xtensa/xtensa_config.h @@ -1,5 +1,5 @@ - /* - * FreeRTOS Kernel V10.6.2 +/* + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2015-2019 Cadence Design Systems, Inc. * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * @@ -47,139 +47,139 @@ #include #include -#include /* required for XSHAL_CLIB */ +#include /* required for XSHAL_CLIB */ #include "xtensa_context.h" /*----------------------------------------------------------------------------- -* STACK REQUIREMENTS -* -* This section defines the minimum stack size, and the extra space required to -* be allocated for saving coprocessor state and/or C library state information -* (if thread safety is enabled for the C library). The sizes are in bytes. -* -* Stack sizes for individual tasks should be derived from these minima based on -* the maximum call depth of the task and the maximum level of interrupt nesting. -* A minimum stack size is defined by XT_STACK_MIN_SIZE. This minimum is based -* on the requirement for a task that calls nothing else but can be interrupted. -* This assumes that interrupt handlers do not call more than a few levels deep. -* If this is not true, i.e. one or more interrupt handlers make deep calls then -* the minimum must be increased. -* -* If the Xtensa processor configuration includes coprocessors, then space is -* allocated to save the coprocessor state on the stack. -* -* If thread safety is enabled for the C runtime library, (XT_USE_THREAD_SAFE_CLIB -* is defined) then space is allocated to save the C library context in the TCB. -* -* Allocating insufficient stack space is a common source of hard-to-find errors. -* During development, it is best to enable the FreeRTOS stack checking features. -* -* Usage: -* -* XT_USE_THREAD_SAFE_CLIB -- Define this to a nonzero value to enable thread-safe -* use of the C library. This will require extra stack -* space to be allocated for tasks that use the C library -* reentrant functions. See below for more information. -* -* NOTE: The Xtensa toolchain supports multiple C libraries and not all of them -* support thread safety. Check your core configuration to see which C library -* was chosen for your system. -* -* XT_STACK_MIN_SIZE -- The minimum stack size for any task. It is recommended -* that you do not use a stack smaller than this for any -* task. In case you want to use stacks smaller than this -* size, you must verify that the smaller size(s) will work -* under all operating conditions. -* -* XT_STACK_EXTRA -- The amount of extra stack space to allocate for a task -* that does not make C library reentrant calls. Add this -* to the amount of stack space required by the task itself. -* -* XT_STACK_EXTRA_CLIB -- The amount of space to allocate for C library state. -* ------------------------------------------------------------------------------*/ + * STACK REQUIREMENTS + * + * This section defines the minimum stack size, and the extra space required to + * be allocated for saving coprocessor state and/or C library state information + * (if thread safety is enabled for the C library). The sizes are in bytes. + * + * Stack sizes for individual tasks should be derived from these minima based on + * the maximum call depth of the task and the maximum level of interrupt nesting. + * A minimum stack size is defined by XT_STACK_MIN_SIZE. This minimum is based + * on the requirement for a task that calls nothing else but can be interrupted. + * This assumes that interrupt handlers do not call more than a few levels deep. + * If this is not true, i.e. one or more interrupt handlers make deep calls then + * the minimum must be increased. + * + * If the Xtensa processor configuration includes coprocessors, then space is + * allocated to save the coprocessor state on the stack. + * + * If thread safety is enabled for the C runtime library, (XT_USE_THREAD_SAFE_CLIB + * is defined) then space is allocated to save the C library context in the TCB. + * + * Allocating insufficient stack space is a common source of hard-to-find errors. + * During development, it is best to enable the FreeRTOS stack checking features. + * + * Usage: + * + * XT_USE_THREAD_SAFE_CLIB -- Define this to a nonzero value to enable thread-safe + * use of the C library. This will require extra stack + * space to be allocated for tasks that use the C library + * reentrant functions. See below for more information. + * + * NOTE: The Xtensa toolchain supports multiple C libraries and not all of them + * support thread safety. Check your core configuration to see which C library + * was chosen for your system. + * + * XT_STACK_MIN_SIZE -- The minimum stack size for any task. It is recommended + * that you do not use a stack smaller than this for any + * task. In case you want to use stacks smaller than this + * size, you must verify that the smaller size(s) will work + * under all operating conditions. + * + * XT_STACK_EXTRA -- The amount of extra stack space to allocate for a task + * that does not make C library reentrant calls. Add this + * to the amount of stack space required by the task itself. + * + * XT_STACK_EXTRA_CLIB -- The amount of space to allocate for C library state. + * + * -----------------------------------------------------------------------------*/ /* Extra space required for interrupt/exception hooks. */ #ifdef XT_INTEXC_HOOKS - #ifdef __XTENSA_CALL0_ABI__ - #define STK_INTEXC_EXTRA 0x200 - #else - #define STK_INTEXC_EXTRA 0x180 - #endif + #ifdef __XTENSA_CALL0_ABI__ + #define STK_INTEXC_EXTRA 0x200 + #else + #define STK_INTEXC_EXTRA 0x180 + #endif #else - #define STK_INTEXC_EXTRA 0 + #define STK_INTEXC_EXTRA 0 #endif /* Check C library thread safety support and compute size of C library save area. - For the supported libraries, we enable thread safety by default, and this can - be overridden from the compiler/make command line. */ -#if (XSHAL_CLIB == XTHAL_CLIB_NEWLIB) || (XSHAL_CLIB == XTHAL_CLIB_XCLIB) - #ifndef XT_USE_THREAD_SAFE_CLIB - #define XT_USE_THREAD_SAFE_CLIB 1 - #endif + * For the supported libraries, we enable thread safety by default, and this can + * be overridden from the compiler/make command line. */ +#if ( XSHAL_CLIB == XTHAL_CLIB_NEWLIB ) || ( XSHAL_CLIB == XTHAL_CLIB_XCLIB ) + #ifndef XT_USE_THREAD_SAFE_CLIB + #define XT_USE_THREAD_SAFE_CLIB 1 + #endif #else - #define XT_USE_THREAD_SAFE_CLIB 0 + #define XT_USE_THREAD_SAFE_CLIB 0 #endif #if XT_USE_THREAD_SAFE_CLIB > 0u - #if XSHAL_CLIB == XTHAL_CLIB_XCLIB - #define XT_HAVE_THREAD_SAFE_CLIB 1 - #if !defined __ASSEMBLER__ - #include - #define XT_CLIB_CONTEXT_AREA_SIZE ((sizeof(struct _reent) + 15) + (-16)) - #define XT_CLIB_GLOBAL_PTR _reent_ptr - #define _REENT_INIT_PTR _init_reent - #define _impure_ptr _reent_ptr - - void _reclaim_reent(void * ptr); - #endif - #elif XSHAL_CLIB == XTHAL_CLIB_NEWLIB - #define XT_HAVE_THREAD_SAFE_CLIB 1 - #if !defined __ASSEMBLER__ - #include - #define XT_CLIB_CONTEXT_AREA_SIZE ((sizeof(struct _reent) + 15) + (-16)) - #define XT_CLIB_GLOBAL_PTR _impure_ptr - #endif - #else - #define XT_HAVE_THREAD_SAFE_CLIB 0 - #error The selected C runtime library is not thread safe. - #endif -#else - #define XT_CLIB_CONTEXT_AREA_SIZE 0 -#endif + #if XSHAL_CLIB == XTHAL_CLIB_XCLIB + #define XT_HAVE_THREAD_SAFE_CLIB 1 + #if !defined __ASSEMBLER__ + #include + #define XT_CLIB_CONTEXT_AREA_SIZE ( ( sizeof( struct _reent ) + 15 ) + ( -16 ) ) + #define XT_CLIB_GLOBAL_PTR _reent_ptr + #define _REENT_INIT_PTR _init_reent + #define _impure_ptr _reent_ptr + + void _reclaim_reent( void * ptr ); + #endif + #elif XSHAL_CLIB == XTHAL_CLIB_NEWLIB + #define XT_HAVE_THREAD_SAFE_CLIB 1 + #if !defined __ASSEMBLER__ + #include + #define XT_CLIB_CONTEXT_AREA_SIZE ( ( sizeof( struct _reent ) + 15 ) + ( -16 ) ) + #define XT_CLIB_GLOBAL_PTR _impure_ptr + #endif + #else /* if XSHAL_CLIB == XTHAL_CLIB_XCLIB */ + #define XT_HAVE_THREAD_SAFE_CLIB 0 + #error The selected C runtime library is not thread safe. + #endif /* if XSHAL_CLIB == XTHAL_CLIB_XCLIB */ +#else /* if XT_USE_THREAD_SAFE_CLIB > 0u */ + #define XT_CLIB_CONTEXT_AREA_SIZE 0 +#endif /* if XT_USE_THREAD_SAFE_CLIB > 0u */ /*------------------------------------------------------------------------------ - Extra size -- interrupt frame plus coprocessor save area plus hook space. - NOTE: Make sure XT_INTEXC_HOOKS is undefined unless you really need the hooks. -------------------------------------------------------------------------------*/ + * Extra size -- interrupt frame plus coprocessor save area plus hook space. + * NOTE: Make sure XT_INTEXC_HOOKS is undefined unless you really need the hooks. + * ------------------------------------------------------------------------------*/ #ifdef __XTENSA_CALL0_ABI__ - #define XT_XTRA_SIZE (XT_STK_FRMSZ + STK_INTEXC_EXTRA + 0x10 + XT_CP_SIZE) + #define XT_XTRA_SIZE ( XT_STK_FRMSZ + STK_INTEXC_EXTRA + 0x10 + XT_CP_SIZE ) #else - #define XT_XTRA_SIZE (XT_STK_FRMSZ + STK_INTEXC_EXTRA + 0x20 + XT_CP_SIZE) + #define XT_XTRA_SIZE ( XT_STK_FRMSZ + STK_INTEXC_EXTRA + 0x20 + XT_CP_SIZE ) #endif /*------------------------------------------------------------------------------ - Space allocated for user code -- function calls and local variables. - NOTE: This number can be adjusted to suit your needs. You must verify that the - amount of space you reserve is adequate for the worst-case conditions in your - application. - NOTE: The windowed ABI requires more stack, since space has to be reserved - for spilling register windows. -------------------------------------------------------------------------------*/ + * Space allocated for user code -- function calls and local variables. + * NOTE: This number can be adjusted to suit your needs. You must verify that the + * amount of space you reserve is adequate for the worst-case conditions in your + * application. + * NOTE: The windowed ABI requires more stack, since space has to be reserved + * for spilling register windows. + * ------------------------------------------------------------------------------*/ #ifdef __XTENSA_CALL0_ABI__ - #define XT_USER_SIZE 0x200 + #define XT_USER_SIZE 0x200 #else - #define XT_USER_SIZE 0x400 + #define XT_USER_SIZE 0x400 #endif /* Minimum recommended stack size. */ -#define XT_STACK_MIN_SIZE ((XT_XTRA_SIZE + XT_USER_SIZE) / sizeof(unsigned char)) +#define XT_STACK_MIN_SIZE ( ( XT_XTRA_SIZE + XT_USER_SIZE ) / sizeof( unsigned char ) ) /* OS overhead with and without C library thread context. */ -#define XT_STACK_EXTRA (XT_XTRA_SIZE) -#define XT_STACK_EXTRA_CLIB (XT_XTRA_SIZE + XT_CLIB_CONTEXT_AREA_SIZE) +#define XT_STACK_EXTRA ( XT_XTRA_SIZE ) +#define XT_STACK_EXTRA_CLIB ( XT_XTRA_SIZE + XT_CLIB_CONTEXT_AREA_SIZE ) /* *INDENT-OFF* */ diff --git a/Source/portable/ThirdParty/XCC/Xtensa/xtensa_context.S b/Source/portable/ThirdParty/XCC/Xtensa/xtensa_context.S index cd23aba87..6662841bc 100644 --- a/Source/portable/ThirdParty/XCC/Xtensa/xtensa_context.S +++ b/Source/portable/ThirdParty/XCC/Xtensa/xtensa_context.S @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2015-2019 Cadence Design Systems, Inc. * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * diff --git a/Source/portable/ThirdParty/XCC/Xtensa/xtensa_context.h b/Source/portable/ThirdParty/XCC/Xtensa/xtensa_context.h index 028efcfe5..861c588cf 100644 --- a/Source/portable/ThirdParty/XCC/Xtensa/xtensa_context.h +++ b/Source/portable/ThirdParty/XCC/Xtensa/xtensa_context.h @@ -1,5 +1,5 @@ - /* - * FreeRTOS Kernel V10.6.2 +/* + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2015-2019 Cadence Design Systems, Inc. * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * @@ -44,7 +44,7 @@ #define XTENSA_CONTEXT_H #ifdef __ASSEMBLER__ -#include + #include #endif #include @@ -53,303 +53,307 @@ /* Align a value up to nearest n-byte boundary, where n is a power of 2. */ -#define ALIGNUP(n, val) (((val) + (n)-1) & -(n)) +#define ALIGNUP( n, val ) ( ( ( val ) + ( n ) - 1 ) & -( n ) ) /* -------------------------------------------------------------------------------- - Macros that help define structures for both C and assembler. -------------------------------------------------------------------------------- -*/ -#if defined(_ASMLANGUAGE) || defined(__ASSEMBLER__) + * ------------------------------------------------------------------------------- + * Macros that help define structures for both C and assembler. + * ------------------------------------------------------------------------------- + */ +#if defined( _ASMLANGUAGE ) || defined( __ASSEMBLER__ ) -#define STRUCT_BEGIN .pushsection .text; .struct 0 -#define STRUCT_FIELD(ctype,size,asname,name) asname: .space size -#define STRUCT_AFIELD(ctype,size,asname,name,n) asname: .space (size)*(n) -#define STRUCT_END(sname) sname##Size:; .popsection + #define STRUCT_BEGIN .pushsection.text; .struct 0 + #define STRUCT_FIELD( ctype, size, asname, name ) asname :.space size + #define STRUCT_AFIELD( ctype, size, asname, name, n ) asname :.space( size ) *( n ) + #define STRUCT_END( sname ) sname ## Size:; .popsection #else -#define STRUCT_BEGIN typedef struct { -#define STRUCT_FIELD(ctype,size,asname,name) ctype name; -#define STRUCT_AFIELD(ctype,size,asname,name,n) ctype name[n]; -#define STRUCT_END(sname) } sname; + #define STRUCT_BEGIN typedef struct { + #define STRUCT_FIELD( ctype, size, asname, name ) ctype name; + #define STRUCT_AFIELD( ctype, size, asname, name, n ) ctype name[ n ]; + #define STRUCT_END( sname ) \ +} \ + sname; #endif //_ASMLANGUAGE || __ASSEMBLER__ /* -------------------------------------------------------------------------------- - INTERRUPT/EXCEPTION STACK FRAME FOR A THREAD OR NESTED INTERRUPT - - A stack frame of this structure is allocated for any interrupt or exception. - It goes on the current stack. If the RTOS has a system stack for handling - interrupts, every thread stack must allow space for just one interrupt stack - frame, then nested interrupt stack frames go on the system stack. - - The frame includes basic registers (explicit) and "extra" registers introduced - by user TIE or the use of the MAC16 option in the user's Xtensa config. - The frame size is minimized by omitting regs not applicable to user's config. - - For Windowed ABI, this stack frame includes the interruptee's base save area, - another base save area to manage gcc nested functions, and a little temporary - space to help manage the spilling of the register windows. -------------------------------------------------------------------------------- -*/ + * ------------------------------------------------------------------------------- + * INTERRUPT/EXCEPTION STACK FRAME FOR A THREAD OR NESTED INTERRUPT + * + * A stack frame of this structure is allocated for any interrupt or exception. + * It goes on the current stack. If the RTOS has a system stack for handling + * interrupts, every thread stack must allow space for just one interrupt stack + * frame, then nested interrupt stack frames go on the system stack. + * + * The frame includes basic registers (explicit) and "extra" registers introduced + * by user TIE or the use of the MAC16 option in the user's Xtensa config. + * The frame size is minimized by omitting regs not applicable to user's config. + * + * For Windowed ABI, this stack frame includes the interruptee's base save area, + * another base save area to manage gcc nested functions, and a little temporary + * space to help manage the spilling of the register windows. + * ------------------------------------------------------------------------------- + */ -STRUCT_BEGIN -STRUCT_FIELD (long, 4, XT_STK_EXIT, exit) /* exit point for dispatch */ -STRUCT_FIELD (long, 4, XT_STK_PC, pc) /* return PC */ -STRUCT_FIELD (long, 4, XT_STK_PS, ps) /* return PS */ -STRUCT_FIELD (long, 4, XT_STK_A0, a0) -STRUCT_FIELD (long, 4, XT_STK_A1, a1) /* stack pointer before interrupt */ -STRUCT_FIELD (long, 4, XT_STK_A2, a2) -STRUCT_FIELD (long, 4, XT_STK_A3, a3) -STRUCT_FIELD (long, 4, XT_STK_A4, a4) -STRUCT_FIELD (long, 4, XT_STK_A5, a5) -STRUCT_FIELD (long, 4, XT_STK_A6, a6) -STRUCT_FIELD (long, 4, XT_STK_A7, a7) -STRUCT_FIELD (long, 4, XT_STK_A8, a8) -STRUCT_FIELD (long, 4, XT_STK_A9, a9) -STRUCT_FIELD (long, 4, XT_STK_A10, a10) -STRUCT_FIELD (long, 4, XT_STK_A11, a11) -STRUCT_FIELD (long, 4, XT_STK_A12, a12) -STRUCT_FIELD (long, 4, XT_STK_A13, a13) -STRUCT_FIELD (long, 4, XT_STK_A14, a14) -STRUCT_FIELD (long, 4, XT_STK_A15, a15) -STRUCT_FIELD (long, 4, XT_STK_SAR, sar) -STRUCT_FIELD (long, 4, XT_STK_EXCCAUSE, exccause) -STRUCT_FIELD (long, 4, XT_STK_EXCVADDR, excvaddr) +STRUCT_BEGIN STRUCT_FIELD( long, + 4, + XT_STK_EXIT, + exit ) /* exit point for dispatch */ +STRUCT_FIELD( long, 4, XT_STK_PC, pc ) /* return PC */ +STRUCT_FIELD( long, 4, XT_STK_PS, ps ) /* return PS */ +STRUCT_FIELD( long, 4, XT_STK_A0, a0 ) +STRUCT_FIELD( long, 4, XT_STK_A1, a1 ) /* stack pointer before interrupt */ +STRUCT_FIELD( long, 4, XT_STK_A2, a2 ) +STRUCT_FIELD( long, 4, XT_STK_A3, a3 ) +STRUCT_FIELD( long, 4, XT_STK_A4, a4 ) +STRUCT_FIELD( long, 4, XT_STK_A5, a5 ) +STRUCT_FIELD( long, 4, XT_STK_A6, a6 ) +STRUCT_FIELD( long, 4, XT_STK_A7, a7 ) +STRUCT_FIELD( long, 4, XT_STK_A8, a8 ) +STRUCT_FIELD( long, 4, XT_STK_A9, a9 ) +STRUCT_FIELD( long, 4, XT_STK_A10, a10 ) +STRUCT_FIELD( long, 4, XT_STK_A11, a11 ) +STRUCT_FIELD( long, 4, XT_STK_A12, a12 ) +STRUCT_FIELD( long, 4, XT_STK_A13, a13 ) +STRUCT_FIELD( long, 4, XT_STK_A14, a14 ) +STRUCT_FIELD( long, 4, XT_STK_A15, a15 ) +STRUCT_FIELD( long, 4, XT_STK_SAR, sar ) +STRUCT_FIELD( long, 4, XT_STK_EXCCAUSE, exccause ) +STRUCT_FIELD( long, 4, XT_STK_EXCVADDR, excvaddr ) #if XCHAL_HAVE_LOOPS -STRUCT_FIELD (long, 4, XT_STK_LBEG, lbeg) -STRUCT_FIELD (long, 4, XT_STK_LEND, lend) -STRUCT_FIELD (long, 4, XT_STK_LCOUNT, lcount) + STRUCT_FIELD( long, 4, XT_STK_LBEG, lbeg ) + STRUCT_FIELD( long, 4, XT_STK_LEND, lend ) + STRUCT_FIELD( long, 4, XT_STK_LCOUNT, lcount ) #endif #ifndef __XTENSA_CALL0_ABI__ /* Temporary space for saving stuff during window spill */ -STRUCT_FIELD (long, 4, XT_STK_TMP0, tmp0) -STRUCT_FIELD (long, 4, XT_STK_TMP1, tmp1) -STRUCT_FIELD (long, 4, XT_STK_TMP2, tmp2) + STRUCT_FIELD( long, 4, XT_STK_TMP0, tmp0 ) + STRUCT_FIELD( long, 4, XT_STK_TMP1, tmp1 ) + STRUCT_FIELD( long, 4, XT_STK_TMP2, tmp2 ) #endif #ifdef XT_USE_SWPRI /* Storage for virtual priority mask */ -STRUCT_FIELD (long, 4, XT_STK_VPRI, vpri) + STRUCT_FIELD( long, 4, XT_STK_VPRI, vpri ) #endif #ifdef XT_USE_OVLY /* Storage for overlay state */ -STRUCT_FIELD (long, 4, XT_STK_OVLY, ovly) + STRUCT_FIELD( long, 4, XT_STK_OVLY, ovly ) #endif -STRUCT_END(XtExcFrame) +STRUCT_END( XtExcFrame ) -#if defined(_ASMLANGUAGE) || defined(__ASSEMBLER__) -#define XT_STK_NEXT1 XtExcFrameSize +#if defined( _ASMLANGUAGE ) || defined( __ASSEMBLER__ ) +#define XT_STK_NEXT1 XtExcFrameSize #else -#define XT_STK_NEXT1 sizeof(XtExcFrame) +#define XT_STK_NEXT1 sizeof( XtExcFrame ) #endif /* Allocate extra storage if needed */ #if XCHAL_EXTRA_SA_SIZE != 0 -#if XCHAL_EXTRA_SA_ALIGN <= 16 -#define XT_STK_EXTRA ALIGNUP(XCHAL_EXTRA_SA_ALIGN, XT_STK_NEXT1) -#else + #if XCHAL_EXTRA_SA_ALIGN <= 16 +#define XT_STK_EXTRA ALIGNUP( XCHAL_EXTRA_SA_ALIGN, XT_STK_NEXT1 ) + #else /* If need more alignment than stack, add space for dynamic alignment */ -#define XT_STK_EXTRA (ALIGNUP(XCHAL_EXTRA_SA_ALIGN, XT_STK_NEXT1) + XCHAL_EXTRA_SA_ALIGN) -#endif -#define XT_STK_NEXT2 (XT_STK_EXTRA + XCHAL_EXTRA_SA_SIZE) +#define XT_STK_EXTRA ( ALIGNUP( XCHAL_EXTRA_SA_ALIGN, XT_STK_NEXT1 ) + XCHAL_EXTRA_SA_ALIGN ) + #endif +#define XT_STK_NEXT2 ( XT_STK_EXTRA + XCHAL_EXTRA_SA_SIZE ) #else -#define XT_STK_NEXT2 XT_STK_NEXT1 +#define XT_STK_NEXT2 XT_STK_NEXT1 -#endif +#endif /* if XCHAL_EXTRA_SA_SIZE != 0 */ /* -------------------------------------------------------------------------------- - This is the frame size. Add space for 4 registers (interruptee's base save - area) and some space for gcc nested functions if any. -------------------------------------------------------------------------------- -*/ -#define XT_STK_FRMSZ (ALIGNUP(0x10, XT_STK_NEXT2) + 0x20) + * ------------------------------------------------------------------------------- + * This is the frame size. Add space for 4 registers (interruptee's base save + * area) and some space for gcc nested functions if any. + * ------------------------------------------------------------------------------- + */ +#define XT_STK_FRMSZ ( ALIGNUP( 0x10, XT_STK_NEXT2 ) + 0x20 ) /* -------------------------------------------------------------------------------- - SOLICITED STACK FRAME FOR A THREAD - - A stack frame of this structure is allocated whenever a thread enters the - RTOS kernel intentionally (and synchronously) to submit to thread scheduling. - It goes on the current thread's stack. - - The solicited frame only includes registers that are required to be preserved - by the callee according to the compiler's ABI conventions, some space to save - the return address for returning to the caller, and the caller's PS register. - - For Windowed ABI, this stack frame includes the caller's base save area. - - Note on XT_SOL_EXIT field: - It is necessary to distinguish a solicited from an interrupt stack frame. - This field corresponds to XT_STK_EXIT in the interrupt stack frame and is - always at the same offset (0). It can be written with a code (usually 0) - to distinguish a solicted frame from an interrupt frame. An RTOS port may - opt to ignore this field if it has another way of distinguishing frames. -------------------------------------------------------------------------------- -*/ + * ------------------------------------------------------------------------------- + * SOLICITED STACK FRAME FOR A THREAD + * + * A stack frame of this structure is allocated whenever a thread enters the + * RTOS kernel intentionally (and synchronously) to submit to thread scheduling. + * It goes on the current thread's stack. + * + * The solicited frame only includes registers that are required to be preserved + * by the callee according to the compiler's ABI conventions, some space to save + * the return address for returning to the caller, and the caller's PS register. + * + * For Windowed ABI, this stack frame includes the caller's base save area. + * + * Note on XT_SOL_EXIT field: + * It is necessary to distinguish a solicited from an interrupt stack frame. + * This field corresponds to XT_STK_EXIT in the interrupt stack frame and is + * always at the same offset (0). It can be written with a code (usually 0) + * to distinguish a solicted frame from an interrupt frame. An RTOS port may + * opt to ignore this field if it has another way of distinguishing frames. + * ------------------------------------------------------------------------------- + */ STRUCT_BEGIN #ifdef __XTENSA_CALL0_ABI__ -STRUCT_FIELD (long, 4, XT_SOL_EXIT, exit) -STRUCT_FIELD (long, 4, XT_SOL_PC, pc) -STRUCT_FIELD (long, 4, XT_SOL_PS, ps) -STRUCT_FIELD (long, 4, XT_SOL_NEXT, next) -STRUCT_FIELD (long, 4, XT_SOL_A12, a12) /* should be on 16-byte alignment */ -STRUCT_FIELD (long, 4, XT_SOL_A13, a13) -STRUCT_FIELD (long, 4, XT_SOL_A14, a14) -STRUCT_FIELD (long, 4, XT_SOL_A15, a15) + STRUCT_FIELD( long, 4, XT_SOL_EXIT, exit ) + STRUCT_FIELD( long, 4, XT_SOL_PC, pc ) + STRUCT_FIELD( long, 4, XT_SOL_PS, ps ) + STRUCT_FIELD( long, 4, XT_SOL_NEXT, next ) + STRUCT_FIELD( long, 4, XT_SOL_A12, a12 ) /* should be on 16-byte alignment */ + STRUCT_FIELD( long, 4, XT_SOL_A13, a13 ) + STRUCT_FIELD( long, 4, XT_SOL_A14, a14 ) + STRUCT_FIELD( long, 4, XT_SOL_A15, a15 ) #else -STRUCT_FIELD (long, 4, XT_SOL_EXIT, exit) -STRUCT_FIELD (long, 4, XT_SOL_PC, pc) -STRUCT_FIELD (long, 4, XT_SOL_PS, ps) -STRUCT_FIELD (long, 4, XT_SOL_NEXT, next) -STRUCT_FIELD (long, 4, XT_SOL_A0, a0) /* should be on 16-byte alignment */ -STRUCT_FIELD (long, 4, XT_SOL_A1, a1) -STRUCT_FIELD (long, 4, XT_SOL_A2, a2) -STRUCT_FIELD (long, 4, XT_SOL_A3, a3) -#endif -STRUCT_END(XtSolFrame) + STRUCT_FIELD( long, 4, XT_SOL_EXIT, exit ) + STRUCT_FIELD( long, 4, XT_SOL_PC, pc ) + STRUCT_FIELD( long, 4, XT_SOL_PS, ps ) + STRUCT_FIELD( long, 4, XT_SOL_NEXT, next ) + STRUCT_FIELD( long, 4, XT_SOL_A0, a0 ) /* should be on 16-byte alignment */ + STRUCT_FIELD( long, 4, XT_SOL_A1, a1 ) + STRUCT_FIELD( long, 4, XT_SOL_A2, a2 ) + STRUCT_FIELD( long, 4, XT_SOL_A3, a3 ) +#endif /* ifdef __XTENSA_CALL0_ABI__ */ +STRUCT_END( XtSolFrame ) /* Size of solicited stack frame */ -#define XT_SOL_FRMSZ ALIGNUP(0x10, XtSolFrameSize) +#define XT_SOL_FRMSZ ALIGNUP( 0x10, XtSolFrameSize ) /* -------------------------------------------------------------------------------- - CO-PROCESSOR STATE SAVE AREA FOR A THREAD - - The RTOS must provide an area per thread to save the state of co-processors - when that thread does not have control. Co-processors are context-switched - lazily (on demand) only when a new thread uses a co-processor instruction, - otherwise a thread retains ownership of the co-processor even when it loses - control of the processor. An Xtensa co-processor exception is triggered when - any co-processor instruction is executed by a thread that is not the owner, - and the context switch of that co-processor is then peformed by the handler. - Ownership represents which thread's state is currently in the co-processor. - - Co-processors may not be used by interrupt or exception handlers. If an - co-processor instruction is executed by an interrupt or exception handler, - the co-processor exception handler will trigger a kernel panic and freeze. - This restriction is introduced to reduce the overhead of saving and restoring - co-processor state (which can be quite large) and in particular remove that - overhead from interrupt handlers. - - The co-processor state save area may be in any convenient per-thread location - such as in the thread control block or above the thread stack area. It need - not be in the interrupt stack frame since interrupts don't use co-processors. - - Along with the save area for each co-processor, two bitmasks with flags per - co-processor (laid out as in the CPENABLE reg) help manage context-switching - co-processors as efficiently as possible: - - XT_CPENABLE - The contents of a non-running thread's CPENABLE register. - It represents the co-processors owned (and whose state is still needed) - by the thread. When a thread is preempted, its CPENABLE is saved here. - When a thread solicits a context-swtich, its CPENABLE is cleared - the - compiler has saved the (caller-saved) co-proc state if it needs to. - When a non-running thread loses ownership of a CP, its bit is cleared. - When a thread runs, it's XT_CPENABLE is loaded into the CPENABLE reg. - Avoids co-processor exceptions when no change of ownership is needed. - - XT_CPSTORED - A bitmask with the same layout as CPENABLE, a bit per co-processor. - Indicates whether the state of each co-processor is saved in the state - save area. When a thread enters the kernel, only the state of co-procs - still enabled in CPENABLE is saved. When the co-processor exception - handler assigns ownership of a co-processor to a thread, it restores - the saved state only if this bit is set, and clears this bit. - - XT_CP_CS_ST - A bitmask with the same layout as CPENABLE, a bit per co-processor. - Indicates whether callee-saved state is saved in the state save area. - Callee-saved state is saved by itself on a solicited context switch, - and restored when needed by the coprocessor exception handler. - Unsolicited switches will cause the entire coprocessor to be saved - when necessary. - - XT_CP_ASA - Pointer to the aligned save area. Allows it to be aligned more than - the overall save area (which might only be stack-aligned or TCB-aligned). - Especially relevant for Xtensa cores configured with a very large data - path that requires alignment greater than 16 bytes (ABI stack alignment). -------------------------------------------------------------------------------- -*/ + * ------------------------------------------------------------------------------- + * CO-PROCESSOR STATE SAVE AREA FOR A THREAD + * + * The RTOS must provide an area per thread to save the state of co-processors + * when that thread does not have control. Co-processors are context-switched + * lazily (on demand) only when a new thread uses a co-processor instruction, + * otherwise a thread retains ownership of the co-processor even when it loses + * control of the processor. An Xtensa co-processor exception is triggered when + * any co-processor instruction is executed by a thread that is not the owner, + * and the context switch of that co-processor is then peformed by the handler. + * Ownership represents which thread's state is currently in the co-processor. + * + * Co-processors may not be used by interrupt or exception handlers. If an + * co-processor instruction is executed by an interrupt or exception handler, + * the co-processor exception handler will trigger a kernel panic and freeze. + * This restriction is introduced to reduce the overhead of saving and restoring + * co-processor state (which can be quite large) and in particular remove that + * overhead from interrupt handlers. + * + * The co-processor state save area may be in any convenient per-thread location + * such as in the thread control block or above the thread stack area. It need + * not be in the interrupt stack frame since interrupts don't use co-processors. + * + * Along with the save area for each co-processor, two bitmasks with flags per + * co-processor (laid out as in the CPENABLE reg) help manage context-switching + * co-processors as efficiently as possible: + * + * XT_CPENABLE + * The contents of a non-running thread's CPENABLE register. + * It represents the co-processors owned (and whose state is still needed) + * by the thread. When a thread is preempted, its CPENABLE is saved here. + * When a thread solicits a context-swtich, its CPENABLE is cleared - the + * compiler has saved the (caller-saved) co-proc state if it needs to. + * When a non-running thread loses ownership of a CP, its bit is cleared. + * When a thread runs, it's XT_CPENABLE is loaded into the CPENABLE reg. + * Avoids co-processor exceptions when no change of ownership is needed. + * + * XT_CPSTORED + * A bitmask with the same layout as CPENABLE, a bit per co-processor. + * Indicates whether the state of each co-processor is saved in the state + * save area. When a thread enters the kernel, only the state of co-procs + * still enabled in CPENABLE is saved. When the co-processor exception + * handler assigns ownership of a co-processor to a thread, it restores + * the saved state only if this bit is set, and clears this bit. + * + * XT_CP_CS_ST + * A bitmask with the same layout as CPENABLE, a bit per co-processor. + * Indicates whether callee-saved state is saved in the state save area. + * Callee-saved state is saved by itself on a solicited context switch, + * and restored when needed by the coprocessor exception handler. + * Unsolicited switches will cause the entire coprocessor to be saved + * when necessary. + * + * XT_CP_ASA + * Pointer to the aligned save area. Allows it to be aligned more than + * the overall save area (which might only be stack-aligned or TCB-aligned). + * Especially relevant for Xtensa cores configured with a very large data + * path that requires alignment greater than 16 bytes (ABI stack alignment). + * ------------------------------------------------------------------------------- + */ #if XCHAL_CP_NUM > 0 /* Offsets of each coprocessor save area within the 'aligned save area': */ -#define XT_CP0_SA 0 -#define XT_CP1_SA ALIGNUP(XCHAL_CP1_SA_ALIGN, XT_CP0_SA + XCHAL_CP0_SA_SIZE) -#define XT_CP2_SA ALIGNUP(XCHAL_CP2_SA_ALIGN, XT_CP1_SA + XCHAL_CP1_SA_SIZE) -#define XT_CP3_SA ALIGNUP(XCHAL_CP3_SA_ALIGN, XT_CP2_SA + XCHAL_CP2_SA_SIZE) -#define XT_CP4_SA ALIGNUP(XCHAL_CP4_SA_ALIGN, XT_CP3_SA + XCHAL_CP3_SA_SIZE) -#define XT_CP5_SA ALIGNUP(XCHAL_CP5_SA_ALIGN, XT_CP4_SA + XCHAL_CP4_SA_SIZE) -#define XT_CP6_SA ALIGNUP(XCHAL_CP6_SA_ALIGN, XT_CP5_SA + XCHAL_CP5_SA_SIZE) -#define XT_CP7_SA ALIGNUP(XCHAL_CP7_SA_ALIGN, XT_CP6_SA + XCHAL_CP6_SA_SIZE) -#define XT_CP_SA_SIZE ALIGNUP(16, XT_CP7_SA + XCHAL_CP7_SA_SIZE) +#define XT_CP0_SA 0 +#define XT_CP1_SA ALIGNUP( XCHAL_CP1_SA_ALIGN, XT_CP0_SA + XCHAL_CP0_SA_SIZE ) +#define XT_CP2_SA ALIGNUP( XCHAL_CP2_SA_ALIGN, XT_CP1_SA + XCHAL_CP1_SA_SIZE ) +#define XT_CP3_SA ALIGNUP( XCHAL_CP3_SA_ALIGN, XT_CP2_SA + XCHAL_CP2_SA_SIZE ) +#define XT_CP4_SA ALIGNUP( XCHAL_CP4_SA_ALIGN, XT_CP3_SA + XCHAL_CP3_SA_SIZE ) +#define XT_CP5_SA ALIGNUP( XCHAL_CP5_SA_ALIGN, XT_CP4_SA + XCHAL_CP4_SA_SIZE ) +#define XT_CP6_SA ALIGNUP( XCHAL_CP6_SA_ALIGN, XT_CP5_SA + XCHAL_CP5_SA_SIZE ) +#define XT_CP7_SA ALIGNUP( XCHAL_CP7_SA_ALIGN, XT_CP6_SA + XCHAL_CP6_SA_SIZE ) +#define XT_CP_SA_SIZE ALIGNUP( 16, XT_CP7_SA + XCHAL_CP7_SA_SIZE ) /* Offsets within the overall save area: */ -#define XT_CPENABLE 0 /* (2 bytes) coprocessors active for this thread */ -#define XT_CPSTORED 2 /* (2 bytes) coprocessors saved for this thread */ -#define XT_CP_CS_ST 4 /* (2 bytes) coprocessor callee-saved regs stored for this thread */ -#define XT_CP_ASA 8 /* (4 bytes) ptr to aligned save area */ +#define XT_CPENABLE 0 /* (2 bytes) coprocessors active for this thread */ +#define XT_CPSTORED 2 /* (2 bytes) coprocessors saved for this thread */ +#define XT_CP_CS_ST 4 /* (2 bytes) coprocessor callee-saved regs stored for this thread */ +#define XT_CP_ASA 8 /* (4 bytes) ptr to aligned save area */ /* Overall size allows for dynamic alignment: */ -#define XT_CP_SIZE (12 + XT_CP_SA_SIZE + XCHAL_TOTAL_SA_ALIGN) -#else -#define XT_CP_SIZE 0 -#endif +#define XT_CP_SIZE ( 12 + XT_CP_SA_SIZE + XCHAL_TOTAL_SA_ALIGN ) +#else /* if XCHAL_CP_NUM > 0 */ +#define XT_CP_SIZE 0 +#endif /* if XCHAL_CP_NUM > 0 */ /* -------------------------------------------------------------------------------- - MACROS TO HANDLE ABI SPECIFICS OF FUNCTION ENTRY AND RETURN - - Convenient where the frame size requirements are the same for both ABIs. - ENTRY(sz), RET(sz) are for framed functions (have locals or make calls). - ENTRY0, RET0 are for frameless functions (no locals, no calls). - - where size = size of stack frame in bytes (must be >0 and aligned to 16). - For framed functions the frame is created and the return address saved at - base of frame (Call0 ABI) or as determined by hardware (Windowed ABI). - For frameless functions, there is no frame and return address remains in a0. - Note: Because CPP macros expand to a single line, macros requiring multi-line - expansions are implemented as assembler macros. -------------------------------------------------------------------------------- -*/ + * ------------------------------------------------------------------------------- + * MACROS TO HANDLE ABI SPECIFICS OF FUNCTION ENTRY AND RETURN + * + * Convenient where the frame size requirements are the same for both ABIs. + * ENTRY(sz), RET(sz) are for framed functions (have locals or make calls). + * ENTRY0, RET0 are for frameless functions (no locals, no calls). + * + * where size = size of stack frame in bytes (must be >0 and aligned to 16). + * For framed functions the frame is created and the return address saved at + * base of frame (Call0 ABI) or as determined by hardware (Windowed ABI). + * For frameless functions, there is no frame and return address remains in a0. + * Note: Because CPP macros expand to a single line, macros requiring multi-line + * expansions are implemented as assembler macros. + * ------------------------------------------------------------------------------- + */ #ifdef __ASSEMBLER__ -#ifdef __XTENSA_CALL0_ABI__ - /* Call0 */ - #define ENTRY(sz) entry1 sz - .macro entry1 size=0x10 - addi sp, sp, -\size - s32i a0, sp, 0 - .endm - #define ENTRY0 - #define RET(sz) ret1 sz - .macro ret1 size=0x10 - l32i a0, sp, 0 - addi sp, sp, \size - ret - .endm - #define RET0 ret -#else - /* Windowed */ - #define ENTRY(sz) entry sp, sz - #define ENTRY0 entry sp, 0x10 - #define RET(sz) retw - #define RET0 retw -#endif -#endif + #ifdef __XTENSA_CALL0_ABI__ + /* Call0 */ +#define ENTRY( sz ) entry1 sz + .macro entry1 size = 0x10 + addi sp, sp, -\ size + s32i a0, sp, 0 + .endm +#define ENTRY0 +#define RET( sz ) ret1 sz + .macro ret1 size = 0x10 + l32i a0, sp, 0 + addi sp, sp, \ size + ret + .endm +#define RET0 ret + #else /* ifdef __XTENSA_CALL0_ABI__ */ + /* Windowed */ +#define ENTRY( sz ) entry sp, sz +#define ENTRY0 entry sp, 0x10 +#define RET( sz ) retw +#define RET0 retw + #endif /* ifdef __XTENSA_CALL0_ABI__ */ +#endif /* ifdef __ASSEMBLER__ */ #endif /* XTENSA_CONTEXT_H */ diff --git a/Source/portable/ThirdParty/XCC/Xtensa/xtensa_init.c b/Source/portable/ThirdParty/XCC/Xtensa/xtensa_init.c index 4c8ad2a5d..2ad9d97c2 100644 --- a/Source/portable/ThirdParty/XCC/Xtensa/xtensa_init.c +++ b/Source/portable/ThirdParty/XCC/Xtensa/xtensa_init.c @@ -1,5 +1,5 @@ - /* - * FreeRTOS Kernel V10.6.2 +/* + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2015-2019 Cadence Design Systems, Inc. * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * @@ -36,35 +36,31 @@ #ifdef XT_BOARD -#include + #include #endif #include "xtensa_rtos.h" #ifdef XT_RTOS_TIMER_INT -unsigned _xt_tick_divisor = 0; /* cached number of cycles per tick */ + unsigned _xt_tick_divisor = 0; /* cached number of cycles per tick */ /* -Compute and initialize at run-time the tick divisor (the number of -processor clock cycles in an RTOS tick, used to set the tick timer). -Called when the processor clock frequency is not known at compile-time. -*/ -void _xt_tick_divisor_init(void) -{ -#ifdef XT_CLOCK_FREQ - - _xt_tick_divisor = (XT_CLOCK_FREQ / XT_TICK_PER_SEC); - -#else - - #ifdef XT_BOARD - _xt_tick_divisor = xtbsp_clock_freq_hz() / XT_TICK_PER_SEC; - #else - #error "No way to obtain processor clock frequency" - #endif /* XT_BOARD */ - -#endif /* XT_CLOCK_FREQ */ -} + * Compute and initialize at run-time the tick divisor (the number of + * processor clock cycles in an RTOS tick, used to set the tick timer). + * Called when the processor clock frequency is not known at compile-time. + */ + void _xt_tick_divisor_init( void ) + { + #ifdef XT_CLOCK_FREQ + _xt_tick_divisor = ( XT_CLOCK_FREQ / XT_TICK_PER_SEC ); + #else + #ifdef XT_BOARD + _xt_tick_divisor = xtbsp_clock_freq_hz() / XT_TICK_PER_SEC; + #else + #error "No way to obtain processor clock frequency" + #endif /* XT_BOARD */ + #endif /* XT_CLOCK_FREQ */ + } #endif /* XT_RTOS_TIMER_INT */ diff --git a/Source/portable/ThirdParty/XCC/Xtensa/xtensa_intr.c b/Source/portable/ThirdParty/XCC/Xtensa/xtensa_intr.c index 1644df50f..c22bad90d 100644 --- a/Source/portable/ThirdParty/XCC/Xtensa/xtensa_intr.c +++ b/Source/portable/ThirdParty/XCC/Xtensa/xtensa_intr.c @@ -1,5 +1,5 @@ - /* - * FreeRTOS Kernel V10.6.2 +/* + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2015-2019 Cadence Design Systems, Inc. * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * @@ -43,95 +43,110 @@ /* Handler table is in xtensa_intr_asm.S */ -extern xt_exc_handler _xt_exception_table[XCHAL_EXCCAUSE_NUM]; + extern xt_exc_handler _xt_exception_table[ XCHAL_EXCCAUSE_NUM ]; /* - Default handler for unhandled exceptions. -*/ -void xt_unhandled_exception(XtExcFrame *frame) -{ - exit(-1); -} + * Default handler for unhandled exceptions. + */ + void xt_unhandled_exception( XtExcFrame * frame ) + { + exit( -1 ); + } /* - This function registers a handler for the specified exception. - The function returns the address of the previous handler. - On error, it returns 0. -*/ -xt_exc_handler xt_set_exception_handler(int n, xt_exc_handler f) -{ - xt_exc_handler old; - - if( n < 0 || n >= XCHAL_EXCCAUSE_NUM ) - return 0; /* invalid exception number */ - - old = _xt_exception_table[n]; - - if (f) { - _xt_exception_table[n] = f; - } - else { - _xt_exception_table[n] = &xt_unhandled_exception; + * This function registers a handler for the specified exception. + * The function returns the address of the previous handler. + * On error, it returns 0. + */ + xt_exc_handler xt_set_exception_handler( int n, + xt_exc_handler f ) + { + xt_exc_handler old; + + if( ( n < 0 ) || ( n >= XCHAL_EXCCAUSE_NUM ) ) + { + return 0; /* invalid exception number */ + } + + old = _xt_exception_table[ n ]; + + if( f ) + { + _xt_exception_table[ n ] = f; + } + else + { + _xt_exception_table[ n ] = &xt_unhandled_exception; + } + + return( ( old == &xt_unhandled_exception ) ? 0 : old ); } - return ((old == &xt_unhandled_exception) ? 0 : old); -} - -#endif +#endif /* if XCHAL_HAVE_EXCEPTIONS */ #if XCHAL_HAVE_INTERRUPTS /* Handler table is in xtensa_intr_asm.S */ -typedef struct xt_handler_table_entry { - void * handler; - void * arg; -} xt_handler_table_entry; + typedef struct xt_handler_table_entry + { + void * handler; + void * arg; + } xt_handler_table_entry; -extern xt_handler_table_entry _xt_interrupt_table[XCHAL_NUM_INTERRUPTS]; + extern xt_handler_table_entry _xt_interrupt_table[ XCHAL_NUM_INTERRUPTS ]; /* - Default handler for unhandled interrupts. -*/ -void xt_unhandled_interrupt(void * arg) -{ - exit(-1); -} + * Default handler for unhandled interrupts. + */ + void xt_unhandled_interrupt( void * arg ) + { + exit( -1 ); + } /* - This function registers a handler for the specified interrupt. The "arg" - parameter specifies the argument to be passed to the handler when it is - invoked. The function returns the address of the previous handler. - On error, it returns 0. -*/ -xt_handler xt_set_interrupt_handler(int n, xt_handler f, void * arg) -{ - xt_handler_table_entry * entry; - xt_handler old; - - if( n < 0 || n >= XCHAL_NUM_INTERRUPTS ) - return 0; /* invalid interrupt number */ - if( Xthal_intlevel[n] > XCHAL_EXCM_LEVEL ) - return 0; /* priority level too high to safely handle in C */ - - entry = _xt_interrupt_table + n; - old = entry->handler; - - if (f) { - entry->handler = f; - entry->arg = arg; - } - else { - entry->handler = &xt_unhandled_interrupt; - entry->arg = (void*)n; + * This function registers a handler for the specified interrupt. The "arg" + * parameter specifies the argument to be passed to the handler when it is + * invoked. The function returns the address of the previous handler. + * On error, it returns 0. + */ + xt_handler xt_set_interrupt_handler( int n, + xt_handler f, + void * arg ) + { + xt_handler_table_entry * entry; + xt_handler old; + + if( ( n < 0 ) || ( n >= XCHAL_NUM_INTERRUPTS ) ) + { + return 0; /* invalid interrupt number */ + } + + if( Xthal_intlevel[ n ] > XCHAL_EXCM_LEVEL ) + { + return 0; /* priority level too high to safely handle in C */ + } + + entry = _xt_interrupt_table + n; + old = entry->handler; + + if( f ) + { + entry->handler = f; + entry->arg = arg; + } + else + { + entry->handler = &xt_unhandled_interrupt; + entry->arg = ( void * ) n; + } + + return( ( old == &xt_unhandled_interrupt ) ? 0 : old ); } - return ((old == &xt_unhandled_interrupt) ? 0 : old); -} - #endif /* XCHAL_HAVE_INTERRUPTS */ diff --git a/Source/portable/ThirdParty/XCC/Xtensa/xtensa_intr_asm.S b/Source/portable/ThirdParty/XCC/Xtensa/xtensa_intr_asm.S index 8737a4ba8..c17fa3c12 100644 --- a/Source/portable/ThirdParty/XCC/Xtensa/xtensa_intr_asm.S +++ b/Source/portable/ThirdParty/XCC/Xtensa/xtensa_intr_asm.S @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2015-2019 Cadence Design Systems, Inc. * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * diff --git a/Source/portable/ThirdParty/XCC/Xtensa/xtensa_overlay_os_hook.c b/Source/portable/ThirdParty/XCC/Xtensa/xtensa_overlay_os_hook.c index b3727fee9..828393e1b 100644 --- a/Source/portable/ThirdParty/XCC/Xtensa/xtensa_overlay_os_hook.c +++ b/Source/portable/ThirdParty/XCC/Xtensa/xtensa_overlay_os_hook.c @@ -1,5 +1,5 @@ - /* - * FreeRTOS Kernel V10.6.2 +/* + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2015-2019 Cadence Design Systems, Inc. * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * @@ -39,7 +39,7 @@ /* Mutex object that controls access to the overlay. Currently only one * overlay region is supported so one mutex suffices. */ -static SemaphoreHandle_t xt_overlay_mutex; + static SemaphoreHandle_t xt_overlay_mutex; /* This function should be overridden to provide OS specific init such @@ -47,30 +47,30 @@ static SemaphoreHandle_t xt_overlay_mutex; * Typically this mutex would be set up with priority inheritance. See * overlay manager documentation for more details. */ -void xt_overlay_init_os(void) -{ - /* Create the mutex for overlay access. Priority inheritance is - * required. - */ - xt_overlay_mutex = xSemaphoreCreateMutex(); -} + void xt_overlay_init_os( void ) + { + /* Create the mutex for overlay access. Priority inheritance is + * required. + */ + xt_overlay_mutex = xSemaphoreCreateMutex(); + } /* This function locks access to shared overlay resources, typically * by acquiring a mutex. */ -void xt_overlay_lock(void) -{ - xSemaphoreTake(xt_overlay_mutex, 0); -} + void xt_overlay_lock( void ) + { + xSemaphoreTake( xt_overlay_mutex, 0 ); + } /* This function releases access to shared overlay resources, typically * by unlocking a mutex. */ -void xt_overlay_unlock(void) -{ - xSemaphoreGive(xt_overlay_mutex); -} + void xt_overlay_unlock( void ) + { + xSemaphoreGive( xt_overlay_mutex ); + } -#endif +#endif /* if configUSE_MUTEX */ diff --git a/Source/portable/ThirdParty/XCC/Xtensa/xtensa_rtos.h b/Source/portable/ThirdParty/XCC/Xtensa/xtensa_rtos.h index 6d6b3fb62..645001222 100644 --- a/Source/portable/ThirdParty/XCC/Xtensa/xtensa_rtos.h +++ b/Source/portable/ThirdParty/XCC/Xtensa/xtensa_rtos.h @@ -1,5 +1,5 @@ - /* - * FreeRTOS Kernel V10.6.2 +/* + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2015-2019 Cadence Design Systems, Inc. * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * @@ -49,9 +49,9 @@ #define XTENSA_RTOS_H #ifdef __ASSEMBLER__ -#include + #include #else -#include + #include #endif #include @@ -59,180 +59,180 @@ #include /* -Include any RTOS specific definitions that are needed by this header. -*/ + * Include any RTOS specific definitions that are needed by this header. + */ #include /* -Convert FreeRTOSConfig definitions to XTENSA definitions. -However these can still be overridden from the command line. -*/ + * Convert FreeRTOSConfig definitions to XTENSA definitions. + * However these can still be overridden from the command line. + */ #ifndef XT_SIMULATOR - #if configXT_SIMULATOR - #define XT_SIMULATOR 1 /* Simulator mode */ - #endif + #if configXT_SIMULATOR + #define XT_SIMULATOR 1 /* Simulator mode */ + #endif #endif #ifndef XT_BOARD - #if configXT_BOARD - #define XT_BOARD 1 /* Board mode */ - #endif + #if configXT_BOARD + #define XT_BOARD 1 /* Board mode */ + #endif #endif #ifndef XT_TIMER_INDEX - #if defined configXT_TIMER_INDEX - #define XT_TIMER_INDEX configXT_TIMER_INDEX /* Index of hardware timer to be used */ - #endif + #if defined configXT_TIMER_INDEX + #define XT_TIMER_INDEX configXT_TIMER_INDEX /* Index of hardware timer to be used */ + #endif #endif #ifndef XT_INTEXC_HOOKS - #if configXT_INTEXC_HOOKS - #define XT_INTEXC_HOOKS 1 /* Enables exception hooks */ - #endif + #if configXT_INTEXC_HOOKS + #define XT_INTEXC_HOOKS 1 /* Enables exception hooks */ + #endif #endif -#if (!XT_SIMULATOR) && (!XT_BOARD) - #error Either XT_SIMULATOR or XT_BOARD must be defined. +#if ( !XT_SIMULATOR ) && ( !XT_BOARD ) + #error Either XT_SIMULATOR or XT_BOARD must be defined. #endif /* -Name of RTOS (for messages). -*/ + * Name of RTOS (for messages). + */ #define XT_RTOS_NAME FreeRTOS /* -Check some Xtensa configuration requirements and report error if not met. -Error messages can be customize to the RTOS port. -*/ + * Check some Xtensa configuration requirements and report error if not met. + * Error messages can be customize to the RTOS port. + */ #if !XCHAL_HAVE_XEA2 -#error "FreeRTOS/Xtensa requires XEA2 (exception architecture 2)." + #error "FreeRTOS/Xtensa requires XEA2 (exception architecture 2)." #endif /******************************************************************************* - -RTOS CALLOUT MACROS MAPPED TO RTOS PORT-SPECIFIC FUNCTIONS. - -Define callout macros used in generic Xtensa code to interact with the RTOS. -The macros are simply the function names for use in calls from assembler code. -Some of these functions may call back to generic functions in xtensa_context.h . - +* +* RTOS CALLOUT MACROS MAPPED TO RTOS PORT-SPECIFIC FUNCTIONS. +* +* Define callout macros used in generic Xtensa code to interact with the RTOS. +* The macros are simply the function names for use in calls from assembler code. +* Some of these functions may call back to generic functions in xtensa_context.h . +* *******************************************************************************/ /* -Inform RTOS of entry into an interrupt handler that will affect it. -Allows RTOS to manage switch to any system stack and count nesting level. -Called after minimal context has been saved, with interrupts disabled. -RTOS port can call0 _xt_context_save to save the rest of the context. -May only be called from assembly code by the 'call0' instruction. -*/ -// void XT_RTOS_INT_ENTER(void) -#define XT_RTOS_INT_ENTER _frxt_int_enter + * Inform RTOS of entry into an interrupt handler that will affect it. + * Allows RTOS to manage switch to any system stack and count nesting level. + * Called after minimal context has been saved, with interrupts disabled. + * RTOS port can call0 _xt_context_save to save the rest of the context. + * May only be called from assembly code by the 'call0' instruction. + */ +/* void XT_RTOS_INT_ENTER(void) */ +#define XT_RTOS_INT_ENTER _frxt_int_enter /* -Inform RTOS of completion of an interrupt handler, and give control to -RTOS to perform thread/task scheduling, switch back from any system stack -and restore the context, and return to the exit dispatcher saved in the -stack frame at XT_STK_EXIT. RTOS port can call0 _xt_context_restore -to save the context saved in XT_RTOS_INT_ENTER via _xt_context_save, -leaving only a minimal part of the context to be restored by the exit -dispatcher. This function does not return to the place it was called from. -May only be called from assembly code by the 'call0' instruction. -*/ -// void XT_RTOS_INT_EXIT(void) + * Inform RTOS of completion of an interrupt handler, and give control to + * RTOS to perform thread/task scheduling, switch back from any system stack + * and restore the context, and return to the exit dispatcher saved in the + * stack frame at XT_STK_EXIT. RTOS port can call0 _xt_context_restore + * to save the context saved in XT_RTOS_INT_ENTER via _xt_context_save, + * leaving only a minimal part of the context to be restored by the exit + * dispatcher. This function does not return to the place it was called from. + * May only be called from assembly code by the 'call0' instruction. + */ +/* void XT_RTOS_INT_EXIT(void) */ #define XT_RTOS_INT_EXIT _frxt_int_exit /* -Inform RTOS of the occurrence of a tick timer interrupt. -If RTOS has no tick timer, leave XT_RTOS_TIMER_INT undefined. -May be coded in or called from C or assembly, per ABI conventions. -RTOS may optionally define XT_TICK_PER_SEC in its own way (eg. macro). -*/ -// void XT_RTOS_TIMER_INT(void) -#define XT_RTOS_TIMER_INT _frxt_timer_int -#define XT_TICK_PER_SEC configTICK_RATE_HZ + * Inform RTOS of the occurrence of a tick timer interrupt. + * If RTOS has no tick timer, leave XT_RTOS_TIMER_INT undefined. + * May be coded in or called from C or assembly, per ABI conventions. + * RTOS may optionally define XT_TICK_PER_SEC in its own way (eg. macro). + */ +/* void XT_RTOS_TIMER_INT(void) */ +#define XT_RTOS_TIMER_INT _frxt_timer_int +#define XT_TICK_PER_SEC configTICK_RATE_HZ /* -Return in a15 the base address of the co-processor state save area for the -thread that triggered a co-processor exception, or 0 if no thread was running. -The state save area is structured as defined in xtensa_context.h and has size -XT_CP_SIZE. Co-processor instructions should only be used in thread code, never -in interrupt handlers or the RTOS kernel. May only be called from assembly code -and by the 'call0' instruction. A result of 0 indicates an unrecoverable error. -The implementation may use only a2-4, a15 (all other regs must be preserved). -*/ -// void* XT_RTOS_CP_STATE(void) + * Return in a15 the base address of the co-processor state save area for the + * thread that triggered a co-processor exception, or 0 if no thread was running. + * The state save area is structured as defined in xtensa_context.h and has size + * XT_CP_SIZE. Co-processor instructions should only be used in thread code, never + * in interrupt handlers or the RTOS kernel. May only be called from assembly code + * and by the 'call0' instruction. A result of 0 indicates an unrecoverable error. + * The implementation may use only a2-4, a15 (all other regs must be preserved). + */ +/* void* XT_RTOS_CP_STATE(void) */ #define XT_RTOS_CP_STATE _frxt_task_coproc_state /******************************************************************************* - -HOOKS TO DYNAMICALLY INSTALL INTERRUPT AND EXCEPTION HANDLERS PER LEVEL. - -This Xtensa RTOS port provides hooks for dynamically installing exception -and interrupt handlers to facilitate automated testing where each test -case can install its own handler for user exceptions and each interrupt -priority (level). This consists of an array of function pointers indexed -by interrupt priority, with index 0 being the user exception handler hook. -Each entry in the array is initially 0, and may be replaced by a function -pointer of type XT_INTEXC_HOOK. A handler may be uninstalled by installing 0. - -The handler for low and medium priority obeys ABI conventions so may be coded -in C. For the exception handler, the cause is the contents of the EXCCAUSE -reg, and the result is -1 if handled, else the cause (still needs handling). -For interrupt handlers, the cause is a mask of pending enabled interrupts at -that level, and the result is the same mask with the bits for the handled -interrupts cleared (those not cleared still need handling). This allows a test -case to either pre-handle or override the default handling for the exception -or interrupt level (see xtensa_vectors.S). - -High priority handlers (including NMI) must be coded in assembly, are always -called by 'call0' regardless of ABI, must preserve all registers except a0, -and must not use or modify the interrupted stack. The hook argument 'cause' -is not passed and the result is ignored, so as not to burden the caller with -saving and restoring a2 (it assumes only one interrupt per level - see the -discussion in high priority interrupts in xtensa_vectors.S). The handler -therefore should be coded to prototype 'void h(void)' even though it plugs -into an array of handlers of prototype 'unsigned h(unsigned)'. - -To enable interrupt/exception hooks, compile the RTOS with '-DXT_INTEXC_HOOKS'. - +* +* HOOKS TO DYNAMICALLY INSTALL INTERRUPT AND EXCEPTION HANDLERS PER LEVEL. +* +* This Xtensa RTOS port provides hooks for dynamically installing exception +* and interrupt handlers to facilitate automated testing where each test +* case can install its own handler for user exceptions and each interrupt +* priority (level). This consists of an array of function pointers indexed +* by interrupt priority, with index 0 being the user exception handler hook. +* Each entry in the array is initially 0, and may be replaced by a function +* pointer of type XT_INTEXC_HOOK. A handler may be uninstalled by installing 0. +* +* The handler for low and medium priority obeys ABI conventions so may be coded +* in C. For the exception handler, the cause is the contents of the EXCCAUSE +* reg, and the result is -1 if handled, else the cause (still needs handling). +* For interrupt handlers, the cause is a mask of pending enabled interrupts at +* that level, and the result is the same mask with the bits for the handled +* interrupts cleared (those not cleared still need handling). This allows a test +* case to either pre-handle or override the default handling for the exception +* or interrupt level (see xtensa_vectors.S). +* +* High priority handlers (including NMI) must be coded in assembly, are always +* called by 'call0' regardless of ABI, must preserve all registers except a0, +* and must not use or modify the interrupted stack. The hook argument 'cause' +* is not passed and the result is ignored, so as not to burden the caller with +* saving and restoring a2 (it assumes only one interrupt per level - see the +* discussion in high priority interrupts in xtensa_vectors.S). The handler +* therefore should be coded to prototype 'void h(void)' even though it plugs +* into an array of handlers of prototype 'unsigned h(unsigned)'. +* +* To enable interrupt/exception hooks, compile the RTOS with '-DXT_INTEXC_HOOKS'. +* *******************************************************************************/ -#define XT_INTEXC_HOOK_NUM (1 + XCHAL_NUM_INTLEVELS + XCHAL_HAVE_NMI) +#define XT_INTEXC_HOOK_NUM ( 1 + XCHAL_NUM_INTLEVELS + XCHAL_HAVE_NMI ) #ifndef __ASSEMBLER__ -typedef unsigned (*XT_INTEXC_HOOK)(unsigned cause); -extern volatile XT_INTEXC_HOOK _xt_intexc_hooks[XT_INTEXC_HOOK_NUM]; + typedef unsigned (* XT_INTEXC_HOOK)( unsigned cause ); + extern volatile XT_INTEXC_HOOK _xt_intexc_hooks[ XT_INTEXC_HOOK_NUM ]; #endif /******************************************************************************* - -CONVENIENCE INCLUSIONS. - -Ensures RTOS specific files need only include this one Xtensa-generic header. -These headers are included last so they can use the RTOS definitions above. - +* +* CONVENIENCE INCLUSIONS. +* +* Ensures RTOS specific files need only include this one Xtensa-generic header. +* These headers are included last so they can use the RTOS definitions above. +* *******************************************************************************/ #include "xtensa_context.h" #ifdef XT_RTOS_TIMER_INT -#include "xtensa_timer.h" + #include "xtensa_timer.h" #endif /******************************************************************************* - -Xtensa Port Version. - +* +* Xtensa Port Version. +* *******************************************************************************/ -#define XTENSA_PORT_VERSION 1.7 -#define XTENSA_PORT_VERSION_STRING "1.7" +#define XTENSA_PORT_VERSION 1.7 +#define XTENSA_PORT_VERSION_STRING "1.7" #endif /* XTENSA_RTOS_H */ diff --git a/Source/portable/ThirdParty/XCC/Xtensa/xtensa_timer.h b/Source/portable/ThirdParty/XCC/Xtensa/xtensa_timer.h index 037a78b41..dee2a663e 100644 --- a/Source/portable/ThirdParty/XCC/Xtensa/xtensa_timer.h +++ b/Source/portable/ThirdParty/XCC/Xtensa/xtensa_timer.h @@ -1,5 +1,5 @@ - /* - * FreeRTOS Kernel V10.6.2 +/* + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2015-2019 Cadence Design Systems, Inc. * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * @@ -47,118 +47,118 @@ #define XTENSA_TIMER_H #ifdef __ASSEMBLER__ -#include + #include #endif #include #include -#include "xtensa_rtos.h" /* in case this wasn't included directly */ +#include "xtensa_rtos.h" /* in case this wasn't included directly */ #include /* -Select timer to use for periodic tick, and determine its interrupt number -and priority. User may specify a timer by defining XT_TIMER_INDEX with -D, -in which case its validity is checked (it must exist in this core and must -not be on a high priority interrupt - an error will be reported in invalid). -Otherwise select the first low or medium priority interrupt timer available. -*/ + * Select timer to use for periodic tick, and determine its interrupt number + * and priority. User may specify a timer by defining XT_TIMER_INDEX with -D, + * in which case its validity is checked (it must exist in this core and must + * not be on a high priority interrupt - an error will be reported in invalid). + * Otherwise select the first low or medium priority interrupt timer available. + */ #if XCHAL_NUM_TIMERS == 0 - #error "This Xtensa configuration is unsupported, it has no timers." + #error "This Xtensa configuration is unsupported, it has no timers." #else -#ifndef XT_TIMER_INDEX - #if XCHAL_TIMER3_INTERRUPT != XTHAL_TIMER_UNCONFIGURED - #if XCHAL_INT_LEVEL(XCHAL_TIMER3_INTERRUPT) <= XCHAL_EXCM_LEVEL - #undef XT_TIMER_INDEX - #define XT_TIMER_INDEX 3 - #endif - #endif - #if XCHAL_TIMER2_INTERRUPT != XTHAL_TIMER_UNCONFIGURED - #if XCHAL_INT_LEVEL(XCHAL_TIMER2_INTERRUPT) <= XCHAL_EXCM_LEVEL - #undef XT_TIMER_INDEX - #define XT_TIMER_INDEX 2 - #endif - #endif - #if XCHAL_TIMER1_INTERRUPT != XTHAL_TIMER_UNCONFIGURED - #if XCHAL_INT_LEVEL(XCHAL_TIMER1_INTERRUPT) <= XCHAL_EXCM_LEVEL - #undef XT_TIMER_INDEX - #define XT_TIMER_INDEX 1 + #ifndef XT_TIMER_INDEX + #if XCHAL_TIMER3_INTERRUPT != XTHAL_TIMER_UNCONFIGURED + #if XCHAL_INT_LEVEL( XCHAL_TIMER3_INTERRUPT ) <= XCHAL_EXCM_LEVEL + #undef XT_TIMER_INDEX + #define XT_TIMER_INDEX 3 + #endif + #endif + #if XCHAL_TIMER2_INTERRUPT != XTHAL_TIMER_UNCONFIGURED + #if XCHAL_INT_LEVEL( XCHAL_TIMER2_INTERRUPT ) <= XCHAL_EXCM_LEVEL + #undef XT_TIMER_INDEX + #define XT_TIMER_INDEX 2 + #endif + #endif + #if XCHAL_TIMER1_INTERRUPT != XTHAL_TIMER_UNCONFIGURED + #if XCHAL_INT_LEVEL( XCHAL_TIMER1_INTERRUPT ) <= XCHAL_EXCM_LEVEL + #undef XT_TIMER_INDEX + #define XT_TIMER_INDEX 1 + #endif + #endif + #if XCHAL_TIMER0_INTERRUPT != XTHAL_TIMER_UNCONFIGURED + #if XCHAL_INT_LEVEL( XCHAL_TIMER0_INTERRUPT ) <= XCHAL_EXCM_LEVEL + #undef XT_TIMER_INDEX + #define XT_TIMER_INDEX 0 + #endif + #endif + #endif /* ifndef XT_TIMER_INDEX */ + #ifndef XT_TIMER_INDEX + #error "There is no suitable timer in this Xtensa configuration." #endif - #endif - #if XCHAL_TIMER0_INTERRUPT != XTHAL_TIMER_UNCONFIGURED - #if XCHAL_INT_LEVEL(XCHAL_TIMER0_INTERRUPT) <= XCHAL_EXCM_LEVEL - #undef XT_TIMER_INDEX - #define XT_TIMER_INDEX 0 - #endif - #endif -#endif -#ifndef XT_TIMER_INDEX - #error "There is no suitable timer in this Xtensa configuration." -#endif -#define XT_CCOMPARE (CCOMPARE + XT_TIMER_INDEX) -#define XT_TIMER_INTNUM XCHAL_TIMER_INTERRUPT(XT_TIMER_INDEX) -#define XT_TIMER_INTPRI XCHAL_INT_LEVEL(XT_TIMER_INTNUM) -#define XT_TIMER_INTEN (1 << XT_TIMER_INTNUM) + #define XT_CCOMPARE ( CCOMPARE + XT_TIMER_INDEX ) + #define XT_TIMER_INTNUM XCHAL_TIMER_INTERRUPT( XT_TIMER_INDEX ) + #define XT_TIMER_INTPRI XCHAL_INT_LEVEL( XT_TIMER_INTNUM ) + #define XT_TIMER_INTEN ( 1 << XT_TIMER_INTNUM ) -#if XT_TIMER_INTNUM == XTHAL_TIMER_UNCONFIGURED - #error "The timer selected by XT_TIMER_INDEX does not exist in this core." -#elif XT_TIMER_INTPRI > XCHAL_EXCM_LEVEL - #error "The timer interrupt cannot be high priority (use medium or low)." -#endif + #if XT_TIMER_INTNUM == XTHAL_TIMER_UNCONFIGURED + #error "The timer selected by XT_TIMER_INDEX does not exist in this core." + #elif XT_TIMER_INTPRI > XCHAL_EXCM_LEVEL + #error "The timer interrupt cannot be high priority (use medium or low)." + #endif #endif /* XCHAL_NUM_TIMERS */ /* -Set processor clock frequency, used to determine clock divisor for timer tick. -User should BE SURE TO ADJUST THIS for the Xtensa platform being used. -If using a supported board via the board-independent API defined in xtbsp.h, -this may be left undefined and frequency and tick divisor will be computed -and cached during run-time initialization. - -NOTE ON SIMULATOR: -Under the Xtensa instruction set simulator, the frequency can only be estimated -because it depends on the speed of the host and the version of the simulator. -Also because it runs much slower than hardware, it is not possible to achieve -real-time performance for most applications under the simulator. A frequency -too low does not allow enough time between timer interrupts, starving threads. -To obtain a more convenient but non-real-time tick duration on the simulator, -compile with xt-xcc option "-DXT_SIMULATOR". -Adjust this frequency to taste (it's not real-time anyway!). -*/ -#if defined(XT_SIMULATOR) && !defined(XT_CLOCK_FREQ) -#define XT_CLOCK_FREQ configCPU_CLOCK_HZ + * Set processor clock frequency, used to determine clock divisor for timer tick. + * User should BE SURE TO ADJUST THIS for the Xtensa platform being used. + * If using a supported board via the board-independent API defined in xtbsp.h, + * this may be left undefined and frequency and tick divisor will be computed + * and cached during run-time initialization. + * + * NOTE ON SIMULATOR: + * Under the Xtensa instruction set simulator, the frequency can only be estimated + * because it depends on the speed of the host and the version of the simulator. + * Also because it runs much slower than hardware, it is not possible to achieve + * real-time performance for most applications under the simulator. A frequency + * too low does not allow enough time between timer interrupts, starving threads. + * To obtain a more convenient but non-real-time tick duration on the simulator, + * compile with xt-xcc option "-DXT_SIMULATOR". + * Adjust this frequency to taste (it's not real-time anyway!). + */ +#if defined( XT_SIMULATOR ) && !defined( XT_CLOCK_FREQ ) + #define XT_CLOCK_FREQ configCPU_CLOCK_HZ #endif -#if !defined(XT_CLOCK_FREQ) && !defined(XT_BOARD) - #error "XT_CLOCK_FREQ must be defined for the target platform." +#if !defined( XT_CLOCK_FREQ ) && !defined( XT_BOARD ) + #error "XT_CLOCK_FREQ must be defined for the target platform." #endif /* -Default number of timer "ticks" per second (default 100 for 10ms tick). -RTOS may define this in its own way (if applicable) in xtensa_rtos.h. -User may redefine this to an optimal value for the application, either by -editing this here or in xtensa_rtos.h, or compiling with xt-xcc option -"-DXT_TICK_PER_SEC=" where is a suitable number. -*/ + * Default number of timer "ticks" per second (default 100 for 10ms tick). + * RTOS may define this in its own way (if applicable) in xtensa_rtos.h. + * User may redefine this to an optimal value for the application, either by + * editing this here or in xtensa_rtos.h, or compiling with xt-xcc option + * "-DXT_TICK_PER_SEC=" where is a suitable number. + */ #ifndef XT_TICK_PER_SEC -#define XT_TICK_PER_SEC configTICK_RATE_HZ /* 10 ms tick = 100 ticks per second */ + #define XT_TICK_PER_SEC configTICK_RATE_HZ /* 10 ms tick = 100 ticks per second */ #endif /* -Derivation of clock divisor for timer tick and interrupt (one per tick). -*/ + * Derivation of clock divisor for timer tick and interrupt (one per tick). + */ #ifdef XT_CLOCK_FREQ -#define XT_TICK_DIVISOR (XT_CLOCK_FREQ / XT_TICK_PER_SEC) + #define XT_TICK_DIVISOR ( XT_CLOCK_FREQ / XT_TICK_PER_SEC ) #endif #ifndef __ASSEMBLER__ -extern unsigned _xt_tick_divisor; -extern void _xt_tick_divisor_init(void); + extern unsigned _xt_tick_divisor; + extern void _xt_tick_divisor_init( void ); #endif -#endif /* XTENSA_TIMER_H */ +#endif /* XTENSA_TIMER_H */ diff --git a/Source/portable/ThirdParty/XCC/Xtensa/xtensa_vectors.S b/Source/portable/ThirdParty/XCC/Xtensa/xtensa_vectors.S index 355e2d50f..a6f88f94c 100644 --- a/Source/portable/ThirdParty/XCC/Xtensa/xtensa_vectors.S +++ b/Source/portable/ThirdParty/XCC/Xtensa/xtensa_vectors.S @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2015-2019 Cadence Design Systems, Inc. * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * diff --git a/Source/portable/ThirdParty/xClang/XCOREAI/port.c b/Source/portable/ThirdParty/xClang/XCOREAI/port.c new file mode 100644 index 000000000..ba4598b6b --- /dev/null +++ b/Source/portable/ThirdParty/xClang/XCOREAI/port.c @@ -0,0 +1,262 @@ +/* Copyright (c) 2019, XMOS Ltd, All rights reserved */ + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" +#include +#include +#include +#include + +static hwtimer_t xKernelTimer; + +uint32_t ulPortYieldRequired[ portMAX_CORE_COUNT ] = { pdFALSE }; + +/*-----------------------------------------------------------*/ + +void vIntercoreInterruptISR( void ) +{ + int xCoreID; + +/* debug_printf( "In KCALL: %u\n", ulData ); */ + xCoreID = rtos_core_id_get(); + ulPortYieldRequired[ xCoreID ] = pdTRUE; +} +/*-----------------------------------------------------------*/ + +DEFINE_RTOS_INTERRUPT_CALLBACK( pxKernelTimerISR, pvData ) +{ + uint32_t ulLastTrigger; + uint32_t ulNow; + int xCoreID; + UBaseType_t uxSavedInterruptStatus; + + xCoreID = 0; + + configASSERT( xCoreID == rtos_core_id_get() ); + + /* Need the next interrupt to be scheduled relative to + * the current trigger time, rather than the current + * time. */ + ulLastTrigger = hwtimer_get_trigger_time( xKernelTimer ); + + /* Check to see if the ISR is late. If it is, we don't + * want to schedule the next interrupt to be in the past. */ + ulNow = hwtimer_get_time( xKernelTimer ); + + if( ulNow - ulLastTrigger >= configCPU_CLOCK_HZ / configTICK_RATE_HZ ) + { + ulLastTrigger = ulNow; + } + + ulLastTrigger += configCPU_CLOCK_HZ / configTICK_RATE_HZ; + hwtimer_change_trigger_time( xKernelTimer, ulLastTrigger ); + + #if configUPDATE_RTOS_TIME_FROM_TICK_ISR == 1 + rtos_time_increment( RTOS_TICK_PERIOD( configTICK_RATE_HZ ) ); + #endif + + uxSavedInterruptStatus = taskENTER_CRITICAL_FROM_ISR(); + + if( xTaskIncrementTick() != pdFALSE ) + { + ulPortYieldRequired[ xCoreID ] = pdTRUE; + } + + taskEXIT_CRITICAL_FROM_ISR( uxSavedInterruptStatus ); +} +/*-----------------------------------------------------------*/ + +void vPortYieldOtherCore( int xOtherCoreID ) +{ + int xCoreID; + + /* + * This function must be called from within a critical section. + */ + + xCoreID = rtos_core_id_get(); + +/* debug_printf("%d->%d\n", xCoreID, xOtherCoreID); */ + +/* debug_printf("Yield core %d from %d\n", xOtherCoreID, xCoreID ); */ + + rtos_irq( xOtherCoreID, xCoreID ); +} +/*-----------------------------------------------------------*/ + +static int prvCoreInit( void ) +{ + int xCoreID; + + xCoreID = rtos_core_register(); + debug_printf( "Logical Core %d initializing as FreeRTOS Core %d\n", get_logical_core_id(), xCoreID ); + + asm volatile ( + "ldap r11, kexcept\n\t" + "set kep, r11\n\t" + : + : + : "r11" + ); + + rtos_irq_enable( configNUMBER_OF_CORES ); + + /* + * All threads wait here until all have enabled IRQs + */ + while( rtos_irq_ready() == pdFALSE ) + { + } + + if( xCoreID == 0 ) + { + uint32_t ulNow; + ulNow = hwtimer_get_time( xKernelTimer ); +/* debug_printf( "The time is now (%u)\n", ulNow ); */ + + ulNow += configCPU_CLOCK_HZ / configTICK_RATE_HZ; + + triggerable_setup_interrupt_callback( xKernelTimer, NULL, RTOS_INTERRUPT_CALLBACK( pxKernelTimerISR ) ); + hwtimer_set_trigger_time( xKernelTimer, ulNow ); + triggerable_enable_trigger( xKernelTimer ); + } + + return xCoreID; +} +/*-----------------------------------------------------------*/ + +DEFINE_RTOS_KERNEL_ENTRY( void, vPortStartSchedulerOnCore, void ) +{ + int xCoreID; + + xCoreID = prvCoreInit(); + + #if ( configUSE_CORE_INIT_HOOK == 1 ) + { + extern void vApplicationCoreInitHook( BaseType_t xCoreID ); + + vApplicationCoreInitHook( xCoreID ); + } + #endif + + debug_printf( "FreeRTOS Core %d initialized\n", xCoreID ); + + /* + * Restore the context of the first thread + * to run and jump into it. + */ + asm volatile ( + "mov r6, %0\n\t" /* R6 must be the FreeRTOS core ID*/ + "ldaw r5, dp[pxCurrentTCBs]\n\t" /* R5 must be the TCB list which is indexed by R6 */ + "bu _freertos_restore_ctx\n\t" + : /* no outputs */ + : "r" ( xCoreID ) + : "r5", "r6" + ); +} +/*-----------------------------------------------------------*/ + +/*-----------------------------------------------------------*/ +/* Public functions required by all ports below: */ +/*-----------------------------------------------------------*/ + +/* + * See header file for description. + */ +StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, + TaskFunction_t pxCode, + void * pvParameters ) +{ + /*debug_printf( "Top of stack was %p for task %p\n", pxTopOfStack, pxCode ); */ + + /* + * Grow the thread's stack by portTHREAD_CONTEXT_STACK_GROWTH + * so we can push the context onto it. + */ + pxTopOfStack -= portTHREAD_CONTEXT_STACK_GROWTH; + + uint32_t dp; + uint32_t cp; + + /* + * We need to get the current CP and DP pointers. + */ + asm volatile ( + "ldaw r11, cp[0]\n\t" /* get CP into R11 */ + "mov %0, r11\n\t" /* get R11 (CP) into cp */ + "ldaw r11, dp[0]\n\t" /* get DP into R11 */ + "mov %1, r11\n\t" /* get R11 (DP) into dp */ + : "=r" ( cp ), "=r" ( dp ) /* output 0 is cp, output 1 is dp */ + : /* there are no inputs */ + : "r11" /* R11 gets clobbered */ + ); + + /* + * Push the thread context onto the stack. + * Saved PC will point to the new thread's + * entry pointer. + * Interrupts will default to enabled. + * KEDI is also set to enable dual issue mode + * upon kernel entry. + */ + pxTopOfStack[ 1 ] = ( StackType_t ) pxCode; /* SP[1] := SPC */ + pxTopOfStack[ 2 ] = XS1_SR_IEBLE_MASK + | XS1_SR_KEDI_MASK; /* SP[2] := SSR */ + pxTopOfStack[ 3 ] = 0x00000000; /* SP[3] := SED */ + pxTopOfStack[ 4 ] = 0x00000000; /* SP[4] := ET */ + pxTopOfStack[ 5 ] = dp; /* SP[5] := DP */ + pxTopOfStack[ 6 ] = cp; /* SP[6] := CP */ + pxTopOfStack[ 7 ] = 0x00000000; /* SP[7] := LR */ + pxTopOfStack[ 8 ] = ( StackType_t ) pvParameters; /* SP[8] := R0 */ + pxTopOfStack[ 9 ] = 0x01010101; /* SP[9] := R1 */ + pxTopOfStack[ 10 ] = 0x02020202; /* SP[10] := R2 */ + pxTopOfStack[ 11 ] = 0x03030303; /* SP[11] := R3 */ + pxTopOfStack[ 12 ] = 0x04040404; /* SP[12] := R4 */ + pxTopOfStack[ 13 ] = 0x05050505; /* SP[13] := R5 */ + pxTopOfStack[ 14 ] = 0x06060606; /* SP[14] := R6 */ + pxTopOfStack[ 15 ] = 0x07070707; /* SP[15] := R7 */ + pxTopOfStack[ 16 ] = 0x08080808; /* SP[16] := R8 */ + pxTopOfStack[ 17 ] = 0x09090909; /* SP[17] := R9 */ + pxTopOfStack[ 18 ] = 0x10101010; /* SP[18] := R10 */ + pxTopOfStack[ 19 ] = 0x11111111; /* SP[19] := R11 */ + pxTopOfStack[ 20 ] = 0x00000000; /* SP[20] := vH and vSR */ + memset( &pxTopOfStack[ 21 ], 0, 32 ); /* SP[21 - 28] := vR */ + memset( &pxTopOfStack[ 29 ], 1, 32 ); /* SP[29 - 36] := vD */ + memset( &pxTopOfStack[ 37 ], 2, 32 ); /* SP[37 - 44] := vC */ + + /*debug_printf( "Top of stack is now %p for task %p\n", pxTopOfStack, pxCode ); */ + + /* + * Returns the new top of the stack + */ + return pxTopOfStack; +} +/*-----------------------------------------------------------*/ + +void vPortStartSMPScheduler( void ); + +/* + * See header file for description. + */ +BaseType_t xPortStartScheduler( void ) +{ + if( ( configNUMBER_OF_CORES > portMAX_CORE_COUNT ) || ( configNUMBER_OF_CORES <= 0 ) ) + { + return pdFAIL; + } + + rtos_locks_initialize(); + xKernelTimer = hwtimer_alloc(); + + vPortStartSMPScheduler(); + + return pdPASS; +} +/*-----------------------------------------------------------*/ + +void vPortEndScheduler( void ) +{ + /* Do not implement. */ +} +/*-----------------------------------------------------------*/ diff --git a/Source/portable/ThirdParty/xClang/XCOREAI/port.xc b/Source/portable/ThirdParty/xClang/XCOREAI/port.xc new file mode 100644 index 000000000..926b15086 --- /dev/null +++ b/Source/portable/ThirdParty/xClang/XCOREAI/port.xc @@ -0,0 +1,26 @@ +/* + * port.xc + * + * Created on: Jul 31, 2019 + * Author: mbruno + */ + +//#include "rtos_support.h" + +extern "C" { + +#include "FreeRTOSConfig.h" /* to get configNUMBER_OF_CORES */ +#ifndef configNUMBER_OF_CORES +#define configNUMBER_OF_CORES 1 +#endif + +void __xcore_interrupt_permitted_ugs_vPortStartSchedulerOnCore(void); + +} /* extern "C" */ + +void vPortStartSMPScheduler( void ) +{ + par (int i = 0; i < configNUMBER_OF_CORES; i++) { + __xcore_interrupt_permitted_ugs_vPortStartSchedulerOnCore(); + } +} diff --git a/Source/portable/ThirdParty/xClang/XCOREAI/portasm.S b/Source/portable/ThirdParty/xClang/XCOREAI/portasm.S new file mode 100644 index 000000000..7445672a0 --- /dev/null +++ b/Source/portable/ThirdParty/xClang/XCOREAI/portasm.S @@ -0,0 +1,189 @@ +// Copyright (c) 2020, XMOS Ltd, All rights reserved + +#include "rtos_support_rtos_config.h" + +/* The FreeRTOS interrupt code calls vTaskSwitchContext. +Therfore it must be added to the rtos_isr group with the +rest of the ISR callback functions. */ +.weak _fptrgroup.rtos_isr.nstackwords.group +.add_to_set _fptrgroup.rtos_isr.nstackwords.group, vTaskSwitchContext.nstackwords, vTaskSwitchContext + +.globl kexcept +.align 128 /* align the kernel section to 128 bytes */ +.type kexcept,@function +.issue_mode dual +.cc_top kexcept.function, kexcept +kexcept: + ldc r11, 0x0008 + shl r11, r11, 16 + ldc r9, 0x0080 + or r11, r11, r9 + bau r11 //_TrapHandler is at 0x00080080. TODO: Is it always? Why can't I access the symbol _TrapHandler? + +_yield: + {set sp, r4 /* Restore the task's SP to save the rest of its context. */ + get r11, id} /* Get the logical core ID into r11. */ + ldaw r0, dp[rtos_core_map] + ldw r0, r0[r11] /* Translate to the RTOS core ID into r0 */ + bu _yield_continue /* Skip the ulPortYieldRequired check and jump right to */ + /* the context save and switch. Also skips saving SPC */ + /* since the kcall handler has already saved it. */ + +.align 64 +kcall: + /* start saving the thread's context */ + extsp RTOS_SUPPORT_INTERRUPT_STACK_GROWTH + stw r1, sp[9] + stw r11, sp[19] + + /* kcall sets SPC to the instruction of the kcall rather than the next instruction */ + /* so we need to adjust the SPC value that we save to the stack: */ + stw spc, sp[1] /* save the saved program counter onto the stack... */ + ldw r1, sp[1] /* so that we can load it into r1 (which we have already saved). */ + add r1, r1, 4 /* Add 4 to the spc to make it point to the instruction after the kcall. */ + {stw r1, sp[1] /* Now save it to the stack. */ + + /* kcall uses the same common function as interrupt callbacks. */ + /* tell it to call _yield above. */ + ldap r11, _yield} + mov r1, r11 + + /* fall into rtos_interrupt_callback_common */ + +.globl rtos_interrupt_callback_common +rtos_interrupt_callback_common: + /* This is the body of the RTOS _xcore_c_interrupt_callback_XXX functions. */ + /* r1 = interrupt_callback_t function */ + + /* Save the thread's context onto the thread's stack. */ + /* The stack was extended for this by the wrapper function. */ + /* Begin only by saving some registers. The rest will be saved */ + /* later if vTaskSwitchContext() needs to be called. */ + /* DP and CP need to be saved because these are restored for the kernel ISR. */ + /* LR needs to be saved because it is clobbered when calling the callback. */ + /* r0-r3, and r11 need to be saved because the callback may clobber them. */ + /* r4 is saved because it is used here to hold the task SP. */ + + stw dp, sp[5] + stw cp, sp[6] + stw lr, sp[7] + stw r0, sp[8] +/*stw r1, sp[9] already saved by the wrapper function. */ + stw r2, sp[10] + stw r3, sp[11] + {stw r4, sp[12] +/*stw r11, sp[19] already saved by the wrapper function. */ + + ldaw r4, sp[0]} /* Get value of current stackpointer into r4. */ + + {kentsp 0 /* switch to the kernel stack. */ + /* The value 0 is safe to use since we don't need the SP */ + /* that it saves to KSP[0]. We already have it in r4. */ + + get r11, ed} /* Get the event data... */ + ldw dp, sp[3] /* (Restore CP and DP required for the RTOS ISR */ + ldw cp, sp[4] /* in case the active thread has modified them.) */ + {mov r0, r11 /* ...into the first argument for the callback function, */ + bla r1} /* and call the callback function. */ + + {set sp, r4 /* Restore the task's SP now. */ + + get r11, id} /* Get the logical core ID into r11. */ + ldaw r0, dp[rtos_core_map] + ldw r0, r0[r11] /* Translate to the RTOS core ID into r0. */ + ldaw r2, dp[ulPortYieldRequired] /* Get the yield required array into r2. */ + ldw r1, r2[r0] /* Is a yield required for this core? */ + {bf r1, _freertos_restore_ctx_partial /* If not, restore the context now. */ + ldc r1, 0} + stw r1, r2[r0] /* Otherwise, clear the yield required flag. */ + + /* Save the rest of the current task's context. */ + + /* Save standard xs2 regs */ + stw spc, sp[1] +_yield_continue: + stw ssr, sp[2] + stw sed, sp[3] + stw et, sp[4] + stw r5, sp[13] + stw r6, sp[14] + stw r7, sp[15] + stw r8, sp[16] + stw r9, sp[17] + stw r10, sp[18] +#if 1 + /* Save VPU status and headroom */ + vgetc r11 + {stw r11, sp[20] + /* Save VPU regs */ + ldaw r11, sp[21]} + {vstr r11[0] + ldaw r11, sp[29]} + {vstd r11[0] + ldaw r11, sp[37]} + vstc r11[0] +#endif + ldaw r5, dp[pxCurrentTCBs] /* Get the current TCB array into r5. */ + ldw r1, r5[r0] /* Get this core's current TCB pointer into r1. */ + stw r4, r1[0x0] /* Save the current task's SP to the first */ + /* word (top of stack) in the current TCB. */ + + {kentsp 0 /* switch back to the kernel stack. */ + + mov r6, r0} /* copy the RTOS core ID into r6 so we don't lose it. */ + ldap r11, vTaskSwitchContext + bla r11 /* Finally call vTaskSwitchContext(core_id) now that the task's */ + /* entire context is saved. Note the core id in r0 is the argument. */ + +//krestsp 0 /* unnecessary since KSP is already set and the SP */ + /* is being restored next from the current TCB. */ + +.globl _freertos_restore_ctx +_freertos_restore_ctx: + + ldw r0, r5[r6] /* get this core's current TCB pointer into r0 */ + ldw r0, r0[0x0] /* Get the top of the stack from the current TCB... */ + set sp, r0 /* into the stack pointer register. */ + + /* Restore the current task's context */ +#if 1 + /* Restore VPU regs */ + ldaw r11, sp[37] + {vldc r11[0] + ldaw r11, sp[29]} + {vldd r11[0] + ldaw r11, sp[21]} + vldr r11[0] + /* Restore VPU status and headroom */ + ldw r11, sp[20] + vsetc r11 +#endif + /* Restore standard xs2 regs */ + ldw spc, sp[1] + ldw ssr, sp[2] + ldw sed, sp[3] + ldw et, sp[4] + ldw r5, sp[13] + ldw r6, sp[14] + ldw r7, sp[15] + ldw r8, sp[16] + ldw r9, sp[17] + ldw r10, sp[18] +_freertos_restore_ctx_partial: + ldw dp, sp[5] + ldw cp, sp[6] + ldw lr, sp[7] + ldw r0, sp[8] + ldw r1, sp[9] + ldw r2, sp[10] + ldw r3, sp[11] + ldw r4, sp[12] + {ldw r11, sp[19] + + /* shrink the stack by the size of the context just restored */ + ldaw sp, sp[RTOS_SUPPORT_INTERRUPT_STACK_GROWTH]} + + kret /* exit kernel mode and return to the thread */ + +.cc_bottom kexcept.function + diff --git a/Source/portable/ThirdParty/xClang/XCOREAI/portmacro.h b/Source/portable/ThirdParty/xClang/XCOREAI/portmacro.h new file mode 100644 index 000000000..06f2b75dc --- /dev/null +++ b/Source/portable/ThirdParty/xClang/XCOREAI/portmacro.h @@ -0,0 +1,214 @@ +/* Copyright (c) 2020, XMOS Ltd, All rights reserved */ + +#ifndef PORTMACRO_H + #define PORTMACRO_H + + #ifndef __ASSEMBLER__ + +/* Inclusion of xc1.h will result in clock being defined as a type. + * By default, FreeRTOS will require standard time.h, where clock is a function. + */ + #ifndef USE_XCORE_CLOCK_TYPE + #define _clock_defined + #endif + + #include + #include "rtos_support.h" + + #ifdef __cplusplus + extern "C" { + #endif + +/* Type definitions. */ + #define portSTACK_TYPE uint32_t + typedef portSTACK_TYPE StackType_t; + typedef double portDOUBLE; + typedef int32_t BaseType_t; + typedef uint32_t UBaseType_t; + + #define portBASE_TYPE BaseType_t + + #if ( configUSE_16_BIT_TICKS == 1 ) + typedef uint16_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffff + #else + typedef uint32_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffffffffUL + +/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do + * not need to be guarded with a critical section. */ + #define portTICK_TYPE_IS_ATOMIC 1 + #endif +/*-----------------------------------------------------------*/ + + #endif /* __ASSEMBLER__ */ + +/* Architecture specifics. These can be used by assembly files as well. */ + #define portSTACK_GROWTH ( -1 ) + #define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) + #define portBYTE_ALIGNMENT 8 + #define portCRITICAL_NESTING_IN_TCB 1 + #define portMAX_CORE_COUNT 8 + #ifndef configNUMBER_OF_CORES + #define configNUMBER_OF_CORES 1 + #endif + +/* This may be set to zero in the config file if the rtos_time + * functions are not needed or if it is incremented elsewhere. */ + #ifndef configUPDATE_RTOS_TIME_FROM_TICK_ISR + #define configUPDATE_RTOS_TIME_FROM_TICK_ISR 1 + #endif + +/* + * When entering an ISR we need to grow the stack by one more word than + * we actually need to save the thread context. This is because there are + * some functions, written in assembly *cough* memcpy() *cough*, that think + * it is OK to store words at SP[0]. Therefore the ISR must leave SP[0] alone + * even though it is normally not necessary to do so. + */ + #define portTHREAD_CONTEXT_STACK_GROWTH RTOS_SUPPORT_INTERRUPT_STACK_GROWTH + + #ifndef __ASSEMBLER__ + +/* Check validity of number of cores specified in config */ + #if ( configNUMBER_OF_CORES < 1 || portMAX_CORE_COUNT < configNUMBER_OF_CORES ) + #error "Invalid number of cores specified in config!" + #endif + + #define portMEMORY_BARRIER() RTOS_MEMORY_BARRIER() + #define portTASK_STACK_DEPTH( pxTaskCode ) RTOS_THREAD_STACK_SIZE( pxTaskCode ) +/*-----------------------------------------------------------*/ + +/* Scheduler utilities. */ + #define portYIELD() asm volatile ( "KCALLI_lu6 0" ::: "memory" ) + + #define portEND_SWITCHING_ISR( xSwitchRequired ) \ + do \ + { \ + if( xSwitchRequired != pdFALSE ) \ + { \ + extern uint32_t ulPortYieldRequired[ portMAX_CORE_COUNT ]; \ + ulPortYieldRequired[ portGET_CORE_ID() ] = pdTRUE; \ + } \ + } while( 0 ) + + #define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x ) +/*-----------------------------------------------------------*/ + +/* SMP utilities. */ + #define portGET_CORE_ID() rtos_core_id_get() + + void vPortYieldOtherCore( int xOtherCoreID ); + #define portYIELD_CORE( x ) vPortYieldOtherCore( x ) +/*-----------------------------------------------------------*/ + +/* Architecture specific optimisations. */ + #ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION + #define configUSE_PORT_OPTIMISED_TASK_SELECTION 0 + #endif + + #if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 + +/* Store/clear the ready priorities in a bit map. */ + #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) ) + #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) ) + +/*-----------------------------------------------------------*/ + + #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - ( uint32_t ) __builtin_clz( uxReadyPriorities ) ) + + #endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */ +/*-----------------------------------------------------------*/ + +/* Critical section management. */ + + #define portGET_INTERRUPT_STATE() rtos_interrupt_mask_get() + +/* + * This differs from the standard portDISABLE_INTERRUPTS() + * in that it also returns what the interrupt state was + * before it disabling interrupts. + */ + #define portDISABLE_INTERRUPTS() rtos_interrupt_mask_all() + + #define portENABLE_INTERRUPTS() rtos_interrupt_unmask_all() + +/* + * Port set interrupt mask and clear interrupt mask. + */ + #define portSET_INTERRUPT_MASK() rtos_interrupt_mask_all() + #define portCLEAR_INTERRUPT_MASK( ulState ) rtos_interrupt_mask_set( ulState ) + + #define portSET_INTERRUPT_MASK_FROM_ISR() ( 0 ) + #define portCLEAR_INTERRUPT_MASK_FROM_ISR( x ) ( ( void ) x ) + +/* + * Will enable interrupts if ulState is non-zero. + */ + #define portRESTORE_INTERRUPTS( ulState ) rtos_interrupt_mask_set( ulState ) + +/* + * Returns non-zero if currently running in an + * ISR or otherwise in kernel mode. + */ + #define portCHECK_IF_IN_ISR() rtos_isr_running() + + #define portASSERT_IF_IN_ISR() configASSERT( portCHECK_IF_IN_ISR() == 0 ) + + #define portGET_ISR_LOCK() rtos_lock_acquire( 0 ) + #define portRELEASE_ISR_LOCK() rtos_lock_release( 0 ) + #define portGET_TASK_LOCK() rtos_lock_acquire( 1 ) + #define portRELEASE_TASK_LOCK() rtos_lock_release( 1 ) + + void vTaskEnterCritical( void ); + void vTaskExitCritical( void ); + #define portENTER_CRITICAL() vTaskEnterCritical() + #define portEXIT_CRITICAL() vTaskExitCritical() + + extern UBaseType_t vTaskEnterCriticalFromISR( void ); + extern void vTaskExitCriticalFromISR( UBaseType_t uxSavedInterruptStatus ); + #define portENTER_CRITICAL_FROM_ISR vTaskEnterCriticalFromISR + #define portEXIT_CRITICAL_FROM_ISR vTaskExitCriticalFromISR + +/*-----------------------------------------------------------*/ + +/* Runtime stats support */ + #if ( configGENERATE_RUN_TIME_STATS == 1 ) + int xscope_gettime( void ); + #define portCONFIGURE_TIMER_FOR_RUN_TIME_STATS() /* nothing needed here */ + #define portGET_RUN_TIME_COUNTER_VALUE() xscope_gettime() + #endif +/*-----------------------------------------------------------*/ + +/* Maps sprintf and snprintf to the lite version in lib_rtos_support */ + #if ( configUSE_DEBUG_SPRINTF == 1 ) + #define sprintf( ... ) rtos_sprintf( __VA_ARGS__ ) + #define snprintf( ... ) rtos_snprintf( __VA_ARGS__ ) + #endif + +/* Attribute for the pxCallbackFunction member of the Timer_t struct. + * Required by xcc to calculate stack usage. */ + #define portTIMER_CALLBACK_ATTRIBUTE __attribute__( ( fptrgroup( "timerCallbackGroup" ) ) ) + +/* Timer callback function macros. For xcc this ensures they get added to the timer callback + * group so that stack usage for certain functions in timers.c can be calculated. */ + #define portTIMER_CALLBACK_FUNCTION_PROTO( vFunction, xTimer ) void vFunction( TimerHandle_t xTimer ) + #define portTIMER_CALLBACK_FUNCTION( vFunction, xTimer ) portTIMER_CALLBACK_ATTRIBUTE void vFunction( TimerHandle_t xTimer ) + +/*-----------------------------------------------------------*/ + +/* Task function macros as described on the FreeRTOS.org WEB site. These are + * not necessary for to use this port. They are defined so the common demo files + * (which build with all the ports) will build. */ + #define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters ) + #define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters ) +/*-----------------------------------------------------------*/ + + + #ifdef __cplusplus +} + #endif + + #endif /* __ASSEMBLER__ */ + +#endif /* PORTMACRO_H */ diff --git a/Source/portable/ThirdParty/xClang/XCOREAI/rtos_support_rtos_config.h b/Source/portable/ThirdParty/xClang/XCOREAI/rtos_support_rtos_config.h new file mode 100644 index 000000000..3e4140903 --- /dev/null +++ b/Source/portable/ThirdParty/xClang/XCOREAI/rtos_support_rtos_config.h @@ -0,0 +1,95 @@ +/* Copyright (c) 2020, XMOS Ltd, All rights reserved */ + +#ifndef RTOS_SUPPORT_RTOS_CONFIG_H_ +#define RTOS_SUPPORT_RTOS_CONFIG_H_ + +/** + * Lets the application know that the RTOS in use is FreeRTOS. + */ +#define RTOS_FREERTOS 1 + +/** + * The number of words to extend the stack by when entering an ISR. + * + * When entering an ISR we need to grow the stack by one more word than + * we actually need to save the thread context. This is because there are + * some functions, written in assembly *cough* memcpy() *cough*, that think + * it is OK to store words at SP[0]. Therefore the ISR must leave SP[0] alone + * even though it is normally not necessary to do so. + */ +#define RTOS_SUPPORT_INTERRUPT_STACK_GROWTH ( 44 + 1 ) + +/** + * The word offset into the stack where R1 is to be stored after it + * is extended when saving a thread's context. + */ +#define RTOS_SUPPORT_INTERRUPT_R1_STACK_OFFSET 9 + +/** + * The word offset into the stack where R11 is to be stored after it + * is extended when saving a thread's context. + */ +#define RTOS_SUPPORT_INTERRUPT_R11_STACK_OFFSET 19 + +/** + * The RTOS provided handler that should run when a + * core receives an intercore interrupt request. + */ +#define RTOS_INTERCORE_INTERRUPT_ISR() \ + do { \ + void vIntercoreInterruptISR( void ); \ + vIntercoreInterruptISR(); \ + } while( 0 ) + +/** + * The number of hardware locks that the RTOS + * requires. For a single core RTOS this could be + * zero. Locks are recursive. + * + * Note that the IRQ routines require a lock and + * will share the first one with the RTOS. + */ +#define RTOS_LOCK_COUNT 2 + +/** + * Remaps all calls to debug_printf() to rtos_printf(). + * When this is on, files should not include both rtos_support.h + * and debug_print.h. + */ +#define RTOS_DEBUG_PRINTF_REMAP 1 + + +#ifdef configENABLE_DEBUG_PRINTF + #if configENABLE_DEBUG_PRINTF + +/* ensure that debug_printf is enabled */ + #ifdef DEBUG_PRINT_ENABLE + #undef DEBUG_PRINT_ENABLE + #endif + #define DEBUG_PRINT_ENABLE 1 + + #ifndef configTASKS_DEBUG + #define configTASKS_DEBUG 0 + #endif + #if configTASKS_DEBUG == 1 + #define DEBUG_PRINT_ENABLE_FREERTOS_TASKS 1 + #else + #define DEBUG_PRINT_DISABLE_FREERTOS_TASKS 1 + #endif + + #else /* configENABLE_DEBUG_PRINTF */ + +/* ensure that debug_printf is disabled */ + #ifdef DEBUG_UNIT + #undef DEBUG_UNIT + #endif + #ifdef DEBUG_PRINT_ENABLE + #undef DEBUG_PRINT_ENABLE + #endif + + #define DEBUG_PRINT_ENABLE 0 + + #endif /* configENABLE_DEBUG_PRINTF */ +#endif /* ifdef configENABLE_DEBUG_PRINTF */ + +#endif /* RTOS_SUPPORT_RTOS_CONFIG_H_ */ diff --git a/Source/portable/WizC/PIC18/Drivers/Tick/Tick.c b/Source/portable/WizC/PIC18/Drivers/Tick/Tick.c index 0116a0a94..5ce4a1105 100644 --- a/Source/portable/WizC/PIC18/Drivers/Tick/Tick.c +++ b/Source/portable/WizC/PIC18/Drivers/Tick/Tick.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/Source/portable/WizC/PIC18/Drivers/Tick/isrTick.c b/Source/portable/WizC/PIC18/Drivers/Tick/isrTick.c index 09e9a3f7f..f597d95e9 100644 --- a/Source/portable/WizC/PIC18/Drivers/Tick/isrTick.c +++ b/Source/portable/WizC/PIC18/Drivers/Tick/isrTick.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/Source/portable/WizC/PIC18/addFreeRTOS.h b/Source/portable/WizC/PIC18/addFreeRTOS.h index bb4227dae..f6b23be03 100644 --- a/Source/portable/WizC/PIC18/addFreeRTOS.h +++ b/Source/portable/WizC/PIC18/addFreeRTOS.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/Source/portable/WizC/PIC18/port.c b/Source/portable/WizC/PIC18/port.c index 9f80512c1..835aeb7e7 100644 --- a/Source/portable/WizC/PIC18/port.c +++ b/Source/portable/WizC/PIC18/port.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -28,7 +28,7 @@ /* Changes from V3.2.1 - + CallReturn Depth increased from 8 to 10 levels to accomodate wizC/fedC V12. + + CallReturn Depth increased from 8 to 10 levels to accommodate wizC/fedC V12. Changes from V3.2.0 + TBLPTRU is now initialised to zero during the initial stack creation of a new task. This solves diff --git a/Source/portable/WizC/PIC18/portmacro.h b/Source/portable/WizC/PIC18/portmacro.h index 40f43efa2..f9912df1e 100644 --- a/Source/portable/WizC/PIC18/portmacro.h +++ b/Source/portable/WizC/PIC18/portmacro.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -176,7 +176,7 @@ extern uint16_t usCalcMinStackSize; * the stack, then saves the new top of stack into the TCB. TOSU and TBLPTRU * are only saved/restored on devices with more than 64kB (32k Words) ROM. * - * The stackpointer is helt by WizC in FSR2 and points to the first free byte. + * The stackpointer is held by WizC in FSR2 and points to the first free byte. * WizC uses a "downgrowing" stack. There is no framepointer. * * We keep track of the interruptstatus using ucCriticalNesting. When this @@ -189,7 +189,7 @@ extern uint16_t usCalcMinStackSize; * re-enabled when the interrupted task is switched back in. * * If this is called from a manual context switch (i.e. from a call to yield), - * then we want to keep the current value of ucCritialNesting so it is restored + * then we want to keep the current value of ucCriticalNesting so it is restored * with its current value. This allows a yield from within a critical section. * * The compiler uses some locations at the bottom of RAM for temporary @@ -376,7 +376,7 @@ extern uint16_t usCalcMinStackSize; ; interrupts need to be enabled. This is done via a \ ; retfie instruction because we need the \ ; interrupt-enabling and the return to the restored \ - ; task to be uninterruptable. \ + ; task to be uninterruptible. \ ; Because bsr, status and W are affected by the test \ ; they are restored after the test. \ ; \ diff --git a/Source/portable/oWatcom/16BitDOS/Flsh186/port.c b/Source/portable/oWatcom/16BitDOS/Flsh186/port.c index c8e99c470..1096fdbd0 100644 --- a/Source/portable/oWatcom/16BitDOS/Flsh186/port.c +++ b/Source/portable/oWatcom/16BitDOS/Flsh186/port.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/Source/portable/oWatcom/16BitDOS/Flsh186/portmacro.h b/Source/portable/oWatcom/16BitDOS/Flsh186/portmacro.h index db5f279c6..171cd6575 100644 --- a/Source/portable/oWatcom/16BitDOS/Flsh186/portmacro.h +++ b/Source/portable/oWatcom/16BitDOS/Flsh186/portmacro.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/Source/portable/oWatcom/16BitDOS/PC/port.c b/Source/portable/oWatcom/16BitDOS/PC/port.c index 0d9238c47..3b98ff638 100644 --- a/Source/portable/oWatcom/16BitDOS/PC/port.c +++ b/Source/portable/oWatcom/16BitDOS/PC/port.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/Source/portable/oWatcom/16BitDOS/PC/portmacro.h b/Source/portable/oWatcom/16BitDOS/PC/portmacro.h index 4fb320715..8f9a4343a 100644 --- a/Source/portable/oWatcom/16BitDOS/PC/portmacro.h +++ b/Source/portable/oWatcom/16BitDOS/PC/portmacro.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/Source/portable/oWatcom/16BitDOS/common/portasm.h b/Source/portable/oWatcom/16BitDOS/common/portasm.h index da987073b..37bccb83e 100644 --- a/Source/portable/oWatcom/16BitDOS/common/portasm.h +++ b/Source/portable/oWatcom/16BitDOS/common/portasm.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/Source/portable/oWatcom/16BitDOS/common/portcomn.c b/Source/portable/oWatcom/16BitDOS/common/portcomn.c index 083726b17..628ac187d 100644 --- a/Source/portable/oWatcom/16BitDOS/common/portcomn.c +++ b/Source/portable/oWatcom/16BitDOS/common/portcomn.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/Source/portable/template/port.c b/Source/portable/template/port.c new file mode 100644 index 000000000..31d3f8e2a --- /dev/null +++ b/Source/portable/template/port.c @@ -0,0 +1,78 @@ +/* + * FreeRTOS Kernel V11.0.1 + * license and copyright intentionally withheld to promote copying into user code. + */ + +#include "FreeRTOS.h" +#include "task.h" + +BaseType_t xPortStartScheduler( void ) +{ + return pdTRUE; +} + +void vPortEndScheduler( void ) +{ +} + +StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, + TaskFunction_t pxCode, + void * pvParameters ) +{ + return NULL; +} + +void vPortYield( void ) +{ + /* Save the current Context */ + + /* Switch to the highest priority task that is ready to run. */ + #if ( configNUMBER_OF_CORES == 1 ) + { + vTaskSwitchContext(); + } + #else + { + vTaskSwitchContext( portGET_CORE_ID() ); + } + #endif + + /* Start executing the task we have just switched to. */ +} + +static void prvTickISR( void ) +{ + /* Interrupts must have been enabled for the ISR to fire, so we have to + * save the context with interrupts enabled. */ + + #if ( configNUMBER_OF_CORES == 1 ) + { + /* Maintain the tick count. */ + if( xTaskIncrementTick() != pdFALSE ) + { + /* Switch to the highest priority task that is ready to run. */ + vTaskSwitchContext(); + } + } + #else + { + UBaseType_t ulPreviousMask; + + /* Tasks or ISRs running on other cores may still in critical section in + * multiple cores environment. Incrementing tick needs to performed in + * critical section. */ + ulPreviousMask = taskENTER_CRITICAL_FROM_ISR(); + + /* Maintain the tick count. */ + if( xTaskIncrementTick() != pdFALSE ) + { + /* Switch to the highest priority task that is ready to run. */ + vTaskSwitchContext( portGET_CORE_ID() ); + } + + taskEXIT_CRITICAL_FROM_ISR( ulPreviousMask ); + } + #endif /* if ( configNUMBER_OF_CORES == 1 ) */ + + /* start executing the new task */ +} diff --git a/Source/portable/template/portmacro.h b/Source/portable/template/portmacro.h new file mode 100644 index 000000000..619571f2d --- /dev/null +++ b/Source/portable/template/portmacro.h @@ -0,0 +1,142 @@ +/* + * FreeRTOS Kernel V11.0.1 + * license and copyright intentionally withheld to promote copying into user code. + */ + +#ifndef PORTMACRO_H +#define PORTMACRO_H + +/*----------------------------------------------------------- + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the + * given hardware and compiler. + * + * These settings should not be altered. + *----------------------------------------------------------- + */ + +/* Type definitions. */ +#define portCHAR char +#define portFLOAT float +#define portDOUBLE double +#define portLONG long +#define portSHORT int +#define portSTACK_TYPE uint8_t +#define portBASE_TYPE char + +#define portSTACK_GROWTH ( -1 ) +#define portBYTE_ALIGNMENT 4 +#define portPOINTER_SIZE_TYPE size_t +typedef portSTACK_TYPE StackType_t; +typedef signed char BaseType_t; +typedef unsigned char UBaseType_t; + +#if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS ) + typedef uint16_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffff +#elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS ) + typedef uint32_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffffffffUL +#elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_64_BITS ) + typedef uint64_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffffffffffffffffULL +#else + #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width. +#endif + +/* Architecture specific optimisations. */ +#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION + #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1 +#endif + +#if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 + +/* Check the configuration. */ + #if ( configMAX_PRIORITIES > 32 ) + #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice. + #endif + +/* Store/clear the ready priorities in a bit map. */ + #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) ) + #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) ) + +/*-----------------------------------------------------------*/ + + #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) \ + do { \ + uxTopPriority = 0; \ + } while( 0 ) + +#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */ + +/* Disable the interrupts */ +#define portDISABLE_INTERRUPTS() do {} while( 0 ) + +/* Enable the interrupts */ +#define portENABLE_INTERRUPTS() do {} while( 0 ) + +#if ( configNUMBER_OF_CORES == 1 ) +/* preserve current interrupt state and then disable interrupts */ + #define portENTER_CRITICAL() do {} while( 0 ) + +/* restore previously preserved interrupt state */ + #define portEXIT_CRITICAL() do {} while( 0 ) +#else + +/* The port can maintain the critical nesting count in TCB or maintain the critical + * nesting count in the port. */ + #define portCRITICAL_NESTING_IN_TCB 1 + +/* vTaskEnterCritical and vTaskExitCritical should be used in the implementation + * of portENTER/EXIT_CRITICAL if the number of cores is more than 1 in the system. */ + #define portENTER_CRITICAL vTaskEnterCritical + #define portEXIT_CRITICAL vTaskExitCritical + +/* vTaskEnterCriticalFromISR and vTaskExitCriticalFromISR should be used in the + * implementation of portENTER/EXIT_CRITICAL_FROM_ISR if the number of cores is + * more than 1 in the system. */ + #define portENTER_CRITICAL_FROM_ISR vTaskEnterCriticalFromISR + #define portEXIT_CRITICAL_FROM_ISR vTaskExitCriticalFromISR + +#endif /* if ( configNUMBER_OF_CORES == 1 ) */ + +extern void vPortYield( void ); +#define portYIELD() vPortYield() + +/* Task function macros as described on the FreeRTOS.org WEB site. */ +#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters ) +#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters ) + +#if ( configNUMBER_OF_CORES > 1 ) + /* Return the core ID on which the code is running. */ + #define portGET_CORE_ID() 0 + +/* Set the interrupt mask. */ + #define portSET_INTERRUPT_MASK() 0 + +/* Clear the interrupt mask. */ + #define portCLEAR_INTERRUPT_MASK( x ) ( ( void ) ( x ) ) + +/* Request the core ID x to yield. */ + #define portYIELD_CORE( x ) do {} while( 0 ) + +/* Acquire the TASK lock. TASK lock is a recursive lock. + * It should be able to be locked by the same core multiple times. */ + #define portGET_TASK_LOCK() do {} while( 0 ) + +/* Release the TASK lock. If a TASK lock is locked by the same core multiple times, + * it should be released as many times as it is locked. */ + #define portRELEASE_TASK_LOCK() do {} while( 0 ) + +/* Acquire the ISR lock. ISR lock is a recursive lock. + * It should be able to be locked by the same core multiple times. */ + #define portGET_ISR_LOCK() do {} while( 0 ) + +/* Release the ISR lock. If a ISR lock is locked by the same core multiple times, \ + * it should be released as many times as it is locked. */ + #define portRELEASE_ISR_LOCK() do {} while( 0 ) + +#endif /* if ( configNUMBER_OF_CORES > 1 ) */ + +#endif /* PORTMACRO_H */ diff --git a/Source/queue.c b/Source/queue.c index 40edbe466..58955920c 100644 --- a/Source/queue.c +++ b/Source/queue.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -42,11 +42,10 @@ #include "croutine.h" #endif -/* Lint e9021, e961 and e750 are suppressed as a MISRA exception justified - * because the MPU ports require MPU_WRAPPERS_INCLUDED_FROM_API_FILE to be defined +/* The MPU ports require MPU_WRAPPERS_INCLUDED_FROM_API_FILE to be defined * for the header files above, but not in this file, in order to generate the * correct privileged Vs unprivileged linkage and placement. */ -#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE /*lint !e961 !e750 !e9021. */ +#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE /* Constants used with the cRxLock and cTxLock structure members. */ @@ -89,7 +88,11 @@ typedef struct SemaphoreData * performed just because a higher priority task has been woken. */ #define queueYIELD_IF_USING_PREEMPTION() #else - #define queueYIELD_IF_USING_PREEMPTION() portYIELD_WITHIN_API() + #if ( configNUMBER_OF_CORES == 1 ) + #define queueYIELD_IF_USING_PREEMPTION() portYIELD_WITHIN_API() + #else /* #if ( configNUMBER_OF_CORES == 1 ) */ + #define queueYIELD_IF_USING_PREEMPTION() vTaskYieldWithinAPI() + #endif /* #if ( configNUMBER_OF_CORES == 1 ) */ #endif /* @@ -149,7 +152,7 @@ typedef xQUEUE Queue_t; * more user friendly. */ typedef struct QUEUE_REGISTRY_ITEM { - const char * pcQueueName; /*lint !e971 Unqualified char types are allowed for strings and single characters only. */ + const char * pcQueueName; QueueHandle_t xHandle; } xQueueRegistryItem; @@ -161,6 +164,10 @@ typedef xQUEUE Queue_t; /* The queue registry is simply an array of QueueRegistryItem_t structures. * The pcQueueName member of a structure being NULL is indicative of the * array position being vacant. */ + +/* MISRA Ref 8.4.2 [Declaration shall be visible] */ +/* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-84 */ +/* coverity[misra_c_2012_rule_8_4_violation] */ PRIVILEGED_DATA QueueRegistryItem_t xQueueRegistry[ configQUEUE_REGISTRY_SIZE ]; #endif /* configQUEUE_REGISTRY_SIZE */ @@ -299,6 +306,8 @@ BaseType_t xQueueGenericReset( QueueHandle_t xQueue, BaseType_t xReturn = pdPASS; Queue_t * const pxQueue = xQueue; + traceENTER_xQueueGenericReset( xQueue, xNewQueue ); + configASSERT( pxQueue ); if( ( pxQueue != NULL ) && @@ -308,10 +317,10 @@ BaseType_t xQueueGenericReset( QueueHandle_t xQueue, { taskENTER_CRITICAL(); { - pxQueue->u.xQueue.pcTail = pxQueue->pcHead + ( pxQueue->uxLength * pxQueue->uxItemSize ); /*lint !e9016 Pointer arithmetic allowed on char types, especially when it assists conveying intent. */ + pxQueue->u.xQueue.pcTail = pxQueue->pcHead + ( pxQueue->uxLength * pxQueue->uxItemSize ); pxQueue->uxMessagesWaiting = ( UBaseType_t ) 0U; pxQueue->pcWriteTo = pxQueue->pcHead; - pxQueue->u.xQueue.pcReadFrom = pxQueue->pcHead + ( ( pxQueue->uxLength - 1U ) * pxQueue->uxItemSize ); /*lint !e9016 Pointer arithmetic allowed on char types, especially when it assists conveying intent. */ + pxQueue->u.xQueue.pcReadFrom = pxQueue->pcHead + ( ( pxQueue->uxLength - 1U ) * pxQueue->uxItemSize ); pxQueue->cRxLock = queueUNLOCKED; pxQueue->cTxLock = queueUNLOCKED; @@ -356,6 +365,8 @@ BaseType_t xQueueGenericReset( QueueHandle_t xQueue, /* A value is returned for calling semantic consistency with previous * versions. */ + traceRETURN_xQueueGenericReset( xReturn ); + return xReturn; } /*-----------------------------------------------------------*/ @@ -370,6 +381,8 @@ BaseType_t xQueueGenericReset( QueueHandle_t xQueue, { Queue_t * pxNewQueue = NULL; + traceENTER_xQueueGenericCreateStatic( uxQueueLength, uxItemSize, pucQueueStorage, pxStaticQueue, ucQueueType ); + /* The StaticQueue_t structure and the queue storage area must be * supplied. */ configASSERT( pxStaticQueue ); @@ -379,8 +392,8 @@ BaseType_t xQueueGenericReset( QueueHandle_t xQueue, /* A queue storage area should be provided if the item size is not 0, and * should not be provided if the item size is 0. */ - ( !( ( pucQueueStorage != NULL ) && ( uxItemSize == 0 ) ) ) && - ( !( ( pucQueueStorage == NULL ) && ( uxItemSize != 0 ) ) ) ) + ( !( ( pucQueueStorage != NULL ) && ( uxItemSize == 0U ) ) ) && + ( !( ( pucQueueStorage == NULL ) && ( uxItemSize != 0U ) ) ) ) { #if ( configASSERT_DEFINED == 1 ) { @@ -391,14 +404,17 @@ BaseType_t xQueueGenericReset( QueueHandle_t xQueue, /* This assertion cannot be branch covered in unit tests */ configASSERT( xSize == sizeof( Queue_t ) ); /* LCOV_EXCL_BR_LINE */ - ( void ) xSize; /* Keeps lint quiet when configASSERT() is not defined. */ + ( void ) xSize; /* Prevent unused variable warning when configASSERT() is not defined. */ } #endif /* configASSERT_DEFINED */ /* The address of a statically allocated queue was passed in, use it. * The address of a statically allocated storage area was also passed in * but is already set. */ - pxNewQueue = ( Queue_t * ) pxStaticQueue; /*lint !e740 !e9087 Unusual cast is ok as the structures are designed to have the same alignment, and the size is checked by an assert. */ + /* MISRA Ref 11.3.1 [Misaligned access] */ + /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-113 */ + /* coverity[misra_c_2012_rule_11_3_violation] */ + pxNewQueue = ( Queue_t * ) pxStaticQueue; #if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) { @@ -417,6 +433,8 @@ BaseType_t xQueueGenericReset( QueueHandle_t xQueue, mtCOVERAGE_TEST_MARKER(); } + traceRETURN_xQueueGenericCreateStatic( pxNewQueue ); + return pxNewQueue; } @@ -432,6 +450,8 @@ BaseType_t xQueueGenericReset( QueueHandle_t xQueue, BaseType_t xReturn; Queue_t * const pxQueue = xQueue; + traceENTER_xQueueGenericGetStaticBuffers( xQueue, ppucQueueStorage, ppxStaticQueue ); + configASSERT( pxQueue ); configASSERT( ppxStaticQueue ); @@ -445,6 +465,9 @@ BaseType_t xQueueGenericReset( QueueHandle_t xQueue, *ppucQueueStorage = ( uint8_t * ) pxQueue->pcHead; } + /* MISRA Ref 11.3.1 [Misaligned access] */ + /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-113 */ + /* coverity[misra_c_2012_rule_11_3_violation] */ *ppxStaticQueue = ( StaticQueue_t * ) pxQueue; xReturn = pdTRUE; } @@ -466,6 +489,8 @@ BaseType_t xQueueGenericReset( QueueHandle_t xQueue, } #endif /* configSUPPORT_DYNAMIC_ALLOCATION */ + traceRETURN_xQueueGenericGetStaticBuffers( xReturn ); + return xReturn; } @@ -482,34 +507,30 @@ BaseType_t xQueueGenericReset( QueueHandle_t xQueue, size_t xQueueSizeInBytes; uint8_t * pucQueueStorage; + traceENTER_xQueueGenericCreate( uxQueueLength, uxItemSize, ucQueueType ); + if( ( uxQueueLength > ( UBaseType_t ) 0 ) && /* Check for multiplication overflow. */ ( ( SIZE_MAX / uxQueueLength ) >= uxItemSize ) && /* Check for addition overflow. */ - ( ( SIZE_MAX - sizeof( Queue_t ) ) >= ( uxQueueLength * uxItemSize ) ) ) + ( ( UBaseType_t ) ( SIZE_MAX - sizeof( Queue_t ) ) >= ( uxQueueLength * uxItemSize ) ) ) { /* Allocate enough space to hold the maximum number of items that * can be in the queue at any time. It is valid for uxItemSize to be * zero in the case the queue is used as a semaphore. */ - xQueueSizeInBytes = ( size_t ) ( uxQueueLength * uxItemSize ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */ - - /* Allocate the queue and storage area. Justification for MISRA - * deviation as follows: pvPortMalloc() always ensures returned memory - * blocks are aligned per the requirements of the MCU stack. In this case - * pvPortMalloc() must return a pointer that is guaranteed to meet the - * alignment requirements of the Queue_t structure - which in this case - * is an int8_t *. Therefore, whenever the stack alignment requirements - * are greater than or equal to the pointer to char requirements the cast - * is safe. In other cases alignment requirements are not strict (one or - * two bytes). */ - pxNewQueue = ( Queue_t * ) pvPortMalloc( sizeof( Queue_t ) + xQueueSizeInBytes ); /*lint !e9087 !e9079 see comment above. */ + xQueueSizeInBytes = ( size_t ) ( ( size_t ) uxQueueLength * ( size_t ) uxItemSize ); + + /* MISRA Ref 11.5.1 [Malloc memory assignment] */ + /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-115 */ + /* coverity[misra_c_2012_rule_11_5_violation] */ + pxNewQueue = ( Queue_t * ) pvPortMalloc( sizeof( Queue_t ) + xQueueSizeInBytes ); if( pxNewQueue != NULL ) { /* Jump past the queue structure to find the location of the queue * storage area. */ pucQueueStorage = ( uint8_t * ) pxNewQueue; - pucQueueStorage += sizeof( Queue_t ); /*lint !e9016 Pointer arithmetic allowed on char types, especially when it assists conveying intent. */ + pucQueueStorage += sizeof( Queue_t ); #if ( configSUPPORT_STATIC_ALLOCATION == 1 ) { @@ -534,6 +555,8 @@ BaseType_t xQueueGenericReset( QueueHandle_t xQueue, mtCOVERAGE_TEST_MARKER(); } + traceRETURN_xQueueGenericCreate( pxNewQueue ); + return pxNewQueue; } @@ -623,9 +646,13 @@ static void prvInitialiseNewQueue( const UBaseType_t uxQueueLength, QueueHandle_t xNewQueue; const UBaseType_t uxMutexLength = ( UBaseType_t ) 1, uxMutexSize = ( UBaseType_t ) 0; + traceENTER_xQueueCreateMutex( ucQueueType ); + xNewQueue = xQueueGenericCreate( uxMutexLength, uxMutexSize, ucQueueType ); prvInitialiseMutex( ( Queue_t * ) xNewQueue ); + traceRETURN_xQueueCreateMutex( xNewQueue ); + return xNewQueue; } @@ -640,6 +667,8 @@ static void prvInitialiseNewQueue( const UBaseType_t uxQueueLength, QueueHandle_t xNewQueue; const UBaseType_t uxMutexLength = ( UBaseType_t ) 1, uxMutexSize = ( UBaseType_t ) 0; + traceENTER_xQueueCreateMutexStatic( ucQueueType, pxStaticQueue ); + /* Prevent compiler warnings about unused parameters if * configUSE_TRACE_FACILITY does not equal 1. */ ( void ) ucQueueType; @@ -647,6 +676,8 @@ static void prvInitialiseNewQueue( const UBaseType_t uxQueueLength, xNewQueue = xQueueGenericCreateStatic( uxMutexLength, uxMutexSize, NULL, pxStaticQueue, ucQueueType ); prvInitialiseMutex( ( Queue_t * ) xNewQueue ); + traceRETURN_xQueueCreateMutexStatic( xNewQueue ); + return xNewQueue; } @@ -660,6 +691,8 @@ static void prvInitialiseNewQueue( const UBaseType_t uxQueueLength, TaskHandle_t pxReturn; Queue_t * const pxSemaphore = ( Queue_t * ) xSemaphore; + traceENTER_xQueueGetMutexHolder( xSemaphore ); + configASSERT( xSemaphore ); /* This function is called by xSemaphoreGetMutexHolder(), and should not @@ -680,8 +713,10 @@ static void prvInitialiseNewQueue( const UBaseType_t uxQueueLength, } taskEXIT_CRITICAL(); + traceRETURN_xQueueGetMutexHolder( pxReturn ); + return pxReturn; - } /*lint !e818 xSemaphore cannot be a pointer to const because it is a typedef. */ + } #endif /* if ( ( configUSE_MUTEXES == 1 ) && ( INCLUDE_xSemaphoreGetMutexHolder == 1 ) ) */ /*-----------------------------------------------------------*/ @@ -692,6 +727,8 @@ static void prvInitialiseNewQueue( const UBaseType_t uxQueueLength, { TaskHandle_t pxReturn; + traceENTER_xQueueGetMutexHolderFromISR( xSemaphore ); + configASSERT( xSemaphore ); /* Mutexes cannot be used in interrupt service routines, so the mutex @@ -706,8 +743,10 @@ static void prvInitialiseNewQueue( const UBaseType_t uxQueueLength, pxReturn = NULL; } + traceRETURN_xQueueGetMutexHolderFromISR( pxReturn ); + return pxReturn; - } /*lint !e818 xSemaphore cannot be a pointer to const because it is a typedef. */ + } #endif /* if ( ( configUSE_MUTEXES == 1 ) && ( INCLUDE_xSemaphoreGetMutexHolder == 1 ) ) */ /*-----------------------------------------------------------*/ @@ -719,6 +758,8 @@ static void prvInitialiseNewQueue( const UBaseType_t uxQueueLength, BaseType_t xReturn; Queue_t * const pxMutex = ( Queue_t * ) xMutex; + traceENTER_xQueueGiveMutexRecursive( xMutex ); + configASSERT( pxMutex ); /* If this is the task that holds the mutex then xMutexHolder will not @@ -761,6 +802,8 @@ static void prvInitialiseNewQueue( const UBaseType_t uxQueueLength, traceGIVE_MUTEX_RECURSIVE_FAILED( pxMutex ); } + traceRETURN_xQueueGiveMutexRecursive( xReturn ); + return xReturn; } @@ -775,6 +818,8 @@ static void prvInitialiseNewQueue( const UBaseType_t uxQueueLength, BaseType_t xReturn; Queue_t * const pxMutex = ( Queue_t * ) xMutex; + traceENTER_xQueueTakeMutexRecursive( xMutex, xTicksToWait ); + configASSERT( pxMutex ); /* Comments regarding mutual exclusion as per those within @@ -804,6 +849,8 @@ static void prvInitialiseNewQueue( const UBaseType_t uxQueueLength, } } + traceRETURN_xQueueTakeMutexRecursive( xReturn ); + return xReturn; } @@ -818,7 +865,9 @@ static void prvInitialiseNewQueue( const UBaseType_t uxQueueLength, { QueueHandle_t xHandle = NULL; - if( ( uxMaxCount != 0 ) && + traceENTER_xQueueCreateCountingSemaphoreStatic( uxMaxCount, uxInitialCount, pxStaticQueue ); + + if( ( uxMaxCount != 0U ) && ( uxInitialCount <= uxMaxCount ) ) { xHandle = xQueueGenericCreateStatic( uxMaxCount, queueSEMAPHORE_QUEUE_ITEM_LENGTH, NULL, pxStaticQueue, queueQUEUE_TYPE_COUNTING_SEMAPHORE ); @@ -840,6 +889,8 @@ static void prvInitialiseNewQueue( const UBaseType_t uxQueueLength, mtCOVERAGE_TEST_MARKER(); } + traceRETURN_xQueueCreateCountingSemaphoreStatic( xHandle ); + return xHandle; } @@ -853,7 +904,9 @@ static void prvInitialiseNewQueue( const UBaseType_t uxQueueLength, { QueueHandle_t xHandle = NULL; - if( ( uxMaxCount != 0 ) && + traceENTER_xQueueCreateCountingSemaphore( uxMaxCount, uxInitialCount ); + + if( ( uxMaxCount != 0U ) && ( uxInitialCount <= uxMaxCount ) ) { xHandle = xQueueGenericCreate( uxMaxCount, queueSEMAPHORE_QUEUE_ITEM_LENGTH, queueQUEUE_TYPE_COUNTING_SEMAPHORE ); @@ -875,6 +928,8 @@ static void prvInitialiseNewQueue( const UBaseType_t uxQueueLength, mtCOVERAGE_TEST_MARKER(); } + traceRETURN_xQueueCreateCountingSemaphore( xHandle ); + return xHandle; } @@ -890,6 +945,8 @@ BaseType_t xQueueGenericSend( QueueHandle_t xQueue, TimeOut_t xTimeOut; Queue_t * const pxQueue = xQueue; + traceENTER_xQueueGenericSend( xQueue, pvItemToQueue, xTicksToWait, xCopyPosition ); + configASSERT( pxQueue ); configASSERT( !( ( pvItemToQueue == NULL ) && ( pxQueue->uxItemSize != ( UBaseType_t ) 0U ) ) ); configASSERT( !( ( xCopyPosition == queueOVERWRITE ) && ( pxQueue->uxLength != 1 ) ) ); @@ -899,9 +956,6 @@ BaseType_t xQueueGenericSend( QueueHandle_t xQueue, } #endif - /*lint -save -e904 This function relaxes the coding standard somewhat to - * allow return statements within the function itself. This is done in the - * interest of execution time efficiency. */ for( ; ; ) { taskENTER_CRITICAL(); @@ -1011,6 +1065,9 @@ BaseType_t xQueueGenericSend( QueueHandle_t xQueue, #endif /* configUSE_QUEUE_SETS */ taskEXIT_CRITICAL(); + + traceRETURN_xQueueGenericSend( pdPASS ); + return pdPASS; } else @@ -1024,6 +1081,8 @@ BaseType_t xQueueGenericSend( QueueHandle_t xQueue, /* Return to the original privilege level before exiting * the function. */ traceQUEUE_SEND_FAILED( pxQueue ); + traceRETURN_xQueueGenericSend( errQUEUE_FULL ); + return errQUEUE_FULL; } else if( xEntryTimeSet == pdFALSE ) @@ -1070,7 +1129,7 @@ BaseType_t xQueueGenericSend( QueueHandle_t xQueue, * is also a higher priority task in the pending ready list. */ if( xTaskResumeAll() == pdFALSE ) { - portYIELD_WITHIN_API(); + taskYIELD_WITHIN_API(); } } else @@ -1087,9 +1146,11 @@ BaseType_t xQueueGenericSend( QueueHandle_t xQueue, ( void ) xTaskResumeAll(); traceQUEUE_SEND_FAILED( pxQueue ); + traceRETURN_xQueueGenericSend( errQUEUE_FULL ); + return errQUEUE_FULL; } - } /*lint -restore */ + } } /*-----------------------------------------------------------*/ @@ -1102,6 +1163,8 @@ BaseType_t xQueueGenericSendFromISR( QueueHandle_t xQueue, UBaseType_t uxSavedInterruptStatus; Queue_t * const pxQueue = xQueue; + traceENTER_xQueueGenericSendFromISR( xQueue, pvItemToQueue, pxHigherPriorityTaskWoken, xCopyPosition ); + configASSERT( pxQueue ); configASSERT( !( ( pvItemToQueue == NULL ) && ( pxQueue->uxItemSize != ( UBaseType_t ) 0U ) ) ); configASSERT( !( ( xCopyPosition == queueOVERWRITE ) && ( pxQueue->uxLength != 1 ) ) ); @@ -1127,7 +1190,7 @@ BaseType_t xQueueGenericSendFromISR( QueueHandle_t xQueue, * read, instead return a flag to say whether a context switch is required or * not (i.e. has a task with a higher priority than us been woken by this * post). */ - uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR(); + uxSavedInterruptStatus = taskENTER_CRITICAL_FROM_ISR(); { if( ( pxQueue->uxMessagesWaiting < pxQueue->uxLength ) || ( xCopyPosition == queueOVERWRITE ) ) { @@ -1252,7 +1315,9 @@ BaseType_t xQueueGenericSendFromISR( QueueHandle_t xQueue, xReturn = errQUEUE_FULL; } } - portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus ); + taskEXIT_CRITICAL_FROM_ISR( uxSavedInterruptStatus ); + + traceRETURN_xQueueGenericSendFromISR( xReturn ); return xReturn; } @@ -1265,6 +1330,8 @@ BaseType_t xQueueGiveFromISR( QueueHandle_t xQueue, UBaseType_t uxSavedInterruptStatus; Queue_t * const pxQueue = xQueue; + traceENTER_xQueueGiveFromISR( xQueue, pxHigherPriorityTaskWoken ); + /* Similar to xQueueGenericSendFromISR() but used with semaphores where the * item size is 0. Don't directly wake a task that was blocked on a queue * read, instead return a flag to say whether a context switch is required or @@ -1298,7 +1365,7 @@ BaseType_t xQueueGiveFromISR( QueueHandle_t xQueue, * link: https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */ portASSERT_IF_INTERRUPT_PRIORITY_INVALID(); - uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR(); + uxSavedInterruptStatus = taskENTER_CRITICAL_FROM_ISR(); { const UBaseType_t uxMessagesWaiting = pxQueue->uxMessagesWaiting; @@ -1317,7 +1384,7 @@ BaseType_t xQueueGiveFromISR( QueueHandle_t xQueue, * can be assumed there is no mutex holder and no need to determine if * priority disinheritance is needed. Simply increase the count of * messages (semaphores) available. */ - pxQueue->uxMessagesWaiting = uxMessagesWaiting + ( UBaseType_t ) 1; + pxQueue->uxMessagesWaiting = ( UBaseType_t ) ( uxMessagesWaiting + ( UBaseType_t ) 1 ); /* The event list is not altered if the queue is locked. This will * be done when the queue is unlocked later. */ @@ -1418,7 +1485,9 @@ BaseType_t xQueueGiveFromISR( QueueHandle_t xQueue, xReturn = errQUEUE_FULL; } } - portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus ); + taskEXIT_CRITICAL_FROM_ISR( uxSavedInterruptStatus ); + + traceRETURN_xQueueGiveFromISR( xReturn ); return xReturn; } @@ -1432,6 +1501,8 @@ BaseType_t xQueueReceive( QueueHandle_t xQueue, TimeOut_t xTimeOut; Queue_t * const pxQueue = xQueue; + traceENTER_xQueueReceive( xQueue, pvBuffer, xTicksToWait ); + /* Check the pointer is not NULL. */ configASSERT( ( pxQueue ) ); @@ -1446,9 +1517,6 @@ BaseType_t xQueueReceive( QueueHandle_t xQueue, } #endif - /*lint -save -e904 This function relaxes the coding standard somewhat to - * allow return statements within the function itself. This is done in the - * interest of execution time efficiency. */ for( ; ; ) { taskENTER_CRITICAL(); @@ -1462,7 +1530,7 @@ BaseType_t xQueueReceive( QueueHandle_t xQueue, /* Data available, remove one item. */ prvCopyDataFromQueue( pxQueue, pvBuffer ); traceQUEUE_RECEIVE( pxQueue ); - pxQueue->uxMessagesWaiting = uxMessagesWaiting - ( UBaseType_t ) 1; + pxQueue->uxMessagesWaiting = ( UBaseType_t ) ( uxMessagesWaiting - ( UBaseType_t ) 1 ); /* There is now space in the queue, were any tasks waiting to * post to the queue? If so, unblock the highest priority waiting @@ -1484,6 +1552,9 @@ BaseType_t xQueueReceive( QueueHandle_t xQueue, } taskEXIT_CRITICAL(); + + traceRETURN_xQueueReceive( pdPASS ); + return pdPASS; } else @@ -1493,7 +1564,10 @@ BaseType_t xQueueReceive( QueueHandle_t xQueue, /* The queue was empty and no block time is specified (or * the block time has expired) so leave now. */ taskEXIT_CRITICAL(); + traceQUEUE_RECEIVE_FAILED( pxQueue ); + traceRETURN_xQueueReceive( errQUEUE_EMPTY ); + return errQUEUE_EMPTY; } else if( xEntryTimeSet == pdFALSE ) @@ -1531,7 +1605,7 @@ BaseType_t xQueueReceive( QueueHandle_t xQueue, if( xTaskResumeAll() == pdFALSE ) { - portYIELD_WITHIN_API(); + taskYIELD_WITHIN_API(); } else { @@ -1556,6 +1630,8 @@ BaseType_t xQueueReceive( QueueHandle_t xQueue, if( prvIsQueueEmpty( pxQueue ) != pdFALSE ) { traceQUEUE_RECEIVE_FAILED( pxQueue ); + traceRETURN_xQueueReceive( errQUEUE_EMPTY ); + return errQUEUE_EMPTY; } else @@ -1563,7 +1639,7 @@ BaseType_t xQueueReceive( QueueHandle_t xQueue, mtCOVERAGE_TEST_MARKER(); } } - } /*lint -restore */ + } } /*-----------------------------------------------------------*/ @@ -1578,6 +1654,8 @@ BaseType_t xQueueSemaphoreTake( QueueHandle_t xQueue, BaseType_t xInheritanceOccurred = pdFALSE; #endif + traceENTER_xQueueSemaphoreTake( xQueue, xTicksToWait ); + /* Check the queue pointer is not NULL. */ configASSERT( ( pxQueue ) ); @@ -1592,9 +1670,6 @@ BaseType_t xQueueSemaphoreTake( QueueHandle_t xQueue, } #endif - /*lint -save -e904 This function relaxes the coding standard somewhat to allow return - * statements within the function itself. This is done in the interest - * of execution time efficiency. */ for( ; ; ) { taskENTER_CRITICAL(); @@ -1611,7 +1686,7 @@ BaseType_t xQueueSemaphoreTake( QueueHandle_t xQueue, /* Semaphores are queues with a data size of zero and where the * messages waiting is the semaphore's count. Reduce the count. */ - pxQueue->uxMessagesWaiting = uxSemaphoreCount - ( UBaseType_t ) 1; + pxQueue->uxMessagesWaiting = ( UBaseType_t ) ( uxSemaphoreCount - ( UBaseType_t ) 1 ); #if ( configUSE_MUTEXES == 1 ) { @@ -1647,6 +1722,9 @@ BaseType_t xQueueSemaphoreTake( QueueHandle_t xQueue, } taskEXIT_CRITICAL(); + + traceRETURN_xQueueSemaphoreTake( pdPASS ); + return pdPASS; } else @@ -1656,7 +1734,10 @@ BaseType_t xQueueSemaphoreTake( QueueHandle_t xQueue, /* The semaphore count was 0 and no block time is specified * (or the block time has expired) so exit now. */ taskEXIT_CRITICAL(); + traceQUEUE_RECEIVE_FAILED( pxQueue ); + traceRETURN_xQueueSemaphoreTake( errQUEUE_EMPTY ); + return errQUEUE_EMPTY; } else if( xEntryTimeSet == pdFALSE ) @@ -1714,7 +1795,7 @@ BaseType_t xQueueSemaphoreTake( QueueHandle_t xQueue, if( xTaskResumeAll() == pdFALSE ) { - portYIELD_WITHIN_API(); + taskYIELD_WITHIN_API(); } else { @@ -1758,6 +1839,14 @@ BaseType_t xQueueSemaphoreTake( QueueHandle_t xQueue, * again, but only as low as the next highest priority * task that is waiting for the same mutex. */ uxHighestWaitingPriority = prvGetDisinheritPriorityAfterTimeout( pxQueue ); + + /* vTaskPriorityDisinheritAfterTimeout uses the uxHighestWaitingPriority + * parameter to index pxReadyTasksLists when adding the task holding + * mutex to the ready list for its new priority. Coverity thinks that + * it can result in out-of-bounds access which is not true because + * uxHighestWaitingPriority, as returned by prvGetDisinheritPriorityAfterTimeout, + * is capped at ( configMAX_PRIORITIES - 1 ). */ + /* coverity[overrun] */ vTaskPriorityDisinheritAfterTimeout( pxQueue->u.xSemaphore.xMutexHolder, uxHighestWaitingPriority ); } taskEXIT_CRITICAL(); @@ -1766,6 +1855,8 @@ BaseType_t xQueueSemaphoreTake( QueueHandle_t xQueue, #endif /* configUSE_MUTEXES */ traceQUEUE_RECEIVE_FAILED( pxQueue ); + traceRETURN_xQueueSemaphoreTake( errQUEUE_EMPTY ); + return errQUEUE_EMPTY; } else @@ -1773,7 +1864,7 @@ BaseType_t xQueueSemaphoreTake( QueueHandle_t xQueue, mtCOVERAGE_TEST_MARKER(); } } - } /*lint -restore */ + } } /*-----------------------------------------------------------*/ @@ -1786,6 +1877,8 @@ BaseType_t xQueuePeek( QueueHandle_t xQueue, int8_t * pcOriginalReadPosition; Queue_t * const pxQueue = xQueue; + traceENTER_xQueuePeek( xQueue, pvBuffer, xTicksToWait ); + /* Check the pointer is not NULL. */ configASSERT( ( pxQueue ) ); @@ -1800,9 +1893,6 @@ BaseType_t xQueuePeek( QueueHandle_t xQueue, } #endif - /*lint -save -e904 This function relaxes the coding standard somewhat to - * allow return statements within the function itself. This is done in the - * interest of execution time efficiency. */ for( ; ; ) { taskENTER_CRITICAL(); @@ -1844,6 +1934,9 @@ BaseType_t xQueuePeek( QueueHandle_t xQueue, } taskEXIT_CRITICAL(); + + traceRETURN_xQueuePeek( pdPASS ); + return pdPASS; } else @@ -1853,7 +1946,10 @@ BaseType_t xQueuePeek( QueueHandle_t xQueue, /* The queue was empty and no block time is specified (or * the block time has expired) so leave now. */ taskEXIT_CRITICAL(); + traceQUEUE_PEEK_FAILED( pxQueue ); + traceRETURN_xQueuePeek( errQUEUE_EMPTY ); + return errQUEUE_EMPTY; } else if( xEntryTimeSet == pdFALSE ) @@ -1892,7 +1988,7 @@ BaseType_t xQueuePeek( QueueHandle_t xQueue, if( xTaskResumeAll() == pdFALSE ) { - portYIELD_WITHIN_API(); + taskYIELD_WITHIN_API(); } else { @@ -1917,6 +2013,8 @@ BaseType_t xQueuePeek( QueueHandle_t xQueue, if( prvIsQueueEmpty( pxQueue ) != pdFALSE ) { traceQUEUE_PEEK_FAILED( pxQueue ); + traceRETURN_xQueuePeek( errQUEUE_EMPTY ); + return errQUEUE_EMPTY; } else @@ -1924,7 +2022,7 @@ BaseType_t xQueuePeek( QueueHandle_t xQueue, mtCOVERAGE_TEST_MARKER(); } } - } /*lint -restore */ + } } /*-----------------------------------------------------------*/ @@ -1936,6 +2034,8 @@ BaseType_t xQueueReceiveFromISR( QueueHandle_t xQueue, UBaseType_t uxSavedInterruptStatus; Queue_t * const pxQueue = xQueue; + traceENTER_xQueueReceiveFromISR( xQueue, pvBuffer, pxHigherPriorityTaskWoken ); + configASSERT( pxQueue ); configASSERT( !( ( pvBuffer == NULL ) && ( pxQueue->uxItemSize != ( UBaseType_t ) 0U ) ) ); @@ -1955,7 +2055,7 @@ BaseType_t xQueueReceiveFromISR( QueueHandle_t xQueue, * link: https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */ portASSERT_IF_INTERRUPT_PRIORITY_INVALID(); - uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR(); + uxSavedInterruptStatus = taskENTER_CRITICAL_FROM_ISR(); { const UBaseType_t uxMessagesWaiting = pxQueue->uxMessagesWaiting; @@ -1967,7 +2067,7 @@ BaseType_t xQueueReceiveFromISR( QueueHandle_t xQueue, traceQUEUE_RECEIVE_FROM_ISR( pxQueue ); prvCopyDataFromQueue( pxQueue, pvBuffer ); - pxQueue->uxMessagesWaiting = uxMessagesWaiting - ( UBaseType_t ) 1; + pxQueue->uxMessagesWaiting = ( UBaseType_t ) ( uxMessagesWaiting - ( UBaseType_t ) 1 ); /* If the queue is locked the event list will not be modified. * Instead update the lock count so the task that unlocks the queue @@ -2015,7 +2115,9 @@ BaseType_t xQueueReceiveFromISR( QueueHandle_t xQueue, traceQUEUE_RECEIVE_FROM_ISR_FAILED( pxQueue ); } } - portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus ); + taskEXIT_CRITICAL_FROM_ISR( uxSavedInterruptStatus ); + + traceRETURN_xQueueReceiveFromISR( xReturn ); return xReturn; } @@ -2029,6 +2131,8 @@ BaseType_t xQueuePeekFromISR( QueueHandle_t xQueue, int8_t * pcOriginalReadPosition; Queue_t * const pxQueue = xQueue; + traceENTER_xQueuePeekFromISR( xQueue, pvBuffer ); + configASSERT( pxQueue ); configASSERT( !( ( pvBuffer == NULL ) && ( pxQueue->uxItemSize != ( UBaseType_t ) 0U ) ) ); configASSERT( pxQueue->uxItemSize != 0 ); /* Can't peek a semaphore. */ @@ -2049,7 +2153,7 @@ BaseType_t xQueuePeekFromISR( QueueHandle_t xQueue, * link: https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */ portASSERT_IF_INTERRUPT_PRIORITY_INVALID(); - uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR(); + uxSavedInterruptStatus = taskENTER_CRITICAL_FROM_ISR(); { /* Cannot block in an ISR, so check there is data available. */ if( pxQueue->uxMessagesWaiting > ( UBaseType_t ) 0 ) @@ -2070,7 +2174,9 @@ BaseType_t xQueuePeekFromISR( QueueHandle_t xQueue, traceQUEUE_PEEK_FROM_ISR_FAILED( pxQueue ); } } - portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus ); + taskEXIT_CRITICAL_FROM_ISR( uxSavedInterruptStatus ); + + traceRETURN_xQueuePeekFromISR( xReturn ); return xReturn; } @@ -2080,6 +2186,8 @@ UBaseType_t uxQueueMessagesWaiting( const QueueHandle_t xQueue ) { UBaseType_t uxReturn; + traceENTER_uxQueueMessagesWaiting( xQueue ); + configASSERT( xQueue ); taskENTER_CRITICAL(); @@ -2088,8 +2196,10 @@ UBaseType_t uxQueueMessagesWaiting( const QueueHandle_t xQueue ) } taskEXIT_CRITICAL(); + traceRETURN_uxQueueMessagesWaiting( uxReturn ); + return uxReturn; -} /*lint !e818 Pointer cannot be declared const as xQueue is a typedef not pointer. */ +} /*-----------------------------------------------------------*/ UBaseType_t uxQueueSpacesAvailable( const QueueHandle_t xQueue ) @@ -2097,16 +2207,20 @@ UBaseType_t uxQueueSpacesAvailable( const QueueHandle_t xQueue ) UBaseType_t uxReturn; Queue_t * const pxQueue = xQueue; + traceENTER_uxQueueSpacesAvailable( xQueue ); + configASSERT( pxQueue ); taskENTER_CRITICAL(); { - uxReturn = pxQueue->uxLength - pxQueue->uxMessagesWaiting; + uxReturn = ( UBaseType_t ) ( pxQueue->uxLength - pxQueue->uxMessagesWaiting ); } taskEXIT_CRITICAL(); + traceRETURN_uxQueueSpacesAvailable( uxReturn ); + return uxReturn; -} /*lint !e818 Pointer cannot be declared const as xQueue is a typedef not pointer. */ +} /*-----------------------------------------------------------*/ UBaseType_t uxQueueMessagesWaitingFromISR( const QueueHandle_t xQueue ) @@ -2114,17 +2228,23 @@ UBaseType_t uxQueueMessagesWaitingFromISR( const QueueHandle_t xQueue ) UBaseType_t uxReturn; Queue_t * const pxQueue = xQueue; + traceENTER_uxQueueMessagesWaitingFromISR( xQueue ); + configASSERT( pxQueue ); uxReturn = pxQueue->uxMessagesWaiting; + traceRETURN_uxQueueMessagesWaitingFromISR( uxReturn ); + return uxReturn; -} /*lint !e818 Pointer cannot be declared const as xQueue is a typedef not pointer. */ +} /*-----------------------------------------------------------*/ void vQueueDelete( QueueHandle_t xQueue ) { Queue_t * const pxQueue = xQueue; + traceENTER_vQueueDelete( xQueue ); + configASSERT( pxQueue ); traceQUEUE_DELETE( pxQueue ); @@ -2160,6 +2280,8 @@ void vQueueDelete( QueueHandle_t xQueue ) ( void ) pxQueue; } #endif /* configSUPPORT_DYNAMIC_ALLOCATION */ + + traceRETURN_vQueueDelete(); } /*-----------------------------------------------------------*/ @@ -2167,6 +2289,10 @@ void vQueueDelete( QueueHandle_t xQueue ) UBaseType_t uxQueueGetQueueNumber( QueueHandle_t xQueue ) { + traceENTER_uxQueueGetQueueNumber( xQueue ); + + traceRETURN_uxQueueGetQueueNumber( ( ( Queue_t * ) xQueue )->uxQueueNumber ); + return ( ( Queue_t * ) xQueue )->uxQueueNumber; } @@ -2178,7 +2304,11 @@ void vQueueDelete( QueueHandle_t xQueue ) void vQueueSetQueueNumber( QueueHandle_t xQueue, UBaseType_t uxQueueNumber ) { + traceENTER_vQueueSetQueueNumber( xQueue, uxQueueNumber ); + ( ( Queue_t * ) xQueue )->uxQueueNumber = uxQueueNumber; + + traceRETURN_vQueueSetQueueNumber(); } #endif /* configUSE_TRACE_FACILITY */ @@ -2188,6 +2318,10 @@ void vQueueDelete( QueueHandle_t xQueue ) uint8_t ucQueueGetQueueType( QueueHandle_t xQueue ) { + traceENTER_ucQueueGetQueueType( xQueue ); + + traceRETURN_ucQueueGetQueueType( ( ( Queue_t * ) xQueue )->ucQueueType ); + return ( ( Queue_t * ) xQueue )->ucQueueType; } @@ -2196,12 +2330,20 @@ void vQueueDelete( QueueHandle_t xQueue ) UBaseType_t uxQueueGetQueueItemSize( QueueHandle_t xQueue ) /* PRIVILEGED_FUNCTION */ { + traceENTER_uxQueueGetQueueItemSize( xQueue ); + + traceRETURN_uxQueueGetQueueItemSize( ( ( Queue_t * ) xQueue )->uxItemSize ); + return ( ( Queue_t * ) xQueue )->uxItemSize; } /*-----------------------------------------------------------*/ UBaseType_t uxQueueGetQueueLength( QueueHandle_t xQueue ) /* PRIVILEGED_FUNCTION */ { + traceENTER_uxQueueGetQueueLength( xQueue ); + + traceRETURN_uxQueueGetQueueLength( ( ( Queue_t * ) xQueue )->uxLength ); + return ( ( Queue_t * ) xQueue )->uxLength; } /*-----------------------------------------------------------*/ @@ -2220,7 +2362,7 @@ UBaseType_t uxQueueGetQueueLength( QueueHandle_t xQueue ) /* PRIVILEGED_FUNCTION * mutex. */ if( listCURRENT_LIST_LENGTH( &( pxQueue->xTasksWaitingToReceive ) ) > 0U ) { - uxHighestPriorityOfWaitingTasks = ( UBaseType_t ) configMAX_PRIORITIES - ( UBaseType_t ) listGET_ITEM_VALUE_OF_HEAD_ENTRY( &( pxQueue->xTasksWaitingToReceive ) ); + uxHighestPriorityOfWaitingTasks = ( UBaseType_t ) ( ( UBaseType_t ) configMAX_PRIORITIES - ( UBaseType_t ) listGET_ITEM_VALUE_OF_HEAD_ENTRY( &( pxQueue->xTasksWaitingToReceive ) ) ); } else { @@ -2263,10 +2405,10 @@ static BaseType_t prvCopyDataToQueue( Queue_t * const pxQueue, } else if( xPosition == queueSEND_TO_BACK ) { - ( void ) memcpy( ( void * ) pxQueue->pcWriteTo, pvItemToQueue, ( size_t ) pxQueue->uxItemSize ); /*lint !e961 !e418 !e9087 MISRA exception as the casts are only redundant for some ports, plus previous logic ensures a null pointer can only be passed to memcpy() if the copy size is 0. Cast to void required by function signature and safe as no alignment requirement and copy length specified in bytes. */ - pxQueue->pcWriteTo += pxQueue->uxItemSize; /*lint !e9016 Pointer arithmetic on char types ok, especially in this use case where it is the clearest way of conveying intent. */ + ( void ) memcpy( ( void * ) pxQueue->pcWriteTo, pvItemToQueue, ( size_t ) pxQueue->uxItemSize ); + pxQueue->pcWriteTo += pxQueue->uxItemSize; - if( pxQueue->pcWriteTo >= pxQueue->u.xQueue.pcTail ) /*lint !e946 MISRA exception justified as comparison of pointers is the cleanest solution. */ + if( pxQueue->pcWriteTo >= pxQueue->u.xQueue.pcTail ) { pxQueue->pcWriteTo = pxQueue->pcHead; } @@ -2277,10 +2419,10 @@ static BaseType_t prvCopyDataToQueue( Queue_t * const pxQueue, } else { - ( void ) memcpy( ( void * ) pxQueue->u.xQueue.pcReadFrom, pvItemToQueue, ( size_t ) pxQueue->uxItemSize ); /*lint !e961 !e9087 !e418 MISRA exception as the casts are only redundant for some ports. Cast to void required by function signature and safe as no alignment requirement and copy length specified in bytes. Assert checks null pointer only used when length is 0. */ + ( void ) memcpy( ( void * ) pxQueue->u.xQueue.pcReadFrom, pvItemToQueue, ( size_t ) pxQueue->uxItemSize ); pxQueue->u.xQueue.pcReadFrom -= pxQueue->uxItemSize; - if( pxQueue->u.xQueue.pcReadFrom < pxQueue->pcHead ) /*lint !e946 MISRA exception justified as comparison of pointers is the cleanest solution. */ + if( pxQueue->u.xQueue.pcReadFrom < pxQueue->pcHead ) { pxQueue->u.xQueue.pcReadFrom = ( pxQueue->u.xQueue.pcTail - pxQueue->uxItemSize ); } @@ -2310,7 +2452,7 @@ static BaseType_t prvCopyDataToQueue( Queue_t * const pxQueue, } } - pxQueue->uxMessagesWaiting = uxMessagesWaiting + ( UBaseType_t ) 1; + pxQueue->uxMessagesWaiting = ( UBaseType_t ) ( uxMessagesWaiting + ( UBaseType_t ) 1 ); return xReturn; } @@ -2321,9 +2463,9 @@ static void prvCopyDataFromQueue( Queue_t * const pxQueue, { if( pxQueue->uxItemSize != ( UBaseType_t ) 0 ) { - pxQueue->u.xQueue.pcReadFrom += pxQueue->uxItemSize; /*lint !e9016 Pointer arithmetic on char types ok, especially in this use case where it is the clearest way of conveying intent. */ + pxQueue->u.xQueue.pcReadFrom += pxQueue->uxItemSize; - if( pxQueue->u.xQueue.pcReadFrom >= pxQueue->u.xQueue.pcTail ) /*lint !e946 MISRA exception justified as use of the relational operator is the cleanest solutions. */ + if( pxQueue->u.xQueue.pcReadFrom >= pxQueue->u.xQueue.pcTail ) { pxQueue->u.xQueue.pcReadFrom = pxQueue->pcHead; } @@ -2332,7 +2474,7 @@ static void prvCopyDataFromQueue( Queue_t * const pxQueue, mtCOVERAGE_TEST_MARKER(); } - ( void ) memcpy( ( void * ) pvBuffer, ( void * ) pxQueue->u.xQueue.pcReadFrom, ( size_t ) pxQueue->uxItemSize ); /*lint !e961 !e418 !e9087 MISRA exception as the casts are only redundant for some ports. Also previous logic ensures a null pointer can only be passed to memcpy() when the count is 0. Cast to void required by function signature and safe as no alignment requirement and copy length specified in bytes. */ + ( void ) memcpy( ( void * ) pvBuffer, ( void * ) pxQueue->u.xQueue.pcReadFrom, ( size_t ) pxQueue->uxItemSize ); } } /*-----------------------------------------------------------*/ @@ -2483,6 +2625,8 @@ BaseType_t xQueueIsQueueEmptyFromISR( const QueueHandle_t xQueue ) BaseType_t xReturn; Queue_t * const pxQueue = xQueue; + traceENTER_xQueueIsQueueEmptyFromISR( xQueue ); + configASSERT( pxQueue ); if( pxQueue->uxMessagesWaiting == ( UBaseType_t ) 0 ) @@ -2494,8 +2638,10 @@ BaseType_t xQueueIsQueueEmptyFromISR( const QueueHandle_t xQueue ) xReturn = pdFALSE; } + traceRETURN_xQueueIsQueueEmptyFromISR( xReturn ); + return xReturn; -} /*lint !e818 xQueue could not be pointer to const because it is a typedef. */ +} /*-----------------------------------------------------------*/ static BaseType_t prvIsQueueFull( const Queue_t * pxQueue ) @@ -2524,6 +2670,8 @@ BaseType_t xQueueIsQueueFullFromISR( const QueueHandle_t xQueue ) BaseType_t xReturn; Queue_t * const pxQueue = xQueue; + traceENTER_xQueueIsQueueFullFromISR( xQueue ); + configASSERT( pxQueue ); if( pxQueue->uxMessagesWaiting == pxQueue->uxLength ) @@ -2535,8 +2683,10 @@ BaseType_t xQueueIsQueueFullFromISR( const QueueHandle_t xQueue ) xReturn = pdFALSE; } + traceRETURN_xQueueIsQueueFullFromISR( xReturn ); + return xReturn; -} /*lint !e818 xQueue could not be pointer to const because it is a typedef. */ +} /*-----------------------------------------------------------*/ #if ( configUSE_CO_ROUTINES == 1 ) @@ -2548,6 +2698,8 @@ BaseType_t xQueueIsQueueFullFromISR( const QueueHandle_t xQueue ) BaseType_t xReturn; Queue_t * const pxQueue = xQueue; + traceENTER_xQueueCRSend( xQueue, pvItemToQueue, xTicksToWait ); + /* If the queue is already full we may have to block. A critical section * is required to prevent an interrupt removing something from the queue * between the check to see if the queue is full and blocking on the queue. */ @@ -2612,6 +2764,8 @@ BaseType_t xQueueIsQueueFullFromISR( const QueueHandle_t xQueue ) } portENABLE_INTERRUPTS(); + traceRETURN_xQueueCRSend( xReturn ); + return xReturn; } @@ -2627,6 +2781,8 @@ BaseType_t xQueueIsQueueFullFromISR( const QueueHandle_t xQueue ) BaseType_t xReturn; Queue_t * const pxQueue = xQueue; + traceENTER_xQueueCRReceive( xQueue, pvBuffer, xTicksToWait ); + /* If the queue is already empty we may have to block. A critical section * is required to prevent an interrupt adding something to the queue * between the check to see if the queue is empty and blocking on the queue. */ @@ -2706,6 +2862,8 @@ BaseType_t xQueueIsQueueFullFromISR( const QueueHandle_t xQueue ) } portENABLE_INTERRUPTS(); + traceRETURN_xQueueCRReceive( xReturn ); + return xReturn; } @@ -2720,6 +2878,8 @@ BaseType_t xQueueIsQueueFullFromISR( const QueueHandle_t xQueue ) { Queue_t * const pxQueue = xQueue; + traceENTER_xQueueCRSendFromISR( xQueue, pvItemToQueue, xCoRoutinePreviouslyWoken ); + /* Cannot block within an ISR so if there is no space on the queue then * exit without doing anything. */ if( pxQueue->uxMessagesWaiting < pxQueue->uxLength ) @@ -2756,6 +2916,8 @@ BaseType_t xQueueIsQueueFullFromISR( const QueueHandle_t xQueue ) mtCOVERAGE_TEST_MARKER(); } + traceRETURN_xQueueCRSendFromISR( xCoRoutinePreviouslyWoken ); + return xCoRoutinePreviouslyWoken; } @@ -2771,6 +2933,8 @@ BaseType_t xQueueIsQueueFullFromISR( const QueueHandle_t xQueue ) BaseType_t xReturn; Queue_t * const pxQueue = xQueue; + traceENTER_xQueueCRReceiveFromISR( xQueue, pvBuffer, pxCoRoutineWoken ); + /* We cannot block from an ISR, so check there is data available. If * not then just leave without doing anything. */ if( pxQueue->uxMessagesWaiting > ( UBaseType_t ) 0 ) @@ -2820,6 +2984,8 @@ BaseType_t xQueueIsQueueFullFromISR( const QueueHandle_t xQueue ) xReturn = pdFAIL; } + traceRETURN_xQueueCRReceiveFromISR( xReturn ); + return xReturn; } @@ -2829,11 +2995,13 @@ BaseType_t xQueueIsQueueFullFromISR( const QueueHandle_t xQueue ) #if ( configQUEUE_REGISTRY_SIZE > 0 ) void vQueueAddToRegistry( QueueHandle_t xQueue, - const char * pcQueueName ) /*lint !e971 Unqualified char types are allowed for strings and single characters only. */ + const char * pcQueueName ) { UBaseType_t ux; QueueRegistryItem_t * pxEntryToWrite = NULL; + traceENTER_vQueueAddToRegistry( xQueue, pcQueueName ); + configASSERT( xQueue ); if( pcQueueName != NULL ) @@ -2868,6 +3036,8 @@ BaseType_t xQueueIsQueueFullFromISR( const QueueHandle_t xQueue ) traceQUEUE_REGISTRY_ADD( xQueue, pcQueueName ); } + + traceRETURN_vQueueAddToRegistry(); } #endif /* configQUEUE_REGISTRY_SIZE */ @@ -2875,10 +3045,12 @@ BaseType_t xQueueIsQueueFullFromISR( const QueueHandle_t xQueue ) #if ( configQUEUE_REGISTRY_SIZE > 0 ) - const char * pcQueueGetName( QueueHandle_t xQueue ) /*lint !e971 Unqualified char types are allowed for strings and single characters only. */ + const char * pcQueueGetName( QueueHandle_t xQueue ) { UBaseType_t ux; - const char * pcReturn = NULL; /*lint !e971 Unqualified char types are allowed for strings and single characters only. */ + const char * pcReturn = NULL; + + traceENTER_pcQueueGetName( xQueue ); configASSERT( xQueue ); @@ -2898,8 +3070,10 @@ BaseType_t xQueueIsQueueFullFromISR( const QueueHandle_t xQueue ) } } + traceRETURN_pcQueueGetName( pcReturn ); + return pcReturn; - } /*lint !e818 xQueue cannot be a pointer to const because it is a typedef. */ + } #endif /* configQUEUE_REGISTRY_SIZE */ /*-----------------------------------------------------------*/ @@ -2910,6 +3084,8 @@ BaseType_t xQueueIsQueueFullFromISR( const QueueHandle_t xQueue ) { UBaseType_t ux; + traceENTER_vQueueUnregisterQueue( xQueue ); + configASSERT( xQueue ); /* See if the handle of the queue being unregistered in actually in the @@ -2932,7 +3108,9 @@ BaseType_t xQueueIsQueueFullFromISR( const QueueHandle_t xQueue ) mtCOVERAGE_TEST_MARKER(); } } - } /*lint !e818 xQueue could not be pointer to const because it is a typedef. */ + + traceRETURN_vQueueUnregisterQueue(); + } #endif /* configQUEUE_REGISTRY_SIZE */ /*-----------------------------------------------------------*/ @@ -2945,6 +3123,8 @@ BaseType_t xQueueIsQueueFullFromISR( const QueueHandle_t xQueue ) { Queue_t * const pxQueue = xQueue; + traceENTER_vQueueWaitForMessageRestricted( xQueue, xTicksToWait, xWaitIndefinitely ); + /* This function should not be called by application code hence the * 'Restricted' in its name. It is not part of the public API. It is * designed for use by kernel code, and has special calling requirements. @@ -2972,6 +3152,8 @@ BaseType_t xQueueIsQueueFullFromISR( const QueueHandle_t xQueue ) } prvUnlockQueue( pxQueue ); + + traceRETURN_vQueueWaitForMessageRestricted(); } #endif /* configUSE_TIMERS */ @@ -2983,8 +3165,12 @@ BaseType_t xQueueIsQueueFullFromISR( const QueueHandle_t xQueue ) { QueueSetHandle_t pxQueue; + traceENTER_xQueueCreateSet( uxEventQueueLength ); + pxQueue = xQueueGenericCreate( uxEventQueueLength, ( UBaseType_t ) sizeof( Queue_t * ), queueQUEUE_TYPE_SET ); + traceRETURN_xQueueCreateSet( pxQueue ); + return pxQueue; } @@ -2998,6 +3184,8 @@ BaseType_t xQueueIsQueueFullFromISR( const QueueHandle_t xQueue ) { BaseType_t xReturn; + traceENTER_xQueueAddToSet( xQueueOrSemaphore, xQueueSet ); + taskENTER_CRITICAL(); { if( ( ( Queue_t * ) xQueueOrSemaphore )->pxQueueSetContainer != NULL ) @@ -3019,6 +3207,8 @@ BaseType_t xQueueIsQueueFullFromISR( const QueueHandle_t xQueue ) } taskEXIT_CRITICAL(); + traceRETURN_xQueueAddToSet( xReturn ); + return xReturn; } @@ -3033,6 +3223,8 @@ BaseType_t xQueueIsQueueFullFromISR( const QueueHandle_t xQueue ) BaseType_t xReturn; Queue_t * const pxQueueOrSemaphore = ( Queue_t * ) xQueueOrSemaphore; + traceENTER_xQueueRemoveFromSet( xQueueOrSemaphore, xQueueSet ); + if( pxQueueOrSemaphore->pxQueueSetContainer != xQueueSet ) { /* The queue was not a member of the set. */ @@ -3056,8 +3248,10 @@ BaseType_t xQueueIsQueueFullFromISR( const QueueHandle_t xQueue ) xReturn = pdPASS; } + traceRETURN_xQueueRemoveFromSet( xReturn ); + return xReturn; - } /*lint !e818 xQueueSet could not be declared as pointing to const as it is a typedef. */ + } #endif /* configUSE_QUEUE_SETS */ /*-----------------------------------------------------------*/ @@ -3069,7 +3263,12 @@ BaseType_t xQueueIsQueueFullFromISR( const QueueHandle_t xQueue ) { QueueSetMemberHandle_t xReturn = NULL; - ( void ) xQueueReceive( ( QueueHandle_t ) xQueueSet, &xReturn, xTicksToWait ); /*lint !e961 Casting from one typedef to another is not redundant. */ + traceENTER_xQueueSelectFromSet( xQueueSet, xTicksToWait ); + + ( void ) xQueueReceive( ( QueueHandle_t ) xQueueSet, &xReturn, xTicksToWait ); + + traceRETURN_xQueueSelectFromSet( xReturn ); + return xReturn; } @@ -3082,7 +3281,12 @@ BaseType_t xQueueIsQueueFullFromISR( const QueueHandle_t xQueue ) { QueueSetMemberHandle_t xReturn = NULL; - ( void ) xQueueReceiveFromISR( ( QueueHandle_t ) xQueueSet, &xReturn, NULL ); /*lint !e961 Casting from one typedef to another is not redundant. */ + traceENTER_xQueueSelectFromSetFromISR( xQueueSet ); + + ( void ) xQueueReceiveFromISR( ( QueueHandle_t ) xQueueSet, &xReturn, NULL ); + + traceRETURN_xQueueSelectFromSetFromISR( xReturn ); + return xReturn; } diff --git a/Source/sbom.spdx b/Source/sbom.spdx index 7c37b2231..205463a51 100644 --- a/Source/sbom.spdx +++ b/Source/sbom.spdx @@ -2,1776 +2,1799 @@ SPDXVersion: SPDX-2.2 DataLicense: CC0-1.0 SPDXID: SPDXRef-DOCUMENT DocumentName: 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b/Source/stream_buffer.c index 53208acee..2f7a45950 100644 --- a/Source/stream_buffer.c +++ b/Source/stream_buffer.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -27,7 +27,6 @@ */ /* Standard includes. */ -#include #include /* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining @@ -48,29 +47,30 @@ #error INCLUDE_xTaskGetCurrentTaskHandle must be set to 1 to build stream_buffer.c #endif -/* Lint e961, e9021 and e750 are suppressed as a MISRA exception justified - * because the MPU ports require MPU_WRAPPERS_INCLUDED_FROM_API_FILE to be defined +/* The MPU ports require MPU_WRAPPERS_INCLUDED_FROM_API_FILE to be defined * for the header files above, but not in this file, in order to generate the * correct privileged Vs unprivileged linkage and placement. */ -#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE /*lint !e961 !e750 !e9021. */ +#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE /* If the user has not provided application specific Rx notification macros, * or #defined the notification macros away, then provide default implementations * that uses task notifications. */ -/*lint -save -e9026 Function like macros allowed and needed here so they can be overridden. */ #ifndef sbRECEIVE_COMPLETED - #define sbRECEIVE_COMPLETED( pxStreamBuffer ) \ - vTaskSuspendAll(); \ - { \ - if( ( pxStreamBuffer )->xTaskWaitingToSend != NULL ) \ - { \ - ( void ) xTaskNotify( ( pxStreamBuffer )->xTaskWaitingToSend, \ - ( uint32_t ) 0, \ - eNoAction ); \ - ( pxStreamBuffer )->xTaskWaitingToSend = NULL; \ - } \ - } \ - ( void ) xTaskResumeAll() + #define sbRECEIVE_COMPLETED( pxStreamBuffer ) \ + do \ + { \ + vTaskSuspendAll(); \ + { \ + if( ( pxStreamBuffer )->xTaskWaitingToSend != NULL ) \ + { \ + ( void ) xTaskNotify( ( pxStreamBuffer )->xTaskWaitingToSend, \ + ( uint32_t ) 0, \ + eNoAction ); \ + ( pxStreamBuffer )->xTaskWaitingToSend = NULL; \ + } \ + } \ + ( void ) xTaskResumeAll(); \ + } while( 0 ) #endif /* sbRECEIVE_COMPLETED */ /* If user has provided a per-instance receive complete callback, then @@ -98,7 +98,7 @@ do { \ UBaseType_t uxSavedInterruptStatus; \ \ - uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR(); \ + uxSavedInterruptStatus = taskENTER_CRITICAL_FROM_ISR(); \ { \ if( ( pxStreamBuffer )->xTaskWaitingToSend != NULL ) \ { \ @@ -109,7 +109,7 @@ ( pxStreamBuffer )->xTaskWaitingToSend = NULL; \ } \ } \ - portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus ); \ + taskEXIT_CRITICAL_FROM_ISR( uxSavedInterruptStatus ); \ } while( 0 ) #endif /* sbRECEIVE_COMPLETED_FROM_ISR */ @@ -154,16 +154,16 @@ * invoke the callback else use the send complete macro which is provided by default for all instances. */ #if ( configUSE_SB_COMPLETED_CALLBACK == 1 ) - #define prvSEND_COMPLETED( pxStreamBuffer ) \ - do { \ - if( ( pxStreamBuffer )->pxSendCompletedCallback != NULL ) \ - { \ - pxStreamBuffer->pxSendCompletedCallback( ( pxStreamBuffer ), pdFALSE, NULL ); \ - } \ - else \ - { \ - sbSEND_COMPLETED( ( pxStreamBuffer ) ); \ - } \ + #define prvSEND_COMPLETED( pxStreamBuffer ) \ + do { \ + if( ( pxStreamBuffer )->pxSendCompletedCallback != NULL ) \ + { \ + ( pxStreamBuffer )->pxSendCompletedCallback( ( pxStreamBuffer ), pdFALSE, NULL ); \ + } \ + else \ + { \ + sbSEND_COMPLETED( ( pxStreamBuffer ) ); \ + } \ } while( 0 ) #else /* if ( configUSE_SB_COMPLETED_CALLBACK == 1 ) */ #define prvSEND_COMPLETED( pxStreamBuffer ) sbSEND_COMPLETED( ( pxStreamBuffer ) ) @@ -175,7 +175,7 @@ do { \ UBaseType_t uxSavedInterruptStatus; \ \ - uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR(); \ + uxSavedInterruptStatus = taskENTER_CRITICAL_FROM_ISR(); \ { \ if( ( pxStreamBuffer )->xTaskWaitingToReceive != NULL ) \ { \ @@ -186,7 +186,7 @@ ( pxStreamBuffer )->xTaskWaitingToReceive = NULL; \ } \ } \ - portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus ); \ + taskEXIT_CRITICAL_FROM_ISR( uxSavedInterruptStatus ); \ } while( 0 ) #endif /* sbSEND_COMPLETE_FROM_ISR */ @@ -208,8 +208,6 @@ sbSEND_COMPLETE_FROM_ISR( ( pxStreamBuffer ), ( pxHigherPriorityTaskWoken ) ) #endif /* if ( configUSE_SB_COMPLETED_CALLBACK == 1 ) */ -/*lint -restore (9026) */ - /* The number of bytes used to hold the length of a message in the buffer. */ #define sbBYTES_TO_STORE_MESSAGE_LENGTH ( sizeof( configMESSAGE_BUFFER_LENGTH_TYPE ) ) @@ -220,7 +218,7 @@ /*-----------------------------------------------------------*/ /* Structure that hold state information on the buffer. */ -typedef struct StreamBufferDef_t /*lint !e9058 Style convention uses tag. */ +typedef struct StreamBufferDef_t { volatile size_t xTail; /* Index to the next item to read within the buffer. */ volatile size_t xHead; /* Index to the next item to write within the buffer. */ @@ -327,6 +325,8 @@ static void prvInitialiseNewStreamBuffer( StreamBuffer_t * const pxStreamBuffer, void * pvAllocatedMemory; uint8_t ucFlags; + traceENTER_xStreamBufferGenericCreate( xBufferSizeBytes, xTriggerLevelBytes, xIsMessageBuffer, pxSendCompletedCallback, pxReceiveCompletedCallback ); + /* In case the stream buffer is going to be used as a message buffer * (that is, it will hold discrete messages with a little meta data that * says how big the next message is) check the buffer will be large enough @@ -361,7 +361,7 @@ static void prvInitialiseNewStreamBuffer( StreamBuffer_t * const pxStreamBuffer, * this is a quirk of the implementation that means otherwise the free * space would be reported as one byte smaller than would be logically * expected. */ - if( xBufferSizeBytes < ( xBufferSizeBytes + 1 + sizeof( StreamBuffer_t ) ) ) + if( xBufferSizeBytes < ( xBufferSizeBytes + 1U + sizeof( StreamBuffer_t ) ) ) { xBufferSizeBytes++; pvAllocatedMemory = pvPortMalloc( xBufferSizeBytes + sizeof( StreamBuffer_t ) ); @@ -373,8 +373,14 @@ static void prvInitialiseNewStreamBuffer( StreamBuffer_t * const pxStreamBuffer, if( pvAllocatedMemory != NULL ) { - prvInitialiseNewStreamBuffer( ( StreamBuffer_t * ) pvAllocatedMemory, /* Structure at the start of the allocated memory. */ /*lint !e9087 Safe cast as allocated memory is aligned. */ /*lint !e826 Area is not too small and alignment is guaranteed provided malloc() behaves as expected and returns aligned buffer. */ - ( ( uint8_t * ) pvAllocatedMemory ) + sizeof( StreamBuffer_t ), /* Storage area follows. */ /*lint !e9016 Indexing past structure valid for uint8_t pointer, also storage area has no alignment requirement. */ + /* MISRA Ref 11.5.1 [Malloc memory assignment] */ + /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-115 */ + /* coverity[misra_c_2012_rule_11_5_violation] */ + prvInitialiseNewStreamBuffer( ( StreamBuffer_t * ) pvAllocatedMemory, /* Structure at the start of the allocated memory. */ + /* MISRA Ref 11.5.1 [Malloc memory assignment] */ + /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-115 */ + /* coverity[misra_c_2012_rule_11_5_violation] */ + ( ( uint8_t * ) pvAllocatedMemory ) + sizeof( StreamBuffer_t ), /* Storage area follows. */ xBufferSizeBytes, xTriggerLevelBytes, ucFlags, @@ -388,7 +394,12 @@ static void prvInitialiseNewStreamBuffer( StreamBuffer_t * const pxStreamBuffer, traceSTREAM_BUFFER_CREATE_FAILED( xIsMessageBuffer ); } - return ( StreamBufferHandle_t ) pvAllocatedMemory; /*lint !e9087 !e826 Safe cast as allocated memory is aligned. */ + traceRETURN_xStreamBufferGenericCreate( pvAllocatedMemory ); + + /* MISRA Ref 11.5.1 [Malloc memory assignment] */ + /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-115 */ + /* coverity[misra_c_2012_rule_11_5_violation] */ + return ( StreamBufferHandle_t ) pvAllocatedMemory; } #endif /* configSUPPORT_DYNAMIC_ALLOCATION */ /*-----------------------------------------------------------*/ @@ -403,10 +414,15 @@ static void prvInitialiseNewStreamBuffer( StreamBuffer_t * const pxStreamBuffer, StreamBufferCallbackFunction_t pxSendCompletedCallback, StreamBufferCallbackFunction_t pxReceiveCompletedCallback ) { - StreamBuffer_t * const pxStreamBuffer = ( StreamBuffer_t * ) pxStaticStreamBuffer; /*lint !e740 !e9087 Safe cast as StaticStreamBuffer_t is opaque Streambuffer_t. */ + /* MISRA Ref 11.3.1 [Misaligned access] */ + /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-113 */ + /* coverity[misra_c_2012_rule_11_3_violation] */ + StreamBuffer_t * const pxStreamBuffer = ( StreamBuffer_t * ) pxStaticStreamBuffer; StreamBufferHandle_t xReturn; uint8_t ucFlags; + traceENTER_xStreamBufferGenericCreateStatic( xBufferSizeBytes, xTriggerLevelBytes, xIsMessageBuffer, pucStreamBufferStorageArea, pxStaticStreamBuffer, pxSendCompletedCallback, pxReceiveCompletedCallback ); + configASSERT( pucStreamBufferStorageArea ); configASSERT( pxStaticStreamBuffer ); configASSERT( xTriggerLevelBytes <= xBufferSizeBytes ); @@ -418,10 +434,16 @@ static void prvInitialiseNewStreamBuffer( StreamBuffer_t * const pxStreamBuffer, xTriggerLevelBytes = ( size_t ) 1; } + /* In case the stream buffer is going to be used as a message buffer + * (that is, it will hold discrete messages with a little meta data that + * says how big the next message is) check the buffer will be large enough + * to hold at least one message. */ + if( xIsMessageBuffer != pdFALSE ) { /* Statically allocated message buffer. */ ucFlags = sbFLAGS_IS_MESSAGE_BUFFER | sbFLAGS_IS_STATICALLY_ALLOCATED; + configASSERT( xBufferSizeBytes > sbBYTES_TO_STORE_MESSAGE_LENGTH ); } else { @@ -429,12 +451,6 @@ static void prvInitialiseNewStreamBuffer( StreamBuffer_t * const pxStreamBuffer, ucFlags = sbFLAGS_IS_STATICALLY_ALLOCATED; } - /* In case the stream buffer is going to be used as a message buffer - * (that is, it will hold discrete messages with a little meta data that - * says how big the next message is) check the buffer will be large enough - * to hold at least one message. */ - configASSERT( xBufferSizeBytes > sbBYTES_TO_STORE_MESSAGE_LENGTH ); - #if ( configASSERT_DEFINED == 1 ) { /* Sanity check that the size of the structure used to declare a @@ -442,7 +458,7 @@ static void prvInitialiseNewStreamBuffer( StreamBuffer_t * const pxStreamBuffer, * message buffer structure. */ volatile size_t xSize = sizeof( StaticStreamBuffer_t ); configASSERT( xSize == sizeof( StreamBuffer_t ) ); - } /*lint !e529 xSize is referenced is configASSERT() is defined. */ + } #endif /* configASSERT_DEFINED */ if( ( pucStreamBufferStorageArea != NULL ) && ( pxStaticStreamBuffer != NULL ) ) @@ -461,7 +477,10 @@ static void prvInitialiseNewStreamBuffer( StreamBuffer_t * const pxStreamBuffer, traceSTREAM_BUFFER_CREATE( pxStreamBuffer, xIsMessageBuffer ); - xReturn = ( StreamBufferHandle_t ) pxStaticStreamBuffer; /*lint !e9087 Data hiding requires cast to opaque type. */ + /* MISRA Ref 11.3.1 [Misaligned access] */ + /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-113 */ + /* coverity[misra_c_2012_rule_11_3_violation] */ + xReturn = ( StreamBufferHandle_t ) pxStaticStreamBuffer; } else { @@ -469,6 +488,8 @@ static void prvInitialiseNewStreamBuffer( StreamBuffer_t * const pxStreamBuffer, traceSTREAM_BUFFER_CREATE_STATIC_FAILED( xReturn, xIsMessageBuffer ); } + traceRETURN_xStreamBufferGenericCreateStatic( xReturn ); + return xReturn; } #endif /* ( configSUPPORT_STATIC_ALLOCATION == 1 ) */ @@ -482,6 +503,8 @@ static void prvInitialiseNewStreamBuffer( StreamBuffer_t * const pxStreamBuffer, BaseType_t xReturn; StreamBuffer_t * const pxStreamBuffer = xStreamBuffer; + traceENTER_xStreamBufferGetStaticBuffers( xStreamBuffer, ppucStreamBufferStorageArea, ppxStaticStreamBuffer ); + configASSERT( pxStreamBuffer ); configASSERT( ppucStreamBufferStorageArea ); configASSERT( ppxStaticStreamBuffer ); @@ -489,6 +512,9 @@ static void prvInitialiseNewStreamBuffer( StreamBuffer_t * const pxStreamBuffer, if( ( pxStreamBuffer->ucFlags & sbFLAGS_IS_STATICALLY_ALLOCATED ) != ( uint8_t ) 0 ) { *ppucStreamBufferStorageArea = pxStreamBuffer->pucBuffer; + /* MISRA Ref 11.3.1 [Misaligned access] */ + /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-113 */ + /* coverity[misra_c_2012_rule_11_3_violation] */ *ppxStaticStreamBuffer = ( StaticStreamBuffer_t * ) pxStreamBuffer; xReturn = pdTRUE; } @@ -497,6 +523,8 @@ static void prvInitialiseNewStreamBuffer( StreamBuffer_t * const pxStreamBuffer, xReturn = pdFALSE; } + traceRETURN_xStreamBufferGetStaticBuffers( xReturn ); + return xReturn; } #endif /* configSUPPORT_STATIC_ALLOCATION */ @@ -506,6 +534,8 @@ void vStreamBufferDelete( StreamBufferHandle_t xStreamBuffer ) { StreamBuffer_t * pxStreamBuffer = xStreamBuffer; + traceENTER_vStreamBufferDelete( xStreamBuffer ); + configASSERT( pxStreamBuffer ); traceSTREAM_BUFFER_DELETE( xStreamBuffer ); @@ -516,7 +546,7 @@ void vStreamBufferDelete( StreamBufferHandle_t xStreamBuffer ) { /* Both the structure and the buffer were allocated using a single call * to pvPortMalloc(), hence only one call to vPortFree() is required. */ - vPortFree( ( void * ) pxStreamBuffer ); /*lint !e9087 Standard free() semantics require void *, plus pxStreamBuffer was allocated by pvPortMalloc(). */ + vPortFree( ( void * ) pxStreamBuffer ); } #else { @@ -532,6 +562,8 @@ void vStreamBufferDelete( StreamBufferHandle_t xStreamBuffer ) * freed - just scrub the structure so future use will assert. */ ( void ) memset( pxStreamBuffer, 0x00, sizeof( StreamBuffer_t ) ); } + + traceRETURN_vStreamBufferDelete(); } /*-----------------------------------------------------------*/ @@ -545,6 +577,8 @@ BaseType_t xStreamBufferReset( StreamBufferHandle_t xStreamBuffer ) UBaseType_t uxStreamBufferNumber; #endif + traceENTER_xStreamBufferReset( xStreamBuffer ); + configASSERT( pxStreamBuffer ); #if ( configUSE_TRACE_FACILITY == 1 ) @@ -588,6 +622,8 @@ BaseType_t xStreamBufferReset( StreamBufferHandle_t xStreamBuffer ) } taskEXIT_CRITICAL(); + traceRETURN_xStreamBufferReset( xReturn ); + return xReturn; } /*-----------------------------------------------------------*/ @@ -598,6 +634,8 @@ BaseType_t xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer, StreamBuffer_t * const pxStreamBuffer = xStreamBuffer; BaseType_t xReturn; + traceENTER_xStreamBufferSetTriggerLevel( xStreamBuffer, xTriggerLevel ); + configASSERT( pxStreamBuffer ); /* It is not valid for the trigger level to be 0. */ @@ -618,6 +656,8 @@ BaseType_t xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer, xReturn = pdFALSE; } + traceRETURN_xStreamBufferSetTriggerLevel( xReturn ); + return xReturn; } /*-----------------------------------------------------------*/ @@ -628,6 +668,8 @@ size_t xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer ) size_t xSpace; size_t xOriginalTail; + traceENTER_xStreamBufferSpacesAvailable( xStreamBuffer ); + configASSERT( pxStreamBuffer ); /* The code below reads xTail and then xHead. This is safe if the stream @@ -651,6 +693,8 @@ size_t xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer ) mtCOVERAGE_TEST_MARKER(); } + traceRETURN_xStreamBufferSpacesAvailable( xSpace ); + return xSpace; } /*-----------------------------------------------------------*/ @@ -660,9 +704,14 @@ size_t xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer ) const StreamBuffer_t * const pxStreamBuffer = xStreamBuffer; size_t xReturn; + traceENTER_xStreamBufferBytesAvailable( xStreamBuffer ); + configASSERT( pxStreamBuffer ); xReturn = prvBytesInBuffer( pxStreamBuffer ); + + traceRETURN_xStreamBufferBytesAvailable( xReturn ); + return xReturn; } /*-----------------------------------------------------------*/ @@ -678,6 +727,8 @@ size_t xStreamBufferSend( StreamBufferHandle_t xStreamBuffer, TimeOut_t xTimeOut; size_t xMaxReportedSpace = 0; + traceENTER_xStreamBufferSend( xStreamBuffer, pvTxData, xDataLengthBytes, xTicksToWait ); + configASSERT( pvTxData ); configASSERT( pxStreamBuffer ); @@ -794,6 +845,8 @@ size_t xStreamBufferSend( StreamBufferHandle_t xStreamBuffer, traceSTREAM_BUFFER_SEND_FAILED( xStreamBuffer ); } + traceRETURN_xStreamBufferSend( xReturn ); + return xReturn; } /*-----------------------------------------------------------*/ @@ -807,6 +860,8 @@ size_t xStreamBufferSendFromISR( StreamBufferHandle_t xStreamBuffer, size_t xReturn, xSpace; size_t xRequiredSpace = xDataLengthBytes; + traceENTER_xStreamBufferSendFromISR( xStreamBuffer, pvTxData, xDataLengthBytes, pxHigherPriorityTaskWoken ); + configASSERT( pvTxData ); configASSERT( pxStreamBuffer ); @@ -844,6 +899,7 @@ size_t xStreamBufferSendFromISR( StreamBufferHandle_t xStreamBuffer, } traceSTREAM_BUFFER_SEND_FROM_ISR( xStreamBuffer, xReturn ); + traceRETURN_xStreamBufferSendFromISR( xReturn ); return xReturn; } @@ -892,7 +948,10 @@ static size_t prvWriteMessageToBuffer( StreamBuffer_t * const pxStreamBuffer, if( xDataLengthBytes != ( size_t ) 0 ) { /* Write the data to the buffer. */ - pxStreamBuffer->xHead = prvWriteBytesToBuffer( pxStreamBuffer, ( const uint8_t * ) pvTxData, xDataLengthBytes, xNextHead ); /*lint !e9079 Storage buffer is implemented as uint8_t for ease of sizing, alignment and access. */ + /* MISRA Ref 11.5.5 [Void pointer assignment] */ + /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-115 */ + /* coverity[misra_c_2012_rule_11_5_violation] */ + pxStreamBuffer->xHead = prvWriteBytesToBuffer( pxStreamBuffer, ( const uint8_t * ) pvTxData, xDataLengthBytes, xNextHead ); } return xDataLengthBytes; @@ -907,6 +966,8 @@ size_t xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer, StreamBuffer_t * const pxStreamBuffer = xStreamBuffer; size_t xReceivedLength = 0, xBytesAvailable, xBytesToStoreMessageLength; + traceENTER_xStreamBufferReceive( xStreamBuffer, pvRxData, xBufferLengthBytes, xTicksToWait ); + configASSERT( pvRxData ); configASSERT( pxStreamBuffer ); @@ -999,6 +1060,8 @@ size_t xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer, mtCOVERAGE_TEST_MARKER(); } + traceRETURN_xStreamBufferReceive( xReceivedLength ); + return xReceivedLength; } /*-----------------------------------------------------------*/ @@ -1009,6 +1072,8 @@ size_t xStreamBufferNextMessageLengthBytes( StreamBufferHandle_t xStreamBuffer ) size_t xReturn, xBytesAvailable; configMESSAGE_BUFFER_LENGTH_TYPE xTempReturn; + traceENTER_xStreamBufferNextMessageLengthBytes( xStreamBuffer ); + configASSERT( pxStreamBuffer ); /* Ensure the stream buffer is being used as a message buffer. */ @@ -1039,6 +1104,8 @@ size_t xStreamBufferNextMessageLengthBytes( StreamBufferHandle_t xStreamBuffer ) xReturn = 0; } + traceRETURN_xStreamBufferNextMessageLengthBytes( xReturn ); + return xReturn; } /*-----------------------------------------------------------*/ @@ -1051,6 +1118,8 @@ size_t xStreamBufferReceiveFromISR( StreamBufferHandle_t xStreamBuffer, StreamBuffer_t * const pxStreamBuffer = xStreamBuffer; size_t xReceivedLength = 0, xBytesAvailable, xBytesToStoreMessageLength; + traceENTER_xStreamBufferReceiveFromISR( xStreamBuffer, pvRxData, xBufferLengthBytes, pxHigherPriorityTaskWoken ); + configASSERT( pvRxData ); configASSERT( pxStreamBuffer ); @@ -1095,6 +1164,7 @@ size_t xStreamBufferReceiveFromISR( StreamBufferHandle_t xStreamBuffer, } traceSTREAM_BUFFER_RECEIVE_FROM_ISR( xStreamBuffer, xReceivedLength ); + traceRETURN_xStreamBufferReceiveFromISR( xReceivedLength ); return xReceivedLength; } @@ -1145,7 +1215,10 @@ static size_t prvReadMessageFromBuffer( StreamBuffer_t * pxStreamBuffer, if( xCount != ( size_t ) 0 ) { /* Read the actual data and update the tail to mark the data as officially consumed. */ - pxStreamBuffer->xTail = prvReadBytesFromBuffer( pxStreamBuffer, ( uint8_t * ) pvRxData, xCount, xNextTail ); /*lint !e9079 Data storage area is implemented as uint8_t array for ease of sizing, indexing and alignment. */ + /* MISRA Ref 11.5.5 [Void pointer assignment] */ + /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-115 */ + /* coverity[misra_c_2012_rule_11_5_violation] */ + pxStreamBuffer->xTail = prvReadBytesFromBuffer( pxStreamBuffer, ( uint8_t * ) pvRxData, xCount, xNextTail ); } return xCount; @@ -1158,6 +1231,8 @@ BaseType_t xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer ) BaseType_t xReturn; size_t xTail; + traceENTER_xStreamBufferIsEmpty( xStreamBuffer ); + configASSERT( pxStreamBuffer ); /* True if no bytes are available. */ @@ -1172,6 +1247,8 @@ BaseType_t xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer ) xReturn = pdFALSE; } + traceRETURN_xStreamBufferIsEmpty( xReturn ); + return xReturn; } /*-----------------------------------------------------------*/ @@ -1182,6 +1259,8 @@ BaseType_t xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer ) size_t xBytesToStoreMessageLength; const StreamBuffer_t * const pxStreamBuffer = xStreamBuffer; + traceENTER_xStreamBufferIsFull( xStreamBuffer ); + configASSERT( pxStreamBuffer ); /* This generic version of the receive function is used by both message @@ -1207,6 +1286,8 @@ BaseType_t xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer ) xReturn = pdFALSE; } + traceRETURN_xStreamBufferIsFull( xReturn ); + return xReturn; } /*-----------------------------------------------------------*/ @@ -1218,9 +1299,11 @@ BaseType_t xStreamBufferSendCompletedFromISR( StreamBufferHandle_t xStreamBuffer BaseType_t xReturn; UBaseType_t uxSavedInterruptStatus; + traceENTER_xStreamBufferSendCompletedFromISR( xStreamBuffer, pxHigherPriorityTaskWoken ); + configASSERT( pxStreamBuffer ); - uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR(); + uxSavedInterruptStatus = taskENTER_CRITICAL_FROM_ISR(); { if( ( pxStreamBuffer )->xTaskWaitingToReceive != NULL ) { @@ -1236,7 +1319,9 @@ BaseType_t xStreamBufferSendCompletedFromISR( StreamBufferHandle_t xStreamBuffer xReturn = pdFALSE; } } - portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus ); + taskEXIT_CRITICAL_FROM_ISR( uxSavedInterruptStatus ); + + traceRETURN_xStreamBufferSendCompletedFromISR( xReturn ); return xReturn; } @@ -1249,9 +1334,11 @@ BaseType_t xStreamBufferReceiveCompletedFromISR( StreamBufferHandle_t xStreamBuf BaseType_t xReturn; UBaseType_t uxSavedInterruptStatus; + traceENTER_xStreamBufferReceiveCompletedFromISR( xStreamBuffer, pxHigherPriorityTaskWoken ); + configASSERT( pxStreamBuffer ); - uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR(); + uxSavedInterruptStatus = taskENTER_CRITICAL_FROM_ISR(); { if( ( pxStreamBuffer )->xTaskWaitingToSend != NULL ) { @@ -1267,7 +1354,9 @@ BaseType_t xStreamBufferReceiveCompletedFromISR( StreamBufferHandle_t xStreamBuf xReturn = pdFALSE; } } - portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus ); + taskEXIT_CRITICAL_FROM_ISR( uxSavedInterruptStatus ); + + traceRETURN_xStreamBufferReceiveCompletedFromISR( xReturn ); return xReturn; } @@ -1289,7 +1378,7 @@ static size_t prvWriteBytesToBuffer( StreamBuffer_t * const pxStreamBuffer, /* Write as many bytes as can be written in the first write. */ configASSERT( ( xHead + xFirstLength ) <= pxStreamBuffer->xLength ); - ( void ) memcpy( ( void * ) ( &( pxStreamBuffer->pucBuffer[ xHead ] ) ), ( const void * ) pucData, xFirstLength ); /*lint !e9087 memcpy() requires void *. */ + ( void ) memcpy( ( void * ) ( &( pxStreamBuffer->pucBuffer[ xHead ] ) ), ( const void * ) pucData, xFirstLength ); /* If the number of bytes written was less than the number that could be * written in the first write... */ @@ -1297,7 +1386,7 @@ static size_t prvWriteBytesToBuffer( StreamBuffer_t * const pxStreamBuffer, { /* ...then write the remaining bytes to the start of the buffer. */ configASSERT( ( xCount - xFirstLength ) <= pxStreamBuffer->xLength ); - ( void ) memcpy( ( void * ) pxStreamBuffer->pucBuffer, ( const void * ) &( pucData[ xFirstLength ] ), xCount - xFirstLength ); /*lint !e9087 memcpy() requires void *. */ + ( void ) memcpy( ( void * ) pxStreamBuffer->pucBuffer, ( const void * ) &( pucData[ xFirstLength ] ), xCount - xFirstLength ); } else { @@ -1337,14 +1426,14 @@ static size_t prvReadBytesFromBuffer( StreamBuffer_t * pxStreamBuffer, * read. Asserts check bounds of read and write. */ configASSERT( xFirstLength <= xCount ); configASSERT( ( xTail + xFirstLength ) <= pxStreamBuffer->xLength ); - ( void ) memcpy( ( void * ) pucData, ( const void * ) &( pxStreamBuffer->pucBuffer[ xTail ] ), xFirstLength ); /*lint !e9087 memcpy() requires void *. */ + ( void ) memcpy( ( void * ) pucData, ( const void * ) &( pxStreamBuffer->pucBuffer[ xTail ] ), xFirstLength ); /* If the total number of wanted bytes is greater than the number * that could be read in the first read... */ if( xCount > xFirstLength ) { /* ...then read the remaining bytes from the start of the buffer. */ - ( void ) memcpy( ( void * ) &( pucData[ xFirstLength ] ), ( void * ) ( pxStreamBuffer->pucBuffer ), xCount - xFirstLength ); /*lint !e9087 memcpy() requires void *. */ + ( void ) memcpy( ( void * ) &( pucData[ xFirstLength ] ), ( void * ) ( pxStreamBuffer->pucBuffer ), xCount - xFirstLength ); } else { @@ -1405,7 +1494,7 @@ static void prvInitialiseNewStreamBuffer( StreamBuffer_t * const pxStreamBuffer, } #endif - ( void ) memset( ( void * ) pxStreamBuffer, 0x00, sizeof( StreamBuffer_t ) ); /*lint !e9087 memset() requires void *. */ + ( void ) memset( ( void * ) pxStreamBuffer, 0x00, sizeof( StreamBuffer_t ) ); pxStreamBuffer->pucBuffer = pucBuffer; pxStreamBuffer->xLength = xBufferSizeBytes; pxStreamBuffer->xTriggerLevelBytes = xTriggerLevelBytes; @@ -1417,16 +1506,27 @@ static void prvInitialiseNewStreamBuffer( StreamBuffer_t * const pxStreamBuffer, } #else { + /* MISRA Ref 11.1.1 [Object type casting] */ + /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-111 */ + /* coverity[misra_c_2012_rule_11_1_violation] */ ( void ) pxSendCompletedCallback; + + /* MISRA Ref 11.1.1 [Object type casting] */ + /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-111 */ + /* coverity[misra_c_2012_rule_11_1_violation] */ ( void ) pxReceiveCompletedCallback; } - #endif + #endif /* if ( configUSE_SB_COMPLETED_CALLBACK == 1 ) */ } #if ( configUSE_TRACE_FACILITY == 1 ) UBaseType_t uxStreamBufferGetStreamBufferNumber( StreamBufferHandle_t xStreamBuffer ) { + traceENTER_uxStreamBufferGetStreamBufferNumber( xStreamBuffer ); + + traceRETURN_uxStreamBufferGetStreamBufferNumber( xStreamBuffer->uxStreamBufferNumber ); + return xStreamBuffer->uxStreamBufferNumber; } @@ -1438,7 +1538,11 @@ static void prvInitialiseNewStreamBuffer( StreamBuffer_t * const pxStreamBuffer, void vStreamBufferSetStreamBufferNumber( StreamBufferHandle_t xStreamBuffer, UBaseType_t uxStreamBufferNumber ) { + traceENTER_vStreamBufferSetStreamBufferNumber( xStreamBuffer, uxStreamBufferNumber ); + xStreamBuffer->uxStreamBufferNumber = uxStreamBufferNumber; + + traceRETURN_vStreamBufferSetStreamBufferNumber(); } #endif /* configUSE_TRACE_FACILITY */ @@ -1448,7 +1552,11 @@ static void prvInitialiseNewStreamBuffer( StreamBuffer_t * const pxStreamBuffer, uint8_t ucStreamBufferGetStreamBufferType( StreamBufferHandle_t xStreamBuffer ) { - return( xStreamBuffer->ucFlags & sbFLAGS_IS_MESSAGE_BUFFER ); + traceENTER_ucStreamBufferGetStreamBufferType( xStreamBuffer ); + + traceRETURN_ucStreamBufferGetStreamBufferType( ( uint8_t ) ( xStreamBuffer->ucFlags & sbFLAGS_IS_MESSAGE_BUFFER ) ); + + return( ( uint8_t ) ( xStreamBuffer->ucFlags & sbFLAGS_IS_MESSAGE_BUFFER ) ); } #endif /* configUSE_TRACE_FACILITY */ diff --git a/Source/tasks.c b/Source/tasks.c index afb70092e..ad3cbdc88 100644 --- a/Source/tasks.c +++ b/Source/tasks.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -41,11 +41,10 @@ #include "timers.h" #include "stack_macros.h" -/* Lint e9021, e961 and e750 are suppressed as a MISRA exception justified - * because the MPU ports require MPU_WRAPPERS_INCLUDED_FROM_API_FILE to be defined +/* The MPU ports require MPU_WRAPPERS_INCLUDED_FROM_API_FILE to be defined * for the header files above, but not in this file, in order to generate the * correct privileged Vs unprivileged linkage and placement. */ -#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE /*lint !e961 !e750 !e9021. */ +#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE /* Set configUSE_STATS_FORMATTING_FUNCTIONS to 2 to include the stats formatting * functions but without including stdio.h here. */ @@ -62,10 +61,45 @@ /* If the cooperative scheduler is being used then a yield should not be * performed just because a higher priority task has been woken. */ - #define taskYIELD_IF_USING_PREEMPTION() + #define taskYIELD_TASK_CORE_IF_USING_PREEMPTION( pxTCB ) + #define taskYIELD_ANY_CORE_IF_USING_PREEMPTION( pxTCB ) #else - #define taskYIELD_IF_USING_PREEMPTION() portYIELD_WITHIN_API() -#endif + + #if ( configNUMBER_OF_CORES == 1 ) + +/* This macro requests the running task pxTCB to yield. In single core + * scheduler, a running task always runs on core 0 and portYIELD_WITHIN_API() + * can be used to request the task running on core 0 to yield. Therefore, pxTCB + * is not used in this macro. */ + #define taskYIELD_TASK_CORE_IF_USING_PREEMPTION( pxTCB ) \ + do { \ + ( void ) ( pxTCB ); \ + portYIELD_WITHIN_API(); \ + } while( 0 ) + + #define taskYIELD_ANY_CORE_IF_USING_PREEMPTION( pxTCB ) \ + do { \ + if( pxCurrentTCB->uxPriority < ( pxTCB )->uxPriority ) \ + { \ + portYIELD_WITHIN_API(); \ + } \ + else \ + { \ + mtCOVERAGE_TEST_MARKER(); \ + } \ + } while( 0 ) + + #else /* if ( configNUMBER_OF_CORES == 1 ) */ + +/* Yield the core on which this task is running. */ + #define taskYIELD_TASK_CORE_IF_USING_PREEMPTION( pxTCB ) prvYieldCore( ( pxTCB )->xTaskRunState ) + +/* Yield for the task if a running task has priority lower than this task. */ + #define taskYIELD_ANY_CORE_IF_USING_PREEMPTION( pxTCB ) prvYieldForTask( pxTCB ) + + #endif /* #if ( configNUMBER_OF_CORES == 1 ) */ + +#endif /* if ( configUSE_PREEMPTION == 0 ) */ /* Values that can be assigned to the ucNotifyState member of the TCB. */ #define taskNOT_WAITING_NOTIFICATION ( ( uint8_t ) 0 ) /* Must be zero as it is the initialised value. */ @@ -133,7 +167,8 @@ /*-----------------------------------------------------------*/ - #define taskSELECT_HIGHEST_PRIORITY_TASK() \ + #if ( configNUMBER_OF_CORES == 1 ) + #define taskSELECT_HIGHEST_PRIORITY_TASK() \ do { \ UBaseType_t uxTopPriority = uxTopReadyPriority; \ \ @@ -149,6 +184,11 @@ listGET_OWNER_OF_NEXT_ENTRY( pxCurrentTCB, &( pxReadyTasksLists[ uxTopPriority ] ) ); \ uxTopReadyPriority = uxTopPriority; \ } while( 0 ) /* taskSELECT_HIGHEST_PRIORITY_TASK */ + #else /* if ( configNUMBER_OF_CORES == 1 ) */ + + #define taskSELECT_HIGHEST_PRIORITY_TASK( xCoreID ) prvSelectHighestPriorityTask( xCoreID ) + + #endif /* if ( configNUMBER_OF_CORES == 1 ) */ /*-----------------------------------------------------------*/ @@ -244,13 +284,65 @@ * responsibility of whichever module is using the value to ensure it gets set back * to its original value when it is released. */ #if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS ) - #define taskEVENT_LIST_ITEM_VALUE_IN_USE 0x8000U + #define taskEVENT_LIST_ITEM_VALUE_IN_USE ( ( uint16_t ) 0x8000U ) #elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS ) - #define taskEVENT_LIST_ITEM_VALUE_IN_USE 0x80000000UL + #define taskEVENT_LIST_ITEM_VALUE_IN_USE ( ( uint32_t ) 0x80000000UL ) #elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_64_BITS ) - #define taskEVENT_LIST_ITEM_VALUE_IN_USE 0x8000000000000000ULL + #define taskEVENT_LIST_ITEM_VALUE_IN_USE ( ( uint64_t ) 0x8000000000000000ULL ) +#endif + +/* Indicates that the task is not actively running on any core. */ +#define taskTASK_NOT_RUNNING ( ( BaseType_t ) ( -1 ) ) + +/* Indicates that the task is actively running but scheduled to yield. */ +#define taskTASK_SCHEDULED_TO_YIELD ( ( BaseType_t ) ( -2 ) ) + +/* Returns pdTRUE if the task is actively running and not scheduled to yield. */ +#if ( configNUMBER_OF_CORES == 1 ) + #define taskTASK_IS_RUNNING( pxTCB ) ( ( ( pxTCB ) == pxCurrentTCB ) ? ( pdTRUE ) : ( pdFALSE ) ) + #define taskTASK_IS_RUNNING_OR_SCHEDULED_TO_YIELD( pxTCB ) ( ( ( pxTCB ) == pxCurrentTCB ) ? ( pdTRUE ) : ( pdFALSE ) ) +#else + #define taskTASK_IS_RUNNING( pxTCB ) ( ( ( ( pxTCB )->xTaskRunState >= ( BaseType_t ) 0 ) && ( ( pxTCB )->xTaskRunState < ( BaseType_t ) configNUMBER_OF_CORES ) ) ? ( pdTRUE ) : ( pdFALSE ) ) + #define taskTASK_IS_RUNNING_OR_SCHEDULED_TO_YIELD( pxTCB ) ( ( ( pxTCB )->xTaskRunState != taskTASK_NOT_RUNNING ) ? ( pdTRUE ) : ( pdFALSE ) ) #endif +/* Indicates that the task is an Idle task. */ +#define taskATTRIBUTE_IS_IDLE ( UBaseType_t ) ( 1UL << 0UL ) + +#if ( ( configNUMBER_OF_CORES > 1 ) && ( portCRITICAL_NESTING_IN_TCB == 1 ) ) + #define portGET_CRITICAL_NESTING_COUNT() ( pxCurrentTCBs[ portGET_CORE_ID() ]->uxCriticalNesting ) + #define portSET_CRITICAL_NESTING_COUNT( x ) ( pxCurrentTCBs[ portGET_CORE_ID() ]->uxCriticalNesting = ( x ) ) + #define portINCREMENT_CRITICAL_NESTING_COUNT() ( pxCurrentTCBs[ portGET_CORE_ID() ]->uxCriticalNesting++ ) + #define portDECREMENT_CRITICAL_NESTING_COUNT() ( pxCurrentTCBs[ portGET_CORE_ID() ]->uxCriticalNesting-- ) +#endif /* #if ( ( configNUMBER_OF_CORES > 1 ) && ( portCRITICAL_NESTING_IN_TCB == 1 ) ) */ + +#define taskBITS_PER_BYTE ( ( size_t ) 8 ) + +#if ( configNUMBER_OF_CORES > 1 ) + +/* Yields the given core. This must be called from a critical section and xCoreID + * must be valid. This macro is not required in single core since there is only + * one core to yield. */ + #define prvYieldCore( xCoreID ) \ + do { \ + if( ( xCoreID ) == ( BaseType_t ) portGET_CORE_ID() ) \ + { \ + /* Pending a yield for this core since it is in the critical section. */ \ + xYieldPendings[ ( xCoreID ) ] = pdTRUE; \ + } \ + else \ + { \ + /* Request other core to yield if it is not requested before. */ \ + if( pxCurrentTCBs[ ( xCoreID ) ]->xTaskRunState != taskTASK_SCHEDULED_TO_YIELD ) \ + { \ + portYIELD_CORE( xCoreID ); \ + pxCurrentTCBs[ ( xCoreID ) ]->xTaskRunState = taskTASK_SCHEDULED_TO_YIELD; \ + } \ + } \ + } while( 0 ) +#endif /* #if ( configNUMBER_OF_CORES > 1 ) */ +/*-----------------------------------------------------------*/ + /* * Task control block. A task control block (TCB) is allocated for each task, * and stores task state information, including a pointer to the task's context @@ -264,11 +356,23 @@ typedef struct tskTaskControlBlock /* The old naming convention is used to xMPU_SETTINGS xMPUSettings; /**< The MPU settings are defined as part of the port layer. THIS MUST BE THE SECOND MEMBER OF THE TCB STRUCT. */ #endif + #if ( configUSE_CORE_AFFINITY == 1 ) && ( configNUMBER_OF_CORES > 1 ) + UBaseType_t uxCoreAffinityMask; /**< Used to link the task to certain cores. UBaseType_t must have greater than or equal to the number of bits as configNUMBER_OF_CORES. */ + #endif + ListItem_t xStateListItem; /**< The list that the state list item of a task is reference from denotes the state of that task (Ready, Blocked, Suspended ). */ ListItem_t xEventListItem; /**< Used to reference a task from an event list. */ UBaseType_t uxPriority; /**< The priority of the task. 0 is the lowest priority. */ StackType_t * pxStack; /**< Points to the start of the stack. */ - char pcTaskName[ configMAX_TASK_NAME_LEN ]; /**< Descriptive name given to the task when created. Facilitates debugging only. */ /*lint !e971 Unqualified char types are allowed for strings and single characters only. */ + #if ( configNUMBER_OF_CORES > 1 ) + volatile BaseType_t xTaskRunState; /**< Used to identify the core the task is running on, if the task is running. Otherwise, identifies the task's state - not running or yielding. */ + UBaseType_t uxTaskAttributes; /**< Task's attributes - currently used to identify the idle tasks. */ + #endif + char pcTaskName[ configMAX_TASK_NAME_LEN ]; /**< Descriptive name given to the task when created. Facilitates debugging only. */ + + #if ( configUSE_TASK_PREEMPTION_DISABLE == 1 ) + BaseType_t xPreemptionDisable; /**< Used to prevent the task from being preempted. */ + #endif #if ( ( portSTACK_GROWTH > 0 ) || ( configRECORD_STACK_HIGH_ADDRESS == 1 ) ) StackType_t * pxEndOfStack; /**< Points to the highest valid address for the stack. */ @@ -311,8 +415,8 @@ typedef struct tskTaskControlBlock /* The old naming convention is used to /* See the comments in FreeRTOS.h with the definition of * tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE. */ - #if ( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0 ) /*lint !e731 !e9029 Macro has been consolidated for readability reasons. */ - uint8_t ucStaticallyAllocated; /**< Set to pdTRUE if the task is a statically allocated to ensure no attempt is made to free the memory. */ + #if ( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0 ) + uint8_t ucStaticallyAllocated; /**< Set to pdTRUE if the task is a statically allocated to ensure no attempt is made to free the memory. */ #endif #if ( INCLUDE_xTaskAbortDelay == 1 ) @@ -328,9 +432,18 @@ typedef struct tskTaskControlBlock /* The old naming convention is used to * below to enable the use of older kernel aware debuggers. */ typedef tskTCB TCB_t; -/*lint -save -e956 A manual analysis and inspection has been used to determine - * which static variables must be declared volatile. */ -portDONT_DISCARD PRIVILEGED_DATA TCB_t * volatile pxCurrentTCB = NULL; +#if ( configNUMBER_OF_CORES == 1 ) + /* MISRA Ref 8.4.1 [Declaration shall be visible] */ + /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-84 */ + /* coverity[misra_c_2012_rule_8_4_violation] */ + portDONT_DISCARD PRIVILEGED_DATA TCB_t * volatile pxCurrentTCB = NULL; +#else + /* MISRA Ref 8.4.1 [Declaration shall be visible] */ + /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-84 */ + /* coverity[misra_c_2012_rule_8_4_violation] */ + portDONT_DISCARD PRIVILEGED_DATA TCB_t * volatile pxCurrentTCBs[ configNUMBER_OF_CORES ]; + #define pxCurrentTCB xTaskGetCurrentTaskHandle() +#endif /* Lists for ready and blocked tasks. -------------------- * xDelayedTaskList1 and xDelayedTaskList2 could be moved to function scope but @@ -368,16 +481,16 @@ PRIVILEGED_DATA static volatile TickType_t xTickCount = ( TickType_t ) configINI PRIVILEGED_DATA static volatile UBaseType_t uxTopReadyPriority = tskIDLE_PRIORITY; PRIVILEGED_DATA static volatile BaseType_t xSchedulerRunning = pdFALSE; PRIVILEGED_DATA static volatile TickType_t xPendedTicks = ( TickType_t ) 0U; -PRIVILEGED_DATA static volatile BaseType_t xYieldPending = pdFALSE; +PRIVILEGED_DATA static volatile BaseType_t xYieldPendings[ configNUMBER_OF_CORES ] = { pdFALSE }; PRIVILEGED_DATA static volatile BaseType_t xNumOfOverflows = ( BaseType_t ) 0; PRIVILEGED_DATA static UBaseType_t uxTaskNumber = ( UBaseType_t ) 0U; PRIVILEGED_DATA static volatile TickType_t xNextTaskUnblockTime = ( TickType_t ) 0U; /* Initialised to portMAX_DELAY before the scheduler starts. */ -PRIVILEGED_DATA static TaskHandle_t xIdleTaskHandle = NULL; /**< Holds the handle of the idle task. The idle task is created automatically when the scheduler is started. */ +PRIVILEGED_DATA static TaskHandle_t xIdleTaskHandles[ configNUMBER_OF_CORES ]; /**< Holds the handles of the idle tasks. The idle tasks are created automatically when the scheduler is started. */ /* Improve support for OpenOCD. The kernel tracks Ready tasks via priority lists. * For tracking the state of remote threads, OpenOCD uses uxTopUsedPriority * to determine the number of priority lists to read back from the remote target. */ -const volatile UBaseType_t uxTopUsedPriority = configMAX_PRIORITIES - 1U; +static const volatile UBaseType_t uxTopUsedPriority = configMAX_PRIORITIES - 1U; /* Context switches are held pending while the scheduler is suspended. Also, * interrupts must not manipulate the xStateListItem of a TCB, or any of the @@ -386,24 +499,57 @@ const volatile UBaseType_t uxTopUsedPriority = configMAX_PRIORITIES - 1U; * moves the task's event list item into the xPendingReadyList, ready for the * kernel to move the task from the pending ready list into the real ready list * when the scheduler is unsuspended. The pending ready list itself can only be - * accessed from a critical section. */ + * accessed from a critical section. + * + * Updates to uxSchedulerSuspended must be protected by both the task lock and the ISR lock + * and must not be done from an ISR. Reads must be protected by either lock and may be done + * from either an ISR or a task. */ PRIVILEGED_DATA static volatile UBaseType_t uxSchedulerSuspended = ( UBaseType_t ) 0U; #if ( configGENERATE_RUN_TIME_STATS == 1 ) /* Do not move these variables to function scope as doing so prevents the * code working with debuggers that need to remove the static qualifier. */ - PRIVILEGED_DATA static configRUN_TIME_COUNTER_TYPE ulTaskSwitchedInTime = 0UL; /**< Holds the value of a timer/counter the last time a task was switched in. */ - PRIVILEGED_DATA static volatile configRUN_TIME_COUNTER_TYPE ulTotalRunTime = 0UL; /**< Holds the total amount of execution time as defined by the run time counter clock. */ +PRIVILEGED_DATA static configRUN_TIME_COUNTER_TYPE ulTaskSwitchedInTime[ configNUMBER_OF_CORES ] = { 0U }; /**< Holds the value of a timer/counter the last time a task was switched in. */ +PRIVILEGED_DATA static volatile configRUN_TIME_COUNTER_TYPE ulTotalRunTime[ configNUMBER_OF_CORES ] = { 0U }; /**< Holds the total amount of execution time as defined by the run time counter clock. */ #endif -/*lint -restore */ - /*-----------------------------------------------------------*/ /* File private functions. --------------------------------*/ +/* + * Creates the idle tasks during scheduler start. + */ +static BaseType_t prvCreateIdleTasks( void ); + +#if ( configNUMBER_OF_CORES > 1 ) + +/* + * Checks to see if another task moved the current task out of the ready + * list while it was waiting to enter a critical section and yields, if so. + */ + static void prvCheckForRunStateChange( void ); +#endif /* #if ( configNUMBER_OF_CORES > 1 ) */ + +#if ( configNUMBER_OF_CORES > 1 ) + +/* + * Yields a core, or cores if multiple priorities are not allowed to run + * simultaneously, to allow the task pxTCB to run. + */ + static void prvYieldForTask( const TCB_t * pxTCB ); +#endif /* #if ( configNUMBER_OF_CORES > 1 ) */ + +#if ( configNUMBER_OF_CORES > 1 ) + +/* + * Selects the highest priority available task for the given core. + */ + static void prvSelectHighestPriorityTask( BaseType_t xCoreID ); +#endif /* #if ( configNUMBER_OF_CORES > 1 ) */ + /** * Utility task that simply returns pdTRUE if the task referenced by xTask is * currently in the Suspended state, or pdFALSE if the task referenced by xTask @@ -426,13 +572,21 @@ static void prvInitialiseTaskLists( void ) PRIVILEGED_FUNCTION; * The idle task is automatically created and added to the ready lists upon * creation of the first user task. * + * In the FreeRTOS SMP, configNUMBER_OF_CORES - 1 passive idle tasks are also + * created to ensure that each core has an idle task to run when no other + * task is available to run. + * * The portTASK_FUNCTION_PROTO() macro is used to allow port/compiler specific - * language extensions. The equivalent prototype for this function is: + * language extensions. The equivalent prototype for these functions are: * * void prvIdleTask( void *pvParameters ); + * void prvPassiveIdleTask( void *pvParameters ); * */ static portTASK_FUNCTION_PROTO( prvIdleTask, pvParameters ) PRIVILEGED_FUNCTION; +#if ( configNUMBER_OF_CORES > 1 ) + static portTASK_FUNCTION_PROTO( prvPassiveIdleTask, pvParameters ) PRIVILEGED_FUNCTION; +#endif /* * Utility to free all memory allocated by the scheduler to hold a TCB, @@ -536,7 +690,7 @@ static void prvResetNextTaskUnblockTime( void ) PRIVILEGED_FUNCTION; * dynamically to fill in the structure's members. */ static void prvInitialiseNewTask( TaskFunction_t pxTaskCode, - const char * const pcName, /*lint !e971 Unqualified char types are allowed for strings and single characters only. */ + const char * const pcName, const uint32_t ulStackDepth, void * const pvParameters, UBaseType_t uxPriority, @@ -550,6 +704,53 @@ static void prvInitialiseNewTask( TaskFunction_t pxTaskCode, */ static void prvAddNewTaskToReadyList( TCB_t * pxNewTCB ) PRIVILEGED_FUNCTION; +/* + * Create a task with static buffer for both TCB and stack. Returns a handle to + * the task if it is created successfully. Otherwise, returns NULL. + */ +#if ( configSUPPORT_STATIC_ALLOCATION == 1 ) + static TCB_t * prvCreateStaticTask( TaskFunction_t pxTaskCode, + const char * const pcName, + const uint32_t ulStackDepth, + void * const pvParameters, + UBaseType_t uxPriority, + StackType_t * const puxStackBuffer, + StaticTask_t * const pxTaskBuffer, + TaskHandle_t * const pxCreatedTask ) PRIVILEGED_FUNCTION; +#endif /* #if ( configSUPPORT_STATIC_ALLOCATION == 1 ) */ + +/* + * Create a restricted task with static buffer for both TCB and stack. Returns + * a handle to the task if it is created successfully. Otherwise, returns NULL. + */ +#if ( ( portUSING_MPU_WRAPPERS == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) ) + static TCB_t * prvCreateRestrictedStaticTask( const TaskParameters_t * const pxTaskDefinition, + TaskHandle_t * const pxCreatedTask ) PRIVILEGED_FUNCTION; +#endif /* #if ( ( portUSING_MPU_WRAPPERS == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) ) */ + +/* + * Create a restricted task with static buffer for task stack and allocated buffer + * for TCB. Returns a handle to the task if it is created successfully. Otherwise, + * returns NULL. + */ +#if ( ( portUSING_MPU_WRAPPERS == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) ) + static TCB_t * prvCreateRestrictedTask( const TaskParameters_t * const pxTaskDefinition, + TaskHandle_t * const pxCreatedTask ) PRIVILEGED_FUNCTION; +#endif /* #if ( ( portUSING_MPU_WRAPPERS == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) ) */ + +/* + * Create a task with allocated buffer for both TCB and stack. Returns a handle to + * the task if it is created successfully. Otherwise, returns NULL. + */ +#if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) + static TCB_t * prvCreateTask( TaskFunction_t pxTaskCode, + const char * const pcName, + const configSTACK_DEPTH_TYPE usStackDepth, + void * const pvParameters, + UBaseType_t uxPriority, + TaskHandle_t * const pxCreatedTask ) PRIVILEGED_FUNCTION; +#endif /* #if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) */ + /* * freertos_tasks_c_additions_init() should only be called if the user definable * macro FREERTOS_TASKS_C_ADDITIONS_INIT() is defined, as that is the only macro @@ -561,197 +762,888 @@ static void prvAddNewTaskToReadyList( TCB_t * pxNewTCB ) PRIVILEGED_FUNCTION; #endif -/*-----------------------------------------------------------*/ +#if ( configUSE_PASSIVE_IDLE_HOOK == 1 ) + extern void vApplicationPassiveIdleHook( void ); +#endif /* #if ( configUSE_PASSIVE_IDLE_HOOK == 1 ) */ -#if ( configSUPPORT_STATIC_ALLOCATION == 1 ) +#if ( ( configUSE_TRACE_FACILITY == 1 ) && ( configUSE_STATS_FORMATTING_FUNCTIONS > 0 ) ) - TaskHandle_t xTaskCreateStatic( TaskFunction_t pxTaskCode, - const char * const pcName, /*lint !e971 Unqualified char types are allowed for strings and single characters only. */ - const uint32_t ulStackDepth, - void * const pvParameters, - UBaseType_t uxPriority, - StackType_t * const puxStackBuffer, - StaticTask_t * const pxTaskBuffer ) +/* + * Convert the snprintf return value to the number of characters + * written. The following are the possible cases: + * + * 1. The buffer supplied to snprintf is large enough to hold the + * generated string. The return value in this case is the number + * of characters actually written, not counting the terminating + * null character. + * 2. The buffer supplied to snprintf is NOT large enough to hold + * the generated string. The return value in this case is the + * number of characters that would have been written if the + * buffer had been sufficiently large, not counting the + * terminating null character. + * 3. Encoding error. The return value in this case is a negative + * number. + * + * From 1 and 2 above ==> Only when the return value is non-negative + * and less than the supplied buffer length, the string has been + * completely written. + */ + static size_t prvSnprintfReturnValueToCharsWritten( int iSnprintfReturnValue, + size_t n ); + +#endif /* #if ( ( configUSE_TRACE_FACILITY == 1 ) && ( configUSE_STATS_FORMATTING_FUNCTIONS > 0 ) ) */ +/*-----------------------------------------------------------*/ + +#if ( configNUMBER_OF_CORES > 1 ) + static void prvCheckForRunStateChange( void ) { - TCB_t * pxNewTCB; - TaskHandle_t xReturn; + UBaseType_t uxPrevCriticalNesting; + const TCB_t * pxThisTCB; - configASSERT( puxStackBuffer != NULL ); - configASSERT( pxTaskBuffer != NULL ); + /* This must only be called from within a task. */ + portASSERT_IF_IN_ISR(); - #if ( configASSERT_DEFINED == 1 ) - { - /* Sanity check that the size of the structure used to declare a - * variable of type StaticTask_t equals the size of the real task - * structure. */ - volatile size_t xSize = sizeof( StaticTask_t ); - configASSERT( xSize == sizeof( TCB_t ) ); - ( void ) xSize; /* Prevent lint warning when configASSERT() is not used. */ - } - #endif /* configASSERT_DEFINED */ + /* This function is always called with interrupts disabled + * so this is safe. */ + pxThisTCB = pxCurrentTCBs[ portGET_CORE_ID() ]; - if( ( pxTaskBuffer != NULL ) && ( puxStackBuffer != NULL ) ) + while( pxThisTCB->xTaskRunState == taskTASK_SCHEDULED_TO_YIELD ) { - /* The memory used for the task's TCB and stack are passed into this - * function - use them. */ - pxNewTCB = ( TCB_t * ) pxTaskBuffer; /*lint !e740 !e9087 Unusual cast is ok as the structures are designed to have the same alignment, and the size is checked by an assert. */ - memset( ( void * ) pxNewTCB, 0x00, sizeof( TCB_t ) ); - pxNewTCB->pxStack = ( StackType_t * ) puxStackBuffer; + /* We are only here if we just entered a critical section + * or if we just suspended the scheduler, and another task + * has requested that we yield. + * + * This is slightly complicated since we need to save and restore + * the suspension and critical nesting counts, as well as release + * and reacquire the correct locks. And then, do it all over again + * if our state changed again during the reacquisition. */ + uxPrevCriticalNesting = portGET_CRITICAL_NESTING_COUNT(); - #if ( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0 ) /*lint !e731 !e9029 Macro has been consolidated for readability reasons. */ + if( uxPrevCriticalNesting > 0U ) { - /* Tasks can be created statically or dynamically, so note this - * task was created statically in case the task is later deleted. */ - pxNewTCB->ucStaticallyAllocated = tskSTATICALLY_ALLOCATED_STACK_AND_TCB; + portSET_CRITICAL_NESTING_COUNT( 0U ); + portRELEASE_ISR_LOCK(); + } + else + { + /* The scheduler is suspended. uxSchedulerSuspended is updated + * only when the task is not requested to yield. */ + mtCOVERAGE_TEST_MARKER(); } - #endif /* tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE */ - - prvInitialiseNewTask( pxTaskCode, pcName, ulStackDepth, pvParameters, uxPriority, &xReturn, pxNewTCB, NULL ); - prvAddNewTaskToReadyList( pxNewTCB ); - } - else - { - xReturn = NULL; - } - - return xReturn; - } - -#endif /* SUPPORT_STATIC_ALLOCATION */ -/*-----------------------------------------------------------*/ -#if ( ( portUSING_MPU_WRAPPERS == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) ) + portRELEASE_TASK_LOCK(); + portMEMORY_BARRIER(); + configASSERT( pxThisTCB->xTaskRunState == taskTASK_SCHEDULED_TO_YIELD ); - BaseType_t xTaskCreateRestrictedStatic( const TaskParameters_t * const pxTaskDefinition, - TaskHandle_t * pxCreatedTask ) - { - TCB_t * pxNewTCB; - BaseType_t xReturn = errCOULD_NOT_ALLOCATE_REQUIRED_MEMORY; + portENABLE_INTERRUPTS(); - configASSERT( pxTaskDefinition->puxStackBuffer != NULL ); - configASSERT( pxTaskDefinition->pxTaskBuffer != NULL ); + /* Enabling interrupts should cause this core to immediately + * service the pending interrupt and yield. If the run state is still + * yielding here then that is a problem. */ + configASSERT( pxThisTCB->xTaskRunState != taskTASK_SCHEDULED_TO_YIELD ); - if( ( pxTaskDefinition->puxStackBuffer != NULL ) && ( pxTaskDefinition->pxTaskBuffer != NULL ) ) - { - /* Allocate space for the TCB. Where the memory comes from depends - * on the implementation of the port malloc function and whether or - * not static allocation is being used. */ - pxNewTCB = ( TCB_t * ) pxTaskDefinition->pxTaskBuffer; - memset( ( void * ) pxNewTCB, 0x00, sizeof( TCB_t ) ); + portDISABLE_INTERRUPTS(); + portGET_TASK_LOCK(); + portGET_ISR_LOCK(); - /* Store the stack location in the TCB. */ - pxNewTCB->pxStack = pxTaskDefinition->puxStackBuffer; + portSET_CRITICAL_NESTING_COUNT( uxPrevCriticalNesting ); - #if ( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0 ) + if( uxPrevCriticalNesting == 0U ) { - /* Tasks can be created statically or dynamically, so note this - * task was created statically in case the task is later deleted. */ - pxNewTCB->ucStaticallyAllocated = tskSTATICALLY_ALLOCATED_STACK_AND_TCB; + portRELEASE_ISR_LOCK(); } - #endif /* tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE */ - - prvInitialiseNewTask( pxTaskDefinition->pvTaskCode, - pxTaskDefinition->pcName, - ( uint32_t ) pxTaskDefinition->usStackDepth, - pxTaskDefinition->pvParameters, - pxTaskDefinition->uxPriority, - pxCreatedTask, pxNewTCB, - pxTaskDefinition->xRegions ); - - prvAddNewTaskToReadyList( pxNewTCB ); - xReturn = pdPASS; } - - return xReturn; } +#endif /* #if ( configNUMBER_OF_CORES > 1 ) */ -#endif /* ( portUSING_MPU_WRAPPERS == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) */ /*-----------------------------------------------------------*/ -#if ( ( portUSING_MPU_WRAPPERS == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) ) - - BaseType_t xTaskCreateRestricted( const TaskParameters_t * const pxTaskDefinition, - TaskHandle_t * pxCreatedTask ) +#if ( configNUMBER_OF_CORES > 1 ) + static void prvYieldForTask( const TCB_t * pxTCB ) { - TCB_t * pxNewTCB; - BaseType_t xReturn = errCOULD_NOT_ALLOCATE_REQUIRED_MEMORY; + BaseType_t xLowestPriorityToPreempt; + BaseType_t xCurrentCoreTaskPriority; + BaseType_t xLowestPriorityCore = ( BaseType_t ) -1; + BaseType_t xCoreID; - configASSERT( pxTaskDefinition->puxStackBuffer ); + #if ( configRUN_MULTIPLE_PRIORITIES == 0 ) + BaseType_t xYieldCount = 0; + #endif /* #if ( configRUN_MULTIPLE_PRIORITIES == 0 ) */ - if( pxTaskDefinition->puxStackBuffer != NULL ) + /* This must be called from a critical section. */ + configASSERT( portGET_CRITICAL_NESTING_COUNT() > 0U ); + + #if ( configRUN_MULTIPLE_PRIORITIES == 0 ) + + /* No task should yield for this one if it is a lower priority + * than priority level of currently ready tasks. */ + if( pxTCB->uxPriority >= uxTopReadyPriority ) + #else + /* Yield is not required for a task which is already running. */ + if( taskTASK_IS_RUNNING( pxTCB ) == pdFALSE ) + #endif { - /* Allocate space for the TCB. Where the memory comes from depends - * on the implementation of the port malloc function and whether or - * not static allocation is being used. */ - pxNewTCB = ( TCB_t * ) pvPortMalloc( sizeof( TCB_t ) ); + xLowestPriorityToPreempt = ( BaseType_t ) pxTCB->uxPriority; - if( pxNewTCB != NULL ) - { - memset( ( void * ) pxNewTCB, 0x00, sizeof( TCB_t ) ); + /* xLowestPriorityToPreempt will be decremented to -1 if the priority of pxTCB + * is 0. This is ok as we will give system idle tasks a priority of -1 below. */ + --xLowestPriorityToPreempt; - /* Store the stack location in the TCB. */ - pxNewTCB->pxStack = pxTaskDefinition->puxStackBuffer; + for( xCoreID = ( BaseType_t ) 0; xCoreID < ( BaseType_t ) configNUMBER_OF_CORES; xCoreID++ ) + { + xCurrentCoreTaskPriority = ( BaseType_t ) pxCurrentTCBs[ xCoreID ]->uxPriority; - #if ( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0 ) + /* System idle tasks are being assigned a priority of tskIDLE_PRIORITY - 1 here. */ + if( ( pxCurrentTCBs[ xCoreID ]->uxTaskAttributes & taskATTRIBUTE_IS_IDLE ) != 0U ) { - /* Tasks can be created statically or dynamically, so note - * this task had a statically allocated stack in case it is - * later deleted. The TCB was allocated dynamically. */ - pxNewTCB->ucStaticallyAllocated = tskSTATICALLY_ALLOCATED_STACK_ONLY; + xCurrentCoreTaskPriority = xCurrentCoreTaskPriority - 1; } - #endif /* tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE */ - prvInitialiseNewTask( pxTaskDefinition->pvTaskCode, - pxTaskDefinition->pcName, - ( uint32_t ) pxTaskDefinition->usStackDepth, - pxTaskDefinition->pvParameters, - pxTaskDefinition->uxPriority, - pxCreatedTask, pxNewTCB, - pxTaskDefinition->xRegions ); + if( ( taskTASK_IS_RUNNING( pxCurrentTCBs[ xCoreID ] ) != pdFALSE ) && ( xYieldPendings[ xCoreID ] == pdFALSE ) ) + { + #if ( configRUN_MULTIPLE_PRIORITIES == 0 ) + if( taskTASK_IS_RUNNING( pxTCB ) == pdFALSE ) + #endif + { + if( xCurrentCoreTaskPriority <= xLowestPriorityToPreempt ) + { + #if ( configUSE_CORE_AFFINITY == 1 ) + if( ( pxTCB->uxCoreAffinityMask & ( ( UBaseType_t ) 1U << ( UBaseType_t ) xCoreID ) ) != 0U ) + #endif + { + #if ( configUSE_TASK_PREEMPTION_DISABLE == 1 ) + if( pxCurrentTCBs[ xCoreID ]->xPreemptionDisable == pdFALSE ) + #endif + { + xLowestPriorityToPreempt = xCurrentCoreTaskPriority; + xLowestPriorityCore = xCoreID; + } + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } - prvAddNewTaskToReadyList( pxNewTCB ); - xReturn = pdPASS; + #if ( configRUN_MULTIPLE_PRIORITIES == 0 ) + { + /* Yield all currently running non-idle tasks with a priority lower than + * the task that needs to run. */ + if( ( xCurrentCoreTaskPriority > ( ( BaseType_t ) tskIDLE_PRIORITY - 1 ) ) && + ( xCurrentCoreTaskPriority < ( BaseType_t ) pxTCB->uxPriority ) ) + { + prvYieldCore( xCoreID ); + xYieldCount++; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + #endif /* #if ( configRUN_MULTIPLE_PRIORITIES == 0 ) */ + } + else + { + mtCOVERAGE_TEST_MARKER(); + } } - } - return xReturn; - } + #if ( configRUN_MULTIPLE_PRIORITIES == 0 ) + if( ( xYieldCount == 0 ) && ( xLowestPriorityCore >= 0 ) ) + #else /* #if ( configRUN_MULTIPLE_PRIORITIES == 0 ) */ + if( xLowestPriorityCore >= 0 ) + #endif /* #if ( configRUN_MULTIPLE_PRIORITIES == 0 ) */ + { + prvYieldCore( xLowestPriorityCore ); + } -#endif /* portUSING_MPU_WRAPPERS */ + #if ( configRUN_MULTIPLE_PRIORITIES == 0 ) + /* Verify that the calling core always yields to higher priority tasks. */ + if( ( ( pxCurrentTCBs[ portGET_CORE_ID() ]->uxTaskAttributes & taskATTRIBUTE_IS_IDLE ) == 0U ) && + ( pxTCB->uxPriority > pxCurrentTCBs[ portGET_CORE_ID() ]->uxPriority ) ) + { + configASSERT( ( xYieldPendings[ portGET_CORE_ID() ] == pdTRUE ) || + ( taskTASK_IS_RUNNING( pxCurrentTCBs[ portGET_CORE_ID() ] ) == pdFALSE ) ); + } + #endif + } + } +#endif /* #if ( configNUMBER_OF_CORES > 1 ) */ /*-----------------------------------------------------------*/ -#if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) - - BaseType_t xTaskCreate( TaskFunction_t pxTaskCode, - const char * const pcName, /*lint !e971 Unqualified char types are allowed for strings and single characters only. */ - const configSTACK_DEPTH_TYPE usStackDepth, - void * const pvParameters, - UBaseType_t uxPriority, - TaskHandle_t * const pxCreatedTask ) +#if ( configNUMBER_OF_CORES > 1 ) + static void prvSelectHighestPriorityTask( BaseType_t xCoreID ) { - TCB_t * pxNewTCB; - BaseType_t xReturn; + UBaseType_t uxCurrentPriority = uxTopReadyPriority; + BaseType_t xTaskScheduled = pdFALSE; + BaseType_t xDecrementTopPriority = pdTRUE; - /* If the stack grows down then allocate the stack then the TCB so the stack - * does not grow into the TCB. Likewise if the stack grows up then allocate - * the TCB then the stack. */ - #if ( portSTACK_GROWTH > 0 ) - { - /* Allocate space for the TCB. Where the memory comes from depends on - * the implementation of the port malloc function and whether or not static - * allocation is being used. */ - pxNewTCB = ( TCB_t * ) pvPortMalloc( sizeof( TCB_t ) ); + #if ( configUSE_CORE_AFFINITY == 1 ) + const TCB_t * pxPreviousTCB = NULL; + #endif + #if ( configRUN_MULTIPLE_PRIORITIES == 0 ) + BaseType_t xPriorityDropped = pdFALSE; + #endif - if( pxNewTCB != NULL ) - { - memset( ( void * ) pxNewTCB, 0x00, sizeof( TCB_t ) ); + /* This function should be called when scheduler is running. */ + configASSERT( xSchedulerRunning == pdTRUE ); - /* Allocate space for the stack used by the task being created. - * The base of the stack memory stored in the TCB so the task can - * be deleted later if required. */ - pxNewTCB->pxStack = ( StackType_t * ) pvPortMallocStack( ( ( ( size_t ) usStackDepth ) * sizeof( StackType_t ) ) ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */ + /* A new task is created and a running task with the same priority yields + * itself to run the new task. When a running task yields itself, it is still + * in the ready list. This running task will be selected before the new task + * since the new task is always added to the end of the ready list. + * The other problem is that the running task still in the same position of + * the ready list when it yields itself. It is possible that it will be selected + * earlier then other tasks which waits longer than this task. + * + * To fix these problems, the running task should be put to the end of the + * ready list before searching for the ready task in the ready list. */ + if( listIS_CONTAINED_WITHIN( &( pxReadyTasksLists[ pxCurrentTCBs[ xCoreID ]->uxPriority ] ), + &pxCurrentTCBs[ xCoreID ]->xStateListItem ) == pdTRUE ) + { + ( void ) uxListRemove( &pxCurrentTCBs[ xCoreID ]->xStateListItem ); + vListInsertEnd( &( pxReadyTasksLists[ pxCurrentTCBs[ xCoreID ]->uxPriority ] ), + &pxCurrentTCBs[ xCoreID ]->xStateListItem ); + } - if( pxNewTCB->pxStack == NULL ) + while( xTaskScheduled == pdFALSE ) + { + #if ( configRUN_MULTIPLE_PRIORITIES == 0 ) + { + if( uxCurrentPriority < uxTopReadyPriority ) + { + /* We can't schedule any tasks, other than idle, that have a + * priority lower than the priority of a task currently running + * on another core. */ + uxCurrentPriority = tskIDLE_PRIORITY; + } + } + #endif + + if( listLIST_IS_EMPTY( &( pxReadyTasksLists[ uxCurrentPriority ] ) ) == pdFALSE ) + { + const List_t * const pxReadyList = &( pxReadyTasksLists[ uxCurrentPriority ] ); + const ListItem_t * pxEndMarker = listGET_END_MARKER( pxReadyList ); + ListItem_t * pxIterator; + + /* The ready task list for uxCurrentPriority is not empty, so uxTopReadyPriority + * must not be decremented any further. */ + xDecrementTopPriority = pdFALSE; + + for( pxIterator = listGET_HEAD_ENTRY( pxReadyList ); pxIterator != pxEndMarker; pxIterator = listGET_NEXT( pxIterator ) ) + { + /* MISRA Ref 11.5.3 [Void pointer assignment] */ + /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-115 */ + /* coverity[misra_c_2012_rule_11_5_violation] */ + TCB_t * pxTCB = ( TCB_t * ) listGET_LIST_ITEM_OWNER( pxIterator ); + + #if ( configRUN_MULTIPLE_PRIORITIES == 0 ) + { + /* When falling back to the idle priority because only one priority + * level is allowed to run at a time, we should ONLY schedule the true + * idle tasks, not user tasks at the idle priority. */ + if( uxCurrentPriority < uxTopReadyPriority ) + { + if( ( pxTCB->uxTaskAttributes & taskATTRIBUTE_IS_IDLE ) == 0U ) + { + continue; + } + } + } + #endif /* #if ( configRUN_MULTIPLE_PRIORITIES == 0 ) */ + + if( pxTCB->xTaskRunState == taskTASK_NOT_RUNNING ) + { + #if ( configUSE_CORE_AFFINITY == 1 ) + if( ( pxTCB->uxCoreAffinityMask & ( ( UBaseType_t ) 1U << ( UBaseType_t ) xCoreID ) ) != 0U ) + #endif + { + /* If the task is not being executed by any core swap it in. */ + pxCurrentTCBs[ xCoreID ]->xTaskRunState = taskTASK_NOT_RUNNING; + #if ( configUSE_CORE_AFFINITY == 1 ) + pxPreviousTCB = pxCurrentTCBs[ xCoreID ]; + #endif + pxTCB->xTaskRunState = xCoreID; + pxCurrentTCBs[ xCoreID ] = pxTCB; + xTaskScheduled = pdTRUE; + } + } + else if( pxTCB == pxCurrentTCBs[ xCoreID ] ) + { + configASSERT( ( pxTCB->xTaskRunState == xCoreID ) || ( pxTCB->xTaskRunState == taskTASK_SCHEDULED_TO_YIELD ) ); + + #if ( configUSE_CORE_AFFINITY == 1 ) + if( ( pxTCB->uxCoreAffinityMask & ( ( UBaseType_t ) 1U << ( UBaseType_t ) xCoreID ) ) != 0U ) + #endif + { + /* The task is already running on this core, mark it as scheduled. */ + pxTCB->xTaskRunState = xCoreID; + xTaskScheduled = pdTRUE; + } + } + else + { + /* This task is running on the core other than xCoreID. */ + mtCOVERAGE_TEST_MARKER(); + } + + if( xTaskScheduled != pdFALSE ) + { + /* A task has been selected to run on this core. */ + break; + } + } + } + else + { + if( xDecrementTopPriority != pdFALSE ) + { + uxTopReadyPriority--; + #if ( configRUN_MULTIPLE_PRIORITIES == 0 ) + { + xPriorityDropped = pdTRUE; + } + #endif + } + } + + /* There are configNUMBER_OF_CORES Idle tasks created when scheduler started. + * The scheduler should be able to select a task to run when uxCurrentPriority + * is tskIDLE_PRIORITY. uxCurrentPriority is never decreased to value blow + * tskIDLE_PRIORITY. */ + if( uxCurrentPriority > tskIDLE_PRIORITY ) + { + uxCurrentPriority--; + } + else + { + /* This function is called when idle task is not created. Break the + * loop to prevent uxCurrentPriority overrun. */ + break; + } + } + + #if ( configRUN_MULTIPLE_PRIORITIES == 0 ) + { + if( xTaskScheduled == pdTRUE ) + { + if( xPriorityDropped != pdFALSE ) + { + /* There may be several ready tasks that were being prevented from running because there was + * a higher priority task running. Now that the last of the higher priority tasks is no longer + * running, make sure all the other idle tasks yield. */ + BaseType_t x; + + for( x = ( BaseType_t ) 0; x < ( BaseType_t ) configNUMBER_OF_CORES; x++ ) + { + if( ( pxCurrentTCBs[ x ]->uxTaskAttributes & taskATTRIBUTE_IS_IDLE ) != 0U ) + { + prvYieldCore( x ); + } + } + } + } + } + #endif /* #if ( configRUN_MULTIPLE_PRIORITIES == 0 ) */ + + #if ( configUSE_CORE_AFFINITY == 1 ) + { + if( xTaskScheduled == pdTRUE ) + { + if( ( pxPreviousTCB != NULL ) && ( listIS_CONTAINED_WITHIN( &( pxReadyTasksLists[ pxPreviousTCB->uxPriority ] ), &( pxPreviousTCB->xStateListItem ) ) != pdFALSE ) ) + { + /* A ready task was just evicted from this core. See if it can be + * scheduled on any other core. */ + UBaseType_t uxCoreMap = pxPreviousTCB->uxCoreAffinityMask; + BaseType_t xLowestPriority = ( BaseType_t ) pxPreviousTCB->uxPriority; + BaseType_t xLowestPriorityCore = -1; + BaseType_t x; + + if( ( pxPreviousTCB->uxTaskAttributes & taskATTRIBUTE_IS_IDLE ) != 0U ) + { + xLowestPriority = xLowestPriority - 1; + } + + if( ( uxCoreMap & ( ( UBaseType_t ) 1U << ( UBaseType_t ) xCoreID ) ) != 0U ) + { + /* pxPreviousTCB was removed from this core and this core is not excluded + * from it's core affinity mask. + * + * pxPreviousTCB is preempted by the new higher priority task + * pxCurrentTCBs[ xCoreID ]. When searching a new core for pxPreviousTCB, + * we do not need to look at the cores on which pxCurrentTCBs[ xCoreID ] + * is allowed to run. The reason is - when more than one cores are + * eligible for an incoming task, we preempt the core with the minimum + * priority task. Because this core (i.e. xCoreID) was preempted for + * pxCurrentTCBs[ xCoreID ], this means that all the others cores + * where pxCurrentTCBs[ xCoreID ] can run, are running tasks with priority + * no lower than pxPreviousTCB's priority. Therefore, the only cores where + * which can be preempted for pxPreviousTCB are the ones where + * pxCurrentTCBs[ xCoreID ] is not allowed to run (and obviously, + * pxPreviousTCB is allowed to run). + * + * This is an optimization which reduces the number of cores needed to be + * searched for pxPreviousTCB to run. */ + uxCoreMap &= ~( pxCurrentTCBs[ xCoreID ]->uxCoreAffinityMask ); + } + else + { + /* pxPreviousTCB's core affinity mask is changed and it is no longer + * allowed to run on this core. Searching all the cores in pxPreviousTCB's + * new core affinity mask to find a core on which it can run. */ + } + + uxCoreMap &= ( ( 1U << configNUMBER_OF_CORES ) - 1U ); + + for( x = ( ( BaseType_t ) configNUMBER_OF_CORES - 1 ); x >= ( BaseType_t ) 0; x-- ) + { + UBaseType_t uxCore = ( UBaseType_t ) x; + BaseType_t xTaskPriority; + + if( ( uxCoreMap & ( ( UBaseType_t ) 1U << uxCore ) ) != 0U ) + { + xTaskPriority = ( BaseType_t ) pxCurrentTCBs[ uxCore ]->uxPriority; + + if( ( pxCurrentTCBs[ uxCore ]->uxTaskAttributes & taskATTRIBUTE_IS_IDLE ) != 0U ) + { + xTaskPriority = xTaskPriority - ( BaseType_t ) 1; + } + + uxCoreMap &= ~( ( UBaseType_t ) 1U << uxCore ); + + if( ( xTaskPriority < xLowestPriority ) && + ( taskTASK_IS_RUNNING( pxCurrentTCBs[ uxCore ] ) != pdFALSE ) && + ( xYieldPendings[ uxCore ] == pdFALSE ) ) + { + #if ( configUSE_TASK_PREEMPTION_DISABLE == 1 ) + if( pxCurrentTCBs[ uxCore ]->xPreemptionDisable == pdFALSE ) + #endif + { + xLowestPriority = xTaskPriority; + xLowestPriorityCore = ( BaseType_t ) uxCore; + } + } + } + } + + if( xLowestPriorityCore >= 0 ) + { + prvYieldCore( xLowestPriorityCore ); + } + } + } + } + #endif /* #if ( configUSE_CORE_AFFINITY == 1 ) */ + } + +#endif /* ( configNUMBER_OF_CORES > 1 ) */ + +/*-----------------------------------------------------------*/ + +#if ( configSUPPORT_STATIC_ALLOCATION == 1 ) + + static TCB_t * prvCreateStaticTask( TaskFunction_t pxTaskCode, + const char * const pcName, + const uint32_t ulStackDepth, + void * const pvParameters, + UBaseType_t uxPriority, + StackType_t * const puxStackBuffer, + StaticTask_t * const pxTaskBuffer, + TaskHandle_t * const pxCreatedTask ) + { + TCB_t * pxNewTCB; + + configASSERT( puxStackBuffer != NULL ); + configASSERT( pxTaskBuffer != NULL ); + + #if ( configASSERT_DEFINED == 1 ) + { + /* Sanity check that the size of the structure used to declare a + * variable of type StaticTask_t equals the size of the real task + * structure. */ + volatile size_t xSize = sizeof( StaticTask_t ); + configASSERT( xSize == sizeof( TCB_t ) ); + ( void ) xSize; /* Prevent unused variable warning when configASSERT() is not used. */ + } + #endif /* configASSERT_DEFINED */ + + if( ( pxTaskBuffer != NULL ) && ( puxStackBuffer != NULL ) ) + { + /* The memory used for the task's TCB and stack are passed into this + * function - use them. */ + /* MISRA Ref 11.3.1 [Misaligned access] */ + /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-113 */ + /* coverity[misra_c_2012_rule_11_3_violation] */ + pxNewTCB = ( TCB_t * ) pxTaskBuffer; + ( void ) memset( ( void * ) pxNewTCB, 0x00, sizeof( TCB_t ) ); + pxNewTCB->pxStack = ( StackType_t * ) puxStackBuffer; + + #if ( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0 ) + { + /* Tasks can be created statically or dynamically, so note this + * task was created statically in case the task is later deleted. */ + pxNewTCB->ucStaticallyAllocated = tskSTATICALLY_ALLOCATED_STACK_AND_TCB; + } + #endif /* tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE */ + + prvInitialiseNewTask( pxTaskCode, pcName, ulStackDepth, pvParameters, uxPriority, pxCreatedTask, pxNewTCB, NULL ); + } + else + { + pxNewTCB = NULL; + } + + return pxNewTCB; + } +/*-----------------------------------------------------------*/ + + TaskHandle_t xTaskCreateStatic( TaskFunction_t pxTaskCode, + const char * const pcName, + const uint32_t ulStackDepth, + void * const pvParameters, + UBaseType_t uxPriority, + StackType_t * const puxStackBuffer, + StaticTask_t * const pxTaskBuffer ) + { + TaskHandle_t xReturn = NULL; + TCB_t * pxNewTCB; + + traceENTER_xTaskCreateStatic( pxTaskCode, pcName, ulStackDepth, pvParameters, uxPriority, puxStackBuffer, pxTaskBuffer ); + + pxNewTCB = prvCreateStaticTask( pxTaskCode, pcName, ulStackDepth, pvParameters, uxPriority, puxStackBuffer, pxTaskBuffer, &xReturn ); + + if( pxNewTCB != NULL ) + { + #if ( ( configNUMBER_OF_CORES > 1 ) && ( configUSE_CORE_AFFINITY == 1 ) ) + { + /* Set the task's affinity before scheduling it. */ + pxNewTCB->uxCoreAffinityMask = tskNO_AFFINITY; + } + #endif + + prvAddNewTaskToReadyList( pxNewTCB ); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + traceRETURN_xTaskCreateStatic( xReturn ); + + return xReturn; + } +/*-----------------------------------------------------------*/ + + #if ( ( configNUMBER_OF_CORES > 1 ) && ( configUSE_CORE_AFFINITY == 1 ) ) + TaskHandle_t xTaskCreateStaticAffinitySet( TaskFunction_t pxTaskCode, + const char * const pcName, + const uint32_t ulStackDepth, + void * const pvParameters, + UBaseType_t uxPriority, + StackType_t * const puxStackBuffer, + StaticTask_t * const pxTaskBuffer, + UBaseType_t uxCoreAffinityMask ) + { + TaskHandle_t xReturn = NULL; + TCB_t * pxNewTCB; + + traceENTER_xTaskCreateStaticAffinitySet( pxTaskCode, pcName, ulStackDepth, pvParameters, uxPriority, puxStackBuffer, pxTaskBuffer, uxCoreAffinityMask ); + + pxNewTCB = prvCreateStaticTask( pxTaskCode, pcName, ulStackDepth, pvParameters, uxPriority, puxStackBuffer, pxTaskBuffer, &xReturn ); + + if( pxNewTCB != NULL ) + { + /* Set the task's affinity before scheduling it. */ + pxNewTCB->uxCoreAffinityMask = uxCoreAffinityMask; + + prvAddNewTaskToReadyList( pxNewTCB ); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + traceRETURN_xTaskCreateStaticAffinitySet( xReturn ); + + return xReturn; + } + #endif /* #if ( ( configNUMBER_OF_CORES > 1 ) && ( configUSE_CORE_AFFINITY == 1 ) ) */ + +#endif /* SUPPORT_STATIC_ALLOCATION */ +/*-----------------------------------------------------------*/ + +#if ( ( portUSING_MPU_WRAPPERS == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) ) + static TCB_t * prvCreateRestrictedStaticTask( const TaskParameters_t * const pxTaskDefinition, + TaskHandle_t * const pxCreatedTask ) + { + TCB_t * pxNewTCB; + + configASSERT( pxTaskDefinition->puxStackBuffer != NULL ); + configASSERT( pxTaskDefinition->pxTaskBuffer != NULL ); + + if( ( pxTaskDefinition->puxStackBuffer != NULL ) && ( pxTaskDefinition->pxTaskBuffer != NULL ) ) + { + /* Allocate space for the TCB. Where the memory comes from depends + * on the implementation of the port malloc function and whether or + * not static allocation is being used. */ + pxNewTCB = ( TCB_t * ) pxTaskDefinition->pxTaskBuffer; + ( void ) memset( ( void * ) pxNewTCB, 0x00, sizeof( TCB_t ) ); + + /* Store the stack location in the TCB. */ + pxNewTCB->pxStack = pxTaskDefinition->puxStackBuffer; + + #if ( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0 ) + { + /* Tasks can be created statically or dynamically, so note this + * task was created statically in case the task is later deleted. */ + pxNewTCB->ucStaticallyAllocated = tskSTATICALLY_ALLOCATED_STACK_AND_TCB; + } + #endif /* tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE */ + + prvInitialiseNewTask( pxTaskDefinition->pvTaskCode, + pxTaskDefinition->pcName, + ( uint32_t ) pxTaskDefinition->usStackDepth, + pxTaskDefinition->pvParameters, + pxTaskDefinition->uxPriority, + pxCreatedTask, pxNewTCB, + pxTaskDefinition->xRegions ); + } + else + { + pxNewTCB = NULL; + } + + return pxNewTCB; + } +/*-----------------------------------------------------------*/ + + BaseType_t xTaskCreateRestrictedStatic( const TaskParameters_t * const pxTaskDefinition, + TaskHandle_t * pxCreatedTask ) + { + TCB_t * pxNewTCB; + BaseType_t xReturn; + + traceENTER_xTaskCreateRestrictedStatic( pxTaskDefinition, pxCreatedTask ); + + configASSERT( pxTaskDefinition != NULL ); + + pxNewTCB = prvCreateRestrictedStaticTask( pxTaskDefinition, pxCreatedTask ); + + if( pxNewTCB != NULL ) + { + #if ( ( configNUMBER_OF_CORES > 1 ) && ( configUSE_CORE_AFFINITY == 1 ) ) + { + /* Set the task's affinity before scheduling it. */ + pxNewTCB->uxCoreAffinityMask = tskNO_AFFINITY; + } + #endif + + prvAddNewTaskToReadyList( pxNewTCB ); + xReturn = pdPASS; + } + else + { + xReturn = errCOULD_NOT_ALLOCATE_REQUIRED_MEMORY; + } + + traceRETURN_xTaskCreateRestrictedStatic( xReturn ); + + return xReturn; + } +/*-----------------------------------------------------------*/ + + #if ( ( configNUMBER_OF_CORES > 1 ) && ( configUSE_CORE_AFFINITY == 1 ) ) + BaseType_t xTaskCreateRestrictedStaticAffinitySet( const TaskParameters_t * const pxTaskDefinition, + UBaseType_t uxCoreAffinityMask, + TaskHandle_t * pxCreatedTask ) + { + TCB_t * pxNewTCB; + BaseType_t xReturn; + + traceENTER_xTaskCreateRestrictedStaticAffinitySet( pxTaskDefinition, uxCoreAffinityMask, pxCreatedTask ); + + configASSERT( pxTaskDefinition != NULL ); + + pxNewTCB = prvCreateRestrictedStaticTask( pxTaskDefinition, pxCreatedTask ); + + if( pxNewTCB != NULL ) + { + /* Set the task's affinity before scheduling it. */ + pxNewTCB->uxCoreAffinityMask = uxCoreAffinityMask; + + prvAddNewTaskToReadyList( pxNewTCB ); + xReturn = pdPASS; + } + else + { + xReturn = errCOULD_NOT_ALLOCATE_REQUIRED_MEMORY; + } + + traceRETURN_xTaskCreateRestrictedStaticAffinitySet( xReturn ); + + return xReturn; + } + #endif /* #if ( ( configNUMBER_OF_CORES > 1 ) && ( configUSE_CORE_AFFINITY == 1 ) ) */ + +#endif /* ( portUSING_MPU_WRAPPERS == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) */ +/*-----------------------------------------------------------*/ + +#if ( ( portUSING_MPU_WRAPPERS == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) ) + static TCB_t * prvCreateRestrictedTask( const TaskParameters_t * const pxTaskDefinition, + TaskHandle_t * const pxCreatedTask ) + { + TCB_t * pxNewTCB; + + configASSERT( pxTaskDefinition->puxStackBuffer ); + + if( pxTaskDefinition->puxStackBuffer != NULL ) + { + /* MISRA Ref 11.5.1 [Malloc memory assignment] */ + /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-115 */ + /* coverity[misra_c_2012_rule_11_5_violation] */ + pxNewTCB = ( TCB_t * ) pvPortMalloc( sizeof( TCB_t ) ); + + if( pxNewTCB != NULL ) + { + ( void ) memset( ( void * ) pxNewTCB, 0x00, sizeof( TCB_t ) ); + + /* Store the stack location in the TCB. */ + pxNewTCB->pxStack = pxTaskDefinition->puxStackBuffer; + + #if ( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0 ) + { + /* Tasks can be created statically or dynamically, so note + * this task had a statically allocated stack in case it is + * later deleted. The TCB was allocated dynamically. */ + pxNewTCB->ucStaticallyAllocated = tskSTATICALLY_ALLOCATED_STACK_ONLY; + } + #endif /* tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE */ + + prvInitialiseNewTask( pxTaskDefinition->pvTaskCode, + pxTaskDefinition->pcName, + ( uint32_t ) pxTaskDefinition->usStackDepth, + pxTaskDefinition->pvParameters, + pxTaskDefinition->uxPriority, + pxCreatedTask, pxNewTCB, + pxTaskDefinition->xRegions ); + } + } + else + { + pxNewTCB = NULL; + } + + return pxNewTCB; + } +/*-----------------------------------------------------------*/ + + BaseType_t xTaskCreateRestricted( const TaskParameters_t * const pxTaskDefinition, + TaskHandle_t * pxCreatedTask ) + { + TCB_t * pxNewTCB; + BaseType_t xReturn; + + traceENTER_xTaskCreateRestricted( pxTaskDefinition, pxCreatedTask ); + + pxNewTCB = prvCreateRestrictedTask( pxTaskDefinition, pxCreatedTask ); + + if( pxNewTCB != NULL ) + { + #if ( ( configNUMBER_OF_CORES > 1 ) && ( configUSE_CORE_AFFINITY == 1 ) ) + { + /* Set the task's affinity before scheduling it. */ + pxNewTCB->uxCoreAffinityMask = tskNO_AFFINITY; + } + #endif /* #if ( ( configNUMBER_OF_CORES > 1 ) && ( configUSE_CORE_AFFINITY == 1 ) ) */ + + prvAddNewTaskToReadyList( pxNewTCB ); + + xReturn = pdPASS; + } + else + { + xReturn = errCOULD_NOT_ALLOCATE_REQUIRED_MEMORY; + } + + traceRETURN_xTaskCreateRestricted( xReturn ); + + return xReturn; + } +/*-----------------------------------------------------------*/ + + #if ( ( configNUMBER_OF_CORES > 1 ) && ( configUSE_CORE_AFFINITY == 1 ) ) + BaseType_t xTaskCreateRestrictedAffinitySet( const TaskParameters_t * const pxTaskDefinition, + UBaseType_t uxCoreAffinityMask, + TaskHandle_t * pxCreatedTask ) + { + TCB_t * pxNewTCB; + BaseType_t xReturn; + + traceENTER_xTaskCreateRestrictedAffinitySet( pxTaskDefinition, uxCoreAffinityMask, pxCreatedTask ); + + pxNewTCB = prvCreateRestrictedTask( pxTaskDefinition, pxCreatedTask ); + + if( pxNewTCB != NULL ) + { + /* Set the task's affinity before scheduling it. */ + pxNewTCB->uxCoreAffinityMask = uxCoreAffinityMask; + + prvAddNewTaskToReadyList( pxNewTCB ); + + xReturn = pdPASS; + } + else + { + xReturn = errCOULD_NOT_ALLOCATE_REQUIRED_MEMORY; + } + + traceRETURN_xTaskCreateRestrictedAffinitySet( xReturn ); + + return xReturn; + } + #endif /* #if ( ( configNUMBER_OF_CORES > 1 ) && ( configUSE_CORE_AFFINITY == 1 ) ) */ + + +#endif /* portUSING_MPU_WRAPPERS */ +/*-----------------------------------------------------------*/ + +#if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) + static TCB_t * prvCreateTask( TaskFunction_t pxTaskCode, + const char * const pcName, + const configSTACK_DEPTH_TYPE usStackDepth, + void * const pvParameters, + UBaseType_t uxPriority, + TaskHandle_t * const pxCreatedTask ) + { + TCB_t * pxNewTCB; + + /* If the stack grows down then allocate the stack then the TCB so the stack + * does not grow into the TCB. Likewise if the stack grows up then allocate + * the TCB then the stack. */ + #if ( portSTACK_GROWTH > 0 ) + { + /* Allocate space for the TCB. Where the memory comes from depends on + * the implementation of the port malloc function and whether or not static + * allocation is being used. */ + /* MISRA Ref 11.5.1 [Malloc memory assignment] */ + /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-115 */ + /* coverity[misra_c_2012_rule_11_5_violation] */ + pxNewTCB = ( TCB_t * ) pvPortMalloc( sizeof( TCB_t ) ); + + if( pxNewTCB != NULL ) + { + ( void ) memset( ( void * ) pxNewTCB, 0x00, sizeof( TCB_t ) ); + + /* Allocate space for the stack used by the task being created. + * The base of the stack memory stored in the TCB so the task can + * be deleted later if required. */ + /* MISRA Ref 11.5.1 [Malloc memory assignment] */ + /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-115 */ + /* coverity[misra_c_2012_rule_11_5_violation] */ + pxNewTCB->pxStack = ( StackType_t * ) pvPortMallocStack( ( ( ( size_t ) usStackDepth ) * sizeof( StackType_t ) ) ); + + if( pxNewTCB->pxStack == NULL ) { /* Could not allocate the stack. Delete the allocated TCB. */ vPortFree( pxNewTCB ); @@ -764,16 +1656,22 @@ static void prvAddNewTaskToReadyList( TCB_t * pxNewTCB ) PRIVILEGED_FUNCTION; StackType_t * pxStack; /* Allocate space for the stack used by the task being created. */ - pxStack = pvPortMallocStack( ( ( ( size_t ) usStackDepth ) * sizeof( StackType_t ) ) ); /*lint !e9079 All values returned by pvPortMalloc() have at least the alignment required by the MCU's stack and this allocation is the stack. */ + /* MISRA Ref 11.5.1 [Malloc memory assignment] */ + /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-115 */ + /* coverity[misra_c_2012_rule_11_5_violation] */ + pxStack = pvPortMallocStack( ( ( ( size_t ) usStackDepth ) * sizeof( StackType_t ) ) ); if( pxStack != NULL ) { /* Allocate space for the TCB. */ - pxNewTCB = ( TCB_t * ) pvPortMalloc( sizeof( TCB_t ) ); /*lint !e9087 !e9079 All values returned by pvPortMalloc() have at least the alignment required by the MCU's stack, and the first member of TCB_t is always a pointer to the task's stack. */ + /* MISRA Ref 11.5.1 [Malloc memory assignment] */ + /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-115 */ + /* coverity[misra_c_2012_rule_11_5_violation] */ + pxNewTCB = ( TCB_t * ) pvPortMalloc( sizeof( TCB_t ) ); if( pxNewTCB != NULL ) { - memset( ( void * ) pxNewTCB, 0x00, sizeof( TCB_t ) ); + ( void ) memset( ( void * ) pxNewTCB, 0x00, sizeof( TCB_t ) ); /* Store the stack location in the TCB. */ pxNewTCB->pxStack = pxStack; @@ -794,7 +1692,7 @@ static void prvAddNewTaskToReadyList( TCB_t * pxNewTCB ) PRIVILEGED_FUNCTION; if( pxNewTCB != NULL ) { - #if ( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0 ) /*lint !e9029 !e731 Macro has been consolidated for readability reasons. */ + #if ( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0 ) { /* Tasks can be created statically or dynamically, so note this * task was created dynamically in case it is later deleted. */ @@ -803,6 +1701,35 @@ static void prvAddNewTaskToReadyList( TCB_t * pxNewTCB ) PRIVILEGED_FUNCTION; #endif /* tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE */ prvInitialiseNewTask( pxTaskCode, pcName, ( uint32_t ) usStackDepth, pvParameters, uxPriority, pxCreatedTask, pxNewTCB, NULL ); + } + + return pxNewTCB; + } +/*-----------------------------------------------------------*/ + + BaseType_t xTaskCreate( TaskFunction_t pxTaskCode, + const char * const pcName, + const configSTACK_DEPTH_TYPE usStackDepth, + void * const pvParameters, + UBaseType_t uxPriority, + TaskHandle_t * const pxCreatedTask ) + { + TCB_t * pxNewTCB; + BaseType_t xReturn; + + traceENTER_xTaskCreate( pxTaskCode, pcName, usStackDepth, pvParameters, uxPriority, pxCreatedTask ); + + pxNewTCB = prvCreateTask( pxTaskCode, pcName, usStackDepth, pvParameters, uxPriority, pxCreatedTask ); + + if( pxNewTCB != NULL ) + { + #if ( ( configNUMBER_OF_CORES > 1 ) && ( configUSE_CORE_AFFINITY == 1 ) ) + { + /* Set the task's affinity before scheduling it. */ + pxNewTCB->uxCoreAffinityMask = tskNO_AFFINITY; + } + #endif + prvAddNewTaskToReadyList( pxNewTCB ); xReturn = pdPASS; } @@ -811,14 +1738,52 @@ static void prvAddNewTaskToReadyList( TCB_t * pxNewTCB ) PRIVILEGED_FUNCTION; xReturn = errCOULD_NOT_ALLOCATE_REQUIRED_MEMORY; } + traceRETURN_xTaskCreate( xReturn ); + return xReturn; } +/*-----------------------------------------------------------*/ + + #if ( ( configNUMBER_OF_CORES > 1 ) && ( configUSE_CORE_AFFINITY == 1 ) ) + BaseType_t xTaskCreateAffinitySet( TaskFunction_t pxTaskCode, + const char * const pcName, + const configSTACK_DEPTH_TYPE usStackDepth, + void * const pvParameters, + UBaseType_t uxPriority, + UBaseType_t uxCoreAffinityMask, + TaskHandle_t * const pxCreatedTask ) + { + TCB_t * pxNewTCB; + BaseType_t xReturn; + + traceENTER_xTaskCreateAffinitySet( pxTaskCode, pcName, usStackDepth, pvParameters, uxPriority, uxCoreAffinityMask, pxCreatedTask ); + + pxNewTCB = prvCreateTask( pxTaskCode, pcName, usStackDepth, pvParameters, uxPriority, pxCreatedTask ); + + if( pxNewTCB != NULL ) + { + /* Set the task's affinity before scheduling it. */ + pxNewTCB->uxCoreAffinityMask = uxCoreAffinityMask; + + prvAddNewTaskToReadyList( pxNewTCB ); + xReturn = pdPASS; + } + else + { + xReturn = errCOULD_NOT_ALLOCATE_REQUIRED_MEMORY; + } + + traceRETURN_xTaskCreateAffinitySet( xReturn ); + + return xReturn; + } + #endif /* #if ( ( configNUMBER_OF_CORES > 1 ) && ( configUSE_CORE_AFFINITY == 1 ) ) */ #endif /* configSUPPORT_DYNAMIC_ALLOCATION */ /*-----------------------------------------------------------*/ static void prvInitialiseNewTask( TaskFunction_t pxTaskCode, - const char * const pcName, /*lint !e971 Unqualified char types are allowed for strings and single characters only. */ + const char * const pcName, const uint32_t ulStackDepth, void * const pvParameters, UBaseType_t uxPriority, @@ -859,7 +1824,7 @@ static void prvInitialiseNewTask( TaskFunction_t pxTaskCode, #if ( portSTACK_GROWTH < 0 ) { pxTopOfStack = &( pxNewTCB->pxStack[ ulStackDepth - ( uint32_t ) 1 ] ); - pxTopOfStack = ( StackType_t * ) ( ( ( portPOINTER_SIZE_TYPE ) pxTopOfStack ) & ( ~( ( portPOINTER_SIZE_TYPE ) portBYTE_ALIGNMENT_MASK ) ) ); /*lint !e923 !e9033 !e9078 MISRA exception. Avoiding casts between pointers and integers is not practical. Size differences accounted for using portPOINTER_SIZE_TYPE type. Checked by assert(). */ + pxTopOfStack = ( StackType_t * ) ( ( ( portPOINTER_SIZE_TYPE ) pxTopOfStack ) & ( ~( ( portPOINTER_SIZE_TYPE ) portBYTE_ALIGNMENT_MASK ) ) ); /* Check the alignment of the calculated top of stack is correct. */ configASSERT( ( ( ( portPOINTER_SIZE_TYPE ) pxTopOfStack & ( portPOINTER_SIZE_TYPE ) portBYTE_ALIGNMENT_MASK ) == 0UL ) ); @@ -875,9 +1840,10 @@ static void prvInitialiseNewTask( TaskFunction_t pxTaskCode, #else /* portSTACK_GROWTH */ { pxTopOfStack = pxNewTCB->pxStack; + pxTopOfStack = ( StackType_t * ) ( ( ( ( portPOINTER_SIZE_TYPE ) pxTopOfStack ) + portBYTE_ALIGNMENT_MASK ) & ( ~( ( portPOINTER_SIZE_TYPE ) portBYTE_ALIGNMENT_MASK ) ) ); - /* Check the alignment of the stack buffer is correct. */ - configASSERT( ( ( ( portPOINTER_SIZE_TYPE ) pxNewTCB->pxStack & ( portPOINTER_SIZE_TYPE ) portBYTE_ALIGNMENT_MASK ) == 0UL ) ); + /* Check the alignment of the calculated top of stack is correct. */ + configASSERT( ( ( ( portPOINTER_SIZE_TYPE ) pxTopOfStack & ( portPOINTER_SIZE_TYPE ) portBYTE_ALIGNMENT_MASK ) == 0UL ) ); /* The other extreme of the stack space is required if stack checking is * performed. */ @@ -907,7 +1873,7 @@ static void prvInitialiseNewTask( TaskFunction_t pxTaskCode, /* Ensure the name string is terminated in the case that the string length * was greater or equal to configMAX_TASK_NAME_LEN. */ - pxNewTCB->pcTaskName[ configMAX_TASK_NAME_LEN - 1 ] = '\0'; + pxNewTCB->pcTaskName[ configMAX_TASK_NAME_LEN - 1U ] = '\0'; } else { @@ -941,7 +1907,7 @@ static void prvInitialiseNewTask( TaskFunction_t pxTaskCode, listSET_LIST_ITEM_OWNER( &( pxNewTCB->xStateListItem ), pxNewTCB ); /* Event lists are always in priority order. */ - listSET_LIST_ITEM_VALUE( &( pxNewTCB->xEventListItem ), ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) uxPriority ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */ + listSET_LIST_ITEM_VALUE( &( pxNewTCB->xEventListItem ), ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) uxPriority ); listSET_LIST_ITEM_OWNER( &( pxNewTCB->xEventListItem ), pxNewTCB ); #if ( portUSING_MPU_WRAPPERS == 1 ) @@ -1014,6 +1980,19 @@ static void prvInitialiseNewTask( TaskFunction_t pxTaskCode, } #endif /* portUSING_MPU_WRAPPERS */ + /* Initialize task state and task attributes. */ + #if ( configNUMBER_OF_CORES > 1 ) + { + pxNewTCB->xTaskRunState = taskTASK_NOT_RUNNING; + + /* Is this an idle task? */ + if( ( ( TaskFunction_t ) pxTaskCode == ( TaskFunction_t ) prvIdleTask ) || ( ( TaskFunction_t ) pxTaskCode == ( TaskFunction_t ) prvPassiveIdleTask ) ) + { + pxNewTCB->uxTaskAttributes |= taskATTRIBUTE_IS_IDLE; + } + } + #endif /* #if ( configNUMBER_OF_CORES > 1 ) */ + if( pxCreatedTask != NULL ) { /* Pass the handle out in an anonymous way. The handle can be used to @@ -1027,88 +2006,196 @@ static void prvInitialiseNewTask( TaskFunction_t pxTaskCode, } /*-----------------------------------------------------------*/ -static void prvAddNewTaskToReadyList( TCB_t * pxNewTCB ) -{ - /* Ensure interrupts don't access the task lists while the lists are being - * updated. */ - taskENTER_CRITICAL(); - { - uxCurrentNumberOfTasks++; +#if ( configNUMBER_OF_CORES == 1 ) - if( pxCurrentTCB == NULL ) + static void prvAddNewTaskToReadyList( TCB_t * pxNewTCB ) + { + /* Ensure interrupts don't access the task lists while the lists are being + * updated. */ + taskENTER_CRITICAL(); { - /* There are no other tasks, or all the other tasks are in - * the suspended state - make this the current task. */ - pxCurrentTCB = pxNewTCB; + uxCurrentNumberOfTasks++; - if( uxCurrentNumberOfTasks == ( UBaseType_t ) 1 ) + if( pxCurrentTCB == NULL ) { - /* This is the first task to be created so do the preliminary - * initialisation required. We will not recover if this call - * fails, but we will report the failure. */ - prvInitialiseTaskLists(); + /* There are no other tasks, or all the other tasks are in + * the suspended state - make this the current task. */ + pxCurrentTCB = pxNewTCB; + + if( uxCurrentNumberOfTasks == ( UBaseType_t ) 1 ) + { + /* This is the first task to be created so do the preliminary + * initialisation required. We will not recover if this call + * fails, but we will report the failure. */ + prvInitialiseTaskLists(); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } } else { - mtCOVERAGE_TEST_MARKER(); + /* If the scheduler is not already running, make this task the + * current task if it is the highest priority task to be created + * so far. */ + if( xSchedulerRunning == pdFALSE ) + { + if( pxCurrentTCB->uxPriority <= pxNewTCB->uxPriority ) + { + pxCurrentTCB = pxNewTCB; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + + uxTaskNumber++; + + #if ( configUSE_TRACE_FACILITY == 1 ) + { + /* Add a counter into the TCB for tracing only. */ + pxNewTCB->uxTCBNumber = uxTaskNumber; } + #endif /* configUSE_TRACE_FACILITY */ + traceTASK_CREATE( pxNewTCB ); + + prvAddTaskToReadyList( pxNewTCB ); + + portSETUP_TCB( pxNewTCB ); + } + taskEXIT_CRITICAL(); + + if( xSchedulerRunning != pdFALSE ) + { + /* If the created task is of a higher priority than the current task + * then it should run now. */ + taskYIELD_ANY_CORE_IF_USING_PREEMPTION( pxNewTCB ); } else { - /* If the scheduler is not already running, make this task the - * current task if it is the highest priority task to be created - * so far. */ + mtCOVERAGE_TEST_MARKER(); + } + } + +#else /* #if ( configNUMBER_OF_CORES == 1 ) */ + + static void prvAddNewTaskToReadyList( TCB_t * pxNewTCB ) + { + /* Ensure interrupts don't access the task lists while the lists are being + * updated. */ + taskENTER_CRITICAL(); + { + uxCurrentNumberOfTasks++; + if( xSchedulerRunning == pdFALSE ) { - if( pxCurrentTCB->uxPriority <= pxNewTCB->uxPriority ) + if( uxCurrentNumberOfTasks == ( UBaseType_t ) 1 ) + { + /* This is the first task to be created so do the preliminary + * initialisation required. We will not recover if this call + * fails, but we will report the failure. */ + prvInitialiseTaskLists(); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + if( ( pxNewTCB->uxTaskAttributes & taskATTRIBUTE_IS_IDLE ) != 0U ) { - pxCurrentTCB = pxNewTCB; + BaseType_t xCoreID; + + /* Check if a core is free. */ + for( xCoreID = ( BaseType_t ) 0; xCoreID < ( BaseType_t ) configNUMBER_OF_CORES; xCoreID++ ) + { + if( pxCurrentTCBs[ xCoreID ] == NULL ) + { + pxNewTCB->xTaskRunState = xCoreID; + pxCurrentTCBs[ xCoreID ] = pxNewTCB; + break; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } } else { mtCOVERAGE_TEST_MARKER(); } } - else + + uxTaskNumber++; + + #if ( configUSE_TRACE_FACILITY == 1 ) { - mtCOVERAGE_TEST_MARKER(); + /* Add a counter into the TCB for tracing only. */ + pxNewTCB->uxTCBNumber = uxTaskNumber; } - } + #endif /* configUSE_TRACE_FACILITY */ + traceTASK_CREATE( pxNewTCB ); - uxTaskNumber++; + prvAddTaskToReadyList( pxNewTCB ); - #if ( configUSE_TRACE_FACILITY == 1 ) - { - /* Add a counter into the TCB for tracing only. */ - pxNewTCB->uxTCBNumber = uxTaskNumber; + portSETUP_TCB( pxNewTCB ); + + if( xSchedulerRunning != pdFALSE ) + { + /* If the created task is of a higher priority than another + * currently running task and preemption is on then it should + * run now. */ + taskYIELD_ANY_CORE_IF_USING_PREEMPTION( pxNewTCB ); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } } - #endif /* configUSE_TRACE_FACILITY */ - traceTASK_CREATE( pxNewTCB ); + taskEXIT_CRITICAL(); + } - prvAddTaskToReadyList( pxNewTCB ); +#endif /* #if ( configNUMBER_OF_CORES == 1 ) */ +/*-----------------------------------------------------------*/ - portSETUP_TCB( pxNewTCB ); - } - taskEXIT_CRITICAL(); +#if ( ( configUSE_TRACE_FACILITY == 1 ) && ( configUSE_STATS_FORMATTING_FUNCTIONS > 0 ) ) - if( xSchedulerRunning != pdFALSE ) + static size_t prvSnprintfReturnValueToCharsWritten( int iSnprintfReturnValue, + size_t n ) { - /* If the created task is of a higher priority than the current task - * then it should run now. */ - if( pxCurrentTCB->uxPriority < pxNewTCB->uxPriority ) + size_t uxCharsWritten; + + if( iSnprintfReturnValue < 0 ) + { + /* Encoding error - Return 0 to indicate that nothing + * was written to the buffer. */ + uxCharsWritten = 0; + } + else if( iSnprintfReturnValue >= ( int ) n ) { - taskYIELD_IF_USING_PREEMPTION(); + /* This is the case when the supplied buffer is not + * large to hold the generated string. Return the + * number of characters actually written without + * counting the terminating NULL character. */ + uxCharsWritten = n - 1U; } else { - mtCOVERAGE_TEST_MARKER(); + /* Complete string was written to the buffer. */ + uxCharsWritten = ( size_t ) iSnprintfReturnValue; } + + return uxCharsWritten; } - else - { - mtCOVERAGE_TEST_MARKER(); - } -} + +#endif /* #if ( ( configUSE_TRACE_FACILITY == 1 ) && ( configUSE_STATS_FORMATTING_FUNCTIONS > 0 ) ) */ /*-----------------------------------------------------------*/ #if ( INCLUDE_vTaskDelete == 1 ) @@ -1117,6 +2204,8 @@ static void prvAddNewTaskToReadyList( TCB_t * pxNewTCB ) { TCB_t * pxTCB; + traceENTER_vTaskDelete( xTaskToDelete ); + taskENTER_CRITICAL(); { /* If null is passed in here then it is the calling task that is @@ -1149,13 +2238,17 @@ static void prvAddNewTaskToReadyList( TCB_t * pxNewTCB ) * not return. */ uxTaskNumber++; - if( pxTCB == pxCurrentTCB ) - { - /* A task is deleting itself. This cannot complete within the - * task itself, as a context switch to another task is required. - * Place the task in the termination list. The idle task will - * check the termination list and free up any memory allocated by - * the scheduler for the TCB and stack of the deleted task. */ + /* If the task is running (or yielding), we must add it to the + * termination list so that an idle task can delete it when it is + * no longer running. */ + if( taskTASK_IS_RUNNING_OR_SCHEDULED_TO_YIELD( pxTCB ) != pdFALSE ) + { + /* A running task or a task which is scheduled to yield is being + * deleted. This cannot complete when the task is still running + * on a core, as a context switch to another task is required. + * Place the task in the termination list. The idle task will check + * the termination list and free up any memory allocated by the + * scheduler for the TCB and stack of the deleted task. */ vListInsertEnd( &xTasksWaitingTermination, &( pxTCB->xStateListItem ) ); /* Increment the ucTasksDeleted variable so the idle task knows @@ -1172,7 +2265,11 @@ static void prvAddNewTaskToReadyList( TCB_t * pxNewTCB ) * after which it is not possible to yield away from this task - * hence xYieldPending is used to latch that a context switch is * required. */ - portPRE_TASK_DELETE_HOOK( pxTCB, &xYieldPending ); + #if ( configNUMBER_OF_CORES == 1 ) + portPRE_TASK_DELETE_HOOK( pxTCB, &( xYieldPendings[ 0 ] ) ); + #else + portPRE_TASK_DELETE_HOOK( pxTCB, &( xYieldPendings[ pxTCB->xTaskRunState ] ) ); + #endif } else { @@ -1184,30 +2281,63 @@ static void prvAddNewTaskToReadyList( TCB_t * pxNewTCB ) prvResetNextTaskUnblockTime(); } } - taskEXIT_CRITICAL(); - /* If the task is not deleting itself, call prvDeleteTCB from outside of - * critical section. If a task deletes itself, prvDeleteTCB is called - * from prvCheckTasksWaitingTermination which is called from Idle task. */ - if( pxTCB != pxCurrentTCB ) + #if ( configNUMBER_OF_CORES == 1 ) { - prvDeleteTCB( pxTCB ); - } + taskEXIT_CRITICAL(); - /* Force a reschedule if it is the currently running task that has just - * been deleted. */ - if( xSchedulerRunning != pdFALSE ) + /* If the task is not deleting itself, call prvDeleteTCB from outside of + * critical section. If a task deletes itself, prvDeleteTCB is called + * from prvCheckTasksWaitingTermination which is called from Idle task. */ + if( pxTCB != pxCurrentTCB ) + { + prvDeleteTCB( pxTCB ); + } + + /* Force a reschedule if it is the currently running task that has just + * been deleted. */ + if( xSchedulerRunning != pdFALSE ) + { + if( pxTCB == pxCurrentTCB ) + { + configASSERT( uxSchedulerSuspended == 0 ); + portYIELD_WITHIN_API(); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + } + #else /* #if ( configNUMBER_OF_CORES == 1 ) */ { - if( pxTCB == pxCurrentTCB ) + /* If a running task is not deleting itself, call prvDeleteTCB. If a running + * task deletes itself, prvDeleteTCB is called from prvCheckTasksWaitingTermination + * which is called from Idle task. */ + if( pxTCB->xTaskRunState == taskTASK_NOT_RUNNING ) { - configASSERT( uxSchedulerSuspended == ( UBaseType_t ) 0U ); - portYIELD_WITHIN_API(); + prvDeleteTCB( pxTCB ); } - else + + /* Force a reschedule if the task that has just been deleted was running. */ + if( ( xSchedulerRunning != pdFALSE ) && ( taskTASK_IS_RUNNING( pxTCB ) == pdTRUE ) ) { - mtCOVERAGE_TEST_MARKER(); + if( pxTCB->xTaskRunState == ( BaseType_t ) portGET_CORE_ID() ) + { + configASSERT( uxSchedulerSuspended == 0 ); + vTaskYieldWithinAPI(); + } + else + { + prvYieldCore( pxTCB->xTaskRunState ); + } } + + taskEXIT_CRITICAL(); } + #endif /* #if ( configNUMBER_OF_CORES == 1 ) */ + + traceRETURN_vTaskDelete(); } #endif /* INCLUDE_vTaskDelete */ @@ -1221,9 +2351,10 @@ static void prvAddNewTaskToReadyList( TCB_t * pxNewTCB ) TickType_t xTimeToWake; BaseType_t xAlreadyYielded, xShouldDelay = pdFALSE; + traceENTER_xTaskDelayUntil( pxPreviousWakeTime, xTimeIncrement ); + configASSERT( pxPreviousWakeTime ); configASSERT( ( xTimeIncrement > 0U ) ); - configASSERT( uxSchedulerSuspended == ( UBaseType_t ) 0U ); vTaskSuspendAll(); { @@ -1231,6 +2362,8 @@ static void prvAddNewTaskToReadyList( TCB_t * pxNewTCB ) * block. */ const TickType_t xConstTickCount = xTickCount; + configASSERT( uxSchedulerSuspended == 1U ); + /* Generate the tick time at which the task wants to wake. */ xTimeToWake = *pxPreviousWakeTime + xTimeIncrement; @@ -1287,13 +2420,15 @@ static void prvAddNewTaskToReadyList( TCB_t * pxNewTCB ) * have put ourselves to sleep. */ if( xAlreadyYielded == pdFALSE ) { - portYIELD_WITHIN_API(); + taskYIELD_WITHIN_API(); } else { mtCOVERAGE_TEST_MARKER(); } + traceRETURN_xTaskDelayUntil( xShouldDelay ); + return xShouldDelay; } @@ -1306,12 +2441,15 @@ static void prvAddNewTaskToReadyList( TCB_t * pxNewTCB ) { BaseType_t xAlreadyYielded = pdFALSE; + traceENTER_vTaskDelay( xTicksToDelay ); + /* A delay time of zero just forces a reschedule. */ if( xTicksToDelay > ( TickType_t ) 0U ) { - configASSERT( uxSchedulerSuspended == ( UBaseType_t ) 0U ); vTaskSuspendAll(); { + configASSERT( uxSchedulerSuspended == 1U ); + traceTASK_DELAY(); /* A task that is removed from the event list while the @@ -1334,12 +2472,14 @@ static void prvAddNewTaskToReadyList( TCB_t * pxNewTCB ) * have put ourselves to sleep. */ if( xAlreadyYielded == pdFALSE ) { - portYIELD_WITHIN_API(); + taskYIELD_WITHIN_API(); } else { mtCOVERAGE_TEST_MARKER(); } + + traceRETURN_vTaskDelay(); } #endif /* INCLUDE_vTaskDelay */ @@ -1356,14 +2496,18 @@ static void prvAddNewTaskToReadyList( TCB_t * pxNewTCB ) List_t const * pxOverflowedDelayedList; const TCB_t * const pxTCB = xTask; + traceENTER_eTaskGetState( xTask ); + configASSERT( pxTCB ); - if( pxTCB == pxCurrentTCB ) - { - /* The task calling this function is querying its own state. */ - eReturn = eRunning; - } - else + #if ( configNUMBER_OF_CORES == 1 ) + if( pxTCB == pxCurrentTCB ) + { + /* The task calling this function is querying its own state. */ + eReturn = eRunning; + } + else + #endif { taskENTER_CRITICAL(); { @@ -1407,7 +2551,7 @@ static void prvAddNewTaskToReadyList( TCB_t * pxNewTCB ) * suspended. */ eReturn = eSuspended; - for( x = 0; x < configTASK_NOTIFICATION_ARRAY_ENTRIES; x++ ) + for( x = ( BaseType_t ) 0; x < ( BaseType_t ) configTASK_NOTIFICATION_ARRAY_ENTRIES; x++ ) { if( pxTCB->ucNotifyState[ x ] == taskWAITING_NOTIFICATION ) { @@ -1439,16 +2583,36 @@ static void prvAddNewTaskToReadyList( TCB_t * pxNewTCB ) } #endif - else /*lint !e525 Negative indentation is intended to make use of pre-processor clearer. */ + else { - /* If the task is not in any other state, it must be in the - * Ready (including pending ready) state. */ - eReturn = eReady; + #if ( configNUMBER_OF_CORES == 1 ) + { + /* If the task is not in any other state, it must be in the + * Ready (including pending ready) state. */ + eReturn = eReady; + } + #else /* #if ( configNUMBER_OF_CORES == 1 ) */ + { + if( taskTASK_IS_RUNNING( pxTCB ) == pdTRUE ) + { + /* Is it actively running on a core? */ + eReturn = eRunning; + } + else + { + /* If the task is not in any other state, it must be in the + * Ready (including pending ready) state. */ + eReturn = eReady; + } + } + #endif /* #if ( configNUMBER_OF_CORES == 1 ) */ } } + traceRETURN_eTaskGetState( eReturn ); + return eReturn; - } /*lint !e818 xTask cannot be a pointer to const because it is a typedef. */ + } #endif /* INCLUDE_eTaskGetState */ /*-----------------------------------------------------------*/ @@ -1460,6 +2624,8 @@ static void prvAddNewTaskToReadyList( TCB_t * pxNewTCB ) TCB_t const * pxTCB; UBaseType_t uxReturn; + traceENTER_uxTaskPriorityGet( xTask ); + taskENTER_CRITICAL(); { /* If null is passed in here then it is the priority of the task @@ -1469,6 +2635,8 @@ static void prvAddNewTaskToReadyList( TCB_t * pxNewTCB ) } taskEXIT_CRITICAL(); + traceRETURN_uxTaskPriorityGet( uxReturn ); + return uxReturn; } @@ -1481,7 +2649,9 @@ static void prvAddNewTaskToReadyList( TCB_t * pxNewTCB ) { TCB_t const * pxTCB; UBaseType_t uxReturn; - UBaseType_t uxSavedInterruptState; + UBaseType_t uxSavedInterruptStatus; + + traceENTER_uxTaskPriorityGetFromISR( xTask ); /* RTOS ports that support interrupt nesting have the concept of a * maximum system call (or maximum API call) interrupt priority. @@ -1501,14 +2671,16 @@ static void prvAddNewTaskToReadyList( TCB_t * pxNewTCB ) * https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */ portASSERT_IF_INTERRUPT_PRIORITY_INVALID(); - uxSavedInterruptState = portSET_INTERRUPT_MASK_FROM_ISR(); + uxSavedInterruptStatus = taskENTER_CRITICAL_FROM_ISR(); { /* If null is passed in here then it is the priority of the calling * task that is being queried. */ pxTCB = prvGetTCBFromHandle( xTask ); uxReturn = pxTCB->uxPriority; } - portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptState ); + taskEXIT_CRITICAL_FROM_ISR( uxSavedInterruptStatus ); + + traceRETURN_uxTaskPriorityGetFromISR( uxReturn ); return uxReturn; } @@ -1516,6 +2688,77 @@ static void prvAddNewTaskToReadyList( TCB_t * pxNewTCB ) #endif /* INCLUDE_uxTaskPriorityGet */ /*-----------------------------------------------------------*/ +#if ( ( INCLUDE_uxTaskPriorityGet == 1 ) && ( configUSE_MUTEXES == 1 ) ) + + UBaseType_t uxTaskBasePriorityGet( const TaskHandle_t xTask ) + { + TCB_t const * pxTCB; + UBaseType_t uxReturn; + + traceENTER_uxTaskBasePriorityGet( xTask ); + + taskENTER_CRITICAL(); + { + /* If null is passed in here then it is the base priority of the task + * that called uxTaskBasePriorityGet() that is being queried. */ + pxTCB = prvGetTCBFromHandle( xTask ); + uxReturn = pxTCB->uxBasePriority; + } + taskEXIT_CRITICAL(); + + traceRETURN_uxTaskBasePriorityGet( uxReturn ); + + return uxReturn; + } + +#endif /* #if ( ( INCLUDE_uxTaskPriorityGet == 1 ) && ( configUSE_MUTEXES == 1 ) ) */ +/*-----------------------------------------------------------*/ + +#if ( ( INCLUDE_uxTaskPriorityGet == 1 ) && ( configUSE_MUTEXES == 1 ) ) + + UBaseType_t uxTaskBasePriorityGetFromISR( const TaskHandle_t xTask ) + { + TCB_t const * pxTCB; + UBaseType_t uxReturn; + UBaseType_t uxSavedInterruptStatus; + + traceENTER_uxTaskBasePriorityGetFromISR( xTask ); + + /* RTOS ports that support interrupt nesting have the concept of a + * maximum system call (or maximum API call) interrupt priority. + * Interrupts that are above the maximum system call priority are keep + * permanently enabled, even when the RTOS kernel is in a critical section, + * but cannot make any calls to FreeRTOS API functions. If configASSERT() + * is defined in FreeRTOSConfig.h then + * portASSERT_IF_INTERRUPT_PRIORITY_INVALID() will result in an assertion + * failure if a FreeRTOS API function is called from an interrupt that has + * been assigned a priority above the configured maximum system call + * priority. Only FreeRTOS functions that end in FromISR can be called + * from interrupts that have been assigned a priority at or (logically) + * below the maximum system call interrupt priority. FreeRTOS maintains a + * separate interrupt safe API to ensure interrupt entry is as fast and as + * simple as possible. More information (albeit Cortex-M specific) is + * provided on the following link: + * https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */ + portASSERT_IF_INTERRUPT_PRIORITY_INVALID(); + + uxSavedInterruptStatus = taskENTER_CRITICAL_FROM_ISR(); + { + /* If null is passed in here then it is the base priority of the calling + * task that is being queried. */ + pxTCB = prvGetTCBFromHandle( xTask ); + uxReturn = pxTCB->uxBasePriority; + } + taskEXIT_CRITICAL_FROM_ISR( uxSavedInterruptStatus ); + + traceRETURN_uxTaskBasePriorityGetFromISR( uxReturn ); + + return uxReturn; + } + +#endif /* #if ( ( INCLUDE_uxTaskPriorityGet == 1 ) && ( configUSE_MUTEXES == 1 ) ) */ +/*-----------------------------------------------------------*/ + #if ( INCLUDE_vTaskPrioritySet == 1 ) void vTaskPrioritySet( TaskHandle_t xTask, @@ -1525,6 +2768,12 @@ static void prvAddNewTaskToReadyList( TCB_t * pxNewTCB ) UBaseType_t uxCurrentBasePriority, uxPriorityUsedOnEntry; BaseType_t xYieldRequired = pdFALSE; + #if ( configNUMBER_OF_CORES > 1 ) + BaseType_t xYieldForTask = pdFALSE; + #endif + + traceENTER_vTaskPrioritySet( xTask, uxNewPriority ); + configASSERT( uxNewPriority < configMAX_PRIORITIES ); /* Ensure the new priority is valid. */ @@ -1558,36 +2807,51 @@ static void prvAddNewTaskToReadyList( TCB_t * pxNewTCB ) if( uxCurrentBasePriority != uxNewPriority ) { /* The priority change may have readied a task of higher - * priority than the calling task. */ + * priority than a running task. */ if( uxNewPriority > uxCurrentBasePriority ) { - if( pxTCB != pxCurrentTCB ) + #if ( configNUMBER_OF_CORES == 1 ) { - /* The priority of a task other than the currently - * running task is being raised. Is the priority being - * raised above that of the running task? */ - if( uxNewPriority > pxCurrentTCB->uxPriority ) + if( pxTCB != pxCurrentTCB ) { - xYieldRequired = pdTRUE; + /* The priority of a task other than the currently + * running task is being raised. Is the priority being + * raised above that of the running task? */ + if( uxNewPriority > pxCurrentTCB->uxPriority ) + { + xYieldRequired = pdTRUE; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } } else { - mtCOVERAGE_TEST_MARKER(); + /* The priority of the running task is being raised, + * but the running task must already be the highest + * priority task able to run so no yield is required. */ } } - else + #else /* #if ( configNUMBER_OF_CORES == 1 ) */ { - /* The priority of the running task is being raised, - * but the running task must already be the highest - * priority task able to run so no yield is required. */ + /* The priority of a task is being raised so + * perform a yield for this task later. */ + xYieldForTask = pdTRUE; } + #endif /* #if ( configNUMBER_OF_CORES == 1 ) */ } - else if( pxTCB == pxCurrentTCB ) + else if( taskTASK_IS_RUNNING( pxTCB ) == pdTRUE ) { - /* Setting the priority of the running task down means + /* Setting the priority of a running task down means * there may now be another task of higher priority that * is ready to execute. */ - xYieldRequired = pdTRUE; + #if ( configUSE_TASK_PREEMPTION_DISABLE == 1 ) + if( pxTCB->xPreemptionDisable == pdFALSE ) + #endif + { + xYieldRequired = pdTRUE; + } } else { @@ -1604,8 +2868,9 @@ static void prvAddNewTaskToReadyList( TCB_t * pxNewTCB ) #if ( configUSE_MUTEXES == 1 ) { /* Only change the priority being used if the task is not - * currently using an inherited priority. */ - if( pxTCB->uxBasePriority == pxTCB->uxPriority ) + * currently using an inherited priority or the new priority + * is bigger than the inherited priority. */ + if( ( pxTCB->uxBasePriority == pxTCB->uxPriority ) || ( uxNewPriority > pxTCB->uxPriority ) ) { pxTCB->uxPriority = uxNewPriority; } @@ -1625,9 +2890,9 @@ static void prvAddNewTaskToReadyList( TCB_t * pxNewTCB ) /* Only reset the event list item value if the value is not * being used for anything else. */ - if( ( listGET_LIST_ITEM_VALUE( &( pxTCB->xEventListItem ) ) & taskEVENT_LIST_ITEM_VALUE_IN_USE ) == 0UL ) + if( ( listGET_LIST_ITEM_VALUE( &( pxTCB->xEventListItem ) ) & taskEVENT_LIST_ITEM_VALUE_IN_USE ) == ( ( TickType_t ) 0UL ) ) { - listSET_LIST_ITEM_VALUE( &( pxTCB->xEventListItem ), ( ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) uxNewPriority ) ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */ + listSET_LIST_ITEM_VALUE( &( pxTCB->xEventListItem ), ( ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) uxNewPriority ) ); } else { @@ -1650,36 +2915,204 @@ static void prvAddNewTaskToReadyList( TCB_t * pxNewTCB ) * reset macro can be called directly. */ portRESET_READY_PRIORITY( uxPriorityUsedOnEntry, uxTopReadyPriority ); } - else + else + { + mtCOVERAGE_TEST_MARKER(); + } + + prvAddTaskToReadyList( pxTCB ); + } + else + { + #if ( configNUMBER_OF_CORES == 1 ) + { + mtCOVERAGE_TEST_MARKER(); + } + #else + { + /* It's possible that xYieldForTask was already set to pdTRUE because + * its priority is being raised. However, since it is not in a ready list + * we don't actually need to yield for it. */ + xYieldForTask = pdFALSE; + } + #endif + } + + if( xYieldRequired != pdFALSE ) + { + /* The running task priority is set down. Request the task to yield. */ + taskYIELD_TASK_CORE_IF_USING_PREEMPTION( pxTCB ); + } + else + { + #if ( configNUMBER_OF_CORES > 1 ) + if( xYieldForTask != pdFALSE ) + { + /* The priority of the task is being raised. If a running + * task has priority lower than this task, it should yield + * for this task. */ + taskYIELD_ANY_CORE_IF_USING_PREEMPTION( pxTCB ); + } + else + #endif /* if ( configNUMBER_OF_CORES > 1 ) */ + { + mtCOVERAGE_TEST_MARKER(); + } + } + + /* Remove compiler warning about unused variables when the port + * optimised task selection is not being used. */ + ( void ) uxPriorityUsedOnEntry; + } + } + taskEXIT_CRITICAL(); + + traceRETURN_vTaskPrioritySet(); + } + +#endif /* INCLUDE_vTaskPrioritySet */ +/*-----------------------------------------------------------*/ + +#if ( ( configNUMBER_OF_CORES > 1 ) && ( configUSE_CORE_AFFINITY == 1 ) ) + void vTaskCoreAffinitySet( const TaskHandle_t xTask, + UBaseType_t uxCoreAffinityMask ) + { + TCB_t * pxTCB; + BaseType_t xCoreID; + UBaseType_t uxPrevCoreAffinityMask; + + #if ( configUSE_PREEMPTION == 1 ) + UBaseType_t uxPrevNotAllowedCores; + #endif + + traceENTER_vTaskCoreAffinitySet( xTask, uxCoreAffinityMask ); + + taskENTER_CRITICAL(); + { + pxTCB = prvGetTCBFromHandle( xTask ); + + uxPrevCoreAffinityMask = pxTCB->uxCoreAffinityMask; + pxTCB->uxCoreAffinityMask = uxCoreAffinityMask; + + if( xSchedulerRunning != pdFALSE ) + { + if( taskTASK_IS_RUNNING( pxTCB ) == pdTRUE ) + { + xCoreID = ( BaseType_t ) pxTCB->xTaskRunState; + + /* If the task can no longer run on the core it was running, + * request the core to yield. */ + if( ( uxCoreAffinityMask & ( ( UBaseType_t ) 1U << ( UBaseType_t ) xCoreID ) ) == 0U ) + { + prvYieldCore( xCoreID ); + } + } + else + { + #if ( configUSE_PREEMPTION == 1 ) + { + /* Calculate the cores on which this task was not allowed to + * run previously. */ + uxPrevNotAllowedCores = ( ~uxPrevCoreAffinityMask ) & ( ( 1U << configNUMBER_OF_CORES ) - 1U ); + + /* Does the new core mask enables this task to run on any of the + * previously not allowed cores? If yes, check if this task can be + * scheduled on any of those cores. */ + if( ( uxPrevNotAllowedCores & uxCoreAffinityMask ) != 0U ) + { + prvYieldForTask( pxTCB ); + } + } + #else /* #if( configUSE_PREEMPTION == 1 ) */ { mtCOVERAGE_TEST_MARKER(); } - - prvAddTaskToReadyList( pxTCB ); - } - else - { - mtCOVERAGE_TEST_MARKER(); + #endif /* #if( configUSE_PREEMPTION == 1 ) */ } + } + } + taskEXIT_CRITICAL(); - if( xYieldRequired != pdFALSE ) - { - taskYIELD_IF_USING_PREEMPTION(); - } - else + traceRETURN_vTaskCoreAffinitySet(); + } +#endif /* #if ( ( configNUMBER_OF_CORES > 1 ) && ( configUSE_CORE_AFFINITY == 1 ) ) */ +/*-----------------------------------------------------------*/ + +#if ( ( configNUMBER_OF_CORES > 1 ) && ( configUSE_CORE_AFFINITY == 1 ) ) + UBaseType_t vTaskCoreAffinityGet( ConstTaskHandle_t xTask ) + { + const TCB_t * pxTCB; + UBaseType_t uxCoreAffinityMask; + + traceENTER_vTaskCoreAffinityGet( xTask ); + + taskENTER_CRITICAL(); + { + pxTCB = prvGetTCBFromHandle( xTask ); + uxCoreAffinityMask = pxTCB->uxCoreAffinityMask; + } + taskEXIT_CRITICAL(); + + traceRETURN_vTaskCoreAffinityGet( uxCoreAffinityMask ); + + return uxCoreAffinityMask; + } +#endif /* #if ( ( configNUMBER_OF_CORES > 1 ) && ( configUSE_CORE_AFFINITY == 1 ) ) */ + +/*-----------------------------------------------------------*/ + +#if ( configUSE_TASK_PREEMPTION_DISABLE == 1 ) + + void vTaskPreemptionDisable( const TaskHandle_t xTask ) + { + TCB_t * pxTCB; + + traceENTER_vTaskPreemptionDisable( xTask ); + + taskENTER_CRITICAL(); + { + pxTCB = prvGetTCBFromHandle( xTask ); + + pxTCB->xPreemptionDisable = pdTRUE; + } + taskEXIT_CRITICAL(); + + traceRETURN_vTaskPreemptionDisable(); + } + +#endif /* #if ( configUSE_TASK_PREEMPTION_DISABLE == 1 ) */ +/*-----------------------------------------------------------*/ + +#if ( configUSE_TASK_PREEMPTION_DISABLE == 1 ) + + void vTaskPreemptionEnable( const TaskHandle_t xTask ) + { + TCB_t * pxTCB; + BaseType_t xCoreID; + + traceENTER_vTaskPreemptionEnable( xTask ); + + taskENTER_CRITICAL(); + { + pxTCB = prvGetTCBFromHandle( xTask ); + + pxTCB->xPreemptionDisable = pdFALSE; + + if( xSchedulerRunning != pdFALSE ) + { + if( taskTASK_IS_RUNNING( pxTCB ) == pdTRUE ) { - mtCOVERAGE_TEST_MARKER(); + xCoreID = ( BaseType_t ) pxTCB->xTaskRunState; + prvYieldCore( xCoreID ); } - - /* Remove compiler warning about unused variables when the port - * optimised task selection is not being used. */ - ( void ) uxPriorityUsedOnEntry; } } taskEXIT_CRITICAL(); + + traceRETURN_vTaskPreemptionEnable(); } -#endif /* INCLUDE_vTaskPrioritySet */ +#endif /* #if ( configUSE_TASK_PREEMPTION_DISABLE == 1 ) */ /*-----------------------------------------------------------*/ #if ( INCLUDE_vTaskSuspend == 1 ) @@ -1688,6 +3121,12 @@ static void prvAddNewTaskToReadyList( TCB_t * pxNewTCB ) { TCB_t * pxTCB; + #if ( configNUMBER_OF_CORES > 1 ) + BaseType_t xTaskRunningOnCore; + #endif + + traceENTER_vTaskSuspend( xTaskToSuspend ); + taskENTER_CRITICAL(); { /* If null is passed in here then it is the running task that is @@ -1696,6 +3135,10 @@ static void prvAddNewTaskToReadyList( TCB_t * pxNewTCB ) traceTASK_SUSPEND( pxTCB ); + #if ( configNUMBER_OF_CORES > 1 ) + xTaskRunningOnCore = pxTCB->xTaskRunState; + #endif + /* Remove task from the ready/delayed list and place in the * suspended list. */ if( uxListRemove( &( pxTCB->xStateListItem ) ) == ( UBaseType_t ) 0 ) @@ -1723,7 +3166,7 @@ static void prvAddNewTaskToReadyList( TCB_t * pxNewTCB ) { BaseType_t x; - for( x = 0; x < configTASK_NOTIFICATION_ARRAY_ENTRIES; x++ ) + for( x = ( BaseType_t ) 0; x < ( BaseType_t ) configTASK_NOTIFICATION_ARRAY_ENTRIES; x++ ) { if( pxTCB->ucNotifyState[ x ] == taskWAITING_NOTIFICATION ) { @@ -1735,54 +3178,106 @@ static void prvAddNewTaskToReadyList( TCB_t * pxNewTCB ) } #endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */ } - taskEXIT_CRITICAL(); - if( xSchedulerRunning != pdFALSE ) + #if ( configNUMBER_OF_CORES == 1 ) { - /* Reset the next expected unblock time in case it referred to the - * task that is now in the Suspended state. */ - taskENTER_CRITICAL(); - { - prvResetNextTaskUnblockTime(); - } taskEXIT_CRITICAL(); - } - else - { - mtCOVERAGE_TEST_MARKER(); - } - if( pxTCB == pxCurrentTCB ) - { if( xSchedulerRunning != pdFALSE ) { - /* The current task has just been suspended. */ - configASSERT( uxSchedulerSuspended == ( UBaseType_t ) 0U ); - portYIELD_WITHIN_API(); + /* Reset the next expected unblock time in case it referred to the + * task that is now in the Suspended state. */ + taskENTER_CRITICAL(); + { + prvResetNextTaskUnblockTime(); + } + taskEXIT_CRITICAL(); } else { - /* The scheduler is not running, but the task that was pointed - * to by pxCurrentTCB has just been suspended and pxCurrentTCB - * must be adjusted to point to a different task. */ - if( listCURRENT_LIST_LENGTH( &xSuspendedTaskList ) == uxCurrentNumberOfTasks ) /*lint !e931 Right has no side effect, just volatile. */ + mtCOVERAGE_TEST_MARKER(); + } + + if( pxTCB == pxCurrentTCB ) + { + if( xSchedulerRunning != pdFALSE ) { - /* No other tasks are ready, so set pxCurrentTCB back to - * NULL so when the next task is created pxCurrentTCB will - * be set to point to it no matter what its relative priority - * is. */ - pxCurrentTCB = NULL; + /* The current task has just been suspended. */ + configASSERT( uxSchedulerSuspended == 0 ); + portYIELD_WITHIN_API(); } else { - vTaskSwitchContext(); + /* The scheduler is not running, but the task that was pointed + * to by pxCurrentTCB has just been suspended and pxCurrentTCB + * must be adjusted to point to a different task. */ + if( listCURRENT_LIST_LENGTH( &xSuspendedTaskList ) == uxCurrentNumberOfTasks ) + { + /* No other tasks are ready, so set pxCurrentTCB back to + * NULL so when the next task is created pxCurrentTCB will + * be set to point to it no matter what its relative priority + * is. */ + pxCurrentTCB = NULL; + } + else + { + vTaskSwitchContext(); + } } } + else + { + mtCOVERAGE_TEST_MARKER(); + } } - else + #else /* #if ( configNUMBER_OF_CORES == 1 ) */ { - mtCOVERAGE_TEST_MARKER(); + if( xSchedulerRunning != pdFALSE ) + { + /* Reset the next expected unblock time in case it referred to the + * task that is now in the Suspended state. */ + prvResetNextTaskUnblockTime(); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + if( taskTASK_IS_RUNNING( pxTCB ) == pdTRUE ) + { + if( xSchedulerRunning != pdFALSE ) + { + if( xTaskRunningOnCore == ( BaseType_t ) portGET_CORE_ID() ) + { + /* The current task has just been suspended. */ + configASSERT( uxSchedulerSuspended == 0 ); + vTaskYieldWithinAPI(); + } + else + { + prvYieldCore( xTaskRunningOnCore ); + } + } + else + { + /* This code path is not possible because only Idle tasks are + * assigned a core before the scheduler is started ( i.e. + * taskTASK_IS_RUNNING is only true for idle tasks before + * the scheduler is started ) and idle tasks cannot be + * suspended. */ + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + taskEXIT_CRITICAL(); } + #endif /* #if ( configNUMBER_OF_CORES == 1 ) */ + + traceRETURN_vTaskSuspend(); } #endif /* INCLUDE_vTaskSuspend */ @@ -1808,10 +3303,34 @@ static void prvAddNewTaskToReadyList( TCB_t * pxNewTCB ) if( listIS_CONTAINED_WITHIN( &xPendingReadyList, &( pxTCB->xEventListItem ) ) == pdFALSE ) { /* Is it in the suspended list because it is in the Suspended - * state, or because is is blocked with no timeout? */ - if( listIS_CONTAINED_WITHIN( NULL, &( pxTCB->xEventListItem ) ) != pdFALSE ) /*lint !e961. The cast is only redundant when NULL is used. */ + * state, or because it is blocked with no timeout? */ + if( listIS_CONTAINED_WITHIN( NULL, &( pxTCB->xEventListItem ) ) != pdFALSE ) { - xReturn = pdTRUE; + #if ( configUSE_TASK_NOTIFICATIONS == 1 ) + { + BaseType_t x; + + /* The task does not appear on the event list item of + * and of the RTOS objects, but could still be in the + * blocked state if it is waiting on its notification + * rather than waiting on an object. If not, is + * suspended. */ + xReturn = pdTRUE; + + for( x = ( BaseType_t ) 0; x < ( BaseType_t ) configTASK_NOTIFICATION_ARRAY_ENTRIES; x++ ) + { + if( pxTCB->ucNotifyState[ x ] == taskWAITING_NOTIFICATION ) + { + xReturn = pdFALSE; + break; + } + } + } + #else /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */ + { + xReturn = pdTRUE; + } + #endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */ } else { @@ -1829,7 +3348,7 @@ static void prvAddNewTaskToReadyList( TCB_t * pxNewTCB ) } return xReturn; - } /*lint !e818 xTask cannot be a pointer to const because it is a typedef. */ + } #endif /* INCLUDE_vTaskSuspend */ /*-----------------------------------------------------------*/ @@ -1840,12 +3359,25 @@ static void prvAddNewTaskToReadyList( TCB_t * pxNewTCB ) { TCB_t * const pxTCB = xTaskToResume; + traceENTER_vTaskResume( xTaskToResume ); + /* It does not make sense to resume the calling task. */ configASSERT( xTaskToResume ); - /* The parameter cannot be NULL as it is impossible to resume the - * currently executing task. */ - if( ( pxTCB != pxCurrentTCB ) && ( pxTCB != NULL ) ) + #if ( configNUMBER_OF_CORES == 1 ) + + /* The parameter cannot be NULL as it is impossible to resume the + * currently executing task. */ + if( ( pxTCB != pxCurrentTCB ) && ( pxTCB != NULL ) ) + #else + + /* The parameter cannot be NULL as it is impossible to resume the + * currently executing task. It is also impossible to resume a task + * that is actively running on another core but it is not safe + * to check their run state here. Therefore, we get into a critical + * section and check if the task is actually suspended or not. */ + if( pxTCB != NULL ) + #endif { taskENTER_CRITICAL(); { @@ -1858,18 +3390,10 @@ static void prvAddNewTaskToReadyList( TCB_t * pxNewTCB ) ( void ) uxListRemove( &( pxTCB->xStateListItem ) ); prvAddTaskToReadyList( pxTCB ); - /* A higher priority task may have just been resumed. */ - if( pxTCB->uxPriority > pxCurrentTCB->uxPriority ) - { - /* This yield may not cause the task just resumed to run, - * but will leave the lists in the correct state for the - * next yield. */ - taskYIELD_IF_USING_PREEMPTION(); - } - else - { - mtCOVERAGE_TEST_MARKER(); - } + /* This yield may not cause the task just resumed to run, + * but will leave the lists in the correct state for the + * next yield. */ + taskYIELD_ANY_CORE_IF_USING_PREEMPTION( pxTCB ); } else { @@ -1882,6 +3406,8 @@ static void prvAddNewTaskToReadyList( TCB_t * pxNewTCB ) { mtCOVERAGE_TEST_MARKER(); } + + traceRETURN_vTaskResume(); } #endif /* INCLUDE_vTaskSuspend */ @@ -1896,6 +3422,8 @@ static void prvAddNewTaskToReadyList( TCB_t * pxNewTCB ) TCB_t * const pxTCB = xTaskToResume; UBaseType_t uxSavedInterruptStatus; + traceENTER_xTaskResumeFromISR( xTaskToResume ); + configASSERT( xTaskToResume ); /* RTOS ports that support interrupt nesting have the concept of a @@ -1916,7 +3444,7 @@ static void prvAddNewTaskToReadyList( TCB_t * pxNewTCB ) * https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */ portASSERT_IF_INTERRUPT_PRIORITY_INVALID(); - uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR(); + uxSavedInterruptStatus = taskENTER_CRITICAL_FROM_ISR(); { if( prvTaskIsTaskSuspended( pxTCB ) != pdFALSE ) { @@ -1925,21 +3453,25 @@ static void prvAddNewTaskToReadyList( TCB_t * pxNewTCB ) /* Check the ready lists can be accessed. */ if( uxSchedulerSuspended == ( UBaseType_t ) 0U ) { - /* Ready lists can be accessed so move the task from the - * suspended list to the ready list directly. */ - if( pxTCB->uxPriority > pxCurrentTCB->uxPriority ) + #if ( configNUMBER_OF_CORES == 1 ) { - xYieldRequired = pdTRUE; + /* Ready lists can be accessed so move the task from the + * suspended list to the ready list directly. */ + if( pxTCB->uxPriority > pxCurrentTCB->uxPriority ) + { + xYieldRequired = pdTRUE; - /* Mark that a yield is pending in case the user is not - * using the return value to initiate a context switch - * from the ISR using portYIELD_FROM_ISR. */ - xYieldPending = pdTRUE; - } - else - { - mtCOVERAGE_TEST_MARKER(); + /* Mark that a yield is pending in case the user is not + * using the return value to initiate a context switch + * from the ISR using the port specific portYIELD_FROM_ISR(). */ + xYieldPendings[ 0 ] = pdTRUE; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } } + #endif /* #if ( configNUMBER_OF_CORES == 1 ) */ ( void ) uxListRemove( &( pxTCB->xStateListItem ) ); prvAddTaskToReadyList( pxTCB ); @@ -1951,62 +3483,192 @@ static void prvAddNewTaskToReadyList( TCB_t * pxNewTCB ) * unsuspended. */ vListInsertEnd( &( xPendingReadyList ), &( pxTCB->xEventListItem ) ); } + + #if ( ( configNUMBER_OF_CORES > 1 ) && ( configUSE_PREEMPTION == 1 ) ) + { + prvYieldForTask( pxTCB ); + + if( xYieldPendings[ portGET_CORE_ID() ] != pdFALSE ) + { + xYieldRequired = pdTRUE; + } + } + #endif /* #if ( ( configNUMBER_OF_CORES > 1 ) && ( configUSE_PREEMPTION == 1 ) ) */ + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + taskEXIT_CRITICAL_FROM_ISR( uxSavedInterruptStatus ); + + traceRETURN_xTaskResumeFromISR( xYieldRequired ); + + return xYieldRequired; + } + +#endif /* ( ( INCLUDE_xTaskResumeFromISR == 1 ) && ( INCLUDE_vTaskSuspend == 1 ) ) */ +/*-----------------------------------------------------------*/ + +static BaseType_t prvCreateIdleTasks( void ) +{ + BaseType_t xReturn = pdPASS; + BaseType_t xCoreID; + char cIdleName[ configMAX_TASK_NAME_LEN ]; + TaskFunction_t pxIdleTaskFunction = NULL; + BaseType_t xIdleTaskNameIndex; + + for( xIdleTaskNameIndex = ( BaseType_t ) 0; xIdleTaskNameIndex < ( BaseType_t ) configMAX_TASK_NAME_LEN; xIdleTaskNameIndex++ ) + { + cIdleName[ xIdleTaskNameIndex ] = configIDLE_TASK_NAME[ xIdleTaskNameIndex ]; + + /* Don't copy all configMAX_TASK_NAME_LEN if the string is shorter than + * configMAX_TASK_NAME_LEN characters just in case the memory after the + * string is not accessible (extremely unlikely). */ + if( cIdleName[ xIdleTaskNameIndex ] == ( char ) 0x00 ) + { + break; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + + /* Add each idle task at the lowest priority. */ + for( xCoreID = ( BaseType_t ) 0; xCoreID < ( BaseType_t ) configNUMBER_OF_CORES; xCoreID++ ) + { + #if ( configNUMBER_OF_CORES == 1 ) + { + pxIdleTaskFunction = prvIdleTask; + } + #else /* #if ( configNUMBER_OF_CORES == 1 ) */ + { + /* In the FreeRTOS SMP, configNUMBER_OF_CORES - 1 passive idle tasks + * are also created to ensure that each core has an idle task to + * run when no other task is available to run. */ + if( xCoreID == 0 ) + { + pxIdleTaskFunction = prvIdleTask; + } + else + { + pxIdleTaskFunction = prvPassiveIdleTask; + } + } + #endif /* #if ( configNUMBER_OF_CORES == 1 ) */ + + /* Update the idle task name with suffix to differentiate the idle tasks. + * This function is not required in single core FreeRTOS since there is + * only one idle task. */ + #if ( configNUMBER_OF_CORES > 1 ) + { + /* Append the idle task number to the end of the name if there is space. */ + if( xIdleTaskNameIndex < ( BaseType_t ) configMAX_TASK_NAME_LEN ) + { + cIdleName[ xIdleTaskNameIndex ] = ( char ) ( xCoreID + '0' ); + + /* And append a null character if there is space. */ + if( ( xIdleTaskNameIndex + 1 ) < ( BaseType_t ) configMAX_TASK_NAME_LEN ) + { + cIdleName[ xIdleTaskNameIndex + 1 ] = '\0'; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } } else { mtCOVERAGE_TEST_MARKER(); } } - portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus ); - - return xYieldRequired; + #endif /* if ( configNUMBER_OF_CORES > 1 ) */ + + #if ( configSUPPORT_STATIC_ALLOCATION == 1 ) + { + StaticTask_t * pxIdleTaskTCBBuffer = NULL; + StackType_t * pxIdleTaskStackBuffer = NULL; + uint32_t ulIdleTaskStackSize; + + /* The Idle task is created using user provided RAM - obtain the + * address of the RAM then create the idle task. */ + #if ( configNUMBER_OF_CORES == 1 ) + { + vApplicationGetIdleTaskMemory( &pxIdleTaskTCBBuffer, &pxIdleTaskStackBuffer, &ulIdleTaskStackSize ); + } + #else + { + if( xCoreID == 0 ) + { + vApplicationGetIdleTaskMemory( &pxIdleTaskTCBBuffer, &pxIdleTaskStackBuffer, &ulIdleTaskStackSize ); + } + else + { + vApplicationGetPassiveIdleTaskMemory( &pxIdleTaskTCBBuffer, &pxIdleTaskStackBuffer, &ulIdleTaskStackSize, xCoreID - 1 ); + } + } + #endif /* if ( configNUMBER_OF_CORES == 1 ) */ + xIdleTaskHandles[ xCoreID ] = xTaskCreateStatic( pxIdleTaskFunction, + cIdleName, + ulIdleTaskStackSize, + ( void * ) NULL, + portPRIVILEGE_BIT, /* In effect ( tskIDLE_PRIORITY | portPRIVILEGE_BIT ), but tskIDLE_PRIORITY is zero. */ + pxIdleTaskStackBuffer, + pxIdleTaskTCBBuffer ); + + if( xIdleTaskHandles[ xCoreID ] != NULL ) + { + xReturn = pdPASS; + } + else + { + xReturn = pdFAIL; + } + } + #else /* if ( configSUPPORT_STATIC_ALLOCATION == 1 ) */ + { + /* The Idle task is being created using dynamically allocated RAM. */ + xReturn = xTaskCreate( pxIdleTaskFunction, + cIdleName, + configMINIMAL_STACK_SIZE, + ( void * ) NULL, + portPRIVILEGE_BIT, /* In effect ( tskIDLE_PRIORITY | portPRIVILEGE_BIT ), but tskIDLE_PRIORITY is zero. */ + &xIdleTaskHandles[ xCoreID ] ); + } + #endif /* configSUPPORT_STATIC_ALLOCATION */ + + /* Break the loop if any of the idle task is failed to be created. */ + if( xReturn == pdFAIL ) + { + break; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } } -#endif /* ( ( INCLUDE_xTaskResumeFromISR == 1 ) && ( INCLUDE_vTaskSuspend == 1 ) ) */ + return xReturn; +} + /*-----------------------------------------------------------*/ void vTaskStartScheduler( void ) { BaseType_t xReturn; - /* Add the idle task at the lowest priority. */ - #if ( configSUPPORT_STATIC_ALLOCATION == 1 ) - { - StaticTask_t * pxIdleTaskTCBBuffer = NULL; - StackType_t * pxIdleTaskStackBuffer = NULL; - uint32_t ulIdleTaskStackSize; - - /* The Idle task is created using user provided RAM - obtain the - * address of the RAM then create the idle task. */ - vApplicationGetIdleTaskMemory( &pxIdleTaskTCBBuffer, &pxIdleTaskStackBuffer, &ulIdleTaskStackSize ); - xIdleTaskHandle = xTaskCreateStatic( prvIdleTask, - configIDLE_TASK_NAME, - ulIdleTaskStackSize, - ( void * ) NULL, /*lint !e961. The cast is not redundant for all compilers. */ - portPRIVILEGE_BIT, /* In effect ( tskIDLE_PRIORITY | portPRIVILEGE_BIT ), but tskIDLE_PRIORITY is zero. */ - pxIdleTaskStackBuffer, - pxIdleTaskTCBBuffer ); /*lint !e961 MISRA exception, justified as it is not a redundant explicit cast to all supported compilers. */ + traceENTER_vTaskStartScheduler(); - if( xIdleTaskHandle != NULL ) - { - xReturn = pdPASS; - } - else - { - xReturn = pdFAIL; - } - } - #else /* if ( configSUPPORT_STATIC_ALLOCATION == 1 ) */ + #if ( configUSE_CORE_AFFINITY == 1 ) && ( configNUMBER_OF_CORES > 1 ) { - /* The Idle task is being created using dynamically allocated RAM. */ - xReturn = xTaskCreate( prvIdleTask, - configIDLE_TASK_NAME, - configMINIMAL_STACK_SIZE, - ( void * ) NULL, - portPRIVILEGE_BIT, /* In effect ( tskIDLE_PRIORITY | portPRIVILEGE_BIT ), but tskIDLE_PRIORITY is zero. */ - &xIdleTaskHandle ); /*lint !e961 MISRA exception, justified as it is not a redundant explicit cast to all supported compilers. */ + /* Sanity check that the UBaseType_t must have greater than or equal to + * the number of bits as confNUMBER_OF_CORES. */ + configASSERT( ( sizeof( UBaseType_t ) * taskBITS_PER_BYTE ) >= configNUMBER_OF_CORES ); } - #endif /* configSUPPORT_STATIC_ALLOCATION */ + #endif /* #if ( configUSE_CORE_AFFINITY == 1 ) && ( configNUMBER_OF_CORES > 1 ) */ + + xReturn = prvCreateIdleTasks(); #if ( configUSE_TIMERS == 1 ) { @@ -2063,7 +3725,10 @@ void vTaskStartScheduler( void ) /* Setting up the timer tick is hardware specific and thus in the * portable interface. */ - xPortStartScheduler(); + + /* The return value for xPortStartScheduler is not required + * hence using a void datatype. */ + ( void ) xPortStartScheduler(); /* In most cases, xPortStartScheduler() will not return. If it * returns pdTRUE then there was not enough heap memory available @@ -2081,45 +3746,115 @@ void vTaskStartScheduler( void ) } /* Prevent compiler warnings if INCLUDE_xTaskGetIdleTaskHandle is set to 0, - * meaning xIdleTaskHandle is not used anywhere else. */ - ( void ) xIdleTaskHandle; + * meaning xIdleTaskHandles are not used anywhere else. */ + ( void ) xIdleTaskHandles; /* OpenOCD makes use of uxTopUsedPriority for thread debugging. Prevent uxTopUsedPriority * from getting optimized out as it is no longer used by the kernel. */ ( void ) uxTopUsedPriority; + + traceRETURN_vTaskStartScheduler(); } /*-----------------------------------------------------------*/ void vTaskEndScheduler( void ) { + traceENTER_vTaskEndScheduler(); + /* Stop the scheduler interrupts and call the portable scheduler end * routine so the original ISRs can be restored if necessary. The port * layer must ensure interrupts enable bit is left in the correct state. */ portDISABLE_INTERRUPTS(); xSchedulerRunning = pdFALSE; vPortEndScheduler(); + + traceRETURN_vTaskEndScheduler(); } /*----------------------------------------------------------*/ void vTaskSuspendAll( void ) { - /* A critical section is not required as the variable is of type - * BaseType_t. Please read Richard Barry's reply in the following link to a - * post in the FreeRTOS support forum before reporting this as a bug! - - * https://goo.gl/wu4acr */ - - /* portSOFTWARE_BARRIER() is only implemented for emulated/simulated ports that - * do not otherwise exhibit real time behaviour. */ - portSOFTWARE_BARRIER(); - - /* The scheduler is suspended if uxSchedulerSuspended is non-zero. An increment - * is used to allow calls to vTaskSuspendAll() to nest. */ - ++uxSchedulerSuspended; - - /* Enforces ordering for ports and optimised compilers that may otherwise place - * the above increment elsewhere. */ - portMEMORY_BARRIER(); + traceENTER_vTaskSuspendAll(); + + #if ( configNUMBER_OF_CORES == 1 ) + { + /* A critical section is not required as the variable is of type + * BaseType_t. Please read Richard Barry's reply in the following link to a + * post in the FreeRTOS support forum before reporting this as a bug! - + * https://goo.gl/wu4acr */ + + /* portSOFTWARE_BARRIER() is only implemented for emulated/simulated ports that + * do not otherwise exhibit real time behaviour. */ + portSOFTWARE_BARRIER(); + + /* The scheduler is suspended if uxSchedulerSuspended is non-zero. An increment + * is used to allow calls to vTaskSuspendAll() to nest. */ + ++uxSchedulerSuspended; + + /* Enforces ordering for ports and optimised compilers that may otherwise place + * the above increment elsewhere. */ + portMEMORY_BARRIER(); + } + #else /* #if ( configNUMBER_OF_CORES == 1 ) */ + { + UBaseType_t ulState; + + /* This must only be called from within a task. */ + portASSERT_IF_IN_ISR(); + + if( xSchedulerRunning != pdFALSE ) + { + /* Writes to uxSchedulerSuspended must be protected by both the task AND ISR locks. + * We must disable interrupts before we grab the locks in the event that this task is + * interrupted and switches context before incrementing uxSchedulerSuspended. + * It is safe to re-enable interrupts after releasing the ISR lock and incrementing + * uxSchedulerSuspended since that will prevent context switches. */ + ulState = portSET_INTERRUPT_MASK(); + + /* portSOFRWARE_BARRIER() is only implemented for emulated/simulated ports that + * do not otherwise exhibit real time behaviour. */ + portSOFTWARE_BARRIER(); + + portGET_TASK_LOCK(); + + /* uxSchedulerSuspended is increased after prvCheckForRunStateChange. The + * purpose is to prevent altering the variable when fromISR APIs are readying + * it. */ + if( uxSchedulerSuspended == 0U ) + { + if( portGET_CRITICAL_NESTING_COUNT() == 0U ) + { + prvCheckForRunStateChange(); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + portGET_ISR_LOCK(); + + /* The scheduler is suspended if uxSchedulerSuspended is non-zero. An increment + * is used to allow calls to vTaskSuspendAll() to nest. */ + ++uxSchedulerSuspended; + portRELEASE_ISR_LOCK(); + + portCLEAR_INTERRUPT_MASK( ulState ); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + #endif /* #if ( configNUMBER_OF_CORES == 1 ) */ + + traceRETURN_vTaskSuspendAll(); } + /*----------------------------------------------------------*/ #if ( configUSE_TICKLESS_IDLE != 0 ) @@ -2160,7 +3895,7 @@ void vTaskSuspendAll( void ) { xReturn = 0; } - else if( listCURRENT_LIST_LENGTH( &( pxReadyTasksLists[ tskIDLE_PRIORITY ] ) ) > 1 ) + else if( listCURRENT_LIST_LENGTH( &( pxReadyTasksLists[ tskIDLE_PRIORITY ] ) ) > 1U ) { /* There are other idle priority tasks in the ready state. If * time slicing is used then the very next tick interrupt must be @@ -2176,7 +3911,8 @@ void vTaskSuspendAll( void ) } else { - xReturn = xNextTaskUnblockTime - xTickCount; + xReturn = xNextTaskUnblockTime; + xReturn -= xTickCount; } return xReturn; @@ -2190,108 +3926,146 @@ BaseType_t xTaskResumeAll( void ) TCB_t * pxTCB = NULL; BaseType_t xAlreadyYielded = pdFALSE; - /* If uxSchedulerSuspended is zero then this function does not match a - * previous call to vTaskSuspendAll(). */ - configASSERT( uxSchedulerSuspended != ( UBaseType_t ) 0U ); + traceENTER_xTaskResumeAll(); - /* It is possible that an ISR caused a task to be removed from an event - * list while the scheduler was suspended. If this was the case then the - * removed task will have been added to the xPendingReadyList. Once the - * scheduler has been resumed it is safe to move all the pending ready - * tasks from this list into their appropriate ready list. */ - taskENTER_CRITICAL(); + #if ( configNUMBER_OF_CORES > 1 ) + if( xSchedulerRunning != pdFALSE ) + #endif { - --uxSchedulerSuspended; - - if( uxSchedulerSuspended == ( UBaseType_t ) 0U ) + /* It is possible that an ISR caused a task to be removed from an event + * list while the scheduler was suspended. If this was the case then the + * removed task will have been added to the xPendingReadyList. Once the + * scheduler has been resumed it is safe to move all the pending ready + * tasks from this list into their appropriate ready list. */ + taskENTER_CRITICAL(); { - if( uxCurrentNumberOfTasks > ( UBaseType_t ) 0U ) - { - /* Move any readied tasks from the pending list into the - * appropriate ready list. */ - while( listLIST_IS_EMPTY( &xPendingReadyList ) == pdFALSE ) - { - pxTCB = listGET_OWNER_OF_HEAD_ENTRY( ( &xPendingReadyList ) ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */ - listREMOVE_ITEM( &( pxTCB->xEventListItem ) ); - portMEMORY_BARRIER(); - listREMOVE_ITEM( &( pxTCB->xStateListItem ) ); - prvAddTaskToReadyList( pxTCB ); + BaseType_t xCoreID; + xCoreID = ( BaseType_t ) portGET_CORE_ID(); - /* If the moved task has a priority higher than the current - * task then a yield must be performed. */ - if( pxTCB->uxPriority > pxCurrentTCB->uxPriority ) - { - xYieldPending = pdTRUE; - } - else - { - mtCOVERAGE_TEST_MARKER(); - } - } + /* If uxSchedulerSuspended is zero then this function does not match a + * previous call to vTaskSuspendAll(). */ + configASSERT( uxSchedulerSuspended != 0U ); - if( pxTCB != NULL ) - { - /* A task was unblocked while the scheduler was suspended, - * which may have prevented the next unblock time from being - * re-calculated, in which case re-calculate it now. Mainly - * important for low power tickless implementations, where - * this can prevent an unnecessary exit from low power - * state. */ - prvResetNextTaskUnblockTime(); - } + --uxSchedulerSuspended; + portRELEASE_TASK_LOCK(); - /* If any ticks occurred while the scheduler was suspended then - * they should be processed now. This ensures the tick count does - * not slip, and that any delayed tasks are resumed at the correct - * time. */ + if( uxSchedulerSuspended == ( UBaseType_t ) 0U ) + { + if( uxCurrentNumberOfTasks > ( UBaseType_t ) 0U ) { - TickType_t xPendedCounts = xPendedTicks; /* Non-volatile copy. */ - - if( xPendedCounts > ( TickType_t ) 0U ) + /* Move any readied tasks from the pending list into the + * appropriate ready list. */ + while( listLIST_IS_EMPTY( &xPendingReadyList ) == pdFALSE ) { - do + /* MISRA Ref 11.5.3 [Void pointer assignment] */ + /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-115 */ + /* coverity[misra_c_2012_rule_11_5_violation] */ + pxTCB = listGET_OWNER_OF_HEAD_ENTRY( ( &xPendingReadyList ) ); + listREMOVE_ITEM( &( pxTCB->xEventListItem ) ); + portMEMORY_BARRIER(); + listREMOVE_ITEM( &( pxTCB->xStateListItem ) ); + prvAddTaskToReadyList( pxTCB ); + + #if ( configNUMBER_OF_CORES == 1 ) { - if( xTaskIncrementTick() != pdFALSE ) + /* If the moved task has a priority higher than the current + * task then a yield must be performed. */ + if( pxTCB->uxPriority > pxCurrentTCB->uxPriority ) { - xYieldPending = pdTRUE; + xYieldPendings[ xCoreID ] = pdTRUE; } else { mtCOVERAGE_TEST_MARKER(); } + } + #else /* #if ( configNUMBER_OF_CORES == 1 ) */ + { + /* All appropriate tasks yield at the moment a task is added to xPendingReadyList. + * If the current core yielded then vTaskSwitchContext() has already been called + * which sets xYieldPendings for the current core to pdTRUE. */ + } + #endif /* #if ( configNUMBER_OF_CORES == 1 ) */ + } - --xPendedCounts; - } while( xPendedCounts > ( TickType_t ) 0U ); - - xPendedTicks = 0; + if( pxTCB != NULL ) + { + /* A task was unblocked while the scheduler was suspended, + * which may have prevented the next unblock time from being + * re-calculated, in which case re-calculate it now. Mainly + * important for low power tickless implementations, where + * this can prevent an unnecessary exit from low power + * state. */ + prvResetNextTaskUnblockTime(); } - else + + /* If any ticks occurred while the scheduler was suspended then + * they should be processed now. This ensures the tick count does + * not slip, and that any delayed tasks are resumed at the correct + * time. + * + * It should be safe to call xTaskIncrementTick here from any core + * since we are in a critical section and xTaskIncrementTick itself + * protects itself within a critical section. Suspending the scheduler + * from any core causes xTaskIncrementTick to increment uxPendedCounts. */ { - mtCOVERAGE_TEST_MARKER(); + TickType_t xPendedCounts = xPendedTicks; /* Non-volatile copy. */ + + if( xPendedCounts > ( TickType_t ) 0U ) + { + do + { + if( xTaskIncrementTick() != pdFALSE ) + { + /* Other cores are interrupted from + * within xTaskIncrementTick(). */ + xYieldPendings[ xCoreID ] = pdTRUE; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + --xPendedCounts; + } while( xPendedCounts > ( TickType_t ) 0U ); + + xPendedTicks = 0; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } } - } - if( xYieldPending != pdFALSE ) - { - #if ( configUSE_PREEMPTION != 0 ) + if( xYieldPendings[ xCoreID ] != pdFALSE ) { - xAlreadyYielded = pdTRUE; + #if ( configUSE_PREEMPTION != 0 ) + { + xAlreadyYielded = pdTRUE; + } + #endif /* #if ( configUSE_PREEMPTION != 0 ) */ + + #if ( configNUMBER_OF_CORES == 1 ) + { + taskYIELD_TASK_CORE_IF_USING_PREEMPTION( pxCurrentTCB ); + } + #endif /* #if ( configNUMBER_OF_CORES == 1 ) */ + } + else + { + mtCOVERAGE_TEST_MARKER(); } - #endif - taskYIELD_IF_USING_PREEMPTION(); - } - else - { - mtCOVERAGE_TEST_MARKER(); } } + else + { + mtCOVERAGE_TEST_MARKER(); + } } - else - { - mtCOVERAGE_TEST_MARKER(); - } + taskEXIT_CRITICAL(); } - taskEXIT_CRITICAL(); + + traceRETURN_xTaskResumeAll( xAlreadyYielded ); return xAlreadyYielded; } @@ -2301,6 +4075,8 @@ TickType_t xTaskGetTickCount( void ) { TickType_t xTicks; + traceENTER_xTaskGetTickCount(); + /* Critical section required if running on a 16 bit processor. */ portTICK_TYPE_ENTER_CRITICAL(); { @@ -2308,6 +4084,8 @@ TickType_t xTaskGetTickCount( void ) } portTICK_TYPE_EXIT_CRITICAL(); + traceRETURN_xTaskGetTickCount( xTicks ); + return xTicks; } /*-----------------------------------------------------------*/ @@ -2317,6 +4095,8 @@ TickType_t xTaskGetTickCountFromISR( void ) TickType_t xReturn; UBaseType_t uxSavedInterruptStatus; + traceENTER_xTaskGetTickCountFromISR(); + /* RTOS ports that support interrupt nesting have the concept of a maximum * system call (or maximum API call) interrupt priority. Interrupts that are * above the maximum system call priority are kept permanently enabled, even @@ -2339,108 +4119,196 @@ TickType_t xTaskGetTickCountFromISR( void ) } portTICK_TYPE_CLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus ); + traceRETURN_xTaskGetTickCountFromISR( xReturn ); + return xReturn; } /*-----------------------------------------------------------*/ UBaseType_t uxTaskGetNumberOfTasks( void ) { + traceENTER_uxTaskGetNumberOfTasks(); + /* A critical section is not required because the variables are of type * BaseType_t. */ + traceRETURN_uxTaskGetNumberOfTasks( uxCurrentNumberOfTasks ); + return uxCurrentNumberOfTasks; } /*-----------------------------------------------------------*/ -char * pcTaskGetName( TaskHandle_t xTaskToQuery ) /*lint !e971 Unqualified char types are allowed for strings and single characters only. */ +char * pcTaskGetName( TaskHandle_t xTaskToQuery ) { TCB_t * pxTCB; + traceENTER_pcTaskGetName( xTaskToQuery ); + /* If null is passed in here then the name of the calling task is being * queried. */ pxTCB = prvGetTCBFromHandle( xTaskToQuery ); configASSERT( pxTCB ); + + traceRETURN_pcTaskGetName( &( pxTCB->pcTaskName[ 0 ] ) ); + return &( pxTCB->pcTaskName[ 0 ] ); } /*-----------------------------------------------------------*/ #if ( INCLUDE_xTaskGetHandle == 1 ) - static TCB_t * prvSearchForNameWithinSingleList( List_t * pxList, - const char pcNameToQuery[] ) - { - TCB_t * pxNextTCB; - TCB_t * pxFirstTCB; - TCB_t * pxReturn = NULL; - UBaseType_t x; - char cNextChar; - BaseType_t xBreakLoop; - - /* This function is called with the scheduler suspended. */ - - if( listCURRENT_LIST_LENGTH( pxList ) > ( UBaseType_t ) 0 ) + #if ( configNUMBER_OF_CORES == 1 ) + static TCB_t * prvSearchForNameWithinSingleList( List_t * pxList, + const char pcNameToQuery[] ) { - listGET_OWNER_OF_NEXT_ENTRY( pxFirstTCB, pxList ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */ + TCB_t * pxNextTCB; + TCB_t * pxFirstTCB; + TCB_t * pxReturn = NULL; + UBaseType_t x; + char cNextChar; + BaseType_t xBreakLoop; - do - { - listGET_OWNER_OF_NEXT_ENTRY( pxNextTCB, pxList ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */ + /* This function is called with the scheduler suspended. */ - /* Check each character in the name looking for a match or - * mismatch. */ - xBreakLoop = pdFALSE; + if( listCURRENT_LIST_LENGTH( pxList ) > ( UBaseType_t ) 0 ) + { + /* MISRA Ref 11.5.3 [Void pointer assignment] */ + /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-115 */ + /* coverity[misra_c_2012_rule_11_5_violation] */ + listGET_OWNER_OF_NEXT_ENTRY( pxFirstTCB, pxList ); - for( x = ( UBaseType_t ) 0; x < ( UBaseType_t ) configMAX_TASK_NAME_LEN; x++ ) + do { - cNextChar = pxNextTCB->pcTaskName[ x ]; + /* MISRA Ref 11.5.3 [Void pointer assignment] */ + /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-115 */ + /* coverity[misra_c_2012_rule_11_5_violation] */ + listGET_OWNER_OF_NEXT_ENTRY( pxNextTCB, pxList ); + + /* Check each character in the name looking for a match or + * mismatch. */ + xBreakLoop = pdFALSE; - if( cNextChar != pcNameToQuery[ x ] ) + for( x = ( UBaseType_t ) 0; x < ( UBaseType_t ) configMAX_TASK_NAME_LEN; x++ ) { - /* Characters didn't match. */ - xBreakLoop = pdTRUE; + cNextChar = pxNextTCB->pcTaskName[ x ]; + + if( cNextChar != pcNameToQuery[ x ] ) + { + /* Characters didn't match. */ + xBreakLoop = pdTRUE; + } + else if( cNextChar == ( char ) 0x00 ) + { + /* Both strings terminated, a match must have been + * found. */ + pxReturn = pxNextTCB; + xBreakLoop = pdTRUE; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + if( xBreakLoop != pdFALSE ) + { + break; + } } - else if( cNextChar == ( char ) 0x00 ) + + if( pxReturn != NULL ) { - /* Both strings terminated, a match must have been - * found. */ - pxReturn = pxNextTCB; - xBreakLoop = pdTRUE; + /* The handle has been found. */ + break; } - else + } while( pxNextTCB != pxFirstTCB ); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + return pxReturn; + } + #else /* if ( configNUMBER_OF_CORES == 1 ) */ + static TCB_t * prvSearchForNameWithinSingleList( List_t * pxList, + const char pcNameToQuery[] ) + { + TCB_t * pxReturn = NULL; + UBaseType_t x; + char cNextChar; + BaseType_t xBreakLoop; + const ListItem_t * pxEndMarker = listGET_END_MARKER( pxList ); + ListItem_t * pxIterator; + + /* This function is called with the scheduler suspended. */ + + if( listCURRENT_LIST_LENGTH( pxList ) > ( UBaseType_t ) 0 ) + { + for( pxIterator = listGET_HEAD_ENTRY( pxList ); pxIterator != pxEndMarker; pxIterator = listGET_NEXT( pxIterator ) ) + { + /* MISRA Ref 11.5.3 [Void pointer assignment] */ + /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-115 */ + /* coverity[misra_c_2012_rule_11_5_violation] */ + TCB_t * pxTCB = listGET_LIST_ITEM_OWNER( pxIterator ); + + /* Check each character in the name looking for a match or + * mismatch. */ + xBreakLoop = pdFALSE; + + for( x = ( UBaseType_t ) 0; x < ( UBaseType_t ) configMAX_TASK_NAME_LEN; x++ ) { - mtCOVERAGE_TEST_MARKER(); + cNextChar = pxTCB->pcTaskName[ x ]; + + if( cNextChar != pcNameToQuery[ x ] ) + { + /* Characters didn't match. */ + xBreakLoop = pdTRUE; + } + else if( cNextChar == ( char ) 0x00 ) + { + /* Both strings terminated, a match must have been + * found. */ + pxReturn = pxTCB; + xBreakLoop = pdTRUE; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + if( xBreakLoop != pdFALSE ) + { + break; + } } - if( xBreakLoop != pdFALSE ) + if( pxReturn != NULL ) { + /* The handle has been found. */ break; } } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } - if( pxReturn != NULL ) - { - /* The handle has been found. */ - break; - } - } while( pxNextTCB != pxFirstTCB ); - } - else - { - mtCOVERAGE_TEST_MARKER(); + return pxReturn; } - - return pxReturn; - } + #endif /* #if ( configNUMBER_OF_CORES == 1 ) */ #endif /* INCLUDE_xTaskGetHandle */ /*-----------------------------------------------------------*/ #if ( INCLUDE_xTaskGetHandle == 1 ) - TaskHandle_t xTaskGetHandle( const char * pcNameToQuery ) /*lint !e971 Unqualified char types are allowed for strings and single characters only. */ + TaskHandle_t xTaskGetHandle( const char * pcNameToQuery ) { UBaseType_t uxQueue = configMAX_PRIORITIES; TCB_t * pxTCB; + traceENTER_xTaskGetHandle( pcNameToQuery ); + /* Task names will be truncated to configMAX_TASK_NAME_LEN - 1 bytes. */ configASSERT( strlen( pcNameToQuery ) < configMAX_TASK_NAME_LEN ); @@ -2457,7 +4325,7 @@ char * pcTaskGetName( TaskHandle_t xTaskToQuery ) /*lint !e971 Unqualified char /* Found the handle. */ break; } - } while( uxQueue > ( UBaseType_t ) tskIDLE_PRIORITY ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */ + } while( uxQueue > ( UBaseType_t ) tskIDLE_PRIORITY ); /* Search the delayed lists. */ if( pxTCB == NULL ) @@ -2492,6 +4360,8 @@ char * pcTaskGetName( TaskHandle_t xTaskToQuery ) /*lint !e971 Unqualified char } ( void ) xTaskResumeAll(); + traceRETURN_xTaskGetHandle( pxTCB ); + return pxTCB; } @@ -2507,6 +4377,8 @@ char * pcTaskGetName( TaskHandle_t xTaskToQuery ) /*lint !e971 Unqualified char BaseType_t xReturn; TCB_t * pxTCB; + traceENTER_xTaskGetStaticBuffers( xTask, ppuxStackBuffer, ppxTaskBuffer ); + configASSERT( ppuxStackBuffer != NULL ); configASSERT( ppxTaskBuffer != NULL ); @@ -2517,6 +4389,9 @@ char * pcTaskGetName( TaskHandle_t xTaskToQuery ) /*lint !e971 Unqualified char if( pxTCB->ucStaticallyAllocated == tskSTATICALLY_ALLOCATED_STACK_AND_TCB ) { *ppuxStackBuffer = pxTCB->pxStack; + /* MISRA Ref 11.3.1 [Misaligned access] */ + /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-113 */ + /* coverity[misra_c_2012_rule_11_3_violation] */ *ppxTaskBuffer = ( StaticTask_t * ) pxTCB; xReturn = pdTRUE; } @@ -2539,6 +4414,8 @@ char * pcTaskGetName( TaskHandle_t xTaskToQuery ) /*lint !e971 Unqualified char } #endif /* tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE == 1 */ + traceRETURN_xTaskGetStaticBuffers( xReturn ); + return xReturn; } @@ -2553,6 +4430,8 @@ char * pcTaskGetName( TaskHandle_t xTaskToQuery ) /*lint !e971 Unqualified char { UBaseType_t uxTask = 0, uxQueue = configMAX_PRIORITIES; + traceENTER_uxTaskGetSystemState( pxTaskStatusArray, uxArraySize, pulTotalRunTime ); + vTaskSuspendAll(); { /* Is there a space in the array for each task in the system? */ @@ -2563,19 +4442,19 @@ char * pcTaskGetName( TaskHandle_t xTaskToQuery ) /*lint !e971 Unqualified char do { uxQueue--; - uxTask += prvListTasksWithinSingleList( &( pxTaskStatusArray[ uxTask ] ), &( pxReadyTasksLists[ uxQueue ] ), eReady ); - } while( uxQueue > ( UBaseType_t ) tskIDLE_PRIORITY ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */ + uxTask = ( UBaseType_t ) ( uxTask + prvListTasksWithinSingleList( &( pxTaskStatusArray[ uxTask ] ), &( pxReadyTasksLists[ uxQueue ] ), eReady ) ); + } while( uxQueue > ( UBaseType_t ) tskIDLE_PRIORITY ); /* Fill in an TaskStatus_t structure with information on each * task in the Blocked state. */ - uxTask += prvListTasksWithinSingleList( &( pxTaskStatusArray[ uxTask ] ), ( List_t * ) pxDelayedTaskList, eBlocked ); - uxTask += prvListTasksWithinSingleList( &( pxTaskStatusArray[ uxTask ] ), ( List_t * ) pxOverflowDelayedTaskList, eBlocked ); + uxTask = ( UBaseType_t ) ( uxTask + prvListTasksWithinSingleList( &( pxTaskStatusArray[ uxTask ] ), ( List_t * ) pxDelayedTaskList, eBlocked ) ); + uxTask = ( UBaseType_t ) ( uxTask + prvListTasksWithinSingleList( &( pxTaskStatusArray[ uxTask ] ), ( List_t * ) pxOverflowDelayedTaskList, eBlocked ) ); #if ( INCLUDE_vTaskDelete == 1 ) { /* Fill in an TaskStatus_t structure with information on * each task that has been deleted but not yet cleaned up. */ - uxTask += prvListTasksWithinSingleList( &( pxTaskStatusArray[ uxTask ] ), &xTasksWaitingTermination, eDeleted ); + uxTask = ( UBaseType_t ) ( uxTask + prvListTasksWithinSingleList( &( pxTaskStatusArray[ uxTask ] ), &xTasksWaitingTermination, eDeleted ) ); } #endif @@ -2583,7 +4462,7 @@ char * pcTaskGetName( TaskHandle_t xTaskToQuery ) /*lint !e971 Unqualified char { /* Fill in an TaskStatus_t structure with information on * each task in the Suspended state. */ - uxTask += prvListTasksWithinSingleList( &( pxTaskStatusArray[ uxTask ] ), &xSuspendedTaskList, eSuspended ); + uxTask = ( UBaseType_t ) ( uxTask + prvListTasksWithinSingleList( &( pxTaskStatusArray[ uxTask ] ), &xSuspendedTaskList, eSuspended ) ); } #endif @@ -2614,6 +4493,8 @@ char * pcTaskGetName( TaskHandle_t xTaskToQuery ) /*lint !e971 Unqualified char } ( void ) xTaskResumeAll(); + traceRETURN_uxTaskGetSystemState( uxTask ); + return uxTask; } @@ -2622,12 +4503,35 @@ char * pcTaskGetName( TaskHandle_t xTaskToQuery ) /*lint !e971 Unqualified char #if ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) - TaskHandle_t xTaskGetIdleTaskHandle( void ) + #if ( configNUMBER_OF_CORES == 1 ) + TaskHandle_t xTaskGetIdleTaskHandle( void ) + { + traceENTER_xTaskGetIdleTaskHandle(); + + /* If xTaskGetIdleTaskHandle() is called before the scheduler has been + * started, then xIdleTaskHandles will be NULL. */ + configASSERT( ( xIdleTaskHandles[ 0 ] != NULL ) ); + + traceRETURN_xTaskGetIdleTaskHandle( xIdleTaskHandles[ 0 ] ); + + return xIdleTaskHandles[ 0 ]; + } + #endif /* if ( configNUMBER_OF_CORES == 1 ) */ + + TaskHandle_t xTaskGetIdleTaskHandleForCore( BaseType_t xCoreID ) { + traceENTER_xTaskGetIdleTaskHandleForCore( xCoreID ); + + /* Ensure the core ID is valid. */ + configASSERT( taskVALID_CORE_ID( xCoreID ) == pdTRUE ); + /* If xTaskGetIdleTaskHandle() is called before the scheduler has been - * started, then xIdleTaskHandle will be NULL. */ - configASSERT( ( xIdleTaskHandle != NULL ) ); - return xIdleTaskHandle; + * started, then xIdleTaskHandles will be NULL. */ + configASSERT( ( xIdleTaskHandles[ xCoreID ] != NULL ) ); + + traceRETURN_xTaskGetIdleTaskHandleForCore( xIdleTaskHandles[ xCoreID ] ); + + return xIdleTaskHandles[ xCoreID ]; } #endif /* INCLUDE_xTaskGetIdleTaskHandle */ @@ -2641,12 +4545,17 @@ char * pcTaskGetName( TaskHandle_t xTaskToQuery ) /*lint !e971 Unqualified char void vTaskStepTick( TickType_t xTicksToJump ) { + TickType_t xUpdatedTickCount; + + traceENTER_vTaskStepTick( xTicksToJump ); + /* Correct the tick count value after a period during which the tick * was suppressed. Note this does *not* call the tick hook function for * each stepped tick. */ - configASSERT( ( xTickCount + xTicksToJump ) <= xNextTaskUnblockTime ); + xUpdatedTickCount = xTickCount + xTicksToJump; + configASSERT( xUpdatedTickCount <= xNextTaskUnblockTime ); - if( ( xTickCount + xTicksToJump ) == xNextTaskUnblockTime ) + if( xUpdatedTickCount == xNextTaskUnblockTime ) { /* Arrange for xTickCount to reach xNextTaskUnblockTime in * xTaskIncrementTick() when the scheduler resumes. This ensures @@ -2668,7 +4577,9 @@ char * pcTaskGetName( TaskHandle_t xTaskToQuery ) /*lint !e971 Unqualified char } xTickCount += xTicksToJump; + traceINCREASE_TICK_COUNT( xTicksToJump ); + traceRETURN_vTaskStepTick(); } #endif /* configUSE_TICKLESS_IDLE */ @@ -2678,6 +4589,8 @@ BaseType_t xTaskCatchUpTicks( TickType_t xTicksToCatchUp ) { BaseType_t xYieldOccurred; + traceENTER_xTaskCatchUpTicks( xTicksToCatchUp ); + /* Must not be called with the scheduler suspended as the implementation * relies on xPendedTicks being wound down to 0 in xTaskResumeAll(). */ configASSERT( uxSchedulerSuspended == ( UBaseType_t ) 0U ); @@ -2694,6 +4607,8 @@ BaseType_t xTaskCatchUpTicks( TickType_t xTicksToCatchUp ) taskEXIT_CRITICAL(); xYieldOccurred = xTaskResumeAll(); + traceRETURN_xTaskCatchUpTicks( xYieldOccurred ); + return xYieldOccurred; } /*----------------------------------------------------------*/ @@ -2705,6 +4620,8 @@ BaseType_t xTaskCatchUpTicks( TickType_t xTicksToCatchUp ) TCB_t * pxTCB = xTask; BaseType_t xReturn; + traceENTER_xTaskAbortDelay( xTask ); + configASSERT( pxTCB ); vTaskSuspendAll(); @@ -2749,21 +4666,33 @@ BaseType_t xTaskCatchUpTicks( TickType_t xTicksToCatchUp ) * switch if preemption is turned off. */ #if ( configUSE_PREEMPTION == 1 ) { - /* Preemption is on, but a context switch should only be - * performed if the unblocked task has a priority that is - * higher than the currently executing task. */ - if( pxTCB->uxPriority > pxCurrentTCB->uxPriority ) + #if ( configNUMBER_OF_CORES == 1 ) { - /* Pend the yield to be performed when the scheduler - * is unsuspended. */ - xYieldPending = pdTRUE; + /* Preemption is on, but a context switch should only be + * performed if the unblocked task has a priority that is + * higher than the currently executing task. */ + if( pxTCB->uxPriority > pxCurrentTCB->uxPriority ) + { + /* Pend the yield to be performed when the scheduler + * is unsuspended. */ + xYieldPendings[ 0 ] = pdTRUE; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } } - else + #else /* #if ( configNUMBER_OF_CORES == 1 ) */ { - mtCOVERAGE_TEST_MARKER(); + taskENTER_CRITICAL(); + { + prvYieldForTask( pxTCB ); + } + taskEXIT_CRITICAL(); } + #endif /* #if ( configNUMBER_OF_CORES == 1 ) */ } - #endif /* configUSE_PREEMPTION */ + #endif /* #if ( configUSE_PREEMPTION == 1 ) */ } else { @@ -2772,6 +4701,8 @@ BaseType_t xTaskCatchUpTicks( TickType_t xTicksToCatchUp ) } ( void ) xTaskResumeAll(); + traceRETURN_xTaskAbortDelay( xReturn ); + return xReturn; } @@ -2784,11 +4715,21 @@ BaseType_t xTaskIncrementTick( void ) TickType_t xItemValue; BaseType_t xSwitchRequired = pdFALSE; + #if ( configUSE_PREEMPTION == 1 ) && ( configNUMBER_OF_CORES > 1 ) + BaseType_t xYieldRequiredForCore[ configNUMBER_OF_CORES ] = { pdFALSE }; + #endif /* #if ( configUSE_PREEMPTION == 1 ) && ( configNUMBER_OF_CORES > 1 ) */ + + traceENTER_xTaskIncrementTick(); + /* Called by the portable layer each time a tick interrupt occurs. * Increments the tick then checks to see if the new tick value will cause any * tasks to be unblocked. */ traceTASK_INCREMENT_TICK( xTickCount ); + /* Tick increment should occur on every kernel timer event. Core 0 has the + * responsibility to increment the tick, or increment the pended ticks if the + * scheduler is suspended. If pended ticks is greater than zero, the core that + * calls xTaskResumeAll has the responsibility to increment the tick. */ if( uxSchedulerSuspended == ( UBaseType_t ) 0U ) { /* Minor optimisation. The tick count cannot change in this @@ -2799,7 +4740,7 @@ BaseType_t xTaskIncrementTick( void ) * delayed lists if it wraps to 0. */ xTickCount = xConstTickCount; - if( xConstTickCount == ( TickType_t ) 0U ) /*lint !e774 'if' does not always evaluate to false as it is looking for an overflow. */ + if( xConstTickCount == ( TickType_t ) 0U ) { taskSWITCH_DELAYED_LISTS(); } @@ -2823,7 +4764,7 @@ BaseType_t xTaskIncrementTick( void ) * unlikely that the * if( xTickCount >= xNextTaskUnblockTime ) test will pass * next time through. */ - xNextTaskUnblockTime = portMAX_DELAY; /*lint !e961 MISRA exception as the casts are only redundant for some ports. */ + xNextTaskUnblockTime = portMAX_DELAY; break; } else @@ -2832,7 +4773,10 @@ BaseType_t xTaskIncrementTick( void ) * item at the head of the delayed list. This is the time * at which the task at the head of the delayed list must * be removed from the Blocked state. */ - pxTCB = listGET_OWNER_OF_HEAD_ENTRY( pxDelayedTaskList ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */ + /* MISRA Ref 11.5.3 [Void pointer assignment] */ + /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-115 */ + /* coverity[misra_c_2012_rule_11_5_violation] */ + pxTCB = listGET_OWNER_OF_HEAD_ENTRY( pxDelayedTaskList ); xItemValue = listGET_LIST_ITEM_VALUE( &( pxTCB->xStateListItem ) ); if( xConstTickCount < xItemValue ) @@ -2843,7 +4787,7 @@ BaseType_t xTaskIncrementTick( void ) * state - so record the item value in * xNextTaskUnblockTime. */ xNextTaskUnblockTime = xItemValue; - break; /*lint !e9011 Code structure here is deemed easier to understand with multiple breaks. */ + break; } else { @@ -2872,24 +4816,32 @@ BaseType_t xTaskIncrementTick( void ) * context switch if preemption is turned off. */ #if ( configUSE_PREEMPTION == 1 ) { - /* Preemption is on, but a context switch should - * only be performed if the unblocked task's - * priority is higher than the currently executing - * task. - * The case of equal priority tasks sharing - * processing time (which happens when both - * preemption and time slicing are on) is - * handled below.*/ - if( pxTCB->uxPriority > pxCurrentTCB->uxPriority ) + #if ( configNUMBER_OF_CORES == 1 ) { - xSwitchRequired = pdTRUE; + /* Preemption is on, but a context switch should + * only be performed if the unblocked task's + * priority is higher than the currently executing + * task. + * The case of equal priority tasks sharing + * processing time (which happens when both + * preemption and time slicing are on) is + * handled below.*/ + if( pxTCB->uxPriority > pxCurrentTCB->uxPriority ) + { + xSwitchRequired = pdTRUE; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } } - else + #else /* #if( configNUMBER_OF_CORES == 1 ) */ { - mtCOVERAGE_TEST_MARKER(); + prvYieldForTask( pxTCB ); } + #endif /* #if( configNUMBER_OF_CORES == 1 ) */ } - #endif /* configUSE_PREEMPTION */ + #endif /* #if ( configUSE_PREEMPTION == 1 ) */ } } } @@ -2899,16 +4851,36 @@ BaseType_t xTaskIncrementTick( void ) * writer has not explicitly turned time slicing off. */ #if ( ( configUSE_PREEMPTION == 1 ) && ( configUSE_TIME_SLICING == 1 ) ) { - if( listCURRENT_LIST_LENGTH( &( pxReadyTasksLists[ pxCurrentTCB->uxPriority ] ) ) > ( UBaseType_t ) 1 ) + #if ( configNUMBER_OF_CORES == 1 ) { - xSwitchRequired = pdTRUE; + if( listCURRENT_LIST_LENGTH( &( pxReadyTasksLists[ pxCurrentTCB->uxPriority ] ) ) > 1U ) + { + xSwitchRequired = pdTRUE; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } } - else + #else /* #if ( configNUMBER_OF_CORES == 1 ) */ { - mtCOVERAGE_TEST_MARKER(); + BaseType_t xCoreID; + + for( xCoreID = 0; xCoreID < ( ( BaseType_t ) configNUMBER_OF_CORES ); xCoreID++ ) + { + if( listCURRENT_LIST_LENGTH( &( pxReadyTasksLists[ pxCurrentTCBs[ xCoreID ]->uxPriority ] ) ) > 1U ) + { + xYieldRequiredForCore[ xCoreID ] = pdTRUE; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } } + #endif /* #if ( configNUMBER_OF_CORES == 1 ) */ } - #endif /* ( ( configUSE_PREEMPTION == 1 ) && ( configUSE_TIME_SLICING == 1 ) ) */ + #endif /* #if ( ( configUSE_PREEMPTION == 1 ) && ( configUSE_TIME_SLICING == 1 ) ) */ #if ( configUSE_TICK_HOOK == 1 ) { @@ -2927,16 +4899,50 @@ BaseType_t xTaskIncrementTick( void ) #if ( configUSE_PREEMPTION == 1 ) { - if( xYieldPending != pdFALSE ) + #if ( configNUMBER_OF_CORES == 1 ) { - xSwitchRequired = pdTRUE; + /* For single core the core ID is always 0. */ + if( xYieldPendings[ 0 ] != pdFALSE ) + { + xSwitchRequired = pdTRUE; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } } - else + #else /* #if ( configNUMBER_OF_CORES == 1 ) */ { - mtCOVERAGE_TEST_MARKER(); + BaseType_t xCoreID, xCurrentCoreID; + xCurrentCoreID = ( BaseType_t ) portGET_CORE_ID(); + + for( xCoreID = 0; xCoreID < ( BaseType_t ) configNUMBER_OF_CORES; xCoreID++ ) + { + #if ( configUSE_TASK_PREEMPTION_DISABLE == 1 ) + if( pxCurrentTCBs[ xCoreID ]->xPreemptionDisable == pdFALSE ) + #endif + { + if( ( xYieldRequiredForCore[ xCoreID ] != pdFALSE ) || ( xYieldPendings[ xCoreID ] != pdFALSE ) ) + { + if( xCoreID == xCurrentCoreID ) + { + xSwitchRequired = pdTRUE; + } + else + { + prvYieldCore( xCoreID ); + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + } } + #endif /* #if ( configNUMBER_OF_CORES == 1 ) */ } - #endif /* configUSE_PREEMPTION */ + #endif /* #if ( configUSE_PREEMPTION == 1 ) */ } else { @@ -2951,6 +4957,8 @@ BaseType_t xTaskIncrementTick( void ) #endif } + traceRETURN_xTaskIncrementTick( xSwitchRequired ); + return xSwitchRequired; } /*-----------------------------------------------------------*/ @@ -2962,6 +4970,8 @@ BaseType_t xTaskIncrementTick( void ) { TCB_t * xTCB; + traceENTER_vTaskSetApplicationTaskTag( xTask, pxHookFunction ); + /* If xTask is NULL then it is the task hook of the calling task that is * getting set. */ if( xTask == NULL ) @@ -2980,6 +4990,8 @@ BaseType_t xTaskIncrementTick( void ) xTCB->pxTaskTag = pxHookFunction; } taskEXIT_CRITICAL(); + + traceRETURN_vTaskSetApplicationTaskTag(); } #endif /* configUSE_APPLICATION_TASK_TAG */ @@ -2992,6 +5004,8 @@ BaseType_t xTaskIncrementTick( void ) TCB_t * pxTCB; TaskHookFunction_t xReturn; + traceENTER_xTaskGetApplicationTaskTag( xTask ); + /* If xTask is NULL then set the calling task's hook. */ pxTCB = prvGetTCBFromHandle( xTask ); @@ -3003,6 +5017,8 @@ BaseType_t xTaskIncrementTick( void ) } taskEXIT_CRITICAL(); + traceRETURN_xTaskGetApplicationTaskTag( xReturn ); + return xReturn; } @@ -3017,16 +5033,20 @@ BaseType_t xTaskIncrementTick( void ) TaskHookFunction_t xReturn; UBaseType_t uxSavedInterruptStatus; + traceENTER_xTaskGetApplicationTaskTagFromISR( xTask ); + /* If xTask is NULL then set the calling task's hook. */ pxTCB = prvGetTCBFromHandle( xTask ); /* Save the hook function in the TCB. A critical section is required as * the value can be accessed from an interrupt. */ - uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR(); + uxSavedInterruptStatus = taskENTER_CRITICAL_FROM_ISR(); { xReturn = pxTCB->pxTaskTag; } - portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus ); + taskEXIT_CRITICAL_FROM_ISR( uxSavedInterruptStatus ); + + traceRETURN_xTaskGetApplicationTaskTagFromISR( xReturn ); return xReturn; } @@ -3042,6 +5062,8 @@ BaseType_t xTaskIncrementTick( void ) TCB_t * xTCB; BaseType_t xReturn; + traceENTER_xTaskCallApplicationTaskHook( xTask, pvParameter ); + /* If xTask is NULL then we are calling our own task hook. */ if( xTask == NULL ) { @@ -3061,92 +5083,210 @@ BaseType_t xTaskIncrementTick( void ) xReturn = pdFAIL; } + traceRETURN_xTaskCallApplicationTaskHook( xReturn ); + return xReturn; } #endif /* configUSE_APPLICATION_TASK_TAG */ /*-----------------------------------------------------------*/ -void vTaskSwitchContext( void ) -{ - if( uxSchedulerSuspended != ( UBaseType_t ) 0U ) - { - /* The scheduler is currently suspended - do not allow a context - * switch. */ - xYieldPending = pdTRUE; - } - else +#if ( configNUMBER_OF_CORES == 1 ) + void vTaskSwitchContext( void ) { - xYieldPending = pdFALSE; - traceTASK_SWITCHED_OUT(); + traceENTER_vTaskSwitchContext(); - #if ( configGENERATE_RUN_TIME_STATS == 1 ) + if( uxSchedulerSuspended != ( UBaseType_t ) 0U ) { - #ifdef portALT_GET_RUN_TIME_COUNTER_VALUE - portALT_GET_RUN_TIME_COUNTER_VALUE( ulTotalRunTime ); - #else - ulTotalRunTime = ( configRUN_TIME_COUNTER_TYPE ) portGET_RUN_TIME_COUNTER_VALUE(); - #endif + /* The scheduler is currently suspended - do not allow a context + * switch. */ + xYieldPendings[ 0 ] = pdTRUE; + } + else + { + xYieldPendings[ 0 ] = pdFALSE; + traceTASK_SWITCHED_OUT(); - /* Add the amount of time the task has been running to the - * accumulated time so far. The time the task started running was - * stored in ulTaskSwitchedInTime. Note that there is no overflow - * protection here so count values are only valid until the timer - * overflows. The guard against negative values is to protect - * against suspect run time stat counter implementations - which - * are provided by the application, not the kernel. */ - if( ulTotalRunTime > ulTaskSwitchedInTime ) + #if ( configGENERATE_RUN_TIME_STATS == 1 ) { - pxCurrentTCB->ulRunTimeCounter += ( ulTotalRunTime - ulTaskSwitchedInTime ); + #ifdef portALT_GET_RUN_TIME_COUNTER_VALUE + portALT_GET_RUN_TIME_COUNTER_VALUE( ulTotalRunTime[ 0 ] ); + #else + ulTotalRunTime[ 0 ] = portGET_RUN_TIME_COUNTER_VALUE(); + #endif + + /* Add the amount of time the task has been running to the + * accumulated time so far. The time the task started running was + * stored in ulTaskSwitchedInTime. Note that there is no overflow + * protection here so count values are only valid until the timer + * overflows. The guard against negative values is to protect + * against suspect run time stat counter implementations - which + * are provided by the application, not the kernel. */ + if( ulTotalRunTime[ 0 ] > ulTaskSwitchedInTime[ 0 ] ) + { + pxCurrentTCB->ulRunTimeCounter += ( ulTotalRunTime[ 0 ] - ulTaskSwitchedInTime[ 0 ] ); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + ulTaskSwitchedInTime[ 0 ] = ulTotalRunTime[ 0 ]; } - else + #endif /* configGENERATE_RUN_TIME_STATS */ + + /* Check for stack overflow, if configured. */ + taskCHECK_FOR_STACK_OVERFLOW(); + + /* Before the currently running task is switched out, save its errno. */ + #if ( configUSE_POSIX_ERRNO == 1 ) { - mtCOVERAGE_TEST_MARKER(); + pxCurrentTCB->iTaskErrno = FreeRTOS_errno; } + #endif - ulTaskSwitchedInTime = ulTotalRunTime; - } - #endif /* configGENERATE_RUN_TIME_STATS */ + /* Select a new task to run using either the generic C or port + * optimised asm code. */ + /* MISRA Ref 11.5.3 [Void pointer assignment] */ + /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-115 */ + /* coverity[misra_c_2012_rule_11_5_violation] */ + taskSELECT_HIGHEST_PRIORITY_TASK(); + traceTASK_SWITCHED_IN(); - /* Check for stack overflow, if configured. */ - taskCHECK_FOR_STACK_OVERFLOW(); + /* Macro to inject port specific behaviour immediately after + * switching tasks, such as setting an end of stack watchpoint + * or reconfiguring the MPU. */ + portTASK_SWITCH_HOOK( pxCurrentTCB ); - /* Before the currently running task is switched out, save its errno. */ - #if ( configUSE_POSIX_ERRNO == 1 ) - { - pxCurrentTCB->iTaskErrno = FreeRTOS_errno; + /* After the new task is switched in, update the global errno. */ + #if ( configUSE_POSIX_ERRNO == 1 ) + { + FreeRTOS_errno = pxCurrentTCB->iTaskErrno; + } + #endif + + #if ( configUSE_C_RUNTIME_TLS_SUPPORT == 1 ) + { + /* Switch C-Runtime's TLS Block to point to the TLS + * Block specific to this task. */ + configSET_TLS_BLOCK( pxCurrentTCB->xTLSBlock ); + } + #endif } - #endif - /* Select a new task to run using either the generic C or port - * optimised asm code. */ - taskSELECT_HIGHEST_PRIORITY_TASK(); /*lint !e9079 void * is used as this macro is used with timers and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */ - traceTASK_SWITCHED_IN(); + traceRETURN_vTaskSwitchContext(); + } +#else /* if ( configNUMBER_OF_CORES == 1 ) */ + void vTaskSwitchContext( BaseType_t xCoreID ) + { + traceENTER_vTaskSwitchContext(); - /* After the new task is switched in, update the global errno. */ - #if ( configUSE_POSIX_ERRNO == 1 ) - { - FreeRTOS_errno = pxCurrentTCB->iTaskErrno; - } - #endif + /* Acquire both locks: + * - The ISR lock protects the ready list from simultaneous access by + * both other ISRs and tasks. + * - We also take the task lock to pause here in case another core has + * suspended the scheduler. We don't want to simply set xYieldPending + * and move on if another core suspended the scheduler. We should only + * do that if the current core has suspended the scheduler. */ - #if ( configUSE_C_RUNTIME_TLS_SUPPORT == 1 ) + portGET_TASK_LOCK(); /* Must always acquire the task lock first. */ + portGET_ISR_LOCK(); { - /* Switch C-Runtime's TLS Block to point to the TLS - * Block specific to this task. */ - configSET_TLS_BLOCK( pxCurrentTCB->xTLSBlock ); + /* vTaskSwitchContext() must never be called from within a critical section. + * This is not necessarily true for single core FreeRTOS, but it is for this + * SMP port. */ + configASSERT( portGET_CRITICAL_NESTING_COUNT() == 0 ); + + if( uxSchedulerSuspended != ( UBaseType_t ) 0U ) + { + /* The scheduler is currently suspended - do not allow a context + * switch. */ + xYieldPendings[ xCoreID ] = pdTRUE; + } + else + { + xYieldPendings[ xCoreID ] = pdFALSE; + traceTASK_SWITCHED_OUT(); + + #if ( configGENERATE_RUN_TIME_STATS == 1 ) + { + #ifdef portALT_GET_RUN_TIME_COUNTER_VALUE + portALT_GET_RUN_TIME_COUNTER_VALUE( ulTotalRunTime[ xCoreID ] ); + #else + ulTotalRunTime[ xCoreID ] = portGET_RUN_TIME_COUNTER_VALUE(); + #endif + + /* Add the amount of time the task has been running to the + * accumulated time so far. The time the task started running was + * stored in ulTaskSwitchedInTime. Note that there is no overflow + * protection here so count values are only valid until the timer + * overflows. The guard against negative values is to protect + * against suspect run time stat counter implementations - which + * are provided by the application, not the kernel. */ + if( ulTotalRunTime[ xCoreID ] > ulTaskSwitchedInTime[ xCoreID ] ) + { + pxCurrentTCBs[ xCoreID ]->ulRunTimeCounter += ( ulTotalRunTime[ xCoreID ] - ulTaskSwitchedInTime[ xCoreID ] ); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + ulTaskSwitchedInTime[ xCoreID ] = ulTotalRunTime[ xCoreID ]; + } + #endif /* configGENERATE_RUN_TIME_STATS */ + + /* Check for stack overflow, if configured. */ + taskCHECK_FOR_STACK_OVERFLOW(); + + /* Before the currently running task is switched out, save its errno. */ + #if ( configUSE_POSIX_ERRNO == 1 ) + { + pxCurrentTCBs[ xCoreID ]->iTaskErrno = FreeRTOS_errno; + } + #endif + + /* Select a new task to run. */ + taskSELECT_HIGHEST_PRIORITY_TASK( xCoreID ); + traceTASK_SWITCHED_IN(); + + /* Macro to inject port specific behaviour immediately after + * switching tasks, such as setting an end of stack watchpoint + * or reconfiguring the MPU. */ + portTASK_SWITCH_HOOK( pxCurrentTCBs[ portGET_CORE_ID() ] ); + + /* After the new task is switched in, update the global errno. */ + #if ( configUSE_POSIX_ERRNO == 1 ) + { + FreeRTOS_errno = pxCurrentTCBs[ xCoreID ]->iTaskErrno; + } + #endif + + #if ( configUSE_C_RUNTIME_TLS_SUPPORT == 1 ) + { + /* Switch C-Runtime's TLS Block to point to the TLS + * Block specific to this task. */ + configSET_TLS_BLOCK( pxCurrentTCBs[ xCoreID ]->xTLSBlock ); + } + #endif + } } - #endif + portRELEASE_ISR_LOCK(); + portRELEASE_TASK_LOCK(); + + traceRETURN_vTaskSwitchContext(); } -} +#endif /* if ( configNUMBER_OF_CORES > 1 ) */ /*-----------------------------------------------------------*/ void vTaskPlaceOnEventList( List_t * const pxEventList, const TickType_t xTicksToWait ) { + traceENTER_vTaskPlaceOnEventList( pxEventList, xTicksToWait ); + configASSERT( pxEventList ); - /* THIS FUNCTION MUST BE CALLED WITH EITHER INTERRUPTS DISABLED OR THE + /* THIS FUNCTION MUST BE CALLED WITH THE * SCHEDULER SUSPENDED AND THE QUEUE BEING ACCESSED LOCKED. */ /* Place the event list item of the TCB in the appropriate event list. @@ -3163,6 +5303,8 @@ void vTaskPlaceOnEventList( List_t * const pxEventList, vListInsert( pxEventList, &( pxCurrentTCB->xEventListItem ) ); prvAddCurrentTaskToDelayedList( xTicksToWait, pdTRUE ); + + traceRETURN_vTaskPlaceOnEventList(); } /*-----------------------------------------------------------*/ @@ -3170,6 +5312,8 @@ void vTaskPlaceOnUnorderedEventList( List_t * pxEventList, const TickType_t xItemValue, const TickType_t xTicksToWait ) { + traceENTER_vTaskPlaceOnUnorderedEventList( pxEventList, xItemValue, xTicksToWait ); + configASSERT( pxEventList ); /* THIS FUNCTION MUST BE CALLED WITH THE SCHEDULER SUSPENDED. It is used by @@ -3189,6 +5333,8 @@ void vTaskPlaceOnUnorderedEventList( List_t * pxEventList, listINSERT_END( pxEventList, &( pxCurrentTCB->xEventListItem ) ); prvAddCurrentTaskToDelayedList( xTicksToWait, pdTRUE ); + + traceRETURN_vTaskPlaceOnUnorderedEventList(); } /*-----------------------------------------------------------*/ @@ -3198,6 +5344,8 @@ void vTaskPlaceOnUnorderedEventList( List_t * pxEventList, TickType_t xTicksToWait, const BaseType_t xWaitIndefinitely ) { + traceENTER_vTaskPlaceOnEventListRestricted( pxEventList, xTicksToWait, xWaitIndefinitely ); + configASSERT( pxEventList ); /* This function should not be called by application code hence the @@ -3222,6 +5370,8 @@ void vTaskPlaceOnUnorderedEventList( List_t * pxEventList, traceTASK_DELAY_UNTIL( ( xTickCount + xTicksToWait ) ); prvAddCurrentTaskToDelayedList( xTicksToWait, xWaitIndefinitely ); + + traceRETURN_vTaskPlaceOnEventListRestricted(); } #endif /* configUSE_TIMERS */ @@ -3232,6 +5382,8 @@ BaseType_t xTaskRemoveFromEventList( const List_t * const pxEventList ) TCB_t * pxUnblockedTCB; BaseType_t xReturn; + traceENTER_xTaskRemoveFromEventList( pxEventList ); + /* THIS FUNCTION MUST BE CALLED FROM A CRITICAL SECTION. It can also be * called from a critical section within an ISR. */ @@ -3245,7 +5397,10 @@ BaseType_t xTaskRemoveFromEventList( const List_t * const pxEventList ) * * This function assumes that a check has already been made to ensure that * pxEventList is not empty. */ - pxUnblockedTCB = listGET_OWNER_OF_HEAD_ENTRY( pxEventList ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */ + /* MISRA Ref 11.5.3 [Void pointer assignment] */ + /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-115 */ + /* coverity[misra_c_2012_rule_11_5_violation] */ + pxUnblockedTCB = listGET_OWNER_OF_HEAD_ENTRY( pxEventList ); configASSERT( pxUnblockedTCB ); listREMOVE_ITEM( &( pxUnblockedTCB->xEventListItem ) ); @@ -3275,22 +5430,42 @@ BaseType_t xTaskRemoveFromEventList( const List_t * const pxEventList ) listINSERT_END( &( xPendingReadyList ), &( pxUnblockedTCB->xEventListItem ) ); } - if( pxUnblockedTCB->uxPriority > pxCurrentTCB->uxPriority ) + #if ( configNUMBER_OF_CORES == 1 ) { - /* Return true if the task removed from the event list has a higher - * priority than the calling task. This allows the calling task to know if - * it should force a context switch now. */ - xReturn = pdTRUE; + if( pxUnblockedTCB->uxPriority > pxCurrentTCB->uxPriority ) + { + /* Return true if the task removed from the event list has a higher + * priority than the calling task. This allows the calling task to know if + * it should force a context switch now. */ + xReturn = pdTRUE; - /* Mark that a yield is pending in case the user is not using the - * "xHigherPriorityTaskWoken" parameter to an ISR safe FreeRTOS function. */ - xYieldPending = pdTRUE; + /* Mark that a yield is pending in case the user is not using the + * "xHigherPriorityTaskWoken" parameter to an ISR safe FreeRTOS function. */ + xYieldPendings[ 0 ] = pdTRUE; + } + else + { + xReturn = pdFALSE; + } } - else + #else /* #if ( configNUMBER_OF_CORES == 1 ) */ { xReturn = pdFALSE; + + #if ( configUSE_PREEMPTION == 1 ) + { + prvYieldForTask( pxUnblockedTCB ); + + if( xYieldPendings[ portGET_CORE_ID() ] != pdFALSE ) + { + xReturn = pdTRUE; + } + } + #endif /* #if ( configUSE_PREEMPTION == 1 ) */ } + #endif /* #if ( configNUMBER_OF_CORES == 1 ) */ + traceRETURN_xTaskRemoveFromEventList( xReturn ); return xReturn; } /*-----------------------------------------------------------*/ @@ -3300,6 +5475,8 @@ void vTaskRemoveFromUnorderedEventList( ListItem_t * pxEventListItem, { TCB_t * pxUnblockedTCB; + traceENTER_vTaskRemoveFromUnorderedEventList( pxEventListItem, xItemValue ); + /* THIS FUNCTION MUST BE CALLED WITH THE SCHEDULER SUSPENDED. It is used by * the event flags implementation. */ configASSERT( uxSchedulerSuspended != ( UBaseType_t ) 0U ); @@ -3309,7 +5486,10 @@ void vTaskRemoveFromUnorderedEventList( ListItem_t * pxEventListItem, /* Remove the event list form the event flag. Interrupts do not access * event flags. */ - pxUnblockedTCB = listGET_LIST_ITEM_OWNER( pxEventListItem ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */ + /* MISRA Ref 11.5.3 [Void pointer assignment] */ + /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-115 */ + /* coverity[misra_c_2012_rule_11_5_violation] */ + pxUnblockedTCB = listGET_LIST_ITEM_OWNER( pxEventListItem ); configASSERT( pxUnblockedTCB ); listREMOVE_ITEM( pxEventListItem ); @@ -3333,19 +5513,39 @@ void vTaskRemoveFromUnorderedEventList( ListItem_t * pxEventListItem, listREMOVE_ITEM( &( pxUnblockedTCB->xStateListItem ) ); prvAddTaskToReadyList( pxUnblockedTCB ); - if( pxUnblockedTCB->uxPriority > pxCurrentTCB->uxPriority ) + #if ( configNUMBER_OF_CORES == 1 ) { - /* The unblocked task has a priority above that of the calling task, so - * a context switch is required. This function is called with the - * scheduler suspended so xYieldPending is set so the context switch - * occurs immediately that the scheduler is resumed (unsuspended). */ - xYieldPending = pdTRUE; + if( pxUnblockedTCB->uxPriority > pxCurrentTCB->uxPriority ) + { + /* The unblocked task has a priority above that of the calling task, so + * a context switch is required. This function is called with the + * scheduler suspended so xYieldPending is set so the context switch + * occurs immediately that the scheduler is resumed (unsuspended). */ + xYieldPendings[ 0 ] = pdTRUE; + } + } + #else /* #if ( configNUMBER_OF_CORES == 1 ) */ + { + #if ( configUSE_PREEMPTION == 1 ) + { + taskENTER_CRITICAL(); + { + prvYieldForTask( pxUnblockedTCB ); + } + taskEXIT_CRITICAL(); + } + #endif } + #endif /* #if ( configNUMBER_OF_CORES == 1 ) */ + + traceRETURN_vTaskRemoveFromUnorderedEventList(); } /*-----------------------------------------------------------*/ void vTaskSetTimeOutState( TimeOut_t * const pxTimeOut ) { + traceENTER_vTaskSetTimeOutState( pxTimeOut ); + configASSERT( pxTimeOut ); taskENTER_CRITICAL(); { @@ -3353,14 +5553,20 @@ void vTaskSetTimeOutState( TimeOut_t * const pxTimeOut ) pxTimeOut->xTimeOnEntering = xTickCount; } taskEXIT_CRITICAL(); + + traceRETURN_vTaskSetTimeOutState(); } /*-----------------------------------------------------------*/ void vTaskInternalSetTimeOutState( TimeOut_t * const pxTimeOut ) { + traceENTER_vTaskInternalSetTimeOutState( pxTimeOut ); + /* For internal use only as it does not use a critical section. */ pxTimeOut->xOverflowCount = xNumOfOverflows; pxTimeOut->xTimeOnEntering = xTickCount; + + traceRETURN_vTaskInternalSetTimeOutState(); } /*-----------------------------------------------------------*/ @@ -3369,6 +5575,8 @@ BaseType_t xTaskCheckForTimeOut( TimeOut_t * const pxTimeOut, { BaseType_t xReturn; + traceENTER_xTaskCheckForTimeOut( pxTimeOut, pxTicksToWait ); + configASSERT( pxTimeOut ); configASSERT( pxTicksToWait ); @@ -3400,7 +5608,7 @@ BaseType_t xTaskCheckForTimeOut( TimeOut_t * const pxTimeOut, else #endif - if( ( xNumOfOverflows != pxTimeOut->xOverflowCount ) && ( xConstTickCount >= pxTimeOut->xTimeOnEntering ) ) /*lint !e525 Indentation preferred as is to make code within pre-processor directives clearer. */ + if( ( xNumOfOverflows != pxTimeOut->xOverflowCount ) && ( xConstTickCount >= pxTimeOut->xTimeOnEntering ) ) { /* The tick count is greater than the time at which * vTaskSetTimeout() was called, but has also overflowed since @@ -3410,7 +5618,7 @@ BaseType_t xTaskCheckForTimeOut( TimeOut_t * const pxTimeOut, xReturn = pdTRUE; *pxTicksToWait = ( TickType_t ) 0; } - else if( xElapsedTime < *pxTicksToWait ) /*lint !e961 Explicit casting is only redundant with some compilers, whereas others require it to prevent integer conversion errors. */ + else if( xElapsedTime < *pxTicksToWait ) { /* Not a genuine timeout. Adjust parameters for time remaining. */ *pxTicksToWait -= xElapsedTime; @@ -3425,13 +5633,20 @@ BaseType_t xTaskCheckForTimeOut( TimeOut_t * const pxTimeOut, } taskEXIT_CRITICAL(); + traceRETURN_xTaskCheckForTimeOut( xReturn ); + return xReturn; } /*-----------------------------------------------------------*/ void vTaskMissedYield( void ) { - xYieldPending = pdTRUE; + traceENTER_vTaskMissedYield(); + + /* Must be called from within a critical section. */ + xYieldPendings[ portGET_CORE_ID() ] = pdTRUE; + + traceRETURN_vTaskMissedYield(); } /*-----------------------------------------------------------*/ @@ -3442,6 +5657,8 @@ void vTaskMissedYield( void ) UBaseType_t uxReturn; TCB_t const * pxTCB; + traceENTER_uxTaskGetTaskNumber( xTask ); + if( xTask != NULL ) { pxTCB = xTask; @@ -3452,6 +5669,8 @@ void vTaskMissedYield( void ) uxReturn = 0U; } + traceRETURN_uxTaskGetTaskNumber( uxReturn ); + return uxReturn; } @@ -3465,18 +5684,97 @@ void vTaskMissedYield( void ) { TCB_t * pxTCB; + traceENTER_vTaskSetTaskNumber( xTask, uxHandle ); + if( xTask != NULL ) { pxTCB = xTask; pxTCB->uxTaskNumber = uxHandle; } + + traceRETURN_vTaskSetTaskNumber(); } #endif /* configUSE_TRACE_FACILITY */ +/*-----------------------------------------------------------*/ + +/* + * ----------------------------------------------------------- + * The passive idle task. + * ---------------------------------------------------------- + * + * The passive idle task is used for all the additional cores in a SMP + * system. There must be only 1 active idle task and the rest are passive + * idle tasks. + * + * The portTASK_FUNCTION() macro is used to allow port/compiler specific + * language extensions. The equivalent prototype for this function is: + * + * void prvPassiveIdleTask( void *pvParameters ); + */ + +#if ( configNUMBER_OF_CORES > 1 ) + static portTASK_FUNCTION( prvPassiveIdleTask, pvParameters ) + { + ( void ) pvParameters; + + taskYIELD(); + + for( ; configCONTROL_INFINITE_LOOP(); ) + { + #if ( configUSE_PREEMPTION == 0 ) + { + /* If we are not using preemption we keep forcing a task switch to + * see if any other task has become available. If we are using + * preemption we don't need to do this as any task becoming available + * will automatically get the processor anyway. */ + taskYIELD(); + } + #endif /* configUSE_PREEMPTION */ + + #if ( ( configUSE_PREEMPTION == 1 ) && ( configIDLE_SHOULD_YIELD == 1 ) ) + { + /* When using preemption tasks of equal priority will be + * timesliced. If a task that is sharing the idle priority is ready + * to run then the idle task should yield before the end of the + * timeslice. + * + * A critical region is not required here as we are just reading from + * the list, and an occasional incorrect value will not matter. If + * the ready list at the idle priority contains one more task than the + * number of idle tasks, which is equal to the configured numbers of cores + * then a task other than the idle task is ready to execute. */ + if( listCURRENT_LIST_LENGTH( &( pxReadyTasksLists[ tskIDLE_PRIORITY ] ) ) > ( UBaseType_t ) configNUMBER_OF_CORES ) + { + taskYIELD(); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + #endif /* ( ( configUSE_PREEMPTION == 1 ) && ( configIDLE_SHOULD_YIELD == 1 ) ) */ + + #if ( configUSE_PASSIVE_IDLE_HOOK == 1 ) + { + /* Call the user defined function from within the idle task. This + * allows the application designer to add background functionality + * without the overhead of a separate task. + * + * This hook is intended to manage core activity such as disabling cores that go idle. + * + * NOTE: vApplicationPassiveIdleHook() MUST NOT, UNDER ANY CIRCUMSTANCES, + * CALL A FUNCTION THAT MIGHT BLOCK. */ + vApplicationPassiveIdleHook(); + } + #endif /* configUSE_PASSIVE_IDLE_HOOK */ + } + } +#endif /* #if ( configNUMBER_OF_CORES > 1 ) */ /* * ----------------------------------------------------------- - * The Idle task. + * The idle task. * ---------------------------------------------------------- * * The portTASK_FUNCTION() macro is used to allow port/compiler specific @@ -3499,7 +5797,15 @@ static portTASK_FUNCTION( prvIdleTask, pvParameters ) * any. */ portALLOCATE_SECURE_CONTEXT( configMINIMAL_SECURE_STACK_SIZE ); - for( ; ; ) + #if ( configNUMBER_OF_CORES > 1 ) + { + /* SMP all cores start up in the idle task. This initial yield gets the application + * tasks started. */ + taskYIELD(); + } + #endif /* #if ( configNUMBER_OF_CORES > 1 ) */ + + for( ; configCONTROL_INFINITE_LOOP(); ) { /* See if any tasks have deleted themselves - if so then the idle task * is responsible for freeing the deleted task's TCB and stack. */ @@ -3524,9 +5830,10 @@ static portTASK_FUNCTION( prvIdleTask, pvParameters ) * * A critical region is not required here as we are just reading from * the list, and an occasional incorrect value will not matter. If - * the ready list at the idle priority contains more than one task + * the ready list at the idle priority contains one more task than the + * number of idle tasks, which is equal to the configured numbers of cores * then a task other than the idle task is ready to execute. */ - if( listCURRENT_LIST_LENGTH( &( pxReadyTasksLists[ tskIDLE_PRIORITY ] ) ) > ( UBaseType_t ) 1 ) + if( listCURRENT_LIST_LENGTH( &( pxReadyTasksLists[ tskIDLE_PRIORITY ] ) ) > ( UBaseType_t ) configNUMBER_OF_CORES ) { taskYIELD(); } @@ -3559,7 +5866,7 @@ static portTASK_FUNCTION( prvIdleTask, pvParameters ) * valid. */ xExpectedIdleTime = prvGetExpectedIdleTime(); - if( xExpectedIdleTime >= configEXPECTED_IDLE_TIME_BEFORE_SLEEP ) + if( xExpectedIdleTime >= ( TickType_t ) configEXPECTED_IDLE_TIME_BEFORE_SLEEP ) { vTaskSuspendAll(); { @@ -3574,7 +5881,7 @@ static portTASK_FUNCTION( prvIdleTask, pvParameters ) * portSUPPRESS_TICKS_AND_SLEEP() to be called. */ configPRE_SUPPRESS_TICKS_AND_SLEEP_PROCESSING( xExpectedIdleTime ); - if( xExpectedIdleTime >= configEXPECTED_IDLE_TIME_BEFORE_SLEEP ) + if( xExpectedIdleTime >= ( TickType_t ) configEXPECTED_IDLE_TIME_BEFORE_SLEEP ) { traceLOW_POWER_IDLE_BEGIN(); portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime ); @@ -3593,6 +5900,20 @@ static portTASK_FUNCTION( prvIdleTask, pvParameters ) } } #endif /* configUSE_TICKLESS_IDLE */ + + #if ( ( configNUMBER_OF_CORES > 1 ) && ( configUSE_PASSIVE_IDLE_HOOK == 1 ) ) + { + /* Call the user defined function from within the idle task. This + * allows the application designer to add background functionality + * without the overhead of a separate task. + * + * This hook is intended to manage core activity such as disabling cores that go idle. + * + * NOTE: vApplicationPassiveIdleHook() MUST NOT, UNDER ANY CIRCUMSTANCES, + * CALL A FUNCTION THAT MIGHT BLOCK. */ + vApplicationPassiveIdleHook(); + } + #endif /* #if ( ( configNUMBER_OF_CORES > 1 ) && ( configUSE_PASSIVE_IDLE_HOOK == 1 ) ) */ } } /*-----------------------------------------------------------*/ @@ -3603,24 +5924,26 @@ static portTASK_FUNCTION( prvIdleTask, pvParameters ) { #if ( INCLUDE_vTaskSuspend == 1 ) /* The idle task exists in addition to the application tasks. */ - const UBaseType_t uxNonApplicationTasks = 1; + const UBaseType_t uxNonApplicationTasks = configNUMBER_OF_CORES; #endif /* INCLUDE_vTaskSuspend */ eSleepModeStatus eReturn = eStandardSleep; + traceENTER_eTaskConfirmSleepModeStatus(); + /* This function must be called from a critical section. */ - if( listCURRENT_LIST_LENGTH( &xPendingReadyList ) != 0 ) + if( listCURRENT_LIST_LENGTH( &xPendingReadyList ) != 0U ) { /* A task was made ready while the scheduler was suspended. */ eReturn = eAbortSleep; } - else if( xYieldPending != pdFALSE ) + else if( xYieldPendings[ portGET_CORE_ID() ] != pdFALSE ) { /* A yield was pended while the scheduler was suspended. */ eReturn = eAbortSleep; } - else if( xPendedTicks != 0 ) + else if( xPendedTicks != 0U ) { /* A tick interrupt has already occurred but was held pending * because the scheduler is suspended. */ @@ -3642,6 +5965,8 @@ static portTASK_FUNCTION( prvIdleTask, pvParameters ) mtCOVERAGE_TEST_MARKER(); } + traceRETURN_eTaskConfirmSleepModeStatus( eReturn ); + return eReturn; } @@ -3656,13 +5981,17 @@ static portTASK_FUNCTION( prvIdleTask, pvParameters ) { TCB_t * pxTCB; + traceENTER_vTaskSetThreadLocalStoragePointer( xTaskToSet, xIndex, pvValue ); + if( ( xIndex >= 0 ) && - ( xIndex < configNUM_THREAD_LOCAL_STORAGE_POINTERS ) ) + ( xIndex < ( BaseType_t ) configNUM_THREAD_LOCAL_STORAGE_POINTERS ) ) { pxTCB = prvGetTCBFromHandle( xTaskToSet ); configASSERT( pxTCB != NULL ); pxTCB->pvThreadLocalStoragePointers[ xIndex ] = pvValue; } + + traceRETURN_vTaskSetThreadLocalStoragePointer(); } #endif /* configNUM_THREAD_LOCAL_STORAGE_POINTERS */ @@ -3676,8 +6005,10 @@ static portTASK_FUNCTION( prvIdleTask, pvParameters ) void * pvReturn = NULL; TCB_t * pxTCB; + traceENTER_pvTaskGetThreadLocalStoragePointer( xTaskToQuery, xIndex ); + if( ( xIndex >= 0 ) && - ( xIndex < configNUM_THREAD_LOCAL_STORAGE_POINTERS ) ) + ( xIndex < ( BaseType_t ) configNUM_THREAD_LOCAL_STORAGE_POINTERS ) ) { pxTCB = prvGetTCBFromHandle( xTaskToQuery ); pvReturn = pxTCB->pvThreadLocalStoragePointers[ xIndex ]; @@ -3687,6 +6018,8 @@ static portTASK_FUNCTION( prvIdleTask, pvParameters ) pvReturn = NULL; } + traceRETURN_pvTaskGetThreadLocalStoragePointer( pvReturn ); + return pvReturn; } @@ -3696,15 +6029,19 @@ static portTASK_FUNCTION( prvIdleTask, pvParameters ) #if ( portUSING_MPU_WRAPPERS == 1 ) void vTaskAllocateMPURegions( TaskHandle_t xTaskToModify, - const MemoryRegion_t * const xRegions ) + const MemoryRegion_t * const pxRegions ) { TCB_t * pxTCB; + traceENTER_vTaskAllocateMPURegions( xTaskToModify, pxRegions ); + /* If null is passed in here then we are modifying the MPU settings of * the calling task. */ pxTCB = prvGetTCBFromHandle( xTaskToModify ); - vPortStoreTaskMPUSettings( &( pxTCB->xMPUSettings ), xRegions, NULL, 0 ); + vPortStoreTaskMPUSettings( &( pxTCB->xMPUSettings ), pxRegions, NULL, 0 ); + + traceRETURN_vTaskAllocateMPURegions(); } #endif /* portUSING_MPU_WRAPPERS */ @@ -3754,16 +6091,64 @@ static void prvCheckTasksWaitingTermination( void ) * being called too often in the idle task. */ while( uxDeletedTasksWaitingCleanUp > ( UBaseType_t ) 0U ) { - taskENTER_CRITICAL(); + #if ( configNUMBER_OF_CORES == 1 ) { - pxTCB = listGET_OWNER_OF_HEAD_ENTRY( ( &xTasksWaitingTermination ) ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */ - ( void ) uxListRemove( &( pxTCB->xStateListItem ) ); - --uxCurrentNumberOfTasks; - --uxDeletedTasksWaitingCleanUp; + taskENTER_CRITICAL(); + { + { + /* MISRA Ref 11.5.3 [Void pointer assignment] */ + /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-115 */ + /* coverity[misra_c_2012_rule_11_5_violation] */ + pxTCB = listGET_OWNER_OF_HEAD_ENTRY( ( &xTasksWaitingTermination ) ); + ( void ) uxListRemove( &( pxTCB->xStateListItem ) ); + --uxCurrentNumberOfTasks; + --uxDeletedTasksWaitingCleanUp; + } + } + taskEXIT_CRITICAL(); + + prvDeleteTCB( pxTCB ); } - taskEXIT_CRITICAL(); + #else /* #if( configNUMBER_OF_CORES == 1 ) */ + { + pxTCB = NULL; + + taskENTER_CRITICAL(); + { + /* For SMP, multiple idles can be running simultaneously + * and we need to check that other idles did not cleanup while we were + * waiting to enter the critical section. */ + if( uxDeletedTasksWaitingCleanUp > ( UBaseType_t ) 0U ) + { + /* MISRA Ref 11.5.3 [Void pointer assignment] */ + /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-115 */ + /* coverity[misra_c_2012_rule_11_5_violation] */ + pxTCB = listGET_OWNER_OF_HEAD_ENTRY( ( &xTasksWaitingTermination ) ); + + if( pxTCB->xTaskRunState == taskTASK_NOT_RUNNING ) + { + ( void ) uxListRemove( &( pxTCB->xStateListItem ) ); + --uxCurrentNumberOfTasks; + --uxDeletedTasksWaitingCleanUp; + } + else + { + /* The TCB to be deleted still has not yet been switched out + * by the scheduler, so we will just exit this loop early and + * try again next time. */ + taskEXIT_CRITICAL(); + break; + } + } + } + taskEXIT_CRITICAL(); - prvDeleteTCB( pxTCB ); + if( pxTCB != NULL ) + { + prvDeleteTCB( pxTCB ); + } + } + #endif /* #if( configNUMBER_OF_CORES == 1 ) */ } } #endif /* INCLUDE_vTaskDelete */ @@ -3779,19 +6164,27 @@ static void prvCheckTasksWaitingTermination( void ) { TCB_t * pxTCB; + traceENTER_vTaskGetInfo( xTask, pxTaskStatus, xGetFreeStackSpace, eState ); + /* xTask is NULL then get the state of the calling task. */ pxTCB = prvGetTCBFromHandle( xTask ); - pxTaskStatus->xHandle = ( TaskHandle_t ) pxTCB; + pxTaskStatus->xHandle = pxTCB; pxTaskStatus->pcTaskName = ( const char * ) &( pxTCB->pcTaskName[ 0 ] ); pxTaskStatus->uxCurrentPriority = pxTCB->uxPriority; pxTaskStatus->pxStackBase = pxTCB->pxStack; - #if ( ( portSTACK_GROWTH > 0 ) && ( configRECORD_STACK_HIGH_ADDRESS == 1 ) ) - pxTaskStatus->pxTopOfStack = pxTCB->pxTopOfStack; + #if ( ( portSTACK_GROWTH > 0 ) || ( configRECORD_STACK_HIGH_ADDRESS == 1 ) ) + pxTaskStatus->pxTopOfStack = ( StackType_t * ) pxTCB->pxTopOfStack; pxTaskStatus->pxEndOfStack = pxTCB->pxEndOfStack; #endif pxTaskStatus->xTaskNumber = pxTCB->uxTCBNumber; + #if ( ( configUSE_CORE_AFFINITY == 1 ) && ( configNUMBER_OF_CORES > 1 ) ) + { + pxTaskStatus->uxCoreAffinityMask = pxTCB->uxCoreAffinityMask; + } + #endif + #if ( configUSE_MUTEXES == 1 ) { pxTaskStatus->uxBasePriority = pxTCB->uxBasePriority; @@ -3817,7 +6210,7 @@ static void prvCheckTasksWaitingTermination( void ) * state is just set to whatever is passed in. */ if( eState != eInvalid ) { - if( pxTCB == pxCurrentTCB ) + if( taskTASK_IS_RUNNING( pxTCB ) == pdTRUE ) { pxTaskStatus->eCurrentState = eRunning; } @@ -3838,6 +6231,24 @@ static void prvCheckTasksWaitingTermination( void ) { pxTaskStatus->eCurrentState = eBlocked; } + else + { + BaseType_t x; + + /* The task does not appear on the event list item of + * and of the RTOS objects, but could still be in the + * blocked state if it is waiting on its notification + * rather than waiting on an object. If not, is + * suspended. */ + for( x = ( BaseType_t ) 0; x < ( BaseType_t ) configTASK_NOTIFICATION_ARRAY_ENTRIES; x++ ) + { + if( pxTCB->ucNotifyState[ x ] == taskWAITING_NOTIFICATION ) + { + pxTaskStatus->eCurrentState = eBlocked; + break; + } + } + } } ( void ) xTaskResumeAll(); } @@ -3880,6 +6291,8 @@ static void prvCheckTasksWaitingTermination( void ) { pxTaskStatus->usStackHighWaterMark = 0; } + + traceRETURN_vTaskGetInfo(); } #endif /* configUSE_TRACE_FACILITY */ @@ -3897,7 +6310,10 @@ static void prvCheckTasksWaitingTermination( void ) if( listCURRENT_LIST_LENGTH( pxList ) > ( UBaseType_t ) 0 ) { - listGET_OWNER_OF_NEXT_ENTRY( pxFirstTCB, pxList ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */ + /* MISRA Ref 11.5.3 [Void pointer assignment] */ + /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-115 */ + /* coverity[misra_c_2012_rule_11_5_violation] */ + listGET_OWNER_OF_NEXT_ENTRY( pxFirstTCB, pxList ); /* Populate an TaskStatus_t structure within the * pxTaskStatusArray array for each task that is referenced from @@ -3905,7 +6321,10 @@ static void prvCheckTasksWaitingTermination( void ) * meaning of each TaskStatus_t structure member. */ do { - listGET_OWNER_OF_NEXT_ENTRY( pxNextTCB, pxList ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */ + /* MISRA Ref 11.5.3 [Void pointer assignment] */ + /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-115 */ + /* coverity[misra_c_2012_rule_11_5_violation] */ + listGET_OWNER_OF_NEXT_ENTRY( pxNextTCB, pxList ); vTaskGetInfo( ( TaskHandle_t ) pxNextTCB, &( pxTaskStatusArray[ uxTask ] ), pdTRUE, eState ); uxTask++; } while( pxNextTCB != pxFirstTCB ); @@ -3933,7 +6352,7 @@ static void prvCheckTasksWaitingTermination( void ) ulCount++; } - ulCount /= ( uint32_t ) sizeof( StackType_t ); /*lint !e961 Casting is not redundant on smaller architectures. */ + ulCount /= ( uint32_t ) sizeof( StackType_t ); return ( configSTACK_DEPTH_TYPE ) ulCount; } @@ -3954,6 +6373,8 @@ static void prvCheckTasksWaitingTermination( void ) uint8_t * pucEndOfStack; configSTACK_DEPTH_TYPE uxReturn; + traceENTER_uxTaskGetStackHighWaterMark2( xTask ); + /* uxTaskGetStackHighWaterMark() and uxTaskGetStackHighWaterMark2() are * the same except for their return type. Using configSTACK_DEPTH_TYPE * allows the user to determine the return type. It gets around the @@ -3975,6 +6396,8 @@ static void prvCheckTasksWaitingTermination( void ) uxReturn = prvTaskCheckFreeStackSpace( pucEndOfStack ); + traceRETURN_uxTaskGetStackHighWaterMark2( uxReturn ); + return uxReturn; } @@ -3989,6 +6412,8 @@ static void prvCheckTasksWaitingTermination( void ) uint8_t * pucEndOfStack; UBaseType_t uxReturn; + traceENTER_uxTaskGetStackHighWaterMark( xTask ); + pxTCB = prvGetTCBFromHandle( xTask ); #if portSTACK_GROWTH < 0 @@ -4003,6 +6428,8 @@ static void prvCheckTasksWaitingTermination( void ) uxReturn = ( UBaseType_t ) prvTaskCheckFreeStackSpace( pucEndOfStack ); + traceRETURN_uxTaskGetStackHighWaterMark( uxReturn ); + return uxReturn; } @@ -4021,7 +6448,7 @@ static void prvCheckTasksWaitingTermination( void ) #if ( configUSE_C_RUNTIME_TLS_SUPPORT == 1 ) { /* Free up the memory allocated for the task's TLS Block. */ - configDEINIT_TLS_BLOCK( pxCurrentTCB->xTLSBlock ); + configDEINIT_TLS_BLOCK( pxTCB->xTLSBlock ); } #endif @@ -4032,7 +6459,7 @@ static void prvCheckTasksWaitingTermination( void ) vPortFreeStack( pxTCB->pxStack ); vPortFree( pxTCB ); } - #elif ( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0 ) /*lint !e731 !e9029 Macro has been consolidated for readability reasons. */ + #elif ( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0 ) { /* The task could have been allocated statically or dynamically, so * check what was statically allocated before trying to free the @@ -4085,19 +6512,59 @@ static void prvResetNextTaskUnblockTime( void ) } /*-----------------------------------------------------------*/ -#if ( ( INCLUDE_xTaskGetCurrentTaskHandle == 1 ) || ( configUSE_MUTEXES == 1 ) ) +#if ( ( INCLUDE_xTaskGetCurrentTaskHandle == 1 ) || ( configUSE_MUTEXES == 1 ) ) || ( configNUMBER_OF_CORES > 1 ) - TaskHandle_t xTaskGetCurrentTaskHandle( void ) - { - TaskHandle_t xReturn; + #if ( configNUMBER_OF_CORES == 1 ) + TaskHandle_t xTaskGetCurrentTaskHandle( void ) + { + TaskHandle_t xReturn; - /* A critical section is not required as this is not called from - * an interrupt and the current TCB will always be the same for any - * individual execution thread. */ - xReturn = pxCurrentTCB; + traceENTER_xTaskGetCurrentTaskHandle(); - return xReturn; - } + /* A critical section is not required as this is not called from + * an interrupt and the current TCB will always be the same for any + * individual execution thread. */ + xReturn = pxCurrentTCB; + + traceRETURN_xTaskGetCurrentTaskHandle( xReturn ); + + return xReturn; + } + #else /* #if ( configNUMBER_OF_CORES == 1 ) */ + TaskHandle_t xTaskGetCurrentTaskHandle( void ) + { + TaskHandle_t xReturn; + UBaseType_t uxSavedInterruptStatus; + + traceENTER_xTaskGetCurrentTaskHandle(); + + uxSavedInterruptStatus = portSET_INTERRUPT_MASK(); + { + xReturn = pxCurrentTCBs[ portGET_CORE_ID() ]; + } + portCLEAR_INTERRUPT_MASK( uxSavedInterruptStatus ); + + traceRETURN_xTaskGetCurrentTaskHandle( xReturn ); + + return xReturn; + } + + TaskHandle_t xTaskGetCurrentTaskHandleForCore( BaseType_t xCoreID ) + { + TaskHandle_t xReturn = NULL; + + traceENTER_xTaskGetCurrentTaskHandleForCore( xCoreID ); + + if( taskVALID_CORE_ID( xCoreID ) != pdFALSE ) + { + xReturn = pxCurrentTCBs[ xCoreID ]; + } + + traceRETURN_xTaskGetCurrentTaskHandleForCore( xReturn ); + + return xReturn; + } + #endif /* #if ( configNUMBER_OF_CORES == 1 ) */ #endif /* ( ( INCLUDE_xTaskGetCurrentTaskHandle == 1 ) || ( configUSE_MUTEXES == 1 ) ) */ /*-----------------------------------------------------------*/ @@ -4108,22 +6575,34 @@ static void prvResetNextTaskUnblockTime( void ) { BaseType_t xReturn; + traceENTER_xTaskGetSchedulerState(); + if( xSchedulerRunning == pdFALSE ) { xReturn = taskSCHEDULER_NOT_STARTED; } else { - if( uxSchedulerSuspended == ( UBaseType_t ) 0U ) - { - xReturn = taskSCHEDULER_RUNNING; - } - else + #if ( configNUMBER_OF_CORES > 1 ) + taskENTER_CRITICAL(); + #endif { - xReturn = taskSCHEDULER_SUSPENDED; + if( uxSchedulerSuspended == ( UBaseType_t ) 0U ) + { + xReturn = taskSCHEDULER_RUNNING; + } + else + { + xReturn = taskSCHEDULER_SUSPENDED; + } } + #if ( configNUMBER_OF_CORES > 1 ) + taskEXIT_CRITICAL(); + #endif } + traceRETURN_xTaskGetSchedulerState( xReturn ); + return xReturn; } @@ -4137,9 +6616,10 @@ static void prvResetNextTaskUnblockTime( void ) TCB_t * const pxMutexHolderTCB = pxMutexHolder; BaseType_t xReturn = pdFALSE; - /* If the mutex was given back by an interrupt while the queue was - * locked then the mutex holder might now be NULL. _RB_ Is this still - * needed as interrupts can no longer use mutexes? */ + traceENTER_xTaskPriorityInherit( pxMutexHolder ); + + /* If the mutex is taken by an interrupt, the mutex holder is NULL. Priority + * inheritance is not applied in this scenario. */ if( pxMutexHolder != NULL ) { /* If the holder of the mutex has a priority below the priority of @@ -4150,9 +6630,9 @@ static void prvResetNextTaskUnblockTime( void ) /* Adjust the mutex holder state to account for its new * priority. Only reset the event list item value if the value is * not being used for anything else. */ - if( ( listGET_LIST_ITEM_VALUE( &( pxMutexHolderTCB->xEventListItem ) ) & taskEVENT_LIST_ITEM_VALUE_IN_USE ) == 0UL ) + if( ( listGET_LIST_ITEM_VALUE( &( pxMutexHolderTCB->xEventListItem ) ) & taskEVENT_LIST_ITEM_VALUE_IN_USE ) == ( ( TickType_t ) 0UL ) ) { - listSET_LIST_ITEM_VALUE( &( pxMutexHolderTCB->xEventListItem ), ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) pxCurrentTCB->uxPriority ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */ + listSET_LIST_ITEM_VALUE( &( pxMutexHolderTCB->xEventListItem ), ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) pxCurrentTCB->uxPriority ); } else { @@ -4178,6 +6658,16 @@ static void prvResetNextTaskUnblockTime( void ) /* Inherit the priority before being moved into the new list. */ pxMutexHolderTCB->uxPriority = pxCurrentTCB->uxPriority; prvAddTaskToReadyList( pxMutexHolderTCB ); + #if ( configNUMBER_OF_CORES > 1 ) + { + /* The priority of the task is raised. Yield for this task + * if it is not running. */ + if( taskTASK_IS_RUNNING( pxMutexHolderTCB ) != pdTRUE ) + { + prvYieldForTask( pxMutexHolderTCB ); + } + } + #endif /* if ( configNUMBER_OF_CORES > 1 ) */ } else { @@ -4214,6 +6704,8 @@ static void prvResetNextTaskUnblockTime( void ) mtCOVERAGE_TEST_MARKER(); } + traceRETURN_xTaskPriorityInherit( xReturn ); + return xReturn; } @@ -4227,6 +6719,8 @@ static void prvResetNextTaskUnblockTime( void ) TCB_t * const pxTCB = pxMutexHolder; BaseType_t xReturn = pdFALSE; + traceENTER_xTaskPriorityDisinherit( pxMutexHolder ); + if( pxMutexHolder != NULL ) { /* A task can only have an inherited priority if it holds the mutex. @@ -4266,8 +6760,18 @@ static void prvResetNextTaskUnblockTime( void ) /* Reset the event list item value. It cannot be in use for * any other purpose if this task is running, and it must be * running to give back the mutex. */ - listSET_LIST_ITEM_VALUE( &( pxTCB->xEventListItem ), ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) pxTCB->uxPriority ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */ + listSET_LIST_ITEM_VALUE( &( pxTCB->xEventListItem ), ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) pxTCB->uxPriority ); prvAddTaskToReadyList( pxTCB ); + #if ( configNUMBER_OF_CORES > 1 ) + { + /* The priority of the task is dropped. Yield the core on + * which the task is running. */ + if( taskTASK_IS_RUNNING( pxTCB ) == pdTRUE ) + { + prvYieldCore( pxTCB->xTaskRunState ); + } + } + #endif /* if ( configNUMBER_OF_CORES > 1 ) */ /* Return true to indicate that a context switch is required. * This is only actually required in the corner case whereby @@ -4294,6 +6798,8 @@ static void prvResetNextTaskUnblockTime( void ) mtCOVERAGE_TEST_MARKER(); } + traceRETURN_xTaskPriorityDisinherit( xReturn ); + return xReturn; } @@ -4309,6 +6815,8 @@ static void prvResetNextTaskUnblockTime( void ) UBaseType_t uxPriorityUsedOnEntry, uxPriorityToUse; const UBaseType_t uxOnlyOneMutexHeld = ( UBaseType_t ) 1; + traceENTER_vTaskPriorityDisinheritAfterTimeout( pxMutexHolder, uxHighestPriorityWaitingTask ); + if( pxMutexHolder != NULL ) { /* If pxMutexHolder is not NULL then the holder must hold at least @@ -4351,9 +6859,9 @@ static void prvResetNextTaskUnblockTime( void ) /* Only reset the event list item value if the value is not * being used for anything else. */ - if( ( listGET_LIST_ITEM_VALUE( &( pxTCB->xEventListItem ) ) & taskEVENT_LIST_ITEM_VALUE_IN_USE ) == 0UL ) + if( ( listGET_LIST_ITEM_VALUE( &( pxTCB->xEventListItem ) ) & taskEVENT_LIST_ITEM_VALUE_IN_USE ) == ( ( TickType_t ) 0UL ) ) { - listSET_LIST_ITEM_VALUE( &( pxTCB->xEventListItem ), ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) uxPriorityToUse ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */ + listSET_LIST_ITEM_VALUE( &( pxTCB->xEventListItem ), ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) uxPriorityToUse ); } else { @@ -4381,10 +6889,267 @@ static void prvResetNextTaskUnblockTime( void ) } prvAddTaskToReadyList( pxTCB ); + #if ( configNUMBER_OF_CORES > 1 ) + { + /* The priority of the task is dropped. Yield the core on + * which the task is running. */ + if( taskTASK_IS_RUNNING( pxTCB ) == pdTRUE ) + { + prvYieldCore( pxTCB->xTaskRunState ); + } + } + #endif /* if ( configNUMBER_OF_CORES > 1 ) */ } else { - mtCOVERAGE_TEST_MARKER(); + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + traceRETURN_vTaskPriorityDisinheritAfterTimeout(); + } + +#endif /* configUSE_MUTEXES */ +/*-----------------------------------------------------------*/ + +#if ( configNUMBER_OF_CORES > 1 ) + +/* If not in a critical section then yield immediately. + * Otherwise set xYieldPendings to true to wait to + * yield until exiting the critical section. + */ + void vTaskYieldWithinAPI( void ) + { + traceENTER_vTaskYieldWithinAPI(); + + if( portGET_CRITICAL_NESTING_COUNT() == 0U ) + { + portYIELD(); + } + else + { + xYieldPendings[ portGET_CORE_ID() ] = pdTRUE; + } + + traceRETURN_vTaskYieldWithinAPI(); + } +#endif /* #if ( configNUMBER_OF_CORES > 1 ) */ + +/*-----------------------------------------------------------*/ + +#if ( ( portCRITICAL_NESTING_IN_TCB == 1 ) && ( configNUMBER_OF_CORES == 1 ) ) + + void vTaskEnterCritical( void ) + { + traceENTER_vTaskEnterCritical(); + + portDISABLE_INTERRUPTS(); + + if( xSchedulerRunning != pdFALSE ) + { + ( pxCurrentTCB->uxCriticalNesting )++; + + /* This is not the interrupt safe version of the enter critical + * function so assert() if it is being called from an interrupt + * context. Only API functions that end in "FromISR" can be used in an + * interrupt. Only assert if the critical nesting count is 1 to + * protect against recursive calls if the assert function also uses a + * critical section. */ + if( pxCurrentTCB->uxCriticalNesting == 1U ) + { + portASSERT_IF_IN_ISR(); + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + traceRETURN_vTaskEnterCritical(); + } + +#endif /* #if ( ( portCRITICAL_NESTING_IN_TCB == 1 ) && ( configNUMBER_OF_CORES == 1 ) ) */ +/*-----------------------------------------------------------*/ + +#if ( configNUMBER_OF_CORES > 1 ) + + void vTaskEnterCritical( void ) + { + traceENTER_vTaskEnterCritical(); + + portDISABLE_INTERRUPTS(); + + if( xSchedulerRunning != pdFALSE ) + { + if( portGET_CRITICAL_NESTING_COUNT() == 0U ) + { + portGET_TASK_LOCK(); + portGET_ISR_LOCK(); + } + + portINCREMENT_CRITICAL_NESTING_COUNT(); + + /* This is not the interrupt safe version of the enter critical + * function so assert() if it is being called from an interrupt + * context. Only API functions that end in "FromISR" can be used in an + * interrupt. Only assert if the critical nesting count is 1 to + * protect against recursive calls if the assert function also uses a + * critical section. */ + if( portGET_CRITICAL_NESTING_COUNT() == 1U ) + { + portASSERT_IF_IN_ISR(); + + if( uxSchedulerSuspended == 0U ) + { + /* The only time there would be a problem is if this is called + * before a context switch and vTaskExitCritical() is called + * after pxCurrentTCB changes. Therefore this should not be + * used within vTaskSwitchContext(). */ + prvCheckForRunStateChange(); + } + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + traceRETURN_vTaskEnterCritical(); + } + +#endif /* #if ( configNUMBER_OF_CORES > 1 ) */ + +/*-----------------------------------------------------------*/ + +#if ( configNUMBER_OF_CORES > 1 ) + + UBaseType_t vTaskEnterCriticalFromISR( void ) + { + UBaseType_t uxSavedInterruptStatus = 0; + + traceENTER_vTaskEnterCriticalFromISR(); + + if( xSchedulerRunning != pdFALSE ) + { + uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR(); + + if( portGET_CRITICAL_NESTING_COUNT() == 0U ) + { + portGET_ISR_LOCK(); + } + + portINCREMENT_CRITICAL_NESTING_COUNT(); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + traceRETURN_vTaskEnterCriticalFromISR( uxSavedInterruptStatus ); + + return uxSavedInterruptStatus; + } + +#endif /* #if ( configNUMBER_OF_CORES > 1 ) */ +/*-----------------------------------------------------------*/ + +#if ( ( portCRITICAL_NESTING_IN_TCB == 1 ) && ( configNUMBER_OF_CORES == 1 ) ) + + void vTaskExitCritical( void ) + { + traceENTER_vTaskExitCritical(); + + if( xSchedulerRunning != pdFALSE ) + { + /* If pxCurrentTCB->uxCriticalNesting is zero then this function + * does not match a previous call to vTaskEnterCritical(). */ + configASSERT( pxCurrentTCB->uxCriticalNesting > 0U ); + + /* This function should not be called in ISR. Use vTaskExitCriticalFromISR + * to exit critical section from ISR. */ + portASSERT_IF_IN_ISR(); + + if( pxCurrentTCB->uxCriticalNesting > 0U ) + { + ( pxCurrentTCB->uxCriticalNesting )--; + + if( pxCurrentTCB->uxCriticalNesting == 0U ) + { + portENABLE_INTERRUPTS(); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + traceRETURN_vTaskExitCritical(); + } + +#endif /* #if ( ( portCRITICAL_NESTING_IN_TCB == 1 ) && ( configNUMBER_OF_CORES == 1 ) ) */ +/*-----------------------------------------------------------*/ + +#if ( configNUMBER_OF_CORES > 1 ) + + void vTaskExitCritical( void ) + { + traceENTER_vTaskExitCritical(); + + if( xSchedulerRunning != pdFALSE ) + { + /* If critical nesting count is zero then this function + * does not match a previous call to vTaskEnterCritical(). */ + configASSERT( portGET_CRITICAL_NESTING_COUNT() > 0U ); + + /* This function should not be called in ISR. Use vTaskExitCriticalFromISR + * to exit critical section from ISR. */ + portASSERT_IF_IN_ISR(); + + if( portGET_CRITICAL_NESTING_COUNT() > 0U ) + { + portDECREMENT_CRITICAL_NESTING_COUNT(); + + if( portGET_CRITICAL_NESTING_COUNT() == 0U ) + { + BaseType_t xYieldCurrentTask; + + /* Get the xYieldPending stats inside the critical section. */ + xYieldCurrentTask = xYieldPendings[ portGET_CORE_ID() ]; + + portRELEASE_ISR_LOCK(); + portRELEASE_TASK_LOCK(); + portENABLE_INTERRUPTS(); + + /* When a task yields in a critical section it just sets + * xYieldPending to true. So now that we have exited the + * critical section check if xYieldPending is true, and + * if so yield. */ + if( xYieldCurrentTask != pdFALSE ) + { + portYIELD(); } } else @@ -4401,54 +7166,33 @@ static void prvResetNextTaskUnblockTime( void ) { mtCOVERAGE_TEST_MARKER(); } + + traceRETURN_vTaskExitCritical(); } -#endif /* configUSE_MUTEXES */ +#endif /* #if ( configNUMBER_OF_CORES > 1 ) */ /*-----------------------------------------------------------*/ -#if ( portCRITICAL_NESTING_IN_TCB == 1 ) +#if ( configNUMBER_OF_CORES > 1 ) - void vTaskEnterCritical( void ) + void vTaskExitCriticalFromISR( UBaseType_t uxSavedInterruptStatus ) { - portDISABLE_INTERRUPTS(); + traceENTER_vTaskExitCriticalFromISR( uxSavedInterruptStatus ); if( xSchedulerRunning != pdFALSE ) { - ( pxCurrentTCB->uxCriticalNesting )++; - - /* This is not the interrupt safe version of the enter critical - * function so assert() if it is being called from an interrupt - * context. Only API functions that end in "FromISR" can be used in an - * interrupt. Only assert if the critical nesting count is 1 to - * protect against recursive calls if the assert function also uses a - * critical section. */ - if( pxCurrentTCB->uxCriticalNesting == 1 ) - { - portASSERT_IF_IN_ISR(); - } - } - else - { - mtCOVERAGE_TEST_MARKER(); - } - } - -#endif /* portCRITICAL_NESTING_IN_TCB */ -/*-----------------------------------------------------------*/ - -#if ( portCRITICAL_NESTING_IN_TCB == 1 ) + /* If critical nesting count is zero then this function + * does not match a previous call to vTaskEnterCritical(). */ + configASSERT( portGET_CRITICAL_NESTING_COUNT() > 0U ); - void vTaskExitCritical( void ) - { - if( xSchedulerRunning != pdFALSE ) - { - if( pxCurrentTCB->uxCriticalNesting > 0U ) + if( portGET_CRITICAL_NESTING_COUNT() > 0U ) { - ( pxCurrentTCB->uxCriticalNesting )--; + portDECREMENT_CRITICAL_NESTING_COUNT(); - if( pxCurrentTCB->uxCriticalNesting == 0U ) + if( portGET_CRITICAL_NESTING_COUNT() == 0U ) { - portENABLE_INTERRUPTS(); + portRELEASE_ISR_LOCK(); + portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus ); } else { @@ -4464,9 +7208,11 @@ static void prvResetNextTaskUnblockTime( void ) { mtCOVERAGE_TEST_MARKER(); } + + traceRETURN_vTaskExitCriticalFromISR(); } -#endif /* portCRITICAL_NESTING_IN_TCB */ +#endif /* #if ( configNUMBER_OF_CORES > 1 ) */ /*-----------------------------------------------------------*/ #if ( configUSE_STATS_FORMATTING_FUNCTIONS > 0 ) @@ -4477,11 +7223,11 @@ static void prvResetNextTaskUnblockTime( void ) size_t x; /* Start by copying the entire string. */ - strcpy( pcBuffer, pcTaskName ); + ( void ) strcpy( pcBuffer, pcTaskName ); /* Pad the end of the string with spaces to ensure columns line up when * printed out. */ - for( x = strlen( pcBuffer ); x < ( size_t ) ( configMAX_TASK_NAME_LEN - 1 ); x++ ) + for( x = strlen( pcBuffer ); x < ( size_t ) ( ( size_t ) configMAX_TASK_NAME_LEN - 1U ); x++ ) { pcBuffer[ x ] = ' '; } @@ -4498,12 +7244,19 @@ static void prvResetNextTaskUnblockTime( void ) #if ( ( configUSE_TRACE_FACILITY == 1 ) && ( configUSE_STATS_FORMATTING_FUNCTIONS > 0 ) ) - void vTaskList( char * pcWriteBuffer ) + void vTaskListTasks( char * pcWriteBuffer, + size_t uxBufferLength ) { TaskStatus_t * pxTaskStatusArray; + size_t uxConsumedBufferLength = 0; + size_t uxCharsWrittenBySnprintf; + int iSnprintfReturnValue; + BaseType_t xOutputBufferFull = pdFALSE; UBaseType_t uxArraySize, x; char cStatus; + traceENTER_vTaskListTasks( pcWriteBuffer, uxBufferLength ); + /* * PLEASE NOTE: * @@ -4511,23 +7264,23 @@ static void prvResetNextTaskUnblockTime( void ) * of the demo applications. Do not consider it to be part of the * scheduler. * - * vTaskList() calls uxTaskGetSystemState(), then formats part of the + * vTaskListTasks() calls uxTaskGetSystemState(), then formats part of the * uxTaskGetSystemState() output into a human readable table that * displays task: names, states, priority, stack usage and task number. * Stack usage specified as the number of unused StackType_t words stack can hold * on top of stack - not the number of bytes. * - * vTaskList() has a dependency on the sprintf() C library function that + * vTaskListTasks() has a dependency on the snprintf() C library function that * might bloat the code size, use a lot of stack, and provide different * results on different platforms. An alternative, tiny, third party, - * and limited functionality implementation of sprintf() is provided in + * and limited functionality implementation of snprintf() is provided in * many of the FreeRTOS/Demo sub-directories in a file called * printf-stdarg.c (note printf-stdarg.c does not provide a full * snprintf() implementation!). * * It is recommended that production systems call uxTaskGetSystemState() * directly to get access to raw stats data, rather than indirectly - * through a call to vTaskList(). + * through a call to vTaskListTasks(). */ @@ -4541,7 +7294,10 @@ static void prvResetNextTaskUnblockTime( void ) /* Allocate an array index for each task. NOTE! if * configSUPPORT_DYNAMIC_ALLOCATION is set to 0 then pvPortMalloc() will * equate to NULL. */ - pxTaskStatusArray = pvPortMalloc( uxCurrentNumberOfTasks * sizeof( TaskStatus_t ) ); /*lint !e9079 All values returned by pvPortMalloc() have at least the alignment required by the MCU's stack and this allocation allocates a struct that has the alignment requirements of a pointer. */ + /* MISRA Ref 11.5.1 [Malloc memory assignment] */ + /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-115 */ + /* coverity[misra_c_2012_rule_11_5_violation] */ + pxTaskStatusArray = pvPortMalloc( uxCurrentNumberOfTasks * sizeof( TaskStatus_t ) ); if( pxTaskStatusArray != NULL ) { @@ -4580,13 +7336,65 @@ static void prvResetNextTaskUnblockTime( void ) break; } - /* Write the task name to the string, padding with spaces so it - * can be printed in tabular form more easily. */ - pcWriteBuffer = prvWriteNameToBuffer( pcWriteBuffer, pxTaskStatusArray[ x ].pcTaskName ); + /* Is there enough space in the buffer to hold task name? */ + if( ( uxConsumedBufferLength + configMAX_TASK_NAME_LEN ) <= uxBufferLength ) + { + /* Write the task name to the string, padding with spaces so it + * can be printed in tabular form more easily. */ + pcWriteBuffer = prvWriteNameToBuffer( pcWriteBuffer, pxTaskStatusArray[ x ].pcTaskName ); + /* Do not count the terminating null character. */ + uxConsumedBufferLength = uxConsumedBufferLength + ( configMAX_TASK_NAME_LEN - 1U ); + + /* Is there space left in the buffer? -1 is done because snprintf + * writes a terminating null character. So we are essentially + * checking if the buffer has space to write at least one non-null + * character. */ + if( uxConsumedBufferLength < ( uxBufferLength - 1U ) ) + { + /* Write the rest of the string. */ + #if ( ( configUSE_CORE_AFFINITY == 1 ) && ( configNUMBER_OF_CORES > 1 ) ) + /* MISRA Ref 21.6.1 [snprintf for utility] */ + /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-216 */ + /* coverity[misra_c_2012_rule_21_6_violation] */ + iSnprintfReturnValue = snprintf( pcWriteBuffer, + uxBufferLength - uxConsumedBufferLength, + "\t%c\t%u\t%u\t%u\t0x%x\r\n", + cStatus, + ( unsigned int ) pxTaskStatusArray[ x ].uxCurrentPriority, + ( unsigned int ) pxTaskStatusArray[ x ].usStackHighWaterMark, + ( unsigned int ) pxTaskStatusArray[ x ].xTaskNumber, + ( unsigned int ) pxTaskStatusArray[ x ].uxCoreAffinityMask ); + #else /* ( ( configUSE_CORE_AFFINITY == 1 ) && ( configNUMBER_OF_CORES > 1 ) ) */ + /* MISRA Ref 21.6.1 [snprintf for utility] */ + /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-216 */ + /* coverity[misra_c_2012_rule_21_6_violation] */ + iSnprintfReturnValue = snprintf( pcWriteBuffer, + uxBufferLength - uxConsumedBufferLength, + "\t%c\t%u\t%u\t%u\r\n", + cStatus, + ( unsigned int ) pxTaskStatusArray[ x ].uxCurrentPriority, + ( unsigned int ) pxTaskStatusArray[ x ].usStackHighWaterMark, + ( unsigned int ) pxTaskStatusArray[ x ].xTaskNumber ); + #endif /* ( ( configUSE_CORE_AFFINITY == 1 ) && ( configNUMBER_OF_CORES > 1 ) ) */ + uxCharsWrittenBySnprintf = prvSnprintfReturnValueToCharsWritten( iSnprintfReturnValue, uxBufferLength - uxConsumedBufferLength ); + + uxConsumedBufferLength += uxCharsWrittenBySnprintf; + pcWriteBuffer += uxCharsWrittenBySnprintf; + } + else + { + xOutputBufferFull = pdTRUE; + } + } + else + { + xOutputBufferFull = pdTRUE; + } - /* Write the rest of the string. */ - sprintf( pcWriteBuffer, "\t%c\t%u\t%u\t%u\r\n", cStatus, ( unsigned int ) pxTaskStatusArray[ x ].uxCurrentPriority, ( unsigned int ) pxTaskStatusArray[ x ].usStackHighWaterMark, ( unsigned int ) pxTaskStatusArray[ x ].xTaskNumber ); /*lint !e586 sprintf() allowed as this is compiled with many compilers and this is a utility function only - not part of the core kernel implementation. */ - pcWriteBuffer += strlen( pcWriteBuffer ); /*lint !e9016 Pointer arithmetic ok on char pointers especially as in this case where it best denotes the intent of the code. */ + if( xOutputBufferFull == pdTRUE ) + { + break; + } } /* Free the array again. NOTE! If configSUPPORT_DYNAMIC_ALLOCATION @@ -4597,6 +7405,8 @@ static void prvResetNextTaskUnblockTime( void ) { mtCOVERAGE_TEST_MARKER(); } + + traceRETURN_vTaskListTasks(); } #endif /* ( ( configUSE_TRACE_FACILITY == 1 ) && ( configUSE_STATS_FORMATTING_FUNCTIONS > 0 ) ) */ @@ -4604,11 +7414,19 @@ static void prvResetNextTaskUnblockTime( void ) #if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( configUSE_STATS_FORMATTING_FUNCTIONS > 0 ) && ( configUSE_TRACE_FACILITY == 1 ) ) - void vTaskGetRunTimeStats( char * pcWriteBuffer ) + void vTaskGetRunTimeStatistics( char * pcWriteBuffer, + size_t uxBufferLength ) { TaskStatus_t * pxTaskStatusArray; + size_t uxConsumedBufferLength = 0; + size_t uxCharsWrittenBySnprintf; + int iSnprintfReturnValue; + BaseType_t xOutputBufferFull = pdFALSE; UBaseType_t uxArraySize, x; - configRUN_TIME_COUNTER_TYPE ulTotalTime, ulStatsAsPercentage; + configRUN_TIME_COUNTER_TYPE ulTotalTime = 0; + configRUN_TIME_COUNTER_TYPE ulStatsAsPercentage; + + traceENTER_vTaskGetRunTimeStatistics( pcWriteBuffer, uxBufferLength ); /* * PLEASE NOTE: @@ -4617,22 +7435,22 @@ static void prvResetNextTaskUnblockTime( void ) * of the demo applications. Do not consider it to be part of the * scheduler. * - * vTaskGetRunTimeStats() calls uxTaskGetSystemState(), then formats part + * vTaskGetRunTimeStatistics() calls uxTaskGetSystemState(), then formats part * of the uxTaskGetSystemState() output into a human readable table that * displays the amount of time each task has spent in the Running state * in both absolute and percentage terms. * - * vTaskGetRunTimeStats() has a dependency on the sprintf() C library + * vTaskGetRunTimeStatistics() has a dependency on the snprintf() C library * function that might bloat the code size, use a lot of stack, and * provide different results on different platforms. An alternative, * tiny, third party, and limited functionality implementation of - * sprintf() is provided in many of the FreeRTOS/Demo sub-directories in + * snprintf() is provided in many of the FreeRTOS/Demo sub-directories in * a file called printf-stdarg.c (note printf-stdarg.c does not provide * a full snprintf() implementation!). * * It is recommended that production systems call uxTaskGetSystemState() * directly to get access to raw stats data, rather than indirectly - * through a call to vTaskGetRunTimeStats(). + * through a call to vTaskGetRunTimeStatistics(). */ /* Make sure the write buffer does not contain a string. */ @@ -4645,7 +7463,10 @@ static void prvResetNextTaskUnblockTime( void ) /* Allocate an array index for each task. NOTE! If * configSUPPORT_DYNAMIC_ALLOCATION is set to 0 then pvPortMalloc() will * equate to NULL. */ - pxTaskStatusArray = pvPortMalloc( uxCurrentNumberOfTasks * sizeof( TaskStatus_t ) ); /*lint !e9079 All values returned by pvPortMalloc() have at least the alignment required by the MCU's stack and this allocation allocates a struct that has the alignment requirements of a pointer. */ + /* MISRA Ref 11.5.1 [Malloc memory assignment] */ + /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-115 */ + /* coverity[misra_c_2012_rule_11_5_violation] */ + pxTaskStatusArray = pvPortMalloc( uxCurrentNumberOfTasks * sizeof( TaskStatus_t ) ); if( pxTaskStatusArray != NULL ) { @@ -4653,7 +7474,7 @@ static void prvResetNextTaskUnblockTime( void ) uxArraySize = uxTaskGetSystemState( pxTaskStatusArray, uxArraySize, &ulTotalTime ); /* For percentage calculations. */ - ulTotalTime /= 100UL; + ulTotalTime /= ( ( configRUN_TIME_COUNTER_TYPE ) 100UL ); /* Avoid divide by zero errors. */ if( ulTotalTime > 0UL ) @@ -4666,43 +7487,97 @@ static void prvResetNextTaskUnblockTime( void ) * ulTotalRunTime has already been divided by 100. */ ulStatsAsPercentage = pxTaskStatusArray[ x ].ulRunTimeCounter / ulTotalTime; - /* Write the task name to the string, padding with - * spaces so it can be printed in tabular form more - * easily. */ - pcWriteBuffer = prvWriteNameToBuffer( pcWriteBuffer, pxTaskStatusArray[ x ].pcTaskName ); - - if( ulStatsAsPercentage > 0UL ) + /* Is there enough space in the buffer to hold task name? */ + if( ( uxConsumedBufferLength + configMAX_TASK_NAME_LEN ) <= uxBufferLength ) { - #ifdef portLU_PRINTF_SPECIFIER_REQUIRED + /* Write the task name to the string, padding with + * spaces so it can be printed in tabular form more + * easily. */ + pcWriteBuffer = prvWriteNameToBuffer( pcWriteBuffer, pxTaskStatusArray[ x ].pcTaskName ); + /* Do not count the terminating null character. */ + uxConsumedBufferLength = uxConsumedBufferLength + ( configMAX_TASK_NAME_LEN - 1U ); + + /* Is there space left in the buffer? -1 is done because snprintf + * writes a terminating null character. So we are essentially + * checking if the buffer has space to write at least one non-null + * character. */ + if( uxConsumedBufferLength < ( uxBufferLength - 1U ) ) { - sprintf( pcWriteBuffer, "\t%lu\t\t%lu%%\r\n", pxTaskStatusArray[ x ].ulRunTimeCounter, ulStatsAsPercentage ); + if( ulStatsAsPercentage > 0UL ) + { + #ifdef portLU_PRINTF_SPECIFIER_REQUIRED + { + /* MISRA Ref 21.6.1 [snprintf for utility] */ + /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-216 */ + /* coverity[misra_c_2012_rule_21_6_violation] */ + iSnprintfReturnValue = snprintf( pcWriteBuffer, + uxBufferLength - uxConsumedBufferLength, + "\t%lu\t\t%lu%%\r\n", + pxTaskStatusArray[ x ].ulRunTimeCounter, + ulStatsAsPercentage ); + } + #else /* ifdef portLU_PRINTF_SPECIFIER_REQUIRED */ + { + /* sizeof( int ) == sizeof( long ) so a smaller + * printf() library can be used. */ + /* MISRA Ref 21.6.1 [snprintf for utility] */ + /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-216 */ + /* coverity[misra_c_2012_rule_21_6_violation] */ + iSnprintfReturnValue = snprintf( pcWriteBuffer, + uxBufferLength - uxConsumedBufferLength, + "\t%u\t\t%u%%\r\n", + ( unsigned int ) pxTaskStatusArray[ x ].ulRunTimeCounter, + ( unsigned int ) ulStatsAsPercentage ); + } + #endif /* ifdef portLU_PRINTF_SPECIFIER_REQUIRED */ + } + else + { + /* If the percentage is zero here then the task has + * consumed less than 1% of the total run time. */ + #ifdef portLU_PRINTF_SPECIFIER_REQUIRED + { + /* MISRA Ref 21.6.1 [snprintf for utility] */ + /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-216 */ + /* coverity[misra_c_2012_rule_21_6_violation] */ + iSnprintfReturnValue = snprintf( pcWriteBuffer, + uxBufferLength - uxConsumedBufferLength, + "\t%lu\t\t<1%%\r\n", + pxTaskStatusArray[ x ].ulRunTimeCounter ); + } + #else + { + /* sizeof( int ) == sizeof( long ) so a smaller + * printf() library can be used. */ + /* MISRA Ref 21.6.1 [snprintf for utility] */ + /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-216 */ + /* coverity[misra_c_2012_rule_21_6_violation] */ + iSnprintfReturnValue = snprintf( pcWriteBuffer, + uxBufferLength - uxConsumedBufferLength, + "\t%u\t\t<1%%\r\n", + ( unsigned int ) pxTaskStatusArray[ x ].ulRunTimeCounter ); + } + #endif /* ifdef portLU_PRINTF_SPECIFIER_REQUIRED */ + } + + uxCharsWrittenBySnprintf = prvSnprintfReturnValueToCharsWritten( iSnprintfReturnValue, uxBufferLength - uxConsumedBufferLength ); + uxConsumedBufferLength += uxCharsWrittenBySnprintf; + pcWriteBuffer += uxCharsWrittenBySnprintf; } - #else + else { - /* sizeof( int ) == sizeof( long ) so a smaller - * printf() library can be used. */ - sprintf( pcWriteBuffer, "\t%u\t\t%u%%\r\n", ( unsigned int ) pxTaskStatusArray[ x ].ulRunTimeCounter, ( unsigned int ) ulStatsAsPercentage ); /*lint !e586 sprintf() allowed as this is compiled with many compilers and this is a utility function only - not part of the core kernel implementation. */ + xOutputBufferFull = pdTRUE; } - #endif } else { - /* If the percentage is zero here then the task has - * consumed less than 1% of the total run time. */ - #ifdef portLU_PRINTF_SPECIFIER_REQUIRED - { - sprintf( pcWriteBuffer, "\t%lu\t\t<1%%\r\n", pxTaskStatusArray[ x ].ulRunTimeCounter ); - } - #else - { - /* sizeof( int ) == sizeof( long ) so a smaller - * printf() library can be used. */ - sprintf( pcWriteBuffer, "\t%u\t\t<1%%\r\n", ( unsigned int ) pxTaskStatusArray[ x ].ulRunTimeCounter ); /*lint !e586 sprintf() allowed as this is compiled with many compilers and this is a utility function only - not part of the core kernel implementation. */ - } - #endif + xOutputBufferFull = pdTRUE; } - pcWriteBuffer += strlen( pcWriteBuffer ); /*lint !e9016 Pointer arithmetic ok on char pointers especially as in this case where it best denotes the intent of the code. */ + if( xOutputBufferFull == pdTRUE ) + { + break; + } } } else @@ -4718,6 +7593,8 @@ static void prvResetNextTaskUnblockTime( void ) { mtCOVERAGE_TEST_MARKER(); } + + traceRETURN_vTaskGetRunTimeStatistics(); } #endif /* ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( configUSE_STATS_FORMATTING_FUNCTIONS > 0 ) ) */ @@ -4727,11 +7604,15 @@ TickType_t uxTaskResetEventItemValue( void ) { TickType_t uxReturn; + traceENTER_uxTaskResetEventItemValue(); + uxReturn = listGET_LIST_ITEM_VALUE( &( pxCurrentTCB->xEventListItem ) ); /* Reset the event list item to its normal value - so it can be used with * queues and semaphores. */ - listSET_LIST_ITEM_VALUE( &( pxCurrentTCB->xEventListItem ), ( ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) pxCurrentTCB->uxPriority ) ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */ + listSET_LIST_ITEM_VALUE( &( pxCurrentTCB->xEventListItem ), ( ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) pxCurrentTCB->uxPriority ) ); + + traceRETURN_uxTaskResetEventItemValue( uxReturn ); return uxReturn; } @@ -4741,14 +7622,22 @@ TickType_t uxTaskResetEventItemValue( void ) TaskHandle_t pvTaskIncrementMutexHeldCount( void ) { + TCB_t * pxTCB; + + traceENTER_pvTaskIncrementMutexHeldCount(); + + pxTCB = pxCurrentTCB; + /* If xSemaphoreCreateMutex() is called before any tasks have been created * then pxCurrentTCB will be NULL. */ - if( pxCurrentTCB != NULL ) + if( pxTCB != NULL ) { - ( pxCurrentTCB->uxMutexesHeld )++; + ( pxTCB->uxMutexesHeld )++; } - return pxCurrentTCB; + traceRETURN_pvTaskIncrementMutexHeldCount( pxTCB ); + + return pxTCB; } #endif /* configUSE_MUTEXES */ @@ -4756,32 +7645,74 @@ TickType_t uxTaskResetEventItemValue( void ) #if ( configUSE_TASK_NOTIFICATIONS == 1 ) - uint32_t ulTaskGenericNotifyTake( UBaseType_t uxIndexToWait, + uint32_t ulTaskGenericNotifyTake( UBaseType_t uxIndexToWaitOn, BaseType_t xClearCountOnExit, TickType_t xTicksToWait ) { uint32_t ulReturn; + BaseType_t xAlreadyYielded; + + traceENTER_ulTaskGenericNotifyTake( uxIndexToWaitOn, xClearCountOnExit, xTicksToWait ); - configASSERT( uxIndexToWait < configTASK_NOTIFICATION_ARRAY_ENTRIES ); + configASSERT( uxIndexToWaitOn < configTASK_NOTIFICATION_ARRAY_ENTRIES ); taskENTER_CRITICAL(); + + /* Only block if the notification count is not already non-zero. */ + if( pxCurrentTCB->ulNotifiedValue[ uxIndexToWaitOn ] == 0UL ) { - /* Only block if the notification count is not already non-zero. */ - if( pxCurrentTCB->ulNotifiedValue[ uxIndexToWait ] == 0UL ) + /* Mark this task as waiting for a notification. */ + pxCurrentTCB->ucNotifyState[ uxIndexToWaitOn ] = taskWAITING_NOTIFICATION; + + if( xTicksToWait > ( TickType_t ) 0 ) { - /* Mark this task as waiting for a notification. */ - pxCurrentTCB->ucNotifyState[ uxIndexToWait ] = taskWAITING_NOTIFICATION; + traceTASK_NOTIFY_TAKE_BLOCK( uxIndexToWaitOn ); - if( xTicksToWait > ( TickType_t ) 0 ) + /* We MUST suspend the scheduler before exiting the critical + * section (i.e. before enabling interrupts). + * + * If we do not do so, a notification sent from an ISR, which + * happens after exiting the critical section and before + * suspending the scheduler, will get lost. The sequence of + * events will be: + * 1. Exit critical section. + * 2. Interrupt - ISR calls xTaskNotifyFromISR which adds the + * task to the Ready list. + * 3. Suspend scheduler. + * 4. prvAddCurrentTaskToDelayedList moves the task to the + * delayed or suspended list. + * 5. Resume scheduler does not touch the task (because it is + * not on the pendingReady list), effectively losing the + * notification from the ISR. + * + * The same does not happen when we suspend the scheduler before + * exiting the critical section. The sequence of events in this + * case will be: + * 1. Suspend scheduler. + * 2. Exit critical section. + * 3. Interrupt - ISR calls xTaskNotifyFromISR which adds the + * task to the pendingReady list as the scheduler is + * suspended. + * 4. prvAddCurrentTaskToDelayedList adds the task to delayed or + * suspended list. Note that this operation does not nullify + * the add to pendingReady list done in the above step because + * a different list item, namely xEventListItem, is used for + * adding the task to the pendingReady list. In other words, + * the task still remains on the pendingReady list. + * 5. Resume scheduler moves the task from pendingReady list to + * the Ready list. + */ + vTaskSuspendAll(); { + taskEXIT_CRITICAL(); + prvAddCurrentTaskToDelayedList( xTicksToWait, pdTRUE ); - traceTASK_NOTIFY_TAKE_BLOCK( uxIndexToWait ); + } + xAlreadyYielded = xTaskResumeAll(); - /* All ports are written to allow a yield in a critical - * section (some will yield immediately, others wait until the - * critical section exits) - but it is not something that - * application code should ever do. */ - portYIELD_WITHIN_API(); + if( xAlreadyYielded == pdFALSE ) + { + taskYIELD_WITHIN_API(); } else { @@ -4790,25 +7721,28 @@ TickType_t uxTaskResetEventItemValue( void ) } else { - mtCOVERAGE_TEST_MARKER(); + taskEXIT_CRITICAL(); } } - taskEXIT_CRITICAL(); + else + { + taskEXIT_CRITICAL(); + } taskENTER_CRITICAL(); { - traceTASK_NOTIFY_TAKE( uxIndexToWait ); - ulReturn = pxCurrentTCB->ulNotifiedValue[ uxIndexToWait ]; + traceTASK_NOTIFY_TAKE( uxIndexToWaitOn ); + ulReturn = pxCurrentTCB->ulNotifiedValue[ uxIndexToWaitOn ]; if( ulReturn != 0UL ) { if( xClearCountOnExit != pdFALSE ) { - pxCurrentTCB->ulNotifiedValue[ uxIndexToWait ] = 0UL; + pxCurrentTCB->ulNotifiedValue[ uxIndexToWaitOn ] = ( uint32_t ) 0UL; } else { - pxCurrentTCB->ulNotifiedValue[ uxIndexToWait ] = ulReturn - ( uint32_t ) 1; + pxCurrentTCB->ulNotifiedValue[ uxIndexToWaitOn ] = ulReturn - ( uint32_t ) 1; } } else @@ -4816,10 +7750,12 @@ TickType_t uxTaskResetEventItemValue( void ) mtCOVERAGE_TEST_MARKER(); } - pxCurrentTCB->ucNotifyState[ uxIndexToWait ] = taskNOT_WAITING_NOTIFICATION; + pxCurrentTCB->ucNotifyState[ uxIndexToWaitOn ] = taskNOT_WAITING_NOTIFICATION; } taskEXIT_CRITICAL(); + traceRETURN_ulTaskGenericNotifyTake( ulReturn ); + return ulReturn; } @@ -4828,39 +7764,80 @@ TickType_t uxTaskResetEventItemValue( void ) #if ( configUSE_TASK_NOTIFICATIONS == 1 ) - BaseType_t xTaskGenericNotifyWait( UBaseType_t uxIndexToWait, + BaseType_t xTaskGenericNotifyWait( UBaseType_t uxIndexToWaitOn, uint32_t ulBitsToClearOnEntry, uint32_t ulBitsToClearOnExit, uint32_t * pulNotificationValue, TickType_t xTicksToWait ) { - BaseType_t xReturn; + BaseType_t xReturn, xAlreadyYielded; - configASSERT( uxIndexToWait < configTASK_NOTIFICATION_ARRAY_ENTRIES ); + traceENTER_xTaskGenericNotifyWait( uxIndexToWaitOn, ulBitsToClearOnEntry, ulBitsToClearOnExit, pulNotificationValue, xTicksToWait ); + + configASSERT( uxIndexToWaitOn < configTASK_NOTIFICATION_ARRAY_ENTRIES ); taskENTER_CRITICAL(); + + /* Only block if a notification is not already pending. */ + if( pxCurrentTCB->ucNotifyState[ uxIndexToWaitOn ] != taskNOTIFICATION_RECEIVED ) { - /* Only block if a notification is not already pending. */ - if( pxCurrentTCB->ucNotifyState[ uxIndexToWait ] != taskNOTIFICATION_RECEIVED ) - { - /* Clear bits in the task's notification value as bits may get - * set by the notifying task or interrupt. This can be used to - * clear the value to zero. */ - pxCurrentTCB->ulNotifiedValue[ uxIndexToWait ] &= ~ulBitsToClearOnEntry; + /* Clear bits in the task's notification value as bits may get + * set by the notifying task or interrupt. This can be used to + * clear the value to zero. */ + pxCurrentTCB->ulNotifiedValue[ uxIndexToWaitOn ] &= ~ulBitsToClearOnEntry; + + /* Mark this task as waiting for a notification. */ + pxCurrentTCB->ucNotifyState[ uxIndexToWaitOn ] = taskWAITING_NOTIFICATION; - /* Mark this task as waiting for a notification. */ - pxCurrentTCB->ucNotifyState[ uxIndexToWait ] = taskWAITING_NOTIFICATION; + if( xTicksToWait > ( TickType_t ) 0 ) + { + traceTASK_NOTIFY_WAIT_BLOCK( uxIndexToWaitOn ); - if( xTicksToWait > ( TickType_t ) 0 ) + /* We MUST suspend the scheduler before exiting the critical + * section (i.e. before enabling interrupts). + * + * If we do not do so, a notification sent from an ISR, which + * happens after exiting the critical section and before + * suspending the scheduler, will get lost. The sequence of + * events will be: + * 1. Exit critical section. + * 2. Interrupt - ISR calls xTaskNotifyFromISR which adds the + * task to the Ready list. + * 3. Suspend scheduler. + * 4. prvAddCurrentTaskToDelayedList moves the task to the + * delayed or suspended list. + * 5. Resume scheduler does not touch the task (because it is + * not on the pendingReady list), effectively losing the + * notification from the ISR. + * + * The same does not happen when we suspend the scheduler before + * exiting the critical section. The sequence of events in this + * case will be: + * 1. Suspend scheduler. + * 2. Exit critical section. + * 3. Interrupt - ISR calls xTaskNotifyFromISR which adds the + * task to the pendingReady list as the scheduler is + * suspended. + * 4. prvAddCurrentTaskToDelayedList adds the task to delayed or + * suspended list. Note that this operation does not nullify + * the add to pendingReady list done in the above step because + * a different list item, namely xEventListItem, is used for + * adding the task to the pendingReady list. In other words, + * the task still remains on the pendingReady list. + * 5. Resume scheduler moves the task from pendingReady list to + * the Ready list. + */ + vTaskSuspendAll(); { + taskEXIT_CRITICAL(); + prvAddCurrentTaskToDelayedList( xTicksToWait, pdTRUE ); - traceTASK_NOTIFY_WAIT_BLOCK( uxIndexToWait ); + } + xAlreadyYielded = xTaskResumeAll(); - /* All ports are written to allow a yield in a critical - * section (some will yield immediately, others wait until the - * critical section exits) - but it is not something that - * application code should ever do. */ - portYIELD_WITHIN_API(); + if( xAlreadyYielded == pdFALSE ) + { + taskYIELD_WITHIN_API(); } else { @@ -4869,27 +7846,30 @@ TickType_t uxTaskResetEventItemValue( void ) } else { - mtCOVERAGE_TEST_MARKER(); + taskEXIT_CRITICAL(); } } - taskEXIT_CRITICAL(); + else + { + taskEXIT_CRITICAL(); + } taskENTER_CRITICAL(); { - traceTASK_NOTIFY_WAIT( uxIndexToWait ); + traceTASK_NOTIFY_WAIT( uxIndexToWaitOn ); if( pulNotificationValue != NULL ) { /* Output the current notification value, which may or may not * have changed. */ - *pulNotificationValue = pxCurrentTCB->ulNotifiedValue[ uxIndexToWait ]; + *pulNotificationValue = pxCurrentTCB->ulNotifiedValue[ uxIndexToWaitOn ]; } /* If ucNotifyValue is set then either the task never entered the * blocked state (because a notification was already pending) or the * task unblocked because of a notification. Otherwise the task * unblocked because of a timeout. */ - if( pxCurrentTCB->ucNotifyState[ uxIndexToWait ] != taskNOTIFICATION_RECEIVED ) + if( pxCurrentTCB->ucNotifyState[ uxIndexToWaitOn ] != taskNOTIFICATION_RECEIVED ) { /* A notification was not received. */ xReturn = pdFALSE; @@ -4898,14 +7878,16 @@ TickType_t uxTaskResetEventItemValue( void ) { /* A notification was already pending or a notification was * received while the task was waiting. */ - pxCurrentTCB->ulNotifiedValue[ uxIndexToWait ] &= ~ulBitsToClearOnExit; + pxCurrentTCB->ulNotifiedValue[ uxIndexToWaitOn ] &= ~ulBitsToClearOnExit; xReturn = pdTRUE; } - pxCurrentTCB->ucNotifyState[ uxIndexToWait ] = taskNOT_WAITING_NOTIFICATION; + pxCurrentTCB->ucNotifyState[ uxIndexToWaitOn ] = taskNOT_WAITING_NOTIFICATION; } taskEXIT_CRITICAL(); + traceRETURN_xTaskGenericNotifyWait( xReturn ); + return xReturn; } @@ -4924,6 +7906,8 @@ TickType_t uxTaskResetEventItemValue( void ) BaseType_t xReturn = pdPASS; uint8_t ucOriginalNotifyState; + traceENTER_xTaskGenericNotify( xTaskToNotify, uxIndexToNotify, ulValue, eAction, pulPreviousNotificationValue ); + configASSERT( uxIndexToNotify < configTASK_NOTIFICATION_ARRAY_ENTRIES ); configASSERT( xTaskToNotify ); pxTCB = xTaskToNotify; @@ -5011,16 +7995,9 @@ TickType_t uxTaskResetEventItemValue( void ) } #endif - if( pxTCB->uxPriority > pxCurrentTCB->uxPriority ) - { - /* The notified task has a priority above the currently - * executing task so a yield is required. */ - taskYIELD_IF_USING_PREEMPTION(); - } - else - { - mtCOVERAGE_TEST_MARKER(); - } + /* Check if the notified task has a priority above the currently + * executing task. */ + taskYIELD_ANY_CORE_IF_USING_PREEMPTION( pxTCB ); } else { @@ -5029,6 +8006,8 @@ TickType_t uxTaskResetEventItemValue( void ) } taskEXIT_CRITICAL(); + traceRETURN_xTaskGenericNotify( xReturn ); + return xReturn; } @@ -5049,6 +8028,8 @@ TickType_t uxTaskResetEventItemValue( void ) BaseType_t xReturn = pdPASS; UBaseType_t uxSavedInterruptStatus; + traceENTER_xTaskGenericNotifyFromISR( xTaskToNotify, uxIndexToNotify, ulValue, eAction, pulPreviousNotificationValue, pxHigherPriorityTaskWoken ); + configASSERT( xTaskToNotify ); configASSERT( uxIndexToNotify < configTASK_NOTIFICATION_ARRAY_ENTRIES ); @@ -5072,7 +8053,7 @@ TickType_t uxTaskResetEventItemValue( void ) pxTCB = xTaskToNotify; - uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR(); + uxSavedInterruptStatus = taskENTER_CRITICAL_FROM_ISR(); { if( pulPreviousNotificationValue != NULL ) { @@ -5146,27 +8127,49 @@ TickType_t uxTaskResetEventItemValue( void ) listINSERT_END( &( xPendingReadyList ), &( pxTCB->xEventListItem ) ); } - if( pxTCB->uxPriority > pxCurrentTCB->uxPriority ) + #if ( configNUMBER_OF_CORES == 1 ) { - /* The notified task has a priority above the currently - * executing task so a yield is required. */ - if( pxHigherPriorityTaskWoken != NULL ) + if( pxTCB->uxPriority > pxCurrentTCB->uxPriority ) { - *pxHigherPriorityTaskWoken = pdTRUE; - } + /* The notified task has a priority above the currently + * executing task so a yield is required. */ + if( pxHigherPriorityTaskWoken != NULL ) + { + *pxHigherPriorityTaskWoken = pdTRUE; + } - /* Mark that a yield is pending in case the user is not - * using the "xHigherPriorityTaskWoken" parameter to an ISR - * safe FreeRTOS function. */ - xYieldPending = pdTRUE; + /* Mark that a yield is pending in case the user is not + * using the "xHigherPriorityTaskWoken" parameter to an ISR + * safe FreeRTOS function. */ + xYieldPendings[ 0 ] = pdTRUE; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } } - else + #else /* #if ( configNUMBER_OF_CORES == 1 ) */ { - mtCOVERAGE_TEST_MARKER(); + #if ( configUSE_PREEMPTION == 1 ) + { + prvYieldForTask( pxTCB ); + + if( xYieldPendings[ portGET_CORE_ID() ] == pdTRUE ) + { + if( pxHigherPriorityTaskWoken != NULL ) + { + *pxHigherPriorityTaskWoken = pdTRUE; + } + } + } + #endif /* if ( configUSE_PREEMPTION == 1 ) */ } + #endif /* #if ( configNUMBER_OF_CORES == 1 ) */ } } - portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus ); + taskEXIT_CRITICAL_FROM_ISR( uxSavedInterruptStatus ); + + traceRETURN_xTaskGenericNotifyFromISR( xReturn ); return xReturn; } @@ -5184,6 +8187,8 @@ TickType_t uxTaskResetEventItemValue( void ) uint8_t ucOriginalNotifyState; UBaseType_t uxSavedInterruptStatus; + traceENTER_vTaskGenericNotifyGiveFromISR( xTaskToNotify, uxIndexToNotify, pxHigherPriorityTaskWoken ); + configASSERT( xTaskToNotify ); configASSERT( uxIndexToNotify < configTASK_NOTIFICATION_ARRAY_ENTRIES ); @@ -5207,7 +8212,7 @@ TickType_t uxTaskResetEventItemValue( void ) pxTCB = xTaskToNotify; - uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR(); + uxSavedInterruptStatus = taskENTER_CRITICAL_FROM_ISR(); { ucOriginalNotifyState = pxTCB->ucNotifyState[ uxIndexToNotify ]; pxTCB->ucNotifyState[ uxIndexToNotify ] = taskNOTIFICATION_RECEIVED; @@ -5237,27 +8242,49 @@ TickType_t uxTaskResetEventItemValue( void ) listINSERT_END( &( xPendingReadyList ), &( pxTCB->xEventListItem ) ); } - if( pxTCB->uxPriority > pxCurrentTCB->uxPriority ) + #if ( configNUMBER_OF_CORES == 1 ) { - /* The notified task has a priority above the currently - * executing task so a yield is required. */ - if( pxHigherPriorityTaskWoken != NULL ) + if( pxTCB->uxPriority > pxCurrentTCB->uxPriority ) { - *pxHigherPriorityTaskWoken = pdTRUE; - } + /* The notified task has a priority above the currently + * executing task so a yield is required. */ + if( pxHigherPriorityTaskWoken != NULL ) + { + *pxHigherPriorityTaskWoken = pdTRUE; + } - /* Mark that a yield is pending in case the user is not - * using the "xHigherPriorityTaskWoken" parameter in an ISR - * safe FreeRTOS function. */ - xYieldPending = pdTRUE; + /* Mark that a yield is pending in case the user is not + * using the "xHigherPriorityTaskWoken" parameter in an ISR + * safe FreeRTOS function. */ + xYieldPendings[ 0 ] = pdTRUE; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } } - else + #else /* #if ( configNUMBER_OF_CORES == 1 ) */ { - mtCOVERAGE_TEST_MARKER(); + #if ( configUSE_PREEMPTION == 1 ) + { + prvYieldForTask( pxTCB ); + + if( xYieldPendings[ portGET_CORE_ID() ] == pdTRUE ) + { + if( pxHigherPriorityTaskWoken != NULL ) + { + *pxHigherPriorityTaskWoken = pdTRUE; + } + } + } + #endif /* #if ( configUSE_PREEMPTION == 1 ) */ } + #endif /* #if ( configNUMBER_OF_CORES == 1 ) */ } } - portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus ); + taskEXIT_CRITICAL_FROM_ISR( uxSavedInterruptStatus ); + + traceRETURN_vTaskGenericNotifyGiveFromISR(); } #endif /* configUSE_TASK_NOTIFICATIONS */ @@ -5271,6 +8298,8 @@ TickType_t uxTaskResetEventItemValue( void ) TCB_t * pxTCB; BaseType_t xReturn; + traceENTER_xTaskGenericNotifyStateClear( xTask, uxIndexToClear ); + configASSERT( uxIndexToClear < configTASK_NOTIFICATION_ARRAY_ENTRIES ); /* If null is passed in here then it is the calling task that is having @@ -5291,6 +8320,8 @@ TickType_t uxTaskResetEventItemValue( void ) } taskEXIT_CRITICAL(); + traceRETURN_xTaskGenericNotifyStateClear( xReturn ); + return xReturn; } @@ -5306,6 +8337,8 @@ TickType_t uxTaskResetEventItemValue( void ) TCB_t * pxTCB; uint32_t ulReturn; + traceENTER_ulTaskGenericNotifyValueClear( xTask, uxIndexToClear, ulBitsToClear ); + configASSERT( uxIndexToClear < configTASK_NOTIFICATION_ARRAY_ENTRIES ); /* If null is passed in here then it is the calling task that is having @@ -5321,6 +8354,8 @@ TickType_t uxTaskResetEventItemValue( void ) } taskEXIT_CRITICAL(); + traceRETURN_ulTaskGenericNotifyValueClear( ulReturn ); + return ulReturn; } @@ -5331,18 +8366,29 @@ TickType_t uxTaskResetEventItemValue( void ) configRUN_TIME_COUNTER_TYPE ulTaskGetRunTimeCounter( const TaskHandle_t xTask ) { - return xTask->ulRunTimeCounter; + TCB_t * pxTCB; + + traceENTER_ulTaskGetRunTimeCounter( xTask ); + + pxTCB = prvGetTCBFromHandle( xTask ); + + traceRETURN_ulTaskGetRunTimeCounter( pxTCB->ulRunTimeCounter ); + + return pxTCB->ulRunTimeCounter; } -#endif +#endif /* if ( configGENERATE_RUN_TIME_STATS == 1 ) */ /*-----------------------------------------------------------*/ #if ( configGENERATE_RUN_TIME_STATS == 1 ) configRUN_TIME_COUNTER_TYPE ulTaskGetRunTimePercent( const TaskHandle_t xTask ) { + TCB_t * pxTCB; configRUN_TIME_COUNTER_TYPE ulTotalTime, ulReturn; + traceENTER_ulTaskGetRunTimePercent( xTask ); + ulTotalTime = ( configRUN_TIME_COUNTER_TYPE ) portGET_RUN_TIME_COUNTER_VALUE(); /* For percentage calculations. */ @@ -5351,37 +8397,80 @@ TickType_t uxTaskResetEventItemValue( void ) /* Avoid divide by zero errors. */ if( ulTotalTime > ( configRUN_TIME_COUNTER_TYPE ) 0 ) { - ulReturn = xTask->ulRunTimeCounter / ulTotalTime; + pxTCB = prvGetTCBFromHandle( xTask ); + ulReturn = pxTCB->ulRunTimeCounter / ulTotalTime; } else { ulReturn = 0; } + traceRETURN_ulTaskGetRunTimePercent( ulReturn ); + return ulReturn; } #endif /* if ( configGENERATE_RUN_TIME_STATS == 1 ) */ /*-----------------------------------------------------------*/ -#if ( configGENERATE_RUN_TIME_STATS == 1 ) +#if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) ) configRUN_TIME_COUNTER_TYPE ulTaskGetIdleRunTimeCounter( void ) { - return ulTaskGetRunTimeCounter( xIdleTaskHandle ); + configRUN_TIME_COUNTER_TYPE ulReturn = 0; + BaseType_t i; + + traceENTER_ulTaskGetIdleRunTimeCounter(); + + for( i = 0; i < ( BaseType_t ) configNUMBER_OF_CORES; i++ ) + { + ulReturn += xIdleTaskHandles[ i ]->ulRunTimeCounter; + } + + traceRETURN_ulTaskGetIdleRunTimeCounter( ulReturn ); + + return ulReturn; } -#endif +#endif /* if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) ) */ /*-----------------------------------------------------------*/ -#if ( configGENERATE_RUN_TIME_STATS == 1 ) +#if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) ) configRUN_TIME_COUNTER_TYPE ulTaskGetIdleRunTimePercent( void ) { - return ulTaskGetRunTimePercent( xIdleTaskHandle ); + configRUN_TIME_COUNTER_TYPE ulTotalTime, ulReturn; + configRUN_TIME_COUNTER_TYPE ulRunTimeCounter = 0; + BaseType_t i; + + traceENTER_ulTaskGetIdleRunTimePercent(); + + ulTotalTime = portGET_RUN_TIME_COUNTER_VALUE() * configNUMBER_OF_CORES; + + /* For percentage calculations. */ + ulTotalTime /= ( configRUN_TIME_COUNTER_TYPE ) 100; + + /* Avoid divide by zero errors. */ + if( ulTotalTime > ( configRUN_TIME_COUNTER_TYPE ) 0 ) + { + for( i = 0; i < ( BaseType_t ) configNUMBER_OF_CORES; i++ ) + { + ulRunTimeCounter += xIdleTaskHandles[ i ]->ulRunTimeCounter; + } + + ulReturn = ulRunTimeCounter / ulTotalTime; + } + else + { + ulReturn = 0; + } + + traceRETURN_ulTaskGetIdleRunTimePercent( ulReturn ); + + return ulReturn; } -#endif +#endif /* if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) ) */ /*-----------------------------------------------------------*/ static void prvAddCurrentTaskToDelayedList( TickType_t xTicksToWait, @@ -5389,6 +8478,8 @@ static void prvAddCurrentTaskToDelayedList( TickType_t xTicksToWait, { TickType_t xTimeToWake; const TickType_t xConstTickCount = xTickCount; + List_t * const pxDelayedList = pxDelayedTaskList; + List_t * const pxOverflowDelayedList = pxOverflowDelayedTaskList; #if ( INCLUDE_xTaskAbortDelay == 1 ) { @@ -5405,7 +8496,7 @@ static void prvAddCurrentTaskToDelayedList( TickType_t xTicksToWait, { /* The current task must be in a ready list, so there is no need to * check, and the port reset macro can be called directly. */ - portRESET_READY_PRIORITY( pxCurrentTCB->uxPriority, uxTopReadyPriority ); /*lint !e931 pxCurrentTCB cannot change as it is the calling task. pxCurrentTCB->uxPriority and uxTopReadyPriority cannot change as called with scheduler suspended or in a critical section. */ + portRESET_READY_PRIORITY( pxCurrentTCB->uxPriority, uxTopReadyPriority ); } else { @@ -5435,13 +8526,15 @@ static void prvAddCurrentTaskToDelayedList( TickType_t xTicksToWait, { /* Wake time has overflowed. Place this item in the overflow * list. */ - vListInsert( pxOverflowDelayedTaskList, &( pxCurrentTCB->xStateListItem ) ); + traceMOVED_TASK_TO_OVERFLOW_DELAYED_LIST(); + vListInsert( pxOverflowDelayedList, &( pxCurrentTCB->xStateListItem ) ); } else { /* The wake time has not overflowed, so the current block list * is used. */ - vListInsert( pxDelayedTaskList, &( pxCurrentTCB->xStateListItem ) ); + traceMOVED_TASK_TO_DELAYED_LIST(); + vListInsert( pxDelayedList, &( pxCurrentTCB->xStateListItem ) ); /* If the task entering the blocked state was placed at the * head of the list of blocked tasks then xNextTaskUnblockTime @@ -5469,13 +8562,15 @@ static void prvAddCurrentTaskToDelayedList( TickType_t xTicksToWait, if( xTimeToWake < xConstTickCount ) { + traceMOVED_TASK_TO_OVERFLOW_DELAYED_LIST(); /* Wake time has overflowed. Place this item in the overflow list. */ - vListInsert( pxOverflowDelayedTaskList, &( pxCurrentTCB->xStateListItem ) ); + vListInsert( pxOverflowDelayedList, &( pxCurrentTCB->xStateListItem ) ); } else { + traceMOVED_TASK_TO_DELAYED_LIST(); /* The wake time has not overflowed, so the current block list is used. */ - vListInsert( pxDelayedTaskList, &( pxCurrentTCB->xStateListItem ) ); + vListInsert( pxDelayedList, &( pxCurrentTCB->xStateListItem ) ); /* If the task entering the blocked state was placed at the head of the * list of blocked tasks then xNextTaskUnblockTime needs to be updated @@ -5503,8 +8598,12 @@ static void prvAddCurrentTaskToDelayedList( TickType_t xTicksToWait, { TCB_t * pxTCB; + traceENTER_xTaskGetMPUSettings( xTask ); + pxTCB = prvGetTCBFromHandle( xTask ); + traceRETURN_xTaskGetMPUSettings( &( pxTCB->xMPUSettings ) ); + return &( pxTCB->xMPUSettings ); } @@ -5532,3 +8631,69 @@ static void prvAddCurrentTaskToDelayedList( TickType_t xTicksToWait, #endif #endif /* if ( configINCLUDE_FREERTOS_TASK_C_ADDITIONS_H == 1 ) */ +/*-----------------------------------------------------------*/ + +#if ( ( configSUPPORT_STATIC_ALLOCATION == 1 ) && ( configKERNEL_PROVIDED_STATIC_MEMORY == 1 ) && ( portUSING_MPU_WRAPPERS == 0 ) ) + +/* + * This is the kernel provided implementation of vApplicationGetIdleTaskMemory() + * to provide the memory that is used by the Idle task. It is used when + * configKERNEL_PROVIDED_STATIC_MEMORY is set to 1. The application can provide + * it's own implementation of vApplicationGetIdleTaskMemory by setting + * configKERNEL_PROVIDED_STATIC_MEMORY to 0 or leaving it undefined. + */ + void vApplicationGetIdleTaskMemory( StaticTask_t ** ppxIdleTaskTCBBuffer, + StackType_t ** ppxIdleTaskStackBuffer, + uint32_t * pulIdleTaskStackSize ) + { + static StaticTask_t xIdleTaskTCB; + static StackType_t uxIdleTaskStack[ configMINIMAL_STACK_SIZE ]; + + *ppxIdleTaskTCBBuffer = &( xIdleTaskTCB ); + *ppxIdleTaskStackBuffer = &( uxIdleTaskStack[ 0 ] ); + *pulIdleTaskStackSize = configMINIMAL_STACK_SIZE; + } + + #if ( configNUMBER_OF_CORES > 1 ) + + void vApplicationGetPassiveIdleTaskMemory( StaticTask_t ** ppxIdleTaskTCBBuffer, + StackType_t ** ppxIdleTaskStackBuffer, + uint32_t * pulIdleTaskStackSize, + BaseType_t xPassiveIdleTaskIndex ) + { + static StaticTask_t xIdleTaskTCBs[ configNUMBER_OF_CORES - 1 ]; + static StackType_t uxIdleTaskStacks[ configNUMBER_OF_CORES - 1 ][ configMINIMAL_STACK_SIZE ]; + + *ppxIdleTaskTCBBuffer = &( xIdleTaskTCBs[ xPassiveIdleTaskIndex ] ); + *ppxIdleTaskStackBuffer = &( uxIdleTaskStacks[ xPassiveIdleTaskIndex ][ 0 ] ); + *pulIdleTaskStackSize = configMINIMAL_STACK_SIZE; + } + + #endif /* #if ( configNUMBER_OF_CORES > 1 ) */ + +#endif /* #if ( ( configSUPPORT_STATIC_ALLOCATION == 1 ) && ( configKERNEL_PROVIDED_STATIC_MEMORY == 1 ) && ( portUSING_MPU_WRAPPERS == 0 ) ) */ +/*-----------------------------------------------------------*/ + +#if ( ( configSUPPORT_STATIC_ALLOCATION == 1 ) && ( configKERNEL_PROVIDED_STATIC_MEMORY == 1 ) && ( portUSING_MPU_WRAPPERS == 0 ) ) + +/* + * This is the kernel provided implementation of vApplicationGetTimerTaskMemory() + * to provide the memory that is used by the Timer service task. It is used when + * configKERNEL_PROVIDED_STATIC_MEMORY is set to 1. The application can provide + * it's own implementation of vApplicationGetTimerTaskMemory by setting + * configKERNEL_PROVIDED_STATIC_MEMORY to 0 or leaving it undefined. + */ + void vApplicationGetTimerTaskMemory( StaticTask_t ** ppxTimerTaskTCBBuffer, + StackType_t ** ppxTimerTaskStackBuffer, + uint32_t * pulTimerTaskStackSize ) + { + static StaticTask_t xTimerTaskTCB; + static StackType_t uxTimerTaskStack[ configTIMER_TASK_STACK_DEPTH ]; + + *ppxTimerTaskTCBBuffer = &( xTimerTaskTCB ); + *ppxTimerTaskStackBuffer = &( uxTimerTaskStack[ 0 ] ); + *pulTimerTaskStackSize = configTIMER_TASK_STACK_DEPTH; + } + +#endif /* #if ( ( configSUPPORT_STATIC_ALLOCATION == 1 ) && ( configKERNEL_PROVIDED_STATIC_MEMORY == 1 ) && ( portUSING_MPU_WRAPPERS == 0 ) ) */ +/*-----------------------------------------------------------*/ diff --git a/Source/timers.c b/Source/timers.c index d5012adcb..045af5e9d 100644 --- a/Source/timers.c +++ b/Source/timers.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V10.6.2 + * FreeRTOS Kernel V11.0.1 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -43,11 +43,10 @@ #error configUSE_TIMERS must be set to 1 to make the xTimerPendFunctionCall() function available. #endif -/* Lint e9021, e961 and e750 are suppressed as a MISRA exception justified - * because the MPU ports require MPU_WRAPPERS_INCLUDED_FROM_API_FILE to be defined +/* The MPU ports require MPU_WRAPPERS_INCLUDED_FROM_API_FILE to be defined * for the header files above, but not in this file, in order to generate the * correct privileged Vs unprivileged linkage and placement. */ -#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE /*lint !e9021 !e961 !e750. */ +#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE /* This entire source file will be skipped if the application is not configured @@ -60,29 +59,38 @@ #define tmrNO_DELAY ( ( TickType_t ) 0U ) #define tmrMAX_TIME_BEFORE_OVERFLOW ( ( TickType_t ) -1 ) -/* The name assigned to the timer service task. This can be overridden by - * defining trmTIMER_SERVICE_TASK_NAME in FreeRTOSConfig.h. */ +/* The name assigned to the timer service task. This can be overridden by + * defining configTIMER_SERVICE_TASK_NAME in FreeRTOSConfig.h. */ #ifndef configTIMER_SERVICE_TASK_NAME #define configTIMER_SERVICE_TASK_NAME "Tmr Svc" #endif + #if ( ( configNUMBER_OF_CORES > 1 ) && ( configUSE_CORE_AFFINITY == 1 ) ) + +/* The core affinity assigned to the timer service task on SMP systems. + * This can be overridden by defining configTIMER_SERVICE_TASK_CORE_AFFINITY in FreeRTOSConfig.h. */ + #ifndef configTIMER_SERVICE_TASK_CORE_AFFINITY + #define configTIMER_SERVICE_TASK_CORE_AFFINITY tskNO_AFFINITY + #endif + #endif /* #if ( ( configNUMBER_OF_CORES > 1 ) && ( configUSE_CORE_AFFINITY == 1 ) ) */ + /* Bit definitions used in the ucStatus member of a timer structure. */ - #define tmrSTATUS_IS_ACTIVE ( ( uint8_t ) 0x01 ) - #define tmrSTATUS_IS_STATICALLY_ALLOCATED ( ( uint8_t ) 0x02 ) - #define tmrSTATUS_IS_AUTORELOAD ( ( uint8_t ) 0x04 ) + #define tmrSTATUS_IS_ACTIVE ( 0x01U ) + #define tmrSTATUS_IS_STATICALLY_ALLOCATED ( 0x02U ) + #define tmrSTATUS_IS_AUTORELOAD ( 0x04U ) /* The definition of the timers themselves. */ - typedef struct tmrTimerControl /* The old naming convention is used to prevent breaking kernel aware debuggers. */ + typedef struct tmrTimerControl /* The old naming convention is used to prevent breaking kernel aware debuggers. */ { - const char * pcTimerName; /**< Text name. This is not used by the kernel, it is included simply to make debugging easier. */ /*lint !e971 Unqualified char types are allowed for strings and single characters only. */ - ListItem_t xTimerListItem; /**< Standard linked list item as used by all kernel features for event management. */ - TickType_t xTimerPeriodInTicks; /**< How quickly and often the timer expires. */ - void * pvTimerID; /**< An ID to identify the timer. This allows the timer to be identified when the same callback is used for multiple timers. */ - TimerCallbackFunction_t pxCallbackFunction; /**< The function that will be called when the timer expires. */ + const char * pcTimerName; /**< Text name. This is not used by the kernel, it is included simply to make debugging easier. */ + ListItem_t xTimerListItem; /**< Standard linked list item as used by all kernel features for event management. */ + TickType_t xTimerPeriodInTicks; /**< How quickly and often the timer expires. */ + void * pvTimerID; /**< An ID to identify the timer. This allows the timer to be identified when the same callback is used for multiple timers. */ + portTIMER_CALLBACK_ATTRIBUTE TimerCallbackFunction_t pxCallbackFunction; /**< The function that will be called when the timer expires. */ #if ( configUSE_TRACE_FACILITY == 1 ) - UBaseType_t uxTimerNumber; /**< An ID assigned by trace tools such as FreeRTOS+Trace */ + UBaseType_t uxTimerNumber; /**< An ID assigned by trace tools such as FreeRTOS+Trace */ #endif - uint8_t ucStatus; /**< Holds bits to say if the timer was statically allocated or not, and if it is active or not. */ + uint8_t ucStatus; /**< Holds bits to say if the timer was statically allocated or not, and if it is active or not. */ } xTIMER; /* The old xTIMER name is maintained above then typedefed to the new Timer_t @@ -103,6 +111,7 @@ typedef struct tmrCallbackParameters { + portTIMER_CALLBACK_ATTRIBUTE PendedFunction_t pxCallbackFunction; /* << The callback function to execute. */ void * pvParameter1; /* << The value that will be used as the callback functions first parameter. */ uint32_t ulParameter2; /* << The value that will be used as the callback functions second parameter. */ @@ -125,9 +134,6 @@ } u; } DaemonTaskMessage_t; -/*lint -save -e956 A manual analysis and inspection has been used to determine - * which static variables must be declared volatile. */ - /* The list in which active timers are stored. Timers are referenced in expire * time order, with the nearest expiry time at the front of the list. Only the * timer service task is allowed to access these lists. @@ -143,8 +149,6 @@ PRIVILEGED_DATA static QueueHandle_t xTimerQueue = NULL; PRIVILEGED_DATA static TaskHandle_t xTimerTaskHandle = NULL; -/*lint -restore */ - /*-----------------------------------------------------------*/ /* @@ -222,7 +226,7 @@ * Called after a Timer_t structure has been allocated either statically or * dynamically to fill in the structure's members. */ - static void prvInitialiseNewTimer( const char * const pcTimerName, /*lint !e971 Unqualified char types are allowed for strings and single characters only. */ + static void prvInitialiseNewTimer( const char * const pcTimerName, const TickType_t xTimerPeriodInTicks, const BaseType_t xAutoReload, void * const pvTimerID, @@ -234,6 +238,8 @@ { BaseType_t xReturn = pdFAIL; + traceENTER_xTimerCreateTimerTask(); + /* This function is called when the scheduler is started if * configUSE_TIMERS is set to 1. Check that the infrastructure used by the * timer service task has been created/initialised. If timers have already @@ -242,36 +248,75 @@ if( xTimerQueue != NULL ) { - #if ( configSUPPORT_STATIC_ALLOCATION == 1 ) + #if ( ( configNUMBER_OF_CORES > 1 ) && ( configUSE_CORE_AFFINITY == 1 ) ) { - StaticTask_t * pxTimerTaskTCBBuffer = NULL; - StackType_t * pxTimerTaskStackBuffer = NULL; - uint32_t ulTimerTaskStackSize; - - vApplicationGetTimerTaskMemory( &pxTimerTaskTCBBuffer, &pxTimerTaskStackBuffer, &ulTimerTaskStackSize ); - xTimerTaskHandle = xTaskCreateStatic( prvTimerTask, + #if ( configSUPPORT_STATIC_ALLOCATION == 1 ) + { + StaticTask_t * pxTimerTaskTCBBuffer = NULL; + StackType_t * pxTimerTaskStackBuffer = NULL; + uint32_t ulTimerTaskStackSize; + + vApplicationGetTimerTaskMemory( &pxTimerTaskTCBBuffer, &pxTimerTaskStackBuffer, &ulTimerTaskStackSize ); + xTimerTaskHandle = xTaskCreateStaticAffinitySet( prvTimerTask, + configTIMER_SERVICE_TASK_NAME, + ulTimerTaskStackSize, + NULL, + ( ( UBaseType_t ) configTIMER_TASK_PRIORITY ) | portPRIVILEGE_BIT, + pxTimerTaskStackBuffer, + pxTimerTaskTCBBuffer, + configTIMER_SERVICE_TASK_CORE_AFFINITY ); + + if( xTimerTaskHandle != NULL ) + { + xReturn = pdPASS; + } + } + #else /* if ( configSUPPORT_STATIC_ALLOCATION == 1 ) */ + { + xReturn = xTaskCreateAffinitySet( prvTimerTask, configTIMER_SERVICE_TASK_NAME, - ulTimerTaskStackSize, + configTIMER_TASK_STACK_DEPTH, NULL, ( ( UBaseType_t ) configTIMER_TASK_PRIORITY ) | portPRIVILEGE_BIT, - pxTimerTaskStackBuffer, - pxTimerTaskTCBBuffer ); - - if( xTimerTaskHandle != NULL ) - { - xReturn = pdPASS; + configTIMER_SERVICE_TASK_CORE_AFFINITY, + &xTimerTaskHandle ); } + #endif /* configSUPPORT_STATIC_ALLOCATION */ } - #else /* if ( configSUPPORT_STATIC_ALLOCATION == 1 ) */ + #else /* #if ( ( configNUMBER_OF_CORES > 1 ) && ( configUSE_CORE_AFFINITY == 1 ) ) */ { - xReturn = xTaskCreate( prvTimerTask, - configTIMER_SERVICE_TASK_NAME, - configTIMER_TASK_STACK_DEPTH, - NULL, - ( ( UBaseType_t ) configTIMER_TASK_PRIORITY ) | portPRIVILEGE_BIT, - &xTimerTaskHandle ); + #if ( configSUPPORT_STATIC_ALLOCATION == 1 ) + { + StaticTask_t * pxTimerTaskTCBBuffer = NULL; + StackType_t * pxTimerTaskStackBuffer = NULL; + uint32_t ulTimerTaskStackSize; + + vApplicationGetTimerTaskMemory( &pxTimerTaskTCBBuffer, &pxTimerTaskStackBuffer, &ulTimerTaskStackSize ); + xTimerTaskHandle = xTaskCreateStatic( prvTimerTask, + configTIMER_SERVICE_TASK_NAME, + ulTimerTaskStackSize, + NULL, + ( ( UBaseType_t ) configTIMER_TASK_PRIORITY ) | portPRIVILEGE_BIT, + pxTimerTaskStackBuffer, + pxTimerTaskTCBBuffer ); + + if( xTimerTaskHandle != NULL ) + { + xReturn = pdPASS; + } + } + #else /* if ( configSUPPORT_STATIC_ALLOCATION == 1 ) */ + { + xReturn = xTaskCreate( prvTimerTask, + configTIMER_SERVICE_TASK_NAME, + configTIMER_TASK_STACK_DEPTH, + NULL, + ( ( UBaseType_t ) configTIMER_TASK_PRIORITY ) | portPRIVILEGE_BIT, + &xTimerTaskHandle ); + } + #endif /* configSUPPORT_STATIC_ALLOCATION */ } - #endif /* configSUPPORT_STATIC_ALLOCATION */ + #endif /* #if ( ( configNUMBER_OF_CORES > 1 ) && ( configUSE_CORE_AFFINITY == 1 ) ) */ } else { @@ -279,13 +324,16 @@ } configASSERT( xReturn ); + + traceRETURN_xTimerCreateTimerTask( xReturn ); + return xReturn; } /*-----------------------------------------------------------*/ #if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) - TimerHandle_t xTimerCreate( const char * const pcTimerName, /*lint !e971 Unqualified char types are allowed for strings and single characters only. */ + TimerHandle_t xTimerCreate( const char * const pcTimerName, const TickType_t xTimerPeriodInTicks, const BaseType_t xAutoReload, void * const pvTimerID, @@ -293,7 +341,12 @@ { Timer_t * pxNewTimer; - pxNewTimer = ( Timer_t * ) pvPortMalloc( sizeof( Timer_t ) ); /*lint !e9087 !e9079 All values returned by pvPortMalloc() have at least the alignment required by the MCU's stack, and the first member of Timer_t is always a pointer to the timer's mame. */ + traceENTER_xTimerCreate( pcTimerName, xTimerPeriodInTicks, xAutoReload, pvTimerID, pxCallbackFunction ); + + /* MISRA Ref 11.5.1 [Malloc memory assignment] */ + /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-115 */ + /* coverity[misra_c_2012_rule_11_5_violation] */ + pxNewTimer = ( Timer_t * ) pvPortMalloc( sizeof( Timer_t ) ); if( pxNewTimer != NULL ) { @@ -304,6 +357,8 @@ prvInitialiseNewTimer( pcTimerName, xTimerPeriodInTicks, xAutoReload, pvTimerID, pxCallbackFunction, pxNewTimer ); } + traceRETURN_xTimerCreate( pxNewTimer ); + return pxNewTimer; } @@ -312,7 +367,7 @@ #if ( configSUPPORT_STATIC_ALLOCATION == 1 ) - TimerHandle_t xTimerCreateStatic( const char * const pcTimerName, /*lint !e971 Unqualified char types are allowed for strings and single characters only. */ + TimerHandle_t xTimerCreateStatic( const char * const pcTimerName, const TickType_t xTimerPeriodInTicks, const BaseType_t xAutoReload, void * const pvTimerID, @@ -321,6 +376,8 @@ { Timer_t * pxNewTimer; + traceENTER_xTimerCreateStatic( pcTimerName, xTimerPeriodInTicks, xAutoReload, pvTimerID, pxCallbackFunction, pxTimerBuffer ); + #if ( configASSERT_DEFINED == 1 ) { /* Sanity check that the size of the structure used to declare a @@ -328,31 +385,36 @@ * structure. */ volatile size_t xSize = sizeof( StaticTimer_t ); configASSERT( xSize == sizeof( Timer_t ) ); - ( void ) xSize; /* Keeps lint quiet when configASSERT() is not defined. */ + ( void ) xSize; /* Prevent unused variable warning when configASSERT() is not defined. */ } #endif /* configASSERT_DEFINED */ /* A pointer to a StaticTimer_t structure MUST be provided, use it. */ configASSERT( pxTimerBuffer ); - pxNewTimer = ( Timer_t * ) pxTimerBuffer; /*lint !e740 !e9087 StaticTimer_t is a pointer to a Timer_t, so guaranteed to be aligned and sized correctly (checked by an assert()), so this is safe. */ + /* MISRA Ref 11.3.1 [Misaligned access] */ + /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-113 */ + /* coverity[misra_c_2012_rule_11_3_violation] */ + pxNewTimer = ( Timer_t * ) pxTimerBuffer; if( pxNewTimer != NULL ) { /* Timers can be created statically or dynamically so note this * timer was created statically in case it is later deleted. The * auto-reload bit may get set in prvInitialiseNewTimer(). */ - pxNewTimer->ucStatus = tmrSTATUS_IS_STATICALLY_ALLOCATED; + pxNewTimer->ucStatus = ( uint8_t ) tmrSTATUS_IS_STATICALLY_ALLOCATED; prvInitialiseNewTimer( pcTimerName, xTimerPeriodInTicks, xAutoReload, pvTimerID, pxCallbackFunction, pxNewTimer ); } + traceRETURN_xTimerCreateStatic( pxNewTimer ); + return pxNewTimer; } #endif /* configSUPPORT_STATIC_ALLOCATION */ /*-----------------------------------------------------------*/ - static void prvInitialiseNewTimer( const char * const pcTimerName, /*lint !e971 Unqualified char types are allowed for strings and single characters only. */ + static void prvInitialiseNewTimer( const char * const pcTimerName, const TickType_t xTimerPeriodInTicks, const BaseType_t xAutoReload, void * const pvTimerID, @@ -376,22 +438,26 @@ if( xAutoReload != pdFALSE ) { - pxNewTimer->ucStatus |= tmrSTATUS_IS_AUTORELOAD; + pxNewTimer->ucStatus |= ( uint8_t ) tmrSTATUS_IS_AUTORELOAD; } traceTIMER_CREATE( pxNewTimer ); } /*-----------------------------------------------------------*/ - BaseType_t xTimerGenericCommand( TimerHandle_t xTimer, - const BaseType_t xCommandID, - const TickType_t xOptionalValue, - BaseType_t * const pxHigherPriorityTaskWoken, - const TickType_t xTicksToWait ) + BaseType_t xTimerGenericCommandFromTask( TimerHandle_t xTimer, + const BaseType_t xCommandID, + const TickType_t xOptionalValue, + BaseType_t * const pxHigherPriorityTaskWoken, + const TickType_t xTicksToWait ) { BaseType_t xReturn = pdFAIL; DaemonTaskMessage_t xMessage; + ( void ) pxHigherPriorityTaskWoken; + + traceENTER_xTimerGenericCommandFromTask( xTimer, xCommandID, xOptionalValue, pxHigherPriorityTaskWoken, xTicksToWait ); + configASSERT( xTimer ); /* Send a message to the timer service task to perform a particular action @@ -403,6 +469,8 @@ xMessage.u.xTimerParameters.xMessageValue = xOptionalValue; xMessage.u.xTimerParameters.pxTimer = xTimer; + configASSERT( xCommandID < tmrFIRST_FROM_ISR_COMMAND ); + if( xCommandID < tmrFIRST_FROM_ISR_COMMAND ) { if( xTaskGetSchedulerState() == taskSCHEDULER_RUNNING ) @@ -414,7 +482,47 @@ xReturn = xQueueSendToBack( xTimerQueue, &xMessage, tmrNO_DELAY ); } } - else + + traceTIMER_COMMAND_SEND( xTimer, xCommandID, xOptionalValue, xReturn ); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + traceRETURN_xTimerGenericCommandFromTask( xReturn ); + + return xReturn; + } +/*-----------------------------------------------------------*/ + + BaseType_t xTimerGenericCommandFromISR( TimerHandle_t xTimer, + const BaseType_t xCommandID, + const TickType_t xOptionalValue, + BaseType_t * const pxHigherPriorityTaskWoken, + const TickType_t xTicksToWait ) + { + BaseType_t xReturn = pdFAIL; + DaemonTaskMessage_t xMessage; + + ( void ) xTicksToWait; + + traceENTER_xTimerGenericCommandFromISR( xTimer, xCommandID, xOptionalValue, pxHigherPriorityTaskWoken, xTicksToWait ); + + configASSERT( xTimer ); + + /* Send a message to the timer service task to perform a particular action + * on a particular timer definition. */ + if( xTimerQueue != NULL ) + { + /* Send a command to the timer service task to start the xTimer timer. */ + xMessage.xMessageID = xCommandID; + xMessage.u.xTimerParameters.xMessageValue = xOptionalValue; + xMessage.u.xTimerParameters.pxTimer = xTimer; + + configASSERT( xCommandID >= tmrFIRST_FROM_ISR_COMMAND ); + + if( xCommandID >= tmrFIRST_FROM_ISR_COMMAND ) { xReturn = xQueueSendToBackFromISR( xTimerQueue, &xMessage, pxHigherPriorityTaskWoken ); } @@ -426,15 +534,22 @@ mtCOVERAGE_TEST_MARKER(); } + traceRETURN_xTimerGenericCommandFromISR( xReturn ); + return xReturn; } /*-----------------------------------------------------------*/ TaskHandle_t xTimerGetTimerDaemonTaskHandle( void ) { + traceENTER_xTimerGetTimerDaemonTaskHandle(); + /* If xTimerGetTimerDaemonTaskHandle() is called before the scheduler has been * started, then xTimerTaskHandle will be NULL. */ configASSERT( ( xTimerTaskHandle != NULL ) ); + + traceRETURN_xTimerGetTimerDaemonTaskHandle( xTimerTaskHandle ); + return xTimerTaskHandle; } /*-----------------------------------------------------------*/ @@ -443,7 +558,12 @@ { Timer_t * pxTimer = xTimer; + traceENTER_xTimerGetPeriod( xTimer ); + configASSERT( xTimer ); + + traceRETURN_xTimerGetPeriod( pxTimer->xTimerPeriodInTicks ); + return pxTimer->xTimerPeriodInTicks; } /*-----------------------------------------------------------*/ @@ -453,12 +573,14 @@ { Timer_t * pxTimer = xTimer; + traceENTER_vTimerSetReloadMode( xTimer, xAutoReload ); + configASSERT( xTimer ); taskENTER_CRITICAL(); { if( xAutoReload != pdFALSE ) { - pxTimer->ucStatus |= tmrSTATUS_IS_AUTORELOAD; + pxTimer->ucStatus |= ( uint8_t ) tmrSTATUS_IS_AUTORELOAD; } else { @@ -466,6 +588,8 @@ } } taskEXIT_CRITICAL(); + + traceRETURN_vTimerSetReloadMode(); } /*-----------------------------------------------------------*/ @@ -474,10 +598,12 @@ Timer_t * pxTimer = xTimer; BaseType_t xReturn; + traceENTER_xTimerGetReloadMode( xTimer ); + configASSERT( xTimer ); taskENTER_CRITICAL(); { - if( ( pxTimer->ucStatus & tmrSTATUS_IS_AUTORELOAD ) == 0 ) + if( ( pxTimer->ucStatus & tmrSTATUS_IS_AUTORELOAD ) == 0U ) { /* Not an auto-reload timer. */ xReturn = pdFALSE; @@ -490,12 +616,22 @@ } taskEXIT_CRITICAL(); + traceRETURN_xTimerGetReloadMode( xReturn ); + return xReturn; } UBaseType_t uxTimerGetReloadMode( TimerHandle_t xTimer ) { - return ( UBaseType_t ) xTimerGetReloadMode( xTimer ); + UBaseType_t uxReturn; + + traceENTER_uxTimerGetReloadMode( xTimer ); + + uxReturn = ( UBaseType_t ) xTimerGetReloadMode( xTimer ); + + traceRETURN_uxTimerGetReloadMode( uxReturn ); + + return uxReturn; } /*-----------------------------------------------------------*/ @@ -504,8 +640,13 @@ Timer_t * pxTimer = xTimer; TickType_t xReturn; + traceENTER_xTimerGetExpiryTime( xTimer ); + configASSERT( xTimer ); xReturn = listGET_LIST_ITEM_VALUE( &( pxTimer->xTimerListItem ) ); + + traceRETURN_xTimerGetExpiryTime( xReturn ); + return xReturn; } /*-----------------------------------------------------------*/ @@ -517,10 +658,15 @@ BaseType_t xReturn; Timer_t * pxTimer = xTimer; + traceENTER_xTimerGetStaticBuffer( xTimer, ppxTimerBuffer ); + configASSERT( ppxTimerBuffer != NULL ); - if( ( pxTimer->ucStatus & tmrSTATUS_IS_STATICALLY_ALLOCATED ) != 0 ) + if( ( pxTimer->ucStatus & tmrSTATUS_IS_STATICALLY_ALLOCATED ) != 0U ) { + /* MISRA Ref 11.3.1 [Misaligned access] */ + /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-113 */ + /* coverity[misra_c_2012_rule_11_3_violation] */ *ppxTimerBuffer = ( StaticTimer_t * ) pxTimer; xReturn = pdTRUE; } @@ -529,16 +675,23 @@ xReturn = pdFALSE; } + traceRETURN_xTimerGetStaticBuffer( xReturn ); + return xReturn; } #endif /* configSUPPORT_STATIC_ALLOCATION */ /*-----------------------------------------------------------*/ - const char * pcTimerGetName( TimerHandle_t xTimer ) /*lint !e971 Unqualified char types are allowed for strings and single characters only. */ + const char * pcTimerGetName( TimerHandle_t xTimer ) { Timer_t * pxTimer = xTimer; + traceENTER_pcTimerGetName( xTimer ); + configASSERT( xTimer ); + + traceRETURN_pcTimerGetName( pxTimer->pcTimerName ); + return pxTimer->pcTimerName; } /*-----------------------------------------------------------*/ @@ -565,7 +718,10 @@ static void prvProcessExpiredTimer( const TickType_t xNextExpireTime, const TickType_t xTimeNow ) { - Timer_t * const pxTimer = ( Timer_t * ) listGET_OWNER_OF_HEAD_ENTRY( pxCurrentTimerList ); /*lint !e9087 !e9079 void * is used as this macro is used with tasks and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */ + /* MISRA Ref 11.5.3 [Void pointer assignment] */ + /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-115 */ + /* coverity[misra_c_2012_rule_11_5_violation] */ + Timer_t * const pxTimer = ( Timer_t * ) listGET_OWNER_OF_HEAD_ENTRY( pxCurrentTimerList ); /* Remove the timer from the list of active timers. A check has already * been performed to ensure the list is not empty. */ @@ -574,7 +730,7 @@ /* If the timer is an auto-reload timer then calculate the next * expiry time and re-insert the timer in the list of active timers. */ - if( ( pxTimer->ucStatus & tmrSTATUS_IS_AUTORELOAD ) != 0 ) + if( ( pxTimer->ucStatus & tmrSTATUS_IS_AUTORELOAD ) != 0U ) { prvReloadTimer( pxTimer, xNextExpireTime, xTimeNow ); } @@ -607,7 +763,7 @@ } #endif /* configUSE_DAEMON_TASK_STARTUP_HOOK */ - for( ; ; ) + for( ; configCONTROL_INFINITE_LOOP(); ) { /* Query the timers list to see if it contains any timers, and if so, * obtain the time at which the next timer will expire. */ @@ -669,7 +825,7 @@ * block time to expire. If a command arrived between the * critical section being exited and this yield then the yield * will not cause the task to block. */ - portYIELD_WITHIN_API(); + taskYIELD_WITHIN_API(); } else { @@ -715,7 +871,7 @@ static TickType_t prvSampleTimeNow( BaseType_t * const pxTimerListsWereSwitched ) { TickType_t xTimeNow; - PRIVILEGED_DATA static TickType_t xLastTime = ( TickType_t ) 0U; /*lint !e956 Variable is only accessible to one task. */ + PRIVILEGED_DATA static TickType_t xLastTime = ( TickType_t ) 0U; xTimeNow = xTaskGetTickCount(); @@ -749,7 +905,7 @@ { /* Has the expiry time elapsed between the command to start/reset a * timer was issued, and the time the command was processed? */ - if( ( ( TickType_t ) ( xTimeNow - xCommandTime ) ) >= pxTimer->xTimerPeriodInTicks ) /*lint !e961 MISRA exception as the casts are only redundant for some ports. */ + if( ( ( TickType_t ) ( xTimeNow - xCommandTime ) ) >= pxTimer->xTimerPeriodInTicks ) { /* The time between a command being issued and the command being * processed actually exceeds the timers period. */ @@ -781,12 +937,12 @@ static void prvProcessReceivedCommands( void ) { - DaemonTaskMessage_t xMessage; + DaemonTaskMessage_t xMessage = { 0 }; Timer_t * pxTimer; BaseType_t xTimerListsWereSwitched; TickType_t xTimeNow; - while( xQueueReceive( xTimerQueue, &xMessage, tmrNO_DELAY ) != pdFAIL ) /*lint !e603 xMessage does not have to be initialised as it is passed out, not in, and it is not used unless xQueueReceive() returns pdTRUE. */ + while( xQueueReceive( xTimerQueue, &xMessage, tmrNO_DELAY ) != pdFAIL ) { #if ( INCLUDE_xTimerPendFunctionCall == 1 ) { @@ -818,7 +974,7 @@ * software timer. */ pxTimer = xMessage.u.xTimerParameters.pxTimer; - if( listIS_CONTAINED_WITHIN( NULL, &( pxTimer->xTimerListItem ) ) == pdFALSE ) /*lint !e961. The cast is only redundant when NULL is passed into the macro. */ + if( listIS_CONTAINED_WITHIN( NULL, &( pxTimer->xTimerListItem ) ) == pdFALSE ) { /* The timer is in a list, remove it. */ ( void ) uxListRemove( &( pxTimer->xTimerListItem ) ); @@ -845,13 +1001,13 @@ case tmrCOMMAND_RESET: case tmrCOMMAND_RESET_FROM_ISR: /* Start or restart a timer. */ - pxTimer->ucStatus |= tmrSTATUS_IS_ACTIVE; + pxTimer->ucStatus |= ( uint8_t ) tmrSTATUS_IS_ACTIVE; if( prvInsertTimerInActiveList( pxTimer, xMessage.u.xTimerParameters.xMessageValue + pxTimer->xTimerPeriodInTicks, xTimeNow, xMessage.u.xTimerParameters.xMessageValue ) != pdFALSE ) { /* The timer expired before it was added to the active * timer list. Process it now. */ - if( ( pxTimer->ucStatus & tmrSTATUS_IS_AUTORELOAD ) != 0 ) + if( ( pxTimer->ucStatus & tmrSTATUS_IS_AUTORELOAD ) != 0U ) { prvReloadTimer( pxTimer, xMessage.u.xTimerParameters.xMessageValue + pxTimer->xTimerPeriodInTicks, xTimeNow ); } @@ -879,7 +1035,7 @@ case tmrCOMMAND_CHANGE_PERIOD: case tmrCOMMAND_CHANGE_PERIOD_FROM_ISR: - pxTimer->ucStatus |= tmrSTATUS_IS_ACTIVE; + pxTimer->ucStatus |= ( uint8_t ) tmrSTATUS_IS_ACTIVE; pxTimer->xTimerPeriodInTicks = xMessage.u.xTimerParameters.xMessageValue; configASSERT( ( pxTimer->xTimerPeriodInTicks > 0 ) ); @@ -970,14 +1126,14 @@ { /* The timer queue is allocated statically in case * configSUPPORT_DYNAMIC_ALLOCATION is 0. */ - PRIVILEGED_DATA static StaticQueue_t xStaticTimerQueue; /*lint !e956 Ok to declare in this manner to prevent additional conditional compilation guards in other locations. */ - PRIVILEGED_DATA static uint8_t ucStaticTimerQueueStorage[ ( size_t ) configTIMER_QUEUE_LENGTH * sizeof( DaemonTaskMessage_t ) ]; /*lint !e956 Ok to declare in this manner to prevent additional conditional compilation guards in other locations. */ + PRIVILEGED_DATA static StaticQueue_t xStaticTimerQueue; + PRIVILEGED_DATA static uint8_t ucStaticTimerQueueStorage[ ( size_t ) configTIMER_QUEUE_LENGTH * sizeof( DaemonTaskMessage_t ) ]; xTimerQueue = xQueueCreateStatic( ( UBaseType_t ) configTIMER_QUEUE_LENGTH, ( UBaseType_t ) sizeof( DaemonTaskMessage_t ), &( ucStaticTimerQueueStorage[ 0 ] ), &xStaticTimerQueue ); } #else { - xTimerQueue = xQueueCreate( ( UBaseType_t ) configTIMER_QUEUE_LENGTH, sizeof( DaemonTaskMessage_t ) ); + xTimerQueue = xQueueCreate( ( UBaseType_t ) configTIMER_QUEUE_LENGTH, ( UBaseType_t ) sizeof( DaemonTaskMessage_t ) ); } #endif /* if ( configSUPPORT_STATIC_ALLOCATION == 1 ) */ @@ -1008,12 +1164,14 @@ BaseType_t xReturn; Timer_t * pxTimer = xTimer; + traceENTER_xTimerIsTimerActive( xTimer ); + configASSERT( xTimer ); /* Is the timer in the list of active timers? */ taskENTER_CRITICAL(); { - if( ( pxTimer->ucStatus & tmrSTATUS_IS_ACTIVE ) == 0 ) + if( ( pxTimer->ucStatus & tmrSTATUS_IS_ACTIVE ) == 0U ) { xReturn = pdFALSE; } @@ -1024,8 +1182,10 @@ } taskEXIT_CRITICAL(); + traceRETURN_xTimerIsTimerActive( xReturn ); + return xReturn; - } /*lint !e818 Can't be pointer to const due to the typedef. */ + } /*-----------------------------------------------------------*/ void * pvTimerGetTimerID( const TimerHandle_t xTimer ) @@ -1033,6 +1193,8 @@ Timer_t * const pxTimer = xTimer; void * pvReturn; + traceENTER_pvTimerGetTimerID( xTimer ); + configASSERT( xTimer ); taskENTER_CRITICAL(); @@ -1041,6 +1203,8 @@ } taskEXIT_CRITICAL(); + traceRETURN_pvTimerGetTimerID( pvReturn ); + return pvReturn; } /*-----------------------------------------------------------*/ @@ -1050,6 +1214,8 @@ { Timer_t * const pxTimer = xTimer; + traceENTER_vTimerSetTimerID( xTimer, pvNewID ); + configASSERT( xTimer ); taskENTER_CRITICAL(); @@ -1057,6 +1223,8 @@ pxTimer->pvTimerID = pvNewID; } taskEXIT_CRITICAL(); + + traceRETURN_vTimerSetTimerID(); } /*-----------------------------------------------------------*/ @@ -1070,6 +1238,8 @@ DaemonTaskMessage_t xMessage; BaseType_t xReturn; + traceENTER_xTimerPendFunctionCallFromISR( xFunctionToPend, pvParameter1, ulParameter2, pxHigherPriorityTaskWoken ); + /* Complete the message with the function parameters and post it to the * daemon task. */ xMessage.xMessageID = tmrCOMMAND_EXECUTE_CALLBACK_FROM_ISR; @@ -1080,6 +1250,7 @@ xReturn = xQueueSendFromISR( xTimerQueue, &xMessage, pxHigherPriorityTaskWoken ); tracePEND_FUNC_CALL_FROM_ISR( xFunctionToPend, pvParameter1, ulParameter2, xReturn ); + traceRETURN_xTimerPendFunctionCallFromISR( xReturn ); return xReturn; } @@ -1097,6 +1268,8 @@ DaemonTaskMessage_t xMessage; BaseType_t xReturn; + traceENTER_xTimerPendFunctionCall( xFunctionToPend, pvParameter1, ulParameter2, xTicksToWait ); + /* This function can only be called after a timer has been created or * after the scheduler has been started because, until then, the timer * queue does not exist. */ @@ -1112,6 +1285,7 @@ xReturn = xQueueSendToBack( xTimerQueue, &xMessage, xTicksToWait ); tracePEND_FUNC_CALL( xFunctionToPend, pvParameter1, ulParameter2, xReturn ); + traceRETURN_xTimerPendFunctionCall( xReturn ); return xReturn; } @@ -1123,6 +1297,10 @@ UBaseType_t uxTimerGetTimerNumber( TimerHandle_t xTimer ) { + traceENTER_uxTimerGetTimerNumber( xTimer ); + + traceRETURN_uxTimerGetTimerNumber( ( ( Timer_t * ) xTimer )->uxTimerNumber ); + return ( ( Timer_t * ) xTimer )->uxTimerNumber; } @@ -1134,7 +1312,11 @@ void vTimerSetTimerNumber( TimerHandle_t xTimer, UBaseType_t uxTimerNumber ) { + traceENTER_vTimerSetTimerNumber( xTimer, uxTimerNumber ); + ( ( Timer_t * ) xTimer )->uxTimerNumber = uxTimerNumber; + + traceRETURN_vTimerSetTimerNumber(); } #endif /* configUSE_TRACE_FACILITY */