timing_constraints_part72.xdc

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create_clock -period 7.500 -name clk [get_ports clk]
set_multicycle_path 2 -setup -from [get_pins data_reg_ip_reg[*]/C] -to [get_pins data_reg_op_reg[*]/D]
set_multicycle_path 1 -hold -from [get_pins data_reg_ip_reg[*]/C] -to [get_pins data_reg_op_reg[*]/D]