-single-cycle-RISC-V-processor-Verilog-

You may contact me about any bugs or errors at the following email [email protected]

Happy testing :)

Name		Name	Last commit message	Last commit date
Latest commit History 2 Commits
ALU_Control.v		ALU_Control.v
Adder.v		Adder.v
Control_Unit.v		Control_Unit.v
Data_Memory.v		Data_Memory.v
IMD.v		IMD.v
IP.v		IP.v
Instruction_Memory.v		Instruction_Memory.v
MUX.v		MUX.v
PC.v		PC.v
README.md		README.md
alux64.v		alux64.v
regfile.v		regfile.v
run.do		run.do
tb.v		tb.v
top.v		top.v

Provide feedback