diff --git a/proxyclient/m1n1/adt.py b/proxyclient/m1n1/adt.py index 9bdcedcab..f098d7572 100644 --- a/proxyclient/m1n1/adt.py +++ b/proxyclient/m1n1/adt.py @@ -287,8 +287,8 @@ "config-data": SafeGreedyRange(Int32ul), } }, - "*pmu*": { - "*": { + "spmi-*": { + "pmu,*": { "info-*name*": CString("ascii"), "info-*": SafeGreedyRange(Hex(Int32ul)), }, diff --git a/proxyclient/m1n1/hv/__init__.py b/proxyclient/m1n1/hv/__init__.py index 6c87976d7..232ccf7b1 100644 --- a/proxyclient/m1n1/hv/__init__.py +++ b/proxyclient/m1n1/hv/__init__.py @@ -1566,6 +1566,8 @@ def cpustart_wh(base, off, data, width): cpu_start = 0x34000 + die * 0x20_0000_0000 elif chip_id in (0x6020, 0x6021, 0x6022): cpu_start = 0x28000 + die * 0x20_0000_0000 + elif chip_id in (0x6030,): + cpu_start = 0x34000 + die * 0x20_0000_0000 elif chip_id in (0x6031,): cpu_start = 0x88000 + die * 0x20_0000_0000 else: @@ -1703,7 +1705,7 @@ def load_raw(self, image, entryoffset=0x800, use_xnu_symbols=False, vmin=0): print(f"Physical memory: 0x{phys_base:x} .. 0x{mem_top:x}") print(f"Guest region start: 0x{guest_base:x}") - + self.entry = guest_base + entryoffset print(f"Mapping guest physical memory...") diff --git a/src/chickens.c b/src/chickens.c index da132b7fc..4e9525cc8 100644 --- a/src/chickens.c +++ b/src/chickens.c @@ -39,6 +39,8 @@ #define MIDR_PART_T6020_AVALANCHE 0x35 #define MIDR_PART_T6021_BLIZZARD 0x38 #define MIDR_PART_T6021_AVALANCHE 0x39 +#define MIDR_PART_T6030_SAWTOOTH 0x44 +#define MIDR_PART_T6030_EVEREST 0x45 #define MIDR_PART_T6031_EVEREST 0x49 #define MIDR_PART_T6031_SAWTOOTH 0x48 @@ -66,6 +68,8 @@ void init_t6020_blizzard(void); void init_t6020_avalanche(int rev); void init_t6021_blizzard(void); void init_t6021_avalanche(int rev); +void init_t6030_sawtooth(void); +void init_t6030_everest(int rev); void init_t6031_sawtooth(void); void init_t6031_everest(int rev); @@ -204,6 +208,16 @@ const char *init_cpu(void) init_t6021_blizzard(); break; + case MIDR_PART_T6030_EVEREST: + cpu = "M3 Pro Everest"; + init_t6030_everest(rev); + break; + + case MIDR_PART_T6030_SAWTOOTH: + cpu = "M3 Pro Sawtooth"; + init_t6030_sawtooth(); + break; + case MIDR_PART_T6031_EVEREST: cpu = "M3 Max Everest"; init_t6031_everest(rev); diff --git a/src/chickens_everest.c b/src/chickens_everest.c index cab8faea1..961bcac5b 100644 --- a/src/chickens_everest.c +++ b/src/chickens_everest.c @@ -36,11 +36,22 @@ static void init_common_everest(void) reg_clr(s3_0_c15_c2_4, BIT(0) | BIT(1) | BIT(16) | BIT(17) | BIT(18) | BIT(22)); } +void init_t6030_everest(int rev) +{ + UNUSED(rev); + msr(s3_1_c15_c1_5, 0x1uL); + if (in_el2()) + msr(s3_4_c15_c14_6, 0x3uL); + init_common_everest(); + reg_set(SYS_IMP_APL_HID4, HID4_ENABLE_LFSR_STALL_LOAD_PIPE2_ISSUE); +} + void init_t6031_everest(int rev) { UNUSED(rev); - msr(s3_1_c15_c1_5, 0x3uL); - msr(s3_4_c15_c14_6, 0x3uL); + msr(s3_1_c15_c1_5, 0x1uL); + if (in_el2()) + msr(s3_4_c15_c14_6, 0x3uL); init_common_everest(); reg_set(SYS_IMP_APL_HID4, HID4_ENABLE_LFSR_STALL_LOAD_PIPE2_ISSUE); } diff --git a/src/chickens_sawtooth.c b/src/chickens_sawtooth.c index 8e9fe317e..b50550f3f 100644 --- a/src/chickens_sawtooth.c +++ b/src/chickens_sawtooth.c @@ -8,6 +8,17 @@ static void init_common_sawtooth(void) reg_set(SYS_IMP_APL_EHID0, EHID0_BLI_UNK32); } +void init_t6030_sawtooth(void) +{ + init_common_sawtooth(); + + reg_mask(SYS_IMP_APL_EHID9, EHID9_DEV_2_THROTTLE_LIMIT_MASK, EHID9_DEV_2_THROTTLE_LIMIT(62)); + reg_set(SYS_IMP_APL_EHID9, EHID9_DEV_2_THROTTLE_ENABLE); + reg_set(SYS_IMP_APL_EHID18, EHID18_BLZ_UNK34); + + reg_mask(SYS_IMP_APL_HID5, HID5_BLZ_UNK_19_18_MASK, HID5_BLZ_UNK19); +} + void init_t6031_sawtooth(void) { init_common_sawtooth(); diff --git a/src/mcc.c b/src/mcc.c index 375388399..f3e7cad60 100644 --- a/src/mcc.c +++ b/src/mcc.c @@ -23,11 +23,11 @@ static bool mcc_initialized = false; #define T6000_DCS_STRIDE 0x100000 #define T6000_DCS_COUNT 4 -#define T6031_PLANE_OFFSET 0 -#define T6031_PLANE_STRIDE 0x40000 -#define T6031_GLOBAL_OFFSET 0x100000 -#define T6031_DCS_OFFSET 0x400000 -#define T6031_DCS_STRIDE 0x200000 +#define T603X_PLANE_OFFSET 0 +#define T603X_PLANE_STRIDE 0x40000 +#define T603X_GLOBAL_OFFSET 0x100000 +#define T603X_DCS_OFFSET 0x400000 +#define T603X_DCS_STRIDE 0x200000 #define PLANE_TZ_MAX_REGS 4 @@ -55,7 +55,15 @@ struct tz_regs t602x_tz_regs = { .enable = 0x6c8, }; -struct tz_regs t603x_tz_regs = { +struct tz_regs t6030_tz_regs = { + .count = 4, + .stride = 0x14, + .start = 0x6dc, + .end = 0x6e0, + .enable = 0x6e8, +}; + +struct tz_regs t6031_tz_regs = { .count = 4, .stride = 0x14, .start = 0x6d8, @@ -78,11 +86,11 @@ struct tz_regs t603x_tz_regs = { (FIELD_PREP(T6000_CACHE_STATUS_DATA_COUNT, T6000_CACHE_WAYS) | \ FIELD_PREP(T6000_CACHE_STATUS_TAG_COUNT, T6000_CACHE_WAYS)) -#define T6031_CACHE_WAYS 12 -#define T6031_CACHE_STATUS_MASK (T6000_CACHE_STATUS_DATA_COUNT | T6000_CACHE_STATUS_TAG_COUNT) -#define T6031_CACHE_STATUS_VAL \ - (FIELD_PREP(T6000_CACHE_STATUS_DATA_COUNT, T6031_CACHE_WAYS) | \ - FIELD_PREP(T6000_CACHE_STATUS_TAG_COUNT, T6031_CACHE_WAYS)) +#define T603X_CACHE_WAYS 12 +#define T603X_CACHE_STATUS_MASK (T6000_CACHE_STATUS_DATA_COUNT | T6000_CACHE_STATUS_TAG_COUNT) +#define T603X_CACHE_STATUS_VAL \ + (FIELD_PREP(T6000_CACHE_STATUS_DATA_COUNT, T603X_CACHE_WAYS) | \ + FIELD_PREP(T6000_CACHE_STATUS_TAG_COUNT, T603X_CACHE_WAYS)) #define T8103_CACHE_WAYS 16 #define T8103_CACHE_STATUS_MASK (T8103_CACHE_STATUS_DATA_COUNT | T8103_CACHE_STATUS_TAG_COUNT) @@ -318,7 +326,7 @@ int mcc_init_t6000(int node, int *path, bool t602x) return 0; } -int mcc_init_t6031(int node, int *path) +int mcc_init_t603x(int node, int *path, int lsn) { u32 reg_len; u32 reg_offset = 3; @@ -330,7 +338,7 @@ int mcc_init_t6031(int node, int *path) mcc_count = reg_len / 16 - reg_offset; - printf("MCC: Initializing T6031 MCCs (%d instances)...\n", mcc_count); + printf("MCC: Initializing T603%x MCCs (%d instances)...\n", lsn, mcc_count); if (mcc_count > MAX_MCC_INSTANCES) { printf("MCC: Too many instances, increase MAX_MCC_INSTANCES!\n"); @@ -357,26 +365,33 @@ int mcc_init_t6031(int node, int *path) return -1; } - mcc_regs[i].plane_base = base + T6031_PLANE_OFFSET; - mcc_regs[i].plane_stride = T6031_PLANE_STRIDE; + mcc_regs[i].plane_base = base + T603X_PLANE_OFFSET; + mcc_regs[i].plane_stride = T603X_PLANE_STRIDE; mcc_regs[i].plane_count = plane_count; - mcc_regs[i].global_base = base + T6031_GLOBAL_OFFSET; + mcc_regs[i].global_base = base + T603X_GLOBAL_OFFSET; - mcc_regs[i].dcs_base = base + T6031_DCS_OFFSET; - mcc_regs[i].dcs_stride = T6031_DCS_STRIDE; + mcc_regs[i].dcs_base = base + T603X_DCS_OFFSET; + mcc_regs[i].dcs_stride = T603X_DCS_STRIDE; mcc_regs[i].dcs_count = dcs_count; mcc_regs[i].cache_enable_val = 1; - mcc_regs[i].cache_ways = T6031_CACHE_WAYS; - mcc_regs[i].cache_status_mask = T6031_CACHE_STATUS_MASK; - mcc_regs[i].cache_status_val = T6031_CACHE_STATUS_VAL; + mcc_regs[i].cache_ways = T603X_CACHE_WAYS; + mcc_regs[i].cache_status_mask = T603X_CACHE_STATUS_MASK; + mcc_regs[i].cache_status_val = T603X_CACHE_STATUS_VAL; mcc_regs[i].cache_disable = 0; - mcc_regs[i].tz = &t603x_tz_regs; + if(lsn == 0){ + mcc_regs[i].tz = &t6030_tz_regs; + } else if(lsn == 1){ + mcc_regs[i].tz = &t6031_tz_regs; + } else { + printf("MCC: Unsupported chip (T603%x)", lsn); + return -1; + } } - printf("MCC: Initialized T6031 MCCs (%d instances, %d planes, %d channels)\n", mcc_count, + printf("MCC: Initialized T603%x MCCs (%d instances, %d planes, %d channels)\n", lsn, mcc_count, mcc_regs[0].plane_count, mcc_regs[0].dcs_count); mcc_initialized = true; @@ -402,8 +417,10 @@ int mcc_init(void) return mcc_init_t6000(node, path, false); } else if (adt_is_compatible(adt, node, "mcc,t6020")) { return mcc_init_t6000(node, path, true); + } else if (adt_is_compatible(adt, node, "mcc,t6030")) { + return mcc_init_t603x(node, path, 0); } else if (adt_is_compatible(adt, node, "mcc,t6031")) { - return mcc_init_t6031(node, path); + return mcc_init_t603x(node, path, 1); } else { printf("MCC: Unsupported version:%s\n", adt_get_property(adt, node, "compatible")->value); return -1; diff --git a/src/smp.c b/src/smp.c index 15ccc0e40..8059159d0 100644 --- a/src/smp.c +++ b/src/smp.c @@ -18,6 +18,7 @@ #define CPU_START_OFF_T8103 0x54000 #define CPU_START_OFF_T8112 0x34000 #define CPU_START_OFF_T6020 0x28000 +#define CPU_START_OFF_T6030 0x34000 #define CPU_START_OFF_T6031 0x88000 #define CPU_REG_CORE GENMASK(7, 0) @@ -279,6 +280,9 @@ void smp_start_secondaries(void) case T6022: cpu_start_off = CPU_START_OFF_T6020; break; + case T6030: + cpu_start_off = CPU_START_OFF_T6030; + break; case T6031: case T6034: cpu_start_off = CPU_START_OFF_T6031; diff --git a/src/soc.h b/src/soc.h index b6632ad2d..2999f5ea5 100644 --- a/src/soc.h +++ b/src/soc.h @@ -25,6 +25,7 @@ #define T6020 0x6020 #define T6021 0x6021 #define T6022 0x6022 +#define T6030 0x6030 #define T6031 0x6031 #define T6034 0x6034 @@ -37,6 +38,8 @@ #define EARLY_UART_BASE 0x39b200000 #elif TARGET == T8112 #define EARLY_UART_BASE 0x235200000 +#elif TARGET == T6030 +#define EARLY_UART_BASE 0x289200000 #elif TARGET == T6034 || TARGET == T6031 #define EARLY_UART_BASE 0x391200000 #elif TARGET == T8015