From 6745735c20aefe972e64d38904793475422df7d3 Mon Sep 17 00:00:00 2001 From: GitHub Actions Date: Tue, 2 Jul 2024 07:05:49 +0000 Subject: [PATCH] Tue Jul 2 07:05:03 UTC 2024 Kernel update --- bsp/drivers/clk/sunxi-ng/ccu-sun55iw3.c | 128 +- bsp/drivers/clk/sunxi-ng/ccu_mult.h | 3 + bsp/drivers/clk/sunxi-ng/ccu_nm.c | 6 +- bsp/drivers/drm/Kconfig | 100 +- bsp/drivers/drm/Makefile | 64 +- bsp/drivers/drm/lib/inc/sha1.h | 55 + bsp/drivers/drm/lib/inc/sha256.h | 40 + bsp/drivers/drm/lib/src/sha1.c | 360 + bsp/drivers/drm/lib/src/sha256.c | 235 + bsp/drivers/drm/panel/Kconfig | 35 +- bsp/drivers/drm/panel/Makefile | 11 +- bsp/drivers/drm/panel/dsi-panel-simple.c | 658 + bsp/drivers/drm/panel/panel-lvds.c | 351 + bsp/drivers/drm/panel/panel-rgb.c | 362 + bsp/drivers/drm/panel/panels.c | 1 + bsp/drivers/drm/panel/panels.h | 6 +- bsp/drivers/drm/phy/Kconfig | 15 + bsp/drivers/drm/phy/Makefile | 7 + bsp/drivers/drm/phy/sunxi_dsi_combophy.c | 523 + bsp/drivers/drm/phy/sunxi_dsi_combophy_reg.c | 400 + bsp/drivers/drm/phy/sunxi_dsi_combophy_reg.h | 765 + .../drm/sunxi_device/hardware/include.h | 1174 +- .../hardware/lowlevel_de/Makefile | 49 + .../hardware/lowlevel_de/afbd/de_fbd_atw.c | 711 + .../hardware/lowlevel_de/afbd/de_fbd_atw.h | 37 + .../lowlevel_de/afbd/de_fbd_atw_type.h | 437 + .../hardware/lowlevel_de/bld/de_bld.c | 315 + .../hardware/lowlevel_de/bld/de_bld.h | 35 + .../lowlevel_de/bld/de_bld_platform.c | 345 + .../lowlevel_de/bld/de_bld_platform.h | 40 + .../hardware/lowlevel_de/bld/de_bld_type.h | 232 + .../hardware/lowlevel_de/cdc/de_cdc.c | 845 + .../hardware/lowlevel_de/cdc/de_cdc.h | 42 + .../lowlevel_de/cdc/de_cdc_platform.c | 64 + .../lowlevel_de/cdc/de_cdc_platform.h | 33 + .../hardware/lowlevel_de/cdc/de_cdc_table.c | 54443 ++++++++++++++++ .../hardware/lowlevel_de/cdc/de_cdc_table.h | 46 + .../hardware/lowlevel_de/cdc/de_cdc_type.h | 192 + .../hardware/lowlevel_de/crc/de_crc.c | 320 + .../hardware/lowlevel_de/crc/de_crc.h | 51 + .../lowlevel_de/crc/de_crc_platform.c | 64 + .../lowlevel_de/crc/de_crc_platform.h | 25 + .../hardware/lowlevel_de/crc/de_crc_type.h | 210 + .../hardware/lowlevel_de/csc/de_csc.c | 1456 + .../hardware/lowlevel_de/csc/de_csc.h | 78 + .../lowlevel_de/csc/de_csc_platform.c | 323 + .../lowlevel_de/csc/de_csc_platform.h | 41 + .../hardware/lowlevel_de/csc/de_csc_table.c | 1585 + .../hardware/lowlevel_de/csc/de_csc_table.h | 47 + .../hardware/lowlevel_de/csc/de_csc_type.h | 162 + .../hardware/lowlevel_de/csc/de_dcsc.h | 31 + .../hardware/lowlevel_de/csc/de_dcsc_type.h | 25 + .../hardware/lowlevel_de/dci/de_dci.c | 799 + .../hardware/lowlevel_de/dci/de_dci.h | 48 + .../lowlevel_de/dci/de_dci_platform.c | 58 + .../lowlevel_de/dci/de_dci_platform.h | 33 + .../hardware/lowlevel_de/dci/de_dci_type.h | 518 + .../hardware/lowlevel_de/de_backend.c | 199 + .../hardware/lowlevel_de/de_backend.h | 46 + .../hardware/lowlevel_de/de_base.h | 197 + .../hardware/lowlevel_de/de_channel.c | 1039 + .../hardware/lowlevel_de/de_channel.h | 149 + .../hardware/lowlevel_de/de_frontend.c | 689 + .../hardware/lowlevel_de/de_frontend.h | 86 + .../hardware/lowlevel_de/de_top.c | 851 + .../hardware/lowlevel_de/de_top.h | 81 + .../hardware/lowlevel_de/dither/de_dither.c | 132 + .../hardware/lowlevel_de/dither/de_dither.h | 58 + .../lowlevel_de/dither/de_dither_platform.c | 110 + .../lowlevel_de/dither/de_dither_platform.h | 30 + .../lowlevel_de/dither/de_dither_type.h | 68 + .../hardware/lowlevel_de/fcm/de_fcm.c | 626 + .../hardware/lowlevel_de/fcm/de_fcm.h | 49 + .../lowlevel_de/fcm/de_fcm_platform.c | 64 + .../lowlevel_de/fcm/de_fcm_platform.h | 33 + .../hardware/lowlevel_de/fcm/de_fcm_type.h | 593 + .../hardware/lowlevel_de/gamma/de_gamma.c | 278 + .../hardware/lowlevel_de/gamma/de_gamma.h | 58 + .../lowlevel_de/gamma/de_gamma_platform.c | 77 + .../lowlevel_de/gamma/de_gamma_platform.h | 28 + .../lowlevel_de/gamma/de_gamma_type.h | 177 + .../hardware/lowlevel_de/ovl/de_ovl.c | 815 + .../hardware/lowlevel_de/ovl/de_ovl.h | 52 + .../lowlevel_de/ovl/de_ovl_platform.c | 320 + .../lowlevel_de/ovl/de_ovl_platform.h | 32 + .../hardware/lowlevel_de/ovl/de_ovl_type.h | 266 + .../hardware/lowlevel_de/scaler/de_scaler.c | 1681 + .../hardware/lowlevel_de/scaler/de_scaler.h | 109 + .../lowlevel_de/scaler/de_scaler_platform.c | 297 + .../lowlevel_de/scaler/de_scaler_platform.h | 47 + .../lowlevel_de/scaler/de_scaler_table.c | 986 + .../lowlevel_de/scaler/de_scaler_table.h | 46 + .../lowlevel_de/scaler/de_scaler_type.h | 1039 + .../hardware/lowlevel_de/sharp/de_sharp.c | 403 + .../hardware/lowlevel_de/sharp/de_sharp.h | 40 + .../lowlevel_de/sharp/de_sharp_platform.c | 58 + .../lowlevel_de/sharp/de_sharp_platform.h | 33 + .../lowlevel_de/sharp/de_sharp_type.h | 234 + .../hardware/lowlevel_de/smbl/de_smbl.c | 547 + .../hardware/lowlevel_de/smbl/de_smbl.h | 61 + .../lowlevel_de/smbl/de_smbl_platform.c | 55 + .../lowlevel_de/smbl/de_smbl_platform.h | 26 + .../hardware/lowlevel_de/smbl/de_smbl_tab.h | 32471 +++++++++ .../hardware/lowlevel_de/smbl/de_smbl_type.h | 266 + .../hardware/lowlevel_de/snr/de_snr.c | 373 + .../hardware/lowlevel_de/snr/de_snr.h | 72 + .../lowlevel_de/snr/de_snr_platform.c | 64 + .../lowlevel_de/snr/de_snr_platform.h | 33 + .../hardware/lowlevel_de/snr/de_snr_type.h | 92 + .../hardware/lowlevel_de/sunxi_de.c | 1278 + .../hardware/lowlevel_de/sunxi_de.h | 89 + .../hardware/lowlevel_de/tfbd/de_tfbd.c | 420 + .../hardware/lowlevel_de/tfbd/de_tfbd.h | 36 + .../hardware/lowlevel_de/tfbd/de_tfbd_type.h | 153 + .../lowlevel_de/tfbd/img_drm_fourcc.h | 145 + .../hardware/lowlevel_de/wb/de_wb.c | 532 + .../hardware/lowlevel_de/wb/de_wb.h | 39 + .../hardware/lowlevel_de/wb/de_wb_type.h | 295 + .../lowlevel_edp/inno_edp13/inno_edp13.c | 1087 +- .../lowlevel_edp/inno_edp13/inno_edp13.h | 9 + .../trilinear_dp14/trilinear_dp14.c | 1651 + .../trilinear_dp14/trilinear_dp14.h | 241 + .../hardware/lowlevel_hdmi20/Makefile | 10 +- .../hardware/lowlevel_hdmi20/dw_avp.c | 1660 +- .../hardware/lowlevel_hdmi20/dw_avp.h | 214 +- .../hardware/lowlevel_hdmi20/dw_cec.c | 1 - .../hardware/lowlevel_hdmi20/dw_dev.c | 127 +- .../hardware/lowlevel_hdmi20/dw_dev.h | 425 +- .../hardware/lowlevel_hdmi20/dw_edid.c | 360 +- .../hardware/lowlevel_hdmi20/dw_edid.h | 50 +- .../hardware/lowlevel_hdmi20/dw_fc.c | 799 +- .../hardware/lowlevel_hdmi20/dw_fc.h | 60 +- .../hardware/lowlevel_hdmi20/dw_hdcp.c | 582 +- .../hardware/lowlevel_hdmi20/dw_hdcp.h | 210 +- .../hardware/lowlevel_hdmi20/dw_hdcp22.c | 497 +- .../hardware/lowlevel_hdmi20/dw_hdcp22.h | 174 +- .../hardware/lowlevel_hdmi20/dw_i2cm.c | 141 +- .../hardware/lowlevel_hdmi20/dw_i2cm.h | 21 +- .../hardware/lowlevel_hdmi20/dw_mc.c | 60 +- .../hardware/lowlevel_hdmi20/dw_mc.h | 49 +- .../hardware/lowlevel_hdmi20/dw_phy.c | 32 +- .../hardware/lowlevel_hdmi20/dw_phy.h | 7 - .../esm_lib/esm_host_lib_auth.c | 3 - .../esm_lib/esm_host_lib_exceptions.c | 1 - .../esm_lib/esm_host_lib_init.c | 3 - .../esm_lib/esm_host_lib_log.c | 1 - .../esm_lib/esm_host_lib_status.c | 1 - .../hardware/lowlevel_hdmi20/phy_aw.c | 6 +- .../hardware/lowlevel_hdmi20/phy_inno.c | 87 +- .../hardware/lowlevel_hdmi20/phy_snps.c | 1529 +- .../hardware/lowlevel_hdmi20/phy_snps.h | 46 +- .../hardware/lowlevel_lcd/dsi_v1.c | 944 + .../hardware/lowlevel_lcd/dsi_v1.h | 288 + .../hardware/lowlevel_lcd/dsi_v1_type.h | 559 + .../hardware/lowlevel_lcd/tcon_lcd.c | 874 + .../hardware/lowlevel_lcd/tcon_lcd.h | 151 + .../hardware/lowlevel_lcd/tcon_lcd_type.h | 615 + .../hardware/lowlevel_tcon/Makefile | 10 + .../hardware/lowlevel_tcon/tcon_top.c | 266 + .../hardware/lowlevel_tcon/tcon_top.h | 37 + .../hardware/lowlevel_tcon/tcon_top_type.h | 184 + .../hardware/lowlevel_tcon/tcon_tv.h | 44 + .../hardware/lowlevel_tcon/tcon_tv_reg.c | 563 + .../hardware/lowlevel_tcon/tcon_tv_reg.h | 410 + bsp/drivers/drm/sunxi_device/sunxi_edp.c | 1065 +- bsp/drivers/drm/sunxi_device/sunxi_edp.h | 576 +- bsp/drivers/drm/sunxi_device/sunxi_edp_hdcp.c | 764 + bsp/drivers/drm/sunxi_device/sunxi_hdmi.c | 894 +- bsp/drivers/drm/sunxi_device/sunxi_hdmi.h | 525 +- bsp/drivers/drm/sunxi_device/sunxi_tcon.c | 1117 + bsp/drivers/drm/sunxi_device/sunxi_tcon.h | 68 +- bsp/drivers/drm/sunxi_device/sunxi_tcon_top.c | 74 +- bsp/drivers/drm/sunxi_device/sunxi_tcon_top.h | 1 + bsp/drivers/drm/sunxi_drm_crtc.c | 1606 +- bsp/drivers/drm/sunxi_drm_crtc.h | 56 +- bsp/drivers/drm/sunxi_drm_drv.c | 396 +- bsp/drivers/drm/sunxi_drm_drv.h | 20 +- bsp/drivers/drm/sunxi_drm_dsi.c | 940 + bsp/drivers/drm/sunxi_drm_edp.c | 896 +- bsp/drivers/drm/sunxi_drm_edp.h | 31 +- bsp/drivers/drm/sunxi_drm_hdmi.c | 2476 +- bsp/drivers/drm/sunxi_drm_hdmi.h | 9 - bsp/drivers/drm/sunxi_drm_intf.h | 2 +- bsp/drivers/drm/sunxi_drm_lvds.c | 594 + bsp/drivers/drm/sunxi_drm_rgb.c | 495 + bsp/drivers/drm/sunxi_drm_trace.c | 19 + bsp/drivers/drm/sunxi_drm_trace.h | 105 + bsp/drivers/drm/sunxi_fbdev.h | 77 + bsp/drivers/drm/sunxi_fbdev_core.c | 330 + bsp/drivers/drm/sunxi_fbdev_platform.c | 290 + bsp/drivers/gpu/panfrost/panfrost_device.c | 9 +- bsp/drivers/gpu/panfrost/panfrost_features.h | 29 - bsp/drivers/gpu/panfrost/panfrost_gpu.c | 36 +- bsp/drivers/gpu/panfrost/panfrost_issues.h | 21 +- bsp/drivers/gpu/panfrost/panfrost_regs.h | 4 +- bsp/drivers/iommu/sunxi-iommu-v1.c | 11 +- bsp/drivers/iommu/sunxi-iommu-v2.c | 11 +- bsp/drivers/iommu/sunxi-iommu-v3.c | 11 +- bsp/drivers/net/wireless/aic8800/Kconfig | 2 +- .../aw_nna_vip/linux/gc_vip_kernel_os_debug.c | 19 +- .../aw_nna_vip/linux/gc_vip_kernel_os_debug.h | 1 + bsp/drivers/pcie/Makefile | 1 + bsp/drivers/pcie/pcie-sunxi-dma.c | 184 +- bsp/drivers/pcie/pcie-sunxi-dma.h | 24 +- bsp/drivers/pcie/pcie-sunxi-ep.c | 31 +- bsp/drivers/pcie/pcie-sunxi-plat.c | 234 +- bsp/drivers/pcie/pcie-sunxi-rc.c | 33 +- bsp/drivers/pcie/pcie-sunxi.h | 13 +- bsp/drivers/phy/sunxi-inno-combophy.c | 270 +- bsp/drivers/power/mfd/axp2101-i2c.c | 1 + bsp/drivers/power/mfd/axp2101.c | 471 +- bsp/drivers/power/power_key/axp2101-pek.c | 86 +- .../power/regulator/axp2101-regulator.c | 183 + bsp/drivers/power/supply/axp2601_battery.h | 4 +- bsp/drivers/rtc/rtc-sunxi.c | 5 +- bsp/drivers/thermal/sunxi_thermal.c | 6 +- bsp/drivers/uart/sunxi-uart-ng-core.c | 4 - bsp/drivers/uart/sunxi-uart.c | 4 - bsp/drivers/usb/dwc3/phy-sunxi-plat.c | 30 +- bsp/drivers/usb/host/sunxi-hci.c | 50 +- bsp/drivers/usb/host/sunxi-hci.h | 2 +- bsp/drivers/ve/cedar-ve/cedar_ve.c | 2 +- .../video/sunxi/disp2/disp/de/disp_lcd.c | 36 +- .../disp2/hdmi2/aw_hdmi_core/aw_hdmi_core.c | 3 + .../disp2/hdmi2/aw_hdmi_core/dw_hdmi/dw_fc.c | 6 + .../disp2/hdmi2/aw_hdmi_core/dw_hdmi/dw_fc.h | 2 + 226 files changed, 139119 insertions(+), 9497 deletions(-) create mode 100644 bsp/drivers/drm/lib/inc/sha1.h create mode 100644 bsp/drivers/drm/lib/inc/sha256.h create mode 100644 bsp/drivers/drm/lib/src/sha1.c create mode 100644 bsp/drivers/drm/lib/src/sha256.c create mode 100644 bsp/drivers/drm/panel/dsi-panel-simple.c create mode 100644 bsp/drivers/drm/panel/panel-lvds.c create mode 100644 bsp/drivers/drm/panel/panel-rgb.c create mode 100644 bsp/drivers/drm/phy/Kconfig create mode 100644 bsp/drivers/drm/phy/Makefile create mode 100644 bsp/drivers/drm/phy/sunxi_dsi_combophy.c create mode 100644 bsp/drivers/drm/phy/sunxi_dsi_combophy_reg.c create mode 100644 bsp/drivers/drm/phy/sunxi_dsi_combophy_reg.h create mode 100644 bsp/drivers/drm/sunxi_device/hardware/lowlevel_de/Makefile create mode 100644 bsp/drivers/drm/sunxi_device/hardware/lowlevel_de/afbd/de_fbd_atw.c create mode 100644 bsp/drivers/drm/sunxi_device/hardware/lowlevel_de/afbd/de_fbd_atw.h create mode 100644 bsp/drivers/drm/sunxi_device/hardware/lowlevel_de/afbd/de_fbd_atw_type.h create mode 100644 bsp/drivers/drm/sunxi_device/hardware/lowlevel_de/bld/de_bld.c create mode 100644 bsp/drivers/drm/sunxi_device/hardware/lowlevel_de/bld/de_bld.h create mode 100644 bsp/drivers/drm/sunxi_device/hardware/lowlevel_de/bld/de_bld_platform.c create mode 100644 bsp/drivers/drm/sunxi_device/hardware/lowlevel_de/bld/de_bld_platform.h create mode 100644 bsp/drivers/drm/sunxi_device/hardware/lowlevel_de/bld/de_bld_type.h create mode 100644 bsp/drivers/drm/sunxi_device/hardware/lowlevel_de/cdc/de_cdc.c create mode 100644 bsp/drivers/drm/sunxi_device/hardware/lowlevel_de/cdc/de_cdc.h create mode 100644 bsp/drivers/drm/sunxi_device/hardware/lowlevel_de/cdc/de_cdc_platform.c create mode 100644 bsp/drivers/drm/sunxi_device/hardware/lowlevel_de/cdc/de_cdc_platform.h create mode 100644 bsp/drivers/drm/sunxi_device/hardware/lowlevel_de/cdc/de_cdc_table.c create mode 100644 bsp/drivers/drm/sunxi_device/hardware/lowlevel_de/cdc/de_cdc_table.h create mode 100644 bsp/drivers/drm/sunxi_device/hardware/lowlevel_de/cdc/de_cdc_type.h create mode 100644 bsp/drivers/drm/sunxi_device/hardware/lowlevel_de/crc/de_crc.c create mode 100644 bsp/drivers/drm/sunxi_device/hardware/lowlevel_de/crc/de_crc.h create mode 100644 bsp/drivers/drm/sunxi_device/hardware/lowlevel_de/crc/de_crc_platform.c create mode 100644 bsp/drivers/drm/sunxi_device/hardware/lowlevel_de/crc/de_crc_platform.h create mode 100644 bsp/drivers/drm/sunxi_device/hardware/lowlevel_de/crc/de_crc_type.h create mode 100644 bsp/drivers/drm/sunxi_device/hardware/lowlevel_de/csc/de_csc.c create mode 100644 bsp/drivers/drm/sunxi_device/hardware/lowlevel_de/csc/de_csc.h create mode 100644 bsp/drivers/drm/sunxi_device/hardware/lowlevel_de/csc/de_csc_platform.c create mode 100644 bsp/drivers/drm/sunxi_device/hardware/lowlevel_de/csc/de_csc_platform.h create mode 100644 bsp/drivers/drm/sunxi_device/hardware/lowlevel_de/csc/de_csc_table.c create mode 100644 bsp/drivers/drm/sunxi_device/hardware/lowlevel_de/csc/de_csc_table.h create mode 100644 bsp/drivers/drm/sunxi_device/hardware/lowlevel_de/csc/de_csc_type.h create mode 100644 bsp/drivers/drm/sunxi_device/hardware/lowlevel_de/csc/de_dcsc.h create mode 100644 bsp/drivers/drm/sunxi_device/hardware/lowlevel_de/csc/de_dcsc_type.h create mode 100644 bsp/drivers/drm/sunxi_device/hardware/lowlevel_de/dci/de_dci.c create mode 100644 bsp/drivers/drm/sunxi_device/hardware/lowlevel_de/dci/de_dci.h create mode 100644 bsp/drivers/drm/sunxi_device/hardware/lowlevel_de/dci/de_dci_platform.c create mode 100644 bsp/drivers/drm/sunxi_device/hardware/lowlevel_de/dci/de_dci_platform.h create mode 100644 bsp/drivers/drm/sunxi_device/hardware/lowlevel_de/dci/de_dci_type.h create mode 100644 bsp/drivers/drm/sunxi_device/hardware/lowlevel_de/de_backend.c create mode 100644 bsp/drivers/drm/sunxi_device/hardware/lowlevel_de/de_backend.h create mode 100644 bsp/drivers/drm/sunxi_device/hardware/lowlevel_de/de_base.h create mode 100644 bsp/drivers/drm/sunxi_device/hardware/lowlevel_de/de_channel.c create mode 100644 bsp/drivers/drm/sunxi_device/hardware/lowlevel_de/de_channel.h create mode 100644 bsp/drivers/drm/sunxi_device/hardware/lowlevel_de/de_frontend.c create mode 100644 bsp/drivers/drm/sunxi_device/hardware/lowlevel_de/de_frontend.h create mode 100644 bsp/drivers/drm/sunxi_device/hardware/lowlevel_de/de_top.c create mode 100644 bsp/drivers/drm/sunxi_device/hardware/lowlevel_de/de_top.h create mode 100644 bsp/drivers/drm/sunxi_device/hardware/lowlevel_de/dither/de_dither.c create mode 100644 bsp/drivers/drm/sunxi_device/hardware/lowlevel_de/dither/de_dither.h create mode 100644 bsp/drivers/drm/sunxi_device/hardware/lowlevel_de/dither/de_dither_platform.c create mode 100644 bsp/drivers/drm/sunxi_device/hardware/lowlevel_de/dither/de_dither_platform.h create mode 100644 bsp/drivers/drm/sunxi_device/hardware/lowlevel_de/dither/de_dither_type.h create mode 100644 bsp/drivers/drm/sunxi_device/hardware/lowlevel_de/fcm/de_fcm.c create mode 100644 bsp/drivers/drm/sunxi_device/hardware/lowlevel_de/fcm/de_fcm.h create mode 100644 bsp/drivers/drm/sunxi_device/hardware/lowlevel_de/fcm/de_fcm_platform.c create mode 100644 bsp/drivers/drm/sunxi_device/hardware/lowlevel_de/fcm/de_fcm_platform.h create mode 100644 bsp/drivers/drm/sunxi_device/hardware/lowlevel_de/fcm/de_fcm_type.h create mode 100644 bsp/drivers/drm/sunxi_device/hardware/lowlevel_de/gamma/de_gamma.c create mode 100644 bsp/drivers/drm/sunxi_device/hardware/lowlevel_de/gamma/de_gamma.h create mode 100644 bsp/drivers/drm/sunxi_device/hardware/lowlevel_de/gamma/de_gamma_platform.c create mode 100644 bsp/drivers/drm/sunxi_device/hardware/lowlevel_de/gamma/de_gamma_platform.h create mode 100644 bsp/drivers/drm/sunxi_device/hardware/lowlevel_de/gamma/de_gamma_type.h create mode 100644 bsp/drivers/drm/sunxi_device/hardware/lowlevel_de/ovl/de_ovl.c create mode 100644 bsp/drivers/drm/sunxi_device/hardware/lowlevel_de/ovl/de_ovl.h create mode 100644 bsp/drivers/drm/sunxi_device/hardware/lowlevel_de/ovl/de_ovl_platform.c create mode 100644 bsp/drivers/drm/sunxi_device/hardware/lowlevel_de/ovl/de_ovl_platform.h create mode 100644 bsp/drivers/drm/sunxi_device/hardware/lowlevel_de/ovl/de_ovl_type.h create mode 100644 bsp/drivers/drm/sunxi_device/hardware/lowlevel_de/scaler/de_scaler.c create mode 100644 bsp/drivers/drm/sunxi_device/hardware/lowlevel_de/scaler/de_scaler.h create mode 100644 bsp/drivers/drm/sunxi_device/hardware/lowlevel_de/scaler/de_scaler_platform.c create mode 100644 bsp/drivers/drm/sunxi_device/hardware/lowlevel_de/scaler/de_scaler_platform.h create mode 100644 bsp/drivers/drm/sunxi_device/hardware/lowlevel_de/scaler/de_scaler_table.c create mode 100644 bsp/drivers/drm/sunxi_device/hardware/lowlevel_de/scaler/de_scaler_table.h create mode 100644 bsp/drivers/drm/sunxi_device/hardware/lowlevel_de/scaler/de_scaler_type.h create mode 100644 bsp/drivers/drm/sunxi_device/hardware/lowlevel_de/sharp/de_sharp.c create mode 100644 bsp/drivers/drm/sunxi_device/hardware/lowlevel_de/sharp/de_sharp.h create mode 100644 bsp/drivers/drm/sunxi_device/hardware/lowlevel_de/sharp/de_sharp_platform.c create mode 100644 bsp/drivers/drm/sunxi_device/hardware/lowlevel_de/sharp/de_sharp_platform.h create mode 100644 bsp/drivers/drm/sunxi_device/hardware/lowlevel_de/sharp/de_sharp_type.h create mode 100644 bsp/drivers/drm/sunxi_device/hardware/lowlevel_de/smbl/de_smbl.c create mode 100644 bsp/drivers/drm/sunxi_device/hardware/lowlevel_de/smbl/de_smbl.h create mode 100644 bsp/drivers/drm/sunxi_device/hardware/lowlevel_de/smbl/de_smbl_platform.c create mode 100644 bsp/drivers/drm/sunxi_device/hardware/lowlevel_de/smbl/de_smbl_platform.h create mode 100644 bsp/drivers/drm/sunxi_device/hardware/lowlevel_de/smbl/de_smbl_tab.h create mode 100644 bsp/drivers/drm/sunxi_device/hardware/lowlevel_de/smbl/de_smbl_type.h create mode 100644 bsp/drivers/drm/sunxi_device/hardware/lowlevel_de/snr/de_snr.c create mode 100644 bsp/drivers/drm/sunxi_device/hardware/lowlevel_de/snr/de_snr.h create mode 100644 bsp/drivers/drm/sunxi_device/hardware/lowlevel_de/snr/de_snr_platform.c create mode 100644 bsp/drivers/drm/sunxi_device/hardware/lowlevel_de/snr/de_snr_platform.h create mode 100644 bsp/drivers/drm/sunxi_device/hardware/lowlevel_de/snr/de_snr_type.h create mode 100644 bsp/drivers/drm/sunxi_device/hardware/lowlevel_de/sunxi_de.c create mode 100644 bsp/drivers/drm/sunxi_device/hardware/lowlevel_de/sunxi_de.h create mode 100644 bsp/drivers/drm/sunxi_device/hardware/lowlevel_de/tfbd/de_tfbd.c create mode 100644 bsp/drivers/drm/sunxi_device/hardware/lowlevel_de/tfbd/de_tfbd.h create mode 100644 bsp/drivers/drm/sunxi_device/hardware/lowlevel_de/tfbd/de_tfbd_type.h create mode 100644 bsp/drivers/drm/sunxi_device/hardware/lowlevel_de/tfbd/img_drm_fourcc.h create mode 100644 bsp/drivers/drm/sunxi_device/hardware/lowlevel_de/wb/de_wb.c create mode 100644 bsp/drivers/drm/sunxi_device/hardware/lowlevel_de/wb/de_wb.h create mode 100644 bsp/drivers/drm/sunxi_device/hardware/lowlevel_de/wb/de_wb_type.h create mode 100644 bsp/drivers/drm/sunxi_device/hardware/lowlevel_edp/trilinear_dp14/trilinear_dp14.c create mode 100644 bsp/drivers/drm/sunxi_device/hardware/lowlevel_edp/trilinear_dp14/trilinear_dp14.h create mode 100644 bsp/drivers/drm/sunxi_device/hardware/lowlevel_lcd/dsi_v1.c create mode 100644 bsp/drivers/drm/sunxi_device/hardware/lowlevel_lcd/dsi_v1.h create mode 100644 bsp/drivers/drm/sunxi_device/hardware/lowlevel_lcd/dsi_v1_type.h create mode 100644 bsp/drivers/drm/sunxi_device/hardware/lowlevel_lcd/tcon_lcd.c create mode 100644 bsp/drivers/drm/sunxi_device/hardware/lowlevel_lcd/tcon_lcd.h create mode 100644 bsp/drivers/drm/sunxi_device/hardware/lowlevel_lcd/tcon_lcd_type.h create mode 100644 bsp/drivers/drm/sunxi_device/hardware/lowlevel_tcon/Makefile create mode 100644 bsp/drivers/drm/sunxi_device/hardware/lowlevel_tcon/tcon_top.c create mode 100644 bsp/drivers/drm/sunxi_device/hardware/lowlevel_tcon/tcon_top.h create mode 100644 bsp/drivers/drm/sunxi_device/hardware/lowlevel_tcon/tcon_top_type.h create mode 100644 bsp/drivers/drm/sunxi_device/hardware/lowlevel_tcon/tcon_tv.h create mode 100644 bsp/drivers/drm/sunxi_device/hardware/lowlevel_tcon/tcon_tv_reg.c create mode 100644 bsp/drivers/drm/sunxi_device/hardware/lowlevel_tcon/tcon_tv_reg.h create mode 100644 bsp/drivers/drm/sunxi_device/sunxi_edp_hdcp.c create mode 100644 bsp/drivers/drm/sunxi_device/sunxi_tcon.c create mode 100644 bsp/drivers/drm/sunxi_drm_dsi.c create mode 100644 bsp/drivers/drm/sunxi_drm_lvds.c create mode 100644 bsp/drivers/drm/sunxi_drm_rgb.c create mode 100644 bsp/drivers/drm/sunxi_drm_trace.c create mode 100644 bsp/drivers/drm/sunxi_drm_trace.h create mode 100644 bsp/drivers/drm/sunxi_fbdev.h create mode 100644 bsp/drivers/drm/sunxi_fbdev_core.c create mode 100644 bsp/drivers/drm/sunxi_fbdev_platform.c diff --git a/bsp/drivers/clk/sunxi-ng/ccu-sun55iw3.c b/bsp/drivers/clk/sunxi-ng/ccu-sun55iw3.c index ab743a9ec1..a3257c3f4d 100644 --- a/bsp/drivers/clk/sunxi-ng/ccu-sun55iw3.c +++ b/bsp/drivers/clk/sunxi-ng/ccu-sun55iw3.c @@ -40,16 +40,17 @@ #define UPD_KEY_VALUE 0x8000000 #define SUN55IW3_PLL_DDR_CTRL_REG 0x0010 -static struct ccu_nkmp pll_ddr_clk = { +static struct ccu_nm pll_ddr_clk = { .enable = BIT(27) | BIT(30) | BIT(31), .lock = BIT(28), - .n = _SUNXI_CCU_MULT_MIN(8, 8, 12), - .m = _SUNXI_CCU_DIV(0, 1), /* input divider */ - .p = _SUNXI_CCU_DIV(1, 1), /* output divider */ + .n = _SUNXI_CCU_MULT_MIN_MAX(8, 8, 50, 105), + .m = _SUNXI_CCU_DIV(0, 1), /* output divider */ + .min_rate = 600000000, + .max_rate = 2520000000, .common = { .reg = 0x0010, .hw.init = CLK_HW_INIT("pll-ddr", "dcxo24M", - &ccu_nkmp_ops, + &ccu_nm_ops, CLK_SET_RATE_UNGATE | CLK_IS_CRITICAL), }, @@ -59,8 +60,9 @@ static struct ccu_nkmp pll_ddr_clk = { static struct ccu_nm pll_peri0_parent_clk = { .enable = BIT(27) | BIT(30) | BIT(31), .lock = BIT(28), - .n = _SUNXI_CCU_MULT_MIN(8, 8, 12), - .m = _SUNXI_CCU_DIV(1, 1), /* input divider */ + .n = _SUNXI_CCU_MULT_MIN_MAX(8, 8, 50, 105), + .min_rate = 1200000000, + .max_rate = 2520000000, .common = { .reg = 0x0020, .hw.init = CLK_HW_INIT("pll-peri0-parent", "dcxo24M", @@ -119,8 +121,9 @@ static CLK_FIXED_FACTOR(pll_peri0_25m_clk, "pll-peri0-25m", static struct ccu_nm pll_peri1_parent_clk = { .enable = BIT(27) | BIT(30) | BIT(31), .lock = BIT(28), - .n = _SUNXI_CCU_MULT_MIN(8, 8, 12), - .m = _SUNXI_CCU_DIV(1, 1), /* input divider */ + .n = _SUNXI_CCU_MULT_MIN_MAX(8, 8, 50, 105), + .min_rate = 1200000000, + .max_rate = 2520000000, .common = { .reg = 0x0028, .hw.init = CLK_HW_INIT("pll-peri1-parent", "dcxo24M", @@ -164,87 +167,100 @@ static CLK_FIXED_FACTOR(pll_peri1_150m_clk, "pll-peri1-150m", 2, 1, 0); #define SUN55IW3_PLL_GPU_CTRL_REG 0x0030 -static struct ccu_nkmp pll_gpu_clk = { +static struct ccu_nm pll_gpu_clk = { .enable = BIT(27) | BIT(30) | BIT(31), .lock = BIT(28), - .n = _SUNXI_CCU_MULT_MIN(8, 8, 12), - .m = _SUNXI_CCU_DIV(1, 1), /* input divider */ - .p = _SUNXI_CCU_DIV(0, 1), /* output divider */ + .n = _SUNXI_CCU_MULT_MIN_MAX(8, 8, 50, 105), + .m = _SUNXI_CCU_DIV(0, 1), /* output divider */ + .min_rate = 600000000, + .max_rate = 2520000000, .common = { .reg = 0x0030, .hw.init = CLK_HW_INIT("pll-gpu", "dcxo24M", - &ccu_nkmp_ops, + &ccu_nm_ops, CLK_SET_RATE_UNGATE), }, }; #define SUN55IW3_PLL_VIDEO0_CTRL_REG 0x0040 -static struct ccu_nkmp pll_video0_4x_clk = { +static struct ccu_nm pll_video0_parent_clk = { .enable = BIT(27) | BIT(30) | BIT(31), .lock = BIT(28), - .n = _SUNXI_CCU_MULT_MIN(8, 8, 12), - .m = _SUNXI_CCU_DIV(1, 1), /* input divider */ - .p = _SUNXI_CCU_DIV(0, 1), /* output divider */ + .n = _SUNXI_CCU_MULT_MIN_MAX(8, 8, 50, 105), + .min_rate = 1200000000, + .max_rate = 2520000000, .common = { .reg = 0x0040, - .hw.init = CLK_HW_INIT("pll-video0-4x", "dcxo24M", - &ccu_nkmp_ops, + .hw.init = CLK_HW_INIT("pll-video0-parent", "dcxo24M", + &ccu_nm_ops, CLK_SET_RATE_UNGATE | CLK_IGNORE_UNUSED), }, }; +static SUNXI_CCU_M(pll_video0_4x_clk, "pll-video0-4x", + "pll-video0-parent", 0x0040, 0, 1, CLK_SET_RATE_PARENT); + static CLK_FIXED_FACTOR_HW(pll_video0_3x_clk, "pll-video0-3x", - &pll_video0_4x_clk.common.hw, - 1, 3, 0); + &pll_video0_parent_clk.common.hw, + 3, 1, 0); #define SUN55IW3_PLL_VIDEO1_CTRL_REG 0x0048 -static struct ccu_nm pll_video1_4x_clk = { +static struct ccu_nm pll_video1_parent_clk = { .enable = BIT(27) | BIT(30) | BIT(31), .lock = BIT(28), - .n = _SUNXI_CCU_MULT_MIN(8, 8, 12), - .m = _SUNXI_CCU_DIV(1, 1), /* input divider */ + .n = _SUNXI_CCU_MULT_MIN_MAX(8, 8, 50, 105), + .min_rate = 1200000000, + .max_rate = 2520000000, .common = { .reg = 0x0048, - .hw.init = CLK_HW_INIT("pll-video1-4x", "dcxo24M", + .hw.init = CLK_HW_INIT("pll-video1-parent", "dcxo24M", &ccu_nm_ops, CLK_SET_RATE_UNGATE | CLK_IGNORE_UNUSED), }, }; +static SUNXI_CCU_M(pll_video1_4x_clk, "pll-video1-4x", + "pll-video1-parent", 0x0048, 0, 1, CLK_SET_RATE_PARENT); + static CLK_FIXED_FACTOR_HW(pll_video1_3x_clk, "pll-video1-3x", - &pll_video1_4x_clk.common.hw, - 1, 3, 0); + &pll_video1_parent_clk.common.hw, + 3, 1, 0); #define SUN55IW3_PLL_VIDEO2_CTRL_REG 0x0050 -static struct ccu_nm pll_video2_4x_clk = { +static struct ccu_nm pll_video2_parent_clk = { .enable = BIT(27) | BIT(30) | BIT(31), .lock = BIT(28), - .n = _SUNXI_CCU_MULT_MIN(8, 8, 12), - .m = _SUNXI_CCU_DIV(1, 1), /* input divider */ + .n = _SUNXI_CCU_MULT_MIN_MAX(8, 8, 50, 105), + .min_rate = 1200000000, + .max_rate = 2520000000, .common = { .reg = 0x0050, - .hw.init = CLK_HW_INIT("pll-video2-4x", "dcxo24M", + .hw.init = CLK_HW_INIT("pll-video2-parent", "dcxo24M", &ccu_nm_ops, CLK_SET_RATE_UNGATE), }, }; +static SUNXI_CCU_M(pll_video2_4x_clk, "pll-video2-4x", + "pll-video2-parent", 0x0050, 0, 1, CLK_SET_RATE_PARENT); + static CLK_FIXED_FACTOR_HW(pll_video2_3x_clk, "pll-video2-3x", - &pll_video2_4x_clk.common.hw, - 1, 3, 0); + &pll_video2_parent_clk.common.hw, + 3, 1, 0); #define SUN55IW3_PLL_VE_CTRL_REG 0x0058 -static struct ccu_nkmp pll_ve_clk = { +static struct ccu_nm pll_ve_clk = { .enable = BIT(27) | BIT(30) | BIT(31), .lock = BIT(28), - .n = _SUNXI_CCU_MULT_MIN(8, 8, 12), - .m = _SUNXI_CCU_DIV(0, 1), /* input divider */ - .p = _SUNXI_CCU_DIV(1, 1), /* output divider */ + .n = _SUNXI_CCU_MULT_MIN_MAX(8, 8, 50, 105), + .m = _SUNXI_CCU_DIV(0, 1), /* output divider */ .sdm = _SUNXI_CCU_SDM_INFO(BIT(24), 0x158), + .min_rate = 600000000, + .max_rate = 2520000000, .common = { .reg = 0x0058, .hw.init = CLK_HW_INIT("pll-ve", "dcxo24M", - &ccu_nkmp_ops, + &ccu_nm_ops, CLK_SET_RATE_UNGATE), }, }; @@ -253,9 +269,10 @@ static struct ccu_nkmp pll_ve_clk = { static struct ccu_nm pll_video3_parent_clk = { .enable = BIT(27) | BIT(30) | BIT(31), .lock = BIT(28), - .n = _SUNXI_CCU_MULT_MIN(8, 8, 12), - .m = _SUNXI_CCU_DIV(1, 1), /* input divider */ + .n = _SUNXI_CCU_MULT_MIN_MAX(8, 8, 50, 105), .sdm = _SUNXI_CCU_SDM_INFO(BIT(24), 0x168), + .min_rate = 1200000000, + .max_rate = 2520000000, .common = { .reg = 0x0068, .hw.init = CLK_HW_INIT("pll-video3-parent", "dcxo24M", @@ -273,14 +290,14 @@ static CLK_FIXED_FACTOR_HW(pll_video3_3x_clk, "pll-video3-3x", #define SUN55IW3_PLL_AUDIO0_REG 0x078 static struct ccu_sdm_setting pll_audio0_sdm_table[] = { - { .rate = 196608000, .pattern = 0xC001EB85, .m = 5, .n = 40 }, /* 24.576 */ + { .rate = 196608000, .pattern = 0xC001D70A, .m = 10, .n = 81 }, /* 24.576 */ { .rate = 1083801600, .pattern = 0xA000A234, .m = 2, .n = 90 }, /* 22.5792 */ }; static struct ccu_nm pll_audio0_4x_clk = { .enable = BIT(27) | BIT(30) | BIT(31), .lock = BIT(28), - .n = _SUNXI_CCU_MULT_MIN(8, 8, 12), + .n = _SUNXI_CCU_MULT_MIN_MAX(8, 8, 50, 105), .m = _SUNXI_CCU_DIV(16, 6), .sdm = _SUNXI_CCU_SDM(pll_audio0_sdm_table, BIT(24), 0x178, BIT(31)), @@ -309,8 +326,9 @@ static CLK_FIXED_FACTOR(pll_audio0_div_48m_clk, "pll-audio0-div-48m", static struct ccu_nm pll_npu_4x_clk = { .enable = BIT(27) | BIT(30) | BIT(31), .lock = BIT(28), - .n = _SUNXI_CCU_MULT_MIN(8, 8, 12), - .m = _SUNXI_CCU_DIV(1, 1), /* input divider */ + .n = _SUNXI_CCU_MULT_MIN_MAX(8, 8, 50, 105), + .min_rate = 1200000000, + .max_rate = 2520000000, .common = { .reg = 0x0080, .hw.init = CLK_HW_INIT("pll-npu-4x", "dcxo24M", @@ -1350,10 +1368,13 @@ static struct clk_hw_onecell_data sun55iw3_hw_clks = { [CLK_PLL_PERI1_160M] = &pll_peri1_160m_clk.hw, [CLK_PLL_PERI1_150M] = &pll_peri1_150m_clk.hw, [CLK_PLL_GPU] = &pll_gpu_clk.common.hw, + [CLK_PLL_VIDEO0_PARENT] = &pll_video0_parent_clk.common.hw, [CLK_PLL_VIDEO0_4X] = &pll_video0_4x_clk.common.hw, [CLK_PLL_VIDEO0_3X] = &pll_video0_3x_clk.hw, + [CLK_PLL_VIDEO1_PARENT] = &pll_video1_parent_clk.common.hw, [CLK_PLL_VIDEO1_4X] = &pll_video1_4x_clk.common.hw, [CLK_PLL_VIDEO1_3X] = &pll_video1_3x_clk.hw, + [CLK_PLL_VIDEO2_PARENT] = &pll_video2_parent_clk.common.hw, [CLK_PLL_VIDEO2_4X] = &pll_video2_4x_clk.common.hw, [CLK_PLL_VIDEO2_3X] = &pll_video2_3x_clk.hw, [CLK_PLL_VIDEO3_PARENT] = &pll_video3_parent_clk.common.hw, @@ -1532,8 +1553,11 @@ static struct ccu_common *sun55iw3_ccu_clks[] = { &pll_peri1_800m_clk.common, &pll_peri1_480m_clk.common, &pll_gpu_clk.common, + &pll_video0_parent_clk.common, &pll_video0_4x_clk.common, + &pll_video1_parent_clk.common, &pll_video1_4x_clk.common, + &pll_video2_parent_clk.common, &pll_video2_4x_clk.common, &pll_video3_parent_clk.common, &pll_video3_4x_clk.common, @@ -1725,11 +1749,6 @@ static const u32 sun55iw3_pll_regs[] = { SUN55IW3_PLL_NPU_CTRL_REG, }; -static const u32 sun55iw3_pll_video_regs[] = { - SUN55IW3_PLL_VIDEO1_CTRL_REG, - SUN55IW3_PLL_VIDEO2_CTRL_REG, -}; - static const u32 sun55iw3_usb_clk_regs[] = { SUN55IW3_USB0_CTRL_REG, SUN55IW3_USB1_CTRL_REG, @@ -1767,14 +1786,7 @@ static int sun55iw3_ccu_probe(struct platform_device *pdev) set_reg(reg + SUN55IW3_PLL_PERIPH1_PATTERN0_REG, 0xd1303333, 32, 0); set_reg(reg +SUN55IW3_PLL_PERI1_CTRL_REG, 1, 1, 24); - /* - * Force the output divider of video PLLs to 0. - * - * See the comment before pll-video0 definition for the reason. - */ - for (i = 0; i < ARRAY_SIZE(sun55iw3_pll_video_regs); i++) { - set_reg(reg + sun55iw3_pll_video_regs[i], 0x0, 1, 0); - } + set_reg(reg + SUN55IW3_PLL_NPU_CTRL_REG, 0x0, 1, 1); /* Enforce m1 = 0, m0 = 1 for Audio PLL */ set_reg(reg + SUN55IW3_PLL_AUDIO0_REG, 0x1, 0, 0); diff --git a/bsp/drivers/clk/sunxi-ng/ccu_mult.h b/bsp/drivers/clk/sunxi-ng/ccu_mult.h index ed2e9ff118..bbd8163d51 100644 --- a/bsp/drivers/clk/sunxi-ng/ccu_mult.h +++ b/bsp/drivers/clk/sunxi-ng/ccu_mult.h @@ -24,6 +24,9 @@ struct ccu_mult_internal { .width = _width, \ } +#define _SUNXI_CCU_MULT_MIN_MAX(_shift, _width, _min, _max) \ + _SUNXI_CCU_MULT_OFFSET_MIN_MAX(_shift, _width, 1, _min, _max) + #define _SUNXI_CCU_MULT_MIN(_shift, _width, _min) \ _SUNXI_CCU_MULT_OFFSET_MIN_MAX(_shift, _width, 1, _min, 0) diff --git a/bsp/drivers/clk/sunxi-ng/ccu_nm.c b/bsp/drivers/clk/sunxi-ng/ccu_nm.c index a8e35c7671..fae204bd06 100644 --- a/bsp/drivers/clk/sunxi-ng/ccu_nm.c +++ b/bsp/drivers/clk/sunxi-ng/ccu_nm.c @@ -256,8 +256,10 @@ static int ccu_nm_set_rate(struct clk_hw *hw, unsigned long _rate, spin_lock_irqsave(nm->common.lock, flags); reg = readl(nm->common.base + nm->common.reg); - reg &= ~GENMASK(nm->n.width + nm->n.shift - 1, nm->n.shift); - reg &= ~GENMASK(nm->m.width + nm->m.shift - 1, nm->m.shift); + if (nm->n.width) + reg &= ~GENMASK(nm->n.width + nm->n.shift - 1, nm->n.shift); + if (nm->m.width) + reg &= ~GENMASK(nm->m.width + nm->m.shift - 1, nm->m.shift); reg |= (_nm.n - nm->n.offset) << nm->n.shift; reg |= (_nm.m - nm->m.offset) << nm->m.shift; diff --git a/bsp/drivers/drm/Kconfig b/bsp/drivers/drm/Kconfig index 3ea1d9414d..ce9801b741 100644 --- a/bsp/drivers/drm/Kconfig +++ b/bsp/drivers/drm/Kconfig @@ -20,6 +20,7 @@ config AW_DRM_DE help If you want use DE of Version 35X, select it. +# remove it after both tcon_lcd/tcon_tv ready? config AW_DRM_TCON bool "Support Timing Controller(TCON)" depends on AW_DRM @@ -27,6 +28,13 @@ config AW_DRM_TCON help If you want use TCON, select it. +config AW_DRM_TCON_TV + bool "Support Timing Controller(TCON_TV)" + depends on AW_DRM + default y + help + If you want use TCON_TV, select it. + config AW_DRM_TCON_TOP bool "Support TCON TOP" depends on AW_DRM @@ -34,35 +42,32 @@ config AW_DRM_TCON_TOP help If you want use TCON TOP, select it. -config AW_DRM_FBDEV_BOOTLOGO - bool "Support Bootlogo Output from uboot" - depends on AW_DRM_LCD +config AW_DRM_LVDS + bool "Support LVDS Output" + depends on AW_DRM + select GENERIC_PHY default n help - If you want bootlogo output for drm driver, select it. + If you want use lvds, select it. -menuconfig AW_DRM_LCD - bool "Support LCD Output" +config AW_DRM_RGB + bool "Support RGB Output" depends on AW_DRM - default y + select GENERIC_PHY + default n help - If you want lcd output for drm driver, select it. + If you want use rgb, select it. -config AW_DRM_LCD_DSI - bool "Support LCD-DSI Output" +config AW_DRM_DSI + bool "Support DSI Output" + depends on AW_DRM select DRM_MIPI_DSI - depends on AW_DRM_LCD + select GENERIC_PHY + select GENERIC_PHY_MIPI_DPHY default n help If you want lcd-dsi output for drm driver, select it. -config AW_DRM_LCD_DSI_COMBO_PHY - bool "Support LCD-DSI COMBO PHY" - depends on AW_DRM_LCD_DSI - default y - help - If you want lcd-dsi combp phy, select it. - menuconfig AW_DRM_HDMI_TX tristate "Support Hdmi Output" depends on AW_DRM @@ -83,38 +88,10 @@ menuconfig AW_DRM_HDMI20 bool "Support HDMI2.0 Output" depends on AW_DRM_HDMI_TX default y - help - If you want hdmi2.0 output for drm driver, select it. - -config AW_HDMI20_HDCP14 - bool "HDMI2.0 HDCP1.4" - depends on (AW_DRM_HDMI20) - default n - help - Say Y here if you want to enable hdcp1.4 function. - Say N here if you want to disable hdcp1.4 function. - If unsure, say N. - -config AW_HDMI20_HDCP22 - bool "HDMI2.0 HDCP2.2" - depends on (AW_DRM_HDMI20) - default n - help - Say Y here if you want to enable hdcp2.2 function. - Say N here if you want to disable hdcp2.2 function. - If unsure, say N. - -config AW_HDMI20_CEC - bool "HDMI2.0 CEC" - depends on (AW_DRM_HDMI20) - default n select CEC_CORE select CEC_NOTIFIER help - Say Y here if you want to enable cec function. - Also enable CEC_CORE and CEC_NOTIFIER. - Say N here if you want to disable cec function. - If unsure, say N. + If you want hdmi2.0 output for drm driver, select it. menuconfig AW_DRM_EDP bool "Support eDP Output" @@ -124,21 +101,42 @@ menuconfig AW_DRM_EDP help If you want edp/dp output for drm driver, select it. -config AW_DRM_EDP_PHY_USED +config AW_DRM_EDP_CONTROLLER_USED def_bool n depends on (AW_DRM_EDP) default n help Selected when aw edp phy used. +config AW_DRM_DP_HDCP + def_bool n + bool "Support HDCP For DisplayPort" + depends on (AW_DRM_EDP) + default n + help + Selected when hdcp need authenticate by software. + config AW_DRM_INNO_EDP13 - bool "Support inno edp 1.3 PHY" + bool "Support inno edp 1.3 controller" + depends on AW_DRM_EDP + select AW_DRM_EDP_CONTROLLER_USED + default n + help + If you want inno edp 1.3 as edp controller, select it. + +config AW_DRM_TRILINEAR_EDP14 + bool "Support trilinear edp 1.4 controller" depends on AW_DRM_EDP - select AW_DRM_EDP_PHY_USED + select AW_DRM_EDP_CONTROLLER_USED + select AW_DRM_DP_HDCP default n help - If you want inno edp 1.3 as edp phy, select it. + If you want trilinear edp 1.4 as edp controller, select it. +menu "sunxi drm panels select" + depends on AW_DRM source "bsp/drivers/drm/panel/Kconfig" +endmenu +source "bsp/drivers/drm/phy/Kconfig" endmenu diff --git a/bsp/drivers/drm/Makefile b/bsp/drivers/drm/Makefile index 87b6589823..ee832d2027 100644 --- a/bsp/drivers/drm/Makefile +++ b/bsp/drivers/drm/Makefile @@ -1,39 +1,63 @@ # SPDX-License-Identifier: GPL-2.0-only -mkfile_path := $(abspath $(lastword $(MAKEFILE_LIST))) -mkfile_dir := $(dir $(mkfile_path)) +ccflags-y += -I$(srctree)/$(obj)/sunxi_device/hardware/ +ccflags-y += -I$(srctree)/$(obj)/sunxi_device/hardware/lowlevel_lcd/ +ccflags-y += -I$(srctree)/$(obj)/sunxi_device/hardware/lowlevel_tcon/ +ccflags-y += -I$(srctree)/$(obj)/phy/ +ccflags-y += -I$(srctree)/$(obj)/lib/inc/ -ccflags-y += -I$(mkfile_dir)/sunxi_device/hardware -ccflags-y += -I$(mkfile_dir)/ +# base +sunxidrm-y += sunxi_drm_drv.o sunxi_drm_crtc.o sunxi_drm_intf.o -# Although now only support v35x, new platform support should not add new dir -ccflags-y += -I$(mkfile_dir)/sunxi_device/hardware/lowlevel_v35x/tcon -ccflags-y += -I$(mkfile_dir)/sunxi_device/hardware/lowlevel_v35x/ -ccflags-y += -DDE_VERSION_V35X -include $(srctree)/$(obj)/sunxi_device/hardware/lowlevel_v35x/Makefile +#fbdev +sunxidrm-$(CONFIG_DRM_FBDEV_EMULATION) += sunxi_fbdev_core.o sunxi_fbdev_platform.o -obj-$(CONFIG_AW_DRM) += sunxidrm.o +# de +include $(srctree)/$(obj)/sunxi_device/hardware/lowlevel_de/Makefile +sunxidrm-$(CONFIG_AW_DRM_DE) += $(de_obj) -sunxidrm-y += sunxi_drm_drv.o sunxi_drm_crtc.o sunxi_drm_intf.o sunxi_drm_fbdev.o -sunxidrm-y += $(obj_low) +# tcon +include $(srctree)/$(obj)/sunxi_device/hardware/lowlevel_tcon/Makefile +sunxidrm-$(CONFIG_AW_DRM_TCON) += $(tcon_obj) \ + sunxi_device/sunxi_tcon.o \ + sunxi_device/hardware/lowlevel_lcd/tcon_lcd.o -sunxidrm-$(CONFIG_AW_DRM_DE) += sunxi_device/sunxi_de_v35x.o -sunxidrm-$(CONFIG_AW_DRM_TCON) += sunxi_device/sunxi_tcon_v35x.o +# tcon_top sunxidrm-$(CONFIG_AW_DRM_TCON_TOP) += sunxi_device/sunxi_tcon_top.o -sunxidrm-$(CONFIG_AW_DRM_LCD) += sunxi_drm_lcd.o panel/panels.o -sunxidrm-$(CONFIG_AW_DRM_LCD_DSI) += sunxi_device/sunxi_dsi.o -sunxidrm-$(CONFIG_AW_DRM_LCD_DSI_COMBO_PHY) += sunxi_device/sunxi_dsi_combo_phy.o -# add HDMI +# dsi +sunxidrm-$(CONFIG_AW_DRM_DSI) += sunxi_drm_dsi.o \ + sunxi_device/hardware/lowlevel_lcd/dsi_v1.o + +# lvds +sunxidrm-$(CONFIG_AW_DRM_LVDS) += sunxi_drm_lvds.o + +# rgb +sunxidrm-$(CONFIG_AW_DRM_RGB) += sunxi_drm_rgb.o + +# HDMI sunxidrm-$(CONFIG_AW_DRM_HDMI_TX) += sunxi_drm_hdmi.o sunxidrm-$(CONFIG_AW_DRM_HDMI_TX) += sunxi_device/sunxi_hdmi.o -ccflags-$(CONFIG_AW_DRM_HDMI20) += -I$(mkfile_dir)/sunxi_device/hardware/lowlevel_hdmi20/ +ccflags-$(CONFIG_AW_DRM_HDMI20) += -I$(src)/sunxi_device/hardware/lowlevel_hdmi20/ include $(srctree)/$(obj)/sunxi_device/hardware/lowlevel_hdmi20/Makefile sunxidrm-$(CONFIG_AW_DRM_HDMI20) += $(obj_low_hdmi) # edp sunxidrm-$(CONFIG_AW_DRM_EDP) += sunxi_drm_edp.o sunxidrm-$(CONFIG_AW_DRM_EDP) += sunxi_device/sunxi_edp.o +sunxidrm-$(CONFIG_AW_DRM_DP_HDCP) += sunxi_device/sunxi_edp_hdcp.o +sunxidrm-$(CONFIG_AW_DRM_DP_HDCP) += lib/src/sha1.o sunxidrm-$(CONFIG_AW_DRM_INNO_EDP13) += sunxi_device/hardware/lowlevel_edp/inno_edp13/inno_edp13.o +sunxidrm-$(CONFIG_AW_DRM_TRILINEAR_EDP14) += sunxi_device/hardware/lowlevel_edp/trilinear_dp14/trilinear_dp14.o + +# phy +obj-$(CONFIG_AW_DRM_PHY) += phy/ # panel -obj-$(CONFIG_AW_DRM_PANEL) += panel/ +obj-y += panel/ + +# tracepoints +# define_trace.h needs to know how to find our header +CFLAGS_sunxi_drm_trace.o := -I$(src) +sunxidrm-y += sunxi_drm_trace.o + +obj-$(CONFIG_AW_DRM) += sunxidrm.o diff --git a/bsp/drivers/drm/lib/inc/sha1.h b/bsp/drivers/drm/lib/inc/sha1.h new file mode 100644 index 0000000000..56f507cf44 --- /dev/null +++ b/bsp/drivers/drm/lib/inc/sha1.h @@ -0,0 +1,55 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * sha1.h + * + * Description: + * This is the header file for code which implements the Secure + * Hashing Algorithm 1 as defined in FIPS PUB 180-1 published + * April 17, 1995. + * + * Many of the variable names in this code, especially the + * single character names, were used because those were the names + * used in the publication. + * + * Please read the file sha1.c for more information. + * + * Copyright (c) 2007-2022 Allwinnertech Co., Ltd. + * Author: huangyongxing + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + */ +#ifndef __SHA1_H__ +#define __SHA1_H__ +//#include +#include +#define SHA1HashSize 20 + +enum { + shaSuccess = 0, + shaNull, /* Null pointer parameter */ + shaInputTooLong, /* input data too long */ + shaStateError /* called Input after Result */ +}; + +/* + * This structure will hold context information for the SHA-1 + * hashing operation + */ +typedef struct SHA1Context { + uint32_t Intermediate_Hash[SHA1HashSize / 4]; // Message Digest + uint32_t Length_Low; // Message length in bits + uint32_t Length_High; // Message length in bits + short int Message_Block_Index; // Index into message block array + uint8_t Message_Block[64]; // 512-bit message blocks + int Computed; // Is the digest computed? + int Corrupted; // Is the message digest corrupted? +} SHA1Context; + +int SHA1Reset(SHA1Context *); +int SHA1Input(SHA1Context *, const uint8_t *, unsigned int); +int SHA1Result(SHA1Context *, uint8_t Message_Digest[SHA1HashSize]); + +#endif diff --git a/bsp/drivers/drm/lib/inc/sha256.h b/bsp/drivers/drm/lib/inc/sha256.h new file mode 100644 index 0000000000..0398ed3ebc --- /dev/null +++ b/bsp/drivers/drm/lib/inc/sha256.h @@ -0,0 +1,40 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +//------------------------------------------------------------------------------ +// +// COPYRIGHT (c) 2018-2022 TRILINEAR TECHNOLOGIES, INC. +// CONFIDENTIAL AND PROPRIETARY +// +// THE SOURCE CODE CONTAINED HEREIN IS PROVIDED ON AN "AS IS" BASIS. +// TRILINEAR TECHNOLOGIES, INC. DISCLAIMS ANY AND ALL WARRANTIES, +// WHETHER EXPRESS, IMPLIED, OR STATUTORY, INCLUDING ANY IMPLIED +// WARRANTIES OF MERCHANTABILITY OR OF FITNESS FOR A PARTICULAR PURPOSE. +// IN NO EVENT SHALL TRILINEAR TECHNOLOGIES, INC. BE LIABLE FOR ANY +// INCIDENTAL, PUNITIVE, OR CONSEQUENTIAL DAMAGES OF ANY KIND WHATSOEVER +// ARISING FROM THE USE OF THIS SOURCE CODE. +// +// THIS DISCLAIMER OF WARRANTY EXTENDS TO THE USER OF THIS SOURCE CODE +// AND USER'S CUSTOMERS, EMPLOYEES, AGENTS, TRANSFEREES, SUCCESSORS, +// AND ASSIGNS. +// +// THIS IS NOT A GRANT OF PATENT RIGHTS +//------------------------------------------------------------------------------ +// +// Original License: +// public domain sha256 implementation based on fips180-3 +// +//------------------------------------------------------------------------------ +#ifndef __SHA256_H__ +#define __SHA256_H__ +#define SHA256_DIGEST_LENGTH 32 + +typedef struct { + uint64_t len; /* processed message length */ + uint32_t h[8]; /* hash state */ + uint8_t buf[64]; /* message block buffer */ +} sha256_t; + +void sha256_init(sha256_t *ctx); +void sha256_update(sha256_t *ctx, const void *m, uint32_t len); +void sha256_sum(sha256_t *ctx, uint8_t md[SHA256_DIGEST_LENGTH]); + +#endif diff --git a/bsp/drivers/drm/lib/src/sha1.c b/bsp/drivers/drm/lib/src/sha1.c new file mode 100644 index 0000000000..92f2a82f53 --- /dev/null +++ b/bsp/drivers/drm/lib/src/sha1.c @@ -0,0 +1,360 @@ + +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * sha1.c + * + * Description: + * This file implements the Secure Hashing Algorithm 1 as + * defined in FIPS PUB 180-1 published April 17, 1995. + * + * The SHA-1, produces a 160-bit message digest for a given + * data stream. It should take about 2**n steps to find a + * message with the same digest as a given message and + * 2**(n/2) to find any two messages with the same digest, + * when n is the digest size in bits. Therefore, this + * algorithm can serve as a means of providing a + * "fingerprint" for a message. + * + * Portability Issues: + * SHA-1 is defined in terms of 32-bit "words". This code + * uses (included via "sha1.h" to define 32 and 8 + * bit unsigned integer types. If your C compiler does not + * support 32 bit unsigned integers, this code is not + * appropriate. + * + * Caveats: + * SHA-1 is designed to work with messages less than 2^64 bits + * long. Although SHA-1 allows a message digest to be generated + * for messages of any number of bits less than 2^64, this + * implementation only works with messages with a length that is + * a multiple of the size of an 8-bit character. + * + * Copyright (c) 2007-2022 Allwinnertech Co., Ltd. + * Author: huangyongxing + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + */ + +#include "sha1.h" + +/* + * Define the SHA1 circular left shift macro + */ +#define SHA1CircularShift(bits, word) \ + (((word) << (bits)) | ((word) >> (32 - (bits)))) + +/* Local Function Prototyptes */ +void SHA1PadMessage(SHA1Context *); +void SHA1ProcessMessageBlock(SHA1Context *); + +/* + * Function: SHA1Reset + * + * Description: + * This function will initialize the SHA1Context in preparation + * for computing a new SHA1 message digest. + * + * Parameters: + * context - [in/out] The context to reset. + * + * Returns: + * Error Code. + * + */ +int SHA1Reset(SHA1Context *context) +{ + if (!context) { + return shaNull; + } + + context->Length_Low = 0; + context->Length_High = 0; + context->Message_Block_Index = 0; + + context->Intermediate_Hash[0] = 0x67452301; + context->Intermediate_Hash[1] = 0xEFCDAB89; + context->Intermediate_Hash[2] = 0x98BADCFE; + context->Intermediate_Hash[3] = 0x10325476; + context->Intermediate_Hash[4] = 0xC3D2E1F0; + + context->Computed = 0; + context->Corrupted = 0; + + return shaSuccess; +} + +/* + * Function: SHA1Result + * + * Description: + * This function will return the 160-bit message digest into the + * Message_Digest array provided by the caller. + * NOTE: The first octet of hash is stored in the 0th element, + * the last octet of hash in the 19th element. + * + * Parameters: + * context - [in/out] The context to use to calculate the SHA-1 hash. + * Message_Digest - [out] Where the digest is returned. + * + * Returns: + * Error Code. + * + */ +int SHA1Result(SHA1Context *context, + uint8_t Message_Digest[SHA1HashSize]) +{ + int i; + + if ((!context) || (!Message_Digest)) { + return shaNull; + } + + if (context->Corrupted) { + return context->Corrupted; + } + + if (!context->Computed) { + SHA1PadMessage(context); + for (i = 0; i < 64; ++i) { + /* message may be sensitive, clear it out */ + context->Message_Block[i] = 0; + } + context->Length_Low = 0; /* and clear length */ + context->Length_High = 0; + context->Computed = 1; + } + + for (i = 0; i < SHA1HashSize; ++i) { + Message_Digest[i] = context->Intermediate_Hash[i >> 2] + >> 8 * (3 - (i & 0x03)); + } + + return shaSuccess; +} + +/* + * Function: SHA1Input + * + * Description: + * This function accepts an array of octets as the next portion + * of the message. + * + * Parameters: + * context - [in/out] The SHA context to update + * message_array - [in] An array of characters representing the next portion of the message. + * length - [in] The length of the message in message_array + * + * Returns: + * Error Code. + * + */ +int SHA1Input(SHA1Context *context, const uint8_t *message_array, unsigned length_val) +{ + unsigned length = length_val; // temporary value to prevent 14 D Attempt to change parameter passed by value + + if (!length) { + return shaSuccess; + } + + if ((!context) || (!message_array)) { + return shaNull; + } + + if (context->Computed) { + context->Corrupted = shaStateError; + return shaStateError; + } + + if (context->Corrupted) { + return context->Corrupted; + } + while ((length--) && (!context->Corrupted)) { + context->Message_Block[context->Message_Block_Index++] = + (*message_array & 0xFF); + + context->Length_Low += 8; + if (context->Length_Low == 0) { + context->Length_High++; + if (context->Length_High == 0) { + /* Message is too long */ + context->Corrupted = 1; + } + } + + if (context->Message_Block_Index == 64) { + SHA1ProcessMessageBlock(context); + } + + message_array++; + } + + return shaSuccess; +} + +/* + * Function: SHA1ProcessMessageBlock + * + * Description: + * This function will process the next 512 bits of the message + * stored in the Message_Block array. + * + * Parameters: + * None. + * + * Returns: + * Nothing. + * + * Comments: + * + * Many of the variable names in this code, especially the + * single character names, were used because those were the + * names used in the publication. + * + * + */ +void SHA1ProcessMessageBlock(SHA1Context *context) +{ + const uint32_t K[] = { /* Constants defined in SHA-1 */ + 0x5A827999, + 0x6ED9EBA1, + 0x8F1BBCDC, + 0xCA62C1D6 + }; + int t; /* Loop counter */ + uint32_t temp; /* Temporary word value */ + uint32_t Word_Sequence[80]; /* Word sequence */ + uint32_t Abuff, Bbuff, Cbuff, Dbuff, Ebuff; /* Word buffers */ + + /* + * Initialize the first 16 words in the array W + */ + for (t = 0; t < 16; t++) { + Word_Sequence[t] = context->Message_Block[t * 4] << 24; + Word_Sequence[t] |= context->Message_Block[t * 4 + 1] << 16; + Word_Sequence[t] |= context->Message_Block[t * 4 + 2] << 8; + Word_Sequence[t] |= context->Message_Block[t * 4 + 3]; + } + + for (t = 16; t < 80; t++) { + Word_Sequence[t] = SHA1CircularShift(1, Word_Sequence[t - 3] ^ Word_Sequence[t - 8] ^ Word_Sequence[t - 14] ^ Word_Sequence[t - 16]); + } + + Abuff = context->Intermediate_Hash[0]; + Bbuff = context->Intermediate_Hash[1]; + Cbuff = context->Intermediate_Hash[2]; + Dbuff = context->Intermediate_Hash[3]; + Ebuff = context->Intermediate_Hash[4]; + + for (t = 0; t < 20; t++) { + temp = SHA1CircularShift(5, Abuff) + + ((Bbuff & Cbuff) | ((~Bbuff) & Dbuff)) + Ebuff + Word_Sequence[t] + K[0]; + Ebuff = Dbuff; + Dbuff = Cbuff; + Cbuff = SHA1CircularShift(30, Bbuff); + + Bbuff = Abuff; + Abuff = temp; + } + + for (t = 20; t < 40; t++) { + temp = SHA1CircularShift(5, Abuff) + (Bbuff ^ Cbuff ^ Dbuff) + Ebuff + Word_Sequence[t] + K[1]; + Ebuff = Dbuff; + Dbuff = Cbuff; + Cbuff = SHA1CircularShift(30, Bbuff); + Bbuff = Abuff; + Abuff = temp; + } + + for (t = 40; t < 60; t++) { + temp = SHA1CircularShift(5, Abuff) + + ((Bbuff & Cbuff) | (Bbuff & Dbuff) | (Cbuff & Dbuff)) + Ebuff + Word_Sequence[t] + K[2]; + Ebuff = Dbuff; + Dbuff = Cbuff; + Cbuff = SHA1CircularShift(30, Bbuff); + Bbuff = Abuff; + Abuff = temp; + } + + for (t = 60; t < 80; t++) { + temp = SHA1CircularShift(5, Abuff) + (Bbuff ^ Cbuff ^ Dbuff) + Ebuff + Word_Sequence[t] + K[3]; + Ebuff = Dbuff; + Dbuff = Cbuff; + Cbuff = SHA1CircularShift(30, Bbuff); + Bbuff = Abuff; + Abuff = temp; + } + + context->Intermediate_Hash[0] += Abuff; + context->Intermediate_Hash[1] += Bbuff; + context->Intermediate_Hash[2] += Cbuff; + context->Intermediate_Hash[3] += Dbuff; + context->Intermediate_Hash[4] += Ebuff; + + context->Message_Block_Index = 0; +} + +/* + * Function: SHA1PadMessage + * + * Description: + * According to the standard, the message must be padded to an even + * 512 bits. The first padding bit must be a '1'. The last 64 + * bits represent the length of the original message. All bits in + * between should be 0. This function will pad the message + * according to those rules by filling the Message_Block array + * accordingly. It will also call the ProcessMessageBlock function + * provided appropriately. When it returns, it can be assumed that + * the message digest has been computed. + * + * Parameters: + * context - [in/out] The context to pad + * ProcessMessageBlock - [in] The appropriate SHA*ProcessMessageBlock function + * + * Returns: + * Nothing. + * + */ +void SHA1PadMessage(SHA1Context *context) +{ + /* + * Check to see if the current message block is too small to hold + * the initial padding bits and length. If so, we will pad the + * block, process it, and then continue padding into a second + * block. + */ + if (context->Message_Block_Index > 55) { + context->Message_Block[context->Message_Block_Index++] = 0x80; + while (context->Message_Block_Index < 64) { + context->Message_Block[context->Message_Block_Index++] = 0; + } + + SHA1ProcessMessageBlock(context); + + while (context->Message_Block_Index < 56) { + context->Message_Block[context->Message_Block_Index++] = 0; + } + } else { + context->Message_Block[context->Message_Block_Index++] = 0x80; + while (context->Message_Block_Index < 56) { + + context->Message_Block[context->Message_Block_Index++] = 0; + } + } + + /* + * Store the message length as the last 8 octets + */ + context->Message_Block[56] = context->Length_High >> 24; + context->Message_Block[57] = context->Length_High >> 16; + context->Message_Block[58] = context->Length_High >> 8; + context->Message_Block[59] = context->Length_High; + context->Message_Block[60] = context->Length_Low >> 24; + context->Message_Block[61] = context->Length_Low >> 16; + context->Message_Block[62] = context->Length_Low >> 8; + context->Message_Block[63] = context->Length_Low; + + SHA1ProcessMessageBlock(context); +} diff --git a/bsp/drivers/drm/lib/src/sha256.c b/bsp/drivers/drm/lib/src/sha256.c new file mode 100644 index 0000000000..0671b91f85 --- /dev/null +++ b/bsp/drivers/drm/lib/src/sha256.c @@ -0,0 +1,235 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +//------------------------------------------------------------------------------ +// COPYRIGHT (c) 2018-2022 TRILINEAR TECHNOLOGIES, INC. +// CONFIDENTIAL AND PROPRIETARY +// +// THE SOURCE CODE CONTAINED HEREIN IS PROVIDED ON AN "AS IS" BASIS. +// TRILINEAR TECHNOLOGIES, INC. DISCLAIMS ANY AND ALL WARRANTIES, +// WHETHER EXPRESS, IMPLIED, OR STATUTORY, INCLUDING ANY IMPLIED +// WARRANTIES OF MERCHANTABILITY OR OF FITNESS FOR A PARTICULAR PURPOSE. +// IN NO EVENT SHALL TRILINEAR TECHNOLOGIES, INC. BE LIABLE FOR ANY +// INCIDENTAL, PUNITIVE, OR CONSEQUENTIAL DAMAGES OF ANY KIND WHATSOEVER +// ARISING FROM THE USE OF THIS SOURCE CODE. +// +// THIS DISCLAIMER OF WARRANTY EXTENDS TO THE USER OF THIS SOURCE CODE +// AND USER'S CUSTOMERS, EMPLOYEES, AGENTS, TRANSFEREES, SUCCESSORS, +// AND ASSIGNS. +// +// THIS IS NOT A GRANT OF PATENT RIGHTS +//------------------------------------------------------------------------------ +// +// Original License: +// public domain sha256 implementation based on fips180-3 +// +//------------------------------------------------------------------------------ +#include +#include +#include + +#include "sha256.h" + +//------------------------------------------------------------------------------ +// sha256 constant array +//------------------------------------------------------------------------------ +static const uint32_t K[64] = { + 0x428a2f98, 0x71374491, 0xb5c0fbcf, 0xe9b5dba5, 0x3956c25b, 0x59f111f1, 0x923f82a4, 0xab1c5ed5, + 0xd807aa98, 0x12835b01, 0x243185be, 0x550c7dc3, 0x72be5d74, 0x80deb1fe, 0x9bdc06a7, 0xc19bf174, + 0xe49b69c1, 0xefbe4786, 0x0fc19dc6, 0x240ca1cc, 0x2de92c6f, 0x4a7484aa, 0x5cb0a9dc, 0x76f988da, + 0x983e5152, 0xa831c66d, 0xb00327c8, 0xbf597fc7, 0xc6e00bf3, 0xd5a79147, 0x06ca6351, 0x14292967, + 0x27b70a85, 0x2e1b2138, 0x4d2c6dfc, 0x53380d13, 0x650a7354, 0x766a0abb, 0x81c2c92e, 0x92722c85, + 0xa2bfe8a1, 0xa81a664b, 0xc24b8b70, 0xc76c51a3, 0xd192e819, 0xd6990624, 0xf40e3585, 0x106aa070, + 0x19a4c116, 0x1e376c08, 0x2748774c, 0x34b0bcb5, 0x391c0cb3, 0x4ed8aa4a, 0x5b9cca4f, 0x682e6ff3, + 0x748f82ee, 0x78a5636f, 0x84c87814, 0x8cc70208, 0x90befffa, 0xa4506ceb, 0xbef9a3f7, 0xc67178f2 +}; + +//------------------------------------------------------------------------------ +// These work together to produce the S0, S1, R0, R1 functions +//------------------------------------------------------------------------------ +static inline uint32_t ror(uint32_t n_val, int k_val) +{ + return (n_val >> k_val) | (n_val << (32 - k_val)); +} +#define Ch(x, y, z) (z ^ (x & (y ^ z))) +#define Maj(x, y, z) ((x & y) | (z & (x | y))) +#define S0(x) (ror(x, 2) ^ ror(x, 13) ^ ror(x, 22)) +#define S1(x) (ror(x, 6) ^ ror(x, 11) ^ ror(x, 25)) +#define R0(x) (ror(x, 7) ^ ror(x, 18) ^ (x >> 3)) +#define R1(x) (ror(x, 17) ^ ror(x, 19) ^ (x >> 10)) + +//------------------------------------------------------------------------------ +// Function: block_process +// Process a block into the sha256 algorithm +// +// Parameters: +// s - sha256 context +// buf - buffer to process +// +// Returns: +// none +//------------------------------------------------------------------------------ +static void block_process(sha256_t *s, const uint8_t *buf) +{ + uint32_t W[64], t1, t2, a_val, b_val, c_val, d_val, e, f, g, h; + int i; + + for (i = 0; i < 16; i++) { + W[i] = (uint32_t)buf[4 * i] << 24; + W[i] |= (uint32_t)buf[4 * i + 1] << 16; + W[i] |= (uint32_t)buf[4 * i + 2] << 8; + W[i] |= buf[4 * i + 3]; + } + for (; i < 64; i++) + W[i] = R1(W[i - 2]) + W[i - 7] + R0(W[i - 15]) + W[i - 16]; + a_val = s->h[0]; + b_val = s->h[1]; + c_val = s->h[2]; + d_val = s->h[3]; + e = s->h[4]; + f = s->h[5]; + g = s->h[6]; + h = s->h[7]; + for (i = 0; i < 64; i++) { + t1 = h + S1(e) + Ch(e, f, g) + K[i] + W[i]; + t2 = S0(a_val) + Maj(a_val, b_val, c_val); + h = g; + g = f; + f = e; + e = d_val + t1; + d_val = c_val; + c_val = b_val; + b_val = a_val; + a_val = t1 + t2; + } + s->h[0] += a_val; + s->h[1] += b_val; + s->h[2] += c_val; + s->h[3] += d_val; + s->h[4] += e; + s->h[5] += f; + s->h[6] += g; + s->h[7] += h; +} + +//------------------------------------------------------------------------------ +// Function: block_pad +// Pad block before executing sha256 algorithm +// +// Parameters: +// s - sha256 context +// +// Returns: +// none +// LDRA: 87 S - Use of pointer arithmetic +//------------------------------------------------------------------------------ +static void block_pad(sha256_t *s) +{ + unsigned r = s->len % 64; + + s->buf[r++] = 0x80; + if (r > 56) { + /*LDRA_INSPECTED 87 S */ + memset(s->buf + r, 0, 64 - r); + r = 0; + block_process(s, s->buf); + } + /*LDRA_INSPECTED 87 S */ + memset(s->buf + r, 0, 56 - r); + s->len *= 8; + s->buf[56] = s->len >> 56; + s->buf[57] = s->len >> 48; + s->buf[58] = s->len >> 40; + s->buf[59] = s->len >> 32; + s->buf[60] = s->len >> 24; + s->buf[61] = s->len >> 16; + s->buf[62] = s->len >> 8; + s->buf[63] = s->len; + block_process(s, s->buf); +} + +//------------------------------------------------------------------------------ +// Function: sha256_init +// Initialize sha256 context +// +// Parameters: +// ctx - sha256 context +// +// Returns: +// none +//------------------------------------------------------------------------------ +void sha256_init(sha256_t *ctx) +{ + ctx->len = 0; + ctx->h[0] = 0x6a09e667; + ctx->h[1] = 0xbb67ae85; + ctx->h[2] = 0x3c6ef372; + ctx->h[3] = 0xa54ff53a; + ctx->h[4] = 0x510e527f; + ctx->h[5] = 0x9b05688c; + ctx->h[6] = 0x1f83d9ab; + ctx->h[7] = 0x5be0cd19; +} + +//------------------------------------------------------------------------------ +// Function: sha256_sum +// Calculate the sha256 over the block in the ctx +// +// Parameters: +// ctx - sha256 context +// md - output digetst +// +// Returns: +// none +//------------------------------------------------------------------------------ +void sha256_sum(sha256_t *ctx, uint8_t md[SHA256_DIGEST_LENGTH]) +{ + int i; + + block_pad(ctx); + for (i = 0; i < 8; i++) { + md[4 * i] = ctx->h[i] >> 24; + md[4 * i + 1] = ctx->h[i] >> 16; + md[4 * i + 2] = ctx->h[i] >> 8; + md[4 * i + 3] = ctx->h[i]; + } +} + +//------------------------------------------------------------------------------ +// Function: sha256_update +// Update the sha256 over the block m (length len) +// +// Parameters: +// ctx - sha256 context +// m - block pointer +// len - block length +// +// Returns: +// none +// LDRA: 87 S - Use of pointer arithmetic +// LDRA: 53 S - Use of comma operator +//------------------------------------------------------------------------------ +void sha256_update(sha256_t *ctx, const void *m, uint32_t len_val) +{ + uint32_t len = len_val; // temporary value to prevent 14 D Attempt to change parameter passed by value + + const uint8_t *p = m; + unsigned r = ctx->len % 64; + + ctx->len += len; + if (r) { + if (len < 64 - r) { + /*LDRA_INSPECTED 87 S */ + memcpy(ctx->buf + r, p, len); + return; + } + /*LDRA_INSPECTED 87 S */ + memcpy(ctx->buf + r, p, 64 - r); + len -= 64 - r; + p += 64 - r; + block_process(ctx, ctx->buf); + } + + /*LDRA_INSPECTED 53 S */ + for (; len >= 64; len -= 64, p += 64) + block_process(ctx, p); + memcpy(ctx->buf, p, len); +} diff --git a/bsp/drivers/drm/panel/Kconfig b/bsp/drivers/drm/panel/Kconfig index 3b5d47c70b..5d89bd64ce 100644 --- a/bsp/drivers/drm/panel/Kconfig +++ b/bsp/drivers/drm/panel/Kconfig @@ -1,32 +1,41 @@ # SPDX-License-Identifier: GPL-2.0-or-later -menuconfig AW_DRM_PANEL - tristate "Support panel based on DRM framework" - depends on AW_DRM +config PANEL_DSI_GENERAL + tristate "dsi general panel" + depends on (AW_DRM) + select VIDEOMODE_HELPERS + select BACKLIGHT_CLASS_DEVICE + select BACKLIGHT_PWM default n help - If you want use DRM panel, select it. + If you want to support general dsi panel, select it. -config PANEL_SQ101D_Q5DI404_84H501H - bool "SQ101D_Q5DI404_84H501H panel" - depends on (AW_DRM_PANEL) +config PANEL_LVDS_GENERAL + tristate "lvds general panel" + depends on (AW_DRM) select VIDEOMODE_HELPERS + select BACKLIGHT_CLASS_DEVICE + select BACKLIGHT_PWM default n help - If you want to support PANEL_SQ101D_Q5DI404_84H501H panel, select it. + If you want to support general lvds panel, select it. -config PANEL_BP101WX1 - bool "BP101WX1 LVDS panel" - depends on (AW_DRM_PANEL) +config PANEL_RGB_GENERAL + tristate "rgb general panel" + depends on (AW_DRM) select VIDEOMODE_HELPERS + select BACKLIGHT_CLASS_DEVICE + select BACKLIGHT_PWM default n help - If you want to support PANEL_BP101WX1 panel, select it. + If you want to support general rgb panel, select it. config PANEL_EDP_GENERAL tristate "eDP general drm panel" - depends on (AW_DRM_PANEL) + depends on (AW_DRM) select VIDEOMODE_HELPERS + select BACKLIGHT_CLASS_DEVICE + select BACKLIGHT_PWM default n help If you want to support general edp panel, select it. diff --git a/bsp/drivers/drm/panel/Makefile b/bsp/drivers/drm/panel/Makefile index df6e680abf..e7df02245d 100644 --- a/bsp/drivers/drm/panel/Makefile +++ b/bsp/drivers/drm/panel/Makefile @@ -8,10 +8,7 @@ ccflags-y += -I$(mkfile_dir)/../sunxi_device/hardware ccflags-y += -I$(mkfile_dir)/../sunxi_device/hardware/lowlevel_v35x/tcon ccflags-y += -I$(mkfile_dir)/../sunxi_device/hardware/lowlevel_v35x/ - - -obj-$(CONFIG_AW_DRM_PANEL) += sunxi_drm_panel.o -#sunxi_drm_panel-y += panels.o -sunxi_drm_panel-$(CONFIG_PANEL_SQ101D_Q5DI404_84H501H) += SQ101D_Q5DI404_84H501H.o -sunxi_drm_panel-$(CONFIG_PANEL_BP101WX1) += panel-bp101wx1.o -sunxi_drm_panel-$(CONFIG_PANEL_EDP_GENERAL) += edp_general_panel.o +obj-$(CONFIG_PANEL_EDP_GENERAL) += edp_general_panel.o +obj-$(CONFIG_PANEL_DSI_GENERAL) += dsi-panel-simple.o +obj-$(CONFIG_PANEL_LVDS_GENERAL) += panel-lvds.o +obj-$(CONFIG_PANEL_RGB_GENERAL) += panel-rgb.o diff --git a/bsp/drivers/drm/panel/dsi-panel-simple.c b/bsp/drivers/drm/panel/dsi-panel-simple.c new file mode 100644 index 0000000000..695e753d73 --- /dev/null +++ b/bsp/drivers/drm/panel/dsi-panel-simple.c @@ -0,0 +1,658 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Generic dsi panel driver + * + * Copyright (C) 2023 Allwinner. + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include