From 9bf2beee0b91ca728d3e2662849fbf0779edea32 Mon Sep 17 00:00:00 2001 From: Austin Seipp Date: Wed, 25 Mar 2020 08:46:39 -0500 Subject: [PATCH] fix(comp): use Verilog-2001 'always @*' combinational blocks Signed-off-by: Austin Seipp --- src/comp/Verilog.hs | 14 +++++++++++--- 1 file changed, 11 insertions(+), 3 deletions(-) diff --git a/src/comp/Verilog.hs b/src/comp/Verilog.hs index af0cc219..f48c65e4 100644 --- a/src/comp/Verilog.hs +++ b/src/comp/Verilog.hs @@ -425,9 +425,11 @@ data VStmt instance PPrint VStmt where - pPrint d p (VAt e s) = sep [text "@" <> pparen True (pPrint d 0 e), pPrint d 0 s] - pPrint d p (Valways (VAt e s)) = sep [text "always@" <> pparen True (pPrint d 0 e), pPrint d 0 s] - pPrint d p (Valways s) = sep [text "always", pPrint d 0 s] + pPrint d p (VAt e s) + | isEventCombinational e = sep [text "@*", pPrint d 0 s] + | otherwise = sep [text "@" <> pparen True (pPrint d 0 e), pPrint d 0 s] + + pPrint d p (Valways s) = text "always" <+> pPrint d 0 s pPrint d p (Vinitial s) = -- NB: see https://github.com/B-Lang-org/bsc/issues/118 TL;DR -- yosys hates synopsys pragmas, so gate them *behind* the @@ -670,6 +672,12 @@ instance PPrint VEventExpr where pPrint d p (VEE e) = pPrint d p e pPrint d p (VEEMacro s e) = text ("`" ++ s) <+> pPrint d (p+1) e +isEventCombinational :: VEventExpr -> Bool +isEventCombinational (VEEposedge _) = False +isEventCombinational (VEEnegedge _) = False +isEventCombinational (VEEMacro _ _) = False +isEventCombinational (VEE _) = True +isEventCombinational (VEEOr l r) = isEventCombinational l && isEventCombinational r data VExpr = VEConst Integer