MinorCPU_stats.txt

---------- Begin Simulation Statistics ----------
final_tick                                   84846000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
host_inst_rate                                 110921                       # Simulator instruction rate (inst/s)
host_mem_usage                                 665712                       # Number of bytes of host memory used
host_op_rate                                   128995                       # Simulator op (including micro ops) rate (op/s)
host_seconds                                     0.48                       # Real time elapsed on the host
host_tick_rate                              177764047                       # Simulator tick rate (ticks/s)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
sim_insts                                       52910                       # Number of instructions simulated
sim_ops                                         61563                       # Number of ops (including micro ops) simulated
sim_seconds                                  0.000085                       # Number of seconds simulated
sim_ticks                                    84846000                       # Number of ticks simulated
system.cpu.committedInsts                       52910                       # Number of instructions committed
system.cpu.committedOps                         61563                       # Number of ops (including micro ops) committed
system.cpu.cpi                               3.207182                       # CPI: cycles per instruction
system.cpu.discardedOps                          2944                       # Number of ops (including micro ops) which were discarded before commit
system.cpu.idleCycles                           94480                       # Total number of cycles that the object has spent stopped
system.cpu.ipc                               0.311800                       # IPC: instructions per cycle
system.cpu.numCycles                           169692                       # number of cpu cycles simulated
system.cpu.numFetchSuspends                         0                       # Number of times Execute suspended instruction fetching
system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
system.cpu.op_class_0::No_OpClass                   0      0.00%      0.00% # Class of committed instruction
system.cpu.op_class_0::IntAlu                   42123     68.42%     68.42% # Class of committed instruction
system.cpu.op_class_0::IntMult                    372      0.60%     69.03% # Class of committed instruction
system.cpu.op_class_0::IntDiv                       0      0.00%     69.03% # Class of committed instruction
system.cpu.op_class_0::FloatAdd                     0      0.00%     69.03% # Class of committed instruction
system.cpu.op_class_0::FloatCmp                     0      0.00%     69.03% # Class of committed instruction
system.cpu.op_class_0::FloatCvt                     0      0.00%     69.03% # Class of committed instruction
system.cpu.op_class_0::FloatMult                    0      0.00%     69.03% # Class of committed instruction
system.cpu.op_class_0::FloatMultAcc                 0      0.00%     69.03% # Class of committed instruction
system.cpu.op_class_0::FloatDiv                     0      0.00%     69.03% # Class of committed instruction
system.cpu.op_class_0::FloatMisc                    0      0.00%     69.03% # Class of committed instruction
system.cpu.op_class_0::FloatSqrt                    0      0.00%     69.03% # Class of committed instruction
system.cpu.op_class_0::SimdAdd                      0      0.00%     69.03% # Class of committed instruction
system.cpu.op_class_0::SimdAddAcc                   0      0.00%     69.03% # Class of committed instruction
system.cpu.op_class_0::SimdAlu                      0      0.00%     69.03% # Class of committed instruction
system.cpu.op_class_0::SimdCmp                      0      0.00%     69.03% # Class of committed instruction
system.cpu.op_class_0::SimdCvt                      0      0.00%     69.03% # Class of committed instruction
system.cpu.op_class_0::SimdMisc                     0      0.00%     69.03% # Class of committed instruction
system.cpu.op_class_0::SimdMult                     0      0.00%     69.03% # Class of committed instruction
system.cpu.op_class_0::SimdMultAcc                  0      0.00%     69.03% # Class of committed instruction
system.cpu.op_class_0::SimdShift                    0      0.00%     69.03% # Class of committed instruction
system.cpu.op_class_0::SimdShiftAcc                 0      0.00%     69.03% # Class of committed instruction
system.cpu.op_class_0::SimdDiv                      0      0.00%     69.03% # Class of committed instruction
system.cpu.op_class_0::SimdSqrt                     0      0.00%     69.03% # Class of committed instruction
system.cpu.op_class_0::SimdFloatAdd                 0      0.00%     69.03% # Class of committed instruction
system.cpu.op_class_0::SimdFloatAlu                 0      0.00%     69.03% # Class of committed instruction
system.cpu.op_class_0::SimdFloatCmp                36      0.06%     69.09% # Class of committed instruction
system.cpu.op_class_0::SimdFloatCvt                18      0.03%     69.11% # Class of committed instruction
system.cpu.op_class_0::SimdFloatDiv                18      0.03%     69.14% # Class of committed instruction
system.cpu.op_class_0::SimdFloatMisc              129      0.21%     69.35% # Class of committed instruction
system.cpu.op_class_0::SimdFloatMult                0      0.00%     69.35% # Class of committed instruction
system.cpu.op_class_0::SimdFloatMultAcc             0      0.00%     69.35% # Class of committed instruction
system.cpu.op_class_0::SimdFloatSqrt                0      0.00%     69.35% # Class of committed instruction
system.cpu.op_class_0::SimdReduceAdd                0      0.00%     69.35% # Class of committed instruction
system.cpu.op_class_0::SimdReduceAlu                0      0.00%     69.35% # Class of committed instruction
system.cpu.op_class_0::SimdReduceCmp                0      0.00%     69.35% # Class of committed instruction
system.cpu.op_class_0::SimdFloatReduceAdd            0      0.00%     69.35% # Class of committed instruction
system.cpu.op_class_0::SimdFloatReduceCmp            0      0.00%     69.35% # Class of committed instruction
system.cpu.op_class_0::SimdAes                      0      0.00%     69.35% # Class of committed instruction
system.cpu.op_class_0::SimdAesMix                   0      0.00%     69.35% # Class of committed instruction
system.cpu.op_class_0::SimdSha1Hash                 0      0.00%     69.35% # Class of committed instruction
system.cpu.op_class_0::SimdSha1Hash2                0      0.00%     69.35% # Class of committed instruction
system.cpu.op_class_0::SimdSha256Hash               0      0.00%     69.35% # Class of committed instruction
system.cpu.op_class_0::SimdSha256Hash2              0      0.00%     69.35% # Class of committed instruction
system.cpu.op_class_0::SimdShaSigma2                0      0.00%     69.35% # Class of committed instruction
system.cpu.op_class_0::SimdShaSigma3                0      0.00%     69.35% # Class of committed instruction
system.cpu.op_class_0::SimdPredAlu                  0      0.00%     69.35% # Class of committed instruction
system.cpu.op_class_0::MemRead                  10196     16.56%     85.92% # Class of committed instruction
system.cpu.op_class_0::MemWrite                  8671     14.08%    100.00% # Class of committed instruction
system.cpu.op_class_0::FloatMemRead                 0      0.00%    100.00% # Class of committed instruction
system.cpu.op_class_0::FloatMemWrite                0      0.00%    100.00% # Class of committed instruction
system.cpu.op_class_0::IprAccess                    0      0.00%    100.00% # Class of committed instruction
system.cpu.op_class_0::InstPrefetch                 0      0.00%    100.00% # Class of committed instruction
system.cpu.op_class_0::total                    61563                       # Class of committed instruction
system.cpu.tickCycles                           75212                       # Number of cycles that the object actually ticked
system.cpu.workload.numSyscalls                    19                       # Number of system calls
system.membus.snoop_filter.hit_multi_requests           33                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.membus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.membus.snoop_filter.hit_single_requests          732                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.membus.snoop_filter.hit_single_snoops            0                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.membus.snoop_filter.tot_requests          1997                       # Total number of requests made to the snoop filter.
system.membus.snoop_filter.tot_snoops               0                       # Total number of snoops made to the snoop filter.
system.clk_domain.clock                          1000                       # Clock period in ticks
system.cpu.branchPred.lookups                   12432                       # Number of BP lookups
system.cpu.branchPred.condPredicted              8789                       # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect               925                       # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups                 5546                       # Number of BTB lookups
system.cpu.branchPred.BTBHits                    4409                       # Number of BTB hits
system.cpu.branchPred.BTBHitPct             79.498738                       # BTB Hit Percentage
system.cpu.branchPred.RASUsed                    1116                       # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASIncorrect                  1                       # Number of incorrect RAS predictions.
system.cpu.branchPred.indirectLookups             532                       # Number of indirect predictor lookups.
system.cpu.branchPred.indirectHits                292                       # Number of indirect target hits.
system.cpu.branchPred.indirectMisses              240                       # Number of indirect misses.
system.cpu.branchPred.indirectMispredicted           95                       # Number of mispredicted indirect branches.
system.cpu.dcache.demand_hits::.cpu.data        18374                       # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total            18374                       # number of demand (read+write) hits
system.cpu.dcache.overall_hits::.cpu.data        18451                       # number of overall hits
system.cpu.dcache.overall_hits::total           18451                       # number of overall hits
system.cpu.dcache.demand_misses::.cpu.data          257                       # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total            257                       # number of demand (read+write) misses
system.cpu.dcache.overall_misses::.cpu.data          273                       # number of overall misses
system.cpu.dcache.overall_misses::total           273                       # number of overall misses
system.cpu.dcache.demand_miss_latency::.cpu.data     15875000                       # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total     15875000                       # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::.cpu.data     15875000                       # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total     15875000                       # number of overall miss cycles
system.cpu.dcache.demand_accesses::.cpu.data        18631                       # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total        18631                       # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::.cpu.data        18724                       # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total        18724                       # number of overall (read+write) accesses
system.cpu.dcache.demand_miss_rate::.cpu.data     0.013794                       # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total     0.013794                       # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::.cpu.data     0.014580                       # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total     0.014580                       # miss rate for overall accesses
system.cpu.dcache.demand_avg_miss_latency::.cpu.data 61770.428016                       # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 61770.428016                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::.cpu.data 58150.183150                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 58150.183150                       # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.dcache.demand_mshr_hits::.cpu.data           64                       # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total           64                       # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::.cpu.data           64                       # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total           64                       # number of overall MSHR hits
system.cpu.dcache.demand_mshr_misses::.cpu.data          193                       # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total          193                       # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::.cpu.data          204                       # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total          204                       # number of overall MSHR misses
system.cpu.dcache.demand_mshr_miss_latency::.cpu.data     11866500                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total     11866500                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::.cpu.data     12512500                       # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total     12512500                       # number of overall MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_rate::.cpu.data     0.010359                       # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total     0.010359                       # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::.cpu.data     0.010895                       # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total     0.010895                       # mshr miss rate for overall accesses
system.cpu.dcache.demand_avg_mshr_miss_latency::.cpu.data 61484.455959                       # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 61484.455959                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::.cpu.data 61335.784314                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 61335.784314                       # average overall mshr miss latency
system.cpu.dcache.replacements                      0                       # number of replacements
system.cpu.dcache.ReadReq_hits::.cpu.data        10391                       # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total           10391                       # number of ReadReq hits
system.cpu.dcache.ReadReq_misses::.cpu.data          128                       # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total           128                       # number of ReadReq misses
system.cpu.dcache.ReadReq_miss_latency::.cpu.data      8038000                       # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total      8038000                       # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_accesses::.cpu.data        10519                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total        10519                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_miss_rate::.cpu.data     0.012168                       # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total     0.012168                       # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_avg_miss_latency::.cpu.data 62796.875000                       # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 62796.875000                       # average ReadReq miss latency
system.cpu.dcache.ReadReq_mshr_hits::.cpu.data           11                       # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total           11                       # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::.cpu.data          117                       # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total          117                       # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::.cpu.data      7313500                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total      7313500                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::.cpu.data     0.011123                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.011123                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::.cpu.data 62508.547009                       # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 62508.547009                       # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_hits::.cpu.data         7983                       # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total           7983                       # number of WriteReq hits
system.cpu.dcache.WriteReq_misses::.cpu.data          129                       # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total          129                       # number of WriteReq misses
system.cpu.dcache.WriteReq_miss_latency::.cpu.data      7837000                       # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total      7837000                       # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_accesses::.cpu.data         8112                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total         8112                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_miss_rate::.cpu.data     0.015902                       # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total     0.015902                       # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_avg_miss_latency::.cpu.data 60751.937984                       # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 60751.937984                       # average WriteReq miss latency
system.cpu.dcache.WriteReq_mshr_hits::.cpu.data           53                       # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total           53                       # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_misses::.cpu.data           76                       # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total           76                       # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_miss_latency::.cpu.data      4553000                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total      4553000                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_rate::.cpu.data     0.009369                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.009369                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::.cpu.data 59907.894737                       # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 59907.894737                       # average WriteReq mshr miss latency
system.cpu.dcache.SoftPFReq_hits::.cpu.data           77                       # number of SoftPFReq hits
system.cpu.dcache.SoftPFReq_hits::total            77                       # number of SoftPFReq hits
system.cpu.dcache.SoftPFReq_misses::.cpu.data           16                       # number of SoftPFReq misses
system.cpu.dcache.SoftPFReq_misses::total           16                       # number of SoftPFReq misses
system.cpu.dcache.SoftPFReq_accesses::.cpu.data           93                       # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::total           93                       # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_miss_rate::.cpu.data     0.172043                       # miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::total     0.172043                       # miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_mshr_misses::.cpu.data           11                       # number of SoftPFReq MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::total           11                       # number of SoftPFReq MSHR misses
system.cpu.dcache.SoftPFReq_mshr_miss_latency::.cpu.data       646000                       # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::total       646000                       # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_rate::.cpu.data     0.118280                       # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.118280                       # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::.cpu.data 58727.272727                       # average SoftPFReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 58727.272727                       # average SoftPFReq mshr miss latency
system.cpu.dcache.LoadLockedReq_hits::.cpu.data          106                       # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total          106                       # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_accesses::.cpu.data          106                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total          106                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_hits::.cpu.data          106                       # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total          106                       # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_accesses::.cpu.data          106                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total          106                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.power_state.pwrStateResidencyTicks::UNDEFINED     84846000                       # Cumulative time (in ticks) in various power states
system.cpu.dcache.tags.tagsinuse           154.779908                       # Cycle average of tags in use
system.cpu.dcache.tags.total_refs               18867                       # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs               204                       # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs             92.485294                       # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle            145000                       # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::.cpu.data   154.779908                       # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::.cpu.data     0.151152                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total     0.151152                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024          204                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0           12                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1          192                       # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024     0.199219                       # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses             38076                       # Number of tag accesses
system.cpu.dcache.tags.data_accesses            38076                       # Number of data accesses
system.cpu.dcache.tags.power_state.pwrStateResidencyTicks::UNDEFINED     84846000                       # Cumulative time (in ticks) in various power states
system.cpu.dtb.instHits                             0                       # ITB inst hits
system.cpu.dtb.instMisses                           0                       # ITB inst misses
system.cpu.dtb.readHits                             0                       # DTB read hits
system.cpu.dtb.readMisses                           0                       # DTB read misses
system.cpu.dtb.writeHits                            0                       # DTB write hits
system.cpu.dtb.writeMisses                          0                       # DTB write misses
system.cpu.dtb.inserts                              0                       # Number of times an entry is inserted into the TLB
system.cpu.dtb.flushTlb                             0                       # Number of times complete TLB was flushed
system.cpu.dtb.flushTlbMva                          0                       # Number of times TLB was flushed by MVA
system.cpu.dtb.flushTlbMvaAsid                      0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flushTlbAsid                         0                       # Number of times TLB was flushed by ASID
system.cpu.dtb.flushedEntries                       0                       # Number of entries that have been flushed from TLB
system.cpu.dtb.alignFaults                          0                       # Number of TLB faults due to alignment restrictions
system.cpu.dtb.prefetchFaults                       0                       # Number of TLB faults due to prefetch
system.cpu.dtb.domainFaults                         0                       # Number of TLB faults due to domain restrictions
system.cpu.dtb.permsFaults                          0                       # Number of TLB faults due to permissions restrictions
system.cpu.dtb.readAccesses                         0                       # DTB read accesses
system.cpu.dtb.writeAccesses                        0                       # DTB write accesses
system.cpu.dtb.instAccesses                         0                       # ITB inst accesses
system.cpu.dtb.hits                                 0                       # Total TLB (inst and data) hits
system.cpu.dtb.misses                               0                       # Total TLB (inst and data) misses
system.cpu.dtb.accesses                             0                       # Total TLB (inst and data) accesses
system.cpu.dtb.stage2_mmu.stage2_tlb.instHits            0                       # ITB inst hits
system.cpu.dtb.stage2_mmu.stage2_tlb.instMisses            0                       # ITB inst misses
system.cpu.dtb.stage2_mmu.stage2_tlb.readHits            0                       # DTB read hits
system.cpu.dtb.stage2_mmu.stage2_tlb.readMisses            0                       # DTB read misses
system.cpu.dtb.stage2_mmu.stage2_tlb.writeHits            0                       # DTB write hits
system.cpu.dtb.stage2_mmu.stage2_tlb.writeMisses            0                       # DTB write misses
system.cpu.dtb.stage2_mmu.stage2_tlb.inserts            0                       # Number of times an entry is inserted into the TLB
system.cpu.dtb.stage2_mmu.stage2_tlb.flushTlb            0                       # Number of times complete TLB was flushed
system.cpu.dtb.stage2_mmu.stage2_tlb.flushTlbMva            0                       # Number of times TLB was flushed by MVA
system.cpu.dtb.stage2_mmu.stage2_tlb.flushTlbMvaAsid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.stage2_mmu.stage2_tlb.flushTlbAsid            0                       # Number of times TLB was flushed by ASID
system.cpu.dtb.stage2_mmu.stage2_tlb.flushedEntries            0                       # Number of entries that have been flushed from TLB
system.cpu.dtb.stage2_mmu.stage2_tlb.alignFaults            0                       # Number of TLB faults due to alignment restrictions
system.cpu.dtb.stage2_mmu.stage2_tlb.prefetchFaults            0                       # Number of TLB faults due to prefetch
system.cpu.dtb.stage2_mmu.stage2_tlb.domainFaults            0                       # Number of TLB faults due to domain restrictions
system.cpu.dtb.stage2_mmu.stage2_tlb.permsFaults            0                       # Number of TLB faults due to permissions restrictions
system.cpu.dtb.stage2_mmu.stage2_tlb.readAccesses            0                       # DTB read accesses
system.cpu.dtb.stage2_mmu.stage2_tlb.writeAccesses            0                       # DTB write accesses
system.cpu.dtb.stage2_mmu.stage2_tlb.instAccesses            0                       # ITB inst accesses
system.cpu.dtb.stage2_mmu.stage2_tlb.hits            0                       # Total TLB (inst and data) hits
system.cpu.dtb.stage2_mmu.stage2_tlb.misses            0                       # Total TLB (inst and data) misses
system.cpu.dtb.stage2_mmu.stage2_tlb.accesses            0                       # Total TLB (inst and data) accesses
system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu.dtb.stage2_mmu.stage2_tlb.walker.requestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.stage2_mmu.stage2_tlb.walker.requestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.stage2_mmu.stage2_tlb.walker.requestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.stage2_mmu.stage2_tlb.walker.requestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.stage2_mmu.stage2_tlb.walker.requestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.stage2_mmu.stage2_tlb.walker.requestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.stage2_mmu.stage2_tlb.walker.requestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.stage2_mmu.stage2_tlb.walker.power_state.pwrStateResidencyTicks::UNDEFINED     84846000                       # Cumulative time (in ticks) in various power states
system.cpu.dtb.walker.walks                         0                       # Table walker walks requested
system.cpu.dtb.walker.requestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.requestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.requestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.requestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.requestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.requestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.requestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.power_state.pwrStateResidencyTicks::UNDEFINED     84846000                       # Cumulative time (in ticks) in various power states
system.cpu.fetch2.intInstructions               35253                       # Number of integer instructions successfully decoded
system.cpu.fetch2.fpInstructions                    0                       # Number of floating point instructions successfully decoded
system.cpu.fetch2.vecInstructions                   0                       # Number of SIMD instructions successfully decoded
system.cpu.fetch2.loadInstructions               8811                       # Number of memory load instructions successfully decoded
system.cpu.fetch2.storeInstructions              4497                       # Number of memory store instructions successfully decoded
system.cpu.fetch2.amoInstructions                   0                       # Number of memory atomic instructions successfully decoded
system.cpu.icache.demand_hits::.cpu.inst        17067                       # number of demand (read+write) hits
system.cpu.icache.demand_hits::total            17067                       # number of demand (read+write) hits
system.cpu.icache.overall_hits::.cpu.inst        17067                       # number of overall hits
system.cpu.icache.overall_hits::total           17067                       # number of overall hits
system.cpu.icache.demand_misses::.cpu.inst         1084                       # number of demand (read+write) misses
system.cpu.icache.demand_misses::total           1084                       # number of demand (read+write) misses
system.cpu.icache.overall_misses::.cpu.inst         1084                       # number of overall misses
system.cpu.icache.overall_misses::total          1084                       # number of overall misses
system.cpu.icache.demand_miss_latency::.cpu.inst     47889500                       # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total     47889500                       # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::.cpu.inst     47889500                       # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total     47889500                       # number of overall miss cycles
system.cpu.icache.demand_accesses::.cpu.inst        18151                       # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total        18151                       # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::.cpu.inst        18151                       # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total        18151                       # number of overall (read+write) accesses
system.cpu.icache.demand_miss_rate::.cpu.inst     0.059721                       # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total     0.059721                       # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::.cpu.inst     0.059721                       # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total     0.059721                       # miss rate for overall accesses
system.cpu.icache.demand_avg_miss_latency::.cpu.inst 44178.505535                       # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 44178.505535                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::.cpu.inst 44178.505535                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 44178.505535                       # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.icache.writebacks::.writebacks          709                       # number of writebacks
system.cpu.icache.writebacks::total               709                       # number of writebacks
system.cpu.icache.demand_mshr_misses::.cpu.inst         1084                       # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total         1084                       # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::.cpu.inst         1084                       # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total         1084                       # number of overall MSHR misses
system.cpu.icache.demand_mshr_miss_latency::.cpu.inst     46805500                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total     46805500                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::.cpu.inst     46805500                       # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total     46805500                       # number of overall MSHR miss cycles
system.cpu.icache.demand_mshr_miss_rate::.cpu.inst     0.059721                       # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total     0.059721                       # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::.cpu.inst     0.059721                       # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total     0.059721                       # mshr miss rate for overall accesses
system.cpu.icache.demand_avg_mshr_miss_latency::.cpu.inst 43178.505535                       # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 43178.505535                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::.cpu.inst 43178.505535                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 43178.505535                       # average overall mshr miss latency
system.cpu.icache.replacements                    709                       # number of replacements
system.cpu.icache.ReadReq_hits::.cpu.inst        17067                       # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total           17067                       # number of ReadReq hits
system.cpu.icache.ReadReq_misses::.cpu.inst         1084                       # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total          1084                       # number of ReadReq misses
system.cpu.icache.ReadReq_miss_latency::.cpu.inst     47889500                       # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total     47889500                       # number of ReadReq miss cycles
system.cpu.icache.ReadReq_accesses::.cpu.inst        18151                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total        18151                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_miss_rate::.cpu.inst     0.059721                       # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total     0.059721                       # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_avg_miss_latency::.cpu.inst 44178.505535                       # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 44178.505535                       # average ReadReq miss latency
system.cpu.icache.ReadReq_mshr_misses::.cpu.inst         1084                       # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total         1084                       # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::.cpu.inst     46805500                       # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total     46805500                       # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::.cpu.inst     0.059721                       # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total     0.059721                       # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::.cpu.inst 43178.505535                       # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 43178.505535                       # average ReadReq mshr miss latency
system.cpu.icache.power_state.pwrStateResidencyTicks::UNDEFINED     84846000                       # Cumulative time (in ticks) in various power states
system.cpu.icache.tags.tagsinuse           285.872299                       # Cycle average of tags in use
system.cpu.icache.tags.total_refs               18151                       # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs              1084                       # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs             16.744465                       # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle             77000                       # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::.cpu.inst   285.872299                       # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::.cpu.inst     0.558344                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total     0.558344                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024          375                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0           74                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1          301                       # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024     0.732422                       # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses             37386                       # Number of tag accesses
system.cpu.icache.tags.data_accesses            37386                       # Number of data accesses
system.cpu.icache.tags.power_state.pwrStateResidencyTicks::UNDEFINED     84846000                       # Cumulative time (in ticks) in various power states
system.cpu.itb.instHits                             0                       # ITB inst hits
system.cpu.itb.instMisses                           0                       # ITB inst misses
system.cpu.itb.readHits                             0                       # DTB read hits
system.cpu.itb.readMisses                           0                       # DTB read misses
system.cpu.itb.writeHits                            0                       # DTB write hits
system.cpu.itb.writeMisses                          0                       # DTB write misses
system.cpu.itb.inserts                              0                       # Number of times an entry is inserted into the TLB
system.cpu.itb.flushTlb                             0                       # Number of times complete TLB was flushed
system.cpu.itb.flushTlbMva                          0                       # Number of times TLB was flushed by MVA
system.cpu.itb.flushTlbMvaAsid                      0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flushTlbAsid                         0                       # Number of times TLB was flushed by ASID
system.cpu.itb.flushedEntries                       0                       # Number of entries that have been flushed from TLB
system.cpu.itb.alignFaults                          0                       # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetchFaults                       0                       # Number of TLB faults due to prefetch
system.cpu.itb.domainFaults                         0                       # Number of TLB faults due to domain restrictions
system.cpu.itb.permsFaults                          0                       # Number of TLB faults due to permissions restrictions
system.cpu.itb.readAccesses                         0                       # DTB read accesses
system.cpu.itb.writeAccesses                        0                       # DTB write accesses
system.cpu.itb.instAccesses                         0                       # ITB inst accesses
system.cpu.itb.hits                                 0                       # Total TLB (inst and data) hits
system.cpu.itb.misses                               0                       # Total TLB (inst and data) misses
system.cpu.itb.accesses                             0                       # Total TLB (inst and data) accesses
system.cpu.itb.stage2_mmu.stage2_tlb.instHits            0                       # ITB inst hits
system.cpu.itb.stage2_mmu.stage2_tlb.instMisses            0                       # ITB inst misses
system.cpu.itb.stage2_mmu.stage2_tlb.readHits            0                       # DTB read hits
system.cpu.itb.stage2_mmu.stage2_tlb.readMisses            0                       # DTB read misses
system.cpu.itb.stage2_mmu.stage2_tlb.writeHits            0                       # DTB write hits
system.cpu.itb.stage2_mmu.stage2_tlb.writeMisses            0                       # DTB write misses
system.cpu.itb.stage2_mmu.stage2_tlb.inserts            0                       # Number of times an entry is inserted into the TLB
system.cpu.itb.stage2_mmu.stage2_tlb.flushTlb            0                       # Number of times complete TLB was flushed
system.cpu.itb.stage2_mmu.stage2_tlb.flushTlbMva            0                       # Number of times TLB was flushed by MVA
system.cpu.itb.stage2_mmu.stage2_tlb.flushTlbMvaAsid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.stage2_mmu.stage2_tlb.flushTlbAsid            0                       # Number of times TLB was flushed by ASID
system.cpu.itb.stage2_mmu.stage2_tlb.flushedEntries            0                       # Number of entries that have been flushed from TLB
system.cpu.itb.stage2_mmu.stage2_tlb.alignFaults            0                       # Number of TLB faults due to alignment restrictions
system.cpu.itb.stage2_mmu.stage2_tlb.prefetchFaults            0                       # Number of TLB faults due to prefetch
system.cpu.itb.stage2_mmu.stage2_tlb.domainFaults            0                       # Number of TLB faults due to domain restrictions
system.cpu.itb.stage2_mmu.stage2_tlb.permsFaults            0                       # Number of TLB faults due to permissions restrictions
system.cpu.itb.stage2_mmu.stage2_tlb.readAccesses            0                       # DTB read accesses
system.cpu.itb.stage2_mmu.stage2_tlb.writeAccesses            0                       # DTB write accesses
system.cpu.itb.stage2_mmu.stage2_tlb.instAccesses            0                       # ITB inst accesses
system.cpu.itb.stage2_mmu.stage2_tlb.hits            0                       # Total TLB (inst and data) hits
system.cpu.itb.stage2_mmu.stage2_tlb.misses            0                       # Total TLB (inst and data) misses
system.cpu.itb.stage2_mmu.stage2_tlb.accesses            0                       # Total TLB (inst and data) accesses
system.cpu.itb.stage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu.itb.stage2_mmu.stage2_tlb.walker.requestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.stage2_mmu.stage2_tlb.walker.requestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.stage2_mmu.stage2_tlb.walker.requestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.stage2_mmu.stage2_tlb.walker.requestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.stage2_mmu.stage2_tlb.walker.requestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.stage2_mmu.stage2_tlb.walker.requestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.stage2_mmu.stage2_tlb.walker.requestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.stage2_mmu.stage2_tlb.walker.power_state.pwrStateResidencyTicks::UNDEFINED     84846000                       # Cumulative time (in ticks) in various power states
system.cpu.itb.walker.walks                         0                       # Table walker walks requested
system.cpu.itb.walker.requestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.requestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.requestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.requestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.requestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.requestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.requestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.power_state.pwrStateResidencyTicks::UNDEFINED     84846000                       # Cumulative time (in ticks) in various power states
system.cpu.power_state.pwrStateResidencyTicks::ON     84846000                       # Cumulative time (in ticks) in various power states
system.cpu.thread_0.numInsts                    52910                       # Number of Instructions committed
system.cpu.thread_0.numOps                      61563                       # Number of Ops committed
system.cpu.thread_0.numMemRefs                      0                       # Number of Memory References
system.cpu_clk_domain.clock                       500                       # Clock period in ticks
system.cpu_voltage_domain.voltage                   1                       # Voltage in Volts
system.mem_ctrls.avgPriority_.writebacks::samples       390.00                       # Average QoS priority value for accepted requests
system.mem_ctrls.avgPriority_.cpu.inst::samples       628.00                       # Average QoS priority value for accepted requests
system.mem_ctrls.avgPriority_.cpu.data::samples       203.00                       # Average QoS priority value for accepted requests
system.mem_ctrls.priorityMinLatency      0.000000018750                       # per QoS priority minimum request to response latency (s)
system.mem_ctrls.priorityMaxLatency      0.000068647750                       # per QoS priority maximum request to response latency (s)
system.mem_ctrls.numReadWriteTurnArounds           21                       # Number of turnarounds from READ to WRITE
system.mem_ctrls.numWriteReadTurnArounds           21                       # Number of turnarounds from WRITE to READ
system.mem_ctrls.numStayReadState                2325                       # Number of times bus staying in READ state
system.mem_ctrls.numStayWriteState                338                       # Number of times bus staying in WRITE state
system.mem_ctrls.readReqs                        1288                       # Number of read requests accepted
system.mem_ctrls.writeReqs                        676                       # Number of write requests accepted
system.mem_ctrls.readBursts                      1288                       # Number of controller read bursts, including those serviced by the write queue
system.mem_ctrls.writeBursts                      676                       # Number of controller write bursts, including those merged in the write queue
system.mem_ctrls.servicedByWrQ                    457                       # Number of controller read bursts serviced by the write queue
system.mem_ctrls.mergedWrBursts                   286                       # Number of controller write bursts merged with an existing one
system.mem_ctrls.neitherReadNorWriteReqs            0                       # Number of requests that are neither read nor write
system.mem_ctrls.avgRdQLen                       1.08                       # Average read queue length when enqueuing
system.mem_ctrls.avgWrQLen                      20.11                       # Average write queue length when enqueuing
system.mem_ctrls.numRdRetry                         0                       # Number of times read queue was full causing retry
system.mem_ctrls.numWrRetry                         0                       # Number of times write queue was full causing retry
system.mem_ctrls.readPktSize::0                     0                       # Read request sizes (log2)
system.mem_ctrls.readPktSize::1                     0                       # Read request sizes (log2)
system.mem_ctrls.readPktSize::2                     0                       # Read request sizes (log2)
system.mem_ctrls.readPktSize::3                     0                       # Read request sizes (log2)
system.mem_ctrls.readPktSize::4                     0                       # Read request sizes (log2)
system.mem_ctrls.readPktSize::5                     0                       # Read request sizes (log2)
system.mem_ctrls.readPktSize::6                  1288                       # Read request sizes (log2)
system.mem_ctrls.writePktSize::0                    0                       # Write request sizes (log2)
system.mem_ctrls.writePktSize::1                    0                       # Write request sizes (log2)
system.mem_ctrls.writePktSize::2                    0                       # Write request sizes (log2)
system.mem_ctrls.writePktSize::3                    0                       # Write request sizes (log2)
system.mem_ctrls.writePktSize::4                    0                       # Write request sizes (log2)
system.mem_ctrls.writePktSize::5                    0                       # Write request sizes (log2)
system.mem_ctrls.writePktSize::6                  676                       # Write request sizes (log2)
system.mem_ctrls.rdQLenPdf::0                     722                       # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::1                     104                       # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::2                       5                       # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::3                       0                       # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::4                       0                       # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::5                       0                       # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::6                       0                       # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::7                       0                       # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::8                       0                       # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::9                       0                       # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::10                      0                       # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::11                      0                       # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::12                      0                       # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::13                      0                       # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::14                      0                       # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::15                      0                       # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::16                      0                       # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::17                      0                       # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::18                      0                       # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::19                      0                       # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::20                      0                       # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::21                      0                       # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::22                      0                       # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::23                      0                       # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::24                      0                       # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::25                      0                       # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::26                      0                       # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::27                      0                       # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::28                      0                       # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::29                      0                       # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::30                      0                       # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::31                      0                       # What read queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::0                       1                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::1                       1                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::2                       1                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::3                       1                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::4                       1                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::5                       1                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::6                       1                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::7                       1                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::8                       1                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::9                       1                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::10                      1                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::11                      1                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::12                      1                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::13                      1                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::14                      1                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::15                      8                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::16                      9                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::17                     19                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::18                     23                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::19                     22                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::20                     24                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::21                     22                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::22                     27                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::23                     22                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::24                     22                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::25                     23                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::26                     22                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::27                     22                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::28                     22                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::29                     22                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::30                     22                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::31                     21                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::32                     21                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::33                      1                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::34                      1                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::35                      0                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::36                      0                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::37                      0                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::38                      0                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::39                      0                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::40                      0                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::41                      0                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::42                      0                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::43                      0                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::44                      0                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::45                      0                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::46                      0                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::47                      0                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::48                      0                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::49                      0                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::50                      0                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::51                      0                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::52                      0                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::53                      0                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::54                      0                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::55                      0                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::56                      0                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::57                      0                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::58                      0                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::59                      0                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::60                      0                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::61                      0                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::62                      0                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::63                      0                       # What write queue length does an incoming req see
system.mem_ctrls.rdPerTurnAround::samples           21                       # Reads before turning the bus around for writes
system.mem_ctrls.rdPerTurnAround::mean      37.952381                       # Reads before turning the bus around for writes
system.mem_ctrls.rdPerTurnAround::gmean     15.074120                       # Reads before turning the bus around for writes
system.mem_ctrls.rdPerTurnAround::stdev     92.282976                       # Reads before turning the bus around for writes
system.mem_ctrls.rdPerTurnAround::0-15             15     71.43%     71.43% # Reads before turning the bus around for writes
system.mem_ctrls.rdPerTurnAround::16-31             2      9.52%     80.95% # Reads before turning the bus around for writes
system.mem_ctrls.rdPerTurnAround::48-63             2      9.52%     90.48% # Reads before turning the bus around for writes
system.mem_ctrls.rdPerTurnAround::64-79             1      4.76%     95.24% # Reads before turning the bus around for writes
system.mem_ctrls.rdPerTurnAround::432-447            1      4.76%    100.00% # Reads before turning the bus around for writes
system.mem_ctrls.rdPerTurnAround::total            21                       # Reads before turning the bus around for writes
system.mem_ctrls.wrPerTurnAround::samples           21                       # Writes before turning the bus around for reads
system.mem_ctrls.wrPerTurnAround::mean      17.095238                       # Writes before turning the bus around for reads
system.mem_ctrls.wrPerTurnAround::gmean     17.029334                       # Writes before turning the bus around for reads
system.mem_ctrls.wrPerTurnAround::stdev      1.578124                       # Writes before turning the bus around for reads
system.mem_ctrls.wrPerTurnAround::16               13     61.90%     61.90% # Writes before turning the bus around for reads
system.mem_ctrls.wrPerTurnAround::17                1      4.76%     66.67% # Writes before turning the bus around for reads
system.mem_ctrls.wrPerTurnAround::18                2      9.52%     76.19% # Writes before turning the bus around for reads
system.mem_ctrls.wrPerTurnAround::19                2      9.52%     85.71% # Writes before turning the bus around for reads
system.mem_ctrls.wrPerTurnAround::20                3     14.29%    100.00% # Writes before turning the bus around for reads
system.mem_ctrls.wrPerTurnAround::total            21                       # Writes before turning the bus around for reads
system.mem_ctrls.bytesReadWrQ                   29248                       # Total number of bytes read from write queue
system.mem_ctrls.bytesReadSys                   82432                       # Total read bytes from the system interface side
system.mem_ctrls.bytesWrittenSys                43264                       # Total written bytes from the system interface side
system.mem_ctrls.avgRdBWSys                    971.55                       # Average system read bandwidth in MiByte/s
system.mem_ctrls.avgWrBWSys                    509.91                       # Average system write bandwidth in MiByte/s
system.mem_ctrls.totGap                      84837500                       # Total gap between requests
system.mem_ctrls.avgGap                      43196.28                       # Average gap between requests
system.mem_ctrls.requestorReadBytes::.cpu.inst        40192                       # Per-requestor bytes read from memory
system.mem_ctrls.requestorReadBytes::.cpu.data        12992                       # Per-requestor bytes read from memory
system.mem_ctrls.requestorWriteBytes::.writebacks        22976                       # Per-requestor bytes write to memory
system.mem_ctrls.requestorReadRate::.cpu.inst 473705301.369540154934                       # Per-requestor bytes read from memory rate (Bytes/sec)
system.mem_ctrls.requestorReadRate::.cpu.data 153124484.359899133444                       # Per-requestor bytes read from memory rate (Bytes/sec)
system.mem_ctrls.requestorWriteRate::.writebacks 270796501.897555589676                       # Per-requestor bytes write to memory rate (Bytes/sec)
system.mem_ctrls.requestorReadAccesses::.cpu.inst         1084                       # Per-requestor read serviced memory accesses
system.mem_ctrls.requestorReadAccesses::.cpu.data          204                       # Per-requestor read serviced memory accesses
system.mem_ctrls.requestorWriteAccesses::.writebacks          676                       # Per-requestor write serviced memory accesses
system.mem_ctrls.requestorReadTotalLat::.cpu.inst     16478000                       # Per-requestor read total memory access latency
system.mem_ctrls.requestorReadTotalLat::.cpu.data      6030500                       # Per-requestor read total memory access latency
system.mem_ctrls.requestorWriteTotalLat::.writebacks   1456684750                       # Per-requestor write total memory access latency
system.mem_ctrls.requestorReadAvgLat::.cpu.inst     15201.11                       # Per-requestor read average memory access latency
system.mem_ctrls.requestorReadAvgLat::.cpu.data     29561.27                       # Per-requestor read average memory access latency
system.mem_ctrls.requestorWriteAvgLat::.writebacks   2154859.10                       # Per-requestor write average memory access latency
system.mem_ctrls.dram.bytes_read::.cpu.inst        69376                       # Number of bytes read from this memory
system.mem_ctrls.dram.bytes_read::.cpu.data        13056                       # Number of bytes read from this memory
system.mem_ctrls.dram.bytes_read::total         82432                       # Number of bytes read from this memory
system.mem_ctrls.dram.bytes_inst_read::.cpu.inst        69376                       # Number of instructions bytes read from this memory
system.mem_ctrls.dram.bytes_inst_read::total        69376                       # Number of instructions bytes read from this memory
system.mem_ctrls.dram.num_reads::.cpu.inst         1084                       # Number of read requests responded to by this memory
system.mem_ctrls.dram.num_reads::.cpu.data          204                       # Number of read requests responded to by this memory
system.mem_ctrls.dram.num_reads::total           1288                       # Number of read requests responded to by this memory
system.mem_ctrls.dram.bw_read::.cpu.inst    817669660                       # Total read bandwidth from this memory (bytes/s)
system.mem_ctrls.dram.bw_read::.cpu.data    153878792                       # Total read bandwidth from this memory (bytes/s)
system.mem_ctrls.dram.bw_read::total        971548452                       # Total read bandwidth from this memory (bytes/s)
system.mem_ctrls.dram.bw_inst_read::.cpu.inst    817669660                       # Instruction read bandwidth from this memory (bytes/s)
system.mem_ctrls.dram.bw_inst_read::total    817669660                       # Instruction read bandwidth from this memory (bytes/s)
system.mem_ctrls.dram.bw_total::.cpu.inst    817669660                       # Total bandwidth to/from this memory (bytes/s)
system.mem_ctrls.dram.bw_total::.cpu.data    153878792                       # Total bandwidth to/from this memory (bytes/s)
system.mem_ctrls.dram.bw_total::total       971548452                       # Total bandwidth to/from this memory (bytes/s)
system.mem_ctrls.dram.readBursts                  831                       # Number of DRAM read bursts
system.mem_ctrls.dram.writeBursts                 359                       # Number of DRAM write bursts
system.mem_ctrls.dram.perBankRdBursts::0           78                       # Per bank write bursts
system.mem_ctrls.dram.perBankRdBursts::1          127                       # Per bank write bursts
system.mem_ctrls.dram.perBankRdBursts::2           34                       # Per bank write bursts
system.mem_ctrls.dram.perBankRdBursts::3           44                       # Per bank write bursts
system.mem_ctrls.dram.perBankRdBursts::4           17                       # Per bank write bursts
system.mem_ctrls.dram.perBankRdBursts::5           63                       # Per bank write bursts
system.mem_ctrls.dram.perBankRdBursts::6           63                       # Per bank write bursts
system.mem_ctrls.dram.perBankRdBursts::7           46                       # Per bank write bursts
system.mem_ctrls.dram.perBankRdBursts::8           65                       # Per bank write bursts
system.mem_ctrls.dram.perBankRdBursts::9          105                       # Per bank write bursts
system.mem_ctrls.dram.perBankRdBursts::10           64                       # Per bank write bursts
system.mem_ctrls.dram.perBankRdBursts::11           70                       # Per bank write bursts
system.mem_ctrls.dram.perBankRdBursts::12           30                       # Per bank write bursts
system.mem_ctrls.dram.perBankRdBursts::13           12                       # Per bank write bursts
system.mem_ctrls.dram.perBankRdBursts::14           11                       # Per bank write bursts
system.mem_ctrls.dram.perBankRdBursts::15            2                       # Per bank write bursts
system.mem_ctrls.dram.perBankWrBursts::0           24                       # Per bank write bursts
system.mem_ctrls.dram.perBankWrBursts::1           91                       # Per bank write bursts
system.mem_ctrls.dram.perBankWrBursts::2           14                       # Per bank write bursts
system.mem_ctrls.dram.perBankWrBursts::3           24                       # Per bank write bursts
system.mem_ctrls.dram.perBankWrBursts::4            1                       # Per bank write bursts
system.mem_ctrls.dram.perBankWrBursts::5           67                       # Per bank write bursts
system.mem_ctrls.dram.perBankWrBursts::6           24                       # Per bank write bursts
system.mem_ctrls.dram.perBankWrBursts::7           12                       # Per bank write bursts
system.mem_ctrls.dram.perBankWrBursts::8           14                       # Per bank write bursts
system.mem_ctrls.dram.perBankWrBursts::9           47                       # Per bank write bursts
system.mem_ctrls.dram.perBankWrBursts::10            6                       # Per bank write bursts
system.mem_ctrls.dram.perBankWrBursts::11           20                       # Per bank write bursts
system.mem_ctrls.dram.perBankWrBursts::12           15                       # Per bank write bursts
system.mem_ctrls.dram.perBankWrBursts::13            0                       # Per bank write bursts
system.mem_ctrls.dram.perBankWrBursts::14            0                       # Per bank write bursts
system.mem_ctrls.dram.perBankWrBursts::15            0                       # Per bank write bursts
system.mem_ctrls.dram.totQLat                 6927250                       # Total ticks spent queuing
system.mem_ctrls.dram.totBusLat               4155000                       # Total ticks spent in databus transfers
system.mem_ctrls.dram.totMemAccLat           22508500                       # Total ticks spent from burst creation until serviced by the DRAM
system.mem_ctrls.dram.avgQLat                 8336.04                       # Average queueing delay per DRAM burst
system.mem_ctrls.dram.avgBusLat               5000.00                       # Average bus latency per DRAM burst
system.mem_ctrls.dram.avgMemAccLat           27086.04                       # Average memory access latency per DRAM burst
system.mem_ctrls.dram.readRowHits                 656                       # Number of row buffer hits during reads
system.mem_ctrls.dram.writeRowHits                310                       # Number of row buffer hits during writes
system.mem_ctrls.dram.readRowHitRate            78.94                       # Row buffer hit rate for reads
system.mem_ctrls.dram.writeRowHitRate           86.35                       # Row buffer hit rate for writes
system.mem_ctrls.dram.bytesPerActivate::samples          213                       # Bytes accessed per row activation
system.mem_ctrls.dram.bytesPerActivate::mean   340.131455                       # Bytes accessed per row activation
system.mem_ctrls.dram.bytesPerActivate::gmean   224.456000                       # Bytes accessed per row activation
system.mem_ctrls.dram.bytesPerActivate::stdev   314.209493                       # Bytes accessed per row activation
system.mem_ctrls.dram.bytesPerActivate::0-127           46     21.60%     21.60% # Bytes accessed per row activation
system.mem_ctrls.dram.bytesPerActivate::128-255           63     29.58%     51.17% # Bytes accessed per row activation
system.mem_ctrls.dram.bytesPerActivate::256-383           38     17.84%     69.01% # Bytes accessed per row activation
system.mem_ctrls.dram.bytesPerActivate::384-511           17      7.98%     77.00% # Bytes accessed per row activation
system.mem_ctrls.dram.bytesPerActivate::512-639           12      5.63%     82.63% # Bytes accessed per row activation
system.mem_ctrls.dram.bytesPerActivate::640-767            4      1.88%     84.51% # Bytes accessed per row activation
system.mem_ctrls.dram.bytesPerActivate::768-895            6      2.82%     87.32% # Bytes accessed per row activation
system.mem_ctrls.dram.bytesPerActivate::896-1023            1      0.47%     87.79% # Bytes accessed per row activation
system.mem_ctrls.dram.bytesPerActivate::1024-1151           26     12.21%    100.00% # Bytes accessed per row activation
system.mem_ctrls.dram.bytesPerActivate::total          213                       # Bytes accessed per row activation
system.mem_ctrls.dram.bytesRead                 53184                       # Total number of bytes read from DRAM
system.mem_ctrls.dram.bytesWritten              22976                       # Total number of bytes written to DRAM
system.mem_ctrls.dram.avgRdBW              626.829786                       # Average DRAM read bandwidth in MiBytes/s
system.mem_ctrls.dram.avgWrBW              270.796502                       # Average DRAM write bandwidth in MiBytes/s
system.mem_ctrls.dram.peakBW                 12800.00                       # Theoretical peak bandwidth in MiByte/s
system.mem_ctrls.dram.busUtil                    7.01                       # Data bus utilization in percentage
system.mem_ctrls.dram.busUtilRead                4.90                       # Data bus utilization in percentage for reads
system.mem_ctrls.dram.busUtilWrite               2.12                       # Data bus utilization in percentage for writes
system.mem_ctrls.dram.pageHitRate               81.18                       # Row buffer hit rate, read and write combined
system.mem_ctrls.dram.power_state.pwrStateResidencyTicks::UNDEFINED     84846000                       # Cumulative time (in ticks) in various power states
system.mem_ctrls.dram.rank0.actEnergy          792540                       # Energy for activate commands per rank (pJ)
system.mem_ctrls.dram.rank0.preEnergy          394680                       # Energy for precharge commands per rank (pJ)
system.mem_ctrls.dram.rank0.readEnergy        3370080                       # Energy for read commands per rank (pJ)
system.mem_ctrls.dram.rank0.writeEnergy       1341540                       # Energy for write commands per rank (pJ)
system.mem_ctrls.dram.rank0.refreshEnergy 6146400.000000                       # Energy for refresh commands per rank (pJ)
system.mem_ctrls.dram.rank0.actBackEnergy     36439530                       # Energy for active background per rank (pJ)
system.mem_ctrls.dram.rank0.preBackEnergy      1895040                       # Energy for precharge background per rank (pJ)
system.mem_ctrls.dram.rank0.actPowerDownEnergy            0                       # Energy for active power-down per rank (pJ)
system.mem_ctrls.dram.rank0.prePowerDownEnergy            0                       # Energy for precharge power-down per rank (pJ)
system.mem_ctrls.dram.rank0.selfRefreshEnergy            0                       # Energy for self refresh per rank (pJ)
system.mem_ctrls.dram.rank0.totalEnergy      50379810                       # Total energy per rank (pJ)
system.mem_ctrls.dram.rank0.averagePower   593.779436                       # Core power per rank (mW)
system.mem_ctrls.dram.rank0.totalIdleTime            0                       # Total Idle time Per DRAM Rank
system.mem_ctrls.dram.rank0.pwrStateTime::IDLE      4601250                       # Time in different power states
system.mem_ctrls.dram.rank0.pwrStateTime::REF      2600000                       # Time in different power states
system.mem_ctrls.dram.rank0.pwrStateTime::SREF            0                       # Time in different power states
system.mem_ctrls.dram.rank0.pwrStateTime::PRE_PDN            0                       # Time in different power states
system.mem_ctrls.dram.rank0.pwrStateTime::ACT     77644750                       # Time in different power states
system.mem_ctrls.dram.rank0.pwrStateTime::ACT_PDN            0                       # Time in different power states
system.mem_ctrls.dram.rank1.actEnergy          806820                       # Energy for activate commands per rank (pJ)
system.mem_ctrls.dram.rank1.preEnergy          413655                       # Energy for precharge commands per rank (pJ)
system.mem_ctrls.dram.rank1.readEnergy        2563260                       # Energy for read commands per rank (pJ)
system.mem_ctrls.dram.rank1.writeEnergy        532440                       # Energy for write commands per rank (pJ)
system.mem_ctrls.dram.rank1.refreshEnergy 6146400.000000                       # Energy for refresh commands per rank (pJ)
system.mem_ctrls.dram.rank1.actBackEnergy     29201670                       # Energy for active background per rank (pJ)
system.mem_ctrls.dram.rank1.preBackEnergy      7990080                       # Energy for precharge background per rank (pJ)
system.mem_ctrls.dram.rank1.actPowerDownEnergy            0                       # Energy for active power-down per rank (pJ)
system.mem_ctrls.dram.rank1.prePowerDownEnergy            0                       # Energy for precharge power-down per rank (pJ)
system.mem_ctrls.dram.rank1.selfRefreshEnergy            0                       # Energy for self refresh per rank (pJ)
system.mem_ctrls.dram.rank1.totalEnergy      47654325                       # Total energy per rank (pJ)
system.mem_ctrls.dram.rank1.averagePower   561.656707                       # Core power per rank (mW)
system.mem_ctrls.dram.rank1.totalIdleTime            0                       # Total Idle time Per DRAM Rank
system.mem_ctrls.dram.rank1.pwrStateTime::IDLE     20544500                       # Time in different power states
system.mem_ctrls.dram.rank1.pwrStateTime::REF      2600000                       # Time in different power states
system.mem_ctrls.dram.rank1.pwrStateTime::SREF            0                       # Time in different power states
system.mem_ctrls.dram.rank1.pwrStateTime::PRE_PDN            0                       # Time in different power states
system.mem_ctrls.dram.rank1.pwrStateTime::ACT     61701500                       # Time in different power states
system.mem_ctrls.dram.rank1.pwrStateTime::ACT_PDN            0                       # Time in different power states
system.mem_ctrls.power_state.pwrStateResidencyTicks::UNDEFINED     84846000                       # Cumulative time (in ticks) in various power states
system.membus.trans_dist::ReadResp               1212                       # Transaction distribution
system.membus.trans_dist::WritebackClean          709                       # Transaction distribution
system.membus.trans_dist::ReadExReq                76                       # Transaction distribution
system.membus.trans_dist::ReadExResp               76                       # Transaction distribution
system.membus.trans_dist::ReadCleanReq           1084                       # Transaction distribution
system.membus.trans_dist::ReadSharedReq           128                       # Transaction distribution
system.membus.pkt_count_system.cpu.icache.mem_side_port::system.mem_ctrls.port         2877                       # Packet count per connected requestor and responder (bytes)
system.membus.pkt_count_system.cpu.dcache.mem_side_port::system.mem_ctrls.port          408                       # Packet count per connected requestor and responder (bytes)
system.membus.pkt_count::total                   3285                       # Packet count per connected requestor and responder (bytes)
system.membus.pkt_size_system.cpu.icache.mem_side_port::system.mem_ctrls.port       114752                       # Cumulative packet size per connected requestor and responder (bytes)
system.membus.pkt_size_system.cpu.dcache.mem_side_port::system.mem_ctrls.port        13056                       # Cumulative packet size per connected requestor and responder (bytes)
system.membus.pkt_size::total                  127808                       # Cumulative packet size per connected requestor and responder (bytes)
system.membus.snoops                                0                       # Total snoops (count)
system.membus.snoopTraffic                          0                       # Total snoop traffic (bytes)
system.membus.snoop_fanout::samples              1288                       # Request fanout histogram
system.membus.snoop_fanout::mean             0.043478                       # Request fanout histogram
system.membus.snoop_fanout::stdev            0.204010                       # Request fanout histogram
system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::0                    1232     95.65%     95.65% # Request fanout histogram
system.membus.snoop_fanout::1                      56      4.35%    100.00% # Request fanout histogram
system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
system.membus.snoop_fanout::total                1288                       # Request fanout histogram
system.membus.power_state.pwrStateResidencyTicks::UNDEFINED     84846000                       # Cumulative time (in ticks) in various power states
system.membus.reqLayer0.occupancy             5009000                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization               5.9                       # Layer utilization (%)
system.membus.respLayer1.occupancy            5615000                       # Layer occupancy (ticks)
system.membus.respLayer1.utilization              6.6                       # Layer utilization (%)
system.membus.respLayer2.occupancy            1096500                       # Layer occupancy (ticks)
system.membus.respLayer2.utilization              1.3                       # Layer utilization (%)
system.voltage_domain.voltage                       1                       # Voltage in Volts

---------- End Simulation Statistics   ----------