Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

[CHERI-RISCV] Inline expansion of capability-based cmpxchg in hybrid mode #490

Open
wants to merge 8 commits into
base: dev
Choose a base branch
from
Open

[CHERI-RISCV] Inline expansion of capability-based cmpxchg in hybrid mode #490

wants to merge 8 commits into from
+4,538 −1,054

Commits on Aug 15, 2022

  1. [CHERI-RISC-V] Swap CheriStoreCond_r operand order to match AMO_rr

    @arichardson
    arichardson committed Aug 15, 2022
    Configuration menu
    Copy the full SHA
    8e402bc View commit details
    Browse the repository at this point in the history

  2. [CHERI-RISC-V] Fix capability i8/i16 cmpxchg in hybrid mode 

    This was previously asserting since the backend tried to use the masked
instrinsics (which cannot be used with capabilities and also should not
be used since we need to remain in-bounds).
The test for this commit will be included in the next one since this
depends on cmpxchg being expanded.
    @arichardson
    arichardson committed Aug 15, 2022
    Configuration menu
    Copy the full SHA
    71e651f View commit details
    Browse the repository at this point in the history

  3. [CHERI-RISC-V] Handle capability-based cmpxchg in hybrid mode 

    This adds the required SelectionDAG nodes and RISCVExpandAtomicPseudoInsts
changes to emit cmpxchg (lr.cap/sc.cap) in hybrid mode.

There is one known issues which will be fixed in the next commits:
All explicit mode atomics are relaxed, so we are missing fences.
    @arichardson
    arichardson committed Aug 15, 2022
    Configuration menu
    Copy the full SHA
    140f9fa View commit details
    Browse the repository at this point in the history

  4. [CHERI-RISC-V] Fix lowering of i8/i16 cmpxchg using a capability pointer 

    We should not be using the expandPartwordCmpXchg() logic since capability-
based atomics have i8 and i16 variants. To fix this, add a Type argument
to TLI->getMinCmpXchgSizeInBits() so that the RISC-V backend can return
8 for capability-based cmpxchg and 32 for non-capability ones.
    @arichardson
    arichardson committed Aug 15, 2022
    Configuration menu
    Copy the full SHA
    16ab419 View commit details
    Browse the repository at this point in the history

  5. [CHERI-Generic] Add cmpxchg tests with all memory order combinations 

    This is in preparation for the next commit since they are still missing
the required fences for RISC-V.
    @arichardson
    arichardson committed Aug 15, 2022
    Configuration menu
    Copy the full SHA
    3285480 View commit details
    Browse the repository at this point in the history

  6. [CHERI-RISC-V] Insert the required fences for explicit address mode a… 

    …tomics

The explicit addressing mode atomics always use relaxed ordering so we
need to insert fences if strong orderings are requested.
Fortunately there is already support for this in the AtomicExpandPass so
all we need to do here is to fix emitLeadingFence/emitTrailingFence and
handle RMW instructions in shouldInsertFencesForAtomic().
    @arichardson
    arichardson committed Aug 15, 2022
    Configuration menu
    Copy the full SHA
    e3d507c View commit details
    Browse the repository at this point in the history

  7. [CHERI-RISC-V] Support capability-based integer atomic RMW ops 

    This allows expanding all integer atomic RMW operations using capability
pointers inline in hybrid mode.
    @arichardson
    arichardson committed Aug 15, 2022
    Configuration menu
    Copy the full SHA
    04c69db View commit details
    Browse the repository at this point in the history

  8. [CHERI-RISC-V] Expand capability AtomicRMW XCHG in hybrid mode 

    This allows expanding e.g. `atomicrmw xchg i32 addrspace(200)*` without a
library call. Code generation could be improved by adding an explicit
pseudo but that can be done as a follow-up change
    @arichardson
    arichardson committed Aug 15, 2022
    Configuration menu
    Copy the full SHA
    ef40de6 View commit details
    Browse the repository at this point in the history