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digital_clock.qsf
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# -------------------------------------------------------------------------- #
#
# Copyright (C) 2017 Intel Corporation. All rights reserved.
# Your use of Intel Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Intel Program License
# Subscription Agreement, the Intel Quartus Prime License Agreement,
# the Intel FPGA IP License Agreement, or other applicable license
# agreement, including, without limitation, that your use is for
# the sole purpose of programming logic devices manufactured by
# Intel and sold by Intel or its authorized distributors. Please
# refer to the applicable agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus Prime
# Version 17.1.0 Build 590 10/25/2017 SJ Lite Edition
# Date created = 11:59:14 June 03, 2024
#
# -------------------------------------------------------------------------- #
#
# Notes:
#
# 1) The default values for assignments are stored in the file:
# digital_clock_assignment_defaults.qdf
# If this file doesn't exist, see file:
# assignment_defaults.qdf
#
# 2) Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus Prime software
# and any changes you make may be lost or overwritten.
#
# -------------------------------------------------------------------------- #
set_global_assignment -name FAMILY "Cyclone IV E"
set_global_assignment -name DEVICE EP4CE6F17C8
set_global_assignment -name TOP_LEVEL_ENTITY digital_clock
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 17.1.0
set_global_assignment -name PROJECT_CREATION_TIME_DATE "11:59:14 JUNE 03, 2024"
set_global_assignment -name LAST_QUARTUS_VERSION "17.1.0 Lite Edition"
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1
set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (Verilog)"
set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation
set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "VERILOG HDL" -section_id eda_simulation
set_global_assignment -name VERILOG_FILE digital_clock.v
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_global_assignment -name VERILOG_FILE clock_divider.v
set_global_assignment -name VERILOG_FILE time_counter.v
set_global_assignment -name VERILOG_FILE date_counter.v
set_global_assignment -name VERILOG_FILE display_controller.v
set_location_assignment PIN_C14 -to DigitronCS_Out[5]
set_location_assignment PIN_D12 -to DigitronCS_Out[4]
set_location_assignment PIN_C11 -to DigitronCS_Out[3]
set_location_assignment PIN_F11 -to DigitronCS_Out[2]
set_location_assignment PIN_G11 -to DigitronCS_Out[1]
set_location_assignment PIN_D14 -to DigitronCS_Out[0]
set_location_assignment PIN_C9 -to Digitron_Out[7]
set_location_assignment PIN_E9 -to Digitron_Out[6]
set_location_assignment PIN_D8 -to Digitron_Out[5]
set_location_assignment PIN_C8 -to Digitron_Out[4]
set_location_assignment PIN_D11 -to Digitron_Out[3]
set_location_assignment PIN_E8 -to Digitron_Out[2]
set_location_assignment PIN_E10 -to Digitron_Out[1]
set_location_assignment PIN_D9 -to Digitron_Out[0]
set_location_assignment PIN_R16 -to rst
set_location_assignment PIN_E1 -to clk_50MHz
set_global_assignment -name ENABLE_OCT_DONE OFF
set_global_assignment -name ENABLE_CONFIGURATION_PINS OFF
set_global_assignment -name ENABLE_BOOT_SEL_PIN OFF
set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "PASSIVE SERIAL"
set_global_assignment -name USE_CONFIGURATION_DEVICE OFF
set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF
set_global_assignment -name RESERVE_ALL_UNUSED_PINS_WEAK_PULLUP "AS INPUT TRI-STATED"
set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise
set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall
set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise
set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall
set_global_assignment -name VERILOG_FILE output_files/digital_clock_tb.v
set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
set_global_assignment -name EDA_TEST_BENCH_ENABLE_STATUS TEST_BENCH_MODE -section_id eda_simulation
set_global_assignment -name EDA_NATIVELINK_SIMULATION_TEST_BENCH digital_clock_tb -section_id eda_simulation
set_global_assignment -name EDA_TEST_BENCH_NAME digital_clock_tb -section_id eda_simulation
set_global_assignment -name EDA_DESIGN_INSTANCE_NAME NA -section_id digital_clock_tb
set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME digital_clock_tb -section_id digital_clock_tb
set_global_assignment -name EDA_TEST_BENCH_FILE output_files/digital_clock_tb.v -section_id digital_clock_tb
set_global_assignment -name VERILOG_FILE time_adjuster.v
set_location_assignment PIN_P15 -to sw0
set_location_assignment PIN_P16 -to sw1
set_location_assignment PIN_N15 -to sw2
set_location_assignment PIN_N16 -to sw3
set_location_assignment PIN_A5 -to led_1
set_location_assignment PIN_B5 -to led_2
set_location_assignment PIN_A4 -to led_3
set_global_assignment -name VERILOG_FILE "alarm,_clock.v"
set_location_assignment PIN_L3 -to buzzer
set_location_assignment PIN_N13 -to sw7
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top