digital_clock_inst.v

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// Generated by Quartus Prime Version 17.1 (Build Build 590 10/25/2017)
// Created on Mon Jun 03 13:37:56 2024

digital_clock digital_clock_inst
(
	.clk_50MHz(clk_50MHz_sig) ,	// input  clk_50MHz_sig
	.rst(rst_sig) ,	// input  rst_sig
	.seg0(seg0_sig) ,	// output [6:0] seg0_sig
	.seg1(seg1_sig) ,	// output [6:0] seg1_sig
	.seg2(seg2_sig) ,	// output [6:0] seg2_sig
	.seg3(seg3_sig) ,	// output [6:0] seg3_sig
	.seg4(seg4_sig) ,	// output [6:0] seg4_sig
	.seg5(seg5_sig) 	// output [6:0] seg5_sig
);