time_counter.v.bak

module time_counter(
    input wire clk,
    input wire rst,
    output reg [4:0] hours,
    output reg [5:0] minutes,
    output reg [5:0] seconds
);
    always @(posedge clk or posedge rst) begin
        if (rst) begin
            hours <= 0;
            minutes <= 0;
            seconds <= 0;
        end else begin
            if (seconds == 59) begin
                seconds <= 0;
                if (minutes == 59) begin
                    minutes <= 0;
                    if (hours == 23) begin
                        hours <= 0;
                    end else begin
                        hours <= hours + 1;
                    end
                end else begin
                    minutes <= minutes + 1;
                end
            end else begin
                seconds <= seconds + 1;
            end
        end
    end
endmodule