From 0f52a512d4ed7e29d6301a875d4b4591d27ef79d Mon Sep 17 00:00:00 2001 From: Viacheslav Bocharov Date: Thu, 8 Feb 2024 09:29:11 +0300 Subject: [PATCH] Revert JetHub u-boot patches for emmc clock phase fix --- ...001-HACK-mmc-meson-gx-limit-to-24MHz.patch | 26 +++ ...clean-up-and-align-on-Linux-settings.patch | 154 ------------------ ...change-clock-phase-value-on-axg-SoCs.patch | 54 ++++++ ...-270-core-phase-during-the-identific.patch | 42 ----- ...001-HACK-mmc-meson-gx-limit-to-24MHz.patch | 26 +++ ...clean-up-and-align-on-Linux-settings.patch | 154 ------------------ ...change-clock-phase-value-on-axg-SoCs.patch | 54 ++++++ ...-270-core-phase-during-the-identific.patch | 42 ----- 8 files changed, 160 insertions(+), 392 deletions(-) create mode 100644 patch/u-boot/v2023.10/board_jethubj100/0001-HACK-mmc-meson-gx-limit-to-24MHz.patch delete mode 100644 patch/u-boot/v2023.10/board_jethubj100/0001-mmc-meson-gx-clean-up-and-align-on-Linux-settings.patch create mode 100644 patch/u-boot/v2023.10/board_jethubj100/0002-mmc-meson-gx-change-clock-phase-value-on-axg-SoCs.patch delete mode 100644 patch/u-boot/v2023.10/board_jethubj100/0002-mmc-meson-gx-set-270-core-phase-during-the-identific.patch create mode 100644 patch/u-boot/v2023.10/board_jethubj80/0001-HACK-mmc-meson-gx-limit-to-24MHz.patch delete mode 100644 patch/u-boot/v2023.10/board_jethubj80/0001-mmc-meson-gx-clean-up-and-align-on-Linux-settings.patch create mode 100644 patch/u-boot/v2023.10/board_jethubj80/0002-mmc-meson-gx-change-clock-phase-value-on-axg-SoCs.patch delete mode 100644 patch/u-boot/v2023.10/board_jethubj80/0002-mmc-meson-gx-set-270-core-phase-during-the-identific.patch diff --git a/patch/u-boot/v2023.10/board_jethubj100/0001-HACK-mmc-meson-gx-limit-to-24MHz.patch b/patch/u-boot/v2023.10/board_jethubj100/0001-HACK-mmc-meson-gx-limit-to-24MHz.patch new file mode 100644 index 000000000000..c2248ae670df --- /dev/null +++ b/patch/u-boot/v2023.10/board_jethubj100/0001-HACK-mmc-meson-gx-limit-to-24MHz.patch @@ -0,0 +1,26 @@ +From 96437178d2cd464c29904514d40ac347cc888ee7 Mon Sep 17 00:00:00 2001 +From: Neil Armstrong +Date: Mon, 2 Sep 2019 15:42:04 +0200 +Subject: [PATCH 1/6] HACK: mmc: meson-gx: limit to 24MHz + +Signed-off-by: Neil Armstrong +--- + drivers/mmc/meson_gx_mmc.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/drivers/mmc/meson_gx_mmc.c b/drivers/mmc/meson_gx_mmc.c +index fcf4f03d1e..6ded4b619b 100644 +--- a/drivers/mmc/meson_gx_mmc.c ++++ b/drivers/mmc/meson_gx_mmc.c +@@ -279,7 +279,7 @@ static int meson_mmc_probe(struct udevice *dev) + cfg->host_caps = MMC_MODE_8BIT | MMC_MODE_4BIT | + MMC_MODE_HS_52MHz | MMC_MODE_HS; + cfg->f_min = DIV_ROUND_UP(SD_EMMC_CLKSRC_24M, CLK_MAX_DIV); +- cfg->f_max = 100000000; /* 100 MHz */ ++ cfg->f_max = SD_EMMC_CLKSRC_24M; + cfg->b_max = 511; /* max 512 - 1 blocks */ + cfg->name = dev->name; + +-- +2.30.2 + diff --git a/patch/u-boot/v2023.10/board_jethubj100/0001-mmc-meson-gx-clean-up-and-align-on-Linux-settings.patch b/patch/u-boot/v2023.10/board_jethubj100/0001-mmc-meson-gx-clean-up-and-align-on-Linux-settings.patch deleted file mode 100644 index 2746ec4014b5..000000000000 --- a/patch/u-boot/v2023.10/board_jethubj100/0001-mmc-meson-gx-clean-up-and-align-on-Linux-settings.patch +++ /dev/null @@ -1,154 +0,0 @@ -From 4ddeedeace6efe89a1cc71df0c06673f7158b857 Mon Sep 17 00:00:00 2001 -From: Jerome Brunet -Date: Fri, 15 Sep 2023 18:01:29 +0200 -Subject: [PATCH 1/7] mmc: meson-gx: clean up and align on Linux settings - -* Remove obsolete comments -* Set core phase to 180 regardless of the SoC like Linux -* Enable always-on clock - -AML mmc driver has been working okay(ish) for a few years -The purpose of this patch is to bring u-boot closer to what -Linux is doing - -Signed-off-by: Jerome Brunet ---- - drivers/mmc/meson_gx_mmc.c | 45 ++++++++++++++++---------------------- - drivers/mmc/meson_gx_mmc.h | 9 ++++++-- - 2 files changed, 26 insertions(+), 28 deletions(-) - -diff --git a/drivers/mmc/meson_gx_mmc.c b/drivers/mmc/meson_gx_mmc.c -index fcf4f03d1e..c6168792cb 100644 ---- a/drivers/mmc/meson_gx_mmc.c -+++ b/drivers/mmc/meson_gx_mmc.c -@@ -17,13 +17,14 @@ - #include - #include "meson_gx_mmc.h" - --bool meson_gx_mmc_is_compatible(struct udevice *dev, -- enum meson_gx_mmc_compatible family) --{ -- enum meson_gx_mmc_compatible compat = dev_get_driver_data(dev); -- -- return compat == family; --} -+struct meson_gx_mmc_version_data meson_gx_mmc_version[] = { -+ [MMC_COMPATIBLE_V2] = { -+ .clk_always_on = BIT(24), -+ }, -+ [MMC_COMPATIBLE_V3] = { -+ .clk_always_on = BIT(28), -+ }, -+}; - - static inline void *get_regbase(const struct mmc *mmc) - { -@@ -44,13 +45,17 @@ static inline void meson_write(struct mmc *mmc, uint32_t val, int offset) - - static void meson_mmc_config_clock(struct mmc *mmc) - { -+ struct meson_mmc_plat *pdata = mmc->priv; - uint32_t meson_mmc_clk = 0; - unsigned int clk, clk_src, clk_div; - - if (!mmc->clock) - return; - -- /* TOFIX This should use the proper clock taken from DT */ -+ /* Clk always on */ -+ meson_mmc_clk |= pdata->version->clk_always_on; -+ meson_mmc_clk |= CLK_CO_PHASE_180; -+ meson_mmc_clk |= CLK_TX_PHASE_000; - - /* 1GHz / CLK_MAX_DIV = 15,9 MHz */ - if (mmc->clock > 16000000) { -@@ -62,20 +67,6 @@ static void meson_mmc_config_clock(struct mmc *mmc) - } - clk_div = DIV_ROUND_UP(clk, mmc->clock); - -- /* -- * SM1 SoCs doesn't work fine over 50MHz with CLK_CO_PHASE_180 -- * If CLK_CO_PHASE_270 is used, it's more stable than other. -- * Other SoCs use CLK_CO_PHASE_180 by default. -- * It needs to find what is a proper value about each SoCs. -- */ -- if (meson_gx_mmc_is_compatible(mmc->dev, MMC_COMPATIBLE_SM1)) -- meson_mmc_clk |= CLK_CO_PHASE_270; -- else -- meson_mmc_clk |= CLK_CO_PHASE_180; -- -- /* 180 phase tx clock */ -- meson_mmc_clk |= CLK_TX_PHASE_000; -- - /* clock settings */ - meson_mmc_clk |= clk_src; - meson_mmc_clk |= clk_div; -@@ -243,6 +234,7 @@ static const struct dm_mmc_ops meson_dm_mmc_ops = { - - static int meson_mmc_of_to_plat(struct udevice *dev) - { -+ enum meson_gx_mmc_compatible compat = dev_get_driver_data(dev); - struct meson_mmc_plat *pdata = dev_get_plat(dev); - fdt_addr_t addr; - -@@ -251,6 +243,7 @@ static int meson_mmc_of_to_plat(struct udevice *dev) - return -EINVAL; - - pdata->regbase = (void *)addr; -+ pdata->version = &meson_gx_mmc_version[compat]; - - return 0; - } -@@ -277,7 +270,7 @@ static int meson_mmc_probe(struct udevice *dev) - cfg->voltages = MMC_VDD_33_34 | MMC_VDD_32_33 | - MMC_VDD_31_32 | MMC_VDD_165_195; - cfg->host_caps = MMC_MODE_8BIT | MMC_MODE_4BIT | -- MMC_MODE_HS_52MHz | MMC_MODE_HS; -+ SD_HS | MMC_MODE_HS_52MHz | MMC_MODE_HS; - cfg->f_min = DIV_ROUND_UP(SD_EMMC_CLKSRC_24M, CLK_MAX_DIV); - cfg->f_max = 100000000; /* 100 MHz */ - cfg->b_max = 511; /* max 512 - 1 blocks */ -@@ -321,9 +314,9 @@ int meson_mmc_bind(struct udevice *dev) - } - - static const struct udevice_id meson_mmc_match[] = { -- { .compatible = "amlogic,meson-gx-mmc", .data = MMC_COMPATIBLE_GX }, -- { .compatible = "amlogic,meson-axg-mmc", .data = MMC_COMPATIBLE_GX }, -- { .compatible = "amlogic,meson-sm1-mmc", .data = MMC_COMPATIBLE_SM1 }, -+ { .compatible = "amlogic,meson-gx-mmc", .data = MMC_COMPATIBLE_V2 }, -+ { .compatible = "amlogic,meson-axg-mmc", .data = MMC_COMPATIBLE_V3 }, -+ { .compatible = "amlogic,meson-sm1-mmc", .data = MMC_COMPATIBLE_V3 }, - { /* sentinel */ } - }; - -diff --git a/drivers/mmc/meson_gx_mmc.h b/drivers/mmc/meson_gx_mmc.h -index 8974b78f55..3ec913d1b5 100644 ---- a/drivers/mmc/meson_gx_mmc.h -+++ b/drivers/mmc/meson_gx_mmc.h -@@ -10,8 +10,8 @@ - #include - - enum meson_gx_mmc_compatible { -- MMC_COMPATIBLE_GX, -- MMC_COMPATIBLE_SM1, -+ MMC_COMPATIBLE_V2, -+ MMC_COMPATIBLE_V3, - }; - - #define SDIO_PORT_A 0 -@@ -84,7 +84,12 @@ enum meson_gx_mmc_compatible { - #define MESON_SD_EMMC_CMD_RSP2 0x64 - #define MESON_SD_EMMC_CMD_RSP3 0x68 - -+struct meson_gx_mmc_version_data { -+ uint32_t clk_always_on; -+}; -+ - struct meson_mmc_plat { -+ struct meson_gx_mmc_version_data *version; - struct mmc_config cfg; - struct mmc mmc; - void *regbase; --- -2.34.1 - diff --git a/patch/u-boot/v2023.10/board_jethubj100/0002-mmc-meson-gx-change-clock-phase-value-on-axg-SoCs.patch b/patch/u-boot/v2023.10/board_jethubj100/0002-mmc-meson-gx-change-clock-phase-value-on-axg-SoCs.patch new file mode 100644 index 000000000000..06074f50220c --- /dev/null +++ b/patch/u-boot/v2023.10/board_jethubj100/0002-mmc-meson-gx-change-clock-phase-value-on-axg-SoCs.patch @@ -0,0 +1,54 @@ +From 4ac22afaa40da590605cd725850b81bfb562b0fb Mon Sep 17 00:00:00 2001 +From: Vyacheslav Bocharov +Date: Thu, 2 Dec 2021 13:10:24 +0300 +Subject: [PATCH 2/2] mmc: meson-gx: change clock phase value on axg SoCs + +Amlogic AXG SoCs seems doesn't work over 50MHz. When phase sets to 270', +it's working fine over 50MHz on Amlogic AXG SoCs. +Based on 0dbb54eb3257c243c7968f967a6b183b1edb56c8 by Neil Armstrong + + +To distinguish which value is used adds an u-boot only axg compatible. +--- + drivers/mmc/meson_gx_mmc.c | 5 +++-- + drivers/mmc/meson_gx_mmc.h | 1 + + 2 files changed, 4 insertions(+), 2 deletions(-) + +diff --git a/drivers/mmc/meson_gx_mmc.c b/drivers/mmc/meson_gx_mmc.c +index fcf4f03d1e..718eae42ec 100644 +--- a/drivers/mmc/meson_gx_mmc.c ++++ b/drivers/mmc/meson_gx_mmc.c +@@ -68,7 +68,8 @@ static void meson_mmc_config_clock(struct mmc *mmc) + * Other SoCs use CLK_CO_PHASE_180 by default. + * It needs to find what is a proper value about each SoCs. + */ +- if (meson_gx_mmc_is_compatible(mmc->dev, MMC_COMPATIBLE_SM1)) ++ if (meson_gx_mmc_is_compatible(mmc->dev, MMC_COMPATIBLE_SM1) || ++ meson_gx_mmc_is_compatible(mmc->dev, MMC_COMPATIBLE_AXG)) + meson_mmc_clk |= CLK_CO_PHASE_270; + else + meson_mmc_clk |= CLK_CO_PHASE_180; +@@ -322,7 +323,7 @@ int meson_mmc_bind(struct udevice *dev) + + static const struct udevice_id meson_mmc_match[] = { + { .compatible = "amlogic,meson-gx-mmc", .data = MMC_COMPATIBLE_GX }, +- { .compatible = "amlogic,meson-axg-mmc", .data = MMC_COMPATIBLE_GX }, ++ { .compatible = "amlogic,meson-axg-mmc", .data = MMC_COMPATIBLE_AXG }, + { .compatible = "amlogic,meson-sm1-mmc", .data = MMC_COMPATIBLE_SM1 }, + { /* sentinel */ } + }; +diff --git a/drivers/mmc/meson_gx_mmc.h b/drivers/mmc/meson_gx_mmc.h +index 8974b78f55..53201cedda 100644 +--- a/drivers/mmc/meson_gx_mmc.h ++++ b/drivers/mmc/meson_gx_mmc.h +@@ -12,6 +12,7 @@ + enum meson_gx_mmc_compatible { + MMC_COMPATIBLE_GX, + MMC_COMPATIBLE_SM1, ++ MMC_COMPATIBLE_AXG, + }; + + #define SDIO_PORT_A 0 +-- +2.30.2 + diff --git a/patch/u-boot/v2023.10/board_jethubj100/0002-mmc-meson-gx-set-270-core-phase-during-the-identific.patch b/patch/u-boot/v2023.10/board_jethubj100/0002-mmc-meson-gx-set-270-core-phase-during-the-identific.patch deleted file mode 100644 index 1369d0583d37..000000000000 --- a/patch/u-boot/v2023.10/board_jethubj100/0002-mmc-meson-gx-set-270-core-phase-during-the-identific.patch +++ /dev/null @@ -1,42 +0,0 @@ -From 250bb8a1d083eda665fde994226ecd51bb44672b Mon Sep 17 00:00:00 2001 -From: Jerome Brunet -Date: Fri, 15 Sep 2023 18:01:30 +0200 -Subject: [PATCH 2/7] mmc: meson-gx: set 270 core phase during the - identification - -It has been reported that some devices have problems with a 180 degree -core phase. Setting 270 helped some of these devices. Other continue to -struggle (while it works fine with 180 in Linux ... :sigh:) - -Poking around the HW, it seems that setting a 270 core phase during the -identification, then using 180 for the rest of the operations, helps the -device operate correctly. - -Signed-off-by: Jerome Brunet ---- - drivers/mmc/meson_gx_mmc.c | 7 ++++++- - 1 file changed, 6 insertions(+), 1 deletion(-) - -diff --git a/drivers/mmc/meson_gx_mmc.c b/drivers/mmc/meson_gx_mmc.c -index c6168792cb..284be2b9dc 100644 ---- a/drivers/mmc/meson_gx_mmc.c -+++ b/drivers/mmc/meson_gx_mmc.c -@@ -54,9 +54,14 @@ static void meson_mmc_config_clock(struct mmc *mmc) - - /* Clk always on */ - meson_mmc_clk |= pdata->version->clk_always_on; -- meson_mmc_clk |= CLK_CO_PHASE_180; - meson_mmc_clk |= CLK_TX_PHASE_000; - -+ /* Core phase according to mode */ -+ if (mmc->selected_mode == MMC_LEGACY) -+ meson_mmc_clk |= CLK_CO_PHASE_270; -+ else -+ meson_mmc_clk |= CLK_CO_PHASE_180; -+ - /* 1GHz / CLK_MAX_DIV = 15,9 MHz */ - if (mmc->clock > 16000000) { - clk = SD_EMMC_CLKSRC_DIV2; --- -2.34.1 - diff --git a/patch/u-boot/v2023.10/board_jethubj80/0001-HACK-mmc-meson-gx-limit-to-24MHz.patch b/patch/u-boot/v2023.10/board_jethubj80/0001-HACK-mmc-meson-gx-limit-to-24MHz.patch new file mode 100644 index 000000000000..c2248ae670df --- /dev/null +++ b/patch/u-boot/v2023.10/board_jethubj80/0001-HACK-mmc-meson-gx-limit-to-24MHz.patch @@ -0,0 +1,26 @@ +From 96437178d2cd464c29904514d40ac347cc888ee7 Mon Sep 17 00:00:00 2001 +From: Neil Armstrong +Date: Mon, 2 Sep 2019 15:42:04 +0200 +Subject: [PATCH 1/6] HACK: mmc: meson-gx: limit to 24MHz + +Signed-off-by: Neil Armstrong +--- + drivers/mmc/meson_gx_mmc.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/drivers/mmc/meson_gx_mmc.c b/drivers/mmc/meson_gx_mmc.c +index fcf4f03d1e..6ded4b619b 100644 +--- a/drivers/mmc/meson_gx_mmc.c ++++ b/drivers/mmc/meson_gx_mmc.c +@@ -279,7 +279,7 @@ static int meson_mmc_probe(struct udevice *dev) + cfg->host_caps = MMC_MODE_8BIT | MMC_MODE_4BIT | + MMC_MODE_HS_52MHz | MMC_MODE_HS; + cfg->f_min = DIV_ROUND_UP(SD_EMMC_CLKSRC_24M, CLK_MAX_DIV); +- cfg->f_max = 100000000; /* 100 MHz */ ++ cfg->f_max = SD_EMMC_CLKSRC_24M; + cfg->b_max = 511; /* max 512 - 1 blocks */ + cfg->name = dev->name; + +-- +2.30.2 + diff --git a/patch/u-boot/v2023.10/board_jethubj80/0001-mmc-meson-gx-clean-up-and-align-on-Linux-settings.patch b/patch/u-boot/v2023.10/board_jethubj80/0001-mmc-meson-gx-clean-up-and-align-on-Linux-settings.patch deleted file mode 100644 index 2746ec4014b5..000000000000 --- a/patch/u-boot/v2023.10/board_jethubj80/0001-mmc-meson-gx-clean-up-and-align-on-Linux-settings.patch +++ /dev/null @@ -1,154 +0,0 @@ -From 4ddeedeace6efe89a1cc71df0c06673f7158b857 Mon Sep 17 00:00:00 2001 -From: Jerome Brunet -Date: Fri, 15 Sep 2023 18:01:29 +0200 -Subject: [PATCH 1/7] mmc: meson-gx: clean up and align on Linux settings - -* Remove obsolete comments -* Set core phase to 180 regardless of the SoC like Linux -* Enable always-on clock - -AML mmc driver has been working okay(ish) for a few years -The purpose of this patch is to bring u-boot closer to what -Linux is doing - -Signed-off-by: Jerome Brunet ---- - drivers/mmc/meson_gx_mmc.c | 45 ++++++++++++++++---------------------- - drivers/mmc/meson_gx_mmc.h | 9 ++++++-- - 2 files changed, 26 insertions(+), 28 deletions(-) - -diff --git a/drivers/mmc/meson_gx_mmc.c b/drivers/mmc/meson_gx_mmc.c -index fcf4f03d1e..c6168792cb 100644 ---- a/drivers/mmc/meson_gx_mmc.c -+++ b/drivers/mmc/meson_gx_mmc.c -@@ -17,13 +17,14 @@ - #include - #include "meson_gx_mmc.h" - --bool meson_gx_mmc_is_compatible(struct udevice *dev, -- enum meson_gx_mmc_compatible family) --{ -- enum meson_gx_mmc_compatible compat = dev_get_driver_data(dev); -- -- return compat == family; --} -+struct meson_gx_mmc_version_data meson_gx_mmc_version[] = { -+ [MMC_COMPATIBLE_V2] = { -+ .clk_always_on = BIT(24), -+ }, -+ [MMC_COMPATIBLE_V3] = { -+ .clk_always_on = BIT(28), -+ }, -+}; - - static inline void *get_regbase(const struct mmc *mmc) - { -@@ -44,13 +45,17 @@ static inline void meson_write(struct mmc *mmc, uint32_t val, int offset) - - static void meson_mmc_config_clock(struct mmc *mmc) - { -+ struct meson_mmc_plat *pdata = mmc->priv; - uint32_t meson_mmc_clk = 0; - unsigned int clk, clk_src, clk_div; - - if (!mmc->clock) - return; - -- /* TOFIX This should use the proper clock taken from DT */ -+ /* Clk always on */ -+ meson_mmc_clk |= pdata->version->clk_always_on; -+ meson_mmc_clk |= CLK_CO_PHASE_180; -+ meson_mmc_clk |= CLK_TX_PHASE_000; - - /* 1GHz / CLK_MAX_DIV = 15,9 MHz */ - if (mmc->clock > 16000000) { -@@ -62,20 +67,6 @@ static void meson_mmc_config_clock(struct mmc *mmc) - } - clk_div = DIV_ROUND_UP(clk, mmc->clock); - -- /* -- * SM1 SoCs doesn't work fine over 50MHz with CLK_CO_PHASE_180 -- * If CLK_CO_PHASE_270 is used, it's more stable than other. -- * Other SoCs use CLK_CO_PHASE_180 by default. -- * It needs to find what is a proper value about each SoCs. -- */ -- if (meson_gx_mmc_is_compatible(mmc->dev, MMC_COMPATIBLE_SM1)) -- meson_mmc_clk |= CLK_CO_PHASE_270; -- else -- meson_mmc_clk |= CLK_CO_PHASE_180; -- -- /* 180 phase tx clock */ -- meson_mmc_clk |= CLK_TX_PHASE_000; -- - /* clock settings */ - meson_mmc_clk |= clk_src; - meson_mmc_clk |= clk_div; -@@ -243,6 +234,7 @@ static const struct dm_mmc_ops meson_dm_mmc_ops = { - - static int meson_mmc_of_to_plat(struct udevice *dev) - { -+ enum meson_gx_mmc_compatible compat = dev_get_driver_data(dev); - struct meson_mmc_plat *pdata = dev_get_plat(dev); - fdt_addr_t addr; - -@@ -251,6 +243,7 @@ static int meson_mmc_of_to_plat(struct udevice *dev) - return -EINVAL; - - pdata->regbase = (void *)addr; -+ pdata->version = &meson_gx_mmc_version[compat]; - - return 0; - } -@@ -277,7 +270,7 @@ static int meson_mmc_probe(struct udevice *dev) - cfg->voltages = MMC_VDD_33_34 | MMC_VDD_32_33 | - MMC_VDD_31_32 | MMC_VDD_165_195; - cfg->host_caps = MMC_MODE_8BIT | MMC_MODE_4BIT | -- MMC_MODE_HS_52MHz | MMC_MODE_HS; -+ SD_HS | MMC_MODE_HS_52MHz | MMC_MODE_HS; - cfg->f_min = DIV_ROUND_UP(SD_EMMC_CLKSRC_24M, CLK_MAX_DIV); - cfg->f_max = 100000000; /* 100 MHz */ - cfg->b_max = 511; /* max 512 - 1 blocks */ -@@ -321,9 +314,9 @@ int meson_mmc_bind(struct udevice *dev) - } - - static const struct udevice_id meson_mmc_match[] = { -- { .compatible = "amlogic,meson-gx-mmc", .data = MMC_COMPATIBLE_GX }, -- { .compatible = "amlogic,meson-axg-mmc", .data = MMC_COMPATIBLE_GX }, -- { .compatible = "amlogic,meson-sm1-mmc", .data = MMC_COMPATIBLE_SM1 }, -+ { .compatible = "amlogic,meson-gx-mmc", .data = MMC_COMPATIBLE_V2 }, -+ { .compatible = "amlogic,meson-axg-mmc", .data = MMC_COMPATIBLE_V3 }, -+ { .compatible = "amlogic,meson-sm1-mmc", .data = MMC_COMPATIBLE_V3 }, - { /* sentinel */ } - }; - -diff --git a/drivers/mmc/meson_gx_mmc.h b/drivers/mmc/meson_gx_mmc.h -index 8974b78f55..3ec913d1b5 100644 ---- a/drivers/mmc/meson_gx_mmc.h -+++ b/drivers/mmc/meson_gx_mmc.h -@@ -10,8 +10,8 @@ - #include - - enum meson_gx_mmc_compatible { -- MMC_COMPATIBLE_GX, -- MMC_COMPATIBLE_SM1, -+ MMC_COMPATIBLE_V2, -+ MMC_COMPATIBLE_V3, - }; - - #define SDIO_PORT_A 0 -@@ -84,7 +84,12 @@ enum meson_gx_mmc_compatible { - #define MESON_SD_EMMC_CMD_RSP2 0x64 - #define MESON_SD_EMMC_CMD_RSP3 0x68 - -+struct meson_gx_mmc_version_data { -+ uint32_t clk_always_on; -+}; -+ - struct meson_mmc_plat { -+ struct meson_gx_mmc_version_data *version; - struct mmc_config cfg; - struct mmc mmc; - void *regbase; --- -2.34.1 - diff --git a/patch/u-boot/v2023.10/board_jethubj80/0002-mmc-meson-gx-change-clock-phase-value-on-axg-SoCs.patch b/patch/u-boot/v2023.10/board_jethubj80/0002-mmc-meson-gx-change-clock-phase-value-on-axg-SoCs.patch new file mode 100644 index 000000000000..06074f50220c --- /dev/null +++ b/patch/u-boot/v2023.10/board_jethubj80/0002-mmc-meson-gx-change-clock-phase-value-on-axg-SoCs.patch @@ -0,0 +1,54 @@ +From 4ac22afaa40da590605cd725850b81bfb562b0fb Mon Sep 17 00:00:00 2001 +From: Vyacheslav Bocharov +Date: Thu, 2 Dec 2021 13:10:24 +0300 +Subject: [PATCH 2/2] mmc: meson-gx: change clock phase value on axg SoCs + +Amlogic AXG SoCs seems doesn't work over 50MHz. When phase sets to 270', +it's working fine over 50MHz on Amlogic AXG SoCs. +Based on 0dbb54eb3257c243c7968f967a6b183b1edb56c8 by Neil Armstrong + + +To distinguish which value is used adds an u-boot only axg compatible. +--- + drivers/mmc/meson_gx_mmc.c | 5 +++-- + drivers/mmc/meson_gx_mmc.h | 1 + + 2 files changed, 4 insertions(+), 2 deletions(-) + +diff --git a/drivers/mmc/meson_gx_mmc.c b/drivers/mmc/meson_gx_mmc.c +index fcf4f03d1e..718eae42ec 100644 +--- a/drivers/mmc/meson_gx_mmc.c ++++ b/drivers/mmc/meson_gx_mmc.c +@@ -68,7 +68,8 @@ static void meson_mmc_config_clock(struct mmc *mmc) + * Other SoCs use CLK_CO_PHASE_180 by default. + * It needs to find what is a proper value about each SoCs. + */ +- if (meson_gx_mmc_is_compatible(mmc->dev, MMC_COMPATIBLE_SM1)) ++ if (meson_gx_mmc_is_compatible(mmc->dev, MMC_COMPATIBLE_SM1) || ++ meson_gx_mmc_is_compatible(mmc->dev, MMC_COMPATIBLE_AXG)) + meson_mmc_clk |= CLK_CO_PHASE_270; + else + meson_mmc_clk |= CLK_CO_PHASE_180; +@@ -322,7 +323,7 @@ int meson_mmc_bind(struct udevice *dev) + + static const struct udevice_id meson_mmc_match[] = { + { .compatible = "amlogic,meson-gx-mmc", .data = MMC_COMPATIBLE_GX }, +- { .compatible = "amlogic,meson-axg-mmc", .data = MMC_COMPATIBLE_GX }, ++ { .compatible = "amlogic,meson-axg-mmc", .data = MMC_COMPATIBLE_AXG }, + { .compatible = "amlogic,meson-sm1-mmc", .data = MMC_COMPATIBLE_SM1 }, + { /* sentinel */ } + }; +diff --git a/drivers/mmc/meson_gx_mmc.h b/drivers/mmc/meson_gx_mmc.h +index 8974b78f55..53201cedda 100644 +--- a/drivers/mmc/meson_gx_mmc.h ++++ b/drivers/mmc/meson_gx_mmc.h +@@ -12,6 +12,7 @@ + enum meson_gx_mmc_compatible { + MMC_COMPATIBLE_GX, + MMC_COMPATIBLE_SM1, ++ MMC_COMPATIBLE_AXG, + }; + + #define SDIO_PORT_A 0 +-- +2.30.2 + diff --git a/patch/u-boot/v2023.10/board_jethubj80/0002-mmc-meson-gx-set-270-core-phase-during-the-identific.patch b/patch/u-boot/v2023.10/board_jethubj80/0002-mmc-meson-gx-set-270-core-phase-during-the-identific.patch deleted file mode 100644 index 1369d0583d37..000000000000 --- a/patch/u-boot/v2023.10/board_jethubj80/0002-mmc-meson-gx-set-270-core-phase-during-the-identific.patch +++ /dev/null @@ -1,42 +0,0 @@ -From 250bb8a1d083eda665fde994226ecd51bb44672b Mon Sep 17 00:00:00 2001 -From: Jerome Brunet -Date: Fri, 15 Sep 2023 18:01:30 +0200 -Subject: [PATCH 2/7] mmc: meson-gx: set 270 core phase during the - identification - -It has been reported that some devices have problems with a 180 degree -core phase. Setting 270 helped some of these devices. Other continue to -struggle (while it works fine with 180 in Linux ... :sigh:) - -Poking around the HW, it seems that setting a 270 core phase during the -identification, then using 180 for the rest of the operations, helps the -device operate correctly. - -Signed-off-by: Jerome Brunet ---- - drivers/mmc/meson_gx_mmc.c | 7 ++++++- - 1 file changed, 6 insertions(+), 1 deletion(-) - -diff --git a/drivers/mmc/meson_gx_mmc.c b/drivers/mmc/meson_gx_mmc.c -index c6168792cb..284be2b9dc 100644 ---- a/drivers/mmc/meson_gx_mmc.c -+++ b/drivers/mmc/meson_gx_mmc.c -@@ -54,9 +54,14 @@ static void meson_mmc_config_clock(struct mmc *mmc) - - /* Clk always on */ - meson_mmc_clk |= pdata->version->clk_always_on; -- meson_mmc_clk |= CLK_CO_PHASE_180; - meson_mmc_clk |= CLK_TX_PHASE_000; - -+ /* Core phase according to mode */ -+ if (mmc->selected_mode == MMC_LEGACY) -+ meson_mmc_clk |= CLK_CO_PHASE_270; -+ else -+ meson_mmc_clk |= CLK_CO_PHASE_180; -+ - /* 1GHz / CLK_MAX_DIV = 15,9 MHz */ - if (mmc->clock > 16000000) { - clk = SD_EMMC_CLKSRC_DIV2; --- -2.34.1 -