diff --git a/config/boards/rk3318-box.tvb b/config/boards/rk3318-box.tvb index b50743b16e1f..ce11d427a34f 100644 --- a/config/boards/rk3318-box.tvb +++ b/config/boards/rk3318-box.tvb @@ -9,8 +9,8 @@ BOOT_SCENARIO="tpl-blob-atf-mainline" DDR_BLOB="rk33/rk3318_ddr_333Mhz_v1.16.bin" BOOT_SOC="rk3328" -BOOTBRANCH_BOARD="tag:v2024.01" -BOOTPATCHDIR="v2024.01" +BOOTBRANCH_BOARD="tag:v2024.07-rc5" +BOOTPATCHDIR="v2024.07" enable_extension xorg-lima-serverflags diff --git a/config/sources/families/rockchip.conf b/config/sources/families/rockchip.conf index 4c403711423c..829648387051 100644 --- a/config/sources/families/rockchip.conf +++ b/config/sources/families/rockchip.conf @@ -42,8 +42,8 @@ elif [[ "$BOOT_SOC" == "rk322x" ]]; then OVERLAY_PREFIX='rk322x' UBOOT_TARGET_MAP="ROCKCHIP_TPL=$SRC/packages/blobs/rockchip/rk322x_ddr_333MHz_v1.11_2t.bin TEE=$SRC/packages/blobs/rockchip/rk322x_tee.bin;;u-boot-rk322x-with-spl.bin" - BOOTBRANCH='tag:v2024.01' - BOOTPATCHDIR='v2024.01' + BOOTBRANCH='tag:v2024.07-rc5' + BOOTPATCHDIR='v2024.07' fi diff --git a/patch/u-boot/v2022.04/board_rk322x-box/dtsi-add-generic-tvbox.patch b/patch/u-boot/v2022.04/board_rk322x-box/dtsi-add-generic-tvbox.patch deleted file mode 100644 index 153bd0313336..000000000000 --- a/patch/u-boot/v2022.04/board_rk322x-box/dtsi-add-generic-tvbox.patch +++ /dev/null @@ -1,230 +0,0 @@ -diff --git a/arch/arm/dts/rk322x-generic-tvbox.dtsi b/arch/arm/dts/rk322x-generic-tvbox.dtsi -new file mode 100644 -index 00000000..9328eaf7 ---- /dev/null -+++ b/arch/arm/dts/rk322x-generic-tvbox.dtsi -@@ -0,0 +1,224 @@ -+// SPDX-License-Identifier: GPL-2.0+ OR X11 -+/* -+ * (C) Copyright 2019 Paolo Sabatino -+ * -+ * Generic rk322x tv box device tree include file. -+ * -+ * This dtsi covers most of the common hardware included in generic tv boxes around the market. -+ * Include this dtsi in your configuration and make the necessary adjustments there for base support. -+ * -+ */ -+ -+/dts-v1/; -+ -+#include "rk322x.dtsi" -+ -+/ { -+ -+ chosen { -+ u-boot,dm-pre-reloc; -+ stdout-path = &uart2; -+ u-boot,spl-boot-order = "same-as-spl", &emmc, &sdmmc; -+ }; -+ -+ memory@60000000 { -+ device_type = "memory"; -+ reg = <0x60000000 0x40000000>; -+ }; -+ -+ leds: leds { -+ compatible = "gpio-leds"; -+ -+ /* -+ Main led is available on all boards. -+ Default state is honoured only if led_default_state() is called inside -+ an early init hook function. -+ */ -+ main { -+ label = "heartbeat"; -+ gpios = <&gpio3 RK_PC5 GPIO_ACTIVE_LOW>; -+ default-state = "on"; -+ linux,default-trigger = "heartbeat"; -+ }; -+ -+ }; -+ -+ vcc_sys: vcc-sys-regulator { -+ compatible = "regulator-fixed"; -+ regulator-name = "vcc_sys"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <5000000>; -+ regulator-max-microvolt = <5000000>; -+ }; -+ -+ vcc_phy: vcc-phy-regulator { -+ compatible = "regulator-fixed"; -+ enable-active-high; -+ regulator-name = "vcc_phy"; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; -+ regulator-always-on; -+ regulator-boot-on; -+ }; -+ -+ vcc_otg_vbus: otg-vbus-regulator { -+ compatible = "regulator-fixed"; -+ gpio = <&gpio3 RK_PC6 GPIO_ACTIVE_HIGH>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&otg_vbus_drv>; -+ regulator-name = "vcc_otg_vbus"; -+ regulator-min-microvolt = <5000000>; -+ regulator-max-microvolt = <5000000>; -+ regulator-boot-on; -+// regulator-always-on; -+ enable-active-high; -+ vin-supply = <&vcc_sys>; -+ }; -+ -+ vcc_host_vbus: vcc-host-regulator { -+ compatible = "regulator-fixed"; -+ gpio = <&gpio3 RK_PC4 GPIO_ACTIVE_HIGH>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&host_vbus_drv>; -+ regulator-min-microvolt = <5000000>; -+ regulator-max-microvolt = <5000000>; -+ regulator-name = "vcc_host"; -+// regulator-always-on; -+ regulator-boot-on; -+ enable-active-high; -+ vin-supply = <&vcc_sys>; -+ }; -+ -+ -+}; -+ -+&gmac { -+ -+ assigned-clocks = <&cru SCLK_MAC_SRC>; -+ assigned-clock-rates = <50000000>; -+ -+ clock_in_out = "output"; -+ phy-supply = <&vcc_phy>; -+ phy-mode = "rmii"; -+ phy-is-integrated; -+ -+ tx_delay = < 0x30 >; // Default is 0x30, but original dts proposes 0x26 -+ rx_delay = < 0x10 >; // Default is 0x10, but original dts proposes 0x11 -+ -+ pinctrl-names = "default"; -+ pinctrl-0 = <&phy_pins>; -+ -+ status = "okay"; -+ -+}; -+ -+&emmc { -+ -+ u-boot,dm-spl; -+ clock-frequency = <50000000>; -+ clock-freq-min-max = <400000 50000000>; -+ broken-cd; -+ cap-mmc-highspeed; -+ mmc-hs200-1_8v; -+ supports-emmc; -+ disable-wp; -+ non-removable; -+ /delete-property/ pinctrl-names; -+ /delete-property/ pinctrl-0; -+ status = "okay"; -+ -+}; -+ -+&sdmmc { -+ -+ u-boot,dm-spl; -+ bus-width = <4>; -+ cap-mmc-highspeed; -+ cap-sd-highspeed; -+ card-detect-delay = <200>; -+ disable-wp; -+ num-slots = <1>; -+ supports-sd; -+ -+ status = "okay"; -+ -+}; -+ -+&uart2 { -+ u-boot,dm-pre-reloc; -+ status = "okay"; -+}; -+ -+&u2phy0 { -+ status = "okay"; -+}; -+ -+&u2phy0_otg { -+ status = "okay"; -+}; -+ -+&u2phy0_host { -+ status = "okay"; -+}; -+ -+&u2phy1 { -+ status = "okay"; -+}; -+ -+&u2phy1_otg { -+ status = "okay"; -+}; -+ -+&u2phy1_host { -+ status = "okay"; -+}; -+ -+&usb_host0_ehci { -+ vbus-supply = <&vcc_host_vbus>; -+ status = "okay"; -+}; -+ -+&usb_host0_ohci { -+ vbus-supply = <&vcc_host_vbus>; -+ status = "okay"; -+}; -+ -+&usb_host1_ehci { -+ vbus-supply = <&vcc_host_vbus>; -+ status = "okay"; -+}; -+ -+&usb_host1_ohci { -+ vbus-supply = <&vcc_host_vbus>; -+ status = "okay"; -+}; -+ -+&usb_host2_ehci { -+ vbus-supply = <&vcc_host_vbus>; -+ status = "okay"; -+}; -+ -+&usb_host2_ohci { -+ vbus-supply = <&vcc_host_vbus>; -+ status = "okay"; -+}; -+ -+&usb20_otg{ -+ vbus-supply = <&vcc_otg_vbus>; -+ status = "okay"; -+}; -+ -+&pinctrl { -+ -+ usb { -+ host_vbus_drv: host-vbus-drv { -+ rockchip,pins = <3 RK_PC4 RK_FUNC_GPIO &pcfg_pull_down>; -+ }; -+ -+ otg_vbus_drv: otg-vbus-drv { -+ rockchip,pins = <3 RK_PC6 RK_FUNC_GPIO &pcfg_pull_down>; -+ }; -+ }; -+ -+}; diff --git a/patch/u-boot/v2022.04/board_rk322x-box/rk322x-box-add-defconfig.patch b/patch/u-boot/v2022.04/board_rk322x-box/rk322x-box-add-defconfig.patch deleted file mode 100644 index ad8cbd3f8d99..000000000000 --- a/patch/u-boot/v2022.04/board_rk322x-box/rk322x-box-add-defconfig.patch +++ /dev/null @@ -1,117 +0,0 @@ -diff --git a/configs/rk322x-box_defconfig b/configs/rk322x-box_defconfig -new file mode 100644 -index 00000000..e9d2bab9 ---- /dev/null -+++ b/configs/rk322x-box_defconfig -@@ -0,0 +1,111 @@ -+CONFIG_ARM=y -+CONFIG_SYS_ARCH_TIMER=y -+CONFIG_ARCH_ROCKCHIP=y -+CONFIG_SYS_TEXT_BASE=0x61000000 -+CONFIG_SYS_MALLOC_F_LEN=0x2000 -+CONFIG_NR_DRAM_BANKS=2 -+CONFIG_DEFAULT_DEVICE_TREE="rk322x-box" -+CONFIG_SPL_TEXT_BASE=0x60000000 -+CONFIG_ROCKCHIP_RK322X=y -+CONFIG_SPL_ROCKCHIP_BACK_TO_BROM=y -+CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x0 -+CONFIG_SPL_MMC=y -+CONFIG_TPL_LDSCRIPT="arch/arm/mach-rockchip/u-boot-tpl.lds" -+CONFIG_TARGET_RK322X_BOX=y -+CONFIG_SPL_STACK_R_ADDR=0x60600000 -+CONFIG_DEBUG_UART_BASE=0x11030000 -+CONFIG_DEBUG_UART_CLOCK=24000000 -+CONFIG_DEBUG_UART=y -+CONFIG_LOCALVERSION="-armbian" -+# CONFIG_LOCALVERSION_AUTO is not set -+CONFIG_SYS_LOAD_ADDR=0x63000000 -+CONFIG_FIT=y -+CONFIG_FIT_VERBOSE=y -+CONFIG_SPL_LOAD_FIT=y -+CONFIG_SPL_FIT_SOURCE="board/rockchip/rk322x-box/rk322x-box.its" -+# CONFIG_USE_SPL_FIT_GENERATOR is not set -+CONFIG_SD_BOOT=y -+CONFIG_BOOTDELAY=0 -+CONFIG_USE_PREBOOT=y -+CONFIG_DEFAULT_FDT_FILE="rk322x-box.dtb" -+# CONFIG_CONSOLE_MUX is not set -+# CONFIG_DISPLAY_CPUINFO is not set -+CONFIG_DISPLAY_BOARDINFO_LATE=y -+CONFIG_BOARD_EARLY_INIT_R=y -+CONFIG_MISC_INIT_R=y -+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set -+CONFIG_SPL_STACK_R=y -+CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x8000 -+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x200 -+CONFIG_SPL_OPTEE_IMAGE=y -+CONFIG_CMD_GPIO=y -+CONFIG_CMD_GPT=y -+CONFIG_CMD_MMC=y -+CONFIG_CMD_USB=y -+CONFIG_CMD_ROCKUSB=y -+# CONFIG_CMD_SETEXPR is not set -+CONFIG_CMD_TIME=y -+CONFIG_SPL_OF_CONTROL=y -+CONFIG_TPL_OF_CONTROL=y -+CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" -+CONFIG_ENV_IS_IN_EXT4=y -+CONFIG_ENV_EXT4_INTERFACE="mmc" -+CONFIG_ENV_EXT4_DEVICE_AND_PART="0:auto" -+CONFIG_ENV_EXT4_FILE="/boot/boot.env" -+CONFIG_NET_RANDOM_ETHADDR=y -+CONFIG_REGMAP=y -+CONFIG_SPL_REGMAP=y -+CONFIG_TPL_REGMAP=y -+CONFIG_SYSCON=y -+CONFIG_SPL_SYSCON=y -+CONFIG_TPL_SYSCON=y -+CONFIG_CLK=y -+CONFIG_SPL_CLK=y -+CONFIG_TPL_CLK=y -+CONFIG_FASTBOOT_BUF_SIZE=0x04000000 -+CONFIG_FASTBOOT_CMD_OEM_FORMAT=y -+CONFIG_ROCKCHIP_GPIO=y -+CONFIG_SYS_I2C_ROCKCHIP=y -+CONFIG_LED=y -+CONFIG_LED_GPIO=y -+CONFIG_MISC=y -+CONFIG_ROCKCHIP_EFUSE=y -+CONFIG_MMC_DW=y -+CONFIG_MMC_DW_ROCKCHIP=y -+CONFIG_DM_ETH=y -+CONFIG_ETH_DESIGNWARE=y -+CONFIG_GMAC_ROCKCHIP=y -+CONFIG_PHY_ROCKCHIP_INNO_USB2=y -+CONFIG_PINCTRL=y -+CONFIG_DM_REGULATOR_FIXED=y -+CONFIG_SPL_DM_REGULATOR_FIXED=y -+CONFIG_RAM=y -+CONFIG_SPL_RAM=y -+CONFIG_TPL_RAM=y -+CONFIG_DM_RESET=y -+CONFIG_DEBUG_UART_SHIFT=2 -+CONFIG_DEBUG_UART_SKIP_INIT=y -+CONFIG_SYSRESET=y -+CONFIG_TEE=y -+CONFIG_OPTEE=y -+CONFIG_USB=y -+CONFIG_USB_EHCI_HCD=y -+CONFIG_USB_EHCI_GENERIC=y -+CONFIG_USB_DWC2=y -+CONFIG_ROCKCHIP_USB2_PHY=y -+CONFIG_USB_KEYBOARD=y -+CONFIG_USB_GADGET=y -+CONFIG_USB_GADGET_PRODUCT_NUM=0x320a -+CONFIG_USB_GADGET_DWC2_OTG=y -+CONFIG_USB_GADGET_VBUS_DRAW=500 -+CONFIG_USB_FUNCTION_MASS_STORAGE=y -+CONFIG_USB_FUNCTION_ROCKUSB=y -+CONFIG_DM_VIDEO=y -+# CONFIG_BACKLIGHT_PWM is not set -+# CONFIG_SYS_WHITE_ON_BLACK is not set -+CONFIG_VIDEO_ROCKCHIP=y -+CONFIG_DISPLAY_ROCKCHIP_HDMI=y -+CONFIG_TPL_TINY_MEMSET=y -+CONFIG_ERRNO_STR=y -+CONFIG_OF_LIBFDT_OVERLAY=y -+CONFIG_BOOTM_OPTEE=y diff --git a/patch/u-boot/v2022.04/board_rk322x-box/rk322x-box-add-device-tree-makefile.patch b/patch/u-boot/v2022.04/board_rk322x-box/rk322x-box-add-device-tree-makefile.patch deleted file mode 100644 index c881ceab3bab..000000000000 --- a/patch/u-boot/v2022.04/board_rk322x-box/rk322x-box-add-device-tree-makefile.patch +++ /dev/null @@ -1,222 +0,0 @@ -diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile -index 20dbc2ff..e6aa0b07 100644 ---- a/arch/arm/dts/Makefile -+++ b/arch/arm/dts/Makefile -@@ -75,7 +75,8 @@ dtb-$(CONFIG_ROCKCHIP_RK3188) += \ - rk3188-radxarock.dtb - - dtb-$(CONFIG_ROCKCHIP_RK322X) += \ -- rk3229-evb.dtb -+ rk3229-evb.dtb \ -+ rk322x-box.dtb - - dtb-$(CONFIG_ROCKCHIP_RK3288) += \ - rk3288-evb.dtb \ -diff --git a/arch/arm/mach-rockchip/rk322x/Kconfig b/arch/arm/mach-rockchip/rk322x/Kconfig -index 8a1f95f7..249add9b 100644 ---- a/arch/arm/mach-rockchip/rk322x/Kconfig -+++ b/arch/arm/mach-rockchip/rk322x/Kconfig -@@ -4,6 +4,10 @@ config TARGET_EVB_RK3229 - bool "EVB_RK3229" - select BOARD_LATE_INIT - -+config TARGET_RK322X_BOX -+ bool "RK322X-BOX" -+ select BOARD_LATE_INIT -+ - config SYS_SOC - default "rk322x" - -@@ -14,5 +18,6 @@ config SPL_SERIAL_SUPPORT - default y - - source "board/rockchip/evb_rk3229/Kconfig" -+source "board/rockchip/rk322x-box/Kconfig" - - endif -diff --git a/board/rockchip/rk322x-box/Kconfig b/board/rockchip/rk322x-box/Kconfig -new file mode 100644 -index 00000000..9ec0227e ---- /dev/null -+++ b/board/rockchip/rk322x-box/Kconfig -@@ -0,0 +1,15 @@ -+if TARGET_RK322X_BOX -+ -+config SYS_BOARD -+ default "rk322x-box" -+ -+config SYS_VENDOR -+ default "rockchip" -+ -+config SYS_CONFIG_NAME -+ default "rk322x-box" -+ -+config BOARD_SPECIFIC_OPTIONS # dummy -+ def_bool y -+ -+endif -diff --git a/board/rockchip/rk322x-box/MAINTAINERS b/board/rockchip/rk322x-box/MAINTAINERS -new file mode 100644 -index 00000000..dddc7865 ---- /dev/null -+++ b/board/rockchip/rk322x-box/MAINTAINERS -@@ -0,0 +1,6 @@ -+XT-MX4VR-V10 -+M: Paolo Sabatino -+S: Out of tree -+F: board/rockchip/rk322x-box -+F: include/configs/rk322x-box.h -+F: configs/rk322x-box_defconfig -diff --git a/board/rockchip/rk322x-box/Makefile b/board/rockchip/rk322x-box/Makefile -new file mode 100644 -index 00000000..965ff42c ---- /dev/null -+++ b/board/rockchip/rk322x-box/Makefile -@@ -0,0 +1,7 @@ -+# -+# (C) Copyright 2015 Google, Inc -+# -+# SPDX-License-Identifier: GPL-2.0+ -+# -+ -+obj-y += rk322x-box.o -diff --git a/board/rockchip/rk322x-box/README b/board/rockchip/rk322x-box/README -new file mode 100644 -index 00000000..9c047470 ---- /dev/null -+++ b/board/rockchip/rk322x-box/README -@@ -0,0 +1,72 @@ -+Get the Source and prebuild binary -+================================== -+ -+ > mkdir ~/rk322x-box -+ > cd ~/rk322x-box -+ > git clone git://git.denx.de/u-boot.git -+ > git clone https://github.com/OP-TEE/optee_os.git -+ > git clone https://github.com/rockchip-linux/rkbin.git -+ > git clone https://github.com/rockchip-linux/rkdeveloptool.git -+ -+Compile the OP-TEE -+=============== -+ -+ > cd optee_os -+ > make clean -+ > make CROSS_COMPILE_ta_arm32=arm-none-eabi- PLATFORM=rockchip-rk322x -+ Get tee.bin in this step, copy it to U-Boot root dir: -+ > cp out/arm-plat-rockchip/core/tee-pager.bin ../u-boot/tee.bin -+ -+Compile the U-Boot -+================== -+ -+ > cd ../u-boot -+ > export CROSS_COMPILE=arm-linux-gnueabihf- -+ > export ARCH=arm -+ > make rk322x-box_defconfig -+ > make -+ > make u-boot.itb -+ -+ Get tpl/u-boot-tpl.bin, spl/u-boot-spl.bin and u-boot.itb in this step. -+ -+Compile the rkdeveloptool -+======================= -+ Follow instructions in latest README -+ > cd ../rkflashtool -+ > autoreconf -i -+ > ./configure -+ > make -+ > sudo make install -+ -+ Get rkdeveloptool in you Host in this step. -+ -+Both origin binaries and Tool are ready now, choose either option 1 or -+option 2 to deploy U-Boot. -+ -+Package the image -+================= -+ -+ > cd ../u-boot -+ > tools/mkimage -n rk322x -T rksd -d tpl/u-boot-spl.bin idbloader.img -+ > cat spl/u-boot-spl.bin >> idbloader.img -+ -+ Get idbloader.img in this step. -+ -+Flash the image to eMMC -+======================= -+Power on(or reset with RESET KEY) with MASKROM KEY preesed, and then: -+ > cd .. -+ > rkdeveloptool db rkbin/rk32/rk322x_loader_v1.04.232.bin -+ > rkdeveloptool wl 64 u-boot/idbloader.img -+ > rkdeveloptool wl 0x4000 u-boot/u-boot.itb -+ > rkdeveloptool rd -+ -+Flash the image to SD card -+========================== -+ > dd if=u-boot/idbloader.img of=/dev/sdb seek=64 -+ > dd if=u-boot/u-boot.itb of=/dev/sdb seek=16384 -+ -+You should be able to get U-Boot log message with OP-TEE boot info. -+ -+For more detail, please reference to: -+http://opensource.rock-chips.com/wiki_Boot_option -diff --git a/include/configs/rk322x-box.h b/include/configs/rk322x-box.h -new file mode 100644 -index 00000000..a909aa19 ---- /dev/null -+++ b/include/configs/rk322x-box.h -@@ -0,0 +1,29 @@ -+/* SPDX-License-Identifier: GPL-2.0+ */ -+/* -+ * (C) Copyright 2017 Rockchip Electronics Co., Ltd -+ */ -+ -+#ifndef __CONFIG_H -+#define __CONFIG_H -+ -+#define ROCKCHIP_DEVICE_SETTINGS \ -+ "stdin=serial,usbkbd\0" \ -+ "stdout=serial,vidconsole\0" \ -+ "stderr=serial,vidconsole\0" \ -+ "fdt_high=0xffffffff\0" \ -+ "initrd_high=0xffffffff\0" -+ -+#include -+ -+#undef BOOT_TARGET_DEVICES -+ -+#define BOOT_TARGET_DEVICES(func) \ -+ func(MMC, mmc, 1) \ -+ func(USB, usb, 0) \ -+ func(MMC, mmc, 0) \ -+ func(PXE, pxe, na) \ -+ func(DHCP, dchp, na) -+ -+#define CONFIG_SYS_MMC_ENV_DEV 0 -+ -+#endif -diff --git a/board/rockchip/rk322x-box/rk322x-box.c b/board/rockchip/rk322x-box/rk322x-box.c -new file mode 100644 -index 00000000..ff7d8c98 ---- /dev/null -+++ b/board/rockchip/rk322x-box/rk322x-box.c -@@ -0,0 +1,21 @@ -+// SPDX-License-Identifier: GPL-2.0+ -+/* -+ * (C) Copyright 2017 Rockchip Electronics Co., Ltd -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+ -+int board_early_init_r(void) { -+ -+ /* LED setup */ -+ if (IS_ENABLED(CONFIG_LED)) -+ led_default_state(); -+ -+ return 0; -+ -+} -+ diff --git a/patch/u-boot/v2022.04/board_rk322x-box/rk322x-box-add-device-tree.patch b/patch/u-boot/v2022.04/board_rk322x-box/rk322x-box-add-device-tree.patch deleted file mode 100644 index 722418a9d800..000000000000 --- a/patch/u-boot/v2022.04/board_rk322x-box/rk322x-box-add-device-tree.patch +++ /dev/null @@ -1,72 +0,0 @@ -diff --git a/arch/arm/dts/rk322x-box.dts b/arch/arm/dts/rk322x-box.dts -new file mode 100755 -index 00000000..eb47f976 ---- /dev/null -+++ b/arch/arm/dts/rk322x-box.dts -@@ -0,0 +1,66 @@ -+// SPDX-License-Identifier: GPL-2.0+ OR X11 -+/* -+ * (C) Copyright 2017 Rockchip Electronics Co., Ltd. -+ */ -+ -+/dts-v1/; -+ -+#include "rk322x-generic-tvbox.dtsi" -+ -+/ { -+ model = "Generic Rockchip rk322x TV Box board"; -+ compatible = "rockchip,rk322x-box"; -+ -+}; -+ -+&leds { -+ -+ /* -+ Alternative led: some boards which have main led wired -+ as ACTIVE_LOW will not show anything during boot, thus -+ we put this gpio led as ACTIVE_HIGH, so at least one -+ may give some hint during boot. -+ Schematics say that this pin is connected to I2C0 data -+ bus, which is usually unused on rk322x boards -+ */ -+ -+ alt { -+ label = "alternative"; -+ gpios = <&gpio0 RK_PA1 GPIO_ACTIVE_HIGH>; -+ default-state = "on"; -+ }; -+ -+}; -+ -+&gmac { -+ -+ tx_delay = < 0x26 >; // Default is 0x30, but original dts proposes 0x26 -+ rx_delay = < 0x11 >; // Default is 0x10, but original dts proposes 0x11 -+ status = "okay"; -+ -+}; -+ -+&emmc { -+ -+ status = "okay"; -+ -+}; -+ -+&sdmmc { -+ cd-gpios = <&gpio1 RK_PC1 GPIO_ACTIVE_LOW>; -+ status = "okay"; -+ -+}; -+ -+&pinctrl { -+ -+ pinctrl-names = "default"; -+ pinctrl-0 = <&gpio_leds>; -+ -+ gpio { -+ gpio_leds: gpio-leds { -+ rockchip,pins = <3 21 RK_FUNC_GPIO &pcfg_pull_down>; -+ }; -+ }; -+ -+}; diff --git a/patch/u-boot/v2022.04/board_rk322x-box/rk322x-box-add-its.patch b/patch/u-boot/v2022.04/board_rk322x-box/rk322x-box-add-its.patch deleted file mode 100644 index 43f204c244d6..000000000000 --- a/patch/u-boot/v2022.04/board_rk322x-box/rk322x-box-add-its.patch +++ /dev/null @@ -1,57 +0,0 @@ -diff --git a/board/rockchip/rk322x-box.its b/board/rockchip/rk322x-box/rk322x-box.its -new file mode 100644 -index 00000000..a5824c61 ---- /dev/null -+++ b/board/rockchip/rk322x-box/rk322x-box.its -@@ -0,0 +1,51 @@ -+/* -+ * Copyright (C) 2017-2019 Rockchip Electronic Co.,Ltd -+ * -+ * Simple U-boot FIT source file containing U-Boot, dtb and optee -+ */ -+ -+/dts-v1/; -+ -+/ { -+ description = "FIT image with OP-TEE support"; -+ #address-cells = <1>; -+ -+ images { -+ uboot { -+ description = "U-Boot"; -+ data = /incbin/("u-boot-dtb.bin"); -+ type = "standalone"; -+ os = "U-Boot"; -+ arch = "arm"; -+ compression = "none"; -+ load = <0x61000000>; -+ }; -+ optee { -+ description = "OP-TEE"; -+ data = /incbin/("../../../../../packages/blobs/rockchip/rk322x_tee.bin"); -+ type = "firmware"; -+ arch = "arm"; -+ os = "tee"; -+ compression = "none"; -+ load = <0x68400000>; -+ entry = <0x68400000>; -+ }; -+ fdt { -+ description = "rk322x-box"; -+ data = /incbin/("arch/arm/dts/rk322x-box.dtb"); -+ load = <0x60010000>; -+ type = "flat_dt"; -+ compression = "none"; -+ }; -+ }; -+ -+ configurations { -+ default = "conf"; -+ conf { -+ description = "rk322x-box"; -+ firmware = "optee"; -+ loadables = "uboot"; -+ fdt = "fdt"; -+ }; -+ }; -+}; diff --git a/patch/u-boot/v2022.04/board_rk322x-box/rockchip-device-settings.patch b/patch/u-boot/v2022.04/board_rk322x-box/rockchip-device-settings.patch deleted file mode 100644 index 9d8ad356b615..000000000000 --- a/patch/u-boot/v2022.04/board_rk322x-box/rockchip-device-settings.patch +++ /dev/null @@ -1,12 +0,0 @@ -diff --git a/include/configs/rk322x_common.h b/include/configs/rk322x_common.h -index 15bb8d63..093db403 100644 ---- a/include/configs/rk322x_common.h -+++ b/include/configs/rk322x_common.h -@@ -51,6 +51,7 @@ - "fdt_high=0x7fffffff\0" \ - "partitions=" PARTS_DEFAULT \ - ENV_MEM_LAYOUT_SETTINGS \ -+ ROCKCHIP_DEVICE_SETTINGS \ - BOOTENV - #endif - diff --git a/patch/u-boot/v2022.04/board_rk322x-box/u-boot-1000-enable-rockchip-efuse-for-rk322x-rk3288-and-rk3328.patch b/patch/u-boot/v2022.04/board_rk322x-box/u-boot-1000-enable-rockchip-efuse-for-rk322x-rk3288-and-rk3328.patch deleted file mode 100644 index 58d278287a40..000000000000 --- a/patch/u-boot/v2022.04/board_rk322x-box/u-boot-1000-enable-rockchip-efuse-for-rk322x-rk3288-and-rk3328.patch +++ /dev/null @@ -1,362 +0,0 @@ -From 768ff9ab40cc54e03895a46a4818d36dec150cac Mon Sep 17 00:00:00 2001 -From: Paolo Sabatino -Date: Sun, 4 Apr 2021 10:29:29 +0000 -Subject: [PATCH] Enable rockchip efuse for rk322x, rk3288 and rk3328 - ---- - arch/arm/dts/rk322x.dtsi | 14 +++ - arch/arm/dts/rk3288.dtsi | 3 +- - configs/evb-rk3229_defconfig | 3 + - configs/evb-rk3328_defconfig | 3 + - configs/miqi-rk3288_defconfig | 2 + - configs/rock64-rk3328_defconfig | 2 + - configs/tinker-rk3288_defconfig | 1 + - configs/tinker-s-rk3288_defconfig | 1 + - drivers/misc/rockchip-efuse.c | 142 ++++++++++++++++++++++++- - include/dt-bindings/clock/rk3228-cru.h | 4 + - 10 files changed, 169 insertions(+), 6 deletions(-) - -diff --git a/arch/arm/dts/rk322x.dtsi b/arch/arm/dts/rk322x.dtsi -index 4a8be5dabb..255e3a7a28 100644 ---- a/arch/arm/dts/rk322x.dtsi -+++ b/arch/arm/dts/rk322x.dtsi -@@ -212,6 +212,20 @@ - status = "disabled"; - }; - -+ efuse: efuse@11040000 { -+ compatible = "rockchip,rk3228-efuse", "rockchip,rk3288-efuse"; -+ reg = <0x11040000 0x20>; -+ clocks = <&cru PCLK_EFUSE_256>; -+ clock-names = "pclk_efuse"; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ -+ /* Data cells */ -+ cpu_id: cpu_id@7 { -+ reg = <0x7 0x10>; -+ }; -+ }; -+ - i2c0: i2c@11050000 { - compatible = "rockchip,rk3228-i2c"; - reg = <0x11050000 0x1000>; -diff --git a/arch/arm/dts/rk3288.dtsi b/arch/arm/dts/rk3288.dtsi -index 22bb06cec5..381391360c 100644 ---- a/arch/arm/dts/rk3288.dtsi -+++ b/arch/arm/dts/rk3288.dtsi -@@ -919,8 +919,7 @@ - - efuse: efuse@ffb40000 { - compatible = "rockchip,rk3288-efuse"; -- reg = <0xffb40000 0x10000>; -- status = "disabled"; -+ reg = <0xffb40000 0x20>; - }; - - gic: interrupt-controller@ffc01000 { -diff --git a/configs/evb-rk3229_defconfig b/configs/evb-rk3229_defconfig -index e708ed4909..e3ba0651fd 100644 ---- a/configs/evb-rk3229_defconfig -+++ b/configs/evb-rk3229_defconfig -@@ -49,6 +49,8 @@ CONFIG_FASTBOOT_BUF_SIZE=0x04000000 - CONFIG_FASTBOOT_CMD_OEM_FORMAT=y - CONFIG_ROCKCHIP_GPIO=y - CONFIG_SYS_I2C_ROCKCHIP=y -+CONFIG_MISC=y -+CONFIG_ROCKCHIP_EFUSE=y - CONFIG_MMC_DW=y - CONFIG_MMC_DW_ROCKCHIP=y - CONFIG_MTD=y -@@ -68,3 +70,4 @@ CONFIG_USB_GADGET=y - CONFIG_USB_GADGET_DWC2_OTG=y - CONFIG_TPL_TINY_MEMSET=y - CONFIG_ERRNO_STR=y -+CONFIG_MISC_INIT_R=y -diff --git a/configs/evb-rk3328_defconfig b/configs/evb-rk3328_defconfig -index 9cbfeb0279..f0acfd8abd 100644 ---- a/configs/evb-rk3328_defconfig -+++ b/configs/evb-rk3328_defconfig -@@ -20,6 +20,7 @@ CONFIG_FIT=y - CONFIG_FIT_VERBOSE=y - CONFIG_SPL_LOAD_FIT=y - CONFIG_DEFAULT_FDT_FILE="rockchip/rk3328-evb.dtb" -+CONFIG_MISC_INIT_R=y - # CONFIG_DISPLAY_CPUINFO is not set - CONFIG_DISPLAY_BOARDINFO_LATE=y - # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set -@@ -56,6 +57,8 @@ CONFIG_FASTBOOT_BUF_ADDR=0x800800 - CONFIG_FASTBOOT_CMD_OEM_FORMAT=y - CONFIG_ROCKCHIP_GPIO=y - CONFIG_SYS_I2C_ROCKCHIP=y -+CONFIG_MISC=y -+CONFIG_ROCKCHIP_EFUSE=y - CONFIG_MMC_DW=y - CONFIG_MMC_DW_ROCKCHIP=y - CONFIG_SF_DEFAULT_SPEED=20000000 -diff --git a/configs/miqi-rk3288_defconfig b/configs/miqi-rk3288_defconfig -index 234ced5ab0..3d42e93866 100644 ---- a/configs/miqi-rk3288_defconfig -+++ b/configs/miqi-rk3288_defconfig -@@ -49,6 +49,8 @@ CONFIG_SPL_CLK=y - CONFIG_FASTBOOT_CMD_OEM_FORMAT=y - CONFIG_ROCKCHIP_GPIO=y - CONFIG_SYS_I2C_ROCKCHIP=y -+CONFIG_MISC=y -+CONFIG_ROCKCHIP_EFUSE=y - CONFIG_MMC_DW=y - CONFIG_MMC_DW_ROCKCHIP=y - CONFIG_MTD=y -diff --git a/configs/rock64-rk3328_defconfig b/configs/rock64-rk3328_defconfig -index cb79cea821..dacb57165e 100644 ---- a/configs/rock64-rk3328_defconfig -+++ b/configs/rock64-rk3328_defconfig -@@ -57,6 +57,8 @@ CONFIG_FASTBOOT_BUF_ADDR=0x800800 - CONFIG_FASTBOOT_CMD_OEM_FORMAT=y - CONFIG_ROCKCHIP_GPIO=y - CONFIG_SYS_I2C_ROCKCHIP=y -+CONFIG_MISC=y -+CONFIG_ROCKCHIP_EFUSE=y - CONFIG_MMC_DW=y - CONFIG_MMC_DW_ROCKCHIP=y - CONFIG_SF_DEFAULT_SPEED=20000000 -diff --git a/configs/tinker-rk3288_defconfig b/configs/tinker-rk3288_defconfig -index 8686a66d13..b7dc845451 100644 ---- a/configs/tinker-rk3288_defconfig -+++ b/configs/tinker-rk3288_defconfig -@@ -52,6 +52,7 @@ CONFIG_FASTBOOT_CMD_OEM_FORMAT=y - CONFIG_ROCKCHIP_GPIO=y - CONFIG_SYS_I2C_ROCKCHIP=y - CONFIG_MISC=y -+CONFIG_ROCKCHIP_EFUSE=y - CONFIG_I2C_EEPROM=y - CONFIG_MMC_DW=y - CONFIG_MMC_DW_ROCKCHIP=y -diff --git a/configs/tinker-s-rk3288_defconfig b/configs/tinker-s-rk3288_defconfig -index 22714833cc..19aa314164 100644 ---- a/configs/tinker-s-rk3288_defconfig -+++ b/configs/tinker-s-rk3288_defconfig -@@ -53,6 +53,7 @@ CONFIG_FASTBOOT_CMD_OEM_FORMAT=y - CONFIG_ROCKCHIP_GPIO=y - CONFIG_SYS_I2C_ROCKCHIP=y - CONFIG_MISC=y -+CONFIG_ROCKCHIP_EFUSE=y - CONFIG_I2C_EEPROM=y - CONFIG_MMC_DW=y - CONFIG_MMC_DW_ROCKCHIP=y -diff --git a/drivers/misc/rockchip-efuse.c b/drivers/misc/rockchip-efuse.c -index 083ee65e0a..0fcbcfc69a 100644 ---- a/drivers/misc/rockchip-efuse.c -+++ b/drivers/misc/rockchip-efuse.c -@@ -14,6 +14,7 @@ - #include - #include - #include -+#include - - #define RK3399_A_SHIFT 16 - #define RK3399_A_MASK 0x3ff -@@ -27,6 +28,24 @@ - #define RK3399_STROBE BIT(1) - #define RK3399_CSB BIT(0) - -+#define RK3288_A_SHIFT 6 -+#define RK3288_A_MASK 0x3ff -+#define RK3288_NFUSES 32 -+#define RK3288_BYTES_PER_FUSE 1 -+#define RK3288_PGENB BIT(3) -+#define RK3288_LOAD BIT(2) -+#define RK3288_STROBE BIT(1) -+#define RK3288_CSB BIT(0) -+ -+#define RK3328_INT_STATUS 0x0018 -+#define RK3328_DOUT 0x0020 -+#define RK3328_AUTO_CTRL 0x0024 -+#define RK3328_INT_FINISH BIT(0) -+#define RK3328_AUTO_ENB BIT(0) -+#define RK3328_AUTO_RD BIT(1) -+ -+typedef int (*EFUSE_READ)(struct udevice *dev, int offset, void *buf, int size); -+ - struct rockchip_efuse_regs { - u32 ctrl; /* 0x00 efuse control register */ - u32 dout; /* 0x04 efuse data out register */ -@@ -35,6 +54,10 @@ struct rockchip_efuse_regs { - u32 jtag_pass; /* 0x10 JTAG password */ - u32 strobe_finish_ctrl; - /* 0x14 efuse strobe finish control register */ -+ u32 int_status;/* 0x18 */ -+ u32 reserved; /* 0x1c */ -+ u32 dout2; /* 0x20 */ -+ u32 auto_ctrl; /* 0x24 */ - }; - - struct rockchip_efuse_plat { -@@ -53,7 +76,7 @@ static int dump_efuses(struct cmd_tbl *cmdtp, int flag, - */ - - struct udevice *dev; -- u8 fuses[128]; -+ u8 fuses[128] = {0}; - int ret; - - /* retrieve the device */ -@@ -77,7 +100,7 @@ static int dump_efuses(struct cmd_tbl *cmdtp, int flag, - } - - U_BOOT_CMD( -- rk3399_dump_efuses, 1, 1, dump_efuses, -+ rockchip_dump_efuses, 1, 1, dump_efuses, - "Dump the content of the efuses", - "" - ); -@@ -127,10 +150,110 @@ static int rockchip_rk3399_efuse_read(struct udevice *dev, int offset, - return 0; - } - -+static int rockchip_rk3288_efuse_read(struct udevice *dev, int offset, -+ void *buf, int size) -+{ -+ struct rockchip_efuse_plat *plat = dev_get_plat(dev); -+ struct rockchip_efuse_regs *efuse = -+ (struct rockchip_efuse_regs *)plat->base; -+ u8 *buffer = buf; -+ int max_size = RK3288_NFUSES * RK3288_BYTES_PER_FUSE; -+ -+ if (size > (max_size - offset)) -+ size = max_size - offset; -+ -+ /* Switch to read mode */ -+ writel(RK3288_LOAD | RK3288_PGENB, &efuse->ctrl); -+ udelay(1); -+ -+ while (size--) { -+ writel(readl(&efuse->ctrl) & -+ (~(RK3288_A_MASK << RK3288_A_SHIFT)), -+ &efuse->ctrl); -+ /* set addr */ -+ writel(readl(&efuse->ctrl) | -+ ((offset++ & RK3288_A_MASK) << RK3288_A_SHIFT), -+ &efuse->ctrl); -+ udelay(1); -+ /* strobe low to high */ -+ writel(readl(&efuse->ctrl) | -+ RK3288_STROBE, &efuse->ctrl); -+ ndelay(60); -+ /* read data */ -+ *buffer++ = readl(&efuse->dout); -+ /* reset strobe to low */ -+ writel(readl(&efuse->ctrl) & -+ (~RK3288_STROBE), &efuse->ctrl); -+ udelay(1); -+ } -+ -+ /* Switch to standby mode */ -+ writel(RK3288_PGENB | RK3288_CSB, &efuse->ctrl); -+ -+ return 0; -+} -+ -+static int rockchip_rk3328_efuse_read(struct udevice *dev, int offset, -+ void *buf, int size) -+{ -+ struct rockchip_efuse_plat *plat = dev_get_plat(dev); -+ struct rockchip_efuse_regs *efuse = -+ (struct rockchip_efuse_regs *)plat->base; -+ unsigned int addr_start, addr_end, addr_offset, addr_len; -+ u32 out_value, status; -+ u8 *buffer; -+ int ret = 0, i = 0, j = 0; -+ -+ /* Max non-secure Byte */ -+ if (size > 32) -+ size = 32; -+ -+ /* 128 Byte efuse, 96 Byte for secure, 32 Byte for non-secure */ -+ offset += 96; -+ addr_start = rounddown(offset, RK3399_BYTES_PER_FUSE) / -+ RK3399_BYTES_PER_FUSE; -+ addr_end = roundup(offset + size, RK3399_BYTES_PER_FUSE) / -+ RK3399_BYTES_PER_FUSE; -+ addr_offset = offset % RK3399_BYTES_PER_FUSE; -+ addr_len = addr_end - addr_start; -+ -+ buffer = calloc(1, sizeof(*buffer) * addr_len * RK3399_BYTES_PER_FUSE); -+ if (!buffer) -+ return -ENOMEM; -+ -+ for (j = 0; j < addr_len; j++) { -+ writel(RK3328_AUTO_RD | RK3328_AUTO_ENB | -+ ((addr_start++ & RK3399_A_MASK) << RK3399_A_SHIFT), -+ &efuse->auto_ctrl); -+ udelay(5); -+ status = readl(&efuse->int_status); -+ if (!(status & RK3328_INT_FINISH)) { -+ ret = -EIO; -+ goto err; -+ } -+ out_value = readl(&efuse->dout2); -+ writel(RK3328_INT_FINISH, &efuse->int_status); -+ -+ memcpy(&buffer[i], &out_value, RK3399_BYTES_PER_FUSE); -+ i += RK3399_BYTES_PER_FUSE; -+ } -+ memcpy(buf, buffer + addr_offset, size); -+err: -+ free(buffer); -+ -+ return ret; -+} -+ - static int rockchip_efuse_read(struct udevice *dev, int offset, - void *buf, int size) - { -- return rockchip_rk3399_efuse_read(dev, offset, buf, size); -+ EFUSE_READ efuse_read = NULL; -+ -+ efuse_read = (EFUSE_READ)dev_get_driver_data(dev); -+ if (!efuse_read) -+ return -ENOSYS; -+ -+ return (*efuse_read)(dev, offset, buf, size); - } - - static const struct misc_ops rockchip_efuse_ops = { -@@ -146,7 +269,18 @@ static int rockchip_efuse_of_to_plat(struct udevice *dev) - } - - static const struct udevice_id rockchip_efuse_ids[] = { -- { .compatible = "rockchip,rk3399-efuse" }, -+ { -+ .compatible = "rockchip,rk3288-efuse", -+ .data = (ulong)&rockchip_rk3288_efuse_read, -+ }, -+ { -+ .compatible = "rockchip,rk3328-efuse", -+ .data = (ulong)&rockchip_rk3328_efuse_read, -+ }, -+ { -+ .compatible = "rockchip,rk3399-efuse", -+ .data = (ulong)&rockchip_rk3399_efuse_read, -+ }, - {} - }; - -diff --git a/include/dt-bindings/clock/rk3228-cru.h b/include/dt-bindings/clock/rk3228-cru.h -index 1217d5239f..13b2f4e4a4 100644 ---- a/include/dt-bindings/clock/rk3228-cru.h -+++ b/include/dt-bindings/clock/rk3228-cru.h -@@ -67,6 +67,10 @@ - #define PCLK_GPIO1 321 - #define PCLK_GPIO2 322 - #define PCLK_GPIO3 323 -+#define PCLK_VIO_H2P 324 -+#define PCLK_HDCP 325 -+#define PCLK_EFUSE_1024 326 -+#define PCLK_EFUSE_256 327 - #define PCLK_GRF 329 - #define PCLK_I2C0 332 - #define PCLK_I2C1 333 --- -2.25.1 - diff --git a/patch/u-boot/v2022.04/board_rk322x-box/u-boot-1002-support-rockchip-gmac-rmii.patch b/patch/u-boot/v2022.04/board_rk322x-box/u-boot-1002-support-rockchip-gmac-rmii.patch deleted file mode 100644 index 79043e6fa945..000000000000 --- a/patch/u-boot/v2022.04/board_rk322x-box/u-boot-1002-support-rockchip-gmac-rmii.patch +++ /dev/null @@ -1,896 +0,0 @@ -From e0f2e3d0a36fdb00896b94a1819f120e843b735c Mon Sep 17 00:00:00 2001 -From: Paolo Sabatino -Date: Sun, 4 Apr 2021 10:34:00 +0000 -Subject: [PATCH] Support rockchip gmac rmii - ---- - arch/arm/dts/rk3229-evb.dts | 32 +- - arch/arm/dts/rk322x.dtsi | 8 +- - arch/arm/dts/rk3328.dtsi | 35 ++ - .../include/asm/arch-rockchip/cru_rk322x.h | 1 + - configs/evb-rk3229_defconfig | 2 + - configs/evb-rk3328_defconfig | 2 + - doc/device-tree-bindings/net/phy.txt | 13 + - drivers/clk/rockchip/clk_rk322x.c | 14 +- - drivers/clk/rockchip/clk_rk3328.c | 86 +++++ - drivers/net/gmac_rockchip.c | 338 ++++++++++++++++-- - 10 files changed, 487 insertions(+), 44 deletions(-) - -diff --git a/arch/arm/dts/rk3229-evb.dts b/arch/arm/dts/rk3229-evb.dts -index 632cdc9bc3..f868524ae1 100644 ---- a/arch/arm/dts/rk3229-evb.dts -+++ b/arch/arm/dts/rk3229-evb.dts -@@ -50,19 +50,25 @@ - }; - - &gmac { -- assigned-clocks = <&cru SCLK_MAC_EXTCLK>, <&cru SCLK_MAC>; -- assigned-clock-parents = <&ext_gmac>, <&cru SCLK_MAC_EXTCLK>; -- clock_in_out = "input"; -- phy-supply = <&vcc_phy>; -- phy-mode = "rgmii"; -- pinctrl-names = "default"; -- pinctrl-0 = <&rgmii_pins>; -- snps,reset-gpio = <&gpio2 RK_PD0 GPIO_ACTIVE_LOW>; -- snps,reset-active-low; -- snps,reset-delays-us = <0 10000 1000000>; -- tx_delay = <0x30>; -- rx_delay = <0x10>; -- status = "okay"; -+ assigned-clocks = <&cru SCLK_MAC_SRC>; -+ assigned-clock-rates = <50000000>; -+ clock_in_out = "output"; -+ phy-supply = <&vcc_phy>; -+ phy-mode = "rmii"; -+ phy-handle = <&phy>; -+ status = "okay"; -+ -+ mdio { -+ compatible = "snps,dwmac-mdio"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ phy: phy@0 { -+ compatible = "ethernet-phy-id1234.d400", "ethernet-phy-ieee802.3-c22"; -+ reg = <0>; -+ phy-is-integrated; -+ }; -+ }; - }; - - &emmc { -diff --git a/arch/arm/dts/rk322x.dtsi b/arch/arm/dts/rk322x.dtsi -index 4a8be5dabb..3c2861f271 100644 ---- a/arch/arm/dts/rk322x.dtsi -+++ b/arch/arm/dts/rk322x.dtsi -@@ -448,13 +448,13 @@ - clocks = <&cru SCLK_MAC>, <&cru SCLK_MAC_RX>, - <&cru SCLK_MAC_TX>, <&cru SCLK_MAC_REF>, - <&cru SCLK_MAC_REFOUT>, <&cru ACLK_GMAC>, -- <&cru PCLK_GMAC>; -+ <&cru PCLK_GMAC>, <&cru SCLK_MAC_PHY>; - clock-names = "stmmaceth", "mac_clk_rx", - "mac_clk_tx", "clk_mac_ref", - "clk_mac_refout", "aclk_mac", -- "pclk_mac"; -- resets = <&cru SRST_GMAC>; -- reset-names = "stmmaceth"; -+ "pclk_mac", "clk_macphy"; -+ resets = <&cru SRST_GMAC>, <&cru SRST_MACPHY>; -+ reset-names = "stmmaceth", "mac-phy"; - rockchip,grf = <&grf>; - status = "disabled"; - }; -diff --git a/arch/arm/dts/rk3328.dtsi b/arch/arm/dts/rk3328.dtsi -index 945387e579..68cf0a7eab 100644 ---- a/arch/arm/dts/rk3328.dtsi -+++ b/arch/arm/dts/rk3328.dtsi -@@ -946,6 +946,41 @@ - }; - }; - -+ gmac2phy: ethernet@ff550000 { -+ compatible = "rockchip,rk3328-gmac"; -+ reg = <0x0 0xff550000 0x0 0x10000>; -+ rockchip,grf = <&grf>; -+ interrupts = ; -+ interrupt-names = "macirq"; -+ clocks = <&cru SCLK_MAC2PHY_SRC>, <&cru SCLK_MAC2PHY_RXTX>, -+ <&cru SCLK_MAC2PHY_RXTX>, <&cru SCLK_MAC2PHY_REF>, -+ <&cru ACLK_MAC2PHY>, <&cru PCLK_MAC2PHY>, -+ <&cru SCLK_MAC2PHY_OUT>; -+ clock-names = "stmmaceth", "mac_clk_rx", -+ "mac_clk_tx", "clk_mac_ref", -+ "aclk_mac", "pclk_mac", -+ "clk_macphy"; -+ resets = <&cru SRST_GMAC2PHY_A>, <&cru SRST_MACPHY>; -+ reset-names = "stmmaceth", "mac-phy"; -+ phy-mode = "rmii"; -+ phy-handle = <&phy>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&fephyled_rxm1 &fephyled_linkm1>; -+ status = "disabled"; -+ -+ mdio { -+ compatible = "snps,dwmac-mdio"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ phy: phy@0 { -+ compatible = "ethernet-phy-id1234.d400", "ethernet-phy-ieee802.3-c22"; -+ reg = <0>; -+ phy-is-integrated; -+ }; -+ }; -+ }; -+ - usb_host0_ehci: usb@ff5c0000 { - compatible = "generic-ehci"; - reg = <0x0 0xff5c0000 0x0 0x10000>; -diff --git a/arch/arm/include/asm/arch-rockchip/cru_rk322x.h b/arch/arm/include/asm/arch-rockchip/cru_rk322x.h -index ee12fa831f..cfbc7e92f7 100644 ---- a/arch/arm/include/asm/arch-rockchip/cru_rk322x.h -+++ b/arch/arm/include/asm/arch-rockchip/cru_rk322x.h -@@ -10,6 +10,7 @@ - - #define APLL_HZ (600 * MHz) - #define GPLL_HZ (594 * MHz) -+#define CPLL_HZ (500 * MHz) - - #define CORE_PERI_HZ 150000000 - #define CORE_ACLK_HZ 300000000 -diff --git a/configs/evb-rk3229_defconfig b/configs/evb-rk3229_defconfig -index e708ed4909..382cc9b263 100644 ---- a/configs/evb-rk3229_defconfig -+++ b/configs/evb-rk3229_defconfig -@@ -58,6 +58,8 @@ CONFIG_GMAC_ROCKCHIP=y - CONFIG_PHY=y - CONFIG_PINCTRL=y - CONFIG_RAM=y -+CONFIG_DM_RESET=y -+CONFIG_RESET_ROCKCHIP=y - CONFIG_SPL_RAM=y - CONFIG_TPL_RAM=y - CONFIG_BAUDRATE=1500000 -diff --git a/configs/evb-rk3328_defconfig b/configs/evb-rk3328_defconfig -index 9cbfeb0279..252f0ed839 100644 ---- a/configs/evb-rk3328_defconfig -+++ b/configs/evb-rk3328_defconfig -@@ -71,6 +71,8 @@ CONFIG_DM_REGULATOR_FIXED=y - CONFIG_REGULATOR_RK8XX=y - CONFIG_PWM_ROCKCHIP=y - CONFIG_RAM=y -+CONFIG_DM_RESET=y -+CONFIG_RESET_ROCKCHIP=y - CONFIG_SPL_RAM=y - CONFIG_TPL_RAM=y - CONFIG_BAUDRATE=1500000 -diff --git a/doc/device-tree-bindings/net/phy.txt b/doc/device-tree-bindings/net/phy.txt -index 6599c667b5..ca1a4a8526 100644 ---- a/doc/device-tree-bindings/net/phy.txt -+++ b/doc/device-tree-bindings/net/phy.txt -@@ -8,6 +8,19 @@ Required properties: - - - reg : The ID number for the phy, usually a small integer - -+Optional Properties: -+ -+- compatible: Compatible list, may contain -+ "ethernet-phy-ieee802.3-c22" or "ethernet-phy-ieee802.3-c45" for -+ PHYs that implement IEEE802.3 clause 22 or IEEE802.3 clause 45 -+ specifications. If neither of these are specified, the default is to -+ assume clause 22. -+ -+- phy-is-integrated: If set, indicates that the PHY is integrated into the same -+ physical package as the Ethernet MAC. If needed, muxers should be configured -+ to ensure the integrated PHY is used. The absence of this property indicates -+ the muxers should be configured so that the external PHY is used. -+ - Example: - - ethernet-phy@0 { -diff --git a/drivers/clk/rockchip/clk_rk322x.c b/drivers/clk/rockchip/clk_rk322x.c -index dbef606d88..925aacc6d6 100644 ---- a/drivers/clk/rockchip/clk_rk322x.c -+++ b/drivers/clk/rockchip/clk_rk322x.c -@@ -43,6 +43,7 @@ enum { - /* use integer mode*/ - static const struct pll_div apll_init_cfg = PLL_DIVISORS(APLL_HZ, 1, 3, 1); - static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 2, 2, 1); -+static const struct pll_div cpll_init_cfg = PLL_DIVISORS(CPLL_HZ, 2, 3, 1); - - static int rkclk_set_pll(struct rk322x_cru *cru, enum rk_clk_id clk_id, - const struct pll_div *div) -@@ -92,11 +93,13 @@ static void rkclk_init(struct rk322x_cru *cru) - rk_clrsetreg(&cru->cru_mode_con, - GPLL_MODE_MASK | APLL_MODE_MASK, - GPLL_MODE_SLOW << GPLL_MODE_SHIFT | -- APLL_MODE_SLOW << APLL_MODE_SHIFT); -+ APLL_MODE_SLOW << APLL_MODE_SHIFT | -+ CPLL_MODE_SLOW << CPLL_MODE_SHIFT); - - /* init pll */ - rkclk_set_pll(cru, CLK_ARM, &apll_init_cfg); - rkclk_set_pll(cru, CLK_GENERAL, &gpll_init_cfg); -+ rkclk_set_pll(cru, CLK_CODEC, &cpll_init_cfg); - - /* - * select apll as cpu/core clock pll source and -@@ -169,7 +172,8 @@ static void rkclk_init(struct rk322x_cru *cru) - rk_clrsetreg(&cru->cru_mode_con, - GPLL_MODE_MASK | APLL_MODE_MASK, - GPLL_MODE_NORM << GPLL_MODE_SHIFT | -- APLL_MODE_NORM << APLL_MODE_SHIFT); -+ APLL_MODE_NORM << APLL_MODE_SHIFT | -+ CPLL_MODE_NORM << CPLL_MODE_SHIFT); - } - - /* Get pll rate by id */ -@@ -259,11 +263,10 @@ static ulong rk322x_mac_set_clk(struct rk322x_cru *cru, uint freq) - ulong pll_rate; - u8 div; - -- if ((con >> MAC_PLL_SEL_SHIFT) & MAC_PLL_SEL_MASK) -+ if (con & MAC_PLL_SEL_MASK) - pll_rate = GPLL_HZ; - else -- /* CPLL is not set */ -- return -EPERM; -+ pll_rate = CPLL_HZ; - - div = DIV_ROUND_UP(pll_rate, freq) - 1; - if (div <= 0x1f) -@@ -392,6 +395,7 @@ static ulong rk322x_clk_set_rate(struct clk *clk, ulong rate) - case CLK_DDR: - new_rate = rk322x_ddr_set_clk(priv->cru, rate); - break; -+ case SCLK_MAC_SRC: - case SCLK_MAC: - new_rate = rk322x_mac_set_clk(priv->cru, rate); - break; -diff --git a/drivers/clk/rockchip/clk_rk3328.c b/drivers/clk/rockchip/clk_rk3328.c -index b825ff4cf8..7add1df309 100644 ---- a/drivers/clk/rockchip/clk_rk3328.c -+++ b/drivers/clk/rockchip/clk_rk3328.c -@@ -97,6 +97,14 @@ enum { - PCLK_DBG_DIV_SHIFT = 0, - PCLK_DBG_DIV_MASK = 0xF << PCLK_DBG_DIV_SHIFT, - -+ /* CLKSEL_CON26 */ -+ GMAC2PHY_PLL_SEL_SHIFT = 7, -+ GMAC2PHY_PLL_SEL_MASK = 1 << GMAC2PHY_PLL_SEL_SHIFT, -+ GMAC2PHY_PLL_SEL_CPLL = 0, -+ GMAC2PHY_PLL_SEL_GPLL = 1, -+ GMAC2PHY_CLK_DIV_MASK = 0x1f, -+ GMAC2PHY_CLK_DIV_SHIFT = 0, -+ - /* CLKSEL_CON27 */ - GMAC2IO_PLL_SEL_SHIFT = 7, - GMAC2IO_PLL_SEL_MASK = 1 << GMAC2IO_PLL_SEL_SHIFT, -@@ -444,6 +452,39 @@ static ulong rk3328_gmac2io_set_clk(struct rk3328_cru *cru, ulong rate) - return ret; - } - -+static ulong rk3328_gmac2phy_src_set_clk(struct rk3328_cru *cru, ulong rate) -+{ -+ u32 con = readl(&cru->clksel_con[26]); -+ ulong pll_rate; -+ u8 div; -+ -+ if ((con >> GMAC2PHY_PLL_SEL_SHIFT) & GMAC2PHY_PLL_SEL_GPLL) -+ pll_rate = GPLL_HZ; -+ else -+ pll_rate = CPLL_HZ; -+ -+ div = DIV_ROUND_UP(pll_rate, rate) - 1; -+ if (div <= 0x1f) -+ rk_clrsetreg(&cru->clksel_con[26], GMAC2PHY_CLK_DIV_MASK, -+ div << GMAC2PHY_CLK_DIV_SHIFT); -+ else -+ debug("Unsupported div for gmac:%d\n", div); -+ -+ return DIV_TO_RATE(pll_rate, div); -+} -+ -+static ulong rk3328_gmac2phy_set_clk(struct rk3328_cru *cru, ulong rate) -+{ -+ struct rk3328_grf_regs *grf; -+ -+ grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); -+ if (readl(&grf->mac_con[2]) & BIT(10)) -+ /* An external clock will always generate the right rate... */ -+ return rate; -+ else -+ return rk3328_gmac2phy_src_set_clk(cru, rate); -+} -+ - static ulong rk3328_mmc_get_clk(struct rk3328_cru *cru, uint clk_id) - { - u32 div, con, con_id; -@@ -640,6 +681,12 @@ static ulong rk3328_clk_set_rate(struct clk *clk, ulong rate) - case SCLK_MAC2IO: - ret = rk3328_gmac2io_set_clk(priv->cru, rate); - break; -+ case SCLK_MAC2PHY: -+ ret = rk3328_gmac2phy_set_clk(priv->cru, rate); -+ break; -+ case SCLK_MAC2PHY_SRC: -+ ret = rk3328_gmac2phy_src_set_clk(priv->cru, rate); -+ break; - case SCLK_PWM: - ret = rk3328_pwm_set_clk(priv->cru, rate); - break; -@@ -763,6 +810,43 @@ static int rk3328_gmac2io_ext_set_parent(struct clk *clk, struct clk *parent) - return -EINVAL; - } - -+static int rk3328_gmac2phy_set_parent(struct clk *clk, struct clk *parent) -+{ -+ struct rk3328_grf_regs *grf; -+ const char *clock_output_name; -+ int ret; -+ -+ grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); -+ -+ /* -+ * If the requested parent is in the same clock-controller and the id -+ * is SCLK_MAC2PHY_SRC ("clk_mac2phy_src"), switch to the internal clock. -+ */ -+ if ((parent->dev == clk->dev) && (parent->id == SCLK_MAC2PHY_SRC)) { -+ debug("%s: switching MAC CLK to SCLK_MAC2IO_PHY\n", __func__); -+ rk_clrreg(&grf->mac_con[2], BIT(10)); -+ return 0; -+ } -+ -+ /* -+ * Otherwise, we need to check the clock-output-names of the -+ * requested parent to see if the requested id is "phy_50m_out". -+ */ -+ ret = dev_read_string_index(parent->dev, "clock-output-names", -+ parent->id, &clock_output_name); -+ if (ret < 0) -+ return -ENODATA; -+ -+ /* If this is "phy_50m_out", switch to the external clock input */ -+ if (!strcmp(clock_output_name, "phy_50m_out")) { -+ debug("%s: switching MAC CLK to PHY_50M_OUT\n", __func__); -+ rk_setreg(&grf->mac_con[2], BIT(10)); -+ return 0; -+ } -+ -+ return -EINVAL; -+} -+ - static int rk3328_clk_set_parent(struct clk *clk, struct clk *parent) - { - switch (clk->id) { -@@ -770,6 +854,8 @@ static int rk3328_clk_set_parent(struct clk *clk, struct clk *parent) - return rk3328_gmac2io_set_parent(clk, parent); - case SCLK_MAC2IO_EXT: - return rk3328_gmac2io_ext_set_parent(clk, parent); -+ case SCLK_MAC2PHY: -+ return rk3328_gmac2phy_set_parent(clk, parent); - case DCLK_LCDC: - case SCLK_PDM: - case SCLK_RTC32K: -diff --git a/drivers/net/gmac_rockchip.c b/drivers/net/gmac_rockchip.c -index f909660484..95456693dd 100644 ---- a/drivers/net/gmac_rockchip.c -+++ b/drivers/net/gmac_rockchip.c -@@ -11,6 +11,7 @@ - #include - #include - #include -+#include - #include - #include - #include -@@ -26,6 +27,8 @@ - #include - #include - #include -+#include -+#include - #include - #include - #include "designware.h" -@@ -43,21 +46,30 @@ DECLARE_GLOBAL_DATA_PTR; - struct gmac_rockchip_plat { - struct dw_eth_pdata dw_eth_pdata; - bool clock_input; -+ bool integrated_phy; -+ struct reset_ctl phy_reset; - int tx_delay; - int rx_delay; - }; - - struct rk_gmac_ops { - int (*fix_mac_speed)(struct dw_eth_dev *priv); -+ int (*fix_rmii_speed)(struct gmac_rockchip_plat *pdata, -+ struct dw_eth_dev *priv); -+ int (*fix_rgmii_speed)(struct gmac_rockchip_plat *pdata, -+ struct dw_eth_dev *priv); - void (*set_to_rmii)(struct gmac_rockchip_plat *pdata); - void (*set_to_rgmii)(struct gmac_rockchip_plat *pdata); -+ void (*integrated_phy_powerup)(struct gmac_rockchip_plat *pdata); - }; - - - static int gmac_rockchip_of_to_plat(struct udevice *dev) - { - struct gmac_rockchip_plat *pdata = dev_get_plat(dev); -+ struct ofnode_phandle_args args; - const char *string; -+ int ret; - - string = dev_read_string(dev, "clock_in_out"); - if (!strcmp(string, "input")) -@@ -65,6 +77,25 @@ static int gmac_rockchip_of_to_plat(struct udevice *dev) - else - pdata->clock_input = false; - -+ /* If phy-handle property is passed from DT, use it as the PHY */ -+ ret = dev_read_phandle_with_args(dev, "phy-handle", NULL, 0, 0, &args); -+ if (ret) { -+ debug("Cannot get phy phandle: ret=%d\n", ret); -+ pdata->integrated_phy = dev_read_bool(dev, "phy-is-integrated"); -+ } else { -+ debug("Found phy-handle subnode\n"); -+ pdata->integrated_phy = ofnode_read_bool(args.node, -+ "phy-is-integrated"); -+ } -+ -+ if (pdata->integrated_phy) { -+ ret = reset_get_by_name(dev, "mac-phy", &pdata->phy_reset); -+ if (ret) { -+ debug("No PHY reset control found: ret=%d\n", ret); -+ return ret; -+ } -+ } -+ - /* Check the new naming-style first... */ - pdata->tx_delay = dev_read_u32_default(dev, "tx_delay", -ENOENT); - pdata->rx_delay = dev_read_u32_default(dev, "rx_delay", -ENOENT); -@@ -78,7 +109,8 @@ static int gmac_rockchip_of_to_plat(struct udevice *dev) - return designware_eth_of_to_plat(dev); - } - --static int px30_gmac_fix_mac_speed(struct dw_eth_dev *priv) -+static int px30_gmac_fix_rmii_speed(struct gmac_rockchip_plat *pdata, -+ struct dw_eth_dev *priv) - { - struct px30_grf *grf; - struct clk clk_speed; -@@ -119,7 +151,43 @@ static int px30_gmac_fix_mac_speed(struct dw_eth_dev *priv) - return 0; - } - --static int rk3228_gmac_fix_mac_speed(struct dw_eth_dev *priv) -+static int rk3228_gmac_fix_rmii_speed(struct gmac_rockchip_plat *pdata, -+ struct dw_eth_dev *priv) -+{ -+ struct rk322x_grf *grf; -+ int clk; -+ enum { -+ RK3228_GMAC_RMII_CLK_MASK = BIT(7), -+ RK3228_GMAC_RMII_CLK_2_5M = 0, -+ RK3228_GMAC_RMII_CLK_25M = BIT(7), -+ -+ RK3228_GMAC_RMII_SPEED_MASK = BIT(2), -+ RK3228_GMAC_RMII_SPEED_10 = 0, -+ RK3228_GMAC_RMII_SPEED_100 = BIT(2), -+ }; -+ -+ switch (priv->phydev->speed) { -+ case 10: -+ clk = RK3228_GMAC_RMII_CLK_2_5M | RK3228_GMAC_RMII_SPEED_10; -+ break; -+ case 100: -+ clk = RK3228_GMAC_RMII_CLK_25M | RK3228_GMAC_RMII_SPEED_100; -+ break; -+ default: -+ debug("Unknown phy speed: %d\n", priv->phydev->speed); -+ return -EINVAL; -+ } -+ -+ grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); -+ rk_clrsetreg(&grf->mac_con[1], -+ RK3228_GMAC_RMII_CLK_MASK | RK3228_GMAC_RMII_SPEED_MASK, -+ clk); -+ -+ return 0; -+} -+ -+static int rk3228_gmac_fix_rgmii_speed(struct gmac_rockchip_plat *pdata, -+ struct dw_eth_dev *priv) - { - struct rk322x_grf *grf; - int clk; -@@ -152,7 +220,8 @@ static int rk3228_gmac_fix_mac_speed(struct dw_eth_dev *priv) - return 0; - } - --static int rk3288_gmac_fix_mac_speed(struct dw_eth_dev *priv) -+static int rk3288_gmac_fix_rgmii_speed(struct gmac_rockchip_plat *pdata, -+ struct dw_eth_dev *priv) - { - struct rk3288_grf *grf; - int clk; -@@ -178,7 +247,8 @@ static int rk3288_gmac_fix_mac_speed(struct dw_eth_dev *priv) - return 0; - } - --static int rk3308_gmac_fix_mac_speed(struct dw_eth_dev *priv) -+static int rk3308_gmac_fix_rmii_speed(struct gmac_rockchip_plat *pdata, -+ struct dw_eth_dev *priv) - { - struct rk3308_grf *grf; - struct clk clk_speed; -@@ -219,7 +289,43 @@ static int rk3308_gmac_fix_mac_speed(struct dw_eth_dev *priv) - return 0; - } - --static int rk3328_gmac_fix_mac_speed(struct dw_eth_dev *priv) -+static int rk3328_gmac_fix_rmii_speed(struct gmac_rockchip_plat *pdata, -+ struct dw_eth_dev *priv) -+{ -+ struct rk3328_grf_regs *grf; -+ int clk; -+ enum { -+ RK3328_GMAC_RMII_CLK_MASK = BIT(7), -+ RK3328_GMAC_RMII_CLK_2_5M = 0, -+ RK3328_GMAC_RMII_CLK_25M = BIT(7), -+ -+ RK3328_GMAC_RMII_SPEED_MASK = BIT(2), -+ RK3328_GMAC_RMII_SPEED_10 = 0, -+ RK3328_GMAC_RMII_SPEED_100 = BIT(2), -+ }; -+ -+ switch (priv->phydev->speed) { -+ case 10: -+ clk = RK3328_GMAC_RMII_CLK_2_5M | RK3328_GMAC_RMII_SPEED_10; -+ break; -+ case 100: -+ clk = RK3328_GMAC_RMII_CLK_25M | RK3328_GMAC_RMII_SPEED_100; -+ break; -+ default: -+ debug("Unknown phy speed: %d\n", priv->phydev->speed); -+ return -EINVAL; -+ } -+ -+ grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); -+ rk_clrsetreg(pdata->integrated_phy ? &grf->mac_con[2] : &grf->mac_con[1], -+ RK3328_GMAC_RMII_CLK_MASK | RK3328_GMAC_RMII_SPEED_MASK, -+ clk); -+ -+ return 0; -+} -+ -+static int rk3328_gmac_fix_rgmii_speed(struct gmac_rockchip_plat *pdata, -+ struct dw_eth_dev *priv) - { - struct rk3328_grf_regs *grf; - int clk; -@@ -252,7 +358,8 @@ static int rk3328_gmac_fix_mac_speed(struct dw_eth_dev *priv) - return 0; - } - --static int rk3368_gmac_fix_mac_speed(struct dw_eth_dev *priv) -+static int rk3368_gmac_fix_rgmii_speed(struct gmac_rockchip_plat *pdata, -+ struct dw_eth_dev *priv) - { - struct rk3368_grf *grf; - int clk; -@@ -284,7 +391,8 @@ static int rk3368_gmac_fix_mac_speed(struct dw_eth_dev *priv) - return 0; - } - --static int rk3399_gmac_fix_mac_speed(struct dw_eth_dev *priv) -+static int rk3399_gmac_fix_rgmii_speed(struct gmac_rockchip_plat *pdata, -+ struct dw_eth_dev *priv) - { - struct rk3399_grf_regs *grf; - int clk; -@@ -310,7 +418,8 @@ static int rk3399_gmac_fix_mac_speed(struct dw_eth_dev *priv) - return 0; - } - --static int rv1108_set_rmii_speed(struct dw_eth_dev *priv) -+static int rv1108_gmac_fix_rmii_speed(struct gmac_rockchip_plat *pdata, -+ struct dw_eth_dev *priv) - { - struct rv1108_grf *grf; - int clk, speed; -@@ -361,6 +470,47 @@ static void px30_gmac_set_to_rmii(struct gmac_rockchip_plat *pdata) - PX30_GMAC_PHY_INTF_SEL_RMII); - } - -+static void rk3228_gmac_set_to_rmii(struct gmac_rockchip_plat *pdata) -+{ -+ struct rk322x_grf *grf; -+ enum { -+ RK3228_GRF_CON_RMII_MODE_MASK = BIT(11), -+ RK3228_GRF_CON_RMII_MODE_SEL = BIT(11), -+ RK3228_RMII_MODE_MASK = BIT(10), -+ RK3228_RMII_MODE_SEL = BIT(10), -+ RK3228_GMAC_PHY_INTF_SEL_MASK = GENMASK(6, 4), -+ RK3228_GMAC_PHY_INTF_SEL_RMII = BIT(6), -+ }; -+ -+ grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); -+ rk_clrsetreg(&grf->mac_con[1], -+ RK3228_GRF_CON_RMII_MODE_MASK | -+ RK3228_RMII_MODE_MASK | -+ RK3228_GMAC_PHY_INTF_SEL_MASK, -+ RK3228_GRF_CON_RMII_MODE_SEL | -+ RK3228_RMII_MODE_SEL | -+ RK3228_GMAC_PHY_INTF_SEL_RMII); -+} -+ -+static void rk3328_gmac_set_to_rmii(struct gmac_rockchip_plat *pdata) -+{ -+ struct rk3328_grf_regs *grf; -+ enum { -+ RK3328_RMII_MODE_MASK = BIT(9), -+ RK3328_RMII_MODE = BIT(9), -+ -+ RK3328_GMAC_PHY_INTF_SEL_MASK = GENMASK(6, 4), -+ RK3328_GMAC_PHY_INTF_SEL_RMII = BIT(6), -+ }; -+ -+ grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); -+ rk_clrsetreg(pdata->integrated_phy ? &grf->mac_con[2] : &grf->mac_con[1], -+ RK3328_RMII_MODE_MASK | -+ RK3328_GMAC_PHY_INTF_SEL_MASK, -+ RK3328_GMAC_PHY_INTF_SEL_RMII | -+ RK3328_RMII_MODE); -+} -+ - static void rk3228_gmac_set_to_rgmii(struct gmac_rockchip_plat *pdata) - { - struct rk322x_grf *grf; -@@ -554,6 +704,126 @@ static void rv1108_gmac_set_to_rmii(struct gmac_rockchip_plat *pdata) - RV1108_GMAC_PHY_INTF_SEL_RMII); - } - -+static void rk3228_gmac_integrated_phy_powerup(struct gmac_rockchip_plat *pdata) -+{ -+ struct rk322x_grf *grf; -+ enum { -+ RK3228_GRF_CON_MUX_GMAC_INTEGRATED_PHY_MASK = BIT(15), -+ RK3228_GRF_CON_MUX_GMAC_INTEGRATED_PHY = BIT(15), -+ }; -+ enum { -+ RK3228_MACPHY_CFG_CLK_50M_MASK = BIT(14), -+ RK3228_MACPHY_CFG_CLK_50M = BIT(14), -+ -+ RK3228_MACPHY_RMII_MODE_MASK = GENMASK(7, 6), -+ RK3228_MACPHY_RMII_MODE = BIT(6), -+ -+ RK3228_MACPHY_ENABLE_MASK = BIT(0), -+ RK3228_MACPHY_DISENABLE = 0, -+ RK3228_MACPHY_ENABLE = BIT(0), -+ }; -+ enum { -+ RK3228_RK_GRF_CON2_MACPHY_ID_MASK = GENMASK(6, 0), -+ RK3228_RK_GRF_CON2_MACPHY_ID = 0x1234, -+ }; -+ enum { -+ RK3228_RK_GRF_CON3_MACPHY_ID_MASK = GENMASK(5, 0), -+ RK3228_RK_GRF_CON3_MACPHY_ID = 0x35, -+ }; -+ -+ grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); -+ rk_clrsetreg(&grf->con_iomux, -+ RK3228_GRF_CON_MUX_GMAC_INTEGRATED_PHY_MASK, -+ RK3228_GRF_CON_MUX_GMAC_INTEGRATED_PHY); -+ -+ rk_clrsetreg(&grf->macphy_con[2], -+ RK3228_RK_GRF_CON2_MACPHY_ID_MASK, -+ RK3228_RK_GRF_CON2_MACPHY_ID); -+ -+ rk_clrsetreg(&grf->macphy_con[3], -+ RK3228_RK_GRF_CON3_MACPHY_ID_MASK, -+ RK3228_RK_GRF_CON3_MACPHY_ID); -+ -+ /* disabled before trying to reset it */ -+ rk_clrsetreg(&grf->macphy_con[0], -+ RK3228_MACPHY_CFG_CLK_50M_MASK | -+ RK3228_MACPHY_RMII_MODE_MASK | -+ RK3228_MACPHY_ENABLE_MASK, -+ RK3228_MACPHY_CFG_CLK_50M | -+ RK3228_MACPHY_RMII_MODE | -+ RK3228_MACPHY_DISENABLE); -+ -+ reset_assert(&pdata->phy_reset); -+ udelay(10); -+ reset_deassert(&pdata->phy_reset); -+ udelay(10); -+ -+ rk_clrsetreg(&grf->macphy_con[0], -+ RK3228_MACPHY_ENABLE_MASK, -+ RK3228_MACPHY_ENABLE); -+ udelay(30 * 1000); -+} -+ -+static void rk3328_gmac_integrated_phy_powerup(struct gmac_rockchip_plat *pdata) -+{ -+ struct rk3328_grf_regs *grf; -+ enum { -+ RK3328_GRF_CON_RMII_MODE_MASK = BIT(9), -+ RK3328_GRF_CON_RMII_MODE = BIT(9), -+ }; -+ enum { -+ RK3328_MACPHY_CFG_CLK_50M_MASK = BIT(14), -+ RK3328_MACPHY_CFG_CLK_50M = BIT(14), -+ -+ RK3328_MACPHY_RMII_MODE_MASK = GENMASK(7, 6), -+ RK3328_MACPHY_RMII_MODE = BIT(6), -+ -+ RK3328_MACPHY_ENABLE_MASK = BIT(0), -+ RK3328_MACPHY_DISENABLE = 0, -+ RK3328_MACPHY_ENABLE = BIT(0), -+ }; -+ enum { -+ RK3328_RK_GRF_CON2_MACPHY_ID_MASK = GENMASK(6, 0), -+ RK3328_RK_GRF_CON2_MACPHY_ID = 0x1234, -+ }; -+ enum { -+ RK3328_RK_GRF_CON3_MACPHY_ID_MASK = GENMASK(5, 0), -+ RK3328_RK_GRF_CON3_MACPHY_ID = 0x35, -+ }; -+ -+ grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); -+ rk_clrsetreg(&grf->macphy_con[1], -+ RK3328_GRF_CON_RMII_MODE_MASK, -+ RK3328_GRF_CON_RMII_MODE); -+ -+ rk_clrsetreg(&grf->macphy_con[2], -+ RK3328_RK_GRF_CON2_MACPHY_ID_MASK, -+ RK3328_RK_GRF_CON2_MACPHY_ID); -+ -+ rk_clrsetreg(&grf->macphy_con[3], -+ RK3328_RK_GRF_CON3_MACPHY_ID_MASK, -+ RK3328_RK_GRF_CON3_MACPHY_ID); -+ -+ /* disabled before trying to reset it */ -+ rk_clrsetreg(&grf->macphy_con[0], -+ RK3328_MACPHY_CFG_CLK_50M_MASK | -+ RK3328_MACPHY_RMII_MODE_MASK | -+ RK3328_MACPHY_ENABLE_MASK, -+ RK3328_MACPHY_CFG_CLK_50M | -+ RK3328_MACPHY_RMII_MODE | -+ RK3328_MACPHY_DISENABLE); -+ -+ reset_assert(&pdata->phy_reset); -+ udelay(10); -+ reset_deassert(&pdata->phy_reset); -+ udelay(10); -+ -+ rk_clrsetreg(&grf->macphy_con[0], -+ RK3328_MACPHY_ENABLE_MASK, -+ RK3328_MACPHY_ENABLE); -+ udelay(30 * 1000); -+} -+ - static int gmac_rockchip_probe(struct udevice *dev) - { - struct gmac_rockchip_plat *pdata = dev_get_plat(dev); -@@ -573,6 +843,9 @@ static int gmac_rockchip_probe(struct udevice *dev) - if (ret) - return ret; - -+ if (pdata->integrated_phy && ops->integrated_phy_powerup) -+ ops->integrated_phy_powerup(pdata); -+ - switch (eth_pdata->phy_interface) { - case PHY_INTERFACE_MODE_RGMII: - /* Set to RGMII mode */ -@@ -656,7 +929,7 @@ static int gmac_rockchip_probe(struct udevice *dev) - break; - - default: -- debug("NO interface defined!\n"); -+ debug("%s: no interface defined!\n", __func__); - return -ENXIO; - } - -@@ -665,18 +938,33 @@ static int gmac_rockchip_probe(struct udevice *dev) - - static int gmac_rockchip_eth_start(struct udevice *dev) - { -- struct eth_pdata *pdata = dev_get_plat(dev); -+ struct eth_pdata *eth_pdata = dev_get_plat(dev); - struct dw_eth_dev *priv = dev_get_priv(dev); - struct rk_gmac_ops *ops = - (struct rk_gmac_ops *)dev_get_driver_data(dev); -+ struct gmac_rockchip_plat *pdata = dev_get_plat(dev); - int ret; - -- ret = designware_eth_init(priv, pdata->enetaddr); -- if (ret) -- return ret; -- ret = ops->fix_mac_speed(priv); -+ ret = designware_eth_init(priv, eth_pdata->enetaddr); - if (ret) - return ret; -+ -+ switch (eth_pdata->phy_interface) { -+ case PHY_INTERFACE_MODE_RGMII: -+ ret = ops->fix_rgmii_speed(pdata, priv); -+ if (ret) -+ return ret; -+ break; -+ case PHY_INTERFACE_MODE_RMII: -+ ret = ops->fix_rmii_speed(pdata, priv); -+ if (ret) -+ return ret; -+ break; -+ default: -+ debug("%s: no interface defined!\n", __func__); -+ return -ENXIO; -+ } -+ - ret = designware_eth_enable(priv); - if (ret) - return ret; -@@ -694,42 +982,48 @@ const struct eth_ops gmac_rockchip_eth_ops = { - }; - - const struct rk_gmac_ops px30_gmac_ops = { -- .fix_mac_speed = px30_gmac_fix_mac_speed, -+ .fix_rmii_speed = px30_gmac_fix_rmii_speed, - .set_to_rmii = px30_gmac_set_to_rmii, - }; - - const struct rk_gmac_ops rk3228_gmac_ops = { -- .fix_mac_speed = rk3228_gmac_fix_mac_speed, -+ .fix_rmii_speed = rk3228_gmac_fix_rmii_speed, -+ .fix_rgmii_speed = rk3228_gmac_fix_rgmii_speed, -+ .set_to_rmii = rk3228_gmac_set_to_rmii, - .set_to_rgmii = rk3228_gmac_set_to_rgmii, -+ .integrated_phy_powerup = rk3228_gmac_integrated_phy_powerup, - }; - - const struct rk_gmac_ops rk3288_gmac_ops = { -- .fix_mac_speed = rk3288_gmac_fix_mac_speed, -+ .fix_rgmii_speed = rk3288_gmac_fix_rgmii_speed, - .set_to_rgmii = rk3288_gmac_set_to_rgmii, - }; - - const struct rk_gmac_ops rk3308_gmac_ops = { -- .fix_mac_speed = rk3308_gmac_fix_mac_speed, -+ .fix_rmii_speed = rk3308_gmac_fix_rmii_speed, - .set_to_rmii = rk3308_gmac_set_to_rmii, - }; - - const struct rk_gmac_ops rk3328_gmac_ops = { -- .fix_mac_speed = rk3328_gmac_fix_mac_speed, -+ .fix_rmii_speed = rk3328_gmac_fix_rmii_speed, -+ .fix_rgmii_speed = rk3328_gmac_fix_rgmii_speed, -+ .set_to_rmii = rk3328_gmac_set_to_rmii, - .set_to_rgmii = rk3328_gmac_set_to_rgmii, -+ .integrated_phy_powerup = rk3328_gmac_integrated_phy_powerup, - }; - - const struct rk_gmac_ops rk3368_gmac_ops = { -- .fix_mac_speed = rk3368_gmac_fix_mac_speed, -+ .fix_rgmii_speed = rk3368_gmac_fix_rgmii_speed, - .set_to_rgmii = rk3368_gmac_set_to_rgmii, - }; - - const struct rk_gmac_ops rk3399_gmac_ops = { -- .fix_mac_speed = rk3399_gmac_fix_mac_speed, -+ .fix_rgmii_speed = rk3399_gmac_fix_rgmii_speed, - .set_to_rgmii = rk3399_gmac_set_to_rgmii, - }; - - const struct rk_gmac_ops rv1108_gmac_ops = { -- .fix_mac_speed = rv1108_set_rmii_speed, -+ .fix_rmii_speed = rv1108_gmac_fix_rmii_speed, - .set_to_rmii = rv1108_gmac_set_to_rmii, - }; - --- -2.25.1 - diff --git a/patch/u-boot/v2022.04/board_rk322x-box/u-boot-1005-support-rockchip-tee-binary.patch b/patch/u-boot/v2022.04/board_rk322x-box/u-boot-1005-support-rockchip-tee-binary.patch deleted file mode 100644 index 467faa299220..000000000000 --- a/patch/u-boot/v2022.04/board_rk322x-box/u-boot-1005-support-rockchip-tee-binary.patch +++ /dev/null @@ -1,24 +0,0 @@ -From 52a917980ff9c621ff189c652df6f6c4afa7f44c Mon Sep 17 00:00:00 2001 -From: Paolo Sabatino -Date: Mon, 12 Apr 2021 13:42:48 +0000 -Subject: [PATCH] Set register r1 to CONFIG_SYS_TEXT_BASE to support rockchip - proprietary OP-TEE binaries - ---- - common/spl/spl_optee.S | 1 + - 1 file changed, 1 insertion(+) - -diff --git a/common/spl/spl_optee.S b/common/spl/spl_optee.S -index 8bd1949d..6dde863f 100644 ---- a/common/spl/spl_optee.S -+++ b/common/spl/spl_optee.S -@@ -8,5 +8,6 @@ - - ENTRY(spl_optee_entry) - ldr lr, =CONFIG_SYS_TEXT_BASE -+ ldr r1, =CONFIG_SYS_TEXT_BASE - mov pc, r3 - ENDPROC(spl_optee_entry) --- -2.25.1 - diff --git a/patch/u-boot/v2022.04/board_rk322x-box/zzz-usbphy-clk-ehci-support.patch b/patch/u-boot/v2022.04/board_rk322x-box/zzz-usbphy-clk-ehci-support.patch deleted file mode 100644 index d28fbb9cadd8..000000000000 --- a/patch/u-boot/v2022.04/board_rk322x-box/zzz-usbphy-clk-ehci-support.patch +++ /dev/null @@ -1,398 +0,0 @@ -diff --git a/arch/arm/dts/rk322x.dtsi b/arch/arm/dts/rk322x.dtsi -index 4a8be5da..8ae54a04 100644 ---- a/arch/arm/dts/rk322x.dtsi -+++ b/arch/arm/dts/rk322x.dtsi -@@ -168,6 +168,60 @@ - u-boot,dm-pre-reloc; - compatible = "rockchip,rk3228-grf", "syscon"; - reg = <0x11000000 0x1000>; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ -+ u2phy0: usb2-phy@760 { -+ compatible = "rockchip,rk3228-usb2phy", "rockchip,rk3288-usb-phy"; -+ reg = <0x0760 0x0c>; -+ clocks = <&cru SCLK_OTGPHY0>; -+ clock-names = "phyclk"; -+ clock-output-names = "usb480m_phy0"; -+ #clock-cells = <0>; -+ status = "disabled"; -+ -+ u2phy0_otg: otg-port { -+ interrupts = , -+ , -+ ; -+ interrupt-names = "otg-bvalid", "otg-id", -+ "linestate"; -+ #phy-cells = <0>; -+ status = "disabled"; -+ }; -+ -+ u2phy0_host: host-port { -+ interrupts = ; -+ interrupt-names = "linestate"; -+ #phy-cells = <0>; -+ status = "disabled"; -+ }; -+ }; -+ -+ u2phy1: usb2-phy@800 { -+ compatible = "rockchip,rk3228-usb2phy", "rockchip,rk3288-usb-phy"; -+ reg = <0x0800 0x0c>; -+ clocks = <&cru SCLK_OTGPHY1>; -+ clock-names = "phyclk"; -+ clock-output-names = "usb480m_phy1"; -+ #clock-cells = <0>; -+ status = "disabled"; -+ -+ u2phy1_otg: otg-port { -+ interrupts = ; -+ interrupt-names = "linestate"; -+ #phy-cells = <0>; -+ status = "disabled"; -+ }; -+ -+ u2phy1_host: host-port { -+ interrupts = ; -+ interrupt-names = "linestate"; -+ #phy-cells = <0>; -+ status = "disabled"; -+ }; -+ }; -+ - }; - - uart0: serial@11010000 { -@@ -435,8 +489,75 @@ - "snps,dwc2"; - reg = <0x30040000 0x40000>; - interrupts = ; -- hnp-srp-disable; -+ clocks = <&cru HCLK_OTG>; -+ clock-names = "otg"; - dr_mode = "otg"; -+ g-np-tx-fifo-size = <16>; -+ g-rx-fifo-size = <280>; -+ g-tx-fifo-size = <256 128 128 64 32 16>; -+ hnp-srp-disable; -+ phys = <&u2phy0_otg>; -+ phy-names = "usb2-phy"; -+ status = "disabled"; -+ }; -+ -+ usb_host0_ehci: usb@30080000 { -+ compatible = "generic-ehci"; -+ reg = <0x30080000 0x20000>; -+ interrupts = ; -+ clocks = <&cru HCLK_HOST0>, <&u2phy0>; -+ phys = <&u2phy0_host>; -+ phy-names = "usb"; -+ status = "disabled"; -+ }; -+ -+ usb_host0_ohci: usb@300a0000 { -+ compatible = "generic-ohci"; -+ reg = <0x300a0000 0x20000>; -+ interrupts = ; -+ clocks = <&cru HCLK_HOST0>, <&u2phy0>; -+ phys = <&u2phy0_host>; -+ phy-names = "usb"; -+ status = "disabled"; -+ }; -+ -+ usb_host1_ehci: usb@300c0000 { -+ compatible = "generic-ehci"; -+ reg = <0x300c0000 0x20000>; -+ interrupts = ; -+ clocks = <&cru HCLK_HOST1>, <&u2phy1>; -+ phys = <&u2phy1_otg>; -+ phy-names = "usb"; -+ status = "disabled"; -+ }; -+ -+ usb_host1_ohci: usb@300e0000 { -+ compatible = "generic-ohci"; -+ reg = <0x300e0000 0x20000>; -+ interrupts = ; -+ clocks = <&cru HCLK_HOST1>, <&u2phy1>; -+ phys = <&u2phy1_otg>; -+ phy-names = "usb"; -+ status = "disabled"; -+ }; -+ -+ usb_host2_ehci: usb@30100000 { -+ compatible = "generic-ehci"; -+ reg = <0x30100000 0x20000>; -+ interrupts = ; -+ clocks = <&cru HCLK_HOST2>, <&u2phy1>; -+ phys = <&u2phy1_host>; -+ phy-names = "usb"; -+ status = "disabled"; -+ }; -+ -+ usb_host2_ohci: usb@30120000 { -+ compatible = "generic-ohci"; -+ reg = <0x30120000 0x20000>; -+ interrupts = ; -+ clocks = <&cru HCLK_HOST2>, <&u2phy1>; -+ phys = <&u2phy1_host>; -+ phy-names = "usb"; - status = "disabled"; - }; - -diff --git a/arch/arm/mach-rockchip/rk322x/syscon_rk322x.c b/arch/arm/mach-rockchip/rk322x/syscon_rk322x.c -index 0d9dca81..37c04095 100644 ---- a/arch/arm/mach-rockchip/rk322x/syscon_rk322x.c -+++ b/arch/arm/mach-rockchip/rk322x/syscon_rk322x.c -@@ -17,5 +17,8 @@ static const struct udevice_id rk322x_syscon_ids[] = { - U_BOOT_DRIVER(syscon_rk322x) = { - .name = "rk322x_syscon", - .id = UCLASS_SYSCON, -+#if !CONFIG_IS_ENABLED(OF_PLATDATA) -+ .bind = dm_scan_fdt_dev, -+#endif - .of_match = rk322x_syscon_ids, - }; -diff --git a/drivers/clk/rockchip/clk_rk322x.c b/drivers/clk/rockchip/clk_rk322x.c -index 054b2fd3..21ee1775 100644 ---- a/drivers/clk/rockchip/clk_rk322x.c -+++ b/drivers/clk/rockchip/clk_rk322x.c -@@ -469,10 +469,131 @@ static int rk322x_clk_set_parent(struct clk *clk, struct clk *parent) - return -ENOENT; - } - -+static int rk322x_clk_enable(struct clk *clk) -+{ -+ -+ struct rk322x_clk_priv *priv = dev_get_priv(clk->dev); -+ struct rk322x_cru *cru = priv->cru; -+ -+ switch (clk->id) { -+ case SCLK_OTGPHY0: -+ rk_clrreg(&cru->cru_clkgate_con[1], BIT(5)); -+ break; -+ case SCLK_OTGPHY1: -+ rk_clrreg(&cru->cru_clkgate_con[1], BIT(6)); -+ break; -+ case HCLK_OTG: -+ rk_clrreg(&cru->cru_clkgate_con[11], BIT(12)); -+ break; -+ case HCLK_HOST0: -+ rk_clrreg(&cru->cru_clkgate_con[11], BIT(6)); -+ break; -+ case HCLK_HOST1: -+ rk_clrreg(&cru->cru_clkgate_con[11], BIT(8)); -+ break; -+ case HCLK_HOST2: -+ rk_clrreg(&cru->cru_clkgate_con[11], BIT(10)); -+ break; -+ case SCLK_MAC: -+ rk_clrreg(&cru->cru_clkgate_con[1], BIT(6)); -+ break; -+ case SCLK_MAC_SRC: -+ rk_clrreg(&cru->cru_clkgate_con[1], BIT(7)); -+ break; -+ case SCLK_MAC_RX: -+ rk_clrreg(&cru->cru_clkgate_con[5], BIT(5)); -+ break; -+ case SCLK_MAC_TX: -+ rk_clrreg(&cru->cru_clkgate_con[5], BIT(6)); -+ break; -+ case SCLK_MAC_REF: -+ rk_clrreg(&cru->cru_clkgate_con[5], BIT(3)); -+ break; -+ case SCLK_MAC_REFOUT: -+ rk_clrreg(&cru->cru_clkgate_con[5], BIT(4)); -+ break; -+ case SCLK_MAC_PHY: -+ rk_clrreg(&cru->cru_clkgate_con[5], BIT(7)); -+ break; -+ case ACLK_GMAC: -+ rk_clrreg(&cru->cru_clkgate_con[11], BIT(4)); -+ break; -+ case PCLK_GMAC: -+ rk_clrreg(&cru->cru_clkgate_con[11], BIT(5)); -+ break; -+ default: -+ log_debug("%s: unsupported clk %ld\n", __func__, clk->id); -+ return -ENOENT; -+ } -+ -+ return 0; -+ -+} -+ -+static int rk322x_clk_disable(struct clk *clk) -+{ -+ -+ struct rk322x_clk_priv *priv = dev_get_priv(clk->dev); -+ struct rk322x_cru *cru = priv->cru; -+ -+ switch (clk->id) { -+ case SCLK_OTGPHY0: -+ rk_setreg(&cru->cru_clkgate_con[1], BIT(5)); -+ break; -+ case SCLK_OTGPHY1: -+ rk_setreg(&cru->cru_clkgate_con[1], BIT(6)); -+ break; -+ case HCLK_OTG: -+ rk_setreg(&cru->cru_clkgate_con[11], BIT(12)); -+ break; -+ case HCLK_HOST0: -+ rk_setreg(&cru->cru_clkgate_con[11], BIT(6)); -+ break; -+ case HCLK_HOST1: -+ rk_setreg(&cru->cru_clkgate_con[11], BIT(8)); -+ break; -+ case HCLK_HOST2: -+ rk_setreg(&cru->cru_clkgate_con[11], BIT(10)); -+ break; -+ case SCLK_MAC_SRC: -+ rk_setreg(&cru->cru_clkgate_con[1], BIT(7)); -+ break; -+ case SCLK_MAC_RX: -+ rk_setreg(&cru->cru_clkgate_con[5], BIT(5)); -+ break; -+ case SCLK_MAC_TX: -+ rk_setreg(&cru->cru_clkgate_con[5], BIT(6)); -+ break; -+ case SCLK_MAC_REF: -+ rk_setreg(&cru->cru_clkgate_con[5], BIT(3)); -+ break; -+ case SCLK_MAC_REFOUT: -+ rk_setreg(&cru->cru_clkgate_con[5], BIT(4)); -+ break; -+ case SCLK_MAC_PHY: -+ rk_setreg(&cru->cru_clkgate_con[5], BIT(7)); -+ break; -+ case ACLK_GMAC: -+ rk_setreg(&cru->cru_clkgate_con[11], BIT(4)); -+ break; -+ case PCLK_GMAC: -+ rk_setreg(&cru->cru_clkgate_con[11], BIT(5)); -+ break; -+ default: -+ log_debug("%s: unsupported clk %ld\n", __func__, clk->id); -+ return -ENOENT; -+ } -+ -+ return 0; -+ -+} -+ - static struct clk_ops rk322x_clk_ops = { - .get_rate = rk322x_clk_get_rate, - .set_rate = rk322x_clk_set_rate, - .set_parent = rk322x_clk_set_parent, -+ .enable = rk322x_clk_enable, -+ .disable = rk322x_clk_disable - }; - - static int rk322x_clk_ofdata_to_platdata(struct udevice *dev) -diff --git a/drivers/phy/rockchip/phy-rockchip-inno-usb2.c b/drivers/phy/rockchip/phy-rockchip-inno-usb2.c -index c5ea6ca3..04caf292 100644 ---- a/drivers/phy/rockchip/phy-rockchip-inno-usb2.c -+++ b/drivers/phy/rockchip/phy-rockchip-inno-usb2.c -@@ -242,6 +242,67 @@ static int rockchip_usb2phy_bind(struct udevice *dev) - return ret; - } - -+static const struct rockchip_usb2phy_cfg rk3228_phy_cfgs[] = { -+ { -+ .reg = 0x760, -+ //.num_ports = 2, -+ //.clkout_ctl = { 0x0768, 4, 4, 1, 0 }, -+ .port_cfgs = { -+ [USB2PHY_PORT_OTG] = { -+ .phy_sus = { 0x0760, 15, 0, 0, 0x1d1 }, -+ .bvalid_det_en = { 0x0680, 3, 3, 0, 1 }, -+ .bvalid_det_st = { 0x0690, 3, 3, 0, 1 }, -+ .bvalid_det_clr = { 0x06a0, 3, 3, 0, 1 }, -+ .ls_det_en = { 0x0680, 2, 2, 0, 1 }, -+ .ls_det_st = { 0x0690, 2, 2, 0, 1 }, -+ .ls_det_clr = { 0x06a0, 2, 2, 0, 1 }, -+ .utmi_bvalid = { 0x0480, 4, 4, 0, 1 }, -+ .utmi_ls = { 0x0480, 3, 2, 0, 1 }, -+ }, -+ [USB2PHY_PORT_HOST] = { -+ .phy_sus = { 0x0764, 15, 0, 0, 0x1d1 }, -+ .ls_det_en = { 0x0680, 4, 4, 0, 1 }, -+ .ls_det_st = { 0x0690, 4, 4, 0, 1 }, -+ .ls_det_clr = { 0x06a0, 4, 4, 0, 1 } -+ } -+ }, -+ /* -+ .chg_det = { -+ .opmode = { 0x0760, 3, 0, 5, 1 }, -+ .cp_det = { 0x0884, 4, 4, 0, 1 }, -+ .dcp_det = { 0x0884, 3, 3, 0, 1 }, -+ .dp_det = { 0x0884, 5, 5, 0, 1 }, -+ .idm_sink_en = { 0x0768, 8, 8, 0, 1 }, -+ .idp_sink_en = { 0x0768, 7, 7, 0, 1 }, -+ .idp_src_en = { 0x0768, 9, 9, 0, 1 }, -+ .rdm_pdwn_en = { 0x0768, 10, 10, 0, 1 }, -+ .vdm_src_en = { 0x0768, 12, 12, 0, 1 }, -+ .vdp_src_en = { 0x0768, 11, 11, 0, 1 }, -+ }, -+ */ -+ }, -+ { -+ .reg = 0x800, -+ //.num_ports = 2, -+ //.clkout_ctl = { 0x0808, 4, 4, 1, 0 }, -+ .port_cfgs = { -+ [USB2PHY_PORT_OTG] = { -+ .phy_sus = { 0x800, 15, 0, 0, 0x1d1 }, -+ .ls_det_en = { 0x0684, 0, 0, 0, 1 }, -+ .ls_det_st = { 0x0694, 0, 0, 0, 1 }, -+ .ls_det_clr = { 0x06a4, 0, 0, 0, 1 } -+ }, -+ [USB2PHY_PORT_HOST] = { -+ .phy_sus = { 0x804, 15, 0, 0, 0x1d1 }, -+ .ls_det_en = { 0x0684, 1, 1, 0, 1 }, -+ .ls_det_st = { 0x0694, 1, 1, 0, 1 }, -+ .ls_det_clr = { 0x06a4, 1, 1, 0, 1 } -+ } -+ }, -+ }, -+ { /* sentinel */ } -+}; -+ - static const struct rockchip_usb2phy_cfg rk3399_usb2phy_cfgs[] = { - { - .reg = 0xe450, -@@ -293,6 +354,10 @@ static const struct udevice_id rockchip_usb2phy_ids[] = { - .compatible = "rockchip,rk3399-usb2phy", - .data = (ulong)&rk3399_usb2phy_cfgs, - }, -+ { -+ .compatible = "rockchip,rk3228-usb2phy", -+ .data = (ulong)&rk3228_phy_cfgs, -+ }, - { /* sentinel */ } - }; - -diff --git a/include/dt-bindings/clock/rk3228-cru.h b/include/dt-bindings/clock/rk3228-cru.h -index 1217d523..b6a25397 100644 ---- a/include/dt-bindings/clock/rk3228-cru.h -+++ b/include/dt-bindings/clock/rk3228-cru.h -@@ -51,6 +51,8 @@ - #define SCLK_MAC_TX 130 - #define SCLK_MAC_PHY 131 - #define SCLK_MAC_OUT 132 -+#define SCLK_OTGPHY0 142 -+#define SCLK_OTGPHY1 143 - - /* dclk gates */ - #define DCLK_VOP 190 -@@ -94,6 +96,10 @@ - #define HCLK_SDMMC 456 - #define HCLK_SDIO 457 - #define HCLK_EMMC 459 -+#define HCLK_HOST0 471 -+#define HCLK_HOST1 472 -+#define HCLK_HOST2 473 -+#define HCLK_OTG 474 - #define HCLK_PERI 478 - - #define CLK_NR_CLKS (HCLK_PERI + 1) diff --git a/patch/u-boot/v2024.01/board_rk322x-box/driver-rockchip-vop-cleanup.patch b/patch/u-boot/v2024.01/board_rk322x-box/driver-rockchip-vop-cleanup.patch deleted file mode 100644 index 98e73932879b..000000000000 --- a/patch/u-boot/v2024.01/board_rk322x-box/driver-rockchip-vop-cleanup.patch +++ /dev/null @@ -1,242 +0,0 @@ -From dc0ea12fdeb6843839ee1a182166bc2506fa0ec7 Mon Sep 17 00:00:00 2001 -From: Jagan Teki -Date: Sun, 19 Feb 2023 00:47:19 +0530 -Subject: [PATCH] video: rockchip: vop: Simplify rkvop_enable - -Signed-off-by: Jagan Teki ---- - drivers/video/rockchip/rk_vop.c | 8 ++++---- - 1 file changed, 4 insertions(+), 4 deletions(-) - -diff --git a/drivers/video/rockchip/rk_vop.c b/drivers/video/rockchip/rk_vop.c -index bc98ab6875a..7e8ce9b29aa 100644 ---- a/drivers/video/rockchip/rk_vop.c -+++ b/drivers/video/rockchip/rk_vop.c -@@ -39,11 +39,13 @@ enum vop_pol { - DCLK_INVERT = 3 - }; - --static void rkvop_enable(struct udevice *dev, struct rk3288_vop *regs, ulong fbbase, -+static void rkvop_enable(struct udevice *dev, ulong fbbase, - int fb_bits_per_pixel, - const struct display_timing *edid, - struct reset_ctl *dclk_rst) - { -+ struct rk_vop_priv *priv = dev_get_priv(dev); -+ struct rk3288_vop *regs = priv->regs; - u32 lb_mode; - u32 rgb_mode; - u32 hactive = edid->hactive.typ; -@@ -243,9 +245,7 @@ static void rkvop_mode_set(struct udevice *dev, - static int rk_display_init(struct udevice *dev, ulong fbbase, ofnode ep_node) - { - struct video_priv *uc_priv = dev_get_uclass_priv(dev); -- struct rk_vop_priv *priv = dev_get_priv(dev); - int vop_id, remote_vop_id; -- struct rk3288_vop *regs = priv->regs; - struct display_timing timing; - struct udevice *disp; - int ret; -@@ -379,7 +379,7 @@ static int rk_display_init(struct udevice *dev, ulong fbbase, ofnode ep_node) - return ret; - } - -- rkvop_enable(dev, regs, fbbase, 1 << l2bpp, &timing, &dclk_rst); -+ rkvop_enable(dev, fbbase, 1 << l2bpp, &timing, &dclk_rst); - - ret = display_enable(disp, 1 << l2bpp, &timing); - if (ret) -From a9b623a13c0c7ba8867875c0267deabd0fed733c Mon Sep 17 00:00:00 2001 -From: Jagan Teki -Date: Sun, 19 Feb 2023 00:53:06 +0530 -Subject: [PATCH] video: rockchip: vop: Add win offset support - -Signed-off-by: Jagan Teki ---- - drivers/video/rockchip/rk_vop.c | 23 ++++++++++++++--------- - drivers/video/rockchip/rk_vop.h | 2 ++ - 2 files changed, 16 insertions(+), 9 deletions(-) - -diff --git a/drivers/video/rockchip/rk_vop.c b/drivers/video/rockchip/rk_vop.c -index 7e8ce9b29aa..757fe7a4338 100644 ---- a/drivers/video/rockchip/rk_vop.c -+++ b/drivers/video/rockchip/rk_vop.c -@@ -46,6 +46,7 @@ static void rkvop_enable(struct udevice *dev, ulong fbbase, - { - struct rk_vop_priv *priv = dev_get_priv(dev); - struct rk3288_vop *regs = priv->regs; -+ struct rk3288_vop *win_regs = priv->regs + priv->win_offset; - u32 lb_mode; - u32 rgb_mode; - u32 hactive = edid->hactive.typ; -@@ -53,32 +54,33 @@ static void rkvop_enable(struct udevice *dev, ulong fbbase, - int ret; - - writel(V_ACT_WIDTH(hactive - 1) | V_ACT_HEIGHT(vactive - 1), -- ®s->win0_act_info); -+ &win_regs->win0_act_info); - - writel(V_DSP_XST(edid->hsync_len.typ + edid->hback_porch.typ) | - V_DSP_YST(edid->vsync_len.typ + edid->vback_porch.typ), -- ®s->win0_dsp_st); -+ &win_regs->win0_dsp_st); - - writel(V_DSP_WIDTH(hactive - 1) | - V_DSP_HEIGHT(vactive - 1), -- ®s->win0_dsp_info); -+ &win_regs->win0_dsp_info); - -- clrsetbits_le32(®s->win0_color_key, M_WIN0_KEY_EN | M_WIN0_KEY_COLOR, -+ clrsetbits_le32(&win_regs->win0_color_key, -+ M_WIN0_KEY_EN | M_WIN0_KEY_COLOR, - V_WIN0_KEY_EN(0) | V_WIN0_KEY_COLOR(0)); - - switch (fb_bits_per_pixel) { - case 16: - rgb_mode = RGB565; -- writel(V_RGB565_VIRWIDTH(hactive), ®s->win0_vir); -+ writel(V_RGB565_VIRWIDTH(hactive), &win_regs->win0_vir); - break; - case 24: - rgb_mode = RGB888; -- writel(V_RGB888_VIRWIDTH(hactive), ®s->win0_vir); -+ writel(V_RGB888_VIRWIDTH(hactive), &win_regs->win0_vir); - break; - case 32: - default: - rgb_mode = ARGB8888; -- writel(V_ARGB888_VIRWIDTH(hactive), ®s->win0_vir); -+ writel(V_ARGB888_VIRWIDTH(hactive), &win_regs->win0_vir); - break; - } - -@@ -91,12 +93,12 @@ static void rkvop_enable(struct udevice *dev, ulong fbbase, - else - lb_mode = LB_RGB_1280X8; - -- clrsetbits_le32(®s->win0_ctrl0, -+ clrsetbits_le32(&win_regs->win0_ctrl0, - M_WIN0_LB_MODE | M_WIN0_DATA_FMT | M_WIN0_EN, - V_WIN0_LB_MODE(lb_mode) | V_WIN0_DATA_FMT(rgb_mode) | - V_WIN0_EN(1)); - -- writel(fbbase, ®s->win0_yrgb_mst); -+ writel(fbbase, &win_regs->win0_yrgb_mst); - writel(0x01, ®s->reg_cfg_done); /* enable reg config */ - - ret = reset_assert(dclk_rst); -@@ -414,6 +416,8 @@ int rk_vop_probe(struct udevice *dev) - { - struct video_uc_plat *plat = dev_get_uclass_plat(dev); - struct rk_vop_priv *priv = dev_get_priv(dev); -+ struct rkvop_driverdata *ops = -+ (struct rkvop_driverdata *)dev_get_driver_data(dev); - int ret = 0; - ofnode port, node; - struct reset_ctl ahb_rst; -@@ -448,6 +453,8 @@ int rk_vop_probe(struct udevice *dev) - #endif - - priv->regs = dev_read_addr_ptr(dev); -+ priv->win_offset = ops->win_offset; -+ priv->dsp_offset = ops->dsp_offset; - - /* - * Try all the ports until we find one that works. In practice this -diff --git a/drivers/video/rockchip/rk_vop.h b/drivers/video/rockchip/rk_vop.h -index 0528fb23f59..909f5602e53 100644 ---- a/drivers/video/rockchip/rk_vop.h -+++ b/drivers/video/rockchip/rk_vop.h -@@ -11,6 +11,7 @@ - struct rk_vop_priv { - void *grf; - void *regs; -+ int win_offset; - }; - - enum vop_features { -@@ -18,6 +19,7 @@ enum vop_features { - }; - - struct rkvop_driverdata { -+ int win_offset; - /* configuration */ - u32 features; - /* block-specific setters/getters */ -From cd5115979e60d360e546ea683e77209e2011e752 Mon Sep 17 00:00:00 2001 -From: Jagan Teki -Date: Mon, 20 Feb 2023 00:52:32 +0530 -Subject: [PATCH] video: rockchip: vop: Add dsp offset support - -Signed-off-by: Jagan Teki ---- - drivers/video/rockchip/rk_vop.c | 14 ++++++++------ - drivers/video/rockchip/rk_vop.h | 2 ++ - 2 files changed, 10 insertions(+), 6 deletions(-) - -diff --git a/drivers/video/rockchip/rk_vop.c b/drivers/video/rockchip/rk_vop.c -index 757fe7a4338..f7c6b4cc25a 100644 ---- a/drivers/video/rockchip/rk_vop.c -+++ b/drivers/video/rockchip/rk_vop.c -@@ -166,6 +166,7 @@ static void rkvop_mode_set(struct udevice *dev, - { - struct rk_vop_priv *priv = dev_get_priv(dev); - struct rk3288_vop *regs = priv->regs; -+ struct rk3288_vop *dsp_regs = priv->regs + priv->dsp_offset; - struct rkvop_driverdata *data = - (struct rkvop_driverdata *)dev_get_driver_data(dev); - -@@ -199,27 +200,27 @@ static void rkvop_mode_set(struct udevice *dev, - - writel(V_HSYNC(hsync_len) | - V_HORPRD(hsync_len + hback_porch + hactive + hfront_porch), -- ®s->dsp_htotal_hs_end); -+ &dsp_regs->dsp_htotal_hs_end); - - writel(V_HEAP(hsync_len + hback_porch + hactive) | - V_HASP(hsync_len + hback_porch), -- ®s->dsp_hact_st_end); -+ &dsp_regs->dsp_hact_st_end); - - writel(V_VSYNC(vsync_len) | - V_VERPRD(vsync_len + vback_porch + vactive + vfront_porch), -- ®s->dsp_vtotal_vs_end); -+ &dsp_regs->dsp_vtotal_vs_end); - - writel(V_VAEP(vsync_len + vback_porch + vactive)| - V_VASP(vsync_len + vback_porch), -- ®s->dsp_vact_st_end); -+ &dsp_regs->dsp_vact_st_end); - - writel(V_HEAP(hsync_len + hback_porch + hactive) | - V_HASP(hsync_len + hback_porch), -- ®s->post_dsp_hact_info); -+ &dsp_regs->post_dsp_hact_info); - - writel(V_VAEP(vsync_len + vback_porch + vactive)| - V_VASP(vsync_len + vback_porch), -- ®s->post_dsp_vact_info); -+ &dsp_regs->post_dsp_vact_info); - - writel(0x01, ®s->reg_cfg_done); /* enable reg config */ - } -diff --git a/drivers/video/rockchip/rk_vop.h b/drivers/video/rockchip/rk_vop.h -index 909f5602e53..7d2581d6a78 100644 ---- a/drivers/video/rockchip/rk_vop.h -+++ b/drivers/video/rockchip/rk_vop.h -@@ -11,6 +11,7 @@ - struct rk_vop_priv { - void *grf; - void *regs; -+ int dsp_offset; - int win_offset; - }; - -@@ -19,6 +20,7 @@ enum vop_features { - }; - - struct rkvop_driverdata { -+ int dsp_offset; - int win_offset; - /* configuration */ - u32 features; diff --git a/patch/u-boot/v2024.01/board_rk322x-box/general-hdmi-01-vendor-phy-handling.patch b/patch/u-boot/v2024.01/board_rk322x-box/general-hdmi-01-vendor-phy-handling.patch deleted file mode 100644 index 78122ce819f3..000000000000 --- a/patch/u-boot/v2024.01/board_rk322x-box/general-hdmi-01-vendor-phy-handling.patch +++ /dev/null @@ -1,239 +0,0 @@ -From db428dbc58ba2788fb13d4bf1985f0540fd7f4b3 Mon Sep 17 00:00:00 2001 -From: Paolo Sabatino -Date: Tue, 30 Apr 2024 22:09:57 +0200 -Subject: [PATCH] video: dw_hdmi: Add Vendor PHY handling - -original work by Jagan Teki ---- - drivers/video/dw_hdmi.c | 46 +++++++++++++++++++++++++++- - drivers/video/meson/meson_dw_hdmi.c | 11 ++++++- - drivers/video/rockchip/rk3399_hdmi.c | 8 ++++- - drivers/video/rockchip/rk_hdmi.c | 2 +- - drivers/video/rockchip/rk_hdmi.h | 3 ++ - drivers/video/sunxi/sunxi_dw_hdmi.c | 11 ++++++- - include/dw_hdmi.h | 14 ++++++++- - 7 files changed, 89 insertions(+), 6 deletions(-) - -diff --git a/drivers/video/dw_hdmi.c b/drivers/video/dw_hdmi.c -index c4fbb18294..fc8c8bb366 100644 ---- a/drivers/video/dw_hdmi.c -+++ b/drivers/video/dw_hdmi.c -@@ -988,7 +988,7 @@ int dw_hdmi_enable(struct dw_hdmi *hdmi, const struct display_timing *edid) - - hdmi_av_composer(hdmi, edid); - -- ret = hdmi->phy_set(hdmi, edid->pixelclock.typ); -+ ret = hdmi->ops->phy_set(hdmi, edid->pixelclock.typ); - if (ret) - return ret; - -@@ -1009,10 +1009,54 @@ int dw_hdmi_enable(struct dw_hdmi *hdmi, const struct display_timing *edid) - return 0; - } - -+static const struct dw_hdmi_phy_ops dw_hdmi_synopsys_phy_ops = { -+ .phy_set = dw_hdmi_phy_cfg, -+}; -+ -+static void dw_hdmi_detect_phy(struct dw_hdmi *hdmi) -+{ -+ if (!hdmi->data) -+ return; -+ -+ /* hook Synopsys PHYs ops */ -+ if (!hdmi->data->phy_force_vendor) { -+ hdmi->ops = &dw_hdmi_synopsys_phy_ops; -+ return; -+ } -+ -+ /* Vendor HDMI PHYs must assign phy_ops in plat_data */ -+ if (!hdmi->data->phy_ops) { -+ printf("Unsupported Vendor HDMI phy_ops\n"); -+ return; -+ } -+ -+ /* hook Vendor HDMI PHYs ops */ -+ hdmi->ops = hdmi->data->phy_ops; -+} -+ -+int dw_hdmi_disable(struct dw_hdmi *hdmi) -+{ -+ uint clkdis; -+ -+ /* disable pixel clock and tmds data path */ -+ clkdis = 0x7f; -+ hdmi_write(hdmi, clkdis, HDMI_MC_CLKDIS); -+ -+ /* disable phy */ -+ hdmi_phy_sel_interface_control(hdmi, 0); -+ hdmi_phy_enable_tmds(hdmi, 0); -+ hdmi_phy_enable_power(hdmi, 0); -+ -+ return 0; -+ -+} -+ - void dw_hdmi_init(struct dw_hdmi *hdmi) - { - uint ih_mute; - -+ dw_hdmi_detect_phy(hdmi); -+ - /* - * boot up defaults are: - * hdmi_ih_mute = 0x03 (disabled) -diff --git a/drivers/video/meson/meson_dw_hdmi.c b/drivers/video/meson/meson_dw_hdmi.c -index 5db01904b5..d0d878b6af 100644 ---- a/drivers/video/meson/meson_dw_hdmi.c -+++ b/drivers/video/meson/meson_dw_hdmi.c -@@ -375,6 +375,15 @@ static int meson_dw_hdmi_wait_hpd(struct dw_hdmi *hdmi) - return -ETIMEDOUT; - } - -+static const struct dw_hdmi_phy_ops dw_hdmi_meson_phy_ops = { -+ .phy_set = meson_dw_hdmi_phy_init, -+}; -+ -+static const struct dw_hdmi_plat_data dw_hdmi_meson_plat_data = { -+ .phy_force_vendor = true, -+ .phy_ops = &dw_hdmi_meson_phy_ops, -+}; -+ - static int meson_dw_hdmi_probe(struct udevice *dev) - { - struct meson_dw_hdmi *priv = dev_get_priv(dev); -@@ -397,7 +406,7 @@ static int meson_dw_hdmi_probe(struct udevice *dev) - - priv->hdmi.hdmi_data.enc_out_bus_format = MEDIA_BUS_FMT_RGB888_1X24; - priv->hdmi.hdmi_data.enc_in_bus_format = MEDIA_BUS_FMT_YUV8_1X24; -- priv->hdmi.phy_set = meson_dw_hdmi_phy_init; -+ priv->hdmi.data = &dw_hdmi_meson_plat_data; - if (meson_hdmi_is_compatible(priv, HDMI_COMPATIBLE_G12A)) - priv->hdmi.reg_io_width = 1; - else { -diff --git a/drivers/video/rockchip/rk3399_hdmi.c b/drivers/video/rockchip/rk3399_hdmi.c -index 3041360c6e..b32139a8a6 100644 ---- a/drivers/video/rockchip/rk3399_hdmi.c -+++ b/drivers/video/rockchip/rk3399_hdmi.c -@@ -64,8 +64,14 @@ static const struct dm_display_ops rk3399_hdmi_ops = { - .enable = rk3399_hdmi_enable, - }; - -+static const struct dw_hdmi_plat_data rk3399_hdmi_drv_data = { -+}; -+ - static const struct udevice_id rk3399_hdmi_ids[] = { -- { .compatible = "rockchip,rk3399-dw-hdmi" }, -+ { -+ .compatible = "rockchip,rk3399-dw-hdmi", -+ .data = (ulong)&rk3399_hdmi_drv_data -+ }, - { } - }; - -diff --git a/drivers/video/rockchip/rk_hdmi.c b/drivers/video/rockchip/rk_hdmi.c -index 8dcd4d5964..e545d69e3b 100644 ---- a/drivers/video/rockchip/rk_hdmi.c -+++ b/drivers/video/rockchip/rk_hdmi.c -@@ -83,6 +83,7 @@ int rk_hdmi_of_to_plat(struct udevice *dev) - struct rk_hdmi_priv *priv = dev_get_priv(dev); - struct dw_hdmi *hdmi = &priv->hdmi; - -+ hdmi->data = (const struct dw_hdmi_plat_data *)dev_get_driver_data(dev); - hdmi->ioaddr = (ulong)dev_read_addr(dev); - hdmi->mpll_cfg = rockchip_mpll_cfg; - hdmi->phy_cfg = rockchip_phy_config; -@@ -90,7 +91,6 @@ int rk_hdmi_of_to_plat(struct udevice *dev) - /* hdmi->i2c_clk_{high,low} are set up by the SoC driver */ - - hdmi->reg_io_width = 4; -- hdmi->phy_set = dw_hdmi_phy_cfg; - - priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); - -diff --git a/drivers/video/rockchip/rk_hdmi.h b/drivers/video/rockchip/rk_hdmi.h -index 200dbaea74..dcfba3d3d7 100644 ---- a/drivers/video/rockchip/rk_hdmi.h -+++ b/drivers/video/rockchip/rk_hdmi.h -@@ -6,6 +6,8 @@ - #ifndef __RK_HDMI_H__ - #define __RK_HDMI_H__ - -+#include -+ - struct rkhdmi_driverdata { - /* configuration */ - u8 i2c_clk_high; -@@ -19,6 +21,7 @@ struct rkhdmi_driverdata { - - struct rk_hdmi_priv { - struct dw_hdmi hdmi; -+ struct phy phy; - void *grf; - }; - -diff --git a/drivers/video/sunxi/sunxi_dw_hdmi.c b/drivers/video/sunxi/sunxi_dw_hdmi.c -index 0324a050d0..f7ecbb923b 100644 ---- a/drivers/video/sunxi/sunxi_dw_hdmi.c -+++ b/drivers/video/sunxi/sunxi_dw_hdmi.c -@@ -328,6 +328,15 @@ static int sunxi_dw_hdmi_enable(struct udevice *dev, int panel_bpp, - return 0; - } - -+static const struct dw_hdmi_phy_ops dw_hdmi_sunxi_phy_ops = { -+ .phy_set = sunxi_dw_hdmi_phy_cfg, -+}; -+ -+static const struct dw_hdmi_plat_data dw_hdmi_sunxi_plat_data = { -+ .phy_force_vendor = true, -+ .phy_ops = &dw_hdmi_sunxi_phy_ops, -+}; -+ - static int sunxi_dw_hdmi_probe(struct udevice *dev) - { - struct sunxi_dw_hdmi_priv *priv = dev_get_priv(dev); -@@ -379,7 +388,7 @@ static int sunxi_dw_hdmi_of_to_plat(struct udevice *dev) - hdmi->i2c_clk_high = 0xd8; - hdmi->i2c_clk_low = 0xfe; - hdmi->reg_io_width = 1; -- hdmi->phy_set = sunxi_dw_hdmi_phy_cfg; -+ hdmi->data = &dw_hdmi_sunxi_plat_data; - - ret = reset_get_bulk(dev, &priv->resets); - if (ret) -diff --git a/include/dw_hdmi.h b/include/dw_hdmi.h -index 8acae3839f..4ad8b39f84 100644 ---- a/include/dw_hdmi.h -+++ b/include/dw_hdmi.h -@@ -534,6 +534,17 @@ struct hdmi_data_info { - struct hdmi_vmode video_mode; - }; - -+struct dw_hdmi; -+ -+struct dw_hdmi_phy_ops { -+ int (*phy_set)(struct dw_hdmi *hdmi, uint mpixelclock); -+}; -+ -+struct dw_hdmi_plat_data { -+ bool phy_force_vendor; -+ const struct dw_hdmi_phy_ops *phy_ops; -+}; -+ - struct dw_hdmi { - ulong ioaddr; - const struct hdmi_mpll_config *mpll_cfg; -@@ -543,8 +554,9 @@ struct dw_hdmi { - u8 reg_io_width; - struct hdmi_data_info hdmi_data; - struct udevice *ddc_bus; -+ const struct dw_hdmi_phy_ops *ops; -+ const struct dw_hdmi_plat_data *data; - -- int (*phy_set)(struct dw_hdmi *hdmi, uint mpixelclock); - void (*write_reg)(struct dw_hdmi *hdmi, u8 val, int offset); - u8 (*read_reg)(struct dw_hdmi *hdmi, int offset); - }; --- -2.34.1 - diff --git a/patch/u-boot/v2024.01/board_rk322x-box/general-hdmi-02-hpd-cleanup.patch b/patch/u-boot/v2024.01/board_rk322x-box/general-hdmi-02-hpd-cleanup.patch deleted file mode 100644 index 8c4500750638..000000000000 --- a/patch/u-boot/v2024.01/board_rk322x-box/general-hdmi-02-hpd-cleanup.patch +++ /dev/null @@ -1,193 +0,0 @@ -From d2804380b05b4e8e6557ce7239a1680853dd5258 Mon Sep 17 00:00:00 2001 -From: Jagan Teki -Date: Sat, 18 Feb 2023 00:30:30 +0530 -Subject: [PATCH] video: rockchip: hdmi: Detect hpd after controller init - -Signed-off-by: Jagan Teki ---- - drivers/video/rockchip/rk_hdmi.c | 6 +++--- - 1 file changed, 3 insertions(+), 3 deletions(-) - -diff --git a/drivers/video/rockchip/rk_hdmi.c b/drivers/video/rockchip/rk_hdmi.c -index 8dcd4d59645..b75a1744896 100644 ---- a/drivers/video/rockchip/rk_hdmi.c -+++ b/drivers/video/rockchip/rk_hdmi.c -@@ -112,14 +112,14 @@ int rk_hdmi_probe(struct udevice *dev) - struct dw_hdmi *hdmi = &priv->hdmi; - int ret; - -+ dw_hdmi_init(hdmi); -+ dw_hdmi_phy_init(hdmi); -+ - ret = dw_hdmi_phy_wait_for_hpd(hdmi); - if (ret < 0) { - debug("hdmi can not get hpd signal\n"); - return -1; - } - -- dw_hdmi_init(hdmi); -- dw_hdmi_phy_init(hdmi); -- - return 0; - } -From 3569108607b8569c16aa5df540cf35db2bf58b05 Mon Sep 17 00:00:00 2001 -From: Jagan Teki -Date: Sun, 19 Feb 2023 00:20:52 +0530 -Subject: [PATCH] video: dw_hdmi: Simplify HPD detection - -Signed-off-by: Jagan Teki ---- - drivers/video/dw_hdmi.c | 13 +++++++++++++ - drivers/video/rockchip/rk_hdmi.c | 8 +++----- - drivers/video/sunxi/sunxi_dw_hdmi.c | 8 +++----- - include/dw_hdmi.h | 1 + - 4 files changed, 20 insertions(+), 10 deletions(-) - -diff --git a/drivers/video/dw_hdmi.c b/drivers/video/dw_hdmi.c -index ea12a094074..0a597206f06 100644 ---- a/drivers/video/dw_hdmi.c -+++ b/drivers/video/dw_hdmi.c -@@ -936,6 +936,19 @@ int dw_hdmi_phy_wait_for_hpd(struct dw_hdmi *hdmi) - return -1; - } - -+int dw_hdmi_detect_hpd(struct dw_hdmi *hdmi) -+{ -+ int ret; -+ -+ ret = dw_hdmi_phy_wait_for_hpd(hdmi); -+ if (ret < 0) { -+ debug("hdmi can not get hpd signal\n"); -+ return -ENODEV; -+ } -+ -+ return 0; -+} -+ - void dw_hdmi_phy_init(struct dw_hdmi *hdmi) - { - /* enable phy i2cm done irq */ -diff --git a/drivers/video/rockchip/rk_hdmi.c b/drivers/video/rockchip/rk_hdmi.c -index e34f532cd68..8a65f2440e4 100644 ---- a/drivers/video/rockchip/rk_hdmi.c -+++ b/drivers/video/rockchip/rk_hdmi.c -@@ -115,11 +115,9 @@ int rk_hdmi_probe(struct udevice *dev) - dw_hdmi_init(hdmi); - dw_hdmi_phy_init(hdmi); - -- ret = dw_hdmi_phy_wait_for_hpd(hdmi); -- if (ret < 0) { -- debug("hdmi can not get hpd signal\n"); -- return -1; -- } -+ ret = dw_hdmi_detect_hpd(hdmi); -+ if (ret < 0) -+ return ret; - - return 0; - } -diff --git a/drivers/video/sunxi/sunxi_dw_hdmi.c b/drivers/video/sunxi/sunxi_dw_hdmi.c -index 46ad9d137b1..6738950fd00 100644 ---- a/drivers/video/sunxi/sunxi_dw_hdmi.c -+++ b/drivers/video/sunxi/sunxi_dw_hdmi.c -@@ -347,11 +347,9 @@ static int sunxi_dw_hdmi_probe(struct udevice *dev) - - sunxi_dw_hdmi_phy_init(&priv->hdmi); - -- ret = dw_hdmi_phy_wait_for_hpd(&priv->hdmi); -- if (ret < 0) { -- debug("hdmi can not get hpd signal\n"); -- return -1; -- } -+ ret = dw_hdmi_detect_hpd(&priv->hdmi); -+ if (ret < 0) -+ return ret; - - dw_hdmi_init(&priv->hdmi); - -diff --git a/include/dw_hdmi.h b/include/dw_hdmi.h -index 4ad8b39f84d..756560e0928 100644 ---- a/include/dw_hdmi.h -+++ b/include/dw_hdmi.h -@@ -554,7 +568,9 @@ int dw_hdmi_phy_wait_for_hpd(struct dw_hdmi *hdmi); - void dw_hdmi_phy_init(struct dw_hdmi *hdmi); - - int dw_hdmi_enable(struct dw_hdmi *hdmi, const struct display_timing *edid); -+int dw_hdmi_disable(struct dw_hdmi *hdmi); - int dw_hdmi_read_edid(struct dw_hdmi *hdmi, u8 *buf, int buf_size); - void dw_hdmi_init(struct dw_hdmi *hdmi); -+int dw_hdmi_detect_hpd(struct dw_hdmi *hdmi); - - #endif -From 89431ed902443d0c62e88ca71ac31059c413b4bf Mon Sep 17 00:00:00 2001 -From: Jagan Teki -Date: Sun, 19 Feb 2023 00:30:37 +0530 -Subject: [PATCH] video: dw_hdmi: Add read_hpd hook - -Signed-off-by: Jagan Teki ---- - drivers/video/dw_hdmi.c | 3 +++ - include/dw_hdmi.h | 1 + - 2 files changed, 4 insertions(+) - -diff --git a/drivers/video/dw_hdmi.c b/drivers/video/dw_hdmi.c -index 0a597206f06..172e6b45a60 100644 ---- a/drivers/video/dw_hdmi.c -+++ b/drivers/video/dw_hdmi.c -@@ -946,6 +946,9 @@ int dw_hdmi_detect_hpd(struct dw_hdmi *hdmi) - return -ENODEV; - } - -+ if (hdmi->ops->read_hpd) -+ hdmi->ops->read_hpd(hdmi, true); -+ - return 0; - } - -diff --git a/include/dw_hdmi.h b/include/dw_hdmi.h -index 756560e0928..d6de472cee8 100644 ---- a/include/dw_hdmi.h -+++ b/include/dw_hdmi.h -@@ -538,6 +538,7 @@ struct dw_hdmi; - - struct dw_hdmi_phy_ops { - int (*phy_set)(struct dw_hdmi *hdmi, uint mpixelclock); -+ void (*read_hpd)(struct dw_hdmi *hdmi, bool hdp_status); - }; - - struct dw_hdmi_plat_data { -From 40405cb1924f60ff27923d5d11e6558117ced815 Mon Sep 17 00:00:00 2001 -From: Jagan Teki -Date: Sun, 19 Feb 2023 00:33:18 +0530 -Subject: [PATCH] video: dw_hdmi: Add setup_hpd hook - -Signed-off-by: Jagan Teki ---- - drivers/video/dw_hdmi.c | 3 +++ - include/dw_hdmi.h | 1 + - 2 files changed, 4 insertions(+) - -diff --git a/drivers/video/dw_hdmi.c b/drivers/video/dw_hdmi.c -index 172e6b45a60..3e0e20e59ba 100644 ---- a/drivers/video/dw_hdmi.c -+++ b/drivers/video/dw_hdmi.c -@@ -1080,4 +1080,7 @@ void dw_hdmi_init(struct dw_hdmi *hdmi) - - /* enable i2c client nack % arbitration error irq */ - hdmi_write(hdmi, ~0x44, HDMI_I2CM_CTLINT); -+ -+ if (hdmi->ops->setup_hpd) -+ hdmi->ops->setup_hpd(hdmi); - } -diff --git a/include/dw_hdmi.h b/include/dw_hdmi.h -index d6de472cee8..9a44b9e90c3 100644 ---- a/include/dw_hdmi.h -+++ b/include/dw_hdmi.h -@@ -539,6 +539,7 @@ struct dw_hdmi; - struct dw_hdmi_phy_ops { - int (*phy_set)(struct dw_hdmi *hdmi, uint mpixelclock); - void (*read_hpd)(struct dw_hdmi *hdmi, bool hdp_status); -+ void (*setup_hpd)(struct dw_hdmi *hdmi); - }; - - struct dw_hdmi_plat_data { diff --git a/patch/u-boot/v2024.01/board_rk3318-box/driver-rockchip-vop-cleanup.patch b/patch/u-boot/v2024.01/board_rk3318-box/driver-rockchip-vop-cleanup.patch deleted file mode 100644 index 98e73932879b..000000000000 --- a/patch/u-boot/v2024.01/board_rk3318-box/driver-rockchip-vop-cleanup.patch +++ /dev/null @@ -1,242 +0,0 @@ -From dc0ea12fdeb6843839ee1a182166bc2506fa0ec7 Mon Sep 17 00:00:00 2001 -From: Jagan Teki -Date: Sun, 19 Feb 2023 00:47:19 +0530 -Subject: [PATCH] video: rockchip: vop: Simplify rkvop_enable - -Signed-off-by: Jagan Teki ---- - drivers/video/rockchip/rk_vop.c | 8 ++++---- - 1 file changed, 4 insertions(+), 4 deletions(-) - -diff --git a/drivers/video/rockchip/rk_vop.c b/drivers/video/rockchip/rk_vop.c -index bc98ab6875a..7e8ce9b29aa 100644 ---- a/drivers/video/rockchip/rk_vop.c -+++ b/drivers/video/rockchip/rk_vop.c -@@ -39,11 +39,13 @@ enum vop_pol { - DCLK_INVERT = 3 - }; - --static void rkvop_enable(struct udevice *dev, struct rk3288_vop *regs, ulong fbbase, -+static void rkvop_enable(struct udevice *dev, ulong fbbase, - int fb_bits_per_pixel, - const struct display_timing *edid, - struct reset_ctl *dclk_rst) - { -+ struct rk_vop_priv *priv = dev_get_priv(dev); -+ struct rk3288_vop *regs = priv->regs; - u32 lb_mode; - u32 rgb_mode; - u32 hactive = edid->hactive.typ; -@@ -243,9 +245,7 @@ static void rkvop_mode_set(struct udevice *dev, - static int rk_display_init(struct udevice *dev, ulong fbbase, ofnode ep_node) - { - struct video_priv *uc_priv = dev_get_uclass_priv(dev); -- struct rk_vop_priv *priv = dev_get_priv(dev); - int vop_id, remote_vop_id; -- struct rk3288_vop *regs = priv->regs; - struct display_timing timing; - struct udevice *disp; - int ret; -@@ -379,7 +379,7 @@ static int rk_display_init(struct udevice *dev, ulong fbbase, ofnode ep_node) - return ret; - } - -- rkvop_enable(dev, regs, fbbase, 1 << l2bpp, &timing, &dclk_rst); -+ rkvop_enable(dev, fbbase, 1 << l2bpp, &timing, &dclk_rst); - - ret = display_enable(disp, 1 << l2bpp, &timing); - if (ret) -From a9b623a13c0c7ba8867875c0267deabd0fed733c Mon Sep 17 00:00:00 2001 -From: Jagan Teki -Date: Sun, 19 Feb 2023 00:53:06 +0530 -Subject: [PATCH] video: rockchip: vop: Add win offset support - -Signed-off-by: Jagan Teki ---- - drivers/video/rockchip/rk_vop.c | 23 ++++++++++++++--------- - drivers/video/rockchip/rk_vop.h | 2 ++ - 2 files changed, 16 insertions(+), 9 deletions(-) - -diff --git a/drivers/video/rockchip/rk_vop.c b/drivers/video/rockchip/rk_vop.c -index 7e8ce9b29aa..757fe7a4338 100644 ---- a/drivers/video/rockchip/rk_vop.c -+++ b/drivers/video/rockchip/rk_vop.c -@@ -46,6 +46,7 @@ static void rkvop_enable(struct udevice *dev, ulong fbbase, - { - struct rk_vop_priv *priv = dev_get_priv(dev); - struct rk3288_vop *regs = priv->regs; -+ struct rk3288_vop *win_regs = priv->regs + priv->win_offset; - u32 lb_mode; - u32 rgb_mode; - u32 hactive = edid->hactive.typ; -@@ -53,32 +54,33 @@ static void rkvop_enable(struct udevice *dev, ulong fbbase, - int ret; - - writel(V_ACT_WIDTH(hactive - 1) | V_ACT_HEIGHT(vactive - 1), -- ®s->win0_act_info); -+ &win_regs->win0_act_info); - - writel(V_DSP_XST(edid->hsync_len.typ + edid->hback_porch.typ) | - V_DSP_YST(edid->vsync_len.typ + edid->vback_porch.typ), -- ®s->win0_dsp_st); -+ &win_regs->win0_dsp_st); - - writel(V_DSP_WIDTH(hactive - 1) | - V_DSP_HEIGHT(vactive - 1), -- ®s->win0_dsp_info); -+ &win_regs->win0_dsp_info); - -- clrsetbits_le32(®s->win0_color_key, M_WIN0_KEY_EN | M_WIN0_KEY_COLOR, -+ clrsetbits_le32(&win_regs->win0_color_key, -+ M_WIN0_KEY_EN | M_WIN0_KEY_COLOR, - V_WIN0_KEY_EN(0) | V_WIN0_KEY_COLOR(0)); - - switch (fb_bits_per_pixel) { - case 16: - rgb_mode = RGB565; -- writel(V_RGB565_VIRWIDTH(hactive), ®s->win0_vir); -+ writel(V_RGB565_VIRWIDTH(hactive), &win_regs->win0_vir); - break; - case 24: - rgb_mode = RGB888; -- writel(V_RGB888_VIRWIDTH(hactive), ®s->win0_vir); -+ writel(V_RGB888_VIRWIDTH(hactive), &win_regs->win0_vir); - break; - case 32: - default: - rgb_mode = ARGB8888; -- writel(V_ARGB888_VIRWIDTH(hactive), ®s->win0_vir); -+ writel(V_ARGB888_VIRWIDTH(hactive), &win_regs->win0_vir); - break; - } - -@@ -91,12 +93,12 @@ static void rkvop_enable(struct udevice *dev, ulong fbbase, - else - lb_mode = LB_RGB_1280X8; - -- clrsetbits_le32(®s->win0_ctrl0, -+ clrsetbits_le32(&win_regs->win0_ctrl0, - M_WIN0_LB_MODE | M_WIN0_DATA_FMT | M_WIN0_EN, - V_WIN0_LB_MODE(lb_mode) | V_WIN0_DATA_FMT(rgb_mode) | - V_WIN0_EN(1)); - -- writel(fbbase, ®s->win0_yrgb_mst); -+ writel(fbbase, &win_regs->win0_yrgb_mst); - writel(0x01, ®s->reg_cfg_done); /* enable reg config */ - - ret = reset_assert(dclk_rst); -@@ -414,6 +416,8 @@ int rk_vop_probe(struct udevice *dev) - { - struct video_uc_plat *plat = dev_get_uclass_plat(dev); - struct rk_vop_priv *priv = dev_get_priv(dev); -+ struct rkvop_driverdata *ops = -+ (struct rkvop_driverdata *)dev_get_driver_data(dev); - int ret = 0; - ofnode port, node; - struct reset_ctl ahb_rst; -@@ -448,6 +453,8 @@ int rk_vop_probe(struct udevice *dev) - #endif - - priv->regs = dev_read_addr_ptr(dev); -+ priv->win_offset = ops->win_offset; -+ priv->dsp_offset = ops->dsp_offset; - - /* - * Try all the ports until we find one that works. In practice this -diff --git a/drivers/video/rockchip/rk_vop.h b/drivers/video/rockchip/rk_vop.h -index 0528fb23f59..909f5602e53 100644 ---- a/drivers/video/rockchip/rk_vop.h -+++ b/drivers/video/rockchip/rk_vop.h -@@ -11,6 +11,7 @@ - struct rk_vop_priv { - void *grf; - void *regs; -+ int win_offset; - }; - - enum vop_features { -@@ -18,6 +19,7 @@ enum vop_features { - }; - - struct rkvop_driverdata { -+ int win_offset; - /* configuration */ - u32 features; - /* block-specific setters/getters */ -From cd5115979e60d360e546ea683e77209e2011e752 Mon Sep 17 00:00:00 2001 -From: Jagan Teki -Date: Mon, 20 Feb 2023 00:52:32 +0530 -Subject: [PATCH] video: rockchip: vop: Add dsp offset support - -Signed-off-by: Jagan Teki ---- - drivers/video/rockchip/rk_vop.c | 14 ++++++++------ - drivers/video/rockchip/rk_vop.h | 2 ++ - 2 files changed, 10 insertions(+), 6 deletions(-) - -diff --git a/drivers/video/rockchip/rk_vop.c b/drivers/video/rockchip/rk_vop.c -index 757fe7a4338..f7c6b4cc25a 100644 ---- a/drivers/video/rockchip/rk_vop.c -+++ b/drivers/video/rockchip/rk_vop.c -@@ -166,6 +166,7 @@ static void rkvop_mode_set(struct udevice *dev, - { - struct rk_vop_priv *priv = dev_get_priv(dev); - struct rk3288_vop *regs = priv->regs; -+ struct rk3288_vop *dsp_regs = priv->regs + priv->dsp_offset; - struct rkvop_driverdata *data = - (struct rkvop_driverdata *)dev_get_driver_data(dev); - -@@ -199,27 +200,27 @@ static void rkvop_mode_set(struct udevice *dev, - - writel(V_HSYNC(hsync_len) | - V_HORPRD(hsync_len + hback_porch + hactive + hfront_porch), -- ®s->dsp_htotal_hs_end); -+ &dsp_regs->dsp_htotal_hs_end); - - writel(V_HEAP(hsync_len + hback_porch + hactive) | - V_HASP(hsync_len + hback_porch), -- ®s->dsp_hact_st_end); -+ &dsp_regs->dsp_hact_st_end); - - writel(V_VSYNC(vsync_len) | - V_VERPRD(vsync_len + vback_porch + vactive + vfront_porch), -- ®s->dsp_vtotal_vs_end); -+ &dsp_regs->dsp_vtotal_vs_end); - - writel(V_VAEP(vsync_len + vback_porch + vactive)| - V_VASP(vsync_len + vback_porch), -- ®s->dsp_vact_st_end); -+ &dsp_regs->dsp_vact_st_end); - - writel(V_HEAP(hsync_len + hback_porch + hactive) | - V_HASP(hsync_len + hback_porch), -- ®s->post_dsp_hact_info); -+ &dsp_regs->post_dsp_hact_info); - - writel(V_VAEP(vsync_len + vback_porch + vactive)| - V_VASP(vsync_len + vback_porch), -- ®s->post_dsp_vact_info); -+ &dsp_regs->post_dsp_vact_info); - - writel(0x01, ®s->reg_cfg_done); /* enable reg config */ - } -diff --git a/drivers/video/rockchip/rk_vop.h b/drivers/video/rockchip/rk_vop.h -index 909f5602e53..7d2581d6a78 100644 ---- a/drivers/video/rockchip/rk_vop.h -+++ b/drivers/video/rockchip/rk_vop.h -@@ -11,6 +11,7 @@ - struct rk_vop_priv { - void *grf; - void *regs; -+ int dsp_offset; - int win_offset; - }; - -@@ -19,6 +20,7 @@ enum vop_features { - }; - - struct rkvop_driverdata { -+ int dsp_offset; - int win_offset; - /* configuration */ - u32 features; diff --git a/patch/u-boot/v2024.01/board_rk3318-box/general-hdmi-01-vendor-phy-handling.patch b/patch/u-boot/v2024.01/board_rk3318-box/general-hdmi-01-vendor-phy-handling.patch deleted file mode 100644 index 78122ce819f3..000000000000 --- a/patch/u-boot/v2024.01/board_rk3318-box/general-hdmi-01-vendor-phy-handling.patch +++ /dev/null @@ -1,239 +0,0 @@ -From db428dbc58ba2788fb13d4bf1985f0540fd7f4b3 Mon Sep 17 00:00:00 2001 -From: Paolo Sabatino -Date: Tue, 30 Apr 2024 22:09:57 +0200 -Subject: [PATCH] video: dw_hdmi: Add Vendor PHY handling - -original work by Jagan Teki ---- - drivers/video/dw_hdmi.c | 46 +++++++++++++++++++++++++++- - drivers/video/meson/meson_dw_hdmi.c | 11 ++++++- - drivers/video/rockchip/rk3399_hdmi.c | 8 ++++- - drivers/video/rockchip/rk_hdmi.c | 2 +- - drivers/video/rockchip/rk_hdmi.h | 3 ++ - drivers/video/sunxi/sunxi_dw_hdmi.c | 11 ++++++- - include/dw_hdmi.h | 14 ++++++++- - 7 files changed, 89 insertions(+), 6 deletions(-) - -diff --git a/drivers/video/dw_hdmi.c b/drivers/video/dw_hdmi.c -index c4fbb18294..fc8c8bb366 100644 ---- a/drivers/video/dw_hdmi.c -+++ b/drivers/video/dw_hdmi.c -@@ -988,7 +988,7 @@ int dw_hdmi_enable(struct dw_hdmi *hdmi, const struct display_timing *edid) - - hdmi_av_composer(hdmi, edid); - -- ret = hdmi->phy_set(hdmi, edid->pixelclock.typ); -+ ret = hdmi->ops->phy_set(hdmi, edid->pixelclock.typ); - if (ret) - return ret; - -@@ -1009,10 +1009,54 @@ int dw_hdmi_enable(struct dw_hdmi *hdmi, const struct display_timing *edid) - return 0; - } - -+static const struct dw_hdmi_phy_ops dw_hdmi_synopsys_phy_ops = { -+ .phy_set = dw_hdmi_phy_cfg, -+}; -+ -+static void dw_hdmi_detect_phy(struct dw_hdmi *hdmi) -+{ -+ if (!hdmi->data) -+ return; -+ -+ /* hook Synopsys PHYs ops */ -+ if (!hdmi->data->phy_force_vendor) { -+ hdmi->ops = &dw_hdmi_synopsys_phy_ops; -+ return; -+ } -+ -+ /* Vendor HDMI PHYs must assign phy_ops in plat_data */ -+ if (!hdmi->data->phy_ops) { -+ printf("Unsupported Vendor HDMI phy_ops\n"); -+ return; -+ } -+ -+ /* hook Vendor HDMI PHYs ops */ -+ hdmi->ops = hdmi->data->phy_ops; -+} -+ -+int dw_hdmi_disable(struct dw_hdmi *hdmi) -+{ -+ uint clkdis; -+ -+ /* disable pixel clock and tmds data path */ -+ clkdis = 0x7f; -+ hdmi_write(hdmi, clkdis, HDMI_MC_CLKDIS); -+ -+ /* disable phy */ -+ hdmi_phy_sel_interface_control(hdmi, 0); -+ hdmi_phy_enable_tmds(hdmi, 0); -+ hdmi_phy_enable_power(hdmi, 0); -+ -+ return 0; -+ -+} -+ - void dw_hdmi_init(struct dw_hdmi *hdmi) - { - uint ih_mute; - -+ dw_hdmi_detect_phy(hdmi); -+ - /* - * boot up defaults are: - * hdmi_ih_mute = 0x03 (disabled) -diff --git a/drivers/video/meson/meson_dw_hdmi.c b/drivers/video/meson/meson_dw_hdmi.c -index 5db01904b5..d0d878b6af 100644 ---- a/drivers/video/meson/meson_dw_hdmi.c -+++ b/drivers/video/meson/meson_dw_hdmi.c -@@ -375,6 +375,15 @@ static int meson_dw_hdmi_wait_hpd(struct dw_hdmi *hdmi) - return -ETIMEDOUT; - } - -+static const struct dw_hdmi_phy_ops dw_hdmi_meson_phy_ops = { -+ .phy_set = meson_dw_hdmi_phy_init, -+}; -+ -+static const struct dw_hdmi_plat_data dw_hdmi_meson_plat_data = { -+ .phy_force_vendor = true, -+ .phy_ops = &dw_hdmi_meson_phy_ops, -+}; -+ - static int meson_dw_hdmi_probe(struct udevice *dev) - { - struct meson_dw_hdmi *priv = dev_get_priv(dev); -@@ -397,7 +406,7 @@ static int meson_dw_hdmi_probe(struct udevice *dev) - - priv->hdmi.hdmi_data.enc_out_bus_format = MEDIA_BUS_FMT_RGB888_1X24; - priv->hdmi.hdmi_data.enc_in_bus_format = MEDIA_BUS_FMT_YUV8_1X24; -- priv->hdmi.phy_set = meson_dw_hdmi_phy_init; -+ priv->hdmi.data = &dw_hdmi_meson_plat_data; - if (meson_hdmi_is_compatible(priv, HDMI_COMPATIBLE_G12A)) - priv->hdmi.reg_io_width = 1; - else { -diff --git a/drivers/video/rockchip/rk3399_hdmi.c b/drivers/video/rockchip/rk3399_hdmi.c -index 3041360c6e..b32139a8a6 100644 ---- a/drivers/video/rockchip/rk3399_hdmi.c -+++ b/drivers/video/rockchip/rk3399_hdmi.c -@@ -64,8 +64,14 @@ static const struct dm_display_ops rk3399_hdmi_ops = { - .enable = rk3399_hdmi_enable, - }; - -+static const struct dw_hdmi_plat_data rk3399_hdmi_drv_data = { -+}; -+ - static const struct udevice_id rk3399_hdmi_ids[] = { -- { .compatible = "rockchip,rk3399-dw-hdmi" }, -+ { -+ .compatible = "rockchip,rk3399-dw-hdmi", -+ .data = (ulong)&rk3399_hdmi_drv_data -+ }, - { } - }; - -diff --git a/drivers/video/rockchip/rk_hdmi.c b/drivers/video/rockchip/rk_hdmi.c -index 8dcd4d5964..e545d69e3b 100644 ---- a/drivers/video/rockchip/rk_hdmi.c -+++ b/drivers/video/rockchip/rk_hdmi.c -@@ -83,6 +83,7 @@ int rk_hdmi_of_to_plat(struct udevice *dev) - struct rk_hdmi_priv *priv = dev_get_priv(dev); - struct dw_hdmi *hdmi = &priv->hdmi; - -+ hdmi->data = (const struct dw_hdmi_plat_data *)dev_get_driver_data(dev); - hdmi->ioaddr = (ulong)dev_read_addr(dev); - hdmi->mpll_cfg = rockchip_mpll_cfg; - hdmi->phy_cfg = rockchip_phy_config; -@@ -90,7 +91,6 @@ int rk_hdmi_of_to_plat(struct udevice *dev) - /* hdmi->i2c_clk_{high,low} are set up by the SoC driver */ - - hdmi->reg_io_width = 4; -- hdmi->phy_set = dw_hdmi_phy_cfg; - - priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); - -diff --git a/drivers/video/rockchip/rk_hdmi.h b/drivers/video/rockchip/rk_hdmi.h -index 200dbaea74..dcfba3d3d7 100644 ---- a/drivers/video/rockchip/rk_hdmi.h -+++ b/drivers/video/rockchip/rk_hdmi.h -@@ -6,6 +6,8 @@ - #ifndef __RK_HDMI_H__ - #define __RK_HDMI_H__ - -+#include -+ - struct rkhdmi_driverdata { - /* configuration */ - u8 i2c_clk_high; -@@ -19,6 +21,7 @@ struct rkhdmi_driverdata { - - struct rk_hdmi_priv { - struct dw_hdmi hdmi; -+ struct phy phy; - void *grf; - }; - -diff --git a/drivers/video/sunxi/sunxi_dw_hdmi.c b/drivers/video/sunxi/sunxi_dw_hdmi.c -index 0324a050d0..f7ecbb923b 100644 ---- a/drivers/video/sunxi/sunxi_dw_hdmi.c -+++ b/drivers/video/sunxi/sunxi_dw_hdmi.c -@@ -328,6 +328,15 @@ static int sunxi_dw_hdmi_enable(struct udevice *dev, int panel_bpp, - return 0; - } - -+static const struct dw_hdmi_phy_ops dw_hdmi_sunxi_phy_ops = { -+ .phy_set = sunxi_dw_hdmi_phy_cfg, -+}; -+ -+static const struct dw_hdmi_plat_data dw_hdmi_sunxi_plat_data = { -+ .phy_force_vendor = true, -+ .phy_ops = &dw_hdmi_sunxi_phy_ops, -+}; -+ - static int sunxi_dw_hdmi_probe(struct udevice *dev) - { - struct sunxi_dw_hdmi_priv *priv = dev_get_priv(dev); -@@ -379,7 +388,7 @@ static int sunxi_dw_hdmi_of_to_plat(struct udevice *dev) - hdmi->i2c_clk_high = 0xd8; - hdmi->i2c_clk_low = 0xfe; - hdmi->reg_io_width = 1; -- hdmi->phy_set = sunxi_dw_hdmi_phy_cfg; -+ hdmi->data = &dw_hdmi_sunxi_plat_data; - - ret = reset_get_bulk(dev, &priv->resets); - if (ret) -diff --git a/include/dw_hdmi.h b/include/dw_hdmi.h -index 8acae3839f..4ad8b39f84 100644 ---- a/include/dw_hdmi.h -+++ b/include/dw_hdmi.h -@@ -534,6 +534,17 @@ struct hdmi_data_info { - struct hdmi_vmode video_mode; - }; - -+struct dw_hdmi; -+ -+struct dw_hdmi_phy_ops { -+ int (*phy_set)(struct dw_hdmi *hdmi, uint mpixelclock); -+}; -+ -+struct dw_hdmi_plat_data { -+ bool phy_force_vendor; -+ const struct dw_hdmi_phy_ops *phy_ops; -+}; -+ - struct dw_hdmi { - ulong ioaddr; - const struct hdmi_mpll_config *mpll_cfg; -@@ -543,8 +554,9 @@ struct dw_hdmi { - u8 reg_io_width; - struct hdmi_data_info hdmi_data; - struct udevice *ddc_bus; -+ const struct dw_hdmi_phy_ops *ops; -+ const struct dw_hdmi_plat_data *data; - -- int (*phy_set)(struct dw_hdmi *hdmi, uint mpixelclock); - void (*write_reg)(struct dw_hdmi *hdmi, u8 val, int offset); - u8 (*read_reg)(struct dw_hdmi *hdmi, int offset); - }; --- -2.34.1 - diff --git a/patch/u-boot/v2024.01/board_rk3318-box/general-hdmi-02-hpd-cleanup.patch b/patch/u-boot/v2024.01/board_rk3318-box/general-hdmi-02-hpd-cleanup.patch deleted file mode 100644 index 8c4500750638..000000000000 --- a/patch/u-boot/v2024.01/board_rk3318-box/general-hdmi-02-hpd-cleanup.patch +++ /dev/null @@ -1,193 +0,0 @@ -From d2804380b05b4e8e6557ce7239a1680853dd5258 Mon Sep 17 00:00:00 2001 -From: Jagan Teki -Date: Sat, 18 Feb 2023 00:30:30 +0530 -Subject: [PATCH] video: rockchip: hdmi: Detect hpd after controller init - -Signed-off-by: Jagan Teki ---- - drivers/video/rockchip/rk_hdmi.c | 6 +++--- - 1 file changed, 3 insertions(+), 3 deletions(-) - -diff --git a/drivers/video/rockchip/rk_hdmi.c b/drivers/video/rockchip/rk_hdmi.c -index 8dcd4d59645..b75a1744896 100644 ---- a/drivers/video/rockchip/rk_hdmi.c -+++ b/drivers/video/rockchip/rk_hdmi.c -@@ -112,14 +112,14 @@ int rk_hdmi_probe(struct udevice *dev) - struct dw_hdmi *hdmi = &priv->hdmi; - int ret; - -+ dw_hdmi_init(hdmi); -+ dw_hdmi_phy_init(hdmi); -+ - ret = dw_hdmi_phy_wait_for_hpd(hdmi); - if (ret < 0) { - debug("hdmi can not get hpd signal\n"); - return -1; - } - -- dw_hdmi_init(hdmi); -- dw_hdmi_phy_init(hdmi); -- - return 0; - } -From 3569108607b8569c16aa5df540cf35db2bf58b05 Mon Sep 17 00:00:00 2001 -From: Jagan Teki -Date: Sun, 19 Feb 2023 00:20:52 +0530 -Subject: [PATCH] video: dw_hdmi: Simplify HPD detection - -Signed-off-by: Jagan Teki ---- - drivers/video/dw_hdmi.c | 13 +++++++++++++ - drivers/video/rockchip/rk_hdmi.c | 8 +++----- - drivers/video/sunxi/sunxi_dw_hdmi.c | 8 +++----- - include/dw_hdmi.h | 1 + - 4 files changed, 20 insertions(+), 10 deletions(-) - -diff --git a/drivers/video/dw_hdmi.c b/drivers/video/dw_hdmi.c -index ea12a094074..0a597206f06 100644 ---- a/drivers/video/dw_hdmi.c -+++ b/drivers/video/dw_hdmi.c -@@ -936,6 +936,19 @@ int dw_hdmi_phy_wait_for_hpd(struct dw_hdmi *hdmi) - return -1; - } - -+int dw_hdmi_detect_hpd(struct dw_hdmi *hdmi) -+{ -+ int ret; -+ -+ ret = dw_hdmi_phy_wait_for_hpd(hdmi); -+ if (ret < 0) { -+ debug("hdmi can not get hpd signal\n"); -+ return -ENODEV; -+ } -+ -+ return 0; -+} -+ - void dw_hdmi_phy_init(struct dw_hdmi *hdmi) - { - /* enable phy i2cm done irq */ -diff --git a/drivers/video/rockchip/rk_hdmi.c b/drivers/video/rockchip/rk_hdmi.c -index e34f532cd68..8a65f2440e4 100644 ---- a/drivers/video/rockchip/rk_hdmi.c -+++ b/drivers/video/rockchip/rk_hdmi.c -@@ -115,11 +115,9 @@ int rk_hdmi_probe(struct udevice *dev) - dw_hdmi_init(hdmi); - dw_hdmi_phy_init(hdmi); - -- ret = dw_hdmi_phy_wait_for_hpd(hdmi); -- if (ret < 0) { -- debug("hdmi can not get hpd signal\n"); -- return -1; -- } -+ ret = dw_hdmi_detect_hpd(hdmi); -+ if (ret < 0) -+ return ret; - - return 0; - } -diff --git a/drivers/video/sunxi/sunxi_dw_hdmi.c b/drivers/video/sunxi/sunxi_dw_hdmi.c -index 46ad9d137b1..6738950fd00 100644 ---- a/drivers/video/sunxi/sunxi_dw_hdmi.c -+++ b/drivers/video/sunxi/sunxi_dw_hdmi.c -@@ -347,11 +347,9 @@ static int sunxi_dw_hdmi_probe(struct udevice *dev) - - sunxi_dw_hdmi_phy_init(&priv->hdmi); - -- ret = dw_hdmi_phy_wait_for_hpd(&priv->hdmi); -- if (ret < 0) { -- debug("hdmi can not get hpd signal\n"); -- return -1; -- } -+ ret = dw_hdmi_detect_hpd(&priv->hdmi); -+ if (ret < 0) -+ return ret; - - dw_hdmi_init(&priv->hdmi); - -diff --git a/include/dw_hdmi.h b/include/dw_hdmi.h -index 4ad8b39f84d..756560e0928 100644 ---- a/include/dw_hdmi.h -+++ b/include/dw_hdmi.h -@@ -554,7 +568,9 @@ int dw_hdmi_phy_wait_for_hpd(struct dw_hdmi *hdmi); - void dw_hdmi_phy_init(struct dw_hdmi *hdmi); - - int dw_hdmi_enable(struct dw_hdmi *hdmi, const struct display_timing *edid); -+int dw_hdmi_disable(struct dw_hdmi *hdmi); - int dw_hdmi_read_edid(struct dw_hdmi *hdmi, u8 *buf, int buf_size); - void dw_hdmi_init(struct dw_hdmi *hdmi); -+int dw_hdmi_detect_hpd(struct dw_hdmi *hdmi); - - #endif -From 89431ed902443d0c62e88ca71ac31059c413b4bf Mon Sep 17 00:00:00 2001 -From: Jagan Teki -Date: Sun, 19 Feb 2023 00:30:37 +0530 -Subject: [PATCH] video: dw_hdmi: Add read_hpd hook - -Signed-off-by: Jagan Teki ---- - drivers/video/dw_hdmi.c | 3 +++ - include/dw_hdmi.h | 1 + - 2 files changed, 4 insertions(+) - -diff --git a/drivers/video/dw_hdmi.c b/drivers/video/dw_hdmi.c -index 0a597206f06..172e6b45a60 100644 ---- a/drivers/video/dw_hdmi.c -+++ b/drivers/video/dw_hdmi.c -@@ -946,6 +946,9 @@ int dw_hdmi_detect_hpd(struct dw_hdmi *hdmi) - return -ENODEV; - } - -+ if (hdmi->ops->read_hpd) -+ hdmi->ops->read_hpd(hdmi, true); -+ - return 0; - } - -diff --git a/include/dw_hdmi.h b/include/dw_hdmi.h -index 756560e0928..d6de472cee8 100644 ---- a/include/dw_hdmi.h -+++ b/include/dw_hdmi.h -@@ -538,6 +538,7 @@ struct dw_hdmi; - - struct dw_hdmi_phy_ops { - int (*phy_set)(struct dw_hdmi *hdmi, uint mpixelclock); -+ void (*read_hpd)(struct dw_hdmi *hdmi, bool hdp_status); - }; - - struct dw_hdmi_plat_data { -From 40405cb1924f60ff27923d5d11e6558117ced815 Mon Sep 17 00:00:00 2001 -From: Jagan Teki -Date: Sun, 19 Feb 2023 00:33:18 +0530 -Subject: [PATCH] video: dw_hdmi: Add setup_hpd hook - -Signed-off-by: Jagan Teki ---- - drivers/video/dw_hdmi.c | 3 +++ - include/dw_hdmi.h | 1 + - 2 files changed, 4 insertions(+) - -diff --git a/drivers/video/dw_hdmi.c b/drivers/video/dw_hdmi.c -index 172e6b45a60..3e0e20e59ba 100644 ---- a/drivers/video/dw_hdmi.c -+++ b/drivers/video/dw_hdmi.c -@@ -1080,4 +1080,7 @@ void dw_hdmi_init(struct dw_hdmi *hdmi) - - /* enable i2c client nack % arbitration error irq */ - hdmi_write(hdmi, ~0x44, HDMI_I2CM_CTLINT); -+ -+ if (hdmi->ops->setup_hpd) -+ hdmi->ops->setup_hpd(hdmi); - } -diff --git a/include/dw_hdmi.h b/include/dw_hdmi.h -index d6de472cee8..9a44b9e90c3 100644 ---- a/include/dw_hdmi.h -+++ b/include/dw_hdmi.h -@@ -539,6 +539,7 @@ struct dw_hdmi; - struct dw_hdmi_phy_ops { - int (*phy_set)(struct dw_hdmi *hdmi, uint mpixelclock); - void (*read_hpd)(struct dw_hdmi *hdmi, bool hdp_status); -+ void (*setup_hpd)(struct dw_hdmi *hdmi); - }; - - struct dw_hdmi_plat_data { diff --git a/patch/u-boot/v2024.01/board_rk3318-box/rk3328-add-usb-reset-props.patch b/patch/u-boot/v2024.01/board_rk3318-box/rk3328-add-usb-reset-props.patch deleted file mode 100644 index 23d36d8d01cb..000000000000 --- a/patch/u-boot/v2024.01/board_rk3318-box/rk3328-add-usb-reset-props.patch +++ /dev/null @@ -1,52 +0,0 @@ -From 156d0912a8fe2794e180d5b6a0c61de1a7e2cd86 Mon Sep 17 00:00:00 2001 -From: Paolo Sabatino -Date: Thu, 2 May 2024 21:23:49 +0200 -Subject: [PATCH] add reset properties for rk3328 USB devices - ---- - arch/arm/dts/rk3328.dtsi | 8 ++++++++ - 1 file changed, 8 insertions(+) - -diff --git a/arch/arm/dts/rk3328.dtsi b/arch/arm/dts/rk3328.dtsi -index e8d8f00be8..46374cabc6 100644 ---- a/arch/arm/dts/rk3328.dtsi -+++ b/arch/arm/dts/rk3328.dtsi -@@ -951,6 +951,8 @@ - clocks = <&cru HCLK_HOST0>, <&u2phy>; - phys = <&u2phy_host>; - phy-names = "usb"; -+ resets = <&cru SRST_USB2HOST_EHCIPHY>; -+ reset-names = "ehci"; - status = "disabled"; - }; - -@@ -961,6 +963,8 @@ - clocks = <&cru HCLK_HOST0>, <&u2phy>; - phys = <&u2phy_host>; - phy-names = "usb"; -+ resets = <&cru SRST_USB2HOST_EHCIPHY>; -+ reset-names = "ehci"; - status = "disabled"; - }; - -@@ -974,6 +978,8 @@ - "bus_clk"; - dr_mode = "otg"; - phy_type = "utmi_wide"; -+ resets = <&cru SRST_USB3OTG>; -+ reset-names = "otg"; - snps,dis-del-phy-power-chg-quirk; - snps,dis_enblslpm_quirk; - snps,dis-tx-ipgap-linecheck-quirk; -@@ -1003,6 +1009,8 @@ - g-np-tx-fifo-size = <16>; - g-rx-fifo-size = <280>; - g-tx-fifo-size = <256 128 128 64 32 16>; -+ resets = <&cru SRST_USB2OTG>; -+ reset-names = "otg"; - phys = <&u2phy_otg>; - phy-names = "usb2-phy"; - status = "disabled"; --- -2.34.1 - diff --git a/patch/u-boot/v2024.01/board_rk3318-box/rk3328-hdmi-driver.patch b/patch/u-boot/v2024.01/board_rk3318-box/rk3328-hdmi-driver.patch deleted file mode 100644 index 848e6009f8fa..000000000000 --- a/patch/u-boot/v2024.01/board_rk3318-box/rk3328-hdmi-driver.patch +++ /dev/null @@ -1,190 +0,0 @@ -From 3b445a031cb98413cd34e6daf8306701b5d451d4 Mon Sep 17 00:00:00 2001 -From: Jagan Teki -Date: Mon, 20 Feb 2023 01:04:39 +0530 -Subject: [PATCH] video: rockchip: Add rk3328 hdmi support - -Signed-off-by: Jagan Teki ---- - drivers/video/rockchip/Makefile | 1 + - drivers/video/rockchip/rk3328_hdmi.c | 141 +++++++++++++++++++++++++++ - drivers/video/rockchip/rk_hdmi.h | 3 + - 3 files changed, 145 insertions(+) - create mode 100644 drivers/video/rockchip/rk3328_hdmi.c - -diff --git a/drivers/video/rockchip/Makefile b/drivers/video/rockchip/Makefile -index 2a23a1a447f..ad954240afa 100644 ---- a/drivers/video/rockchip/Makefile -+++ b/drivers/video/rockchip/Makefile -@@ -11,6 +11,7 @@ obj-$(CONFIG_ROCKCHIP_RK3399) += rk3399_vop.o - obj-$(CONFIG_DISPLAY_ROCKCHIP_EDP) += rk_edp.o - obj-$(CONFIG_DISPLAY_ROCKCHIP_LVDS) += rk_lvds.o - obj-hdmi-$(CONFIG_ROCKCHIP_RK3288) += rk3288_hdmi.o -+obj-hdmi-$(CONFIG_ROCKCHIP_RK3328) += rk3328_hdmi.o - obj-hdmi-$(CONFIG_ROCKCHIP_RK3399) += rk3399_hdmi.o - obj-$(CONFIG_DISPLAY_ROCKCHIP_HDMI) += rk_hdmi.o $(obj-hdmi-y) - obj-mipi-$(CONFIG_ROCKCHIP_RK3288) += rk3288_mipi.o -diff --git a/drivers/video/rockchip/rk3328_hdmi.c b/drivers/video/rockchip/rk3328_hdmi.c -new file mode 100644 -index 0000000000..6f562d0ed8 ---- /dev/null -+++ b/drivers/video/rockchip/rk3328_hdmi.c -@@ -0,0 +1,158 @@ -+// SPDX-License-Identifier: GPL-2.0+ -+/* -+ * Copyright (c) 2023 Edgeble AI Technologies Pvt. Ltd. -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include "rk_hdmi.h" -+ -+#define RK3328_IO_3V_DOMAIN (7 << (9 + 16)) -+#define RK3328_IO_5V_DOMAIN ((7 << 9) | (3 << (9 + 16))) -+#define RK3328_IO_DDC_IN_MSK ((3 << 10) | (3 << (10 + 16))) -+#define RK3328_IO_CTRL_BY_HDMI ((1 << 13) | (1 << (13 + 16))) -+ -+static int rk3328_hdmi_enable(struct udevice *dev, int panel_bpp, -+ const struct display_timing *edid) -+{ -+ struct rk_hdmi_priv *priv = dev_get_priv(dev); -+ -+ return dw_hdmi_enable(&priv->hdmi, edid); -+} -+ -+static int rk3328_dw_hdmi_phy_cfg(struct dw_hdmi *hdmi, uint pixclock) -+{ -+ struct rk_hdmi_priv *priv = container_of(hdmi, struct rk_hdmi_priv, hdmi); -+ struct phy_configure_opts_inno_hdmi params; -+ int ret; -+ -+ params.pixel_clock = pixclock; -+ params.bus_width = 8; -+ -+ ret = generic_phy_configure(&priv->phy, ¶ms); -+ if (ret < 0) { -+ printf("failed to configure phy (pixel_clock=%d, bus_width=%d)\n", -+ params.pixel_clock, params.bus_width); -+ return ret; -+ } -+ -+ ret = generic_phy_power_on(&priv->phy); -+ if (ret) { -+ printf("failed to power on hdmi phy (ret=%d)\n", ret); -+ return ret; -+ } -+ -+ return 0; -+} -+ -+static void rk3328_dw_hdmi_setup_hpd(struct dw_hdmi *hdmi) -+{ -+ struct rk_hdmi_priv *priv = container_of(hdmi, struct rk_hdmi_priv, hdmi); -+ struct rk3328_grf_regs *grf = priv->grf; -+ -+ writel(RK3328_IO_DDC_IN_MSK, &grf->soc_con[2]); -+ writel(RK3328_IO_CTRL_BY_HDMI, &grf->soc_con[3]); -+} -+ -+static void rk3328_dw_hdmi_read_hpd(struct dw_hdmi *hdmi, bool hpd_status) -+{ -+ struct rk_hdmi_priv *priv = container_of(hdmi, struct rk_hdmi_priv, hdmi); -+ struct rk3328_grf_regs *grf = priv->grf; -+ -+ if (hpd_status) -+ writel(RK3328_IO_5V_DOMAIN, &grf->soc_con[4]); -+ else -+ writel(RK3328_IO_3V_DOMAIN, &grf->soc_con[4]); -+} -+ -+static const struct dw_hdmi_phy_ops dw_hdmi_rk3328_phy_ops = { -+ .phy_set = rk3328_dw_hdmi_phy_cfg, -+ .setup_hpd = rk3328_dw_hdmi_setup_hpd, -+ .read_hpd = rk3328_dw_hdmi_read_hpd, -+}; -+ -+static const struct dw_hdmi_plat_data dw_hdmi_rk3328_plat_data = { -+ .phy_force_vendor = true, -+ .phy_ops = &dw_hdmi_rk3328_phy_ops, -+}; -+ -+static int rk3328_hdmi_of_to_plat(struct udevice *dev) -+{ -+ struct rk_hdmi_priv *priv = dev_get_priv(dev); -+ struct dw_hdmi *hdmi = &priv->hdmi; -+ -+ hdmi->i2c_clk_high = 0x71; -+ hdmi->i2c_clk_low = 0x76; -+ -+ rk_hdmi_of_to_plat(dev); -+ -+ hdmi->data = &dw_hdmi_rk3328_plat_data; -+ -+ return 0; -+} -+ -+static int rk3328_hdmi_probe(struct udevice *dev) -+{ -+ struct rk_hdmi_priv *priv = dev_get_priv(dev); -+ int ret; -+ -+ ret = generic_phy_get_by_name(dev, "hdmi", &priv->phy); -+ if (ret) { -+ printf("failed to get hdmi phy\n"); -+ return ret; -+ }; -+ -+ ret = rk_hdmi_probe(dev); -+ if (ret) { -+ printf("failed to probe rk hdmi\n"); -+ return ret; -+ } -+ -+ return 0; -+} -+ -+static int rk3328_hdmi_remove(struct udevice *dev) -+{ -+ struct rk_hdmi_priv *priv = dev_get_priv(dev); -+ int ret; -+ -+ debug("%s\n", __func__); -+ -+ dw_hdmi_disable(&priv->hdmi); -+ -+ ret = generic_phy_power_off(&priv->phy); -+ if (ret) { -+ printf("failed to on hdmi phy (ret=%d)\n", ret); -+ } -+ -+ return 0; -+ -+} -+ -+static const struct dm_display_ops rk3328_hdmi_ops = { -+ .read_edid = rk_hdmi_read_edid, -+ .enable = rk3328_hdmi_enable, -+}; -+ -+static const struct udevice_id rk3328_hdmi_ids[] = { -+ { .compatible = "rockchip,rk3328-dw-hdmi" }, -+ { } -+}; -+ -+U_BOOT_DRIVER(rk3328_hdmi_rockchip) = { -+ .name = "rk3328_hdmi_rockchip", -+ .id = UCLASS_DISPLAY, -+ .of_match = rk3328_hdmi_ids, -+ .ops = &rk3328_hdmi_ops, -+ .of_to_plat = rk3328_hdmi_of_to_plat, -+ .probe = rk3328_hdmi_probe, -+ .priv_auto = sizeof(struct rk_hdmi_priv), -+ .remove = rk3328_hdmi_remove, -+ .flags = DM_FLAG_OS_PREPARE -+}; - diff --git a/patch/u-boot/v2024.01/board_rk3318-box/rk3328-vop-driver.patch b/patch/u-boot/v2024.01/board_rk3318-box/rk3328-vop-driver.patch deleted file mode 100644 index d794a39c1308..000000000000 --- a/patch/u-boot/v2024.01/board_rk3318-box/rk3328-vop-driver.patch +++ /dev/null @@ -1,339 +0,0 @@ -From 32a6e8629d11cfa79d33fa733d1b845e36eadaef Mon Sep 17 00:00:00 2001 -From: Jagan Teki -Date: Mon, 20 Feb 2023 00:58:55 +0530 -Subject: [PATCH] video: rockchip: Add rk3328 vop support - -Signed-off-by: Jagan Teki ---- - drivers/video/rockchip/Makefile | 1 + - drivers/video/rockchip/rk3328_vop.c | 66 +++++++++++++++++++++++++++++ - 2 files changed, 67 insertions(+) - create mode 100644 drivers/video/rockchip/rk3328_vop.c - -diff --git a/drivers/video/rockchip/Makefile b/drivers/video/rockchip/Makefile -index 9aced5ef3f4..2a23a1a447f 100644 ---- a/drivers/video/rockchip/Makefile -+++ b/drivers/video/rockchip/Makefile -@@ -6,6 +6,7 @@ - ifdef CONFIG_VIDEO_ROCKCHIP - obj-y += rk_vop.o - obj-$(CONFIG_ROCKCHIP_RK3288) += rk3288_vop.o -+obj-$(CONFIG_ROCKCHIP_RK3328) += rk3328_vop.o - obj-$(CONFIG_ROCKCHIP_RK3399) += rk3399_vop.o - obj-$(CONFIG_DISPLAY_ROCKCHIP_EDP) += rk_edp.o - obj-$(CONFIG_DISPLAY_ROCKCHIP_LVDS) += rk_lvds.o -diff --git a/drivers/video/rockchip/rk3328_vop.c b/drivers/video/rockchip/rk3328_vop.c -new file mode 100644 -index 0000000000..5275d65417 ---- /dev/null -+++ b/drivers/video/rockchip/rk3328_vop.c -@@ -0,0 +1,111 @@ -+// SPDX-License-Identifier: GPL-2.0+ -+/* -+ * Copyright (c) 2023 Edgeble AI Technologies Pvt. Ltd. -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include "rk_vop.h" -+ -+DECLARE_GLOBAL_DATA_PTR; -+ -+static void rk3328_set_pin_polarity(struct udevice *dev, -+ enum vop_modes mode, u32 polarity) -+{ -+ struct rk_vop_priv *priv = dev_get_priv(dev); -+ struct rk3288_vop *regs = priv->regs; -+ -+ switch (mode) { -+ case VOP_MODE_HDMI: -+ clrsetbits_le32(®s->dsp_ctrl1, -+ M_RK3399_DSP_HDMI_POL, -+ V_RK3399_DSP_HDMI_POL(polarity)); -+ break; -+ default: -+ debug("%s: unsupported output mode %x\n", __func__, mode); -+ } -+} -+ -+static int rk3328_vop_probe(struct udevice *dev) -+{ -+ /* Before relocation we don't need to do anything */ -+ if (!(gd->flags & GD_FLG_RELOC)) -+ return 0; -+ -+ return rk_vop_probe(dev); -+} -+ -+/** -+ * Remove the device deasserting the dclk, thus disabling the VOP. -+ * This is essential to avoid iommu complaining later during kernel boot -+ * @see https://lore.kernel.org/linux-arm-kernel/20230330131746.1475514-1-jagan@amarulasolutions.com/ -+ */ -+static int rk3328_vop_remove(struct udevice *dev) -+{ -+ struct rk_vop_priv *priv = dev_get_priv(dev); -+ struct rk3288_vop *regs = priv->regs; -+ struct reset_ctl dclk_rst; -+ -+ int ret; -+ -+ debug("%s\n", __func__); -+ -+ /* set to standby */ -+ setbits_le32(®s->sys_ctrl, V_STANDBY_EN(1)); -+ clrsetbits_le32(®s->sys_ctrl, M_ALL_OUT_EN, 0x0); -+ -+ ret = reset_get_by_name(dev, "dclk", &dclk_rst); -+ if (ret) { -+ printf("failed to get dclk reset (ret=%d)\n", ret); -+ } -+ -+ /* assert and deassert reset */ -+ ret = reset_assert(&dclk_rst); -+ if (ret) { -+ printf("failed to assert dclk reset (ret=%d)\n", ret); -+ } -+ udelay(20); -+ -+ ret = reset_deassert(&dclk_rst); -+ if (ret) { -+ printf("failed to deassert dclk reset (ret=%d)\n", ret); -+ } -+ -+ return 0; -+ -+} -+ -+struct rkvop_driverdata rk3328_driverdata = { -+ .dsp_offset = 0x490, -+ .win_offset = 0xd0, -+ .features = VOP_FEATURE_OUTPUT_10BIT, -+ .set_pin_polarity = rk3328_set_pin_polarity, -+}; -+ -+static const struct udevice_id rk3328_vop_ids[] = { -+ { -+ .compatible = "rockchip,rk3328-vop", -+ .data = (ulong)&rk3328_driverdata -+ }, -+ { /* sentile */ } -+}; -+ -+static const struct video_ops rk3328_vop_ops = { -+}; -+ -+U_BOOT_DRIVER(rockchip_rk3328_vop) = { -+ .name = "rockchip_rk3328_vop", -+ .id = UCLASS_VIDEO, -+ .of_match = rk3328_vop_ids, -+ .ops = &rk3328_vop_ops, -+ .bind = rk_vop_bind, -+ .probe = rk3328_vop_probe, -+ .remove = rk3328_vop_remove, -+ .priv_auto = sizeof(struct rk_vop_priv), -+ .flags = DM_FLAG_OS_PREPARE -+}; -From 192910962f05ea174e3f30cc1ef182981bf8ef71 Mon Sep 17 00:00:00 2001 -From: Jagan Teki -Date: Thu, 16 Feb 2023 22:48:09 +0530 -Subject: [PATCH] ARM: dts: rk3328: Enable VOP for u-boot,dm-pre-reloc - - Model: Firefly roc-rk3328-cc - DRAM: 1 GiB (effective 1022 MiB) - Video device 'vop@ff370000' cannot allocate frame buffer memory -ensure the device is set up before relocation - Error binding driver 'rockchip_rk3328_vop': -28 - Some drivers failed to bind - initcall sequence 000000003ffcd5e8 failed at call 000000000021a5c4 (err=-28) - ### ERROR ### Please RESET the board ### - -Signed-off-by: Jagan Teki ---- - arch/arm/dts/rk3328-u-boot.dtsi | 4 ++++ - 1 file changed, 4 insertions(+) - -diff --git a/arch/arm/dts/rk3328-u-boot.dtsi b/arch/arm/dts/rk3328-u-boot.dtsi -index d4a7540a92c..bd6702dedc7 100644 ---- a/arch/arm/dts/rk3328-u-boot.dtsi -+++ b/arch/arm/dts/rk3328-u-boot.dtsi -@@ -73,3 +73,7 @@ - &spi0 { - u-boot,dm-pre-reloc; - }; -+ -+&vop { -+ bootph-all; -+}; -From ac6442b276b1aef478e1b701e3f4754d98ca61ab Mon Sep 17 00:00:00 2001 -From: Jagan Teki -Date: Thu, 16 Feb 2023 10:48:48 +0530 -Subject: [PATCH] clk: rockchip: rk3328: Add VOP clk support - -Signed-off-by: Jagan Teki ---- - .../include/asm/arch-rockchip/cru_rk3328.h | 34 ++++++++ - drivers/clk/rockchip/clk_rk3328.c | 83 ++++++++++++++++++- - 2 files changed, 115 insertions(+), 2 deletions(-) - -diff --git a/arch/arm/include/asm/arch-rockchip/cru_rk3328.h b/arch/arm/include/asm/arch-rockchip/cru_rk3328.h -index 226744d67d9..4ad1d33e056 100644 ---- a/arch/arm/include/asm/arch-rockchip/cru_rk3328.h -+++ b/arch/arm/include/asm/arch-rockchip/cru_rk3328.h -@@ -62,6 +62,40 @@ check_member(rk3328_cru, sdmmc_ext_con[1], 0x39c); - enum apll_frequencies { - APLL_816_MHZ, - APLL_600_MHZ, -+ -+ /* CRU_CLK_SEL37_CON */ -+ ACLK_VIO_PLL_SEL_CPLL = 0, -+ ACLK_VIO_PLL_SEL_GPLL = 1, -+ ACLK_VIO_PLL_SEL_HDMIPHY = 2, -+ ACLK_VIO_PLL_SEL_USB480M = 3, -+ ACLK_VIO_PLL_SEL_SHIFT = 6, -+ ACLK_VIO_PLL_SEL_MASK = 3 << ACLK_VIO_PLL_SEL_SHIFT, -+ ACLK_VIO_DIV_CON_SHIFT = 0, -+ ACLK_VIO_DIV_CON_MASK = 0x1f << ACLK_VIO_DIV_CON_SHIFT, -+ HCLK_VIO_DIV_CON_SHIFT = 8, -+ HCLK_VIO_DIV_CON_MASK = 0x1f << HCLK_VIO_DIV_CON_SHIFT, -+ -+ /* CRU_CLK_SEL39_CON */ -+ ACLK_VOP_PLL_SEL_CPLL = 0, -+ ACLK_VOP_PLL_SEL_GPLL = 1, -+ ACLK_VOP_PLL_SEL_HDMIPHY = 2, -+ ACLK_VOP_PLL_SEL_USB480M = 3, -+ ACLK_VOP_PLL_SEL_SHIFT = 6, -+ ACLK_VOP_PLL_SEL_MASK = 3 << ACLK_VOP_PLL_SEL_SHIFT, -+ ACLK_VOP_DIV_CON_SHIFT = 0, -+ ACLK_VOP_DIV_CON_MASK = 0x1f << ACLK_VOP_DIV_CON_SHIFT, -+ -+ /* CRU_CLK_SEL40_CON */ -+ DCLK_LCDC_PLL_SEL_GPLL = 0, -+ DCLK_LCDC_PLL_SEL_CPLL = 1, -+ DCLK_LCDC_PLL_SEL_SHIFT = 0, -+ DCLK_LCDC_PLL_SEL_MASK = 1 << DCLK_LCDC_PLL_SEL_SHIFT, -+ DCLK_LCDC_SEL_HDMIPHY = 0, -+ DCLK_LCDC_SEL_PLL = 1, -+ DCLK_LCDC_SEL_SHIFT = 1, -+ DCLK_LCDC_SEL_MASK = 1 << DCLK_LCDC_SEL_SHIFT, -+ DCLK_LCDC_DIV_CON_SHIFT = 8, -+ DCLK_LCDC_DIV_CON_MASK = 0xFf << DCLK_LCDC_DIV_CON_SHIFT, - }; - - void rk3328_configure_cpu(struct rk3328_cru *cru, -diff --git a/drivers/clk/rockchip/clk_rk3328.c b/drivers/clk/rockchip/clk_rk3328.c -index b825ff4cf83..195247d9e02 100644 ---- a/drivers/clk/rockchip/clk_rk3328.c -+++ b/drivers/clk/rockchip/clk_rk3328.c -@@ -581,6 +581,81 @@ static ulong rk3328_spi_set_clk(struct rk3328_cru *cru, uint hz) - return rk3328_spi_get_clk(cru); - } - -+#ifndef CONFIG_SPL_BUILD -+static ulong rk3328_vop_get_clk(struct rk3328_clk_priv *priv, ulong clk_id) -+{ -+ struct rk3328_cru *cru = priv->cru; -+ u32 div, con, parent; -+ -+ switch (clk_id) { -+ case ACLK_VOP_PRE: -+ con = readl(&cru->clksel_con[39]); -+ div = (con & ACLK_VOP_DIV_CON_MASK) >> ACLK_VOP_DIV_CON_SHIFT; -+ parent = GPLL_HZ; -+ break; -+ case ACLK_VIO_PRE: -+ con = readl(&cru->clksel_con[37]); -+ div = (con & ACLK_VIO_DIV_CON_MASK) >> ACLK_VIO_DIV_CON_SHIFT; -+ parent = GPLL_HZ; -+ break; -+ default: -+ debug("%s: Unsupported vop get clk#%ld\n", __func__, clk_id); -+ return -ENOENT; -+ } -+ -+ return DIV_TO_RATE(parent, div); -+} -+ -+static ulong rk3328_vop_set_clk(struct rk3328_clk_priv *priv, -+ ulong clk_id, uint hz) -+{ -+ struct rk3328_cru *cru = priv->cru; -+ int src_clk_div; -+ u32 con, parent; -+ -+ src_clk_div = DIV_ROUND_UP(GPLL_HZ, hz); -+ assert(src_clk_div - 1 < 31); -+ -+ switch (clk_id) { -+ case ACLK_VOP_PRE: -+ rk_clrsetreg(&cru->clksel_con[39], -+ ACLK_VOP_PLL_SEL_MASK | ACLK_VOP_DIV_CON_MASK, -+ ACLK_VOP_PLL_SEL_GPLL << ACLK_VOP_PLL_SEL_SHIFT | -+ (src_clk_div - 1) << ACLK_VOP_DIV_CON_SHIFT); -+ break; -+ case ACLK_VIO_PRE: -+ rk_clrsetreg(&cru->clksel_con[37], -+ ACLK_VIO_PLL_SEL_MASK | ACLK_VIO_DIV_CON_MASK, -+ ACLK_VIO_PLL_SEL_GPLL << ACLK_VIO_PLL_SEL_SHIFT | -+ (src_clk_div - 1) << ACLK_VIO_DIV_CON_SHIFT); -+ break; -+ case DCLK_LCDC: -+ con = readl(&cru->clksel_con[40]); -+ con = (con & DCLK_LCDC_SEL_MASK) >> DCLK_LCDC_SEL_SHIFT; -+ if (con) { -+ parent = readl(&cru->clksel_con[40]); -+ parent = (parent & DCLK_LCDC_PLL_SEL_MASK) >> -+ DCLK_LCDC_PLL_SEL_SHIFT; -+ if (parent) -+ src_clk_div = DIV_ROUND_UP(GPLL_HZ, hz); -+ else -+ src_clk_div = DIV_ROUND_UP(GPLL_HZ, hz); -+ -+ rk_clrsetreg(&cru->clksel_con[40], -+ DCLK_LCDC_DIV_CON_MASK, -+ (src_clk_div - 1) << -+ DCLK_LCDC_DIV_CON_SHIFT); -+ } -+ break; -+ default: -+ printf("%s: Unable to set vop clk#%ld\n", __func__, clk_id); -+ return -EINVAL; -+ } -+ -+ return rk3328_vop_get_clk(priv, clk_id); -+} -+#endif -+ - static ulong rk3328_clk_get_rate(struct clk *clk) - { - struct rk3328_clk_priv *priv = dev_get_priv(clk->dev); -@@ -649,7 +724,13 @@ static ulong rk3328_clk_set_rate(struct clk *clk, ulong rate) - case SCLK_SPI: - ret = rk3328_spi_set_clk(priv->cru, rate); - break; -+#ifndef CONFIG_SPL_BUILD - case DCLK_LCDC: -+ case ACLK_VOP_PRE: -+ case ACLK_VIO_PRE: -+ rate = rk3328_vop_set_clk(priv, clk->id, rate); -+ break; -+#endif - case SCLK_PDM: - case SCLK_RTC32K: - case SCLK_UART0: -@@ -664,11 +745,9 @@ static ulong rk3328_clk_set_rate(struct clk *clk, ulong rate) - case ACLK_PERI_PRE: - case HCLK_PERI: - case PCLK_PERI: -- case ACLK_VIO_PRE: - case HCLK_VIO_PRE: - case ACLK_RGA_PRE: - case SCLK_RGA: -- case ACLK_VOP_PRE: - case ACLK_RKVDEC_PRE: - case ACLK_RKVENC: - case ACLK_VPU_PRE: diff --git a/patch/u-boot/v2024.01/driver-rockchip-inno-hdmi-phy.patch b/patch/u-boot/v2024.01/driver-rockchip-inno-hdmi-phy.patch deleted file mode 100644 index d68726a87967..000000000000 --- a/patch/u-boot/v2024.01/driver-rockchip-inno-hdmi-phy.patch +++ /dev/null @@ -1,1075 +0,0 @@ -From 42a891d30cd2c4c00ee674738128c03277d2d5f8 Mon Sep 17 00:00:00 2001 -From: Jagan Teki -Date: Thu, 16 Feb 2023 21:59:42 +0530 -Subject: [PATCH] phy: rockchip: Add Rockchip INNO HDMI PHY driver - -Signed-off-by: Jagan Teki -Signed-off-by: Jagan Teki ---- - drivers/phy/rockchip/Kconfig | 7 + - drivers/phy/rockchip/Makefile | 1 + - drivers/phy/rockchip/phy-rockchip-inno-hdmi.c | 734 ++++++++++++++++++ - 3 files changed, 742 insertions(+) - create mode 100644 drivers/phy/rockchip/phy-rockchip-inno-hdmi.c - -diff --git a/drivers/phy/rockchip/Kconfig b/drivers/phy/rockchip/Kconfig -index 13057639403..4809c436c17 100644 ---- a/drivers/phy/rockchip/Kconfig -+++ b/drivers/phy/rockchip/Kconfig -@@ -4,6 +4,13 @@ - - menu "Rockchip PHY driver" - -+config PHY_ROCKCHIP_INNO_HDMI -+ bool "Rockchip INNO HDMI PHY Driver" -+ depends on ARCH_ROCKCHIP -+ select PHY -+ help -+ Enable this to support the Rockchip Innosilicon HDMI PHY. -+ - config PHY_ROCKCHIP_INNO_USB2 - bool "Rockchip INNO USB2PHY Driver" - depends on ARCH_ROCKCHIP -diff --git a/drivers/phy/rockchip/Makefile b/drivers/phy/rockchip/Makefile -index a236877234b..800d5c61ef2 100644 ---- a/drivers/phy/rockchip/Makefile -+++ b/drivers/phy/rockchip/Makefile -@@ -3,6 +3,7 @@ - # Copyright (C) 2020 Amarula Solutions(India) - # - -+obj-$(CONFIG_PHY_ROCKCHIP_INNO_HDMI) += phy-rockchip-inno-hdmi.o - obj-$(CONFIG_PHY_ROCKCHIP_INNO_USB2) += phy-rockchip-inno-usb2.o - obj-$(CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY) += phy-rockchip-naneng-combphy.o - obj-$(CONFIG_PHY_ROCKCHIP_PCIE) += phy-rockchip-pcie.o -diff --git a/drivers/phy/rockchip/phy-rockchip-inno-hdmi.c b/drivers/phy/rockchip/phy-rockchip-inno-hdmi.c -new file mode 100644 -index 0000000000..207bb0acf6 ---- /dev/null -+++ b/drivers/phy/rockchip/phy-rockchip-inno-hdmi.c -@@ -0,0 +1,989 @@ -+// SPDX-License-Identifier: GPL-2.0+ -+/* -+ * Rockchip Innosilicon HDMI PHY -+ * -+ * Copyright (c) 2023 Edgeble AI Technologies Pvt. Ltd. -+ * Copyright (c) 2017 Rockchip Electronics Co. Ltd. -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#define INNO_HDMI_PHY_TIMEOUT_LOOP_COUNT 1000 -+#define UPDATE(x, h, l) (((x) << (l)) & GENMASK((h), (l))) -+ -+/* REG: 0x00 */ -+#define PRE_PLL_REFCLK_SEL_MASK BIT(0) -+#define PRE_PLL_REFCLK_SEL_PCLK BIT(0) -+#define PRE_PLL_REFCLK_SEL_OSCCLK 0 -+/* REG: 0x01 */ -+#define BYPASS_RXSENSE_EN BIT(2) -+#define BYPASS_PWRON_EN BIT(1) -+#define BYPASS_PLLPD_EN BIT(0) -+/* REG: 0x02 */ -+#define INT_POL_HIGH BIT(7) -+#define BYPASS_PDATA_EN BIT(4) -+#define RK3328_PDATA_EN BIT(0) -+#define RK3228_PDATA_EN_DISABLE BIT(0) -+/* REG: 0x03 */ -+#define BYPASS_AUTO_TERM_RES_CAL BIT(7) -+#define AUDO_TERM_RES_CAL_SPEED_14_8(x) UPDATE(x, 6, 0) -+/* REG: 0x04 */ -+#define AUDO_TERM_RES_CAL_SPEED_7_0(x) UPDATE(x, 7, 0) -+/* REG: 0xaa */ -+#define POST_PLL_CTRL_MANUAL BIT(0) -+/* REG: 0xe0 */ -+#define RK3228_POST_PLL_POWER_DOWN BIT(5) -+#define RK3228_POST_PLL_POWER_UP 0 -+#define RK3228_PRE_PLL_POWER_DOWN BIT(4) -+#define RK3228_RXSENSE_CLK_CH_MASK BIT(3) -+#define RK3228_RXSENSE_CLK_CH_ENABLE BIT(3) -+#define RK3228_RXSENSE_DATA_CH2_MASK BIT(2) -+#define RK3228_RXSENSE_DATA_CH2_ENABLE BIT(2) -+#define RK3228_RXSENSE_DATA_CH1_MASK BIT(1) -+#define RK3228_RXSENSE_DATA_CH1_ENABLE BIT(1) -+#define RK3228_RXSENSE_DATA_CH0_MASK BIT(0) -+#define RK3228_RXSENSE_DATA_CH0_ENABLE BIT(0) -+/* REG: 0xe1 */ -+#define RK3228_BANDGAP_ENABLE BIT(4) -+#define RK3228_TMDS_DRIVER_ENABLE GENMASK(3, 0) -+/* REG: 0xe2 */ -+#define RK3228_PRE_PLL_FB_DIV_8_MASK BIT(7) -+#define RK3228_PRE_PLL_FB_DIV_8(x) UPDATE((x) >> 8, 7, 7) -+#define RK3228_PCLK_VCO_DIV_5_MASK BIT(5) -+#define RK3228_PCLK_VCO_DIV_5(x) UPDATE(x, 5, 5) -+#define RK3228_PRE_PLL_PRE_DIV_MASK GENMASK(4, 0) -+#define RK3228_PRE_PLL_PRE_DIV(x) UPDATE(x, 4, 0) -+/* REG: 0xe3 */ -+#define RK3228_PRE_PLL_FB_DIV_7_0(x) UPDATE(x, 7, 0) -+/* REG: 0xe4 */ -+#define RK3228_PRE_PLL_PCLK_DIV_B_MASK GENMASK(6, 5) -+#define RK3228_PRE_PLL_PCLK_DIV_B_SHIFT 5 -+#define RK3228_PRE_PLL_PCLK_DIV_B(x) UPDATE(x, 6, 5) -+#define RK3228_PRE_PLL_PCLK_DIV_A_MASK GENMASK(4, 0) -+#define RK3228_PRE_PLL_PCLK_DIV_A(x) UPDATE(x, 4, 0) -+/* REG: 0xe5 */ -+#define RK3228_PRE_PLL_PCLK_DIV_C_MASK GENMASK(6, 5) -+#define RK3228_PRE_PLL_PCLK_DIV_C(x) UPDATE(x, 6, 5) -+#define RK3228_PRE_PLL_PCLK_DIV_D_MASK GENMASK(4, 0) -+#define RK3228_PRE_PLL_PCLK_DIV_D(x) UPDATE(x, 4, 0) -+/* REG: 0xe6 */ -+#define RK3228_PRE_PLL_TMDSCLK_DIV_C_MASK GENMASK(5, 4) -+#define RK3228_PRE_PLL_TMDSCLK_DIV_C(x) UPDATE(x, 5, 4) -+#define RK3228_PRE_PLL_TMDSCLK_DIV_A_MASK GENMASK(3, 2) -+#define RK3228_PRE_PLL_TMDSCLK_DIV_A(x) UPDATE(x, 3, 2) -+#define RK3228_PRE_PLL_TMDSCLK_DIV_B_MASK GENMASK(1, 0) -+#define RK3228_PRE_PLL_TMDSCLK_DIV_B(x) UPDATE(x, 1, 0) -+/* REG: 0xe8 */ -+#define RK3228_PRE_PLL_LOCK_STATUS BIT(0) -+/* REG: 0xe9 */ -+#define RK3228_POST_PLL_POST_DIV_ENABLE UPDATE(3, 7, 6) -+#define RK3228_POST_PLL_PRE_DIV_MASK GENMASK(4, 0) -+#define RK3228_POST_PLL_PRE_DIV(x) UPDATE(x, 4, 0) -+/* REG: 0xea */ -+#define RK3228_POST_PLL_FB_DIV_7_0(x) UPDATE(x, 7, 0) -+/* REG: 0xeb */ -+#define RK3228_POST_PLL_FB_DIV_8_MASK BIT(7) -+#define RK3228_POST_PLL_FB_DIV_8(x) UPDATE((x) >> 8, 7, 7) -+#define RK3228_POST_PLL_POST_DIV_MASK GENMASK(5, 4) -+#define RK3228_POST_PLL_POST_DIV(x) UPDATE(x, 5, 4) -+#define RK3228_POST_PLL_LOCK_STATUS BIT(0) -+/* REG: 0xee */ -+#define RK3228_TMDS_CH_TA_ENABLE GENMASK(7, 4) -+/* REG: 0xef */ -+#define RK3228_TMDS_CLK_CH_TA(x) UPDATE(x, 7, 6) -+#define RK3228_TMDS_DATA_CH2_TA(x) UPDATE(x, 5, 4) -+#define RK3228_TMDS_DATA_CH1_TA(x) UPDATE(x, 3, 2) -+#define RK3228_TMDS_DATA_CH0_TA(x) UPDATE(x, 1, 0) -+/* REG: 0xf0 */ -+#define RK3228_TMDS_DATA_CH2_PRE_EMPHASIS_MASK GENMASK(5, 4) -+#define RK3228_TMDS_DATA_CH2_PRE_EMPHASIS(x) UPDATE(x, 5, 4) -+#define RK3228_TMDS_DATA_CH1_PRE_EMPHASIS_MASK GENMASK(3, 2) -+#define RK3228_TMDS_DATA_CH1_PRE_EMPHASIS(x) UPDATE(x, 3, 2) -+#define RK3228_TMDS_DATA_CH0_PRE_EMPHASIS_MASK GENMASK(1, 0) -+#define RK3228_TMDS_DATA_CH0_PRE_EMPHASIS(x) UPDATE(x, 1, 0) -+/* REG: 0xf1 */ -+#define RK3228_TMDS_CLK_CH_OUTPUT_SWING(x) UPDATE(x, 7, 4) -+#define RK3228_TMDS_DATA_CH2_OUTPUT_SWING(x) UPDATE(x, 3, 0) -+/* REG: 0xf2 */ -+#define RK3228_TMDS_DATA_CH1_OUTPUT_SWING(x) UPDATE(x, 7, 4) -+#define RK3228_TMDS_DATA_CH0_OUTPUT_SWING(x) UPDATE(x, 3, 0) -+ -+struct inno_hdmi_phy; -+ -+struct phy_config { -+ unsigned long tmdsclock; -+ u8 regs[14]; -+}; -+ -+struct pre_pll_config { -+ unsigned long pixclock; -+ unsigned long tmdsclock; -+ u8 prediv; -+ u16 fbdiv; -+ u8 tmds_div_a; -+ u8 tmds_div_b; -+ u8 tmds_div_c; -+ u8 pclk_div_a; -+ u8 pclk_div_b; -+ u8 pclk_div_c; -+ u8 pclk_div_d; -+ u8 vco_div_5_en; -+ u32 fracdiv; -+}; -+ -+struct post_pll_config { -+ unsigned long tmdsclock; -+ u8 prediv; -+ u16 fbdiv; -+ u8 postdiv; -+ u8 version; -+}; -+ -+struct inno_hdmi_phy_plat_ops { -+ void (*init)(struct inno_hdmi_phy *inno); -+ int (*power_on)(struct inno_hdmi_phy *inno, -+ const struct post_pll_config *cfg, -+ const struct phy_config *phy_cfg); -+ void (*power_off)(struct inno_hdmi_phy *inno); -+ int (*pre_pll_update)(struct inno_hdmi_phy *inno, -+ const struct pre_pll_config *cfg); -+ unsigned long (*recalc_rate)(struct inno_hdmi_phy *inno, -+ unsigned long parent_rate); -+ int (*clk_is_prepared)(struct inno_hdmi_phy *inno); -+ int (*clk_prepare)(struct inno_hdmi_phy *inno); -+ -+}; -+ -+enum inno_hdmi_phy_type { -+ INNO_HDMI_PHY_RK3228, -+ INNO_HDMI_PHY_RK3328, -+}; -+ -+struct inno_hdmi_phy_data { -+ enum inno_hdmi_phy_type phy_type; -+ const struct inno_hdmi_phy_plat_ops *plat_ops; -+ const struct phy_config *phy_cfg_table; -+}; -+ -+struct rockchip_inno_data { -+ char compatible[30]; -+ const void *data; -+}; -+ -+struct inno_hdmi_phy { -+ struct udevice *dev; -+ ofnode node; -+ void *regs; -+ -+ unsigned long pixclock; -+ u32 bus_width; -+ struct phy_config *phy_cfg; -+ const struct inno_hdmi_phy_data *data; -+}; -+ -+static const struct pre_pll_config pre_pll_cfg_table[] = { -+ { 27000000, 27000000, 1, 90, 3, 2, 2, 10, 3, 3, 4, 0, 0}, -+ { 27000000, 33750000, 1, 90, 1, 3, 3, 10, 3, 3, 4, 0, 0}, -+ { 40000000, 40000000, 1, 80, 2, 2, 2, 12, 2, 2, 2, 0, 0}, -+ { 59341000, 59341000, 1, 98, 3, 1, 2, 1, 3, 3, 4, 0, 0xE6AE6B}, -+ { 59400000, 59400000, 1, 99, 3, 1, 1, 1, 3, 3, 4, 0, 0}, -+ { 59341000, 74176250, 1, 98, 0, 3, 3, 1, 3, 3, 4, 0, 0xE6AE6B}, -+ { 59400000, 74250000, 1, 99, 1, 2, 2, 1, 3, 3, 4, 0, 0}, -+ { 74176000, 74176000, 1, 98, 1, 2, 2, 1, 2, 3, 4, 0, 0xE6AE6B}, -+ { 74250000, 74250000, 1, 99, 1, 2, 2, 1, 2, 3, 4, 0, 0}, -+ { 74176000, 92720000, 4, 494, 1, 2, 2, 1, 3, 3, 4, 0, 0x816817}, -+ { 74250000, 92812500, 4, 495, 1, 2, 2, 1, 3, 3, 4, 0, 0}, -+ {148352000, 148352000, 1, 98, 1, 1, 1, 1, 2, 2, 2, 0, 0xE6AE6B}, -+ {148500000, 148500000, 1, 99, 1, 1, 1, 1, 2, 2, 2, 0, 0}, -+ {148352000, 185440000, 4, 494, 0, 2, 2, 1, 3, 2, 2, 0, 0x816817}, -+ {148500000, 185625000, 4, 495, 0, 2, 2, 1, 3, 2, 2, 0, 0}, -+ {296703000, 296703000, 1, 98, 0, 1, 1, 1, 0, 2, 2, 0, 0xE6AE6B}, -+ {297000000, 297000000, 1, 99, 0, 1, 1, 1, 0, 2, 2, 0, 0}, -+ {296703000, 370878750, 4, 494, 1, 2, 0, 1, 3, 1, 1, 0, 0x816817}, -+ {297000000, 371250000, 4, 495, 1, 2, 0, 1, 3, 1, 1, 0, 0}, -+ {593407000, 296703500, 1, 98, 0, 1, 1, 1, 0, 2, 1, 0, 0xE6AE6B}, -+ {594000000, 297000000, 1, 99, 0, 1, 1, 1, 0, 2, 1, 0, 0}, -+ {593407000, 370879375, 4, 494, 1, 2, 0, 1, 3, 1, 1, 1, 0x816817}, -+ {594000000, 371250000, 4, 495, 1, 2, 0, 1, 3, 1, 1, 1, 0}, -+ {593407000, 593407000, 1, 98, 0, 2, 0, 1, 0, 1, 1, 0, 0xE6AE6B}, -+ {594000000, 594000000, 1, 99, 0, 2, 0, 1, 0, 1, 1, 0, 0}, -+ { ~0UL, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0} -+}; -+ -+static const struct post_pll_config post_pll_cfg_table[] = { -+ {33750000, 1, 40, 8, 1}, -+ {33750000, 1, 80, 8, 2}, -+ {33750000, 1, 10, 2, 4}, -+ {74250000, 1, 40, 8, 1}, -+ {74250000, 18, 80, 8, 2}, -+ {148500000, 2, 40, 4, 3}, -+ {297000000, 4, 40, 2, 3}, -+ {594000000, 8, 40, 1, 3}, -+ { ~0UL, 0, 0, 0, 0} -+}; -+ -+/* phy tuning values for an undocumented set of registers */ -+static const struct phy_config rk3228_phy_cfg[] = { -+ { 165000000, { -+ 0xaa, 0x00, 0x44, 0x44, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, -+ }, -+ }, { -+ 340000000, { -+ 0xaa, 0x15, 0x6a, 0xaa, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, -+ }, -+ }, { -+ 594000000, { -+ 0xaa, 0x15, 0x7a, 0xaa, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, -+ }, -+ }, { /* sentinel */ }, -+}; -+ -+/* phy tuning values for an undocumented set of registers */ -+static const struct phy_config rk3328_phy_cfg[] = { -+ { 165000000, { -+ 0x07, 0x08, 0x08, 0x08, 0x00, 0x00, 0x08, 0x08, 0x08, -+ 0x00, 0xac, 0xcc, 0xcc, 0xcc, -+ }, -+ }, { -+ 340000000, { -+ 0x0b, 0x0d, 0x0d, 0x0d, 0x07, 0x15, 0x08, 0x08, 0x08, -+ 0x3f, 0xac, 0xcc, 0xcd, 0xdd, -+ }, -+ }, { -+ 594000000, { -+ 0x10, 0x1a, 0x1a, 0x1a, 0x07, 0x15, 0x08, 0x08, 0x08, -+ 0x00, 0xac, 0xcc, 0xcc, 0xcc, -+ }, -+ }, { -+ ~0UL, { -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, -+ }, -+ } -+}; -+ -+static inline void inno_write(struct inno_hdmi_phy *inno, u32 reg, u8 val) -+{ -+ writel(val, inno->regs + (reg * 4)); -+} -+ -+static inline u8 inno_read(struct inno_hdmi_phy *inno, u32 reg) -+{ -+ u32 val; -+ -+ val = readl(inno->regs + (reg * 4)); -+ -+ return val; -+} -+ -+static inline void inno_update_bits(struct inno_hdmi_phy *inno, u8 reg, -+ u8 mask, u8 val) -+{ -+ u32 tmp, orig; -+ -+ orig = inno_read(inno, reg); -+ tmp = orig & ~mask; -+ tmp |= val & mask; -+ inno_write(inno, reg, tmp); -+} -+ -+static u32 inno_hdmi_phy_get_tmdsclk(struct inno_hdmi_phy *inno, -+ unsigned long rate) -+{ -+ u32 tmdsclk; -+ -+ switch (inno->bus_width) { -+ case 4: -+ tmdsclk = (u32)rate / 2; -+ break; -+ case 5: -+ tmdsclk = (u32)rate * 5 / 8; -+ break; -+ case 6: -+ tmdsclk = (u32)rate * 3 / 4; -+ break; -+ case 10: -+ tmdsclk = (u32)rate * 5 / 4; -+ break; -+ case 12: -+ tmdsclk = (u32)rate * 3 / 2; -+ break; -+ case 16: -+ tmdsclk = (u32)rate * 2; -+ break; -+ default: -+ tmdsclk = rate; -+ } -+ -+ return tmdsclk; -+} -+ -+static int inno_hdmi_phy_power_on(struct phy *phy) -+{ -+ struct inno_hdmi_phy *inno = dev_get_priv(phy->dev); -+ const struct post_pll_config *cfg = post_pll_cfg_table; -+ const struct phy_config *phy_cfg = inno->data->phy_cfg_table; -+ u32 tmdsclock = inno_hdmi_phy_get_tmdsclk(inno, inno->pixclock); -+ u32 chipversion = 1; -+ -+ debug("[PHY] %s: In?\n", __func__); -+ -+ if (inno->phy_cfg) -+ phy_cfg = inno->phy_cfg; -+ -+ if (!tmdsclock) { -+ printf("TMDS clock is zero!\n"); -+ return -EINVAL; -+ } -+ -+ printf("tmdsclock = %d; chipversion = %d\n", tmdsclock, chipversion); -+ -+ for (; cfg->tmdsclock != ~0UL; cfg++) -+ if (tmdsclock <= cfg->tmdsclock && -+ cfg->version & chipversion) -+ break; -+ -+ for (; phy_cfg->tmdsclock != ~0UL; phy_cfg++) -+ if (tmdsclock <= phy_cfg->tmdsclock) -+ break; -+ -+ if (cfg->tmdsclock == ~0UL || phy_cfg->tmdsclock == ~0UL) -+ return -EINVAL; -+ -+ debug("Inno HDMI PHY Power On\n"); -+ if (inno->data->plat_ops->power_on) -+ return inno->data->plat_ops->power_on(inno, cfg, phy_cfg); -+ else -+ return -EINVAL; -+} -+ -+static int inno_hdmi_phy_power_off(struct phy *phy) -+{ -+ struct inno_hdmi_phy *inno = dev_get_priv(phy->dev); -+ -+ if (inno->data->plat_ops->power_off) -+ inno->data->plat_ops->power_off(inno); -+ debug("Inno HDMI PHY Power Off\n"); -+ -+ return 0; -+} -+ -+static int inno_hdmi_phy_rk3328_clk_is_prepared(struct inno_hdmi_phy *inno) -+{ -+ u8 status = inno_read(inno, 0xa0) & 1; -+ -+ return status ? 0 : 1; -+} -+ -+static int inno_hdmi_phy_rk3328_clk_prepare(struct inno_hdmi_phy *inno) -+{ -+ inno_update_bits(inno, 0xa0, 1, 0); -+ -+ return 0; -+} -+ -+static int inno_hdmi_phy_rk3228_clk_is_prepared(struct inno_hdmi_phy *inno) -+{ -+ u8 status = inno_read(inno, 0xe0) & RK3228_PRE_PLL_POWER_DOWN; -+ -+ status = status ? 0 : 1; -+ -+ debug("%s: status=%d\n", __func__, status); -+ -+ return status; -+} -+ -+static int inno_hdmi_phy_rk3228_clk_prepare(struct inno_hdmi_phy *inno) -+{ -+ inno_update_bits(inno, 0xe0, RK3228_PRE_PLL_POWER_DOWN, 0); -+ -+ debug("%s\n", __func__); -+ -+ return 0; -+} -+ -+static int inno_hdmi_phy_clk_set_rate(struct inno_hdmi_phy *inno, -+ unsigned long rate) -+{ -+ const struct pre_pll_config *cfg = pre_pll_cfg_table; -+ u32 tmdsclock = inno_hdmi_phy_get_tmdsclk(inno, rate); -+ -+ for (; cfg->pixclock != ~0UL; cfg++) -+ if (cfg->pixclock == rate && cfg->tmdsclock == tmdsclock) -+ break; -+ -+ if (cfg->pixclock == ~0UL) { -+ printf("unsupported rate %lu\n", rate); -+ return -EINVAL; -+ } -+ -+ if (inno->data->plat_ops->pre_pll_update) -+ inno->data->plat_ops->pre_pll_update(inno, cfg); -+ -+ inno->pixclock = rate; -+ -+ return 0; -+} -+ -+static int -+inno_hdmi_phy_rk3328_power_on(struct inno_hdmi_phy *inno, -+ const struct post_pll_config *cfg, -+ const struct phy_config *phy_cfg) -+{ -+ u32 val; -+ -+ /* set pdata_en to 0 */ -+ inno_update_bits(inno, 0x02, 1, 0); -+ /* Power off post PLL */ -+ inno_update_bits(inno, 0xaa, 1, 1); -+ -+ val = cfg->fbdiv & 0xff; -+ inno_write(inno, 0xac, val); -+ if (cfg->postdiv == 1) { -+ inno_write(inno, 0xaa, 2); -+ val = (cfg->fbdiv >> 8) | cfg->prediv; -+ inno_write(inno, 0xab, val); -+ } else { -+ val = (cfg->postdiv / 2) - 1; -+ inno_write(inno, 0xad, val); -+ val = (cfg->fbdiv >> 8) | cfg->prediv; -+ inno_write(inno, 0xab, val); -+ inno_write(inno, 0xaa, 0x0e); -+ } -+ -+ for (val = 0; val < 14; val++) -+ inno_write(inno, 0xb5 + val, phy_cfg->regs[val]); -+ -+ /* bit[7:6] of reg c8/c9/ca/c8 is ESD detect threshold: -+ * 00 - 340mV -+ * 01 - 280mV -+ * 10 - 260mV -+ * 11 - 240mV -+ * default is 240mV, now we set it to 340mV -+ */ -+ inno_write(inno, 0xc8, 0); -+ inno_write(inno, 0xc9, 0); -+ inno_write(inno, 0xca, 0); -+ inno_write(inno, 0xcb, 0); -+ -+ if (phy_cfg->tmdsclock > 340000000) { -+ /* Set termination resistor to 100ohm */ -+ val = 75000000 / 100000; -+ inno_write(inno, 0xc5, ((val >> 8) & 0xff) | 0x80); -+ inno_write(inno, 0xc6, val & 0xff); -+ inno_write(inno, 0xc7, 3 << 1); -+ inno_write(inno, 0xc5, ((val >> 8) & 0xff)); -+ } else if (phy_cfg->tmdsclock > 165000000) { -+ inno_write(inno, 0xc5, 0x81); -+ /* clk termination resistor is 50ohm -+ * data termination resistor is 150ohm -+ */ -+ inno_write(inno, 0xc8, 0x30); -+ inno_write(inno, 0xc9, 0x10); -+ inno_write(inno, 0xca, 0x10); -+ inno_write(inno, 0xcb, 0x10); -+ } else { -+ inno_write(inno, 0xc5, 0x81); -+ } -+ -+ /* set TMDS sync detection counter length */ -+ val = 47520000000UL / phy_cfg->tmdsclock; -+ inno_write(inno, 0xd8, (val >> 8) & 0xff); -+ inno_write(inno, 0xd9, val & 0xff); -+ -+ /* Power up post PLL */ -+ inno_update_bits(inno, 0xaa, 1, 0); -+ /* Power up tmds driver */ -+ inno_update_bits(inno, 0xb0, 4, 4); -+ inno_write(inno, 0xb2, 0x0f); -+ -+ /* Wait for post PLL lock */ -+ for (val = 0; val < 5; val++) { -+ if (inno_read(inno, 0xaf) & 1) -+ break; -+ udelay(1000); -+ } -+ if (!(inno_read(inno, 0xaf) & 1)) { -+ printf("HDMI PHY Post PLL unlock\n"); -+ return -ETIMEDOUT; -+ } -+ if (phy_cfg->tmdsclock > 340000000) -+ mdelay(100); -+ /* set pdata_en to 1 */ -+ inno_update_bits(inno, 0x02, 1, 1); -+ -+ return 0; -+} -+ -+static void inno_hdmi_phy_rk3328_power_off(struct inno_hdmi_phy *inno) -+{ -+ /* Power off driver */ -+ inno_write(inno, 0xb2, 0); -+ /* Power off band gap */ -+ inno_update_bits(inno, 0xb0, 4, 0); -+ /* Power off post pll */ -+ inno_update_bits(inno, 0xaa, 1, 1); -+} -+ -+static int -+inno_hdmi_phy_rk3328_pre_pll_update(struct inno_hdmi_phy *inno, -+ const struct pre_pll_config *cfg) -+{ -+ u32 val; -+ -+ /* Power off PLL */ -+ inno_update_bits(inno, 0xa0, 1, 1); -+ /* Configure pre-pll */ -+ inno_update_bits(inno, 0xa0, 2, (cfg->vco_div_5_en & 1) << 1); -+ inno_write(inno, 0xa1, cfg->prediv); -+ if (cfg->fracdiv) -+ val = ((cfg->fbdiv >> 8) & 0x0f) | 0xc0; -+ else -+ val = ((cfg->fbdiv >> 8) & 0x0f) | 0xf0; -+ inno_write(inno, 0xa2, val); -+ inno_write(inno, 0xa3, cfg->fbdiv & 0xff); -+ val = (cfg->pclk_div_a & 0x1f) | -+ ((cfg->pclk_div_b & 3) << 5); -+ inno_write(inno, 0xa5, val); -+ val = (cfg->pclk_div_d & 0x1f) | -+ ((cfg->pclk_div_c & 3) << 5); -+ inno_write(inno, 0xa6, val); -+ val = ((cfg->tmds_div_a & 3) << 4) | -+ ((cfg->tmds_div_b & 3) << 2) | -+ (cfg->tmds_div_c & 3); -+ inno_write(inno, 0xa4, val); -+ -+ if (cfg->fracdiv) { -+ val = cfg->fracdiv & 0xff; -+ inno_write(inno, 0xd3, val); -+ val = (cfg->fracdiv >> 8) & 0xff; -+ inno_write(inno, 0xd2, val); -+ val = (cfg->fracdiv >> 16) & 0xff; -+ inno_write(inno, 0xd1, val); -+ } else { -+ inno_write(inno, 0xd3, 0); -+ inno_write(inno, 0xd2, 0); -+ inno_write(inno, 0xd1, 0); -+ } -+ -+ /* Power up PLL */ -+ inno_update_bits(inno, 0xa0, 1, 0); -+ -+ /* Wait for PLL lock */ -+ for (val = 0; val < 5; val++) { -+ if (inno_read(inno, 0xa9) & 1) -+ break; -+ udelay(1000); -+ } -+ if (val == 5) { -+ printf("Pre-PLL unlock\n"); -+ return -ETIMEDOUT; -+ } -+ -+ return 0; -+} -+ -+static unsigned long -+inno_hdmi_phy_rk3328_pll_recalc_rate(struct inno_hdmi_phy *inno, -+ unsigned long parent_rate) -+{ -+ unsigned long rate, vco, frac; -+ u8 nd, no_a, no_b, no_d; -+ __maybe_unused u8 no_c; -+ u16 nf; -+ -+ nd = inno_read(inno, 0xa1) & 0x3f; -+ nf = ((inno_read(inno, 0xa2) & 0x0f) << 8) | inno_read(inno, 0xa3); -+ vco = parent_rate * nf; -+ if ((inno_read(inno, 0xa2) & 0x30) == 0) { -+ frac = inno_read(inno, 0xd3) | -+ (inno_read(inno, 0xd2) << 8) | -+ (inno_read(inno, 0xd1) << 16); -+ vco += DIV_ROUND_CLOSEST(parent_rate * frac, (1 << 24)); -+ } -+ if (inno_read(inno, 0xa0) & 2) { -+ rate = vco / (nd * 5); -+ } else { -+ no_a = inno_read(inno, 0xa5) & 0x1f; -+ no_b = ((inno_read(inno, 0xa5) >> 5) & 7) + 2; -+ no_c = (1 << ((inno_read(inno, 0xa6) >> 5) & 7)); -+ no_d = inno_read(inno, 0xa6) & 0x1f; -+ if (no_a == 1) -+ rate = vco / (nd * no_b * no_d * 2); -+ else -+ rate = vco / (nd * no_a * no_d * 2); -+ } -+ inno->pixclock = rate; -+ -+ return rate; -+} -+ -+static void inno_hdmi_phy_rk3328_init(struct inno_hdmi_phy *inno) -+{ -+ debug("[PHY] %s: In?\n", __func__); -+ /* -+ * Use phy internal register control -+ * rxsense/poweron/pllpd/pdataen signal. -+ */ -+ inno_write(inno, 0x01, BYPASS_RXSENSE_EN | BYPASS_PWRON_EN | BYPASS_PLLPD_EN); -+ inno_write(inno, 0x02, INT_POL_HIGH | BYPASS_PDATA_EN | RK3328_PDATA_EN); -+ debug("[PHY] %s: done!\n", __func__); -+} -+ -+static const struct inno_hdmi_phy_plat_ops rk3328_hdmi_phy_plat_ops = { -+ .init = inno_hdmi_phy_rk3328_init, -+ .power_on = inno_hdmi_phy_rk3328_power_on, -+ .power_off = inno_hdmi_phy_rk3328_power_off, -+ .pre_pll_update = inno_hdmi_phy_rk3328_pre_pll_update, -+ .recalc_rate = inno_hdmi_phy_rk3328_pll_recalc_rate, -+ .clk_is_prepared = inno_hdmi_phy_rk3328_clk_is_prepared, -+ .clk_prepare = inno_hdmi_phy_rk3328_clk_prepare -+}; -+ -+static void inno_hdmi_phy_rk3228_init(struct inno_hdmi_phy *inno) -+{ -+ debug("[PHY] %s: In?\n", __func__); -+ /* -+ * Use phy internal register control -+ * rxsense/poweron/pllpd/pdataen signal. -+ */ -+ inno_write(inno, 0x01, BYPASS_RXSENSE_EN | BYPASS_PWRON_EN | BYPASS_PLLPD_EN); -+ inno_update_bits(inno, 0x02, BYPASS_PDATA_EN, BYPASS_PDATA_EN); -+ -+ /* manual power down post-PLL */ -+ inno_update_bits(inno, 0xaa, POST_PLL_CTRL_MANUAL, POST_PLL_CTRL_MANUAL); -+ -+ debug("[PHY] %s: done!\n", __func__); -+} -+ -+static int -+inno_hdmi_phy_rk3228_power_on(struct inno_hdmi_phy *inno, -+ const struct post_pll_config *cfg, -+ const struct phy_config *phy_cfg) -+{ -+ u32 val; -+ -+ /* set pdata_en to 0 */ -+ inno_update_bits(inno, 0x02, RK3228_PDATA_EN_DISABLE, RK3228_PDATA_EN_DISABLE); -+ inno_update_bits(inno, 0xe0, RK3228_PRE_PLL_POWER_DOWN | RK3228_POST_PLL_POWER_DOWN, -+ RK3228_PRE_PLL_POWER_DOWN | RK3228_POST_PLL_POWER_DOWN); -+ -+ /* Post-PLL update */ -+ inno_update_bits(inno, 0xe9, RK3228_POST_PLL_PRE_DIV_MASK, -+ RK3228_POST_PLL_PRE_DIV(cfg->prediv)); -+ inno_update_bits(inno, 0xeb, RK3228_POST_PLL_FB_DIV_8_MASK, -+ RK3228_POST_PLL_FB_DIV_8(cfg->fbdiv)); -+ inno_write(inno, 0xea, RK3228_POST_PLL_FB_DIV_7_0(cfg->fbdiv)); -+ -+ if (cfg->postdiv == 1) { -+ inno_update_bits(inno, 0xe9, RK3228_POST_PLL_POST_DIV_ENABLE, 0); -+ } else { -+ int div = cfg->postdiv / 2 - 1; -+ -+ inno_update_bits(inno, 0xe9, RK3228_POST_PLL_POST_DIV_ENABLE, -+ RK3228_POST_PLL_POST_DIV_ENABLE); -+ inno_update_bits(inno, 0xeb, RK3228_POST_PLL_POST_DIV_MASK, -+ RK3228_POST_PLL_POST_DIV(div)); -+ } -+ -+ for (val = 0; val < 4; val++) -+ inno_write(inno, 0xef + val, phy_cfg->regs[val]); -+ -+ inno_update_bits(inno, 0xe0, RK3228_PRE_PLL_POWER_DOWN | -+ RK3228_POST_PLL_POWER_DOWN, 0); -+ inno_update_bits(inno, 0xe1, RK3228_BANDGAP_ENABLE, -+ RK3228_BANDGAP_ENABLE); -+ inno_update_bits(inno, 0xe1, RK3228_TMDS_DRIVER_ENABLE, -+ RK3228_TMDS_DRIVER_ENABLE); -+ -+ /* Wait for post PLL lock, up to 100ms */ -+ for (val = 0; val < 100; val++) { -+ if (inno_read(inno, 0xeb) & RK3228_POST_PLL_LOCK_STATUS) -+ break; -+ udelay(1000); -+ } -+ -+ if (!(inno_read(inno, 0xeb) & RK3228_POST_PLL_LOCK_STATUS)) { -+ printf("%s: HDMI PHY Post PLL unlock\n", __func__); -+ return -ETIMEDOUT; -+ } -+ -+ if (phy_cfg->tmdsclock > 340000000) -+ mdelay(100); -+ -+ /* set pdata_en_disable to 0 */ -+ inno_update_bits(inno, 0x02, RK3228_PDATA_EN_DISABLE, 0); -+ -+ return 0; -+} -+ -+static void inno_hdmi_phy_rk3228_power_off(struct inno_hdmi_phy *inno) -+{ -+ -+ debug("%s\n", __func__); -+ -+ inno_update_bits(inno, 0xe1, RK3228_TMDS_DRIVER_ENABLE, 0); -+ inno_update_bits(inno, 0xe1, RK3228_BANDGAP_ENABLE, 0); -+ inno_update_bits(inno, 0xe0, RK3228_POST_PLL_POWER_DOWN, -+ RK3228_POST_PLL_POWER_DOWN); -+} -+ -+static unsigned long -+inno_hdmi_phy_rk3228_pll_recalc_rate(struct inno_hdmi_phy *inno, -+ unsigned long parent_rate) -+{ -+ u64 rate, vco; -+ u8 nd, no_a, no_b, no_d; -+ __maybe_unused u8 no_c; -+ u16 nf; -+ -+ nd = inno_read(inno, 0xe2) & RK3228_PRE_PLL_PRE_DIV_MASK; -+ nf = (inno_read(inno, 0xe2) & RK3228_PRE_PLL_FB_DIV_8_MASK) << 1; -+ nf |= inno_read(inno, 0xe3); -+ vco = parent_rate * nf; -+ -+ if (inno_read(inno, 0xe2) & RK3228_PCLK_VCO_DIV_5_MASK) { -+ rate = vco / (nd * 5); -+ } else { -+ no_a = inno_read(inno, 0xe4) & RK3228_PRE_PLL_PCLK_DIV_A_MASK; -+ if (!no_a) -+ no_a = 1; -+ no_b = inno_read(inno, 0xe4) & RK3228_PRE_PLL_PCLK_DIV_B_MASK; -+ no_b >>= RK3228_PRE_PLL_PCLK_DIV_B_SHIFT; -+ no_b += 2; -+ no_d = inno_read(inno, 0xe5) & RK3228_PRE_PLL_PCLK_DIV_D_MASK; -+ -+ if (no_a == 1) -+ rate = vco / (nd * no_b * no_d * 2); -+ else -+ rate = vco / (nd * no_a * no_d * 2); -+ -+ } -+ -+ inno->pixclock = rate; -+ -+ debug("%s, pixclock=%llu\n", __func__, rate); -+ -+ return rate; -+} -+ -+static int -+inno_hdmi_phy_rk3228_pre_pll_update(struct inno_hdmi_phy *inno, -+ const struct pre_pll_config *cfg) -+{ -+ u32 val; -+ -+ debug("%s\n", __func__); -+ -+ /* Power down PRE-PLL */ -+ inno_update_bits(inno, 0xe0, RK3228_PRE_PLL_POWER_DOWN, -+ RK3228_PRE_PLL_POWER_DOWN); -+ -+ inno_update_bits(inno, 0xe2, RK3228_PRE_PLL_FB_DIV_8_MASK | -+ RK3228_PCLK_VCO_DIV_5_MASK | -+ RK3228_PRE_PLL_PRE_DIV_MASK, -+ RK3228_PRE_PLL_FB_DIV_8(cfg->fbdiv) | -+ RK3228_PCLK_VCO_DIV_5(cfg->vco_div_5_en) | -+ RK3228_PRE_PLL_PRE_DIV(cfg->prediv)); -+ inno_write(inno, 0xe3, RK3228_PRE_PLL_FB_DIV_7_0(cfg->fbdiv)); -+ inno_update_bits(inno, 0xe4, RK3228_PRE_PLL_PCLK_DIV_B_MASK | -+ RK3228_PRE_PLL_PCLK_DIV_A_MASK, -+ RK3228_PRE_PLL_PCLK_DIV_B(cfg->pclk_div_b) | -+ RK3228_PRE_PLL_PCLK_DIV_A(cfg->pclk_div_a)); -+ inno_update_bits(inno, 0xe5, RK3228_PRE_PLL_PCLK_DIV_C_MASK | -+ RK3228_PRE_PLL_PCLK_DIV_D_MASK, -+ RK3228_PRE_PLL_PCLK_DIV_C(cfg->pclk_div_c) | -+ RK3228_PRE_PLL_PCLK_DIV_D(cfg->pclk_div_d)); -+ inno_update_bits(inno, 0xe6, RK3228_PRE_PLL_TMDSCLK_DIV_C_MASK | -+ RK3228_PRE_PLL_TMDSCLK_DIV_A_MASK | -+ RK3228_PRE_PLL_TMDSCLK_DIV_B_MASK, -+ RK3228_PRE_PLL_TMDSCLK_DIV_C(cfg->tmds_div_c) | -+ RK3228_PRE_PLL_TMDSCLK_DIV_A(cfg->tmds_div_a) | -+ RK3228_PRE_PLL_TMDSCLK_DIV_B(cfg->tmds_div_b)); -+ -+ /* Power up PRE-PLL */ -+ inno_update_bits(inno, 0xe0, RK3228_PRE_PLL_POWER_DOWN, 0); -+ -+ /* Wait for PLL lock, up to 100ms*/ -+ for (val = 0; val < 100; val++) { -+ if (inno_read(inno, 0xe8) & RK3228_PRE_PLL_LOCK_STATUS) -+ break; -+ udelay(1000); -+ } -+ if (!(inno_read(inno, 0xe8) & RK3228_PRE_PLL_LOCK_STATUS)) { -+ printf("%s, failed to lock Pre-PLL, left unlocked\n", __func__); -+ return -ETIMEDOUT; -+ } -+ -+ return 0; -+} -+ -+static const struct inno_hdmi_phy_plat_ops rk3228_hdmi_phy_plat_ops = { -+ .init = inno_hdmi_phy_rk3228_init, -+ .power_on = inno_hdmi_phy_rk3228_power_on, -+ .power_off = inno_hdmi_phy_rk3228_power_off, -+ .pre_pll_update = inno_hdmi_phy_rk3228_pre_pll_update, -+ .recalc_rate = inno_hdmi_phy_rk3228_pll_recalc_rate, -+ .clk_is_prepared = inno_hdmi_phy_rk3228_clk_is_prepared, -+ .clk_prepare = inno_hdmi_phy_rk3228_clk_prepare -+}; -+ -+static unsigned long inno_hdmi_phy_set_pll(struct phy *phy, -+ unsigned long rate) -+{ -+ struct inno_hdmi_phy *inno = dev_get_priv(phy->dev); -+ -+ debug("[PHY] %s: In?\n", __func__); -+ -+ if (inno->data->plat_ops->clk_prepare) -+ inno->data->plat_ops->clk_prepare(inno); -+ -+ if (inno->data->plat_ops->clk_is_prepared) -+ inno->data->plat_ops->clk_is_prepared(inno); -+ -+ inno_hdmi_phy_clk_set_rate(inno, rate); -+ -+ debug("[PHY] %s: done!\n", __func__); -+ -+ return 0; -+} -+ -+static int -+inno_hdmi_phy_set_bus_width(struct phy *phy, u32 bus_width) -+{ -+ struct inno_hdmi_phy *inno = dev_get_priv(phy->dev); -+ -+ debug("[PHY] %s: In?\n", __func__); -+ inno->bus_width = bus_width; -+ debug("[PHY] %s: done!\n", __func__); -+ -+ return 0; -+} -+ -+static long -+inno_hdmi_phy_clk_round_rate(struct phy *phy, unsigned long rate) -+{ -+ struct inno_hdmi_phy *inno = dev_get_priv(phy->dev); -+ const struct pre_pll_config *cfg = pre_pll_cfg_table; -+ u32 tmdsclock = inno_hdmi_phy_get_tmdsclk(inno, rate); -+ int i; -+ -+ debug("[PHY] %s: [rate %ld] In?\n", __func__, rate); -+ for (; cfg->pixclock != ~0UL; cfg++) -+ if (cfg->pixclock == rate) -+ break; -+ -+ /* -+ * If there is no dts phy cfg table, use default phy cfg table. -+ * The tmds clock maximum is 594MHz. So there is no need to check -+ * whether tmds clock is out of range. -+ */ -+ if (!inno->phy_cfg) -+ return cfg->pixclock; -+ -+ /* Check if tmds clock is out of dts phy config's range. */ -+ for (i = 0; inno->phy_cfg[i].tmdsclock != ~0UL; i++) { -+ if (inno->phy_cfg[i].tmdsclock >= tmdsclock) -+ break; -+ } -+ -+ if (inno->phy_cfg[i].tmdsclock == ~0UL) -+ return -EINVAL; -+ -+ debug("[PHY] %s: [pixclock %ld] done!\n", __func__, cfg->pixclock); -+ return cfg->pixclock; -+} -+ -+static int -+inno_hdmi_phy_configure(struct phy *phy, void *params) -+{ -+ struct phy_configure_opts_inno_hdmi *config = params; -+ int ret; -+ unsigned long rate; -+ -+ rate = inno_hdmi_phy_clk_round_rate(phy, config->pixel_clock); -+ if (rate < 0) { -+ printf("failed phy round rate (pixel_clok=%d, rate=%ld)\n", -+ config->pixel_clock, rate); -+ return ret; -+ } -+ -+ inno_hdmi_phy_set_bus_width(phy, config->bus_width); -+ -+ ret = inno_hdmi_phy_set_pll(phy, rate); -+ if (ret) { -+ printf("failed set phy pll (ret=%d)\n", ret); -+ return ret; -+ } -+ -+ return 0; -+ -+} -+ -+static struct phy_ops inno_hdmi_phy_ops = { -+ .power_on = inno_hdmi_phy_power_on, -+ .power_off = inno_hdmi_phy_power_off, -+ .configure = inno_hdmi_phy_configure, -+}; -+ -+static int inno_hdmi_phy_probe(struct udevice *dev) -+{ -+ struct inno_hdmi_phy *inno = dev_get_priv(dev); -+ -+ debug("[PHY] %s: In?\n", __func__); -+ inno->regs = dev_read_addr_ptr(dev); -+ if (!inno->regs) -+ return -ENOMEM; -+ -+ inno->data = (const struct inno_hdmi_phy_data *)dev_get_driver_data(dev); -+ if (!inno->data) -+ return -EINVAL; -+ -+ if (inno->data->plat_ops->init) -+ inno->data->plat_ops->init(inno); -+ -+ debug("[PHY] %s: done!\n", __func__); -+ return 0; -+} -+ -+static const struct inno_hdmi_phy_data rk3328_inno_hdmi_phy_drv_data = { -+ .phy_type = INNO_HDMI_PHY_RK3328, -+ .plat_ops = &rk3328_hdmi_phy_plat_ops, -+ .phy_cfg_table = rk3328_phy_cfg, -+}; -+ -+static const struct inno_hdmi_phy_data rk3228_inno_hdmi_phy_drv_data = { -+ .phy_type = INNO_HDMI_PHY_RK3228, -+ .plat_ops = &rk3228_hdmi_phy_plat_ops, -+ .phy_cfg_table = rk3228_phy_cfg, -+}; -+ -+static const struct udevice_id inno_hdmi_phy_ids[] = { -+ { -+ .compatible = "rockchip,rk3228-hdmi-phy", -+ .data = (ulong)&rk3228_inno_hdmi_phy_drv_data, -+ }, -+ { -+ .compatible = "rockchip,rk3328-hdmi-phy", -+ .data = (ulong)&rk3328_inno_hdmi_phy_drv_data, -+ }, -+ { /* sentile */ } -+}; -+ -+U_BOOT_DRIVER(inno_hdmi_phy) = { -+ .name = "inno_hdmi_phy", -+ .id = UCLASS_PHY, -+ .of_match = inno_hdmi_phy_ids, -+ .ops = &inno_hdmi_phy_ops, -+ .probe = inno_hdmi_phy_probe, -+ .priv_auto = sizeof(struct inno_hdmi_phy), -+}; -diff --git a/include/inno/phy-inno-hdmi.h b/include/inno/phy-inno-hdmi.h -new file mode 100644 -index 0000000000..a73712c921 ---- /dev/null -+++ b/include/inno/phy-inno-hdmi.h -@@ -0,0 +1,30 @@ -+/* SPDX-License-Identifier: GPL-2.0 */ -+ -+#ifndef __PHY_INNO_HDMI_H_ -+#define __PHY_INNO_HDMI_H_ -+ -+/** -+ * struct phy_configure_opts_inno_hdmi - INNO HDMI configuration set -+ * -+ * This structure is used to represent the configuration state of a -+ * INNO HDMI phy. -+ */ -+struct phy_configure_opts_inno_hdmi { -+ /** -+ * @pixel_clock: -+ * -+ * pixel clock rate in Hertz -+ * -+ */ -+ unsigned int pixel_clock; -+ -+ /** -+ * @bus_width: -+ * -+ * bus width to assign -+ */ -+ unsigned int bus_width; -+ -+}; -+ -+#endif /* __PHY_INNO_HDMI_H_ */ diff --git a/patch/u-boot/v2024.01/general-dwc-otg-fix-var.patch b/patch/u-boot/v2024.01/general-dwc-otg-fix-var.patch deleted file mode 100644 index 1573cdbdcefc..000000000000 --- a/patch/u-boot/v2024.01/general-dwc-otg-fix-var.patch +++ /dev/null @@ -1,30 +0,0 @@ -From ac3f6f2e9cbe96d11a0db2801699669b2941cd09 Mon Sep 17 00:00:00 2001 -From: Paolo Sabatino -Date: Mon, 29 Apr 2024 16:17:17 +0200 -Subject: [PATCH 1/4] fix borked DWC2 OTG driver - ---- - drivers/usb/gadget/dwc2_udc_otg_phy.c | 7 +------ - 1 file changed, 1 insertion(+), 6 deletions(-) - -diff --git a/drivers/usb/gadget/dwc2_udc_otg_phy.c b/drivers/usb/gadget/dwc2_udc_otg_phy.c -index 7f8e9564b9..e87f8b5e47 100644 ---- a/drivers/usb/gadget/dwc2_udc_otg_phy.c -+++ b/drivers/usb/gadget/dwc2_udc_otg_phy.c -@@ -59,12 +59,7 @@ void otg_phy_init(struct dwc2_udc *dev) - writel((readl(&phy->phypwr) &~(OTG_DISABLE_0 | ANALOG_PWRDOWN) - &~FORCE_SUSPEND_0), &phy->phypwr); - -- if (s5p_cpu_id == 0x4412) -- writel((readl(&phy->phyclk) & ~(EXYNOS4X12_ID_PULLUP0 | -- EXYNOS4X12_COMMON_ON_N0)) | EXYNOS4X12_CLK_SEL_24MHZ, -- &phy->phyclk); /* PLL 24Mhz */ -- else -- writel((readl(&phy->phyclk) & ~(ID_PULLUP0 | COMMON_ON_N0)) | -+ writel((readl(&phy->phyclk) & ~(ID_PULLUP0 | COMMON_ON_N0)) | - CLK_SEL_24MHZ, &phy->phyclk); /* PLL 24Mhz */ - - writel((readl(&phy->rstcon) &~(LINK_SW_RST | PHYLNK_SW_RST)) --- -2.34.1 - diff --git a/patch/u-boot/v2024.01/board_rk322x-box/rk3228-hdmi-clk-fixes.patch b/patch/u-boot/v2024.07/board_rk322x-box/rk3228-hdmi-clk-fixes.patch similarity index 100% rename from patch/u-boot/v2024.01/board_rk322x-box/rk3228-hdmi-clk-fixes.patch rename to patch/u-boot/v2024.07/board_rk322x-box/rk3228-hdmi-clk-fixes.patch diff --git a/patch/u-boot/v2024.01/board_rk322x-box/rk3228-hdmi-driver.patch b/patch/u-boot/v2024.07/board_rk322x-box/rk3228-hdmi-driver.patch similarity index 81% rename from patch/u-boot/v2024.01/board_rk322x-box/rk3228-hdmi-driver.patch rename to patch/u-boot/v2024.07/board_rk322x-box/rk3228-hdmi-driver.patch index a246f81814bf..1327abf4529f 100644 --- a/patch/u-boot/v2024.01/board_rk322x-box/rk3228-hdmi-driver.patch +++ b/patch/u-boot/v2024.07/board_rk322x-box/rk3228-hdmi-driver.patch @@ -1,19 +1,32 @@ -From eb306bf33a53aabf66754f70f61c01348e768d91 Mon Sep 17 00:00:00 2001 +From 98792aa8f196df9f771c52e5bcac2c34a2937cd2 Mon Sep 17 00:00:00 2001 From: Paolo Sabatino -Date: Mon, 29 Apr 2024 16:18:27 +0200 -Subject: [PATCH 3/4] rockchip rk3228 HDMI driver +Date: Sun, 30 Jun 2024 17:37:39 +0200 +Subject: [PATCH] rk3228 hdmi driver --- - drivers/video/rockchip/rk3228_hdmi.c | 161 +++++++++++++++++++++++++++ - 1 file changed, 161 insertions(+) + drivers/video/rockchip/Makefile | 1 + + drivers/video/rockchip/rk3228_hdmi.c | 168 +++++++++++++++++++++++++++ + 2 files changed, 169 insertions(+) create mode 100644 drivers/video/rockchip/rk3228_hdmi.c +diff --git a/drivers/video/rockchip/Makefile b/drivers/video/rockchip/Makefile +index f55beceebf..ac55864a33 100644 +--- a/drivers/video/rockchip/Makefile ++++ b/drivers/video/rockchip/Makefile +@@ -10,6 +10,7 @@ obj-$(CONFIG_ROCKCHIP_RK3328) += rk3328_vop.o + obj-$(CONFIG_ROCKCHIP_RK3399) += rk3399_vop.o + obj-$(CONFIG_DISPLAY_ROCKCHIP_EDP) += rk_edp.o + obj-$(CONFIG_DISPLAY_ROCKCHIP_LVDS) += rk_lvds.o ++obj-hdmi-$(CONFIG_ROCKCHIP_RK322X) += rk3228_hdmi.o + obj-hdmi-$(CONFIG_ROCKCHIP_RK3288) += rk3288_hdmi.o + obj-hdmi-$(CONFIG_ROCKCHIP_RK3328) += rk3328_hdmi.o + obj-hdmi-$(CONFIG_ROCKCHIP_RK3399) += rk3399_hdmi.o diff --git a/drivers/video/rockchip/rk3228_hdmi.c b/drivers/video/rockchip/rk3228_hdmi.c new file mode 100644 -index 0000000000..ec67790c71 +index 0000000000..3a95fcf0d8 --- /dev/null +++ b/drivers/video/rockchip/rk3228_hdmi.c -@@ -0,0 +1,179 @@ +@@ -0,0 +1,168 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (c) 2023 Edgeble AI Technologies Pvt. Ltd. @@ -26,7 +39,6 @@ index 0000000000..ec67790c71 +#include +#include +#include -+#include +#include "rk_hdmi.h" + +#define HIWORD_UPDATE(val, mask) (val | (mask) << 16) @@ -52,16 +64,11 @@ index 0000000000..ec67790c71 +static int rk3228_dw_hdmi_phy_cfg(struct dw_hdmi *hdmi, uint pixclock) +{ + struct rk_hdmi_priv *priv = container_of(hdmi, struct rk_hdmi_priv, hdmi); -+ struct phy_configure_opts_inno_hdmi params; + int ret; + -+ params.pixel_clock = pixclock; -+ params.bus_width = 8; -+ -+ ret = generic_phy_configure(&priv->phy, ¶ms); ++ ret = generic_phy_init(&priv->phy); + if (ret < 0) { -+ printf("failed to configure phy (pixel_clock=%d, bus_width=%d)\n", -+ params.pixel_clock, params.bus_width); ++ printf("failed to init phy (ret=%d)\n", ret); + return ret; + } + @@ -97,11 +104,6 @@ index 0000000000..ec67790c71 + .setup_hpd = rk3228_dw_hdmi_setup_hpd, +}; + -+static const struct dw_hdmi_plat_data dw_hdmi_rk3228_plat_data = { -+ .phy_force_vendor = true, -+ .phy_ops = &dw_hdmi_rk3228_phy_ops, -+}; -+ +static int rk3228_hdmi_of_to_plat(struct udevice *dev) +{ + struct rk_hdmi_priv *priv = dev_get_priv(dev); @@ -112,7 +114,7 @@ index 0000000000..ec67790c71 + + rk_hdmi_of_to_plat(dev); + -+ hdmi->data = &dw_hdmi_rk3228_plat_data; ++ hdmi->ops = &dw_hdmi_rk3228_phy_ops; + + return 0; +} @@ -193,19 +195,6 @@ index 0000000000..ec67790c71 + .remove = rk3228_hdmi_remove, + .flags = DM_FLAG_OS_PREPARE +}; -diff --git a/drivers/video/rockchip/Makefile b/drivers/video/rockchip/Makefile -index 8128289cc8..10a98e8c5a 100644 ---- a/drivers/video/rockchip/Makefile -+++ b/drivers/video/rockchip/Makefile -@@ -10,6 +10,7 @@ obj-$(CONFIG_ROCKCHIP_RK3399) += rk3399_vop.o - obj-$(CONFIG_DISPLAY_ROCKCHIP_EDP) += rk_edp.o - obj-$(CONFIG_DISPLAY_ROCKCHIP_LVDS) += rk_lvds.o - obj-hdmi-$(CONFIG_ROCKCHIP_RK3288) += rk3288_hdmi.o -+obj-hdmi-$(CONFIG_ROCKCHIP_RK322X) += rk3228_hdmi.o - obj-hdmi-$(CONFIG_ROCKCHIP_RK3399) += rk3399_hdmi.o - obj-$(CONFIG_DISPLAY_ROCKCHIP_HDMI) += rk_hdmi.o $(obj-hdmi-y) - obj-mipi-$(CONFIG_ROCKCHIP_RK3288) += rk3288_mipi.o -- 2.34.1 - diff --git a/patch/u-boot/v2024.07/board_rk322x-box/rk3228-inno-phy-driver.patch b/patch/u-boot/v2024.07/board_rk322x-box/rk3228-inno-phy-driver.patch new file mode 100644 index 000000000000..3860ea2ab4a5 --- /dev/null +++ b/patch/u-boot/v2024.07/board_rk322x-box/rk3228-inno-phy-driver.patch @@ -0,0 +1,493 @@ +From 3f6e2571e3bc164fceacc2057476fdf0724f1131 Mon Sep 17 00:00:00 2001 +From: Paolo Sabatino +Date: Sun, 30 Jun 2024 17:18:22 +0200 +Subject: [PATCH] add rk3228 support to inno hdmi driver + +--- + drivers/phy/rockchip/phy-rockchip-inno-hdmi.c | 379 ++++++++++++++++++ + 1 file changed, 379 insertions(+) + +diff --git a/drivers/phy/rockchip/phy-rockchip-inno-hdmi.c b/drivers/phy/rockchip/phy-rockchip-inno-hdmi.c +index 604e2703da..e41428be22 100644 +--- a/drivers/phy/rockchip/phy-rockchip-inno-hdmi.c ++++ b/drivers/phy/rockchip/phy-rockchip-inno-hdmi.c +@@ -19,6 +19,110 @@ + + #define UPDATE(x, h, l) (((x) << (l)) & GENMASK((h), (l))) + ++/* ++ * ---- Registers for RK322x ++ */ ++/* REG: 0x00 */ ++#define RK3228_PRE_PLL_REFCLK_SEL_MASK BIT(0) ++#define RK3228_PRE_PLL_REFCLK_SEL_PCLK BIT(0) ++#define RK3228_PRE_PLL_REFCLK_SEL_OSCCLK 0 ++/* REG: 0x01 */ ++#define RK3228_BYPASS_RXSENSE_EN BIT(2) ++#define RK3228_BYPASS_PWRON_EN BIT(1) ++#define RK3228_BYPASS_PLLPD_EN BIT(0) ++/* REG: 0x02 */ ++#define RK3228_INT_POL_HIGH BIT(7) ++#define RK3228_BYPASS_PDATA_EN BIT(4) ++#define RK3328_PDATA_EN BIT(0) ++#define RK3228_PDATA_EN_DISABLE BIT(0) ++/* REG: 0x03 */ ++#define RK3228_BYPASS_AUTO_TERM_RES_CAL BIT(7) ++#define RK3228_AUDO_TERM_RES_CAL_SPEED_14_8(x) UPDATE(x, 6, 0) ++/* REG: 0x04 */ ++#define RK3228_AUDO_TERM_RES_CAL_SPEED_7_0(x) UPDATE(x, 7, 0) ++/* REG: 0xaa */ ++#define RK3228_POST_PLL_CTRL_MANUAL BIT(0) ++/* REG: 0xe0 */ ++#define RK3228_POST_PLL_POWER_DOWN BIT(5) ++#define RK3228_POST_PLL_POWER_UP 0 ++#define RK3228_PRE_PLL_POWER_DOWN BIT(4) ++#define RK3228_RXSENSE_CLK_CH_MASK BIT(3) ++#define RK3228_RXSENSE_CLK_CH_ENABLE BIT(3) ++#define RK3228_RXSENSE_DATA_CH2_MASK BIT(2) ++#define RK3228_RXSENSE_DATA_CH2_ENABLE BIT(2) ++#define RK3228_RXSENSE_DATA_CH1_MASK BIT(1) ++#define RK3228_RXSENSE_DATA_CH1_ENABLE BIT(1) ++#define RK3228_RXSENSE_DATA_CH0_MASK BIT(0) ++#define RK3228_RXSENSE_DATA_CH0_ENABLE BIT(0) ++/* REG: 0xe1 */ ++#define RK3228_BANDGAP_ENABLE BIT(4) ++#define RK3228_TMDS_DRIVER_ENABLE GENMASK(3, 0) ++/* REG: 0xe2 */ ++#define RK3228_PRE_PLL_FB_DIV_8_MASK BIT(7) ++#define RK3228_PRE_PLL_FB_DIV_8(x) UPDATE((x) >> 8, 7, 7) ++#define RK3228_PCLK_VCO_DIV_5_MASK BIT(5) ++#define RK3228_PCLK_VCO_DIV_5(x) UPDATE(x, 5, 5) ++#define RK3228_PRE_PLL_PRE_DIV_MASK GENMASK(4, 0) ++#define RK3228_PRE_PLL_PRE_DIV(x) UPDATE(x, 4, 0) ++/* REG: 0xe3 */ ++#define RK3228_PRE_PLL_FB_DIV_7_0(x) UPDATE(x, 7, 0) ++/* REG: 0xe4 */ ++#define RK3228_PRE_PLL_PCLK_DIV_B_MASK GENMASK(6, 5) ++#define RK3228_PRE_PLL_PCLK_DIV_B_SHIFT 5 ++#define RK3228_PRE_PLL_PCLK_DIV_B(x) UPDATE(x, 6, 5) ++#define RK3228_PRE_PLL_PCLK_DIV_A_MASK GENMASK(4, 0) ++#define RK3228_PRE_PLL_PCLK_DIV_A(x) UPDATE(x, 4, 0) ++/* REG: 0xe5 */ ++#define RK3228_PRE_PLL_PCLK_DIV_C_MASK GENMASK(6, 5) ++#define RK3228_PRE_PLL_PCLK_DIV_C(x) UPDATE(x, 6, 5) ++#define RK3228_PRE_PLL_PCLK_DIV_D_MASK GENMASK(4, 0) ++#define RK3228_PRE_PLL_PCLK_DIV_D(x) UPDATE(x, 4, 0) ++/* REG: 0xe6 */ ++#define RK3228_PRE_PLL_TMDSCLK_DIV_C_MASK GENMASK(5, 4) ++#define RK3228_PRE_PLL_TMDSCLK_DIV_C(x) UPDATE(x, 5, 4) ++#define RK3228_PRE_PLL_TMDSCLK_DIV_A_MASK GENMASK(3, 2) ++#define RK3228_PRE_PLL_TMDSCLK_DIV_A(x) UPDATE(x, 3, 2) ++#define RK3228_PRE_PLL_TMDSCLK_DIV_B_MASK GENMASK(1, 0) ++#define RK3228_PRE_PLL_TMDSCLK_DIV_B(x) UPDATE(x, 1, 0) ++/* REG: 0xe8 */ ++#define RK3228_PRE_PLL_LOCK_STATUS BIT(0) ++/* REG: 0xe9 */ ++#define RK3228_POST_PLL_POST_DIV_ENABLE UPDATE(3, 7, 6) ++#define RK3228_POST_PLL_PRE_DIV_MASK GENMASK(4, 0) ++#define RK3228_POST_PLL_PRE_DIV(x) UPDATE(x, 4, 0) ++/* REG: 0xea */ ++#define RK3228_POST_PLL_FB_DIV_7_0(x) UPDATE(x, 7, 0) ++/* REG: 0xeb */ ++#define RK3228_POST_PLL_FB_DIV_8_MASK BIT(7) ++#define RK3228_POST_PLL_FB_DIV_8(x) UPDATE((x) >> 8, 7, 7) ++#define RK3228_POST_PLL_POST_DIV_MASK GENMASK(5, 4) ++#define RK3228_POST_PLL_POST_DIV(x) UPDATE(x, 5, 4) ++#define RK3228_POST_PLL_LOCK_STATUS BIT(0) ++/* REG: 0xee */ ++#define RK3228_TMDS_CH_TA_ENABLE GENMASK(7, 4) ++/* REG: 0xef */ ++#define RK3228_TMDS_CLK_CH_TA(x) UPDATE(x, 7, 6) ++#define RK3228_TMDS_DATA_CH2_TA(x) UPDATE(x, 5, 4) ++#define RK3228_TMDS_DATA_CH1_TA(x) UPDATE(x, 3, 2) ++#define RK3228_TMDS_DATA_CH0_TA(x) UPDATE(x, 1, 0) ++/* REG: 0xf0 */ ++#define RK3228_TMDS_DATA_CH2_PRE_EMPHASIS_MASK GENMASK(5, 4) ++#define RK3228_TMDS_DATA_CH2_PRE_EMPHASIS(x) UPDATE(x, 5, 4) ++#define RK3228_TMDS_DATA_CH1_PRE_EMPHASIS_MASK GENMASK(3, 2) ++#define RK3228_TMDS_DATA_CH1_PRE_EMPHASIS(x) UPDATE(x, 3, 2) ++#define RK3228_TMDS_DATA_CH0_PRE_EMPHASIS_MASK GENMASK(1, 0) ++#define RK3228_TMDS_DATA_CH0_PRE_EMPHASIS(x) UPDATE(x, 1, 0) ++/* REG: 0xf1 */ ++#define RK3228_TMDS_CLK_CH_OUTPUT_SWING(x) UPDATE(x, 7, 4) ++#define RK3228_TMDS_DATA_CH2_OUTPUT_SWING(x) UPDATE(x, 3, 0) ++/* REG: 0xf2 */ ++#define RK3228_TMDS_DATA_CH1_OUTPUT_SWING(x) UPDATE(x, 7, 4) ++#define RK3228_TMDS_DATA_CH0_OUTPUT_SWING(x) UPDATE(x, 3, 0) ++ ++ ++/* ++ * ---- Registers for RK3328 ++ */ + /* REG: 0x01 */ + #define RK3328_BYPASS_RXSENSE_EN BIT(2) + #define RK3328_BYPASS_POWERON_EN BIT(1) +@@ -177,6 +281,7 @@ struct inno_hdmi_phy_plat_ops { + }; + + enum inno_hdmi_phy_type { ++ INNO_HDMI_PHY_RK3228, + INNO_HDMI_PHY_RK3328, + }; + +@@ -388,6 +493,25 @@ static const struct post_pll_config post_pll_cfg_table[] = { + { /* sentinel */ } + }; + ++/* phy tuning values for an undocumented set of registers */ ++static const struct phy_config rk3228_phy_cfg[] = { ++ { 165000000, { ++ 0xaa, 0x00, 0x44, 0x44, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, ++ }, ++ }, { ++ 340000000, { ++ 0xaa, 0x15, 0x6a, 0xaa, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, ++ }, ++ }, { ++ 594000000, { ++ 0xaa, 0x15, 0x7a, 0xaa, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, ++ }, ++ }, { /* sentinel */ }, ++}; ++ + /* phy tuning values for an undocumented set of registers */ + static const struct phy_config rk3328_phy_cfg[] = { + { 165000000, { +@@ -453,6 +577,46 @@ static unsigned long inno_hdmi_phy_get_tmdsclk(struct inno_hdmi_phy *inno, + } + } + ++static ++unsigned long inno_hdmi_phy_rk3228_clk_recalc_rate(struct phy *phy, ++ unsigned long parent_rate) ++{ ++ struct inno_hdmi_phy *inno = dev_get_priv(phy->dev); ++ u64 rate, vco; ++ u8 nd, no_a, no_b, no_d; ++ __maybe_unused u8 no_c; ++ u16 nf; ++ ++ nd = inno_read(inno, 0xe2) & RK3228_PRE_PLL_PRE_DIV_MASK; ++ nf = (inno_read(inno, 0xe2) & RK3228_PRE_PLL_FB_DIV_8_MASK) << 1; ++ nf |= inno_read(inno, 0xe3); ++ vco = parent_rate * nf; ++ ++ if (inno_read(inno, 0xe2) & RK3228_PCLK_VCO_DIV_5_MASK) { ++ rate = vco / (nd * 5); ++ } else { ++ no_a = inno_read(inno, 0xe4) & RK3228_PRE_PLL_PCLK_DIV_A_MASK; ++ if (!no_a) ++ no_a = 1; ++ no_b = inno_read(inno, 0xe4) & RK3228_PRE_PLL_PCLK_DIV_B_MASK; ++ no_b >>= RK3228_PRE_PLL_PCLK_DIV_B_SHIFT; ++ no_b += 2; ++ no_d = inno_read(inno, 0xe5) & RK3228_PRE_PLL_PCLK_DIV_D_MASK; ++ ++ if (no_a == 1) ++ rate = vco / (nd * no_b * no_d * 2); ++ else ++ rate = vco / (nd * no_a * no_d * 2); ++ ++ } ++ ++ inno->pixclock = rate; ++ ++ dev_info(phy->dev, "rate %lu vco %llu\n", inno->pixclock, vco); ++ ++ return inno->pixclock; ++} ++ + static + unsigned long inno_hdmi_phy_rk3328_clk_recalc_rate(struct phy *phy, + unsigned long parent_rate) +@@ -494,6 +658,23 @@ unsigned long inno_hdmi_phy_rk3328_clk_recalc_rate(struct phy *phy, + return inno->pixclock; + } + ++static long inno_hdmi_phy_rk3228_clk_round_rate(struct phy *phy, ++ unsigned long rate) ++{ ++ const struct pre_pll_config *cfg = pre_pll_cfg_table; ++ ++ rate = (rate / 1000) * 1000; ++ ++ for (; cfg->pixclock != 0; cfg++) ++ if (cfg->pixclock == rate) ++ break; ++ ++ if (cfg->pixclock == 0) ++ return -EINVAL; ++ ++ return cfg->pixclock; ++} ++ + static long inno_hdmi_phy_rk3328_clk_round_rate(struct phy *phy, + unsigned long rate) + { +@@ -528,6 +709,71 @@ struct pre_pll_config *inno_hdmi_phy_get_pre_pll_cfg(struct inno_hdmi_phy *inno, + return cfg; + } + ++static int ++inno_hdmi_phy_rk3228_clk_set_rate(struct phy *phy, ++ unsigned long rate, ++ unsigned long parent_rate) ++{ ++ ++ struct inno_hdmi_phy *inno = dev_get_priv(phy->dev); ++ unsigned long tmdsclock = inno_hdmi_phy_get_tmdsclk(inno, rate); ++ const struct pre_pll_config *cfg; ++ ++ int ret; ++ u32 val; ++ ++ dev_info(phy->dev, "rate %lu tmdsclk %lu\n", rate, tmdsclock); ++ ++ if (inno->pixclock == rate && inno->tmdsclock == tmdsclock) ++ return 0; ++ ++ cfg = inno_hdmi_phy_get_pre_pll_cfg(inno, rate); ++ if (IS_ERR(cfg)) ++ return PTR_ERR(cfg); ++ ++ /* Power down PRE-PLL */ ++ inno_update_bits(inno, 0xe0, RK3228_PRE_PLL_POWER_DOWN, ++ RK3228_PRE_PLL_POWER_DOWN); ++ ++ inno_update_bits(inno, 0xe2, RK3228_PRE_PLL_FB_DIV_8_MASK | ++ RK3228_PCLK_VCO_DIV_5_MASK | ++ RK3228_PRE_PLL_PRE_DIV_MASK, ++ RK3228_PRE_PLL_FB_DIV_8(cfg->fbdiv) | ++ RK3228_PCLK_VCO_DIV_5(cfg->vco_div_5_en) | ++ RK3228_PRE_PLL_PRE_DIV(cfg->prediv)); ++ inno_write(inno, 0xe3, RK3228_PRE_PLL_FB_DIV_7_0(cfg->fbdiv)); ++ inno_update_bits(inno, 0xe4, RK3228_PRE_PLL_PCLK_DIV_B_MASK | ++ RK3228_PRE_PLL_PCLK_DIV_A_MASK, ++ RK3228_PRE_PLL_PCLK_DIV_B(cfg->pclk_div_b) | ++ RK3228_PRE_PLL_PCLK_DIV_A(cfg->pclk_div_a)); ++ inno_update_bits(inno, 0xe5, RK3228_PRE_PLL_PCLK_DIV_C_MASK | ++ RK3228_PRE_PLL_PCLK_DIV_D_MASK, ++ RK3228_PRE_PLL_PCLK_DIV_C(cfg->pclk_div_c) | ++ RK3228_PRE_PLL_PCLK_DIV_D(cfg->pclk_div_d)); ++ inno_update_bits(inno, 0xe6, RK3228_PRE_PLL_TMDSCLK_DIV_C_MASK | ++ RK3228_PRE_PLL_TMDSCLK_DIV_A_MASK | ++ RK3228_PRE_PLL_TMDSCLK_DIV_B_MASK, ++ RK3228_PRE_PLL_TMDSCLK_DIV_C(cfg->tmds_div_c) | ++ RK3228_PRE_PLL_TMDSCLK_DIV_A(cfg->tmds_div_a) | ++ RK3228_PRE_PLL_TMDSCLK_DIV_B(cfg->tmds_div_b)); ++ ++ /* Power up PRE-PLL */ ++ inno_update_bits(inno, 0xe0, RK3228_PRE_PLL_POWER_DOWN, 0); ++ ++ /* Wait for Pre-PLL lock */ ++ ret = inno_poll(inno, 0xe8, val, val & RK3228_PRE_PLL_LOCK_STATUS, ++ 1000, 10000); ++ if (ret) { ++ dev_err(phy->dev, "Pre-PLL locking failed\n"); ++ return ret; ++ } ++ ++ inno->pixclock = rate; ++ inno->tmdsclock = tmdsclock; ++ ++ return 0; ++} ++ + static int + inno_hdmi_phy_rk3328_clk_set_rate(struct phy *phy, + unsigned long rate, +@@ -588,6 +834,13 @@ inno_hdmi_phy_rk3328_clk_set_rate(struct phy *phy, + return 0; + } + ++static void inno_hdmi_phy_rk3228_clk_enable(struct phy *phy) ++{ ++ struct inno_hdmi_phy *inno = dev_get_priv(phy->dev); ++ ++ inno_update_bits(inno, 0xe0, RK3228_PRE_PLL_POWER_DOWN, 0); ++} ++ + static void inno_hdmi_phy_rk3328_clk_enable(struct phy *phy) + { + struct inno_hdmi_phy *inno = dev_get_priv(phy->dev); +@@ -595,6 +848,14 @@ static void inno_hdmi_phy_rk3328_clk_enable(struct phy *phy) + inno_update_bits(inno, 0xa0, RK3328_PRE_PLL_POWER_DOWN, 0); + } + ++static void inno_hdmi_phy_rk3228_clk_disable(struct phy *phy) ++{ ++ struct inno_hdmi_phy *inno = dev_get_priv(phy->dev); ++ ++ inno_update_bits(inno, 0xe0, RK3228_PRE_PLL_POWER_DOWN, ++ RK3228_PRE_PLL_POWER_DOWN); ++} ++ + static void inno_hdmi_phy_rk3328_clk_disable(struct phy *phy) + { + struct inno_hdmi_phy *inno = dev_get_priv(phy->dev); +@@ -603,6 +864,65 @@ static void inno_hdmi_phy_rk3328_clk_disable(struct phy *phy) + RK3328_PRE_PLL_POWER_DOWN); + } + ++static int ++inno_hdmi_phy_rk3228_power_on(struct phy *phy, ++ const struct post_pll_config *cfg, ++ const struct phy_config *phy_cfg) ++{ ++ struct inno_hdmi_phy *inno = dev_get_priv(phy->dev); ++ u32 val; ++ int ret; ++ ++ /* set pdata_en to 0 */ ++ inno_update_bits(inno, 0x02, RK3228_PDATA_EN_DISABLE, RK3228_PDATA_EN_DISABLE); ++ inno_update_bits(inno, 0xe0, RK3228_PRE_PLL_POWER_DOWN | RK3228_POST_PLL_POWER_DOWN, ++ RK3228_PRE_PLL_POWER_DOWN | RK3228_POST_PLL_POWER_DOWN); ++ ++ /* Post-PLL update */ ++ inno_update_bits(inno, 0xe9, RK3228_POST_PLL_PRE_DIV_MASK, ++ RK3228_POST_PLL_PRE_DIV(cfg->prediv)); ++ inno_update_bits(inno, 0xeb, RK3228_POST_PLL_FB_DIV_8_MASK, ++ RK3228_POST_PLL_FB_DIV_8(cfg->fbdiv)); ++ inno_write(inno, 0xea, RK3228_POST_PLL_FB_DIV_7_0(cfg->fbdiv)); ++ ++ if (cfg->postdiv == 1) { ++ inno_update_bits(inno, 0xe9, RK3228_POST_PLL_POST_DIV_ENABLE, 0); ++ } else { ++ int div = cfg->postdiv / 2 - 1; ++ ++ inno_update_bits(inno, 0xe9, RK3228_POST_PLL_POST_DIV_ENABLE, ++ RK3228_POST_PLL_POST_DIV_ENABLE); ++ inno_update_bits(inno, 0xeb, RK3228_POST_PLL_POST_DIV_MASK, ++ RK3228_POST_PLL_POST_DIV(div)); ++ } ++ ++ for (val = 0; val < 4; val++) ++ inno_write(inno, 0xef + val, phy_cfg->regs[val]); ++ ++ inno_update_bits(inno, 0xe0, RK3228_PRE_PLL_POWER_DOWN | ++ RK3228_POST_PLL_POWER_DOWN, 0); ++ inno_update_bits(inno, 0xe1, RK3228_BANDGAP_ENABLE, ++ RK3228_BANDGAP_ENABLE); ++ inno_update_bits(inno, 0xe1, RK3228_TMDS_DRIVER_ENABLE, ++ RK3228_TMDS_DRIVER_ENABLE); ++ ++ /* Wait for post PLL lock */ ++ ret = inno_poll(inno, 0xeb, val, val & RK3228_POST_PLL_LOCK_STATUS, ++ 1000, 10000); ++ if (ret) { ++ dev_err(phy->dev, "Post-PLL locking failed\n"); ++ return ret; ++ } ++ ++ if (phy_cfg->tmdsclock > 340000000) ++ mdelay(100); ++ ++ /* set pdata_en_disable to 0 */ ++ inno_update_bits(inno, 0x02, RK3228_PDATA_EN_DISABLE, 0); ++ ++ return 0; ++} ++ + static int + inno_hdmi_phy_rk3328_power_on(struct phy *phy, + const struct post_pll_config *cfg, +@@ -695,6 +1015,18 @@ inno_hdmi_phy_rk3328_power_on(struct phy *phy, + return 0; + } + ++static void inno_hdmi_phy_rk3228_power_off(struct phy *phy) ++{ ++ struct inno_hdmi_phy *inno = dev_get_priv(phy->dev); ++ ++ debug("%s\n", __func__); ++ ++ inno_update_bits(inno, 0xe1, RK3228_TMDS_DRIVER_ENABLE, 0); ++ inno_update_bits(inno, 0xe1, RK3228_BANDGAP_ENABLE, 0); ++ inno_update_bits(inno, 0xe0, RK3228_POST_PLL_POWER_DOWN, ++ RK3228_POST_PLL_POWER_DOWN); ++} ++ + static void inno_hdmi_phy_rk3328_power_off(struct phy *phy) + { + struct inno_hdmi_phy *inno = dev_get_priv(phy->dev); +@@ -709,6 +1041,32 @@ static void inno_hdmi_phy_rk3328_power_off(struct phy *phy) + inno_write(inno, 0x07, 0); + } + ++static void inno_hdmi_phy_rk3228_init(struct phy *phy) ++{ ++ struct inno_hdmi_phy *inno = dev_get_priv(phy->dev); ++ const struct inno_hdmi_phy_plat_ops *plat_ops = inno->data->plat_ops; ++ ++ debug("[PHY] %s: begin!\n", __func__); ++ ++ /* ++ * Use phy internal register control ++ * rxsense/poweron/pllpd/pdataen signal. ++ */ ++ inno_write(inno, 0x01, RK3228_BYPASS_RXSENSE_EN | RK3228_BYPASS_PWRON_EN | RK3228_BYPASS_PLLPD_EN); ++ inno_update_bits(inno, 0x02, RK3228_BYPASS_PDATA_EN, RK3228_BYPASS_PDATA_EN); ++ ++ /* manual power down post-PLL */ ++ inno_update_bits(inno, 0xaa, RK3228_POST_PLL_CTRL_MANUAL, RK3228_POST_PLL_CTRL_MANUAL); ++ ++ if (plat_ops->clk_recalc_rate) ++ plat_ops->clk_recalc_rate(phy, clk_get_rate(&inno->refoclk)); ++ ++ if (plat_ops->clk_round_rate) ++ plat_ops->clk_round_rate(phy, inno->pixclock); ++ ++ debug("[PHY] %s: done!\n", __func__); ++} ++ + static void inno_hdmi_phy_rk3328_init(struct phy *phy) + { + struct inno_hdmi_phy *inno = dev_get_priv(phy->dev); +@@ -735,6 +1093,17 @@ static void inno_hdmi_phy_rk3328_init(struct phy *phy) + plat_ops->clk_round_rate(phy, inno->pixclock); + } + ++static const struct inno_hdmi_phy_plat_ops rk3228_hdmi_phy_plat_ops = { ++ .init = inno_hdmi_phy_rk3228_init, ++ .power_on = inno_hdmi_phy_rk3228_power_on, ++ .power_off = inno_hdmi_phy_rk3228_power_off, ++ .clk_enable = inno_hdmi_phy_rk3228_clk_enable, ++ .clk_disable = inno_hdmi_phy_rk3228_clk_disable, ++ .clk_recalc_rate = inno_hdmi_phy_rk3228_clk_recalc_rate, ++ .clk_round_rate = inno_hdmi_phy_rk3228_clk_round_rate, ++ .clk_set_rate = inno_hdmi_phy_rk3228_clk_set_rate, ++}; ++ + static const struct inno_hdmi_phy_plat_ops rk3328_hdmi_phy_plat_ops = { + .init = inno_hdmi_phy_rk3328_init, + .power_on = inno_hdmi_phy_rk3328_power_on, +@@ -861,6 +1230,12 @@ static int inno_hdmi_phy_probe(struct udevice *dev) + return 0; + } + ++static const struct inno_hdmi_phy_data rk3228_inno_hdmi_phy_drv_data = { ++ .phy_type = INNO_HDMI_PHY_RK3228, ++ .plat_ops = &rk3228_hdmi_phy_plat_ops, ++ .phy_cfg_table = rk3228_phy_cfg, ++}; ++ + static const struct inno_hdmi_phy_data rk3328_inno_hdmi_phy_drv_data = { + .phy_type = INNO_HDMI_PHY_RK3328, + .plat_ops = &rk3328_hdmi_phy_plat_ops, +@@ -868,6 +1243,10 @@ static const struct inno_hdmi_phy_data rk3328_inno_hdmi_phy_drv_data = { + }; + + static const struct udevice_id inno_hdmi_phy_ids[] = { ++ { ++ .compatible = "rockchip,rk3228-hdmi-phy", ++ .data = (ulong)&rk3228_inno_hdmi_phy_drv_data, ++ }, + { + .compatible = "rockchip,rk3328-hdmi-phy", + .data = (ulong)&rk3328_inno_hdmi_phy_drv_data, +-- +2.34.1 + diff --git a/patch/u-boot/v2024.01/board_rk322x-box/rk3228-vop-driver.patch b/patch/u-boot/v2024.07/board_rk322x-box/rk3228-vop-driver.patch similarity index 89% rename from patch/u-boot/v2024.01/board_rk322x-box/rk3228-vop-driver.patch rename to patch/u-boot/v2024.07/board_rk322x-box/rk3228-vop-driver.patch index 0b50e33cd373..286a15b0cfa0 100644 --- a/patch/u-boot/v2024.01/board_rk322x-box/rk3228-vop-driver.patch +++ b/patch/u-boot/v2024.07/board_rk322x-box/rk3228-vop-driver.patch @@ -1,13 +1,26 @@ -From d62c24664878bd4ca198806580a7dc9aea41db1f Mon Sep 17 00:00:00 2001 +From 87c948b811c99b0a9004016099152a406b8db903 Mon Sep 17 00:00:00 2001 From: Paolo Sabatino -Date: Mon, 29 Apr 2024 16:18:05 +0200 -Subject: [PATCH 2/4] rockchip rk3228 VOP driver +Date: Sun, 30 Jun 2024 17:41:01 +0200 +Subject: [PATCH] rk3228 vop driver --- - drivers/video/rockchip/rk3228_vop.c | 109 ++++++++++++++++++++++++++++ - 1 file changed, 109 insertions(+) + drivers/video/rockchip/Makefile | 1 + + drivers/video/rockchip/rk3228_vop.c | 107 ++++++++++++++++++++++++++++ + 2 files changed, 108 insertions(+) create mode 100644 drivers/video/rockchip/rk3228_vop.c +diff --git a/drivers/video/rockchip/Makefile b/drivers/video/rockchip/Makefile +index ac55864a33..28ac47a81b 100644 +--- a/drivers/video/rockchip/Makefile ++++ b/drivers/video/rockchip/Makefile +@@ -5,6 +5,7 @@ + + ifdef CONFIG_VIDEO_ROCKCHIP + obj-y += rk_vop.o ++obj-$(CONFIG_ROCKCHIP_RK322X) += rk3228_vop.o + obj-$(CONFIG_ROCKCHIP_RK3288) += rk3288_vop.o + obj-$(CONFIG_ROCKCHIP_RK3328) += rk3328_vop.o + obj-$(CONFIG_ROCKCHIP_RK3399) += rk3399_vop.o diff --git a/drivers/video/rockchip/rk3228_vop.c b/drivers/video/rockchip/rk3228_vop.c new file mode 100644 index 0000000000..ec558078a0 @@ -121,19 +134,6 @@ index 0000000000..ec558078a0 + .priv_auto = sizeof(struct rk_vop_priv), + .flags = DM_FLAG_OS_PREPARE +}; - -diff --git a/drivers/video/rockchip/Makefile b/drivers/video/rockchip/Makefile -index 8128289cc8..0e4cc65fdf 100644 ---- a/drivers/video/rockchip/Makefile -+++ b/drivers/video/rockchip/Makefile -@@ -6,6 +6,7 @@ - ifdef CONFIG_VIDEO_ROCKCHIP - obj-y += rk_vop.o - obj-$(CONFIG_ROCKCHIP_RK3288) += rk3288_vop.o -+obj-$(CONFIG_ROCKCHIP_RK322X) += rk3228_vop.o - obj-$(CONFIG_ROCKCHIP_RK3399) += rk3399_vop.o - obj-$(CONFIG_DISPLAY_ROCKCHIP_EDP) += rk_edp.o - obj-$(CONFIG_DISPLAY_ROCKCHIP_LVDS) += rk_lvds.o -- 2.34.1 diff --git a/patch/u-boot/v2024.01/board_rk322x-box/rk322x-add-usb-reset-props.patch b/patch/u-boot/v2024.07/board_rk322x-box/rk322x-add-usb-reset-props.patch similarity index 100% rename from patch/u-boot/v2024.01/board_rk322x-box/rk322x-add-usb-reset-props.patch rename to patch/u-boot/v2024.07/board_rk322x-box/rk322x-add-usb-reset-props.patch diff --git a/patch/u-boot/v2024.01/board_rk322x-box/rk322x-box-add-defconfig.patch b/patch/u-boot/v2024.07/board_rk322x-box/rk322x-box-add-defconfig.patch similarity index 94% rename from patch/u-boot/v2024.01/board_rk322x-box/rk322x-box-add-defconfig.patch rename to patch/u-boot/v2024.07/board_rk322x-box/rk322x-box-add-defconfig.patch index eb26baa4487e..cfaa29cd77c7 100644 --- a/patch/u-boot/v2024.01/board_rk322x-box/rk322x-box-add-defconfig.patch +++ b/patch/u-boot/v2024.07/board_rk322x-box/rk322x-box-add-defconfig.patch @@ -1,9 +1,9 @@ diff --git a/configs/rk322x-box_defconfig b/configs/rk322x-box_defconfig new file mode 100644 -index 0000000000..767c7edb72 +index 0000000000..cd93614c51 --- /dev/null +++ b/configs/rk322x-box_defconfig -@@ -0,0 +1,125 @@ +@@ -0,0 +1,128 @@ +CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y +CONFIG_SPL_SKIP_LOWLEVEL_INIT=y @@ -26,6 +26,7 @@ index 0000000000..767c7edb72 +CONFIG_SPL_MMC=y +CONFIG_TARGET_RK322X_BOX=y +CONFIG_SPL_STACK_R_ADDR=0x60600000 ++CONFIG_SPL_STACK_R=y +CONFIG_DEBUG_UART_BASE=0x11030000 +CONFIG_DEBUG_UART_CLOCK=24000000 +CONFIG_SYS_LOAD_ADDR=0x61800800 @@ -35,11 +36,12 @@ index 0000000000..767c7edb72 +CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y +CONFIG_SPL_LOAD_FIT=y ++CONFIG_SYS_BOOTM_LEN=0x4000000 +CONFIG_SD_BOOT=y +CONFIG_BOOTDELAY=1 +CONFIG_USE_PREBOOT=y +CONFIG_DEFAULT_FDT_FILE="rk322x-box.dtb" -+CONFIG_LOGLEVEL=4 ++CONFIG_LOGLEVEL=6 +CONFIG_SILENT_CONSOLE=y +# CONFIG_SPL_SILENT_CONSOLE is not set +# CONFIG_TPL_SILENT_CONSOLE is not set @@ -51,9 +53,9 @@ index 0000000000..767c7edb72 +CONFIG_SPL_PAD_TO=0x7f8000 +CONFIG_SPL_NO_BSS_LIMIT=y +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set -+CONFIG_SPL_STACK_R=y +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x200 -+CONFIG_SYS_BOOTM_LEN=0x4000000 ++# CONFIG_BOOTM_EFI is not set ++# CONFIG_CMD_BOOTEFI is not set +CONFIG_CMD_GPIO=y +CONFIG_CMD_GPT=y +CONFIG_CMD_MMC=y @@ -62,7 +64,7 @@ index 0000000000..767c7edb72 +# CONFIG_CMD_CLS is not set +CONFIG_CMD_TIME=y +# CONFIG_SPL_DOS_PARTITION is not set -+# CONFIG_SPL_PARTITION_UUIDS is not set ++# CONFIG_SPL_EFI_PARTITION is not set +CONFIG_PARTITION_TYPE_GUID=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_TPL_OF_CONTROL=y @@ -127,5 +129,6 @@ index 0000000000..767c7edb72 +CONFIG_DISPLAY_ROCKCHIP_HDMI=y +CONFIG_FS_BTRFS=y +CONFIG_TPL_TINY_MEMSET=y ++CONFIG_SPL_CRC32=y +CONFIG_ERRNO_STR=y +CONFIG_BOOTM_OPTEE=y diff --git a/patch/u-boot/v2024.01/board_rk322x-box/rk322x-box-add-device-tree-makefile.patch b/patch/u-boot/v2024.07/board_rk322x-box/rk322x-box-add-device-tree-makefile.patch similarity index 100% rename from patch/u-boot/v2024.01/board_rk322x-box/rk322x-box-add-device-tree-makefile.patch rename to patch/u-boot/v2024.07/board_rk322x-box/rk322x-box-add-device-tree-makefile.patch diff --git a/patch/u-boot/v2024.01/board_rk322x-box/rk322x-box-add-device-tree.patch b/patch/u-boot/v2024.07/board_rk322x-box/rk322x-box-add-device-tree.patch similarity index 100% rename from patch/u-boot/v2024.01/board_rk322x-box/rk322x-box-add-device-tree.patch rename to patch/u-boot/v2024.07/board_rk322x-box/rk322x-box-add-device-tree.patch diff --git a/patch/u-boot/v2024.01/board_rk322x-box/u-boot-1002-support-rockchip-gmac-rmii.patch b/patch/u-boot/v2024.07/board_rk322x-box/u-boot-1002-support-rockchip-gmac-rmii.patch similarity index 100% rename from patch/u-boot/v2024.01/board_rk322x-box/u-boot-1002-support-rockchip-gmac-rmii.patch rename to patch/u-boot/v2024.07/board_rk322x-box/u-boot-1002-support-rockchip-gmac-rmii.patch diff --git a/patch/u-boot/v2024.01/board_rk322x-box/u-boot-1005-support-rockchip-tee-binary.patch b/patch/u-boot/v2024.07/board_rk322x-box/u-boot-1005-support-rockchip-tee-binary.patch similarity index 100% rename from patch/u-boot/v2024.01/board_rk322x-box/u-boot-1005-support-rockchip-tee-binary.patch rename to patch/u-boot/v2024.07/board_rk322x-box/u-boot-1005-support-rockchip-tee-binary.patch diff --git a/patch/u-boot/v2024.01/board_rk322x-box/u-boot-1006-usbphy-otg-ehci-support.patch b/patch/u-boot/v2024.07/board_rk322x-box/u-boot-1006-usbphy-otg-ehci-support.patch similarity index 77% rename from patch/u-boot/v2024.01/board_rk322x-box/u-boot-1006-usbphy-otg-ehci-support.patch rename to patch/u-boot/v2024.07/board_rk322x-box/u-boot-1006-usbphy-otg-ehci-support.patch index 61ae2deeadeb..6211a159c323 100644 --- a/patch/u-boot/v2024.01/board_rk322x-box/u-boot-1006-usbphy-otg-ehci-support.patch +++ b/patch/u-boot/v2024.07/board_rk322x-box/u-boot-1006-usbphy-otg-ehci-support.patch @@ -1,13 +1,13 @@ -From 62b9c5ea4a5d41f8adf122797958b202d566f735 Mon Sep 17 00:00:00 2001 +From cf6a1483e87f01165606c10d19c8faa8cd7ce69f Mon Sep 17 00:00:00 2001 From: Paolo Sabatino -Date: Thu, 25 Apr 2024 21:59:34 +0200 +Date: Sun, 30 Jun 2024 16:46:51 +0200 Subject: [PATCH] OTG/EHCI USB support for rk322x --- arch/arm/mach-rockchip/rk322x/syscon_rk322x.c | 3 + drivers/clk/rockchip/clk_rk322x.c | 121 ++++++++++++++++++ - drivers/phy/rockchip/phy-rockchip-inno-usb2.c | 49 +++++++ - 3 files changed, 173 insertions(+) + drivers/phy/rockchip/phy-rockchip-inno-usb2.c | 32 +++++ + 3 files changed, 156 insertions(+) diff --git a/arch/arm/mach-rockchip/rk322x/syscon_rk322x.c b/arch/arm/mach-rockchip/rk322x/syscon_rk322x.c index 0d9dca8173..37c040950b 100644 @@ -23,10 +23,10 @@ index 0d9dca8173..37c040950b 100644 .of_match = rk322x_syscon_ids, }; diff --git a/drivers/clk/rockchip/clk_rk322x.c b/drivers/clk/rockchip/clk_rk322x.c -index f6d2ca6134..44b5778589 100644 +index 4cd8a1b2e6..9bc07a570a 100644 --- a/drivers/clk/rockchip/clk_rk322x.c +++ b/drivers/clk/rockchip/clk_rk322x.c -@@ -474,10 +474,131 @@ static int rk322x_clk_set_parent(struct clk *clk, struct clk *parent) +@@ -596,10 +596,131 @@ static int rk322x_clk_set_parent(struct clk *clk, struct clk *parent) return -ENOENT; } @@ -159,10 +159,10 @@ index f6d2ca6134..44b5778589 100644 static int rk322x_clk_of_to_plat(struct udevice *dev) diff --git a/drivers/phy/rockchip/phy-rockchip-inno-usb2.c b/drivers/phy/rockchip/phy-rockchip-inno-usb2.c -index 70e61eccb7..c905ccb8f9 100644 +index 43f6e020a6..8b814dbf26 100644 --- a/drivers/phy/rockchip/phy-rockchip-inno-usb2.c +++ b/drivers/phy/rockchip/phy-rockchip-inno-usb2.c -@@ -375,6 +375,51 @@ static const struct rockchip_usb2phy_cfg rk3328_usb2phy_cfgs[] = { +@@ -361,6 +361,34 @@ static const struct rockchip_usb2phy_cfg rk3328_usb2phy_cfgs[] = { { /* sentinel */ } }; @@ -173,20 +173,9 @@ index 70e61eccb7..c905ccb8f9 100644 + .port_cfgs = { + [USB2PHY_PORT_OTG] = { + .phy_sus = { 0x0760, 15, 0, 0, 0x1d1 }, -+ .bvalid_det_en = { 0x0680, 3, 3, 0, 1 }, -+ .bvalid_det_st = { 0x0690, 3, 3, 0, 1 }, -+ .bvalid_det_clr = { 0x06a0, 3, 3, 0, 1 }, -+ .ls_det_en = { 0x0680, 2, 2, 0, 1 }, -+ .ls_det_st = { 0x0690, 2, 2, 0, 1 }, -+ .ls_det_clr = { 0x06a0, 2, 2, 0, 1 }, -+ .utmi_bvalid = { 0x0480, 4, 4, 0, 1 }, -+ .utmi_ls = { 0x0480, 3, 2, 0, 1 }, + }, + [USB2PHY_PORT_HOST] = { + .phy_sus = { 0x0764, 15, 0, 0, 0x1d1 }, -+ .ls_det_en = { 0x0680, 4, 4, 0, 1 }, -+ .ls_det_st = { 0x0690, 4, 4, 0, 1 }, -+ .ls_det_clr = { 0x06a0, 4, 4, 0, 1 } + } + }, + }, @@ -196,15 +185,9 @@ index 70e61eccb7..c905ccb8f9 100644 + .port_cfgs = { + [USB2PHY_PORT_OTG] = { + .phy_sus = { 0x800, 15, 0, 0, 0x1d1 }, -+ .ls_det_en = { 0x0684, 0, 0, 0, 1 }, -+ .ls_det_st = { 0x0694, 0, 0, 0, 1 }, -+ .ls_det_clr = { 0x06a4, 0, 0, 0, 1 } + }, + [USB2PHY_PORT_HOST] = { + .phy_sus = { 0x804, 15, 0, 0, 0x1d1 }, -+ .ls_det_en = { 0x0684, 1, 1, 0, 1 }, -+ .ls_det_st = { 0x0694, 1, 1, 0, 1 }, -+ .ls_det_clr = { 0x06a4, 1, 1, 0, 1 } + } + }, + }, @@ -214,7 +197,7 @@ index 70e61eccb7..c905ccb8f9 100644 static const struct rockchip_usb2phy_cfg rk3399_usb2phy_cfgs[] = { { .reg = 0xe450, -@@ -532,6 +577,10 @@ static const struct udevice_id rockchip_usb2phy_ids[] = { +@@ -466,6 +494,10 @@ static const struct udevice_id rockchip_usb2phy_ids[] = { .compatible = "rockchip,rk3328-usb2phy", .data = (ulong)&rk3328_usb2phy_cfgs, }, diff --git a/patch/u-boot/v2024.01/board_rk3318-box/general-support-rmii-integrated-phy.patch b/patch/u-boot/v2024.07/board_rk3318-box/general-support-rmii-integrated-phy.patch similarity index 100% rename from patch/u-boot/v2024.01/board_rk3318-box/general-support-rmii-integrated-phy.patch rename to patch/u-boot/v2024.07/board_rk3318-box/general-support-rmii-integrated-phy.patch diff --git a/patch/u-boot/v2024.01/board_rk3318-box/rk3318-box-add-defconfig.patch b/patch/u-boot/v2024.07/board_rk3318-box/rk3318-box-add-defconfig.patch similarity index 75% rename from patch/u-boot/v2024.01/board_rk3318-box/rk3318-box-add-defconfig.patch rename to patch/u-boot/v2024.07/board_rk3318-box/rk3318-box-add-defconfig.patch index 2c4a569d8ace..ce479426d82d 100644 --- a/patch/u-boot/v2024.01/board_rk3318-box/rk3318-box-add-defconfig.patch +++ b/patch/u-boot/v2024.07/board_rk3318-box/rk3318-box-add-defconfig.patch @@ -1,32 +1,23 @@ diff --git a/configs/rk3318-box_defconfig b/configs/rk3318-box_defconfig new file mode 100644 -index 0000000000..d356b21ac6 +index 0000000000..97bb10576e --- /dev/null +++ b/configs/rk3318-box_defconfig -@@ -0,0 +1,141 @@ +@@ -0,0 +1,131 @@ +CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y +CONFIG_COUNTER_FREQUENCY=24000000 +CONFIG_ARCH_ROCKCHIP=y -+CONFIG_TEXT_BASE=0x200000 +CONFIG_NR_DRAM_BANKS=1 -+CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y -+CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc00000 +CONFIG_SF_DEFAULT_SPEED=20000000 +CONFIG_ENV_OFFSET=0x3F8000 -+CONFIG_DEFAULT_DEVICE_TREE="rk3318-box" ++CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3318-box" +CONFIG_OF_LIBFDT_OVERLAY=y +CONFIG_DM_RESET=y +CONFIG_ROCKCHIP_RK3328=y -+CONFIG_TPL_ROCKCHIP_COMMON_BOARD=y -+CONFIG_TPL_LIBCOMMON_SUPPORT=y -+CONFIG_TPL_LIBGENERIC_SUPPORT=y ++CONFIG_ROCKCHIP_EXTERNAL_TPL=y +CONFIG_SPL_DRIVERS_MISC=y +CONFIG_TARGET_BOX_RK3318=y -+CONFIG_SPL_STACK_R_ADDR=0x4000000 -+CONFIG_SPL_STACK=0x400000 -+CONFIG_TPL_SYS_MALLOC_F_LEN=0x800 -+CONFIG_SPL_SYS_MALLOC_F_LEN=0x4000 +CONFIG_PRE_CON_BUF_ADDR=0xf200000 +CONFIG_DEBUG_UART_BASE=0xFF130000 +CONFIG_DEBUG_UART_CLOCK=24000000 @@ -36,7 +27,9 @@ index 0000000000..d356b21ac6 +# CONFIG_LOCALVERSION_AUTO is not set +CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y ++CONFIG_SPL_FIT_SIGNATURE=y +CONFIG_SPL_LOAD_FIT=y ++CONFIG_LEGACY_IMAGE_FORMAT=y +CONFIG_BOOTDELAY=1 +CONFIG_USE_PREBOOT=y +CONFIG_DEFAULT_FDT_FILE="rockchip/rk3318-box.dtb" @@ -44,26 +37,17 @@ index 0000000000..d356b21ac6 +CONFIG_SILENT_CONSOLE=y +# CONFIG_SPL_SILENT_CONSOLE is not set +# CONFIG_TPL_SILENT_CONSOLE is not set -+CONFIG_PRE_CONSOLE_BUFFER=y +# CONFIG_SYS_DEVICE_NULLDEV is not set +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_DISPLAY_BOARDINFO_LATE=y -+CONFIG_MISC_INIT_R=y ++CONFIG_LAST_STAGE_INIT=y +CONFIG_SPL_MAX_SIZE=0x40000 +CONFIG_SPL_PAD_TO=0x7f8000 -+CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -+CONFIG_SPL_BSS_START_ADDR=0x2000000 -+CONFIG_SPL_BSS_MAX_SIZE=0x2000 +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set -+# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set -+CONFIG_SPL_STACK_R=y -+CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000 +CONFIG_SPL_ATF=y +CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y -+CONFIG_TPL_SYS_MALLOC_SIMPLE=y +CONFIG_CMD_BOOTZ=y +CONFIG_CMD_GPIO=y -+CONFIG_CMD_GPIO_READ=y +CONFIG_CMD_GPT=y +CONFIG_CMD_MMC=y +CONFIG_CMD_USB=y @@ -72,13 +56,13 @@ index 0000000000..d356b21ac6 +CONFIG_CMD_BTRFS=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_TPL_OF_CONTROL=y -+CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" ++CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_TPL_OF_PLATDATA=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_SYS_MMC_ENV_DEV=1 -+CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_TPL_DM=y ++CONFIG_SPL_DM_SEQ_ALIAS=y +CONFIG_REGMAP=y +CONFIG_SPL_REGMAP=y +CONFIG_TPL_REGMAP=y @@ -92,12 +76,11 @@ index 0000000000..d356b21ac6 +CONFIG_SPL_CLK=y +CONFIG_ROCKCHIP_GPIO=y +CONFIG_SYS_I2C_ROCKCHIP=y -+CONFIG_MISC=y -+CONFIG_ROCKCHIP_EFUSE=y +CONFIG_MMC_DW=y +CONFIG_MMC_DW_ROCKCHIP=y +CONFIG_DM_MDIO=y +CONFIG_DM_ETH_PHY=y ++CONFIG_PHY_GIGE=y +CONFIG_ETH_DESIGNWARE=y +CONFIG_RGMII=y +CONFIG_MII=y @@ -118,13 +101,17 @@ index 0000000000..d356b21ac6 +CONFIG_RAM=y +CONFIG_SPL_RAM=y +CONFIG_TPL_RAM=y ++CONFIG_DM_RNG=y ++CONFIG_RNG_ROCKCHIP=y +CONFIG_BAUDRATE=1500000 +CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_DEBUG_UART_ANNOUNCE=y +CONFIG_SYS_NS16550_MEM32=y ++CONFIG_SYSINFO=y +CONFIG_SYSRESET=y +# CONFIG_TPL_SYSRESET is not set +CONFIG_USB=y ++CONFIG_DM_USB_GADGET=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y +CONFIG_USB_EHCI_HCD=y @@ -135,8 +122,10 @@ index 0000000000..d356b21ac6 +CONFIG_USB_DWC3=y +CONFIG_USB_DWC3_GENERIC=y +CONFIG_USB_KEYBOARD=y ++CONFIG_USB_KEYBOARD_FN_KEYS=y +CONFIG_VIDEO=y +# CONFIG_BACKLIGHT_PWM is not set ++CONFIG_VIDEO_ANSI=y +# CONFIG_PANEL is not set +CONFIG_DISPLAY=y +CONFIG_VIDEO_ROCKCHIP=y @@ -145,3 +134,4 @@ index 0000000000..d356b21ac6 +CONFIG_SPL_TINY_MEMSET=y +CONFIG_TPL_TINY_MEMSET=y +CONFIG_ERRNO_STR=y ++# CONFIG_EFI_LOADER is not set diff --git a/patch/u-boot/v2024.01/board_rk3318-box/rk3318-box-add-dts.patch b/patch/u-boot/v2024.07/board_rk3318-box/rk3318-box-add-dts.patch similarity index 92% rename from patch/u-boot/v2024.01/board_rk3318-box/rk3318-box-add-dts.patch rename to patch/u-boot/v2024.07/board_rk3318-box/rk3318-box-add-dts.patch index 069e2f0d5e36..94016d136070 100644 --- a/patch/u-boot/v2024.01/board_rk3318-box/rk3318-box-add-dts.patch +++ b/patch/u-boot/v2024.07/board_rk3318-box/rk3318-box-add-dts.patch @@ -1,20 +1,99 @@ +From 07a80d60680491abbf0db91071a66fe17ceeae4f Mon Sep 17 00:00:00 2001 +From: Paolo Sabatino +Date: Sun, 16 Jun 2024 16:00:41 +0200 +Subject: [PATCH] Add rk3318-box device tree + +--- + arch/arm/dts/Makefile | 3 + + arch/arm/dts/rk3318-box-u-boot.dtsi | 58 +++ + dts/upstream/src/arm64/rockchip/rk3318-box.dts | 648 ++++++++++++++++++++++++++++ + 3 files changed, 709 insertions(+) + create mode 100644 arch/arm/dts/rk3318-box-u-boot.dtsi + create mode 100644 arch/arm/dts/rk3318-box.dts + diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile -index cf4f4ae8..3475d564 100644 +index 8fb6a8a1f1..a08f1a82e4 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile -@@ -107,6 +107,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3308) += \ - rk3308-roc-cc.dtb +@@ -90,6 +90,9 @@ dtb-$(CONFIG_ROCKCHIP_RK3288) += \ + rk3288-veyron-speedy.dtb \ + rk3288-vyasa.dtb - dtb-$(CONFIG_ROCKCHIP_RK3328) += \ -+ rk3318-box.dtb \ - rk3328-evb.dtb \ - rk3328-nanopi-r2-rev00.dtb \ - rk3328-orangepi-r1-plus.dtb \ -diff --git a/arch/arm/dts/rk3318-box.dts b/arch/arm/dts/rk3318-box.dts ++dtb-$(CONFIG_ROCKCHIP_RK3328) += \ ++ rk3318-box.dtb ++ + dtb-$(CONFIG_ROCKCHIP_RK3368) += \ + rk3368-lion-haikou.dtb \ + rk3368-sheep.dtb \ +diff --git a/arch/arm/dts/rk3318-box-u-boot.dtsi b/arch/arm/dts/rk3318-box-u-boot.dtsi new file mode 100644 -index 00000000..d4678c7c +index 0000000000..ffe48d8932 --- /dev/null -+++ b/arch/arm/dts/rk3318-box.dts ++++ b/arch/arm/dts/rk3318-box-u-boot.dtsi +@@ -0,0 +1,58 @@ ++// SPDX-License-Identifier: GPL-2.0+ ++/* ++ * (C) Copyright 2020 Armbian project (jock) ++ */ ++ ++#include "rk3328-u-boot.dtsi" ++#include "rk3328-sdram-ddr3-666.dtsi" ++ ++/* ++ * Remove the OP-TEE binary node from the binman assembly to avoid ++ * the relative u-boot warning. rk3318-box has not op-tee binary. ++ * The absolute path of the offending binary is: ++ * /binman/simple-bin/fit/images/@tee-SEQ/tee-os ++ * ++ * see rockchip-u-boot.dtsi for the binman mayhem ++ * ++ */ ++&fit { ++ images { ++ /delete-node/ @tee-SEQ; ++ }; ++}; ++ ++/ { ++ chosen { ++ u-boot,spl-boot-order = "same-as-spl", &sdmmc, &sdmmc_ext, &emmc; ++ }; ++ ++}; ++ ++/* ++&usb_host0_xhci { ++ vbus-supply = <&vcc_host_vbus>; ++ status = "okay"; ++}; ++*/ ++ ++&sdio { ++ status="disabled"; ++}; ++ ++&pinctrl { ++ ++ sdmmc0-1 { ++ sdmmc0m1_pwren: sdmmc0m1-pwren { ++ rockchip,pins = <0 RK_PD6 3 &pcfg_pull_up_4ma>; ++ }; ++ ++ sdmmc0m1_pin: sdmmc0m1-pin { ++ rockchip,pins = <0 RK_PD6 RK_FUNC_GPIO &pcfg_pull_up_4ma>; ++ }; ++ }; ++ ++}; ++ ++&vdd_arm { ++ regulator-init-microvolt = <1200000>; ++}; +diff --git a/dts/upstream/src/arm64/rockchip/rk3318-box.dts b/dts/upstream/src/arm64/rockchip/rk3318-box.dts +new file mode 100644 +index 0000000000..ad98288ea9 +--- /dev/null ++++ b/dts/upstream/src/arm64/rockchip/rk3318-box.dts @@ -0,0 +1,648 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* @@ -504,12 +583,12 @@ index 00000000..d4678c7c + status = "okay"; + vcodec-supply = <&vdd_logic>; +}; -+*/ ++ + +&rkvdec_mmu { + status = "okay"; +}; -+ ++*/ +&threshold { + temperature = <80000>; /* millicelsius */ +}; @@ -664,67 +743,6 @@ index 00000000..d4678c7c +&analog_sound { + status = "okay"; +}; -diff --git a/arch/arm/dts/rk3318-box-u-boot.dtsi b/arch/arm/dts/rk3318-box-u-boot.dtsi -new file mode 100644 -index 0000000000..ffe48d8932 ---- /dev/null -+++ b/arch/arm/dts/rk3318-box-u-boot.dtsi -@@ -0,0 +1,58 @@ -+// SPDX-License-Identifier: GPL-2.0+ -+/* -+ * (C) Copyright 2020 Armbian project (jock) -+ */ -+ -+#include "rk3328-u-boot.dtsi" -+#include "rk3328-sdram-ddr3-666.dtsi" -+ -+/* -+ * Remove the OP-TEE binary node from the binman assembly to avoid -+ * the relative u-boot warning. rk3318-box has not op-tee binary. -+ * The absolute path of the offending binary is: -+ * /binman/simple-bin/fit/images/@tee-SEQ/tee-os -+ * -+ * see rockchip-u-boot.dtsi for the binman mayhem -+ * -+ */ -+&fit { -+ images { -+ /delete-node/ @tee-SEQ; -+ }; -+}; -+ -+/ { -+ chosen { -+ u-boot,spl-boot-order = "same-as-spl", &sdmmc, &sdmmc_ext, &emmc; -+ }; -+ -+}; -+ -+/* -+&usb_host0_xhci { -+ vbus-supply = <&vcc_host_vbus>; -+ status = "okay"; -+}; -+*/ -+ -+&sdio { -+ status="disabled"; -+}; -+ -+&pinctrl { -+ -+ sdmmc0-1 { -+ sdmmc0m1_pwren: sdmmc0m1-pwren { -+ rockchip,pins = <0 RK_PD6 3 &pcfg_pull_up_4ma>; -+ }; -+ -+ sdmmc0m1_pin: sdmmc0m1-pin { -+ rockchip,pins = <0 RK_PD6 RK_FUNC_GPIO &pcfg_pull_up_4ma>; -+ }; -+ }; -+ -+}; -+ -+&vdd_arm { -+ regulator-init-microvolt = <1200000>; -+}; +-- +2.34.1 + diff --git a/patch/u-boot/v2024.01/board_rk3318-box/rk3318-box-add-makefile.patch b/patch/u-boot/v2024.07/board_rk3318-box/rk3318-box-add-makefile.patch similarity index 100% rename from patch/u-boot/v2024.01/board_rk3318-box/rk3318-box-add-makefile.patch rename to patch/u-boot/v2024.07/board_rk3318-box/rk3318-box-add-makefile.patch diff --git a/patch/u-boot/v2024.07/board_rk3318-box/rk3328-add-usb-reset-props.patch b/patch/u-boot/v2024.07/board_rk3318-box/rk3328-add-usb-reset-props.patch new file mode 100644 index 000000000000..8029dc487a90 --- /dev/null +++ b/patch/u-boot/v2024.07/board_rk3318-box/rk3328-add-usb-reset-props.patch @@ -0,0 +1,74 @@ +diff --git a/dts/upstream/src/arm64/rockchip/rk3328.dtsi b/dts/upstream/src/arm64/rockchip/rk3328.dtsi +index 7b4c15c4a9..a7830155dd 100644 +--- a/dts/upstream/src/arm64/rockchip/rk3328.dtsi ++++ b/dts/upstream/src/arm64/rockchip/rk3328.dtsi +@@ -977,6 +998,8 @@ + g-tx-fifo-size = <256 128 128 64 32 16>; + phys = <&u2phy_otg>; + phy-names = "usb2-phy"; ++ resets = <&cru SRST_USB2OTG>; ++ reset-names = "otg"; + status = "disabled"; + }; + +@@ -987,6 +1010,8 @@ + clocks = <&cru HCLK_HOST0>, <&u2phy>; + phys = <&u2phy_host>; + phy-names = "usb"; ++ resets = <&cru SRST_USB2HOST_EHCIPHY>; ++ reset-names = "ehci"; + status = "disabled"; + }; + +@@ -997,6 +1022,8 @@ + clocks = <&cru HCLK_HOST0>, <&u2phy>; + phys = <&u2phy_host>; + phy-names = "usb"; ++ resets = <&cru SRST_USB2HOST_EHCIPHY>; ++ reset-names = "ehci"; + status = "disabled"; + }; + +@@ -1010,6 +1037,8 @@ + "bus_clk"; + dr_mode = "otg"; + phy_type = "utmi_wide"; ++ resets = <&cru SRST_USB3OTG>; ++ reset-names = "otg"; + snps,dis-del-phy-power-chg-quirk; + snps,dis_enblslpm_quirk; + snps,dis-tx-ipgap-linecheck-quirk; + +diff --git a/drivers/usb/host/dwc2.c b/drivers/usb/host/dwc2.c +index 936e30438d..09d3805e78 100644 +--- a/drivers/usb/host/dwc2.c ++++ b/drivers/usb/host/dwc2.c +@@ -1436,7 +1438,10 @@ static int dwc2_usb_remove(struct udevice *dev) + + dwc2_uninit_common(priv->regs); + +- reset_release_bulk(&priv->resets); ++ // Assert first and then leave the resets deasserted ++ reset_assert_bulk(&priv->resets); ++ reset_deassert_bulk(&priv->resets); ++ + clk_disable_bulk(&priv->clks); + clk_release_bulk(&priv->clks); + +diff --git a/drivers/usb/host/ehci-generic.c b/drivers/usb/host/ehci-generic.c +index 936e30438d..09d3805e78 100644 +--- a/drivers/usb/host/ehci-generic.c ++++ b/drivers/usb/host/ehci-generic.c +@@ -148,9 +148,9 @@ static int ehci_usb_remove(struct udevice *dev) + if (ret) + return ret; + +- ret = reset_release_bulk(&priv->resets); +- if (ret) +- return ret; ++ // Assert first and then leave the resets deasserted ++ reset_assert_bulk(&priv->resets); ++ reset_deassert_bulk(&priv->resets); + + return clk_release_bulk(&priv->clocks); + } diff --git a/patch/u-boot/v2024.01/board_rk3318-box/rk3328-resets-for-mmc-controllers.patch b/patch/u-boot/v2024.07/board_rk3318-box/rk3328-resets-for-mmc-controllers.patch similarity index 82% rename from patch/u-boot/v2024.01/board_rk3318-box/rk3328-resets-for-mmc-controllers.patch rename to patch/u-boot/v2024.07/board_rk3318-box/rk3328-resets-for-mmc-controllers.patch index c8530a9bef72..23628c5661e0 100644 --- a/patch/u-boot/v2024.01/board_rk3318-box/rk3328-resets-for-mmc-controllers.patch +++ b/patch/u-boot/v2024.07/board_rk3318-box/rk3328-resets-for-mmc-controllers.patch @@ -4,13 +4,13 @@ Date: Fri, 5 Nov 2021 16:03:11 +0000 Subject: [PATCH 1/2] rk3328: resets for mmc controllers --- - arch/arm/dts/rk3328.dtsi | 7 +++++++ + dts/upstream/src/arm64/rockchip/rk3328.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) -diff --git a/arch/arm/dts/rk3328.dtsi b/arch/arm/dts/rk3328.dtsi +diff --git a/dts/upstream/src/arm64/rockchip/rk3328.dtsi b/dts/upstream/src/arm64/rockchip/rk3328.dtsi index 945387e5..3314d5e4 100644 ---- a/arch/arm/dts/rk3328.dtsi -+++ b/arch/arm/dts/rk3328.dtsi +--- a/dts/upstream/src/arm64/rockchip/rk3328.dtsi ++++ b/dts/upstream/src/arm64/rockchip/rk3328.dtsi @@ -859,6 +859,8 @@ clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>, <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; diff --git a/patch/u-boot/v2024.01/board_rk3318-box/rk3328-sdmmc_ext-node.patch b/patch/u-boot/v2024.07/board_rk3318-box/rk3328-sdmmc_ext-node.patch similarity index 75% rename from patch/u-boot/v2024.01/board_rk3318-box/rk3328-sdmmc_ext-node.patch rename to patch/u-boot/v2024.07/board_rk3318-box/rk3328-sdmmc_ext-node.patch index f8d2228ffca4..040d4dcfa2dd 100644 --- a/patch/u-boot/v2024.01/board_rk3318-box/rk3328-sdmmc_ext-node.patch +++ b/patch/u-boot/v2024.07/board_rk3318-box/rk3328-sdmmc_ext-node.patch @@ -4,18 +4,18 @@ Date: Fri, 5 Nov 2021 16:03:53 +0000 Subject: [PATCH 2/2] rk3328: sdmmc_ext node --- - arch/arm/dts/rk3328.dtsi | 14 ++++++++++++++ + /dts/upstream/src/arm64/rockchip/rk3328.dtsi | 14 ++++++++++++++ 1 file changed, 14 insertions(+) -diff --git a/arch/arm/dts/rk3328.dtsi b/arch/arm/dts/rk3328.dtsi +diff --git a//dts/upstream/src/arm64/rockchip/rk3328.dtsi b//dts/upstream/src/arm64/rockchip/rk3328.dtsi index 3314d5e4..a1fedc56 100644 ---- a/arch/arm/dts/rk3328.dtsi -+++ b/arch/arm/dts/rk3328.dtsi +--- a//dts/upstream/src/arm64/rockchip/rk3328.dtsi ++++ b//dts/upstream/src/arm64/rockchip/rk3328.dtsi @@ -895,6 +895,20 @@ status = "disabled"; }; -+ sdmmc_ext: dwmmc@ff5f0000 { ++ sdmmc_ext: mmc@ff5f0000 { + compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc"; + reg = <0x0 0xff5f0000 0x0 0x4000>; + interrupts = ; diff --git a/patch/u-boot/v2024.07/general-dw-hdmi-disable.patch b/patch/u-boot/v2024.07/general-dw-hdmi-disable.patch new file mode 100644 index 000000000000..6427e2a23439 --- /dev/null +++ b/patch/u-boot/v2024.07/general-dw-hdmi-disable.patch @@ -0,0 +1,53 @@ +From 3ba46ffdad0cc96c5ffb0e5b3474800db954456e Mon Sep 17 00:00:00 2001 +From: Paolo Sabatino +Date: Sun, 30 Jun 2024 17:36:02 +0200 +Subject: [PATCH] add dw_hdmi_disable() function to DW-HDMI driver + +--- + drivers/video/dw_hdmi.c | 17 +++++++++++++++++ + include/dw_hdmi.h | 1 + + 2 files changed, 18 insertions(+) + +diff --git a/drivers/video/dw_hdmi.c b/drivers/video/dw_hdmi.c +index c217af9787..66dde8cc1b 100644 +--- a/drivers/video/dw_hdmi.c ++++ b/drivers/video/dw_hdmi.c +@@ -1025,6 +1025,23 @@ int dw_hdmi_enable(struct dw_hdmi *hdmi, const struct display_timing *edid) + return 0; + } + ++int dw_hdmi_disable(struct dw_hdmi *hdmi) ++{ ++ uint clkdis; ++ ++ /* disable pixel clock and tmds data path */ ++ clkdis = 0x7f; ++ hdmi_write(hdmi, clkdis, HDMI_MC_CLKDIS); ++ ++ /* disable phy */ ++ hdmi_phy_sel_interface_control(hdmi, 0); ++ hdmi_phy_enable_tmds(hdmi, 0); ++ hdmi_phy_enable_power(hdmi, 0); ++ ++ return 0; ++ ++} ++ + static const struct dw_hdmi_phy_ops dw_hdmi_synopsys_phy_ops = { + .phy_set = dw_hdmi_phy_cfg, + }; +diff --git a/include/dw_hdmi.h b/include/dw_hdmi.h +index f4d66edace..5fe97e5a07 100644 +--- a/include/dw_hdmi.h ++++ b/include/dw_hdmi.h +@@ -562,6 +562,7 @@ int dw_hdmi_phy_wait_for_hpd(struct dw_hdmi *hdmi); + void dw_hdmi_phy_init(struct dw_hdmi *hdmi); + + int dw_hdmi_enable(struct dw_hdmi *hdmi, const struct display_timing *edid); ++int dw_hdmi_disable(struct dw_hdmi *hdmi); + int dw_hdmi_read_edid(struct dw_hdmi *hdmi, u8 *buf, int buf_size); + void dw_hdmi_init(struct dw_hdmi *hdmi); + int dw_hdmi_detect_hpd(struct dw_hdmi *hdmi); +-- +2.34.1 + diff --git a/patch/u-boot/v2024.01/general-dwc-otg-usb-fix.patch b/patch/u-boot/v2024.07/general-dwc-otg-usb-fix.patch similarity index 100% rename from patch/u-boot/v2024.01/general-dwc-otg-usb-fix.patch rename to patch/u-boot/v2024.07/general-dwc-otg-usb-fix.patch diff --git a/patch/u-boot/v2024.07/general-fix-inno-phy-macro.patch b/patch/u-boot/v2024.07/general-fix-inno-phy-macro.patch new file mode 100644 index 000000000000..d27760177292 --- /dev/null +++ b/patch/u-boot/v2024.07/general-fix-inno-phy-macro.patch @@ -0,0 +1,45 @@ +From 729ceebfef3f3d2c6a7a4811c89ccd404d6e0a58 Mon Sep 17 00:00:00 2001 +From: Paolo Sabatino +Date: Sun, 16 Jun 2024 18:07:03 +0200 +Subject: [PATCH] fix inno_poll macro + +--- + drivers/phy/rockchip/phy-rockchip-inno-hdmi.c | 8 ++++---- + 1 file changed, 4 insertions(+), 4 deletions(-) + +diff --git a/drivers/phy/rockchip/phy-rockchip-inno-hdmi.c b/drivers/phy/rockchip/phy-rockchip-inno-hdmi.c +index 3bb1a254ff..604e2703da 100644 +--- a/drivers/phy/rockchip/phy-rockchip-inno-hdmi.c ++++ b/drivers/phy/rockchip/phy-rockchip-inno-hdmi.c +@@ -432,8 +432,8 @@ static inline void inno_update_bits(struct inno_hdmi_phy *inno, u8 reg, + inno_write(inno, reg, tmp); + } + +-#define inno_poll(reg, val, cond, sleep_us, timeout_us) \ +- readl_poll_sleep_timeout((reg) * 4, val, cond, sleep_us, timeout_us) ++#define inno_poll(inno, reg, val, cond, sleep_us, timeout_us) \ ++ readl_poll_sleep_timeout(inno->regs + (reg * 4), val, cond, sleep_us, timeout_us) + + static unsigned long inno_hdmi_phy_get_tmdsclk(struct inno_hdmi_phy *inno, + unsigned long rate) +@@ -575,7 +575,7 @@ inno_hdmi_phy_rk3328_clk_set_rate(struct phy *phy, + inno_update_bits(inno, 0xa0, RK3328_PRE_PLL_POWER_DOWN, 0); + + /* Wait for Pre-PLL lock */ +- ret = inno_poll(0xa9, val, val & RK3328_PRE_PLL_LOCK_STATUS, ++ ret = inno_poll(inno, 0xa9, val, val & RK3328_PRE_PLL_LOCK_STATUS, + 1000, 10000); + if (ret) { + dev_err(phy->dev, "Pre-PLL locking failed\n"); +@@ -674,7 +674,7 @@ inno_hdmi_phy_rk3328_power_on(struct phy *phy, + RK3328_TMDS_DRIVER_ENABLE); + + /* Wait for post PLL lock */ +- ret = inno_poll(0xaf, v, v & RK3328_POST_PLL_LOCK_STATUS, ++ ret = inno_poll(inno, 0xaf, v, v & RK3328_POST_PLL_LOCK_STATUS, + 1000, 10000); + if (ret) { + dev_err(phy->dev, "Post-PLL locking failed\n"); +-- +2.34.1 +