From c647f409b206ccf7404b0dbde24f702c230d4b36 Mon Sep 17 00:00:00 2001 From: Muhammed Efe Cetin Date: Sat, 30 Nov 2024 02:45:25 +0300 Subject: [PATCH 001/120] nanopi-r6s: fix mmc0/mmc1 ordering --- ...0001-adjust-wrong-mmc0-mmc1-ordering.patch | 28 +++++++++++++++++++ 1 file changed, 28 insertions(+) create mode 100644 patch/u-boot/v2024.10/board_nanopi-r6s/0001-adjust-wrong-mmc0-mmc1-ordering.patch diff --git a/patch/u-boot/v2024.10/board_nanopi-r6s/0001-adjust-wrong-mmc0-mmc1-ordering.patch b/patch/u-boot/v2024.10/board_nanopi-r6s/0001-adjust-wrong-mmc0-mmc1-ordering.patch new file mode 100644 index 000000000000..6b9e674c3c16 --- /dev/null +++ b/patch/u-boot/v2024.10/board_nanopi-r6s/0001-adjust-wrong-mmc0-mmc1-ordering.patch @@ -0,0 +1,28 @@ +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Muhammed Efe Cetin +Date: Sat, 30 Nov 2024 02:09:36 +0300 +Subject: adjust wrong mmc0/mmc1 ordering + +--- + arch/arm/dts/rk3588s-nanopi-r6s-u-boot.dtsi | 7 +++++++ + 1 file changed, 7 insertions(+) + +diff --git a/arch/arm/dts/rk3588s-nanopi-r6s-u-boot.dtsi b/arch/arm/dts/rk3588s-nanopi-r6s-u-boot.dtsi +index 111111111111..222222222222 100644 +--- a/arch/arm/dts/rk3588s-nanopi-r6s-u-boot.dtsi ++++ b/arch/arm/dts/rk3588s-nanopi-r6s-u-boot.dtsi +@@ -1,3 +1,10 @@ + // SPDX-License-Identifier: (GPL-2.0+ OR MIT) + + #include "rk3588s-u-boot.dtsi" ++ ++/ { ++ aliases { ++ mmc0 = &sdhci; ++ mmc1 = &sdmmc; ++ }; ++}; +\ No newline at end of file +-- +Armbian + From c90a0f7890bddc8e755847fc8227e15828950251 Mon Sep 17 00:00:00 2001 From: Paolo Sabatino Date: Fri, 29 Nov 2024 22:06:06 +0100 Subject: [PATCH 002/120] rockchip: bump edge kernel to 6.12 --- config/kernel/linux-rockchip-edge.config | 126 +- config/sources/families/rockchip.conf | 2 +- .../linux-1003-temp-dw_hdmi-rockchip.patch | 63 - .../0000.patching_config.yaml | 6 +- .../armbian.series | 0 .../dt/rk322x-box.dts | 0 .../dt/rk3288-xt-q8l-v10.dts | 0 .../kernel-6.8-tools-cgroup-makefile.patch | 0 .../libreelec.series | 1 - .../overlay/Makefile | 0 .../overlay/README.rk322x-overlays | 0 .../overlay/README.rockchip-overlays | 0 .../overlay/rk322x-bt-8723cs.dtso | 0 .../overlay/rk322x-cpu-hs-lv.dtso | 0 .../overlay/rk322x-cpu-hs.dtso | 0 .../overlay/rk322x-cpu-stability.dtso | 0 .../overlay/rk322x-ddr3-330.dtso | 0 .../overlay/rk322x-ddr3-528.dtso | 0 .../overlay/rk322x-ddr3-660.dtso | 0 .../overlay/rk322x-ddr3-800.dtso | 0 .../overlay/rk322x-emmc-ddr-ph180.dtso | 0 .../overlay/rk322x-emmc-ddr-ph45.dtso | 0 .../overlay/rk322x-emmc-hs200.dtso | 0 .../overlay/rk322x-emmc-pins.dtso | 0 .../overlay/rk322x-emmc.dtso | 0 .../overlay/rk322x-fixup.scr-cmd | 0 .../overlay/rk322x-ir-wakeup.dtso | 0 .../overlay/rk322x-led-conf-default.dtso | 0 .../overlay/rk322x-led-conf1.dtso | 0 .../overlay/rk322x-led-conf2.dtso | 0 .../overlay/rk322x-led-conf3.dtso | 0 .../overlay/rk322x-led-conf4.dtso | 0 .../overlay/rk322x-led-conf5.dtso | 0 .../overlay/rk322x-led-conf6.dtso | 0 .../overlay/rk322x-led-conf7.dtso | 0 .../overlay/rk322x-led-conf8.dtso | 0 .../overlay/rk322x-nand.dtso | 0 .../overlay/rk322x-usb-otg-peripheral.dtso | 0 .../overlay/rk322x-wlan-alt-wiring.dtso | 0 .../overlay/rockchip-ds1307.dtbo | Bin .../overlay/rockchip-ds1307.dtso | 0 .../overlay/rockchip-fixup.scr-cmd | 0 .../overlay/rockchip-i2c1.dtbo | Bin .../overlay/rockchip-i2c1.dtso | 0 .../overlay/rockchip-i2c4.dtbo | Bin .../overlay/rockchip-i2c4.dtso | 0 .../overlay/rockchip-pwm1.dtso | 0 .../overlay/rockchip-pwm2.dtso | 0 .../overlay/rockchip-pwm3.dtso | 0 .../overlay/rockchip-spi0.dtbo | Bin .../overlay/rockchip-spi0.dtso | 0 .../overlay/rockchip-spi2.dtbo | Bin .../overlay/rockchip-spi2.dtso | 0 .../overlay/rockchip-spidev0.dtbo | Bin .../overlay/rockchip-spidev0.dtso | 0 .../overlay/rockchip-spidev2.dtbo | Bin .../overlay/rockchip-spidev2.dtso | 0 .../overlay/rockchip-uart1.dtbo | Bin .../overlay/rockchip-uart1.dtso | 0 .../overlay/rockchip-uart2.dtbo | Bin .../overlay/rockchip-uart2.dtso | 0 .../overlay/rockchip-uart3.dtbo | Bin .../overlay/rockchip-uart3.dtso | 0 .../overlay/rockchip-uart4.dtbo | Bin .../overlay/rockchip-uart4.dtso | 0 .../overlay/rockchip-w1-gpio.dtbo | Bin .../overlay/rockchip-w1-gpio.dtso | 0 .../bt-broadcom-serdev-workaround.patch | 0 .../clk-rk322x-composite-mmc-clk.patch | 0 .../clk-rockchip-max-frac-divider.patch | 0 .../driver-rk322x-audio-codec.patch | 0 .../driver-rk3288-gpiomem.patch | 0 .../driver-tinkerboard-alc4040-codec.patch | 0 .../drm-rk322x-plane-overlay.patch | 0 .../drm-rk322x-yuv-10bit-modes.patch | 0 .../drm-rockchip-hardware-cursor.patch | 12 +- .../patches.armbian/dts-miqi-fan.patch | 0 .../patches.armbian/dts-miqi-hevc-rga.patch | 0 .../patches.armbian/dts-miqi-mali-gpu.patch | 0 .../dts-miqi-regulator-fix.patch | 0 .../patches.armbian/dts-rk322x-iep-node.patch | 0 .../dts-rk322x-pinctrl-nand.patch | 0 .../dts-rk3288-disable-serial-dma.patch | 0 .../dts-rk3288-fix-mmc-aliases.patch | 0 .../dts-rk3288-gpu-500mhz-opp.patch | 0 .../dts-rk3288-pinctrl-spi2.patch | 0 .../dts-rk3288-thermal-rearrange-zones.patch | 0 .../dts-tinkerboard-bt-rtl8723bs.patch | 0 .../dts-tinkerboard-bt-uart-pins.patch | 0 .../dts-tinkerboard-hevc-rga.patch | 0 .../dts-tinkerboard-sdio-wifi.patch | 0 .../dts-tinkerboard-sdmmc-properties.patch | 0 .../dts-tinkerboard-spi-interface.patch | 0 .../dts-veyron-flag-cache-flush.patch | 0 ...eral-add-overlay-compilation-support.patch | 54 +- .../general-add-overlay-configfs.patch | 0 ...eral-add-restart-handler-for-act8846.patch | 0 .../general-dwc2-fix-wait-peripheral.patch | 0 .../general-dwc2-fix-wait-time.patch | 0 .../general-dwc2-nak-gadget.patch | 0 .../general-fix-reboot-from-kwiboo.patch | 0 ...eral-linux-export-mm-trace-rss-stats.patch | 0 .../general-rk322x-gpio-ir-driver.patch | 0 .../general-rockchip-various-fixes.patch | 0 .../ir-keymap-rk322x-box.patch | 0 .../ir-keymap-xt-q8l-v10.patch | 0 .../misc-tinkerboard-spi-interface.patch | 0 .../mmc-tinkerboard-sdmmc-reboot-fix.patch | 0 .../rk322x-dmc-driver-01-sipv2-calls.patch | 0 .../rk322x-dmc-driver-02-sip-constants.patch | 0 .../rk322x-dmc-driver-03-dfi-driver.patch | 0 .../rk322x-dmc-driver-04-driver.patch | 0 .../rk322x-dwc2-no-clock-gating.patch | 0 .../rk322x-usb-reset-props.patch | 0 .../wifi-ath9k-no-bulk-EP3-EP4.patch | 0 .../wifi-brcmfmac-add-bcm43342.patch | 0 .../wifi-brcmfmac-ap6330-firmware.patch | 0 .../patches.armbian/wifi-driver-esp8089.patch | 5 +- .../patches.armbian/wifi-driver-ssv6051.patch | 7 +- .../linux-0002-rockchip-from-list.patch | 44 + .../linux-0011-v4l2-from-list.patch | 659 ++++ .../linux-1000-drm-rockchip.patch | 2639 ++++++++++++++ .../linux-1001-v4l2-rockchip.patch | 506 +++ .../linux-1002-for-libreelec.patch | 688 ++++ .../linux-2000-v4l2-wip-rkvdec-hevc.patch | 3226 +++++++++++++++++ .../linux-2001-v4l2-wip-iep-driver.patch | 1803 +++++++++ .../series.conf | 1 - 127 files changed, 9701 insertions(+), 141 deletions(-) delete mode 100644 patch/kernel/archive/rockchip-6.11/patches.libreelec/linux-1003-temp-dw_hdmi-rockchip.patch rename patch/kernel/archive/{rockchip-6.11 => rockchip-6.12}/0000.patching_config.yaml (95%) rename patch/kernel/archive/{rockchip-6.11 => rockchip-6.12}/armbian.series (100%) rename patch/kernel/archive/{rockchip-6.11 => rockchip-6.12}/dt/rk322x-box.dts (100%) rename patch/kernel/archive/{rockchip-6.11 => rockchip-6.12}/dt/rk3288-xt-q8l-v10.dts (100%) rename patch/kernel/archive/{rockchip-6.11 => rockchip-6.12}/kernel-6.8-tools-cgroup-makefile.patch (100%) rename patch/kernel/archive/{rockchip-6.11 => rockchip-6.12}/libreelec.series (87%) rename patch/kernel/archive/{rockchip-6.11 => rockchip-6.12}/overlay/Makefile (100%) rename patch/kernel/archive/{rockchip-6.11 => rockchip-6.12}/overlay/README.rk322x-overlays (100%) rename patch/kernel/archive/{rockchip-6.11 => rockchip-6.12}/overlay/README.rockchip-overlays (100%) rename patch/kernel/archive/{rockchip-6.11 => rockchip-6.12}/overlay/rk322x-bt-8723cs.dtso (100%) rename patch/kernel/archive/{rockchip-6.11 => rockchip-6.12}/overlay/rk322x-cpu-hs-lv.dtso (100%) rename patch/kernel/archive/{rockchip-6.11 => rockchip-6.12}/overlay/rk322x-cpu-hs.dtso (100%) rename patch/kernel/archive/{rockchip-6.11 => rockchip-6.12}/overlay/rk322x-cpu-stability.dtso (100%) rename patch/kernel/archive/{rockchip-6.11 => rockchip-6.12}/overlay/rk322x-ddr3-330.dtso (100%) rename patch/kernel/archive/{rockchip-6.11 => rockchip-6.12}/overlay/rk322x-ddr3-528.dtso (100%) rename patch/kernel/archive/{rockchip-6.11 => rockchip-6.12}/overlay/rk322x-ddr3-660.dtso (100%) rename patch/kernel/archive/{rockchip-6.11 => rockchip-6.12}/overlay/rk322x-ddr3-800.dtso (100%) rename patch/kernel/archive/{rockchip-6.11 => rockchip-6.12}/overlay/rk322x-emmc-ddr-ph180.dtso (100%) rename patch/kernel/archive/{rockchip-6.11 => rockchip-6.12}/overlay/rk322x-emmc-ddr-ph45.dtso (100%) rename patch/kernel/archive/{rockchip-6.11 => rockchip-6.12}/overlay/rk322x-emmc-hs200.dtso (100%) rename patch/kernel/archive/{rockchip-6.11 => rockchip-6.12}/overlay/rk322x-emmc-pins.dtso (100%) rename patch/kernel/archive/{rockchip-6.11 => rockchip-6.12}/overlay/rk322x-emmc.dtso (100%) rename patch/kernel/archive/{rockchip-6.11 => rockchip-6.12}/overlay/rk322x-fixup.scr-cmd (100%) rename patch/kernel/archive/{rockchip-6.11 => rockchip-6.12}/overlay/rk322x-ir-wakeup.dtso (100%) rename patch/kernel/archive/{rockchip-6.11 => rockchip-6.12}/overlay/rk322x-led-conf-default.dtso (100%) rename patch/kernel/archive/{rockchip-6.11 => rockchip-6.12}/overlay/rk322x-led-conf1.dtso (100%) rename patch/kernel/archive/{rockchip-6.11 => rockchip-6.12}/overlay/rk322x-led-conf2.dtso (100%) rename patch/kernel/archive/{rockchip-6.11 => rockchip-6.12}/overlay/rk322x-led-conf3.dtso (100%) rename patch/kernel/archive/{rockchip-6.11 => rockchip-6.12}/overlay/rk322x-led-conf4.dtso (100%) rename patch/kernel/archive/{rockchip-6.11 => rockchip-6.12}/overlay/rk322x-led-conf5.dtso (100%) rename patch/kernel/archive/{rockchip-6.11 => rockchip-6.12}/overlay/rk322x-led-conf6.dtso (100%) rename patch/kernel/archive/{rockchip-6.11 => rockchip-6.12}/overlay/rk322x-led-conf7.dtso (100%) rename patch/kernel/archive/{rockchip-6.11 => rockchip-6.12}/overlay/rk322x-led-conf8.dtso (100%) rename patch/kernel/archive/{rockchip-6.11 => rockchip-6.12}/overlay/rk322x-nand.dtso (100%) rename patch/kernel/archive/{rockchip-6.11 => rockchip-6.12}/overlay/rk322x-usb-otg-peripheral.dtso (100%) rename patch/kernel/archive/{rockchip-6.11 => rockchip-6.12}/overlay/rk322x-wlan-alt-wiring.dtso (100%) rename patch/kernel/archive/{rockchip-6.11 => rockchip-6.12}/overlay/rockchip-ds1307.dtbo (100%) rename patch/kernel/archive/{rockchip-6.11 => rockchip-6.12}/overlay/rockchip-ds1307.dtso (100%) rename patch/kernel/archive/{rockchip-6.11 => rockchip-6.12}/overlay/rockchip-fixup.scr-cmd (100%) rename patch/kernel/archive/{rockchip-6.11 => rockchip-6.12}/overlay/rockchip-i2c1.dtbo (100%) rename patch/kernel/archive/{rockchip-6.11 => rockchip-6.12}/overlay/rockchip-i2c1.dtso (100%) rename patch/kernel/archive/{rockchip-6.11 => rockchip-6.12}/overlay/rockchip-i2c4.dtbo (100%) rename patch/kernel/archive/{rockchip-6.11 => rockchip-6.12}/overlay/rockchip-i2c4.dtso (100%) rename patch/kernel/archive/{rockchip-6.11 => rockchip-6.12}/overlay/rockchip-pwm1.dtso (100%) rename patch/kernel/archive/{rockchip-6.11 => rockchip-6.12}/overlay/rockchip-pwm2.dtso (100%) rename patch/kernel/archive/{rockchip-6.11 => rockchip-6.12}/overlay/rockchip-pwm3.dtso (100%) rename patch/kernel/archive/{rockchip-6.11 => rockchip-6.12}/overlay/rockchip-spi0.dtbo (100%) rename patch/kernel/archive/{rockchip-6.11 => rockchip-6.12}/overlay/rockchip-spi0.dtso (100%) rename patch/kernel/archive/{rockchip-6.11 => rockchip-6.12}/overlay/rockchip-spi2.dtbo (100%) rename patch/kernel/archive/{rockchip-6.11 => rockchip-6.12}/overlay/rockchip-spi2.dtso (100%) rename patch/kernel/archive/{rockchip-6.11 => rockchip-6.12}/overlay/rockchip-spidev0.dtbo (100%) rename patch/kernel/archive/{rockchip-6.11 => rockchip-6.12}/overlay/rockchip-spidev0.dtso (100%) rename patch/kernel/archive/{rockchip-6.11 => rockchip-6.12}/overlay/rockchip-spidev2.dtbo (100%) rename patch/kernel/archive/{rockchip-6.11 => rockchip-6.12}/overlay/rockchip-spidev2.dtso (100%) rename patch/kernel/archive/{rockchip-6.11 => rockchip-6.12}/overlay/rockchip-uart1.dtbo (100%) rename patch/kernel/archive/{rockchip-6.11 => rockchip-6.12}/overlay/rockchip-uart1.dtso (100%) rename patch/kernel/archive/{rockchip-6.11 => rockchip-6.12}/overlay/rockchip-uart2.dtbo (100%) rename patch/kernel/archive/{rockchip-6.11 => rockchip-6.12}/overlay/rockchip-uart2.dtso (100%) rename patch/kernel/archive/{rockchip-6.11 => rockchip-6.12}/overlay/rockchip-uart3.dtbo (100%) rename patch/kernel/archive/{rockchip-6.11 => rockchip-6.12}/overlay/rockchip-uart3.dtso (100%) rename patch/kernel/archive/{rockchip-6.11 => rockchip-6.12}/overlay/rockchip-uart4.dtbo (100%) rename patch/kernel/archive/{rockchip-6.11 => rockchip-6.12}/overlay/rockchip-uart4.dtso (100%) rename patch/kernel/archive/{rockchip-6.11 => rockchip-6.12}/overlay/rockchip-w1-gpio.dtbo (100%) rename patch/kernel/archive/{rockchip-6.11 => rockchip-6.12}/overlay/rockchip-w1-gpio.dtso (100%) rename patch/kernel/archive/{rockchip-6.11 => rockchip-6.12}/patches.armbian/bt-broadcom-serdev-workaround.patch (100%) rename patch/kernel/archive/{rockchip-6.11 => rockchip-6.12}/patches.armbian/clk-rk322x-composite-mmc-clk.patch (100%) rename patch/kernel/archive/{rockchip-6.11 => rockchip-6.12}/patches.armbian/clk-rockchip-max-frac-divider.patch (100%) rename patch/kernel/archive/{rockchip-6.11 => rockchip-6.12}/patches.armbian/driver-rk322x-audio-codec.patch (100%) rename patch/kernel/archive/{rockchip-6.11 => rockchip-6.12}/patches.armbian/driver-rk3288-gpiomem.patch (100%) rename patch/kernel/archive/{rockchip-6.11 => rockchip-6.12}/patches.armbian/driver-tinkerboard-alc4040-codec.patch (100%) rename patch/kernel/archive/{rockchip-6.11 => rockchip-6.12}/patches.armbian/drm-rk322x-plane-overlay.patch (100%) rename patch/kernel/archive/{rockchip-6.11 => rockchip-6.12}/patches.armbian/drm-rk322x-yuv-10bit-modes.patch (100%) rename patch/kernel/archive/{rockchip-6.11 => rockchip-6.12}/patches.armbian/drm-rockchip-hardware-cursor.patch (95%) rename patch/kernel/archive/{rockchip-6.11 => rockchip-6.12}/patches.armbian/dts-miqi-fan.patch (100%) rename patch/kernel/archive/{rockchip-6.11 => rockchip-6.12}/patches.armbian/dts-miqi-hevc-rga.patch (100%) rename patch/kernel/archive/{rockchip-6.11 => rockchip-6.12}/patches.armbian/dts-miqi-mali-gpu.patch (100%) rename patch/kernel/archive/{rockchip-6.11 => rockchip-6.12}/patches.armbian/dts-miqi-regulator-fix.patch (100%) rename patch/kernel/archive/{rockchip-6.11 => rockchip-6.12}/patches.armbian/dts-rk322x-iep-node.patch (100%) rename patch/kernel/archive/{rockchip-6.11 => rockchip-6.12}/patches.armbian/dts-rk322x-pinctrl-nand.patch (100%) rename patch/kernel/archive/{rockchip-6.11 => rockchip-6.12}/patches.armbian/dts-rk3288-disable-serial-dma.patch (100%) rename patch/kernel/archive/{rockchip-6.11 => rockchip-6.12}/patches.armbian/dts-rk3288-fix-mmc-aliases.patch (100%) rename patch/kernel/archive/{rockchip-6.11 => rockchip-6.12}/patches.armbian/dts-rk3288-gpu-500mhz-opp.patch (100%) rename patch/kernel/archive/{rockchip-6.11 => rockchip-6.12}/patches.armbian/dts-rk3288-pinctrl-spi2.patch (100%) rename patch/kernel/archive/{rockchip-6.11 => rockchip-6.12}/patches.armbian/dts-rk3288-thermal-rearrange-zones.patch (100%) rename patch/kernel/archive/{rockchip-6.11 => rockchip-6.12}/patches.armbian/dts-tinkerboard-bt-rtl8723bs.patch (100%) rename patch/kernel/archive/{rockchip-6.11 => rockchip-6.12}/patches.armbian/dts-tinkerboard-bt-uart-pins.patch (100%) rename patch/kernel/archive/{rockchip-6.11 => rockchip-6.12}/patches.armbian/dts-tinkerboard-hevc-rga.patch (100%) rename patch/kernel/archive/{rockchip-6.11 => rockchip-6.12}/patches.armbian/dts-tinkerboard-sdio-wifi.patch (100%) rename patch/kernel/archive/{rockchip-6.11 => rockchip-6.12}/patches.armbian/dts-tinkerboard-sdmmc-properties.patch (100%) rename patch/kernel/archive/{rockchip-6.11 => rockchip-6.12}/patches.armbian/dts-tinkerboard-spi-interface.patch (100%) rename patch/kernel/archive/{rockchip-6.11 => rockchip-6.12}/patches.armbian/dts-veyron-flag-cache-flush.patch (100%) rename patch/kernel/archive/{rockchip-6.11 => rockchip-6.12}/patches.armbian/general-add-overlay-compilation-support.patch (54%) rename patch/kernel/archive/{rockchip-6.11 => rockchip-6.12}/patches.armbian/general-add-overlay-configfs.patch (100%) rename patch/kernel/archive/{rockchip-6.11 => rockchip-6.12}/patches.armbian/general-add-restart-handler-for-act8846.patch (100%) rename patch/kernel/archive/{rockchip-6.11 => rockchip-6.12}/patches.armbian/general-dwc2-fix-wait-peripheral.patch (100%) rename patch/kernel/archive/{rockchip-6.11 => rockchip-6.12}/patches.armbian/general-dwc2-fix-wait-time.patch (100%) rename patch/kernel/archive/{rockchip-6.11 => rockchip-6.12}/patches.armbian/general-dwc2-nak-gadget.patch (100%) rename patch/kernel/archive/{rockchip-6.11 => rockchip-6.12}/patches.armbian/general-fix-reboot-from-kwiboo.patch (100%) rename patch/kernel/archive/{rockchip-6.11 => rockchip-6.12}/patches.armbian/general-linux-export-mm-trace-rss-stats.patch (100%) rename patch/kernel/archive/{rockchip-6.11 => rockchip-6.12}/patches.armbian/general-rk322x-gpio-ir-driver.patch (100%) rename patch/kernel/archive/{rockchip-6.11 => rockchip-6.12}/patches.armbian/general-rockchip-various-fixes.patch (100%) rename patch/kernel/archive/{rockchip-6.11 => rockchip-6.12}/patches.armbian/ir-keymap-rk322x-box.patch (100%) rename patch/kernel/archive/{rockchip-6.11 => rockchip-6.12}/patches.armbian/ir-keymap-xt-q8l-v10.patch (100%) rename patch/kernel/archive/{rockchip-6.11 => rockchip-6.12}/patches.armbian/misc-tinkerboard-spi-interface.patch (100%) rename patch/kernel/archive/{rockchip-6.11 => rockchip-6.12}/patches.armbian/mmc-tinkerboard-sdmmc-reboot-fix.patch (100%) rename patch/kernel/archive/{rockchip-6.11 => rockchip-6.12}/patches.armbian/rk322x-dmc-driver-01-sipv2-calls.patch (100%) rename patch/kernel/archive/{rockchip-6.11 => rockchip-6.12}/patches.armbian/rk322x-dmc-driver-02-sip-constants.patch (100%) rename patch/kernel/archive/{rockchip-6.11 => rockchip-6.12}/patches.armbian/rk322x-dmc-driver-03-dfi-driver.patch (100%) rename patch/kernel/archive/{rockchip-6.11 => rockchip-6.12}/patches.armbian/rk322x-dmc-driver-04-driver.patch (100%) rename patch/kernel/archive/{rockchip-6.11 => rockchip-6.12}/patches.armbian/rk322x-dwc2-no-clock-gating.patch (100%) rename patch/kernel/archive/{rockchip-6.11 => rockchip-6.12}/patches.armbian/rk322x-usb-reset-props.patch (100%) rename patch/kernel/archive/{rockchip-6.11 => rockchip-6.12}/patches.armbian/wifi-ath9k-no-bulk-EP3-EP4.patch (100%) rename patch/kernel/archive/{rockchip-6.11 => rockchip-6.12}/patches.armbian/wifi-brcmfmac-add-bcm43342.patch (100%) rename patch/kernel/archive/{rockchip-6.11 => rockchip-6.12}/patches.armbian/wifi-brcmfmac-ap6330-firmware.patch (100%) rename patch/kernel/archive/{rockchip-6.11 => rockchip-6.12}/patches.armbian/wifi-driver-esp8089.patch (99%) rename patch/kernel/archive/{rockchip-6.11 => rockchip-6.12}/patches.armbian/wifi-driver-ssv6051.patch (99%) create mode 100644 patch/kernel/archive/rockchip-6.12/patches.libreelec/linux-0002-rockchip-from-list.patch create mode 100644 patch/kernel/archive/rockchip-6.12/patches.libreelec/linux-0011-v4l2-from-list.patch create mode 100644 patch/kernel/archive/rockchip-6.12/patches.libreelec/linux-1000-drm-rockchip.patch create mode 100644 patch/kernel/archive/rockchip-6.12/patches.libreelec/linux-1001-v4l2-rockchip.patch create mode 100644 patch/kernel/archive/rockchip-6.12/patches.libreelec/linux-1002-for-libreelec.patch create mode 100644 patch/kernel/archive/rockchip-6.12/patches.libreelec/linux-2000-v4l2-wip-rkvdec-hevc.patch create mode 100644 patch/kernel/archive/rockchip-6.12/patches.libreelec/linux-2001-v4l2-wip-iep-driver.patch rename patch/kernel/archive/{rockchip-6.11 => rockchip-6.12}/series.conf (98%) diff --git a/config/kernel/linux-rockchip-edge.config b/config/kernel/linux-rockchip-edge.config index a55f3b189ef0..28c124f67d6b 100644 --- a/config/kernel/linux-rockchip-edge.config +++ b/config/kernel/linux-rockchip-edge.config @@ -1,22 +1,24 @@ # # Automatically generated file; DO NOT EDIT. -# Linux/arm 6.11.0 Kernel Configuration +# Linux/arm 6.12.1 Kernel Configuration # -CONFIG_CC_VERSION_TEXT="arm-linux-gnueabihf-gcc (Ubuntu 11.3.0-1ubuntu1~22.04) 11.3.0" +CONFIG_CC_VERSION_TEXT="arm-linux-gnueabihf-gcc (Ubuntu 13.2.0-23ubuntu4) 13.2.0" CONFIG_CC_IS_GCC=y -CONFIG_GCC_VERSION=110300 +CONFIG_GCC_VERSION=130200 CONFIG_CLANG_VERSION=0 CONFIG_AS_IS_GNU=y -CONFIG_AS_VERSION=23800 +CONFIG_AS_VERSION=24200 CONFIG_LD_IS_BFD=y -CONFIG_LD_VERSION=23800 +CONFIG_LD_VERSION=24200 CONFIG_LLD_VERSION=0 +CONFIG_RUSTC_VERSION=0 +CONFIG_RUSTC_LLVM_VERSION=0 CONFIG_CC_CAN_LINK=y CONFIG_CC_CAN_LINK_STATIC=y CONFIG_GCC_ASM_GOTO_OUTPUT_BROKEN=y CONFIG_CC_HAS_ASM_INLINE=y CONFIG_CC_HAS_NO_PROFILE_FN_ATTR=y -CONFIG_PAHOLE_VERSION=122 +CONFIG_PAHOLE_VERSION=125 CONFIG_IRQ_WORK=y CONFIG_BUILDTIME_TABLE_SORT=y CONFIG_THREAD_INFO_IN_TASK=y @@ -169,6 +171,7 @@ CONFIG_MEMCG=y CONFIG_BLK_CGROUP=y CONFIG_CGROUP_WRITEBACK=y CONFIG_CGROUP_SCHED=y +CONFIG_GROUP_SCHED_WEIGHT=y CONFIG_FAIR_GROUP_SCHED=y CONFIG_CFS_BANDWIDTH=y CONFIG_RT_GROUP_SCHED=y @@ -177,6 +180,7 @@ CONFIG_CGROUP_PIDS=y CONFIG_CGROUP_RDMA=y CONFIG_CGROUP_FREEZER=y CONFIG_CPUSETS=y +# CONFIG_CPUSETS_V1 is not set CONFIG_PROC_PID_CPUSET=y CONFIG_CGROUP_DEVICE=y CONFIG_CGROUP_CPUACCT=y @@ -482,6 +486,8 @@ CONFIG_ALIGNMENT_TRAP=y # CONFIG_PARAVIRT is not set # CONFIG_PARAVIRT_TIME_ACCOUNTING is not set # CONFIG_XEN is not set +CONFIG_CC_HAVE_STACKPROTECTOR_TLS=y +CONFIG_STACKPROTECTOR_PER_TASK=y # end of Kernel Features # @@ -497,6 +503,7 @@ CONFIG_ZBOOT_ROM_BSS=0x0 CONFIG_CMDLINE="" CONFIG_ARCH_SUPPORTS_KEXEC=y CONFIG_ARCH_SUPPORTS_CRASH_DUMP=y +CONFIG_ARCH_DEFAULT_CRASH_DUMP=y CONFIG_AUTO_ZRELADDR=y # CONFIG_EFI is not set # end of Boot options @@ -597,6 +604,7 @@ CONFIG_ARCH_HIBERNATION_POSSIBLE=y CONFIG_AS_VFP_VMRS_FPINST=y CONFIG_CPU_MITIGATIONS=y +CONFIG_ARCH_HAS_DMA_OPS=y # # General architecture-dependent options @@ -702,10 +710,7 @@ CONFIG_MODULE_FORCE_UNLOAD=y # CONFIG_MODVERSIONS is not set # CONFIG_MODULE_SRCVERSION_ALL is not set # CONFIG_MODULE_SIG is not set -CONFIG_MODULE_COMPRESS_NONE=y -# CONFIG_MODULE_COMPRESS_GZIP is not set -# CONFIG_MODULE_COMPRESS_XZ is not set -# CONFIG_MODULE_COMPRESS_ZSTD is not set +# CONFIG_MODULE_COMPRESS is not set # CONFIG_MODULE_ALLOW_MISSING_NAMESPACE_IMPORTS is not set CONFIG_MODPROBE_PATH="/sbin/modprobe" # CONFIG_TRIM_UNUSED_KSYMS is not set @@ -815,12 +820,12 @@ CONFIG_ZSWAP_SHRINKER_DEFAULT_ON=y CONFIG_ZSWAP_COMPRESSOR_DEFAULT_ZSTD=y CONFIG_ZSWAP_COMPRESSOR_DEFAULT="zstd" # CONFIG_ZSWAP_ZPOOL_DEFAULT_ZBUD is not set -CONFIG_ZSWAP_ZPOOL_DEFAULT_Z3FOLD=y +CONFIG_ZSWAP_ZPOOL_DEFAULT_Z3FOLD_DEPRECATED=y # CONFIG_ZSWAP_ZPOOL_DEFAULT_ZSMALLOC is not set CONFIG_ZSWAP_ZPOOL_DEFAULT="z3fold" CONFIG_ZBUD=y +CONFIG_Z3FOLD_DEPRECATED=y CONFIG_Z3FOLD=y -CONFIG_HAVE_ZSMALLOC=y CONFIG_ZSMALLOC=y # CONFIG_ZSMALLOC_STAT is not set CONFIG_ZSMALLOC_CHAIN_SIZE=8 @@ -848,7 +853,7 @@ CONFIG_FLATMEM=y CONFIG_ARCH_KEEP_MEMBLOCK=y CONFIG_MEMORY_ISOLATION=y CONFIG_EXCLUSIVE_SYSTEM_RAM=y -CONFIG_SPLIT_PTLOCK_CPUS=4 +CONFIG_SPLIT_PTE_PTLOCKS=y CONFIG_COMPACTION=y CONFIG_COMPACT_UNEVICTABLE_DEFAULT=1 # CONFIG_PAGE_REPORTING is not set @@ -898,6 +903,7 @@ CONFIG_NET_EGRESS=y CONFIG_NET_XGRESS=y CONFIG_NET_REDIRECT=y CONFIG_SKB_EXTENSIONS=y +CONFIG_NET_DEVMEM=y # # Networking options @@ -1672,6 +1678,7 @@ CONFIG_BT_HCIUART_RTL=y # CONFIG_BT_HCIUART_QCA is not set # CONFIG_BT_HCIUART_AG6XX is not set # CONFIG_BT_HCIUART_MRVL is not set +# CONFIG_BT_HCIUART_AML is not set # CONFIG_BT_HCIBCM203X is not set # CONFIG_BT_HCIBPA10X is not set CONFIG_BT_HCIBFUSB=y @@ -1715,7 +1722,6 @@ CONFIG_MAC80211_RC_DEFAULT="minstrel_ht" CONFIG_MAC80211_MESH=y CONFIG_MAC80211_LEDS=y CONFIG_MAC80211_DEBUGFS=y -# CONFIG_MAC80211_MESSAGE_TRACING is not set # CONFIG_MAC80211_DEBUG_MENU is not set CONFIG_MAC80211_STA_HASH_MAX_SIZE=0 CONFIG_RFKILL=y @@ -1783,6 +1789,7 @@ CONFIG_DEV_COREDUMP=y # CONFIG_DEBUG_DEVRES is not set # CONFIG_DEBUG_TEST_DRIVER_REMOVE is not set # CONFIG_TEST_ASYNC_DRIVER_PROBE is not set +CONFIG_GENERIC_CPU_DEVICES=y CONFIG_GENERIC_CPU_AUTOPROBE=y CONFIG_GENERIC_CPU_VULNERABILITIES=y CONFIG_SOC_BUS=y @@ -1824,12 +1831,26 @@ CONFIG_PROC_EVENTS=y # CONFIG_ARM_SCMI_PROTOCOL=m # CONFIG_ARM_SCMI_RAW_MODE_SUPPORT is not set +# CONFIG_ARM_SCMI_DEBUG_COUNTERS is not set + +# +# SCMI Transport Drivers +# CONFIG_ARM_SCMI_HAVE_TRANSPORT=y CONFIG_ARM_SCMI_HAVE_SHMEM=y -# CONFIG_ARM_SCMI_TRANSPORT_OPTEE is not set -CONFIG_ARM_SCMI_TRANSPORT_SMC=y +CONFIG_ARM_SCMI_TRANSPORT_SMC=m # CONFIG_ARM_SCMI_TRANSPORT_SMC_ATOMIC_ENABLE is not set +# CONFIG_ARM_SCMI_TRANSPORT_OPTEE is not set # CONFIG_ARM_SCMI_TRANSPORT_VIRTIO is not set +# end of SCMI Transport Drivers + +# +# ARM SCMI NXP i.MX Vendor Protocols +# +# CONFIG_IMX_SCMI_BBM_EXT is not set +# CONFIG_IMX_SCMI_MISC_EXT is not set +# end of ARM SCMI NXP i.MX Vendor Protocols + # CONFIG_ARM_SCMI_POWER_CONTROL is not set # end of ARM System Control and Management Interface Protocol @@ -1880,13 +1901,17 @@ CONFIG_BLK_DEV=y # CONFIG_BLK_DEV_NULL_BLK is not set CONFIG_CDROM=y CONFIG_ZRAM=m -CONFIG_ZRAM_DEF_COMP_LZORLE=y -# CONFIG_ZRAM_DEF_COMP_ZSTD is not set -# CONFIG_ZRAM_DEF_COMP_LZ4 is not set +# CONFIG_ZRAM_BACKEND_LZ4 is not set +# CONFIG_ZRAM_BACKEND_LZ4HC is not set +CONFIG_ZRAM_BACKEND_ZSTD=y +CONFIG_ZRAM_BACKEND_DEFLATE=y +# CONFIG_ZRAM_BACKEND_842 is not set +CONFIG_ZRAM_BACKEND_LZO=y +# CONFIG_ZRAM_DEF_COMP_LZORLE is not set # CONFIG_ZRAM_DEF_COMP_LZO is not set -# CONFIG_ZRAM_DEF_COMP_LZ4HC is not set -# CONFIG_ZRAM_DEF_COMP_842 is not set -CONFIG_ZRAM_DEF_COMP="lzo-rle" +CONFIG_ZRAM_DEF_COMP_ZSTD=y +# CONFIG_ZRAM_DEF_COMP_DEFLATE is not set +CONFIG_ZRAM_DEF_COMP="zstd" CONFIG_ZRAM_WRITEBACK=y CONFIG_ZRAM_TRACK_ENTRY_ACTIME=y # CONFIG_ZRAM_MEMORY_TRACKING is not set @@ -1925,6 +1950,7 @@ CONFIG_NVME_TCP=m # # CONFIG_AD525X_DPOT is not set # CONFIG_DUMMY_IRQ is not set +CONFIG_RPMB=y # CONFIG_ICS932S401 is not set # CONFIG_ENCLOSURE_SERVICES is not set # CONFIG_APDS9802ALS is not set @@ -2180,6 +2206,7 @@ CONFIG_NET_VENDOR_NI=y # CONFIG_NET_VENDOR_NATSEMI is not set # CONFIG_NET_VENDOR_NETRONOME is not set # CONFIG_ETHOC is not set +# CONFIG_OA_TC6 is not set CONFIG_NET_VENDOR_PENSANDO=y # CONFIG_NET_VENDOR_QUALCOMM is not set # CONFIG_NET_VENDOR_RENESAS is not set @@ -2289,13 +2316,16 @@ CONFIG_CAN_TI_HECC=m CONFIG_CAN_C_CAN=m CONFIG_CAN_C_CAN_PLATFORM=m CONFIG_CAN_CC770=m +# CONFIG_CAN_CC770_ISA is not set CONFIG_CAN_CC770_PLATFORM=m # CONFIG_CAN_CTUCANFD_PLATFORM is not set CONFIG_CAN_IFI_CANFD=m CONFIG_CAN_M_CAN=m CONFIG_CAN_M_CAN_PLATFORM=m CONFIG_CAN_M_CAN_TCAN4X5X=m +# CONFIG_CAN_ROCKCHIP_CANFD is not set CONFIG_CAN_SJA1000=m +# CONFIG_CAN_SJA1000_ISA is not set CONFIG_CAN_SJA1000_PLATFORM=m CONFIG_CAN_SOFTING=m @@ -2468,7 +2498,6 @@ CONFIG_BRCMFMAC=m CONFIG_BRCMFMAC_PROTO_BCDC=y CONFIG_BRCMFMAC_SDIO=y # CONFIG_BRCMFMAC_USB is not set -# CONFIG_BRCM_TRACING is not set # CONFIG_BRCMDBG is not set CONFIG_WLAN_VENDOR_INTEL=y CONFIG_WLAN_VENDOR_INTERSIL=y @@ -2640,7 +2669,6 @@ CONFIG_KEYBOARD_MATRIX=m # CONFIG_KEYBOARD_LM8323 is not set # CONFIG_KEYBOARD_LM8333 is not set # CONFIG_KEYBOARD_MAX7359 is not set -# CONFIG_KEYBOARD_MCS is not set # CONFIG_KEYBOARD_MPR121 is not set # CONFIG_KEYBOARD_NEWTON is not set # CONFIG_KEYBOARD_OPENCORES is not set @@ -2723,7 +2751,6 @@ CONFIG_TOUCHSCREEN_BU21029=m # CONFIG_TOUCHSCREEN_CY8CTMA140 is not set # CONFIG_TOUCHSCREEN_CY8CTMG110 is not set # CONFIG_TOUCHSCREEN_CYTTSP_CORE is not set -# CONFIG_TOUCHSCREEN_CYTTSP4_CORE is not set # CONFIG_TOUCHSCREEN_CYTTSP5 is not set # CONFIG_TOUCHSCREEN_DYNAPRO is not set # CONFIG_TOUCHSCREEN_HAMPSHIRE is not set @@ -2748,7 +2775,6 @@ CONFIG_TOUCHSCREEN_ELAN=y # CONFIG_TOUCHSCREEN_WACOM_W8001 is not set # CONFIG_TOUCHSCREEN_WACOM_I2C is not set # CONFIG_TOUCHSCREEN_MAX11801 is not set -# CONFIG_TOUCHSCREEN_MCS5000 is not set # CONFIG_TOUCHSCREEN_MMS114 is not set # CONFIG_TOUCHSCREEN_MELFAS_MIP4 is not set # CONFIG_TOUCHSCREEN_MSG2638 is not set @@ -2954,6 +2980,7 @@ CONFIG_HW_RANDOM_OPTEE=m # CONFIG_HW_RANDOM_CCTRNG is not set # CONFIG_HW_RANDOM_XIPHERA is not set CONFIG_HW_RANDOM_ARM_SMCCC_TRNG=y +CONFIG_HW_RANDOM_ROCKCHIP=y CONFIG_DEVMEM=y CONFIG_DEVPORT=y CONFIG_TCG_TPM=y @@ -2980,7 +3007,6 @@ CONFIG_TCG_TIS_I2C_INFINEON=y # CONFIG_I2C=y CONFIG_I2C_BOARDINFO=y -CONFIG_I2C_COMPAT=y CONFIG_I2C_CHARDEV=y CONFIG_I2C_MUX=y @@ -3010,6 +3036,8 @@ CONFIG_I2C_ALGOBIT=m # I2C system bus drivers (mostly embedded / system-on-chip) # # CONFIG_I2C_CBUS_GPIO is not set +CONFIG_I2C_DESIGNWARE_CORE=y +CONFIG_I2C_DESIGNWARE_SLAVE=y # CONFIG_I2C_DESIGNWARE_PLATFORM is not set # CONFIG_I2C_EMEV2 is not set # CONFIG_I2C_GPIO is not set @@ -3506,6 +3534,7 @@ CONFIG_THERMAL=y # CONFIG_THERMAL_NETLINK is not set # CONFIG_THERMAL_STATISTICS is not set # CONFIG_THERMAL_DEBUGFS is not set +# CONFIG_THERMAL_CORE_TESTING is not set CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0 CONFIG_THERMAL_HWMON=y CONFIG_THERMAL_OF=y @@ -3565,6 +3594,7 @@ CONFIG_BCMA_POSSIBLE=y # Multifunction device drivers # CONFIG_MFD_CORE=y +# CONFIG_MFD_ADP5585 is not set # CONFIG_MFD_ACT8945A is not set # CONFIG_MFD_AS3711 is not set # CONFIG_MFD_SMPRO is not set @@ -4077,7 +4107,6 @@ CONFIG_VIDEO_MUX=m # # Chips&Media media platform drivers # -# CONFIG_VIDEO_E5010_JPEG_ENC is not set # # Intel media platform drivers @@ -4114,7 +4143,6 @@ CONFIG_VIDEO_MUX=m # # Raspberry Pi media platform drivers # -# CONFIG_VIDEO_RASPBERRYPI_PISP_BE is not set # # Renesas media platform drivers @@ -4148,6 +4176,7 @@ CONFIG_DVB_C8SECTPFE=m # Verisilicon media platform drivers # CONFIG_VIDEO_HANTRO=m +# CONFIG_VIDEO_HANTRO_HEVC_RFC is not set CONFIG_VIDEO_HANTRO_ROCKCHIP=y # @@ -4632,6 +4661,7 @@ CONFIG_VIDEO=y CONFIG_DRM=y # CONFIG_DRM_DEBUG_MM is not set CONFIG_DRM_KMS_HELPER=y +# CONFIG_DRM_PANIC is not set # CONFIG_DRM_DEBUG_DP_MST_TOPOLOGY_REFS is not set # CONFIG_DRM_DEBUG_MODESET_LOCK is not set CONFIG_DRM_FBDEV_EMULATION=y @@ -4711,6 +4741,7 @@ CONFIG_DRM_PANEL=y # CONFIG_DRM_PANEL_SAMSUNG_S6E8AA0 is not set # CONFIG_DRM_PANEL_SEIKO_43WVF1G is not set # CONFIG_DRM_PANEL_SHARP_LS037V7DW01 is not set +# CONFIG_DRM_PANEL_SITRONIX_ST7701 is not set # CONFIG_DRM_PANEL_SITRONIX_ST7789V is not set # CONFIG_DRM_PANEL_SONY_ACX565AKM is not set # CONFIG_DRM_PANEL_EDP is not set @@ -4899,10 +4930,10 @@ CONFIG_SND_MAX_CARDS=32 CONFIG_SND_SUPPORT_OLD_API=y CONFIG_SND_PROC_FS=y CONFIG_SND_VERBOSE_PROCFS=y -# CONFIG_SND_VERBOSE_PRINTK is not set CONFIG_SND_CTL_FAST_LOOKUP=y # CONFIG_SND_DEBUG is not set # CONFIG_SND_CTL_INPUT_VALIDATION is not set +# CONFIG_SND_UTIMER is not set CONFIG_SND_SEQUENCER=m CONFIG_SND_SEQ_DUMMY=m CONFIG_SND_SEQ_HRTIMER_DEFAULT=y @@ -5183,6 +5214,7 @@ CONFIG_SND_SOC_WM8904=m # CONFIG_SND_SOC_ZL38060 is not set CONFIG_SND_SOC_MAX9759=m CONFIG_SND_SOC_MT6351=m +# CONFIG_SND_SOC_MT6357 is not set CONFIG_SND_SOC_MT6358=m # CONFIG_SND_SOC_MT6660 is not set # CONFIG_SND_SOC_NAU8315 is not set @@ -5250,6 +5282,7 @@ CONFIG_HID_GFRM=m # CONFIG_HID_GLORIOUS is not set CONFIG_HID_HOLTEK=m CONFIG_HOLTEK_FF=y +# CONFIG_HID_GOODIX_SPI is not set # CONFIG_HID_GOOGLE_STADIA_FF is not set # CONFIG_HID_VIVALDI is not set CONFIG_HID_GT683R=m @@ -5862,6 +5895,7 @@ CONFIG_RTC_DRV_EM3027=m CONFIG_RTC_DRV_RV3028=m # CONFIG_RTC_DRV_RV3032 is not set CONFIG_RTC_DRV_RV8803=m +# CONFIG_RTC_DRV_SD2405AL is not set CONFIG_RTC_DRV_SD3078=m # @@ -5948,6 +5982,7 @@ CONFIG_PL330_DMA=y # CONFIG_XILINX_DMA is not set # CONFIG_XILINX_XDMA is not set # CONFIG_XILINX_ZYNQMP_DPDMA is not set +# CONFIG_AMD_QDMA is not set # CONFIG_QCOM_HIDMA_MGMT is not set # CONFIG_QCOM_HIDMA is not set CONFIG_DW_DMAC_CORE=m @@ -6080,7 +6115,6 @@ CONFIG_FB_TFT_UC1611=m CONFIG_FB_TFT_UC1701=m CONFIG_FB_TFT_UPD161704=m # CONFIG_MOST_COMPONENTS is not set -# CONFIG_KS7010 is not set # CONFIG_XIL_AXIS_FIFO is not set CONFIG_FIELDBUS_DEV=m CONFIG_HMS_ANYBUSS_BUS=m @@ -6299,6 +6333,7 @@ CONFIG_EXTCON=y # CONFIG_EXTCON_ADC_JACK is not set # CONFIG_EXTCON_FSA9480 is not set # CONFIG_EXTCON_GPIO is not set +# CONFIG_EXTCON_LC824206XA is not set # CONFIG_EXTCON_MAX3355 is not set # CONFIG_EXTCON_PTN5150 is not set # CONFIG_EXTCON_RT8973A is not set @@ -6338,6 +6373,8 @@ CONFIG_ADXL345_SPI=m # CONFIG_ADXL367_I2C is not set # CONFIG_ADXL372_SPI is not set # CONFIG_ADXL372_I2C is not set +# CONFIG_ADXL380_SPI is not set +# CONFIG_ADXL380_I2C is not set # CONFIG_BMA180 is not set # CONFIG_BMA220 is not set # CONFIG_BMA400 is not set @@ -6375,7 +6412,9 @@ CONFIG_HID_SENSOR_ACCEL_3D=m # # Analog to digital converters # +# CONFIG_AD4000 is not set # CONFIG_AD4130 is not set +# CONFIG_AD4695 is not set # CONFIG_AD7091R5 is not set # CONFIG_AD7091R8 is not set # CONFIG_AD7124 is not set @@ -6427,6 +6466,7 @@ CONFIG_AD7768_1=m # CONFIG_MCP3564 is not set # CONFIG_MCP3911 is not set # CONFIG_NAU7802 is not set +# CONFIG_PAC1921 is not set # CONFIG_PAC1934 is not set CONFIG_ROCKCHIP_SARADC=y # CONFIG_RICHTEK_RTQ6056 is not set @@ -6558,6 +6598,7 @@ CONFIG_AD5758=m # CONFIG_DS4424 is not set # CONFIG_LTC1660 is not set # CONFIG_LTC2632 is not set +# CONFIG_LTC2664 is not set # CONFIG_M62332 is not set # CONFIG_MAX517 is not set # CONFIG_MAX5522 is not set @@ -6644,6 +6685,7 @@ CONFIG_MAX30102=m # # CONFIG_AM2315 is not set # CONFIG_DHT11 is not set +# CONFIG_ENS210 is not set # CONFIG_HDC100X is not set # CONFIG_HDC2010 is not set # CONFIG_HDC3020 is not set @@ -6692,6 +6734,7 @@ CONFIG_IIO_ADIS_LIB_BUFFER=y # CONFIG_APDS9306 is not set # CONFIG_APDS9960 is not set # CONFIG_AS73211 is not set +# CONFIG_BH1745 is not set # CONFIG_BH1750 is not set # CONFIG_BH1780 is not set # CONFIG_CM32181 is not set @@ -6831,6 +6874,7 @@ CONFIG_HID_SENSOR_PRESS=m # CONFIG_MPRLS0025PA is not set # CONFIG_MS5611 is not set # CONFIG_MS5637 is not set +# CONFIG_SDP500 is not set # CONFIG_IIO_ST_PRESS is not set # CONFIG_T5403 is not set # CONFIG_HP206C is not set @@ -6846,6 +6890,7 @@ CONFIG_HID_SENSOR_PRESS=m # # Proximity and distance sensors # +# CONFIG_HX9023S is not set # CONFIG_IRSD200 is not set CONFIG_ISL29501=m # CONFIG_LIDAR_LITE_V2 is not set @@ -6860,6 +6905,7 @@ CONFIG_MB1232=m # CONFIG_SRF08 is not set # CONFIG_VCNL3020 is not set # CONFIG_VL53L0X_I2C is not set +# CONFIG_AW96103 is not set # end of Proximity and distance sensors # @@ -6997,6 +7043,7 @@ CONFIG_NVMEM_LAYOUTS=y # # CONFIG_NVMEM_LAYOUT_SL28_VPD is not set # CONFIG_NVMEM_LAYOUT_ONIE_TLV is not set +# CONFIG_NVMEM_LAYOUT_U_BOOT_ENV is not set # end of Layout Types # CONFIG_NVMEM_RMEM is not set @@ -7116,6 +7163,7 @@ CONFIG_BCACHEFS_POSIX_ACL=y # CONFIG_BCACHEFS_LOCK_TIME_STATS is not set # CONFIG_BCACHEFS_NO_LATENCY_ACCT is not set CONFIG_BCACHEFS_SIX_OPTIMISTIC_SPIN=y +# CONFIG_BCACHEFS_PATH_TRACEPOINTS is not set CONFIG_FS_POSIX_ACL=y CONFIG_EXPORTFS=y CONFIG_EXPORTFS_BLOCK_OPS=y @@ -7254,6 +7302,7 @@ CONFIG_EROFS_FS=m CONFIG_EROFS_FS_XATTR=y CONFIG_EROFS_FS_POSIX_ACL=y CONFIG_EROFS_FS_SECURITY=y +CONFIG_EROFS_FS_BACKED_BY_FILE=y # CONFIG_EROFS_FS_ZIP is not set # CONFIG_EROFS_FS_ONDEMAND is not set CONFIG_NETWORK_FILESYSTEMS=y @@ -7292,6 +7341,7 @@ CONFIG_LOCKD=m CONFIG_LOCKD_V4=y CONFIG_NFS_ACL_SUPPORT=m CONFIG_NFS_COMMON=y +# CONFIG_NFS_LOCALIO is not set CONFIG_NFS_V4_2_SSC_HELPER=y CONFIG_SUNRPC=m CONFIG_SUNRPC_GSS=m @@ -7316,6 +7366,7 @@ CONFIG_CIFS_POSIX=y # CONFIG_CIFS_DFS_UPCALL is not set # CONFIG_CIFS_SWN_UPCALL is not set CONFIG_CIFS_FSCACHE=y +CONFIG_CIFS_COMPRESSION=y CONFIG_SMB_SERVER=m CONFIG_SMB_SERVER_CHECK_CAP_NET_ADMIN=y CONFIG_SMB_SERVER_KERBEROS5=y @@ -7389,6 +7440,9 @@ CONFIG_KEYS=y # CONFIG_ENCRYPTED_KEYS is not set # CONFIG_KEY_DH_OPERATIONS is not set # CONFIG_SECURITY_DMESG_RESTRICT is not set +CONFIG_PROC_MEM_ALWAYS_FORCE=y +# CONFIG_PROC_MEM_FORCE_PTRACE is not set +# CONFIG_PROC_MEM_NO_FORCE is not set CONFIG_SECURITY=y CONFIG_SECURITYFS=y CONFIG_SECURITY_NETWORK=y @@ -7412,6 +7466,7 @@ CONFIG_SECURITY_YAMA=y # CONFIG_SECURITY_SAFESETID is not set # CONFIG_SECURITY_LOCKDOWN_LSM is not set # CONFIG_SECURITY_LANDLOCK is not set +# CONFIG_SECURITY_IPE is not set CONFIG_INTEGRITY=y # CONFIG_INTEGRITY_SIGNATURE is not set CONFIG_INTEGRITY_AUDIT=y @@ -7428,7 +7483,12 @@ CONFIG_LSM="yama,loadpin,safesetid,integrity" # # Memory initialization # +CONFIG_CC_HAS_AUTO_VAR_INIT_PATTERN=y +CONFIG_CC_HAS_AUTO_VAR_INIT_ZERO_BARE=y +CONFIG_CC_HAS_AUTO_VAR_INIT_ZERO=y CONFIG_INIT_STACK_NONE=y +# CONFIG_INIT_STACK_ALL_PATTERN is not set +# CONFIG_INIT_STACK_ALL_ZERO is not set # CONFIG_INIT_ON_ALLOC_DEFAULT_ON is not set # CONFIG_INIT_ON_FREE_DEFAULT_ON is not set CONFIG_CC_HAS_ZERO_CALL_USED_REGS=y @@ -7763,7 +7823,9 @@ CONFIG_XZ_DEC_X86=y CONFIG_XZ_DEC_POWERPC=y CONFIG_XZ_DEC_ARM=y CONFIG_XZ_DEC_ARMTHUMB=y +CONFIG_XZ_DEC_ARM64=y CONFIG_XZ_DEC_SPARC=y +CONFIG_XZ_DEC_RISCV=y # CONFIG_XZ_DEC_MICROLZMA is not set CONFIG_XZ_DEC_BCJ=y # CONFIG_XZ_DEC_TEST is not set @@ -7791,7 +7853,7 @@ CONFIG_HAS_IOMEM=y CONFIG_HAS_IOPORT=y CONFIG_HAS_IOPORT_MAP=y CONFIG_HAS_DMA=y -CONFIG_DMA_OPS=y +CONFIG_DMA_OPS_HELPERS=y CONFIG_NEED_SG_DMA_LENGTH=y CONFIG_NEED_DMA_MAP_STATE=y CONFIG_DMA_DECLARE_COHERENT=y diff --git a/config/sources/families/rockchip.conf b/config/sources/families/rockchip.conf index 6650d68c7802..a3ad9d0c191b 100644 --- a/config/sources/families/rockchip.conf +++ b/config/sources/families/rockchip.conf @@ -56,7 +56,7 @@ case $BRANCH in edge) - declare -g KERNEL_MAJOR_MINOR="6.11" # Major and minor versions of this kernel. + declare -g KERNEL_MAJOR_MINOR="6.12" # Major and minor versions of this kernel. ;; esac diff --git a/patch/kernel/archive/rockchip-6.11/patches.libreelec/linux-1003-temp-dw_hdmi-rockchip.patch b/patch/kernel/archive/rockchip-6.11/patches.libreelec/linux-1003-temp-dw_hdmi-rockchip.patch deleted file mode 100644 index 649732ddbedd..000000000000 --- a/patch/kernel/archive/rockchip-6.11/patches.libreelec/linux-1003-temp-dw_hdmi-rockchip.patch +++ /dev/null @@ -1,63 +0,0 @@ -diff --git a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c -index 0370bb247fcb..55c0b8dddad5 100644 ---- a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c 2023-06-25 03:23:55.724209412 +0000 -+++ b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c 2023-06-25 04:16:27.469899470 +0000 -@@ -254,35 +245,31 @@ - const struct drm_display_info *info, - const struct drm_display_mode *mode) - { -- struct rockchip_hdmi *hdmi = data; -- const struct dw_hdmi_mpll_config *mpll_cfg = rockchip_mpll_cfg; -- int pclk = mode->clock * 1000; -- bool exact_match = hdmi->plat_data->phy_force_vendor; -- int i; -- -- if (hdmi->ref_clk) { -- int rpclk = clk_round_rate(hdmi->ref_clk, pclk); -- -- if (abs(rpclk - pclk) > pclk / 1000) -- return MODE_NOCLOCK; -- } -- -- for (i = 0; mpll_cfg[i].mpixelclock != (~0UL); i++) { -- /* -- * For vendor specific phys force an exact match of the pixelclock -- * to preserve the original behaviour of the driver. -- */ -- if (exact_match && pclk == mpll_cfg[i].mpixelclock) -- return MODE_OK; -- /* -- * The Synopsys phy can work with pixelclocks up to the value given -- * in the corresponding mpll_cfg entry. -- */ -- if (!exact_match && pclk <= mpll_cfg[i].mpixelclock) -- return MODE_OK; -+ struct dw_hdmi_plat_data *pdata = (struct dw_hdmi_plat_data *)data; -+ const struct dw_hdmi_mpll_config *mpll_cfg = pdata->mpll_cfg; -+ int clock = mode->clock; -+ unsigned int i = 0; -+ -+ if (pdata->ycbcr_420_allowed && drm_mode_is_420(info, mode) && -+ (info->color_formats & DRM_COLOR_FORMAT_YCBCR420)) { -+ clock /= 2; -+ mpll_cfg = pdata->mpll_cfg_420; -+ } -+ -+ if ((!mpll_cfg && clock > 340000) || -+ (info->max_tmds_clock && clock > info->max_tmds_clock)) -+ return MODE_CLOCK_HIGH; -+ -+ if (mpll_cfg) { -+ while ((clock * 1000) < mpll_cfg[i].mpixelclock && -+ mpll_cfg[i].mpixelclock != (~0UL)) -+ i++; -+ -+ if (mpll_cfg[i].mpixelclock == (~0UL)) -+ return MODE_CLOCK_HIGH; - } - -- return MODE_BAD; -+ return MODE_OK; - } - - static void dw_hdmi_rockchip_encoder_disable(struct drm_encoder *encoder) diff --git a/patch/kernel/archive/rockchip-6.11/0000.patching_config.yaml b/patch/kernel/archive/rockchip-6.12/0000.patching_config.yaml similarity index 95% rename from patch/kernel/archive/rockchip-6.11/0000.patching_config.yaml rename to patch/kernel/archive/rockchip-6.12/0000.patching_config.yaml index c956d602cc6c..141801ee796c 100644 --- a/patch/kernel/archive/rockchip-6.11/0000.patching_config.yaml +++ b/patch/kernel/archive/rockchip-6.12/0000.patching_config.yaml @@ -1,10 +1,10 @@ config: # Just some info stuff; not used by the patching scripts - name: rockchip-6.11 + name: rockchip-6.12 kind: kernel type: mainline # or: vendor - branch: linux-6.11.y - last-known-good-tag: v6.11 + branch: linux-6.12.y + last-known-good-tag: v6.12 maintainers: - { github: paolo.sabatino, name: Paolo Sabatino, email: paolo.sabatino@gmail.com, armbian-forum: jock } diff --git a/patch/kernel/archive/rockchip-6.11/armbian.series b/patch/kernel/archive/rockchip-6.12/armbian.series similarity index 100% rename from patch/kernel/archive/rockchip-6.11/armbian.series rename to patch/kernel/archive/rockchip-6.12/armbian.series diff --git a/patch/kernel/archive/rockchip-6.11/dt/rk322x-box.dts b/patch/kernel/archive/rockchip-6.12/dt/rk322x-box.dts similarity index 100% rename from patch/kernel/archive/rockchip-6.11/dt/rk322x-box.dts rename to patch/kernel/archive/rockchip-6.12/dt/rk322x-box.dts diff --git a/patch/kernel/archive/rockchip-6.11/dt/rk3288-xt-q8l-v10.dts b/patch/kernel/archive/rockchip-6.12/dt/rk3288-xt-q8l-v10.dts similarity index 100% rename from patch/kernel/archive/rockchip-6.11/dt/rk3288-xt-q8l-v10.dts rename to patch/kernel/archive/rockchip-6.12/dt/rk3288-xt-q8l-v10.dts diff --git a/patch/kernel/archive/rockchip-6.11/kernel-6.8-tools-cgroup-makefile.patch b/patch/kernel/archive/rockchip-6.12/kernel-6.8-tools-cgroup-makefile.patch similarity index 100% rename from patch/kernel/archive/rockchip-6.11/kernel-6.8-tools-cgroup-makefile.patch rename to patch/kernel/archive/rockchip-6.12/kernel-6.8-tools-cgroup-makefile.patch diff --git a/patch/kernel/archive/rockchip-6.11/libreelec.series b/patch/kernel/archive/rockchip-6.12/libreelec.series similarity index 87% rename from patch/kernel/archive/rockchip-6.11/libreelec.series rename to patch/kernel/archive/rockchip-6.12/libreelec.series index 6d4878166c87..baa5c9472284 100644 --- a/patch/kernel/archive/rockchip-6.11/libreelec.series +++ b/patch/kernel/archive/rockchip-6.12/libreelec.series @@ -4,6 +4,5 @@ patches.libreelec/linux-1000-drm-rockchip.patch patches.libreelec/linux-1001-v4l2-rockchip.patch patches.libreelec/linux-1002-for-libreelec.patch - patches.libreelec/linux-1003-temp-dw_hdmi-rockchip.patch patches.libreelec/linux-2000-v4l2-wip-rkvdec-hevc.patch patches.libreelec/linux-2001-v4l2-wip-iep-driver.patch diff --git a/patch/kernel/archive/rockchip-6.11/overlay/Makefile b/patch/kernel/archive/rockchip-6.12/overlay/Makefile similarity index 100% rename from patch/kernel/archive/rockchip-6.11/overlay/Makefile rename to patch/kernel/archive/rockchip-6.12/overlay/Makefile diff --git a/patch/kernel/archive/rockchip-6.11/overlay/README.rk322x-overlays b/patch/kernel/archive/rockchip-6.12/overlay/README.rk322x-overlays similarity index 100% rename from patch/kernel/archive/rockchip-6.11/overlay/README.rk322x-overlays rename to patch/kernel/archive/rockchip-6.12/overlay/README.rk322x-overlays diff --git a/patch/kernel/archive/rockchip-6.11/overlay/README.rockchip-overlays b/patch/kernel/archive/rockchip-6.12/overlay/README.rockchip-overlays similarity index 100% rename from patch/kernel/archive/rockchip-6.11/overlay/README.rockchip-overlays rename to patch/kernel/archive/rockchip-6.12/overlay/README.rockchip-overlays diff --git a/patch/kernel/archive/rockchip-6.11/overlay/rk322x-bt-8723cs.dtso b/patch/kernel/archive/rockchip-6.12/overlay/rk322x-bt-8723cs.dtso similarity index 100% rename from patch/kernel/archive/rockchip-6.11/overlay/rk322x-bt-8723cs.dtso rename to patch/kernel/archive/rockchip-6.12/overlay/rk322x-bt-8723cs.dtso diff --git a/patch/kernel/archive/rockchip-6.11/overlay/rk322x-cpu-hs-lv.dtso b/patch/kernel/archive/rockchip-6.12/overlay/rk322x-cpu-hs-lv.dtso similarity index 100% rename from patch/kernel/archive/rockchip-6.11/overlay/rk322x-cpu-hs-lv.dtso rename to patch/kernel/archive/rockchip-6.12/overlay/rk322x-cpu-hs-lv.dtso diff --git a/patch/kernel/archive/rockchip-6.11/overlay/rk322x-cpu-hs.dtso b/patch/kernel/archive/rockchip-6.12/overlay/rk322x-cpu-hs.dtso similarity index 100% rename from patch/kernel/archive/rockchip-6.11/overlay/rk322x-cpu-hs.dtso rename to patch/kernel/archive/rockchip-6.12/overlay/rk322x-cpu-hs.dtso diff --git a/patch/kernel/archive/rockchip-6.11/overlay/rk322x-cpu-stability.dtso b/patch/kernel/archive/rockchip-6.12/overlay/rk322x-cpu-stability.dtso similarity index 100% rename from patch/kernel/archive/rockchip-6.11/overlay/rk322x-cpu-stability.dtso rename to patch/kernel/archive/rockchip-6.12/overlay/rk322x-cpu-stability.dtso diff --git a/patch/kernel/archive/rockchip-6.11/overlay/rk322x-ddr3-330.dtso b/patch/kernel/archive/rockchip-6.12/overlay/rk322x-ddr3-330.dtso similarity index 100% rename from patch/kernel/archive/rockchip-6.11/overlay/rk322x-ddr3-330.dtso rename to patch/kernel/archive/rockchip-6.12/overlay/rk322x-ddr3-330.dtso diff --git a/patch/kernel/archive/rockchip-6.11/overlay/rk322x-ddr3-528.dtso b/patch/kernel/archive/rockchip-6.12/overlay/rk322x-ddr3-528.dtso similarity index 100% rename from patch/kernel/archive/rockchip-6.11/overlay/rk322x-ddr3-528.dtso rename to patch/kernel/archive/rockchip-6.12/overlay/rk322x-ddr3-528.dtso diff --git a/patch/kernel/archive/rockchip-6.11/overlay/rk322x-ddr3-660.dtso b/patch/kernel/archive/rockchip-6.12/overlay/rk322x-ddr3-660.dtso similarity index 100% rename from patch/kernel/archive/rockchip-6.11/overlay/rk322x-ddr3-660.dtso rename to patch/kernel/archive/rockchip-6.12/overlay/rk322x-ddr3-660.dtso diff --git a/patch/kernel/archive/rockchip-6.11/overlay/rk322x-ddr3-800.dtso b/patch/kernel/archive/rockchip-6.12/overlay/rk322x-ddr3-800.dtso similarity index 100% rename from patch/kernel/archive/rockchip-6.11/overlay/rk322x-ddr3-800.dtso rename to patch/kernel/archive/rockchip-6.12/overlay/rk322x-ddr3-800.dtso diff --git a/patch/kernel/archive/rockchip-6.11/overlay/rk322x-emmc-ddr-ph180.dtso b/patch/kernel/archive/rockchip-6.12/overlay/rk322x-emmc-ddr-ph180.dtso similarity index 100% rename from patch/kernel/archive/rockchip-6.11/overlay/rk322x-emmc-ddr-ph180.dtso rename to patch/kernel/archive/rockchip-6.12/overlay/rk322x-emmc-ddr-ph180.dtso diff --git a/patch/kernel/archive/rockchip-6.11/overlay/rk322x-emmc-ddr-ph45.dtso b/patch/kernel/archive/rockchip-6.12/overlay/rk322x-emmc-ddr-ph45.dtso similarity index 100% rename from patch/kernel/archive/rockchip-6.11/overlay/rk322x-emmc-ddr-ph45.dtso rename to patch/kernel/archive/rockchip-6.12/overlay/rk322x-emmc-ddr-ph45.dtso diff --git a/patch/kernel/archive/rockchip-6.11/overlay/rk322x-emmc-hs200.dtso b/patch/kernel/archive/rockchip-6.12/overlay/rk322x-emmc-hs200.dtso similarity index 100% rename from patch/kernel/archive/rockchip-6.11/overlay/rk322x-emmc-hs200.dtso rename to patch/kernel/archive/rockchip-6.12/overlay/rk322x-emmc-hs200.dtso diff --git a/patch/kernel/archive/rockchip-6.11/overlay/rk322x-emmc-pins.dtso b/patch/kernel/archive/rockchip-6.12/overlay/rk322x-emmc-pins.dtso similarity index 100% rename from patch/kernel/archive/rockchip-6.11/overlay/rk322x-emmc-pins.dtso rename to patch/kernel/archive/rockchip-6.12/overlay/rk322x-emmc-pins.dtso diff --git a/patch/kernel/archive/rockchip-6.11/overlay/rk322x-emmc.dtso b/patch/kernel/archive/rockchip-6.12/overlay/rk322x-emmc.dtso similarity index 100% rename from patch/kernel/archive/rockchip-6.11/overlay/rk322x-emmc.dtso rename to patch/kernel/archive/rockchip-6.12/overlay/rk322x-emmc.dtso diff --git a/patch/kernel/archive/rockchip-6.11/overlay/rk322x-fixup.scr-cmd b/patch/kernel/archive/rockchip-6.12/overlay/rk322x-fixup.scr-cmd similarity index 100% rename from patch/kernel/archive/rockchip-6.11/overlay/rk322x-fixup.scr-cmd rename to patch/kernel/archive/rockchip-6.12/overlay/rk322x-fixup.scr-cmd diff --git a/patch/kernel/archive/rockchip-6.11/overlay/rk322x-ir-wakeup.dtso b/patch/kernel/archive/rockchip-6.12/overlay/rk322x-ir-wakeup.dtso similarity index 100% rename from patch/kernel/archive/rockchip-6.11/overlay/rk322x-ir-wakeup.dtso rename to patch/kernel/archive/rockchip-6.12/overlay/rk322x-ir-wakeup.dtso diff --git a/patch/kernel/archive/rockchip-6.11/overlay/rk322x-led-conf-default.dtso b/patch/kernel/archive/rockchip-6.12/overlay/rk322x-led-conf-default.dtso similarity index 100% rename from patch/kernel/archive/rockchip-6.11/overlay/rk322x-led-conf-default.dtso rename to patch/kernel/archive/rockchip-6.12/overlay/rk322x-led-conf-default.dtso diff --git a/patch/kernel/archive/rockchip-6.11/overlay/rk322x-led-conf1.dtso b/patch/kernel/archive/rockchip-6.12/overlay/rk322x-led-conf1.dtso similarity index 100% rename from patch/kernel/archive/rockchip-6.11/overlay/rk322x-led-conf1.dtso rename to patch/kernel/archive/rockchip-6.12/overlay/rk322x-led-conf1.dtso diff --git a/patch/kernel/archive/rockchip-6.11/overlay/rk322x-led-conf2.dtso b/patch/kernel/archive/rockchip-6.12/overlay/rk322x-led-conf2.dtso similarity index 100% rename from patch/kernel/archive/rockchip-6.11/overlay/rk322x-led-conf2.dtso rename to patch/kernel/archive/rockchip-6.12/overlay/rk322x-led-conf2.dtso diff --git a/patch/kernel/archive/rockchip-6.11/overlay/rk322x-led-conf3.dtso b/patch/kernel/archive/rockchip-6.12/overlay/rk322x-led-conf3.dtso similarity index 100% rename from patch/kernel/archive/rockchip-6.11/overlay/rk322x-led-conf3.dtso rename to patch/kernel/archive/rockchip-6.12/overlay/rk322x-led-conf3.dtso diff --git a/patch/kernel/archive/rockchip-6.11/overlay/rk322x-led-conf4.dtso b/patch/kernel/archive/rockchip-6.12/overlay/rk322x-led-conf4.dtso similarity index 100% rename from patch/kernel/archive/rockchip-6.11/overlay/rk322x-led-conf4.dtso rename to patch/kernel/archive/rockchip-6.12/overlay/rk322x-led-conf4.dtso diff --git a/patch/kernel/archive/rockchip-6.11/overlay/rk322x-led-conf5.dtso b/patch/kernel/archive/rockchip-6.12/overlay/rk322x-led-conf5.dtso similarity index 100% rename from patch/kernel/archive/rockchip-6.11/overlay/rk322x-led-conf5.dtso rename to patch/kernel/archive/rockchip-6.12/overlay/rk322x-led-conf5.dtso diff --git a/patch/kernel/archive/rockchip-6.11/overlay/rk322x-led-conf6.dtso b/patch/kernel/archive/rockchip-6.12/overlay/rk322x-led-conf6.dtso similarity index 100% rename from patch/kernel/archive/rockchip-6.11/overlay/rk322x-led-conf6.dtso rename to patch/kernel/archive/rockchip-6.12/overlay/rk322x-led-conf6.dtso diff --git a/patch/kernel/archive/rockchip-6.11/overlay/rk322x-led-conf7.dtso b/patch/kernel/archive/rockchip-6.12/overlay/rk322x-led-conf7.dtso similarity index 100% rename from patch/kernel/archive/rockchip-6.11/overlay/rk322x-led-conf7.dtso rename to patch/kernel/archive/rockchip-6.12/overlay/rk322x-led-conf7.dtso diff --git a/patch/kernel/archive/rockchip-6.11/overlay/rk322x-led-conf8.dtso b/patch/kernel/archive/rockchip-6.12/overlay/rk322x-led-conf8.dtso similarity index 100% rename from patch/kernel/archive/rockchip-6.11/overlay/rk322x-led-conf8.dtso rename to patch/kernel/archive/rockchip-6.12/overlay/rk322x-led-conf8.dtso diff --git a/patch/kernel/archive/rockchip-6.11/overlay/rk322x-nand.dtso b/patch/kernel/archive/rockchip-6.12/overlay/rk322x-nand.dtso similarity index 100% rename from patch/kernel/archive/rockchip-6.11/overlay/rk322x-nand.dtso rename to patch/kernel/archive/rockchip-6.12/overlay/rk322x-nand.dtso diff --git a/patch/kernel/archive/rockchip-6.11/overlay/rk322x-usb-otg-peripheral.dtso b/patch/kernel/archive/rockchip-6.12/overlay/rk322x-usb-otg-peripheral.dtso similarity index 100% rename from patch/kernel/archive/rockchip-6.11/overlay/rk322x-usb-otg-peripheral.dtso rename to patch/kernel/archive/rockchip-6.12/overlay/rk322x-usb-otg-peripheral.dtso diff --git a/patch/kernel/archive/rockchip-6.11/overlay/rk322x-wlan-alt-wiring.dtso b/patch/kernel/archive/rockchip-6.12/overlay/rk322x-wlan-alt-wiring.dtso similarity index 100% rename from patch/kernel/archive/rockchip-6.11/overlay/rk322x-wlan-alt-wiring.dtso rename to patch/kernel/archive/rockchip-6.12/overlay/rk322x-wlan-alt-wiring.dtso diff --git a/patch/kernel/archive/rockchip-6.11/overlay/rockchip-ds1307.dtbo b/patch/kernel/archive/rockchip-6.12/overlay/rockchip-ds1307.dtbo similarity index 100% rename from patch/kernel/archive/rockchip-6.11/overlay/rockchip-ds1307.dtbo rename to patch/kernel/archive/rockchip-6.12/overlay/rockchip-ds1307.dtbo diff --git a/patch/kernel/archive/rockchip-6.11/overlay/rockchip-ds1307.dtso b/patch/kernel/archive/rockchip-6.12/overlay/rockchip-ds1307.dtso similarity index 100% rename from patch/kernel/archive/rockchip-6.11/overlay/rockchip-ds1307.dtso rename to patch/kernel/archive/rockchip-6.12/overlay/rockchip-ds1307.dtso diff --git a/patch/kernel/archive/rockchip-6.11/overlay/rockchip-fixup.scr-cmd b/patch/kernel/archive/rockchip-6.12/overlay/rockchip-fixup.scr-cmd similarity index 100% rename from patch/kernel/archive/rockchip-6.11/overlay/rockchip-fixup.scr-cmd rename to patch/kernel/archive/rockchip-6.12/overlay/rockchip-fixup.scr-cmd diff --git a/patch/kernel/archive/rockchip-6.11/overlay/rockchip-i2c1.dtbo b/patch/kernel/archive/rockchip-6.12/overlay/rockchip-i2c1.dtbo similarity index 100% rename from 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patch/kernel/archive/rockchip-6.12/overlay/rockchip-i2c4.dtso diff --git a/patch/kernel/archive/rockchip-6.11/overlay/rockchip-pwm1.dtso b/patch/kernel/archive/rockchip-6.12/overlay/rockchip-pwm1.dtso similarity index 100% rename from patch/kernel/archive/rockchip-6.11/overlay/rockchip-pwm1.dtso rename to patch/kernel/archive/rockchip-6.12/overlay/rockchip-pwm1.dtso diff --git a/patch/kernel/archive/rockchip-6.11/overlay/rockchip-pwm2.dtso b/patch/kernel/archive/rockchip-6.12/overlay/rockchip-pwm2.dtso similarity index 100% rename from patch/kernel/archive/rockchip-6.11/overlay/rockchip-pwm2.dtso rename to patch/kernel/archive/rockchip-6.12/overlay/rockchip-pwm2.dtso diff --git a/patch/kernel/archive/rockchip-6.11/overlay/rockchip-pwm3.dtso b/patch/kernel/archive/rockchip-6.12/overlay/rockchip-pwm3.dtso similarity index 100% rename from patch/kernel/archive/rockchip-6.11/overlay/rockchip-pwm3.dtso rename to patch/kernel/archive/rockchip-6.12/overlay/rockchip-pwm3.dtso diff --git a/patch/kernel/archive/rockchip-6.11/overlay/rockchip-spi0.dtbo b/patch/kernel/archive/rockchip-6.12/overlay/rockchip-spi0.dtbo similarity index 100% rename from patch/kernel/archive/rockchip-6.11/overlay/rockchip-spi0.dtbo rename to patch/kernel/archive/rockchip-6.12/overlay/rockchip-spi0.dtbo diff --git a/patch/kernel/archive/rockchip-6.11/overlay/rockchip-spi0.dtso b/patch/kernel/archive/rockchip-6.12/overlay/rockchip-spi0.dtso similarity index 100% rename from patch/kernel/archive/rockchip-6.11/overlay/rockchip-spi0.dtso rename to patch/kernel/archive/rockchip-6.12/overlay/rockchip-spi0.dtso diff --git a/patch/kernel/archive/rockchip-6.11/overlay/rockchip-spi2.dtbo b/patch/kernel/archive/rockchip-6.12/overlay/rockchip-spi2.dtbo similarity index 100% rename from patch/kernel/archive/rockchip-6.11/overlay/rockchip-spi2.dtbo rename to patch/kernel/archive/rockchip-6.12/overlay/rockchip-spi2.dtbo diff --git a/patch/kernel/archive/rockchip-6.11/overlay/rockchip-spi2.dtso b/patch/kernel/archive/rockchip-6.12/overlay/rockchip-spi2.dtso similarity index 100% rename from patch/kernel/archive/rockchip-6.11/overlay/rockchip-spi2.dtso rename to patch/kernel/archive/rockchip-6.12/overlay/rockchip-spi2.dtso diff --git a/patch/kernel/archive/rockchip-6.11/overlay/rockchip-spidev0.dtbo b/patch/kernel/archive/rockchip-6.12/overlay/rockchip-spidev0.dtbo similarity index 100% rename from patch/kernel/archive/rockchip-6.11/overlay/rockchip-spidev0.dtbo rename to patch/kernel/archive/rockchip-6.12/overlay/rockchip-spidev0.dtbo diff --git a/patch/kernel/archive/rockchip-6.11/overlay/rockchip-spidev0.dtso b/patch/kernel/archive/rockchip-6.12/overlay/rockchip-spidev0.dtso similarity index 100% rename from patch/kernel/archive/rockchip-6.11/overlay/rockchip-spidev0.dtso rename to patch/kernel/archive/rockchip-6.12/overlay/rockchip-spidev0.dtso diff --git a/patch/kernel/archive/rockchip-6.11/overlay/rockchip-spidev2.dtbo b/patch/kernel/archive/rockchip-6.12/overlay/rockchip-spidev2.dtbo similarity index 100% rename from patch/kernel/archive/rockchip-6.11/overlay/rockchip-spidev2.dtbo rename to patch/kernel/archive/rockchip-6.12/overlay/rockchip-spidev2.dtbo diff --git a/patch/kernel/archive/rockchip-6.11/overlay/rockchip-spidev2.dtso b/patch/kernel/archive/rockchip-6.12/overlay/rockchip-spidev2.dtso similarity index 100% rename from patch/kernel/archive/rockchip-6.11/overlay/rockchip-spidev2.dtso rename to patch/kernel/archive/rockchip-6.12/overlay/rockchip-spidev2.dtso diff --git a/patch/kernel/archive/rockchip-6.11/overlay/rockchip-uart1.dtbo b/patch/kernel/archive/rockchip-6.12/overlay/rockchip-uart1.dtbo similarity index 100% rename from patch/kernel/archive/rockchip-6.11/overlay/rockchip-uart1.dtbo rename to patch/kernel/archive/rockchip-6.12/overlay/rockchip-uart1.dtbo diff --git a/patch/kernel/archive/rockchip-6.11/overlay/rockchip-uart1.dtso b/patch/kernel/archive/rockchip-6.12/overlay/rockchip-uart1.dtso similarity index 100% rename from patch/kernel/archive/rockchip-6.11/overlay/rockchip-uart1.dtso rename to patch/kernel/archive/rockchip-6.12/overlay/rockchip-uart1.dtso diff --git a/patch/kernel/archive/rockchip-6.11/overlay/rockchip-uart2.dtbo b/patch/kernel/archive/rockchip-6.12/overlay/rockchip-uart2.dtbo similarity index 100% rename from patch/kernel/archive/rockchip-6.11/overlay/rockchip-uart2.dtbo rename to patch/kernel/archive/rockchip-6.12/overlay/rockchip-uart2.dtbo diff --git a/patch/kernel/archive/rockchip-6.11/overlay/rockchip-uart2.dtso b/patch/kernel/archive/rockchip-6.12/overlay/rockchip-uart2.dtso similarity index 100% rename from patch/kernel/archive/rockchip-6.11/overlay/rockchip-uart2.dtso rename to patch/kernel/archive/rockchip-6.12/overlay/rockchip-uart2.dtso diff --git a/patch/kernel/archive/rockchip-6.11/overlay/rockchip-uart3.dtbo b/patch/kernel/archive/rockchip-6.12/overlay/rockchip-uart3.dtbo similarity index 100% rename from patch/kernel/archive/rockchip-6.11/overlay/rockchip-uart3.dtbo rename to patch/kernel/archive/rockchip-6.12/overlay/rockchip-uart3.dtbo diff --git a/patch/kernel/archive/rockchip-6.11/overlay/rockchip-uart3.dtso b/patch/kernel/archive/rockchip-6.12/overlay/rockchip-uart3.dtso similarity index 100% rename from patch/kernel/archive/rockchip-6.11/overlay/rockchip-uart3.dtso rename to patch/kernel/archive/rockchip-6.12/overlay/rockchip-uart3.dtso diff --git a/patch/kernel/archive/rockchip-6.11/overlay/rockchip-uart4.dtbo b/patch/kernel/archive/rockchip-6.12/overlay/rockchip-uart4.dtbo similarity index 100% rename from patch/kernel/archive/rockchip-6.11/overlay/rockchip-uart4.dtbo rename to patch/kernel/archive/rockchip-6.12/overlay/rockchip-uart4.dtbo diff --git a/patch/kernel/archive/rockchip-6.11/overlay/rockchip-uart4.dtso b/patch/kernel/archive/rockchip-6.12/overlay/rockchip-uart4.dtso similarity index 100% rename from patch/kernel/archive/rockchip-6.11/overlay/rockchip-uart4.dtso rename to patch/kernel/archive/rockchip-6.12/overlay/rockchip-uart4.dtso diff --git a/patch/kernel/archive/rockchip-6.11/overlay/rockchip-w1-gpio.dtbo b/patch/kernel/archive/rockchip-6.12/overlay/rockchip-w1-gpio.dtbo similarity index 100% rename from patch/kernel/archive/rockchip-6.11/overlay/rockchip-w1-gpio.dtbo rename to patch/kernel/archive/rockchip-6.12/overlay/rockchip-w1-gpio.dtbo diff --git a/patch/kernel/archive/rockchip-6.11/overlay/rockchip-w1-gpio.dtso b/patch/kernel/archive/rockchip-6.12/overlay/rockchip-w1-gpio.dtso similarity index 100% rename from patch/kernel/archive/rockchip-6.11/overlay/rockchip-w1-gpio.dtso rename to patch/kernel/archive/rockchip-6.12/overlay/rockchip-w1-gpio.dtso diff --git a/patch/kernel/archive/rockchip-6.11/patches.armbian/bt-broadcom-serdev-workaround.patch b/patch/kernel/archive/rockchip-6.12/patches.armbian/bt-broadcom-serdev-workaround.patch similarity index 100% rename from patch/kernel/archive/rockchip-6.11/patches.armbian/bt-broadcom-serdev-workaround.patch rename to patch/kernel/archive/rockchip-6.12/patches.armbian/bt-broadcom-serdev-workaround.patch diff --git a/patch/kernel/archive/rockchip-6.11/patches.armbian/clk-rk322x-composite-mmc-clk.patch b/patch/kernel/archive/rockchip-6.12/patches.armbian/clk-rk322x-composite-mmc-clk.patch similarity index 100% rename from patch/kernel/archive/rockchip-6.11/patches.armbian/clk-rk322x-composite-mmc-clk.patch rename to patch/kernel/archive/rockchip-6.12/patches.armbian/clk-rk322x-composite-mmc-clk.patch diff --git a/patch/kernel/archive/rockchip-6.11/patches.armbian/clk-rockchip-max-frac-divider.patch b/patch/kernel/archive/rockchip-6.12/patches.armbian/clk-rockchip-max-frac-divider.patch similarity index 100% rename from patch/kernel/archive/rockchip-6.11/patches.armbian/clk-rockchip-max-frac-divider.patch rename to patch/kernel/archive/rockchip-6.12/patches.armbian/clk-rockchip-max-frac-divider.patch diff --git a/patch/kernel/archive/rockchip-6.11/patches.armbian/driver-rk322x-audio-codec.patch b/patch/kernel/archive/rockchip-6.12/patches.armbian/driver-rk322x-audio-codec.patch similarity index 100% rename from patch/kernel/archive/rockchip-6.11/patches.armbian/driver-rk322x-audio-codec.patch rename to patch/kernel/archive/rockchip-6.12/patches.armbian/driver-rk322x-audio-codec.patch diff --git a/patch/kernel/archive/rockchip-6.11/patches.armbian/driver-rk3288-gpiomem.patch b/patch/kernel/archive/rockchip-6.12/patches.armbian/driver-rk3288-gpiomem.patch similarity index 100% rename from patch/kernel/archive/rockchip-6.11/patches.armbian/driver-rk3288-gpiomem.patch rename to patch/kernel/archive/rockchip-6.12/patches.armbian/driver-rk3288-gpiomem.patch diff --git a/patch/kernel/archive/rockchip-6.11/patches.armbian/driver-tinkerboard-alc4040-codec.patch b/patch/kernel/archive/rockchip-6.12/patches.armbian/driver-tinkerboard-alc4040-codec.patch similarity index 100% rename from patch/kernel/archive/rockchip-6.11/patches.armbian/driver-tinkerboard-alc4040-codec.patch rename to patch/kernel/archive/rockchip-6.12/patches.armbian/driver-tinkerboard-alc4040-codec.patch diff --git a/patch/kernel/archive/rockchip-6.11/patches.armbian/drm-rk322x-plane-overlay.patch b/patch/kernel/archive/rockchip-6.12/patches.armbian/drm-rk322x-plane-overlay.patch similarity index 100% rename from patch/kernel/archive/rockchip-6.11/patches.armbian/drm-rk322x-plane-overlay.patch rename to patch/kernel/archive/rockchip-6.12/patches.armbian/drm-rk322x-plane-overlay.patch diff --git a/patch/kernel/archive/rockchip-6.11/patches.armbian/drm-rk322x-yuv-10bit-modes.patch b/patch/kernel/archive/rockchip-6.12/patches.armbian/drm-rk322x-yuv-10bit-modes.patch similarity index 100% rename from patch/kernel/archive/rockchip-6.11/patches.armbian/drm-rk322x-yuv-10bit-modes.patch rename to patch/kernel/archive/rockchip-6.12/patches.armbian/drm-rk322x-yuv-10bit-modes.patch diff --git a/patch/kernel/archive/rockchip-6.11/patches.armbian/drm-rockchip-hardware-cursor.patch b/patch/kernel/archive/rockchip-6.12/patches.armbian/drm-rockchip-hardware-cursor.patch similarity index 95% rename from patch/kernel/archive/rockchip-6.11/patches.armbian/drm-rockchip-hardware-cursor.patch rename to patch/kernel/archive/rockchip-6.12/patches.armbian/drm-rockchip-hardware-cursor.patch index 863a70aaa42e..0c4abae7c7b1 100644 --- a/patch/kernel/archive/rockchip-6.11/patches.armbian/drm-rockchip-hardware-cursor.patch +++ b/patch/kernel/archive/rockchip-6.12/patches.armbian/drm-rockchip-hardware-cursor.patch @@ -13,7 +13,7 @@ diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c b/drivers/gpu/drm/rockc index 83a926c0a..b0832320e 100644 --- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c +++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c -@@ -1160,6 +1160,207 @@ static void vop_plane_atomic_async_update(struct drm_plane *plane, +@@ -1160,6 +1160,197 @@ static void vop_plane_atomic_async_update(struct drm_plane *plane, } } @@ -28,10 +28,8 @@ index 83a926c0a..b0832320e 100644 + const struct vop_win_data *win = vop_win->data; + struct vop *vop = to_vop(new_state->crtc); + struct drm_framebuffer *fb = new_state->fb; -+ unsigned int actual_w, actual_h; + unsigned int dsp_stx, dsp_sty; + uint32_t dsp_st; -+ struct drm_rect *src = &new_state->src; + struct drm_rect *dest = &new_state->dst; + struct drm_gem_object *obj; + struct rockchip_gem_object *rk_obj; @@ -58,8 +56,6 @@ index 83a926c0a..b0832320e 100644 + obj = fb->obj[0]; + rk_obj = to_rockchip_obj(obj); + -+// actual_w = drm_rect_width(src) >> 16; -+// actual_h = drm_rect_height(src) >> 16; + + dsp_stx = dest->x1 + crtc->mode.htotal - crtc->mode.hsync_start; + dsp_sty = dest->y1 + crtc->mode.vtotal - crtc->mode.vsync_start; @@ -71,8 +67,6 @@ index 83a926c0a..b0832320e 100644 + * For y-mirroring we need to move address + * to the beginning of the last line. + */ -+// if (new_state->rotation & DRM_MODE_REFLECT_Y) -+// dma_addr += (actual_h - 1) * fb->pitches[0]; + + spin_lock(&vop->reg_lock); + @@ -82,10 +76,6 @@ index 83a926c0a..b0832320e 100644 + + VOP_WIN_SET(vop, win, format, format); + -+// if (win->phy->scl) -+// scl_vop_cal_scl_fac(vop, win, actual_w, actual_h, -+// drm_rect_width(dest), drm_rect_height(dest), -+// fb->format); + + rb_swap = has_rb_swapped(vop->data->version, fb->format->format); + VOP_WIN_SET(vop, win, rb_swap, rb_swap); diff --git a/patch/kernel/archive/rockchip-6.11/patches.armbian/dts-miqi-fan.patch b/patch/kernel/archive/rockchip-6.12/patches.armbian/dts-miqi-fan.patch similarity index 100% rename from patch/kernel/archive/rockchip-6.11/patches.armbian/dts-miqi-fan.patch rename to patch/kernel/archive/rockchip-6.12/patches.armbian/dts-miqi-fan.patch diff --git a/patch/kernel/archive/rockchip-6.11/patches.armbian/dts-miqi-hevc-rga.patch b/patch/kernel/archive/rockchip-6.12/patches.armbian/dts-miqi-hevc-rga.patch similarity index 100% rename from patch/kernel/archive/rockchip-6.11/patches.armbian/dts-miqi-hevc-rga.patch rename to patch/kernel/archive/rockchip-6.12/patches.armbian/dts-miqi-hevc-rga.patch diff --git a/patch/kernel/archive/rockchip-6.11/patches.armbian/dts-miqi-mali-gpu.patch b/patch/kernel/archive/rockchip-6.12/patches.armbian/dts-miqi-mali-gpu.patch similarity index 100% rename from patch/kernel/archive/rockchip-6.11/patches.armbian/dts-miqi-mali-gpu.patch rename to patch/kernel/archive/rockchip-6.12/patches.armbian/dts-miqi-mali-gpu.patch diff --git a/patch/kernel/archive/rockchip-6.11/patches.armbian/dts-miqi-regulator-fix.patch b/patch/kernel/archive/rockchip-6.12/patches.armbian/dts-miqi-regulator-fix.patch similarity index 100% rename from patch/kernel/archive/rockchip-6.11/patches.armbian/dts-miqi-regulator-fix.patch rename to patch/kernel/archive/rockchip-6.12/patches.armbian/dts-miqi-regulator-fix.patch diff --git a/patch/kernel/archive/rockchip-6.11/patches.armbian/dts-rk322x-iep-node.patch b/patch/kernel/archive/rockchip-6.12/patches.armbian/dts-rk322x-iep-node.patch similarity index 100% rename from patch/kernel/archive/rockchip-6.11/patches.armbian/dts-rk322x-iep-node.patch rename to patch/kernel/archive/rockchip-6.12/patches.armbian/dts-rk322x-iep-node.patch diff --git a/patch/kernel/archive/rockchip-6.11/patches.armbian/dts-rk322x-pinctrl-nand.patch b/patch/kernel/archive/rockchip-6.12/patches.armbian/dts-rk322x-pinctrl-nand.patch similarity index 100% rename from patch/kernel/archive/rockchip-6.11/patches.armbian/dts-rk322x-pinctrl-nand.patch rename to patch/kernel/archive/rockchip-6.12/patches.armbian/dts-rk322x-pinctrl-nand.patch diff --git a/patch/kernel/archive/rockchip-6.11/patches.armbian/dts-rk3288-disable-serial-dma.patch b/patch/kernel/archive/rockchip-6.12/patches.armbian/dts-rk3288-disable-serial-dma.patch similarity index 100% rename from patch/kernel/archive/rockchip-6.11/patches.armbian/dts-rk3288-disable-serial-dma.patch rename to patch/kernel/archive/rockchip-6.12/patches.armbian/dts-rk3288-disable-serial-dma.patch diff --git a/patch/kernel/archive/rockchip-6.11/patches.armbian/dts-rk3288-fix-mmc-aliases.patch b/patch/kernel/archive/rockchip-6.12/patches.armbian/dts-rk3288-fix-mmc-aliases.patch similarity index 100% rename from patch/kernel/archive/rockchip-6.11/patches.armbian/dts-rk3288-fix-mmc-aliases.patch rename to patch/kernel/archive/rockchip-6.12/patches.armbian/dts-rk3288-fix-mmc-aliases.patch diff --git a/patch/kernel/archive/rockchip-6.11/patches.armbian/dts-rk3288-gpu-500mhz-opp.patch b/patch/kernel/archive/rockchip-6.12/patches.armbian/dts-rk3288-gpu-500mhz-opp.patch similarity index 100% rename from patch/kernel/archive/rockchip-6.11/patches.armbian/dts-rk3288-gpu-500mhz-opp.patch rename to patch/kernel/archive/rockchip-6.12/patches.armbian/dts-rk3288-gpu-500mhz-opp.patch diff --git a/patch/kernel/archive/rockchip-6.11/patches.armbian/dts-rk3288-pinctrl-spi2.patch b/patch/kernel/archive/rockchip-6.12/patches.armbian/dts-rk3288-pinctrl-spi2.patch similarity index 100% rename from patch/kernel/archive/rockchip-6.11/patches.armbian/dts-rk3288-pinctrl-spi2.patch rename to patch/kernel/archive/rockchip-6.12/patches.armbian/dts-rk3288-pinctrl-spi2.patch diff --git a/patch/kernel/archive/rockchip-6.11/patches.armbian/dts-rk3288-thermal-rearrange-zones.patch b/patch/kernel/archive/rockchip-6.12/patches.armbian/dts-rk3288-thermal-rearrange-zones.patch similarity index 100% rename from patch/kernel/archive/rockchip-6.11/patches.armbian/dts-rk3288-thermal-rearrange-zones.patch rename to patch/kernel/archive/rockchip-6.12/patches.armbian/dts-rk3288-thermal-rearrange-zones.patch diff --git a/patch/kernel/archive/rockchip-6.11/patches.armbian/dts-tinkerboard-bt-rtl8723bs.patch b/patch/kernel/archive/rockchip-6.12/patches.armbian/dts-tinkerboard-bt-rtl8723bs.patch similarity index 100% rename from patch/kernel/archive/rockchip-6.11/patches.armbian/dts-tinkerboard-bt-rtl8723bs.patch rename to patch/kernel/archive/rockchip-6.12/patches.armbian/dts-tinkerboard-bt-rtl8723bs.patch diff --git a/patch/kernel/archive/rockchip-6.11/patches.armbian/dts-tinkerboard-bt-uart-pins.patch b/patch/kernel/archive/rockchip-6.12/patches.armbian/dts-tinkerboard-bt-uart-pins.patch similarity index 100% rename from patch/kernel/archive/rockchip-6.11/patches.armbian/dts-tinkerboard-bt-uart-pins.patch rename to patch/kernel/archive/rockchip-6.12/patches.armbian/dts-tinkerboard-bt-uart-pins.patch diff --git a/patch/kernel/archive/rockchip-6.11/patches.armbian/dts-tinkerboard-hevc-rga.patch b/patch/kernel/archive/rockchip-6.12/patches.armbian/dts-tinkerboard-hevc-rga.patch similarity index 100% rename from patch/kernel/archive/rockchip-6.11/patches.armbian/dts-tinkerboard-hevc-rga.patch rename to patch/kernel/archive/rockchip-6.12/patches.armbian/dts-tinkerboard-hevc-rga.patch diff --git a/patch/kernel/archive/rockchip-6.11/patches.armbian/dts-tinkerboard-sdio-wifi.patch b/patch/kernel/archive/rockchip-6.12/patches.armbian/dts-tinkerboard-sdio-wifi.patch similarity index 100% rename from patch/kernel/archive/rockchip-6.11/patches.armbian/dts-tinkerboard-sdio-wifi.patch rename to patch/kernel/archive/rockchip-6.12/patches.armbian/dts-tinkerboard-sdio-wifi.patch diff --git a/patch/kernel/archive/rockchip-6.11/patches.armbian/dts-tinkerboard-sdmmc-properties.patch b/patch/kernel/archive/rockchip-6.12/patches.armbian/dts-tinkerboard-sdmmc-properties.patch similarity index 100% rename from patch/kernel/archive/rockchip-6.11/patches.armbian/dts-tinkerboard-sdmmc-properties.patch rename to patch/kernel/archive/rockchip-6.12/patches.armbian/dts-tinkerboard-sdmmc-properties.patch diff --git a/patch/kernel/archive/rockchip-6.11/patches.armbian/dts-tinkerboard-spi-interface.patch b/patch/kernel/archive/rockchip-6.12/patches.armbian/dts-tinkerboard-spi-interface.patch similarity index 100% rename from patch/kernel/archive/rockchip-6.11/patches.armbian/dts-tinkerboard-spi-interface.patch rename to patch/kernel/archive/rockchip-6.12/patches.armbian/dts-tinkerboard-spi-interface.patch diff --git a/patch/kernel/archive/rockchip-6.11/patches.armbian/dts-veyron-flag-cache-flush.patch b/patch/kernel/archive/rockchip-6.12/patches.armbian/dts-veyron-flag-cache-flush.patch similarity index 100% rename from patch/kernel/archive/rockchip-6.11/patches.armbian/dts-veyron-flag-cache-flush.patch rename to patch/kernel/archive/rockchip-6.12/patches.armbian/dts-veyron-flag-cache-flush.patch diff --git a/patch/kernel/archive/rockchip-6.11/patches.armbian/general-add-overlay-compilation-support.patch b/patch/kernel/archive/rockchip-6.12/patches.armbian/general-add-overlay-compilation-support.patch similarity index 54% rename from patch/kernel/archive/rockchip-6.11/patches.armbian/general-add-overlay-compilation-support.patch rename to patch/kernel/archive/rockchip-6.12/patches.armbian/general-add-overlay-compilation-support.patch index a5a375ee1f6e..267fd37eb3de 100644 --- a/patch/kernel/archive/rockchip-6.11/patches.armbian/general-add-overlay-compilation-support.patch +++ b/patch/kernel/archive/rockchip-6.12/patches.armbian/general-add-overlay-compilation-support.patch @@ -1,15 +1,15 @@ -From a8f9689004d59f0a454ce8cb06bf1556971c1bad Mon Sep 17 00:00:00 2001 +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 From: Paolo Sabatino -Date: Sat, 20 Jul 2024 13:58:49 +0200 -Subject: [PATCH] compile .scr and install overlays in right path +Date: Wed, 2 Oct 2024 19:30:34 +0300 +Subject: compile .scr and install overlays in right path --- - scripts/Makefile.dtbinst | 13 ++++++++++++- - scripts/Makefile.lib | 8 +++++++- + scripts/Makefile.dtbinst | 13 +++++++++- + scripts/Makefile.dtbs | 8 +++++- 2 files changed, 19 insertions(+), 2 deletions(-) diff --git a/scripts/Makefile.dtbinst b/scripts/Makefile.dtbinst -index 9d920419a62c..9144a1b7c909 100644 +index 111111111111..222222222222 100644 --- a/scripts/Makefile.dtbinst +++ b/scripts/Makefile.dtbinst @@ -33,7 +33,18 @@ endef @@ -32,33 +32,35 @@ index 9d920419a62c..9144a1b7c909 100644 endif # CONFIG_ARCH_WANT_FLAT_DTB_INSTALL -diff --git a/scripts/Makefile.lib b/scripts/Makefile.lib -index 207325eaf1d1..587588518095 100644 ---- a/scripts/Makefile.lib -+++ b/scripts/Makefile.lib -@@ -394,18 +394,24 @@ quiet_cmd_wrap_S_dtb = WRAP $@ - echo '.balign STRUCT_ALIGNMENT'; \ - } > $@ +diff --git a/scripts/Makefile.dtbs b/scripts/Makefile.dtbs +index 111111111111..222222222222 100644 +--- a/scripts/Makefile.dtbs ++++ b/scripts/Makefile.dtbs +@@ -122,17 +122,23 @@ dtc-tmp = $(subst $(comma),_,$(dot-target).dts.tmp) + quiet_cmd_dtc = DTC $(quiet_dtb_check_tag) $@ + cmd_dtc = \ + $(HOSTCC) -E $(dtc_cpp_flags) -x assembler-with-cpp -o $(dtc-tmp) $< ; \ +- $(DTC) -o $@ -b 0 $(addprefix -i,$(dir $<) $(DTC_INCLUDE)) \ ++ $(DTC) -@ -o $@ -b 0 $(addprefix -i,$(dir $<) $(DTC_INCLUDE)) \ + $(DTC_FLAGS) -d $(depfile).dtc.tmp $(dtc-tmp) ; \ + cat $(depfile).pre.tmp $(depfile).dtc.tmp > $(depfile) \ + $(cmd_dtb_check) +quiet_cmd_scr = MKIMAGE $@ +cmd_scr = mkimage -C none -A $(ARCH) -T script -d $< $@ + - $(obj)/%.dtb.S: $(obj)/%.dtb FORCE - $(call if_changed,wrap_S_dtb) + $(obj)/%.dtb: $(obj)/%.dts $(DTC) $(DT_TMP_SCHEMA) FORCE + $(call if_changed_dep,dtc) - $(obj)/%.dtbo.S: $(obj)/%.dtbo FORCE - $(call if_changed,wrap_S_dtb) + $(obj)/%.dtbo: $(src)/%.dtso $(DTC) FORCE + $(call if_changed_dep,dtc) +$(obj)/%.scr: $(src)/%.scr-cmd FORCE + $(call if_changed,scr) + - quiet_dtb_check_tag = $(if $(dtb-check-enabled),[C], ) - cmd_dtb_check = $(if $(dtb-check-enabled),; $(DT_CHECKER) $(DT_CHECKER_FLAGS) -u $(srctree)/$(DT_BINDING_DIR) -p $(DT_TMP_SCHEMA) $@ || true) + # targets + # --------------------------------------------------------------------------- - quiet_cmd_dtc = DTC $(quiet_dtb_check_tag) $@ - cmd_dtc = $(HOSTCC) -E $(dtc_cpp_flags) -x assembler-with-cpp -o $(dtc-tmp) $< ; \ -- $(DTC) -o $@ -b 0 \ -+ $(DTC) -@ -o $@ -b 0 \ - $(addprefix -i,$(dir $<) $(DTC_INCLUDE)) $(DTC_FLAGS) \ - -d $(depfile).dtc.tmp $(dtc-tmp) ; \ - cat $(depfile).pre.tmp $(depfile).dtc.tmp > $(depfile) \ +-- +Armbian + diff --git a/patch/kernel/archive/rockchip-6.11/patches.armbian/general-add-overlay-configfs.patch b/patch/kernel/archive/rockchip-6.12/patches.armbian/general-add-overlay-configfs.patch similarity index 100% rename from patch/kernel/archive/rockchip-6.11/patches.armbian/general-add-overlay-configfs.patch rename to patch/kernel/archive/rockchip-6.12/patches.armbian/general-add-overlay-configfs.patch diff --git a/patch/kernel/archive/rockchip-6.11/patches.armbian/general-add-restart-handler-for-act8846.patch b/patch/kernel/archive/rockchip-6.12/patches.armbian/general-add-restart-handler-for-act8846.patch similarity index 100% rename from patch/kernel/archive/rockchip-6.11/patches.armbian/general-add-restart-handler-for-act8846.patch rename to patch/kernel/archive/rockchip-6.12/patches.armbian/general-add-restart-handler-for-act8846.patch diff --git a/patch/kernel/archive/rockchip-6.11/patches.armbian/general-dwc2-fix-wait-peripheral.patch b/patch/kernel/archive/rockchip-6.12/patches.armbian/general-dwc2-fix-wait-peripheral.patch similarity index 100% rename from patch/kernel/archive/rockchip-6.11/patches.armbian/general-dwc2-fix-wait-peripheral.patch rename to patch/kernel/archive/rockchip-6.12/patches.armbian/general-dwc2-fix-wait-peripheral.patch diff --git a/patch/kernel/archive/rockchip-6.11/patches.armbian/general-dwc2-fix-wait-time.patch b/patch/kernel/archive/rockchip-6.12/patches.armbian/general-dwc2-fix-wait-time.patch similarity index 100% rename from patch/kernel/archive/rockchip-6.11/patches.armbian/general-dwc2-fix-wait-time.patch rename to patch/kernel/archive/rockchip-6.12/patches.armbian/general-dwc2-fix-wait-time.patch diff --git a/patch/kernel/archive/rockchip-6.11/patches.armbian/general-dwc2-nak-gadget.patch b/patch/kernel/archive/rockchip-6.12/patches.armbian/general-dwc2-nak-gadget.patch similarity index 100% rename from patch/kernel/archive/rockchip-6.11/patches.armbian/general-dwc2-nak-gadget.patch rename to patch/kernel/archive/rockchip-6.12/patches.armbian/general-dwc2-nak-gadget.patch diff --git a/patch/kernel/archive/rockchip-6.11/patches.armbian/general-fix-reboot-from-kwiboo.patch b/patch/kernel/archive/rockchip-6.12/patches.armbian/general-fix-reboot-from-kwiboo.patch similarity index 100% rename from patch/kernel/archive/rockchip-6.11/patches.armbian/general-fix-reboot-from-kwiboo.patch rename to patch/kernel/archive/rockchip-6.12/patches.armbian/general-fix-reboot-from-kwiboo.patch diff --git a/patch/kernel/archive/rockchip-6.11/patches.armbian/general-linux-export-mm-trace-rss-stats.patch b/patch/kernel/archive/rockchip-6.12/patches.armbian/general-linux-export-mm-trace-rss-stats.patch similarity index 100% rename from patch/kernel/archive/rockchip-6.11/patches.armbian/general-linux-export-mm-trace-rss-stats.patch rename to patch/kernel/archive/rockchip-6.12/patches.armbian/general-linux-export-mm-trace-rss-stats.patch diff --git a/patch/kernel/archive/rockchip-6.11/patches.armbian/general-rk322x-gpio-ir-driver.patch b/patch/kernel/archive/rockchip-6.12/patches.armbian/general-rk322x-gpio-ir-driver.patch similarity index 100% rename from patch/kernel/archive/rockchip-6.11/patches.armbian/general-rk322x-gpio-ir-driver.patch rename to patch/kernel/archive/rockchip-6.12/patches.armbian/general-rk322x-gpio-ir-driver.patch diff --git a/patch/kernel/archive/rockchip-6.11/patches.armbian/general-rockchip-various-fixes.patch b/patch/kernel/archive/rockchip-6.12/patches.armbian/general-rockchip-various-fixes.patch similarity index 100% rename from patch/kernel/archive/rockchip-6.11/patches.armbian/general-rockchip-various-fixes.patch rename to patch/kernel/archive/rockchip-6.12/patches.armbian/general-rockchip-various-fixes.patch diff --git a/patch/kernel/archive/rockchip-6.11/patches.armbian/ir-keymap-rk322x-box.patch b/patch/kernel/archive/rockchip-6.12/patches.armbian/ir-keymap-rk322x-box.patch similarity index 100% rename from patch/kernel/archive/rockchip-6.11/patches.armbian/ir-keymap-rk322x-box.patch rename to patch/kernel/archive/rockchip-6.12/patches.armbian/ir-keymap-rk322x-box.patch diff --git a/patch/kernel/archive/rockchip-6.11/patches.armbian/ir-keymap-xt-q8l-v10.patch b/patch/kernel/archive/rockchip-6.12/patches.armbian/ir-keymap-xt-q8l-v10.patch similarity index 100% rename from patch/kernel/archive/rockchip-6.11/patches.armbian/ir-keymap-xt-q8l-v10.patch rename to patch/kernel/archive/rockchip-6.12/patches.armbian/ir-keymap-xt-q8l-v10.patch diff --git a/patch/kernel/archive/rockchip-6.11/patches.armbian/misc-tinkerboard-spi-interface.patch b/patch/kernel/archive/rockchip-6.12/patches.armbian/misc-tinkerboard-spi-interface.patch similarity index 100% rename from patch/kernel/archive/rockchip-6.11/patches.armbian/misc-tinkerboard-spi-interface.patch rename to patch/kernel/archive/rockchip-6.12/patches.armbian/misc-tinkerboard-spi-interface.patch diff --git a/patch/kernel/archive/rockchip-6.11/patches.armbian/mmc-tinkerboard-sdmmc-reboot-fix.patch b/patch/kernel/archive/rockchip-6.12/patches.armbian/mmc-tinkerboard-sdmmc-reboot-fix.patch similarity index 100% rename from patch/kernel/archive/rockchip-6.11/patches.armbian/mmc-tinkerboard-sdmmc-reboot-fix.patch rename to patch/kernel/archive/rockchip-6.12/patches.armbian/mmc-tinkerboard-sdmmc-reboot-fix.patch diff --git a/patch/kernel/archive/rockchip-6.11/patches.armbian/rk322x-dmc-driver-01-sipv2-calls.patch b/patch/kernel/archive/rockchip-6.12/patches.armbian/rk322x-dmc-driver-01-sipv2-calls.patch similarity index 100% rename from patch/kernel/archive/rockchip-6.11/patches.armbian/rk322x-dmc-driver-01-sipv2-calls.patch rename to patch/kernel/archive/rockchip-6.12/patches.armbian/rk322x-dmc-driver-01-sipv2-calls.patch diff --git a/patch/kernel/archive/rockchip-6.11/patches.armbian/rk322x-dmc-driver-02-sip-constants.patch b/patch/kernel/archive/rockchip-6.12/patches.armbian/rk322x-dmc-driver-02-sip-constants.patch similarity index 100% rename from patch/kernel/archive/rockchip-6.11/patches.armbian/rk322x-dmc-driver-02-sip-constants.patch rename to patch/kernel/archive/rockchip-6.12/patches.armbian/rk322x-dmc-driver-02-sip-constants.patch diff --git a/patch/kernel/archive/rockchip-6.11/patches.armbian/rk322x-dmc-driver-03-dfi-driver.patch b/patch/kernel/archive/rockchip-6.12/patches.armbian/rk322x-dmc-driver-03-dfi-driver.patch similarity index 100% rename from patch/kernel/archive/rockchip-6.11/patches.armbian/rk322x-dmc-driver-03-dfi-driver.patch rename to patch/kernel/archive/rockchip-6.12/patches.armbian/rk322x-dmc-driver-03-dfi-driver.patch diff --git a/patch/kernel/archive/rockchip-6.11/patches.armbian/rk322x-dmc-driver-04-driver.patch b/patch/kernel/archive/rockchip-6.12/patches.armbian/rk322x-dmc-driver-04-driver.patch similarity index 100% rename from patch/kernel/archive/rockchip-6.11/patches.armbian/rk322x-dmc-driver-04-driver.patch rename to patch/kernel/archive/rockchip-6.12/patches.armbian/rk322x-dmc-driver-04-driver.patch diff --git a/patch/kernel/archive/rockchip-6.11/patches.armbian/rk322x-dwc2-no-clock-gating.patch b/patch/kernel/archive/rockchip-6.12/patches.armbian/rk322x-dwc2-no-clock-gating.patch similarity index 100% rename from patch/kernel/archive/rockchip-6.11/patches.armbian/rk322x-dwc2-no-clock-gating.patch rename to patch/kernel/archive/rockchip-6.12/patches.armbian/rk322x-dwc2-no-clock-gating.patch diff --git a/patch/kernel/archive/rockchip-6.11/patches.armbian/rk322x-usb-reset-props.patch b/patch/kernel/archive/rockchip-6.12/patches.armbian/rk322x-usb-reset-props.patch similarity index 100% rename from patch/kernel/archive/rockchip-6.11/patches.armbian/rk322x-usb-reset-props.patch rename to patch/kernel/archive/rockchip-6.12/patches.armbian/rk322x-usb-reset-props.patch diff --git a/patch/kernel/archive/rockchip-6.11/patches.armbian/wifi-ath9k-no-bulk-EP3-EP4.patch b/patch/kernel/archive/rockchip-6.12/patches.armbian/wifi-ath9k-no-bulk-EP3-EP4.patch similarity index 100% rename from patch/kernel/archive/rockchip-6.11/patches.armbian/wifi-ath9k-no-bulk-EP3-EP4.patch rename to patch/kernel/archive/rockchip-6.12/patches.armbian/wifi-ath9k-no-bulk-EP3-EP4.patch diff --git a/patch/kernel/archive/rockchip-6.11/patches.armbian/wifi-brcmfmac-add-bcm43342.patch b/patch/kernel/archive/rockchip-6.12/patches.armbian/wifi-brcmfmac-add-bcm43342.patch similarity index 100% rename from patch/kernel/archive/rockchip-6.11/patches.armbian/wifi-brcmfmac-add-bcm43342.patch rename to patch/kernel/archive/rockchip-6.12/patches.armbian/wifi-brcmfmac-add-bcm43342.patch diff --git a/patch/kernel/archive/rockchip-6.11/patches.armbian/wifi-brcmfmac-ap6330-firmware.patch b/patch/kernel/archive/rockchip-6.12/patches.armbian/wifi-brcmfmac-ap6330-firmware.patch similarity index 100% rename from patch/kernel/archive/rockchip-6.11/patches.armbian/wifi-brcmfmac-ap6330-firmware.patch rename to patch/kernel/archive/rockchip-6.12/patches.armbian/wifi-brcmfmac-ap6330-firmware.patch diff --git a/patch/kernel/archive/rockchip-6.11/patches.armbian/wifi-driver-esp8089.patch b/patch/kernel/archive/rockchip-6.12/patches.armbian/wifi-driver-esp8089.patch similarity index 99% rename from patch/kernel/archive/rockchip-6.11/patches.armbian/wifi-driver-esp8089.patch rename to patch/kernel/archive/rockchip-6.12/patches.armbian/wifi-driver-esp8089.patch index 4dc64bfd7984..727afc1b843e 100644 --- a/patch/kernel/archive/rockchip-6.11/patches.armbian/wifi-driver-esp8089.patch +++ b/patch/kernel/archive/rockchip-6.12/patches.armbian/wifi-driver-esp8089.patch @@ -3542,7 +3542,7 @@ new file mode 100644 index 000000000000..14186365fdd4 --- /dev/null +++ b/drivers/net/wireless/esp8089/esp_mac80211.c -@@ -0,0 +1,1728 @@ +@@ -0,0 +1,1731 @@ +/* + * Copyright (c) 2011-2014 Espressif System. + * @@ -4938,6 +4938,9 @@ index 000000000000..14186365fdd4 + .set_tsf = esp_op_set_tsf, + .reset_tsf = esp_op_reset_tsf, + .rfkill_poll = esp_op_rfkill_poll, ++ .add_chanctx = ieee80211_emulate_add_chanctx, ++ .remove_chanctx = ieee80211_emulate_remove_chanctx, ++ .change_chanctx = ieee80211_emulate_change_chanctx, +#ifdef HW_SCAN + .hw_scan = esp_op_hw_scan, + .remain_on_channel = esp_op_remain_on_channel, diff --git a/patch/kernel/archive/rockchip-6.11/patches.armbian/wifi-driver-ssv6051.patch b/patch/kernel/archive/rockchip-6.12/patches.armbian/wifi-driver-ssv6051.patch similarity index 99% rename from patch/kernel/archive/rockchip-6.11/patches.armbian/wifi-driver-ssv6051.patch rename to patch/kernel/archive/rockchip-6.12/patches.armbian/wifi-driver-ssv6051.patch index 65d6bf2429a3..669c07b57441 100644 --- a/patch/kernel/archive/rockchip-6.11/patches.armbian/wifi-driver-ssv6051.patch +++ b/patch/kernel/archive/rockchip-6.12/patches.armbian/wifi-driver-ssv6051.patch @@ -35324,10 +35324,10 @@ index 000000000000..93b5275715b5 +#endif diff --git a/drivers/net/wireless/ssv6051/smac/dev.c b/drivers/net/wireless/ssv6051/smac/dev.c new file mode 100644 -index 000000000000..214e93fae460 +index 000000000000..cd93fa42648b --- /dev/null +++ b/drivers/net/wireless/ssv6051/smac/dev.c -@@ -0,0 +1,3881 @@ +@@ -0,0 +1,3884 @@ +/* + * Copyright (c) 2015 South Silicon Valley Microelectronics Inc. + * Copyright (c) 2015 iComm Corporation @@ -38511,6 +38511,9 @@ index 000000000000..214e93fae460 + .conf_tx = ssv6200_conf_tx, + .ampdu_action = ssv6200_ampdu_action, + .wake_tx_queue = ieee80211_handle_wake_tx_queue, ++ .add_chanctx = ieee80211_emulate_add_chanctx, ++ .remove_chanctx = ieee80211_emulate_remove_chanctx, ++ .change_chanctx = ieee80211_emulate_change_chanctx, +#ifdef CONFIG_PM + .suspend = ssv6xxx_suspend, + .resume = ssv6xxx_resume, diff --git a/patch/kernel/archive/rockchip-6.12/patches.libreelec/linux-0002-rockchip-from-list.patch b/patch/kernel/archive/rockchip-6.12/patches.libreelec/linux-0002-rockchip-from-list.patch new file mode 100644 index 000000000000..fbb292deb6e1 --- /dev/null +++ b/patch/kernel/archive/rockchip-6.12/patches.libreelec/linux-0002-rockchip-from-list.patch @@ -0,0 +1,44 @@ +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Jonas Karlman +Date: Sun, 17 Feb 2019 22:14:38 +0000 +Subject: [PATCH] mmc: core: set initial signal voltage on power off + +Some boards have SD card connectors where the power rail cannot be switched +off by the driver. If the card has not been power cycled, it may still be +using 1.8V signaling after a warm re-boot. Bootroms expecting 3.3V signaling +will fail to boot from a UHS card that continue to use 1.8V signaling. + +Set initial signal voltage in mmc_power_off() to allow re-boot to function. + +This fixes re-boot with UHS cards on Asus Tinker Board (Rockchip RK3288), +same issue have been seen on some Rockchip RK3399 boards. + +I am sending this as a RFC because I have no insights into SD/MMC subsystem, +this change fix a re-boot issue on my boards and does not break emmc/sdio. +Is this an acceptable workaround? Any advice is appreciated. + +Signed-off-by: Jonas Karlman +--- + drivers/mmc/core/core.c | 8 ++++++++ + 1 file changed, 8 insertions(+) + +diff --git a/drivers/mmc/core/core.c b/drivers/mmc/core/core.c +index ef53a2578824..d4c53074154a 100644 +--- a/drivers/mmc/core/core.c ++++ b/drivers/mmc/core/core.c +@@ -1368,6 +1368,14 @@ void mmc_power_off(struct mmc_host *host) + if (host->ios.power_mode == MMC_POWER_OFF) + return; + ++ mmc_set_initial_signal_voltage(host); ++ ++ /* ++ * This delay should be sufficient to allow the power supply ++ * to reach the minimum voltage. ++ */ ++ mmc_delay(host->ios.power_delay_ms); ++ + mmc_pwrseq_power_off(host); + + host->ios.clock = 0; + diff --git a/patch/kernel/archive/rockchip-6.12/patches.libreelec/linux-0011-v4l2-from-list.patch b/patch/kernel/archive/rockchip-6.12/patches.libreelec/linux-0011-v4l2-from-list.patch new file mode 100644 index 000000000000..ed0c61c2cb9c --- /dev/null +++ b/patch/kernel/archive/rockchip-6.12/patches.libreelec/linux-0011-v4l2-from-list.patch @@ -0,0 +1,659 @@ +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Jonas Karlman +Date: Mon, 6 Jul 2020 21:54:35 +0000 +Subject: [PATCH] media: v4l2-common: Add helpers to calculate bytesperline and + sizeimage + +Add helper functions to calculate plane bytesperline and sizeimage, these +new helpers consider block width and height when calculating plane +bytesperline and sizeimage. + +This prepare support for new pixel formats added in next patch that make +use of block width and height. + +Signed-off-by: Jonas Karlman +--- + drivers/media/v4l2-core/v4l2-common.c | 77 +++++++++++++-------------- + 1 file changed, 38 insertions(+), 39 deletions(-) + +diff --git a/drivers/media/v4l2-core/v4l2-common.c b/drivers/media/v4l2-core/v4l2-common.c +index e0fbe6ba4b6c..cb2f1acab7cf 100644 +--- a/drivers/media/v4l2-core/v4l2-common.c ++++ b/drivers/media/v4l2-core/v4l2-common.c +@@ -338,6 +338,33 @@ static inline unsigned int v4l2_format_block_height(const struct v4l2_format_inf + return info->block_h[plane]; + } + ++static inline unsigned int v4l2_format_plane_width(const struct v4l2_format_info *info, int plane, ++ unsigned int width) ++{ ++ unsigned int hdiv = plane ? info->hdiv : 1; ++ unsigned int bytes = DIV_ROUND_UP(width * info->bpp[plane], ++ v4l2_format_block_width(info, plane) * ++ v4l2_format_block_height(info, plane)); ++ ++ return DIV_ROUND_UP(bytes, hdiv); ++} ++ ++static inline unsigned int v4l2_format_plane_height(const struct v4l2_format_info *info, int plane, ++ unsigned int height) ++{ ++ unsigned int vdiv = plane ? info->vdiv : 1; ++ unsigned int lines = ALIGN(height, v4l2_format_block_height(info, plane)); ++ ++ return DIV_ROUND_UP(lines, vdiv); ++} ++ ++static inline unsigned int v4l2_format_plane_size(const struct v4l2_format_info *info, int plane, ++ unsigned int width, unsigned int height) ++{ ++ return v4l2_format_plane_width(info, plane, width) * ++ v4l2_format_plane_height(info, plane, height); ++} ++ + void v4l2_apply_frmsize_constraints(u32 *width, u32 *height, + const struct v4l2_frmsize_stepwise *frmsize) + { +@@ -373,37 +400,19 @@ int v4l2_fill_pixfmt_mp(struct v4l2_pix_format_mplane *pixfmt, + + if (info->mem_planes == 1) { + plane = &pixfmt->plane_fmt[0]; +- plane->bytesperline = ALIGN(width, v4l2_format_block_width(info, 0)) * info->bpp[0] / info->bpp_div[0]; ++ plane->bytesperline = v4l2_format_plane_width(info, 0, width); + plane->sizeimage = 0; + +- for (i = 0; i < info->comp_planes; i++) { +- unsigned int hdiv = (i == 0) ? 1 : info->hdiv; +- unsigned int vdiv = (i == 0) ? 1 : info->vdiv; +- unsigned int aligned_width; +- unsigned int aligned_height; +- +- aligned_width = ALIGN(width, v4l2_format_block_width(info, i)); +- aligned_height = ALIGN(height, v4l2_format_block_height(info, i)); +- +- plane->sizeimage += info->bpp[i] * +- DIV_ROUND_UP(aligned_width, hdiv) * +- DIV_ROUND_UP(aligned_height, vdiv) / info->bpp_div[i]; +- } ++ for (i = 0; i < info->comp_planes; i++) ++ plane->sizeimage += ++ v4l2_format_plane_size(info, i, width, height); + } else { + for (i = 0; i < info->comp_planes; i++) { +- unsigned int hdiv = (i == 0) ? 1 : info->hdiv; +- unsigned int vdiv = (i == 0) ? 1 : info->vdiv; +- unsigned int aligned_width; +- unsigned int aligned_height; +- +- aligned_width = ALIGN(width, v4l2_format_block_width(info, i)); +- aligned_height = ALIGN(height, v4l2_format_block_height(info, i)); +- + plane = &pixfmt->plane_fmt[i]; + plane->bytesperline = +- info->bpp[i] * DIV_ROUND_UP(aligned_width, hdiv) / info->bpp_div[i]; +- plane->sizeimage = +- plane->bytesperline * DIV_ROUND_UP(aligned_height, vdiv); ++ v4l2_format_plane_width(info, i, width); ++ plane->sizeimage = plane->bytesperline * ++ v4l2_format_plane_height(info, i, height); + } + } + return 0; +@@ -427,22 +436,12 @@ int v4l2_fill_pixfmt(struct v4l2_pix_format *pixfmt, u32 pixelformat, + pixfmt->width = width; + pixfmt->height = height; + pixfmt->pixelformat = pixelformat; +- pixfmt->bytesperline = ALIGN(width, v4l2_format_block_width(info, 0)) * info->bpp[0] / info->bpp_div[0]; ++ pixfmt->bytesperline = v4l2_format_plane_width(info, 0, width); + pixfmt->sizeimage = 0; + +- for (i = 0; i < info->comp_planes; i++) { +- unsigned int hdiv = (i == 0) ? 1 : info->hdiv; +- unsigned int vdiv = (i == 0) ? 1 : info->vdiv; +- unsigned int aligned_width; +- unsigned int aligned_height; +- +- aligned_width = ALIGN(width, v4l2_format_block_width(info, i)); +- aligned_height = ALIGN(height, v4l2_format_block_height(info, i)); +- +- pixfmt->sizeimage += info->bpp[i] * +- DIV_ROUND_UP(aligned_width, hdiv) * +- DIV_ROUND_UP(aligned_height, vdiv) / info->bpp_div[i]; +- } ++ for (i = 0; i < info->comp_planes; i++) ++ pixfmt->sizeimage += ++ v4l2_format_plane_size(info, i, width, height); + return 0; + } + EXPORT_SYMBOL_GPL(v4l2_fill_pixfmt); + +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Jonas Karlman +Date: Mon, 6 Jul 2020 21:54:36 +0000 +Subject: [PATCH] media: v4l2: Add NV15 and NV20 pixel formats + +Add NV15 and NV20 pixel formats used by the Rockchip Video Decoder for +10-bit buffers. + +NV15 and NV20 is a packed 10-bit 4:2:0/4:2:2 semi-planar Y/UV format +similar to P010 and P210 but has no padding between components. Instead, +luminance and chrominance samples are grouped into 4s so that each group is +packed into an integer number of bytes: + +YYYY = UVUV = 4 * 10 bits = 40 bits = 5 bytes + +The '15' and '20' suffix refers to the optimum effective bits per pixel +which is achieved when the total number of luminance samples is a multiple +of 8 for NV15 and 4 for NV20. + +Signed-off-by: Jonas Karlman +--- + drivers/media/v4l2-core/v4l2-common.c | 3 +++ + drivers/media/v4l2-core/v4l2-ioctl.c | 2 ++ + include/uapi/linux/videodev2.h | 3 +++ + 3 files changed, 8 insertions(+) + +diff --git a/drivers/media/v4l2-core/v4l2-common.c b/drivers/media/v4l2-core/v4l2-common.c +index cb2f1acab7cf..8446a1deffd8 100644 +--- a/drivers/media/v4l2-core/v4l2-common.c ++++ b/drivers/media/v4l2-core/v4l2-common.c +@@ -268,6 +268,9 @@ const struct v4l2_format_info *v4l2_format_info(u32 format) + { .format = V4L2_PIX_FMT_NV42, .pixel_enc = V4L2_PIXEL_ENC_YUV, .mem_planes = 1, .comp_planes = 2, .bpp = { 1, 2, 0, 0 }, .bpp_div = { 1, 1, 1, 1 }, .hdiv = 1, .vdiv = 1 }, + { .format = V4L2_PIX_FMT_P010, .pixel_enc = V4L2_PIXEL_ENC_YUV, .mem_planes = 1, .comp_planes = 2, .bpp = { 2, 2, 0, 0 }, .bpp_div = { 1, 1, 1, 1 }, .hdiv = 2, .vdiv = 1 }, + ++ { .format = V4L2_PIX_FMT_NV15, .pixel_enc = V4L2_PIXEL_ENC_YUV, .mem_planes = 1, .comp_planes = 2, .bpp = { 5, 5, 0, 0 }, .bpp_div = { 1, 1, 1, 1 }, .hdiv = 2, .vdiv = 2, .block_w = { 4, 2, 0, 0 }, .block_h = { 1, 1, 0, 0 } }, ++ { .format = V4L2_PIX_FMT_NV20, .pixel_enc = V4L2_PIXEL_ENC_YUV, .mem_planes = 1, .comp_planes = 2, .bpp = { 5, 5, 0, 0 }, .bpp_div = { 1, 1, 1, 1 }, .hdiv = 2, .vdiv = 1, .block_w = { 4, 2, 0, 0 }, .block_h = { 1, 1, 0, 0 } }, ++ + { .format = V4L2_PIX_FMT_YUV410, .pixel_enc = V4L2_PIXEL_ENC_YUV, .mem_planes = 1, .comp_planes = 3, .bpp = { 1, 1, 1, 0 }, .bpp_div = { 1, 1, 1, 1 }, .hdiv = 4, .vdiv = 4 }, + { .format = V4L2_PIX_FMT_YVU410, .pixel_enc = V4L2_PIXEL_ENC_YUV, .mem_planes = 1, .comp_planes = 3, .bpp = { 1, 1, 1, 0 }, .bpp_div = { 1, 1, 1, 1 }, .hdiv = 4, .vdiv = 4 }, + { .format = V4L2_PIX_FMT_YUV411P, .pixel_enc = V4L2_PIXEL_ENC_YUV, .mem_planes = 1, .comp_planes = 3, .bpp = { 1, 1, 1, 0 }, .bpp_div = { 1, 1, 1, 1 }, .hdiv = 4, .vdiv = 1 }, +diff --git a/drivers/media/v4l2-core/v4l2-ioctl.c b/drivers/media/v4l2-core/v4l2-ioctl.c +index e6fd355a2e92..24771edaa4f2 100644 +--- a/drivers/media/v4l2-core/v4l2-ioctl.c ++++ b/drivers/media/v4l2-core/v4l2-ioctl.c +@@ -1354,6 +1354,8 @@ static void v4l_fill_fmtdesc(struct v4l2_fmtdesc *fmt) + case V4L2_PIX_FMT_NV42: descr = "Y/VU 4:4:4"; break; + case V4L2_PIX_FMT_P010: descr = "10-bit Y/UV 4:2:0"; break; + case V4L2_PIX_FMT_P012: descr = "12-bit Y/UV 4:2:0"; break; ++ case V4L2_PIX_FMT_NV15: descr = "10-bit Y/UV 4:2:0 (Packed)"; break; ++ case V4L2_PIX_FMT_NV20: descr = "10-bit Y/UV 4:2:2 (Packed)"; break; + case V4L2_PIX_FMT_NV12_4L4: descr = "Y/UV 4:2:0 (4x4 Linear)"; break; + case V4L2_PIX_FMT_NV12_16L16: descr = "Y/UV 4:2:0 (16x16 Linear)"; break; + case V4L2_PIX_FMT_NV12_32L32: descr = "Y/UV 4:2:0 (32x32 Linear)"; break; +diff --git a/include/uapi/linux/videodev2.h b/include/uapi/linux/videodev2.h +index 01e630f2ec78..cea44992aea3 100644 +--- a/include/uapi/linux/videodev2.h ++++ b/include/uapi/linux/videodev2.h +@@ -628,6 +628,9 @@ struct v4l2_pix_format { + #define V4L2_PIX_FMT_NV42 v4l2_fourcc('N', 'V', '4', '2') /* 24 Y/VU 4:4:4 */ + #define V4L2_PIX_FMT_P010 v4l2_fourcc('P', '0', '1', '0') /* 24 Y/UV 4:2:0 10-bit per component */ + ++#define V4L2_PIX_FMT_NV15 v4l2_fourcc('N', 'V', '1', '5') /* 15 Y/UV 4:2:0 10-bit packed */ ++#define V4L2_PIX_FMT_NV20 v4l2_fourcc('N', 'V', '2', '0') /* 20 Y/UV 4:2:2 10-bit packed */ ++ + /* two non contiguous planes - one Y, one Cr + Cb interleaved */ + #define V4L2_PIX_FMT_NV12M v4l2_fourcc('N', 'M', '1', '2') /* 12 Y/UV 4:2:0 */ + #define V4L2_PIX_FMT_NV21M v4l2_fourcc('N', 'M', '2', '1') /* 21 Y/VU 4:2:0 */ + +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Jonas Karlman +Date: Mon, 6 Jul 2020 21:54:36 +0000 +Subject: [PATCH] media: rkvdec: h264: Use bytesperline and buffer height to + calculate stride + +Use bytesperline and buffer height to calculate the strides configured. + +This does not really change anything other than ensuring the bytesperline +that is signaled to userspace matches what is configured in HW. + +Signed-off-by: Jonas Karlman +--- + drivers/staging/media/rkvdec/rkvdec-h264.c | 10 +++++----- + 1 file changed, 5 insertions(+), 5 deletions(-) + +diff --git a/drivers/staging/media/rkvdec/rkvdec-h264.c b/drivers/staging/media/rkvdec/rkvdec-h264.c +index 4fc167b42cf0..a8635105e387 100644 +--- a/drivers/staging/media/rkvdec/rkvdec-h264.c ++++ b/drivers/staging/media/rkvdec/rkvdec-h264.c +@@ -896,9 +896,9 @@ static void config_registers(struct rkvdec_ctx *ctx, + dma_addr_t rlc_addr; + dma_addr_t refer_addr; + u32 rlc_len; +- u32 hor_virstride = 0; +- u32 ver_virstride = 0; +- u32 y_virstride = 0; ++ u32 hor_virstride; ++ u32 ver_virstride; ++ u32 y_virstride; + u32 yuv_virstride = 0; + u32 offset; + dma_addr_t dst_addr; +@@ -909,8 +909,8 @@ static void config_registers(struct rkvdec_ctx *ctx, + + f = &ctx->decoded_fmt; + dst_fmt = &f->fmt.pix_mp; +- hor_virstride = (sps->bit_depth_luma_minus8 + 8) * dst_fmt->width / 8; +- ver_virstride = round_up(dst_fmt->height, 16); ++ hor_virstride = dst_fmt->plane_fmt[0].bytesperline; ++ ver_virstride = dst_fmt->height; + y_virstride = hor_virstride * ver_virstride; + + if (sps->chroma_format_idc == 0) + +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Jonas Karlman +Date: Mon, 6 Jul 2020 21:54:37 +0000 +Subject: [PATCH] media: rkvdec: Extract rkvdec_fill_decoded_pixfmt helper + method + +This extract setting decoded pixfmt into a helper method, current code is +replaced with a call to the new helper method. + +The helper method is also called from a new function in next patch. + +Signed-off-by: Jonas Karlman +--- + drivers/staging/media/rkvdec/rkvdec.c | 29 ++++++++++++++------------- + 1 file changed, 15 insertions(+), 14 deletions(-) + +diff --git a/drivers/staging/media/rkvdec/rkvdec.c b/drivers/staging/media/rkvdec/rkvdec.c +index 7bab7586918c..40cc791aef26 100644 +--- a/drivers/staging/media/rkvdec/rkvdec.c ++++ b/drivers/staging/media/rkvdec/rkvdec.c +@@ -27,6 +27,17 @@ + #include "rkvdec.h" + #include "rkvdec-regs.h" + ++static void rkvdec_fill_decoded_pixfmt(struct rkvdec_ctx *ctx, ++ struct v4l2_pix_format_mplane *pix_mp) ++{ ++ v4l2_fill_pixfmt_mp(pix_mp, pix_mp->pixelformat, ++ pix_mp->width, pix_mp->height); ++ pix_mp->plane_fmt[0].sizeimage += 128 * ++ DIV_ROUND_UP(pix_mp->width, 16) * ++ DIV_ROUND_UP(pix_mp->height, 16); ++ pix_mp->field = V4L2_FIELD_NONE; ++} ++ + static int rkvdec_try_ctrl(struct v4l2_ctrl *ctrl) + { + struct rkvdec_ctx *ctx = container_of(ctrl->handler, struct rkvdec_ctx, ctrl_hdl); +@@ -192,13 +203,9 @@ static void rkvdec_reset_decoded_fmt(struct rkvdec_ctx *ctx) + + rkvdec_reset_fmt(ctx, f, ctx->coded_fmt_desc->decoded_fmts[0]); + f->type = V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE; +- v4l2_fill_pixfmt_mp(&f->fmt.pix_mp, +- ctx->coded_fmt_desc->decoded_fmts[0], +- ctx->coded_fmt.fmt.pix_mp.width, +- ctx->coded_fmt.fmt.pix_mp.height); +- f->fmt.pix_mp.plane_fmt[0].sizeimage += 128 * +- DIV_ROUND_UP(f->fmt.pix_mp.width, 16) * +- DIV_ROUND_UP(f->fmt.pix_mp.height, 16); ++ f->fmt.pix_mp.width = ctx->coded_fmt.fmt.pix_mp.width; ++ f->fmt.pix_mp.height = ctx->coded_fmt.fmt.pix_mp.height; ++ rkvdec_fill_decoded_pixfmt(ctx, &f->fmt.pix_mp); + } + + static int rkvdec_enum_framesizes(struct file *file, void *priv, +@@ -264,13 +271,7 @@ static int rkvdec_try_capture_fmt(struct file *file, void *priv, + &pix_mp->height, + &coded_desc->frmsize); + +- v4l2_fill_pixfmt_mp(pix_mp, pix_mp->pixelformat, +- pix_mp->width, pix_mp->height); +- pix_mp->plane_fmt[0].sizeimage += +- 128 * +- DIV_ROUND_UP(pix_mp->width, 16) * +- DIV_ROUND_UP(pix_mp->height, 16); +- pix_mp->field = V4L2_FIELD_NONE; ++ rkvdec_fill_decoded_pixfmt(ctx, pix_mp); + + return 0; + } + +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Jonas Karlman +Date: Mon, 6 Jul 2020 21:54:37 +0000 +Subject: [PATCH] media: rkvdec: Lock capture pixel format in s_ctrl and s_fmt + +Add an optional valid_fmt operation that should return the valid +pixelformat of CAPTURE buffers. + +This is used in next patch to ensure correct pixelformat is used for 10-bit +and 4:2:2 content. + +Signed-off-by: Jonas Karlman +--- + drivers/staging/media/rkvdec/rkvdec.c | 67 +++++++++++++++++++++++---- + drivers/staging/media/rkvdec/rkvdec.h | 2 + + 2 files changed, 61 insertions(+), 8 deletions(-) + +diff --git a/drivers/staging/media/rkvdec/rkvdec.c b/drivers/staging/media/rkvdec/rkvdec.c +index 40cc791aef26..e93e1cb0f829 100644 +--- a/drivers/staging/media/rkvdec/rkvdec.c ++++ b/drivers/staging/media/rkvdec/rkvdec.c +@@ -38,19 +38,56 @@ static void rkvdec_fill_decoded_pixfmt(struct rkvdec_ctx *ctx, + pix_mp->field = V4L2_FIELD_NONE; + } + ++static u32 rkvdec_valid_fmt(struct rkvdec_ctx *ctx, struct v4l2_ctrl *ctrl) ++{ ++ const struct rkvdec_coded_fmt_desc *coded_desc = ctx->coded_fmt_desc; ++ ++ if (coded_desc->ops->valid_fmt) ++ return coded_desc->ops->valid_fmt(ctx, ctrl); ++ ++ return ctx->valid_fmt; ++} ++ + static int rkvdec_try_ctrl(struct v4l2_ctrl *ctrl) + { + struct rkvdec_ctx *ctx = container_of(ctrl->handler, struct rkvdec_ctx, ctrl_hdl); + const struct rkvdec_coded_fmt_desc *desc = ctx->coded_fmt_desc; + +- if (desc->ops->try_ctrl) +- return desc->ops->try_ctrl(ctx, ctrl); ++ if (desc->ops->try_ctrl) { ++ int ret; ++ ret = desc->ops->try_ctrl(ctx, ctrl); ++ if (ret) ++ return ret; ++ } ++ ++ if (ctx->valid_fmt && ctx->valid_fmt != rkvdec_valid_fmt(ctx, ctrl)) ++ /* Only current valid format */ ++ return -EINVAL; ++ ++ return 0; ++} ++ ++static int rkvdec_s_ctrl(struct v4l2_ctrl *ctrl) ++{ ++ struct rkvdec_ctx *ctx = container_of(ctrl->handler, struct rkvdec_ctx, ctrl_hdl); ++ ++ if (ctrl->id == V4L2_CID_STATELESS_H264_SPS && !ctx->valid_fmt) { ++ ctx->valid_fmt = rkvdec_valid_fmt(ctx, ctrl); ++ if (ctx->valid_fmt) { ++ struct v4l2_pix_format_mplane *pix_mp; ++ ++ pix_mp = &ctx->decoded_fmt.fmt.pix_mp; ++ pix_mp->pixelformat = ctx->valid_fmt; ++ rkvdec_fill_decoded_pixfmt(ctx, pix_mp); ++ } ++ } + + return 0; + } + + static const struct v4l2_ctrl_ops rkvdec_ctrl_ops = { + .try_ctrl = rkvdec_try_ctrl, ++ .s_ctrl = rkvdec_s_ctrl, + }; + + static const struct rkvdec_ctrl_desc rkvdec_h264_ctrl_descs[] = { +@@ -201,6 +238,7 @@ static void rkvdec_reset_decoded_fmt(struct rkvdec_ctx *ctx) + { + struct v4l2_format *f = &ctx->decoded_fmt; + ++ ctx->valid_fmt = 0; + rkvdec_reset_fmt(ctx, f, ctx->coded_fmt_desc->decoded_fmts[0]); + f->type = V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE; + f->fmt.pix_mp.width = ctx->coded_fmt.fmt.pix_mp.width; +@@ -256,13 +294,17 @@ static int rkvdec_try_capture_fmt(struct file *file, void *priv, + if (WARN_ON(!coded_desc)) + return -EINVAL; + +- for (i = 0; i < coded_desc->num_decoded_fmts; i++) { +- if (coded_desc->decoded_fmts[i] == pix_mp->pixelformat) +- break; +- } ++ if (ctx->valid_fmt) { ++ pix_mp->pixelformat = ctx->valid_fmt; ++ } else { ++ for (i = 0; i < coded_desc->num_decoded_fmts; i++) { ++ if (coded_desc->decoded_fmts[i] == pix_mp->pixelformat) ++ break; ++ } + +- if (i == coded_desc->num_decoded_fmts) +- pix_mp->pixelformat = coded_desc->decoded_fmts[0]; ++ if (i == coded_desc->num_decoded_fmts) ++ pix_mp->pixelformat = coded_desc->decoded_fmts[0]; ++ } + + /* Always apply the frmsize constraint of the coded end. */ + pix_mp->width = max(pix_mp->width, ctx->coded_fmt.fmt.pix_mp.width); +@@ -326,6 +368,7 @@ static int rkvdec_s_capture_fmt(struct file *file, void *priv, + return ret; + + ctx->decoded_fmt = *f; ++ ctx->valid_fmt = f->fmt.pix_mp.pixelformat; + return 0; + } + +@@ -429,6 +472,14 @@ static int rkvdec_enum_capture_fmt(struct file *file, void *priv, + if (WARN_ON(!ctx->coded_fmt_desc)) + return -EINVAL; + ++ if (ctx->valid_fmt) { ++ if (f->index) ++ return -EINVAL; ++ ++ f->pixelformat = ctx->valid_fmt; ++ return 0; ++ } ++ + if (f->index >= ctx->coded_fmt_desc->num_decoded_fmts) + return -EINVAL; + +diff --git a/drivers/staging/media/rkvdec/rkvdec.h b/drivers/staging/media/rkvdec/rkvdec.h +index 633335ebb9c4..b9e219438bc9 100644 +--- a/drivers/staging/media/rkvdec/rkvdec.h ++++ b/drivers/staging/media/rkvdec/rkvdec.h +@@ -66,6 +66,7 @@ vb2_to_rkvdec_decoded_buf(struct vb2_buffer *buf) + struct rkvdec_coded_fmt_ops { + int (*adjust_fmt)(struct rkvdec_ctx *ctx, + struct v4l2_format *f); ++ u32 (*valid_fmt)(struct rkvdec_ctx *ctx, struct v4l2_ctrl *ctrl); + int (*start)(struct rkvdec_ctx *ctx); + void (*stop)(struct rkvdec_ctx *ctx); + int (*run)(struct rkvdec_ctx *ctx); +@@ -101,6 +102,7 @@ struct rkvdec_ctx { + struct v4l2_fh fh; + struct v4l2_format coded_fmt; + struct v4l2_format decoded_fmt; ++ u32 valid_fmt; + const struct rkvdec_coded_fmt_desc *coded_fmt_desc; + struct v4l2_ctrl_handler ctrl_hdl; + struct rkvdec_dev *dev; + +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Jonas Karlman +Date: Mon, 6 Jul 2020 21:54:37 +0000 +Subject: [PATCH] media: rkvdec: h264: Support High 10 and 4:2:2 profiles + +Add support and enable decoding of H264 High 10 and 4:2:2 profiles. + +Decoded CAPTURE buffer width is aligned to 64 pixels to accommodate HW +requirement on 10-bit format buffers. + +The new valid_fmt operation is implemented and return a valid pixelformat +for the provided SPS control. + +Signed-off-by: Jonas Karlman +--- + drivers/staging/media/rkvdec/rkvdec-h264.c | 33 ++++++++++++++++------ + drivers/staging/media/rkvdec/rkvdec.c | 19 +++++++++---- + 2 files changed, 37 insertions(+), 15 deletions(-) + +diff --git a/drivers/staging/media/rkvdec/rkvdec-h264.c b/drivers/staging/media/rkvdec/rkvdec-h264.c +index a8635105e387..0069d3d198db 100644 +--- a/drivers/staging/media/rkvdec/rkvdec-h264.c ++++ b/drivers/staging/media/rkvdec/rkvdec-h264.c +@@ -1031,19 +1031,14 @@ static int rkvdec_h264_validate_sps(struct rkvdec_ctx *ctx, + { + unsigned int width, height; + +- /* +- * TODO: The hardware supports 10-bit and 4:2:2 profiles, +- * but it's currently broken in the driver. +- * Reject them for now, until it's fixed. +- */ +- if (sps->chroma_format_idc > 1) +- /* Only 4:0:0 and 4:2:0 are supported */ ++ if (sps->chroma_format_idc > 2) ++ /* Only 4:0:0, 4:2:0 and 4:2:2 are supported */ + return -EINVAL; + if (sps->bit_depth_luma_minus8 != sps->bit_depth_chroma_minus8) + /* Luma and chroma bit depth mismatch */ + return -EINVAL; +- if (sps->bit_depth_luma_minus8 != 0) +- /* Only 8-bit is supported */ ++ if (sps->bit_depth_luma_minus8 != 0 && sps->bit_depth_luma_minus8 != 2) ++ /* Only 8-bit and 10-bit is supported */ + return -EINVAL; + + width = (sps->pic_width_in_mbs_minus1 + 1) * 16; +@@ -1064,6 +1059,25 @@ static int rkvdec_h264_validate_sps(struct rkvdec_ctx *ctx, + return 0; + } + ++static u32 rkvdec_h264_valid_fmt(struct rkvdec_ctx *ctx, struct v4l2_ctrl *ctrl) ++{ ++ const struct v4l2_ctrl_h264_sps *sps = ctrl->p_new.p_h264_sps; ++ ++ if (sps->bit_depth_luma_minus8 == 0) { ++ if (sps->chroma_format_idc == 2) ++ return V4L2_PIX_FMT_NV16; ++ else ++ return V4L2_PIX_FMT_NV12; ++ } else if (sps->bit_depth_luma_minus8 == 2) { ++ if (sps->chroma_format_idc == 2) ++ return V4L2_PIX_FMT_NV20; ++ else ++ return V4L2_PIX_FMT_NV15; ++ } ++ ++ return 0; ++} ++ + static int rkvdec_h264_start(struct rkvdec_ctx *ctx) + { + struct rkvdec_dev *rkvdec = ctx->dev; +@@ -1185,6 +1199,7 @@ static int rkvdec_h264_try_ctrl(struct rkvdec_ctx *ctx, struct v4l2_ctrl *ctrl) + + const struct rkvdec_coded_fmt_ops rkvdec_h264_fmt_ops = { + .adjust_fmt = rkvdec_h264_adjust_fmt, ++ .valid_fmt = rkvdec_h264_valid_fmt, + .start = rkvdec_h264_start, + .stop = rkvdec_h264_stop, + .run = rkvdec_h264_run, +diff --git a/drivers/staging/media/rkvdec/rkvdec.c b/drivers/staging/media/rkvdec/rkvdec.c +index e93e1cb0f829..4f5436c89e08 100644 +--- a/drivers/staging/media/rkvdec/rkvdec.c ++++ b/drivers/staging/media/rkvdec/rkvdec.c +@@ -31,7 +31,7 @@ static void rkvdec_fill_decoded_pixfmt(struct rkvdec_ctx *ctx, + struct v4l2_pix_format_mplane *pix_mp) + { + v4l2_fill_pixfmt_mp(pix_mp, pix_mp->pixelformat, +- pix_mp->width, pix_mp->height); ++ ALIGN(pix_mp->width, 64), pix_mp->height); + pix_mp->plane_fmt[0].sizeimage += 128 * + DIV_ROUND_UP(pix_mp->width, 16) * + DIV_ROUND_UP(pix_mp->height, 16); +@@ -136,8 +136,11 @@ static const struct rkvdec_ctrls rkvdec_h264_ctrls = { + .num_ctrls = ARRAY_SIZE(rkvdec_h264_ctrl_descs), + }; + +-static const u32 rkvdec_h264_vp9_decoded_fmts[] = { ++static const u32 rkvdec_h264_decoded_fmts[] = { + V4L2_PIX_FMT_NV12, ++ V4L2_PIX_FMT_NV15, ++ V4L2_PIX_FMT_NV16, ++ V4L2_PIX_FMT_NV20, + }; + + static const struct rkvdec_ctrl_desc rkvdec_vp9_ctrl_descs[] = { +@@ -160,6 +163,10 @@ static const struct rkvdec_ctrls rkvdec_vp9_ctrls = { + .num_ctrls = ARRAY_SIZE(rkvdec_vp9_ctrl_descs), + }; + ++static const u32 rkvdec_vp9_decoded_fmts[] = { ++ V4L2_PIX_FMT_NV12, ++}; ++ + static const struct rkvdec_coded_fmt_desc rkvdec_coded_fmts[] = { + { + .fourcc = V4L2_PIX_FMT_H264_SLICE, +@@ -173,8 +180,8 @@ static const struct rkvdec_coded_fmt_desc rkvdec_coded_fmts[] = { + }, + .ctrls = &rkvdec_h264_ctrls, + .ops = &rkvdec_h264_fmt_ops, +- .num_decoded_fmts = ARRAY_SIZE(rkvdec_h264_vp9_decoded_fmts), +- .decoded_fmts = rkvdec_h264_vp9_decoded_fmts, ++ .num_decoded_fmts = ARRAY_SIZE(rkvdec_h264_decoded_fmts), ++ .decoded_fmts = rkvdec_h264_decoded_fmts, + .subsystem_flags = VB2_V4L2_FL_SUPPORTS_M2M_HOLD_CAPTURE_BUF, + }, + { +@@ -189,8 +196,8 @@ static const struct rkvdec_coded_fmt_desc rkvdec_coded_fmts[] = { + }, + .ctrls = &rkvdec_vp9_ctrls, + .ops = &rkvdec_vp9_fmt_ops, +- .num_decoded_fmts = ARRAY_SIZE(rkvdec_h264_vp9_decoded_fmts), +- .decoded_fmts = rkvdec_h264_vp9_decoded_fmts, ++ .num_decoded_fmts = ARRAY_SIZE(rkvdec_vp9_decoded_fmts), ++ .decoded_fmts = rkvdec_vp9_decoded_fmts, + } + }; + + +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Alex Bee +Date: Sun, 27 Mar 2022 14:18:07 +0200 +Subject: [PATCH] media: rkvdec-h264: Don't hardcode SPS/PPS parameters + +Some SPS/PPS parameters are currently hardcoded in the driver +even though so do exist in the uapi which is stable by now. + +Use them instead of hardcoding them. + +Signed-off-by: Alex Bee +--- + drivers/staging/media/rkvdec/rkvdec-h264.c | 13 +++++++------ + 1 file changed, 7 insertions(+), 6 deletions(-) + +diff --git a/drivers/staging/media/rkvdec/rkvdec-h264.c b/drivers/staging/media/rkvdec/rkvdec-h264.c +index 0069d3d198db..2c27acaba85e 100644 +--- a/drivers/staging/media/rkvdec/rkvdec-h264.c ++++ b/drivers/staging/media/rkvdec/rkvdec-h264.c +@@ -655,13 +655,14 @@ static void assemble_hw_pps(struct rkvdec_ctx *ctx, + + #define WRITE_PPS(value, field) set_ps_field(hw_ps->info, field, value) + /* write sps */ +- WRITE_PPS(0xf, SEQ_PARAMETER_SET_ID); +- WRITE_PPS(0xff, PROFILE_IDC); +- WRITE_PPS(1, CONSTRAINT_SET3_FLAG); ++ WRITE_PPS(sps->seq_parameter_set_id, SEQ_PARAMETER_SET_ID); ++ WRITE_PPS(sps->profile_idc, PROFILE_IDC); ++ WRITE_PPS((sps->constraint_set_flags & 1 << 3) ? 1 : 0, CONSTRAINT_SET3_FLAG); + WRITE_PPS(sps->chroma_format_idc, CHROMA_FORMAT_IDC); + WRITE_PPS(sps->bit_depth_luma_minus8, BIT_DEPTH_LUMA); + WRITE_PPS(sps->bit_depth_chroma_minus8, BIT_DEPTH_CHROMA); +- WRITE_PPS(0, QPPRIME_Y_ZERO_TRANSFORM_BYPASS_FLAG); ++ WRITE_PPS(!!(sps->flags & V4L2_H264_SPS_FLAG_QPPRIME_Y_ZERO_TRANSFORM_BYPASS), ++ QPPRIME_Y_ZERO_TRANSFORM_BYPASS_FLAG); + WRITE_PPS(sps->log2_max_frame_num_minus4, LOG2_MAX_FRAME_NUM_MINUS4); + WRITE_PPS(sps->max_num_ref_frames, MAX_NUM_REF_FRAMES); + WRITE_PPS(sps->pic_order_cnt_type, PIC_ORDER_CNT_TYPE); +@@ -688,8 +689,8 @@ static void assemble_hw_pps(struct rkvdec_ctx *ctx, + DIRECT_8X8_INFERENCE_FLAG); + + /* write pps */ +- WRITE_PPS(0xff, PIC_PARAMETER_SET_ID); +- WRITE_PPS(0x1f, PPS_SEQ_PARAMETER_SET_ID); ++ WRITE_PPS(pps->pic_parameter_set_id, PIC_PARAMETER_SET_ID); ++ WRITE_PPS(pps->seq_parameter_set_id, PPS_SEQ_PARAMETER_SET_ID); + WRITE_PPS(!!(pps->flags & V4L2_H264_PPS_FLAG_ENTROPY_CODING_MODE), + ENTROPY_CODING_MODE_FLAG); + WRITE_PPS(!!(pps->flags & V4L2_H264_PPS_FLAG_BOTTOM_FIELD_PIC_ORDER_IN_FRAME_PRESENT), diff --git a/patch/kernel/archive/rockchip-6.12/patches.libreelec/linux-1000-drm-rockchip.patch b/patch/kernel/archive/rockchip-6.12/patches.libreelec/linux-1000-drm-rockchip.patch new file mode 100644 index 000000000000..6af1e51feea3 --- /dev/null +++ b/patch/kernel/archive/rockchip-6.12/patches.libreelec/linux-1000-drm-rockchip.patch @@ -0,0 +1,2639 @@ +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Jonas Karlman +Date: Sun, 3 May 2020 16:51:31 +0000 +Subject: [PATCH] drm/rockchip: vop: filter modes outside 0.5% pixel clock + tolerance + +Filter modes that require a pixel clock that differ more then 0.5% +from the requested pixel clock. + +This filter is only applied to tmds only connector and/or encoders. + +Signed-off-by: Jonas Karlman +Signed-off-by: Alex Bee +--- + drivers/gpu/drm/rockchip/rockchip_drm_vop.c | 54 +++++++++++++++++++++ + 1 file changed, 54 insertions(+) + +diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c +index dbe4d411b30f..fac23d370ee0 100644 +--- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c ++++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c +@@ -1207,6 +1207,59 @@ static void vop_crtc_disable_vblank(struct drm_crtc *crtc) + spin_unlock_irqrestore(&vop->irq_lock, flags); + } + ++static bool vop_crtc_is_tmds(struct drm_crtc *crtc) ++{ ++ struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc->state); ++ struct drm_encoder *encoder; ++ ++ switch (s->output_type) { ++ case DRM_MODE_CONNECTOR_LVDS: ++ case DRM_MODE_CONNECTOR_DSI: ++ return false; ++ case DRM_MODE_CONNECTOR_eDP: ++ case DRM_MODE_CONNECTOR_HDMIA: ++ case DRM_MODE_CONNECTOR_DisplayPort: ++ return true; ++ } ++ ++ drm_for_each_encoder_mask(encoder, crtc->dev, crtc->state->encoder_mask) ++ if (encoder->encoder_type == DRM_MODE_ENCODER_TMDS) ++ return true; ++ ++ return false; ++} ++ ++/* ++ * The VESA DMT standard specifies a 0.5% pixel clock frequency tolerance. ++ * The CVT spec reuses that tolerance in its examples. ++ */ ++#define CLOCK_TOLERANCE_PER_MILLE 5 ++ ++static enum drm_mode_status vop_crtc_mode_valid5(struct drm_crtc *crtc, ++ const struct drm_display_mode *mode) ++{ ++ struct vop *vop = to_vop(crtc); ++ long rounded_rate; ++ long lowest, highest; ++ ++ if (!vop_crtc_is_tmds(crtc)) ++ return MODE_OK; ++ ++ rounded_rate = clk_round_rate(vop->dclk, mode->clock * 1000 + 999); ++ if (rounded_rate < 0) ++ return MODE_NOCLOCK; ++ ++ lowest = mode->clock * (1000 - CLOCK_TOLERANCE_PER_MILLE); ++ if (rounded_rate < lowest) ++ return MODE_CLOCK_LOW; ++ ++ highest = mode->clock * (1000 + CLOCK_TOLERANCE_PER_MILLE); ++ if (rounded_rate > highest) ++ return MODE_CLOCK_HIGH; ++ ++ return MODE_OK; ++} ++ + static bool vop_crtc_mode_fixup(struct drm_crtc *crtc, + const struct drm_display_mode *mode, + struct drm_display_mode *adjusted_mode) + +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Jonas Karlman +Date: Mon, 20 Jul 2020 15:15:50 +0000 +Subject: [PATCH] drm/rockchip: vop: filter interlaced modes + +The current version of the driver does not support interlaced modes, +lets filter any interlaced mode. + +Signed-off-by: Jonas Karlman +--- + drivers/gpu/drm/rockchip/rockchip_drm_vop.c | 3 +++ + 1 file changed, 3 insertions(+) + +diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c +index fac23d370ee0..9f7326c5b1f5 100644 +--- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c ++++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c +@@ -1245,6 +1245,9 @@ static enum drm_mode_status vop_crtc_mode_valid(struct drm_crtc *crtc, + if (!vop_crtc_is_tmds(crtc)) + return MODE_OK; + ++ if (mode->flags & DRM_MODE_FLAG_INTERLACE) ++ return MODE_NO_INTERLACE; ++ + rounded_rate = clk_round_rate(vop->dclk, mode->clock * 1000 + 999); + if (rounded_rate < 0) + return MODE_NOCLOCK; + +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Jonas Karlman +Date: Mon, 20 Jul 2020 11:46:16 +0000 +Subject: [PATCH] drm/rockchip: vop: filter modes above max output supported + +Filter any mode with a resolution not supported by the VOP. + +Signed-off-by: Jonas Karlman +Signed-off-by: Alex Bee +--- + drivers/gpu/drm/rockchip/rockchip_drm_vop.c | 48 +++++++++++++++------ + 1 file changed, 34 insertions(+), 14 deletions(-) + +diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c +index 9f7326c5b1f5..30e252ba7184 100644 +--- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c ++++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c +@@ -1229,6 +1229,24 @@ static bool vop_crtc_is_tmds(struct drm_crtc *crtc) + return false; + } + ++static enum drm_mode_status vop_crtc_size_valid(struct drm_crtc *crtc, ++ const struct drm_display_mode *mode) ++{ ++ struct vop *vop = to_vop(crtc); ++ const struct vop_rect *max_output = &vop->data->max_output; ++ ++ if (max_output->width && max_output->height) { ++ /* only the size of the resulting rect matters */ ++ if(drm_mode_validate_size(mode, max_output->width, ++ max_output->height) != MODE_OK) { ++ return drm_mode_validate_size(mode, max_output->height, ++ max_output->width); ++ } ++ } ++ ++ return MODE_OK; ++} ++ + /* + * The VESA DMT standard specifies a 0.5% pixel clock frequency tolerance. + * The CVT spec reuses that tolerance in its examples. +@@ -1242,25 +1260,24 @@ static enum drm_mode_status vop_crtc_mode_valid(struct drm_crtc *crtc, + long rounded_rate; + long lowest, highest; + +- if (!vop_crtc_is_tmds(crtc)) +- return MODE_OK; +- + if (mode->flags & DRM_MODE_FLAG_INTERLACE) +- return MODE_NO_INTERLACE; ++ return MODE_NO_INTERLACE; + +- rounded_rate = clk_round_rate(vop->dclk, mode->clock * 1000 + 999); +- if (rounded_rate < 0) +- return MODE_NOCLOCK; ++ if (vop_crtc_is_tmds(crtc)) { ++ rounded_rate = clk_round_rate(vop->dclk, mode->clock * 1000 + 999); ++ if (rounded_rate < 0) ++ return MODE_NOCLOCK; + +- lowest = mode->clock * (1000 - CLOCK_TOLERANCE_PER_MILLE); +- if (rounded_rate < lowest) +- return MODE_CLOCK_LOW; ++ lowest = mode->clock * (1000 - CLOCK_TOLERANCE_PER_MILLE); ++ if (rounded_rate < lowest) ++ return MODE_CLOCK_LOW; + +- highest = mode->clock * (1000 + CLOCK_TOLERANCE_PER_MILLE); +- if (rounded_rate > highest) +- return MODE_CLOCK_HIGH; ++ highest = mode->clock * (1000 + CLOCK_TOLERANCE_PER_MILLE); ++ if (rounded_rate > highest) ++ return MODE_CLOCK_HIGH; ++ } + +- return MODE_OK; ++ return vop_crtc_size_valid(crtc, mode); + } + + static bool vop_crtc_mode_fixup(struct drm_crtc *crtc, +@@ -1270,6 +1287,9 @@ static bool vop_crtc_mode_fixup(struct drm_crtc *crtc, + struct vop *vop = to_vop(crtc); + unsigned long rate; + ++ if (vop_crtc_size_valid(crtc, adjusted_mode) != MODE_OK) ++ return false; ++ + /* + * Clock craziness. + * + +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Yakir Yang +Date: Mon, 11 Jul 2016 19:05:39 +0800 +Subject: [PATCH] drm/rockchip: dw_hdmi: adjust cklvl & txlvl for RF/EMI + +Dut to the high HDMI signal voltage driver, Mickey have meet +a serious RF/EMI problem, so we decided to reduce HDMI signal +voltage to a proper value. + +The default params for phy is cklvl = 20 & txlvl = 13 (RF/EMI failed) + ck: lvl = 13, term=100, vlo = 2.71, vhi=3.14, vswing = 0.43 + tx: lvl = 20, term=100, vlo = 2.81, vhi=3.16, vswing = 0.35 + +1. We decided to reduce voltage value to lower, but VSwing still +keep high, RF/EMI have been improved but still failed. + ck: lvl = 6, term=100, vlo = 2.61, vhi=3.11, vswing = 0.50 + tx: lvl = 6, term=100, vlo = 2.61, vhi=3.11, vswing = 0.50 + +2. We try to keep voltage value and vswing both lower, then RF/EMI +test all passed ;) + ck: lvl = 11, term= 66, vlo = 2.68, vhi=3.09, vswing = 0.40 + tx: lvl = 11, term= 66, vlo = 2.68, vhi=3.09, vswing = 0.40 +When we back to run HDMI different test and single-end test, we see +different test passed, but signle-end test failed. The oscilloscope +show that simgle-end clock's VL value is 1.78v (which remind LowLimit +should not lower then 2.6v). + +3. That's to say there are some different between PHY document and +measure value. And according to experiment 2 results, we need to +higher clock voltage and lower data voltage, then we can keep RF/EMI +satisfied and single-end & differen test passed. + ck: lvl = 9, term=100, vlo = 2.65, vhi=3.12, vswing = 0.47 + tx: lvl = 16, term=100, vlo = 2.75, vhi=3.15, vswing = 0.39 + +Signed-off-by: Yakir Yang +Signed-off-by: Jonas Karlman +--- + drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c +index c14f88893868..4411ca8fd7ed 100644 +--- a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c ++++ b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c +@@ -201,7 +201,7 @@ static const struct dw_hdmi_curr_ctrl rockchip_cur_ctr[] = { + static const struct dw_hdmi_phy_config rockchip_phy_config[] = { + /*pixelclk symbol term vlev*/ + { 74250000, 0x8009, 0x0004, 0x0272}, +- { 148500000, 0x802b, 0x0004, 0x028d}, ++ { 165000000, 0x802b, 0x0004, 0x0209}, + { 297000000, 0x8039, 0x0005, 0x028d}, + { ~0UL, 0x0000, 0x0000, 0x0000} + }; + +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Nickey Yang +Date: Mon, 13 Feb 2017 15:40:29 +0800 +Subject: [PATCH] drm/rockchip: dw_hdmi: add phy_config for 594Mhz pixel clock + +Add phy_config for 594Mhz pixel clock used for 4K@60hz + +Signed-off-by: Nickey Yang +Signed-off-by: Jonas Karlman +--- + drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c +index 4411ca8fd7ed..bec381cde0bc 100644 +--- a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c ++++ b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c +@@ -203,6 +203,7 @@ static const struct dw_hdmi_phy_config rockchip_phy_config[] = { + { 74250000, 0x8009, 0x0004, 0x0272}, + { 165000000, 0x802b, 0x0004, 0x0209}, + { 297000000, 0x8039, 0x0005, 0x028d}, ++ { 594000000, 0x8039, 0x0000, 0x019d}, + { ~0UL, 0x0000, 0x0000, 0x0000} + }; + + +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Douglas Anderson +Date: Mon, 11 Jul 2016 19:05:36 +0800 +Subject: [PATCH] drm/rockchip: dw_hdmi: Set cur_ctr to 0 always + +Jitter was improved by lowering the MPLL bandwidth to account for high +frequency noise in the rk3288 PLL. In each case MPLL bandwidth was +lowered only enough to get us a comfortable margin. We believe that +lowering the bandwidth like this is safe given sufficient testing. + +Signed-off-by: Douglas Anderson +Signed-off-by: Yakir Yang +Signed-off-by: Jonas Karlman +--- + drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c | 16 ++-------------- + 1 file changed, 2 insertions(+), 14 deletions(-) + +diff --git a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c +index bec381cde0bc..72c1d65c7b75 100644 +--- a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c ++++ b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c +@@ -178,20 +178,6 @@ static const struct dw_hdmi_mpll_config rockchip_mpll_cfg[] = { + static const struct dw_hdmi_curr_ctrl rockchip_cur_ctr[] = { + /* pixelclk bpp8 bpp10 bpp12 */ + { +- 40000000, { 0x0018, 0x0018, 0x0018 }, +- }, { +- 65000000, { 0x0028, 0x0028, 0x0028 }, +- }, { +- 66000000, { 0x0038, 0x0038, 0x0038 }, +- }, { +- 74250000, { 0x0028, 0x0038, 0x0038 }, +- }, { +- 83500000, { 0x0028, 0x0038, 0x0038 }, +- }, { +- 146250000, { 0x0038, 0x0038, 0x0038 }, +- }, { +- 148500000, { 0x0000, 0x0038, 0x0038 }, +- }, { + 600000000, { 0x0000, 0x0000, 0x0000 }, + }, { + ~0UL, { 0x0000, 0x0000, 0x0000}, + +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Jonas Karlman +Date: Sat, 10 Oct 2020 10:16:32 +0000 +Subject: [PATCH] drm/rockchip: dw-hdmi: encoder error handling + +Signed-off-by: Jonas Karlman +--- + drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c | 10 ++++++++-- + 1 file changed, 8 insertions(+), 2 deletions(-) + +diff --git a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c +index 38dded2baaf7..9e460b7e14a4 100644 +--- a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c ++++ b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c +@@ -592,7 +592,7 @@ static int dw_hdmi_rockchip_bind(struct device *dev, struct device *master, + if (IS_ERR(hdmi->phy)) { + ret = PTR_ERR(hdmi->phy); + if (ret != -EPROBE_DEFER) +- drm_err(hdmi, "failed to get phy\n"); ++ drm_err(hdmi, "failed to get phy: %d\n", ret); + return ret; + } + +@@ -605,7 +605,12 @@ static int dw_hdmi_rockchip_bind(struct device *dev, struct device *master, + } + + drm_encoder_helper_add(encoder, &dw_hdmi_rockchip_encoder_helper_funcs); +- drm_simple_encoder_init(drm, encoder, DRM_MODE_ENCODER_TMDS); ++ ++ ret = drm_simple_encoder_init(drm, encoder, DRM_MODE_ENCODER_TMDS); ++ if (ret) { ++ DRM_DEV_ERROR(hdmi->dev, "Failed to init encoder: %d\n", ret); ++ goto err_disable_clk; ++ } + + platform_set_drvdata(pdev, hdmi); + +@@ -624,7 +629,7 @@ static int dw_hdmi_rockchip_bind(struct device *dev, struct device *master, + + err_bind: + drm_encoder_cleanup(encoder); +- ++err_disable_clk: + return ret; + } + + +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Jonas Karlman +Date: Sat, 10 Oct 2020 14:32:21 +0000 +Subject: [PATCH] drm/rockchip: vop: split rk3288 vop + +Signed-off-by: Jonas Karlman +--- + drivers/gpu/drm/rockchip/rockchip_vop_reg.c | 21 ++++++++++++++++++--- + 1 file changed, 18 insertions(+), 3 deletions(-) + +diff --git a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c +index 9b25b8ffd0ce..a2b281e290e0 100644 +--- a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c ++++ b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c +@@ -740,7 +740,7 @@ static const struct vop_intr rk3288_vop_intr = { + .clear = VOP_REG(RK3288_INTR_CTRL0, 0xf, 8), + }; + +-static const struct vop_data rk3288_vop = { ++static const struct vop_data rk3288_vop_big = { + .version = VOP_VERSION(3, 1), + .feature = VOP_FEATURE_OUTPUT_RGB10, + .max_output = { 3840, 2160 }, +@@ -753,6 +753,19 @@ static const struct vop_data rk3288_vop = { + .lut_size = 1024, + }; + ++static const struct vop_data rk3288_vop_lit = { ++ .version = VOP_VERSION(3, 1), ++ .feature = VOP_FEATURE_OUTPUT_RGB10, ++ .max_output = { 2560, 1600 }, ++ .intr = &rk3288_vop_intr, ++ .common = &rk3288_common, ++ .modeset = &rk3288_modeset, ++ .output = &rk3288_output, ++ .win = rk3288_vop_win_data, ++ .win_size = ARRAY_SIZE(rk3288_vop_win_data), ++ .lut_size = 1024, ++}; ++ + static const int rk3368_vop_intrs[] = { + FS_INTR, + 0, 0, +@@ -1142,8 +1155,10 @@ static const struct of_device_id vop_driver_dt_match[] = { + .data = &rk3066_vop }, + { .compatible = "rockchip,rk3188-vop", + .data = &rk3188_vop }, +- { .compatible = "rockchip,rk3288-vop", +- .data = &rk3288_vop }, ++ { .compatible = "rockchip,rk3288-vop-big", ++ .data = &rk3288_vop_big }, ++ { .compatible = "rockchip,rk3288-vop-lit", ++ .data = &rk3288_vop_lit }, + { .compatible = "rockchip,rk3368-vop", + .data = &rk3368_vop }, + { .compatible = "rockchip,rk3366-vop", + +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Jonas Karlman +Date: Sat, 10 Oct 2020 14:33:30 +0000 +Subject: [PATCH] ARM: dts: rockchip: split rk3288 vop + +Signed-off-by: Jonas Karlman +--- + arch/arm/boot/dts/rockchip/rk3288.dtsi | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +diff --git a/arch/arm/boot/dts/rockchip/rk3288.dtsi b/arch/arm/boot/dts/rockchip/rk3288.dtsi +index 487b0e03d4b4..c60eacab8a79 100644 +--- a/arch/arm/boot/dts/rockchip/rk3288.dtsi ++++ b/arch/arm/boot/dts/rockchip/rk3288.dtsi +@@ -1017,7 +1017,7 @@ rga: rga@ff920000 { + }; + + vopb: vop@ff930000 { +- compatible = "rockchip,rk3288-vop"; ++ compatible = "rockchip,rk3288-vop-big"; + reg = <0x0 0xff930000 0x0 0x19c>, <0x0 0xff931000 0x0 0x1000>; + interrupts = ; + clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>; +@@ -1066,7 +1066,7 @@ vopb_mmu: iommu@ff930300 { + }; + + vopl: vop@ff940000 { +- compatible = "rockchip,rk3288-vop"; ++ compatible = "rockchip,rk3288-vop-lit"; + reg = <0x0 0xff940000 0x0 0x19c>, <0x0 0xff941000 0x0 0x1000>; + interrupts = ; + clocks = <&cru ACLK_VOP1>, <&cru DCLK_VOP1>, <&cru HCLK_VOP1>; + +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Jonas Karlman +Date: Mon, 20 Jul 2020 18:00:44 +0000 +Subject: [PATCH] drm/bridge: dw-hdmi: add mtmdsclock parameter to phy + configure ops + +Signed-off-by: Jonas Karlman +--- + drivers/gpu/drm/bridge/synopsys/dw-hdmi.c | 10 ++++++---- + drivers/gpu/drm/renesas/rcar-du/rcar_dw_hdmi.c | 3 ++- + include/drm/bridge/dw_hdmi.h | 3 ++- + 3 files changed, 10 insertions(+), 6 deletions(-) + +diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c +index 40d8ca37f5bc..22af42a08980 100644 +--- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c ++++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c +@@ -138,7 +138,8 @@ struct dw_hdmi_phy_data { + bool has_svsret; + int (*configure)(struct dw_hdmi *hdmi, + const struct dw_hdmi_plat_data *pdata, +- unsigned long mpixelclock); ++ unsigned long mpixelclock, ++ unsigned long mtmdsclock); + }; + + struct dw_hdmi { +@@ -1585,7 +1586,8 @@ static int dw_hdmi_phy_power_on(struct dw_hdmi *hdmi) + */ + static int hdmi_phy_configure_dwc_hdmi_3d_tx(struct dw_hdmi *hdmi, + const struct dw_hdmi_plat_data *pdata, +- unsigned long mpixelclock) ++ unsigned long mpixelclock, ++ unsigned long mtmdsclock) + { + const struct dw_hdmi_mpll_config *mpll_config = pdata->mpll_cfg; + const struct dw_hdmi_curr_ctrl *curr_ctrl = pdata->cur_ctr; +@@ -1660,9 +1662,9 @@ static int hdmi_phy_configure(struct dw_hdmi *hdmi, + + /* Write to the PHY as configured by the platform */ + if (pdata->configure_phy) +- ret = pdata->configure_phy(hdmi, pdata->priv_data, mpixelclock); ++ ret = pdata->configure_phy(hdmi, pdata->priv_data, mpixelclock, mtmdsclock); + else +- ret = phy->configure(hdmi, pdata, mpixelclock); ++ ret = phy->configure(hdmi, pdata, mpixelclock, mtmdsclock); + if (ret) { + dev_err(hdmi->dev, "PHY configuration failed (clock %lu)\n", + mpixelclock); +diff --git a/drivers/gpu/drm/renesas/rcar-du/rcar_dw_hdmi.c b/drivers/gpu/drm/renesas/rcar-du/rcar_dw_hdmi.c +index 18ed14911b98..9c75095a25c5 100644 +--- a/drivers/gpu/drm/renesas/rcar-du/rcar_dw_hdmi.c ++++ b/drivers/gpu/drm/renesas/rcar-du/rcar_dw_hdmi.c +@@ -53,7 +53,8 @@ rcar_hdmi_mode_valid(struct dw_hdmi *hdmi, void *data, + } + + static int rcar_hdmi_phy_configure(struct dw_hdmi *hdmi, void *data, +- unsigned long mpixelclock) ++ unsigned long mpixelclock, ++ unsigned long mtmdsclock) + { + const struct rcar_hdmi_phy_params *params = rcar_hdmi_phy_params; + +diff --git a/include/drm/bridge/dw_hdmi.h b/include/drm/bridge/dw_hdmi.h +index f668e75fbabe..48fb72f9614f 100644 +--- a/include/drm/bridge/dw_hdmi.h ++++ b/include/drm/bridge/dw_hdmi.h +@@ -159,7 +159,8 @@ struct dw_hdmi_plat_data { + const struct dw_hdmi_curr_ctrl *cur_ctr; + const struct dw_hdmi_phy_config *phy_config; + int (*configure_phy)(struct dw_hdmi *hdmi, void *data, +- unsigned long mpixelclock); ++ unsigned long mpixelclock, ++ unsigned long mtmdsclock); + + unsigned int disable_cec : 1; + }; + +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Jonas Karlman +Date: Mon, 20 Jul 2020 21:34:48 +0000 +Subject: [PATCH] drm/bridge: dw-hdmi: support configuring phy for deep color + +Q: Should we rename dw_hdmi_curr_ctrl and dw_hdmi_phy_config mpixelclock to mtmdsclock ? + +Signed-off-by: Jonas Karlman +--- + drivers/gpu/drm/bridge/synopsys/dw-hdmi.c | 17 ++++++++++++----- + 1 file changed, 12 insertions(+), 5 deletions(-) + +diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c +index 22af42a08980..7fd45a7006b1 100644 +--- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c ++++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c +@@ -1592,6 +1592,7 @@ static int hdmi_phy_configure_dwc_hdmi_3d_tx(struct dw_hdmi *hdmi, + const struct dw_hdmi_mpll_config *mpll_config = pdata->mpll_cfg; + const struct dw_hdmi_curr_ctrl *curr_ctrl = pdata->cur_ctr; + const struct dw_hdmi_phy_config *phy_config = pdata->phy_config; ++ int depth; + + /* TOFIX Will need 420 specific PHY configuration tables */ + +@@ -1601,11 +1602,11 @@ static int hdmi_phy_configure_dwc_hdmi_3d_tx(struct dw_hdmi *hdmi, + break; + + for (; curr_ctrl->mpixelclock != ~0UL; curr_ctrl++) +- if (mpixelclock <= curr_ctrl->mpixelclock) ++ if (mtmdsclock <= curr_ctrl->mpixelclock) + break; + + for (; phy_config->mpixelclock != ~0UL; phy_config++) +- if (mpixelclock <= phy_config->mpixelclock) ++ if (mtmdsclock <= phy_config->mpixelclock) + break; + + if (mpll_config->mpixelclock == ~0UL || +@@ -1613,11 +1614,17 @@ static int hdmi_phy_configure_dwc_hdmi_3d_tx(struct dw_hdmi *hdmi, + phy_config->mpixelclock == ~0UL) + return -EINVAL; + +- dw_hdmi_phy_i2c_write(hdmi, mpll_config->res[0].cpce, ++ depth = hdmi_bus_fmt_color_depth(hdmi->hdmi_data.enc_out_bus_format); ++ if (depth > 8 && mpixelclock != mtmdsclock) ++ depth = fls(depth - 8) - 1; ++ else ++ depth = 0; ++ ++ dw_hdmi_phy_i2c_write(hdmi, mpll_config->res[depth].cpce, + HDMI_3D_TX_PHY_CPCE_CTRL); +- dw_hdmi_phy_i2c_write(hdmi, mpll_config->res[0].gmp, ++ dw_hdmi_phy_i2c_write(hdmi, mpll_config->res[depth].gmp, + HDMI_3D_TX_PHY_GMPCTRL); +- dw_hdmi_phy_i2c_write(hdmi, curr_ctrl->curr[0], ++ dw_hdmi_phy_i2c_write(hdmi, curr_ctrl->curr[depth], + HDMI_3D_TX_PHY_CURRCTRL); + + dw_hdmi_phy_i2c_write(hdmi, 0, HDMI_3D_TX_PHY_PLLPHBYCTRL); + +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Jonas Karlman +Date: Mon, 20 Jul 2020 22:25:15 +0000 +Subject: [PATCH] drm/bridge: dw-hdmi: add mpll_cfg_420 for ycbcr420 mode + +Signed-off-by: Jonas Karlman +--- + drivers/gpu/drm/bridge/synopsys/dw-hdmi.c | 4 +++- + include/drm/bridge/dw_hdmi.h | 1 + + 2 files changed, 4 insertions(+), 1 deletion(-) + +diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c +index 7fd45a7006b1..a2d101ebf7a7 100644 +--- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c ++++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c +@@ -1594,7 +1594,9 @@ static int hdmi_phy_configure_dwc_hdmi_3d_tx(struct dw_hdmi *hdmi, + const struct dw_hdmi_phy_config *phy_config = pdata->phy_config; + int depth; + +- /* TOFIX Will need 420 specific PHY configuration tables */ ++ if (hdmi_bus_fmt_is_yuv420(hdmi->hdmi_data.enc_out_bus_format) && ++ pdata->mpll_cfg_420) ++ mpll_config = pdata->mpll_cfg_420; + + /* PLL/MPLL Cfg - always match on final entry */ + for (; mpll_config->mpixelclock != ~0UL; mpll_config++) +diff --git a/include/drm/bridge/dw_hdmi.h b/include/drm/bridge/dw_hdmi.h +index 48fb72f9614f..02554d324b4b 100644 +--- a/include/drm/bridge/dw_hdmi.h ++++ b/include/drm/bridge/dw_hdmi.h +@@ -156,6 +156,7 @@ struct dw_hdmi_plat_data { + + /* Synopsys PHY support */ + const struct dw_hdmi_mpll_config *mpll_cfg; ++ const struct dw_hdmi_mpll_config *mpll_cfg_420; + const struct dw_hdmi_curr_ctrl *cur_ctr; + const struct dw_hdmi_phy_config *phy_config; + int (*configure_phy)(struct dw_hdmi *hdmi, void *data, + +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Jonas Karlman +Date: Mon, 20 Jul 2020 22:26:19 +0000 +Subject: [PATCH] drm/rockchip: dw-hdmi: add YCbCr420 mpll cfg for rk3399 + +Signed-off-by: Jonas Karlman +--- + drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c | 41 +++++++++++++++++++++ + 1 file changed, 41 insertions(+) + +diff --git a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c +index d42ac9fa3246..a37565649c13 100644 +--- a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c ++++ b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c +@@ -177,6 +177,46 @@ static const struct dw_hdmi_mpll_config rockchip_mpll_cfg[] = { + } + }; + ++static const struct dw_hdmi_mpll_config rockchip_mpll_cfg_420[] = { ++ { ++ 30666000, { ++ { 0x00b7, 0x0000 }, ++ { 0x2157, 0x0000 }, ++ { 0x40f7, 0x0000 }, ++ }, ++ }, { ++ 92000000, { ++ { 0x00b7, 0x0000 }, ++ { 0x2143, 0x0001 }, ++ { 0x40a3, 0x0001 }, ++ }, ++ }, { ++ 184000000, { ++ { 0x0073, 0x0001 }, ++ { 0x2146, 0x0002 }, ++ { 0x4062, 0x0002 }, ++ }, ++ }, { ++ 340000000, { ++ { 0x0052, 0x0003 }, ++ { 0x214d, 0x0003 }, ++ { 0x4065, 0x0003 }, ++ }, ++ }, { ++ 600000000, { ++ { 0x0041, 0x0003 }, ++ { 0x3b4d, 0x0003 }, ++ { 0x5a65, 0x0003 }, ++ }, ++ }, { ++ ~0UL, { ++ { 0x0000, 0x0000 }, ++ { 0x0000, 0x0000 }, ++ { 0x0000, 0x0000 }, ++ }, ++ } ++}; ++ + static const struct dw_hdmi_curr_ctrl rockchip_cur_ctr[] = { + /* pixelclk bpp8 bpp10 bpp12 */ + { +@@ -474,6 +514,7 @@ static struct rockchip_hdmi_chip_data rk3399_chip_data = { + static const struct dw_hdmi_plat_data rk3399_hdmi_drv_data = { + .mode_valid = dw_hdmi_rockchip_mode_valid, + .mpll_cfg = rockchip_mpll_cfg, ++ .mpll_cfg_420 = rockchip_mpll_cfg_420, + .cur_ctr = rockchip_cur_ctr, + .phy_config = rockchip_phy_config, + .phy_data = &rk3399_chip_data, + +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Shunqing Chen +Date: Wed, 15 Jul 2020 15:19:11 +0800 +Subject: [PATCH] drm/rockchip: dw-hdmi: add YCbCr420 mpll cfg for rk3288w + +Signed-off-by: Shunqing Chen +Signed-off-by: Jonas Karlman +--- + drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c | 41 +++++++++++++++++++++ + 1 file changed, 41 insertions(+) + +diff --git a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c +index a37565649c13..66fee351f4a7 100644 +--- a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c ++++ b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c +@@ -217,6 +217,46 @@ static const struct dw_hdmi_mpll_config rockchip_mpll_cfg_420[] = { + } + }; + ++static const struct dw_hdmi_mpll_config rockchip_rk3288w_mpll_cfg_420[] = { ++ { ++ 30666000, { ++ { 0x00b7, 0x0000 }, ++ { 0x2157, 0x0000 }, ++ { 0x40f7, 0x0000 }, ++ }, ++ }, { ++ 92000000, { ++ { 0x00b7, 0x0000 }, ++ { 0x2143, 0x0001 }, ++ { 0x40a3, 0x0001 }, ++ }, ++ }, { ++ 184000000, { ++ { 0x0073, 0x0001 }, ++ { 0x2146, 0x0002 }, ++ { 0x4062, 0x0002 }, ++ }, ++ }, { ++ 340000000, { ++ { 0x0052, 0x0003 }, ++ { 0x214d, 0x0003 }, ++ { 0x4065, 0x0003 }, ++ }, ++ }, { ++ 600000000, { ++ { 0x0040, 0x0003 }, ++ { 0x3b4c, 0x0003 }, ++ { 0x5a65, 0x0003 }, ++ }, ++ }, { ++ ~0UL, { ++ { 0x0000, 0x0000 }, ++ { 0x0000, 0x0000 }, ++ { 0x0000, 0x0000 }, ++ }, ++ } ++}; ++ + static const struct dw_hdmi_curr_ctrl rockchip_cur_ctr[] = { + /* pixelclk bpp8 bpp10 bpp12 */ + { +@@ -479,6 +519,7 @@ static struct rockchip_hdmi_chip_data rk3288_chip_data = { + static const struct dw_hdmi_plat_data rk3288_hdmi_drv_data = { + .mode_valid = dw_hdmi_rockchip_mode_valid, + .mpll_cfg = rockchip_mpll_cfg, ++ .mpll_cfg_420 = rockchip_rk3288w_mpll_cfg_420, + .cur_ctr = rockchip_cur_ctr, + .phy_config = rockchip_phy_config, + .phy_data = &rk3288_chip_data, + +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Jonas Karlman +Date: Fri, 20 Dec 2019 08:12:42 +0000 +Subject: [PATCH] drm/rockchip: dw-hdmi: add bridge and switch to + drm_bridge_funcs + +Switch the dw-hdmi driver to drm_bridge_funcs by implementing +a new local bridge, connecting it to the dw-hdmi bridge. + +Also enable bridge format negotiation by implementing +atomic_get_input_bus_fmts and support for 8-bit RGB 4:4:4. + +Signed-off-by: Jonas Karlman +--- + drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c | 118 ++++++++++++++------ + 1 file changed, 81 insertions(+), 37 deletions(-) + +diff --git a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c +index 66fee351f4a7..d6d8f3335813 100644 +--- a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c ++++ b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c +@@ -5,6 +5,7 @@ + + #include + #include ++#include + #include + #include + #include +@@ -72,6 +73,7 @@ struct rockchip_hdmi_chip_data { + struct rockchip_hdmi { + struct device *dev; + struct regmap *regmap; ++ struct drm_bridge bridge; + struct rockchip_encoder encoder; + const struct rockchip_hdmi_chip_data *chip_data; + struct clk *ref_clk; +@@ -82,11 +84,9 @@ struct rockchip_hdmi { + struct phy *phy; + }; + +-static struct rockchip_hdmi *to_rockchip_hdmi(struct drm_encoder *encoder) ++static struct rockchip_hdmi *to_rockchip_hdmi(struct drm_bridge *bridge) + { +- struct rockchip_encoder *rkencoder = to_rockchip_encoder(encoder); +- +- return container_of(rkencoder, struct rockchip_hdmi, encoder); ++ return container_of(bridge, struct rockchip_hdmi, bridge); + } + + static const struct dw_hdmi_mpll_config rockchip_mpll_cfg[] = { +@@ -335,31 +335,21 @@ dw_hdmi_rockchip_mode_valid(struct dw_hdmi *hdmi, void *data, + + return MODE_OK; + } +- +-static void dw_hdmi_rockchip_encoder_disable(struct drm_encoder *encoder) ++static void ++dw_hdmi_rockchip_bridge_mode_set(struct drm_bridge *bridge, ++ const struct drm_display_mode *mode, ++ const struct drm_display_mode *adjusted_mode) + { +-} ++ struct rockchip_hdmi *hdmi = to_rockchip_hdmi(bridge); + +-static bool +-dw_hdmi_rockchip_encoder_mode_fixup(struct drm_encoder *encoder, +- const struct drm_display_mode *mode, +- struct drm_display_mode *adj_mode) +-{ +- return true; ++ clk_set_rate(hdmi->ref_clk, adjusted_mode->clock * 1000); + } + +-static void dw_hdmi_rockchip_encoder_mode_set(struct drm_encoder *encoder, +- struct drm_display_mode *mode, +- struct drm_display_mode *adj_mode) ++static void dw_hdmi_rockchip_bridge_enable(struct drm_bridge *bridge) + { +- struct rockchip_hdmi *hdmi = to_rockchip_hdmi(encoder); ++ struct rockchip_hdmi *hdmi = to_rockchip_hdmi(bridge); ++ struct drm_encoder *encoder = bridge->encoder; + +- clk_set_rate(hdmi->ref_clk, adj_mode->clock * 1000); +-} +- +-static void dw_hdmi_rockchip_encoder_enable(struct drm_encoder *encoder) +-{ +- struct rockchip_hdmi *hdmi = to_rockchip_hdmi(encoder); + u32 val; + int ret; + +@@ -387,10 +377,21 @@ static void dw_hdmi_rockchip_encoder_enable(struct drm_encoder *encoder) + ret ? "LIT" : "BIG"); + } + ++static bool is_rgb(u32 format) ++{ ++ switch (format) { ++ case MEDIA_BUS_FMT_RGB888_1X24: ++ return true; ++ default: ++ return false; ++ } ++} ++ + static int +-dw_hdmi_rockchip_encoder_atomic_check(struct drm_encoder *encoder, +- struct drm_crtc_state *crtc_state, +- struct drm_connector_state *conn_state) ++dw_hdmi_rockchip_bridge_atomic_check(struct drm_bridge *bridge, ++ struct drm_bridge_state *bridge_state, ++ struct drm_crtc_state *crtc_state, ++ struct drm_connector_state *conn_state) + { + struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc_state); + +@@ -400,12 +401,38 @@ dw_hdmi_rockchip_encoder_atomic_check(struct drm_encoder *encoder, + return 0; + } + +-static const struct drm_encoder_helper_funcs dw_hdmi_rockchip_encoder_helper_funcs = { +- .mode_fixup = dw_hdmi_rockchip_encoder_mode_fixup, +- .mode_set = dw_hdmi_rockchip_encoder_mode_set, +- .enable = dw_hdmi_rockchip_encoder_enable, +- .disable = dw_hdmi_rockchip_encoder_disable, +- .atomic_check = dw_hdmi_rockchip_encoder_atomic_check, ++static u32 *dw_hdmi_rockchip_get_input_bus_fmts(struct drm_bridge *bridge, ++ struct drm_bridge_state *bridge_state, ++ struct drm_crtc_state *crtc_state, ++ struct drm_connector_state *conn_state, ++ u32 output_fmt, ++ unsigned int *num_input_fmts) ++{ ++ u32 *input_fmt; ++ ++ *num_input_fmts = 0; ++ ++ if (!is_rgb(output_fmt)) ++ return NULL; ++ ++ input_fmt = kzalloc(sizeof(*input_fmt), GFP_KERNEL); ++ if (!input_fmt) ++ return NULL; ++ ++ *num_input_fmts = 1; ++ *input_fmt = output_fmt; ++ ++ return input_fmt; ++} ++ ++static const struct drm_bridge_funcs dw_hdmi_rockchip_bridge_funcs = { ++ .mode_set = dw_hdmi_rockchip_bridge_mode_set, ++ .enable = dw_hdmi_rockchip_bridge_enable, ++ .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state, ++ .atomic_destroy_state = drm_atomic_helper_bridge_destroy_state, ++ .atomic_get_input_bus_fmts = dw_hdmi_rockchip_get_input_bus_fmts, ++ .atomic_check = dw_hdmi_rockchip_bridge_atomic_check, ++ .atomic_reset = drm_atomic_helper_bridge_reset, + }; + + static int dw_hdmi_rockchip_genphy_init(struct dw_hdmi *dw_hdmi, void *data, +@@ -602,6 +629,7 @@ static int dw_hdmi_rockchip_bind(struct device *dev, struct device *master, + struct dw_hdmi_plat_data *plat_data; + const struct of_device_id *match; + struct drm_device *drm = data; ++ struct drm_bridge *next_bridge; + struct drm_encoder *encoder; + struct rockchip_hdmi *hdmi; + int ret; +@@ -679,20 +707,21 @@ static int dw_hdmi_rockchip_bind(struct device *dev, struct device *master, + RK3568_HDMI_SCLIN_MSK)); + } + +- drm_encoder_helper_add(encoder, &dw_hdmi_rockchip_encoder_helper_funcs); +- + ret = drm_simple_encoder_init(drm, encoder, DRM_MODE_ENCODER_TMDS); + if (ret) { + DRM_DEV_ERROR(hdmi->dev, "Failed to init encoder: %d\n", ret); + goto err_disable_clk; + } + ++ hdmi->bridge.funcs = &dw_hdmi_rockchip_bridge_funcs; ++ drm_bridge_attach(encoder, &hdmi->bridge, NULL, 0); ++ + platform_set_drvdata(pdev, hdmi); + +- hdmi->hdmi = dw_hdmi_bind(pdev, encoder, plat_data); ++ hdmi->hdmi = dw_hdmi_probe(pdev, plat_data); + + /* +- * If dw_hdmi_bind() fails we'll never call dw_hdmi_unbind(), ++ * If dw_hdmi_probe() fails we'll never call dw_hdmi_unbind(), + * which would have called the encoder cleanup. Do it manually. + */ + if (IS_ERR(hdmi->hdmi)) { +@@ -700,8 +729,23 @@ static int dw_hdmi_rockchip_bind(struct device *dev, struct device *master, + goto err_bind; + } + ++ next_bridge = of_drm_find_bridge(pdev->dev.of_node); ++ if (!next_bridge) { ++ ret = -EPROBE_DEFER; ++ goto err_dw_hdmi_remove; ++ } ++ ++ ret = drm_bridge_attach(encoder, next_bridge, &hdmi->bridge, 0); ++ if (ret) { ++ if (ret != -EPROBE_DEFER) ++ DRM_DEV_ERROR(hdmi->dev, "Failed to attach dw-hdmi bridge: %d\n", ret); ++ goto err_dw_hdmi_remove; ++ } ++ + return 0; + ++err_dw_hdmi_remove: ++ dw_hdmi_remove(hdmi->hdmi); + err_bind: + drm_encoder_cleanup(encoder); + err_disable_clk: +@@ -719,7 +763,7 @@ static void dw_hdmi_rockchip_unbind(struct device *dev, struct device *master, + { + struct rockchip_hdmi *hdmi = dev_get_drvdata(dev); + +- dw_hdmi_unbind(hdmi->hdmi); ++ dw_hdmi_remove(hdmi->hdmi); + drm_encoder_cleanup(&hdmi->encoder.encoder); + clk_disable_unprepare(hdmi->ref_clk); + + +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Jonas Karlman +Date: Fri, 9 Oct 2020 15:29:27 +0000 +Subject: [PATCH] drm/rockchip: vop: add immutable zpos property + +Signed-off-by: Jonas Karlman +--- + drivers/gpu/drm/rockchip/rockchip_drm_fb.c | 2 ++ + drivers/gpu/drm/rockchip/rockchip_drm_vop.c | 6 ++++-- + 2 files changed, 6 insertions(+), 2 deletions(-) + +diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_fb.c b/drivers/gpu/drm/rockchip/rockchip_drm_fb.c +index 092bf863110b..e2ee0d6a8d55 100644 +--- a/drivers/gpu/drm/rockchip/rockchip_drm_fb.c ++++ b/drivers/gpu/drm/rockchip/rockchip_drm_fb.c +@@ -133,6 +133,8 @@ void rockchip_drm_mode_config_init(struct drm_device *dev) + dev->mode_config.max_width = 4096; + dev->mode_config.max_height = 4096; + ++ dev->mode_config.normalize_zpos = true; ++ + dev->mode_config.funcs = &rockchip_drm_mode_config_funcs; + dev->mode_config.helper_private = &rockchip_mode_config_helpers; + +diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c +index 30e252ba7184..897f7980ee5d 100644 +--- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c ++++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c +@@ -1917,7 +1917,7 @@ static irqreturn_t vop_isr(int irq, void *data) + return ret; + } + +-static void vop_plane_add_properties(struct drm_plane *plane, ++static void vop_plane_add_properties(struct drm_plane *plane, int zpos, + const struct vop_win_data *win_data) + { + unsigned int flags = 0; +@@ -1927,6 +1927,8 @@ static void vop_plane_add_properties(struct drm_plane *plane, + if (flags) + drm_plane_create_rotation_property(plane, DRM_MODE_ROTATE_0, + DRM_MODE_ROTATE_0 | flags); ++ ++ drm_plane_create_zpos_immutable_property(plane, zpos); + } + + static int vop_create_crtc(struct vop *vop) +@@ -1967,7 +1969,7 @@ static int vop_create_crtc(struct vop *vop) + + plane = &vop_win->base; + drm_plane_helper_add(plane, &plane_helper_funcs); +- vop_plane_add_properties(plane, win_data); ++ vop_plane_add_properties(plane, i, win_data); + if (plane->type == DRM_PLANE_TYPE_PRIMARY) + primary = plane; + else if (plane->type == DRM_PLANE_TYPE_CURSOR) + +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Jonas Karlman +Date: Sat, 10 Oct 2020 09:20:44 +0000 +Subject: [PATCH] drm/rockchip: vop: add plane color properties + +Signed-off-by: Jonas Karlman +--- + drivers/gpu/drm/rockchip/rockchip_drm_vop.c | 32 +++++++++++++++++++-- + 1 file changed, 30 insertions(+), 2 deletions(-) + +diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c +index 897f7980ee5d..eadf1b0f1704 100644 +--- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c ++++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c +@@ -1917,8 +1917,23 @@ static irqreturn_t vop_isr(int irq, void *data) + return ret; + } + ++static bool plane_supports_yuv_format(const struct drm_plane *plane) ++{ ++ const struct drm_format_info *info; ++ int i; ++ ++ for (i = 0; i < plane->format_count; i++) { ++ info = drm_format_info(plane->format_types[i]); ++ if (info->is_yuv) ++ return true; ++ } ++ ++ return false; ++} ++ + static void vop_plane_add_properties(struct drm_plane *plane, int zpos, +- const struct vop_win_data *win_data) ++ const struct vop_win_data *win_data, ++ const struct vop_data *vop_data) + { + unsigned int flags = 0; + +@@ -1929,6 +1944,19 @@ static void vop_plane_add_properties(struct drm_plane *plane, int zpos, + DRM_MODE_ROTATE_0 | flags); + + drm_plane_create_zpos_immutable_property(plane, zpos); ++ ++ if (!plane_supports_yuv_format(plane)) ++ return; ++ ++ flags = BIT(DRM_COLOR_YCBCR_BT601) | BIT(DRM_COLOR_YCBCR_BT709); ++ if (vop_data->feature & VOP_FEATURE_OUTPUT_RGB10) ++ flags |= BIT(DRM_COLOR_YCBCR_BT2020); ++ ++ drm_plane_create_color_properties(plane, flags, ++ BIT(DRM_COLOR_YCBCR_LIMITED_RANGE) | ++ BIT(DRM_COLOR_YCBCR_FULL_RANGE), ++ DRM_COLOR_YCBCR_BT601, ++ DRM_COLOR_YCBCR_LIMITED_RANGE); + } + + static int vop_create_crtc(struct vop *vop) +@@ -1969,7 +1997,7 @@ static int vop_create_crtc(struct vop *vop) + + plane = &vop_win->base; + drm_plane_helper_add(plane, &plane_helper_funcs); +- vop_plane_add_properties(plane, i, win_data); ++ vop_plane_add_properties(plane, i, win_data, vop_data); + if (plane->type == DRM_PLANE_TYPE_PRIMARY) + primary = plane; + else if (plane->type == DRM_PLANE_TYPE_CURSOR) + +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Nickey Yang +Date: Mon, 17 Jul 2017 16:35:34 +0800 +Subject: [PATCH] HACK: clk: rockchip: rk3288: dedicate npll for vopb and hdmi + use + +MINIARM: set npll be used for hdmi only + +Signed-off-by: Nickey Yang +Signed-off-by: Jonas Karlman +Signed-off-by: Alex Bee +--- + arch/arm/boot/dts/rockchip/rk3288.dtsi | 2 ++ + drivers/clk/rockchip/clk-rk3288.c | 9 +++++---- + 2 files changed, 7 insertions(+), 4 deletions(-) + +diff --git a/arch/arm/boot/dts/rockchip/rk3288.dtsi b/arch/arm/boot/dts/rockchip/rk3288.dtsi +index c60eacab8a79..d1ae42757242 100644 +--- a/arch/arm/boot/dts/rockchip/rk3288.dtsi ++++ b/arch/arm/boot/dts/rockchip/rk3288.dtsi +@@ -1026,6 +1026,8 @@ vopb: vop@ff930000 { + resets = <&cru SRST_LCDC0_AXI>, <&cru SRST_LCDC0_AHB>, <&cru SRST_LCDC0_DCLK>; + reset-names = "axi", "ahb", "dclk"; + iommus = <&vopb_mmu>; ++ assigned-clocks = <&cru DCLK_VOP0>; ++ assigned-clock-parents = <&cru PLL_NPLL>; + status = "disabled"; + + vopb_out: port { +diff --git a/drivers/clk/rockchip/clk-rk3288.c b/drivers/clk/rockchip/clk-rk3288.c +index baa5aebd3277..5cfcbaaa154e 100644 +--- a/drivers/clk/rockchip/clk-rk3288.c ++++ b/drivers/clk/rockchip/clk-rk3288.c +@@ -195,8 +195,9 @@ PNAME(mux_ddrphy_p) = { "dpll_ddr", "gpll_ddr" }; + PNAME(mux_aclk_cpu_src_p) = { "cpll_aclk_cpu", "gpll_aclk_cpu" }; + + PNAME(mux_pll_src_cpll_gpll_p) = { "cpll", "gpll" }; +-PNAME(mux_pll_src_npll_cpll_gpll_p) = { "npll", "cpll", "gpll" }; +-PNAME(mux_pll_src_cpll_gpll_npll_p) = { "cpll", "gpll", "npll" }; ++PNAME(mux_pll_src_npll_cpll_gpll_p) = { "prevent:npll", "cpll", "gpll" }; ++PNAME(mux_pll_src_cpll_gpll_npll_p) = { "cpll", "gpll", "prevent:npll" }; ++PNAME(vop0_mux_pll_src_cpll_gpll_npll_p) = { "prevent:cpll", "prevent:gpll", "npll" }; + PNAME(mux_pll_src_cpll_gpll_usb480m_p) = { "cpll", "gpll", "unstable:usbphy480m_src" }; + PNAME(mux_pll_src_cpll_gll_usb_npll_p) = { "cpll", "gpll", "unstable:usbphy480m_src", "npll" }; + +@@ -232,7 +233,7 @@ static struct rockchip_pll_clock rk3288_pll_clks[] __initdata = { + [gpll] = PLL(pll_rk3066, PLL_GPLL, "gpll", mux_pll_p, 0, RK3288_PLL_CON(12), + RK3288_MODE_CON, 12, 8, ROCKCHIP_PLL_SYNC_RATE, rk3288_pll_rates), + [npll] = PLL(pll_rk3066, PLL_NPLL, "npll", mux_pll_p, 0, RK3288_PLL_CON(16), +- RK3288_MODE_CON, 14, 9, ROCKCHIP_PLL_SYNC_RATE, rk3288_pll_rates), ++ RK3288_MODE_CON, 14, 9, 0, rk3288_pll_rates), + }; + + static struct clk_div_table div_hclk_cpu_t[] = { +@@ -442,7 +443,7 @@ static struct rockchip_clk_branch rk3288_clk_branches[] __initdata = { + RK3288_CLKSEL_CON(30), 14, 2, MFLAGS, 8, 5, DFLAGS, + RK3288_CLKGATE_CON(3), 4, GFLAGS), + +- COMPOSITE(DCLK_VOP0, "dclk_vop0", mux_pll_src_cpll_gpll_npll_p, 0, ++ COMPOSITE(DCLK_VOP0, "dclk_vop0", vop0_mux_pll_src_cpll_gpll_npll_p, CLK_SET_RATE_NO_REPARENT | CLK_SET_RATE_PARENT, + RK3288_CLKSEL_CON(27), 0, 2, MFLAGS, 8, 8, DFLAGS, + RK3288_CLKGATE_CON(3), 1, GFLAGS), + COMPOSITE(DCLK_VOP1, "dclk_vop1", mux_pll_src_cpll_gpll_npll_p, 0, + +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Jonas Karlman +Date: Sat, 4 Aug 2018 14:51:14 +0200 +Subject: [PATCH] HACK: clk: rockchip: rk3288: use npll table to to improve + HDMI compatibility + +Based on https://github.com/TinkerBoard/debian_kernel/commit/3d90870530b8a2901681f7b7fa598ee7381e49f3 + +Signed-off-by: Jonas Karlman +Signed-off-by: Alex Bee +--- + drivers/clk/rockchip/clk-rk3288.c | 39 ++++++++++++++++++++++++++++++- + 1 file changed, 38 insertions(+), 1 deletion(-) + +diff --git a/drivers/clk/rockchip/clk-rk3288.c b/drivers/clk/rockchip/clk-rk3288.c +index 5cfcbaaa154e..fa1c6e646bdf 100644 +--- a/drivers/clk/rockchip/clk-rk3288.c ++++ b/drivers/clk/rockchip/clk-rk3288.c +@@ -121,6 +121,43 @@ static struct rockchip_pll_rate_table rk3288_pll_rates[] = { + { /* sentinel */ }, + }; + ++static struct rockchip_pll_rate_table rk3288_npll_rates[] = { ++ RK3066_PLL_RATE_NB(594000000, 1, 198, 8, 1), ++ RK3066_PLL_RATE_NB(585000000, 6, 585, 4, 32), ++ RK3066_PLL_RATE_NB(432000000, 3, 216, 4, 32), ++ RK3066_PLL_RATE_NB(426000000, 3, 213, 4, 32), ++ RK3066_PLL_RATE_NB(400000000, 1, 100, 6, 32), ++ RK3066_PLL_RATE(348500000, 8, 697, 6), ++ RK3066_PLL_RATE_NB(342000000, 3, 171, 4, 32), ++ RK3066_PLL_RATE_NB(297000000, 2, 198, 8, 16), ++ RK3066_PLL_RATE_NB(270000000, 1, 135, 12, 32), ++ RK3066_PLL_RATE_NB(260000000, 1, 130, 12, 32), ++ RK3066_PLL_RATE(241500000, 2, 161, 8), ++ RK3066_PLL_RATE(162000000, 1, 81, 12), ++ RK3066_PLL_RATE(154000000, 6, 539, 14), ++ RK3066_PLL_RATE_NB(148500000, 1, 99, 16, 32), ++ RK3066_PLL_RATE(148352000, 13, 1125, 14), ++ RK3066_PLL_RATE_NB(146250000, 6, 585, 16, 32), ++ RK3066_PLL_RATE(121750000, 6, 487, 16), ++ RK3066_PLL_RATE(119000000, 3, 238, 16), ++ RK3066_PLL_RATE_NB(108000000, 1, 54, 12, 32), ++ RK3066_PLL_RATE_NB(106500000, 4, 213, 12, 32), ++ RK3066_PLL_RATE(101000000, 3, 202, 16), ++ RK3066_PLL_RATE(88750000, 6, 355, 16), ++ RK3066_PLL_RATE_NB(85500000, 4, 171, 12, 32), ++ RK3066_PLL_RATE(83500000, 3, 167, 16), ++ RK3066_PLL_RATE(79500000, 1, 53, 16), ++ RK3066_PLL_RATE_NB(74250000, 4, 198, 16, 32), ++ RK3066_PLL_RATE(74176000, 26, 1125, 14), ++ RK3066_PLL_RATE(72000000, 1, 48, 16), ++ RK3066_PLL_RATE(71000000, 3, 142, 16), ++ RK3066_PLL_RATE(68250000, 2, 91, 16), ++ RK3066_PLL_RATE(65000000, 3, 130, 16), ++ RK3066_PLL_RATE(40000000, 3, 80, 16), ++ RK3066_PLL_RATE(33750000, 2, 45, 16), ++ { /* sentinel */ }, ++}; ++ + #define RK3288_DIV_ACLK_CORE_M0_MASK 0xf + #define RK3288_DIV_ACLK_CORE_M0_SHIFT 0 + #define RK3288_DIV_ACLK_CORE_MP_MASK 0xf +@@ -233,7 +270,7 @@ static struct rockchip_pll_clock rk3288_pll_clks[] __initdata = { + [gpll] = PLL(pll_rk3066, PLL_GPLL, "gpll", mux_pll_p, 0, RK3288_PLL_CON(12), + RK3288_MODE_CON, 12, 8, ROCKCHIP_PLL_SYNC_RATE, rk3288_pll_rates), + [npll] = PLL(pll_rk3066, PLL_NPLL, "npll", mux_pll_p, 0, RK3288_PLL_CON(16), +- RK3288_MODE_CON, 14, 9, 0, rk3288_pll_rates), ++ RK3288_MODE_CON, 14, 9, 0, rk3288_npll_rates), + }; + + static struct clk_div_table div_hclk_cpu_t[] = { + +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Jonas Karlman +Date: Mon, 25 May 2020 20:36:45 +0000 +Subject: [PATCH] HACK: clk: rockchip: rk3399: dedicate vpll for vopb and hdmi + use + +Rockchip PLLs are kown provide the least jitter for +vco rates between 800 MHz and 2 GHz. I added the +rates for VPLL which are used for VOPs dclk and there- +fore HDMI phy in that manner and used the rates which +require the lowest frac divs. +Additionally I added some rates which are useful to +provide additional VESA and non-VESA rates for HDMI +output. + +Signed-off-by: Jonas Karlman +Signed-off-by: Alex Bee +--- + drivers/clk/rockchip/clk-rk3399.c | 49 ++++++++++++++++++++++++++----- + 1 file changed, 42 insertions(+), 7 deletions(-) + +diff --git a/drivers/clk/rockchip/clk-rk3399.c b/drivers/clk/rockchip/clk-rk3399.c +index 306910a3a0d3..436d2789611c 100644 +--- a/drivers/clk/rockchip/clk-rk3399.c ++++ b/drivers/clk/rockchip/clk-rk3399.c +@@ -105,6 +105,39 @@ static struct rockchip_pll_rate_table rk3399_pll_rates[] = { + { /* sentinel */ }, + }; + ++static struct rockchip_pll_rate_table rk3399_vpll_rates[] = { ++ /* _mhz, _refdiv, _fbdiv, _postdiv1, _postdiv2, _dsmpd, _frac */ ++ RK3036_PLL_RATE( 594000000, 1, 74, 3, 1, 0, 4194304), /* vco = 1782000000 fout = 594000000 */ ++ RK3036_PLL_RATE( 593406592, 1, 74, 3, 1, 0, 2949838), /* vco = 1780219777 fout = 593406592.36908 */ ++ RK3036_PLL_RATE( 319750000, 1, 79, 6, 1, 0, 15728640), /* vco = 1918500000 fout = 319750000 */ ++ RK3036_PLL_RATE( 297000000, 1, 74, 6, 1, 0, 4194304), /* vco = 1782000000 fout = 297000000 */ ++ RK3036_PLL_RATE( 296703296, 1, 74, 6, 1, 0, 2949838), /* vco = 1780219777 fout = 296703296.18454 */ ++ RK3036_PLL_RATE( 241500000, 1, 60, 6, 1, 0, 6291456), /* vco = 1449000000 fout = 241500000 */ ++ RK3036_PLL_RATE( 162000000, 1, 67, 5, 2, 0, 8388608), /* vco = 1620000000 fout = 162000000 */ ++ RK3036_PLL_RATE( 148500000, 1, 74, 6, 2, 0, 4194304), /* vco = 1782000000 fout = 148500000*/ ++ RK3036_PLL_RATE( 148351648, 1, 74, 6, 2, 0, 2949838), /* vco = 1780219777 fout = 148351648.09227 */ ++ RK3036_PLL_RATE( 136750000, 1, 68, 2, 6, 0, 6291456), /* vco = 1641000000 fout = 136750000 */ ++ RK3036_PLL_RATE( 135000000, 1, 56, 5, 2, 0, 4194304), /* vco = 1350000000 fout = 135000000 */ ++ RK3036_PLL_RATE( 119000000, 1, 59, 6, 2, 0, 8388608), /* vco = 1428000000 fout = 119000000 */ ++ RK3036_PLL_RATE( 108000000, 1, 63, 7, 2, 1, 0), /* vco = 1512000000 fout = 108000000 */ ++ RK3036_PLL_RATE( 106500000, 1, 62, 7, 2, 0, 2097152), /* vco = 1491000000 fout = 106500000 */ ++ RK3036_PLL_RATE( 88750000, 1, 55, 5, 3, 0, 7864320), /* vco = 1331250000 fout = 88750000 */ ++ RK3036_PLL_RATE( 85500000, 1, 57, 4, 4, 1, 0), /* vco = 1368000000 fout = 85500000 */ ++ RK3036_PLL_RATE( 78750000, 1, 59, 6, 3, 0, 1048576), /* vco = 1417500000 fout = 78750000 */ ++ RK3036_PLL_RATE( 74250000, 1, 74, 6, 4, 0, 4194304), /* vco = 1782000000 fout = 74250000 */ ++ RK3036_PLL_RATE( 74175824, 1, 74, 6, 4, 0, 2949838), /* vco = 1780219777 fout = 74175824.046135 */ ++ RK3036_PLL_RATE( 71000000, 1, 71, 6, 4, 1, 0), /* vco = 1704000000 fout = 71000000 */ ++ RK3036_PLL_RATE( 65000000, 1, 65, 6, 4, 0, 0), /* vco = 1560000000 fout = 65000000 */ ++ RK3036_PLL_RATE( 59340659, 1, 59, 6, 4, 0, 5715310), /* vco = 1424175816 fout = 59340659.022331 */ ++ RK3036_PLL_RATE( 54000000, 1, 63, 7, 4, 1, 0), /* vco = 1512000000 fout = 54000000 */ ++ RK3036_PLL_RATE( 49500000, 1, 72, 5, 7, 0, 3145728), /* vco = 1732500000 fout = 49500000 */ ++ RK3036_PLL_RATE( 40000000, 1, 70, 7, 6, 1, 0), /* vco = 1680000000 fout = 40000000 */ ++ RK3036_PLL_RATE( 31500000, 1, 55, 7, 6, 0, 2097152), /* vco = 1323000000 fout = 31500000 */ ++ RK3036_PLL_RATE( 27000000, 1, 55, 7, 7, 0, 2097152), /* vco = 1323000000 fout = 27000000 */ ++ RK3036_PLL_RATE( 26973026, 1, 55, 7, 7, 0, 1173214), /* vco = 1321678296 fout = 26973026.450799 */ ++ { /* sentinel */ }, ++}; ++ + /* CRU parents */ + PNAME(mux_pll_p) = { "xin24m", "xin32k" }; + +@@ -123,7 +156,7 @@ PNAME(mux_ddrclk_p) = { "clk_ddrc_lpll_src", + PNAME(mux_aclk_cci_p) = { "cpll_aclk_cci_src", + "gpll_aclk_cci_src", + "npll_aclk_cci_src", +- "vpll_aclk_cci_src" }; ++ "prevent:vpll" }; + PNAME(mux_cci_trace_p) = { "cpll_cci_trace", + "gpll_cci_trace" }; + PNAME(mux_cs_p) = { "cpll_cs", "gpll_cs", +@@ -149,10 +182,12 @@ PNAME(mux_pll_src_cpll_gpll_npll_upll_24m_p) = { "cpll", "gpll", "npll", + PNAME(mux_pll_src_cpll_gpll_npll_ppll_upll_24m_p) = { "cpll", "gpll", "npll", + "ppll", "upll", "xin24m" }; + +-PNAME(mux_pll_src_vpll_cpll_gpll_p) = { "vpll", "cpll", "gpll" }; +-PNAME(mux_pll_src_vpll_cpll_gpll_npll_p) = { "vpll", "cpll", "gpll", ++PNAME(mux_pll_src_vpll_cpll_gpll_p) = { "prevent:vpll", "cpll", "gpll" }; ++PNAME(vop0_mux_pll_src_vpll_cpll_gpll_p) = { "vpll", "prevent:cpll", "prevent:gpll" }; ++ ++PNAME(mux_pll_src_vpll_cpll_gpll_npll_p) = { "prevent:vpll", "cpll", "gpll", + "npll" }; +-PNAME(mux_pll_src_vpll_cpll_gpll_24m_p) = { "vpll", "cpll", "gpll", ++PNAME(mux_pll_src_vpll_cpll_gpll_24m_p) = { "prevent:vpll", "cpll", "gpll", + "xin24m" }; + + PNAME(mux_dclk_vop0_p) = { "dclk_vop0_div", +@@ -229,7 +264,7 @@ static struct rockchip_pll_clock rk3399_pll_clks[] __initdata = { + [npll] = PLL(pll_rk3399, PLL_NPLL, "npll", mux_pll_p, 0, RK3399_PLL_CON(40), + RK3399_PLL_CON(43), 8, 31, ROCKCHIP_PLL_SYNC_RATE, rk3399_pll_rates), + [vpll] = PLL(pll_rk3399, PLL_VPLL, "vpll", mux_pll_p, 0, RK3399_PLL_CON(48), +- RK3399_PLL_CON(51), 8, 31, ROCKCHIP_PLL_SYNC_RATE, rk3399_pll_rates), ++ RK3399_PLL_CON(51), 8, 31, ROCKCHIP_PLL_SYNC_RATE, rk3399_vpll_rates), + }; + + static struct rockchip_pll_clock rk3399_pmu_pll_clks[] __initdata = { +@@ -279,7 +314,7 @@ static struct rockchip_clk_branch rk3399_uart4_pmu_fracmux __initdata = + RK3399_PMU_CLKSEL_CON(5), 8, 2, MFLAGS); + + static struct rockchip_clk_branch rk3399_dclk_vop0_fracmux __initdata = +- MUX(DCLK_VOP0, "dclk_vop0", mux_dclk_vop0_p, CLK_SET_RATE_PARENT, ++ MUX(DCLK_VOP0, "dclk_vop0", mux_dclk_vop0_p, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, + RK3399_CLKSEL_CON(49), 11, 1, MFLAGS); + + static struct rockchip_clk_branch rk3399_dclk_vop1_fracmux __initdata = +@@ -1162,7 +1197,7 @@ static struct rockchip_clk_branch rk3399_clk_branches[] __initdata = { + GATE(HCLK_VOP0_NOC, "hclk_vop0_noc", "hclk_vop0_pre", CLK_IGNORE_UNUSED, + RK3399_CLKGATE_CON(28), 0, GFLAGS), + +- COMPOSITE(DCLK_VOP0_DIV, "dclk_vop0_div", mux_pll_src_vpll_cpll_gpll_p, 0, ++ COMPOSITE(DCLK_VOP0_DIV, "dclk_vop0_div", vop0_mux_pll_src_vpll_cpll_gpll_p, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, + RK3399_CLKSEL_CON(49), 8, 2, MFLAGS, 0, 8, DFLAGS, + RK3399_CLKGATE_CON(10), 12, GFLAGS), + + +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Jonas Karlman +Date: Sun, 19 Jul 2020 16:35:11 +0000 +Subject: [PATCH] HACK: dts: rockchip: do not use vopl for hdmi + +--- + arch/arm/boot/dts/rockchip/rk3288.dtsi | 9 --------- + arch/arm64/boot/dts/rockchip/rk3399-base.dtsi | 9 --------- + 2 files changed, 18 deletions(-) + +diff --git a/arch/arm/boot/dts/rockchip/rk3288.dtsi b/arch/arm/boot/dts/rockchip/rk3288.dtsi +index d1ae42757242..7b2cde230b87 100644 +--- a/arch/arm/boot/dts/rockchip/rk3288.dtsi ++++ b/arch/arm/boot/dts/rockchip/rk3288.dtsi +@@ -1083,11 +1083,6 @@ vopl_out: port { + #address-cells = <1>; + #size-cells = <0>; + +- vopl_out_hdmi: endpoint@0 { +- reg = <0>; +- remote-endpoint = <&hdmi_in_vopl>; +- }; +- + vopl_out_edp: endpoint@1 { + reg = <1>; + remote-endpoint = <&edp_in_vopl>; +@@ -1227,10 +1222,6 @@ hdmi_in_vopb: endpoint@0 { + remote-endpoint = <&vopb_out_hdmi>; + }; + +- hdmi_in_vopl: endpoint@1 { +- reg = <1>; +- remote-endpoint = <&vopl_out_hdmi>; +- }; + }; + }; + +diff --git a/arch/arm64/boot/dts/rockchip/rk3399-base.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-base.dtsi +index 92c2207e686c..980b12cb0a49 100644 +--- a/arch/arm64/boot/dts/rockchip/rk3399-base.dtsi ++++ b/arch/arm64/boot/dts/rockchip/rk3399-base.dtsi +@@ -1846,11 +1846,6 @@ vopl_out_edp: endpoint@1 { + remote-endpoint = <&edp_in_vopl>; + }; + +- vopl_out_hdmi: endpoint@2 { +- reg = <2>; +- remote-endpoint = <&hdmi_in_vopl>; +- }; +- + vopl_out_mipi1: endpoint@3 { + reg = <3>; + remote-endpoint = <&mipi1_in_vopl>; +@@ -2048,10 +2043,6 @@ hdmi_in_vopb: endpoint@0 { + reg = <0>; + remote-endpoint = <&vopb_out_hdmi>; + }; +- hdmi_in_vopl: endpoint@1 { +- reg = <1>; +- remote-endpoint = <&vopl_out_hdmi>; +- }; + }; + }; + }; + +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Jonas Karlman +Date: Fri, 20 Dec 2019 08:12:43 +0000 +Subject: [PATCH] WIP: drm/bridge: dw-hdmi: limit mode and bus format to + max_tmds_clock + +--- + drivers/gpu/drm/bridge/synopsys/dw-hdmi.c | 120 ++++++++++++++-------- + 1 file changed, 76 insertions(+), 44 deletions(-) + +diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c +index a2d101ebf7a7..7f6ffbc3e7b2 100644 +--- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c ++++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c +@@ -2003,6 +2003,21 @@ static void hdmi_config_drm_infoframe(struct dw_hdmi *hdmi, + HDMI_FC_PACKET_TX_EN_DRM_MASK, HDMI_FC_PACKET_TX_EN); + } + ++static unsigned int ++hdmi_get_tmdsclock(unsigned int bus_format, unsigned int pixelclock) ++{ ++ int color_depth = hdmi_bus_fmt_color_depth(bus_format); ++ unsigned int tmdsclock = pixelclock; ++ ++ if (!hdmi_bus_fmt_is_yuv422(bus_format) && color_depth > 8) ++ tmdsclock = (u64)pixelclock * color_depth / 8; ++ ++ if (hdmi_bus_fmt_is_yuv420(bus_format)) ++ tmdsclock /= 2; ++ ++ return tmdsclock; ++} ++ + static void hdmi_av_composer(struct dw_hdmi *hdmi, + const struct drm_display_info *display, + const struct drm_display_mode *mode) +@@ -2014,29 +2029,11 @@ static void hdmi_av_composer(struct dw_hdmi *hdmi, + unsigned int vdisplay, hdisplay; + + vmode->mpixelclock = mode->clock * 1000; ++ vmode->mtmdsclock = ++ hdmi_get_tmdsclock(hdmi->hdmi_data.enc_out_bus_format, ++ vmode->mpixelclock); + + dev_dbg(hdmi->dev, "final pixclk = %d\n", vmode->mpixelclock); +- +- vmode->mtmdsclock = vmode->mpixelclock; +- +- if (!hdmi_bus_fmt_is_yuv422(hdmi->hdmi_data.enc_out_bus_format)) { +- switch (hdmi_bus_fmt_color_depth( +- hdmi->hdmi_data.enc_out_bus_format)) { +- case 16: +- vmode->mtmdsclock = vmode->mpixelclock * 2; +- break; +- case 12: +- vmode->mtmdsclock = vmode->mpixelclock * 3 / 2; +- break; +- case 10: +- vmode->mtmdsclock = vmode->mpixelclock * 5 / 4; +- break; +- } +- } +- +- if (hdmi_bus_fmt_is_yuv420(hdmi->hdmi_data.enc_out_bus_format)) +- vmode->mtmdsclock /= 2; +- + dev_dbg(hdmi->dev, "final tmdsclock = %d\n", vmode->mtmdsclock); + + /* Set up HDMI_FC_INVIDCONF */ +@@ -2663,8 +2660,21 @@ static int dw_hdmi_connector_create(struct dw_hdmi *hdmi) + * - MEDIA_BUS_FMT_RGB888_1X24, + */ + +-/* Can return a maximum of 11 possible output formats for a mode/connector */ +-#define MAX_OUTPUT_SEL_FORMATS 11 ++/* Can return a maximum of 15 possible output formats for a mode/connector */ ++#define MAX_OUTPUT_SEL_FORMATS 15 ++ ++static bool is_tmds_allowed(struct drm_display_info *info, ++ struct drm_display_mode *mode, ++ u32 bus_format) ++{ ++ unsigned long tmdsclock = hdmi_get_tmdsclock(bus_format, mode->clock); ++ int max_tmds_clock = info->max_tmds_clock ? info->max_tmds_clock : 340000; ++ ++ if (max_tmds_clock >= tmdsclock) ++ return true; ++ ++ return false; ++} + + static u32 *dw_hdmi_bridge_atomic_get_output_bus_fmts(struct drm_bridge *bridge, + struct drm_bridge_state *bridge_state, +@@ -2676,8 +2686,6 @@ static u32 *dw_hdmi_bridge_atomic_get_output_bus_fmts(struct drm_bridge *bridge, + struct drm_display_info *info = &conn->display_info; + struct drm_display_mode *mode = &crtc_state->mode; + u8 max_bpc = conn_state->max_requested_bpc; +- bool is_hdmi2_sink = info->hdmi.scdc.supported || +- (info->color_formats & DRM_COLOR_FORMAT_YCBCR420); + u32 *output_fmts; + unsigned int i = 0; + +@@ -2701,25 +2709,28 @@ static u32 *dw_hdmi_bridge_atomic_get_output_bus_fmts(struct drm_bridge *bridge, + * If the current mode enforces 4:2:0, force the output but format + * to 4:2:0 and do not add the YUV422/444/RGB formats + */ +- if (conn->ycbcr_420_allowed && +- (drm_mode_is_420_only(info, mode) || +- (is_hdmi2_sink && drm_mode_is_420_also(info, mode)))) { ++ if (conn->ycbcr_420_allowed && drm_mode_is_420(info, mode) && ++ (info->color_formats & DRM_COLOR_FORMAT_YCBCR420)) { + + /* Order bus formats from 16bit to 8bit if supported */ + if (max_bpc >= 16 && info->bpc == 16 && +- (info->hdmi.y420_dc_modes & DRM_EDID_YCBCR420_DC_48)) ++ (info->hdmi.y420_dc_modes & DRM_EDID_YCBCR420_DC_48) && ++ is_tmds_allowed(info, mode, MEDIA_BUS_FMT_UYYVYY16_0_5X48)) + output_fmts[i++] = MEDIA_BUS_FMT_UYYVYY16_0_5X48; + + if (max_bpc >= 12 && info->bpc >= 12 && +- (info->hdmi.y420_dc_modes & DRM_EDID_YCBCR420_DC_36)) ++ (info->hdmi.y420_dc_modes & DRM_EDID_YCBCR420_DC_36) && ++ is_tmds_allowed(info, mode, MEDIA_BUS_FMT_UYYVYY12_0_5X36)) + output_fmts[i++] = MEDIA_BUS_FMT_UYYVYY12_0_5X36; + + if (max_bpc >= 10 && info->bpc >= 10 && +- (info->hdmi.y420_dc_modes & DRM_EDID_YCBCR420_DC_30)) ++ (info->hdmi.y420_dc_modes & DRM_EDID_YCBCR420_DC_30) && ++ is_tmds_allowed(info, mode, MEDIA_BUS_FMT_UYYVYY10_0_5X30)) + output_fmts[i++] = MEDIA_BUS_FMT_UYYVYY10_0_5X30; + + /* Default 8bit fallback */ +- output_fmts[i++] = MEDIA_BUS_FMT_UYYVYY8_0_5X24; ++ if (is_tmds_allowed(info, mode, MEDIA_BUS_FMT_UYYVYY8_0_5X24)) ++ output_fmts[i++] = MEDIA_BUS_FMT_UYYVYY8_0_5X24; + + if (drm_mode_is_420_only(info, mode)) + *num_output_fmts = i; +@@ -2732,40 +2744,51 @@ static u32 *dw_hdmi_bridge_atomic_get_output_bus_fmts(struct drm_bridge *bridge, + */ + + /* Default 8bit RGB fallback */ +- output_fmts[i++] = MEDIA_BUS_FMT_RGB888_1X24; ++ if (is_tmds_allowed(info, mode, MEDIA_BUS_FMT_RGB888_1X24)) ++ output_fmts[i++] = MEDIA_BUS_FMT_RGB888_1X24; + + if (max_bpc >= 16 && info->bpc == 16) { +- if (info->color_formats & DRM_COLOR_FORMAT_YCBCR444) ++ if ((info->color_formats & DRM_COLOR_FORMAT_YCBCR444) && ++ is_tmds_allowed(info, mode, MEDIA_BUS_FMT_YUV16_1X48)) + output_fmts[i++] = MEDIA_BUS_FMT_YUV16_1X48; + +- output_fmts[i++] = MEDIA_BUS_FMT_RGB161616_1X48; ++ if (is_tmds_allowed(info, mode, MEDIA_BUS_FMT_RGB161616_1X48)) ++ output_fmts[i++] = MEDIA_BUS_FMT_RGB161616_1X48; + } + + if (max_bpc >= 12 && info->bpc >= 12) { +- if (info->color_formats & DRM_COLOR_FORMAT_YCBCR422) ++ if ((info->color_formats & DRM_COLOR_FORMAT_YCBCR422) && ++ is_tmds_allowed(info, mode, MEDIA_BUS_FMT_UYVY12_1X24)) + output_fmts[i++] = MEDIA_BUS_FMT_UYVY12_1X24; + +- if (info->color_formats & DRM_COLOR_FORMAT_YCBCR444) ++ if ((info->color_formats & DRM_COLOR_FORMAT_YCBCR444) && ++ is_tmds_allowed(info, mode, MEDIA_BUS_FMT_YUV12_1X36)) + output_fmts[i++] = MEDIA_BUS_FMT_YUV12_1X36; + +- output_fmts[i++] = MEDIA_BUS_FMT_RGB121212_1X36; ++ if (is_tmds_allowed(info, mode, MEDIA_BUS_FMT_RGB121212_1X36)) ++ output_fmts[i++] = MEDIA_BUS_FMT_RGB121212_1X36; + } + + if (max_bpc >= 10 && info->bpc >= 10) { +- if (info->color_formats & DRM_COLOR_FORMAT_YCBCR422) ++ if ((info->color_formats & DRM_COLOR_FORMAT_YCBCR422) && ++ is_tmds_allowed(info, mode, MEDIA_BUS_FMT_UYVY10_1X20)) + output_fmts[i++] = MEDIA_BUS_FMT_UYVY10_1X20; + +- if (info->color_formats & DRM_COLOR_FORMAT_YCBCR444) ++ if ((info->color_formats & DRM_COLOR_FORMAT_YCBCR444) && ++ is_tmds_allowed(info, mode, MEDIA_BUS_FMT_YUV10_1X30)) + output_fmts[i++] = MEDIA_BUS_FMT_YUV10_1X30; + +- output_fmts[i++] = MEDIA_BUS_FMT_RGB101010_1X30; ++ if (is_tmds_allowed(info, mode, MEDIA_BUS_FMT_RGB101010_1X30)) ++ output_fmts[i++] = MEDIA_BUS_FMT_RGB101010_1X30; + } + +- if (info->color_formats & DRM_COLOR_FORMAT_YCBCR422) ++ if ((info->color_formats & DRM_COLOR_FORMAT_YCBCR422) && ++ is_tmds_allowed(info, mode, MEDIA_BUS_FMT_UYVY8_1X16)) + output_fmts[i++] = MEDIA_BUS_FMT_UYVY8_1X16; + +- if (info->color_formats & DRM_COLOR_FORMAT_YCBCR444) ++ if ((info->color_formats & DRM_COLOR_FORMAT_YCBCR444) && ++ is_tmds_allowed(info, mode, MEDIA_BUS_FMT_YUV8_1X24)) + output_fmts[i++] = MEDIA_BUS_FMT_YUV8_1X24; + + *num_output_fmts = i; + +@@ -2946,11 +2969,20 @@ dw_hdmi_bridge_mode_valid(struct drm_bridge *bridge, + struct dw_hdmi *hdmi = bridge->driver_private; + const struct dw_hdmi_plat_data *pdata = hdmi->plat_data; + enum drm_mode_status mode_status = MODE_OK; ++ int max_tmds_clock = info->max_tmds_clock ? info->max_tmds_clock : 340000; ++ int clock = mode->clock; + + /* We don't support double-clocked modes */ + if (mode->flags & DRM_MODE_FLAG_DBLCLK) + return MODE_BAD; + ++ if (pdata->ycbcr_420_allowed && drm_mode_is_420(info, mode) && ++ (info->color_formats & DRM_COLOR_FORMAT_YCBCR420)) ++ clock /= 2; ++ ++ if (clock > max_tmds_clock) ++ return MODE_CLOCK_HIGH; ++ + if (pdata->mode_valid) + mode_status = pdata->mode_valid(hdmi, pdata->priv_data, info, + mode); + +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Jonas Karlman +Date: Fri, 20 Dec 2019 08:12:42 +0000 +Subject: [PATCH] WIP: drm/rockchip: dw_hdmi: add 10-bit rgb bus format + +--- + drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c | 42 +++++++++++++++++++++ + drivers/gpu/drm/rockchip/rockchip_drm_drv.h | 1 + + 2 files changed, 43 insertions(+) + +diff --git a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c +index d6d8f3335813..89424c5bc24a 100644 +--- a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c ++++ b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c +@@ -84,6 +84,8 @@ struct rockchip_hdmi { + struct phy *phy; + }; + ++#define to_crtc_state(x) container_of(x, struct drm_crtc_state, x) ++ + static struct rockchip_hdmi *to_rockchip_hdmi(struct drm_bridge *bridge) + { + return container_of(bridge, struct rockchip_hdmi, bridge); +@@ -341,6 +343,11 @@ dw_hdmi_rockchip_bridge_mode_set(struct drm_bridge *bridge, + const struct drm_display_mode *adjusted_mode) + { + struct rockchip_hdmi *hdmi = to_rockchip_hdmi(bridge); ++ struct drm_crtc_state *crtc_state = to_crtc_state(adjusted_mode); ++ struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc_state); ++ ++ if (hdmi->phy) ++ phy_set_bus_width(hdmi->phy, s->bus_width); + + clk_set_rate(hdmi->ref_clk, adjusted_mode->clock * 1000); + } +@@ -381,6 +388,17 @@ static bool is_rgb(u32 format) + { + switch (format) { + case MEDIA_BUS_FMT_RGB888_1X24: ++ case MEDIA_BUS_FMT_RGB101010_1X30: ++ return true; ++ default: ++ return false; ++ } ++} ++ ++static bool is_10bit(u32 format) ++{ ++ switch (format) { ++ case MEDIA_BUS_FMT_RGB101010_1X30: + return true; + default: + return false; +@@ -394,9 +412,24 @@ dw_hdmi_rockchip_bridge_atomic_check(struct drm_bridge *bridge, + struct drm_connector_state *conn_state) + { + struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc_state); ++ struct drm_atomic_state *state = bridge_state->base.state; ++ struct drm_crtc_state *old_crtc_state; ++ struct rockchip_crtc_state *old_state; ++ u32 format = bridge_state->output_bus_cfg.format; + + s->output_mode = ROCKCHIP_OUT_MODE_AAAA; + s->output_type = DRM_MODE_CONNECTOR_HDMIA; ++ s->output_bpc = 10; ++ s->bus_format = format; ++ s->bus_width = is_10bit(format) ? 10 : 8; ++ ++ old_crtc_state = drm_atomic_get_old_crtc_state(state, conn_state->crtc); ++ if (old_crtc_state && !crtc_state->mode_changed) { ++ old_state = to_rockchip_crtc_state(old_crtc_state); ++ if (s->bus_format != old_state->bus_format || ++ s->bus_width != old_state->bus_width) ++ crtc_state->mode_changed = true; ++ } + + return 0; + } +@@ -408,10 +441,19 @@ static u32 *dw_hdmi_rockchip_get_input_bus_fmts(struct drm_bridge *bridge, + u32 output_fmt, + unsigned int *num_input_fmts) + { ++ struct rockchip_hdmi *hdmi = to_rockchip_hdmi(bridge); ++ struct drm_encoder *encoder = bridge->encoder; + u32 *input_fmt; ++ bool has_10bit = true; + + *num_input_fmts = 0; + ++ if (drm_of_encoder_active_endpoint_id(hdmi->dev->of_node, encoder)) ++ has_10bit = false; ++ ++ if (!has_10bit && is_10bit(output_fmt)) ++ return NULL; ++ + if (!is_rgb(output_fmt)) + return NULL; + +diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_drv.h b/drivers/gpu/drm/rockchip/rockchip_drm_drv.h +index 1641440837af..381e5ccab5f3 100644 +--- a/drivers/gpu/drm/rockchip/rockchip_drm_drv.h ++++ b/drivers/gpu/drm/rockchip/rockchip_drm_drv.h +@@ -34,6 +34,7 @@ struct rockchip_crtc_state { + u32 bus_format; + u32 bus_flags; + int color_space; ++ int bus_width; + }; + #define to_rockchip_crtc_state(s) \ + container_of(s, struct rockchip_crtc_state, base) + +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Jonas Karlman +Date: Sun, 8 Dec 2019 23:42:44 +0000 +Subject: [PATCH] WIP: drm: dw-hdmi: add content type connector property + +Signed-off-by: Jonas Karlman +--- + drivers/gpu/drm/bridge/synopsys/dw-hdmi.c | 8 +++++++- + 1 file changed, 7 insertions(+), 1 deletion(-) + +diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c +index 7f6ffbc3e7b2..ae4c49e84470 100644 +--- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c ++++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c +@@ -1790,6 +1790,7 @@ static void hdmi_config_AVI(struct dw_hdmi *hdmi, + const struct drm_connector *connector, + const struct drm_display_mode *mode) + { ++ const struct drm_connector_state *conn_state = connector->state; + struct hdmi_avi_infoframe frame; + u8 val; + +@@ -1847,6 +1848,8 @@ static void hdmi_config_AVI(struct dw_hdmi *hdmi, + HDMI_EXTENDED_COLORIMETRY_XV_YCC_601; + } + ++ drm_hdmi_avi_infoframe_content_type(&frame, conn_state); ++ + /* + * The Designware IP uses a different byte format from standard + * AVI info frames, though generally the bits are in the correct +@@ -2551,7 +2554,8 @@ static int dw_hdmi_connector_atomic_check(struct drm_connector *connector, + if (!crtc) + return 0; + +- if (!drm_connector_atomic_hdr_metadata_equal(old_state, new_state)) { ++ if (!drm_connector_atomic_hdr_metadata_equal(old_state, new_state) || ++ old_state->content_type != new_state->content_type) { + crtc_state = drm_atomic_get_crtc_state(state, crtc); + if (IS_ERR(crtc_state)) + return PTR_ERR(crtc_state); +@@ -2619,6 +2623,8 @@ static int dw_hdmi_connector_create(struct dw_hdmi *hdmi) + + drm_connector_attach_max_bpc_property(connector, 8, 16); + ++ drm_connector_attach_content_type_property(connector); ++ + if (hdmi->version >= 0x200a && hdmi->plat_data->use_drm_infoframe) + drm_connector_attach_hdr_output_metadata_property(connector); + + +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Jonas Karlman +Date: Fri, 20 Dec 2019 08:12:43 +0000 +Subject: [PATCH] WIP: drm/rockchip: add yuv444 support + +--- + drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c | 29 ++++++++++++++++++++- + drivers/gpu/drm/rockchip/rockchip_drm_vop.c | 29 +++++++++++++++++++++ + drivers/gpu/drm/rockchip/rockchip_drm_vop.h | 6 +++++ + drivers/gpu/drm/rockchip/rockchip_vop_reg.c | 19 ++++++++++++++ + 4 files changed, 82 insertions(+), 1 deletion(-) + +diff --git a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c +index 89424c5bc24a..05de2052d95d 100644 +--- a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c ++++ b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c +@@ -68,6 +68,7 @@ struct rockchip_hdmi_chip_data { + u32 lcdsel_big; + u32 lcdsel_lit; + int max_tmds_clock; ++ bool ycbcr_444_allowed; + }; + + struct rockchip_hdmi { +@@ -395,10 +396,22 @@ static bool is_rgb(u32 format) + } + } + ++static bool is_yuv444(u32 format) ++{ ++ switch (format) { ++ case MEDIA_BUS_FMT_YUV10_1X30: ++ case MEDIA_BUS_FMT_YUV8_1X24: ++ return true; ++ default: ++ return false; ++ } ++} ++ + static bool is_10bit(u32 format) + { + switch (format) { + case MEDIA_BUS_FMT_RGB101010_1X30: ++ case MEDIA_BUS_FMT_YUV10_1X30: + return true; + default: + return false; +@@ -415,12 +428,22 @@ dw_hdmi_rockchip_bridge_atomic_check(struct drm_bridge *bridge, + struct drm_atomic_state *state = bridge_state->base.state; + struct drm_crtc_state *old_crtc_state; + struct rockchip_crtc_state *old_state; ++ struct drm_bridge *next_bridge; ++ struct drm_bridge_state *next_bridge_state; + u32 format = bridge_state->output_bus_cfg.format; + + s->output_mode = ROCKCHIP_OUT_MODE_AAAA; + s->output_type = DRM_MODE_CONNECTOR_HDMIA; + s->output_bpc = 10; + s->bus_format = format; ++ ++ next_bridge = drm_bridge_get_next_bridge(bridge); ++ if (next_bridge) { ++ next_bridge_state = drm_atomic_get_new_bridge_state(state, ++ next_bridge); ++ format = next_bridge_state->output_bus_cfg.format; ++ } ++ + s->bus_width = is_10bit(format) ? 10 : 8; + + old_crtc_state = drm_atomic_get_old_crtc_state(state, conn_state->crtc); +@@ -454,7 +477,10 @@ static u32 *dw_hdmi_rockchip_get_input_bus_fmts(struct drm_bridge *bridge, + if (!has_10bit && is_10bit(output_fmt)) + return NULL; + +- if (!is_rgb(output_fmt)) ++ if (is_yuv444(output_fmt)) { ++ if (!hdmi->chip_data->ycbcr_444_allowed) ++ return NULL; ++ } else if (!is_rgb(output_fmt)) + return NULL; + + input_fmt = kzalloc(sizeof(*input_fmt), GFP_KERNEL); +@@ -604,6 +630,7 @@ static const struct dw_hdmi_phy_ops rk3328_hdmi_phy_ops = { + static struct rockchip_hdmi_chip_data rk3328_chip_data = { + .lcdsel_grf_reg = -1, + .max_tmds_clock = 594000, ++ .ycbcr_444_allowed = true, + }; + + static const struct dw_hdmi_plat_data rk3328_hdmi_drv_data = { +diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c +index eadf1b0f1704..0e4eca0d5121 100644 +--- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c ++++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c +@@ -347,6 +347,17 @@ static int vop_convert_afbc_format(uint32_t format) + return -EINVAL; + } + ++static bool is_yuv_output(uint32_t bus_format) ++{ ++ switch (bus_format) { ++ case MEDIA_BUS_FMT_YUV8_1X24: ++ case MEDIA_BUS_FMT_YUV10_1X30: ++ return true; ++ default: ++ return false; ++ } ++} ++ + static uint16_t scl_vop_cal_scale(enum scale_mode mode, uint32_t src, + uint32_t dst, bool is_horizontal, + int vsu_mode, int *vskiplines) +@@ -1455,6 +1466,7 @@ static void vop_crtc_atomic_enable(struct drm_crtc *crtc, + u16 vact_end = vact_st + vdisplay; + uint32_t pin_pol, val; + int dither_bpc = s->output_bpc ? s->output_bpc : 10; ++ bool yuv_output = is_yuv_output(s->bus_format); + int ret; + + if (old_state && old_state->self_refresh_active) { +@@ -1520,6 +1532,8 @@ static void vop_crtc_atomic_enable(struct drm_crtc *crtc, + !(vop_data->feature & VOP_FEATURE_OUTPUT_RGB10)) + s->output_mode = ROCKCHIP_OUT_MODE_P888; + ++ VOP_REG_SET(vop, common, dsp_data_swap, yuv_output ? 2 : 0); ++ + if (s->output_mode == ROCKCHIP_OUT_MODE_AAAA && dither_bpc <= 8) + VOP_REG_SET(vop, common, pre_dither_down, 1); + else +@@ -1535,6 +1549,21 @@ static void vop_crtc_atomic_enable(struct drm_crtc *crtc, + + VOP_REG_SET(vop, common, out_mode, s->output_mode); + ++ VOP_REG_SET(vop, common, overlay_mode, yuv_output); ++ VOP_REG_SET(vop, common, dsp_out_yuv, yuv_output); ++ ++ /* ++ * Background color is 10bit depth if vop version >= 3.5 ++ */ ++ if (!yuv_output) ++ val = 0; ++ else if (VOP_MAJOR(vop_data->version) == 3 && ++ VOP_MINOR(vop_data->version) >= 5) ++ val = 0x20010200; ++ else ++ val = 0x801080; ++ VOP_REG_SET(vop, common, dsp_background, val); ++ + VOP_REG_SET(vop, modeset, htotal_pw, (htotal << 16) | hsync_len); + val = hact_st << 16; + val |= hact_end; +diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.h b/drivers/gpu/drm/rockchip/rockchip_drm_vop.h +index ca4e2b7415fe..47ad74ef1afb 100644 +--- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.h ++++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.h +@@ -119,10 +119,16 @@ struct vop_common { + struct vop_reg mmu_en; + struct vop_reg out_mode; + struct vop_reg standby; ++ ++ struct vop_reg overlay_mode; ++ struct vop_reg dsp_data_swap; ++ struct vop_reg dsp_out_yuv; ++ struct vop_reg dsp_background; + }; + + struct vop_misc { + struct vop_reg global_regdone_en; ++ struct vop_reg win_channel[4]; + }; + + struct vop_intr { +diff --git a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c +index a2b281e290e0..b16a4c42773c 100644 +--- a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c ++++ b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c +@@ -705,6 +705,11 @@ static const struct vop_common rk3288_common = { + .dsp_blank = VOP_REG(RK3288_DSP_CTRL0, 0x3, 18), + .out_mode = VOP_REG(RK3288_DSP_CTRL0, 0xf, 0), + .cfg_done = VOP_REG_SYNC(RK3288_REG_CFG_DONE, 0x1, 0), ++ ++ .overlay_mode = VOP_REG(RK3288_SYS_CTRL, 0x1, 16), ++ .dsp_data_swap = VOP_REG(RK3288_DSP_CTRL0, 0x1f, 12), ++ .dsp_out_yuv = VOP_REG(RK3288_POST_SCL_CTRL, 0x1, 2), ++ .dsp_background = VOP_REG(RK3288_DSP_BG, 0xffffffff, 0), + }; + + /* +@@ -926,6 +931,11 @@ static const struct vop_common rk3399_common = { + .dsp_blank = VOP_REG(RK3399_DSP_CTRL0, 0x3, 18), + .out_mode = VOP_REG(RK3399_DSP_CTRL0, 0xf, 0), + .cfg_done = VOP_REG_SYNC(RK3399_REG_CFG_DONE, 0x1, 0), ++ ++ .overlay_mode = VOP_REG(RK3399_SYS_CTRL, 0x1, 16), ++ .dsp_data_swap = VOP_REG(RK3399_DSP_CTRL0, 0x1f, 12), ++ .dsp_out_yuv = VOP_REG(RK3288_POST_SCL_CTRL, 0x1, 2), ++ .dsp_background = VOP_REG(RK3288_DSP_BG, 0xffffffff, 0), + }; + + static const struct vop_yuv2yuv_phy rk3399_yuv2yuv_win01_data = { +@@ -1096,6 +1106,10 @@ static const struct vop_output rk3328_output = { + + static const struct vop_misc rk3328_misc = { + .global_regdone_en = VOP_REG(RK3328_SYS_CTRL, 0x1, 11), ++ ++ .win_channel[0] = VOP_REG(RK3328_WIN0_CTRL2, 0xff, 0), ++ .win_channel[1] = VOP_REG(RK3328_WIN1_CTRL2, 0xff, 0), ++ .win_channel[2] = VOP_REG(RK3328_WIN2_CTRL2, 0xff, 0), + }; + + static const struct vop_common rk3328_common = { +@@ -1108,6 +1122,11 @@ static const struct vop_common rk3328_common = { + .dsp_blank = VOP_REG(RK3328_DSP_CTRL0, 0x3, 18), + .out_mode = VOP_REG(RK3328_DSP_CTRL0, 0xf, 0), + .cfg_done = VOP_REG_SYNC(RK3328_REG_CFG_DONE, 0x1, 0), ++ ++ .overlay_mode = VOP_REG(RK3328_SYS_CTRL, 0x1, 16), ++ .dsp_data_swap = VOP_REG(RK3328_DSP_CTRL0, 0x1f, 12), ++ .dsp_out_yuv = VOP_REG(RK3328_POST_SCL_CTRL, 0x1, 2), ++ .dsp_background = VOP_REG(RK3328_DSP_BG, 0xffffffff, 0), + }; + + static const struct vop_intr rk3328_vop_intr = { + +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Jonas Karlman +Date: Fri, 20 Dec 2019 08:12:43 +0000 +Subject: [PATCH] WIP: drm/rockchip: add yuv420 support + +--- + drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c | 22 +++++++++++++++++++++ + drivers/gpu/drm/rockchip/rockchip_drm_vop.c | 19 +++++++++++++++++- + drivers/gpu/drm/rockchip/rockchip_drm_vop.h | 10 ++++++---- + drivers/gpu/drm/rockchip/rockchip_vop_reg.c | 2 ++ + 4 files changed, 48 insertions(+), 5 deletions(-) + +diff --git a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c +index 05de2052d95d..cb201612199f 100644 +--- a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c ++++ b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c +@@ -407,9 +407,21 @@ static bool is_yuv444(u32 format) + } + } + ++static bool is_yuv420(u32 format) ++{ ++ switch (format) { ++ case MEDIA_BUS_FMT_UYYVYY10_0_5X30: ++ case MEDIA_BUS_FMT_UYYVYY8_0_5X24: ++ return true; ++ default: ++ return false; ++ } ++} ++ + static bool is_10bit(u32 format) + { + switch (format) { ++ case MEDIA_BUS_FMT_UYYVYY10_0_5X30: + case MEDIA_BUS_FMT_RGB101010_1X30: + case MEDIA_BUS_FMT_YUV10_1X30: + return true; +@@ -446,6 +458,11 @@ dw_hdmi_rockchip_bridge_atomic_check(struct drm_bridge *bridge, + + s->bus_width = is_10bit(format) ? 10 : 8; + ++ if (is_yuv420(format)) { ++ s->output_mode = ROCKCHIP_OUT_MODE_YUV420; ++ s->bus_width /= 2; ++ } ++ + old_crtc_state = drm_atomic_get_old_crtc_state(state, conn_state->crtc); + if (old_crtc_state && !crtc_state->mode_changed) { + old_state = to_rockchip_crtc_state(old_crtc_state); +@@ -466,6 +483,7 @@ static u32 *dw_hdmi_rockchip_get_input_bus_fmts(struct drm_bridge *bridge, + { + struct rockchip_hdmi *hdmi = to_rockchip_hdmi(bridge); + struct drm_encoder *encoder = bridge->encoder; ++ struct drm_connector *connector = conn_state->connector; + u32 *input_fmt; + bool has_10bit = true; + +@@ -480,6 +498,9 @@ static u32 *dw_hdmi_rockchip_get_input_bus_fmts(struct drm_bridge *bridge, + if (is_yuv444(output_fmt)) { + if (!hdmi->chip_data->ycbcr_444_allowed) + return NULL; ++ } else if (is_yuv420(output_fmt)) { ++ if (!connector->ycbcr_420_allowed) ++ return NULL; + } else if (!is_rgb(output_fmt)) + return NULL; + +@@ -640,6 +661,7 @@ static const struct dw_hdmi_plat_data rk3328_hdmi_drv_data = { + .phy_name = "inno_dw_hdmi_phy2", + .phy_force_vendor = true, + .use_drm_infoframe = true, ++ .ycbcr_420_allowed = true, + }; + + static struct rockchip_hdmi_chip_data rk3399_chip_data = { +diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c +index 0e4eca0d5121..e50f71ad3ceb 100644 +--- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c ++++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c +@@ -10,6 +10,7 @@ + #include + #include + #include ++#include + #include + #include + #include +@@ -348,6 +349,19 @@ static int vop_convert_afbc_format(uint32_t format) + } + + static bool is_yuv_output(uint32_t bus_format) ++{ ++ switch (bus_format) { ++ case MEDIA_BUS_FMT_YUV8_1X24: ++ case MEDIA_BUS_FMT_YUV10_1X30: ++ case MEDIA_BUS_FMT_UYYVYY8_0_5X24: ++ case MEDIA_BUS_FMT_UYYVYY10_0_5X30: ++ return true; ++ default: ++ return false; ++ } ++} ++ ++static bool bus_fmt_has_uv_swapped(uint32_t bus_format) + { + switch (bus_format) { + case MEDIA_BUS_FMT_YUV8_1X24: +@@ -1532,7 +1546,7 @@ static void vop_crtc_atomic_enable(struct drm_crtc *crtc, + !(vop_data->feature & VOP_FEATURE_OUTPUT_RGB10)) + s->output_mode = ROCKCHIP_OUT_MODE_P888; + +- VOP_REG_SET(vop, common, dsp_data_swap, yuv_output ? 2 : 0); ++ VOP_REG_SET(vop, common, dsp_data_swap, bus_fmt_has_uv_swapped(s->bus_format) ? 2 : 0); + + if (s->output_mode == ROCKCHIP_OUT_MODE_AAAA && dither_bpc <= 8) + VOP_REG_SET(vop, common, pre_dither_down, 1); +@@ -1549,6 +1563,9 @@ static void vop_crtc_atomic_enable(struct drm_crtc *crtc, + + VOP_REG_SET(vop, common, out_mode, s->output_mode); + ++ VOP_REG_SET(vop, common, dclk_ddr, ++ s->output_mode == ROCKCHIP_OUT_MODE_YUV420 ? 1 : 0); ++ + VOP_REG_SET(vop, common, overlay_mode, yuv_output); + VOP_REG_SET(vop, common, dsp_out_yuv, yuv_output); + +diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.h b/drivers/gpu/drm/rockchip/rockchip_drm_vop.h +index 47ad74ef1afb..94a615dca672 100644 +--- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.h ++++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.h +@@ -121,6 +121,7 @@ struct vop_common { + struct vop_reg standby; + + struct vop_reg overlay_mode; ++ struct vop_reg dclk_ddr; + struct vop_reg dsp_data_swap; + struct vop_reg dsp_out_yuv; + struct vop_reg dsp_background; +diff --git a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c +index b16a4c42773c..5463b04240f7 100644 +--- a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c ++++ b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c +@@ -707,6 +707,7 @@ static const struct vop_common rk3288_common = { + .cfg_done = VOP_REG_SYNC(RK3288_REG_CFG_DONE, 0x1, 0), + + .overlay_mode = VOP_REG(RK3288_SYS_CTRL, 0x1, 16), ++ .dclk_ddr = VOP_REG(RK3288_DSP_CTRL0, 0x1, 8), + .dsp_data_swap = VOP_REG(RK3288_DSP_CTRL0, 0x1f, 12), + .dsp_out_yuv = VOP_REG(RK3288_POST_SCL_CTRL, 0x1, 2), + .dsp_background = VOP_REG(RK3288_DSP_BG, 0xffffffff, 0), +@@ -1124,6 +1125,7 @@ static const struct vop_common rk3328_common = { + .cfg_done = VOP_REG_SYNC(RK3328_REG_CFG_DONE, 0x1, 0), + + .overlay_mode = VOP_REG(RK3328_SYS_CTRL, 0x1, 16), ++ .dclk_ddr = VOP_REG(RK3328_DSP_CTRL0, 0x1, 8), + .dsp_data_swap = VOP_REG(RK3328_DSP_CTRL0, 0x1f, 12), + .dsp_out_yuv = VOP_REG(RK3328_POST_SCL_CTRL, 0x1, 2), + .dsp_background = VOP_REG(RK3328_DSP_BG, 0xffffffff, 0), + +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Alex Bee +Date: Sat, 15 Aug 2020 23:20:34 +0200 +Subject: [PATCH] drm/rockchip: enable ycbcr_420_allowed and ycbcr_444_allowed + for RK3228 + +--- + drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c | 2 ++ + 1 file changed, 2 insertions(+) + +diff --git a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c +index cb201612199f..8627f6826bfe 100644 +--- a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c ++++ b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c +@@ -616,6 +616,7 @@ static const struct dw_hdmi_phy_ops rk3228_hdmi_phy_ops = { + static struct rockchip_hdmi_chip_data rk3228_chip_data = { + .lcdsel_grf_reg = -1, + .max_tmds_clock = 594000, ++ .ycbcr_444_allowed = true, + }; + + static const struct dw_hdmi_plat_data rk3228_hdmi_drv_data = { +@@ -624,6 +625,7 @@ static const struct dw_hdmi_plat_data rk3228_hdmi_drv_data = { + .phy_ops = &rk3228_hdmi_phy_ops, + .phy_name = "inno_dw_hdmi_phy2", + .phy_force_vendor = true, ++ .ycbcr_420_allowed = true, + }; + + static struct rockchip_hdmi_chip_data rk3288_chip_data = { + +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Jonas Karlman +Date: Sat, 18 Nov 2017 11:09:39 +0100 +Subject: [PATCH] rockchip: vop: force skip lines if image too big + +--- + drivers/gpu/drm/rockchip/rockchip_drm_vop.c | 13 ++++++++++--- + 1 file changed, 10 insertions(+), 3 deletions(-) + +diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c +index e50f71ad3ceb..ef0a078c22f4 100644 +--- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c ++++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c +@@ -958,6 +958,7 @@ static void vop_plane_atomic_update(struct drm_plane *plane, + int format; + int is_yuv = fb->format->is_yuv; + int i; ++ int skiplines = 0; + + /* + * can't update plane when vop is disabled. +@@ -976,8 +977,14 @@ static void vop_plane_atomic_update(struct drm_plane *plane, + obj = fb->obj[0]; + rk_obj = to_rockchip_obj(obj); + ++ /* ++ * Force skip lines when image is yuv and 3840 width, ++ * fixes a "jumping" green lines issue on RK3328. ++ */ + actual_w = drm_rect_width(src) >> 16; +- actual_h = drm_rect_height(src) >> 16; ++ if (actual_w == 3840 && is_yuv) ++ skiplines = 1; ++ actual_h = drm_rect_height(src) >> (16 + skiplines); + act_info = (actual_h - 1) << 16 | ((actual_w - 1) & 0xffff); + + dsp_info = (drm_rect_height(dest) - 1) << 16; +@@ -1019,7 +1026,7 @@ static void vop_plane_atomic_update(struct drm_plane *plane, + + VOP_WIN_SET(vop, win, format, format); + VOP_WIN_SET(vop, win, fmt_10, is_fmt_10(fb->format->format)); +- VOP_WIN_SET(vop, win, yrgb_vir, DIV_ROUND_UP(fb->pitches[0], 4)); ++ VOP_WIN_SET(vop, win, yrgb_vir, DIV_ROUND_UP(fb->pitches[0], 4 >> skiplines)); + VOP_WIN_SET(vop, win, yrgb_mst, dma_addr); + VOP_WIN_YUV2YUV_SET(vop, win_yuv2yuv, y2r_en, is_yuv); + VOP_WIN_SET(vop, win, y_mir_en, +@@ -1040,7 +1047,7 @@ static void vop_plane_atomic_update(struct drm_plane *plane, + offset += (src->y1 >> 16) * fb->pitches[1] / vsub; + + dma_addr = rk_uv_obj->dma_addr + offset + fb->offsets[1]; +- VOP_WIN_SET(vop, win, uv_vir, DIV_ROUND_UP(fb->pitches[1], 4)); ++ VOP_WIN_SET(vop, win, uv_vir, DIV_ROUND_UP(fb->pitches[1], 4 >> skiplines)); + VOP_WIN_SET(vop, win, uv_mst, dma_addr); + + for (i = 0; i < NUM_YUV2YUV_COEFFICIENTS; i++) { + +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Alex Bee +Date: Sat, 10 Apr 2021 16:54:26 +0200 +Subject: [PATCH] drm/bridge: dw-hdmi: fix RGB to YUV color space conversion + +We are currently providing color space conversion coefficents +for RGB to YUV conversion for full range to full range. +This is wrong, since we are hardcoding YCC quantization range +limited in the AVI infoframe (which is correct according to +HDMI specs). This results in to dark colors if this conversion +is used. +I verfied this by setting YCC quantization range to full in +AVI infoframe which resulted in correct colors. Doing this, +however, will be ignored by some (most) sinks. + +This patch fixes this, by providing CSC coefficents which +convert RGB full range to YUV limited range for both BT601 +and BT709 colorspaces. + +Fixes: 9aaf880ed4ee ("imx-drm: Add mx6 hdmi transmitter support") +Signed-off-by: Alex Bee +--- + drivers/gpu/drm/bridge/synopsys/dw-hdmi.c | 12 ++++++------ + 1 file changed, 6 insertions(+), 6 deletions(-) + +diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c +index ae4c49e84470..92e621f2714f 100644 +--- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c ++++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c +@@ -82,15 +82,15 @@ static const u16 csc_coeff_rgb_out_eitu709[3][4] = { + }; + + static const u16 csc_coeff_rgb_in_eitu601[3][4] = { +- { 0x2591, 0x1322, 0x074b, 0x0000 }, +- { 0x6535, 0x2000, 0x7acc, 0x0200 }, +- { 0x6acd, 0x7534, 0x2000, 0x0200 } ++ { 0x2040, 0x1080, 0x0640, 0x0040 }, ++ { 0xe880, 0x1c00, 0xfb80, 0x0200 }, ++ { 0xed80, 0xf680, 0x1c00, 0x0200 } + }; + + static const u16 csc_coeff_rgb_in_eitu709[3][4] = { +- { 0x2dc5, 0x0d9b, 0x049e, 0x0000 }, +- { 0x62f0, 0x2000, 0x7d11, 0x0200 }, +- { 0x6756, 0x78ab, 0x2000, 0x0200 } ++ { 0x2740, 0x0bc0, 0x0400, 0x0040 }, ++ { 0xe680, 0x1c00, 0xfd80, 0x0200 }, ++ { 0xea40, 0xf980, 0x1c00, 0x0200 } + }; + + static const u16 csc_coeff_rgb_full_to_rgb_limited[3][4] = { + +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Jonas Karlman +Date: Tue, 1 Oct 2019 20:52:42 +0000 +Subject: [PATCH] media: cec-adap: add debounce support when setting an invalid + phys addr + +When EDID is refreshed, HDMI cable is unplugged/replugged or +an AVR is power cycled the CEC phys addr gets invalidated. + +This can cause some disruption of CEC communication when +adapter is being reconfigured. + +Add a debounce_ms module option that can be used to debounce setting +an invalid phys addr. Default is not to use debouncing. + +Using a configured debounce_ms of e.g. 5000 ms, cec reconfiguring +could be avoided when AVR was power cycled on my setup. + +Power off AVR (default cec.debounce_ms=0): +[ 101.536866] cec-dw_hdmi: new physical address f.f.f.f +[ 102.495686] cec-dw_hdmi: new physical address 2.1.0.0 +[ 102.495913] cec-dw_hdmi: physical address: 2.1.0.0, claim 1 logical addresses +[ 102.628574] cec-dw_hdmi: config: la 1 pa 2.1.0.0 +[ 105.130115] cec-dw_hdmi: new physical address f.f.f.f +[ 106.979705] cec-dw_hdmi: new physical address 2.1.0.0 +[ 106.979872] cec-dw_hdmi: physical address: 2.1.0.0, claim 1 logical addresses +[ 107.112399] cec-dw_hdmi: config: la 1 pa 2.1.0.0 +[ 108.979408] cec-dw_hdmi: reported physical address 2.0.0.0 for logical address 5 +[ 109.205386] cec-dw_hdmi: reported physical address 2.0.0.0 for logical address 11 + +Power on AVR (default cec.debounce_ms=0): +[ 158.398447] cec-dw_hdmi: new physical address f.f.f.f +[ 161.977714] cec-dw_hdmi: new physical address 2.1.0.0 +[ 161.978766] cec-dw_hdmi: physical address: 2.1.0.0, claim 1 logical addresses +[ 162.115624] cec-dw_hdmi: config: la 1 pa 2.1.0.0 +[ 162.402750] cec-dw_hdmi: new physical address f.f.f.f +[ 162.403389] cec-dw_hdmi: cec_transmit_msg_fh: adapter is unconfigured +[ 162.886757] cec-dw_hdmi: new physical address 2.1.0.0 +[ 162.886964] cec-dw_hdmi: physical address: 2.1.0.0, claim 1 logical addresses +[ 163.510725] cec-dw_hdmi: config: la 1 pa 2.1.0.0 +[ 173.034200] cec-dw_hdmi: message 10 89 02 05 timed out + +Power off AVR (cec.debounce_ms=5000): +[ 251.720471] cec-dw_hdmi: reported physical address 2.0.0.0 for logical address 5 +[ 251.922432] cec-dw_hdmi: reported physical address 2.0.0.0 for logical address 11 + +Power on AVR (cec.debounce_ms=5000): +[ 291.154262] cec-dw_hdmi: reported physical address 2.0.0.0 for logical address 5 +[ 291.296199] cec-dw_hdmi: reported physical address 2.0.0.0 for logical address 11 + +Signed-off-by: Jonas Karlman +--- + drivers/media/cec/core/cec-adap.c | 9 ++++++++- + drivers/media/cec/core/cec-core.c | 18 ++++++++++++++++++ + drivers/media/cec/core/cec-priv.h | 1 + + include/media/cec.h | 2 ++ + 4 files changed, 29 insertions(+), 1 deletion(-) + +diff --git a/drivers/media/cec/core/cec-adap.c b/drivers/media/cec/core/cec-adap.c +index 41a79293ee02..542ab1425339 100644 +--- a/drivers/media/cec/core/cec-adap.c ++++ b/drivers/media/cec/core/cec-adap.c +@@ -1674,8 +1674,15 @@ void cec_s_phys_addr(struct cec_adapter *adap, u16 phys_addr, bool block) + if (IS_ERR_OR_NULL(adap)) + return; + ++ cancel_delayed_work_sync(&adap->debounce_work); ++ + mutex_lock(&adap->lock); +- __cec_s_phys_addr(adap, phys_addr, block); ++ if (cec_debounce_ms > 0 && !block && phys_addr == CEC_PHYS_ADDR_INVALID && ++ adap->phys_addr != phys_addr) ++ schedule_delayed_work(&adap->debounce_work, ++ msecs_to_jiffies(cec_debounce_ms)); ++ else ++ __cec_s_phys_addr(adap, phys_addr, block); + mutex_unlock(&adap->lock); + } + EXPORT_SYMBOL_GPL(cec_s_phys_addr); +diff --git a/drivers/media/cec/core/cec-core.c b/drivers/media/cec/core/cec-core.c +index af358e901b5f..bece8c56e5af 100644 +--- a/drivers/media/cec/core/cec-core.c ++++ b/drivers/media/cec/core/cec-core.c +@@ -40,6 +40,10 @@ static bool debug_phys_addr; + module_param(debug_phys_addr, bool, 0644); + MODULE_PARM_DESC(debug_phys_addr, "add CEC_CAP_PHYS_ADDR if set"); + ++int cec_debounce_ms; ++module_param_named(debounce_ms, cec_debounce_ms, int, 0644); ++MODULE_PARM_DESC(debounce_ms, "debounce invalid phys addr"); ++ + static dev_t cec_dev_t; + + /* Active devices */ +@@ -188,6 +192,8 @@ static void cec_devnode_unregister(struct cec_adapter *adap) + + mutex_unlock(&devnode->lock); + ++ cancel_delayed_work_sync(&adap->debounce_work); ++ + mutex_lock(&adap->lock); + __cec_s_phys_addr(adap, CEC_PHYS_ADDR_INVALID, false); + __cec_s_log_addrs(adap, NULL, false); +@@ -246,6 +252,17 @@ static const struct file_operations cec_error_inj_fops = { + }; + #endif + ++static void cec_s_phys_addr_debounce(struct work_struct *work) ++{ ++ struct delayed_work *delayed_work = to_delayed_work(work); ++ struct cec_adapter *adap = ++ container_of(delayed_work, struct cec_adapter, debounce_work); ++ ++ mutex_lock(&adap->lock); ++ __cec_s_phys_addr(adap, CEC_PHYS_ADDR_INVALID, false); ++ mutex_unlock(&adap->lock); ++} ++ + struct cec_adapter *cec_allocate_adapter(const struct cec_adap_ops *ops, + void *priv, const char *name, u32 caps, + u8 available_las) +@@ -283,6 +300,7 @@ struct cec_adapter *cec_allocate_adapter(const struct cec_adap_ops *ops, + INIT_LIST_HEAD(&adap->transmit_queue); + INIT_LIST_HEAD(&adap->wait_queue); + init_waitqueue_head(&adap->kthread_waitq); ++ INIT_DELAYED_WORK(&adap->debounce_work, cec_s_phys_addr_debounce); + + /* adap->devnode initialization */ + INIT_LIST_HEAD(&adap->devnode.fhs); +diff --git a/drivers/media/cec/core/cec-priv.h b/drivers/media/cec/core/cec-priv.h +index b78df931aa74..ebbea63ea9de 100644 +--- a/drivers/media/cec/core/cec-priv.h ++++ b/drivers/media/cec/core/cec-priv.h +@@ -37,6 +37,7 @@ static inline bool msg_is_raw(const struct cec_msg *msg) + + /* cec-core.c */ + extern int cec_debug; ++extern int cec_debounce_ms; + + /* cec-adap.c */ + int cec_monitor_all_cnt_inc(struct cec_adapter *adap); +diff --git a/include/media/cec.h b/include/media/cec.h +index abee41ae02d0..544eedb5d671 100644 +--- a/include/media/cec.h ++++ b/include/media/cec.h +@@ -236,6 +236,8 @@ struct cec_adapter { + struct task_struct *kthread; + wait_queue_head_t kthread_waitq; + ++ struct delayed_work debounce_work; ++ + const struct cec_adap_ops *ops; + void *priv; + u32 capabilities; + +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Alex Bee +Date: Fri, 22 Oct 2021 11:17:30 +0200 +Subject: [PATCH] WIP: drm/bridge: synopsys: Fix CEC not working after + power-cyclying + +This fixes standby -> power-on on Rockchip platform for, at least, +RK3288/RK3328/RK3399 where CEC wasn't working after powering on again. +It might differ for other phy implementations: +The whole HPD-detection part shoud be reworked and we should in general +avoid to rely in RX_SENSE phy status (at least for HDMI), since it differs +depending on sink's implementation. + +Signed-off-by: Alex Bee +--- + drivers/gpu/drm/bridge/synopsys/dw-hdmi.c | 14 ++++++++------ + 1 file changed, 8 insertions(+), 6 deletions(-) + +diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c +index 92e621f2714f..7551e3ab77d6 100644 +--- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c ++++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c +@@ -3179,12 +3179,6 @@ static irqreturn_t dw_hdmi_irq(int irq, void *dev_id) + phy_stat & HDMI_PHY_HPD, + phy_stat & HDMI_PHY_RX_SENSE); + +- if ((phy_stat & (HDMI_PHY_RX_SENSE | HDMI_PHY_HPD)) == 0) { +- mutex_lock(&hdmi->cec_notifier_mutex); +- cec_notifier_phys_addr_invalidate(hdmi->cec_notifier); +- mutex_unlock(&hdmi->cec_notifier_mutex); +- } +- + if (phy_stat & HDMI_PHY_HPD) + status = connector_status_connected; + +@@ -3201,6 +3195,14 @@ static irqreturn_t dw_hdmi_irq(int irq, void *dev_id) + drm_helper_hpd_irq_event(hdmi->bridge.dev); + drm_bridge_hpd_notify(&hdmi->bridge, status); + } ++ ++ if (status == connector_status_disconnected && ++ (phy_stat & HDMI_PHY_RX_SENSE) && ++ (phy_int_pol & HDMI_PHY_RX_SENSE)) { ++ mutex_lock(&hdmi->cec_notifier_mutex); ++ cec_notifier_phys_addr_invalidate(hdmi->cec_notifier); ++ mutex_unlock(&hdmi->cec_notifier_mutex); ++ } + } + + hdmi_writeb(hdmi, intr_stat, HDMI_IH_PHY_STAT0); + +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Jonas Karlman +Date: Fri, 9 Oct 2020 15:24:53 +0000 +Subject: [PATCH] drm/rockchip: vop: create planes in window order + +Signed-off-by: Jonas Karlman +--- + drivers/gpu/drm/rockchip/rockchip_drm_vop.c | 36 +++------------------ + 1 file changed, 4 insertions(+), 32 deletions(-) + +diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c +index 49619f794061..9915bf124374 100644 +--- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c ++++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c +@@ -2023,19 +2023,10 @@ static int vop_create_crtc(struct vop *vop) + int ret; + int i; + +- /* +- * Create drm_plane for primary and cursor planes first, since we need +- * to pass them to drm_crtc_init_with_planes, which sets the +- * "possible_crtcs" to the newly initialized crtc. +- */ + for (i = 0; i < vop_data->win_size; i++) { + struct vop_win *vop_win = &vop->win[i]; + const struct vop_win_data *win_data = vop_win->data; + +- if (win_data->type != DRM_PLANE_TYPE_PRIMARY && +- win_data->type != DRM_PLANE_TYPE_CURSOR) +- continue; +- + ret = drm_universal_plane_init(vop->drm_dev, &vop_win->base, + 0, &vop_plane_funcs, + win_data->phy->data_formats, +@@ -2068,32 +2059,13 @@ static int vop_create_crtc(struct vop *vop) + drm_crtc_enable_color_mgmt(crtc, 0, false, vop_data->lut_size); + } + +- /* +- * Create drm_planes for overlay windows with possible_crtcs restricted +- * to the newly created crtc. +- */ ++ /* Set possible_crtcs to the newly created crtc for overlay windows */ + for (i = 0; i < vop_data->win_size; i++) { + struct vop_win *vop_win = &vop->win[i]; +- const struct vop_win_data *win_data = vop_win->data; +- unsigned long possible_crtcs = drm_crtc_mask(crtc); +- +- if (win_data->type != DRM_PLANE_TYPE_OVERLAY) +- continue; + +- ret = drm_universal_plane_init(vop->drm_dev, &vop_win->base, +- possible_crtcs, +- &vop_plane_funcs, +- win_data->phy->data_formats, +- win_data->phy->nformats, +- win_data->phy->format_modifiers, +- win_data->type, NULL); +- if (ret) { +- DRM_DEV_ERROR(vop->dev, "failed to init overlay %d\n", +- ret); +- goto err_cleanup_crtc; +- } +- drm_plane_helper_add(&vop_win->base, &plane_helper_funcs); +- vop_plane_add_properties(&vop_win->base, win_data); ++ plane = &vop_win->base; ++ if (plane->type == DRM_PLANE_TYPE_OVERLAY) ++ plane->possible_crtcs = drm_crtc_mask(crtc); + } + + port = of_get_child_by_name(dev->of_node, "port"); diff --git a/patch/kernel/archive/rockchip-6.12/patches.libreelec/linux-1001-v4l2-rockchip.patch b/patch/kernel/archive/rockchip-6.12/patches.libreelec/linux-1001-v4l2-rockchip.patch new file mode 100644 index 000000000000..a80516538408 --- /dev/null +++ b/patch/kernel/archive/rockchip-6.12/patches.libreelec/linux-1001-v4l2-rockchip.patch @@ -0,0 +1,506 @@ +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Jonas Karlman +Date: Sat, 23 May 2020 10:16:01 +0000 +Subject: [PATCH] WIP: media: rkvdec: pm runtime dont use autosuspend before + disable and cleanup + +Signed-off-by: Jonas Karlman +--- + drivers/staging/media/rkvdec/rkvdec.c | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +diff --git a/drivers/staging/media/rkvdec/rkvdec.c b/drivers/staging/media/rkvdec/rkvdec.c +index 4f5436c89e08..eaf2f133a264 100644 +--- a/drivers/staging/media/rkvdec/rkvdec.c ++++ b/drivers/staging/media/rkvdec/rkvdec.c +@@ -1125,9 +1125,9 @@ static int rkvdec_remove(struct platform_device *pdev) + + cancel_delayed_work_sync(&rkvdec->watchdog_work); + +- rkvdec_v4l2_cleanup(rkvdec); +- pm_runtime_disable(&pdev->dev); + pm_runtime_dont_use_autosuspend(&pdev->dev); ++ pm_runtime_disable(&pdev->dev); ++ rkvdec_v4l2_cleanup(rkvdec); + } + + #ifdef CONFIG_PM + +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Randy Li +Date: Sun, 6 Jan 2019 01:48:37 +0800 +Subject: [PATCH] soc: rockchip: power-domain: export idle request + +We need to put the power status of HEVC IP into IDLE unless +we can't reset that IP or the SoC would crash down. +rockchip_pmu_idle_request(dev, true)---> enter idle +rockchip_pmu_idle_request(dev, false)---> exit idle + +Signed-off-by: Caesar Wang +Signed-off-by: Jeffy Chen +Signed-off-by: Randy Li +--- + drivers/pmdomain/rockchip/pm-domains.c | 23 +++++++++++++++++++++++ + include/linux/rockchip_pmu.h | 15 +++++++++++++++ + include/soc/rockchip/pm_domains.h | 6 ++++++ + 3 files changed, 44 insertions(+) + create mode 100644 include/linux/rockchip_pmu.h + +diff --git a/drivers/pmdomain/rockchip/pm-domains.c b/drivers/pmdomain/rockchip/pm-domains.c +index 89795abac951..ffb5d62c9d52 100644 +--- a/drivers/pmdomain/rockchip/pm-domains.c ++++ b/drivers/pmdomain/rockchip/pm-domains.c +@@ -309,6 +309,29 @@ static int rockchip_pmu_set_idle_request(struct rockchip_pm_domain *pd, + return 0; + } + ++int rockchip_pmu_idle_request(struct device *dev, bool idle) ++{ ++ struct generic_pm_domain *genpd; ++ struct rockchip_pm_domain *pd; ++ int ret; ++ ++ if (IS_ERR_OR_NULL(dev)) ++ return -EINVAL; ++ ++ if (IS_ERR_OR_NULL(dev->pm_domain)) ++ return -EINVAL; ++ ++ genpd = pd_to_genpd(dev->pm_domain); ++ pd = to_rockchip_pd(genpd); ++ ++ mutex_lock(&pd->pmu->mutex); ++ ret = rockchip_pmu_set_idle_request(pd, idle); ++ mutex_unlock(&pd->pmu->mutex); ++ ++ return ret; ++} ++EXPORT_SYMBOL(rockchip_pmu_idle_request); ++ + static int rockchip_pmu_save_qos(struct rockchip_pm_domain *pd) + { + int i; +diff --git a/include/linux/rockchip_pmu.h b/include/linux/rockchip_pmu.h +new file mode 100644 +index 000000000000..720b3314e71a +--- /dev/null ++++ b/include/linux/rockchip_pmu.h +@@ -0,0 +1,15 @@ ++/* ++ * pm_domain.h - Definitions and headers related to device power domains. ++ * ++ * Copyright (C) 2017 Randy Li . ++ * ++ * This file is released under the GPLv2. ++ */ ++ ++#ifndef _LINUX_ROCKCHIP_PM_H ++#define _LINUX_ROCKCHIP_PM_H ++#include ++ ++int rockchip_pmu_idle_request(struct device *dev, bool idle); ++ ++#endif /* _LINUX_ROCKCHIP_PM_H */ +diff --git a/include/soc/rockchip/pm_domains.h b/include/soc/rockchip/pm_domains.h +index 7dbd941fc937..c5a59dd71754 100644 +--- a/include/soc/rockchip/pm_domains.h ++++ b/include/soc/rockchip/pm_domains.h +@@ -10,6 +10,7 @@ + + int rockchip_pmu_block(void); + void rockchip_pmu_unblock(void); ++int rockchip_pmu_idle_request(struct device *dev, bool idle); + + #else /* CONFIG_ROCKCHIP_PM_DOMAINS */ + +@@ -20,6 +21,11 @@ static inline int rockchip_pmu_block(void) + + static inline void rockchip_pmu_unblock(void) { } + ++static inline int rockchip_pmu_idle_request(struct device *dev, bool idle) ++{ ++ return -ENOTSUPP; ++} ++ + #endif /* CONFIG_ROCKCHIP_PM_DOMAINS */ + + #endif /* __SOC_ROCKCHIP_PM_DOMAINS_H__ */ + +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Alex Bee +Date: Wed, 20 May 2020 17:04:47 +0200 +Subject: [PATCH] WIP: media: rkvdec: implement reset controls + +--- + .../bindings/media/rockchip,vdec.yaml | 19 +++++++ + drivers/staging/media/rkvdec/rkvdec-regs.h | 5 ++ + drivers/staging/media/rkvdec/rkvdec.c | 53 +++++++++++++++++++ + drivers/staging/media/rkvdec/rkvdec.h | 11 +++- + 4 files changed, 87 insertions(+), 1 deletion(-) + +diff --git a/Documentation/devicetree/bindings/media/rockchip,vdec.yaml b/Documentation/devicetree/bindings/media/rockchip,vdec.yaml +index 3bcfb8e12333..dd6958df1de8 100644 +--- a/Documentation/devicetree/bindings/media/rockchip,vdec.yaml ++++ b/Documentation/devicetree/bindings/media/rockchip,vdec.yaml +@@ -53,6 +53,18 @@ properties: + iommus: + maxItems: 1 + ++ resets: ++ maxItems: 6 ++ ++ reset-names: ++ items: ++ - const: video_h ++ - const: video_a ++ - const: video_core ++ - const: video_cabac ++ - const: niu_a ++ - const: niu_h ++ + required: + - compatible + - reg +@@ -60,6 +72,8 @@ required: + - clocks + - clock-names + - power-domains ++ - resets ++ - reset-names + + additionalProperties: false + +@@ -78,6 +92,11 @@ examples: + clock-names = "axi", "ahb", "cabac", "core"; + power-domains = <&power RK3399_PD_VDU>; + iommus = <&vdec_mmu>; ++ resets = <&cru SRST_H_VDU>, <&cru SRST_A_VDU>, ++ <&cru SRST_VDU_CORE>, <&cru SRST_VDU_CA>, ++ <&cru SRST_A_VDU_NOC>, <&cru SRST_H_VDU_NOC>; ++ reset-names = "video_h", "video_a", "video_core", "video_cabac", ++ "niu_a", "niu_h"; + }; + + ... +diff --git a/drivers/staging/media/rkvdec/rkvdec-regs.h b/drivers/staging/media/rkvdec/rkvdec-regs.h +index 15b9bee92016..3acc914888f6 100644 +--- a/drivers/staging/media/rkvdec/rkvdec-regs.h ++++ b/drivers/staging/media/rkvdec/rkvdec-regs.h +@@ -28,6 +28,11 @@ + #define RKVDEC_SOFTRST_EN_P BIT(20) + #define RKVDEC_FORCE_SOFTRESET_VALID BIT(21) + #define RKVDEC_SOFTRESET_RDY BIT(22) ++#define RKVDEC_ERR_MASK (RKVDEC_BUS_STA \ ++ | RKVDEC_ERR_STA \ ++ | RKVDEC_TIMEOUT_STA \ ++ | RKVDEC_BUF_EMPTY_STA \ ++ | RKVDEC_COLMV_REF_ERR_STA ) + + #define RKVDEC_REG_SYSCTRL 0x008 + #define RKVDEC_IN_ENDIAN BIT(0) +diff --git a/drivers/staging/media/rkvdec/rkvdec.c b/drivers/staging/media/rkvdec/rkvdec.c +index eaf2f133a264..f55abb7c377f 100644 +--- a/drivers/staging/media/rkvdec/rkvdec.c ++++ b/drivers/staging/media/rkvdec/rkvdec.c +@@ -10,12 +10,15 @@ + */ + + #include ++#include + #include + #include + #include + #include + #include + #include ++#include ++#include + #include + #include + #include +@@ -717,6 +720,11 @@ static void rkvdec_job_finish(struct rkvdec_ctx *ctx, + + pm_runtime_mark_last_busy(rkvdec->dev); + pm_runtime_put_autosuspend(rkvdec->dev); ++ ++ if (result == VB2_BUF_STATE_ERROR && ++ rkvdec->reset_mask == RESET_NONE) ++ rkvdec->reset_mask |= RESET_SOFT; ++ + rkvdec_job_finish_no_pm(ctx, result); + } + +@@ -754,6 +762,33 @@ static void rkvdec_device_run(void *priv) + + if (WARN_ON(!desc)) + return; ++ if (rkvdec->reset_mask != RESET_NONE) { ++ ++ if (rkvdec->reset_mask & RESET_SOFT) { ++ writel(RKVDEC_SOFTRST_EN_P, ++ rkvdec->regs + RKVDEC_REG_INTERRUPT); ++ udelay(RKVDEC_RESET_DELAY); ++ if (readl(rkvdec->regs + RKVDEC_REG_INTERRUPT) ++ & RKVDEC_SOFTRESET_RDY) ++ dev_info_ratelimited(rkvdec->dev, ++ "softreset failed\n"); ++ } ++ ++ if (rkvdec->reset_mask & RESET_HARD) { ++ rockchip_pmu_idle_request(rkvdec->dev, true); ++ ret = reset_control_assert(rkvdec->rstc); ++ if (!ret) { ++ udelay(RKVDEC_RESET_DELAY); ++ ret = reset_control_deassert(rkvdec->rstc); ++ } ++ rockchip_pmu_idle_request(rkvdec->dev, false); ++ if (ret) ++ dev_notice_ratelimited(rkvdec->dev, ++ "hardreset failed\n"); ++ } ++ rkvdec->reset_mask = RESET_NONE; ++ pm_runtime_suspend(rkvdec->dev); ++ } + + ret = pm_runtime_resume_and_get(rkvdec->dev); + if (ret < 0) { +@@ -1020,6 +1055,11 @@ static irqreturn_t rkvdec_irq_handler(int irq, void *priv) + if (cancel_delayed_work(&rkvdec->watchdog_work)) { + struct rkvdec_ctx *ctx; + ++ if (state == VB2_BUF_STATE_ERROR) { ++ rkvdec->reset_mask |= (status & RKVDEC_ERR_MASK) ? ++ RESET_HARD : RESET_SOFT; ++ } ++ + ctx = v4l2_m2m_get_curr_priv(rkvdec->m2m_dev); + rkvdec_job_finish(ctx, state); + } +@@ -1037,6 +1077,7 @@ static void rkvdec_watchdog_func(struct work_struct *work) + ctx = v4l2_m2m_get_curr_priv(rkvdec->m2m_dev); + if (ctx) { + dev_err(rkvdec->dev, "Frame processing timed out!\n"); ++ rkvdec->reset_mask |= RESET_HARD; + writel(RKVDEC_IRQ_DIS, rkvdec->regs + RKVDEC_REG_INTERRUPT); + writel(0, rkvdec->regs + RKVDEC_REG_SYSCTRL); + rkvdec_job_finish(ctx, VB2_BUF_STATE_ERROR); +@@ -1105,6 +1146,18 @@ static int rkvdec_probe(struct platform_device *pdev) + return ret; + } + ++ ++ rkvdec->rstc = devm_reset_control_array_get(&pdev->dev, false, true); ++ if (IS_ERR(rkvdec->rstc)) { ++ dev_err(&pdev->dev, ++ "get resets failed %ld\n", PTR_ERR(rkvdec->rstc)); ++ return PTR_ERR(rkvdec->rstc); ++ } else { ++ dev_dbg(&pdev->dev, ++ "requested %d resets\n", ++ reset_control_get_count(&pdev->dev)); ++ } ++ + pm_runtime_set_autosuspend_delay(&pdev->dev, 100); + pm_runtime_use_autosuspend(&pdev->dev); + pm_runtime_enable(&pdev->dev); +diff --git a/drivers/staging/media/rkvdec/rkvdec.h b/drivers/staging/media/rkvdec/rkvdec.h +index b9e219438bc9..f02f79c405f0 100644 +--- a/drivers/staging/media/rkvdec/rkvdec.h ++++ b/drivers/staging/media/rkvdec/rkvdec.h +@@ -11,10 +11,11 @@ + #ifndef RKVDEC_H_ + #define RKVDEC_H_ + ++#include + #include ++#include + #include + #include +-#include + + #include + #include +@@ -22,6 +23,12 @@ + #include + #include + ++#define RESET_NONE 0 ++#define RESET_SOFT BIT(0) ++#define RESET_HARD BIT(1) ++ ++#define RKVDEC_RESET_DELAY 5 ++ + struct rkvdec_ctx; + + struct rkvdec_ctrl_desc { +@@ -96,6 +103,8 @@ struct rkvdec_dev { + void __iomem *regs; + struct mutex vdev_lock; /* serializes ioctls */ + struct delayed_work watchdog_work; ++ struct reset_control *rstc; ++ u8 reset_mask; + }; + + struct rkvdec_ctx { + +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Alex Bee +Date: Tue, 18 Aug 2020 11:38:04 +0200 +Subject: [PATCH] WIP: arm64: dts: add resets to vdec for RK3399 + +--- + arch/arm64/boot/dts/rockchip/rk3399-base.dtsi | 5 +++++ + 1 file changed, 5 insertions(+) + +diff --git a/arch/arm64/boot/dts/rockchip/rk3399-base.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-base.dtsi +index 980b12cb0a49..6e3149e587c5 100644 +--- a/arch/arm64/boot/dts/rockchip/rk3399-base.dtsi ++++ b/arch/arm64/boot/dts/rockchip/rk3399-base.dtsi +@@ -1345,6 +1348,11 @@ vdec: video-codec@ff660000 { + clock-names = "axi", "ahb", "cabac", "core"; + iommus = <&vdec_mmu>; + power-domains = <&power RK3399_PD_VDU>; ++ resets = <&cru SRST_H_VDU>, <&cru SRST_A_VDU>, ++ <&cru SRST_VDU_CORE>, <&cru SRST_VDU_CA>, ++ <&cru SRST_A_VDU_NOC>, <&cru SRST_H_VDU_NOC>; ++ reset-names = "video_h", "video_a", "video_core", "video_cabac", ++ "niu_a", "niu_h"; + }; + + vdec_mmu: iommu@ff660480 { + +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Alex Bee +Date: Sat, 21 Aug 2021 16:12:36 +0200 +Subject: [PATCH] media: hantro: rockchip: Increase RK3288's max ACLK + +Required to proper decode H.264@4K + +Signed-off-by: Alex Bee +--- + drivers/media/platform/verisilicon/rockchip_vpu_hw.c | 14 +++++++++++--- + 1 file changed, 11 insertions(+), 3 deletions(-) + +diff --git a/drivers/media/platform/verisilicon/rockchip_vpu_hw.c b/drivers/media/platform/verisilicon/rockchip_vpu_hw.c +index 8de6fd2e8eef..002b1a600f93 100644 +--- a/drivers/media/platform/verisilicon/rockchip_vpu_hw.c ++++ b/drivers/media/platform/verisilicon/rockchip_vpu_hw.c +@@ -15,7 +15,8 @@ + #include "rockchip_vpu2_regs.h" + + #define RK3066_ACLK_MAX_FREQ (300 * 1000 * 1000) +-#define RK3288_ACLK_MAX_FREQ (400 * 1000 * 1000) ++#define RK3288_ACLK_MAX_FREQ (600 * 1000 * 1000) ++#define RK3399_ACLK_MAX_FREQ (400 * 1000 * 1000) + #define RK3588_ACLK_MAX_FREQ (300 * 1000 * 1000) + + #define ROCKCHIP_VPU981_MIN_SIZE 64 +@@ -346,13 +347,20 @@ static int rk3066_vpu_hw_init(struct hantro_dev *vpu) + return 0; + } + +-static int rockchip_vpu_hw_init(struct hantro_dev *vpu) ++static int rk3288_vpu_hw_init(struct hantro_dev *vpu) + { + /* Bump ACLK to max. possible freq. to improve performance. */ + clk_set_rate(vpu->clocks[0].clk, RK3288_ACLK_MAX_FREQ); + return 0; + } + ++static int rockchip_vpu_hw_init(struct hantro_dev *vpu) ++{ ++ /* Bump ACLK to max. possible freq. to improve performance. */ ++ clk_set_rate(vpu->clocks[0].clk, RK3399_ACLK_MAX_FREQ); ++ return 0; ++} ++ + static void rk3066_vpu_dec_reset(struct hantro_ctx *ctx) + { + struct hantro_dev *vpu = ctx->dev; +@@ -592,7 +600,7 @@ const struct hantro_variant rk3288_vpu_variant = { + .codec_ops = rk3288_vpu_codec_ops, + .irqs = rockchip_vpu1_irqs, + .num_irqs = ARRAY_SIZE(rockchip_vpu1_irqs), +- .init = rockchip_vpu_hw_init, ++ .init = rk3288_vpu_hw_init, + .clk_names = rockchip_vpu_clk_names, + .num_clocks = ARRAY_SIZE(rockchip_vpu_clk_names) + }; + +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Alex Bee +Date: Sun, 4 Jul 2021 15:19:44 +0200 +Subject: [PATCH] media: rkvdec: disable QoS for VP9 (corruptions on RK3328 + otherwise) + +Signed-off-by: Alex Bee +--- + drivers/staging/media/rkvdec/rkvdec-regs.h | 2 ++ + drivers/staging/media/rkvdec/rkvdec-vp9.c | 8 ++++++++ + 2 files changed, 10 insertions(+) + +diff --git a/drivers/staging/media/rkvdec/rkvdec-regs.h b/drivers/staging/media/rkvdec/rkvdec-regs.h +index 3acc914888f6..265f5234f4eb 100644 +--- a/drivers/staging/media/rkvdec/rkvdec-regs.h ++++ b/drivers/staging/media/rkvdec/rkvdec-regs.h +@@ -222,6 +222,8 @@ + #define RKVDEC_REG_H264_ERR_E 0x134 + #define RKVDEC_H264_ERR_EN_HIGHBITS(x) ((x) & 0x3fffffff) + ++#define RKVDEC_QOS_CTRL 0x18C ++ + #define RKVDEC_REG_PREF_LUMA_CACHE_COMMAND 0x410 + #define RKVDEC_REG_PREF_CHR_CACHE_COMMAND 0x450 + +diff --git a/drivers/staging/media/rkvdec/rkvdec-vp9.c b/drivers/staging/media/rkvdec/rkvdec-vp9.c +index d8c1c0db15c7..a289bc968e91 100644 +--- a/drivers/staging/media/rkvdec/rkvdec-vp9.c ++++ b/drivers/staging/media/rkvdec/rkvdec-vp9.c +@@ -802,6 +802,7 @@ static int rkvdec_vp9_run(struct rkvdec_ctx *ctx) + struct rkvdec_dev *rkvdec = ctx->dev; + struct rkvdec_vp9_run run = { }; + int ret; ++ u32 reg; + + ret = rkvdec_vp9_run_preamble(ctx, &run); + if (ret) { +@@ -823,6 +824,13 @@ static int rkvdec_vp9_run(struct rkvdec_ctx *ctx) + writel(1, rkvdec->regs + RKVDEC_REG_PREF_CHR_CACHE_COMMAND); + + writel(0xe, rkvdec->regs + RKVDEC_REG_STRMD_ERR_EN); ++ ++ /* disable QOS for RK3328 - no effect on other SoCs */ ++ reg = readl(rkvdec->regs + RKVDEC_QOS_CTRL); ++ reg |= 0xFFFF; ++ reg &= (~BIT(12)); ++ writel(reg, rkvdec->regs + RKVDEC_QOS_CTRL); ++ + /* Start decoding! */ + writel(RKVDEC_INTERRUPT_DEC_E | RKVDEC_CONFIG_DEC_CLK_GATE_E | + RKVDEC_TIMEOUT_E | RKVDEC_BUF_EMPTY_E, + +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Alex Bee +Date: Thu, 16 Jun 2022 13:18:22 +0200 +Subject: [PATCH] WIP: arm64: dts: add resets to vdec for RK3328 + +--- + arch/arm64/boot/dts/rockchip/rk3328.dtsi | 5 +++++ + 1 file changed, 5 insertions(+) + +diff --git a/arch/arm64/boot/dts/rockchip/rk3328.dtsi b/arch/arm64/boot/dts/rockchip/rk3328.dtsi +index 5519347232f6..431c4ec198be 100644 +--- a/arch/arm64/boot/dts/rockchip/rk3328.dtsi ++++ b/arch/arm64/boot/dts/rockchip/rk3328.dtsi +@@ -674,6 +674,11 @@ vdec: video-codec@ff360000 { + assigned-clocks = <&cru ACLK_RKVDEC>, <&cru SCLK_VDEC_CABAC>, + <&cru SCLK_VDEC_CORE>; + assigned-clock-rates = <400000000>, <400000000>, <300000000>; ++ resets = <&cru SRST_VDEC_H>, <&cru SRST_VDEC_A>, ++ <&cru SRST_VDEC_CORE>, <&cru SRST_VDEC_CABAC>, ++ <&cru SRST_VDEC_NIU_A>, <&cru SRST_VDEC_NIU_H>; ++ reset-names = "video_h", "video_a", "video_core", "video_cabac", ++ "niu_a", "niu_h"; + iommus = <&vdec_mmu>; + power-domains = <&power RK3328_PD_VIDEO>; + }; diff --git a/patch/kernel/archive/rockchip-6.12/patches.libreelec/linux-1002-for-libreelec.patch b/patch/kernel/archive/rockchip-6.12/patches.libreelec/linux-1002-for-libreelec.patch new file mode 100644 index 000000000000..363a367de2ca --- /dev/null +++ b/patch/kernel/archive/rockchip-6.12/patches.libreelec/linux-1002-for-libreelec.patch @@ -0,0 +1,688 @@ +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Alex Bee +Date: Wed, 2 Sep 2020 19:52:02 +0200 +Subject: [PATCH] arm64: dts: rockchip: add gpu powerdomain, gpu opp-table and + cooling cell for RK3328 + +Note: since the regulator that supplies the GPU usually also supplies +other SoC components, we have to make sure voltage is never lower then +1075 mV - also disable 500 MHz for now, since it will crash if rkvdec +is running at the same time (voltage to high) + +Signed-off-by: Alex Bee +--- + .../arm64/boot/dts/rockchip/rk3328-roc-cc.dts | 4 +++ + .../arm64/boot/dts/rockchip/rk3328-rock64.dts | 4 +++ + arch/arm64/boot/dts/rockchip/rk3328.dtsi | 35 +++++++++++++++++++ + 3 files changed, 43 insertions(+) + +diff --git a/arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts b/arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts +index aa22a0c22265..51c7723d6762 100644 +--- a/arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts +@@ -166,6 +166,10 @@ &gmac2io { + status = "okay"; + }; + ++&gpu { ++ mali-supply = <&vdd_logic>; ++}; ++ + &hdmi { + status = "okay"; + }; +diff --git a/arch/arm64/boot/dts/rockchip/rk3328-rock64.dts b/arch/arm64/boot/dts/rockchip/rk3328-rock64.dts +index f69a38f42d2d..c198a8a7f95a 100644 +--- a/arch/arm64/boot/dts/rockchip/rk3328-rock64.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3328-rock64.dts +@@ -162,6 +162,10 @@ &gmac2io { + status = "okay"; + }; + ++&gpu { ++ mali-supply = <&vdd_logic>; ++}; ++ + &hdmi { + status = "okay"; + }; +diff --git a/arch/arm64/boot/dts/rockchip/rk3328.dtsi b/arch/arm64/boot/dts/rockchip/rk3328.dtsi +index 431c4ec198be..eec03adf0902 100644 +--- a/arch/arm64/boot/dts/rockchip/rk3328.dtsi ++++ b/arch/arm64/boot/dts/rockchip/rk3328.dtsi +@@ -300,6 +300,11 @@ power: power-controller { + #address-cells = <1>; + #size-cells = <0>; + ++ power-domain@RK3328_PD_GPU { ++ reg = ; ++ clocks = <&cru ACLK_GPU>; ++ #power-domain-cells = <0>; ++ }; + power-domain@RK3328_PD_HEVC { + reg = ; + #power-domain-cells = <0>; +@@ -539,6 +544,11 @@ map0 { + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + contribution = <4096>; + }; ++ map1 { ++ trip = <&target>; ++ cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; ++ contribution = <4096>; ++ }; + }; + }; + +@@ -620,7 +630,32 @@ gpu: gpu@ff300000 { + "ppmmu1"; + clocks = <&cru ACLK_GPU>, <&cru ACLK_GPU>; + clock-names = "bus", "core"; ++ operating-points-v2 = <&gpu_opp_table>; ++ power-domains = <&power RK3328_PD_GPU>; + resets = <&cru SRST_GPU_A>; ++ #cooling-cells = <2>; ++ }; ++ ++ gpu_opp_table: gpu-opp-table { ++ compatible = "operating-points-v2"; ++ ++ opp-200000000 { ++ opp-hz = /bits/ 64 <200000000>; ++ opp-microvolt = <1075000>; ++ }; ++ opp-300000000 { ++ opp-hz = /bits/ 64 <300000000>; ++ opp-microvolt = <1075000>; ++ }; ++ opp-400000000 { ++ opp-hz = /bits/ 64 <400000000>; ++ opp-microvolt = <1075000>; ++ }; ++ opp-500000000 { ++ opp-hz = /bits/ 64 <500000000>; ++ opp-microvolt = <1150000>; ++ status = "disabled"; ++ }; + }; + + h265e_mmu: iommu@ff330200 { + +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Alex Bee +Date: Tue, 2 Feb 2021 17:22:21 +0200 +Subject: [PATCH] ARM: dts: RK3288 miqi add hdmi sound nodes + +Signed-off-by: Alex Bee +--- + arch/arm/boot/dts/rockchip/rk3288-miqi.dts | 20 ++++++++++++++++++++ + 1 file changed, 20 insertions(+) + +diff --git a/arch/arm/boot/dts/rockchip/rk3288-miqi.dts b/arch/arm/boot/dts/rockchip/rk3288-miqi.dts +index 713f55e143c6..8d30c49f406e 100644 +--- a/arch/arm/boot/dts/rockchip/rk3288-miqi.dts ++++ b/arch/arm/boot/dts/rockchip/rk3288-miqi.dts +@@ -78,6 +78,21 @@ vcc_sys: vsys-regulator { + regulator-always-on; + regulator-boot-on; + }; ++ ++ sound { ++ compatible = "simple-audio-card"; ++ simple-audio-card,format = "i2s"; ++ simple-audio-card,name = "HDMI"; ++ simple-audio-card,mclk-fs = <512>; ++ ++ simple-audio-card,codec { ++ sound-dai = <&hdmi>; ++ }; ++ ++ simple-audio-card,cpu { ++ sound-dai = <&i2s>; ++ }; ++ }; + }; + + &cpu0 { +@@ -284,6 +299,11 @@ &i2c5 { + status = "okay"; + }; + ++&i2s { ++ #sound-dai-cells = <0>; ++ status = "okay"; ++}; ++ + &io_domains { + status = "okay"; + + +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Alex Bee +Date: Fri, 2 Apr 2021 17:54:22 +0200 +Subject: [PATCH] ARM/arm64: dts: rockchip: align sound card names + +Signed-off-by: Alex Bee +--- + arch/arm/boot/dts/rockchip/rk3288-tinker.dtsi | 2 +- + arch/arm64/boot/dts/rockchip/rk3399-base.dtsi | 2 +- + 2 files changed, 2 insertions(+), 2 deletions(-) + +diff --git a/arch/arm/boot/dts/rockchip/rk3288-tinker.dtsi b/arch/arm/boot/dts/rockchip/rk3288-tinker.dtsi +index 09618bb7d872..db9106a3dd22 100644 +--- a/arch/arm/boot/dts/rockchip/rk3288-tinker.dtsi ++++ b/arch/arm/boot/dts/rockchip/rk3288-tinker.dtsi +@@ -73,7 +73,7 @@ sdio_pwrseq: sdio-pwrseq { + sound { + compatible = "simple-audio-card"; + simple-audio-card,format = "i2s"; +- simple-audio-card,name = "rockchip,tinker-codec"; ++ simple-audio-card,name = "HDMI"; + simple-audio-card,mclk-fs = <512>; + + simple-audio-card,codec { +diff --git a/arch/arm64/boot/dts/rockchip/rk3399-base.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-base.dtsi +index 093ebe070775..a10fe60b7680 100644 +--- a/arch/arm64/boot/dts/rockchip/rk3399-base.dtsi ++++ b/arch/arm64/boot/dts/rockchip/rk3399-base.dtsi +@@ -1893,7 +1893,7 @@ hdmi_sound: hdmi-sound { + compatible = "simple-audio-card"; + simple-audio-card,format = "i2s"; + simple-audio-card,mclk-fs = <256>; +- simple-audio-card,name = "hdmi-sound"; ++ simple-audio-card,name = "HDMI"; + status = "disabled"; + + simple-audio-card,cpu { + +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Jonas Karlman +Date: Sun, 25 Mar 2018 22:17:06 +0200 +Subject: [PATCH] ASoC: hdmi-codec: fix channel allocation + +--- + sound/soc/codecs/hdmi-codec.c | 113 ++++++++++++++++------------------ + 1 file changed, 52 insertions(+), 61 deletions(-) + +diff --git a/sound/soc/codecs/hdmi-codec.c b/sound/soc/codecs/hdmi-codec.c +index 5679102de91f..f0cd183f7873 100644 +--- a/sound/soc/codecs/hdmi-codec.c ++++ b/sound/soc/codecs/hdmi-codec.c +@@ -194,78 +194,69 @@ static const struct snd_pcm_chmap_elem hdmi_codec_8ch_chmaps[] = { + */ + static const struct hdmi_codec_cea_spk_alloc hdmi_codec_channel_alloc[] = { + { .ca_id = 0x00, .n_ch = 2, +- .mask = FL | FR}, +- /* 2.1 */ +- { .ca_id = 0x01, .n_ch = 4, +- .mask = FL | FR | LFE}, +- /* Dolby Surround */ ++ .mask = FL | FR }, ++ { .ca_id = 0x03, .n_ch = 4, ++ .mask = FL | FR | LFE | FC }, + { .ca_id = 0x02, .n_ch = 4, + .mask = FL | FR | FC }, +- /* surround51 */ ++ { .ca_id = 0x01, .n_ch = 4, ++ .mask = FL | FR | LFE }, + { .ca_id = 0x0b, .n_ch = 6, +- .mask = FL | FR | LFE | FC | RL | RR}, +- /* surround40 */ +- { .ca_id = 0x08, .n_ch = 6, +- .mask = FL | FR | RL | RR }, +- /* surround41 */ +- { .ca_id = 0x09, .n_ch = 6, +- .mask = FL | FR | LFE | RL | RR }, +- /* surround50 */ ++ .mask = FL | FR | LFE | FC | RL | RR }, + { .ca_id = 0x0a, .n_ch = 6, + .mask = FL | FR | FC | RL | RR }, +- /* 6.1 */ +- { .ca_id = 0x0f, .n_ch = 8, +- .mask = FL | FR | LFE | FC | RL | RR | RC }, +- /* surround71 */ ++ { .ca_id = 0x09, .n_ch = 6, ++ .mask = FL | FR | LFE | RL | RR }, ++ { .ca_id = 0x08, .n_ch = 6, ++ .mask = FL | FR | RL | RR }, ++ { .ca_id = 0x07, .n_ch = 6, ++ .mask = FL | FR | LFE | FC | RC }, ++ { .ca_id = 0x06, .n_ch = 6, ++ .mask = FL | FR | FC | RC }, ++ { .ca_id = 0x05, .n_ch = 6, ++ .mask = FL | FR | LFE | RC }, ++ { .ca_id = 0x04, .n_ch = 6, ++ .mask = FL | FR | RC }, + { .ca_id = 0x13, .n_ch = 8, + .mask = FL | FR | LFE | FC | RL | RR | RLC | RRC }, +- /* others */ +- { .ca_id = 0x03, .n_ch = 8, +- .mask = FL | FR | LFE | FC }, +- { .ca_id = 0x04, .n_ch = 8, +- .mask = FL | FR | RC}, +- { .ca_id = 0x05, .n_ch = 8, +- .mask = FL | FR | LFE | RC }, +- { .ca_id = 0x06, .n_ch = 8, +- .mask = FL | FR | FC | RC }, +- { .ca_id = 0x07, .n_ch = 8, +- .mask = FL | FR | LFE | FC | RC }, +- { .ca_id = 0x0c, .n_ch = 8, +- .mask = FL | FR | RC | RL | RR }, +- { .ca_id = 0x0d, .n_ch = 8, +- .mask = FL | FR | LFE | RL | RR | RC }, +- { .ca_id = 0x0e, .n_ch = 8, +- .mask = FL | FR | FC | RL | RR | RC }, +- { .ca_id = 0x10, .n_ch = 8, +- .mask = FL | FR | RL | RR | RLC | RRC }, +- { .ca_id = 0x11, .n_ch = 8, +- .mask = FL | FR | LFE | RL | RR | RLC | RRC }, ++ { .ca_id = 0x1f, .n_ch = 8, ++ .mask = FL | FR | LFE | FC | RL | RR | FLC | FRC }, + { .ca_id = 0x12, .n_ch = 8, + .mask = FL | FR | FC | RL | RR | RLC | RRC }, +- { .ca_id = 0x14, .n_ch = 8, +- .mask = FL | FR | FLC | FRC }, +- { .ca_id = 0x15, .n_ch = 8, +- .mask = FL | FR | LFE | FLC | FRC }, +- { .ca_id = 0x16, .n_ch = 8, +- .mask = FL | FR | FC | FLC | FRC }, +- { .ca_id = 0x17, .n_ch = 8, +- .mask = FL | FR | LFE | FC | FLC | FRC }, +- { .ca_id = 0x18, .n_ch = 8, +- .mask = FL | FR | RC | FLC | FRC }, +- { .ca_id = 0x19, .n_ch = 8, +- .mask = FL | FR | LFE | RC | FLC | FRC }, +- { .ca_id = 0x1a, .n_ch = 8, +- .mask = FL | FR | RC | FC | FLC | FRC }, +- { .ca_id = 0x1b, .n_ch = 8, +- .mask = FL | FR | LFE | RC | FC | FLC | FRC }, +- { .ca_id = 0x1c, .n_ch = 8, +- .mask = FL | FR | RL | RR | FLC | FRC }, +- { .ca_id = 0x1d, .n_ch = 8, +- .mask = FL | FR | LFE | RL | RR | FLC | FRC }, + { .ca_id = 0x1e, .n_ch = 8, + .mask = FL | FR | FC | RL | RR | FLC | FRC }, +- { .ca_id = 0x1f, .n_ch = 8, +- .mask = FL | FR | LFE | FC | RL | RR | FLC | FRC }, ++ { .ca_id = 0x11, .n_ch = 8, ++ .mask = FL | FR | LFE | RL | RR | RLC | RRC }, ++ { .ca_id = 0x1d, .n_ch = 8, ++ .mask = FL | FR | LFE | RL | RR | FLC | FRC }, ++ { .ca_id = 0x10, .n_ch = 8, ++ .mask = FL | FR | RL | RR | RLC | RRC }, ++ { .ca_id = 0x1c, .n_ch = 8, ++ .mask = FL | FR | RL | RR | FLC | FRC }, ++ { .ca_id = 0x0f, .n_ch = 8, ++ .mask = FL | FR | LFE | FC | RL | RR | RC }, ++ { .ca_id = 0x1b, .n_ch = 8, ++ .mask = FL | FR | LFE | RC | FC | FLC | FRC }, ++ { .ca_id = 0x0e, .n_ch = 8, ++ .mask = FL | FR | FC | RL | RR | RC }, ++ { .ca_id = 0x1a, .n_ch = 8, ++ .mask = FL | FR | RC | FC | FLC | FRC }, ++ { .ca_id = 0x0d, .n_ch = 8, ++ .mask = FL | FR | LFE | RL | RR | RC }, ++ { .ca_id = 0x19, .n_ch = 8, ++ .mask = FL | FR | LFE | RC | FLC | FRC }, ++ { .ca_id = 0x0c, .n_ch = 8, ++ .mask = FL | FR | RC | RL | RR }, ++ { .ca_id = 0x18, .n_ch = 8, ++ .mask = FL | FR | RC | FLC | FRC }, ++ { .ca_id = 0x17, .n_ch = 8, ++ .mask = FL | FR | LFE | FC | FLC | FRC }, ++ { .ca_id = 0x16, .n_ch = 8, ++ .mask = FL | FR | FC | FLC | FRC }, ++ { .ca_id = 0x15, .n_ch = 8, ++ .mask = FL | FR | LFE | FLC | FRC }, ++ { .ca_id = 0x14, .n_ch = 8, ++ .mask = FL | FR | FLC | FRC }, + }; + + struct hdmi_codec_priv { + +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Alex Bee +Date: Sat, 27 Feb 2021 17:52:02 +0100 +Subject: [PATCH] arm64: dts: rockchip: add SPDIF nodes for RK3328 A1 board + +Signed-off-by: Alex Bee +--- + arch/arm64/boot/dts/rockchip/rk3328-a1.dts | 23 ++++++++++++++++++++++ + 1 file changed, 23 insertions(+) + +diff --git a/arch/arm64/boot/dts/rockchip/rk3328-a1.dts b/arch/arm64/boot/dts/rockchip/rk3328-a1.dts +index 40bf808642b9..27a1799027c2 100644 +--- a/arch/arm64/boot/dts/rockchip/rk3328-a1.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3328-a1.dts +@@ -57,6 +57,24 @@ ir-receiver { + gpios = <&gpio2 RK_PA2 GPIO_ACTIVE_LOW>; + linux,rc-map-name = "rc-beelink-gs1"; + }; ++ ++ spdif_sound: spdif-sound { ++ compatible = "simple-audio-card"; ++ simple-audio-card,name = "SPDIF"; ++ ++ simple-audio-card,cpu { ++ sound-dai = <&spdif>; ++ }; ++ ++ simple-audio-card,codec { ++ sound-dai = <&spdif_dit>; ++ }; ++ }; ++ ++ spdif_dit: spdif-dit { ++ compatible = "linux,spdif-dit"; ++ #sound-dai-cells = <0>; ++ }; + }; + + &analog_sound { +@@ -325,6 +343,11 @@ &sdmmc { + status = "okay"; + }; + ++&spdif { ++ pinctrl-0 = <&spdifm0_tx>; ++ status = "okay"; ++}; ++ + &tsadc { + rockchip,hw-tshut-mode = <0>; + rockchip,hw-tshut-polarity = <0>; + +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Alex Bee +Date: Sat, 27 Feb 2021 18:01:13 +0100 +Subject: [PATCH] arm64: dts: rockchip: Add ir-receiver node for RK3328 ROC CC + +Signed-off-by: Alex Bee +--- + arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts | 14 ++++++++++++++ + 1 file changed, 14 insertions(+) + +diff --git a/arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts b/arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts +index 51c7723d6762..cf321302daec 100644 +--- a/arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts +@@ -88,6 +88,13 @@ vcc_phy: vcc-phy-regulator { + regulator-boot-on; + }; + ++ ir-receiver { ++ compatible = "gpio-ir-receiver"; ++ gpios = <&gpio2 RK_PA2 GPIO_ACTIVE_LOW>; ++ pinctrl-0 = <&ir_int>; ++ pinctrl-names = "default"; ++ }; ++ + leds { + compatible = "gpio-leds"; + +@@ -312,6 +319,13 @@ &io_domains { + }; + + &pinctrl { ++ ++ ir { ++ ir_int: ir-int { ++ rockchip,pins = <2 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ }; ++ + pmic { + pmic_int_l: pmic-int-l { + rockchip,pins = <1 RK_PD0 RK_FUNC_GPIO &pcfg_pull_up>; + +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Alex Bee +Date: Mon, 1 Mar 2021 21:24:15 +0100 +Subject: [PATCH] ARM: dts: add cec pinctrl for RK3288 miqi board + +--- + arch/arm/boot/dts/rockchip/rk3288-miqi.dts | 2 ++ + 1 file changed, 2 insertions(+) + +diff --git a/arch/arm/boot/dts/rockchip/rk3288-miqi.dts b/arch/arm/boot/dts/rockchip/rk3288-miqi.dts +index 8d30c49f406e..6d90db5a3b75 100644 +--- a/arch/arm/boot/dts/rockchip/rk3288-miqi.dts ++++ b/arch/arm/boot/dts/rockchip/rk3288-miqi.dts +@@ -145,6 +145,8 @@ &gpu { + + &hdmi { + ddc-i2c-bus = <&i2c5>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&hdmi_cec_c0>; + status = "okay"; + }; + + +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Alex Bee +Date: Mon, 1 Mar 2021 19:22:15 +0100 +Subject: [PATCH] HACK: arm64: dts: enable FE phy for Beelink A1 also + +--- + arch/arm64/boot/dts/rockchip/rk3328-a1.dts | 8 ++++++++ + 1 file changed, 8 insertions(+) + +diff --git a/arch/arm64/boot/dts/rockchip/rk3328-a1.dts b/arch/arm64/boot/dts/rockchip/rk3328-a1.dts +index 27a1799027c2..7de9dfa71d89 100644 +--- a/arch/arm64/boot/dts/rockchip/rk3328-a1.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3328-a1.dts +@@ -147,6 +147,14 @@ rtl8211f: ethernet-phy@0 { + }; + }; + ++&gmac2phy { ++ clock_in_out = "output"; ++ assigned-clock-rate = <50000000>; ++ assigned-clocks = <&cru SCLK_MAC2PHY>; ++ assigned-clock-parents = <&cru SCLK_MAC2PHY_SRC>; ++ status = "okay"; ++}; ++ + &gpu { + mali-supply = <&vdd_logic>; + }; + +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Jonas Karlman +Date: Tue, 26 Feb 2019 20:45:14 +0000 +Subject: [PATCH] WIP: dw-hdmi-cec: sleep 100ms on error + +--- + drivers/gpu/drm/bridge/synopsys/dw-hdmi-cec.c | 18 ++++++++++++++++-- + 1 file changed, 16 insertions(+), 2 deletions(-) + +diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi-cec.c b/drivers/gpu/drm/bridge/synopsys/dw-hdmi-cec.c +index c8f44bcb298a..d4280ce4542c 100644 +--- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi-cec.c ++++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi-cec.c +@@ -4,6 +4,7 @@ + * + * Copyright (C) 2015-2017 Russell King. + */ ++#include + #include + #include + #include +@@ -129,8 +130,15 @@ static irqreturn_t dw_hdmi_cec_hardirq(int irq, void *data) + + dw_hdmi_write(cec, stat, HDMI_IH_CEC_STAT0); + +- if (stat & CEC_STAT_ERROR_INIT) { +- cec->tx_status = CEC_TX_STATUS_ERROR; ++ /* Status with both done and error_initiator bits have been seen ++ * on Rockchip RK3328 devices, transmit attempt seems to have failed ++ * when this happens, report as low drive and block cec-framework ++ * 100ms before core retransmits the failed message, this seems to ++ * mitigate the issue with failed transmit attempts. ++ */ ++ if ((stat & (CEC_STAT_DONE|CEC_STAT_ERROR_INIT)) == (CEC_STAT_DONE|CEC_STAT_ERROR_INIT)) { ++ pr_debug("dw_hdmi_cec_hardirq: stat=%02x LOW_DRIVE\n", stat); ++ cec->tx_status = CEC_TX_STATUS_LOW_DRIVE; + cec->tx_done = true; + ret = IRQ_WAKE_THREAD; + } else if (stat & CEC_STAT_DONE) { +@@ -141,6 +149,10 @@ static irqreturn_t dw_hdmi_cec_hardirq(int irq, void *data) + cec->tx_status = CEC_TX_STATUS_NACK; + cec->tx_done = true; + ret = IRQ_WAKE_THREAD; ++ } else if (stat & CEC_STAT_ERROR_INIT) { ++ cec->tx_status = CEC_TX_STATUS_ERROR; ++ cec->tx_done = true; ++ ret = IRQ_WAKE_THREAD; + } + + if (stat & CEC_STAT_EOM) { +@@ -173,6 +185,8 @@ static irqreturn_t dw_hdmi_cec_thread(int irq, void *data) + + if (cec->tx_done) { + cec->tx_done = false; ++ if (cec->tx_status == CEC_TX_STATUS_LOW_DRIVE) ++ msleep(100); + cec_transmit_attempt_done(adap, cec->tx_status); + } + if (cec->rx_done) { + +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Alex Bee +Date: Wed, 5 May 2021 19:11:12 +0200 +Subject: [PATCH] arm64: boot: dts: Increase ACLK_PERILP0 clock rate for RK3399 + +As per vendor kernel. Leaving this clock at the lower rate will +result in poor DMA controller performance + +Signed-off-by: Alex Bee +--- + arch/arm64/boot/dts/rockchip/rk3399-base.dtsi | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/arch/arm64/boot/dts/rockchip/rk3399-base.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-base.dtsi +index a10fe60b7680..dbe6a9cb98a5 100644 +--- a/arch/arm64/boot/dts/rockchip/rk3399-base.dtsi ++++ b/arch/arm64/boot/dts/rockchip/rk3399-base.dtsi +@@ -1477,7 +1477,7 @@ cru: clock-controller@ff760000 { + <1000000000>, + <150000000>, <75000000>, + <37500000>, +- <100000000>, <100000000>, ++ <300000000>, <100000000>, + <50000000>, <600000000>, + <100000000>, <50000000>, + <400000000>, <400000000>, + +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Alex Bee +Date: Sat, 21 Aug 2021 17:04:46 +0200 +Subject: [PATCH] arm64: dts: rockchip: Enable USB3 for rk3328 Beelink A1 + +Signed-off-by: Alex Bee +--- + arch/arm64/boot/dts/rockchip/rk3328-a1.dts | 5 +++++ + 1 file changed, 5 insertions(+) + +diff --git a/arch/arm64/boot/dts/rockchip/rk3328-a1.dts b/arch/arm64/boot/dts/rockchip/rk3328-a1.dts +index 7de9dfa71d89..e857e5a727f4 100644 +--- a/arch/arm64/boot/dts/rockchip/rk3328-a1.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3328-a1.dts +@@ -389,6 +389,11 @@ &usb_host0_ehci { + status = "okay"; + }; + ++&usbdrd3 { ++ dr_mode = "host"; ++ status = "okay"; ++}; ++ + &vop { + status = "okay"; + }; + +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Alex Bee +Date: Sat, 30 Oct 2021 12:19:19 +0200 +Subject: [PATCH] WIP: drm: bridge: dw-hdmi: switch from .hw_parmas to .prepare + for i2s + +Seems to be the only way to get AES bits correctly as set by +userspace. +TODO: check other consequences. + +Signed-off-by: Alex Bee +--- + drivers/gpu/drm/bridge/synopsys/dw-hdmi-i2s-audio.c | 8 ++++---- + 1 file changed, 4 insertions(+), 4 deletions(-) + +diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi-i2s-audio.c b/drivers/gpu/drm/bridge/synopsys/dw-hdmi-i2s-audio.c +index a2f0860b20bb..8961f9c7885d 100644 +--- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi-i2s-audio.c ++++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi-i2s-audio.c +@@ -34,9 +34,9 @@ static inline u8 hdmi_read(struct dw_hdmi_i2s_audio_data *audio, int offset) + return audio->read(hdmi, offset); + } + +-static int dw_hdmi_i2s_hw_params(struct device *dev, void *data, +- struct hdmi_codec_daifmt *fmt, +- struct hdmi_codec_params *hparms) ++static int dw_hdmi_i2s_prepare(struct device *dev, void *data, ++ struct hdmi_codec_daifmt *fmt, ++ struct hdmi_codec_params *hparms) + { + struct dw_hdmi_i2s_audio_data *audio = data; + struct dw_hdmi *hdmi = audio->hdmi; +@@ -178,7 +178,7 @@ static int dw_hdmi_i2s_hook_plugged_cb(struct device *dev, void *data, + } + + static const struct hdmi_codec_ops dw_hdmi_i2s_ops = { +- .hw_params = dw_hdmi_i2s_hw_params, ++ .prepare = dw_hdmi_i2s_prepare, + .audio_startup = dw_hdmi_i2s_audio_startup, + .audio_shutdown = dw_hdmi_i2s_audio_shutdown, + .get_eld = dw_hdmi_i2s_get_eld, + +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Alex Bee +Date: Sun, 18 Sep 2022 10:35:52 +0200 +Subject: [PATCH] arm64: dts: rockchip: Disbake fusb for rk3399-roc-pc + +As it will lead to an unbootable device in case one if those ports +is used to power up the device. +See https://lkml.org/lkml/2022/6/20/413 +--- + arch/arm64/boot/dts/rockchip/rk3399-roc-pc.dtsi | 6 +++--- + 1 file changed, 3 insertions(+), 3 deletions(-) + +diff --git a/arch/arm64/boot/dts/rockchip/rk3399-roc-pc.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-roc-pc.dtsi +index 2f4b1b2e3ac7..7217ead94d39 100644 +--- a/arch/arm64/boot/dts/rockchip/rk3399-roc-pc.dtsi ++++ b/arch/arm64/boot/dts/rockchip/rk3399-roc-pc.dtsi +@@ -215,7 +215,7 @@ vdd_log: vdd-log { + regulator-name = "vdd_log"; + regulator-always-on; + regulator-boot-on; +- regulator-min-microvolt = <450000>; ++ regulator-min-microvolt = <430000>; + regulator-max-microvolt = <1400000>; + pwm-supply = <&vcc3v3_sys>; + }; +@@ -536,7 +536,7 @@ fusb1: usb-typec@22 { + pinctrl-names = "default"; + pinctrl-0 = <&fusb1_int>; + vbus-supply = <&vcc_vbus_typec1>; +- status = "okay"; ++ status = "disabled"; + }; + }; + +@@ -553,7 +553,7 @@ fusb0: usb-typec@22 { + pinctrl-names = "default"; + pinctrl-0 = <&fusb0_int>; + vbus-supply = <&vcc_vbus_typec0>; +- status = "okay"; ++ status = "disabled"; + }; + + mp8859: regulator@66 { diff --git a/patch/kernel/archive/rockchip-6.12/patches.libreelec/linux-2000-v4l2-wip-rkvdec-hevc.patch b/patch/kernel/archive/rockchip-6.12/patches.libreelec/linux-2000-v4l2-wip-rkvdec-hevc.patch new file mode 100644 index 000000000000..58b3e72e5a27 --- /dev/null +++ b/patch/kernel/archive/rockchip-6.12/patches.libreelec/linux-2000-v4l2-wip-rkvdec-hevc.patch @@ -0,0 +1,3226 @@ +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Jonas Karlman +Date: Sat, 23 May 2020 15:17:45 +0000 +Subject: [PATCH] WIP: media: rkvdec: add HEVC backend + +NOTE: cabac table and scailing list code is copied 1:1 from mpp +TODO: fix lowdelay flag and rework the scaling list part + +Signed-off-by: Jonas Karlman +Signed-off-by: Alex Bee +--- + drivers/staging/media/rkvdec/Makefile | 2 +- + drivers/staging/media/rkvdec/rkvdec-hevc.c | 2572 ++++++++++++++++++++ + drivers/staging/media/rkvdec/rkvdec-regs.h | 1 + + drivers/staging/media/rkvdec/rkvdec.c | 73 +- + drivers/staging/media/rkvdec/rkvdec.h | 1 + + 5 files changed, 2647 insertions(+), 2 deletions(-) + create mode 100644 drivers/staging/media/rkvdec/rkvdec-hevc.c + +diff --git a/drivers/staging/media/rkvdec/Makefile b/drivers/staging/media/rkvdec/Makefile +index cb86b429cfaa..a77122641d14 100644 +--- a/drivers/staging/media/rkvdec/Makefile ++++ b/drivers/staging/media/rkvdec/Makefile +@@ -1,3 +1,3 @@ + obj-$(CONFIG_VIDEO_ROCKCHIP_VDEC) += rockchip-vdec.o + +-rockchip-vdec-y += rkvdec.o rkvdec-h264.o rkvdec-vp9.o ++rockchip-vdec-y += rkvdec.o rkvdec-h264.o rkvdec-hevc.o rkvdec-vp9.o +diff --git a/drivers/staging/media/rkvdec/rkvdec-hevc.c b/drivers/staging/media/rkvdec/rkvdec-hevc.c +new file mode 100644 +index 000000000000..7a375a23eaf1 +--- /dev/null ++++ b/drivers/staging/media/rkvdec/rkvdec-hevc.c +@@ -0,0 +1,2572 @@ ++// SPDX-License-Identifier: GPL-2.0 ++/* ++ * Rockchip Video Decoder HEVC backend ++ * ++ * Copyright (C) 2019 Collabora, Ltd. ++ * Boris Brezillon ++ * ++ * Copyright (C) 2016 Rockchip Electronics Co., Ltd. ++ * Jeffy Chen ++ */ ++ ++#include ++ ++#include "rkvdec.h" ++#include "rkvdec-regs.h" ++ ++/* Size in u8/u32 units. */ ++#define RKV_CABAC_TABLE_SIZE 27456 ++#define RKV_SCALING_LIST_SIZE 1360 ++#define RKV_PPS_SIZE (80 / 4) ++#define RKV_PPS_LEN 64 ++#define RKV_RPS_SIZE (32 / 4) ++#define RKV_RPS_LEN 600 ++ ++struct rkvdec_sps_pps_packet { ++ u32 info[RKV_PPS_SIZE]; ++}; ++ ++struct rkvdec_rps_packet { ++ u32 info[RKV_RPS_SIZE]; ++}; ++ ++struct rkvdec_ps_field { ++ u16 offset; ++ u8 len; ++}; ++ ++#define PS_FIELD(_offset, _len) \ ++ ((struct rkvdec_ps_field){ _offset, _len }) ++ ++/* SPS */ ++#define VIDEO_PARAMETER_SET_ID PS_FIELD(0, 4) ++#define SEQ_PARAMETER_SET_ID PS_FIELD(4, 4) ++#define CHROMA_FORMAT_IDC PS_FIELD(8, 2) ++#define PIC_WIDTH_IN_LUMA_SAMPLES PS_FIELD(10, 13) ++#define PIC_HEIGHT_IN_LUMA_SAMPLES PS_FIELD(23, 13) ++#define BIT_DEPTH_LUMA PS_FIELD(36, 4) ++#define BIT_DEPTH_CHROMA PS_FIELD(40, 4) ++#define LOG2_MAX_PIC_ORDER_CNT_LSB PS_FIELD(44, 5) ++#define LOG2_DIFF_MAX_MIN_LUMA_CODING_BLOCK_SIZE PS_FIELD(49, 2) ++#define LOG2_MIN_LUMA_CODING_BLOCK_SIZE PS_FIELD(51, 3) ++#define LOG2_MIN_TRANSFORM_BLOCK_SIZE PS_FIELD(54, 3) ++#define LOG2_DIFF_MAX_MIN_LUMA_TRANSFORM_BLOCK_SIZE PS_FIELD(57, 2) ++#define MAX_TRANSFORM_HIERARCHY_DEPTH_INTER PS_FIELD(59, 3) ++#define MAX_TRANSFORM_HIERARCHY_DEPTH_INTRA PS_FIELD(62, 3) ++#define SCALING_LIST_ENABLED_FLAG PS_FIELD(65, 1) ++#define AMP_ENABLED_FLAG PS_FIELD(66, 1) ++#define SAMPLE_ADAPTIVE_OFFSET_ENABLED_FLAG PS_FIELD(67, 1) ++#define PCM_ENABLED_FLAG PS_FIELD(68, 1) ++#define PCM_SAMPLE_BIT_DEPTH_LUMA PS_FIELD(69, 4) ++#define PCM_SAMPLE_BIT_DEPTH_CHROMA PS_FIELD(73, 4) ++#define PCM_LOOP_FILTER_DISABLED_FLAG PS_FIELD(77, 1) ++#define LOG2_DIFF_MAX_MIN_PCM_LUMA_CODING_BLOCK_SIZE PS_FIELD(78, 3) ++#define LOG2_MIN_PCM_LUMA_CODING_BLOCK_SIZE PS_FIELD(81, 3) ++#define NUM_SHORT_TERM_REF_PIC_SETS PS_FIELD(84, 7) ++#define LONG_TERM_REF_PICS_PRESENT_FLAG PS_FIELD(91, 1) ++#define NUM_LONG_TERM_REF_PICS_SPS PS_FIELD(92, 6) ++#define SPS_TEMPORAL_MVP_ENABLED_FLAG PS_FIELD(98, 1) ++#define STRONG_INTRA_SMOOTHING_ENABLED_FLAG PS_FIELD(99, 1) ++/* PPS */ ++#define PIC_PARAMETER_SET_ID PS_FIELD(128, 6) ++#define PPS_SEQ_PARAMETER_SET_ID PS_FIELD(134, 4) ++#define DEPENDENT_SLICE_SEGMENTS_ENABLED_FLAG PS_FIELD(138, 1) ++#define OUTPUT_FLAG_PRESENT_FLAG PS_FIELD(139, 1) ++#define NUM_EXTRA_SLICE_HEADER_BITS PS_FIELD(140, 13) ++#define SIGN_DATA_HIDING_ENABLED_FLAG PS_FIELD(153, 1) ++#define CABAC_INIT_PRESENT_FLAG PS_FIELD(154, 1) ++#define NUM_REF_IDX_L0_DEFAULT_ACTIVE PS_FIELD(155, 4) ++#define NUM_REF_IDX_L1_DEFAULT_ACTIVE PS_FIELD(159, 4) ++#define INIT_QP_MINUS26 PS_FIELD(163, 7) ++#define CONSTRAINED_INTRA_PRED_FLAG PS_FIELD(170, 1) ++#define TRANSFORM_SKIP_ENABLED_FLAG PS_FIELD(171, 1) ++#define CU_QP_DELTA_ENABLED_FLAG PS_FIELD(172, 1) ++#define LOG2_MIN_CU_QP_DELTA_SIZE PS_FIELD(173, 3) ++#define PPS_CB_QP_OFFSET PS_FIELD(176, 5) ++#define PPS_CR_QP_OFFSET PS_FIELD(181, 5) ++#define PPS_SLICE_CHROMA_QP_OFFSETS_PRESENT_FLAG PS_FIELD(186, 1) ++#define WEIGHTED_PRED_FLAG PS_FIELD(187, 1) ++#define WEIGHTED_BIPRED_FLAG PS_FIELD(188, 1) ++#define TRANSQUANT_BYPASS_ENABLED_FLAG PS_FIELD(189, 1) ++#define TILES_ENABLED_FLAG PS_FIELD(190, 1) ++#define ENTROPY_CODING_SYNC_ENABLED_FLAG PS_FIELD(191, 1) ++#define PPS_LOOP_FILTER_ACROSS_SLICES_ENABLED_FLAG PS_FIELD(192, 1) ++#define LOOP_FILTER_ACROSS_TILES_ENABLED_FLAG PS_FIELD(193, 1) ++#define DEBLOCKING_FILTER_OVERRIDE_ENABLED_FLAG PS_FIELD(194, 1) ++#define PPS_DEBLOCKING_FILTER_DISABLED_FLAG PS_FIELD(195, 1) ++#define PPS_BETA_OFFSET_DIV2 PS_FIELD(196, 4) ++#define PPS_TC_OFFSET_DIV2 PS_FIELD(200, 4) ++#define LISTS_MODIFICATION_PRESENT_FLAG PS_FIELD(204, 1) ++#define LOG2_PARALLEL_MERGE_LEVEL PS_FIELD(205, 3) ++#define SLICE_SEGMENT_HEADER_EXTENSION_PRESENT_FLAG PS_FIELD(208, 1) ++#define NUM_TILE_COLUMNS PS_FIELD(212, 5) ++#define NUM_TILE_ROWS PS_FIELD(217, 5) ++#define COLUMN_WIDTH(i) PS_FIELD(256 + (i * 8), 8) ++#define ROW_HEIGHT(i) PS_FIELD(416 + (i * 8), 8) ++#define SCALING_LIST_ADDRESS PS_FIELD(592, 32) ++ ++/* Data structure describing auxiliary buffer format. */ ++struct rkvdec_hevc_priv_tbl { ++ u8 cabac_table[RKV_CABAC_TABLE_SIZE]; ++ u8 scaling_list[RKV_SCALING_LIST_SIZE]; ++ struct rkvdec_sps_pps_packet param_set[RKV_PPS_LEN]; ++ struct rkvdec_rps_packet rps[RKV_RPS_LEN]; ++}; ++ ++struct rkvdec_hevc_run { ++ struct rkvdec_run base; ++ const struct v4l2_ctrl_hevc_slice_params *slices_params; ++ const struct v4l2_ctrl_hevc_decode_params *decode_params; ++ const struct v4l2_ctrl_hevc_sps *sps; ++ const struct v4l2_ctrl_hevc_pps *pps; ++ const struct v4l2_ctrl_hevc_scaling_matrix *scaling_matrix; ++ int num_slices; ++}; ++ ++struct rkvdec_hevc_ctx { ++ struct rkvdec_aux_buf priv_tbl; ++ struct v4l2_ctrl_hevc_scaling_matrix scaling_matrix_cache; ++}; ++ ++// TODO: refactor scaling list code, was copied 1:1 from mpp ++ ++typedef struct ScalingList { ++ /* This is a little wasteful, since sizeID 0 only needs 8 coeffs, ++ * and size ID 3 only has 2 arrays, not 6. */ ++ u8 sl[4][6][64]; ++ u8 sl_dc[2][6]; ++} scalingList_t; ++ ++typedef struct ScalingFactor_Model { ++ u8 scalingfactor0[1248]; ++ u8 scalingfactor1[96]; /*4X4 TU Rotate, total 16X4*/ ++ u8 scalingdc[12]; /*N1005 Vienna Meeting*/ ++ u8 reserverd[4]; /*16Bytes align*/ ++} scalingFactor_t; ++ ++#define SCALING_LIST_SIZE_NUM 4 ++ ++static void ++hal_record_scaling_list(scalingFactor_t *pScalingFactor_out, ++ scalingList_t *pScalingList) ++{ ++ int i; ++ u32 g_scalingListNum_model[SCALING_LIST_SIZE_NUM] = {6, 6, 6, 2}; // from C Model ++ u32 nIndex = 0; ++ u32 sizeId, matrixId, listId; ++ u8 *p = pScalingFactor_out->scalingfactor0; ++ u8 tmpBuf[8 * 8]; ++ ++ //output non-default scalingFactor Table (1248 BYTES) ++ for (sizeId = 0; sizeId < SCALING_LIST_SIZE_NUM; sizeId++) { ++ for (listId = 0; listId < g_scalingListNum_model[sizeId]; listId++) { ++ if (sizeId < 3) { ++ for (i = 0; i < (sizeId == 0 ? 16 : 64); i++) { ++ pScalingFactor_out->scalingfactor0[nIndex++] = (u8)pScalingList->sl[sizeId][listId][i]; ++ } ++ } else { ++ for (i = 0; i < 64; i ++) { ++ pScalingFactor_out->scalingfactor0[nIndex++] = (u8)pScalingList->sl[sizeId][listId][i]; ++ } ++ for (i = 0; i < 128; i ++) { ++ pScalingFactor_out->scalingfactor0[nIndex++] = 0; ++ } ++ } ++ } ++ } ++ //output non-default scalingFactor Table Rotation(96 Bytes) ++ nIndex = 0; ++ for (listId = 0; listId < g_scalingListNum_model[0]; listId++) { ++ u8 temp16[16] = {0}; ++ for (i = 0; i < 16; i ++) { ++ temp16[i] = (u8)pScalingList->sl[0][listId][i]; ++ } ++ for (i = 0; i < 4; i ++) { ++ pScalingFactor_out->scalingfactor1[nIndex++] = temp16[i]; ++ pScalingFactor_out->scalingfactor1[nIndex++] = temp16[i + 4]; ++ pScalingFactor_out->scalingfactor1[nIndex++] = temp16[i + 8]; ++ pScalingFactor_out->scalingfactor1[nIndex++] = temp16[i + 12]; ++ } ++ } ++ //output non-default ScalingList_DC_Coeff (12 BYTES) ++ nIndex = 0; ++ for (listId = 0; listId < g_scalingListNum_model[2]; listId++) { //sizeId = 2 ++ pScalingFactor_out->scalingdc[nIndex++] = (u8)pScalingList->sl_dc[0][listId];// zrh warning: sl_dc differed from scalingList->getScalingListDC ++ } ++ for (listId = 0; listId < g_scalingListNum_model[3]; listId++) { //sizeId = 3 ++ pScalingFactor_out->scalingdc[nIndex++] = (u8)pScalingList->sl_dc[1][listId];// zrh warning: sl_dc differed from scalingList->getScalingListDC ++ pScalingFactor_out->scalingdc[nIndex++] = 0; ++ pScalingFactor_out->scalingdc[nIndex++] = 0; ++ } ++ ++ //align 16X address ++ nIndex = 0; ++ for (i = 0; i < 4; i ++) { ++ pScalingFactor_out->reserverd[nIndex++] = 0; ++ } ++ ++ //----------------------All above code show the normal store way in HM-------------------------- ++ //--------from now on, the scalingfactor0 is rotated 90', the scalingfactor1 is also rotated 90' ++ ++ //sizeId == 0 ++ for (matrixId = 0; matrixId < 6; matrixId++) { ++ p = pScalingFactor_out->scalingfactor0 + matrixId * 16; ++ ++ for (i = 0; i < 4; i++) { ++ tmpBuf[4 * 0 + i] = p[i * 4 + 0]; ++ tmpBuf[4 * 1 + i] = p[i * 4 + 1]; ++ tmpBuf[4 * 2 + i] = p[i * 4 + 2]; ++ tmpBuf[4 * 3 + i] = p[i * 4 + 3]; ++ } ++ memcpy(p, tmpBuf, 4 * 4 * sizeof(u8)); ++ } ++ //sizeId == 1 ++ for (matrixId = 0; matrixId < 6; matrixId++) { ++ p = pScalingFactor_out->scalingfactor0 + 6 * 16 + matrixId * 64; ++ ++ for (i = 0; i < 8; i++) { ++ tmpBuf[8 * 0 + i] = p[i * 8 + 0]; ++ tmpBuf[8 * 1 + i] = p[i * 8 + 1]; ++ tmpBuf[8 * 2 + i] = p[i * 8 + 2]; ++ tmpBuf[8 * 3 + i] = p[i * 8 + 3]; ++ tmpBuf[8 * 4 + i] = p[i * 8 + 4]; ++ tmpBuf[8 * 5 + i] = p[i * 8 + 5]; ++ tmpBuf[8 * 6 + i] = p[i * 8 + 6]; ++ tmpBuf[8 * 7 + i] = p[i * 8 + 7]; ++ } ++ memcpy(p, tmpBuf, 8 * 8 * sizeof(u8)); ++ } ++ //sizeId == 2 ++ for (matrixId = 0; matrixId < 6; matrixId++) { ++ p = pScalingFactor_out->scalingfactor0 + 6 * 16 + 6 * 64 + matrixId * 64; ++ ++ for (i = 0; i < 8; i++) { ++ tmpBuf[8 * 0 + i] = p[i * 8 + 0]; ++ tmpBuf[8 * 1 + i] = p[i * 8 + 1]; ++ tmpBuf[8 * 2 + i] = p[i * 8 + 2]; ++ tmpBuf[8 * 3 + i] = p[i * 8 + 3]; ++ tmpBuf[8 * 4 + i] = p[i * 8 + 4]; ++ tmpBuf[8 * 5 + i] = p[i * 8 + 5]; ++ tmpBuf[8 * 6 + i] = p[i * 8 + 6]; ++ tmpBuf[8 * 7 + i] = p[i * 8 + 7]; ++ } ++ memcpy(p, tmpBuf, 8 * 8 * sizeof(u8)); ++ } ++ //sizeId == 3 ++ for (matrixId = 0; matrixId < 6; matrixId++) { ++ p = pScalingFactor_out->scalingfactor0 + 6 * 16 + 6 * 64 + 6 * 64 + matrixId * 64; ++ ++ for (i = 0; i < 8; i++) { ++ tmpBuf[8 * 0 + i] = p[i * 8 + 0]; ++ tmpBuf[8 * 1 + i] = p[i * 8 + 1]; ++ tmpBuf[8 * 2 + i] = p[i * 8 + 2]; ++ tmpBuf[8 * 3 + i] = p[i * 8 + 3]; ++ tmpBuf[8 * 4 + i] = p[i * 8 + 4]; ++ tmpBuf[8 * 5 + i] = p[i * 8 + 5]; ++ tmpBuf[8 * 6 + i] = p[i * 8 + 6]; ++ tmpBuf[8 * 7 + i] = p[i * 8 + 7]; ++ } ++ memcpy(p, tmpBuf, 8 * 8 * sizeof(u8)); ++ } ++ ++ //sizeId == 0 ++ for (matrixId = 0; matrixId < 6; matrixId++) { ++ p = pScalingFactor_out->scalingfactor1 + matrixId * 16; ++ ++ for (i = 0; i < 4; i++) { ++ tmpBuf[4 * 0 + i] = p[i * 4 + 0]; ++ tmpBuf[4 * 1 + i] = p[i * 4 + 1]; ++ tmpBuf[4 * 2 + i] = p[i * 4 + 2]; ++ tmpBuf[4 * 3 + i] = p[i * 4 + 3]; ++ } ++ memcpy(p, tmpBuf, 4 * 4 * sizeof(u8)); ++ } ++} ++ ++static const u8 rkvdec_hevc_cabac_table[RKV_CABAC_TABLE_SIZE] = { ++ 0x07, 0x0f, 0x48, 0x58, 0x58, 0x40, 0x40, 0x40, 0x40, 0x40, 0x0f, 0x40, 0x40, 0x40, 0x0f, 0x68, ++ 0x48, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x07, 0x40, 0x40, 0x68, ++ 0x58, 0x60, 0x40, 0x1f, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x48, 0x48, 0x60, 0x60, 0x50, 0x58, ++ 0x50, 0x07, 0x58, 0x68, 0x50, 0x58, 0x68, 0x68, 0x68, 0x68, 0x68, 0x50, 0x48, 0x68, 0x60, 0x60, ++ 0x50, 0x58, 0x50, 0x07, 0x58, 0x68, 0x50, 0x58, 0x68, 0x68, 0x68, 0x68, 0x68, 0x50, 0x48, 0x68, ++ 0x48, 0x48, 0x1f, 0x58, 0x68, 0x68, 0x58, 0x60, 0x60, 0x60, 0x50, 0x50, 0x50, 0x48, 0x58, 0x58, ++ 0x37, 0x07, 0x58, 0x48, 0x58, 0x58, 0x37, 0x07, 0x58, 0x48, 0x58, 0x58, 0x37, 0x07, 0x58, 0x50, ++ 0x48, 0x1f, 0x1f, 0x0f, 0x0f, 0x0f, 0x0f, 0x07, 0x0f, 0x48, 0x68, 0x0f, 0x48, 0x68, 0x40, 0x40, ++ 0x50, 0x50, 0x07, 0x40, 0x50, 0x0f, 0x40, 0x48, 0x07, 0x40, 0x27, 0x50, 0x48, 0x48, 0x40, 0x0f, ++ 0x50, 0x37, 0x1f, 0x1f, 0x50, 0x37, 0x40, 0x27, 0x40, 0x07, 0x0f, 0x17, 0x0f, 0x0f, 0x40, 0x40, ++ 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x07, 0x0f, 0x47, 0x57, 0x58, 0x40, 0x40, 0x40, 0x40, 0x40, 0x0f, 0x40, 0x40, 0x40, 0x0f, 0x66, ++ 0x47, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x07, 0x00, 0x00, 0x67, ++ 0x57, 0x5e, 0x00, 0x1f, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x47, 0x47, 0x5f, 0x5f, 0x4f, 0x57, ++ 0x4f, 0x07, 0x57, 0x67, 0x4f, 0x57, 0x67, 0x67, 0x67, 0x67, 0x66, 0x4f, 0x47, 0x66, 0x5f, 0x5f, ++ 0x4f, 0x57, 0x4f, 0x07, 0x57, 0x67, 0x4f, 0x57, 0x67, 0x67, 0x67, 0x67, 0x66, 0x4f, 0x47, 0x66, ++ 0x46, 0x48, 0x20, 0x57, 0x67, 0x67, 0x57, 0x5f, 0x5f, 0x5e, 0x4f, 0x4f, 0x4f, 0x47, 0x57, 0x57, ++ 0x37, 0x07, 0x57, 0x47, 0x57, 0x57, 0x37, 0x07, 0x57, 0x47, 0x57, 0x57, 0x37, 0x07, 0x57, 0x4f, ++ 0x47, 0x1f, 0x1f, 0x0f, 0x10, 0x0f, 0x10, 0x07, 0x10, 0x47, 0x67, 0x10, 0x47, 0x67, 0x40, 0x40, ++ 0x4f, 0x4e, 0x08, 0x00, 0x4f, 0x0f, 0x00, 0x47, 0x07, 0x01, 0x27, 0x4e, 0x47, 0x47, 0x00, 0x0f, ++ 0x4f, 0x37, 0x1f, 0x1f, 0x4f, 0x36, 0x00, 0x27, 0x00, 0x07, 0x10, 0x17, 0x0f, 0x0f, 0x40, 0x40, ++ 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x07, 0x0e, 0x47, 0x57, 0x58, 0x40, 0x40, 0x40, 0x40, 0x40, 0x0e, 0x40, 0x40, 0x40, 0x0e, 0x64, ++ 0x47, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x07, 0x00, 0x00, 0x66, ++ 0x57, 0x5d, 0x00, 0x1e, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x47, 0x47, 0x5e, 0x5e, 0x4e, 0x56, ++ 0x4f, 0x07, 0x56, 0x66, 0x4f, 0x56, 0x66, 0x67, 0x66, 0x66, 0x64, 0x4e, 0x46, 0x64, 0x5e, 0x5e, ++ 0x4e, 0x56, 0x4f, 0x07, 0x56, 0x66, 0x4f, 0x56, 0x66, 0x67, 0x66, 0x66, 0x64, 0x4e, 0x46, 0x64, ++ 0x45, 0x48, 0x20, 0x57, 0x66, 0x66, 0x56, 0x5e, 0x5e, 0x5d, 0x4e, 0x4e, 0x4e, 0x46, 0x56, 0x57, ++ 0x36, 0x07, 0x56, 0x46, 0x56, 0x57, 0x36, 0x07, 0x56, 0x46, 0x56, 0x57, 0x36, 0x07, 0x56, 0x4f, ++ 0x47, 0x1e, 0x1e, 0x0f, 0x10, 0x0f, 0x10, 0x07, 0x10, 0x47, 0x66, 0x10, 0x47, 0x66, 0x40, 0x40, ++ 0x4f, 0x4d, 0x08, 0x00, 0x4f, 0x0f, 0x00, 0x47, 0x07, 0x03, 0x27, 0x4d, 0x47, 0x46, 0x01, 0x0f, ++ 0x4f, 0x36, 0x1f, 0x1e, 0x4f, 0x34, 0x01, 0x26, 0x00, 0x07, 0x10, 0x17, 0x0f, 0x0f, 0x40, 0x40, ++ 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x07, 0x0d, 0x47, 0x57, 0x58, 0x40, 0x40, 0x40, 0x40, 0x40, 0x0e, 0x40, 0x40, 0x40, 0x0e, 0x62, ++ 0x47, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x07, 0x00, 0x00, 0x65, ++ 0x57, 0x5c, 0x00, 0x1e, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x47, 0x47, 0x5d, 0x5d, 0x4e, 0x56, ++ 0x4f, 0x07, 0x56, 0x66, 0x4f, 0x55, 0x65, 0x67, 0x66, 0x65, 0x63, 0x4d, 0x46, 0x62, 0x5d, 0x5d, ++ 0x4e, 0x56, 0x4f, 0x07, 0x56, 0x66, 0x4f, 0x55, 0x65, 0x67, 0x66, 0x65, 0x63, 0x4d, 0x46, 0x62, ++ 0x44, 0x48, 0x20, 0x57, 0x65, 0x65, 0x56, 0x5d, 0x5d, 0x5c, 0x4e, 0x4d, 0x4e, 0x45, 0x56, 0x57, ++ 0x36, 0x07, 0x56, 0x45, 0x56, 0x57, 0x36, 0x07, 0x56, 0x45, 0x56, 0x57, 0x36, 0x07, 0x56, 0x4f, ++ 0x47, 0x1e, 0x1e, 0x0f, 0x10, 0x0f, 0x10, 0x07, 0x10, 0x47, 0x65, 0x10, 0x47, 0x65, 0x40, 0x40, ++ 0x4f, 0x4c, 0x08, 0x00, 0x4f, 0x0f, 0x00, 0x47, 0x07, 0x04, 0x27, 0x4c, 0x47, 0x45, 0x01, 0x0f, ++ 0x4f, 0x36, 0x1f, 0x1e, 0x4f, 0x33, 0x01, 0x25, 0x00, 0x07, 0x10, 0x17, 0x0f, 0x0f, 0x40, 0x40, ++ 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x07, 0x0c, 0x46, 0x56, 0x58, 0x40, 0x40, 0x40, 0x40, 0x40, 0x0d, 0x40, 0x40, 0x40, 0x0d, 0x60, ++ 0x46, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x07, 0x01, 0x01, 0x64, ++ 0x56, 0x5b, 0x01, 0x1d, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x46, 0x46, 0x5c, 0x5c, 0x4d, 0x55, ++ 0x4e, 0x07, 0x55, 0x65, 0x4e, 0x54, 0x64, 0x66, 0x65, 0x64, 0x61, 0x4c, 0x45, 0x60, 0x5c, 0x5c, ++ 0x4d, 0x55, 0x4e, 0x07, 0x55, 0x65, 0x4e, 0x54, 0x64, 0x66, 0x65, 0x64, 0x61, 0x4c, 0x45, 0x60, ++ 0x43, 0x49, 0x21, 0x56, 0x64, 0x64, 0x55, 0x5c, 0x5c, 0x5b, 0x4d, 0x4c, 0x4d, 0x44, 0x55, 0x56, ++ 0x35, 0x07, 0x55, 0x44, 0x55, 0x56, 0x35, 0x07, 0x55, 0x44, 0x55, 0x56, 0x35, 0x07, 0x55, 0x4e, ++ 0x46, 0x1d, 0x1d, 0x0f, 0x11, 0x0f, 0x11, 0x07, 0x11, 0x46, 0x64, 0x11, 0x46, 0x64, 0x40, 0x40, ++ 0x4e, 0x4b, 0x09, 0x01, 0x4e, 0x0f, 0x01, 0x46, 0x07, 0x06, 0x27, 0x4b, 0x46, 0x44, 0x02, 0x0f, ++ 0x4e, 0x35, 0x1e, 0x1d, 0x4e, 0x31, 0x02, 0x24, 0x01, 0x07, 0x11, 0x16, 0x0f, 0x0f, 0x40, 0x40, ++ 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x07, 0x0b, 0x46, 0x56, 0x58, 0x40, 0x40, 0x40, 0x40, 0x40, 0x0c, 0x40, 0x40, 0x40, 0x0c, 0x5e, ++ 0x46, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x07, 0x01, 0x01, 0x63, ++ 0x56, 0x59, 0x01, 0x1c, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x46, 0x46, 0x5b, 0x5b, 0x4c, 0x54, ++ 0x4e, 0x07, 0x54, 0x64, 0x4e, 0x53, 0x63, 0x66, 0x64, 0x63, 0x60, 0x4b, 0x44, 0x5e, 0x5b, 0x5b, ++ 0x4c, 0x54, 0x4e, 0x07, 0x54, 0x64, 0x4e, 0x53, 0x63, 0x66, 0x64, 0x63, 0x60, 0x4b, 0x44, 0x5e, ++ 0x41, 0x49, 0x21, 0x56, 0x63, 0x63, 0x54, 0x5b, 0x5b, 0x59, 0x4c, 0x4b, 0x4c, 0x43, 0x54, 0x56, ++ 0x34, 0x07, 0x54, 0x43, 0x54, 0x56, 0x34, 0x07, 0x54, 0x43, 0x54, 0x56, 0x34, 0x07, 0x54, 0x4e, ++ 0x46, 0x1c, 0x1c, 0x0f, 0x11, 0x0f, 0x11, 0x07, 0x11, 0x46, 0x63, 0x11, 0x46, 0x63, 0x40, 0x40, ++ 0x4e, 0x49, 0x09, 0x01, 0x4e, 0x0f, 0x01, 0x46, 0x07, 0x07, 0x27, 0x49, 0x46, 0x43, 0x03, 0x0f, ++ 0x4e, 0x34, 0x1e, 0x1c, 0x4e, 0x30, 0x03, 0x23, 0x01, 0x07, 0x11, 0x16, 0x0f, 0x0f, 0x40, 0x40, ++ 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x07, 0x0a, 0x46, 0x56, 0x58, 0x40, 0x40, 0x40, 0x40, 0x40, 0x0c, 0x40, 0x40, 0x40, 0x0c, 0x5c, ++ 0x46, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x07, 0x01, 0x01, 0x62, ++ 0x56, 0x58, 0x01, 0x1c, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x46, 0x46, 0x5a, 0x5a, 0x4c, 0x54, ++ 0x4e, 0x07, 0x54, 0x64, 0x4e, 0x52, 0x62, 0x66, 0x64, 0x62, 0x5e, 0x4a, 0x44, 0x5c, 0x5a, 0x5a, ++ 0x4c, 0x54, 0x4e, 0x07, 0x54, 0x64, 0x4e, 0x52, 0x62, 0x66, 0x64, 0x62, 0x5e, 0x4a, 0x44, 0x5c, ++ 0x40, 0x49, 0x21, 0x56, 0x62, 0x62, 0x54, 0x5a, 0x5a, 0x58, 0x4c, 0x4a, 0x4c, 0x42, 0x54, 0x56, ++ 0x34, 0x07, 0x54, 0x42, 0x54, 0x56, 0x34, 0x07, 0x54, 0x42, 0x54, 0x56, 0x34, 0x07, 0x54, 0x4e, ++ 0x46, 0x1c, 0x1c, 0x0f, 0x11, 0x0f, 0x11, 0x07, 0x11, 0x46, 0x62, 0x11, 0x46, 0x62, 0x40, 0x40, ++ 0x4e, 0x48, 0x09, 0x01, 0x4e, 0x0f, 0x01, 0x46, 0x07, 0x09, 0x27, 0x48, 0x46, 0x42, 0x03, 0x0f, ++ 0x4e, 0x34, 0x1e, 0x1c, 0x4e, 0x2e, 0x03, 0x22, 0x01, 0x07, 0x11, 0x16, 0x0f, 0x0f, 0x40, 0x40, ++ 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x07, 0x09, 0x45, 0x55, 0x58, 0x40, 0x40, 0x40, 0x40, 0x40, 0x0b, 0x40, 0x40, 0x40, 0x0b, 0x5a, ++ 0x45, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x07, 0x02, 0x02, 0x61, ++ 0x55, 0x57, 0x02, 0x1b, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x45, 0x45, 0x59, 0x59, 0x4b, 0x53, ++ 0x4d, 0x07, 0x53, 0x63, 0x4d, 0x51, 0x61, 0x65, 0x63, 0x61, 0x5d, 0x49, 0x43, 0x5a, 0x59, 0x59, ++ 0x4b, 0x53, 0x4d, 0x07, 0x53, 0x63, 0x4d, 0x51, 0x61, 0x65, 0x63, 0x61, 0x5d, 0x49, 0x43, 0x5a, ++ 0x00, 0x4a, 0x22, 0x55, 0x61, 0x61, 0x53, 0x59, 0x59, 0x57, 0x4b, 0x49, 0x4b, 0x41, 0x53, 0x55, ++ 0x33, 0x07, 0x53, 0x41, 0x53, 0x55, 0x33, 0x07, 0x53, 0x41, 0x53, 0x55, 0x33, 0x07, 0x53, 0x4d, ++ 0x45, 0x1b, 0x1b, 0x0f, 0x12, 0x0f, 0x12, 0x07, 0x12, 0x45, 0x61, 0x12, 0x45, 0x61, 0x40, 0x40, ++ 0x4d, 0x47, 0x0a, 0x02, 0x4d, 0x0f, 0x02, 0x45, 0x07, 0x0a, 0x27, 0x47, 0x45, 0x41, 0x04, 0x0f, ++ 0x4d, 0x33, 0x1d, 0x1b, 0x4d, 0x2d, 0x04, 0x21, 0x02, 0x07, 0x12, 0x15, 0x0f, 0x0f, 0x40, 0x40, ++ 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x07, 0x08, 0x45, 0x55, 0x58, 0x40, 0x40, 0x40, 0x40, 0x40, 0x0a, 0x40, 0x40, 0x40, 0x0a, 0x59, ++ 0x45, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x07, 0x02, 0x02, 0x60, ++ 0x55, 0x56, 0x02, 0x1a, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x45, 0x45, 0x58, 0x58, 0x4b, 0x53, ++ 0x4d, 0x07, 0x53, 0x63, 0x4d, 0x50, 0x60, 0x65, 0x63, 0x60, 0x5b, 0x48, 0x43, 0x59, 0x58, 0x58, ++ 0x4b, 0x53, 0x4d, 0x07, 0x53, 0x63, 0x4d, 0x50, 0x60, 0x65, 0x63, 0x60, 0x5b, 0x48, 0x43, 0x59, ++ 0x01, 0x4a, 0x22, 0x55, 0x60, 0x60, 0x53, 0x58, 0x58, 0x56, 0x4b, 0x48, 0x4b, 0x40, 0x53, 0x55, ++ 0x32, 0x07, 0x53, 0x40, 0x53, 0x55, 0x32, 0x07, 0x53, 0x40, 0x53, 0x55, 0x32, 0x07, 0x53, 0x4d, ++ 0x45, 0x1a, 0x1a, 0x0f, 0x12, 0x0f, 0x12, 0x07, 0x12, 0x45, 0x60, 0x12, 0x45, 0x60, 0x40, 0x40, ++ 0x4d, 0x46, 0x0a, 0x02, 0x4d, 0x0f, 0x02, 0x45, 0x07, 0x0c, 0x27, 0x46, 0x45, 0x40, 0x04, 0x0f, ++ 0x4d, 0x32, 0x1d, 0x1a, 0x4d, 0x2b, 0x04, 0x20, 0x02, 0x07, 0x12, 0x15, 0x0f, 0x0f, 0x40, 0x40, ++ 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x07, 0x07, 0x45, 0x55, 0x58, 0x40, 0x40, 0x40, 0x40, 0x40, 0x0a, 0x40, 0x40, 0x40, 0x0a, 0x57, ++ 0x45, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x07, 0x02, 0x02, 0x5f, ++ 0x55, 0x54, 0x02, 0x1a, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x45, 0x45, 0x57, 0x57, 0x4a, 0x52, ++ 0x4d, 0x07, 0x52, 0x62, 0x4d, 0x4f, 0x5f, 0x65, 0x62, 0x5f, 0x59, 0x47, 0x42, 0x57, 0x57, 0x57, ++ 0x4a, 0x52, 0x4d, 0x07, 0x52, 0x62, 0x4d, 0x4f, 0x5f, 0x65, 0x62, 0x5f, 0x59, 0x47, 0x42, 0x57, ++ 0x03, 0x4a, 0x22, 0x55, 0x5f, 0x5f, 0x52, 0x57, 0x57, 0x54, 0x4a, 0x47, 0x4a, 0x00, 0x52, 0x55, ++ 0x32, 0x07, 0x52, 0x00, 0x52, 0x55, 0x32, 0x07, 0x52, 0x00, 0x52, 0x55, 0x32, 0x07, 0x52, 0x4d, ++ 0x45, 0x1a, 0x1a, 0x0f, 0x12, 0x0f, 0x12, 0x07, 0x12, 0x45, 0x5f, 0x12, 0x45, 0x5f, 0x40, 0x40, ++ 0x4d, 0x44, 0x0a, 0x02, 0x4d, 0x0f, 0x02, 0x45, 0x07, 0x0e, 0x27, 0x44, 0x45, 0x00, 0x05, 0x0f, ++ 0x4d, 0x32, 0x1d, 0x1a, 0x4d, 0x29, 0x05, 0x1f, 0x02, 0x07, 0x12, 0x15, 0x0f, 0x0f, 0x40, 0x40, ++ 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x07, 0x06, 0x44, 0x54, 0x58, 0x40, 0x40, 0x40, 0x40, 0x40, 0x09, 0x40, 0x40, 0x40, 0x09, 0x55, ++ 0x44, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x07, 0x03, 0x03, 0x5e, ++ 0x54, 0x53, 0x03, 0x19, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x44, 0x44, 0x56, 0x56, 0x49, 0x51, ++ 0x4c, 0x07, 0x51, 0x61, 0x4c, 0x4e, 0x5e, 0x64, 0x61, 0x5e, 0x58, 0x46, 0x41, 0x55, 0x56, 0x56, ++ 0x49, 0x51, 0x4c, 0x07, 0x51, 0x61, 0x4c, 0x4e, 0x5e, 0x64, 0x61, 0x5e, 0x58, 0x46, 0x41, 0x55, ++ 0x04, 0x4b, 0x23, 0x54, 0x5e, 0x5e, 0x51, 0x56, 0x56, 0x53, 0x49, 0x46, 0x49, 0x01, 0x51, 0x54, ++ 0x31, 0x07, 0x51, 0x01, 0x51, 0x54, 0x31, 0x07, 0x51, 0x01, 0x51, 0x54, 0x31, 0x07, 0x51, 0x4c, ++ 0x44, 0x19, 0x19, 0x0f, 0x13, 0x0f, 0x13, 0x07, 0x13, 0x44, 0x5e, 0x13, 0x44, 0x5e, 0x40, 0x40, ++ 0x4c, 0x43, 0x0b, 0x03, 0x4c, 0x0f, 0x03, 0x44, 0x07, 0x0f, 0x27, 0x43, 0x44, 0x01, 0x06, 0x0f, ++ 0x4c, 0x31, 0x1c, 0x19, 0x4c, 0x28, 0x06, 0x1e, 0x03, 0x07, 0x13, 0x14, 0x0f, 0x0f, 0x40, 0x40, ++ 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x07, 0x05, 0x44, 0x54, 0x58, 0x40, 0x40, 0x40, 0x40, 0x40, 0x09, 0x40, 0x40, 0x40, 0x09, 0x53, ++ 0x44, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x07, 0x03, 0x03, 0x5d, ++ 0x54, 0x52, 0x03, 0x19, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x44, 0x44, 0x55, 0x55, 0x49, 0x51, ++ 0x4c, 0x07, 0x51, 0x61, 0x4c, 0x4d, 0x5d, 0x64, 0x61, 0x5d, 0x56, 0x45, 0x41, 0x53, 0x55, 0x55, ++ 0x49, 0x51, 0x4c, 0x07, 0x51, 0x61, 0x4c, 0x4d, 0x5d, 0x64, 0x61, 0x5d, 0x56, 0x45, 0x41, 0x53, ++ 0x05, 0x4b, 0x23, 0x54, 0x5d, 0x5d, 0x51, 0x55, 0x55, 0x52, 0x49, 0x45, 0x49, 0x02, 0x51, 0x54, ++ 0x31, 0x07, 0x51, 0x02, 0x51, 0x54, 0x31, 0x07, 0x51, 0x02, 0x51, 0x54, 0x31, 0x07, 0x51, 0x4c, ++ 0x44, 0x19, 0x19, 0x0f, 0x13, 0x0f, 0x13, 0x07, 0x13, 0x44, 0x5d, 0x13, 0x44, 0x5d, 0x40, 0x40, ++ 0x4c, 0x42, 0x0b, 0x03, 0x4c, 0x0f, 0x03, 0x44, 0x07, 0x11, 0x27, 0x42, 0x44, 0x02, 0x06, 0x0f, ++ 0x4c, 0x31, 0x1c, 0x19, 0x4c, 0x26, 0x06, 0x1d, 0x03, 0x07, 0x13, 0x14, 0x0f, 0x0f, 0x40, 0x40, ++ 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x07, 0x04, 0x44, 0x54, 0x58, 0x40, 0x40, 0x40, 0x40, 0x40, 0x08, 0x40, 0x40, 0x40, 0x08, 0x51, ++ 0x44, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x07, 0x03, 0x03, 0x5c, ++ 0x54, 0x51, 0x03, 0x18, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x44, 0x44, 0x54, 0x54, 0x48, 0x50, ++ 0x4c, 0x07, 0x50, 0x60, 0x4c, 0x4c, 0x5c, 0x64, 0x60, 0x5c, 0x55, 0x44, 0x40, 0x51, 0x54, 0x54, ++ 0x48, 0x50, 0x4c, 0x07, 0x50, 0x60, 0x4c, 0x4c, 0x5c, 0x64, 0x60, 0x5c, 0x55, 0x44, 0x40, 0x51, ++ 0x06, 0x4b, 0x23, 0x54, 0x5c, 0x5c, 0x50, 0x54, 0x54, 0x51, 0x48, 0x44, 0x48, 0x03, 0x50, 0x54, ++ 0x30, 0x07, 0x50, 0x03, 0x50, 0x54, 0x30, 0x07, 0x50, 0x03, 0x50, 0x54, 0x30, 0x07, 0x50, 0x4c, ++ 0x44, 0x18, 0x18, 0x0f, 0x13, 0x0f, 0x13, 0x07, 0x13, 0x44, 0x5c, 0x13, 0x44, 0x5c, 0x40, 0x40, ++ 0x4c, 0x41, 0x0b, 0x03, 0x4c, 0x0f, 0x03, 0x44, 0x07, 0x12, 0x27, 0x41, 0x44, 0x03, 0x07, 0x0f, ++ 0x4c, 0x30, 0x1c, 0x18, 0x4c, 0x25, 0x07, 0x1c, 0x03, 0x07, 0x13, 0x14, 0x0f, 0x0f, 0x40, 0x40, ++ 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x07, 0x03, 0x43, 0x53, 0x58, 0x40, 0x40, 0x40, 0x40, 0x40, 0x07, 0x40, 0x40, 0x40, 0x07, 0x4f, ++ 0x43, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x07, 0x04, 0x04, 0x5b, ++ 0x53, 0x4f, 0x04, 0x17, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x43, 0x43, 0x53, 0x53, 0x47, 0x4f, ++ 0x4b, 0x07, 0x4f, 0x5f, 0x4b, 0x4b, 0x5b, 0x63, 0x5f, 0x5b, 0x53, 0x43, 0x00, 0x4f, 0x53, 0x53, ++ 0x47, 0x4f, 0x4b, 0x07, 0x4f, 0x5f, 0x4b, 0x4b, 0x5b, 0x63, 0x5f, 0x5b, 0x53, 0x43, 0x00, 0x4f, ++ 0x08, 0x4c, 0x24, 0x53, 0x5b, 0x5b, 0x4f, 0x53, 0x53, 0x4f, 0x47, 0x43, 0x47, 0x04, 0x4f, 0x53, ++ 0x2f, 0x07, 0x4f, 0x04, 0x4f, 0x53, 0x2f, 0x07, 0x4f, 0x04, 0x4f, 0x53, 0x2f, 0x07, 0x4f, 0x4b, ++ 0x43, 0x17, 0x17, 0x0f, 0x14, 0x0f, 0x14, 0x07, 0x14, 0x43, 0x5b, 0x14, 0x43, 0x5b, 0x40, 0x40, ++ 0x4b, 0x00, 0x0c, 0x04, 0x4b, 0x0f, 0x04, 0x43, 0x07, 0x14, 0x27, 0x00, 0x43, 0x04, 0x08, 0x0f, ++ 0x4b, 0x2f, 0x1b, 0x17, 0x4b, 0x23, 0x08, 0x1b, 0x04, 0x07, 0x14, 0x13, 0x0f, 0x0f, 0x40, 0x40, ++ 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x07, 0x02, 0x43, 0x53, 0x58, 0x40, 0x40, 0x40, 0x40, 0x40, 0x07, 0x40, 0x40, 0x40, 0x07, 0x4d, ++ 0x43, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x07, 0x04, 0x04, 0x5a, ++ 0x53, 0x4e, 0x04, 0x17, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x43, 0x43, 0x52, 0x52, 0x47, 0x4f, ++ 0x4b, 0x07, 0x4f, 0x5f, 0x4b, 0x4a, 0x5a, 0x63, 0x5f, 0x5a, 0x52, 0x42, 0x00, 0x4d, 0x52, 0x52, ++ 0x47, 0x4f, 0x4b, 0x07, 0x4f, 0x5f, 0x4b, 0x4a, 0x5a, 0x63, 0x5f, 0x5a, 0x52, 0x42, 0x00, 0x4d, ++ 0x09, 0x4c, 0x24, 0x53, 0x5a, 0x5a, 0x4f, 0x52, 0x52, 0x4e, 0x47, 0x42, 0x47, 0x05, 0x4f, 0x53, ++ 0x2f, 0x07, 0x4f, 0x05, 0x4f, 0x53, 0x2f, 0x07, 0x4f, 0x05, 0x4f, 0x53, 0x2f, 0x07, 0x4f, 0x4b, ++ 0x43, 0x17, 0x17, 0x0f, 0x14, 0x0f, 0x14, 0x07, 0x14, 0x43, 0x5a, 0x14, 0x43, 0x5a, 0x40, 0x40, ++ 0x4b, 0x01, 0x0c, 0x04, 0x4b, 0x0f, 0x04, 0x43, 0x07, 0x15, 0x27, 0x01, 0x43, 0x05, 0x08, 0x0f, ++ 0x4b, 0x2f, 0x1b, 0x17, 0x4b, 0x22, 0x08, 0x1a, 0x04, 0x07, 0x14, 0x13, 0x0f, 0x0f, 0x40, 0x40, ++ 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x07, 0x01, 0x43, 0x53, 0x58, 0x40, 0x40, 0x40, 0x40, 0x40, 0x06, 0x40, 0x40, 0x40, 0x06, 0x4b, ++ 0x43, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x07, 0x04, 0x04, 0x59, ++ 0x53, 0x4d, 0x04, 0x16, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x43, 0x43, 0x51, 0x51, 0x46, 0x4e, ++ 0x4b, 0x07, 0x4e, 0x5e, 0x4b, 0x49, 0x59, 0x63, 0x5e, 0x59, 0x50, 0x41, 0x01, 0x4b, 0x51, 0x51, ++ 0x46, 0x4e, 0x4b, 0x07, 0x4e, 0x5e, 0x4b, 0x49, 0x59, 0x63, 0x5e, 0x59, 0x50, 0x41, 0x01, 0x4b, ++ 0x0a, 0x4c, 0x24, 0x53, 0x59, 0x59, 0x4e, 0x51, 0x51, 0x4d, 0x46, 0x41, 0x46, 0x06, 0x4e, 0x53, ++ 0x2e, 0x07, 0x4e, 0x06, 0x4e, 0x53, 0x2e, 0x07, 0x4e, 0x06, 0x4e, 0x53, 0x2e, 0x07, 0x4e, 0x4b, ++ 0x43, 0x16, 0x16, 0x0f, 0x14, 0x0f, 0x14, 0x07, 0x14, 0x43, 0x59, 0x14, 0x43, 0x59, 0x40, 0x40, ++ 0x4b, 0x02, 0x0c, 0x04, 0x4b, 0x0f, 0x04, 0x43, 0x07, 0x17, 0x27, 0x02, 0x43, 0x06, 0x09, 0x0f, ++ 0x4b, 0x2e, 0x1b, 0x16, 0x4b, 0x20, 0x09, 0x19, 0x04, 0x07, 0x14, 0x13, 0x0f, 0x0f, 0x40, 0x40, ++ 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x07, 0x00, 0x43, 0x53, 0x58, 0x40, 0x40, 0x40, 0x40, 0x40, 0x05, 0x40, 0x40, 0x40, 0x05, 0x4a, ++ 0x43, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x07, 0x04, 0x04, 0x59, ++ 0x53, 0x4c, 0x04, 0x15, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x43, 0x43, 0x51, 0x51, 0x46, 0x4e, ++ 0x4b, 0x07, 0x4e, 0x5e, 0x4b, 0x49, 0x59, 0x63, 0x5e, 0x59, 0x4f, 0x41, 0x01, 0x4a, 0x51, 0x51, ++ 0x46, 0x4e, 0x4b, 0x07, 0x4e, 0x5e, 0x4b, 0x49, 0x59, 0x63, 0x5e, 0x59, 0x4f, 0x41, 0x01, 0x4a, ++ 0x0b, 0x4d, 0x24, 0x53, 0x59, 0x59, 0x4e, 0x51, 0x51, 0x4c, 0x46, 0x41, 0x46, 0x06, 0x4e, 0x53, ++ 0x2d, 0x07, 0x4e, 0x06, 0x4e, 0x53, 0x2d, 0x07, 0x4e, 0x06, 0x4e, 0x53, 0x2d, 0x07, 0x4e, 0x4b, ++ 0x43, 0x15, 0x15, 0x0f, 0x14, 0x0f, 0x14, 0x07, 0x14, 0x43, 0x59, 0x14, 0x43, 0x59, 0x40, 0x40, ++ 0x4b, 0x03, 0x0c, 0x04, 0x4b, 0x0f, 0x04, 0x43, 0x07, 0x18, 0x27, 0x03, 0x43, 0x06, 0x09, 0x0f, ++ 0x4b, 0x2d, 0x1a, 0x15, 0x4b, 0x1e, 0x09, 0x18, 0x04, 0x07, 0x14, 0x12, 0x0f, 0x0f, 0x40, 0x40, ++ 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x07, 0x00, 0x42, 0x52, 0x58, 0x40, 0x40, 0x40, 0x40, 0x40, 0x05, 0x40, 0x40, 0x40, 0x05, 0x48, ++ 0x42, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x07, 0x05, 0x05, 0x58, ++ 0x52, 0x4a, 0x05, 0x15, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x42, 0x42, 0x50, 0x50, 0x45, 0x4d, ++ 0x4a, 0x07, 0x4d, 0x5d, 0x4a, 0x48, 0x58, 0x62, 0x5d, 0x58, 0x4d, 0x40, 0x02, 0x48, 0x50, 0x50, ++ 0x45, 0x4d, 0x4a, 0x07, 0x4d, 0x5d, 0x4a, 0x48, 0x58, 0x62, 0x5d, 0x58, 0x4d, 0x40, 0x02, 0x48, ++ 0x0d, 0x4d, 0x25, 0x52, 0x58, 0x58, 0x4d, 0x50, 0x50, 0x4a, 0x45, 0x40, 0x45, 0x07, 0x4d, 0x52, ++ 0x2d, 0x07, 0x4d, 0x07, 0x4d, 0x52, 0x2d, 0x07, 0x4d, 0x07, 0x4d, 0x52, 0x2d, 0x07, 0x4d, 0x4a, ++ 0x42, 0x15, 0x15, 0x0f, 0x15, 0x0f, 0x15, 0x07, 0x15, 0x42, 0x58, 0x15, 0x42, 0x58, 0x40, 0x40, ++ 0x4a, 0x05, 0x0d, 0x05, 0x4a, 0x0f, 0x05, 0x42, 0x07, 0x1a, 0x27, 0x05, 0x42, 0x07, 0x0a, 0x0f, ++ 0x4a, 0x2d, 0x1a, 0x15, 0x4a, 0x1d, 0x0a, 0x18, 0x05, 0x07, 0x15, 0x12, 0x0f, 0x0f, 0x40, 0x40, ++ 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x07, 0x40, 0x42, 0x52, 0x58, 0x40, 0x40, 0x40, 0x40, 0x40, 0x04, 0x40, 0x40, 0x40, 0x04, 0x46, ++ 0x42, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x07, 0x05, 0x05, 0x57, ++ 0x52, 0x49, 0x05, 0x14, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x42, 0x42, 0x4f, 0x4f, 0x44, 0x4c, ++ 0x4a, 0x07, 0x4c, 0x5c, 0x4a, 0x47, 0x57, 0x62, 0x5c, 0x57, 0x4b, 0x00, 0x03, 0x46, 0x4f, 0x4f, ++ 0x44, 0x4c, 0x4a, 0x07, 0x4c, 0x5c, 0x4a, 0x47, 0x57, 0x62, 0x5c, 0x57, 0x4b, 0x00, 0x03, 0x46, ++ 0x0e, 0x4d, 0x25, 0x52, 0x57, 0x57, 0x4c, 0x4f, 0x4f, 0x49, 0x44, 0x00, 0x44, 0x08, 0x4c, 0x52, ++ 0x2c, 0x07, 0x4c, 0x08, 0x4c, 0x52, 0x2c, 0x07, 0x4c, 0x08, 0x4c, 0x52, 0x2c, 0x07, 0x4c, 0x4a, ++ 0x42, 0x14, 0x14, 0x0f, 0x15, 0x0f, 0x15, 0x07, 0x15, 0x42, 0x57, 0x15, 0x42, 0x57, 0x40, 0x40, ++ 0x4a, 0x06, 0x0d, 0x05, 0x4a, 0x0f, 0x05, 0x42, 0x07, 0x1c, 0x27, 0x06, 0x42, 0x08, 0x0b, 0x0f, ++ 0x4a, 0x2c, 0x1a, 0x14, 0x4a, 0x1b, 0x0b, 0x17, 0x05, 0x07, 0x15, 0x12, 0x0f, 0x0f, 0x40, 0x40, ++ 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x07, 0x41, 0x42, 0x52, 0x58, 0x40, 0x40, 0x40, 0x40, 0x40, 0x04, 0x40, 0x40, 0x40, 0x04, 0x44, ++ 0x42, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x07, 0x05, 0x05, 0x56, ++ 0x52, 0x48, 0x05, 0x14, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x42, 0x42, 0x4e, 0x4e, 0x44, 0x4c, ++ 0x4a, 0x07, 0x4c, 0x5c, 0x4a, 0x46, 0x56, 0x62, 0x5c, 0x56, 0x4a, 0x01, 0x03, 0x44, 0x4e, 0x4e, ++ 0x44, 0x4c, 0x4a, 0x07, 0x4c, 0x5c, 0x4a, 0x46, 0x56, 0x62, 0x5c, 0x56, 0x4a, 0x01, 0x03, 0x44, ++ 0x0f, 0x4d, 0x25, 0x52, 0x56, 0x56, 0x4c, 0x4e, 0x4e, 0x48, 0x44, 0x01, 0x44, 0x09, 0x4c, 0x52, ++ 0x2c, 0x07, 0x4c, 0x09, 0x4c, 0x52, 0x2c, 0x07, 0x4c, 0x09, 0x4c, 0x52, 0x2c, 0x07, 0x4c, 0x4a, ++ 0x42, 0x14, 0x14, 0x0f, 0x15, 0x0f, 0x15, 0x07, 0x15, 0x42, 0x56, 0x15, 0x42, 0x56, 0x40, 0x40, ++ 0x4a, 0x07, 0x0d, 0x05, 0x4a, 0x0f, 0x05, 0x42, 0x07, 0x1d, 0x27, 0x07, 0x42, 0x09, 0x0b, 0x0f, ++ 0x4a, 0x2c, 0x1a, 0x14, 0x4a, 0x1a, 0x0b, 0x16, 0x05, 0x07, 0x15, 0x12, 0x0f, 0x0f, 0x40, 0x40, ++ 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x07, 0x42, 0x41, 0x51, 0x58, 0x40, 0x40, 0x40, 0x40, 0x40, 0x03, 0x40, 0x40, 0x40, 0x03, 0x42, ++ 0x41, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x07, 0x06, 0x06, 0x55, ++ 0x51, 0x47, 0x06, 0x13, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x41, 0x41, 0x4d, 0x4d, 0x43, 0x4b, ++ 0x49, 0x07, 0x4b, 0x5b, 0x49, 0x45, 0x55, 0x61, 0x5b, 0x55, 0x48, 0x02, 0x04, 0x42, 0x4d, 0x4d, ++ 0x43, 0x4b, 0x49, 0x07, 0x4b, 0x5b, 0x49, 0x45, 0x55, 0x61, 0x5b, 0x55, 0x48, 0x02, 0x04, 0x42, ++ 0x10, 0x4e, 0x26, 0x51, 0x55, 0x55, 0x4b, 0x4d, 0x4d, 0x47, 0x43, 0x02, 0x43, 0x0a, 0x4b, 0x51, ++ 0x2b, 0x07, 0x4b, 0x0a, 0x4b, 0x51, 0x2b, 0x07, 0x4b, 0x0a, 0x4b, 0x51, 0x2b, 0x07, 0x4b, 0x49, ++ 0x41, 0x13, 0x13, 0x0f, 0x16, 0x0f, 0x16, 0x07, 0x16, 0x41, 0x55, 0x16, 0x41, 0x55, 0x40, 0x40, ++ 0x49, 0x08, 0x0e, 0x06, 0x49, 0x0f, 0x06, 0x41, 0x07, 0x1f, 0x27, 0x08, 0x41, 0x0a, 0x0c, 0x0f, ++ 0x49, 0x2b, 0x19, 0x13, 0x49, 0x18, 0x0c, 0x15, 0x06, 0x07, 0x16, 0x11, 0x0f, 0x0f, 0x40, 0x40, ++ 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x07, 0x43, 0x41, 0x51, 0x58, 0x40, 0x40, 0x40, 0x40, 0x40, 0x02, 0x40, 0x40, 0x40, 0x02, 0x40, ++ 0x41, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x07, 0x06, 0x06, 0x54, ++ 0x51, 0x45, 0x06, 0x12, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x41, 0x41, 0x4c, 0x4c, 0x42, 0x4a, ++ 0x49, 0x07, 0x4a, 0x5a, 0x49, 0x44, 0x54, 0x61, 0x5a, 0x54, 0x47, 0x03, 0x05, 0x40, 0x4c, 0x4c, ++ 0x42, 0x4a, 0x49, 0x07, 0x4a, 0x5a, 0x49, 0x44, 0x54, 0x61, 0x5a, 0x54, 0x47, 0x03, 0x05, 0x40, ++ 0x12, 0x4e, 0x26, 0x51, 0x54, 0x54, 0x4a, 0x4c, 0x4c, 0x45, 0x42, 0x03, 0x42, 0x0b, 0x4a, 0x51, ++ 0x2a, 0x07, 0x4a, 0x0b, 0x4a, 0x51, 0x2a, 0x07, 0x4a, 0x0b, 0x4a, 0x51, 0x2a, 0x07, 0x4a, 0x49, ++ 0x41, 0x12, 0x12, 0x0f, 0x16, 0x0f, 0x16, 0x07, 0x16, 0x41, 0x54, 0x16, 0x41, 0x54, 0x40, 0x40, ++ 0x49, 0x0a, 0x0e, 0x06, 0x49, 0x0f, 0x06, 0x41, 0x07, 0x20, 0x27, 0x0a, 0x41, 0x0b, 0x0d, 0x0f, ++ 0x49, 0x2a, 0x19, 0x12, 0x49, 0x17, 0x0d, 0x14, 0x06, 0x07, 0x16, 0x11, 0x0f, 0x0f, 0x40, 0x40, ++ 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x07, 0x44, 0x41, 0x51, 0x58, 0x40, 0x40, 0x40, 0x40, 0x40, 0x02, 0x40, 0x40, 0x40, 0x02, 0x01, ++ 0x41, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x07, 0x06, 0x06, 0x53, ++ 0x51, 0x44, 0x06, 0x12, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x41, 0x41, 0x4b, 0x4b, 0x42, 0x4a, ++ 0x49, 0x07, 0x4a, 0x5a, 0x49, 0x43, 0x53, 0x61, 0x5a, 0x53, 0x45, 0x04, 0x05, 0x01, 0x4b, 0x4b, ++ 0x42, 0x4a, 0x49, 0x07, 0x4a, 0x5a, 0x49, 0x43, 0x53, 0x61, 0x5a, 0x53, 0x45, 0x04, 0x05, 0x01, ++ 0x13, 0x4e, 0x26, 0x51, 0x53, 0x53, 0x4a, 0x4b, 0x4b, 0x44, 0x42, 0x04, 0x42, 0x0c, 0x4a, 0x51, ++ 0x2a, 0x07, 0x4a, 0x0c, 0x4a, 0x51, 0x2a, 0x07, 0x4a, 0x0c, 0x4a, 0x51, 0x2a, 0x07, 0x4a, 0x49, ++ 0x41, 0x12, 0x12, 0x0f, 0x16, 0x0f, 0x16, 0x07, 0x16, 0x41, 0x53, 0x16, 0x41, 0x53, 0x40, 0x40, ++ 0x49, 0x0b, 0x0e, 0x06, 0x49, 0x0f, 0x06, 0x41, 0x07, 0x22, 0x27, 0x0b, 0x41, 0x0c, 0x0d, 0x0f, ++ 0x49, 0x2a, 0x19, 0x12, 0x49, 0x15, 0x0d, 0x13, 0x06, 0x07, 0x16, 0x11, 0x0f, 0x0f, 0x40, 0x40, ++ 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x07, 0x45, 0x40, 0x50, 0x58, 0x40, 0x40, 0x40, 0x40, 0x40, 0x01, 0x40, 0x40, 0x40, 0x01, 0x03, ++ 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x07, 0x07, 0x07, 0x52, ++ 0x50, 0x43, 0x07, 0x11, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x4a, 0x4a, 0x41, 0x49, ++ 0x48, 0x07, 0x49, 0x59, 0x48, 0x42, 0x52, 0x60, 0x59, 0x52, 0x44, 0x05, 0x06, 0x03, 0x4a, 0x4a, ++ 0x41, 0x49, 0x48, 0x07, 0x49, 0x59, 0x48, 0x42, 0x52, 0x60, 0x59, 0x52, 0x44, 0x05, 0x06, 0x03, ++ 0x14, 0x4f, 0x27, 0x50, 0x52, 0x52, 0x49, 0x4a, 0x4a, 0x43, 0x41, 0x05, 0x41, 0x0d, 0x49, 0x50, ++ 0x29, 0x07, 0x49, 0x0d, 0x49, 0x50, 0x29, 0x07, 0x49, 0x0d, 0x49, 0x50, 0x29, 0x07, 0x49, 0x48, ++ 0x40, 0x11, 0x11, 0x0f, 0x17, 0x0f, 0x17, 0x07, 0x17, 0x40, 0x52, 0x17, 0x40, 0x52, 0x40, 0x40, ++ 0x48, 0x0c, 0x0f, 0x07, 0x48, 0x0f, 0x07, 0x40, 0x07, 0x23, 0x27, 0x0c, 0x40, 0x0d, 0x0e, 0x0f, ++ 0x48, 0x29, 0x18, 0x11, 0x48, 0x14, 0x0e, 0x12, 0x07, 0x07, 0x17, 0x10, 0x0f, 0x0f, 0x40, 0x40, ++ 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x07, 0x46, 0x40, 0x50, 0x58, 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x40, 0x40, 0x40, 0x00, 0x04, ++ 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x07, 0x07, 0x07, 0x51, ++ 0x50, 0x42, 0x07, 0x10, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x49, 0x49, 0x41, 0x49, ++ 0x48, 0x07, 0x49, 0x59, 0x48, 0x41, 0x51, 0x60, 0x59, 0x51, 0x42, 0x06, 0x06, 0x04, 0x49, 0x49, ++ 0x41, 0x49, 0x48, 0x07, 0x49, 0x59, 0x48, 0x41, 0x51, 0x60, 0x59, 0x51, 0x42, 0x06, 0x06, 0x04, ++ 0x15, 0x4f, 0x27, 0x50, 0x51, 0x51, 0x49, 0x49, 0x49, 0x42, 0x41, 0x06, 0x41, 0x0e, 0x49, 0x50, ++ 0x28, 0x07, 0x49, 0x0e, 0x49, 0x50, 0x28, 0x07, 0x49, 0x0e, 0x49, 0x50, 0x28, 0x07, 0x49, 0x48, ++ 0x40, 0x10, 0x10, 0x0f, 0x17, 0x0f, 0x17, 0x07, 0x17, 0x40, 0x51, 0x17, 0x40, 0x51, 0x40, 0x40, ++ 0x48, 0x0d, 0x0f, 0x07, 0x48, 0x0f, 0x07, 0x40, 0x07, 0x25, 0x27, 0x0d, 0x40, 0x0e, 0x0e, 0x0f, ++ 0x48, 0x28, 0x18, 0x10, 0x48, 0x12, 0x0e, 0x11, 0x07, 0x07, 0x17, 0x10, 0x0f, 0x0f, 0x40, 0x40, ++ 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x07, 0x47, 0x40, 0x50, 0x58, 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x40, 0x40, 0x40, 0x00, 0x06, ++ 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x07, 0x07, 0x07, 0x50, ++ 0x50, 0x40, 0x07, 0x10, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x48, 0x48, 0x40, 0x48, ++ 0x48, 0x07, 0x48, 0x58, 0x48, 0x40, 0x50, 0x60, 0x58, 0x50, 0x40, 0x07, 0x07, 0x06, 0x48, 0x48, ++ 0x40, 0x48, 0x48, 0x07, 0x48, 0x58, 0x48, 0x40, 0x50, 0x60, 0x58, 0x50, 0x40, 0x07, 0x07, 0x06, ++ 0x17, 0x4f, 0x27, 0x50, 0x50, 0x50, 0x48, 0x48, 0x48, 0x40, 0x40, 0x07, 0x40, 0x0f, 0x48, 0x50, ++ 0x28, 0x07, 0x48, 0x0f, 0x48, 0x50, 0x28, 0x07, 0x48, 0x0f, 0x48, 0x50, 0x28, 0x07, 0x48, 0x48, ++ 0x40, 0x10, 0x10, 0x0f, 0x17, 0x0f, 0x17, 0x07, 0x17, 0x40, 0x50, 0x17, 0x40, 0x50, 0x40, 0x40, ++ 0x48, 0x0f, 0x0f, 0x07, 0x48, 0x0f, 0x07, 0x40, 0x07, 0x27, 0x27, 0x0f, 0x40, 0x0f, 0x0f, 0x0f, ++ 0x48, 0x28, 0x18, 0x10, 0x48, 0x10, 0x0f, 0x10, 0x07, 0x07, 0x17, 0x10, 0x0f, 0x0f, 0x40, 0x40, ++ 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x07, 0x48, 0x00, 0x4f, 0x58, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x08, ++ 0x00, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x07, 0x08, 0x08, 0x4f, ++ 0x4f, 0x00, 0x08, 0x0f, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x47, 0x47, 0x00, 0x47, ++ 0x47, 0x07, 0x47, 0x57, 0x47, 0x00, 0x4f, 0x5f, 0x57, 0x4f, 0x00, 0x08, 0x08, 0x08, 0x47, 0x47, ++ 0x00, 0x47, 0x47, 0x07, 0x47, 0x57, 0x47, 0x00, 0x4f, 0x5f, 0x57, 0x4f, 0x00, 0x08, 0x08, 0x08, ++ 0x18, 0x50, 0x28, 0x4f, 0x4f, 0x4f, 0x47, 0x47, 0x47, 0x00, 0x00, 0x08, 0x00, 0x10, 0x47, 0x4f, ++ 0x27, 0x07, 0x47, 0x10, 0x47, 0x4f, 0x27, 0x07, 0x47, 0x10, 0x47, 0x4f, 0x27, 0x07, 0x47, 0x47, ++ 0x00, 0x0f, 0x0f, 0x0f, 0x18, 0x0f, 0x18, 0x07, 0x18, 0x00, 0x4f, 0x18, 0x00, 0x4f, 0x40, 0x40, ++ 0x47, 0x10, 0x10, 0x08, 0x47, 0x0f, 0x08, 0x00, 0x07, 0x28, 0x27, 0x10, 0x00, 0x10, 0x10, 0x0f, ++ 0x47, 0x27, 0x17, 0x0f, 0x47, 0x0f, 0x10, 0x0f, 0x08, 0x07, 0x18, 0x0f, 0x0f, 0x0f, 0x40, 0x40, ++ 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x07, 0x49, 0x00, 0x4f, 0x58, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x0a, ++ 0x00, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x07, 0x08, 0x08, 0x4e, ++ 0x4f, 0x01, 0x08, 0x0f, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x46, 0x46, 0x00, 0x47, ++ 0x47, 0x07, 0x47, 0x57, 0x47, 0x01, 0x4e, 0x5f, 0x57, 0x4e, 0x02, 0x09, 0x08, 0x0a, 0x46, 0x46, ++ 0x00, 0x47, 0x47, 0x07, 0x47, 0x57, 0x47, 0x01, 0x4e, 0x5f, 0x57, 0x4e, 0x02, 0x09, 0x08, 0x0a, ++ 0x19, 0x50, 0x28, 0x4f, 0x4e, 0x4e, 0x47, 0x46, 0x46, 0x01, 0x00, 0x09, 0x00, 0x11, 0x47, 0x4f, ++ 0x27, 0x07, 0x47, 0x11, 0x47, 0x4f, 0x27, 0x07, 0x47, 0x11, 0x47, 0x4f, 0x27, 0x07, 0x47, 0x47, ++ 0x00, 0x0f, 0x0f, 0x0f, 0x18, 0x0f, 0x18, 0x07, 0x18, 0x00, 0x4e, 0x18, 0x00, 0x4e, 0x40, 0x40, ++ 0x47, 0x11, 0x10, 0x08, 0x47, 0x0f, 0x08, 0x00, 0x07, 0x2a, 0x27, 0x11, 0x00, 0x11, 0x10, 0x0f, ++ 0x47, 0x27, 0x17, 0x0f, 0x47, 0x0d, 0x10, 0x0e, 0x08, 0x07, 0x18, 0x0f, 0x0f, 0x0f, 0x40, 0x40, ++ 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x07, 0x4a, 0x00, 0x4f, 0x58, 0x40, 0x40, 0x40, 0x40, 0x40, 0x41, 0x40, 0x40, 0x40, 0x41, 0x0c, ++ 0x00, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x07, 0x08, 0x08, 0x4d, ++ 0x4f, 0x02, 0x08, 0x0e, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x45, 0x45, 0x01, 0x46, ++ 0x47, 0x07, 0x46, 0x56, 0x47, 0x02, 0x4d, 0x5f, 0x56, 0x4d, 0x03, 0x0a, 0x09, 0x0c, 0x45, 0x45, ++ 0x01, 0x46, 0x47, 0x07, 0x46, 0x56, 0x47, 0x02, 0x4d, 0x5f, 0x56, 0x4d, 0x03, 0x0a, 0x09, 0x0c, ++ 0x1a, 0x50, 0x28, 0x4f, 0x4d, 0x4d, 0x46, 0x45, 0x45, 0x02, 0x01, 0x0a, 0x01, 0x12, 0x46, 0x4f, ++ 0x26, 0x07, 0x46, 0x12, 0x46, 0x4f, 0x26, 0x07, 0x46, 0x12, 0x46, 0x4f, 0x26, 0x07, 0x46, 0x47, ++ 0x00, 0x0e, 0x0e, 0x0f, 0x18, 0x0f, 0x18, 0x07, 0x18, 0x00, 0x4d, 0x18, 0x00, 0x4d, 0x40, 0x40, ++ 0x47, 0x12, 0x10, 0x08, 0x47, 0x0f, 0x08, 0x00, 0x07, 0x2b, 0x27, 0x12, 0x00, 0x12, 0x11, 0x0f, ++ 0x47, 0x26, 0x17, 0x0e, 0x47, 0x0c, 0x11, 0x0d, 0x08, 0x07, 0x18, 0x0f, 0x0f, 0x0f, 0x40, 0x40, ++ 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x07, 0x4b, 0x01, 0x4e, 0x58, 0x40, 0x40, 0x40, 0x40, 0x40, 0x42, 0x40, 0x40, 0x40, 0x42, 0x0e, ++ 0x01, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x07, 0x09, 0x09, 0x4c, ++ 0x4e, 0x04, 0x09, 0x0d, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x01, 0x01, 0x44, 0x44, 0x02, 0x45, ++ 0x46, 0x07, 0x45, 0x55, 0x46, 0x03, 0x4c, 0x5e, 0x55, 0x4c, 0x05, 0x0b, 0x0a, 0x0e, 0x44, 0x44, ++ 0x02, 0x45, 0x46, 0x07, 0x45, 0x55, 0x46, 0x03, 0x4c, 0x5e, 0x55, 0x4c, 0x05, 0x0b, 0x0a, 0x0e, ++ 0x1c, 0x51, 0x29, 0x4e, 0x4c, 0x4c, 0x45, 0x44, 0x44, 0x04, 0x02, 0x0b, 0x02, 0x13, 0x45, 0x4e, ++ 0x25, 0x07, 0x45, 0x13, 0x45, 0x4e, 0x25, 0x07, 0x45, 0x13, 0x45, 0x4e, 0x25, 0x07, 0x45, 0x46, ++ 0x01, 0x0d, 0x0d, 0x0f, 0x19, 0x0f, 0x19, 0x07, 0x19, 0x01, 0x4c, 0x19, 0x01, 0x4c, 0x40, 0x40, ++ 0x46, 0x14, 0x11, 0x09, 0x46, 0x0f, 0x09, 0x01, 0x07, 0x2d, 0x27, 0x14, 0x01, 0x13, 0x12, 0x0f, ++ 0x46, 0x25, 0x16, 0x0d, 0x46, 0x0a, 0x12, 0x0c, 0x09, 0x07, 0x19, 0x0e, 0x0f, 0x0f, 0x40, 0x40, ++ 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x07, 0x4c, 0x01, 0x4e, 0x58, 0x40, 0x40, 0x40, 0x40, 0x40, 0x42, 0x40, 0x40, 0x40, 0x42, 0x10, ++ 0x01, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x07, 0x09, 0x09, 0x4b, ++ 0x4e, 0x05, 0x09, 0x0d, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x01, 0x01, 0x43, 0x43, 0x02, 0x45, ++ 0x46, 0x07, 0x45, 0x55, 0x46, 0x04, 0x4b, 0x5e, 0x55, 0x4b, 0x06, 0x0c, 0x0a, 0x10, 0x43, 0x43, ++ 0x02, 0x45, 0x46, 0x07, 0x45, 0x55, 0x46, 0x04, 0x4b, 0x5e, 0x55, 0x4b, 0x06, 0x0c, 0x0a, 0x10, ++ 0x1d, 0x51, 0x29, 0x4e, 0x4b, 0x4b, 0x45, 0x43, 0x43, 0x05, 0x02, 0x0c, 0x02, 0x14, 0x45, 0x4e, ++ 0x25, 0x07, 0x45, 0x14, 0x45, 0x4e, 0x25, 0x07, 0x45, 0x14, 0x45, 0x4e, 0x25, 0x07, 0x45, 0x46, ++ 0x01, 0x0d, 0x0d, 0x0f, 0x19, 0x0f, 0x19, 0x07, 0x19, 0x01, 0x4b, 0x19, 0x01, 0x4b, 0x40, 0x40, ++ 0x46, 0x15, 0x11, 0x09, 0x46, 0x0f, 0x09, 0x01, 0x07, 0x2e, 0x27, 0x15, 0x01, 0x14, 0x12, 0x0f, ++ 0x46, 0x25, 0x16, 0x0d, 0x46, 0x09, 0x12, 0x0b, 0x09, 0x07, 0x19, 0x0e, 0x0f, 0x0f, 0x40, 0x40, ++ 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x07, 0x4d, 0x01, 0x4e, 0x58, 0x40, 0x40, 0x40, 0x40, 0x40, 0x43, 0x40, 0x40, 0x40, 0x43, 0x12, ++ 0x01, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x07, 0x09, 0x09, 0x4a, ++ 0x4e, 0x06, 0x09, 0x0c, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x01, 0x01, 0x42, 0x42, 0x03, 0x44, ++ 0x46, 0x07, 0x44, 0x54, 0x46, 0x05, 0x4a, 0x5e, 0x54, 0x4a, 0x08, 0x0d, 0x0b, 0x12, 0x42, 0x42, ++ 0x03, 0x44, 0x46, 0x07, 0x44, 0x54, 0x46, 0x05, 0x4a, 0x5e, 0x54, 0x4a, 0x08, 0x0d, 0x0b, 0x12, ++ 0x1e, 0x51, 0x29, 0x4e, 0x4a, 0x4a, 0x44, 0x42, 0x42, 0x06, 0x03, 0x0d, 0x03, 0x15, 0x44, 0x4e, ++ 0x24, 0x07, 0x44, 0x15, 0x44, 0x4e, 0x24, 0x07, 0x44, 0x15, 0x44, 0x4e, 0x24, 0x07, 0x44, 0x46, ++ 0x01, 0x0c, 0x0c, 0x0f, 0x19, 0x0f, 0x19, 0x07, 0x19, 0x01, 0x4a, 0x19, 0x01, 0x4a, 0x40, 0x40, ++ 0x46, 0x16, 0x11, 0x09, 0x46, 0x0f, 0x09, 0x01, 0x07, 0x30, 0x27, 0x16, 0x01, 0x15, 0x13, 0x0f, ++ 0x46, 0x24, 0x16, 0x0c, 0x46, 0x07, 0x13, 0x0a, 0x09, 0x07, 0x19, 0x0e, 0x0f, 0x0f, 0x40, 0x40, ++ 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x07, 0x4e, 0x01, 0x4e, 0x58, 0x40, 0x40, 0x40, 0x40, 0x40, 0x44, 0x40, 0x40, 0x40, 0x44, 0x13, ++ 0x01, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x07, 0x09, 0x09, 0x4a, ++ 0x4e, 0x07, 0x09, 0x0b, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x01, 0x01, 0x42, 0x42, 0x03, 0x44, ++ 0x46, 0x07, 0x44, 0x54, 0x46, 0x05, 0x4a, 0x5e, 0x54, 0x4a, 0x09, 0x0d, 0x0b, 0x13, 0x42, 0x42, ++ 0x03, 0x44, 0x46, 0x07, 0x44, 0x54, 0x46, 0x05, 0x4a, 0x5e, 0x54, 0x4a, 0x09, 0x0d, 0x0b, 0x13, ++ 0x1f, 0x52, 0x29, 0x4e, 0x4a, 0x4a, 0x44, 0x42, 0x42, 0x07, 0x03, 0x0d, 0x03, 0x15, 0x44, 0x4e, ++ 0x23, 0x07, 0x44, 0x15, 0x44, 0x4e, 0x23, 0x07, 0x44, 0x15, 0x44, 0x4e, 0x23, 0x07, 0x44, 0x46, ++ 0x01, 0x0b, 0x0b, 0x0f, 0x19, 0x0f, 0x19, 0x07, 0x19, 0x01, 0x4a, 0x19, 0x01, 0x4a, 0x40, 0x40, ++ 0x46, 0x17, 0x11, 0x09, 0x46, 0x0f, 0x09, 0x01, 0x07, 0x31, 0x27, 0x17, 0x01, 0x15, 0x13, 0x0f, ++ 0x46, 0x23, 0x15, 0x0b, 0x46, 0x05, 0x13, 0x09, 0x09, 0x07, 0x19, 0x0d, 0x0f, 0x0f, 0x40, 0x40, ++ 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x07, 0x4e, 0x02, 0x4d, 0x58, 0x40, 0x40, 0x40, 0x40, 0x40, 0x44, 0x40, 0x40, 0x40, 0x44, 0x15, ++ 0x02, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x07, 0x0a, 0x0a, 0x49, ++ 0x4d, 0x09, 0x0a, 0x0b, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x02, 0x02, 0x41, 0x41, 0x04, 0x43, ++ 0x45, 0x07, 0x43, 0x53, 0x45, 0x06, 0x49, 0x5d, 0x53, 0x49, 0x0b, 0x0e, 0x0c, 0x15, 0x41, 0x41, ++ 0x04, 0x43, 0x45, 0x07, 0x43, 0x53, 0x45, 0x06, 0x49, 0x5d, 0x53, 0x49, 0x0b, 0x0e, 0x0c, 0x15, ++ 0x21, 0x52, 0x2a, 0x4d, 0x49, 0x49, 0x43, 0x41, 0x41, 0x09, 0x04, 0x0e, 0x04, 0x16, 0x43, 0x4d, ++ 0x23, 0x07, 0x43, 0x16, 0x43, 0x4d, 0x23, 0x07, 0x43, 0x16, 0x43, 0x4d, 0x23, 0x07, 0x43, 0x45, ++ 0x02, 0x0b, 0x0b, 0x0f, 0x1a, 0x0f, 0x1a, 0x07, 0x1a, 0x02, 0x49, 0x1a, 0x02, 0x49, 0x40, 0x40, ++ 0x45, 0x19, 0x12, 0x0a, 0x45, 0x0f, 0x0a, 0x02, 0x07, 0x33, 0x27, 0x19, 0x02, 0x16, 0x14, 0x0f, ++ 0x45, 0x23, 0x15, 0x0b, 0x45, 0x04, 0x14, 0x09, 0x0a, 0x07, 0x1a, 0x0d, 0x0f, 0x0f, 0x40, 0x40, ++ 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x07, 0x4f, 0x02, 0x4d, 0x58, 0x40, 0x40, 0x40, 0x40, 0x40, 0x45, 0x40, 0x40, 0x40, 0x45, 0x17, ++ 0x02, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x07, 0x0a, 0x0a, 0x48, ++ 0x4d, 0x0a, 0x0a, 0x0a, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x02, 0x02, 0x40, 0x40, 0x05, 0x42, ++ 0x45, 0x07, 0x42, 0x52, 0x45, 0x07, 0x48, 0x5d, 0x52, 0x48, 0x0d, 0x0f, 0x0d, 0x17, 0x40, 0x40, ++ 0x05, 0x42, 0x45, 0x07, 0x42, 0x52, 0x45, 0x07, 0x48, 0x5d, 0x52, 0x48, 0x0d, 0x0f, 0x0d, 0x17, ++ 0x22, 0x52, 0x2a, 0x4d, 0x48, 0x48, 0x42, 0x40, 0x40, 0x0a, 0x05, 0x0f, 0x05, 0x17, 0x42, 0x4d, ++ 0x22, 0x07, 0x42, 0x17, 0x42, 0x4d, 0x22, 0x07, 0x42, 0x17, 0x42, 0x4d, 0x22, 0x07, 0x42, 0x45, ++ 0x02, 0x0a, 0x0a, 0x0f, 0x1a, 0x0f, 0x1a, 0x07, 0x1a, 0x02, 0x48, 0x1a, 0x02, 0x48, 0x40, 0x40, ++ 0x45, 0x1a, 0x12, 0x0a, 0x45, 0x0f, 0x0a, 0x02, 0x07, 0x35, 0x27, 0x1a, 0x02, 0x17, 0x15, 0x0f, ++ 0x45, 0x22, 0x15, 0x0a, 0x45, 0x02, 0x15, 0x08, 0x0a, 0x07, 0x1a, 0x0d, 0x0f, 0x0f, 0x40, 0x40, ++ 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x07, 0x50, 0x02, 0x4d, 0x58, 0x40, 0x40, 0x40, 0x40, 0x40, 0x45, 0x40, 0x40, 0x40, 0x45, 0x19, ++ 0x02, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x07, 0x0a, 0x0a, 0x47, ++ 0x4d, 0x0b, 0x0a, 0x0a, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x02, 0x02, 0x00, 0x00, 0x05, 0x42, ++ 0x45, 0x07, 0x42, 0x52, 0x45, 0x08, 0x47, 0x5d, 0x52, 0x47, 0x0e, 0x10, 0x0d, 0x19, 0x00, 0x00, ++ 0x05, 0x42, 0x45, 0x07, 0x42, 0x52, 0x45, 0x08, 0x47, 0x5d, 0x52, 0x47, 0x0e, 0x10, 0x0d, 0x19, ++ 0x23, 0x52, 0x2a, 0x4d, 0x47, 0x47, 0x42, 0x00, 0x00, 0x0b, 0x05, 0x10, 0x05, 0x18, 0x42, 0x4d, ++ 0x22, 0x07, 0x42, 0x18, 0x42, 0x4d, 0x22, 0x07, 0x42, 0x18, 0x42, 0x4d, 0x22, 0x07, 0x42, 0x45, ++ 0x02, 0x0a, 0x0a, 0x0f, 0x1a, 0x0f, 0x1a, 0x07, 0x1a, 0x02, 0x47, 0x1a, 0x02, 0x47, 0x40, 0x40, ++ 0x45, 0x1b, 0x12, 0x0a, 0x45, 0x0f, 0x0a, 0x02, 0x07, 0x36, 0x27, 0x1b, 0x02, 0x18, 0x15, 0x0f, ++ 0x45, 0x22, 0x15, 0x0a, 0x45, 0x01, 0x15, 0x07, 0x0a, 0x07, 0x1a, 0x0d, 0x0f, 0x0f, 0x40, 0x40, ++ 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x07, 0x51, 0x03, 0x4c, 0x58, 0x40, 0x40, 0x40, 0x40, 0x40, 0x46, 0x40, 0x40, 0x40, 0x46, 0x1b, ++ 0x03, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x07, 0x0b, 0x0b, 0x46, ++ 0x4c, 0x0c, 0x0b, 0x09, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x03, 0x03, 0x01, 0x01, 0x06, 0x41, ++ 0x44, 0x07, 0x41, 0x51, 0x44, 0x09, 0x46, 0x5c, 0x51, 0x46, 0x10, 0x11, 0x0e, 0x1b, 0x01, 0x01, ++ 0x06, 0x41, 0x44, 0x07, 0x41, 0x51, 0x44, 0x09, 0x46, 0x5c, 0x51, 0x46, 0x10, 0x11, 0x0e, 0x1b, ++ 0x24, 0x53, 0x2b, 0x4c, 0x46, 0x46, 0x41, 0x01, 0x01, 0x0c, 0x06, 0x11, 0x06, 0x19, 0x41, 0x4c, ++ 0x21, 0x07, 0x41, 0x19, 0x41, 0x4c, 0x21, 0x07, 0x41, 0x19, 0x41, 0x4c, 0x21, 0x07, 0x41, 0x44, ++ 0x03, 0x09, 0x09, 0x0f, 0x1b, 0x0f, 0x1b, 0x07, 0x1b, 0x03, 0x46, 0x1b, 0x03, 0x46, 0x40, 0x40, ++ 0x44, 0x1c, 0x13, 0x0b, 0x44, 0x0f, 0x0b, 0x03, 0x07, 0x38, 0x27, 0x1c, 0x03, 0x19, 0x16, 0x0f, ++ 0x44, 0x21, 0x14, 0x09, 0x44, 0x40, 0x16, 0x06, 0x0b, 0x07, 0x1b, 0x0c, 0x0f, 0x0f, 0x40, 0x40, ++ 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x07, 0x52, 0x03, 0x4c, 0x58, 0x40, 0x40, 0x40, 0x40, 0x40, 0x47, 0x40, 0x40, 0x40, 0x47, 0x1d, ++ 0x03, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x07, 0x0b, 0x0b, 0x45, ++ 0x4c, 0x0e, 0x0b, 0x08, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x03, 0x03, 0x02, 0x02, 0x07, 0x40, ++ 0x44, 0x07, 0x40, 0x50, 0x44, 0x0a, 0x45, 0x5c, 0x50, 0x45, 0x11, 0x12, 0x0f, 0x1d, 0x02, 0x02, ++ 0x07, 0x40, 0x44, 0x07, 0x40, 0x50, 0x44, 0x0a, 0x45, 0x5c, 0x50, 0x45, 0x11, 0x12, 0x0f, 0x1d, ++ 0x26, 0x53, 0x2b, 0x4c, 0x45, 0x45, 0x40, 0x02, 0x02, 0x0e, 0x07, 0x12, 0x07, 0x1a, 0x40, 0x4c, ++ 0x20, 0x07, 0x40, 0x1a, 0x40, 0x4c, 0x20, 0x07, 0x40, 0x1a, 0x40, 0x4c, 0x20, 0x07, 0x40, 0x44, ++ 0x03, 0x08, 0x08, 0x0f, 0x1b, 0x0f, 0x1b, 0x07, 0x1b, 0x03, 0x45, 0x1b, 0x03, 0x45, 0x40, 0x40, ++ 0x44, 0x1e, 0x13, 0x0b, 0x44, 0x0f, 0x0b, 0x03, 0x07, 0x39, 0x27, 0x1e, 0x03, 0x1a, 0x17, 0x0f, ++ 0x44, 0x20, 0x14, 0x08, 0x44, 0x41, 0x17, 0x05, 0x0b, 0x07, 0x1b, 0x0c, 0x0f, 0x0f, 0x40, 0x40, ++ 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x07, 0x53, 0x03, 0x4c, 0x58, 0x40, 0x40, 0x40, 0x40, 0x40, 0x47, 0x40, 0x40, 0x40, 0x47, 0x1f, ++ 0x03, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x07, 0x0b, 0x0b, 0x44, ++ 0x4c, 0x0f, 0x0b, 0x08, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x03, 0x03, 0x03, 0x03, 0x07, 0x40, ++ 0x44, 0x07, 0x40, 0x50, 0x44, 0x0b, 0x44, 0x5c, 0x50, 0x44, 0x13, 0x13, 0x0f, 0x1f, 0x03, 0x03, ++ 0x07, 0x40, 0x44, 0x07, 0x40, 0x50, 0x44, 0x0b, 0x44, 0x5c, 0x50, 0x44, 0x13, 0x13, 0x0f, 0x1f, ++ 0x27, 0x53, 0x2b, 0x4c, 0x44, 0x44, 0x40, 0x03, 0x03, 0x0f, 0x07, 0x13, 0x07, 0x1b, 0x40, 0x4c, ++ 0x20, 0x07, 0x40, 0x1b, 0x40, 0x4c, 0x20, 0x07, 0x40, 0x1b, 0x40, 0x4c, 0x20, 0x07, 0x40, 0x44, ++ 0x03, 0x08, 0x08, 0x0f, 0x1b, 0x0f, 0x1b, 0x07, 0x1b, 0x03, 0x44, 0x1b, 0x03, 0x44, 0x40, 0x40, ++ 0x44, 0x1f, 0x13, 0x0b, 0x44, 0x0f, 0x0b, 0x03, 0x07, 0x3b, 0x27, 0x1f, 0x03, 0x1b, 0x17, 0x0f, ++ 0x44, 0x20, 0x14, 0x08, 0x44, 0x43, 0x17, 0x04, 0x0b, 0x07, 0x1b, 0x0c, 0x0f, 0x0f, 0x40, 0x40, ++ 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x07, 0x54, 0x04, 0x4b, 0x58, 0x40, 0x40, 0x40, 0x40, 0x40, 0x48, 0x40, 0x40, 0x40, 0x48, 0x21, ++ 0x04, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x07, 0x0c, 0x0c, 0x43, ++ 0x4b, 0x10, 0x0c, 0x07, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x04, 0x04, 0x04, 0x04, 0x08, 0x00, ++ 0x43, 0x07, 0x00, 0x4f, 0x43, 0x0c, 0x43, 0x5b, 0x4f, 0x43, 0x14, 0x14, 0x10, 0x21, 0x04, 0x04, ++ 0x08, 0x00, 0x43, 0x07, 0x00, 0x4f, 0x43, 0x0c, 0x43, 0x5b, 0x4f, 0x43, 0x14, 0x14, 0x10, 0x21, ++ 0x28, 0x54, 0x2c, 0x4b, 0x43, 0x43, 0x00, 0x04, 0x04, 0x10, 0x08, 0x14, 0x08, 0x1c, 0x00, 0x4b, ++ 0x1f, 0x07, 0x00, 0x1c, 0x00, 0x4b, 0x1f, 0x07, 0x00, 0x1c, 0x00, 0x4b, 0x1f, 0x07, 0x00, 0x43, ++ 0x04, 0x07, 0x07, 0x0f, 0x1c, 0x0f, 0x1c, 0x07, 0x1c, 0x04, 0x43, 0x1c, 0x04, 0x43, 0x40, 0x40, ++ 0x43, 0x20, 0x14, 0x0c, 0x43, 0x0f, 0x0c, 0x04, 0x07, 0x3c, 0x27, 0x20, 0x04, 0x1c, 0x18, 0x0f, ++ 0x43, 0x1f, 0x13, 0x07, 0x43, 0x44, 0x18, 0x03, 0x0c, 0x07, 0x1c, 0x0b, 0x0f, 0x0f, 0x40, 0x40, ++ 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x07, 0x55, 0x04, 0x4b, 0x58, 0x40, 0x40, 0x40, 0x40, 0x40, 0x49, 0x40, 0x40, 0x40, 0x49, 0x22, ++ 0x04, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x07, 0x0c, 0x0c, 0x42, ++ 0x4b, 0x11, 0x0c, 0x06, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x04, 0x04, 0x05, 0x05, 0x08, 0x00, ++ 0x43, 0x07, 0x00, 0x4f, 0x43, 0x0d, 0x42, 0x5b, 0x4f, 0x42, 0x16, 0x15, 0x10, 0x22, 0x05, 0x05, ++ 0x08, 0x00, 0x43, 0x07, 0x00, 0x4f, 0x43, 0x0d, 0x42, 0x5b, 0x4f, 0x42, 0x16, 0x15, 0x10, 0x22, ++ 0x29, 0x54, 0x2c, 0x4b, 0x42, 0x42, 0x00, 0x05, 0x05, 0x11, 0x08, 0x15, 0x08, 0x1d, 0x00, 0x4b, ++ 0x1e, 0x07, 0x00, 0x1d, 0x00, 0x4b, 0x1e, 0x07, 0x00, 0x1d, 0x00, 0x4b, 0x1e, 0x07, 0x00, 0x43, ++ 0x04, 0x06, 0x06, 0x0f, 0x1c, 0x0f, 0x1c, 0x07, 0x1c, 0x04, 0x42, 0x1c, 0x04, 0x42, 0x40, 0x40, ++ 0x43, 0x21, 0x14, 0x0c, 0x43, 0x0f, 0x0c, 0x04, 0x07, 0x3e, 0x27, 0x21, 0x04, 0x1d, 0x18, 0x0f, ++ 0x43, 0x1e, 0x13, 0x06, 0x43, 0x46, 0x18, 0x02, 0x0c, 0x07, 0x1c, 0x0b, 0x0f, 0x0f, 0x40, 0x40, ++ 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x07, 0x56, 0x04, 0x4b, 0x58, 0x40, 0x40, 0x40, 0x40, 0x40, 0x49, 0x40, 0x40, 0x40, 0x49, 0x24, ++ 0x04, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x07, 0x0c, 0x0c, 0x41, ++ 0x4b, 0x13, 0x0c, 0x06, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x04, 0x04, 0x06, 0x06, 0x09, 0x01, ++ 0x43, 0x07, 0x01, 0x4e, 0x43, 0x0e, 0x41, 0x5b, 0x4e, 0x41, 0x18, 0x16, 0x11, 0x24, 0x06, 0x06, ++ 0x09, 0x01, 0x43, 0x07, 0x01, 0x4e, 0x43, 0x0e, 0x41, 0x5b, 0x4e, 0x41, 0x18, 0x16, 0x11, 0x24, ++ 0x2b, 0x54, 0x2c, 0x4b, 0x41, 0x41, 0x01, 0x06, 0x06, 0x13, 0x09, 0x16, 0x09, 0x1e, 0x01, 0x4b, ++ 0x1e, 0x07, 0x01, 0x1e, 0x01, 0x4b, 0x1e, 0x07, 0x01, 0x1e, 0x01, 0x4b, 0x1e, 0x07, 0x01, 0x43, ++ 0x04, 0x06, 0x06, 0x0f, 0x1c, 0x0f, 0x1c, 0x07, 0x1c, 0x04, 0x41, 0x1c, 0x04, 0x41, 0x40, 0x40, ++ 0x43, 0x23, 0x14, 0x0c, 0x43, 0x0f, 0x0c, 0x04, 0x07, 0x3e, 0x27, 0x23, 0x04, 0x1e, 0x19, 0x0f, ++ 0x43, 0x1e, 0x13, 0x06, 0x43, 0x48, 0x19, 0x01, 0x0c, 0x07, 0x1c, 0x0b, 0x0f, 0x0f, 0x40, 0x40, ++ 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x07, 0x57, 0x05, 0x4a, 0x58, 0x40, 0x40, 0x40, 0x40, 0x40, 0x4a, 0x40, 0x40, 0x40, 0x4a, 0x26, ++ 0x05, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x07, 0x0d, 0x0d, 0x40, ++ 0x4a, 0x14, 0x0d, 0x05, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x05, 0x05, 0x07, 0x07, 0x0a, 0x02, ++ 0x42, 0x07, 0x02, 0x4d, 0x42, 0x0f, 0x40, 0x5a, 0x4d, 0x40, 0x19, 0x17, 0x12, 0x26, 0x07, 0x07, ++ 0x0a, 0x02, 0x42, 0x07, 0x02, 0x4d, 0x42, 0x0f, 0x40, 0x5a, 0x4d, 0x40, 0x19, 0x17, 0x12, 0x26, ++ 0x2c, 0x55, 0x2d, 0x4a, 0x40, 0x40, 0x02, 0x07, 0x07, 0x14, 0x0a, 0x17, 0x0a, 0x1f, 0x02, 0x4a, ++ 0x1d, 0x07, 0x02, 0x1f, 0x02, 0x4a, 0x1d, 0x07, 0x02, 0x1f, 0x02, 0x4a, 0x1d, 0x07, 0x02, 0x42, ++ 0x05, 0x05, 0x05, 0x0f, 0x1d, 0x0f, 0x1d, 0x07, 0x1d, 0x05, 0x40, 0x1d, 0x05, 0x40, 0x40, 0x40, ++ 0x42, 0x24, 0x15, 0x0d, 0x42, 0x0f, 0x0d, 0x05, 0x07, 0x3e, 0x27, 0x24, 0x05, 0x1f, 0x1a, 0x0f, ++ 0x42, 0x1d, 0x12, 0x05, 0x42, 0x49, 0x1a, 0x00, 0x0d, 0x07, 0x1d, 0x0a, 0x0f, 0x0f, 0x40, 0x40, ++ 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x07, 0x58, 0x05, 0x4a, 0x58, 0x40, 0x40, 0x40, 0x40, 0x40, 0x4a, 0x40, 0x40, 0x40, 0x4a, 0x28, ++ 0x05, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x07, 0x0d, 0x0d, 0x00, ++ 0x4a, 0x15, 0x0d, 0x05, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x05, 0x05, 0x08, 0x08, 0x0a, 0x02, ++ 0x42, 0x07, 0x02, 0x4d, 0x42, 0x10, 0x00, 0x5a, 0x4d, 0x00, 0x1b, 0x18, 0x12, 0x28, 0x08, 0x08, ++ 0x0a, 0x02, 0x42, 0x07, 0x02, 0x4d, 0x42, 0x10, 0x00, 0x5a, 0x4d, 0x00, 0x1b, 0x18, 0x12, 0x28, ++ 0x2d, 0x55, 0x2d, 0x4a, 0x00, 0x00, 0x02, 0x08, 0x08, 0x15, 0x0a, 0x18, 0x0a, 0x20, 0x02, 0x4a, ++ 0x1d, 0x07, 0x02, 0x20, 0x02, 0x4a, 0x1d, 0x07, 0x02, 0x20, 0x02, 0x4a, 0x1d, 0x07, 0x02, 0x42, ++ 0x05, 0x05, 0x05, 0x0f, 0x1d, 0x0f, 0x1d, 0x07, 0x1d, 0x05, 0x00, 0x1d, 0x05, 0x00, 0x40, 0x40, ++ 0x42, 0x25, 0x15, 0x0d, 0x42, 0x0f, 0x0d, 0x05, 0x07, 0x3e, 0x27, 0x25, 0x05, 0x20, 0x1a, 0x0f, ++ 0x42, 0x1d, 0x12, 0x05, 0x42, 0x4b, 0x1a, 0x40, 0x0d, 0x07, 0x1d, 0x0a, 0x0f, 0x0f, 0x40, 0x40, ++ 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x07, 0x59, 0x05, 0x4a, 0x58, 0x40, 0x40, 0x40, 0x40, 0x40, 0x4b, 0x40, 0x40, 0x40, 0x4b, 0x2a, ++ 0x05, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x07, 0x0d, 0x0d, 0x01, ++ 0x4a, 0x16, 0x0d, 0x04, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x05, 0x05, 0x09, 0x09, 0x0b, 0x03, ++ 0x42, 0x07, 0x03, 0x4c, 0x42, 0x11, 0x01, 0x5a, 0x4c, 0x01, 0x1c, 0x19, 0x13, 0x2a, 0x09, 0x09, ++ 0x0b, 0x03, 0x42, 0x07, 0x03, 0x4c, 0x42, 0x11, 0x01, 0x5a, 0x4c, 0x01, 0x1c, 0x19, 0x13, 0x2a, ++ 0x2e, 0x55, 0x2d, 0x4a, 0x01, 0x01, 0x03, 0x09, 0x09, 0x16, 0x0b, 0x19, 0x0b, 0x21, 0x03, 0x4a, ++ 0x1c, 0x07, 0x03, 0x21, 0x03, 0x4a, 0x1c, 0x07, 0x03, 0x21, 0x03, 0x4a, 0x1c, 0x07, 0x03, 0x42, ++ 0x05, 0x04, 0x04, 0x0f, 0x1d, 0x0f, 0x1d, 0x07, 0x1d, 0x05, 0x01, 0x1d, 0x05, 0x01, 0x40, 0x40, ++ 0x42, 0x26, 0x15, 0x0d, 0x42, 0x0f, 0x0d, 0x05, 0x07, 0x3e, 0x27, 0x26, 0x05, 0x21, 0x1b, 0x0f, ++ 0x42, 0x1c, 0x12, 0x04, 0x42, 0x4c, 0x1b, 0x41, 0x0d, 0x07, 0x1d, 0x0a, 0x0f, 0x0f, 0x40, 0x40, ++ 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x07, 0x5a, 0x06, 0x49, 0x58, 0x40, 0x40, 0x40, 0x40, 0x40, 0x4c, 0x40, 0x40, 0x40, 0x4c, 0x2c, ++ 0x06, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x07, 0x0e, 0x0e, 0x02, ++ 0x49, 0x18, 0x0e, 0x03, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x06, 0x06, 0x0a, 0x0a, 0x0c, 0x04, ++ 0x41, 0x07, 0x04, 0x4b, 0x41, 0x12, 0x02, 0x59, 0x4b, 0x02, 0x1e, 0x1a, 0x14, 0x2c, 0x0a, 0x0a, ++ 0x0c, 0x04, 0x41, 0x07, 0x04, 0x4b, 0x41, 0x12, 0x02, 0x59, 0x4b, 0x02, 0x1e, 0x1a, 0x14, 0x2c, ++ 0x30, 0x56, 0x2e, 0x49, 0x02, 0x02, 0x04, 0x0a, 0x0a, 0x18, 0x0c, 0x1a, 0x0c, 0x22, 0x04, 0x49, ++ 0x1b, 0x07, 0x04, 0x22, 0x04, 0x49, 0x1b, 0x07, 0x04, 0x22, 0x04, 0x49, 0x1b, 0x07, 0x04, 0x41, ++ 0x06, 0x03, 0x03, 0x0f, 0x1e, 0x0f, 0x1e, 0x07, 0x1e, 0x06, 0x02, 0x1e, 0x06, 0x02, 0x40, 0x40, ++ 0x41, 0x28, 0x16, 0x0e, 0x41, 0x0f, 0x0e, 0x06, 0x07, 0x3e, 0x27, 0x28, 0x06, 0x22, 0x1c, 0x0f, ++ 0x41, 0x1b, 0x11, 0x03, 0x41, 0x4e, 0x1c, 0x42, 0x0e, 0x07, 0x1e, 0x09, 0x0f, 0x0f, 0x40, 0x40, ++ 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x07, 0x5b, 0x06, 0x49, 0x58, 0x40, 0x40, 0x40, 0x40, 0x40, 0x4c, 0x40, 0x40, 0x40, 0x4c, 0x2e, ++ 0x06, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x07, 0x0e, 0x0e, 0x03, ++ 0x49, 0x19, 0x0e, 0x03, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x06, 0x06, 0x0b, 0x0b, 0x0c, 0x04, ++ 0x41, 0x07, 0x04, 0x4b, 0x41, 0x13, 0x03, 0x59, 0x4b, 0x03, 0x1f, 0x1b, 0x14, 0x2e, 0x0b, 0x0b, ++ 0x0c, 0x04, 0x41, 0x07, 0x04, 0x4b, 0x41, 0x13, 0x03, 0x59, 0x4b, 0x03, 0x1f, 0x1b, 0x14, 0x2e, ++ 0x31, 0x56, 0x2e, 0x49, 0x03, 0x03, 0x04, 0x0b, 0x0b, 0x19, 0x0c, 0x1b, 0x0c, 0x23, 0x04, 0x49, ++ 0x1b, 0x07, 0x04, 0x23, 0x04, 0x49, 0x1b, 0x07, 0x04, 0x23, 0x04, 0x49, 0x1b, 0x07, 0x04, 0x41, ++ 0x06, 0x03, 0x03, 0x0f, 0x1e, 0x0f, 0x1e, 0x07, 0x1e, 0x06, 0x03, 0x1e, 0x06, 0x03, 0x40, 0x40, ++ 0x41, 0x29, 0x16, 0x0e, 0x41, 0x0f, 0x0e, 0x06, 0x07, 0x3e, 0x27, 0x29, 0x06, 0x23, 0x1c, 0x0f, ++ 0x41, 0x1b, 0x11, 0x03, 0x41, 0x4f, 0x1c, 0x43, 0x0e, 0x07, 0x1e, 0x09, 0x0f, 0x0f, 0x40, 0x40, ++ 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x07, 0x5c, 0x06, 0x49, 0x58, 0x40, 0x40, 0x40, 0x40, 0x40, 0x4d, 0x40, 0x40, 0x40, 0x4d, 0x30, ++ 0x06, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x07, 0x0e, 0x0e, 0x04, ++ 0x49, 0x1a, 0x0e, 0x02, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x06, 0x06, 0x0c, 0x0c, 0x0d, 0x05, ++ 0x41, 0x07, 0x05, 0x4a, 0x41, 0x14, 0x04, 0x59, 0x4a, 0x04, 0x21, 0x1c, 0x15, 0x30, 0x0c, 0x0c, ++ 0x0d, 0x05, 0x41, 0x07, 0x05, 0x4a, 0x41, 0x14, 0x04, 0x59, 0x4a, 0x04, 0x21, 0x1c, 0x15, 0x30, ++ 0x32, 0x56, 0x2e, 0x49, 0x04, 0x04, 0x05, 0x0c, 0x0c, 0x1a, 0x0d, 0x1c, 0x0d, 0x24, 0x05, 0x49, ++ 0x1a, 0x07, 0x05, 0x24, 0x05, 0x49, 0x1a, 0x07, 0x05, 0x24, 0x05, 0x49, 0x1a, 0x07, 0x05, 0x41, ++ 0x06, 0x02, 0x02, 0x0f, 0x1e, 0x0f, 0x1e, 0x07, 0x1e, 0x06, 0x04, 0x1e, 0x06, 0x04, 0x40, 0x40, ++ 0x41, 0x2a, 0x16, 0x0e, 0x41, 0x0f, 0x0e, 0x06, 0x07, 0x3e, 0x27, 0x2a, 0x06, 0x24, 0x1d, 0x0f, ++ 0x41, 0x1a, 0x11, 0x02, 0x41, 0x51, 0x1d, 0x44, 0x0e, 0x07, 0x1e, 0x09, 0x0f, 0x0f, 0x40, 0x40, ++ 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x07, 0x5d, 0x06, 0x49, 0x58, 0x40, 0x40, 0x40, 0x40, 0x40, 0x4e, 0x40, 0x40, 0x40, 0x4e, 0x31, ++ 0x06, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x07, 0x0e, 0x0e, 0x04, ++ 0x49, 0x1b, 0x0e, 0x01, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x06, 0x06, 0x0c, 0x0c, 0x0d, 0x05, ++ 0x41, 0x07, 0x05, 0x4a, 0x41, 0x14, 0x04, 0x59, 0x4a, 0x04, 0x22, 0x1c, 0x15, 0x31, 0x0c, 0x0c, ++ 0x0d, 0x05, 0x41, 0x07, 0x05, 0x4a, 0x41, 0x14, 0x04, 0x59, 0x4a, 0x04, 0x22, 0x1c, 0x15, 0x31, ++ 0x33, 0x57, 0x2e, 0x49, 0x04, 0x04, 0x05, 0x0c, 0x0c, 0x1b, 0x0d, 0x1c, 0x0d, 0x24, 0x05, 0x49, ++ 0x19, 0x07, 0x05, 0x24, 0x05, 0x49, 0x19, 0x07, 0x05, 0x24, 0x05, 0x49, 0x19, 0x07, 0x05, 0x41, ++ 0x06, 0x01, 0x01, 0x0f, 0x1e, 0x0f, 0x1e, 0x07, 0x1e, 0x06, 0x04, 0x1e, 0x06, 0x04, 0x40, 0x40, ++ 0x41, 0x2b, 0x16, 0x0e, 0x41, 0x0f, 0x0e, 0x06, 0x07, 0x3e, 0x27, 0x2b, 0x06, 0x24, 0x1d, 0x0f, ++ 0x41, 0x19, 0x10, 0x01, 0x41, 0x53, 0x1d, 0x45, 0x0e, 0x07, 0x1e, 0x08, 0x0f, 0x0f, 0x40, 0x40, ++ 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x07, 0x5d, 0x07, 0x48, 0x58, 0x40, 0x40, 0x40, 0x40, 0x40, 0x4e, 0x40, 0x40, 0x40, 0x4e, 0x33, ++ 0x07, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x07, 0x0f, 0x0f, 0x05, ++ 0x48, 0x1d, 0x0f, 0x01, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x07, 0x07, 0x0d, 0x0d, 0x0e, 0x06, ++ 0x40, 0x07, 0x06, 0x49, 0x40, 0x15, 0x05, 0x58, 0x49, 0x05, 0x24, 0x1d, 0x16, 0x33, 0x0d, 0x0d, ++ 0x0e, 0x06, 0x40, 0x07, 0x06, 0x49, 0x40, 0x15, 0x05, 0x58, 0x49, 0x05, 0x24, 0x1d, 0x16, 0x33, ++ 0x35, 0x57, 0x2f, 0x48, 0x05, 0x05, 0x06, 0x0d, 0x0d, 0x1d, 0x0e, 0x1d, 0x0e, 0x25, 0x06, 0x48, ++ 0x19, 0x07, 0x06, 0x25, 0x06, 0x48, 0x19, 0x07, 0x06, 0x25, 0x06, 0x48, 0x19, 0x07, 0x06, 0x40, ++ 0x07, 0x01, 0x01, 0x0f, 0x1f, 0x0f, 0x1f, 0x07, 0x1f, 0x07, 0x05, 0x1f, 0x07, 0x05, 0x40, 0x40, ++ 0x40, 0x2d, 0x17, 0x0f, 0x40, 0x0f, 0x0f, 0x07, 0x07, 0x3e, 0x27, 0x2d, 0x07, 0x25, 0x1e, 0x0f, ++ 0x40, 0x19, 0x10, 0x01, 0x40, 0x54, 0x1e, 0x45, 0x0f, 0x07, 0x1f, 0x08, 0x0f, 0x0f, 0x40, 0x40, ++ 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x07, 0x5e, 0x07, 0x48, 0x58, 0x40, 0x40, 0x40, 0x40, 0x40, 0x4f, 0x40, 0x40, 0x40, 0x4f, 0x35, ++ 0x07, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x07, 0x0f, 0x0f, 0x06, ++ 0x48, 0x1e, 0x0f, 0x00, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x07, 0x07, 0x0e, 0x0e, 0x0f, 0x07, ++ 0x40, 0x07, 0x07, 0x48, 0x40, 0x16, 0x06, 0x58, 0x48, 0x06, 0x26, 0x1e, 0x17, 0x35, 0x0e, 0x0e, ++ 0x0f, 0x07, 0x40, 0x07, 0x07, 0x48, 0x40, 0x16, 0x06, 0x58, 0x48, 0x06, 0x26, 0x1e, 0x17, 0x35, ++ 0x36, 0x57, 0x2f, 0x48, 0x06, 0x06, 0x07, 0x0e, 0x0e, 0x1e, 0x0f, 0x1e, 0x0f, 0x26, 0x07, 0x48, ++ 0x18, 0x07, 0x07, 0x26, 0x07, 0x48, 0x18, 0x07, 0x07, 0x26, 0x07, 0x48, 0x18, 0x07, 0x07, 0x40, ++ 0x07, 0x00, 0x00, 0x0f, 0x1f, 0x0f, 0x1f, 0x07, 0x1f, 0x07, 0x06, 0x1f, 0x07, 0x06, 0x40, 0x40, ++ 0x40, 0x2e, 0x17, 0x0f, 0x40, 0x0f, 0x0f, 0x07, 0x07, 0x3e, 0x27, 0x2e, 0x07, 0x26, 0x1f, 0x0f, ++ 0x40, 0x18, 0x10, 0x00, 0x40, 0x56, 0x1f, 0x46, 0x0f, 0x07, 0x1f, 0x08, 0x0f, 0x0f, 0x40, 0x40, ++ 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x07, 0x5f, 0x07, 0x48, 0x58, 0x40, 0x40, 0x40, 0x40, 0x40, 0x4f, 0x40, 0x40, 0x40, 0x4f, 0x37, ++ 0x07, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x07, 0x0f, 0x0f, 0x07, ++ 0x48, 0x1f, 0x0f, 0x00, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x07, 0x07, 0x0f, 0x0f, 0x0f, 0x07, ++ 0x40, 0x07, 0x07, 0x48, 0x40, 0x17, 0x07, 0x58, 0x48, 0x07, 0x27, 0x1f, 0x17, 0x37, 0x0f, 0x0f, ++ 0x0f, 0x07, 0x40, 0x07, 0x07, 0x48, 0x40, 0x17, 0x07, 0x58, 0x48, 0x07, 0x27, 0x1f, 0x17, 0x37, ++ 0x37, 0x57, 0x2f, 0x48, 0x07, 0x07, 0x07, 0x0f, 0x0f, 0x1f, 0x0f, 0x1f, 0x0f, 0x27, 0x07, 0x48, ++ 0x18, 0x07, 0x07, 0x27, 0x07, 0x48, 0x18, 0x07, 0x07, 0x27, 0x07, 0x48, 0x18, 0x07, 0x07, 0x40, ++ 0x07, 0x00, 0x00, 0x0f, 0x1f, 0x0f, 0x1f, 0x07, 0x1f, 0x07, 0x07, 0x1f, 0x07, 0x07, 0x40, 0x40, ++ 0x40, 0x2f, 0x17, 0x0f, 0x40, 0x0f, 0x0f, 0x07, 0x07, 0x3e, 0x27, 0x2f, 0x07, 0x27, 0x1f, 0x0f, ++ 0x40, 0x18, 0x10, 0x00, 0x40, 0x57, 0x1f, 0x47, 0x0f, 0x07, 0x1f, 0x08, 0x0f, 0x0f, 0x40, 0x40, ++ 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x07, 0x07, 0x48, 0x48, 0x60, 0x40, 0x27, 0x07, 0x07, 0x27, 0x40, 0x48, 0x40, 0x40, 0x40, 0x0f, ++ 0x48, 0x68, 0x60, 0x40, 0x68, 0x68, 0x68, 0x68, 0x68, 0x07, 0x07, 0x0f, 0x50, 0x40, 0x60, 0x07, ++ 0x68, 0x27, 0x48, 0x17, 0x40, 0x50, 0x1f, 0x40, 0x40, 0x40, 0x48, 0x48, 0x58, 0x60, 0x60, 0x60, ++ 0x68, 0x68, 0x58, 0x68, 0x60, 0x60, 0x60, 0x68, 0x68, 0x68, 0x60, 0x50, 0x48, 0x50, 0x58, 0x60, ++ 0x60, 0x60, 0x68, 0x68, 0x58, 0x68, 0x60, 0x60, 0x60, 0x68, 0x68, 0x68, 0x60, 0x50, 0x48, 0x50, ++ 0x07, 0x50, 0x58, 0x40, 0x48, 0x40, 0x48, 0x07, 0x48, 0x48, 0x48, 0x68, 0x07, 0x1f, 0x17, 0x50, ++ 0x0f, 0x07, 0x40, 0x1f, 0x17, 0x50, 0x0f, 0x07, 0x40, 0x1f, 0x17, 0x50, 0x0f, 0x07, 0x40, 0x40, ++ 0x07, 0x48, 0x48, 0x48, 0x07, 0x48, 0x07, 0x17, 0x17, 0x17, 0x50, 0x17, 0x17, 0x50, 0x40, 0x40, ++ 0x40, 0x2f, 0x2f, 0x17, 0x40, 0x0f, 0x17, 0x1f, 0x1f, 0x1f, 0x27, 0x0f, 0x07, 0x07, 0x0f, 0x07, ++ 0x07, 0x3e, 0x1f, 0x17, 0x40, 0x17, 0x07, 0x1f, 0x48, 0x17, 0x48, 0x40, 0x48, 0x17, 0x40, 0x40, ++ 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x07, 0x07, 0x47, 0x47, 0x5f, 0x40, 0x27, 0x07, 0x07, 0x27, 0x40, 0x47, 0x40, 0x40, 0x40, 0x0f, ++ 0x47, 0x66, 0x5f, 0x00, 0x66, 0x66, 0x66, 0x65, 0x65, 0x07, 0x07, 0x0f, 0x4f, 0x00, 0x5e, 0x07, ++ 0x67, 0x27, 0x47, 0x17, 0x40, 0x4f, 0x1f, 0x40, 0x40, 0x40, 0x47, 0x47, 0x57, 0x5f, 0x5e, 0x5f, ++ 0x66, 0x66, 0x57, 0x67, 0x5f, 0x5e, 0x5f, 0x67, 0x67, 0x66, 0x5e, 0x4f, 0x47, 0x4f, 0x57, 0x5f, ++ 0x5e, 0x5f, 0x66, 0x66, 0x57, 0x67, 0x5f, 0x5e, 0x5f, 0x67, 0x67, 0x66, 0x5e, 0x4f, 0x47, 0x4f, ++ 0x08, 0x4f, 0x56, 0x40, 0x48, 0x40, 0x47, 0x07, 0x47, 0x47, 0x47, 0x66, 0x07, 0x1f, 0x17, 0x4f, ++ 0x10, 0x07, 0x40, 0x1f, 0x17, 0x4f, 0x10, 0x07, 0x40, 0x1f, 0x17, 0x4f, 0x10, 0x07, 0x40, 0x40, ++ 0x07, 0x47, 0x47, 0x47, 0x08, 0x47, 0x08, 0x17, 0x17, 0x17, 0x4f, 0x17, 0x17, 0x4f, 0x40, 0x40, ++ 0x40, 0x2f, 0x2f, 0x17, 0x40, 0x0f, 0x17, 0x1f, 0x1f, 0x20, 0x27, 0x10, 0x07, 0x08, 0x10, 0x08, ++ 0x07, 0x3e, 0x1f, 0x17, 0x40, 0x17, 0x08, 0x1f, 0x47, 0x17, 0x46, 0x00, 0x47, 0x17, 0x40, 0x40, ++ 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x07, 0x06, 0x46, 0x47, 0x5e, 0x40, 0x26, 0x06, 0x06, 0x27, 0x40, 0x47, 0x40, 0x40, 0x40, 0x0f, ++ 0x47, 0x64, 0x5e, 0x01, 0x65, 0x64, 0x64, 0x63, 0x63, 0x07, 0x07, 0x0f, 0x4e, 0x00, 0x5d, 0x07, ++ 0x66, 0x27, 0x46, 0x17, 0x40, 0x4f, 0x1e, 0x40, 0x40, 0x40, 0x47, 0x47, 0x56, 0x5e, 0x5d, 0x5e, ++ 0x65, 0x64, 0x56, 0x66, 0x5e, 0x5c, 0x5e, 0x66, 0x66, 0x65, 0x5d, 0x4e, 0x46, 0x4e, 0x56, 0x5e, ++ 0x5d, 0x5e, 0x65, 0x64, 0x56, 0x66, 0x5e, 0x5c, 0x5e, 0x66, 0x66, 0x65, 0x5d, 0x4e, 0x46, 0x4e, ++ 0x09, 0x4f, 0x54, 0x40, 0x48, 0x40, 0x47, 0x07, 0x47, 0x46, 0x46, 0x64, 0x07, 0x1f, 0x16, 0x4f, ++ 0x10, 0x07, 0x40, 0x1f, 0x16, 0x4f, 0x10, 0x07, 0x40, 0x1f, 0x16, 0x4f, 0x10, 0x07, 0x40, 0x40, ++ 0x07, 0x46, 0x46, 0x46, 0x09, 0x46, 0x09, 0x17, 0x17, 0x16, 0x4f, 0x17, 0x16, 0x4f, 0x40, 0x40, ++ 0x40, 0x2e, 0x2e, 0x17, 0x40, 0x0f, 0x17, 0x1e, 0x1e, 0x20, 0x27, 0x10, 0x07, 0x09, 0x10, 0x08, ++ 0x07, 0x3e, 0x1f, 0x17, 0x40, 0x17, 0x08, 0x1e, 0x46, 0x17, 0x45, 0x01, 0x46, 0x17, 0x40, 0x40, ++ 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x07, 0x06, 0x45, 0x47, 0x5e, 0x40, 0x25, 0x06, 0x05, 0x27, 0x40, 0x47, 0x40, 0x40, 0x40, 0x0f, ++ 0x47, 0x63, 0x5d, 0x01, 0x64, 0x63, 0x62, 0x60, 0x60, 0x07, 0x07, 0x0f, 0x4e, 0x00, 0x5c, 0x07, ++ 0x65, 0x27, 0x45, 0x17, 0x40, 0x4f, 0x1d, 0x40, 0x40, 0x40, 0x47, 0x47, 0x56, 0x5d, 0x5c, 0x5d, ++ 0x64, 0x63, 0x56, 0x65, 0x5d, 0x5b, 0x5d, 0x65, 0x65, 0x64, 0x5c, 0x4d, 0x46, 0x4d, 0x56, 0x5d, ++ 0x5c, 0x5d, 0x64, 0x63, 0x56, 0x65, 0x5d, 0x5b, 0x5d, 0x65, 0x65, 0x64, 0x5c, 0x4d, 0x46, 0x4d, ++ 0x09, 0x4f, 0x52, 0x40, 0x48, 0x40, 0x47, 0x07, 0x47, 0x46, 0x46, 0x62, 0x07, 0x1f, 0x16, 0x4f, ++ 0x10, 0x07, 0x40, 0x1f, 0x16, 0x4f, 0x10, 0x07, 0x40, 0x1f, 0x16, 0x4f, 0x10, 0x07, 0x40, 0x40, ++ 0x07, 0x46, 0x46, 0x45, 0x09, 0x45, 0x09, 0x17, 0x17, 0x16, 0x4f, 0x17, 0x16, 0x4f, 0x40, 0x40, ++ 0x40, 0x2d, 0x2d, 0x17, 0x40, 0x0f, 0x17, 0x1e, 0x1e, 0x20, 0x27, 0x10, 0x07, 0x09, 0x10, 0x08, ++ 0x07, 0x3d, 0x1f, 0x17, 0x40, 0x17, 0x08, 0x1e, 0x45, 0x17, 0x44, 0x01, 0x45, 0x17, 0x40, 0x40, ++ 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x07, 0x05, 0x44, 0x46, 0x5d, 0x40, 0x24, 0x05, 0x04, 0x27, 0x40, 0x46, 0x40, 0x40, 0x40, 0x0f, ++ 0x46, 0x61, 0x5c, 0x02, 0x63, 0x61, 0x60, 0x5e, 0x5e, 0x07, 0x07, 0x0e, 0x4d, 0x01, 0x5b, 0x07, ++ 0x64, 0x27, 0x44, 0x16, 0x40, 0x4e, 0x1c, 0x40, 0x40, 0x40, 0x46, 0x46, 0x55, 0x5c, 0x5b, 0x5c, ++ 0x63, 0x61, 0x55, 0x64, 0x5c, 0x59, 0x5c, 0x64, 0x64, 0x63, 0x5b, 0x4c, 0x45, 0x4c, 0x55, 0x5c, ++ 0x5b, 0x5c, 0x63, 0x61, 0x55, 0x64, 0x5c, 0x59, 0x5c, 0x64, 0x64, 0x63, 0x5b, 0x4c, 0x45, 0x4c, ++ 0x0a, 0x4e, 0x50, 0x40, 0x48, 0x40, 0x46, 0x07, 0x46, 0x45, 0x45, 0x60, 0x07, 0x1e, 0x15, 0x4e, ++ 0x11, 0x07, 0x40, 0x1e, 0x15, 0x4e, 0x11, 0x07, 0x40, 0x1e, 0x15, 0x4e, 0x11, 0x07, 0x40, 0x41, ++ 0x07, 0x45, 0x45, 0x44, 0x0a, 0x44, 0x0a, 0x16, 0x17, 0x15, 0x4e, 0x17, 0x15, 0x4e, 0x40, 0x40, ++ 0x40, 0x2c, 0x2c, 0x16, 0x40, 0x0f, 0x16, 0x1d, 0x1d, 0x21, 0x27, 0x11, 0x07, 0x0a, 0x11, 0x09, ++ 0x06, 0x3c, 0x1e, 0x16, 0x40, 0x16, 0x09, 0x1d, 0x44, 0x16, 0x43, 0x02, 0x44, 0x16, 0x40, 0x40, ++ 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x07, 0x04, 0x43, 0x46, 0x5c, 0x40, 0x23, 0x04, 0x03, 0x27, 0x40, 0x46, 0x40, 0x40, 0x40, 0x0f, ++ 0x46, 0x60, 0x5b, 0x03, 0x61, 0x60, 0x5e, 0x5b, 0x5b, 0x07, 0x07, 0x0e, 0x4c, 0x01, 0x59, 0x07, ++ 0x63, 0x27, 0x43, 0x16, 0x40, 0x4e, 0x1b, 0x40, 0x40, 0x40, 0x46, 0x46, 0x54, 0x5b, 0x59, 0x5b, ++ 0x61, 0x60, 0x54, 0x63, 0x5b, 0x58, 0x5b, 0x63, 0x63, 0x61, 0x59, 0x4b, 0x44, 0x4b, 0x54, 0x5b, ++ 0x59, 0x5b, 0x61, 0x60, 0x54, 0x63, 0x5b, 0x58, 0x5b, 0x63, 0x63, 0x61, 0x59, 0x4b, 0x44, 0x4b, ++ 0x0b, 0x4e, 0x4e, 0x40, 0x48, 0x40, 0x46, 0x07, 0x46, 0x44, 0x44, 0x5e, 0x07, 0x1e, 0x14, 0x4e, ++ 0x11, 0x07, 0x40, 0x1e, 0x14, 0x4e, 0x11, 0x07, 0x40, 0x1e, 0x14, 0x4e, 0x11, 0x07, 0x40, 0x41, ++ 0x07, 0x44, 0x44, 0x43, 0x0b, 0x43, 0x0b, 0x16, 0x17, 0x14, 0x4e, 0x17, 0x14, 0x4e, 0x40, 0x40, ++ 0x40, 0x2b, 0x2b, 0x16, 0x40, 0x0f, 0x16, 0x1c, 0x1c, 0x21, 0x27, 0x11, 0x07, 0x0b, 0x11, 0x09, ++ 0x06, 0x3b, 0x1e, 0x16, 0x40, 0x16, 0x09, 0x1c, 0x43, 0x16, 0x41, 0x03, 0x43, 0x16, 0x40, 0x40, ++ 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x07, 0x04, 0x42, 0x46, 0x5c, 0x40, 0x22, 0x04, 0x02, 0x27, 0x40, 0x46, 0x40, 0x40, 0x40, 0x0f, ++ 0x46, 0x5e, 0x5a, 0x03, 0x60, 0x5e, 0x5c, 0x59, 0x59, 0x07, 0x07, 0x0e, 0x4c, 0x01, 0x58, 0x07, ++ 0x62, 0x27, 0x42, 0x16, 0x40, 0x4e, 0x1a, 0x40, 0x40, 0x40, 0x46, 0x46, 0x54, 0x5a, 0x58, 0x5a, ++ 0x60, 0x5e, 0x54, 0x62, 0x5a, 0x56, 0x5a, 0x62, 0x62, 0x60, 0x58, 0x4a, 0x44, 0x4a, 0x54, 0x5a, ++ 0x58, 0x5a, 0x60, 0x5e, 0x54, 0x62, 0x5a, 0x56, 0x5a, 0x62, 0x62, 0x60, 0x58, 0x4a, 0x44, 0x4a, ++ 0x0b, 0x4e, 0x4c, 0x40, 0x48, 0x40, 0x46, 0x07, 0x46, 0x44, 0x44, 0x5c, 0x07, 0x1e, 0x14, 0x4e, ++ 0x11, 0x07, 0x40, 0x1e, 0x14, 0x4e, 0x11, 0x07, 0x40, 0x1e, 0x14, 0x4e, 0x11, 0x07, 0x40, 0x41, ++ 0x07, 0x44, 0x44, 0x42, 0x0b, 0x42, 0x0b, 0x16, 0x17, 0x14, 0x4e, 0x17, 0x14, 0x4e, 0x40, 0x40, ++ 0x40, 0x2a, 0x2a, 0x16, 0x40, 0x0f, 0x16, 0x1c, 0x1c, 0x21, 0x27, 0x11, 0x07, 0x0b, 0x11, 0x09, ++ 0x06, 0x3a, 0x1e, 0x16, 0x40, 0x16, 0x09, 0x1c, 0x42, 0x16, 0x40, 0x03, 0x42, 0x16, 0x40, 0x40, ++ 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x07, 0x03, 0x41, 0x45, 0x5b, 0x40, 0x21, 0x03, 0x01, 0x27, 0x40, 0x45, 0x40, 0x40, 0x40, 0x0f, ++ 0x45, 0x5d, 0x59, 0x04, 0x5f, 0x5d, 0x5a, 0x56, 0x56, 0x07, 0x07, 0x0d, 0x4b, 0x02, 0x57, 0x07, ++ 0x61, 0x27, 0x41, 0x15, 0x40, 0x4d, 0x19, 0x40, 0x40, 0x40, 0x45, 0x45, 0x53, 0x59, 0x57, 0x59, ++ 0x5f, 0x5d, 0x53, 0x61, 0x59, 0x55, 0x59, 0x61, 0x61, 0x5f, 0x57, 0x49, 0x43, 0x49, 0x53, 0x59, ++ 0x57, 0x59, 0x5f, 0x5d, 0x53, 0x61, 0x59, 0x55, 0x59, 0x61, 0x61, 0x5f, 0x57, 0x49, 0x43, 0x49, ++ 0x0c, 0x4d, 0x4a, 0x40, 0x48, 0x40, 0x45, 0x07, 0x45, 0x43, 0x43, 0x5a, 0x07, 0x1d, 0x13, 0x4d, ++ 0x12, 0x07, 0x40, 0x1d, 0x13, 0x4d, 0x12, 0x07, 0x40, 0x1d, 0x13, 0x4d, 0x12, 0x07, 0x40, 0x42, ++ 0x07, 0x43, 0x43, 0x41, 0x0c, 0x41, 0x0c, 0x15, 0x17, 0x13, 0x4d, 0x17, 0x13, 0x4d, 0x40, 0x40, ++ 0x40, 0x29, 0x29, 0x15, 0x40, 0x0f, 0x15, 0x1b, 0x1b, 0x22, 0x27, 0x12, 0x07, 0x0c, 0x12, 0x0a, ++ 0x05, 0x39, 0x1d, 0x15, 0x40, 0x15, 0x0a, 0x1b, 0x41, 0x15, 0x00, 0x04, 0x41, 0x15, 0x40, 0x40, ++ 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x07, 0x02, 0x40, 0x45, 0x5b, 0x40, 0x20, 0x02, 0x00, 0x27, 0x40, 0x45, 0x40, 0x40, 0x40, 0x0f, ++ 0x45, 0x5b, 0x58, 0x04, 0x5e, 0x5b, 0x59, 0x54, 0x54, 0x07, 0x07, 0x0d, 0x4b, 0x02, 0x56, 0x07, ++ 0x60, 0x27, 0x40, 0x15, 0x40, 0x4d, 0x18, 0x40, 0x40, 0x40, 0x45, 0x45, 0x53, 0x58, 0x56, 0x58, ++ 0x5e, 0x5b, 0x53, 0x60, 0x58, 0x53, 0x58, 0x60, 0x60, 0x5e, 0x56, 0x48, 0x43, 0x48, 0x53, 0x58, ++ 0x56, 0x58, 0x5e, 0x5b, 0x53, 0x60, 0x58, 0x53, 0x58, 0x60, 0x60, 0x5e, 0x56, 0x48, 0x43, 0x48, ++ 0x0c, 0x4d, 0x49, 0x40, 0x48, 0x40, 0x45, 0x07, 0x45, 0x43, 0x43, 0x59, 0x07, 0x1d, 0x12, 0x4d, ++ 0x12, 0x07, 0x40, 0x1d, 0x12, 0x4d, 0x12, 0x07, 0x40, 0x1d, 0x12, 0x4d, 0x12, 0x07, 0x40, 0x42, ++ 0x07, 0x43, 0x43, 0x40, 0x0c, 0x40, 0x0c, 0x15, 0x17, 0x12, 0x4d, 0x17, 0x12, 0x4d, 0x40, 0x40, ++ 0x40, 0x28, 0x28, 0x15, 0x40, 0x0f, 0x15, 0x1a, 0x1a, 0x22, 0x27, 0x12, 0x07, 0x0c, 0x12, 0x0a, ++ 0x05, 0x38, 0x1d, 0x15, 0x40, 0x15, 0x0a, 0x1a, 0x40, 0x15, 0x01, 0x04, 0x40, 0x15, 0x40, 0x40, ++ 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x07, 0x02, 0x00, 0x45, 0x5a, 0x40, 0x1f, 0x02, 0x40, 0x27, 0x40, 0x45, 0x40, 0x40, 0x40, 0x0f, ++ 0x45, 0x59, 0x57, 0x05, 0x5c, 0x59, 0x57, 0x51, 0x51, 0x07, 0x07, 0x0d, 0x4a, 0x02, 0x54, 0x07, ++ 0x5f, 0x27, 0x00, 0x15, 0x40, 0x4d, 0x17, 0x40, 0x40, 0x40, 0x45, 0x45, 0x52, 0x57, 0x54, 0x57, ++ 0x5c, 0x59, 0x52, 0x5f, 0x57, 0x51, 0x57, 0x5f, 0x5f, 0x5c, 0x54, 0x47, 0x42, 0x47, 0x52, 0x57, ++ 0x54, 0x57, 0x5c, 0x59, 0x52, 0x5f, 0x57, 0x51, 0x57, 0x5f, 0x5f, 0x5c, 0x54, 0x47, 0x42, 0x47, ++ 0x0d, 0x4d, 0x47, 0x40, 0x48, 0x40, 0x45, 0x07, 0x45, 0x42, 0x42, 0x57, 0x07, 0x1d, 0x12, 0x4d, ++ 0x12, 0x07, 0x40, 0x1d, 0x12, 0x4d, 0x12, 0x07, 0x40, 0x1d, 0x12, 0x4d, 0x12, 0x07, 0x40, 0x42, ++ 0x07, 0x42, 0x42, 0x00, 0x0d, 0x00, 0x0d, 0x15, 0x17, 0x12, 0x4d, 0x17, 0x12, 0x4d, 0x40, 0x40, ++ 0x40, 0x27, 0x27, 0x15, 0x40, 0x0f, 0x15, 0x1a, 0x1a, 0x22, 0x27, 0x12, 0x07, 0x0d, 0x12, 0x0a, ++ 0x05, 0x37, 0x1d, 0x15, 0x40, 0x15, 0x0a, 0x1a, 0x00, 0x15, 0x03, 0x05, 0x00, 0x15, 0x40, 0x40, ++ 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x07, 0x01, 0x01, 0x44, 0x59, 0x40, 0x1e, 0x01, 0x41, 0x27, 0x40, 0x44, 0x40, 0x40, 0x40, 0x0f, ++ 0x44, 0x58, 0x56, 0x06, 0x5b, 0x58, 0x55, 0x4f, 0x4f, 0x07, 0x07, 0x0c, 0x49, 0x03, 0x53, 0x07, ++ 0x5e, 0x27, 0x01, 0x14, 0x40, 0x4c, 0x16, 0x40, 0x40, 0x40, 0x44, 0x44, 0x51, 0x56, 0x53, 0x56, ++ 0x5b, 0x58, 0x51, 0x5e, 0x56, 0x50, 0x56, 0x5e, 0x5e, 0x5b, 0x53, 0x46, 0x41, 0x46, 0x51, 0x56, ++ 0x53, 0x56, 0x5b, 0x58, 0x51, 0x5e, 0x56, 0x50, 0x56, 0x5e, 0x5e, 0x5b, 0x53, 0x46, 0x41, 0x46, ++ 0x0e, 0x4c, 0x45, 0x40, 0x48, 0x40, 0x44, 0x07, 0x44, 0x41, 0x41, 0x55, 0x07, 0x1c, 0x11, 0x4c, ++ 0x13, 0x07, 0x40, 0x1c, 0x11, 0x4c, 0x13, 0x07, 0x40, 0x1c, 0x11, 0x4c, 0x13, 0x07, 0x40, 0x43, ++ 0x07, 0x41, 0x41, 0x01, 0x0e, 0x01, 0x0e, 0x14, 0x17, 0x11, 0x4c, 0x17, 0x11, 0x4c, 0x40, 0x40, ++ 0x40, 0x26, 0x26, 0x14, 0x40, 0x0f, 0x14, 0x19, 0x19, 0x23, 0x27, 0x13, 0x07, 0x0e, 0x13, 0x0b, ++ 0x04, 0x36, 0x1c, 0x14, 0x40, 0x14, 0x0b, 0x19, 0x01, 0x14, 0x04, 0x06, 0x01, 0x14, 0x40, 0x40, ++ 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x07, 0x01, 0x02, 0x44, 0x59, 0x40, 0x1d, 0x01, 0x42, 0x27, 0x40, 0x44, 0x40, 0x40, 0x40, 0x0f, ++ 0x44, 0x56, 0x55, 0x06, 0x5a, 0x56, 0x53, 0x4c, 0x4c, 0x07, 0x07, 0x0c, 0x49, 0x03, 0x52, 0x07, ++ 0x5d, 0x27, 0x02, 0x14, 0x40, 0x4c, 0x15, 0x40, 0x40, 0x40, 0x44, 0x44, 0x51, 0x55, 0x52, 0x55, ++ 0x5a, 0x56, 0x51, 0x5d, 0x55, 0x4e, 0x55, 0x5d, 0x5d, 0x5a, 0x52, 0x45, 0x41, 0x45, 0x51, 0x55, ++ 0x52, 0x55, 0x5a, 0x56, 0x51, 0x5d, 0x55, 0x4e, 0x55, 0x5d, 0x5d, 0x5a, 0x52, 0x45, 0x41, 0x45, ++ 0x0e, 0x4c, 0x43, 0x40, 0x48, 0x40, 0x44, 0x07, 0x44, 0x41, 0x41, 0x53, 0x07, 0x1c, 0x11, 0x4c, ++ 0x13, 0x07, 0x40, 0x1c, 0x11, 0x4c, 0x13, 0x07, 0x40, 0x1c, 0x11, 0x4c, 0x13, 0x07, 0x40, 0x43, ++ 0x07, 0x41, 0x41, 0x02, 0x0e, 0x02, 0x0e, 0x14, 0x17, 0x11, 0x4c, 0x17, 0x11, 0x4c, 0x40, 0x40, ++ 0x40, 0x25, 0x25, 0x14, 0x40, 0x0f, 0x14, 0x19, 0x19, 0x23, 0x27, 0x13, 0x07, 0x0e, 0x13, 0x0b, ++ 0x04, 0x35, 0x1c, 0x14, 0x40, 0x14, 0x0b, 0x19, 0x02, 0x14, 0x05, 0x06, 0x02, 0x14, 0x40, 0x40, ++ 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x07, 0x00, 0x03, 0x44, 0x58, 0x40, 0x1c, 0x00, 0x43, 0x27, 0x40, 0x44, 0x40, 0x40, 0x40, 0x0f, ++ 0x44, 0x55, 0x54, 0x07, 0x59, 0x55, 0x51, 0x4a, 0x4a, 0x07, 0x07, 0x0c, 0x48, 0x03, 0x51, 0x07, ++ 0x5c, 0x27, 0x03, 0x14, 0x40, 0x4c, 0x14, 0x40, 0x40, 0x40, 0x44, 0x44, 0x50, 0x54, 0x51, 0x54, ++ 0x59, 0x55, 0x50, 0x5c, 0x54, 0x4d, 0x54, 0x5c, 0x5c, 0x59, 0x51, 0x44, 0x40, 0x44, 0x50, 0x54, ++ 0x51, 0x54, 0x59, 0x55, 0x50, 0x5c, 0x54, 0x4d, 0x54, 0x5c, 0x5c, 0x59, 0x51, 0x44, 0x40, 0x44, ++ 0x0f, 0x4c, 0x41, 0x40, 0x48, 0x40, 0x44, 0x07, 0x44, 0x40, 0x40, 0x51, 0x07, 0x1c, 0x10, 0x4c, ++ 0x13, 0x07, 0x40, 0x1c, 0x10, 0x4c, 0x13, 0x07, 0x40, 0x1c, 0x10, 0x4c, 0x13, 0x07, 0x40, 0x43, ++ 0x07, 0x40, 0x40, 0x03, 0x0f, 0x03, 0x0f, 0x14, 0x17, 0x10, 0x4c, 0x17, 0x10, 0x4c, 0x40, 0x40, ++ 0x40, 0x24, 0x24, 0x14, 0x40, 0x0f, 0x14, 0x18, 0x18, 0x23, 0x27, 0x13, 0x07, 0x0f, 0x13, 0x0b, ++ 0x04, 0x34, 0x1c, 0x14, 0x40, 0x14, 0x0b, 0x18, 0x03, 0x14, 0x06, 0x07, 0x03, 0x14, 0x40, 0x40, ++ 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x07, 0x40, 0x04, 0x43, 0x57, 0x40, 0x1b, 0x40, 0x44, 0x27, 0x40, 0x43, 0x40, 0x40, 0x40, 0x0f, ++ 0x43, 0x53, 0x53, 0x08, 0x57, 0x53, 0x4f, 0x47, 0x47, 0x07, 0x07, 0x0b, 0x47, 0x04, 0x4f, 0x07, ++ 0x5b, 0x27, 0x04, 0x13, 0x40, 0x4b, 0x13, 0x40, 0x40, 0x40, 0x43, 0x43, 0x4f, 0x53, 0x4f, 0x53, ++ 0x57, 0x53, 0x4f, 0x5b, 0x53, 0x4b, 0x53, 0x5b, 0x5b, 0x57, 0x4f, 0x43, 0x00, 0x43, 0x4f, 0x53, ++ 0x4f, 0x53, 0x57, 0x53, 0x4f, 0x5b, 0x53, 0x4b, 0x53, 0x5b, 0x5b, 0x57, 0x4f, 0x43, 0x00, 0x43, ++ 0x10, 0x4b, 0x00, 0x40, 0x48, 0x40, 0x43, 0x07, 0x43, 0x00, 0x00, 0x4f, 0x07, 0x1b, 0x0f, 0x4b, ++ 0x14, 0x07, 0x40, 0x1b, 0x0f, 0x4b, 0x14, 0x07, 0x40, 0x1b, 0x0f, 0x4b, 0x14, 0x07, 0x40, 0x44, ++ 0x07, 0x00, 0x00, 0x04, 0x10, 0x04, 0x10, 0x13, 0x17, 0x0f, 0x4b, 0x17, 0x0f, 0x4b, 0x40, 0x40, ++ 0x40, 0x23, 0x23, 0x13, 0x40, 0x0f, 0x13, 0x17, 0x17, 0x24, 0x27, 0x14, 0x07, 0x10, 0x14, 0x0c, ++ 0x03, 0x33, 0x1b, 0x13, 0x40, 0x13, 0x0c, 0x17, 0x04, 0x13, 0x08, 0x08, 0x04, 0x13, 0x40, 0x40, ++ 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x07, 0x40, 0x05, 0x43, 0x57, 0x40, 0x1a, 0x40, 0x45, 0x27, 0x40, 0x43, 0x40, 0x40, 0x40, 0x0f, ++ 0x43, 0x52, 0x52, 0x08, 0x56, 0x52, 0x4d, 0x45, 0x45, 0x07, 0x07, 0x0b, 0x47, 0x04, 0x4e, 0x07, ++ 0x5a, 0x27, 0x05, 0x13, 0x40, 0x4b, 0x12, 0x40, 0x40, 0x40, 0x43, 0x43, 0x4f, 0x52, 0x4e, 0x52, ++ 0x56, 0x52, 0x4f, 0x5a, 0x52, 0x4a, 0x52, 0x5a, 0x5a, 0x56, 0x4e, 0x42, 0x00, 0x42, 0x4f, 0x52, ++ 0x4e, 0x52, 0x56, 0x52, 0x4f, 0x5a, 0x52, 0x4a, 0x52, 0x5a, 0x5a, 0x56, 0x4e, 0x42, 0x00, 0x42, ++ 0x10, 0x4b, 0x02, 0x40, 0x48, 0x40, 0x43, 0x07, 0x43, 0x00, 0x00, 0x4d, 0x07, 0x1b, 0x0f, 0x4b, ++ 0x14, 0x07, 0x40, 0x1b, 0x0f, 0x4b, 0x14, 0x07, 0x40, 0x1b, 0x0f, 0x4b, 0x14, 0x07, 0x40, 0x44, ++ 0x07, 0x00, 0x00, 0x05, 0x10, 0x05, 0x10, 0x13, 0x17, 0x0f, 0x4b, 0x17, 0x0f, 0x4b, 0x40, 0x40, ++ 0x40, 0x22, 0x22, 0x13, 0x40, 0x0f, 0x13, 0x17, 0x17, 0x24, 0x27, 0x14, 0x07, 0x10, 0x14, 0x0c, ++ 0x03, 0x32, 0x1b, 0x13, 0x40, 0x13, 0x0c, 0x17, 0x05, 0x13, 0x09, 0x08, 0x05, 0x13, 0x40, 0x40, ++ 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x07, 0x41, 0x06, 0x43, 0x56, 0x40, 0x19, 0x41, 0x46, 0x27, 0x40, 0x43, 0x40, 0x40, 0x40, 0x0f, ++ 0x43, 0x50, 0x51, 0x09, 0x55, 0x50, 0x4b, 0x42, 0x42, 0x07, 0x07, 0x0b, 0x46, 0x04, 0x4d, 0x07, ++ 0x59, 0x27, 0x06, 0x13, 0x40, 0x4b, 0x11, 0x40, 0x40, 0x40, 0x43, 0x43, 0x4e, 0x51, 0x4d, 0x51, ++ 0x55, 0x50, 0x4e, 0x59, 0x51, 0x48, 0x51, 0x59, 0x59, 0x55, 0x4d, 0x41, 0x01, 0x41, 0x4e, 0x51, ++ 0x4d, 0x51, 0x55, 0x50, 0x4e, 0x59, 0x51, 0x48, 0x51, 0x59, 0x59, 0x55, 0x4d, 0x41, 0x01, 0x41, ++ 0x11, 0x4b, 0x04, 0x40, 0x48, 0x40, 0x43, 0x07, 0x43, 0x01, 0x01, 0x4b, 0x07, 0x1b, 0x0e, 0x4b, ++ 0x14, 0x07, 0x40, 0x1b, 0x0e, 0x4b, 0x14, 0x07, 0x40, 0x1b, 0x0e, 0x4b, 0x14, 0x07, 0x40, 0x44, ++ 0x07, 0x01, 0x01, 0x06, 0x11, 0x06, 0x11, 0x13, 0x17, 0x0e, 0x4b, 0x17, 0x0e, 0x4b, 0x40, 0x40, ++ 0x40, 0x21, 0x21, 0x13, 0x40, 0x0f, 0x13, 0x16, 0x16, 0x24, 0x27, 0x14, 0x07, 0x11, 0x14, 0x0c, ++ 0x03, 0x31, 0x1b, 0x13, 0x40, 0x13, 0x0c, 0x16, 0x06, 0x13, 0x0a, 0x09, 0x06, 0x13, 0x40, 0x40, ++ 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x07, 0x42, 0x06, 0x43, 0x56, 0x40, 0x18, 0x42, 0x47, 0x27, 0x40, 0x43, 0x40, 0x40, 0x40, 0x0f, ++ 0x43, 0x4f, 0x51, 0x09, 0x54, 0x4f, 0x4a, 0x40, 0x40, 0x07, 0x07, 0x0a, 0x46, 0x04, 0x4c, 0x07, ++ 0x59, 0x27, 0x06, 0x12, 0x40, 0x4b, 0x10, 0x40, 0x40, 0x40, 0x43, 0x43, 0x4e, 0x51, 0x4c, 0x51, ++ 0x54, 0x4f, 0x4e, 0x59, 0x51, 0x47, 0x51, 0x59, 0x59, 0x54, 0x4c, 0x41, 0x01, 0x41, 0x4e, 0x51, ++ 0x4c, 0x51, 0x54, 0x4f, 0x4e, 0x59, 0x51, 0x47, 0x51, 0x59, 0x59, 0x54, 0x4c, 0x41, 0x01, 0x41, ++ 0x11, 0x4b, 0x05, 0x40, 0x48, 0x40, 0x43, 0x07, 0x43, 0x01, 0x01, 0x4a, 0x07, 0x1a, 0x0d, 0x4b, ++ 0x14, 0x07, 0x40, 0x1a, 0x0d, 0x4b, 0x14, 0x07, 0x40, 0x1a, 0x0d, 0x4b, 0x14, 0x07, 0x40, 0x45, ++ 0x07, 0x01, 0x01, 0x06, 0x11, 0x06, 0x11, 0x12, 0x17, 0x0d, 0x4b, 0x17, 0x0d, 0x4b, 0x40, 0x40, ++ 0x40, 0x20, 0x20, 0x12, 0x40, 0x0f, 0x12, 0x15, 0x15, 0x24, 0x27, 0x14, 0x07, 0x11, 0x14, 0x0c, ++ 0x02, 0x30, 0x1a, 0x12, 0x40, 0x12, 0x0c, 0x15, 0x06, 0x12, 0x0b, 0x09, 0x06, 0x12, 0x40, 0x40, ++ 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x07, 0x42, 0x07, 0x42, 0x55, 0x40, 0x18, 0x42, 0x47, 0x27, 0x40, 0x42, 0x40, 0x40, 0x40, 0x0f, ++ 0x42, 0x4d, 0x50, 0x0a, 0x52, 0x4d, 0x48, 0x02, 0x02, 0x07, 0x07, 0x0a, 0x45, 0x05, 0x4a, 0x07, ++ 0x58, 0x27, 0x07, 0x12, 0x40, 0x4a, 0x10, 0x40, 0x40, 0x40, 0x42, 0x42, 0x4d, 0x50, 0x4a, 0x50, ++ 0x52, 0x4d, 0x4d, 0x58, 0x50, 0x45, 0x50, 0x58, 0x58, 0x52, 0x4a, 0x40, 0x02, 0x40, 0x4d, 0x50, ++ 0x4a, 0x50, 0x52, 0x4d, 0x4d, 0x58, 0x50, 0x45, 0x50, 0x58, 0x58, 0x52, 0x4a, 0x40, 0x02, 0x40, ++ 0x12, 0x4a, 0x07, 0x40, 0x48, 0x40, 0x42, 0x07, 0x42, 0x02, 0x02, 0x48, 0x07, 0x1a, 0x0d, 0x4a, ++ 0x15, 0x07, 0x40, 0x1a, 0x0d, 0x4a, 0x15, 0x07, 0x40, 0x1a, 0x0d, 0x4a, 0x15, 0x07, 0x40, 0x45, ++ 0x07, 0x02, 0x02, 0x07, 0x12, 0x07, 0x12, 0x12, 0x17, 0x0d, 0x4a, 0x17, 0x0d, 0x4a, 0x40, 0x40, ++ 0x40, 0x20, 0x20, 0x12, 0x40, 0x0f, 0x12, 0x15, 0x15, 0x25, 0x27, 0x15, 0x07, 0x12, 0x15, 0x0d, ++ 0x02, 0x30, 0x1a, 0x12, 0x40, 0x12, 0x0d, 0x15, 0x07, 0x12, 0x0d, 0x0a, 0x07, 0x12, 0x40, 0x40, ++ 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x07, 0x43, 0x08, 0x42, 0x54, 0x40, 0x17, 0x43, 0x48, 0x27, 0x40, 0x42, 0x40, 0x40, 0x40, 0x0f, ++ 0x42, 0x4b, 0x4f, 0x0b, 0x51, 0x4b, 0x46, 0x04, 0x04, 0x07, 0x07, 0x0a, 0x44, 0x05, 0x49, 0x07, ++ 0x57, 0x27, 0x08, 0x12, 0x40, 0x4a, 0x0f, 0x40, 0x40, 0x40, 0x42, 0x42, 0x4c, 0x4f, 0x49, 0x4f, ++ 0x51, 0x4b, 0x4c, 0x57, 0x4f, 0x43, 0x4f, 0x57, 0x57, 0x51, 0x49, 0x00, 0x03, 0x00, 0x4c, 0x4f, ++ 0x49, 0x4f, 0x51, 0x4b, 0x4c, 0x57, 0x4f, 0x43, 0x4f, 0x57, 0x57, 0x51, 0x49, 0x00, 0x03, 0x00, ++ 0x13, 0x4a, 0x09, 0x40, 0x48, 0x40, 0x42, 0x07, 0x42, 0x03, 0x03, 0x46, 0x07, 0x1a, 0x0c, 0x4a, ++ 0x15, 0x07, 0x40, 0x1a, 0x0c, 0x4a, 0x15, 0x07, 0x40, 0x1a, 0x0c, 0x4a, 0x15, 0x07, 0x40, 0x45, ++ 0x07, 0x03, 0x03, 0x08, 0x13, 0x08, 0x13, 0x12, 0x17, 0x0c, 0x4a, 0x17, 0x0c, 0x4a, 0x40, 0x40, ++ 0x40, 0x1f, 0x1f, 0x12, 0x40, 0x0f, 0x12, 0x14, 0x14, 0x25, 0x27, 0x15, 0x07, 0x13, 0x15, 0x0d, ++ 0x02, 0x2f, 0x1a, 0x12, 0x40, 0x12, 0x0d, 0x14, 0x08, 0x12, 0x0e, 0x0b, 0x08, 0x12, 0x40, 0x40, ++ 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x07, 0x43, 0x09, 0x42, 0x54, 0x40, 0x16, 0x43, 0x49, 0x27, 0x40, 0x42, 0x40, 0x40, 0x40, 0x0f, ++ 0x42, 0x4a, 0x4e, 0x0b, 0x50, 0x4a, 0x44, 0x07, 0x07, 0x07, 0x07, 0x0a, 0x44, 0x05, 0x48, 0x07, ++ 0x56, 0x27, 0x09, 0x12, 0x40, 0x4a, 0x0e, 0x40, 0x40, 0x40, 0x42, 0x42, 0x4c, 0x4e, 0x48, 0x4e, ++ 0x50, 0x4a, 0x4c, 0x56, 0x4e, 0x42, 0x4e, 0x56, 0x56, 0x50, 0x48, 0x01, 0x03, 0x01, 0x4c, 0x4e, ++ 0x48, 0x4e, 0x50, 0x4a, 0x4c, 0x56, 0x4e, 0x42, 0x4e, 0x56, 0x56, 0x50, 0x48, 0x01, 0x03, 0x01, ++ 0x13, 0x4a, 0x0b, 0x40, 0x48, 0x40, 0x42, 0x07, 0x42, 0x03, 0x03, 0x44, 0x07, 0x1a, 0x0c, 0x4a, ++ 0x15, 0x07, 0x40, 0x1a, 0x0c, 0x4a, 0x15, 0x07, 0x40, 0x1a, 0x0c, 0x4a, 0x15, 0x07, 0x40, 0x45, ++ 0x07, 0x03, 0x03, 0x09, 0x13, 0x09, 0x13, 0x12, 0x17, 0x0c, 0x4a, 0x17, 0x0c, 0x4a, 0x40, 0x40, ++ 0x40, 0x1e, 0x1e, 0x12, 0x40, 0x0f, 0x12, 0x14, 0x14, 0x25, 0x27, 0x15, 0x07, 0x13, 0x15, 0x0d, ++ 0x02, 0x2e, 0x1a, 0x12, 0x40, 0x12, 0x0d, 0x14, 0x09, 0x12, 0x0f, 0x0b, 0x09, 0x12, 0x40, 0x40, ++ 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x07, 0x44, 0x0a, 0x41, 0x53, 0x40, 0x15, 0x44, 0x4a, 0x27, 0x40, 0x41, 0x40, 0x40, 0x40, 0x0f, ++ 0x41, 0x48, 0x4d, 0x0c, 0x4f, 0x48, 0x42, 0x09, 0x09, 0x07, 0x07, 0x09, 0x43, 0x06, 0x47, 0x07, ++ 0x55, 0x27, 0x0a, 0x11, 0x40, 0x49, 0x0d, 0x40, 0x40, 0x40, 0x41, 0x41, 0x4b, 0x4d, 0x47, 0x4d, ++ 0x4f, 0x48, 0x4b, 0x55, 0x4d, 0x40, 0x4d, 0x55, 0x55, 0x4f, 0x47, 0x02, 0x04, 0x02, 0x4b, 0x4d, ++ 0x47, 0x4d, 0x4f, 0x48, 0x4b, 0x55, 0x4d, 0x40, 0x4d, 0x55, 0x55, 0x4f, 0x47, 0x02, 0x04, 0x02, ++ 0x14, 0x49, 0x0d, 0x40, 0x48, 0x40, 0x41, 0x07, 0x41, 0x04, 0x04, 0x42, 0x07, 0x19, 0x0b, 0x49, ++ 0x16, 0x07, 0x40, 0x19, 0x0b, 0x49, 0x16, 0x07, 0x40, 0x19, 0x0b, 0x49, 0x16, 0x07, 0x40, 0x46, ++ 0x07, 0x04, 0x04, 0x0a, 0x14, 0x0a, 0x14, 0x11, 0x17, 0x0b, 0x49, 0x17, 0x0b, 0x49, 0x40, 0x40, ++ 0x40, 0x1d, 0x1d, 0x11, 0x40, 0x0f, 0x11, 0x13, 0x13, 0x26, 0x27, 0x16, 0x07, 0x14, 0x16, 0x0e, ++ 0x01, 0x2d, 0x19, 0x11, 0x40, 0x11, 0x0e, 0x13, 0x0a, 0x11, 0x10, 0x0c, 0x0a, 0x11, 0x40, 0x40, ++ 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x07, 0x45, 0x0b, 0x41, 0x52, 0x40, 0x14, 0x45, 0x4b, 0x27, 0x40, 0x41, 0x40, 0x40, 0x40, 0x0f, ++ 0x41, 0x47, 0x4c, 0x0d, 0x4d, 0x47, 0x40, 0x0c, 0x0c, 0x07, 0x07, 0x09, 0x42, 0x06, 0x45, 0x07, ++ 0x54, 0x27, 0x0b, 0x11, 0x40, 0x49, 0x0c, 0x40, 0x40, 0x40, 0x41, 0x41, 0x4a, 0x4c, 0x45, 0x4c, ++ 0x4d, 0x47, 0x4a, 0x54, 0x4c, 0x00, 0x4c, 0x54, 0x54, 0x4d, 0x45, 0x03, 0x05, 0x03, 0x4a, 0x4c, ++ 0x45, 0x4c, 0x4d, 0x47, 0x4a, 0x54, 0x4c, 0x00, 0x4c, 0x54, 0x54, 0x4d, 0x45, 0x03, 0x05, 0x03, ++ 0x15, 0x49, 0x0f, 0x40, 0x48, 0x40, 0x41, 0x07, 0x41, 0x05, 0x05, 0x40, 0x07, 0x19, 0x0a, 0x49, ++ 0x16, 0x07, 0x40, 0x19, 0x0a, 0x49, 0x16, 0x07, 0x40, 0x19, 0x0a, 0x49, 0x16, 0x07, 0x40, 0x46, ++ 0x07, 0x05, 0x05, 0x0b, 0x15, 0x0b, 0x15, 0x11, 0x17, 0x0a, 0x49, 0x17, 0x0a, 0x49, 0x40, 0x40, ++ 0x40, 0x1c, 0x1c, 0x11, 0x40, 0x0f, 0x11, 0x12, 0x12, 0x26, 0x27, 0x16, 0x07, 0x15, 0x16, 0x0e, ++ 0x01, 0x2c, 0x19, 0x11, 0x40, 0x11, 0x0e, 0x12, 0x0b, 0x11, 0x12, 0x0d, 0x0b, 0x11, 0x40, 0x40, ++ 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x07, 0x45, 0x0c, 0x41, 0x52, 0x40, 0x13, 0x45, 0x4c, 0x27, 0x40, 0x41, 0x40, 0x40, 0x40, 0x0f, ++ 0x41, 0x45, 0x4b, 0x0d, 0x4c, 0x45, 0x01, 0x0e, 0x0e, 0x07, 0x07, 0x09, 0x42, 0x06, 0x44, 0x07, ++ 0x53, 0x27, 0x0c, 0x11, 0x40, 0x49, 0x0b, 0x40, 0x40, 0x40, 0x41, 0x41, 0x4a, 0x4b, 0x44, 0x4b, ++ 0x4c, 0x45, 0x4a, 0x53, 0x4b, 0x02, 0x4b, 0x53, 0x53, 0x4c, 0x44, 0x04, 0x05, 0x04, 0x4a, 0x4b, ++ 0x44, 0x4b, 0x4c, 0x45, 0x4a, 0x53, 0x4b, 0x02, 0x4b, 0x53, 0x53, 0x4c, 0x44, 0x04, 0x05, 0x04, ++ 0x15, 0x49, 0x11, 0x40, 0x48, 0x40, 0x41, 0x07, 0x41, 0x05, 0x05, 0x01, 0x07, 0x19, 0x0a, 0x49, ++ 0x16, 0x07, 0x40, 0x19, 0x0a, 0x49, 0x16, 0x07, 0x40, 0x19, 0x0a, 0x49, 0x16, 0x07, 0x40, 0x46, ++ 0x07, 0x05, 0x05, 0x0c, 0x15, 0x0c, 0x15, 0x11, 0x17, 0x0a, 0x49, 0x17, 0x0a, 0x49, 0x40, 0x40, ++ 0x40, 0x1b, 0x1b, 0x11, 0x40, 0x0f, 0x11, 0x12, 0x12, 0x26, 0x27, 0x16, 0x07, 0x15, 0x16, 0x0e, ++ 0x01, 0x2b, 0x19, 0x11, 0x40, 0x11, 0x0e, 0x12, 0x0c, 0x11, 0x13, 0x0d, 0x0c, 0x11, 0x40, 0x40, ++ 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x07, 0x46, 0x0d, 0x40, 0x51, 0x40, 0x12, 0x46, 0x4d, 0x27, 0x40, 0x40, 0x40, 0x40, 0x40, 0x0f, ++ 0x40, 0x44, 0x4a, 0x0e, 0x4b, 0x44, 0x03, 0x11, 0x11, 0x07, 0x07, 0x08, 0x41, 0x07, 0x43, 0x07, ++ 0x52, 0x27, 0x0d, 0x10, 0x40, 0x48, 0x0a, 0x40, 0x40, 0x40, 0x40, 0x40, 0x49, 0x4a, 0x43, 0x4a, ++ 0x4b, 0x44, 0x49, 0x52, 0x4a, 0x03, 0x4a, 0x52, 0x52, 0x4b, 0x43, 0x05, 0x06, 0x05, 0x49, 0x4a, ++ 0x43, 0x4a, 0x4b, 0x44, 0x49, 0x52, 0x4a, 0x03, 0x4a, 0x52, 0x52, 0x4b, 0x43, 0x05, 0x06, 0x05, ++ 0x16, 0x48, 0x13, 0x40, 0x48, 0x40, 0x40, 0x07, 0x40, 0x06, 0x06, 0x03, 0x07, 0x18, 0x09, 0x48, ++ 0x17, 0x07, 0x40, 0x18, 0x09, 0x48, 0x17, 0x07, 0x40, 0x18, 0x09, 0x48, 0x17, 0x07, 0x40, 0x47, ++ 0x07, 0x06, 0x06, 0x0d, 0x16, 0x0d, 0x16, 0x10, 0x17, 0x09, 0x48, 0x17, 0x09, 0x48, 0x40, 0x40, ++ 0x40, 0x1a, 0x1a, 0x10, 0x40, 0x0f, 0x10, 0x11, 0x11, 0x27, 0x27, 0x17, 0x07, 0x16, 0x17, 0x0f, ++ 0x00, 0x2a, 0x18, 0x10, 0x40, 0x10, 0x0f, 0x11, 0x0d, 0x10, 0x14, 0x0e, 0x0d, 0x10, 0x40, 0x40, ++ 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x07, 0x47, 0x0e, 0x40, 0x51, 0x40, 0x11, 0x47, 0x4e, 0x27, 0x40, 0x40, 0x40, 0x40, 0x40, 0x0f, ++ 0x40, 0x42, 0x49, 0x0e, 0x4a, 0x42, 0x04, 0x13, 0x13, 0x07, 0x07, 0x08, 0x41, 0x07, 0x42, 0x07, ++ 0x51, 0x27, 0x0e, 0x10, 0x40, 0x48, 0x09, 0x40, 0x40, 0x40, 0x40, 0x40, 0x49, 0x49, 0x42, 0x49, ++ 0x4a, 0x42, 0x49, 0x51, 0x49, 0x05, 0x49, 0x51, 0x51, 0x4a, 0x42, 0x06, 0x06, 0x06, 0x49, 0x49, ++ 0x42, 0x49, 0x4a, 0x42, 0x49, 0x51, 0x49, 0x05, 0x49, 0x51, 0x51, 0x4a, 0x42, 0x06, 0x06, 0x06, ++ 0x16, 0x48, 0x14, 0x40, 0x48, 0x40, 0x40, 0x07, 0x40, 0x06, 0x06, 0x04, 0x07, 0x18, 0x08, 0x48, ++ 0x17, 0x07, 0x40, 0x18, 0x08, 0x48, 0x17, 0x07, 0x40, 0x18, 0x08, 0x48, 0x17, 0x07, 0x40, 0x47, ++ 0x07, 0x06, 0x06, 0x0e, 0x16, 0x0e, 0x16, 0x10, 0x17, 0x08, 0x48, 0x17, 0x08, 0x48, 0x40, 0x40, ++ 0x40, 0x19, 0x19, 0x10, 0x40, 0x0f, 0x10, 0x10, 0x10, 0x27, 0x27, 0x17, 0x07, 0x16, 0x17, 0x0f, ++ 0x00, 0x29, 0x18, 0x10, 0x40, 0x10, 0x0f, 0x10, 0x0e, 0x10, 0x15, 0x0e, 0x0e, 0x10, 0x40, 0x40, ++ 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x07, 0x47, 0x0f, 0x40, 0x50, 0x40, 0x10, 0x47, 0x4f, 0x27, 0x40, 0x40, 0x40, 0x40, 0x40, 0x0f, ++ 0x40, 0x40, 0x48, 0x0f, 0x48, 0x40, 0x06, 0x16, 0x16, 0x07, 0x07, 0x08, 0x40, 0x07, 0x40, 0x07, ++ 0x50, 0x27, 0x0f, 0x10, 0x40, 0x48, 0x08, 0x40, 0x40, 0x40, 0x40, 0x40, 0x48, 0x48, 0x40, 0x48, ++ 0x48, 0x40, 0x48, 0x50, 0x48, 0x07, 0x48, 0x50, 0x50, 0x48, 0x40, 0x07, 0x07, 0x07, 0x48, 0x48, ++ 0x40, 0x48, 0x48, 0x40, 0x48, 0x50, 0x48, 0x07, 0x48, 0x50, 0x50, 0x48, 0x40, 0x07, 0x07, 0x07, ++ 0x17, 0x48, 0x16, 0x40, 0x48, 0x40, 0x40, 0x07, 0x40, 0x07, 0x07, 0x06, 0x07, 0x18, 0x08, 0x48, ++ 0x17, 0x07, 0x40, 0x18, 0x08, 0x48, 0x17, 0x07, 0x40, 0x18, 0x08, 0x48, 0x17, 0x07, 0x40, 0x47, ++ 0x07, 0x07, 0x07, 0x0f, 0x17, 0x0f, 0x17, 0x10, 0x17, 0x08, 0x48, 0x17, 0x08, 0x48, 0x40, 0x40, ++ 0x40, 0x18, 0x18, 0x10, 0x40, 0x0f, 0x10, 0x10, 0x10, 0x27, 0x27, 0x17, 0x07, 0x17, 0x17, 0x0f, ++ 0x00, 0x28, 0x18, 0x10, 0x40, 0x10, 0x0f, 0x10, 0x0f, 0x10, 0x17, 0x0f, 0x0f, 0x10, 0x40, 0x40, ++ 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x07, 0x48, 0x10, 0x00, 0x4f, 0x40, 0x0f, 0x48, 0x50, 0x27, 0x40, 0x00, 0x40, 0x40, 0x40, 0x0f, ++ 0x00, 0x00, 0x47, 0x10, 0x47, 0x00, 0x08, 0x18, 0x18, 0x07, 0x07, 0x07, 0x00, 0x08, 0x00, 0x07, ++ 0x4f, 0x27, 0x10, 0x0f, 0x40, 0x47, 0x07, 0x40, 0x40, 0x40, 0x00, 0x00, 0x47, 0x47, 0x00, 0x47, ++ 0x47, 0x00, 0x47, 0x4f, 0x47, 0x08, 0x47, 0x4f, 0x4f, 0x47, 0x00, 0x08, 0x08, 0x08, 0x47, 0x47, ++ 0x00, 0x47, 0x47, 0x00, 0x47, 0x4f, 0x47, 0x08, 0x47, 0x4f, 0x4f, 0x47, 0x00, 0x08, 0x08, 0x08, ++ 0x18, 0x47, 0x18, 0x40, 0x48, 0x40, 0x00, 0x07, 0x00, 0x08, 0x08, 0x08, 0x07, 0x17, 0x07, 0x47, ++ 0x18, 0x07, 0x40, 0x17, 0x07, 0x47, 0x18, 0x07, 0x40, 0x17, 0x07, 0x47, 0x18, 0x07, 0x40, 0x48, ++ 0x07, 0x08, 0x08, 0x10, 0x18, 0x10, 0x18, 0x0f, 0x17, 0x07, 0x47, 0x17, 0x07, 0x47, 0x40, 0x40, ++ 0x40, 0x17, 0x17, 0x0f, 0x40, 0x0f, 0x0f, 0x0f, 0x0f, 0x28, 0x27, 0x18, 0x07, 0x18, 0x18, 0x10, ++ 0x40, 0x27, 0x17, 0x0f, 0x40, 0x0f, 0x10, 0x0f, 0x10, 0x0f, 0x18, 0x10, 0x10, 0x0f, 0x40, 0x40, ++ 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x07, 0x48, 0x11, 0x00, 0x4f, 0x40, 0x0e, 0x48, 0x51, 0x27, 0x40, 0x00, 0x40, 0x40, 0x40, 0x0f, ++ 0x00, 0x02, 0x46, 0x10, 0x46, 0x02, 0x0a, 0x1b, 0x1b, 0x07, 0x07, 0x07, 0x00, 0x08, 0x01, 0x07, ++ 0x4e, 0x27, 0x11, 0x0f, 0x40, 0x47, 0x06, 0x40, 0x40, 0x40, 0x00, 0x00, 0x47, 0x46, 0x01, 0x46, ++ 0x46, 0x02, 0x47, 0x4e, 0x46, 0x0a, 0x46, 0x4e, 0x4e, 0x46, 0x01, 0x09, 0x08, 0x09, 0x47, 0x46, ++ 0x01, 0x46, 0x46, 0x02, 0x47, 0x4e, 0x46, 0x0a, 0x46, 0x4e, 0x4e, 0x46, 0x01, 0x09, 0x08, 0x09, ++ 0x18, 0x47, 0x1a, 0x40, 0x48, 0x40, 0x00, 0x07, 0x00, 0x08, 0x08, 0x0a, 0x07, 0x17, 0x07, 0x47, ++ 0x18, 0x07, 0x40, 0x17, 0x07, 0x47, 0x18, 0x07, 0x40, 0x17, 0x07, 0x47, 0x18, 0x07, 0x40, 0x48, ++ 0x07, 0x08, 0x08, 0x11, 0x18, 0x11, 0x18, 0x0f, 0x17, 0x07, 0x47, 0x17, 0x07, 0x47, 0x40, 0x40, ++ 0x40, 0x16, 0x16, 0x0f, 0x40, 0x0f, 0x0f, 0x0f, 0x0f, 0x28, 0x27, 0x18, 0x07, 0x18, 0x18, 0x10, ++ 0x40, 0x26, 0x17, 0x0f, 0x40, 0x0f, 0x10, 0x0f, 0x11, 0x0f, 0x19, 0x10, 0x11, 0x0f, 0x40, 0x40, ++ 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x07, 0x49, 0x12, 0x00, 0x4e, 0x40, 0x0d, 0x49, 0x52, 0x27, 0x40, 0x00, 0x40, 0x40, 0x40, 0x0f, ++ 0x00, 0x03, 0x45, 0x11, 0x45, 0x03, 0x0c, 0x1d, 0x1d, 0x07, 0x07, 0x07, 0x01, 0x08, 0x02, 0x07, ++ 0x4d, 0x27, 0x12, 0x0f, 0x40, 0x47, 0x05, 0x40, 0x40, 0x40, 0x00, 0x00, 0x46, 0x45, 0x02, 0x45, ++ 0x45, 0x03, 0x46, 0x4d, 0x45, 0x0b, 0x45, 0x4d, 0x4d, 0x45, 0x02, 0x0a, 0x09, 0x0a, 0x46, 0x45, ++ 0x02, 0x45, 0x45, 0x03, 0x46, 0x4d, 0x45, 0x0b, 0x45, 0x4d, 0x4d, 0x45, 0x02, 0x0a, 0x09, 0x0a, ++ 0x19, 0x47, 0x1c, 0x40, 0x48, 0x40, 0x00, 0x07, 0x00, 0x09, 0x09, 0x0c, 0x07, 0x17, 0x06, 0x47, ++ 0x18, 0x07, 0x40, 0x17, 0x06, 0x47, 0x18, 0x07, 0x40, 0x17, 0x06, 0x47, 0x18, 0x07, 0x40, 0x48, ++ 0x07, 0x09, 0x09, 0x12, 0x19, 0x12, 0x19, 0x0f, 0x17, 0x06, 0x47, 0x17, 0x06, 0x47, 0x40, 0x40, ++ 0x40, 0x15, 0x15, 0x0f, 0x40, 0x0f, 0x0f, 0x0e, 0x0e, 0x28, 0x27, 0x18, 0x07, 0x19, 0x18, 0x10, ++ 0x40, 0x25, 0x17, 0x0f, 0x40, 0x0f, 0x10, 0x0e, 0x12, 0x0f, 0x1a, 0x11, 0x12, 0x0f, 0x40, 0x40, ++ 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x07, 0x4a, 0x13, 0x01, 0x4d, 0x40, 0x0c, 0x4a, 0x53, 0x27, 0x40, 0x01, 0x40, 0x40, 0x40, 0x0f, ++ 0x01, 0x05, 0x44, 0x12, 0x43, 0x05, 0x0e, 0x20, 0x20, 0x07, 0x07, 0x06, 0x02, 0x09, 0x04, 0x07, ++ 0x4c, 0x27, 0x13, 0x0e, 0x40, 0x46, 0x04, 0x40, 0x40, 0x40, 0x01, 0x01, 0x45, 0x44, 0x04, 0x44, ++ 0x43, 0x05, 0x45, 0x4c, 0x44, 0x0d, 0x44, 0x4c, 0x4c, 0x43, 0x04, 0x0b, 0x0a, 0x0b, 0x45, 0x44, ++ 0x04, 0x44, 0x43, 0x05, 0x45, 0x4c, 0x44, 0x0d, 0x44, 0x4c, 0x4c, 0x43, 0x04, 0x0b, 0x0a, 0x0b, ++ 0x1a, 0x46, 0x1e, 0x40, 0x48, 0x40, 0x01, 0x07, 0x01, 0x0a, 0x0a, 0x0e, 0x07, 0x16, 0x05, 0x46, ++ 0x19, 0x07, 0x40, 0x16, 0x05, 0x46, 0x19, 0x07, 0x40, 0x16, 0x05, 0x46, 0x19, 0x07, 0x40, 0x49, ++ 0x07, 0x0a, 0x0a, 0x13, 0x1a, 0x13, 0x1a, 0x0e, 0x17, 0x05, 0x46, 0x17, 0x05, 0x46, 0x40, 0x40, ++ 0x40, 0x14, 0x14, 0x0e, 0x40, 0x0f, 0x0e, 0x0d, 0x0d, 0x29, 0x27, 0x19, 0x07, 0x1a, 0x19, 0x11, ++ 0x41, 0x24, 0x16, 0x0e, 0x40, 0x0e, 0x11, 0x0d, 0x13, 0x0e, 0x1c, 0x12, 0x13, 0x0e, 0x40, 0x40, ++ 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x07, 0x4a, 0x14, 0x01, 0x4d, 0x40, 0x0b, 0x4a, 0x54, 0x27, 0x40, 0x01, 0x40, 0x40, 0x40, 0x0f, ++ 0x01, 0x06, 0x43, 0x12, 0x42, 0x06, 0x10, 0x22, 0x22, 0x07, 0x07, 0x06, 0x02, 0x09, 0x05, 0x07, ++ 0x4b, 0x27, 0x14, 0x0e, 0x40, 0x46, 0x03, 0x40, 0x40, 0x40, 0x01, 0x01, 0x45, 0x43, 0x05, 0x43, ++ 0x42, 0x06, 0x45, 0x4b, 0x43, 0x0e, 0x43, 0x4b, 0x4b, 0x42, 0x05, 0x0c, 0x0a, 0x0c, 0x45, 0x43, ++ 0x05, 0x43, 0x42, 0x06, 0x45, 0x4b, 0x43, 0x0e, 0x43, 0x4b, 0x4b, 0x42, 0x05, 0x0c, 0x0a, 0x0c, ++ 0x1a, 0x46, 0x20, 0x40, 0x48, 0x40, 0x01, 0x07, 0x01, 0x0a, 0x0a, 0x10, 0x07, 0x16, 0x05, 0x46, ++ 0x19, 0x07, 0x40, 0x16, 0x05, 0x46, 0x19, 0x07, 0x40, 0x16, 0x05, 0x46, 0x19, 0x07, 0x40, 0x49, ++ 0x07, 0x0a, 0x0a, 0x14, 0x1a, 0x14, 0x1a, 0x0e, 0x17, 0x05, 0x46, 0x17, 0x05, 0x46, 0x40, 0x40, ++ 0x40, 0x13, 0x13, 0x0e, 0x40, 0x0f, 0x0e, 0x0d, 0x0d, 0x29, 0x27, 0x19, 0x07, 0x1a, 0x19, 0x11, ++ 0x41, 0x23, 0x16, 0x0e, 0x40, 0x0e, 0x11, 0x0d, 0x14, 0x0e, 0x1d, 0x12, 0x14, 0x0e, 0x40, 0x40, ++ 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x07, 0x4b, 0x15, 0x01, 0x4c, 0x40, 0x0a, 0x4b, 0x55, 0x27, 0x40, 0x01, 0x40, 0x40, 0x40, 0x0f, ++ 0x01, 0x08, 0x42, 0x13, 0x41, 0x08, 0x12, 0x25, 0x25, 0x07, 0x07, 0x06, 0x03, 0x09, 0x06, 0x07, ++ 0x4a, 0x27, 0x15, 0x0e, 0x40, 0x46, 0x02, 0x40, 0x40, 0x40, 0x01, 0x01, 0x44, 0x42, 0x06, 0x42, ++ 0x41, 0x08, 0x44, 0x4a, 0x42, 0x10, 0x42, 0x4a, 0x4a, 0x41, 0x06, 0x0d, 0x0b, 0x0d, 0x44, 0x42, ++ 0x06, 0x42, 0x41, 0x08, 0x44, 0x4a, 0x42, 0x10, 0x42, 0x4a, 0x4a, 0x41, 0x06, 0x0d, 0x0b, 0x0d, ++ 0x1b, 0x46, 0x22, 0x40, 0x48, 0x40, 0x01, 0x07, 0x01, 0x0b, 0x0b, 0x12, 0x07, 0x16, 0x04, 0x46, ++ 0x19, 0x07, 0x40, 0x16, 0x04, 0x46, 0x19, 0x07, 0x40, 0x16, 0x04, 0x46, 0x19, 0x07, 0x40, 0x49, ++ 0x07, 0x0b, 0x0b, 0x15, 0x1b, 0x15, 0x1b, 0x0e, 0x17, 0x04, 0x46, 0x17, 0x04, 0x46, 0x40, 0x40, ++ 0x40, 0x12, 0x12, 0x0e, 0x40, 0x0f, 0x0e, 0x0c, 0x0c, 0x29, 0x27, 0x19, 0x07, 0x1b, 0x19, 0x11, ++ 0x41, 0x22, 0x16, 0x0e, 0x40, 0x0e, 0x11, 0x0c, 0x15, 0x0e, 0x1e, 0x13, 0x15, 0x0e, 0x40, 0x40, ++ 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x07, 0x4c, 0x15, 0x01, 0x4c, 0x40, 0x09, 0x4c, 0x56, 0x27, 0x40, 0x01, 0x40, 0x40, 0x40, 0x0f, ++ 0x01, 0x09, 0x42, 0x13, 0x40, 0x09, 0x13, 0x27, 0x27, 0x07, 0x07, 0x05, 0x03, 0x09, 0x07, 0x07, ++ 0x4a, 0x27, 0x15, 0x0d, 0x40, 0x46, 0x01, 0x40, 0x40, 0x40, 0x01, 0x01, 0x44, 0x42, 0x07, 0x42, ++ 0x40, 0x09, 0x44, 0x4a, 0x42, 0x11, 0x42, 0x4a, 0x4a, 0x40, 0x07, 0x0d, 0x0b, 0x0d, 0x44, 0x42, ++ 0x07, 0x42, 0x40, 0x09, 0x44, 0x4a, 0x42, 0x11, 0x42, 0x4a, 0x4a, 0x40, 0x07, 0x0d, 0x0b, 0x0d, ++ 0x1b, 0x46, 0x23, 0x40, 0x48, 0x40, 0x01, 0x07, 0x01, 0x0b, 0x0b, 0x13, 0x07, 0x15, 0x03, 0x46, ++ 0x19, 0x07, 0x40, 0x15, 0x03, 0x46, 0x19, 0x07, 0x40, 0x15, 0x03, 0x46, 0x19, 0x07, 0x40, 0x4a, ++ 0x07, 0x0b, 0x0b, 0x15, 0x1b, 0x15, 0x1b, 0x0d, 0x17, 0x03, 0x46, 0x17, 0x03, 0x46, 0x40, 0x40, ++ 0x40, 0x11, 0x11, 0x0d, 0x40, 0x0f, 0x0d, 0x0b, 0x0b, 0x29, 0x27, 0x19, 0x07, 0x1b, 0x19, 0x11, ++ 0x42, 0x21, 0x15, 0x0d, 0x40, 0x0d, 0x11, 0x0b, 0x15, 0x0d, 0x1f, 0x13, 0x15, 0x0d, 0x40, 0x40, ++ 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x07, 0x4c, 0x16, 0x02, 0x4b, 0x40, 0x09, 0x4c, 0x56, 0x27, 0x40, 0x02, 0x40, 0x40, 0x40, 0x0f, ++ 0x02, 0x0b, 0x41, 0x14, 0x01, 0x0b, 0x15, 0x2a, 0x2a, 0x07, 0x07, 0x05, 0x04, 0x0a, 0x09, 0x07, ++ 0x49, 0x27, 0x16, 0x0d, 0x40, 0x45, 0x01, 0x40, 0x40, 0x40, 0x02, 0x02, 0x43, 0x41, 0x09, 0x41, ++ 0x01, 0x0b, 0x43, 0x49, 0x41, 0x13, 0x41, 0x49, 0x49, 0x01, 0x09, 0x0e, 0x0c, 0x0e, 0x43, 0x41, ++ 0x09, 0x41, 0x01, 0x0b, 0x43, 0x49, 0x41, 0x13, 0x41, 0x49, 0x49, 0x01, 0x09, 0x0e, 0x0c, 0x0e, ++ 0x1c, 0x45, 0x25, 0x40, 0x48, 0x40, 0x02, 0x07, 0x02, 0x0c, 0x0c, 0x15, 0x07, 0x15, 0x03, 0x45, ++ 0x1a, 0x07, 0x40, 0x15, 0x03, 0x45, 0x1a, 0x07, 0x40, 0x15, 0x03, 0x45, 0x1a, 0x07, 0x40, 0x4a, ++ 0x07, 0x0c, 0x0c, 0x16, 0x1c, 0x16, 0x1c, 0x0d, 0x17, 0x03, 0x45, 0x17, 0x03, 0x45, 0x40, 0x40, ++ 0x40, 0x11, 0x11, 0x0d, 0x40, 0x0f, 0x0d, 0x0b, 0x0b, 0x2a, 0x27, 0x1a, 0x07, 0x1c, 0x1a, 0x12, ++ 0x42, 0x21, 0x15, 0x0d, 0x40, 0x0d, 0x12, 0x0b, 0x16, 0x0d, 0x21, 0x14, 0x16, 0x0d, 0x40, 0x40, ++ 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x07, 0x4d, 0x17, 0x02, 0x4a, 0x40, 0x08, 0x4d, 0x57, 0x27, 0x40, 0x02, 0x40, 0x40, 0x40, 0x0f, ++ 0x02, 0x0d, 0x40, 0x15, 0x02, 0x0d, 0x17, 0x2c, 0x2c, 0x07, 0x07, 0x05, 0x05, 0x0a, 0x0a, 0x07, ++ 0x48, 0x27, 0x17, 0x0d, 0x40, 0x45, 0x00, 0x40, 0x40, 0x40, 0x02, 0x02, 0x42, 0x40, 0x0a, 0x40, ++ 0x02, 0x0d, 0x42, 0x48, 0x40, 0x15, 0x40, 0x48, 0x48, 0x02, 0x0a, 0x0f, 0x0d, 0x0f, 0x42, 0x40, ++ 0x0a, 0x40, 0x02, 0x0d, 0x42, 0x48, 0x40, 0x15, 0x40, 0x48, 0x48, 0x02, 0x0a, 0x0f, 0x0d, 0x0f, ++ 0x1d, 0x45, 0x27, 0x40, 0x48, 0x40, 0x02, 0x07, 0x02, 0x0d, 0x0d, 0x17, 0x07, 0x15, 0x02, 0x45, ++ 0x1a, 0x07, 0x40, 0x15, 0x02, 0x45, 0x1a, 0x07, 0x40, 0x15, 0x02, 0x45, 0x1a, 0x07, 0x40, 0x4a, ++ 0x07, 0x0d, 0x0d, 0x17, 0x1d, 0x17, 0x1d, 0x0d, 0x17, 0x02, 0x45, 0x17, 0x02, 0x45, 0x40, 0x40, ++ 0x40, 0x10, 0x10, 0x0d, 0x40, 0x0f, 0x0d, 0x0a, 0x0a, 0x2a, 0x27, 0x1a, 0x07, 0x1d, 0x1a, 0x12, ++ 0x42, 0x20, 0x15, 0x0d, 0x40, 0x0d, 0x12, 0x0a, 0x17, 0x0d, 0x22, 0x15, 0x17, 0x0d, 0x40, 0x40, ++ 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x07, 0x4d, 0x18, 0x02, 0x4a, 0x40, 0x07, 0x4d, 0x58, 0x27, 0x40, 0x02, 0x40, 0x40, 0x40, 0x0f, ++ 0x02, 0x0e, 0x00, 0x15, 0x03, 0x0e, 0x19, 0x2f, 0x2f, 0x07, 0x07, 0x05, 0x05, 0x0a, 0x0b, 0x07, ++ 0x47, 0x27, 0x18, 0x0d, 0x40, 0x45, 0x40, 0x40, 0x40, 0x40, 0x02, 0x02, 0x42, 0x00, 0x0b, 0x00, ++ 0x03, 0x0e, 0x42, 0x47, 0x00, 0x16, 0x00, 0x47, 0x47, 0x03, 0x0b, 0x10, 0x0d, 0x10, 0x42, 0x00, ++ 0x0b, 0x00, 0x03, 0x0e, 0x42, 0x47, 0x00, 0x16, 0x00, 0x47, 0x47, 0x03, 0x0b, 0x10, 0x0d, 0x10, ++ 0x1d, 0x45, 0x29, 0x40, 0x48, 0x40, 0x02, 0x07, 0x02, 0x0d, 0x0d, 0x19, 0x07, 0x15, 0x02, 0x45, ++ 0x1a, 0x07, 0x40, 0x15, 0x02, 0x45, 0x1a, 0x07, 0x40, 0x15, 0x02, 0x45, 0x1a, 0x07, 0x40, 0x4a, ++ 0x07, 0x0d, 0x0d, 0x18, 0x1d, 0x18, 0x1d, 0x0d, 0x17, 0x02, 0x45, 0x17, 0x02, 0x45, 0x40, 0x40, ++ 0x40, 0x0f, 0x0f, 0x0d, 0x40, 0x0f, 0x0d, 0x0a, 0x0a, 0x2a, 0x27, 0x1a, 0x07, 0x1d, 0x1a, 0x12, ++ 0x42, 0x1f, 0x15, 0x0d, 0x40, 0x0d, 0x12, 0x0a, 0x18, 0x0d, 0x23, 0x15, 0x18, 0x0d, 0x40, 0x40, ++ 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x07, 0x4e, 0x19, 0x03, 0x49, 0x40, 0x06, 0x4e, 0x59, 0x27, 0x40, 0x03, 0x40, 0x40, 0x40, 0x0f, ++ 0x03, 0x10, 0x01, 0x16, 0x04, 0x10, 0x1b, 0x31, 0x31, 0x07, 0x07, 0x04, 0x06, 0x0b, 0x0c, 0x07, ++ 0x46, 0x27, 0x19, 0x0c, 0x40, 0x44, 0x41, 0x40, 0x40, 0x40, 0x03, 0x03, 0x41, 0x01, 0x0c, 0x01, ++ 0x04, 0x10, 0x41, 0x46, 0x01, 0x18, 0x01, 0x46, 0x46, 0x04, 0x0c, 0x11, 0x0e, 0x11, 0x41, 0x01, ++ 0x0c, 0x01, 0x04, 0x10, 0x41, 0x46, 0x01, 0x18, 0x01, 0x46, 0x46, 0x04, 0x0c, 0x11, 0x0e, 0x11, ++ 0x1e, 0x44, 0x2b, 0x40, 0x48, 0x40, 0x03, 0x07, 0x03, 0x0e, 0x0e, 0x1b, 0x07, 0x14, 0x01, 0x44, ++ 0x1b, 0x07, 0x40, 0x14, 0x01, 0x44, 0x1b, 0x07, 0x40, 0x14, 0x01, 0x44, 0x1b, 0x07, 0x40, 0x4b, ++ 0x07, 0x0e, 0x0e, 0x19, 0x1e, 0x19, 0x1e, 0x0c, 0x17, 0x01, 0x44, 0x17, 0x01, 0x44, 0x40, 0x40, ++ 0x40, 0x0e, 0x0e, 0x0c, 0x40, 0x0f, 0x0c, 0x09, 0x09, 0x2b, 0x27, 0x1b, 0x07, 0x1e, 0x1b, 0x13, ++ 0x43, 0x1e, 0x14, 0x0c, 0x40, 0x0c, 0x13, 0x09, 0x19, 0x0c, 0x24, 0x16, 0x19, 0x0c, 0x40, 0x40, ++ 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x07, 0x4f, 0x1a, 0x03, 0x48, 0x40, 0x05, 0x4f, 0x5a, 0x27, 0x40, 0x03, 0x40, 0x40, 0x40, 0x0f, ++ 0x03, 0x11, 0x02, 0x17, 0x06, 0x11, 0x1d, 0x34, 0x34, 0x07, 0x07, 0x04, 0x07, 0x0b, 0x0e, 0x07, ++ 0x45, 0x27, 0x1a, 0x0c, 0x40, 0x44, 0x42, 0x40, 0x40, 0x40, 0x03, 0x03, 0x40, 0x02, 0x0e, 0x02, ++ 0x06, 0x11, 0x40, 0x45, 0x02, 0x19, 0x02, 0x45, 0x45, 0x06, 0x0e, 0x12, 0x0f, 0x12, 0x40, 0x02, ++ 0x0e, 0x02, 0x06, 0x11, 0x40, 0x45, 0x02, 0x19, 0x02, 0x45, 0x45, 0x06, 0x0e, 0x12, 0x0f, 0x12, ++ 0x1f, 0x44, 0x2d, 0x40, 0x48, 0x40, 0x03, 0x07, 0x03, 0x0f, 0x0f, 0x1d, 0x07, 0x14, 0x00, 0x44, ++ 0x1b, 0x07, 0x40, 0x14, 0x00, 0x44, 0x1b, 0x07, 0x40, 0x14, 0x00, 0x44, 0x1b, 0x07, 0x40, 0x4b, ++ 0x07, 0x0f, 0x0f, 0x1a, 0x1f, 0x1a, 0x1f, 0x0c, 0x17, 0x00, 0x44, 0x17, 0x00, 0x44, 0x40, 0x40, ++ 0x40, 0x0d, 0x0d, 0x0c, 0x40, 0x0f, 0x0c, 0x08, 0x08, 0x2b, 0x27, 0x1b, 0x07, 0x1f, 0x1b, 0x13, ++ 0x43, 0x1d, 0x14, 0x0c, 0x40, 0x0c, 0x13, 0x08, 0x1a, 0x0c, 0x26, 0x17, 0x1a, 0x0c, 0x40, 0x40, ++ 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x07, 0x4f, 0x1b, 0x03, 0x48, 0x40, 0x04, 0x4f, 0x5b, 0x27, 0x40, 0x03, 0x40, 0x40, 0x40, 0x0f, ++ 0x03, 0x13, 0x03, 0x17, 0x07, 0x13, 0x1f, 0x36, 0x36, 0x07, 0x07, 0x04, 0x07, 0x0b, 0x0f, 0x07, ++ 0x44, 0x27, 0x1b, 0x0c, 0x40, 0x44, 0x43, 0x40, 0x40, 0x40, 0x03, 0x03, 0x40, 0x03, 0x0f, 0x03, ++ 0x07, 0x13, 0x40, 0x44, 0x03, 0x1b, 0x03, 0x44, 0x44, 0x07, 0x0f, 0x13, 0x0f, 0x13, 0x40, 0x03, ++ 0x0f, 0x03, 0x07, 0x13, 0x40, 0x44, 0x03, 0x1b, 0x03, 0x44, 0x44, 0x07, 0x0f, 0x13, 0x0f, 0x13, ++ 0x1f, 0x44, 0x2f, 0x40, 0x48, 0x40, 0x03, 0x07, 0x03, 0x0f, 0x0f, 0x1f, 0x07, 0x14, 0x00, 0x44, ++ 0x1b, 0x07, 0x40, 0x14, 0x00, 0x44, 0x1b, 0x07, 0x40, 0x14, 0x00, 0x44, 0x1b, 0x07, 0x40, 0x4b, ++ 0x07, 0x0f, 0x0f, 0x1b, 0x1f, 0x1b, 0x1f, 0x0c, 0x17, 0x00, 0x44, 0x17, 0x00, 0x44, 0x40, 0x40, ++ 0x40, 0x0c, 0x0c, 0x0c, 0x40, 0x0f, 0x0c, 0x08, 0x08, 0x2b, 0x27, 0x1b, 0x07, 0x1f, 0x1b, 0x13, ++ 0x43, 0x1c, 0x14, 0x0c, 0x40, 0x0c, 0x13, 0x08, 0x1b, 0x0c, 0x27, 0x17, 0x1b, 0x0c, 0x40, 0x40, ++ 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x07, 0x50, 0x1c, 0x04, 0x47, 0x40, 0x03, 0x50, 0x5c, 0x27, 0x40, 0x04, 0x40, 0x40, 0x40, 0x0f, ++ 0x04, 0x14, 0x04, 0x18, 0x08, 0x14, 0x21, 0x39, 0x39, 0x07, 0x07, 0x03, 0x08, 0x0c, 0x10, 0x07, ++ 0x43, 0x27, 0x1c, 0x0b, 0x40, 0x43, 0x44, 0x40, 0x40, 0x40, 0x04, 0x04, 0x00, 0x04, 0x10, 0x04, ++ 0x08, 0x14, 0x00, 0x43, 0x04, 0x1c, 0x04, 0x43, 0x43, 0x08, 0x10, 0x14, 0x10, 0x14, 0x00, 0x04, ++ 0x10, 0x04, 0x08, 0x14, 0x00, 0x43, 0x04, 0x1c, 0x04, 0x43, 0x43, 0x08, 0x10, 0x14, 0x10, 0x14, ++ 0x20, 0x43, 0x31, 0x40, 0x48, 0x40, 0x04, 0x07, 0x04, 0x10, 0x10, 0x21, 0x07, 0x13, 0x40, 0x43, ++ 0x1c, 0x07, 0x40, 0x13, 0x40, 0x43, 0x1c, 0x07, 0x40, 0x13, 0x40, 0x43, 0x1c, 0x07, 0x40, 0x4c, ++ 0x07, 0x10, 0x10, 0x1c, 0x20, 0x1c, 0x20, 0x0b, 0x17, 0x40, 0x43, 0x17, 0x40, 0x43, 0x40, 0x40, ++ 0x40, 0x0b, 0x0b, 0x0b, 0x40, 0x0f, 0x0b, 0x07, 0x07, 0x2c, 0x27, 0x1c, 0x07, 0x20, 0x1c, 0x14, ++ 0x44, 0x1b, 0x13, 0x0b, 0x40, 0x0b, 0x14, 0x07, 0x1c, 0x0b, 0x28, 0x18, 0x1c, 0x0b, 0x40, 0x40, ++ 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x07, 0x51, 0x1d, 0x04, 0x47, 0x40, 0x02, 0x51, 0x5d, 0x27, 0x40, 0x04, 0x40, 0x40, 0x40, 0x0f, ++ 0x04, 0x16, 0x05, 0x18, 0x09, 0x16, 0x22, 0x3b, 0x3b, 0x07, 0x07, 0x03, 0x08, 0x0c, 0x11, 0x07, ++ 0x42, 0x27, 0x1d, 0x0b, 0x40, 0x43, 0x45, 0x40, 0x40, 0x40, 0x04, 0x04, 0x00, 0x05, 0x11, 0x05, ++ 0x09, 0x16, 0x00, 0x42, 0x05, 0x1e, 0x05, 0x42, 0x42, 0x09, 0x11, 0x15, 0x10, 0x15, 0x00, 0x05, ++ 0x11, 0x05, 0x09, 0x16, 0x00, 0x42, 0x05, 0x1e, 0x05, 0x42, 0x42, 0x09, 0x11, 0x15, 0x10, 0x15, ++ 0x20, 0x43, 0x32, 0x40, 0x48, 0x40, 0x04, 0x07, 0x04, 0x10, 0x10, 0x22, 0x07, 0x13, 0x41, 0x43, ++ 0x1c, 0x07, 0x40, 0x13, 0x41, 0x43, 0x1c, 0x07, 0x40, 0x13, 0x41, 0x43, 0x1c, 0x07, 0x40, 0x4c, ++ 0x07, 0x10, 0x10, 0x1d, 0x20, 0x1d, 0x20, 0x0b, 0x17, 0x41, 0x43, 0x17, 0x41, 0x43, 0x40, 0x40, ++ 0x40, 0x0a, 0x0a, 0x0b, 0x40, 0x0f, 0x0b, 0x06, 0x06, 0x2c, 0x27, 0x1c, 0x07, 0x20, 0x1c, 0x14, ++ 0x44, 0x1a, 0x13, 0x0b, 0x40, 0x0b, 0x14, 0x06, 0x1d, 0x0b, 0x29, 0x18, 0x1d, 0x0b, 0x40, 0x40, ++ 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x07, 0x51, 0x1e, 0x04, 0x46, 0x40, 0x01, 0x51, 0x5e, 0x27, 0x40, 0x04, 0x40, 0x40, 0x40, 0x0f, ++ 0x04, 0x18, 0x06, 0x19, 0x0b, 0x18, 0x24, 0x3e, 0x3e, 0x07, 0x07, 0x03, 0x09, 0x0c, 0x13, 0x07, ++ 0x41, 0x27, 0x1e, 0x0b, 0x40, 0x43, 0x46, 0x40, 0x40, 0x40, 0x04, 0x04, 0x01, 0x06, 0x13, 0x06, ++ 0x0b, 0x18, 0x01, 0x41, 0x06, 0x20, 0x06, 0x41, 0x41, 0x0b, 0x13, 0x16, 0x11, 0x16, 0x01, 0x06, ++ 0x13, 0x06, 0x0b, 0x18, 0x01, 0x41, 0x06, 0x20, 0x06, 0x41, 0x41, 0x0b, 0x13, 0x16, 0x11, 0x16, ++ 0x21, 0x43, 0x34, 0x40, 0x48, 0x40, 0x04, 0x07, 0x04, 0x11, 0x11, 0x24, 0x07, 0x13, 0x41, 0x43, ++ 0x1c, 0x07, 0x40, 0x13, 0x41, 0x43, 0x1c, 0x07, 0x40, 0x13, 0x41, 0x43, 0x1c, 0x07, 0x40, 0x4c, ++ 0x07, 0x11, 0x11, 0x1e, 0x21, 0x1e, 0x21, 0x0b, 0x17, 0x41, 0x43, 0x17, 0x41, 0x43, 0x40, 0x40, ++ 0x40, 0x09, 0x09, 0x0b, 0x40, 0x0f, 0x0b, 0x06, 0x06, 0x2c, 0x27, 0x1c, 0x07, 0x21, 0x1c, 0x14, ++ 0x44, 0x19, 0x13, 0x0b, 0x40, 0x0b, 0x14, 0x06, 0x1e, 0x0b, 0x2b, 0x19, 0x1e, 0x0b, 0x40, 0x40, ++ 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x07, 0x52, 0x1f, 0x05, 0x45, 0x40, 0x00, 0x52, 0x5f, 0x27, 0x40, 0x05, 0x40, 0x40, 0x40, 0x0f, ++ 0x05, 0x19, 0x07, 0x1a, 0x0c, 0x19, 0x26, 0x3e, 0x3e, 0x07, 0x07, 0x02, 0x0a, 0x0d, 0x14, 0x07, ++ 0x40, 0x27, 0x1f, 0x0a, 0x40, 0x42, 0x47, 0x40, 0x40, 0x40, 0x05, 0x05, 0x02, 0x07, 0x14, 0x07, ++ 0x0c, 0x19, 0x02, 0x40, 0x07, 0x21, 0x07, 0x40, 0x40, 0x0c, 0x14, 0x17, 0x12, 0x17, 0x02, 0x07, ++ 0x14, 0x07, 0x0c, 0x19, 0x02, 0x40, 0x07, 0x21, 0x07, 0x40, 0x40, 0x0c, 0x14, 0x17, 0x12, 0x17, ++ 0x22, 0x42, 0x36, 0x40, 0x48, 0x40, 0x05, 0x07, 0x05, 0x12, 0x12, 0x26, 0x07, 0x12, 0x42, 0x42, ++ 0x1d, 0x07, 0x40, 0x12, 0x42, 0x42, 0x1d, 0x07, 0x40, 0x12, 0x42, 0x42, 0x1d, 0x07, 0x40, 0x4d, ++ 0x07, 0x12, 0x12, 0x1f, 0x22, 0x1f, 0x22, 0x0a, 0x17, 0x42, 0x42, 0x17, 0x42, 0x42, 0x40, 0x40, ++ 0x40, 0x08, 0x08, 0x0a, 0x40, 0x0f, 0x0a, 0x05, 0x05, 0x2d, 0x27, 0x1d, 0x07, 0x22, 0x1d, 0x15, ++ 0x45, 0x18, 0x12, 0x0a, 0x40, 0x0a, 0x15, 0x05, 0x1f, 0x0a, 0x2c, 0x1a, 0x1f, 0x0a, 0x40, 0x40, ++ 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x07, 0x52, 0x20, 0x05, 0x45, 0x40, 0x40, 0x52, 0x60, 0x27, 0x40, 0x05, 0x40, 0x40, 0x40, 0x0f, ++ 0x05, 0x1b, 0x08, 0x1a, 0x0d, 0x1b, 0x28, 0x3e, 0x3e, 0x07, 0x07, 0x02, 0x0a, 0x0d, 0x15, 0x07, ++ 0x00, 0x27, 0x20, 0x0a, 0x40, 0x42, 0x48, 0x40, 0x40, 0x40, 0x05, 0x05, 0x02, 0x08, 0x15, 0x08, ++ 0x0d, 0x1b, 0x02, 0x00, 0x08, 0x23, 0x08, 0x00, 0x00, 0x0d, 0x15, 0x18, 0x12, 0x18, 0x02, 0x08, ++ 0x15, 0x08, 0x0d, 0x1b, 0x02, 0x00, 0x08, 0x23, 0x08, 0x00, 0x00, 0x0d, 0x15, 0x18, 0x12, 0x18, ++ 0x22, 0x42, 0x38, 0x40, 0x48, 0x40, 0x05, 0x07, 0x05, 0x12, 0x12, 0x28, 0x07, 0x12, 0x42, 0x42, ++ 0x1d, 0x07, 0x40, 0x12, 0x42, 0x42, 0x1d, 0x07, 0x40, 0x12, 0x42, 0x42, 0x1d, 0x07, 0x40, 0x4d, ++ 0x07, 0x12, 0x12, 0x20, 0x22, 0x20, 0x22, 0x0a, 0x17, 0x42, 0x42, 0x17, 0x42, 0x42, 0x40, 0x40, ++ 0x40, 0x07, 0x07, 0x0a, 0x40, 0x0f, 0x0a, 0x05, 0x05, 0x2d, 0x27, 0x1d, 0x07, 0x22, 0x1d, 0x15, ++ 0x45, 0x17, 0x12, 0x0a, 0x40, 0x0a, 0x15, 0x05, 0x20, 0x0a, 0x2d, 0x1a, 0x20, 0x0a, 0x40, 0x40, ++ 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x07, 0x53, 0x21, 0x05, 0x44, 0x40, 0x41, 0x53, 0x61, 0x27, 0x40, 0x05, 0x40, 0x40, 0x40, 0x0f, ++ 0x05, 0x1c, 0x09, 0x1b, 0x0e, 0x1c, 0x2a, 0x3e, 0x3e, 0x07, 0x07, 0x02, 0x0b, 0x0d, 0x16, 0x07, ++ 0x01, 0x27, 0x21, 0x0a, 0x40, 0x42, 0x49, 0x40, 0x40, 0x40, 0x05, 0x05, 0x03, 0x09, 0x16, 0x09, ++ 0x0e, 0x1c, 0x03, 0x01, 0x09, 0x24, 0x09, 0x01, 0x01, 0x0e, 0x16, 0x19, 0x13, 0x19, 0x03, 0x09, ++ 0x16, 0x09, 0x0e, 0x1c, 0x03, 0x01, 0x09, 0x24, 0x09, 0x01, 0x01, 0x0e, 0x16, 0x19, 0x13, 0x19, ++ 0x23, 0x42, 0x3a, 0x40, 0x48, 0x40, 0x05, 0x07, 0x05, 0x13, 0x13, 0x2a, 0x07, 0x12, 0x43, 0x42, ++ 0x1d, 0x07, 0x40, 0x12, 0x43, 0x42, 0x1d, 0x07, 0x40, 0x12, 0x43, 0x42, 0x1d, 0x07, 0x40, 0x4d, ++ 0x07, 0x13, 0x13, 0x21, 0x23, 0x21, 0x23, 0x0a, 0x17, 0x43, 0x42, 0x17, 0x43, 0x42, 0x40, 0x40, ++ 0x40, 0x06, 0x06, 0x0a, 0x40, 0x0f, 0x0a, 0x04, 0x04, 0x2d, 0x27, 0x1d, 0x07, 0x23, 0x1d, 0x15, ++ 0x45, 0x16, 0x12, 0x0a, 0x40, 0x0a, 0x15, 0x04, 0x21, 0x0a, 0x2e, 0x1b, 0x21, 0x0a, 0x40, 0x40, ++ 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x07, 0x54, 0x22, 0x06, 0x43, 0x40, 0x42, 0x54, 0x62, 0x27, 0x40, 0x06, 0x40, 0x40, 0x40, 0x0f, ++ 0x06, 0x1e, 0x0a, 0x1c, 0x10, 0x1e, 0x2c, 0x3e, 0x3e, 0x07, 0x07, 0x01, 0x0c, 0x0e, 0x18, 0x07, ++ 0x02, 0x27, 0x22, 0x09, 0x40, 0x41, 0x4a, 0x40, 0x40, 0x40, 0x06, 0x06, 0x04, 0x0a, 0x18, 0x0a, ++ 0x10, 0x1e, 0x04, 0x02, 0x0a, 0x26, 0x0a, 0x02, 0x02, 0x10, 0x18, 0x1a, 0x14, 0x1a, 0x04, 0x0a, ++ 0x18, 0x0a, 0x10, 0x1e, 0x04, 0x02, 0x0a, 0x26, 0x0a, 0x02, 0x02, 0x10, 0x18, 0x1a, 0x14, 0x1a, ++ 0x24, 0x41, 0x3c, 0x40, 0x48, 0x40, 0x06, 0x07, 0x06, 0x14, 0x14, 0x2c, 0x07, 0x11, 0x44, 0x41, ++ 0x1e, 0x07, 0x40, 0x11, 0x44, 0x41, 0x1e, 0x07, 0x40, 0x11, 0x44, 0x41, 0x1e, 0x07, 0x40, 0x4e, ++ 0x07, 0x14, 0x14, 0x22, 0x24, 0x22, 0x24, 0x09, 0x17, 0x44, 0x41, 0x17, 0x44, 0x41, 0x40, 0x40, ++ 0x40, 0x05, 0x05, 0x09, 0x40, 0x0f, 0x09, 0x03, 0x03, 0x2e, 0x27, 0x1e, 0x07, 0x24, 0x1e, 0x16, ++ 0x46, 0x15, 0x11, 0x09, 0x40, 0x09, 0x16, 0x03, 0x22, 0x09, 0x30, 0x1c, 0x22, 0x09, 0x40, 0x40, ++ 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x07, 0x54, 0x23, 0x06, 0x43, 0x40, 0x43, 0x54, 0x63, 0x27, 0x40, 0x06, 0x40, 0x40, 0x40, 0x0f, ++ 0x06, 0x1f, 0x0b, 0x1c, 0x11, 0x1f, 0x2e, 0x3e, 0x3e, 0x07, 0x07, 0x01, 0x0c, 0x0e, 0x19, 0x07, ++ 0x03, 0x27, 0x23, 0x09, 0x40, 0x41, 0x4b, 0x40, 0x40, 0x40, 0x06, 0x06, 0x04, 0x0b, 0x19, 0x0b, ++ 0x11, 0x1f, 0x04, 0x03, 0x0b, 0x27, 0x0b, 0x03, 0x03, 0x11, 0x19, 0x1b, 0x14, 0x1b, 0x04, 0x0b, ++ 0x19, 0x0b, 0x11, 0x1f, 0x04, 0x03, 0x0b, 0x27, 0x0b, 0x03, 0x03, 0x11, 0x19, 0x1b, 0x14, 0x1b, ++ 0x24, 0x41, 0x3e, 0x40, 0x48, 0x40, 0x06, 0x07, 0x06, 0x14, 0x14, 0x2e, 0x07, 0x11, 0x44, 0x41, ++ 0x1e, 0x07, 0x40, 0x11, 0x44, 0x41, 0x1e, 0x07, 0x40, 0x11, 0x44, 0x41, 0x1e, 0x07, 0x40, 0x4e, ++ 0x07, 0x14, 0x14, 0x23, 0x24, 0x23, 0x24, 0x09, 0x17, 0x44, 0x41, 0x17, 0x44, 0x41, 0x40, 0x40, ++ 0x40, 0x04, 0x04, 0x09, 0x40, 0x0f, 0x09, 0x03, 0x03, 0x2e, 0x27, 0x1e, 0x07, 0x24, 0x1e, 0x16, ++ 0x46, 0x14, 0x11, 0x09, 0x40, 0x09, 0x16, 0x03, 0x23, 0x09, 0x31, 0x1c, 0x23, 0x09, 0x40, 0x40, ++ 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x07, 0x55, 0x24, 0x06, 0x42, 0x40, 0x44, 0x55, 0x64, 0x27, 0x40, 0x06, 0x40, 0x40, 0x40, 0x0f, ++ 0x06, 0x21, 0x0c, 0x1d, 0x12, 0x21, 0x30, 0x3e, 0x3e, 0x07, 0x07, 0x01, 0x0d, 0x0e, 0x1a, 0x07, ++ 0x04, 0x27, 0x24, 0x09, 0x40, 0x41, 0x4c, 0x40, 0x40, 0x40, 0x06, 0x06, 0x05, 0x0c, 0x1a, 0x0c, ++ 0x12, 0x21, 0x05, 0x04, 0x0c, 0x29, 0x0c, 0x04, 0x04, 0x12, 0x1a, 0x1c, 0x15, 0x1c, 0x05, 0x0c, ++ 0x1a, 0x0c, 0x12, 0x21, 0x05, 0x04, 0x0c, 0x29, 0x0c, 0x04, 0x04, 0x12, 0x1a, 0x1c, 0x15, 0x1c, ++ 0x25, 0x41, 0x3e, 0x40, 0x48, 0x40, 0x06, 0x07, 0x06, 0x15, 0x15, 0x30, 0x07, 0x11, 0x45, 0x41, ++ 0x1e, 0x07, 0x40, 0x11, 0x45, 0x41, 0x1e, 0x07, 0x40, 0x11, 0x45, 0x41, 0x1e, 0x07, 0x40, 0x4e, ++ 0x07, 0x15, 0x15, 0x24, 0x25, 0x24, 0x25, 0x09, 0x17, 0x45, 0x41, 0x17, 0x45, 0x41, 0x40, 0x40, ++ 0x40, 0x03, 0x03, 0x09, 0x40, 0x0f, 0x09, 0x02, 0x02, 0x2e, 0x27, 0x1e, 0x07, 0x25, 0x1e, 0x16, ++ 0x46, 0x13, 0x11, 0x09, 0x40, 0x09, 0x16, 0x02, 0x24, 0x09, 0x32, 0x1d, 0x24, 0x09, 0x40, 0x40, ++ 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x07, 0x56, 0x24, 0x06, 0x42, 0x40, 0x45, 0x56, 0x65, 0x27, 0x40, 0x06, 0x40, 0x40, 0x40, 0x0f, ++ 0x06, 0x22, 0x0c, 0x1d, 0x13, 0x22, 0x31, 0x3e, 0x3e, 0x07, 0x07, 0x00, 0x0d, 0x0e, 0x1b, 0x07, ++ 0x04, 0x27, 0x24, 0x08, 0x40, 0x41, 0x4d, 0x40, 0x40, 0x40, 0x06, 0x06, 0x05, 0x0c, 0x1b, 0x0c, ++ 0x13, 0x22, 0x05, 0x04, 0x0c, 0x2a, 0x0c, 0x04, 0x04, 0x13, 0x1b, 0x1c, 0x15, 0x1c, 0x05, 0x0c, ++ 0x1b, 0x0c, 0x13, 0x22, 0x05, 0x04, 0x0c, 0x2a, 0x0c, 0x04, 0x04, 0x13, 0x1b, 0x1c, 0x15, 0x1c, ++ 0x25, 0x41, 0x3e, 0x40, 0x48, 0x40, 0x06, 0x07, 0x06, 0x15, 0x15, 0x31, 0x07, 0x10, 0x46, 0x41, ++ 0x1e, 0x07, 0x40, 0x10, 0x46, 0x41, 0x1e, 0x07, 0x40, 0x10, 0x46, 0x41, 0x1e, 0x07, 0x40, 0x4f, ++ 0x07, 0x15, 0x15, 0x24, 0x25, 0x24, 0x25, 0x08, 0x17, 0x46, 0x41, 0x17, 0x46, 0x41, 0x40, 0x40, ++ 0x40, 0x02, 0x02, 0x08, 0x40, 0x0f, 0x08, 0x01, 0x01, 0x2e, 0x27, 0x1e, 0x07, 0x25, 0x1e, 0x16, ++ 0x47, 0x12, 0x10, 0x08, 0x40, 0x08, 0x16, 0x01, 0x24, 0x08, 0x33, 0x1d, 0x24, 0x08, 0x40, 0x40, ++ 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x07, 0x56, 0x25, 0x07, 0x41, 0x40, 0x45, 0x56, 0x65, 0x27, 0x40, 0x07, 0x40, 0x40, 0x40, 0x0f, ++ 0x07, 0x24, 0x0d, 0x1e, 0x15, 0x24, 0x33, 0x3e, 0x3e, 0x07, 0x07, 0x00, 0x0e, 0x0f, 0x1d, 0x07, ++ 0x05, 0x27, 0x25, 0x08, 0x40, 0x40, 0x4d, 0x40, 0x40, 0x40, 0x07, 0x07, 0x06, 0x0d, 0x1d, 0x0d, ++ 0x15, 0x24, 0x06, 0x05, 0x0d, 0x2c, 0x0d, 0x05, 0x05, 0x15, 0x1d, 0x1d, 0x16, 0x1d, 0x06, 0x0d, ++ 0x1d, 0x0d, 0x15, 0x24, 0x06, 0x05, 0x0d, 0x2c, 0x0d, 0x05, 0x05, 0x15, 0x1d, 0x1d, 0x16, 0x1d, ++ 0x26, 0x40, 0x3e, 0x40, 0x48, 0x40, 0x07, 0x07, 0x07, 0x16, 0x16, 0x33, 0x07, 0x10, 0x46, 0x40, ++ 0x1f, 0x07, 0x40, 0x10, 0x46, 0x40, 0x1f, 0x07, 0x40, 0x10, 0x46, 0x40, 0x1f, 0x07, 0x40, 0x4f, ++ 0x07, 0x16, 0x16, 0x25, 0x26, 0x25, 0x26, 0x08, 0x17, 0x46, 0x40, 0x17, 0x46, 0x40, 0x40, 0x40, ++ 0x40, 0x02, 0x02, 0x08, 0x40, 0x0f, 0x08, 0x01, 0x01, 0x2f, 0x27, 0x1f, 0x07, 0x26, 0x1f, 0x17, ++ 0x47, 0x12, 0x10, 0x08, 0x40, 0x08, 0x17, 0x01, 0x25, 0x08, 0x35, 0x1e, 0x25, 0x08, 0x40, 0x40, ++ 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x07, 0x57, 0x26, 0x07, 0x40, 0x40, 0x46, 0x57, 0x66, 0x27, 0x40, 0x07, 0x40, 0x40, 0x40, 0x0f, ++ 0x07, 0x26, 0x0e, 0x1f, 0x16, 0x26, 0x35, 0x3e, 0x3e, 0x07, 0x07, 0x00, 0x0f, 0x0f, 0x1e, 0x07, ++ 0x06, 0x27, 0x26, 0x08, 0x40, 0x40, 0x4e, 0x40, 0x40, 0x40, 0x07, 0x07, 0x07, 0x0e, 0x1e, 0x0e, ++ 0x16, 0x26, 0x07, 0x06, 0x0e, 0x2e, 0x0e, 0x06, 0x06, 0x16, 0x1e, 0x1e, 0x17, 0x1e, 0x07, 0x0e, ++ 0x1e, 0x0e, 0x16, 0x26, 0x07, 0x06, 0x0e, 0x2e, 0x0e, 0x06, 0x06, 0x16, 0x1e, 0x1e, 0x17, 0x1e, ++ 0x27, 0x40, 0x3e, 0x40, 0x48, 0x40, 0x07, 0x07, 0x07, 0x17, 0x17, 0x35, 0x07, 0x10, 0x47, 0x40, ++ 0x1f, 0x07, 0x40, 0x10, 0x47, 0x40, 0x1f, 0x07, 0x40, 0x10, 0x47, 0x40, 0x1f, 0x07, 0x40, 0x4f, ++ 0x07, 0x17, 0x17, 0x26, 0x27, 0x26, 0x27, 0x08, 0x17, 0x47, 0x40, 0x17, 0x47, 0x40, 0x40, 0x40, ++ 0x40, 0x01, 0x01, 0x08, 0x40, 0x0f, 0x08, 0x00, 0x00, 0x2f, 0x27, 0x1f, 0x07, 0x27, 0x1f, 0x17, ++ 0x47, 0x11, 0x10, 0x08, 0x40, 0x08, 0x17, 0x00, 0x26, 0x08, 0x36, 0x1f, 0x26, 0x08, 0x40, 0x40, ++ 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x07, 0x57, 0x27, 0x07, 0x40, 0x40, 0x47, 0x57, 0x67, 0x27, 0x40, 0x07, 0x40, 0x40, 0x40, 0x0f, ++ 0x07, 0x27, 0x0f, 0x1f, 0x17, 0x27, 0x37, 0x3e, 0x3e, 0x07, 0x07, 0x00, 0x0f, 0x0f, 0x1f, 0x07, ++ 0x07, 0x27, 0x27, 0x08, 0x40, 0x40, 0x4f, 0x40, 0x40, 0x40, 0x07, 0x07, 0x07, 0x0f, 0x1f, 0x0f, ++ 0x17, 0x27, 0x07, 0x07, 0x0f, 0x2f, 0x0f, 0x07, 0x07, 0x17, 0x1f, 0x1f, 0x17, 0x1f, 0x07, 0x0f, ++ 0x1f, 0x0f, 0x17, 0x27, 0x07, 0x07, 0x0f, 0x2f, 0x0f, 0x07, 0x07, 0x17, 0x1f, 0x1f, 0x17, 0x1f, ++ 0x27, 0x40, 0x3e, 0x40, 0x48, 0x40, 0x07, 0x07, 0x07, 0x17, 0x17, 0x37, 0x07, 0x10, 0x47, 0x40, ++ 0x1f, 0x07, 0x40, 0x10, 0x47, 0x40, 0x1f, 0x07, 0x40, 0x10, 0x47, 0x40, 0x1f, 0x07, 0x40, 0x4f, ++ 0x07, 0x17, 0x17, 0x27, 0x27, 0x27, 0x27, 0x08, 0x17, 0x47, 0x40, 0x17, 0x47, 0x40, 0x40, 0x40, ++ 0x40, 0x00, 0x00, 0x08, 0x40, 0x0f, 0x08, 0x00, 0x00, 0x2f, 0x27, 0x1f, 0x07, 0x27, 0x1f, 0x17, ++ 0x47, 0x10, 0x10, 0x08, 0x40, 0x08, 0x17, 0x00, 0x27, 0x08, 0x37, 0x1f, 0x27, 0x08, 0x40, 0x40, ++ 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x07, 0x3e, 0x48, 0x48, 0x60, 0x40, 0x27, 0x07, 0x07, 0x1f, 0x40, 0x48, 0x40, 0x40, 0x17, 0x0f, ++ 0x48, 0x68, 0x40, 0x07, 0x68, 0x68, 0x68, 0x68, 0x68, 0x07, 0x07, 0x0f, 0x3e, 0x17, 0x40, 0x07, ++ 0x68, 0x27, 0x50, 0x17, 0x40, 0x07, 0x1f, 0x40, 0x40, 0x40, 0x48, 0x48, 0x58, 0x60, 0x50, 0x60, ++ 0x68, 0x60, 0x58, 0x68, 0x68, 0x68, 0x58, 0x60, 0x68, 0x68, 0x68, 0x50, 0x48, 0x58, 0x58, 0x60, ++ 0x50, 0x60, 0x68, 0x60, 0x58, 0x68, 0x68, 0x68, 0x58, 0x60, 0x68, 0x68, 0x68, 0x50, 0x48, 0x58, ++ 0x07, 0x50, 0x58, 0x40, 0x40, 0x40, 0x48, 0x07, 0x48, 0x48, 0x48, 0x68, 0x50, 0x1f, 0x17, 0x50, ++ 0x0f, 0x07, 0x40, 0x1f, 0x17, 0x50, 0x0f, 0x07, 0x40, 0x1f, 0x17, 0x50, 0x0f, 0x07, 0x40, 0x40, ++ 0x07, 0x40, 0x40, 0x40, 0x07, 0x40, 0x07, 0x17, 0x17, 0x17, 0x50, 0x17, 0x17, 0x50, 0x40, 0x40, ++ 0x40, 0x2f, 0x17, 0x17, 0x40, 0x0f, 0x17, 0x1f, 0x1f, 0x1f, 0x27, 0x0f, 0x07, 0x07, 0x0f, 0x40, ++ 0x07, 0x3e, 0x1f, 0x17, 0x40, 0x0f, 0x17, 0x1f, 0x48, 0x17, 0x48, 0x48, 0x48, 0x17, 0x40, 0x40, ++ 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x07, 0x3e, 0x47, 0x47, 0x5f, 0x40, 0x27, 0x07, 0x07, 0x20, 0x40, 0x47, 0x40, 0x40, 0x17, 0x0f, ++ 0x47, 0x66, 0x40, 0x08, 0x66, 0x66, 0x66, 0x65, 0x65, 0x07, 0x07, 0x0f, 0x3e, 0x17, 0x00, 0x07, ++ 0x67, 0x27, 0x4e, 0x17, 0x40, 0x07, 0x1f, 0x40, 0x40, 0x40, 0x47, 0x47, 0x57, 0x5f, 0x4f, 0x5f, ++ 0x66, 0x5e, 0x57, 0x67, 0x67, 0x66, 0x57, 0x5f, 0x67, 0x67, 0x66, 0x4f, 0x47, 0x56, 0x57, 0x5f, ++ 0x4f, 0x5f, 0x66, 0x5e, 0x57, 0x67, 0x67, 0x66, 0x57, 0x5f, 0x67, 0x67, 0x66, 0x4f, 0x47, 0x56, ++ 0x08, 0x4f, 0x56, 0x40, 0x40, 0x40, 0x47, 0x07, 0x47, 0x47, 0x47, 0x66, 0x4f, 0x1f, 0x17, 0x4f, ++ 0x10, 0x07, 0x40, 0x1f, 0x17, 0x4f, 0x10, 0x07, 0x40, 0x1f, 0x17, 0x4f, 0x10, 0x07, 0x40, 0x40, ++ 0x07, 0x00, 0x00, 0x00, 0x08, 0x00, 0x08, 0x17, 0x17, 0x17, 0x4f, 0x17, 0x17, 0x4f, 0x40, 0x40, ++ 0x40, 0x2f, 0x17, 0x17, 0x40, 0x0f, 0x17, 0x1f, 0x1f, 0x20, 0x27, 0x10, 0x07, 0x08, 0x10, 0x00, ++ 0x07, 0x3e, 0x1f, 0x17, 0x40, 0x0f, 0x17, 0x1f, 0x47, 0x17, 0x46, 0x47, 0x47, 0x17, 0x40, 0x40, ++ 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x07, 0x3e, 0x46, 0x47, 0x5e, 0x40, 0x26, 0x06, 0x06, 0x20, 0x40, 0x47, 0x40, 0x40, 0x16, 0x0f, ++ 0x47, 0x64, 0x40, 0x08, 0x65, 0x64, 0x64, 0x63, 0x63, 0x07, 0x07, 0x0f, 0x3e, 0x17, 0x01, 0x07, ++ 0x66, 0x27, 0x4d, 0x17, 0x40, 0x07, 0x1e, 0x40, 0x40, 0x40, 0x47, 0x47, 0x56, 0x5e, 0x4e, 0x5e, ++ 0x65, 0x5d, 0x56, 0x66, 0x66, 0x64, 0x56, 0x5e, 0x66, 0x66, 0x64, 0x4e, 0x46, 0x55, 0x56, 0x5e, ++ 0x4e, 0x5e, 0x65, 0x5d, 0x56, 0x66, 0x66, 0x64, 0x56, 0x5e, 0x66, 0x66, 0x64, 0x4e, 0x46, 0x55, ++ 0x09, 0x4f, 0x54, 0x40, 0x40, 0x40, 0x47, 0x07, 0x47, 0x46, 0x46, 0x64, 0x4e, 0x1f, 0x16, 0x4f, ++ 0x10, 0x07, 0x40, 0x1f, 0x16, 0x4f, 0x10, 0x07, 0x40, 0x1f, 0x16, 0x4f, 0x10, 0x07, 0x40, 0x40, ++ 0x07, 0x00, 0x00, 0x01, 0x09, 0x01, 0x09, 0x17, 0x17, 0x16, 0x4f, 0x17, 0x16, 0x4f, 0x40, 0x40, ++ 0x40, 0x2e, 0x17, 0x17, 0x40, 0x0f, 0x17, 0x1e, 0x1e, 0x20, 0x27, 0x10, 0x07, 0x09, 0x10, 0x01, ++ 0x07, 0x3e, 0x1f, 0x17, 0x40, 0x0f, 0x17, 0x1e, 0x46, 0x17, 0x45, 0x46, 0x46, 0x17, 0x40, 0x40, ++ 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x07, 0x3e, 0x45, 0x47, 0x5e, 0x40, 0x25, 0x06, 0x05, 0x20, 0x40, 0x47, 0x40, 0x40, 0x16, 0x0f, ++ 0x47, 0x63, 0x40, 0x08, 0x64, 0x63, 0x62, 0x60, 0x60, 0x07, 0x07, 0x0f, 0x3e, 0x17, 0x01, 0x07, ++ 0x65, 0x27, 0x4c, 0x17, 0x40, 0x07, 0x1d, 0x40, 0x40, 0x40, 0x47, 0x47, 0x56, 0x5d, 0x4e, 0x5d, ++ 0x64, 0x5c, 0x56, 0x65, 0x65, 0x63, 0x56, 0x5e, 0x65, 0x65, 0x63, 0x4d, 0x46, 0x54, 0x56, 0x5d, ++ 0x4e, 0x5d, 0x64, 0x5c, 0x56, 0x65, 0x65, 0x63, 0x56, 0x5e, 0x65, 0x65, 0x63, 0x4d, 0x46, 0x54, ++ 0x09, 0x4f, 0x52, 0x40, 0x40, 0x40, 0x47, 0x07, 0x47, 0x46, 0x46, 0x62, 0x4e, 0x1f, 0x16, 0x4f, ++ 0x10, 0x07, 0x40, 0x1f, 0x16, 0x4f, 0x10, 0x07, 0x40, 0x1f, 0x16, 0x4f, 0x10, 0x07, 0x40, 0x40, ++ 0x07, 0x00, 0x00, 0x01, 0x09, 0x01, 0x09, 0x17, 0x17, 0x16, 0x4f, 0x17, 0x16, 0x4f, 0x40, 0x40, ++ 0x40, 0x2d, 0x17, 0x17, 0x40, 0x0f, 0x17, 0x1e, 0x1e, 0x20, 0x27, 0x10, 0x07, 0x09, 0x10, 0x01, ++ 0x07, 0x3e, 0x1f, 0x17, 0x40, 0x0f, 0x17, 0x1e, 0x45, 0x17, 0x44, 0x45, 0x45, 0x17, 0x40, 0x40, ++ 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x07, 0x3e, 0x44, 0x46, 0x5d, 0x40, 0x24, 0x05, 0x04, 0x21, 0x40, 0x46, 0x40, 0x40, 0x15, 0x0f, ++ 0x46, 0x61, 0x40, 0x09, 0x63, 0x61, 0x60, 0x5e, 0x5e, 0x07, 0x07, 0x0e, 0x3e, 0x16, 0x02, 0x07, ++ 0x64, 0x27, 0x4b, 0x16, 0x40, 0x06, 0x1c, 0x40, 0x40, 0x40, 0x46, 0x46, 0x55, 0x5c, 0x4d, 0x5c, ++ 0x63, 0x5b, 0x55, 0x64, 0x64, 0x61, 0x55, 0x5d, 0x64, 0x64, 0x61, 0x4c, 0x45, 0x53, 0x55, 0x5c, ++ 0x4d, 0x5c, 0x63, 0x5b, 0x55, 0x64, 0x64, 0x61, 0x55, 0x5d, 0x64, 0x64, 0x61, 0x4c, 0x45, 0x53, ++ 0x0a, 0x4e, 0x50, 0x40, 0x41, 0x40, 0x46, 0x07, 0x46, 0x45, 0x45, 0x60, 0x4d, 0x1e, 0x15, 0x4e, ++ 0x11, 0x07, 0x40, 0x1e, 0x15, 0x4e, 0x11, 0x07, 0x40, 0x1e, 0x15, 0x4e, 0x11, 0x07, 0x40, 0x41, ++ 0x07, 0x01, 0x01, 0x02, 0x0a, 0x02, 0x0a, 0x16, 0x17, 0x15, 0x4e, 0x17, 0x15, 0x4e, 0x40, 0x40, ++ 0x40, 0x2c, 0x16, 0x16, 0x40, 0x0f, 0x16, 0x1d, 0x1d, 0x21, 0x27, 0x11, 0x07, 0x0a, 0x11, 0x02, ++ 0x06, 0x3e, 0x1e, 0x16, 0x40, 0x0f, 0x16, 0x1d, 0x44, 0x16, 0x43, 0x44, 0x44, 0x16, 0x40, 0x40, ++ 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x07, 0x3e, 0x43, 0x46, 0x5c, 0x40, 0x23, 0x04, 0x03, 0x21, 0x40, 0x46, 0x40, 0x40, 0x14, 0x0f, ++ 0x46, 0x60, 0x40, 0x09, 0x61, 0x60, 0x5e, 0x5b, 0x5b, 0x07, 0x07, 0x0e, 0x3e, 0x16, 0x03, 0x07, ++ 0x63, 0x27, 0x49, 0x16, 0x40, 0x06, 0x1b, 0x40, 0x40, 0x40, 0x46, 0x46, 0x54, 0x5b, 0x4c, 0x5b, ++ 0x61, 0x59, 0x54, 0x63, 0x63, 0x60, 0x54, 0x5c, 0x63, 0x63, 0x60, 0x4b, 0x44, 0x51, 0x54, 0x5b, ++ 0x4c, 0x5b, 0x61, 0x59, 0x54, 0x63, 0x63, 0x60, 0x54, 0x5c, 0x63, 0x63, 0x60, 0x4b, 0x44, 0x51, ++ 0x0b, 0x4e, 0x4e, 0x40, 0x41, 0x40, 0x46, 0x07, 0x46, 0x44, 0x44, 0x5e, 0x4c, 0x1e, 0x14, 0x4e, ++ 0x11, 0x07, 0x40, 0x1e, 0x14, 0x4e, 0x11, 0x07, 0x40, 0x1e, 0x14, 0x4e, 0x11, 0x07, 0x40, 0x41, ++ 0x07, 0x01, 0x01, 0x03, 0x0b, 0x03, 0x0b, 0x16, 0x17, 0x14, 0x4e, 0x17, 0x14, 0x4e, 0x40, 0x40, ++ 0x40, 0x2b, 0x16, 0x16, 0x40, 0x0f, 0x16, 0x1c, 0x1c, 0x21, 0x27, 0x11, 0x07, 0x0b, 0x11, 0x03, ++ 0x06, 0x3e, 0x1e, 0x16, 0x40, 0x0f, 0x16, 0x1c, 0x43, 0x16, 0x41, 0x43, 0x43, 0x16, 0x40, 0x40, ++ 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x07, 0x3e, 0x42, 0x46, 0x5c, 0x40, 0x22, 0x04, 0x02, 0x21, 0x40, 0x46, 0x40, 0x40, 0x14, 0x0f, ++ 0x46, 0x5e, 0x40, 0x09, 0x60, 0x5e, 0x5c, 0x59, 0x59, 0x07, 0x07, 0x0e, 0x3e, 0x16, 0x03, 0x07, ++ 0x62, 0x27, 0x48, 0x16, 0x40, 0x06, 0x1a, 0x40, 0x40, 0x40, 0x46, 0x46, 0x54, 0x5a, 0x4c, 0x5a, ++ 0x60, 0x58, 0x54, 0x62, 0x62, 0x5e, 0x54, 0x5c, 0x62, 0x62, 0x5e, 0x4a, 0x44, 0x50, 0x54, 0x5a, ++ 0x4c, 0x5a, 0x60, 0x58, 0x54, 0x62, 0x62, 0x5e, 0x54, 0x5c, 0x62, 0x62, 0x5e, 0x4a, 0x44, 0x50, ++ 0x0b, 0x4e, 0x4c, 0x40, 0x41, 0x40, 0x46, 0x07, 0x46, 0x44, 0x44, 0x5c, 0x4c, 0x1e, 0x14, 0x4e, ++ 0x11, 0x07, 0x40, 0x1e, 0x14, 0x4e, 0x11, 0x07, 0x40, 0x1e, 0x14, 0x4e, 0x11, 0x07, 0x40, 0x41, ++ 0x07, 0x01, 0x01, 0x03, 0x0b, 0x03, 0x0b, 0x16, 0x17, 0x14, 0x4e, 0x17, 0x14, 0x4e, 0x40, 0x40, ++ 0x40, 0x2a, 0x16, 0x16, 0x40, 0x0f, 0x16, 0x1c, 0x1c, 0x21, 0x27, 0x11, 0x07, 0x0b, 0x11, 0x03, ++ 0x06, 0x3e, 0x1e, 0x16, 0x40, 0x0f, 0x16, 0x1c, 0x42, 0x16, 0x40, 0x42, 0x42, 0x16, 0x40, 0x40, ++ 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x07, 0x3e, 0x41, 0x45, 0x5b, 0x40, 0x21, 0x03, 0x01, 0x22, 0x40, 0x45, 0x40, 0x40, 0x13, 0x0f, ++ 0x45, 0x5d, 0x40, 0x0a, 0x5f, 0x5d, 0x5a, 0x56, 0x56, 0x07, 0x07, 0x0d, 0x3e, 0x15, 0x04, 0x07, ++ 0x61, 0x27, 0x47, 0x15, 0x40, 0x05, 0x19, 0x40, 0x40, 0x40, 0x45, 0x45, 0x53, 0x59, 0x4b, 0x59, ++ 0x5f, 0x57, 0x53, 0x61, 0x61, 0x5d, 0x53, 0x5b, 0x61, 0x61, 0x5d, 0x49, 0x43, 0x4f, 0x53, 0x59, ++ 0x4b, 0x59, 0x5f, 0x57, 0x53, 0x61, 0x61, 0x5d, 0x53, 0x5b, 0x61, 0x61, 0x5d, 0x49, 0x43, 0x4f, ++ 0x0c, 0x4d, 0x4a, 0x40, 0x42, 0x40, 0x45, 0x07, 0x45, 0x43, 0x43, 0x5a, 0x4b, 0x1d, 0x13, 0x4d, ++ 0x12, 0x07, 0x40, 0x1d, 0x13, 0x4d, 0x12, 0x07, 0x40, 0x1d, 0x13, 0x4d, 0x12, 0x07, 0x40, 0x42, ++ 0x07, 0x02, 0x02, 0x04, 0x0c, 0x04, 0x0c, 0x15, 0x17, 0x13, 0x4d, 0x17, 0x13, 0x4d, 0x40, 0x40, ++ 0x40, 0x29, 0x15, 0x15, 0x40, 0x0f, 0x15, 0x1b, 0x1b, 0x22, 0x27, 0x12, 0x07, 0x0c, 0x12, 0x04, ++ 0x05, 0x3e, 0x1d, 0x15, 0x40, 0x0f, 0x15, 0x1b, 0x41, 0x15, 0x00, 0x41, 0x41, 0x15, 0x40, 0x40, ++ 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x07, 0x3e, 0x40, 0x45, 0x5b, 0x40, 0x20, 0x02, 0x00, 0x22, 0x40, 0x45, 0x40, 0x40, 0x12, 0x0f, ++ 0x45, 0x5b, 0x40, 0x0a, 0x5e, 0x5b, 0x59, 0x54, 0x54, 0x07, 0x07, 0x0d, 0x3e, 0x15, 0x04, 0x07, ++ 0x60, 0x27, 0x46, 0x15, 0x40, 0x05, 0x18, 0x40, 0x40, 0x40, 0x45, 0x45, 0x53, 0x58, 0x4b, 0x58, ++ 0x5e, 0x56, 0x53, 0x60, 0x60, 0x5b, 0x53, 0x5b, 0x60, 0x60, 0x5b, 0x48, 0x43, 0x4e, 0x53, 0x58, ++ 0x4b, 0x58, 0x5e, 0x56, 0x53, 0x60, 0x60, 0x5b, 0x53, 0x5b, 0x60, 0x60, 0x5b, 0x48, 0x43, 0x4e, ++ 0x0c, 0x4d, 0x49, 0x40, 0x42, 0x40, 0x45, 0x07, 0x45, 0x43, 0x43, 0x59, 0x4b, 0x1d, 0x12, 0x4d, ++ 0x12, 0x07, 0x40, 0x1d, 0x12, 0x4d, 0x12, 0x07, 0x40, 0x1d, 0x12, 0x4d, 0x12, 0x07, 0x40, 0x42, ++ 0x07, 0x02, 0x02, 0x04, 0x0c, 0x04, 0x0c, 0x15, 0x17, 0x12, 0x4d, 0x17, 0x12, 0x4d, 0x40, 0x40, ++ 0x40, 0x28, 0x15, 0x15, 0x40, 0x0f, 0x15, 0x1a, 0x1a, 0x22, 0x27, 0x12, 0x07, 0x0c, 0x12, 0x04, ++ 0x05, 0x3e, 0x1d, 0x15, 0x40, 0x0f, 0x15, 0x1a, 0x40, 0x15, 0x01, 0x40, 0x40, 0x15, 0x40, 0x40, ++ 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x07, 0x3e, 0x00, 0x45, 0x5a, 0x40, 0x1f, 0x02, 0x40, 0x22, 0x40, 0x45, 0x40, 0x40, 0x12, 0x0f, ++ 0x45, 0x59, 0x40, 0x0a, 0x5c, 0x59, 0x57, 0x51, 0x51, 0x07, 0x07, 0x0d, 0x3e, 0x15, 0x05, 0x07, ++ 0x5f, 0x27, 0x44, 0x15, 0x40, 0x05, 0x17, 0x40, 0x40, 0x40, 0x45, 0x45, 0x52, 0x57, 0x4a, 0x57, ++ 0x5c, 0x54, 0x52, 0x5f, 0x5f, 0x59, 0x52, 0x5a, 0x5f, 0x5f, 0x59, 0x47, 0x42, 0x4c, 0x52, 0x57, ++ 0x4a, 0x57, 0x5c, 0x54, 0x52, 0x5f, 0x5f, 0x59, 0x52, 0x5a, 0x5f, 0x5f, 0x59, 0x47, 0x42, 0x4c, ++ 0x0d, 0x4d, 0x47, 0x40, 0x42, 0x40, 0x45, 0x07, 0x45, 0x42, 0x42, 0x57, 0x4a, 0x1d, 0x12, 0x4d, ++ 0x12, 0x07, 0x40, 0x1d, 0x12, 0x4d, 0x12, 0x07, 0x40, 0x1d, 0x12, 0x4d, 0x12, 0x07, 0x40, 0x42, ++ 0x07, 0x02, 0x02, 0x05, 0x0d, 0x05, 0x0d, 0x15, 0x17, 0x12, 0x4d, 0x17, 0x12, 0x4d, 0x40, 0x40, ++ 0x40, 0x27, 0x15, 0x15, 0x40, 0x0f, 0x15, 0x1a, 0x1a, 0x22, 0x27, 0x12, 0x07, 0x0d, 0x12, 0x05, ++ 0x05, 0x3e, 0x1d, 0x15, 0x40, 0x0f, 0x15, 0x1a, 0x00, 0x15, 0x03, 0x00, 0x00, 0x15, 0x40, 0x40, ++ 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x07, 0x3e, 0x01, 0x44, 0x59, 0x40, 0x1e, 0x01, 0x41, 0x23, 0x40, 0x44, 0x40, 0x40, 0x11, 0x0f, ++ 0x44, 0x58, 0x40, 0x0b, 0x5b, 0x58, 0x55, 0x4f, 0x4f, 0x07, 0x07, 0x0c, 0x3e, 0x14, 0x06, 0x07, ++ 0x5e, 0x27, 0x43, 0x14, 0x40, 0x04, 0x16, 0x40, 0x40, 0x40, 0x44, 0x44, 0x51, 0x56, 0x49, 0x56, ++ 0x5b, 0x53, 0x51, 0x5e, 0x5e, 0x58, 0x51, 0x59, 0x5e, 0x5e, 0x58, 0x46, 0x41, 0x4b, 0x51, 0x56, ++ 0x49, 0x56, 0x5b, 0x53, 0x51, 0x5e, 0x5e, 0x58, 0x51, 0x59, 0x5e, 0x5e, 0x58, 0x46, 0x41, 0x4b, ++ 0x0e, 0x4c, 0x45, 0x40, 0x43, 0x40, 0x44, 0x07, 0x44, 0x41, 0x41, 0x55, 0x49, 0x1c, 0x11, 0x4c, ++ 0x13, 0x07, 0x40, 0x1c, 0x11, 0x4c, 0x13, 0x07, 0x40, 0x1c, 0x11, 0x4c, 0x13, 0x07, 0x40, 0x43, ++ 0x07, 0x03, 0x03, 0x06, 0x0e, 0x06, 0x0e, 0x14, 0x17, 0x11, 0x4c, 0x17, 0x11, 0x4c, 0x40, 0x40, ++ 0x40, 0x26, 0x14, 0x14, 0x40, 0x0f, 0x14, 0x19, 0x19, 0x23, 0x27, 0x13, 0x07, 0x0e, 0x13, 0x06, ++ 0x04, 0x3e, 0x1c, 0x14, 0x40, 0x0f, 0x14, 0x19, 0x01, 0x14, 0x04, 0x01, 0x01, 0x14, 0x40, 0x40, ++ 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x07, 0x3e, 0x02, 0x44, 0x59, 0x40, 0x1d, 0x01, 0x42, 0x23, 0x40, 0x44, 0x40, 0x40, 0x11, 0x0f, ++ 0x44, 0x56, 0x40, 0x0b, 0x5a, 0x56, 0x53, 0x4c, 0x4c, 0x07, 0x07, 0x0c, 0x3e, 0x14, 0x06, 0x07, ++ 0x5d, 0x27, 0x42, 0x14, 0x40, 0x04, 0x15, 0x40, 0x40, 0x40, 0x44, 0x44, 0x51, 0x55, 0x49, 0x55, ++ 0x5a, 0x52, 0x51, 0x5d, 0x5d, 0x56, 0x51, 0x59, 0x5d, 0x5d, 0x56, 0x45, 0x41, 0x4a, 0x51, 0x55, ++ 0x49, 0x55, 0x5a, 0x52, 0x51, 0x5d, 0x5d, 0x56, 0x51, 0x59, 0x5d, 0x5d, 0x56, 0x45, 0x41, 0x4a, ++ 0x0e, 0x4c, 0x43, 0x40, 0x43, 0x40, 0x44, 0x07, 0x44, 0x41, 0x41, 0x53, 0x49, 0x1c, 0x11, 0x4c, ++ 0x13, 0x07, 0x40, 0x1c, 0x11, 0x4c, 0x13, 0x07, 0x40, 0x1c, 0x11, 0x4c, 0x13, 0x07, 0x40, 0x43, ++ 0x07, 0x03, 0x03, 0x06, 0x0e, 0x06, 0x0e, 0x14, 0x17, 0x11, 0x4c, 0x17, 0x11, 0x4c, 0x40, 0x40, ++ 0x40, 0x25, 0x14, 0x14, 0x40, 0x0f, 0x14, 0x19, 0x19, 0x23, 0x27, 0x13, 0x07, 0x0e, 0x13, 0x06, ++ 0x04, 0x3e, 0x1c, 0x14, 0x40, 0x0f, 0x14, 0x19, 0x02, 0x14, 0x05, 0x02, 0x02, 0x14, 0x40, 0x40, ++ 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x07, 0x3e, 0x03, 0x44, 0x58, 0x40, 0x1c, 0x00, 0x43, 0x23, 0x40, 0x44, 0x40, 0x40, 0x10, 0x0f, ++ 0x44, 0x55, 0x40, 0x0b, 0x59, 0x55, 0x51, 0x4a, 0x4a, 0x07, 0x07, 0x0c, 0x3d, 0x14, 0x07, 0x07, ++ 0x5c, 0x27, 0x41, 0x14, 0x40, 0x04, 0x14, 0x40, 0x40, 0x40, 0x44, 0x44, 0x50, 0x54, 0x48, 0x54, ++ 0x59, 0x51, 0x50, 0x5c, 0x5c, 0x55, 0x50, 0x58, 0x5c, 0x5c, 0x55, 0x44, 0x40, 0x49, 0x50, 0x54, ++ 0x48, 0x54, 0x59, 0x51, 0x50, 0x5c, 0x5c, 0x55, 0x50, 0x58, 0x5c, 0x5c, 0x55, 0x44, 0x40, 0x49, ++ 0x0f, 0x4c, 0x41, 0x40, 0x43, 0x40, 0x44, 0x07, 0x44, 0x40, 0x40, 0x51, 0x48, 0x1c, 0x10, 0x4c, ++ 0x13, 0x07, 0x40, 0x1c, 0x10, 0x4c, 0x13, 0x07, 0x40, 0x1c, 0x10, 0x4c, 0x13, 0x07, 0x40, 0x43, ++ 0x07, 0x03, 0x03, 0x07, 0x0f, 0x07, 0x0f, 0x14, 0x17, 0x10, 0x4c, 0x17, 0x10, 0x4c, 0x40, 0x40, ++ 0x40, 0x24, 0x14, 0x14, 0x40, 0x0f, 0x14, 0x18, 0x18, 0x23, 0x27, 0x13, 0x07, 0x0f, 0x13, 0x07, ++ 0x04, 0x3e, 0x1c, 0x14, 0x40, 0x0f, 0x14, 0x18, 0x03, 0x14, 0x06, 0x03, 0x03, 0x14, 0x40, 0x40, ++ 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x07, 0x3e, 0x04, 0x43, 0x57, 0x40, 0x1b, 0x40, 0x44, 0x24, 0x40, 0x43, 0x40, 0x40, 0x0f, 0x0f, ++ 0x43, 0x53, 0x40, 0x0c, 0x57, 0x53, 0x4f, 0x47, 0x47, 0x07, 0x07, 0x0b, 0x3b, 0x13, 0x08, 0x07, ++ 0x5b, 0x27, 0x00, 0x13, 0x40, 0x03, 0x13, 0x40, 0x40, 0x40, 0x43, 0x43, 0x4f, 0x53, 0x47, 0x53, ++ 0x57, 0x4f, 0x4f, 0x5b, 0x5b, 0x53, 0x4f, 0x57, 0x5b, 0x5b, 0x53, 0x43, 0x00, 0x47, 0x4f, 0x53, ++ 0x47, 0x53, 0x57, 0x4f, 0x4f, 0x5b, 0x5b, 0x53, 0x4f, 0x57, 0x5b, 0x5b, 0x53, 0x43, 0x00, 0x47, ++ 0x10, 0x4b, 0x00, 0x40, 0x44, 0x40, 0x43, 0x07, 0x43, 0x00, 0x00, 0x4f, 0x47, 0x1b, 0x0f, 0x4b, ++ 0x14, 0x07, 0x40, 0x1b, 0x0f, 0x4b, 0x14, 0x07, 0x40, 0x1b, 0x0f, 0x4b, 0x14, 0x07, 0x40, 0x44, ++ 0x07, 0x04, 0x04, 0x08, 0x10, 0x08, 0x10, 0x13, 0x17, 0x0f, 0x4b, 0x17, 0x0f, 0x4b, 0x40, 0x40, ++ 0x40, 0x23, 0x13, 0x13, 0x40, 0x0f, 0x13, 0x17, 0x17, 0x24, 0x27, 0x14, 0x07, 0x10, 0x14, 0x08, ++ 0x03, 0x3e, 0x1b, 0x13, 0x40, 0x0f, 0x13, 0x17, 0x04, 0x13, 0x08, 0x04, 0x04, 0x13, 0x40, 0x40, ++ 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x07, 0x3e, 0x05, 0x43, 0x57, 0x40, 0x1a, 0x40, 0x45, 0x24, 0x40, 0x43, 0x40, 0x40, 0x0f, 0x0f, ++ 0x43, 0x52, 0x40, 0x0c, 0x56, 0x52, 0x4d, 0x45, 0x45, 0x07, 0x07, 0x0b, 0x3a, 0x13, 0x08, 0x07, ++ 0x5a, 0x27, 0x01, 0x13, 0x40, 0x03, 0x12, 0x40, 0x40, 0x40, 0x43, 0x43, 0x4f, 0x52, 0x47, 0x52, ++ 0x56, 0x4e, 0x4f, 0x5a, 0x5a, 0x52, 0x4f, 0x57, 0x5a, 0x5a, 0x52, 0x42, 0x00, 0x46, 0x4f, 0x52, ++ 0x47, 0x52, 0x56, 0x4e, 0x4f, 0x5a, 0x5a, 0x52, 0x4f, 0x57, 0x5a, 0x5a, 0x52, 0x42, 0x00, 0x46, ++ 0x10, 0x4b, 0x02, 0x40, 0x44, 0x40, 0x43, 0x07, 0x43, 0x00, 0x00, 0x4d, 0x47, 0x1b, 0x0f, 0x4b, ++ 0x14, 0x07, 0x40, 0x1b, 0x0f, 0x4b, 0x14, 0x07, 0x40, 0x1b, 0x0f, 0x4b, 0x14, 0x07, 0x40, 0x44, ++ 0x07, 0x04, 0x04, 0x08, 0x10, 0x08, 0x10, 0x13, 0x17, 0x0f, 0x4b, 0x17, 0x0f, 0x4b, 0x40, 0x40, ++ 0x40, 0x22, 0x13, 0x13, 0x40, 0x0f, 0x13, 0x17, 0x17, 0x24, 0x27, 0x14, 0x07, 0x10, 0x14, 0x08, ++ 0x03, 0x3e, 0x1b, 0x13, 0x40, 0x0f, 0x13, 0x17, 0x05, 0x13, 0x09, 0x05, 0x05, 0x13, 0x40, 0x40, ++ 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x07, 0x3e, 0x06, 0x43, 0x56, 0x40, 0x19, 0x41, 0x46, 0x24, 0x40, 0x43, 0x40, 0x40, 0x0e, 0x0f, ++ 0x43, 0x50, 0x40, 0x0c, 0x55, 0x50, 0x4b, 0x42, 0x42, 0x07, 0x07, 0x0b, 0x38, 0x13, 0x09, 0x07, ++ 0x59, 0x27, 0x02, 0x13, 0x40, 0x03, 0x11, 0x40, 0x40, 0x40, 0x43, 0x43, 0x4e, 0x51, 0x46, 0x51, ++ 0x55, 0x4d, 0x4e, 0x59, 0x59, 0x50, 0x4e, 0x56, 0x59, 0x59, 0x50, 0x41, 0x01, 0x45, 0x4e, 0x51, ++ 0x46, 0x51, 0x55, 0x4d, 0x4e, 0x59, 0x59, 0x50, 0x4e, 0x56, 0x59, 0x59, 0x50, 0x41, 0x01, 0x45, ++ 0x11, 0x4b, 0x04, 0x40, 0x44, 0x40, 0x43, 0x07, 0x43, 0x01, 0x01, 0x4b, 0x46, 0x1b, 0x0e, 0x4b, ++ 0x14, 0x07, 0x40, 0x1b, 0x0e, 0x4b, 0x14, 0x07, 0x40, 0x1b, 0x0e, 0x4b, 0x14, 0x07, 0x40, 0x44, ++ 0x07, 0x04, 0x04, 0x09, 0x11, 0x09, 0x11, 0x13, 0x17, 0x0e, 0x4b, 0x17, 0x0e, 0x4b, 0x40, 0x40, ++ 0x40, 0x21, 0x13, 0x13, 0x40, 0x0f, 0x13, 0x16, 0x16, 0x24, 0x27, 0x14, 0x07, 0x11, 0x14, 0x09, ++ 0x03, 0x3d, 0x1b, 0x13, 0x40, 0x0f, 0x13, 0x16, 0x06, 0x13, 0x0a, 0x06, 0x06, 0x13, 0x40, 0x40, ++ 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x07, 0x3e, 0x06, 0x43, 0x56, 0x40, 0x18, 0x42, 0x47, 0x24, 0x40, 0x43, 0x40, 0x40, 0x0d, 0x0f, ++ 0x43, 0x4f, 0x40, 0x0c, 0x54, 0x4f, 0x4a, 0x40, 0x40, 0x07, 0x07, 0x0a, 0x36, 0x12, 0x09, 0x07, ++ 0x59, 0x27, 0x03, 0x12, 0x40, 0x02, 0x10, 0x40, 0x40, 0x40, 0x43, 0x43, 0x4e, 0x51, 0x46, 0x51, ++ 0x54, 0x4c, 0x4e, 0x59, 0x59, 0x4f, 0x4e, 0x56, 0x59, 0x59, 0x4f, 0x41, 0x01, 0x44, 0x4e, 0x51, ++ 0x46, 0x51, 0x54, 0x4c, 0x4e, 0x59, 0x59, 0x4f, 0x4e, 0x56, 0x59, 0x59, 0x4f, 0x41, 0x01, 0x44, ++ 0x11, 0x4b, 0x05, 0x40, 0x45, 0x40, 0x43, 0x07, 0x43, 0x01, 0x01, 0x4a, 0x46, 0x1a, 0x0d, 0x4b, ++ 0x14, 0x07, 0x40, 0x1a, 0x0d, 0x4b, 0x14, 0x07, 0x40, 0x1a, 0x0d, 0x4b, 0x14, 0x07, 0x40, 0x45, ++ 0x07, 0x04, 0x04, 0x09, 0x11, 0x09, 0x11, 0x12, 0x17, 0x0d, 0x4b, 0x17, 0x0d, 0x4b, 0x40, 0x40, ++ 0x40, 0x20, 0x12, 0x12, 0x40, 0x0f, 0x12, 0x15, 0x15, 0x24, 0x27, 0x14, 0x07, 0x11, 0x14, 0x09, ++ 0x02, 0x3b, 0x1a, 0x12, 0x40, 0x0f, 0x12, 0x15, 0x06, 0x12, 0x0b, 0x06, 0x06, 0x12, 0x40, 0x40, ++ 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x07, 0x3e, 0x07, 0x42, 0x55, 0x40, 0x18, 0x42, 0x47, 0x25, 0x40, 0x42, 0x40, 0x40, 0x0d, 0x0f, ++ 0x42, 0x4d, 0x40, 0x0d, 0x52, 0x4d, 0x48, 0x02, 0x02, 0x07, 0x07, 0x0a, 0x35, 0x12, 0x0a, 0x07, ++ 0x58, 0x27, 0x05, 0x12, 0x40, 0x02, 0x10, 0x40, 0x40, 0x40, 0x42, 0x42, 0x4d, 0x50, 0x45, 0x50, ++ 0x52, 0x4a, 0x4d, 0x58, 0x58, 0x4d, 0x4d, 0x55, 0x58, 0x58, 0x4d, 0x40, 0x02, 0x42, 0x4d, 0x50, ++ 0x45, 0x50, 0x52, 0x4a, 0x4d, 0x58, 0x58, 0x4d, 0x4d, 0x55, 0x58, 0x58, 0x4d, 0x40, 0x02, 0x42, ++ 0x12, 0x4a, 0x07, 0x40, 0x45, 0x40, 0x42, 0x07, 0x42, 0x02, 0x02, 0x48, 0x45, 0x1a, 0x0d, 0x4a, ++ 0x15, 0x07, 0x40, 0x1a, 0x0d, 0x4a, 0x15, 0x07, 0x40, 0x1a, 0x0d, 0x4a, 0x15, 0x07, 0x40, 0x45, ++ 0x07, 0x05, 0x05, 0x0a, 0x12, 0x0a, 0x12, 0x12, 0x17, 0x0d, 0x4a, 0x17, 0x0d, 0x4a, 0x40, 0x40, ++ 0x40, 0x20, 0x12, 0x12, 0x40, 0x0f, 0x12, 0x15, 0x15, 0x25, 0x27, 0x15, 0x07, 0x12, 0x15, 0x0a, ++ 0x02, 0x3a, 0x1a, 0x12, 0x40, 0x0f, 0x12, 0x15, 0x07, 0x12, 0x0d, 0x07, 0x07, 0x12, 0x40, 0x40, ++ 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x07, 0x3e, 0x08, 0x42, 0x54, 0x40, 0x17, 0x43, 0x48, 0x25, 0x40, 0x42, 0x40, 0x40, 0x0c, 0x0f, ++ 0x42, 0x4b, 0x40, 0x0d, 0x51, 0x4b, 0x46, 0x04, 0x04, 0x07, 0x07, 0x0a, 0x33, 0x12, 0x0b, 0x07, ++ 0x57, 0x27, 0x06, 0x12, 0x40, 0x02, 0x0f, 0x40, 0x40, 0x40, 0x42, 0x42, 0x4c, 0x4f, 0x44, 0x4f, ++ 0x51, 0x49, 0x4c, 0x57, 0x57, 0x4b, 0x4c, 0x54, 0x57, 0x57, 0x4b, 0x00, 0x03, 0x41, 0x4c, 0x4f, ++ 0x44, 0x4f, 0x51, 0x49, 0x4c, 0x57, 0x57, 0x4b, 0x4c, 0x54, 0x57, 0x57, 0x4b, 0x00, 0x03, 0x41, ++ 0x13, 0x4a, 0x09, 0x40, 0x45, 0x40, 0x42, 0x07, 0x42, 0x03, 0x03, 0x46, 0x44, 0x1a, 0x0c, 0x4a, ++ 0x15, 0x07, 0x40, 0x1a, 0x0c, 0x4a, 0x15, 0x07, 0x40, 0x1a, 0x0c, 0x4a, 0x15, 0x07, 0x40, 0x45, ++ 0x07, 0x05, 0x05, 0x0b, 0x13, 0x0b, 0x13, 0x12, 0x17, 0x0c, 0x4a, 0x17, 0x0c, 0x4a, 0x40, 0x40, ++ 0x40, 0x1f, 0x12, 0x12, 0x40, 0x0f, 0x12, 0x14, 0x14, 0x25, 0x27, 0x15, 0x07, 0x13, 0x15, 0x0b, ++ 0x02, 0x39, 0x1a, 0x12, 0x40, 0x0f, 0x12, 0x14, 0x08, 0x12, 0x0e, 0x08, 0x08, 0x12, 0x40, 0x40, ++ 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x07, 0x3e, 0x09, 0x42, 0x54, 0x40, 0x16, 0x43, 0x49, 0x25, 0x40, 0x42, 0x40, 0x40, 0x0c, 0x0f, ++ 0x42, 0x4a, 0x40, 0x0d, 0x50, 0x4a, 0x44, 0x07, 0x07, 0x07, 0x07, 0x0a, 0x32, 0x12, 0x0b, 0x07, ++ 0x56, 0x27, 0x07, 0x12, 0x40, 0x02, 0x0e, 0x40, 0x40, 0x40, 0x42, 0x42, 0x4c, 0x4e, 0x44, 0x4e, ++ 0x50, 0x48, 0x4c, 0x56, 0x56, 0x4a, 0x4c, 0x54, 0x56, 0x56, 0x4a, 0x01, 0x03, 0x40, 0x4c, 0x4e, ++ 0x44, 0x4e, 0x50, 0x48, 0x4c, 0x56, 0x56, 0x4a, 0x4c, 0x54, 0x56, 0x56, 0x4a, 0x01, 0x03, 0x40, ++ 0x13, 0x4a, 0x0b, 0x40, 0x45, 0x40, 0x42, 0x07, 0x42, 0x03, 0x03, 0x44, 0x44, 0x1a, 0x0c, 0x4a, ++ 0x15, 0x07, 0x40, 0x1a, 0x0c, 0x4a, 0x15, 0x07, 0x40, 0x1a, 0x0c, 0x4a, 0x15, 0x07, 0x40, 0x45, ++ 0x07, 0x05, 0x05, 0x0b, 0x13, 0x0b, 0x13, 0x12, 0x17, 0x0c, 0x4a, 0x17, 0x0c, 0x4a, 0x40, 0x40, ++ 0x40, 0x1e, 0x12, 0x12, 0x40, 0x0f, 0x12, 0x14, 0x14, 0x25, 0x27, 0x15, 0x07, 0x13, 0x15, 0x0b, ++ 0x02, 0x38, 0x1a, 0x12, 0x40, 0x0f, 0x12, 0x14, 0x09, 0x12, 0x0f, 0x09, 0x09, 0x12, 0x40, 0x40, ++ 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x07, 0x3e, 0x0a, 0x41, 0x53, 0x40, 0x15, 0x44, 0x4a, 0x26, 0x40, 0x41, 0x40, 0x40, 0x0b, 0x0f, ++ 0x41, 0x48, 0x40, 0x0e, 0x4f, 0x48, 0x42, 0x09, 0x09, 0x07, 0x07, 0x09, 0x30, 0x11, 0x0c, 0x07, ++ 0x55, 0x27, 0x08, 0x11, 0x40, 0x01, 0x0d, 0x40, 0x40, 0x40, 0x41, 0x41, 0x4b, 0x4d, 0x43, 0x4d, ++ 0x4f, 0x47, 0x4b, 0x55, 0x55, 0x48, 0x4b, 0x53, 0x55, 0x55, 0x48, 0x02, 0x04, 0x00, 0x4b, 0x4d, ++ 0x43, 0x4d, 0x4f, 0x47, 0x4b, 0x55, 0x55, 0x48, 0x4b, 0x53, 0x55, 0x55, 0x48, 0x02, 0x04, 0x00, ++ 0x14, 0x49, 0x0d, 0x40, 0x46, 0x40, 0x41, 0x07, 0x41, 0x04, 0x04, 0x42, 0x43, 0x19, 0x0b, 0x49, ++ 0x16, 0x07, 0x40, 0x19, 0x0b, 0x49, 0x16, 0x07, 0x40, 0x19, 0x0b, 0x49, 0x16, 0x07, 0x40, 0x46, ++ 0x07, 0x06, 0x06, 0x0c, 0x14, 0x0c, 0x14, 0x11, 0x17, 0x0b, 0x49, 0x17, 0x0b, 0x49, 0x40, 0x40, ++ 0x40, 0x1d, 0x11, 0x11, 0x40, 0x0f, 0x11, 0x13, 0x13, 0x26, 0x27, 0x16, 0x07, 0x14, 0x16, 0x0c, ++ 0x01, 0x36, 0x19, 0x11, 0x40, 0x0f, 0x11, 0x13, 0x0a, 0x11, 0x10, 0x0a, 0x0a, 0x11, 0x40, 0x40, ++ 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x07, 0x3e, 0x0b, 0x41, 0x52, 0x40, 0x14, 0x45, 0x4b, 0x26, 0x40, 0x41, 0x40, 0x40, 0x0a, 0x0f, ++ 0x41, 0x47, 0x40, 0x0e, 0x4d, 0x47, 0x40, 0x0c, 0x0c, 0x07, 0x07, 0x09, 0x2f, 0x11, 0x0d, 0x07, ++ 0x54, 0x27, 0x0a, 0x11, 0x40, 0x01, 0x0c, 0x40, 0x40, 0x40, 0x41, 0x41, 0x4a, 0x4c, 0x42, 0x4c, ++ 0x4d, 0x45, 0x4a, 0x54, 0x54, 0x47, 0x4a, 0x52, 0x54, 0x54, 0x47, 0x03, 0x05, 0x02, 0x4a, 0x4c, ++ 0x42, 0x4c, 0x4d, 0x45, 0x4a, 0x54, 0x54, 0x47, 0x4a, 0x52, 0x54, 0x54, 0x47, 0x03, 0x05, 0x02, ++ 0x15, 0x49, 0x0f, 0x40, 0x46, 0x40, 0x41, 0x07, 0x41, 0x05, 0x05, 0x40, 0x42, 0x19, 0x0a, 0x49, ++ 0x16, 0x07, 0x40, 0x19, 0x0a, 0x49, 0x16, 0x07, 0x40, 0x19, 0x0a, 0x49, 0x16, 0x07, 0x40, 0x46, ++ 0x07, 0x06, 0x06, 0x0d, 0x15, 0x0d, 0x15, 0x11, 0x17, 0x0a, 0x49, 0x17, 0x0a, 0x49, 0x40, 0x40, ++ 0x40, 0x1c, 0x11, 0x11, 0x40, 0x0f, 0x11, 0x12, 0x12, 0x26, 0x27, 0x16, 0x07, 0x15, 0x16, 0x0d, ++ 0x01, 0x35, 0x19, 0x11, 0x40, 0x0f, 0x11, 0x12, 0x0b, 0x11, 0x12, 0x0b, 0x0b, 0x11, 0x40, 0x40, ++ 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x07, 0x3e, 0x0c, 0x41, 0x52, 0x40, 0x13, 0x45, 0x4c, 0x26, 0x40, 0x41, 0x40, 0x40, 0x0a, 0x0f, ++ 0x41, 0x45, 0x40, 0x0e, 0x4c, 0x45, 0x01, 0x0e, 0x0e, 0x07, 0x07, 0x09, 0x2d, 0x11, 0x0d, 0x07, ++ 0x53, 0x27, 0x0b, 0x11, 0x40, 0x01, 0x0b, 0x40, 0x40, 0x40, 0x41, 0x41, 0x4a, 0x4b, 0x42, 0x4b, ++ 0x4c, 0x44, 0x4a, 0x53, 0x53, 0x45, 0x4a, 0x52, 0x53, 0x53, 0x45, 0x04, 0x05, 0x03, 0x4a, 0x4b, ++ 0x42, 0x4b, 0x4c, 0x44, 0x4a, 0x53, 0x53, 0x45, 0x4a, 0x52, 0x53, 0x53, 0x45, 0x04, 0x05, 0x03, ++ 0x15, 0x49, 0x11, 0x40, 0x46, 0x40, 0x41, 0x07, 0x41, 0x05, 0x05, 0x01, 0x42, 0x19, 0x0a, 0x49, ++ 0x16, 0x07, 0x40, 0x19, 0x0a, 0x49, 0x16, 0x07, 0x40, 0x19, 0x0a, 0x49, 0x16, 0x07, 0x40, 0x46, ++ 0x07, 0x06, 0x06, 0x0d, 0x15, 0x0d, 0x15, 0x11, 0x17, 0x0a, 0x49, 0x17, 0x0a, 0x49, 0x40, 0x40, ++ 0x40, 0x1b, 0x11, 0x11, 0x40, 0x0f, 0x11, 0x12, 0x12, 0x26, 0x27, 0x16, 0x07, 0x15, 0x16, 0x0d, ++ 0x01, 0x34, 0x19, 0x11, 0x40, 0x0f, 0x11, 0x12, 0x0c, 0x11, 0x13, 0x0c, 0x0c, 0x11, 0x40, 0x40, ++ 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x07, 0x3e, 0x0d, 0x40, 0x51, 0x40, 0x12, 0x46, 0x4d, 0x27, 0x40, 0x40, 0x40, 0x40, 0x09, 0x0f, ++ 0x40, 0x44, 0x40, 0x0f, 0x4b, 0x44, 0x03, 0x11, 0x11, 0x07, 0x07, 0x08, 0x2c, 0x10, 0x0e, 0x07, ++ 0x52, 0x27, 0x0c, 0x10, 0x40, 0x00, 0x0a, 0x40, 0x40, 0x40, 0x40, 0x40, 0x49, 0x4a, 0x41, 0x4a, ++ 0x4b, 0x43, 0x49, 0x52, 0x52, 0x44, 0x49, 0x51, 0x52, 0x52, 0x44, 0x05, 0x06, 0x04, 0x49, 0x4a, ++ 0x41, 0x4a, 0x4b, 0x43, 0x49, 0x52, 0x52, 0x44, 0x49, 0x51, 0x52, 0x52, 0x44, 0x05, 0x06, 0x04, ++ 0x16, 0x48, 0x13, 0x40, 0x47, 0x40, 0x40, 0x07, 0x40, 0x06, 0x06, 0x03, 0x41, 0x18, 0x09, 0x48, ++ 0x17, 0x07, 0x40, 0x18, 0x09, 0x48, 0x17, 0x07, 0x40, 0x18, 0x09, 0x48, 0x17, 0x07, 0x40, 0x47, ++ 0x07, 0x07, 0x07, 0x0e, 0x16, 0x0e, 0x16, 0x10, 0x17, 0x09, 0x48, 0x17, 0x09, 0x48, 0x40, 0x40, ++ 0x40, 0x1a, 0x10, 0x10, 0x40, 0x0f, 0x10, 0x11, 0x11, 0x27, 0x27, 0x17, 0x07, 0x16, 0x17, 0x0e, ++ 0x00, 0x33, 0x18, 0x10, 0x40, 0x0f, 0x10, 0x11, 0x0d, 0x10, 0x14, 0x0d, 0x0d, 0x10, 0x40, 0x40, ++ 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x07, 0x3e, 0x0e, 0x40, 0x51, 0x40, 0x11, 0x47, 0x4e, 0x27, 0x40, 0x40, 0x40, 0x40, 0x08, 0x0f, ++ 0x40, 0x42, 0x40, 0x0f, 0x4a, 0x42, 0x04, 0x13, 0x13, 0x07, 0x07, 0x08, 0x2a, 0x10, 0x0e, 0x07, ++ 0x51, 0x27, 0x0d, 0x10, 0x40, 0x00, 0x09, 0x40, 0x40, 0x40, 0x40, 0x40, 0x49, 0x49, 0x41, 0x49, ++ 0x4a, 0x42, 0x49, 0x51, 0x51, 0x42, 0x49, 0x51, 0x51, 0x51, 0x42, 0x06, 0x06, 0x05, 0x49, 0x49, ++ 0x41, 0x49, 0x4a, 0x42, 0x49, 0x51, 0x51, 0x42, 0x49, 0x51, 0x51, 0x51, 0x42, 0x06, 0x06, 0x05, ++ 0x16, 0x48, 0x14, 0x40, 0x47, 0x40, 0x40, 0x07, 0x40, 0x06, 0x06, 0x04, 0x41, 0x18, 0x08, 0x48, ++ 0x17, 0x07, 0x40, 0x18, 0x08, 0x48, 0x17, 0x07, 0x40, 0x18, 0x08, 0x48, 0x17, 0x07, 0x40, 0x47, ++ 0x07, 0x07, 0x07, 0x0e, 0x16, 0x0e, 0x16, 0x10, 0x17, 0x08, 0x48, 0x17, 0x08, 0x48, 0x40, 0x40, ++ 0x40, 0x19, 0x10, 0x10, 0x40, 0x0f, 0x10, 0x10, 0x10, 0x27, 0x27, 0x17, 0x07, 0x16, 0x17, 0x0e, ++ 0x00, 0x31, 0x18, 0x10, 0x40, 0x0f, 0x10, 0x10, 0x0e, 0x10, 0x15, 0x0e, 0x0e, 0x10, 0x40, 0x40, ++ 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x07, 0x3e, 0x0f, 0x40, 0x50, 0x40, 0x10, 0x47, 0x4f, 0x27, 0x40, 0x40, 0x40, 0x40, 0x08, 0x0f, ++ 0x40, 0x40, 0x40, 0x0f, 0x48, 0x40, 0x06, 0x16, 0x16, 0x07, 0x07, 0x08, 0x28, 0x10, 0x0f, 0x07, ++ 0x50, 0x27, 0x0f, 0x10, 0x40, 0x00, 0x08, 0x40, 0x40, 0x40, 0x40, 0x40, 0x48, 0x48, 0x40, 0x48, ++ 0x48, 0x40, 0x48, 0x50, 0x50, 0x40, 0x48, 0x50, 0x50, 0x50, 0x40, 0x07, 0x07, 0x07, 0x48, 0x48, ++ 0x40, 0x48, 0x48, 0x40, 0x48, 0x50, 0x50, 0x40, 0x48, 0x50, 0x50, 0x50, 0x40, 0x07, 0x07, 0x07, ++ 0x17, 0x48, 0x16, 0x40, 0x47, 0x40, 0x40, 0x07, 0x40, 0x07, 0x07, 0x06, 0x40, 0x18, 0x08, 0x48, ++ 0x17, 0x07, 0x40, 0x18, 0x08, 0x48, 0x17, 0x07, 0x40, 0x18, 0x08, 0x48, 0x17, 0x07, 0x40, 0x47, ++ 0x07, 0x07, 0x07, 0x0f, 0x17, 0x0f, 0x17, 0x10, 0x17, 0x08, 0x48, 0x17, 0x08, 0x48, 0x40, 0x40, ++ 0x40, 0x18, 0x10, 0x10, 0x40, 0x0f, 0x10, 0x10, 0x10, 0x27, 0x27, 0x17, 0x07, 0x17, 0x17, 0x0f, ++ 0x00, 0x30, 0x18, 0x10, 0x40, 0x0f, 0x10, 0x10, 0x0f, 0x10, 0x17, 0x0f, 0x0f, 0x10, 0x40, 0x40, ++ 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x07, 0x3e, 0x10, 0x00, 0x4f, 0x40, 0x0f, 0x48, 0x50, 0x28, 0x40, 0x00, 0x40, 0x40, 0x07, 0x0f, ++ 0x00, 0x00, 0x40, 0x10, 0x47, 0x00, 0x08, 0x18, 0x18, 0x07, 0x07, 0x07, 0x27, 0x0f, 0x10, 0x07, ++ 0x4f, 0x27, 0x10, 0x0f, 0x40, 0x40, 0x07, 0x40, 0x40, 0x40, 0x00, 0x00, 0x47, 0x47, 0x00, 0x47, ++ 0x47, 0x00, 0x47, 0x4f, 0x4f, 0x00, 0x47, 0x4f, 0x4f, 0x4f, 0x00, 0x08, 0x08, 0x08, 0x47, 0x47, ++ 0x00, 0x47, 0x47, 0x00, 0x47, 0x4f, 0x4f, 0x00, 0x47, 0x4f, 0x4f, 0x4f, 0x00, 0x08, 0x08, 0x08, ++ 0x18, 0x47, 0x18, 0x40, 0x48, 0x40, 0x00, 0x07, 0x00, 0x08, 0x08, 0x08, 0x00, 0x17, 0x07, 0x47, ++ 0x18, 0x07, 0x40, 0x17, 0x07, 0x47, 0x18, 0x07, 0x40, 0x17, 0x07, 0x47, 0x18, 0x07, 0x40, 0x48, ++ 0x07, 0x08, 0x08, 0x10, 0x18, 0x10, 0x18, 0x0f, 0x17, 0x07, 0x47, 0x17, 0x07, 0x47, 0x40, 0x40, ++ 0x40, 0x17, 0x0f, 0x0f, 0x40, 0x0f, 0x0f, 0x0f, 0x0f, 0x28, 0x27, 0x18, 0x07, 0x18, 0x18, 0x10, ++ 0x40, 0x2f, 0x17, 0x0f, 0x40, 0x0f, 0x0f, 0x0f, 0x10, 0x0f, 0x18, 0x10, 0x10, 0x0f, 0x40, 0x40, ++ 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x07, 0x3e, 0x11, 0x00, 0x4f, 0x40, 0x0e, 0x48, 0x51, 0x28, 0x40, 0x00, 0x40, 0x40, 0x07, 0x0f, ++ 0x00, 0x02, 0x40, 0x10, 0x46, 0x02, 0x0a, 0x1b, 0x1b, 0x07, 0x07, 0x07, 0x25, 0x0f, 0x10, 0x07, ++ 0x4e, 0x27, 0x11, 0x0f, 0x40, 0x40, 0x06, 0x40, 0x40, 0x40, 0x00, 0x00, 0x47, 0x46, 0x00, 0x46, ++ 0x46, 0x01, 0x47, 0x4e, 0x4e, 0x02, 0x47, 0x4f, 0x4e, 0x4e, 0x02, 0x09, 0x08, 0x09, 0x47, 0x46, ++ 0x00, 0x46, 0x46, 0x01, 0x47, 0x4e, 0x4e, 0x02, 0x47, 0x4f, 0x4e, 0x4e, 0x02, 0x09, 0x08, 0x09, ++ 0x18, 0x47, 0x1a, 0x40, 0x48, 0x40, 0x00, 0x07, 0x00, 0x08, 0x08, 0x0a, 0x00, 0x17, 0x07, 0x47, ++ 0x18, 0x07, 0x40, 0x17, 0x07, 0x47, 0x18, 0x07, 0x40, 0x17, 0x07, 0x47, 0x18, 0x07, 0x40, 0x48, ++ 0x07, 0x08, 0x08, 0x10, 0x18, 0x10, 0x18, 0x0f, 0x17, 0x07, 0x47, 0x17, 0x07, 0x47, 0x40, 0x40, ++ 0x40, 0x16, 0x0f, 0x0f, 0x40, 0x0f, 0x0f, 0x0f, 0x0f, 0x28, 0x27, 0x18, 0x07, 0x18, 0x18, 0x10, ++ 0x40, 0x2e, 0x17, 0x0f, 0x40, 0x0f, 0x0f, 0x0f, 0x11, 0x0f, 0x19, 0x11, 0x11, 0x0f, 0x40, 0x40, ++ 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x07, 0x3e, 0x12, 0x00, 0x4e, 0x40, 0x0d, 0x49, 0x52, 0x28, 0x40, 0x00, 0x40, 0x40, 0x06, 0x0f, ++ 0x00, 0x03, 0x40, 0x10, 0x45, 0x03, 0x0c, 0x1d, 0x1d, 0x07, 0x07, 0x07, 0x24, 0x0f, 0x11, 0x07, ++ 0x4d, 0x27, 0x12, 0x0f, 0x40, 0x40, 0x05, 0x40, 0x40, 0x40, 0x00, 0x00, 0x46, 0x45, 0x01, 0x45, ++ 0x45, 0x02, 0x46, 0x4d, 0x4d, 0x03, 0x46, 0x4e, 0x4d, 0x4d, 0x03, 0x0a, 0x09, 0x0a, 0x46, 0x45, ++ 0x01, 0x45, 0x45, 0x02, 0x46, 0x4d, 0x4d, 0x03, 0x46, 0x4e, 0x4d, 0x4d, 0x03, 0x0a, 0x09, 0x0a, ++ 0x19, 0x47, 0x1c, 0x40, 0x48, 0x40, 0x00, 0x07, 0x00, 0x09, 0x09, 0x0c, 0x01, 0x17, 0x06, 0x47, ++ 0x18, 0x07, 0x40, 0x17, 0x06, 0x47, 0x18, 0x07, 0x40, 0x17, 0x06, 0x47, 0x18, 0x07, 0x40, 0x48, ++ 0x07, 0x08, 0x08, 0x11, 0x19, 0x11, 0x19, 0x0f, 0x17, 0x06, 0x47, 0x17, 0x06, 0x47, 0x40, 0x40, ++ 0x40, 0x15, 0x0f, 0x0f, 0x40, 0x0f, 0x0f, 0x0e, 0x0e, 0x28, 0x27, 0x18, 0x07, 0x19, 0x18, 0x11, ++ 0x40, 0x2c, 0x17, 0x0f, 0x40, 0x0f, 0x0f, 0x0e, 0x12, 0x0f, 0x1a, 0x12, 0x12, 0x0f, 0x40, 0x40, ++ 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x07, 0x3e, 0x13, 0x01, 0x4d, 0x40, 0x0c, 0x4a, 0x53, 0x29, 0x40, 0x01, 0x40, 0x40, 0x05, 0x0f, ++ 0x01, 0x05, 0x40, 0x11, 0x43, 0x05, 0x0e, 0x20, 0x20, 0x07, 0x07, 0x06, 0x22, 0x0e, 0x12, 0x07, ++ 0x4c, 0x27, 0x14, 0x0e, 0x40, 0x41, 0x04, 0x40, 0x40, 0x40, 0x01, 0x01, 0x45, 0x44, 0x02, 0x44, ++ 0x43, 0x04, 0x45, 0x4c, 0x4c, 0x05, 0x45, 0x4d, 0x4c, 0x4c, 0x05, 0x0b, 0x0a, 0x0c, 0x45, 0x44, ++ 0x02, 0x44, 0x43, 0x04, 0x45, 0x4c, 0x4c, 0x05, 0x45, 0x4d, 0x4c, 0x4c, 0x05, 0x0b, 0x0a, 0x0c, ++ 0x1a, 0x46, 0x1e, 0x40, 0x49, 0x40, 0x01, 0x07, 0x01, 0x0a, 0x0a, 0x0e, 0x02, 0x16, 0x05, 0x46, ++ 0x19, 0x07, 0x40, 0x16, 0x05, 0x46, 0x19, 0x07, 0x40, 0x16, 0x05, 0x46, 0x19, 0x07, 0x40, 0x49, ++ 0x07, 0x09, 0x09, 0x12, 0x1a, 0x12, 0x1a, 0x0e, 0x17, 0x05, 0x46, 0x17, 0x05, 0x46, 0x40, 0x40, ++ 0x40, 0x14, 0x0e, 0x0e, 0x40, 0x0f, 0x0e, 0x0d, 0x0d, 0x29, 0x27, 0x19, 0x07, 0x1a, 0x19, 0x12, ++ 0x41, 0x2b, 0x16, 0x0e, 0x40, 0x0f, 0x0e, 0x0d, 0x13, 0x0e, 0x1c, 0x13, 0x13, 0x0e, 0x40, 0x40, ++ 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x07, 0x3e, 0x14, 0x01, 0x4d, 0x40, 0x0b, 0x4a, 0x54, 0x29, 0x40, 0x01, 0x40, 0x40, 0x05, 0x0f, ++ 0x01, 0x06, 0x40, 0x11, 0x42, 0x06, 0x10, 0x22, 0x22, 0x07, 0x07, 0x06, 0x21, 0x0e, 0x12, 0x07, ++ 0x4b, 0x27, 0x15, 0x0e, 0x40, 0x41, 0x03, 0x40, 0x40, 0x40, 0x01, 0x01, 0x45, 0x43, 0x02, 0x43, ++ 0x42, 0x05, 0x45, 0x4b, 0x4b, 0x06, 0x45, 0x4d, 0x4b, 0x4b, 0x06, 0x0c, 0x0a, 0x0d, 0x45, 0x43, ++ 0x02, 0x43, 0x42, 0x05, 0x45, 0x4b, 0x4b, 0x06, 0x45, 0x4d, 0x4b, 0x4b, 0x06, 0x0c, 0x0a, 0x0d, ++ 0x1a, 0x46, 0x20, 0x40, 0x49, 0x40, 0x01, 0x07, 0x01, 0x0a, 0x0a, 0x10, 0x02, 0x16, 0x05, 0x46, ++ 0x19, 0x07, 0x40, 0x16, 0x05, 0x46, 0x19, 0x07, 0x40, 0x16, 0x05, 0x46, 0x19, 0x07, 0x40, 0x49, ++ 0x07, 0x09, 0x09, 0x12, 0x1a, 0x12, 0x1a, 0x0e, 0x17, 0x05, 0x46, 0x17, 0x05, 0x46, 0x40, 0x40, ++ 0x40, 0x13, 0x0e, 0x0e, 0x40, 0x0f, 0x0e, 0x0d, 0x0d, 0x29, 0x27, 0x19, 0x07, 0x1a, 0x19, 0x12, ++ 0x41, 0x2a, 0x16, 0x0e, 0x40, 0x0f, 0x0e, 0x0d, 0x14, 0x0e, 0x1d, 0x14, 0x14, 0x0e, 0x40, 0x40, ++ 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x07, 0x3e, 0x15, 0x01, 0x4c, 0x40, 0x0a, 0x4b, 0x55, 0x29, 0x40, 0x01, 0x40, 0x40, 0x04, 0x0f, ++ 0x01, 0x08, 0x40, 0x11, 0x41, 0x08, 0x12, 0x25, 0x25, 0x07, 0x07, 0x06, 0x1f, 0x0e, 0x13, 0x07, ++ 0x4a, 0x27, 0x16, 0x0e, 0x40, 0x41, 0x02, 0x40, 0x40, 0x40, 0x01, 0x01, 0x44, 0x42, 0x03, 0x42, ++ 0x41, 0x06, 0x44, 0x4a, 0x4a, 0x08, 0x44, 0x4c, 0x4a, 0x4a, 0x08, 0x0d, 0x0b, 0x0e, 0x44, 0x42, ++ 0x03, 0x42, 0x41, 0x06, 0x44, 0x4a, 0x4a, 0x08, 0x44, 0x4c, 0x4a, 0x4a, 0x08, 0x0d, 0x0b, 0x0e, ++ 0x1b, 0x46, 0x22, 0x40, 0x49, 0x40, 0x01, 0x07, 0x01, 0x0b, 0x0b, 0x12, 0x03, 0x16, 0x04, 0x46, ++ 0x19, 0x07, 0x40, 0x16, 0x04, 0x46, 0x19, 0x07, 0x40, 0x16, 0x04, 0x46, 0x19, 0x07, 0x40, 0x49, ++ 0x07, 0x09, 0x09, 0x13, 0x1b, 0x13, 0x1b, 0x0e, 0x17, 0x04, 0x46, 0x17, 0x04, 0x46, 0x40, 0x40, ++ 0x40, 0x12, 0x0e, 0x0e, 0x40, 0x0f, 0x0e, 0x0c, 0x0c, 0x29, 0x27, 0x19, 0x07, 0x1b, 0x19, 0x13, ++ 0x41, 0x29, 0x16, 0x0e, 0x40, 0x0f, 0x0e, 0x0c, 0x15, 0x0e, 0x1e, 0x15, 0x15, 0x0e, 0x40, 0x40, ++ 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x07, 0x3e, 0x15, 0x01, 0x4c, 0x40, 0x09, 0x4c, 0x56, 0x29, 0x40, 0x01, 0x40, 0x40, 0x03, 0x0f, ++ 0x01, 0x09, 0x40, 0x11, 0x40, 0x09, 0x13, 0x27, 0x27, 0x07, 0x07, 0x05, 0x1d, 0x0d, 0x13, 0x07, ++ 0x4a, 0x27, 0x17, 0x0d, 0x40, 0x42, 0x01, 0x40, 0x40, 0x40, 0x01, 0x01, 0x44, 0x42, 0x03, 0x42, ++ 0x40, 0x07, 0x44, 0x4a, 0x4a, 0x09, 0x44, 0x4c, 0x4a, 0x4a, 0x09, 0x0d, 0x0b, 0x0f, 0x44, 0x42, ++ 0x03, 0x42, 0x40, 0x07, 0x44, 0x4a, 0x4a, 0x09, 0x44, 0x4c, 0x4a, 0x4a, 0x09, 0x0d, 0x0b, 0x0f, ++ 0x1b, 0x46, 0x23, 0x40, 0x4a, 0x40, 0x01, 0x07, 0x01, 0x0b, 0x0b, 0x13, 0x03, 0x15, 0x03, 0x46, ++ 0x19, 0x07, 0x40, 0x15, 0x03, 0x46, 0x19, 0x07, 0x40, 0x15, 0x03, 0x46, 0x19, 0x07, 0x40, 0x4a, ++ 0x07, 0x09, 0x09, 0x13, 0x1b, 0x13, 0x1b, 0x0d, 0x17, 0x03, 0x46, 0x17, 0x03, 0x46, 0x40, 0x40, ++ 0x40, 0x11, 0x0d, 0x0d, 0x40, 0x0f, 0x0d, 0x0b, 0x0b, 0x29, 0x27, 0x19, 0x07, 0x1b, 0x19, 0x13, ++ 0x42, 0x27, 0x15, 0x0d, 0x40, 0x0f, 0x0d, 0x0b, 0x15, 0x0d, 0x1f, 0x15, 0x15, 0x0d, 0x40, 0x40, ++ 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x07, 0x3e, 0x16, 0x02, 0x4b, 0x40, 0x09, 0x4c, 0x56, 0x2a, 0x40, 0x02, 0x40, 0x40, 0x03, 0x0f, ++ 0x02, 0x0b, 0x40, 0x12, 0x01, 0x0b, 0x15, 0x2a, 0x2a, 0x07, 0x07, 0x05, 0x1c, 0x0d, 0x14, 0x07, ++ 0x49, 0x27, 0x19, 0x0d, 0x40, 0x42, 0x01, 0x40, 0x40, 0x40, 0x02, 0x02, 0x43, 0x41, 0x04, 0x41, ++ 0x01, 0x09, 0x43, 0x49, 0x49, 0x0b, 0x43, 0x4b, 0x49, 0x49, 0x0b, 0x0e, 0x0c, 0x11, 0x43, 0x41, ++ 0x04, 0x41, 0x01, 0x09, 0x43, 0x49, 0x49, 0x0b, 0x43, 0x4b, 0x49, 0x49, 0x0b, 0x0e, 0x0c, 0x11, ++ 0x1c, 0x45, 0x25, 0x40, 0x4a, 0x40, 0x02, 0x07, 0x02, 0x0c, 0x0c, 0x15, 0x04, 0x15, 0x03, 0x45, ++ 0x1a, 0x07, 0x40, 0x15, 0x03, 0x45, 0x1a, 0x07, 0x40, 0x15, 0x03, 0x45, 0x1a, 0x07, 0x40, 0x4a, ++ 0x07, 0x0a, 0x0a, 0x14, 0x1c, 0x14, 0x1c, 0x0d, 0x17, 0x03, 0x45, 0x17, 0x03, 0x45, 0x40, 0x40, ++ 0x40, 0x11, 0x0d, 0x0d, 0x40, 0x0f, 0x0d, 0x0b, 0x0b, 0x2a, 0x27, 0x1a, 0x07, 0x1c, 0x1a, 0x14, ++ 0x42, 0x26, 0x15, 0x0d, 0x40, 0x0f, 0x0d, 0x0b, 0x16, 0x0d, 0x21, 0x16, 0x16, 0x0d, 0x40, 0x40, ++ 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x07, 0x3e, 0x17, 0x02, 0x4a, 0x40, 0x08, 0x4d, 0x57, 0x2a, 0x40, 0x02, 0x40, 0x40, 0x02, 0x0f, ++ 0x02, 0x0d, 0x40, 0x12, 0x02, 0x0d, 0x17, 0x2c, 0x2c, 0x07, 0x07, 0x05, 0x1a, 0x0d, 0x15, 0x07, ++ 0x48, 0x27, 0x1a, 0x0d, 0x40, 0x42, 0x00, 0x40, 0x40, 0x40, 0x02, 0x02, 0x42, 0x40, 0x05, 0x40, ++ 0x02, 0x0a, 0x42, 0x48, 0x48, 0x0d, 0x42, 0x4a, 0x48, 0x48, 0x0d, 0x0f, 0x0d, 0x12, 0x42, 0x40, ++ 0x05, 0x40, 0x02, 0x0a, 0x42, 0x48, 0x48, 0x0d, 0x42, 0x4a, 0x48, 0x48, 0x0d, 0x0f, 0x0d, 0x12, ++ 0x1d, 0x45, 0x27, 0x40, 0x4a, 0x40, 0x02, 0x07, 0x02, 0x0d, 0x0d, 0x17, 0x05, 0x15, 0x02, 0x45, ++ 0x1a, 0x07, 0x40, 0x15, 0x02, 0x45, 0x1a, 0x07, 0x40, 0x15, 0x02, 0x45, 0x1a, 0x07, 0x40, 0x4a, ++ 0x07, 0x0a, 0x0a, 0x15, 0x1d, 0x15, 0x1d, 0x0d, 0x17, 0x02, 0x45, 0x17, 0x02, 0x45, 0x40, 0x40, ++ 0x40, 0x10, 0x0d, 0x0d, 0x40, 0x0f, 0x0d, 0x0a, 0x0a, 0x2a, 0x27, 0x1a, 0x07, 0x1d, 0x1a, 0x15, ++ 0x42, 0x25, 0x15, 0x0d, 0x40, 0x0f, 0x0d, 0x0a, 0x17, 0x0d, 0x22, 0x17, 0x17, 0x0d, 0x40, 0x40, ++ 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x07, 0x3e, 0x18, 0x02, 0x4a, 0x40, 0x07, 0x4d, 0x58, 0x2a, 0x40, 0x02, 0x40, 0x40, 0x02, 0x0f, ++ 0x02, 0x0e, 0x40, 0x12, 0x03, 0x0e, 0x19, 0x2f, 0x2f, 0x07, 0x07, 0x05, 0x19, 0x0d, 0x15, 0x07, ++ 0x47, 0x27, 0x1b, 0x0d, 0x40, 0x42, 0x40, 0x40, 0x40, 0x40, 0x02, 0x02, 0x42, 0x00, 0x05, 0x00, ++ 0x03, 0x0b, 0x42, 0x47, 0x47, 0x0e, 0x42, 0x4a, 0x47, 0x47, 0x0e, 0x10, 0x0d, 0x13, 0x42, 0x00, ++ 0x05, 0x00, 0x03, 0x0b, 0x42, 0x47, 0x47, 0x0e, 0x42, 0x4a, 0x47, 0x47, 0x0e, 0x10, 0x0d, 0x13, ++ 0x1d, 0x45, 0x29, 0x40, 0x4a, 0x40, 0x02, 0x07, 0x02, 0x0d, 0x0d, 0x19, 0x05, 0x15, 0x02, 0x45, ++ 0x1a, 0x07, 0x40, 0x15, 0x02, 0x45, 0x1a, 0x07, 0x40, 0x15, 0x02, 0x45, 0x1a, 0x07, 0x40, 0x4a, ++ 0x07, 0x0a, 0x0a, 0x15, 0x1d, 0x15, 0x1d, 0x0d, 0x17, 0x02, 0x45, 0x17, 0x02, 0x45, 0x40, 0x40, ++ 0x40, 0x0f, 0x0d, 0x0d, 0x40, 0x0f, 0x0d, 0x0a, 0x0a, 0x2a, 0x27, 0x1a, 0x07, 0x1d, 0x1a, 0x15, ++ 0x42, 0x24, 0x15, 0x0d, 0x40, 0x0f, 0x0d, 0x0a, 0x18, 0x0d, 0x23, 0x18, 0x18, 0x0d, 0x40, 0x40, ++ 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x07, 0x3e, 0x19, 0x03, 0x49, 0x40, 0x06, 0x4e, 0x59, 0x2b, 0x40, 0x03, 0x40, 0x40, 0x01, 0x0f, ++ 0x03, 0x10, 0x40, 0x13, 0x04, 0x10, 0x1b, 0x31, 0x31, 0x07, 0x07, 0x04, 0x17, 0x0c, 0x16, 0x07, ++ 0x46, 0x27, 0x1c, 0x0c, 0x40, 0x43, 0x41, 0x40, 0x40, 0x40, 0x03, 0x03, 0x41, 0x01, 0x06, 0x01, ++ 0x04, 0x0c, 0x41, 0x46, 0x46, 0x10, 0x41, 0x49, 0x46, 0x46, 0x10, 0x11, 0x0e, 0x14, 0x41, 0x01, ++ 0x06, 0x01, 0x04, 0x0c, 0x41, 0x46, 0x46, 0x10, 0x41, 0x49, 0x46, 0x46, 0x10, 0x11, 0x0e, 0x14, ++ 0x1e, 0x44, 0x2b, 0x40, 0x4b, 0x40, 0x03, 0x07, 0x03, 0x0e, 0x0e, 0x1b, 0x06, 0x14, 0x01, 0x44, ++ 0x1b, 0x07, 0x40, 0x14, 0x01, 0x44, 0x1b, 0x07, 0x40, 0x14, 0x01, 0x44, 0x1b, 0x07, 0x40, 0x4b, ++ 0x07, 0x0b, 0x0b, 0x16, 0x1e, 0x16, 0x1e, 0x0c, 0x17, 0x01, 0x44, 0x17, 0x01, 0x44, 0x40, 0x40, ++ 0x40, 0x0e, 0x0c, 0x0c, 0x40, 0x0f, 0x0c, 0x09, 0x09, 0x2b, 0x27, 0x1b, 0x07, 0x1e, 0x1b, 0x16, ++ 0x43, 0x22, 0x14, 0x0c, 0x40, 0x0f, 0x0c, 0x09, 0x19, 0x0c, 0x24, 0x19, 0x19, 0x0c, 0x40, 0x40, ++ 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x07, 0x3e, 0x1a, 0x03, 0x48, 0x40, 0x05, 0x4f, 0x5a, 0x2b, 0x40, 0x03, 0x40, 0x40, 0x00, 0x0f, ++ 0x03, 0x11, 0x40, 0x13, 0x06, 0x11, 0x1d, 0x34, 0x34, 0x07, 0x07, 0x04, 0x16, 0x0c, 0x17, 0x07, ++ 0x45, 0x27, 0x1e, 0x0c, 0x40, 0x43, 0x42, 0x40, 0x40, 0x40, 0x03, 0x03, 0x40, 0x02, 0x07, 0x02, ++ 0x06, 0x0e, 0x40, 0x45, 0x45, 0x11, 0x40, 0x48, 0x45, 0x45, 0x11, 0x12, 0x0f, 0x16, 0x40, 0x02, ++ 0x07, 0x02, 0x06, 0x0e, 0x40, 0x45, 0x45, 0x11, 0x40, 0x48, 0x45, 0x45, 0x11, 0x12, 0x0f, 0x16, ++ 0x1f, 0x44, 0x2d, 0x40, 0x4b, 0x40, 0x03, 0x07, 0x03, 0x0f, 0x0f, 0x1d, 0x07, 0x14, 0x00, 0x44, ++ 0x1b, 0x07, 0x40, 0x14, 0x00, 0x44, 0x1b, 0x07, 0x40, 0x14, 0x00, 0x44, 0x1b, 0x07, 0x40, 0x4b, ++ 0x07, 0x0b, 0x0b, 0x17, 0x1f, 0x17, 0x1f, 0x0c, 0x17, 0x00, 0x44, 0x17, 0x00, 0x44, 0x40, 0x40, ++ 0x40, 0x0d, 0x0c, 0x0c, 0x40, 0x0f, 0x0c, 0x08, 0x08, 0x2b, 0x27, 0x1b, 0x07, 0x1f, 0x1b, 0x17, ++ 0x43, 0x21, 0x14, 0x0c, 0x40, 0x0f, 0x0c, 0x08, 0x1a, 0x0c, 0x26, 0x1a, 0x1a, 0x0c, 0x40, 0x40, ++ 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x07, 0x3e, 0x1b, 0x03, 0x48, 0x40, 0x04, 0x4f, 0x5b, 0x2b, 0x40, 0x03, 0x40, 0x40, 0x00, 0x0f, ++ 0x03, 0x13, 0x40, 0x13, 0x07, 0x13, 0x1f, 0x36, 0x36, 0x07, 0x07, 0x04, 0x14, 0x0c, 0x17, 0x07, ++ 0x44, 0x27, 0x1f, 0x0c, 0x40, 0x43, 0x43, 0x40, 0x40, 0x40, 0x03, 0x03, 0x40, 0x03, 0x07, 0x03, ++ 0x07, 0x0f, 0x40, 0x44, 0x44, 0x13, 0x40, 0x48, 0x44, 0x44, 0x13, 0x13, 0x0f, 0x17, 0x40, 0x03, ++ 0x07, 0x03, 0x07, 0x0f, 0x40, 0x44, 0x44, 0x13, 0x40, 0x48, 0x44, 0x44, 0x13, 0x13, 0x0f, 0x17, ++ 0x1f, 0x44, 0x2f, 0x40, 0x4b, 0x40, 0x03, 0x07, 0x03, 0x0f, 0x0f, 0x1f, 0x07, 0x14, 0x00, 0x44, ++ 0x1b, 0x07, 0x40, 0x14, 0x00, 0x44, 0x1b, 0x07, 0x40, 0x14, 0x00, 0x44, 0x1b, 0x07, 0x40, 0x4b, ++ 0x07, 0x0b, 0x0b, 0x17, 0x1f, 0x17, 0x1f, 0x0c, 0x17, 0x00, 0x44, 0x17, 0x00, 0x44, 0x40, 0x40, ++ 0x40, 0x0c, 0x0c, 0x0c, 0x40, 0x0f, 0x0c, 0x08, 0x08, 0x2b, 0x27, 0x1b, 0x07, 0x1f, 0x1b, 0x17, ++ 0x43, 0x20, 0x14, 0x0c, 0x40, 0x0f, 0x0c, 0x08, 0x1b, 0x0c, 0x27, 0x1b, 0x1b, 0x0c, 0x40, 0x40, ++ 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x07, 0x3e, 0x1c, 0x04, 0x47, 0x40, 0x03, 0x50, 0x5c, 0x2c, 0x40, 0x04, 0x40, 0x40, 0x40, 0x0f, ++ 0x04, 0x14, 0x40, 0x14, 0x08, 0x14, 0x21, 0x39, 0x39, 0x07, 0x07, 0x03, 0x13, 0x0b, 0x18, 0x07, ++ 0x43, 0x27, 0x20, 0x0b, 0x40, 0x44, 0x44, 0x40, 0x40, 0x40, 0x04, 0x04, 0x00, 0x04, 0x08, 0x04, ++ 0x08, 0x10, 0x00, 0x43, 0x43, 0x14, 0x00, 0x47, 0x43, 0x43, 0x14, 0x14, 0x10, 0x18, 0x00, 0x04, ++ 0x08, 0x04, 0x08, 0x10, 0x00, 0x43, 0x43, 0x14, 0x00, 0x47, 0x43, 0x43, 0x14, 0x14, 0x10, 0x18, ++ 0x20, 0x43, 0x31, 0x40, 0x4c, 0x40, 0x04, 0x07, 0x04, 0x10, 0x10, 0x21, 0x08, 0x13, 0x40, 0x43, ++ 0x1c, 0x07, 0x40, 0x13, 0x40, 0x43, 0x1c, 0x07, 0x40, 0x13, 0x40, 0x43, 0x1c, 0x07, 0x40, 0x4c, ++ 0x07, 0x0c, 0x0c, 0x18, 0x20, 0x18, 0x20, 0x0b, 0x17, 0x40, 0x43, 0x17, 0x40, 0x43, 0x40, 0x40, ++ 0x40, 0x0b, 0x0b, 0x0b, 0x40, 0x0f, 0x0b, 0x07, 0x07, 0x2c, 0x27, 0x1c, 0x07, 0x20, 0x1c, 0x18, ++ 0x44, 0x1f, 0x13, 0x0b, 0x40, 0x0f, 0x0b, 0x07, 0x1c, 0x0b, 0x28, 0x1c, 0x1c, 0x0b, 0x40, 0x40, ++ 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x07, 0x3e, 0x1d, 0x04, 0x47, 0x40, 0x02, 0x51, 0x5d, 0x2c, 0x40, 0x04, 0x40, 0x40, 0x41, 0x0f, ++ 0x04, 0x16, 0x40, 0x14, 0x09, 0x16, 0x22, 0x3b, 0x3b, 0x07, 0x07, 0x03, 0x11, 0x0b, 0x18, 0x07, ++ 0x42, 0x27, 0x21, 0x0b, 0x40, 0x44, 0x45, 0x40, 0x40, 0x40, 0x04, 0x04, 0x00, 0x05, 0x08, 0x05, ++ 0x09, 0x11, 0x00, 0x42, 0x42, 0x16, 0x00, 0x47, 0x42, 0x42, 0x16, 0x15, 0x10, 0x19, 0x00, 0x05, ++ 0x08, 0x05, 0x09, 0x11, 0x00, 0x42, 0x42, 0x16, 0x00, 0x47, 0x42, 0x42, 0x16, 0x15, 0x10, 0x19, ++ 0x20, 0x43, 0x32, 0x40, 0x4c, 0x40, 0x04, 0x07, 0x04, 0x10, 0x10, 0x22, 0x08, 0x13, 0x41, 0x43, ++ 0x1c, 0x07, 0x40, 0x13, 0x41, 0x43, 0x1c, 0x07, 0x40, 0x13, 0x41, 0x43, 0x1c, 0x07, 0x40, 0x4c, ++ 0x07, 0x0c, 0x0c, 0x18, 0x20, 0x18, 0x20, 0x0b, 0x17, 0x41, 0x43, 0x17, 0x41, 0x43, 0x40, 0x40, ++ 0x40, 0x0a, 0x0b, 0x0b, 0x40, 0x0f, 0x0b, 0x06, 0x06, 0x2c, 0x27, 0x1c, 0x07, 0x20, 0x1c, 0x18, ++ 0x44, 0x1d, 0x13, 0x0b, 0x40, 0x0f, 0x0b, 0x06, 0x1d, 0x0b, 0x29, 0x1d, 0x1d, 0x0b, 0x40, 0x40, ++ 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x07, 0x3e, 0x1e, 0x04, 0x46, 0x40, 0x01, 0x51, 0x5e, 0x2c, 0x40, 0x04, 0x40, 0x40, 0x41, 0x0f, ++ 0x04, 0x18, 0x40, 0x14, 0x0b, 0x18, 0x24, 0x3e, 0x3e, 0x07, 0x07, 0x03, 0x0f, 0x0b, 0x19, 0x07, ++ 0x41, 0x27, 0x23, 0x0b, 0x40, 0x44, 0x46, 0x40, 0x40, 0x40, 0x04, 0x04, 0x01, 0x06, 0x09, 0x06, ++ 0x0b, 0x13, 0x01, 0x41, 0x41, 0x18, 0x01, 0x46, 0x41, 0x41, 0x18, 0x16, 0x11, 0x1b, 0x01, 0x06, ++ 0x09, 0x06, 0x0b, 0x13, 0x01, 0x41, 0x41, 0x18, 0x01, 0x46, 0x41, 0x41, 0x18, 0x16, 0x11, 0x1b, ++ 0x21, 0x43, 0x34, 0x40, 0x4c, 0x40, 0x04, 0x07, 0x04, 0x11, 0x11, 0x24, 0x09, 0x13, 0x41, 0x43, ++ 0x1c, 0x07, 0x40, 0x13, 0x41, 0x43, 0x1c, 0x07, 0x40, 0x13, 0x41, 0x43, 0x1c, 0x07, 0x40, 0x4c, ++ 0x07, 0x0c, 0x0c, 0x19, 0x21, 0x19, 0x21, 0x0b, 0x17, 0x41, 0x43, 0x17, 0x41, 0x43, 0x40, 0x40, ++ 0x40, 0x09, 0x0b, 0x0b, 0x40, 0x0f, 0x0b, 0x06, 0x06, 0x2c, 0x27, 0x1c, 0x07, 0x21, 0x1c, 0x19, ++ 0x44, 0x1c, 0x13, 0x0b, 0x40, 0x0f, 0x0b, 0x06, 0x1e, 0x0b, 0x2b, 0x1e, 0x1e, 0x0b, 0x40, 0x40, ++ 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x07, 0x3e, 0x1f, 0x05, 0x45, 0x40, 0x00, 0x52, 0x5f, 0x2d, 0x40, 0x05, 0x40, 0x40, 0x42, 0x0f, ++ 0x05, 0x19, 0x40, 0x15, 0x0c, 0x19, 0x26, 0x3e, 0x3e, 0x07, 0x07, 0x02, 0x0e, 0x0a, 0x1a, 0x07, ++ 0x40, 0x27, 0x24, 0x0a, 0x40, 0x45, 0x47, 0x40, 0x40, 0x40, 0x05, 0x05, 0x02, 0x07, 0x0a, 0x07, ++ 0x0c, 0x14, 0x02, 0x40, 0x40, 0x19, 0x02, 0x45, 0x40, 0x40, 0x19, 0x17, 0x12, 0x1c, 0x02, 0x07, ++ 0x0a, 0x07, 0x0c, 0x14, 0x02, 0x40, 0x40, 0x19, 0x02, 0x45, 0x40, 0x40, 0x19, 0x17, 0x12, 0x1c, ++ 0x22, 0x42, 0x36, 0x40, 0x4d, 0x40, 0x05, 0x07, 0x05, 0x12, 0x12, 0x26, 0x0a, 0x12, 0x42, 0x42, ++ 0x1d, 0x07, 0x40, 0x12, 0x42, 0x42, 0x1d, 0x07, 0x40, 0x12, 0x42, 0x42, 0x1d, 0x07, 0x40, 0x4d, ++ 0x07, 0x0d, 0x0d, 0x1a, 0x22, 0x1a, 0x22, 0x0a, 0x17, 0x42, 0x42, 0x17, 0x42, 0x42, 0x40, 0x40, ++ 0x40, 0x08, 0x0a, 0x0a, 0x40, 0x0f, 0x0a, 0x05, 0x05, 0x2d, 0x27, 0x1d, 0x07, 0x22, 0x1d, 0x1a, ++ 0x45, 0x1b, 0x12, 0x0a, 0x40, 0x0f, 0x0a, 0x05, 0x1f, 0x0a, 0x2c, 0x1f, 0x1f, 0x0a, 0x40, 0x40, ++ 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x07, 0x3e, 0x20, 0x05, 0x45, 0x40, 0x40, 0x52, 0x60, 0x2d, 0x40, 0x05, 0x40, 0x40, 0x42, 0x0f, ++ 0x05, 0x1b, 0x40, 0x15, 0x0d, 0x1b, 0x28, 0x3e, 0x3e, 0x07, 0x07, 0x02, 0x0c, 0x0a, 0x1a, 0x07, ++ 0x00, 0x27, 0x25, 0x0a, 0x40, 0x45, 0x48, 0x40, 0x40, 0x40, 0x05, 0x05, 0x02, 0x08, 0x0a, 0x08, ++ 0x0d, 0x15, 0x02, 0x00, 0x00, 0x1b, 0x02, 0x45, 0x00, 0x00, 0x1b, 0x18, 0x12, 0x1d, 0x02, 0x08, ++ 0x0a, 0x08, 0x0d, 0x15, 0x02, 0x00, 0x00, 0x1b, 0x02, 0x45, 0x00, 0x00, 0x1b, 0x18, 0x12, 0x1d, ++ 0x22, 0x42, 0x38, 0x40, 0x4d, 0x40, 0x05, 0x07, 0x05, 0x12, 0x12, 0x28, 0x0a, 0x12, 0x42, 0x42, ++ 0x1d, 0x07, 0x40, 0x12, 0x42, 0x42, 0x1d, 0x07, 0x40, 0x12, 0x42, 0x42, 0x1d, 0x07, 0x40, 0x4d, ++ 0x07, 0x0d, 0x0d, 0x1a, 0x22, 0x1a, 0x22, 0x0a, 0x17, 0x42, 0x42, 0x17, 0x42, 0x42, 0x40, 0x40, ++ 0x40, 0x07, 0x0a, 0x0a, 0x40, 0x0f, 0x0a, 0x05, 0x05, 0x2d, 0x27, 0x1d, 0x07, 0x22, 0x1d, 0x1a, ++ 0x45, 0x1a, 0x12, 0x0a, 0x40, 0x0f, 0x0a, 0x05, 0x20, 0x0a, 0x2d, 0x20, 0x20, 0x0a, 0x40, 0x40, ++ 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x07, 0x3e, 0x21, 0x05, 0x44, 0x40, 0x41, 0x53, 0x61, 0x2d, 0x40, 0x05, 0x40, 0x40, 0x43, 0x0f, ++ 0x05, 0x1c, 0x40, 0x15, 0x0e, 0x1c, 0x2a, 0x3e, 0x3e, 0x07, 0x07, 0x02, 0x0b, 0x0a, 0x1b, 0x07, ++ 0x01, 0x27, 0x26, 0x0a, 0x40, 0x45, 0x49, 0x40, 0x40, 0x40, 0x05, 0x05, 0x03, 0x09, 0x0b, 0x09, ++ 0x0e, 0x16, 0x03, 0x01, 0x01, 0x1c, 0x03, 0x44, 0x01, 0x01, 0x1c, 0x19, 0x13, 0x1e, 0x03, 0x09, ++ 0x0b, 0x09, 0x0e, 0x16, 0x03, 0x01, 0x01, 0x1c, 0x03, 0x44, 0x01, 0x01, 0x1c, 0x19, 0x13, 0x1e, ++ 0x23, 0x42, 0x3a, 0x40, 0x4d, 0x40, 0x05, 0x07, 0x05, 0x13, 0x13, 0x2a, 0x0b, 0x12, 0x43, 0x42, ++ 0x1d, 0x07, 0x40, 0x12, 0x43, 0x42, 0x1d, 0x07, 0x40, 0x12, 0x43, 0x42, 0x1d, 0x07, 0x40, 0x4d, ++ 0x07, 0x0d, 0x0d, 0x1b, 0x23, 0x1b, 0x23, 0x0a, 0x17, 0x43, 0x42, 0x17, 0x43, 0x42, 0x40, 0x40, ++ 0x40, 0x06, 0x0a, 0x0a, 0x40, 0x0f, 0x0a, 0x04, 0x04, 0x2d, 0x27, 0x1d, 0x07, 0x23, 0x1d, 0x1b, ++ 0x45, 0x18, 0x12, 0x0a, 0x40, 0x0f, 0x0a, 0x04, 0x21, 0x0a, 0x2e, 0x21, 0x21, 0x0a, 0x40, 0x40, ++ 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x07, 0x3e, 0x22, 0x06, 0x43, 0x40, 0x42, 0x54, 0x62, 0x2e, 0x40, 0x06, 0x40, 0x40, 0x44, 0x0f, ++ 0x06, 0x1e, 0x40, 0x16, 0x10, 0x1e, 0x2c, 0x3e, 0x3e, 0x07, 0x07, 0x01, 0x09, 0x09, 0x1c, 0x07, ++ 0x02, 0x27, 0x28, 0x09, 0x40, 0x46, 0x4a, 0x40, 0x40, 0x40, 0x06, 0x06, 0x04, 0x0a, 0x0c, 0x0a, ++ 0x10, 0x18, 0x04, 0x02, 0x02, 0x1e, 0x04, 0x43, 0x02, 0x02, 0x1e, 0x1a, 0x14, 0x20, 0x04, 0x0a, ++ 0x0c, 0x0a, 0x10, 0x18, 0x04, 0x02, 0x02, 0x1e, 0x04, 0x43, 0x02, 0x02, 0x1e, 0x1a, 0x14, 0x20, ++ 0x24, 0x41, 0x3c, 0x40, 0x4e, 0x40, 0x06, 0x07, 0x06, 0x14, 0x14, 0x2c, 0x0c, 0x11, 0x44, 0x41, ++ 0x1e, 0x07, 0x40, 0x11, 0x44, 0x41, 0x1e, 0x07, 0x40, 0x11, 0x44, 0x41, 0x1e, 0x07, 0x40, 0x4e, ++ 0x07, 0x0e, 0x0e, 0x1c, 0x24, 0x1c, 0x24, 0x09, 0x17, 0x44, 0x41, 0x17, 0x44, 0x41, 0x40, 0x40, ++ 0x40, 0x05, 0x09, 0x09, 0x40, 0x0f, 0x09, 0x03, 0x03, 0x2e, 0x27, 0x1e, 0x07, 0x24, 0x1e, 0x1c, ++ 0x46, 0x17, 0x11, 0x09, 0x40, 0x0f, 0x09, 0x03, 0x22, 0x09, 0x30, 0x22, 0x22, 0x09, 0x40, 0x40, ++ 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x07, 0x3e, 0x23, 0x06, 0x43, 0x40, 0x43, 0x54, 0x63, 0x2e, 0x40, 0x06, 0x40, 0x40, 0x44, 0x0f, ++ 0x06, 0x1f, 0x40, 0x16, 0x11, 0x1f, 0x2e, 0x3e, 0x3e, 0x07, 0x07, 0x01, 0x08, 0x09, 0x1c, 0x07, ++ 0x03, 0x27, 0x29, 0x09, 0x40, 0x46, 0x4b, 0x40, 0x40, 0x40, 0x06, 0x06, 0x04, 0x0b, 0x0c, 0x0b, ++ 0x11, 0x19, 0x04, 0x03, 0x03, 0x1f, 0x04, 0x43, 0x03, 0x03, 0x1f, 0x1b, 0x14, 0x21, 0x04, 0x0b, ++ 0x0c, 0x0b, 0x11, 0x19, 0x04, 0x03, 0x03, 0x1f, 0x04, 0x43, 0x03, 0x03, 0x1f, 0x1b, 0x14, 0x21, ++ 0x24, 0x41, 0x3e, 0x40, 0x4e, 0x40, 0x06, 0x07, 0x06, 0x14, 0x14, 0x2e, 0x0c, 0x11, 0x44, 0x41, ++ 0x1e, 0x07, 0x40, 0x11, 0x44, 0x41, 0x1e, 0x07, 0x40, 0x11, 0x44, 0x41, 0x1e, 0x07, 0x40, 0x4e, ++ 0x07, 0x0e, 0x0e, 0x1c, 0x24, 0x1c, 0x24, 0x09, 0x17, 0x44, 0x41, 0x17, 0x44, 0x41, 0x40, 0x40, ++ 0x40, 0x04, 0x09, 0x09, 0x40, 0x0f, 0x09, 0x03, 0x03, 0x2e, 0x27, 0x1e, 0x07, 0x24, 0x1e, 0x1c, ++ 0x46, 0x16, 0x11, 0x09, 0x40, 0x0f, 0x09, 0x03, 0x23, 0x09, 0x31, 0x23, 0x23, 0x09, 0x40, 0x40, ++ 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x07, 0x3e, 0x24, 0x06, 0x42, 0x40, 0x44, 0x55, 0x64, 0x2e, 0x40, 0x06, 0x40, 0x40, 0x45, 0x0f, ++ 0x06, 0x21, 0x40, 0x16, 0x12, 0x21, 0x30, 0x3e, 0x3e, 0x07, 0x07, 0x01, 0x06, 0x09, 0x1d, 0x07, ++ 0x04, 0x27, 0x2a, 0x09, 0x40, 0x46, 0x4c, 0x40, 0x40, 0x40, 0x06, 0x06, 0x05, 0x0c, 0x0d, 0x0c, ++ 0x12, 0x1a, 0x05, 0x04, 0x04, 0x21, 0x05, 0x42, 0x04, 0x04, 0x21, 0x1c, 0x15, 0x22, 0x05, 0x0c, ++ 0x0d, 0x0c, 0x12, 0x1a, 0x05, 0x04, 0x04, 0x21, 0x05, 0x42, 0x04, 0x04, 0x21, 0x1c, 0x15, 0x22, ++ 0x25, 0x41, 0x3e, 0x40, 0x4e, 0x40, 0x06, 0x07, 0x06, 0x15, 0x15, 0x30, 0x0d, 0x11, 0x45, 0x41, ++ 0x1e, 0x07, 0x40, 0x11, 0x45, 0x41, 0x1e, 0x07, 0x40, 0x11, 0x45, 0x41, 0x1e, 0x07, 0x40, 0x4e, ++ 0x07, 0x0e, 0x0e, 0x1d, 0x25, 0x1d, 0x25, 0x09, 0x17, 0x45, 0x41, 0x17, 0x45, 0x41, 0x40, 0x40, ++ 0x40, 0x03, 0x09, 0x09, 0x40, 0x0f, 0x09, 0x02, 0x02, 0x2e, 0x27, 0x1e, 0x07, 0x25, 0x1e, 0x1d, ++ 0x46, 0x15, 0x11, 0x09, 0x40, 0x0f, 0x09, 0x02, 0x24, 0x09, 0x32, 0x24, 0x24, 0x09, 0x40, 0x40, ++ 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x07, 0x3e, 0x24, 0x06, 0x42, 0x40, 0x45, 0x56, 0x65, 0x2e, 0x40, 0x06, 0x40, 0x40, 0x46, 0x0f, ++ 0x06, 0x22, 0x40, 0x16, 0x13, 0x22, 0x31, 0x3e, 0x3e, 0x07, 0x07, 0x00, 0x04, 0x08, 0x1d, 0x07, ++ 0x04, 0x27, 0x2b, 0x08, 0x40, 0x47, 0x4d, 0x40, 0x40, 0x40, 0x06, 0x06, 0x05, 0x0c, 0x0d, 0x0c, ++ 0x13, 0x1b, 0x05, 0x04, 0x04, 0x22, 0x05, 0x42, 0x04, 0x04, 0x22, 0x1c, 0x15, 0x23, 0x05, 0x0c, ++ 0x0d, 0x0c, 0x13, 0x1b, 0x05, 0x04, 0x04, 0x22, 0x05, 0x42, 0x04, 0x04, 0x22, 0x1c, 0x15, 0x23, ++ 0x25, 0x41, 0x3e, 0x40, 0x4f, 0x40, 0x06, 0x07, 0x06, 0x15, 0x15, 0x31, 0x0d, 0x10, 0x46, 0x41, ++ 0x1e, 0x07, 0x40, 0x10, 0x46, 0x41, 0x1e, 0x07, 0x40, 0x10, 0x46, 0x41, 0x1e, 0x07, 0x40, 0x4f, ++ 0x07, 0x0e, 0x0e, 0x1d, 0x25, 0x1d, 0x25, 0x08, 0x17, 0x46, 0x41, 0x17, 0x46, 0x41, 0x40, 0x40, ++ 0x40, 0x02, 0x08, 0x08, 0x40, 0x0f, 0x08, 0x01, 0x01, 0x2e, 0x27, 0x1e, 0x07, 0x25, 0x1e, 0x1d, ++ 0x47, 0x13, 0x10, 0x08, 0x40, 0x0f, 0x08, 0x01, 0x24, 0x08, 0x33, 0x24, 0x24, 0x08, 0x40, 0x40, ++ 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x07, 0x3e, 0x25, 0x07, 0x41, 0x40, 0x45, 0x56, 0x65, 0x2f, 0x40, 0x07, 0x40, 0x40, 0x46, 0x0f, ++ 0x07, 0x24, 0x40, 0x17, 0x15, 0x24, 0x33, 0x3e, 0x3e, 0x07, 0x07, 0x00, 0x03, 0x08, 0x1e, 0x07, ++ 0x05, 0x27, 0x2d, 0x08, 0x40, 0x47, 0x4d, 0x40, 0x40, 0x40, 0x07, 0x07, 0x06, 0x0d, 0x0e, 0x0d, ++ 0x15, 0x1d, 0x06, 0x05, 0x05, 0x24, 0x06, 0x41, 0x05, 0x05, 0x24, 0x1d, 0x16, 0x25, 0x06, 0x0d, ++ 0x0e, 0x0d, 0x15, 0x1d, 0x06, 0x05, 0x05, 0x24, 0x06, 0x41, 0x05, 0x05, 0x24, 0x1d, 0x16, 0x25, ++ 0x26, 0x40, 0x3e, 0x40, 0x4f, 0x40, 0x07, 0x07, 0x07, 0x16, 0x16, 0x33, 0x0e, 0x10, 0x46, 0x40, ++ 0x1f, 0x07, 0x40, 0x10, 0x46, 0x40, 0x1f, 0x07, 0x40, 0x10, 0x46, 0x40, 0x1f, 0x07, 0x40, 0x4f, ++ 0x07, 0x0f, 0x0f, 0x1e, 0x26, 0x1e, 0x26, 0x08, 0x17, 0x46, 0x40, 0x17, 0x46, 0x40, 0x40, 0x40, ++ 0x40, 0x02, 0x08, 0x08, 0x40, 0x0f, 0x08, 0x01, 0x01, 0x2f, 0x27, 0x1f, 0x07, 0x26, 0x1f, 0x1e, ++ 0x47, 0x12, 0x10, 0x08, 0x40, 0x0f, 0x08, 0x01, 0x25, 0x08, 0x35, 0x25, 0x25, 0x08, 0x40, 0x40, ++ 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x07, 0x3e, 0x26, 0x07, 0x40, 0x40, 0x46, 0x57, 0x66, 0x2f, 0x40, 0x07, 0x40, 0x40, 0x47, 0x0f, ++ 0x07, 0x26, 0x40, 0x17, 0x16, 0x26, 0x35, 0x3e, 0x3e, 0x07, 0x07, 0x00, 0x01, 0x08, 0x1f, 0x07, ++ 0x06, 0x27, 0x2e, 0x08, 0x40, 0x47, 0x4e, 0x40, 0x40, 0x40, 0x07, 0x07, 0x07, 0x0e, 0x0f, 0x0e, ++ 0x16, 0x1e, 0x07, 0x06, 0x06, 0x26, 0x07, 0x40, 0x06, 0x06, 0x26, 0x1e, 0x17, 0x26, 0x07, 0x0e, ++ 0x0f, 0x0e, 0x16, 0x1e, 0x07, 0x06, 0x06, 0x26, 0x07, 0x40, 0x06, 0x06, 0x26, 0x1e, 0x17, 0x26, ++ 0x27, 0x40, 0x3e, 0x40, 0x4f, 0x40, 0x07, 0x07, 0x07, 0x17, 0x17, 0x35, 0x0f, 0x10, 0x47, 0x40, ++ 0x1f, 0x07, 0x40, 0x10, 0x47, 0x40, 0x1f, 0x07, 0x40, 0x10, 0x47, 0x40, 0x1f, 0x07, 0x40, 0x4f, ++ 0x07, 0x0f, 0x0f, 0x1f, 0x27, 0x1f, 0x27, 0x08, 0x17, 0x47, 0x40, 0x17, 0x47, 0x40, 0x40, 0x40, ++ 0x40, 0x01, 0x08, 0x08, 0x40, 0x0f, 0x08, 0x00, 0x00, 0x2f, 0x27, 0x1f, 0x07, 0x27, 0x1f, 0x1f, ++ 0x47, 0x11, 0x10, 0x08, 0x40, 0x0f, 0x08, 0x00, 0x26, 0x08, 0x36, 0x26, 0x26, 0x08, 0x40, 0x40, ++ 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x07, 0x3e, 0x27, 0x07, 0x40, 0x40, 0x47, 0x57, 0x67, 0x2f, 0x40, 0x07, 0x40, 0x40, 0x47, 0x0f, ++ 0x07, 0x27, 0x40, 0x17, 0x17, 0x27, 0x37, 0x3e, 0x3e, 0x07, 0x07, 0x00, 0x00, 0x08, 0x1f, 0x07, ++ 0x07, 0x27, 0x2f, 0x08, 0x40, 0x47, 0x4f, 0x40, 0x40, 0x40, 0x07, 0x07, 0x07, 0x0f, 0x0f, 0x0f, ++ 0x17, 0x1f, 0x07, 0x07, 0x07, 0x27, 0x07, 0x40, 0x07, 0x07, 0x27, 0x1f, 0x17, 0x27, 0x07, 0x0f, ++ 0x0f, 0x0f, 0x17, 0x1f, 0x07, 0x07, 0x07, 0x27, 0x07, 0x40, 0x07, 0x07, 0x27, 0x1f, 0x17, 0x27, ++ 0x27, 0x40, 0x3e, 0x40, 0x4f, 0x40, 0x07, 0x07, 0x07, 0x17, 0x17, 0x37, 0x0f, 0x10, 0x47, 0x40, ++ 0x1f, 0x07, 0x40, 0x10, 0x47, 0x40, 0x1f, 0x07, 0x40, 0x10, 0x47, 0x40, 0x1f, 0x07, 0x40, 0x4f, ++ 0x07, 0x0f, 0x0f, 0x1f, 0x27, 0x1f, 0x27, 0x08, 0x17, 0x47, 0x40, 0x17, 0x47, 0x40, 0x40, 0x40, ++ 0x40, 0x00, 0x08, 0x08, 0x40, 0x0f, 0x08, 0x00, 0x00, 0x2f, 0x27, 0x1f, 0x07, 0x27, 0x1f, 0x1f, ++ 0x47, 0x10, 0x10, 0x08, 0x40, 0x0f, 0x08, 0x00, 0x27, 0x08, 0x37, 0x27, 0x27, 0x08, 0x40, 0x40, ++ 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++}; ++ ++static void set_ps_field(u32 *buf, struct rkvdec_ps_field field, u32 value) ++{ ++ u8 bit = field.offset % 32, word = field.offset / 32; ++ u64 mask = GENMASK_ULL(bit + field.len - 1, bit); ++ u64 val = ((u64)value << bit) & mask; ++ ++ buf[word] &= ~mask; ++ buf[word] |= val; ++ if (bit + field.len > 32) { ++ buf[word + 1] &= ~(mask >> 32); ++ buf[word + 1] |= val >> 32; ++ } ++} ++ ++static void assemble_hw_pps(struct rkvdec_ctx *ctx, ++ struct rkvdec_hevc_run *run) ++{ ++ struct rkvdec_hevc_ctx *hevc_ctx = ctx->priv; ++ const struct v4l2_ctrl_hevc_sps *sps = run->sps; ++ const struct v4l2_ctrl_hevc_pps *pps = run->pps; ++ struct rkvdec_hevc_priv_tbl *priv_tbl = hevc_ctx->priv_tbl.cpu; ++ struct rkvdec_sps_pps_packet *hw_ps; ++ u32 min_cb_log2_size_y, ctb_log2_size_y, ctb_size_y; ++ u32 log2_min_cu_qp_delta_size; ++ dma_addr_t scaling_list_address; ++ u32 scaling_distance; ++ int i; ++ ++ /* ++ * HW read the SPS/PPS information from PPS packet index by PPS id. ++ * offset from the base can be calculated by PPS_id * 80 (size per PPS ++ * packet unit). so the driver copy SPS/PPS information to the exact PPS ++ * packet unit for HW accessing. ++ */ ++ hw_ps = &priv_tbl->param_set[pps->pic_parameter_set_id]; ++ memset(hw_ps, 0, sizeof(*hw_ps)); ++ ++ min_cb_log2_size_y = sps->log2_min_luma_coding_block_size_minus3 + 3; ++ ctb_log2_size_y = min_cb_log2_size_y + ++ sps->log2_diff_max_min_luma_coding_block_size; ++ ctb_size_y = 1 << ctb_log2_size_y; ++ ++#define WRITE_PPS(value, field) set_ps_field(hw_ps->info, field, value) ++ /* write sps */ ++ WRITE_PPS(sps->video_parameter_set_id, VIDEO_PARAMETER_SET_ID); ++ WRITE_PPS(sps->seq_parameter_set_id, SEQ_PARAMETER_SET_ID); ++ WRITE_PPS(sps->chroma_format_idc, CHROMA_FORMAT_IDC); ++ WRITE_PPS(sps->pic_width_in_luma_samples, PIC_WIDTH_IN_LUMA_SAMPLES); ++ WRITE_PPS(sps->pic_height_in_luma_samples, PIC_HEIGHT_IN_LUMA_SAMPLES); ++ WRITE_PPS(sps->bit_depth_luma_minus8 + 8, BIT_DEPTH_LUMA); ++ WRITE_PPS(sps->bit_depth_chroma_minus8 + 8, BIT_DEPTH_CHROMA); ++ WRITE_PPS(sps->log2_max_pic_order_cnt_lsb_minus4 + 4, ++ LOG2_MAX_PIC_ORDER_CNT_LSB); ++ WRITE_PPS(sps->log2_diff_max_min_luma_coding_block_size, ++ LOG2_DIFF_MAX_MIN_LUMA_CODING_BLOCK_SIZE); ++ WRITE_PPS(sps->log2_min_luma_coding_block_size_minus3 + 3, ++ LOG2_MIN_LUMA_CODING_BLOCK_SIZE); ++ WRITE_PPS(sps->log2_min_luma_transform_block_size_minus2 + 2, ++ LOG2_MIN_TRANSFORM_BLOCK_SIZE); ++ WRITE_PPS(sps->log2_diff_max_min_luma_transform_block_size, ++ LOG2_DIFF_MAX_MIN_LUMA_TRANSFORM_BLOCK_SIZE); ++ WRITE_PPS(sps->max_transform_hierarchy_depth_inter, ++ MAX_TRANSFORM_HIERARCHY_DEPTH_INTER); ++ WRITE_PPS(sps->max_transform_hierarchy_depth_intra, ++ MAX_TRANSFORM_HIERARCHY_DEPTH_INTRA); ++ WRITE_PPS(!!(sps->flags & V4L2_HEVC_SPS_FLAG_SCALING_LIST_ENABLED), ++ SCALING_LIST_ENABLED_FLAG); ++ WRITE_PPS(!!(sps->flags & V4L2_HEVC_SPS_FLAG_AMP_ENABLED), ++ AMP_ENABLED_FLAG); ++ WRITE_PPS(!!(sps->flags & V4L2_HEVC_SPS_FLAG_SAMPLE_ADAPTIVE_OFFSET), ++ SAMPLE_ADAPTIVE_OFFSET_ENABLED_FLAG); ++ if (sps->flags & V4L2_HEVC_SPS_FLAG_PCM_ENABLED) { ++ WRITE_PPS(1, PCM_ENABLED_FLAG); ++ WRITE_PPS(sps->pcm_sample_bit_depth_luma_minus1 + 1, ++ PCM_SAMPLE_BIT_DEPTH_LUMA); ++ WRITE_PPS(sps->pcm_sample_bit_depth_chroma_minus1 + 1, ++ PCM_SAMPLE_BIT_DEPTH_CHROMA); ++ WRITE_PPS(!!(sps->flags & V4L2_HEVC_SPS_FLAG_PCM_LOOP_FILTER_DISABLED), ++ PCM_LOOP_FILTER_DISABLED_FLAG); ++ WRITE_PPS(sps->log2_diff_max_min_pcm_luma_coding_block_size, ++ LOG2_DIFF_MAX_MIN_PCM_LUMA_CODING_BLOCK_SIZE); ++ WRITE_PPS(sps->log2_min_pcm_luma_coding_block_size_minus3 + 3, ++ LOG2_MIN_PCM_LUMA_CODING_BLOCK_SIZE); ++ } ++ WRITE_PPS(sps->num_short_term_ref_pic_sets, NUM_SHORT_TERM_REF_PIC_SETS); ++ WRITE_PPS(!!(sps->flags & V4L2_HEVC_SPS_FLAG_LONG_TERM_REF_PICS_PRESENT), ++ LONG_TERM_REF_PICS_PRESENT_FLAG); ++ WRITE_PPS(sps->num_long_term_ref_pics_sps, NUM_LONG_TERM_REF_PICS_SPS); ++ WRITE_PPS(!!(sps->flags & V4L2_HEVC_SPS_FLAG_SPS_TEMPORAL_MVP_ENABLED), ++ SPS_TEMPORAL_MVP_ENABLED_FLAG); ++ WRITE_PPS(!!(sps->flags & V4L2_HEVC_SPS_FLAG_STRONG_INTRA_SMOOTHING_ENABLED), ++ STRONG_INTRA_SMOOTHING_ENABLED_FLAG); ++ ++ /* write pps */ ++ WRITE_PPS(pps->pic_parameter_set_id, PIC_PARAMETER_SET_ID); ++ WRITE_PPS(sps->seq_parameter_set_id, PPS_SEQ_PARAMETER_SET_ID); ++ WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_DEPENDENT_SLICE_SEGMENT_ENABLED), ++ DEPENDENT_SLICE_SEGMENTS_ENABLED_FLAG); ++ WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_OUTPUT_FLAG_PRESENT), ++ OUTPUT_FLAG_PRESENT_FLAG); ++ WRITE_PPS(pps->num_extra_slice_header_bits, NUM_EXTRA_SLICE_HEADER_BITS); ++ WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_SIGN_DATA_HIDING_ENABLED), ++ SIGN_DATA_HIDING_ENABLED_FLAG); ++ WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_CABAC_INIT_PRESENT), ++ CABAC_INIT_PRESENT_FLAG); ++ WRITE_PPS(pps->num_ref_idx_l0_default_active_minus1 + 1, ++ NUM_REF_IDX_L0_DEFAULT_ACTIVE); ++ WRITE_PPS(pps->num_ref_idx_l1_default_active_minus1 + 1, ++ NUM_REF_IDX_L1_DEFAULT_ACTIVE); ++ WRITE_PPS(pps->init_qp_minus26, INIT_QP_MINUS26); ++ WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_CONSTRAINED_INTRA_PRED), ++ CONSTRAINED_INTRA_PRED_FLAG); ++ WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_TRANSFORM_SKIP_ENABLED), ++ TRANSFORM_SKIP_ENABLED_FLAG); ++ WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_CU_QP_DELTA_ENABLED), ++ CU_QP_DELTA_ENABLED_FLAG); ++ ++ log2_min_cu_qp_delta_size = ctb_log2_size_y - pps->diff_cu_qp_delta_depth; ++ WRITE_PPS(log2_min_cu_qp_delta_size, LOG2_MIN_CU_QP_DELTA_SIZE); ++ ++ WRITE_PPS(pps->pps_cb_qp_offset, PPS_CB_QP_OFFSET); ++ WRITE_PPS(pps->pps_cr_qp_offset, PPS_CR_QP_OFFSET); ++ WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_PPS_SLICE_CHROMA_QP_OFFSETS_PRESENT), ++ PPS_SLICE_CHROMA_QP_OFFSETS_PRESENT_FLAG); ++ WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_WEIGHTED_PRED), ++ WEIGHTED_PRED_FLAG); ++ WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_WEIGHTED_BIPRED), ++ WEIGHTED_BIPRED_FLAG); ++ WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_TRANSQUANT_BYPASS_ENABLED), ++ TRANSQUANT_BYPASS_ENABLED_FLAG); ++ WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_TILES_ENABLED), ++ TILES_ENABLED_FLAG); ++ WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_ENTROPY_CODING_SYNC_ENABLED), ++ ENTROPY_CODING_SYNC_ENABLED_FLAG); ++ WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_PPS_LOOP_FILTER_ACROSS_SLICES_ENABLED), ++ PPS_LOOP_FILTER_ACROSS_SLICES_ENABLED_FLAG); ++ WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_LOOP_FILTER_ACROSS_TILES_ENABLED), ++ LOOP_FILTER_ACROSS_TILES_ENABLED_FLAG); ++ WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_DEBLOCKING_FILTER_OVERRIDE_ENABLED), ++ DEBLOCKING_FILTER_OVERRIDE_ENABLED_FLAG); ++ WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_PPS_DISABLE_DEBLOCKING_FILTER), ++ PPS_DEBLOCKING_FILTER_DISABLED_FLAG); ++ WRITE_PPS(pps->pps_beta_offset_div2, PPS_BETA_OFFSET_DIV2); ++ WRITE_PPS(pps->pps_tc_offset_div2, PPS_TC_OFFSET_DIV2); ++ WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_LISTS_MODIFICATION_PRESENT), ++ LISTS_MODIFICATION_PRESENT_FLAG); ++ WRITE_PPS(pps->log2_parallel_merge_level_minus2 + 2, LOG2_PARALLEL_MERGE_LEVEL); ++ WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_SLICE_SEGMENT_HEADER_EXTENSION_PRESENT), ++ SLICE_SEGMENT_HEADER_EXTENSION_PRESENT_FLAG); ++ WRITE_PPS(pps->num_tile_columns_minus1 + 1, NUM_TILE_COLUMNS); ++ WRITE_PPS(pps->num_tile_rows_minus1 + 1, NUM_TILE_ROWS); ++ ++ if (pps->flags & V4L2_HEVC_PPS_FLAG_TILES_ENABLED) { ++ for (i = 0; i <= pps->num_tile_columns_minus1; i++) ++ WRITE_PPS(pps->column_width_minus1[i], COLUMN_WIDTH(i)); ++ for (i = 0; i <= pps->num_tile_rows_minus1; i++) ++ WRITE_PPS(pps->row_height_minus1[i], ROW_HEIGHT(i)); ++ } else { ++ WRITE_PPS(((sps->pic_width_in_luma_samples + ctb_size_y - 1) / ctb_size_y) - 1, ++ COLUMN_WIDTH(0)); ++ WRITE_PPS(((sps->pic_height_in_luma_samples + ctb_size_y - 1) / ctb_size_y) - 1, ++ ROW_HEIGHT(0)); ++ } ++ ++ scaling_distance = offsetof(struct rkvdec_hevc_priv_tbl, scaling_list); ++ scaling_list_address = hevc_ctx->priv_tbl.dma + scaling_distance; ++ WRITE_PPS(scaling_list_address, SCALING_LIST_ADDRESS); ++} ++ ++static void assemble_hw_rps(struct rkvdec_ctx *ctx, ++ struct rkvdec_hevc_run *run) ++{ ++ const struct v4l2_ctrl_hevc_decode_params *decode_params = run->decode_params; ++ const struct v4l2_ctrl_hevc_slice_params *sl_params; ++ const struct v4l2_hevc_dpb_entry *dpb; ++ struct rkvdec_hevc_ctx *hevc_ctx = ctx->priv; ++ struct rkvdec_hevc_priv_tbl *priv_tbl = hevc_ctx->priv_tbl.cpu; ++ struct rkvdec_rps_packet *hw_ps; ++ int i, j; ++ unsigned int lowdelay; ++ ++#define WRITE_RPS(value, field) set_ps_field(hw_ps->info, field, value) ++ ++#define REF_PIC_LONG_TERM_L0(i) PS_FIELD(i * 5, 1) ++#define REF_PIC_IDX_L0(i) PS_FIELD(1 + (i * 5), 4) ++#define REF_PIC_LONG_TERM_L1(i) PS_FIELD((i < 5 ? 75 : 132) + (i * 5), 1) ++#define REF_PIC_IDX_L1(i) PS_FIELD((i < 4 ? 76 : 128) + (i * 5), 4) ++ ++#define LOWDELAY PS_FIELD(182, 1) ++#define LONG_TERM_RPS_BIT_OFFSET PS_FIELD(183, 10) ++#define SHORT_TERM_RPS_BIT_OFFSET PS_FIELD(193, 9) ++#define NUM_RPS_POC PS_FIELD(202, 4) ++ ++ for (j = 0; j < run->num_slices; j++) { ++ sl_params = &run->slices_params[j]; ++ dpb = decode_params->dpb; ++ lowdelay = (sl_params->slice_type == V4L2_HEVC_SLICE_TYPE_I) ? 0 : 1; ++ ++ hw_ps = &priv_tbl->rps[j]; ++ memset(hw_ps, 0, sizeof(*hw_ps)); ++ ++ for (i = 0; i <= sl_params->num_ref_idx_l0_active_minus1; i++) { ++ WRITE_RPS(!!(dpb[sl_params->ref_idx_l0[i]].flags & V4L2_HEVC_DPB_ENTRY_LONG_TERM_REFERENCE), ++ REF_PIC_LONG_TERM_L0(i)); ++ WRITE_RPS(sl_params->ref_idx_l0[i], REF_PIC_IDX_L0(i)); ++ ++ if (dpb[sl_params->ref_idx_l0[i]].pic_order_cnt_val > sl_params->slice_pic_order_cnt) ++ lowdelay = 0; ++ ++ } ++ ++ for (i = 0; i <= sl_params->num_ref_idx_l1_active_minus1; i++) { ++ WRITE_RPS(!!(dpb[sl_params->ref_idx_l1[i]].flags & V4L2_HEVC_DPB_ENTRY_LONG_TERM_REFERENCE), ++ REF_PIC_LONG_TERM_L1(i)); ++ WRITE_RPS(sl_params->ref_idx_l1[i], REF_PIC_IDX_L1(i)); ++ ++ if (dpb[sl_params->ref_idx_l1[i]].pic_order_cnt_val > sl_params->slice_pic_order_cnt) ++ lowdelay = 0; ++ } ++ ++ WRITE_RPS(lowdelay, LOWDELAY); ++ ++ WRITE_RPS(sl_params->long_term_ref_pic_set_size + ++ sl_params->short_term_ref_pic_set_size, ++ LONG_TERM_RPS_BIT_OFFSET); ++ WRITE_RPS(sl_params->short_term_ref_pic_set_size, ++ SHORT_TERM_RPS_BIT_OFFSET); ++ ++ WRITE_RPS(decode_params->num_poc_st_curr_before + ++ decode_params->num_poc_st_curr_after + ++ decode_params->num_poc_lt_curr, ++ NUM_RPS_POC); ++ } ++} ++ ++static void assemble_hw_scaling_list(struct rkvdec_ctx *ctx, ++ struct rkvdec_hevc_run *run) ++{ ++ const struct v4l2_ctrl_hevc_scaling_matrix *scaling = run->scaling_matrix; ++ struct rkvdec_hevc_ctx *hevc_ctx = ctx->priv; ++ struct rkvdec_hevc_priv_tbl *tbl = hevc_ctx->priv_tbl.cpu; ++ u8 *dst; ++ scalingList_t sl; ++ int i, j; ++ ++ if (!memcmp((void*)&hevc_ctx->scaling_matrix_cache, scaling, ++ sizeof(struct v4l2_ctrl_hevc_scaling_matrix))) ++ return; ++ ++ memset(&sl, 0, sizeof(scalingList_t)); ++ ++ for (i = 0; i < 6; i++) { ++ for (j = 0; j < 16; j++) ++ sl.sl[0][i][j] = scaling->scaling_list_4x4[i][j]; ++ for (j = 0; j < 64; j++) { ++ sl.sl[1][i][j] = scaling->scaling_list_8x8[i][j]; ++ sl.sl[2][i][j] = scaling->scaling_list_16x16[i][j]; ++ if (i < 2) ++ sl.sl[3][i][j] = scaling->scaling_list_32x32[i][j]; ++ } ++ sl.sl_dc[0][i] = scaling->scaling_list_dc_coef_16x16[i]; ++ if (i < 2) ++ sl.sl_dc[1][i] = scaling->scaling_list_dc_coef_32x32[i]; ++ } ++ ++ dst = tbl->scaling_list; ++ hal_record_scaling_list((scalingFactor_t *)dst, &sl); ++ ++ memcpy((void*)&hevc_ctx->scaling_matrix_cache, scaling, ++ sizeof(struct v4l2_ctrl_hevc_scaling_matrix)); ++} ++ ++static struct vb2_buffer * ++get_ref_buf(struct rkvdec_ctx *ctx, struct rkvdec_hevc_run *run, ++ unsigned int dpb_idx) ++{ ++ struct v4l2_m2m_ctx *m2m_ctx = ctx->fh.m2m_ctx; ++ const struct v4l2_ctrl_hevc_decode_params *decode_params = run->decode_params; ++ const struct v4l2_hevc_dpb_entry *dpb = decode_params->dpb; ++ struct vb2_queue *cap_q = &m2m_ctx->cap_q_ctx.q; ++ struct vb2_buffer *vb2_buf = NULL; ++ ++ if (dpb_idx < decode_params->num_active_dpb_entries) ++ vb2_buf = vb2_find_buffer(cap_q, dpb[dpb_idx].timestamp); ++ ++ /* ++ * If a DPB entry is unused or invalid, address of current destination ++ * buffer is returned. ++ */ ++ if (!vb2_buf) ++ return &run->base.bufs.dst->vb2_buf; ++ ++ return vb2_buf; ++} ++ ++static void config_registers(struct rkvdec_ctx *ctx, ++ struct rkvdec_hevc_run *run) ++{ ++ struct rkvdec_dev *rkvdec = ctx->dev; ++ const struct v4l2_ctrl_hevc_decode_params *decode_params = run->decode_params; ++ const struct v4l2_ctrl_hevc_slice_params *sl_params = &run->slices_params[0]; ++ const struct v4l2_hevc_dpb_entry *dpb = decode_params->dpb; ++ struct rkvdec_hevc_ctx *hevc_ctx = ctx->priv; ++ dma_addr_t priv_start_addr = hevc_ctx->priv_tbl.dma; ++ const struct v4l2_pix_format_mplane *dst_fmt; ++ struct vb2_v4l2_buffer *src_buf = run->base.bufs.src; ++ struct vb2_v4l2_buffer *dst_buf = run->base.bufs.dst; ++ const struct v4l2_format *f; ++ dma_addr_t rlc_addr; ++ dma_addr_t refer_addr; ++ u32 rlc_len; ++ u32 hor_virstride; ++ u32 ver_virstride; ++ u32 y_virstride; ++ u32 uv_virstride; ++ u32 yuv_virstride; ++ u32 offset; ++ dma_addr_t dst_addr; ++ u32 reg, i; ++ ++ reg = RKVDEC_MODE(RKVDEC_MODE_HEVC); ++ writel_relaxed(reg, rkvdec->regs + RKVDEC_REG_SYSCTRL); ++ ++ f = &ctx->decoded_fmt; ++ dst_fmt = &f->fmt.pix_mp; ++ hor_virstride = dst_fmt->plane_fmt[0].bytesperline; ++ ver_virstride = dst_fmt->height; ++ y_virstride = hor_virstride * ver_virstride; ++ uv_virstride = y_virstride / 2; ++ yuv_virstride = y_virstride + uv_virstride; ++ ++ reg = RKVDEC_Y_HOR_VIRSTRIDE(hor_virstride / 16) | ++ RKVDEC_UV_HOR_VIRSTRIDE(hor_virstride / 16) | ++ RKVDEC_SLICE_NUM_LOWBITS(run->num_slices); ++ writel_relaxed(reg, rkvdec->regs + RKVDEC_REG_PICPAR); ++ ++ /* config rlc base address */ ++ rlc_addr = vb2_dma_contig_plane_dma_addr(&src_buf->vb2_buf, 0); ++ writel_relaxed(rlc_addr, rkvdec->regs + RKVDEC_REG_STRM_RLC_BASE); ++ ++ rlc_len = vb2_get_plane_payload(&src_buf->vb2_buf, 0); ++ reg = RKVDEC_STRM_LEN(round_up(rlc_len, 16) + 64); ++ writel_relaxed(reg, rkvdec->regs + RKVDEC_REG_STRM_LEN); ++ ++ /* config cabac table */ ++ offset = offsetof(struct rkvdec_hevc_priv_tbl, cabac_table); ++ writel_relaxed(priv_start_addr + offset, ++ rkvdec->regs + RKVDEC_REG_CABACTBL_PROB_BASE); ++ ++ /* config output base address */ ++ dst_addr = vb2_dma_contig_plane_dma_addr(&dst_buf->vb2_buf, 0); ++ writel_relaxed(dst_addr, rkvdec->regs + RKVDEC_REG_DECOUT_BASE); ++ ++ reg = RKVDEC_Y_VIRSTRIDE(y_virstride / 16); ++ writel_relaxed(reg, rkvdec->regs + RKVDEC_REG_Y_VIRSTRIDE); ++ ++ reg = RKVDEC_YUV_VIRSTRIDE(yuv_virstride / 16); ++ writel_relaxed(reg, rkvdec->regs + RKVDEC_REG_YUV_VIRSTRIDE); ++ ++ /* config ref pic address */ ++ for (i = 0; i < 15; i++) { ++ struct vb2_buffer *vb_buf = get_ref_buf(ctx, run, i); ++ ++ if (i < 4 && decode_params->num_active_dpb_entries) { ++ reg = GENMASK(decode_params->num_active_dpb_entries - 1, 0); ++ reg = (reg >> (i * 4)) & 0xf; ++ } else ++ reg = 0; ++ ++ refer_addr = vb2_dma_contig_plane_dma_addr(vb_buf, 0); ++ writel_relaxed(refer_addr | reg, ++ rkvdec->regs + RKVDEC_REG_H264_BASE_REFER(i)); ++ ++ reg = RKVDEC_POC_REFER(i < decode_params->num_active_dpb_entries ? dpb[i].pic_order_cnt_val : 0); ++ writel_relaxed(reg, ++ rkvdec->regs + RKVDEC_REG_H264_POC_REFER0(i)); ++ } ++ ++ reg = RKVDEC_CUR_POC(sl_params->slice_pic_order_cnt); ++ writel_relaxed(reg, rkvdec->regs + RKVDEC_REG_CUR_POC0); ++ ++ /* config hw pps address */ ++ offset = offsetof(struct rkvdec_hevc_priv_tbl, param_set); ++ writel_relaxed(priv_start_addr + offset, ++ rkvdec->regs + RKVDEC_REG_PPS_BASE); ++ ++ /* config hw rps address */ ++ offset = offsetof(struct rkvdec_hevc_priv_tbl, rps); ++ writel_relaxed(priv_start_addr + offset, ++ rkvdec->regs + RKVDEC_REG_RPS_BASE); ++ ++ reg = RKVDEC_AXI_DDR_RDATA(0); ++ writel_relaxed(reg, rkvdec->regs + RKVDEC_REG_AXI_DDR_RDATA); ++ ++ reg = RKVDEC_AXI_DDR_WDATA(0); ++ writel_relaxed(reg, rkvdec->regs + RKVDEC_REG_AXI_DDR_WDATA); ++} ++ ++#define RKVDEC_HEVC_MAX_DEPTH_IN_BYTES 2 ++ ++static int rkvdec_hevc_adjust_fmt(struct rkvdec_ctx *ctx, ++ struct v4l2_format *f) ++{ ++ struct v4l2_pix_format_mplane *fmt = &f->fmt.pix_mp; ++ ++ fmt->num_planes = 1; ++ if (!fmt->plane_fmt[0].sizeimage) ++ fmt->plane_fmt[0].sizeimage = fmt->width * fmt->height * ++ RKVDEC_HEVC_MAX_DEPTH_IN_BYTES; ++ return 0; ++} ++ ++static int rkvdec_hevc_validate_sps(struct rkvdec_ctx *ctx, ++ const struct v4l2_ctrl_hevc_sps *sps) ++{ ++ if (sps->chroma_format_idc > 1) ++ /* Only 4:0:0 and 4:2:0 are supported */ ++ return -EINVAL; ++ if (sps->bit_depth_luma_minus8 != sps->bit_depth_chroma_minus8) ++ /* Luma and chroma bit depth mismatch */ ++ return -EINVAL; ++ if (sps->bit_depth_luma_minus8 != 0 && sps->bit_depth_luma_minus8 != 2) ++ /* Only 8-bit and 10-bit is supported */ ++ return -EINVAL; ++ ++ if (sps->pic_width_in_luma_samples > ctx->coded_fmt.fmt.pix_mp.width || ++ sps->pic_height_in_luma_samples > ctx->coded_fmt.fmt.pix_mp.height) ++ return -EINVAL; ++ ++ return 0; ++} ++ ++static u32 rkvdec_hevc_valid_fmt(struct rkvdec_ctx *ctx, struct v4l2_ctrl *ctrl) ++{ ++ const struct v4l2_ctrl_hevc_sps *sps = ctrl->p_new.p_hevc_sps; ++ ++ if (sps->bit_depth_luma_minus8 == 2) ++ return V4L2_PIX_FMT_NV15; ++ else ++ return V4L2_PIX_FMT_NV12; ++} ++ ++static int rkvdec_hevc_start(struct rkvdec_ctx *ctx) ++{ ++ struct rkvdec_dev *rkvdec = ctx->dev; ++ struct rkvdec_hevc_priv_tbl *priv_tbl; ++ struct rkvdec_hevc_ctx *hevc_ctx; ++ struct v4l2_ctrl *ctrl; ++ int ret; ++ ++ ctrl = v4l2_ctrl_find(&ctx->ctrl_hdl, ++ V4L2_CID_STATELESS_HEVC_SPS); ++ if (!ctrl) ++ return -EINVAL; ++ ++ ret = rkvdec_hevc_validate_sps(ctx, ctrl->p_new.p_hevc_sps); ++ if (ret) ++ return ret; ++ ++ hevc_ctx = kzalloc(sizeof(*hevc_ctx), GFP_KERNEL); ++ if (!hevc_ctx) ++ return -ENOMEM; ++ ++ ++ priv_tbl = dma_alloc_coherent(rkvdec->dev, sizeof(*priv_tbl), ++ &hevc_ctx->priv_tbl.dma, GFP_KERNEL); ++ if (!priv_tbl) { ++ ret = -ENOMEM; ++ goto err_free_ctx; ++ } ++ ++ hevc_ctx->priv_tbl.size = sizeof(*priv_tbl); ++ hevc_ctx->priv_tbl.cpu = priv_tbl; ++ memset(priv_tbl, 0, sizeof(*priv_tbl)); ++ memcpy(priv_tbl->cabac_table, rkvdec_hevc_cabac_table, ++ sizeof(rkvdec_hevc_cabac_table)); ++ ++ ctx->priv = hevc_ctx; ++ return 0; ++ ++err_free_ctx: ++ kfree(hevc_ctx); ++ return ret; ++} ++ ++static void rkvdec_hevc_stop(struct rkvdec_ctx *ctx) ++{ ++ struct rkvdec_hevc_ctx *hevc_ctx = ctx->priv; ++ struct rkvdec_dev *rkvdec = ctx->dev; ++ ++ dma_free_coherent(rkvdec->dev, hevc_ctx->priv_tbl.size, ++ hevc_ctx->priv_tbl.cpu, hevc_ctx->priv_tbl.dma); ++ kfree(hevc_ctx); ++} ++ ++static void rkvdec_hevc_run_preamble(struct rkvdec_ctx *ctx, ++ struct rkvdec_hevc_run *run) ++{ ++ struct v4l2_ctrl *ctrl; ++ ctrl = v4l2_ctrl_find(&ctx->ctrl_hdl, ++ V4L2_CID_STATELESS_HEVC_DECODE_PARAMS); ++ run->decode_params = ctrl ? ctrl->p_cur.p : NULL; ++ ctrl = v4l2_ctrl_find(&ctx->ctrl_hdl, ++ V4L2_CID_STATELESS_HEVC_SLICE_PARAMS); ++ run->slices_params = ctrl ? ctrl->p_cur.p : NULL; ++ run->num_slices = ctrl->new_elems; ++ ctrl = v4l2_ctrl_find(&ctx->ctrl_hdl, ++ V4L2_CID_STATELESS_HEVC_SPS); ++ run->sps = ctrl ? ctrl->p_cur.p : NULL; ++ ctrl = v4l2_ctrl_find(&ctx->ctrl_hdl, ++ V4L2_CID_STATELESS_HEVC_PPS); ++ run->pps = ctrl ? ctrl->p_cur.p : NULL; ++ ctrl = v4l2_ctrl_find(&ctx->ctrl_hdl, ++ V4L2_CID_STATELESS_HEVC_SCALING_MATRIX); ++ run->scaling_matrix = ctrl ? ctrl->p_cur.p : NULL; ++ ++ rkvdec_run_preamble(ctx, &run->base); ++} ++ ++static int rkvdec_hevc_run(struct rkvdec_ctx *ctx) ++{ ++ struct rkvdec_dev *rkvdec = ctx->dev; ++ struct rkvdec_hevc_run run; ++ ++ rkvdec_hevc_run_preamble(ctx, &run); ++ ++ assemble_hw_scaling_list(ctx, &run); ++ assemble_hw_pps(ctx, &run); ++ assemble_hw_rps(ctx, &run); ++ config_registers(ctx, &run); ++ ++ rkvdec_run_postamble(ctx, &run.base); ++ ++ // sw_cabac_error_e - cabac error enable ++ writel_relaxed(0xfdfffffd, rkvdec->regs + RKVDEC_REG_STRMD_ERR_EN); ++ // slice end error enable = BIT(28) ++ // frame end error enable = BIT(29) ++ writel_relaxed(0x30000000, rkvdec->regs + RKVDEC_REG_H264_ERR_E); ++ ++ schedule_delayed_work(&rkvdec->watchdog_work, msecs_to_jiffies(2000)); ++ ++ writel(1, rkvdec->regs + RKVDEC_REG_PREF_LUMA_CACHE_COMMAND); ++ writel(1, rkvdec->regs + RKVDEC_REG_PREF_CHR_CACHE_COMMAND); ++ ++ /* Start decoding! */ ++ writel(RKVDEC_INTERRUPT_DEC_E | RKVDEC_CONFIG_DEC_CLK_GATE_E | ++ RKVDEC_TIMEOUT_E | RKVDEC_BUF_EMPTY_E, ++ rkvdec->regs + RKVDEC_REG_INTERRUPT); ++ ++ return 0; ++} ++ ++static int rkvdec_hevc_try_ctrl(struct rkvdec_ctx *ctx, struct v4l2_ctrl *ctrl) ++{ ++ if (ctrl->id == V4L2_CID_STATELESS_HEVC_SPS) ++ return rkvdec_hevc_validate_sps(ctx, ctrl->p_new.p_hevc_sps); ++ ++ return 0; ++} ++ ++const struct rkvdec_coded_fmt_ops rkvdec_hevc_fmt_ops = { ++ .adjust_fmt = rkvdec_hevc_adjust_fmt, ++ .start = rkvdec_hevc_start, ++ .stop = rkvdec_hevc_stop, ++ .run = rkvdec_hevc_run, ++ .try_ctrl = rkvdec_hevc_try_ctrl, ++ .valid_fmt = rkvdec_hevc_valid_fmt, ++}; +diff --git a/drivers/staging/media/rkvdec/rkvdec-regs.h b/drivers/staging/media/rkvdec/rkvdec-regs.h +index 265f5234f4eb..4319ee3ccbbc 100644 +--- a/drivers/staging/media/rkvdec/rkvdec-regs.h ++++ b/drivers/staging/media/rkvdec/rkvdec-regs.h +@@ -48,6 +48,7 @@ + #define RKVDEC_RLC_MODE BIT(11) + #define RKVDEC_STRM_START_BIT(x) (((x) & 0x7f) << 12) + #define RKVDEC_MODE(x) (((x) & 0x03) << 20) ++#define RKVDEC_MODE_HEVC 0 + #define RKVDEC_MODE_H264 1 + #define RKVDEC_MODE_VP9 2 + #define RKVDEC_RPS_MODE BIT(24) +diff --git a/drivers/staging/media/rkvdec/rkvdec.c b/drivers/staging/media/rkvdec/rkvdec.c +index f55abb7c377f..00a9bf583596 100644 +--- a/drivers/staging/media/rkvdec/rkvdec.c ++++ b/drivers/staging/media/rkvdec/rkvdec.c +@@ -74,7 +74,7 @@ static int rkvdec_s_ctrl(struct v4l2_ctrl *ctrl) + { + struct rkvdec_ctx *ctx = container_of(ctrl->handler, struct rkvdec_ctx, ctrl_hdl); + +- if (ctrl->id == V4L2_CID_STATELESS_H264_SPS && !ctx->valid_fmt) { ++ if (!ctx->valid_fmt) { + ctx->valid_fmt = rkvdec_valid_fmt(ctx, ctrl); + if (ctx->valid_fmt) { + struct v4l2_pix_format_mplane *pix_mp; +@@ -134,6 +134,62 @@ static const struct rkvdec_ctrl_desc rkvdec_h264_ctrl_descs[] = { + }, + }; + ++static const struct rkvdec_ctrl_desc rkvdec_hevc_ctrl_descs[] = { ++ { ++ .cfg.id = V4L2_CID_STATELESS_HEVC_SLICE_PARAMS, ++ .cfg.flags = V4L2_CTRL_FLAG_DYNAMIC_ARRAY, ++ .cfg.type = V4L2_CTRL_TYPE_HEVC_SLICE_PARAMS, ++ .cfg.dims = { 600 }, ++ }, ++ { ++ .cfg.id = V4L2_CID_STATELESS_HEVC_SPS, ++ .cfg.ops = &rkvdec_ctrl_ops, ++ }, ++ { ++ .cfg.id = V4L2_CID_STATELESS_HEVC_PPS, ++ }, ++ { ++ .cfg.id = V4L2_CID_STATELESS_HEVC_SCALING_MATRIX, ++ }, ++ { ++ .cfg.id = V4L2_CID_STATELESS_HEVC_DECODE_PARAMS, ++ }, ++ { ++ .cfg.id = V4L2_CID_STATELESS_HEVC_DECODE_MODE, ++ .cfg.min = V4L2_STATELESS_HEVC_DECODE_MODE_FRAME_BASED, ++ .cfg.max = V4L2_STATELESS_HEVC_DECODE_MODE_FRAME_BASED, ++ .cfg.def = V4L2_STATELESS_HEVC_DECODE_MODE_FRAME_BASED, ++ }, ++ { ++ .cfg.id = V4L2_CID_STATELESS_HEVC_START_CODE, ++ .cfg.min = V4L2_STATELESS_HEVC_START_CODE_ANNEX_B, ++ .cfg.def = V4L2_STATELESS_HEVC_START_CODE_ANNEX_B, ++ .cfg.max = V4L2_STATELESS_HEVC_START_CODE_ANNEX_B, ++ }, ++ { ++ .cfg.id = V4L2_CID_MPEG_VIDEO_HEVC_PROFILE, ++ .cfg.min = V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN, ++ .cfg.max = V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN_10, ++ .cfg.def = V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN, ++ }, ++ { ++ .cfg.id = V4L2_CID_MPEG_VIDEO_HEVC_LEVEL, ++ .cfg.min = V4L2_MPEG_VIDEO_HEVC_LEVEL_1, ++ .cfg.max = V4L2_MPEG_VIDEO_HEVC_LEVEL_5_1, ++ }, ++}; ++ ++static const struct rkvdec_ctrls rkvdec_hevc_ctrls = { ++ .ctrls = rkvdec_hevc_ctrl_descs, ++ .num_ctrls = ARRAY_SIZE(rkvdec_hevc_ctrl_descs), ++}; ++ ++static const u32 rkvdec_hevc_decoded_fmts[] = { ++ V4L2_PIX_FMT_NV12, ++ V4L2_PIX_FMT_NV15, ++}; ++ ++ + static const struct rkvdec_ctrls rkvdec_h264_ctrls = { + .ctrls = rkvdec_h264_ctrl_descs, + .num_ctrls = ARRAY_SIZE(rkvdec_h264_ctrl_descs), +@@ -187,6 +243,21 @@ static const struct rkvdec_coded_fmt_desc rkvdec_coded_fmts[] = { + .decoded_fmts = rkvdec_h264_decoded_fmts, + .subsystem_flags = VB2_V4L2_FL_SUPPORTS_M2M_HOLD_CAPTURE_BUF, + }, ++ { ++ .fourcc = V4L2_PIX_FMT_HEVC_SLICE, ++ .frmsize = { ++ .min_width = 64, ++ .max_width = 4096, ++ .step_width = 64, ++ .min_height = 64, ++ .max_height = 2304, ++ .step_height = 16, ++ }, ++ .ctrls = &rkvdec_hevc_ctrls, ++ .ops = &rkvdec_hevc_fmt_ops, ++ .num_decoded_fmts = ARRAY_SIZE(rkvdec_hevc_decoded_fmts), ++ .decoded_fmts = rkvdec_hevc_decoded_fmts, ++ }, + { + .fourcc = V4L2_PIX_FMT_VP9_FRAME, + .frmsize = { +diff --git a/drivers/staging/media/rkvdec/rkvdec.h b/drivers/staging/media/rkvdec/rkvdec.h +index f02f79c405f0..d6222a2588be 100644 +--- a/drivers/staging/media/rkvdec/rkvdec.h ++++ b/drivers/staging/media/rkvdec/rkvdec.h +@@ -133,6 +133,7 @@ void rkvdec_run_preamble(struct rkvdec_ctx *ctx, struct rkvdec_run *run); + void rkvdec_run_postamble(struct rkvdec_ctx *ctx, struct rkvdec_run *run); + + extern const struct rkvdec_coded_fmt_ops rkvdec_h264_fmt_ops; ++extern const struct rkvdec_coded_fmt_ops rkvdec_hevc_fmt_ops; + extern const struct rkvdec_coded_fmt_ops rkvdec_vp9_fmt_ops; + + #endif /* RKVDEC_H_ */ + +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Alex Bee +Date: Sat, 30 Jan 2021 18:16:39 +0100 +Subject: [PATCH] media: rkvdec: add variants support + +rkvdec IP has different versions which among others differ in +the supported decoding formats. +This adds an variant implementation in order support other +than the currently supported RK3399 version. + +Note: Since matching of supported codecs is index-based the +available codec options have been reordered here: from +supported by all versions to not commonly supported. This seems +the better soultion than duplicatiing code for every newly added IP. + +Signed-off-by: Alex Bee +--- + drivers/staging/media/rkvdec/rkvdec.c | 105 ++++++++++++++++++-------- + drivers/staging/media/rkvdec/rkvdec.h | 10 +++ + 2 files changed, 85 insertions(+), 30 deletions(-) + +diff --git a/drivers/staging/media/rkvdec/rkvdec.c b/drivers/staging/media/rkvdec/rkvdec.c +index 00a9bf583596..955c53afe20f 100644 +--- a/drivers/staging/media/rkvdec/rkvdec.c ++++ b/drivers/staging/media/rkvdec/rkvdec.c +@@ -14,6 +14,7 @@ + #include + #include + #include ++#include + #include + #include + #include +@@ -227,6 +228,22 @@ static const u32 rkvdec_vp9_decoded_fmts[] = { + }; + + static const struct rkvdec_coded_fmt_desc rkvdec_coded_fmts[] = { ++ { ++ .fourcc = V4L2_PIX_FMT_HEVC_SLICE, ++ .frmsize = { ++ .min_width = 64, ++ .max_width = 4096, ++ .step_width = 64, ++ .min_height = 64, ++ .max_height = 2304, ++ .step_height = 16, ++ }, ++ .ctrls = &rkvdec_hevc_ctrls, ++ .ops = &rkvdec_hevc_fmt_ops, ++ .num_decoded_fmts = ARRAY_SIZE(rkvdec_hevc_decoded_fmts), ++ .decoded_fmts = rkvdec_hevc_decoded_fmts, ++ .capability = RKVDEC_CAPABILITY_HEVC, ++ }, + { + .fourcc = V4L2_PIX_FMT_H264_SLICE, + .frmsize = { +@@ -242,21 +259,7 @@ static const struct rkvdec_coded_fmt_desc rkvdec_coded_fmts[] = { + .num_decoded_fmts = ARRAY_SIZE(rkvdec_h264_decoded_fmts), + .decoded_fmts = rkvdec_h264_decoded_fmts, + .subsystem_flags = VB2_V4L2_FL_SUPPORTS_M2M_HOLD_CAPTURE_BUF, +- }, +- { +- .fourcc = V4L2_PIX_FMT_HEVC_SLICE, +- .frmsize = { +- .min_width = 64, +- .max_width = 4096, +- .step_width = 64, +- .min_height = 64, +- .max_height = 2304, +- .step_height = 16, +- }, +- .ctrls = &rkvdec_hevc_ctrls, +- .ops = &rkvdec_hevc_fmt_ops, +- .num_decoded_fmts = ARRAY_SIZE(rkvdec_hevc_decoded_fmts), +- .decoded_fmts = rkvdec_hevc_decoded_fmts, ++ .capability = RKVDEC_CAPABILITY_H264, + }, + { + .fourcc = V4L2_PIX_FMT_VP9_FRAME, +@@ -272,16 +275,31 @@ static const struct rkvdec_coded_fmt_desc rkvdec_coded_fmts[] = { + .ops = &rkvdec_vp9_fmt_ops, + .num_decoded_fmts = ARRAY_SIZE(rkvdec_vp9_decoded_fmts), + .decoded_fmts = rkvdec_vp9_decoded_fmts, +- } ++ .capability = RKVDEC_CAPABILITY_VP9, ++ }, + }; + + static const struct rkvdec_coded_fmt_desc * +-rkvdec_find_coded_fmt_desc(u32 fourcc) ++rkvdec_default_coded_fmt_desc(unsigned int capabilities) ++{ ++ unsigned int i; ++ ++ for (i = 0; i < ARRAY_SIZE(rkvdec_coded_fmts); i++) { ++ if (rkvdec_coded_fmts[i].capability & capabilities) ++ return &rkvdec_coded_fmts[i]; ++ } ++ ++ return NULL; ++} ++ ++static const struct rkvdec_coded_fmt_desc * ++rkvdec_find_coded_fmt_desc(u32 fourcc, unsigned int capabilities) + { + unsigned int i; + + for (i = 0; i < ARRAY_SIZE(rkvdec_coded_fmts); i++) { +- if (rkvdec_coded_fmts[i].fourcc == fourcc) ++ if (rkvdec_coded_fmts[i].fourcc == fourcc && ++ (rkvdec_coded_fmts[i].capability & capabilities)) + return &rkvdec_coded_fmts[i]; + } + +@@ -304,7 +322,7 @@ static void rkvdec_reset_coded_fmt(struct rkvdec_ctx *ctx) + { + struct v4l2_format *f = &ctx->coded_fmt; + +- ctx->coded_fmt_desc = &rkvdec_coded_fmts[0]; ++ ctx->coded_fmt_desc = rkvdec_default_coded_fmt_desc(ctx->dev->capabilities); + rkvdec_reset_fmt(ctx, f, ctx->coded_fmt_desc->fourcc); + + f->type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE; +@@ -331,11 +349,13 @@ static int rkvdec_enum_framesizes(struct file *file, void *priv, + struct v4l2_frmsizeenum *fsize) + { + const struct rkvdec_coded_fmt_desc *fmt; ++ struct rkvdec_dev *rkvdec = video_drvdata(file); + + if (fsize->index != 0) + return -EINVAL; + +- fmt = rkvdec_find_coded_fmt_desc(fsize->pixel_format); ++ fmt = rkvdec_find_coded_fmt_desc(fsize->pixel_format, ++ rkvdec->capabilities); + if (!fmt) + return -EINVAL; + +@@ -406,10 +426,11 @@ static int rkvdec_try_output_fmt(struct file *file, void *priv, + struct rkvdec_ctx *ctx = fh_to_rkvdec_ctx(priv); + const struct rkvdec_coded_fmt_desc *desc; + +- desc = rkvdec_find_coded_fmt_desc(pix_mp->pixelformat); ++ desc = rkvdec_find_coded_fmt_desc(pix_mp->pixelformat, ++ ctx->dev->capabilities); + if (!desc) { +- pix_mp->pixelformat = rkvdec_coded_fmts[0].fourcc; +- desc = &rkvdec_coded_fmts[0]; ++ desc = rkvdec_default_coded_fmt_desc(ctx->dev->capabilities); ++ pix_mp->pixelformat = desc->fourcc; + } + + v4l2_apply_frmsize_constraints(&pix_mp->width, +@@ -487,7 +508,8 @@ static int rkvdec_s_output_fmt(struct file *file, void *priv, + if (ret) + return ret; + +- desc = rkvdec_find_coded_fmt_desc(f->fmt.pix_mp.pixelformat); ++ desc = rkvdec_find_coded_fmt_desc(f->fmt.pix_mp.pixelformat, ++ ctx->dev->capabilities); + if (!desc) + return -EINVAL; + ctx->coded_fmt_desc = desc; +@@ -538,7 +560,10 @@ static int rkvdec_g_capture_fmt(struct file *file, void *priv, + static int rkvdec_enum_output_fmt(struct file *file, void *priv, + struct v4l2_fmtdesc *f) + { +- if (f->index >= ARRAY_SIZE(rkvdec_coded_fmts)) ++ struct rkvdec_ctx *ctx = fh_to_rkvdec_ctx(priv); ++ ++ if (f->index >= ARRAY_SIZE(rkvdec_coded_fmts) || ++ !(ctx->dev->capabilities & rkvdec_coded_fmts[f->index].capability)) + return -EINVAL; + + f->pixelformat = rkvdec_coded_fmts[f->index].fourcc; +@@ -946,14 +971,17 @@ static int rkvdec_init_ctrls(struct rkvdec_ctx *ctx) + int ret; + + for (i = 0; i < ARRAY_SIZE(rkvdec_coded_fmts); i++) +- nctrls += rkvdec_coded_fmts[i].ctrls->num_ctrls; ++ if (rkvdec_coded_fmts[i].capability & ctx->dev->capabilities) ++ nctrls += rkvdec_coded_fmts[i].ctrls->num_ctrls; + + v4l2_ctrl_handler_init(&ctx->ctrl_hdl, nctrls); + + for (i = 0; i < ARRAY_SIZE(rkvdec_coded_fmts); i++) { +- ret = rkvdec_add_ctrls(ctx, rkvdec_coded_fmts[i].ctrls); +- if (ret) +- goto err_free_handler; ++ if (rkvdec_coded_fmts[i].capability & ctx->dev->capabilities) { ++ ret = rkvdec_add_ctrls(ctx, rkvdec_coded_fmts[i].ctrls); ++ if (ret) ++ goto err_free_handler; ++ } + } + + ret = v4l2_ctrl_handler_setup(&ctx->ctrl_hdl); +@@ -1155,8 +1183,17 @@ static void rkvdec_watchdog_func(struct work_struct *work) + } + } + ++static const struct rkvdec_variant rk3399_rkvdec_variant = { ++ .capabilities = RKVDEC_CAPABILITY_H264 | ++ RKVDEC_CAPABILITY_HEVC | ++ RKVDEC_CAPABILITY_VP9 ++}; ++ + static const struct of_device_id of_rkvdec_match[] = { +- { .compatible = "rockchip,rk3399-vdec" }, ++ { ++ .compatible = "rockchip,rk3399-vdec", ++ .data = &rk3399_rkvdec_variant, ++ }, + { /* sentinel */ } + }; + MODULE_DEVICE_TABLE(of, of_rkvdec_match); +@@ -1168,6 +1205,7 @@ static const char * const rkvdec_clk_names[] = { + static int rkvdec_probe(struct platform_device *pdev) + { + struct rkvdec_dev *rkvdec; ++ const struct rkvdec_variant *variant; + unsigned int i; + int ret, irq; + +@@ -1193,6 +1231,13 @@ static int rkvdec_probe(struct platform_device *pdev) + if (ret) + return ret; + ++ variant = of_device_get_match_data(rkvdec->dev); ++ if (!variant) ++ return -EINVAL; ++ ++ rkvdec->capabilities = variant->capabilities; ++ ++ + rkvdec->regs = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(rkvdec->regs)) + return PTR_ERR(rkvdec->regs); +diff --git a/drivers/staging/media/rkvdec/rkvdec.h b/drivers/staging/media/rkvdec/rkvdec.h +index d6222a2588be..ad8e83884121 100644 +--- a/drivers/staging/media/rkvdec/rkvdec.h ++++ b/drivers/staging/media/rkvdec/rkvdec.h +@@ -29,6 +29,10 @@ + + #define RKVDEC_RESET_DELAY 5 + ++#define RKVDEC_CAPABILITY_H264 BIT(0) ++#define RKVDEC_CAPABILITY_HEVC BIT(1) ++#define RKVDEC_CAPABILITY_VP9 BIT(2) ++ + struct rkvdec_ctx; + + struct rkvdec_ctrl_desc { +@@ -70,6 +74,10 @@ vb2_to_rkvdec_decoded_buf(struct vb2_buffer *buf) + base.vb.vb2_buf); + } + ++struct rkvdec_variant { ++ unsigned int capabilities; ++}; ++ + struct rkvdec_coded_fmt_ops { + int (*adjust_fmt)(struct rkvdec_ctx *ctx, + struct v4l2_format *f); +@@ -91,6 +99,7 @@ struct rkvdec_coded_fmt_desc { + unsigned int num_decoded_fmts; + const u32 *decoded_fmts; + u32 subsystem_flags; ++ unsigned int capability; + }; + + struct rkvdec_dev { +@@ -105,6 +114,7 @@ struct rkvdec_dev { + struct delayed_work watchdog_work; + struct reset_control *rstc; + u8 reset_mask; ++ unsigned int capabilities; + }; + + struct rkvdec_ctx { + +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Alex Bee +Date: Sat, 30 Jan 2021 18:21:59 +0100 +Subject: [PATCH] media: rkvdec: add RK3288 variant + +This adds RK3288 variant to rkvdec driver. In this earlier version +of the IP only HEVC decoding is supported. + +Signed-off-by: Alex Bee +--- + drivers/staging/media/rkvdec/rkvdec.c | 8 ++++++++ + 1 file changed, 8 insertions(+) + +diff --git a/drivers/staging/media/rkvdec/rkvdec.c b/drivers/staging/media/rkvdec/rkvdec.c +index 955c53afe20f..4e228cd82f21 100644 +--- a/drivers/staging/media/rkvdec/rkvdec.c ++++ b/drivers/staging/media/rkvdec/rkvdec.c +@@ -1189,11 +1189,19 @@ static const struct rkvdec_variant rk3399_rkvdec_variant = { + RKVDEC_CAPABILITY_VP9 + }; + ++static const struct rkvdec_variant rk3288_hevc_variant = { ++ .capabilities = RKVDEC_CAPABILITY_HEVC ++}; ++ + static const struct of_device_id of_rkvdec_match[] = { + { + .compatible = "rockchip,rk3399-vdec", + .data = &rk3399_rkvdec_variant, + }, ++ { ++ .compatible = "rockchip,rk3288-hevc", ++ .data = &rk3288_hevc_variant, ++ }, + { /* sentinel */ } + }; + MODULE_DEVICE_TABLE(of, of_rkvdec_match); + +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Alex Bee +Date: Sat, 30 Jan 2021 18:27:30 +0100 +Subject: [PATCH] ARM: dts: RK3288: add hevc node + +Signed-off-by: Alex Bee +--- + arch/arm/boot/dts/rockchip/rk3288.dtsi | 21 ++++++++++++++++++++- + 1 file changed, 20 insertions(+), 1 deletion(-) + +diff --git a/arch/arm/boot/dts/rockchip/rk3288.dtsi b/arch/arm/boot/dts/rockchip/rk3288.dtsi +index 7b2cde230b87..59fba3ac6aae 100644 +--- a/arch/arm/boot/dts/rockchip/rk3288.dtsi ++++ b/arch/arm/boot/dts/rockchip/rk3288.dtsi +@@ -1248,6 +1248,25 @@ vpu_mmu: iommu@ff9a0800 { + power-domains = <&power RK3288_PD_VIDEO>; + }; + ++ hevc: hevc@ff9c0000 { ++ compatible = "rockchip,rk3288-hevc"; ++ reg = <0x0 0xff9c0000 0x0 0x400>; ++ interrupts = ; ++ interrupt-names = "irq_dec"; ++ clocks = <&cru ACLK_HEVC>, <&cru HCLK_HEVC>, <&cru SCLK_HEVC_CABAC>, ++ <&cru SCLK_HEVC_CORE>; ++ clock-names = "axi", "ahb", "cabac", "core"; ++ assigned-clocks = <&cru ACLK_HEVC>, <&cru HCLK_HEVC>, ++ <&cru SCLK_HEVC_CORE>, ++ <&cru SCLK_HEVC_CABAC>; ++ assigned-clock-rates = <400000000>, <100000000>, ++ <300000000>, <300000000>; ++ iommus = <&hevc_mmu>; ++ power-domains = <&power RK3288_PD_HEVC>; ++ resets = <&cru SRST_HEVC>; ++ reset-names = "video_core"; ++ }; ++ + hevc_mmu: iommu@ff9c0440 { + compatible = "rockchip,iommu"; + reg = <0x0 0xff9c0440 0x0 0x40>, <0x0 0xff9c0480 0x0 0x40>; +@@ -1255,7 +1274,7 @@ hevc_mmu: iommu@ff9c0440 { + clocks = <&cru ACLK_HEVC>, <&cru HCLK_HEVC>; + clock-names = "aclk", "iface"; + #iommu-cells = <0>; +- status = "disabled"; ++ power-domains = <&power RK3288_PD_HEVC>; + }; + + gpu: gpu@ffa30000 { + +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Nicolas Dufresne +Date: Tue, 10 May 2022 14:37:29 -0400 +Subject: [PATCH] media: rkvdec: Fix HEVC RPS bit offsets + +The offsets from the uAPI need to be extended to include some bits +that can be calculated from the parameters. This has been compared +to match with the vendor bit sizes (which simply parse again the +data to calcualte it). + +Fixed by this change: +- LTRPSPS_A_Qualcomm_1 +- RPS_C_ericsson_5 +- RPS_D_ericsson_6 +- RPS_E_qualcomm_5 + +Signed-off-by: Nicolas Dufresne +--- + drivers/staging/media/rkvdec/rkvdec-hevc.c | 26 +++++++++++++++++++--- + 1 file changed, 23 insertions(+), 3 deletions(-) + +diff --git a/drivers/staging/media/rkvdec/rkvdec-hevc.c b/drivers/staging/media/rkvdec/rkvdec-hevc.c +index 7a375a23eaf1..580073d49b6a 100644 +--- a/drivers/staging/media/rkvdec/rkvdec-hevc.c ++++ b/drivers/staging/media/rkvdec/rkvdec-hevc.c +@@ -10,6 +10,7 @@ + */ + + #include ++#include + + #include "rkvdec.h" + #include "rkvdec-regs.h" +@@ -2175,6 +2176,7 @@ static void assemble_hw_rps(struct rkvdec_ctx *ctx, + struct rkvdec_hevc_run *run) + { + const struct v4l2_ctrl_hevc_decode_params *decode_params = run->decode_params; ++ const struct v4l2_ctrl_hevc_sps *sps = run->sps; + const struct v4l2_ctrl_hevc_slice_params *sl_params; + const struct v4l2_hevc_dpb_entry *dpb; + struct rkvdec_hevc_ctx *hevc_ctx = ctx->priv; +@@ -2196,9 +2198,21 @@ static void assemble_hw_rps(struct rkvdec_ctx *ctx, + #define NUM_RPS_POC PS_FIELD(202, 4) + + for (j = 0; j < run->num_slices; j++) { ++ uint st_bit_offset = 0; ++ + sl_params = &run->slices_params[j]; + dpb = decode_params->dpb; +- lowdelay = (sl_params->slice_type == V4L2_HEVC_SLICE_TYPE_I) ? 0 : 1; ++ ++ if (sl_params->slice_type != V4L2_HEVC_SLICE_TYPE_I) { ++ num_l0_refs = sl_params->num_ref_idx_l0_active_minus1 + 1; ++ ++ if (sl_params->slice_type == V4L2_HEVC_SLICE_TYPE_B) ++ num_l1_refs = sl_params->num_ref_idx_l1_active_minus1 + 1; ++ ++ lowdelay = 1; ++ } else { ++ lowdelay = 0; ++ } + + hw_ps = &priv_tbl->rps[j]; + memset(hw_ps, 0, sizeof(*hw_ps)); +@@ -2224,8 +2238,14 @@ static void assemble_hw_rps(struct rkvdec_ctx *ctx, + + WRITE_RPS(lowdelay, LOWDELAY); + +- WRITE_RPS(sl_params->long_term_ref_pic_set_size + +- sl_params->short_term_ref_pic_set_size, ++ if (!(decode_params->flags & V4L2_HEVC_DECODE_PARAM_FLAG_IDR_PIC)) { ++ if (sl_params->short_term_ref_pic_set_size) ++ st_bit_offset = sl_params->short_term_ref_pic_set_size; ++ else if (sps->num_short_term_ref_pic_sets > 1) ++ st_bit_offset = fls(sps->num_short_term_ref_pic_sets - 1); ++ } ++ ++ WRITE_RPS(st_bit_offset + sl_params->long_term_ref_pic_set_size, + LONG_TERM_RPS_BIT_OFFSET); + WRITE_RPS(sl_params->short_term_ref_pic_set_size, + SHORT_TERM_RPS_BIT_OFFSET); + +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Nicolas Dufresne +Date: Tue, 10 May 2022 15:12:03 -0400 +Subject: [PATCH] media: rkvdec: Fix number of HEVC references being set in RPS + +The numbers from the bitstream are values between 1 - 16 (as they are +the number - 1). The difference between 0 and 1 needs to be determined +base on the slice type. I frames have no reference, P frames only have +L0 reference, and B frames have both. + +Signed-off-by: Nicolas Dufresne +--- + drivers/staging/media/rkvdec/rkvdec-hevc.c | 6 ++++-- + 1 file changed, 4 insertions(+), 2 deletions(-) + +diff --git a/drivers/staging/media/rkvdec/rkvdec-hevc.c b/drivers/staging/media/rkvdec/rkvdec-hevc.c +index 580073d49b6a..ce15028918b2 100644 +--- a/drivers/staging/media/rkvdec/rkvdec-hevc.c ++++ b/drivers/staging/media/rkvdec/rkvdec-hevc.c +@@ -2199,6 +2199,8 @@ static void assemble_hw_rps(struct rkvdec_ctx *ctx, + + for (j = 0; j < run->num_slices; j++) { + uint st_bit_offset = 0; ++ uint num_l0_refs = 0; ++ uint num_l1_refs = 0; + + sl_params = &run->slices_params[j]; + dpb = decode_params->dpb; +@@ -2217,7 +2219,7 @@ static void assemble_hw_rps(struct rkvdec_ctx *ctx, + hw_ps = &priv_tbl->rps[j]; + memset(hw_ps, 0, sizeof(*hw_ps)); + +- for (i = 0; i <= sl_params->num_ref_idx_l0_active_minus1; i++) { ++ for (i = 0; i < num_l0_refs; i++) { + WRITE_RPS(!!(dpb[sl_params->ref_idx_l0[i]].flags & V4L2_HEVC_DPB_ENTRY_LONG_TERM_REFERENCE), + REF_PIC_LONG_TERM_L0(i)); + WRITE_RPS(sl_params->ref_idx_l0[i], REF_PIC_IDX_L0(i)); +@@ -2227,7 +2229,7 @@ static void assemble_hw_rps(struct rkvdec_ctx *ctx, + + } + +- for (i = 0; i <= sl_params->num_ref_idx_l1_active_minus1; i++) { ++ for (i = 0; i < num_l1_refs; i++) { + WRITE_RPS(!!(dpb[sl_params->ref_idx_l1[i]].flags & V4L2_HEVC_DPB_ENTRY_LONG_TERM_REFERENCE), + REF_PIC_LONG_TERM_L1(i)); + WRITE_RPS(sl_params->ref_idx_l1[i], REF_PIC_IDX_L1(i)); diff --git a/patch/kernel/archive/rockchip-6.12/patches.libreelec/linux-2001-v4l2-wip-iep-driver.patch b/patch/kernel/archive/rockchip-6.12/patches.libreelec/linux-2001-v4l2-wip-iep-driver.patch new file mode 100644 index 000000000000..541c84937605 --- /dev/null +++ b/patch/kernel/archive/rockchip-6.12/patches.libreelec/linux-2001-v4l2-wip-iep-driver.patch @@ -0,0 +1,1803 @@ +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Alex Bee +Date: Sun, 11 Oct 2020 17:03:12 +0200 +Subject: [PATCH] dt-bindings: media: Add Rockchip IEP binding + +Signed-off-by: Alex Bee +--- + .../bindings/media/rockchip-iep.yaml | 73 +++++++++++++++++++ + 1 file changed, 73 insertions(+) + create mode 100644 Documentation/devicetree/bindings/media/rockchip-iep.yaml + +diff --git a/Documentation/devicetree/bindings/media/rockchip-iep.yaml b/Documentation/devicetree/bindings/media/rockchip-iep.yaml +new file mode 100644 +index 000000000000..a9efcda13fc1 +--- /dev/null ++++ b/Documentation/devicetree/bindings/media/rockchip-iep.yaml +@@ -0,0 +1,73 @@ ++# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) ++%YAML 1.2 ++--- ++$id: http://devicetree.org/schemas/media/rockchip-iep.yaml# ++$schema: http://devicetree.org/meta-schemas/core.yaml# ++ ++title: Rockchip Image Enhancement Processor (IEP) ++ ++description: ++ Rockchip IEP supports various image enhancement operations for YUV and RGB domains. ++ Deinterlacing, spatial and temporal sampling noise reduction are supported by the ++ YUV block. Gamma adjustment, edge enhancement, detail enhancement are supported in ++ the RGB block. Brightness, Saturation, Contrast, Hue adjustment is supported for ++ both domains. Furthermore it supports converting RGB to YUV / YUV to RGB. ++ ++maintainers: ++ - Heiko Stuebner ++ ++properties: ++ compatible: ++ oneOf: ++ - const: rockchip,rk3228-iep ++ - items: ++ - enum: ++ - rockchip,rk3288-iep ++ - rockchip,rk3328-iep ++ - rockchip,rk3368-iep ++ - rockchip,rk3399-iep ++ - const: rockchip,rk3228-iep ++ ++ reg: ++ maxItems: 1 ++ ++ interrupts: ++ maxItems: 1 ++ ++ clocks: ++ maxItems: 2 ++ ++ clock-names: ++ items: ++ - const: axi ++ - const: ahb ++ ++ power-domains: ++ maxItems: 1 ++ ++ iommus: ++ maxItems: 1 ++ ++required: ++ - compatible ++ - reg ++ - interrupts ++ - clocks ++ - clock-names ++ ++additionalProperties: false ++ ++examples: ++ - | ++ #include ++ #include ++ #include ++ iep: iep@20070000 { ++ compatible = "rockchip,rk3228-iep"; ++ reg = <0x20070000 0x800>; ++ interrupts = ; ++ clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>; ++ clock-names = "axi", "ahb"; ++ iommus = <&iep_mmu>; ++ power-domains = <&power RK3228_PD_VIO>; ++ }; + +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Alex Bee +Date: Sun, 11 Oct 2020 21:24:10 +0200 +Subject: [PATCH] media: rockchip: Add Rockchip IEP driver + +Signed-off-by: Alex Bee +--- + drivers/media/platform/rockchip/Kconfig | 1 + + drivers/media/platform/rockchip/Makefile | 1 + + drivers/media/platform/rockchip/iep/Kconfig | 16 + + drivers/media/platform/rockchip/iep/Makefile | 5 + + .../media/platform/rockchip/iep/iep-regs.h | 291 +++++ + drivers/media/platform/rockchip/iep/iep.c | 1089 +++++++++++++++++ + drivers/media/platform/rockchip/iep/iep.h | 112 ++ + 7 files changed, 1515 insertions(+) + create mode 100644 drivers/media/platform/rockchip/iep/Kconfig + create mode 100644 drivers/media/platform/rockchip/iep/Makefile + create mode 100644 drivers/media/platform/rockchip/iep/iep-regs.h + create mode 100644 drivers/media/platform/rockchip/iep/iep.c + create mode 100644 drivers/media/platform/rockchip/iep/iep.h + +diff --git a/drivers/media/platform/rockchip/Kconfig b/drivers/media/platform/rockchip/Kconfig +index b41d3960c1b4..9ff362805ded 100644 +--- a/drivers/media/platform/rockchip/Kconfig ++++ b/drivers/media/platform/rockchip/Kconfig +@@ -2,5 +2,6 @@ + + comment "Rockchip media platform drivers" + ++source "drivers/media/platform/rockchip/iep/Kconfig" + source "drivers/media/platform/rockchip/rga/Kconfig" + source "drivers/media/platform/rockchip/rkisp1/Kconfig" +diff --git a/drivers/media/platform/rockchip/Makefile b/drivers/media/platform/rockchip/Makefile +index 4f782b876ac9..c075ecc2fa14 100644 +--- a/drivers/media/platform/rockchip/Makefile ++++ b/drivers/media/platform/rockchip/Makefile +@@ -1,3 +1,4 @@ + # SPDX-License-Identifier: GPL-2.0-only ++obj-y += iep/ + obj-y += rga/ + obj-y += rkisp1/ +diff --git a/drivers/media/platform/rockchip/iep/Kconfig b/drivers/media/platform/rockchip/iep/Kconfig +new file mode 100644 +index 000000000000..d95155a95133 +--- /dev/null ++++ b/drivers/media/platform/rockchip/iep/Kconfig +@@ -0,0 +1,16 @@ ++# SPDX-License-Identifier: GPL-2.0-only ++ ++config VIDEO_ROCKCHIP_IEP ++ tristate "Rockchip Image Enhancement Processor" ++ depends on V4L_MEM2MEM_DRIVERS ++ depends on VIDEO_DEV ++ depends on ARCH_ROCKCHIP || COMPILE_TEST ++ select VIDEOBUF2_DMA_CONTIG ++ select V4L2_MEM2MEM_DEV ++ help ++ This is a v4l2 driver for Rockchip Image Enhancement Processor (IEP) ++ found in most Rockchip RK3xxx SoCs. ++ Rockchip IEP supports various enhancement operations for RGB and YUV ++ images. The driver currently implements YUV deinterlacing only. ++ To compile this driver as a module, choose M here: the module ++ will be called rockchip-iep +diff --git a/drivers/media/platform/rockchip/iep/Makefile b/drivers/media/platform/rockchip/iep/Makefile +new file mode 100644 +index 000000000000..5c89b3277469 +--- /dev/null ++++ b/drivers/media/platform/rockchip/iep/Makefile +@@ -0,0 +1,5 @@ ++# SPDX-License-Identifier: GPL-2.0-only ++ ++rockchip-iep-objs := iep.o ++ ++obj-$(CONFIG_VIDEO_ROCKCHIP_IEP) += rockchip-iep.o +diff --git a/drivers/media/platform/rockchip/iep/iep-regs.h b/drivers/media/platform/rockchip/iep/iep-regs.h +new file mode 100644 +index 000000000000..a68685ef3604 +--- /dev/null ++++ b/drivers/media/platform/rockchip/iep/iep-regs.h +@@ -0,0 +1,291 @@ ++/* SPDX-License-Identifier: GPL-2.0-only */ ++/* ++ * Rockchip Image Enhancement Processor (IEP) driver ++ * ++ * Copyright (C) 2020 Alex Bee ++ * ++ */ ++ ++#ifndef __IEP_REGS_H__ ++#define __IEP_REGS_H__ ++ ++/* IEP Registers addresses */ ++#define IEP_CONFIG0 0x000 /* Configuration register0 */ ++#define IEP_VOP_DIRECT_PATH BIT(0) ++#define IEP_DEIN_HIGH_FREQ_SHFT 1 ++#define IEP_DEIN_HIGH_FREQ_MASK (0x7f << IEP_DEIN_HIGH_FREQ_SHFT) ++#define IEP_DEIN_MODE_SHFT 8 ++#define IEP_DEIN_MODE_MASK (7 << IEP_DEIN_MODE_SHFT) ++#define IEP_DEIN_HIGH_FREQ_EN BIT(11) ++#define IEP_DEIN_EDGE_INTPOL_EN BIT(12) ++#define IEP_YUV_DENOISE_EN BIT(13) ++#define IEP_YUV_ENHNC_EN BIT(14) ++#define IEP_DEIN_EDGE_INTPOL_SMTH_EN BIT(15) ++#define IEP_RGB_CLR_ENHNC_EN BIT(16) ++#define IEP_RGB_CNTRST_ENHNC_EN BIT(17) ++#define IEP_RGB_ENHNC_MODE_BYPASS (0 << 18) ++#define IEP_RGB_ENHNC_MODE_DNS BIT(18) ++#define IEP_RGB_ENHNC_MODE_DTL (2 << 18) ++#define IEP_RGB_ENHNC_MODE_EDG (3 << 18) ++#define IEP_RGB_ENHNC_MODE_MASK (3 << 18) ++#define IEP_RGB_CNTRST_ENHNC_DDE_FRST BIT(20) ++#define IEP_DEIN_EDGE_INTPOL_RADIUS_SHFT 21 ++#define IEP_DEIN_EDGE_INTPOL_RADIUS_MASK (3 << IEP_DEIN_EDGE_INTPOL_RADIUS_SHFT) ++#define IEP_DEIN_EDGE_INTPOL_SELECT BIT(23) ++ ++#define IEP_CONFIG1 0x004 /* Configuration register1 */ ++#define IEP_SRC_FMT_SHFT 0 ++#define IEP_SRC_FMT_MASK (3 << IEP_SRC_FMT_SHFT) ++#define IEP_SRC_RGB_SWP_SHFT 2 ++#define IEP_SRC_RGB_SWP_MASK (2 << IEP_SRC_RGB_SWP_SHFT) ++#define IEP_SRC_YUV_SWP_SHFT 4 ++#define IEP_SRC_YUV_SWP_MASK (3 << IEP_SRC_YUV_SWP_SHFT) ++#define IEP_DST_FMT_SHFT 8 ++#define IEP_DST_FMT_MASK (3 << IEP_DST_FMT_SHFT) ++#define IEP_DST_RGB_SWP_SHFT 10 ++#define IEP_DST_RGB_SWP_MASK (2 << IEP_DST_RGB_SWP_SHFT) ++#define IEP_DST_YUV_SWP_SHFT 12 ++#define IEP_DST_YUV_SWP_MASK (3 << IEP_DST_YUV_SWP_SHFT) ++#define IEP_DTH_UP_EN BIT(14) ++#define IEP_DTH_DWN_EN BIT(15) ++#define IEP_YUV2RGB_COE_BT601_1 (0 << 16) ++#define IEP_YUV2RGB_COE_BT601_F BIT(16) ++#define IEP_YUV2RGB_COE_BT709_1 (2 << 16) ++#define IEP_YUV2RGB_COE_BT709_F (3 << 16) ++#define IEP_YUV2RGB_COE_MASK (3 << 16) ++#define IEP_RGB2YUV_COE_BT601_1 (0 << 18) ++#define IEP_RGB2YUV_COE_BT601_F BIT(18) ++#define IEP_RGB2YUV_COE_BT709_1 (2 << 18) ++#define IEP_RGB2YUV_COE_BT709_F (3 << 18) ++#define IEP_RGB2YUV_COE_MASK (3 << 18) ++#define IEP_YUV2RGB_EN BIT(20) ++#define IEP_RGB2YUV_EN BIT(21) ++#define IEP_YUV2RGB_CLIP_EN BIT(22) ++#define IEP_RGB2YUV_CLIP_EN BIT(23) ++#define IEP_GLB_ALPHA_SHFT 24 ++#define IEP_GLB_ALPHA_MASK (0x7f << IEP_GLB_ALPHA_SHFT) ++ ++#define IEP_STATUS 0x008 /* Status register */ ++#define IEP_STATUS_YUV_DNS BIT(0) ++#define IEP_STATUS_SCL BIT(1) ++#define IEP_STATUS_DIL BIT(2) ++#define IEP_STATUS_DDE BIT(3) ++#define IEP_STATUS_DMA_WR_YUV BIT(4) ++#define IEP_STATUS_DMA_RE_YUV BIT(5) ++#define IEP_STATUS_DMA_WR_RGB BIT(6) ++#define IEP_STATUS_DMA_RE_RGB BIT(7) ++#define IEP_STATUS_VOP_DIRECT_PATH BIT(8) ++#define IEP_STATUS_DMA_IA_WR_YUV BIT(16) ++#define IEP_STATUS_DMA_IA_RE_YUV BIT(17) ++#define IEP_STATUS_DMA_IA_WR_RGB BIT(18) ++#define IEP_STATUS_DMA_IA_RE_RGB BIT(19) ++ ++#define IEP_INT 0x00c /* Interrupt register*/ ++#define IEP_INT_FRAME_DONE BIT(0) /* Frame process done interrupt */ ++#define IEP_INT_FRAME_DONE_EN BIT(8) /* Frame process done interrupt enable */ ++#define IEP_INT_FRAME_DONE_CLR BIT(16) /* Frame process done interrupt clear */ ++ ++#define IEP_FRM_START 0x010 /* Frame start */ ++#define IEP_SRST 0x014 /* Soft reset */ ++#define IEP_CONFIG_DONE 0x018 /* Configuration done */ ++#define IEP_FRM_CNT 0x01c /* Frame counter */ ++ ++#define IEP_VIR_IMG_WIDTH 0x020 /* Image virtual width */ ++#define IEP_IMG_SCL_FCT 0x024 /* Scaling factor */ ++#define IEP_SRC_IMG_SIZE 0x028 /* src image width/height */ ++#define IEP_DST_IMG_SIZE 0x02c /* dst image width/height */ ++#define IEP_DST_IMG_WIDTH_TILE0 0x030 /* dst image tile0 width */ ++#define IEP_DST_IMG_WIDTH_TILE1 0x034 /* dst image tile1 width */ ++#define IEP_DST_IMG_WIDTH_TILE2 0x038 /* dst image tile2 width */ ++#define IEP_DST_IMG_WIDTH_TILE3 0x03c /* dst image tile3 width */ ++ ++#define IEP_ENH_YUV_CNFG_0 0x040 /* Brightness, contrast, saturation adjustment */ ++#define IEP_YUV_BRIGHTNESS_SHFT 0 ++#define IEP_YUV_BRIGHTNESS_MASK (0x3f << IEP_YUV_BRIGHTNESS_SHFT) ++#define IEP_YUV_CONTRAST_SHFT 8 ++#define IEP_YUV_CONTRAST_MASK (0xff << IEP_YUV_CONTRAST_SHFT) ++#define IEP_YUV_SATURATION_SHFT 16 ++#define IEP_YUV_SATURATION_MASK (0x1ff << IEP_YUV_SATURATION_SHFT) ++ ++#define IEP_ENH_YUV_CNFG_1 0x044 /* Hue configuration */ ++#define IEP_YUV_COS_HUE_SHFT 0 ++#define IEP_YUV_COS_HUE_MASK (0xff << IEP_YUV_COS_HUE_SHFT) ++#define IEP_YUV_SIN_HUE_SHFT 8 ++#define IEP_YUV_SIN_HUE_MASK (0xff << IEP_YUV_SIN_HUE_SHFT) ++ ++#define IEP_ENH_YUV_CNFG_2 0x048 /* Color bar configuration */ ++#define IEP_YUV_COLOR_BAR_Y_SHFT 0 ++#define IEP_YUV_COLOR_BAR_Y_MASK (0xff << IEP_YUV_COLOR_BAR_Y_SHFT) ++#define IEP_YUV_COLOR_BAR_U_SHFT 8 ++#define IEP_YUV_COLOR_BAR_U_MASK (0xff << IEP_YUV_COLOR_BAR_U_SHFT) ++#define IEP_YUV_COLOR_BAR_V_SHFT 16 ++#define IEP_YUV_COLOR_BAR_V_MASK (0xff << IEP_YUV_COLOR_BAR_V_SHFT) ++#define IEP_YUV_VIDEO_MODE_SHFT 24 ++#define IEP_YUV_VIDEO_MODE_MASK (3 << IEP_YUV_VIDEO_MODE_SHFT) ++ ++#define IEP_ENH_RGB_CNFG 0x04c /* RGB enhancement configuration */ ++#define IEP_ENH_RGB_C_COE 0x050 /* RGB color enhancement coefficient */ ++ ++#define IEP_RAW_CONFIG0 0x058 /* Raw configuration register0 */ ++#define IEP_RAW_CONFIG1 0x05c /* Raw configuration register1 */ ++#define IEP_RAW_VIR_IMG_WIDTH 0x060 /* Raw image virtual width */ ++#define IEP_RAW_IMG_SCL_FCT 0x064 /* Raw scaling factor */ ++#define IEP_RAW_SRC_IMG_SIZE 0x068 /* Raw src image width/height */ ++#define IEP_RAW_DST_IMG_SIZE 0x06c /* Raw src image width/height */ ++#define IEP_RAW_ENH_YUV_CNFG_0 0x070 /* Raw brightness,contrast,saturation adjustment */ ++#define IEP_RAW_ENH_YUV_CNFG_1 0x074 /* Raw hue configuration */ ++#define IEP_RAW_ENH_YUV_CNFG_2 0x078 /* Raw color bar configuration */ ++#define IEP_RAW_ENH_RGB_CNFG 0x07c /* Raw RGB enhancement configuration */ ++ ++#define IEP_SRC_ADDR_Y_RGB 0x080 /* Start addr. of src image 0 (Y/RGB) */ ++#define IEP_SRC_ADDR_CBCR 0x084 /* Start addr. of src image 0 (Cb/Cr) */ ++#define IEP_SRC_ADDR_CR 0x088 /* Start addr. of src image 0 (Cr) */ ++#define IEP_SRC_ADDR_Y1 0x08c /* Start addr. of src image 1 (Y) */ ++#define IEP_SRC_ADDR_CBCR1 0x090 /* Start addr. of src image 1 (Cb/Cr) */ ++#define IEP_SRC_ADDR_CR1 0x094 /* Start addr. of src image 1 (Cr) */ ++#define IEP_SRC_ADDR_Y_ITEMP 0x098 /* Start addr. of src image(Y int part) */ ++#define IEP_SRC_ADDR_CBCR_ITEMP 0x09c /* Start addr. of src image(CBCR int part) */ ++#define IEP_SRC_ADDR_CR_ITEMP 0x0a0 /* Start addr. of src image(CR int part) */ ++#define IEP_SRC_ADDR_Y_FTEMP 0x0a4 /* Start addr. of src image(Y frac part) */ ++#define IEP_SRC_ADDR_CBCR_FTEMP 0x0a8 /* Start addr. of src image(CBCR frac part) */ ++#define IEP_SRC_ADDR_CR_FTEMP 0x0ac /* Start addr. of src image(CR frac part) */ ++ ++#define IEP_DST_ADDR_Y_RGB 0x0b0 /* Start addr. of dst image 0 (Y/RGB) */ ++#define IEP_DST_ADDR_CBCR 0x0b4 /* Start addr. of dst image 0 (Cb/Cr) */ ++#define IEP_DST_ADDR_CR 0x0b8 /* Start addr. of dst image 0 (Cr) */ ++#define IEP_DST_ADDR_Y1 0x0bc /* Start addr. of dst image 1 (Y) */ ++#define IEP_DST_ADDR_CBCR1 0x0c0 /* Start addr. of dst image 1 (Cb/Cr) */ ++#define IEP_DST_ADDR_CR1 0x0c4 /* Start addr. of dst image 1 (Cr) */ ++#define IEP_DST_ADDR_Y_ITEMP 0x0c8 /* Start addr. of dst image(Y int part) */ ++#define IEP_DST_ADDR_CBCR_ITEMP 0x0cc /* Start addr. of dst image(CBCR int part)*/ ++#define IEP_DST_ADDR_CR_ITEMP 0x0d0 /* Start addr. of dst image(CR int part) */ ++#define IEP_DST_ADDR_Y_FTEMP 0x0d4 /* Start addr. of dst image(Y frac part) */ ++#define IEP_DST_ADDR_CBCR_FTEMP 0x0d8 /* Start addr. of dst image(CBCR frac part) */ ++#define IEP_DST_ADDR_CR_FTEMP 0x0dc /* Start addr. of dst image(CR frac part)*/ ++ ++#define IEP_DEIN_MTN_TAB0 0x0e0 /* Deinterlace motion table0 */ ++#define IEP_DEIN_MTN_TAB1 0x0e4 /* Deinterlace motion table1 */ ++#define IEP_DEIN_MTN_TAB2 0x0e8 /* Deinterlace motion table2 */ ++#define IEP_DEIN_MTN_TAB3 0x0ec /* Deinterlace motion table3 */ ++#define IEP_DEIN_MTN_TAB4 0x0f0 /* Deinterlace motion table4 */ ++#define IEP_DEIN_MTN_TAB5 0x0f4 /* Deinterlace motion table5 */ ++#define IEP_DEIN_MTN_TAB6 0x0f8 /* Deinterlace motion table6 */ ++#define IEP_DEIN_MTN_TAB7 0x0fc /* Deinterlace motion table7 */ ++ ++#define IEP_ENH_CG_TAB 0x100 /* Contrast and gamma enhancement table */ ++#define IEP_ENH_DDE_COE0 0x400 /* Denoise,detail and edge enhancement coefficient */ ++#define IEP_ENH_DDE_COE1 0x500 /* Denoise,detail and edge enhancement coefficient1 */ ++ ++#define IEP_INT_MASK (IEP_INT_FRAME_DONE) ++ ++/* IEP colorformats */ ++#define IEP_COLOR_FMT_XRGB 0U ++#define IEP_COLOR_FMT_RGB565 1U ++#define IEP_COLOR_FMT_YUV422 2U ++#define IEP_COLOR_FMT_YUV420 3U ++ ++/* IEP YUV color swaps */ ++#define IEP_YUV_SWP_SP_UV 0U ++#define IEP_YUV_SWP_SP_VU 1U ++#define IEP_YUV_SWP_P 2U ++ ++/* IEP XRGB color swaps */ ++#define XRGB_SWP_XRGB 0U ++#define XRGB_SWP_XBGR 1U ++#define XRGB_SWP_BGRX 2U ++ ++/* IEP RGB565 color swaps */ ++#define RGB565_SWP_RGB 0U ++#define RGB565_SWP_BGR 1U ++ ++#define FMT_IS_YUV(fmt) (fmt == IEP_COLOR_FMT_XRGB || fmt == IEP_COLOR_FMT_RGB565 ? 0 : 1) ++ ++#define IEP_IMG_SIZE(w, h) (((w - 1) & 0x1fff) << 0 | \ ++ ((h - 1) & 0x1fff) << 16) ++ ++#define IEP_VIR_WIDTH(src_w, dst_w) (((src_w / 4) & 0x1fff) << 0 | \ ++ ((dst_w / 4) & 0x1fff) << 16) ++ ++#define IEP_Y_STRIDE(w, h) (w * h) ++#define IEP_UV_STRIDE(w, h, fac) (w * h + w * h / fac) ++ ++#define IEP_SRC_FMT_SWP_MASK(f) (FMT_IS_YUV(f) ? IEP_SRC_YUV_SWP_MASK : IEP_SRC_RGB_SWP_MASK) ++#define IEP_DST_FMT_SWP_MASK(f) (FMT_IS_YUV(f) ? IEP_DST_YUV_SWP_MASK : IEP_DST_RGB_SWP_MASK) ++ ++#define IEP_SRC_FMT(f, swp) (f << IEP_SRC_FMT_SHFT | \ ++ (swp << (FMT_IS_YUV(f) ? IEP_SRC_YUV_SWP_SHFT : IEP_SRC_RGB_SWP_SHFT))) ++#define IEP_DST_FMT(f, swp) (f << IEP_DST_FMT_SHFT | \ ++ (swp << (FMT_IS_YUV(f) ? IEP_DST_YUV_SWP_SHFT : IEP_DST_RGB_SWP_SHFT))) ++ ++/* IEP DEINTERLACE MODES */ ++#define IEP_DEIN_MODE_YUV 0U ++#define IEP_DEIN_MODE_I4O2 1U ++#define IEP_DEIN_MODE_I4O1B 2U ++#define IEP_DEIN_MODE_I4O1T 3U ++#define IEP_DEIN_MODE_I2O1B 4U ++#define IEP_DEIN_MODE_I2O1T 5U ++#define IEP_DEIN_MODE_BYPASS 6U ++ ++#define IEP_DEIN_IN_FIELDS_2 2U ++#define IEP_DEIN_IN_FIELDS_4 4U ++ ++#define IEP_DEIN_OUT_FRAMES_1 1U ++#define IEP_DEIN_OUT_FRAMES_2 2U ++ ++/* values taken from BSP driver */ ++static const u32 default_dein_motion_tbl[][2] = { ++ { IEP_DEIN_MTN_TAB0, 0x40404040 }, ++ { IEP_DEIN_MTN_TAB1, 0x3c3e3f3f }, ++ { IEP_DEIN_MTN_TAB2, 0x3336393b }, ++ { IEP_DEIN_MTN_TAB3, 0x272a2d31 }, ++ { IEP_DEIN_MTN_TAB4, 0x181c2023 }, ++ { IEP_DEIN_MTN_TAB5, 0x0c0e1215 }, ++ { IEP_DEIN_MTN_TAB6, 0x03040609 }, ++ { IEP_DEIN_MTN_TAB7, 0x00000001 }, ++ ++}; ++ ++#define IEP_DEIN_IN_IMG0_Y(bff) (bff ? IEP_SRC_ADDR_Y_RGB : IEP_SRC_ADDR_Y1) ++#define IEP_DEIN_IN_IMG0_CBCR(bff) (bff ? IEP_SRC_ADDR_CBCR : IEP_SRC_ADDR_CBCR1) ++#define IEP_DEIN_IN_IMG0_CR(bff) (bff ? IEP_SRC_ADDR_CR : IEP_SRC_ADDR_CR1) ++#define IEP_DEIN_IN_IMG1_Y(bff) (IEP_DEIN_IN_IMG0_Y(!bff)) ++#define IEP_DEIN_IN_IMG1_CBCR(bff) (IEP_DEIN_IN_IMG0_CBCR(!bff)) ++#define IEP_DEIN_IN_IMG1_CR(bff) (IEP_DEIN_IN_IMG0_CR(!bff)) ++ ++#define IEP_DEIN_OUT_IMG0_Y(bff) (bff ? IEP_DST_ADDR_Y1 : IEP_DST_ADDR_Y_RGB) ++#define IEP_DEIN_OUT_IMG0_CBCR(bff) (bff ? IEP_DST_ADDR_CBCR1 : IEP_DST_ADDR_CBCR) ++#define IEP_DEIN_OUT_IMG0_CR(bff) (bff ? IEP_DST_ADDR_CR1 : IEP_DST_ADDR_CR) ++#define IEP_DEIN_OUT_IMG1_Y(bff) (IEP_DEIN_OUT_IMG0_Y(!bff)) ++#define IEP_DEIN_OUT_IMG1_CBCR(bff) (IEP_DEIN_OUT_IMG0_CBCR(!bff)) ++#define IEP_DEIN_OUT_IMG1_CR(bff) (IEP_DEIN_OUT_IMG0_CR(!bff)) ++ ++#define IEP_DEIN_MODE(m) (m << IEP_DEIN_MODE_SHFT) ++ ++#define IEP_DEIN_IN_MODE_FIELDS(m) ((m == IEP_DEIN_MODE_I4O1T || m == IEP_DEIN_MODE_I4O1B \ ++ || m == IEP_DEIN_MODE_I4O2) \ ++ ? IEP_DEIN_IN_FIELDS_4 : IEP_DEIN_IN_FIELDS_2) ++ ++#define IEP_DEIN_OUT_MODE_FRAMES(m) (m == IEP_DEIN_MODE_I4O2 \ ++ ? IEP_DEIN_OUT_FRAMES_2 : IEP_DEIN_OUT_FRAMES_1) ++ ++#define IEP_DEIN_OUT_MODE_1FRM_TOP_FIELD(m) (m == IEP_DEIN_MODE_I4O1T || IEP_DEIN_MODE_I2O1T \ ++ ? 1 : 0) ++ ++#define IEP_DEIN_EDGE_INTPOL_RADIUS(r) (r << IEP_DEIN_EDGE_INTPOL_RADIUS_SHFT) ++ ++#define IEP_DEIN_HIGH_FREQ(f) (f << IEP_DEIN_HIGH_FREQ_SHFT) ++ ++/* YUV Enhance video modes */ ++#define VIDEO_MODE_BLACK_SCREEN 0U ++#define VIDEO_MODE_BLUE_SCREEN 1U ++#define VIDEO_MODE_COLOR_BARS 2U ++#define VIDEO_MODE_NORMAL_VIDEO 3U ++ ++#define YUV_VIDEO_MODE(m) ((m << IEP_YUV_VIDEO_MODE_SHFT) & IEP_YUV_VIDEO_MODE_MASK) ++#define YUV_BRIGHTNESS(v) ((v << IEP_YUV_BRIGHTNESS_SHFT) & IEP_YUV_BRIGHTNESS_MASK) ++#define YUV_CONTRAST(v) ((v << IEP_YUV_CONTRAST_SHFT) & IEP_YUV_CONTRAST_MASK) ++#define YUV_SATURATION(v) ((v << IEP_YUV_SATURATION_SHFT) & IEP_YUV_SATURATION_MASK) ++#define YUV_COS_HUE(v) ((v << IEP_YUV_COS_HUE_SHFT) & IEP_YUV_COS_HUE_MASK) ++#define YUV_SIN_HUE(v) ((v << IEP_YUV_SIN_HUE_SHFT) & IEP_YUV_SIN_HUE_MASK) ++ ++#endif +diff --git a/drivers/media/platform/rockchip/iep/iep.c b/drivers/media/platform/rockchip/iep/iep.c +new file mode 100644 +index 000000000000..f4b9320733be +--- /dev/null ++++ b/drivers/media/platform/rockchip/iep/iep.c +@@ -0,0 +1,1087 @@ ++// SPDX-License-Identifier: GPL-2.0-only ++/* ++ * Rockchip Image Enhancement Processor (IEP) driver ++ * ++ * Copyright (C) 2020 Alex Bee ++ * ++ * Based on Allwinner sun8i deinterlacer with scaler driver ++ * Copyright (C) 2019 Jernej Skrabec ++ * ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include "iep-regs.h" ++#include "iep.h" ++ ++static struct iep_fmt formats[] = { ++ { ++ .fourcc = V4L2_PIX_FMT_NV12, ++ .color_swap = IEP_YUV_SWP_SP_UV, ++ .hw_format = IEP_COLOR_FMT_YUV420, ++ .depth = 12, ++ .uv_factor = 4, ++ }, ++ { ++ .fourcc = V4L2_PIX_FMT_NV21, ++ .color_swap = IEP_YUV_SWP_SP_VU, ++ .hw_format = IEP_COLOR_FMT_YUV420, ++ .depth = 12, ++ .uv_factor = 4, ++ }, ++ { ++ .fourcc = V4L2_PIX_FMT_NV16, ++ .color_swap = IEP_YUV_SWP_SP_UV, ++ .hw_format = IEP_COLOR_FMT_YUV422, ++ .depth = 16, ++ .uv_factor = 2, ++ }, ++ { ++ .fourcc = V4L2_PIX_FMT_NV61, ++ .color_swap = IEP_YUV_SWP_SP_VU, ++ .hw_format = IEP_COLOR_FMT_YUV422, ++ .depth = 16, ++ .uv_factor = 2, ++ }, ++ { ++ .fourcc = V4L2_PIX_FMT_YUV420, ++ .color_swap = IEP_YUV_SWP_P, ++ .hw_format = IEP_COLOR_FMT_YUV420, ++ .depth = 12, ++ .uv_factor = 4, ++ }, ++ { ++ .fourcc = V4L2_PIX_FMT_YUV422P, ++ .color_swap = IEP_YUV_SWP_P, ++ .hw_format = IEP_COLOR_FMT_YUV422, ++ .depth = 16, ++ .uv_factor = 2, ++ }, ++}; ++ ++static struct iep_fmt *iep_fmt_find(struct v4l2_pix_format *pix_fmt) ++{ ++ unsigned int i; ++ ++ for (i = 0; i < ARRAY_SIZE(formats); i++) { ++ if (formats[i].fourcc == pix_fmt->pixelformat) ++ return &formats[i]; ++ } ++ ++ return NULL; ++} ++ ++static bool iep_check_pix_format(u32 pixelformat) ++{ ++ unsigned int i; ++ ++ for (i = 0; i < ARRAY_SIZE(formats); i++) ++ if (formats[i].fourcc == pixelformat) ++ return true; ++ ++ return false; ++} ++ ++static struct vb2_v4l2_buffer *iep_m2m_next_dst_buf(struct iep_ctx *ctx) ++{ ++ struct vb2_v4l2_buffer *dst_buf = v4l2_m2m_next_dst_buf(ctx->fh.m2m_ctx); ++ ++ /* application has set a dst sequence: take it as start point */ ++ if (ctx->dst_sequence == 0 && dst_buf->sequence > 0) ++ ctx->dst_sequence = dst_buf->sequence; ++ ++ dst_buf->sequence = ctx->dst_sequence++; ++ ++ return dst_buf; ++} ++ ++static void iep_m2m_dst_bufs_done(struct iep_ctx *ctx, enum vb2_buffer_state state) ++{ ++ if (ctx->dst0_buf) { ++ v4l2_m2m_buf_done(ctx->dst0_buf, state); ++ ctx->dst_buffs_done++; ++ ctx->dst0_buf = NULL; ++ } ++ ++ if (ctx->dst1_buf) { ++ v4l2_m2m_buf_done(ctx->dst1_buf, state); ++ ctx->dst_buffs_done++; ++ ctx->dst1_buf = NULL; ++ } ++} ++ ++static void iep_setup_formats(struct iep_ctx *ctx) ++{ ++ /* setup src dimensions */ ++ iep_write(ctx->iep, IEP_SRC_IMG_SIZE, ++ IEP_IMG_SIZE(ctx->src_fmt.pix.width, ctx->src_fmt.pix.height)); ++ ++ /* setup dst dimensions */ ++ iep_write(ctx->iep, IEP_DST_IMG_SIZE, ++ IEP_IMG_SIZE(ctx->dst_fmt.pix.width, ctx->dst_fmt.pix.height)); ++ ++ /* setup virtual width */ ++ iep_write(ctx->iep, IEP_VIR_IMG_WIDTH, ++ IEP_VIR_WIDTH(ctx->src_fmt.pix.width, ctx->dst_fmt.pix.width)); ++ ++ /* setup src format */ ++ iep_shadow_mod(ctx->iep, IEP_CONFIG1, IEP_RAW_CONFIG1, ++ IEP_SRC_FMT_MASK | IEP_SRC_FMT_SWP_MASK(ctx->src_fmt.hw_fmt->hw_format), ++ IEP_SRC_FMT(ctx->src_fmt.hw_fmt->hw_format, ++ ctx->src_fmt.hw_fmt->color_swap)); ++ /* setup dst format */ ++ iep_shadow_mod(ctx->iep, IEP_CONFIG1, IEP_RAW_CONFIG1, ++ IEP_DST_FMT_MASK | IEP_DST_FMT_SWP_MASK(ctx->dst_fmt.hw_fmt->hw_format), ++ IEP_DST_FMT(ctx->dst_fmt.hw_fmt->hw_format, ++ ctx->dst_fmt.hw_fmt->color_swap)); ++ ++ ctx->fmt_changed = false; ++} ++ ++static void iep_dein_init(struct rockchip_iep *iep) ++{ ++ unsigned int i; ++ ++ /* values taken from BSP driver */ ++ iep_shadow_mod(iep, IEP_CONFIG0, IEP_RAW_CONFIG0, ++ (IEP_DEIN_EDGE_INTPOL_SMTH_EN | ++ IEP_DEIN_EDGE_INTPOL_RADIUS_MASK | ++ IEP_DEIN_HIGH_FREQ_EN | ++ IEP_DEIN_HIGH_FREQ_MASK), ++ (IEP_DEIN_EDGE_INTPOL_SMTH_EN | ++ IEP_DEIN_EDGE_INTPOL_RADIUS(3) | ++ IEP_DEIN_HIGH_FREQ_EN | ++ IEP_DEIN_HIGH_FREQ(64))); ++ ++ for (i = 0; i < ARRAY_SIZE(default_dein_motion_tbl); i++) ++ iep_write(iep, default_dein_motion_tbl[i][0], ++ default_dein_motion_tbl[i][1]); ++} ++ ++static void iep_init(struct rockchip_iep *iep) ++{ ++ iep_write(iep, IEP_CONFIG0, ++ IEP_DEIN_MODE(IEP_DEIN_MODE_BYPASS) // | ++ //IEP_YUV_ENHNC_EN ++ ); ++ ++ /* TODO: B/S/C/H works ++ * only in 1-frame-out modes ++ iep_write(iep, IEP_ENH_YUV_CNFG_0, ++ YUV_BRIGHTNESS(0) | ++ YUV_CONTRAST(128) | ++ YUV_SATURATION(128)); ++ ++ iep_write(iep, IEP_ENH_YUV_CNFG_1, ++ YUV_COS_HUE(255) | ++ YUV_SIN_HUE(255)); ++ ++ iep_write(iep, IEP_ENH_YUV_CNFG_2, ++ YUV_VIDEO_MODE(VIDEO_MODE_NORMAL_VIDEO)); ++ ++ */ ++ ++ /* reset frame counter */ ++ iep_write(iep, IEP_FRM_CNT, 0); ++} ++ ++static void iep_device_run(void *priv) ++{ ++ struct iep_ctx *ctx = priv; ++ struct rockchip_iep *iep = ctx->iep; ++ struct vb2_v4l2_buffer *src, *dst; ++ unsigned int dein_mode; ++ dma_addr_t addr; ++ ++ if (ctx->fmt_changed) ++ iep_setup_formats(ctx); ++ ++ if (ctx->prev_src_buf) ++ dein_mode = IEP_DEIN_MODE_I4O2; ++ else ++ dein_mode = ctx->field_bff ? IEP_DEIN_MODE_I2O1B : IEP_DEIN_MODE_I2O1T; ++ ++ iep_shadow_mod(iep, IEP_CONFIG0, IEP_RAW_CONFIG0, ++ IEP_DEIN_MODE_MASK, IEP_DEIN_MODE(dein_mode)); ++ ++ /* sync RAW_xxx registers with actual used */ ++ iep_write(iep, IEP_CONFIG_DONE, 1); ++ ++ /* setup src buff(s)/addresses */ ++ src = v4l2_m2m_next_src_buf(ctx->fh.m2m_ctx); ++ addr = vb2_dma_contig_plane_dma_addr(&src->vb2_buf, 0); ++ ++ iep_write(iep, IEP_DEIN_IN_IMG0_Y(ctx->field_bff), addr); ++ ++ iep_write(iep, IEP_DEIN_IN_IMG0_CBCR(ctx->field_bff), ++ addr + ctx->src_fmt.y_stride); ++ ++ iep_write(iep, IEP_DEIN_IN_IMG0_CR(ctx->field_bff), ++ addr + ctx->src_fmt.uv_stride); ++ ++ if (IEP_DEIN_IN_MODE_FIELDS(dein_mode) == IEP_DEIN_IN_FIELDS_4) ++ addr = vb2_dma_contig_plane_dma_addr(&ctx->prev_src_buf->vb2_buf, 0); ++ ++ iep_write(iep, IEP_DEIN_IN_IMG1_Y(ctx->field_bff), addr); ++ ++ iep_write(iep, IEP_DEIN_IN_IMG1_CBCR(ctx->field_bff), ++ addr + ctx->src_fmt.y_stride); ++ ++ iep_write(iep, IEP_DEIN_IN_IMG1_CR(ctx->field_bff), ++ addr + ctx->src_fmt.uv_stride); ++ ++ /* setup dst buff(s)/addresses */ ++ dst = iep_m2m_next_dst_buf(ctx); ++ addr = vb2_dma_contig_plane_dma_addr(&dst->vb2_buf, 0); ++ ++ if (IEP_DEIN_OUT_MODE_FRAMES(dein_mode) == IEP_DEIN_OUT_FRAMES_2) { ++ v4l2_m2m_buf_copy_metadata(ctx->prev_src_buf, dst, true); ++ ++ iep_write(iep, IEP_DEIN_OUT_IMG0_Y(ctx->field_bff), addr); ++ ++ iep_write(iep, IEP_DEIN_OUT_IMG0_CBCR(ctx->field_bff), ++ addr + ctx->dst_fmt.y_stride); ++ ++ iep_write(iep, IEP_DEIN_OUT_IMG0_CR(ctx->field_bff), ++ addr + ctx->dst_fmt.uv_stride); ++ ++ ctx->dst0_buf = v4l2_m2m_dst_buf_remove(ctx->fh.m2m_ctx); ++ ++ dst = iep_m2m_next_dst_buf(ctx); ++ addr = vb2_dma_contig_plane_dma_addr(&dst->vb2_buf, 0); ++ } ++ ++ v4l2_m2m_buf_copy_metadata(src, dst, true); ++ ++ iep_write(iep, IEP_DEIN_OUT_IMG1_Y(ctx->field_bff), addr); ++ ++ iep_write(iep, IEP_DEIN_OUT_IMG1_CBCR(ctx->field_bff), ++ addr + ctx->dst_fmt.y_stride); ++ ++ iep_write(iep, IEP_DEIN_OUT_IMG1_CR(ctx->field_bff), ++ addr + ctx->dst_fmt.uv_stride); ++ ++ ctx->dst1_buf = v4l2_m2m_dst_buf_remove(ctx->fh.m2m_ctx); ++ ++ iep_mod(ctx->iep, IEP_INT, IEP_INT_FRAME_DONE_EN, ++ IEP_INT_FRAME_DONE_EN); ++ ++ /* start HW */ ++ iep_write(iep, IEP_FRM_START, 1); ++} ++ ++static int iep_job_ready(void *priv) ++{ ++ struct iep_ctx *ctx = priv; ++ ++ return v4l2_m2m_num_dst_bufs_ready(ctx->fh.m2m_ctx) >= 2 && ++ v4l2_m2m_num_src_bufs_ready(ctx->fh.m2m_ctx) >= 1; ++} ++ ++static void iep_job_abort(void *priv) ++{ ++ struct iep_ctx *ctx = priv; ++ ++ /* Will cancel the transaction in the next interrupt handler */ ++ ctx->job_abort = true; ++} ++ ++static const struct v4l2_m2m_ops iep_m2m_ops = { ++ .device_run = iep_device_run, ++ .job_ready = iep_job_ready, ++ .job_abort = iep_job_abort, ++}; ++ ++static int iep_queue_setup(struct vb2_queue *vq, unsigned int *nbuffers, ++ unsigned int *nplanes, unsigned int sizes[], ++ struct device *alloc_devs[]) ++{ ++ struct iep_ctx *ctx = vb2_get_drv_priv(vq); ++ struct v4l2_pix_format *pix_fmt; ++ ++ if (V4L2_TYPE_IS_OUTPUT(vq->type)) ++ pix_fmt = &ctx->src_fmt.pix; ++ else ++ pix_fmt = &ctx->dst_fmt.pix; ++ ++ if (*nplanes) { ++ if (sizes[0] < pix_fmt->sizeimage) ++ return -EINVAL; ++ } else { ++ sizes[0] = pix_fmt->sizeimage; ++ *nplanes = 1; ++ } ++ ++ return 0; ++} ++ ++static int iep_buf_prepare(struct vb2_buffer *vb) ++{ ++ struct vb2_queue *vq = vb->vb2_queue; ++ struct iep_ctx *ctx = vb2_get_drv_priv(vq); ++ struct v4l2_pix_format *pix_fmt; ++ ++ if (V4L2_TYPE_IS_OUTPUT(vq->type)) ++ pix_fmt = &ctx->src_fmt.pix; ++ else ++ pix_fmt = &ctx->dst_fmt.pix; ++ ++ if (vb2_plane_size(vb, 0) < pix_fmt->sizeimage) ++ return -EINVAL; ++ ++ /* set bytesused for capture buffers */ ++ if (!V4L2_TYPE_IS_OUTPUT(vq->type)) ++ vb2_set_plane_payload(vb, 0, pix_fmt->sizeimage); ++ ++ return 0; ++} ++ ++static void iep_buf_queue(struct vb2_buffer *vb) ++{ ++ struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb); ++ struct iep_ctx *ctx = vb2_get_drv_priv(vb->vb2_queue); ++ ++ v4l2_m2m_buf_queue(ctx->fh.m2m_ctx, vbuf); ++} ++ ++static void iep_queue_cleanup(struct vb2_queue *vq, u32 state) ++{ ++ struct iep_ctx *ctx = vb2_get_drv_priv(vq); ++ struct vb2_v4l2_buffer *vbuf; ++ ++ do { ++ if (V4L2_TYPE_IS_OUTPUT(vq->type)) ++ vbuf = v4l2_m2m_src_buf_remove(ctx->fh.m2m_ctx); ++ else ++ vbuf = v4l2_m2m_dst_buf_remove(ctx->fh.m2m_ctx); ++ ++ if (vbuf) ++ v4l2_m2m_buf_done(vbuf, state); ++ } while (vbuf); ++ ++ if (V4L2_TYPE_IS_OUTPUT(vq->type) && ctx->prev_src_buf) ++ v4l2_m2m_buf_done(ctx->prev_src_buf, state); ++ else ++ iep_m2m_dst_bufs_done(ctx, state); ++} ++ ++static int iep_start_streaming(struct vb2_queue *vq, unsigned int count) ++{ ++ struct iep_ctx *ctx = vb2_get_drv_priv(vq); ++ struct device *dev = ctx->iep->dev; ++ int ret; ++ ++ if (V4L2_TYPE_IS_OUTPUT(vq->type)) { ++ ret = pm_runtime_get_sync(dev); ++ if (ret < 0) { ++ dev_err(dev, "Failed to enable module\n"); ++ goto err_runtime_get; ++ } ++ ++ ctx->field_order_bff = ++ ctx->src_fmt.pix.field == V4L2_FIELD_INTERLACED_BT; ++ ctx->field_bff = ctx->field_order_bff; ++ ++ ctx->src_sequence = 0; ++ ctx->dst_sequence = 0; ++ ++ ctx->prev_src_buf = NULL; ++ ++ ctx->dst0_buf = NULL; ++ ctx->dst1_buf = NULL; ++ ctx->dst_buffs_done = 0; ++ ++ ctx->job_abort = false; ++ ++ iep_init(ctx->iep); ++ //if (ctx->src_fmt.pix.field != ctx->dst_fmt.pix.field) ++ iep_dein_init(ctx->iep); ++ } ++ ++ return 0; ++ ++err_runtime_get: ++ iep_queue_cleanup(vq, VB2_BUF_STATE_QUEUED); ++ ++ return ret; ++} ++ ++static void iep_stop_streaming(struct vb2_queue *vq) ++{ ++ struct iep_ctx *ctx = vb2_get_drv_priv(vq); ++ ++ if (V4L2_TYPE_IS_OUTPUT(vq->type)) { ++ pm_runtime_mark_last_busy(ctx->iep->dev); ++ pm_runtime_put_autosuspend(ctx->iep->dev); ++ } ++ ++ iep_queue_cleanup(vq, VB2_BUF_STATE_ERROR); ++} ++ ++static const struct vb2_ops iep_qops = { ++ .queue_setup = iep_queue_setup, ++ .buf_prepare = iep_buf_prepare, ++ .buf_queue = iep_buf_queue, ++ .start_streaming = iep_start_streaming, ++ .stop_streaming = iep_stop_streaming, ++ .wait_prepare = vb2_ops_wait_prepare, ++ .wait_finish = vb2_ops_wait_finish, ++}; ++ ++static int iep_queue_init(void *priv, struct vb2_queue *src_vq, ++ struct vb2_queue *dst_vq) ++{ ++ struct iep_ctx *ctx = priv; ++ int ret; ++ ++ src_vq->type = V4L2_BUF_TYPE_VIDEO_OUTPUT; ++ src_vq->dma_attrs = DMA_ATTR_ALLOC_SINGLE_PAGES | ++ DMA_ATTR_NO_KERNEL_MAPPING; ++ src_vq->io_modes = VB2_MMAP | VB2_DMABUF; ++ src_vq->drv_priv = ctx; ++ src_vq->buf_struct_size = sizeof(struct v4l2_m2m_buffer); ++ src_vq->min_queued_buffers = 1; ++ src_vq->ops = &iep_qops; ++ src_vq->mem_ops = &vb2_dma_contig_memops; ++ src_vq->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_COPY; ++ src_vq->lock = &ctx->iep->mutex; ++ src_vq->dev = ctx->iep->v4l2_dev.dev; ++ ++ ret = vb2_queue_init(src_vq); ++ if (ret) ++ return ret; ++ ++ dst_vq->dma_attrs = DMA_ATTR_ALLOC_SINGLE_PAGES | ++ DMA_ATTR_NO_KERNEL_MAPPING; ++ dst_vq->type = V4L2_BUF_TYPE_VIDEO_CAPTURE; ++ dst_vq->io_modes = VB2_MMAP | VB2_DMABUF; ++ dst_vq->drv_priv = ctx; ++ dst_vq->buf_struct_size = sizeof(struct v4l2_m2m_buffer); ++ dst_vq->min_queued_buffers = 2; ++ dst_vq->ops = &iep_qops; ++ dst_vq->mem_ops = &vb2_dma_contig_memops; ++ dst_vq->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_COPY; ++ dst_vq->lock = &ctx->iep->mutex; ++ dst_vq->dev = ctx->iep->v4l2_dev.dev; ++ ++ ret = vb2_queue_init(dst_vq); ++ if (ret) ++ return ret; ++ ++ return 0; ++} ++ ++static void iep_prepare_format(struct v4l2_pix_format *pix_fmt) ++{ ++ unsigned int height = pix_fmt->height; ++ unsigned int width = pix_fmt->width; ++ unsigned int sizeimage, bytesperline; ++ ++ struct iep_fmt *hw_fmt = iep_fmt_find(pix_fmt); ++ ++ if (!hw_fmt) { ++ hw_fmt = &formats[0]; ++ pix_fmt->pixelformat = hw_fmt->fourcc; ++ } ++ ++ width = ALIGN(clamp(width, IEP_MIN_WIDTH, ++ IEP_MAX_WIDTH), 16); ++ height = ALIGN(clamp(height, IEP_MIN_HEIGHT, ++ IEP_MAX_HEIGHT), 16); ++ ++ bytesperline = FMT_IS_YUV(hw_fmt->hw_format) ++ ? width : (width * hw_fmt->depth) >> 3; ++ ++ sizeimage = height * (width * hw_fmt->depth) >> 3; ++ ++ pix_fmt->width = width; ++ pix_fmt->height = height; ++ pix_fmt->bytesperline = bytesperline; ++ pix_fmt->sizeimage = sizeimage; ++} ++ ++static int iep_open(struct file *file) ++{ ++ struct rockchip_iep *iep = video_drvdata(file); ++ struct iep_ctx *ctx = NULL; ++ ++ int ret; ++ ++ if (mutex_lock_interruptible(&iep->mutex)) ++ return -ERESTARTSYS; ++ ++ ctx = kzalloc(sizeof(*ctx), GFP_KERNEL); ++ if (!ctx) { ++ mutex_unlock(&iep->mutex); ++ return -ENOMEM; ++ } ++ ++ /* default output format */ ++ ctx->src_fmt.pix.pixelformat = formats[0].fourcc; ++ ctx->src_fmt.pix.field = V4L2_FIELD_INTERLACED; ++ ctx->src_fmt.pix.width = IEP_DEFAULT_WIDTH; ++ ctx->src_fmt.pix.height = IEP_DEFAULT_HEIGHT; ++ iep_prepare_format(&ctx->src_fmt.pix); ++ ctx->src_fmt.hw_fmt = &formats[0]; ++ ctx->dst_fmt.y_stride = IEP_Y_STRIDE(ctx->src_fmt.pix.width, ctx->src_fmt.pix.height); ++ ctx->dst_fmt.uv_stride = IEP_UV_STRIDE(ctx->src_fmt.pix.width, ctx->src_fmt.pix.height, ++ ctx->src_fmt.hw_fmt->uv_factor); ++ ++ /* default capture format */ ++ ctx->dst_fmt.pix.pixelformat = formats[0].fourcc; ++ ctx->dst_fmt.pix.field = V4L2_FIELD_NONE; ++ ctx->dst_fmt.pix.width = IEP_DEFAULT_WIDTH; ++ ctx->dst_fmt.pix.height = IEP_DEFAULT_HEIGHT; ++ iep_prepare_format(&ctx->dst_fmt.pix); ++ ctx->dst_fmt.hw_fmt = &formats[0]; ++ ctx->dst_fmt.y_stride = IEP_Y_STRIDE(ctx->dst_fmt.pix.width, ctx->dst_fmt.pix.height); ++ ctx->dst_fmt.uv_stride = IEP_UV_STRIDE(ctx->dst_fmt.pix.width, ctx->dst_fmt.pix.height, ++ ctx->dst_fmt.hw_fmt->uv_factor); ++ /* ensure fmts are written to HW */ ++ ctx->fmt_changed = true; ++ ++ v4l2_fh_init(&ctx->fh, video_devdata(file)); ++ file->private_data = &ctx->fh; ++ ctx->iep = iep; ++ ++ ctx->fh.m2m_ctx = v4l2_m2m_ctx_init(iep->m2m_dev, ctx, ++ &iep_queue_init); ++ ++ if (IS_ERR(ctx->fh.m2m_ctx)) { ++ ret = PTR_ERR(ctx->fh.m2m_ctx); ++ goto err_free; ++ } ++ ++ v4l2_fh_add(&ctx->fh); ++ ++ mutex_unlock(&iep->mutex); ++ ++ return 0; ++ ++err_free: ++ kfree(ctx); ++ mutex_unlock(&iep->mutex); ++ ++ return ret; ++} ++ ++static int iep_release(struct file *file) ++{ ++ struct rockchip_iep *iep = video_drvdata(file); ++ struct iep_ctx *ctx = container_of(file->private_data, ++ struct iep_ctx, fh); ++ ++ mutex_lock(&iep->mutex); ++ ++ v4l2_fh_del(&ctx->fh); ++ v4l2_fh_exit(&ctx->fh); ++ v4l2_m2m_ctx_release(ctx->fh.m2m_ctx); ++ kfree(ctx); ++ ++ mutex_unlock(&iep->mutex); ++ return 0; ++} ++ ++static const struct v4l2_file_operations iep_fops = { ++ .owner = THIS_MODULE, ++ .open = iep_open, ++ .release = iep_release, ++ .poll = v4l2_m2m_fop_poll, ++ .unlocked_ioctl = video_ioctl2, ++ .mmap = v4l2_m2m_fop_mmap, ++}; ++ ++static int iep_querycap(struct file *file, void *priv, ++ struct v4l2_capability *cap) ++{ ++ strscpy(cap->driver, IEP_NAME, sizeof(cap->driver)); ++ strscpy(cap->card, IEP_NAME, sizeof(cap->card)); ++ snprintf(cap->bus_info, sizeof(cap->bus_info), ++ "platform:%s", IEP_NAME); ++ ++ return 0; ++} ++ ++static int iep_enum_fmt(struct file *file, void *priv, ++ struct v4l2_fmtdesc *f) ++{ ++ struct iep_fmt *fmt; ++ ++ if (f->index < ARRAY_SIZE(formats)) { ++ fmt = &formats[f->index]; ++ f->pixelformat = fmt->fourcc; ++ ++ return 0; ++ } ++ ++ return -EINVAL; ++} ++ ++static int iep_enum_framesizes(struct file *file, void *priv, ++ struct v4l2_frmsizeenum *fsize) ++{ ++ if (fsize->index != 0) ++ return -EINVAL; ++ ++ if (!iep_check_pix_format(fsize->pixel_format)) ++ return -EINVAL; ++ ++ fsize->type = V4L2_FRMSIZE_TYPE_STEPWISE; ++ ++ fsize->stepwise.min_width = IEP_MIN_WIDTH; ++ fsize->stepwise.max_width = IEP_MAX_WIDTH; ++ fsize->stepwise.step_width = 16; ++ ++ fsize->stepwise.min_height = IEP_MIN_HEIGHT; ++ fsize->stepwise.max_height = IEP_MAX_HEIGHT; ++ fsize->stepwise.step_height = 16; ++ ++ return 0; ++} ++ ++static inline struct iep_ctx *iep_file2ctx(struct file *file) ++{ ++ return container_of(file->private_data, struct iep_ctx, fh); ++} ++ ++static int iep_g_fmt_vid_cap(struct file *file, void *priv, ++ struct v4l2_format *f) ++{ ++ struct iep_ctx *ctx = iep_file2ctx(file); ++ ++ f->fmt.pix = ctx->dst_fmt.pix; ++ ++ return 0; ++} ++ ++static int iep_g_fmt_vid_out(struct file *file, void *priv, ++ struct v4l2_format *f) ++{ ++ struct iep_ctx *ctx = iep_file2ctx(file); ++ ++ f->fmt.pix = ctx->src_fmt.pix; ++ ++ return 0; ++} ++ ++static int iep_try_fmt_vid_cap(struct file *file, void *priv, ++ struct v4l2_format *f) ++{ ++ f->fmt.pix.field = V4L2_FIELD_NONE; ++ iep_prepare_format(&f->fmt.pix); ++ ++ return 0; ++} ++ ++static int iep_try_fmt_vid_out(struct file *file, void *priv, ++ struct v4l2_format *f) ++{ ++ if (f->fmt.pix.field != V4L2_FIELD_INTERLACED_TB && ++ f->fmt.pix.field != V4L2_FIELD_INTERLACED_BT && ++ f->fmt.pix.field != V4L2_FIELD_INTERLACED) ++ f->fmt.pix.field = V4L2_FIELD_INTERLACED; ++ ++ iep_prepare_format(&f->fmt.pix); ++ ++ return 0; ++} ++ ++static int iep_s_fmt_vid_out(struct file *file, void *priv, ++ struct v4l2_format *f) ++{ ++ struct iep_ctx *ctx = iep_file2ctx(file); ++ struct vb2_queue *vq; ++ ++ int ret; ++ ++ ret = iep_try_fmt_vid_out(file, priv, f); ++ if (ret) ++ return ret; ++ ++ vq = v4l2_m2m_get_vq(ctx->fh.m2m_ctx, f->type); ++ if (vb2_is_busy(vq)) ++ return -EBUSY; ++ ++ ctx->src_fmt.pix = f->fmt.pix; ++ ctx->src_fmt.hw_fmt = iep_fmt_find(&f->fmt.pix); ++ ctx->src_fmt.y_stride = IEP_Y_STRIDE(f->fmt.pix.width, f->fmt.pix.height); ++ ctx->src_fmt.uv_stride = IEP_UV_STRIDE(f->fmt.pix.width, f->fmt.pix.height, ++ ctx->src_fmt.hw_fmt->uv_factor); ++ ++ /* Propagate colorspace information to capture. */ ++ ctx->dst_fmt.pix.colorspace = f->fmt.pix.colorspace; ++ ctx->dst_fmt.pix.xfer_func = f->fmt.pix.xfer_func; ++ ctx->dst_fmt.pix.ycbcr_enc = f->fmt.pix.ycbcr_enc; ++ ctx->dst_fmt.pix.quantization = f->fmt.pix.quantization; ++ ++ /* scaling is not supported */ ++ ctx->dst_fmt.pix.width = f->fmt.pix.width; ++ ctx->dst_fmt.pix.height = f->fmt.pix.height; ++ ctx->dst_fmt.y_stride = IEP_Y_STRIDE(f->fmt.pix.width, f->fmt.pix.height); ++ ctx->dst_fmt.uv_stride = IEP_UV_STRIDE(f->fmt.pix.width, f->fmt.pix.height, ++ ctx->dst_fmt.hw_fmt->uv_factor); ++ ++ ctx->fmt_changed = true; ++ ++ return 0; ++} ++ ++static int iep_s_fmt_vid_cap(struct file *file, void *priv, ++ struct v4l2_format *f) ++{ ++ struct iep_ctx *ctx = iep_file2ctx(file); ++ struct vb2_queue *vq; ++ int ret; ++ ++ ret = iep_try_fmt_vid_cap(file, priv, f); ++ if (ret) ++ return ret; ++ ++ vq = v4l2_m2m_get_vq(ctx->fh.m2m_ctx, f->type); ++ if (vb2_is_busy(vq)) ++ return -EBUSY; ++ ++ /* scaling is not supported */ ++ f->fmt.pix.width = ctx->src_fmt.pix.width; ++ f->fmt.pix.height = ctx->src_fmt.pix.height; ++ ++ ctx->dst_fmt.pix = f->fmt.pix; ++ ctx->dst_fmt.hw_fmt = iep_fmt_find(&f->fmt.pix); ++ ++ ctx->dst_fmt.y_stride = IEP_Y_STRIDE(f->fmt.pix.width, f->fmt.pix.height); ++ ctx->dst_fmt.uv_stride = IEP_UV_STRIDE(f->fmt.pix.width, f->fmt.pix.height, ++ ctx->dst_fmt.hw_fmt->uv_factor); ++ ++ ctx->fmt_changed = true; ++ ++ return 0; ++} ++ ++static const struct v4l2_ioctl_ops iep_ioctl_ops = { ++ .vidioc_querycap = iep_querycap, ++ ++ .vidioc_enum_framesizes = iep_enum_framesizes, ++ ++ .vidioc_enum_fmt_vid_cap = iep_enum_fmt, ++ .vidioc_g_fmt_vid_cap = iep_g_fmt_vid_cap, ++ .vidioc_try_fmt_vid_cap = iep_try_fmt_vid_cap, ++ .vidioc_s_fmt_vid_cap = iep_s_fmt_vid_cap, ++ ++ .vidioc_enum_fmt_vid_out = iep_enum_fmt, ++ .vidioc_g_fmt_vid_out = iep_g_fmt_vid_out, ++ .vidioc_try_fmt_vid_out = iep_try_fmt_vid_out, ++ .vidioc_s_fmt_vid_out = iep_s_fmt_vid_out, ++ ++ .vidioc_reqbufs = v4l2_m2m_ioctl_reqbufs, ++ .vidioc_querybuf = v4l2_m2m_ioctl_querybuf, ++ .vidioc_qbuf = v4l2_m2m_ioctl_qbuf, ++ .vidioc_dqbuf = v4l2_m2m_ioctl_dqbuf, ++ .vidioc_prepare_buf = v4l2_m2m_ioctl_prepare_buf, ++ .vidioc_create_bufs = v4l2_m2m_ioctl_create_bufs, ++ .vidioc_expbuf = v4l2_m2m_ioctl_expbuf, ++ ++ .vidioc_streamon = v4l2_m2m_ioctl_streamon, ++ .vidioc_streamoff = v4l2_m2m_ioctl_streamoff, ++}; ++ ++static const struct video_device iep_video_device = { ++ .name = IEP_NAME, ++ .vfl_dir = VFL_DIR_M2M, ++ .fops = &iep_fops, ++ .ioctl_ops = &iep_ioctl_ops, ++ .minor = -1, ++ .release = video_device_release_empty, ++ .device_caps = V4L2_CAP_VIDEO_M2M | V4L2_CAP_STREAMING, ++}; ++ ++static int iep_parse_dt(struct rockchip_iep *iep) ++{ ++ int ret = 0; ++ ++ iep->axi_clk = devm_clk_get(iep->dev, "axi"); ++ if (IS_ERR(iep->axi_clk)) { ++ dev_err(iep->dev, "failed to get aclk clock\n"); ++ return PTR_ERR(iep->axi_clk); ++ } ++ ++ iep->ahb_clk = devm_clk_get(iep->dev, "ahb"); ++ if (IS_ERR(iep->ahb_clk)) { ++ dev_err(iep->dev, "failed to get hclk clock\n"); ++ return PTR_ERR(iep->ahb_clk); ++ } ++ ++ ret = clk_set_rate(iep->axi_clk, 300000000); ++ ++ if (ret) ++ dev_err(iep->dev, "failed to set axi clock rate to 300 MHz\n"); ++ ++ return ret; ++} ++ ++static irqreturn_t iep_isr(int irq, void *prv) ++{ ++ struct rockchip_iep *iep = prv; ++ struct iep_ctx *ctx; ++ u32 val; ++ enum vb2_buffer_state state = VB2_BUF_STATE_DONE; ++ ++ ctx = v4l2_m2m_get_curr_priv(iep->m2m_dev); ++ if (!ctx) { ++ v4l2_err(&iep->v4l2_dev, ++ "Instance released before the end of transaction\n"); ++ return IRQ_NONE; ++ } ++ ++ /* ++ * The irq is shared with the iommu. If the runtime-pm state of the ++ * iep-device is disabled or the interrupt status doesn't match the ++ * expeceted mask the irq has been targeted to the iommu. ++ */ ++ ++ if (!pm_runtime_active(iep->dev) || ++ !(iep_read(iep, IEP_INT) & IEP_INT_MASK)) ++ return IRQ_NONE; ++ ++ /* disable interrupt - will be re-enabled at next iep_device_run */ ++ iep_mod(ctx->iep, IEP_INT, ++ IEP_INT_FRAME_DONE_EN, 0); ++ ++ iep_mod(iep, IEP_INT, IEP_INT_FRAME_DONE_CLR, ++ IEP_INT_FRAME_DONE_CLR); ++ ++ /* wait for all status regs to show "idle" */ ++ val = readl_poll_timeout(iep->regs + IEP_STATUS, val, ++ (val == 0), 100, IEP_TIMEOUT); ++ ++ if (val) { ++ dev_err(iep->dev, ++ "Failed to wait for job to finish: status: %u\n", val); ++ state = VB2_BUF_STATE_ERROR; ++ ctx->job_abort = true; ++ } ++ ++ iep_m2m_dst_bufs_done(ctx, state); ++ ++ ctx->field_bff = (ctx->dst_buffs_done % 2 == 0) ++ ? ctx->field_order_bff : !ctx->field_order_bff; ++ ++ if (ctx->dst_buffs_done == 2 || ctx->job_abort) { ++ if (ctx->prev_src_buf) ++ v4l2_m2m_buf_done(ctx->prev_src_buf, state); ++ ++ /* current src buff will be next prev */ ++ ctx->prev_src_buf = v4l2_m2m_src_buf_remove(ctx->fh.m2m_ctx); ++ ++ v4l2_m2m_job_finish(ctx->iep->m2m_dev, ctx->fh.m2m_ctx); ++ ctx->dst_buffs_done = 0; ++ ++ } else { ++ iep_device_run(ctx); ++ } ++ ++ return IRQ_HANDLED; ++} ++ ++static int iep_probe(struct platform_device *pdev) ++{ ++ struct rockchip_iep *iep; ++ struct video_device *vfd; ++ struct resource *res; ++ int ret = 0; ++ int irq; ++ ++ if (!pdev->dev.of_node) ++ return -ENODEV; ++ ++ iep = devm_kzalloc(&pdev->dev, sizeof(*iep), GFP_KERNEL); ++ if (!iep) ++ return -ENOMEM; ++ ++ platform_set_drvdata(pdev, iep); ++ iep->dev = &pdev->dev; ++ iep->vfd = iep_video_device; ++ ++ ret = iep_parse_dt(iep); ++ if (ret) ++ dev_err(&pdev->dev, "Unable to parse OF data\n"); ++ ++ res = platform_get_resource(pdev, IORESOURCE_MEM, 0); ++ ++ iep->regs = devm_ioremap_resource(iep->dev, res); ++ if (IS_ERR(iep->regs)) { ++ ret = PTR_ERR(iep->regs); ++ goto err_put_clk; ++ } ++ ++ ret = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32)); ++ if (ret) { ++ dev_err(&pdev->dev, "Could not set DMA coherent mask.\n"); ++ goto err_put_clk; ++ } ++ ++ vb2_dma_contig_set_max_seg_size(&pdev->dev, DMA_BIT_MASK(32)); ++ ++ irq = platform_get_irq(pdev, 0); ++ if (irq < 0) { ++ ret = irq; ++ goto err_put_clk; ++ } ++ ++ /* IRQ is shared with IOMMU */ ++ ret = devm_request_irq(iep->dev, irq, iep_isr, IRQF_SHARED, ++ dev_name(iep->dev), iep); ++ if (ret < 0) { ++ dev_err(iep->dev, "failed to request irq\n"); ++ goto err_put_clk; ++ } ++ ++ mutex_init(&iep->mutex); ++ ++ ret = v4l2_device_register(&pdev->dev, &iep->v4l2_dev); ++ if (ret) { ++ dev_err(iep->dev, "Failed to register V4L2 device\n"); ++ ++ return ret; ++ } ++ ++ vfd = &iep->vfd; ++ vfd->lock = &iep->mutex; ++ vfd->v4l2_dev = &iep->v4l2_dev; ++ ++ snprintf(vfd->name, sizeof(vfd->name), "%s", ++ iep_video_device.name); ++ ++ video_set_drvdata(vfd, iep); ++ ++ ret = video_register_device(vfd, VFL_TYPE_VIDEO, 0); ++ if (ret) { ++ v4l2_err(&iep->v4l2_dev, "Failed to register video device\n"); ++ ++ goto err_v4l2; ++ } ++ ++ v4l2_info(&iep->v4l2_dev, ++ "Device %s registered as /dev/video%d\n", vfd->name, vfd->num); ++ ++ iep->m2m_dev = v4l2_m2m_init(&iep_m2m_ops); ++ if (IS_ERR(iep->m2m_dev)) { ++ v4l2_err(&iep->v4l2_dev, ++ "Failed to initialize V4L2 M2M device\n"); ++ ret = PTR_ERR(iep->m2m_dev); ++ ++ goto err_video; ++ } ++ ++ pm_runtime_set_autosuspend_delay(iep->dev, 100); ++ pm_runtime_use_autosuspend(iep->dev); ++ pm_runtime_enable(iep->dev); ++ ++ return ret; ++ ++err_video: ++ video_unregister_device(&iep->vfd); ++err_v4l2: ++ v4l2_device_unregister(&iep->v4l2_dev); ++err_put_clk: ++ pm_runtime_dont_use_autosuspend(iep->dev); ++ pm_runtime_disable(iep->dev); ++ ++return ret; ++} ++ ++static void iep_remove(struct platform_device *pdev) ++{ ++ struct rockchip_iep *iep = platform_get_drvdata(pdev); ++ ++ pm_runtime_dont_use_autosuspend(iep->dev); ++ pm_runtime_disable(iep->dev); ++ ++ v4l2_m2m_release(iep->m2m_dev); ++ video_unregister_device(&iep->vfd); ++ v4l2_device_unregister(&iep->v4l2_dev); ++} ++ ++static int __maybe_unused iep_runtime_suspend(struct device *dev) ++{ ++ struct rockchip_iep *iep = dev_get_drvdata(dev); ++ ++ clk_disable_unprepare(iep->ahb_clk); ++ clk_disable_unprepare(iep->axi_clk); ++ ++ return 0; ++} ++ ++static int __maybe_unused iep_runtime_resume(struct device *dev) ++{ ++ struct rockchip_iep *iep; ++ int ret = 0; ++ ++ iep = dev_get_drvdata(dev); ++ ++ ret = clk_prepare_enable(iep->axi_clk); ++ if (ret) { ++ dev_err(iep->dev, "Cannot enable axi clock: %d\n", ret); ++ return ret; ++ } ++ ++ ret = clk_prepare_enable(iep->ahb_clk); ++ if (ret) { ++ dev_err(iep->dev, "Cannot enable ahb clock: %d\n", ret); ++ goto err_disable_axi_clk; ++ } ++ ++ return ret; ++ ++err_disable_axi_clk: ++ clk_disable_unprepare(iep->axi_clk); ++ return ret; ++} ++ ++static const struct dev_pm_ops iep_pm_ops = { ++ SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, ++ pm_runtime_force_resume) ++ SET_RUNTIME_PM_OPS(iep_runtime_suspend, ++ iep_runtime_resume, NULL) ++}; ++ ++static const struct of_device_id rockchip_iep_match[] = { ++ { ++ .compatible = "rockchip,rk3228-iep", ++ }, ++ {}, ++}; ++ ++MODULE_DEVICE_TABLE(of, rockchip_iep_match); ++ ++static struct platform_driver iep_pdrv = { ++ .probe = iep_probe, ++ .remove = iep_remove, ++ .driver = { ++ .name = IEP_NAME, ++ .pm = &iep_pm_ops, ++ .of_match_table = rockchip_iep_match, ++ }, ++}; ++ ++module_platform_driver(iep_pdrv); ++ ++MODULE_AUTHOR("Alex Bee "); ++MODULE_DESCRIPTION("Rockchip Image Enhancement Processor"); ++MODULE_LICENSE("GPL v2"); +diff --git a/drivers/media/platform/rockchip/iep/iep.h b/drivers/media/platform/rockchip/iep/iep.h +new file mode 100644 +index 000000000000..7d9fc61624b6 +--- /dev/null ++++ b/drivers/media/platform/rockchip/iep/iep.h +@@ -0,0 +1,112 @@ ++/* SPDX-License-Identifier: GPL-2.0-only */ ++/* ++ * Rockchip Image Enhancement Processor (IEP) driver ++ * ++ * Copyright (C) 2020 Alex Bee ++ * ++ */ ++#ifndef __IEP_H__ ++#define __IEP_H__ ++ ++#include ++#include ++#include ++#include ++ ++#define IEP_NAME "rockchip-iep" ++ ++/* Hardware limits */ ++#define IEP_MIN_WIDTH 320U ++#define IEP_MAX_WIDTH 1920U ++ ++#define IEP_MIN_HEIGHT 240U ++#define IEP_MAX_HEIGHT 1088U ++ ++/* Hardware defaults */ ++#define IEP_DEFAULT_WIDTH 320U ++#define IEP_DEFAULT_HEIGHT 240U ++ ++//ns ++#define IEP_TIMEOUT 250000 ++ ++struct iep_fmt { ++ u32 fourcc; ++ u8 depth; ++ u8 uv_factor; ++ u8 color_swap; ++ u8 hw_format; ++}; ++ ++struct iep_frm_fmt { ++ struct iep_fmt *hw_fmt; ++ struct v4l2_pix_format pix; ++ ++ unsigned int y_stride; ++ unsigned int uv_stride; ++}; ++ ++struct iep_ctx { ++ struct v4l2_fh fh; ++ struct rockchip_iep *iep; ++ ++ struct iep_frm_fmt src_fmt; ++ struct iep_frm_fmt dst_fmt; ++ ++ struct vb2_v4l2_buffer *prev_src_buf; ++ struct vb2_v4l2_buffer *dst0_buf; ++ struct vb2_v4l2_buffer *dst1_buf; ++ ++ u32 dst_sequence; ++ u32 src_sequence; ++ ++ /* bff = bottom field first */ ++ bool field_order_bff; ++ bool field_bff; ++ ++ unsigned int dst_buffs_done; ++ ++ bool fmt_changed; ++ bool job_abort; ++}; ++ ++struct rockchip_iep { ++ struct v4l2_device v4l2_dev; ++ struct v4l2_m2m_dev *m2m_dev; ++ struct video_device vfd; ++ ++ struct device *dev; ++ ++ void __iomem *regs; ++ ++ struct clk *axi_clk; ++ struct clk *ahb_clk; ++ ++ /* vfd lock */ ++ struct mutex mutex; ++}; ++ ++static inline void iep_write(struct rockchip_iep *iep, u32 reg, u32 value) ++{ ++ writel(value, iep->regs + reg); ++}; ++ ++static inline u32 iep_read(struct rockchip_iep *iep, u32 reg) ++{ ++ return readl(iep->regs + reg); ++}; ++ ++static inline void iep_shadow_mod(struct rockchip_iep *iep, u32 reg, ++ u32 shadow_reg, u32 mask, u32 val) ++{ ++ u32 temp = iep_read(iep, shadow_reg) & ~(mask); ++ ++ temp |= val & mask; ++ iep_write(iep, reg, temp); ++}; ++ ++static inline void iep_mod(struct rockchip_iep *iep, u32 reg, u32 mask, u32 val) ++{ ++ iep_shadow_mod(iep, reg, reg, mask, val); ++}; ++ ++#endif + +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Alex Bee +Date: Wed, 14 Oct 2020 20:22:38 +0200 +Subject: [PATCH] ARM64: dts: rockchip: Add IEP node for RK3328 + +while at that also add the mmu required + +Signed-off-by: Alex Bee +--- + arch/arm64/boot/dts/rockchip/rk3328.dtsi | 22 ++++++++++++++++++++++ + 1 file changed, 22 insertions(+) + +diff --git a/arch/arm64/boot/dts/rockchip/rk3328.dtsi b/arch/arm64/boot/dts/rockchip/rk3328.dtsi +index eec03adf0902..5455a46c9a6b 100644 +--- a/arch/arm64/boot/dts/rockchip/rk3328.dtsi ++++ b/arch/arm64/boot/dts/rockchip/rk3328.dtsi +@@ -760,6 +760,28 @@ vop_mmu: iommu@ff373f00 { + status = "disabled"; + }; + ++ iep: iep@ff3a0000 { ++ compatible = "rockchip,rk3328-iep", "rockchip,rk3228-iep"; ++ reg = <0x0 0xff3a0000 0x0 0x800>; ++ interrupts = ; ++ interrupt-names = "iep"; ++ clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>; ++ clock-names = "axi", "ahb"; ++ power-domains = <&power RK3328_PD_VIDEO>; ++ iommus = <&iep_mmu>; ++ }; ++ ++ iep_mmu: iommu@ff3a0800 { ++ compatible = "rockchip,iommu"; ++ reg = <0x0 0xff3a0800 0x0 0x40>; ++ interrupts = ; ++ interrupt-names = "iep_mmu"; ++ clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>; ++ clock-names = "aclk", "iface"; ++ power-domains = <&power RK3328_PD_VIDEO>; ++ #iommu-cells = <0>; ++ }; ++ + hdmi: hdmi@ff3c0000 { + compatible = "rockchip,rk3328-dw-hdmi"; + reg = <0x0 0xff3c0000 0x0 0x20000>; + +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Alex Bee +Date: Wed, 14 Oct 2020 20:43:12 +0200 +Subject: [PATCH] ARM64: dts: rockchip: Add IEP node for RK3399 + +Signed-off-by: Alex Bee +--- + arch/arm64/boot/dts/rockchip/rk3399-base.dtsi | 13 ++++++++++++- + 1 file changed, 12 insertions(+), 1 deletion(-) + +diff --git a/arch/arm64/boot/dts/rockchip/rk3399-base.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-base.dtsi +index dbe6a9cb98a5..f0629b7a81c6 100644 +--- a/arch/arm64/boot/dts/rockchip/rk3399-base.dtsi ++++ b/arch/arm64/boot/dts/rockchip/rk3399-base.dtsi +@@ -1365,14 +1365,25 @@ vdec_mmu: iommu@ff660480 { + #iommu-cells = <0>; + }; + ++ iep: iep@ff670000 { ++ compatible = "rockchip,rk3399-iep", "rockchip,rk3228-iep"; ++ reg = <0x0 0xff670000 0x0 0x800>; ++ interrupts = ; ++ interrupt-names = "iep"; ++ clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>; ++ clock-names = "axi", "ahb"; ++ power-domains = <&power RK3399_PD_IEP>; ++ iommus = <&iep_mmu>; ++ }; ++ + iep_mmu: iommu@ff670800 { + compatible = "rockchip,iommu"; + reg = <0x0 0xff670800 0x0 0x40>; + interrupts = ; + clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>; + clock-names = "aclk", "iface"; ++ power-domains = <&power RK3399_PD_IEP>; + #iommu-cells = <0>; +- status = "disabled"; + }; + + rga: rga@ff680000 { + +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Alex Bee +Date: Wed, 14 Oct 2020 20:53:56 +0200 +Subject: [PATCH] ARM: dts: rockchip: Add IEP node for RK3288 + +Signed-off-by: Alex Bee +--- + arch/arm/boot/dts/rockchip/rk3288.dtsi | 13 ++++++++++++- + 1 file changed, 12 insertions(+), 1 deletion(-) + +diff --git a/arch/arm/boot/dts/rockchip/rk3288.dtsi b/arch/arm/boot/dts/rockchip/rk3288.dtsi +index 59fba3ac6aae..06545f423de2 100644 +--- a/arch/arm/boot/dts/rockchip/rk3288.dtsi ++++ b/arch/arm/boot/dts/rockchip/rk3288.dtsi +@@ -984,14 +984,25 @@ crypto: crypto@ff8a0000 { + reset-names = "crypto-rst"; + }; + ++ iep: iep@ff90000 { ++ compatible = "rockchip,rk3288-iep", "rockchip,rk3228-iep"; ++ reg = <0x0 0xff900000 0x0 0x800>; ++ interrupts = ; ++ interrupt-names = "iep"; ++ clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>; ++ clock-names = "axi", "ahb"; ++ power-domains = <&power RK3288_PD_VIO>; ++ iommus = <&iep_mmu>; ++ }; ++ + iep_mmu: iommu@ff900800 { + compatible = "rockchip,iommu"; + reg = <0x0 0xff900800 0x0 0x40>; + interrupts = ; + clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>; + clock-names = "aclk", "iface"; ++ power-domains = <&power RK3288_PD_VIO>; + #iommu-cells = <0>; +- status = "disabled"; + }; + + isp_mmu: iommu@ff914000 { diff --git a/patch/kernel/archive/rockchip-6.11/series.conf b/patch/kernel/archive/rockchip-6.12/series.conf similarity index 98% rename from patch/kernel/archive/rockchip-6.11/series.conf rename to patch/kernel/archive/rockchip-6.12/series.conf index f75d733bbebe..43cf51f05019 100644 --- a/patch/kernel/archive/rockchip-6.11/series.conf +++ b/patch/kernel/archive/rockchip-6.12/series.conf @@ -4,7 +4,6 @@ patches.libreelec/linux-1000-drm-rockchip.patch patches.libreelec/linux-1001-v4l2-rockchip.patch patches.libreelec/linux-1002-for-libreelec.patch - patches.libreelec/linux-1003-temp-dw_hdmi-rockchip.patch patches.libreelec/linux-2000-v4l2-wip-rkvdec-hevc.patch patches.libreelec/linux-2001-v4l2-wip-iep-driver.patch # Series from patches.armbian/ From 0449f6dd92807c72ea35db9274a18ac5027399b8 Mon Sep 17 00:00:00 2001 From: Werner Date: Sun, 1 Dec 2024 10:04:22 +0100 Subject: [PATCH 003/120] `WIREGUARD` is deprecated (#7520) --- config/boards/radxa-e20c.csc | 1 - 1 file changed, 1 deletion(-) diff --git a/config/boards/radxa-e20c.csc b/config/boards/radxa-e20c.csc index fd9a7c650631..6f6dd5740a20 100644 --- a/config/boards/radxa-e20c.csc +++ b/config/boards/radxa-e20c.csc @@ -8,5 +8,4 @@ FULL_DESKTOP="no" BOOT_LOGO="desktop" BOOT_FDT_FILE="rockchip/rk3528-radxa-e20c.dtb" BOOT_SCENARIO="spl-blobs" -WIREGUARD="no" IMAGE_PARTITION_TABLE="gpt" From 35352fa288cedcee806caa83bb5de6c9162758b7 Mon Sep 17 00:00:00 2001 From: Jianfeng Liu Date: Sat, 30 Nov 2024 23:41:22 +0800 Subject: [PATCH 004/120] rk35xx-vendor: bump to 6.1 rkr4.1 sdk kernel --- config/sources/families/rk35xx.conf | 2 +- config/sources/families/rockchip-rk3588.conf | 2 +- patch/kernel/rk35xx-vendor-6.1/0000.patching_config.yaml | 4 ++-- 3 files changed, 4 insertions(+), 4 deletions(-) diff --git a/config/sources/families/rk35xx.conf b/config/sources/families/rk35xx.conf index c252a5cd6c59..50e83ad213e0 100644 --- a/config/sources/families/rk35xx.conf +++ b/config/sources/families/rk35xx.conf @@ -37,7 +37,7 @@ case $BRANCH in declare -g KERNEL_MAJOR_MINOR="6.1" # Major and minor versions of this kernel. declare -g -i KERNEL_GIT_CACHE_TTL=120 # 2 minutes; this is a high-traffic repo KERNELSOURCE='https://github.com/armbian/linux-rockchip.git' - KERNELBRANCH='branch:rk-6.1-rkr3' + KERNELBRANCH='branch:rk-6.1-rkr4.1' KERNELPATCHDIR='rk35xx-vendor-6.1' ;; esac diff --git a/config/sources/families/rockchip-rk3588.conf b/config/sources/families/rockchip-rk3588.conf index 626035b70cc4..2b589ab0c718 100644 --- a/config/sources/families/rockchip-rk3588.conf +++ b/config/sources/families/rockchip-rk3588.conf @@ -34,7 +34,7 @@ case $BRANCH in declare -g KERNEL_MAJOR_MINOR="6.1" # Major and minor versions of this kernel. declare -g -i KERNEL_GIT_CACHE_TTL=120 # 2 minutes; this is a high-traffic repo KERNELSOURCE='https://github.com/armbian/linux-rockchip.git' - KERNELBRANCH='branch:rk-6.1-rkr3' + KERNELBRANCH='branch:rk-6.1-rkr4.1' KERNELPATCHDIR='rk35xx-vendor-6.1' LINUXFAMILY=rk35xx ;; diff --git a/patch/kernel/rk35xx-vendor-6.1/0000.patching_config.yaml b/patch/kernel/rk35xx-vendor-6.1/0000.patching_config.yaml index c77f324d61de..e2e43b1ec21f 100644 --- a/patch/kernel/rk35xx-vendor-6.1/0000.patching_config.yaml +++ b/patch/kernel/rk35xx-vendor-6.1/0000.patching_config.yaml @@ -4,8 +4,8 @@ config: name: rk35xx-6.1 kind: kernel type: vendor # or: vendor - branch: rk-6.1-rkr3 - last-known-good-tag: v6.1.75 + branch: rk-6.1-rkr4.1 + last-known-good-tag: v6.1.84 # .dts files in these directories will be copied as-is to the build tree; later ones overwrite earlier ones. # This is meant to provide a way to "add a board DTS" without having to null-patch them in. From 384045a7361fb4439a2a7ef0d3c96b12025bcba1 Mon Sep 17 00:00:00 2001 From: amazingfate Date: Mon, 25 Nov 2024 01:53:51 +0800 Subject: [PATCH 005/120] extension: mesa-vpu: remove adding chromium ppa We already have imported chromium debs from ppa to armbian's repo --- extensions/mesa-vpu.sh | 28 ---------------------------- 1 file changed, 28 deletions(-) diff --git a/extensions/mesa-vpu.sh b/extensions/mesa-vpu.sh index aaba956d7ec1..3bc89d0cfa0b 100644 --- a/extensions/mesa-vpu.sh +++ b/extensions/mesa-vpu.sh @@ -90,34 +90,6 @@ function post_install_kernel_debs__3d() { # Add chromium if building a desktop if [[ "${BUILD_DESKTOP}" == "yes" ]]; then - if [[ "${ARCH}" == "arm64" ]]; then - - display_alert "Adding Amazingfate Chromium PPAs" "${EXTENSION}" "info" - do_with_retries 3 chroot_sdcard add-apt-repository ppa:liujianfeng1994/chromium --yes --no-update - sed -i "s/oracular/noble/g" "${SDCARD}"/etc/apt/sources.list.d/liujianfeng1994-ubuntu-chromium-"${RELEASE}".* - - display_alert "Pinning amazingfated's Chromium PPAs" "${EXTENSION}" "info" - cat <<- EOF > "${SDCARD}"/etc/apt/preferences.d/liujianfeng1994-chromium-pin - Package: chromium - Pin: release o=LP-PPA-liujianfeng1994-chromium - Pin-Priority: 1001 - EOF - - else - - display_alert "Adding Xtradebs Apps PPAs" "${EXTENSION}" "info" - do_with_retries 3 chroot_sdcard add-apt-repository ppa:xtradeb/apps --yes --no-update - sed -i "s/oracular/noble/g" "${SDCARD}"/etc/apt/sources.list.d/xtradeb-ubuntu-apps-"${RELEASE}".* - - display_alert "Pinning Xtradebs PPAs" "${EXTENSION}" "info" - cat <<- EOF > "${SDCARD}"/etc/apt/preferences.d/xtradebs-apps-pin - Package: chromium - Pin: release o=LP-PPA-xtradebs-apps - Pin-Priority: 1001 - EOF - - fi - pkgs+=("chromium") fi fi From ccc887a36c96dd5088c008547ee00ac65135b8bf Mon Sep 17 00:00:00 2001 From: amazingfate Date: Mon, 25 Nov 2024 02:06:36 +0800 Subject: [PATCH 006/120] hinlink-h88k: edge: add rfkill nodes to devicetree for m.2 wifi and bluetooth --- .../dt/rk3588-hinlink-h88k.dts | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/patch/kernel/archive/rockchip-rk3588-6.12/dt/rk3588-hinlink-h88k.dts b/patch/kernel/archive/rockchip-rk3588-6.12/dt/rk3588-hinlink-h88k.dts index ed962d5a9ee1..9363eef2d592 100644 --- a/patch/kernel/archive/rockchip-rk3588-6.12/dt/rk3588-hinlink-h88k.dts +++ b/patch/kernel/archive/rockchip-rk3588-6.12/dt/rk3588-hinlink-h88k.dts @@ -92,6 +92,20 @@ }; }; + rfkilli-wifi { + compatible = "rfkill-gpio"; + label = "rfkill-pcie-wlan"; + radio-type = "wlan"; + shutdown-gpios = <&gpio3 RK_PB1 GPIO_ACTIVE_HIGH>; + }; + + rfkill-bt { + compatible = "rfkill-gpio"; + label = "rfkill-m2-bt"; + radio-type = "bluetooth"; + shutdown-gpios = <&gpio3 RK_PA6 GPIO_ACTIVE_HIGH>; + }; + vcc12v_dcin: vcc12v-dcin { compatible = "regulator-fixed"; regulator-always-on; From f41cd5ca51a111ea9f2e59ba8cf3f1cf24a4796e Mon Sep 17 00:00:00 2001 From: Andy Yan Date: Sun, 14 Jul 2024 15:06:17 +0800 Subject: [PATCH 007/120] Add support for rk3588 based GenBook GenBook is a rk3588 based laptop from coolpi. The armbian can boot from a usb disk, with pre installed mainline u-boot on SPI Nor flash. Signed-off-by: Andy Yan --- config/boards/coolpi-genbook.csc | 36 ++++++++++++++++++++++++++++++++ 1 file changed, 36 insertions(+) create mode 100644 config/boards/coolpi-genbook.csc diff --git a/config/boards/coolpi-genbook.csc b/config/boards/coolpi-genbook.csc new file mode 100644 index 000000000000..a274fe512b7e --- /dev/null +++ b/config/boards/coolpi-genbook.csc @@ -0,0 +1,36 @@ +# Rockchip RK3588 SoC octa core 4-16GB SoC eMMC USB3 NVME +BOARD_NAME="CoolPi GenBook" +BOARDFAMILY="rockchip-rk3588" +BOARD_MAINTAINER="Andyshrk" +BOARD_FIRMWARE_INSTALL="-full" +BOOT_SOC="rk3588" +BOOTCONFIG="coolpi-cm5-genbook-rk3588_defconfig" +KERNEL_TARGET="edge" +FULL_DESKTOP="yes" +BOOT_LOGO="desktop" +BOOT_FDT_FILE="rockchip/rk3588-coolpi-cm5-genbook.dtb" +BOOT_SCENARIO="spl-blobs" +BOOT_SUPPORT_SPI="yes" +BOOT_SPI_RKSPI_LOADER="yes" +IMAGE_PARTITION_TABLE="gpt" + +# Mainline U-Boot +function post_family_config_branch_edge__coolpi-genbook_use_mainline_uboot() { + display_alert "$BOARD" "mainline (next branch) u-boot overrides for $BOARD / $BRANCH" "info" + + declare -g BOOTSOURCE="https://github.com/u-boot/u-boot.git" # Mainline U-Boot + unset BOOTBRANCH + unset BOOTPATCHDIR + declare -g BOOTBRANCH_BOARD="tag:v2025.01-rc3" + declare -g UBOOT_TARGET_MAP="BL31=${RKBIN_DIR}/${BL31_BLOB} ROCKCHIP_TPL=${RKBIN_DIR}/${DDR_BLOB};;u-boot-rockchip.bin u-boot-rockchip-spi.bin" + unset uboot_custom_postprocess write_uboot_platform write_uboot_platform_mtd # disable stuff from rockchip64_common; we're using binman here which does all the work already + + # Just use the binman-provided u-boot-rockchip.bin, which is ready-to-go + function write_uboot_platform() { + dd "if=$1/u-boot-rockchip.bin" "of=$2" bs=32k seek=1 conv=notrunc status=none + } + + function write_uboot_platform_mtd() { + flashcp -v -p "$1/u-boot-rockchip-spi.bin" /dev/mtd0 + } +} From 447c2a4207946c05403996305a314a735cd6ac72 Mon Sep 17 00:00:00 2001 From: "dependabot[bot]" <49699333+dependabot[bot]@users.noreply.github.com> Date: Mon, 25 Nov 2024 19:11:34 +0000 Subject: [PATCH 008/120] build(deps): bump setuptools from 75.3.0 to 75.6.0 Bumps [setuptools](https://github.com/pypa/setuptools) from 75.3.0 to 75.6.0. - [Release notes](https://github.com/pypa/setuptools/releases) - [Changelog](https://github.com/pypa/setuptools/blob/main/NEWS.rst) - [Commits](https://github.com/pypa/setuptools/compare/v75.3.0...v75.6.0) --- updated-dependencies: - dependency-name: setuptools dependency-type: direct:production update-type: version-update:semver-minor ... Signed-off-by: dependabot[bot] --- requirements.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/requirements.txt b/requirements.txt index 4a7b233e0613..21e57d719693 100644 --- a/requirements.txt +++ b/requirements.txt @@ -5,7 +5,7 @@ # Always use a fixed version, this is important for correct hashing. # Dependabot will keep these versions up to date. -setuptools == 75.3.0 # for building Python packages +setuptools == 75.6.0 # for building Python packages pyelftools == 0.31 # for building U-Boot unidiff == 0.7.5 # for parsing unified diff GitPython == 3.1.43 # for manipulating git repos From 1285de6bd81e0a3bcfaf00a32f3ac44e6a163ec6 Mon Sep 17 00:00:00 2001 From: igorpecovnik <6281704+igorpecovnik@users.noreply.github.com> Date: Mon, 2 Dec 2024 08:10:13 +0000 Subject: [PATCH 009/120] `Automatic` board configs status synchronise --- .github/CODEOWNERS | 18 +++++++++--------- config/boards/bananapim5.conf | 2 +- config/boards/retroidpocket-rp5.csc | 2 +- config/boards/retroidpocket-rpmini.csc | 2 +- config/boards/rock-s0.conf | 2 +- config/boards/rockpi-s.conf | 2 +- 6 files changed, 14 insertions(+), 14 deletions(-) diff --git a/.github/CODEOWNERS b/.github/CODEOWNERS index ea8763b58652..57d0667cc5b2 100644 --- a/.github/CODEOWNERS +++ b/.github/CODEOWNERS @@ -30,7 +30,7 @@ config/boards/bananapim2s.conf @jeanrhum @pyavitz config/boards/bananapim2zero.csc @mhawkins-consultant config/boards/bananapim3.csc @AaronNGray config/boards/bananapim4zero.conf @pyavitz -config/boards/bananapim5.conf @bretmlw +config/boards/bananapim5.conf @igorpecovnik config/boards/bananapim64.csc @devdotnetorg config/boards/bananapim7.conf @amazingfate config/boards/bigtreetech-cb1.conf @JohnTheCoolingFan @@ -90,7 +90,7 @@ config/boards/odroidhc4.conf @igorpecovnik config/boards/odroidm1.conf @rpardini config/boards/odroidn2.conf @NicoD-SBC config/boards/odroidxu4.conf @joekhoobyar -config/boards/olimex-teres-a64.conf @Kreyren +config/boards/olimex-teres-a64.csc @Kreyren config/boards/onecloud.conf @hzyitc config/boards/oneplus-kebab.conf @amazingfate config/boards/orangepi4-lts.conf @paolosabatino @@ -100,10 +100,10 @@ config/boards/orangepi5.conf @efectn config/boards/orangepione.conf @StephenGraf config/boards/orangepipc.csc @lbmendes config/boards/orangepipcplus.csc @Janmcha -config/boards/orangepizero2.wip @AGM1968 @krachlatte +config/boards/orangepizero2.csc @AGM1968 @krachlatte config/boards/orangepizero2w.csc @chraac config/boards/orangepizero3.csc @alexl83 @chraac -config/boards/orangepizeroplus.conf @schwar3kat +config/boards/orangepizeroplus.csc @schwar3kat config/boards/phytiumpi.conf @chainsx config/boards/pine64.conf @PanderMusubi config/boards/pinebook-pro.csc @TRSx80 @ahoneybun @@ -141,7 +141,7 @@ config/boards/sk-tda4vm.conf @glneo config/boards/station-m1.csc @150balbes config/boards/station-m3.csc @chainsx config/boards/sweet-potato.conf @Tonymac32 -config/boards/thinkpad-x13s.wip @PeterChrz @rpardini +config/boards/thinkpad-x13s.conf @PeterChrz @rpardini config/boards/tinkerboard.conf @paolosabatino config/boards/tritium-h3.conf @Tonymac32 config/boards/tritium-h5.conf @Tonymac32 @@ -152,7 +152,7 @@ config/boards/wsl2-x86.csc @rpardini config/boards/x96-mate.tvb @Ressetkk config/boards/x96q.tvb @sicXnull config/boards/xiaomi-elish.conf @amazingfate -config/boards/xiaomi-umi.conf @FantasyGmm +config/boards/xiaomi-umi.eos @FantasyGmm config/boards/youyeetoo-r1-v3.csc @SuperKali config/kernel/linux-arm64-*.config @FantasyGmm config/kernel/linux-bcm2711-*.config @PanderMusubi @teknoid @@ -160,7 +160,7 @@ config/kernel/linux-imx8m-*.config @schmiedelm config/kernel/linux-k3-*.config @glneo config/kernel/linux-meson-*.config @hzyitc config/kernel/linux-meson-s4t7-*.config @adeepn @rpardini @viraniac -config/kernel/linux-meson64-*.config @NicoD-SBC @SteeManMI @Tonymac32 @adeepn @bretmlw @clee @engineer-80 @igorpecovnik @jeanrhum @monkaBlyat @pyavitz @rpardini @teknoid +config/kernel/linux-meson64-*.config @NicoD-SBC @SteeManMI @Tonymac32 @adeepn @clee @engineer-80 @igorpecovnik @jeanrhum @monkaBlyat @pyavitz @rpardini @teknoid config/kernel/linux-mvebu-*.config @Heisath config/kernel/linux-odroidxu4-*.config @joekhoobyar config/kernel/linux-phytium-embedded-*.config @chainsx @@ -184,7 +184,7 @@ patch/kernel/bcm2711-*/ @PanderMusubi @teknoid patch/kernel/imx8m-*/ @schmiedelm patch/kernel/k3-*/ @glneo patch/kernel/meson-*/ @hzyitc -patch/kernel/meson64-*/ @NicoD-SBC @SteeManMI @Tonymac32 @adeepn @bretmlw @clee @engineer-80 @igorpecovnik @jeanrhum @monkaBlyat @pyavitz @rpardini @teknoid +patch/kernel/meson64-*/ @NicoD-SBC @SteeManMI @Tonymac32 @adeepn @clee @engineer-80 @igorpecovnik @jeanrhum @monkaBlyat @pyavitz @rpardini @teknoid patch/kernel/mvebu-*/ @Heisath patch/kernel/odroidxu4-*/ @joekhoobyar patch/kernel/phytium-embedded-*/ @chainsx @@ -202,7 +202,7 @@ sources/families/imx8m.conf @schmiedelm sources/families/k3.conf @glneo sources/families/meson-s4t7.conf @adeepn @rpardini @viraniac sources/families/meson.conf @hzyitc -sources/families/meson64.conf @NicoD-SBC @SteeManMI @Tonymac32 @adeepn @bretmlw @clee @engineer-80 @igorpecovnik @jeanrhum @monkaBlyat @pyavitz @rpardini @teknoid +sources/families/meson64.conf @NicoD-SBC @SteeManMI @Tonymac32 @adeepn @clee @engineer-80 @igorpecovnik @jeanrhum @monkaBlyat @pyavitz @rpardini @teknoid sources/families/mvebu.conf @Heisath sources/families/odroidxu4.conf @joekhoobyar sources/families/phytium-embedded.conf @chainsx diff --git a/config/boards/bananapim5.conf b/config/boards/bananapim5.conf index 8dfa3f417182..97cf7c5ed6b4 100644 --- a/config/boards/bananapim5.conf +++ b/config/boards/bananapim5.conf @@ -1,7 +1,7 @@ # Amlogic S905X3 quad core 2-4GB RAM SoC eMMC GBE USB3 SPI BOARD_NAME="Banana Pi M5" BOARDFAMILY="meson-sm1" -BOARD_MAINTAINER="bretmlw" +BOARD_MAINTAINER="igorpecovnik" BOOTCONFIG="bananapi-m5_defconfig" BOOT_FDT_FILE="amlogic/meson-sm1-bananapi-m5.dtb" KERNEL_TARGET="current,edge" diff --git a/config/boards/retroidpocket-rp5.csc b/config/boards/retroidpocket-rp5.csc index d0caffdc5ad7..4da38f80cbb6 100644 --- a/config/boards/retroidpocket-rp5.csc +++ b/config/boards/retroidpocket-rp5.csc @@ -1,6 +1,6 @@ # Retroid Pocket RP5 Configuration declare -g BOARD_NAME="Retroid Pocket RP5" -declare -g BOARD_MAINTAINER="tjstyle" +declare -g BOARD_MAINTAINER="" declare -g BOARDFAMILY="sm8250" declare -g KERNEL_TARGET="current" declare -g EXTRAWIFI="no" diff --git a/config/boards/retroidpocket-rpmini.csc b/config/boards/retroidpocket-rpmini.csc index 9b5d79fd9395..8b549b0600d5 100644 --- a/config/boards/retroidpocket-rpmini.csc +++ b/config/boards/retroidpocket-rpmini.csc @@ -1,6 +1,6 @@ # Retroid Pocket RPMini Configuration declare -g BOARD_NAME="Retroid Pocket RPMini" -declare -g BOARD_MAINTAINER="tjstyle" +declare -g BOARD_MAINTAINER="" declare -g BOARDFAMILY="sm8250" declare -g KERNEL_TARGET="current" declare -g EXTRAWIFI="no" diff --git a/config/boards/rock-s0.conf b/config/boards/rock-s0.conf index edfed9983a0d..8bb1955c012f 100644 --- a/config/boards/rock-s0.conf +++ b/config/boards/rock-s0.conf @@ -3,7 +3,7 @@ BOARD_NAME="Rock S0" BOARDFAMILY=rockchip64 -BOARD_MAINTAINER=brentr +BOARD_MAINTAINER="brentr" BOOTCONFIG=rock-s0-rk3308_defconfig BOOT_FDT_FILE=rockchip/rk3308-rock-s0.dtb diff --git a/config/boards/rockpi-s.conf b/config/boards/rockpi-s.conf index 7344c9883d0c..c61d8a4b83ac 100644 --- a/config/boards/rockpi-s.conf +++ b/config/boards/rockpi-s.conf @@ -3,7 +3,7 @@ BOARD_NAME="Rockpi S" BOARDFAMILY=rockchip64 -BOARD_MAINTAINER=brentr +BOARD_MAINTAINER="brentr" BOOTCONFIG=rock-pi-s-rk3308_defconfig BOOT_FDT_FILE=rockchip/rk3308-rock-pi-s.dtb From db3fdc74117392d3d0c0ec02811c8939769fe6da Mon Sep 17 00:00:00 2001 From: Patrick Yavitz Date: Wed, 4 Dec 2024 12:53:29 -0500 Subject: [PATCH 010/120] BananaPi BPI-CM4: `Enable i2c2 via overlay` Discussion: https://forum.armbian.com/topic/47842-how-do-i-enable-i2c2-on-armbian-24111-bookworm-minimal/ Signed-off-by: Patrick Yavitz --- .../archive/meson64-6.12/overlay/Makefile | 1 + .../overlay/meson-g12b-bananapi-cm4-i2c2.dtso | 20 +++++++++++++++++++ .../archive/meson64-6.6/overlay/Makefile | 1 + .../overlay/meson-g12b-bananapi-cm4-i2c2.dts | 20 +++++++++++++++++++ 4 files changed, 42 insertions(+) create mode 100644 patch/kernel/archive/meson64-6.12/overlay/meson-g12b-bananapi-cm4-i2c2.dtso create mode 100644 patch/kernel/archive/meson64-6.6/overlay/meson-g12b-bananapi-cm4-i2c2.dts diff --git a/patch/kernel/archive/meson64-6.12/overlay/Makefile b/patch/kernel/archive/meson64-6.12/overlay/Makefile index fe5e0f7258cd..cff92a0bffea 100644 --- a/patch/kernel/archive/meson64-6.12/overlay/Makefile +++ b/patch/kernel/archive/meson64-6.12/overlay/Makefile @@ -21,6 +21,7 @@ dtbo-$(CONFIG_ARCH_MESON) += \ meson-g12a-radxa-zero-uart-ao-b-on-gpioao-2-gpioao-3.dtbo \ meson-g12a-radxa-zero-uart-ao-b-on-gpioao-8-gpioao-9.dtbo \ meson-g12a-radxa-zero-uart-ee-c.dtbo \ + meson-g12b-bananapi-cm4-i2c2.dtbo \ meson-g12b-bananapi-cm4-pwm-gpioh-5-fan.dtbo \ meson-g12b-bananapi-cm4-wifi-freq-200mhz.dtbo \ meson-g12b-bananapi-m2s-rtl8822cs.dtbo \ diff --git a/patch/kernel/archive/meson64-6.12/overlay/meson-g12b-bananapi-cm4-i2c2.dtso b/patch/kernel/archive/meson64-6.12/overlay/meson-g12b-bananapi-cm4-i2c2.dtso new file mode 100644 index 000000000000..b0fbeee3d2ff --- /dev/null +++ b/patch/kernel/archive/meson64-6.12/overlay/meson-g12b-bananapi-cm4-i2c2.dtso @@ -0,0 +1,20 @@ +/dts-v1/; +/plugin/; + +/ { + compatible = "bananapi,bpi-cm4io", "bananapi,bpi-cm4", "amlogic,a311d", "amlogic,g12b"; + + fragment@0 { + target = <&i2c2>; + __overlay__ { + status = "okay"; + }; + }; + + fragment@1 { + target = <&uart_A>; + __overlay__ { + status = "disabled"; + }; + }; +}; diff --git a/patch/kernel/archive/meson64-6.6/overlay/Makefile b/patch/kernel/archive/meson64-6.6/overlay/Makefile index 1373e070c6b9..9a6893242991 100644 --- a/patch/kernel/archive/meson64-6.6/overlay/Makefile +++ b/patch/kernel/archive/meson64-6.6/overlay/Makefile @@ -21,6 +21,7 @@ dtbo-$(CONFIG_ARCH_MESON) += \ meson-g12a-radxa-zero-uart-ao-b-on-gpioao-2-gpioao-3.dtbo \ meson-g12a-radxa-zero-uart-ao-b-on-gpioao-8-gpioao-9.dtbo \ meson-g12a-radxa-zero-uart-ee-c.dtbo \ + meson-g12b-bananapi-cm4-i2c2.dtbo \ meson-g12b-bananapi-cm4-pwm-gpioh-5-fan.dtbo \ meson-g12b-bananapi-cm4-wifi-freq-200mhz.dtbo \ meson-g12b-bananapi-m2s-rtl8822cs.dtbo \ diff --git a/patch/kernel/archive/meson64-6.6/overlay/meson-g12b-bananapi-cm4-i2c2.dts b/patch/kernel/archive/meson64-6.6/overlay/meson-g12b-bananapi-cm4-i2c2.dts new file mode 100644 index 000000000000..b0fbeee3d2ff --- /dev/null +++ b/patch/kernel/archive/meson64-6.6/overlay/meson-g12b-bananapi-cm4-i2c2.dts @@ -0,0 +1,20 @@ +/dts-v1/; +/plugin/; + +/ { + compatible = "bananapi,bpi-cm4io", "bananapi,bpi-cm4", "amlogic,a311d", "amlogic,g12b"; + + fragment@0 { + target = <&i2c2>; + __overlay__ { + status = "okay"; + }; + }; + + fragment@1 { + target = <&uart_A>; + __overlay__ { + status = "disabled"; + }; + }; +}; From 316169b0a0ecc012d658053a19e3487d1a353a5f Mon Sep 17 00:00:00 2001 From: Paolo Sabatino Date: Sat, 30 Nov 2024 18:20:50 +0100 Subject: [PATCH 011/120] rockchip: remove kernel 6.11 patch leftovers --- .../linux-0002-rockchip-from-list.patch | 131 - .../linux-0011-v4l2-from-list.patch | 659 ---- .../linux-1000-drm-rockchip.patch | 2901 --------------- .../linux-1001-v4l2-rockchip.patch | 506 --- .../linux-1002-for-libreelec.patch | 688 ---- .../linux-2000-v4l2-wip-rkvdec-hevc.patch | 3226 ----------------- .../linux-2001-v4l2-wip-iep-driver.patch | 1805 --------- 7 files changed, 9916 deletions(-) delete mode 100644 patch/kernel/archive/rockchip-6.11/patches.libreelec/linux-0002-rockchip-from-list.patch delete mode 100644 patch/kernel/archive/rockchip-6.11/patches.libreelec/linux-0011-v4l2-from-list.patch delete mode 100644 patch/kernel/archive/rockchip-6.11/patches.libreelec/linux-1000-drm-rockchip.patch delete mode 100644 patch/kernel/archive/rockchip-6.11/patches.libreelec/linux-1001-v4l2-rockchip.patch delete mode 100644 patch/kernel/archive/rockchip-6.11/patches.libreelec/linux-1002-for-libreelec.patch delete mode 100644 patch/kernel/archive/rockchip-6.11/patches.libreelec/linux-2000-v4l2-wip-rkvdec-hevc.patch delete mode 100644 patch/kernel/archive/rockchip-6.11/patches.libreelec/linux-2001-v4l2-wip-iep-driver.patch diff --git a/patch/kernel/archive/rockchip-6.11/patches.libreelec/linux-0002-rockchip-from-list.patch b/patch/kernel/archive/rockchip-6.11/patches.libreelec/linux-0002-rockchip-from-list.patch deleted file mode 100644 index 517eaf53c059..000000000000 --- a/patch/kernel/archive/rockchip-6.11/patches.libreelec/linux-0002-rockchip-from-list.patch +++ /dev/null @@ -1,131 +0,0 @@ -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Jonas Karlman -Date: Sun, 17 Feb 2019 22:14:38 +0000 -Subject: [PATCH] mmc: core: set initial signal voltage on power off - -Some boards have SD card connectors where the power rail cannot be switched -off by the driver. If the card has not been power cycled, it may still be -using 1.8V signaling after a warm re-boot. Bootroms expecting 3.3V signaling -will fail to boot from a UHS card that continue to use 1.8V signaling. - -Set initial signal voltage in mmc_power_off() to allow re-boot to function. - -This fixes re-boot with UHS cards on Asus Tinker Board (Rockchip RK3288), -same issue have been seen on some Rockchip RK3399 boards. - -I am sending this as a RFC because I have no insights into SD/MMC subsystem, -this change fix a re-boot issue on my boards and does not break emmc/sdio. -Is this an acceptable workaround? Any advice is appreciated. - -Signed-off-by: Jonas Karlman ---- - drivers/mmc/core/core.c | 8 ++++++++ - 1 file changed, 8 insertions(+) - -diff --git a/drivers/mmc/core/core.c b/drivers/mmc/core/core.c -index ef53a2578824..d4c53074154a 100644 ---- a/drivers/mmc/core/core.c -+++ b/drivers/mmc/core/core.c -@@ -1358,6 +1358,14 @@ void mmc_power_off(struct mmc_host *host) - if (host->ios.power_mode == MMC_POWER_OFF) - return; - -+ mmc_set_initial_signal_voltage(host); -+ -+ /* -+ * This delay should be sufficient to allow the power supply -+ * to reach the minimum voltage. -+ */ -+ mmc_delay(host->ios.power_delay_ms); -+ - mmc_pwrseq_power_off(host); - - host->ios.clock = 0; - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Alex Bee -Date: Wed, 23 Jun 2021 16:59:18 +0200 -Subject: [PATCH] arm64: dts: rockchip: Add sdmmc_ext for RK3328 - -RK3328 SoC has a fourth mmc controller called SDMMC_EXT. Some -boards have sdio wifi connected to it. In order to use it -one would have to add the pinctrls from sdmmc0ext group which -is done on board level. - -Signed-off-by: Alex Bee ---- - arch/arm64/boot/dts/rockchip/rk3328.dtsi | 14 ++++++++++++++ - 1 file changed, 14 insertions(+) - -diff --git a/arch/arm64/boot/dts/rockchip/rk3328.dtsi b/arch/arm64/boot/dts/rockchip/rk3328.dtsi -index 49ae15708a0b..60348d517efb 100644 ---- a/arch/arm64/boot/dts/rockchip/rk3328.dtsi -+++ b/arch/arm64/boot/dts/rockchip/rk3328.dtsi -@@ -993,6 +993,20 @@ usb_host0_ohci: usb@ff5d0000 { - status = "disabled"; - }; - -+ sdmmc_ext: mmc@ff5f0000 { -+ compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc"; -+ reg = <0x0 0xff5f0000 0x0 0x4000>; -+ interrupts = ; -+ clocks = <&cru HCLK_SDMMC_EXT>, <&cru SCLK_SDMMC_EXT>, -+ <&cru SCLK_SDMMC_EXT_DRV>, <&cru SCLK_SDMMC_EXT_SAMPLE>; -+ clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; -+ fifo-depth = <0x100>; -+ max-frequency = <150000000>; -+ resets = <&cru SRST_SDMMCEXT>; -+ reset-names = "reset"; -+ status = "disabled"; -+ }; -+ - usbdrd3: usb@ff600000 { - compatible = "rockchip,rk3328-dwc3", "snps,dwc3"; - reg = <0x0 0xff600000 0x0 0x100000>; - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Alex Bee -Date: Wed, 23 Jun 2021 17:02:08 +0200 -Subject: [PATCH] arm64: dts: rockchip: Add sdmmc/sdio/emmc reset controls for - RK3328 - -The DW MCI controller driver will use them to reset the IP block before -initialisation. - -Fixes: d717f7352ec6 ("arm64: dts: rockchip: add sdmmc/sdio/emmc nodes for RK3328 SoCs") -Signed-off-by: Alex Bee ---- - arch/arm64/boot/dts/rockchip/rk3328.dtsi | 6 ++++++ - 1 file changed, 6 insertions(+) - -diff --git a/arch/arm64/boot/dts/rockchip/rk3328.dtsi b/arch/arm64/boot/dts/rockchip/rk3328.dtsi -index 60348d517efb..d7e44d174d7b 100644 ---- a/arch/arm64/boot/dts/rockchip/rk3328.dtsi -+++ b/arch/arm64/boot/dts/rockchip/rk3328.dtsi -@@ -871,6 +871,8 @@ sdmmc: mmc@ff500000 { - clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; - fifo-depth = <0x100>; - max-frequency = <150000000>; -+ resets = <&cru SRST_MMC0>; -+ reset-names = "reset"; - status = "disabled"; - }; - -@@ -883,6 +885,8 @@ sdio: mmc@ff510000 { - clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; - fifo-depth = <0x100>; - max-frequency = <150000000>; -+ resets = <&cru SRST_SDIO>; -+ reset-names = "reset"; - status = "disabled"; - }; - -@@ -895,6 +899,8 @@ emmc: mmc@ff520000 { - clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; - fifo-depth = <0x100>; - max-frequency = <150000000>; -+ resets = <&cru SRST_EMMC>; -+ reset-names = "reset"; - status = "disabled"; - }; - diff --git a/patch/kernel/archive/rockchip-6.11/patches.libreelec/linux-0011-v4l2-from-list.patch b/patch/kernel/archive/rockchip-6.11/patches.libreelec/linux-0011-v4l2-from-list.patch deleted file mode 100644 index ed0c61c2cb9c..000000000000 --- a/patch/kernel/archive/rockchip-6.11/patches.libreelec/linux-0011-v4l2-from-list.patch +++ /dev/null @@ -1,659 +0,0 @@ -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Jonas Karlman -Date: Mon, 6 Jul 2020 21:54:35 +0000 -Subject: [PATCH] media: v4l2-common: Add helpers to calculate bytesperline and - sizeimage - -Add helper functions to calculate plane bytesperline and sizeimage, these -new helpers consider block width and height when calculating plane -bytesperline and sizeimage. - -This prepare support for new pixel formats added in next patch that make -use of block width and height. - -Signed-off-by: Jonas Karlman ---- - drivers/media/v4l2-core/v4l2-common.c | 77 +++++++++++++-------------- - 1 file changed, 38 insertions(+), 39 deletions(-) - -diff --git a/drivers/media/v4l2-core/v4l2-common.c b/drivers/media/v4l2-core/v4l2-common.c -index e0fbe6ba4b6c..cb2f1acab7cf 100644 ---- a/drivers/media/v4l2-core/v4l2-common.c -+++ b/drivers/media/v4l2-core/v4l2-common.c -@@ -338,6 +338,33 @@ static inline unsigned int v4l2_format_block_height(const struct v4l2_format_inf - return info->block_h[plane]; - } - -+static inline unsigned int v4l2_format_plane_width(const struct v4l2_format_info *info, int plane, -+ unsigned int width) -+{ -+ unsigned int hdiv = plane ? info->hdiv : 1; -+ unsigned int bytes = DIV_ROUND_UP(width * info->bpp[plane], -+ v4l2_format_block_width(info, plane) * -+ v4l2_format_block_height(info, plane)); -+ -+ return DIV_ROUND_UP(bytes, hdiv); -+} -+ -+static inline unsigned int v4l2_format_plane_height(const struct v4l2_format_info *info, int plane, -+ unsigned int height) -+{ -+ unsigned int vdiv = plane ? info->vdiv : 1; -+ unsigned int lines = ALIGN(height, v4l2_format_block_height(info, plane)); -+ -+ return DIV_ROUND_UP(lines, vdiv); -+} -+ -+static inline unsigned int v4l2_format_plane_size(const struct v4l2_format_info *info, int plane, -+ unsigned int width, unsigned int height) -+{ -+ return v4l2_format_plane_width(info, plane, width) * -+ v4l2_format_plane_height(info, plane, height); -+} -+ - void v4l2_apply_frmsize_constraints(u32 *width, u32 *height, - const struct v4l2_frmsize_stepwise *frmsize) - { -@@ -373,37 +400,19 @@ int v4l2_fill_pixfmt_mp(struct v4l2_pix_format_mplane *pixfmt, - - if (info->mem_planes == 1) { - plane = &pixfmt->plane_fmt[0]; -- plane->bytesperline = ALIGN(width, v4l2_format_block_width(info, 0)) * info->bpp[0] / info->bpp_div[0]; -+ plane->bytesperline = v4l2_format_plane_width(info, 0, width); - plane->sizeimage = 0; - -- for (i = 0; i < info->comp_planes; i++) { -- unsigned int hdiv = (i == 0) ? 1 : info->hdiv; -- unsigned int vdiv = (i == 0) ? 1 : info->vdiv; -- unsigned int aligned_width; -- unsigned int aligned_height; -- -- aligned_width = ALIGN(width, v4l2_format_block_width(info, i)); -- aligned_height = ALIGN(height, v4l2_format_block_height(info, i)); -- -- plane->sizeimage += info->bpp[i] * -- DIV_ROUND_UP(aligned_width, hdiv) * -- DIV_ROUND_UP(aligned_height, vdiv) / info->bpp_div[i]; -- } -+ for (i = 0; i < info->comp_planes; i++) -+ plane->sizeimage += -+ v4l2_format_plane_size(info, i, width, height); - } else { - for (i = 0; i < info->comp_planes; i++) { -- unsigned int hdiv = (i == 0) ? 1 : info->hdiv; -- unsigned int vdiv = (i == 0) ? 1 : info->vdiv; -- unsigned int aligned_width; -- unsigned int aligned_height; -- -- aligned_width = ALIGN(width, v4l2_format_block_width(info, i)); -- aligned_height = ALIGN(height, v4l2_format_block_height(info, i)); -- - plane = &pixfmt->plane_fmt[i]; - plane->bytesperline = -- info->bpp[i] * DIV_ROUND_UP(aligned_width, hdiv) / info->bpp_div[i]; -- plane->sizeimage = -- plane->bytesperline * DIV_ROUND_UP(aligned_height, vdiv); -+ v4l2_format_plane_width(info, i, width); -+ plane->sizeimage = plane->bytesperline * -+ v4l2_format_plane_height(info, i, height); - } - } - return 0; -@@ -427,22 +436,12 @@ int v4l2_fill_pixfmt(struct v4l2_pix_format *pixfmt, u32 pixelformat, - pixfmt->width = width; - pixfmt->height = height; - pixfmt->pixelformat = pixelformat; -- pixfmt->bytesperline = ALIGN(width, v4l2_format_block_width(info, 0)) * info->bpp[0] / info->bpp_div[0]; -+ pixfmt->bytesperline = v4l2_format_plane_width(info, 0, width); - pixfmt->sizeimage = 0; - -- for (i = 0; i < info->comp_planes; i++) { -- unsigned int hdiv = (i == 0) ? 1 : info->hdiv; -- unsigned int vdiv = (i == 0) ? 1 : info->vdiv; -- unsigned int aligned_width; -- unsigned int aligned_height; -- -- aligned_width = ALIGN(width, v4l2_format_block_width(info, i)); -- aligned_height = ALIGN(height, v4l2_format_block_height(info, i)); -- -- pixfmt->sizeimage += info->bpp[i] * -- DIV_ROUND_UP(aligned_width, hdiv) * -- DIV_ROUND_UP(aligned_height, vdiv) / info->bpp_div[i]; -- } -+ for (i = 0; i < info->comp_planes; i++) -+ pixfmt->sizeimage += -+ v4l2_format_plane_size(info, i, width, height); - return 0; - } - EXPORT_SYMBOL_GPL(v4l2_fill_pixfmt); - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Jonas Karlman -Date: Mon, 6 Jul 2020 21:54:36 +0000 -Subject: [PATCH] media: v4l2: Add NV15 and NV20 pixel formats - -Add NV15 and NV20 pixel formats used by the Rockchip Video Decoder for -10-bit buffers. - -NV15 and NV20 is a packed 10-bit 4:2:0/4:2:2 semi-planar Y/UV format -similar to P010 and P210 but has no padding between components. Instead, -luminance and chrominance samples are grouped into 4s so that each group is -packed into an integer number of bytes: - -YYYY = UVUV = 4 * 10 bits = 40 bits = 5 bytes - -The '15' and '20' suffix refers to the optimum effective bits per pixel -which is achieved when the total number of luminance samples is a multiple -of 8 for NV15 and 4 for NV20. - -Signed-off-by: Jonas Karlman ---- - drivers/media/v4l2-core/v4l2-common.c | 3 +++ - drivers/media/v4l2-core/v4l2-ioctl.c | 2 ++ - include/uapi/linux/videodev2.h | 3 +++ - 3 files changed, 8 insertions(+) - -diff --git a/drivers/media/v4l2-core/v4l2-common.c b/drivers/media/v4l2-core/v4l2-common.c -index cb2f1acab7cf..8446a1deffd8 100644 ---- a/drivers/media/v4l2-core/v4l2-common.c -+++ b/drivers/media/v4l2-core/v4l2-common.c -@@ -268,6 +268,9 @@ const struct v4l2_format_info *v4l2_format_info(u32 format) - { .format = V4L2_PIX_FMT_NV42, .pixel_enc = V4L2_PIXEL_ENC_YUV, .mem_planes = 1, .comp_planes = 2, .bpp = { 1, 2, 0, 0 }, .bpp_div = { 1, 1, 1, 1 }, .hdiv = 1, .vdiv = 1 }, - { .format = V4L2_PIX_FMT_P010, .pixel_enc = V4L2_PIXEL_ENC_YUV, .mem_planes = 1, .comp_planes = 2, .bpp = { 2, 2, 0, 0 }, .bpp_div = { 1, 1, 1, 1 }, .hdiv = 2, .vdiv = 1 }, - -+ { .format = V4L2_PIX_FMT_NV15, .pixel_enc = V4L2_PIXEL_ENC_YUV, .mem_planes = 1, .comp_planes = 2, .bpp = { 5, 5, 0, 0 }, .bpp_div = { 1, 1, 1, 1 }, .hdiv = 2, .vdiv = 2, .block_w = { 4, 2, 0, 0 }, .block_h = { 1, 1, 0, 0 } }, -+ { .format = V4L2_PIX_FMT_NV20, .pixel_enc = V4L2_PIXEL_ENC_YUV, .mem_planes = 1, .comp_planes = 2, .bpp = { 5, 5, 0, 0 }, .bpp_div = { 1, 1, 1, 1 }, .hdiv = 2, .vdiv = 1, .block_w = { 4, 2, 0, 0 }, .block_h = { 1, 1, 0, 0 } }, -+ - { .format = V4L2_PIX_FMT_YUV410, .pixel_enc = V4L2_PIXEL_ENC_YUV, .mem_planes = 1, .comp_planes = 3, .bpp = { 1, 1, 1, 0 }, .bpp_div = { 1, 1, 1, 1 }, .hdiv = 4, .vdiv = 4 }, - { .format = V4L2_PIX_FMT_YVU410, .pixel_enc = V4L2_PIXEL_ENC_YUV, .mem_planes = 1, .comp_planes = 3, .bpp = { 1, 1, 1, 0 }, .bpp_div = { 1, 1, 1, 1 }, .hdiv = 4, .vdiv = 4 }, - { .format = V4L2_PIX_FMT_YUV411P, .pixel_enc = V4L2_PIXEL_ENC_YUV, .mem_planes = 1, .comp_planes = 3, .bpp = { 1, 1, 1, 0 }, .bpp_div = { 1, 1, 1, 1 }, .hdiv = 4, .vdiv = 1 }, -diff --git a/drivers/media/v4l2-core/v4l2-ioctl.c b/drivers/media/v4l2-core/v4l2-ioctl.c -index e6fd355a2e92..24771edaa4f2 100644 ---- a/drivers/media/v4l2-core/v4l2-ioctl.c -+++ b/drivers/media/v4l2-core/v4l2-ioctl.c -@@ -1354,6 +1354,8 @@ static void v4l_fill_fmtdesc(struct v4l2_fmtdesc *fmt) - case V4L2_PIX_FMT_NV42: descr = "Y/VU 4:4:4"; break; - case V4L2_PIX_FMT_P010: descr = "10-bit Y/UV 4:2:0"; break; - case V4L2_PIX_FMT_P012: descr = "12-bit Y/UV 4:2:0"; break; -+ case V4L2_PIX_FMT_NV15: descr = "10-bit Y/UV 4:2:0 (Packed)"; break; -+ case V4L2_PIX_FMT_NV20: descr = "10-bit Y/UV 4:2:2 (Packed)"; break; - case V4L2_PIX_FMT_NV12_4L4: descr = "Y/UV 4:2:0 (4x4 Linear)"; break; - case V4L2_PIX_FMT_NV12_16L16: descr = "Y/UV 4:2:0 (16x16 Linear)"; break; - case V4L2_PIX_FMT_NV12_32L32: descr = "Y/UV 4:2:0 (32x32 Linear)"; break; -diff --git a/include/uapi/linux/videodev2.h b/include/uapi/linux/videodev2.h -index 01e630f2ec78..cea44992aea3 100644 ---- a/include/uapi/linux/videodev2.h -+++ b/include/uapi/linux/videodev2.h -@@ -628,6 +628,9 @@ struct v4l2_pix_format { - #define V4L2_PIX_FMT_NV42 v4l2_fourcc('N', 'V', '4', '2') /* 24 Y/VU 4:4:4 */ - #define V4L2_PIX_FMT_P010 v4l2_fourcc('P', '0', '1', '0') /* 24 Y/UV 4:2:0 10-bit per component */ - -+#define V4L2_PIX_FMT_NV15 v4l2_fourcc('N', 'V', '1', '5') /* 15 Y/UV 4:2:0 10-bit packed */ -+#define V4L2_PIX_FMT_NV20 v4l2_fourcc('N', 'V', '2', '0') /* 20 Y/UV 4:2:2 10-bit packed */ -+ - /* two non contiguous planes - one Y, one Cr + Cb interleaved */ - #define V4L2_PIX_FMT_NV12M v4l2_fourcc('N', 'M', '1', '2') /* 12 Y/UV 4:2:0 */ - #define V4L2_PIX_FMT_NV21M v4l2_fourcc('N', 'M', '2', '1') /* 21 Y/VU 4:2:0 */ - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Jonas Karlman -Date: Mon, 6 Jul 2020 21:54:36 +0000 -Subject: [PATCH] media: rkvdec: h264: Use bytesperline and buffer height to - calculate stride - -Use bytesperline and buffer height to calculate the strides configured. - -This does not really change anything other than ensuring the bytesperline -that is signaled to userspace matches what is configured in HW. - -Signed-off-by: Jonas Karlman ---- - drivers/staging/media/rkvdec/rkvdec-h264.c | 10 +++++----- - 1 file changed, 5 insertions(+), 5 deletions(-) - -diff --git a/drivers/staging/media/rkvdec/rkvdec-h264.c b/drivers/staging/media/rkvdec/rkvdec-h264.c -index 4fc167b42cf0..a8635105e387 100644 ---- a/drivers/staging/media/rkvdec/rkvdec-h264.c -+++ b/drivers/staging/media/rkvdec/rkvdec-h264.c -@@ -896,9 +896,9 @@ static void config_registers(struct rkvdec_ctx *ctx, - dma_addr_t rlc_addr; - dma_addr_t refer_addr; - u32 rlc_len; -- u32 hor_virstride = 0; -- u32 ver_virstride = 0; -- u32 y_virstride = 0; -+ u32 hor_virstride; -+ u32 ver_virstride; -+ u32 y_virstride; - u32 yuv_virstride = 0; - u32 offset; - dma_addr_t dst_addr; -@@ -909,8 +909,8 @@ static void config_registers(struct rkvdec_ctx *ctx, - - f = &ctx->decoded_fmt; - dst_fmt = &f->fmt.pix_mp; -- hor_virstride = (sps->bit_depth_luma_minus8 + 8) * dst_fmt->width / 8; -- ver_virstride = round_up(dst_fmt->height, 16); -+ hor_virstride = dst_fmt->plane_fmt[0].bytesperline; -+ ver_virstride = dst_fmt->height; - y_virstride = hor_virstride * ver_virstride; - - if (sps->chroma_format_idc == 0) - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Jonas Karlman -Date: Mon, 6 Jul 2020 21:54:37 +0000 -Subject: [PATCH] media: rkvdec: Extract rkvdec_fill_decoded_pixfmt helper - method - -This extract setting decoded pixfmt into a helper method, current code is -replaced with a call to the new helper method. - -The helper method is also called from a new function in next patch. - -Signed-off-by: Jonas Karlman ---- - drivers/staging/media/rkvdec/rkvdec.c | 29 ++++++++++++++------------- - 1 file changed, 15 insertions(+), 14 deletions(-) - -diff --git a/drivers/staging/media/rkvdec/rkvdec.c b/drivers/staging/media/rkvdec/rkvdec.c -index 7bab7586918c..40cc791aef26 100644 ---- a/drivers/staging/media/rkvdec/rkvdec.c -+++ b/drivers/staging/media/rkvdec/rkvdec.c -@@ -27,6 +27,17 @@ - #include "rkvdec.h" - #include "rkvdec-regs.h" - -+static void rkvdec_fill_decoded_pixfmt(struct rkvdec_ctx *ctx, -+ struct v4l2_pix_format_mplane *pix_mp) -+{ -+ v4l2_fill_pixfmt_mp(pix_mp, pix_mp->pixelformat, -+ pix_mp->width, pix_mp->height); -+ pix_mp->plane_fmt[0].sizeimage += 128 * -+ DIV_ROUND_UP(pix_mp->width, 16) * -+ DIV_ROUND_UP(pix_mp->height, 16); -+ pix_mp->field = V4L2_FIELD_NONE; -+} -+ - static int rkvdec_try_ctrl(struct v4l2_ctrl *ctrl) - { - struct rkvdec_ctx *ctx = container_of(ctrl->handler, struct rkvdec_ctx, ctrl_hdl); -@@ -192,13 +203,9 @@ static void rkvdec_reset_decoded_fmt(struct rkvdec_ctx *ctx) - - rkvdec_reset_fmt(ctx, f, ctx->coded_fmt_desc->decoded_fmts[0]); - f->type = V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE; -- v4l2_fill_pixfmt_mp(&f->fmt.pix_mp, -- ctx->coded_fmt_desc->decoded_fmts[0], -- ctx->coded_fmt.fmt.pix_mp.width, -- ctx->coded_fmt.fmt.pix_mp.height); -- f->fmt.pix_mp.plane_fmt[0].sizeimage += 128 * -- DIV_ROUND_UP(f->fmt.pix_mp.width, 16) * -- DIV_ROUND_UP(f->fmt.pix_mp.height, 16); -+ f->fmt.pix_mp.width = ctx->coded_fmt.fmt.pix_mp.width; -+ f->fmt.pix_mp.height = ctx->coded_fmt.fmt.pix_mp.height; -+ rkvdec_fill_decoded_pixfmt(ctx, &f->fmt.pix_mp); - } - - static int rkvdec_enum_framesizes(struct file *file, void *priv, -@@ -264,13 +271,7 @@ static int rkvdec_try_capture_fmt(struct file *file, void *priv, - &pix_mp->height, - &coded_desc->frmsize); - -- v4l2_fill_pixfmt_mp(pix_mp, pix_mp->pixelformat, -- pix_mp->width, pix_mp->height); -- pix_mp->plane_fmt[0].sizeimage += -- 128 * -- DIV_ROUND_UP(pix_mp->width, 16) * -- DIV_ROUND_UP(pix_mp->height, 16); -- pix_mp->field = V4L2_FIELD_NONE; -+ rkvdec_fill_decoded_pixfmt(ctx, pix_mp); - - return 0; - } - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Jonas Karlman -Date: Mon, 6 Jul 2020 21:54:37 +0000 -Subject: [PATCH] media: rkvdec: Lock capture pixel format in s_ctrl and s_fmt - -Add an optional valid_fmt operation that should return the valid -pixelformat of CAPTURE buffers. - -This is used in next patch to ensure correct pixelformat is used for 10-bit -and 4:2:2 content. - -Signed-off-by: Jonas Karlman ---- - drivers/staging/media/rkvdec/rkvdec.c | 67 +++++++++++++++++++++++---- - drivers/staging/media/rkvdec/rkvdec.h | 2 + - 2 files changed, 61 insertions(+), 8 deletions(-) - -diff --git a/drivers/staging/media/rkvdec/rkvdec.c b/drivers/staging/media/rkvdec/rkvdec.c -index 40cc791aef26..e93e1cb0f829 100644 ---- a/drivers/staging/media/rkvdec/rkvdec.c -+++ b/drivers/staging/media/rkvdec/rkvdec.c -@@ -38,19 +38,56 @@ static void rkvdec_fill_decoded_pixfmt(struct rkvdec_ctx *ctx, - pix_mp->field = V4L2_FIELD_NONE; - } - -+static u32 rkvdec_valid_fmt(struct rkvdec_ctx *ctx, struct v4l2_ctrl *ctrl) -+{ -+ const struct rkvdec_coded_fmt_desc *coded_desc = ctx->coded_fmt_desc; -+ -+ if (coded_desc->ops->valid_fmt) -+ return coded_desc->ops->valid_fmt(ctx, ctrl); -+ -+ return ctx->valid_fmt; -+} -+ - static int rkvdec_try_ctrl(struct v4l2_ctrl *ctrl) - { - struct rkvdec_ctx *ctx = container_of(ctrl->handler, struct rkvdec_ctx, ctrl_hdl); - const struct rkvdec_coded_fmt_desc *desc = ctx->coded_fmt_desc; - -- if (desc->ops->try_ctrl) -- return desc->ops->try_ctrl(ctx, ctrl); -+ if (desc->ops->try_ctrl) { -+ int ret; -+ ret = desc->ops->try_ctrl(ctx, ctrl); -+ if (ret) -+ return ret; -+ } -+ -+ if (ctx->valid_fmt && ctx->valid_fmt != rkvdec_valid_fmt(ctx, ctrl)) -+ /* Only current valid format */ -+ return -EINVAL; -+ -+ return 0; -+} -+ -+static int rkvdec_s_ctrl(struct v4l2_ctrl *ctrl) -+{ -+ struct rkvdec_ctx *ctx = container_of(ctrl->handler, struct rkvdec_ctx, ctrl_hdl); -+ -+ if (ctrl->id == V4L2_CID_STATELESS_H264_SPS && !ctx->valid_fmt) { -+ ctx->valid_fmt = rkvdec_valid_fmt(ctx, ctrl); -+ if (ctx->valid_fmt) { -+ struct v4l2_pix_format_mplane *pix_mp; -+ -+ pix_mp = &ctx->decoded_fmt.fmt.pix_mp; -+ pix_mp->pixelformat = ctx->valid_fmt; -+ rkvdec_fill_decoded_pixfmt(ctx, pix_mp); -+ } -+ } - - return 0; - } - - static const struct v4l2_ctrl_ops rkvdec_ctrl_ops = { - .try_ctrl = rkvdec_try_ctrl, -+ .s_ctrl = rkvdec_s_ctrl, - }; - - static const struct rkvdec_ctrl_desc rkvdec_h264_ctrl_descs[] = { -@@ -201,6 +238,7 @@ static void rkvdec_reset_decoded_fmt(struct rkvdec_ctx *ctx) - { - struct v4l2_format *f = &ctx->decoded_fmt; - -+ ctx->valid_fmt = 0; - rkvdec_reset_fmt(ctx, f, ctx->coded_fmt_desc->decoded_fmts[0]); - f->type = V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE; - f->fmt.pix_mp.width = ctx->coded_fmt.fmt.pix_mp.width; -@@ -256,13 +294,17 @@ static int rkvdec_try_capture_fmt(struct file *file, void *priv, - if (WARN_ON(!coded_desc)) - return -EINVAL; - -- for (i = 0; i < coded_desc->num_decoded_fmts; i++) { -- if (coded_desc->decoded_fmts[i] == pix_mp->pixelformat) -- break; -- } -+ if (ctx->valid_fmt) { -+ pix_mp->pixelformat = ctx->valid_fmt; -+ } else { -+ for (i = 0; i < coded_desc->num_decoded_fmts; i++) { -+ if (coded_desc->decoded_fmts[i] == pix_mp->pixelformat) -+ break; -+ } - -- if (i == coded_desc->num_decoded_fmts) -- pix_mp->pixelformat = coded_desc->decoded_fmts[0]; -+ if (i == coded_desc->num_decoded_fmts) -+ pix_mp->pixelformat = coded_desc->decoded_fmts[0]; -+ } - - /* Always apply the frmsize constraint of the coded end. */ - pix_mp->width = max(pix_mp->width, ctx->coded_fmt.fmt.pix_mp.width); -@@ -326,6 +368,7 @@ static int rkvdec_s_capture_fmt(struct file *file, void *priv, - return ret; - - ctx->decoded_fmt = *f; -+ ctx->valid_fmt = f->fmt.pix_mp.pixelformat; - return 0; - } - -@@ -429,6 +472,14 @@ static int rkvdec_enum_capture_fmt(struct file *file, void *priv, - if (WARN_ON(!ctx->coded_fmt_desc)) - return -EINVAL; - -+ if (ctx->valid_fmt) { -+ if (f->index) -+ return -EINVAL; -+ -+ f->pixelformat = ctx->valid_fmt; -+ return 0; -+ } -+ - if (f->index >= ctx->coded_fmt_desc->num_decoded_fmts) - return -EINVAL; - -diff --git a/drivers/staging/media/rkvdec/rkvdec.h b/drivers/staging/media/rkvdec/rkvdec.h -index 633335ebb9c4..b9e219438bc9 100644 ---- a/drivers/staging/media/rkvdec/rkvdec.h -+++ b/drivers/staging/media/rkvdec/rkvdec.h -@@ -66,6 +66,7 @@ vb2_to_rkvdec_decoded_buf(struct vb2_buffer *buf) - struct rkvdec_coded_fmt_ops { - int (*adjust_fmt)(struct rkvdec_ctx *ctx, - struct v4l2_format *f); -+ u32 (*valid_fmt)(struct rkvdec_ctx *ctx, struct v4l2_ctrl *ctrl); - int (*start)(struct rkvdec_ctx *ctx); - void (*stop)(struct rkvdec_ctx *ctx); - int (*run)(struct rkvdec_ctx *ctx); -@@ -101,6 +102,7 @@ struct rkvdec_ctx { - struct v4l2_fh fh; - struct v4l2_format coded_fmt; - struct v4l2_format decoded_fmt; -+ u32 valid_fmt; - const struct rkvdec_coded_fmt_desc *coded_fmt_desc; - struct v4l2_ctrl_handler ctrl_hdl; - struct rkvdec_dev *dev; - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Jonas Karlman -Date: Mon, 6 Jul 2020 21:54:37 +0000 -Subject: [PATCH] media: rkvdec: h264: Support High 10 and 4:2:2 profiles - -Add support and enable decoding of H264 High 10 and 4:2:2 profiles. - -Decoded CAPTURE buffer width is aligned to 64 pixels to accommodate HW -requirement on 10-bit format buffers. - -The new valid_fmt operation is implemented and return a valid pixelformat -for the provided SPS control. - -Signed-off-by: Jonas Karlman ---- - drivers/staging/media/rkvdec/rkvdec-h264.c | 33 ++++++++++++++++------ - drivers/staging/media/rkvdec/rkvdec.c | 19 +++++++++---- - 2 files changed, 37 insertions(+), 15 deletions(-) - -diff --git a/drivers/staging/media/rkvdec/rkvdec-h264.c b/drivers/staging/media/rkvdec/rkvdec-h264.c -index a8635105e387..0069d3d198db 100644 ---- a/drivers/staging/media/rkvdec/rkvdec-h264.c -+++ b/drivers/staging/media/rkvdec/rkvdec-h264.c -@@ -1031,19 +1031,14 @@ static int rkvdec_h264_validate_sps(struct rkvdec_ctx *ctx, - { - unsigned int width, height; - -- /* -- * TODO: The hardware supports 10-bit and 4:2:2 profiles, -- * but it's currently broken in the driver. -- * Reject them for now, until it's fixed. -- */ -- if (sps->chroma_format_idc > 1) -- /* Only 4:0:0 and 4:2:0 are supported */ -+ if (sps->chroma_format_idc > 2) -+ /* Only 4:0:0, 4:2:0 and 4:2:2 are supported */ - return -EINVAL; - if (sps->bit_depth_luma_minus8 != sps->bit_depth_chroma_minus8) - /* Luma and chroma bit depth mismatch */ - return -EINVAL; -- if (sps->bit_depth_luma_minus8 != 0) -- /* Only 8-bit is supported */ -+ if (sps->bit_depth_luma_minus8 != 0 && sps->bit_depth_luma_minus8 != 2) -+ /* Only 8-bit and 10-bit is supported */ - return -EINVAL; - - width = (sps->pic_width_in_mbs_minus1 + 1) * 16; -@@ -1064,6 +1059,25 @@ static int rkvdec_h264_validate_sps(struct rkvdec_ctx *ctx, - return 0; - } - -+static u32 rkvdec_h264_valid_fmt(struct rkvdec_ctx *ctx, struct v4l2_ctrl *ctrl) -+{ -+ const struct v4l2_ctrl_h264_sps *sps = ctrl->p_new.p_h264_sps; -+ -+ if (sps->bit_depth_luma_minus8 == 0) { -+ if (sps->chroma_format_idc == 2) -+ return V4L2_PIX_FMT_NV16; -+ else -+ return V4L2_PIX_FMT_NV12; -+ } else if (sps->bit_depth_luma_minus8 == 2) { -+ if (sps->chroma_format_idc == 2) -+ return V4L2_PIX_FMT_NV20; -+ else -+ return V4L2_PIX_FMT_NV15; -+ } -+ -+ return 0; -+} -+ - static int rkvdec_h264_start(struct rkvdec_ctx *ctx) - { - struct rkvdec_dev *rkvdec = ctx->dev; -@@ -1185,6 +1199,7 @@ static int rkvdec_h264_try_ctrl(struct rkvdec_ctx *ctx, struct v4l2_ctrl *ctrl) - - const struct rkvdec_coded_fmt_ops rkvdec_h264_fmt_ops = { - .adjust_fmt = rkvdec_h264_adjust_fmt, -+ .valid_fmt = rkvdec_h264_valid_fmt, - .start = rkvdec_h264_start, - .stop = rkvdec_h264_stop, - .run = rkvdec_h264_run, -diff --git a/drivers/staging/media/rkvdec/rkvdec.c b/drivers/staging/media/rkvdec/rkvdec.c -index e93e1cb0f829..4f5436c89e08 100644 ---- a/drivers/staging/media/rkvdec/rkvdec.c -+++ b/drivers/staging/media/rkvdec/rkvdec.c -@@ -31,7 +31,7 @@ static void rkvdec_fill_decoded_pixfmt(struct rkvdec_ctx *ctx, - struct v4l2_pix_format_mplane *pix_mp) - { - v4l2_fill_pixfmt_mp(pix_mp, pix_mp->pixelformat, -- pix_mp->width, pix_mp->height); -+ ALIGN(pix_mp->width, 64), pix_mp->height); - pix_mp->plane_fmt[0].sizeimage += 128 * - DIV_ROUND_UP(pix_mp->width, 16) * - DIV_ROUND_UP(pix_mp->height, 16); -@@ -136,8 +136,11 @@ static const struct rkvdec_ctrls rkvdec_h264_ctrls = { - .num_ctrls = ARRAY_SIZE(rkvdec_h264_ctrl_descs), - }; - --static const u32 rkvdec_h264_vp9_decoded_fmts[] = { -+static const u32 rkvdec_h264_decoded_fmts[] = { - V4L2_PIX_FMT_NV12, -+ V4L2_PIX_FMT_NV15, -+ V4L2_PIX_FMT_NV16, -+ V4L2_PIX_FMT_NV20, - }; - - static const struct rkvdec_ctrl_desc rkvdec_vp9_ctrl_descs[] = { -@@ -160,6 +163,10 @@ static const struct rkvdec_ctrls rkvdec_vp9_ctrls = { - .num_ctrls = ARRAY_SIZE(rkvdec_vp9_ctrl_descs), - }; - -+static const u32 rkvdec_vp9_decoded_fmts[] = { -+ V4L2_PIX_FMT_NV12, -+}; -+ - static const struct rkvdec_coded_fmt_desc rkvdec_coded_fmts[] = { - { - .fourcc = V4L2_PIX_FMT_H264_SLICE, -@@ -173,8 +180,8 @@ static const struct rkvdec_coded_fmt_desc rkvdec_coded_fmts[] = { - }, - .ctrls = &rkvdec_h264_ctrls, - .ops = &rkvdec_h264_fmt_ops, -- .num_decoded_fmts = ARRAY_SIZE(rkvdec_h264_vp9_decoded_fmts), -- .decoded_fmts = rkvdec_h264_vp9_decoded_fmts, -+ .num_decoded_fmts = ARRAY_SIZE(rkvdec_h264_decoded_fmts), -+ .decoded_fmts = rkvdec_h264_decoded_fmts, - .subsystem_flags = VB2_V4L2_FL_SUPPORTS_M2M_HOLD_CAPTURE_BUF, - }, - { -@@ -189,8 +196,8 @@ static const struct rkvdec_coded_fmt_desc rkvdec_coded_fmts[] = { - }, - .ctrls = &rkvdec_vp9_ctrls, - .ops = &rkvdec_vp9_fmt_ops, -- .num_decoded_fmts = ARRAY_SIZE(rkvdec_h264_vp9_decoded_fmts), -- .decoded_fmts = rkvdec_h264_vp9_decoded_fmts, -+ .num_decoded_fmts = ARRAY_SIZE(rkvdec_vp9_decoded_fmts), -+ .decoded_fmts = rkvdec_vp9_decoded_fmts, - } - }; - - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Alex Bee -Date: Sun, 27 Mar 2022 14:18:07 +0200 -Subject: [PATCH] media: rkvdec-h264: Don't hardcode SPS/PPS parameters - -Some SPS/PPS parameters are currently hardcoded in the driver -even though so do exist in the uapi which is stable by now. - -Use them instead of hardcoding them. - -Signed-off-by: Alex Bee ---- - drivers/staging/media/rkvdec/rkvdec-h264.c | 13 +++++++------ - 1 file changed, 7 insertions(+), 6 deletions(-) - -diff --git a/drivers/staging/media/rkvdec/rkvdec-h264.c b/drivers/staging/media/rkvdec/rkvdec-h264.c -index 0069d3d198db..2c27acaba85e 100644 ---- a/drivers/staging/media/rkvdec/rkvdec-h264.c -+++ b/drivers/staging/media/rkvdec/rkvdec-h264.c -@@ -655,13 +655,14 @@ static void assemble_hw_pps(struct rkvdec_ctx *ctx, - - #define WRITE_PPS(value, field) set_ps_field(hw_ps->info, field, value) - /* write sps */ -- WRITE_PPS(0xf, SEQ_PARAMETER_SET_ID); -- WRITE_PPS(0xff, PROFILE_IDC); -- WRITE_PPS(1, CONSTRAINT_SET3_FLAG); -+ WRITE_PPS(sps->seq_parameter_set_id, SEQ_PARAMETER_SET_ID); -+ WRITE_PPS(sps->profile_idc, PROFILE_IDC); -+ WRITE_PPS((sps->constraint_set_flags & 1 << 3) ? 1 : 0, CONSTRAINT_SET3_FLAG); - WRITE_PPS(sps->chroma_format_idc, CHROMA_FORMAT_IDC); - WRITE_PPS(sps->bit_depth_luma_minus8, BIT_DEPTH_LUMA); - WRITE_PPS(sps->bit_depth_chroma_minus8, BIT_DEPTH_CHROMA); -- WRITE_PPS(0, QPPRIME_Y_ZERO_TRANSFORM_BYPASS_FLAG); -+ WRITE_PPS(!!(sps->flags & V4L2_H264_SPS_FLAG_QPPRIME_Y_ZERO_TRANSFORM_BYPASS), -+ QPPRIME_Y_ZERO_TRANSFORM_BYPASS_FLAG); - WRITE_PPS(sps->log2_max_frame_num_minus4, LOG2_MAX_FRAME_NUM_MINUS4); - WRITE_PPS(sps->max_num_ref_frames, MAX_NUM_REF_FRAMES); - WRITE_PPS(sps->pic_order_cnt_type, PIC_ORDER_CNT_TYPE); -@@ -688,8 +689,8 @@ static void assemble_hw_pps(struct rkvdec_ctx *ctx, - DIRECT_8X8_INFERENCE_FLAG); - - /* write pps */ -- WRITE_PPS(0xff, PIC_PARAMETER_SET_ID); -- WRITE_PPS(0x1f, PPS_SEQ_PARAMETER_SET_ID); -+ WRITE_PPS(pps->pic_parameter_set_id, PIC_PARAMETER_SET_ID); -+ WRITE_PPS(pps->seq_parameter_set_id, PPS_SEQ_PARAMETER_SET_ID); - WRITE_PPS(!!(pps->flags & V4L2_H264_PPS_FLAG_ENTROPY_CODING_MODE), - ENTROPY_CODING_MODE_FLAG); - WRITE_PPS(!!(pps->flags & V4L2_H264_PPS_FLAG_BOTTOM_FIELD_PIC_ORDER_IN_FRAME_PRESENT), diff --git a/patch/kernel/archive/rockchip-6.11/patches.libreelec/linux-1000-drm-rockchip.patch b/patch/kernel/archive/rockchip-6.11/patches.libreelec/linux-1000-drm-rockchip.patch deleted file mode 100644 index 4ecb43bb8203..000000000000 --- a/patch/kernel/archive/rockchip-6.11/patches.libreelec/linux-1000-drm-rockchip.patch +++ /dev/null @@ -1,2901 +0,0 @@ -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Jonas Karlman -Date: Sun, 3 May 2020 16:51:31 +0000 -Subject: [PATCH] drm/rockchip: vop: filter modes outside 0.5% pixel clock - tolerance - -Filter modes that require a pixel clock that differ more then 0.5% -from the requested pixel clock. - -This filter is only applied to tmds only connector and/or encoders. - -Signed-off-by: Jonas Karlman -Signed-off-by: Alex Bee ---- - drivers/gpu/drm/rockchip/rockchip_drm_vop.c | 54 +++++++++++++++++++++ - 1 file changed, 54 insertions(+) - -diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c -index dbe4d411b30f..fac23d370ee0 100644 ---- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c -+++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c -@@ -1206,6 +1206,59 @@ static void vop_crtc_disable_vblank(struct drm_crtc *crtc) - spin_unlock_irqrestore(&vop->irq_lock, flags); - } - -+static bool vop_crtc_is_tmds(struct drm_crtc *crtc) -+{ -+ struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc->state); -+ struct drm_encoder *encoder; -+ -+ switch (s->output_type) { -+ case DRM_MODE_CONNECTOR_LVDS: -+ case DRM_MODE_CONNECTOR_DSI: -+ return false; -+ case DRM_MODE_CONNECTOR_eDP: -+ case DRM_MODE_CONNECTOR_HDMIA: -+ case DRM_MODE_CONNECTOR_DisplayPort: -+ return true; -+ } -+ -+ drm_for_each_encoder_mask(encoder, crtc->dev, crtc->state->encoder_mask) -+ if (encoder->encoder_type == DRM_MODE_ENCODER_TMDS) -+ return true; -+ -+ return false; -+} -+ -+/* -+ * The VESA DMT standard specifies a 0.5% pixel clock frequency tolerance. -+ * The CVT spec reuses that tolerance in its examples. -+ */ -+#define CLOCK_TOLERANCE_PER_MILLE 5 -+ -+static enum drm_mode_status vop_crtc_mode_valid5(struct drm_crtc *crtc, -+ const struct drm_display_mode *mode) -+{ -+ struct vop *vop = to_vop(crtc); -+ long rounded_rate; -+ long lowest, highest; -+ -+ if (!vop_crtc_is_tmds(crtc)) -+ return MODE_OK; -+ -+ rounded_rate = clk_round_rate(vop->dclk, mode->clock * 1000 + 999); -+ if (rounded_rate < 0) -+ return MODE_NOCLOCK; -+ -+ lowest = mode->clock * (1000 - CLOCK_TOLERANCE_PER_MILLE); -+ if (rounded_rate < lowest) -+ return MODE_CLOCK_LOW; -+ -+ highest = mode->clock * (1000 + CLOCK_TOLERANCE_PER_MILLE); -+ if (rounded_rate > highest) -+ return MODE_CLOCK_HIGH; -+ -+ return MODE_OK; -+} -+ - static bool vop_crtc_mode_fixup(struct drm_crtc *crtc, - const struct drm_display_mode *mode, - struct drm_display_mode *adjusted_mode) - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Jonas Karlman -Date: Mon, 20 Jul 2020 15:15:50 +0000 -Subject: [PATCH] drm/rockchip: vop: filter interlaced modes - -The current version of the driver does not support interlaced modes, -lets filter any interlaced mode. - -Signed-off-by: Jonas Karlman ---- - drivers/gpu/drm/rockchip/rockchip_drm_vop.c | 3 +++ - 1 file changed, 3 insertions(+) - -diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c -index fac23d370ee0..9f7326c5b1f5 100644 ---- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c -+++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c -@@ -1244,6 +1244,9 @@ static enum drm_mode_status vop_crtc_mode_valid(struct drm_crtc *crtc, - if (!vop_crtc_is_tmds(crtc)) - return MODE_OK; - -+ if (mode->flags & DRM_MODE_FLAG_INTERLACE) -+ return MODE_NO_INTERLACE; -+ - rounded_rate = clk_round_rate(vop->dclk, mode->clock * 1000 + 999); - if (rounded_rate < 0) - return MODE_NOCLOCK; - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Jonas Karlman -Date: Mon, 20 Jul 2020 11:46:16 +0000 -Subject: [PATCH] drm/rockchip: vop: filter modes above max output supported - -Filter any mode with a resolution not supported by the VOP. - -Signed-off-by: Jonas Karlman -Signed-off-by: Alex Bee ---- - drivers/gpu/drm/rockchip/rockchip_drm_vop.c | 48 +++++++++++++++------ - 1 file changed, 34 insertions(+), 14 deletions(-) - -diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c -index 9f7326c5b1f5..30e252ba7184 100644 ---- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c -+++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c -@@ -1228,6 +1228,24 @@ static bool vop_crtc_is_tmds(struct drm_crtc *crtc) - return false; - } - -+static enum drm_mode_status vop_crtc_size_valid(struct drm_crtc *crtc, -+ const struct drm_display_mode *mode) -+{ -+ struct vop *vop = to_vop(crtc); -+ const struct vop_rect *max_output = &vop->data->max_output; -+ -+ if (max_output->width && max_output->height) { -+ /* only the size of the resulting rect matters */ -+ if(drm_mode_validate_size(mode, max_output->width, -+ max_output->height) != MODE_OK) { -+ return drm_mode_validate_size(mode, max_output->height, -+ max_output->width); -+ } -+ } -+ -+ return MODE_OK; -+} -+ - /* - * The VESA DMT standard specifies a 0.5% pixel clock frequency tolerance. - * The CVT spec reuses that tolerance in its examples. -@@ -1241,25 +1259,24 @@ static enum drm_mode_status vop_crtc_mode_valid(struct drm_crtc *crtc, - long rounded_rate; - long lowest, highest; - -- if (!vop_crtc_is_tmds(crtc)) -- return MODE_OK; -- - if (mode->flags & DRM_MODE_FLAG_INTERLACE) -- return MODE_NO_INTERLACE; -+ return MODE_NO_INTERLACE; - -- rounded_rate = clk_round_rate(vop->dclk, mode->clock * 1000 + 999); -- if (rounded_rate < 0) -- return MODE_NOCLOCK; -+ if (vop_crtc_is_tmds(crtc)) { -+ rounded_rate = clk_round_rate(vop->dclk, mode->clock * 1000 + 999); -+ if (rounded_rate < 0) -+ return MODE_NOCLOCK; - -- lowest = mode->clock * (1000 - CLOCK_TOLERANCE_PER_MILLE); -- if (rounded_rate < lowest) -- return MODE_CLOCK_LOW; -+ lowest = mode->clock * (1000 - CLOCK_TOLERANCE_PER_MILLE); -+ if (rounded_rate < lowest) -+ return MODE_CLOCK_LOW; - -- highest = mode->clock * (1000 + CLOCK_TOLERANCE_PER_MILLE); -- if (rounded_rate > highest) -- return MODE_CLOCK_HIGH; -+ highest = mode->clock * (1000 + CLOCK_TOLERANCE_PER_MILLE); -+ if (rounded_rate > highest) -+ return MODE_CLOCK_HIGH; -+ } - -- return MODE_OK; -+ return vop_crtc_size_valid(crtc, mode); - } - - static bool vop_crtc_mode_fixup(struct drm_crtc *crtc, -@@ -1269,6 +1286,9 @@ static bool vop_crtc_mode_fixup(struct drm_crtc *crtc, - struct vop *vop = to_vop(crtc); - unsigned long rate; - -+ if (vop_crtc_size_valid(crtc, adjusted_mode) != MODE_OK) -+ return false; -+ - /* - * Clock craziness. - * - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Yakir Yang -Date: Mon, 11 Jul 2016 19:05:39 +0800 -Subject: [PATCH] drm/rockchip: dw_hdmi: adjust cklvl & txlvl for RF/EMI - -Dut to the high HDMI signal voltage driver, Mickey have meet -a serious RF/EMI problem, so we decided to reduce HDMI signal -voltage to a proper value. - -The default params for phy is cklvl = 20 & txlvl = 13 (RF/EMI failed) - ck: lvl = 13, term=100, vlo = 2.71, vhi=3.14, vswing = 0.43 - tx: lvl = 20, term=100, vlo = 2.81, vhi=3.16, vswing = 0.35 - -1. We decided to reduce voltage value to lower, but VSwing still -keep high, RF/EMI have been improved but still failed. - ck: lvl = 6, term=100, vlo = 2.61, vhi=3.11, vswing = 0.50 - tx: lvl = 6, term=100, vlo = 2.61, vhi=3.11, vswing = 0.50 - -2. We try to keep voltage value and vswing both lower, then RF/EMI -test all passed ;) - ck: lvl = 11, term= 66, vlo = 2.68, vhi=3.09, vswing = 0.40 - tx: lvl = 11, term= 66, vlo = 2.68, vhi=3.09, vswing = 0.40 -When we back to run HDMI different test and single-end test, we see -different test passed, but signle-end test failed. The oscilloscope -show that simgle-end clock's VL value is 1.78v (which remind LowLimit -should not lower then 2.6v). - -3. That's to say there are some different between PHY document and -measure value. And according to experiment 2 results, we need to -higher clock voltage and lower data voltage, then we can keep RF/EMI -satisfied and single-end & differen test passed. - ck: lvl = 9, term=100, vlo = 2.65, vhi=3.12, vswing = 0.47 - tx: lvl = 16, term=100, vlo = 2.75, vhi=3.15, vswing = 0.39 - -Signed-off-by: Yakir Yang -Signed-off-by: Jonas Karlman ---- - drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - -diff --git a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c -index c14f88893868..4411ca8fd7ed 100644 ---- a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c -+++ b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c -@@ -193,7 +193,7 @@ static const struct dw_hdmi_curr_ctrl rockchip_cur_ctr[] = { - static const struct dw_hdmi_phy_config rockchip_phy_config[] = { - /*pixelclk symbol term vlev*/ - { 74250000, 0x8009, 0x0004, 0x0272}, -- { 148500000, 0x802b, 0x0004, 0x028d}, -+ { 165000000, 0x802b, 0x0004, 0x0209}, - { 297000000, 0x8039, 0x0005, 0x028d}, - { ~0UL, 0x0000, 0x0000, 0x0000} - }; - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Nickey Yang -Date: Mon, 13 Feb 2017 15:40:29 +0800 -Subject: [PATCH] drm/rockchip: dw_hdmi: add phy_config for 594Mhz pixel clock - -Add phy_config for 594Mhz pixel clock used for 4K@60hz - -Signed-off-by: Nickey Yang -Signed-off-by: Jonas Karlman ---- - drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c | 1 + - 1 file changed, 1 insertion(+) - -diff --git a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c -index 4411ca8fd7ed..bec381cde0bc 100644 ---- a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c -+++ b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c -@@ -195,6 +195,7 @@ static const struct dw_hdmi_phy_config rockchip_phy_config[] = { - { 74250000, 0x8009, 0x0004, 0x0272}, - { 165000000, 0x802b, 0x0004, 0x0209}, - { 297000000, 0x8039, 0x0005, 0x028d}, -+ { 594000000, 0x8039, 0x0000, 0x019d}, - { ~0UL, 0x0000, 0x0000, 0x0000} - }; - - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Douglas Anderson -Date: Mon, 11 Jul 2016 19:05:36 +0800 -Subject: [PATCH] drm/rockchip: dw_hdmi: Set cur_ctr to 0 always - -Jitter was improved by lowering the MPLL bandwidth to account for high -frequency noise in the rk3288 PLL. In each case MPLL bandwidth was -lowered only enough to get us a comfortable margin. We believe that -lowering the bandwidth like this is safe given sufficient testing. - -Signed-off-by: Douglas Anderson -Signed-off-by: Yakir Yang -Signed-off-by: Jonas Karlman ---- - drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c | 16 ++-------------- - 1 file changed, 2 insertions(+), 14 deletions(-) - -diff --git a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c -index bec381cde0bc..72c1d65c7b75 100644 ---- a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c -+++ b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c -@@ -172,20 +172,6 @@ static const struct dw_hdmi_mpll_config rockchip_mpll_cfg[] = { - static const struct dw_hdmi_curr_ctrl rockchip_cur_ctr[] = { - /* pixelclk bpp8 bpp10 bpp12 */ - { -- 40000000, { 0x0018, 0x0018, 0x0018 }, -- }, { -- 65000000, { 0x0028, 0x0028, 0x0028 }, -- }, { -- 66000000, { 0x0038, 0x0038, 0x0038 }, -- }, { -- 74250000, { 0x0028, 0x0038, 0x0038 }, -- }, { -- 83500000, { 0x0028, 0x0038, 0x0038 }, -- }, { -- 146250000, { 0x0038, 0x0038, 0x0038 }, -- }, { -- 148500000, { 0x0000, 0x0038, 0x0038 }, -- }, { - 600000000, { 0x0000, 0x0000, 0x0000 }, - }, { - ~0UL, { 0x0000, 0x0000, 0x0000}, - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Douglas Anderson -Date: Mon, 11 Jul 2016 19:05:42 +0800 -Subject: [PATCH] drm/rockchip: dw_hdmi: Use auto-generated tables - -The previous tables for mpll_cfg and curr_ctrl were created using the -20-pages of example settings provided by the PHY vendor. Those -example settings weren't particularly dense, so there were places -where we were guessing what the settings would be for 10-bit and -12-bit (not that we use those anyway). It was also always a lot of -extra work every time we wanted to add a new clock rate since we had -to cross-reference several tables. - -In I've gone through the work to figure -out how to generate this table automatically. Let's now use the -automatically generated table and then we'll never need to look at it -again. - -We only support 8-bit mode right now and only support a small number -of clock rates and and I've verified that the only 8-bit rate that was -affected was 148.5. That mode appears to have been wrong in the old -table. - -Signed-off-by: Douglas Anderson -Signed-off-by: Yakir Yang -Signed-off-by: Jonas Karlman ---- - drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c | 130 +++++++++++--------- - 1 file changed, 69 insertions(+), 61 deletions(-) - -diff --git a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c -index 72c1d65c7b75..0370bb247fcb 100644 ---- a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c -+++ b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c -@@ -95,86 +95,88 @@ - - static const struct dw_hdmi_mpll_config rockchip_mpll_cfg[] = { - { -- 27000000, { -- { 0x00b3, 0x0000}, -- { 0x2153, 0x0000}, -- { 0x40f3, 0x0000} -- }, -- }, { -- 36000000, { -- { 0x00b3, 0x0000}, -- { 0x2153, 0x0000}, -- { 0x40f3, 0x0000} -- }, -- }, { -- 40000000, { -- { 0x00b3, 0x0000}, -- { 0x2153, 0x0000}, -- { 0x40f3, 0x0000} -- }, -- }, { -- 54000000, { -- { 0x0072, 0x0001}, -- { 0x2142, 0x0001}, -- { 0x40a2, 0x0001}, -- }, -- }, { -- 65000000, { -- { 0x0072, 0x0001}, -- { 0x2142, 0x0001}, -- { 0x40a2, 0x0001}, -- }, -- }, { -- 66000000, { -- { 0x013e, 0x0003}, -- { 0x217e, 0x0002}, -- { 0x4061, 0x0002} -- }, -- }, { -- 74250000, { -- { 0x0072, 0x0001}, -- { 0x2145, 0x0002}, -- { 0x4061, 0x0002} -- }, -- }, { -- 83500000, { -- { 0x0072, 0x0001}, -- }, -- }, { -- 108000000, { -- { 0x0051, 0x0002}, -- { 0x2145, 0x0002}, -- { 0x4061, 0x0002} -- }, -- }, { -- 106500000, { -- { 0x0051, 0x0002}, -- { 0x2145, 0x0002}, -- { 0x4061, 0x0002} -- }, -- }, { -- 146250000, { -- { 0x0051, 0x0002}, -- { 0x2145, 0x0002}, -- { 0x4061, 0x0002} -- }, -- }, { -- 148500000, { -- { 0x0051, 0x0003}, -- { 0x214c, 0x0003}, -- { 0x4064, 0x0003} -+ 30666000, { -+ { 0x00b3, 0x0000 }, -+ { 0x2153, 0x0000 }, -+ { 0x40f3, 0x0000 }, -+ }, -+ }, { -+ 36800000, { -+ { 0x00b3, 0x0000 }, -+ { 0x2153, 0x0000 }, -+ { 0x40a2, 0x0001 }, -+ }, -+ }, { -+ 46000000, { -+ { 0x00b3, 0x0000 }, -+ { 0x2142, 0x0001 }, -+ { 0x40a2, 0x0001 }, -+ }, -+ }, { -+ 61333000, { -+ { 0x0072, 0x0001 }, -+ { 0x2142, 0x0001 }, -+ { 0x40a2, 0x0001 }, -+ }, -+ }, { -+ 73600000, { -+ { 0x0072, 0x0001 }, -+ { 0x2142, 0x0001 }, -+ { 0x4061, 0x0002 }, -+ }, -+ }, { -+ 92000000, { -+ { 0x0072, 0x0001 }, -+ { 0x2145, 0x0002 }, -+ { 0x4061, 0x0002 }, -+ }, -+ }, { -+ 122666000, { -+ { 0x0051, 0x0002 }, -+ { 0x2145, 0x0002 }, -+ { 0x4061, 0x0002 }, -+ }, -+ }, { -+ 147200000, { -+ { 0x0051, 0x0002 }, -+ { 0x2145, 0x0002 }, -+ { 0x4064, 0x0003 }, -+ }, -+ }, { -+ 184000000, { -+ { 0x0051, 0x0002 }, -+ { 0x214c, 0x0003 }, -+ { 0x4064, 0x0003 }, - }, -- }, { -+ }, { -+ 226666000, { -+ { 0x0040, 0x0003 }, -+ { 0x214c, 0x0003 }, -+ { 0x4064, 0x0003 }, -+ }, -+ }, { -+ 272000000, { -+ { 0x0040, 0x0003 }, -+ { 0x214c, 0x0003 }, -+ { 0x5a64, 0x0003 }, -+ }, -+ }, { - 340000000, { - { 0x0040, 0x0003 }, - { 0x3b4c, 0x0003 }, - { 0x5a64, 0x0003 }, - }, -- }, { -+ }, { -+ 600000000, { -+ { 0x1a40, 0x0003 }, -+ { 0x3b4c, 0x0003 }, -+ { 0x5a64, 0x0003 }, -+ }, -+ }, { - ~0UL, { -- { 0x00a0, 0x000a }, -- { 0x2001, 0x000f }, -- { 0x4002, 0x000f }, -+ { 0x0000, 0x0000 }, -+ { 0x0000, 0x0000 }, -+ { 0x0000, 0x0000 }, - }, - } - }; - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Jonas Karlman -Date: Wed, 8 Jan 2020 21:07:49 +0000 -Subject: [PATCH] drm/rockchip: dw-hdmi: allow high tmds bit rates - -Prepare support for High TMDS Bit Rates used by HDMI2.0 display modes. - -Signed-off-by: Jonas Karlman ---- - drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c | 2 ++ - 1 file changed, 2 insertions(+) - -diff --git a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c -index 55c0b8dddad5..15ecb257b902 100644 ---- a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c -+++ b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c -@@ -327,6 +327,8 @@ static int dw_hdmi_rockchip_genphy_init(struct dw_hdmi *dw_hdmi, void *data, - { - struct rockchip_hdmi *hdmi = (struct rockchip_hdmi *)data; - -+ dw_hdmi_set_high_tmds_clock_ratio(dw_hdmi, display); -+ - return phy_power_on(hdmi->phy); - } - - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Jonas Karlman -Date: Wed, 8 Jan 2020 21:07:52 +0000 -Subject: [PATCH] drm/rockchip: dw-hdmi: remove unused plat_data on - rk3228/rk3328 - -mpll_cfg/cur_ctr/phy_config is not used when phy_force_vendor is true, -lets remove them. - -Signed-off-by: Jonas Karlman ---- - drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c | 6 ------ - 1 file changed, 6 deletions(-) - -diff --git a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c -index 15ecb257b902..38dded2baaf7 100644 ---- a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c -+++ b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c -@@ -417,9 +417,6 @@ static struct rockchip_hdmi_chip_data rk3228_chip_data = { - - static const struct dw_hdmi_plat_data rk3228_hdmi_drv_data = { - .mode_valid = dw_hdmi_rockchip_mode_valid, -- .mpll_cfg = rockchip_mpll_cfg, -- .cur_ctr = rockchip_cur_ctr, -- .phy_config = rockchip_phy_config, - .phy_data = &rk3228_chip_data, - .phy_ops = &rk3228_hdmi_phy_ops, - .phy_name = "inno_dw_hdmi_phy2", -@@ -454,9 +451,6 @@ static struct rockchip_hdmi_chip_data rk3328_chip_data = { - - static const struct dw_hdmi_plat_data rk3328_hdmi_drv_data = { - .mode_valid = dw_hdmi_rockchip_mode_valid, -- .mpll_cfg = rockchip_mpll_cfg, -- .cur_ctr = rockchip_cur_ctr, -- .phy_config = rockchip_phy_config, - .phy_data = &rk3328_chip_data, - .phy_ops = &rk3328_hdmi_phy_ops, - .phy_name = "inno_dw_hdmi_phy2", - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Jonas Karlman -Date: Sat, 10 Oct 2020 10:16:32 +0000 -Subject: [PATCH] drm/rockchip: dw-hdmi: encoder error handling - -Signed-off-by: Jonas Karlman ---- - drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c | 10 ++++++++-- - 1 file changed, 8 insertions(+), 2 deletions(-) - -diff --git a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c -index 38dded2baaf7..9e460b7e14a4 100644 ---- a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c -+++ b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c -@@ -558,7 +558,7 @@ static int dw_hdmi_rockchip_bind(struct device *dev, struct device *master, - if (IS_ERR(hdmi->phy)) { - ret = PTR_ERR(hdmi->phy); - if (ret != -EPROBE_DEFER) -- DRM_DEV_ERROR(hdmi->dev, "failed to get phy\n"); -+ DRM_DEV_ERROR(hdmi->dev, "Failed to get phy: %d\n", ret); - return ret; - } - -@@ -590,7 +590,12 @@ static int dw_hdmi_rockchip_bind(struct device *dev, struct device *master, - } - - drm_encoder_helper_add(encoder, &dw_hdmi_rockchip_encoder_helper_funcs); -- drm_simple_encoder_init(drm, encoder, DRM_MODE_ENCODER_TMDS); -+ -+ ret = drm_simple_encoder_init(drm, encoder, DRM_MODE_ENCODER_TMDS); -+ if (ret) { -+ DRM_DEV_ERROR(hdmi->dev, "Failed to init encoder: %d\n", ret); -+ goto err_disable_clk; -+ } - - platform_set_drvdata(pdev, hdmi); - -@@ -609,6 +614,7 @@ static int dw_hdmi_rockchip_bind(struct device *dev, struct device *master, - - err_bind: - drm_encoder_cleanup(encoder); -+err_disable_clk: - clk_disable_unprepare(hdmi->ref_clk); - err_clk: - regulator_disable(hdmi->avdd_1v8); - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Jonas Karlman -Date: Sat, 10 Oct 2020 14:32:21 +0000 -Subject: [PATCH] drm/rockchip: vop: split rk3288 vop - -Signed-off-by: Jonas Karlman ---- - drivers/gpu/drm/rockchip/rockchip_vop_reg.c | 21 ++++++++++++++++++--- - 1 file changed, 18 insertions(+), 3 deletions(-) - -diff --git a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c -index 9b25b8ffd0ce..a2b281e290e0 100644 ---- a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c -+++ b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c -@@ -740,7 +740,7 @@ static const struct vop_intr rk3288_vop_intr = { - .clear = VOP_REG(RK3288_INTR_CTRL0, 0xf, 8), - }; - --static const struct vop_data rk3288_vop = { -+static const struct vop_data rk3288_vop_big = { - .version = VOP_VERSION(3, 1), - .feature = VOP_FEATURE_OUTPUT_RGB10, - .max_output = { 3840, 2160 }, -@@ -753,6 +753,19 @@ static const struct vop_data rk3288_vop = { - .lut_size = 1024, - }; - -+static const struct vop_data rk3288_vop_lit = { -+ .version = VOP_VERSION(3, 1), -+ .feature = VOP_FEATURE_OUTPUT_RGB10, -+ .max_output = { 2560, 1600 }, -+ .intr = &rk3288_vop_intr, -+ .common = &rk3288_common, -+ .modeset = &rk3288_modeset, -+ .output = &rk3288_output, -+ .win = rk3288_vop_win_data, -+ .win_size = ARRAY_SIZE(rk3288_vop_win_data), -+ .lut_size = 1024, -+}; -+ - static const int rk3368_vop_intrs[] = { - FS_INTR, - 0, 0, -@@ -1142,8 +1155,10 @@ static const struct of_device_id vop_driver_dt_match[] = { - .data = &rk3066_vop }, - { .compatible = "rockchip,rk3188-vop", - .data = &rk3188_vop }, -- { .compatible = "rockchip,rk3288-vop", -- .data = &rk3288_vop }, -+ { .compatible = "rockchip,rk3288-vop-big", -+ .data = &rk3288_vop_big }, -+ { .compatible = "rockchip,rk3288-vop-lit", -+ .data = &rk3288_vop_lit }, - { .compatible = "rockchip,rk3368-vop", - .data = &rk3368_vop }, - { .compatible = "rockchip,rk3366-vop", - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Jonas Karlman -Date: Sat, 10 Oct 2020 14:33:30 +0000 -Subject: [PATCH] ARM: dts: rockchip: split rk3288 vop - -Signed-off-by: Jonas Karlman ---- - arch/arm/boot/dts/rockchip/rk3288.dtsi | 4 ++-- - 1 file changed, 2 insertions(+), 2 deletions(-) - -diff --git a/arch/arm/boot/dts/rockchip/rk3288.dtsi b/arch/arm/boot/dts/rockchip/rk3288.dtsi -index 487b0e03d4b4..c60eacab8a79 100644 ---- a/arch/arm/boot/dts/rockchip/rk3288.dtsi -+++ b/arch/arm/boot/dts/rockchip/rk3288.dtsi -@@ -1017,7 +1017,7 @@ rga: rga@ff920000 { - }; - - vopb: vop@ff930000 { -- compatible = "rockchip,rk3288-vop"; -+ compatible = "rockchip,rk3288-vop-big"; - reg = <0x0 0xff930000 0x0 0x19c>, <0x0 0xff931000 0x0 0x1000>; - interrupts = ; - clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>; -@@ -1066,7 +1066,7 @@ vopb_mmu: iommu@ff930300 { - }; - - vopl: vop@ff940000 { -- compatible = "rockchip,rk3288-vop"; -+ compatible = "rockchip,rk3288-vop-lit"; - reg = <0x0 0xff940000 0x0 0x19c>, <0x0 0xff941000 0x0 0x1000>; - interrupts = ; - clocks = <&cru ACLK_VOP1>, <&cru DCLK_VOP1>, <&cru HCLK_VOP1>; - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Jonas Karlman -Date: Mon, 20 Jul 2020 18:00:44 +0000 -Subject: [PATCH] drm/bridge: dw-hdmi: add mtmdsclock parameter to phy - configure ops - -Signed-off-by: Jonas Karlman ---- - drivers/gpu/drm/bridge/synopsys/dw-hdmi.c | 10 ++++++---- - drivers/gpu/drm/renesas/rcar-du/rcar_dw_hdmi.c | 3 ++- - include/drm/bridge/dw_hdmi.h | 3 ++- - 3 files changed, 10 insertions(+), 6 deletions(-) - -diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c -index 40d8ca37f5bc..22af42a08980 100644 ---- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c -+++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c -@@ -138,7 +138,8 @@ struct dw_hdmi_phy_data { - bool has_svsret; - int (*configure)(struct dw_hdmi *hdmi, - const struct dw_hdmi_plat_data *pdata, -- unsigned long mpixelclock); -+ unsigned long mpixelclock, -+ unsigned long mtmdsclock); - }; - - struct dw_hdmi { -@@ -1585,7 +1586,8 @@ static int dw_hdmi_phy_power_on(struct dw_hdmi *hdmi) - */ - static int hdmi_phy_configure_dwc_hdmi_3d_tx(struct dw_hdmi *hdmi, - const struct dw_hdmi_plat_data *pdata, -- unsigned long mpixelclock) -+ unsigned long mpixelclock, -+ unsigned long mtmdsclock) - { - const struct dw_hdmi_mpll_config *mpll_config = pdata->mpll_cfg; - const struct dw_hdmi_curr_ctrl *curr_ctrl = pdata->cur_ctr; -@@ -1660,9 +1662,9 @@ static int hdmi_phy_configure(struct dw_hdmi *hdmi, - - /* Write to the PHY as configured by the platform */ - if (pdata->configure_phy) -- ret = pdata->configure_phy(hdmi, pdata->priv_data, mpixelclock); -+ ret = pdata->configure_phy(hdmi, pdata->priv_data, mpixelclock, mtmdsclock); - else -- ret = phy->configure(hdmi, pdata, mpixelclock); -+ ret = phy->configure(hdmi, pdata, mpixelclock, mtmdsclock); - if (ret) { - dev_err(hdmi->dev, "PHY configuration failed (clock %lu)\n", - mpixelclock); -diff --git a/drivers/gpu/drm/renesas/rcar-du/rcar_dw_hdmi.c b/drivers/gpu/drm/renesas/rcar-du/rcar_dw_hdmi.c -index 18ed14911b98..9c75095a25c5 100644 ---- a/drivers/gpu/drm/renesas/rcar-du/rcar_dw_hdmi.c -+++ b/drivers/gpu/drm/renesas/rcar-du/rcar_dw_hdmi.c -@@ -53,7 +53,8 @@ rcar_hdmi_mode_valid(struct dw_hdmi *hdmi, void *data, - } - - static int rcar_hdmi_phy_configure(struct dw_hdmi *hdmi, void *data, -- unsigned long mpixelclock) -+ unsigned long mpixelclock, -+ unsigned long mtmdsclock) - { - const struct rcar_hdmi_phy_params *params = rcar_hdmi_phy_params; - -diff --git a/include/drm/bridge/dw_hdmi.h b/include/drm/bridge/dw_hdmi.h -index f668e75fbabe..48fb72f9614f 100644 ---- a/include/drm/bridge/dw_hdmi.h -+++ b/include/drm/bridge/dw_hdmi.h -@@ -159,7 +159,8 @@ struct dw_hdmi_plat_data { - const struct dw_hdmi_curr_ctrl *cur_ctr; - const struct dw_hdmi_phy_config *phy_config; - int (*configure_phy)(struct dw_hdmi *hdmi, void *data, -- unsigned long mpixelclock); -+ unsigned long mpixelclock, -+ unsigned long mtmdsclock); - - unsigned int disable_cec : 1; - }; - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Jonas Karlman -Date: Mon, 20 Jul 2020 21:34:48 +0000 -Subject: [PATCH] drm/bridge: dw-hdmi: support configuring phy for deep color - -Q: Should we rename dw_hdmi_curr_ctrl and dw_hdmi_phy_config mpixelclock to mtmdsclock ? - -Signed-off-by: Jonas Karlman ---- - drivers/gpu/drm/bridge/synopsys/dw-hdmi.c | 17 ++++++++++++----- - 1 file changed, 12 insertions(+), 5 deletions(-) - -diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c -index 22af42a08980..7fd45a7006b1 100644 ---- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c -+++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c -@@ -1592,6 +1592,7 @@ static int hdmi_phy_configure_dwc_hdmi_3d_tx(struct dw_hdmi *hdmi, - const struct dw_hdmi_mpll_config *mpll_config = pdata->mpll_cfg; - const struct dw_hdmi_curr_ctrl *curr_ctrl = pdata->cur_ctr; - const struct dw_hdmi_phy_config *phy_config = pdata->phy_config; -+ int depth; - - /* TOFIX Will need 420 specific PHY configuration tables */ - -@@ -1601,11 +1602,11 @@ static int hdmi_phy_configure_dwc_hdmi_3d_tx(struct dw_hdmi *hdmi, - break; - - for (; curr_ctrl->mpixelclock != ~0UL; curr_ctrl++) -- if (mpixelclock <= curr_ctrl->mpixelclock) -+ if (mtmdsclock <= curr_ctrl->mpixelclock) - break; - - for (; phy_config->mpixelclock != ~0UL; phy_config++) -- if (mpixelclock <= phy_config->mpixelclock) -+ if (mtmdsclock <= phy_config->mpixelclock) - break; - - if (mpll_config->mpixelclock == ~0UL || -@@ -1613,11 +1614,17 @@ static int hdmi_phy_configure_dwc_hdmi_3d_tx(struct dw_hdmi *hdmi, - phy_config->mpixelclock == ~0UL) - return -EINVAL; - -- dw_hdmi_phy_i2c_write(hdmi, mpll_config->res[0].cpce, -+ depth = hdmi_bus_fmt_color_depth(hdmi->hdmi_data.enc_out_bus_format); -+ if (depth > 8 && mpixelclock != mtmdsclock) -+ depth = fls(depth - 8) - 1; -+ else -+ depth = 0; -+ -+ dw_hdmi_phy_i2c_write(hdmi, mpll_config->res[depth].cpce, - HDMI_3D_TX_PHY_CPCE_CTRL); -- dw_hdmi_phy_i2c_write(hdmi, mpll_config->res[0].gmp, -+ dw_hdmi_phy_i2c_write(hdmi, mpll_config->res[depth].gmp, - HDMI_3D_TX_PHY_GMPCTRL); -- dw_hdmi_phy_i2c_write(hdmi, curr_ctrl->curr[0], -+ dw_hdmi_phy_i2c_write(hdmi, curr_ctrl->curr[depth], - HDMI_3D_TX_PHY_CURRCTRL); - - dw_hdmi_phy_i2c_write(hdmi, 0, HDMI_3D_TX_PHY_PLLPHBYCTRL); - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Jonas Karlman -Date: Mon, 20 Jul 2020 22:25:15 +0000 -Subject: [PATCH] drm/bridge: dw-hdmi: add mpll_cfg_420 for ycbcr420 mode - -Signed-off-by: Jonas Karlman ---- - drivers/gpu/drm/bridge/synopsys/dw-hdmi.c | 4 +++- - include/drm/bridge/dw_hdmi.h | 1 + - 2 files changed, 4 insertions(+), 1 deletion(-) - -diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c -index 7fd45a7006b1..a2d101ebf7a7 100644 ---- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c -+++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c -@@ -1594,7 +1594,9 @@ static int hdmi_phy_configure_dwc_hdmi_3d_tx(struct dw_hdmi *hdmi, - const struct dw_hdmi_phy_config *phy_config = pdata->phy_config; - int depth; - -- /* TOFIX Will need 420 specific PHY configuration tables */ -+ if (hdmi_bus_fmt_is_yuv420(hdmi->hdmi_data.enc_out_bus_format) && -+ pdata->mpll_cfg_420) -+ mpll_config = pdata->mpll_cfg_420; - - /* PLL/MPLL Cfg - always match on final entry */ - for (; mpll_config->mpixelclock != ~0UL; mpll_config++) -diff --git a/include/drm/bridge/dw_hdmi.h b/include/drm/bridge/dw_hdmi.h -index 48fb72f9614f..02554d324b4b 100644 ---- a/include/drm/bridge/dw_hdmi.h -+++ b/include/drm/bridge/dw_hdmi.h -@@ -156,6 +156,7 @@ struct dw_hdmi_plat_data { - - /* Synopsys PHY support */ - const struct dw_hdmi_mpll_config *mpll_cfg; -+ const struct dw_hdmi_mpll_config *mpll_cfg_420; - const struct dw_hdmi_curr_ctrl *cur_ctr; - const struct dw_hdmi_phy_config *phy_config; - int (*configure_phy)(struct dw_hdmi *hdmi, void *data, - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Jonas Karlman -Date: Mon, 20 Jul 2020 22:26:19 +0000 -Subject: [PATCH] drm/rockchip: dw-hdmi: add YCbCr420 mpll cfg for rk3399 - -Signed-off-by: Jonas Karlman ---- - drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c | 41 +++++++++++++++++++++ - 1 file changed, 41 insertions(+) - -diff --git a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c -index d42ac9fa3246..a37565649c13 100644 ---- a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c -+++ b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c -@@ -177,6 +177,46 @@ static const struct dw_hdmi_mpll_config rockchip_mpll_cfg[] = { - } - }; - -+static const struct dw_hdmi_mpll_config rockchip_mpll_cfg_420[] = { -+ { -+ 30666000, { -+ { 0x00b7, 0x0000 }, -+ { 0x2157, 0x0000 }, -+ { 0x40f7, 0x0000 }, -+ }, -+ }, { -+ 92000000, { -+ { 0x00b7, 0x0000 }, -+ { 0x2143, 0x0001 }, -+ { 0x40a3, 0x0001 }, -+ }, -+ }, { -+ 184000000, { -+ { 0x0073, 0x0001 }, -+ { 0x2146, 0x0002 }, -+ { 0x4062, 0x0002 }, -+ }, -+ }, { -+ 340000000, { -+ { 0x0052, 0x0003 }, -+ { 0x214d, 0x0003 }, -+ { 0x4065, 0x0003 }, -+ }, -+ }, { -+ 600000000, { -+ { 0x0041, 0x0003 }, -+ { 0x3b4d, 0x0003 }, -+ { 0x5a65, 0x0003 }, -+ }, -+ }, { -+ ~0UL, { -+ { 0x0000, 0x0000 }, -+ { 0x0000, 0x0000 }, -+ { 0x0000, 0x0000 }, -+ }, -+ } -+}; -+ - static const struct dw_hdmi_curr_ctrl rockchip_cur_ctr[] = { - /* pixelclk bpp8 bpp10 bpp12 */ - { -@@ -474,6 +514,7 @@ static struct rockchip_hdmi_chip_data rk3399_chip_data = { - static const struct dw_hdmi_plat_data rk3399_hdmi_drv_data = { - .mode_valid = dw_hdmi_rockchip_mode_valid, - .mpll_cfg = rockchip_mpll_cfg, -+ .mpll_cfg_420 = rockchip_mpll_cfg_420, - .cur_ctr = rockchip_cur_ctr, - .phy_config = rockchip_phy_config, - .phy_data = &rk3399_chip_data, - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Shunqing Chen -Date: Wed, 15 Jul 2020 15:19:11 +0800 -Subject: [PATCH] drm/rockchip: dw-hdmi: add YCbCr420 mpll cfg for rk3288w - -Signed-off-by: Shunqing Chen -Signed-off-by: Jonas Karlman ---- - drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c | 41 +++++++++++++++++++++ - 1 file changed, 41 insertions(+) - -diff --git a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c -index a37565649c13..66fee351f4a7 100644 ---- a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c -+++ b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c -@@ -217,6 +217,46 @@ static const struct dw_hdmi_mpll_config rockchip_mpll_cfg_420[] = { - } - }; - -+static const struct dw_hdmi_mpll_config rockchip_rk3288w_mpll_cfg_420[] = { -+ { -+ 30666000, { -+ { 0x00b7, 0x0000 }, -+ { 0x2157, 0x0000 }, -+ { 0x40f7, 0x0000 }, -+ }, -+ }, { -+ 92000000, { -+ { 0x00b7, 0x0000 }, -+ { 0x2143, 0x0001 }, -+ { 0x40a3, 0x0001 }, -+ }, -+ }, { -+ 184000000, { -+ { 0x0073, 0x0001 }, -+ { 0x2146, 0x0002 }, -+ { 0x4062, 0x0002 }, -+ }, -+ }, { -+ 340000000, { -+ { 0x0052, 0x0003 }, -+ { 0x214d, 0x0003 }, -+ { 0x4065, 0x0003 }, -+ }, -+ }, { -+ 600000000, { -+ { 0x0040, 0x0003 }, -+ { 0x3b4c, 0x0003 }, -+ { 0x5a65, 0x0003 }, -+ }, -+ }, { -+ ~0UL, { -+ { 0x0000, 0x0000 }, -+ { 0x0000, 0x0000 }, -+ { 0x0000, 0x0000 }, -+ }, -+ } -+}; -+ - static const struct dw_hdmi_curr_ctrl rockchip_cur_ctr[] = { - /* pixelclk bpp8 bpp10 bpp12 */ - { -@@ -479,6 +519,7 @@ static struct rockchip_hdmi_chip_data rk3288_chip_data = { - static const struct dw_hdmi_plat_data rk3288_hdmi_drv_data = { - .mode_valid = dw_hdmi_rockchip_mode_valid, - .mpll_cfg = rockchip_mpll_cfg, -+ .mpll_cfg_420 = rockchip_rk3288w_mpll_cfg_420, - .cur_ctr = rockchip_cur_ctr, - .phy_config = rockchip_phy_config, - .phy_data = &rk3288_chip_data, - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Jonas Karlman -Date: Fri, 20 Dec 2019 08:12:42 +0000 -Subject: [PATCH] drm/rockchip: dw-hdmi: add bridge and switch to - drm_bridge_funcs - -Switch the dw-hdmi driver to drm_bridge_funcs by implementing -a new local bridge, connecting it to the dw-hdmi bridge. - -Also enable bridge format negotiation by implementing -atomic_get_input_bus_fmts and support for 8-bit RGB 4:4:4. - -Signed-off-by: Jonas Karlman ---- - drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c | 118 ++++++++++++++------ - 1 file changed, 81 insertions(+), 37 deletions(-) - -diff --git a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c -index 66fee351f4a7..d6d8f3335813 100644 ---- a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c -+++ b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c -@@ -5,6 +5,7 @@ - - #include - #include -+#include - #include - #include - #include -@@ -72,6 +73,7 @@ struct rockchip_hdmi_chip_data { - struct rockchip_hdmi { - struct device *dev; - struct regmap *regmap; -+ struct drm_bridge bridge; - struct rockchip_encoder encoder; - const struct rockchip_hdmi_chip_data *chip_data; - struct clk *ref_clk; -@@ -82,11 +84,9 @@ struct rockchip_hdmi { - struct phy *phy; - }; - --static struct rockchip_hdmi *to_rockchip_hdmi(struct drm_encoder *encoder) -+static struct rockchip_hdmi *to_rockchip_hdmi(struct drm_bridge *bridge) - { -- struct rockchip_encoder *rkencoder = to_rockchip_encoder(encoder); -- -- return container_of(rkencoder, struct rockchip_hdmi, encoder); -+ return container_of(bridge, struct rockchip_hdmi, bridge); - } - - static const struct dw_hdmi_mpll_config rockchip_mpll_cfg[] = { -@@ -335,31 +335,21 @@ dw_hdmi_rockchip_mode_valid(struct dw_hdmi *hdmi, void *data, - - return MODE_OK; - } -- --static void dw_hdmi_rockchip_encoder_disable(struct drm_encoder *encoder) -+static void -+dw_hdmi_rockchip_bridge_mode_set(struct drm_bridge *bridge, -+ const struct drm_display_mode *mode, -+ const struct drm_display_mode *adjusted_mode) - { --} -+ struct rockchip_hdmi *hdmi = to_rockchip_hdmi(bridge); - --static bool --dw_hdmi_rockchip_encoder_mode_fixup(struct drm_encoder *encoder, -- const struct drm_display_mode *mode, -- struct drm_display_mode *adj_mode) --{ -- return true; -+ clk_set_rate(hdmi->ref_clk, adjusted_mode->clock * 1000); - } - --static void dw_hdmi_rockchip_encoder_mode_set(struct drm_encoder *encoder, -- struct drm_display_mode *mode, -- struct drm_display_mode *adj_mode) -+static void dw_hdmi_rockchip_bridge_enable(struct drm_bridge *bridge) - { -- struct rockchip_hdmi *hdmi = to_rockchip_hdmi(encoder); -+ struct rockchip_hdmi *hdmi = to_rockchip_hdmi(bridge); -+ struct drm_encoder *encoder = bridge->encoder; - -- clk_set_rate(hdmi->ref_clk, adj_mode->clock * 1000); --} -- --static void dw_hdmi_rockchip_encoder_enable(struct drm_encoder *encoder) --{ -- struct rockchip_hdmi *hdmi = to_rockchip_hdmi(encoder); - u32 val; - int ret; - -@@ -387,10 +377,21 @@ static void dw_hdmi_rockchip_encoder_enable(struct drm_encoder *encoder) - ret ? "LIT" : "BIG"); - } - -+static bool is_rgb(u32 format) -+{ -+ switch (format) { -+ case MEDIA_BUS_FMT_RGB888_1X24: -+ return true; -+ default: -+ return false; -+ } -+} -+ - static int --dw_hdmi_rockchip_encoder_atomic_check(struct drm_encoder *encoder, -- struct drm_crtc_state *crtc_state, -- struct drm_connector_state *conn_state) -+dw_hdmi_rockchip_bridge_atomic_check(struct drm_bridge *bridge, -+ struct drm_bridge_state *bridge_state, -+ struct drm_crtc_state *crtc_state, -+ struct drm_connector_state *conn_state) - { - struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc_state); - -@@ -400,12 +401,38 @@ dw_hdmi_rockchip_encoder_atomic_check(struct drm_encoder *encoder, - return 0; - } - --static const struct drm_encoder_helper_funcs dw_hdmi_rockchip_encoder_helper_funcs = { -- .mode_fixup = dw_hdmi_rockchip_encoder_mode_fixup, -- .mode_set = dw_hdmi_rockchip_encoder_mode_set, -- .enable = dw_hdmi_rockchip_encoder_enable, -- .disable = dw_hdmi_rockchip_encoder_disable, -- .atomic_check = dw_hdmi_rockchip_encoder_atomic_check, -+static u32 *dw_hdmi_rockchip_get_input_bus_fmts(struct drm_bridge *bridge, -+ struct drm_bridge_state *bridge_state, -+ struct drm_crtc_state *crtc_state, -+ struct drm_connector_state *conn_state, -+ u32 output_fmt, -+ unsigned int *num_input_fmts) -+{ -+ u32 *input_fmt; -+ -+ *num_input_fmts = 0; -+ -+ if (!is_rgb(output_fmt)) -+ return NULL; -+ -+ input_fmt = kzalloc(sizeof(*input_fmt), GFP_KERNEL); -+ if (!input_fmt) -+ return NULL; -+ -+ *num_input_fmts = 1; -+ *input_fmt = output_fmt; -+ -+ return input_fmt; -+} -+ -+static const struct drm_bridge_funcs dw_hdmi_rockchip_bridge_funcs = { -+ .mode_set = dw_hdmi_rockchip_bridge_mode_set, -+ .enable = dw_hdmi_rockchip_bridge_enable, -+ .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state, -+ .atomic_destroy_state = drm_atomic_helper_bridge_destroy_state, -+ .atomic_get_input_bus_fmts = dw_hdmi_rockchip_get_input_bus_fmts, -+ .atomic_check = dw_hdmi_rockchip_bridge_atomic_check, -+ .atomic_reset = drm_atomic_helper_bridge_reset, - }; - - static int dw_hdmi_rockchip_genphy_init(struct dw_hdmi *dw_hdmi, void *data, -@@ -602,6 +629,7 @@ static int dw_hdmi_rockchip_bind(struct device *dev, struct device *master, - struct dw_hdmi_plat_data *plat_data; - const struct of_device_id *match; - struct drm_device *drm = data; -+ struct drm_bridge *next_bridge; - struct drm_encoder *encoder; - struct rockchip_hdmi *hdmi; - int ret; -@@ -679,20 +707,21 @@ static int dw_hdmi_rockchip_bind(struct device *dev, struct device *master, - RK3568_HDMI_SCLIN_MSK)); - } - -- drm_encoder_helper_add(encoder, &dw_hdmi_rockchip_encoder_helper_funcs); -- - ret = drm_simple_encoder_init(drm, encoder, DRM_MODE_ENCODER_TMDS); - if (ret) { - DRM_DEV_ERROR(hdmi->dev, "Failed to init encoder: %d\n", ret); - goto err_disable_clk; - } - -+ hdmi->bridge.funcs = &dw_hdmi_rockchip_bridge_funcs; -+ drm_bridge_attach(encoder, &hdmi->bridge, NULL, 0); -+ - platform_set_drvdata(pdev, hdmi); - -- hdmi->hdmi = dw_hdmi_bind(pdev, encoder, plat_data); -+ hdmi->hdmi = dw_hdmi_probe(pdev, plat_data); - - /* -- * If dw_hdmi_bind() fails we'll never call dw_hdmi_unbind(), -+ * If dw_hdmi_probe() fails we'll never call dw_hdmi_unbind(), - * which would have called the encoder cleanup. Do it manually. - */ - if (IS_ERR(hdmi->hdmi)) { -@@ -700,8 +729,23 @@ static int dw_hdmi_rockchip_bind(struct device *dev, struct device *master, - goto err_bind; - } - -+ next_bridge = of_drm_find_bridge(pdev->dev.of_node); -+ if (!next_bridge) { -+ ret = -EPROBE_DEFER; -+ goto err_dw_hdmi_remove; -+ } -+ -+ ret = drm_bridge_attach(encoder, next_bridge, &hdmi->bridge, 0); -+ if (ret) { -+ if (ret != -EPROBE_DEFER) -+ DRM_DEV_ERROR(hdmi->dev, "Failed to attach dw-hdmi bridge: %d\n", ret); -+ goto err_dw_hdmi_remove; -+ } -+ - return 0; - -+err_dw_hdmi_remove: -+ dw_hdmi_remove(hdmi->hdmi); - err_bind: - drm_encoder_cleanup(encoder); - err_disable_clk: -@@ -719,7 +763,7 @@ static void dw_hdmi_rockchip_unbind(struct device *dev, struct device *master, - { - struct rockchip_hdmi *hdmi = dev_get_drvdata(dev); - -- dw_hdmi_unbind(hdmi->hdmi); -+ dw_hdmi_remove(hdmi->hdmi); - drm_encoder_cleanup(&hdmi->encoder.encoder); - clk_disable_unprepare(hdmi->ref_clk); - - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Jonas Karlman -Date: Fri, 9 Oct 2020 15:29:27 +0000 -Subject: [PATCH] drm/rockchip: vop: add immutable zpos property - -Signed-off-by: Jonas Karlman ---- - drivers/gpu/drm/rockchip/rockchip_drm_fb.c | 2 ++ - drivers/gpu/drm/rockchip/rockchip_drm_vop.c | 6 ++++-- - 2 files changed, 6 insertions(+), 2 deletions(-) - -diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_fb.c b/drivers/gpu/drm/rockchip/rockchip_drm_fb.c -index 092bf863110b..e2ee0d6a8d55 100644 ---- a/drivers/gpu/drm/rockchip/rockchip_drm_fb.c -+++ b/drivers/gpu/drm/rockchip/rockchip_drm_fb.c -@@ -133,6 +133,8 @@ void rockchip_drm_mode_config_init(struct drm_device *dev) - dev->mode_config.max_width = 4096; - dev->mode_config.max_height = 4096; - -+ dev->mode_config.normalize_zpos = true; -+ - dev->mode_config.funcs = &rockchip_drm_mode_config_funcs; - dev->mode_config.helper_private = &rockchip_mode_config_helpers; - -diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c -index 30e252ba7184..897f7980ee5d 100644 ---- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c -+++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c -@@ -1917,7 +1917,7 @@ static irqreturn_t vop_isr(int irq, void *data) - return ret; - } - --static void vop_plane_add_properties(struct drm_plane *plane, -+static void vop_plane_add_properties(struct drm_plane *plane, int zpos, - const struct vop_win_data *win_data) - { - unsigned int flags = 0; -@@ -1927,6 +1927,8 @@ static void vop_plane_add_properties(struct drm_plane *plane, - if (flags) - drm_plane_create_rotation_property(plane, DRM_MODE_ROTATE_0, - DRM_MODE_ROTATE_0 | flags); -+ -+ drm_plane_create_zpos_immutable_property(plane, zpos); - } - - static int vop_create_crtc(struct vop *vop) -@@ -1967,7 +1969,7 @@ static int vop_create_crtc(struct vop *vop) - - plane = &vop_win->base; - drm_plane_helper_add(plane, &plane_helper_funcs); -- vop_plane_add_properties(plane, win_data); -+ vop_plane_add_properties(plane, i, win_data); - if (plane->type == DRM_PLANE_TYPE_PRIMARY) - primary = plane; - else if (plane->type == DRM_PLANE_TYPE_CURSOR) - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Jonas Karlman -Date: Sat, 10 Oct 2020 09:20:44 +0000 -Subject: [PATCH] drm/rockchip: vop: add plane color properties - -Signed-off-by: Jonas Karlman ---- - drivers/gpu/drm/rockchip/rockchip_drm_vop.c | 32 +++++++++++++++++++-- - 1 file changed, 30 insertions(+), 2 deletions(-) - -diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c -index 897f7980ee5d..eadf1b0f1704 100644 ---- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c -+++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c -@@ -1917,8 +1917,23 @@ static irqreturn_t vop_isr(int irq, void *data) - return ret; - } - -+static bool plane_supports_yuv_format(const struct drm_plane *plane) -+{ -+ const struct drm_format_info *info; -+ int i; -+ -+ for (i = 0; i < plane->format_count; i++) { -+ info = drm_format_info(plane->format_types[i]); -+ if (info->is_yuv) -+ return true; -+ } -+ -+ return false; -+} -+ - static void vop_plane_add_properties(struct drm_plane *plane, int zpos, -- const struct vop_win_data *win_data) -+ const struct vop_win_data *win_data, -+ const struct vop_data *vop_data) - { - unsigned int flags = 0; - -@@ -1929,6 +1944,19 @@ static void vop_plane_add_properties(struct drm_plane *plane, int zpos, - DRM_MODE_ROTATE_0 | flags); - - drm_plane_create_zpos_immutable_property(plane, zpos); -+ -+ if (!plane_supports_yuv_format(plane)) -+ return; -+ -+ flags = BIT(DRM_COLOR_YCBCR_BT601) | BIT(DRM_COLOR_YCBCR_BT709); -+ if (vop_data->feature & VOP_FEATURE_OUTPUT_RGB10) -+ flags |= BIT(DRM_COLOR_YCBCR_BT2020); -+ -+ drm_plane_create_color_properties(plane, flags, -+ BIT(DRM_COLOR_YCBCR_LIMITED_RANGE) | -+ BIT(DRM_COLOR_YCBCR_FULL_RANGE), -+ DRM_COLOR_YCBCR_BT601, -+ DRM_COLOR_YCBCR_LIMITED_RANGE); - } - - static int vop_create_crtc(struct vop *vop) -@@ -1969,7 +1997,7 @@ static int vop_create_crtc(struct vop *vop) - - plane = &vop_win->base; - drm_plane_helper_add(plane, &plane_helper_funcs); -- vop_plane_add_properties(plane, i, win_data); -+ vop_plane_add_properties(plane, i, win_data, vop_data); - if (plane->type == DRM_PLANE_TYPE_PRIMARY) - primary = plane; - else if (plane->type == DRM_PLANE_TYPE_CURSOR) - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Nickey Yang -Date: Mon, 17 Jul 2017 16:35:34 +0800 -Subject: [PATCH] HACK: clk: rockchip: rk3288: dedicate npll for vopb and hdmi - use - -MINIARM: set npll be used for hdmi only - -Signed-off-by: Nickey Yang -Signed-off-by: Jonas Karlman -Signed-off-by: Alex Bee ---- - arch/arm/boot/dts/rockchip/rk3288.dtsi | 2 ++ - drivers/clk/rockchip/clk-rk3288.c | 9 +++++---- - 2 files changed, 7 insertions(+), 4 deletions(-) - -diff --git a/arch/arm/boot/dts/rockchip/rk3288.dtsi b/arch/arm/boot/dts/rockchip/rk3288.dtsi -index c60eacab8a79..d1ae42757242 100644 ---- a/arch/arm/boot/dts/rockchip/rk3288.dtsi -+++ b/arch/arm/boot/dts/rockchip/rk3288.dtsi -@@ -1026,6 +1026,8 @@ vopb: vop@ff930000 { - resets = <&cru SRST_LCDC0_AXI>, <&cru SRST_LCDC0_AHB>, <&cru SRST_LCDC0_DCLK>; - reset-names = "axi", "ahb", "dclk"; - iommus = <&vopb_mmu>; -+ assigned-clocks = <&cru DCLK_VOP0>; -+ assigned-clock-parents = <&cru PLL_NPLL>; - status = "disabled"; - - vopb_out: port { -diff --git a/drivers/clk/rockchip/clk-rk3288.c b/drivers/clk/rockchip/clk-rk3288.c -index baa5aebd3277..5cfcbaaa154e 100644 ---- a/drivers/clk/rockchip/clk-rk3288.c -+++ b/drivers/clk/rockchip/clk-rk3288.c -@@ -195,8 +195,9 @@ PNAME(mux_ddrphy_p) = { "dpll_ddr", "gpll_ddr" }; - PNAME(mux_aclk_cpu_src_p) = { "cpll_aclk_cpu", "gpll_aclk_cpu" }; - - PNAME(mux_pll_src_cpll_gpll_p) = { "cpll", "gpll" }; --PNAME(mux_pll_src_npll_cpll_gpll_p) = { "npll", "cpll", "gpll" }; --PNAME(mux_pll_src_cpll_gpll_npll_p) = { "cpll", "gpll", "npll" }; -+PNAME(mux_pll_src_npll_cpll_gpll_p) = { "prevent:npll", "cpll", "gpll" }; -+PNAME(mux_pll_src_cpll_gpll_npll_p) = { "cpll", "gpll", "prevent:npll" }; -+PNAME(vop0_mux_pll_src_cpll_gpll_npll_p) = { "prevent:cpll", "prevent:gpll", "npll" }; - PNAME(mux_pll_src_cpll_gpll_usb480m_p) = { "cpll", "gpll", "unstable:usbphy480m_src" }; - PNAME(mux_pll_src_cpll_gll_usb_npll_p) = { "cpll", "gpll", "unstable:usbphy480m_src", "npll" }; - -@@ -232,7 +233,7 @@ static struct rockchip_pll_clock rk3288_pll_clks[] __initdata = { - [gpll] = PLL(pll_rk3066, PLL_GPLL, "gpll", mux_pll_p, 0, RK3288_PLL_CON(12), - RK3288_MODE_CON, 12, 8, ROCKCHIP_PLL_SYNC_RATE, rk3288_pll_rates), - [npll] = PLL(pll_rk3066, PLL_NPLL, "npll", mux_pll_p, 0, RK3288_PLL_CON(16), -- RK3288_MODE_CON, 14, 9, ROCKCHIP_PLL_SYNC_RATE, rk3288_pll_rates), -+ RK3288_MODE_CON, 14, 9, 0, rk3288_pll_rates), - }; - - static struct clk_div_table div_hclk_cpu_t[] = { -@@ -442,7 +443,7 @@ static struct rockchip_clk_branch rk3288_clk_branches[] __initdata = { - RK3288_CLKSEL_CON(30), 14, 2, MFLAGS, 8, 5, DFLAGS, - RK3288_CLKGATE_CON(3), 4, GFLAGS), - -- COMPOSITE(DCLK_VOP0, "dclk_vop0", mux_pll_src_cpll_gpll_npll_p, 0, -+ COMPOSITE(DCLK_VOP0, "dclk_vop0", vop0_mux_pll_src_cpll_gpll_npll_p, CLK_SET_RATE_NO_REPARENT | CLK_SET_RATE_PARENT, - RK3288_CLKSEL_CON(27), 0, 2, MFLAGS, 8, 8, DFLAGS, - RK3288_CLKGATE_CON(3), 1, GFLAGS), - COMPOSITE(DCLK_VOP1, "dclk_vop1", mux_pll_src_cpll_gpll_npll_p, 0, - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Jonas Karlman -Date: Sat, 4 Aug 2018 14:51:14 +0200 -Subject: [PATCH] HACK: clk: rockchip: rk3288: use npll table to to improve - HDMI compatibility - -Based on https://github.com/TinkerBoard/debian_kernel/commit/3d90870530b8a2901681f7b7fa598ee7381e49f3 - -Signed-off-by: Jonas Karlman -Signed-off-by: Alex Bee ---- - drivers/clk/rockchip/clk-rk3288.c | 39 ++++++++++++++++++++++++++++++- - 1 file changed, 38 insertions(+), 1 deletion(-) - -diff --git a/drivers/clk/rockchip/clk-rk3288.c b/drivers/clk/rockchip/clk-rk3288.c -index 5cfcbaaa154e..fa1c6e646bdf 100644 ---- a/drivers/clk/rockchip/clk-rk3288.c -+++ b/drivers/clk/rockchip/clk-rk3288.c -@@ -121,6 +121,43 @@ static struct rockchip_pll_rate_table rk3288_pll_rates[] = { - { /* sentinel */ }, - }; - -+static struct rockchip_pll_rate_table rk3288_npll_rates[] = { -+ RK3066_PLL_RATE_NB(594000000, 1, 198, 8, 1), -+ RK3066_PLL_RATE_NB(585000000, 6, 585, 4, 32), -+ RK3066_PLL_RATE_NB(432000000, 3, 216, 4, 32), -+ RK3066_PLL_RATE_NB(426000000, 3, 213, 4, 32), -+ RK3066_PLL_RATE_NB(400000000, 1, 100, 6, 32), -+ RK3066_PLL_RATE(348500000, 8, 697, 6), -+ RK3066_PLL_RATE_NB(342000000, 3, 171, 4, 32), -+ RK3066_PLL_RATE_NB(297000000, 2, 198, 8, 16), -+ RK3066_PLL_RATE_NB(270000000, 1, 135, 12, 32), -+ RK3066_PLL_RATE_NB(260000000, 1, 130, 12, 32), -+ RK3066_PLL_RATE(241500000, 2, 161, 8), -+ RK3066_PLL_RATE(162000000, 1, 81, 12), -+ RK3066_PLL_RATE(154000000, 6, 539, 14), -+ RK3066_PLL_RATE_NB(148500000, 1, 99, 16, 32), -+ RK3066_PLL_RATE(148352000, 13, 1125, 14), -+ RK3066_PLL_RATE_NB(146250000, 6, 585, 16, 32), -+ RK3066_PLL_RATE(121750000, 6, 487, 16), -+ RK3066_PLL_RATE(119000000, 3, 238, 16), -+ RK3066_PLL_RATE_NB(108000000, 1, 54, 12, 32), -+ RK3066_PLL_RATE_NB(106500000, 4, 213, 12, 32), -+ RK3066_PLL_RATE(101000000, 3, 202, 16), -+ RK3066_PLL_RATE(88750000, 6, 355, 16), -+ RK3066_PLL_RATE_NB(85500000, 4, 171, 12, 32), -+ RK3066_PLL_RATE(83500000, 3, 167, 16), -+ RK3066_PLL_RATE(79500000, 1, 53, 16), -+ RK3066_PLL_RATE_NB(74250000, 4, 198, 16, 32), -+ RK3066_PLL_RATE(74176000, 26, 1125, 14), -+ RK3066_PLL_RATE(72000000, 1, 48, 16), -+ RK3066_PLL_RATE(71000000, 3, 142, 16), -+ RK3066_PLL_RATE(68250000, 2, 91, 16), -+ RK3066_PLL_RATE(65000000, 3, 130, 16), -+ RK3066_PLL_RATE(40000000, 3, 80, 16), -+ RK3066_PLL_RATE(33750000, 2, 45, 16), -+ { /* sentinel */ }, -+}; -+ - #define RK3288_DIV_ACLK_CORE_M0_MASK 0xf - #define RK3288_DIV_ACLK_CORE_M0_SHIFT 0 - #define RK3288_DIV_ACLK_CORE_MP_MASK 0xf -@@ -233,7 +270,7 @@ static struct rockchip_pll_clock rk3288_pll_clks[] __initdata = { - [gpll] = PLL(pll_rk3066, PLL_GPLL, "gpll", mux_pll_p, 0, RK3288_PLL_CON(12), - RK3288_MODE_CON, 12, 8, ROCKCHIP_PLL_SYNC_RATE, rk3288_pll_rates), - [npll] = PLL(pll_rk3066, PLL_NPLL, "npll", mux_pll_p, 0, RK3288_PLL_CON(16), -- RK3288_MODE_CON, 14, 9, 0, rk3288_pll_rates), -+ RK3288_MODE_CON, 14, 9, 0, rk3288_npll_rates), - }; - - static struct clk_div_table div_hclk_cpu_t[] = { - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Jonas Karlman -Date: Mon, 25 May 2020 20:36:45 +0000 -Subject: [PATCH] HACK: clk: rockchip: rk3399: dedicate vpll for vopb and hdmi - use - -Rockchip PLLs are kown provide the least jitter for -vco rates between 800 MHz and 2 GHz. I added the -rates for VPLL which are used for VOPs dclk and there- -fore HDMI phy in that manner and used the rates which -require the lowest frac divs. -Additionally I added some rates which are useful to -provide additional VESA and non-VESA rates for HDMI -output. - -Signed-off-by: Jonas Karlman -Signed-off-by: Alex Bee ---- - drivers/clk/rockchip/clk-rk3399.c | 49 ++++++++++++++++++++++++++----- - 1 file changed, 42 insertions(+), 7 deletions(-) - -diff --git a/drivers/clk/rockchip/clk-rk3399.c b/drivers/clk/rockchip/clk-rk3399.c -index 306910a3a0d3..436d2789611c 100644 ---- a/drivers/clk/rockchip/clk-rk3399.c -+++ b/drivers/clk/rockchip/clk-rk3399.c -@@ -105,6 +105,39 @@ static struct rockchip_pll_rate_table rk3399_pll_rates[] = { - { /* sentinel */ }, - }; - -+static struct rockchip_pll_rate_table rk3399_vpll_rates[] = { -+ /* _mhz, _refdiv, _fbdiv, _postdiv1, _postdiv2, _dsmpd, _frac */ -+ RK3036_PLL_RATE( 594000000, 1, 74, 3, 1, 0, 4194304), /* vco = 1782000000 fout = 594000000 */ -+ RK3036_PLL_RATE( 593406592, 1, 74, 3, 1, 0, 2949838), /* vco = 1780219777 fout = 593406592.36908 */ -+ RK3036_PLL_RATE( 319750000, 1, 79, 6, 1, 0, 15728640), /* vco = 1918500000 fout = 319750000 */ -+ RK3036_PLL_RATE( 297000000, 1, 74, 6, 1, 0, 4194304), /* vco = 1782000000 fout = 297000000 */ -+ RK3036_PLL_RATE( 296703296, 1, 74, 6, 1, 0, 2949838), /* vco = 1780219777 fout = 296703296.18454 */ -+ RK3036_PLL_RATE( 241500000, 1, 60, 6, 1, 0, 6291456), /* vco = 1449000000 fout = 241500000 */ -+ RK3036_PLL_RATE( 162000000, 1, 67, 5, 2, 0, 8388608), /* vco = 1620000000 fout = 162000000 */ -+ RK3036_PLL_RATE( 148500000, 1, 74, 6, 2, 0, 4194304), /* vco = 1782000000 fout = 148500000*/ -+ RK3036_PLL_RATE( 148351648, 1, 74, 6, 2, 0, 2949838), /* vco = 1780219777 fout = 148351648.09227 */ -+ RK3036_PLL_RATE( 136750000, 1, 68, 2, 6, 0, 6291456), /* vco = 1641000000 fout = 136750000 */ -+ RK3036_PLL_RATE( 135000000, 1, 56, 5, 2, 0, 4194304), /* vco = 1350000000 fout = 135000000 */ -+ RK3036_PLL_RATE( 119000000, 1, 59, 6, 2, 0, 8388608), /* vco = 1428000000 fout = 119000000 */ -+ RK3036_PLL_RATE( 108000000, 1, 63, 7, 2, 1, 0), /* vco = 1512000000 fout = 108000000 */ -+ RK3036_PLL_RATE( 106500000, 1, 62, 7, 2, 0, 2097152), /* vco = 1491000000 fout = 106500000 */ -+ RK3036_PLL_RATE( 88750000, 1, 55, 5, 3, 0, 7864320), /* vco = 1331250000 fout = 88750000 */ -+ RK3036_PLL_RATE( 85500000, 1, 57, 4, 4, 1, 0), /* vco = 1368000000 fout = 85500000 */ -+ RK3036_PLL_RATE( 78750000, 1, 59, 6, 3, 0, 1048576), /* vco = 1417500000 fout = 78750000 */ -+ RK3036_PLL_RATE( 74250000, 1, 74, 6, 4, 0, 4194304), /* vco = 1782000000 fout = 74250000 */ -+ RK3036_PLL_RATE( 74175824, 1, 74, 6, 4, 0, 2949838), /* vco = 1780219777 fout = 74175824.046135 */ -+ RK3036_PLL_RATE( 71000000, 1, 71, 6, 4, 1, 0), /* vco = 1704000000 fout = 71000000 */ -+ RK3036_PLL_RATE( 65000000, 1, 65, 6, 4, 0, 0), /* vco = 1560000000 fout = 65000000 */ -+ RK3036_PLL_RATE( 59340659, 1, 59, 6, 4, 0, 5715310), /* vco = 1424175816 fout = 59340659.022331 */ -+ RK3036_PLL_RATE( 54000000, 1, 63, 7, 4, 1, 0), /* vco = 1512000000 fout = 54000000 */ -+ RK3036_PLL_RATE( 49500000, 1, 72, 5, 7, 0, 3145728), /* vco = 1732500000 fout = 49500000 */ -+ RK3036_PLL_RATE( 40000000, 1, 70, 7, 6, 1, 0), /* vco = 1680000000 fout = 40000000 */ -+ RK3036_PLL_RATE( 31500000, 1, 55, 7, 6, 0, 2097152), /* vco = 1323000000 fout = 31500000 */ -+ RK3036_PLL_RATE( 27000000, 1, 55, 7, 7, 0, 2097152), /* vco = 1323000000 fout = 27000000 */ -+ RK3036_PLL_RATE( 26973026, 1, 55, 7, 7, 0, 1173214), /* vco = 1321678296 fout = 26973026.450799 */ -+ { /* sentinel */ }, -+}; -+ - /* CRU parents */ - PNAME(mux_pll_p) = { "xin24m", "xin32k" }; - -@@ -123,7 +156,7 @@ PNAME(mux_ddrclk_p) = { "clk_ddrc_lpll_src", - PNAME(mux_aclk_cci_p) = { "cpll_aclk_cci_src", - "gpll_aclk_cci_src", - "npll_aclk_cci_src", -- "vpll_aclk_cci_src" }; -+ "prevent:vpll" }; - PNAME(mux_cci_trace_p) = { "cpll_cci_trace", - "gpll_cci_trace" }; - PNAME(mux_cs_p) = { "cpll_cs", "gpll_cs", -@@ -149,10 +182,12 @@ PNAME(mux_pll_src_cpll_gpll_npll_upll_24m_p) = { "cpll", "gpll", "npll", - PNAME(mux_pll_src_cpll_gpll_npll_ppll_upll_24m_p) = { "cpll", "gpll", "npll", - "ppll", "upll", "xin24m" }; - --PNAME(mux_pll_src_vpll_cpll_gpll_p) = { "vpll", "cpll", "gpll" }; --PNAME(mux_pll_src_vpll_cpll_gpll_npll_p) = { "vpll", "cpll", "gpll", -+PNAME(mux_pll_src_vpll_cpll_gpll_p) = { "prevent:vpll", "cpll", "gpll" }; -+PNAME(vop0_mux_pll_src_vpll_cpll_gpll_p) = { "vpll", "prevent:cpll", "prevent:gpll" }; -+ -+PNAME(mux_pll_src_vpll_cpll_gpll_npll_p) = { "prevent:vpll", "cpll", "gpll", - "npll" }; --PNAME(mux_pll_src_vpll_cpll_gpll_24m_p) = { "vpll", "cpll", "gpll", -+PNAME(mux_pll_src_vpll_cpll_gpll_24m_p) = { "prevent:vpll", "cpll", "gpll", - "xin24m" }; - - PNAME(mux_dclk_vop0_p) = { "dclk_vop0_div", -@@ -229,7 +264,7 @@ static struct rockchip_pll_clock rk3399_pll_clks[] __initdata = { - [npll] = PLL(pll_rk3399, PLL_NPLL, "npll", mux_pll_p, 0, RK3399_PLL_CON(40), - RK3399_PLL_CON(43), 8, 31, ROCKCHIP_PLL_SYNC_RATE, rk3399_pll_rates), - [vpll] = PLL(pll_rk3399, PLL_VPLL, "vpll", mux_pll_p, 0, RK3399_PLL_CON(48), -- RK3399_PLL_CON(51), 8, 31, ROCKCHIP_PLL_SYNC_RATE, rk3399_pll_rates), -+ RK3399_PLL_CON(51), 8, 31, ROCKCHIP_PLL_SYNC_RATE, rk3399_vpll_rates), - }; - - static struct rockchip_pll_clock rk3399_pmu_pll_clks[] __initdata = { -@@ -279,7 +314,7 @@ static struct rockchip_clk_branch rk3399_uart4_pmu_fracmux __initdata = - RK3399_PMU_CLKSEL_CON(5), 8, 2, MFLAGS); - - static struct rockchip_clk_branch rk3399_dclk_vop0_fracmux __initdata = -- MUX(DCLK_VOP0, "dclk_vop0", mux_dclk_vop0_p, CLK_SET_RATE_PARENT, -+ MUX(DCLK_VOP0, "dclk_vop0", mux_dclk_vop0_p, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, - RK3399_CLKSEL_CON(49), 11, 1, MFLAGS); - - static struct rockchip_clk_branch rk3399_dclk_vop1_fracmux __initdata = -@@ -1162,7 +1197,7 @@ static struct rockchip_clk_branch rk3399_clk_branches[] __initdata = { - GATE(HCLK_VOP0_NOC, "hclk_vop0_noc", "hclk_vop0_pre", CLK_IGNORE_UNUSED, - RK3399_CLKGATE_CON(28), 0, GFLAGS), - -- COMPOSITE(DCLK_VOP0_DIV, "dclk_vop0_div", mux_pll_src_vpll_cpll_gpll_p, 0, -+ COMPOSITE(DCLK_VOP0_DIV, "dclk_vop0_div", vop0_mux_pll_src_vpll_cpll_gpll_p, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, - RK3399_CLKSEL_CON(49), 8, 2, MFLAGS, 0, 8, DFLAGS, - RK3399_CLKGATE_CON(10), 12, GFLAGS), - - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Jonas Karlman -Date: Sun, 19 Jul 2020 16:35:11 +0000 -Subject: [PATCH] HACK: dts: rockchip: do not use vopl for hdmi - ---- - arch/arm/boot/dts/rockchip/rk3288.dtsi | 9 --------- - arch/arm64/boot/dts/rockchip/rk3399.dtsi | 9 --------- - 2 files changed, 18 deletions(-) - -diff --git a/arch/arm/boot/dts/rockchip/rk3288.dtsi b/arch/arm/boot/dts/rockchip/rk3288.dtsi -index d1ae42757242..7b2cde230b87 100644 ---- a/arch/arm/boot/dts/rockchip/rk3288.dtsi -+++ b/arch/arm/boot/dts/rockchip/rk3288.dtsi -@@ -1090,11 +1090,6 @@ - #address-cells = <1>; - #size-cells = <0>; - -- vopl_out_hdmi: endpoint@0 { -- reg = <0>; -- remote-endpoint = <&hdmi_in_vopl>; -- }; -- - vopl_out_edp: endpoint@1 { - reg = <1>; - remote-endpoint = <&edp_in_vopl>; -@@ -1257,10 +1262,6 @@ - remote-endpoint = <&vopb_out_hdmi>; - }; - -- hdmi_in_vopl: endpoint@1 { -- reg = <1>; -- remote-endpoint = <&vopl_out_hdmi>; -- }; - }; - - hdmi_out: port@1 { -diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi -index 92c2207e686c..980b12cb0a49 100644 ---- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi -+++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi -@@ -1728,11 +1728,6 @@ vopl_out_edp: endpoint@1 { - remote-endpoint = <&edp_in_vopl>; - }; - -- vopl_out_hdmi: endpoint@2 { -- reg = <2>; -- remote-endpoint = <&hdmi_in_vopl>; -- }; -- - vopl_out_mipi1: endpoint@3 { - reg = <3>; - remote-endpoint = <&mipi1_in_vopl>; -@@ -1926,10 +1921,6 @@ hdmi_in_vopb: endpoint@0 { - reg = <0>; - remote-endpoint = <&vopb_out_hdmi>; - }; -- hdmi_in_vopl: endpoint@1 { -- reg = <1>; -- remote-endpoint = <&vopl_out_hdmi>; -- }; - }; - }; - }; - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Jonas Karlman -Date: Fri, 20 Dec 2019 08:12:43 +0000 -Subject: [PATCH] WIP: drm/bridge: dw-hdmi: limit mode and bus format to - max_tmds_clock - ---- - drivers/gpu/drm/bridge/synopsys/dw-hdmi.c | 120 ++++++++++++++-------- - 1 file changed, 76 insertions(+), 44 deletions(-) - -diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c -index a2d101ebf7a7..7f6ffbc3e7b2 100644 ---- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c -+++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c -@@ -2003,6 +2003,21 @@ static void hdmi_config_drm_infoframe(struct dw_hdmi *hdmi, - HDMI_FC_PACKET_TX_EN_DRM_MASK, HDMI_FC_PACKET_TX_EN); - } - -+static unsigned int -+hdmi_get_tmdsclock(unsigned int bus_format, unsigned int pixelclock) -+{ -+ int color_depth = hdmi_bus_fmt_color_depth(bus_format); -+ unsigned int tmdsclock = pixelclock; -+ -+ if (!hdmi_bus_fmt_is_yuv422(bus_format) && color_depth > 8) -+ tmdsclock = (u64)pixelclock * color_depth / 8; -+ -+ if (hdmi_bus_fmt_is_yuv420(bus_format)) -+ tmdsclock /= 2; -+ -+ return tmdsclock; -+} -+ - static void hdmi_av_composer(struct dw_hdmi *hdmi, - const struct drm_display_info *display, - const struct drm_display_mode *mode) -@@ -2014,29 +2029,11 @@ static void hdmi_av_composer(struct dw_hdmi *hdmi, - unsigned int vdisplay, hdisplay; - - vmode->mpixelclock = mode->clock * 1000; -+ vmode->mtmdsclock = -+ hdmi_get_tmdsclock(hdmi->hdmi_data.enc_out_bus_format, -+ vmode->mpixelclock); - - dev_dbg(hdmi->dev, "final pixclk = %d\n", vmode->mpixelclock); -- -- vmode->mtmdsclock = vmode->mpixelclock; -- -- if (!hdmi_bus_fmt_is_yuv422(hdmi->hdmi_data.enc_out_bus_format)) { -- switch (hdmi_bus_fmt_color_depth( -- hdmi->hdmi_data.enc_out_bus_format)) { -- case 16: -- vmode->mtmdsclock = vmode->mpixelclock * 2; -- break; -- case 12: -- vmode->mtmdsclock = vmode->mpixelclock * 3 / 2; -- break; -- case 10: -- vmode->mtmdsclock = vmode->mpixelclock * 5 / 4; -- break; -- } -- } -- -- if (hdmi_bus_fmt_is_yuv420(hdmi->hdmi_data.enc_out_bus_format)) -- vmode->mtmdsclock /= 2; -- - dev_dbg(hdmi->dev, "final tmdsclock = %d\n", vmode->mtmdsclock); - - /* Set up HDMI_FC_INVIDCONF */ -@@ -2663,8 +2660,21 @@ static int dw_hdmi_connector_create(struct dw_hdmi *hdmi) - * - MEDIA_BUS_FMT_RGB888_1X24, - */ - --/* Can return a maximum of 11 possible output formats for a mode/connector */ --#define MAX_OUTPUT_SEL_FORMATS 11 -+/* Can return a maximum of 15 possible output formats for a mode/connector */ -+#define MAX_OUTPUT_SEL_FORMATS 15 -+ -+static bool is_tmds_allowed(struct drm_display_info *info, -+ struct drm_display_mode *mode, -+ u32 bus_format) -+{ -+ unsigned long tmdsclock = hdmi_get_tmdsclock(bus_format, mode->clock); -+ int max_tmds_clock = info->max_tmds_clock ? info->max_tmds_clock : 340000; -+ -+ if (max_tmds_clock >= tmdsclock) -+ return true; -+ -+ return false; -+} - - static u32 *dw_hdmi_bridge_atomic_get_output_bus_fmts(struct drm_bridge *bridge, - struct drm_bridge_state *bridge_state, -@@ -2676,8 +2686,6 @@ static u32 *dw_hdmi_bridge_atomic_get_output_bus_fmts(struct drm_bridge *bridge, - struct drm_display_info *info = &conn->display_info; - struct drm_display_mode *mode = &crtc_state->mode; - u8 max_bpc = conn_state->max_requested_bpc; -- bool is_hdmi2_sink = info->hdmi.scdc.supported || -- (info->color_formats & DRM_COLOR_FORMAT_YCBCR420); - u32 *output_fmts; - unsigned int i = 0; - -@@ -2701,25 +2709,28 @@ static u32 *dw_hdmi_bridge_atomic_get_output_bus_fmts(struct drm_bridge *bridge, - * If the current mode enforces 4:2:0, force the output but format - * to 4:2:0 and do not add the YUV422/444/RGB formats - */ -- if (conn->ycbcr_420_allowed && -- (drm_mode_is_420_only(info, mode) || -- (is_hdmi2_sink && drm_mode_is_420_also(info, mode)))) { -+ if (conn->ycbcr_420_allowed && drm_mode_is_420(info, mode) && -+ (info->color_formats & DRM_COLOR_FORMAT_YCBCR420)) { - - /* Order bus formats from 16bit to 8bit if supported */ - if (max_bpc >= 16 && info->bpc == 16 && -- (info->hdmi.y420_dc_modes & DRM_EDID_YCBCR420_DC_48)) -+ (info->hdmi.y420_dc_modes & DRM_EDID_YCBCR420_DC_48) && -+ is_tmds_allowed(info, mode, MEDIA_BUS_FMT_UYYVYY16_0_5X48)) - output_fmts[i++] = MEDIA_BUS_FMT_UYYVYY16_0_5X48; - - if (max_bpc >= 12 && info->bpc >= 12 && -- (info->hdmi.y420_dc_modes & DRM_EDID_YCBCR420_DC_36)) -+ (info->hdmi.y420_dc_modes & DRM_EDID_YCBCR420_DC_36) && -+ is_tmds_allowed(info, mode, MEDIA_BUS_FMT_UYYVYY12_0_5X36)) - output_fmts[i++] = MEDIA_BUS_FMT_UYYVYY12_0_5X36; - - if (max_bpc >= 10 && info->bpc >= 10 && -- (info->hdmi.y420_dc_modes & DRM_EDID_YCBCR420_DC_30)) -+ (info->hdmi.y420_dc_modes & DRM_EDID_YCBCR420_DC_30) && -+ is_tmds_allowed(info, mode, MEDIA_BUS_FMT_UYYVYY10_0_5X30)) - output_fmts[i++] = MEDIA_BUS_FMT_UYYVYY10_0_5X30; - - /* Default 8bit fallback */ -- output_fmts[i++] = MEDIA_BUS_FMT_UYYVYY8_0_5X24; -+ if (is_tmds_allowed(info, mode, MEDIA_BUS_FMT_UYYVYY8_0_5X24)) -+ output_fmts[i++] = MEDIA_BUS_FMT_UYYVYY8_0_5X24; - - if (drm_mode_is_420_only(info, mode)) - *num_output_fmts = i; -@@ -2732,40 +2744,51 @@ static u32 *dw_hdmi_bridge_atomic_get_output_bus_fmts(struct drm_bridge *bridge, - */ - - /* Default 8bit RGB fallback */ -- output_fmts[i++] = MEDIA_BUS_FMT_RGB888_1X24; -+ if (is_tmds_allowed(info, mode, MEDIA_BUS_FMT_RGB888_1X24)) -+ output_fmts[i++] = MEDIA_BUS_FMT_RGB888_1X24; - - if (max_bpc >= 16 && info->bpc == 16) { -- if (info->color_formats & DRM_COLOR_FORMAT_YCBCR444) -+ if ((info->color_formats & DRM_COLOR_FORMAT_YCBCR444) && -+ is_tmds_allowed(info, mode, MEDIA_BUS_FMT_YUV16_1X48)) - output_fmts[i++] = MEDIA_BUS_FMT_YUV16_1X48; - -- output_fmts[i++] = MEDIA_BUS_FMT_RGB161616_1X48; -+ if (is_tmds_allowed(info, mode, MEDIA_BUS_FMT_RGB161616_1X48)) -+ output_fmts[i++] = MEDIA_BUS_FMT_RGB161616_1X48; - } - - if (max_bpc >= 12 && info->bpc >= 12) { -- if (info->color_formats & DRM_COLOR_FORMAT_YCBCR422) -+ if ((info->color_formats & DRM_COLOR_FORMAT_YCBCR422) && -+ is_tmds_allowed(info, mode, MEDIA_BUS_FMT_UYVY12_1X24)) - output_fmts[i++] = MEDIA_BUS_FMT_UYVY12_1X24; - -- if (info->color_formats & DRM_COLOR_FORMAT_YCBCR444) -+ if ((info->color_formats & DRM_COLOR_FORMAT_YCBCR444) && -+ is_tmds_allowed(info, mode, MEDIA_BUS_FMT_YUV12_1X36)) - output_fmts[i++] = MEDIA_BUS_FMT_YUV12_1X36; - -- output_fmts[i++] = MEDIA_BUS_FMT_RGB121212_1X36; -+ if (is_tmds_allowed(info, mode, MEDIA_BUS_FMT_RGB121212_1X36)) -+ output_fmts[i++] = MEDIA_BUS_FMT_RGB121212_1X36; - } - - if (max_bpc >= 10 && info->bpc >= 10) { -- if (info->color_formats & DRM_COLOR_FORMAT_YCBCR422) -+ if ((info->color_formats & DRM_COLOR_FORMAT_YCBCR422) && -+ is_tmds_allowed(info, mode, MEDIA_BUS_FMT_UYVY10_1X20)) - output_fmts[i++] = MEDIA_BUS_FMT_UYVY10_1X20; - -- if (info->color_formats & DRM_COLOR_FORMAT_YCBCR444) -+ if ((info->color_formats & DRM_COLOR_FORMAT_YCBCR444) && -+ is_tmds_allowed(info, mode, MEDIA_BUS_FMT_YUV10_1X30)) - output_fmts[i++] = MEDIA_BUS_FMT_YUV10_1X30; - -- output_fmts[i++] = MEDIA_BUS_FMT_RGB101010_1X30; -+ if (is_tmds_allowed(info, mode, MEDIA_BUS_FMT_RGB101010_1X30)) -+ output_fmts[i++] = MEDIA_BUS_FMT_RGB101010_1X30; - } - -- if (info->color_formats & DRM_COLOR_FORMAT_YCBCR422) -+ if ((info->color_formats & DRM_COLOR_FORMAT_YCBCR422) && -+ is_tmds_allowed(info, mode, MEDIA_BUS_FMT_UYVY8_1X16)) - output_fmts[i++] = MEDIA_BUS_FMT_UYVY8_1X16; - -- if (info->color_formats & DRM_COLOR_FORMAT_YCBCR444) -+ if ((info->color_formats & DRM_COLOR_FORMAT_YCBCR444) && -+ is_tmds_allowed(info, mode, MEDIA_BUS_FMT_YUV8_1X24)) - output_fmts[i++] = MEDIA_BUS_FMT_YUV8_1X24; - - *num_output_fmts = i; - -@@ -2946,11 +2969,20 @@ dw_hdmi_bridge_mode_valid(struct drm_bridge *bridge, - struct dw_hdmi *hdmi = bridge->driver_private; - const struct dw_hdmi_plat_data *pdata = hdmi->plat_data; - enum drm_mode_status mode_status = MODE_OK; -+ int max_tmds_clock = info->max_tmds_clock ? info->max_tmds_clock : 340000; -+ int clock = mode->clock; - - /* We don't support double-clocked modes */ - if (mode->flags & DRM_MODE_FLAG_DBLCLK) - return MODE_BAD; - -+ if (pdata->ycbcr_420_allowed && drm_mode_is_420(info, mode) && -+ (info->color_formats & DRM_COLOR_FORMAT_YCBCR420)) -+ clock /= 2; -+ -+ if (clock > max_tmds_clock) -+ return MODE_CLOCK_HIGH; -+ - if (pdata->mode_valid) - mode_status = pdata->mode_valid(hdmi, pdata->priv_data, info, - mode); - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Jonas Karlman -Date: Fri, 20 Dec 2019 08:12:42 +0000 -Subject: [PATCH] WIP: drm/rockchip: dw_hdmi: add 10-bit rgb bus format - ---- - drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c | 42 +++++++++++++++++++++ - drivers/gpu/drm/rockchip/rockchip_drm_drv.h | 1 + - 2 files changed, 43 insertions(+) - -diff --git a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c -index d6d8f3335813..89424c5bc24a 100644 ---- a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c -+++ b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c -@@ -84,6 +84,8 @@ struct rockchip_hdmi { - struct phy *phy; - }; - -+#define to_crtc_state(x) container_of(x, struct drm_crtc_state, x) -+ - static struct rockchip_hdmi *to_rockchip_hdmi(struct drm_bridge *bridge) - { - return container_of(bridge, struct rockchip_hdmi, bridge); -@@ -341,6 +343,11 @@ dw_hdmi_rockchip_bridge_mode_set(struct drm_bridge *bridge, - const struct drm_display_mode *adjusted_mode) - { - struct rockchip_hdmi *hdmi = to_rockchip_hdmi(bridge); -+ struct drm_crtc_state *crtc_state = to_crtc_state(adjusted_mode); -+ struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc_state); -+ -+ if (hdmi->phy) -+ phy_set_bus_width(hdmi->phy, s->bus_width); - - clk_set_rate(hdmi->ref_clk, adjusted_mode->clock * 1000); - } -@@ -381,6 +388,17 @@ static bool is_rgb(u32 format) - { - switch (format) { - case MEDIA_BUS_FMT_RGB888_1X24: -+ case MEDIA_BUS_FMT_RGB101010_1X30: -+ return true; -+ default: -+ return false; -+ } -+} -+ -+static bool is_10bit(u32 format) -+{ -+ switch (format) { -+ case MEDIA_BUS_FMT_RGB101010_1X30: - return true; - default: - return false; -@@ -394,9 +412,24 @@ dw_hdmi_rockchip_bridge_atomic_check(struct drm_bridge *bridge, - struct drm_connector_state *conn_state) - { - struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc_state); -+ struct drm_atomic_state *state = bridge_state->base.state; -+ struct drm_crtc_state *old_crtc_state; -+ struct rockchip_crtc_state *old_state; -+ u32 format = bridge_state->output_bus_cfg.format; - - s->output_mode = ROCKCHIP_OUT_MODE_AAAA; - s->output_type = DRM_MODE_CONNECTOR_HDMIA; -+ s->output_bpc = 10; -+ s->bus_format = format; -+ s->bus_width = is_10bit(format) ? 10 : 8; -+ -+ old_crtc_state = drm_atomic_get_old_crtc_state(state, conn_state->crtc); -+ if (old_crtc_state && !crtc_state->mode_changed) { -+ old_state = to_rockchip_crtc_state(old_crtc_state); -+ if (s->bus_format != old_state->bus_format || -+ s->bus_width != old_state->bus_width) -+ crtc_state->mode_changed = true; -+ } - - return 0; - } -@@ -408,10 +441,19 @@ static u32 *dw_hdmi_rockchip_get_input_bus_fmts(struct drm_bridge *bridge, - u32 output_fmt, - unsigned int *num_input_fmts) - { -+ struct rockchip_hdmi *hdmi = to_rockchip_hdmi(bridge); -+ struct drm_encoder *encoder = bridge->encoder; - u32 *input_fmt; -+ bool has_10bit = true; - - *num_input_fmts = 0; - -+ if (drm_of_encoder_active_endpoint_id(hdmi->dev->of_node, encoder)) -+ has_10bit = false; -+ -+ if (!has_10bit && is_10bit(output_fmt)) -+ return NULL; -+ - if (!is_rgb(output_fmt)) - return NULL; - -diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_drv.h b/drivers/gpu/drm/rockchip/rockchip_drm_drv.h -index 1641440837af..381e5ccab5f3 100644 ---- a/drivers/gpu/drm/rockchip/rockchip_drm_drv.h -+++ b/drivers/gpu/drm/rockchip/rockchip_drm_drv.h -@@ -34,6 +34,7 @@ struct rockchip_crtc_state { - u32 bus_format; - u32 bus_flags; - int color_space; -+ int bus_width; - }; - #define to_rockchip_crtc_state(s) \ - container_of(s, struct rockchip_crtc_state, base) - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Jonas Karlman -Date: Sun, 8 Dec 2019 23:42:44 +0000 -Subject: [PATCH] WIP: drm: dw-hdmi: add content type connector property - -Signed-off-by: Jonas Karlman ---- - drivers/gpu/drm/bridge/synopsys/dw-hdmi.c | 8 +++++++- - 1 file changed, 7 insertions(+), 1 deletion(-) - -diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c -index 7f6ffbc3e7b2..ae4c49e84470 100644 ---- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c -+++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c -@@ -1790,6 +1790,7 @@ static void hdmi_config_AVI(struct dw_hdmi *hdmi, - const struct drm_connector *connector, - const struct drm_display_mode *mode) - { -+ const struct drm_connector_state *conn_state = connector->state; - struct hdmi_avi_infoframe frame; - u8 val; - -@@ -1847,6 +1848,8 @@ static void hdmi_config_AVI(struct dw_hdmi *hdmi, - HDMI_EXTENDED_COLORIMETRY_XV_YCC_601; - } - -+ drm_hdmi_avi_infoframe_content_type(&frame, conn_state); -+ - /* - * The Designware IP uses a different byte format from standard - * AVI info frames, though generally the bits are in the correct -@@ -2551,7 +2554,8 @@ static int dw_hdmi_connector_atomic_check(struct drm_connector *connector, - if (!crtc) - return 0; - -- if (!drm_connector_atomic_hdr_metadata_equal(old_state, new_state)) { -+ if (!drm_connector_atomic_hdr_metadata_equal(old_state, new_state) || -+ old_state->content_type != new_state->content_type) { - crtc_state = drm_atomic_get_crtc_state(state, crtc); - if (IS_ERR(crtc_state)) - return PTR_ERR(crtc_state); -@@ -2619,6 +2623,8 @@ static int dw_hdmi_connector_create(struct dw_hdmi *hdmi) - - drm_connector_attach_max_bpc_property(connector, 8, 16); - -+ drm_connector_attach_content_type_property(connector); -+ - if (hdmi->version >= 0x200a && hdmi->plat_data->use_drm_infoframe) - drm_connector_attach_hdr_output_metadata_property(connector); - - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Jonas Karlman -Date: Fri, 20 Dec 2019 08:12:43 +0000 -Subject: [PATCH] WIP: drm/rockchip: add yuv444 support - ---- - drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c | 29 ++++++++++++++++++++- - drivers/gpu/drm/rockchip/rockchip_drm_vop.c | 29 +++++++++++++++++++++ - drivers/gpu/drm/rockchip/rockchip_drm_vop.h | 6 +++++ - drivers/gpu/drm/rockchip/rockchip_vop_reg.c | 19 ++++++++++++++ - 4 files changed, 82 insertions(+), 1 deletion(-) - -diff --git a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c -index 89424c5bc24a..05de2052d95d 100644 ---- a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c -+++ b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c -@@ -68,6 +68,7 @@ struct rockchip_hdmi_chip_data { - int lcdsel_grf_reg; - u32 lcdsel_big; - u32 lcdsel_lit; -+ bool ycbcr_444_allowed; - }; - - struct rockchip_hdmi { -@@ -395,10 +396,22 @@ static bool is_rgb(u32 format) - } - } - -+static bool is_yuv444(u32 format) -+{ -+ switch (format) { -+ case MEDIA_BUS_FMT_YUV10_1X30: -+ case MEDIA_BUS_FMT_YUV8_1X24: -+ return true; -+ default: -+ return false; -+ } -+} -+ - static bool is_10bit(u32 format) - { - switch (format) { - case MEDIA_BUS_FMT_RGB101010_1X30: -+ case MEDIA_BUS_FMT_YUV10_1X30: - return true; - default: - return false; -@@ -415,12 +428,22 @@ dw_hdmi_rockchip_bridge_atomic_check(struct drm_bridge *bridge, - struct drm_atomic_state *state = bridge_state->base.state; - struct drm_crtc_state *old_crtc_state; - struct rockchip_crtc_state *old_state; -+ struct drm_bridge *next_bridge; -+ struct drm_bridge_state *next_bridge_state; - u32 format = bridge_state->output_bus_cfg.format; - - s->output_mode = ROCKCHIP_OUT_MODE_AAAA; - s->output_type = DRM_MODE_CONNECTOR_HDMIA; - s->output_bpc = 10; - s->bus_format = format; -+ -+ next_bridge = drm_bridge_get_next_bridge(bridge); -+ if (next_bridge) { -+ next_bridge_state = drm_atomic_get_new_bridge_state(state, -+ next_bridge); -+ format = next_bridge_state->output_bus_cfg.format; -+ } -+ - s->bus_width = is_10bit(format) ? 10 : 8; - - old_crtc_state = drm_atomic_get_old_crtc_state(state, conn_state->crtc); -@@ -454,7 +477,10 @@ static u32 *dw_hdmi_rockchip_get_input_bus_fmts(struct drm_bridge *bridge, - if (!has_10bit && is_10bit(output_fmt)) - return NULL; - -- if (!is_rgb(output_fmt)) -+ if (is_yuv444(output_fmt)) { -+ if (!hdmi->chip_data->ycbcr_444_allowed) -+ return NULL; -+ } else if (!is_rgb(output_fmt)) - return NULL; - - input_fmt = kzalloc(sizeof(*input_fmt), GFP_KERNEL); -@@ -604,6 +630,7 @@ static const struct dw_hdmi_phy_ops rk3328_hdmi_phy_ops = { - - static struct rockchip_hdmi_chip_data rk3328_chip_data = { - .lcdsel_grf_reg = -1, -+ .ycbcr_444_allowed = true, - }; - - static const struct dw_hdmi_plat_data rk3328_hdmi_drv_data = { -diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c -index eadf1b0f1704..0e4eca0d5121 100644 ---- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c -+++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c -@@ -347,6 +347,17 @@ static int vop_convert_afbc_format(uint32_t format) - return -EINVAL; - } - -+static bool is_yuv_output(uint32_t bus_format) -+{ -+ switch (bus_format) { -+ case MEDIA_BUS_FMT_YUV8_1X24: -+ case MEDIA_BUS_FMT_YUV10_1X30: -+ return true; -+ default: -+ return false; -+ } -+} -+ - static uint16_t scl_vop_cal_scale(enum scale_mode mode, uint32_t src, - uint32_t dst, bool is_horizontal, - int vsu_mode, int *vskiplines) -@@ -1455,6 +1466,7 @@ static void vop_crtc_atomic_enable(struct drm_crtc *crtc, - u16 vact_end = vact_st + vdisplay; - uint32_t pin_pol, val; - int dither_bpc = s->output_bpc ? s->output_bpc : 10; -+ bool yuv_output = is_yuv_output(s->bus_format); - int ret; - - if (old_state && old_state->self_refresh_active) { -@@ -1520,6 +1532,8 @@ static void vop_crtc_atomic_enable(struct drm_crtc *crtc, - !(vop_data->feature & VOP_FEATURE_OUTPUT_RGB10)) - s->output_mode = ROCKCHIP_OUT_MODE_P888; - -+ VOP_REG_SET(vop, common, dsp_data_swap, yuv_output ? 2 : 0); -+ - if (s->output_mode == ROCKCHIP_OUT_MODE_AAAA && dither_bpc <= 8) - VOP_REG_SET(vop, common, pre_dither_down, 1); - else -@@ -1535,6 +1549,21 @@ static void vop_crtc_atomic_enable(struct drm_crtc *crtc, - - VOP_REG_SET(vop, common, out_mode, s->output_mode); - -+ VOP_REG_SET(vop, common, overlay_mode, yuv_output); -+ VOP_REG_SET(vop, common, dsp_out_yuv, yuv_output); -+ -+ /* -+ * Background color is 10bit depth if vop version >= 3.5 -+ */ -+ if (!yuv_output) -+ val = 0; -+ else if (VOP_MAJOR(vop_data->version) == 3 && -+ VOP_MINOR(vop_data->version) >= 5) -+ val = 0x20010200; -+ else -+ val = 0x801080; -+ VOP_REG_SET(vop, common, dsp_background, val); -+ - VOP_REG_SET(vop, modeset, htotal_pw, (htotal << 16) | hsync_len); - val = hact_st << 16; - val |= hact_end; -diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.h b/drivers/gpu/drm/rockchip/rockchip_drm_vop.h -index ca4e2b7415fe..47ad74ef1afb 100644 ---- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.h -+++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.h -@@ -119,10 +119,16 @@ struct vop_common { - struct vop_reg mmu_en; - struct vop_reg out_mode; - struct vop_reg standby; -+ -+ struct vop_reg overlay_mode; -+ struct vop_reg dsp_data_swap; -+ struct vop_reg dsp_out_yuv; -+ struct vop_reg dsp_background; - }; - - struct vop_misc { - struct vop_reg global_regdone_en; -+ struct vop_reg win_channel[4]; - }; - - struct vop_intr { -diff --git a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c -index a2b281e290e0..b16a4c42773c 100644 ---- a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c -+++ b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c -@@ -705,6 +705,11 @@ static const struct vop_common rk3288_common = { - .dsp_blank = VOP_REG(RK3288_DSP_CTRL0, 0x3, 18), - .out_mode = VOP_REG(RK3288_DSP_CTRL0, 0xf, 0), - .cfg_done = VOP_REG_SYNC(RK3288_REG_CFG_DONE, 0x1, 0), -+ -+ .overlay_mode = VOP_REG(RK3288_SYS_CTRL, 0x1, 16), -+ .dsp_data_swap = VOP_REG(RK3288_DSP_CTRL0, 0x1f, 12), -+ .dsp_out_yuv = VOP_REG(RK3288_POST_SCL_CTRL, 0x1, 2), -+ .dsp_background = VOP_REG(RK3288_DSP_BG, 0xffffffff, 0), - }; - - /* -@@ -926,6 +931,11 @@ static const struct vop_common rk3399_common = { - .dsp_blank = VOP_REG(RK3399_DSP_CTRL0, 0x3, 18), - .out_mode = VOP_REG(RK3399_DSP_CTRL0, 0xf, 0), - .cfg_done = VOP_REG_SYNC(RK3399_REG_CFG_DONE, 0x1, 0), -+ -+ .overlay_mode = VOP_REG(RK3399_SYS_CTRL, 0x1, 16), -+ .dsp_data_swap = VOP_REG(RK3399_DSP_CTRL0, 0x1f, 12), -+ .dsp_out_yuv = VOP_REG(RK3288_POST_SCL_CTRL, 0x1, 2), -+ .dsp_background = VOP_REG(RK3288_DSP_BG, 0xffffffff, 0), - }; - - static const struct vop_yuv2yuv_phy rk3399_yuv2yuv_win01_data = { -@@ -1096,6 +1106,10 @@ static const struct vop_output rk3328_output = { - - static const struct vop_misc rk3328_misc = { - .global_regdone_en = VOP_REG(RK3328_SYS_CTRL, 0x1, 11), -+ -+ .win_channel[0] = VOP_REG(RK3328_WIN0_CTRL2, 0xff, 0), -+ .win_channel[1] = VOP_REG(RK3328_WIN1_CTRL2, 0xff, 0), -+ .win_channel[2] = VOP_REG(RK3328_WIN2_CTRL2, 0xff, 0), - }; - - static const struct vop_common rk3328_common = { -@@ -1108,6 +1122,11 @@ static const struct vop_common rk3328_common = { - .dsp_blank = VOP_REG(RK3328_DSP_CTRL0, 0x3, 18), - .out_mode = VOP_REG(RK3328_DSP_CTRL0, 0xf, 0), - .cfg_done = VOP_REG_SYNC(RK3328_REG_CFG_DONE, 0x1, 0), -+ -+ .overlay_mode = VOP_REG(RK3328_SYS_CTRL, 0x1, 16), -+ .dsp_data_swap = VOP_REG(RK3328_DSP_CTRL0, 0x1f, 12), -+ .dsp_out_yuv = VOP_REG(RK3328_POST_SCL_CTRL, 0x1, 2), -+ .dsp_background = VOP_REG(RK3328_DSP_BG, 0xffffffff, 0), - }; - - static const struct vop_intr rk3328_vop_intr = { - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Jonas Karlman -Date: Fri, 20 Dec 2019 08:12:43 +0000 -Subject: [PATCH] WIP: drm/rockchip: add yuv420 support - ---- - drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c | 22 +++++++++++++++++++++ - drivers/gpu/drm/rockchip/rockchip_drm_vop.c | 19 +++++++++++++++++- - drivers/gpu/drm/rockchip/rockchip_drm_vop.h | 10 ++++++---- - drivers/gpu/drm/rockchip/rockchip_vop_reg.c | 2 ++ - 4 files changed, 48 insertions(+), 5 deletions(-) - -diff --git a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c -index 05de2052d95d..cb201612199f 100644 ---- a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c -+++ b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c -@@ -407,9 +407,21 @@ static bool is_yuv444(u32 format) - } - } - -+static bool is_yuv420(u32 format) -+{ -+ switch (format) { -+ case MEDIA_BUS_FMT_UYYVYY10_0_5X30: -+ case MEDIA_BUS_FMT_UYYVYY8_0_5X24: -+ return true; -+ default: -+ return false; -+ } -+} -+ - static bool is_10bit(u32 format) - { - switch (format) { -+ case MEDIA_BUS_FMT_UYYVYY10_0_5X30: - case MEDIA_BUS_FMT_RGB101010_1X30: - case MEDIA_BUS_FMT_YUV10_1X30: - return true; -@@ -446,6 +458,11 @@ dw_hdmi_rockchip_bridge_atomic_check(struct drm_bridge *bridge, - - s->bus_width = is_10bit(format) ? 10 : 8; - -+ if (is_yuv420(format)) { -+ s->output_mode = ROCKCHIP_OUT_MODE_YUV420; -+ s->bus_width /= 2; -+ } -+ - old_crtc_state = drm_atomic_get_old_crtc_state(state, conn_state->crtc); - if (old_crtc_state && !crtc_state->mode_changed) { - old_state = to_rockchip_crtc_state(old_crtc_state); -@@ -466,6 +483,7 @@ static u32 *dw_hdmi_rockchip_get_input_bus_fmts(struct drm_bridge *bridge, - { - struct rockchip_hdmi *hdmi = to_rockchip_hdmi(bridge); - struct drm_encoder *encoder = bridge->encoder; -+ struct drm_connector *connector = conn_state->connector; - u32 *input_fmt; - bool has_10bit = true; - -@@ -480,6 +498,9 @@ static u32 *dw_hdmi_rockchip_get_input_bus_fmts(struct drm_bridge *bridge, - if (is_yuv444(output_fmt)) { - if (!hdmi->chip_data->ycbcr_444_allowed) - return NULL; -+ } else if (is_yuv420(output_fmt)) { -+ if (!connector->ycbcr_420_allowed) -+ return NULL; - } else if (!is_rgb(output_fmt)) - return NULL; - -@@ -640,6 +661,7 @@ static const struct dw_hdmi_plat_data rk3328_hdmi_drv_data = { - .phy_name = "inno_dw_hdmi_phy2", - .phy_force_vendor = true, - .use_drm_infoframe = true, -+ .ycbcr_420_allowed = true, - }; - - static struct rockchip_hdmi_chip_data rk3399_chip_data = { -diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c -index 0e4eca0d5121..e50f71ad3ceb 100644 ---- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c -+++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c -@@ -10,6 +10,7 @@ - #include - #include - #include -+#include - #include - #include - #include -@@ -348,6 +349,19 @@ static int vop_convert_afbc_format(uint32_t format) - } - - static bool is_yuv_output(uint32_t bus_format) -+{ -+ switch (bus_format) { -+ case MEDIA_BUS_FMT_YUV8_1X24: -+ case MEDIA_BUS_FMT_YUV10_1X30: -+ case MEDIA_BUS_FMT_UYYVYY8_0_5X24: -+ case MEDIA_BUS_FMT_UYYVYY10_0_5X30: -+ return true; -+ default: -+ return false; -+ } -+} -+ -+static bool bus_fmt_has_uv_swapped(uint32_t bus_format) - { - switch (bus_format) { - case MEDIA_BUS_FMT_YUV8_1X24: -@@ -1532,7 +1546,7 @@ static void vop_crtc_atomic_enable(struct drm_crtc *crtc, - !(vop_data->feature & VOP_FEATURE_OUTPUT_RGB10)) - s->output_mode = ROCKCHIP_OUT_MODE_P888; - -- VOP_REG_SET(vop, common, dsp_data_swap, yuv_output ? 2 : 0); -+ VOP_REG_SET(vop, common, dsp_data_swap, bus_fmt_has_uv_swapped(s->bus_format) ? 2 : 0); - - if (s->output_mode == ROCKCHIP_OUT_MODE_AAAA && dither_bpc <= 8) - VOP_REG_SET(vop, common, pre_dither_down, 1); -@@ -1549,6 +1563,9 @@ static void vop_crtc_atomic_enable(struct drm_crtc *crtc, - - VOP_REG_SET(vop, common, out_mode, s->output_mode); - -+ VOP_REG_SET(vop, common, dclk_ddr, -+ s->output_mode == ROCKCHIP_OUT_MODE_YUV420 ? 1 : 0); -+ - VOP_REG_SET(vop, common, overlay_mode, yuv_output); - VOP_REG_SET(vop, common, dsp_out_yuv, yuv_output); - -diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.h b/drivers/gpu/drm/rockchip/rockchip_drm_vop.h -index 47ad74ef1afb..94a615dca672 100644 ---- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.h -+++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.h -@@ -121,6 +121,7 @@ struct vop_common { - struct vop_reg standby; - - struct vop_reg overlay_mode; -+ struct vop_reg dclk_ddr; - struct vop_reg dsp_data_swap; - struct vop_reg dsp_out_yuv; - struct vop_reg dsp_background; -diff --git a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c -index b16a4c42773c..5463b04240f7 100644 ---- a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c -+++ b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c -@@ -707,6 +707,7 @@ static const struct vop_common rk3288_common = { - .cfg_done = VOP_REG_SYNC(RK3288_REG_CFG_DONE, 0x1, 0), - - .overlay_mode = VOP_REG(RK3288_SYS_CTRL, 0x1, 16), -+ .dclk_ddr = VOP_REG(RK3288_DSP_CTRL0, 0x1, 8), - .dsp_data_swap = VOP_REG(RK3288_DSP_CTRL0, 0x1f, 12), - .dsp_out_yuv = VOP_REG(RK3288_POST_SCL_CTRL, 0x1, 2), - .dsp_background = VOP_REG(RK3288_DSP_BG, 0xffffffff, 0), -@@ -1124,6 +1125,7 @@ static const struct vop_common rk3328_common = { - .cfg_done = VOP_REG_SYNC(RK3328_REG_CFG_DONE, 0x1, 0), - - .overlay_mode = VOP_REG(RK3328_SYS_CTRL, 0x1, 16), -+ .dclk_ddr = VOP_REG(RK3328_DSP_CTRL0, 0x1, 8), - .dsp_data_swap = VOP_REG(RK3328_DSP_CTRL0, 0x1f, 12), - .dsp_out_yuv = VOP_REG(RK3328_POST_SCL_CTRL, 0x1, 2), - .dsp_background = VOP_REG(RK3328_DSP_BG, 0xffffffff, 0), - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Alex Bee -Date: Sat, 15 Aug 2020 23:20:34 +0200 -Subject: [PATCH] drm/rockchip: enable ycbcr_420_allowed and ycbcr_444_allowed - for RK3228 - ---- - drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c | 2 ++ - 1 file changed, 2 insertions(+) - -diff --git a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c -index cb201612199f..8627f6826bfe 100644 ---- a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c -+++ b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c -@@ -616,6 +616,7 @@ static const struct dw_hdmi_phy_ops rk3228_hdmi_phy_ops = { - - static struct rockchip_hdmi_chip_data rk3228_chip_data = { - .lcdsel_grf_reg = -1, -+ .ycbcr_444_allowed = true, - }; - - static const struct dw_hdmi_plat_data rk3228_hdmi_drv_data = { -@@ -624,6 +625,7 @@ static const struct dw_hdmi_plat_data rk3228_hdmi_drv_data = { - .phy_ops = &rk3228_hdmi_phy_ops, - .phy_name = "inno_dw_hdmi_phy2", - .phy_force_vendor = true, -+ .ycbcr_420_allowed = true, - }; - - static struct rockchip_hdmi_chip_data rk3288_chip_data = { - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Jonas Karlman -Date: Sat, 18 Nov 2017 11:09:39 +0100 -Subject: [PATCH] rockchip: vop: force skip lines if image too big - ---- - drivers/gpu/drm/rockchip/rockchip_drm_vop.c | 13 ++++++++++--- - 1 file changed, 10 insertions(+), 3 deletions(-) - -diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c -index e50f71ad3ceb..ef0a078c22f4 100644 ---- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c -+++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c -@@ -965,6 +965,7 @@ static void vop_plane_atomic_update(struct drm_plane *plane, - int format; - int is_yuv = fb->format->is_yuv; - int i; -+ int skiplines = 0; - - /* - * can't update plane when vop is disabled. -@@ -983,8 +984,14 @@ static void vop_plane_atomic_update(struct drm_plane *plane, - obj = fb->obj[0]; - rk_obj = to_rockchip_obj(obj); - -+ /* -+ * Force skip lines when image is yuv and 3840 width, -+ * fixes a "jumping" green lines issue on RK3328. -+ */ - actual_w = drm_rect_width(src) >> 16; -- actual_h = drm_rect_height(src) >> 16; -+ if (actual_w == 3840 && is_yuv) -+ skiplines = 1; -+ actual_h = drm_rect_height(src) >> (16 + skiplines); - act_info = (actual_h - 1) << 16 | ((actual_w - 1) & 0xffff); - - dsp_info = (drm_rect_height(dest) - 1) << 16; -@@ -1026,7 +1033,7 @@ static void vop_plane_atomic_update(struct drm_plane *plane, - - VOP_WIN_SET(vop, win, format, format); - VOP_WIN_SET(vop, win, fmt_10, is_fmt_10(fb->format->format)); -- VOP_WIN_SET(vop, win, yrgb_vir, DIV_ROUND_UP(fb->pitches[0], 4)); -+ VOP_WIN_SET(vop, win, yrgb_vir, DIV_ROUND_UP(fb->pitches[0], 4 >> skiplines)); - VOP_WIN_SET(vop, win, yrgb_mst, dma_addr); - VOP_WIN_YUV2YUV_SET(vop, win_yuv2yuv, y2r_en, is_yuv); - VOP_WIN_SET(vop, win, y_mir_en, -@@ -1050,7 +1057,7 @@ static void vop_plane_atomic_update(struct drm_plane *plane, - offset += (src->y1 >> 16) * fb->pitches[1] / vsub; - - dma_addr = rk_uv_obj->dma_addr + offset + fb->offsets[1]; -- VOP_WIN_SET(vop, win, uv_vir, DIV_ROUND_UP(fb->pitches[1], 4)); -+ VOP_WIN_SET(vop, win, uv_vir, DIV_ROUND_UP(fb->pitches[1], 4 >> skiplines)); - VOP_WIN_SET(vop, win, uv_mst, dma_addr); - - for (i = 0; i < NUM_YUV2YUV_COEFFICIENTS; i++) { - - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Alex Bee -Date: Sat, 10 Apr 2021 16:54:26 +0200 -Subject: [PATCH] drm/bridge: dw-hdmi: fix RGB to YUV color space conversion - -We are currently providing color space conversion coefficents -for RGB to YUV conversion for full range to full range. -This is wrong, since we are hardcoding YCC quantization range -limited in the AVI infoframe (which is correct according to -HDMI specs). This results in to dark colors if this conversion -is used. -I verfied this by setting YCC quantization range to full in -AVI infoframe which resulted in correct colors. Doing this, -however, will be ignored by some (most) sinks. - -This patch fixes this, by providing CSC coefficents which -convert RGB full range to YUV limited range for both BT601 -and BT709 colorspaces. - -Fixes: 9aaf880ed4ee ("imx-drm: Add mx6 hdmi transmitter support") -Signed-off-by: Alex Bee ---- - drivers/gpu/drm/bridge/synopsys/dw-hdmi.c | 12 ++++++------ - 1 file changed, 6 insertions(+), 6 deletions(-) - -diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c -index ae4c49e84470..92e621f2714f 100644 ---- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c -+++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c -@@ -82,15 +82,15 @@ static const u16 csc_coeff_rgb_out_eitu709[3][4] = { - }; - - static const u16 csc_coeff_rgb_in_eitu601[3][4] = { -- { 0x2591, 0x1322, 0x074b, 0x0000 }, -- { 0x6535, 0x2000, 0x7acc, 0x0200 }, -- { 0x6acd, 0x7534, 0x2000, 0x0200 } -+ { 0x2040, 0x1080, 0x0640, 0x0040 }, -+ { 0xe880, 0x1c00, 0xfb80, 0x0200 }, -+ { 0xed80, 0xf680, 0x1c00, 0x0200 } - }; - - static const u16 csc_coeff_rgb_in_eitu709[3][4] = { -- { 0x2dc5, 0x0d9b, 0x049e, 0x0000 }, -- { 0x62f0, 0x2000, 0x7d11, 0x0200 }, -- { 0x6756, 0x78ab, 0x2000, 0x0200 } -+ { 0x2740, 0x0bc0, 0x0400, 0x0040 }, -+ { 0xe680, 0x1c00, 0xfd80, 0x0200 }, -+ { 0xea40, 0xf980, 0x1c00, 0x0200 } - }; - - static const u16 csc_coeff_rgb_full_to_rgb_limited[3][4] = { - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Jonas Karlman -Date: Tue, 1 Oct 2019 20:52:42 +0000 -Subject: [PATCH] media: cec-adap: add debounce support when setting an invalid - phys addr - -When EDID is refreshed, HDMI cable is unplugged/replugged or -an AVR is power cycled the CEC phys addr gets invalidated. - -This can cause some disruption of CEC communication when -adapter is being reconfigured. - -Add a debounce_ms module option that can be used to debounce setting -an invalid phys addr. Default is not to use debouncing. - -Using a configured debounce_ms of e.g. 5000 ms, cec reconfiguring -could be avoided when AVR was power cycled on my setup. - -Power off AVR (default cec.debounce_ms=0): -[ 101.536866] cec-dw_hdmi: new physical address f.f.f.f -[ 102.495686] cec-dw_hdmi: new physical address 2.1.0.0 -[ 102.495913] cec-dw_hdmi: physical address: 2.1.0.0, claim 1 logical addresses -[ 102.628574] cec-dw_hdmi: config: la 1 pa 2.1.0.0 -[ 105.130115] cec-dw_hdmi: new physical address f.f.f.f -[ 106.979705] cec-dw_hdmi: new physical address 2.1.0.0 -[ 106.979872] cec-dw_hdmi: physical address: 2.1.0.0, claim 1 logical addresses -[ 107.112399] cec-dw_hdmi: config: la 1 pa 2.1.0.0 -[ 108.979408] cec-dw_hdmi: reported physical address 2.0.0.0 for logical address 5 -[ 109.205386] cec-dw_hdmi: reported physical address 2.0.0.0 for logical address 11 - -Power on AVR (default cec.debounce_ms=0): -[ 158.398447] cec-dw_hdmi: new physical address f.f.f.f -[ 161.977714] cec-dw_hdmi: new physical address 2.1.0.0 -[ 161.978766] cec-dw_hdmi: physical address: 2.1.0.0, claim 1 logical addresses -[ 162.115624] cec-dw_hdmi: config: la 1 pa 2.1.0.0 -[ 162.402750] cec-dw_hdmi: new physical address f.f.f.f -[ 162.403389] cec-dw_hdmi: cec_transmit_msg_fh: adapter is unconfigured -[ 162.886757] cec-dw_hdmi: new physical address 2.1.0.0 -[ 162.886964] cec-dw_hdmi: physical address: 2.1.0.0, claim 1 logical addresses -[ 163.510725] cec-dw_hdmi: config: la 1 pa 2.1.0.0 -[ 173.034200] cec-dw_hdmi: message 10 89 02 05 timed out - -Power off AVR (cec.debounce_ms=5000): -[ 251.720471] cec-dw_hdmi: reported physical address 2.0.0.0 for logical address 5 -[ 251.922432] cec-dw_hdmi: reported physical address 2.0.0.0 for logical address 11 - -Power on AVR (cec.debounce_ms=5000): -[ 291.154262] cec-dw_hdmi: reported physical address 2.0.0.0 for logical address 5 -[ 291.296199] cec-dw_hdmi: reported physical address 2.0.0.0 for logical address 11 - -Signed-off-by: Jonas Karlman ---- - drivers/media/cec/core/cec-adap.c | 9 ++++++++- - drivers/media/cec/core/cec-core.c | 18 ++++++++++++++++++ - drivers/media/cec/core/cec-priv.h | 1 + - include/media/cec.h | 2 ++ - 4 files changed, 29 insertions(+), 1 deletion(-) - -diff --git a/drivers/media/cec/core/cec-adap.c b/drivers/media/cec/core/cec-adap.c -index 41a79293ee02..542ab1425339 100644 ---- a/drivers/media/cec/core/cec-adap.c -+++ b/drivers/media/cec/core/cec-adap.c -@@ -1674,8 +1674,15 @@ void cec_s_phys_addr(struct cec_adapter *adap, u16 phys_addr, bool block) - if (IS_ERR_OR_NULL(adap)) - return; - -+ cancel_delayed_work_sync(&adap->debounce_work); -+ - mutex_lock(&adap->lock); -- __cec_s_phys_addr(adap, phys_addr, block); -+ if (cec_debounce_ms > 0 && !block && phys_addr == CEC_PHYS_ADDR_INVALID && -+ adap->phys_addr != phys_addr) -+ schedule_delayed_work(&adap->debounce_work, -+ msecs_to_jiffies(cec_debounce_ms)); -+ else -+ __cec_s_phys_addr(adap, phys_addr, block); - mutex_unlock(&adap->lock); - } - EXPORT_SYMBOL_GPL(cec_s_phys_addr); -diff --git a/drivers/media/cec/core/cec-core.c b/drivers/media/cec/core/cec-core.c -index af358e901b5f..bece8c56e5af 100644 ---- a/drivers/media/cec/core/cec-core.c -+++ b/drivers/media/cec/core/cec-core.c -@@ -40,6 +40,10 @@ static bool debug_phys_addr; - module_param(debug_phys_addr, bool, 0644); - MODULE_PARM_DESC(debug_phys_addr, "add CEC_CAP_PHYS_ADDR if set"); - -+int cec_debounce_ms; -+module_param_named(debounce_ms, cec_debounce_ms, int, 0644); -+MODULE_PARM_DESC(debounce_ms, "debounce invalid phys addr"); -+ - static dev_t cec_dev_t; - - /* Active devices */ -@@ -188,6 +192,8 @@ static void cec_devnode_unregister(struct cec_adapter *adap) - - mutex_unlock(&devnode->lock); - -+ cancel_delayed_work_sync(&adap->debounce_work); -+ - mutex_lock(&adap->lock); - __cec_s_phys_addr(adap, CEC_PHYS_ADDR_INVALID, false); - __cec_s_log_addrs(adap, NULL, false); -@@ -246,6 +252,17 @@ static const struct file_operations cec_error_inj_fops = { - }; - #endif - -+static void cec_s_phys_addr_debounce(struct work_struct *work) -+{ -+ struct delayed_work *delayed_work = to_delayed_work(work); -+ struct cec_adapter *adap = -+ container_of(delayed_work, struct cec_adapter, debounce_work); -+ -+ mutex_lock(&adap->lock); -+ __cec_s_phys_addr(adap, CEC_PHYS_ADDR_INVALID, false); -+ mutex_unlock(&adap->lock); -+} -+ - struct cec_adapter *cec_allocate_adapter(const struct cec_adap_ops *ops, - void *priv, const char *name, u32 caps, - u8 available_las) -@@ -283,6 +300,7 @@ struct cec_adapter *cec_allocate_adapter(const struct cec_adap_ops *ops, - INIT_LIST_HEAD(&adap->transmit_queue); - INIT_LIST_HEAD(&adap->wait_queue); - init_waitqueue_head(&adap->kthread_waitq); -+ INIT_DELAYED_WORK(&adap->debounce_work, cec_s_phys_addr_debounce); - - /* adap->devnode initialization */ - INIT_LIST_HEAD(&adap->devnode.fhs); -diff --git a/drivers/media/cec/core/cec-priv.h b/drivers/media/cec/core/cec-priv.h -index b78df931aa74..ebbea63ea9de 100644 ---- a/drivers/media/cec/core/cec-priv.h -+++ b/drivers/media/cec/core/cec-priv.h -@@ -37,6 +37,7 @@ static inline bool msg_is_raw(const struct cec_msg *msg) - - /* cec-core.c */ - extern int cec_debug; -+extern int cec_debounce_ms; - int cec_get_device(struct cec_devnode *devnode); - void cec_put_device(struct cec_devnode *devnode); - -diff --git a/include/media/cec.h b/include/media/cec.h -index abee41ae02d0..544eedb5d671 100644 ---- a/include/media/cec.h -+++ b/include/media/cec.h -@@ -236,6 +236,8 @@ struct cec_adapter { - struct task_struct *kthread; - wait_queue_head_t kthread_waitq; - -+ struct delayed_work debounce_work; -+ - const struct cec_adap_ops *ops; - void *priv; - u32 capabilities; - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Alex Bee -Date: Fri, 22 Oct 2021 11:17:30 +0200 -Subject: [PATCH] WIP: drm/bridge: synopsys: Fix CEC not working after - power-cyclying - -This fixes standby -> power-on on Rockchip platform for, at least, -RK3288/RK3328/RK3399 where CEC wasn't working after powering on again. -It might differ for other phy implementations: -The whole HPD-detection part shoud be reworked and we should in general -avoid to rely in RX_SENSE phy status (at least for HDMI), since it differs -depending on sink's implementation. - -Signed-off-by: Alex Bee ---- - drivers/gpu/drm/bridge/synopsys/dw-hdmi.c | 14 ++++++++------ - 1 file changed, 8 insertions(+), 6 deletions(-) - -diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c -index 92e621f2714f..7551e3ab77d6 100644 ---- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c -+++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c -@@ -3179,12 +3179,6 @@ static irqreturn_t dw_hdmi_irq(int irq, void *dev_id) - phy_stat & HDMI_PHY_HPD, - phy_stat & HDMI_PHY_RX_SENSE); - -- if ((phy_stat & (HDMI_PHY_RX_SENSE | HDMI_PHY_HPD)) == 0) { -- mutex_lock(&hdmi->cec_notifier_mutex); -- cec_notifier_phys_addr_invalidate(hdmi->cec_notifier); -- mutex_unlock(&hdmi->cec_notifier_mutex); -- } -- - if (phy_stat & HDMI_PHY_HPD) - status = connector_status_connected; - -@@ -3201,6 +3195,14 @@ static irqreturn_t dw_hdmi_irq(int irq, void *dev_id) - drm_helper_hpd_irq_event(hdmi->bridge.dev); - drm_bridge_hpd_notify(&hdmi->bridge, status); - } -+ -+ if (status == connector_status_disconnected && -+ (phy_stat & HDMI_PHY_RX_SENSE) && -+ (phy_int_pol & HDMI_PHY_RX_SENSE)) { -+ mutex_lock(&hdmi->cec_notifier_mutex); -+ cec_notifier_phys_addr_invalidate(hdmi->cec_notifier); -+ mutex_unlock(&hdmi->cec_notifier_mutex); -+ } - } - - hdmi_writeb(hdmi, intr_stat, HDMI_IH_PHY_STAT0); - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Jonas Karlman -Date: Fri, 9 Oct 2020 15:24:53 +0000 -Subject: [PATCH] drm/rockchip: vop: create planes in window order - -Signed-off-by: Jonas Karlman ---- - drivers/gpu/drm/rockchip/rockchip_drm_vop.c | 36 +++------------------ - 1 file changed, 4 insertions(+), 32 deletions(-) - -diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c -index 49619f794061..9915bf124374 100644 ---- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c -+++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c -@@ -2023,19 +2023,10 @@ static int vop_create_crtc(struct vop *vop) - int ret; - int i; - -- /* -- * Create drm_plane for primary and cursor planes first, since we need -- * to pass them to drm_crtc_init_with_planes, which sets the -- * "possible_crtcs" to the newly initialized crtc. -- */ - for (i = 0; i < vop_data->win_size; i++) { - struct vop_win *vop_win = &vop->win[i]; - const struct vop_win_data *win_data = vop_win->data; - -- if (win_data->type != DRM_PLANE_TYPE_PRIMARY && -- win_data->type != DRM_PLANE_TYPE_CURSOR) -- continue; -- - ret = drm_universal_plane_init(vop->drm_dev, &vop_win->base, - 0, &vop_plane_funcs, - win_data->phy->data_formats, -@@ -2068,32 +2059,13 @@ static int vop_create_crtc(struct vop *vop) - drm_crtc_enable_color_mgmt(crtc, 0, false, vop_data->lut_size); - } - -- /* -- * Create drm_planes for overlay windows with possible_crtcs restricted -- * to the newly created crtc. -- */ -+ /* Set possible_crtcs to the newly created crtc for overlay windows */ - for (i = 0; i < vop_data->win_size; i++) { - struct vop_win *vop_win = &vop->win[i]; -- const struct vop_win_data *win_data = vop_win->data; -- unsigned long possible_crtcs = drm_crtc_mask(crtc); -- -- if (win_data->type != DRM_PLANE_TYPE_OVERLAY) -- continue; - -- ret = drm_universal_plane_init(vop->drm_dev, &vop_win->base, -- possible_crtcs, -- &vop_plane_funcs, -- win_data->phy->data_formats, -- win_data->phy->nformats, -- win_data->phy->format_modifiers, -- win_data->type, NULL); -- if (ret) { -- DRM_DEV_ERROR(vop->dev, "failed to init overlay %d\n", -- ret); -- goto err_cleanup_crtc; -- } -- drm_plane_helper_add(&vop_win->base, &plane_helper_funcs); -- vop_plane_add_properties(&vop_win->base, win_data); -+ plane = &vop_win->base; -+ if (plane->type == DRM_PLANE_TYPE_OVERLAY) -+ plane->possible_crtcs = drm_crtc_mask(crtc); - } - - port = of_get_child_by_name(dev->of_node, "port"); diff --git a/patch/kernel/archive/rockchip-6.11/patches.libreelec/linux-1001-v4l2-rockchip.patch b/patch/kernel/archive/rockchip-6.11/patches.libreelec/linux-1001-v4l2-rockchip.patch deleted file mode 100644 index d705909546c6..000000000000 --- a/patch/kernel/archive/rockchip-6.11/patches.libreelec/linux-1001-v4l2-rockchip.patch +++ /dev/null @@ -1,506 +0,0 @@ -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Jonas Karlman -Date: Sat, 23 May 2020 10:16:01 +0000 -Subject: [PATCH] WIP: media: rkvdec: pm runtime dont use autosuspend before - disable and cleanup - -Signed-off-by: Jonas Karlman ---- - drivers/staging/media/rkvdec/rkvdec.c | 4 ++-- - 1 file changed, 2 insertions(+), 2 deletions(-) - -diff --git a/drivers/staging/media/rkvdec/rkvdec.c b/drivers/staging/media/rkvdec/rkvdec.c -index 4f5436c89e08..eaf2f133a264 100644 ---- a/drivers/staging/media/rkvdec/rkvdec.c -+++ b/drivers/staging/media/rkvdec/rkvdec.c -@@ -1125,9 +1125,9 @@ static int rkvdec_remove(struct platform_device *pdev) - - cancel_delayed_work_sync(&rkvdec->watchdog_work); - -- rkvdec_v4l2_cleanup(rkvdec); -- pm_runtime_disable(&pdev->dev); - pm_runtime_dont_use_autosuspend(&pdev->dev); -+ pm_runtime_disable(&pdev->dev); -+ rkvdec_v4l2_cleanup(rkvdec); - } - - #ifdef CONFIG_PM - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Randy Li -Date: Sun, 6 Jan 2019 01:48:37 +0800 -Subject: [PATCH] soc: rockchip: power-domain: export idle request - -We need to put the power status of HEVC IP into IDLE unless -we can't reset that IP or the SoC would crash down. -rockchip_pmu_idle_request(dev, true)---> enter idle -rockchip_pmu_idle_request(dev, false)---> exit idle - -Signed-off-by: Caesar Wang -Signed-off-by: Jeffy Chen -Signed-off-by: Randy Li ---- - drivers/pmdomain/rockchip/pm-domains.c | 23 +++++++++++++++++++++++ - include/linux/rockchip_pmu.h | 15 +++++++++++++++ - include/soc/rockchip/pm_domains.h | 6 ++++++ - 3 files changed, 44 insertions(+) - create mode 100644 include/linux/rockchip_pmu.h - -diff --git a/drivers/pmdomain/rockchip/pm-domains.c b/drivers/pmdomain/rockchip/pm-domains.c -index 89795abac951..ffb5d62c9d52 100644 ---- a/drivers/pmdomain/rockchip/pm-domains.c -+++ b/drivers/pmdomain/rockchip/pm-domains.c -@@ -309,6 +309,29 @@ static int rockchip_pmu_set_idle_request(struct rockchip_pm_domain *pd, - return 0; - } - -+int rockchip_pmu_idle_request(struct device *dev, bool idle) -+{ -+ struct generic_pm_domain *genpd; -+ struct rockchip_pm_domain *pd; -+ int ret; -+ -+ if (IS_ERR_OR_NULL(dev)) -+ return -EINVAL; -+ -+ if (IS_ERR_OR_NULL(dev->pm_domain)) -+ return -EINVAL; -+ -+ genpd = pd_to_genpd(dev->pm_domain); -+ pd = to_rockchip_pd(genpd); -+ -+ mutex_lock(&pd->pmu->mutex); -+ ret = rockchip_pmu_set_idle_request(pd, idle); -+ mutex_unlock(&pd->pmu->mutex); -+ -+ return ret; -+} -+EXPORT_SYMBOL(rockchip_pmu_idle_request); -+ - static int rockchip_pmu_save_qos(struct rockchip_pm_domain *pd) - { - int i; -diff --git a/include/linux/rockchip_pmu.h b/include/linux/rockchip_pmu.h -new file mode 100644 -index 000000000000..720b3314e71a ---- /dev/null -+++ b/include/linux/rockchip_pmu.h -@@ -0,0 +1,15 @@ -+/* -+ * pm_domain.h - Definitions and headers related to device power domains. -+ * -+ * Copyright (C) 2017 Randy Li . -+ * -+ * This file is released under the GPLv2. -+ */ -+ -+#ifndef _LINUX_ROCKCHIP_PM_H -+#define _LINUX_ROCKCHIP_PM_H -+#include -+ -+int rockchip_pmu_idle_request(struct device *dev, bool idle); -+ -+#endif /* _LINUX_ROCKCHIP_PM_H */ -diff --git a/include/soc/rockchip/pm_domains.h b/include/soc/rockchip/pm_domains.h -index 7dbd941fc937..c5a59dd71754 100644 ---- a/include/soc/rockchip/pm_domains.h -+++ b/include/soc/rockchip/pm_domains.h -@@ -10,6 +10,7 @@ - - int rockchip_pmu_block(void); - void rockchip_pmu_unblock(void); -+int rockchip_pmu_idle_request(struct device *dev, bool idle); - - #else /* CONFIG_ROCKCHIP_PM_DOMAINS */ - -@@ -20,6 +21,11 @@ static inline int rockchip_pmu_block(void) - - static inline void rockchip_pmu_unblock(void) { } - -+static inline int rockchip_pmu_idle_request(struct device *dev, bool idle) -+{ -+ return -ENOTSUPP; -+} -+ - #endif /* CONFIG_ROCKCHIP_PM_DOMAINS */ - - #endif /* __SOC_ROCKCHIP_PM_DOMAINS_H__ */ - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Alex Bee -Date: Wed, 20 May 2020 17:04:47 +0200 -Subject: [PATCH] WIP: media: rkvdec: implement reset controls - ---- - .../bindings/media/rockchip,vdec.yaml | 19 +++++++ - drivers/staging/media/rkvdec/rkvdec-regs.h | 5 ++ - drivers/staging/media/rkvdec/rkvdec.c | 53 +++++++++++++++++++ - drivers/staging/media/rkvdec/rkvdec.h | 11 +++- - 4 files changed, 87 insertions(+), 1 deletion(-) - -diff --git a/Documentation/devicetree/bindings/media/rockchip,vdec.yaml b/Documentation/devicetree/bindings/media/rockchip,vdec.yaml -index 3bcfb8e12333..dd6958df1de8 100644 ---- a/Documentation/devicetree/bindings/media/rockchip,vdec.yaml -+++ b/Documentation/devicetree/bindings/media/rockchip,vdec.yaml -@@ -53,6 +53,18 @@ properties: - iommus: - maxItems: 1 - -+ resets: -+ maxItems: 6 -+ -+ reset-names: -+ items: -+ - const: video_h -+ - const: video_a -+ - const: video_core -+ - const: video_cabac -+ - const: niu_a -+ - const: niu_h -+ - required: - - compatible - - reg -@@ -60,6 +72,8 @@ required: - - clocks - - clock-names - - power-domains -+ - resets -+ - reset-names - - additionalProperties: false - -@@ -78,6 +92,11 @@ examples: - clock-names = "axi", "ahb", "cabac", "core"; - power-domains = <&power RK3399_PD_VDU>; - iommus = <&vdec_mmu>; -+ resets = <&cru SRST_H_VDU>, <&cru SRST_A_VDU>, -+ <&cru SRST_VDU_CORE>, <&cru SRST_VDU_CA>, -+ <&cru SRST_A_VDU_NOC>, <&cru SRST_H_VDU_NOC>; -+ reset-names = "video_h", "video_a", "video_core", "video_cabac", -+ "niu_a", "niu_h"; - }; - - ... -diff --git a/drivers/staging/media/rkvdec/rkvdec-regs.h b/drivers/staging/media/rkvdec/rkvdec-regs.h -index 15b9bee92016..3acc914888f6 100644 ---- a/drivers/staging/media/rkvdec/rkvdec-regs.h -+++ b/drivers/staging/media/rkvdec/rkvdec-regs.h -@@ -28,6 +28,11 @@ - #define RKVDEC_SOFTRST_EN_P BIT(20) - #define RKVDEC_FORCE_SOFTRESET_VALID BIT(21) - #define RKVDEC_SOFTRESET_RDY BIT(22) -+#define RKVDEC_ERR_MASK (RKVDEC_BUS_STA \ -+ | RKVDEC_ERR_STA \ -+ | RKVDEC_TIMEOUT_STA \ -+ | RKVDEC_BUF_EMPTY_STA \ -+ | RKVDEC_COLMV_REF_ERR_STA ) - - #define RKVDEC_REG_SYSCTRL 0x008 - #define RKVDEC_IN_ENDIAN BIT(0) -diff --git a/drivers/staging/media/rkvdec/rkvdec.c b/drivers/staging/media/rkvdec/rkvdec.c -index eaf2f133a264..f55abb7c377f 100644 ---- a/drivers/staging/media/rkvdec/rkvdec.c -+++ b/drivers/staging/media/rkvdec/rkvdec.c -@@ -10,12 +10,15 @@ - */ - - #include -+#include - #include - #include - #include - #include - #include - #include -+#include -+#include - #include - #include - #include -@@ -717,6 +720,11 @@ static void rkvdec_job_finish(struct rkvdec_ctx *ctx, - - pm_runtime_mark_last_busy(rkvdec->dev); - pm_runtime_put_autosuspend(rkvdec->dev); -+ -+ if (result == VB2_BUF_STATE_ERROR && -+ rkvdec->reset_mask == RESET_NONE) -+ rkvdec->reset_mask |= RESET_SOFT; -+ - rkvdec_job_finish_no_pm(ctx, result); - } - -@@ -754,6 +762,33 @@ static void rkvdec_device_run(void *priv) - - if (WARN_ON(!desc)) - return; -+ if (rkvdec->reset_mask != RESET_NONE) { -+ -+ if (rkvdec->reset_mask & RESET_SOFT) { -+ writel(RKVDEC_SOFTRST_EN_P, -+ rkvdec->regs + RKVDEC_REG_INTERRUPT); -+ udelay(RKVDEC_RESET_DELAY); -+ if (readl(rkvdec->regs + RKVDEC_REG_INTERRUPT) -+ & RKVDEC_SOFTRESET_RDY) -+ dev_info_ratelimited(rkvdec->dev, -+ "softreset failed\n"); -+ } -+ -+ if (rkvdec->reset_mask & RESET_HARD) { -+ rockchip_pmu_idle_request(rkvdec->dev, true); -+ ret = reset_control_assert(rkvdec->rstc); -+ if (!ret) { -+ udelay(RKVDEC_RESET_DELAY); -+ ret = reset_control_deassert(rkvdec->rstc); -+ } -+ rockchip_pmu_idle_request(rkvdec->dev, false); -+ if (ret) -+ dev_notice_ratelimited(rkvdec->dev, -+ "hardreset failed\n"); -+ } -+ rkvdec->reset_mask = RESET_NONE; -+ pm_runtime_suspend(rkvdec->dev); -+ } - - ret = pm_runtime_resume_and_get(rkvdec->dev); - if (ret < 0) { -@@ -1020,6 +1055,11 @@ static irqreturn_t rkvdec_irq_handler(int irq, void *priv) - if (cancel_delayed_work(&rkvdec->watchdog_work)) { - struct rkvdec_ctx *ctx; - -+ if (state == VB2_BUF_STATE_ERROR) { -+ rkvdec->reset_mask |= (status & RKVDEC_ERR_MASK) ? -+ RESET_HARD : RESET_SOFT; -+ } -+ - ctx = v4l2_m2m_get_curr_priv(rkvdec->m2m_dev); - rkvdec_job_finish(ctx, state); - } -@@ -1037,6 +1077,7 @@ static void rkvdec_watchdog_func(struct work_struct *work) - ctx = v4l2_m2m_get_curr_priv(rkvdec->m2m_dev); - if (ctx) { - dev_err(rkvdec->dev, "Frame processing timed out!\n"); -+ rkvdec->reset_mask |= RESET_HARD; - writel(RKVDEC_IRQ_DIS, rkvdec->regs + RKVDEC_REG_INTERRUPT); - writel(0, rkvdec->regs + RKVDEC_REG_SYSCTRL); - rkvdec_job_finish(ctx, VB2_BUF_STATE_ERROR); -@@ -1105,6 +1146,18 @@ static int rkvdec_probe(struct platform_device *pdev) - return ret; - } - -+ -+ rkvdec->rstc = devm_reset_control_array_get(&pdev->dev, false, true); -+ if (IS_ERR(rkvdec->rstc)) { -+ dev_err(&pdev->dev, -+ "get resets failed %ld\n", PTR_ERR(rkvdec->rstc)); -+ return PTR_ERR(rkvdec->rstc); -+ } else { -+ dev_dbg(&pdev->dev, -+ "requested %d resets\n", -+ reset_control_get_count(&pdev->dev)); -+ } -+ - pm_runtime_set_autosuspend_delay(&pdev->dev, 100); - pm_runtime_use_autosuspend(&pdev->dev); - pm_runtime_enable(&pdev->dev); -diff --git a/drivers/staging/media/rkvdec/rkvdec.h b/drivers/staging/media/rkvdec/rkvdec.h -index b9e219438bc9..f02f79c405f0 100644 ---- a/drivers/staging/media/rkvdec/rkvdec.h -+++ b/drivers/staging/media/rkvdec/rkvdec.h -@@ -11,10 +11,11 @@ - #ifndef RKVDEC_H_ - #define RKVDEC_H_ - -+#include - #include -+#include - #include - #include --#include - - #include - #include -@@ -22,6 +23,12 @@ - #include - #include - -+#define RESET_NONE 0 -+#define RESET_SOFT BIT(0) -+#define RESET_HARD BIT(1) -+ -+#define RKVDEC_RESET_DELAY 5 -+ - struct rkvdec_ctx; - - struct rkvdec_ctrl_desc { -@@ -96,6 +103,8 @@ struct rkvdec_dev { - void __iomem *regs; - struct mutex vdev_lock; /* serializes ioctls */ - struct delayed_work watchdog_work; -+ struct reset_control *rstc; -+ u8 reset_mask; - }; - - struct rkvdec_ctx { - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Alex Bee -Date: Tue, 18 Aug 2020 11:38:04 +0200 -Subject: [PATCH] WIP: arm64: dts: add resets to vdec for RK3399 - ---- - arch/arm64/boot/dts/rockchip/rk3399.dtsi | 5 +++++ - 1 file changed, 5 insertions(+) - -diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi -index 980b12cb0a49..6e3149e587c5 100644 ---- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi -+++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi -@@ -1345,6 +1348,11 @@ vdec: video-codec@ff660000 { - clock-names = "axi", "ahb", "cabac", "core"; - iommus = <&vdec_mmu>; - power-domains = <&power RK3399_PD_VDU>; -+ resets = <&cru SRST_H_VDU>, <&cru SRST_A_VDU>, -+ <&cru SRST_VDU_CORE>, <&cru SRST_VDU_CA>, -+ <&cru SRST_A_VDU_NOC>, <&cru SRST_H_VDU_NOC>; -+ reset-names = "video_h", "video_a", "video_core", "video_cabac", -+ "niu_a", "niu_h"; - }; - - vdec_mmu: iommu@ff660480 { - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Alex Bee -Date: Sat, 21 Aug 2021 16:12:36 +0200 -Subject: [PATCH] media: hantro: rockchip: Increase RK3288's max ACLK - -Required to proper decode H.264@4K - -Signed-off-by: Alex Bee ---- - drivers/media/platform/verisilicon/rockchip_vpu_hw.c | 14 +++++++++++--- - 1 file changed, 11 insertions(+), 3 deletions(-) - -diff --git a/drivers/media/platform/verisilicon/rockchip_vpu_hw.c b/drivers/media/platform/verisilicon/rockchip_vpu_hw.c -index 8de6fd2e8eef..002b1a600f93 100644 ---- a/drivers/media/platform/verisilicon/rockchip_vpu_hw.c -+++ b/drivers/media/platform/verisilicon/rockchip_vpu_hw.c -@@ -15,7 +15,8 @@ - #include "rockchip_vpu2_regs.h" - - #define RK3066_ACLK_MAX_FREQ (300 * 1000 * 1000) --#define RK3288_ACLK_MAX_FREQ (400 * 1000 * 1000) -+#define RK3288_ACLK_MAX_FREQ (600 * 1000 * 1000) -+#define RK3399_ACLK_MAX_FREQ (400 * 1000 * 1000) - #define RK3588_ACLK_MAX_FREQ (300 * 1000 * 1000) - - #define ROCKCHIP_VPU981_MIN_SIZE 64 -@@ -346,13 +347,20 @@ static int rk3066_vpu_hw_init(struct hantro_dev *vpu) - return 0; - } - --static int rockchip_vpu_hw_init(struct hantro_dev *vpu) -+static int rk3288_vpu_hw_init(struct hantro_dev *vpu) - { - /* Bump ACLK to max. possible freq. to improve performance. */ - clk_set_rate(vpu->clocks[0].clk, RK3288_ACLK_MAX_FREQ); - return 0; - } - -+static int rockchip_vpu_hw_init(struct hantro_dev *vpu) -+{ -+ /* Bump ACLK to max. possible freq. to improve performance. */ -+ clk_set_rate(vpu->clocks[0].clk, RK3399_ACLK_MAX_FREQ); -+ return 0; -+} -+ - static void rk3066_vpu_dec_reset(struct hantro_ctx *ctx) - { - struct hantro_dev *vpu = ctx->dev; -@@ -592,7 +600,7 @@ const struct hantro_variant rk3288_vpu_variant = { - .codec_ops = rk3288_vpu_codec_ops, - .irqs = rockchip_vpu1_irqs, - .num_irqs = ARRAY_SIZE(rockchip_vpu1_irqs), -- .init = rockchip_vpu_hw_init, -+ .init = rk3288_vpu_hw_init, - .clk_names = rockchip_vpu_clk_names, - .num_clocks = ARRAY_SIZE(rockchip_vpu_clk_names) - }; - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Alex Bee -Date: Sun, 4 Jul 2021 15:19:44 +0200 -Subject: [PATCH] media: rkvdec: disable QoS for VP9 (corruptions on RK3328 - otherwise) - -Signed-off-by: Alex Bee ---- - drivers/staging/media/rkvdec/rkvdec-regs.h | 2 ++ - drivers/staging/media/rkvdec/rkvdec-vp9.c | 8 ++++++++ - 2 files changed, 10 insertions(+) - -diff --git a/drivers/staging/media/rkvdec/rkvdec-regs.h b/drivers/staging/media/rkvdec/rkvdec-regs.h -index 3acc914888f6..265f5234f4eb 100644 ---- a/drivers/staging/media/rkvdec/rkvdec-regs.h -+++ b/drivers/staging/media/rkvdec/rkvdec-regs.h -@@ -222,6 +222,8 @@ - #define RKVDEC_REG_H264_ERR_E 0x134 - #define RKVDEC_H264_ERR_EN_HIGHBITS(x) ((x) & 0x3fffffff) - -+#define RKVDEC_QOS_CTRL 0x18C -+ - #define RKVDEC_REG_PREF_LUMA_CACHE_COMMAND 0x410 - #define RKVDEC_REG_PREF_CHR_CACHE_COMMAND 0x450 - -diff --git a/drivers/staging/media/rkvdec/rkvdec-vp9.c b/drivers/staging/media/rkvdec/rkvdec-vp9.c -index d8c1c0db15c7..a289bc968e91 100644 ---- a/drivers/staging/media/rkvdec/rkvdec-vp9.c -+++ b/drivers/staging/media/rkvdec/rkvdec-vp9.c -@@ -802,6 +802,7 @@ static int rkvdec_vp9_run(struct rkvdec_ctx *ctx) - struct rkvdec_dev *rkvdec = ctx->dev; - struct rkvdec_vp9_run run = { }; - int ret; -+ u32 reg; - - ret = rkvdec_vp9_run_preamble(ctx, &run); - if (ret) { -@@ -823,6 +824,13 @@ static int rkvdec_vp9_run(struct rkvdec_ctx *ctx) - writel(1, rkvdec->regs + RKVDEC_REG_PREF_CHR_CACHE_COMMAND); - - writel(0xe, rkvdec->regs + RKVDEC_REG_STRMD_ERR_EN); -+ -+ /* disable QOS for RK3328 - no effect on other SoCs */ -+ reg = readl(rkvdec->regs + RKVDEC_QOS_CTRL); -+ reg |= 0xFFFF; -+ reg &= (~BIT(12)); -+ writel(reg, rkvdec->regs + RKVDEC_QOS_CTRL); -+ - /* Start decoding! */ - writel(RKVDEC_INTERRUPT_DEC_E | RKVDEC_CONFIG_DEC_CLK_GATE_E | - RKVDEC_TIMEOUT_E | RKVDEC_BUF_EMPTY_E, - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Alex Bee -Date: Thu, 16 Jun 2022 13:18:22 +0200 -Subject: [PATCH] WIP: arm64: dts: add resets to vdec for RK3328 - ---- - arch/arm64/boot/dts/rockchip/rk3328.dtsi | 5 +++++ - 1 file changed, 5 insertions(+) - -diff --git a/arch/arm64/boot/dts/rockchip/rk3328.dtsi b/arch/arm64/boot/dts/rockchip/rk3328.dtsi -index 5519347232f6..431c4ec198be 100644 ---- a/arch/arm64/boot/dts/rockchip/rk3328.dtsi -+++ b/arch/arm64/boot/dts/rockchip/rk3328.dtsi -@@ -674,6 +674,11 @@ vdec: video-codec@ff360000 { - assigned-clocks = <&cru ACLK_RKVDEC>, <&cru SCLK_VDEC_CABAC>, - <&cru SCLK_VDEC_CORE>; - assigned-clock-rates = <400000000>, <400000000>, <300000000>; -+ resets = <&cru SRST_VDEC_H>, <&cru SRST_VDEC_A>, -+ <&cru SRST_VDEC_CORE>, <&cru SRST_VDEC_CABAC>, -+ <&cru SRST_VDEC_NIU_A>, <&cru SRST_VDEC_NIU_H>; -+ reset-names = "video_h", "video_a", "video_core", "video_cabac", -+ "niu_a", "niu_h"; - iommus = <&vdec_mmu>; - power-domains = <&power RK3328_PD_VIDEO>; - }; diff --git a/patch/kernel/archive/rockchip-6.11/patches.libreelec/linux-1002-for-libreelec.patch b/patch/kernel/archive/rockchip-6.11/patches.libreelec/linux-1002-for-libreelec.patch deleted file mode 100644 index 1143681e4d09..000000000000 --- a/patch/kernel/archive/rockchip-6.11/patches.libreelec/linux-1002-for-libreelec.patch +++ /dev/null @@ -1,688 +0,0 @@ -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Alex Bee -Date: Wed, 2 Sep 2020 19:52:02 +0200 -Subject: [PATCH] arm64: dts: rockchip: add gpu powerdomain, gpu opp-table and - cooling cell for RK3328 - -Note: since the regulator that supplies the GPU usually also supplies -other SoC components, we have to make sure voltage is never lower then -1075 mV - also disable 500 MHz for now, since it will crash if rkvdec -is running at the same time (voltage to high) - -Signed-off-by: Alex Bee ---- - .../arm64/boot/dts/rockchip/rk3328-roc-cc.dts | 4 +++ - .../arm64/boot/dts/rockchip/rk3328-rock64.dts | 4 +++ - arch/arm64/boot/dts/rockchip/rk3328.dtsi | 35 +++++++++++++++++++ - 3 files changed, 43 insertions(+) - -diff --git a/arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts b/arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts -index aa22a0c22265..51c7723d6762 100644 ---- a/arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts -@@ -166,6 +166,10 @@ &gmac2io { - status = "okay"; - }; - -+&gpu { -+ mali-supply = <&vdd_logic>; -+}; -+ - &hdmi { - status = "okay"; - }; -diff --git a/arch/arm64/boot/dts/rockchip/rk3328-rock64.dts b/arch/arm64/boot/dts/rockchip/rk3328-rock64.dts -index f69a38f42d2d..c198a8a7f95a 100644 ---- a/arch/arm64/boot/dts/rockchip/rk3328-rock64.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3328-rock64.dts -@@ -162,6 +162,10 @@ &gmac2io { - status = "okay"; - }; - -+&gpu { -+ mali-supply = <&vdd_logic>; -+}; -+ - &hdmi { - status = "okay"; - }; -diff --git a/arch/arm64/boot/dts/rockchip/rk3328.dtsi b/arch/arm64/boot/dts/rockchip/rk3328.dtsi -index 431c4ec198be..eec03adf0902 100644 ---- a/arch/arm64/boot/dts/rockchip/rk3328.dtsi -+++ b/arch/arm64/boot/dts/rockchip/rk3328.dtsi -@@ -300,6 +300,11 @@ power: power-controller { - #address-cells = <1>; - #size-cells = <0>; - -+ power-domain@RK3328_PD_GPU { -+ reg = ; -+ clocks = <&cru ACLK_GPU>; -+ #power-domain-cells = <0>; -+ }; - power-domain@RK3328_PD_HEVC { - reg = ; - #power-domain-cells = <0>; -@@ -539,6 +544,11 @@ map0 { - <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - contribution = <4096>; - }; -+ map1 { -+ trip = <&target>; -+ cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; -+ contribution = <4096>; -+ }; - }; - }; - -@@ -620,7 +630,32 @@ gpu: gpu@ff300000 { - "ppmmu1"; - clocks = <&cru ACLK_GPU>, <&cru ACLK_GPU>; - clock-names = "bus", "core"; -+ operating-points-v2 = <&gpu_opp_table>; -+ power-domains = <&power RK3328_PD_GPU>; - resets = <&cru SRST_GPU_A>; -+ #cooling-cells = <2>; -+ }; -+ -+ gpu_opp_table: gpu-opp-table { -+ compatible = "operating-points-v2"; -+ -+ opp-200000000 { -+ opp-hz = /bits/ 64 <200000000>; -+ opp-microvolt = <1075000>; -+ }; -+ opp-300000000 { -+ opp-hz = /bits/ 64 <300000000>; -+ opp-microvolt = <1075000>; -+ }; -+ opp-400000000 { -+ opp-hz = /bits/ 64 <400000000>; -+ opp-microvolt = <1075000>; -+ }; -+ opp-500000000 { -+ opp-hz = /bits/ 64 <500000000>; -+ opp-microvolt = <1150000>; -+ status = "disabled"; -+ }; - }; - - h265e_mmu: iommu@ff330200 { - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Alex Bee -Date: Tue, 2 Feb 2021 17:22:21 +0200 -Subject: [PATCH] ARM: dts: RK3288 miqi add hdmi sound nodes - -Signed-off-by: Alex Bee ---- - arch/arm/boot/dts/rockchip/rk3288-miqi.dts | 20 ++++++++++++++++++++ - 1 file changed, 20 insertions(+) - -diff --git a/arch/arm/boot/dts/rockchip/rk3288-miqi.dts b/arch/arm/boot/dts/rockchip/rk3288-miqi.dts -index 713f55e143c6..8d30c49f406e 100644 ---- a/arch/arm/boot/dts/rockchip/rk3288-miqi.dts -+++ b/arch/arm/boot/dts/rockchip/rk3288-miqi.dts -@@ -78,6 +78,21 @@ vcc_sys: vsys-regulator { - regulator-always-on; - regulator-boot-on; - }; -+ -+ sound { -+ compatible = "simple-audio-card"; -+ simple-audio-card,format = "i2s"; -+ simple-audio-card,name = "HDMI"; -+ simple-audio-card,mclk-fs = <512>; -+ -+ simple-audio-card,codec { -+ sound-dai = <&hdmi>; -+ }; -+ -+ simple-audio-card,cpu { -+ sound-dai = <&i2s>; -+ }; -+ }; - }; - - &cpu0 { -@@ -284,6 +299,11 @@ &i2c5 { - status = "okay"; - }; - -+&i2s { -+ #sound-dai-cells = <0>; -+ status = "okay"; -+}; -+ - &io_domains { - status = "okay"; - - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Alex Bee -Date: Fri, 2 Apr 2021 17:54:22 +0200 -Subject: [PATCH] ARM/arm64: dts: rockchip: align sound card names - -Signed-off-by: Alex Bee ---- - arch/arm/boot/dts/rockchip/rk3288-tinker.dtsi | 2 +- - arch/arm64/boot/dts/rockchip/rk3399.dtsi | 2 +- - 2 files changed, 2 insertions(+), 2 deletions(-) - -diff --git a/arch/arm/boot/dts/rockchip/rk3288-tinker.dtsi b/arch/arm/boot/dts/rockchip/rk3288-tinker.dtsi -index 09618bb7d872..db9106a3dd22 100644 ---- a/arch/arm/boot/dts/rockchip/rk3288-tinker.dtsi -+++ b/arch/arm/boot/dts/rockchip/rk3288-tinker.dtsi -@@ -73,7 +73,7 @@ sdio_pwrseq: sdio-pwrseq { - sound { - compatible = "simple-audio-card"; - simple-audio-card,format = "i2s"; -- simple-audio-card,name = "rockchip,tinker-codec"; -+ simple-audio-card,name = "HDMI"; - simple-audio-card,mclk-fs = <512>; - - simple-audio-card,codec { -diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi -index 093ebe070775..a10fe60b7680 100644 ---- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi -+++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi -@@ -1893,7 +1893,7 @@ hdmi_sound: hdmi-sound { - compatible = "simple-audio-card"; - simple-audio-card,format = "i2s"; - simple-audio-card,mclk-fs = <256>; -- simple-audio-card,name = "hdmi-sound"; -+ simple-audio-card,name = "HDMI"; - status = "disabled"; - - simple-audio-card,cpu { - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Jonas Karlman -Date: Sun, 25 Mar 2018 22:17:06 +0200 -Subject: [PATCH] ASoC: hdmi-codec: fix channel allocation - ---- - sound/soc/codecs/hdmi-codec.c | 113 ++++++++++++++++------------------ - 1 file changed, 52 insertions(+), 61 deletions(-) - -diff --git a/sound/soc/codecs/hdmi-codec.c b/sound/soc/codecs/hdmi-codec.c -index 5679102de91f..f0cd183f7873 100644 ---- a/sound/soc/codecs/hdmi-codec.c -+++ b/sound/soc/codecs/hdmi-codec.c -@@ -194,78 +194,69 @@ static const struct snd_pcm_chmap_elem hdmi_codec_8ch_chmaps[] = { - */ - static const struct hdmi_codec_cea_spk_alloc hdmi_codec_channel_alloc[] = { - { .ca_id = 0x00, .n_ch = 2, -- .mask = FL | FR}, -- /* 2.1 */ -- { .ca_id = 0x01, .n_ch = 4, -- .mask = FL | FR | LFE}, -- /* Dolby Surround */ -+ .mask = FL | FR }, -+ { .ca_id = 0x03, .n_ch = 4, -+ .mask = FL | FR | LFE | FC }, - { .ca_id = 0x02, .n_ch = 4, - .mask = FL | FR | FC }, -- /* surround51 */ -+ { .ca_id = 0x01, .n_ch = 4, -+ .mask = FL | FR | LFE }, - { .ca_id = 0x0b, .n_ch = 6, -- .mask = FL | FR | LFE | FC | RL | RR}, -- /* surround40 */ -- { .ca_id = 0x08, .n_ch = 6, -- .mask = FL | FR | RL | RR }, -- /* surround41 */ -- { .ca_id = 0x09, .n_ch = 6, -- .mask = FL | FR | LFE | RL | RR }, -- /* surround50 */ -+ .mask = FL | FR | LFE | FC | RL | RR }, - { .ca_id = 0x0a, .n_ch = 6, - .mask = FL | FR | FC | RL | RR }, -- /* 6.1 */ -- { .ca_id = 0x0f, .n_ch = 8, -- .mask = FL | FR | LFE | FC | RL | RR | RC }, -- /* surround71 */ -+ { .ca_id = 0x09, .n_ch = 6, -+ .mask = FL | FR | LFE | RL | RR }, -+ { .ca_id = 0x08, .n_ch = 6, -+ .mask = FL | FR | RL | RR }, -+ { .ca_id = 0x07, .n_ch = 6, -+ .mask = FL | FR | LFE | FC | RC }, -+ { .ca_id = 0x06, .n_ch = 6, -+ .mask = FL | FR | FC | RC }, -+ { .ca_id = 0x05, .n_ch = 6, -+ .mask = FL | FR | LFE | RC }, -+ { .ca_id = 0x04, .n_ch = 6, -+ .mask = FL | FR | RC }, - { .ca_id = 0x13, .n_ch = 8, - .mask = FL | FR | LFE | FC | RL | RR | RLC | RRC }, -- /* others */ -- { .ca_id = 0x03, .n_ch = 8, -- .mask = FL | FR | LFE | FC }, -- { .ca_id = 0x04, .n_ch = 8, -- .mask = FL | FR | RC}, -- { .ca_id = 0x05, .n_ch = 8, -- .mask = FL | FR | LFE | RC }, -- { .ca_id = 0x06, .n_ch = 8, -- .mask = FL | FR | FC | RC }, -- { .ca_id = 0x07, .n_ch = 8, -- .mask = FL | FR | LFE | FC | RC }, -- { .ca_id = 0x0c, .n_ch = 8, -- .mask = FL | FR | RC | RL | RR }, -- { .ca_id = 0x0d, .n_ch = 8, -- .mask = FL | FR | LFE | RL | RR | RC }, -- { .ca_id = 0x0e, .n_ch = 8, -- .mask = FL | FR | FC | RL | RR | RC }, -- { .ca_id = 0x10, .n_ch = 8, -- .mask = FL | FR | RL | RR | RLC | RRC }, -- { .ca_id = 0x11, .n_ch = 8, -- .mask = FL | FR | LFE | RL | RR | RLC | RRC }, -+ { .ca_id = 0x1f, .n_ch = 8, -+ .mask = FL | FR | LFE | FC | RL | RR | FLC | FRC }, - { .ca_id = 0x12, .n_ch = 8, - .mask = FL | FR | FC | RL | RR | RLC | RRC }, -- { .ca_id = 0x14, .n_ch = 8, -- .mask = FL | FR | FLC | FRC }, -- { .ca_id = 0x15, .n_ch = 8, -- .mask = FL | FR | LFE | FLC | FRC }, -- { .ca_id = 0x16, .n_ch = 8, -- .mask = FL | FR | FC | FLC | FRC }, -- { .ca_id = 0x17, .n_ch = 8, -- .mask = FL | FR | LFE | FC | FLC | FRC }, -- { .ca_id = 0x18, .n_ch = 8, -- .mask = FL | FR | RC | FLC | FRC }, -- { .ca_id = 0x19, .n_ch = 8, -- .mask = FL | FR | LFE | RC | FLC | FRC }, -- { .ca_id = 0x1a, .n_ch = 8, -- .mask = FL | FR | RC | FC | FLC | FRC }, -- { .ca_id = 0x1b, .n_ch = 8, -- .mask = FL | FR | LFE | RC | FC | FLC | FRC }, -- { .ca_id = 0x1c, .n_ch = 8, -- .mask = FL | FR | RL | RR | FLC | FRC }, -- { .ca_id = 0x1d, .n_ch = 8, -- .mask = FL | FR | LFE | RL | RR | FLC | FRC }, - { .ca_id = 0x1e, .n_ch = 8, - .mask = FL | FR | FC | RL | RR | FLC | FRC }, -- { .ca_id = 0x1f, .n_ch = 8, -- .mask = FL | FR | LFE | FC | RL | RR | FLC | FRC }, -+ { .ca_id = 0x11, .n_ch = 8, -+ .mask = FL | FR | LFE | RL | RR | RLC | RRC }, -+ { .ca_id = 0x1d, .n_ch = 8, -+ .mask = FL | FR | LFE | RL | RR | FLC | FRC }, -+ { .ca_id = 0x10, .n_ch = 8, -+ .mask = FL | FR | RL | RR | RLC | RRC }, -+ { .ca_id = 0x1c, .n_ch = 8, -+ .mask = FL | FR | RL | RR | FLC | FRC }, -+ { .ca_id = 0x0f, .n_ch = 8, -+ .mask = FL | FR | LFE | FC | RL | RR | RC }, -+ { .ca_id = 0x1b, .n_ch = 8, -+ .mask = FL | FR | LFE | RC | FC | FLC | FRC }, -+ { .ca_id = 0x0e, .n_ch = 8, -+ .mask = FL | FR | FC | RL | RR | RC }, -+ { .ca_id = 0x1a, .n_ch = 8, -+ .mask = FL | FR | RC | FC | FLC | FRC }, -+ { .ca_id = 0x0d, .n_ch = 8, -+ .mask = FL | FR | LFE | RL | RR | RC }, -+ { .ca_id = 0x19, .n_ch = 8, -+ .mask = FL | FR | LFE | RC | FLC | FRC }, -+ { .ca_id = 0x0c, .n_ch = 8, -+ .mask = FL | FR | RC | RL | RR }, -+ { .ca_id = 0x18, .n_ch = 8, -+ .mask = FL | FR | RC | FLC | FRC }, -+ { .ca_id = 0x17, .n_ch = 8, -+ .mask = FL | FR | LFE | FC | FLC | FRC }, -+ { .ca_id = 0x16, .n_ch = 8, -+ .mask = FL | FR | FC | FLC | FRC }, -+ { .ca_id = 0x15, .n_ch = 8, -+ .mask = FL | FR | LFE | FLC | FRC }, -+ { .ca_id = 0x14, .n_ch = 8, -+ .mask = FL | FR | FLC | FRC }, - }; - - struct hdmi_codec_priv { - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Alex Bee -Date: Sat, 27 Feb 2021 17:52:02 +0100 -Subject: [PATCH] arm64: dts: rockchip: add SPDIF nodes for RK3328 A1 board - -Signed-off-by: Alex Bee ---- - arch/arm64/boot/dts/rockchip/rk3328-a1.dts | 23 ++++++++++++++++++++++ - 1 file changed, 23 insertions(+) - -diff --git a/arch/arm64/boot/dts/rockchip/rk3328-a1.dts b/arch/arm64/boot/dts/rockchip/rk3328-a1.dts -index 40bf808642b9..27a1799027c2 100644 ---- a/arch/arm64/boot/dts/rockchip/rk3328-a1.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3328-a1.dts -@@ -57,6 +57,24 @@ ir-receiver { - gpios = <&gpio2 RK_PA2 GPIO_ACTIVE_LOW>; - linux,rc-map-name = "rc-beelink-gs1"; - }; -+ -+ spdif_sound: spdif-sound { -+ compatible = "simple-audio-card"; -+ simple-audio-card,name = "SPDIF"; -+ -+ simple-audio-card,cpu { -+ sound-dai = <&spdif>; -+ }; -+ -+ simple-audio-card,codec { -+ sound-dai = <&spdif_dit>; -+ }; -+ }; -+ -+ spdif_dit: spdif-dit { -+ compatible = "linux,spdif-dit"; -+ #sound-dai-cells = <0>; -+ }; - }; - - &analog_sound { -@@ -325,6 +343,11 @@ &sdmmc { - status = "okay"; - }; - -+&spdif { -+ pinctrl-0 = <&spdifm0_tx>; -+ status = "okay"; -+}; -+ - &tsadc { - rockchip,hw-tshut-mode = <0>; - rockchip,hw-tshut-polarity = <0>; - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Alex Bee -Date: Sat, 27 Feb 2021 18:01:13 +0100 -Subject: [PATCH] arm64: dts: rockchip: Add ir-receiver node for RK3328 ROC CC - -Signed-off-by: Alex Bee ---- - arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts | 14 ++++++++++++++ - 1 file changed, 14 insertions(+) - -diff --git a/arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts b/arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts -index 51c7723d6762..cf321302daec 100644 ---- a/arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts -@@ -88,6 +88,13 @@ vcc_phy: vcc-phy-regulator { - regulator-boot-on; - }; - -+ ir-receiver { -+ compatible = "gpio-ir-receiver"; -+ gpios = <&gpio2 RK_PA2 GPIO_ACTIVE_LOW>; -+ pinctrl-0 = <&ir_int>; -+ pinctrl-names = "default"; -+ }; -+ - leds { - compatible = "gpio-leds"; - -@@ -312,6 +319,13 @@ &io_domains { - }; - - &pinctrl { -+ -+ ir { -+ ir_int: ir-int { -+ rockchip,pins = <2 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ }; -+ - pmic { - pmic_int_l: pmic-int-l { - rockchip,pins = <1 RK_PD0 RK_FUNC_GPIO &pcfg_pull_up>; - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Alex Bee -Date: Mon, 1 Mar 2021 21:24:15 +0100 -Subject: [PATCH] ARM: dts: add cec pinctrl for RK3288 miqi board - ---- - arch/arm/boot/dts/rockchip/rk3288-miqi.dts | 2 ++ - 1 file changed, 2 insertions(+) - -diff --git a/arch/arm/boot/dts/rockchip/rk3288-miqi.dts b/arch/arm/boot/dts/rockchip/rk3288-miqi.dts -index 8d30c49f406e..6d90db5a3b75 100644 ---- a/arch/arm/boot/dts/rockchip/rk3288-miqi.dts -+++ b/arch/arm/boot/dts/rockchip/rk3288-miqi.dts -@@ -145,6 +145,8 @@ &gpu { - - &hdmi { - ddc-i2c-bus = <&i2c5>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&hdmi_cec_c0>; - status = "okay"; - }; - - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Alex Bee -Date: Mon, 1 Mar 2021 19:22:15 +0100 -Subject: [PATCH] HACK: arm64: dts: enable FE phy for Beelink A1 also - ---- - arch/arm64/boot/dts/rockchip/rk3328-a1.dts | 8 ++++++++ - 1 file changed, 8 insertions(+) - -diff --git a/arch/arm64/boot/dts/rockchip/rk3328-a1.dts b/arch/arm64/boot/dts/rockchip/rk3328-a1.dts -index 27a1799027c2..7de9dfa71d89 100644 ---- a/arch/arm64/boot/dts/rockchip/rk3328-a1.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3328-a1.dts -@@ -147,6 +147,14 @@ rtl8211f: ethernet-phy@0 { - }; - }; - -+&gmac2phy { -+ clock_in_out = "output"; -+ assigned-clock-rate = <50000000>; -+ assigned-clocks = <&cru SCLK_MAC2PHY>; -+ assigned-clock-parents = <&cru SCLK_MAC2PHY_SRC>; -+ status = "okay"; -+}; -+ - &gpu { - mali-supply = <&vdd_logic>; - }; - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Jonas Karlman -Date: Tue, 26 Feb 2019 20:45:14 +0000 -Subject: [PATCH] WIP: dw-hdmi-cec: sleep 100ms on error - ---- - drivers/gpu/drm/bridge/synopsys/dw-hdmi-cec.c | 18 ++++++++++++++++-- - 1 file changed, 16 insertions(+), 2 deletions(-) - -diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi-cec.c b/drivers/gpu/drm/bridge/synopsys/dw-hdmi-cec.c -index c8f44bcb298a..d4280ce4542c 100644 ---- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi-cec.c -+++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi-cec.c -@@ -4,6 +4,7 @@ - * - * Copyright (C) 2015-2017 Russell King. - */ -+#include - #include - #include - #include -@@ -129,8 +130,15 @@ static irqreturn_t dw_hdmi_cec_hardirq(int irq, void *data) - - dw_hdmi_write(cec, stat, HDMI_IH_CEC_STAT0); - -- if (stat & CEC_STAT_ERROR_INIT) { -- cec->tx_status = CEC_TX_STATUS_ERROR; -+ /* Status with both done and error_initiator bits have been seen -+ * on Rockchip RK3328 devices, transmit attempt seems to have failed -+ * when this happens, report as low drive and block cec-framework -+ * 100ms before core retransmits the failed message, this seems to -+ * mitigate the issue with failed transmit attempts. -+ */ -+ if ((stat & (CEC_STAT_DONE|CEC_STAT_ERROR_INIT)) == (CEC_STAT_DONE|CEC_STAT_ERROR_INIT)) { -+ pr_debug("dw_hdmi_cec_hardirq: stat=%02x LOW_DRIVE\n", stat); -+ cec->tx_status = CEC_TX_STATUS_LOW_DRIVE; - cec->tx_done = true; - ret = IRQ_WAKE_THREAD; - } else if (stat & CEC_STAT_DONE) { -@@ -141,6 +149,10 @@ static irqreturn_t dw_hdmi_cec_hardirq(int irq, void *data) - cec->tx_status = CEC_TX_STATUS_NACK; - cec->tx_done = true; - ret = IRQ_WAKE_THREAD; -+ } else if (stat & CEC_STAT_ERROR_INIT) { -+ cec->tx_status = CEC_TX_STATUS_ERROR; -+ cec->tx_done = true; -+ ret = IRQ_WAKE_THREAD; - } - - if (stat & CEC_STAT_EOM) { -@@ -173,6 +185,8 @@ static irqreturn_t dw_hdmi_cec_thread(int irq, void *data) - - if (cec->tx_done) { - cec->tx_done = false; -+ if (cec->tx_status == CEC_TX_STATUS_LOW_DRIVE) -+ msleep(100); - cec_transmit_attempt_done(adap, cec->tx_status); - } - if (cec->rx_done) { - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Alex Bee -Date: Wed, 5 May 2021 19:11:12 +0200 -Subject: [PATCH] arm64: boot: dts: Increase ACLK_PERILP0 clock rate for RK3399 - -As per vendor kernel. Leaving this clock at the lower rate will -result in poor DMA controller performance - -Signed-off-by: Alex Bee ---- - arch/arm64/boot/dts/rockchip/rk3399.dtsi | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - -diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi -index a10fe60b7680..dbe6a9cb98a5 100644 ---- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi -+++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi -@@ -1477,7 +1477,7 @@ cru: clock-controller@ff760000 { - <1000000000>, - <150000000>, <75000000>, - <37500000>, -- <100000000>, <100000000>, -+ <300000000>, <100000000>, - <50000000>, <600000000>, - <100000000>, <50000000>, - <400000000>, <400000000>, - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Alex Bee -Date: Sat, 21 Aug 2021 17:04:46 +0200 -Subject: [PATCH] arm64: dts: rockchip: Enable USB3 for rk3328 Beelink A1 - -Signed-off-by: Alex Bee ---- - arch/arm64/boot/dts/rockchip/rk3328-a1.dts | 5 +++++ - 1 file changed, 5 insertions(+) - -diff --git a/arch/arm64/boot/dts/rockchip/rk3328-a1.dts b/arch/arm64/boot/dts/rockchip/rk3328-a1.dts -index 7de9dfa71d89..e857e5a727f4 100644 ---- a/arch/arm64/boot/dts/rockchip/rk3328-a1.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3328-a1.dts -@@ -389,6 +389,11 @@ &usb_host0_ehci { - status = "okay"; - }; - -+&usbdrd3 { -+ dr_mode = "host"; -+ status = "okay"; -+}; -+ - &vop { - status = "okay"; - }; - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Alex Bee -Date: Sat, 30 Oct 2021 12:19:19 +0200 -Subject: [PATCH] WIP: drm: bridge: dw-hdmi: switch from .hw_parmas to .prepare - for i2s - -Seems to be the only way to get AES bits correctly as set by -userspace. -TODO: check other consequences. - -Signed-off-by: Alex Bee ---- - drivers/gpu/drm/bridge/synopsys/dw-hdmi-i2s-audio.c | 8 ++++---- - 1 file changed, 4 insertions(+), 4 deletions(-) - -diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi-i2s-audio.c b/drivers/gpu/drm/bridge/synopsys/dw-hdmi-i2s-audio.c -index a2f0860b20bb..8961f9c7885d 100644 ---- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi-i2s-audio.c -+++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi-i2s-audio.c -@@ -34,9 +34,9 @@ static inline u8 hdmi_read(struct dw_hdmi_i2s_audio_data *audio, int offset) - return audio->read(hdmi, offset); - } - --static int dw_hdmi_i2s_hw_params(struct device *dev, void *data, -- struct hdmi_codec_daifmt *fmt, -- struct hdmi_codec_params *hparms) -+static int dw_hdmi_i2s_prepare(struct device *dev, void *data, -+ struct hdmi_codec_daifmt *fmt, -+ struct hdmi_codec_params *hparms) - { - struct dw_hdmi_i2s_audio_data *audio = data; - struct dw_hdmi *hdmi = audio->hdmi; -@@ -178,7 +178,7 @@ static int dw_hdmi_i2s_hook_plugged_cb(struct device *dev, void *data, - } - - static const struct hdmi_codec_ops dw_hdmi_i2s_ops = { -- .hw_params = dw_hdmi_i2s_hw_params, -+ .prepare = dw_hdmi_i2s_prepare, - .audio_startup = dw_hdmi_i2s_audio_startup, - .audio_shutdown = dw_hdmi_i2s_audio_shutdown, - .get_eld = dw_hdmi_i2s_get_eld, - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Alex Bee -Date: Sun, 18 Sep 2022 10:35:52 +0200 -Subject: [PATCH] arm64: dts: rockchip: Disbake fusb for rk3399-roc-pc - -As it will lead to an unbootable device in case one if those ports -is used to power up the device. -See https://lkml.org/lkml/2022/6/20/413 ---- - arch/arm64/boot/dts/rockchip/rk3399-roc-pc.dtsi | 6 +++--- - 1 file changed, 3 insertions(+), 3 deletions(-) - -diff --git a/arch/arm64/boot/dts/rockchip/rk3399-roc-pc.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-roc-pc.dtsi -index 2f4b1b2e3ac7..7217ead94d39 100644 ---- a/arch/arm64/boot/dts/rockchip/rk3399-roc-pc.dtsi -+++ b/arch/arm64/boot/dts/rockchip/rk3399-roc-pc.dtsi -@@ -215,7 +215,7 @@ vdd_log: vdd-log { - regulator-name = "vdd_log"; - regulator-always-on; - regulator-boot-on; -- regulator-min-microvolt = <450000>; -+ regulator-min-microvolt = <430000>; - regulator-max-microvolt = <1400000>; - pwm-supply = <&vcc3v3_sys>; - }; -@@ -536,7 +536,7 @@ fusb1: usb-typec@22 { - pinctrl-names = "default"; - pinctrl-0 = <&fusb1_int>; - vbus-supply = <&vcc_vbus_typec1>; -- status = "okay"; -+ status = "disabled"; - }; - }; - -@@ -553,7 +553,7 @@ fusb0: usb-typec@22 { - pinctrl-names = "default"; - pinctrl-0 = <&fusb0_int>; - vbus-supply = <&vcc_vbus_typec0>; -- status = "okay"; -+ status = "disabled"; - }; - - mp8859: regulator@66 { diff --git a/patch/kernel/archive/rockchip-6.11/patches.libreelec/linux-2000-v4l2-wip-rkvdec-hevc.patch b/patch/kernel/archive/rockchip-6.11/patches.libreelec/linux-2000-v4l2-wip-rkvdec-hevc.patch deleted file mode 100644 index 58b3e72e5a27..000000000000 --- a/patch/kernel/archive/rockchip-6.11/patches.libreelec/linux-2000-v4l2-wip-rkvdec-hevc.patch +++ /dev/null @@ -1,3226 +0,0 @@ -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Jonas Karlman -Date: Sat, 23 May 2020 15:17:45 +0000 -Subject: [PATCH] WIP: media: rkvdec: add HEVC backend - -NOTE: cabac table and scailing list code is copied 1:1 from mpp -TODO: fix lowdelay flag and rework the scaling list part - -Signed-off-by: Jonas Karlman -Signed-off-by: Alex Bee ---- - drivers/staging/media/rkvdec/Makefile | 2 +- - drivers/staging/media/rkvdec/rkvdec-hevc.c | 2572 ++++++++++++++++++++ - drivers/staging/media/rkvdec/rkvdec-regs.h | 1 + - drivers/staging/media/rkvdec/rkvdec.c | 73 +- - drivers/staging/media/rkvdec/rkvdec.h | 1 + - 5 files changed, 2647 insertions(+), 2 deletions(-) - create mode 100644 drivers/staging/media/rkvdec/rkvdec-hevc.c - -diff --git a/drivers/staging/media/rkvdec/Makefile b/drivers/staging/media/rkvdec/Makefile -index cb86b429cfaa..a77122641d14 100644 ---- a/drivers/staging/media/rkvdec/Makefile -+++ b/drivers/staging/media/rkvdec/Makefile -@@ -1,3 +1,3 @@ - obj-$(CONFIG_VIDEO_ROCKCHIP_VDEC) += rockchip-vdec.o - --rockchip-vdec-y += rkvdec.o rkvdec-h264.o rkvdec-vp9.o -+rockchip-vdec-y += rkvdec.o rkvdec-h264.o rkvdec-hevc.o rkvdec-vp9.o -diff --git a/drivers/staging/media/rkvdec/rkvdec-hevc.c b/drivers/staging/media/rkvdec/rkvdec-hevc.c -new file mode 100644 -index 000000000000..7a375a23eaf1 ---- /dev/null -+++ b/drivers/staging/media/rkvdec/rkvdec-hevc.c -@@ -0,0 +1,2572 @@ -+// SPDX-License-Identifier: GPL-2.0 -+/* -+ * Rockchip Video Decoder HEVC backend -+ * -+ * Copyright (C) 2019 Collabora, Ltd. -+ * Boris Brezillon -+ * -+ * Copyright (C) 2016 Rockchip Electronics Co., Ltd. -+ * Jeffy Chen -+ */ -+ -+#include -+ -+#include "rkvdec.h" -+#include "rkvdec-regs.h" -+ -+/* Size in u8/u32 units. */ -+#define RKV_CABAC_TABLE_SIZE 27456 -+#define RKV_SCALING_LIST_SIZE 1360 -+#define RKV_PPS_SIZE (80 / 4) -+#define RKV_PPS_LEN 64 -+#define RKV_RPS_SIZE (32 / 4) -+#define RKV_RPS_LEN 600 -+ -+struct rkvdec_sps_pps_packet { -+ u32 info[RKV_PPS_SIZE]; -+}; -+ -+struct rkvdec_rps_packet { -+ u32 info[RKV_RPS_SIZE]; -+}; -+ -+struct rkvdec_ps_field { -+ u16 offset; -+ u8 len; -+}; -+ -+#define PS_FIELD(_offset, _len) \ -+ ((struct rkvdec_ps_field){ _offset, _len }) -+ -+/* SPS */ -+#define VIDEO_PARAMETER_SET_ID PS_FIELD(0, 4) -+#define SEQ_PARAMETER_SET_ID PS_FIELD(4, 4) -+#define CHROMA_FORMAT_IDC PS_FIELD(8, 2) -+#define PIC_WIDTH_IN_LUMA_SAMPLES PS_FIELD(10, 13) -+#define PIC_HEIGHT_IN_LUMA_SAMPLES PS_FIELD(23, 13) -+#define BIT_DEPTH_LUMA PS_FIELD(36, 4) -+#define BIT_DEPTH_CHROMA PS_FIELD(40, 4) -+#define LOG2_MAX_PIC_ORDER_CNT_LSB PS_FIELD(44, 5) -+#define LOG2_DIFF_MAX_MIN_LUMA_CODING_BLOCK_SIZE PS_FIELD(49, 2) -+#define LOG2_MIN_LUMA_CODING_BLOCK_SIZE PS_FIELD(51, 3) -+#define LOG2_MIN_TRANSFORM_BLOCK_SIZE PS_FIELD(54, 3) -+#define LOG2_DIFF_MAX_MIN_LUMA_TRANSFORM_BLOCK_SIZE PS_FIELD(57, 2) -+#define MAX_TRANSFORM_HIERARCHY_DEPTH_INTER PS_FIELD(59, 3) -+#define MAX_TRANSFORM_HIERARCHY_DEPTH_INTRA PS_FIELD(62, 3) -+#define SCALING_LIST_ENABLED_FLAG PS_FIELD(65, 1) -+#define AMP_ENABLED_FLAG PS_FIELD(66, 1) -+#define SAMPLE_ADAPTIVE_OFFSET_ENABLED_FLAG PS_FIELD(67, 1) -+#define PCM_ENABLED_FLAG PS_FIELD(68, 1) -+#define PCM_SAMPLE_BIT_DEPTH_LUMA PS_FIELD(69, 4) -+#define PCM_SAMPLE_BIT_DEPTH_CHROMA PS_FIELD(73, 4) -+#define PCM_LOOP_FILTER_DISABLED_FLAG PS_FIELD(77, 1) -+#define LOG2_DIFF_MAX_MIN_PCM_LUMA_CODING_BLOCK_SIZE PS_FIELD(78, 3) -+#define LOG2_MIN_PCM_LUMA_CODING_BLOCK_SIZE PS_FIELD(81, 3) -+#define NUM_SHORT_TERM_REF_PIC_SETS PS_FIELD(84, 7) -+#define LONG_TERM_REF_PICS_PRESENT_FLAG PS_FIELD(91, 1) -+#define NUM_LONG_TERM_REF_PICS_SPS PS_FIELD(92, 6) -+#define SPS_TEMPORAL_MVP_ENABLED_FLAG PS_FIELD(98, 1) -+#define STRONG_INTRA_SMOOTHING_ENABLED_FLAG PS_FIELD(99, 1) -+/* PPS */ -+#define PIC_PARAMETER_SET_ID PS_FIELD(128, 6) -+#define PPS_SEQ_PARAMETER_SET_ID PS_FIELD(134, 4) -+#define DEPENDENT_SLICE_SEGMENTS_ENABLED_FLAG PS_FIELD(138, 1) -+#define OUTPUT_FLAG_PRESENT_FLAG PS_FIELD(139, 1) -+#define NUM_EXTRA_SLICE_HEADER_BITS PS_FIELD(140, 13) -+#define SIGN_DATA_HIDING_ENABLED_FLAG PS_FIELD(153, 1) -+#define CABAC_INIT_PRESENT_FLAG PS_FIELD(154, 1) -+#define NUM_REF_IDX_L0_DEFAULT_ACTIVE PS_FIELD(155, 4) -+#define NUM_REF_IDX_L1_DEFAULT_ACTIVE PS_FIELD(159, 4) -+#define INIT_QP_MINUS26 PS_FIELD(163, 7) -+#define CONSTRAINED_INTRA_PRED_FLAG PS_FIELD(170, 1) -+#define TRANSFORM_SKIP_ENABLED_FLAG PS_FIELD(171, 1) -+#define CU_QP_DELTA_ENABLED_FLAG PS_FIELD(172, 1) -+#define LOG2_MIN_CU_QP_DELTA_SIZE PS_FIELD(173, 3) -+#define PPS_CB_QP_OFFSET PS_FIELD(176, 5) -+#define PPS_CR_QP_OFFSET PS_FIELD(181, 5) -+#define PPS_SLICE_CHROMA_QP_OFFSETS_PRESENT_FLAG PS_FIELD(186, 1) -+#define WEIGHTED_PRED_FLAG PS_FIELD(187, 1) -+#define WEIGHTED_BIPRED_FLAG PS_FIELD(188, 1) -+#define TRANSQUANT_BYPASS_ENABLED_FLAG PS_FIELD(189, 1) -+#define TILES_ENABLED_FLAG PS_FIELD(190, 1) -+#define ENTROPY_CODING_SYNC_ENABLED_FLAG PS_FIELD(191, 1) -+#define PPS_LOOP_FILTER_ACROSS_SLICES_ENABLED_FLAG PS_FIELD(192, 1) -+#define LOOP_FILTER_ACROSS_TILES_ENABLED_FLAG PS_FIELD(193, 1) -+#define DEBLOCKING_FILTER_OVERRIDE_ENABLED_FLAG PS_FIELD(194, 1) -+#define PPS_DEBLOCKING_FILTER_DISABLED_FLAG PS_FIELD(195, 1) -+#define PPS_BETA_OFFSET_DIV2 PS_FIELD(196, 4) -+#define PPS_TC_OFFSET_DIV2 PS_FIELD(200, 4) -+#define LISTS_MODIFICATION_PRESENT_FLAG PS_FIELD(204, 1) -+#define LOG2_PARALLEL_MERGE_LEVEL PS_FIELD(205, 3) -+#define SLICE_SEGMENT_HEADER_EXTENSION_PRESENT_FLAG PS_FIELD(208, 1) -+#define NUM_TILE_COLUMNS PS_FIELD(212, 5) -+#define NUM_TILE_ROWS PS_FIELD(217, 5) -+#define COLUMN_WIDTH(i) PS_FIELD(256 + (i * 8), 8) -+#define ROW_HEIGHT(i) PS_FIELD(416 + (i * 8), 8) -+#define SCALING_LIST_ADDRESS PS_FIELD(592, 32) -+ -+/* Data structure describing auxiliary buffer format. */ -+struct rkvdec_hevc_priv_tbl { -+ u8 cabac_table[RKV_CABAC_TABLE_SIZE]; -+ u8 scaling_list[RKV_SCALING_LIST_SIZE]; -+ struct rkvdec_sps_pps_packet param_set[RKV_PPS_LEN]; -+ struct rkvdec_rps_packet rps[RKV_RPS_LEN]; -+}; -+ -+struct rkvdec_hevc_run { -+ struct rkvdec_run base; -+ const struct v4l2_ctrl_hevc_slice_params *slices_params; -+ const struct v4l2_ctrl_hevc_decode_params *decode_params; -+ const struct v4l2_ctrl_hevc_sps *sps; -+ const struct v4l2_ctrl_hevc_pps *pps; -+ const struct v4l2_ctrl_hevc_scaling_matrix *scaling_matrix; -+ int num_slices; -+}; -+ -+struct rkvdec_hevc_ctx { -+ struct rkvdec_aux_buf priv_tbl; -+ struct v4l2_ctrl_hevc_scaling_matrix scaling_matrix_cache; -+}; -+ -+// TODO: refactor scaling list code, was copied 1:1 from mpp -+ -+typedef struct ScalingList { -+ /* This is a little wasteful, since sizeID 0 only needs 8 coeffs, -+ * and size ID 3 only has 2 arrays, not 6. */ -+ u8 sl[4][6][64]; -+ u8 sl_dc[2][6]; -+} scalingList_t; -+ -+typedef struct ScalingFactor_Model { -+ u8 scalingfactor0[1248]; -+ u8 scalingfactor1[96]; /*4X4 TU Rotate, total 16X4*/ -+ u8 scalingdc[12]; /*N1005 Vienna Meeting*/ -+ u8 reserverd[4]; /*16Bytes align*/ -+} scalingFactor_t; -+ -+#define SCALING_LIST_SIZE_NUM 4 -+ -+static void -+hal_record_scaling_list(scalingFactor_t *pScalingFactor_out, -+ scalingList_t *pScalingList) -+{ -+ int i; -+ u32 g_scalingListNum_model[SCALING_LIST_SIZE_NUM] = {6, 6, 6, 2}; // from C Model -+ u32 nIndex = 0; -+ u32 sizeId, matrixId, listId; -+ u8 *p = pScalingFactor_out->scalingfactor0; -+ u8 tmpBuf[8 * 8]; -+ -+ //output non-default scalingFactor Table (1248 BYTES) -+ for (sizeId = 0; sizeId < SCALING_LIST_SIZE_NUM; sizeId++) { -+ for (listId = 0; listId < g_scalingListNum_model[sizeId]; listId++) { -+ if (sizeId < 3) { -+ for (i = 0; i < (sizeId == 0 ? 16 : 64); i++) { -+ pScalingFactor_out->scalingfactor0[nIndex++] = (u8)pScalingList->sl[sizeId][listId][i]; -+ } -+ } else { -+ for (i = 0; i < 64; i ++) { -+ pScalingFactor_out->scalingfactor0[nIndex++] = (u8)pScalingList->sl[sizeId][listId][i]; -+ } -+ for (i = 0; i < 128; i ++) { -+ pScalingFactor_out->scalingfactor0[nIndex++] = 0; -+ } -+ } -+ } -+ } -+ //output non-default scalingFactor Table Rotation(96 Bytes) -+ nIndex = 0; -+ for (listId = 0; listId < g_scalingListNum_model[0]; listId++) { -+ u8 temp16[16] = {0}; -+ for (i = 0; i < 16; i ++) { -+ temp16[i] = (u8)pScalingList->sl[0][listId][i]; -+ } -+ for (i = 0; i < 4; i ++) { -+ pScalingFactor_out->scalingfactor1[nIndex++] = temp16[i]; -+ pScalingFactor_out->scalingfactor1[nIndex++] = temp16[i + 4]; -+ pScalingFactor_out->scalingfactor1[nIndex++] = temp16[i + 8]; -+ pScalingFactor_out->scalingfactor1[nIndex++] = temp16[i + 12]; -+ } -+ } -+ //output non-default ScalingList_DC_Coeff (12 BYTES) -+ nIndex = 0; -+ for (listId = 0; listId < g_scalingListNum_model[2]; listId++) { //sizeId = 2 -+ pScalingFactor_out->scalingdc[nIndex++] = (u8)pScalingList->sl_dc[0][listId];// zrh warning: sl_dc differed from scalingList->getScalingListDC -+ } -+ for (listId = 0; listId < g_scalingListNum_model[3]; listId++) { //sizeId = 3 -+ pScalingFactor_out->scalingdc[nIndex++] = (u8)pScalingList->sl_dc[1][listId];// zrh warning: sl_dc differed from scalingList->getScalingListDC -+ pScalingFactor_out->scalingdc[nIndex++] = 0; -+ pScalingFactor_out->scalingdc[nIndex++] = 0; -+ } -+ -+ //align 16X address -+ nIndex = 0; -+ for (i = 0; i < 4; i ++) { -+ pScalingFactor_out->reserverd[nIndex++] = 0; -+ } -+ -+ //----------------------All above code show the normal store way in HM-------------------------- -+ //--------from now on, the scalingfactor0 is rotated 90', the scalingfactor1 is also rotated 90' -+ -+ //sizeId == 0 -+ for (matrixId = 0; matrixId < 6; matrixId++) { -+ p = pScalingFactor_out->scalingfactor0 + matrixId * 16; -+ -+ for (i = 0; i < 4; i++) { -+ tmpBuf[4 * 0 + i] = p[i * 4 + 0]; -+ tmpBuf[4 * 1 + i] = p[i * 4 + 1]; -+ tmpBuf[4 * 2 + i] = p[i * 4 + 2]; -+ tmpBuf[4 * 3 + i] = p[i * 4 + 3]; -+ } -+ memcpy(p, tmpBuf, 4 * 4 * sizeof(u8)); -+ } -+ //sizeId == 1 -+ for (matrixId = 0; matrixId < 6; matrixId++) { -+ p = pScalingFactor_out->scalingfactor0 + 6 * 16 + matrixId * 64; -+ -+ for (i = 0; i < 8; i++) { -+ tmpBuf[8 * 0 + i] = p[i * 8 + 0]; -+ tmpBuf[8 * 1 + i] = p[i * 8 + 1]; -+ tmpBuf[8 * 2 + i] = p[i * 8 + 2]; -+ tmpBuf[8 * 3 + i] = p[i * 8 + 3]; -+ tmpBuf[8 * 4 + i] = p[i * 8 + 4]; -+ tmpBuf[8 * 5 + i] = p[i * 8 + 5]; -+ tmpBuf[8 * 6 + i] = p[i * 8 + 6]; -+ tmpBuf[8 * 7 + i] = p[i * 8 + 7]; -+ } -+ memcpy(p, tmpBuf, 8 * 8 * sizeof(u8)); -+ } -+ //sizeId == 2 -+ for (matrixId = 0; matrixId < 6; matrixId++) { -+ p = pScalingFactor_out->scalingfactor0 + 6 * 16 + 6 * 64 + matrixId * 64; -+ -+ for (i = 0; i < 8; i++) { -+ tmpBuf[8 * 0 + i] = p[i * 8 + 0]; -+ tmpBuf[8 * 1 + i] = p[i * 8 + 1]; -+ tmpBuf[8 * 2 + i] = p[i * 8 + 2]; -+ tmpBuf[8 * 3 + i] = p[i * 8 + 3]; -+ tmpBuf[8 * 4 + i] = p[i * 8 + 4]; -+ tmpBuf[8 * 5 + i] = p[i * 8 + 5]; -+ tmpBuf[8 * 6 + i] = p[i * 8 + 6]; -+ tmpBuf[8 * 7 + i] = p[i * 8 + 7]; -+ } -+ memcpy(p, tmpBuf, 8 * 8 * sizeof(u8)); -+ } -+ //sizeId == 3 -+ for (matrixId = 0; matrixId < 6; matrixId++) { -+ p = pScalingFactor_out->scalingfactor0 + 6 * 16 + 6 * 64 + 6 * 64 + matrixId * 64; -+ -+ for (i = 0; i < 8; i++) { -+ tmpBuf[8 * 0 + i] = p[i * 8 + 0]; -+ tmpBuf[8 * 1 + i] = p[i * 8 + 1]; -+ tmpBuf[8 * 2 + i] = p[i * 8 + 2]; -+ tmpBuf[8 * 3 + i] = p[i * 8 + 3]; -+ tmpBuf[8 * 4 + i] = p[i * 8 + 4]; -+ tmpBuf[8 * 5 + i] = p[i * 8 + 5]; -+ tmpBuf[8 * 6 + i] = p[i * 8 + 6]; -+ tmpBuf[8 * 7 + i] = p[i * 8 + 7]; -+ } -+ memcpy(p, tmpBuf, 8 * 8 * sizeof(u8)); -+ } -+ -+ //sizeId == 0 -+ for (matrixId = 0; matrixId < 6; matrixId++) { -+ p = pScalingFactor_out->scalingfactor1 + matrixId * 16; -+ -+ for (i = 0; i < 4; i++) { -+ tmpBuf[4 * 0 + i] = p[i * 4 + 0]; -+ tmpBuf[4 * 1 + i] = p[i * 4 + 1]; -+ tmpBuf[4 * 2 + i] = p[i * 4 + 2]; -+ tmpBuf[4 * 3 + i] = p[i * 4 + 3]; -+ } -+ memcpy(p, tmpBuf, 4 * 4 * sizeof(u8)); -+ } -+} -+ -+static const u8 rkvdec_hevc_cabac_table[RKV_CABAC_TABLE_SIZE] = { -+ 0x07, 0x0f, 0x48, 0x58, 0x58, 0x40, 0x40, 0x40, 0x40, 0x40, 0x0f, 0x40, 0x40, 0x40, 0x0f, 0x68, -+ 0x48, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x07, 0x40, 0x40, 0x68, -+ 0x58, 0x60, 0x40, 0x1f, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x48, 0x48, 0x60, 0x60, 0x50, 0x58, -+ 0x50, 0x07, 0x58, 0x68, 0x50, 0x58, 0x68, 0x68, 0x68, 0x68, 0x68, 0x50, 0x48, 0x68, 0x60, 0x60, -+ 0x50, 0x58, 0x50, 0x07, 0x58, 0x68, 0x50, 0x58, 0x68, 0x68, 0x68, 0x68, 0x68, 0x50, 0x48, 0x68, -+ 0x48, 0x48, 0x1f, 0x58, 0x68, 0x68, 0x58, 0x60, 0x60, 0x60, 0x50, 0x50, 0x50, 0x48, 0x58, 0x58, -+ 0x37, 0x07, 0x58, 0x48, 0x58, 0x58, 0x37, 0x07, 0x58, 0x48, 0x58, 0x58, 0x37, 0x07, 0x58, 0x50, -+ 0x48, 0x1f, 0x1f, 0x0f, 0x0f, 0x0f, 0x0f, 0x07, 0x0f, 0x48, 0x68, 0x0f, 0x48, 0x68, 0x40, 0x40, -+ 0x50, 0x50, 0x07, 0x40, 0x50, 0x0f, 0x40, 0x48, 0x07, 0x40, 0x27, 0x50, 0x48, 0x48, 0x40, 0x0f, -+ 0x50, 0x37, 0x1f, 0x1f, 0x50, 0x37, 0x40, 0x27, 0x40, 0x07, 0x0f, 0x17, 0x0f, 0x0f, 0x40, 0x40, -+ 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x07, 0x0f, 0x47, 0x57, 0x58, 0x40, 0x40, 0x40, 0x40, 0x40, 0x0f, 0x40, 0x40, 0x40, 0x0f, 0x66, -+ 0x47, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x07, 0x00, 0x00, 0x67, -+ 0x57, 0x5e, 0x00, 0x1f, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x47, 0x47, 0x5f, 0x5f, 0x4f, 0x57, -+ 0x4f, 0x07, 0x57, 0x67, 0x4f, 0x57, 0x67, 0x67, 0x67, 0x67, 0x66, 0x4f, 0x47, 0x66, 0x5f, 0x5f, -+ 0x4f, 0x57, 0x4f, 0x07, 0x57, 0x67, 0x4f, 0x57, 0x67, 0x67, 0x67, 0x67, 0x66, 0x4f, 0x47, 0x66, -+ 0x46, 0x48, 0x20, 0x57, 0x67, 0x67, 0x57, 0x5f, 0x5f, 0x5e, 0x4f, 0x4f, 0x4f, 0x47, 0x57, 0x57, -+ 0x37, 0x07, 0x57, 0x47, 0x57, 0x57, 0x37, 0x07, 0x57, 0x47, 0x57, 0x57, 0x37, 0x07, 0x57, 0x4f, -+ 0x47, 0x1f, 0x1f, 0x0f, 0x10, 0x0f, 0x10, 0x07, 0x10, 0x47, 0x67, 0x10, 0x47, 0x67, 0x40, 0x40, -+ 0x4f, 0x4e, 0x08, 0x00, 0x4f, 0x0f, 0x00, 0x47, 0x07, 0x01, 0x27, 0x4e, 0x47, 0x47, 0x00, 0x0f, -+ 0x4f, 0x37, 0x1f, 0x1f, 0x4f, 0x36, 0x00, 0x27, 0x00, 0x07, 0x10, 0x17, 0x0f, 0x0f, 0x40, 0x40, -+ 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 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0x1f, 0x27, 0x08, 0x17, 0x47, 0x40, 0x17, 0x47, 0x40, 0x40, 0x40, -+ 0x40, 0x00, 0x08, 0x08, 0x40, 0x0f, 0x08, 0x00, 0x00, 0x2f, 0x27, 0x1f, 0x07, 0x27, 0x1f, 0x1f, -+ 0x47, 0x10, 0x10, 0x08, 0x40, 0x0f, 0x08, 0x00, 0x27, 0x08, 0x37, 0x27, 0x27, 0x08, 0x40, 0x40, -+ 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+}; -+ -+static void set_ps_field(u32 *buf, struct rkvdec_ps_field field, u32 value) -+{ -+ u8 bit = field.offset % 32, word = field.offset / 32; -+ u64 mask = GENMASK_ULL(bit + field.len - 1, bit); -+ u64 val = ((u64)value << bit) & mask; -+ -+ buf[word] &= ~mask; -+ buf[word] |= val; -+ if (bit + field.len > 32) { -+ buf[word + 1] &= ~(mask >> 32); -+ buf[word + 1] |= val >> 32; -+ } -+} -+ -+static void assemble_hw_pps(struct rkvdec_ctx *ctx, -+ struct rkvdec_hevc_run *run) -+{ -+ struct rkvdec_hevc_ctx *hevc_ctx = ctx->priv; -+ const struct v4l2_ctrl_hevc_sps *sps = run->sps; -+ const struct v4l2_ctrl_hevc_pps *pps = run->pps; -+ struct rkvdec_hevc_priv_tbl *priv_tbl = hevc_ctx->priv_tbl.cpu; -+ struct rkvdec_sps_pps_packet *hw_ps; -+ u32 min_cb_log2_size_y, ctb_log2_size_y, ctb_size_y; -+ u32 log2_min_cu_qp_delta_size; -+ dma_addr_t scaling_list_address; -+ u32 scaling_distance; -+ int i; -+ -+ /* -+ * HW read the SPS/PPS information from PPS packet index by PPS id. -+ * offset from the base can be calculated by PPS_id * 80 (size per PPS -+ * packet unit). so the driver copy SPS/PPS information to the exact PPS -+ * packet unit for HW accessing. -+ */ -+ hw_ps = &priv_tbl->param_set[pps->pic_parameter_set_id]; -+ memset(hw_ps, 0, sizeof(*hw_ps)); -+ -+ min_cb_log2_size_y = sps->log2_min_luma_coding_block_size_minus3 + 3; -+ ctb_log2_size_y = min_cb_log2_size_y + -+ sps->log2_diff_max_min_luma_coding_block_size; -+ ctb_size_y = 1 << ctb_log2_size_y; -+ -+#define WRITE_PPS(value, field) set_ps_field(hw_ps->info, field, value) -+ /* write sps */ -+ WRITE_PPS(sps->video_parameter_set_id, VIDEO_PARAMETER_SET_ID); -+ WRITE_PPS(sps->seq_parameter_set_id, SEQ_PARAMETER_SET_ID); -+ WRITE_PPS(sps->chroma_format_idc, CHROMA_FORMAT_IDC); -+ WRITE_PPS(sps->pic_width_in_luma_samples, PIC_WIDTH_IN_LUMA_SAMPLES); -+ WRITE_PPS(sps->pic_height_in_luma_samples, PIC_HEIGHT_IN_LUMA_SAMPLES); -+ WRITE_PPS(sps->bit_depth_luma_minus8 + 8, BIT_DEPTH_LUMA); -+ WRITE_PPS(sps->bit_depth_chroma_minus8 + 8, BIT_DEPTH_CHROMA); -+ WRITE_PPS(sps->log2_max_pic_order_cnt_lsb_minus4 + 4, -+ LOG2_MAX_PIC_ORDER_CNT_LSB); -+ WRITE_PPS(sps->log2_diff_max_min_luma_coding_block_size, -+ LOG2_DIFF_MAX_MIN_LUMA_CODING_BLOCK_SIZE); -+ WRITE_PPS(sps->log2_min_luma_coding_block_size_minus3 + 3, -+ LOG2_MIN_LUMA_CODING_BLOCK_SIZE); -+ WRITE_PPS(sps->log2_min_luma_transform_block_size_minus2 + 2, -+ LOG2_MIN_TRANSFORM_BLOCK_SIZE); -+ WRITE_PPS(sps->log2_diff_max_min_luma_transform_block_size, -+ LOG2_DIFF_MAX_MIN_LUMA_TRANSFORM_BLOCK_SIZE); -+ WRITE_PPS(sps->max_transform_hierarchy_depth_inter, -+ MAX_TRANSFORM_HIERARCHY_DEPTH_INTER); -+ WRITE_PPS(sps->max_transform_hierarchy_depth_intra, -+ MAX_TRANSFORM_HIERARCHY_DEPTH_INTRA); -+ WRITE_PPS(!!(sps->flags & V4L2_HEVC_SPS_FLAG_SCALING_LIST_ENABLED), -+ SCALING_LIST_ENABLED_FLAG); -+ WRITE_PPS(!!(sps->flags & V4L2_HEVC_SPS_FLAG_AMP_ENABLED), -+ AMP_ENABLED_FLAG); -+ WRITE_PPS(!!(sps->flags & V4L2_HEVC_SPS_FLAG_SAMPLE_ADAPTIVE_OFFSET), -+ SAMPLE_ADAPTIVE_OFFSET_ENABLED_FLAG); -+ if (sps->flags & V4L2_HEVC_SPS_FLAG_PCM_ENABLED) { -+ WRITE_PPS(1, PCM_ENABLED_FLAG); -+ WRITE_PPS(sps->pcm_sample_bit_depth_luma_minus1 + 1, -+ PCM_SAMPLE_BIT_DEPTH_LUMA); -+ WRITE_PPS(sps->pcm_sample_bit_depth_chroma_minus1 + 1, -+ PCM_SAMPLE_BIT_DEPTH_CHROMA); -+ WRITE_PPS(!!(sps->flags & V4L2_HEVC_SPS_FLAG_PCM_LOOP_FILTER_DISABLED), -+ PCM_LOOP_FILTER_DISABLED_FLAG); -+ WRITE_PPS(sps->log2_diff_max_min_pcm_luma_coding_block_size, -+ LOG2_DIFF_MAX_MIN_PCM_LUMA_CODING_BLOCK_SIZE); -+ WRITE_PPS(sps->log2_min_pcm_luma_coding_block_size_minus3 + 3, -+ LOG2_MIN_PCM_LUMA_CODING_BLOCK_SIZE); -+ } -+ WRITE_PPS(sps->num_short_term_ref_pic_sets, NUM_SHORT_TERM_REF_PIC_SETS); -+ WRITE_PPS(!!(sps->flags & V4L2_HEVC_SPS_FLAG_LONG_TERM_REF_PICS_PRESENT), -+ LONG_TERM_REF_PICS_PRESENT_FLAG); -+ WRITE_PPS(sps->num_long_term_ref_pics_sps, NUM_LONG_TERM_REF_PICS_SPS); -+ WRITE_PPS(!!(sps->flags & V4L2_HEVC_SPS_FLAG_SPS_TEMPORAL_MVP_ENABLED), -+ SPS_TEMPORAL_MVP_ENABLED_FLAG); -+ WRITE_PPS(!!(sps->flags & V4L2_HEVC_SPS_FLAG_STRONG_INTRA_SMOOTHING_ENABLED), -+ STRONG_INTRA_SMOOTHING_ENABLED_FLAG); -+ -+ /* write pps */ -+ WRITE_PPS(pps->pic_parameter_set_id, PIC_PARAMETER_SET_ID); -+ WRITE_PPS(sps->seq_parameter_set_id, PPS_SEQ_PARAMETER_SET_ID); -+ WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_DEPENDENT_SLICE_SEGMENT_ENABLED), -+ DEPENDENT_SLICE_SEGMENTS_ENABLED_FLAG); -+ WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_OUTPUT_FLAG_PRESENT), -+ OUTPUT_FLAG_PRESENT_FLAG); -+ WRITE_PPS(pps->num_extra_slice_header_bits, NUM_EXTRA_SLICE_HEADER_BITS); -+ WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_SIGN_DATA_HIDING_ENABLED), -+ SIGN_DATA_HIDING_ENABLED_FLAG); -+ WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_CABAC_INIT_PRESENT), -+ CABAC_INIT_PRESENT_FLAG); -+ WRITE_PPS(pps->num_ref_idx_l0_default_active_minus1 + 1, -+ NUM_REF_IDX_L0_DEFAULT_ACTIVE); -+ WRITE_PPS(pps->num_ref_idx_l1_default_active_minus1 + 1, -+ NUM_REF_IDX_L1_DEFAULT_ACTIVE); -+ WRITE_PPS(pps->init_qp_minus26, INIT_QP_MINUS26); -+ WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_CONSTRAINED_INTRA_PRED), -+ CONSTRAINED_INTRA_PRED_FLAG); -+ WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_TRANSFORM_SKIP_ENABLED), -+ TRANSFORM_SKIP_ENABLED_FLAG); -+ WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_CU_QP_DELTA_ENABLED), -+ CU_QP_DELTA_ENABLED_FLAG); -+ -+ log2_min_cu_qp_delta_size = ctb_log2_size_y - pps->diff_cu_qp_delta_depth; -+ WRITE_PPS(log2_min_cu_qp_delta_size, LOG2_MIN_CU_QP_DELTA_SIZE); -+ -+ WRITE_PPS(pps->pps_cb_qp_offset, PPS_CB_QP_OFFSET); -+ WRITE_PPS(pps->pps_cr_qp_offset, PPS_CR_QP_OFFSET); -+ WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_PPS_SLICE_CHROMA_QP_OFFSETS_PRESENT), -+ PPS_SLICE_CHROMA_QP_OFFSETS_PRESENT_FLAG); -+ WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_WEIGHTED_PRED), -+ WEIGHTED_PRED_FLAG); -+ WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_WEIGHTED_BIPRED), -+ WEIGHTED_BIPRED_FLAG); -+ WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_TRANSQUANT_BYPASS_ENABLED), -+ TRANSQUANT_BYPASS_ENABLED_FLAG); -+ WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_TILES_ENABLED), -+ TILES_ENABLED_FLAG); -+ WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_ENTROPY_CODING_SYNC_ENABLED), -+ ENTROPY_CODING_SYNC_ENABLED_FLAG); -+ WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_PPS_LOOP_FILTER_ACROSS_SLICES_ENABLED), -+ PPS_LOOP_FILTER_ACROSS_SLICES_ENABLED_FLAG); -+ WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_LOOP_FILTER_ACROSS_TILES_ENABLED), -+ LOOP_FILTER_ACROSS_TILES_ENABLED_FLAG); -+ WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_DEBLOCKING_FILTER_OVERRIDE_ENABLED), -+ DEBLOCKING_FILTER_OVERRIDE_ENABLED_FLAG); -+ WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_PPS_DISABLE_DEBLOCKING_FILTER), -+ PPS_DEBLOCKING_FILTER_DISABLED_FLAG); -+ WRITE_PPS(pps->pps_beta_offset_div2, PPS_BETA_OFFSET_DIV2); -+ WRITE_PPS(pps->pps_tc_offset_div2, PPS_TC_OFFSET_DIV2); -+ WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_LISTS_MODIFICATION_PRESENT), -+ LISTS_MODIFICATION_PRESENT_FLAG); -+ WRITE_PPS(pps->log2_parallel_merge_level_minus2 + 2, LOG2_PARALLEL_MERGE_LEVEL); -+ WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_SLICE_SEGMENT_HEADER_EXTENSION_PRESENT), -+ SLICE_SEGMENT_HEADER_EXTENSION_PRESENT_FLAG); -+ WRITE_PPS(pps->num_tile_columns_minus1 + 1, NUM_TILE_COLUMNS); -+ WRITE_PPS(pps->num_tile_rows_minus1 + 1, NUM_TILE_ROWS); -+ -+ if (pps->flags & V4L2_HEVC_PPS_FLAG_TILES_ENABLED) { -+ for (i = 0; i <= pps->num_tile_columns_minus1; i++) -+ WRITE_PPS(pps->column_width_minus1[i], COLUMN_WIDTH(i)); -+ for (i = 0; i <= pps->num_tile_rows_minus1; i++) -+ WRITE_PPS(pps->row_height_minus1[i], ROW_HEIGHT(i)); -+ } else { -+ WRITE_PPS(((sps->pic_width_in_luma_samples + ctb_size_y - 1) / ctb_size_y) - 1, -+ COLUMN_WIDTH(0)); -+ WRITE_PPS(((sps->pic_height_in_luma_samples + ctb_size_y - 1) / ctb_size_y) - 1, -+ ROW_HEIGHT(0)); -+ } -+ -+ scaling_distance = offsetof(struct rkvdec_hevc_priv_tbl, scaling_list); -+ scaling_list_address = hevc_ctx->priv_tbl.dma + scaling_distance; -+ WRITE_PPS(scaling_list_address, SCALING_LIST_ADDRESS); -+} -+ -+static void assemble_hw_rps(struct rkvdec_ctx *ctx, -+ struct rkvdec_hevc_run *run) -+{ -+ const struct v4l2_ctrl_hevc_decode_params *decode_params = run->decode_params; -+ const struct v4l2_ctrl_hevc_slice_params *sl_params; -+ const struct v4l2_hevc_dpb_entry *dpb; -+ struct rkvdec_hevc_ctx *hevc_ctx = ctx->priv; -+ struct rkvdec_hevc_priv_tbl *priv_tbl = hevc_ctx->priv_tbl.cpu; -+ struct rkvdec_rps_packet *hw_ps; -+ int i, j; -+ unsigned int lowdelay; -+ -+#define WRITE_RPS(value, field) set_ps_field(hw_ps->info, field, value) -+ -+#define REF_PIC_LONG_TERM_L0(i) PS_FIELD(i * 5, 1) -+#define REF_PIC_IDX_L0(i) PS_FIELD(1 + (i * 5), 4) -+#define REF_PIC_LONG_TERM_L1(i) PS_FIELD((i < 5 ? 75 : 132) + (i * 5), 1) -+#define REF_PIC_IDX_L1(i) PS_FIELD((i < 4 ? 76 : 128) + (i * 5), 4) -+ -+#define LOWDELAY PS_FIELD(182, 1) -+#define LONG_TERM_RPS_BIT_OFFSET PS_FIELD(183, 10) -+#define SHORT_TERM_RPS_BIT_OFFSET PS_FIELD(193, 9) -+#define NUM_RPS_POC PS_FIELD(202, 4) -+ -+ for (j = 0; j < run->num_slices; j++) { -+ sl_params = &run->slices_params[j]; -+ dpb = decode_params->dpb; -+ lowdelay = (sl_params->slice_type == V4L2_HEVC_SLICE_TYPE_I) ? 0 : 1; -+ -+ hw_ps = &priv_tbl->rps[j]; -+ memset(hw_ps, 0, sizeof(*hw_ps)); -+ -+ for (i = 0; i <= sl_params->num_ref_idx_l0_active_minus1; i++) { -+ WRITE_RPS(!!(dpb[sl_params->ref_idx_l0[i]].flags & V4L2_HEVC_DPB_ENTRY_LONG_TERM_REFERENCE), -+ REF_PIC_LONG_TERM_L0(i)); -+ WRITE_RPS(sl_params->ref_idx_l0[i], REF_PIC_IDX_L0(i)); -+ -+ if (dpb[sl_params->ref_idx_l0[i]].pic_order_cnt_val > sl_params->slice_pic_order_cnt) -+ lowdelay = 0; -+ -+ } -+ -+ for (i = 0; i <= sl_params->num_ref_idx_l1_active_minus1; i++) { -+ WRITE_RPS(!!(dpb[sl_params->ref_idx_l1[i]].flags & V4L2_HEVC_DPB_ENTRY_LONG_TERM_REFERENCE), -+ REF_PIC_LONG_TERM_L1(i)); -+ WRITE_RPS(sl_params->ref_idx_l1[i], REF_PIC_IDX_L1(i)); -+ -+ if (dpb[sl_params->ref_idx_l1[i]].pic_order_cnt_val > sl_params->slice_pic_order_cnt) -+ lowdelay = 0; -+ } -+ -+ WRITE_RPS(lowdelay, LOWDELAY); -+ -+ WRITE_RPS(sl_params->long_term_ref_pic_set_size + -+ sl_params->short_term_ref_pic_set_size, -+ LONG_TERM_RPS_BIT_OFFSET); -+ WRITE_RPS(sl_params->short_term_ref_pic_set_size, -+ SHORT_TERM_RPS_BIT_OFFSET); -+ -+ WRITE_RPS(decode_params->num_poc_st_curr_before + -+ decode_params->num_poc_st_curr_after + -+ decode_params->num_poc_lt_curr, -+ NUM_RPS_POC); -+ } -+} -+ -+static void assemble_hw_scaling_list(struct rkvdec_ctx *ctx, -+ struct rkvdec_hevc_run *run) -+{ -+ const struct v4l2_ctrl_hevc_scaling_matrix *scaling = run->scaling_matrix; -+ struct rkvdec_hevc_ctx *hevc_ctx = ctx->priv; -+ struct rkvdec_hevc_priv_tbl *tbl = hevc_ctx->priv_tbl.cpu; -+ u8 *dst; -+ scalingList_t sl; -+ int i, j; -+ -+ if (!memcmp((void*)&hevc_ctx->scaling_matrix_cache, scaling, -+ sizeof(struct v4l2_ctrl_hevc_scaling_matrix))) -+ return; -+ -+ memset(&sl, 0, sizeof(scalingList_t)); -+ -+ for (i = 0; i < 6; i++) { -+ for (j = 0; j < 16; j++) -+ sl.sl[0][i][j] = scaling->scaling_list_4x4[i][j]; -+ for (j = 0; j < 64; j++) { -+ sl.sl[1][i][j] = scaling->scaling_list_8x8[i][j]; -+ sl.sl[2][i][j] = scaling->scaling_list_16x16[i][j]; -+ if (i < 2) -+ sl.sl[3][i][j] = scaling->scaling_list_32x32[i][j]; -+ } -+ sl.sl_dc[0][i] = scaling->scaling_list_dc_coef_16x16[i]; -+ if (i < 2) -+ sl.sl_dc[1][i] = scaling->scaling_list_dc_coef_32x32[i]; -+ } -+ -+ dst = tbl->scaling_list; -+ hal_record_scaling_list((scalingFactor_t *)dst, &sl); -+ -+ memcpy((void*)&hevc_ctx->scaling_matrix_cache, scaling, -+ sizeof(struct v4l2_ctrl_hevc_scaling_matrix)); -+} -+ -+static struct vb2_buffer * -+get_ref_buf(struct rkvdec_ctx *ctx, struct rkvdec_hevc_run *run, -+ unsigned int dpb_idx) -+{ -+ struct v4l2_m2m_ctx *m2m_ctx = ctx->fh.m2m_ctx; -+ const struct v4l2_ctrl_hevc_decode_params *decode_params = run->decode_params; -+ const struct v4l2_hevc_dpb_entry *dpb = decode_params->dpb; -+ struct vb2_queue *cap_q = &m2m_ctx->cap_q_ctx.q; -+ struct vb2_buffer *vb2_buf = NULL; -+ -+ if (dpb_idx < decode_params->num_active_dpb_entries) -+ vb2_buf = vb2_find_buffer(cap_q, dpb[dpb_idx].timestamp); -+ -+ /* -+ * If a DPB entry is unused or invalid, address of current destination -+ * buffer is returned. -+ */ -+ if (!vb2_buf) -+ return &run->base.bufs.dst->vb2_buf; -+ -+ return vb2_buf; -+} -+ -+static void config_registers(struct rkvdec_ctx *ctx, -+ struct rkvdec_hevc_run *run) -+{ -+ struct rkvdec_dev *rkvdec = ctx->dev; -+ const struct v4l2_ctrl_hevc_decode_params *decode_params = run->decode_params; -+ const struct v4l2_ctrl_hevc_slice_params *sl_params = &run->slices_params[0]; -+ const struct v4l2_hevc_dpb_entry *dpb = decode_params->dpb; -+ struct rkvdec_hevc_ctx *hevc_ctx = ctx->priv; -+ dma_addr_t priv_start_addr = hevc_ctx->priv_tbl.dma; -+ const struct v4l2_pix_format_mplane *dst_fmt; -+ struct vb2_v4l2_buffer *src_buf = run->base.bufs.src; -+ struct vb2_v4l2_buffer *dst_buf = run->base.bufs.dst; -+ const struct v4l2_format *f; -+ dma_addr_t rlc_addr; -+ dma_addr_t refer_addr; -+ u32 rlc_len; -+ u32 hor_virstride; -+ u32 ver_virstride; -+ u32 y_virstride; -+ u32 uv_virstride; -+ u32 yuv_virstride; -+ u32 offset; -+ dma_addr_t dst_addr; -+ u32 reg, i; -+ -+ reg = RKVDEC_MODE(RKVDEC_MODE_HEVC); -+ writel_relaxed(reg, rkvdec->regs + RKVDEC_REG_SYSCTRL); -+ -+ f = &ctx->decoded_fmt; -+ dst_fmt = &f->fmt.pix_mp; -+ hor_virstride = dst_fmt->plane_fmt[0].bytesperline; -+ ver_virstride = dst_fmt->height; -+ y_virstride = hor_virstride * ver_virstride; -+ uv_virstride = y_virstride / 2; -+ yuv_virstride = y_virstride + uv_virstride; -+ -+ reg = RKVDEC_Y_HOR_VIRSTRIDE(hor_virstride / 16) | -+ RKVDEC_UV_HOR_VIRSTRIDE(hor_virstride / 16) | -+ RKVDEC_SLICE_NUM_LOWBITS(run->num_slices); -+ writel_relaxed(reg, rkvdec->regs + RKVDEC_REG_PICPAR); -+ -+ /* config rlc base address */ -+ rlc_addr = vb2_dma_contig_plane_dma_addr(&src_buf->vb2_buf, 0); -+ writel_relaxed(rlc_addr, rkvdec->regs + RKVDEC_REG_STRM_RLC_BASE); -+ -+ rlc_len = vb2_get_plane_payload(&src_buf->vb2_buf, 0); -+ reg = RKVDEC_STRM_LEN(round_up(rlc_len, 16) + 64); -+ writel_relaxed(reg, rkvdec->regs + RKVDEC_REG_STRM_LEN); -+ -+ /* config cabac table */ -+ offset = offsetof(struct rkvdec_hevc_priv_tbl, cabac_table); -+ writel_relaxed(priv_start_addr + offset, -+ rkvdec->regs + RKVDEC_REG_CABACTBL_PROB_BASE); -+ -+ /* config output base address */ -+ dst_addr = vb2_dma_contig_plane_dma_addr(&dst_buf->vb2_buf, 0); -+ writel_relaxed(dst_addr, rkvdec->regs + RKVDEC_REG_DECOUT_BASE); -+ -+ reg = RKVDEC_Y_VIRSTRIDE(y_virstride / 16); -+ writel_relaxed(reg, rkvdec->regs + RKVDEC_REG_Y_VIRSTRIDE); -+ -+ reg = RKVDEC_YUV_VIRSTRIDE(yuv_virstride / 16); -+ writel_relaxed(reg, rkvdec->regs + RKVDEC_REG_YUV_VIRSTRIDE); -+ -+ /* config ref pic address */ -+ for (i = 0; i < 15; i++) { -+ struct vb2_buffer *vb_buf = get_ref_buf(ctx, run, i); -+ -+ if (i < 4 && decode_params->num_active_dpb_entries) { -+ reg = GENMASK(decode_params->num_active_dpb_entries - 1, 0); -+ reg = (reg >> (i * 4)) & 0xf; -+ } else -+ reg = 0; -+ -+ refer_addr = vb2_dma_contig_plane_dma_addr(vb_buf, 0); -+ writel_relaxed(refer_addr | reg, -+ rkvdec->regs + RKVDEC_REG_H264_BASE_REFER(i)); -+ -+ reg = RKVDEC_POC_REFER(i < decode_params->num_active_dpb_entries ? dpb[i].pic_order_cnt_val : 0); -+ writel_relaxed(reg, -+ rkvdec->regs + RKVDEC_REG_H264_POC_REFER0(i)); -+ } -+ -+ reg = RKVDEC_CUR_POC(sl_params->slice_pic_order_cnt); -+ writel_relaxed(reg, rkvdec->regs + RKVDEC_REG_CUR_POC0); -+ -+ /* config hw pps address */ -+ offset = offsetof(struct rkvdec_hevc_priv_tbl, param_set); -+ writel_relaxed(priv_start_addr + offset, -+ rkvdec->regs + RKVDEC_REG_PPS_BASE); -+ -+ /* config hw rps address */ -+ offset = offsetof(struct rkvdec_hevc_priv_tbl, rps); -+ writel_relaxed(priv_start_addr + offset, -+ rkvdec->regs + RKVDEC_REG_RPS_BASE); -+ -+ reg = RKVDEC_AXI_DDR_RDATA(0); -+ writel_relaxed(reg, rkvdec->regs + RKVDEC_REG_AXI_DDR_RDATA); -+ -+ reg = RKVDEC_AXI_DDR_WDATA(0); -+ writel_relaxed(reg, rkvdec->regs + RKVDEC_REG_AXI_DDR_WDATA); -+} -+ -+#define RKVDEC_HEVC_MAX_DEPTH_IN_BYTES 2 -+ -+static int rkvdec_hevc_adjust_fmt(struct rkvdec_ctx *ctx, -+ struct v4l2_format *f) -+{ -+ struct v4l2_pix_format_mplane *fmt = &f->fmt.pix_mp; -+ -+ fmt->num_planes = 1; -+ if (!fmt->plane_fmt[0].sizeimage) -+ fmt->plane_fmt[0].sizeimage = fmt->width * fmt->height * -+ RKVDEC_HEVC_MAX_DEPTH_IN_BYTES; -+ return 0; -+} -+ -+static int rkvdec_hevc_validate_sps(struct rkvdec_ctx *ctx, -+ const struct v4l2_ctrl_hevc_sps *sps) -+{ -+ if (sps->chroma_format_idc > 1) -+ /* Only 4:0:0 and 4:2:0 are supported */ -+ return -EINVAL; -+ if (sps->bit_depth_luma_minus8 != sps->bit_depth_chroma_minus8) -+ /* Luma and chroma bit depth mismatch */ -+ return -EINVAL; -+ if (sps->bit_depth_luma_minus8 != 0 && sps->bit_depth_luma_minus8 != 2) -+ /* Only 8-bit and 10-bit is supported */ -+ return -EINVAL; -+ -+ if (sps->pic_width_in_luma_samples > ctx->coded_fmt.fmt.pix_mp.width || -+ sps->pic_height_in_luma_samples > ctx->coded_fmt.fmt.pix_mp.height) -+ return -EINVAL; -+ -+ return 0; -+} -+ -+static u32 rkvdec_hevc_valid_fmt(struct rkvdec_ctx *ctx, struct v4l2_ctrl *ctrl) -+{ -+ const struct v4l2_ctrl_hevc_sps *sps = ctrl->p_new.p_hevc_sps; -+ -+ if (sps->bit_depth_luma_minus8 == 2) -+ return V4L2_PIX_FMT_NV15; -+ else -+ return V4L2_PIX_FMT_NV12; -+} -+ -+static int rkvdec_hevc_start(struct rkvdec_ctx *ctx) -+{ -+ struct rkvdec_dev *rkvdec = ctx->dev; -+ struct rkvdec_hevc_priv_tbl *priv_tbl; -+ struct rkvdec_hevc_ctx *hevc_ctx; -+ struct v4l2_ctrl *ctrl; -+ int ret; -+ -+ ctrl = v4l2_ctrl_find(&ctx->ctrl_hdl, -+ V4L2_CID_STATELESS_HEVC_SPS); -+ if (!ctrl) -+ return -EINVAL; -+ -+ ret = rkvdec_hevc_validate_sps(ctx, ctrl->p_new.p_hevc_sps); -+ if (ret) -+ return ret; -+ -+ hevc_ctx = kzalloc(sizeof(*hevc_ctx), GFP_KERNEL); -+ if (!hevc_ctx) -+ return -ENOMEM; -+ -+ -+ priv_tbl = dma_alloc_coherent(rkvdec->dev, sizeof(*priv_tbl), -+ &hevc_ctx->priv_tbl.dma, GFP_KERNEL); -+ if (!priv_tbl) { -+ ret = -ENOMEM; -+ goto err_free_ctx; -+ } -+ -+ hevc_ctx->priv_tbl.size = sizeof(*priv_tbl); -+ hevc_ctx->priv_tbl.cpu = priv_tbl; -+ memset(priv_tbl, 0, sizeof(*priv_tbl)); -+ memcpy(priv_tbl->cabac_table, rkvdec_hevc_cabac_table, -+ sizeof(rkvdec_hevc_cabac_table)); -+ -+ ctx->priv = hevc_ctx; -+ return 0; -+ -+err_free_ctx: -+ kfree(hevc_ctx); -+ return ret; -+} -+ -+static void rkvdec_hevc_stop(struct rkvdec_ctx *ctx) -+{ -+ struct rkvdec_hevc_ctx *hevc_ctx = ctx->priv; -+ struct rkvdec_dev *rkvdec = ctx->dev; -+ -+ dma_free_coherent(rkvdec->dev, hevc_ctx->priv_tbl.size, -+ hevc_ctx->priv_tbl.cpu, hevc_ctx->priv_tbl.dma); -+ kfree(hevc_ctx); -+} -+ -+static void rkvdec_hevc_run_preamble(struct rkvdec_ctx *ctx, -+ struct rkvdec_hevc_run *run) -+{ -+ struct v4l2_ctrl *ctrl; -+ ctrl = v4l2_ctrl_find(&ctx->ctrl_hdl, -+ V4L2_CID_STATELESS_HEVC_DECODE_PARAMS); -+ run->decode_params = ctrl ? ctrl->p_cur.p : NULL; -+ ctrl = v4l2_ctrl_find(&ctx->ctrl_hdl, -+ V4L2_CID_STATELESS_HEVC_SLICE_PARAMS); -+ run->slices_params = ctrl ? ctrl->p_cur.p : NULL; -+ run->num_slices = ctrl->new_elems; -+ ctrl = v4l2_ctrl_find(&ctx->ctrl_hdl, -+ V4L2_CID_STATELESS_HEVC_SPS); -+ run->sps = ctrl ? ctrl->p_cur.p : NULL; -+ ctrl = v4l2_ctrl_find(&ctx->ctrl_hdl, -+ V4L2_CID_STATELESS_HEVC_PPS); -+ run->pps = ctrl ? ctrl->p_cur.p : NULL; -+ ctrl = v4l2_ctrl_find(&ctx->ctrl_hdl, -+ V4L2_CID_STATELESS_HEVC_SCALING_MATRIX); -+ run->scaling_matrix = ctrl ? ctrl->p_cur.p : NULL; -+ -+ rkvdec_run_preamble(ctx, &run->base); -+} -+ -+static int rkvdec_hevc_run(struct rkvdec_ctx *ctx) -+{ -+ struct rkvdec_dev *rkvdec = ctx->dev; -+ struct rkvdec_hevc_run run; -+ -+ rkvdec_hevc_run_preamble(ctx, &run); -+ -+ assemble_hw_scaling_list(ctx, &run); -+ assemble_hw_pps(ctx, &run); -+ assemble_hw_rps(ctx, &run); -+ config_registers(ctx, &run); -+ -+ rkvdec_run_postamble(ctx, &run.base); -+ -+ // sw_cabac_error_e - cabac error enable -+ writel_relaxed(0xfdfffffd, rkvdec->regs + RKVDEC_REG_STRMD_ERR_EN); -+ // slice end error enable = BIT(28) -+ // frame end error enable = BIT(29) -+ writel_relaxed(0x30000000, rkvdec->regs + RKVDEC_REG_H264_ERR_E); -+ -+ schedule_delayed_work(&rkvdec->watchdog_work, msecs_to_jiffies(2000)); -+ -+ writel(1, rkvdec->regs + RKVDEC_REG_PREF_LUMA_CACHE_COMMAND); -+ writel(1, rkvdec->regs + RKVDEC_REG_PREF_CHR_CACHE_COMMAND); -+ -+ /* Start decoding! */ -+ writel(RKVDEC_INTERRUPT_DEC_E | RKVDEC_CONFIG_DEC_CLK_GATE_E | -+ RKVDEC_TIMEOUT_E | RKVDEC_BUF_EMPTY_E, -+ rkvdec->regs + RKVDEC_REG_INTERRUPT); -+ -+ return 0; -+} -+ -+static int rkvdec_hevc_try_ctrl(struct rkvdec_ctx *ctx, struct v4l2_ctrl *ctrl) -+{ -+ if (ctrl->id == V4L2_CID_STATELESS_HEVC_SPS) -+ return rkvdec_hevc_validate_sps(ctx, ctrl->p_new.p_hevc_sps); -+ -+ return 0; -+} -+ -+const struct rkvdec_coded_fmt_ops rkvdec_hevc_fmt_ops = { -+ .adjust_fmt = rkvdec_hevc_adjust_fmt, -+ .start = rkvdec_hevc_start, -+ .stop = rkvdec_hevc_stop, -+ .run = rkvdec_hevc_run, -+ .try_ctrl = rkvdec_hevc_try_ctrl, -+ .valid_fmt = rkvdec_hevc_valid_fmt, -+}; -diff --git a/drivers/staging/media/rkvdec/rkvdec-regs.h b/drivers/staging/media/rkvdec/rkvdec-regs.h -index 265f5234f4eb..4319ee3ccbbc 100644 ---- a/drivers/staging/media/rkvdec/rkvdec-regs.h -+++ b/drivers/staging/media/rkvdec/rkvdec-regs.h -@@ -48,6 +48,7 @@ - #define RKVDEC_RLC_MODE BIT(11) - #define RKVDEC_STRM_START_BIT(x) (((x) & 0x7f) << 12) - #define RKVDEC_MODE(x) (((x) & 0x03) << 20) -+#define RKVDEC_MODE_HEVC 0 - #define RKVDEC_MODE_H264 1 - #define RKVDEC_MODE_VP9 2 - #define RKVDEC_RPS_MODE BIT(24) -diff --git a/drivers/staging/media/rkvdec/rkvdec.c b/drivers/staging/media/rkvdec/rkvdec.c -index f55abb7c377f..00a9bf583596 100644 ---- a/drivers/staging/media/rkvdec/rkvdec.c -+++ b/drivers/staging/media/rkvdec/rkvdec.c -@@ -74,7 +74,7 @@ static int rkvdec_s_ctrl(struct v4l2_ctrl *ctrl) - { - struct rkvdec_ctx *ctx = container_of(ctrl->handler, struct rkvdec_ctx, ctrl_hdl); - -- if (ctrl->id == V4L2_CID_STATELESS_H264_SPS && !ctx->valid_fmt) { -+ if (!ctx->valid_fmt) { - ctx->valid_fmt = rkvdec_valid_fmt(ctx, ctrl); - if (ctx->valid_fmt) { - struct v4l2_pix_format_mplane *pix_mp; -@@ -134,6 +134,62 @@ static const struct rkvdec_ctrl_desc rkvdec_h264_ctrl_descs[] = { - }, - }; - -+static const struct rkvdec_ctrl_desc rkvdec_hevc_ctrl_descs[] = { -+ { -+ .cfg.id = V4L2_CID_STATELESS_HEVC_SLICE_PARAMS, -+ .cfg.flags = V4L2_CTRL_FLAG_DYNAMIC_ARRAY, -+ .cfg.type = V4L2_CTRL_TYPE_HEVC_SLICE_PARAMS, -+ .cfg.dims = { 600 }, -+ }, -+ { -+ .cfg.id = V4L2_CID_STATELESS_HEVC_SPS, -+ .cfg.ops = &rkvdec_ctrl_ops, -+ }, -+ { -+ .cfg.id = V4L2_CID_STATELESS_HEVC_PPS, -+ }, -+ { -+ .cfg.id = V4L2_CID_STATELESS_HEVC_SCALING_MATRIX, -+ }, -+ { -+ .cfg.id = V4L2_CID_STATELESS_HEVC_DECODE_PARAMS, -+ }, -+ { -+ .cfg.id = V4L2_CID_STATELESS_HEVC_DECODE_MODE, -+ .cfg.min = V4L2_STATELESS_HEVC_DECODE_MODE_FRAME_BASED, -+ .cfg.max = V4L2_STATELESS_HEVC_DECODE_MODE_FRAME_BASED, -+ .cfg.def = V4L2_STATELESS_HEVC_DECODE_MODE_FRAME_BASED, -+ }, -+ { -+ .cfg.id = V4L2_CID_STATELESS_HEVC_START_CODE, -+ .cfg.min = V4L2_STATELESS_HEVC_START_CODE_ANNEX_B, -+ .cfg.def = V4L2_STATELESS_HEVC_START_CODE_ANNEX_B, -+ .cfg.max = V4L2_STATELESS_HEVC_START_CODE_ANNEX_B, -+ }, -+ { -+ .cfg.id = V4L2_CID_MPEG_VIDEO_HEVC_PROFILE, -+ .cfg.min = V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN, -+ .cfg.max = V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN_10, -+ .cfg.def = V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN, -+ }, -+ { -+ .cfg.id = V4L2_CID_MPEG_VIDEO_HEVC_LEVEL, -+ .cfg.min = V4L2_MPEG_VIDEO_HEVC_LEVEL_1, -+ .cfg.max = V4L2_MPEG_VIDEO_HEVC_LEVEL_5_1, -+ }, -+}; -+ -+static const struct rkvdec_ctrls rkvdec_hevc_ctrls = { -+ .ctrls = rkvdec_hevc_ctrl_descs, -+ .num_ctrls = ARRAY_SIZE(rkvdec_hevc_ctrl_descs), -+}; -+ -+static const u32 rkvdec_hevc_decoded_fmts[] = { -+ V4L2_PIX_FMT_NV12, -+ V4L2_PIX_FMT_NV15, -+}; -+ -+ - static const struct rkvdec_ctrls rkvdec_h264_ctrls = { - .ctrls = rkvdec_h264_ctrl_descs, - .num_ctrls = ARRAY_SIZE(rkvdec_h264_ctrl_descs), -@@ -187,6 +243,21 @@ static const struct rkvdec_coded_fmt_desc rkvdec_coded_fmts[] = { - .decoded_fmts = rkvdec_h264_decoded_fmts, - .subsystem_flags = VB2_V4L2_FL_SUPPORTS_M2M_HOLD_CAPTURE_BUF, - }, -+ { -+ .fourcc = V4L2_PIX_FMT_HEVC_SLICE, -+ .frmsize = { -+ .min_width = 64, -+ .max_width = 4096, -+ .step_width = 64, -+ .min_height = 64, -+ .max_height = 2304, -+ .step_height = 16, -+ }, -+ .ctrls = &rkvdec_hevc_ctrls, -+ .ops = &rkvdec_hevc_fmt_ops, -+ .num_decoded_fmts = ARRAY_SIZE(rkvdec_hevc_decoded_fmts), -+ .decoded_fmts = rkvdec_hevc_decoded_fmts, -+ }, - { - .fourcc = V4L2_PIX_FMT_VP9_FRAME, - .frmsize = { -diff --git a/drivers/staging/media/rkvdec/rkvdec.h b/drivers/staging/media/rkvdec/rkvdec.h -index f02f79c405f0..d6222a2588be 100644 ---- a/drivers/staging/media/rkvdec/rkvdec.h -+++ b/drivers/staging/media/rkvdec/rkvdec.h -@@ -133,6 +133,7 @@ void rkvdec_run_preamble(struct rkvdec_ctx *ctx, struct rkvdec_run *run); - void rkvdec_run_postamble(struct rkvdec_ctx *ctx, struct rkvdec_run *run); - - extern const struct rkvdec_coded_fmt_ops rkvdec_h264_fmt_ops; -+extern const struct rkvdec_coded_fmt_ops rkvdec_hevc_fmt_ops; - extern const struct rkvdec_coded_fmt_ops rkvdec_vp9_fmt_ops; - - #endif /* RKVDEC_H_ */ - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Alex Bee -Date: Sat, 30 Jan 2021 18:16:39 +0100 -Subject: [PATCH] media: rkvdec: add variants support - -rkvdec IP has different versions which among others differ in -the supported decoding formats. -This adds an variant implementation in order support other -than the currently supported RK3399 version. - -Note: Since matching of supported codecs is index-based the -available codec options have been reordered here: from -supported by all versions to not commonly supported. This seems -the better soultion than duplicatiing code for every newly added IP. - -Signed-off-by: Alex Bee ---- - drivers/staging/media/rkvdec/rkvdec.c | 105 ++++++++++++++++++-------- - drivers/staging/media/rkvdec/rkvdec.h | 10 +++ - 2 files changed, 85 insertions(+), 30 deletions(-) - -diff --git a/drivers/staging/media/rkvdec/rkvdec.c b/drivers/staging/media/rkvdec/rkvdec.c -index 00a9bf583596..955c53afe20f 100644 ---- a/drivers/staging/media/rkvdec/rkvdec.c -+++ b/drivers/staging/media/rkvdec/rkvdec.c -@@ -14,6 +14,7 @@ - #include - #include - #include -+#include - #include - #include - #include -@@ -227,6 +228,22 @@ static const u32 rkvdec_vp9_decoded_fmts[] = { - }; - - static const struct rkvdec_coded_fmt_desc rkvdec_coded_fmts[] = { -+ { -+ .fourcc = V4L2_PIX_FMT_HEVC_SLICE, -+ .frmsize = { -+ .min_width = 64, -+ .max_width = 4096, -+ .step_width = 64, -+ .min_height = 64, -+ .max_height = 2304, -+ .step_height = 16, -+ }, -+ .ctrls = &rkvdec_hevc_ctrls, -+ .ops = &rkvdec_hevc_fmt_ops, -+ .num_decoded_fmts = ARRAY_SIZE(rkvdec_hevc_decoded_fmts), -+ .decoded_fmts = rkvdec_hevc_decoded_fmts, -+ .capability = RKVDEC_CAPABILITY_HEVC, -+ }, - { - .fourcc = V4L2_PIX_FMT_H264_SLICE, - .frmsize = { -@@ -242,21 +259,7 @@ static const struct rkvdec_coded_fmt_desc rkvdec_coded_fmts[] = { - .num_decoded_fmts = ARRAY_SIZE(rkvdec_h264_decoded_fmts), - .decoded_fmts = rkvdec_h264_decoded_fmts, - .subsystem_flags = VB2_V4L2_FL_SUPPORTS_M2M_HOLD_CAPTURE_BUF, -- }, -- { -- .fourcc = V4L2_PIX_FMT_HEVC_SLICE, -- .frmsize = { -- .min_width = 64, -- .max_width = 4096, -- .step_width = 64, -- .min_height = 64, -- .max_height = 2304, -- .step_height = 16, -- }, -- .ctrls = &rkvdec_hevc_ctrls, -- .ops = &rkvdec_hevc_fmt_ops, -- .num_decoded_fmts = ARRAY_SIZE(rkvdec_hevc_decoded_fmts), -- .decoded_fmts = rkvdec_hevc_decoded_fmts, -+ .capability = RKVDEC_CAPABILITY_H264, - }, - { - .fourcc = V4L2_PIX_FMT_VP9_FRAME, -@@ -272,16 +275,31 @@ static const struct rkvdec_coded_fmt_desc rkvdec_coded_fmts[] = { - .ops = &rkvdec_vp9_fmt_ops, - .num_decoded_fmts = ARRAY_SIZE(rkvdec_vp9_decoded_fmts), - .decoded_fmts = rkvdec_vp9_decoded_fmts, -- } -+ .capability = RKVDEC_CAPABILITY_VP9, -+ }, - }; - - static const struct rkvdec_coded_fmt_desc * --rkvdec_find_coded_fmt_desc(u32 fourcc) -+rkvdec_default_coded_fmt_desc(unsigned int capabilities) -+{ -+ unsigned int i; -+ -+ for (i = 0; i < ARRAY_SIZE(rkvdec_coded_fmts); i++) { -+ if (rkvdec_coded_fmts[i].capability & capabilities) -+ return &rkvdec_coded_fmts[i]; -+ } -+ -+ return NULL; -+} -+ -+static const struct rkvdec_coded_fmt_desc * -+rkvdec_find_coded_fmt_desc(u32 fourcc, unsigned int capabilities) - { - unsigned int i; - - for (i = 0; i < ARRAY_SIZE(rkvdec_coded_fmts); i++) { -- if (rkvdec_coded_fmts[i].fourcc == fourcc) -+ if (rkvdec_coded_fmts[i].fourcc == fourcc && -+ (rkvdec_coded_fmts[i].capability & capabilities)) - return &rkvdec_coded_fmts[i]; - } - -@@ -304,7 +322,7 @@ static void rkvdec_reset_coded_fmt(struct rkvdec_ctx *ctx) - { - struct v4l2_format *f = &ctx->coded_fmt; - -- ctx->coded_fmt_desc = &rkvdec_coded_fmts[0]; -+ ctx->coded_fmt_desc = rkvdec_default_coded_fmt_desc(ctx->dev->capabilities); - rkvdec_reset_fmt(ctx, f, ctx->coded_fmt_desc->fourcc); - - f->type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE; -@@ -331,11 +349,13 @@ static int rkvdec_enum_framesizes(struct file *file, void *priv, - struct v4l2_frmsizeenum *fsize) - { - const struct rkvdec_coded_fmt_desc *fmt; -+ struct rkvdec_dev *rkvdec = video_drvdata(file); - - if (fsize->index != 0) - return -EINVAL; - -- fmt = rkvdec_find_coded_fmt_desc(fsize->pixel_format); -+ fmt = rkvdec_find_coded_fmt_desc(fsize->pixel_format, -+ rkvdec->capabilities); - if (!fmt) - return -EINVAL; - -@@ -406,10 +426,11 @@ static int rkvdec_try_output_fmt(struct file *file, void *priv, - struct rkvdec_ctx *ctx = fh_to_rkvdec_ctx(priv); - const struct rkvdec_coded_fmt_desc *desc; - -- desc = rkvdec_find_coded_fmt_desc(pix_mp->pixelformat); -+ desc = rkvdec_find_coded_fmt_desc(pix_mp->pixelformat, -+ ctx->dev->capabilities); - if (!desc) { -- pix_mp->pixelformat = rkvdec_coded_fmts[0].fourcc; -- desc = &rkvdec_coded_fmts[0]; -+ desc = rkvdec_default_coded_fmt_desc(ctx->dev->capabilities); -+ pix_mp->pixelformat = desc->fourcc; - } - - v4l2_apply_frmsize_constraints(&pix_mp->width, -@@ -487,7 +508,8 @@ static int rkvdec_s_output_fmt(struct file *file, void *priv, - if (ret) - return ret; - -- desc = rkvdec_find_coded_fmt_desc(f->fmt.pix_mp.pixelformat); -+ desc = rkvdec_find_coded_fmt_desc(f->fmt.pix_mp.pixelformat, -+ ctx->dev->capabilities); - if (!desc) - return -EINVAL; - ctx->coded_fmt_desc = desc; -@@ -538,7 +560,10 @@ static int rkvdec_g_capture_fmt(struct file *file, void *priv, - static int rkvdec_enum_output_fmt(struct file *file, void *priv, - struct v4l2_fmtdesc *f) - { -- if (f->index >= ARRAY_SIZE(rkvdec_coded_fmts)) -+ struct rkvdec_ctx *ctx = fh_to_rkvdec_ctx(priv); -+ -+ if (f->index >= ARRAY_SIZE(rkvdec_coded_fmts) || -+ !(ctx->dev->capabilities & rkvdec_coded_fmts[f->index].capability)) - return -EINVAL; - - f->pixelformat = rkvdec_coded_fmts[f->index].fourcc; -@@ -946,14 +971,17 @@ static int rkvdec_init_ctrls(struct rkvdec_ctx *ctx) - int ret; - - for (i = 0; i < ARRAY_SIZE(rkvdec_coded_fmts); i++) -- nctrls += rkvdec_coded_fmts[i].ctrls->num_ctrls; -+ if (rkvdec_coded_fmts[i].capability & ctx->dev->capabilities) -+ nctrls += rkvdec_coded_fmts[i].ctrls->num_ctrls; - - v4l2_ctrl_handler_init(&ctx->ctrl_hdl, nctrls); - - for (i = 0; i < ARRAY_SIZE(rkvdec_coded_fmts); i++) { -- ret = rkvdec_add_ctrls(ctx, rkvdec_coded_fmts[i].ctrls); -- if (ret) -- goto err_free_handler; -+ if (rkvdec_coded_fmts[i].capability & ctx->dev->capabilities) { -+ ret = rkvdec_add_ctrls(ctx, rkvdec_coded_fmts[i].ctrls); -+ if (ret) -+ goto err_free_handler; -+ } - } - - ret = v4l2_ctrl_handler_setup(&ctx->ctrl_hdl); -@@ -1155,8 +1183,17 @@ static void rkvdec_watchdog_func(struct work_struct *work) - } - } - -+static const struct rkvdec_variant rk3399_rkvdec_variant = { -+ .capabilities = RKVDEC_CAPABILITY_H264 | -+ RKVDEC_CAPABILITY_HEVC | -+ RKVDEC_CAPABILITY_VP9 -+}; -+ - static const struct of_device_id of_rkvdec_match[] = { -- { .compatible = "rockchip,rk3399-vdec" }, -+ { -+ .compatible = "rockchip,rk3399-vdec", -+ .data = &rk3399_rkvdec_variant, -+ }, - { /* sentinel */ } - }; - MODULE_DEVICE_TABLE(of, of_rkvdec_match); -@@ -1168,6 +1205,7 @@ static const char * const rkvdec_clk_names[] = { - static int rkvdec_probe(struct platform_device *pdev) - { - struct rkvdec_dev *rkvdec; -+ const struct rkvdec_variant *variant; - unsigned int i; - int ret, irq; - -@@ -1193,6 +1231,13 @@ static int rkvdec_probe(struct platform_device *pdev) - if (ret) - return ret; - -+ variant = of_device_get_match_data(rkvdec->dev); -+ if (!variant) -+ return -EINVAL; -+ -+ rkvdec->capabilities = variant->capabilities; -+ -+ - rkvdec->regs = devm_platform_ioremap_resource(pdev, 0); - if (IS_ERR(rkvdec->regs)) - return PTR_ERR(rkvdec->regs); -diff --git a/drivers/staging/media/rkvdec/rkvdec.h b/drivers/staging/media/rkvdec/rkvdec.h -index d6222a2588be..ad8e83884121 100644 ---- a/drivers/staging/media/rkvdec/rkvdec.h -+++ b/drivers/staging/media/rkvdec/rkvdec.h -@@ -29,6 +29,10 @@ - - #define RKVDEC_RESET_DELAY 5 - -+#define RKVDEC_CAPABILITY_H264 BIT(0) -+#define RKVDEC_CAPABILITY_HEVC BIT(1) -+#define RKVDEC_CAPABILITY_VP9 BIT(2) -+ - struct rkvdec_ctx; - - struct rkvdec_ctrl_desc { -@@ -70,6 +74,10 @@ vb2_to_rkvdec_decoded_buf(struct vb2_buffer *buf) - base.vb.vb2_buf); - } - -+struct rkvdec_variant { -+ unsigned int capabilities; -+}; -+ - struct rkvdec_coded_fmt_ops { - int (*adjust_fmt)(struct rkvdec_ctx *ctx, - struct v4l2_format *f); -@@ -91,6 +99,7 @@ struct rkvdec_coded_fmt_desc { - unsigned int num_decoded_fmts; - const u32 *decoded_fmts; - u32 subsystem_flags; -+ unsigned int capability; - }; - - struct rkvdec_dev { -@@ -105,6 +114,7 @@ struct rkvdec_dev { - struct delayed_work watchdog_work; - struct reset_control *rstc; - u8 reset_mask; -+ unsigned int capabilities; - }; - - struct rkvdec_ctx { - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Alex Bee -Date: Sat, 30 Jan 2021 18:21:59 +0100 -Subject: [PATCH] media: rkvdec: add RK3288 variant - -This adds RK3288 variant to rkvdec driver. In this earlier version -of the IP only HEVC decoding is supported. - -Signed-off-by: Alex Bee ---- - drivers/staging/media/rkvdec/rkvdec.c | 8 ++++++++ - 1 file changed, 8 insertions(+) - -diff --git a/drivers/staging/media/rkvdec/rkvdec.c b/drivers/staging/media/rkvdec/rkvdec.c -index 955c53afe20f..4e228cd82f21 100644 ---- a/drivers/staging/media/rkvdec/rkvdec.c -+++ b/drivers/staging/media/rkvdec/rkvdec.c -@@ -1189,11 +1189,19 @@ static const struct rkvdec_variant rk3399_rkvdec_variant = { - RKVDEC_CAPABILITY_VP9 - }; - -+static const struct rkvdec_variant rk3288_hevc_variant = { -+ .capabilities = RKVDEC_CAPABILITY_HEVC -+}; -+ - static const struct of_device_id of_rkvdec_match[] = { - { - .compatible = "rockchip,rk3399-vdec", - .data = &rk3399_rkvdec_variant, - }, -+ { -+ .compatible = "rockchip,rk3288-hevc", -+ .data = &rk3288_hevc_variant, -+ }, - { /* sentinel */ } - }; - MODULE_DEVICE_TABLE(of, of_rkvdec_match); - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Alex Bee -Date: Sat, 30 Jan 2021 18:27:30 +0100 -Subject: [PATCH] ARM: dts: RK3288: add hevc node - -Signed-off-by: Alex Bee ---- - arch/arm/boot/dts/rockchip/rk3288.dtsi | 21 ++++++++++++++++++++- - 1 file changed, 20 insertions(+), 1 deletion(-) - -diff --git a/arch/arm/boot/dts/rockchip/rk3288.dtsi b/arch/arm/boot/dts/rockchip/rk3288.dtsi -index 7b2cde230b87..59fba3ac6aae 100644 ---- a/arch/arm/boot/dts/rockchip/rk3288.dtsi -+++ b/arch/arm/boot/dts/rockchip/rk3288.dtsi -@@ -1248,6 +1248,25 @@ vpu_mmu: iommu@ff9a0800 { - power-domains = <&power RK3288_PD_VIDEO>; - }; - -+ hevc: hevc@ff9c0000 { -+ compatible = "rockchip,rk3288-hevc"; -+ reg = <0x0 0xff9c0000 0x0 0x400>; -+ interrupts = ; -+ interrupt-names = "irq_dec"; -+ clocks = <&cru ACLK_HEVC>, <&cru HCLK_HEVC>, <&cru SCLK_HEVC_CABAC>, -+ <&cru SCLK_HEVC_CORE>; -+ clock-names = "axi", "ahb", "cabac", "core"; -+ assigned-clocks = <&cru ACLK_HEVC>, <&cru HCLK_HEVC>, -+ <&cru SCLK_HEVC_CORE>, -+ <&cru SCLK_HEVC_CABAC>; -+ assigned-clock-rates = <400000000>, <100000000>, -+ <300000000>, <300000000>; -+ iommus = <&hevc_mmu>; -+ power-domains = <&power RK3288_PD_HEVC>; -+ resets = <&cru SRST_HEVC>; -+ reset-names = "video_core"; -+ }; -+ - hevc_mmu: iommu@ff9c0440 { - compatible = "rockchip,iommu"; - reg = <0x0 0xff9c0440 0x0 0x40>, <0x0 0xff9c0480 0x0 0x40>; -@@ -1255,7 +1274,7 @@ hevc_mmu: iommu@ff9c0440 { - clocks = <&cru ACLK_HEVC>, <&cru HCLK_HEVC>; - clock-names = "aclk", "iface"; - #iommu-cells = <0>; -- status = "disabled"; -+ power-domains = <&power RK3288_PD_HEVC>; - }; - - gpu: gpu@ffa30000 { - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Nicolas Dufresne -Date: Tue, 10 May 2022 14:37:29 -0400 -Subject: [PATCH] media: rkvdec: Fix HEVC RPS bit offsets - -The offsets from the uAPI need to be extended to include some bits -that can be calculated from the parameters. This has been compared -to match with the vendor bit sizes (which simply parse again the -data to calcualte it). - -Fixed by this change: -- LTRPSPS_A_Qualcomm_1 -- RPS_C_ericsson_5 -- RPS_D_ericsson_6 -- RPS_E_qualcomm_5 - -Signed-off-by: Nicolas Dufresne ---- - drivers/staging/media/rkvdec/rkvdec-hevc.c | 26 +++++++++++++++++++--- - 1 file changed, 23 insertions(+), 3 deletions(-) - -diff --git a/drivers/staging/media/rkvdec/rkvdec-hevc.c b/drivers/staging/media/rkvdec/rkvdec-hevc.c -index 7a375a23eaf1..580073d49b6a 100644 ---- a/drivers/staging/media/rkvdec/rkvdec-hevc.c -+++ b/drivers/staging/media/rkvdec/rkvdec-hevc.c -@@ -10,6 +10,7 @@ - */ - - #include -+#include - - #include "rkvdec.h" - #include "rkvdec-regs.h" -@@ -2175,6 +2176,7 @@ static void assemble_hw_rps(struct rkvdec_ctx *ctx, - struct rkvdec_hevc_run *run) - { - const struct v4l2_ctrl_hevc_decode_params *decode_params = run->decode_params; -+ const struct v4l2_ctrl_hevc_sps *sps = run->sps; - const struct v4l2_ctrl_hevc_slice_params *sl_params; - const struct v4l2_hevc_dpb_entry *dpb; - struct rkvdec_hevc_ctx *hevc_ctx = ctx->priv; -@@ -2196,9 +2198,21 @@ static void assemble_hw_rps(struct rkvdec_ctx *ctx, - #define NUM_RPS_POC PS_FIELD(202, 4) - - for (j = 0; j < run->num_slices; j++) { -+ uint st_bit_offset = 0; -+ - sl_params = &run->slices_params[j]; - dpb = decode_params->dpb; -- lowdelay = (sl_params->slice_type == V4L2_HEVC_SLICE_TYPE_I) ? 0 : 1; -+ -+ if (sl_params->slice_type != V4L2_HEVC_SLICE_TYPE_I) { -+ num_l0_refs = sl_params->num_ref_idx_l0_active_minus1 + 1; -+ -+ if (sl_params->slice_type == V4L2_HEVC_SLICE_TYPE_B) -+ num_l1_refs = sl_params->num_ref_idx_l1_active_minus1 + 1; -+ -+ lowdelay = 1; -+ } else { -+ lowdelay = 0; -+ } - - hw_ps = &priv_tbl->rps[j]; - memset(hw_ps, 0, sizeof(*hw_ps)); -@@ -2224,8 +2238,14 @@ static void assemble_hw_rps(struct rkvdec_ctx *ctx, - - WRITE_RPS(lowdelay, LOWDELAY); - -- WRITE_RPS(sl_params->long_term_ref_pic_set_size + -- sl_params->short_term_ref_pic_set_size, -+ if (!(decode_params->flags & V4L2_HEVC_DECODE_PARAM_FLAG_IDR_PIC)) { -+ if (sl_params->short_term_ref_pic_set_size) -+ st_bit_offset = sl_params->short_term_ref_pic_set_size; -+ else if (sps->num_short_term_ref_pic_sets > 1) -+ st_bit_offset = fls(sps->num_short_term_ref_pic_sets - 1); -+ } -+ -+ WRITE_RPS(st_bit_offset + sl_params->long_term_ref_pic_set_size, - LONG_TERM_RPS_BIT_OFFSET); - WRITE_RPS(sl_params->short_term_ref_pic_set_size, - SHORT_TERM_RPS_BIT_OFFSET); - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Nicolas Dufresne -Date: Tue, 10 May 2022 15:12:03 -0400 -Subject: [PATCH] media: rkvdec: Fix number of HEVC references being set in RPS - -The numbers from the bitstream are values between 1 - 16 (as they are -the number - 1). The difference between 0 and 1 needs to be determined -base on the slice type. I frames have no reference, P frames only have -L0 reference, and B frames have both. - -Signed-off-by: Nicolas Dufresne ---- - drivers/staging/media/rkvdec/rkvdec-hevc.c | 6 ++++-- - 1 file changed, 4 insertions(+), 2 deletions(-) - -diff --git a/drivers/staging/media/rkvdec/rkvdec-hevc.c b/drivers/staging/media/rkvdec/rkvdec-hevc.c -index 580073d49b6a..ce15028918b2 100644 ---- a/drivers/staging/media/rkvdec/rkvdec-hevc.c -+++ b/drivers/staging/media/rkvdec/rkvdec-hevc.c -@@ -2199,6 +2199,8 @@ static void assemble_hw_rps(struct rkvdec_ctx *ctx, - - for (j = 0; j < run->num_slices; j++) { - uint st_bit_offset = 0; -+ uint num_l0_refs = 0; -+ uint num_l1_refs = 0; - - sl_params = &run->slices_params[j]; - dpb = decode_params->dpb; -@@ -2217,7 +2219,7 @@ static void assemble_hw_rps(struct rkvdec_ctx *ctx, - hw_ps = &priv_tbl->rps[j]; - memset(hw_ps, 0, sizeof(*hw_ps)); - -- for (i = 0; i <= sl_params->num_ref_idx_l0_active_minus1; i++) { -+ for (i = 0; i < num_l0_refs; i++) { - WRITE_RPS(!!(dpb[sl_params->ref_idx_l0[i]].flags & V4L2_HEVC_DPB_ENTRY_LONG_TERM_REFERENCE), - REF_PIC_LONG_TERM_L0(i)); - WRITE_RPS(sl_params->ref_idx_l0[i], REF_PIC_IDX_L0(i)); -@@ -2227,7 +2229,7 @@ static void assemble_hw_rps(struct rkvdec_ctx *ctx, - - } - -- for (i = 0; i <= sl_params->num_ref_idx_l1_active_minus1; i++) { -+ for (i = 0; i < num_l1_refs; i++) { - WRITE_RPS(!!(dpb[sl_params->ref_idx_l1[i]].flags & V4L2_HEVC_DPB_ENTRY_LONG_TERM_REFERENCE), - REF_PIC_LONG_TERM_L1(i)); - WRITE_RPS(sl_params->ref_idx_l1[i], REF_PIC_IDX_L1(i)); diff --git a/patch/kernel/archive/rockchip-6.11/patches.libreelec/linux-2001-v4l2-wip-iep-driver.patch b/patch/kernel/archive/rockchip-6.11/patches.libreelec/linux-2001-v4l2-wip-iep-driver.patch deleted file mode 100644 index c778dc3bbf4d..000000000000 --- a/patch/kernel/archive/rockchip-6.11/patches.libreelec/linux-2001-v4l2-wip-iep-driver.patch +++ /dev/null @@ -1,1805 +0,0 @@ -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Alex Bee -Date: Sun, 11 Oct 2020 17:03:12 +0200 -Subject: [PATCH] dt-bindings: media: Add Rockchip IEP binding - -Signed-off-by: Alex Bee ---- - .../bindings/media/rockchip-iep.yaml | 73 +++++++++++++++++++ - 1 file changed, 73 insertions(+) - create mode 100644 Documentation/devicetree/bindings/media/rockchip-iep.yaml - -diff --git a/Documentation/devicetree/bindings/media/rockchip-iep.yaml b/Documentation/devicetree/bindings/media/rockchip-iep.yaml -new file mode 100644 -index 000000000000..a9efcda13fc1 ---- /dev/null -+++ b/Documentation/devicetree/bindings/media/rockchip-iep.yaml -@@ -0,0 +1,73 @@ -+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) -+%YAML 1.2 -+--- -+$id: http://devicetree.org/schemas/media/rockchip-iep.yaml# -+$schema: http://devicetree.org/meta-schemas/core.yaml# -+ -+title: Rockchip Image Enhancement Processor (IEP) -+ -+description: -+ Rockchip IEP supports various image enhancement operations for YUV and RGB domains. -+ Deinterlacing, spatial and temporal sampling noise reduction are supported by the -+ YUV block. Gamma adjustment, edge enhancement, detail enhancement are supported in -+ the RGB block. Brightness, Saturation, Contrast, Hue adjustment is supported for -+ both domains. Furthermore it supports converting RGB to YUV / YUV to RGB. -+ -+maintainers: -+ - Heiko Stuebner -+ -+properties: -+ compatible: -+ oneOf: -+ - const: rockchip,rk3228-iep -+ - items: -+ - enum: -+ - rockchip,rk3288-iep -+ - rockchip,rk3328-iep -+ - rockchip,rk3368-iep -+ - rockchip,rk3399-iep -+ - const: rockchip,rk3228-iep -+ -+ reg: -+ maxItems: 1 -+ -+ interrupts: -+ maxItems: 1 -+ -+ clocks: -+ maxItems: 2 -+ -+ clock-names: -+ items: -+ - const: axi -+ - const: ahb -+ -+ power-domains: -+ maxItems: 1 -+ -+ iommus: -+ maxItems: 1 -+ -+required: -+ - compatible -+ - reg -+ - interrupts -+ - clocks -+ - clock-names -+ -+additionalProperties: false -+ -+examples: -+ - | -+ #include -+ #include -+ #include -+ iep: iep@20070000 { -+ compatible = "rockchip,rk3228-iep"; -+ reg = <0x20070000 0x800>; -+ interrupts = ; -+ clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>; -+ clock-names = "axi", "ahb"; -+ iommus = <&iep_mmu>; -+ power-domains = <&power RK3228_PD_VIO>; -+ }; - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Alex Bee -Date: Sun, 11 Oct 2020 21:24:10 +0200 -Subject: [PATCH] media: rockchip: Add Rockchip IEP driver - -Signed-off-by: Alex Bee ---- - drivers/media/platform/rockchip/Kconfig | 1 + - drivers/media/platform/rockchip/Makefile | 1 + - drivers/media/platform/rockchip/iep/Kconfig | 16 + - drivers/media/platform/rockchip/iep/Makefile | 5 + - .../media/platform/rockchip/iep/iep-regs.h | 291 +++++ - drivers/media/platform/rockchip/iep/iep.c | 1089 +++++++++++++++++ - drivers/media/platform/rockchip/iep/iep.h | 112 ++ - 7 files changed, 1515 insertions(+) - create mode 100644 drivers/media/platform/rockchip/iep/Kconfig - create mode 100644 drivers/media/platform/rockchip/iep/Makefile - create mode 100644 drivers/media/platform/rockchip/iep/iep-regs.h - create mode 100644 drivers/media/platform/rockchip/iep/iep.c - create mode 100644 drivers/media/platform/rockchip/iep/iep.h - -diff --git a/drivers/media/platform/rockchip/Kconfig b/drivers/media/platform/rockchip/Kconfig -index b41d3960c1b4..9ff362805ded 100644 ---- a/drivers/media/platform/rockchip/Kconfig -+++ b/drivers/media/platform/rockchip/Kconfig -@@ -2,5 +2,6 @@ - - comment "Rockchip media platform drivers" - -+source "drivers/media/platform/rockchip/iep/Kconfig" - source "drivers/media/platform/rockchip/rga/Kconfig" - source "drivers/media/platform/rockchip/rkisp1/Kconfig" -diff --git a/drivers/media/platform/rockchip/Makefile b/drivers/media/platform/rockchip/Makefile -index 4f782b876ac9..c075ecc2fa14 100644 ---- a/drivers/media/platform/rockchip/Makefile -+++ b/drivers/media/platform/rockchip/Makefile -@@ -1,3 +1,4 @@ - # SPDX-License-Identifier: GPL-2.0-only -+obj-y += iep/ - obj-y += rga/ - obj-y += rkisp1/ -diff --git a/drivers/media/platform/rockchip/iep/Kconfig b/drivers/media/platform/rockchip/iep/Kconfig -new file mode 100644 -index 000000000000..d95155a95133 ---- /dev/null -+++ b/drivers/media/platform/rockchip/iep/Kconfig -@@ -0,0 +1,16 @@ -+# SPDX-License-Identifier: GPL-2.0-only -+ -+config VIDEO_ROCKCHIP_IEP -+ tristate "Rockchip Image Enhancement Processor" -+ depends on V4L_MEM2MEM_DRIVERS -+ depends on VIDEO_DEV -+ depends on ARCH_ROCKCHIP || COMPILE_TEST -+ select VIDEOBUF2_DMA_CONTIG -+ select V4L2_MEM2MEM_DEV -+ help -+ This is a v4l2 driver for Rockchip Image Enhancement Processor (IEP) -+ found in most Rockchip RK3xxx SoCs. -+ Rockchip IEP supports various enhancement operations for RGB and YUV -+ images. The driver currently implements YUV deinterlacing only. -+ To compile this driver as a module, choose M here: the module -+ will be called rockchip-iep -diff --git a/drivers/media/platform/rockchip/iep/Makefile b/drivers/media/platform/rockchip/iep/Makefile -new file mode 100644 -index 000000000000..5c89b3277469 ---- /dev/null -+++ b/drivers/media/platform/rockchip/iep/Makefile -@@ -0,0 +1,5 @@ -+# SPDX-License-Identifier: GPL-2.0-only -+ -+rockchip-iep-objs := iep.o -+ -+obj-$(CONFIG_VIDEO_ROCKCHIP_IEP) += rockchip-iep.o -diff --git a/drivers/media/platform/rockchip/iep/iep-regs.h b/drivers/media/platform/rockchip/iep/iep-regs.h -new file mode 100644 -index 000000000000..a68685ef3604 ---- /dev/null -+++ b/drivers/media/platform/rockchip/iep/iep-regs.h -@@ -0,0 +1,291 @@ -+/* SPDX-License-Identifier: GPL-2.0-only */ -+/* -+ * Rockchip Image Enhancement Processor (IEP) driver -+ * -+ * Copyright (C) 2020 Alex Bee -+ * -+ */ -+ -+#ifndef __IEP_REGS_H__ -+#define __IEP_REGS_H__ -+ -+/* IEP Registers addresses */ -+#define IEP_CONFIG0 0x000 /* Configuration register0 */ -+#define IEP_VOP_DIRECT_PATH BIT(0) -+#define IEP_DEIN_HIGH_FREQ_SHFT 1 -+#define IEP_DEIN_HIGH_FREQ_MASK (0x7f << IEP_DEIN_HIGH_FREQ_SHFT) -+#define IEP_DEIN_MODE_SHFT 8 -+#define IEP_DEIN_MODE_MASK (7 << IEP_DEIN_MODE_SHFT) -+#define IEP_DEIN_HIGH_FREQ_EN BIT(11) -+#define IEP_DEIN_EDGE_INTPOL_EN BIT(12) -+#define IEP_YUV_DENOISE_EN BIT(13) -+#define IEP_YUV_ENHNC_EN BIT(14) -+#define IEP_DEIN_EDGE_INTPOL_SMTH_EN BIT(15) -+#define IEP_RGB_CLR_ENHNC_EN BIT(16) -+#define IEP_RGB_CNTRST_ENHNC_EN BIT(17) -+#define IEP_RGB_ENHNC_MODE_BYPASS (0 << 18) -+#define IEP_RGB_ENHNC_MODE_DNS BIT(18) -+#define IEP_RGB_ENHNC_MODE_DTL (2 << 18) -+#define IEP_RGB_ENHNC_MODE_EDG (3 << 18) -+#define IEP_RGB_ENHNC_MODE_MASK (3 << 18) -+#define IEP_RGB_CNTRST_ENHNC_DDE_FRST BIT(20) -+#define IEP_DEIN_EDGE_INTPOL_RADIUS_SHFT 21 -+#define IEP_DEIN_EDGE_INTPOL_RADIUS_MASK (3 << IEP_DEIN_EDGE_INTPOL_RADIUS_SHFT) -+#define IEP_DEIN_EDGE_INTPOL_SELECT BIT(23) -+ -+#define IEP_CONFIG1 0x004 /* Configuration register1 */ -+#define IEP_SRC_FMT_SHFT 0 -+#define IEP_SRC_FMT_MASK (3 << IEP_SRC_FMT_SHFT) -+#define IEP_SRC_RGB_SWP_SHFT 2 -+#define IEP_SRC_RGB_SWP_MASK (2 << IEP_SRC_RGB_SWP_SHFT) -+#define IEP_SRC_YUV_SWP_SHFT 4 -+#define IEP_SRC_YUV_SWP_MASK (3 << IEP_SRC_YUV_SWP_SHFT) -+#define IEP_DST_FMT_SHFT 8 -+#define IEP_DST_FMT_MASK (3 << IEP_DST_FMT_SHFT) -+#define IEP_DST_RGB_SWP_SHFT 10 -+#define IEP_DST_RGB_SWP_MASK (2 << IEP_DST_RGB_SWP_SHFT) -+#define IEP_DST_YUV_SWP_SHFT 12 -+#define IEP_DST_YUV_SWP_MASK (3 << IEP_DST_YUV_SWP_SHFT) -+#define IEP_DTH_UP_EN BIT(14) -+#define IEP_DTH_DWN_EN BIT(15) -+#define IEP_YUV2RGB_COE_BT601_1 (0 << 16) -+#define IEP_YUV2RGB_COE_BT601_F BIT(16) -+#define IEP_YUV2RGB_COE_BT709_1 (2 << 16) -+#define IEP_YUV2RGB_COE_BT709_F (3 << 16) -+#define IEP_YUV2RGB_COE_MASK (3 << 16) -+#define IEP_RGB2YUV_COE_BT601_1 (0 << 18) -+#define IEP_RGB2YUV_COE_BT601_F BIT(18) -+#define IEP_RGB2YUV_COE_BT709_1 (2 << 18) -+#define IEP_RGB2YUV_COE_BT709_F (3 << 18) -+#define IEP_RGB2YUV_COE_MASK (3 << 18) -+#define IEP_YUV2RGB_EN BIT(20) -+#define IEP_RGB2YUV_EN BIT(21) -+#define IEP_YUV2RGB_CLIP_EN BIT(22) -+#define IEP_RGB2YUV_CLIP_EN BIT(23) -+#define IEP_GLB_ALPHA_SHFT 24 -+#define IEP_GLB_ALPHA_MASK (0x7f << IEP_GLB_ALPHA_SHFT) -+ -+#define IEP_STATUS 0x008 /* Status register */ -+#define IEP_STATUS_YUV_DNS BIT(0) -+#define IEP_STATUS_SCL BIT(1) -+#define IEP_STATUS_DIL BIT(2) -+#define IEP_STATUS_DDE BIT(3) -+#define IEP_STATUS_DMA_WR_YUV BIT(4) -+#define IEP_STATUS_DMA_RE_YUV BIT(5) -+#define IEP_STATUS_DMA_WR_RGB BIT(6) -+#define IEP_STATUS_DMA_RE_RGB BIT(7) -+#define IEP_STATUS_VOP_DIRECT_PATH BIT(8) -+#define IEP_STATUS_DMA_IA_WR_YUV BIT(16) -+#define IEP_STATUS_DMA_IA_RE_YUV BIT(17) -+#define IEP_STATUS_DMA_IA_WR_RGB BIT(18) -+#define IEP_STATUS_DMA_IA_RE_RGB BIT(19) -+ -+#define IEP_INT 0x00c /* Interrupt register*/ -+#define IEP_INT_FRAME_DONE BIT(0) /* Frame process done interrupt */ -+#define IEP_INT_FRAME_DONE_EN BIT(8) /* Frame process done interrupt enable */ -+#define IEP_INT_FRAME_DONE_CLR BIT(16) /* Frame process done interrupt clear */ -+ -+#define IEP_FRM_START 0x010 /* Frame start */ -+#define IEP_SRST 0x014 /* Soft reset */ -+#define IEP_CONFIG_DONE 0x018 /* Configuration done */ -+#define IEP_FRM_CNT 0x01c /* Frame counter */ -+ -+#define IEP_VIR_IMG_WIDTH 0x020 /* Image virtual width */ -+#define IEP_IMG_SCL_FCT 0x024 /* Scaling factor */ -+#define IEP_SRC_IMG_SIZE 0x028 /* src image width/height */ -+#define IEP_DST_IMG_SIZE 0x02c /* dst image width/height */ -+#define IEP_DST_IMG_WIDTH_TILE0 0x030 /* dst image tile0 width */ -+#define IEP_DST_IMG_WIDTH_TILE1 0x034 /* dst image tile1 width */ -+#define IEP_DST_IMG_WIDTH_TILE2 0x038 /* dst image tile2 width */ -+#define IEP_DST_IMG_WIDTH_TILE3 0x03c /* dst image tile3 width */ -+ -+#define IEP_ENH_YUV_CNFG_0 0x040 /* Brightness, contrast, saturation adjustment */ -+#define IEP_YUV_BRIGHTNESS_SHFT 0 -+#define IEP_YUV_BRIGHTNESS_MASK (0x3f << IEP_YUV_BRIGHTNESS_SHFT) -+#define IEP_YUV_CONTRAST_SHFT 8 -+#define IEP_YUV_CONTRAST_MASK (0xff << IEP_YUV_CONTRAST_SHFT) -+#define IEP_YUV_SATURATION_SHFT 16 -+#define IEP_YUV_SATURATION_MASK (0x1ff << IEP_YUV_SATURATION_SHFT) -+ -+#define IEP_ENH_YUV_CNFG_1 0x044 /* Hue configuration */ -+#define IEP_YUV_COS_HUE_SHFT 0 -+#define IEP_YUV_COS_HUE_MASK (0xff << IEP_YUV_COS_HUE_SHFT) -+#define IEP_YUV_SIN_HUE_SHFT 8 -+#define IEP_YUV_SIN_HUE_MASK (0xff << IEP_YUV_SIN_HUE_SHFT) -+ -+#define IEP_ENH_YUV_CNFG_2 0x048 /* Color bar configuration */ -+#define IEP_YUV_COLOR_BAR_Y_SHFT 0 -+#define IEP_YUV_COLOR_BAR_Y_MASK (0xff << IEP_YUV_COLOR_BAR_Y_SHFT) -+#define IEP_YUV_COLOR_BAR_U_SHFT 8 -+#define IEP_YUV_COLOR_BAR_U_MASK (0xff << IEP_YUV_COLOR_BAR_U_SHFT) -+#define IEP_YUV_COLOR_BAR_V_SHFT 16 -+#define IEP_YUV_COLOR_BAR_V_MASK (0xff << IEP_YUV_COLOR_BAR_V_SHFT) -+#define IEP_YUV_VIDEO_MODE_SHFT 24 -+#define IEP_YUV_VIDEO_MODE_MASK (3 << IEP_YUV_VIDEO_MODE_SHFT) -+ -+#define IEP_ENH_RGB_CNFG 0x04c /* RGB enhancement configuration */ -+#define IEP_ENH_RGB_C_COE 0x050 /* RGB color enhancement coefficient */ -+ -+#define IEP_RAW_CONFIG0 0x058 /* Raw configuration register0 */ -+#define IEP_RAW_CONFIG1 0x05c /* Raw configuration register1 */ -+#define IEP_RAW_VIR_IMG_WIDTH 0x060 /* Raw image virtual width */ -+#define IEP_RAW_IMG_SCL_FCT 0x064 /* Raw scaling factor */ -+#define IEP_RAW_SRC_IMG_SIZE 0x068 /* Raw src image width/height */ -+#define IEP_RAW_DST_IMG_SIZE 0x06c /* Raw src image width/height */ -+#define IEP_RAW_ENH_YUV_CNFG_0 0x070 /* Raw brightness,contrast,saturation adjustment */ -+#define IEP_RAW_ENH_YUV_CNFG_1 0x074 /* Raw hue configuration */ -+#define IEP_RAW_ENH_YUV_CNFG_2 0x078 /* Raw color bar configuration */ -+#define IEP_RAW_ENH_RGB_CNFG 0x07c /* Raw RGB enhancement configuration */ -+ -+#define IEP_SRC_ADDR_Y_RGB 0x080 /* Start addr. of src image 0 (Y/RGB) */ -+#define IEP_SRC_ADDR_CBCR 0x084 /* Start addr. of src image 0 (Cb/Cr) */ -+#define IEP_SRC_ADDR_CR 0x088 /* Start addr. of src image 0 (Cr) */ -+#define IEP_SRC_ADDR_Y1 0x08c /* Start addr. of src image 1 (Y) */ -+#define IEP_SRC_ADDR_CBCR1 0x090 /* Start addr. of src image 1 (Cb/Cr) */ -+#define IEP_SRC_ADDR_CR1 0x094 /* Start addr. of src image 1 (Cr) */ -+#define IEP_SRC_ADDR_Y_ITEMP 0x098 /* Start addr. of src image(Y int part) */ -+#define IEP_SRC_ADDR_CBCR_ITEMP 0x09c /* Start addr. of src image(CBCR int part) */ -+#define IEP_SRC_ADDR_CR_ITEMP 0x0a0 /* Start addr. of src image(CR int part) */ -+#define IEP_SRC_ADDR_Y_FTEMP 0x0a4 /* Start addr. of src image(Y frac part) */ -+#define IEP_SRC_ADDR_CBCR_FTEMP 0x0a8 /* Start addr. of src image(CBCR frac part) */ -+#define IEP_SRC_ADDR_CR_FTEMP 0x0ac /* Start addr. of src image(CR frac part) */ -+ -+#define IEP_DST_ADDR_Y_RGB 0x0b0 /* Start addr. of dst image 0 (Y/RGB) */ -+#define IEP_DST_ADDR_CBCR 0x0b4 /* Start addr. of dst image 0 (Cb/Cr) */ -+#define IEP_DST_ADDR_CR 0x0b8 /* Start addr. of dst image 0 (Cr) */ -+#define IEP_DST_ADDR_Y1 0x0bc /* Start addr. of dst image 1 (Y) */ -+#define IEP_DST_ADDR_CBCR1 0x0c0 /* Start addr. of dst image 1 (Cb/Cr) */ -+#define IEP_DST_ADDR_CR1 0x0c4 /* Start addr. of dst image 1 (Cr) */ -+#define IEP_DST_ADDR_Y_ITEMP 0x0c8 /* Start addr. of dst image(Y int part) */ -+#define IEP_DST_ADDR_CBCR_ITEMP 0x0cc /* Start addr. of dst image(CBCR int part)*/ -+#define IEP_DST_ADDR_CR_ITEMP 0x0d0 /* Start addr. of dst image(CR int part) */ -+#define IEP_DST_ADDR_Y_FTEMP 0x0d4 /* Start addr. of dst image(Y frac part) */ -+#define IEP_DST_ADDR_CBCR_FTEMP 0x0d8 /* Start addr. of dst image(CBCR frac part) */ -+#define IEP_DST_ADDR_CR_FTEMP 0x0dc /* Start addr. of dst image(CR frac part)*/ -+ -+#define IEP_DEIN_MTN_TAB0 0x0e0 /* Deinterlace motion table0 */ -+#define IEP_DEIN_MTN_TAB1 0x0e4 /* Deinterlace motion table1 */ -+#define IEP_DEIN_MTN_TAB2 0x0e8 /* Deinterlace motion table2 */ -+#define IEP_DEIN_MTN_TAB3 0x0ec /* Deinterlace motion table3 */ -+#define IEP_DEIN_MTN_TAB4 0x0f0 /* Deinterlace motion table4 */ -+#define IEP_DEIN_MTN_TAB5 0x0f4 /* Deinterlace motion table5 */ -+#define IEP_DEIN_MTN_TAB6 0x0f8 /* Deinterlace motion table6 */ -+#define IEP_DEIN_MTN_TAB7 0x0fc /* Deinterlace motion table7 */ -+ -+#define IEP_ENH_CG_TAB 0x100 /* Contrast and gamma enhancement table */ -+#define IEP_ENH_DDE_COE0 0x400 /* Denoise,detail and edge enhancement coefficient */ -+#define IEP_ENH_DDE_COE1 0x500 /* Denoise,detail and edge enhancement coefficient1 */ -+ -+#define IEP_INT_MASK (IEP_INT_FRAME_DONE) -+ -+/* IEP colorformats */ -+#define IEP_COLOR_FMT_XRGB 0U -+#define IEP_COLOR_FMT_RGB565 1U -+#define IEP_COLOR_FMT_YUV422 2U -+#define IEP_COLOR_FMT_YUV420 3U -+ -+/* IEP YUV color swaps */ -+#define IEP_YUV_SWP_SP_UV 0U -+#define IEP_YUV_SWP_SP_VU 1U -+#define IEP_YUV_SWP_P 2U -+ -+/* IEP XRGB color swaps */ -+#define XRGB_SWP_XRGB 0U -+#define XRGB_SWP_XBGR 1U -+#define XRGB_SWP_BGRX 2U -+ -+/* IEP RGB565 color swaps */ -+#define RGB565_SWP_RGB 0U -+#define RGB565_SWP_BGR 1U -+ -+#define FMT_IS_YUV(fmt) (fmt == IEP_COLOR_FMT_XRGB || fmt == IEP_COLOR_FMT_RGB565 ? 0 : 1) -+ -+#define IEP_IMG_SIZE(w, h) (((w - 1) & 0x1fff) << 0 | \ -+ ((h - 1) & 0x1fff) << 16) -+ -+#define IEP_VIR_WIDTH(src_w, dst_w) (((src_w / 4) & 0x1fff) << 0 | \ -+ ((dst_w / 4) & 0x1fff) << 16) -+ -+#define IEP_Y_STRIDE(w, h) (w * h) -+#define IEP_UV_STRIDE(w, h, fac) (w * h + w * h / fac) -+ -+#define IEP_SRC_FMT_SWP_MASK(f) (FMT_IS_YUV(f) ? IEP_SRC_YUV_SWP_MASK : IEP_SRC_RGB_SWP_MASK) -+#define IEP_DST_FMT_SWP_MASK(f) (FMT_IS_YUV(f) ? IEP_DST_YUV_SWP_MASK : IEP_DST_RGB_SWP_MASK) -+ -+#define IEP_SRC_FMT(f, swp) (f << IEP_SRC_FMT_SHFT | \ -+ (swp << (FMT_IS_YUV(f) ? IEP_SRC_YUV_SWP_SHFT : IEP_SRC_RGB_SWP_SHFT))) -+#define IEP_DST_FMT(f, swp) (f << IEP_DST_FMT_SHFT | \ -+ (swp << (FMT_IS_YUV(f) ? IEP_DST_YUV_SWP_SHFT : IEP_DST_RGB_SWP_SHFT))) -+ -+/* IEP DEINTERLACE MODES */ -+#define IEP_DEIN_MODE_YUV 0U -+#define IEP_DEIN_MODE_I4O2 1U -+#define IEP_DEIN_MODE_I4O1B 2U -+#define IEP_DEIN_MODE_I4O1T 3U -+#define IEP_DEIN_MODE_I2O1B 4U -+#define IEP_DEIN_MODE_I2O1T 5U -+#define IEP_DEIN_MODE_BYPASS 6U -+ -+#define IEP_DEIN_IN_FIELDS_2 2U -+#define IEP_DEIN_IN_FIELDS_4 4U -+ -+#define IEP_DEIN_OUT_FRAMES_1 1U -+#define IEP_DEIN_OUT_FRAMES_2 2U -+ -+/* values taken from BSP driver */ -+static const u32 default_dein_motion_tbl[][2] = { -+ { IEP_DEIN_MTN_TAB0, 0x40404040 }, -+ { IEP_DEIN_MTN_TAB1, 0x3c3e3f3f }, -+ { IEP_DEIN_MTN_TAB2, 0x3336393b }, -+ { IEP_DEIN_MTN_TAB3, 0x272a2d31 }, -+ { IEP_DEIN_MTN_TAB4, 0x181c2023 }, -+ { IEP_DEIN_MTN_TAB5, 0x0c0e1215 }, -+ { IEP_DEIN_MTN_TAB6, 0x03040609 }, -+ { IEP_DEIN_MTN_TAB7, 0x00000001 }, -+ -+}; -+ -+#define IEP_DEIN_IN_IMG0_Y(bff) (bff ? IEP_SRC_ADDR_Y_RGB : IEP_SRC_ADDR_Y1) -+#define IEP_DEIN_IN_IMG0_CBCR(bff) (bff ? IEP_SRC_ADDR_CBCR : IEP_SRC_ADDR_CBCR1) -+#define IEP_DEIN_IN_IMG0_CR(bff) (bff ? IEP_SRC_ADDR_CR : IEP_SRC_ADDR_CR1) -+#define IEP_DEIN_IN_IMG1_Y(bff) (IEP_DEIN_IN_IMG0_Y(!bff)) -+#define IEP_DEIN_IN_IMG1_CBCR(bff) (IEP_DEIN_IN_IMG0_CBCR(!bff)) -+#define IEP_DEIN_IN_IMG1_CR(bff) (IEP_DEIN_IN_IMG0_CR(!bff)) -+ -+#define IEP_DEIN_OUT_IMG0_Y(bff) (bff ? IEP_DST_ADDR_Y1 : IEP_DST_ADDR_Y_RGB) -+#define IEP_DEIN_OUT_IMG0_CBCR(bff) (bff ? IEP_DST_ADDR_CBCR1 : IEP_DST_ADDR_CBCR) -+#define IEP_DEIN_OUT_IMG0_CR(bff) (bff ? IEP_DST_ADDR_CR1 : IEP_DST_ADDR_CR) -+#define IEP_DEIN_OUT_IMG1_Y(bff) (IEP_DEIN_OUT_IMG0_Y(!bff)) -+#define IEP_DEIN_OUT_IMG1_CBCR(bff) (IEP_DEIN_OUT_IMG0_CBCR(!bff)) -+#define IEP_DEIN_OUT_IMG1_CR(bff) (IEP_DEIN_OUT_IMG0_CR(!bff)) -+ -+#define IEP_DEIN_MODE(m) (m << IEP_DEIN_MODE_SHFT) -+ -+#define IEP_DEIN_IN_MODE_FIELDS(m) ((m == IEP_DEIN_MODE_I4O1T || m == IEP_DEIN_MODE_I4O1B \ -+ || m == IEP_DEIN_MODE_I4O2) \ -+ ? IEP_DEIN_IN_FIELDS_4 : IEP_DEIN_IN_FIELDS_2) -+ -+#define IEP_DEIN_OUT_MODE_FRAMES(m) (m == IEP_DEIN_MODE_I4O2 \ -+ ? IEP_DEIN_OUT_FRAMES_2 : IEP_DEIN_OUT_FRAMES_1) -+ -+#define IEP_DEIN_OUT_MODE_1FRM_TOP_FIELD(m) (m == IEP_DEIN_MODE_I4O1T || IEP_DEIN_MODE_I2O1T \ -+ ? 1 : 0) -+ -+#define IEP_DEIN_EDGE_INTPOL_RADIUS(r) (r << IEP_DEIN_EDGE_INTPOL_RADIUS_SHFT) -+ -+#define IEP_DEIN_HIGH_FREQ(f) (f << IEP_DEIN_HIGH_FREQ_SHFT) -+ -+/* YUV Enhance video modes */ -+#define VIDEO_MODE_BLACK_SCREEN 0U -+#define VIDEO_MODE_BLUE_SCREEN 1U -+#define VIDEO_MODE_COLOR_BARS 2U -+#define VIDEO_MODE_NORMAL_VIDEO 3U -+ -+#define YUV_VIDEO_MODE(m) ((m << IEP_YUV_VIDEO_MODE_SHFT) & IEP_YUV_VIDEO_MODE_MASK) -+#define YUV_BRIGHTNESS(v) ((v << IEP_YUV_BRIGHTNESS_SHFT) & IEP_YUV_BRIGHTNESS_MASK) -+#define YUV_CONTRAST(v) ((v << IEP_YUV_CONTRAST_SHFT) & IEP_YUV_CONTRAST_MASK) -+#define YUV_SATURATION(v) ((v << IEP_YUV_SATURATION_SHFT) & IEP_YUV_SATURATION_MASK) -+#define YUV_COS_HUE(v) ((v << IEP_YUV_COS_HUE_SHFT) & IEP_YUV_COS_HUE_MASK) -+#define YUV_SIN_HUE(v) ((v << IEP_YUV_SIN_HUE_SHFT) & IEP_YUV_SIN_HUE_MASK) -+ -+#endif -diff --git a/drivers/media/platform/rockchip/iep/iep.c b/drivers/media/platform/rockchip/iep/iep.c -new file mode 100644 -index 000000000000..f4b9320733be ---- /dev/null -+++ b/drivers/media/platform/rockchip/iep/iep.c -@@ -0,0 +1,1089 @@ -+// SPDX-License-Identifier: GPL-2.0-only -+/* -+ * Rockchip Image Enhancement Processor (IEP) driver -+ * -+ * Copyright (C) 2020 Alex Bee -+ * -+ * Based on Allwinner sun8i deinterlacer with scaler driver -+ * Copyright (C) 2019 Jernej Skrabec -+ * -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include "iep-regs.h" -+#include "iep.h" -+ -+static struct iep_fmt formats[] = { -+ { -+ .fourcc = V4L2_PIX_FMT_NV12, -+ .color_swap = IEP_YUV_SWP_SP_UV, -+ .hw_format = IEP_COLOR_FMT_YUV420, -+ .depth = 12, -+ .uv_factor = 4, -+ }, -+ { -+ .fourcc = V4L2_PIX_FMT_NV21, -+ .color_swap = IEP_YUV_SWP_SP_VU, -+ .hw_format = IEP_COLOR_FMT_YUV420, -+ .depth = 12, -+ .uv_factor = 4, -+ }, -+ { -+ .fourcc = V4L2_PIX_FMT_NV16, -+ .color_swap = IEP_YUV_SWP_SP_UV, -+ .hw_format = IEP_COLOR_FMT_YUV422, -+ .depth = 16, -+ .uv_factor = 2, -+ }, -+ { -+ .fourcc = V4L2_PIX_FMT_NV61, -+ .color_swap = IEP_YUV_SWP_SP_VU, -+ .hw_format = IEP_COLOR_FMT_YUV422, -+ .depth = 16, -+ .uv_factor = 2, -+ }, -+ { -+ .fourcc = V4L2_PIX_FMT_YUV420, -+ .color_swap = IEP_YUV_SWP_P, -+ .hw_format = IEP_COLOR_FMT_YUV420, -+ .depth = 12, -+ .uv_factor = 4, -+ }, -+ { -+ .fourcc = V4L2_PIX_FMT_YUV422P, -+ .color_swap = IEP_YUV_SWP_P, -+ .hw_format = IEP_COLOR_FMT_YUV422, -+ .depth = 16, -+ .uv_factor = 2, -+ }, -+}; -+ -+static struct iep_fmt *iep_fmt_find(struct v4l2_pix_format *pix_fmt) -+{ -+ unsigned int i; -+ -+ for (i = 0; i < ARRAY_SIZE(formats); i++) { -+ if (formats[i].fourcc == pix_fmt->pixelformat) -+ return &formats[i]; -+ } -+ -+ return NULL; -+} -+ -+static bool iep_check_pix_format(u32 pixelformat) -+{ -+ unsigned int i; -+ -+ for (i = 0; i < ARRAY_SIZE(formats); i++) -+ if (formats[i].fourcc == pixelformat) -+ return true; -+ -+ return false; -+} -+ -+static struct vb2_v4l2_buffer *iep_m2m_next_dst_buf(struct iep_ctx *ctx) -+{ -+ struct vb2_v4l2_buffer *dst_buf = v4l2_m2m_next_dst_buf(ctx->fh.m2m_ctx); -+ -+ /* application has set a dst sequence: take it as start point */ -+ if (ctx->dst_sequence == 0 && dst_buf->sequence > 0) -+ ctx->dst_sequence = dst_buf->sequence; -+ -+ dst_buf->sequence = ctx->dst_sequence++; -+ -+ return dst_buf; -+} -+ -+static void iep_m2m_dst_bufs_done(struct iep_ctx *ctx, enum vb2_buffer_state state) -+{ -+ if (ctx->dst0_buf) { -+ v4l2_m2m_buf_done(ctx->dst0_buf, state); -+ ctx->dst_buffs_done++; -+ ctx->dst0_buf = NULL; -+ } -+ -+ if (ctx->dst1_buf) { -+ v4l2_m2m_buf_done(ctx->dst1_buf, state); -+ ctx->dst_buffs_done++; -+ ctx->dst1_buf = NULL; -+ } -+} -+ -+static void iep_setup_formats(struct iep_ctx *ctx) -+{ -+ /* setup src dimensions */ -+ iep_write(ctx->iep, IEP_SRC_IMG_SIZE, -+ IEP_IMG_SIZE(ctx->src_fmt.pix.width, ctx->src_fmt.pix.height)); -+ -+ /* setup dst dimensions */ -+ iep_write(ctx->iep, IEP_DST_IMG_SIZE, -+ IEP_IMG_SIZE(ctx->dst_fmt.pix.width, ctx->dst_fmt.pix.height)); -+ -+ /* setup virtual width */ -+ iep_write(ctx->iep, IEP_VIR_IMG_WIDTH, -+ IEP_VIR_WIDTH(ctx->src_fmt.pix.width, ctx->dst_fmt.pix.width)); -+ -+ /* setup src format */ -+ iep_shadow_mod(ctx->iep, IEP_CONFIG1, IEP_RAW_CONFIG1, -+ IEP_SRC_FMT_MASK | IEP_SRC_FMT_SWP_MASK(ctx->src_fmt.hw_fmt->hw_format), -+ IEP_SRC_FMT(ctx->src_fmt.hw_fmt->hw_format, -+ ctx->src_fmt.hw_fmt->color_swap)); -+ /* setup dst format */ -+ iep_shadow_mod(ctx->iep, IEP_CONFIG1, IEP_RAW_CONFIG1, -+ IEP_DST_FMT_MASK | IEP_DST_FMT_SWP_MASK(ctx->dst_fmt.hw_fmt->hw_format), -+ IEP_DST_FMT(ctx->dst_fmt.hw_fmt->hw_format, -+ ctx->dst_fmt.hw_fmt->color_swap)); -+ -+ ctx->fmt_changed = false; -+} -+ -+static void iep_dein_init(struct rockchip_iep *iep) -+{ -+ unsigned int i; -+ -+ /* values taken from BSP driver */ -+ iep_shadow_mod(iep, IEP_CONFIG0, IEP_RAW_CONFIG0, -+ (IEP_DEIN_EDGE_INTPOL_SMTH_EN | -+ IEP_DEIN_EDGE_INTPOL_RADIUS_MASK | -+ IEP_DEIN_HIGH_FREQ_EN | -+ IEP_DEIN_HIGH_FREQ_MASK), -+ (IEP_DEIN_EDGE_INTPOL_SMTH_EN | -+ IEP_DEIN_EDGE_INTPOL_RADIUS(3) | -+ IEP_DEIN_HIGH_FREQ_EN | -+ IEP_DEIN_HIGH_FREQ(64))); -+ -+ for (i = 0; i < ARRAY_SIZE(default_dein_motion_tbl); i++) -+ iep_write(iep, default_dein_motion_tbl[i][0], -+ default_dein_motion_tbl[i][1]); -+} -+ -+static void iep_init(struct rockchip_iep *iep) -+{ -+ iep_write(iep, IEP_CONFIG0, -+ IEP_DEIN_MODE(IEP_DEIN_MODE_BYPASS) // | -+ //IEP_YUV_ENHNC_EN -+ ); -+ -+ /* TODO: B/S/C/H works -+ * only in 1-frame-out modes -+ iep_write(iep, IEP_ENH_YUV_CNFG_0, -+ YUV_BRIGHTNESS(0) | -+ YUV_CONTRAST(128) | -+ YUV_SATURATION(128)); -+ -+ iep_write(iep, IEP_ENH_YUV_CNFG_1, -+ YUV_COS_HUE(255) | -+ YUV_SIN_HUE(255)); -+ -+ iep_write(iep, IEP_ENH_YUV_CNFG_2, -+ YUV_VIDEO_MODE(VIDEO_MODE_NORMAL_VIDEO)); -+ -+ */ -+ -+ /* reset frame counter */ -+ iep_write(iep, IEP_FRM_CNT, 0); -+} -+ -+static void iep_device_run(void *priv) -+{ -+ struct iep_ctx *ctx = priv; -+ struct rockchip_iep *iep = ctx->iep; -+ struct vb2_v4l2_buffer *src, *dst; -+ unsigned int dein_mode; -+ dma_addr_t addr; -+ -+ if (ctx->fmt_changed) -+ iep_setup_formats(ctx); -+ -+ if (ctx->prev_src_buf) -+ dein_mode = IEP_DEIN_MODE_I4O2; -+ else -+ dein_mode = ctx->field_bff ? IEP_DEIN_MODE_I2O1B : IEP_DEIN_MODE_I2O1T; -+ -+ iep_shadow_mod(iep, IEP_CONFIG0, IEP_RAW_CONFIG0, -+ IEP_DEIN_MODE_MASK, IEP_DEIN_MODE(dein_mode)); -+ -+ /* sync RAW_xxx registers with actual used */ -+ iep_write(iep, IEP_CONFIG_DONE, 1); -+ -+ /* setup src buff(s)/addresses */ -+ src = v4l2_m2m_next_src_buf(ctx->fh.m2m_ctx); -+ addr = vb2_dma_contig_plane_dma_addr(&src->vb2_buf, 0); -+ -+ iep_write(iep, IEP_DEIN_IN_IMG0_Y(ctx->field_bff), addr); -+ -+ iep_write(iep, IEP_DEIN_IN_IMG0_CBCR(ctx->field_bff), -+ addr + ctx->src_fmt.y_stride); -+ -+ iep_write(iep, IEP_DEIN_IN_IMG0_CR(ctx->field_bff), -+ addr + ctx->src_fmt.uv_stride); -+ -+ if (IEP_DEIN_IN_MODE_FIELDS(dein_mode) == IEP_DEIN_IN_FIELDS_4) -+ addr = vb2_dma_contig_plane_dma_addr(&ctx->prev_src_buf->vb2_buf, 0); -+ -+ iep_write(iep, IEP_DEIN_IN_IMG1_Y(ctx->field_bff), addr); -+ -+ iep_write(iep, IEP_DEIN_IN_IMG1_CBCR(ctx->field_bff), -+ addr + ctx->src_fmt.y_stride); -+ -+ iep_write(iep, IEP_DEIN_IN_IMG1_CR(ctx->field_bff), -+ addr + ctx->src_fmt.uv_stride); -+ -+ /* setup dst buff(s)/addresses */ -+ dst = iep_m2m_next_dst_buf(ctx); -+ addr = vb2_dma_contig_plane_dma_addr(&dst->vb2_buf, 0); -+ -+ if (IEP_DEIN_OUT_MODE_FRAMES(dein_mode) == IEP_DEIN_OUT_FRAMES_2) { -+ v4l2_m2m_buf_copy_metadata(ctx->prev_src_buf, dst, true); -+ -+ iep_write(iep, IEP_DEIN_OUT_IMG0_Y(ctx->field_bff), addr); -+ -+ iep_write(iep, IEP_DEIN_OUT_IMG0_CBCR(ctx->field_bff), -+ addr + ctx->dst_fmt.y_stride); -+ -+ iep_write(iep, IEP_DEIN_OUT_IMG0_CR(ctx->field_bff), -+ addr + ctx->dst_fmt.uv_stride); -+ -+ ctx->dst0_buf = v4l2_m2m_dst_buf_remove(ctx->fh.m2m_ctx); -+ -+ dst = iep_m2m_next_dst_buf(ctx); -+ addr = vb2_dma_contig_plane_dma_addr(&dst->vb2_buf, 0); -+ } -+ -+ v4l2_m2m_buf_copy_metadata(src, dst, true); -+ -+ iep_write(iep, IEP_DEIN_OUT_IMG1_Y(ctx->field_bff), addr); -+ -+ iep_write(iep, IEP_DEIN_OUT_IMG1_CBCR(ctx->field_bff), -+ addr + ctx->dst_fmt.y_stride); -+ -+ iep_write(iep, IEP_DEIN_OUT_IMG1_CR(ctx->field_bff), -+ addr + ctx->dst_fmt.uv_stride); -+ -+ ctx->dst1_buf = v4l2_m2m_dst_buf_remove(ctx->fh.m2m_ctx); -+ -+ iep_mod(ctx->iep, IEP_INT, IEP_INT_FRAME_DONE_EN, -+ IEP_INT_FRAME_DONE_EN); -+ -+ /* start HW */ -+ iep_write(iep, IEP_FRM_START, 1); -+} -+ -+static int iep_job_ready(void *priv) -+{ -+ struct iep_ctx *ctx = priv; -+ -+ return v4l2_m2m_num_dst_bufs_ready(ctx->fh.m2m_ctx) >= 2 && -+ v4l2_m2m_num_src_bufs_ready(ctx->fh.m2m_ctx) >= 1; -+} -+ -+static void iep_job_abort(void *priv) -+{ -+ struct iep_ctx *ctx = priv; -+ -+ /* Will cancel the transaction in the next interrupt handler */ -+ ctx->job_abort = true; -+} -+ -+static const struct v4l2_m2m_ops iep_m2m_ops = { -+ .device_run = iep_device_run, -+ .job_ready = iep_job_ready, -+ .job_abort = iep_job_abort, -+}; -+ -+static int iep_queue_setup(struct vb2_queue *vq, unsigned int *nbuffers, -+ unsigned int *nplanes, unsigned int sizes[], -+ struct device *alloc_devs[]) -+{ -+ struct iep_ctx *ctx = vb2_get_drv_priv(vq); -+ struct v4l2_pix_format *pix_fmt; -+ -+ if (V4L2_TYPE_IS_OUTPUT(vq->type)) -+ pix_fmt = &ctx->src_fmt.pix; -+ else -+ pix_fmt = &ctx->dst_fmt.pix; -+ -+ if (*nplanes) { -+ if (sizes[0] < pix_fmt->sizeimage) -+ return -EINVAL; -+ } else { -+ sizes[0] = pix_fmt->sizeimage; -+ *nplanes = 1; -+ } -+ -+ return 0; -+} -+ -+static int iep_buf_prepare(struct vb2_buffer *vb) -+{ -+ struct vb2_queue *vq = vb->vb2_queue; -+ struct iep_ctx *ctx = vb2_get_drv_priv(vq); -+ struct v4l2_pix_format *pix_fmt; -+ -+ if (V4L2_TYPE_IS_OUTPUT(vq->type)) -+ pix_fmt = &ctx->src_fmt.pix; -+ else -+ pix_fmt = &ctx->dst_fmt.pix; -+ -+ if (vb2_plane_size(vb, 0) < pix_fmt->sizeimage) -+ return -EINVAL; -+ -+ /* set bytesused for capture buffers */ -+ if (!V4L2_TYPE_IS_OUTPUT(vq->type)) -+ vb2_set_plane_payload(vb, 0, pix_fmt->sizeimage); -+ -+ return 0; -+} -+ -+static void iep_buf_queue(struct vb2_buffer *vb) -+{ -+ struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb); -+ struct iep_ctx *ctx = vb2_get_drv_priv(vb->vb2_queue); -+ -+ v4l2_m2m_buf_queue(ctx->fh.m2m_ctx, vbuf); -+} -+ -+static void iep_queue_cleanup(struct vb2_queue *vq, u32 state) -+{ -+ struct iep_ctx *ctx = vb2_get_drv_priv(vq); -+ struct vb2_v4l2_buffer *vbuf; -+ -+ do { -+ if (V4L2_TYPE_IS_OUTPUT(vq->type)) -+ vbuf = v4l2_m2m_src_buf_remove(ctx->fh.m2m_ctx); -+ else -+ vbuf = v4l2_m2m_dst_buf_remove(ctx->fh.m2m_ctx); -+ -+ if (vbuf) -+ v4l2_m2m_buf_done(vbuf, state); -+ } while (vbuf); -+ -+ if (V4L2_TYPE_IS_OUTPUT(vq->type) && ctx->prev_src_buf) -+ v4l2_m2m_buf_done(ctx->prev_src_buf, state); -+ else -+ iep_m2m_dst_bufs_done(ctx, state); -+} -+ -+static int iep_start_streaming(struct vb2_queue *vq, unsigned int count) -+{ -+ struct iep_ctx *ctx = vb2_get_drv_priv(vq); -+ struct device *dev = ctx->iep->dev; -+ int ret; -+ -+ if (V4L2_TYPE_IS_OUTPUT(vq->type)) { -+ ret = pm_runtime_get_sync(dev); -+ if (ret < 0) { -+ dev_err(dev, "Failed to enable module\n"); -+ goto err_runtime_get; -+ } -+ -+ ctx->field_order_bff = -+ ctx->src_fmt.pix.field == V4L2_FIELD_INTERLACED_BT; -+ ctx->field_bff = ctx->field_order_bff; -+ -+ ctx->src_sequence = 0; -+ ctx->dst_sequence = 0; -+ -+ ctx->prev_src_buf = NULL; -+ -+ ctx->dst0_buf = NULL; -+ ctx->dst1_buf = NULL; -+ ctx->dst_buffs_done = 0; -+ -+ ctx->job_abort = false; -+ -+ iep_init(ctx->iep); -+ //if (ctx->src_fmt.pix.field != ctx->dst_fmt.pix.field) -+ iep_dein_init(ctx->iep); -+ } -+ -+ return 0; -+ -+err_runtime_get: -+ iep_queue_cleanup(vq, VB2_BUF_STATE_QUEUED); -+ -+ return ret; -+} -+ -+static void iep_stop_streaming(struct vb2_queue *vq) -+{ -+ struct iep_ctx *ctx = vb2_get_drv_priv(vq); -+ -+ if (V4L2_TYPE_IS_OUTPUT(vq->type)) { -+ pm_runtime_mark_last_busy(ctx->iep->dev); -+ pm_runtime_put_autosuspend(ctx->iep->dev); -+ } -+ -+ iep_queue_cleanup(vq, VB2_BUF_STATE_ERROR); -+} -+ -+static const struct vb2_ops iep_qops = { -+ .queue_setup = iep_queue_setup, -+ .buf_prepare = iep_buf_prepare, -+ .buf_queue = iep_buf_queue, -+ .start_streaming = iep_start_streaming, -+ .stop_streaming = iep_stop_streaming, -+ .wait_prepare = vb2_ops_wait_prepare, -+ .wait_finish = vb2_ops_wait_finish, -+}; -+ -+static int iep_queue_init(void *priv, struct vb2_queue *src_vq, -+ struct vb2_queue *dst_vq) -+{ -+ struct iep_ctx *ctx = priv; -+ int ret; -+ -+ src_vq->type = V4L2_BUF_TYPE_VIDEO_OUTPUT; -+ src_vq->dma_attrs = DMA_ATTR_ALLOC_SINGLE_PAGES | -+ DMA_ATTR_NO_KERNEL_MAPPING; -+ src_vq->io_modes = VB2_MMAP | VB2_DMABUF; -+ src_vq->drv_priv = ctx; -+ src_vq->buf_struct_size = sizeof(struct v4l2_m2m_buffer); -+ src_vq->min_queued_buffers = 1; -+ src_vq->ops = &iep_qops; -+ src_vq->mem_ops = &vb2_dma_contig_memops; -+ src_vq->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_COPY; -+ src_vq->lock = &ctx->iep->mutex; -+ src_vq->dev = ctx->iep->v4l2_dev.dev; -+ -+ ret = vb2_queue_init(src_vq); -+ if (ret) -+ return ret; -+ -+ dst_vq->dma_attrs = DMA_ATTR_ALLOC_SINGLE_PAGES | -+ DMA_ATTR_NO_KERNEL_MAPPING; -+ dst_vq->type = V4L2_BUF_TYPE_VIDEO_CAPTURE; -+ dst_vq->io_modes = VB2_MMAP | VB2_DMABUF; -+ dst_vq->drv_priv = ctx; -+ dst_vq->buf_struct_size = sizeof(struct v4l2_m2m_buffer); -+ dst_vq->min_queued_buffers = 2; -+ dst_vq->ops = &iep_qops; -+ dst_vq->mem_ops = &vb2_dma_contig_memops; -+ dst_vq->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_COPY; -+ dst_vq->lock = &ctx->iep->mutex; -+ dst_vq->dev = ctx->iep->v4l2_dev.dev; -+ -+ ret = vb2_queue_init(dst_vq); -+ if (ret) -+ return ret; -+ -+ return 0; -+} -+ -+static void iep_prepare_format(struct v4l2_pix_format *pix_fmt) -+{ -+ unsigned int height = pix_fmt->height; -+ unsigned int width = pix_fmt->width; -+ unsigned int sizeimage, bytesperline; -+ -+ struct iep_fmt *hw_fmt = iep_fmt_find(pix_fmt); -+ -+ if (!hw_fmt) { -+ hw_fmt = &formats[0]; -+ pix_fmt->pixelformat = hw_fmt->fourcc; -+ } -+ -+ width = ALIGN(clamp(width, IEP_MIN_WIDTH, -+ IEP_MAX_WIDTH), 16); -+ height = ALIGN(clamp(height, IEP_MIN_HEIGHT, -+ IEP_MAX_HEIGHT), 16); -+ -+ bytesperline = FMT_IS_YUV(hw_fmt->hw_format) -+ ? width : (width * hw_fmt->depth) >> 3; -+ -+ sizeimage = height * (width * hw_fmt->depth) >> 3; -+ -+ pix_fmt->width = width; -+ pix_fmt->height = height; -+ pix_fmt->bytesperline = bytesperline; -+ pix_fmt->sizeimage = sizeimage; -+} -+ -+static int iep_open(struct file *file) -+{ -+ struct rockchip_iep *iep = video_drvdata(file); -+ struct iep_ctx *ctx = NULL; -+ -+ int ret; -+ -+ if (mutex_lock_interruptible(&iep->mutex)) -+ return -ERESTARTSYS; -+ -+ ctx = kzalloc(sizeof(*ctx), GFP_KERNEL); -+ if (!ctx) { -+ mutex_unlock(&iep->mutex); -+ return -ENOMEM; -+ } -+ -+ /* default output format */ -+ ctx->src_fmt.pix.pixelformat = formats[0].fourcc; -+ ctx->src_fmt.pix.field = V4L2_FIELD_INTERLACED; -+ ctx->src_fmt.pix.width = IEP_DEFAULT_WIDTH; -+ ctx->src_fmt.pix.height = IEP_DEFAULT_HEIGHT; -+ iep_prepare_format(&ctx->src_fmt.pix); -+ ctx->src_fmt.hw_fmt = &formats[0]; -+ ctx->dst_fmt.y_stride = IEP_Y_STRIDE(ctx->src_fmt.pix.width, ctx->src_fmt.pix.height); -+ ctx->dst_fmt.uv_stride = IEP_UV_STRIDE(ctx->src_fmt.pix.width, ctx->src_fmt.pix.height, -+ ctx->src_fmt.hw_fmt->uv_factor); -+ -+ /* default capture format */ -+ ctx->dst_fmt.pix.pixelformat = formats[0].fourcc; -+ ctx->dst_fmt.pix.field = V4L2_FIELD_NONE; -+ ctx->dst_fmt.pix.width = IEP_DEFAULT_WIDTH; -+ ctx->dst_fmt.pix.height = IEP_DEFAULT_HEIGHT; -+ iep_prepare_format(&ctx->dst_fmt.pix); -+ ctx->dst_fmt.hw_fmt = &formats[0]; -+ ctx->dst_fmt.y_stride = IEP_Y_STRIDE(ctx->dst_fmt.pix.width, ctx->dst_fmt.pix.height); -+ ctx->dst_fmt.uv_stride = IEP_UV_STRIDE(ctx->dst_fmt.pix.width, ctx->dst_fmt.pix.height, -+ ctx->dst_fmt.hw_fmt->uv_factor); -+ /* ensure fmts are written to HW */ -+ ctx->fmt_changed = true; -+ -+ v4l2_fh_init(&ctx->fh, video_devdata(file)); -+ file->private_data = &ctx->fh; -+ ctx->iep = iep; -+ -+ ctx->fh.m2m_ctx = v4l2_m2m_ctx_init(iep->m2m_dev, ctx, -+ &iep_queue_init); -+ -+ if (IS_ERR(ctx->fh.m2m_ctx)) { -+ ret = PTR_ERR(ctx->fh.m2m_ctx); -+ goto err_free; -+ } -+ -+ v4l2_fh_add(&ctx->fh); -+ -+ mutex_unlock(&iep->mutex); -+ -+ return 0; -+ -+err_free: -+ kfree(ctx); -+ mutex_unlock(&iep->mutex); -+ -+ return ret; -+} -+ -+static int iep_release(struct file *file) -+{ -+ struct rockchip_iep *iep = video_drvdata(file); -+ struct iep_ctx *ctx = container_of(file->private_data, -+ struct iep_ctx, fh); -+ -+ mutex_lock(&iep->mutex); -+ -+ v4l2_fh_del(&ctx->fh); -+ v4l2_fh_exit(&ctx->fh); -+ v4l2_m2m_ctx_release(ctx->fh.m2m_ctx); -+ kfree(ctx); -+ -+ mutex_unlock(&iep->mutex); -+ return 0; -+} -+ -+static const struct v4l2_file_operations iep_fops = { -+ .owner = THIS_MODULE, -+ .open = iep_open, -+ .release = iep_release, -+ .poll = v4l2_m2m_fop_poll, -+ .unlocked_ioctl = video_ioctl2, -+ .mmap = v4l2_m2m_fop_mmap, -+}; -+ -+static int iep_querycap(struct file *file, void *priv, -+ struct v4l2_capability *cap) -+{ -+ strscpy(cap->driver, IEP_NAME, sizeof(cap->driver)); -+ strscpy(cap->card, IEP_NAME, sizeof(cap->card)); -+ snprintf(cap->bus_info, sizeof(cap->bus_info), -+ "platform:%s", IEP_NAME); -+ -+ return 0; -+} -+ -+static int iep_enum_fmt(struct file *file, void *priv, -+ struct v4l2_fmtdesc *f) -+{ -+ struct iep_fmt *fmt; -+ -+ if (f->index < ARRAY_SIZE(formats)) { -+ fmt = &formats[f->index]; -+ f->pixelformat = fmt->fourcc; -+ -+ return 0; -+ } -+ -+ return -EINVAL; -+} -+ -+static int iep_enum_framesizes(struct file *file, void *priv, -+ struct v4l2_frmsizeenum *fsize) -+{ -+ if (fsize->index != 0) -+ return -EINVAL; -+ -+ if (!iep_check_pix_format(fsize->pixel_format)) -+ return -EINVAL; -+ -+ fsize->type = V4L2_FRMSIZE_TYPE_STEPWISE; -+ -+ fsize->stepwise.min_width = IEP_MIN_WIDTH; -+ fsize->stepwise.max_width = IEP_MAX_WIDTH; -+ fsize->stepwise.step_width = 16; -+ -+ fsize->stepwise.min_height = IEP_MIN_HEIGHT; -+ fsize->stepwise.max_height = IEP_MAX_HEIGHT; -+ fsize->stepwise.step_height = 16; -+ -+ return 0; -+} -+ -+static inline struct iep_ctx *iep_file2ctx(struct file *file) -+{ -+ return container_of(file->private_data, struct iep_ctx, fh); -+} -+ -+static int iep_g_fmt_vid_cap(struct file *file, void *priv, -+ struct v4l2_format *f) -+{ -+ struct iep_ctx *ctx = iep_file2ctx(file); -+ -+ f->fmt.pix = ctx->dst_fmt.pix; -+ -+ return 0; -+} -+ -+static int iep_g_fmt_vid_out(struct file *file, void *priv, -+ struct v4l2_format *f) -+{ -+ struct iep_ctx *ctx = iep_file2ctx(file); -+ -+ f->fmt.pix = ctx->src_fmt.pix; -+ -+ return 0; -+} -+ -+static int iep_try_fmt_vid_cap(struct file *file, void *priv, -+ struct v4l2_format *f) -+{ -+ f->fmt.pix.field = V4L2_FIELD_NONE; -+ iep_prepare_format(&f->fmt.pix); -+ -+ return 0; -+} -+ -+static int iep_try_fmt_vid_out(struct file *file, void *priv, -+ struct v4l2_format *f) -+{ -+ if (f->fmt.pix.field != V4L2_FIELD_INTERLACED_TB && -+ f->fmt.pix.field != V4L2_FIELD_INTERLACED_BT && -+ f->fmt.pix.field != V4L2_FIELD_INTERLACED) -+ f->fmt.pix.field = V4L2_FIELD_INTERLACED; -+ -+ iep_prepare_format(&f->fmt.pix); -+ -+ return 0; -+} -+ -+static int iep_s_fmt_vid_out(struct file *file, void *priv, -+ struct v4l2_format *f) -+{ -+ struct iep_ctx *ctx = iep_file2ctx(file); -+ struct vb2_queue *vq; -+ -+ int ret; -+ -+ ret = iep_try_fmt_vid_out(file, priv, f); -+ if (ret) -+ return ret; -+ -+ vq = v4l2_m2m_get_vq(ctx->fh.m2m_ctx, f->type); -+ if (vb2_is_busy(vq)) -+ return -EBUSY; -+ -+ ctx->src_fmt.pix = f->fmt.pix; -+ ctx->src_fmt.hw_fmt = iep_fmt_find(&f->fmt.pix); -+ ctx->src_fmt.y_stride = IEP_Y_STRIDE(f->fmt.pix.width, f->fmt.pix.height); -+ ctx->src_fmt.uv_stride = IEP_UV_STRIDE(f->fmt.pix.width, f->fmt.pix.height, -+ ctx->src_fmt.hw_fmt->uv_factor); -+ -+ /* Propagate colorspace information to capture. */ -+ ctx->dst_fmt.pix.colorspace = f->fmt.pix.colorspace; -+ ctx->dst_fmt.pix.xfer_func = f->fmt.pix.xfer_func; -+ ctx->dst_fmt.pix.ycbcr_enc = f->fmt.pix.ycbcr_enc; -+ ctx->dst_fmt.pix.quantization = f->fmt.pix.quantization; -+ -+ /* scaling is not supported */ -+ ctx->dst_fmt.pix.width = f->fmt.pix.width; -+ ctx->dst_fmt.pix.height = f->fmt.pix.height; -+ ctx->dst_fmt.y_stride = IEP_Y_STRIDE(f->fmt.pix.width, f->fmt.pix.height); -+ ctx->dst_fmt.uv_stride = IEP_UV_STRIDE(f->fmt.pix.width, f->fmt.pix.height, -+ ctx->dst_fmt.hw_fmt->uv_factor); -+ -+ ctx->fmt_changed = true; -+ -+ return 0; -+} -+ -+static int iep_s_fmt_vid_cap(struct file *file, void *priv, -+ struct v4l2_format *f) -+{ -+ struct iep_ctx *ctx = iep_file2ctx(file); -+ struct vb2_queue *vq; -+ int ret; -+ -+ ret = iep_try_fmt_vid_cap(file, priv, f); -+ if (ret) -+ return ret; -+ -+ vq = v4l2_m2m_get_vq(ctx->fh.m2m_ctx, f->type); -+ if (vb2_is_busy(vq)) -+ return -EBUSY; -+ -+ /* scaling is not supported */ -+ f->fmt.pix.width = ctx->src_fmt.pix.width; -+ f->fmt.pix.height = ctx->src_fmt.pix.height; -+ -+ ctx->dst_fmt.pix = f->fmt.pix; -+ ctx->dst_fmt.hw_fmt = iep_fmt_find(&f->fmt.pix); -+ -+ ctx->dst_fmt.y_stride = IEP_Y_STRIDE(f->fmt.pix.width, f->fmt.pix.height); -+ ctx->dst_fmt.uv_stride = IEP_UV_STRIDE(f->fmt.pix.width, f->fmt.pix.height, -+ ctx->dst_fmt.hw_fmt->uv_factor); -+ -+ ctx->fmt_changed = true; -+ -+ return 0; -+} -+ -+static const struct v4l2_ioctl_ops iep_ioctl_ops = { -+ .vidioc_querycap = iep_querycap, -+ -+ .vidioc_enum_framesizes = iep_enum_framesizes, -+ -+ .vidioc_enum_fmt_vid_cap = iep_enum_fmt, -+ .vidioc_g_fmt_vid_cap = iep_g_fmt_vid_cap, -+ .vidioc_try_fmt_vid_cap = iep_try_fmt_vid_cap, -+ .vidioc_s_fmt_vid_cap = iep_s_fmt_vid_cap, -+ -+ .vidioc_enum_fmt_vid_out = iep_enum_fmt, -+ .vidioc_g_fmt_vid_out = iep_g_fmt_vid_out, -+ .vidioc_try_fmt_vid_out = iep_try_fmt_vid_out, -+ .vidioc_s_fmt_vid_out = iep_s_fmt_vid_out, -+ -+ .vidioc_reqbufs = v4l2_m2m_ioctl_reqbufs, -+ .vidioc_querybuf = v4l2_m2m_ioctl_querybuf, -+ .vidioc_qbuf = v4l2_m2m_ioctl_qbuf, -+ .vidioc_dqbuf = v4l2_m2m_ioctl_dqbuf, -+ .vidioc_prepare_buf = v4l2_m2m_ioctl_prepare_buf, -+ .vidioc_create_bufs = v4l2_m2m_ioctl_create_bufs, -+ .vidioc_expbuf = v4l2_m2m_ioctl_expbuf, -+ -+ .vidioc_streamon = v4l2_m2m_ioctl_streamon, -+ .vidioc_streamoff = v4l2_m2m_ioctl_streamoff, -+}; -+ -+static const struct video_device iep_video_device = { -+ .name = IEP_NAME, -+ .vfl_dir = VFL_DIR_M2M, -+ .fops = &iep_fops, -+ .ioctl_ops = &iep_ioctl_ops, -+ .minor = -1, -+ .release = video_device_release_empty, -+ .device_caps = V4L2_CAP_VIDEO_M2M | V4L2_CAP_STREAMING, -+}; -+ -+static int iep_parse_dt(struct rockchip_iep *iep) -+{ -+ int ret = 0; -+ -+ iep->axi_clk = devm_clk_get(iep->dev, "axi"); -+ if (IS_ERR(iep->axi_clk)) { -+ dev_err(iep->dev, "failed to get aclk clock\n"); -+ return PTR_ERR(iep->axi_clk); -+ } -+ -+ iep->ahb_clk = devm_clk_get(iep->dev, "ahb"); -+ if (IS_ERR(iep->ahb_clk)) { -+ dev_err(iep->dev, "failed to get hclk clock\n"); -+ return PTR_ERR(iep->ahb_clk); -+ } -+ -+ ret = clk_set_rate(iep->axi_clk, 300000000); -+ -+ if (ret) -+ dev_err(iep->dev, "failed to set axi clock rate to 300 MHz\n"); -+ -+ return ret; -+} -+ -+static irqreturn_t iep_isr(int irq, void *prv) -+{ -+ struct rockchip_iep *iep = prv; -+ struct iep_ctx *ctx; -+ u32 val; -+ enum vb2_buffer_state state = VB2_BUF_STATE_DONE; -+ -+ ctx = v4l2_m2m_get_curr_priv(iep->m2m_dev); -+ if (!ctx) { -+ v4l2_err(&iep->v4l2_dev, -+ "Instance released before the end of transaction\n"); -+ return IRQ_NONE; -+ } -+ -+ /* -+ * The irq is shared with the iommu. If the runtime-pm state of the -+ * iep-device is disabled or the interrupt status doesn't match the -+ * expeceted mask the irq has been targeted to the iommu. -+ */ -+ -+ if (!pm_runtime_active(iep->dev) || -+ !(iep_read(iep, IEP_INT) & IEP_INT_MASK)) -+ return IRQ_NONE; -+ -+ /* disable interrupt - will be re-enabled at next iep_device_run */ -+ iep_mod(ctx->iep, IEP_INT, -+ IEP_INT_FRAME_DONE_EN, 0); -+ -+ iep_mod(iep, IEP_INT, IEP_INT_FRAME_DONE_CLR, -+ IEP_INT_FRAME_DONE_CLR); -+ -+ /* wait for all status regs to show "idle" */ -+ val = readl_poll_timeout(iep->regs + IEP_STATUS, val, -+ (val == 0), 100, IEP_TIMEOUT); -+ -+ if (val) { -+ dev_err(iep->dev, -+ "Failed to wait for job to finish: status: %u\n", val); -+ state = VB2_BUF_STATE_ERROR; -+ ctx->job_abort = true; -+ } -+ -+ iep_m2m_dst_bufs_done(ctx, state); -+ -+ ctx->field_bff = (ctx->dst_buffs_done % 2 == 0) -+ ? ctx->field_order_bff : !ctx->field_order_bff; -+ -+ if (ctx->dst_buffs_done == 2 || ctx->job_abort) { -+ if (ctx->prev_src_buf) -+ v4l2_m2m_buf_done(ctx->prev_src_buf, state); -+ -+ /* current src buff will be next prev */ -+ ctx->prev_src_buf = v4l2_m2m_src_buf_remove(ctx->fh.m2m_ctx); -+ -+ v4l2_m2m_job_finish(ctx->iep->m2m_dev, ctx->fh.m2m_ctx); -+ ctx->dst_buffs_done = 0; -+ -+ } else { -+ iep_device_run(ctx); -+ } -+ -+ return IRQ_HANDLED; -+} -+ -+static int iep_probe(struct platform_device *pdev) -+{ -+ struct rockchip_iep *iep; -+ struct video_device *vfd; -+ struct resource *res; -+ int ret = 0; -+ int irq; -+ -+ if (!pdev->dev.of_node) -+ return -ENODEV; -+ -+ iep = devm_kzalloc(&pdev->dev, sizeof(*iep), GFP_KERNEL); -+ if (!iep) -+ return -ENOMEM; -+ -+ platform_set_drvdata(pdev, iep); -+ iep->dev = &pdev->dev; -+ iep->vfd = iep_video_device; -+ -+ ret = iep_parse_dt(iep); -+ if (ret) -+ dev_err(&pdev->dev, "Unable to parse OF data\n"); -+ -+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0); -+ -+ iep->regs = devm_ioremap_resource(iep->dev, res); -+ if (IS_ERR(iep->regs)) { -+ ret = PTR_ERR(iep->regs); -+ goto err_put_clk; -+ } -+ -+ ret = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32)); -+ if (ret) { -+ dev_err(&pdev->dev, "Could not set DMA coherent mask.\n"); -+ goto err_put_clk; -+ } -+ -+ vb2_dma_contig_set_max_seg_size(&pdev->dev, DMA_BIT_MASK(32)); -+ -+ irq = platform_get_irq(pdev, 0); -+ if (irq < 0) { -+ ret = irq; -+ goto err_put_clk; -+ } -+ -+ /* IRQ is shared with IOMMU */ -+ ret = devm_request_irq(iep->dev, irq, iep_isr, IRQF_SHARED, -+ dev_name(iep->dev), iep); -+ if (ret < 0) { -+ dev_err(iep->dev, "failed to request irq\n"); -+ goto err_put_clk; -+ } -+ -+ mutex_init(&iep->mutex); -+ -+ ret = v4l2_device_register(&pdev->dev, &iep->v4l2_dev); -+ if (ret) { -+ dev_err(iep->dev, "Failed to register V4L2 device\n"); -+ -+ return ret; -+ } -+ -+ vfd = &iep->vfd; -+ vfd->lock = &iep->mutex; -+ vfd->v4l2_dev = &iep->v4l2_dev; -+ -+ snprintf(vfd->name, sizeof(vfd->name), "%s", -+ iep_video_device.name); -+ -+ video_set_drvdata(vfd, iep); -+ -+ ret = video_register_device(vfd, VFL_TYPE_VIDEO, 0); -+ if (ret) { -+ v4l2_err(&iep->v4l2_dev, "Failed to register video device\n"); -+ -+ goto err_v4l2; -+ } -+ -+ v4l2_info(&iep->v4l2_dev, -+ "Device %s registered as /dev/video%d\n", vfd->name, vfd->num); -+ -+ iep->m2m_dev = v4l2_m2m_init(&iep_m2m_ops); -+ if (IS_ERR(iep->m2m_dev)) { -+ v4l2_err(&iep->v4l2_dev, -+ "Failed to initialize V4L2 M2M device\n"); -+ ret = PTR_ERR(iep->m2m_dev); -+ -+ goto err_video; -+ } -+ -+ pm_runtime_set_autosuspend_delay(iep->dev, 100); -+ pm_runtime_use_autosuspend(iep->dev); -+ pm_runtime_enable(iep->dev); -+ -+ return ret; -+ -+err_video: -+ video_unregister_device(&iep->vfd); -+err_v4l2: -+ v4l2_device_unregister(&iep->v4l2_dev); -+err_put_clk: -+ pm_runtime_dont_use_autosuspend(iep->dev); -+ pm_runtime_disable(iep->dev); -+ -+return ret; -+} -+ -+static void iep_remove(struct platform_device *pdev) -+{ -+ struct rockchip_iep *iep = platform_get_drvdata(pdev); -+ -+ pm_runtime_dont_use_autosuspend(iep->dev); -+ pm_runtime_disable(iep->dev); -+ -+ v4l2_m2m_release(iep->m2m_dev); -+ video_unregister_device(&iep->vfd); -+ v4l2_device_unregister(&iep->v4l2_dev); -+ -+ return; -+} -+ -+static int __maybe_unused iep_runtime_suspend(struct device *dev) -+{ -+ struct rockchip_iep *iep = dev_get_drvdata(dev); -+ -+ clk_disable_unprepare(iep->ahb_clk); -+ clk_disable_unprepare(iep->axi_clk); -+ -+ return 0; -+} -+ -+static int __maybe_unused iep_runtime_resume(struct device *dev) -+{ -+ struct rockchip_iep *iep; -+ int ret = 0; -+ -+ iep = dev_get_drvdata(dev); -+ -+ ret = clk_prepare_enable(iep->axi_clk); -+ if (ret) { -+ dev_err(iep->dev, "Cannot enable axi clock: %d\n", ret); -+ return ret; -+ } -+ -+ ret = clk_prepare_enable(iep->ahb_clk); -+ if (ret) { -+ dev_err(iep->dev, "Cannot enable ahb clock: %d\n", ret); -+ goto err_disable_axi_clk; -+ } -+ -+ return ret; -+ -+err_disable_axi_clk: -+ clk_disable_unprepare(iep->axi_clk); -+ return ret; -+} -+ -+static const struct dev_pm_ops iep_pm_ops = { -+ SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, -+ pm_runtime_force_resume) -+ SET_RUNTIME_PM_OPS(iep_runtime_suspend, -+ iep_runtime_resume, NULL) -+}; -+ -+static const struct of_device_id rockchip_iep_match[] = { -+ { -+ .compatible = "rockchip,rk3228-iep", -+ }, -+ {}, -+}; -+ -+MODULE_DEVICE_TABLE(of, rockchip_iep_match); -+ -+static struct platform_driver iep_pdrv = { -+ .probe = iep_probe, -+ .remove = iep_remove, -+ .driver = { -+ .name = IEP_NAME, -+ .pm = &iep_pm_ops, -+ .of_match_table = rockchip_iep_match, -+ }, -+}; -+ -+module_platform_driver(iep_pdrv); -+ -+MODULE_AUTHOR("Alex Bee "); -+MODULE_DESCRIPTION("Rockchip Image Enhancement Processor"); -+MODULE_LICENSE("GPL v2"); -diff --git a/drivers/media/platform/rockchip/iep/iep.h b/drivers/media/platform/rockchip/iep/iep.h -new file mode 100644 -index 000000000000..7d9fc61624b6 ---- /dev/null -+++ b/drivers/media/platform/rockchip/iep/iep.h -@@ -0,0 +1,112 @@ -+/* SPDX-License-Identifier: GPL-2.0-only */ -+/* -+ * Rockchip Image Enhancement Processor (IEP) driver -+ * -+ * Copyright (C) 2020 Alex Bee -+ * -+ */ -+#ifndef __IEP_H__ -+#define __IEP_H__ -+ -+#include -+#include -+#include -+#include -+ -+#define IEP_NAME "rockchip-iep" -+ -+/* Hardware limits */ -+#define IEP_MIN_WIDTH 320U -+#define IEP_MAX_WIDTH 1920U -+ -+#define IEP_MIN_HEIGHT 240U -+#define IEP_MAX_HEIGHT 1088U -+ -+/* Hardware defaults */ -+#define IEP_DEFAULT_WIDTH 320U -+#define IEP_DEFAULT_HEIGHT 240U -+ -+//ns -+#define IEP_TIMEOUT 250000 -+ -+struct iep_fmt { -+ u32 fourcc; -+ u8 depth; -+ u8 uv_factor; -+ u8 color_swap; -+ u8 hw_format; -+}; -+ -+struct iep_frm_fmt { -+ struct iep_fmt *hw_fmt; -+ struct v4l2_pix_format pix; -+ -+ unsigned int y_stride; -+ unsigned int uv_stride; -+}; -+ -+struct iep_ctx { -+ struct v4l2_fh fh; -+ struct rockchip_iep *iep; -+ -+ struct iep_frm_fmt src_fmt; -+ struct iep_frm_fmt dst_fmt; -+ -+ struct vb2_v4l2_buffer *prev_src_buf; -+ struct vb2_v4l2_buffer *dst0_buf; -+ struct vb2_v4l2_buffer *dst1_buf; -+ -+ u32 dst_sequence; -+ u32 src_sequence; -+ -+ /* bff = bottom field first */ -+ bool field_order_bff; -+ bool field_bff; -+ -+ unsigned int dst_buffs_done; -+ -+ bool fmt_changed; -+ bool job_abort; -+}; -+ -+struct rockchip_iep { -+ struct v4l2_device v4l2_dev; -+ struct v4l2_m2m_dev *m2m_dev; -+ struct video_device vfd; -+ -+ struct device *dev; -+ -+ void __iomem *regs; -+ -+ struct clk *axi_clk; -+ struct clk *ahb_clk; -+ -+ /* vfd lock */ -+ struct mutex mutex; -+}; -+ -+static inline void iep_write(struct rockchip_iep *iep, u32 reg, u32 value) -+{ -+ writel(value, iep->regs + reg); -+}; -+ -+static inline u32 iep_read(struct rockchip_iep *iep, u32 reg) -+{ -+ return readl(iep->regs + reg); -+}; -+ -+static inline void iep_shadow_mod(struct rockchip_iep *iep, u32 reg, -+ u32 shadow_reg, u32 mask, u32 val) -+{ -+ u32 temp = iep_read(iep, shadow_reg) & ~(mask); -+ -+ temp |= val & mask; -+ iep_write(iep, reg, temp); -+}; -+ -+static inline void iep_mod(struct rockchip_iep *iep, u32 reg, u32 mask, u32 val) -+{ -+ iep_shadow_mod(iep, reg, reg, mask, val); -+}; -+ -+#endif - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Alex Bee -Date: Wed, 14 Oct 2020 20:22:38 +0200 -Subject: [PATCH] ARM64: dts: rockchip: Add IEP node for RK3328 - -while at that also add the mmu required - -Signed-off-by: Alex Bee ---- - arch/arm64/boot/dts/rockchip/rk3328.dtsi | 22 ++++++++++++++++++++++ - 1 file changed, 22 insertions(+) - -diff --git a/arch/arm64/boot/dts/rockchip/rk3328.dtsi b/arch/arm64/boot/dts/rockchip/rk3328.dtsi -index eec03adf0902..5455a46c9a6b 100644 ---- a/arch/arm64/boot/dts/rockchip/rk3328.dtsi -+++ b/arch/arm64/boot/dts/rockchip/rk3328.dtsi -@@ -760,6 +760,28 @@ vop_mmu: iommu@ff373f00 { - status = "disabled"; - }; - -+ iep: iep@ff3a0000 { -+ compatible = "rockchip,rk3328-iep", "rockchip,rk3228-iep"; -+ reg = <0x0 0xff3a0000 0x0 0x800>; -+ interrupts = ; -+ interrupt-names = "iep"; -+ clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>; -+ clock-names = "axi", "ahb"; -+ power-domains = <&power RK3328_PD_VIDEO>; -+ iommus = <&iep_mmu>; -+ }; -+ -+ iep_mmu: iommu@ff3a0800 { -+ compatible = "rockchip,iommu"; -+ reg = <0x0 0xff3a0800 0x0 0x40>; -+ interrupts = ; -+ interrupt-names = "iep_mmu"; -+ clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>; -+ clock-names = "aclk", "iface"; -+ power-domains = <&power RK3328_PD_VIDEO>; -+ #iommu-cells = <0>; -+ }; -+ - hdmi: hdmi@ff3c0000 { - compatible = "rockchip,rk3328-dw-hdmi"; - reg = <0x0 0xff3c0000 0x0 0x20000>; - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Alex Bee -Date: Wed, 14 Oct 2020 20:43:12 +0200 -Subject: [PATCH] ARM64: dts: rockchip: Add IEP node for RK3399 - -Signed-off-by: Alex Bee ---- - arch/arm64/boot/dts/rockchip/rk3399.dtsi | 13 ++++++++++++- - 1 file changed, 12 insertions(+), 1 deletion(-) - -diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi -index dbe6a9cb98a5..f0629b7a81c6 100644 ---- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi -+++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi -@@ -1365,14 +1365,25 @@ vdec_mmu: iommu@ff660480 { - #iommu-cells = <0>; - }; - -+ iep: iep@ff670000 { -+ compatible = "rockchip,rk3399-iep", "rockchip,rk3228-iep"; -+ reg = <0x0 0xff670000 0x0 0x800>; -+ interrupts = ; -+ interrupt-names = "iep"; -+ clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>; -+ clock-names = "axi", "ahb"; -+ power-domains = <&power RK3399_PD_IEP>; -+ iommus = <&iep_mmu>; -+ }; -+ - iep_mmu: iommu@ff670800 { - compatible = "rockchip,iommu"; - reg = <0x0 0xff670800 0x0 0x40>; - interrupts = ; - clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>; - clock-names = "aclk", "iface"; -+ power-domains = <&power RK3399_PD_IEP>; - #iommu-cells = <0>; -- status = "disabled"; - }; - - rga: rga@ff680000 { - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Alex Bee -Date: Wed, 14 Oct 2020 20:53:56 +0200 -Subject: [PATCH] ARM: dts: rockchip: Add IEP node for RK3288 - -Signed-off-by: Alex Bee ---- - arch/arm/boot/dts/rockchip/rk3288.dtsi | 13 ++++++++++++- - 1 file changed, 12 insertions(+), 1 deletion(-) - -diff --git a/arch/arm/boot/dts/rockchip/rk3288.dtsi b/arch/arm/boot/dts/rockchip/rk3288.dtsi -index 59fba3ac6aae..06545f423de2 100644 ---- a/arch/arm/boot/dts/rockchip/rk3288.dtsi -+++ b/arch/arm/boot/dts/rockchip/rk3288.dtsi -@@ -984,14 +984,25 @@ crypto: crypto@ff8a0000 { - reset-names = "crypto-rst"; - }; - -+ iep: iep@ff90000 { -+ compatible = "rockchip,rk3288-iep", "rockchip,rk3228-iep"; -+ reg = <0x0 0xff900000 0x0 0x800>; -+ interrupts = ; -+ interrupt-names = "iep"; -+ clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>; -+ clock-names = "axi", "ahb"; -+ power-domains = <&power RK3288_PD_VIO>; -+ iommus = <&iep_mmu>; -+ }; -+ - iep_mmu: iommu@ff900800 { - compatible = "rockchip,iommu"; - reg = <0x0 0xff900800 0x0 0x40>; - interrupts = ; - clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>; - clock-names = "aclk", "iface"; -+ power-domains = <&power RK3288_PD_VIO>; - #iommu-cells = <0>; -- status = "disabled"; - }; - - isp_mmu: iommu@ff914000 { From 4ede989f2c3bc141f1c43749592cb46d9db2faaa Mon Sep 17 00:00:00 2001 From: Paolo Sabatino Date: Sun, 1 Dec 2024 21:54:10 +0100 Subject: [PATCH 012/120] rockchip: fix asound.conf for rk322x-box and xt-q8l-v10 boards sound node in device trees have been migrated to audio-graph-card2 to overcome limitations and configuration mayhems in ALSA userland libraries --- packages/bsp/rockchip/asound.conf | 56 ++++----- .../archive/rockchip-6.12/dt/rk322x-box.dts | 115 +++++++++++------- .../rockchip-6.12/dt/rk3288-xt-q8l-v10.dts | 75 ++++++------ .../general-rockchip-various-fixes.patch | 23 ---- .../archive/rockchip-6.6/dt/rk322x-box.dts | 115 +++++++++++------- .../rockchip-6.6/dt/rk3288-xt-q8l-v10.dts | 75 ++++++------ .../general-rockchip-various-fixes.patch | 2 +- 7 files changed, 238 insertions(+), 223 deletions(-) diff --git a/packages/bsp/rockchip/asound.conf b/packages/bsp/rockchip/asound.conf index 6559665239de..4aec50abab31 100644 --- a/packages/bsp/rockchip/asound.conf +++ b/packages/bsp/rockchip/asound.conf @@ -1,27 +1,3 @@ -pcm.OnBoard_D0 { - - type hw - card OnBoard - device 0 - -} - -pcm.OnBoard_D1 { - - type hw - card OnBoard - device 1 - -} - -pcm.OnBoard_D2 { - - type hw - card OnBoard - device 2 - -} - # Configuration to expose the SPDIF device of RK3288 to ALSA. # The device tree must describe a simple-audio-card device named "SPDIF" # for this to work properly @@ -53,24 +29,18 @@ cards.SPDIF.pcm.iec958.0 { } # Configuration to expose the HDMI device of RK3288 to ALSA. -# The device tree must describe a simple-audio-card device named "DW-I2S-HDMI" +# The device tree must describe a simple-audio-card device named "HDMI" # for this to work properly # This percolates to PulseAudio, which will eventually show the proper # labels to the audio device -cards.DW-I2S-HDMI.pcm.hdmi.0 { - @args [ CARD DEVICE CTLINDEX AES0 AES1 AES2 AES3 ] +cards.HDMI.pcm.hdmi.0 { + @args [ CARD AES0 AES1 AES2 AES3 ] @args.CARD { type string } - @args.DEVICE { - type integer - } - @args.CTLINDEX { - type integer - } @args.AES0 { type integer } @@ -83,6 +53,22 @@ cards.DW-I2S-HDMI.pcm.hdmi.0 { @args.AES3 { type integer } - type hw - card $CARD + type hooks + slave.pcm { + type hw + card $CARD + } + hooks.0 { + type ctl_elems + hook_args [ + { + interface PCM + name "IEC958 Playback Default" + lock true + preserve true + value [ $AES0 $AES1 $AES2 $AES3 ] + } + ] + } } + diff --git a/patch/kernel/archive/rockchip-6.12/dt/rk322x-box.dts b/patch/kernel/archive/rockchip-6.12/dt/rk322x-box.dts index ddc25ec77f7f..1382c432b60c 100644 --- a/patch/kernel/archive/rockchip-6.12/dt/rk322x-box.dts +++ b/patch/kernel/archive/rockchip-6.12/dt/rk322x-box.dts @@ -24,7 +24,7 @@ /delete-node/ opp-table-0; /* - * Rebuild the thermal zones and cooling maps ourselved + * Rebuild the thermal zones and cooling maps ourselves */ /delete-node/ thermal-zones; @@ -37,20 +37,6 @@ mmc2 = &emmc; }; - analog-sound { - compatible = "simple-audio-card"; - simple-audio-card,format = "i2s"; - simple-audio-card,mclk-fs = <256>; - simple-audio-card,name = "analog"; - simple-audio-card,cpu { - sound-dai = <&i2s1>; - }; - - simple-audio-card,codec { - sound-dai = <&codec>; - }; - }; - chosen { bootargs = "earlyprintk=uart8250,mmio32,0x11030000"; }; @@ -142,25 +128,6 @@ reset-gpios = <&gpio2 RK_PD2 GPIO_ACTIVE_LOW>; }; - - spdif_out: spdif-out { - status = "okay"; - compatible = "linux,spdif-dit"; - #sound-dai-cells = <0>; - }; - - spdif-sound { - status = "okay"; - compatible = "simple-audio-card"; - simple-audio-card,name = "SPDIF"; - simple-audio-card,cpu { - sound-dai = <&spdif>; - }; - simple-audio-card,codec { - sound-dai = <&spdif_out>; - }; - }; - vcc_sys: vcc-sys-regulator { compatible = "regulator-fixed"; regulator-name = "vcc_sys"; @@ -318,11 +285,35 @@ }; }; -}; + hdmi-sound { + compatible = "audio-graph-card2"; + label = "HDMI"; + links = <&i2s0_port>; + }; + + analog-sound { + compatible = "audio-graph-card2"; + label = "analog"; + links = <&i2s1_port>; + }; + + spdif-sound { + compatible = "audio-graph-card2"; + label = "SPDIF"; + links = <&spdif_port>; + }; + + spdif_out: spdif-out { + status = "okay"; + compatible = "linux,spdif-dit"; + #sound-dai-cells = <0>; + spdif_out_port: port { + spdif_out_ep: endpoint { + remote-endpoint = <&spdif_ep>; + }; + }; + }; -&codec { - #sound-dai-cells = <0>; - status = "okay"; }; &cpu0 { @@ -460,23 +451,63 @@ &hdmi { status = "okay"; + hdmi_port: port { + hdmi_ep: endpoint { + remote-endpoint = <&i2s0_ep>; + }; + }; }; -&hdmi_sound { +&hdmi_phy { status = "okay"; }; -&hdmi_phy { +&codec { + #sound-dai-cells = <0>; + status = "okay"; + codec_port: port { + codec_ep: endpoint { + remote-endpoint = <&i2s1_ep>; + }; + }; +}; + +&spdif { status = "okay"; + spdif_port: port { + spdif_ep: endpoint { + remote-endpoint = <&spdif_out_ep>; + }; + }; }; &i2s0 { status = "okay"; + i2s0_port: port { + i2s0_ep: endpoint { + system-clock-direction-out; + frame-master; + bitclock-master; + mclk-fs = <256>; + dai-format = "i2s"; + remote-endpoint = <&hdmi_ep>; + }; + }; }; &i2s1 { #sound-dai-cells = <0>; status = "okay"; + i2s1_port: port { + i2s1_ep: endpoint { + system-clock-direction-out; + frame-master; + bitclock-master; + mclk-fs = <256>; + dai-format = "i2s"; + remote-endpoint = <&codec_ep>; + }; + }; }; /** Integration to pin controller */ @@ -742,10 +773,6 @@ status = "okay"; }; -&spdif { - status = "okay"; -}; - &tsadc { rockchip,grf = <&grf>; rockchip,hw-tshut-mode = <0>; diff --git a/patch/kernel/archive/rockchip-6.12/dt/rk3288-xt-q8l-v10.dts b/patch/kernel/archive/rockchip-6.12/dt/rk3288-xt-q8l-v10.dts index b715818fe691..a26e0c4c7535 100644 --- a/patch/kernel/archive/rockchip-6.12/dt/rk3288-xt-q8l-v10.dts +++ b/patch/kernel/archive/rockchip-6.12/dt/rk3288-xt-q8l-v10.dts @@ -202,7 +202,7 @@ * Required power sequence to properly enable the wireless/bluetooth * module connected to sdio0 */ - sdio0_pwrseq: sdio0_pwrseq { + sdio0_pwrseq: sdio0-pwrseq { compatible = "mmc-pwrseq-simple"; pinctrl-names = "default"; pinctrl-0 = <&wifi_enable_h>; @@ -220,43 +220,26 @@ }; */ - /* - * Sound taken from tinkerboard device tree, adapted to q8. - */ - soundcard-hdmi { - compatible = "simple-audio-card"; - simple-audio-card,format = "i2s"; - simple-audio-card,name = "DW-I2S-HDMI"; - simple-audio-card,mclk-fs = <512>; - - simple-audio-card,codec { - sound-dai = <&hdmi>; - }; - - simple-audio-card,cpu { - sound-dai = <&i2s>; - }; + hdmi-sound { + compatible = "audio-graph-card2"; + label = "HDMI"; + links = <&i2s_port>; }; - soundcard-spdif { - compatible = "simple-audio-card"; - simple-audio-card,name = "SPDIF"; - simple-audio-card,dai-link@1 { - - cpu { - sound-dai = <&spdif>; - }; - - codec { - sound-dai = <&spdif_out>; - }; - - }; + spdif-sound { + compatible = "audio-graph-card2"; + label = "SPDIF"; + links = <&spdif_port>; }; spdif_out: spdif-out { compatible = "linux,spdif-dit"; #sound-dai-cells = <0>; + spdif_out_port: port { + spdif_out_ep: endpoint { + remote-endpoint = <&spdif_ep>; + }; + }; }; }; @@ -300,6 +283,11 @@ &hdmi { ddc-i2c-bus = <&i2c5>; status = "ok"; + hdmi_port: port { + hdmi_ep: endpoint { + remote-endpoint = <&i2s_ep>; + }; + }; }; &gpu { @@ -758,7 +746,7 @@ sdio0 { wifi_enable_h: wifienable-h { - rockchip,pins = <4 28 RK_FUNC_GPIO &pcfg_output_high>; + rockchip,pins = <4 28 RK_FUNC_GPIO &pcfg_pull_down>; }; }; @@ -868,9 +856,6 @@ vqmmc-supply = <&vcc_18>; // This must be the same as in io_domains, // otherwise the mmc1 device won't be detected properly - // clock-frequency = <50000000>; - // max-frequency = <50000000>; - pinctrl-names = "default"; pinctrl-0 = <&sdio0_bus4>, <&sdio0_cmd>, <&sdio0_clk>, <&sdio0_int>; @@ -884,6 +869,8 @@ keep-power-in-suspend; disable-wp; + //sd-uhs-sdr50; // required to be enabled, otherwise the device gets + // detected, but there is no communication status = "okay"; @@ -896,9 +883,6 @@ status = "okay"; }; - //sd-uhs-sdr104; // required to be disabled, otherwise the device get - // detected, but there is no communication - }; &spi0 { @@ -1053,11 +1037,26 @@ &i2s { #sound-dai-cells = <0>; status = "okay"; + i2s_port: port { + i2s_ep: endpoint { + system-clock-direction-out; + frame-master; + bitclock-master; + mclk-fs = <512>; + dai-format = "i2s"; + remote-endpoint = <&hdmi_ep>; + }; + }; }; // spdif is present on q8 device, enable it &spdif { status = "okay"; + spdif_port: port { + spdif_ep: endpoint { + remote-endpoint = <&spdif_out_ep>; + }; + }; }; /* diff --git a/patch/kernel/archive/rockchip-6.12/patches.armbian/general-rockchip-various-fixes.patch b/patch/kernel/archive/rockchip-6.12/patches.armbian/general-rockchip-various-fixes.patch index 1a0d56418bcd..00d644bde46b 100644 --- a/patch/kernel/archive/rockchip-6.12/patches.armbian/general-rockchip-various-fixes.patch +++ b/patch/kernel/archive/rockchip-6.12/patches.armbian/general-rockchip-various-fixes.patch @@ -26,29 +26,6 @@ index 831561fc1814..24e963b01d87 100644 serial0 = &uart0; serial1 = &uart1; serial2 = &uart2; -@@ -105,6 +106,22 @@ arm-pmu { - interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; - }; - -+ hdmi_sound: hdmi-sound { -+ compatible = "simple-audio-card"; -+ simple-audio-card,name = "hdmi-sound"; -+ simple-audio-card,format = "i2s"; -+ simple-audio-card,mclk-fs = <256>; -+ status = "disabled"; -+ -+ simple-audio-card,cpu { -+ sound-dai = <&i2s0>; -+ }; -+ -+ simple-audio-card,codec { -+ sound-dai = <&hdmi>; -+ }; -+ }; -+ - psci { - compatible = "arm,psci-1.0", "arm,psci-0.2"; - method = "smc"; @@ -132,6 +149,17 @@ display_subsystem: display-subsystem { ports = <&vop_out>; }; diff --git a/patch/kernel/archive/rockchip-6.6/dt/rk322x-box.dts b/patch/kernel/archive/rockchip-6.6/dt/rk322x-box.dts index ddc25ec77f7f..1382c432b60c 100644 --- a/patch/kernel/archive/rockchip-6.6/dt/rk322x-box.dts +++ b/patch/kernel/archive/rockchip-6.6/dt/rk322x-box.dts @@ -24,7 +24,7 @@ /delete-node/ opp-table-0; /* - * Rebuild the thermal zones and cooling maps ourselved + * Rebuild the thermal zones and cooling maps ourselves */ /delete-node/ thermal-zones; @@ -37,20 +37,6 @@ mmc2 = &emmc; }; - analog-sound { - compatible = "simple-audio-card"; - simple-audio-card,format = "i2s"; - simple-audio-card,mclk-fs = <256>; - simple-audio-card,name = "analog"; - simple-audio-card,cpu { - sound-dai = <&i2s1>; - }; - - simple-audio-card,codec { - sound-dai = <&codec>; - }; - }; - chosen { bootargs = "earlyprintk=uart8250,mmio32,0x11030000"; }; @@ -142,25 +128,6 @@ reset-gpios = <&gpio2 RK_PD2 GPIO_ACTIVE_LOW>; }; - - spdif_out: spdif-out { - status = "okay"; - compatible = "linux,spdif-dit"; - #sound-dai-cells = <0>; - }; - - spdif-sound { - status = "okay"; - compatible = "simple-audio-card"; - simple-audio-card,name = "SPDIF"; - simple-audio-card,cpu { - sound-dai = <&spdif>; - }; - simple-audio-card,codec { - sound-dai = <&spdif_out>; - }; - }; - vcc_sys: vcc-sys-regulator { compatible = "regulator-fixed"; regulator-name = "vcc_sys"; @@ -318,11 +285,35 @@ }; }; -}; + hdmi-sound { + compatible = "audio-graph-card2"; + label = "HDMI"; + links = <&i2s0_port>; + }; + + analog-sound { + compatible = "audio-graph-card2"; + label = "analog"; + links = <&i2s1_port>; + }; + + spdif-sound { + compatible = "audio-graph-card2"; + label = "SPDIF"; + links = <&spdif_port>; + }; + + spdif_out: spdif-out { + status = "okay"; + compatible = "linux,spdif-dit"; + #sound-dai-cells = <0>; + spdif_out_port: port { + spdif_out_ep: endpoint { + remote-endpoint = <&spdif_ep>; + }; + }; + }; -&codec { - #sound-dai-cells = <0>; - status = "okay"; }; &cpu0 { @@ -460,23 +451,63 @@ &hdmi { status = "okay"; + hdmi_port: port { + hdmi_ep: endpoint { + remote-endpoint = <&i2s0_ep>; + }; + }; }; -&hdmi_sound { +&hdmi_phy { status = "okay"; }; -&hdmi_phy { +&codec { + #sound-dai-cells = <0>; + status = "okay"; + codec_port: port { + codec_ep: endpoint { + remote-endpoint = <&i2s1_ep>; + }; + }; +}; + +&spdif { status = "okay"; + spdif_port: port { + spdif_ep: endpoint { + remote-endpoint = <&spdif_out_ep>; + }; + }; }; &i2s0 { status = "okay"; + i2s0_port: port { + i2s0_ep: endpoint { + system-clock-direction-out; + frame-master; + bitclock-master; + mclk-fs = <256>; + dai-format = "i2s"; + remote-endpoint = <&hdmi_ep>; + }; + }; }; &i2s1 { #sound-dai-cells = <0>; status = "okay"; + i2s1_port: port { + i2s1_ep: endpoint { + system-clock-direction-out; + frame-master; + bitclock-master; + mclk-fs = <256>; + dai-format = "i2s"; + remote-endpoint = <&codec_ep>; + }; + }; }; /** Integration to pin controller */ @@ -742,10 +773,6 @@ status = "okay"; }; -&spdif { - status = "okay"; -}; - &tsadc { rockchip,grf = <&grf>; rockchip,hw-tshut-mode = <0>; diff --git a/patch/kernel/archive/rockchip-6.6/dt/rk3288-xt-q8l-v10.dts b/patch/kernel/archive/rockchip-6.6/dt/rk3288-xt-q8l-v10.dts index b715818fe691..a26e0c4c7535 100644 --- a/patch/kernel/archive/rockchip-6.6/dt/rk3288-xt-q8l-v10.dts +++ b/patch/kernel/archive/rockchip-6.6/dt/rk3288-xt-q8l-v10.dts @@ -202,7 +202,7 @@ * Required power sequence to properly enable the wireless/bluetooth * module connected to sdio0 */ - sdio0_pwrseq: sdio0_pwrseq { + sdio0_pwrseq: sdio0-pwrseq { compatible = "mmc-pwrseq-simple"; pinctrl-names = "default"; pinctrl-0 = <&wifi_enable_h>; @@ -220,43 +220,26 @@ }; */ - /* - * Sound taken from tinkerboard device tree, adapted to q8. - */ - soundcard-hdmi { - compatible = "simple-audio-card"; - simple-audio-card,format = "i2s"; - simple-audio-card,name = "DW-I2S-HDMI"; - simple-audio-card,mclk-fs = <512>; - - simple-audio-card,codec { - sound-dai = <&hdmi>; - }; - - simple-audio-card,cpu { - sound-dai = <&i2s>; - }; + hdmi-sound { + compatible = "audio-graph-card2"; + label = "HDMI"; + links = <&i2s_port>; }; - soundcard-spdif { - compatible = "simple-audio-card"; - simple-audio-card,name = "SPDIF"; - simple-audio-card,dai-link@1 { - - cpu { - sound-dai = <&spdif>; - }; - - codec { - sound-dai = <&spdif_out>; - }; - - }; + spdif-sound { + compatible = "audio-graph-card2"; + label = "SPDIF"; + links = <&spdif_port>; }; spdif_out: spdif-out { compatible = "linux,spdif-dit"; #sound-dai-cells = <0>; + spdif_out_port: port { + spdif_out_ep: endpoint { + remote-endpoint = <&spdif_ep>; + }; + }; }; }; @@ -300,6 +283,11 @@ &hdmi { ddc-i2c-bus = <&i2c5>; status = "ok"; + hdmi_port: port { + hdmi_ep: endpoint { + remote-endpoint = <&i2s_ep>; + }; + }; }; &gpu { @@ -758,7 +746,7 @@ sdio0 { wifi_enable_h: wifienable-h { - rockchip,pins = <4 28 RK_FUNC_GPIO &pcfg_output_high>; + rockchip,pins = <4 28 RK_FUNC_GPIO &pcfg_pull_down>; }; }; @@ -868,9 +856,6 @@ vqmmc-supply = <&vcc_18>; // This must be the same as in io_domains, // otherwise the mmc1 device won't be detected properly - // clock-frequency = <50000000>; - // max-frequency = <50000000>; - pinctrl-names = "default"; pinctrl-0 = <&sdio0_bus4>, <&sdio0_cmd>, <&sdio0_clk>, <&sdio0_int>; @@ -884,6 +869,8 @@ keep-power-in-suspend; disable-wp; + //sd-uhs-sdr50; // required to be enabled, otherwise the device gets + // detected, but there is no communication status = "okay"; @@ -896,9 +883,6 @@ status = "okay"; }; - //sd-uhs-sdr104; // required to be disabled, otherwise the device get - // detected, but there is no communication - }; &spi0 { @@ -1053,11 +1037,26 @@ &i2s { #sound-dai-cells = <0>; status = "okay"; + i2s_port: port { + i2s_ep: endpoint { + system-clock-direction-out; + frame-master; + bitclock-master; + mclk-fs = <512>; + dai-format = "i2s"; + remote-endpoint = <&hdmi_ep>; + }; + }; }; // spdif is present on q8 device, enable it &spdif { status = "okay"; + spdif_port: port { + spdif_ep: endpoint { + remote-endpoint = <&spdif_out_ep>; + }; + }; }; /* diff --git a/patch/kernel/archive/rockchip-6.6/patches.armbian/general-rockchip-various-fixes.patch b/patch/kernel/archive/rockchip-6.6/patches.armbian/general-rockchip-various-fixes.patch index 7b442be36046..64da12bfef9b 100644 --- a/patch/kernel/archive/rockchip-6.6/patches.armbian/general-rockchip-various-fixes.patch +++ b/patch/kernel/archive/rockchip-6.6/patches.armbian/general-rockchip-various-fixes.patch @@ -32,7 +32,7 @@ index 75af99c76..c50b2ccd7 100644 + hdmi_sound: hdmi-sound { + compatible = "simple-audio-card"; -+ simple-audio-card,name = "hdmi-sound"; ++ simple-audio-card,name = "HDMI"; + simple-audio-card,format = "i2s"; + simple-audio-card,mclk-fs = <256>; + status = "disabled"; From 3839eaa71355abbdeb439557422d9958c51b47d9 Mon Sep 17 00:00:00 2001 From: Paolo Sabatino Date: Wed, 4 Dec 2024 15:01:34 +0100 Subject: [PATCH 013/120] rockchip: fix rk3288 usb otg host functionality this commit reverts commit ca2dc35e555e7043de585f4e46123d8fbd2b5a21 from mainline kernel because rk3288 requires clock gating to assert irq on usb device plug in and thus proceed with reset-on-wake quirk --- .../archive/rockchip-6.12/armbian.series | 1 + ...-dwc2-fix-rk3288-reset-on-wake-quirk.patch | 24 +++++++++++++++++++ .../kernel/archive/rockchip-6.12/series.conf | 1 + 3 files changed, 26 insertions(+) create mode 100644 patch/kernel/archive/rockchip-6.12/patches.armbian/general-dwc2-fix-rk3288-reset-on-wake-quirk.patch diff --git a/patch/kernel/archive/rockchip-6.12/armbian.series b/patch/kernel/archive/rockchip-6.12/armbian.series index afd8f3b90306..847a170939ac 100644 --- a/patch/kernel/archive/rockchip-6.12/armbian.series +++ b/patch/kernel/archive/rockchip-6.12/armbian.series @@ -29,6 +29,7 @@ patches.armbian/general-add-overlay-compilation-support.patch patches.armbian/general-add-overlay-configfs.patch patches.armbian/general-add-restart-handler-for-act8846.patch + patches.armbian/general-dwc2-fix-rk3288-reset-on-wake-quirk.patch patches.armbian/general-dwc2-fix-wait-peripheral.patch patches.armbian/general-dwc2-fix-wait-time.patch patches.armbian/general-dwc2-nak-gadget.patch diff --git a/patch/kernel/archive/rockchip-6.12/patches.armbian/general-dwc2-fix-rk3288-reset-on-wake-quirk.patch b/patch/kernel/archive/rockchip-6.12/patches.armbian/general-dwc2-fix-rk3288-reset-on-wake-quirk.patch new file mode 100644 index 000000000000..bc3a6f29630b --- /dev/null +++ b/patch/kernel/archive/rockchip-6.12/patches.armbian/general-dwc2-fix-rk3288-reset-on-wake-quirk.patch @@ -0,0 +1,24 @@ +From c046bcccf1ca331cff3b89f09eed080a5407aa5a Mon Sep 17 00:00:00 2001 +From: Paolo Sabatino +Date: Wed, 4 Dec 2024 14:32:40 +0100 +Subject: [PATCH] rockchip: fix rk3288 reset-on-wake quirk + +--- + drivers/usb/dwc2/params.c | 1 - + 1 file changed, 1 deletion(-) + +diff --git a/drivers/usb/dwc2/params.c b/drivers/usb/dwc2/params.c +index 4d73fae80b12..0109055a9a8e 100644 +--- a/drivers/usb/dwc2/params.c ++++ b/drivers/usb/dwc2/params.c +@@ -130,7 +130,6 @@ static void dwc2_set_rk_params(struct dwc2_hsotg *hsotg) + p->lpm_clock_gating = false; + p->besl = false; + p->hird_threshold_en = false; +- p->no_clock_gating = true; + } + + static void dwc2_set_ltq_danube_params(struct dwc2_hsotg *hsotg) +-- +2.43.0 + diff --git a/patch/kernel/archive/rockchip-6.12/series.conf b/patch/kernel/archive/rockchip-6.12/series.conf index 43cf51f05019..9d32a6f1fe3c 100644 --- a/patch/kernel/archive/rockchip-6.12/series.conf +++ b/patch/kernel/archive/rockchip-6.12/series.conf @@ -37,6 +37,7 @@ patches.armbian/general-add-overlay-compilation-support.patch patches.armbian/general-add-overlay-configfs.patch patches.armbian/general-add-restart-handler-for-act8846.patch + patches.armbian/general-dwc2-fix-rk3288-reset-on-wake-quirk.patch patches.armbian/general-dwc2-fix-wait-peripheral.patch patches.armbian/general-dwc2-fix-wait-time.patch patches.armbian/general-dwc2-nak-gadget.patch From 9614a2014c9384e0a3190171f5ca40eff6eacb9a Mon Sep 17 00:00:00 2001 From: Chen Jiali Date: Thu, 28 Nov 2024 15:15:51 +0800 Subject: [PATCH 014/120] fix: add some patch to repair eMMC startup issues --- ...C-frequency-to-improve-compatibility.patch | 18 +++++++ ...mmc-core-phase-in-the-tuning-process.patch | 52 +++++++++++++++++++ ...mmc-meson-gx-limit-to-24MHz.patch.disable} | 0 ...config-reset-board-if-failed-to-boot.patch | 22 ++++++++ 4 files changed, 92 insertions(+) create mode 100644 patch/kernel/archive/meson64-6.6/0018-Reduce-eMMC-frequency-to-improve-compatibility.patch create mode 100644 patch/u-boot/v2023.07.02/board_radxa-zero/001-HACK-fix-meson-mmc-core-phase-in-the-tuning-process.patch rename patch/u-boot/v2023.07.02/board_radxa-zero/{001-HACK-mmc-meson-gx-limit-to-24MHz.patch => 001-HACK-mmc-meson-gx-limit-to-24MHz.patch.disable} (100%) create mode 100644 patch/u-boot/v2023.07.02/board_radxa-zero/003-configs-radxa-zero_defconfig-reset-board-if-failed-to-boot.patch diff --git a/patch/kernel/archive/meson64-6.6/0018-Reduce-eMMC-frequency-to-improve-compatibility.patch b/patch/kernel/archive/meson64-6.6/0018-Reduce-eMMC-frequency-to-improve-compatibility.patch new file mode 100644 index 000000000000..174932bca6a5 --- /dev/null +++ b/patch/kernel/archive/meson64-6.6/0018-Reduce-eMMC-frequency-to-improve-compatibility.patch @@ -0,0 +1,18 @@ +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Chen Jiali +Date: Tue, 23 Apr 2024 16:05:42 +0800 +Subject: [PATCH 1/1] Reduce eMMC frequency to improve compatibility + +diff --git a/arch/arm64/boot/dts/amlogic/meson-g12a-radxa-zero.dts b/arch/arm64/boot/dts/amlogic/meson-g12a-radxa-zero.dts +index cf0a9be83..29ace14b4 100644 +--- a/arch/arm64/boot/dts/amlogic/meson-g12a-radxa-zero.dts ++++ b/arch/arm64/boot/dts/amlogic/meson-g12a-radxa-zero.dts +@@ -358,7 +358,7 @@ &sd_emmc_c { + cap-mmc-highspeed; + mmc-ddr-1_8v; + mmc-hs200-1_8v; +- max-frequency = <200000000>; ++ max-frequency = <150000000>; + disable-wp; + + mmc-pwrseq = <&emmc_pwrseq>; diff --git a/patch/u-boot/v2023.07.02/board_radxa-zero/001-HACK-fix-meson-mmc-core-phase-in-the-tuning-process.patch b/patch/u-boot/v2023.07.02/board_radxa-zero/001-HACK-fix-meson-mmc-core-phase-in-the-tuning-process.patch new file mode 100644 index 000000000000..b02d79d7bbeb --- /dev/null +++ b/patch/u-boot/v2023.07.02/board_radxa-zero/001-HACK-fix-meson-mmc-core-phase-in-the-tuning-process.patch @@ -0,0 +1,52 @@ +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: ZHANG Yuntian <95260730+RadxaYuntian@users.noreply.github.com> +Date: Mon, 21 Aug 2023 15:28:09 +0800 +Subject: HACK: fix meson mmc core phase in the tuning process + +This is needed to use with Samsung eMMC module. + +Tested with Samsung, Foresee, and YMTC eMMC modules on Radxa Zero. + +Idea taken from the following patch and comments: +https://patchwork.ozlabs.org/project/uboot/patch/20191126211206.4537-2-linux.amoon@gmail.com/ +--- + drivers/mmc/meson_gx_mmc.c | 5 +++-- + drivers/mmc/meson_gx_mmc.h | 4 ++++ + 2 files changed, 7 insertions(+), 2 deletions(-) + +diff --git a/drivers/mmc/meson_gx_mmc.c b/drivers/mmc/meson_gx_mmc.c +index 111111111111..222222222222 100644 +--- a/drivers/mmc/meson_gx_mmc.c ++++ b/drivers/mmc/meson_gx_mmc.c +@@ -71,10 +71,11 @@ static void meson_mmc_config_clock(struct mmc *mmc) + if (meson_gx_mmc_is_compatible(mmc->dev, MMC_COMPATIBLE_SM1)) + meson_mmc_clk |= CLK_CO_PHASE_270; + else +- meson_mmc_clk |= CLK_CO_PHASE_180; ++ meson_mmc_clk |= CLK_CO_PHASE_090; + +- /* 180 phase tx clock */ ++ /* 000 phase tx & rx clock */ + meson_mmc_clk |= CLK_TX_PHASE_000; ++ meson_mmc_clk |= CLK_RX_PHASE_000; + + /* clock settings */ + meson_mmc_clk |= clk_src; +diff --git a/drivers/mmc/meson_gx_mmc.h b/drivers/mmc/meson_gx_mmc.h +index 111111111111..222222222222 100644 +--- a/drivers/mmc/meson_gx_mmc.h ++++ b/drivers/mmc/meson_gx_mmc.h +@@ -33,6 +33,10 @@ enum meson_gx_mmc_compatible { + #define CLK_TX_PHASE_090 (1 << 10) + #define CLK_TX_PHASE_180 (2 << 10) + #define CLK_TX_PHASE_270 (3 << 10) ++#define CLK_RX_PHASE_000 (0 << 12) ++#define CLK_RX_PHASE_090 (1 << 12) ++#define CLK_RX_PHASE_180 (2 << 12) ++#define CLK_RX_PHASE_270 (3 << 12) + #define CLK_ALWAYS_ON BIT(24) + + #define MESON_SD_EMMC_CFG 0x44 +-- +Armbian + diff --git a/patch/u-boot/v2023.07.02/board_radxa-zero/001-HACK-mmc-meson-gx-limit-to-24MHz.patch b/patch/u-boot/v2023.07.02/board_radxa-zero/001-HACK-mmc-meson-gx-limit-to-24MHz.patch.disable similarity index 100% rename from patch/u-boot/v2023.07.02/board_radxa-zero/001-HACK-mmc-meson-gx-limit-to-24MHz.patch rename to patch/u-boot/v2023.07.02/board_radxa-zero/001-HACK-mmc-meson-gx-limit-to-24MHz.patch.disable diff --git a/patch/u-boot/v2023.07.02/board_radxa-zero/003-configs-radxa-zero_defconfig-reset-board-if-failed-to-boot.patch b/patch/u-boot/v2023.07.02/board_radxa-zero/003-configs-radxa-zero_defconfig-reset-board-if-failed-to-boot.patch new file mode 100644 index 000000000000..5ca54f82087c --- /dev/null +++ b/patch/u-boot/v2023.07.02/board_radxa-zero/003-configs-radxa-zero_defconfig-reset-board-if-failed-to-boot.patch @@ -0,0 +1,22 @@ +From d2e637bf6a433d0a991800e00489ca2535cb8965 Mon Sep 17 00:00:00 2001 +From: ZHANG Yuntian +Date: Thu, 27 Jul 2023 15:58:56 +0800 +Subject: configs: radxa-zero_defconfig: reset board if failed to boot + +Signed-off-by: ZHANG Yuntian +--- + configs/radxa-zero_defconfig | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/configs/radxa-zero_defconfig b/configs/radxa-zero_defconfig +index 111111111111..222222222222 100644 +--- a/configs/radxa-zero_defconfig ++++ b/configs/radxa-zero_defconfig +@@ -1,5 +1,6 @@ + CONFIG_ARM=y + CONFIG_ARCH_MESON=y ++CONFIG_BOOTCOMMAND="bootflow scan; run distro_bootcmd; echo Boot failed. Reset in 3 seconds...; sleep 3; reset;" + CONFIG_TEXT_BASE=0x01000000 + CONFIG_NR_DRAM_BANKS=1 + CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +-- From 55adb93544018620225cda5252531e10ddc54d0b Mon Sep 17 00:00:00 2001 From: Chen Jiali Date: Wed, 4 Dec 2024 17:40:49 +0800 Subject: [PATCH 015/120] fix: radxa-zero: slow down sdio for all kernel branch --- ...-dts-slow-down-sdio-for-working-emmc.patch} | 0 ...o-dts-slow-down-sdio-for-working-emmc.patch | 18 ++++++++++++++++++ ...o-dts-slow-down-sdio-for-working-emmc.patch | 18 ++++++++++++++++++ 3 files changed, 36 insertions(+) rename patch/kernel/archive/{meson64-6.6/0018-Reduce-eMMC-frequency-to-improve-compatibility.patch => meson64-6.1/board-radxa-zero-dts-slow-down-sdio-for-working-emmc.patch} (100%) create mode 100644 patch/kernel/archive/meson64-6.12/board-radxa-zero-dts-slow-down-sdio-for-working-emmc.patch create mode 100644 patch/kernel/archive/meson64-6.6/board-radxa-zero-dts-slow-down-sdio-for-working-emmc.patch diff --git a/patch/kernel/archive/meson64-6.6/0018-Reduce-eMMC-frequency-to-improve-compatibility.patch b/patch/kernel/archive/meson64-6.1/board-radxa-zero-dts-slow-down-sdio-for-working-emmc.patch similarity index 100% rename from patch/kernel/archive/meson64-6.6/0018-Reduce-eMMC-frequency-to-improve-compatibility.patch rename to patch/kernel/archive/meson64-6.1/board-radxa-zero-dts-slow-down-sdio-for-working-emmc.patch diff --git a/patch/kernel/archive/meson64-6.12/board-radxa-zero-dts-slow-down-sdio-for-working-emmc.patch b/patch/kernel/archive/meson64-6.12/board-radxa-zero-dts-slow-down-sdio-for-working-emmc.patch new file mode 100644 index 000000000000..174932bca6a5 --- /dev/null +++ b/patch/kernel/archive/meson64-6.12/board-radxa-zero-dts-slow-down-sdio-for-working-emmc.patch @@ -0,0 +1,18 @@ +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Chen Jiali +Date: Tue, 23 Apr 2024 16:05:42 +0800 +Subject: [PATCH 1/1] Reduce eMMC frequency to improve compatibility + +diff --git a/arch/arm64/boot/dts/amlogic/meson-g12a-radxa-zero.dts b/arch/arm64/boot/dts/amlogic/meson-g12a-radxa-zero.dts +index cf0a9be83..29ace14b4 100644 +--- a/arch/arm64/boot/dts/amlogic/meson-g12a-radxa-zero.dts ++++ b/arch/arm64/boot/dts/amlogic/meson-g12a-radxa-zero.dts +@@ -358,7 +358,7 @@ &sd_emmc_c { + cap-mmc-highspeed; + mmc-ddr-1_8v; + mmc-hs200-1_8v; +- max-frequency = <200000000>; ++ max-frequency = <150000000>; + disable-wp; + + mmc-pwrseq = <&emmc_pwrseq>; diff --git a/patch/kernel/archive/meson64-6.6/board-radxa-zero-dts-slow-down-sdio-for-working-emmc.patch b/patch/kernel/archive/meson64-6.6/board-radxa-zero-dts-slow-down-sdio-for-working-emmc.patch new file mode 100644 index 000000000000..174932bca6a5 --- /dev/null +++ b/patch/kernel/archive/meson64-6.6/board-radxa-zero-dts-slow-down-sdio-for-working-emmc.patch @@ -0,0 +1,18 @@ +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Chen Jiali +Date: Tue, 23 Apr 2024 16:05:42 +0800 +Subject: [PATCH 1/1] Reduce eMMC frequency to improve compatibility + +diff --git a/arch/arm64/boot/dts/amlogic/meson-g12a-radxa-zero.dts b/arch/arm64/boot/dts/amlogic/meson-g12a-radxa-zero.dts +index cf0a9be83..29ace14b4 100644 +--- a/arch/arm64/boot/dts/amlogic/meson-g12a-radxa-zero.dts ++++ b/arch/arm64/boot/dts/amlogic/meson-g12a-radxa-zero.dts +@@ -358,7 +358,7 @@ &sd_emmc_c { + cap-mmc-highspeed; + mmc-ddr-1_8v; + mmc-hs200-1_8v; +- max-frequency = <200000000>; ++ max-frequency = <150000000>; + disable-wp; + + mmc-pwrseq = <&emmc_pwrseq>; From 9eaaaae0441affa23202825ca59ba0b3fbe299f1 Mon Sep 17 00:00:00 2001 From: amazingfate Date: Sun, 1 Dec 2024 12:00:40 +0800 Subject: [PATCH 016/120] sm8250: bump current and edge to 6.12 --- config/sources/families/sm8250.conf | 6 +- ...m8250-move-lpass-codec-macros-to-use.patch | 96 -------- ...si-add-set-column-page-multi-helpers.patch | 43 ---- .../0001-drm-Add-drm-notifier-support.patch | 0 ...el-turn-on-off-signal-to-touchscreen.patch | 0 ...Input-Add-nt36523-touchscreen-driver.patch | 2 +- ...m8250-xiaomi-elish-enable-wifi-and-b.patch | 10 +- ...m8250-xiaomi-elish-enable-touchscree.patch | 4 +- ...006-ASoC-qcom-sm8250-Add-tdm-support.patch | 6 +- ...m8250-xiaomi-elish-Add-sound-support.patch | 4 +- ...0008-Asoc-wm_adsp-Add-prefix-support.patch | 0 ...m8250-oneplus-instantnoodlep-Add-dev.patch | 2 +- ...ge-sync-mode-to-sync-on-DSI0-rather-.patch | 0 ...dpu1-improve-support-for-active-CTLs.patch | 0 ...e-one-active-CTL-if-it-is-available.patch} | 20 +- ...late-has_active_ctls-in-the-catalog.patch} | 0 ..._encoder_phys_-proper-support-for-ac.patch | 0 ...-BIT-DPU_CTL_SPLIT_DISPLAY-from-acti.patch | 4 +- ...m8250-xiaomi-elish-add-keyboard-supp.patch | 4 +- ...m8250-xiaomi-elish-remove-framebuffe.patch | 0 ...-use-devm_mipi_dsi_-function-to-reg.patch} | 0 ...019-input-nt36xxx-Enable-pen-support.patch | 118 ++++++++++ ...020-nt36xxx-add-pen-input-resolution.patch | 58 +++++ ...m8250-oneplus-instantnoodlep-Restore.patch | 217 ++++++++++++++++++ ...pmi-spmi-pmic-arb.c-remove-warnings.patch} | 0 ...adsp-Use-xiaomi-elish-firmware-name.patch} | 0 ...rt-the-firmware-download-delay-from.patch} | 2 +- ...d-mipi_dsi_generic_write_multi_type.patch} | 4 +- ...panel-add-driver-for-samsung-amb655x.patch | 6 +- ...creen-add-Synaptics-TCM-oncell-S3908.patch | 15 +- ...-arm64-dts-qcom-add-OnePlus-8T-kebab.patch | 2 +- ...om-Add-venus-firmware-for-OnePlus-8T.patch | 0 ...t-choke-on-disabling-the-writeback-.patch} | 9 +- ...8250-add-uart16-Signed-off-by-Teguh.patch} | 16 +- ...er-for-Qualcomm-SMB5-Signed-off-by-.patch} | 34 ++- ...power-supply-Driver-for-Qualcomm-FG.patch} | 15 +- ...8150b-Add-a-charger-Signed-off-by-T.patch} | 12 +- ...8150b-Add-a-FG-Signed-off-by-Teguh-.patch} | 10 +- ...C-CH13726A-panel-Signed-off-by-Tegu.patch} | 25 +- ...or-HEROIC-HTR3212-Signed-off-by-Teg.patch} | 19 +- ...-Input-driver-for-AYN-Odin2-Gamepad.patch} | 15 +- ...ut-add-Qualcomm-SPMI-haptics-driver.patch} | 18 +- ...qcom-pm8150b-introduce-spmi-haptics.patch} | 10 +- ...d-SM8250-Retroid-Pocket-variant-Sig.patch} | 29 ++- .../0042-tools-disable-sched_ext_clean.patch | 25 ++ 45 files changed, 558 insertions(+), 302 deletions(-) delete mode 100644 patch/kernel/archive/sm8250-6.11/0019-arm64-dts-qcom-sm8250-move-lpass-codec-macros-to-use.patch delete mode 100644 patch/kernel/archive/sm8250-6.11/0025-drm-mipi-dsi-add-set-column-page-multi-helpers.patch rename patch/kernel/archive/{sm8250-6.11 => sm8250-6.12}/0001-drm-Add-drm-notifier-support.patch (100%) rename patch/kernel/archive/{sm8250-6.11 => sm8250-6.12}/0002-drm-dsi-emit-panel-turn-on-off-signal-to-touchscreen.patch (100%) rename patch/kernel/archive/{sm8250-6.11 => sm8250-6.12}/0003-Input-Add-nt36523-touchscreen-driver.patch (99%) rename patch/kernel/archive/{sm8250-6.11 => sm8250-6.12}/0004-arm64-dts-qcom-sm8250-xiaomi-elish-enable-wifi-and-b.patch (94%) rename patch/kernel/archive/{sm8250-6.11 => sm8250-6.12}/0005-arm64-dts-qcom-sm8250-xiaomi-elish-enable-touchscree.patch (97%) rename patch/kernel/archive/{sm8250-6.11 => sm8250-6.12}/0006-ASoC-qcom-sm8250-Add-tdm-support.patch (96%) rename patch/kernel/archive/{sm8250-6.11 => sm8250-6.12}/0007-arm64-dts-qcom-sm8250-xiaomi-elish-Add-sound-support.patch (98%) rename patch/kernel/archive/{sm8250-6.11 => sm8250-6.12}/0008-Asoc-wm_adsp-Add-prefix-support.patch (100%) rename patch/kernel/archive/{sm8250-6.11 => sm8250-6.12}/0009-arm64-dts-qcom-sm8250-oneplus-instantnoodlep-Add-dev.patch (99%) rename patch/kernel/archive/{sm8250-6.11 => sm8250-6.12}/0010-drm-msm-dsi-change-sync-mode-to-sync-on-DSI0-rather-.patch (100%) rename patch/kernel/archive/{sm8250-6.11 => sm8250-6.12}/0011-drm-msm-dpu1-improve-support-for-active-CTLs.patch (100%) rename patch/kernel/archive/{sm8250-6.11/0012-drm-msm-dpu1-use-one-active-CTL-if-it-is-available.patch.disabled => sm8250-6.12/0012-drm-msm-dpu1-use-one-active-CTL-if-it-is-available.patch} (87%) rename patch/kernel/archive/{sm8250-6.11/0013-drm-msm-dpu-populate-has_active_ctls-in-the-catalog.patch.disabled => sm8250-6.12/0013-drm-msm-dpu-populate-has_active_ctls-in-the-catalog.patch} (100%) rename patch/kernel/archive/{sm8250-6.11 => sm8250-6.12}/0014-drm-msm-dpu1-dpu_encoder_phys_-proper-support-for-ac.patch (100%) rename patch/kernel/archive/{sm8250-6.11 => sm8250-6.12}/0015-drm-msm-dpu-Drop-BIT-DPU_CTL_SPLIT_DISPLAY-from-acti.patch (98%) rename patch/kernel/archive/{sm8250-6.11 => sm8250-6.12}/0016-arm64-dts-qcom-sm8250-xiaomi-elish-add-keyboard-supp.patch (95%) rename patch/kernel/archive/{sm8250-6.11 => sm8250-6.12}/0017-arm64-dts-qcom-sm8250-xiaomi-elish-remove-framebuffe.patch (100%) rename patch/kernel/archive/{sm8250-6.11/0020-drm-panel-nt36523-use-devm_mipi_dsi_-function-to-reg.patch => sm8250-6.12/0018-drm-panel-nt36523-use-devm_mipi_dsi_-function-to-reg.patch} (100%) create mode 100644 patch/kernel/archive/sm8250-6.12/0019-input-nt36xxx-Enable-pen-support.patch create mode 100644 patch/kernel/archive/sm8250-6.12/0020-nt36xxx-add-pen-input-resolution.patch create mode 100644 patch/kernel/archive/sm8250-6.12/0021-arm64-dts-qcom-sm8250-oneplus-instantnoodlep-Restore.patch rename patch/kernel/archive/{sm8250-6.11/0021-drivers-spmi-spmi-pmic-arb.c-remove-warnings.patch => sm8250-6.12/0022-drivers-spmi-spmi-pmic-arb.c-remove-warnings.patch} (100%) rename patch/kernel/archive/{sm8250-6.11/0022-Asoc-wm_adsp-Use-xiaomi-elish-firmware-name.patch => sm8250-6.12/0023-Asoc-wm_adsp-Use-xiaomi-elish-firmware-name.patch} (100%) rename patch/kernel/archive/{sm8250-6.11/0023-input-nt36523-short-the-firmware-download-delay-from.patch => sm8250-6.12/0024-input-nt36523-short-the-firmware-download-delay-from.patch} (93%) rename patch/kernel/archive/{sm8250-6.11/0024-drm-mipi-add-mipi_dsi_generic_write_multi_type.patch => sm8250-6.12/0025-drm-mipi-add-mipi_dsi_generic_write_multi_type.patch} (95%) rename patch/kernel/archive/{sm8250-6.11 => sm8250-6.12}/0026-drm-panel-add-driver-for-samsung-amb655x.patch (98%) rename patch/kernel/archive/{sm8250-6.11 => sm8250-6.12}/0027-Input-touchscreen-add-Synaptics-TCM-oncell-S3908.patch (98%) rename patch/kernel/archive/{sm8250-6.11 => sm8250-6.12}/0028-arm64-dts-qcom-add-OnePlus-8T-kebab.patch (99%) rename patch/kernel/archive/{sm8250-6.11 => sm8250-6.12}/0029-arm64-dts-qcom-Add-venus-firmware-for-OnePlus-8T.patch (100%) rename patch/kernel/archive/{sm8250-6.11/0030_drm-msm-dpu1--don't-choke-on-disabling-the-writeba.patch => sm8250-6.12/0030-drm-msm-dpu1-don-t-choke-on-disabling-the-writeback-.patch} (88%) rename patch/kernel/archive/{sm8250-6.11/0031_arm64--dts--qcom--sm8250--add-uart16-Signed-off-by.patch => sm8250-6.12/0031-arm64-dts-qcom-sm8250-add-uart16-Signed-off-by-Teguh.patch} (77%) rename patch/kernel/archive/{sm8250-6.11/0032_power--supply--Driver-for-Qualcomm-SMB5-Signed-off.patch => sm8250-6.12/0032-power-supply-Driver-for-Qualcomm-SMB5-Signed-off-by-.patch} (97%) rename patch/kernel/archive/{sm8250-6.11/0033_power--supply--Driver-for-Qualcomm-FG.patch => sm8250-6.12/0033-power-supply-Driver-for-Qualcomm-FG.patch} (99%) rename patch/kernel/archive/{sm8250-6.11/0034_arm64--dts--qcom--pm8150b--Add-a-charger-Signed-of.patch => sm8250-6.12/0034-arm64-dts-qcom-pm8150b-Add-a-charger-Signed-off-by-T.patch} (82%) rename patch/kernel/archive/{sm8250-6.11/0035_arm64--dts--qcom--pm8150b--Add-a-FG-Signed-off-by-.patch => sm8250-6.12/0035-arm64-dts-qcom-pm8150b-Add-a-FG-Signed-off-by-Teguh-.patch} (77%) rename patch/kernel/archive/{sm8250-6.11/0036_drm--panel--Add-DDIC-CH13726A-panel-Signed-off-by-.patch => sm8250-6.12/0036-drm-panel-Add-DDIC-CH13726A-panel-Signed-off-by-Tegu.patch} (94%) rename patch/kernel/archive/{sm8250-6.11/0037_leds--Add-driver-for-HEROIC-HTR3212-Signed-off-by-.patch => sm8250-6.12/0037-leds-Add-driver-for-HEROIC-HTR3212-Signed-off-by-Teg.patch} (94%) rename patch/kernel/archive/{sm8250-6.11/0038_Input--driver-for-AYN-Odin2-Gamepad.patch => sm8250-6.12/0038-Input-driver-for-AYN-Odin2-Gamepad.patch} (96%) rename patch/kernel/archive/{sm8250-6.11/0039_input--add-Qualcomm-SPMI-haptics-driver.patch => sm8250-6.12/0039-input-add-Qualcomm-SPMI-haptics-driver.patch} (98%) rename patch/kernel/archive/{sm8250-6.11/0040_arm64--dts--qcom--pm8150b--introduce-spmi-haptics.patch => sm8250-6.12/0040-arm64-dts-qcom-pm8150b-introduce-spmi-haptics.patch} (82%) rename patch/kernel/archive/{sm8250-6.11/0041_arm64--dts--qcom--add-SM8250-Retroid-Pocket-varian.patch => sm8250-6.12/0041-arm64-dts-qcom-add-SM8250-Retroid-Pocket-variant-Sig.patch} (97%) create mode 100644 patch/kernel/archive/sm8250-6.12/0042-tools-disable-sched_ext_clean.patch diff --git a/config/sources/families/sm8250.conf b/config/sources/families/sm8250.conf index a0e4874bf1fe..da72ed0c511b 100644 --- a/config/sources/families/sm8250.conf +++ b/config/sources/families/sm8250.conf @@ -16,13 +16,13 @@ enable_extension "image-output-abl" case $BRANCH in current) - declare -g KERNEL_MAJOR_MINOR="6.11" # Major and minor versions of this kernel. - declare -g KERNELBRANCH='branch:linux-6.11.y' + declare -g KERNEL_MAJOR_MINOR="6.12" # Major and minor versions of this kernel. + declare -g KERNELBRANCH='branch:linux-6.12.y' declare -g -i KERNEL_GIT_CACHE_TTL=120 # 2 minutes; this is a high-traffic repo ;; edge) - declare -g KERNEL_MAJOR_MINOR="6.10" # Major and minor versions of this kernel. + declare -g KERNEL_MAJOR_MINOR="6.12" # Major and minor versions of this kernel. ;; esac diff --git a/patch/kernel/archive/sm8250-6.11/0019-arm64-dts-qcom-sm8250-move-lpass-codec-macros-to-use.patch b/patch/kernel/archive/sm8250-6.11/0019-arm64-dts-qcom-sm8250-move-lpass-codec-macros-to-use.patch deleted file mode 100644 index c55a83e1fba9..000000000000 --- a/patch/kernel/archive/sm8250-6.11/0019-arm64-dts-qcom-sm8250-move-lpass-codec-macros-to-use.patch +++ /dev/null @@ -1,96 +0,0 @@ -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Srinivas Kandagatla -Date: Thu, 15 Aug 2024 18:05:42 +0100 -Subject: arm64: dts: qcom: sm8250: move lpass codec macros to use clks - directly - -Move lpass codecs va and wsa macros to use the clks directly from -AFE clock controller instead of going via gfm mux like other codec macros -and SoCs. - -This makes it more align with the other SoCs and codec macros in this SoC -which take AFE clocks directly. This will also avoid an extra clk mux layer, -provides consistency and avoids the buggy mux driver which will be removed. - -This should also fix RB5 audio. - -Remove the gfm mux drivers for both audiocc and aoncc. - -Signed-off-by: Srinivas Kandagatla ---- - arch/arm64/boot/dts/qcom/sm8250.dtsi | 31 ++-------- - 1 file changed, 4 insertions(+), 27 deletions(-) - -diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi -index 111111111111..222222222222 100644 ---- a/arch/arm64/boot/dts/qcom/sm8250.dtsi -+++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi -@@ -8,8 +8,6 @@ - #include - #include - #include --#include --#include - #include - #include - #include -@@ -2633,14 +2631,13 @@ tcsr: syscon@1fc0000 { - wsamacro: codec@3240000 { - compatible = "qcom,sm8250-lpass-wsa-macro"; - reg = <0 0x03240000 0 0x1000>; -- clocks = <&audiocc LPASS_CDC_WSA_MCLK>, -- <&audiocc LPASS_CDC_WSA_NPL>, -+ clocks = <&q6afecc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, -+ <&q6afecc LPASS_CLK_ID_TX_CORE_NPL_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, - <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, - <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, -- <&aoncc LPASS_CDC_VA_MCLK>, - <&vamacro>; - -- clock-names = "mclk", "npl", "macro", "dcodec", "va", "fsgen"; -+ clock-names = "mclk", "npl", "macro", "dcodec", "fsgen"; - - #clock-cells = <0>; - clock-output-names = "mclk"; -@@ -2674,20 +2671,10 @@ swr0: soundwire@3250000 { - status = "disabled"; - }; - -- audiocc: clock-controller@3300000 { -- compatible = "qcom,sm8250-lpass-audiocc"; -- reg = <0 0x03300000 0 0x30000>; -- #clock-cells = <1>; -- clocks = <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, -- <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, -- <&q6afecc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>; -- clock-names = "core", "audio", "bus"; -- }; -- - vamacro: codec@3370000 { - compatible = "qcom,sm8250-lpass-va-macro"; - reg = <0 0x03370000 0 0x1000>; -- clocks = <&aoncc LPASS_CDC_VA_MCLK>, -+ clocks = <&q6afecc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, - <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, - <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>; - -@@ -2792,16 +2779,6 @@ swr2: soundwire@3230000 { - #size-cells = <0>; - }; - -- aoncc: clock-controller@3380000 { -- compatible = "qcom,sm8250-lpass-aoncc"; -- reg = <0 0x03380000 0 0x40000>; -- #clock-cells = <1>; -- clocks = <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, -- <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, -- <&q6afecc LPASS_CLK_ID_TX_CORE_NPL_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>; -- clock-names = "core", "audio", "bus"; -- }; -- - lpass_tlmm: pinctrl@33c0000 { - compatible = "qcom,sm8250-lpass-lpi-pinctrl"; - reg = <0 0x033c0000 0x0 0x20000>, --- -Armbian - diff --git a/patch/kernel/archive/sm8250-6.11/0025-drm-mipi-dsi-add-set-column-page-multi-helpers.patch b/patch/kernel/archive/sm8250-6.11/0025-drm-mipi-dsi-add-set-column-page-multi-helpers.patch deleted file mode 100644 index 40589713c455..000000000000 --- a/patch/kernel/archive/sm8250-6.11/0025-drm-mipi-dsi-add-set-column-page-multi-helpers.patch +++ /dev/null @@ -1,43 +0,0 @@ -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Caleb Connolly -Date: Sun, 30 Jun 2024 20:36:28 +0200 -Subject: drm/mipi-dsi: add set column/page multi helpers - -Introduce mipi_dsi_dcs_set_column_address_multi() and -mipi_dsi_dcs_set_page_address_multi() helpers. - -Signed-off-by: Caleb Connolly ---- - include/drm/drm_mipi_dsi.h | 16 ++++++++++ - 1 file changed, 16 insertions(+) - -diff --git a/include/drm/drm_mipi_dsi.h b/include/drm/drm_mipi_dsi.h -index 111111111111..222222222222 100644 ---- a/include/drm/drm_mipi_dsi.h -+++ b/include/drm/drm_mipi_dsi.h -@@ -442,6 +442,22 @@ void mipi_dsi_dcs_set_tear_on_multi(struct mipi_dsi_multi_context *ctx, - mipi_dsi_dcs_write_buffer_multi(ctx, d, ARRAY_SIZE(d)); \ - } while (0) - -+#define mipi_dsi_dcs_set_column_address_multi(ctx, start, end) \ -+ do { \ -+ static const u8 d[] = { MIPI_DCS_SET_COLUMN_ADDRESS, \ -+ (start) >> 8, (start) & 0xff, \ -+ (end) >> 8, (end) & 0xff }; \ -+ mipi_dsi_dcs_write_buffer_multi(ctx, d, ARRAY_SIZE(d)); \ -+ } while (0) -+ -+#define mipi_dsi_dcs_set_page_address_multi(ctx, start, end) \ -+ do { \ -+ static const u8 d[] = { MIPI_DCS_SET_PAGE_ADDRESS, \ -+ (start) >> 8, (start) & 0xff, \ -+ (end) >> 8, (end) & 0xff }; \ -+ mipi_dsi_dcs_write_buffer_multi(ctx, d, ARRAY_SIZE(d)); \ -+ } while (0) -+ - /** - * mipi_dsi_dcs_write_long_multi - transmit a DCS long command with payload - * @ctx: Context for multiple DSI transactions --- -Armbian - diff --git a/patch/kernel/archive/sm8250-6.11/0001-drm-Add-drm-notifier-support.patch b/patch/kernel/archive/sm8250-6.12/0001-drm-Add-drm-notifier-support.patch similarity index 100% rename from patch/kernel/archive/sm8250-6.11/0001-drm-Add-drm-notifier-support.patch rename to patch/kernel/archive/sm8250-6.12/0001-drm-Add-drm-notifier-support.patch diff --git a/patch/kernel/archive/sm8250-6.11/0002-drm-dsi-emit-panel-turn-on-off-signal-to-touchscreen.patch b/patch/kernel/archive/sm8250-6.12/0002-drm-dsi-emit-panel-turn-on-off-signal-to-touchscreen.patch similarity index 100% rename from patch/kernel/archive/sm8250-6.11/0002-drm-dsi-emit-panel-turn-on-off-signal-to-touchscreen.patch rename to patch/kernel/archive/sm8250-6.12/0002-drm-dsi-emit-panel-turn-on-off-signal-to-touchscreen.patch diff --git a/patch/kernel/archive/sm8250-6.11/0003-Input-Add-nt36523-touchscreen-driver.patch b/patch/kernel/archive/sm8250-6.12/0003-Input-Add-nt36523-touchscreen-driver.patch similarity index 99% rename from patch/kernel/archive/sm8250-6.11/0003-Input-Add-nt36523-touchscreen-driver.patch rename to patch/kernel/archive/sm8250-6.12/0003-Input-Add-nt36523-touchscreen-driver.patch index b347a3b3515f..41aec6a8f27e 100644 --- a/patch/kernel/archive/sm8250-6.11/0003-Input-Add-nt36523-touchscreen-driver.patch +++ b/patch/kernel/archive/sm8250-6.12/0003-Input-Add-nt36523-touchscreen-driver.patch @@ -31,7 +31,7 @@ diff --git a/drivers/input/touchscreen/Makefile b/drivers/input/touchscreen/Make index 111111111111..222222222222 100644 --- a/drivers/input/touchscreen/Makefile +++ b/drivers/input/touchscreen/Makefile -@@ -121,3 +121,4 @@ obj-$(CONFIG_TOUCHSCREEN_IQS5XX) += iqs5xx.o +@@ -117,3 +117,4 @@ obj-$(CONFIG_TOUCHSCREEN_IQS5XX) += iqs5xx.o obj-$(CONFIG_TOUCHSCREEN_IQS7211) += iqs7211.o obj-$(CONFIG_TOUCHSCREEN_ZINITIX) += zinitix.o obj-$(CONFIG_TOUCHSCREEN_HIMAX_HX83112B) += himax_hx83112b.o diff --git a/patch/kernel/archive/sm8250-6.11/0004-arm64-dts-qcom-sm8250-xiaomi-elish-enable-wifi-and-b.patch b/patch/kernel/archive/sm8250-6.12/0004-arm64-dts-qcom-sm8250-xiaomi-elish-enable-wifi-and-b.patch similarity index 94% rename from patch/kernel/archive/sm8250-6.11/0004-arm64-dts-qcom-sm8250-xiaomi-elish-enable-wifi-and-b.patch rename to patch/kernel/archive/sm8250-6.12/0004-arm64-dts-qcom-sm8250-xiaomi-elish-enable-wifi-and-b.patch index 494ebd383a49..4750ef828042 100644 --- a/patch/kernel/archive/sm8250-6.11/0004-arm64-dts-qcom-sm8250-xiaomi-elish-enable-wifi-and-b.patch +++ b/patch/kernel/archive/sm8250-6.12/0004-arm64-dts-qcom-sm8250-xiaomi-elish-enable-wifi-and-b.patch @@ -5,8 +5,8 @@ Subject: arm64: dts: qcom: sm8250-xiaomi-elish: enable wifi and bluetooth Signed-off-by: Jianhua Lu --- - arch/arm64/boot/dts/qcom/sm8250-xiaomi-elish-common.dtsi | 113 ++++++++++ - 1 file changed, 113 insertions(+) + arch/arm64/boot/dts/qcom/sm8250-xiaomi-elish-common.dtsi | 115 ++++++++++ + 1 file changed, 115 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8250-xiaomi-elish-common.dtsi b/arch/arm64/boot/dts/qcom/sm8250-xiaomi-elish-common.dtsi index 111111111111..222222222222 100644 @@ -91,7 +91,7 @@ index 111111111111..222222222222 100644 reserved-memory { xbl_aop_mem: xbl-aop@80600000 { reg = <0x0 0x80600000 0x0 0x260000>; -@@ -619,6 +684,23 @@ &pcie0_phy { +@@ -619,6 +684,25 @@ &pcie0_phy { status = "okay"; }; @@ -109,13 +109,15 @@ index 111111111111..222222222222 100644 + vddrfa1p7-supply = <&vreg_pmu_rfa_1p7>; + vddpcie0p9-supply = <&vreg_pmu_pcie_0p9>; + vddpcie1p8-supply = <&vreg_pmu_pcie_1p8>; ++ ++ qcom,ath11k-calibration-variant = "Xiaomi_Pad_5Pro"; + }; +}; + &pm8150_gpios { vol_up_n: vol-up-n-state { pins = "gpio6"; -@@ -701,6 +783,37 @@ &slpi { +@@ -701,6 +785,37 @@ &slpi { &tlmm { gpio-reserved-ranges = <40 4>; diff --git a/patch/kernel/archive/sm8250-6.11/0005-arm64-dts-qcom-sm8250-xiaomi-elish-enable-touchscree.patch b/patch/kernel/archive/sm8250-6.12/0005-arm64-dts-qcom-sm8250-xiaomi-elish-enable-touchscree.patch similarity index 97% rename from patch/kernel/archive/sm8250-6.11/0005-arm64-dts-qcom-sm8250-xiaomi-elish-enable-touchscree.patch rename to patch/kernel/archive/sm8250-6.12/0005-arm64-dts-qcom-sm8250-xiaomi-elish-enable-touchscree.patch index 62966402d797..516e29c66a0e 100644 --- a/patch/kernel/archive/sm8250-6.11/0005-arm64-dts-qcom-sm8250-xiaomi-elish-enable-touchscree.patch +++ b/patch/kernel/archive/sm8250-6.12/0005-arm64-dts-qcom-sm8250-xiaomi-elish-enable-touchscree.patch @@ -27,7 +27,7 @@ diff --git a/arch/arm64/boot/dts/qcom/sm8250-xiaomi-elish-common.dtsi b/arch/arm index 111111111111..222222222222 100644 --- a/arch/arm64/boot/dts/qcom/sm8250-xiaomi-elish-common.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8250-xiaomi-elish-common.dtsi -@@ -764,6 +764,16 @@ &pon_resin { +@@ -766,6 +766,16 @@ &pon_resin { status = "okay"; }; @@ -44,7 +44,7 @@ index 111111111111..222222222222 100644 &qupv3_id_0 { status = "okay"; }; -@@ -781,6 +791,28 @@ &slpi { +@@ -783,6 +793,28 @@ &slpi { status = "okay"; }; diff --git a/patch/kernel/archive/sm8250-6.11/0006-ASoC-qcom-sm8250-Add-tdm-support.patch b/patch/kernel/archive/sm8250-6.12/0006-ASoC-qcom-sm8250-Add-tdm-support.patch similarity index 96% rename from patch/kernel/archive/sm8250-6.11/0006-ASoC-qcom-sm8250-Add-tdm-support.patch rename to patch/kernel/archive/sm8250-6.12/0006-ASoC-qcom-sm8250-Add-tdm-support.patch index 7f9a5991ba62..a1a63d040936 100644 --- a/patch/kernel/archive/sm8250-6.11/0006-ASoC-qcom-sm8250-Add-tdm-support.patch +++ b/patch/kernel/archive/sm8250-6.12/0006-ASoC-qcom-sm8250-Add-tdm-support.patch @@ -86,8 +86,8 @@ index 111111111111..222222222222 100644 + int ret,j; switch (cpu_dai->id) { - case TERTIARY_MI2S_RX: -@@ -63,6 +118,21 @@ static int sm8250_snd_startup(struct snd_pcm_substream *substream) + case PRIMARY_MI2S_RX: +@@ -71,6 +126,21 @@ static int sm8250_snd_startup(struct snd_pcm_substream *substream) snd_soc_dai_set_fmt(cpu_dai, fmt); snd_soc_dai_set_fmt(codec_dai, codec_dai_fmt); break; @@ -109,7 +109,7 @@ index 111111111111..222222222222 100644 default: break; } -@@ -88,6 +158,11 @@ static int sm8250_snd_hw_params(struct snd_pcm_substream *substream, +@@ -96,6 +166,11 @@ static int sm8250_snd_hw_params(struct snd_pcm_substream *substream, struct snd_soc_dai *cpu_dai = snd_soc_rtd_to_cpu(rtd, 0); struct sm8250_snd_data *pdata = snd_soc_card_get_drvdata(rtd->card); diff --git a/patch/kernel/archive/sm8250-6.11/0007-arm64-dts-qcom-sm8250-xiaomi-elish-Add-sound-support.patch b/patch/kernel/archive/sm8250-6.12/0007-arm64-dts-qcom-sm8250-xiaomi-elish-Add-sound-support.patch similarity index 98% rename from patch/kernel/archive/sm8250-6.11/0007-arm64-dts-qcom-sm8250-xiaomi-elish-Add-sound-support.patch rename to patch/kernel/archive/sm8250-6.12/0007-arm64-dts-qcom-sm8250-xiaomi-elish-Add-sound-support.patch index 9b4575c657c4..869ac8acf6f4 100644 --- a/patch/kernel/archive/sm8250-6.11/0007-arm64-dts-qcom-sm8250-xiaomi-elish-Add-sound-support.patch +++ b/patch/kernel/archive/sm8250-6.12/0007-arm64-dts-qcom-sm8250-xiaomi-elish-Add-sound-support.patch @@ -173,7 +173,7 @@ index 111111111111..222222222222 100644 &i2c11 { clock-frequency = <400000>; status = "okay"; -@@ -786,11 +934,63 @@ &qupv3_id_2 { +@@ -788,11 +936,63 @@ &qupv3_id_2 { status = "okay"; }; @@ -237,7 +237,7 @@ index 111111111111..222222222222 100644 &spi4 { status = "okay"; pinctrl-names = "default"; -@@ -831,6 +1031,38 @@ wlan_en_state: wlan-default-state { +@@ -833,6 +1033,38 @@ wlan_en_state: wlan-default-state { output-low; bias-pull-up; }; diff --git a/patch/kernel/archive/sm8250-6.11/0008-Asoc-wm_adsp-Add-prefix-support.patch b/patch/kernel/archive/sm8250-6.12/0008-Asoc-wm_adsp-Add-prefix-support.patch similarity index 100% rename from patch/kernel/archive/sm8250-6.11/0008-Asoc-wm_adsp-Add-prefix-support.patch rename to patch/kernel/archive/sm8250-6.12/0008-Asoc-wm_adsp-Add-prefix-support.patch diff --git a/patch/kernel/archive/sm8250-6.11/0009-arm64-dts-qcom-sm8250-oneplus-instantnoodlep-Add-dev.patch b/patch/kernel/archive/sm8250-6.12/0009-arm64-dts-qcom-sm8250-oneplus-instantnoodlep-Add-dev.patch similarity index 99% rename from patch/kernel/archive/sm8250-6.11/0009-arm64-dts-qcom-sm8250-oneplus-instantnoodlep-Add-dev.patch rename to patch/kernel/archive/sm8250-6.12/0009-arm64-dts-qcom-sm8250-oneplus-instantnoodlep-Add-dev.patch index 2b07d24e8fe5..5992076411eb 100644 --- a/patch/kernel/archive/sm8250-6.11/0009-arm64-dts-qcom-sm8250-oneplus-instantnoodlep-Add-dev.patch +++ b/patch/kernel/archive/sm8250-6.12/0009-arm64-dts-qcom-sm8250-oneplus-instantnoodlep-Add-dev.patch @@ -13,7 +13,7 @@ diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefi index 111111111111..222222222222 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile -@@ -235,6 +235,7 @@ dtb-$(CONFIG_ARCH_QCOM) += sm8150-sony-xperia-kumano-bahamut.dtb +@@ -242,6 +242,7 @@ dtb-$(CONFIG_ARCH_QCOM) += sm8150-sony-xperia-kumano-bahamut.dtb dtb-$(CONFIG_ARCH_QCOM) += sm8150-sony-xperia-kumano-griffin.dtb dtb-$(CONFIG_ARCH_QCOM) += sm8250-hdk.dtb dtb-$(CONFIG_ARCH_QCOM) += sm8250-mtp.dtb diff --git a/patch/kernel/archive/sm8250-6.11/0010-drm-msm-dsi-change-sync-mode-to-sync-on-DSI0-rather-.patch b/patch/kernel/archive/sm8250-6.12/0010-drm-msm-dsi-change-sync-mode-to-sync-on-DSI0-rather-.patch similarity index 100% rename from patch/kernel/archive/sm8250-6.11/0010-drm-msm-dsi-change-sync-mode-to-sync-on-DSI0-rather-.patch rename to patch/kernel/archive/sm8250-6.12/0010-drm-msm-dsi-change-sync-mode-to-sync-on-DSI0-rather-.patch diff --git a/patch/kernel/archive/sm8250-6.11/0011-drm-msm-dpu1-improve-support-for-active-CTLs.patch b/patch/kernel/archive/sm8250-6.12/0011-drm-msm-dpu1-improve-support-for-active-CTLs.patch similarity index 100% rename from patch/kernel/archive/sm8250-6.11/0011-drm-msm-dpu1-improve-support-for-active-CTLs.patch rename to patch/kernel/archive/sm8250-6.12/0011-drm-msm-dpu1-improve-support-for-active-CTLs.patch diff --git a/patch/kernel/archive/sm8250-6.11/0012-drm-msm-dpu1-use-one-active-CTL-if-it-is-available.patch.disabled b/patch/kernel/archive/sm8250-6.12/0012-drm-msm-dpu1-use-one-active-CTL-if-it-is-available.patch similarity index 87% rename from patch/kernel/archive/sm8250-6.11/0012-drm-msm-dpu1-use-one-active-CTL-if-it-is-available.patch.disabled rename to patch/kernel/archive/sm8250-6.12/0012-drm-msm-dpu1-use-one-active-CTL-if-it-is-available.patch index bebd5a5f1193..61dd7e04aa29 100644 --- a/patch/kernel/archive/sm8250-6.11/0012-drm-msm-dpu1-use-one-active-CTL-if-it-is-available.patch.disabled +++ b/patch/kernel/archive/sm8250-6.12/0012-drm-msm-dpu1-use-one-active-CTL-if-it-is-available.patch @@ -10,37 +10,29 @@ available. Signed-off-by: Dmitry Baryshkov --- - drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 8 ++++-- + drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 6 +++- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 1 + drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c | 14 +++++++--- drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h | 1 + - 4 files changed, 18 insertions(+), 6 deletions(-) + 4 files changed, 17 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c index 111111111111..222222222222 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c -@@ -1180,14 +1180,18 @@ static void dpu_encoder_virt_atomic_mode_set(struct drm_encoder *drm_enc, +@@ -1198,7 +1198,11 @@ static void dpu_encoder_virt_atomic_mode_set(struct drm_encoder *drm_enc, return; } -- if (!hw_ctl[i]) { +- phys->hw_ctl = i < num_ctl ? to_dpu_hw_ctl(hw_ctl[i]) : NULL; + /* Use first (and only) CTL if active CTLs are supported */ + if (dpu_kms->catalog->caps->has_active_ctls) + phys->hw_ctl = to_dpu_hw_ctl(hw_ctl[0]); + else -+ phys->hw_ctl = to_dpu_hw_ctl(hw_ctl[i]); -+ if (!phys->hw_ctl) { ++ phys->hw_ctl = i < num_ctl ? to_dpu_hw_ctl(hw_ctl[i]) : NULL; + if (!phys->hw_ctl) { DPU_ERROR_ENC(dpu_enc, "no ctl block assigned at idx: %d\n", i); - return; - } - - phys->hw_pp = dpu_enc->hw_pp[i]; -- phys->hw_ctl = to_dpu_hw_ctl(hw_ctl[i]); - - phys->cached_mode = crtc_state->adjusted_mode; - if (phys->ops.atomic_mode_set) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h index 111111111111..222222222222 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h diff --git a/patch/kernel/archive/sm8250-6.11/0013-drm-msm-dpu-populate-has_active_ctls-in-the-catalog.patch.disabled b/patch/kernel/archive/sm8250-6.12/0013-drm-msm-dpu-populate-has_active_ctls-in-the-catalog.patch similarity index 100% rename from patch/kernel/archive/sm8250-6.11/0013-drm-msm-dpu-populate-has_active_ctls-in-the-catalog.patch.disabled rename to patch/kernel/archive/sm8250-6.12/0013-drm-msm-dpu-populate-has_active_ctls-in-the-catalog.patch diff --git a/patch/kernel/archive/sm8250-6.11/0014-drm-msm-dpu1-dpu_encoder_phys_-proper-support-for-ac.patch b/patch/kernel/archive/sm8250-6.12/0014-drm-msm-dpu1-dpu_encoder_phys_-proper-support-for-ac.patch similarity index 100% rename from patch/kernel/archive/sm8250-6.11/0014-drm-msm-dpu1-dpu_encoder_phys_-proper-support-for-ac.patch rename to patch/kernel/archive/sm8250-6.12/0014-drm-msm-dpu1-dpu_encoder_phys_-proper-support-for-ac.patch diff --git a/patch/kernel/archive/sm8250-6.11/0015-drm-msm-dpu-Drop-BIT-DPU_CTL_SPLIT_DISPLAY-from-acti.patch b/patch/kernel/archive/sm8250-6.12/0015-drm-msm-dpu-Drop-BIT-DPU_CTL_SPLIT_DISPLAY-from-acti.patch similarity index 98% rename from patch/kernel/archive/sm8250-6.11/0015-drm-msm-dpu-Drop-BIT-DPU_CTL_SPLIT_DISPLAY-from-acti.patch rename to patch/kernel/archive/sm8250-6.12/0015-drm-msm-dpu-Drop-BIT-DPU_CTL_SPLIT_DISPLAY-from-acti.patch index 82a3959e819e..ecbb0d58dc36 100644 --- a/patch/kernel/archive/sm8250-6.11/0015-drm-msm-dpu-Drop-BIT-DPU_CTL_SPLIT_DISPLAY-from-acti.patch +++ b/patch/kernel/archive/sm8250-6.12/0015-drm-msm-dpu-Drop-BIT-DPU_CTL_SPLIT_DISPLAY-from-acti.patch @@ -21,7 +21,7 @@ diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h b/drivers/gp index 111111111111..222222222222 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h -@@ -37,17 +37,16 @@ static const struct dpu_mdp_cfg sm8150_mdp = { +@@ -38,17 +38,16 @@ static const struct dpu_mdp_cfg sm8150_mdp = { }, }; @@ -45,7 +45,7 @@ diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h b/drivers/g index 111111111111..222222222222 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h -@@ -41,12 +41,12 @@ static const struct dpu_ctl_cfg sc8180x_ctl[] = { +@@ -42,12 +42,12 @@ static const struct dpu_ctl_cfg sc8180x_ctl[] = { { .name = "ctl_0", .id = CTL_0, .base = 0x1000, .len = 0x1e0, diff --git a/patch/kernel/archive/sm8250-6.11/0016-arm64-dts-qcom-sm8250-xiaomi-elish-add-keyboard-supp.patch b/patch/kernel/archive/sm8250-6.12/0016-arm64-dts-qcom-sm8250-xiaomi-elish-add-keyboard-supp.patch similarity index 95% rename from patch/kernel/archive/sm8250-6.11/0016-arm64-dts-qcom-sm8250-xiaomi-elish-add-keyboard-supp.patch rename to patch/kernel/archive/sm8250-6.12/0016-arm64-dts-qcom-sm8250-xiaomi-elish-add-keyboard-supp.patch index aa847f88f993..8815c6953024 100644 --- a/patch/kernel/archive/sm8250-6.11/0016-arm64-dts-qcom-sm8250-xiaomi-elish-add-keyboard-supp.patch +++ b/patch/kernel/archive/sm8250-6.12/0016-arm64-dts-qcom-sm8250-xiaomi-elish-add-keyboard-supp.patch @@ -27,7 +27,7 @@ index 111111111111..222222222222 100644 &mdss { status = "okay"; }; -@@ -1063,6 +1072,14 @@ dout-pins { +@@ -1065,6 +1074,14 @@ dout-pins { bias-disable; }; }; @@ -42,7 +42,7 @@ index 111111111111..222222222222 100644 }; &uart6 { -@@ -1106,6 +1123,29 @@ &usb_1_dwc3_hs_out { +@@ -1108,6 +1125,29 @@ &usb_1_dwc3_hs_out { remote-endpoint = <&pm8150b_hs_in>; }; diff --git a/patch/kernel/archive/sm8250-6.11/0017-arm64-dts-qcom-sm8250-xiaomi-elish-remove-framebuffe.patch b/patch/kernel/archive/sm8250-6.12/0017-arm64-dts-qcom-sm8250-xiaomi-elish-remove-framebuffe.patch similarity index 100% rename from patch/kernel/archive/sm8250-6.11/0017-arm64-dts-qcom-sm8250-xiaomi-elish-remove-framebuffe.patch rename to patch/kernel/archive/sm8250-6.12/0017-arm64-dts-qcom-sm8250-xiaomi-elish-remove-framebuffe.patch diff --git a/patch/kernel/archive/sm8250-6.11/0020-drm-panel-nt36523-use-devm_mipi_dsi_-function-to-reg.patch b/patch/kernel/archive/sm8250-6.12/0018-drm-panel-nt36523-use-devm_mipi_dsi_-function-to-reg.patch similarity index 100% rename from patch/kernel/archive/sm8250-6.11/0020-drm-panel-nt36523-use-devm_mipi_dsi_-function-to-reg.patch rename to patch/kernel/archive/sm8250-6.12/0018-drm-panel-nt36523-use-devm_mipi_dsi_-function-to-reg.patch diff --git a/patch/kernel/archive/sm8250-6.12/0019-input-nt36xxx-Enable-pen-support.patch b/patch/kernel/archive/sm8250-6.12/0019-input-nt36xxx-Enable-pen-support.patch new file mode 100644 index 000000000000..9818a190c7e5 --- /dev/null +++ b/patch/kernel/archive/sm8250-6.12/0019-input-nt36xxx-Enable-pen-support.patch @@ -0,0 +1,118 @@ +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: map220v +Date: Tue, 28 Nov 2023 15:28:53 +0300 +Subject: input: nt36xxx: Enable pen support + +--- + drivers/input/touchscreen/nt36523/nt36xxx.c | 47 +++++++++- + drivers/input/touchscreen/nt36523/nt36xxx.h | 1 + + drivers/input/touchscreen/nt36523/nt36xxx_fw_update.c | 1 + + 3 files changed, 45 insertions(+), 4 deletions(-) + +diff --git a/drivers/input/touchscreen/nt36523/nt36xxx.c b/drivers/input/touchscreen/nt36523/nt36xxx.c +index 111111111111..222222222222 100644 +--- a/drivers/input/touchscreen/nt36523/nt36xxx.c ++++ b/drivers/input/touchscreen/nt36523/nt36xxx.c +@@ -1173,6 +1173,43 @@ static int8_t nvt_ts_check_chip_ver_trim(uint32_t chip_ver_trim_addr) + return 0; + } + ++int32_t disable_pen_input_device(bool disable) { ++ uint8_t buf[8] = {0}; ++ int32_t ret = 0; ++ ++ NVT_LOG("++\n"); ++ if (!bTouchIsAwake || !ts) { ++ NVT_LOG("touch suspend, stop set pen state %s", disable ? "DISABLE" : "ENABLE"); ++ goto nvt_set_pen_enable_out; ++ } ++ ++ msleep(35); ++ disable = (!(ts->pen_input_dev_enable) || ts->pen_is_charge) ? true : disable; ++ ++ //---set xdata index to EVENT BUF ADDR--- ++ ret = nvt_set_page(ts->mmap->EVENT_BUF_ADDR | EVENT_MAP_HOST_CMD); ++ if (ret < 0) { ++ NVT_ERR("Set event buffer index fail!\n"); ++ goto nvt_set_pen_enable_out; ++ } ++ ++ buf[0] = EVENT_MAP_HOST_CMD; ++ buf[1] = 0x7B; ++ buf[2] = !!disable; ++ ret = CTP_SPI_WRITE(ts->client, buf, 3); ++ if (ret < 0) { ++ NVT_ERR("set pen %s failed!\n", disable ? "DISABLE" : "ENABLE"); ++ goto nvt_set_pen_enable_out; ++ } ++ NVT_LOG("pen charge state is %s, %s pen input device\n", ++ ts->pen_is_charge ? "ENABLE" : "DISABLE", ++ disable ? "DISABLE" : "ENABLE"); ++ ++nvt_set_pen_enable_out: ++ NVT_LOG("--\n"); ++ return ret; ++} ++ + static void nvt_suspend_work(struct work_struct *work) + { + struct nvt_ts_data *ts_core = container_of(work, struct nvt_ts_data, suspend_work); +@@ -1437,11 +1474,11 @@ static int32_t nvt_ts_probe(struct spi_device *client) + init_completion(&ts->dev_pm_suspend_completion); + ts->fw_debug = false; + +-#ifdef CONFIG_FACTORY_BUILD ++//#ifdef CONFIG_FACTORY_BUILD + ts->pen_input_dev_enable = 1; +-#else +- ts->pen_input_dev_enable = 0; +-#endif ++//#else ++// ts->pen_input_dev_enable = 0; ++//#endif + + #if BOOT_UPDATE_FIRMWARE + nvt_fwu_wq = alloc_workqueue("nvt_fwu_wq", WQ_UNBOUND | WQ_MEM_RECLAIM, 1); +@@ -1701,6 +1738,7 @@ static int32_t nvt_ts_suspend(struct device *dev) + + if (ts->pen_input_dev_enable) { + NVT_LOG("if enable pen,will close it"); ++ disable_pen_input_device(true); + } + + if (ts->db_wakeup) { +@@ -1798,6 +1836,7 @@ static int32_t nvt_ts_resume(struct device *dev) + + mutex_unlock(&ts->lock); + ++ disable_pen_input_device(false); + if (likely(ts->ic_state == NVT_IC_RESUME_IN)) { + ts->ic_state = NVT_IC_RESUME_OUT; + } else { +diff --git a/drivers/input/touchscreen/nt36523/nt36xxx.h b/drivers/input/touchscreen/nt36523/nt36xxx.h +index 111111111111..222222222222 100644 +--- a/drivers/input/touchscreen/nt36523/nt36xxx.h ++++ b/drivers/input/touchscreen/nt36523/nt36xxx.h +@@ -235,6 +235,7 @@ int32_t nvt_read_pid(void); + bool nvt_get_dbgfw_status(void); + int32_t nvt_set_pocket_palm_switch(uint8_t pocket_palm_switch); + void Boot_Update_Firmware(struct work_struct *work); ++int32_t disable_pen_input_device(bool disable); + #if NVT_TOUCH_ESD_PROTECT + extern void nvt_esd_check_enable(uint8_t enable); + #endif /* #if NVT_TOUCH_ESD_PROTECT */ +diff --git a/drivers/input/touchscreen/nt36523/nt36xxx_fw_update.c b/drivers/input/touchscreen/nt36523/nt36xxx_fw_update.c +index 111111111111..222222222222 100644 +--- a/drivers/input/touchscreen/nt36523/nt36xxx_fw_update.c ++++ b/drivers/input/touchscreen/nt36523/nt36xxx_fw_update.c +@@ -851,6 +851,7 @@ void Boot_Update_Firmware(struct work_struct *work) + { + mutex_lock(&ts->lock); + nvt_update_firmware(ts->fw_name); ++ disable_pen_input_device(false); + nvt_get_fw_info(); + mutex_unlock(&ts->lock); + } +-- +Armbian + diff --git a/patch/kernel/archive/sm8250-6.12/0020-nt36xxx-add-pen-input-resolution.patch b/patch/kernel/archive/sm8250-6.12/0020-nt36xxx-add-pen-input-resolution.patch new file mode 100644 index 000000000000..58cab04a837b --- /dev/null +++ b/patch/kernel/archive/sm8250-6.12/0020-nt36xxx-add-pen-input-resolution.patch @@ -0,0 +1,58 @@ +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Nicola Guerrera +Date: Thu, 14 Nov 2024 22:57:02 +0100 +Subject: nt36xxx: add pen input resolution + +--- + drivers/input/touchscreen/nt36523/nt36xxx.c | 15 +++++++--- + drivers/input/touchscreen/nt36523/nt36xxx.h | 4 ++- + 2 files changed, 14 insertions(+), 5 deletions(-) + +diff --git a/drivers/input/touchscreen/nt36523/nt36xxx.c b/drivers/input/touchscreen/nt36523/nt36xxx.c +index 111111111111..222222222222 100644 +--- a/drivers/input/touchscreen/nt36523/nt36xxx.c ++++ b/drivers/input/touchscreen/nt36523/nt36xxx.c +@@ -1421,14 +1421,21 @@ static int32_t nvt_ts_probe(struct spi_device *client) + ts->pen_input_dev->keybit[BIT_WORD(BTN_STYLUS2)] |= BIT_MASK(BTN_STYLUS2); + ts->pen_input_dev->propbit[0] = BIT(INPUT_PROP_DIRECT); + ++ int x_max, y_max; ++ + if (ts->wgp_stylus) { +- input_set_abs_params(ts->pen_input_dev, ABS_X, 0, ts->abs_x_max * 2 - 1, 0, 0); +- input_set_abs_params(ts->pen_input_dev, ABS_Y, 0, ts->abs_y_max * 2 - 1, 0, 0); ++ x_max = ts->abs_x_max * 2 - 1; ++ y_max = ts->abs_y_max * 2 - 1; + } else { +- input_set_abs_params(ts->pen_input_dev, ABS_X, 0, ts->abs_x_max - 1, 0, 0); +- input_set_abs_params(ts->pen_input_dev, ABS_Y, 0, ts->abs_y_max - 1, 0, 0); ++ x_max = ts->abs_x_max - 1; ++ y_max = ts->abs_y_max - 1; + } + ++ input_set_abs_params(ts->pen_input_dev, ABS_X, 0, x_max, 0, 0); ++ input_set_abs_params(ts->pen_input_dev, ABS_Y, 0, y_max , 0, 0); ++ input_abs_set_res(ts->pen_input_dev, ABS_X, x_max / PANEL_DEFAULT_WIDTH_MM); ++ input_abs_set_res(ts->pen_input_dev, ABS_Y, y_max / PANEL_DEFAULT_HEIGHT_MM); ++ + input_set_abs_params(ts->pen_input_dev, ABS_PRESSURE, 0, PEN_PRESSURE_MAX, 0, 0); + input_set_abs_params(ts->pen_input_dev, ABS_DISTANCE, 0, PEN_DISTANCE_MAX, 0, 0); + input_set_abs_params(ts->pen_input_dev, ABS_TILT_X, PEN_TILT_MIN, PEN_TILT_MAX, 0, 0); +diff --git a/drivers/input/touchscreen/nt36523/nt36xxx.h b/drivers/input/touchscreen/nt36523/nt36xxx.h +index 111111111111..222222222222 100644 +--- a/drivers/input/touchscreen/nt36523/nt36xxx.h ++++ b/drivers/input/touchscreen/nt36523/nt36xxx.h +@@ -70,7 +70,9 @@ extern const uint16_t touch_key_array[TOUCH_KEY_NUM]; + #define PEN_DISTANCE_MAX (1) + #define PEN_TILT_MIN (-60) + #define PEN_TILT_MAX (60) +- ++//---for pen resolution--- ++#define PANEL_DEFAULT_WIDTH_MM 148 // 148mm ++#define PANEL_DEFAULT_HEIGHT_MM 237 // 237mm + /* Enable only when module have tp reset pin and connected to host */ + #define NVT_TOUCH_SUPPORT_HW_RST 0 + +-- +Armbian + diff --git a/patch/kernel/archive/sm8250-6.12/0021-arm64-dts-qcom-sm8250-oneplus-instantnoodlep-Restore.patch b/patch/kernel/archive/sm8250-6.12/0021-arm64-dts-qcom-sm8250-oneplus-instantnoodlep-Restore.patch new file mode 100644 index 000000000000..126477e153d0 --- /dev/null +++ b/patch/kernel/archive/sm8250-6.12/0021-arm64-dts-qcom-sm8250-oneplus-instantnoodlep-Restore.patch @@ -0,0 +1,217 @@ +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Denys Vitali +Date: Fri, 22 Nov 2024 15:50:44 +0100 +Subject: arm64: dts: qcom: sm8250-oneplus-instantnoodlep: Restore Wi-Fi / BT + functionality + +--- + arch/arm64/boot/dts/qcom/sm8250-oneplus-instantnoodlep.dts | 131 ++++++++-- + 1 file changed, 110 insertions(+), 21 deletions(-) + +diff --git a/arch/arm64/boot/dts/qcom/sm8250-oneplus-instantnoodlep.dts b/arch/arm64/boot/dts/qcom/sm8250-oneplus-instantnoodlep.dts +index 111111111111..222222222222 100644 +--- a/arch/arm64/boot/dts/qcom/sm8250-oneplus-instantnoodlep.dts ++++ b/arch/arm64/boot/dts/qcom/sm8250-oneplus-instantnoodlep.dts +@@ -78,6 +78,67 @@ vol-down { + gpio-key,wakeup; + }; + }; ++ ++ qca6390-pmu { ++ compatible = "qcom,qca6390-pmu"; ++ ++ pinctrl-names = "default"; ++ pinctrl-0 = <&bt_en_state>, <&wlan_en_state>; ++ ++ vddaon-supply = <&vreg_s6a_0p95>; ++ vddpmu-supply = <&vreg_s2f_0p95>; ++ vddrfa0p95-supply = <&vreg_s2f_0p95>; ++ vddrfa1p3-supply = <&vreg_s8c_1p3>; ++ vddrfa1p9-supply = <&vreg_s5a_1p9>; ++ vddpcie1p3-supply = <&vreg_s8c_1p3>; ++ vddpcie1p9-supply = <&vreg_s5a_1p9>; ++ vddio-supply = <&vreg_s4a_1p8>; ++ ++ wlan-enable-gpios = <&tlmm 20 GPIO_ACTIVE_HIGH>; ++ bt-enable-gpios = <&tlmm 21 GPIO_ACTIVE_HIGH>; ++ ++ regulators { ++ vreg_pmu_rfa_cmn: ldo0 { ++ regulator-name = "vreg_pmu_rfa_cmn"; ++ }; ++ ++ vreg_pmu_aon_0p59: ldo1 { ++ regulator-name = "vreg_pmu_aon_0p59"; ++ }; ++ ++ vreg_pmu_wlcx_0p8: ldo2 { ++ regulator-name = "vreg_pmu_wlcx_0p8"; ++ }; ++ ++ vreg_pmu_wlmx_0p85: ldo3 { ++ regulator-name = "vreg_pmu_wlmx_0p85"; ++ }; ++ ++ vreg_pmu_btcmx_0p85: ldo4 { ++ regulator-name = "vreg_pmu_btcmx_0p85"; ++ }; ++ ++ vreg_pmu_rfa_0p8: ldo5 { ++ regulator-name = "vreg_pmu_rfa_0p8"; ++ }; ++ ++ vreg_pmu_rfa_1p2: ldo6 { ++ regulator-name = "vreg_pmu_rfa_1p2"; ++ }; ++ ++ vreg_pmu_rfa_1p7: ldo7 { ++ regulator-name = "vreg_pmu_rfa_1p7"; ++ }; ++ ++ vreg_pmu_pcie_0p9: ldo8 { ++ regulator-name = "vreg_pmu_pcie_0p9"; ++ }; ++ ++ vreg_pmu_pcie_1p8: ldo9 { ++ regulator-name = "vreg_pmu_pcie_1p8"; ++ }; ++ }; ++ }; + + reserved-memory { + removed_mem: memory@80b00000 { +@@ -192,7 +253,7 @@ vreg_s4a_1p8: vreg-s4a-1p8 { + qca639x: qca639x { + compatible = "qcom,qca6390"; + #power-domain-cells = <0>; +- ++ + vddaon-supply = <&vreg_s6a_0p95>; + vddpmu-supply = <&vreg_s2f_0p95>; + vddrfa1-supply = <&vreg_s2f_0p95>; +@@ -203,9 +264,9 @@ qca639x: qca639x { + vddio-supply = <&vreg_s4a_1p8>; + + pinctrl-names = "default", "sleep"; +- pinctrl-0 = <&wlan_en_active>; ++ pinctrl-0 = <&wlan_en_state>; + pinctrl-1 = <&wlan_en_sleep>; +- ++ + wlan-en-gpios = <&tlmm 20 GPIO_ACTIVE_HIGH>; + }; + +@@ -390,6 +451,7 @@ vreg_s5a_1p9: smps5 { + regulator-initial-mode = ; + }; + ++ + vreg_s6a_0p95: smps6 { + regulator-name = "vreg_s6a_0p95"; + regulator-min-microvolt = <920000>; +@@ -614,15 +676,32 @@ &slpi { + status = "okay"; + }; + ++ + &pcie0 { + status = "okay"; + }; + + &pcie0_phy { ++ status = "okay"; + vdda-phy-supply = <&vreg_l5a_0p88>; + vdda-pll-supply = <&vreg_l9a_1p2>; +- status = "okay"; +- power-domains = <&qca639x>; ++}; ++ ++&pcieport0 { ++ wifi@0 { ++ compatible = "pci17cb,1101"; ++ reg = <0x10000 0x0 0x0 0x0 0x0>; ++ ++ vddrfacmn-supply = <&vreg_pmu_rfa_cmn>; ++ vddaon-supply = <&vreg_pmu_aon_0p59>; ++ vddwlcx-supply = <&vreg_pmu_wlcx_0p8>; ++ vddwlmx-supply = <&vreg_pmu_wlmx_0p85>; ++ vddrfa0p8-supply = <&vreg_pmu_rfa_0p8>; ++ vddrfa1p2-supply = <&vreg_pmu_rfa_1p2>; ++ vddrfa1p7-supply = <&vreg_pmu_rfa_1p7>; ++ vddpcie0p9-supply = <&vreg_pmu_pcie_0p9>; ++ vddpcie1p8-supply = <&vreg_pmu_pcie_1p8>; ++ }; + }; + + &pcie1 { +@@ -697,7 +776,7 @@ &qupv3_id_2 { + &tlmm { + gpio-reserved-ranges = <28 4>, <40 4>; + +- bt_en_active: bt-default-state { ++ bt_en_state: bt-default-state { + bt-en { + pins = "gpio21"; + function = "gpio"; +@@ -717,7 +796,7 @@ bt_en_sleep: bt-sleep-state { + bias-pull-down; + }; + +- wlan_en_active: wlan-default-state { ++ wlan_en_state: wlan-default-state { + wlan-en { + pins = "gpio20"; + function = "gpio"; +@@ -752,20 +831,6 @@ ts_rst_suspend: ts-rst-suspend { + }; + }; + +-&uart6 { +- status = "okay"; +- +- bluetooth { +- compatible = "qcom,qca6390-bt"; +- pinctrl-names = "default", "sleep"; +- pinctrl-0 = <&bt_en_active>; +- pinctrl-1 = <&bt_en_sleep>; +- +- power-domains = <&qca639x>; +- enable-gpios = <&tlmm 21 GPIO_ACTIVE_HIGH>; +- }; +-}; +- + &ufs_mem_hc { + vcc-supply = <&vreg_l17a_3p0>; + vcc-max-microamp = <800000>; +@@ -830,3 +895,27 @@ &venus { + firmware-name = "postmarketos/venus.mbn"; + status = "okay"; + }; ++ ++ ++&uart6 { ++ status = "okay"; ++ ++ bluetooth { ++ compatible = "qcom,qca6390-bt"; ++ ++ vddrfacmn-supply = <&vreg_pmu_rfa_cmn>; ++ vddaon-supply = <&vreg_pmu_aon_0p59>; ++ vddbtcmx-supply = <&vreg_pmu_btcmx_0p85>; ++ vddrfa0p8-supply = <&vreg_pmu_rfa_0p8>; ++ vddrfa1p2-supply = <&vreg_pmu_rfa_1p2>; ++ vddrfa1p7-supply = <&vreg_pmu_rfa_1p7>; ++ }; ++}; ++ ++&qup_i2c7_default { ++ status = "disabled"; ++}; ++ ++&qup_spi7_data_clk { ++ status = "disabled"; ++}; +\ No newline at end of file +-- +Armbian + diff --git a/patch/kernel/archive/sm8250-6.11/0021-drivers-spmi-spmi-pmic-arb.c-remove-warnings.patch b/patch/kernel/archive/sm8250-6.12/0022-drivers-spmi-spmi-pmic-arb.c-remove-warnings.patch similarity index 100% rename from patch/kernel/archive/sm8250-6.11/0021-drivers-spmi-spmi-pmic-arb.c-remove-warnings.patch rename to patch/kernel/archive/sm8250-6.12/0022-drivers-spmi-spmi-pmic-arb.c-remove-warnings.patch diff --git a/patch/kernel/archive/sm8250-6.11/0022-Asoc-wm_adsp-Use-xiaomi-elish-firmware-name.patch b/patch/kernel/archive/sm8250-6.12/0023-Asoc-wm_adsp-Use-xiaomi-elish-firmware-name.patch similarity index 100% rename from patch/kernel/archive/sm8250-6.11/0022-Asoc-wm_adsp-Use-xiaomi-elish-firmware-name.patch rename to patch/kernel/archive/sm8250-6.12/0023-Asoc-wm_adsp-Use-xiaomi-elish-firmware-name.patch diff --git a/patch/kernel/archive/sm8250-6.11/0023-input-nt36523-short-the-firmware-download-delay-from.patch b/patch/kernel/archive/sm8250-6.12/0024-input-nt36523-short-the-firmware-download-delay-from.patch similarity index 93% rename from patch/kernel/archive/sm8250-6.11/0023-input-nt36523-short-the-firmware-download-delay-from.patch rename to patch/kernel/archive/sm8250-6.12/0024-input-nt36523-short-the-firmware-download-delay-from.patch index 8701c4e1d469..856c089f81e6 100644 --- a/patch/kernel/archive/sm8250-6.11/0023-input-nt36523-short-the-firmware-download-delay-from.patch +++ b/patch/kernel/archive/sm8250-6.12/0024-input-nt36523-short-the-firmware-download-delay-from.patch @@ -11,7 +11,7 @@ diff --git a/drivers/input/touchscreen/nt36523/nt36xxx.c b/drivers/input/touchsc index 111111111111..222222222222 100644 --- a/drivers/input/touchscreen/nt36523/nt36xxx.c +++ b/drivers/input/touchscreen/nt36523/nt36xxx.c -@@ -1452,7 +1452,7 @@ static int32_t nvt_ts_probe(struct spi_device *client) +@@ -1496,7 +1496,7 @@ static int32_t nvt_ts_probe(struct spi_device *client) } INIT_DELAYED_WORK(&ts->nvt_fwu_work, Boot_Update_Firmware); // please make sure boot update start after display reset(RESX) sequence diff --git a/patch/kernel/archive/sm8250-6.11/0024-drm-mipi-add-mipi_dsi_generic_write_multi_type.patch b/patch/kernel/archive/sm8250-6.12/0025-drm-mipi-add-mipi_dsi_generic_write_multi_type.patch similarity index 95% rename from patch/kernel/archive/sm8250-6.11/0024-drm-mipi-add-mipi_dsi_generic_write_multi_type.patch rename to patch/kernel/archive/sm8250-6.12/0025-drm-mipi-add-mipi_dsi_generic_write_multi_type.patch index e8fb4ab9e306..34bd63eacf20 100644 --- a/patch/kernel/archive/sm8250-6.11/0024-drm-mipi-add-mipi_dsi_generic_write_multi_type.patch +++ b/patch/kernel/archive/sm8250-6.12/0025-drm-mipi-add-mipi_dsi_generic_write_multi_type.patch @@ -20,7 +20,7 @@ diff --git a/drivers/gpu/drm/drm_mipi_dsi.c b/drivers/gpu/drm/drm_mipi_dsi.c index 111111111111..222222222222 100644 --- a/drivers/gpu/drm/drm_mipi_dsi.c +++ b/drivers/gpu/drm/drm_mipi_dsi.c -@@ -820,6 +820,46 @@ void mipi_dsi_generic_write_multi(struct mipi_dsi_multi_context *ctx, +@@ -824,6 +824,46 @@ void mipi_dsi_generic_write_multi(struct mipi_dsi_multi_context *ctx, } EXPORT_SYMBOL(mipi_dsi_generic_write_multi); @@ -80,7 +80,7 @@ index 111111111111..222222222222 100644 ssize_t mipi_dsi_generic_read(struct mipi_dsi_device *dsi, const void *params, size_t num_params, void *data, size_t size); -@@ -440,6 +442,20 @@ void mipi_dsi_dcs_set_tear_on_multi(struct mipi_dsi_multi_context *ctx, +@@ -452,6 +454,20 @@ void mipi_dsi_dcs_set_tear_scanline_multi(struct mipi_dsi_multi_context *ctx, mipi_dsi_dcs_write_buffer_multi(ctx, d, ARRAY_SIZE(d)); \ } while (0) diff --git a/patch/kernel/archive/sm8250-6.11/0026-drm-panel-add-driver-for-samsung-amb655x.patch b/patch/kernel/archive/sm8250-6.12/0026-drm-panel-add-driver-for-samsung-amb655x.patch similarity index 98% rename from patch/kernel/archive/sm8250-6.11/0026-drm-panel-add-driver-for-samsung-amb655x.patch rename to patch/kernel/archive/sm8250-6.12/0026-drm-panel-add-driver-for-samsung-amb655x.patch index 65b929f5144f..ce16fdcb57db 100644 --- a/patch/kernel/archive/sm8250-6.11/0026-drm-panel-add-driver-for-samsung-amb655x.patch +++ b/patch/kernel/archive/sm8250-6.12/0026-drm-panel-add-driver-for-samsung-amb655x.patch @@ -23,7 +23,7 @@ diff --git a/MAINTAINERS b/MAINTAINERS index 111111111111..222222222222 100644 --- a/MAINTAINERS +++ b/MAINTAINERS -@@ -7231,6 +7231,13 @@ S: Maintained +@@ -7334,6 +7334,13 @@ S: Maintained F: Documentation/devicetree/bindings/display/panel/raydium,rm67191.yaml F: drivers/gpu/drm/panel/panel-raydium-rm67191.c @@ -41,7 +41,7 @@ diff --git a/drivers/gpu/drm/panel/Kconfig b/drivers/gpu/drm/panel/Kconfig index 111111111111..222222222222 100644 --- a/drivers/gpu/drm/panel/Kconfig +++ b/drivers/gpu/drm/panel/Kconfig -@@ -611,6 +611,15 @@ config DRM_PANEL_SAMSUNG_S6E88A0_AMS452EF01 +@@ -620,6 +620,15 @@ config DRM_PANEL_SAMSUNG_S6E88A0_AMS452EF01 select DRM_MIPI_DSI select VIDEOMODE_HELPERS @@ -61,7 +61,7 @@ diff --git a/drivers/gpu/drm/panel/Makefile b/drivers/gpu/drm/panel/Makefile index 111111111111..222222222222 100644 --- a/drivers/gpu/drm/panel/Makefile +++ b/drivers/gpu/drm/panel/Makefile -@@ -61,6 +61,7 @@ obj-$(CONFIG_DRM_PANEL_RAYDIUM_RM68200) += panel-raydium-rm68200.o +@@ -62,6 +62,7 @@ obj-$(CONFIG_DRM_PANEL_RAYDIUM_RM68200) += panel-raydium-rm68200.o obj-$(CONFIG_DRM_PANEL_RAYDIUM_RM692E5) += panel-raydium-rm692e5.o obj-$(CONFIG_DRM_PANEL_RAYDIUM_RM69380) += panel-raydium-rm69380.o obj-$(CONFIG_DRM_PANEL_RONBO_RB070D30) += panel-ronbo-rb070d30.o diff --git a/patch/kernel/archive/sm8250-6.11/0027-Input-touchscreen-add-Synaptics-TCM-oncell-S3908.patch b/patch/kernel/archive/sm8250-6.12/0027-Input-touchscreen-add-Synaptics-TCM-oncell-S3908.patch similarity index 98% rename from patch/kernel/archive/sm8250-6.11/0027-Input-touchscreen-add-Synaptics-TCM-oncell-S3908.patch rename to patch/kernel/archive/sm8250-6.12/0027-Input-touchscreen-add-Synaptics-TCM-oncell-S3908.patch index 9abe97b62eea..e84393a9f28d 100644 --- a/patch/kernel/archive/sm8250-6.11/0027-Input-touchscreen-add-Synaptics-TCM-oncell-S3908.patch +++ b/patch/kernel/archive/sm8250-6.12/0027-Input-touchscreen-add-Synaptics-TCM-oncell-S3908.patch @@ -23,14 +23,14 @@ Signed-off-by: Caleb Connolly MAINTAINERS | 7 + drivers/input/touchscreen/Kconfig | 11 + drivers/input/touchscreen/Makefile | 1 + - drivers/input/touchscreen/synaptics_tcm_oncell.c | 571 ++++++++++ - 4 files changed, 590 insertions(+) + drivers/input/touchscreen/synaptics_tcm_oncell.c | 570 ++++++++++ + 4 files changed, 589 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 111111111111..222222222222 100644 --- a/MAINTAINERS +++ b/MAINTAINERS -@@ -22082,6 +22082,13 @@ S: Maintained +@@ -22333,6 +22333,13 @@ S: Maintained F: Documentation/devicetree/bindings/regulator/silergy,sy8106a.yaml F: drivers/regulator/sy8106a-regulator.c @@ -48,7 +48,7 @@ diff --git a/drivers/input/touchscreen/Kconfig b/drivers/input/touchscreen/Kconf index 111111111111..222222222222 100644 --- a/drivers/input/touchscreen/Kconfig +++ b/drivers/input/touchscreen/Kconfig -@@ -534,6 +534,17 @@ config TOUCHSCREEN_S6SY761 +@@ -504,6 +504,17 @@ config TOUCHSCREEN_S6SY761 To compile this driver as module, choose M here: the module will be called s6sy761. @@ -70,7 +70,7 @@ diff --git a/drivers/input/touchscreen/Makefile b/drivers/input/touchscreen/Make index 111111111111..222222222222 100644 --- a/drivers/input/touchscreen/Makefile +++ b/drivers/input/touchscreen/Makefile -@@ -89,6 +89,7 @@ obj-$(CONFIG_TOUCHSCREEN_STMPE) += stmpe-ts.o +@@ -85,6 +85,7 @@ obj-$(CONFIG_TOUCHSCREEN_STMPE) += stmpe-ts.o obj-$(CONFIG_TOUCHSCREEN_SUN4I) += sun4i-ts.o obj-$(CONFIG_TOUCHSCREEN_SUR40) += sur40.o obj-$(CONFIG_TOUCHSCREEN_SURFACE3_SPI) += surface3_spi.o @@ -83,7 +83,7 @@ new file mode 100644 index 000000000000..111111111111 --- /dev/null +++ b/drivers/input/touchscreen/synaptics_tcm_oncell.c -@@ -0,0 +1,571 @@ +@@ -0,0 +1,570 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Driver for Synaptics TCM Oncell Touchscreens @@ -92,14 +92,13 @@ index 000000000000..111111111111 + * Copyright (c) 2024 Caleb Connolly + */ + -+#include +#include +#include +#include +#include +#include +#include -+#include ++#include +#include +#include +#include diff --git a/patch/kernel/archive/sm8250-6.11/0028-arm64-dts-qcom-add-OnePlus-8T-kebab.patch b/patch/kernel/archive/sm8250-6.12/0028-arm64-dts-qcom-add-OnePlus-8T-kebab.patch similarity index 99% rename from patch/kernel/archive/sm8250-6.11/0028-arm64-dts-qcom-add-OnePlus-8T-kebab.patch rename to patch/kernel/archive/sm8250-6.12/0028-arm64-dts-qcom-add-OnePlus-8T-kebab.patch index 9bd221226aac..7580ba9f4b5c 100644 --- a/patch/kernel/archive/sm8250-6.11/0028-arm64-dts-qcom-add-OnePlus-8T-kebab.patch +++ b/patch/kernel/archive/sm8250-6.12/0028-arm64-dts-qcom-add-OnePlus-8T-kebab.patch @@ -18,7 +18,7 @@ diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefi index 111111111111..222222222222 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile -@@ -236,6 +236,7 @@ dtb-$(CONFIG_ARCH_QCOM) += sm8150-sony-xperia-kumano-griffin.dtb +@@ -243,6 +243,7 @@ dtb-$(CONFIG_ARCH_QCOM) += sm8150-sony-xperia-kumano-griffin.dtb dtb-$(CONFIG_ARCH_QCOM) += sm8250-hdk.dtb dtb-$(CONFIG_ARCH_QCOM) += sm8250-mtp.dtb dtb-$(CONFIG_ARCH_QCOM) += sm8250-oneplus-instantnoodlep.dtb diff --git a/patch/kernel/archive/sm8250-6.11/0029-arm64-dts-qcom-Add-venus-firmware-for-OnePlus-8T.patch b/patch/kernel/archive/sm8250-6.12/0029-arm64-dts-qcom-Add-venus-firmware-for-OnePlus-8T.patch similarity index 100% rename from patch/kernel/archive/sm8250-6.11/0029-arm64-dts-qcom-Add-venus-firmware-for-OnePlus-8T.patch rename to patch/kernel/archive/sm8250-6.12/0029-arm64-dts-qcom-Add-venus-firmware-for-OnePlus-8T.patch diff --git a/patch/kernel/archive/sm8250-6.11/0030_drm-msm-dpu1--don't-choke-on-disabling-the-writeba.patch b/patch/kernel/archive/sm8250-6.12/0030-drm-msm-dpu1-don-t-choke-on-disabling-the-writeback-.patch similarity index 88% rename from patch/kernel/archive/sm8250-6.11/0030_drm-msm-dpu1--don't-choke-on-disabling-the-writeba.patch rename to patch/kernel/archive/sm8250-6.12/0030-drm-msm-dpu1-don-t-choke-on-disabling-the-writeback-.patch index 4ab8620123d9..94fc5143d216 100644 --- a/patch/kernel/archive/sm8250-6.11/0030_drm-msm-dpu1--don't-choke-on-disabling-the-writeba.patch +++ b/patch/kernel/archive/sm8250-6.12/0030-drm-msm-dpu1-don-t-choke-on-disabling-the-writeback-.patch @@ -1,8 +1,7 @@ -From 5344b8b729fc379a54d6aa4fa1ae648395efa62c Mon Sep 17 00:00:00 2001 +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Fri, 2 Aug 2024 22:47:33 +0300 -Subject: [PATCH] drm/msm/dpu1: don't choke on disabling the writeback - connector +Subject: drm/msm/dpu1: don't choke on disabling the writeback connector During suspend/resume process all connectors are explicitly disabled and then reenabled. However resume fails because of the connector_status check: @@ -22,7 +21,7 @@ Signed-off-by: Dmitry Baryshkov 1 file changed, 3 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_writeback.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_writeback.c -index 16f144cbc0c98..8ff496082902b 100644 +index 111111111111..222222222222 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_writeback.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_writeback.c @@ -42,9 +42,6 @@ static int dpu_wb_conn_atomic_check(struct drm_connector *connector, @@ -36,5 +35,5 @@ index 16f144cbc0c98..8ff496082902b 100644 crtc = conn_state->crtc; -- -2.34.1 +Armbian diff --git a/patch/kernel/archive/sm8250-6.11/0031_arm64--dts--qcom--sm8250--add-uart16-Signed-off-by.patch b/patch/kernel/archive/sm8250-6.12/0031-arm64-dts-qcom-sm8250-add-uart16-Signed-off-by-Teguh.patch similarity index 77% rename from patch/kernel/archive/sm8250-6.11/0031_arm64--dts--qcom--sm8250--add-uart16-Signed-off-by.patch rename to patch/kernel/archive/sm8250-6.12/0031-arm64-dts-qcom-sm8250-add-uart16-Signed-off-by-Teguh.patch index 601d6407f28d..0bccd7f07de5 100644 --- a/patch/kernel/archive/sm8250-6.11/0031_arm64--dts--qcom--sm8250--add-uart16-Signed-off-by.patch +++ b/patch/kernel/archive/sm8250-6.12/0031-arm64-dts-qcom-sm8250-add-uart16-Signed-off-by-Teguh.patch @@ -1,18 +1,18 @@ -From 275fcb4f35b6cffcaabde3f876b4453996a77ead Mon Sep 17 00:00:00 2001 +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 From: Teguh Sobirin Date: Wed, 20 Nov 2024 22:58:09 +0700 -Subject: [PATCH] arm64: dts: qcom: sm8250: add uart16 Signed-off-by: Teguh - Sobirin +Subject: arm64: dts: qcom: sm8250: add uart16 Signed-off-by: Teguh Sobirin + --- - arch/arm64/boot/dts/qcom/sm8250.dtsi | 22 ++++++++++++++++++++++ + arch/arm64/boot/dts/qcom/sm8250.dtsi | 22 ++++++++++ 1 file changed, 22 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi -index 9d6c97d1fd9d6..eaf6cb8bdcb8f 100644 +index 111111111111..222222222222 100644 --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi -@@ -1155,6 +1155,23 @@ spi16: spi@888000 { +@@ -1153,6 +1153,23 @@ spi16: spi@888000 { status = "disabled"; }; @@ -36,7 +36,7 @@ index 9d6c97d1fd9d6..eaf6cb8bdcb8f 100644 i2c17: i2c@88c000 { compatible = "qcom,geni-i2c"; reg = <0 0x0088c000 0 0x4000>; -@@ -5748,6 +5765,11 @@ qup_uart12_default: qup-uart12-default-state { +@@ -5725,6 +5742,11 @@ qup_uart12_default: qup-uart12-default-state { function = "qup12"; }; @@ -49,5 +49,5 @@ index 9d6c97d1fd9d6..eaf6cb8bdcb8f 100644 pins = "gpio52", "gpio53", "gpio54", "gpio55"; function = "qup17"; -- -2.34.1 +Armbian diff --git a/patch/kernel/archive/sm8250-6.11/0032_power--supply--Driver-for-Qualcomm-SMB5-Signed-off.patch b/patch/kernel/archive/sm8250-6.12/0032-power-supply-Driver-for-Qualcomm-SMB5-Signed-off-by-.patch similarity index 97% rename from patch/kernel/archive/sm8250-6.11/0032_power--supply--Driver-for-Qualcomm-SMB5-Signed-off.patch rename to patch/kernel/archive/sm8250-6.12/0032-power-supply-Driver-for-Qualcomm-SMB5-Signed-off-by-.patch index 9fe70d09bec5..b6eb82558c84 100644 --- a/patch/kernel/archive/sm8250-6.11/0032_power--supply--Driver-for-Qualcomm-SMB5-Signed-off.patch +++ b/patch/kernel/archive/sm8250-6.12/0032-power-supply-Driver-for-Qualcomm-SMB5-Signed-off-by-.patch @@ -1,18 +1,17 @@ -From 8894f9ffb67033dcbfa54770c987e576e2ff82fb Mon Sep 17 00:00:00 2001 +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 From: Teguh Sobirin Date: Sun, 24 Nov 2024 23:04:43 +0700 -Subject: [PATCH] power: supply: Driver for Qualcomm SMB5 Signed-off-by: Teguh - Sobirin +Subject: power: supply: Driver for Qualcomm SMB5 Signed-off-by: Teguh Sobirin + --- drivers/power/supply/Kconfig | 9 + drivers/power/supply/Makefile | 1 + - drivers/power/supply/qcom_pm8150b_charger.c | 945 ++++++++++++++++++++ - 3 files changed, 955 insertions(+) - create mode 100644 drivers/power/supply/qcom_pm8150b_charger.c + drivers/power/supply/qcom_pm8150b_charger.c | 940 ++++++++++ + 3 files changed, 950 insertions(+) diff --git a/drivers/power/supply/Kconfig b/drivers/power/supply/Kconfig -index bcfa63fb9f1e2..ec3f3d5b20c8f 100644 +index 111111111111..222222222222 100644 --- a/drivers/power/supply/Kconfig +++ b/drivers/power/supply/Kconfig @@ -1008,6 +1008,15 @@ config CHARGER_QCOM_SMB2 @@ -32,7 +31,7 @@ index bcfa63fb9f1e2..ec3f3d5b20c8f 100644 tristate "Mitsumi MM8013 fuel gauge driver" depends on I2C diff --git a/drivers/power/supply/Makefile b/drivers/power/supply/Makefile -index 8dcb415453171..9237f62701582 100644 +index 111111111111..222222222222 100644 --- a/drivers/power/supply/Makefile +++ b/drivers/power/supply/Makefile @@ -116,4 +116,5 @@ obj-$(CONFIG_BATTERY_SURFACE) += surface_battery.o @@ -43,10 +42,10 @@ index 8dcb415453171..9237f62701582 100644 obj-$(CONFIG_FUEL_GAUGE_MM8013) += mm8013.o diff --git a/drivers/power/supply/qcom_pm8150b_charger.c b/drivers/power/supply/qcom_pm8150b_charger.c new file mode 100644 -index 0000000000000..48791e145345d +index 000000000000..111111111111 --- /dev/null +++ b/drivers/power/supply/qcom_pm8150b_charger.c -@@ -0,0 +1,945 @@ +@@ -0,0 +1,940 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2024, Teguh Sobirin . @@ -369,13 +368,6 @@ index 0000000000000..48791e145345d + POWER_SUPPLY_PROP_USB_TYPE, +}; + -+static enum power_supply_usb_type smb5_usb_types[] = { -+ POWER_SUPPLY_USB_TYPE_UNKNOWN, -+ POWER_SUPPLY_USB_TYPE_SDP, -+ POWER_SUPPLY_USB_TYPE_DCP, -+ POWER_SUPPLY_USB_TYPE_CDP, -+}; -+ +static int smb5_get_prop_usb_online(struct smb5_chip *chip, int *val) +{ + unsigned int stat; @@ -744,8 +736,10 @@ index 0000000000000..48791e145345d +static const struct power_supply_desc smb5_psy_desc = { + .name = "pmi8998_charger", + .type = POWER_SUPPLY_TYPE_USB, -+ .usb_types = smb5_usb_types, -+ .num_usb_types = ARRAY_SIZE(smb5_usb_types), ++ .usb_types = BIT(POWER_SUPPLY_USB_TYPE_SDP) | ++ BIT(POWER_SUPPLY_USB_TYPE_CDP) | ++ BIT(POWER_SUPPLY_USB_TYPE_DCP) | ++ BIT(POWER_SUPPLY_USB_TYPE_UNKNOWN), + .properties = smb5_properties, + .num_properties = ARRAY_SIZE(smb5_properties), + .get_property = smb5_get_property, @@ -993,5 +987,5 @@ index 0000000000000..48791e145345d +MODULE_DESCRIPTION("Qualcomm SMB5 Charger Driver"); +MODULE_LICENSE("GPL"); -- -2.34.1 +Armbian diff --git a/patch/kernel/archive/sm8250-6.11/0033_power--supply--Driver-for-Qualcomm-FG.patch b/patch/kernel/archive/sm8250-6.12/0033-power-supply-Driver-for-Qualcomm-FG.patch similarity index 99% rename from patch/kernel/archive/sm8250-6.11/0033_power--supply--Driver-for-Qualcomm-FG.patch rename to patch/kernel/archive/sm8250-6.12/0033-power-supply-Driver-for-Qualcomm-FG.patch index 190a8e0cca53..9085b2a41388 100644 --- a/patch/kernel/archive/sm8250-6.11/0033_power--supply--Driver-for-Qualcomm-FG.patch +++ b/patch/kernel/archive/sm8250-6.12/0033-power-supply-Driver-for-Qualcomm-FG.patch @@ -1,7 +1,7 @@ -From 98c6370f7380874d5b78871b3d24d92b74b4bdcb Mon Sep 17 00:00:00 2001 +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 From: Teguh Sobirin Date: Wed, 20 Nov 2024 23:00:52 +0700 -Subject: [PATCH] power: supply: Driver for Qualcomm FG +Subject: power: supply: Driver for Qualcomm FG support for pm8150 taken from: https://github.com/map220v/sm8150-mainline @@ -9,12 +9,11 @@ Signed-off-by: Teguh Sobirin --- drivers/power/supply/Kconfig | 8 + drivers/power/supply/Makefile | 1 + - drivers/power/supply/qcom_fg.c | 1364 ++++++++++++++++++++++++++++++++ + drivers/power/supply/qcom_fg.c | 1364 ++++++++++ 3 files changed, 1373 insertions(+) - create mode 100644 drivers/power/supply/qcom_fg.c diff --git a/drivers/power/supply/Kconfig b/drivers/power/supply/Kconfig -index ec3f3d5b20c8f..b1e56c53f6248 100644 +index 111111111111..222222222222 100644 --- a/drivers/power/supply/Kconfig +++ b/drivers/power/supply/Kconfig @@ -1017,6 +1017,14 @@ config CHARGER_QCOM_SMB5 @@ -33,7 +32,7 @@ index ec3f3d5b20c8f..b1e56c53f6248 100644 tristate "Mitsumi MM8013 fuel gauge driver" depends on I2C diff --git a/drivers/power/supply/Makefile b/drivers/power/supply/Makefile -index 9237f62701582..52a75dae57816 100644 +index 111111111111..222222222222 100644 --- a/drivers/power/supply/Makefile +++ b/drivers/power/supply/Makefile @@ -117,4 +117,5 @@ obj-$(CONFIG_CHARGER_SURFACE) += surface_charger.o @@ -44,7 +43,7 @@ index 9237f62701582..52a75dae57816 100644 obj-$(CONFIG_FUEL_GAUGE_MM8013) += mm8013.o diff --git a/drivers/power/supply/qcom_fg.c b/drivers/power/supply/qcom_fg.c new file mode 100644 -index 0000000000000..a3b164994fe4e +index 000000000000..111111111111 --- /dev/null +++ b/drivers/power/supply/qcom_fg.c @@ -0,0 +1,1364 @@ @@ -1414,5 +1413,5 @@ index 0000000000000..a3b164994fe4e +MODULE_LICENSE("GPL v2"); \ No newline at end of file -- -2.34.1 +Armbian diff --git a/patch/kernel/archive/sm8250-6.11/0034_arm64--dts--qcom--pm8150b--Add-a-charger-Signed-of.patch b/patch/kernel/archive/sm8250-6.12/0034-arm64-dts-qcom-pm8150b-Add-a-charger-Signed-off-by-T.patch similarity index 82% rename from patch/kernel/archive/sm8250-6.11/0034_arm64--dts--qcom--pm8150b--Add-a-charger-Signed-of.patch rename to patch/kernel/archive/sm8250-6.12/0034-arm64-dts-qcom-pm8150b-Add-a-charger-Signed-off-by-T.patch index 259a3f421c69..4facdb16f9de 100644 --- a/patch/kernel/archive/sm8250-6.11/0034_arm64--dts--qcom--pm8150b--Add-a-charger-Signed-of.patch +++ b/patch/kernel/archive/sm8250-6.12/0034-arm64-dts-qcom-pm8150b-Add-a-charger-Signed-off-by-T.patch @@ -1,15 +1,15 @@ -From 000b9f019f77eca40d579aa86bba3b1b63c374d0 Mon Sep 17 00:00:00 2001 +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 From: Teguh Sobirin Date: Wed, 20 Nov 2024 23:01:45 +0700 -Subject: [PATCH] arm64: dts: qcom: pm8150b: Add a charger Signed-off-by: Teguh - Sobirin +Subject: arm64: dts: qcom: pm8150b: Add a charger Signed-off-by: Teguh Sobirin + --- - arch/arm64/boot/dts/qcom/pm8150b.dtsi | 32 +++++++++++++++++++++++++++ + arch/arm64/boot/dts/qcom/pm8150b.dtsi | 32 ++++++++++ 1 file changed, 32 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/pm8150b.dtsi b/arch/arm64/boot/dts/qcom/pm8150b.dtsi -index 3f7b0b6a1d109..d0cfe63619547 100644 +index 111111111111..222222222222 100644 --- a/arch/arm64/boot/dts/qcom/pm8150b.dtsi +++ b/arch/arm64/boot/dts/qcom/pm8150b.dtsi @@ -107,6 +107,26 @@ pm8150b_temp: temp-alarm@2400 { @@ -59,5 +59,5 @@ index 3f7b0b6a1d109..d0cfe63619547 100644 reg = ; qcom,pre-scaling = <1 1>; -- -2.34.1 +Armbian diff --git a/patch/kernel/archive/sm8250-6.11/0035_arm64--dts--qcom--pm8150b--Add-a-FG-Signed-off-by-.patch b/patch/kernel/archive/sm8250-6.12/0035-arm64-dts-qcom-pm8150b-Add-a-FG-Signed-off-by-Teguh-.patch similarity index 77% rename from patch/kernel/archive/sm8250-6.11/0035_arm64--dts--qcom--pm8150b--Add-a-FG-Signed-off-by-.patch rename to patch/kernel/archive/sm8250-6.12/0035-arm64-dts-qcom-pm8150b-Add-a-FG-Signed-off-by-Teguh-.patch index 02f13ad12eda..188da5346aa6 100644 --- a/patch/kernel/archive/sm8250-6.11/0035_arm64--dts--qcom--pm8150b--Add-a-FG-Signed-off-by-.patch +++ b/patch/kernel/archive/sm8250-6.12/0035-arm64-dts-qcom-pm8150b-Add-a-FG-Signed-off-by-Teguh-.patch @@ -1,15 +1,15 @@ -From 9cf8452cf472d813961ff4a970a759d197c5b99f Mon Sep 17 00:00:00 2001 +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 From: Teguh Sobirin Date: Wed, 20 Nov 2024 23:02:30 +0700 -Subject: [PATCH] arm64: dts: qcom: pm8150b: Add a FG Signed-off-by: Teguh - Sobirin +Subject: arm64: dts: qcom: pm8150b: Add a FG Signed-off-by: Teguh Sobirin + --- arch/arm64/boot/dts/qcom/pm8150b.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/pm8150b.dtsi b/arch/arm64/boot/dts/qcom/pm8150b.dtsi -index d0cfe63619547..42ef21238f18b 100644 +index 111111111111..222222222222 100644 --- a/arch/arm64/boot/dts/qcom/pm8150b.dtsi +++ b/arch/arm64/boot/dts/qcom/pm8150b.dtsi @@ -127,6 +127,14 @@ pm8150b_charger: charger@1000 { @@ -28,5 +28,5 @@ index d0cfe63619547..42ef21238f18b 100644 compatible = "qcom,spmi-adc5"; reg = <0x3100>; -- -2.34.1 +Armbian diff --git a/patch/kernel/archive/sm8250-6.11/0036_drm--panel--Add-DDIC-CH13726A-panel-Signed-off-by-.patch b/patch/kernel/archive/sm8250-6.12/0036-drm-panel-Add-DDIC-CH13726A-panel-Signed-off-by-Tegu.patch similarity index 94% rename from patch/kernel/archive/sm8250-6.11/0036_drm--panel--Add-DDIC-CH13726A-panel-Signed-off-by-.patch rename to patch/kernel/archive/sm8250-6.12/0036-drm-panel-Add-DDIC-CH13726A-panel-Signed-off-by-Tegu.patch index f770162c3524..97baa1590c4d 100644 --- a/patch/kernel/archive/sm8250-6.11/0036_drm--panel--Add-DDIC-CH13726A-panel-Signed-off-by-.patch +++ b/patch/kernel/archive/sm8250-6.12/0036-drm-panel-Add-DDIC-CH13726A-panel-Signed-off-by-Tegu.patch @@ -1,18 +1,17 @@ -From a61edacbee6718f398f37358dc705dd434f3c219 Mon Sep 17 00:00:00 2001 +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 From: Teguh Sobirin Date: Wed, 20 Nov 2024 23:04:35 +0700 -Subject: [PATCH] drm: panel: Add DDIC CH13726A panel Signed-off-by: Teguh - Sobirin +Subject: drm: panel: Add DDIC CH13726A panel Signed-off-by: Teguh Sobirin + --- drivers/gpu/drm/panel/Kconfig | 11 + drivers/gpu/drm/panel/Makefile | 1 + - drivers/gpu/drm/panel/panel-ddic-ch13726a.c | 341 ++++++++++++++++++++ + drivers/gpu/drm/panel/panel-ddic-ch13726a.c | 341 ++++++++++ 3 files changed, 353 insertions(+) - create mode 100644 drivers/gpu/drm/panel/panel-ddic-ch13726a.c diff --git a/drivers/gpu/drm/panel/Kconfig b/drivers/gpu/drm/panel/Kconfig -index 9f49b0189d3b8..c6fcccdcffa07 100644 +index 111111111111..222222222222 100644 --- a/drivers/gpu/drm/panel/Kconfig +++ b/drivers/gpu/drm/panel/Kconfig @@ -87,6 +87,17 @@ config DRM_PANEL_BOE_TV101WUM_NL6 @@ -30,16 +29,16 @@ index 9f49b0189d3b8..c6fcccdcffa07 100644 + Say Y here if you want to enable support for DDIC CH13726A-based + display panels. + - config DRM_PANEL_EBBG_FT8719 - tristate "EBBG FT8719 panel driver" + config DRM_PANEL_BOE_TV101WUM_LL2 + tristate "BOE TV101WUM LL2 1200x1920 panel" depends on OF diff --git a/drivers/gpu/drm/panel/Makefile b/drivers/gpu/drm/panel/Makefile -index 5581387707c62..239a1049fb89e 100644 +index 111111111111..222222222222 100644 --- a/drivers/gpu/drm/panel/Makefile +++ b/drivers/gpu/drm/panel/Makefile -@@ -7,6 +7,7 @@ obj-$(CONFIG_DRM_PANEL_BOE_BF060Y8M_AJ0) += panel-boe-bf060y8m-aj0.o - obj-$(CONFIG_DRM_PANEL_BOE_HIMAX8279D) += panel-boe-himax8279d.o +@@ -8,6 +8,7 @@ obj-$(CONFIG_DRM_PANEL_BOE_HIMAX8279D) += panel-boe-himax8279d.o obj-$(CONFIG_DRM_PANEL_BOE_TH101MB31UIG002_28A) += panel-boe-th101mb31ig002-28a.o + obj-$(CONFIG_DRM_PANEL_BOE_TV101WUM_LL2) += panel-boe-tv101wum-ll2.o obj-$(CONFIG_DRM_PANEL_BOE_TV101WUM_NL6) += panel-boe-tv101wum-nl6.o +obj-$(CONFIG_DRM_PANEL_DDIC_CH13726A) += panel-ddic-ch13726a.o obj-$(CONFIG_DRM_PANEL_DSI_CM) += panel-dsi-cm.o @@ -47,7 +46,7 @@ index 5581387707c62..239a1049fb89e 100644 obj-$(CONFIG_DRM_PANEL_SIMPLE) += panel-simple.o diff --git a/drivers/gpu/drm/panel/panel-ddic-ch13726a.c b/drivers/gpu/drm/panel/panel-ddic-ch13726a.c new file mode 100644 -index 0000000000000..772bb057c44d8 +index 000000000000..111111111111 --- /dev/null +++ b/drivers/gpu/drm/panel/panel-ddic-ch13726a.c @@ -0,0 +1,341 @@ @@ -393,5 +392,5 @@ index 0000000000000..772bb057c44d8 +MODULE_DESCRIPTION("DRM driver for CH13726A DSI panels"); +MODULE_LICENSE("GPL"); -- -2.34.1 +Armbian diff --git a/patch/kernel/archive/sm8250-6.11/0037_leds--Add-driver-for-HEROIC-HTR3212-Signed-off-by-.patch b/patch/kernel/archive/sm8250-6.12/0037-leds-Add-driver-for-HEROIC-HTR3212-Signed-off-by-Teg.patch similarity index 94% rename from patch/kernel/archive/sm8250-6.11/0037_leds--Add-driver-for-HEROIC-HTR3212-Signed-off-by-.patch rename to patch/kernel/archive/sm8250-6.12/0037-leds-Add-driver-for-HEROIC-HTR3212-Signed-off-by-Teg.patch index 6f5553a3b82b..12f4023b6ee9 100644 --- a/patch/kernel/archive/sm8250-6.11/0037_leds--Add-driver-for-HEROIC-HTR3212-Signed-off-by-.patch +++ b/patch/kernel/archive/sm8250-6.12/0037-leds-Add-driver-for-HEROIC-HTR3212-Signed-off-by-Teg.patch @@ -1,18 +1,17 @@ -From 1ab0badb6c453857541e2c3cbe6a2332beca0e11 Mon Sep 17 00:00:00 2001 +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 From: Teguh Sobirin Date: Thu, 21 Nov 2024 00:16:42 +0700 -Subject: [PATCH] leds: Add driver for HEROIC HTR3212 Signed-off-by: Teguh - Sobirin +Subject: leds: Add driver for HEROIC HTR3212 Signed-off-by: Teguh Sobirin + --- - drivers/leds/Kconfig | 10 ++ + drivers/leds/Kconfig | 10 + drivers/leds/Makefile | 1 + - drivers/leds/leds-htr3212.c | 298 ++++++++++++++++++++++++++++++++++++ + drivers/leds/leds-htr3212.c | 298 ++++++++++ 3 files changed, 309 insertions(+) - create mode 100644 drivers/leds/leds-htr3212.c diff --git a/drivers/leds/Kconfig b/drivers/leds/Kconfig -index 8d9d8da376e46..30de92434e3b0 100644 +index 111111111111..222222222222 100644 --- a/drivers/leds/Kconfig +++ b/drivers/leds/Kconfig @@ -211,6 +211,16 @@ config LEDS_EXPRESSWIRE @@ -33,7 +32,7 @@ index 8d9d8da376e46..30de92434e3b0 100644 tristate "LED support for CZ.NIC's Turris Omnia" depends on LEDS_CLASS_MULTICOLOR diff --git a/drivers/leds/Makefile b/drivers/leds/Makefile -index 18afbb5a23ee5..e2277fa7f00dd 100644 +index 111111111111..222222222222 100644 --- a/drivers/leds/Makefile +++ b/drivers/leds/Makefile @@ -32,6 +32,7 @@ obj-$(CONFIG_LEDS_DA9052) += leds-da9052.o @@ -46,7 +45,7 @@ index 18afbb5a23ee5..e2277fa7f00dd 100644 obj-$(CONFIG_LEDS_IPAQ_MICRO) += leds-ipaq-micro.o diff --git a/drivers/leds/leds-htr3212.c b/drivers/leds/leds-htr3212.c new file mode 100644 -index 0000000000000..e9367c4aad04b +index 000000000000..111111111111 --- /dev/null +++ b/drivers/leds/leds-htr3212.c @@ -0,0 +1,298 @@ @@ -349,5 +348,5 @@ index 0000000000000..e9367c4aad04b +MODULE_DESCRIPTION("HEROIC HTR3212 LED Driver"); +MODULE_LICENSE("GPL v2"); -- -2.34.1 +Armbian diff --git a/patch/kernel/archive/sm8250-6.11/0038_Input--driver-for-AYN-Odin2-Gamepad.patch b/patch/kernel/archive/sm8250-6.12/0038-Input-driver-for-AYN-Odin2-Gamepad.patch similarity index 96% rename from patch/kernel/archive/sm8250-6.11/0038_Input--driver-for-AYN-Odin2-Gamepad.patch rename to patch/kernel/archive/sm8250-6.12/0038-Input-driver-for-AYN-Odin2-Gamepad.patch index 8c411610e31c..c839b1e85b0f 100644 --- a/patch/kernel/archive/sm8250-6.11/0038_Input--driver-for-AYN-Odin2-Gamepad.patch +++ b/patch/kernel/archive/sm8250-6.12/0038-Input-driver-for-AYN-Odin2-Gamepad.patch @@ -1,19 +1,18 @@ -From b195a31aa9e0fc606b1e938626ae533c2bcebab1 Mon Sep 17 00:00:00 2001 +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 From: Teguh Sobirin Date: Wed, 20 Nov 2024 23:13:18 +0700 -Subject: [PATCH] Input: driver for AYN Odin2 Gamepad +Subject: Input: driver for AYN Odin2 Gamepad There have been improvements from the original Odin 2 Gamepad driver Signed-off-by: Teguh Sobirin --- drivers/input/joystick/Kconfig | 4 + drivers/input/joystick/Makefile | 1 + - drivers/input/joystick/odin2.c | 313 ++++++++++++++++++++++++++++++++ + drivers/input/joystick/odin2.c | 313 ++++++++++ 3 files changed, 318 insertions(+) - create mode 100644 drivers/input/joystick/odin2.c diff --git a/drivers/input/joystick/Kconfig b/drivers/input/joystick/Kconfig -index 7755e5b454d2c..031b7428068a8 100644 +index 111111111111..222222222222 100644 --- a/drivers/input/joystick/Kconfig +++ b/drivers/input/joystick/Kconfig @@ -344,6 +344,10 @@ config JOYSTICK_MAPLE @@ -28,7 +27,7 @@ index 7755e5b454d2c..031b7428068a8 100644 tristate "PlayStation 1/2 joypads via SPI interface" depends on SPI diff --git a/drivers/input/joystick/Makefile b/drivers/input/joystick/Makefile -index 9976f596a9208..ba7d72514c8b9 100644 +index 111111111111..222222222222 100644 --- a/drivers/input/joystick/Makefile +++ b/drivers/input/joystick/Makefile @@ -25,6 +25,7 @@ obj-$(CONFIG_JOYSTICK_JOYDUMP) += joydump.o @@ -41,7 +40,7 @@ index 9976f596a9208..ba7d72514c8b9 100644 obj-$(CONFIG_JOYSTICK_QWIIC) += qwiic-joystick.o diff --git a/drivers/input/joystick/odin2.c b/drivers/input/joystick/odin2.c new file mode 100644 -index 0000000000000..63a32175b4415 +index 000000000000..111111111111 --- /dev/null +++ b/drivers/input/joystick/odin2.c @@ -0,0 +1,313 @@ @@ -359,5 +358,5 @@ index 0000000000000..63a32175b4415 +MODULE_AUTHOR("Teguh Sobirin "); +MODULE_ALIAS("platform:" DRIVER_NAME); -- -2.34.1 +Armbian diff --git a/patch/kernel/archive/sm8250-6.11/0039_input--add-Qualcomm-SPMI-haptics-driver.patch b/patch/kernel/archive/sm8250-6.12/0039-input-add-Qualcomm-SPMI-haptics-driver.patch similarity index 98% rename from patch/kernel/archive/sm8250-6.11/0039_input--add-Qualcomm-SPMI-haptics-driver.patch rename to patch/kernel/archive/sm8250-6.12/0039-input-add-Qualcomm-SPMI-haptics-driver.patch index c701a2040085..2437d2d0979e 100644 --- a/patch/kernel/archive/sm8250-6.11/0039_input--add-Qualcomm-SPMI-haptics-driver.patch +++ b/patch/kernel/archive/sm8250-6.12/0039-input-add-Qualcomm-SPMI-haptics-driver.patch @@ -1,7 +1,7 @@ -From 484a974e62ed69f1bb8b564f719613623e5eb3c6 Mon Sep 17 00:00:00 2001 +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 From: Teguh Sobirin Date: Mon, 25 Nov 2024 02:27:16 +0700 -Subject: [PATCH] input: add Qualcomm SPMI haptics driver +Subject: input: add Qualcomm SPMI haptics driver Add support for the haptics found in pmi8998 and related PMICs. Based on the ff-memless interface. Currently this driver provides @@ -13,14 +13,12 @@ Signed-off-by: Teguh Sobirin --- drivers/input/misc/Kconfig | 12 + drivers/input/misc/Makefile | 1 + - drivers/input/misc/qcom-spmi-haptics.c | 990 ++++++++++++++++++ + drivers/input/misc/qcom-spmi-haptics.c | 990 ++++++++++ include/dt-bindings/input/qcom,spmi-haptics.h | 31 + 4 files changed, 1034 insertions(+) - create mode 100644 drivers/input/misc/qcom-spmi-haptics.c - create mode 100644 include/dt-bindings/input/qcom,spmi-haptics.h diff --git a/drivers/input/misc/Kconfig b/drivers/input/misc/Kconfig -index 6a852c76331b6..df77c0fdc93e7 100644 +index 111111111111..222222222222 100644 --- a/drivers/input/misc/Kconfig +++ b/drivers/input/misc/Kconfig @@ -214,6 +214,18 @@ config INPUT_PMIC8XXX_PWRKEY @@ -43,7 +41,7 @@ index 6a852c76331b6..df77c0fdc93e7 100644 tristate "SPARC Speaker support" depends on PCI && SPARC64 diff --git a/drivers/input/misc/Makefile b/drivers/input/misc/Makefile -index 4f7f736831ba8..0a3fb90f366fe 100644 +index 111111111111..222222222222 100644 --- a/drivers/input/misc/Makefile +++ b/drivers/input/misc/Makefile @@ -41,6 +41,7 @@ obj-$(CONFIG_INPUT_DRV2667_HAPTICS) += drv2667.o @@ -56,7 +54,7 @@ index 4f7f736831ba8..0a3fb90f366fe 100644 obj-$(CONFIG_INPUT_IBM_PANEL) += ibm-panel.o diff --git a/drivers/input/misc/qcom-spmi-haptics.c b/drivers/input/misc/qcom-spmi-haptics.c new file mode 100644 -index 0000000000000..64ef78ec18218 +index 000000000000..111111111111 --- /dev/null +++ b/drivers/input/misc/qcom-spmi-haptics.c @@ -0,0 +1,990 @@ @@ -1052,7 +1050,7 @@ index 0000000000000..64ef78ec18218 +MODULE_AUTHOR("Caleb Connolly "); diff --git a/include/dt-bindings/input/qcom,spmi-haptics.h b/include/dt-bindings/input/qcom,spmi-haptics.h new file mode 100644 -index 0000000000000..c25c004807015 +index 000000000000..111111111111 --- /dev/null +++ b/include/dt-bindings/input/qcom,spmi-haptics.h @@ -0,0 +1,31 @@ @@ -1088,5 +1086,5 @@ index 0000000000000..c25c004807015 + +#endif /* _DT_BINDINGS_QCOM_PMIC_SPMI_HAPTICS_ */ -- -2.34.1 +Armbian diff --git a/patch/kernel/archive/sm8250-6.11/0040_arm64--dts--qcom--pm8150b--introduce-spmi-haptics.patch b/patch/kernel/archive/sm8250-6.12/0040-arm64-dts-qcom-pm8150b-introduce-spmi-haptics.patch similarity index 82% rename from patch/kernel/archive/sm8250-6.11/0040_arm64--dts--qcom--pm8150b--introduce-spmi-haptics.patch rename to patch/kernel/archive/sm8250-6.12/0040-arm64-dts-qcom-pm8150b-introduce-spmi-haptics.patch index a68a2757c292..e58dcbf12dc3 100644 --- a/patch/kernel/archive/sm8250-6.11/0040_arm64--dts--qcom--pm8150b--introduce-spmi-haptics.patch +++ b/patch/kernel/archive/sm8250-6.12/0040-arm64-dts-qcom-pm8150b-introduce-spmi-haptics.patch @@ -1,16 +1,16 @@ -From 67c96945a031cda1c5aa331f016d4e83b4557910 Mon Sep 17 00:00:00 2001 +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 From: Teguh Sobirin Date: Mon, 25 Nov 2024 02:17:47 +0700 -Subject: [PATCH] arm64: dts: qcom: pm8150b: introduce spmi haptics +Subject: arm64: dts: qcom: pm8150b: introduce spmi haptics Add bindings for Qualcomm SPMI haptics on platforms using pm8150b. Signed-off-by: Teguh Sobirin --- - arch/arm64/boot/dts/qcom/pm8150b.dtsi | 16 ++++++++++++++++ + arch/arm64/boot/dts/qcom/pm8150b.dtsi | 16 ++++++++++ 1 file changed, 16 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/pm8150b.dtsi b/arch/arm64/boot/dts/qcom/pm8150b.dtsi -index 42ef21238f18b..efad258834df9 100644 +index 111111111111..222222222222 100644 --- a/arch/arm64/boot/dts/qcom/pm8150b.dtsi +++ b/arch/arm64/boot/dts/qcom/pm8150b.dtsi @@ -5,6 +5,7 @@ @@ -43,5 +43,5 @@ index 42ef21238f18b..efad258834df9 100644 }; }; -- -2.34.1 +Armbian diff --git a/patch/kernel/archive/sm8250-6.11/0041_arm64--dts--qcom--add-SM8250-Retroid-Pocket-varian.patch b/patch/kernel/archive/sm8250-6.12/0041-arm64-dts-qcom-add-SM8250-Retroid-Pocket-variant-Sig.patch similarity index 97% rename from patch/kernel/archive/sm8250-6.11/0041_arm64--dts--qcom--add-SM8250-Retroid-Pocket-varian.patch rename to patch/kernel/archive/sm8250-6.12/0041-arm64-dts-qcom-add-SM8250-Retroid-Pocket-variant-Sig.patch index 7ea59bbfbb4d..df0ac4ceb2ce 100644 --- a/patch/kernel/archive/sm8250-6.11/0041_arm64--dts--qcom--add-SM8250-Retroid-Pocket-varian.patch +++ b/patch/kernel/archive/sm8250-6.12/0041-arm64-dts-qcom-add-SM8250-Retroid-Pocket-variant-Sig.patch @@ -1,24 +1,21 @@ -From e1159a967783255e9f68f7bd449e12b5f2767b28 Mon Sep 17 00:00:00 2001 +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 From: Teguh Sobirin Date: Mon, 25 Nov 2024 02:19:13 +0700 -Subject: [PATCH] arm64: dts: qcom: add SM8250 Retroid Pocket variant - Signed-off-by: Teguh Sobirin +Subject: arm64: dts: qcom: add SM8250 Retroid Pocket variant Signed-off-by: + Teguh Sobirin --- - arch/arm64/boot/dts/qcom/Makefile | 2 + - .../dts/qcom/sm8250-retroidpocket-common.dtsi | 1435 +++++++++++++++++ - .../dts/qcom/sm8250-retroidpocket-rp5.dts | 100 ++ - .../dts/qcom/sm8250-retroidpocket-rpmini.dts | 98 ++ + arch/arm64/boot/dts/qcom/Makefile | 2 + + arch/arm64/boot/dts/qcom/sm8250-retroidpocket-common.dtsi | 1435 ++++++++++ + arch/arm64/boot/dts/qcom/sm8250-retroidpocket-rp5.dts | 100 + + arch/arm64/boot/dts/qcom/sm8250-retroidpocket-rpmini.dts | 98 + 4 files changed, 1635 insertions(+) - create mode 100644 arch/arm64/boot/dts/qcom/sm8250-retroidpocket-common.dtsi - create mode 100644 arch/arm64/boot/dts/qcom/sm8250-retroidpocket-rp5.dts - create mode 100644 arch/arm64/boot/dts/qcom/sm8250-retroidpocket-rpmini.dts diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile -index 0e5c810304fbe..aecec23e2eaae 100644 +index 111111111111..222222222222 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile -@@ -237,6 +237,8 @@ dtb-$(CONFIG_ARCH_QCOM) += sm8250-hdk.dtb +@@ -244,6 +244,8 @@ dtb-$(CONFIG_ARCH_QCOM) += sm8250-hdk.dtb dtb-$(CONFIG_ARCH_QCOM) += sm8250-mtp.dtb dtb-$(CONFIG_ARCH_QCOM) += sm8250-oneplus-instantnoodlep.dtb dtb-$(CONFIG_ARCH_QCOM) += sm8250-oneplus-kebab.dtb @@ -29,7 +26,7 @@ index 0e5c810304fbe..aecec23e2eaae 100644 dtb-$(CONFIG_ARCH_QCOM) += sm8250-xiaomi-elish-boe.dtb diff --git a/arch/arm64/boot/dts/qcom/sm8250-retroidpocket-common.dtsi b/arch/arm64/boot/dts/qcom/sm8250-retroidpocket-common.dtsi new file mode 100644 -index 0000000000000..58ca9d330a152 +index 000000000000..111111111111 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sm8250-retroidpocket-common.dtsi @@ -0,0 +1,1435 @@ @@ -1470,7 +1467,7 @@ index 0000000000000..58ca9d330a152 +}; diff --git a/arch/arm64/boot/dts/qcom/sm8250-retroidpocket-rp5.dts b/arch/arm64/boot/dts/qcom/sm8250-retroidpocket-rp5.dts new file mode 100644 -index 0000000000000..a059378fcbea7 +index 000000000000..111111111111 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sm8250-retroidpocket-rp5.dts @@ -0,0 +1,100 @@ @@ -1576,7 +1573,7 @@ index 0000000000000..a059378fcbea7 +}; diff --git a/arch/arm64/boot/dts/qcom/sm8250-retroidpocket-rpmini.dts b/arch/arm64/boot/dts/qcom/sm8250-retroidpocket-rpmini.dts new file mode 100644 -index 0000000000000..9f572e87b84e7 +index 000000000000..111111111111 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sm8250-retroidpocket-rpmini.dts @@ -0,0 +1,98 @@ @@ -1679,5 +1676,5 @@ index 0000000000000..9f572e87b84e7 + }; +}; -- -2.34.1 +Armbian diff --git a/patch/kernel/archive/sm8250-6.12/0042-tools-disable-sched_ext_clean.patch b/patch/kernel/archive/sm8250-6.12/0042-tools-disable-sched_ext_clean.patch new file mode 100644 index 000000000000..2ce2dae21120 --- /dev/null +++ b/patch/kernel/archive/sm8250-6.12/0042-tools-disable-sched_ext_clean.patch @@ -0,0 +1,25 @@ +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: amazingfate +Date: Wed, 6 Nov 2024 19:57:53 +0800 +Subject: tools: disable sched_ext_clean + +--- + tools/Makefile | 3 +-- + 1 file changed, 1 insertion(+), 2 deletions(-) + +diff --git a/tools/Makefile b/tools/Makefile +index 111111111111..222222222222 100644 +--- a/tools/Makefile ++++ b/tools/Makefile +@@ -220,7 +220,6 @@ clean: acpi_clean counter_clean cpupower_clean hv_clean firewire_clean \ + mm_clean bpf_clean iio_clean x86_energy_perf_policy_clean tmon_clean \ + freefall_clean build_clean libbpf_clean libsubcmd_clean \ + gpio_clean objtool_clean leds_clean wmi_clean pci_clean firmware_clean debugging_clean \ +- intel-speed-select_clean tracing_clean thermal_clean thermometer_clean thermal-engine_clean \ +- sched_ext_clean ++ intel-speed-select_clean tracing_clean thermal_clean thermometer_clean thermal-engine_clean + + .PHONY: FORCE +-- +Armbian + From 523be17a78916ee6e55aa99c23c7b1d5155ba73b Mon Sep 17 00:00:00 2001 From: igorpecovnik <6281704+igorpecovnik@users.noreply.github.com> Date: Wed, 4 Dec 2024 23:07:09 +0000 Subject: [PATCH 017/120] `Automatic` board configs status synchronise --- .github/CODEOWNERS | 1 + config/boards/coolpi-genbook.csc | 2 +- 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/.github/CODEOWNERS b/.github/CODEOWNERS index 57d0667cc5b2..d8e0870087c8 100644 --- a/.github/CODEOWNERS +++ b/.github/CODEOWNERS @@ -38,6 +38,7 @@ config/boards/cherryba-m1.csc @IsMrX config/boards/clearfogpro.csc @Heisath config/boards/cm3588-nas.csc @ColorfulRhino config/boards/coolpi-cm5.csc @andyshrk +config/boards/coolpi-genbook.csc @andyshrk config/boards/firefly-itx-3588j.csc @SeeleVolleri config/boards/fxblox-rk1.csc @mahdichi config/boards/gateway-gz80x.conf @pyavitz diff --git a/config/boards/coolpi-genbook.csc b/config/boards/coolpi-genbook.csc index a274fe512b7e..3188591875a5 100644 --- a/config/boards/coolpi-genbook.csc +++ b/config/boards/coolpi-genbook.csc @@ -1,7 +1,7 @@ # Rockchip RK3588 SoC octa core 4-16GB SoC eMMC USB3 NVME BOARD_NAME="CoolPi GenBook" BOARDFAMILY="rockchip-rk3588" -BOARD_MAINTAINER="Andyshrk" +BOARD_MAINTAINER="andyshrk" BOARD_FIRMWARE_INSTALL="-full" BOOT_SOC="rk3588" BOOTCONFIG="coolpi-cm5-genbook-rk3588_defconfig" From 3a7ba30f3fbcee87e6fc73331e7aa4a983e2c845 Mon Sep 17 00:00:00 2001 From: JohnTheCoolingFan Date: Wed, 4 Dec 2024 13:46:27 +0300 Subject: [PATCH 018/120] add board `bigtreetech-cb2`: BigTreeTech CB2 --- config/boards/bigtreetech-cb2.csc | 48 + .../dt/rk3566-bigtreetech-cb2.dts | 1036 +++++++++++++++++ .../bigtreetech-cb2-dts-and-defconfig.patch | 645 ++++++++++ 3 files changed, 1729 insertions(+) create mode 100644 config/boards/bigtreetech-cb2.csc create mode 100644 patch/kernel/archive/rockchip64-6.6/dt/rk3566-bigtreetech-cb2.dts create mode 100644 patch/u-boot/v2024.10/board_bigtreetech-cb2/bigtreetech-cb2-dts-and-defconfig.patch diff --git a/config/boards/bigtreetech-cb2.csc b/config/boards/bigtreetech-cb2.csc new file mode 100644 index 000000000000..9ee8f98fd858 --- /dev/null +++ b/config/boards/bigtreetech-cb2.csc @@ -0,0 +1,48 @@ +# Rockchip RK3566 quad core 2GB-8GB GBE eMMC NVMe USB3 WiFi +BOARD_NAME="BigTreeTech CB2" +BOARDFAMILY="rockchip64" +BOARD_MAINTAINER="" +BOOTCONFIG="bigtreetech-cb2-rk3566_defconfig" +BOOT_SOC="rk3566" +KERNEL_TARGET="current,edge" +KERNEL_TEST_TARGET="current" +BOOT_FDT_FILE="rockchip/rk3566-bigtreetech-cb2.dtb" +IMAGE_PARTITION_TABLE="gpt" +BOOT_SCENARIO="spl-blobs" +OVERLAY_PREFIX='rk3566' +FULL_DESKTOP="yes" +BOOT_LOGO="desktop" + +# TODO: replace with BOOT_SCENARIO=binman when it gets merged and in good shape +function post_family_config__bigtreetech-cb2_uboot_overrides() { + display_alert "$BOARD" "mainline u-boot overrides" "info" + + DDR_BLOB="rk35/rk3566_ddr_1056MHz_v1.21.bin" + BL31_BLOB="rk35/rk3568_bl31_v1.44.elf" # NOT a typo, bl31 is shared across 68 and 66 + + declare -g BOOTDELAY=1 # Wait for UART interrupt to enter UMS/RockUSB mode etc + declare -g BOOTSOURCE="https://github.com/u-boot/u-boot.git" + declare -g BOOTBRANCH="tag:v2024.10" + declare -g BOOTPATCHDIR="v2024.10/board_bigtreetech-cb2" + #declare -g BOOTDIR="u-boot-${BOARD}" + declare -g UBOOT_TARGET_MAP="BL31=${RKBIN_DIR}/${BL31_BLOB} ROCKCHIP_TPL=${RKBIN_DIR}/${DDR_BLOB};;u-boot-rockchip.bin" + unset uboot_custom_postprocess write_uboot_platform write_uboot_platform_mtd # disable stuff from rockchip64_common; we're using binman here which does all the work already + + # Just use the binman-provided u-boot-rockchip.bin, which is ready-to-go + function write_uboot_platform() { + dd "if=${1}/u-boot-rockchip.bin" "of=${2}" bs=32k seek=1 conv=notrunc + } + + function write_uboot_platform_mtd() { + declare -a extra_opts_flashcp=("--verbose") + if flashcp -h | grep -q -e '--partition'; then + echo "Confirmed flashcp supports --partition -- read and write only changed blocks." >&2 + extra_opts_flashcp+=("--partition") + else + echo "flashcp does not support --partition, will write full SPI flash blocks." >&2 + fi + flashcp "${extra_opts_flashcp[@]}" "${1}/u-boot-rockchip-spi.bin" /dev/mtd0 + } +} + +# vim: ft=bash diff --git a/patch/kernel/archive/rockchip64-6.6/dt/rk3566-bigtreetech-cb2.dts b/patch/kernel/archive/rockchip64-6.6/dt/rk3566-bigtreetech-cb2.dts new file mode 100644 index 000000000000..0a2338f6ec42 --- /dev/null +++ b/patch/kernel/archive/rockchip64-6.6/dt/rk3566-bigtreetech-cb2.dts @@ -0,0 +1,1036 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2020 Rockchip Electronics Co., Ltd. + * + */ +/dts-v1/; + +#include +#include +#include +#include +#include "rk3566.dtsi" + +/ { + model = "Rockchip RK3566 OPi 3B"; + compatible = "rockchip,rk3566-orangepi-3b", "rockchip,rk3566"; + + aliases { + ethernet0 = &gmac1; + mmc0 = &sdhci; + mmc1 = &sdmmc0; + }; + + chosen: chosen { + stdout-path = "serial2:1500000n8"; + }; + + fan: pwm-fan { + compatible = "pwm-fan"; + #cooling-cells = <2>; + pwms = <&pwm7 0 50000 0>; + cooling-levels = <0 50 100 150 200 255>; + rockchip,temp-trips = < + 50000 1 + 55000 2 + 60000 3 + 65000 4 + 70000 5 + >; + }; + + hdmi-con { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_con_in: endpoint { + remote-endpoint = <&hdmi_out_con>; + }; + }; + }; + + leds: leds { + compatible = "gpio-leds"; + + led@0 { + gpios = <&gpio4 RK_PA1 GPIO_ACTIVE_HIGH>; + label = "power_led"; + linux,default-trigger = "default-on"; + pinctrl-names = "default"; + pinctrl-0 =<&blue_led>; + }; + + led@1 { + gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>; + label = "status_led"; + linux,default-trigger = "heartbeat"; + pinctrl-names = "default"; + pinctrl-0 =<&leds_gpio>; + }; + }; + + rk809-sound { + compatible = "simple-audio-card"; + simple-audio-card,format = "i2s"; + simple-audio-card,name = "Analog RK809"; + simple-audio-card,mclk-fs = <256>; + + simple-audio-card,cpu { + sound-dai = <&i2s1_8ch>; + }; + + simple-audio-card,codec { + sound-dai = <&rk809>; + }; + }; + + sdio_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + clocks = <&rk809 1>; + clock-names = "ext_clock"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_enable_h>; + + /* + * On the module itself this is one of these (depending + * on the actual card populated): + * - SDIO_RESET_L_WL_REG_ON + * - PDN (power down when low) + */ + post-power-on-delay-ms = <200>; + reset-gpios = <&gpio0 RK_PD3 GPIO_ACTIVE_LOW>; + }; + + /* labeled +12v in schematic */ + vcc12v_dcin: vcc12v-dcin-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc12v_dcin"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + }; + + /* labeled +5v in schematic */ + vcc_5v: vcc-5v-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc_5v"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc12v_dcin>; + }; + + vbus: vbus { + compatible = "regulator-fixed"; + regulator-name = "vbus"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + /* labeled +3.3v For PCIe only in schematic */ + vcc3v3_pcie: vcc3v3-pcie-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_pcie"; + regulator-always-on; + regulator-boot-on; + enable-active-high; + gpio = <&gpio0 RK_PB1 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pcie_drv>; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc12v_dcin>; + }; + + vcc3v3_sys: vcc3v3-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vbus>; + }; + + vcc5v0_sys: vcc5v0-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vbus>; + }; + + vcc5v0_usb: vcc5v0-usb { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_usb"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vbus>; + }; + + vcc_sd: vcc-sd { + compatible = "regulator-fixed"; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "vcc_sd"; + vin-supply = <&vcc3v3_sys>; + }; + + vcc5v0_host: vcc5v0-host-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio0 RK_PB6 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc5v0_host_en>; + regulator-name = "vcc5v0_host3"; + regulator-always-on; + }; + + vcc5v0_otg: vcc5v0-otg-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio0 RK_PB5 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc5v0_otg_en>; + regulator-name = "vcc5v0_otg3"; + regulator-always-on; + }; + + vcc5v0_usb2t: vcc5v0-usb2t-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio0 RK_PD5 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc5v0_usb2t_en>; + regulator-name = "vcc5v0_usb2t"; + regulator-always-on; + }; + + vcc5v0_usb2b: vcc5v0-usb2b-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio0 RK_PC4 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc5v0_usb2b_en>; + regulator-name = "vcc5v0_usb2b"; + regulator-always-on; + }; + + ext_cam_clk: ext-cam-clk { + status = "okay"; + compatible = "fixed-clock"; + clock-frequency = <25000000>; + clock-output-names = "ext_cam_clk"; + #clock-cells = <0>; + }; + + can_mcp2515_osc: can-mcp2515-osc { + compatible = "fixed-clock"; + clock-frequency = <8000000>; + #clock-cells = <0>; + }; +}; + +&combphy1 { + status = "okay"; +}; + +&combphy2 { + status = "okay"; +}; + +&cpu0 { + cpu-supply = <&vdd_cpu>; +}; + +&cpu1 { + cpu-supply = <&vdd_cpu>; +}; + +&cpu2 { + cpu-supply = <&vdd_cpu>; +}; + +&cpu3 { + cpu-supply = <&vdd_cpu>; +}; + +&gmac1 { + assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>; + assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>, <&cru CLK_MAC1_2TOP>; + assigned-clock-rates = <0>, <125000000>; + clock_in_out = "input"; + phy-mode = "rgmii"; + pinctrl-names = "default"; + pinctrl-0 = <&gmac1m0_miim + &gmac1m0_tx_bus2 + &gmac1m0_rx_bus2 + &gmac1m0_rgmii_clk + &gmac1m0_clkinout + &gmac1m0_rgmii_bus>; + + snps,reset-gpio = <&gpio0 RK_PC5 GPIO_ACTIVE_LOW>; + snps,reset-active-low; + reset-gpios = <&gpio1 RK_PB2 GPIO_ACTIVE_HIGH>; + /* Reset time is 20ms, 100ms for rtl8211f */ + //snps,reset-delays-us = <0 20000 100000>; + snps,reset-delays-us = <0 50000 200000>; + tx_delay = <0x30>; + rx_delay = <0x10>; + phy-handle = <&rgmii_phy0>; + status = "okay"; +}; + +&gpu { + mali-supply = <&vdd_gpu>; + status = "okay"; +}; + +&hdmi { + avdd-0v9-supply = <&vdda0v9_image>; + avdd-1v8-supply = <&vcca1v8_image>; + status = "okay"; +}; + +&hdmi_in { + hdmi_in_vp0: endpoint { + remote-endpoint = <&vp0_out_hdmi>; + }; +}; + +&hdmi_out { + hdmi_out_con: endpoint { + remote-endpoint = <&hdmi_con_in>; + }; +}; + +&hdmi_sound { + status = "okay"; +}; + +&i2c0 { + status = "okay"; + + vdd_cpu: tsc4525@1c { + compatible = "tcs,tcs4525"; + reg = <0x1c>; + vin-supply = <&vcc5v0_sys>; + regulator-compatible = "fan53555-reg"; + regulator-name = "vdd_cpu"; + regulator-min-microvolt = <712500>; + regulator-max-microvolt = <1390000>; + regulator-init-microvolt = <900000>; + regulator-initial-mode = <1>; + regulator-ramp-delay = <2300>; + fcs,suspend-voltage-selector = <1>; + regulator-boot-on; + regulator-always-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + rk809: pmic@20 { + compatible = "rockchip,rk809"; + reg = <0x20>; + interrupt-parent = <&gpio0>; + interrupts = <3 IRQ_TYPE_LEVEL_LOW>; + + assigned-clocks = <&cru I2S1_MCLKOUT_TX>; + assigned-clock-parents = <&cru CLK_I2S1_8CH_TX>; + #clock-cells = <1>; + clock-names = "mclk"; + clocks = <&cru I2S1_MCLKOUT_TX>; + pinctrl-names = "default", "pmic-sleep", + "pmic-power-off", "pmic-reset"; + pinctrl-0 = <&pmic_int>, <&i2s1m0_mclk>; + pinctrl-1 = <&soc_slppin_slp>, <&rk817_slppin_slp>; + pinctrl-2 = <&soc_slppin_gpio>, <&rk817_slppin_pwrdn>; + pinctrl-3 = <&soc_slppin_gpio>, <&rk817_slppin_rst>; + #sound-dai-cells = <0>; + + rockchip,system-power-controller; + wakeup-source; + + vcc1-supply = <&vcc3v3_sys>; + vcc2-supply = <&vcc3v3_sys>; + vcc3-supply = <&vcc3v3_sys>; + vcc4-supply = <&vcc3v3_sys>; + vcc5-supply = <&vcc3v3_sys>; + vcc6-supply = <&vcc3v3_sys>; + vcc7-supply = <&vcc3v3_sys>; + vcc8-supply = <&vcc3v3_sys>; + vcc9-supply = <&vcc3v3_sys>; + + pinctrl_rk8xx: pinctrl_rk8xx { + gpio-controller; + #gpio-cells = <2>; + + rk817_slppin_null: rk817_slppin_null { + pins = "gpio_slp"; + function = "pin_fun0"; + }; + + rk817_slppin_slp: rk817_slppin_slp { + pins = "gpio_slp"; + function = "pin_fun1"; + }; + + rk817_slppin_pwrdn: rk817_slppin_pwrdn { + pins = "gpio_slp"; + function = "pin_fun2"; + }; + + rk817_slppin_rst: rk817_slppin_rst { + pins = "gpio_slp"; + function = "pin_fun3"; + }; + }; + + regulators { + vdd_logic: DCDC_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1350000>; + regulator-init-microvolt = <900000>; + regulator-ramp-delay = <6001>; + regulator-initial-mode = <0x2>; + regulator-name = "vdd_logic"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_gpu: DCDC_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1350000>; + regulator-init-microvolt = <900000>; + regulator-ramp-delay = <6001>; + regulator-initial-mode = <0x2>; + regulator-name = "vdd_gpu"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_ddr: DCDC_REG3 { + regulator-always-on; + regulator-boot-on; + regulator-initial-mode = <0x2>; + regulator-name = "vcc_ddr"; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vdd_npu: DCDC_REG4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1350000>; + regulator-init-microvolt = <900000>; + regulator-ramp-delay = <6001>; + regulator-initial-mode = <0x2>; + regulator-name = "vdd_npu"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda0v9_image: LDO_REG1 { + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + regulator-name = "vdda0v9_image"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda_0v9: LDO_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + regulator-name = "vdda_0v9"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda0v9_pmu: LDO_REG3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + regulator-name = "vdda0v9_pmu"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <900000>; + }; + }; + + vccio_acodec: LDO_REG4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-name = "vccio_acodec"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vccio_sd: LDO_REG5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vccio_sd"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc3v3_pmu: LDO_REG6 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc3v3_pmu"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vcca_1v8: LDO_REG7 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcca_1v8"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcca1v8_pmu: LDO_REG8 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcca1v8_pmu"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vcca1v8_image: LDO_REG9 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcca1v8_image"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v8: DCDC_REG5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc_1v8"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_3v3: SWITCH_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vcc_3v3"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc3v3_sd: SWITCH_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vcc3v3_sd"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; + + codec { + mic-in-differential; + }; + }; +}; + +&i2c2 { + pinctrl-0 = <&i2c2m1_xfer>; +}; + +/* + * i2c3_m0 is exposed on the 40-pin (green connectors) + * pin 27 - i2c3_sda_m0 + * pin 28 - i2c3_scl_m0 + */ +&i2c3 { + status = "okay"; + + tft_tp: ns2009@48 { + compatible = "ti,tsc2007"; + reg = <0x48>; + status = "okay"; + ti,x-plate-ohms = <660>; + ti,rt-thr = <3000>; + ti,fuzzx = <32>; + ti,fuzzy = <16>; + i2c,ignore-nak = <1>; + }; +}; + +&i2s0_8ch { + status = "okay"; +}; + +&i2s1_8ch { + pinctrl-names = "default"; + pinctrl-0 = <&i2s1m0_sclktx + &i2s1m0_lrcktx + &i2s1m0_sdi0 + &i2s1m0_sdo0>; + rockchip,trcm-sync-tx-only; + status = "okay"; +}; + +&spi1 { + pinctrl-0 = <&spi1m1_cs0 &spi1m1_pins>; + + can_mcp2515: can-mcp2515@0 { + status = "disabled"; + compatible = "microchip,mcp2515"; + reg = <0x00>; + interrupt-parent = <&gpio4>; + interrupts = <3 IRQ_TYPE_LEVEL_LOW>; + spi-max-frequency = <10000000>; + clocks = <&can_mcp2515_osc>; + vdd-supply = <&vcc3v3_sys>; + xceiver-supply = <&vcc3v3_sys>; + pinctrl-names = "default"; + pinctrl-0 = <&mcp2515_int_pin>; + }; + + /* + tft_35: st7789v@1 { + status = "disabled"; + compatible = "sitronix,st7796s"; + reg = <0x01>; + spi-max-frequency = <12500000>; + fps = <60>; + buswidth = <8>; + rotate = <0>; + width = <480>; + height = <320>; + bpp = <24>; + bgr; + regwidth = <8>; + debug = <0>; + txbuflen = <0x2000>; + spi-cpol; + spi-cpha; + dc-gpios = <&gpio0 RK_C7 GPIO_ACTIVE_HIGH>; + }; + */ +}; + +&spi3 { + pinctrl-0 = <&spi3m1_cs0 &spi3m1_pins>; +}; + +&mdio1 { + rgmii_phy0: phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0x0>; + }; +}; + +&pcie2x1 { + reset-gpios = <&gpio0 RK_PB6 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc3v3_pcie>; + status = "okay"; +}; + +&pinctrl { + wireless-bluetooth { + uart1_gpios: uart1-gpios { + rockchip,pins = <2 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + sd { + sdmmc0_pwr_h: sdmmc0-pwr-h { + rockchip,pins = + <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + mxc6655xa { + mxc6655xa_irq_gpio: mxc6655xa_irq_gpio { + rockchip,pins = <3 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + pmic { + pmic_int: pmic_int { + rockchip,pins = + <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + soc_slppin_gpio: soc_slppin_gpio { + rockchip,pins = + <0 RK_PA2 RK_FUNC_GPIO &pcfg_output_low>; + }; + + soc_slppin_slp: soc_slppin_slp { + rockchip,pins = + <0 RK_PA2 1 &pcfg_pull_none>; + }; + + soc_slppin_rst: soc_slppin_rst { + rockchip,pins = + <0 RK_PA2 2 &pcfg_pull_none>; + }; + }; + + touch { + touch_gpio: touch-gpio { + rockchip,pins = + <0 RK_PB5 RK_FUNC_GPIO &pcfg_pull_up>, + <0 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + sdio-pwrseq { + wifi_enable_h: wifi-enable-h { + rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + wifi_host_wake: wifi-host-wake-l { + rockchip,pins = <2 RK_PB1 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; + + usb { + vcc5v0_host_en: vcc5v0-host-en { + rockchip,pins = <0 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + vcc5v0_otg_en: vcc5v0-otg-en { + rockchip,pins = <0 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + vcc5v0_usb2t_en: vcc5v0_usb2t-en { + rockchip,pins = <3 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + vcc5v0_usb2b_en: vcc5v0-usb2b-en { + rockchip,pins = <4 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + work-led { + leds_gpio: leds-gpio { + rockchip,pins = <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + blue_led: led-blue { + rockchip,pins = <4 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + headphone { + hp_det: hp-det { + rockchip,pins = <0 RK_PC4 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; + + pcie { + pcie_drv: pcie-drv { + rockchip,pins = <4 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + edp { + edp_hpd: edp-hpd { + rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + bl_en: bl-en { + rockchip,pins = <0 RK_PB5 RK_FUNC_GPIO &pcfg_output_high>; + }; + }; + + bt { + bt_enable: bt-enable-h { + rockchip,pins = <2 RK_PB7 RK_FUNC_GPIO &pcfg_pull_down>; + }; + + bt_host_wake: bt-host-wake-l { + rockchip,pins = <2 RK_PC1 RK_FUNC_GPIO &pcfg_pull_down>; + }; + + bt_wake: bt-wake-l { + rockchip,pins = <2 RK_PC0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + mcp2515_int_pin { + mcp2515_int_pin: mcp2515_in_pin { + rockchip,pins = <4 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; +}; + + /* + * There are 10 independent IO domains in RK3566/RK3568, including PMUIO[0:2] and VCCIO[1:7]. + * 1/ PMUIO0 and PMUIO1 are fixed-level power domains which cannot be configured; + * 2/ PMUIO2 and VCCIO1,VCCIO[3:7] domains require that their hardware power supply voltages + * must be consistent with the software configuration correspondingly + * a/ When the hardware IO level is connected to 1.8V, the software voltage configuration + * should also be configured to 1.8V accordingly; + * b/ When the hardware IO level is connected to 3.3V, the software voltage configuration + * should also be configured to 3.3V accordingly; + * 3/ VCCIO2 voltage control selection (0xFDC20140) + * BIT[0]: 0x0: from GPIO_0A7 (default) + * BIT[0]: 0x1: from GRF + * Default is determined by Pin FLASH_VOL_SEL/GPIO0_A7: + * L:VCCIO2 must supply 3.3V + * H:VCCIO2 must supply 1.8V + */ + +&pmu_io_domains { + status = "okay"; + pmuio1-supply = <&vcc3v3_pmu>; + pmuio2-supply = <&vcc3v3_pmu>; + vccio1-supply = <&vcc_3v3>; + vccio2-supply = <&vcc_1v8>; + vccio3-supply = <&vccio_sd>; + vccio4-supply = <&vcc_1v8>; + vccio5-supply = <&vcc_3v3>; + vccio6-supply = <&vcc_3v3>; + vccio7-supply = <&vcc_3v3>; +}; + +&pwm0 { + pinctrl-0 = <&pwm0m1_pins>; +}; + +&pwm7 { + status = "disabled"; +}; + +&pwm12 { + pinctrl-0 = <&pwm12m1_pins>; +}; + +&pwm13 { + pinctrl-0 = <&pwm13m1_pins>; +}; + +&pwm14 { + pinctrl-0 = <&pwm14m1_pins>; +}; + +&pwm15 { + pinctrl-0 = <&pwm15m1_pins>; +}; + +&saradc { + status = "okay"; + vref-supply = <&vcca_1v8>; +}; + +&sdhci { + bus-width = <8>; + max-frequency = <200000000>; + non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd>; + status = "okay"; +}; + +&sdmmc0 { + max-frequency = <150000000>; + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + disable-wp; + sd-uhs-sdr104; + vmmc-supply = <&vcc_sd>; + vqmmc-supply = <&vccio_sd>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>; + status = "okay"; +}; + +&sdmmc1 { + max-frequency = <150000000>; + bus-width = <4>; + disable-wp; + cap-sd-highspeed; + cap-sdio-irq; + keep-power-in-suspend; + mmc-pwrseq = <&sdio_pwrseq>; + non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc1_bus4 &sdmmc1_cmd &sdmmc1_clk>; + sd-uhs-sdr104; + status = "okay"; + rockchip,default-sample-phase = <90>; + + sdio-wifi@1 { + compatible = "brcm,bcm4329-fmac"; + reg = <0x1>; + interrupt-parent = <&gpio2>; + interrupts = <9 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "host-wake"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_host_wake>; + brcm,drive-strength = <10>; + }; +}; + +&sfc { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; +}; + +&tsadc { + status = "okay"; +}; + +&uart1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart1m0_xfer &uart1m0_ctsn &uart1m0_rtsn>; + uart-has-rtscts; + dma-names = "tx\0rx"; + + bluetooth { + compatible = "brcm,bcm4345c5"; + clocks = <&rk809 1>; + clock-names = "lpo"; + device-wakeup-gpios = <&gpio2 RK_PC0 GPIO_ACTIVE_HIGH>; + host-wakeup-gpios = <&gpio2 RK_PC1 GPIO_ACTIVE_HIGH>; + shutdown-gpios = <&gpio2 RK_PB7 GPIO_ACTIVE_HIGH>; + //pinctrl-names = "default"; + //pinctrl-0 = <&bt_host_wake &bt_wake &bt_enable>; + vbat-supply = <&vcc3v3_sys>; + vddio-supply = <&vcca1v8_pmu>; + }; +}; + +/* (debug) uart2 has connectors near the usb-c power, but also on the 40-pin pins 6 (tx) and 8 (rx) - don't wire both */ +&uart2 { + status = "okay"; +}; + +&uart5 { + pinctrl-0 = <&uart5m1_xfer>; +}; + +&uart7 { + pinctrl-0 = <&uart7m2_xfer>; +}; + +&usb2phy0 { + status = "okay"; +}; + +&usb2phy0_host { + phy-supply = <&vcc5v0_host &vcc5v0_otg>; + status = "okay"; +}; + +&usb2phy0_otg { + status = "okay"; +}; + +&usb2phy1 { + status = "okay"; +}; + +&usb2phy1_host { + status = "okay"; + phy-supply = <&vcc5v0_usb2t &vcc5v0_usb2b>; +}; + +&usb2phy1_otg { + status = "okay"; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; + +&usb_host0_xhci { + dr_mode = "host"; + extcon = <&usb2phy0>; + status = "okay"; +}; + +&usb_host1_ehci { + status = "okay"; +}; + +&usb_host1_ohci { + status = "okay"; +}; + +&usb_host1_xhci { + status = "okay"; +}; + +&vop { + assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>; + assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>; + status = "okay"; +}; + +&vop_mmu { + status = "okay"; +}; + +&vp0 { + vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 { + reg = ; + remote-endpoint = <&hdmi_in_vp0>; + }; +}; diff --git a/patch/u-boot/v2024.10/board_bigtreetech-cb2/bigtreetech-cb2-dts-and-defconfig.patch b/patch/u-boot/v2024.10/board_bigtreetech-cb2/bigtreetech-cb2-dts-and-defconfig.patch new file mode 100644 index 000000000000..d567e3141b47 --- /dev/null +++ b/patch/u-boot/v2024.10/board_bigtreetech-cb2/bigtreetech-cb2-dts-and-defconfig.patch @@ -0,0 +1,645 @@ +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: JohnTheCoolingFan +Date: Mon, 18 Nov 2024 03:35:50 +0000 +Subject: Add BigTreeTech CB2 defconfig and device tree + +Signed-off-by: JohnTheCoolingFan +--- + arch/arm/dts/rk3566-bigtreetech-cb2-u-boot.dtsi | 3 + + arch/arm/dts/rk3566-bigtreetech-cb2.dts | 494 ++++++++++ + configs/bigtreetech-cb2-rk3566_defconfig | 115 +++ + 3 files changed, 612 insertions(+) + +diff --git a/arch/arm/dts/rk3566-bigtreetech-cb2-u-boot.dtsi b/arch/arm/dts/rk3566-bigtreetech-cb2-u-boot.dtsi +new file mode 100644 +index 00000000000..2e2341667f6 +--- /dev/null ++++ b/arch/arm/dts/rk3566-bigtreetech-cb2-u-boot.dtsi +@@ -0,0 +1,3 @@ ++// SPDX-License-Identifier: GPL-2.0+ ++ ++#include "rk356x-u-boot.dtsi" +diff --git a/arch/arm/dts/rk3566-bigtreetech-cb2.dts b/arch/arm/dts/rk3566-bigtreetech-cb2.dts +new file mode 100644 +index 00000000000..6bcf5b26f49 +--- /dev/null ++++ b/arch/arm/dts/rk3566-bigtreetech-cb2.dts +@@ -0,0 +1,494 @@ ++/* ++ * SPDX-License-Identifier: GPL-2.0+ ++ * ++ * (C) Copyright 2020 Rockchip Electronics Co., Ltd ++ */ ++ ++/dts-v1/; ++#include "rk356x.dtsi" ++#include "rk3566-bigtreetech-cb2-u-boot.dtsi" ++#include ++#include ++ ++/ { ++ model = "BigTreeTech CB2"; ++ compatible = "rockchip,rk3566"; ++ ++ aliases { ++ mmc0 = &sdhci; ++ mmc1 = &sdmmc0; ++ }; ++ ++ chosen { ++ stdout-path = "serial2:1500000n8"; ++ }; ++ ++ dc_12v: dc-12v { ++ compatible = "regulator-fixed"; ++ regulator-name = "dc_12v"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <12000000>; ++ regulator-max-microvolt = <12000000>; ++ }; ++ ++ vcc5v0_sys: vcc5v0-sys { ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc5v0_sys"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <5000000>; ++ regulator-max-microvolt = <5000000>; ++ vin-supply = <&dc_12v>; ++ }; ++ ++ vcc3v3_sys: vcc3v3-sys { ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc3v3_sys"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ vin-supply = <&vcc5v0_sys>; ++ }; ++ ++ vcc5v0_host: vcc5v0-host-regulator { ++ compatible = "regulator-fixed"; ++ enable-active-high; ++ gpio = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&vcc5v0_host_en>; ++ regulator-name = "vcc5v0_host"; ++ regulator-always-on; ++ regulator-boot-on; ++ }; ++ ++ led_sys: led-sys { ++ compatible = "regulator-fixed"; ++ regulator-name = "led_sys"; ++ enable-active-high; ++ gpio = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>; // Turn on blue led ++ regulator-boot-on; ++ regulator-always-on; ++ vin-supply = <&vcc3v3_sys>; ++ }; ++ ++ adc-keys { ++ compatible = "adc-keys"; ++ io-channels = <&saradc 0>; ++ io-channel-names = "buttons"; ++ keyup-threshold-microvolt = <1800000>; ++ status = "okay"; ++ ++ volumeup-key { ++ linux,code = ; ++ label = "volume up"; ++ press-threshold-microvolt = <9>; ++ }; ++ }; ++}; ++ ++&sdhci { ++ bus-width = <8>; ++ cap-mmc-highspeed; ++ mmc-hs200-1_8v; ++ no-sd; ++ no-sdio; ++ non-removable; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_datastrobe>; ++ status = "okay"; ++}; ++ ++&sdmmc0 { ++ bus-width = <4>; ++ cap-sd-highspeed; ++ disable-wp; ++ no-mmc; ++ no-sdio; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>; ++ status = "okay"; ++}; ++ ++&sfc { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ status = "okay"; ++ ++ flash@0 { ++ compatible = "jedec,spi-nor"; ++ reg = <0>; ++ spi-max-frequency = <24000000>; ++ }; ++}; ++ ++/* ++&crypto { ++ status = "okay"; ++}; ++*/ ++ ++&uart2 { ++ status = "okay"; ++}; ++ ++&pmu_io_domains { ++ status = "okay"; ++ pmuio1-supply = <&vcc3v3_pmu>; ++ pmuio2-supply = <&vcc3v3_pmu>; ++ vccio1-supply = <&vccio_acodec>; ++ vccio3-supply = <&vccio_sd>; ++ vccio4-supply = <&vcc_1v8>; ++ vccio5-supply = <&vcc_3v3>; ++ vccio6-supply = <&vcc_1v8>; ++ vccio7-supply = <&vcc_3v3>; ++}; ++ ++&gpio0 { ++}; ++ ++&gpio3 { ++}; ++ ++&i2c0 { ++ status = "okay"; ++ clock-frequency = <100000>; ++ ++ vdd_cpu: tcs4525@1c { ++ compatible = "tcs,tcs452x"; ++ reg = <0x1c>; ++ vin-supply = <&vcc5v0_sys>; ++ regulator-compatible = "fan53555-reg"; ++ regulator-name = "vdd_cpu"; ++ regulator-min-microvolt = <712500>; ++ regulator-max-microvolt = <1390000>; ++ regulator-init-microvolt = <900000>; ++ regulator-ramp-delay = <2300>; ++ fcs,suspend-voltage-selector = <1>; ++ regulator-boot-on; ++ regulator-always-on; ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ rk809: pmic@20 { ++ status = "okay"; ++ compatible = "rockchip,rk809"; ++ reg = <0x20>; ++ interrupt-parent = <&gpio0>; ++ interrupts = <3 IRQ_TYPE_LEVEL_LOW>; ++ ++ pinctrl-names = "default", "pmic-sleep", ++ "pmic-power-off", "pmic-reset"; ++ pinctrl-0 = <&pmic_int>; ++ pinctrl-1 = <&soc_slppin_slp>, <&rk817_slppin_slp>; ++ pinctrl-2 = <&soc_slppin_gpio>, <&rk817_slppin_pwrdn>; ++ pinctrl-3 = <&soc_slppin_gpio>, <&rk817_slppin_rst>; ++ ++ rockchip,system-power-controller; ++ wakeup-source; ++ #clock-cells = <1>; ++ clock-output-names = "rk808-clkout1", "rk808-clkout2"; ++ //fb-inner-reg-idxs = <2>; ++ /* 1: rst regs (default in codes), 0: rst the pmic */ ++ pmic-reset-func = <0>; ++ /* not save the PMIC_POWER_EN register in uboot */ ++ not-save-power-en = <1>; ++ ++ vcc1-supply = <&vcc3v3_sys>; ++ vcc2-supply = <&vcc3v3_sys>; ++ vcc3-supply = <&vcc3v3_sys>; ++ vcc4-supply = <&vcc3v3_sys>; ++ vcc5-supply = <&vcc3v3_sys>; ++ vcc6-supply = <&vcc3v3_sys>; ++ vcc7-supply = <&vcc3v3_sys>; ++ vcc8-supply = <&vcc3v3_sys>; ++ vcc9-supply = <&vcc3v3_sys>; ++ ++ pwrkey { ++ status = "okay"; ++ }; ++ ++ pinctrl_rk8xx: pinctrl_rk8xx { ++ gpio-controller; ++ #gpio-cells = <2>; ++ ++ rk817_slppin_null: rk817_slppin_null { ++ pins = "gpio_slp"; ++ function = "pin_fun0"; ++ }; ++ ++ rk817_slppin_slp: rk817_slppin_slp { ++ pins = "gpio_slp"; ++ function = "pin_fun1"; ++ }; ++ ++ rk817_slppin_pwrdn: rk817_slppin_pwrdn { ++ pins = "gpio_slp"; ++ function = "pin_fun2"; ++ }; ++ ++ rk817_slppin_rst: rk817_slppin_rst { ++ pins = "gpio_slp"; ++ function = "pin_fun3"; ++ }; ++ }; ++ ++ regulators { ++ vdd_logic: DCDC_REG1 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <500000>; ++ regulator-max-microvolt = <1350000>; ++ regulator-init-microvolt = <900000>; ++ regulator-ramp-delay = <6001>; ++ regulator-initial-mode = <0x2>; ++ regulator-name = "vdd_logic"; ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ }; ++ }; ++ ++ vdd_gpu: DCDC_REG2 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <500000>; ++ regulator-max-microvolt = <1350000>; ++ regulator-init-microvolt = <900000>; ++ regulator-ramp-delay = <6001>; ++ regulator-initial-mode = <0x2>; ++ regulator-name = "vdd_gpu"; ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ }; ++ }; ++ ++ vcc_ddr: DCDC_REG3 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-initial-mode = <0x2>; ++ regulator-name = "vcc_ddr"; ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ }; ++ }; ++ ++ vdd_npu: DCDC_REG4 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <500000>; ++ regulator-max-microvolt = <1350000>; ++ regulator-init-microvolt = <900000>; ++ regulator-ramp-delay = <6001>; ++ regulator-initial-mode = <0x2>; ++ regulator-name = "vdd_npu"; ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ }; ++ }; ++ ++ vdda0v9_image: LDO_REG1 { ++ regulator-boot-on; ++ regulator-always-on; ++ regulator-min-microvolt = <900000>; ++ regulator-max-microvolt = <900000>; ++ regulator-name = "vdda0v9_image"; ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vdda_0v9: LDO_REG2 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <900000>; ++ regulator-max-microvolt = <900000>; ++ regulator-name = "vdda_0v9"; ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vdda0v9_pmu: LDO_REG3 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <900000>; ++ regulator-max-microvolt = <900000>; ++ regulator-name = "vdda0v9_pmu"; ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ regulator-suspend-microvolt = <900000>; ++ }; ++ }; ++ ++ vccio_acodec: LDO_REG4 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-name = "vccio_acodec"; ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vccio_sd: LDO_REG5 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-name = "vccio_sd"; ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vcc3v3_pmu: LDO_REG6 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-name = "vcc3v3_pmu"; ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ regulator-suspend-microvolt = <3300000>; ++ }; ++ }; ++ ++ vcca_1v8: LDO_REG7 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ regulator-name = "vcca_1v8"; ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vcca1v8_pmu: LDO_REG8 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ regulator-name = "vcca1v8_pmu"; ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ regulator-suspend-microvolt = <1800000>; ++ }; ++ }; ++ ++ vcca1v8_image: LDO_REG9 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ regulator-name = "vcca1v8_image"; ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vcc_1v8: DCDC_REG5 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ regulator-name = "vcc_1v8"; ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vcc_3v3: SWITCH_REG1 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-name = "vcc_3v3"; ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vcc3v3_sd: SWITCH_REG2 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-name = "vcc3v3_sd"; ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ }; ++ }; ++}; ++ ++&usb2phy1_host { ++ phy-supply = <&vcc5v0_host>; ++ status = "okay"; ++}; ++ ++&usb2phy1_otg { ++ phy-supply = <&vcc5v0_host>; ++ status = "okay"; ++}; ++ ++&usb2phy1 { ++ status = "okay"; ++}; ++ ++&usb_host0_ehci { ++ status = "okay"; ++}; ++ ++&usb_host0_ohci { ++ status = "okay"; ++}; ++ ++&usb_host1_ehci { ++ status = "okay"; ++}; ++ ++&usb_host1_ohci { ++ status = "okay"; ++}; ++ ++&usb2phy1_grf { ++}; ++ ++ ++&pinctrl { ++ ++ pcfg_output_low_pull_down: pcfg_output_low_pull_down { ++ bias-pull-down; ++ output-low; ++ }; ++ ++ pmic { ++ pmic_int: pmic_int { ++ rockchip,pins = ++ <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>; ++ }; ++ ++ soc_slppin_gpio: soc_slppin_gpio { ++ rockchip,pins = ++ <0 RK_PA2 RK_FUNC_GPIO &pcfg_output_low_pull_down>; ++ }; ++ ++ soc_slppin_slp: soc_slppin_slp { ++ rockchip,pins = ++ <0 RK_PA2 RK_FUNC_1 &pcfg_pull_up>; ++ }; ++ ++ soc_slppin_rst: soc_slppin_rst { ++ rockchip,pins = ++ <0 RK_PA2 RK_FUNC_2 &pcfg_pull_none>; ++ }; ++ }; ++ ++ usb { ++ vcc5v0_host_en: vcc5v0-host-en { ++ rockchip,pins = <0 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ }; ++}; +diff --git a/configs/bigtreetech-cb2-rk3566_defconfig b/configs/bigtreetech-cb2-rk3566_defconfig +new file mode 100644 +index 00000000000..3c7c294545a +--- /dev/null ++++ b/configs/bigtreetech-cb2-rk3566_defconfig +@@ -0,0 +1,115 @@ ++CONFIG_ARM=y ++CONFIG_ARCH_ROCKCHIP=y ++CONFIG_SYS_MALLOC_F_LEN=0x80000 ++CONFIG_SF_DEFAULT_SPEED=20000000 ++CONFIG_DEFAULT_DEVICE_TREE="rk3566-bigtreetech-cb2" ++CONFIG_ROCKCHIP_RK3568=y ++CONFIG_SPL_SERIAL=y ++CONFIG_DEBUG_UART_BASE=0xFE660000 ++CONFIG_DEBUG_UART_CLOCK=24000000 ++CONFIG_SPL_LIBDISK_SUPPORT=y ++CONFIG_SPL_SPI_FLASH_SUPPORT=y ++CONFIG_SPL_SPI=y ++CONFIG_SYS_LOAD_ADDR=0xc00800 ++CONFIG_PCI=y ++CONFIG_DEBUG_UART=y ++CONFIG_FIT=y ++CONFIG_FIT_VERBOSE=y ++CONFIG_SPL_FIT_SIGNATURE=y ++CONFIG_SPL_LOAD_FIT=y ++CONFIG_LEGACY_IMAGE_FORMAT=y ++CONFIG_BOOTDELAY=0 ++# CONFIG_DISPLAY_CPUINFO is not set ++CONFIG_DISPLAY_BOARDINFO_LATE=y ++CONFIG_SPL_MAX_SIZE=0x40000 ++CONFIG_SPL_PAD_TO=0x7f8000 ++# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set ++CONFIG_SPL_MMC_WRITE=y ++CONFIG_SPL_DM_RESET=y ++CONFIG_SPL_SPI_LOAD=y ++CONFIG_SYS_SPI_U_BOOT_OFFS=0x60000 ++CONFIG_SPL_ATF=y ++CONFIG_SYS_PROMPT="CB2@uboot:~$ " ++CONFIG_CMD_BOOTZ=y ++# CONFIG_CMD_BOOTEFI_HELLO_COMPILE is not set ++# CONFIG_CMD_ELF is not set ++# CONFIG_CMD_IMI is not set ++# CONFIG_CMD_XIMG is not set ++# CONFIG_CMD_LZMADEC is not set ++# CONFIG_CMD_UNZIP is not set ++CONFIG_CMD_GPT=y ++# CONFIG_CMD_LOADB is not set ++# CONFIG_CMD_LOADS is not set ++CONFIG_CMD_MMC=y ++CONFIG_CMD_MTD=y ++CONFIG_CMD_PCI=y ++CONFIG_CMD_USB=y ++CONFIG_CMD_USB_MASS_STORAGE=y ++# CONFIG_CMD_ITEST is not set ++CONFIG_CMD_TFTPPUT=y ++# CONFIG_NET_TFTP_VARS is not set ++# CONFIG_SPL_DOS_PARTITION is not set ++# CONFIG_ISO_PARTITION is not set ++CONFIG_EFI_PARTITION_ENTRIES_NUMBERS=64 ++CONFIG_SPL_OF_CONTROL=y ++CONFIG_OF_LIVE=y ++# CONFIG_OF_UPSTREAM is not set ++CONFIG_OF_SPL_REMOVE_PROPS="" ++CONFIG_SYS_RELOC_GD_ENV_ADDR=y ++CONFIG_SPL_DM_SEQ_ALIAS=y ++CONFIG_SPL_REGMAP=y ++CONFIG_SPL_SYSCON=y ++CONFIG_SPL_CLK=y ++CONFIG_FASTBOOT_BUF_ADDR=0xc00800 ++CONFIG_FASTBOOT_BUF_SIZE=0x04000000 ++CONFIG_ROCKCHIP_GPIO=y ++CONFIG_SYS_I2C_ROCKCHIP=y ++CONFIG_LED=y ++CONFIG_LED_GPIO=y ++CONFIG_MISC=y ++CONFIG_MMC_DW=y ++CONFIG_MMC_DW_ROCKCHIP=y ++CONFIG_MMC_SDHCI=y ++CONFIG_MMC_SDHCI_SDMA=y ++CONFIG_MMC_SDHCI_ROCKCHIP=y ++CONFIG_SPI_FLASH_EON=y ++CONFIG_SPI_FLASH_GIGADEVICE=y ++CONFIG_SPI_FLASH_MACRONIX=y ++CONFIG_SPI_FLASH_WINBOND=y ++CONFIG_SPI_FLASH_XMC=y ++CONFIG_SPI_FLASH_MTD=y ++CONFIG_PHY_MOTORCOMM=y ++CONFIG_DM_ETH_PHY=y ++CONFIG_PHY_GIGE=y ++CONFIG_DWC_ETH_QOS=y ++CONFIG_NVME=y ++CONFIG_DM_PCI_COMPAT=y ++CONFIG_PCIE_DW_ROCKCHIP=y ++CONFIG_PHY_ROCKCHIP_INNO_USB2=y ++CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y ++CONFIG_SPL_PINCTRL=y ++CONFIG_DM_PMIC=y ++CONFIG_PMIC_RK8XX=y ++CONFIG_SPL_PMIC_RK8XX=y ++CONFIG_REGULATOR_RK8XX=y ++CONFIG_SPL_RAM=y ++CONFIG_ROCKCHIP_SDRAM_COMMON=y ++CONFIG_BAUDRATE=1500000 ++CONFIG_DEBUG_UART_SHIFT=2 ++CONFIG_SYS_NS16550_MEM32=y ++CONFIG_ROCKCHIP_SFC=y ++CONFIG_SYSRESET=y ++CONFIG_USB=y ++CONFIG_USB_XHCI_HCD=y ++CONFIG_USB_XHCI_DWC3=y ++CONFIG_USB_XHCI_PCI=y ++CONFIG_USB_EHCI_HCD=y ++CONFIG_USB_EHCI_GENERIC=y ++CONFIG_USB_OHCI_HCD=y ++CONFIG_USB_OHCI_GENERIC=y ++CONFIG_USB_DWC3=y ++CONFIG_USB_DWC3_GENERIC=y ++CONFIG_USB_GADGET=y ++CONFIG_SHA512=y ++CONFIG_SPL_GZIP=y ++CONFIG_ERRNO_STR=y +-- +Created with Armbian build tools https://github.com/armbian/build + From 0bebaf03e80af4b6eb5eaa3db15f5295ffb84ee0 Mon Sep 17 00:00:00 2001 From: JohnTheCoolingFan Date: Wed, 4 Dec 2024 13:50:58 +0300 Subject: [PATCH 019/120] BigTreeTech CB2 edge device tree --- .../dt/rk3566-bigtreetech-cb2.dts | 1036 +++++++++++++++++ 1 file changed, 1036 insertions(+) create mode 100644 patch/kernel/archive/rockchip64-6.12/dt/rk3566-bigtreetech-cb2.dts diff --git a/patch/kernel/archive/rockchip64-6.12/dt/rk3566-bigtreetech-cb2.dts b/patch/kernel/archive/rockchip64-6.12/dt/rk3566-bigtreetech-cb2.dts new file mode 100644 index 000000000000..9d6c690c3a03 --- /dev/null +++ b/patch/kernel/archive/rockchip64-6.12/dt/rk3566-bigtreetech-cb2.dts @@ -0,0 +1,1036 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2020 Rockchip Electronics Co., Ltd. + * + */ +/dts-v1/; + +#include +#include +#include +#include +#include "rk3566.dtsi" + +/ { + model = "Rockchip RK3566 OPi 3B"; + compatible = "rockchip,rk3566-orangepi-3b", "rockchip,rk3566"; + + aliases { + ethernet0 = &gmac1; + mmc0 = &sdhci; + mmc1 = &sdmmc0; + }; + + chosen: chosen { + stdout-path = "serial2:1500000n8"; + }; + + fan: pwm-fan { + compatible = "pwm-fan"; + #cooling-cells = <2>; + pwms = <&pwm7 0 50000 0>; + cooling-levels = <0 50 100 150 200 255>; + rockchip,temp-trips = < + 50000 1 + 55000 2 + 60000 3 + 65000 4 + 70000 5 + >; + }; + + hdmi-con { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_con_in: endpoint { + remote-endpoint = <&hdmi_out_con>; + }; + }; + }; + + leds: leds { + compatible = "gpio-leds"; + + led@0 { + gpios = <&gpio4 RK_PA1 GPIO_ACTIVE_HIGH>; + label = "power_led"; + linux,default-trigger = "default-on"; + pinctrl-names = "default"; + pinctrl-0 =<&blue_led>; + }; + + led@1 { + gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>; + label = "status_led"; + linux,default-trigger = "heartbeat"; + pinctrl-names = "default"; + pinctrl-0 =<&leds_gpio>; + }; + }; + + rk809-sound { + compatible = "simple-audio-card"; + simple-audio-card,format = "i2s"; + simple-audio-card,name = "Analog RK809"; + simple-audio-card,mclk-fs = <256>; + + simple-audio-card,cpu { + sound-dai = <&i2s1_8ch>; + }; + + simple-audio-card,codec { + sound-dai = <&rk809>; + }; + }; + + sdio_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + clocks = <&rk809 1>; + clock-names = "ext_clock"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_enable_h>; + + /* + * On the module itself this is one of these (depending + * on the actual card populated): + * - SDIO_RESET_L_WL_REG_ON + * - PDN (power down when low) + */ + post-power-on-delay-ms = <200>; + reset-gpios = <&gpio0 RK_PD3 GPIO_ACTIVE_LOW>; + }; + + /* labeled +12v in schematic */ + vcc12v_dcin: vcc12v-dcin-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc12v_dcin"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + }; + + /* labeled +5v in schematic */ + vcc_5v: vcc-5v-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc_5v"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc12v_dcin>; + }; + + vbus: vbus { + compatible = "regulator-fixed"; + regulator-name = "vbus"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + /* labeled +3.3v For PCIe only in schematic */ + vcc3v3_pcie: vcc3v3-pcie-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_pcie"; + regulator-always-on; + regulator-boot-on; + enable-active-high; + gpio = <&gpio0 RK_PB1 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pcie_drv>; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc12v_dcin>; + }; + + vcc3v3_sys: vcc3v3-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vbus>; + }; + + vcc5v0_sys: vcc5v0-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vbus>; + }; + + vcc5v0_usb: vcc5v0-usb { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_usb"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vbus>; + }; + + vcc_sd: vcc-sd { + compatible = "regulator-fixed"; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "vcc_sd"; + vin-supply = <&vcc3v3_sys>; + }; + + vcc5v0_host: vcc5v0-host-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio0 RK_PB6 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc5v0_host_en>; + regulator-name = "vcc5v0_host3"; + regulator-always-on; + }; + + vcc5v0_otg: vcc5v0-otg-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio0 RK_PB5 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc5v0_otg_en>; + regulator-name = "vcc5v0_otg3"; + regulator-always-on; + }; + + vcc5v0_usb2t: vcc5v0-usb2t-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio0 RK_PD5 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc5v0_usb2t_en>; + regulator-name = "vcc5v0_usb2t"; + regulator-always-on; + }; + + vcc5v0_usb2b: vcc5v0-usb2b-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio0 RK_PC4 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc5v0_usb2b_en>; + regulator-name = "vcc5v0_usb2b"; + regulator-always-on; + }; + + ext_cam_clk: ext-cam-clk { + status = "okay"; + compatible = "fixed-clock"; + clock-frequency = <25000000>; + clock-output-names = "ext_cam_clk"; + #clock-cells = <0>; + }; + + can_mcp2515_osc: can-mcp2515-osc { + compatible = "fixed-clock"; + clock-frequency = <8000000>; + #clock-cells = <0>; + }; +}; + +&combphy1 { + status = "okay"; +}; + +&combphy2 { + status = "okay"; +}; + +&cpu0 { + cpu-supply = <&vdd_cpu>; +}; + +&cpu1 { + cpu-supply = <&vdd_cpu>; +}; + +&cpu2 { + cpu-supply = <&vdd_cpu>; +}; + +&cpu3 { + cpu-supply = <&vdd_cpu>; +}; + +&gmac1 { + assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>; + assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>, <&cru CLK_MAC1_2TOP>; + assigned-clock-rates = <0>, <125000000>; + clock_in_out = "input"; + phy-mode = "rgmii"; + pinctrl-names = "default"; + pinctrl-0 = <&gmac1m0_miim + &gmac1m0_tx_bus2 + &gmac1m0_rx_bus2 + &gmac1m0_rgmii_clk + &gmac1m0_clkinout + &gmac1m0_rgmii_bus>; + + snps,reset-gpio = <&gpio0 RK_PC5 GPIO_ACTIVE_LOW>; + snps,reset-active-low; + reset-gpios = <&gpio1 RK_PB2 GPIO_ACTIVE_HIGH>; + /* Reset time is 20ms, 100ms for rtl8211f */ + //snps,reset-delays-us = <0 20000 100000>; + snps,reset-delays-us = <0 50000 200000>; + tx_delay = <0x30>; + rx_delay = <0x10>; + phy-handle = <&rgmii_phy0>; + status = "okay"; +}; + +&gpu { + mali-supply = <&vdd_gpu>; + status = "okay"; +}; + +&hdmi { + avdd-0v9-supply = <&vdda0v9_image>; + avdd-1v8-supply = <&vcca1v8_image>; + status = "okay"; +}; + +&hdmi_in { + hdmi_in_vp0: endpoint { + remote-endpoint = <&vp0_out_hdmi>; + }; +}; + +&hdmi_out { + hdmi_out_con: endpoint { + remote-endpoint = <&hdmi_con_in>; + }; +}; + +&hdmi_sound { + status = "okay"; +}; + +&i2c0 { + status = "okay"; + + vdd_cpu: tsc4525@1c { + compatible = "tcs,tcs452x"; + reg = <0x1c>; + vin-supply = <&vcc5v0_sys>; + regulator-compatible = "fan53555-reg"; + regulator-name = "vdd_cpu"; + regulator-min-microvolt = <712500>; + regulator-max-microvolt = <1390000>; + regulator-init-microvolt = <900000>; + regulator-initial-mode = <1>; + regulator-ramp-delay = <2300>; + fcs,suspend-voltage-selector = <1>; + regulator-boot-on; + regulator-always-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + rk809: pmic@20 { + compatible = "rockchip,rk809"; + reg = <0x20>; + interrupt-parent = <&gpio0>; + interrupts = <3 IRQ_TYPE_LEVEL_LOW>; + + assigned-clocks = <&cru I2S1_MCLKOUT_TX>; + assigned-clock-parents = <&cru CLK_I2S1_8CH_TX>; + #clock-cells = <1>; + clock-names = "mclk"; + clocks = <&cru I2S1_MCLKOUT_TX>; + pinctrl-names = "default", "pmic-sleep", + "pmic-power-off", "pmic-reset"; + pinctrl-0 = <&pmic_int>, <&i2s1m0_mclk>; + pinctrl-1 = <&soc_slppin_slp>, <&rk817_slppin_slp>; + pinctrl-2 = <&soc_slppin_gpio>, <&rk817_slppin_pwrdn>; + pinctrl-3 = <&soc_slppin_gpio>, <&rk817_slppin_rst>; + #sound-dai-cells = <0>; + + rockchip,system-power-controller; + wakeup-source; + + vcc1-supply = <&vcc3v3_sys>; + vcc2-supply = <&vcc3v3_sys>; + vcc3-supply = <&vcc3v3_sys>; + vcc4-supply = <&vcc3v3_sys>; + vcc5-supply = <&vcc3v3_sys>; + vcc6-supply = <&vcc3v3_sys>; + vcc7-supply = <&vcc3v3_sys>; + vcc8-supply = <&vcc3v3_sys>; + vcc9-supply = <&vcc3v3_sys>; + + pinctrl_rk8xx: pinctrl_rk8xx { + gpio-controller; + #gpio-cells = <2>; + + rk817_slppin_null: rk817_slppin_null { + pins = "gpio_slp"; + function = "pin_fun0"; + }; + + rk817_slppin_slp: rk817_slppin_slp { + pins = "gpio_slp"; + function = "pin_fun1"; + }; + + rk817_slppin_pwrdn: rk817_slppin_pwrdn { + pins = "gpio_slp"; + function = "pin_fun2"; + }; + + rk817_slppin_rst: rk817_slppin_rst { + pins = "gpio_slp"; + function = "pin_fun3"; + }; + }; + + regulators { + vdd_logic: DCDC_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1350000>; + regulator-init-microvolt = <900000>; + regulator-ramp-delay = <6001>; + regulator-initial-mode = <0x2>; + regulator-name = "vdd_logic"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_gpu: DCDC_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1350000>; + regulator-init-microvolt = <900000>; + regulator-ramp-delay = <6001>; + regulator-initial-mode = <0x2>; + regulator-name = "vdd_gpu"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_ddr: DCDC_REG3 { + regulator-always-on; + regulator-boot-on; + regulator-initial-mode = <0x2>; + regulator-name = "vcc_ddr"; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vdd_npu: DCDC_REG4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1350000>; + regulator-init-microvolt = <900000>; + regulator-ramp-delay = <6001>; + regulator-initial-mode = <0x2>; + regulator-name = "vdd_npu"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda0v9_image: LDO_REG1 { + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + regulator-name = "vdda0v9_image"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda_0v9: LDO_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + regulator-name = "vdda_0v9"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda0v9_pmu: LDO_REG3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + regulator-name = "vdda0v9_pmu"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <900000>; + }; + }; + + vccio_acodec: LDO_REG4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-name = "vccio_acodec"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vccio_sd: LDO_REG5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vccio_sd"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc3v3_pmu: LDO_REG6 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc3v3_pmu"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vcca_1v8: LDO_REG7 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcca_1v8"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcca1v8_pmu: LDO_REG8 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcca1v8_pmu"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vcca1v8_image: LDO_REG9 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcca1v8_image"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v8: DCDC_REG5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc_1v8"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_3v3: SWITCH_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vcc_3v3"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc3v3_sd: SWITCH_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vcc3v3_sd"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; + + codec { + mic-in-differential; + }; + }; +}; + +&i2c2 { + pinctrl-0 = <&i2c2m1_xfer>; +}; + +/* + * i2c3_m0 is exposed on the 40-pin (green connectors) + * pin 27 - i2c3_sda_m0 + * pin 28 - i2c3_scl_m0 + */ +&i2c3 { + status = "okay"; + + tft_tp: ns2009@48 { + compatible = "ti,tsc2007"; + reg = <0x48>; + status = "okay"; + ti,x-plate-ohms = <660>; + ti,rt-thr = <3000>; + ti,fuzzx = <32>; + ti,fuzzy = <16>; + i2c,ignore-nak = <1>; + }; +}; + +&i2s0_8ch { + status = "okay"; +}; + +&i2s1_8ch { + pinctrl-names = "default"; + pinctrl-0 = <&i2s1m0_sclktx + &i2s1m0_lrcktx + &i2s1m0_sdi0 + &i2s1m0_sdo0>; + rockchip,trcm-sync-tx-only; + status = "okay"; +}; + +&spi1 { + pinctrl-0 = <&spi1m1_cs0 &spi1m1_pins>; + + can_mcp2515: can-mcp2515@0 { + status = "disabled"; + compatible = "microchip,mcp2515"; + reg = <0x00>; + interrupt-parent = <&gpio4>; + interrupts = <3 IRQ_TYPE_LEVEL_LOW>; + spi-max-frequency = <10000000>; + clocks = <&can_mcp2515_osc>; + vdd-supply = <&vcc3v3_sys>; + xceiver-supply = <&vcc3v3_sys>; + pinctrl-names = "default"; + pinctrl-0 = <&mcp2515_int_pin>; + }; + + /* + tft_35: st7789v@1 { + status = "disabled"; + compatible = "sitronix,st7796s"; + reg = <0x01>; + spi-max-frequency = <12500000>; + fps = <60>; + buswidth = <8>; + rotate = <0>; + width = <480>; + height = <320>; + bpp = <24>; + bgr; + regwidth = <8>; + debug = <0>; + txbuflen = <0x2000>; + spi-cpol; + spi-cpha; + dc-gpios = <&gpio0 RK_C7 GPIO_ACTIVE_HIGH>; + }; + */ +}; + +&spi3 { + pinctrl-0 = <&spi3m1_cs0 &spi3m1_pins>; +}; + +&mdio1 { + rgmii_phy0: phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0x0>; + }; +}; + +&pcie2x1 { + reset-gpios = <&gpio0 RK_PB6 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc3v3_pcie>; + status = "okay"; +}; + +&pinctrl { + wireless-bluetooth { + uart1_gpios: uart1-gpios { + rockchip,pins = <2 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + sd { + sdmmc0_pwr_h: sdmmc0-pwr-h { + rockchip,pins = + <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + mxc6655xa { + mxc6655xa_irq_gpio: mxc6655xa_irq_gpio { + rockchip,pins = <3 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + pmic { + pmic_int: pmic_int { + rockchip,pins = + <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + soc_slppin_gpio: soc_slppin_gpio { + rockchip,pins = + <0 RK_PA2 RK_FUNC_GPIO &pcfg_output_low>; + }; + + soc_slppin_slp: soc_slppin_slp { + rockchip,pins = + <0 RK_PA2 1 &pcfg_pull_none>; + }; + + soc_slppin_rst: soc_slppin_rst { + rockchip,pins = + <0 RK_PA2 2 &pcfg_pull_none>; + }; + }; + + touch { + touch_gpio: touch-gpio { + rockchip,pins = + <0 RK_PB5 RK_FUNC_GPIO &pcfg_pull_up>, + <0 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + sdio-pwrseq { + wifi_enable_h: wifi-enable-h { + rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + wifi_host_wake: wifi-host-wake-l { + rockchip,pins = <2 RK_PB1 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; + + usb { + vcc5v0_host_en: vcc5v0-host-en { + rockchip,pins = <0 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + vcc5v0_otg_en: vcc5v0-otg-en { + rockchip,pins = <0 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + vcc5v0_usb2t_en: vcc5v0_usb2t-en { + rockchip,pins = <3 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + vcc5v0_usb2b_en: vcc5v0-usb2b-en { + rockchip,pins = <4 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + work-led { + leds_gpio: leds-gpio { + rockchip,pins = <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + blue_led: led-blue { + rockchip,pins = <4 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + headphone { + hp_det: hp-det { + rockchip,pins = <0 RK_PC4 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; + + pcie { + pcie_drv: pcie-drv { + rockchip,pins = <4 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + edp { + edp_hpd: edp-hpd { + rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + bl_en: bl-en { + rockchip,pins = <0 RK_PB5 RK_FUNC_GPIO &pcfg_output_high>; + }; + }; + + bt { + bt_enable: bt-enable-h { + rockchip,pins = <2 RK_PB7 RK_FUNC_GPIO &pcfg_pull_down>; + }; + + bt_host_wake: bt-host-wake-l { + rockchip,pins = <2 RK_PC1 RK_FUNC_GPIO &pcfg_pull_down>; + }; + + bt_wake: bt-wake-l { + rockchip,pins = <2 RK_PC0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + mcp2515_int_pin { + mcp2515_int_pin: mcp2515_in_pin { + rockchip,pins = <4 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; +}; + + /* + * There are 10 independent IO domains in RK3566/RK3568, including PMUIO[0:2] and VCCIO[1:7]. + * 1/ PMUIO0 and PMUIO1 are fixed-level power domains which cannot be configured; + * 2/ PMUIO2 and VCCIO1,VCCIO[3:7] domains require that their hardware power supply voltages + * must be consistent with the software configuration correspondingly + * a/ When the hardware IO level is connected to 1.8V, the software voltage configuration + * should also be configured to 1.8V accordingly; + * b/ When the hardware IO level is connected to 3.3V, the software voltage configuration + * should also be configured to 3.3V accordingly; + * 3/ VCCIO2 voltage control selection (0xFDC20140) + * BIT[0]: 0x0: from GPIO_0A7 (default) + * BIT[0]: 0x1: from GRF + * Default is determined by Pin FLASH_VOL_SEL/GPIO0_A7: + * L:VCCIO2 must supply 3.3V + * H:VCCIO2 must supply 1.8V + */ + +&pmu_io_domains { + status = "okay"; + pmuio1-supply = <&vcc3v3_pmu>; + pmuio2-supply = <&vcc3v3_pmu>; + vccio1-supply = <&vcc_3v3>; + vccio2-supply = <&vcc_1v8>; + vccio3-supply = <&vccio_sd>; + vccio4-supply = <&vcc_1v8>; + vccio5-supply = <&vcc_3v3>; + vccio6-supply = <&vcc_3v3>; + vccio7-supply = <&vcc_3v3>; +}; + +&pwm0 { + pinctrl-0 = <&pwm0m1_pins>; +}; + +&pwm7 { + status = "disabled"; +}; + +&pwm12 { + pinctrl-0 = <&pwm12m1_pins>; +}; + +&pwm13 { + pinctrl-0 = <&pwm13m1_pins>; +}; + +&pwm14 { + pinctrl-0 = <&pwm14m1_pins>; +}; + +&pwm15 { + pinctrl-0 = <&pwm15m1_pins>; +}; + +&saradc { + status = "okay"; + vref-supply = <&vcca_1v8>; +}; + +&sdhci { + bus-width = <8>; + max-frequency = <200000000>; + non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd>; + status = "okay"; +}; + +&sdmmc0 { + max-frequency = <150000000>; + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + disable-wp; + sd-uhs-sdr104; + vmmc-supply = <&vcc_sd>; + vqmmc-supply = <&vccio_sd>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>; + status = "okay"; +}; + +&sdmmc1 { + max-frequency = <150000000>; + bus-width = <4>; + disable-wp; + cap-sd-highspeed; + cap-sdio-irq; + keep-power-in-suspend; + mmc-pwrseq = <&sdio_pwrseq>; + non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc1_bus4 &sdmmc1_cmd &sdmmc1_clk>; + sd-uhs-sdr104; + status = "okay"; + rockchip,default-sample-phase = <90>; + + sdio-wifi@1 { + compatible = "brcm,bcm4329-fmac"; + reg = <0x1>; + interrupt-parent = <&gpio2>; + interrupts = <9 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "host-wake"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_host_wake>; + brcm,drive-strength = <10>; + }; +}; + +&sfc { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; +}; + +&tsadc { + status = "okay"; +}; + +&uart1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart1m0_xfer &uart1m0_ctsn &uart1m0_rtsn>; + uart-has-rtscts; + dma-names = "tx\0rx"; + + bluetooth { + compatible = "brcm,bcm4345c5"; + clocks = <&rk809 1>; + clock-names = "lpo"; + device-wakeup-gpios = <&gpio2 RK_PC0 GPIO_ACTIVE_HIGH>; + host-wakeup-gpios = <&gpio2 RK_PC1 GPIO_ACTIVE_HIGH>; + shutdown-gpios = <&gpio2 RK_PB7 GPIO_ACTIVE_HIGH>; + //pinctrl-names = "default"; + //pinctrl-0 = <&bt_host_wake &bt_wake &bt_enable>; + vbat-supply = <&vcc3v3_sys>; + vddio-supply = <&vcca1v8_pmu>; + }; +}; + +/* (debug) uart2 has connectors near the usb-c power, but also on the 40-pin pins 6 (tx) and 8 (rx) - don't wire both */ +&uart2 { + status = "okay"; +}; + +&uart5 { + pinctrl-0 = <&uart5m1_xfer>; +}; + +&uart7 { + pinctrl-0 = <&uart7m2_xfer>; +}; + +&usb2phy0 { + status = "okay"; +}; + +&usb2phy0_host { + phy-supply = <&vcc5v0_host &vcc5v0_otg>; + status = "okay"; +}; + +&usb2phy0_otg { + status = "okay"; +}; + +&usb2phy1 { + status = "okay"; +}; + +&usb2phy1_host { + status = "okay"; + phy-supply = <&vcc5v0_usb2t &vcc5v0_usb2b>; +}; + +&usb2phy1_otg { + status = "okay"; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; + +&usb_host0_xhci { + dr_mode = "host"; + extcon = <&usb2phy0>; + status = "okay"; +}; + +&usb_host1_ehci { + status = "okay"; +}; + +&usb_host1_ohci { + status = "okay"; +}; + +&usb_host1_xhci { + status = "okay"; +}; + +&vop { + assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>; + assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>; + status = "okay"; +}; + +&vop_mmu { + status = "okay"; +}; + +&vp0 { + vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 { + reg = ; + remote-endpoint = <&hdmi_in_vp0>; + }; +}; From f156779bdf92856fca87a509e3a85a71d9f16499 Mon Sep 17 00:00:00 2001 From: JohnTheCoolingFan Date: Wed, 4 Dec 2024 14:34:08 +0300 Subject: [PATCH 020/120] Move bigtreetech cb2 from csc category --- config/boards/{bigtreetech-cb2.csc => bigtreetech-cb2.conf} | 0 1 file changed, 0 insertions(+), 0 deletions(-) rename config/boards/{bigtreetech-cb2.csc => bigtreetech-cb2.conf} (100%) diff --git a/config/boards/bigtreetech-cb2.csc b/config/boards/bigtreetech-cb2.conf similarity index 100% rename from config/boards/bigtreetech-cb2.csc rename to config/boards/bigtreetech-cb2.conf From a3b81f1d08a4a757b0dd35a42c90852dd1d0b818 Mon Sep 17 00:00:00 2001 From: JohnTheCoolingFan Date: Wed, 4 Dec 2024 19:39:31 +0300 Subject: [PATCH 021/120] BigTreeTech CB2 maintainer --- config/boards/bigtreetech-cb2.conf | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/config/boards/bigtreetech-cb2.conf b/config/boards/bigtreetech-cb2.conf index 9ee8f98fd858..b9ce764d7ded 100644 --- a/config/boards/bigtreetech-cb2.conf +++ b/config/boards/bigtreetech-cb2.conf @@ -1,7 +1,7 @@ # Rockchip RK3566 quad core 2GB-8GB GBE eMMC NVMe USB3 WiFi BOARD_NAME="BigTreeTech CB2" BOARDFAMILY="rockchip64" -BOARD_MAINTAINER="" +BOARD_MAINTAINER="JohnTheCoolingFan" BOOTCONFIG="bigtreetech-cb2-rk3566_defconfig" BOOT_SOC="rk3566" KERNEL_TARGET="current,edge" From 6ba9d13dd93756966b9646cad57e96ecf9e255b7 Mon Sep 17 00:00:00 2001 From: JohnTheCoolingFan Date: Thu, 5 Dec 2024 10:07:41 +0300 Subject: [PATCH 022/120] BigTreeTech CB2: fix misplaced `reset-gpios` This property was supposed to go to pcie2x1, not gmac1 --- .../rockchip64-6.12/dt/rk3566-bigtreetech-cb2.dts | 9 +++++++-- .../archive/rockchip64-6.6/dt/rk3566-bigtreetech-cb2.dts | 9 +++++++-- 2 files changed, 14 insertions(+), 4 deletions(-) diff --git a/patch/kernel/archive/rockchip64-6.12/dt/rk3566-bigtreetech-cb2.dts b/patch/kernel/archive/rockchip64-6.12/dt/rk3566-bigtreetech-cb2.dts index 9d6c690c3a03..ea50d423a3ba 100644 --- a/patch/kernel/archive/rockchip64-6.12/dt/rk3566-bigtreetech-cb2.dts +++ b/patch/kernel/archive/rockchip64-6.12/dt/rk3566-bigtreetech-cb2.dts @@ -280,7 +280,6 @@ snps,reset-gpio = <&gpio0 RK_PC5 GPIO_ACTIVE_LOW>; snps,reset-active-low; - reset-gpios = <&gpio1 RK_PB2 GPIO_ACTIVE_HIGH>; /* Reset time is 20ms, 100ms for rtl8211f */ //snps,reset-delays-us = <0 20000 100000>; snps,reset-delays-us = <0 50000 200000>; @@ -677,7 +676,9 @@ }; &pcie2x1 { - reset-gpios = <&gpio0 RK_PB6 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpio1 RK_PB2 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pcie_reset_h>; vpcie3v3-supply = <&vcc3v3_pcie>; status = "okay"; }; @@ -780,6 +781,10 @@ pcie_drv: pcie-drv { rockchip,pins = <4 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>; }; + + pcie_reset_h: pcie-reset-h { + rockchip,pins = <1 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; + }; }; edp { diff --git a/patch/kernel/archive/rockchip64-6.6/dt/rk3566-bigtreetech-cb2.dts b/patch/kernel/archive/rockchip64-6.6/dt/rk3566-bigtreetech-cb2.dts index 0a2338f6ec42..c68a302c87cd 100644 --- a/patch/kernel/archive/rockchip64-6.6/dt/rk3566-bigtreetech-cb2.dts +++ b/patch/kernel/archive/rockchip64-6.6/dt/rk3566-bigtreetech-cb2.dts @@ -280,7 +280,6 @@ snps,reset-gpio = <&gpio0 RK_PC5 GPIO_ACTIVE_LOW>; snps,reset-active-low; - reset-gpios = <&gpio1 RK_PB2 GPIO_ACTIVE_HIGH>; /* Reset time is 20ms, 100ms for rtl8211f */ //snps,reset-delays-us = <0 20000 100000>; snps,reset-delays-us = <0 50000 200000>; @@ -677,7 +676,9 @@ }; &pcie2x1 { - reset-gpios = <&gpio0 RK_PB6 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpio1 RK_PB2 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pcie_reset_h>; vpcie3v3-supply = <&vcc3v3_pcie>; status = "okay"; }; @@ -780,6 +781,10 @@ pcie_drv: pcie-drv { rockchip,pins = <4 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>; }; + + pcie_reset_h: pcie-reset-h { + rockchip,pins = <1 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; + }; }; edp { From 8e5175052d21677490da99db6538f023f0ff9e1d Mon Sep 17 00:00:00 2001 From: Ricardo Pardini Date: Wed, 4 Dec 2024 12:17:17 +0100 Subject: [PATCH 023/120] mixtile-edge2: bump vendor to `branch:rk-6.1-rkr4.1` - In line with 35352fa288cedcee806caa83bb5de6c9162758b7 (bump to rkr4.1) - "Copypasta from rockchip-rk3588.conf family file -- we _really_ gotta find a better way!" - I'm not proud of having done it this way, but now it broke (two vendor debs are produced in different versions) so lets fix it --- config/boards/mixtile-edge2.csc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/config/boards/mixtile-edge2.csc b/config/boards/mixtile-edge2.csc index 66cdbb67dd3d..41a7e170c30d 100644 --- a/config/boards/mixtile-edge2.csc +++ b/config/boards/mixtile-edge2.csc @@ -40,7 +40,7 @@ function post_family_config_branch_vendor__kernel_and_uboot_rk35xx_mixtile_edge2 # Copypasta from rockchip-rk3588.conf family file -- we _really_ gotta find a better way! declare -g KERNEL_MAJOR_MINOR="6.1" # Major and minor versions of this kernel. declare -g KERNELSOURCE='https://github.com/armbian/linux-rockchip.git' - declare -g KERNELBRANCH='branch:rk-6.1-rkr3' + declare -g KERNELBRANCH='branch:rk-6.1-rkr4.1' declare -g KERNELPATCHDIR='rk35xx-vendor-6.1' declare -g LINUXFAMILY=rk35xx declare -g -i KERNEL_GIT_CACHE_TTL=120 # 2 minutes From 06c9c2dbe5671e5d8f783b8fdee675acc1e60628 Mon Sep 17 00:00:00 2001 From: Maxim Medvedev Date: Fri, 29 Nov 2024 19:46:48 +0100 Subject: [PATCH 024/120] feat: add ST7796 kernel module (fbtft) Add support for ST7796 based LCD module (connected via SPI interface). One of real device example is [MKS PI-TS35 display](https://github.com/makerbase-mks/MKS-TFT-Hardware/tree/master/MKS%20PI-TS35). --- config/kernel/linux-rockchip64-current.config | 1 + config/kernel/linux-rockchip64-edge.config | 1 + .../general-st7796-driver.patch | 196 ++++++++++++++++++ .../general-st7796-driver.patch | 196 ++++++++++++++++++ .../general-st7796-driver.patch | 196 ++++++++++++++++++ 5 files changed, 590 insertions(+) create mode 100644 patch/kernel/archive/rockchip64-6.12/general-st7796-driver.patch create mode 100644 patch/kernel/archive/rockchip64-6.6/general-st7796-driver.patch create mode 100644 patch/kernel/archive/rockchip64-6.9/general-st7796-driver.patch diff --git a/config/kernel/linux-rockchip64-current.config b/config/kernel/linux-rockchip64-current.config index 2e8e7e9cebcc..e7db6f5d8fa9 100644 --- a/config/kernel/linux-rockchip64-current.config +++ b/config/kernel/linux-rockchip64-current.config @@ -7796,6 +7796,7 @@ CONFIG_FB_TFT_SSD1331=m CONFIG_FB_TFT_SSD1351=m CONFIG_FB_TFT_ST7735R=m CONFIG_FB_TFT_ST7789V=m +CONFIG_FB_TFT_ST7796=m CONFIG_FB_TFT_TINYLCD=m CONFIG_FB_TFT_TLS8204=m CONFIG_FB_TFT_UC1611=m diff --git a/config/kernel/linux-rockchip64-edge.config b/config/kernel/linux-rockchip64-edge.config index 18a6f5228004..4eaae942d505 100644 --- a/config/kernel/linux-rockchip64-edge.config +++ b/config/kernel/linux-rockchip64-edge.config @@ -8031,6 +8031,7 @@ CONFIG_FB_TFT_SSD1331=m CONFIG_FB_TFT_SSD1351=m CONFIG_FB_TFT_ST7735R=m CONFIG_FB_TFT_ST7789V=m +CONFIG_FB_TFT_ST7796=m CONFIG_FB_TFT_TINYLCD=m CONFIG_FB_TFT_TLS8204=m CONFIG_FB_TFT_UC1611=m diff --git a/patch/kernel/archive/rockchip64-6.12/general-st7796-driver.patch b/patch/kernel/archive/rockchip64-6.12/general-st7796-driver.patch new file mode 100644 index 000000000000..e986a922556a --- /dev/null +++ b/patch/kernel/archive/rockchip64-6.12/general-st7796-driver.patch @@ -0,0 +1,196 @@ +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Maxim Medvedev +Date: Fri, 12 May 2023 22:30:14 +0000 +Subject: Custom st7796 display module + +--- + +diff --git a/drivers/staging/fbtft/Kconfig b/drivers/staging/fbtft/Kconfig +index 4d29e8c1014..265c7e3fe76 100644 +--- a/drivers/staging/fbtft/Kconfig ++++ b/drivers/staging/fbtft/Kconfig +@@ -82,6 +82,12 @@ config FB_TFT_ILI9481 + help + Generic Framebuffer support for ILI9481 + ++config FB_TFT_ST7796 ++ tristate "FB driver for the ST7796 LCD Controller" ++ depends on FB_TFT ++ help ++ Generic Framebuffer support for ST7796 ++ + config FB_TFT_ILI9486 + tristate "FB driver for the ILI9486 LCD Controller" + depends on FB_TFT +diff --git a/drivers/staging/fbtft/Makefile b/drivers/staging/fbtft/Makefile +index e9cdf0f0a7d..3c62b33e596 100644 +--- a/drivers/staging/fbtft/Makefile ++++ b/drivers/staging/fbtft/Makefile +@@ -16,6 +16,7 @@ obj-$(CONFIG_FB_TFT_ILI9325) += fb_ili9325.o + obj-$(CONFIG_FB_TFT_ILI9340) += fb_ili9340.o + obj-$(CONFIG_FB_TFT_ILI9341) += fb_ili9341.o + obj-$(CONFIG_FB_TFT_ILI9481) += fb_ili9481.o ++obj-$(CONFIG_FB_TFT_ST7796) += fb_st7796.o + obj-$(CONFIG_FB_TFT_ILI9486) += fb_ili9486.o + obj-$(CONFIG_FB_TFT_PCD8544) += fb_pcd8544.o + obj-$(CONFIG_FB_TFT_RA8875) += fb_ra8875.o +diff --git a/drivers/staging/fbtft/fb_st7796.c b/drivers/staging/fbtft/fb_st7796.c +new file mode 100755 +index 00000000000..c7deedbea69 +--- /dev/null ++++ b/drivers/staging/fbtft/fb_st7796.c +@@ -0,0 +1,160 @@ ++// SPDX-License-Identifier: GPL-2.0+ ++/* ++ * FB driver for the ST7796 LCD display controller ++ * ++ * Based on ILI9486 from Christian Vogelgsang and adafruit22fb.c by Noralf Tronnes. ++ */ ++ ++#include ++#include ++#include ++#include ++#include