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Next186Simple.gprj
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Next186Simple.gprj
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<?xml version="1" encoding="UTF-8"?>
<!DOCTYPE gowin-fpga-project>
<Project>
<Template>FPGA</Template>
<Version>5</Version>
<Device name="GW2AR-18C" pn="GW2AR-LV18QN88C8/I7">gw2ar18c-000</Device>
<FileList>
<File path="src/DSP32.v" type="file.verilog" enable="1"/>
<File path="src/KB_8042.v" type="file.verilog" enable="1"/>
<File path="src/Nano20k_top.v" type="file.verilog" enable="1"/>
<File path="src/Next186/Next186_ALU.v" type="file.verilog" enable="1"/>
<File path="src/Next186/Next186_BIU_2T_delayread.v" type="file.verilog" enable="1"/>
<File path="src/Next186/Next186_CPU.v" type="file.verilog" enable="1"/>
<File path="src/Next186/Next186_Regs.v" type="file.verilog" enable="1"/>
<File path="src/PIC_8259.v" type="file.verilog" enable="1"/>
<File path="src/UART_8250.v" type="file.verilog" enable="1"/>
<File path="src/cache.v" type="file.verilog" enable="1"/>
<File path="src/cache_controller.v" type="file.verilog" enable="1"/>
<File path="src/ddr_186.v" type="file.verilog" enable="1"/>
<File path="src/fifo_hs/fifo_hs.v" type="file.verilog" enable="1"/>
<File path="src/fifo_hs/fifo_hs_DSP32.v" type="file.verilog" enable="1"/>
<File path="src/fifo_hs/fifo_hs_q16.v" type="file.verilog" enable="1"/>
<File path="src/fifo_hs/fifo_hs_sndfifo.v" type="file.verilog" enable="1"/>
<File path="src/gowin_clkdiv/gowin_clkdiv.v" type="file.verilog" enable="1"/>
<File path="src/gowin_dpb/gowin_dpb12x8NibHH.v" type="file.verilog" enable="1"/>
<File path="src/gowin_dpb/gowin_dpb12x8NibHL.v" type="file.verilog" enable="1"/>
<File path="src/gowin_dpb/gowin_dpb12x8NibLH.v" type="file.verilog" enable="1"/>
<File path="src/gowin_dpb/gowin_dpb12x8NibLL.v" type="file.verilog" enable="1"/>
<File path="src/gowin_dpb/gowin_dpb_DSP32_datamem16.v" type="file.verilog" enable="1"/>
<File path="src/gowin_dpb/gowin_dpb_DSP32_instrmem.v" type="file.verilog" enable="1"/>
<File path="src/gowin_dpb/gowin_dpb_VGAFont.v" type="file.verilog" enable="1"/>
<File path="src/gowin_dpb/gowin_dpb_VGA_DAC_SRAM.v" type="file.verilog" enable="1"/>
<File path="src/gowin_rpll/gowin_rpll.v" type="file.verilog" enable="1"/>
<File path="src/gowin_rpll/gowin_rpll2.v" type="file.verilog" enable="1"/>
<File path="src/hdmi/svo_defines.vh" type="file.verilog" enable="1"/>
<File path="src/hdmi/svo_enc.v" type="file.verilog" enable="1"/>
<File path="src/hdmi/svo_hdmi_out.v" type="file.verilog" enable="1"/>
<File path="src/hdmi/svo_tcard.v" type="file.verilog" enable="1"/>
<File path="src/hdmi/svo_tmds.v" type="file.verilog" enable="1"/>
<File path="src/rs232_phy.v" type="file.verilog" enable="1"/>
<File path="src/sdram.v" type="file.verilog" enable="1"/>
<File path="src/soundwave.v" type="file.verilog" enable="1"/>
<File path="src/timer8253.v" type="file.verilog" enable="1"/>
<File path="src/unit186.v" type="file.verilog" enable="1"/>
<File path="src/vga.v" type="file.verilog" enable="1"/>
<File path="src/Nano20.cst" type="file.cst" enable="1"/>
<File path="src/GeneralTimings.sdc" type="file.sdc" enable="1"/>
</FileList>
</Project>