VEX/XOP/EVEX support

[DankRank]

I kinda assumed that 32-bit didn't support these, but turns out those extra register bits are inverted for a reason: if you stick to the first eight registers, the instructions (LDS, LES, BOUND) will always have 11xxxxxx in the mod/rm byte, which is illegal, since all of these operate on memory only. Thus IA-32 does support (E)VEX prefixes.

I don't think this is much of an issue, since by the time AVX becomes old enough to actually be used by anyone, people will stop targeting IA-32, and switch to AMD64 (see #1, the need to support VEX is actually part of the reason why I initially limited the scope to IA-32).

[DankRank]

TIL MVEX is a thing

[DankRank]

Intel made too many names for the same things

• Larrabee, L1OM, LRBni
• Knights Corner, MVEX, K1OM, Intel IMCI, Intel MIC

The former I won't be supporting, since it clashes with MVEX/EVEX, and it's only ever been available in prototype chips. (for similar reasons I won't support AMD's SSE5/DEX either)

IMCI/MVEX was only ever available in 1st Gen Xeon Phi, after that it was replaced by AVX-512. I'm not sure whether I'll implement that one or not. In any case, both l1om and k1om (327364-001) are considered separate arches from amd64, so I think it's safe to say these extensions are outside the scope of this project.

On the other hand, support for XOP (and other remnants of SSE5) would be nice and easy to implement, since it's an addon for AVX, and not a reimplementation of it.