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To make a port to ARM SVE easier in #117, the new memory allocation system should let the maximum memory alignment be a runtime variable accessed using an extern declaration in a header (not to be used before initialized!) instead of a compile time constant.
Because the new memory system has not made it into the stable branch yet, it would be best to make this change before beta version 0.3.0. SVE will probably not be the last instruction set to use variable width registers directly in hardware instructions.
Then we might as well use this to ask Intel processors for the cache line width using intrinsic functions.
The text was updated successfully, but these errors were encountered:
To make a port to ARM SVE easier in #117, the new memory allocation system should let the maximum memory alignment be a runtime variable accessed using an extern declaration in a header (not to be used before initialized!) instead of a compile time constant.
Because the new memory system has not made it into the stable branch yet, it would be best to make this change before beta version 0.3.0. SVE will probably not be the last instruction set to use variable width registers directly in hardware instructions.
Then we might as well use this to ask Intel processors for the cache line width using intrinsic functions.
The text was updated successfully, but these errors were encountered: