ArtyS7_RPU_SoC.xpr

<?xml version="1.0" encoding="UTF-8"?>
<!-- Product Version: Vivado v2018.1 (64-bit)              -->
<!--                                                         -->
<!-- Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.   -->

<Project Version="7" Minor="36" Path="C:/dev/RPU/ArtyS7-RPU-SoC/ArtyS7_RPU_SoC.xpr">
  <DefaultLaunch Dir="$PRUNDIR"/>
  <Configuration>
    <Option Name="Id" Val="58d62a35a8594acbaabe575d961a5c41"/>
    <Option Name="Part" Val="xc7s50csga324-2"/>
    <Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
    <Option Name="CompiledLibDirXSim" Val=""/>
    <Option Name="CompiledLibDirModelSim" Val="$PCACHEDIR/compile_simlib/modelsim"/>
    <Option Name="CompiledLibDirQuesta" Val="$PCACHEDIR/compile_simlib/questa"/>
    <Option Name="CompiledLibDirIES" Val="$PCACHEDIR/compile_simlib/ies"/>
    <Option Name="CompiledLibDirXcelium" Val="$PCACHEDIR/compile_simlib/xcelium"/>
    <Option Name="CompiledLibDirVCS" Val="$PCACHEDIR/compile_simlib/vcs"/>
    <Option Name="CompiledLibDirRiviera" Val="$PCACHEDIR/compile_simlib/riviera"/>
    <Option Name="CompiledLibDirActivehdl" Val="$PCACHEDIR/compile_simlib/activehdl"/>
    <Option Name="TargetLanguage" Val="VHDL"/>
    <Option Name="SimulatorLanguage" Val="VHDL"/>
    <Option Name="BoardPart" Val=""/>
    <Option Name="SourceMgmtMode" Val="None"/>
    <Option Name="ActiveSimSet" Val="sim_1"/>
    <Option Name="DefaultLib" Val="xil_defaultlib"/>
    <Option Name="ProjectType" Val="Default"/>
    <Option Name="IPOutputRepo" Val="C:/dev/RPU/ArtyS7_RPU_SoC_test/ArtyS7_RPU_SoC.cache/ip"/>
    <Option Name="IPCachePermission" Val="read"/>
    <Option Name="IPCachePermission" Val="write"/>
    <Option Name="EnableCoreContainer" Val="FALSE"/>
    <Option Name="CreateRefXciForCoreContainers" Val="FALSE"/>
    <Option Name="IPUserFilesDir" Val="$PPRDIR/../ArtyS7_RPU_SoC_test/ArtyS7_RPU_SoC.ip_user_files"/>
    <Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
    <Option Name="EnableBDX" Val="FALSE"/>
    <Option Name="DSAVendor" Val="xilinx"/>
    <Option Name="DSANumComputeUnits" Val="60"/>
    <Option Name="WTXSimLaunchSim" Val="478"/>
    <Option Name="WTModelSimLaunchSim" Val="0"/>
    <Option Name="WTQuestaLaunchSim" Val="0"/>
    <Option Name="WTIesLaunchSim" Val="0"/>
    <Option Name="WTVcsLaunchSim" Val="0"/>
    <Option Name="WTRivieraLaunchSim" Val="0"/>
    <Option Name="WTActivehdlLaunchSim" Val="0"/>
    <Option Name="WTXSimExportSim" Val="108"/>
    <Option Name="WTModelSimExportSim" Val="108"/>
    <Option Name="WTQuestaExportSim" Val="108"/>
    <Option Name="WTIesExportSim" Val="108"/>
    <Option Name="WTVcsExportSim" Val="108"/>
    <Option Name="WTRivieraExportSim" Val="108"/>
    <Option Name="WTActivehdlExportSim" Val="108"/>
    <Option Name="GenerateIPUpgradeLog" Val="TRUE"/>
    <Option Name="XSimRadix" Val="hex"/>
    <Option Name="XSimTimeUnit" Val="ns"/>
    <Option Name="XSimArrayDisplayLimit" Val="1024"/>
    <Option Name="XSimTraceLimit" Val="65536"/>
    <Option Name="SimTypes" Val="rtl"/>
  </Configuration>
  <FileSets Version="1" Minor="31">
    <FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1">
      <Filter Type="Srcs"/>
      <File Path="$PSRCDIR/sources_1/bd/clk_video/clk_video.bd">
        <FileInfo>
          <Attr Name="UsedIn" Val="synthesis"/>
          <Attr Name="UsedIn" Val="implementation"/>
          <Attr Name="UsedIn" Val="simulation"/>
        </FileInfo>
        <CompFileExtendedInfo CompFileName="clk_video.bd" FileRelPathName="ip/clk_video_clk_wiz_0_0/clk_video_clk_wiz_0_0.xci">
          <Proxy FileSetName="clk_video_clk_wiz_0_0"/>
        </CompFileExtendedInfo>
      </File>
      <File Path="$PSRCDIR/sources_1/bd/BRAM_64KB/BRAM_64KB.bd">
        <FileInfo>
          <Attr Name="UsedIn" Val="synthesis"/>
          <Attr Name="UsedIn" Val="implementation"/>
          <Attr Name="UsedIn" Val="simulation"/>
        </FileInfo>
        <CompFileExtendedInfo CompFileName="BRAM_64KB.bd" FileRelPathName="ip/BRAM_64KB_blk_mem_gen_0_0/BRAM_64KB_blk_mem_gen_0_0.xci">
          <Proxy FileSetName="BRAM_64KB_blk_mem_gen_0_0"/>
        </CompFileExtendedInfo>
      </File>
      <File Path="$PSRCDIR/sources_1/bd/clk_main/clk_main.bd">
        <FileInfo>
          <Attr Name="UsedIn" Val="synthesis"/>
          <Attr Name="UsedIn" Val="implementation"/>
          <Attr Name="UsedIn" Val="simulation"/>
        </FileInfo>
      </File>
      <File Path="$PSRCDIR/sources_1/bd/BRAM_trace/BRAM_trace.bd">
        <FileInfo>
          <Attr Name="UsedIn" Val="synthesis"/>
          <Attr Name="UsedIn" Val="implementation"/>
          <Attr Name="UsedIn" Val="simulation"/>
        </FileInfo>
        <CompFileExtendedInfo CompFileName="BRAM_trace.bd" FileRelPathName="ip/BRAM_trace_blk_mem_gen_0_0/BRAM_trace_blk_mem_gen_0_0.xci">
          <Proxy FileSetName="BRAM_trace_blk_mem_gen_0_0"/>
        </CompFileExtendedInfo>
      </File>
      <File Path="$PPRDIR/hdl/BRAM_64KB_wrapper.vhd">
        <FileInfo>
          <Attr Name="UsedIn" Val="synthesis"/>
          <Attr Name="UsedIn" Val="simulation"/>
        </FileInfo>
      </File>
      <File Path="$PSRCDIR/sources_1/imports/hdl/BRAM_trace_wrapper.vhd">
        <FileInfo>
          <Attr Name="ImportPath" Val="$PSRCDIR/sources_1/bd/BRAM_trace/hdl/BRAM_trace_wrapper.vhd"/>
          <Attr Name="ImportTime" Val="1544532577"/>
          <Attr Name="UsedIn" Val="synthesis"/>
          <Attr Name="UsedIn" Val="simulation"/>
        </FileInfo>
      </File>
      <File Path="$PPRDIR/hdl/soc/gfx/TDMS_encoder.vhd">
        <FileInfo>
          <Attr Name="Library" Val="xil_defaultlib"/>
          <Attr Name="UsedIn" Val="synthesis"/>
          <Attr Name="UsedIn" Val="simulation"/>
        </FileInfo>
      </File>
      <File Path="$PPRDIR/hdl/soc/gfx/char_generator.vhd">
        <FileInfo>
          <Attr Name="UsedIn" Val="synthesis"/>
          <Attr Name="UsedIn" Val="simulation"/>
        </FileInfo>
      </File>
      <File Path="$PSRCDIR/sources_1/imports/hdl/clk_main_wrapper.vhd">
        <FileInfo>
          <Attr Name="ImportPath" Val="$PSRCDIR/sources_1/bd/clk_main/hdl/clk_main_wrapper.vhd"/>
          <Attr Name="ImportTime" Val="1544801325"/>
          <Attr Name="UsedIn" Val="synthesis"/>
          <Attr Name="UsedIn" Val="simulation"/>
        </FileInfo>
      </File>
      <File Path="$PSRCDIR/sources_1/imports/hdl/clk_video_wrapper.vhd">
        <FileInfo>
          <Attr Name="ImportPath" Val="$PSRCDIR/sources_1/bd/clk_video/hdl/clk_video_wrapper.vhd"/>
          <Attr Name="ImportTime" Val="1544798904"/>
          <Attr Name="UsedIn" Val="synthesis"/>
          <Attr Name="UsedIn" Val="simulation"/>
        </FileInfo>
      </File>
      <File Path="$PPRDIR/RPU/vhdl/constants.vhd">
        <FileInfo>
          <Attr Name="Library" Val="xil_defaultlib"/>
          <Attr Name="UsedIn" Val="synthesis"/>
          <Attr Name="UsedIn" Val="simulation"/>
        </FileInfo>
      </File>
      <File Path="$PPRDIR/RPU/vhdl/control_unit.vhd">
        <FileInfo>
          <Attr Name="Library" Val="xil_defaultlib"/>
          <Attr Name="UsedIn" Val="synthesis"/>
          <Attr Name="UsedIn" Val="simulation"/>
        </FileInfo>
      </File>
      <File Path="$PPRDIR/RPU/vhdl/core.vhd">
        <FileInfo>
          <Attr Name="Library" Val="xil_defaultlib"/>
          <Attr Name="UsedIn" Val="synthesis"/>
          <Attr Name="UsedIn" Val="simulation"/>
        </FileInfo>
      </File>
      <File Path="$PPRDIR/RPU/vhdl/csr_unit.vhd">
        <FileInfo>
          <Attr Name="UsedIn" Val="synthesis"/>
          <Attr Name="UsedIn" Val="simulation"/>
        </FileInfo>
      </File>
      <File Path="$PPRDIR/hdl/soc/gfx/dvid.vhd">
        <FileInfo>
          <Attr Name="Library" Val="xil_defaultlib"/>
          <Attr Name="UsedIn" Val="synthesis"/>
          <Attr Name="UsedIn" Val="simulation"/>
        </FileInfo>
      </File>
      <File Path="$PPRDIR/RPU/vhdl/lint_unit.vhd">
        <FileInfo>
          <Attr Name="UsedIn" Val="synthesis"/>
          <Attr Name="UsedIn" Val="simulation"/>
        </FileInfo>
      </File>
      <File Path="$PPRDIR/RPU/vhdl/mem_controller.vhd">
        <FileInfo>
          <Attr Name="Library" Val="xil_defaultlib"/>
          <Attr Name="UsedIn" Val="synthesis"/>
          <Attr Name="UsedIn" Val="simulation"/>
        </FileInfo>
      </File>
      <File Path="$PPRDIR/RPU/vhdl/pc_unit.vhd">
        <FileInfo>
          <Attr Name="Library" Val="xil_defaultlib"/>
          <Attr Name="UsedIn" Val="synthesis"/>
          <Attr Name="UsedIn" Val="simulation"/>
        </FileInfo>
      </File>
      <File Path="$PPRDIR/RPU/vhdl/register_set.vhd">
        <FileInfo>
          <Attr Name="Library" Val="xil_defaultlib"/>
          <Attr Name="UsedIn" Val="synthesis"/>
          <Attr Name="UsedIn" Val="simulation"/>
        </FileInfo>
      </File>
      <File Path="$PPRDIR/hdl/soc/spi_master.vhd">
        <FileInfo>
          <Attr Name="Library" Val="xil_defaultlib"/>
          <Attr Name="UsedIn" Val="synthesis"/>
          <Attr Name="UsedIn" Val="simulation"/>
        </FileInfo>
      </File>
      <File Path="$PPRDIR/hdl/soc/gfx/test_font_ram.vhd">
        <FileInfo>
          <Attr Name="Library" Val="xil_defaultlib"/>
          <Attr Name="UsedIn" Val="synthesis"/>
          <Attr Name="UsedIn" Val="simulation"/>
        </FileInfo>
      </File>
      <File Path="$PPRDIR/hdl/xilinx/uart_rx6.vhd">
        <FileInfo>
          <Attr Name="UsedIn" Val="synthesis"/>
          <Attr Name="UsedIn" Val="simulation"/>
        </FileInfo>
      </File>
      <File Path="$PPRDIR/RPU/vhdl/unit_alu_RV32_I.vhd">
        <FileInfo>
          <Attr Name="Library" Val="xil_defaultlib"/>
          <Attr Name="UsedIn" Val="synthesis"/>
          <Attr Name="UsedIn" Val="simulation"/>
        </FileInfo>
      </File>
      <File Path="$PPRDIR/RPU/vhdl/unit_decoder_RV32I.vhd">
        <FileInfo>
          <Attr Name="Library" Val="xil_defaultlib"/>
          <Attr Name="UsedIn" Val="synthesis"/>
          <Attr Name="UsedIn" Val="simulation"/>
        </FileInfo>
      </File>
      <File Path="$PPRDIR/hdl/soc/gfx/vga_gen.vhd">
        <FileInfo>
          <Attr Name="UsedIn" Val="synthesis"/>
          <Attr Name="UsedIn" Val="simulation"/>
        </FileInfo>
      </File>
      <File Path="$PPRDIR/hdl/rpu_top.vhd">
        <FileInfo>
          <Attr Name="UsedIn" Val="synthesis"/>
          <Attr Name="UsedIn" Val="simulation"/>
        </FileInfo>
      </File>
      <File Path="$PPRDIR/hdl/soc/clocking.vhd">
        <FileInfo>
          <Attr Name="UsedIn" Val="synthesis"/>
          <Attr Name="UsedIn" Val="simulation"/>
        </FileInfo>
      </File>
      <File Path="$PPRDIR/rom/coe/bootloader.coe">
        <FileInfo>
          <Attr Name="UsedIn" Val="synthesis"/>
          <Attr Name="UsedIn" Val="simulation"/>
        </FileInfo>
      </File>
      <File Path="$PSRCDIR/sources_1/ip/mig_7series_0/mig_a.prj">
        <FileInfo>
          <Attr Name="UsedIn" Val="synthesis"/>
          <Attr Name="ScopedToCell" Val="mig_7series_0"/>
          <Attr Name="ScopedToCell" Val="mig_7series_0"/>
        </FileInfo>
      </File>
      <File Path="$PSRCDIR/sources_1/imports/RPU/vivado/rom/coe/bootloader.coe">
        <FileInfo>
          <Attr Name="UsedIn" Val="synthesis"/>
          <Attr Name="UsedIn" Val="simulation"/>
        </FileInfo>
      </File>
      <File Path="$PPRDIR/hdl/cache.vhd">
        <FileInfo>
          <Attr Name="UsedIn" Val="synthesis"/>
          <Attr Name="UsedIn" Val="simulation"/>
        </FileInfo>
      </File>
      <File Path="$PPRDIR/RPU/vhdl/alu_int32_div.vhd">
        <FileInfo>
          <Attr Name="UsedIn" Val="synthesis"/>
          <Attr Name="UsedIn" Val="simulation"/>
        </FileInfo>
      </File>
      <File Path="$PSRCDIR/sources_1/bd/BRAM_cache/BRAM_cache.bd">
        <FileInfo>
          <Attr Name="UsedIn" Val="synthesis"/>
          <Attr Name="UsedIn" Val="implementation"/>
          <Attr Name="UsedIn" Val="simulation"/>
        </FileInfo>
        <CompFileExtendedInfo CompFileName="BRAM_cache.bd" FileRelPathName="ip/BRAM_cache_blk_mem_gen_0_0/BRAM_cache_blk_mem_gen_0_0.xci">
          <Proxy FileSetName="BRAM_cache_blk_mem_gen_0_0"/>
        </CompFileExtendedInfo>
      </File>
      <File Path="$PSRCDIR/sources_1/bd/BRAM_cache/hdl/BRAM_cache_wrapper.vhd">
        <FileInfo>
          <Attr Name="UsedIn" Val="synthesis"/>
          <Attr Name="UsedIn" Val="simulation"/>
        </FileInfo>
      </File>
      <Config>
        <Option Name="DesignMode" Val="RTL"/>
        <Option Name="TopModule" Val="rpu_top"/>
      </Config>
    </FileSet>
    <FileSet Name="constrs_1" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1">
      <Filter Type="Constrs"/>
      <File Path="$PSRCDIR/constrs_1/imports/Arty-S7-50-Rev-B-Master.xdc">
        <FileInfo>
          <Attr Name="UsedIn" Val="synthesis"/>
          <Attr Name="UsedIn" Val="implementation"/>
        </FileInfo>
      </File>
      <Config>
        <Option Name="TargetConstrsFile" Val="$PSRCDIR/constrs_1/imports/Arty-S7-50-Rev-B-Master.xdc"/>
        <Option Name="ConstrsType" Val="XDC"/>
      </Config>
    </FileSet>
    <FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1">
      <Filter Type="Srcs"/>
      <File Path="$PPRDIR/RPU/tests/rpu_core_tb.vhd">
        <FileInfo>
          <Attr Name="UsedIn" Val="synthesis"/>
          <Attr Name="UsedIn" Val="simulation"/>
        </FileInfo>
      </File>
      <File Path="$PPRDIR/rpu_core_tb_behav1.wcfg">
        <FileInfo>
          <Attr Name="UsedIn" Val="simulation"/>
        </FileInfo>
      </File>
      <File Path="$PPRDIR/hdl/test/cache_tb.vhd">
        <FileInfo>
          <Attr Name="UsedIn" Val="synthesis"/>
          <Attr Name="UsedIn" Val="simulation"/>
        </FileInfo>
      </File>
      <File Path="$PPRDIR/hdl/test/rpu_top_test.vhd">
        <FileInfo>
          <Attr Name="UsedIn" Val="synthesis"/>
          <Attr Name="UsedIn" Val="simulation"/>
        </FileInfo>
      </File>
      <File Path="$PPRDIR/RPU/tests/tb_alu_int32_div.vhd">
        <FileInfo>
          <Attr Name="UsedIn" Val="synthesis"/>
          <Attr Name="UsedIn" Val="simulation"/>
        </FileInfo>
      </File>
      <Config>
        <Option Name="DesignMode" Val="RTL"/>
        <Option Name="TopModule" Val="rpu_core_tb"/>
        <Option Name="TopLib" Val="xil_defaultlib"/>
        <Option Name="TransportPathDelay" Val="0"/>
        <Option Name="TransportIntDelay" Val="0"/>
        <Option Name="SrcSet" Val="sources_1"/>
        <Option Name="XSimWcfgFile" Val="$PPRDIR/tb_core_01_behav.wcfg"/>
        <Option Name="XSimWcfgFile" Val="$PPRDIR/rpu_core_tb_behav.wcfg"/>
        <Option Name="XSimWcfgFile" Val="$PPRDIR/rpu_core_tb_behav1.wcfg"/>
        <Option Name="xsim.simulate.runtime" Val="22020ns"/>
        <Option Name="NGOutputHDLFormat" Val="vhdl"/>
        <Option Name="NLNetlistMode" Val="funcsim"/>
      </Config>
    </FileSet>
    <FileSet Name="mig_7series_0" Type="BlockSrcs" RelSrcDir="$PSRCDIR/mig_7series_0">
      <File Path="$PSRCDIR/sources_1/ip/mig_7series_0/mig_7series_0.xci">
        <FileInfo>
          <Attr Name="UsedIn" Val="synthesis"/>
          <Attr Name="UsedIn" Val="implementation"/>
          <Attr Name="UsedIn" Val="simulation"/>
        </FileInfo>
      </File>
      <Config>
        <Option Name="TopModule" Val="mig_7series_0"/>
        <Option Name="UseBlackboxStub" Val="1"/>
      </Config>
    </FileSet>
    <FileSet Name="BRAM_64KB_blk_mem_gen_0_0" Type="BlockSrcs" RelSrcDir="$PSRCDIR/BRAM_64KB_blk_mem_gen_0_0">
      <Config>
        <Option Name="TopModule" Val="BRAM_64KB_blk_mem_gen_0_0"/>
        <Option Name="UseBlackboxStub" Val="1"/>
      </Config>
    </FileSet>
    <FileSet Name="BRAM_trace_blk_mem_gen_0_0" Type="BlockSrcs" RelSrcDir="$PSRCDIR/BRAM_trace_blk_mem_gen_0_0">
      <Config>
        <Option Name="TopModule" Val="BRAM_trace_blk_mem_gen_0_0"/>
        <Option Name="UseBlackboxStub" Val="1"/>
      </Config>
    </FileSet>
    <FileSet Name="clk_video_clk_wiz_0_0" Type="BlockSrcs" RelSrcDir="$PSRCDIR/clk_video_clk_wiz_0_0">
      <Config>
        <Option Name="TopModule" Val="clk_video_clk_wiz_0_0"/>
        <Option Name="UseBlackboxStub" Val="1"/>
      </Config>
    </FileSet>
    <FileSet Name="BRAM_cache_blk_mem_gen_0_0" Type="BlockSrcs" RelSrcDir="$PSRCDIR/BRAM_cache_blk_mem_gen_0_0">
      <Config>
        <Option Name="TopModule" Val="BRAM_cache_blk_mem_gen_0_0"/>
        <Option Name="UseBlackboxStub" Val="1"/>
      </Config>
    </FileSet>
  </FileSets>
  <Simulators>
    <Simulator Name="XSim">
      <Option Name="Description" Val="Vivado Simulator"/>
      <Option Name="CompiledLib" Val="0"/>
    </Simulator>
    <Simulator Name="ModelSim">
      <Option Name="Description" Val="ModelSim Simulator"/>
    </Simulator>
    <Simulator Name="Questa">
      <Option Name="Description" Val="Questa Advanced Simulator"/>
    </Simulator>
    <Simulator Name="Riviera">
      <Option Name="Description" Val="Riviera-PRO Simulator"/>
    </Simulator>
    <Simulator Name="ActiveHDL">
      <Option Name="Description" Val="Active-HDL Simulator"/>
    </Simulator>
  </Simulators>
  <Runs Version="1" Minor="10">
    <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7s50csga324-2" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/synth_1" IncludeInArchive="true">
      <Strategy Version="1" Minor="2">
        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2018"/>
        <Step Id="synth_design"/>
      </Strategy>
      <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
      <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2018"/>
      <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
    </Run>
    <Run Id="mig_7series_0_synth_1" Type="Ft3:Synth" SrcSet="mig_7series_0" Part="xc7s50csga324-2" ConstrsSet="mig_7series_0" Description="Vivado Synthesis Defaults" WriteIncrSynthDcp="false" Dir="$PRUNDIR/mig_7series_0_synth_1" IncludeInArchive="true">
      <Strategy Version="1" Minor="2">
        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2018"/>
        <Step Id="synth_design"/>
      </Strategy>
      <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
      <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2018"/>
      <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
    </Run>
    <Run Id="BRAM_64KB_blk_mem_gen_0_0_synth_1" Type="Ft3:Synth" SrcSet="BRAM_64KB_blk_mem_gen_0_0" Part="xc7s50csga324-2" ConstrsSet="BRAM_64KB_blk_mem_gen_0_0" Description="Vivado Synthesis Defaults" WriteIncrSynthDcp="false" Dir="$PRUNDIR/BRAM_64KB_blk_mem_gen_0_0_synth_1" IncludeInArchive="true">
      <Strategy Version="1" Minor="2">
        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2018"/>
        <Step Id="synth_design"/>
      </Strategy>
      <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
      <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2018"/>
      <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
    </Run>
    <Run Id="BRAM_trace_blk_mem_gen_0_0_synth_1" Type="Ft3:Synth" SrcSet="BRAM_trace_blk_mem_gen_0_0" Part="xc7s50csga324-2" ConstrsSet="BRAM_trace_blk_mem_gen_0_0" Description="Vivado Synthesis Defaults" WriteIncrSynthDcp="false" Dir="$PRUNDIR/BRAM_trace_blk_mem_gen_0_0_synth_1" IncludeInArchive="true">
      <Strategy Version="1" Minor="2">
        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2018"/>
        <Step Id="synth_design"/>
      </Strategy>
      <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
      <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2018"/>
      <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
    </Run>
    <Run Id="clk_video_clk_wiz_0_0_synth_1" Type="Ft3:Synth" SrcSet="clk_video_clk_wiz_0_0" Part="xc7s50csga324-2" ConstrsSet="clk_video_clk_wiz_0_0" Description="Vivado Synthesis Defaults" WriteIncrSynthDcp="false" Dir="$PRUNDIR/clk_video_clk_wiz_0_0_synth_1" IncludeInArchive="true">
      <Strategy Version="1" Minor="2">
        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2018"/>
        <Step Id="synth_design"/>
      </Strategy>
      <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
      <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2018"/>
      <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
    </Run>
    <Run Id="BRAM_cache_blk_mem_gen_0_0_synth_1" Type="Ft3:Synth" SrcSet="BRAM_cache_blk_mem_gen_0_0" Part="xc7s50csga324-2" ConstrsSet="BRAM_cache_blk_mem_gen_0_0" Description="Vivado Synthesis Defaults" WriteIncrSynthDcp="false" Dir="$PRUNDIR/BRAM_cache_blk_mem_gen_0_0_synth_1" IncludeInArchive="true">
      <Strategy Version="1" Minor="2">
        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2018"/>
        <Step Id="synth_design"/>
      </Strategy>
      <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
      <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2018"/>
      <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
    </Run>
    <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7s50csga324-2" ConstrsSet="constrs_1" Description="Default settings for Implementation." WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/impl_1" SynthRun="synth_1" IncludeInArchive="true">
      <Strategy Version="1" Minor="2">
        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2018"/>
        <Step Id="init_design"/>
        <Step Id="opt_design"/>
        <Step Id="power_opt_design"/>
        <Step Id="place_design"/>
        <Step Id="post_place_power_opt_design"/>
        <Step Id="phys_opt_design"/>
        <Step Id="route_design"/>
        <Step Id="post_route_phys_opt_design"/>
        <Step Id="write_bitstream"/>
      </Strategy>
      <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
      <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2018"/>
      <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
    </Run>
    <Run Id="mig_7series_0_impl_1" Type="Ft2:EntireDesign" Part="xc7s50csga324-2" ConstrsSet="mig_7series_0" Description="Default settings for Implementation." WriteIncrSynthDcp="false" SynthRun="mig_7series_0_synth_1" IncludeInArchive="false">
      <Strategy Version="1" Minor="2">
        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2018"/>
        <Step Id="init_design"/>
        <Step Id="opt_design"/>
        <Step Id="power_opt_design"/>
        <Step Id="place_design"/>
        <Step Id="post_place_power_opt_design"/>
        <Step Id="phys_opt_design"/>
        <Step Id="route_design"/>
        <Step Id="post_route_phys_opt_design"/>
        <Step Id="write_bitstream"/>
      </Strategy>
      <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2018"/>
      <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
    </Run>
    <Run Id="BRAM_64KB_blk_mem_gen_0_0_impl_1" Type="Ft2:EntireDesign" Part="xc7s50csga324-2" ConstrsSet="BRAM_64KB_blk_mem_gen_0_0" Description="Default settings for Implementation." WriteIncrSynthDcp="false" SynthRun="BRAM_64KB_blk_mem_gen_0_0_synth_1" IncludeInArchive="false">
      <Strategy Version="1" Minor="2">
        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2018"/>
        <Step Id="init_design"/>
        <Step Id="opt_design"/>
        <Step Id="power_opt_design"/>
        <Step Id="place_design"/>
        <Step Id="post_place_power_opt_design"/>
        <Step Id="phys_opt_design"/>
        <Step Id="route_design"/>
        <Step Id="post_route_phys_opt_design"/>
        <Step Id="write_bitstream"/>
      </Strategy>
      <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2018"/>
      <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
    </Run>
    <Run Id="BRAM_trace_blk_mem_gen_0_0_impl_1" Type="Ft2:EntireDesign" Part="xc7s50csga324-2" ConstrsSet="BRAM_trace_blk_mem_gen_0_0" Description="Default settings for Implementation." WriteIncrSynthDcp="false" SynthRun="BRAM_trace_blk_mem_gen_0_0_synth_1" IncludeInArchive="false">
      <Strategy Version="1" Minor="2">
        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2018"/>
        <Step Id="init_design"/>
        <Step Id="opt_design"/>
        <Step Id="power_opt_design"/>
        <Step Id="place_design"/>
        <Step Id="post_place_power_opt_design"/>
        <Step Id="phys_opt_design"/>
        <Step Id="route_design"/>
        <Step Id="post_route_phys_opt_design"/>
        <Step Id="write_bitstream"/>
      </Strategy>
      <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2018"/>
      <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
    </Run>
    <Run Id="clk_video_clk_wiz_0_0_impl_1" Type="Ft2:EntireDesign" Part="xc7s50csga324-2" ConstrsSet="clk_video_clk_wiz_0_0" Description="Default settings for Implementation." WriteIncrSynthDcp="false" SynthRun="clk_video_clk_wiz_0_0_synth_1" IncludeInArchive="false">
      <Strategy Version="1" Minor="2">
        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2018"/>
        <Step Id="init_design"/>
        <Step Id="opt_design"/>
        <Step Id="power_opt_design"/>
        <Step Id="place_design"/>
        <Step Id="post_place_power_opt_design"/>
        <Step Id="phys_opt_design"/>
        <Step Id="route_design"/>
        <Step Id="post_route_phys_opt_design"/>
        <Step Id="write_bitstream"/>
      </Strategy>
      <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2018"/>
      <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
    </Run>
    <Run Id="BRAM_cache_blk_mem_gen_0_0_impl_1" Type="Ft2:EntireDesign" Part="xc7s50csga324-2" ConstrsSet="BRAM_cache_blk_mem_gen_0_0" Description="Default settings for Implementation." WriteIncrSynthDcp="false" SynthRun="BRAM_cache_blk_mem_gen_0_0_synth_1" IncludeInArchive="false">
      <Strategy Version="1" Minor="2">
        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2018"/>
        <Step Id="init_design"/>
        <Step Id="opt_design"/>
        <Step Id="power_opt_design"/>
        <Step Id="place_design"/>
        <Step Id="post_place_power_opt_design"/>
        <Step Id="phys_opt_design"/>
        <Step Id="route_design"/>
        <Step Id="post_route_phys_opt_design"/>
        <Step Id="write_bitstream"/>
      </Strategy>
      <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2018"/>
      <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
    </Run>
  </Runs>
  <Board/>
</Project>