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Fix for simulation fail caused by VCS directives in Vivado #1

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YijunLi-FiM opened this issue Jan 29, 2022 · 0 comments
Open

Fix for simulation fail caused by VCS directives in Vivado #1

YijunLi-FiM opened this issue Jan 29, 2022 · 0 comments

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@YijunLi-FiM
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Referencing a similar issue, code block using VCS directives should be surrounded with ifdef VCS ... endif, and current simulation harness only considered Iverilog | VCS setup.
For instance, in lab2/sim/adder_testbench.v:22, ifndef IVERILOG should be ifdef VCS.
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@YijunLi-FiM