diff --git a/gcc/common/config/tricore/tricore-common.c b/gcc/common/config/tricore/tricore-common.c index 4d76f373611..7a400b1e2d1 100644 --- a/gcc/common/config/tricore/tricore-common.c +++ b/gcc/common/config/tricore/tricore-common.c @@ -137,12 +137,24 @@ tric_opt_error (int value, const char *op1, const char *op2, location_t loc) } - +/* + Configures options for the specific devices. For example, tc45xx shall have soft double precision hardware by default +*/ +void tric_configure_options_for_device(const char *name, struct gcc_options *opts) +{ + const char* tc45xx = "tc45xx"; + if(name + && 0 == strcmp (name, tc45xx)) + { + //By default, tc45xx shall have soft double precision operations + opts->x_target_flags |= MASK_DP_SOFT_FLOAT; + } +} /* Implement `TARGET_HANDLE_OPTION' */ static bool -tric_handle_option (struct gcc_options *opts ATTRIBUTE_UNUSED, +tric_handle_option (struct gcc_options *opts, struct gcc_options *opts_set ATTRIBUTE_UNUSED, const struct cl_decoded_option *decoded, location_t loc) { @@ -237,6 +249,7 @@ tric_handle_option (struct gcc_options *opts ATTRIBUTE_UNUSED, case OPT_mcpu_: tric_set_device (arg); + tric_configure_options_for_device(arg, opts); return true; case OPT_mtc: diff --git a/gcc/config/tricore/devices.def b/gcc/config/tricore/devices.def index 2cddfbdf883..9a304db9aa9 100644 --- a/gcc/config/tricore/devices.def +++ b/gcc/config/tricore/devices.def @@ -78,5 +78,9 @@ DEF_DEVICE ("tc2d5d", "0x2d5d", "161", "tc161") DEF_DEVICE ("tc33xx", "0x3300", "162", "tc162") DEF_DEVICE ("tc38xx", "0x3800", "162", "tc162") /* since v4.9.1.0-infineon-2.0 */ DEF_DEVICE ("tc39xx", "0x3900", "162", "tc162") /* since v4.6.6.0 */ -DEF_DEVICE ("tc49Ax", "0x4900", "18", "tc18") /* updated */ -DEF_DEVICE ("tc4DAx", "0x4D00", "18", "tc18") /* updated */ +DEF_DEVICE ("tc49Ax", "0x49A0", "18", "tc18") +DEF_DEVICE ("tc4DAx", "0x4D00", "18", "tc18") +DEF_DEVICE ("tc49xx", "0x4900", "18", "tc18") +DEF_DEVICE ("tc48xx", "0x4800", "18", "tc18") +DEF_DEVICE ("tc46xx", "0x4600", "18", "tc18") +DEF_DEVICE ("tc45xx", "0x4500", "18", "tc18") diff --git a/gcc/config/tricore/memory.x b/gcc/config/tricore/memory.x index 45706f376ca..01f8dfefe40 100644 --- a/gcc/config/tricore/memory.x +++ b/gcc/config/tricore/memory.x @@ -1064,7 +1064,7 @@ __ISTACK_SIZE = 256; __HEAP_MIN = 8K; __CSA_SIZE = 16K; -#elif __TRICORE_NAME__ == 0x4900 +#elif __TRICORE_NAME__ == 0x49A0 #define __MESSAGE__ "Using wrong Memory Map. This Map is for TC49Ax" #define I_C_F_B 0x80000000 #define I_C_F_S 4M @@ -1097,10 +1097,191 @@ __CSA_SIZE = 16K; #define P_D_R_B 0 #define P_D_R_S 0 -__USTACK_SIZE = 4K; -__ISTACK_SIZE = 256; -__HEAP_MIN = 8K; -__CSA_SIZE = 16K; +/* Values taken from TC4 iLLDs */ +__USTACK_SIZE = 2K; +__ISTACK_SIZE = 1k; +__HEAP_MIN = 4K; +__CSA_SIZE = 8K; + +#elif __TRICORE_NAME__ == 0x4900 +#define __MESSAGE__ "Using wrong Memory Map. This Map is for TC49xx" +#define I_C_F_B 0x80000000 +#define I_C_F_S 4M +#define I_C_F_B_0 0x80000000 +#define I_C_F_S_0 4M +#define I_C_F_B_1 0x80400000 +#define I_C_F_S_1 4M +#define I_C_F_B_2 0x80800000 +#define I_C_F_S_2 4M +#define I_C_F_B_3 0x80C00000 +#define I_C_F_S_3 4M +#define I_C_F_B_4 0x81000000 +#define I_C_F_S_4 4M +#define I_D_F_B 0xAE000000 +#define I_D_F_S 1M +#define I_D_F_B_0 0xAE000000 +#define I_D_F_S_0 1M +#define E_C_R_B 0 +#define E_C_R_S 0 +#define E_D_R_B 0 +#define E_D_R_S 0 +#define I_C_R_B 0xC0000000 +#define I_C_R_S 64K +#define I_D_R_B 0xD0000000 +#define I_D_R_S 240K +#define P_C_R_B 0 +#define P_C_R_S 0 +#define P_D_R_B 0 +#define P_D_R_S 0 + +/* Values taken from TC4 iLLDs */ +__USTACK_SIZE = 2K; +__ISTACK_SIZE = 1k; +__HEAP_MIN = 4K; +__CSA_SIZE = 8K; + +#elif __TRICORE_NAME__ == 0x4D00 +#define __MESSAGE__ "Using wrong Memory Map. This Map is for TC4Dxx" +#define I_C_F_B 0x80000000 +#define I_C_F_S 4M +#define I_C_F_B_0 0x80000000 +#define I_C_F_S_0 4M +#define I_C_F_B_1 0x80400000 +#define I_C_F_S_1 4M +#define I_C_F_B_2 0x80800000 +#define I_C_F_S_2 2M +#define I_C_F_B_3 0x80A00000 +#define I_C_F_S_3 4M +#define I_C_F_B_4 0x80E00000 +#define I_C_F_S_4 4M +#define I_C_F_B_5 0x81200000 +#define I_C_F_S_5 2M +#define I_D_F_B 0xAE000000 +#define I_D_F_S 1M +#define I_D_F_B_0 0xAE000000 +#define I_D_F_S_0 1M +#define E_C_R_B 0 +#define E_C_R_S 0 +#define E_D_R_B 0 +#define E_D_R_S 0 +#define I_C_R_B 0xC0000000 +#define I_C_R_S 64K +#define I_D_R_B 0xD0000000 +#define I_D_R_S 240K +#define P_C_R_B 0 +#define P_C_R_S 0 +#define P_D_R_B 0 +#define P_D_R_S 0 + +/* Values taken from TC4 iLLDs */ +__USTACK_SIZE = 2K; +__ISTACK_SIZE = 1k; +__HEAP_MIN = 4K; +__CSA_SIZE = 8K; + + +#elif __TRICORE_NAME__ == 0x4800 +#define __MESSAGE__ "Using wrong Memory Map. This Map is for TC48xx" +#define I_C_F_B 0x80000000 +#define I_C_F_S 4M +#define I_C_F_B_0 0x80000000 +#define I_C_F_S_0 4M +#define I_C_F_B_1 0x80400000 +#define I_C_F_S_1 4M +#define I_C_F_B_2 0x80800000 +#define I_C_F_S_2 4M +#define I_C_F_B_3 0x80C00000 +#define I_C_F_S_3 4M +#define I_D_F_B 0xAE000000 +#define I_D_F_S 256K +#define I_D_F_B_0 0xAE000000 +#define I_D_F_S_0 256K +#define E_C_R_B 0 +#define E_C_R_S 0 +#define E_D_R_B 0 +#define E_D_R_S 0 +#define I_C_R_B 0xC0000000 +#define I_C_R_S 64K +#define I_D_R_B 0xD0000000 +#define I_D_R_S 240K +#define P_C_R_B 0 +#define P_C_R_S 0 +#define P_D_R_B 0 +#define P_D_R_S 0 + +/* Values taken from TC4 iLLDs */ +__USTACK_SIZE = 2K; +__ISTACK_SIZE = 1k; +__HEAP_MIN = 4K; +__CSA_SIZE = 8K; + + +#elif __TRICORE_NAME__ == 0x4600 +#define __MESSAGE__ "Using wrong Memory Map. This Map is for TC46xx" +#define I_C_F_B 0x80000000 +#define I_C_F_S 4M +#define I_C_F_B_0 0x80000000 +#define I_C_F_S_0 4M +#define I_C_F_B_1 0x80400000 +#define I_C_F_S_1 4M +#define I_C_F_B_2 0x80800000 +#define I_C_F_S_2 2M +#define I_C_F_B_3 0x80A00000 +#define I_C_F_S_3 2M +#define I_D_F_B 0xAE000000 +#define I_D_F_S 512K +#define I_D_F_B_0 0xAE000000 +#define I_D_F_S_0 512K +#define E_C_R_B 0 +#define E_C_R_S 0 +#define E_D_R_B 0 +#define E_D_R_S 0 +#define I_C_R_B 0xC0000000 +#define I_C_R_S 64K +#define I_D_R_B 0xD0000000 +#define I_D_R_S 240K +#define P_C_R_B 0 +#define P_C_R_S 0 +#define P_D_R_B 0 +#define P_D_R_S 0 + +/* Values taken from TC4 iLLDs */ +__USTACK_SIZE = 2K; +__ISTACK_SIZE = 1k; +__HEAP_MIN = 4K; +__CSA_SIZE = 8K; + + +#elif __TRICORE_NAME__ == 0x4500 +#define __MESSAGE__ "Using wrong Memory Map. This Map is for TC45xx" +#define I_C_F_B 0x80000000 +#define I_C_F_S 2M +#define I_C_F_B_0 0x80000000 +#define I_C_F_S_0 2M +#define I_C_F_B_1 0x80200000 +#define I_C_F_S_1 2M +#define I_D_F_B 0xAE000000 +#define I_D_F_S 64K +#define I_D_F_B_0 0xAE000000 +#define I_D_F_S_0 64K +#define E_C_R_B 0 +#define E_C_R_S 0 +#define E_D_R_B 0 +#define E_D_R_S 0 +#define I_C_R_B 0xC0000000 +#define I_C_R_S 32K +#define I_D_R_B 0xD0000000 +#define I_D_R_S 240K +#define P_C_R_B 0 +#define P_C_R_S 0 +#define P_D_R_B 0 +#define P_D_R_S 0 + +/* Values taken from TC4 iLLDs */ +__USTACK_SIZE = 2K; +__ISTACK_SIZE = 1k; +__HEAP_MIN = 4K; +__CSA_SIZE = 8K; #endif diff --git a/gcc/config/tricore/t-multilib b/gcc/config/tricore/t-multilib index 628fce6d751..f9f0b9693db 100644 --- a/gcc/config/tricore/t-multilib +++ b/gcc/config/tricore/t-multilib @@ -59,6 +59,10 @@ MULTILIB_MATCHES = \ mtc162=mcpu?tc38xx \ mtc162=mcpu?tc39xx \ mtc18=mcpu?tc49Ax \ - mtc18=mcpu?tc4DAx + mtc18=mcpu?tc4DAx \ + mtc18=mcpu?tc49xx \ + mtc18=mcpu?tc48xx \ + mtc18=mcpu?tc46xx \ + mtc18=mcpu?tc45xx -TRIC_DEVICES = tc1796 tc1130 tc116x tc1161 tc1162 tc1762 tc1764 tc1766 tc1792 tc1920 tc1167 tc1197 tc1337 tc1367 tc1387 tc1724 tc1728 tc1736 tc1767 tc1782 tc1783 tc1784 tc1797 tc1791 tc1793 tc1798 tc22xx tc23xx tc26xx tc27xx tc29xx tc2d5d tc33xx tc38xx tc39xx tc49Ax tc4DAx +TRIC_DEVICES = tc1796 tc1130 tc116x tc1161 tc1162 tc1762 tc1764 tc1766 tc1792 tc1920 tc1167 tc1197 tc1337 tc1367 tc1387 tc1724 tc1728 tc1736 tc1767 tc1782 tc1783 tc1784 tc1797 tc1791 tc1793 tc1798 tc22xx tc23xx tc26xx tc27xx tc29xx tc2d5d tc33xx tc38xx tc39xx tc49Ax tc4DAx tc49xx tc48xx tc46xx tc45xx diff --git a/gcc/config/tricore/t-tricore b/gcc/config/tricore/t-tricore index 5ea8b2c5de2..76586fb47ff 100644 --- a/gcc/config/tricore/t-tricore +++ b/gcc/config/tricore/t-tricore @@ -43,12 +43,20 @@ install-devices: installdirs $(MEMORY_CPU) $(CRT0_CPU) $(CRT0_S) crti.S crtn.S $(INSTALL_DATA) crt0-tc1x.S $(DESTDIR)$(libsubdir) $(INSTALL_DATA) crt0-tc2x.S $(DESTDIR)$(libsubdir) -MULTILIB_OPTIONS = mtc131/mtc16/mtc161/mtc162/mtc18 fshort-double -MULTILIB_DIRNAMES = tc131 tc16 tc161 tc162 tc18 short-double +MULTILIB_OPTIONS = mtc131/mtc16/mtc161/mtc162/mtc18 fshort-double msoft-sp-float msoft-dp-float +MULTILIB_DIRNAMES = tc131 tc16 tc161 tc162 tc18 short-double soft-single-float soft-double-float #MULTILIB_OPTIONS = mtc161 fshort-double #MULTILIB_DIRNAMES = tc161 short-double MULTILIB_EXCEPTIONS = +# a library with msoft-sp-float without any device specified is not interesting +MULTILIB_EXCEPTIONS += msoft-sp-float* +# a library with msoft-dp-float without any device specified is not interesting +MULTILIB_EXCEPTIONS += msoft-dp-float* +# msoft-dp-float makes no sense for tc131, which doesn't have a dp float hardware to disable +MULTILIB_EXCEPTIONS += mtc131/msoft-dp-float +# msoft-dp-float makes no sense for tc16*, which doesn't have a dp float hardware to disable +MULTILIB_EXCEPTIONS += mtc16*/msoft-dp-float # MULTILIB_MATCHES # TRIC_DEVICES diff --git a/gcc/config/tricore/tricore-devices.c b/gcc/config/tricore/tricore-devices.c index 59427eb741d..52c76a580fe 100644 --- a/gcc/config/tricore/tricore-devices.c +++ b/gcc/config/tricore/tricore-devices.c @@ -118,16 +118,16 @@ tric_set_device (const char *name) if (tric_core && tric_device) return; if(tric_core) + { + for (device = tric_devices; device->name != NULL; device++) { - for (device = tric_devices; device->name != NULL; device++) - { - if (!STREQ (tric_core->name, device->core_mtc)) - continue; - /* Found the device */ - tric_device = device; - return; - } + if (!STREQ (tric_core->name, device->core_mtc)) + continue; + /* Found the device */ + tric_device = device; + return; } + } else name = tric_devices[0].name; } @@ -161,4 +161,4 @@ tric_set_device (const char *name) break; } -} +} \ No newline at end of file diff --git a/gcc/config/tricore/tricore-mcpu.opt b/gcc/config/tricore/tricore-mcpu.opt index 373c0f1b186..7fb2f3d7b8f 100644 --- a/gcc/config/tricore/tricore-mcpu.opt +++ b/gcc/config/tricore/tricore-mcpu.opt @@ -145,6 +145,18 @@ Enum(tric_mcpu) String(tc49Ax) Value(35) EnumValue Enum(tric_mcpu) String(tc4DAx) Value(36) +EnumValue +Enum(tric_mcpu) String(tc49xx) Value(36) + +EnumValue +Enum(tric_mcpu) String(tc45xx) Value(37) + +EnumValue +Enum(tric_mcpu) String(tc48xx) Value(38) + +EnumValue +Enum(tric_mcpu) String(tc46xx) Value(39) + EnumValue Enum(tric_merrata) String(cpu048) Value(tric_errata_cpu048) diff --git a/gcc/config/tricore/tricore.c b/gcc/config/tricore/tricore.c index e50ec6138e9..80de0f5c73b 100644 --- a/gcc/config/tricore/tricore.c +++ b/gcc/config/tricore/tricore.c @@ -5370,7 +5370,7 @@ tric_option_override (void) flag_finite_math_only = 1; } - if (flag_pic) + if (flag_pic == 1 || flag_pic == 2) error ("%qs: position independent code is not supported for " "this machine, try %qs", "-fpic", "-mcode-pic"); @@ -10130,6 +10130,8 @@ tric_eabi_round_type_align (tree type, unsigned computed, unsigned specified) unsigned tric_eabi_data_alignment (tree type, unsigned basic_align) { + if(tric_opt_force_align_arrays == 0) return basic_align; + unsigned best_align = BITS_PER_WORD; if (TREE_CODE (type) == ARRAY_TYPE) { diff --git a/gcc/config/tricore/tricore.h b/gcc/config/tricore/tricore.h index dba0ed72f2d..ff20457835b 100644 --- a/gcc/config/tricore/tricore.h +++ b/gcc/config/tricore/tricore.h @@ -913,6 +913,9 @@ typedef struct GTY(()) tric_section #define INIT_EXPANDERS tric_init_expanders() +#define SP_FPU_ENABLED (!TARGET_SP_SOFT_FLOAT) +#define DP_FPU_ENABLED (!TARGET_DP_SOFT_FLOAT) + /* Helper functions for late backend optimizations */ bool copy_constant_string (rtx_insn *, rtx *); bool remove_strcmp (rtx_insn *, rtx *); diff --git a/gcc/config/tricore/tricore.md b/gcc/config/tricore/tricore.md index c359a437d42..36e43dbccf7 100644 --- a/gcc/config/tricore/tricore.md +++ b/gcc/config/tricore/tricore.md @@ -1,5 +1,4 @@ -;; Machine description for Infineon TriCore -;; Copyright 2005-2014 Free Software Foundation, Inc. +;; Machine description for Infineon TriCore ;; Copyright 2005-2014 Free Software Foundation, Inc. ;; Contributed by HighTec EDV ;; This file is part of GCC. @@ -86,7 +85,7 @@ ]) -;; Define bit positions of result produced by cmp.f +;; Define bit positions of result produced by cmp.f and cmp.df (define_constants [(CMP_F_LT 0) @@ -560,7 +559,7 @@ [(set (match_operand:SF 0 "register_operand" "=d") (float_truncate:SF (match_operand:DF 1 "register_operand" "d"))) (clobber (reg:SI REG_PSW))] - "TRIC_HAVE_DP" + "TRIC_HAVE_DP && DP_FPU_ENABLED" "dftof\t%0, %A1" [(set_attr "pipe" "fp") (set_attr "length" "4")]) @@ -569,7 +568,7 @@ [(set (match_operand:DF 0 "register_operand" "=d") (float_extend:DF (match_operand:SF 1 "register_operand" "d"))) (clobber (reg:SI REG_PSW))] - "TRIC_HAVE_DP" + "TRIC_HAVE_DP && DP_FPU_ENABLED" "ftodf\t%A0, %1" [(set_attr "pipe" "fp") (set_attr "length" "4")]) @@ -578,7 +577,7 @@ [(set (match_operand:HF 0 "register_operand" "=d") (float_truncate:HF (match_operand:SF 1 "register_operand" "d"))) (clobber (reg:SI REG_PSW))] - "TRIC_HAVE_HP_CONVERT" + "TRIC_HAVE_HP_CONVERT && SP_FPU_ENABLED" "ftohp\t%0, %1" [(set_attr "pipe" "fp") (set_attr "length" "4")]) @@ -587,7 +586,7 @@ [(set (match_operand:SF 0 "register_operand" "=d") (float_extend:SF (match_operand:HF 1 "register_operand" "d"))) (clobber (reg:SI REG_PSW))] - "TRIC_HAVE_HP_CONVERT" + "TRIC_HAVE_HP_CONVERT && SP_FPU_ENABLED" "hptof\t%0, %1" [(set_attr "pipe" "fp") (set_attr "length" "4")]) @@ -2248,7 +2247,7 @@ (plus:SF (match_operand:SF 1 "register_operand" "d") (match_operand:SF 2 "register_operand" "d"))) (clobber (reg:SI REG_PSW))] - "" + "SP_FPU_ENABLED" "add.f\t%0, %1, %2" [(set_attr "pipe" "fp2")]) @@ -2257,7 +2256,7 @@ (plus:DF (match_operand:DF 1 "register_operand" "d") (match_operand:DF 2 "register_operand" "d"))) (clobber (reg:SI REG_PSW))] - "TRIC_HAVE_DP" + "TRIC_HAVE_DP && DP_FPU_ENABLED" "add.df\t%A0, %A1, %A2" [(set_attr "pipe" "fp2")]) @@ -2266,7 +2265,7 @@ (minus:SF (match_operand:SF 1 "register_operand" "d") (match_operand:SF 2 "register_operand" "d"))) (clobber (reg:SI REG_PSW))] - "" + "SP_FPU_ENABLED" "sub.f\t%0, %1, %2" [(set_attr "pipe" "fp2")]) @@ -2275,7 +2274,7 @@ (minus:DF (match_operand:DF 1 "register_operand" "d") (match_operand:DF 2 "register_operand" "d"))) (clobber (reg:SI REG_PSW))] - "TRIC_HAVE_DP" + "TRIC_HAVE_DP && DP_FPU_ENABLED" "sub.df\t%A0, %A1, %A2" [(set_attr "pipe" "fp2")]) @@ -2284,7 +2283,7 @@ (div:SF (match_operand:SF 1 "register_operand" "d") (match_operand:SF 2 "register_operand" "d"))) (clobber (reg:SI REG_PSW))] - "" + "SP_FPU_ENABLED" "div.f\t%0, %1, %2" [(set_attr "pipe" "fpdiv")]) @@ -2293,7 +2292,7 @@ (div:DF (match_operand:DF 1 "register_operand" "d") (match_operand:DF 2 "register_operand" "d"))) (clobber (reg:SI REG_PSW))] - "TRIC_HAVE_DP" + "TRIC_HAVE_DP && DP_FPU_ENABLED" "div.df\t%A0, %A1, %A2" [(set_attr "pipe" "fpdiv")]) @@ -2302,7 +2301,7 @@ (mult:SF (match_operand:SF 1 "register_operand" "d") (match_operand:SF 2 "register_operand" "d"))) (clobber (reg:SI REG_PSW))] - "" + "SP_FPU_ENABLED" "mul.f\t%0, %1, %2" [(set_attr "pipe" "fp2")]) @@ -2311,7 +2310,7 @@ (mult:DF (match_operand:DF 1 "register_operand" "d") (match_operand:DF 2 "register_operand" "d"))) (clobber (reg:SI REG_PSW))] - "TRIC_HAVE_DP" + "TRIC_HAVE_DP && DP_FPU_ENABLED" "mul.df\t%A0, %A1, %A2" [(set_attr "pipe" "fp2")]) @@ -2331,7 +2330,8 @@ if (0 == which_alternative) { - if (TRIC_18UP) return asmcode[2]; else return asmcode[which_alternative]; + if (TRIC_18UP && SP_FPU_ENABLED) return asmcode[2]; + else return asmcode[which_alternative]; } if (1 == which_alternative) { @@ -2344,7 +2344,7 @@ (define_insn "negdf2" [(set (match_operand:DF 0 "register_operand" "=d") (neg:DF (match_operand:DF 1 "register_operand" "d")))] - "(TRIC_HAVE_DP)" + "TRIC_HAVE_DP && DP_FPU_ENABLED" "neg.df\t%A0, %A1" [(set_attr "pipe" "fp2")]) @@ -2353,7 +2353,7 @@ (smax:SF (match_operand:SF 1 "register_operand" "d") (match_operand:SF 2 "register_operand" "d"))) (clobber (reg:SI REG_PSW))] - "(TRIC_18UP)" + "(TRIC_18UP && SP_FPU_ENABLED)" "max.f %0,%1,%2" [(set_attr "pipe" "fp2")]) @@ -2372,7 +2372,7 @@ (const_int 0)) (match_dup 1) (match_dup 2)))] - "" + "SP_FPU_ENABLED" { if (TRIC_18UP) { @@ -2392,7 +2392,7 @@ (smax:DF (match_operand:DF 1 "register_operand" "d") (match_operand:DF 2 "register_operand" "d"))) (clobber (reg:SI REG_PSW))] - "(TRIC_HAVE_DP)" + "TRIC_HAVE_DP && DP_FPU_ENABLED" "max.df %A0,%A1,%A2" [(set_attr "pipe" "fp2")]) @@ -2401,7 +2401,7 @@ (smin:SF (match_operand:SF 1 "register_operand" "d") (match_operand:SF 2 "register_operand" "d"))) (clobber (reg:SI REG_PSW))] - "(TRIC_18UP)" + "(TRIC_18UP && SP_FPU_ENABLED)" "min.f %0,%1,%2" [(set_attr "pipe" "fp2")]) @@ -2420,8 +2420,9 @@ (const_int 0)) (match_dup 1) (match_dup 2)))] - "" + "SP_FPU_ENABLED" { + if (TRIC_18UP) { emit_insn (gen_sminsf3_insn (operands[0], operands[1],operands[2])); @@ -2439,7 +2440,7 @@ (smin:DF (match_operand:DF 1 "register_operand" "d") (match_operand:DF 2 "register_operand" "d"))) (clobber (reg:SI REG_PSW))] - "(TRIC_HAVE_DP)" + "TRIC_HAVE_DP && DP_FPU_ENABLED" "min.df %A0,%A1,%A2" [(set_attr "pipe" "fp2")]) @@ -2481,7 +2482,7 @@ (unspec:SI [(match_operand:SF 1 "register_operand" "d") (match_operand:SF 2 "register_operand" "d")] UNSPEC_CMP_F)) (clobber (reg:SI REG_PSW))] - "" + "SP_FPU_ENABLED" "cmp.f\t%0, %1, %2" [(set_attr "pipe" "fp")]) @@ -2490,7 +2491,7 @@ (unspec:SI [(match_operand:DF 1 "register_operand" "d") (match_operand:DF 2 "register_operand" "d")] UNSPEC_CMP_DF)) (clobber (reg:SI REG_PSW))] - "(TRIC_HAVE_DP)" + "TRIC_HAVE_DP && DP_FPU_ENABLED" "cmp.df\t%0, %A1, %A2" [(set_attr "pipe" "fp")]) @@ -2498,7 +2499,7 @@ [(set (match_operand:SF 0 "register_operand" "=d") (float:SF (match_operand:SI 1 "register_operand" "d"))) (clobber (reg:SI REG_PSW))] - "" + "SP_FPU_ENABLED" "itof\t%0, %1" [(set_attr "pipe" "fp2")]) @@ -2506,7 +2507,7 @@ [(set (match_operand:DF 0 "register_operand" "=d") (float:DF (match_operand:SI 1 "register_operand" "d"))) (clobber (reg:SI REG_PSW))] - "(TRIC_HAVE_DP)" + "TRIC_HAVE_DP && DP_FPU_ENABLED" "itodf\t%A0, %1" [(set_attr "pipe" "fp2")]) @@ -2514,7 +2515,7 @@ [(set (match_operand:DF 0 "register_operand" "=d") (float:DF (match_operand:DI 1 "register_operand" "d"))) (clobber (reg:SI REG_PSW))] - "(TRIC_HAVE_DP)" + "TRIC_HAVE_DP && DP_FPU_ENABLED" "ltodf\t%A0, %A1" [(set_attr "pipe" "fp2")]) @@ -2522,7 +2523,7 @@ [(set (match_operand:SF 0 "register_operand" "=d") (unsigned_float:SF (match_operand:SI 1 "register_operand" "d"))) (clobber (reg:SI REG_PSW))] - "" + "SP_FPU_ENABLED" "utof\t%0, %1" [(set_attr "pipe" "fp2")]) @@ -2530,7 +2531,7 @@ [(set (match_operand:DF 0 "register_operand" "=d") (unsigned_float:DF (match_operand:SI 1 "register_operand" "d"))) (clobber (reg:SI REG_PSW))] - "(TRIC_HAVE_DP)" + "TRIC_HAVE_DP && DP_FPU_ENABLED" "utodf\t%A0, %1" [(set_attr "pipe" "fp2")]) @@ -2538,7 +2539,7 @@ [(set (match_operand:DF 0 "register_operand" "=d") (unsigned_float:DF (match_operand:DI 1 "register_operand" "d"))) (clobber (reg:SI REG_PSW))] - "(TRIC_HAVE_DP)" + "TRIC_HAVE_DP && DP_FPU_ENABLED" "ultodf\t%A0, %A1" [(set_attr "pipe" "fp2")]) @@ -2551,7 +2552,7 @@ (clobber (reg:DI REG_D0))]) (set (match_operand:SI 0 "register_operand" "") (reg:SI REG_D2))] - "" + "SP_FPU_ENABLED" { if (TRIC_HAVE_FTOIZ) { @@ -2569,7 +2570,7 @@ (clobber (reg:DI REG_D0))]) (set (match_operand:SI 0 "register_operand" "") (reg:SI REG_D2))] - "" + "SP_FPU_ENABLED" { if (TRIC_HAVE_FTOIZ) { @@ -2582,7 +2583,7 @@ [(set (match_operand:DI 0 "register_operand" "=d") (fix:DI (match_operand:DF 1 "register_operand" "d"))) (clobber (reg:SI REG_PSW))] - "(TRIC_HAVE_DP)" + "TRIC_HAVE_DP && DP_FPU_ENABLED" "dftolz\t%A0, %A1" [(set_attr "pipe" "fp2")]) @@ -2590,7 +2591,7 @@ [(set (match_operand:DI 0 "register_operand" "=d") (unsigned_fix:DI (match_operand:DF 1 "register_operand" "d"))) (clobber (reg:SI REG_PSW))] - "(TRIC_HAVE_DP)" + "TRIC_HAVE_DP && DP_FPU_ENABLED" "dftoulz\t%A0, %A1" [(set_attr "pipe" "fp2")]) @@ -2598,7 +2599,7 @@ [(set (match_operand:SI 0 "register_operand" "=d") (fix:SI (match_operand:SF 1 "register_operand" "d"))) (clobber (reg:SI REG_PSW))] - "TRIC_HAVE_FTOIZ" + "TRIC_HAVE_FTOIZ && SP_FPU_ENABLED" "ftoiz\t%0, %1" [(set_attr "pipe" "fp2")]) @@ -2606,7 +2607,7 @@ [(set (match_operand:SI 0 "register_operand" "=d") (unsigned_fix:SI (match_operand:SF 1 "register_operand" "d"))) (clobber (reg:SI REG_PSW))] - "TRIC_HAVE_FTOIZ" + "TRIC_HAVE_FTOIZ && SP_FPU_ENABLED" "ftouz\t%0, %1" [(set_attr "pipe" "fp2")]) @@ -2615,7 +2616,7 @@ (fix:SI (reg:SF REG_D4))) (clobber (reg:SI REG_A2)) (clobber (reg:DI REG_D0))] - "!TRIC_HAVE_FTOIZ" + "!TRIC_HAVE_FTOIZ && SP_FPU_ENABLED" "call\t__fixsfsi" [(set_attr "pipe" "ctx")]) @@ -2624,7 +2625,7 @@ (unsigned_fix:SI (reg:SF REG_D4))) (clobber (reg:SI REG_A2)) (clobber (reg:DI REG_D0))] - "!TRIC_HAVE_FTOIZ" + "!TRIC_HAVE_FTOIZ && SP_FPU_ENABLED" "call\t__fixunssfsi" [(set_attr "pipe" "ctx")]) @@ -2632,7 +2633,7 @@ [(set (match_operand:SI 0 "register_operand" "=d") (fix:SI (match_operand:DF 1 "register_operand" "d"))) (clobber (reg:SI REG_PSW))] - "TRIC_HAVE_DP" + "TRIC_HAVE_DP && DP_FPU_ENABLED" "dftoiz\t%0, %A1" [(set_attr "pipe" "fp2")]) @@ -2640,7 +2641,7 @@ [(set (match_operand:SI 0 "register_operand" "=d") (unsigned_fix:SI (match_operand:DF 1 "register_operand" "d"))) (clobber (reg:SI REG_PSW))] - "TRIC_HAVE_DP" + "TRIC_HAVE_DP && DP_FPU_ENABLED" "dftouz\t%0, %A1" [(set_attr "pipe" "fp2")]) @@ -2651,7 +2652,7 @@ (match_operand:SF 2 "register_operand" "d") (match_operand:SF 3 "register_operand" "d"))) (clobber (reg:SI REG_PSW))] - "!TRIC_ERRATA_076" + "!TRIC_ERRATA_076 && SP_FPU_ENABLED" "madd.f\t%0, %3, %1, %2" [(set_attr "pipe" "fp3")]) @@ -2662,7 +2663,7 @@ (match_operand:DF 2 "register_operand" "d") (match_operand:DF 3 "register_operand" "d"))) (clobber (reg:SI REG_PSW))] - "TRIC_HAVE_DP" + "TRIC_HAVE_DP && DP_FPU_ENABLED" "madd.df\t%A0, %A3, %A1, %A2" [(set_attr "pipe" "fp3")]) @@ -2675,7 +2676,7 @@ (clobber (reg:SI REG_PSW))]) (set (match_operand:SF 0 "register_operand" "") (neg:SF (match_dup 4)))] - "!TRIC_ERRATA_076" + "!TRIC_ERRATA_076 && SP_FPU_ENABLED" { operands[4] = gen_reg_rtx (SFmode); }) @@ -2689,7 +2690,7 @@ (clobber (reg:SI REG_PSW))]) (set (match_operand:DF 0 "register_operand" "") (neg:DF (match_dup 4)))] - "TRIC_HAVE_DP" + "TRIC_HAVE_DP && DP_FPU_ENABLED" { operands[4] = gen_reg_rtx (DFmode); }) @@ -2701,7 +2702,7 @@ (match_operand:SF 2 "register_operand" "d") (match_operand:SF 3 "register_operand" "d"))) (clobber (reg:SI REG_PSW))] - "!TRIC_ERRATA_076" + "!TRIC_ERRATA_076 && SP_FPU_ENABLED" "msub.f\t%0, %3, %1, %2" [(set_attr "pipe" "fp3")]) @@ -2712,7 +2713,7 @@ (match_operand:DF 2 "register_operand" "d") (match_operand:DF 3 "register_operand" "d"))) (clobber (reg:SI REG_PSW))] - "TRIC_HAVE_DP" + "TRIC_HAVE_DP && DP_FPU_ENABLED" "msub.df\t%A0, %A3, %A1, %A2" [(set_attr "pipe" "fp3")]) @@ -2725,7 +2726,7 @@ (clobber (reg:SI REG_PSW))]) (set (match_operand:SF 0 "register_operand" "") (neg:SF (match_dup 4)))] - "!TRIC_ERRATA_076" + "!TRIC_ERRATA_076 && SP_FPU_ENABLED" { operands[4] = gen_reg_rtx (SFmode); }) @@ -2739,7 +2740,7 @@ (clobber (reg:SI REG_PSW))]) (set (match_operand:DF 0 "register_operand" "") (neg:DF (match_dup 4)))] - "TRIC_HAVE_DP" + "TRIC_HAVE_DP && DP_FPU_ENABLED" { operands[4] = gen_reg_rtx (DFmode); }) @@ -3623,19 +3624,25 @@ "insert\t%0, %1, 0, 31, 1", "abs.f\t%0,%1" }; - if (0 == which_alternative) - { - if (TRIC_18UP) return asmcode[1]; else return asmcode[which_alternative]; - } - return ""; + if (TRIC_18UP && SP_FPU_ENABLED) return asmcode[1]; + else return asmcode[0]; } - [(set_attr "pipe" "fp2")]) + [(set (attr "pipe") + (if_then_else + (and + (ne (symbol_ref "TRIC_18UP") (const_int 0)) + (ne (symbol_ref "SP_FPU_ENABLED") (const_int 0)) + ) + (const_string "ip") + (const_string "fp2") + ) + )]) (define_insn "absdf2" [(set (match_operand:DF 0 "register_operand" "=d") (abs:DF (match_operand:DF 1 "register_operand" "d")))] - "(TRIC_HAVE_DP)" + "TRIC_HAVE_DP && DP_FPU_ENABLED" "abs.df\t%A0, %A1" [(set_attr "pipe" "fp2")]) @@ -4116,7 +4123,7 @@ (match_operand:SF 2 "register_operand" "")]) (label_ref (match_operand 3 "" "")) (pc)))] - "" + "SP_FPU_ENABLED" { tric_emit_cbranchsf4 (operands); DONE; @@ -4129,7 +4136,7 @@ (match_operand:DF 2 "register_operand" "")]) (label_ref (match_operand 3 "" "")) (pc)))] - "(TRIC_HAVE_DP)" + "TRIC_HAVE_DP && DP_FPU_ENABLED" { tric_emit_cbranchdf4 (operands); DONE; diff --git a/gcc/config/tricore/tricore.opt b/gcc/config/tricore/tricore.opt index e79c0f287f0..ddc710d9939 100644 --- a/gcc/config/tricore/tricore.opt +++ b/gcc/config/tricore/tricore.opt @@ -221,3 +221,23 @@ Perform strcmp asm replacements optimization as builtin, default is on greater/e mstrcmp-imm= Target Joined UInteger Var(tric_opt_flag_strcmp_imm) Init(0) Perform strcmp imm replacements, strcmp full replacement, default is on in greater/equal -O3. + +mforce-align-arrays +Target UInteger Var(tric_opt_force_align_arrays) Init(0) +Force all arrays to be 32 bit aligned. + +msoft-sp-float +Target RejectNegative Mask(SP_SOFT_FLOAT) +Inhibit the use of hardware single precision floating point instructions. + +mhard-sp-float +Target RejectNegative InverseMask(SP_SOFT_FLOAT) +Enable hardware single precision floating point instructions. + +msoft-dp-float +Target RejectNegative Mask(DP_SOFT_FLOAT) +Inhibit the use of hardware double precision floating point instructions. + +mhard-dp-float +Target RejectNegative InverseMask(DP_SOFT_FLOAT) +Enable hardware double precision floating point instructions. \ No newline at end of file diff --git a/libgcc/config/tricore/t-tricore b/libgcc/config/tricore/t-tricore index 5a9e59075b1..1a828443ce5 100644 --- a/libgcc/config/tricore/t-tricore +++ b/libgcc/config/tricore/t-tricore @@ -4,8 +4,6 @@ LIB1ASMFUNCS = \ _udivmodsi4 \ _rstcntxt \ _bswapsi2 \ - _fixsfsi \ - _fixunssfsi \ _paritysi2 \ _ashldi3 \ _ashrdi3 \ @@ -14,6 +12,11 @@ LIB1ASMFUNCS = \ memset \ memcmp +ifeq (,$(findstring soft-single-float, $(MULTISUBDIR))) +# The compiler is called without the flag -msoft-sp-float, we can add libcc function overrides which use Floating Point hardware +LIB1ASMFUNCS += _fixsfsi _fixunssfsi +endif + LIB2FUNCS_EXCLUDE = \ _divdi3 _moddi3 _divmoddi4 \