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RedFatPlugin.cpp
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RedFatPlugin.cpp
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/* ____ _ _____ _
* | _ \ ___ __| | ___|_ _| |_
* --- | |_) / _ \/ _` | |_ / _` | __| ---------------------->
* | _ < __/ (_| | _| (_| | |_
* |_| \_\___|\__,_|_| \__,_|\__| BINARY HARDENING SYSTEM
*
* Copyright (C) 2022 National University of Singapore
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
#include <map>
#include <string>
#include <set>
#include <cassert>
#include <cstdarg>
#include <cstdio>
#include <cstring>
#include <getopt.h>
#include <sys/mman.h>
#include "e9plugin.h"
using namespace e9tool;
#include "redfat-rt.h"
/*************************************************************************/
/* MISC. */
/*************************************************************************/
/*
* Prototypes.
*/
static const OpInfo *getMemOp(const InstrInfo *I);
/*
* Instrumentation.
*/
enum Instrumentation : uint8_t
{
MODE_NONE, // Do-not-instrument
MODE_REDZONE, // Redzone-only
MODE_LOWFAT // Redzone+lowfat
};
/*
* Options.
*/
static bool REDFAT_XREADS = false;
static bool REDFAT_XWRITES = true;
static bool REDFAT_XLOWFAT = false;
static bool REDFAT_XSTACK = true;
static bool REDFAT_XFRAME = true;
static bool REDFAT_XGLOBALS = true;
static bool REDFAT_XSIZE = false;
static bool REDFAT_XADJUST = false;
static bool REDFAT_XALLOWLIST_GEN = false;
static bool REDFAT_XALLOWLIST_USE = false;
static bool REDFAT_XPROFILE = false;
static bool REDFAT_OELIM = true;
static size_t REDFAT_OBATCH = 50;
static bool REDFAT_OMERGE = true;
static bool REDFAT_OSCRATCH = true;
static bool REDFAT_OFLAGS = true;
static bool REDFAT_OSTACK = true;
static bool REDFAT_OFRAME = false;
static bool REDFAT_OGLOBALS = true;
static bool REDFAT_OSYSV = false;
static bool REDFAT_LOG = false;
static bool REDFAT_FORCE = false;
static const char *REDFAT_XALLOWLIST = nullptr;
static Instrumentation REDFAT_XALLOWLIST_MODE[] =
{
MODE_REDZONE, // Lowfat-Unsafe
MODE_LOWFAT, // Lowfat-Safe
MODE_REDZONE, // Nonfat-only
MODE_REDZONE // Not-reached
};
/*
* Logging.
*/
static void log(char c)
{
if (!REDFAT_LOG)
return;
fputc(c, stderr);
}
static void log(const char *msg, ...)
{
if (!REDFAT_LOG)
return;
va_list ap;
va_start(ap, msg);
vfprintf(stderr, msg, ap);
va_end(ap);
}
/*
* Allow-list
*/
static std::map<uintptr_t, int8_t> allowlist;
static Instrumentation allowlist_lookup(const InstrInfo *I)
{
if (!REDFAT_XALLOWLIST_USE)
{
// Allow-list disabled = always instrument with Lowfat
return REDFAT_XALLOWLIST_MODE[ALLOW_LOWFAT];
}
auto i = allowlist.find(I->address);
if (allowlist.find(I->address) == allowlist.end())
{
// Not covered = do not instrument with Lowfat
return REDFAT_XALLOWLIST_MODE[ALLOW_UNKNOWN];
}
const OpInfo *op = getMemOp(I);
if (op == nullptr || op->mem.base == REGISTER_NONE)
return REDFAT_XALLOWLIST_MODE[ALLOW_UNKNOWN];
return REDFAT_XALLOWLIST_MODE[i->second];
}
/*************************************************************************/
/* REGISTERS */
/*************************************************************************/
/*
* Translate an x86_reg into an x64 register number.
*/
static int regno(Register reg)
{
switch (reg)
{
case REGISTER_AH: case REGISTER_AL:
case REGISTER_AX: case REGISTER_EAX: case REGISTER_RAX:
return 0;
case REGISTER_CH: case REGISTER_CL:
case REGISTER_CX: case REGISTER_ECX: case REGISTER_RCX:
return 1;
case REGISTER_DH: case REGISTER_DL:
case REGISTER_DX: case REGISTER_EDX: case REGISTER_RDX:
return 2;
case REGISTER_BH: case REGISTER_BL:
case REGISTER_BX: case REGISTER_EBX: case REGISTER_RBX:
return 3;
case REGISTER_SP: case REGISTER_SPL: case REGISTER_ESP:
case REGISTER_RSP:
return 4;
case REGISTER_BP: case REGISTER_BPL: case REGISTER_EBP:
case REGISTER_RBP:
return 5;
case REGISTER_SI: case REGISTER_SIL: case REGISTER_ESI:
case REGISTER_RSI:
return 6;
case REGISTER_DI: case REGISTER_DIL: case REGISTER_EDI:
case REGISTER_RDI:
return 7;
case REGISTER_R8B: case REGISTER_R8W: case REGISTER_R8D:
case REGISTER_R8:
return 8;
case REGISTER_R9B: case REGISTER_R9W: case REGISTER_R9D:
case REGISTER_R9:
return 9;
case REGISTER_R10B: case REGISTER_R10W: case REGISTER_R10D:
case REGISTER_R10:
return 10;
case REGISTER_R11B: case REGISTER_R11W: case REGISTER_R11D:
case REGISTER_R11:
return 11;
case REGISTER_R12B: case REGISTER_R12W: case REGISTER_R12D:
case REGISTER_R12:
return 12;
case REGISTER_R13B: case REGISTER_R13W: case REGISTER_R13D:
case REGISTER_R13:
return 13;
case REGISTER_R14B: case REGISTER_R14W: case REGISTER_R14D:
case REGISTER_R14:
return 14;
case REGISTER_R15B: case REGISTER_R15W: case REGISTER_R15D:
case REGISTER_R15:
return 15;
default:
return -1;
}
}
/*
* Returns `true' if the whole 64bit register will be clobbered with a write.
* (Either directly or by zero-extension).
*/
static bool regClobbered(Register reg)
{
switch (reg)
{
case REGISTER_EAX: case REGISTER_RAX:
return true;
case REGISTER_ECX: case REGISTER_RCX:
return true;
case REGISTER_EDX: case REGISTER_RDX:
return true;
case REGISTER_EBX: case REGISTER_RBX:
return true;
case REGISTER_ESP: case REGISTER_RSP:
return true;
case REGISTER_EBP: case REGISTER_RBP:
return true;
case REGISTER_ESI: case REGISTER_RSI:
return true;
case REGISTER_EDI: case REGISTER_RDI:
return true;
case REGISTER_R8D: case REGISTER_R8:
return true;
case REGISTER_R9D: case REGISTER_R9:
return true;
case REGISTER_R10D: case REGISTER_R10:
return true;
case REGISTER_R11D: case REGISTER_R11:
return true;
case REGISTER_R12D: case REGISTER_R12:
return true;
case REGISTER_R13D: case REGISTER_R13:
return true;
case REGISTER_R14D: case REGISTER_R14:
return true;
case REGISTER_R15D: case REGISTER_R15:
return true;
default:
return false;
}
}
/*
* Get register name from register index.
*/
static const char *regNameFromIdx(int r)
{
switch (r)
{
case 0: return "%rax";
case 1: return "%rcx";
case 2: return "%rdx";
case 3: return "%rbx";
case 4: return "%rsp";
case 5: return "%rbp";
case 6: return "%rsi";
case 7: return "%rdi";
case 8: return "%r8";
case 9: return "%r9";
case 10: return "%r10";
case 11: return "%r11";
case 12: return "%r12";
case 13: return "%r13";
case 14: return "%r14";
case 15: return "%r15";
default: return "???";
}
}
static const char *regName(Register reg)
{
return regNameFromIdx(regno(reg));
}
/*
* Representation of a register set.
* (Implemented as a bitset over the regno).
*/
struct RegSet
{
uint32_t regs = 0;
void clear()
{
regs = 0;
}
bool get(Register reg) const
{
int r = regno(reg);
if (r < 0)
return false;
return (((1 << r) & regs) != 0);
}
bool member(Register reg) const
{
return get(reg);
}
void set(Register reg, bool val)
{
int r = regno(reg);
if (r < 0)
return;
if (val)
regs |= (1 << r);
else
regs &= ~(1 << r);
}
void add(Register reg)
{
set(reg, true);
}
void remove(Register reg)
{
set(reg, false);
}
void dump() const
{
log('{');
bool prev = false;
for (unsigned r = 0; r < 16; r++)
{
if (((1 << r) & regs) == 0)
continue;
if (prev)
log(',');
prev = true;
log("%s", regNameFromIdx(r));
}
log('}');
}
};
/*************************************************************************/
/* CODEGEN SUPPORT */
/*************************************************************************/
/*
* Representation of a memory operation that is scheduled to be checked.
* (part of a batch of instructions to be checked).
*/
struct BatchEntry
{
const Instr *I; // Instruction to be checked
ssize_t lb; // Lower bound
ssize_t ub; // Upper bound
bool read = false; // Read only?
bool redzone = true; // Redzone check?
bool lowfat = false; // LowFat check?
bool removed = false; // Removed?
BatchEntry(const Instr *I, ssize_t lb, ssize_t ub) : I(I), lb(lb), ub(ub)
{
;
}
};
/*
* Adjustments.
*/
typedef std::map<Register, off_t> Adjusts;
/*
* Representation of a batch of instructions to be checked.
*/
struct Batch
{
std::vector<BatchEntry> entries; // Instructions & bounds
Adjusts adjusts; // Adjustments
RegSet scratch; // Available scratch registers
bool clobber_flags = false; // Can clobber %rflags?
};
/*
* RedFat info/state.
*/
struct RedFat
{
const ELF *elf = nullptr; // The ELF file
const Instr *Is = nullptr; // All instrs
size_t size = 0; // size of Is
Targets targets; // Jump targets
std::map<intptr_t, Batch> batches; // All batches
RegSet clobbered; // Current clobbers
std::vector<BatchEntry> batch; // Current batch
// Stats
unsigned num_reads = 0;
unsigned num_writes = 0;
size_t batches_num = 0;
size_t batches_size = 0;
};
/*
* Stats.
*/
struct Stats
{
unsigned num_redzone_reads_unopt;
unsigned num_redzone_writes_unopt;
unsigned num_redzone_reads_opt;
unsigned num_redzone_writes_opt;
unsigned num_lowfat_reads_unopt;
unsigned num_lowfat_writes_unopt;
unsigned num_lowfat_reads_opt;
unsigned num_lowfat_writes_opt;
};
/*
* Collect stats.
*/
static void getStats(const std::vector<BatchEntry> &entries, Stats *stats)
{
memset(stats, 0, sizeof(*stats));
for (const auto &entry: entries)
{
if (entry.read && entry.redzone)
stats->num_redzone_reads_unopt++;
if (!entry.read && entry.redzone)
stats->num_redzone_writes_unopt++;
if (entry.read && entry.lowfat)
stats->num_lowfat_reads_unopt++;
if (!entry.read && entry.lowfat)
stats->num_lowfat_writes_unopt++;
if (!entry.removed)
{
if (entry.read && entry.redzone)
stats->num_redzone_reads_opt++;
if (!entry.read && entry.redzone)
stats->num_redzone_writes_opt++;
if (entry.read && entry.lowfat)
stats->num_lowfat_reads_opt++;
if (!entry.read && entry.lowfat)
stats->num_lowfat_writes_opt++;
}
}
}
/*
* Save a register value to TLS.
*/
static void emitSAVE(FILE *stream, int32_t offset, Register regA)
{
int a = regno(regA);
uint8_t rex = 0x48 | (a >= 8? 0x04: 0x00);
uint8_t modrm = (0x00 << 6) | ((uint8_t)(a & 0x7) << 3) | 0x04;
fprintf(stream, "%u,%u,%u,%u,%u,{\"int32\":%d},",
0x64, rex, 0x89, modrm, 0x25, offset);
}
/*
* Restore a register value from TLS.
*/
static void emitRESTORE(FILE *stream, int32_t offset, Register regA)
{
int a = regno(regA);
uint8_t rex = 0x48 | (a >= 8? 0x04: 0x00);
uint8_t modrm = (0x00 << 6) | ((uint8_t)(a & 0x7) << 3) | 0x04;
fprintf(stream, "%u,%u,%u,%u,%u,{\"int32\":%d},",
0x64, rex, 0x8b, modrm, 0x25, offset);
}
/*
* Load a 64bit value from an address (table+regA) into regB.
*/
static void emitLOAD(FILE *stream, int32_t table, Register regA, Register regB)
{
int a = regno(regA);
int b = regno(regB);
uint8_t rex = 0x48 | (a >= 8? 0x02: 0x00) | (b >= 8? 0x04: 0x00);
uint8_t modrm = (0x00 << 6) | ((uint8_t)(b & 0x7) << 3) | 0x04;
uint8_t sib = 0xc5 | ((uint8_t)(a & 0x7) << 3);
fprintf(stream, "%u,%u,%u,%u,{\"int32\":%d},",
rex, 0x8b, modrm, sib, table);
}
/*
* Converts a memory-access instruction (I) into a "Load Effective Address"
* (LEA) instruction that loads the corresponding pointer into the reg.
*/
static void emitLEA(FILE *stream, const InstrInfo *I, int32_t ub, Register reg)
{
int r = regno(reg);
uint8_t rex = (r < 8? 0x48: 0x4c);
if (I->hasREX())
rex |= (I->getREX() & 0x03);
else if (I->hasVEX())
{
uint32_t vex = I->getVEX();
rex |= ((vex & 0xFF) == 0xC4? (~vex & 0x6000) >> 13: 0x00);
}
else if (I->hasEVEX())
{
uint32_t evex = I->getEVEX();
rex |= (evex & 0x6000) >> 13;
}
uint8_t modrm = I->getMODRM();
modrm = (modrm & 0xc7) | (((uint8_t)r & 0x7) << 3);
uint8_t mod = (modrm >> 6) & 0x3;
uint8_t rm = modrm & 0x7;
uint8_t base = 0;
uint8_t sib = I->getSIB();
if (I->hasSIB())
base = sib & 0x7;
assert(!((mod == 0x0 && rm == 0x5))); // No PC-rel!
intptr_t disp = (intptr_t)ub;
switch (mod)
{
case 0x00:
if (base == 0x5)
break;
if (disp >= INT8_MIN && disp <= INT8_MAX)
modrm = (modrm & 0x3f) | (0x01 << 6);
else
modrm = (modrm & 0x3f) | (0x02 << 6);
break;
case 0x01:
if (disp < INT8_MIN || disp > INT8_MAX)
modrm = (modrm & 0x3f) | (0x02 << 6);
break;
default:
break;
}
fprintf(stream, "%u,%u,%u,", rex, 0x8d, modrm);
if (I->hasSIB())
fprintf(stream, "%u,", sib);
mod = (modrm >> 6) & 0x3;
switch (mod)
{
case 0x00:
if (I->hasSIB() && base == 0x5)
fprintf(stream, "{\"int32\":%d},", (int32_t)disp);
break;
case 0x01:
fprintf(stream, "{\"int8\":%d},", (int32_t)disp);
break;
case 0x02:
fprintf(stream, "{\"int32\":%d},", (int32_t)disp);
break;
}
}
/*
* Move a 32bit constant (x) into reg.
*/
static void emitMOV(FILE *stream, uint32_t x, Register reg)
{
int r = regno(reg);
if (r >= 8)
fprintf(stream, "%u,", 0x41);
uint8_t opcode = 0xb8 + (r & 0x7);
fprintf(stream, "%u,{\"int32\":%d},", opcode, (int)x);
}
/*
* Move between two 64bit registers.
*/
static void emitMOV(FILE *stream, Register regA, Register regB)
{
int a = regno(regA);
int b = regno(regB);
if (a == b)
return;
uint8_t rex = 0x48;
rex |= (a >= 8? 0x04: 0x00);
rex |= (b >= 8? 0x01: 0x00);
uint8_t modrm = 0xc0 | (uint8_t)(b & 0x7) | ((uint8_t)(a & 0x7) << 3);
fprintf(stream, "%u,%u,%u,", rex, 0x89, modrm);
}
/*
* Move 64bit registers with adjustment.
*/
static void emitADJUST(FILE *stream, off_t adjust, Register regA,
Register regB)
{
if (adjust == 0 || adjust < INT32_MIN || adjust > INT32_MAX)
{
emitMOV(stream, regA, regB);
return;
}
int a = regno(regA);
int b = regno(regB);
uint8_t rex = 0x48;
rex |= (b >= 8? 0x04: 0x00);
rex |= (a >= 8? 0x01: 0x00);
uint8_t mod = 0x00;
uint8_t r = (uint8_t)(b & 0x7);
uint8_t rm = (uint8_t)(a & 0x7);
uint8_t sib = 0x00;
if (adjust != 0 && adjust >= INT8_MIN && adjust <= INT8_MAX)
mod = 0x01;
else
mod = 0x02;
if (regA == REGISTER_RSP || regA == REGISTER_R12)
{
rm = 0x04;
sib = 0x24;
}
uint8_t modrm = (mod << 6) | (r << 3) | rm;
fprintf(stream, "%u,%u,%u,", rex, 0x8d, modrm);
if (sib != 0x0)
fprintf(stream, "%u,", sib);
if (mod == 0x1)
fprintf(stream, "{\"int8\":%d},", (int32_t)adjust);
else if (mod == 0x2)
fprintf(stream, "{\"int32\":%d},", (int32_t)adjust);
}
/*
* Exchange two 64bit registers.
*/
static void emitXCHG(FILE *stream, Register regA, Register regB)
{
int a = regno(regA);
int b = regno(regB);
if (a == b)
return;
if (a > b)
{
int tmp = a;
a = b;
b = tmp;
}
if (a == 0) // 0 == %rax which needs special handling
{
uint8_t rex = (b >= 8? 0x49: 0x48);
uint8_t opcode = 0x90 + (b & 0x7);
fprintf(stream, "%u,%u,", rex, opcode);
return;
}
uint8_t rex = 0x48;
rex |= (a >= 8? 0x01: 0x00);
rex |= (b >= 8? 0x04: 0x00);
uint8_t modrm = 0xc0 | (uint8_t)(a & 0x7) | ((uint8_t)(b & 0x7) << 3);
fprintf(stream, "%u,%u,%u,", rex, 0x87, modrm);
}
/*
* Dereference the pointer in regA and store the result in regB.
*/
static void emitDEREF(FILE *stream, Register regA, Register regB)
{
int a = regno(regA);
int b = regno(regB);
uint8_t rex = 0x48 | (a >= 8? 0x01: 0x00) | (b >= 8? 0x04: 0x00);
uint8_t modrm = 0x00 | ((uint8_t)(b & 0x7) << 3) | (uint8_t)(a & 0x7);
fprintf(stream, "%u,%u,%u,", rex, 0x8b, modrm);
}
/*
* Emit instructions to calculate the lowfat_index() operation without
* affecting %rflags. For this we use BMI2's RORX instruction.
*/
static void emitIDX(FILE *stream, Register regA, Register regB)
{
int a = regno(regA);
int b = regno(regB);
// rorx $35,%regA,%regB
uint8_t b1 = 0x43 | (a < 8? 0x20: 0x00) | (b < 8? 0x80: 0x00);
uint8_t b2 = 0xfb;
uint8_t modrm = 0xc0 | (uint8_t)(a & 0x7) | (((uint8_t)(b & 0x7)) << 3);
fprintf(stream, "%u,%u,%u,%u,%u,%u,", 0xc4, b1, b2, 0xf0, modrm, 35);
// movzwl %regBw,%regBd
modrm = 0xc0 | ((uint8_t)(b & 0x7) << 3) | (uint8_t)(b & 0x7);
if (b >= 8)
fprintf(stream, "%u,", 0x45);
fprintf(stream, "%u,%u,%u,", 0x0f, 0xb7, modrm);
}
/*
* Swap the upper and lower 32bit word of regA and store the result in regB.
*/
static void emitSWAP(FILE *stream, Register regA, Register regB)
{
int a = regno(regA);
int b = regno(regB);
// rorx $32,%regA,%regB
uint8_t b1 = 0x43 | (a < 8? 0x20: 0x00) | (b < 8? 0x80: 0x00);
uint8_t b2 = 0xfb;
uint8_t modrm = 0xc0 | (uint8_t)(a & 0x7) | (((uint8_t)(b & 0x7)) << 3);
fprintf(stream, "%u,%u,%u,%u,%u,%u,", 0xc4, b1, b2, 0xf0, modrm, 32);
}
/*
* Multiplication.
*/
static void emitMUL(FILE *stream, int32_t table, Register regA, Register regB,
Register regC)
{
assert(regA != REGISTER_RSP);
int a = regno(regA);
int b = regno(regB);
int c = regno(regC);
uint8_t b1 = 0x02 | (a < 8? 0x40: 0x00) | (c < 8? 0x80: 0x00);
uint8_t b2 = 0x83 | (uint8_t)((~b) & 0xf) << 3;
uint8_t modrm = (0x00 << 6) | (((uint8_t)(c & 0x7)) << 3) | 0x04;
uint8_t sib = (0x03 << 6) | (((uint8_t)(a & 0x7)) << 3) | 0x05;
fprintf(stream, "%u,%u,%u,%u,%u,%u,{\"int32\":%d},", 0xc4, b1, b2, 0xf6,
modrm, sib, table);
}
/*
* Multiplication.
*/
static void emitMUL(FILE *stream, Register regA, Register regB, Register regC)
{
int a = regno(regA);
int b = regno(regB);
int c = regno(regC);
uint8_t b1 = 0x02 | (a < 8? 0x20: 0x00) | (c < 8? 0x80: 0x00);
uint8_t b2 = 0x83 | (uint8_t)((~b) & 0xf) << 3;
uint8_t modrm = (0x03 << 6) | (((uint8_t)(c & 0x7)) << 3) |
((uint8_t)(a & 0x7));
fprintf(stream, "%u,%u,%u,%u,%u,", 0xc4, b1, b2, 0xf6, modrm);
}
/*
* Bitwise negation of reg.
*/
static void emitNOT(FILE *stream, Register reg)
{
int r = regno(reg);
uint8_t rex = (r >= 8? 0x49: 0x48);
uint8_t modrm = 0xd0 | (uint8_t)(r & 0x7);
fprintf(stream, "%u,%u,%u,", rex, 0xf7, modrm);
}
/*
* Calculate (regC = offset + regA + regB) without affecting the flags.
*/
static void emitADD(FILE *stream, bool r64, int32_t offset, Register regA,
Register regB, Register regC)
{
int a = regno(regA);
int b = regno(regB);
int c = regno(regC);
uint8_t rex = 0x00;
if (r64 || a >= 8 || b >= 8 || c >= 8)
{
rex = 0x40;
if (r64)
rex |= 0x08;
if (c >= 8)
rex |= 0x04;
if (a >= 8)
rex |= 0x01;
if (b >= 8)
rex |= 0x02;
}
uint8_t mod = 0x00;
uint8_t rm = 0x04;
uint8_t r = (uint8_t)(c & 0x7);
if (offset != 0 && offset >= INT8_MIN && offset <= INT8_MAX)
mod = 0x01;
else
mod = 0x02;
if (mod == 0x00 && (regB == REGISTER_RBP || regB == REGISTER_R13))
mod = 0x01;
uint8_t modrm = (mod << 6) | (r << 3) | rm;
uint8_t scale = 0x00;
uint8_t idx = (uint8_t)(b & 0x7);
uint8_t base = (uint8_t)(a & 0x7);
uint8_t sib = (scale << 6) | (idx << 3) | base;
if (rex != 0x00)
fprintf(stream, "%u,", rex);
fprintf(stream, "%u,%u,%u,", /*LEA=*/0x8d, modrm, sib);
if (mod == 0x1)
fprintf(stream, "{\"int8\":%d},", (int32_t)offset);
else if (mod == 0x2)
fprintf(stream, "{\"int32\":%d},", (int32_t)offset);
}
/*
* Subtraction.
*/
static void emitSUB(FILE *stream, Register regA, Register regB)
{
int a = regno(regA);
int b = regno(regB);
uint8_t rex = 0x48 | (b >= 8? 0x04: 0x00) | (a >= 8? 0x01: 0x00);
uint8_t modrm = 0xc0 | (uint8_t)(b & 0x7) | ((uint8_t)(a & 0x7) << 3);
fprintf(stream, "%u,%u,%u,", rex, 0x29, modrm);
}
/*
* Calculate regB = regB + offset. We are allowed to affect the flags.
*/
static void emitADD(FILE *stream, bool r64, int32_t offset, Register regB)
{
if (offset == 0)
return;
bool sub = false;
if (offset < 0)
{
sub = true;
offset = -offset;
}
bool imm8 = false;
if (offset >= INT8_MIN && offset <= INT8_MAX)
imm8 = true;
int b = regno(regB);
uint8_t rex = (b >= 8? 0x41: 0x00);
rex |= (r64? 0x48: 0x00);
if (b == /*rax=*/0 && !imm8)
{
// Special handling for %eax:
if (rex != 0x00)
fprintf(stream, "%u,", rex);
fprintf(stream, "%u,{\"int32\":%d},", (sub? 0x2d: 0x05), offset);
return;
}
uint8_t opcode = (imm8? 0x83: 0x81);
uint8_t o = (sub? 0x05: 0x00);
uint8_t modrm = 0xc0 | (o << 3) | ((uint8_t)b & 0x7);
if (rex != 0x00)
fprintf(stream, "%u,", rex);
fprintf(stream, "%u,%u,", opcode, modrm);
if (imm8)
fprintf(stream, "{\"int8\":%d},", offset);
else
fprintf(stream, "{\"int32\":%d},", offset);
}
/*
* Emit a comparison with the memory location *regA and a register regB.
*/
static void emitDEREF_CMP(FILE *stream, Register regA, Register regB)
{
int a = regno(regA);
int b = regno(regB);
uint8_t rex = 0x48 | (a >= 8? 0x04: 0x00) | (b >= 8? 0x01: 0x00);
uint8_t modrm = 0x00 | (uint8_t)(a & 0x7) | ((uint8_t)(b & 0x7) << 3);
fprintf(stream, "%u,%u,%u,", rex, 0x3b, modrm);
}
/*
* Emit a comparison between two registers.
*/
static void emitCMP(FILE *stream, Register regA, Register regB)
{
int a = regno(regA);
int b = regno(regB);
uint8_t rex = 0x48 | (b >= 8? 0x04: 0x00) | (a >= 8? 0x01: 0x00);
uint8_t modrm = 0xc0 | (uint8_t)(a & 0x7) | ((uint8_t)(b & 0x7) << 3);
fprintf(stream, "%u,%u,%u,", rex, 0x3b, modrm);
}
/*
* Emit instructions to jump to PASS if (%rcx == 0)
*/
static void emitJMP_IF_PASS(FILE *stream, int check_no)
{
// If (%rcx == 0) then this is a non-fat pointer.
// jrcxz .Lpassed
if (!REDFAT_XPROFILE || !REDFAT_XSIZE)
{
fprintf(stream, "%u,{\"rel8\":\".Lpassed_%d\"},", 0xe3, check_no);
return;
}
// The target might be too far away for jrcxz...
fprintf(stream, "%u,{\"rel8\":\".Ltmp_%d\"},", 0xe3, check_no);
fprintf(stream, "%u,{\"rel8\":\".Lskip_%d\"},", 0xeb, check_no);
fprintf(stream, "\".Ltmp_%d\",%u,{\"rel32\":\".Lpassed_%d\"},",
check_no, 0xe9, check_no);
fprintf(stream, "\".Lskip_%d\",", check_no);
}
/*
* Emit an instruction to abort the execution.
*/
static void emitABORT(FILE *stream)
{
fprintf(stream, "%u,%u,", 0x0f, 0x0b); // ud2
}
/*************************************************************************/
/* CHECK */
/*************************************************************************/
/*
* Emits the trampoline that checks the given batch of instructions.
*/
static void emitCHECK(FILE *stream, const ELF *elf,
const std::vector<BatchEntry> &entries, const Adjusts &adjusts,
const RegSet &scratch, bool clobberFlags = false)
{
if (entries.size() == 0)
return;
bool save_scratch = false, save_rcx = !scratch.member(REGISTER_RCX),
save_rdx = !scratch.member(REGISTER_RDX);
const Register regs[] =
{REGISTER_RAX, REGISTER_RBX, REGISTER_RBP, REGISTER_RSI, REGISTER_RDI,
REGISTER_R8, REGISTER_R9, REGISTER_R10, REGISTER_R11, REGISTER_R12,
REGISTER_R13, REGISTER_R14, REGISTER_R15};
Register regScratch[2] = {REGISTER_INVALID, REGISTER_INVALID};
for (unsigned i = 0; i < sizeof(regs) / sizeof(regs[0]); i++)
{
if (scratch.member(regs[i]))
{
if (regScratch[0] == REGISTER_INVALID)
regScratch[0] = regs[i];
else
{
regScratch[1] = regs[i];
break;
}
}
}
if (REDFAT_XPROFILE)
{
Stats stats;
getStats(entries, &stats);
if (!clobberFlags)
{
emitSAVE(stream, 0x70, REGISTER_RAX);
fprintf(stream, "%u,%u,%u,", 0x0f, 0x90, 0xc0);
fprintf(stream, "%u,", 0x9f);
}
// lock add $size,PROFILE
if (stats.num_redzone_reads_unopt != 0)
fprintf(stream, "%u,%u,%u,%u,%u,{\"int32\":%d},{\"int8\":%d},",
0xf0, 0x48, 0x83, 0x04, 0x25,
REDFAT_PROFILE_VAR(REDFAT_PROFILE_REDZONE_READ_UNOPTIMIZED_CHECKS),
stats.num_redzone_reads_unopt);
if (stats.num_redzone_writes_unopt != 0)
fprintf(stream, "%u,%u,%u,%u,%u,{\"int32\":%d},{\"int8\":%d},",
0xf0, 0x48, 0x83, 0x04, 0x25,
REDFAT_PROFILE_VAR(REDFAT_PROFILE_REDZONE_WRITE_UNOPTIMIZED_CHECKS),
stats.num_redzone_writes_unopt);
if (stats.num_lowfat_reads_unopt != 0)
fprintf(stream, "%u,%u,%u,%u,%u,{\"int32\":%d},{\"int8\":%d},",
0xf0, 0x48, 0x83, 0x04, 0x25,
REDFAT_PROFILE_VAR(REDFAT_PROFILE_LOWFAT_READ_UNOPTIMIZED_CHECKS),
stats.num_lowfat_reads_unopt);
if (stats.num_lowfat_writes_unopt != 0)
fprintf(stream, "%u,%u,%u,%u,%u,{\"int32\":%d},{\"int8\":%d},",
0xf0, 0x48, 0x83, 0x04, 0x25,
REDFAT_PROFILE_VAR(REDFAT_PROFILE_LOWFAT_WRITE_UNOPTIMIZED_CHECKS),
stats.num_lowfat_writes_unopt);
if (stats.num_redzone_reads_opt != 0)
fprintf(stream, "%u,%u,%u,%u,%u,{\"int32\":%d},{\"int8\":%d},",
0xf0, 0x48, 0x83, 0x04, 0x25,
REDFAT_PROFILE_VAR(REDFAT_PROFILE_REDZONE_READ_OPTIMIZED_CHECKS),
stats.num_redzone_reads_opt);
if (stats.num_redzone_writes_opt != 0)
fprintf(stream, "%u,%u,%u,%u,%u,{\"int32\":%d},{\"int8\":%d},",
0xf0, 0x48, 0x83, 0x04, 0x25,
REDFAT_PROFILE_VAR(REDFAT_PROFILE_REDZONE_WRITE_OPTIMIZED_CHECKS),
stats.num_redzone_writes_opt);
if (stats.num_lowfat_reads_opt != 0)
fprintf(stream, "%u,%u,%u,%u,%u,{\"int32\":%d},{\"int8\":%d},",
0xf0, 0x48, 0x83, 0x04, 0x25,
REDFAT_PROFILE_VAR(REDFAT_PROFILE_LOWFAT_READ_OPTIMIZED_CHECKS),
stats.num_lowfat_reads_opt);
if (stats.num_lowfat_writes_opt != 0)
fprintf(stream, "%u,%u,%u,%u,%u,{\"int32\":%d},{\"int8\":%d},",
0xf0, 0x48, 0x83, 0x04, 0x25,
REDFAT_PROFILE_VAR(REDFAT_PROFILE_LOWFAT_WRITE_OPTIMIZED_CHECKS),
stats.num_lowfat_writes_opt);
if (!clobberFlags)
{
fprintf(stream, "%u,%u,", 0x04, 0x7f);
fprintf(stream, "%u,", 0x9e);
emitRESTORE(stream, 0x70, REGISTER_RAX);
}
}
if (regScratch[0] == REGISTER_INVALID)