This repository has been moved to another location; the currently maintained version is available at: https://github.com/LSC-Unicamp/riscv-isa-ci
CI/CD for RISC-V cores
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Software developed to test processors based on the RISC-V architecture. The software covers tests from the synthesis of the processor in HDL language (Verilog or VHDL) to the execution of instructions with the processor operating on an FPGA.
To run the software, the installation of some dependencies is required. Among them are:
- Litex: https://github.com/enjoy-digital/litex
- Requests: https://pypi.org/project/requests/
- GitPython: https://pypi.org/project/GitPython/0.3.2/
- OSS-Cad-Suite: https://github.com/YosysHQ/oss-cad-suite-build
- Toolchain for the board to be used: Gowin, Vivado, Quartus ...
To run the processors, at least one FPGA is required. Currently, the following FPGAs are supported:
- Tang nano 20k
- Tang nano 9k
- Lattice ECP5 45F
- Clone and Pull GIT repositories
- Synthesis of Core(s)/SoC(s)
- Standardization of pinouts for various FPGAs
- Verification of the synthesis process
- Writing to FPGA
- Serial debugger with FPGA
- Execution of instructions
- Automated sending of memory files to FPGA
In case of any questions, application bugs, or suggestions, use the issues menu on Github.
This repository is licensed under the GNU General Public License V3. Third-party libraries and software follow the licenses used by the original repositories.
- UART Module Implementation: https://github.com/ben-marshall/uart