This repository contains the Neural FPGA project.
Neural FPGA project goal is to produce custom hardware able to do inference over generic neural networks using only open source tools. In order to test our hardware designs we rely on hardware simulations and FPGAs.
Hardware simulation open source tools have been available since long time (see Verilator, Icarus Verilog), but open source tools to generate bitstreams for FPGAs were lacking until recent. Project IceStorm was the first complete tool to program a commercially available FPGA, the Lattice iCE40. Following, the project prjtrellis is documenting the bitstream format for the more capable Lattice ECP5. And others are comming.
On this project we won't focus on specific FPGAs, but because we would like to run our designs on real hardware we will try to fit our designs to available hardware with open source tools. This for the time being will be Ice40 and ECP5 from Lattice.
The main output of this project are cores that can do inference on generic neural networks trained with TensorFlow.
The project depends on several tools, check the requirements on each project to set up your dev environment:
- SpinalHDL for the hardware description language.
- VexRiscv used as softcore. Check details on how to install openOCD
- Verilator for the hardware simulations
- RISC-V GNU Embedded Toolchain to build the software targetted to riscv. YOu can build it yourself (https://github.com/riscv/riscv-gnu-toolchain) or get a pre-built one from https://www.sifive.com or https://github.com/gnu-mcu-eclipse/riscv-none-gcc/releases
- Tensorflow: To train and do inference.